Motorola Solutions 89FC5810 Non-Broadcast Transmitter User Manual Summit BR 800 Tx FCC Filing 3
Motorola Solutions, Inc. Non-Broadcast Transmitter Summit BR 800 Tx FCC Filing 3
Exhibit D Users Manual per 2 1033 c3
APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Operational or User’s Manual The manual should include instruction, installation, operator, or technical manuals with required ‘information to the users’. This manual should include a statement that cautions the user that changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. The manual shall include RF Hazard warning statements, if applicable. The instruction and service manual for this base radio are not published at this time. However, draft copy of some of the manual information has been assembled and has been included as part of this filing package. Upon request, published and/or printed manuals will be sent to the commission and/or telecommunication certification body (TCB) as soon as they become available. All of the descriptions, block diagrams, and schematics that are included in this filing package are current as of the package submittal date. EXHIBIT DESCRIPTION D1-1 Manual Front Matter (Draft) D1-2 Specifications (Draft) D1-3 Field Replaceable Units and Orderable Parts (Draft) D1-4 Tune-Up Procedure D1-5 Racking Configurations D1-6 Functional Description / Operation of Modules and Interconnect (Draft) EXHIBIT D APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Manual Front Matter (Draft) EXHIBIT D1-1 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Manual Front Matter (Draft, Continued) EXHIBIT D1-1 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Manual Front Matter (Draft, Continued) EXHIBIT D1-1 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Manual Front Matter (Draft, Continued) EXHIBIT D1-1 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Specifications (Draft) General Performance Model HxWxD Weight Power Requirements T7039 5.25" x 19" x 18" (133x483x457mm) 45 lbs (20 kg) AC: 90-264 VAC, 47-63 Hz DC: 43-60 VDC -22 to 140F (-30 to 60C) 50 ohms Temperature Range Input / Output Impedance Antenna Connectors Transmit: N female Receive: N female Modulation HPD Transmit / Receive: 64QAM, 16QAM, QPSK IV&D Transmit / Receive: C4FM, LSM Frequency Stability Channel Spacing External Reference HPD: 25 kHz C4FM / LSM: 12.5 kHz Transmitter Frequency Range Power output 851-870 MHz HPD: 2-50 Watts (Average) C4FM: 2-100 Watts LSM: 2-100 Watts (Average) Electronic Bandwidth Intermodulation Attenuation Spurious and Harmonic Emissions Attenuation Full Bandwidth 40 dB 85 dB FCC Type Acceptance FCC Designation: ABZ89FC5810 ABZ89FR5811 Frequency Range 851-869 MHz 806-824 MHz Type Transmitter, HPD Transmitter, C4FM/LSM Receiver Power Output Variable 2-50 W Variable 2-100 W N/A EXHIBIT D1-2 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Field Replaceable Units and Orderable Parts (Draft) Field replaceable units, or FRUs, include special packaging to allow shipment to customers. Parts and FRUs available for customer order are listed in this section. All parts and FRUs are sourced through the Radio Products and Service Division (RPSD). FRU # DLN6567A DLN6568A DLN6566A DLN6569A DLN6636A DLN1317A DLN6634A DLN1306A DLN1340A DLN1338A DLN1327A DLN1329A DLN1330A DLN1331A DLN1332A DLN1339A Description FRU: PA Mid Power 700 / 800 MHz FRU: AC / 48V DC Power Supply FRU: Transceiver 700 / 800 MHz FRU: Site Controller FRU: Expansion HUB External Dual Circulator 700 / 800 MHz FRU:700 / 800 MHz Site LNA FRU: 700 / 800 MHz Cabinet LNA FRU: Receive Multi-Coupler Tray FRU: Fan Module FRU: Power Supply Fan Module FRU: Site Controller Backplane FRU: Base Radio Backplane FRU: AC Junction Panel FRU: Expandable Site Subsystem Backplane FRU: AC Distribution PARENT ITEM NA NA NA NA Part Number TRN7663A TRN7755A TTN5049A TTN5103A X153 TTN5028A ### ### ### ### ### ### WEB NIR ### DLN1316A DLN1315A CLN1790A TKN8750A TKN9133A TLF7320A TLF7340A TLN3391A TRN7751A CLN1790A CLN1790A CLN1790A CLN1790A CLN1790A CLN1790A Description Power Cable, North America Power Cable, Continental Europe Power Cable, UK / Ireland Power Cable, Australia Cables All Other Rack Mount Hardware Fan Filler Panel FRU: Ps Filler Panel Diplexer, 700 / 800 MHz Transmit Post Filter 700 MHz Transmit Post Filter 800 MHz Phasing Harness FRU: Base Radio Preselector 700 / 800 MHz FRU: Site Preselector 700 / 800 MHz FRU: Duplexer, 700 MHz Duplexer, 800 MHz Dual Circulator Tray Cable Peripherals Cables Peripherals Tray Double Circulator Low Pass Filter Circulator Load Peripheral Shelf EXHIBIT D1-3 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Tune-Up Procedure There is no field tune-up procedure. All adjustments are software controlled and are pre-set at the factory. Certain station operating parameters can be changed via man-machine interface (MMI) commands, within predetermined limits. Examples include transmit / receiver operating frequencies and transmitter power level. EXHIBIT D1-4 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Racking Configurations There are various equipment racking configurations available to customers. The following section includes sketches which depict many of the racking alternatives. Configuration Layout PA #5 PA #4 PA #6 Bay #3 Bay #2 PA #3 PA #2 PA PA #1 Bay #1 PS XCVR XCVR #6 XCVR #5 PS #5 SC #2 XCVR #4 PS #4 ALARM XCVR #3 XCVR #2 XCVR #2 SC #1 XCVR #1 PS XCVR #1 Base Radio Fan Module #1 serves PA Bay #1 Fan Module #2 serves PA Bay #2 Fan Module #3 serves PA Bay #3 Fan Module #4 serves XCVR Bay #1 Fan Module #5 serves XCVR Bay #2 Fan Module #6 serves XCVR Bay #3 PS #6 PS #3 PS #2 PS #1 Receive Only Base Radio GTR 8000 Expandable Site Sub-system Layout EXHIBIT D1-5 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Control Module Overview The transceiver control circuitry performs the digital signal processing data formatting for the base radio (BR) and provides the external interfaces to the rest of the communication equipment present at the site. The Host Processor is the MPC8250 and the DSP is the MSC8101. General functionality includes: • Data and Control interface to the Receiver chip set devices • Data and Control interface to the Exciter chip set devices • Block Encoder / Decoder Interface • DSP interfaces • DSP / Host interface • Host bus size and speed • Host memory size, speed, and types supported • External ports (ethernet, RS232, etc.) • External physical interfaces (switches, connectors, etc.) Control Switches There is one switch on the Front Panel of the XCVR Control Module. The function of this multifunction switch can be seen in the table below. The switch is debounced in hardware for 100 ms for the “less than 1 second” case. When the switch is pressed for greater than 3 seconds a “PreReset” signal is sent to the Host processor via the CPLDs IRQ1x signal followed by the actual reset command 1 second later. Switch Switch1 Pressed for less than 1 second (See note) Switch1 Pressed for greater than 3 seconds Switch Functions Function (Application Specific) When this switch closure conditions are met, the Host CPLD/FPGA will generate an interrupt on IRQ2x XCVR Control Module Reset When these switch closure conditions are met the Host CPLD/FPGA will generate a Pre-reset signal to the MPC8250 via IRQ1x of the CPLD followed by a HRESET one second later. Note: This switch function can be SW controlled. The typical usage for this switch is Access Disable, which disables the power amplifier. EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Front Panel LEDs The number and color scheme of the LEDs is described in the following table. The Alarm LED (LED0) is placed closest to the outside edge of the front panel. The physical location of the other LEDs are placed in numerical order next to LED0. LED Color Normal LED Operation Status Condition Alarm Red Off Status Green Red Off LED7_g LED7_r Green Red LED6_g LED6_r Green Red LED5_g LED5_r Green Red LED4_g LED4_r Green Red LED3_g LED3_r Red Green LED2_g LED2_r Red Green Off Green Flashing Green Red Constant Amber Off Green Flashing Green Red Constant Amber Off Green Flashing Green Red Constant Amber Off Green Flashing Green Red Constant Amber Off Green Flashing Green Red Constant Amber Off Green Flashing Green Red Constant Amber See Service User Interface Spec document for more info. Same as above See Service User Interface Spec document for more info. No Power Spare Spare No Power No Power No Power No Power No Power EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) LED Color Status Condition LED1_g LED1_r Red Green No Power Ethernet Link1 Green Off Green Flashing Green Red Constant Amber Off On Off On Off On Off On Off No link established ON Link established (referenced to front view, connector tab at top, green LED will be on the left side of the connector) No Activity Amber Ethernet Link2 Green Amber Front Panel Ethernet (visual indication on connector) Green Yellow/ Amber Off On No link established Link established, No Activity Link activity No link established Link established, No Activity Link activity Link activity (referenced to front view, connector tab at top, green LED will be on the right side of the connector) Exciter Module Overview The exciter, in conjunction with the Power Amplifier or PA, provides the transmitter functions for the Base Radio. The exciter, which is a part of ‘transceiver’ RF board, consists of a baseband circuit block, a baseband modulator circuit block, a pre-amplifier circuit block, and a final amplifier circuit block. The transmitter Voltage Controlled Oscillator (VCO) and frequency synthesis circuitry blocks are also part of the exciter. Other functional blocks in the exciter include the various DC voltage regulators which drive the different circuits, the digital decoding circuitry block which interfaces the exciter circuits to the microprocessor in the control section, metering capability, and exciter to receiver loopback capability for diagnostic purposes. The exciter interconnects to the control module using an 84-pin flex cable connector. There are no user controls or indicators on the exciter. EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Power Amplifier Module Overview The power amplifier (PA) module is a forced convection cooled RF power amplifier that operates to the following electrical performance specifications: - RF Gain: 42 dB - Input Return Loss: 10 dB - Max Current Draw: 17.4 Amps - Rated Average Power Out: 100 Watt - Rated Peak Power Out: 200 Watt - Supply Voltage: 29 Volts DC - Operational Frequency Range: 746 MHz to 870 MHz The Power Amplifier is comprised of six internal modules. These are described briefly in the following paragraphs. 1. The Core Board provides the following functionality: - Routes DC to the Converter and Driver Boards - Routes RF to the Driver Board - Provides gain and FB power control - Provides for diagnostic sensors - Provides for intermediate voltages used by itself and other modules in the PA - Provides the PA’s digital interface to the rest of the Base Radio - Provides for cooling measures control - Provides for control of subordinate modules 2. The Power Converter Board provides the following functionality: - Provides 29 Volts DC and an intermediate voltage to the Distribution Board 3. The Driver Amplifier Board provides the following functionality: - Provides the first RF gain stage of the PA - Provides supporting bias circuits for the Driver Amplifier 4. The Final Amplifier Board provides the following functionality: - Provides the second RF gain stage of the PA (parallel stage) - Provides supporting bias circuits for the Final Amplifier - Provides for RF power splitting - Provides for RF power combining - Provides diagnostics EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) 5. The Distribution Board provides the following functionality: - Provides for RF routing from the Driver Amplifier to the Final Amplifier - Provides for RF routing from the Final Amplifier to the Output Module - Provides for DC power routing from the Core Board to the Output Module - Provides for DC power routing from the Power Converter Board to the Final Amplifier - Provides for Forward and Reverse Power routing from the Output Module to the Core Board - Provides for feedback power coupling to the Core Board - Routes module control from the Core Board to the Final Module - Routes diagnostics from the Final Module to the Core Board 6. The Output Module provides the following functionality: - Provides output isolation to the PA - Provides for harmonic attenuation - Provides for forward and reverse power detection Power Supply Module Overview The power supply module operates from either an AC or DC input and provides the DC operating voltages for the other Base Radio modules. These modules are sometimes also referred to as field replaceable units (FRU). When operating from an AC source (90 to 264 VAC, 47 to 63 Hz), the supply generates two DC output voltages of 28.94 Volts with reference to output ground. The power supply automatically adjusts to AC input ranges and supplies a steady output. In AC mode, the power supply contains a separate battery charger which can be used to maintain the charge on a 48 Volt DC nominal system, positive or negative ground (if installed). When operating from a DC source (43 VDC to 60 VDC, positive or negative ground), the supply generates two DC output voltages of 28.94 Volts with reference to output ground. The battery charger is not useable when operating from a DC input power source. When both AC and DC sources are available, the power supply operates from the AC source. When the AC source is lost, the power supply automatically shifts to DC operating mode. When the AC source is restored, the power supply automatically shifts to AC operating mode. The power supply contains several switching-type power supply circuits, power factor correction circuitry, battery charging circuitry, diagnostics and monitoring circuitry. The power supply module interconnects to the chassis backplane using a multi-pin power connector. Two Torx screws on the front panel of the power supply module secure it in the chassis. EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Power Supply Controls and Indicators The power supply module has three front panel light emitting diode (LED) indicators: 1) ALARM: a RED LED that when illuminated indicates the power supply is no longer operating within its design specifications 2) STATUS: a GREEN LED that when illuminated indicates the power supply is operating within its design specifications 3) FAN: a RED LED that when illuminated indicates the power supply fan is no longer functioning per its design specifications. The front panel ON/OFF switch is used to enable or disable the DC outputs of the power supply module. Power Supply Performance Specifications Operating Temperature: -30 to +60 °C Input Voltage: 90 to 264 Volts AC 43 to 60 Volts DC AC: DC: Input Frequency Range (AC operation): 47 to 63 Hz Input Current: 10 Amps Maximum 18A maximum AC: DC: Steady-State Output Voltage: Main DC Output: Aux DC Output: 28.94 Volts DC +/- 2.7% 28.94 Volts DC +/- 2.7% Total Output Power Rating: DC Outputs: Battery Charger: 600 Watts 150 Watts Battery Charger Output Voltage Range: 45 to 58 Volts DC Output Ripple: All outputs 50 mV p-p (measured with 20 MHz BW oscilloscope at 25°C) Short Circuit Current: 0.5 Amp average (maximum) Receiver Module Overview The Receiver, which supports three-branch diversity, provides the receiver functions for the Base Radio. The receiver is a part of the ‘transceiver’ RF board and consists of a front end low noise amplifier section, an on board pre-selector section, an IF filter section, and a baseband converter section. The receiver Voltage Controlled Oscillator (VCO) and frequency synthesis circuitry blocks are also part of the receiver section. A digital decoding section for interface to the control section microprocessor also exists as part of the receiver module. The receiver interconnects to the control module using an 84-pin flex cable connector. There are no user controls or indicators on the receiver. EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Additional Information – Control, Reference, Interconnect The Host The host microprocessor is a MPC8250A also known as the Power Quad Integrated Communications Controller II (PowerQUICC II). The MPC8250 features 64-bit data and 32-bit address busses providing up to 4 GBytes of address space. The MPC8250 is comprised of a variant of the PowerPC 603e core with Memory Management Units (MMUs), and a Communication Processor Module (CPM). The MPC8250 is in a 480-pin TBGA package to allow easier migration to other PowerQUICC processors. Control and Communications Features • • • • Microprocessor — 266 MHz PowerQuicc II Core — 66 MHz External Bus — 64-bit (only 32 used) wide 60x Compatible Data Bus, 4 GB Address Space — 32-bit wide Local Data Bus, 256 KB Address Space — Separate 16-Kbyte data and instruction caches — Three User Programmable Machines — SDRAM Controller — Virtual DMA for memory to memory and memory to I/O transfers — 166 MHz Communication Processor Module — COP/JTAG Test Access Port — Four General Purpose Timers — Bus Monitor — Software Watchdog Timer — Periodic Interval Timer — Flexible Interrupt Controller Main Memory — 32 Mbytes of SDRAM, one 32-bits wide bank — Option to place an additional 96 MB of SDRAM (for a total of 128 MB) — On board SDRAM components — 66/133 MHz Device with 9 ns (or faster) Cycle Time — No Parity Support Non-volatile Memory — 32 MB Compact Flash Memory Card (Application, 16 bit), which can be easily upgraded to larger densities — One 8/16 MB Flash device (Test app., Boot 0, parameter/data storage, 16 bit) — On board Flash components External Interfaces — Serial Peripheral Interface (SPI) Bus — One V.24 / RS-232 Serial Port: Synchronous (Front panel) — One RS-232 Serial Port, (TXD and RXD only): (Front panel) — One RS232 / Ethernet CST Port (Front panel) — Three internal 10/100BaseT Ethernet ports EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Serial Interfaces and I/O The following table shows the MPC8250’s communication port configuration for the control board. SCC1 will support a synchronous RS232 port. It will also support the same V.24 functionality. Port MPC8250 Communication Port Configuration Interface supported FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 MCC1 MCC2 I2C IDMA2 IDMA3 IDMA4 SPI 10/100BaseT Ethernet 10/100BaseT Ethernet 10/100BaseT Ethernet Sync. RS232 / V.24 Asynch RS232 Transparent RX-only for PSM Unused Unused Front panel RS232 Unused Unused I2C to 1-wire Bridge (to Dallas DS2433 EEPROM) IDMA2 (DSP) IDMA3 (DSP) IDMA4 (Compact Flash) SPI The control board has 64 MB of total SDRAM in the form of two 32 MB(16Mx16) devices. It supports a total of two separate Flash memory banks, one bank for boot and one for application code. It also supports a CompactFlash memory card. CompactFlash I/O cards are not supported. The Control board supports both Type I and Type II form factor cards. Reset Configuration The front panel has one switch. The switch provides two functions, Access Disable and Reset. The Front Panel switch is debounced for 16-32 ms. An Access Disable function will occur if the switch is pressed for less than 1 second but greater than the debounce time. A Reset sequence will occur if the switch is pressed for greater than 3 seconds. The reset sequence will consist of a Pre-Reset signal after 3 seconds followed by the actual reset 1 second later. The Pre-reset signal is used to notify the MPC8250 that an HRESET* is coming and to gracefully shutdown the processor before reset occurs. The DSP is an industrial temperature StarCore (SC140) based MSC8101. Production parts will operate at the highest core and CPM rates supported at the date of shipment. Initial devices have a maximum core frequency of 275 MHz but will run at 268.8 MHz with CPMs running about half that speed. Core voltages are 1.6 VDC and IO voltages are 3.3 VDC. On chip memory size is 512 KB. The package is a 332 pin FC-PBGA. See the following table for clock mode and frequency information. DSP Clock Information Clock Mode DSP Clock Input Core Clock CPM Clock System Bus Clock SCC Clock Clock Out BRG Clock 06 67.2 MHz 268.8 MHz 134.4 MHz 67.2 MHz 67.2 MHz 67.2 MHz 16.8 MHz default, configurable in SCCR Station Reference The station reference clock is 16.8 MHz. This clock is derived from a VCXO and in normal operation is locked to an external reference of 5 MHz, 10 MHz, 20 MHz, or 5 MHz / 1 PPS. The 5MHz_1PPs signal is a 5 MHz signal with an embedded 1 PPS clock. Typically the duty cycle of the clock is 25%. The duty cycle will change to 75% EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) for one period to indicate this is the 1 PPS mark. The external reference sources are the Ext_Ref input, the two CP2 links, and the OCXO which resides on the Supplemental Analog Card (SAC) (future development). The STIC FPGA will automatically or manually (based on the STIC’s memory mapped register configuration) determine what clock will be used as the reference. The same applies to the 1 PPS signals which come from a variety of sources. The 1 PPS sources are the CP2_A, CP2_B, Ext_Ref, and Ext_1PPS. A block diagram of the Station Reference Circuit can be seen in the Figure below. The 16.8 MHz and external reference clocks will be divided down to 200 kHz internally in the STIC. These resulting signals will be fed into an internal phase detector function block which will measure the phase difference between the two signals. If the rising edge of the 200 kHz clock sourced from 16.8 MHz occurs later than the rising edge of the 200 kHz clock sourced from the external reference, then the Phase_Det_U output of the FPGA will pulse high for the duration of the phase difference. The high pulse on the Phase_Det_U will result in the Charge Pump increasing its output voltage and increasing the VCXO frequency. The same scenario occurs if the 200 kHz clock sourced from 16.8 MHz occurs before the rising edge of the 200 kHz clock sourced from the external reference. In this case the output of the Phase_Det_D pulses high for the duration of the difference. This pulse will result in the Charge Pump decreasing the phase locked loop steering voltage and decreasing the VCXO frequency. The OCXO can be calibrated by applying a 5 or 10 MHz input signal (preferably a rubidium or equivalent) to the reference BNC on the front panel of the XCVR. The STIC will automatically generate an interrupt (if not masked in SW) to the DSP to indicate the presence of a valid 5 or 10 MHz input signal. The station reference will use this signal to lock the 16.8 MHz VCXO. When locked it will record the steering voltage required to create this lock condition by reading an ADC. Then the OCXO frequency reference will be used to lock the 16.8 MHz VCXO. The VCXO steering voltage required for lock will also be recorded using the same ADC. The two VCXO steering voltages will be compared. If the voltages are different, the OCXO steering voltage will be changed via the DAC. The OCXO steering voltage will be changed until its output frequency creates the same VCXO steering voltage as the VCXO steering voltage recorded when using the 5/10 MHz input reference. The OCXO DAC will reside on the SAC. Data for the OCXO DAC will be placed on the DSP TDM bus TX Slot #8 (Outbound from DSP, Inbound to SAC FGPA). The CST interface can be used to initiate the calibration process and indicate when the calibration is complete. It can also record and timestamp the calibration date(s) and indicate when another calibration is required. Station Reference Block Diagram The external references supported are the two 20 MHz clocks from the Site Controller, the external reference, and the OCXO from the SAC board (future development). The STIC will monitor all of these signals and determine which ones are not present or grossly out of tolerance. Each one of these fault conditions can be enabled to create an interrupt to the DSP. The reference clock status can be determined by reading the STIC’s IRQ register and/or the Clock Frequency Status registers. The FPGA can automatically determine which reference should use EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) and automatically select that reference. It also has the option of manually selecting the reference that should be used. The order or priority of the reference clocks are shown below. External Reference Clock Sources and Frequencies Supported Clock Frequencies Reference Source Clock Supported (clocks shown in accending order with highest priority clock first) CP2 Link1 CP2 Link2 External Reference OCXO Reference Front Panel 20 MHz 20 MHz 5 MHz, 10 MHz, 20 MHz, and 5 MHz / 1 PPS 10 MHz or 20 MHz 5 MHz or 10 MHz 1 PPS Sources The table below shows the possible 1 PPS sources and their priority levels. Each source can be manually or automatically selected based on the configuation of the STIC FPGA. While both CP2 links have an imbedded 1PPS signal, the Host CPLD will select which CP2 1 PPS signal gets sent to the FPGA. Thus there is only one CP2 1 PPS signal to the FPGA. 1PPS Sources and Frequencies Supported Reference Source Clock (clocks shown in accending order with highest priority clock first) CP2 Link (CP2A or CP2B) (aka Raw_1PPs) Ext_Ref (Demodulated 5MHz_1PPS) External 1PPS External Interfaces RS-232 Port This Async port is used to hook up to a dial up modem, MOSCAD, and as the zone link for a Trunking IR system. This port can also be configured for asyncronous operation. This port interfaces to SCC2 of the MPC8250. RJ-45 Pin # Async. RS-232 Port Signals RS-232 Signal Type RTS DSR/CD RxD Local_Failsoft* GND TxD DTR CTS Output Input Input Input GND Output Output Input Resource PD26 PC12 PD28 PA13 PD27 PC21 PC13 EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) V.24 Port This port can be used for either synchronous or asynchronous applications. This RJ45 connector and pinout is the same as used on previous product V.24 boards. This port can also be configured for asyncronous operation. This port interfaces to SCC1 of the MPC8250. Synchronous V.24 RJ-45 Telco Pin-out (on Xcvr) RJ-45 Pin V.24 Type Resource Signal RCLK RX Line Det. TCLK GND RX Data TX Data CTS RTS Input Input Input/Output GND Input Output Input Output PC20 PC14 PC29 PD31 PD30 PC15 PD29 External 1 PPS The external 1PPS connector currently resides on the Backplane. It is DC coupled, high impedance input, accepts 3.3V DC TTL level signals and is 5 Volt tolerant. External References There are two external references (Ext_Ref and 5MHz_In). The Ext_Ref signal resides on the Backplane. It accepts both 5 MHz, 5 MHz / 1 PPS, and 10 MHz references and is DC coupled. The second external reference (5MHz_In) is located on the front panel behind the fan assembly. It has a 50 ohm input resistance and is AC coupled. This input will be used to align the OCXO residing on the SAC. System Connector The System connector is a 50-pin Mini SCSI connector. It is used for all the Wildcard general purpose inputs and outputs. It also provides I/O for both MRTI Phone Patch and 6809 Trunking Controller configurations. Pin # Signal Aux In1 (Site Failsoft) Aux In2 (TX Inhibit) Aux In3 (Rx Inhibit) Aux In4 (Duplex Enable) Aux In5 (In Cabinet Repeat) Aux In6 Aux In7 Aux In8 Aux In 9 Opto+ (Ext_PTT) 10 Aux In 9 Opto(Ext_PTT) 11 12 13 14 15 16 17 Aux In 10 Opto+ Aux In 10 OptoAux In 11 Opto+ Aux In 11 OptoAux In 12 Opto+ Aux In 12 OptoAux Out1 (Failsoft Indicate) Wildcard Connector Type Function/Notes Input Input Input Input Input Customer-defined transistor buffered input (Note1) Customer-defined transistor buffered input (Note1) Customer-defined transistor buffered input (Note1) Customer-defined transistor buffered input (Note1) Customer-defined transistor buffered input (Note1) Input Input Input Aux In 9 Opto+ (Ext_PTT) Aux In 9 Opto(Ext_PTT) Input Input Input Input Input Input Output Customer-defined transistor buffered input Customer-defined transistor buffered input Customer-defined transistor buffered input Opto-isolated customer defined input (Opto A+) Opto-isolated customer defined input (Opto A-) Doubles as MRTI PTT and 6809 PTT Opto-isolated customer defined input Opto-isolated customer defined input Opto-isolated customer defined input Opto-isolated customer defined input Opto-isolated customer defined input Opto-isolated customer defined input Customer-defined transistor buffered output (Note1) EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Pin # Signal 18 19 20 21 22 23 Aux Out2 Aux Out3 Aux Out4 Aux Out5 Aux Out6 Aux Out Relay7 N.O.(RdStat) Aux Out Relay7 Com (RdStat) Aux Out Relay8 N.O. Aux Out Relay8 Com Aux Out Relay9 N.O. Aux Out Relay9 Com Aux Out Relay10 N.O. Aux Out Relay10 Com GND Aux Out11 Ext_Reset GND GND Mute Monitor In CCI / PL Strip In RxAudio RSTAT/Aux Indicate Out Detect TSTAT/RXCarrier Detect Tx Data+ TX Data -/GND MRTI TxAudio In Patch Inhibit Out GND GND PL+ PLGen TX+ GenTX- 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Type Output Output Output Output Output Function/Notes Customer-defined transistor buffered output Customer-defined transistor buffered output Customer-defined transistor buffered output Customer-defined transistor buffered output Customer-defined transistor buffered output N.O. contact of Relay A (Note1) COM contact of Relay A (Note1) N.O. contact of Relay A COM contact of Relay A N.O. contact of Relay A COM contact of Relay A N.O. contact of Relay A COM contact of Relay A Output Input Customer-defined transistor buffered output External Reset Input (to CPLD) Input Input Output Output 6809 Mute / MRTI Monitor Input 6809 CCI / MRTI PL Strip Input 6809/MRTI RX Audio output 6809 RSTAT / MRTI Aux Indicate output Output Input 6809 TDATA / MRTI RX Carrier output 6809 Tdata to AuxTX ADC Ground MRTI Transmit Audio (to PCM Codec) MRTI Patch Inhibit output Input Output Input Input Input Input Transceiver Power / Backplane Connector This connector provides the interconnect between the XCVR Control and XCVR RF (Exciter and Receiver) board which also incorporates the power supply. This connector consists of the two 10/100 BaseT Ethernet signals, SPI signals for the 28.6 VDC power supply and Power Amplifier, Fan Kit signals, and the CP2 TDM links. All of these signals go to the backplane. This connector also supplies the XCVR Control board with power from the power supply on the XCVR RF board. Pin # 10 11 12 13 Signal ETH_TX1+ GND ETH_TX1GND NC SPARE ETH_RX1+ GND ETH_RX1GND NC GND SPARE XCVR Power/Backplane Interconnect Type Function/Notes Output Primary Ethernet Link Output Primary Ethernet Link Input Primary Ethernet Link Input Primary Ethernet Link EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Pin # 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Signal GND NC GND PWR_ON_ SEQUENCE GND NC GND ETH_TX2+ GND ETH_TX2GND NC GND 12VDC 12VDC 12VDC 12VDC NC GND ETH_RX2+ GND ETH_RX2GND NC SPARE TDM_TX1+ GND TDM_TX1GND NC SPARE TDM_CLK1+ GND TDM_CLK1GND NC SPARE TDM_TX2+ GND TDM_TX2GND NC SPARE TDM_CLK2+ GND TDM_CLK2GND 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC 3.3VDC Wattmeter_Vf GND NC GND Type Function/Notes Input Provides 2V (Host Core) power up sequence control Output Redundant Ethernet Link Output Redundant Ethernet Link Output Redundant Ethernet Link Output Redundant Ethernet Link Input Primary TDM Link Input Primary TDM Link Input Primary TDM Link Input Primary TDM Link Input Redundant TDM Link Input Redundant TDM Link Input Redundant TDM Link Input Redundant TDM Link Input Wattmeter Forward Power voltage EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Pin # Signal 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 PSM_4.2MHz+ GND PSM_4.2MHzGND NC Fan_PWR_Status SPARE DIFF GND SPARE DIFF GND NC GND Wattmeter_Vr GND Fan Fail Lamp Test 88 89 90 91 GND NC GND TEMP 92 93 94 95 96 97 98 99 100 101 102 103 GND 5VDC 5VDC 5VDC 5VDC 5VDC 5VDC 5VDC 5VDC ANT_RLY_PDx GND ANT_RLY 104 105 106 107 GND FAN_FAIL GND FAN_POWER_ CNTL 108 109 110 111 112 113 114 115 116 117 FAN_DETECTx ALT_RESETx GND NC GND PA_SPI_CLK GND NC PA1_SPI_EN PA1_PRESENCE_D ETECT GND PA_ENABLEx GND NC HPB_IRQx HPB_SPI_EN GND NC 118 119 120 121 122 123 124 125 Type Function/Notes To PA for PSM To PA for PSM Pins 79 and 81 form diff pair spare Pins 79 and 81 form diff pair spare Input Wattmeter Reflected Power voltage Normally high, a logic low will illuminate the Fan Fail LED Temperature signal from Circulator. Goes to ADC1 channel 0 (first channel) A low indicates the antenna relay is present Output From PC30 on DSP. Needs to be defined. Voltage level, protection, default state etc. Input Multidrop signal? Output Controls fan power switch on XCVR RF board. Input Output Multidrop signal? (for PA and PS) Output Dedicated SPI_CLK for PA Output Input Pulled down by PA when PA is present Output Low activates PA(for P2 HW and beyond)) Input Output EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Pin # 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal Type Function/Notes HPB_PRESENCE_ DETECT HPB_SPI_CLK GND NC GND SPI_A0 GND NC SPI_A1 SPI_A2 GND SPI_A3 GND NC SPI_MOSI SPI_MISO GND NC GND PS1_SPI_EN GND NC PS1_FAULT Input Pulled down by HPB when HPB is present Output Dedicated SPI_CLK for HPB Output SPI, to PS&PA Output Output SPI, to PS&PA SPI, to PS&PA Output SPI, to PS&PA Output Input SPI SPI PS_PRESENCE_D ETECT GND PS_SPI_CLK GND NC BP_ID1 NC GND EXT_REF GND NC EXT_1PPS Input Indicates to XCVR Control board that the Power supply detected a fault condition and to write the condition to its EEPROM before it goes off-line. Pulled down by PS when PS is present Output Dedicated SPI_CLK for PS Input/Output BP_ID1 Output Input Input Input RF Board Receiver Interconnect The XCVR Control board interfaces to the RF board via a ribbon cable. The signals going to the RF board Receiver’s interface are shown in the following Table. Pin # Signal 10 11 Attn_Cntl_1_5 GND Attn_Cntl_1_4 GND Attn_Cntl_1_3 GND Attn_Cntl_1_2 GND Attn_Cntl_1_1 GND Rcvr3_CU_Cntl RF Board Receiver Interconnect Type Function/Notes Output To RCVR from FPGA GPIO1_5 Output To RCVR from FPGA GPIO1_4 Output To RCVR from FPGA GPIO1_3 Output To RCVR from FPGA GPIO1_2 Output To RCVR from FPGA GPIO1_1 Output switch control for RX power From Host EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Pin # Signal 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GND Abacus3 FS3 GND Abacus3 Data3 GND Abacus3 Clk3 GND Abacus3 FS2 GND Abacus3 Data2 GND Abacus3 Clk2 GND Abacus3 FS1 GND Abacus3 Data1 GND Abacus3 Clk1 GND Rcvr2_CU_Cntl 32 33 34 35 36 37 38 39 40 41 42 43 GND Attn_Cntl_2_5 GND Attn_Cntl_2_4 GND Attn_Cntl_2_3 GND Attn_Cntl_2_2 GND Attn_Cntl_2_1 GND Aba_SPI_En3 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 GND Aba_SPI_Data3 GND Aba_SPI_Clk3 GND Aba_SPI_En2 GND Aba_SPI_Data2 GND Aba_SPI_Clk2 GND Aba_ SPI_En1 GND Aba_ SPI_Data1 GND Aba_ SPI _Clk1 GND SPI CLK GND RCVR_SPI_EN GND SPI MOSI GND SPI MISO GND SPI Addr2 Type Function/Notes Input From Abacus3_3, to FPGA Input From Abacus3_3, to FPGA Input From Abacus3_3, to FPGA Input From Abacus3_2, to FPGA Input From Abacus3_2, to FPGA Input From Abacus3_2, to FPGA Input From Abacus3_1, to FPGA Input From Abacus3_1, to FPGA Input From Abacus3_1, to FPGA Output Switch control for RX power From Host Output To RCVR from FPGA GPIO2_5 Output To RCVR from FPGA GPIO2_4 Output To RCVR from FPGA GPIO2_3 Output To RCVR from FPGA GPIO2_2 Output To RCVR from FPGA GPIO2_1 Output Output SPI CLK From Host pin PD6 Output Input Output SPI Addr signal (MSB) for Abacus3s, Metering, tunable filters, and LV EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Pin # Signal Type Function/Notes Fract-N. See DSP SPI section for address decoding. 70 71 GND SPI Addr1 Output SPI Addr signal for Abacus3s, Metering, tunable filters, and LV Fract-N. See DSP SPI section for address decoding. 72 73 GND SPI Addr0 Output SPI Addr signal (LSB) for Abacus3s, Metering, tunable filters, and LV Fract-N. See DSP SPI section for address decoding. 74 75 76 77 78 79 80 81 82 83 84 GND Noise_Cntl_1 GND SYNCB GND GND GND 16.8MHz_ref GND GND GND Output To RCVR from FPGA GPIO2_0 Output Reset SSI data RF Board Exciter Interconnect The XCVR Control board interfaces to the RF board Exciter interface via a ribbon cable. The signals going to the RF board Exciter’s interface are shown in Table 8.9. Pin # Signal 10 11 Exciter_PWDN GND RXD GND RCLK GND RFS GND PSM_ACQ GND Exc_Tmhk_ Resetx GND Exc_Jav_Resetx 12 13 14 15 16 17 GND Spare GND Javelin TSLOT/Tx Enable 18 19 20 21 GND GND GND SCF_2X_CLK 22 23 24 GND SCF_CLK GND RF Board Exciter Interconnect Type Function/Notes Shuts off power to Exciter Receive data for PSM (to Host SCC3) Receive Clock for PSM (to Host SCC3) Frame Sync for PSM (to Host SCC3) Output Alt_Resetx AND’ed Exc_Tmhk_Resetx (From Host PC31) Alt_Resetx AND’ed Exc_Jav_Resetx (From Host PC27 ) Output Exciter, GPIO from MSC8101 (Pin PA23). Note PA22 reserved for TSLOTB if differential signaling is used From FPGA EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Pin # Signal Type 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DMCS GND Tomahawk FS GND Spare GND SSI Data GND GND GND SSI CLK GND GND GND Spare GND Spare GND Power Detector dynamic range control Cntl* GND GND GND SPI CLK GND Exciter_SPI_En GND SPI MOSI Output 44 45 46 47 48 49 50 51 Input Output Input Function/Notes Exciter, to Tomahawk Exciter, from Tomahawk Exciter, to Tomahawk Exciter, from Tomahawk Output from Host pin PA22. This signal is pulled down. Output Exciter , same signal to Rcvr Output From Host Output Exciter , same signal to Rcvr 52 53 54 55 56 57 GND SPI MISO GND Spare GND SPI_A3 Output SPI MSB Address signals for Tomahawk, Javelin, EEPROM, LV Fract-N, and Metering CSs. (See SPI section for address decoding.) 58 59 GND SPI_A2 Output SPI Address signals for Tomahawk, Javelin, EEPROM, LV Fract-N, and Metering CSs. (See SPI section for address decoding.) 60 61 GND SPI_A1 Output SPI Address signals for Tomahawk, Javelin, EEPROM, LV Fract-N, and Metering CSs. (See SPI section for address decoding.) 62 63 GND SPI_A0 Output SPI LSB Address signals for Tomahawk, Javelin, EEPROM, LV Fract-N, and Metering CSs. (See SPI section for address decoding.) 64 65 66 67 68 69 70 Input GND GND GND TX Forward Switch Cntl* GND Spare GND From Host Normally low. EXHIBIT D1-6 APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5810 User / Operational Manual Functional Description / Operation of Modules and Interconnect (Draft) Pin # 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Signal Type Function/Notes Input to FPGA SPI_ADC_MISO DSP_DC_NULL_ DOUT GND DSP_DC_NULL_ DIN GND DSP_DC_NULL_ CS GND DSP_DC_NULL_ CLK GND GND GND 16.8MHz_ref GND GND GND Output from FPGA SPI_ADC_MOSI Output from FPGA SPI_ADC_CS Output from FPGA SPI_ADC_CLK Output Exciter , Javelin Front Panel RS-232 / Ethernet (DB9) / RJ45 Interface The Front Panel CST port supports 2-wire RS-232 on a DB9 connector and 10/100BaseT Ethernet on a RJ45 connector. See tables below for connector pinout. Only the TXD and RXD signals are supported by the SMC, no other handshake signals are provided. Refer to the SMC section of the MPC8250 User’s Manual for features and programming information. The table below shows the signals supported along with the Host hardware resource responsible the RS232 signals. The front panel also supports a 10/100BaseT Ethernet port. The connector is configured and an MDI-X port that can be connected to a laptop using a standard cable. In essence, the transmit and receive signal pairs are reversed on the BRC front panel compared to that defined in IEEE Std. 802.3 Clause 14.5.1. The Ethernet PHY is a Broadcom BCM5221. Its address (4:0) is '00100'. Both the Front Panel Ethernet PHYand the CP2 PHY (BCM5222) communicate to the Host via the "bit -banged" GPIO MDC and MDIO signals. Front Panel Port Signals RJ45 Pin # RS-232 Signal RD+ (Ethernet) RD- (Ethernet) TD+ (Ethernet) NC NC TD- (Ethernet) NC NC Front Panel RS232 Cable Adapter RJ45 Pin # RS232 DB9 / Female NC TXD (RS232) (Host PA9) RXD (RS232) (Host PA8) NC GND Ext_Trigger_In (DSP IRQ1) NC GND Ext_Trigger_Out (DSP PA20) EXHIBIT D1-6
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