Motorola MC68HC908MR32 MC68HC908MR32/D User Manual To The Ec3225a3 5555 4d7c B029 Fd7e7043b557

User Manual: Motorola MC68HC908MR32 to the manual

Open the PDF directly: View PDF PDF.
Page Count: 388 [warning: Documents this large are best viewed by clicking the View PDF Link!]

MC68HC908MR32/D
REV 4
M
6
8H
C
08M
6
0
8M68HC08
M
8
HC08M68H
C
MC68HC908MR32
MC68HC908MR16
Advance Information
HCMOS
Microcontroller Unit
blank
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA 3
MC68HC908MR32
MC68HC908MR16
Technical Summary
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer's technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2001
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
4MOTOROLA
Revision History
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.motorola.com/semiconductors/
The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Revision History
Date Revision
Level Description Page
Number(s)
August, 2001 3
Figure 2-1. Memory Map — Added FLASH Block Protect
Register (FLBPR) at address location $FF7E 41
Figure A-1. MC68HC908MR16 Memory Map — Added FLASH
Block Protect Register (FLBPR) at address location $FF7E 386
October, 2001 4 19.4.3 Conversion Time — Reworked equations and text for
clarity. 344
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA List of Sections 5
Advance Information — MC68HC908MR16/MC68HC908MR32
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .29
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .39
Section 3. Random-Access Memory (RAM) . . . . . . . . . .55
Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . .57
Section 5. Configuration Register (CONFIG) . . . . . . . . .67
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . .71
Section 7. System Integration Module (SIM) . . . . . . . . .89
Section 8. Clock Generator Module (CGM). . . . . . . . . .109
Section 9. Pulse-Width Modulator
for Motor Control (PWMMC) . . . . . . . . . .135
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .185
Section 11. Timer Interface A (TIMA). . . . . . . . . . . . . . .199
Section 12. Timer Interface B (TIMB). . . . . . . . . . . . . . .225
Section 13. Serial Peripheral Interface
Module (SPI) . . . . . . . . . . . . . . . . . . . . . . .247
Section 14. Serial Communications Interface
Module (SCI) . . . . . . . . . . . . . . . . . . . . . . .277
Section 15. Input/Output (I/O) Ports . . . . . . . . . . . . . . .307
Section 16. Computer Operating Properly (COP) . . . .323
Section 17. External Interrupt (IRQ) . . . . . . . . . . . . . . .329
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
6 List of Sections MOTOROLA
List of Sections
Section 18. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . .335
Section 19. Analog-to-Digital Converter (ADC) . . . . . .341
Section 20. Power-On Reset (POR) . . . . . . . . . . . . . . . .357
Section 21. Break Module (BRK) . . . . . . . . . . . . . . . . . .359
Section 22. Electrical Specifications. . . . . . . . . . . . . . .367
Section 23. Mechanical Specifications . . . . . . . . . . . . .379
Section 24. Ordering Information . . . . . . . . . . . . . . . . .383
Appendix A. MC68HC908MR16 . . . . . . . . . . . . . . . . . . .385
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Table of Contents 7
Advance Information — MC68HC908MR16/MC68HC908MR32
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
1.5.1 Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . .35
1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .35
1.5.3 External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .35
1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .36
1.5.5 CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . .36
1.5.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .36
1.5.7 Analog Power Supply Pins (VDDA and VSSA). . . . . . . . . . . .36
1.5.8 ADC Voltage Decoupling Capacitor Pin (VREFH) . . . . . . . . .36
1.5.9 ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . .36
1.5.10 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . .37
1.5.11 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . .37
1.5.12 Port C I/O Pins (PTC6–PTC2
and PTC1/ATD9–PTC0/ATD8) . . . . . . . . . . . . . . . . . . . .37
1.5.13 Port D Input-Only Pins (PTD6/IS3–PTD4/IS1
and PTD3/FAULT4–PTD0/FAULT1). . . . . . . . . . . . . . . .37
1.5.14 PWM Pins (PWM6–PWM1) . . . . . . . . . . . . . . . . . . . . . . . . .37
1.5.15 PWM Ground Pin (PWMGND) . . . . . . . . . . . . . . . . . . . . . . .38
1.5.16 Port E I/O Pins (PTE7/TCH3A–PTE3/TCLKA
and PTE2/TCH1B–PTE0/TCLKB). . . . . . . . . . . . . . . . . .38
1.5.17 Port F I/O Pins (PTF5/TxD–PTF4/RxD
and PTF3/MISO–PTF0/SPSCK) . . . . . . . . . . . . . . . . . . .38
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
8 Table of Contents MOTOROLA
Table of Contents
Section 2. Memory Map
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .39
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.5 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Section 3. Random-Access Memory (RAM)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Section 4. FLASH Memory
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .60
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .61
4.7 FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . . . .62
4.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . .65
4.10 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.11 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Section 5. Configuration Register (CONFIG)
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table of Contents
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Table of Contents 9
Section 6. Central Processor Unit (CPU)
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Section 7. System Integration Module (SIM)
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .92
7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . .93
7.3.3 Clocks in Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .93
7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .95
7.4.2.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . .97
7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.4.2.5 Forced Monitor Mode Entry Reset (MENRST). . . . . . . . .98
7.4.2.6 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . .98
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
10 Table of Contents MOTOROLA
Table of Contents
7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .98
7.5.2 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .98
7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
7.6.1.2 Software Interrupt (SWI) Instruction. . . . . . . . . . . . . . . .102
7.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.7 Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
7.8.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .104
7.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .106
7.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .107
Section 8. Clock Generator Module (CGM)
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.4.1 Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .113
8.4.2.1 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . .115
8.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . . .115
8.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . .117
8.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . . .119
8.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . .119
8.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . .119
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .121
8.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .121
8.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . .121
8.5.4 PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . .122
8.5.5 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .122
Table of Contents
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Table of Contents 11
8.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .122
8.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . .122
8.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .122
8.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .126
8.6.3 PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . .128
8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
8.8 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .130
8.9.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .130
8.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .132
8.9.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . .133
8.9.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . .133
Section 9. Pulse-Width Modulator for Motor Control
(PWMMC)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.4 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.4.1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.4.2 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
9.5 PWM Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
9.5.1 Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
9.5.2 PWM Data Overflow and Underflow Conditions. . . . . . . . .147
9.6 Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
9.6.1 Selecting Six Independent PWMs
or Three Complementary PWM Pairs . . . . . . . . . . . . . .147
9.6.2 Dead-Time Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9.6.3 Top/Bottom Correction with Motor Phase
Current Polarity Sensing . . . . . . . . . . . . . . . . . . . . . . . .153
9.6.4 Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
9.6.5 PWM Output Port Control. . . . . . . . . . . . . . . . . . . . . . . . . .158
9.7 Fault Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
12 Table of Contents MOTOROLA
Table of Contents
9.7.1 Fault Condition Input Pins . . . . . . . . . . . . . . . . . . . . . . . . .161
9.7.1.1 Fault Pin Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
9.7.1.2 Automatic Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
9.7.1.3 Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
9.7.2 Software Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . .165
9.7.3 Output Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
9.8 Initialization and the PWMEN Bit . . . . . . . . . . . . . . . . . . . . . .166
9.9 PWM Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . .168
9.10 Control Logic Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
9.10.1 PWM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .168
9.10.2 PWM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . .169
9.10.3 PWMx Value Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .170
9.10.4 PWM Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . .171
9.10.5 PWM Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . .173
9.10.6 Dead-Time Write-Once Register . . . . . . . . . . . . . . . . . . . .176
9.10.7 PWM Disable Mapping Write-Once Register . . . . . . . . . . .176
9.10.8 Fault Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
9.10.9 Fault Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
9.10.10 Fault Acknowledge Register. . . . . . . . . . . . . . . . . . . . . . . .180
9.10.11 PWM Output Control Register . . . . . . . . . . . . . . . . . . . . . .182
9.11 PWM Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Section 10. Monitor ROM (MON)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
10.4.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .188
10.4.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . .188
10.4.1.2 Forced Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .190
10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
10.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
10.4.4 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
10.4.5 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
10.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Table of Contents
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Table of Contents 13
Section 11. Timer Interface A (TIMA)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
11.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .204
11.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
11.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
11.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .206
11.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .207
11.4.4 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .208
11.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .209
11.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .210
11.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
11.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
11.7.1 TIMA Clock Pin (PTE3/TCLKA) . . . . . . . . . . . . . . . . . . . . .213
11.7.2 TIMA Channel I/O Pins
(PTE4/TCH0A–PTE7/TCH3A) . . . . . . . . . . . . . . . . . . .213
11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
11.8.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . . .214
11.8.2 TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .216
11.8.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . .217
11.8.4 TIMA Channel Status and Control Registers . . . . . . . . . . .217
11.8.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .222
Section 12. Timer Interface B (TIMB)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
12.4.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .227
12.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
14 Table of Contents MOTOROLA
Table of Contents
12.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
12.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .230
12.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .231
12.4.4 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .232
12.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .233
12.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .234
12.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
12.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
12.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
12.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
12.7.1 TIMB Clock Pin (PTD4/ATD12) . . . . . . . . . . . . . . . . . . . . .237
12.7.2 TIMB Channel I/O Pins
(PTE1/TCH0B–PTE2/TCH1B) . . . . . . . . . . . . . . . . . . .237
12.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
12.8.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . . . .238
12.8.2 TIMB Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .240
12.8.3 TIMB Counter Modulo Registers . . . . . . . . . . . . . . . . . . . .241
12.8.4 TIMB Channel Status and Control Registers . . . . . . . . . . .242
12.8.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .245
Section 13. Serial Peripheral Interface
Module (SPI)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
13.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
13.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
13.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
13.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
13.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
13.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .253
13.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .253
13.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .255
13.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .256
Table of Contents
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Table of Contents 15
13.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
13.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
13.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
13.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
13.9 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
13.10 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .264
13.11 Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
13.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
13.12.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .267
13.12.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .267
13.12.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
13.12.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
13.12.5 VSS (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
13.13 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
13.13.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
13.13.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .272
13.13.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
Section 14. Serial Communications Interface
Module (SCI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
14.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
14.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
14.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
14.4.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .281
14.4.2.3 Break Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
14.4.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
14.4.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .284
14.4.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.4.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .286
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
16 Table of Contents MOTOROLA
Table of Contents
14.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
14.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
14.4.3.5 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
14.4.3.6 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
14.4.3.7 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
14.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
14.6 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .291
14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
14.7.1 PTF5/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . .291
14.7.2 PTF4/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . .292
14.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
14.8.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .292
14.8.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .295
14.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .298
14.8.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
14.8.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
14.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
14.8.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .304
Section 15. Input/Output (I/O) Ports
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
15.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
15.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .310
15.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
15.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
15.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . .312
15.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
15.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
15.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .314
15.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
15.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
15.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
15.7.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .318
Table of Contents
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Table of Contents 17
15.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
15.8.1 Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
15.8.2 Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . .320
Section 16. Computer Operating Properly (COP)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
16.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.4.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
16.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
16.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
16.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
16.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
16.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
16.8 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
16.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
Section 17. External Interrupt (IRQ)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
17.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
17.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .334
Section 18. Low-Voltage Inhibit (LVI)
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
18 Table of Contents MOTOROLA
Table of Contents
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
18.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
18.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .337
18.4.3 False Reset Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . .337
18.4.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
18.5 LVI Status and Control Register. . . . . . . . . . . . . . . . . . . . . . .338
18.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
18.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
18.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
Section 19. Analog-to-Digital Converter (ADC)
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
19.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
19.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
19.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
19.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .345
19.4.5 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
19.4.6 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
19.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
19.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
19.7.1 ADC Analog Power Pin (VDDAD) . . . . . . . . . . . . . . . . . . . .347
19.7.2 ADC Analog Ground Pin (VSSAD). . . . . . . . . . . . . . . . . . . .347
19.7.3 ADC Voltage Reference Pin (VREFH) . . . . . . . . . . . . . . . . .347
19.7.4 ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . .348
19.7.5 ADC Voltage In (ADVIN) . . . . . . . . . . . . . . . . . . . . . . . . . .348
19.7.6 ADC External Connections. . . . . . . . . . . . . . . . . . . . . . . . .348
19.7.6.1 VREFH and VREFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
19.7.6.2 ANx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
19.7.6.3 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
Table of Contents
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Table of Contents 19
19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
19.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .349
19.8.2 ADC Data Register High . . . . . . . . . . . . . . . . . . . . . . . . . .352
19.8.3 ADC Data Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . .353
19.8.4 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
Section 20. Power-On Reset (POR)
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
Section 21. Break Module (BRK)
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360
21.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .362
21.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .362
21.4.3 TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . .362
21.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .362
21.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
21.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
21.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
21.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
21.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .363
21.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .364
21.6.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
21.6.4 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . .366
Section 22. Electrical Specifications
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
22.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .368
22.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .369
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
20 Table of Contents MOTOROLA
Table of Contents
22.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
22.6 DC Electrical Characteristics (VDD = 5.0 Vdc ± 10%). . . . . . .370
22.7 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .371
22.8 Control Timing (VDD = 5.0 Vdc ± 10%) . . . . . . . . . . . . . . . . .372
22.9 Serial Peripheral Interface Characteristics
(VDD = 5.0 Vdc ± 10%). . . . . . . . . . . . . . . . . . . . . . . . . . . .373
22.10 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . .376
22.11 Clock Generation Module Component Specifications . . . . . .376
22.12 CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .376
22.13 CGM Acquisition/Lock Time Specifications . . . . . . . . . . . .377
22.14 Analog-to-Digital Converter (ADC) Characteristics. . . . . . . . .378
Section 23. Mechanical Specifications
23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
23.3 64-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . .380
23.4 56-Pin Shrink Dual In-Line Package (SDIP). . . . . . . . . . . . . .381
Section 24. Ordering Information
24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
24.3 Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
Appendix A. MC68HC908MR16
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
A.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA List of Figures 21
Advance Information — MC68HC908MR16/MC68HC908MR32
List of Figures
Figure Title Page
1-1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1-2 64-Pin QFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . .33
1-3 56-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .34
1-4 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2-1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2-2 Control, Status, and Data Registers Summary . . . . . . . . . .42
4-1 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . .59
4-2 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . .63
4-4 FLASH Block Protect Start Address. . . . . . . . . . . . . . . . . . .65
4-3 FLASH Block Protect Register (FLBPR) . . . . . . . . . . . . . . .65
5-1 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . .68
6-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6-3 Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .75
7-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
7-2 CGM Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7-3 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7-4 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . .95
7-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7-6 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7-7 Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7-8 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7-9 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
22 List of Figures MOTOROLA
List of Figures
Figure Title Page
7-10 Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . .101
7-11 Wait Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .103
7-12 Wait Recovery from Interrupt . . . . . . . . . . . . . . . . . . . . . . .103
7-13 Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . .103
7-14 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . .104
7-15 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . .106
7-16 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .107
8-1 CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8-2 CGM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .113
8-3 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . .120
8-4 CGM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .123
8-5 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . .124
8-6 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . .126
8-7 PLL Programming Register (PPG). . . . . . . . . . . . . . . . . . .128
9-1 PWM Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . .137
9-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9-3 Center-Aligned PWM (Positive Polarity). . . . . . . . . . . . . . .141
9-4 Edge-Aligned PWM (Positive Polarity). . . . . . . . . . . . . . . .142
9-5 Reload Frequency Change . . . . . . . . . . . . . . . . . . . . . . . .144
9-6 PWM Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . .144
9-7 Center-Aligned PWM Value Loading . . . . . . . . . . . . . . . . .145
9-8 Center-Aligned Loading of Modulus. . . . . . . . . . . . . . . . . .145
9-9 Edge-Aligned PWM Value Loading . . . . . . . . . . . . . . . . . .146
9-10 Edge-Aligned Modulus Loading . . . . . . . . . . . . . . . . . . . . .146
9-11 Complementary Pairing . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9-12 Typical AC Motor Drive . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9-13 Dead-Time Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9-14 Effects of Dead-Time Insertion. . . . . . . . . . . . . . . . . . . . . .151
9-15 Dead-Time at Duty Cycle Boundaries . . . . . . . . . . . . . . . .152
9-16 Dead-Time and Small Pulse Widths. . . . . . . . . . . . . . . . . .152
9-17 Ideal Complementary Operation (Dead-Time = 0) . . . . . . .154
9-18 Current Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
9-19 Top/Bottom Correction for PWMs 1 and 2 . . . . . . . . . . . . .156
9-20 PWM Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
9-21 PWM Output Control Register (PWMOUT) . . . . . . . . . . . .158
9-22 Dead-Time Insertion During OUTCTL = 1 . . . . . . . . . . . . .159
List of Figures
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA List of Figures 23
Figure Title Page
9-23 Dead-Time Insertion During OUTCTL = 1 . . . . . . . . . . . . .160
9-24 PWM Disable Mapping Write-Once
Register (DISMAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
9-25 PWM Disabling Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . .162
9-26 PWM Disabling Decode Scheme . . . . . . . . . . . . . . . . . . . .163
9-27 PWM Disabling in Automatic Mode . . . . . . . . . . . . . . . . . .163
9-28 PWM Disabling in Manual Mode (Example 1) . . . . . . . . . .165
9-29 PWM Disabling in Manual Mode (Example 2) . . . . . . . . . .165
9-30 PWM Software Disable . . . . . . . . . . . . . . . . . . . . . . . . . . .166
9-31 PWMEN and PWM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . .167
9-32 PWM Counter Register High (PCNTH) . . . . . . . . . . . . . . .168
9-33 PWM Counter Register Low (PCNTL) . . . . . . . . . . . . . . . .168
9-34 PWM Counter Modulo Register High (PMODH) . . . . . . . .169
9-35 PWM Counter Modulo Register Low (PMODL) . . . . . . . . .169
9-36 PWMx Value Registers High (PVALxH) . . . . . . . . . . . . . . .170
9-37 PWMx Value Registers Low (PVALxL) . . . . . . . . . . . . . . .170
9-38 PWM Control Register 1 (PCTL1) . . . . . . . . . . . . . . . . . . .171
9-39 PWM Control Register 2 (PCTL2) . . . . . . . . . . . . . . . . . . .174
9-40 Dead-Time Write-Once Register (DEADTM) . . . . . . . . . . .176
9-41 PWM Disable Mapping
Write-Once Register (DISMAP). . . . . . . . . . . . . . . . . . .176
9-42 Fault Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . .177
9-43 Fault Status Register (FSR) . . . . . . . . . . . . . . . . . . . . . . . .179
9-44 Fault Acknowledge Register (FTACK) . . . . . . . . . . . . . . . .180
9-45 PWM Output Control Register (PWMOUT) . . . . . . . . . . . .182
9-46 PWM Clock Cycle and PWM Cycle Definitions . . . . . . . . .184
9-47 PWM Load Cycle/Frequency Definition . . . . . . . . . . . . . . .184
10-1 Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
10-2 Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
10-3 Sample Monitor Waveforms. . . . . . . . . . . . . . . . . . . . . . . .191
10-4 Read Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
10-5 Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
10-6 Monitor Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . .197
11-1 TIMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
11-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .202
11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .208
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
24 List of Figures MOTOROLA
List of Figures
Figure Title Page
11-4 TIMA Status and Control Register (TASC). . . . . . . . . . . . .214
11-5 TIMA Counter Registers (TACNTH and TACNTL). . . . . . .216
11-6 TIMA Counter Modulo Registers
(TAMODH and TAMODL) . . . . . . . . . . . . . . . . . . . . . . .217
11-7 TIMA Channel Status and Control Registers
(TASC0–TASC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
11-8 CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
11-9 TIMA Channel Registers
(TACH0H/L–TACH3H/L) . . . . . . . . . . . . . . . . . . . . . . . .222
12-1 TIMB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
12-2 TIMB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .228
12-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .232
12-4 TIMB Status and Control Register (TBSC). . . . . . . . . . . . .238
12-5 TIMB Counter Registers (TBCNTH and TBCNTL). . . . . . .240
12-6 TIMB Counter Modulo Registers
(TBMODH and TBMODL) . . . . . . . . . . . . . . . . . . . . . . .241
12-7 TIMB Channel Status and Control Registers
(TBSC0–TBSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
12-8 CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
12-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . .246
13-1 SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .250
13-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . .251
13-2 SPI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .251
13-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . .254
13-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
13-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . .255
13-7 Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . .257
13-8 Missed Read of Overflow Condition. . . . . . . . . . . . . . . . . .259
13-9 Clearing SPRF When OVRF Interrupt
Is Not Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
13-10 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . .263
13-11 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . .265
13-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
13-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .270
13-14 SPI Status and Control Register (SPSCR). . . . . . . . . . . . .272
13-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .275
List of Figures
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA List of Figures 25
Figure Title Page
14-1 SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .279
14-2 SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .280
14-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
14-4 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
14-5 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .285
14-6 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .286
14-7 SCI Control Register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . .293
14-8 SCI Control Register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . .296
14-9 SCI Control Register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . .298
14-10 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . .300
14-11 Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .302
14-12 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . .303
14-13 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . .304
14-14 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . .304
15-1 I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . .308
15-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .310
15-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .310
15-4 Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
15-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .312
15-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .312
15-7 Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
15-8 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .314
15-9 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . .314
15-10 Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
15-12 Port D Input Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
15-11 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .316
15-13 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . .317
15-14 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . .318
15-15 Port E I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
15-16 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . .319
15-17 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . .320
15-18 Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
16-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
16-2 COP I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . .324
16-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . .326
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
26 List of Figures MOTOROLA
List of Figures
Figure Title Page
17-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .330
17-2 IRQ I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .330
17-3 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .332
17-4 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . .334
18-1 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .336
18-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .337
18-3 LVI Status and Control Register (LVISCR) . . . . . . . . . . . .338
19-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
19-2 8-Bit Truncation Mode Error. . . . . . . . . . . . . . . . . . . . . . . .346
19-3 ADC Status and Control Register (ADSCR). . . . . . . . . . . .349
19-4 ADC Data Register High (ADRH)
Left Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
19-5 ADC Data Register High (ADRH)
Right Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .352
19-6 ADC Data Register Low (ADRL)
Left Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
19-7 ADC Data Register Low (ADRL)
Right Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .353
19-8 ADC Data Register Low (ADRL) 8-Bit Mode . . . . . . . . . . .354
19-9 ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . .354
21-1 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . .361
21-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
21-3 Break Status and Control Register (BRKSCR) . . . . . . . . .363
21-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . .364
21-5 Break Address Register Low (BRKL). . . . . . . . . . . . . . . . .364
21-6 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . .365
21-7 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .366
22-1 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
22-2 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
23-1 MC68HC908MR32FU . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
23-2 MC68HC908MR32B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
A-1 MC68HC908MR16 Memory Map. . . . . . . . . . . . . . . . . . . .386
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA List of Tables 27
Advance Information — MC68HC908MR16/MC68HC908MR32
List of Tables
Table Title Page
2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4-1 Examples of Protect Start Address. . . . . . . . . . . . . . . . . . . . .66
6-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6-2 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8-1 Variable Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
8-2 VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . .128
9-1 PWM Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
9-2 PWM Reload Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .144
9-3 PWM Data Overflow and Underflow Conditions. . . . . . . . . .147
9-4 Current Sense Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
9-5 Correction Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
9-6 OUTx Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
9-7 Correction Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
9-8 PWM Reload Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .174
9-9 PWM Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
9-10 OUTx Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
10-1 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
10-2 Monitor Mode Signal Requirements and Options. . . . . . . . .189
10-3 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . .193
10-4 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . .193
10-5 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . .194
10-6 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . .194
10-7 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . .195
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
28 List of Tables MOTOROLA
List of Tables
Table Title Page
10-8 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . .195
10-9 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . .196
11-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
11-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . .220
12-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
12-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . .244
13-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
13-2 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
13-3 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
13-4 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . .274
14-1 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
14-2 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
14-3 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
14-4 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . .295
14-5 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . .305
14-6 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .305
14-7 SCI Baud Rate Selection Examples. . . . . . . . . . . . . . . . . . .306
15-1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
15-2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
15-3 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
15-4 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
15-5 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
15-6 Port F Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
18-1 LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
19-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
19-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
24-1 Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA General Description 29
Advance Information — MC68HC908MR16/MC68HC908MR32
Section 1. General Description
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
1.5.1 Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . .35
1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .35
1.5.3 External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .35
1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .36
1.5.5 CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . .36
1.5.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .36
1.5.7 Analog Power Supply Pins (VDDA and VSSA). . . . . . . . . . . .36
1.5.8 ADC Voltage Decoupling Capacitor Pin (VREFH) . . . . . . . . .36
1.5.9 ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . .36
1.5.10 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . .37
1.5.11 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . .37
1.5.12 Port C I/O Pins (PTC6–PTC2
and PTC1/ATD9–PTC0/ATD8) . . . . . . . . . . . . . . . . . . . .37
1.5.13 Port D Input-Only Pins (PTD6/IS3–PTD4/IS1
and PTD3/FAULT4–PTD0/FAULT1). . . . . . . . . . . . . . . .37
1.5.14 PWM Pins (PWM6–PWM1) . . . . . . . . . . . . . . . . . . . . . . . . .37
1.5.15 PWM Ground Pin (PWMGND) . . . . . . . . . . . . . . . . . . . . . . .38
1.5.16 Port E I/O Pins (PTE7/TCH3A–PTE3/TCLKA
and PTE2/TCH1B–PTE0/TCLKB). . . . . . . . . . . . . . . . . .38
1.5.17 Port F I/O Pins (PTF5/TxD–PTF4/RxD
and PTF3/MISO–PTF0/SPSCK) . . . . . . . . . . . . . . . . . . .38
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
30 General Description MOTOROLA
General Description
1.2 Introduction
The MC68HC908MR32 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
1.3 Features
Features of the MC68HC908MR32 include:
High-performance M68HC08 architecture
Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
8-MHz internal bus frequency
On-chip FLASH memory with in-circuit programming capabilities
of FLASH program memory:
MC68HC908MR32 — 32 Kbytes
MC68HC908MR16 — 16 Kbytes
On-chip programming firmware for use with host personal
computer
FLASH data security(1)
768 bytes of on-chip random-access memory (RAM)
12-bit, 6-channel center-aligned or edge-aligned pulse-width
modulator (PWMMC)
Serial peripheral interface module (SPI)
Serial communications interface module (SCI)
16-bit, 4-channel timer interface module (TIMA)
16-bit, 2-channel timer interface module (TIMB)
Clock generator module (CGM)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
General Description
MCU Block Diagram
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA General Description 31
Low-voltage inhibit (LVI) module with software selectable trip
points
10-bit, 10-channel analog-to-digital converter (ADC)
System protection features:
Optional computer operating properly (COP) reset
Low-voltage detection with optional reset
Illegal opcode or address detection with optional reset
Fault detection with optional PWM disabling
Available packages:
64-pin plastic quad flat pack (QFP)
56-pin shrink dual in-line package (SDIP)
Low-power design, fully static with wait mode
Master reset pin (RST) and power-on reset (POR)
Stop mode as an option
Break module (BRK) supports setting the in-circuit simulator (ICS)
single break point
Features of the CPU08 include:
Enhanced M68HC05 programming model
Extensive loop control functions
16 addressing modes (eight more than the M68HC05)
16-bit index register and stack pointer
Memory-to-memory data transfers
•Fast 8 × 8 multiply instruction
Fast 16/8 divide instruction
Binary-coded decimal (BCD) instructions
Optimization for controller applications
C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908MR32.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
32 General Description MOTOROLA
General Description
Figure 1-1. MCU Block Diagram
CLOCK GENERATOR
MODULE
SYSTEM INTEGRATION
MODULE
SERIAL COMMUNICATIONS INTERFACE
MODULE
SERIAL PERIPHERAL INTERFACE
MODULE(2)
TIMER INTERFACE
MODULE A
LOW-VOLTAGE INHIBIT
MODULE
POWER-ON RESET
MODULE
COMPUTER OPERATING PROPERLY
MODULE
ARITHMETIC/LOGIC
UNIT
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS — 112 BYTES
USER FLASH — 32,256 BYTES
USER RAM — 768 BYTES
MONITOR ROM — 240 BYTES
USER FLASH VECTOR SPACE — 46 BYTES
IRQ
MODULE
POWER
PTA
DDRA
DDRB
PTB
DDRC
PTCPTD
DDRE
PTE
PTF
DDRF
INTERNAL BUS
OSC1
OSC2
CGMXFC
RST
IRQ
VSS
VDD
VDDA
PTA7–PTA0
PTE7/TCH3A
PTE6/TCH2A
PTE5/TCH1A
PTE4/TCH0A
PTE3/TCLKA
PTE2/TCH1B(1)
PTE1/TCH0B(1)
PTE0/TCLKB(1)
PTF5/TxD
PTF4/RxD
PTF3/MISO(1)
PTF2/MOSI(1)
PTF1/SS(1)
PTF0/SPSCK(1)
TIMER INTERFACE
MODULE B
PULSE-WIDTH MODULATOR
MODULE
PTB7/ATD7
PTB6/ATD6
PTB5/ATD5
PTB4/ATD4
PTB3/ATD3
PTB2/ATD2
PTB1/ATD1
PTB0/ATD0
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1/ATD9(1)
PTC0/ATD8
PTD6/IS3
PTD5/IS2
PTD4/IS1
PTD3/FAULT4
PTD2/FAULT3
PTD1/FAULT2
PTD0/FAULT1
PWM6–PWM1
ANALOG-TO-DIGITAL CONVERTER
MODULE
VSSA
VDDA
VSSA(3)
PWMGND
VREFL(3
VREFH
Notes:
1. These pins are not available in the 56-pin SDIP package.
2. This module is not available in the 56-pin SDIP package.
3. In the 56-pin SDIP package, these pins are bonded together.
SINGLE BRKPT BREAK
MODULE
General Description
Pin Assignments
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA General Description 33
1.5 Pin Assignments
Figure 1-2 shows the 64-pin QFP pin assignments and Figure 1-3
shows the 56-pin SDIP pin assignments.
Figure 1-2. 64-Pin QFP Pin Assignments
PTC1/ATD9
PTA2
VSS
PTC0/ATD8
PTB7/ATD7
PTB6/ATD6
PTB5/ATD5
PTB4/ATD4
PTB3/ATD3
PTB2/ATD2
VDDA
VSSA
VREFL
VREFH
PTC2
PTC3
PTC4
PTC5
IRQ
PTF5/TxD
PTF4/RxD
PTF3/MISO
PTF2/MOSI
PTF1/SS
PTF0/SPSCK
VDD
PTE7/TCH3A
PTE6/TCH2A
PTE5/TCH1A
PTE4/TCH0A
PTE3/TCLKA
PTE2/TCH1B
PTE1/TCH0B
PTA1
PTA0
VSSA
OSC2
OSC1
CGMXFC
VDDA
RST
PTB1/ATD1
PTB0/ATD0
PTA7
PTA6
PTA5
PTA4
PTA3
PTD1/FAULT2
PTC6
PTD0/FAULT1
PTD2/FAULT3
PTD3/FAULT4
PTD4/IS1
PTD5/IS2
PTD6/IS3
PWM1
PWM2
PWM3
PWM4
PTE0/TCLKB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWMGND
PWM5
PWM6
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
34 General Description MOTOROLA
General Description
Figure 1-3. 56-Pin SDIP Pin Assignments
PTA2 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PTA3
PTA4
PTA5
PTA6
PTA7
PTB0/ATD0
PTB1/ATD1
PTB2/ATD2
PTB3/ATD3
PTB4/ATD4
PTB5/ATD5
PTB6/ATD5
PTB7/ATD7
PTC0/ATD8
VDDAD
VSSAD/VREFL
VREFH
PTC2
PTC3
PTC4
PTC5
PTC6
PTD0/FAULT1
PTD1/FAULT2
PTD2/FAULT3
PTD3/FAULT4
PTD4/IS1 PTD5/IS2
PTD6/IS3
PWM1
PWM2
PWM3
PWM4
PWMGND
PWM5
PWM6
NC
PTE3/TCLKA
PTE4/TCH0A
PTE5/TCH1A
PTE6/TCH2A
PTE7/TCH3A
VDD
VSS
PTF4/RxD
PTF5/TxD
IRQ
RST
VDDA
CGMXFC
OSC1
OSC2
VSSA
PTA0
PTA1
Note: PTC1, PTE0, PTE1, PTE2, PTF0, PTF1, PTF2, and PTF3 are removed from this package.
General Description
Pin Assignments
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA General Description 35
1.5.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high-current levels.
Figure 1-4. Power Supply Bypassing
1.5.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. For more detailed information, see Section 8. Clock Generator
Module (CGM).
1.5.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
MCU
VDD
C2
C1
0.1 µF
VSS
VDD
+
Note: Component values shown represent typical applications.
1–10 µF
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
36 General Description MOTOROLA
General Description
any internal reset source is asserted. See Section 7. System
Integration Module (SIM).
1.5.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. See Section 17. External
Interrupt (IRQ).
1.5.5 CGM Power Supply Pins (VDDA and VSSA)
VDDA and VSSA are the power supply pins for the analog portion of the
clock generator module (CGM). Decoupling of these pins should be per
the digital supply. See Section 8. Clock Generator Module (CGM).
1.5.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See
Section 8. Clock Generator Module (CGM).
1.5.7 Analog Power Supply Pins (VDDA and VSSA)
VDDAD and VSSA are the power supply pins for the analog-to-digital
converter. Decoupling of these pins should be per the digital supply. See
Section 19. Analog-to-Digital Converter (ADC).
1.5.8 ADC Voltage Decoupling Capacitor Pin (VREFH)
VREFH is the power supply for setting the reference voltage. Connect the
VREFH pin to the same voltage potential as VDDAD. See Section 19.
Analog-to-Digital Converter (ADC).
1.5.9 ADC Voltage Reference Low Pin (VREFL)
VREFL is the lower reference supply for the ADC. Connect the VREFL pin
to the same voltage potential as VSSAD. See Section 19.
Analog-to-Digital Converter (ADC).
General Description
Pin Assignments
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA General Description 37
1.5.10 Port A Input/Output (I/O) Pins (PTA7PTA0)
PTA7–PTA0 are general-purpose bidirectional input/output (I/O) port
pins. See Section 15. Input/Output (I/O) Ports.
1.5.11 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)
Port B is an 8-bit special function port that shares all eight pins with the
analog-to-digital converter (ADC). See Section 19. Analog-to-Digital
Converter (ADC) and Section 15. Input/Output (I/O) Ports.
1.5.12 Port C I/O Pins (PTC6–PTC2 and PTC1/ATD9–PTC0/ATD8)
PTC6–PTC2 are general-purpose bidirectional I/O port pins (see
Section 15. Input/Output (I/O) Ports). PTC1/ATD9–PTC0/ATD8 are
special function port pins that are shared with the analog-to-digital
converter (ADC). See Section 19. Analog-to-Digital Converter (ADC)
and Section 15. Input/Output (I/O) Ports.
1.5.13 Port D Input-Only Pins (PTD6/IS3–PTD4/IS1 and PTD3/FAULT4–PTD0/FAULT1)
PTD6/IS3–PTD4/IS1 are special function input-only port pins that also
serve as current sensing pins for the pulse-width modulator module
(PWMMC). PTD3/FAULT4–PTD0/FAULT1 are special function port pins
that also serve as fault pins for the PWMMC. See Section 9.
Pulse-Width Modulator for Motor Control (PWMMC) and Section 15.
Input/Output (I/O) Ports.
1.5.14 PWM Pins (PWM6–PWM1)
PWM6–PWM1 are dedicated pins used for the outputs of the
pulse-width modulator module (PWMMC). These are high-current sink
pins. See Section 9. Pulse-Width Modulator for Motor Control
(PWMMC) and Section 22. Electrical Specifications.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
38 General Description MOTOROLA
General Description
1.5.15 PWM Ground Pin (PWMGND)
PWMGND is the ground pin for the pulse-width modulator module
(PWMMC). This dedicated ground pin is used as the ground for the six
high-current PWM pins. See Section 9. Pulse-Width Modulator for
Motor Control (PWMMC).
1.5.16 Port E I/O Pins (PTE7/TCH3A–PTE3/TCLKA and PTE2/TCH1B–PTE0/TCLKB)
Port E is an 8-bit special function port that shares its pins with the two
timer interface modules (TIMA and TIMB). See Section 11. Timer
Interface A (TIMA), Section 12. Timer Interface B (TIMB), and
Section 15. Input/Output (I/O) Ports.
1.5.17 Port F I/O Pins (PTF5/TxD–PTF4/RxD and PTF3/MISO–PTF0/SPSCK)
Port F is a 6-bit special function port that shares two of its pins with the
serial communications interface module (SCI) and four of its pins with
the serial peripheral interface module (SPI). See Section 13. Serial
Peripheral Interface Module (SPI), Section 14. Serial
Communications Interface Module (SCI), and Section 15.
Input/Output (I/O) Ports.
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Memory Map 39
Advance Information — MC68HC908MR16/MC68HC908MR32
Section 2. Memory Map
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .39
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.5 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.2 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory
space. The memory map, shown in Figure 2-1, includes:
32 Kbytes of FLASH
768 bytes of random-access memory (RAM)
46 bytes of user-defined vectors
240 bytes of monitor read-only memory (ROM)
2.3 Unimplemented Memory Locations
Some addresses are unimplemented. Accessing an unimplemented
address can cause an illegal address reset. In the memory map and in
the input/output (I/O) register summary, unimplemented addresses are
shaded.
Some I/O bits are read only; the write function is unimplemented. Writing
to a read-only I/O bit has no effect on microcontroller unit (MCU)
operation. In register figures, the write function of read-only bits is
shaded.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
40 Memory Map MOTOROLA
Memory Map
Similarly, some I/O bits are write only; the read function is
unimplemented. Reading of write-only I/O bits has no effect on MCU
operation. In register figures, the read function of write-only bits is
shaded.
2.4 Reserved Memory Locations
Some addresses are reserved. Writing to a reserved address can
have unpredictable effects on MCU operation. In the memory map,
Figure 2-1, and in the I/O register summary, Figure 2-2, reserved
addresses are marked with the word reserved.
Some I/O bits are reserved. Writing to a reserved bit can have
unpredictable effects on MCU operation. In register figures, reserved
bits are marked with the letter R.
2.5 I/O Section
Addresses $0000–$005F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
$FE00, SIM break status register (SBSR)
$FE01, SIM reset status register (SRSR)
$FE03, SIM break flag control register (SBFCR)
$FE07, FLASH control register (FLCR)
$FE0C, Break address register high (BRKH)
$FE0D, Break address register low (BRKL)
$FE0E, Break status and control register (BRKSCR)
$FE0F, LVI status and control register (LVISCR)
$FF7E, FLASH block protect register (FLBPR)
$FFFF, COP control register (COPCTL)
Memory Map
I/O Section
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Memory Map 41
$0000
$005F I/O REGISTERS — 96 BYTES
$0060
$035F RAM — 768 BYTES
$0360
$7FFF UNIMPLEMENTED — 31,904 BYTES
$8000
$FDFF FLASH — 32,256 BYTES
$FE00 SIM BREAK STATUS REGISTER (SBSR)
$FE01 SIM RESET STATUS REGISTER (SRSR)
$FE02 RESERVED
$FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR)
$FE04 RESERVED
$FE05 RESERVED
$FE06 RESERVED
$FE07 RESERVED
$FE08 FLASH CONTROL REGISTER (FLCR)
$FE09 UNIMPLEMENTED
$FE0A UNIMPLEMENTED
$FE0B UNIMPLEMENTED
$FE0C SIM BREAK ADDRESS REGISTER HIGH (BRKH)
$FE0D SIM BREAK ADDRESS REGISTER LOW (BRKL)
$FE0E SIM BREAK FLAG CONTROL REGISTER (SBFCR)
$FE0F LVI STATUS AND CONTROL REGISTER (LVISCR)
$FE10
$FEFF MONITOR ROM — 240 BYTES
$FF00
$FF7D UNIMPLEMENTED — 126 BYTES
$FF7E FLASH BLOCK PROTECT REGISTER (FLBPR)
$FF7F
$FFD1 UNIMPLEMENTED — 83 BYTES
$FFD2
$FFFF VECTORS — 46 BYTES
Figure 2-1. Memory Map
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
42 Memory Map MOTOROLA
Memory Map
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
$0000 Port A Data Register
(PTA)
See page 310.
Read: PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by reset
$0001 Port B Data Register
(PTB)
See page 312.
Read: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
$0002 Port C Data Register
(PTC)
See page 314.
Read: 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Write: R
Reset: Unaffected by reset
$0003 Port D Data Register
(PTD)
See page 316.
Read: 0 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write: R R R R R R R R
Reset: Unaffected by reset
$0004 Data Direction Register A
(DDRA)
See page 310.
Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 0 0 0 0 0 0 0 0
$0005 Data Direction Register B
(DDRB)
See page 312.
Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset: 0 0 0 0 0 0 0 0
$0006 Data Direction Register C
(DDRC)
See page 314.
Read: 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write: R
Reset: 0 0 0 0 0 0 0 0
$0007 Unimplemented
$0008 Port E Data Register
(PTE)
See page 317.
Read: PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0
Write:
Reset: Unaffected by reset
$0009 Port F Data Register
(PTF)
See page 319.
Read: 0 0 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
Write: R R
Reset: Unaffected by reset
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 1 of 10)
Memory Map
I/O Section
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Memory Map 43
$000A Unimplemented
$000B Unimplemented
$000C Data Direction Register E
(DDRE)
See page 318.
Read: DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Write:
Reset: 0 0 0 0 0 0 0 0
$000D Data Direction Register F
(DDRF)
See page 320.
Read: 0 0 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Write: R R
Reset: 0 0 0 0 0 0
$000E TIMA Status/Control Register
(TASC)
See page 214.
Read: TOF TOIE TSTOP 00
PS2 PS1 PS0
Write: 0 TRST R
Reset: 0 0 1 0 0 0 0 0
$000F TIMA Counter Register High
(TACNTH)
See page 216.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
$0010 TIMA Counter Register Low
(TACNTL)
See page 216.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
$0011 TIMA Counter Modulo
Register High (TAMODH)
See page 217.
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: 1 1 1 1 1 1 1 1
$0012 TIMA Counter Modulo
Register Low (TAMODL)
See page 217.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 1 1 1 1 1 1 1 1
$0013 TIMA Channel 0 Status/Control
Register (TASC0)
See page 218.
Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset: 0 0 0 0 0 0 0 0
$0014 TIMA Channel 0 Register High
(TACH0H)
See page 222.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 2 of 10)
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
44 Memory Map MOTOROLA
Memory Map
$0015 TIMA Channel 0 Register Low
(TACH0L)
See page 222.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
$0016 TIMA Channel 1 Status/Control
Register (TASC1)
See page 222.
Read: CH1F CH1IE 0MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0 R
Reset: 0 0 0 0 0 0 0 0
$0017 TIMA Channel 1 Register High
(TACH1H)
See page 222.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
$0018 TIMA Channel 1 Register Low
(TACH1L)
See page 222.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
$0019 TIMA Channel 2 Status/Control
Register (TASC2)
See page 218.
Read: CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX
Write: 0
Reset: 0 0 0 0 0 0 0 0
$001A TIMA Channel 2 Register High
(TACH2H)
See page 222.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
$001B TIMA Channel 2 Register Low
(TACH2L)
See page 222.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
$001C TIMA Channel 3 Status/Control
Register (TASC3)
See page 218.
Read: CH3F CH3IE 0MS3A ELS3B ELS3A TOV3 CH3MAX
Write: 0 R
Reset: 0 0 0 0 0 0 0 0
$001D TIMA Channel 3 Register High
(TACH3H)
See page 222.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
$001E TIMA Channel 3 Register Low
(TACH3L)
See page 222.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 3 of 10)
Memory Map
I/O Section
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Memory Map 45
$001F Configuration Register
(CONFIG)
See page 68.
Read: EDGE BOTNEG TOPNEG INDEP LVIRST LVIPWR STOPE COPD
Write:
Reset: 0 0 0 0 1 1 0 0
$0020 PWM Control Register 1
(PCTL1)
See page 171.
Read: DISX DISY PWMINT PWMF ISENS1 ISENS0 LDOK PWMEN
Write:
Reset: 0 0 0 0 0 0 0 0
$0021 PWM Control Register 2
(PCTL2)
See page 174.
Read: LDFQ1 LDFQ0 0IPOL1 IPOL2 IPOL3 PRSC1 PRSC0
Write:
Reset: 0 0 0 0 0 0 0 0
$0022 Fault Control Register
(FCR)
See page 177.
Read: FINT4 FMODE4 FINT3 FMODE3 FINT2 FMODE2 FINT1 FMODE1
Write:
Reset: 0 0 0 0 0 0 0 0
$0023 Fault Status Register
(FSR)
See page 179.
Read: FPIN4 FFLAG4 FPIN3 FFLAG3 FPIN2 FFLAG2 FPIN1 FFLAG1
Write:
Reset: U 0 U 0 U 0 U 0
$0024 Fault Acknowledge Register
(FTACK)
See page 180.
Read: 0 0 DT6 DT5 DT4 DT3 DT2 DT1
Write: FTACK4 FTACK3 FTACK2 FTACK1
Reset: 0 0 0 0 0 0 0 0
$0025 PWM Output Control
Register (PWMOUT)
See page 182.
Read: 0 OUTCTL OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Write:
Reset: 0 0 0 0 0 0 0 0
$0026 PWM Counter Register High
(PCNTH)
See page 168.
Read: 0 0 0 0 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
$0027 PWM Counter Register Low
(PCNTL)
See page 168.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
$0028 PWM Counter Modulo Register
High (PMODH)
See page 169.
Read: 0 0 0 0 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 X X X X
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 4 of 10)
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
46 Memory Map MOTOROLA
Memory Map
$0029 PWM Counter Modulo Register
Low (PMODL)
See page 169.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: X X X X X X X X
$002A PWM 1 Value Register High
(PVAL1H)
See page 170.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
$002B PWM 1 Value Register Low
(PVAL1L)
See page 170.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
$002C PWM 2 Value Register High
(PVAL2H)
See page 170.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
$002D PWM 2 Value Register Low
(PVAL2L)
See page 170.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
$002E PWM 3 Value Register High
(PVAL3H)
See page 170.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
$002F PWM 3 Value Register Low
(PVAL3L)
See page 170.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
$0030 PWM 4 Value Register High
(PVAL4H)
See page 170.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
$0031 PWM 4 Value Register Low
(PVAL4L)
See page 170.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
$0032 PWM 5 Value Register High
(PMVAL5H)
See page 170.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 5 of 10)
Memory Map
I/O Section
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Memory Map 47
$0033 PWM 5 Value Register Low
(PVAL5L)
See page 170.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
$0034 PWM 6 Value Register High
(PVAL6H)
See page 170.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
$0035 PWM 6 Value Register Low
(PMVAL6L)
See page 170.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
$0036 Dead-Time Write-Once
Register (DEADTM)
See page 176.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 1 1 1 1 1 1 1 1
$0037 PWM Disable Mapping
Write-Once Register
(DISMAP) See page 161.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 1 1 1 1 1 1 1 1
$0038 SCI Control Register 1
(SCC1)
See page 293.
Read: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
Write:
Reset: 0 0 0 0 0 0 0 0
$0039 SCI Control Register 2
(SCC2)
See page 296.
Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK
Write:
Reset: 0 0 0 0 0 0 0 0
$003A SCI Control Register 3
(SCC3)
See page 298.
Read: R8 T8 00
ORIE NEIE FEIE PEIE
Write: R R R
Reset: U U 0 0 0 0 0 0
$003B SCI Status Register 1
(SCS1)
See page 300.
Read: SCTE TC SCRF IDLE OR NF FE PE
Write: R R R R R R R R
Reset: 1 1 0 0 0 0 0 0
$003C SCI Status Register 2
(SCS2)
See page 303.
Read: 0 0 0 0 0 0 BKF RPF
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 6 of 10)
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
48 Memory Map MOTOROLA
Memory Map
$003D SCI Data Register
(SCDR)
See page 304.
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
$003E SCI Baud Rate Register
(SCBR)
See page 304.
Read: 0 0 SCP1 SCP0 0SCR2 SCR1 SCR0
Write: R R R
Reset: 0 0 0 0 0 0 0 0
$003F IRQ Status/Control Register
(ISCR)
See page 334.
Read: 0 0 0 0 IRQF 0IMASK1 MODE1
Write: R R R R ACK1
Reset: 0 0 0 0 0 0 0 0
$0040 ADC Status and Control
Register (ADSCR)
See page 349.
Read: COCO/
IDMAS AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset: 0 0 0 1 1 1 1 1
$0041 ADC Data Register High
Right Justified Mode(ADRH)
See page 352.
Read: 0 0 0 0 0 0 AD9 AD8
Write: R R R R R R R R
Reset: Unaffected by reset
$0042 ADC Data Register Low
Right Justified Mode (ADRL)
See page 353.
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write: R R R R R R R R
Reset: Unaffected by reset
$0043 ADC Clock Register
(ADCLK)
See page 354.
Read: ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 0 0
Write: R
Reset: 0 1 1 1 0 0 0 0
$0044 SPI Control Register
(SPCR)
See page 270.
Read: SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
Write:
Reset: 0 0 1 0 1 0 0 0
$0045 SPI Status and Control
Register (SPSCR)
See page 272.
Read: SPRF ERRIE OVRF MODF SPTE MODFEN SPR1 SPR0
Write: R R R R
Reset: 0 0 0 0 1 0 0 0
$0046 SPI Data Register
(SPDR)
See page 275.
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 7 of 10)
Memory Map
I/O Section
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Memory Map 49
$0047 Unimplemented
$0050 Unimplemented
$0051 TIMB Status/Control Register
(TBSC)
See page 238.
Read: TOF TOIE TSTOP 00
PS2 PS1 PS0
Write: 0 TRST R
Reset: 0 0 1 0 0 0 0 0
$0052 TIMB Counter Register High
(TBCNTH)
See page 240.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
$0053 TIMB Counter Register Low
(TBCNTL)
See page 240.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
$0054 TIMB Counter Modulo Register
High (TBMODH)
See page 241.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 1 1 1 1 1 1 1 1
$0055 TIMB Counter Modulo Register
Low (TBMODL)
See page 241.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 1 1 1 1 1 1 1 1
$0056 TIMB Channel 0 Status/Control
Register
(TBSC0) See page 242.
Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset: 0 0 0 0 0 0 0 0
$0057 TIMB Channel 0 Register High
(TBCH0H)
See page 246.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
$0058 TIMB Channel 0 Register Low
(TBCH0L)
See page 246.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 8 of 10)
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
50 Memory Map MOTOROLA
Memory Map
$0059 TIMB Channel 1 Status/Control
Register
(TBSC1) See page 242.
Read: CH1F CH1IE 0MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0 R
Reset: 0 0 0 0 0 0 0 0
$005A TIMB Channel 1 Register High
(TBCH1H)
See page 246.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
$005B TIMB Channel 1 Register Low
(TBCH1L)
See page 246.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
$005C PLL Control Register
(PCTL)
See page 124.
Read: PLLIE PLLF PLLON BCS 1111
Write: R R R R R
Reset: 0 0 1 0 1 1 1 1
$005D PLL Bandwidth Control
Register (PBWC)
See page 126.
Read: AUTO LOCK ACQ XLD 0000
Write: R R R R R
Reset: 0 0 0 0 0 0 0 0
$005E PLL Programming Register
(PPG)
See page 128.
Read: MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Write:
Reset: 0 1 1 0 0 1 1 0
$005F Unimplemented
$FE00 SIM Break Status Register
(SBSR)
See page 104.
Read: RR R R R RBWR
Write:
Reset: 0
$FE01 SIM Reset Status Register
(SRSR)
See page 106.
Read: POR PIN COP ILOP ILAD MENRST LVI 0
Write: R R R R R R R R
Reset: 1 0 0 0 0 0 0 0
$FE03 SIM Break Flag Control
Register (SBFCR)
See page 107.
Read: BCFE R R R R R R R
Write:
Reset: 0
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 9 of 10)
Memory Map
I/O Section
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Memory Map 51
$FE08
FLASH Control Register
(FLCR)
See page 59.
Read: 0 0 0 0 HVEN MASS ERASE PGM
Write:
Reset: 0 0 0 0 0 0 0 0
$FE0C Break Address Register High
(BRKH)
See page 364.
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
$FE0D Break Address Register Low
(BRKL)
See page 364.
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
$FE0E Break Status and Control Reg-
ister (BRKSCR)
See page 363.
Read: BRKE BRKA 00 0 000
Write:
Reset: 0 0 0 0 0 0 0 0
$FE0F LVI Status and Control
Register (LVISCR)
See page 338.
Read: LVIOUT 0 TRPSEL 00000
Write: R R R R R R R
Reset: 0 0 0 0 0 0 0 0
$FF7E FLASH Block Protect Register
(FLBPR)
See page 65.
Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset: 0 00 0 0 000
$FFFF COP Control Register
(COPCTL)
See page 326.
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 10 of 10)
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
52 Memory Map MOTOROLA
Memory Map
Table 2-1 is a list of vector locations.
Table 2-1. Vector Addresses
Address Vector
Low
$FFD2 SCI transmit vector (high)
$FFD3 SCI transmit vector (low)
$FFD4 SCI receive vector (high)
$FFD5 SCI receive vector (low)
$FFD6 SCI error vector (high)
$FFD7 SCI error vector (low)
$FFD8 SPI transmit vector (high)(1)
$FFD9 SPI transmit vector (low)(1)
$FFDA SPI receive vector (high)(1)
$FFDB SPI receive vector (low)(1)
$FFDC A/D vector (high)
$FFDD A/D vector (low)
$FFDE TIM B overflow vector (high)
$FFDF TIM B overflow vector (low)
$FFE0 TIM B channel 1 vector (high)
$FFE1 TIM B channel 1 vector (low)
$FFE2 TIM B channel 0 vector (high)
$FFE3 TIM B channel 0 vector (low)
$FFE4 TIM A overflow vector (high)
$FFE5 TIM A overflow vector (low)
$FFE6 TIM A channel 3 vector (high)
$FFE7 TIM A channel 3 vector (low)
$FFE8 TIM A channel 2 vector (high)
$FFE9 TIM A channel 2 vector (low)
$FFEA TIM A channel 1 vector (high)
$FFEB TIM A channel 1 vector (low)
$FFEC TIM A channel 0 vector (high)
$FFED TIM A channel 0 vector (low)
1. The SPI module is not available in the 56-pin SDIP package.
Priority
Memory Map
Monitor ROM
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Memory Map 53
2.6 Monitor ROM
The 240 bytes at addresses $FE10–$FEFF are reserved ROM
addresses that contain the instructions for the monitor functions. See
Section 10. Monitor ROM (MON).
$FFEE PWMMC vector (high)
$FFEF PWMMC vector (low)
$FFF0 FAULT 4 (high)
$FFF1 FAULT 4 (low)
$FFF2 FAULT 3 (high)
$FFF3 FAULT 3 (low)
$FFF4 FAULT 2 (high)
$FFF5 FAULT 2 (low)
$FFF6 FAULT 1 (high)
$FFF7 FAULT 1 (low)
$FFF8 PLL vector (high)
$FFF9 PLL vector (low)
$FFFA IRQ vector (high)
$FFFB IRQ vector (low)
$FFFC SWI vector (high)
$FFFD SWI vector (low)
High
$FFFE Reset vector (high)
$FFFF Reset vector (low)
Table 2-1. Vector Addresses (Continued)
Address Vector
Priority
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
54 Memory Map MOTOROLA
Memory Map
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Random-Access Memory (RAM) 55
Advance Information — MC68HC908MR16/MC68HC908MR32
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.2 Introduction
This section describes the 768 bytes of random-access memory (RAM).
3.3 Functional Description
Addresses $0060–$035F are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 160 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing
mode instructions can access efficiently all page zero RAM locations.
Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the central processor unit (CPU) uses
five bytes of the stack to save the contents of the CPU registers.
NOTE: For M68HC05 and M1468HC05 compatibility, the H register is not
stacked.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
56 Random-Access Memory (RAM) MOTOROLA
Random-Access Memory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA FLASH Memory 57
Advance Information — MC68HC908MR16/MC68HC908MR32
Section 4. FLASH Memory
4.1 Contents
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .60
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .61
4.7 FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . . . .62
4.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . .65
4.10 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.11 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.2 Introduction
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
58 FLASH Memory MOTOROLA
FLASH Memory
4.3 Functional Description
The FLASH memory is an array of 32,256 bytes with an additional
46 bytes of user vectors and one byte of block protection.
NOTE: An erased bit reads as a logic 1 and a programmed bit reads as a logic 0.
Program and erase operations are facilitated through control bits in a
memory mapped register. Details for these operations appear later in
this section.
Memory in the FLASH array is organized into two rows per page. The
page size is 128 bytes per page. The minimum erase page size is
128 bytes. Programming is performed on a row basis, 64 bytes at a time.
The address ranges for the user memory and vectors are:
$8000–$FDFF, user memory
$FF7E, block protect register (FLBPR)
$FE08, FLASH control register (FLCR)
$FFDC–$FFFF, reserved for user-defined interrupt and reset
vectors
Programming tools are available from Motorola. Contact a local Motorola
representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.(1)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
FLASH Memory
FLASH Control Register
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA FLASH Memory 59
4.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
Setting this read/write bit configures the 32-Kbyte FLASH array for
mass erase operation.
1 = MASS erase operation selected
0 = MASS erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
Address: $FE08
Bit 7654321Bit 0
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
= Unimplemented
Figure 4-1. FLASH Control Register (FLCR)
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
60 FLASH Memory MOTOROLA
FLASH Memory
4.5 FLASH Page Erase Operation
Use this step-by-step procedure to erase a page (128 bytes) of FLASH
memory to read as logic 1:
1. Set the ERASE bit, and clear the MASS bit in the FLASH control
register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address within the page address
range desired.
4. Wait for a time, tNVS, minimum of 10 µs.
5. Set the HVEN bit.
6. Wait for a time, tErase, minimum of 1 ms.
7. Clear the ERASE bit.
8. Wait for a time, tNVH, minimum of 5 µs.
9. Clear the HVEN bit.
10. After a time, tRCV (typically 1 µs), the memory can be accessed
again in read mode.
NOTE: While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
FLASH Memory
FLASH Mass Erase Operation
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA FLASH Memory 61
4.6 FLASH Mass Erase Operation
Use this step-by-step procedure to erase the entire FLASH memory to
read as logic 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control
register.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH address(2) within the FLASH
memory address range.
4. Wait for a time, tNVS, minimum of 10 µs.
5. Set the HVEN bit.
6. Wait for a time, tMErase, minimum of 4 ms.
7. Clear the ERASE bit.
8. Wait for a time, tNVHL, minimum of 100 µs.
9. Clear the HVEN bit.
10. After a time, tRCV (minimum of 1 µs), the memory can be accessed
again in read mode.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
2. In monitor mode, when security sequence fails (see Section 10. Monitor ROM (MON)), write
to the FLASH block protect register instead of any FLASH address.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
62 FLASH Memory MOTOROLA
FLASH Memory
4.7 FLASH Program/Read Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes starting from addresses $XX00,
$XX40, $0080 and $XXC0.
Use this step-by-step procedure to program a row of FLASH memory
(Figure 4-2 provides a flowchart representation):
1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH address within the row address
range desired.
4. Wait for a time, tNVS, minimum of 10 µs.
5. Set the HVEN bit.
6. Wait for a time, tPGS, minimum of 5 µs.
7. Write data to the FLASH address to be programmed.
8. Wait for a time, tPROG, minimum of 30 µs.
9. Repeat step 7 and 8 until all the bytes within the row are
programmed.
10. Clear the PGM bit.(3)
11. Wait for a time, tNVH, minimum of 5 µs.
12. Clear the HVEN bit.
13. After a time, tRCV (minimum of 1 µs), the memory can be accessed
in read mode again.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE: The time between each FLASH address change, or the time between
the last FLASH address programmed to clearing of the PGM bit, must
not exceed the maximum programming time, tPROG.
FLASH Memory
FLASH Program/Read Operation
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA FLASH Memory 63
Figure 4-2. FLASH Programming Flowchart
SET HVEN BIT
READ THE FLASH BLOCK PROTECT REGISTER
WRITE ANY DATA TO ANY FLASH ADDRESS
WITHIN THE ROW ADDRESS RANGE DESIRED
WAIT FOR A TIME, tNVS
SET PGM BIT
WAIT FOR A TIME, tPGS
WRITE DATA TO THE FLASH ADDRESS
TO BE PROGRAMMED
WAIT FOR A TIME, tPROG
CLEAR PGM BIT
WAIT FOR A TIME, tNVH
CLEAR HVEN BIT
WAIT FOR A TIME, tRCV
COMPLETED
PROGRAMMING
THIS ROW?
YES
NO
END OF PROGRAMMING
The time between each FLASH address change (step 7 to step 7), or
must not exceed the maximum programming
time, tPROG max.
the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
Note:
1
2
3
4
5
6
7
8
10
11
12
13
ALGORITHM FOR PROGRAMMING
A ROW (64 BYTES) OF FLASH MEMORY
This row program algorithm assumes the row/s
to be programmed are initially erased.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
64 FLASH Memory MOTOROLA
FLASH Memory
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum. See Section
22. Electrical Specifications.
4.8 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
a block of memory from unintentional erase or program operations due
to system malfunction. This protection is done by using a FLASH block
protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be
protected. The range of the protected area starts from a location defined
by FLBPR and ends at the bottom of the FLASH memory ($FFFF). When
the memory is protected, the HVEN bit cannot be set in either ERASE or
PROGRAM operations.
NOTE: In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit
When the FLBPR is programmed with all 0s, the entire memory is
protected from being programmed and erased. When all the bits are
erased (all 1s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of
memory, whose address ranges are shown in 4.9 FLASH Block Protect
Register. Once the FLBPR is programmed with a value other than $FF,
any erase or program of the FLBPR or the protected block of FLASH
memory is prohibited. The FLBPR itself can be erased or programmed
only with an external voltage, VTST, present on the IRQ pin. This voltage
also allows entry from reset into the monitor mode.
FLASH Memory
FLASH Block Protect Register
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA FLASH Memory 65
4.9 FLASH Block Protect Register
The FLASH block protect register (FLBPR) is implemented as a byte
within the FLASH memory, and therefore can be written only during a
programming sequence of the FLASH memory. The value in this register
determines the starting location of the protected range within the FLASH
memory.
BPR[7:0] — FLASH Block Protect Bits
These eight bits represent bits [14:7] of a 16-bit memory address.
Bit 15 is logic 1 and bits [6:0] are logic 0s.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory at $FFFF. With
this mechanism, the protect start address can be XX00 and XX80
(128 bytes page boundaries) within the FLASH memory.
Figure 4-4. FLASH Block Protect Start Address
Refer to Table 4-1 for examples of the protect start address.
Address: $FF7E
Bit 7654321Bit 0
Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset:00000000
U = Unaffected by reset. Initial value from factory is 1.
Write to this register by a programming sequence to the FLASH memory.
Figure 4-3. FLASH Block Protect Register (FLBPR)
1FLBPR VALUE
16-BIT MEMORY ADDRESS
0000000
START ADDRESS OF FLASH
BLOCK PROTECT
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
66 FLASH Memory MOTOROLA
FLASH Memory
4.10 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH. Otherwise, the operation will
discontinue, and the FLASH will be on standby mode.
4.11 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.
The STOP instruction should not be executed while performing a
program or erase operation on the FLASH, otherwise the operation will
discontinue, and the FLASH will be on standby mode
NOTE: Standby mode is the power-saving mode of the FLASH module in which
all internal control signals to the FLASH are inactive and the current
consumption of the FLASH is at a minimum.
Table 4-1. Examples of Protect Start Address
BPR[7:0] Start of Address of Protect Range
$00 The entire FLASH memory is protected.
$01 (0000 0001) $8080 (1000 0000 1000 0000)
$02 (0000 0010) $8100 (1000 0001 0000 0000)
and so on...
$FE (1111 1110) $FF00 (1111 1111 0000 0000)
$FF The entire FLASH memory is not protected.
Note: The end address of the protected range is always $FFFF.
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Configuration Register (CONFIG) 67
Advance Information — MC68HC908MR16/MC68HC908MR32
Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
5.2 Introduction
This section describes the configuration register (CONFIG). This register
contains bits that configure these options:
Resets caused by the low-voltage inhibit (LVI) module
Power to the LVI module
Computer operating properly (COP) module
Top-side pulse-width modulator (PWM) polarity
Bottom-side PWM polarity
Edge-aligned versus center-aligned PWMs
Six independent PWMs versus three complementary PWM pairs
5.3 Functional Description
The configuration register (CONFIG) is used in the initialization of
various options. The configuration register can be written once after
each reset. All of the configuration register bits are cleared during reset.
Since the various options affect the operation of the microcontroller unit
(MCU), it is recommended that this register be written immediately after
reset. The configuration register is located at $001F and may be read at
anytime.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
68 Configuration Register (CONFIG) MOTOROLA
Configuration Register (CONFIG)
NOTE: On a FLASH device, the options are one-time writeable by the user after
each reset. The registers are not in the FLASH memory but are special
registers containing one-time writeable latches after each reset. Upon a
reset, the configuration register defaults to predetermined settings as
shown in Figure 5-1.
If the LVI module and the LVI reset signal are enabled, a reset occurs
when VDD falls to a voltage, VLVRx, and remains at or below that level for
at least nine consecutive central processor unit (CPU) cycles. Once an
LVI reset occurs, the MCU remains in reset until VDD rises to a voltage,
VLVRX.
5.4 Configuration Register
EDGE — Edge-Align Enable Bit
EDGE determines if the motor control PWM will operate in
edge-aligned mode or center-aligned mode. See Section 9.
Pulse-Width Modulator for Motor Control (PWMMC).
1 = Edge-aligned mode enabled
0 = Center-aligned mode enabled
BOTNEG — Bottom-Side PWM Polarity Bit
BOTNEG determines if the bottom-side PWMs will have positive or
negative polarity. See Section 9. Pulse-Width Modulator for Motor
Control (PWMMC).
1 = Negative polarity
0 = Positive polarity
Address: $001F
Bit 7654321Bit 0
Read: EDGE BOTNEG TOPNEG INDEP LVIRST LVIPWR STOPE COPD
Write:
Reset:00001100
Figure 5-1. Configuration Register (CONFIG)
Configuration Register (CONFIG)
Configuration Register
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Configuration Register (CONFIG) 69
TOPNEG — Top-Side PWM Polarity Bit
TOPNEG determines if the top-side PWMs will have positive or
negative polarity. See Section 9. Pulse-Width Modulator for Motor
Control (PWMMC).
1 = Negative polarity
0 = Positive polarity
INDEP — Independent Mode Enable Bit
INDEP determines if the motor control PWMs will be six independent
PWMs or three complementary PWM pairs. See Section 9.
Pulse-Width Modulator for Motor Control (PWMMC).
1 = Six independent PWMs
0 = Three complementary PWM pairs
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. See
Section 18. Low-Voltage Inhibit (LVI).
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. See Section 18. Low-Voltage
Inhibit (LVI).
1 = LVI module power enabled
0 = LVI module power disabled
STOPE — Stop Enable Bit
Writing a 0 or a 1 to bit 1 has no effect on MCU operation. Bit 1
operates the same as the other bits within this write-once register
operate.
1 = STOP mode enabled
0 = STOP mode disabled
COPD — COP Disable Bit
COPD disables the COP module. See Section 16. Computer
Operating Properly (COP).
1 = COP module disabled
0 = COP module enabled
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
70 Configuration Register (CONFIG) MOTOROLA
Configuration Register (CONFIG)
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Central Processor Unit (CPU) 71
Advance Information — MC68HC908MR16/MC68HC908MR32
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
6.2 Introduction
This section describes the central processor unit (CPU08, version A).
The M68HC08 CPU is an enhanced and fully object-code-compatible
version of the M68HC05 CPU. The CPU08 Reference Manual, Motorola
document order number CPU08RM/AD, contains a description of the
CPU instruction set, addressing modes, and architecture.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
72 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
6.3 Features
Features of the CPU08 include:
Fully upward, object-code compatibility with M68HC05 Family
16-bit stack pointer with stack manipulation instructions
16-bit index register with X-register manipulation instructions
8-MHz CPU internal bus frequency
64-Kbyte program/data memory space
16 addressing modes
Memory-to-memory data moves without using accumulator
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
Enhanced binary-coded decimal (BCD) data handling
Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64 Kbytes
Low-power wait mode
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
Figure 6-1. CPU Registers
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
ACCUMULATOR (A)
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
V11HINZC
H X
0
0
0
0
7
15
15
15
70
Central Processor Unit (CPU)
CPU Registers
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Central Processor Unit (CPU) 73
6.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 6-2. Accumulator (A)
Bit
151413121110987654321
Bit
0
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 6-3. Index Register (H:X)
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
74 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
6.4.3 Stack Pointer
The stack pointer (SP) is a 16-bit register that contains the address of
the next location on the stack. During a reset, the stack pointer is preset
to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000–$00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.
Bit
151413121110987654321
Bit
0
Read:
Write:
Reset:0000000011111111
Figure 6-4. Stack Pointer (SP)
Central Processor Unit (CPU)
CPU Registers
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Central Processor Unit (CPU) 75
6.4.4 Program Counter
The program counter (PC) is a 16-bit register that contains the address
of the next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
6.4.5 Condition Code Register
The 8-bit condition code register (CCR) contains the interrupt mask and
five flags that indicate the results of the instruction just executed. Bits 6
and 5 are set permanently to logic 1. The functions of the condition code
register are described here.
Bit
151413121110987654321
Bit
0
Read:
Write:
Reset: Loaded with vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Bit 7654321Bit 0
Read: V11HINZC
Write:
Reset:X11X1XXX
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
76 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The
half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations. The decimal adjust A (DAA) instruction uses the states of
the H and C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask Bit
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 compatibility, the upper byte of the index register (H)
is not stacked automatically. If the interrupt service routine modifies H,
then the user must stack and unstack H using the push H onto stack
(PSHH) and pull H from stack (PULH) instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
Central Processor Unit (CPU)
Arithmetic/Logic Unit (ALU)
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Central Processor Unit (CPU) 77
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual, Motorola document order
number CPU08RM/AD, for a description of the instructions and
addressing modes and more detail about CPU architecture.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
Advance Information MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
78 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
6.6.1 Wait Mode
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
6.6.2 Stop Mode
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
Loading the instruction register with the software interrupt (SWI)
instruction
Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
Central Processor Unit (CPU)
Instruction Set Summary
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0 Advance Information
MOTOROLA Central Processor Unit (CPU) 79
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
Table 6-1. Instruction Set Summary (Sheet 1 of 8)
Source
Form Operation Description Effect