Murata Electronics North America DRWLS1271L DR-WLS1271L-102 User Manual

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Date Submitted	2012-12-17 00:00:00
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Document Title	Microsoft Word - DR-WLS1271L-102 Data Sheet 12-13-12.doc
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Preliminary and RFM Confidential
DR-WLS1271L-102
FCC/IC Certified
WLAN/Bluetooth
Multifunction Module
Data Sheet
www.RFM.com
© 2012 by RF Monolithics, Inc.
Technical support +1.972.448.3700
E-mail: tech_sup@rfm.com
Page 1 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Scope
This specification applies to the IEEE802.11b/g/n WLAN and Bluetooth 4.0 standards.
Interfaces
WLAN:
Bluetooth:
SDIO
UART and PCM
IC and Firmware
WLAN/BT BB/MAC IC:
Front-end IC for WL1271L:
TI WL1271L (PG 3.1)
TriQuint TQM679002A (E 2.6)
Clocks and Compliance
Sleep Clock:
RoHS:
Bluetooth:
Certifications:
External 32.768 kHz oscillator required
This module is compliant with the RoHS directive
Qualified Design Listing: B017989
FCC, and Industry Canada (IC)
For mobile operating conditions (greater than 20 cm to the body) - This equipment complies with FCC
radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed
and operated with minimum distance 20 cm between the radiator and your body. This transmitter must
not be co-located or operating in conjunction with any other antenna or transmitter.
For portable operating conditions (less than 20 cm to the body) - This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment may operate in direct contact with the body of the user under normal operating conditions. This transmitter must not be co-located
or operating in conjunction with any other antenna or transmitter.
Certification testing conducted with Antenna Factor ANT-RAF-RPS 2.4/5 GHz antenna, RSMA connector.
Part Numbers
Module:
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© 2012 by RF Monolithics, Inc.
DR-WLS1271L-102
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Page 2 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Block Diagram
3 8 .4 M H z
F a s t C L K
S lo w
C L K
S D IO
2 .4 G H z
W L A N /B T
W L 1 2 7 1 L
F ro n t E n d
IC a n d R F
F ilte r in g
P C M
U A R T
V IO
D C -D C
C o n v e rte r
D u a l
R e g
V IN
DR-WLS1271L-102 WLAN Features
• WLAN MAC baseband processor and RF transceiver which are IEEE802.11b/g and IEEE802.11n
PICS compliant
• Optimized for ultra-low current consumption in all operating modes
• Accepts 19.2, 26, 38.4, 52 MHz reference clock inputs for easy integration into cellular handsets, etc.
• IEEE Standard 802.11d, e, h, i, k, r, PICS compliant
• Support for Cisco Client eXtensions (CCX) standard
• Serial debug interface
• Secure Digital Input/Output (SDIO) host interface
• Medium Access Controller (MAC)
– Embedded ARM™ central processing unit (CPU)
– Hardware-based encryption/decryption using 64-, 128- or 256-bit WEP, TKIP or AES keys
– Supports Wi-Fi protected access (WPA and WPA2.0) and IEEE Standard 802.11i, including
hardware accelerated Advanced Encryption Standard (AES)]
– Designed to work with IEEE Std 802.1x for Virtual Private Network (VPN) solutions
• Baseband Processor
– IEEE Std 802.11n single-stream data rates (MCS0-7) and SGI support
• 2.4 GHz Radio
– Digital Radio Processor (DRP) implementation
– Integrated LNA
– Supports IEEE Std 802.11b, g, b/g and 802.11n
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© 2012 by RF Monolithics, Inc.
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E-mail: tech_sup@rfm.com
Page 3 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
DR-WLS1271L-102 Bluetooth Features
• V4.0 + EDR, Power Class 1.5 + BLE
• Bluetooth Qualified Design Listing: B017988
• BT Enhanced Data Rates - 2 and 3 Mbps
• Enhanced UART host interface
• Very low power consumption
• On-chip Embedded radio
– Integrated 2.4 GHz RF transceiver
– All digital PLL transmitter with digitally controlled oscillator
– Near-zero IF architecture
– On-chip TX/RX switch
– Support for Class-1.5 applications
• Embedded ARM microprocessor system
– High rate four wire UART HCI (H4) and three wire UART HCI (H5)
– Automatic clock-detection mechanism
• Flexible PCM interface - full flexibility for data order, sampling and positioning
• Temperature detection and compensation mechanism ensures minimal variation in the RF performance
over the entire operating temperature range
• Low-power scan achieves paging and inquiry scans at 1/3 normal power
• Digital Radio Processor (DRP) single-ended 50 ohm I/O for easy RF interfacing
• Patch trap mechanism and reserved RAM enables easy bug fixes
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Page 4 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
• Advance Audio Interfaces and capabilities
– A2DP support
– A2DP internal loopback
– Wide-band speech support
– On board SBC encoder/decoder - offloads host for A2DP and wide-band speech processing
– Full support for Bluetooth low energy (BLE) standard. BLE can operate in parallel with standard
Bluetooth function.
WLAN Functional Blocks
The DR-WLS1271L-102 WLAN architecture includes a digital radio processor and a point-to-multipoint
baseband core function. The architecture is based on a single-processor ARM core. The device includes
on-chip peripherals to enable easy communication between a host system and the WLAN core function.
WLAN SDIO Transport Layer
SDIO is the WLAN host interface in the DR-WLS1271L-102. This interface is a standard SDIO interface
(SDIO Version 2.0), supporting a maximum clock rate of 26 MHz. The DR-WLS1271L-102 SDIO also
supports the following features:
• 4-bit data bus
• Functions number 0 and 2
• Multi-Block data transfer
• The SDIO interface is used for WLAN. The WLAN block uses function 2. Function 0 is used for the
common I/O area.
WLAN MAC
The DR-WLS1271L-102 MAC implements the IEEE standard 802.11 MAC sub-layer using both dedicated
hardware and embedded firmware. The MAC hardware implements real-time functions, including access
protocol management, encryption and decryption.
WLAN Baseband Processor
The DR-WLS1271L-102 baseband processor sits between the on-chip MAC and the radio. The DRWLS1271L-102 baseband processor implements the IEEE 802.11b/g/n PHY sub-layers and has been
optimized to perform well in conditions of high multipath and noise.
WLAN RF Radio
The DR-WLS1271L-102 radio is a highly integrated Digital Radio Processor (DRP) designed for
802.11b/g/n applications. The DR-WLS1271L-102 RF interface is a single-band RF front end for 2.4 GHz
802.11b/g/n applications.
BT Functional Blocks
The DR-WLS1271L-102 BT architecture comprises a digital radio processor and a point-to-multipoint
baseband core function. The architecture is based on a single-processor ARM core. The device includes
on-chip peripherals to enable easy communication between a host system and the Bluetooth core function.
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Page 5 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
BT HCI UART Transport Layers
The DR-WLS1271L-102 incorporates one UART module dedicated to the Host Controller Interface (HCI)
transport layer. The HCI interface is used to transport commands, events, ACL and data between the
Bluetooth device and its host using HCI data packets. The DR-WLS1271L-102 supports the following HCI
transport layers, detected automatically when communication starts:
• UART transport layer - HCI four-wire (H4) and HCI three-wire (H5)
• HCI interface has a 256 byte receive buffer
The HCI UART supports most baud rates (including all PC rates) up to a maximum of 4 Mbps. After power-up, the baud rate is set for 115.2 kbps. The maximum baud rate deviation supported is -2.5%, +1.5%.
The baud rate can thereafter be changed with a VS command. The DR-WLS1271L-102 responds with a
Command Complete Event (still at 115.2 kbps), after which the baud rate change takes place. The only
parameter needed is the desired baud rate. HCI hardware includes the following features:
• Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions
• Transmitter underflow detection
• CTR/RTS hardware flow control
BT UART 4-Wire Interface - H4
The interface includes four signals: TXD, RXD, CTS and RTS. Flow control between the host and the
DR-WLS1271L-102 is byte-wise by hardware. Flow control is obtained by the following:
H O S T _ R X
H O S T T X
H o s t
P ro c e s s o r H O S T _ C T S
H O S T _ R T S
H C I_ R X
H C I_ T X
H C I_ C T S
D R -W L S 1 2 7 1 L -1 0 2
H C I_ R T S
When the UART RX buffer of the DR-WLS1271L-102 passes the “flow control” threshold, it sets the
UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high, the
DR-WLS1271L-102 stops transmitting on the interface. In case HCI_CTS is set high in the middle of
transmitting a byte, the DR-WLS1271L-102 finishes transmitting the byte and stops the transmission.
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Page 6 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
BT UART 3-Wire Interface - H5
This interface consists of three signals: TXD, RXD and GND:
HCI_RX Receive Data on the UART Interface
HCI_TX Transmit Data on the UART Interface
GND Ground
XON/XOFF software flow control is normally used.
The DR-WLS1271L-102 also supports a four-wire mode for H5, with RTS/CTS hardware flow control.
Since the same UART module is used for the 3- and 4-wire HCI UART interface, all features supported by
the 4-wire interface are also supported for the 3-wire interface. H5 features:
• Flow control configured with HCI_VS command, software XON/XOFF, hardware (RTS/CTS), or none
• Power management
• Configurable timers for re-transmission management
• CRC
BT Audio CODEC Interface
The CODEC interface is a fully dedicated programmable serial port that provides the logic to interface to
several kinds of PCM codecs. The interface supports:
• Two voice channels
• Master/slave modes
• Coding schemes: μ-Law, A-Law, Linear, Transparent
• Long & short frames
• Different data widths, orders and positions
• UDI profile
• High rate PCM interface for EDR
• Enlarged interface options to support a wider variety of codecs
• PCM bus sharing
PCM Hardware Interface
The PCM interface is one implementation of the codec interface. It contains the following four lines:
• Clock - configurable direction (input or output)
• Frame Sync - configurable direction (input or output)
• Data In - Input
• Data Out - Output/Hi-Z
The DR-WLS1271L-102 device can be either the master of the interface where it generates the clock and
the frame-sync signals, or slave where it receives these two signals. The PCM interface is fully configured
by means of a VS command. For slave mode, clock input frequencies of up to 16 MHz are supported. At
clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the DR-WLS1271L102 can generate any clock frequency between 64 kHz and 4.096 MHz.
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Page 7 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Data Format
The data format is fully configurable:
• The data length can be from 8 to 320 bits, in 1-bit increments, when working with two channels, or up to
640 bits when using 1 channel. The data length can be set independently for each channel.
• The data position within a frame is also configurable with 1-clock (bit) resolution, and can be set independently (relative to the edge of the Frame Sync signal) for each channel.
• The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start
with MSB while Data_Out starts with LSB. Each channel is separately configurable. The inverse bit order
(i.e. LSB first) is supported only for sample sizes up to 24 bits.
• The data in and data out size do not necessarily have to be the same length.
• The Data_Out line is configured as a ‘high-Z’ output between data words. Data_Out can also be set for
permanent high-Z, irrespective of data out. This allows the DR-WLS1271L-102 to be a bus slave in a multi-slave PCM environment. At power up, Data_Out is configured as high-Z.
Frame-Idle Period
The CODEC interface has the capability for frame-idle periods, where the PCM clock can “take a break”
and become ‘0’ at the end of the PCM frame, after all data has been transferred. The DR-WLS1271L-102
supports frame-idle periods both as master and slave of the PCM bus. When DR-WLS1271L-102 is the
master of the interface, the frame-idle period is configurable. There are 2 configurable parameters:
• Clk_Idle_Start - indicates the number of PCM clock cycles from the beginning of the frame till the beginning of the idle period. After Clk_Idle_Start clock cycles, the clock becomes ‘0’.
• Clk_Idle_End - indicates the time from the beginning of the frame till the end of the idle period. This time
is given in multiples of PCM clock periods. The delta between Clk_Idle_Start and Clk_Idle_End is the
clock idle period, e.g., for PCM clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60,
Clk_Idle_End = 90. Between each two-frame sync there are 70 clock cycles (instead of 100). The clock
idle period starts 60 clock cycles after the beginning of the frame and lasts 90-60=30 clock cycles. This
means that the idle period ends 100-90=10 clock cycles before the end of the frame. The data transmission must end prior to the beginning of the idle period.
Audio Encoding
The DR-WLS1271L-102 CODEC interface can use one of four audio coding patterns:
• A-Law (8-bit)
• m-Law (8-bit)
• Linear (8 or 16-bit)
• Transparent
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Page 8 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Mechanical
D R -W L S 1 2 7 1 L -1 0 2 P a c k a g e D r a w in g
S id e
T o p
B o tto m
2 .4 G H z
0 .0 8 0
(2 .0 )
0 .5 0
(1 .3 )
0 .7 3 2
(1 8 .6 )
0 .1 5 (3 .8 )
M a x im u m H e ig h t
0 .1 2 0
(3 .0 )
0 .0 8 0
(2 .0 )
0 .0 8 0
(2 .0 )
4 1
2 7
4 2
0 .1 2 0
(3 .0 )
0 .0 3 0
(0 .8 )
0 .0 4 0
(1 .0 )
0 .5 5 6
(1 4 .1 )
0 .1 6 0
(4 .1 )
0 .0 3 0
(0 .8 )
0 .2 6 9
(6 .8 )
4 0
5 1
0 .5 2 9
(1 3 .4 )
5 2
0 .4 6 9
(1 1 .9 )
0 .0 3 0
(0 .8 )
0 .0 2 8
(0 .7 )
5 0
1 4
0 .1 0 4
(2 .7 )
0 .3 8 0
(9 .7 )
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© 2012 by RF Monolithics, Inc.
0 .0 4 0
(1 .0 )
2 6
2 8
V ie w fr o m T o p
D im e n s io n s in in c h e s (m m )
1 5
0 .0 3 0
(0 .8 )
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1 6
0 .0 9 2
(2 .3 )
0 .0 2 8
(0 .7 )
Page 9 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Module Terminal Descriptions
Num
Terminal Name
Type
System
IC Terminal Connection
Description
PCM SYNC
I/O
BT
WL1271L
AUD_FSYNC
PCM I/F
PCM CLK
I/O
BT
WL1271L
AUD_CLK
PCM I/F
PCM OUT
I/O
BT
WL1271L
AUD_OUT
PCM I/F
PCM IN
I/O
BT
WL1271L
AUD_IN
PCM I/F
HOST WAKE
I/O
BT
WL1271L
BT_FUNC5
Host Wake Up
NOT USED
BT ENABLE
BT
WL1271L
BT_EN
Mechanical Connection
BT Enable/Reset
WLAN IRQ
WLAN
WL1271L
WLAN_IRQ
WLAN interrupt request
GND
SOC Ground
10
NOT USED
Mechanical Connection
11
NOT USED
Mechanical Connection
12
NOT USED
Mechanical Connection
13
NOT USED
Mechanical Connection
14
WLAN TX
I/O
WLAN
WL1271L
WL_RS232_TX
15
WLAN RX
I/O
WLAN
WL1271L
WL_RS232_RX
RS232_RX
RS232_TX
16
WLAN EN
WLAN
WL1271L
WL_EN
WLAN Enable/Reset
17
SDIO D2
I/O
WLAN
WL1271L
SDIO_D2
SDIO DATA 2
18
SDIO D1
I/O
WLAN
WL1271L
SDIO_D1
SDIO DATA 1
19
SDIO CMD
I/O
WLAN
WL1271L
SDIO_CMD
20
NOT USED
Mechanical Connection
21
GND
SOC Ground
SDIO CMD
22
SDIO CLK
WLAN
WL1271L
SDIO_CLK
SDIO CLK
23
UART DBG
I/O
WLAN
WL1271L
WL_UART_DBG
WL_UART_DBG
24
SDIO D0
I/O
WLAN
WL1271L
SDIO_D0
25
NOT USED
26
SDIO D3
I/O
WLAN
WL1271L
SDIO_D3
27
BT UART DBG
I/O
BT
WL1271L
BT_UART_DBG
28
NOT USED
WL1271L
SLOWCLK
WL1271L
BT_FUNC2
SDIO DATA 0
Mechanical Connection
SDIO DATA 3
BT_UART_DBG, connect to
TP for software debug
Mechanical Connection
29
NOT USED
30
SLEEP CLOCK
31
BT WAKE
I/O
32
NOT USED
Mechanical Connection
33
NOT USED
Mechanical Connection
34
NOT USED
Mechanical Connection
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Mechanical Connection
BT
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SLEEP_CLK Input
BT_WU/BT
Page 10 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Num
Terminal Name
Type
System
IC Terminal Connection
35
BT CTS
I/O
BT
36
NOT USED
37
BT RTS
38
NOT USED
39
BT TX
40
NOT USED
41
BT RX
42
GND
SOC Ground
43
GND
SOC Ground
44
GND
SOC Ground
45
GND
WL1271L
HCI_CTS
Description
BT UART CTS
Mechanical Connection
I/O
BT
WL1271L
HCI_RTS
I/O
BT
WL1271L
HCI_TX
BT UART RTS
Mechanical Connection
BT UART TX
Mechanical Connection
I/O
BT
WL1271L
HCI_RX
BT UART RX
SOC Ground
46
VBAT IN
47
GND
SOC Ground
48
GND
49
2.4 GHZ ANT
50
GND
SOC Ground
RF receiver input
RF transmitter output
SOC Ground
51
GND
SOC Ground
52
GND
SOC Ground
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© 2012 by RF Monolithics, Inc.
I/O
SOC
WL1271L,
TPS62601
PMS_VBAT, VIN
WLAN
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Power supply input
Page 11 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Absolute Maximum Ratings
Ratings
Storage Temperature
Supply Voltage
Minimum
Maximum
Units
-40
+85
°C
VBAT
-0.5
+4.8
VIO
-0.5
+2.1
Minimum
Typical
Maximum
Units
-40
+25
+85
°C
Operating Conditions
Specifications
Temperature
1, 2
2.7
3.6
4.8
1.70
1.80
1.90
Condition
Minimum
Maximum
Units
Logic High Input Voltage (VDD_IO = IO supply for ring)
Default
0.70 * VIO
VIO
Logic Low Input Voltage
Default
0.35 * VIO
Supply Voltage
VBAT
VIO
Digital I/O Terminal Specifications
Specifications
Logic High Output Voltage
Logic Low Output Voltage
4 mA
VIO - 0.450
VIO
1 mA
VIO - 0.112
VIO
0.3 mA
VIO - 0.033
VIO
4 mA
0.450
1 mA
0.112
0.09 mA
0.010
Notes:
1.
2.
3.
The device can be reliably operated for 5,000 active WLAN hours cumulative at T ambient of 85 °C.
BIP (calibration) must be run to achieve full power output when temperatures changes more than 20 °C
from the last BIP.
VIO voltage derived from regulator on module.
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Page 12 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
External Slow Clock Requirements
Specifications
Condition
Minimum
Slow Clock Frequency
Slow Clock Accuracy
Clock Transition Time, Tr/Tf 10 to 90%
Maximum
Units
±150
ppm
32.768
WLAN
Tr/Tf
Clock Duty Cycle
Input Voltage Limits
Typical
Square Wave,
DC-coupled
kHz
100
ns
30
50
70
0.65 * VIO
VIO
0.35 * VIO
Input Impedance
MΩ
Input Capacitance
pF
Rise and Fall Time
100
ns
Phase Noise
-125
dBc/Hz
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Page 13 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
WLAN Power-up Sequence
V B A T , 2 .3 to 5 .5 V
V IO , 1 .8 V
S L O W C L K
W L _ E N
< 1 0 0 µ s
D C _ R E Q
D C 2 D C , 1 .8 V
C L K _ R E Q
S D IO
C L K
W L A N _ IR Q
R E F
T 1
T 2
W A K E
U P
The following sequence describes device power up from shutdown. Only the WLAN core is enabled; the BT core
is disabled.
1. No signals are allowed on the IO pins if no IO power supplied, because the IOs are not fail-safe. Exceptions are CLQ_REQ,
SLEEP_CLK (SLOWCLK), and XTALP, which are fail-safe and can tolerate external voltages with no VIO and DC2DC.
2. VBAT,VIO and SLEEP_CLK must be available before WLAN_EN (WL_EN).
3. TWAKE-UP = T1+T2. The duration of T1 is the time from WLAN_EN high until FREF is valid for DR-WLS1271L-102 (55 ms typical).
The duration of T2 depends on:
- Operating system
- Host enumeration for the SDIO
- PLL configuration
- Firmware download
- Releasing the core from reset
- Firmware initialization
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Page 14 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
WLAN Power-down Sequence
V B A T , 2 .3 to 5 .5 V
V IO , 1 .8 V
S L O W C L K
W L _ E N
D C _ R E Q
D C 2 D C , 1 .8 V
C L K _ R E Q
S D IO
C L K
W L A N _ IR Q
1. DC_REQ of DR-WLS1271L-102 will go low only if WLAN is the only core working. If BT is working, it will stay high.
2. CLK_REQ will go low only if WLAN is the only core working. If BT is working it will stay high.
3. WLAN_EN must remain de-asserted for at least 64 ms before it is re-asserted.
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Page 15 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Bluetooth Power-up Sequence
V B A T
V IO
S L E E P C L O C K
B T _ R E S E T X
D C _ R E Q
(in te r n a l)
< 1 0 0 µ s
D C 2 D C
(1 .8 V )
C L K _ R E Q
R E F
U A R T _ R T S
T 1
W A K E
U P
The following sequence describes device power-up from shutdown. Only the BT core is enabled; the WLAN core
is disabled.
1. No signals are allowed on the IO pins if no IO power supplied, because the IOs are not failsafe. Exceptions are CLK_REQ,
SLEEP_CLK, XTALP and AUD_xxx, which are failsafe and can tolerate external voltages with no VIO and DC2DC.
2. VIO and SLEEP_CLK must be stable before releasing BT_EN.
3. Fast clock must be stable a maximum 55 ms after BT_EN goes HIGH.
4. The duration of T1 is defined as the time from BT_EN = high until Fref is valid (55 ms typical).
5. The duration of TWAKE-UP is defined as the time from the rising edge of BT_EN to the falling edge of HCI_RTS (70 ms typical).
6. The DR-WLS1271L-102 indicates completion of BT power up sequence by asserting HCI_RTS low. This occurs up to 100 ms
after BT_EN goes high.
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© 2012 by RF Monolithics, Inc.
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Page 16 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Bluetooth Power-down Sequence
V B A T , 2 .3 to 5 .5 V
V IO , 1 .8 V
S L O W C L K
B T _ E N
D C _ R E Q
D C 2 D C , 1 .8 V
C L K _ R E Q
H C I_ R T S
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B lu e to o th in a c tiv e
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Page 17 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Host Interface Combination
WLAN
BT
SDIO
UART
Remarks
All core functions support automatic host-interface recognition. The user does not need to configure it in
advance.
SDIO Interface Clock Switching Characteristics, 25 pF Load Capacitance
Symbol
Parameter
FCLOCK
DC
Minimum
Maximum
Clock Frequency
25
Units
MHz
Low/High Duty Cycle
40
60
tWL
Pulse Duration, Clock Low
10
ns
tWH
Pulse Duration, Clock High
10
ns
tTLH
Clock Rise Time
4.3
tTHL
Clock Fall Time
tISU
Set-up Time, Input Valid before Clock
tIH
ns
3.5
ns
ns
Hold Time, Input Valid after Clock
tODLY1
Delay Time, Clock Falling Edge to Output Valid
14
ns
ns
tODLY2
Delay Time, Clock Falling Edge to Output Invalid
14
ns
SDIO Timing
W L
W H
0.7
C lo c k
0.2
T L H
T H L
IS U
In p u t
O D L Y 1
O u tp u t
O D L Y 2
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IH
IL
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© 2012 by RF Monolithics, Inc.
IL
IH
IH
O H
O L
Page 18 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
SDIO Interface Read
C M D
(In p u t/O u tp u t)
C R
tCC
tRC
tAC
C o m m a n d
R e a d
tCR
R C
C a rd R e s p o n s e
R e a d C o m m a n d
S D 0 -S D 3
(In p u t/O u tp u t)
Symbol
C C
A C
Parameter
Delay Time, Assign Relative Address or
Data Transfer Mode; Read command CMD invalid
to card response CMD valid
Delay Time, CMD command invalid to
CMD command valid
Delay Time, CMD response invalid to
CMD command valid
Access Time, CMD command invalid to
SD0-SD3 read data valid
Minimum
Maximum
Units
64
Clock Cycles
Clock Cycles
Clock Cycles
Clock Cycles
SDIO Interface Write
C M D
(In p u t/O u tp u t)
C a rd R e s p o n s e
S D 0 -S D 3
(In p u t/O u tp u t)
Symbol
Td1
Td2
W r ite
Parameter
Delay Time, CMD Card Response Invalid to
SD0-SD3 Write Data Valid
Delay Time, SD0-SD3 Write Data Invalid to
CRC Status Valid
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© 2012 by RF Monolithics, Inc.
C R C
d 1
B u s y
S ta tu s
d 2
Minimum
Maximum
Units
Clock Cycles
Clock Cycles
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Page 19 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
BT Audio CODEC/PCM Interface Switching Characteristics
c lk
A U D _ C L K
is
ih
A U D _ IN /F S Y N C _ IN
o p
A U D _ O U T /F S Y N C _ O U T
PCM Master
Symbol
TCLK
Parameter
Clock Period
Minimum
Maximum
Units
166.7 (6 MHz)
15625 (64 kHz)
ns
TW
High/Low Pulse Width
tis
AUD_IN Setup Time
25
50% of TCLK
tih
AUD_IN Hold Time
top
AUD_OUT Propagation Time, 40 pF Load
10
top
FSYNC_OUT Propagation Time, 40 pF Load
10
Minimum
Maximum
ns
PCM Slave
Symbol
TCLK
Parameter
Clock Period
62.5 (16 MHz)
TW
High/Low Pulse Width
tis
AUD_IN Setup Time
tih
AUD_IN Hold Time
tis
FSYNC_IN Setup Time
tih
FSYNC_IN Hold Time
top
AUD_OUT Propagation Time, 40 pF Load
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© 2012 by RF Monolithics, Inc.
Units
ns
40% of TCLK
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ns
21
Page 20 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
UART Interface Timing
H C I_ R T S
H C I_ R X
H C I_ C T S
H C I_ T X
1 0 b its
Symbol
Parameter
Condition
Minimum
Typical
Maximum
Units
BR
Baud Rate
Most Standard Rates
37.5
4000
kbps
t5, t7
Baud Rate Accuracy
Receive/Transmit
-2.5
1.5
µs
byte
t3
CTS Low to TX_DATA
t4
CTS High to TX_DATA
t6
CTS High Pulse Width
bit
t1
RTS Low to RX_DATA ON
µs
t2
RTS High to RX_DATA OFF
16
byte
Hardware Flow Control
Interrupt set to 1/4 FIFO
DR-WLS1271L-102 IRQ Operation
1. The default state of the WLAN_IRQ prior to firmware initialization is 0.
2. During firmware initialization, the WLAN_IRQ is configured by the SDIO module; a WLAN_IRQ
changes its state to 1
3. A WLAN firmware interrupt is handled as follows:
(a) The WLAN firmware creates an Interrupt-to-Host, indicated by a 1-to-0 transition on the WLAN_IRQ
line (host must be configured as active-low or falling-edge detect).
(b) After the host is available, depending on the interrupt priority and other host tasks, it masks the
firmware interrupt. The WLAN_IRQ line returns to 1 (0-to-1 transition on the WLAN_IRQ line).
(c) The host reads the internal register status to determine the interrupt sources - the register is cleared
after the read
(d) The host processes in sequence all the interrupts read from this register
(e) The host unmasks the firmware interrupts.
4. The host is ready to receive another interrupt from the WLAN device.
DR-WLS1271L-102 BT function Low Power Mode Protocols
The DR-WLS1271L-102 device includes a mechanism that handles the transition between operating
mode and deep sleep low-power mode. The protocol is done via the UART and is known as eHCILL (enhanced HCI Low Level) power management protocol. This protocol is backward compatible with the
BRF6150/ BRF6300/BRF6350/WL1273 HCILL Protocol, so a Host that implements the HCILL for
BRF6150/ BRF6350 does not need to change anything in order to work with the DR-WLS1271L-102. The
"Enhanced" portion of the HCILL introduces changes that allow a simpler host implementation of this protocol. See BT-SW-0024 (BRF Enhanced HCILL 4 wire Power Management Protocol). In addition to the
HCILL protocol, the WL1273 also supports the power management schemes inherent in the UART H5
transport layers.
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Page 21 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
DC and RF Characteristics for IEEE 802.11b, 11 Mbps
Conditions: 25 C, VBAT=3.6 V, VDDIO=1.8 V, TCXO Fast Clock Source
System Specifications
Data
Standard
IEEE802.11b
Mode
DSSS/CCK
Frequency
2412 to 2462 MHz
Data Rate
1, 2, 5.5, 11 Mbps
DC Specifications
Minimum
Typical
Maximum
Units
DC Current:
TX Mode
250
320
mA
RX Mode
100
150
mA
Sleep Mode
100
200
µA
Minimum
Typical
Maximum
Units
14
16
18
dBm
1st Sidelobes
-40
-30
dBr
2nd Sidelobes
-55
-50
dBr
Transmitter Specifications
RF Output Power
Spectrum Mask:
Power-on and Power-off Ramp
0.1
2.0
µs
15
37
dB
10
35
0.03 to 1.00 GHz
-80
-36
dBm
1.00 to 12.75 GHz
-60
-30
dBm
1.80 to 1.90 GHz
-80
-47
dBm
5.15 to 5.30 GHz
-80
-47
dBm
Minimum
Typical
Maximum
Units
-87
-76
dBm
-10
dBm
RF Carrier Suppression
Modulation Accuracy (EVM)
Spurious Emissions:
Receiver Specifications
Sensitivity:
Minimum Input Level, 11 Mbps, FER  8%
Maximum Input Level, FER  8%
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Page 22 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
DC and RF Characteristics for IEEE 802.11g Operation, 54 Mbps
Conditions: 25 C, VBAT=3.6 V, VDDIO=1.8 V, TCXO Fast Clock Source
System Specifications
Data
Standard
IEEE802.11g
Mode
OFDM
Frequency
2412 to 2462 MHz
Data Rate
6, 9, 12, 18, 24, 36, 48, 54 Mbps
DC Specifications
Minimum
Typical
Maximum
Units
DC Current:
TX Mode
180
245
mA
RX Mode
100
150
mA
Sleep Mode
100
200
µA
Minimum
Typical
Maximum
Units
11
13
15
dBm
at fC ±11 MHz
-30
-20
dBr
at fC ±20 MHz
-33
-28
dBr
at fC ±30 MHz
-45
-40
dBr
0.03 to 1.00 GHz
-80
-36
dBm
1.00 to 12.75 GHz
-65
-30
dBm
1.80 to 1.90 GHz
-80
-47
dBm
5.15 to 5.30 GHz
-80
-47
dBm
-30
-25
dB
Minimum
Typical
Maximum
Units
-73
-65
dBm
-20
-4
dBm
Transmitter Specifications
RF Output Power
Spectrum Mask:
Spurious Emissions:
Constellation Error (EVM)
Receiver Specifications
Sensitivity:
Minimum Input Level, 54 Mbps, PER  10%
Maximum Input Level, PER  10%
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Page 23 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
DC and RF Characteristics for IEEE 802.11n Operation, 65 Mbps (MCS7)
Conditions: 25 C, VBAT=3.6 V, VDDIO=1.8 V, TCXO Fast Clock Source
System Specifications
Data
Standard
IEEE802.11n-2.4G
Mode
OFDM
Frequency
2412 to 2462 MHz
Data Rate
6.5, 13, 19.5, 26, 39, 52, 58.5, 65 Mbps
DC Specifications
Minimum
Typical
Maximum
Units
DC Current:
TX Mode
180
245
mA
RX Mode
100
150
mA
Sleep Mode
100
200
µA
Minimum
Typical
Maximum
Units
10
12
14
dBm
at fC ±11 MHz
-30
-20
dBr
at fC ±20 MHz
-35
-28
dBr
at fC ±30 MHz
-50
-45
dBr
-80
-28
dB
0.03 to 1.00 GHz
-80
-36
dBm
1.00 to 12.75 GHz
-65
-30
dBm
1.80 to 1.90 GHz
-80
-47
dBm
-80
-47
dBm
Minimum
Typical
Maximum
Units
-67
-64
dBm
-20
-5
dBm
Transmitter Specifications
RF Output Power
Spectrum Mask:
Constellation Error (EVM)
Spurious Emissions:
5.15 to 5.30 GHz
Receiver Specifications
Sensitivity:
Minimum Input Level, 65 Mbps, PER  10%
Maximum Input Level, PER  10%
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Page 24 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
DC and RF Characteristics for Bluetooth Operation
Conditions: 25 C, VBAT=3.6 V, VDDIO=1.8 V, TCXO Fast Clock Source
System Specifications
Data
Bluetooth Standard
Version 4.0
Channel Spacing
1 MHz
Number of RF Channels
79
Power Class
Frequency hopping spread spectrum, pseudorandom hopping
pattern, time division multiple access on transmit or receive,
frequency hop after each RX/TX cycle
Operating Mode
DC Specifications
Minimum
Typical
Maximum
Units
DH1 Packet, 50% RX/TX Slot Duty Cycle
37
60
mA
DH3 Packet, 50% RX/TX Slot Duty Cycle
46
60
mA
DH5 Packet, 50% RX/TX Slot Duty Cycle
48
60
mA
Minimum
Typical
Maximum
Units
4.5
8.0
DC Current:
Transmitter Specifications
RF Output Power
Frequency Range, RX/TX
2400 to 2483.5
-20 dB Bandwidth
0.8
dBm
MHz
1.0
MHz
Adjacent Channel Power :
M-N=2
-45
-20
dBm
M-N ≥3
-46
-40
dBm
Modulation  f1 average
140
158
175
kHz
Modulation  f2 maximum
115
132
kHz
Modulation  f2 average /  f1 average
0.8
0.9
Modulation Characteristics:
Carrier Frequency Drift:
1 Slot
-25
+25
kHz
3 Slots
-40
+40
kHz
5 Slots
-40
+40
kHz
-20
+20
kHz/50 µs
0.03 to 1.00 GHz
-58
-36
dBm
1.00 to 12.75 GHz
-40
-30
dBm
1.80 to 1.90 GHz
80
-47
dBm
80
-47
dBm
-4
-0.2
dB
Maximum Frequency Drift Rate
Spurious Emissions:
5.15 to 5.30 GHz
ERD Relative Power, /4-DPQSK and 8DPSK
EDR Carrier Frequency Stability and Modulation Accuracy:
/4-DPQSK and 8DPSK
-75
+75
kHz
/4-DPQSK and 8DPSK
-10
+10
kHz
/4-DPQSK and 8DPSK
kHz
-75
+75
RMS DEVM, /4-DPQSK
20
99% DEVM, /4-DPQSK
10
30
Peak DEVM, /4-DPQSK
14
35
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Page 25 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Transmitter Specifications (continued)
RMS DEVM, 8DPSK
Minimum
Typical
Maximum
Units
13
99% DEVM, 8DPSK
10
20
Peak DEVM, 8DPSK
15
25
Receiver Specifications
Minimum
Typical
Maximum
Units
2402 MHz
-90
-70
dBm
2441 MHz
-90
-70
dBm
2480 MHz
-90
-70
dBm
Co-channel ratio, -60 dBm Input
11
dB
1 MHz ratio, -60 dBm Input
-9
dB
2 MHz ratio, -60 dBm Input
-46
-30
dB
3 MHz ratio, -67 dBm Input
-48
-40
dB
-30
-20
dB
30 to 2000 MHz
-10
-8
dBm
2000 to 2400 MHz
-27
dBm
2500 to 3000 MHz
-27
dBm
3000 to 12750 MHz
-10
-5
dBm
Intermodulation Performance, -64 dBm Input, BER  0.1%
-39
-30
dBm
Maximum Input Level
-20
10
dBm
Sensitivity, BER  0.1%:
C/I Performance, BER  0.1% :
Image ±1 MHz ratio, -67 dBm input
Blocking Performance, BER  0.1% :
EDR Sensitivity, BER  0.01%:
/4-DQPSK
-90
-70
dBm
8DPSK
-84
-70
dBm
1. Up to three spurious responses within Bluetooth limits are allowed.
2. Up to five spurious responses within Bluetooth limits are allowed.
3. Up to twenty-four spurious responses within Bluetooth limits are allowed.
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Page 26 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Storage Conditions
This product should be stored without opening the packing in an ambient temperature range of 5 to 35 C
and humidity range from 20 to 70% RH, and be used within six months of receipt. Packing materials can
be deformed at temperatures above 40 C. If the product is not used six months or more after receipt, its
solderbility should be tested before being used. The product should be stored in non-corrosive gas. Any
excess mechanical shock such as sticking the packing materials with a sharp object or dropping the
product, etc., must be avoided in order not to damage the packing materials. This product is applicable to
MSL3, based on JEDEC Standard J-STD-020.
After the packing is opened, the product should be stored at an ambient temperature below 30 C and at
humidity level less than 60% RH. The product should be used within 168 hours. If the color of the indicator in the packing has changed, the product should be baked before soldering at 125 to 130 C for 24
hours. The products should be baked on the heat-resistant tray, as the tape and reel materials are not
heat-resistant.
Handling Conditions
Use care in handling or transporting this product as excessive stress or mechanical shock can crack or
break the product. Do not touch this product with bare hands as this can result in poor solderability.
Standard PCB Design (Land Pattern and Dimensions)
All the ground terminals should be connected to the ground patterns, and unconnected terminals should
be soldered to unconnected PCB pads for mechanical strength. The best land pattern depends on the
pattern generation method, grounding method, land dimensions, land forming method of the unconnected
terminals and the PCB material and thickness. Contact RFM technical support if you have any questions
about adapting the recommend land pattern to your application specifics or before using non-standard
land dimensions, etc.
Module PCB Placement
This product can be broken by uneven forces from a worn-out chucking locating claw or a suction nozzle.
To prevent damage, be sure to follow the specifications for the maintenance of the chip placer being
used. Be aware that mechanical chucking can damage this product when used for mounting it on a PCB.
Module Soldering
Preheat so that the temperature difference T between the solder and module surface is less than
130 C. If the module is immersed in solvent after mounting, care should be taken to limit the temperature
difference to 100 C. These provisions are necessary to prevent damage due to excessive differential expansion. Contact RFM technical support if you have any questions about soldering methods or are considering other soldering conditions.
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Page 27 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Using a Soldering Iron
A soldering iron of 18 W or less, using a ceramic heater is recommended. The soldering iron tip diameter
should be 3 mm maximum, and the tip temperature should be 350 C or less. The iron contact time at
each terminal should be limited to 3 seconds. The soldering iron should be applied to the land pattern
next to the module terminal, not directly on the module ceramic substrate.
Example Reflow Soldering Profile
Use rosin flux or a weakly active flux with a chlorine content of 0.2% or less by weight.
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Page 28 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Solder Paste Amount and Assembly Standards
Ensure that solder is applied smoothly to a minimum height of 0.2 to 0.5 mm at the end surface of the
module’s external pads. If too much or little solder is applied, the mechanical strength can be insufficient.
P r o p e r A m o u n t o f S o ld e r P a s te
M o d u le
U n a c c e p ta b le A s s e m b ly
C h a s s is
S o ld e r G r o u n d
W ic k in g to M o d u le
P C B
L a n d
S o ld e r
F ille t
H e ig h t
P C B
S u b s tra te
S o ld e r W ic k in g
fr o m W ir e o f
L e a d e d C o m p o n e n t
S o ld e r in g
Ir o n
W ir e L e a d o f
C o m p o n e n t
M o u n te d L a te r
S a tis fa c to r y A s s e m b ly u s in g S o ld e r M a s k in g
S o ld e r M a s k
B lo c k s W ic k in g
to M o d u le
S o ld e r M a s k
B lo c k s W ic k in g to
C o m p o n e n t L e a d
S o ld e r M a s k
Cleaning
This product is moisture sensitive and not suitable for water-based cleaning.
Operational Conditions
This product is designed to work under normal environmental conditions - ambient temperature, humidity
and pressure. If this product is used under the following circumstances, erratic operation or complete failure can occur:
Atmosphere containing a corrosive gas (Cl2, NH3, SOx, NOx, etc.)
Atmosphere containing a combustible or volatile gas
Dusty location
Location with direct sunlight
Location subject to water splashes, high humidity or condensation
If the customer’s application could subject a module to one or more of the above conditions, consult with
RFM technical support before use. Avoid static electricity or excessive voltage while assembling this
module on a PCB or testing it.
Power Supply Voltages
Power supply voltages applied to this product must conform to the specifications for the module. Contact
RFM technical support if you have any questions about power supply requirements.
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Page 29 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12
Preliminary and RFM Confidential
Labeling Requirements
FCC Certification - The WLS1271L-102 hardware has been certified for operation under FCC Part 15
Rules, Section 15.247.
FCC Notice - This device complies with Part 15 of the FCC rules. Operation is subject to the following two
conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
A clearly visible label is required on the outside of the user’s (OEM) enclosure stating the following text:
Contains FCC ID: HSW-WLS1271L-102
Contains IC: 4492A-WLS1271L-102
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must accept
any interference received, including interference that may cause undesired operation.
WARNING: This device operates under Part 15 of the FCC rules. Any modification to this device, not
expressly authorized by RFM, Inc., may void the user’s authority to operate this device.
This apparatus complies with Health Canada’s Safety Code 6 / IC RSS 210.
IC RSS-210 Notice - Operation is subject to the following two conditions: (1) this device may not cause
interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.
ICES-003
This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus
as set out in the radio interference regulations of Industry Canada.
Le present appareil numerique n’emet pas de bruits radioelectriques depassant les limites applicables
aux appareils numeriques de Classe B prescrites dans le reglement sur le brouillage radioelectrique
edicte par Industrie Canada.
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Page 30 of 30
DR-WSL1271L-102 Data Sheet - 12/13/12

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Create Date                     : 2012:12:13 13:28:58-06:00
Format                          : application/pdf
Title                           : Microsoft Word - DR-WLS1271L-102 Data Sheet 12-13-12.doc
Creator                         : Fperkins
Document ID                     : uuid:d9d5dc66-e8fe-40e3-b2bd-0dbd3646812b
Instance ID                     : uuid:556bb324-f5be-4fcd-822d-cde3d52513c7
Page Count                      : 30
Author                          : Fperkins

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