National Instruments Ni Cdaq 9172 Users Manual User Guide And Specifications

2015-02-05

• NI cDAQ-9172 User Guide and Specifications
• Figure 1. NI cDAQ-9172
• Safety Guidelines
  • Safety Guidelines for Hazardous Voltages
• Installing the NI cDAQ-9172
  • Figure 2. NI cDAQ-9172 with Dimensions in Millimeters (Inches)
  • Mounting the NI cDAQ-9172
    • NI 9901 Desktop Mounting Kit
    • Figure 3. NI 9901 Desktop Mounting Kit
    • Mounting the NI 9910 DIN-Rail Kit
    • Figure 4. DIN-Rail Dimensions and Installation on the NI cDAQ-9172
    • Mounting the NI 9905 Panel Mount Kit
    • Figure 5. Panel Mount Dimensions and Installation on the NI cDAQ-9172
• Setting Up the NI cDAQ-9172
  • Figure 6. Ring Lug Attached to Ground Terminal
  • Figure 7. cDAQ Chassis With Secured Cables
• Understanding LED Indications
  • Active LED
    • Table 1. Active LED
  • Ready LED
    • Table 2. Ready LED
• Using the NI cDAQ-9172
  • Figure 8. NI cDAQ-9172 Block Diagram
  • C Series I/0 Modules
  • Correlated vs. Static DIO Modules
  • cDAQ Module Interface
  • USB-STC2
    • AI and AO Sample Timing
    • Triggering Modes
    • Independent Data Streams
    • PFI Signals
    • Flexible Counter/Timers
• Analog Input
  • Analog Input Triggering
    • AI Start Trigger Signal
    • AI Reference Trigger Signal
    • Figure 9. Reference Trigger Final Buffer
    • AI Pause Trigger Signal
  • Analog Input Timing Signals
    • AI Sample Clock
    • Figure 10. Sample Clock Timing Options
    • AI Sample Clock Timebase
    • Convert Behavior For Analog Input Modules
    • Figure 11. Sample Clock Timing Example
  • Getting Started with AI Applications in Software
• Analog Output
  • Analog Output Data Generation Methods
    • Software-Timed Generations
    • Hardware-Timed Generations
  • Analog Output Triggering
  • Analog Output Timing Signals
    • AO Sample Clock
    • Figure 12. Analog Output Timing Options
    • AO Start Trigger Signal
    • AO Pause Trigger Signal
    • Figure 13. ao/PauseTrigger with the Onboard Clock Source
    • Figure 14. ao/PauseTrigger with Other Signal Source
  • Minimizing Glitches on the Output Signal
  • Getting Started with AO Applications in Software
• Digital I/O
  • Correlated vs. Static DIO Modules
    • Table 3. Digital Module Slot Features (Continued)
  • Static DIO
  • Digital Waveform Acquisition (Correlated Input)
    • DI Sample Clock Signal
  • Digital Waveform Generation (Correlated Output)
    • Buffered Digital Waveform Generation
  • Change Detection Event
    • Routing Change Detection Event to an Output Terminal
  • Change Detection Acquisition
    • Nonbuffered Change Detection Acquisition
    • Buffered Change Detection Acquisition
  • Digital Input/Output Configuration for NI 9401
• PFI
• Counters
  • Figure 15. NI cDAQ-9172 Counters
  • Counter Input Applications
    • Counting Edges
    • Figure 16. Single-Point (On-Demand) Edge Counting
    • Figure 17. Single-Point (On-Demand) Edge Counting with Pause Trigger
    • Figure 18. Buffered (Sample Clock) Edge Counting
    • Pulse-Width Measurement
    • Figure 19. Single Pulse-Width Measurement
    • Figure 20. Buffered Pulse-Width Measurement
    • Period Measurement
    • Figure 21. Single Period Measurement
    • Figure 22. Buffered Period Measurement
    • Semi-Period Measurement
    • Figure 23. Buffered Semi-Period Measurement
    • Frequency Measurement
    • Figure 24. Frequency Measurement-Method 1
    • Figure 25. Frequency Measurement-Method 1b
    • Figure 26. Frequency Measurement-Method 2
    • Figure 27. Frequency Measurement-Method 3
    • Table 4. Frequency Measurement Method 1
    • Table 5. Frequency Measurement Method Comparison
    • Position Measurement
    • Figure 28. X1 Encoding
    • Figure 29. X2 Encoding
    • Figure 30. X4 Encoding
    • Figure 31. Channel Z Reload with X4 Decoding
    • Figure 32. Measurements Using Two Pulse Encoders
    • Two-Signal Edge-Separation Measurement
    • Figure 33. Single Two-Signal Edge-Separation Measurement
    • Figure 34. Buffered Two-Signal Edge-Separation Measurement
  • Counter Output Applications
    • Simple Pulse Generation
    • Figure 35. Single Pulse Generation
    • Figure 36. Single Pulse Generation with Start Trigger
    • Figure 37. Retriggerable Single Pulse Generation
    • Pulse Train Generation
    • Figure 38. Continuous Pulse Train Generation
    • Frequency Generation
    • Figure 39. Frequency Generator Block Diagram
    • Figure 40. Frequency Generator Output Waveform
    • Frequency Division
  • Counter Timing Signals
    • Counter n Source Signal
    • Table 6. Counter Applications and Counter n Source
    • Counter n Gate Signal
    • Counter n Aux Signal
    • Counter n A, Counter n B, and Counter n Z Signals
    • Counter n Up_Down Signal
    • Counter n HW Arm Signal
    • Counter n Internal Output and Counter n TC Signals
    • Frequency Output Signal
  • Default Counter/Timer Routing
  • Counter Triggering
    • Arm Start Trigger
    • Start Trigger
    • Pause Trigger
  • Other Counter Features
    • Cascading Counters
    • Counter Filters
    • Table 7. Counter Input Filters
    • Figure 41. Filter Example
    • Prescaling
    • Figure 42. Prescaling
    • Duplicate Count Prevention
    • Figure 43. Duplicate Count Prevention Example
    • Figure 44. Duplicate Count Example
    • Figure 45. Duplicate Count Prevention Example
    • Synchronization Modes
    • Table 8. Synchronization Mode Conditions
    • Figure 46. 80 MHz Source Mode
    • Figure 47. Other Internal Source Mode
    • Figure 48. External Source Model
• Digital Routing and Clock Generation
  • Clock Routing
    • Figure 49. NI cDAQ-9172 Clock Routing Circuitry
    • 80 MHz Timebase
    • 20 MHz Timebase
    • 100 kHz Timebase
• Specifications
  • Analog Input
  • Analog Output
  • Digital Waveform Characteristics (Slots 1 through 4 Only)
  • PFI Characteristics (Slots 5 and 6 Only)1
  • General-Purpose Counter/Timers (Slots 5 and 6 Only)
  • Frequency Generator (Slots 5 and 6 Only)
  • External Digital Triggers (Slots 5 and 6 or with Some AI Modules)
  • Module I/O States
  • Power Requirements
  • Bus Interface
  • Physical Characteristics
  • Safety Standards
  • Environmental
  • Shock and Vibration
  • Electromagnetic Compatibility
  • CE Compliance
  • Waste Electrical and Electronic Equipment (WEEE)
• Where to Go for Support