000 0081 01_CMOS_Family_Library_Schematic_Symbols_Aug86 01 CMOS Family Library Schematic Symbols Aug86
000-0081-01_CMOS_Family_Library_Schematic_Symbols_Aug86 000-0081-01_CMOS_Family_Library_Schematic_Symbols_Aug86
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August 1986
(
000-0081-01
ii
COPYRIGHT
Copyright (c) 1986 by Personal CAD Systems, Inc.
(P·CAD).
(
All rights reserved. No part of this publication may be
reproduced, stored in a retrieval system, or transmitted, in
any form or by any means, electronic, mechanical,
photocopying, recording, or otherwise, without the prior
written permission of Personal CAD Systems, Inc.
\
/
Personal CAD Systems, Inc. provides this manual "as is"
without warranty of any kind, either expressed or implied,
including, but not limited to, the implied warranties of
merchantability and fitness for a particular purpose. P-CAD
may make improvements and/or changes in the product(s)
and/or the program(s) described in this manual at any time
and without notice.
Although P-CAD has gone to great effort to verify the
integrity of the information herein, this publication could
contain technical inaccuracies or typographical errors.
Changes are periodically made to the information herein.
These changes will be incorporated in new editions of this
publication.
TRADEMARKS
P-CAD, PC-CAPS, PC-CARDS, PC-LOGS, PC-BACK, PC-DRC/NLC,
PC-DRILL, PC-FORM, PC-LINK, PC-MODEL, PC-NODES, PC-PACK,
PC-PHOTO, PC-PLACE, PC-PLOTS, PC-PRINT, PC-ROUTE, POSTSIM,
PREPACK, and PRESIM are trademarks of Personal CAD Systems,
Inc. (P - CAD) .
Universal Semiconductor is a registered trademark of
Universal Semiconductor, Inc.
Motorola is a registered trademark of Motorola, Inc.
COS/MOS, QMOS, and RCA are registered trademarks of RCA,
Inc.
000-0081-01
o
CONTENTS
OVERVIEW
CREATING A OESIGN ••••• ,"
.. , .• ,.".
" ••
< c . " " , ••
Layer Structure " •... " . . . . . """'" .... " ..
Drawing Sheets .,.,.,.,.,,.,,,'",,, ... ,
Components ..• ' •.• """,.,,'"
", , , , , . " ,
GENERAL INFORMATION .. ,,'" ........ ,.,'
5
COMPONENT LIST BY SEQUENCE
COMPONENT LIST BY FUNCTION
COMPONENT PIN SEQUENCES
.~~~8~~"~~~
~~~n~r.c~Q~"~~"
COMPONENT PLOTS ","" .. , ......... ".,,"'. ." '" . '" "".
TABLES
1.
2.
LAYS.SYM Layer Structure
LAYS,,5CH Layer Structure
000 0081·01
~7:,
PiC
iv
000·0081-01
Schematic Symbols
OVERVIEW
This manual and the ten CMOS Schematic Symbol Diskettes
comprise the P-CAD CMOS Schematic Symbols Library_ The
library has been developed at the request of our users, and
we welcome any suggestions for improvements or additions_
The library diskettes contain the following files for use
with the PC-CAPS schematic capture program:
•
Component files
•
Layer structure files, LAYS_SYM and LAYS.SCH
•
Standard-size drawing sheet files, ASIZE.SCH through
ESIZE.SCH
•
CMOS.FIL and CMOS.LIB files
CMOS.FIL is a sample text file used as input into PREPACK
to create the binary file CMOS.LIB that contains
packaging information for PC-PACK. Both CMOS.FIL and
CMOS.LIB contain all the components in the CMOS Component
Library. Normal usage is to extract only those
components used in a design and put them in a new .FIL
file for input to PREPACK.
Storage of these files in a practical and efficient
directory structure is discussed in the next section of this
manual. The following section, "Creating a Design", tells
you how to use the files with PC-CAPS.
The remainder of the manual is devoted to lists of
components by sequence and function, component pin
sequences, and component plots.
FILE MANAGEMENT
The complete CMOS Component Symbols Library includes more
than 2.4 MB of files. If you are loading the library on the
hard disk of your stand-alone computer, you should omit any
of the components that you will not need in order to
conserve disk space. This is especially important if you
are using a 10 MB hard disk.
(
000-0081-01
CMOS Family Components
2
If your hard disk space is very limited, you may remove
individual unneeded components from the library_ Each
component is contained in a separate DOS file, and
individual components may be erased using the DOS erase
command. Refer to your IBM DOS Manual or the "DOS
Reference" chapter included with your PC-CAPS or PC-CARDS
User's Manuals for instructions on listing and erasing
fi les.
/
P-CAD recommends a specific directory structure for
efficient system operation. Your library symbols are
normally placed in a specific subdirectory to make it easu
to manage these files. The directory structure is described
in your P-CAD Installation Guide.
CREATING A DESIGN
To use the library in a design, run PC-CAPS. Instructions
are given in the "Using PC-CAPS" chapter of your PC-CAPS
User's Manual. When the menu is displayed, select FILE/LOAD
and load the layer structure. You can load LAYS.SCH or one
of the standard'size drawing sheet files, ASIZE.SCH through
ESIZE.SCH.
Laver Structure
Two layer structure files are included with this library,
lAYS.SYM and LAYS.SCH. There is no difference between
lAYS.SYM and LAYS.SCH other than the color and active state
of the layers.
The following layer structure, LAYS.SYM, is a standard P-CAD
layer structure and is recommended when creating library
components.
Table'.
taye ..
Nalile
LAYS.SY" Layer Structure
Pen
Status
Use
WIRES
OFF
Interconnecting
wires
2
BUS
OFF
Interconnecting
busses/wires
:3
GATE
ABL (A)
Symbol graphics
(ANSII)
2
000-0081-01
~
~~
Schematic Symbols
3
Table 1 Continued
Layer
NaIR
Pen
Status
Use
4
IEEE
2
OFF
Symbol graphics
(I EEE)
5
PINFUN
3
OFF
Pin functions
(IEEE)
6
PINNUM
ABl
Pin numbers
7
PINNAM
6
ABL
Pin names
8
PINCON
4
ABL
Pin connections
9
REFDES
2
ABL
Reference
Designators
10
ATTR
6
OFF
Visible attributes
11
SDOT
OFF
Solder dots
(not used)
12
DEVICE
5
ABL
Device name
13
OUTLIN
5
OFF
Component
outline
14
ATTR2
6
OFF
Invisible
attributes
15
NOTES
6
OFF
Notes/text/
documentation
16
NETNAM
4
OFF
Net/signal names
(schematic)
17
CMPNAM
5
OFF
Component
instance names
18
BORDER
5
OFF
Drawing/schematic
border
The following layer structure, LAYS.SCH, is another standard
P·CAD layer structure and is recommended when creating
schematics.
000·0081-01
CMOS Family Components
Table 2.
Layer
Malle
4
LAYS.SCH Layer Structure
Pen
IJIRES
Status
Use
ABL (A)
Interconnecting
wires
2
BUS
2
ABL
Interconnecting
busses/wires
3
GATE
3
ON
Symbol graphics
(ANSII)
4
IEEE
3
OFF
Symbol graphics
(I EEE)
5
PINFUN
3
OFF
Pin functions
( IEEE)
6
PINNUM
4
ON
Pin numbers
7
PINNAM
3
ON
Pin names
8
PINCON
4
ON
Pin connections
9
REFDES
5
ON
Reference
Designators
10
ATTR
6
OFF
Visible attributes
11
SDOT
ON
Solder dots
12
DEVICE
6
ON
Device name
13
OUTL IN
6
OFF
Component
outline
14
ATTR2
7
OF F
Invisible
attributes
15
NOTES
7
OFF
Notes/text/
documentation
16
NETNAM
8
ABL
Net/signal names
(schematic)
000-0081-01
C)
Schematic Symbols
5
Table 2 Continued
Layer
lIalie
Pen
Status
Use
17
CMPNAM
8
OFF
Component
instance names
18
BORDER
9
OFF
Drawing/schematic
border
Drawing Sheets
The standard-size drawing sheet files, ASIZE.SCH through
ESIZE.SCH, were created using the LAYS.SCH layer structure.
When loaded, they provide the correct layer structure for
the library plus a standard-size drawing sheet border.
Co.pcments
When you have loaded your layer structure or drawing sheet
file, you can enter the symbols, wires, text, instances, and
net names. Complete instructions are given in the "Using
PC-CAPS" chapter of your PC-CAPS User's Manual. Each
PC-CAPS component c~ntains the electrical "intelligence"
required to create schematics and extract data.
GENERAL INFORMATIOII
This library is comprised of symbols from four technologies:
1.
2.
3.
4.
Standard CMOS 4000 series
Standard CMOS 4500 series
High Speed CMOS ( 74HCxxx
High Speed TTL Compatible
CD40xxx
CD45xxx
74HCTxxx)
This library was created using the following sources
1. Universal Semiconductor Inc. High Speed CMOS
data book. (1985 version)
2. RCA Solid State QMOS data book.
(1985 version)
3. RCA COS/MaS Integrated Circuits book.
(1980 version)
4. Motorola Semiconductor Inc. CMOS Integrated
Circuits data book. (1978 version)
000-0081-01
CMOS Family Components
6
IEEE representations of all the devices are included.
complex devices are treated as gray boxes; limited
information concerning the function of the devices is
provided. All simple devices have normal IEEE
representations.
All
We have included mUltiple representations of several symbols
to better match your exact needs. The symbol files with
names ending in ~S~ contain a single gate per symbol whereas
the same symbol files without names ending in ~S~ contain
multiple gates per symbol. For example, the HCT175 (quad D
flip-flop) is represented as a single flip-flop in the file
HT175.SYM and as a single component containing four
flip-flops in the file HT17S$.SYM.
Due to system limitations regarding filename length, the
names of the symbol files in this library are truncated
versions of the component names:
CDxxxx shortened to Cxxxx.SYM
74HCxxxx shortened to Hxxxx.SYM
74HCTxxxx shortened to HTxxxx.SYM
000-0081 01
Schematic Symbols
COMPONENT LIST BY SEQUENCE
COMPONENT
t
~
..
C04000B
C04001B
C04002B
C04006B
C04008B
CD4009UB
C04010B
C04011B
C0401ZB
C04013B
CD401365
C040146
C040156
C0401565
C040166
C0401665
C040176
C040186
C040196
c040196S
C040206
C040216
C040226
C040236
C040246
CD40256
CD40266
C040276
C040286
C040296
C040306
C040316
C040326
C040326S
C040336
C040346
C040356
C04037A
CD4037A5
C040386
CD40386S
C040406
C04041U6
C040426
C040426S
0000081-01
DISK NUMBER
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PLOT NUMBER
(AN5I/lEEE)
COl/COlE
COl/COlE
COl/COlE
C01/C01E
C01/C01E
COl/COlE
C01/C01E
C01/C01E
COl/COlE
C01/C01E
COl/COlE
COl/COlE
C01/C01E
COl/COlE
COZ/C02E
C02/C02E
C02/C02E
C02/C02E
C02/C02E
CDZ/C02E
C02/C02E
C02/C02E
C02/C02E
C02/C02E
C02/C02E
C02/C02E
C03/C03E
C03/C03E
C03/CD3E
C03/C03E
CD3/C03E
CD3/C03E
C03/C03E
C03/CD3E
C03/C03E
C03/C03E
CD3/C03E
CD3/C03E
C04/C04E
C04/C04E
C04/C04E
C04/C04E
C04/C04E
C04/C04E
CD4/C04E
7
CMOS Family Components
COMPONENT
CD4043B
CD4043BS
CD4044B
CD4044BS
CD4045B
CD4046B
CD4047B
CD4048B
CD4049UB
CD4050B
CD4051B
CD4052B
CD4053B
CD4054B
CD4055B
CD4056B
CD4057A
CD4059A
CD4060B
CD4063B
CD4066B
CD4067B
CD4068B
CD4069UB
CD4070B
CD4071B
CD4072B
CD4073B
CD4075B
CD4076B
CD4077B
CD4078B
CD4081B
CD4082B
CD4085B
CD4085BS
CD4086B
CD4089B
CD4093B
CD4094B
CD4095B
CD4096B
CD4097B
CD4098B
CD4099B
CD4502B
CD4502BS
CD4503B
8
DISK NUMBER
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PLOT NUMBER
(ANS I /I EEE)
CD4/CD4E
CD4/CD4E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD5/CD5E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD6/CD6E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD7/CD7E
CD8/CD8E
CD8/CD8E
CD8/CD8E
CD8/CD8E
CD8/CD8E
CD8/CD8E
CD8/CD8E
CD8/CD8E
000-0081-01
Schematic Symbols
COMPONENT
(
CD4508B
CD4510B
CD4511B
CD4512B
C04514B
CD4515B
CD4516B
CD4517B
CD4517BS
C04518B
C04518BS
C04520B
C04520BS
C04527B
CD4532B
CD4536B
C04538B
C04538BS
CD4541B
C04555B
C04556B
C04585B
CD4724B
C022104A
CD22105A
C022859
C040100B
C040101B
CD40102B
C040103B
C040104B
C040105B
C040106B
C040107B
CD40108B
C040109B
CD40109BS
CD40110B
C040115
CD40116
CD40117B
CD40147B
CD40160B
C040161B
CD40162B
CD40163B
CD40174B
CD40174BS
000-0081-01
DISK NUMBER
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
PLOT NUMBER
(ANS I /I EEE)
CD8/CD8E
CD8/CD8E
CD9/CD9E
CD9/CD9E
CD9/CD9E
CD9/CD9E
CD9/CD9E
CD9/CD9E
C09/C09E
C09/C09E
C09/C09E
C09/C09E
C09/C09E
C09/C09E
C09/C09E
C09/C09E
C010/C010E
C010/C010E
C010/C010E
C010/C010E
C010/C010E
C010/C010E
C010/C010E
C010/C010E
C010/C010E
C010/C010E
C010/C010E
C010/C010E
C011/C011E
CO 11 /CO 11 E
CO 11 /CO 11 E
CO 11 /CO 11 E
CD 11 /CO 11 E
CO 11 /CO 11 E
CD11/CDllE
CDll/C011E
CDll/CD11E
C011/C011E
CO 11 /CO 11 E
CD12/CD12E
C012/CD12E
CD12/CD12E
C012/CD12E
C012/C012E
CD12/C012E
CD12/CD12E
CD12/CD12E
CD12/CD12E
9
CMOS Family Components
COMPONENT
C040175B
C040175BS
C040181B
C040182B
C040192B
C040193B
C040194B
C040208B
C040257B
C040257BS
HCOO
HC02
HC03
HC04
HC05
HC08
HC10
HC 11
HC14
HC20
HC21
HC27
HC30
HC32
HC42
HC44
HC51
HC73
HC74
HC75
HC76
HC85
HC86
HC93
HC107
HC109
HC112
HC123
HC125
HC126
HC132
HC133
HC137
HC138
HC139
HC145
10
DISK NUMBER
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
PLOT NUMBER
(ANSI/IEEE)
C012/C012E
C012/C012E
C013/C013E
C013/C013E
C013/C013E
C013/C013E
C013/C013E
C013/C013E
C013/C013E
C013/C013E
HC1/HC1E
HC1/HC1E
HC1/HC1E
HC1/HC1E
HC1/HC1E
HC1/HC1E
HC1/HC1E
HC1/HC1E
HC1/HC1E
HC2/HC2E
HC2/HC2E
HC2/HC2E
HC2/HC2E
HC2/HC2E
HC2/HC2E
HC2/HC2E
HC2/HC2E
HC2/HC2E
HC2/HC2E
HC2/HC2E
HC3/HC3E
HC3/HC3E
HC3/HC3E
HC3/HC3E
HC3/HC3E
HC3/HC3E
HC3/HC3E
HC3/HC3E
HC3/HC3E
HC3/HC3E
HC3/HC3E
HC4/HC4E
HC4/HC4E
HC4/HC4E
HC4/HC4E
HC4/HC4E
000-0081-01
Schematic Symbols
COMPONENT
If
(~
"
~.,
(-
HC147
HC151
HC153
HC153S
HC154
HC157
HC157S
HC158
HC158S
HC160
HC161
HC162
HC163
HC164
HC165
HC166
HC173
HC174
HC174S
HC175
HC175S
HC181
HC182
HC190
HC191
HC192
HC193
HC194
HC195
HC221
HC237
HC238
HC240
HC240S
HC241
HC242
HC243
HC244
HC244S
HC245
HC251
HC253
HC253S
HC257
HC258
HC259
HC266
HC273
000-0081-01
DISK NUMBER
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
PLOT NUMBER
(ANSI/lEEE)
HC4/HC4E
HC4/HC4E
HC4/HC4E
HC4/HC4E
HC4/HC4E
HC4/HC4E
HC4/HC4E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC5/HC5E
HC6/HC6E
HC6/HC6E
HC6/HC6E
HC6/HC6E
HC6/HC6E
HC6/HC6E
HC6/HC6E
HC6/HC6E
HC6/HC6E
HC6/HC6E
HC6/HC6E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HC7/HC7E
HCB/HCBE
HCB/HCBE
HC8/HC8E
11
CMOS Family Components
COMPONENT
HC280
HC283
HC297
HC299
HC354
HC356
HC365
HC365S
HC366
HC366S
HC367
HC368
HC373
HC374
HC375
HC375S
HC377
HC390
HC393
HC423
HC533
HC534
HC540
HC541
HC563
HC564
HC573
HC574
HC583
HC597
HC640
HC643
HC646
HC648
HC670
HC688
HC4002
HC4015
HC4016
HC4017
HC4020
HC4024
HC4040
HC4046
HC4049
HC4050
HC4051
HC4052
12
DISK NUMBER
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
PLOT NUMBER
(ANSI/lEEE)
HC8/HC8E
HC8/HC8E
HC8/HC8E
HC8/HC8E
HC8/HC8E
HC8/HC8E
HC8/HC8E
HC9/HC9E
HC9/HC9E
HC9/HC9E
HC9/HC9E
HC9/HC9E
HC9/HC9E
HC9/HC9E
HC9/HC9E
HC9/HC9E
HC9/HC9E
HC9/HC9E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC10/HC10E
HC11/HC11E
HC11/HC11E
HC11/HC11E
HC11/HC11E
HC11/HC11E
HC11/HC11E
HC11/HC11E
HC11/HC11E
HC11/HC11E
HC11/HC11E
HC11/HC11E
HC12/HC12E
HC12/HC12E
HC12/HC12E
HC12/HC12E
HC12/HC12E
HC12/HC12E
000-0081-01
Schematic Symbols
COMPONENT
(
HC4053
HC4059
HC4060
HC4066
HC4067
HC4075
HC4078
HC4094
HC4316
HC4316S
HC4351
HC4352
HC4353
HC4510
HC4511
HC4514
HC4515
HC4516
HC4518
HC4520
HC4538
HC7046
HC7266
HC40102
HC40103
HC40104
HC40105
HCTOO
HCT02
HCT03
HCT04
HCT05
HCT08
HCT10
HCTll
HCT14
HCT20
HCT21
HCT27
HCT30
HCT32
HCT42
HCT44
HCT51
HCT73
HCT74
HCT75
000-0081-01
DISK NUMBER
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
PLOT NUMBER
(ANSI/lEEE)
HC12/HC12E
HC12/HC12E
HC12/HC12E
HC13/HC13E
HC13/HC13E
HC13/HC13E
HC13/HC13E
HC 13/HC 13E
HC13/HC13E
HC13/HC13E
HC13/HC13E
HC13/HC13E
HCn/HC13E
HCn/HC13E
HCn/HCnE
HC14/HC14E
HC14/HC14E
HC14/HC14E
HC14/HC14E
HC14/HC14E
HC14/HC14E
HC14/HC14E
HC14/HC14E
HC14/HC14E
HC14/HC14E
HC14/HC14E
HC14/HC14E
HCT1/HCT1E
HCT1/HCT1E
HCT1/HCT1E
HCT1/HCT1E
HCT1/HCT1E
HCT1/HCT1E
HCT1/HCT1E
HCT1/HCT1E
HCT1/HCT1E
HCT2/HCT2E
HCT2/HCT2E
HCT2/HCT2E
HCT2/HCT2E
HCT2/HCT2E
HCT2/HCT2E
HCT2/HCT2E
HCT2/HCT2E
HCT2/HCT2E
HCT2!HCT2E
HCT2/HCT2E
13
CMOS Family Components
COMPONENT
HCT76
HCT85
HCT86
HCT93
HCT107
HCT109
HCT112
HCT123
HCT125
HCT126
HCT 132
HCT 133
HCT137
HCT138
HCT139
HCT145
HCT147
HCT151
HCT153
HCT153S
HCT154
HCT157
HCT157S
HCT158
HCT158S
HCT160
HCT161
HCT162
HCT163
HCT164
HCT165
HCT166
HCT173
HCT174
HCT174S
HCT 175
HCT175S
HCT181
HCT182
HCT190
HCT191
HCT192
HCT193
HCT194
HCT195
HCT221
HCT237
HCT238
14
DISK NUMBER
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
PLOT NUMBER
(ANS I II EEE)
HCT3/HCT3E
HCT3/HCT3E
HCT3/HCT3E
HCT3/HCT3E
HCT3/HCT3E
HCT3/HCT3E
HCT3/HCT3E
HCT3/HCT3E
HCT3/HCT3E
HCT3/HCT3E
HCT3/HCT3E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT4/HCT4E
HCT5/HCTSE
HCT5/HCT5E
HCT5/HCT5E
HCT5/HCT5E
HeT5/HCT5E
HCT5/HCT5E
HCT5/HCT5E
HCT5/HCT5E
HCT5/HCT5E
HCT5/HCT5E
HCT5/HCT5E
HCT5/HCT5E
HCT6/HCT6E
HCT6/HCT6E
HCT6/HCT6E
HCT6/HCT6E
HCT6/HCT6E
HCT6/HCT6E
HCT6/HCT6E
HCT6/HCT6E
HCT6/HCT6E
HCT6/HCT6E
HCT6/HCT6E
HCT7/HCT7E
HCT7/HCT7E
000 - 0081' G;
Schematic Symbols
COMPONENT
(
HCT240
HCT2/.0S
HCT241
HCT242
HCT243
HCT2'.4
HCT244S
HCT2'.5
HCT251
HCT253
HCT2535
HCT257
HCT258
HCT259
HCT266
HCT273
HCT280
HCT283
HCT297
HCT299
HC1354
HC1356
HC1365
HCT3655
HC1366
HC13665
HC1367
HCT368
HC1373
HCT374
HC1375
HCT3755
HC1377
HC1390
HC1393
HCT423
HCT533
HCT534
HCT540
HCT541
HCT563
HCT564
HCT573
HCT574
HCT583
HCT597
HCT640
HCT643
HCT646
000-0081-01
DISK NUMBER
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PLOT NUMBER
(ANSI/IEEE)
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT7/HCT7E
HCT8/HCT8E
HCT8/HCT8E
HCT8/HCT8E
HCT8/HCT8E
HCT8/HCT8E
HCT8/HCT8E
HCT8/HCT8E
HCT8/HCT8E
HCT8/HCT8E
HCT8/HCT8E
HCT9/HCT9E
HCT9/HCT9E
HCT9/HCT9E
HCT9/HCT9E
HCT9/HCT9E
HCT9/HCT9E
HCT9/HCT9E
HCT9/HCT9E
HCT9/HCT9E
HCT9/HCT9E
HCT9/HCT9E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT10/HCT10E
HCT11/HCT11E
HCT11/HCT11E
15
CMOS Family Components
COMPONENT
HCT648
HCT670
HCT688
HCT4002
HCT4015
HCT4016
HCT4017
HCT4020
HCT4024
HCT4040
HCT4046
HCT4049
HCT4050
HCT4051
HCT4052
HCT4053
HCT4059
HCT4060
HCT4066
HCT4067
HCT4075
HCT4078
HCT4094
HCT4316
HCT4316S
HCT4351
HCT4352
HCT4353
HCT4510
HCT4511
HCT4514
HCT4515
HCT4516
HCT4518
HCT4520
HCT4538
HCT7046
HCT7266
HCT40102
HCT40103
HCT40104
HCT40105
16
DISK NUMBER
8
8
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
PLOT NUMBER
(ANSI/lEEE)
HCT11/HCT11E
HCT11/HCT11E
HCT11/HCT11E
HCT11/HCT11E
HCT11/HCT 11 E
HCT11/HCT11E
HCT11/HCT11E
HCT11/HCT11E
HCT11/HCT11E
HCT12!HCT12E
HCT12!HCT12E
HCT12/HCT 12E
HCT12/HCT 12E
HCT12!HCT12E
HCT12/HCT12E
HCT12/HCT12E
HCT12!HCT12E
HCT12/HCT 12E
HCT12/HCT 12E
HCT13/HCT BE
HCT13/HCT BE
HCTB/HCT13E
HCT13/HCTBE
HCT13/HCT13E
HCT13/HCT13E
HCT13/HCT13E
HCT13/HCT13E
HCT13/HCT13E
HCT13/HCT13E
HCT 13/HCT BE
HCT14/HCT14E
HCT14/HCT14E
HCT14/HCT14E
HCT14/HCT14E
HCT14/HCT14E
HCT14/HCT 14E
HCT14/HCT14E
HCT14/HCT14E
HCT14/HCT14E
HCT14/HCT14E
HCT14/HCT14E
HCT14/HCT14E
000-0081-01
Schematic Symbols
COMPONENT LIST BY FUNCTION
This list includes the following functional categories:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
AND/NAND GATES
ARITHMETIC CIRCUITS
BUFFERS AND INVERTERS
COUNTERS
DECODERS/ENCODERS
DISPLAY DRIVERS
FLIp·FLOPS
INTERFACE CIRCUITS
LATCHES
MULTIFUNCTION AND·OR·INVERT GATES
MULTIPLEXERS/DEMULTIPLEXERS
MULTIVIBRATORS
OR/NOR GATES
PHASE· LOCKED LOOPS
REGISTERS
SCHMITT TRIGGERS
SIJITCHES
TIMING CIRCUITS
TRANSCEIVERS
AND/NAND GATES
CD4011B
CD4012B
CD4023B
CD4068B
CD4073B
CD4081B
CD4082B
CD40107B
HCOO
HC03
(
HC08
HC10
HC11
HC20
HC21
HC30
HC133
HCTOO
000-0081-01
Quad 2-input NAND gate
Dual 4-input NAND gate
Triple 3-input NAND gate
8-input NAND/AND gate
Triple 3-input AND gate
Quad 2-input AND gate
Dual 4-input AND gate
Dual 2-input NAND buffer/driver
Quad 2-input NAND gate
Quad 2-input open drain NAND
gate
Quad 2-input AND gate
Triple 3-input NAND gate
Triple 3-input AND gate
Dual 4-input NAND gate
Dual 4-input AND gate
8-input NAND gate
13-input NAND gate
Quad 2-input NAND gate
17
CMOS Family Components
HCT03
HCT08
HCT10
HCT11
HCT20
HCT21
HCT30
HCT133
18
Quad 2-input open drain NAND
gate
Quad 2-input AND gate
Triple 3-input NAND gate
Triple 3-input AND gate
Dual 4-input NAND gate
Dual 4-input AND gate
8-input NAND gate
13-input NAND gate
ARITHMETIC CIRCUITS
CD40088
CD40328
CD40388
CD4057A
CD40638
CD40898
CD401018
CD401818
CD40182B
CD4527B
CD4585B
HC85
HC181
HC182
HC280
HC283
HC583
HC688
HCT85
HCT181
HCT182
HCT280
HCT283
HCT583
HCT688
4-bit full adder
Triple serial adder, positive
logic
Triple serial adder, negative
logic
4-bit arithmetic logic unit
4-bit magnitude comparator
Binary rate multiplier
9-bit parity generator/checker
Arithmetic logic unit
Look-ahead carry generator
BCD rate multiplier
4-bit magnitude comparator
4-bit magnitude comparator
Arithmetic Logic Unit
Carry generator
8-bit odd/even parity
generator/checker
4-bit full adder with fast carry
4-bit full adder with fast carry
8-bit magnitude comparator
4-bit magnitude comparator
Arithmetic Logic Unit
Carry generator
8-bit odd/even parity
generator/checker
4-bit full adder with fast carry
4-bit full adder with fast carry
8-bit magnitude comparator
000-0081-01
Schematic Symbols
BUFFERS AND INVERTERS
CD4009UB
CD4010B
CD4041UB
CD4049UB
CD4050B
CD4069UB
CD4502B
CD4503B
HC04
HC05
HC125
HC126
HC240
HC241
HC244
HC365
HC366
HC367
HC368
HC540
HC541
HCT04
HCT05
HCT125
HCT126
HCT240
HCT241
HCT244
HCT365
HCT366
HCT367
HCT368
HCT540
(
HCT541
000-0081-01
Hex buffer/converter (inverting)
Hex buffer/converter
(non-inverting)
Quad true/complement buffer
Hex buffer/converter (inverting)
Hex buffer/converter
(non-inverting)
Hex inverter
Hex inverter/buffer (3-state)
Hex buffer(3-state non-inverting)
Hex inverter ( triple buffered)
Hex inverter with open-drain
output
Quad tri-state buffer
Quad tri-state buffer
Octal tri-state buffer (inverting)
Octal tri-state buffer
Octal tri-state buffer
Hex buffer/line driver (3-state)
Hex buffer/line driver
(3-state inverting)
Hex buffer/line driver (3-state)
Hex buffer/line driver
(3-state inverting)
Octal buffer/line driver
(3-state inverting)
Octal buffer/line driver(3-state)
Hex inverter ( triple buffered)
Hex inverter with open-drain
output
Quad tri-state buffer
Quad tri-state buffer
Octal tri-state buffer (inverting)
Octal tri-state buffer
Octal tri-state buffer
Hex buffer/line driver (3-state)
Hex buffer/line driver
(3-state inverting)
Hex buffer/line driver (3-state)
Hex buffer/line driver
(3-state inverting)
Octal buffer/line driver
(3-state inverting)
Octal buffer/line driver(3-state)
19
CMOS Family Components
20
COUNTERS
C04017B
C04018B
C04020B
C04022B
C04024B
C04029B
C04040B
C04059A
C04060B
C040102B
C040103B
C040110B
C040160B
C040161B
C040162B
C040163B
C040192B
C040193B
C04510B
C04516B
C04518B
C04520B
HC93
HC160
HC161
HC162
HC163
HC190
Oecade counter/divider plus 10
decoded decimal outputs
Programmable divide-by-N counter
14-stage ripple-carry binary
counter
Divide-by-8 counter/divider
with 8 decimal outputs
7-stage counter
Presettable up/down counter
12-stage counter
Programmable divide-by-N counter
14-stage counter/divider and
osci llator
Preset table 2-decade BCO down
counter
Presettable 8-bit binary down
counter
Oecade up/down counter/latch/
display driver
Oecade counter/asynchronous clear
Binary counter/asynchronous clear
Oecade counter/synchronous clear
Binary counter/synchronous clear
Presettable 4-bit BCO up/down
counter
Presettable 4-bit binary up/down
counter
Presettable 4-bit BCO up/down
counter
Preset table 4-bit binary up/down
counter
Oual BCD up counter
Oual binary up counter
4-bit binary ripple counter
Synchronous BCO decade counter
with asynchronous reset
Synchronous 4-bit binary counter
with asynchronous reset
Synchronous BCO decade counter
with synchronous reset
Synchronous 4-bit binary counter
with synchronous reset
Presettable synchronous BCO
decade up/down counter
000-0081-01
Schematic Symbols
HC191
HC192
HC193
HC390
HC393
HC4017
HC4020
HC4024
HC4040
HC4059
HC4060
HC40102
HC40103
HC4510
HC4516
HC4518
HC4520
HCT93
HCT160
HCT161
HCT162
HCT163
HCT190
HCT191
HCT192
HCT193
HCT390
HCT393
HCT4017
(
HCT4020
HCT4024
HCT4040
000-0081-01
Synchronous binary up/down
counter with mode control
Synchronous BCD decade up/down
counter
Synchronous 4-bit binary up/down
counter
Dual 4-bit decade counter
Dual 4-bit binary ripple counter
Johnson decade counter with 10
decoded outputs
14-stage binary ripple counter
7-stage binary ripple counter
12-bit binary counter
Programmable divide by N counter
14-stage binary counter with
oscillator
a-bit synchronous BCD down counter
8-bit binary down counter
Up/down BCD counter
Up/down binary counter
Dual synchronous BCD counter
Dual 4-bit synchronous binary
counter
4-bit binary ripple counter
Synchronous BCD decade counter
with asynchronous reset
Synchronous 4-bit binary counter
with asynchronous reset
Synchronous BCD decade counter
with synchronous reset
Synchronous 4-bit binary counter
with synchronous reset
Presettable synchronous BCD
decade up/down counter
Synchronous binary up/down
counter with mode control
Synchronous BCD decade up/down
counter
Synchronous 4-bit binary up/down
counter
Dual 4-bit decade counter
Dual 4-bit binary ripple counter
Johnson decade counter with 10
decoded outputs
14-stage binary ripple counter
7-stage binary ripple counter
12-bit binary counter
21
CMOS Family Components
HCT4059
HCT4060
HCT40102
HCT40103
HCT4510
HCT4516
HCT4518
HCT4520
22
Programmable divide by N counter
14-stage binary counter with
oscillator
8-bit synchronous BCD down counter
8-bit binary down counter
Up/down BCD counter
Up/down binary counter
Dual synchronous BCD counter
Dual 4-bit synchronous binary
counter
DECODERS / ENCODERS
CD4028B
CD40 14 7B
CD4514B
CD4515B
CD4532B
CD4555B
CD4556B
HC42
Hc,.4
HC137
HC138
HC139
HC145
HC147
HC154
HC237
HC238
HC4511
HC4514
HC4515
HCT42
BCD-tO-decimal decoder
10-line to 4-line
BCD priority encoder
4-bit latch/4-to-16 line
decoder (outputs high)
4-bit latch/4-to-16 line
decoder (outputs low)
8-bit priority encoder
Dual 1-of-4 decoder/demultiplexer
(outputs high)
Dual 1-of-4 decoder/demultiplexer
(outputs low)
BCD-to-decimal decoder (1-to-10)
1-of-10 decoder
3-to-8 line decoder (inverting)
with latch
Dual 3-to-8 line decoder
Dual 2-to-4 line decoder
1-of-10 decoder/driver with
open drain outputs
10-to-4 line priority encoder
4 - to - 16 line
decoder/demultiplexer
3-to-8 line decoder with address
latches
3-to-8 line decoder/demultiplexer
BCD-to-7 segment decoder/latch/
dr i ver
4-to-16 decoder/demultiplexer
with input latch
4-to-16 line decoder
with input latch
BCD-to-decimal decoder (1-of-10)
000-0081-01
Schematic Symbols
HCT44
HCT137
HCT 138
HCT 139
HCT145
HCT147
HCT154
HCT237
HCT238
HCT4511
HCT4514
HCT4515
1-of-10 decoder
3-to-8 line decoder (inverting)
wi th latch
Dual 3-to-8 line decoder
Dual 2-to-4 line decoder
1-of-l0 decoder/driver with
open drain outputs
10-to-4 line priority encoder
4-to-16 line
decoder/demultiplexer
3-to-8 line decoder
3-to-8 line decoder/demultiplexer
BCD-to-7 segment decoder/latch/
driver
4-to-16 decoder/demultiplexer
with input latch
4-to-16 line decoder
with input latch
DISPLAY DRIVERS
CD4026B
CD4033B
CD4054B
CD4055B
CD4056B
CD4511B
CD22104A
CD22105A
Decade counter/divider with
7-segment display outputs and
display enable
Decade counter/divider with
7-segment display outputs and
ripple blanking
4-segment display driver
BCD-to-7-segment decoder/driver
with "display-frequency" output
BCD-to-7-segment decoder/driver
with strobe-latch function
BCD-to-7-segment latch
decoder/driver
4-digit decoder/driver with
decimal display
4-digit decoder/driver with
decimal display
FLIP- FLOPS
(
CD4013B
CD4027B
DOO-0081-01
Dual D-typeflip-flopwith
set/reset capability
Dual J-K flip-flopwith
set/reset capability
23
CMOS Family Components
C040958
C040968
C0401748
C0401758
HC73
HC74
HC76
HC107
HC109
HC112
HC173
HC174
HC175
HC273
HC373
HC374
HC377
HC534
HC564
HC574
HCT73
HCT74
HCT76
HCT107
HCT109
HCT112
HCT173
HCT174
HCT175
HCT273
HCT373
24
Gated J-K master-slave flip-flops
(non-inverting inputs)
Gated J-K master-slave flip-flops
(inverting/non-inverting inputs)
Hex Ootype flip-flop
with clear
Quad Ootype flip-fLop
with clear
Dual J-K flip-flops with clear
Dual 0 flip-flops with preset
and clear
Dual J-K flip-flops with preset
and clear
Dual J-K flip-flops with clear
Dual J-K flip-flop with preset
and clear
Dual J-K flip-flops with preset
and clear
Quad 0 type flip-flops (3-state)
Hex 0 flip-flops with clear
Quad 0 flip-flops with clear
Octal 0 flip-flops with clear
Octal 0 flip-flops with 3-state
outputs
Octal 0 flip-flops with 3-state
outputs
Octal 0 flip-flop
Octal 0 flip-flop with 3-state
inverted outputs
Octal 0 flip-flop
(3-state inverting)
Octal 0 flip-flop (3-state)
Dual J-K flip-flops with clear
Dual 0 flip-flops with preset
and clear
Dual J-K flip-flops with preset
and clear
Dual J-K flip-flops with clear
Dual J-K flip-flop with preset
and clear
Dual J-K flip-flops with preset
and clear
Quad 0 type flip-flops (3-state)
Hex 0 flip-flops with clear
Quad 0 flip-flops with clear
Octal 0 flip-flops with clear
Octal 0 flip-flops with 3-state
outputs
000-0081-01
Schematic Symbols
HCT374
HCT377
HCT534
HCT564
HCT574
Octal D flip-flops with 3-state
outputs
Octal D flip-fLop
Octal D fLip-flop with 3-state
inverted outputs
Octal D fLip-flop
(3-state inverting)
Octal D flip-flop (3-state)
INTERFACE CIRCUITS
CD40109B
CD40115
CD40116
CD40117B
HC4049
HC4050
HCT4049
HCT4050
Quad low-to-high voltage
level shifter
8-bit bidirectional CMOS-to-TTL
level converter
8-bit bidirectional CMOS-to-TTL
level converter
Programmable dual 4-bit
terminator
Hex inverting HIGH-TO-LOW
level shifter
Hex HIGH-TO-LOW level shifter
Hex inverting HIGH-TO-LOW
level shifter
Hex HIGH-TO-LOW LeveL shifter
LATCHES
CD4042B
CD4043B
CD4044B
CD4099B
CD4508B
CD4724B
HC75
(
HC259
HC375
HC533
000 - 0081 - 01
Quad clocked D-type Latch
Quad NOR R-S latch
(3-state outputs)
Quad NAND R-S latch
(3-state outputs)
8-bit addressable Latch
Dual 4-bit latch
8-bit addressable latch
4-bit bistabLe Latch with
complimentary outputs
8-bit addressable Latch
4-bi t latch
Octal D type latch with
3-state inverted outputs
25
CMOS Family Components
HC563
HC573
HCT75
HCT259
HCT375
HCT533
HCT563
HCT573
26
Octal transparent latch
(3-state inverting)
Octal transparent latch (3-state)
4-bit bistable latch with
complimentary outputs
8-bit addressable latch
4-bit latch
Octal D type latch with
3-state inverted outputs
Octal transparent latch
(3-state inverting)
Octal transparent latch (3-state)
'\
)
MULTIFUNCTION AND-DR-INVERT GATES
CD4019B
CD4037A
CD4048B
CD4085B
CD4086B
HC51
HCT51
Quad AND!OR select gate
Triple AND-OR bi-phase pairs
Multifunctional expandable
8-input gate
Dual 2-wide, 2-input AND-ORinvert gate
Expandable 4-wide, 2-input
AND-DR-invert gate
Dual AND-OR-INVERT gate
Dual AND-OR-INVERT gate
I
-/
MULTIPLEXERS/DEMULTIPLEXERS
CD4051B
CD4052B
CD4053B
CD4067B
CD4097B
CD40257B
CD4512B
HC151
HC153
HC157
'\
Single 8-channel multiplexer/
demultiplexer
Differential 4-channel
multiplexer/demultiplexer
Triple 2-channel multiplexer!
demultiplexer
Single 16-channel multiplexer!
demultiplexer
Differential 8-channel
multiplexer/demultiplexer
Quad 2-line-to-1-line
data select/multiplexer
8-channel data selector
8-channel digital multiplexer
Dual 4-input multiplexer
Quad 2-input mUltiplexer
000-0081-01
Schematic Symbols
HC158
HC251
HC253
HC257
HC258
HC354
HC356
HC4051
HC4052
HC4053
HC4067
HC4351
HC4352
HC4353
HCT151
HCT153
HCT157
HCT158
HCT251
HCT253
HCT257
HCT258
HCT354
HCT356
HCT4051
HCT4052
HCT4053
HCT4067
HCT4351
HCT4352
HCT4353
000-0081-01
Quad 2-input multiplexer
8-channel 3-state multiplexer
Dual 4-input multiplexer(3-state)
Quad 2-channel 3-state multiplexer
Quad 2-channel 3-state multiplexer
8-input multiplexer/register
( 3-state )
8-input multiplexer/register
( 3-state )
8-channel analog mUltiplexer/
demultiplexer
Dual 4-channel analog
multiplexer/demultiplexer
Triple 2-channel analog
multiplexer/demultiplexer
16-channel analog multiplexer/
demultiplexer
Analog multiplexer with latch
Analog multiplexer with latch
Analog multiplexer with latch
8-channel digital multiplexer
Dual 4-input multiplexer
Quad 2-input multiplexer
Quad 2-input multiplexer
8-channel 3-state multiplexer
Dual 4-input multiplexer(3-state)
Quad 2-channel 3-state multiplexer
Quad 2-channel 3-state multiplexer
8-input multiplexer/register
( 3-state )
8-input multiplexer/register
( 3-state )
8-channel analog multiplexer/
demultiplexer
Dual 4-channel analog
multiplexer/demultiplexer
Triple 2-channel analog
multiplexer/demultiplexer
16-channel analog multiplexer/
demultiplexer
Analog multiplexer with latch
Analog multiplexer with latch
Analog multiplexer with latch
27
CMOS Family Components
28
MULTIVIBRATORS
CD4047B
CD4098B
CD4538B
HC123
HC221
HC423
HC4538
HCT123
HCT221
HCT423
HCT4538
Monostable/astable multivibrator
Dual monostable multivibrator
Dual precision monostable
multivibrator
Dual retriggerable monostable
multivibrator
Dual non-retriggerable monostable
multivibrator
Dual retriggerable monostable
multivibrator with reset
Dual precision monostable
multivibrator
Dual retriggerable monostable
multivibrator
Dual non-retriggerable monostable
multivibrator
Dual retrigg~rable monostable
multivibrator with reset
Dual precision monostable
multivibrator
OR/NOR GATES
CD4000B
CD4001B
CD4002B
CD4025B
CD4030B
CD4070B
CD4071B
CD4072B
CD4075B
CD4077B
CD4078B
HC02
HC27
HC32
HC86
HC266
HC4002
HC4075
HC4078
HC7266
Dual 3-input NOR gate plus
inverter
Quad 2-input NOR gate
Dual 4-input NOR gate
Triple 3-input NOR gate
Quad exclusive-OR gate
Quad exclusive-OR gate
Quad 2-input OR gate
Dual 4-input OR gate
Triple 3-input OR gate
Quad exclusive-NOR gate
8-input NOR/OR gate
Quad 2-input NOR gate
Triple 3-input NOR gate
Quad 2-input OR gate
Quad 2-input exclusive OR gate
Quad 2-input exclusive NOR gate
Dual 4-input NOR gate
Triple 3-input OR gate
8-input NOR/OR gate
Quad exclusive NOR gates
000-0081-01
Schematic Symbols
HCT02
HCT27
HCT32
HCT86
HCT266
HCT4002
HCT4075
HCT4078
HCT7266
Quad 2-input NOR gate
Triple 3-input NOR gate
Quad 2-input OR gate
Quad 2-input exclusive OR gate
Quad 2-input exclusive NOR gate
Dual 4-input NOR gate
Triple 3-input OR gate
8-input NOR/OR gate
Quad exclusive NOR gates
PHASE-LOCKED LOOPS
CD4046B
HC297
HC4046
HC7046
HCT297
HCT4046
HCT7046
Micropower phase-locked loop
Digital phase-locked loop filter
Phase-locked loop
Phase-locked loop with IN-LOCK
detection
Digital phase-locked loop filter
Phase-locked loop
Phase-locked loop with IN-LOCK
detection
REG I STERS
CD4006B
CD4014B
CD4015B
CD4021B
CD4031B
CD4034B
CD4035B
000-0081-01
18-stage static shift register
8-stage with synchronous parallel
or serial input/serial output
static shift register
Dual 4-stage with serial input/
parallel output static shift
register
8-stagewithasynchronous
parallel input or synchronous
serial input/serial output
static shift register
64-stage static shift register
8-stage bidirectional parallel
or serial input/parallel output
static shift register
4-stage parallel-in/parallel-out
with J-K input and true/
complement output static shift
register
29
CMOS Family Components
C040768
C040948
C0401008
C0401048
C0401058
C040108B
C0401948
C0402088
C045178
HC164
HC165
HC166
HC194
HC195
HC299
HC597
HC670
HC4015
HC4094
HC40104
HC40105
HCT164
HCT165
HCT166
HCT194
HCT195
30
4-bit register with Ootype
flip-flops (3-state outputs)
8-stage shift-and-store
bus register
32-bit left/right static shift
register
4-bit universal bidirectional
static shift register with
3-state outputs
4-bit x 16 word FIFO buffer
register
4 x 4 multi port register
4-bit universal bidirectional
shift register
4 x 4 multiport register
Oual 64-stage static shift
register
8-bit serial-in/parallel-out
shift register
8-bit parallel-in serial-out
shift register
8-bit parallel-in serial-out
shift register
4-bit bidirectional universal
shift register
4-bit parallel access
shift register
8-bit universal shift register
(3-state)
B-bit shift register
with I/P latch
4 x 4 register file (3-state)
Oual 4-bit serial-in/parallel-out
shift register
8-stage shift-and-store
bus register
4-bit bidirectional universal
shift register ( 3-state )
4-bit x 16-words FIFO register
8-bit serial-in/parallel-out
shift register
B-bit parallel-in serial-out
shift register
8-bit parallel-in serial-out
shift register
4-bit bidirectional universal
shift register
4-bit parallel access
shift register
000-0081-01
Schematic Symbols
HCT299
HCT597
HCT670
HCT4015
HCT4094
HCT40104
HCT40105
8"bit universal shift register
(3" state)
8"bit shift register
wi th liP latch
4 x 4 register file (3"state)
Dual 4"bit serial"in/parallel"out
shift register
8"stage shift"and"store
bus register
4"bit bidirectional universal
shift register ( 3"state )
4"bit x 16"words FIFO register
SCHMITT TRIGGERS
C04093B
CD40106B
HC14
HC132
HCT14
HCT 132
Quad 2"input NAND Schmitt trigger
Hex Schmitt trigger
Hex inverting Schmitt trigger
Quad 2"input NAND Schmitt trigger
Hex inverting Schmitt trigger
Quad 2"input NAND Schmitt trigger
SIJITCHES
CD4016B
CD4066B
HC4016
HC4066
HC4316
HCT4016
HCT4066
HCT4316
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Quad
bilateral switch
bilateral switch
bilateral switch
bilateral switch
analog switch
bilateral switch
bilateral switch
analog switch
TIMING CIRCUITS
CD22859
(
CD4045B
CD4536B
CD4541B
000"0081 "01
Dual"tone multi frequency
tone generator
21"stage counter timing circuit
Programmable timing circuit with
24 ripple"binary counter stages
Programmable timing circuit with
16"stage binary counter
31
CMOS Family Components
32
TRANSCEIVERS
HC242
HC243
HC245
HC640
HC643
HC646
HC648
HCT242
HCT243
HCT245
HCT640
HCT643
HCT646
HCT648
Quad bus transceiver
(3-state inverting)
Quad bus transceiver (3-state)
Octal 3-state transceiver
Octal bus transceiver
( 3-state inverting)
Octal bus transceiver
( 3-state; true inverting
Octal bus transceiver/register
( 3-state )
Octal bus transceiver/register
( 3-state inverting)
Quad bus transceiver
(3-state inverting)
Quad bus transceiver (3-state)
Octal 3-state transceiver
Octal bus transceiver
( 3-state inverting)
Octal bus transceiver
( 3-state; true inverting
Octal bus transceiver/register
( 3-state )
Octal bus transceiver/register
( 3-state inverting)
/
~.
000-0081-01
/
Schematic Symbols
COMPONENT PIN SEQUENCES
£
~
C4000B: NUMBER DF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
{n/c}
= {n/c}
A
=B
=C
ill
SIGNAL
6
7
8
= [GND]
9
=l
10
1
2
3
4
5
SIGNAL
INA (A)
= INB (A)
= DUTY (A)
= DUTY (B)
INA (B)
ill
6
7
8
9
10
ill
11
12
13
14
H
G
K
C4D01B: NUMBER DF GATES PER PACKAGE
ill
=
1
2
3
4
5
SIGNAL
DUTY CA)
INA (A)
= INB (A)
INC (A)
IND (A)
ill
6
7
8
9
10
SIGNAL
ill
= I NB CB)
= [GNO]
= INA (C)
11
12
13
14
INB (C)
DUTY (C)
ill
1
2
3
4
5
SIGNAL
= 01
D1+4'
ClK
D2
D3
f
000-0081-01
ill
{n/c}
= [GND]
{n/c}
= INA (B)
= INB (B)
6
7
8
SIGNAL
= D4
[GND]
D4+4
9 = D4+5
D3+4
10
SIGNAL
DUTY (D)
(D)
(D)
[VCC]
= INA
= INB
2
SIGNAL
C4006B: NUMBER DF GATES PER PACKAGE
D
=E
F
= [VCC]
=4
C4002B: NUMBER DF GATES PER PACKAGE
ill
SIGNAL
ill
SIGNAL
11
12
13
14
= IND (B)
DUTY (B)
= [VCC]
ill
SIGNAL
INC (B)
=
11
12
13
14
= D2+4
D2+5
D1+4
[VCC]
33
CMOS Family Components
34
C4008B: NUMBER OF GATES PER PACKAGE
illill
ill
1
2
3
4
5
6
= A4
B3
= A3
B2
= A2
= B1
ill
SIGNAL
ill
SIGNAL
12
S3
13 = S4
14
COUT
15 = B4
[VCC]
16
7 = A1
[GND]
8
9 = CIN
10
S1
11 = S2
~.
!
~.
\.
.~'l
I
C4009UB: NUMBER OF GATES PER PACKAGE
SIGNAL
ill
1
2
3
4
5
6
=
=
=
=
=
=
VCC
OUTA'
INA
OUTB'
INB
aUTC'
ill
SIGNAL
7
INC
8 = [GND]
9 = IND
10
OUTD'
11 = INE
ill
SIGNAL
12
13
14
15
16
OUTE'
{n/c}
INF
OUTF'
[VCC]
C4010B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = VCC
2
aUTA
3
INA
4
OUTB
5
INB
6
OUTC
ill
SIGNAL
7 = INC
8
9
10
11
[GND]
IND
OUTD
INE
C4011B: NUMBER OF GATES PER PACKAGE
ill
illill
1 = INA (A)
INB (A)
2
3
OUTY (A)
4 = OUTY (B)
5
INA (B)
'\
ill
6
7
8
9
10
SIGNAL
INB (B)
[GND]
INA (C)
INB (C)
OUTY (C)
ill
SIGNAL
12
13
14
15
16
OUTE
{n/c}
INF
OUTF
[VCC]
ill
SIGNAL
4
11
12
13
14
OUTY (D)
INA (D)
INB (D)
[VCC]
(
~
000-0081-01
,
Schematic Symbols
C4012B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
OUTY (A)
INA (A)
INB (A)
INC (A)
IND (A)
ill
6
?
B
9
10
SIGNAL
ill
{n/c}
[GND]
{n/c}
INA (B)
INB (B)
11
12
13
14
C4013B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
Q (A)
Q' (A)
ClK (A)
RESET (A)
D (A)
ill
6
?
B
9
10
2
SIGNAL
SET (A)
[GNO]
SET (B)
D (B)
RESET (B)
SIGNAL
INC (B)
INO (B)
OUTY (B)
[VCC]
2
ill
SIGNAL
11
12
14
ClK (B)
Q' (B)
Q (B)
[VCC]
SIGNAL
13
C4013BS: NUMBER OF GATES PER PACKAGE
.'is
r,'~
I~
ill
SIGNAL
ill
SIGNAL
ill
1
2
3
4
Q1
Q1'
ClK1
RESET1
D1
6
?
B
SET1
[GND]
SET2
D2
RESET2
11
12
5
9
10
14
ClK2
Q2'
Q2
[VCC]
ill
SIGNAL
12
13
14
15
16
POUT?
PINS
PIN6
PIN?
[VCC]
13
C4014B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
PINB
POUT6
POUTB
PIN4
PIN3
PIN2
(
000-00B1-01
ill
?
B
9
10
11
SIGNAL
PIN1
[GND]
PSC
ClK
SIN
35
CMOS Family Components
36
C4015B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
ClK (B)
Q4 (B)
Q3 (A)
Q2 (A)
Q1 (A)
RESET (A)
ill
7
8
9
10
11
2
SIGNAL
ill
DATA (A)
[GND]
ClK (A)
Q4 (A)
Q3 (B)
12
13
14
15
16
SIGNAL
Q2 (B)
Q1 (B)
RESET (B)
DATA (B)
[VCC]
C4015BS: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
= ClKB
Q4B
Q3A
Q2A
Q1A
RESETA
ill
7
8
9
10
11
SIGNAL
= DATAA
1
2
3
4
5
SIGNAL
10 (A)
01 (A)
01 (B)
10 (B)
CNTRl (B)
ill
6
7
8
9
10
12
13
14
15
16
[GND]
ClKA
Q4A
Q3B
C4016B: NUMBER OF GATES PER PACKAGE
ill
ill
SIGNAL
CNTRl (C)
[GND]
10 (C)
01 (C)
01 (D)
SIGNAL
= Q2B
Q1B
RESETB
DATAB
[VCC]
4
ill
11
12
13
14
SIGNAL
10 (D)
CNTRl (D)
CNTRl (A)
[VCC]
C4016BS: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
A- 10
A"OI
B-OI
B-IO
CNTRl-B
ill
6
7
8
9
10
SIGNAL
ill
SIGNAL
CNTRl-C
[GND]
C- 10
C-OI
0-01
11
12
13
14
0-10
CNTRl-D
CNTRl-A
[VCC]
000-0081-01
'-.
/
Schematic Symbols
C4017B: NUMBER OF GATES PER PACKAGE
ill
4"
Is,~
1
2
3
4
5
6
illlli
Q5
Q1
QO
Q2
Q6
Q7
ill
SIGNAL
ill
7 = Q3
[GND]
8
Q8
9
Q4
10
Q9
11
12
13
14
15
16 =
SIGNAL
CO
CLKE'
CLK
RST
[VCC]
C4018B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 DATA
2
JAM1
3 = JAM2
4 = Q2'
5
Q1'
6
Q3'
ill
SIGNAL
\i,
ill
1
2
3
4
5
6
SIGNAL
ill
SIGNAL
(D)
(C)
7
8
9
10
11
B (A)
[GND]
KA (D)
D (A)
D (B)
B
A
B
A
B
A
(C)
(B)
(B)
(A)
SIGNAL
12 = JAM5
Q5'
13
14
CLK
15
RESET
[VCC]
16
7 = JAM3
[GND]
8
JAM4
9
10 = PREN
Q4'
11
C4019B: NUMBER OF GATES PER PACKAGE
'""
ill
4
ill
SIGNAL
D (C)
12
D (D)
13
14 = KB (D)
15 = A (D)
[VCC]
16
C4019BS: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
B4
2 = A3
3
B3
4
A2
5 = B2
6
Al
(
000-0081-01
ill
7
8
9
10
11
SIGNAL
B1
[GND]
KA
D1
D2
ill
12
SIGNAL
D3
13 = D4
14
KB
15 = A4
16 = [VCC]
37
CMOS Family Components
38
C4020B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
= Q12
Q13
= Q14
= Q6
= Q5
ill
7
8
9
10
11
SIGNAL
ill
= Q4
= [GND]
= Q1
= ClK
12
13
14
15
16
RESET
Q7
SIGNAL
(
= Q9
Q8
Q10
= Q11
= [VCC]
"'-
/
C4021B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
= PIN8
= POUT6
POUT8
PIN4
PIN3
PIN2
ill
7
8
9
10
11
SIGNAL
ill
= PIN1
= [GND]
12
13
14
15
16
PSC
ClK
SIN
SIGNAL
= POUT7
= PINS
PIN6
PIN7
[VCC]
C4022B: NUMBER OF GATES PER PACKAGE
,
\
ill
1
2
3
4
5
6
SIGNAL
Q1
QO
Q2
= Q5
Q6
(n/c)
ill
SIGNAL
ill
7
8
9
10
11
Q3
[GND]
(n/c)
Q7
Q4
12
13
14
15
16
C4023B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
INA
INB
INA
INB
INC
(A)
(A)
(B)
(B)
(B)
ill
6
7
8
9
10
SIGNAL
OUTY (B)
[GND]
INC (A)
OUTY (A)
OUTY (C)
SIGNAL
'-
CO
ClKE'
ClK
RST
[VCC]
3
ill
11
12
13
14
SIGNAL
INC (C)
(C)
INA (C)
[VCC]
= INB
,/
\~
000-0081-01
,J
Schematic Symbols
C4024B: NUMBER OF GATES PER PACKAGE
.'
.~
:~
ill
1
2
3
4
5
SIGNAL
ClK
RESET
Q7
Q6
Q5
ill
6
7
8
9
10
SIGNAL
ill
Q4
[GND]
{n/c}
Q3
{n/c}
11
12
13
14
C4025B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
,
,~
SIGNAL
= INA
INB
= INA
= INB
(A)
(A)
(B)
(B)
INC (B)
ill
SIGNAL
= Q2
Q1
= {n/c}
[VCC]
=3
SIGNAL
ill
OUTY (B)
[GND]
8 = INC (A)
OUTY (A)
9
OUTY (C)
10
11
12
13
14
6
7
SIGNAL
= INC
INB
= INA
(C)
(C)
(C)
[VCC]
C4026B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
ill
SIGNAL
ill
SIGNAL
,~
1
2
3
4
5
6
ClK
ClK-INH
DEIN
= DEOUT
CO
F
7
8
9
10
11
=G
C4027B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
Q (B)
QI (B)
ClK (B)
RESET (B)
K (B)
J (B)
(
000-0081-01
ill
7
8
9
10
11
12
13
14
15
16
[GND]
D
A
E
B
C
= UG-C
RESET
[VCC]
2
SIGNAL
ill
SIGNAL
SET (B)
[GND]
SET (A)
J (A)
K (A)
12
13
14
15
16
RESET (A)
ClK (A)
QI (A)
= Q (A)
[VCC]
39
CMOS Family Components
40
C4028B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
4
2
=0
7
9
5
ill
7
8
9
10
11
SIGNAL
1
2
3
4
5
6
SIGNAL
PE
Q4
= JAM4
JAM1
CIN'
Q1
ill
7
8
9
10
11
ill
1
2
3
4
5
SIGNAL
INA (A)
INB (A)
OUTY (A)
OUTY (B)
INA (B)
ill
6
7
8
9
10
12
13
14
15
16
ill
= CO'
12
13
14
15
16
[GND]
BID
= U/D
Q2
ill
INB (B)
11
12
13
14
INA (C)
INB (C)
OUTY (C)
/'
\
'-
-/
,/
'-,
1
3
= [VCC]
SIGNAL
= JAM2
JAM3
Q3
CLK
[VCC]
4
SIGNAL
= [GND]
=C
=B
=
SIGNAL
C4030B: NUMBER OF GATES PER PACKAGE
SIGNAL
/
=6
= [GND]
=8
A
=D
C4029B: NUMBER OF GATES PER PACKAGE
ill
ill
SIGNAL
\
'-
/
OUTY (D)
(D)
INB (D)
[VCC]
= INA
C4031B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
DIN2
= CLK
= {n/c}
= {n/c}
QBAR
=Q
ill
7
8
9
10
11
SIGNAL
Q'
= [GND]
CLKD
SEL
{n/c}
ill
12
13
14
15
16
SIGNAL
{n/c}
{n/c}
{n/c}
DIN1
[VCC]
/
\
000-0081-01
,7
Schematic Symbols
C4032B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
ill
SUM (C)
INV (C)
ClK (C)
SUM (B)
I NV (B)
CR (C)
7
8
9
10
11
SIGNAL
1
2
3
4
5
6
SIGNAL
SUM3
INV3
ClK
SUM2
INV2
CR
ill
7
8
9
10
11
ill
= INV
(A)
[GND]
SUM (A)
A (A)
B (A)
C4032BS: NUMBER OF GATES PER PACKAGE
ill
3
SIGNAL
= INV1
[GND]
SUM1
Al
Bl
12
SIGNAL
14
15
16
B (B)
A (B)
B (C)
A (C)
[VCC]
ill
SIGNAL
13
=
12
13
14
15
16
B2
A2
B3
A3
[VCC]
C4033B: NUMBER OF GATES PER PACKAGE
1:1$,
ill
1
2
3
4
5
6
SIGNAL
ill
ClK
ClK-INH
RBI
RBO
7
8
9
10
11
co
SIGNAL
=G
[GND]
0
A
E
ill.
12
13
14
15
16
SIGNAL
B
C
LT
RESET
[VCC]
F
C4034B: NUMBER OF GATES PER PACKAGE
ill.
1
2
3
4
5
6
7
8
SIGNAL
B8
B7
B6
B5
B4
B3
B2
B1
000-0081-01
ill.
SIGNAL
ill
9
10
11
12
EN-A
SERIN
A-B
[GND]
P-S
A-S
ClK
A1
17
18
19
20
21
22
23
24
13
14
15
16
SIGNAL
= A2
A3
= A4
A5
A6
A7
A8
[VCC]
41
CMOS Family Components
42
C4035B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
= Q1
TIC
K'
J
= RESET
ill
SIGNAL
7
8
ill
12
PIS
[GND)
9
PI - 1
10 = PI-2
11
PI-3
SIGNAL
VCC (C)
1
2 = B (C)
3 = C (A)
A (C)
4
C (B)
5
ill
= PI-4
/'
'\
\"
Q4
Q3
14
Q2
15
16 = [VCC)
13
CLK
C4037A: NUMBER OF GATES PER PACKAGE
SIGNAL
ill
=3
SIGNAL
6 = C (C)
7 = [GND]
D (C)
8
E (C)
9
D (B)
10
ill
SIGNAL
11
12
14
E (B)
E (A)
D (A)
[VCC]
ill
SIGNAL
13
C4037AS: NUMBER OF GATES PER PACKAGE
/'
ill
1
2
3
4
5
SIGNAL
VCC
=B
C1
A
C2
ill
6
7
8
9
10
SIGNAL
C3
[GND)
D3
E3
D2
C4038B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
SUM (C)
INV (C)
CLK (C)
SUM (B)
INV (B)
= CR (C)
ill
7
8
9
10
11
11
12
13
14 =
"
\
./
!
E2
E1
D1
[VCC)
=3
SIGNAL
ill
I NV (A)
[GND)
SUM (A)
A (A)
B (A)
12
13
14
15
16
SIGNAL
B (B)
A (B)
B (C)
A (C)
= [VCC]
,
C
\
,/
000-0081 -01
Schematic Symbols
C4038BS: NUMBER OF GATES PER PACKAGE
m
1
2
3
4
5
6
SIGNAL
SUM3
INV3
ClK
SUM2
INV2
CR
m
7
8
9
10
11
m
SIGNAL
INV1
[GND]
SUM1
A1
B1
12
13
14
15
16
SIGNAL
B2
A2
B3
A3
[VCC]
C4040B: NUMBER OF GATES PER PACKAGE
m
1
2
3
4
5
6
,
6{
SIGNAL
012
06
05
07
04
03
ill
7
8
9
10
11
m
SIGNAL
02
[GND]
01
ClK
RESET
12
13
14
15
16
C4041UB: NUMBER OF GATES PER PACKAGE
m
1
2
3
4
5
SIGNAL
OUT (A)
OUT' (A)
IN (A)
OUT (B)
OUT' (B)
m
6
7
8
9
10
ill
1
2
3
4
5
6
SIGNAL
o (D)
o (A)
0' (A)
D (A)
ClK (D)
POL (D)
(
000-0081-01
09
08
010
011
[VCC]
4
m
SIGNAL
IN (B)
[GND]
OUT (C)
OUT' (C)
IN (C)
C4042B: NUMBER OF GATES PER PACKAGE
SIGNAL
11
12
13
14
SIGNAL
OUT (D)
OUT' (D)
IN (D)
[VCC]
4
ill
SIGNAL
ill
SIGNAL
7
D (B)
[GND]
0' (B)
o (B)
o (Cl
12
13
14
15
16
0' (C)
D (C)
D (D)
0' (D)
[VCC]
8
9
10
11
43
CMOS Family Components
44
C4042BS: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
04
= 01
01'
= D1
eLK
= POL
ill
7
8
9
10
11
SIGNAL
= D2
= [GND)
02'
= 02
= 03
C4043B: NUMBER OF GATES PER PACKAGE
SIGNAL
ill
(D)
(A)
= R (A)
S (A)
EN (D)
5
S (B)
6
7
8
ill
1
2
3
4
Q
Q
ill
12
13
14
15
16
SIGNAL
03'
D3
D4
= 04'
[vCC)
!
~,
"
=4
SIGNAL
= R (B)
[GND)
9 = o (B)
o (C)
10
R (e)
11
ill
12
13
14
15
16
SIGNAL
S (e)
= {n/e}
= S (D)
= R (D)
= [vce)
e4043BS: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
04
01
R1
S1
EN
S2
ill
7
8
9
10
11
SIGNAL
R2
= [GND)
02
Q3
R3
ill
12
13
14
15
16
,;/
SIGNAL
S3
= {n/e}
S4
R4
[vee)
C4044B: NUMBER OF GATES PER PACKAGE = 4
SIGNAL
ill
1 o (D)
{n/e}
2
3 = S (A)
R (A)
4
EN (D)
5
R (B)
6
7
8
ill
SIGNAL
S (B)
= [GND)
o (B)
9
10 = o (C)
S (C)
11
ill
SIGNAL
R (C)
12
13 = Q (A)
R (D)
14
S (D)
15
[VCC)
16
!
\,
000-0081-01
j
schematic Symbols
C4044BS: NUMBER OF GATES PER PACKAGE
m
1
2
3
4
5
6
SIGNAL
m
Q4
7
{n/c}
8
9
S1
R1
EN
R2
10
11
SIGNAL
S2
[GND]
Q2
Q3
S3
E..!J!
12
13
14
15
16
SIGNAL
R3
Q1
R4
S4
[VCC]
C4045B: NUMBER OF GATES PER PACKAGE
m
1
2
3
4
5
6
SIGNAL
SP
SN
[VCC]
{n/c}
{n/c}
{n/c}
E..!J!
7
8
9
10
11
SIGNAL
Y
Y+D
{n/c}
{n/c}
{n/c}
E..!J!
12
13
14
15
16
SIGNAL
{n/c}
{n/c}
[GND]
xo
X1
C4046B: NUMBER OF GATES PER PACKAGE
m
1
2
3
4
5
6
SIGNAL
PPULSE
PCOMP1
COMP
VCOOUT
INH
cl -1
E..!J!
7
8
9
10
11
SIGNAL
E..!J!
SIGNAL
C1 - 2
[GND]
VCOIN
DMOD
RXl
12
13
14
15
16
RX2
PCOMP2
SIGIN
ZENER
[VCC]
SIGNAL
PIN
SIGNAL
N- TR I G
[GND]
P-TRIG
EX-RSET
11
12
13
14
Q'
RE-TRIG
OSC-OUT
[VCC]
C4047B: NUMBER OF GATES PER PACKAGE
E..!J!
1
2
3
4
5
SIGNAL
C
R
RC-COM
ASTABL'
ASTABL
(
000-0081-01
PIN
6
7
8
9
10
Q
45
CMOS Family Components
46
C4048B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
J
KD
=H
=G
=F
ill
7
8
9
10
11
SIGNAL
= KB
= [GND]
1
2
3
4
5
6
1
2
3
4
5
6
12
14
15
16
C
=B
A
EXPAND
= [VCC]
SIGNAL
E
SIGNAL
= [VCC]
OUT (A)
IN (A)
= OUT (B)
IN (B)
OUT (C)
SIGNAL
ill
7
8
9
10
11
= IN (C)
= [GND]
12
13
14
15
16
SIGNAL
ill
IN (D)
OUT (D)
IN (E)
[VCC]
OUT (A)
IN (A)
OUT (B)
IN (B)
= OUT (C)
7
8
9
10
11
SIGNAL
= IN
(C)
[GND]
IN (D)
OUT (D)
IN (E)
/
\
6
ill
C4050B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
13
KC
KA
D
C4049UB: NUMBER OF GATES PER PACKAGE
ill
ill
= OUT (E)
= (n/c)
= IN (F)
= OUT (F)
(n/c)
=6
/
ill
SIGNAL
12
= OUT (E)
(n/c}
IN (F)
= OUT (F)
{n/c}
13
14
15
16
/
C4051B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
4
6
0/1
=7
5
INH
ill
7
8
9
10
11
SIGNAL
VEE
[GND]
C
B
A
ill
12
13
14
15
16
SIGNAL
3
=0
=1
2
= [VCC]
(
000-0081-01
,7'
Schematic Symbols
C4052B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
YO
2 = Y2
3
YOII
4
Y3
5 = Yl
6
INH
ill
7
SIGNAL
VEE
8 = [GND]
B
9
10
11
A
X3
ill
SIGNAL
12
XO
XOII
14
Xl
15
X2
16 = [VCC]
13
C4053B: NUMBER OF GATES PER PACKAGE =
ill
SIGNAL
1
BY
2 = BX
3
CY
4
COli
5 = CX
6
INH
,~r
ill
7
SIGNAL
VEE
8 = [GND]
C
9
10
11
B
A
ill
12
SIGNAL
AX
13 = AY
14
AOII
15
BOil
16 = [VCC]
C4054B: NUMBER OF GATES PER PACKAGE
1,;1:.,
~,
ill
1
2
3
4
5
6
SIGNAL
STRB4
DFIN
OUT4
OUT3
OUT2
OUTl
ill
SIGNAL
VEE
[GND]
INl
10
STRBl
11 = IN2
7
8
9
ill
SIGNAL
12
13
14
15
16
STRB2
IN3
STRB3
IN4
[VCC]
ill
SIGNAL
C4055B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
DFOUT
IN2
INl
IN3
INO
DFIN
(
000-0081-01
ill
7
SIGNAL
VEE
[GND]
A
10 = B
11
C
8
9
12
13
14
15
16
D
E
G
F
[VCC]
47
CMOS Family Components
48
C4056B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6 =
SIGNAL
STRB
IN2
IN1
IN3
INO
OFIN
ill
SIGNAL
7
VEE
8 = [GNO]
9
A
10
B
11
C
ill
SIGNAL
12 = 0
13
E
14 = G
15
F
16 = [VCC]
(
"
;'
C4057A: NUMBER OF GATES PER PACKAGE =
ill
SIGNAL
1 = 01
2 = 04
3
02
4
NEG
5
ZI/lN
6
SELC
7
SELD
8
COND/A
9 = COND/C
10
RIGHT
ill
SIGNAL
11 = BYPASS
{n/e}
12
13
M1
14
ROT1
15
M2
16
O/FLOW
17
O/IND
18
LEFT
CONO/B
19
ill
SIGNAL
20 = CLK
21
SELB
22
SELA
23 = O/CNTRL
24
ZI/OUT
[GND]
25
[VCC]
26
03
27
28
ROT2
,,'.'
C4059A: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
8 =
SIGNAL
CLK
L
J1
J2
J3
J4
J16
J15
ill
9
10
11
12
13
14
15
16
SIGNAL
J 14
J13
KC
[GNO]
KB
KA
J12
J 11
ill
17
18
19
20
21
22
23
24
SIGNAL
J10
J9
J8
J7
J6
J5
OUT
[vec]
C4060B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = Q12
Q13
2
Q14
3
Q6
4
Q5
5
Q7
6
ill
7
8
9
10
11
SIGNAL
Q4
[GNO]
FYO
FYO'
FYI
£.D!
SIGNAL
12
13
14
15
16
RESET
Q9
08
Q10
[vec]
000-0081-01
(/
Schematic Symbols
C4063B: NUMBER OF GATES PER PACKAGE
"
"
(
ill
SIGNAL
B3
1
IAB
A>B
5
A=B
6
ill
SIGNAL
7 = A8
5
IA<8
6
IA=B
ill
7
8
9
10
11
SIGNAL
A1
[GNO]
B1
AO
80
ill
SIGNAL
AB
13
14 = 83
15
A3
16 = [VCC]
C4724B: NUMBER OF GATES PER PACKAGE =
ill
SIGNAL
1 = AO
2
A1
3
A2
QO
4
Q1
5
Q2
6
ill
SIGNAL
Q3
7
8 = [GNO]
Q4
9
Q5
10
11 = Q6
ill
~
Q7
12
DATA
13
14 = WR-OIS
15 = RESET
[VCC]
16
C22104A: NUMBER OF GATES PER PACKAGE
~.
~
ill
SIGNAL
[VCC]
1
2
E1
3
G1
4
F1
5
BP- 10
6
A2
7
B2
8
C2
9
02
10 = E2
11
G2
12
F2
13 = A3
14
B3
(
000-0081-01
ill
SIGNAL
C3
15
03
16
17
E3
18 = G3
19
F3
A4
20
B4
21
22
C4
04
23
24
E4
G4
25
26
F4
27 = BO
ill
SIGNAL
28 = B1
29
B2
B3
30
31
01
02
32
03
33
04
34
[GNO]
35
36 = OSC-IN
37
A1
B1
38
39
C1
01
40
61
CMOS Family Components
62
C22105A: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = [VCC]
2
E1
3 = G1
4
F1
BP-IO
5
6 = A2
7
B2
8
C2
9
D2
10
E2
11
G2
12
F2
13 = A3
14
B3
ill
SIGNAL
15
C3
16
D3
E3
17
18
G3
19 = F3
20 = A4
21 = B4
22
C4
23 = D4
24
E4
25 = G4
F4
26
27
BO
ill
SIGNAL
/~
= B1
B2
= B3
DSC1
= DSC2
28
29
30
31
32
33
34
35
36
37
38
39
40
CS1
CS2
[GND]
= OSC-IN
= A1
= B1
C1
D1
ill
SIGNAL
I
~--
C22859: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
= [VCC]
TX
C1
= C2
C3
[GND]
ill
SIGNAL
7
8
OSC1
OSC2
9
C4
10
RX
11 = R4
12
13
14
15
16
R3
R2
R1
CD'
= VOUT
C40100B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
(n/e}
CINH
CLK
SLO
(n/e}
ill
7
8
9
10
11
SIGNAL
ill
(n/e}
12
[GND]
RC
13
{n/e}
SRI
14
15
16
SIGNAL
SRO
L/R
(n/e}
{n/e}
[VCC]
SLI
C40101B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
D1
02
03
04
D9
ill
6
7
8
9
10
SIGNAL
ODD
[GND]
INH
EVEN
05
ill
11
12
13
14
SIGNAL
06
07
08
[VCC]
000-0081-01
('
Schematic Symbols
C40102B: NUMBER OF GATES PER PACKAGE
4
.~
"
ill
SIGNAL
1 = ClK
ClR'
2
CI-CE'
3
JO
4
5
J1
J2
6
ill
SIGNAL
7
J3
8
9
[GNO]
APE'
J4
J5
10
11
ill
SIGNAL
12
13
14
15
16
J6
J7
CO-ZO'
SPE'
[VCC]
ill
SIGNAL
C40103B: NUMBER OF GATES PER PACKAGE
,
rJ~
~
ill
SIGNAL
1
2
3
4
5
6
ClK
ClR'
CI -CE'
JO
J1
J2
ill
SIGNAL
7 = J3
8 = [GNO]
9
APE'
10 = J4
11
J5
12
J6
J7
13
14 = CO-ZO'
15
SPE'
[VCC]
16
C40104B: NUMBER OF GATES PER PACKAGE =
ill
1
2
3
4
5
6
SIGNAL
OE
SRIN
DO
01
02
03
ill
7
SIGNAL
SLIN
[GNO]
8
9 = SO
10
11
S1
ClK
ill
12
13
14
15
16
SIGNAL
Q3
Q2
Q1
QO
[VCC]
C40105B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
2
3
4
5
6
OE'
OIR
SHFT-I
DO
01
02
(
000-0081-01
ill
SIGNAL
7 = 03
[GNO]
MR
Q3
10
Q2
11
8
9
ill
SIGNAL
12
13
14
15
16
Q1
QO
OOR
SHFT-O
[VCC]
63
CMOS Family Components
64
C40106B: NUMBER OF GATES PER PACKAGE
ill
=
=
=
=
5 =
1
2
3
4
SIGNAL
IN (A)
OUT (A)
IN (B)
OUT (B)
IN (C)
ill
SIGNAL
SIGNAL
1 = {n/c}
{n/c}
2
INA (A)
3
INB (A)
4
OUTY (A)
5
ill
6 = OUT (C)
7 = [GND]
OUT (D)
8
IN (D)
9
OUT (E)
10
C40107B: NUMBER OF GATES PER PACKAGE
ill
6
ill
SIGNAL
11 = IN (E)
12
OUT (F)
13 = IN (F)
14
[VCC]
/
/
~.
'.
"
..7
2
SIGNAL
ill
6 = {n/c}
7 = [GND]
{n/c}
8
OUTY (B)
9
10 = INB (B)
SIGNAL
11
INA (B)
12 = {n/c}
{n/c}
13
[VCC]
14
C40108B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = Q3B
Q2B
2
3
ENA
4 = QOA
5 = Q1A
Q2A
6
7 = Q3A
IJO
8
ill
SIGNAL
9 = IJ1
R1B
10
11
ROB
[GND]
12
ROA
13
R1A
14
15
IJREN
16
CLK
C40109B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
vcc (D)
1
EN (A)
2
A (A)
3
4 = E (A)
E (B)
5
(,
A (B)
ill
17
18
19
20
21
22
23
24
SIGNAL
= D3
= D2
= D1
DO
ENB
= QOB
Q1B
[VCC]
(
"-,
4
ill
SIGNAL
ill
7
8
9
10
11
EN (B)
[GND]
EN (C)
A (C)
E (C)
12
SIGNAL
{n/c}
E (D)
14 = A (D)
EN (D)
15
[VCC]
16
13
(
~
000-0081-01
'/
Schematic Symbols
C40109BS: NUMBER OF GATES PER PACKAGE
ill
"
\;t
1
2
3
4
5
6
SIGNAL
VCC
ENA
A
=E
F
B
ill
7
8
9
10
11
SIGNAL
ENB
[GND]
ENC
C
G
ill
SIGNAL
12
13
14
15
16
{n/c}
H
0
END
[VCC]
C40110B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
=A
G
F
= TOG-EN'
RESET
LE
ill
SIGNAL
ill
7
= CLK-DN
12
13
14
15
16
8
9
10
11
[GND]
CLK-UP
CARRY
BORROW
SIGNAL
=E
0
C
B
[VCC]
C40115: NUMBER OF GATES PER PACKAGE
.¢j
\ •.10
\~
ill
1
2
3
4
5
6
7
8
SIGNAL
= [VCC]
A1
= A2
= A3
A4
= A5
= A6
= A7
ill
9
10
11
12
13
14
15
SIGNAL
= A8
EN
[GND]
{n/c}
DIS
B8
B7
ill
16
17
18
19
20
21
22
SIGNAL
B6
B5
B4
B3
B2
B1
VCC
C40116: NUMBER OF GATES PER PACKAGE
ill
-
(
1
2
3
4
5
6
7
8
SIGNAL
[VCC]
A1
A2
A3
ill
9
10
11
12
A4
13
A5
A6
A7
14
15
000-0081-01
SIGNAL
A8
EN
[GND]
GND2
DIS
B8
B7
ill
16
17
18
19
20
21
22
SIGNAL
B6
B5
B4
B3
B2
B1
vee
65
CMOS Family Components
66
C40117B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
STRB (A)
STRB (B)
1 (A)
= 2 (A)
3 (A)
ill
SIGNAL
4 (A)
= [GND]
4 (B)
8
3 (B)
9
2 (B)
10
6
7
2
ill
11
12
13
14
SIGNAL
''\
1 (B)
DATA (B)
DATA (A)
[VCC]
}
C40147B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
4
5
=6
7
8
ill
7
8
9
10
11
SIGNAL
B
[GND]
A
9
1
ill
12
13
14
15
16
SIGNAL
2
3
=D
0
[VCC]
C
C40160B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
CLR'
CLK
= Pl
= P2
P3
P4
ill
7
8
9
10
11
SIGNAL
PE
[GND]
LOAD'
TE
Q4
ill
12
13
14
15
16
SIGNAL
/
"
,
,
/
Q3
Q2
Ql
COUT
[VCC]
C40161B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
= CLR'
CLK
Pl
P2
P3
P4
ill
7
8
9
10
11
SIGNAL
PE
[GND]
LOAD'
TE
Q4
t.lli
12
13
14
15
16
SIGNAL
Q3
Q2
Ql
COUT
[VCC]
('
000-0081-01
Schematic Symbols
C40162B: NUMBER OF GATES PER PACKAGE
rt'
~.
ill
SIGNAL
1 = ClR'
2
ClK
3
P1
4
P2
5
P3
6
P4
ill
7
8
9
10
11
SIGNAL
ill
12
PE
[GND]
lOAD'
TE
Q4
13
14
15
16
SIGNAL
Q3
Q2
Q1
COUT
[VCC]
C40163B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = ClR'
2
ClK
3
P1
4 = P2
5
P3
6
P4
/,"
ft:or
I{
ill
SIGNAL
SIGNAL
1
ClR' ( F)
Q (A)
2
3 = D (A)
4
D (B)
5 = Q (B)
6
D (C)
ill
7
8
9
10
11
SIGNAL
Q3
12
13 = Q2
14 = Q1
15
COUT
[VCC]
16
7 = PE
[GND]
8
9
lOAD'
10 = TE
Q4
11
C40174B: NUMBER OF GATES PER PACKAGE
ill
ill
6
SIGNAL
ill
Q (C)
[GND]
ClK (F)
Q (D)
D (D)
12
13
14
15
16
SIGNAL
Q (E)
D (E)
D (F)
Q (F)
[VCC]
C40174BS: NUMBER OF GATES PER PACKAGE = 1
ill
1
2
3
4
5
6
SIGNAL
ClR'
Q1
D1
D2
Q2
D3
(
000-0081-01
ill
7
8
9
10
11
SIGNAL
Q3
[GND]
ClK
Q4
04
ill
SIGNAL
Q5
D5
14 = D6
Q6
15
16
[VCC]
12
13
67
CMOS Family Components
68
C40175B: NUMBER OF GATES PER PACKAGE
SIGNAL
ill
1 = CLR' (D)
2 Q (A)
3 = Q' (A)
D (A)
4
5 = D (B)
Q' (B)
6
ill
4
SIGNAL
Q (B)
7
8 = [GND]
CLK (D)
9
10 = Q (C)
11 = Q' (C)
ill
SIGNAL
D (C)
12
13 = D (D)
Q' (D)
14
Q (D)
15
16 = [VCC]
(
"
\
"'-
j
/
",
C40175BS: NUMBER OF GATES PER PACKAGE =
SIGNAL
ill
1
2
3
4
5
6
CLR'
= Q1
= Q1'
D1
= D2
= Q2'
ill
SIGNAL
Q2
7
[GND]
8
9 = CLK
10 = Q3
Q3'
11
ill
SIGNAL
12
D3
13
D4
14 = Q4'
Q4
15
[VCC]
16
C40181B: NUMBER OF GATES PER PACKAGE =
SIGNAL
ill
1
2
3
4
5
6
7
8
BO'
= AO'
= S3
S2
S1
SO
= CN
= M
ill
SIGNAL
9
FO'
10 = Fl'
11 = F2'
[GND]
12
13 = F3'
14
A=B
15
P'
16 = CN+4
ill
SIGNAL
,
/
/
17
G'
18 = B3'
19
A3'
20
B2'
21
A2'
22
B1'
23 = Al'
[VCC]
24
C40182B: NUMBER OF GATES PER PACKAGE =
ill
1
2
3
4 =
5
6
SIGNAL
G1'
P1'
GO'
PO'
G3'
P3'
ill
SIGNAL
7 = P'
[GND]
8
CN+Z
9
10
G'
11 = CN+Y
ill
SIGNAL
CN+X
12
13 = CN
14
G2'
15
P2'
[VCC]
16
000-0081-01
(~j
Schematic Symbols
C40192B: NUMBER OF GATES PER PACKAGE
£
\~
'<.
ill
SIGNAL
1
J2
Q2
2
Q1
3
4
CLK-D
5 = CLK-U
Q3
6
ill
SIGNAL
7 = Q4
[GND]
8
9
J4
10
J3
11
PE'
ill
SIGNAL
12 = CARRY'
13
BORR'
14
RESET
15
J1
[VCC]
16
C40193B: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = J2
Q2
2
Q1
3
4
CLK-D
5
CLK-U
Q3
6
ill
SIGNAL
Q4
7
[GND]
8
9 = J4
10 = J3
11
PE'
ill
SIGNAL
12
CARRY'
13
BORR'
14 = RESET
15 = J1
[VCC]
16
C40194B: NUMBER OF GATES PER PACKAGE
;:[
\'~
~
ill
SIGNAL
1
RESET'
2
SRIN
3 = DO
4
D1
5 = D2
6
D3
ill
SIGNAL
7
SLlN
8 = [GND]
9
SO
10
S1
11
CLK
ill
SIGNAL
12 = Q3
Q2
13
Q1
14
QO
15
[VCC]
16
C40208B: NUMBER OF GATES PER PACKAGE
ill
(
SIGNAL
1 = Q3B
Q2B
2
3
ENA
4 = QOA
Q1A
5
Q2A
6
7 = Q3A
WO
8
000-0081-01
ill
9
10
11
12
13
14
15
16
SIGNAL
W1
ROB
R1B
[GND]
ROA
R1A
WREN
CLK
ill
SIGNAL
17 = D3
18
D2
19 = D1
20
DO
21
ENB
QOB
22
23 = Q1B
[VCC]
24
69
CMOS Family Components
70
C40257B: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
IN-SEL (D)
= A (A)
B (A)
D (A)
A (B)
B (B)
ill
7
SIGNAL
SIGNAL
ill
1
2
3
4
5
6
= IN-SEL
= A1
= B1
= D1
8
7
9
10
11
13
14
15
16
SIGNAL
ill
1
2
3
4
5
INA (A)
INB (A)
OUTY (A)
= INA (B)
INB (B)
ill
6
7
1
2
3
4
5
SIGNAL
= OUTY
(A)
INA (A)
INB (A)
OUTY (B)
INA (B)
ill
6
7
"
/
= D4
= 84
A4
OUT-DIS
[VCC]
I
ill
= OUTY (B)
= [GND]
11
12
13
14
SIGNAL
\,
-
= OUTY
(D)
INA (D)
INB (D)
[vec]
=4
SIGNAL
ill
SIGNAL
= I NB (B)
= [GND]
11
12
13
14
INA (D)
INB (D)
OUTY (D)
= [vee]
INA (C)
INB (C)
10 = OUTY (C)
8
9
/'
\~
SIGNAL
=4
SIGNAL
H02: NUMBER OF GATES PER PACKAGE
ill
12'
13
14
15
16
OUTY (C)
INA (C)
10 = INB (C)
8
9
D (D)
B (D)
A (D)
OUT-DIS (D)
[VCC]
=1
ill
= D2
= [GND]
= D3
= B3
= A3
HOO: NUMBER OF GATES PER PACKAGE
SIGNAL
I
12
[GND]
D (C)
B (e)
10
11 = A (C)
8
9
ill
SIGNAL
ill
= D (B)
e40257BS: NUMBER OF GATES PER PACKAGE
A2
B2
4
(
~
000-0081-01
,'/
Schematic Symbols
H03: NUMBER OF GATES PER PACKAGE
(
ill
1
2
3
4
S
SIGNAL
INA (A)
(A)
OUTY (A)
INA (B)
INB (B)
= INB
SIGNAL
ill
= OUTY (B)
= [GND]
11
12
ill
6
7
8
OUTY (C)
INA (C)
INB (C)
9
10
H04: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
A (A)
6
A (B)
7
8
0 (B)
9
A (C)
10
,
N~
'"
~
ill
1
2
3
4
S
SIGNAL
=A
y
(A)
(A)
A (B)
Y (B)
= A (C)
(C)
[GND]
o (D)
A (D)
o (E)
11
12
13
14
y (C)
1
2
3
4
5
SIGNAL
INA (A)
(A)
OUTY (A)
INA (B)
INB (B)
= INB
(
000-0081-01
11
12
13
14
=
H08: NUMBER OF GATES PER PACKAGE
ill
ill
[GND]
Y (D)
A (D)
9
10 = Y (E)
7
8
SIGNAL
ill
6
7
8
9
10
=
OUTY (D)
(D)
INB (D)
[VCC]
= INA
SIGNAL
= A (E)
= o (F)
A (F)
= [VCC]
=6
SIGNAL
ill
6
ill
o
HOS: NUMBER OF GATES PER PACKAGE
13
14
SIGNAL
=6
SIGNAL
ill
0 (A)
=4
OUTY (B)
[GND]
OUTY (C)
INA (C)
INB (C)
SIGNAL
= A (E)
= Y (F)
= A (F)
[VCC]
4
ill
11
12
13
14
SIGNAL
OUTY (D)
(D)
(D)
[VCC]
= INA
= INB
71
CMOS Family Components
72
H10: NUMBER OF GATES PER PACKAGE = 3
ill
SIGNAL
1
INA (A)
2 = INB (A)
3
INA (B)
4 = INB (B)
INC (B)
5
ill
SIGNAL
6 = OUTY (B)
7 = [GND]
8 = OUTY (C)
9 = INA (C)
INB (C)
10
ill
SIGNAL
11 = INC (C)
12
OUTY (A)
13 = INC (A)
14 = [VCC]
(
~
,
"
",,,-l
H11: NUMBER OF GATES PER PACKAGE = 3
ill
SIGNAL
INA (A)
1
2 = INB (A)
3 = INA (B)
4
INB (B)
INC (B)
5
ill
SIGNAL
6 = OUTY (B)
7 = [GND]
8 = OUTY (C)
9 = INA (C)
10
INB (C)
ill
SIGNAL
11 = INC (C)
12
OUTY (A)
13
INC (A)
14 = [VCC]
H14: NUMBER OF GATES PER PACKAGE = 6
ill
SIGNAL
IN (A)
1
OUT (A)
2
3 = IN (B)
4 = OUT (B)
IN (C)
5
ill
SIGNAL
6 = OUT (C)
7 = [GND]
OUT (D)
8
IN (D)
9
10
OUT (E)
ill
SIGNAL
11 = IN (E)
12 = OUT (F)
IN (F)
13
[VCC]
14
H20: NUMBER OF GATES PER PACKAGE = 2
ill
1
2
3
4
5
SIGNAL
I NA (A)
INB (A)
{n/c}
INC (A)
I NO (A)
ill
SIGNAL
6 = OUTY (A)
7 = [GND]
OUTY (B)
8
INA (B)
9
INB (B)
10
ill
SIGNAL
11 = (n/c}
INC (B)
12
13 = IND (B)
14
[VCC]
000-0081-01
/
"
Schematic Symbols
,
J'
H21: NUMBER DF GATES PER PACKAGE
SIGNAL
ill
INA (A)
INB (A)
{n/c}
INC CA)
IND (A)
1
2
3
4
5
ill
6
7
8
9
1D
SIGNAL
DUTY (A)
[GND]
DUTY (B)
INA (B)
INB (B)
H27: NUMBER DF GATES PER PACKAGE
SIGNAL
ill
1
2
3
4
5
=
INA
INB
INA
INB
INC
(A)
CA)
(B)
(B)
(B)
ill
6
7
8
9
1D
li>t:
~
SIGNAL
ill
1
2
3
4
5
=
INA
INB
INC
IND
INE
ill
DUTY (B)
[GND]
DUTY (C)
INA (C)
INB (C)
= I NF
= [GND]
8
9
DUTY'
{n/c}
{n/c}
10
H32: NUMBER DF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
I NA (A)
INB (A)
DUTY (A)
INA (B)
INB (B)
000-0081-01
ill
6
7
8
9
10
SIGNAL
11
12
13
14
{n/c}
INC (B)
(B)
= IND
= [VCC]
ill
SIGNAL
INC (C)
DUTY (A)
13 = INC (A)
[VCC]
14
11
12
=
SIGNAL
6
7
ill
=3
SIGNAL
H30: NUMBER DF GATES PER PACKAGE
,~
=2
ill
SIGNAL
11
12
13
14
ING
INH
{n/c}
[VCC]
ill
SIGNAL
=4
SIGNAL
DUTY (B)
[GND]
DUTY (C)
INA (C)
INB (C)
11
12
13
14
DUTY (D)
INA (D)
INB (D)
[VCC]
73
CMOS Family Components
74
H42: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
YO'
= Y1'
Y2'
Y3'
Y4'
Y5'
ill
7
8
9
10
11
SIGNAL
1
2
3
4
5
6
SIGNAL
= 00'
= 01'
02'
03'
04'
05'
ill
7
8
9
10
11
ill
12
13
14
15
16
Y6'
[GNO]
Y7'
Y8'
Y9'
H44: NUMBER OF GATES PER PACKAGE
ill
=
(
\'--
A3
A2
A1
AD
[vec]
ill
= 06'
[GNO]
= 07'
12
13
14
15
16
08'
09'
SIGNAL
A3
A2
A1
= AD
[vec]
=
I
/
"
PIN
-1
2
3
4
5
SIGNAL
= A-1-A2
B2
C2
02
PIN
6"
7
8
9
10
ill
1
2
3
4
5
SIGNAL
ill
ClK (A)
ClR' (A)
K (A)
= [VCC]
ClK (B)
6
7
8
9
10
"
12
13
14
SIGNAL
F1
B1
C1
[VCC]
ill
SIGNAL
PIN
SIGNAL
yz[GNO]
Y1
01
E1
H73: NUMBER OF GATES PER PACKAGE
",
-/
=
SIGNAL
H51: NUMBER OF GATES PER PACKAGE
SIGNAL
"
\
=2
SIGNAL
ClR' (B)
J (B)
Q' (B)
Q (B)
K (B)
11
12
13
14
[GND]
Q (A)
Q' (A)
J (A)
(
000-0081-01
,
\
I
/
Schematic Symbols
H74 : NUMBER OF GATES PER PACKAGE = 2
Ell!.
1
2
3
4
5
SIGNAL
ClR' (A)
D (A)
ClK (A)
PR' (A)
Q (A)
Ell!.
6
7
8
9
10
SIGNAL
Ell!.
(A)
[GND]
Q' (B)
Q (B)
PR' (B)
11
12
13
14
Q'
SIGNAL
ClK (B)
D (B)
ClR' (B)
[VCC]
H75: NUMBER OF GATES PER PACKAGE = 4
Ell!.
1
2
3
4
5
6
SIGNAL
(A)
D (A)
D (B)
G (C,D)
[VCC]
D (C)
Q'
Ell!.
7
8
9
10
11
SIGNAL
Ell!.
SIGNAL
D (D)
(D)
(D)
(C)
(C)
12
13
14
15
16
[GND]
G (A,B)
Q' (B)
Q (B)
Q (A)
Q'
Q
Q
Q'
H76: NUMBER OF GATES PER PACKAGE = 2
PIN
1
2
3
4
5
6
SIGNAL
ClK (A)
PR' (A)
ClR' (A)
J (A)
[VCC]
ClK (B)
Ell!.
7
8
9
10
11
SIGNAL
PR' (B)
ClR' ( B)
J (B)
Q' (B)
Q (B)
!:l.f!.
SIGNAL
12
13
14
15
16
K (B)
[GND]
Q' (A)
Q (A)
K (A)
Ell!.
SIGNAL
H85: NUMBER OF GATES PER PACKAGE =
Ell!.
1
2
3
4
5
6
SIGNAL
B3
IAB
A>B
A=B
(
000-0081-01
PIN
7
8
9
10
11
SIGNAL
AB
4
A>B
5
6
A=B
ill
SIGNAL
ill
7 = A
l~,
!:.!Ji
SIGNAL
7 = Y (A)
[GND]
8
Y (B)
9
CO (B)
10
11
C1 (B)
!:.!Ji
SIGNAL
12 = C2 (B)
C3 (B)
14
AO
15
OE' (B)
[VCC]
16
13
HT153S: NUMBER OF GATES PER PACKAGE
!:.!Ji
1
2
3
4
5
6
SIGNAL
10E'
A1
1C3
1C2
1C1
1CO
!:.!Ji
SIGNAL
7
1Y
8 = [GND]
9
2Y
10
2CO
11
2C1
!:.!Ji
SIGNAL
12 = 2C2
2C3
13
14
AO
15
20E'
[VCC]
16
HT154: NUMBER OF GATES PER PACKAGE
!:.!Ji
f
SIGNAL
1 = YO'
Y1'
2
3 = Y2'
Y3'
4
5 = Y4'
Y5'
6
7
Y6'
8
Y7'
000-0081-01
!:.!Ji
SIGNAL
9
Y8'
10 = Y9'
11
Y10'
[GND]
12
13
Y11 '
14
Y12'
15
YB'
16
Y14'
!:.!Ji
17
18
19
20
21
22
23
24
SIGNAL
Y15'
El'
E2'
A3
A2
A1
AO
[VCC]
119
CMOS Family Components
120
HT157: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
SEL
= A (A)
= B (A)
= Y (A)
= A (B)
B (B)
ill
7
8
9
10
11
SIGNAL
1
2
3
4
5
6
llill!&
SEL
= 1A
= 1B
1Y
= 2A
ill
7
8
9
10
11
2B
ill
= Y (B)
= [GNO]
= Y (C)
B (C)
= A (C)
HT157S: NUMBER OF GATES PER PACKAGE
ill
=4
12
13
14
15
16
Y (D)
= B (D)
= A (D)
OE'
= [VCC]
ill
= 2Y
= [GNO]
= 3Y
3B
= 3A
12
13
14
15
16
4Y
4B
= 4A
OE'
= [VCC]
=4
'\
SIGNAL
ill
llill!&
ill
SIGNAL
1
2
3
4
5
6
= SEL
= A (A)
= B (A)
= Y' (A)
= A (B)
7
8
= Y' (B)
= [GNO]
12
13
14
15
16
= Y' (D)
= B (D)
ill
SIGNAL
9
B (B)
Y' (C)
B (C)
= A (C)
."
>~
SIGNAL
ill
10
11
/'
=
SIGNAL
HT158: NUMBER OF GATES PER PACKAGE
llill!&
A (D)
OE'
[VCC]
HT158S: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
SEL
1A
1B
1Y'
2A
2B
ill
7
8
9
10
11
SIGNAL
= 2Y'
= [GNO]
= 3Y'
= 3B
3A
12
13
14
15
16
4Y'
4B
4A
OE'
[VCC]
C
-,
000-0081-01
"
000-0081-01
CMOS Family Components
122
HT164: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = A
2 = B
QA
3
4
OB
5 = OC
ill
6
7
8
9
10
SIGNAL
QO
[GNO]
ClK
ClR'
QE
ill
11
12
13
SIGNAL
QF
QG
QH
14
[vec]
ill
SIGNAL
HT165: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
= Pl'
ClK
= 04
= 05
06
= 07
ill
SIGNAL
7
Q7'
12
8
9
[GNO]
Q7
OS
DO
13 = 02
10
11
01
14 = 03
15
CE'
[vec]
16
HT166: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
ill
SIGNAL
ill
SIGNAL
/
\
1
OS
2
DO
3 = 01
4 = 02
5 = 03
6
CE'
7
8
9
10
11
ClK
[GNO]
MR'
04
05
12
06
13 = Q7
07
14
15
PE'
[VCC]
16
'-
/'
HT173: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
OE1'
2
OE2'
3 = QO
Q1
4
5 = Q2
Q3
6
ill
7
8
9
10
11
SIGNAL
ClK
[GNO]
El'
E2'
03
ill
SIGNAL
12
02
13 = 01
14
DO
15 = MR
[VCC]
16
('
000-0081-01
Schematic Symbols
HT174: NUMBER OF GATES PER PACKAGE
ill.
1
2
3
4
5
6
SIGNAL
ClR'
o (A)
D
D
0
D
(A)
(B)
(B)
(C)
ill.
SIGNAL
7
o (C)
8
9
[GND]
ClK
o (D)
D (D)
10
11
6
ill.
12
13
14
15
16
SIGNAL
o (E)
D (E)
D (F)
o
(F)
[VCC]
HT 174S: NUMBER OF GATES PER PACKAGE
ill.
1
2
3
4
5
6
('
''I'
SIGNAL
ClR'
01
D1
D2
02
03
ill.
7
8
9
10
11
SIGNAL
ill.
03
[GND]
ClK
04
D4
HT 175: NUMBER OF GATES PER PACKAGE
12
13
14
15
16
SIGNAL
05
D5
D6
06
[VCC]
4
ii~
ill.
1
2
3
4
5
6
SIGNAL
ClR'
o (A)
0' (A)
D (A)
o (B)
0' (8)
ill.
SIGNAL
7
o (B)
8
9
[GNO]
ClK
o (C)
0' (C)
10
11
ill.
12
13
14
15
16
SIGNAL
D (C)
(D)
0' (D)
o (D)
[VCC]
o
HT175S: NUMBER OF GATES PER PACKAGE
ill.
(
1
2
3
4
5
6
SIGNAL
ClR'
01
01 '
01
02
02'
000-0081-01
ill.
7
8
9
10
11
SIGNAL
02
[GNO]
ClK
03
03'
ill.
12
13
14
15
16
SIGNAL
03
04
04'
04
[VCC]
123
CMOS Family Components
124
HT181 : NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = BO
AO
2
3 = S3
4
S2
5 = S1
6
SO
CN'
7
8
M
ill
SIGNAL
9
FO
10
F1
11
F2
12 = [GND]
13
F3
14
A=B
15
P
CN+4'
16
ill
17
18
19
20
21
22
23
24
SIGNAL
G
B3
A3
B2
A2
Bl
A1
[VCC]
/\
'~./
I"
HT182: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = Gl'
Pl'
3 = GO'
PO'
4
G3'
5
6
P3'
2
ill
SIGNAL
7
P7'
8 = [GND]
CN+Z
9
10
G'
CN+Y
11
ill
SIGNAL
CN+X
12
13
CN
14 = G2'
15
P2'
[VCC]
16
(
I
HT190: NUMBER OF GATES PER PACKAGE =
ill
SIGNAL
1 = P1
Q1
QO
3
4
CE'
5
DIU'
Q2
6
2
ill
7
8
9
10
11
SIGNAL
Q3
[GND]
P3
P2
PL'
ill
12
SIGNAL
14
15
16
TC
RC'
CP
PO
[VCC]
ill
SIGNAL
13
'"
'\
I
./
HT191 : NUMBER OF GATES PER PACKAGE =
ill
SIGNAL
1 = P1
Q1
2
QO
3
4
CE'
5 = DIU'
Q2
6
ill
7
8
9
10
11
SIGNAL
Q3
[GND]
P3
P2
PL'
12
13
14
15
16
TC
RC'
CP
PO
[VCC]
000-0081-01
(
.
;
/
Schematic Symbols
HT192: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
P1
01
00
CPO
CPU
02
ill
7
8
9
10
11
SIGNAL
03
[GNO]
p3
P2
PL'
ill
12
13
14
15
16
SIGNAL
TCU'
TCO'
MR
PO
[VCC]
HT193: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
P1
01
00
CPO
CPU
02
ill
7
8
9
10
11
SIGNAL
03
[GNO]
P3
P2
PL'
ill
12
13
14
15
16
SIGNAL
TCU'
TCO'
MR
PO
[VCC]
HT194: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
CLR'
SR
A
B
C
0
ill
7
8
9
10
11
SIGNAL
SL
[GNO]
SO
S1
CLK
ill
12
13
14
15
16
SIGNAL
00
OC
OB
OA
[VCC]
HT195: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
MR'
J
K'
DO
01
02
(:
000-0081-01
ill
7
8
9
10
11
SIGNAL
03
[GNO]
PE'
CLK
03'
ill
12
13
14
15
16
SIGNAL
03
02
01
00
[VCC]
125
CMOS FamiLy Components
126
HT221 : NUMBER OF GATES PER PACKAGE
ill
SIGNAL
ill
1
2
3
4
5
6
= A' (A)
= B (A)
R' (A)
= Q' (A)
Q (B)
= ex (B)
7
8
9
10
11
2
SIGNAL
ill
RXCX (B)
[GND]
A' (B)
B (B)
R' (B)
12
SIGNAL
Q'
(B)
13 = Q (A)
CX (A)
14
15 = RXCX (A)
16 = [Vce]
HT237: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
AO
A1
A2
LE'
OE1'
OEO
ill
SIGNAL
ill
12,=
13 =
14 =
15 =
16 =
7 = Y7
[GND]
8
9
Y6
10
Y5
11
Y4
SIGNAL
Y3
Y2
Y1
YO
[VCC]
HT238: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
AO
2
A1
3 = A2
4
El'
5 = E2'
6
E3
ill
SIGNAL
SIGNAL
1 = OE' (A)
AO (A)
2
3 = Y3' (B)
A1 (A)
4
5
Y2' (B)
A2 (A)
6
7
Y1' (B)
ill
ill
SIGNAL
8
9
10
11
12
13
14
A3 (A)
YO' (B)
[GND]
AO (B)
Y3' (A)
A1 (B)
Y2' (A)
"
SIGNAL
Y3
Y2
14
Y1
15 = YO
[vec]
16
7 = Y7
[GND]
8
9
Y6
10
Y5
11
Y4
HT240: NUMBER OF GATES PER PACKAGE
ill
('
12
13
2
ill
SIGNAL
15 = A2 (B)
16 = Y1' (A)
17 = A3 (B)
18
YO' (A)
19
OE' (B)
[vec]
20
000-0081-01
(
/
/
Schematic Symbols
HT240S: NUMBER OF GATES PER PACKAGE
ill
(
1
2
3
4
5
6
7
SIGNAL
OE1'
1AO
2Y3'
= 1A1
2Y2'
1A2
2Y1'
ill
8
9
10
11
12
13
14
SIGNAL
1A3
2YO'
[GND]
2AO
1Y3'
2A1
1Y2'
ill
SIGNAL
15
16
17
18
19
20
2A2
1Y1'
2A3
1YO'
OE2'
[VCC]
ill
SIGNAL
HT241: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
1G'
1A1
2Y4
1A2
2Y3
1A3
2Y2
ill
8
9
10
11
12
13
14
SIGNAL
1A4
2Y1
[GND]
2A1
1Y4
2A2
1Y3
15
16
17
18
19
20
= 2A3
= 1Y2
2A4
1Y1
= 2G
[VCC]
..
4
,If
"
HT242: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
OEB'
= {n/c}
AO
A1
A2
ill
6
7
8
9
10
SIGNAL
A3
[GND]
B3
B2
B1
ill
SIGNAL
11
12
14
BO
{n/c}
OEA
[VCC]
ill
SIGNAL
11
12
13
14
BO
{n/c}
OEA
[VCC]
13
HT243: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
ill
OEB'
{n/c}
AO
A1
A2
6
7
8
9
10
(
000-0081-01
SIGNAL
A3
[GND]
B3
B2
B1
127
CMOS Family Components
128
HT244: NUMBER OF GATES PER PACKAGE
E.!J!
1
2
3
4
5
6
7
2
SIGNAL
E.!J!
SIGNAL
E.!J!
SIGNAL
DE' (A)
AO (A)
Y3 (B)
A1 (A)
Y2 (B)
A2 (A)
Y1 (B)
8
9
10
11
12
A3 (A)
YO (B)
[GNO]
AO (B)
Y3 (A)
A1 (B)
Y2 (A)
15
16
18
19
20
A2 (B)
Y1 (A)
A3 (B)
YO (A)
DE' (B)
[VCC]
E.!J!
SIGNAL
13
14
17
HT244S: NUMBER OF GATES PER PACKAGE
E.!J!
1
2
3
4
5
6
7
SIGNAL
DE l'
1AO
2Y3
1A1
2Y2
1A2
2Y1
E.!J!
8
9
10
11
12
13
14
SIGNAL
1A3
2YO
[GNO]
2AO
1Y3
2A1
1Y2
15
16
17
18
19
20
2A2
1Y1
2A3
1Y0
DE2'
[VCC]
HT245: NUMBER OF GATES PER PACKAGE
E.!J!
1
2
3
4
5
6
7
SIGNAL
OIR
A1
A2
A3
A4
A5
A6
E.!J!
8
9
10
11
12
13
14
SIGNAL
A7
A8
[GNO]
B8
B7
B6
B5
E.!J!
15
16
17
18
19
20
SIGNAL
B4
B3
B2
B1
DE'
[VCC]
HT251: NUMBER OF GATES PER PACKAGE
E.!J!
1
2
3
4
5
6
SIGNAL
03
02
01
DO
Y
Y'
E.!J!
7
8
9
10
11
SIGNAL
DE'
[GNO]
A2
A1
AO
E.!J!
12
13
14
15
16
SIGNAL
07
06
05
04
[VCC]
000-0081-01
Schematic Symbols
HT253: NUMBER OF GATES PER PACKAGE
ill
(
SIGNAL
1 = OE' (A)
S1
2
13 (A)
3
4
12 (A)
11 (A)
5
6
10 (A)
ill
7
8
9
10
11 =
2
SIGNAL
ill
SIGNAL
Y (A)
[GND]
Y (B)
10 (B)
11 (B)
12
14
15
16
12 (B)
13 (B)
SO
OE' (B)
[VCC]
ill
SIGNAL
13
HT253S: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = 10E'
S1
2
3
113
4
112
111
5
6
110
ill
SIGNAL
7 = 1Y
[GND]
8
9
2Y
10
210
11
211
12
13
14
15
16
212
213
SO
20E'
[VCC]
HT257: NUMBER OF GATES PER PACKAGE
(
ill
1
2
3
4
5
6
SIGNAL
SEL
1A
1B
1Y
2A
2B
ill
7
8
9
10
11
SIGNAL
2Y
[GND]
3Y
3B
3A
ill
12
13
14
15
16
SIGNAL
4Y
4B
4A
OE'
[VCC]
HT258: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
SEL
1A
1B
1Y'
2A
2B
(
000-0081-01
ill
7
8
9
10
11
SIGNAL
2Y'
[GND]
3Y'
3B
3A
ill
12
13
14
15
16
SIGNAL
4Y'
4B
4A
OE'
[VCC]
129
CMOS Family Components
130
HT259: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = AO
2
A1
3 = A2
QO
4
Q1
5
Q2
6
ill
7
8
9
10
11 =
SIGNAL
Q3
[GND]
Q4
Q5
Q6
HT266: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = INA (A)
INB (A)
2
OUTY (A)
3
OUTY (B)
4
INA (B)
5
ill
6
7
8
9
10
ill
SIGNAL
INB (B)
[GND]
INA (C)
INB (C)
OUTY (C)
12
13
14
15
16
SIGNAL
Q7
D
LE
MR'
[VCC]
("
,
j
4
ill
SIGNAL
OUTY (D)
11
12 = INA (D)
INB (D)
13
[VCC]
14
HT273: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = CLR'
Q1
2
3
D1
4
D2
5 = Q2
03
6
7
D3
ill
8
9
10
11
12
13
14
SIGNAL
D4
Q4
[GND]
CLK
Q5
D5
D6
ill
15
16
17
18
19
20
SIGNAL
(
\
Q6
Q7
D7
D8
Q8
[VCC]
"'-.
"
HT280: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
16
17
{n/c}
18
EVEN
ill
6
7
8
9
10
SIGNAL
ODD
[GND]
10
11
12
ill
SIGNAL
11
12
13
14
13
14
15
[VCC]
C-,~
000-0081-01
Schematic Symbols
HT283: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
S1
B1
A1
SO
AO
BO
ill
7
8
9
10
11
SIGNAL
CIN
[GNO)
COUT
S3
B3
m
12
13
14
15
16
SIGNAL
A3
S2
A2
B2
[VCC)
HT297: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
ill
SIGNAL
m
1
2
3
4
5
6
B
A
ENCTR
K/CLK
ID/CLK
D/U'
7
8
9
10
11
ID/OUT
[GND)
FY/A1
FY /B
XORPD
12
13
14
15
16
SIGNAL
ECPD
FY/A2
D
C
[VCC)
HT299: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
SO
OE l'
OE2'
1/06
1/04
1/02
1/00
ill
8
9
10
11
12
13
14
SIGNAL
QO
MR'
[GND)
DSO
CLK
1/01
1/03
m
15
16
17
18
19
20
SIGNAL
1/05
1/07
Q7
Ds7
S1
[VCC)
HT354: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
(
6
7
SIGNAL
D7
06
D5
04
03
02
01
000-0081-01
ill
8
9
10
11
12
13
14
SIGNAL
00
E'
[GND]
LE'
S2
S1
sa
m
15
16
17
18
19
20
SIGNAL
DE l'
OE2'
oE3
Y'
Y
[VCC]
131
CMOS Family Components
132
HT356: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
D7
D6
D5
D4
= D3
D2
D1
ill
8
9
10
11
12
13
14
SIGNAL
DO
CLK
[GND]
LE'
S2
S1
SO
HT365 : NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
OE l'
A (A)
Y (A)
A (B)
Y (B)
A (C)
ill
7
8
9
10
11
ill
15
16
17
18
19
20
SIGNAL
OE l'
OE2'
OE3
Y'
Y
[Vee]
6
SIGNAL
ill
Y (e)
[GND]
Y (D)
A (D)
Y (E)
SIGNAL
12
13
14
15
16
A (E)
Y (F)
A (F)
OE2'
[vee]
ill
SIGNAL
HT365S: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
OE l'
1A
1Y
2A
2Y
3A
ill
7
8
9
10
11
SIGNAL
3Y
[GND]
4Y
4A
5Y
HT366: NUMBER OF GATES PER PACKAGE
12
SA
13
6Y
14
15
16
6A
OE2'
[VCC]
6
ill
SIGNAL
ill
SIGNAL
ill
SIGNAL
1
2
3
4
5
OE l'
A (A)
Y' (A)
A (B)
Y' (B)
A (C)
7
8
9
10
11
Y' (e)
[GND]
Y' (D)
A (D)
Y' (E)
12
13
14
15
16
A (E)
Y' (F)
A (F)
OE2'
[Vce]
6
000-0081-01
Schematic Symbols
,
I~
HT366S: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
OE1'
2 = lA
3
lY'
4
2A
5 = 2Y'
6
3A
ill
7
8
9
10
11
SIGNAL
3Y'
[GNO]
4Y'
4A
5Y'
ill
llill1.
12
5A
13
6Y'
14
6A
15 = OE2'
[VCC]
16
HT367: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
OE1'
2 = lA
lY
3
4
2A
5 = 2Y
6
3A
~,
ill
7
8
9
10
11
SIGNAL
3Y
[GNO]
4Y
4A
5Y
ill
SIGNAL
12 = 5A
13
6Y
14
6A
15 = OE2'
[VCC]
16
HT368: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
OE1'
lA
1Y'
2A
2Y'
3A
ill
7
8
9
10
11
SIGNAL
3Y'
[GNO]
4Y'
4A
5Y'
ill
12
13
14
15
16
llill1.
5A
6Y'
6A
OE2'
[VCC]
HT373: NUMBER OF GATES PER PACKAGE
ill
(
SIGNAL
1 = OE'
2
00
3
00
4
01
5
01
6
02
7
02
000-0081-01
ill
SIGNAL
8
03
9 = 03
[GNO]
10
11
LE'
12
04
13
04
14
05
ill
15
16
17
18
19
20
SIGNAL
05
06
06
07
07
[VCC]
133
CMOS Family Components
134
HT374 : NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
OE'
1Q
10
20
2Q
3Q
3D
ill
8
9
10
11
12
13
14
SIGNAL
1
2
3
4
5
6
SIGNAL
o (A)
QI (A)
Q (A)
EN (A,B)
Q (B)
Q' (B)
ill
7
8
9
10
11
15
16
17
18
19
20
40
4Q
[GNO]
CLK
5Q
5D
60
HT375 : NUMBER OF GATES PER PACKAGE
ill
ill
SIGNAL
SIGNAL
6Q
7Q
7D
80
8Q
[VCC]
4
ill
o (B)
12
[GNO]
o (C)
Q' (C)
Q (C)
13
14
15
16
SIGNAL
EN (C,O)
Q (D)
Q' (D)
D (D)
[VCC]
HT375S: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
D1
Q1 '
Q1
EN1
Q2
Q2'
ill
7
8
9
10
11
SIGNAL
D2
[GNO]
D3
Q3'
Q3
ill
12
13
14
15
16
SIGNAL
EN2
Q4
Q4'
D4
[vec]
HT377: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
EN'
1Q
1D
20
2Q
3Q
3D
ill
8
9
10
11
12
13
14
SIGNAL
4D
4Q
[GND]
CLK
5Q
5D
6D
ill
15
16
17
18
19
20
SIGNAL
6Q
7Q
70
8D
8Q
[VCC]
000-0081-01
000-0081-01
CMOS Family Components
136
HT534: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
S
6
7
SIGNAL
OE'
Q1'
01
02
Q2'
Q3'
03
ill
8
9
10
11
12
13
14
SIGNAL
04
Q4'
[GNO]
CLK
Q5'
05
06
ill
15
16
17
18
19
20
SIGNAL
Q6'
Q7'
07
08
Q8'
[VCC]
HT540: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
OE l'
= AO
A1
= A2
A3
A4
AS
ill
8
9
10
11
12
13
14
SIGNAL
A6
A7
[GNO]
Y7'
Y6'
Y5'
Y4'
ill
15
16
17
18
19
20
SIGNAL
Y3'
Y2'
Yl'
YO'
OE2'
[VCC]
HT541: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
OE1'
AO
A1
A2
A3
A4
AS
ill
8
9
10
11
12
13
14
SIGNAL
A6
A7
[GNO]
Y7
Y6
Y5
Y4
ill
15
16
17
18
19
20
SIGNAL
Y3
Y2
Y1
YO
OE2'
[VCC]
HT563: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
OE'
00
01
02
03
04
D5
ill
8
9
10
11
12
13
14
SIGNAL
06
07
[GNO]
LE'
07'
06'
05'
ill
15
16
17
18
19
20
SIGNAL
Q4'
Q3'"
Q2'
Q l'
00'
[VeCl
000-0081-01
."
;
Schematic Symbols
HT564: NUMBER DF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
DE'
00
01
02
03
04
05
ill
8
9
10
11
12
13
14
SIGNAL
06
07
[GNO]
ClK
07'
06'
05'
ill
15
16
17
18
19
20
SIGNAL
04'
03'
02'
01'
00'
[VCC]
HT573: NUMBER DF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
DE'
00
01
02
03
04
05
ill
8
9
10
11
12
13
14
SIGNAL
06
07
[GNO]
lE'
07
Q6
05
ill
15
16
17
18
19
20
SIGNAL
04
03
02
01
00
[VCC]
HT574: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
DE'
DO
01
02
03
04
05
ill
8
9
10
11
12
13
14
SIGNAL
06
07
[GNO]
ClK
07
Q6
05
ill
SIGNAL
18
19
20
04
Q3
02
Q1
QO
[VCC]
ill
SIGNAL
15
16
17
HT583: NUMBER OF GATES PER PACKAGE
ill
(
1
2
3
4
5
6
SIGNAL
B1
B2
B3
A3
CN
CN+4
000-0081-01
ill
7
8
9
10
11
SIGNAL
S2
[GND]
S3
s1
so
12
13
14
15
16
BO
AO
A1
A2
[VCC]
137
CMOS Family Components
138
HT597: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
=B
=C
=D
E
F
G
ill
SIGNAL
ill
SIGNAL
7
8
9
10
11
H
[GND]
QH
RESET
SH-CLK
12
13
14
15
16
LT-CLK
SS-PL
SA
A
[VCC]
ill
SIGNAL
(
'"
i
"'-
HT640: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
= DIR
= AD
= A1
= A2
= A3
= A4
= A5
ill
8
9
10
11
12
13
14
SIGNAL
A6
A7
[GND]
B7
B6
B5
B4
15
16
17
18
19
20
B3
B2
B1
BO
OE'
[VCC]
(
HT643: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
= DIR
AD
A1
= A2
A3
A4
A5
ill
8
9
10
11
12
13
14
SIGNAL
A6
A7
[GND]
B7
B6
B5
B4
ill
15
16
17
18
19
20
SIGNAL
"
/'
B3
B2
B1
BO
OE'
[VCC]
HT646: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
8
SIGNAL
= CAB
SAB
DIR
AD
A1
A2
A3
A4
ill
9
10
11
12
13
14
15
16
SIGNAL
A5
A6
A7
[GND]
B7
B6
B5
B4
ill
17
18
19
20
21
22
23
24
SIGNAL
B3
B2
B1
BO
OE'
SBA
CBA
[VCC]
000-0081-01
C~
Schematic Symbols
HT648: NUMBER OF GATES PER PACKAGE
~
!~
ill
SIGNAL
1 = CAB
SAB
2
3 = OIR
4
AO
5
A1
6 = A2
7
A3
8
A4
ill
9
10
11
12 =
13
14
15
16
SIGNAL
ill
SIGNAL
17
B3
B2
18
19 = B1
20
BO
21
DE'
22 = SBA
CBA
23
[VCC]
24
AS
A6
A7
[GNO]
B7
B6
B5
B4
HT670: NUMBER DF GATES PER PACKAGE
ill
SIGNAL
1
01
2 = 02
03
3
4
RA1
5
RAO
Q3
6
ill
7
8
9
10
11
SIGNAL
ill
Q2
[GNO]
Q1
QO
RE'
SIGNAL
12
liE'
13 = IIA1
IIAO
14
DO
15
[VCC]
16
HT688: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
SIGNAL
E'
AO
BO
A1
B1
A2
B2
ill
8
9
10
11
12
13
14
SIGNAL
A3
B3
[GNO]
(
1
2
3
4
5
SIGNAL
DUTY (A)
INA (A)
INB (A)
INC (A)
INO (A)
000-0081-01
ill
6
7
8
9
10
15
16
17
18
19
20
A4
B4
AS
B5
HT4002: NUMBER OF GATES PER PACKAGE
ill
ill
SIGNAL
A6
B6
A7
B7
y
[VCC]
2
SIGNAL
ill
{n/c}
[GNO]
{n/c}
INA (B)
I NB (B)
11
12
13
14
SIGNAL
INC (B)
INO (B)
DUTY (B)
[VCC]
139
CMOS Family Components
140
HT4015: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
= ClK (B)
= Q4 (A)
Q3 (A)
= Q2 (A)
= Q1 (A)
MR (A)
6
1
2
3
4
5
ill
7
8
9
10
11 =
2
SIGNAL
DATA (A)
[GND]
ClK (A)
Q4 (B)
Q3 (B)
ill
12
13
14
15
16 =
SIGNAL
Q2 (B)
Q1 (B)
MR (B)
DATA (B)
[VCC]
i- -',
I
~-
HT4016: NUMBER OF GATES PER PACKAGE = 4
ill
SIGNAL
1 = 10 (A)
2
01 (A)
01 (B)
3
10 (B)
4
CNTRl (B)
5
ill
SIGNAL
6 = CNTRl (C)
7
8
9
10
[GND]
10 (C)
01 (C)
01 (D)
ill
11
12
13
14
SIGNAL
10 (D)
CNTRl (D)
CNTRl (A)
(VCC]
HT4017: NUMBER OF GATES PER PACKAGE =
ill
SIGNAL
1 = Q5
Q1
2
QO
3
4 = Q2
5 = Q6
6 = Q7
ill
SIGNAL
7 = Q3
[GND]
8
Q8
9
Q4
10
Q9
11
ill
12
13
14
15
16
SIGNAL
-,
i
\ ,
--
TC
CE'
ClK
MR
[VCC]
HT4020: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
= Q12
= Q13
= Q14
Q6
= Q5
Q7
ill
SIGNAL
7 = Q4
[GND]
8
Q1
9
10 = ClK
11
MR
ill
12
13
14
15
16 =
SIGNAL
Q9
Q8
Q10
Q11
[VCC]
C,,:i
000-0081-01
Schematic Symbols
HT4024: NUMBER OF GATES PER PACKAGE
~
!~
ill
1
2
3
4
5
SIGNAL
ClK
MR
Q7
Q6
Q5
ill
SIGNAL
ill
6
7
8
9
10
Q4
[GND]
{n/c}
Q3
{n/c}
11
12
13
14
SIGNAL
Q2
Q1
{n!c}
[VCC]
HT4040: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
Q12
Q6
Q5
Q7
Q4
Q3
PIN
7
8
9
10
11
SIGNAL
ill
Q2
[GND]
Q1
ClK
MR
12
13
14
15
16
SIGNAL
Q9
Q8
Q10
Q11
[VCC]
HT4046: NUMBER OF GATES PER PACKAGE
,"
i
\\
ill
1
2
3
4
5
6
SIGNAL
ill
SIGNAL
ill
SIGNAL
P-PUlSE
P-COMP1
COMP
VCO-OUT
INH
C1-1
7
8
9
10
11
C1-2
[GND]
VCO-IN
DMOD
R1
12
13
14
15
16
R2
P-COMP2
SIG- IN
ZENER
[VCC]
HT4049: NUMBER OF GATES PER PACKAGE
PIN
1
2
3
4
5
6
SIGNAL
[vec]
Y'
A
Y'
A
Y'
(A)
(A)
(B)
(B)
(
000-0081-01
(e)
PIN
SIGNAL
7
A (e)
[GND]
A (D)
Y' (D)
A (E)
8
9
10
11
6
ill
SIGNAL
12
Y' (E)
{n/c}
A (F)
Y' ( F)
{n!c}
13
14
15
16
141
CMOS Family Components
142
HT4050: NUMBER OF GATES PER PACKAGE
SIGNAL
ill
[VCC]
1
Y (A)
2
A (A)
3
4 = Y (B)
5 A (B)
Y (C)
6
ill
SIGNAL
7 = A (C)
8 = [GND]
9 = A (D)
10 = Y (D)
11 = A (E)
6
ill
SIGNAL
12
Y (E)
(
,,/
13 = {n/c}
A (F)
14
Y (F)
15
16 = {n/c}
HT4051: NUMBER OF GATES PER PACKAGE
SIGNAL
ill
1
2
3
4
5
6
=
=
=
=
A4
A6
AD/I
A7
AS
EI
ill
7
SIGNAL
VEE
[GND]
8
9 = S2
10
S1
11 = SO
ill
12
SIGNAL
A3
13 = AO
14
A1
15 = A2
[VCC]
16
/
HT4052: NUMBER OF GATES PER PACKAGE =
ill
SIGNAL
1 = BO
B2
2
3
BOil
4 = B3
5
B1
EI
6
ill
7
SIGNAL
VEE
8 = [GND]
9
S1
10
11
SO
A3
ill
./-'
SIGNAL
12
AO
13
AOII
14 = A1
15
A2
[VCC]
16
HT4053: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 B1
2 = BO
3
C1
4 = COli
5
CO
EI
6
ill
7
SIGNAL
VEE
8 = [GND]
9
S2
10
11
S1
SO
ill
12
13
14
15
16
SIGNAL
AO
A1
AOII
BOil
[VCC]
(
~
000-0081-01
Schematic Symbols
HT4059: NUMBER OF GATES PER PACKAGE
('
ill
SIGNAL
1
CLK
2
lE
3
J1
4
J2
5 = J3
6
J4
7
J16
8 = J15
ill
SIGNAL
ill
SIGNAL
Jl0
17
18 = J9
19
J8
20
J7
J6
21
22
J5
Q
23
[VCC]
24
J14
9
10
J13
11 = S2
[GND]
12
13
S1
14 = SO
15
J12
16
J 11
HT4060: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
Q12
Q13
Q14
Q6
Q5
Q7
ill
7
8
9
10
11
SIGNAL
ill
Q4
[GND]
FYO
FYO'
FYI
12
13
14
15
16
SIGNAL
MR
Q9
Q8
Q10
[VCC]
/~
1\
HT4066: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
~
SIGNAL
10 (A)
01 (A)
01 (B)
10 (B)
CNTRL (B)
ill
6
7
8
9
10
SIGNAL
CNTRL (C)
[GND]
10 (C)
01 (C)
01 (D)
4
ill
11
12
13
14
SIGNAL
10 (D)
CNTRL (D)
CNTRL (A)
[VCC]
HT4067: NUMBER OF GATES PER PACKAGE
SIGNAL
ill
1
OUT /IN
2 = 17
3
16
15
4
5
14
6
13
7
12
8
11
9
10
11
12
ill
(
000-0081-01
13
14
15
16
SIGNAL
10
SO
51
[GND]
53
52
E'
115
ill
17
18
19
20
21
22
23
24
SIGNAL
114
113
112
111
110
19
18
[VCC]
143
CMOS Family Components
144
HT4075: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
INA
INB
INA
INB
INC
(A)
(A)
(B)
(B)
(B)
ill
6
7
8
9
10
3
SIGNAL
OUTY (B)
[GND]
INC (A)
OUTY (A)
OUTY (C)
ill
SIGNAL
11
12
INA (C)
INB (C)
INC (C)
[VCC]
13
14
HT4078: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
SIGNAL
K
A
B
C
D
ill
SIGNAL
ill
6
7
8
9
10
{n/c}
[GND]
{n/c}
E
F
11
12
13
14
SIGNAL
G
H
y
[VCC]
HT4094: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
STR
DS
CP
QO
Q1
Q2
ill
7
8
9
10
11
SIGNAL
Q3
[GND]
QS
QS'
Q7
HT4316: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
X (A)
Y (A)
Y (B)
X (B)
CNTRL (B)
CNTRL (C)
ill
7
8
9
10
11
ill
12
13
14
15
16
SIGNAL
Q6
Q5
Q4
OE
[VCC]
4
SIGNAL
ill
EN
[GND]
VEE
X (C)
Y (C)
12
13
14
15
16
SIGNAL
Y (D)
X (D)
CNTRL (D)
CNTRL (A)
[VCC]
000-0081-01
'-"'C.
Schematic Symbols
HT4316S: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
XA
2 = YA
YB
3
4 = XB
5
BC
6
CC
ill
SIGNAL
7 = EN
[GND]
8
9
VEE
10
XC
11
YC
ill
SIGNAL
12
13
14
15
16
YO
XD
DC
AC
[VCC]
ill
SIGNAL
HT4351: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
X4
2 = X6
3
X
4
X7
5
X5
6 = ENl '
ill
SIGNAL
7 = EN2
8
VEE
[GND]
9
10
LE
11
C
12
B
13
14
15
16
17
18
A
X3
XO
Xl
X2
[VCC]
HT4352: NUMBER OF GATES PER PACKAGE
(:,
.~
ill
SIGNAL
1
YO
2
Y2
3
Y
Y3
4
5 = Yl
EN1'
6
ill
SIGNAL
7 = EN2
8
VEE
[GND]
9
10
LE
B
11
12
A
ill
13
14
15
16
17
18
SIGNAL
X3
xo
X
Xl
X2
[VCC]
HT4353: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1
YI
2 = YO
ZI
3
4
Z
5
ZO
EN2'
6
(
000- 0081-01
ill
7
8
9
10
11
12
SIGNAL
ENl
VEE
[GND]
LE
C
B
ill
13
14
15
16
17
18
SIGNAL
A
XO
XI
X
Y
[VCC]
145
CMOS Family Components
146
HT4510: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
PE
Q4
P4
P1
CIN'
Q1
ill
SIGNAL
ill
7
8
9
10
11
COUT'
[GND]
RESET
UfD
Q2
12
13
14
15
16
SIGNAL
P2
P3
Q3
CLK
[VCC]
/
(
".
/
HT4511: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
INB
INC
LT'
BLI
LE'
IND
ill
7
8
9
10
11
SIGNAL
INA
[GND]
E
D
C
ill
12
13
14
15
16
SIGNAL
B
A
G
F
[VCC]
HT4514: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
7
8
SIGNAL
LEI
AO
A1
Y7
Y6
Y5
Y4
Y3
ill
SIGNAL
9 = Y1
10
Y2
11
YO
[GND]
12
13
YB
14
Y12
15
Y15
16
Y14
,
/
ill
17
18
19
20
21
22
23
24
SIGNAL
-
Y9
Y8
Y11
Y10
A2
A3
E'
[VCC]
HT4515: NUMBER OF GATES PER PACKAGE
ill
SIGNAL
1 = LE'
AO
2
3
A1
4
Y7'
5
Y6'
6
Y5'
7
Y4'
8
Y3'
ill
9
10
11
12
13
14
15
16
SIGNAL
Y1 I
Y2'
YO'
[GND]
Y13'
Y12'
Y15'
Y14'
ill
17
18
19
20
21
22
23
24
SIGNAL
Y9'
Y8'
Y11'
Y10'
A2
A3
E'
[VCC]
000-0081-01
(
~
,7
Schematic SymboLs
HT4516: NUMBER OF GATES PER PACKAGE
(il
ill
1
2
3
4
5
6
SIGNAL
PE
= Q4
P4
P1
CIN'
Q1
ill
7
8
9
10
11
SIGNAL
ill
COUT'
[GND]
RESET
UfD
Q2
12
13
14
15
16
HT4518: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
ClK (A)
E (A)
QO (A)
Q1 (A)
= Q2 (A)
Q3 (A)
ill
ill
1
2
3
4
5
6
SIGNAL
= ClK
(A)
E (A)
QO (A)
Q1 (A)
Q2 (A)
Q3 (A)
MR (A)
[GND]
ClK (B)
9
10 = E (B)
QO (B)
11
7
8
9
10
11
1
2
3
4
5
6
SIGNAL
CX (B)
RXCX (B)
R' (B)
A (B)
B' (B)
Q (B)
(
000-0081-01
ill
7
8
9
10
11
2
ill
MR (A)
[GND]
ClK (B)
E (B)
QO (B)
2
ill
Q' (B)
12
13
14
15
16
Q' (A)
Q (A)
B' (A)
SIGNAL
12 = Q1 (B)
Q2 (B)
13
Q3 (B)
14
15
MR (B)
16
[VCC]
SIGNAL
= [GND]
SIGNAL
12
Q1 (B)
13 = Q2 (B)
Q3 (B)
14
15
MR (B)
16 = [VCC]
SIGNAL
HT4538: NUMBER OF GATES PER PACKAGE
ill
ill
7
8
ill
P2
P3
Q3
ClK
= [VCC]
2
SIGNAL
HT4520: NUMBER OF GATES PER PACKAGE
SIGNAL
SIGNAL
A (A)
R' (A)
RXCX (A)
CX (A)
[VCC]
147
CMOS Family Components
148
HT7046: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
= LOCK-SIG
P-COMP1
COMP
VCO-OUT
INH
C1 -1
ill
SIGNAL
7
C1-2
[GND]
VCO-IN
10 = DMOD
11
R1
1
2
3
4
5
SIGNAL
= INA
(A)
INB (A)
OUTY (A)
OUTY (B)
INA (B)
12
13
14
15
16
8
9
HT7266: NUMBER OF GATES PER PACKAGE
ill
ill
ill
6
7
8
9
10
§.!.§ill
= INB (B)
= [GND]
= INA (C)
INB (C)
OUTY (C)
SIGNAL
= R2
P-COMP2
= SIG-IN
C2
= [VCC]
/
(
""
4
ill
SIGNAL
11 = OUTY (D)
INA (D)
12
INB (0)
13
[VCC]
14
HT40102: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
CP
MR'
TE'
PO
P1
P2
ill
SIGNAL
7 = P3
[GND]
8
9
PL'
10
P4
11
P5
/
ill
/
,
"
/
SIGNAL
12
13
14
15
16
P6
P7
TC'
PE'
[VCC]
ill
SIGNAL
HT40103: NUMBER OF GATES PER PACKAGE
ill
1
2
3
4
5
6
SIGNAL
CP
MR'
TE'
PO
P1
P2
ill
SIGNAL
7 = P3
[GND]
8
9
PL'
10
P4
11
P5
12
P6
13 = P7
14
15
16
TC'
PE'
[VCC]
(
~
000-0081-01
/
i
Schematic Symbols
HT40104: NUMBER OF GATES PER PACKAGE
Ell!
1
2
3
4
5
6
SIGNAL
OE
OSR
= DO
01
02
03
Ell!
7
8
9
10
11
SIGNAL
OSl
[GNO]
SO
S1
ClK
Ell!
12
13
14
15
16
SIGNAL
Q3
Q2
Q1
QO
[VCC]
HT40105: NUMBER OF GATES PER PACKAGE
Ell!
1
2
3
4
5
6
SIGNAL
Ell!
OE'
7
= OIR
8
9
10
11
S1
DO
01
02
,
,!
>7:.'
(
000-0081-01
SIGNAL
03
[GNO]
MR
Q3
Q2
Ell!
SIGNAL
12
Q1
13
= QO
OOR
so
14
15
16
[VCC]
149
CMOS Family Components
150
000-0081-01
~
C)
C)
C)
A1
C)
C)
H
6
CO
K
DT+4
I
02+4
CD400lB
I
10
11
12
C2
03+4
I
04+4
04+5
CD4002B
CD4001B
B
i'1:1
0
z:
51
52
53
54
BI
B2
B3
B4
02+5
~ ~ ~
84
-13
CD4000B
AI
A2
A3
A4
01+4
CD4002B
CD400IB
n
E1
01
~ ~ ~
CD400IB
0
.~,
r""~~
•
-oj
'1:1
r0
-oj
-L
III
CIN
CD400BB
m
COUT
CD400BB
G1
F1
INA
INB
INC
IND
INE
INF
~ ~ ~
aUlA
OUTB
DUTC
auTO
CD4011B
DUTE
DUTF
CD4010B
13
J{psc
K1
....!..j
01
RESET! 01
pt
2
:tl
5
•
H4
CD40138
I
CD4012B
N1
en
n
::r
I
3
C1)
M1
PINI
PIN2
PIN3
~FI
02
CD4013B
10
11
12
L1
I
CD40148
01
02
03
04
CD4015B
'"
rt
M2
OIA
02A
03A
04A
LK
RESET
DATA
~
I
CD4011B
CD40t1B
J1
J2
CD4012B
12
~ ~ ~
VCC
CD4D09UB
CD4011B
OIB
02B
03B
04B
01
02
03
04
CD40158
CD4015B
n
en
"<
3
'1:1
,...
...
0
00
(Jl
n
c
V1
A3
A2
Ai
A4
B1
C1
CNTRL-A
A-IO
A-OJ
LK
2
CO
0
~ ~
:i
C04023B
J3
C04023B
¥.1
Ql"r
~
PIN5
~piN8
C04020B
POUTS
POUT7
POUTa
C04021B
CD4025B
CD4023B
0
0
0
0
0
~
K1
f-¥l.
~ ~
:i
I
CD40248
C04025B
L3
'1:j
,..
I
0
rt
C04025B
n
CI
N
I
1\
('
\,
'\
~
/
~
0
0
0
0
0
00
"~
.A'ii?" ,
Ai
81
82
n
01
LK
CLK-INH
RESET
DEDUT
CLKD
9
ii
I-"--
6
I_
G2
~CR
K- Tol ;'"
SUM
p!L.j~
CD4030B
~~
~CR
;NV
SUMl
j~
-4
III
~~
CD4029B
G3
~
r0
CD4030B
91
92
93
94
CD4026B
G1
Z
:!)~
CD402BB
F1
0
Z
-4
CD4027B
LK
DEIN
~
m
CD4030B
CO
0
CD4027B
i
~~
SET
J
LK
K
RESET
;NV
CD4030B
SUMl
9BAR
--CD4031B
CD4032B
CD4032B
CD4032B
Hi
J1
~
Ii
SERIN
L2
L1
K1
.-!j.
L3
.-!jA
(I)
0
::7
CD
.-!jA
3
....
Q)
0
SUM2
P"-
IJ
CD
SUM3
p±-.
--l
RBD
no>
5
1
4
CD4033B
CD40328
UU
E
CD4035B
CD4034B
VCC
1
E
1
CD4037A
VCC
CD4037A
6
0
B
(I)
C
-<
1
E
9
~
...
0
VCC
CD4037A
n
CI
III
3
00
II)
U1
C.H
n
--%eLK
LK
3
SUMt
ll.jil
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C1
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SUM~
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2
CD403BB
5
B3
B2
B1
Ai
B
•
SUMr
~
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1
I C3
uo
I
SUM3
r-
RESET
LK
1
,.."1:1
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0
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III
G1
0
0
0
~
VJ
IJ1
..,..
F3
F4
CD4042B
CD4042B
CD4042B
LK
CD4042B
Ii
CD4041UB
Hi
H2
~ ~
0
0
~ ~
00
CD4043B
0
G
CD4043B
CD4D43B
1
~ ~
G
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....
0
rt
1
n
CD4043B
....0
CD4043B
~
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0
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CD404IUB
CD4037.
n
0
3
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LK
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3
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CD40AOB
F2
F1
CD404IUB
a
VI
III
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t
n
3:
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•
CD4D3BB
~
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SUM2
INV3
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CD4041UB
6
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INVl
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m
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CD403B8
CD4038B
01
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Ai
A2
A3
A4
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0
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PCOMP1 ~
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RX2
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SIGIN
COMP
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CD4044B
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N-TRIG
P-TRIG
RE-TRIG
EX-RSET
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C04049UB
C04049uB
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C04049UB
CD4049UB
C04049UB
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C040478
CD4048B
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CD4046B
J1
11
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C040508
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C040508
~
CD4050B
~
CD4050B
0
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3
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5
6
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A
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INH
A
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3
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VI
V2
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C040548
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VI
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A
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C04055B
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KB
KC
ClK
l
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2
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m
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A3
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24
1
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OUT
NEGG
01
02
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01
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Q5
Q6
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GI2
GI3
QI4
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BI
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G2
CD4066B
G3
0
0
0
CD4066B
0
0
G4
co
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(/)
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o
9
~
C040668
(\
~~ ~
CD4071B
~~ ~
CD4071B
CD4070B
OUTIIN
I
~ ~ ~ ~~ ~
CD4069UB
CD4069UB
CD4069UB
~
~~
11
12
13
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CD4067B
CD4069U8
0
3
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0
....
C04068B
9
10
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n
CD4060B
CD4070B
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16
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8
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3
2
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en
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2
3:
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n
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0
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