061 2880 00_4170_Local_Graphics_Processing_Unit_Instruction_Manual_Apr1984 00 4170 Local Graphics Processing Unit Instruction Manual Apr1984
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Part No. 061-2880-00
Product Group 16
N
4170
LOCAL GRAPHICS
PROCESSING UNIT
INSTRUCTION
TEK MANUAL
Part No. 061-2880-00
Product Group 16
4170
LOCAL GRAPHICS
PROCESSING UNIT
First Printing SEP 1983
Revised APR 1984
~tron~
COMMITTED TO EXCELLENCE
I WARNING
I
This equipment generates, uses, and can radiate radio
frequency energy and if not installed and used in accordance
with the instruction manual, may cause interference to radio
communications. It has been tested and found to comply with
the limits for Class A computing devices pursuant to Subpart J
of Part 15 of FCC Rules, which are designed to provide
reasonable protection against such interference when operated in a commercial environment. Operation of this equipment
in a residential area is likely to cause interference in which
case the users at their own expense will be required to take
whatever measures may be required to correct the
interference.
Copyright © 1983 by Tektronix, Inc., Beaverton, Oregon. Printed in
the United States of America. All rights reserved. Contents of this
publication may not be reproduced in any form without permission of
Tektronix, Inc.
This instrument, in whole or in part, may be protected by one or more
U.S. or foreign patents or patent applications. Information provided
on request by Tektronix, Inc., P.O. Box 500, Beaverton, Oregon
97077.
Tektronix is a registered trademark of Tektronix, Inc.
CP/M-86 is a registered trademark of Digital Research. ASM-86
and DDT-86 are trademarks of Digital Research.
Intel is a registered trademark of Intel Corporation.
MODEM86 is a copyrighted and licensed program of CompuView
Products.
Centronics is a registered trademark of Centronics, Inc.
MANUAL REVISION STATUS
PRODUCT: 4170 Local Graphics Processing Unit
This manual supports the following versions of this product: 8010100 and up.
REV DATE
DESCRIPTION
SEP 1983
Original Issue
OCT 1983
Revised: pages 1-1,4-39,4-40,5-5, 6-4, 8-2, 8-3, 8-5, 8-21, 8-22, 8-35, 8-37, 8-42, 8-43, 9-5, 9-6, 9-10,
9-47, 9-48, 9-49, 9-50, 9-51, 9-52. Added: pages 8-2A, 8-22A, 9-6A, 9-48A, 9-52A, 9-528, 9-52C, 9-520.
DEC 1983
Revised: pages 5-5, 6-1, 9-6, 9-6A, 9-10. Added: page 9-10A.
JAN 1984
Revised: pages 9-20 and 9-21.
Added: page 9-20A.
MAR 1984
APR 1984
4170 INSTRUCTION
Pages replaced, changed, or deleted to correct miscellaneous errors and to support Version 1.2 software. Contents list and Sections 1, 4, 5, 6, and 7 replaced. Section 9, Appendix S, and 4110 Series
Direct Terminal Interface Programmers Reference Manual (070-4534-01) deleted. Pages 2-4 and 3-7
changed.
Revised: pages iv, 4-1, 4-11, 4-13, 4-16, 4-17, 4-20, 4-22, 4-29, 4-33,4-36,4-39,4-41,5-4,5-5,5-24,5-28,
5-29, 5-30, 7-35, 7-37, 7-39, 7-40, 7-41, 7-42, 7-43, 7-47, 7-52, 7-53, 7-55, 7-75.
REV. APR 1984
CONTENTS
Section 1
INTRODUCTION
Page
Do You Need To Read This Manual? ......•.... 1-1
Suggested Reading Paths .............•.... 1-1
First Time Use . . . . . . . . . . . . . . . . . . . . . . . . 1-1
After Installing the 4170 ............. 1-1
If You Are An Experienced Programmer .. 1-2
Servicing the 4170 .................... 1-2
About This Manual ........................ 1-3
Do You Need To Read Other Manuals? ......... 1-5
Abo u t Th e 4 1 70 .••••••••••••••••••••••••••••• 1 -7
Product Description ...................... 1-7
4170 System Configurations ............... 1-8
The 4170 and its Te rminal ............. 1-8
The 4170 and a Host System ............ 1-8
4170 Software ............................ 1-9
The CP/M-86 Operating System .......... 1-9
Additional Operating System
Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
MODEM86 ••••••••••••••••••••••••••••••• 1-10
FORTRAN-86 ....•....................... 1-10
IGL ...........••..••....•...•..•...... 1-10
GSX-86 •••••••••••••••••••••••••••••.•• 1-11
DTI ...........•..•.•..••.•.•...•..•••• 1-11
Accessories . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . 1-12
Section 2 SPECIFICATIONS
Performance Conditions ....................... 2-2
Physical Characteristics ..................... 2-2
Environmental Conditions ..................... 2-4
Electrical Characteristics ................... 2-7
Installation Requirements .................... 2-8
Functional Characteristics ................... 2-9
Section 3 CONTROLS, INDICATORS, AND CONNECTORS
Front Features ............................... 3-1
Control Panel (exposed items) ............. 3-3
Control Panel Door ........................ 3-4
Cue Card .•...••.•....••..•.•.•.••.•.•...•. 3-6
Disk Drive Features ....................... 3-8
Rear Panel Features .......................... 3-8
4170 INSTRUCTION
Rev, IVlar 1 984
ii
Seotion 4 INSTALLATION PROCEDURES
Select ion a Sit e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Installation Guidelines ...................... 4-2
What to Install ............................ 4-3
Before You Begin ........................... 4-4
If You Add an Option Later ................... 4-4
1 • Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
2.Voltage Selection/Checkout ............... 4-7
3.Removing the Front Cover ................. 4-9
4.Removing the Side Cover .................. 4-11
Locat ion of Maj or Components ................. 4-12
5. Installing Memory Options ................ 4-13
6.Installing the Hard Disk Unit ............ 4-19
7.Installing the Disk Interface ............ 4-21
8.Installing the Optional Peripheral
Int erface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2("7
9.Installing the Color Copier Interface .... 4-31
10. Replacing the Si de Cover ................ 4- 33
11 . Replacing the Front Cover .....•......... 4- 37
12.Connecting a Terminal ................... 4-39
13·Verifying Operation ..................... 4-41
Repackaging Instructions ..................... 4-42
Seotion 5 GETTING STARTED
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
How To Use This Section .................. 5-1
Procedures For First-Time Operation ......... 5-2
Setting Up Communications With Your
Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
The 4170 CMOS-Reset Procedure ......... 5-6
Loading CP/M-86 from the Diskette ........ 5-11
Setting a Faster Baud Rate ............ 5-12
Making a Backup of the Operating
System Diskette ................•......... 5-12
Formatting a New Diskette ......•......... 5-13
Copying the Operating System Diskette .... 5-14
Using the Hard Disk ...................... 5-18
Formatting the Hard Disk ....•......... 5-18
Setting Up the Hard Disk as the
Default/Boot Drive .................... 5-22
Connecting the 4170 to a Host ............ 5-24
Connecting to a Host Computer ......... 5-24
Getting Started with the
MODEM86 Program .............•......... 5-27
Transferring Files Between the Host
and 4 1 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 31
iii
Rev, Mar 1984
4170 INSTRUCTION
Connecting a Printer ..................... 5-38
Connecting a Printer ..............•... 5-38
Configuring the 4170 .................. 5-40
Using a Printer ....................... 5-40
Section 6 OPERATING INFORMATION
Before You Start ............................. 6-1
Mass Memory and Local Memory Naming
Con ven ti ons ............................... 6-1
Know Your Terminal ........................ 6-2
Familiariza tion Exercises .................... 6-2
Differences from Standard CP/M-86 ......... 6-4
Error Messages ......................... 6-4
Section 7 PROGRAMMING INFORMATION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
General Information ..............•.....•..... 7-2
Mass Storage Device Names ................. 7-2
Logical-to-Physical Device Mapping ........ 7-3
The IOBYTE ............................. 7-4
Using STAT to Change
Device Assignments ..................... 7-5
Tektronix Supplied Utili ties ................. 7-6
Syntax Conventions ........................ 7-6
AR ••••••..•••.•••••••••••••••••.•••••••••• 7-7
CONFIG •.•................••.•........•...• 7-10
DEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
FORMAT . . . • • • . • . • • • • . . • • . • . . • • . . . . . . . . • . . . . 7-19
Formatting Flexible Diskettes .......... 7-19
Formatting a Hard Disk ................. 7-20
RUN .•.••...•...................•..•.•.••.. 7-22
SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
SETDEV .••..••....••••......••..•....•....• 7-26
Host Communications and the MODEM86
Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Which Program to Use ...................... 7-34
Entering MODEM86 Commands ................. 7-36
Overview of the MODEM86 Main
Menu Options .................•......... 7-39
Overview of Command Suboptions ......... 7-41
Transferring Files Using Terminal Mode .... 7-43
T Menu Option -- Terminal Mode in
Full-Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43
Transferring Files from a Host
Computer ............................... 7-44
Transferring Files to a Host
Computer ............................... 7-46
H Menu Option -- Terminal Mode in
Half-Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
E Menu Option -- Terminal Mode with
Ec ho i ng. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4 7
W Menu Option -- Write and Close
Conversation File ...................... 7-47
4170 INSTRUCTION
Rev, Apr 1984
iv
P Menu Option -- Purge Conversation
File ..................................... 7-48
Examples ............................... 7-48
Error-Free File Transfer .................. 7-49
S Menu Option -- Send File Mode
R Menu Option -- Receive File Mode ..... 7-49
Examples .........•..................... 7-50
Changing Preconfigured MODEM86 Programs ... 7-52
Ut iIi ties ..................................... 7-56
Printing Host Files .................... 7-56
Squeezed Files ......................... 7-56
Tab Character Processing ............... 7-57
Conversion of Binary Files ............. 7-58
If You Have a Problem with MODEM86 ........ 7-59
MODEMSET Gives Strange Default
Answers ••••••••••.••••••••••••••••••••• 7-59
SIO Parameter Error Message ............ 7-59
Incompatible Versions Error Message .... 7-60
Data is Lost from Each Line ............ 7-60
Checksummed File Copying Aborts ........ 7-60
File Data and Host Messages not
Displayed ........................
III
0
co
•••••
7-61
MODEM86 Runs but Nothing is Received
from the Host .......................... 7-61
Protocols Used ............................ 7-63
Single File Transfer ........ 0 ....
7-63
Multifile Transfer ..................... 7-64
CRC-16 Checksum ........................... 7-64
FORTRAN-86 ..................................... 7-65
The FORTRAN-86 Files ...................... 7-65
Compiling a FORTRAN-86 Program ............ 7-66
Linking and Executing a FORTRAN-86
Program ............................ " ....... 7-67
Compiling and Linking with
Flexible Disks ......................... 7-68
FORTRAN-86 Features Unique to
4170 CP /M-86 .............................. 7-69
Fortran Overlays .................
7-70
Additional Details about FORTRAN-86 ....... 7-73
IGL ......................... " . . . . . . . . . . . . . . . . . . . . . 7-74
Introduction .............................. 7-74
Requirements for Running IGL ........... 7-74
Diskette Contents ...................... 7-75
Terminals Supported .................... 7-75
Integer Size ....... 0 .................. 07-75
Logical Unit Numbers ................... 7-76
F i leN am e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7 6
File Types .......
7-76
Error Message File ....
7-76
0
0
0
v
Rev, fv'lar 1 984
••••••••
•••••••••••••••
o
•••••
0
•••••
••••••••••••
0
•••
4170 INSTRUCTION
Using IGL with a Hard Disk ................ 7-77
Setup for Hard Disk Operation .......... 7-77
Compiling an IGL FORTRAN Application
Source File ............................ 7-77
Linking Your IGL FORTRAN Object File ... 7-78
Running Your IGL FORTRAN Program ....... 7-79
IGL wi th Flexible Diskettes ............... 7-80
Setup for Flexible Diskette
Operation .............................. 7-80
Compiling an IGL FORTRAN Application
Source File ............................ 7-81
Linking Your IGL FORTRAN Object File ... 7-81
Running Your IGL FORTRAN Program ....... 7-83
GSX-86 ....................................... 7-84
Introduction .............................. 7-84
Diskette Contents ...................... 7-84
GSX-86 FORTRAN Interface .................. 7-85
An Example: Compiling, Linking, and
Running the Demonstration Program ......... 7-86
Tektronix Extensions to GSX-86 ............ 7-87
Device Specific Information For Tektronix
Device Drivers ............................ 7-95
DTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-101
Using the DTI on the 4170 ................. 7-101
Terminal Modes ............................ 7-102
Graphic Input .......................... 7-103
Terminal and Routine Compatibility ........ 7-106
Section 8 SELF TEST
Introduction ................................. 8-1
What the User Needs to Know .................. 8-1
Power-up Self Test ........................ 8-1
Extended Self Test ........................ 8-2
Error Code Meanings ....................... 8-2
What The Service Technician Needs to Know .... 8-6
Power-up Self Test ........................ 8-7
Extended Self Test ........................ 8-7
Starting Extended Self Test ............ 8-7
Initial Tests .......................... 8-7
Keyboard Test .......................... 8-7
Remainder of Extended Self Test ........ 8-8
Keyboard and LED Check (Fe, Fd) ........... 8-9
Processor Check (Ex) ...................... 8-10
Communications and Bus Checks (Dx) ........ 8-12
RAM Che ck (Bx) ............................ 8-1 6
3PPI Che ck (6x) ........................... 8-20
Option 45 Disk Controller
Board Check (5x) .......................... 8-22
Option 44 Disk Controller
4170 INSTRUCTION
Rev, Nar 1984
vi
Board Check (8x) ........•..•.......... .... 8-2j
Hard and Soft Errors ................... 8-23
Disk Media Problems .................... 8-24
Adjustment Self Test ..•........•............. 8-35
The General Menu ..........•.....•...... 8-j6
Processor Board Menu ....•......•....... 8-37
3PPI Menu •....•...•..•.•..•..•....•...• 8-'39
Option 44 Flexible Disk Menu .•..•..•... 8-41
Option 45 Disk Menu .•.....••.•.....•.•• 8-45
Section 9
(deleted)
Seotion 10
GLOSSARY
I WARNING'
The following servicing instructions are for
qualified personnel only. To avoid personal
injury, do not perform any servicing other than
that described in the operating instructions
unless you are qualified to do so.
Section 11
SERVICE SAFETY SUMMARY
Seotion 12
THEORY OF OPERATION
Overview •••..••••••••••••••••.••••••••••••• 12-1
Card-cage/Motherboard ...................... 12-3
Processor Bus ....•....•.............•.......• 12-8
Microprocessor and Numeric Co-processor ..• 12-10
Interrupt Controller ........•........•.... 12-10
Processor and System Bus Interface ........ 12-10
S y stem
l'-'i f.- :, ~ ~, r: V • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
1 2 -1 1
Control, Status, and Timing ............... 12-11
Host Computer Port ..........•............. 12-12
Pront Panel Port ..•.......•.....•......... 12-12
Detailed Processor Board Circuit
Descriptions ..•..•..•..........•..•......• 12-1 2
MPU (Schematic A2-1) and FPU
(Schematic A2-2) .......................... 12-1?
The Bus Cyele .......................... 1 2-20
lVlPU Internal States .................... 12-20
Memory and I/O Address Space Access .... 12-20
Reset and Initialization ...•........... 12-21
Interrupt Operations •.................. 12-21
Interrupt Controller (Schematic A2-2) ..... 12-21
Programmable Interrupt Controller ...... 12-2)
The Interrupt Sequence ................. 12-26
13TI~TA-O and Cascade Addresses for
~)lave
PIC~)
...•••••.••.••••.•••....••.•• 1 2-2'"1
Address Drivers (Schematic A2-2) .......... 12-27
vii
Rev, lVlar 1 984
4170 INSTRUCTIUN
Data Drivers/Receivers (Schematic A2-2) ... 12-27
Bus Command Driver (Schematic A2-2) ...•..• 12-30
Control Logic .••....•...........•...... 12-34
Control Signal Generator ...........•... 12-34
MPU Status Decoder •.•....••........•... 12-37
Command Generator ........••••...•..•... 12-37
Read Only Memory (ROMS) (Schematic A2-3) .. 12-38
ROM Configuration ...................... 12-38
Fi rmware ••••••••••••••••••••••••••••••• 12-38
S"traps ............•..•.••....••........ 12-38
Non-Volatile RAM (Schematic A2-4) ......... 12-42
Read Access •••••••••••••••••••••••••••• 12-43
write Access .....••.•.................. 12-43
Microprocessor Control (Schematic A2-1) ... 12-43
Clock and Reset ........................ 12-47
Ready Signals •....•...•.......••.....•. 12-47
Bus Transfer Logic (Schematic A2-1) .•..... 12-48
End-of-Data-Transfer Strap ....•........ 12-49
Address Decod ing ( Schematic A2-3) ......... 1 2-51
Bus Timeout Detector (Schematic A2-1) ..... 12-54
Sta tUB Input (Schemat ic A2-5) ............. 12-56
Bus Clock Generator (Schematic A2-1) ...•.. 12-J7
MPU Timing Generator (Schematic A2-1) •.... 12-59
Programmable 'rimer and Baud Hate Generator
(Schemat ic A2-5) ..••...................... 12-61
Programmable Interval Timer ............... 12-64
RS-232 State Change Detector
(Schematic-A2) ....................•....... 12-65
RS-232 Communications Interface
(Schematic A2-5) .............•.•.....•.•.. 12-66
Programmable Communications Interface •. 12-68
MPU Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-72
Data Communication ................•.... 12-73
In t e r ru p t s ..••••••••.••••.•••••••••••.• 1 2 - rl 3
Front Panel Controller (Schematic A2-4) ... 12-73
Front Panel Controller Microcomputer ..• 12-75
Keycode Data ........•.•......•.••.•..•. 12-79
LED and Bell .....•.......•.•.....••..•. 12-79
BCC RAM Memory ......•••..•....•..•.•....•.•.. 12-79
Three Port Peripheral Interface
(And Option 10 3PPI) ...•..................•.. 12-80
Opt ion 44 Dis k Con t roll e r Bo a rd ..•.•......... 12 -81
System Configuration .........•...........• 12-81
Background Information ......••.•••....•... 12-83
ryie d ia . . . . . • . . . . • . . • . • . . . . . . . . . • . . • . . . • . 12-83
Media Formatting ....................... 12-83
Sector Data Structure .....•...•..•.•... 12-85
l"1l"I"l Disk Encoding ~1ethod .............•. 12-91
Write Precompensation .........•......•. 12-93
4170 INSTRUCTION
Rev, ['tar 1 984
viii
Operation Overview ..•.•••...•....•....•... 12-93
Status/Command Phase ..................• 12-97
Execution Phase ....••...•............•. 12-102
Resul t Phase ••....•.•......
12-107
Circuit Descriptions ..........•.....••.•.. 12-107
Disk Drive Control ..........••......... 12-109
0,
...........
II
Clocks ................ ., ••..•.•••.••.••.•. 12-113
Write Control ................•.....•.•. 12-11 6
Disk Drive Control .................•... 12-126
Terminal Bus Interface •....•........... 12-129
Option 45 MSIB Controller ......•..........•.. 12-146
Hard Disk Controller .......•.•.....•....•.... 12-147
Option 9 Color Copier Interface .............. 12-153
'E'ront Panel •......•••.•.•.••••.••.•.....
12-1 53
Keys Ci rcui try ................•........... 12-1 55
Dis play Cire u i try. . . . • • . . . • • . . . . • . . . . . • . . . 1 2 -1 55
Reset Ci rcui try ................•.......... 12-1 55
Tone Generator .................•.......... 12-155
Power Supply Module ...............•........•. 12-156
OverviE~w .................................... 12-1 56
Detailed Descriptions of Circuit Blocks ... 12-157
Line Input and Filter .......•.•........ 12-159
II
••••
Line Select •..•..•••.•••••.•••••.••...• 12-15-Compatible MFM (A) Format
Description ................................ 12-88
I/O Port Memory Map ........................ 12-97
FDC Status Byte ............................ 12-101
3-To-1 Decoder ............................. 12-111
Board Status Byte .......................... 12-135
Pin Assignments ............................ 1 2-1 56
Function Key Definitions ................... 13-1
Test Points ................................ 1 3-6
-21 Minutes ................................ 13-3
+21 Minutes ................................ 13-3
Processor Board Straps ..................... A-3
I/O Address/Bank Number Strap Positions .... A-9
Bank/No Bank Strap Positions ............... A-10
4170 INSTRUCTION
Rev, Mar 1984
xiv
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
A-14
A-16
xv
4170 Mode Strap Position ................... A-10
Port A and B Address Range Strap Positions.A-11
Port A Address Space Strap Positions ....... A-12
Board Size Strap Positions . .......... ...... A-13
8207 Configuration Strap Positions ......... A-13
Clock Source Strap Position ................ A-14
I/O Address Strap Positions ................ A-16
Interrupt Level Select Strap Settings ...... A-20
I/O Base Address . ......................... . A-20
Head Load Control .................... ... ... A-13
Write-Protect Strap Settings ............... A-21
Option 45 Disk Controller Straps ........... A-24
Rev, Mar 1984
4170 INSTRUCTION
OPERATORS SAFETY SUMMARY
This general safety information is for both operating and servicing personnel. Specific warnings and cautions will be found
throughout the manual where they apply, but may not appear in this summary.
TERMS
IN THIS MANUAL
CAUTION statements identify conditions or practices that
can result in damage to the equipment or other property.
POWER SOURCE
This product is designed to operate from a power source
that does not apply more than 250 volts rms between the
supply conductors or between either supply conductor and
ground. A protective ground connection by way of the
grounding conductor in the power cord is essential for safe
operation.
WARNING statements identify conditions or practices that
can result in personal injury or loss of life.
GROUNDING THE PRODUCT
AS MARKED ON EQUIPMENT
CAUTION indicates a personal injury hazard not immediately accessible as one reads the marking, or a hazard to
property including the equipment itself.
This product is grounded through the grounding conductor
of the power cord. To avoid electrical shock, plug the power
cord into a properly wired receptacle before connecting to
the power input or output terminals. A protective ground
connection by way of the grounding conductor in the power
cord is essential for safe operation.
DANGER indicates a personal injury hazard immediately
accessible as one reads the marking.
DANGER ARISING FROM
LOSS OF GROUND
SYMBOLS
Upon loss of the protective-ground connection, all accessible conductive parts (including knobs and controls that may
appear to be insulating) can render an electric shock.
IN THIS MANUAL
Ij\ This symbol indicates where applicable cautionary or
~ other information is to be found.
USE THE PROPER POWER CORD
Use only the power cord and connector specified for your
product.
As Marked on Equipment
Use only a power cord that is in good condition.
~
DANGER high voltage.
@
Protective ground (earth) terminal.
&
ATTENTION - refer to manual.
CD
Refer to manual.
4170 INSTRUCTION
Refer cord and connector changes to qualified service personnel.
REV, MAR 1984
xvi
OPERATORS SAFETY SUMMARY
USE THE PROPER FUSE
DO NOT REMOVE COVERS OR PANELS
To avoid fire hazard, use only the fuse specified in the parts
To avoid personal injury, do not remove the product covers
or panels. Do not operate the product without the covers
and panels properly installed.
list for your product, and which is identical in type, voltage
rating, and current rating.
Refer fuse replacement to qualified service personnel.
DO NOT OPERATE IN
EXPLOSIVE ATMOSPHERES
To avoid explosion, do not operate this product in an atmosphere of explosive gases unless it has been specifically
certified for such operation.
4170 INSTRUCTION
figure 1-1. 4170 Local Graphics Processing
Unit~
4170 I NSTRUCTION
xviii
Seotion 1
INTRODUCTION
DO YOU NEED TO READ THIS MANUAL?
Yes, you need to read this manual to install the 4170 and to
learn how to use it. But you probably don't need to read all of
this manual -- perhaps only certain parts of it. The Suggested
Reading Paths that follow will help to introduce you to the
4170 QuicKlY: with as few problems as possible.
SUGGESTED READING PATHS
First Time Use
First, to install the 4170, use the instructions in Section 4 of
this manual. Section 4 also contains procedures for connecting a
terminal to the 4170. After completing the procedures in Section
4, then go to Section 5~ and follow the instructions there for
making a backup copy of the CP/M-86 Operating System diskette.
(It is a good idea to make a backup of the Operating System
diskette before you begin using the system; this way, if the
diskette is accidentally damaged, you'll still have a copy of
it.) In Section 5, you'll also learn how to get started using the
optional hard disk, host communications, and peripherals.
After Installing the 4170
After you have made a backup of the Operating System diskette,
you are ready to begin using your 4170. If you are new to the
CP/M-86 Operating System, read Section 6 and Digital Research's
CP/M-86 Operating System User's Guide to learn how to use
some otFier CPjM-86 Operating" System commands. (Knowing the
CP/M-86 commands will make it easier for you to run specific
applications programs later.) At this point, you are ready to
begin using a specific applications program, such as Wordstar or
SuperCalc. Follow the instructions that came with the application
program for getting started.
If you are an experienced CP/M-86 user, to refresh your memory
about CP/M-86 commands, refer to the CP/M-86 Operating System
User's Guide or the CP/M-86 Operating System Command
"SUillrriarY:- Then proceed with using a specific applications
program.
4170 INSTRUCTION
Rev, Mar 1984
1-1
SECTION 1
INTRODUCTION
If You Are An Experienced Programmer
After installing the 4170 and making backup copies of the
diskettes, experienced programmers may skip to Section 7, which
contains complete descriptions of the Tektronix-supplied
utilities that supplemen~ the CP/M-86 commands.
Section 7 also
gives further information on the host communications utility,
MODEM86. Finally, Section 7 describes the applications software
-- FORTRAN, IGL, GSX, and DTI -- supplied with the 4170.
Depending on your specific application, after reading Section 7
you may want to refer to other documentation supplied with the
4170 (see the list of manuals supplied with the 4170, later in
this section).
Servicing the 4170
If the 4170 requires service, contact your local Tektronix field
office. (This manual includes service and maintenance information
that the Tektronix service technician may use; see Ab~yt ~~~~
Manual,
which follows.)
-----
1 -2
Rev, IVJar 1 984
4170 INSTRUC'I'ION
SECTION 1
INTRODUCTION
ABOUT THIS MANUAL
This instruction manual contains:
o
Section 1, Introduction (this section). Introduces the
4170, its features and options, and the manuals and
diskettes supplied with it.
o
Section 2,
the 4170.
o
Section 3, Controls, Indicators, and Connectors.
Shows the locations of -the"-controls;--lIght -Indicators, and
connectors on the 4170's front and rear panels.
o
Section 4, Installation. Gives the procedures for
installing tneLff7~ana connecting a terminal to it.
o
Section 5, Getting Started. Contains instructions for
the first-time users, and-examples of using host
communications and peripherals.
o
Section 6, Operating Information. Contains exercises
to help you---o8"come-famITlar wll11 some of the CP /M-86 commands.
o
Section 7, Programming Information. Contains reference
information on the applications software.
o
Section 8, Self-Test. Describes how to run the
adjustment self-test.
o
(Section 9 has been deleted. The information that it
previously contained now appears in other sections.)
o
Section 10, Qlossary. A list of terms used in this
manual.
o
Section 11, Service Safety Summary. Safety
considerations-ror-those performing service on this
instrument.
4170 INSTRUCTION
Specifica~ion~.
Provides specifications for
Rev, Mar 1984
1-3
SECTION 1
INTRODUCTION
o
Section 12, Theory of 0Eeration. Describes how the
4170's circuitry works.
o
Section 13, Checks and Adjustments. Contains service procedures
for qualified service technicians.
o
Section 14, Maintenance. Contains disassembly and
reassembly procedures and preventive maintenance procedures.
o
Section 15, Replaceable Electrical Parts; Section 16,
Diagrams; Section 11, Replaceable Mechanical Parts.
Parts·lists and schematics for the 4170.
o
Appendix A, Strap Information. Information on strap
settings.
1-4
Rev, Mar 1984
4170 INSTRUCTION
SECTION 1
INTRODUCTION
DO YOU NEED TO READ OTHER MANUALS?
The 4170 comes with 11 manuals. Some are Digital Research manuals
and document the CP/M-86 Operating System; others are Intel
manuals and cover Intel utilities. Finally, Tektronix supplies
this manual, the 4170~nstruction Manual, as well as manuals
on IGL.
What other manuals do you need to read? That depends on what you
intend to do. If you'll be writing programs in FORTRAN, you'll
probably want to refer to the Intel FORTRAN-86 manuals;
otherwise, you may not need them.
Here's a list of the manuals that come with the 4170, with a
brief description of what each manual contains and an indication
of the manual's intended audience:
o
Tektronix 4170 Instruction Manual (this manual). Contains
instructions and operating information for
users; describes the Tektronix commands that supplement
CP/M-86; provides introductory information on applications
software provided.
TnS~arration
o
Tektronix 4010C01 PLOT 10 Interactive Graphics Library
users Manual and Reference Guide.
The users manual
documents the IGL library of graphics subroutines. (A subset
of IGL subroutines is included with the 4170; expanded IGL
capabilities are available as options.) The reference guide
is a quick-reference summary for experienced IGL
programmers.
o
4110 Series Direct Terminal Interface Programmers
Reference Manual. Documents the DTI routines for Local
Programmability.
o
CP/M-86 Operating System User's Guide (1). A manual for
be&inning users of CP/M-86. Describes in detail the
CPjM-86 Operating System, the CP/M-86 commands, and the
CP/M-86 line editor commands.
o
CP/M-86 Operating System Command Summary (1). A
quick-reference card that summarizes the purpose and syntax
of CP/M-86 commands. Intended as a refresher for those
familiar with CP/M-86.
(1) Published by Digital Research, Inc.
4170 INSTRUCTION
Rev, Mar 1984
1-5
SEc'rION 1
INTRODUCTION
a
CP/M-86 Operating System, System Guide (1). A system
progr'3.mmers'-iiianualth1ir- clarifIes-the differences between
CP/M-86 and CP/M-80.
a
CP/M-86 Operating System Programmer's Guide (1).
EXpTains ASN=80-operafion-ror-asseiiioTy-ranguage programmers.
a
FORTRAN-86 Users Guide and Pocket Reference (2).
FrOvides-InI'Oriiiationon thela-nguage;-t11e-compiler, and the
execution of FORTRAN-86 programs. The Pocket Reference
summarizes the information for experienced FORTRAN=S6programmers.
o
iAPX86,88 Family Utilities Users Guide and Pocket
Reference--r2J:--Describes-the iA"PX FamIly utiLlties used by
~~and FORTRAN-86 programmers.
o
GSX-86 Graphics Extension User's Guide (1). Describes
howtOset-up-your system"-torun-GSX=S6 programs (this is
the Graphics System Extension for the CP/M-86 operating
system); includes information on devices supported by GSX.
o
GSX Graphics ExtenSion Programmer's Guide (1). Provides
the information necessarY-far-programmers to adapt GSX for
other devices.
If you purchase CP/M-86-compatible software, you'll probably get
additional manuals. For example, if you purchase Wordstar (a
text-editing applications program) from Tektronix, you'll receive
instructions on how to get the software running and also
instructions on how to use the text-editing commands.
(1) Published by Digital Research, Inc.
(2) Published by Intel, Inc.
1 -6
Rev, Mar 1984
4170 INSTRUCTION
SECTION 1
INTRODUCTION
ABOUT THE 4170
With a TEKTRONIX 4170 Local Graphics Processing Unit, you can run
most applications software packages that are compatible with
CP/M-86.
The 4170 is often used with a Tektronix 4105, 4107,
4109, or 4014 terminal because it gives you the processing power
you need for writing, editing, compiling, linking, and debugging
graphics programs for those terminals. The 4170 provides this
graphics processing power locally; that is, when you connect
your terminal to the 4170, the 4170 acts as the host computer. If
you desire, you can also connect the 4170 to a host mainframe,
and run applications programs either from the host or from the
4170.
PRODUCT DESCRIPTION
The 4170 contains:
o
A processing unit and local memory.
o
Two flexible-disk drive units, which provide additional
storage for data and programs.
o
Interfaces for connecting the 4170 to a terminal, a
host, and peripherals.
The operating system for the 4170 is the CP/M-86 Operating
Syst~which is-roaded from a diskette in one of the two
flexible disk drives or from the optional hard disk.
The
operating system gives you a set of commands that allow you
rocontror-the-transfer of information between various parts of
the 4170 system; the operating system enables you to copy files,
for example, from a flexible disk drive to a printer.
An important feature of the 4170 is its simple design -- you, the
user, can install the 4170 and its options, and you can service
most of the instrument. Therefore, this manual contains the
information you'll need for installation and service, as well as
operating and programming information.
4170 INSTRUCTION
Rev, Mar 1984
1-7
SECTION 1
INTRODUCTION
4170 SYSTEM CONFIGURATIONS
A terminal connects to one of the three peripheral ports on the
back of the 4170.
The two remaining ports connect to peripherals
such as a plotter, a printer, or a gr~phics tablet.
You can use
the Option 09 parallel interface to connect a printer that
requires a Centronix-style parallel interface.
The 4170 and its Terminal
The 4170 must be connected to an RS-232 terminal.
you to control the 4170 system.
This allows
The terminal's keyboard is the main input device for sending
information to the 4170; the terminal's display scre~n is the
main output device for receiving data from the 41'70.
Read your
terminal operator's manual for a complete description of its
controls and indicators.
When you connect a terminal to the 4170, you have a local
processing system.
The 4170, with operating system and
applications software, performs the functions of a host computer.
The 4170 and a Host System
When connected to a host system, the 4170 acts as an interface
between the host and the terminal. An applications program may
run on the host while the 4170 performs the local processing
tasks as directed by the host software. The processing is then
"shared" by the host and the 4170.
Section 7 provides programming information that you may need to
interface your host to the 4170.
1 -8
Rev, Mar 1984
4170 INSTRUCTION
SECTION 1
INTRODUCTION
4170 SOFTWARE
Your 4170 comes with 10 diskettes. The soft/ware on the 10
diskettes is organized to reduce the number of times that you
must change diskettes.
The 10 diskettes supplied with your 4170 are:
o
4100P01 CP/M-86 Operating System
o
4100P01 MODEM-86
o
4100P01 FORTRAN (2 diskettes)
o
4100P73 PLOT 10 Interactive Graphics Library Fundamental
Support for 4170 (2 diskettes)
o
4100P01 GSX Graphics System Extension (2 diskettes)
o
4100P01 DTI and BIOS Source
o
IDD Program Exchange (unsupported software)
The following paragraphs introduce you to the operating system
and the software. (For detailed descriptions about using the
software provided, see Section 7, Programming Information.)
The CP/M-86 Operating System
The operating system for the 4170 is CP/M-86. CP/M-86 is a
single-user, single-tasking operating system that is most useful
in interactive applications such as program development and
debugging, small business computing, and word processing. The
CP/M-86 operating system manages the system memory, the disk
drives, and peripheral devices (such as terminals, printers,
tablets, and plotters) connected to the 3PPI and Option 09 ports.
Refer to the CP/M-86 Operating System System Guide, a Digital
Research publication, for a more detailed description of the
operating system.
Experienced system programmers may want to modify the BIOS
portion (the Basic Input/Output System) of the 4170 operating
system. To do this, refer to the documentation file "readme.doc"
on the FDTI and BIOS operating system diskette for more
information.
4170 INSTRUCTION
Rev, Mar 1984
1-9
SECTION 1
INTRODUCTION
Additional Operating System Utilities
Tektronix has written and included seven operating system
utilities: AR, CONFIG, DEL, FORMAT, RUN, SD, and SETDEV.
The AR
utility makes archive copies of files.
The CONFIG utility
defines the logical-to-physical device assignment and sets RS-232
communication parameters for the 4170 peripheral ports.
DEL
erases a file.
FORMAT defines the physical and logical
organization of data located on the disk. The RUN utility loads
and executes load-time-Iocatable programs. The SD utility sorts a
directory alphabetically. The SETDEV utility is similar to CONFIG
but easier to use; SETDEV allows you to check and selectively change
logical-to-physical device assignments, device communications
parameters, and the default and boot drive specifications.
MODEM86
MODEM86 provides communications between the 4170 and the host
computer.
A description of how to start host communications with
MODEM86 is given in Section 5; however, for a more complete
explanation, refer to Section 7, Program~~~~_~~f<2.~ma!.i0!2'
FORTRAN-86
FORTRAN-86 is an extended version of the FORTRAN 77 subset as
defined by the American National Standards Institute (ANSI).
It
is supplied to you on two diskettes.
Refer to Section 7 and the
Intel FORTRAN-86 User's Guide for details about using
FORTRAN-86.
------------------
IGL
The Interactive Graphics Library (IGL) provides a library of
FORTRAN-callable, device-independent subroutines that provide
high-level graphics functions.
IGL should be used wh~n working
with applications programs that require device and host
independence. IGL follows the SIGGRAPH CORE proposed standard.
Usually these programs will be uploaded and/or downloaded from a
host mainframe.
The supplied routines include the IGL primary
command set and the device drivers for the 4105, 4014, and the
4662 Option 31.
Refer to Section 7, Programming Information,
for more details about IGL.
------------- -.-------
1 -1 0
Rev, Mar 1984
4170 INSTRUCTION
SECTION 1
INTRODUCTION
GSX-86
GSX-86 is a device-independent graphics system for use with
CP/M-86. GSX-86 should be used when the applications program
will be transported to a non-Tektronix graphics device.
The
GSX-86 Graphics Extension Programmer's Guide and the GSX-86
GrapfifCsEXtens ion User's GUide, wri ttEm by Digital Research,
are also" supplied with the 4170. Additional information,
including information about Tektronix extensions, is in
Section 7.
DTI
DTI is a library of FORTRAN-callable subroutines (written by
Tektronix) for the 4100 Series terminals. DTI controls or
emulates a 4100 Series terminal's graphics features to simplify
programming support for the terminal. Section 7 contains
information on using DTI with the 4170; it also highlights the
differences between using the 4170 DTI and the DTI supplied with
4100 Series Local Programmability. (Included at the end of this
manual is the 4100 Series DTI Programmers Reference Manual,
which describes the use of the DTI supplied with 4100 Series
Local Programmability.)
4170 INSTRUCTION
Rev, Mar 1984
1 -1 1
SECTION 1
INTRODUCTION
ACCESSORIES
The following accessories are standard equipment for the 4170:
o
Manuals -- see the list of manuals earlier in this section.
o
Cables and connectors:
4170 power cord
4170-to-terminal power cord
RS-232 host port cable
Self Test loop-back connector
o
Box of 10 software diskettes
o
Box of 10 blank diskettes
Optional accessories include:
o
o
o
Alignment diskette
Extender board
Head cleaning kit (for flexible disk drive units)
In addition, you can order these manuals as optional
accessories:
o
o
o
o
o
ECe (Error Correcting Code) RAM Service Manual
4110 Series Mass Storage Service Manual
3PPI Instruction Manual
5-1/4 Inch Disk-Drive Service Manual (by Shugart
Associates, Inc.)
Hard Disk Drive Service Manual (by Seagate, Inc.)
To order any of these items see Replaceable Mechanical
Section 13, for part numbers.
1-12
Rev, Mar 1984
Par!~,
4170 INSTRUCTION
Seotion 2
SPiCIPICATIORS
This section lists two different types of specifications: those
that cannot be verified by the user (environmental, physical, or
static) and those that can be verified as actual operational
parameters. The user-verifiable specifications can be verified
through the adjustment procedure located in Section 13.
(User-verifiable specifications are listed only in Table 2-11 and
parts of Tables 2-5 to 2-7.)
The following tables contain specifications or characteristics
for the 4170.
Table
2- I•
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
Desoription
Physical Characteristics
Environmental Characteristics
Electrical Characteristics
Installation Requirements
General Functional Characteristics
Host Interface Specification
Peripheral Interface Specification
Software Specifications
Diskette Media Characteristics
Diskette Drive Unit Characteristics
User-Verifiable Drive Unit Specifications
4170 INSTRUCTION
2-1
SECTION 2
SPECIFICATIONS
PERFORMANC~
CONDITIONS
To ensure proper performance, the following conditions m~st be
met. The specifications are valid only under these conditions:
o
The 4170 must be o~erating at an ambient temperature of 50
to 104 F
(10 to 40 C)(a)
Nonoperating
-40 to +125
Nonoperating
20 kV
compatibility
(related to line
transients)(c)
Oscillatory surge
susceptibility
3.0 kV
-----------------------------------------------------------Electromagnetic
vulnerability
Unidirectional
surge
susceptibility
vulnerability
3.5 kV
1 .5
kV
2.0 kV
-----------------------------------------------------------(a)Measured at 4170's rear panel.
(b)Derate the maximum operating temperature -1 C
for each 1,000 ft (300 m) above 5000 ft (1.5 km).
(c)This instrument qualifies under FCC Part 15 Subpart J Class A
computing devices and VDE 0871/6.78 with respect to radiated
and conducted emissions.
2-6
4170 INSTRUCTION
SECTION 2
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
These characteristics and specifications pertain to the 4170's power
supply outputs and its specifications.
Table 2-3
ELECTRICAL CHARACTERISTICS
: Characteristic
: Specification
I Fuse
I Internal 5 A
: Power supply input
: voltage requirements
: 87 to 128 Vac or
: 174 to 250 Vac
4170 INSTRUCTION
2-7
SECTION 2
SPECIFICATIONS
INSTALLATION REQUIREMENTS
Table 2-4 lists the factors (and values) to consider when
selecting the operation site for the 4170. Also, check the
dimensional requirements (in Table 2-1), and the environmental
factors (in Table 2-2).
Table 2-4
INSTALLATION REQUIREMENTS
: Characteristic
I Specification
: Heat disSipation
: 682 Btu (200 W). Includes Options!
: 03 , 09 , 10, 31, 45.
:
I
I
I
I
I
I
: Surge current
I
I
I
I
: 34 A (typical)
I
I
Cooling clearance
2-8
4 in min at rear fan exhaust. 3
in min at floor level, perpendicular to front and rear panel.
If carpet nap exceeds 1/2 in,
provide increased air flow by
supporting the 4170 to regain
min clearance.
4170 INSTRUCTION
SECTION 2
SPECIFICATIONS
FUNCTIONAL CHARACTERISTICS
The functional characteristics are grouped in three categories:
general characteristics (including 4170-to-terminal interfacing
information), specifications for the host interface, and finally,
specifications for the peripheral interface.
!able 2-5
GERERAL FUNCTIONAL CHARACTERISTICS
: Characteristic
Memory size
RAM (std)
(optional)
Disks (std)
(opt ional)
I Specification
256
512
768
896
K
K (Option 29)
K (Option 30)
K (Option 31 )
327.6 K (each) unformatted
10 M (Option 03)
I Operating system
l CP/M-86
: Available languages
I FORTRAN-86,
I/O ports
Interface
specification for
~rimary terminal
(4105, 4107, etc.)
Modes
ASSEI~BLER
Host -- RS-232-C (1 ea)
Terminal -- RS-232-C (1 ea)
Peripherals -- RS-232-C (2 ea)
Copier I/F port (option 9)
3 additional RS-232-C Ports
(Optional)
Full duplex (simultaneous
transmit and receive)
Data rate
Up to 19.2k baud (sustained)
Data protocol
Asynchronous
4170 INSTRUCTION
2-9
SECTION 2
SPECIFICATIONS
Table 2-6
HOST INTERPACE SPECIFICATIONS
: Charaoteristic
: Specifioation
: Operational modes
Data rates
: Data protocol
I
I
Full duplex
: 50, 75, 110, 134.5, 150, 300,
: 600, 1200, 1800, 2400, 4800,
: 9600, 19200 baud
: Asynchronous
I
I
Protocols
Full duplex data communications
DC1/DC3 flagging, for both
host-to-4170 and 4170-to-host
data flow
DTR (data terminal ready)
flagging for host-to-4170 data
flow
CTS (clear to send) flagging for
4170-to-host data flow
2-10
4170 INSTRUCTION
SECTION 2
SPECIFICATIONS
Table 2-7
PERIPHERAL IBTERPACE SPECIPICATIOB
l Characteristic
Operational modes
l Specification
Simplex: one-way data
transmission
Full duplex: simultaneous
transmit and receive
Data rates
: Data protocol
4170 INSTRUCTION
50,75, 110, 134.5, 150,300,
600, 1200, 1800, 2000, 2400,
3600, 4800, 7200, 9600, 19200
baud
l Asynchronous
2-11
SECTION 2
SPECIFICATIONS
Table 2-8
SOPTWARI SPBCIPICATIOIS
I Characteristic
I Specification
I Operating system
I CP/M-86
I Compiler
I FORTRAN-86
I Software support
I
package
I
2-12
: Local version of Tektronix
:
I PLOT-10 IGL (primary command set I
: and some device drivers)
I
4170 INSTRUCTION
SECTION 2
SPECIFICATIONS
Table 2-9
DISKETTE MEDIA CHARACTERISTICS
: Characteristic
Type
Soft-sectored
Storage Environment
Temperature
Humidity
Med ia lifetime
Passes per track
Insertions
4170 INSTRUCTION
: Value
5-1/4" flexible diskettes:
double-sided
double-density
48 tracks per inch
+50 to +122F
(+10 to +50C)
8 to 80%
3 million
30,000 +
2-13
SECTION 2
SPECIFICATIONS
Table 2-10
DISKETTE DRIVE UNIT CHARACTERISTICS
: Characteristic
: Double Density
Format data capacity
Per disk
327K bytes
(formatted)
500K bytes
(unformatted)
Per track
6,250 bytes
Transfer rate
I 250 kb/s
Access time
(average)
II 93 ms
Recording density
(ins id e track)
II 5876 b/in
Flux density
: 5,876 fcin
Track density
: 48 t/in
Number of tracks
: 40 tracks
2-14
I
I
4170 INSTRUCTION
SECTION 2
SPEC IFICATIONS
Table 2-11
USER-VERIFIABLE DRIVE UNIT SPECIFICATIONS
: Characteristic
: Value
: tolerance
: Rotational speed
: 300 r/min
: <+/->3 r/min
l Period between index
I
I
: pulses
: 200 ms
Seek access time
Track-to-track
Settling time
: Motor start time
4170 INSTRUCTION
6 ms
15 ms
: 500 ms max imum
2-15
Section ,
CONTROLS, INDICATORS, AND COIBECTORS
This section describes the controls, indicators, connectors, and
other features on the front and rear of the 4170.
'RONT PEATURES
The front of the instrument contains the following features (see
Figure 3-1):
o
Front control panel (controls and indicators)
o
Two disk drive units
o
Cue card
o
Lifting handle
The front panel is recessed where it meets the top panel, making
a handle. Use this and the rear handle when moving the 4170.
4170 INSTRUCTION
3-1
SECTION 3
CONTROLS
'igure ,-1. 4170 'ront Panel 'eatures.
3-2
4170 INSTRUCTION
SECTION 3
CONTROLS
COITROL PAIEL (EXPOSED ITEMS)
The control panel contains the following exposed items:
o
POWER switch -- This switch turns on the 4170.
o
POWER OR indicator -- Indicates the power is on by
displaying a green light.
o
STATUS -- Two digit display that indicates status codes
during Self Test. Each display can only display the 16
hexadecimal digits. When Option 03 is installed, these
displays indicates which track number the hard disk is
seeking. That track number will not change until the hard
disk is seeking another track.
o
WRITB PROTECT A and B -- These two switches set
o
Disk Drives A and B -- Drive A is the drive
~
located closest to the left-hand edge of the 4170. Drive B
is the remaining drive. Each drive has a unit busy
indicator and a diskette retainer. The unit busy indicator
is located above the diskette retainer and lights when the
drive is reading or writing on its diskette.
write-protection for their respective flexible drive units.
The lights indicate which drive units are currently
write-protected.
4170 INSTRUCTION
3-3
SECTION :3
CONTROLS
CONTROL PANEL DOOR
The control panel contains a small door that shields most of the
control buttons and several indicators. This door prevents an
operator's knee from bumping the control buttons. Remove
this door by pulling out on its left edge (use the finger notch
shown in Figure 3-2). This exposes the following controls and
indicators:
o
Three LED indicators:
T1, T2, T3
These indicators operate with Self Test to indicate what is
happening during the diagnostic program. If you are not
familiar with Tektronix terminals of the type that use these
lights, see Section 8 for a complete explanation.
o
Seventeen push buttons:
TEST -- Starts Self Test when
used with RESET.
RESET -- Resets the 4170; also used
with the TEST button to start Self Test.
RPT
Repeats current part of Self Test.
CTL
When pressed with other keys, sends control codes to
processor. Same as the control key on terminals.
C, D, E -- When used with the CTL button, sends control codes to
the processor.
F1 through F8 -- Performs the same functions as the special
function keys on your Tektronix terminal keyboard.
2nd -- Activates a function key's alternate function when
pressed with one of buttons F1 through F8.
CONT -- Continues running Self Test after it is halted.
3-4
4170 INSTRUCTION
SECTION 3
CONTROLS
'1aure ,·2.
4170 INSTRUCTION
Removing the Pop-off Door.
3-5
SECTION 3
CONTROLS
CUI CARD
The slot at the left of Disk Drive A contains a cue card. This
card pulls directly out and contains abbreviated instructions for
starting the 4170. It also contains some Self Test information. See
Figure 3-3.
3-6
4170 INSTRUCTION
SECTION 3
CONTROLS
POWER-UP AND OPERATING INFORMATION
1.
Insert the diskette containing CP/M-a6 Operating
System in drive A and close the diskette latch.
2.
Set the connected terminal baud rate to 2400 and
connect terminal to Terminal Port on 4170.
3.
Press the POWER button on the 4170.
4.
Wait for the 4170 Power-Up tesllo run. If the test
is successful, the operating system message and
prompt A> appears on the terminal screen. The
system is now operational and you may enter
commands.
(NOTE: cR = press Return key.)
SIDE 1
• To list files in your directory enter: DIR CR. Your
files list (on disk drive A) is displayed on the
terminal screen.
• To format a new diskette, first insert a new
diskette in drive B, then enter: FORMAT CR.
When a format question appears, answer:
B CR.
• Learn more about the system by using the
help feature, enter: HELP cR
5.
Refer to the 4170 Instruction Manual for more
extensive and detailed operating information.
SELF-TEST DIAGNOSTIC
INFORMATION
SUMMARY OF COMMANDS
The Self-Test program may be used to diagnose
system problems. If a hardware malfunction occurs,
this program helps locate the problem, and may print
an error message on the terminal screen. Section a in
the 4170 Instruction Manual includes a full
explanation of Self-Test and its error messages. To
run Self-Test:
1. Attach terminal to TERMINAL port of the 4170.
Terminal baud rate must be 2400.
2. Open the door around the two WRITE-PROTECT
switches on the 4170 front panel.
3. Simultaneously press the TEST and RESET
buttons on the 4170 front panel. Hold down TEST
for a few seconds after releasing RESET.
4. The first test performed is the keyboard test.
Upon completion the bell rings once, then do one
of the following:
a. Press any key to resume Self-Test.
b. Press CNTRL 0 to skip lengthy memory test.
c. Press CNTRL C to start the adjustment
portion of Self-Test.
5. If an error occurs a bell rings 2 or 3 times and an
error code is displayed on the 4170 front panel. If
possible, a message is also sent to the terminal.
6. When Self-Test is finished the operating system
message and prompt A> appears on the terminal
screen.
SIDE2
Refer to the CP / M-86 Command Reference Manual
for complete descriptions of each CP/M command this is only a summary.
*AR
ASM86
* CONFIG
COPYDISK
DDT86
*DEL
DIR
DIRS
ED
ERA
* FORMAT
GENCMD
HELP
PIP
REN
*RUN
*SD
STAT
SUBMIT
TYPE
USER
Archive a file
8086 assembler
Sets 4170 configuration
Disk-to-disk copy/backup
Dynamic (software) Debugging Tool
Delete a file
Lists the directory of disk files
Lists the system files on the disk
Character file editor
Erases a filename from the directory
Formats a new disk
Generates a command (executable) file
Help/information command
Peripheral Interchange Program
Rename a file
Execute a UDI program
Print an alphabetically sorted directory
Set/get status
Execute a command file
Copy a file to the terminal screen
Set/get your user number
* Tektronix Utility - see 4170 Instruction Manual for
complete descriptions.
P1gure ,-,. Cue Card.
4170 INSTRUCTION
REV, MAR 1984
3-7
SECTION 3
CONTROLS
DISK DRIVE
~BA'URES
The flexible-disk drive units each have a diskette loading slot.
After a diskette is inserted, rotate the wing-type disk retainer
clockwise. This holds the diskette in place.
WARNING
I
Do not attempt to remove a diskette while the
unit-busy indicator is on. Attempting to
remove a diskette when the unit-busy
indicator is on will cause data loss.
Each drive unit has a unit-busy indicator that lights when the
drive is writing or reading data to or from its diskette.
REAR PAnL
~EA TURES
The following connectors and switch are mounted on the 4170's rear
panel (see Figure 3-4).
3-8
4170 INSTRUCTION
SECTION 3
CONTROLS
Plgure ' -4. Rear Panel Peature ••
4170 INSTRUCTION
3-9
SECTION 3
CONTROLS
o AC IK -- This male IEC connector accepts a standard
ac power cord.
o AC OUT -- This female IEC connector provides ac power for
the terminal or other peripherals.
o MAIKS VOLTAGE SELECTOR -- This switch sets the 4170 to receive
either 115V or 230V ac power.
o HOST connector -- This 25-pin male connector supplies RS-232
communications to a remote host.
o '-PORT PERIPHERAL IKTERPACE -- These 25-pin female
connectors pass control and data to and from the 4170's periphera
o 'era1nal -- Connects the 4170 to its main terminal.
o Port 1 -- Connects the 4170 to a peripheral device or
secondary terminal.
o Port 2 -- (same as Port 1).
o EXTERKAL PERIPHERAL DC SOURCE
This 9-pin female
connector supplies dc power to a peripheral such as a
graphics tablet.
o OPTIOI 9 -- This optional connector passes control
and data signals to a Tektronix 4690 Series color copier.
o MASS STORAGE IITERPACE -- This connector passes data
and control between the 4170's optional mass storage interface
and an external mass storage device.
o RIMOTE OK OUTPUT -- The circuitry behind this connector
enables the 4170 to remotely operate optional disk units.
3-10
4170 INSTRUCTION
Section 4
INSTALLATION PROCEDURES
This section contains the procedures required to install your
4170; A repackaging procedure is also included in case you
ship your 4170 to another location.
Tektronix has made these procedures as simple as possible. Persons totally new to the 4170 have successfully
installed it using these procedures; have confidence that
you can too. But before you begin, some words of caution:
SELECTING A SITE
Figure 4-1 shows the 4170 dimensions and clearances.
Consider this information, potential cable routing problems,
and air circulation problems when selecting an installation
site.
READ EACH STEP THOROUGHLY AND LOOK AT EACH
ACCOMPANYING ILLUSTRATION BEFORE ATTEMPTING
THE STEP.
Should you encounter a problem, please call your local
Tektronix field office for assistance. Chances are that they
can correct your problem over the phone.
NOTE
During the installation procedure you will need
access to all sides of the 4170. Make sure that
you have enough room before you begin.
Figure 4-1. 4170 Dimensions.
4170 INSTRUCTION
REV, APR 1984
4-1
INSTALLATION
Most of the installation is done with the 4170 lying on its
side. it is easier to get to the components when the unit is in
this position. However, the circuit boards must be installed
(with the board components down) as shown in Figure 4-2.
·INSTALLATION GUIDELINES
NOTE
DO NOT LAY THE 4170 ON ITS SIDE UNTIL
INSTRUCTED TO IN THE PROCEDURE.
In addition, when installing a board, turn board ejectors so
that they are parallel with card guides, push board into
place, then lock board ejectors into place. Doing this will
ensure that the board is seated in its connector at the rear of
the card cage.
Figure 4-2. Installing a Circuit Board.
4-2
REV, MAR 1984
4170 INSTRUCTION
INSTALLATION
What To Install
Before You Begin
Table 4-1 lists all the procedures required to install your
4170. The table also has two columns that you need to
complete: the TO DO column and the DONE column. Look
at the table now. As you can see, some of the procedures
already have a check mark in the TO DO column. These are
the procedures that must be done for all 4170 installations.
To determine if you need to perform additional procedures:
There are 13 possible procedures for installing a 4170.
These procedures begin immediately after this explanation
and are a series of lettered steps. As you read each step,
you will notice a small box before each step. Place a check
mark in that box when you have completed the step.
1.
Find the list on the box(es) your 4170 is shipped in to
see what options were shipped with your 4170.
(4170F03 is shipped in a separate box.)
When you complete the entire procedure, put a check mark
in that procedure's DONE column in Table 4-1. This gives
you a record of the completed procedure and guides you to
the next procedure.
Begin the installation with Procedure 1 (unpacking).
2.
Place a check mark in the TO 00 column of Table 4-1
oppOSite each option shipped with your 4170.
The TO DO column of Table 4-1 now lists all the installation
procedures that you must do to install your 4170. Review
this list and temporarily remove this page from the manual.
With this page removed, you can easily refer to Table 4-1 to
find out what you must do next.
Table 4·1
INITIAL INSTALLATION PROCEDURES
Table 4-2 identifies the procedures that you will need to do if
an option is added after the 4170 has already been
installed. You don't need to go through the entire installation
procedure, just those steps listed in this table.
Procedure
Shipped
Option
1. Unpacking
-
",
2. Voltage Selection/Checkout
-
",
3. Removing Front Cover
-
",
4. Removing Side Cover
-
",
5. Installing Memory Options
4170F30,
4170F31,
4170F32,
4170F51
6. Installing Hard Disk
4170F03
4170F45
3,4,1,10,11,13
7. Installing Disk Interface
4170F44,
4170F45
8. Installing Peripheral
Interface
4170F10
9. Installing Color Copier
Interface
4170F09
10. Replacing Side Cover
-
",
11 . Replacing Front Cover
-
",
12. Connecting a Terminal
13. Verifying Operation
4170 INSTRUCTION
To Do
IF YOU ADD AN OPTION LATER
Done
Table 4·2
FUTURE OPTION INSTALLATION PROCEDURES
",
",
REV, MAR 1984
Option
Installation Procedure
4170F03
3,4,6,10,11,13
4170F09
3,4,9,10,11,13
4170F10
3,4,8,10,11,13
4170F30,F31,F32,
F51
3,5,11,13
INSTALLATION
1. UNPACKING
NOTE
Save all packing material and cartons for repackaging the 4170 in case you need to ship it to another
location.
A.
0
Before unpacking the unit, be sure to visually
inspect the shipping container for damage. Any
damage should be reported to the carrier
immediately.
NOTE
You can remove the 4170 from the shipping
carton by lifting it out of the box (it weighs
about 40 pounds) or by cutting the end of the
box and sliding the 4170 out. Study the pictures
and decide which you want to do. If you decide
to lift it out start with step B. If you decide to
cut the carton, start with step R
B.
0
Lift the protective packi ng off the top of the 4170
and set it aside.
NOTE
It is easier to complete the installation of the
options ifyou set the 4170 on a desk or table
where you can walk around it.
C.
0
Remove the protective plastic cover from the 4170.
D.
0
Lift the 4170 out of the carton using the two lifting
handles, just under the top front edge and about
four inches down from the back edge (indicated by
arrows). BE CAREFUL WHEN LIFTING TO AVOID
HURTING YOUR BACK.
E.
0
Set the 4170 upright on a desk or table and skip to
step J.
4170 INSTRUCTION
REV, MAR 1984
4-5
INSTALLATION
F.
0
Cut the end of the carton as shown and fold the
end of the carton down.
G. 0
Slide the 4170 out of the carton.
H. 0
Remove the packing material and plastic sheet
from the top of the 4170. Set the packing material
aside.
NOTE
It is easier to install options in the 4170 ifyou set
it on a desk or table where you can walk around
it.
I.
0
Carefully pick the 4170 up, lifting it off the bottom
packing material, and set it upright on a desk or
table.
J.
0
Remove, BUT DO NOT OPEN, the remaining
boxes, containing the 4170 software and optional
F-kits from the carton and set them aside until later.
K. 0
Check that accessories in box with the 4170 manual are all present.
0
You are done with Procedure 1. Check it off Table
4-1 and go to Procedure 2.
L.
4-6
REV, MAR 1984
4170 INSTRUCTION
INSTALLATION
2. VOLTAGE
SELECTION/CHECKOUT
A.
0
Set the Voltage Selection switch on the back of the
4170 to correspond to your facility line voltage
(115Vor 230V).lf you're not sure, ask someone.
8.
0
Remove the CAUTION label from the AC IN
CONNECTOR. Remove the ac power cord from
the accessory box and connect it to the AC IN
connector on the rear panel.
C.
0
Connect the power cord to the nearest ac outlet.
.&.
~
Verify the switch (step A) is set to correct voltage.
O.
0
Peel "N' and "8" adhesive disk drive labels from
the backing paper and stick them next to the disk
drives A and 8 busy indicators as shown. The "C"
and "0" labels are extra and can be used externally in the future.
E.
0
Apply power by pressing the POWER switch.
F.
0
The 4170 runs an automatic internal test. Satisfactory completion is signaled by a single bell. the
code 00 displayed on the status indicator, and both
A and 8 disk drive busy lights are not lit.
NOTE
Any other code indicates the power-up test
failed. Contact your local Tektronix service
center, DO NOT GO ANYFURTHER.
G.
0
You are done with Procedure 2. Check it off Table
4-1 and go to Procedure 3.
4170 INSTRUCTION
REV, MAR 1984
4-7
INSTALLATION
3. REMOVING THE FRONT COVER
~
There are no exposed hazardous voltages in the
4170. However, components may be damaged if
boards are installed or removed while power is on.
To avoid this potential hazard ALWAYS turn off
power and disconnect the power cord before
removing covers from the unit.
A.
0
Turn off power.
B.
0
Unplug the power cord.
C.
0
Remove the two slotted screws from the bottom of
the front cover. You should be able to remove these
screws by hand. If not, use a small coin to loosen
them.
D.
0
Remove the front cover by pulling out at the bottom
and sliding it down to free it from the top panel.
E.
0
You are done with Procedure 3. Check it off Table
4-1 and find out what you need to do next.
4170 INSTRUCTION
REV, MAR 1984
4-9
INSTALLATION
4. REMOVING THE SIDE COVER
NOTE
When laying the unit on its side, it is advisable to
place the plastic bag your 4170 was packed in
under it to prevent scratching the paint.
A.
0
Lay the 4170 down on its left side.
NOTE
The screwdriver is in the accessory carton with
this manual, the ac power cord, and the interface cable.
B.
0
Using the screwdriver that came with the 4170,
remove the two large screws from the back of the
unit. (These two large screws secure the side
cover in place; they are not the smaller screws that
secure the individual connector panels in place.)
C.
0
Remove the three front screws (earlier units had
only two front screws).
NOTE
In the next step you may have to gently lift each
corner of the cover to free it from the guides
before removing the cover.
D.
0
Grasp the cover at the upper corners as shown and
lift it off.
E.
0
Set the cover aside.
F.
0
You are done with Procedure 4. Check it off Table
4-1. Before you do the next procedure, review
Figure 4-3, which follows, to learn the location of
major components.
4170 INSTRUCTION
REV, APR 1984
4-11
INSTALLATION
~
LOCATION OF MAJOR
COMPONENTS
The major component locations are shown in Figure 4-3.
You should familiarize yourself with these components
since they are referred to in the following
procedures. The name following the board slot name is the
name found on the board installed in that slot.
When you are installing and removing boards from
the unit, try to handle the boards only by the ejectors. Some of the boards have static sensitive components on them and there is a risk of damage.
Exercise care when handling them.
NOTE
The card cage is held in place by the side cover.
With the side cover removed the card cage is loose.
This is normal.
Figure 4-3. Major Component Locations.
4-12
REV, MAR 1984
4170 INSTRUCTION
INSTALLATION
5. INSTALLING MEMORY OPTIONS
BEFORE STARTING
called "Memory" boards although the name "ECC RAM
Controller" is printed on the boards.) After you remove the
boards, the procedures instruct you to move some clips on
each board; these clips are small rectangular blocks that
connect two pins (see the illustration below). After you
remove the boards, you will be able to see the clips clearly.
In Steps A, B, and C (which follow), you will remove the
Memory boards from the STD RAM and OPT RAM slots of
the card cage, and from the carton containing the optional
Memory boards. (In the procedures here, the boards are
Figure 4-4 shows the clip positions as the boards are
shipped from the factory. Follow the procedures to determine exactly what clips you must move on each board.
(Some clips are preset and should not be moved.)
(4170F30, 31,32, & 51)
CLIP
Figure 4-4. Memory Board Clip Locations (as shipped from factory).
4170 INSTRUCTION
REV, MAR 1984
4-13
INSTALLATION
A.
0
Remove the Memory board from the STD RAM
(bottom) slot in the card cage by pulling out on the
board ejectors to release the board. Slide it out and
set it aside for the moment.
B.
0
If there is a board in the OPT RAM slot of the card
cage remove it as well.
NOTE
The Memory board(s) removed in Step A or
Step B may not necessarily be returned to the
slot it was removedfrom. Do not worry; just
follow the instructions exactly for a successful
installation.
4170F30
..," #
""'\.
SCREWS (4)
A. SINGLE RAM ARRAY BOARD
4170F51
c.
4-14
SINGLE MEMORY DU'KnLl
B. FULL MEMORY BOARD
+ RAM ARRAY BOARD
4170F31
D. FULL MEMORY BOARD
REV, MAR 1984
4685-18A
4170 INSTRUCTION
INSTALLATION
C.
D
Open the carton containing the Memory F-kit
(4170F30, F31, F32 or F51) and remove the parts
from the shipping envelopes.
If your kit has a RAM Array board (4170F30 or 32) continue
with step D. Otherwise skip to step G.
D.
D
Install the small RAM Array board on the Memory
board removed from the 4170 by carefully aligning
the connector pins on the bottom of the RAM Array
board with the socket on the top of the Memory
board as shown.
HINT: Seat RAM Array board by pressing at
the center of the pins. Be careful - pins are
sharp.
E.
D
Push the RAM Array board down until the pins are
seated in the socket (the bottom side of the RAM
Array board is flush with the top of the socket and
the board rests on the four posts on the Memory
board).
F.
D
Use the four screws from the kit to secure the RAM
Array board to the posts on the Memory board.
4170 INSTRUCTION
REV, MAR 1984
4-15
INSTALLATION
G.
0
H. 0
I.
0
Pick up a full Memory board. (A full Memory board
has two small RAM Array boards installed, as
shown in the upper left corner of the illustration
above.)
Move the four clips as indicated. (The illustration
above uses small squares and circles to represent
the pins on the board.) Because the clips fit tightly,
to remove them you may need to wiggle them while
pulling gently on them, or you may need to use
your fingernail or a thin object to loosen them.
Check the other clips and make sure they are
properly installed, if not move them to the proper
pins.
NOTE
Remember when installing boards that the component side should be down, and the board
should be handled by the ejectors to prevent
possible damage to components.
J.
0
Install the board in the STD RAM (bottom) slot of
the card cage. Lock the board in place by pressing
in the board ejectors until they lock over the edge
ofthe board.
K.
0
If you only have one Memory board you are done.
Check Procedure 5 off Table 4-1 and go to the next
procedure. Otherwise continue with step L.
4·16
REV, APR 1984
4170 INSTRUCTION
INSTALLATION
L.
D
If the remaining board looks like the board in A, set
the clips as indicated under A. If it looks like B, use
the settings under B.
4170 INSTRUCTION
REV, APR 1984
4-17
INSTALLATION
NOTE
Remember when installing boards that the component side should be down, and the board
should be handled by the ejectors to prevent
possible damage to components.
M.
0
Install the board in the OPT RAM slot of the card
cage. Lock the board in place by pressing in the
board ejectors until they lock over the edge of the
board.
N.
0
You are done with Procedure 5. Check it off Table
4-1 and find out what you need to do next.
4-18
ADD, MAR 1984
4170 INSTRUCTION
INSTALLATION
6. INSTALLING THE HARD DISK
UNIT (4170F03)
~
The Disk Unit can be damaged by dropping or
by a blow. Handle it with care.
A.
0
Open the carton containing the Hard Disk by cutting the tape on the top of the carton.
B.
0
Cut the tape on the inside packing and lift top
cover.
C.
0
Remove box containing Disk Unit and cut tape to
open box.
D.
0
Insert a finger in the holes on each end of the DISK
RETAINER and carefully lift the retainer and Disk
Unit out of the box.
E.
0
Save all packing materials for use later, if you need
to repackage the Hard Disk for shipment to
another location.
NOTE
Lookfor and save data sheets(s) shipped with
the hard disk. This information will be used
later.
4170 INSTRUCTION
REV, MAR 1984
4-19
INSTALLATION
F.
0
Loosen (BUT DO NOT REMOVE) the four disk
mounting stud screws (located on the bottom of the
4170 cabinet behind the card cage) about V4 inch.
G.
0
Look at the way the power supply is held in place.
The hard disk will be held in place in the same
manner.
H.
0
Orient the hard disk as shown in the illustration.
Note that the plug labeled P9 should be toward the
card cage, not the back of the 4170.
I.
0
The hard disk may be awkward to position. It
requires careful handling, since dropping it or
bumping it sharply may result in damage. Hold the
hard disk in one hand and move the cable bundle
aside with your other hand. Slide the hard disk into
position. The mounting studs go through the large
holes in the disk mounting brackets.
J.
0
Move the hard disk so the mounting studs are in
the narrow slots in the hard disk mounting brackets.
K.
0
Tighten the four mounting screws securely. If the
screws are loose, the Disk Unit could vibrate loose
during operation.
L.
0
Connect P9 to the connector on the back edge of
the card cage as shown. Plug P9 is keyed to aid in
proper orientation.
M.
0
You are done with Procedure 6. Check it off Table
4-1 and go to Procedure 7.
4-20
REV, APR 1984
CARD CAGE
4170 INSTRUCTION
INSTALLATION
7. INSTALLING THE DISK
INTERFACE (4170F44 & 45)
Two different Disk Interfaces are available for the 4170. Only
one may be installed. One is used to control the two Flexible
Disk drives that are standard in the unit. This disk interface
is the Flexible Disk Interface (4170F44). If you have a hard
disk (4170F03), this disk interface is the optional Flexiblel
Hard Disk Interface kit (4170F45). This procedure installs
either disk interface.
A.
0
Open the carton containing the Disk Interface kit.
B.
0
Remove all of the parts from their individual packaging and verify that the kit parts correspond to
one of these pictures.
'\
/
4170 INSTRUCTION
REV, MAR 1984
4-21
INSTALLATION
~
To avoid breaking wires when disconnecting cables,
grip the connector by the plug and pull. DO NOT
PULL THE CABLE OFF BY PULLING ON
THE WIRES.
C.
D
Disconnect the cable from the front edge of the
Processor board.
D.
D
Take cable assembly 1 from the kit. You will note
that there are two connectors near one end of the
cable, marked P1 A and P1 B in the picture. Plug
the P1 B connector (on the end of the cable) into
the socket on the back of DISK DRIVE B, orienting
the locating stripe as shown. Now plug the other
(P1A) connector into the socket on DISK DRIVE A.
See inset figure for 4170F44.
HINT: Compare the disk units to the picture
to make sure you understand the cable connections and orientation.
E.
0
Route the other end of the cable between the edge
of the card cage and the cabinet frame as shown. It
will be connected in Procedure 10.
HINT: Remove the cable clamp by simultaneously lifting both ends of the upper portion
of the clamp.
4-22
REV, MAR 1984
4170 INSTRUCTION
INSTALLATION
NOTE
Remember when installing boards that the component side of the board must be down, and the
board should be handled by the ejectors to prevent possible damage to the components.
F.
0
Slide the Disk Interface board into the DISK ifF slot
in the card cage. Do not attempt to seat the board.
This will be done later.
G.
0
If you have installed all of the parts in your kit, skip
to step P. Otherwise continue with step H.
HINT: You may need to slide the Disk Interface board part way out of the card cage so it
does not interfere with the edge connector.
H.
0
Remove cable assembly 2 from the kit. Hold the
edge connector so that you can see the locating
mark as you look down on the edge connector.
HINT: Stand with the back of the 4170 (the
part with the voltage selector switch on it) in
front of you. Now look down and you will see
the 4170 as shown in the small inset figure.
I.
0
Slide one end of the edge connector through the
DISK ifF opening as shown. Push the remainder of
the connector through the opening then pull it back
out far enough so the shoulders on the connector
are against the inside of the card cage.
J.
0
Secure the connector to the back of the card cage
using the two screws from the kit.
4170 INSTRUCTION
REV, MAR 1984
4-23
INSTALLATION
K.
0
Plug the Hard Disk connector to P2 on the Hard
disk as shown. Make sure orientation is correct
(Pin 1 is down and cable exits connector to the
front of the 4170).
CARD CAGE
4170 INSTRUCTION
REV, MAR 1984
4-25
INSTALLATION
l.
0
Keeping the screws for use, remove and discard
Blank Panel 1 from the back of the 4170.
M.
0
Position the panel (connected to the cable installed
in H) as shown and secure it using the four screws
removed in J. Tighten the screws.
HINT: Do not connect the rest of the cables
at this time. They will be connected later.
NOTE
Do not do steps Nand 0 if you are going to connect Mass Storage Interface Bus (MSIB) compatible devices, such as TEKTRONIX 4926 10M Byte
Hard Disk Drive, to the 4170.
The following is a list of permitted external CP/M-a6 disk
drive names (C:, 0:, E:, etc.) that correspond to user
selected MSIB addresses. MSIB address 0 is assigned to
internal 4170 hard disks C: and 0: (0: is not presently used).
Use this list when you are assigning MSIB addresses to the
connected MSIB devices. MSIB address assigning is done
at the external MSIB device. Refer to the device manual to
find out how to set the MSIB address for the device.
CP/M-86 Drive Names
Mise Address to
Assign
C:and 0:
E: and F:
G: and H:
l:andJ:
K: and L:
M: and N:
0: and P:
Reserved
o
1
2
3
4
5
6
7
N.
0
Remove the TERMINATOR from the kit and plug it
into the socket on the panel as shown. TERMINATOR is keyed.
O.
0
Lock the TERMINATOR in place by tightening the
two holding screws on the TERMINATOR
assembly.
p.
0
You are done with Procedure 7. Check it off Table
4-1 and find out what you need to do next.
4-26
REV. MAR 1984
4170 INSTRUCTION
INSTALLATION
8. INSTALLING THE OPTIONAL
PERIPHERAL INTERFACE
(4170F10)
A.
0
Open the carton containing the Peripheral Interface F-kit.
B.
0
Remove all of the parts from their individual packaging and verify that the kit contains the parts
shown in the picture.
HINT: Stand with the back ofthe 4170 (the
part with the voltage selector switch on it) in
front of you. Now look down and you will see
the 4170 as shown in the small inset figure.
C.
"'
0
Hold the edge connector with the locating mark so
you can see the locating mark as you look down on
the edge connector. Slide the end of the edge
connector through the 1st OPT opooing as shown.
Push the rest of the connector through the opening
then pull it back out far enough so the shoulders of
the connector are against the inside of the card
cage. Secure with two screws from kit.
OVERLAY
BACKPLATE
A. OPTIONAL PERIPHERAL INTERFACE KIT
\
4170 INSTRUCTION
REV, MAR 1984 .
4-27
INSTALLATION
D.
0
Keeping the screws for later use, remove and
discard Blank Panel 2 from the back of the 4170.
NOTE
There is printing on both sides oj overlay.
Ensure that correct label (PORT 3, PORT 4,
and PORT 5) Jaces out.
E.
0
Place the overlay on the new backplate as shown.
F.
0
Align the new backplate (with the overlay) behind
the opening in place of Blank Panel 2. Secure the
backplate with the screws removed in step D.
4-28
REV, MAR 1984
4170 INSTRUCTION
INSTALLATION
G.
D
Verify that the I/O ADDR clip is in position FB40 as
shown.
NOTE
Remember when installing boards the component side of the board must be down and the
board should be handled by the ejectors to prevent possible damage to the components.
H.
D
Slide the Peripheral Interface board into the 1st
OPT slot in the card cage. Lock the board in place
by pressing in on the board ejectors until they lock
over the edge of the board.
HINT: If the board does not slide in and lock
easily you may have installed the edge connector (step C) upside down.
I.
D
You are done with Procedure 8. Check it off Table
4-1 and find out what you need to do next.
4170 INSTRUCTION
REV, APR 1984
4-29
INSTALLATION
9. INSTALLING THE PARALLEL
COLOR COPIER
IIFBOARD
INTERFACE (4170F09)
A.
D
Open the carton containing the Parallel Interface
F-kit.
B.
D
Remove all of the parts from their individual packaging and verify that the kit contains the parts
shown in the picture.
BACKPLATE
HINT: Stand with the back of the 4170 (the
part with the voltage selector switch on it) in
front of you. Now look down and you will see
the 4170 as shown in the small inset figure.
SCREWS (2)
A. PARALLEL INTERFACE KIT
C.
D
Hold cable assembly edge connector so you can
see the locating mark as you look down on the
edge connector. Slide end of it through the 2nd
OPT opening in the back of the card cage as
shown. Push the rest of the connector through the
opening, then pull it back far enough so the shoulders of the connector are against the inside of the
card cage. Secure the connector using the screws
provided in the F-kit.
4170 INSTRUCTION
REV, MAR 1984
4-31
INSTALLATION
D.
0
Keeping the screws for later use, remove and
discard Blank Panel 2 from the back of the 4170.
E.
0
Align the new backplate behind the opening as
shown. Secure the backplate with the screws
removed in D.
NOTE
Remember when installing boards the component side of the board must be down and the
board should be handled by the ejectors to prevent possible damage to the components.
F.
0
Slide the Interface board into the 2nd OPT slot in
the card cage. Lock the board into place by pressing in the board ejectors until they lock over the
edge of the board.
G.
0
You are done with Procedure 9. Check it off Table
4-1 and find out what you need to do next.
4-32
REV, MAR 1984
4170 INSTRUCTION
INSTALLATION
10. REPLACING THE SIDE COVER
A.
D
Check to make sure that all internal screws and
connections you have made are tight.
B.
D
Set the 4170 back upright.
NOTE
Look on the side oj the card cage Jor the threewire cable.
C.
D
Connect the three-wire cable to J206 (on the side
of the DISK IIF card) as shown.
D.
D
If you have the hard disk interface (4170F45) in
your 4170, skip to Step I.
E.
D
Connect the large disk cable to the connector on
the edge of the Disk IIF board, making sure the
four white-wire loops are down.
F.
D
Lock the DISK IIF board in place by sliding it in and
pressing in the board ejectors until they lock over
the edge of the board.
G.
D
Connect the processor cable to the connector on
the edge of the Processor board as shown. The red
stripe on the cable should be down.
H.
D
Skip to step L.
4170 INSTRUCTION
REV, APR 1984
4-33
INSTALLATION
NOTE
You may find it easier to remove the DISK IIF
board to attach the disk cable to it.
I..
0
Connect the large flat cable to the connector under
the edge of the Disk ifF card as shown. Make sure
that the red stripe on the cable is down and that the
pins and connector are properly aligned.
J.
0
Lock the Disk ifF board in place by sliding it in and
pressing in the board ejectors until they lock over
the edge of the board.
K.
0
Connect the processor cable to the connector
along the edge of the Processor board as shown.
The red stripe on the cable should be down.
L.
0
Route cables through cable clamps as shown in
Figure 4-5 if you do not have a Hard Disk. Route
cables as shown in Figure 4-6 if you have a Hard
Disk.
4-34
REV, MAR 1984
4170 INSTRUCTION
INSTALLATION
Figure 4-5. Cable Routing (Without Hard Disk).
Figure 4-6. Cable Routing (With Hard Disk).
4170 INSTRUCTION
4-35
INSTALLATION
M.
0
Lay 4170 down on its left side.
N.
0
Position the card cage so that it is not resting on
the two guides located between the disk drives and
the card cage. The guides are part of the cabinet
frame.
O.
0
Carefully slide the side cover on. Pay particular
attention to aligning the guides on the inside top of
the side cover with the top of the cabinet frame.
Be sure the cabinet frame screen clears the side
cover.
HINT: The card cage is held in place by the
side cover. You may need to slightly reposition it so the side cover will slide into place.
p.
0
Check around the sides of the side cover to make
sure it fits tight on the frame.
Q.
0
Replace the two screws on the back of the unit as
shown.
R.
0
Replace the three screws on the front of the unit as
shown.
S.
0
You are done with Procedure 10. Check it off Table
4-1 and go to Procedure 11.
4-36
REV, APR 1984
4170 INSTRUCTION
INSTALLATION
11. REPLACING THE FRONT COVER
A.
0
Set unit upright.
HINT: Look at the circuit board installed in
either the 3PPI or PROCESSOR slot to see a
locked ejector. Note how ejector contacts the
card cage.
B.
0
Verify that all the boards are properly installed and
the board ejectors are locked.
C.
0
Slide the front cover into place as shown. Make
sure the upper right edge of the cover slips behind
the back of the control panel as shown.
D.
0
Replace the two knurled screws as shown to
secure the front cover.
E.
0
You are done with Procedure 11. Check it off Table
4-1 and find out what you need to do next.
4170 INSTRUCTION
REV, MAR 1984
4-37
INSTALLATION
12. CONNECTING A TERMINAL
~
When connecting cables make sure they are out of
the way and do not present a hazard to people
walking by.
A.
D
Connect one end of the terminal interface cable to
the TERMINAL connector on the back of the 4170
as shown.
B.
D
Connect the other end of the cable to the connector on the back of the terminal. On a Tektronix
4105,4107, or 4109 terminal, the connector is
labeled COMPUTER.
c. D
TERMINAL
CONNECTOR
c::=J
DO
Connect the power cord from the terminal to the
AC OUT connector on the back of the 4170 as
shown.
HINT: Some terminals are designed to only
be connected to a wall outlet. They cannot
be connected to the 4170. In this case, connect the terminal to facility power and turn it
on. You can, however, connect the Tektronix
4105,4107, and 4109 terminals directly to
the 4170 using the interface cable supplied.
D.
D
Connectthe 4170 power cord to the AC IN connector on the back of the 4170 as shown.
E.
D
Connect the other end of the 4170 power cord to
the nearest power outlet and turn on power to the
terminal.
F.
D
Turn disk drive A and B diskette retainers to
open position as shown. Pull out shipping retainers. Save retainers with the rest of the packing materials.
G.
D
Insert Cue Card in slot to left of Drive A.
H.
D
You are done with Procedure 12. Check it off Table
4-1 and go to Procedure 13 to verify operation.
)
4170 INSTRUCTION
REV. APR 1984
4-39
INSTALLATION
13. VERIFYING OPERATION
A.
0
Press the power switch to apply power to the 4170.
NOTE
Failure ofthefollowing steps indicates the internal diagnostics of the 4170 detected an error.
Verify that you completed the installation procedures correctly. If the problem is still present,
contact your local Tektronix Service Center for
assistance.
B.
0
Verify the bell rings once, 00 status is displayed,
and the red disk drive A busy indicator is on.
C.
0
Save the test connector that came in the accessory
carton (with the screwdriver, the power cords, and
the terminal interface cable). This connector is
used during self-test procedures that may be performed at a later time.
D.
0
You have completed the installation and checkout
procedures and your 4170 is ready for use. Go to
the Getting Started section in this manual.
NOTE
Remove and open remaining box in 4170 shipping box. This box contains your diskettes and
additional manuals.
4170 INSTRUCTION
REV. APR 1984
4-41
INST AllA nON
4.
REPACKAGING INSTRUCTIONS
(K) Unplug the cable from P2 on top of the Hard Disk
unit.
If you need to repackage the 4170 for shipment to another
site you should use the original materials that were used to
ship the 4170 to you. If these materials are no longer available contact your local Tektronix representative to obtain the
materials you need. Once you have the materials, proceed
as follows:
1.
Turn off power to the 4170 and disconnect all external
cables and power cords.
2.
If your 4170 has a Hard Disk installed you will need to
remove it. The Hard Disk removal and packing is
described in steps 3 through 6. If you do not have a
Hard Disk go to step 7.
3.
(F) Loosen the four disk mounting screws.
(H) Remove the disk by Sliding it toward the power
supply module (to clear the mounting screws) and
lifting it out of the mounting cabinet. Tighten the
four mounting screws.
(D) Set the disk in the Disk Retainer and place it in the
box.
(e) Seal the box with tape and place the box in the
large shipping carton (8).
(A) Seal the shipping carton with tape.
Remove the front and side covers from the 4170. (Refer
to Installation Procedures 3 and 4 for details.)
5.
6.
Replace the side cover (see steps M, N, 0, and P of
Installation Procedure 10).
Replace the front cover (see 11, REPLACING THE
FRONT COVER).
NOTE
In step 4 the letters in parentheses refer to the
corresponding steps of9, INSTALLING THE
HARD DISK UNIT.
(l) Unplug the cable from P9 on the card cage.
7.
Install the shipping retainers in the disk drives (Installation Procedure 12, step G).
8.
Place the 4170 in the shipping cartons as shown in
Figure 4-7.
9.
Place the diskettes and software manuals in the large
box, seal the box with tape and place it in the bottom of
the shipping carton.
10. Place this manual, the power cable, POZIDRIVE®
screwdriver, and other accessories in the small accessory box and place the box in the shipping carton.
11. Seal the shipping carton with reinforced tape, apply the
necessary shipping labels to the 4170 and Hard Disk
cartons.
The 4170 is now ready to ship to another site.
4-42
REV. MAR 1984
4170 INSTRUCTION
INST ALLATION
Figure 4-7. Repacking.
4170 INSTRUCTION
4-43
REV, MAR 1984
Section 5
GETTING STARTED
INTRODUCTION
This section introduces you to the operation of the 4170 and
tells you how to get the 4170 running for the first time. Before
reading this section, follow the instructions in Section 4,
Installation, for installing your 4170 and for connecting a
terminal to your 4170.
This section covers:
o
Setting up communications with your terminal.
o
Loading the CP/M-86 operating system.
o
Making backup copies of the operating system diskette and
other software.
o
Using the optional hard disk (including how to format the
hard disk and how to set up the hard disk so that the
operating system automatically loads from the hard disk).
o
Connecting the 4170 to a host.
o
Connecting the 4170 to a printer.
HOW TO USE THIS SECTION
If you just installed the 4170 and this is the first time that
you are using it, follow the first three procedures in this
section (to establish communications with your terminal, to load
the operating systeill, and to make a backup copy of the operating
system diskette).
After you have made a back-up copy of the operating system
diskette, you may want to read other procedures in this section
if you are going to use a hard disk, host communications, or a
printer. If you are not going to use a hard disk, host
communications, or a printer, you may decide to skip those
procedures. Instead, you may want to load an applications
program, using the instructions provided with it, or you may want
to go directly to Section 6, Operating Information, to do the
exercises there and learn some other CP!M-86 operating system
commands.
4170 INSTRUCTION
Rev, Mar 1984
5-1
SECTION 5
Getting Started
PROCEDURES FOR FIRST-TIME OPERATION
SETTING UP COMMUNICATIONS WITH YOUR TERMINAL
Use these procedures to estRblish communications between your
terminal and the 4170. Because some applications packages re~uire
you to change communications parameters, even after using the
4170 for some time, you may lose communications on occasion; if
so, refer back to the procedures here to reestablish
communications between the terminal and the 4170. Before you
begin, check that the cable between your terminal and the 4170's
terminal port (Port 0) is securely connected.
1. If the 4170 and the terminal are not already on, press the
power button on the 4170 (Figure 5-1) and on the terminal.
(When you turn on the 4170, it tests certain parts of its
circuitry. When this self-test is complete, the 4170's bell
rings once and the STATUS display on the front panel changes
from "FF" to "00".)
Figure 5-1. Turning on the 4170.
5-2
Rev, Mar 1984
4170 INSTRUCTION
uECTION 5
GETTING STARTED
2. Set the terminal's communication parameters. How you do this
depends on the kind of terminal you have. Here are the
parameters that you must set:
o
o
o
o
o
Baud rate - 2400
Flagging - in/out ("in/out" flagging is DC1/DC3 flagging
on a 4100 Series terminal)
Parity - none
Stop bits - 1
Data bits - 8
NOTE
Flagging for the terminal should be set
to in/out (which is DC1/DC3 flagging).
Flagging for the 4170 is set to "none"
(by the CMOS-reset procedure in the next
step). If you are going to use applications
programs that use CTRL-S or CTRL-Q (such as
Wordstar, SuperCalc or Emacs), flagging for
the 4170 must be set to none or these
programs will not work properly; the
terminal's flagging may be set to in/out
(DC1/DC3) as described here.
Tektronix 4100 Series Terminals. If you are connecting the
4170 to a Tektronix 4100 Series terminal, refer to Table 5-1.
4170 INSTRUCTION
Rev, Mar 1984
5-3
SECTION 5
GET'rING STAR'rED
Ta ble 5-1
CHANGING A 4100 SERIES TERMINAL'S COMMUNICATION PARAMETERS
I Terminal Type
I
I
5-4
I To Change Parameters
I Using Setup Commands
Tektronix
4105, 4107, or
4109 termin:3.ls
*baudrate 2400
*flagging in/out
*parity none
*stopbits 1
Tektronix
4112, 4113,
4114, 4115, or
4116 terminals
*baudrate 2400
*flagging in/out
*parity none
*stopbits 1
Rev, Apr 1984
I Alternate Method
I
I
*factory
*flagging in/out
I
Reset the terminal's
Setup memory and set
the terminal flagging
to in/out. Refer to
the operators manual
for the specific
terminal.
4170 INSTRUCTION
SECTION 5
GETTING STARTED
The middle column of Table 5-1 lists the Setup commands that
you must enter to set the terminal's communication parameters.
To set the parameters on a 4105, for example, put the terminal
in Setup mode (by pressing the Setup key) and enter these
Setup commands (the means that you should press the
RETURN key; the * is the Setup mode prompt):
*baud 2400SETDEV con, baud=19200
Then change the baud rate for your terminal. If you have a
Tektronix 4100 Series terminal, press the Setup key and enter
this Setup command:
*baud 19200
Press the Setup key again to take the terminal out of Setup
mode, and press .
MAKING A BACKUP OF THE OPERATING SYSTEM DISKETTE
This procedure describes how to make a copy of the CP/M-86
operating system diskette. After you have successfully loaded the
operating system for the first time, you should immediately make
a copy of the operating system diskette. Store the original in a
safe place, and use the copy for your day-to-day operations. This
way, if the copy is damaged, you still have the original diskette
and can make another copy.
The procedure consists of two steps: (1) formatting a new
diskette, and (2) copying the operating system diSkette. You will
need a new blank diskette before you can copy the operating
system diskette.
Tektronix recommends that you use this same procedure to copy all
diskettes supplied to you. You may use the 10 extra blank
diskettes (supplied with the 4170) for this purpose.
5-12
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
Formatting a New Diskette
This procedure formats a disk in drive B. If you make a typing
mistake at any time, use the Backspace or Rubout keys to correct
the error.
1. Enter the command FORMAT B: after the system prompt A>:
A>FORMAT B:(CR>
CAUTION
Formatting destroys any data that may be on
the diskette. Be sure that you do not need
any data on the diskette you're going to
format, or that it is a new blank diskette,
before you confirm the FORMAT operation in
the next step.
2. The system responds with this prompt:
Formatting drive B:
5 1/4" Double-Sided Floppy (512 bytes/sector)
with interleave of O.
Insert a disk in drive B.
Format the disk? (Y or N; default N):
Insert a new diskette into Drive B and close the drive door
latch. Enter Y and press
when the prompt reappears.
3. When the format is completed, the system prompts for another
diskette:
Formatting completed.
Insert a disk in drive B.
Format the disk? (Y or N; default N):
If you want to format other diskettes at this time, enter
Y(CR>; otherwise, press any key except Y and then
.
Copying the Operating System Diskette
Next, you will copy the CP/M-86 operating system diskette to the
diskette that you just formatted. Make sure the CP/M-86 operating
system diskette is in drive A and that the formatted diskette is
in drive B.
5-14
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
1. Enter the command COPYDISK after the system prompt A>:
A>COPYDISK
When the COPYDISK utility is loaded into memory from the
operating system diskette, this prompt appears:
CP/M-86 Full Disk COpy Utility
Version 2.0
Enter Source Disk Drive (A-D)?
2. Enter A to indicate that you want to copy the
operating system diskette in drive A.
Enter Source Disk Drive (A-D)? A
If the nothing happens after you press to indicate that you are going to write on the
formatted diskette in drive B.
Again, if nothing happens after you press to confirm the copy.
The system first reports that the copy is started:
Copy started
This is followed by a message that tells you what stage of the
copy is taking place. There are three stages during the copy.
First, the system reads each track on the diskette in the
source drive. Then, it writes each track to the diskette in
the destination drive. Finally, the system verifies that each
track was correctly written. During the three stages, the
system updates a message on your screen that looks like this:
Reading track ##
If the destination drive is write-protected (either by the
switch or the notch in the diskette), an error like this is
displayed:
Permanent Error Writing Track 79, Sector 31
Ignore error (yiN)?
If this error occurs, unprotect the diskette or the drive,
enter N to exit from the COPYDISK program, and try again.
This kind of error may also occur during the verification
stage; if so, enter N and try the copy again.
5-16
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
5. If the copy is successful, the system reports when the copy is
completed and prompts you for another copy:
Copy completed.
Copy another disk
(yiN)?
Enter .(CR> to exit the copy program.
6. Remove the operating system diskette from Drive A. Store it
in a safe place.
CAUTION
The next step instructs you to create a label
for the copy of the operating system
diskette. To prevent damage to the diskette,
write out the label before you place it
on the disk.
7. Remove the duplicate operating system diskette from drive B.
Attach a label to the diskette so you can identify it as a
copy of the operating system diskette.
8. Install the duplicate operating system diskette in drive A.
9. Press CTRL-C (the CTRL and the C keys at the same time) on the
terminal keyboard to "log-in" the new disk in drive A. After
you ~ress CTRL-C, the system responds with the system prompt
A>. (When you insert a different diskette or when you
switch between drives A and B, a CTRL-C at the terminal
informs the system of the change. If you don't press the
CTRL-C and you try to write to the diskette, you may get an
error.)
Now you should duplicate your other diskettes, repeating the
procedures here for formatting and copying diskettes. Then, if
you are going to use a hard disk, host communications, or a
printer, you may continue with the following procedures. Or,
after making copies of your other diskettes, you may want to skip
to Section 6, to do the exercises and learn more of the CP/M-86
commands.
4170 INSTRUCTION
Rev, Mar 1984
5-17
SECTION 5
GETTING STARTED
USING THE HARD DISK
If you have the optional hard disk (Option 4170F03), read the
procedures here to get started using the hard disk. There are
two hard disk procedures given here: formatting the hard disk and
setting up the hard disk as the default/boot disk.
You have the option of setting up the hard disk as the
default/boot disk. (The default disk is the disk the
operating system defaults to after ~ooting; the boot disk
is the disk that the system automatically boots from when the
4170 is powered up.) If you have a hard disk and you configure
the system as the default/boot disk, the system will boot from
the hard disk and nefault to it after booting. Even when the hard
disk is used as the boot drive, you must still have a formatted
diskette in drive A: before the system will boot. (You do not
have to use the operating system diskette; any formatted diskette
will work.)
Formatting the Hard Disk
NOTE
Tektronix formats the hard disk before it is
shipped. You do not need to use this
procedure to format the disk before using it.
However, if you intend to configure the hard
disk as the default/boot drive and there are
files already on the hard disk, you may want
to format the disk first to delete those
files. (The file CPM.SYS must be the first
physical file on the hard disk, so the hard
disk must be empty before it can be made the
default/boot disk.) If you have not yet used
the hard disk, you may skip to the next step,
Setting Up the Hard Disk as the
Default/Boot Drive.
5-18
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
1. Insert the CP/M-86 operating system diskette in drive
Press CTRL-C to log in drive A:
A.
A> (CTRL-C)
A>
2. Enter the FORMAT command after the system prompt A>.
Specify drive C:, the hard disk, as the disk to be formatted:
A>FORMAT C:
The FORMAT utility is loaded into memory from the operating
system diskette, and this message appears on your terminal
screen:
Formatting drive C:
Winchester drive (512 bytes/sector) with interleave of 5.
Please enter the numbers of any tracks known to be bad.
More than one number may be entered on a line but they
must be separated by commas. Any spaces are ignored.
Consecutive tracks may be s~ecified by entering the
startins track, a dash ('-'), and the ending track (e.g.,
'14-18'). To end the list, press RETURN without
entering any characters. If you don't know of any bad
tracks, just press RETURN.
Enter bad tracks:
Occasionally certain parts of a hard disk are known to be
unreliable; these are called "bad tracks." If your disk has
bad tracks, it does not mean that the disk is unusable, but
that small parts of it cannot reliably record information.
When you format the disk, the system identifies up to 160 bad
tracks and formats alternate tracks. Even when FORMAT detects
bad tracks, you still have the full 8 megabytes of hard disk
storage that CP/M-86 supports.
4170 INSTRUCTION
Rev, Mar 1984
5-19
SECTION 5
GETTING STARTED
When you installed the hard disk option in your 4170, there
should have been a sheet of paper tlike the one shown in
Figure 5-7) in the box with your disk drive. This sheet
contains information from the disk drive manufacturer about
bad tracks on your disk. To figure out the bad track numbers
from the information on this sheet, use this formula:
(4
*
Cylinder#) + Head#
= Badtrack#
Using Figure 5-7 as an example, 79 is the only bad track for
that disk (the Cylinder# is 19 and the Head# is 3). Thus, you
would specify:
Enter bad tracks: 79
If there was more than one bad track, separate the tracks with
commas, like this:
Enter bad tracks: 79,87 when you
see the prompt for bad track numbers. FORMAT can detect bad
tracks on its own. (Because the manufacturer's testing is so
extensive, it is preferable to specify known bad tracks if you
have the manufacturer's list; if you have the manufacturer's
list, you should use it.) If FORMAT detects more than 160 bad
tracks, it reports an error; if this occurs, contact your
Tektronix field office.
When FORMAT finds bad tracks, the 4170 displays this message:
Formatting alternate tracks.
FORMAT identifies the bad tracks and formats alternate tracks
(which are otherwise unused). Thus, you still have the full
amount of storage on the disk available.
5-20
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
o
o
o
o
o
o
o
o
o
o
o
o
G
MODEL NO. : 412
SERIAL NO. : 528775
TEST
PASSED DRIVE
SYS : 19 1 822
RESULT
SELECTS AVAILABLE 1,2,3,4
START TIME
12V NOM
4 SEC
12V LOW
7 SEC
12V HIGH
4.3 SEC
STOP TIME
9.4 SEC
3 MS STEP TEST
PASS
12V NOM
PASS
12V LOW
12V HIGH
PASS
OUTS IDE WINDOW MARGIN
LATE EDGE
34 NS
EARLY EDGE
34 NS
TOTAL
68 NS
LONG TERM RIW ERRORS
SOFT
o
HARD
o
CYLINDER #
TEST Deu : 45
DATE
11 271 84
TEST
RESULT
TRK ZERO
PASS
R.P.M. SPEED
12V NOM
359:3.5 RPM
12V LOW
3597.4 RPM
359:3.8 RPM
12V HIGH
ST. TIME REV. V.
5.7 SEC
20.8 MS
SK. COMPo TIME
HEAD SETTLE
PASS
r.S.V.
PASS
FULL CYL.
PASS
INSIDE WINDOW MARGIN :
LATE EDGE
26 NS
EARLY EDGE
24 NS
TOTAL
50 NS
-®V
ST 412
fi:D ERROR MAP
CYL ~ :;:;I:.C BY, E
1'>'
10
155
SIN 528775
BYTI:::::;I INDEX
3337
HEAD#--------~---~
4685-135
o
o
o
o
o
o
o
o
o
o
o
0
Figure 5-7. Calculating Bad Tracks from the Manufacturer's
Test Report.
4170 INSTRUCTION
Rev, Mar 1984
5-21
SECTION 5
GETTING STARTED
FORMAT asks you to confirm the FORMAT operation before it begins:
Format the disk? (Y or N; default N): Y
Are you SURE? (Y or N; default N): Y
This will take about 5 minutes
Formatting Winchester
Checking for bad tracks
Writing loader
Format complete.
After the hard disk is formatted, if you are going to configure
it as the default/boot drive, complete the following procedure.
Setting Up the Hard Disk as the Default/Boot Drive
To set up the hard disk as the default/boot drive, you must:
o
Copy the file CPM.SYS as the first physical file on the hard
disk.
o
Configure the system (using SETDEV) so that the hard disk is
the default/boot drive.
Copying CPM.SYS to the Hard Disk. To do this, you will
use the Peripheral Interchange Program (PIP) to copy the file
from the CP/M-86 operating system diskette to User 15 on the hard
disk. Enter the command:
PIP C:[G15]=A:CPM.SYS[ROVG15]
This copies CPM.SYS as the first physical file on the hard disk.
5-22
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
Making the Hard Disk the Default/Boot Drive. Next, you
use the SETDEV utility to set up the hard disk as the
default/boot disk. Enter this command:
A)SETDEV bootdrive=C:, defaultdrive=C:(CR)
The 4170 now boots from the hard disk, and after booting the
system defaults to the hard disk drive (C:). To verify this,
press RESET on the 4170 (located on the 4170's control panel,
beneath the pop-off door).
NOTE
Make sure that there is a formatted disk in
drive A.
The terminal screen should display a message like this:
Tektronix 4170 CP/M-86 V1.1 Release 1.2
C)
4170 INSTRUCTION
Rev, Mar 1984
5-23
SECfION 5
GETTING STARTED
CONNECTING THE 4170 TO A HOST
This discussion covers how to connect your 4170 to a host
computer and how to establish communications between the host and
the 4170 using the MODEM86 program. Tektronix provides several
preconfigured versions of the MODEM86 program; this section
introduces you to those versions and discusses which version you
should use. The MODEM86 program is described in more detail in
Section 7, Programming Information.
The discussion here of host/4170 communications includes:
o
o
o
Connecting to a host computer.
Getting started with the MODEM86 program.
Transferring files between a host and the 4170.
Connecting to a Host Computer
Figure 5-8 shows the 4170 in a typical configuration with a host.
As the figure illustrates, the 4170 is often connected to the
host via a telephone modem, which is, in turn, usually connected
to the 4170's HOST port. If you want to connect the 4170 to more
than one host, you can use anyone of the 3PPI (Three-Port
Peripheral Interface) ports in addition to the HOST port. Figure
5-9 shows the locations of the HOST port, the standard 3PPI
ports, and the optional 3PPI ports. (The optional 3PPI ports are
available as Option 4170F10.)
If your 4170 is not already connected to the host, connect the
cable (from the host or modem) to the HOST port or to a 3PPI
port; be sure to secure the cable with two screws.
To transfer files between two 4170s, you may need a special cable
connector, depending on which ports you intend to use. A standard
RS-232-C cable is required to connect the HOST port on one 4170
to a 3PPI port on the other. If you intend to use a 3PPI port on
each unit, or the HOST port on each unit, a "null modem" cable
with the following pin connections is required:
Connector
A Pins
1
2
3
4
Connector
B Pins
<------>
<------>
<------>
<------>
Connector
A Pins
1
3
2
5
5
6
7
11
Connector
B Pins
<------>
<------>
<------>
<------>
4
20
7
11
Connector
A Pins
Connector
B Pins
12 <------> 12
19 <------> 19
20 <------> 6
To connect two 3PPI ports, Tektronix cable 012-0689-01 provides
these pin connections on a cable with two male ends.
5-24
Rev, Apr 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
PRINTER
TERMINAL
,-I
I
I
I
I
,-
-- -
I
--~
I
I
I
I
9i!
MODEM
MOOEM
ADDITIONAL
HOST
COMPUTER
HOST
COMPUTER
1~I_---'11------"1
I
G
EJ~I
4685-137
Figure 5-8. Typical 4170 System Configuration.
4170 INSTRUCTION
Rev, Mar 1984
5-25
SECTION 5
GETTING S~ARTED
"
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TERjlAlNAL
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STANDAR 0
3PPI
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OPTIONAL
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HOST
CONNECTOR
OPTION 09 PORT
( PARALLEL INTERFACE)
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4685·139
F11ure 5-9. 4170 Port Locations.
5-26
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
Getting Started with the MODEM86 Program
Use the procedures here to run the MODEM86 program on your
system and to establish communications between the host and the
4170. To follow these instructions, you'll need the MODEM86
and CP/M-86 operating system diskettes.
.
1. Turn on the 4170 and terminal. Load the operating system.
2. Insert the MODEM86 diskette in drive B, and close the drive
door latch.
3. Enter the directory command to view what's on the MODEM86
diskette in dri~e B:
A>DIR B:(CR>
Figure 5-10 shows a directory of the MODEM86 diskette.
Tektronix provides several configurations of MODEM86, the
program for communicating between a 4170 and a host. The
different configurations are MODM86-H.CMD, MODM86-1.CMD,
MODM86-2.CMD, MODM86-3.CMD, MODM86-4.CMD, and MODM86-5.CMD.
(Other files on the disk are described in Section 7.)
4. Change the default drive to drive B:
A>B:(CR>
When the system prompt B> appears, type a CTRL-C to log
in drive B.
A)dir b:
B:
B:
B:
B:
B:
B:
B:
B:
COM2CMD
EXPAND
REMOVECC
UNSQZ
CMD2COM
MODEM86
REMOVECC
README
COM
CMD
CMD
CMD
CMD
SET
COM
1ST
MODEM86
MODM86-3
SHRINK
MODM86-4
MODEM SET
EXPAND
MODErm6
SYSTEM FILE(S) EXIST
A) ,
COM
CMD
CMD
CMD
CMD
COM
CMD
COM2CMD
MODEM SET
SIOBIOS
MODM86-H
MODM86-5
UNSQZ
MODM86-1
CMD
COM
A86
CMD
CMD
COM
CMD
DISTMDM
PHONES
SIOBIOS
CMD2COM
BIN2HEX
SHRINK
MODM86-2
SUB
DAT
MAC
COM
COM
COM
CMD
4685-143
Figure 5-10. Directory of the MODEM86 Diskette.
4170 INSTRUCTION
Rev, Mar 1984
5-27
SECTION 5
GETTING STARTED
5. You are now ready to use one of the MODEM86 programs. The
program you will use depends on the 4170 port to which your
host is connected. For example, if the host is connected to
the HOST port on the 4170, you will use the program MODM86-H.
Refer to the list below to determine which MODEM86 program you
will use.
Program
Port
HOST
Port
Port
Port
Port
Port
Port
1
2
3
4
5
MODM86-H
MODM86-1
MODM86-2
MODM86-3
MODM86-4
MODM86-5
6. Enter the program name after the system prompt. If your host
is connected to the host port, for example, enter:
B>MODM86-H
(Note that you must type MODM86-H, not MODEM86-H.)
The program displays the MODEM86 main menu (Figure 5-11).
(Section 7 describes the menu functions in more detail.)
8 >r~odm86-h
MODEM86 as of 03/29/84
(C) Cop!::!r i 3h t. 1 982-1984
T
E
R
L
~lark
-
Herse!::!
Tet'minal mode in full-duplex
Tet'minal mode lJ!i th echo
Receive a file
List file director!::! entries
:x: - T033le expert mode (menu on/off)
? - Help, comrtland s!::!ntax description
[) - Disconnec t (han3 IIp phone)
H - Tet'minal mode in half-duplex
S F M(J Q -
Send ·3 fi Ie
Displ.3!::! file data
Menu
Current values displa\:.l
Qui t, exi t to operahn3 :.\:.Istem
Default drive: 8
Entet' cOf'iIft'land:
4685-144A
Figure 5-11. MODEM86 Main Menu.
5-28
Rev, Apr 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
7.
View the communications parameters that the MODEM86 program
has set, and verify that they are acceptable for your
particular host. To view the parameters, enter a V
(Current Values Display) after the prompt, like this:
Enter command: V
The MODEM86 program displays the current values of the
communications parameters it expects. For example, if you are
using MODM86-H, you see this message:
Communication port #: 1
Baud rate: 1200
Parity: None
Stop bits: 1
Host handshaking signals: On
Conversation save file: None
Press any key to continue:
Notice that "1" is the communication port number for the
MODM86-H program. This is the MODEMSET communication port
number (and not the number of a 4170 3PPI port); MODEMSET
communication port 1 corresponds to the 4170's HOST port.
(See Section 7 for a cross-reference of MODEMSET numbers and
4170 physical ports.)
Next, determine if the baud rate of 1200 is what your host
expects. For example, if the host transmits at a rate of
4800, then you must change the baud rate from 1200 to 4800.
The next step instructs you how to do this. If you want to
change other program defaults (such as parity or stopbits),
you can do so using the MODEMSET program supplied on the
MODEM86 diskette; see Changing Preconfigured MODEM86
Programs in Section 7. In most cases, changing the baud
rate is sufficient to establish communications.
Press any key to redisplay the MODEM86 main menu.
4170 INSTRUCTION
Rev, Apr 1984
5-29
SECTION 5
GETTING STARTED
8.
To change the baud rate, enter T after the prompt on the
MODEM86 main menu:
Enter command: T
The MODEM86 program responds with:
Conversation save file: None
Terminal Mode Control Characters:
B)Break D)Disconnect E)Exit L)Literal R)Rate T)Transfer
The first line of this message reports that there was no
conversation save file specified when you gave the T
command. (Conversation save files are discussed under the
heading Transferring Files from the Host to the 4170,
later in this section.) The last two lines of the message
summarize the functions of the control characters that you can
enter.
To change the baud rate, press CTRL-R (hold down the CTRL key
and press the R key). The CTRL-R (the control character for
Rate) does not print, but this prompt appears:
Enter new baud rate:
Enter the baud rate that your host expects for communications
between it and the 4170. A baud rate of 4800 bits/second or
less is recommended for literal data transfers. (Higher rates
could possibly result in lost data during literal transfers.
Rates of up to 19200 baud, however, may be used when
transferring files with the Sand R menu options because
these options use the Ward Christiansen error-checking
protocol; see Section 7 for more information.)
If you have a phone modem, dial up a telephone line and
connect to the host. The terminal now acts as if it is
directly connected to the host.
Enter a CTRL-E to return to the MODEM86 main menu. If you
enter Q from the MODEM86 main menu (to quit and exit to the
CP/M-86 operating system), you can use CP/M-86 without
disconnecting from the host. To return to using the host,
simply reenter the program name (for example, MODM86-H) and
change the baud rate again, if necessary. Thus, you can
bounce back and forth between using the host and using the
4170 and CP/M-86.
5-30
Rev, Apr 1984
4170 INSTRUCTION
SECTION 5
Getting Started
Transferring Files Between the Host and 4170
When the MODEM86 main menu (Figure 5-11) is visible, you can
transfer files between the host and the 4170. To transfer files,
you use the T (Terminal Mode) menu function.
The following
discussion covers:
o
How to transfer a file from the host to the 4170.
o
How to transfer a file to the host from the 4170.
It is recommended that you select small files when you
experiment with the MODEM86 examples here. This will allow you to
run through the steps quickly to speed up your understanding of
how to get started using MODEM86.
See Section 7, Programming Information, for additional
details on transferring files with MODEM86.
Transferring Files from the Host.
To transfer a file
from the host to the 4170, it is recommended that you have room
on the diskette that is the file's destination. Because the
MODEM86 diskette is full, the following procedure first instructs
you to copy the MODEM86 program you'll need to the operating
system diskette; make sure that there is space on the operating
system diskette for the copy. (After you've used MODEM86 for a
while, you'll realize that the program allows you to insert a
different diskette when a transferred file is too long to fit on
the first diskette.)
1. Insert the operating system disk in drive A and the MODEM86
diskette in drive B. Log in both drives (make the drive active
and enter a CTRL-C). Make sure the write-protect switches on
the drives are off; otherwise, you may get a BDOS error later.
2. Copy the appropriate MODEM86 program for your system to the
operating system diskette. If your host is connected to the
host port, for example, then copy the MODM86-H.CMD program; in
this case, enter:
A)PIP A:=B:modm86-h.cmd[OV]
Remove the MODEM86 diskette and put it away.
4170 INSTRUCTION
Rev, Mar 1984
5-31
SECTION 5
GETTING STARTED
3. Establish communications with the host. To do this, type the
name of the appropriate MODEM86 program. For example:
A>MODM86-H
The MODEM86 main menu appears (refer back to Figure 5-11).
From that menu, select T (Terminal Mode), and if
necessary, do a CTRL-R to set the baud rate. Dial a phone line
or otherwise connect to the host. When you have established
host communications, type a CTRL-E to exit back to the MODEM86
main menu.
4. Select the T (Terminal Mode) function again, only this
time, specify a conversation save file. For example:
Enter command: T save.txt
A conversation save file (save.txt, in this example) saves
your dialog between the host and the terminal; it provides a
medium in which you can save whatever the host transmits to
the terminal
including host commands as well as transferred
files.
After you press the carriage return, this message appears:
Conversation save file: A:SAVE.TXT
start saving conversation (yiN) [YJ?
(The terminal displays a BDOS error instead of this prompt if
the drive is write-protected. Unprotect the drive and press
to get the prompt.)
5. Enter N because you do not yet want to begin saving
conversation in the file save.txt. This list of control
characters appears:
Terminal Mode Control Characters:
B)Break D)Disoonneot E)Exit L)Literal P)Purge R)Rate
T)Transfer Y)Yank
When you are ready to turn on the conversation-save feature to
capture the file from the host, you will enter a CTRL-Y
(Yank); CTRL-Y acts as a toggle to turn conversation saving
off and on. At this point, what you type on the terminal is
sent to the host but not saved.
5-32
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
6. Enter the host command that begins transmitting text, but
before you press the carriage return key, enter a CTRL-Y.
After the CTRL-Y, press
The CTRL-Y toggles the conversation save feature on, so that
when the host begins transmitting, the MODEM86 program saves
the data in a file save.txt. (When the conversation save
feature is on, a colon (:) appears on the left side of your
screen. The colon is not saved as part of the file.) As soon
as you press , the host starts transmitting the file to
the 4170; you should see it scroll across your terminal
screen.
When the transfer is complete, if your system has a host
prompt, it reappears. (The prompt, unfortunately, is also
saved in the file, because the conversation-save feature is
still on. You may use ED, the CP/M-86 line editor, or another
text editor to delete the prompt from the file, if necessary.)
7. Press CTRL-Y to turn off conversation save and CTRL-E to exit
Terminal Mode. The MODEM86 main menu appears, preceded by this
message:
++Remember to write or purge conversation eave file.++
At this point, the conversation save file has been saved in a
buffer, but it has not been written to a diskette. The prompt
reminds you to write the file (W from the MODEM86 main
menu) or to purge or delete it from the buffer (p from
the main menu) .
4170 INSTRUCTION
Rev, Mar 1984
5-33
SECTION 5
Getting Started
8. Enter the appropriate command after the prompt to write or to
purge the conversation save file. For example, entering W
writes the file save.txt to the default drive (drive A in this
example) :
Default drive: A
Enter command: W (CR>
When the file is written to the diskette in drive A, the
MODEM86 main menu appears and indicates that the file was
written correctly.
9. Enter L (List file directory entries) to check that the
file transfer was successful:
Enter command: L(CR>
You should see that the file save.txt now exists on the
diskette in drive A. To view the contents of that file, ~uit
MODEM86 (Q from the MODEM86 main menu) and enter this CP/M-86
command:
A>type save.txt(CR>
If MODEM86 does not work properly, refer to the heading If You
Have Problems with MODEM86 in Section 7.
Transferring Files from the 4170. To transfer files
from the 4170 to the host, ybu must know how to open a file on
your particular host. This usually involves using some kind of
text ~ditor to create a new file in which data can be captUred.
As an example, this discussion uses a text editor called TECO,
but how you open a file depends on your particular host.
This example uses the operating system diskette and the MODM86-H
program (in drive A) as in the previous example.
5-34
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
1. Establish communications with the host. As before, enter the
program name to get the MODEM86 main menu:
. A>modm86-h
Then enter T after the prompt:
Enter command: T
This list of control characters is displayed:
Terminal Mode Control Characters:
B)Break D)Disconnect E)Exit L)Literal R)Rate T)Tranafer
Change the baud rate, if required, with CTRL-R, and dial a
phone line, if required.
2. Open a file on the host that will capture what is transmitted
by the 4170 and MODEM86. What you enter depends on your
particular host; consult your system manual or system
programmer for assistance.
Here is an example for a particular host system. The following
commands (after the host prompt @) invoke a text editor
called TECO. After the TECO prompt *, the commands open a
file called "from4170.txt" in which the transmitted data will be
inserted:
Or teco(CR>
*ew from4170.txt$$
*i
3. After you have opened a file on your host (using whatever
particulars your host requires), press CTRL-T. This is the
control character for a Transfer (refer back to the list of
control characters under Step 1).
The MODEM86 program prompts you for a filename:
Enter file name to be transferred - CR to quit:
4170 INSTRUCTION
Rev, Mar 1984
5-35
SECTION 5
GETTING STARTED
4. Type in the name of the file you want to transfer from the
4170. For example, to transfer the file "intro.doc" from the
operating system diskette in drive A:
Enter file name to be transferred - OR to quit: intro.doc
You can specify a drive (such as B:) before the filename;
otherwise, the default drive is assumed.
If the MODEM86 program finds the file on the specified drive,
it responds with a message like this:
A:INTRO.DOO open, size: 25 (00000019H) sectors
Minimum duration of transfer: 0 minutes and 3 seconds
Should LFls be sent (yiN) [N]?
The MODEM86 program does some internal calculations, using
the current baud rate and the size of the file (in sectors),
to estimate how long the file transfer will take.
If the file does not exist on the specified drive (or if you
made an error in typing the filename), you'll see a message
like this instead:
Can't open filename.ext ++ File does not exist ++ Enter file
name to be transferred - OR to quit:
You can then reenter the filename or specify a different file.
5-36
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
5. Enter N after the prompt for sending linefeed characters
(LF's):
Should LF's be sent (yiN) [N]? N
(Answering Y attaches an extra linefeed character to every
carriage return-linefeed sequence. Usually you will want to
answer N.)
NOTE
No carriage return is required; the transfer
begins immediately after you respond to the
prompt for sending LF's.
This message concludes the transfer:
++ File transfer completed ++
6. Close the file on the host that was previously opened for the
transferred data. Again, this depends on your particular host
system.
Using the earlier example of a host file opened with TECO,
these commands close the file "from4170.txt":
$$
*ex$$
@
After the host prompt appears (@ in the example), you may
want to do a directory to verify that the file "from4170.txt"
exists on the host.
This completes the examples of getting started with host
communications. Section 7, Programming Information, discusses
the causes of some typical problems that you may encounter. See
that section for more information about using MODEM86.
4170 INSTRUCTION
Rev, Mar 1984
5-37
SECTION 5
GETTING STARTED
CONNECTING A PRINTER
If you have a printer, this section instructs you how to connect
the printer, how to configure the 4170, and how to use the
printer.
This section talks specifically about a printer, but the
procedure is similar for most peripherals. Generally, to connect
a peripheral, you must:
o
Attach the peripheral to one of the 3PPI ports or to the
Option 09 port.
o
Assign the peripheral to a logical device (using SETDEV).
o
Configure the communications for that logical device (using
SETDEV) to match the peripheral's requirements.
Finally, to use the peripheral, you can specify the logical
device in several r,P7M-86 commands (PIP, TYPE, etc.). As
discussed in the following, you may also use CTRL-P to toggle
output to the logical device LST:.
Conneoting a Printer
If your printer uses an RS-232 interface, connect the printer
cable to one of the 3PPI ports (see Figure 5-12). If your printer
uses a Centronics-style parallel interface, you must have Option
09 for the 4170; in this case, connect the printer cable to the
Option 09 port (Figure 5-12).
5-38
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
--
r....
/
~
/
IJ
'\
V
"
TERMINA L
PORT
(PORT 0)
PORT l'
PORT2
V
ttl
~:
I~
II
II
~e
10
10
DIR
The DIR command and the directory appear on the terminal and are
output to the printer. After the directory of the operating
system diskette has printed, enter another CTR1-P to turn off
printing.
5-40
Rev, Mar 1984
4170 INSTRUCTION
SECTION 5
GETTING STARTED
The CTRL-P can also be used in conjunction with the CP/M-86
command TYPE. Try entering this command, but before you press the
RETURN key, enter a CTRL-P:
A)TYPE intro.doc
(OTRL-P)
.
The character means that
you should press the RETURN key.
1. Enter the following command:
STAT USR:
When CONFIG is invoked without a filespec, it goes through a
complete session of prompting for input from the user via the
terminal. Figure 7-1 shows the prompts. (Responding to the
CONFIG prompts can be rather time-consuming, especially if you
want to reconfigure only one device. Use the SETDEV utility, also
supplied by Tektronix, instead.)
In this example, CONFIG begins execution and uses the values in
the file FACTORY.TXT (when you specify a filename, the left angle
bracket «) must precede the filename):
CONFIG
Because there is no prompting when you specify a file with
CONFIG, it executes rapidly.
The responses to the prompts in Figure 7-1 are the same as the
values in the file FACTORY.TXT; thus, responding to the prompts
as in Figure 7-1 has the same effect as specifying CONFIG with
FACTORY. TXT.
7-10
Rev, Mar 1984
·4170 INSTRUCTION
SECTION 7
Programming Information
Here is a summary of the default values contained in FACTORY.TXT:
CON: - Port 0 (Terminal Port)
LST: - Port 1
AUX: - Port 2
All ports are set as follows:
Baud Rate(Transmit and Receive) - 2400
DC1/DC3(CTRL-S/CTRL-Q) Flagging - No
RTS/CTS (Request to Send/Clear to Send) Flagging - No
DTR (Data Terminal Ready) Flagging - No
ETX/ACK (End of Text/Acknowledge) Flagging - No
Data bits - 8
Stop bits - 1
Parity - Odd (Transmitted from 4170) and Disabled (Received
by the 4170)
Boot Drive - A
Default Drive - A
When FACTORY.TXT is used with CONFIG, flagging for the terminal
(the logical device CON:) is set to none. You may specify only
one kind of flagging at a time with CONFIG. ETX/ACK flagging is a
no-op.
NOTE
If you use CONFIG to change the flagging for
the terminal, do not select DC1/DC3 flagging
if you are going to use applications programs
(such as Wordstar, SuperCalc, or Emacs) that
use CTRL-S or CTRL-Q; these programs will not
work properly if DC1/DC3 flagging is enabled.
NOTE
Although the CONFIG menu does not list it as
a valid selection for the baud rate, you may
specify "19" to CONFIG's request for a baud
rate and thus select 38400 baud.
You can edit the file FACTORY. TXT to create a file for your
specific configuration requirements. If you edit FACTORY. TXT to
supply your own configuration parameters, first copy the file and
rename it. Be sure that you edit the file carefully and that you
specify the exact number of characters that CONFIG expects;
otherwise CONFIG will not work and you may lose communications
between the terminal and the 4170.
4170 INSTRUCTION
Rev, Mar 1984
7-11
SECTION 7
Programming Information
Error Messages
If CONFIG prompts for input and it expects a response of Y or N,
it checks the character entered and requests reentry if any other
character is entered. When CONFIG expects numeric responses, it
does not check the values entered; therefore, you must enter
numeric values carefully. If you specify a filename to CONFIG and
the file contains extraneous or incorrect parameters, the system
will not work properly; if this occurs, use the procedure
described in Section 5 to restore communications between the
terminal and the 4170.
7-12
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
A)config
Tektronix cp/M-86 System Configuration Utility
Version 1.0
Enter the Physical Port assigned to the Console.
Terminal Port
1 - Port 1
2 - Port 2
3 - Port 3
4 - Port 4
5 - Port 5
6 - Host
7 - Printer Port
Enter the physical port number. (0-7) ? 0
o-
Baud Rate:
No baud rate for this device
1 - 50 Baud
2 - 62.5 Baud
3 - 75 Baud
4 - 110 Baud
5 - 134.5 Baud
6 - 150 Baud
7 - 200 Baud
8 - 300 Baud
9 - 600 Baud
10 - 1200 Baud
11 - 1800 Baud
12 - 2000 Baud
13 - 2400 Baud
14 - 3600 Baud
1 5 - 4800 Baud
16 - 7200 Baud
17 - 9600 Baud
18 - 19.2K Baud
Enter the baud rate number. (0-18) ? 13
o-
Flagging:
Do you want
Do you want
Do you want
Do you want
DC1/DC3 (control-S/control-Q) fla~ging. (yiN) ? n
RTS/cTS (hardware) flagging. (YIN) ? n
DTR (Data Terminal Ready) flagging. (yiN) ? n
ETX/ACK flagging. (yiN) ? n
Number of Data Bits per character:
o - 5 Data Bits
1 - 6 Data Bits
2 - 7 Data Bits
3 - 8 Data Bits
Enter the number of data bits per character. (0-3) ? 3
Number of Stop Bits per character:
1 stop Bit
1 - 2 Stop Bits
Enter the number of stop bits per character. (0-1) ? 0
o-
Parity:
Odd Parity
1 - Even Parity
Enter the number for data parity. (0-1) ? 0
o-
Do you want parity enabled. (yiN) ? n
(continued)
4685-141
Figure 7-1. CONFIG with the Same Values as Factory.Txt.
4170 INSTRUCTION
Rev, Mar 1984
7-13
SECTION 7
Programming Information
Enter the Physical Port assigned to the List Device.
Terminal Port
1 - Port 1
2 - Port 2
3 - Port 3
4 - Port 4
5 - Port 5
6 - Host
7 - Printer Port
Enter the physical port number. (0-7) ?
o -
Baud Rate:
o - No baud rate for this device
1 - 50 Baud
2 - 62.5 Baud
3 - 75 Baud
4 - 110 Baud
5 - 134.5 Baud
6 - 150 Baud
7 - 200 Baud
8 - 300 Baud
9 - 600 Baud
10 - 1 200 Baud
11 - 1800 Baud
12 - 2000 Baud
13 - 2400 Baud
14 - 3600 Baud
15 - 4800 Baud
16 - 7200 Baud
17 - 9600 Baud
18 - 1 9. 2K Baud
Enter the baud rate number. (0-18) ? 13
Flagging:
Do you want
Do you want
Do you want
Do you want
DC1/DC3 (control-S/control-Q) fla~ging. (yiN) ? n
RTS/cTS (hardware) flagging. (YIN) ? n
DTR (Data Terminal Ready) flagging. (yiN) ? n
ETX/ACK flagging. (yiN) ? n
Number of Data Bits per character:
5 Data Bits
1 - 6 Data Bits
2 - 7 Data Bits
3 - 8 Data Bits
Enter the number of data bits per character. (0-3) ? 3
o -
Number of Stop Bits per character:
o - 1 Stop Bit
1 - 2 Stop Bits
Enter the number of stop bits per character. (0-1) ? 0
Parity:
Odd Parity
1 - Even Parity
Enter the number for data parity. (0-1) ? 0
o-
Do you want parity enabled. (yiN) ? n
(continued)
4685-141
Figure 7-1. CONFIG (cont).
7-14
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Enter the Physical Port assigned to the Auxiliary Device.
o - Terminal Port
1 - Port 1
2 - Port 2
3 - Port 3
4 - Port 4
5 - Port 5
6 - Host
7 - Printer Port
Enter the physical port number. (0-7) ? 2
Baud Rate:
o - No baud rate for this device
1 - 50 Baud
2 - 62.5 Baud
3 - 75 Baud
4 - 110 Baud
5 - 134.5 Baud
6 - 150 Baud
7 - 200 Baud
8 - 300 Baud
9 - 600 Baud
1 0 - 1 200 Baud
11 - 1 800 Baud
12 - 2000 Baud
13 - 2400 Baud
14 - 3600 Baud
15 - 4800 Baud
16 - 7200 Baud
1 7 - 9600 Baud
18 - 1 9. 2K Baud
Enter the baud rate number. (0-18) ? 13
Flagging:
Do you want
Do you want
Do you want
Do you want
DC1/DC3 (control-S/control-Q) flagging. (yiN) ? n
RTS/cTS (hardware) flagging. (yiN) ? n
DTR (Data Terminal Ready) flagging. (yiN) ? n
ETX/ACK flagging. (yiN) ? n
Number of Data Bits per character:
5 Data Bits
1 - 6 Data Bits
2 - 7 Data Bits
3 - 8 Data Bits
Enter the number of data bits per character. (0-3) ? 3
o-
Number of Stop Bits per character:
1 Stop Bit
1 - 2 stop Bits
Enter the number of stop bits per character. (0-1) ? 0
o -
Parity:
Odd Parity
1 - Even Parity
Enter the number for data parity. (0-1) ? 0
o-
Do you want parity enabled. (yiN) ? n
Enter the Boot Drive. (A-P) ? a
Enter the Default Drive. (A-P) ? a
Setting System Configuration.
Is that what you want to do (yiN) ? Y
Configuration Started.
Tektrunix 4170 cp/M-86 V1.2
Release 1.2
A)
4685-141
Figure 7-1. CONFIG (cont).
4170 INSTRUCTION
Rev, Mar 1984
7-15
SECTION 7
Programming Information
DEL
(Delete)
The DEL utility, like the standard CP/M-86 ERA command, erases
files. Unlike ERA, however, DEL can be made to ask your
permission before deleting each file in a list. DEL always
requires confirmation of blanket file deletion requests (using
the ambiguous filespec * * or ?????????). DEL is distributed in
the file DEL.CMD.
I DEL {filespec{[GnnQ]}, ... }
filespec
is either a literal name or an ambiguous file name
(constructed with the wildcards "*" or II?"). You
may include a drive specifier; the default drive
is the current drive.
[GnnQ]
is an optional modifier. Gnn specifies the user number
from which the file or files are to be deleted (the
default is the current user number). Q(Query)
tells DEL to ask before deleting each file.
NOTE
If you invoke DEL without arguments, it
displays a brief message describing its
syntax and returns control to the operating
system.
When you use the Query option (Q), DEL finds each file that
matches the filespec, displays its name, and asks you with a
question mark whether it should be deleted. DEL recognizes these
responses:
y
Yes, delete the file and continue.
n
No, keep the file and continue.
g
Go ahead and delete this file or all files matching
the filespec without asking.
CTRL-C
Stop and return control to the operating system.
7-16
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
NOTE
If you press any key during file deletion,
DEL automatically goes into query mode. DEL
remains in query mode until the operation is
done or you press the "g" (go) key.
Even without the Query option, DEL asks before deleting Read-Only
files and requests confirmation before obeying commands to delete
all files (filespecs such as *.* and ?????????).
Examples
The sequence shown below deletes all but one of the files with
the filetype ".bak" under user number zero:
A)del *.bak[gOq]
Deleting files:
A: CATALOG. BAK[GO]?y
A:TEACH.BAK[GO]?y
A:COMMANDS.BAK[GO]?n
A)
4170 INSTRUCTION
Rev, Mar 1984
7-17
SECTION 7
Programming Information
Error Messages
Illegal file name given.
The command included an incorrect filespec or option.
filespec and command syntax.
Check the
**Ineufficient memory to continue.
Not enough memory is available to the operation system to store
the filespecs during processing. If adequate memory is available
and the problem persists, reload the operating system.
Filename does not exist.
The file specified in the command does not exist. This message
is issued only if you have included an unambiguous but incorrect
file name in the command; it is never issued in response to a
command to delete an ambiguous filespec.
y/Y
yes
no
go (and stop asking for confirmation)
giG
CTRL C abort
n/N
DEL prints this message in response to an invalid confirmation.
Note that "G" only prevents requests for confirmation for the
filespec being processed; if a subsequent filespec on the command
line is followed by the "Q" option, requests for confirmation
resume.
7-18
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
FORMAT
(Format a Disk)
Before you can use either a hard disk or a flexible diskette for
the first time, you must format it. To do so, use the FORMAT
utility. This utility erases any data present on the disk being
formatted, and writes track and sector information on the disk
surface for the operating system to use. When FORMAT is followed
by a device name, prompts explain how you should continue.
FORMAT is distributed in the file FORMAT.CMD.
FORMAT ldevice:}
device:
is the drive (A: through P:) containing the disk you
want to format.
Drives A: and B: are the flexible
disk drives; the optional hard disk is drive C:.
(External disk drives -- such as a Tektronix 4926,
4925, or 4926 Option 25 -- use device names E:
through P:. The exact device name is determined by
strap settings at installation.)
NOTE
If you invoke FORMAT without a device name,
it displays a brief message descri"bing its
function and returns control to the operating
system. FORMAT issued with the device name Q:
causes a ~uick-reference syntax message to be
displayed.
CAUTION
Formatting a disk destroys any data on
the disk. Be sure that the disk does not
contain valuable data before you format it.
Formatting Flexible Diskettes
Before you format a diskette in drive A or B, be sure that the
diskette in the drive does not contain data you want to save.
Type one of these commands:
FORMAT A:
FORMAT B:
(to format the disk in drive A)
(to format the disk in drive B)
FORMAT asks you to confirm that you do indeed want to format the
diskette and thus destroy any data on it.
If you confirm that it
should go ahead, FORMAT erases and formats the diskette.
4170 INSTRUCTION
Rev, Mar 1984
7-19
SECTION 7
Programming Information
Formatting a Hard Disk
As with a £lexible disk, FORMAT erases any data on the hard disk
and writes the track and sector information that the operating
system requires on the disk surface.
In addition, when a hard disk is formatted, FORMAT detects "bad
tracks." (Hard disks usually contain a number of tracks that
cannot be reliably written to and read from.) FORMAT marks these
tracks, and then assigns alternate (normally unused) tracks so that
you have the full amount of storage available.
NOTE
The optional hard disk is formatted at the
factory and does not need to be reformatted
before you use it.
If you format the optional hard disk, FORMAT lets you input the
list of bad tracks supplied by the disk manufacturer. If you do
not have this list, or suspect that it is in error, FORMAT
proceeds and marks the tracks that it cannot verify. (Section 5
describes how to specify bad tracks from the manufacturer's
list.)
FORMAT can handle up to 160 bad tracks. If the disk contains
more than 160 bad tracks, FORMAT returns an error message. If
your hard disk contains more than 160 bad tracks, it should be
replaced; contact your local Tektronix field office.
Example
A>FORMAT B:(CR>
Formatting drive B:
5 1/4" Double-Sided Floppy (512 bytes/sector)
with interleave of 0
Insert a disk in drive B
Format the disk? (Y or N; default N): Y(CR>
Formatting (this takes approximately 30 seconds) ...
Formatting completed.
Insert a disk in drive B
Format the disk? (Y or N; default N): N(CR>
A>
See Section 5, Getting
a hard disk.
7-20
~tarted,
Rev, Mar 1984
for an example of formatting
4170 INSTRUCTION
SECTION 7
Programming Information
Error Messages
Error messages are standard CP/M-86 error messages and the
following:
Check that the disk and drive are not write-protected.
Remove the write-protect tab from the disk, or turn
off the drive's write-protect switch. If the disk was not
write-protected, formatting a second time may correct
the error.
If formatting a second time does not correct the error, the
diskette may be bad; try another diskette.
Only drives A: through P: are allowed.
The drive you specified is not in the valid range A: through P:.
Drive not present. Aborting.
The specified drive (A: through P:) is not connected.
Number of bad tracks exceeds 160
The hard disk contains more than 160 bad tracks and should be
replaced. Contact your local Tektronix field office.
If either of these two errors occurs, try formatting the hard
disk again:
Error - in requesting alternate track.
Error - in writing alternate track.
If the error recurs, there may be a problem with the disk or the
disk controller; contact your local Tektronix field office.
4170 INSTRUCTION
Rev, Mar 1984
7-21
SECTION 7
Programming Information
RUN
(Run .LTL Program)
RUN reads load-time-locatable programs (extension .LTL) from disk
files, loads them into memory, and begins executing them. RUN
loads ONLY the load-time-locatable object programs created by
LINK86 from the output of Intel language compilers such as ASM86
and FORTRAN-86. The names of such files have the extension
".LTL", meaning "load time locatable." RUN is contained in the
file RUN.CMD.
RUN progname
i arguments li & li ; comment 1
progname
is the name of the load-time-locatable program
file to be loaded and run.
The file specifier may
include a drive specifier and a user number of the
usual form ([Gnn]).
The file extension .LTL is
assumed.
arguments
is list of any arguments required by the program
to be loaded.
&
is an optional continuation character. The
ampersand (&) indicates that the command or
arguments continue on the next line after a
carriage return; this enables you to break long
command sequences into as many lines as necessary.
; comment
optional remarks which have no effect on program
loading or execution.
7-22
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Examples
To load and run the load-time-locatable~file FORTST.LTL
contained under user number 2 on drive B, type:
A)RUN B:FORTST[G2]sd lst:=.for[ag1]
The listing device displays a message like this:
Disk A:, User 01
prog1.for[4k]
"SD LST:=.FOR[AG1]"
V1.20
prog2.for[4k]
Total of 14k in , files with 2998k space remaining.
4170 INSTRUCTION
Rev, Mar 1984
7-25
SECTION 7
Programming Information
SETDEV
(Set Device)
SETDEV allows the user to check and selectively change the
logical-to-physical device assignments and to reconfigure device
parameters. Unlike CONFIG, which requires you to specify all
parameters for all devices, SETDEV allows you to specify as few
parameters as you want for a specific device. Also unlike CONFIG,
SETDEV allows you to view the current configuration settings.
SETDEV is distributed in the file SETDEV.CMD.
SETDEV has two syntax forms, which follow. Most SETDEV arguments
can be abbreviated to as few as one or two characters; in the
discussion of SETDEV here, the characters in bold UPPERCASE
show how you may abbreviate each argument.
SETDEV logdevj=physdev}, jparameter1=setting},
lparameter2=setting}, ... jSHow}
or
SETDEV lQuery}
logdev
is a logical device name. The valid logical
device names are Console, Auxiliary,
and List (or Lst). The logical device
name must precede any parameter specifications;
the only time it may be omitted is when SETDEV is
issued with only "show" or "query". A single
SETDEV command allows only one
logical-to-physical device assignment.
physdev
is a physical device port. The ports can be the
standard 3PPI ports (Ports 0-2), the optional
3PPI ports (Ports 3-5), the Host port, and the
Option 09 port. An error is reported if you
specify a port that does not exist on your 4170.
The valid port names are:
PORTO or PO
PORT1 or P1
PORT2 or P2
PORT3 or P3
PORT4 or P4
PORT5 or P5
Host
Option9 (or Opt9) , or Parallel
7-26
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
parameter
is a communications parameter or a drive
specification being changed. Table 7-1 lists the
parameters and shows how they may be abbreviated.
An e~uals sign (=) separates the parameter from
its setting; commas (and optionally, spaces)
separate one parameter specification from
another.
setting
is a valid value for the communications parameter
being changed. Table 7-1 lists valid settings for
each parameter, and shows how they may be
abbreviated.
SHow
displays a list of parameter settings for all
devices. If "show" is included with parameters to
be changed, SETDEV first shows how the parameters
will look once they are changed. "Show" can be
specified without specifying a logical device.
Query
causes SETDEV to prompt for parameter changes.
NOTE
If you invoke SETDEV with no arguments, it
displays a brief help message and returns
control to the operating system.
4170 INSTRUCTION
Rev, Mar 1984
7-27
SECTION 7
Programming Information
Table 7-1
PARAMETERS AND SETTINGS FOR SETDEV
: Parameter
Baud
: Valid Settings
50, 62.5, 75, 110, 134.5, 200,
300, 600, 1200, 1800, 2000,
2400, 3600, 4800, 7200, 9600,
1 9200, or 38400
---------------------------------------------------------: Parity
: Odd, Even, or None
: Databits
: 5, 6, 7, or 8
: Stopbits
: 1
: Flagging
I
I
: None, Xon, Dtr, or
: Rts/cts
: DEfaultdrive
: A:, B:,
... P:
i BOotdrive
: A:, B:,
... P:
or 2
NOTE
"Xon" flagging is DC1/DC3 flagging. If you
are going to use applications programs that
use CTRL-S or CTRL-Q (such as Wordstar,
SuperCalc, or Emacs), do not select Xon
flagging for communications between the 4170
and the logical device Console (the
terminal); these applications programs may
not work properly if Xon (DC1/DC3) flagging
is enabled.
Only one kind of flagging may be specified
with SETDEV at a time.
7-28
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Discussion
SETDEV allows you to selectively change communication parameters,
as opposed to CONFIG, which requires you to reenter all
parameters. SETDEV also lets you display the current parameters
with the optional argument "show".
When the second syntax form is used:
A>SETDEV query
SETDEV displays a menu and prompts you for changes. Figure 7-2
shows the menu that SETDEV query issues and illustrates how
to change device parameters by responding to the prompts. Note
that you can press to leave a parameter unchanged in
response to the prompting.
Examples
Suppose that you are adding a printer, that you are connecting it
to Port 1, and that you want it to be the logical device LST:.
After connecting the printer, use SETDEV to assign the printer to
the list device and to change the required communication
parameters (with the first syntax form, parameters not specified
retain their values). Note that the logical device must precede
any parameter specifications.
A)SETDEV lst=port1, ba=300, pa=none
After you press the (CR>, SETDEV responds with this message:
SETDEV CP/M-86 Device Configuration Utility V1.0
Setting new configuration ....
SETDEV can also be used to change the default drive (the drive
selected after the operating system is booted) and the boot
drive. To change the default drive, enter:
A>SETDEV def=C:
4170 INSTRUCTION
Rev, Mar 1984
7-29
SECTION 7
Programming Information
Valid boot and default device names are A: through P:. Device
names A: and B: refer to the flexible disk drives, while device
name C: refers to the optional hard disk drive. (The device name
D: is presently unused and is reserved for future use.) Device
names E: through P: refer to external devices, such as the
Tektronix 4926 Hard Disk Drive; the exact device name depends on
strap settings that are made during installation. SETDEV reports
an error if the device name specified is not in the valid range
A: through P:. If the device specified (from A: to P:) is not
connected, however, SETDEV does not report an error and uses
drive A: instead.
7-30
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
A>setdev query
SETDEV CP/M-86 Device Configuration Utility V1.0
SETDEV Query Mode.
Enter one of the following (may be abbreviated to a single letter):
SHOW to display the current configuration
CONSOLE, AUXILIARY, or LIST to change parameters for that device
DEFAULTDRIVE to change the drive selected after CP/M-86 is booted
BOOTDRIVE to change the drive used to load CP/M-86
KEEP to quit SETDEV and keep the changes
Press CTRL-C (ftC) to quit without saving any changes.
Enter choice and press RETURN -> aux
The AUXILIARY device is currently assigned to PORT2.
Choose:
PORTO, PORT1, PORT2, ... PORT5, HOST, or OPTION9
and press RETURN, or just press RETURN for PORT2 -> p3
The current baud rate for the AUXILIARY device is 4800.
Choose:
50, 62.5, 75, 110, 134.5, 150, 200, 300, 600, 1200, 1800, 2000,
2400, 3600, 4800, 7200, 9600, 19200, 38400
and press RETURN, or just press RETURN for 4800 -> 9600
The current parity for the AUXILIARY device is NONE.
Choose:
NONE, ODD, or EVEN
and press RETURN, or just press RETURN for NONE ->
The number of databits for the AUXILIARY device is 8.
Choose:
5, 6, 7, or 8
and press RETURN, or just press RETURN for 8 ->
The number of stopbits for the AUXILIARY device is 1.
Choose:
1 or 2
and press RETURN, or just press RETURN for
->
The flagging mode for the AUXILIARY device is XON/XOFF.
Choose:
NONE, XON/XOFF, RTS/CTS or DTR
and press RETURN, or Just press RETURN for XON/XOFF ->
Enter one of the following (may be abbreviated to a single letter):
SHOW to display the current configuration
CONSOLE, AUXILIARY, or LIST to change parameters for that device
DEFAULTDRIVE to change the drive selected after CP/M-86 is booted
BOOTDRIVE to change the drive used to load CP/M-86
KEEP to guit SETDEV and keep the changes
Press CTRL-C (ftC) to quit without saving any changes.
Enter choice and press RETURN -> keep
Setting new configuration ...
4685-133
Figure 7-2. An Example of SETDEV Query.
4170 INSTRUCTION
Rev, Mar 1984
7-31
SECTION 7
Programming Information
SETDEV specified only with "show" displays the current settings
for all devices (Figure 7-3 shows a typical display):
A>SETDEV show
In the next example, a parameter to be changed is specified along
with "show":
A>SETDEV 1st, ba=300, pa=none, show
SETDEV displays the new configuration, with the baud rate and
parity revised to the specified values.
C>
C>setdev show
SETDEV CP/M-86 Device Configuration Utility V1.0
Current CP/M-86 Device Configuration:
CONSOLE device is PORTO
baudrate ...• 2400
parity ...•.. NONE
databits .•.. 8
stopbi ts .... 1
flagging .•.. XON/XOFF
AUXILIARY device is PORT2
baudrate ..•. 2400
parity .•.... NONE
databits •.•. 8
stopbi ts ••.. 1
flagging ..•. XON/XOFF
LIST device is PORT1
baudrate .. ·.300
parity .•.•.. NONE
databi ts .... 8
stopbi ts .... 1
flagging .... XON/XOFF
Defaultdrive .... C:
Bootdrive •...... A:
C>
4685-145
Figure 7-3. SETDEV Show.
7-32
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Error Messages
setdev: can't understand 'xxxxx'.
The SETDEV command did not understand the string 'xxxxx'. Either
you mistyped the string or it is an invalid parameter .
• etdev: a CP/M logical device must be specified first.
A logical device name must be specified before a physical port.
setdev: physical device not available: 'xxxx'.
The specified physical device does not exist in the 4170.
See the list of valid physical device ports above.
setdev: '=' and argument required after 'xxxx'.
The parameter 'xxxx' must be separated from its argument by an
equals sign (=).
.
setdev: invalid baud rate.
Refer to Table 7-1 for valid baud rates.
setdev: invalid parity type.
The valid parity types are ODD, EVEN, and NONE.
setdev: invalid number of stopbits.
The valid values are 1 or 2.
setdev: invalid number of databits.
The valid values are 5, 6, 7, or 8.
setdev: invalid flagging data.
The valid values for flagging are NONE, XON, DTR, or RTS/CTS.
setdev:invalid drive specified.
Valid drive specifications for the boot and default drives are A:
through P:.
4170 INSTRUCTION
Rev, Mar 1984
7-33
SECTION 7
Programming Information
HOST COMMUNICATIONS AND THE MODEM86 UTILITY
The MODEM86 utility is used to establish communications between
the 4170 and a host computer. Section 5 explains how to get
started using MODEM86. If have not used MODEM86 before, follow
the instructions in Section 5 under the heading Connecting the
4170 to the Host.
Tektronix provides several preconfigured versions of the MODEM86
program on the MODEM86 diskette. The different versions are
MODM86-H.CMD, MODM86-1.CMD, MODM86-2.CMD, MODM86-3.CMD,
MODM86-4.CMD, and MODM86-5.CMD.
WHICH PROGRAM TO USE
The program to run depends on the 4170 port to which your host is
connected. For example, if the host is connected to the HOST port
on the 4170, you run the program MODM86-H. Refer to the list
below to determine which MODEM86 program to run.
Port
HOST
Port
Port
Port
Port
Port
Program
Port
1
2
3
4
5
MODM86-H
MODM86-1
MODM86-2
MODM86-3
MODM86-4
MODM86-5
(The file README. 1ST on your MODEM86 diskette also describes the
MODEM86 programs and their differences.)
The simplest way to run the MODEM86 program is to just type the
program's file name. If the host is connected to the host port,
for example, enter:
A>MODM86-H
(Note that you must type MODM86-H, not MODEM86-H.)
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MODEM86 starts by displaying the following menu options:
P - Purge (delete) present file (from terminal mode)
W - Write file to disk (from terminal mode)
C - Call number (intelligent modem only)
D - Disconnect (hang up phone)
T - Terminal mode in full-duplex
H
Terminal mode in half-duplex
E - Terminal mode with echo
R - Receive a file
S - Send a file
M - Menu
X - Toggle expert mode (menu on/off)
? - Help, command syntax description
F - File data display
L - List directory
V - Current value display
Q - Quit, exit to operating system
The menu options are described later in this document. Some menu
options may be missing from the menu at any given time, because
certain options only make sense at certain times.
After displaying the menu, MODEM86 then indicates the current
default disk drive and prompts for a command as follows:
Default drive: A
Enter command:
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ENTERING MODEM86 COMMANDS
MODEM86 expects a command from the main menu, followed
by a , whenever this prompt appears:
Enter command:
Generally, the command contains a menu option that may be
preceded by a drive specification and may be followed by
suboptions and a file specification. Here is the syntax:
{d:}{m{sssssss}{.baud}{filespec} }
where:
d:
m
s
baud
filespec
if specified, d: becomes the default disk drive
m is a menu option from the MODEM86 main menu; the menu
option may be omitted only when you are changing
the default drive
up to seven suboptions may be included with an
option from the main menu (See Overview of Command
Suboptions, which follows.)
baud rate in bits per second
indicates the name of a conversation save file
or the name of a file to be transferred. When you
use the M (Multifile) suboption, you may include
more than one filespec to indicate which files
will be sent.
Lowercase letters used in a command are translated into
uppercase.
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The "?" main menu option may be used to display a command syntax
description and a list of suboptions (suboptions are discussed
later in this section):
Enter command: ?(CR)
At the conclusion of each command, MODEM86 redisplays the menu
and default drive and prompts for another command. You can change
the default drive as follows:
Enter command: B:(CR)
You can change the default drive and display the help text with
one command:
Enter command: B:?(CR)
The following example shows how suboptions and a baud rate may be
included with a command:
Enter command: VN1.9600
The suboptions are N (no parity) and 1 (1 stopbit) and the baud
rate is changed to 9600 bits/second. The V option (from the main
menu) displays the changed communication parameters.
The baud rates that may be specified are 110, 300, 600, 1200,
2400, 4800, 9600, and 19200. The baud rate used must be the same
as the modem baud rate.
The default communication parameters (such as the baud rate) are
set by the MODEM86 program that you invoke (MODM86-H, MODM86-1,
etc.) For example, the MODM86-H program defaults to a baud rate
of 1200 bits/second. To change the defaults (for baud rate,
parity, stopbits, etc.), you must use the MODEMSET program; see
Changing Pre configured MODEM86 Programs, later in this
section.
NOTE
The MODEM86 program overrides (but does not
change) the baud rate and other communication
parameters set with the CONFIG or SETDEV
utilities. When you exit MODEM86, the
parameters set with CONFIG or SETDEV are
still in effect.
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Subsequent commands use the same communications settings unless
the settings are otherwise specified. Answer or Originate mode
(the 'A' suboption or the 'G' suboption, respectively) also stays
in effect until the mode is specified again. If the baud rate
needs to be changed, it may be done without changing the mode.
For instance, if MODEM86 is in Originate mode at 300 bits/second,
then the command R.600 NAME.TYP will allow MODEM86 to receive
a file at 600 bits/second in Originate mode. If the
Answer/Originate mode needs to be changed, then that may be done
without selecting the baud rate again.
A main menu option may be specified with the MODEM86 program
name, in a manner similar to specifying file names for CP/M-86
programs. For example, the following program call displays the
help text before displaying the menu and prompting for a second
command:
A>MODM86-H ?(CR>
The following command puts MODEM86 in expert mode immediately,
and thus avoids displaying a menu even before the first command
prompt:
A>MODM86-H X(CR>
In this manner, MODEM86 does not start by displaying the main
menu. Instead, it goes directly into the mode specified by the
program command. When that task is completed, MODEM86 displays
the main menu.
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Overview of the MODEM86 Main Menu Options
Here is a summary of the options (in alphabetical order) from the
MODEM86 main menu. Several options require an "intelligent"
modem, such as a Hayes modem, for the menu option to work.
C
used to call the host using an autodial modem connected to the
serial port. (Requires intelligent modem.)
D
used to disconnect from the host.
E
used to enter terminal mode with local echoing.
F
used to display a file or set of files on the console.
There
may be more than one filespec and each filespec may be
ambiguous. The contents of all files with matching
names are displayed on the console along with the file size
and name. If expert mode is off, then each file ,is separated
by a pause. CTRL-S may be used to temporarily stop the
display at any time; CTRL-Q starts it again. MODEM86 then
waits for another character to be typed before it continues.
CTRL-C may be used to terminate the display at any time.
H
used to enter terminal mode in half-duplex. This is useful for
talking to a smart modem or for hosts that require helf-duplex
mode operation.
L
lists the directory of the current default disk drive if no
filespecs are added. There may be more than one filespec and
each filespec may be ambiguous.
If any filespecs are included,
matching file names are displayed.
M used to get another menu.
on.
(Requires intelligent modem.)
This is useful when expert mode is
P
used to purge (delete) the conversation save file.
R
used to receive a data file from the host computer using an
error-checking protocol. (See Error-Free File Transfer,
later in this section.)
S
used to send a data file to the remote computer using an
error-checking protocol. (See Error-Free File Transfer,
later in this section.)
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T
used to enter terminal mode in full-duplex, without local echoing.
Q
used to quit (that is, exit) the program. If there is a
conversation save file open, MODEM86 does not allow the use
of Q to return to the operating system until either the W
menu option or the P menu option is used to close the
conversation save file. (This prevents data from being
accidentally lost.)
V
used to display the current values of various settings which
are remembered from command to command. This includes the bit
rate, modem mode, parity, number of stop bits, and the
conversation save file name.
W used to write out the conversation buffer to the conversation
save file, and to close the file.
X
toggles expert mode on and off. In expert mode the menu is not
displayed prior to asking for the next command.
?
prints help text on the terminal.
Some of these main menu options are described in more detail in a
following discussion, Transferring Files Using Terminal Mode.
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Overview of Command Suboptions
You may specify up to seven suboptions from this list after an
option from the main menu:
A
The A (answer mode) suboption is used to put an intelligent
modem into answer mode. Once answer mode has been selected,
any subsequent commands use the same mode.
(Requires
intelligent modem.)
B
The B (batch) suboption is used to prevent the program from
going into menu option mode after the command. Instead,
MODEM86 exits to the operating system.
C
The C (clear space parity) suboption is used to select 7-bit
characters with an additional parity bit, which is set to
zero. The parity is not checked with this option.
D
The 0 (disconnect) suboption is used to disconnect from the
host by hanging up the phone, or turning off the handshaking
signals after the menu option is completed.
This is done
after the T suboption if both are chosen.
This is similar in
function to the 0 menu option.
(Requires intelligent modem.)
E
The E (even parity) suboption is used to select 7-bit
characters with an additional even parity bit for serial I/O.
F
The F (file data viewing) suboption is used to view file data
as it is received.
G The G (originate mode) suboption is used to put the modem
board into originate mode. Once originate mode has been
selected, any subsequent commands use the same mode.
(Requires intelligent modem.)
H The H (half-duplex) suboption is used to return to
half-duplex terminal mode after another menu option is
completed.
M The M (multifile) suboption is used only with the Rand S
menu options to indicate a multifile transfer.
N
The N (no parity) suboption is used to select 8-bit
characters with no parity for serial I/O.
o
The 0 (odd parity) suboption is used to select 7-bit
characters with an additional odd parity bit for serial I/O.
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Q The Q (quiet) suboption is used to keep any MODEM86 messages
from being displayed. This can speed up file copies at higher
bit rates, or sometimes make file copies at higher bit rates
work. This is because writing the error messages can take
long enough to miss characters on the serial port. When
characters are missed, the data must be re-sent, but usually
the results of resending are the same. When this happens,
quiet mode can keep MODEM86 from missing the data, since it
doesn't print the message. This option also suppresses many
prompts for verification.
R
The R (redial) suboption, when you are using an intelligent
modem, continuously redials the phone number until there is
an answer. The user may abort the redialing by typing a
CTRL-X. This is only used with the C menu suboption.
(Requires intelligent modem.)
S
The S (set mark parity) suboption is used to select 7-bit
characters with an additional parity bit, which is always set
to one. The parity is not checked with this suboption.
T
The T (terminal mode) suboption is used to return to
full-duplex terminal mode automatically after another menu
option is completed.
V The V (view all data) suboption is used to view all file data
as it is transferred as well as any extra characters used for
headers and checksums.
X The X (extended checksum) suboption makes the file copy
checksum a 16-bit CRC-16 checksum. This is more reliable than
the parity checksum otherwise used.
1
The 1 suboption is used to select 1 stop-bit for each serial
character to and from the serial port. This is the default.
2
The 2 suboption is used to select 2 stop-bits for each serial
CLaracter to and from the serial port.
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TRANSFERRING FILES USING TERMINAL MODE
To transfer files between the 4170 and the host (without
error-checking protocol), you can use the T (Terminal mode)
option from the MODEM86 main menu.
In Terminal mode, characters typed at the keyboard are sent to
the host computer, which is expected to echo them back to the
MODEM86 program. Characters received from the host, including
echoed characters, are displayed on the screen.
T Menu Option -- Terminal Mode in Full-Duplex
The T menu option may be used with or without a file name. If a
file is specified (it should be a new file), then this enables
the conversation save feature. Conversation save files are
used for capturing files transmitted from the host to the 4170.
A list of all special control characters is given at the start of
Terminal mode. The list may include these characters (what
actually appears varies according to what was specified with T):
CTRL-B sends a break on the serial line. This is usually used
to get the attention of the host computer or to abort
something.
CTRL-D causes the program to turn off all the modem handshaking
signals it can, and do as much as possible to disconnect from
the host.
CTRL-E exits Terminal mode.
CTRL-L is used as a literal-next indication. The next
character typed is sent to the host computer without being
interpreted as a special MODEM86 command. This is used to send
the host control characters (such as CTRL-B).
CTRL-P purges the conversation save buffer. (Note that it
purges the buffer, not the conversation save file.)
CTRL-Q causes host output to continue after it has been halted
with CTRL-S.
CTRL-R allows the baud rate to be changed without changing
other parameters. The program asks you for the new baud rate.
CTRL-S halts host output.
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CTRL-T is used to initiate a file transfer from the 4170 to the
host. (See the discussion Transferring Files to the Host,
later in this section.)
CTRL-Y toggles conversation saving on and off.
If these particular control characters are inconvenient for some
reason, their functions can be reassigned to other control
characters with MODEMSET. (See Changing Preconfigured MODEM86
Programs, later in this section.)
Transferring Files From a Host Computer
Section 5 describes the procedure for using the T (Terminal
mode) menu option and the conversation save feature to capture
files transmitted from the host. (Before reading the discussion
here, refer to the the heading Transferring Files from the
Host in Section 5.)
When the conversation save feature is active, anything received
by the modem is saved in memory and may later be written to the
conversation save file. The conversation save feature is toggled
on and off by typing a CTRL-Y. A colon (:) is printed at the
beginning of each new line when the conversation save feature is
active. The colon is not transmitted over the modem nor will it
be saved in memory_ If you have not entered a filename with the
T (Terminal mode) since the last W (Write) or P (Purge), then the
conversation save feature cannot be activated.
If the conversation save memory buffer is full, the contents are
automatically written to the file specified in the T command, but
the file is not closed. Communications wi.ll then continue with
the buffer reinitialized. Your host computer should accept CTRL-S
and CTRL-Q (for the Host Output Pause and Host Output Continue
functions, respectively) or data may be lost during the file
write. If your host uses different characters for these
functions, you can use MODEMSET to change the characters to be
compatible (see Changing Preconfigured MODEM86 Programs,
later in this section). On small files that do not fill up the
memory buffer, this will not be a problem, even if your host
computer does not use CTRL-S and CTRL-Q.
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If errors are encountered while writing out the contents of the
conversation save buffer to the disk, MODEM86 closes the
conversation save file after writing as much as possible. Then it
indicates that the disk may be removed, if desired, and a new
disk inserted. Finally, it asks for the name of a new
conversation save file. Thus, even if the conversation file is
too big for one disk, it can be saved. (This may also happen
after you use the W main menu option to write and close the
conversation save file.)
While in Terminal mode, a CTRL-P can be used to purge the
conversation save buffer. This empties just the buffer, not the
entire conversation save file. MODEM86 asks if this is really
intended, since CTRL-P may have been entered by mistake and it
destroys data. You may decide to purge the conversation save
buffer if, after saving something to the buffer, you discover
that it should not be saved.
Use CTRL-E to exit from the Terminal mode and enter the Menu
Option mode. This is normally done when communications are over,
but there are other times when exiting Terminal mode is
desirable.
The conversation save file must be closed after exiting Terminal
mode using the W menu option. If this is not done before exiting
MODEM86, all saved conversation data is lost. The file is not
closed automatically because there are times you may want to
leave Terminal mode using CTRL-E, do another menu option, and
then reenter Terminal mode and continue saving to the same file.
To reenter Terminal mode in this fashion, use the T menu option
again with no file name. You may reenter Terminal mode (with the
conversation saved in the same file) as many times as required,
as long as you do not close the save file with the W menu option.
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Transferring Files to a Host Computer
Section 5 explains how to transfer files to the host from the
4170. (See the heading Transferring Files from the 4170 in
Section 5 before reading the following discussion.)
Briefly, transferring files to the host involves using Terminal
mode and CTRL-T; while in Terminal mode, CTRL-T allows MODEM86
to send an ASCII (as opposed to binary) file over the serial
connection to the host computer. You can also use CTRL-T to send
common sequences of commands to the host.
This type of transfer does no error-checking; there is no
protocol specified between the MODEM86 program and the host other
than that the host should be ready to receive data via the serial
connection. If the host computer sends a CTRL-S (X-OFF), then
MODEM86 stops sending until it receives a CTRL-Q (X-ON). (If your
host uses different characters for these functions, you can use
MODEMSET to change the characters to be compatible -- see
Changing Preconfigured MODEM86 Programs, later in this
section). Since host computers normally echo data being input
and binary files can have the X-ON and X-OFF bytes in them,
transfers using CTRL-T in Terminal mode are really only safe for
ASCII (character) files. (However, the MODEM86 utility program
BIN2HEX can be used to convert a binary file into a character
file prior to transfer; see Conversion of Binary Files, later
in this section.)
In most cases CTRL-T is preceded by a host command that captures
the data that will be sent into a host file. MODEM86 asks for the
name of the file to transfer and whether line feeds should be
sent after carriage returns at the end of each line. Typing a
CTRL-X during a simple file transfer cancels the transfer.
MODEM86 estimates how long it will take to transfer the file to
the host. The estimate is a minimum, based on the file size and
the baud rate. This minimum will probably be exceeded by at least
a little bit, because of time taken to do disk reads and the
delays caused by the host sending a CTRL-S (X-OFF).
If you specify the F or V suboptions with the T option, the
terminal displays the host's responses to file data (including
host echo of the file data, if any). If you do not specify either
F or V, then no host characters are displayed during the file
copy. In general, it is suggested that you choose either the F
or V suboption, since error messages from the host are then
displayed; otherwise, you will not see these messages. Displaying
the host's responses also slows down the file data transfer at
line endings and allows the host more time to digest each line.
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You may also use the CTRL-T simple file transfer for things like
autodialing and autologon. If you use an autodial modem, then you
may create a file with appropriate commands in it, and later
specify that file in a CTRL-T simple file transfer command. This
"results in the file being sent to the modem, which takes the
appropriate actions according to the commands. Similarly, you
can create a file with what is needed to log-on to a host. You
can use the CTRL-T simple file transfer, then, to send the
commands to the host, as though you had typed them in.
H Menu Option -- Terminal Mode in Half-Duplex
The H (Terminal Mode in Half-Duplex) option enables terminal mode
in half-duplex. This mode is useful to talk to an intelligent
modem; when the automatic dialing commands is used, for example,
the modem's response echoes on the screen. Also, some host
systems may require half-duplex terminal mode.
E Menu Option -- Terminal Mode With Echoing
The E (Terminal Mode with Echoing) option is useful when the 4170
is required to communicate with another terminal or computer
running MODEM86. One terminal should be in Terminal mode with
Echoing, and the other terminal should be in Terminal mode.
Terminal mode with echoing is similar to regular Terminal mode.
The difference is that when you type characters at your terminal,
you will see the characters on your terminal's screen and they
will "echo" or appear on the screen of the other terminal.
Characters typed at the other terminal will also appear on your
screen.
W Menu Option -- Write and Close Conversation File
The W option must be used after leaving Terminal mode. This
writes the last conversation save memory buffer to the disk and
closes the conversation save file. If there is a conversation
save file open, you cannot return to the operating system (the Q
option) until either the W option or the P option is used to
close the conversation save file. This prevents data from being
accidentally lost.
If errors are encountered while writing out the contents of the
conversation save buffer to the disk, MODEM86 closes the
conversation save file after writing as much as possible. Then it
indicates that the disk may be removed and a new disk inserted.
Finally, it asks for the name of a new conversation save file in
which it saves the remainder of the conversation save buffer.
Thus, even if the file conversation is too big for one disk, it
can be saved.
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P Menu Option -- Purge Conversation File
The P (Purge) option erases (deletes) the most recent file
accessed in Terminal mode. This is useful when, after
communications, you decide that the conversation did not need to
be saved in the file. If there is a conversation save file open,
MODEM86 does not allow you to use the Q option to return to the
operating system until either the W option or the P option closes
the conversation save file.
Examples
To enter Terminal mode, to save communication in the file
save.txt, to use the default baud rate, and to specify Originate
mode:
Enter command: TG save.txt
Once in Terminal mode, type CTRL-Y to start saving, CTRL-E to
exit Terminal mode, and W to write and close the file save.txt.
To act as the host computer to another computer that is using the
above command, with no saving:
Enter command: EA
To write out the rest of the save buffer to the file save.txt
(specified in the first example):
Enter command: W
To purge or delete the file save.txt rather than saving it:
Enter command: P
The next example is the same as the first example, but there is
no intelligent modem. The modem is set to originate by hand, and
the baud rate is 1200 bits/second:
Enter command: T.1200 save.txt
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ERROR-FREE FILE TRANSFER
S Menu Option -- Send File Mode
R Menu Option -- Receive File Mode
The S (send file) and the R (receive file) menu options are used
to do error-free file transfers between two 4170s, between a 4170
and another system running MODEM86, or between a 4170 and a
system running a MODEM86-compatible program such as XMODEM.
(Many free-access bulletin board systems use MODEM86 or a
MODEM86-compatible program, enabling you to transfer data between
those systems and the 4170.)
To do error-free file transfers between two systems, one unit
runs MODEM86 and uses the S option to send the file data, while
the other unit runs MODEM86 and uses the R option to receive the
same file data.
A special protocol (a procedure to follow for sending and receiving
the data) is used to ensure that the file is received intact
without the possibility of lost or changed data, which often
happens in file transfers without a protocol.
It is not necessary to understand the protocol to use the Sand R
options; it is necessary only to understand how to give the
commands that start the transfer to the program. The Sand R menu
options normally require one filename to be specified -- the name
of the file to be sent or received.
Using the M (Multifile) suboption, you can specify more than one
file and/or ambiguous filenames to designate the files to be
transferred. To send files, use the S option and the suboption M
(along with any other suboptions and a baud rate, if desired). To
receive the files being sent, use the R menu option and the M
suboption. For multifile transfers, you must not name the
received files since filenames are sent by the sending program,
but you may specify a disk drive (otherwise, the files are
written to the default drive). Existing files with the same name
as a received file are deleted.
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For the S menu option, MODEM86 estimates how long it will take
to transfer the file. The estimate is a minimum, based on the
file size and the baud rate. This minimum will probably be
exceeded by at least a small amount because of the time taken to
do disk reads, delays caused by the other unit, and possible
resending of blocks in the event of errors. For the R menu
option, MODEM86 cannot estimate the duration of the file transfer
because the size of the file is not known until the file is
received.
Examples
To send the file stuff.txt with the modem in the Originate mode at the
current baud rate:
Enter command: 8G stuff.txt
To send another file (more.txt) with the same modem mode and the
same baud rate:
Enter command: 8 more.txt
To receive the file junk.txt on drive B (at the new baud rate of
600 with the modem in Answer mode), to view just the file data
being received, and to return to Terminal mode when done:
Enter command: RAFT.600 B:junk.txt
To send all the ".com" files, with no messages to be displayed,
at the current baud rate and with the current modem mode:
Enter command: 8MQ *.com
To send two files (afile.txt and bfile.txt) from two different
drives with one command:
Enter command: 8M A:afile.txt B:bfile.txt
To receive on drive A the two files sent by the previous example
(afile.txt and bfile.txt):
Enter command: RM A:
Note that for the R command to work the baud rates must be the
same and the modem modes must be the opposite. Because the above
example uses R with the multifile suboption (M), no file names
are specified.
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To receive the file safe.com on drive B using the Extended
(CRC-16) Checksum mode at a new baud rate of 1200 bits/seconds:
Enter command: RX.1200 B:safe.com
To send all the ".com" files from disk B:, use the Originate mode
(intelligent modem only) at 600 bits/second, and return to Terminal
mode when done:
Enter command: SMGT.600 B:*.com
To receive all the files being sent from the previous example on
the default drive using Answer mode (intelligent modems only) at
600 bits/second:
Enter command: RMA.600
To send asm.com from the default drive, all the ".hex" files from
the default drive, and all the files starting with "m" from the
drive B:
Enter command: 8M.600 asm.com *.hex B:m*.*
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CHANGING PRECONFIGURED MODEMa6 PROGRAMS
The original MODEM86 program was designed to enable host
communications on several types of computers, including the
Tektronix 4170. The MODEM SET program was used to preconfigure to
create the preconfigured 4170 versions of MODEM86 (MODM86-H,
MODM86-1, etc.). To create these different versions, these
parameters were specified to MODEMSET:
(1) Computer - Tektronix 4170
The MODEM86 communications port depends on the particular
MODEM86 program. Here is a cross-reference of the preconfigured
MODEM86 programs, the MODEMSET communications port number, and
the corresponding 4170 physical port. (Note that MODEMSET
communications port 2, which is reserved for OEM use,
corresponds to Port 0, the terminal port, on the 4170.)
Preconfigured
Program
MODM86-H
MODMS6-1
MODMS6-2
MODM86-3
MODM86-4
MODM86-5
MODEMSET Communications Port
4170
Physical Port
1
HOST
Port
Port
Port
Port
Port
3
4
5
6
7
Port
1
2
3
4
5
(2) CPU and Memory
CPU Clock - 5MHz
Data Path Width - 16 bits
Wait States - 1
(3) Serial I/O Port Hardware
Serial I/O Device - For MODM86-H, the device is the
Tektronix Host Port; for MODM86-1 thru MODM86-5, it is
the INS 8250 ACE.
Serial I/O Device Memory Mapped - No
Serial I/O Device Base Address (in hex) - EO
Serial I/O Register Separation - 02H
Bit Rate Generator ClOCK Input - 2458 kHz
Serial Interrupt Enable Modified - Yes
Serial Receive Character Interrupt Enabled - Yes
Interrupt Controller Base Address (in hex) - ES
Interrupt Controller Register Separation - 02H
Interrupt Controller Base Vector Number - 80
Serial Receive Character Interrupts
(IRQ number in hex) - 1
Interrupt Routine Checked - Yes
7-52
Rev, Apr 1984
4170 INSTRUCTION
SECTION 7
Programming Informa tion
(4) Terminal Mode Control Characters
CTRL-B
Break
CTRL-D
Disconnect
CTRL-E
End Terminal Mode
CTRL-L
Literal
CTRL-P
Purge conversation buffer
CTRL-R
Bit Rate Change
CTRL-T
File Transfer
CTRL-Y
Toggle Conversation Saving
CTRL-S
Host Output Pause
CTRL-Q
Host Output Continue
(5) Default Settings Group
Baud Rate - 1200 bits/second
Minimum Timeout Period - 0 seconds
Parity - None
Stop Bits - 1
Expert Mode - No
Use of Bells - Yes
Host Requires Line Feeds - No
XOFF/XON's Sent Automatically - Yes
NOTE
It is recommended that you only change
terminal mode control characters or default
settings listed in (4) and (5).
You can make changes to any of the preconfigured 4170 versions
using the following procedure. (It is suggested that you copy the
MODEl186 diskette first and only make changes to the copy.) The
diagram in Figure 7-4 outlines the procedure. Notice how you may
repeat the procedure (in an almost cyclical fashion) until you
get the precise configuration that you want.
You may want to reconfigure a version of MODEM86, for example, to
specify a different baud rate as the default, or to change the
control characters that MODEM86 uses.
4170 INSTRUCTION
Rev, Apr 1984
7-53
SECTION 7
Programming Information
.
MODM86-H.CMD
MODM86-1.CMD
··
·
MODM86-S.CMD
Rename an existing MODEM86 program to MODEM86.SET.
MODEM86.SET
MODEM86. SET becomes input for
MODEMSE T and sets the defaults.
MODEMSET.CMD
Run MODE MSET. This generates a new version
of the prog ram, called MODEM86.CMD.
MODEM86.CMD
Rename th e new version of the program.
MODM86-H.CMD
MODM86-1.CMD
'-- -
··
The process can later be repeated, as necessary.
·
MODM86-S.CMD
4685-140
Figure 7-4. Changing a Preconfigured MODEM86 Program.
7-54
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Procedure for Reconfiguring MODEMS6. First, rename one
of the 4170 versions of MODEM86 (MODM86-H.CMD, MODM86-1.CMD, ...
MODM86-5.CMD) to the filename MODEM86.SET. MODEM86.SET is input
to MODEMSET.CMD and sets the default values for the MODEMSET
program.
Then enter the command:
MODEMSET(CR)
and follow the prompts. Press GENCMD MODEM86 8080
BYTES READ
0000
RECORDS WRITTEN 00
A)DDT86
DDT86 1.1
-RMODEM86.CMD
START
END
6DCO:0000 6DCO:4CFF
-WMODEM86.CMD,0180,4CFF
-C
Notice that the starting address used in the W command should
always be 0180, and the ending address should always be the same
as the one displayed by DDT86.
7-58
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
IF YOU HAVE A PROBLEM WITH MODEM86
If you encounter problems with MODEM86, refer to the following
headings, which describe some typical problems with MODEM86. If
your problem does not match one of these descriptions, contact
your local Tektronix field office.
MODEMSET Gives Strange Default Answers
MODEMSET gets the default answers from the MODEM86.SET file. The
MODEM86.SET file is just a version of MODEM86 that has been
renamed for MODEMSET. If you renamed the wrong file, the values
will not look right. Press return until the MODEM SET menu is
printed again, choose the first selection again, and respond to
the prompts without using the defaults, unless they are the
correct answers.
This problem may also indicate that the version of MODEM SET is
not compatible with the version of MODEM86 in MODEM86.SET. This
means that the MODEM86 diskette may not have the right files;
contact your local Tektronix field office for a new diskette.
SIO Parameter Error Message
MODEM86 only prints this error when it detects something wrong
with the serial I/O port description provided to it by MODEMSET.
Usually this is because when you reconfigured a MODEM86 program
you answered a prompt incorrectly for the system that MODEM86 is
currently running on. The solution is to run MODEMSET again, and
to carefully answer the questions.
Sometimes MODEM86 cannot detect a configuration error. Usually
when this happens, it does something wrong immediately and the
system often requires resetting. Again, the solution is to
reconfigure MODEM86 using MODEM SET , carefully answering the
questions. The default configuration answers can be used, but
there is a good chance that they are wrong. It is a good idea to
verify the answers by carefully; refer to the earlier discussion
in this section, Changing Preconfigured MODEM86 Programs.
4170 INSTRUCTION
Rev, Mar 1984
7-59
SECTION 7
Programming Information
Incompatible Versions Error Message
Occasionally an incompatible MODEMSET program is placed on a disk
with MODEM86. Both MODEMSET and MODEM86 have internal version
numbers to prevent this from happening without a warning.
MODEMSET leaves a copy of its version number in MODEM86 during
the configuration process. The version numbers are later compared
when MODEM86 runs. If the versions are not the same, this error
message occurs. Contact your local Tektronix field office.
Data is Lost From Each Line
Sometimes, serial data is missed when a line feed is followed too
closely by characters from the next line. In this case, it is
wise to tell the host to delay after a line feed prior to sending
more data, if it can be done. Otherwise, MODEM86 may miss a few
characters at the beginning of each line at the higher data rates
(such as those greater than 1200 bits/seconds).
If a host delay after a line feed does not solve this problem,
the baud rate is probably higher than the 4170 or its terminal
can handle. Try lowering the baud rate to 300; this should be
slow enough to be handled by most terminals. If this works, the
baud rate was probably too high originally. Try higher baud rates
until you find the highest baud rate that the system can handle.
Checksummed File Copying Aborts
This is often a baud rate problem. There are several possible
solutions.
The most common problem is that the baud rates used by the
4170 and host are not the same. The solution is to match the baud
rates and try again.
The quiet suboption Q can be used to keep any MODEM86 messages
from being displayed. This can speed up file copies at higher
baud rates, or sometimes make file copies at higher baud rates
work. Displaying characters may take long enough so that
characters on the serial port are missed. When the characters are
missed, the data is resent, but usually the result of resending
is the same. When this happens, Quiet mode can keep MODEM86 from
missing the data, since the message is not printed.
If the Q suboption fails to work, another possible solution is
to use the F suboption on both the 4170 and the host. This
could slow both down at critical points.
7-60
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
If neither the Q or F suboptions allow the file copy to proceed,
you may have to reduce the baud rate for the file copy. Set the
baud to 300 bits/second, and then increment it until you find the
highest baud rate that works. Sometimes it is possible to do file
copying with the IQI or 'F' suboptions at higher baud rates than
normal terminal operations.
File Data and Host Messages not Displayed
During a simple non-checksummed file transfer (started by a
CTRL-T while in Terminal mode), file data and host messages are
not normally displayed. This speeds up the file transfer because
there is no delay caused by the scrolling of the terminal.
However, if something goes wrong, any error message generated by
the host is not displayed. This may make it difficult to
determine what went wrong. The solution is to use the F or V
suboptions on the T option to enter Terminal mode. When at least
one of these options is used, all echoing and messages from the
host are displayed during the simple file transfer. Depending on
the kind of terminal, this often has the effect of slowing down
the transfer by delaying after each line feed. This can help the
file copy if the host needs time to digest each line as it comes
in.
MODEM86 Runs but Nothing is Received From the Host
There are a number of situations that have this symptom. Check
out all of the following possibilities:
o
Check the handshaking signals line using the V option. If
MODEM86 indicates that the handshaking signals are not all
on, then one of the signals (DCD -- Data Carrier Detect -Pin 8, CTS -- Clear To Send -- Pin 5, or DSR -- Data Set
Ready -- Pin 6) is not connected to the modem and may be
required before the serial IC will send data to the host. It
may also be the case that one of the signals RTS (Request To
Send -- Pin 4) or DTR (Data Terminal Ready -- Pin 20) was
not connected and the host did not see any data from the
computer running MODEM86.
o
For some computers, a null modem cable is necessary for
connection to a modem. For most computers, a null modem is
not necessary to connect two computers together. A null
modem is a cable with the wires "crossed" so that: Pin 2 on
each end is connected to Pin 3 on the other end; Pin 8 on
each end is connected to Pin 20 on the other end and to Pins
5 and 6 on the same end; and Pins 1 and 7 are connected
directly to the same numbered pins on the other end.
4170 INSTRUCTION
Rev, Mar 1984
7-61
SECTION 7
Programming Information
o
Check that the the 3-Port Peripheral Interface is installed
correctly.
o
If the modem being used has a half/full duplex switch, is it
set to full duplex? If it is set to half duplex, change it
to full.
o
If the modem being used has an originate/answer switch, is
it set to originate? If it is set to answer, change it to
originate. Most hosts use Answer mode, and expect terminals
to use Originate mode.
o
If the modem is an acoustic modem, is the handset placed in
the modem correctly? One end of the modem acoustic coupler
must always have the cord end of the handset, and the modem
is usually marked to indicate which end. Also, is the
handset being placed in the modem acoustic coupler quickly
enough? If not, the host will probably hang up the phone
before it is in. If the handset never seems to be placed in
the acoustic coupler quickly enough, try putting the handset
into the coupler after the first ring, instead of when the
carrier signal comes on as the host answers the phone.
o
Is the modem a "smart" modem, capable of handling
autodialing? The modem must be told to dial up the host.
Refer to the modem documentation for help with this.
o
Was the baud rate specified correctly using MODEMSET, or in
the MODEM86 command? If specified incorrectly, MODEM86 will
not receive any characters correctly, although it will be
able to detect the carrier signal and will think the host is
connected. The solution is to specify the correct baud rate.
o
Is the network or host phone number being dialed while
MODEM86 is running? If not, the network or host may hang up
because the DTR (Data Terminal Ready) signal may not be
provided when the host answers the phone. The solution is to
hang up, and then dial the host again while MODEM86 is
running.
o
Is the phone number dialed the correct number for the host
being used? Is it the correct phone number for the baud rate
being used? If not, the solution is to use the correct phone
number.
7-62
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
PROTOCOLS USED
The protocols used are the same as the CP/M MODEM 7.412 program,
with a modification for the possibility of a CRC-16 checksum.
(The CP/M MODEM 7.412 program is used on many public bulletin
board systems and RCPM systems. Because the same protocols are
used, you can transfer data between those systems and a 4170 with
MODEM86.)
Whenever MODEM86 expects to receive something, there is a timeout
period; when the timeout expires, MODEM86 tries to recover, up to
a limit of ten times. When MODEM86 reaches the limit, it asks
whether it should retry another ten times or quit. When it
succeeds after recovery, the error count is reset to zero.
Single File Transfer
1. Receiver sends an NAK.
2. Transmitter (sets checksum to zero and) sends:
o
SOH for more data (included in the checksum), or
o
EOT for end of transfer (go to 6), or
o
CAN for cancel (go to 7).
3. Transmitter sends:
o
Block number mod 256 (included in the checksum).
o
255 - (Block number mod 256) (included in the checksum).
o
128 bytes of data.
o
Checksum bytes (1 or 2 depending on type used).
4. Receiver sends ACK if checksum is OK, sends NAK if not (or a
timeout), or sends a CAN (go to 7).
5. Transmitter starts at Step 2 with next block ACKed, or same
block NAKed. If no response at all (timeout), assumes NAK.
6. Receiver sends ACK.
7. End of transfer.
4170 INSTRUCTION
Rev, Mar 1984
7-63
SECTION 7
Programming Information
Multifile Transfer
1. Receiver sends a NAK.
2. Transmitter sends an ACK (then sets checksum to zero).
3. Transmitter sends:
o
EOT for no more files (go to 9), or
o
11 characters of file name (padded with blanks).
4. Receiver sends back an ACK after each file name character.
5. Transmitter sends a CTRL-Z (included in the checksum).
6. Receiver sends back the checksum.
7. Transmitter sends an ACK if the checksum is good (go to 8)
or sends a 075H if the checksum is bad (go to 1).
8. Use single file protocol to send file data (go to 1).
9. End of transfer.
CRC-16 CHECKSUM
The CRC-16 checksum is a standard block checksum generated by the
binary generator polynomial X**16+X**15+ ... X**2+1. For a
reference, see Technical Aspects of Data Communications by
John E. McNamara. (CRC stands for Cyclical Redundancy Check.)
Portions of this MODEM86 discussion were reproduced or
modified with permission from MODEM86 Documentation,
copyright 1982, 1983 by Mark Hersey, Compuview
Products, Inc.
7-64
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
FORTRAN-86
FORTRAN-86 is an extended version of the FORTRAN 77 subset
defined by the American National Standards Institute (ANSI). The
FORTRAN-86 compiler translates your FORTRAN source programs into
relocatable object code.
This code can then be linked with other
object code modules (generated by FORTRAN-86, ASM86, or other
compatible languages) and executed.
THE FORTRAN-86 FILES
The FORTRAN files are distributed on two flexible disks -FORTRAN-86, Volumes I and II. The FORTRAN files include
FORT86.LTL -- the FORTRAN compiler; LINK86.LTL -- the linkage
editor; LIB86.LTL -- the librarian utility; and the run-time
libraries.
Also included on the FORTRAN-86 diskettes is
FDTI.LIB, an object library of the FORTRAN Direct Terminal
Interface source code.
NOTE
The Direct Terminal Interface (DTI) is
recommended for application programs that run
on 4100 terminals with Local Programmability
and that use specific features of these
terminals. Because it directly controls
terminal features, DTI offers high
performance and small code size. However,
using DTI limits transportability
specifically to the 4100 terminals. (See
Using the DTI on the 4170, at the end of
lnTssect i on:;-------,--
When writing applications requiring
transportability to non-Tektronix graphics
devices, you should use the GSX-86 drivers.
The Interactive Graphics Library is
appropriate for applications that will be
uploaded or downloaded from a host mainframe
and that follow the SIGGRAPH CORE proposed
standard.
4170 INSTRUCTION
Rev, Mar 1984
7-65
SECTION 7
Programming Information
The FORTRAN-86 diskettes contain several libraries of object code
subroutines that perform I/O and other important functions for
FORTRAN programs during execution. These files are also known as
"run-time" libraries and are called:
CEL87.LIB
F86RNO.LIB
F86RN1 . LIB
F86RN2.LIB
F86RN3.LIB
F86RN4.LIB
EH87.LIB
8087.LIB
LARGE.LIB
Although these files are not needed for FORTRAN compilation, you
will need them to link and execute your compiled FORTRAN object
code.
COMPILING A FORTRAN-86 PROGRAM
To compile a FORTRAN source program, type:
RUN FORT86 myprog.for {controls}
myprog.for
is the file containing your source program. The file
specification should conform to the operating
system's convention for naming files.
controls
is an optional list of compiler controls separated by
spaces. (See Additiona~D~tail~ later in this section.)
For example, to compile the .source code file MYFORT. FOR on drive
B: with the compiler and loader on the current default drive
( A: ), type:
RUN FORT86 B:MYFORT.FOR
FORT86 generates an object code file with the same name as your
source file and an extension OBJ. It may also produce various
other files containing listings, symbol tables, etc.; this
depends on the controls you specify during invocation.
7-66
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
During compilation, FORTRAN-86 creates and uses several temporary
work files, deleting them when compilation is complete. Always
leave plenty of space for these work files on the disk (typically
60 to 80 K bytes). The FORTRAN compiler also creates a file with
a .1ST extension. TYPE this file to read any errors produced
during compilation.
LINKING AND EXECUTING A FORTRAN-S6 PROGRAM
To link the object file generated by FORT86 with the run-time
libraries and other object files of your own, type the invocation
as follows (filespecs of files that are not on the default drive
must include a drive specifier):
run 11nkS6 myprog.obj,{file list,}celS7.1ib,fS6rnO.lib, &. These
continuation characters enable the linker to accept a command
longer than one line. The linker creates a file with a .MP1
extension. This file contains results of the linking operation.
TYPE myprog.MP1 to review results of the link operation.
NOTE
Use the STREAM or QS programs (supplied on
the Program Exchange diskette) to simplify
link operations. Type out the files
STREAM.DOC or QS.DOC (also on the Program
Exchange diskette) for more information.
(STREAM.DOC gives an example of using STREAM
to compile and link an object file.)
4170 INSTRUCTION
Rev, Mar 1984
7-67
SECTION 7
Programming Information
To execute your linked program, type:
RUN myprog
The RUN utility loads and runs your program. Control returns
to the operating system after your program is finished.
Compiling and Linking with Flexible Disks
To compile and link FORTRAN programs using only the two flexible
disk drives, it is recommended that you put the compiler
(FORT86.LTL) on one diskette, the linker (LINK86.LTL) and
run-time libraries on another, and the FORTRAN source program on
a third diskette.
Then, when you compile and link the source program, specify the
disk drive before file names, as reQuired. For example, this
command compiles the source "myprog.for" on the diskette in drive
A (using the compiler on the diskette in drive B):
A>RUN B:FORT86 myprog.for
Because the compiling operation creates several temporary work
files (and then deletes them upon completion), you should allow
plenty of space on the source diskette for the work files.
To link the object file, remove the diskette that has the compiler,
and insert the diskette with the linker and run-time libraries in
its place. Then, specify the link command, as in this example
(the example assumes that the diskette in drive A has the object
file "myprog.obj" and that the diskette in drive B has the linker
and run-time libraries):
A>RUN B:LINK86 myprog.obj,B:ce187.1ib,B:f86rnO.lib, &
A»B:f86rn1.1ib,B:f86rn2.1ib,B:f86rn3.1ib,B:f86rn4.1ib, &
A»B: eh87.11 b,B :8087 .li b, B:large .li"b to myprog.l tl bind purge
If you are using only flexible disk drives to compile and link an
IGL program, refer to the procedure IGL Wi th ..1:.lexi~!~
Disk~!~~~, later in this section.
7-68
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
FORTRAN-86 FEATURES UNIQUE TO 4170 CP/M-86
As explained in the FORTRAN-86 User's Manual, FORTRAN-86 allows
you to associate logical unIt numoers with specific files and
physical devices.
This is done using OPEN statements (connection)
and with UNIT controls appended to RUN commands (preconnection).
Only two unit numbers are connected by default:
o
Unit 5 - keyboard of connected terminal
o
Unit 6 - display screen of connected terminal
Other logical units in the range 0 - 255 are undefined.
To
associate a unit number with a file on a specific disk or drive
or under a particular user number, include the appropriate drive
and user number specifiers in the name you give in the FORTRAN
OPEN statement.
The following OPEN statement, for example, opens
the file MYFILE.DAT on drive B: under user number 4, connecting
it to unit 99:
OPEN(99,FILE='B:MYFILE.DAT[g4], ,STATUS='NEW')
Similarly, you can talk to the 4170 CP/M-86 logical devices
Console (CON:), Auxiliary (AUX:), and List (LST:). Use the
following names in place of disk file names:
CP/M Console
CON:
CONOUT:
CONIN:
device:
Console input and output
Console output
Console input
CP/M Auxiliary device:
AUX:
Auxiliary input and output
AXO:
Auxiliary output
AXI:
Auxiliary input
CP/M List device:
LST:
List output
For example, to set FORTRAN logical unit number 7 for Auxiliary
input and unit 8 for Auxiliary output, you can use the following
OPEN statements:
OPEN(UNIT=7,FILE='AXI:')
OPEN(UNIT=8,FILE='AXO:')
4170 INSTRUCTION
Rev, Mar 1984
7-69
SECTION 7
Programming Information
The CP/M logical devices can be used with file pre-connection
also. The following command assigns FORTRAN logical unit numebr
15 to the CP/M List device:
RUN MYPROG(UNIT15=LST:)
FORTRAN OVERLAYS
When a FORTRAN program is too large to load into memory in its
entirety, you may need to "overlay" the program to make it
usable. Overlaying is a practice of loading program modules into
a common region of memory as they are needed. Essentially, this
reduces the needed memory to an amount sufficient to hold both
the main or "root" program and the largest subprogram.
The operating system has a special subroutine, DQOVER, to load
overlays. A call to DQOVER has this form:
CALL DQOVER (MODNAM,IERROR)
l'10DNAM
is the character string identifying the overlay module
to be loaded. An overlay module can include several
subprograms.
IERROR
returns an integer indicating whether the overlay was
loaded successfully: 0 indicates success; less than 0
indicates a failure, probably because the overlay was
not found.
Once DQOVER has loaded an overlay module, you can invoke
subprograms from that module as usual. Overlay modules remain in
memory until overwritten by subsequent overlays.
7-70
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
The following is an example of a simple overlayed program:
File ROOT.FOR:
PROGRAM ROOT
print *,'This is the root module"
C Load the first overlay and call it
call d~over( 'OV1 ',ierr)
if (ierr .ne. 0) goto 100
call ov1
C Load the second overlay and call it
call d~over( 'OV2' ,ierr)
if (ierr .ne. 0) goto 100
call ov2
goto 900
100
print 'Error on overlay load: ',ierr
900
end
File OV1.FOR:
subroutine ov1
print * , 'This is overlay 1 '
return
end
File OV2.FOR:
subroutine ov2
print *,' This is overlay 2'
return
end
Linking an overlayed program is a three-step process. First.
link the root and any re~uired libraries. Second, link each
overlay against the root and any re~uired libraries. Third, link
the files produced by all the previous links into the final
executable file.
4170 INSTRUCTION
Rev, Mar 1984
7-71
SECTION 7
Programming Information
Here are the commands to link the root. These commands also
force some routines required explicitly for proper overlay
execution into the root.
Run l1nk86 Root.obj, eh87.lib(tqinstruction retry),ce187.lib,&
f86rnO.11b,f86rn2.lib(input edit table,output edit table),&
f86rn1.l1b,f86rn2.lib,&
-fS6rn4.l1b(format seq device driver,unformat se~device driver),&
fS6rn3.l1b,f86rn4~11b~&
- eh87.lib,8087.lib,large.lib &
to root.lnk overlay(root)
Then link the overlays against the root:
Run l1nkS6 ov1.obj,ce187.l1b,&
f86rnO.11b,f86rn1.lib,f86rn2.lib,f86rn3.lib, f86rn4.lib,&
ehS7.l1b, S087.l1b, large.lib &
to ov1 .lnk overlay(ov1) assumeroot (root.lnk)
Run link86 ov2.obj, ce187.lib,
fS6rnO.lib,f86rn1 .lib,f86rn2.lib,f86rn3.lib, f86rn4.lib,&
eh87.l1b, 8087.lib, large.~ib &
to ov2.lnk overlay(ov2) assumeroot(root.lnk)
Finally, link everything together:
Run link86 root.lnk,ov1 .lnk,ov2.lnk to root.ltl purge bind nomap
It is normal to receive warnings for UNRESOLVED EXTERNALS from
the linker in all the links except the last. However, if the
final link also reports an UNRESOLVED EXTERNAL, then the missing
symbol must be located and the problem corrected.
The PURGE and BIND directives are used only on the final link.
Also note the use of the ASSUMEROOT directive. This directive
tells the linker that a subroutine call in an overlay should
point to the subroutine in the root, if the file ROOT.LNK contains
that subroutine. This avoids loading the same subroutine into
both the root and the overlay.
The above examples were designed for the sample program. If
additional object files need to be added to the root or overlay
files, add them following the main program or overlay. For
example:
Run link86 root.obj,sub1 .obj,sub2.obj,eh87.lib(tqins ... etc.),
Run link86 ov1 .obj,sub3.obj,sub4.obj,ceI87.lib,& etc ..
7-72
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
If additional library files are used, add them to the root file
as well as to the overlays:
Run link86 root.obj,fdti.lib,eh87.lib, etc ...
Run link86 ov1.obj,fdti.lib,ce187.lib,etc ...
ADDITIONAL DETAILS ABOUT FORTRAN-86
The Intel manual,FORTRAN-86 Users Manual describes FORTRAN-86
in detail. The FORTRAN::sbPoC'l{8:r-ReTerence Guide provides a
concise list of FORTRAN-s5- statements and compiler controls for
quick reference.
CAUTION
Do not use the invocation commands and device
descriptors as given in the two Intel
manuals; FORTRAN-86 under the 4170 CP/M-86
recognizes only the invocation sequence
described in this section.
4170 INSTRUCTION
Rev, Mar 1984
7-73
SECTION 7
Programming Information
IGL
INTRODUCTION
The 4170 software includes an object library version of the
Interactive Graphics Library (IGL). This verSlon contains the
Primary Command Set, Panel Support, Panel Emulation, and selected
device drivers. For expanded IGL capabilities (Line Smoothing,
Segments, 3-D, and additional terminal support), you may order
the Tektronix 4170P73, Options 23 and 24.
Refer to the IGL User's Manual (that supports Level 5 and up) and
the IGL Reference Guide for more detailed information on using
IGL. (These manuals are included with the 4170.)
This section contains information for getting IGL programs
running on your 4170. It includes:
o
General information for using the subset of IGL provided.
o
Information for setting up IGL on the hard disk and for
compiling, linking, and running programs on the hard disk.
o
Information for using IGL if you don't have a hard disk
(including how to redistribute files on diskettes so that
you can compile, link, and run your programs).
Requirements for Running IGL
The minimum requirements for running IGL are a graphics terminal
attached to the 4170 and at least 256K bytes of memory. It is
strongly recommended that the optional hard disk be a part of the
4170, and that IGL, FORTRAN, and your application program be
resident on the hard disk. A system with a hard disk (Options 03
and 45) can handle the largest IGL programs, and affords the
added benefits of increased development speed and greater
convenience. If you do not have a hard disk, you may need some
blank disks to redistribute the IGL files.
7-74
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Diskette Contents
Your two IGL diskettes contain these files:
o
IGLA.LIB--the first part of the IGL library
o
IGLB.LIB--the second part of the IGL library
o
ERRFIL.DAT--the random access error message file
o
DEMO.FOR--a sample program
Terminals Supported
IGL is configured with the following device drivers:
4110 Series terminal driver (supports the 4110 Series
terminals -- the 4112, 4113, 4114, 4115, and 4116 terminals).
4014 terminal driver (supports the 4014, 4015 and 4016 graphics
terminals with the Enhanced Graphics Module).
4105 terminal driver (supports the 4105 graphics terminal; for
the 4107 and 4109 terminals, use the 4113 device driver).
4662 plotter driver (supports the standard 4662 _plotter and the
eight-pen 4662 Option 31).
Integer Size
IGL has been installed using 32-bit integers. All IGL routines
using integer arguments must be passed 32-bit integers. You may
compile your application with the STORAGE(INTEGER*4) compiler
control or explicitly declare all integers passed to IGL routines
as INTEGER*4.
4170 INSTRUCTION
Rev, Apr 1984
7-75
SECTION 7
Progr~mming
Information
Logical Unit Numbers
IGL may use FORTRAN logical unit numbers 10 through 17 for file
processing. You should not attempt to use these unit numbers in
your progr~ms.
File Names
IGL expects file names used by HFOPEN (Host File Open) to be
exactly six characters long, starting with an alphabetic
character. Lower case letters are acceptable. The file name
supplied to HFOPEN must not have an extension - HFOPEN appends an
extension of ".DAT" to the file name.
File Types
IGL for the 4170 does not support file format 6 - random
read-only file. You must use file format 5 - random read/write
file. If you port progr~ms from an IGL host I/O package that
supports random read-only files, you must change the calls to
HFOPEN to use format 5.
Error Message File
IGL is shipped with an error message file. You may call the IGL
routines REPORT and CHECK to get the latest error reported by IGL.
These routines open a disk file with the CP/M-86 name ERRFIL.DAT.
If you use REPORT or CHECK, be sure the file is in your user
number or in user number 0 with a SYS attribute.
7-76
Rev, JVIar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
USING IGL WITH A HARD DISK
Setup for Hard Disk Operation
When you receive IGL, FORTRAN, and the 4170 Operating System, you
get these programs on flexible diskettes. To make working with
IGL more convenient, put the following files (using PIP) in User
o of the hard disk:
ED. C~1D
RUN. CND
FORT86.LTL
LINK86.LTL
IGLA.LIB
IGLB.LIB
CEL87.LIB
F86RNO.LIB
F86RN1.LIB
F86RN2.LIB
F86RN3·LIB
F86RN4.LIB
EH87.LIB
8087.LIB
LARGE. LIB
Use the STAT utility to change all of these file attributes to
SYS (so they may be referenced from any other user number).
Put the file DEf·W.FOR in a user number of your choice.
Oompiling an IGL FORTRAN Application Source File
After you have created an IGL FORTRAN 77 source file (or would
prefer to use DEMO. FOR as a source file) you will need to compile
it with the FORTRAN-86 compiler. The compiler accepts your
application source file as input and produces a relocatable
object file suitable for linking with the IGL library files,
IGLA.LIB and IGLB.LIB.
To compile your source program, type the following:
RUN FORT86 myprog.FOR NOTYPE NOLIST STORAGE(INTEGER*4)
means "press the RETURN key". MYPROG is the name of your
source file (it could be DEMO).
4170 INSTRUCTION
Rev, Mar 1984
7-77
SECTION 7
Programming Information
When the compiler is finished, it outputs a message to the
terminal specifying how many errors and warnings it found in
your source file. If the compiler message says you have any
errors or warnings you can use the TYPE command to examine the
myprog.LST file that the compiler creates. You can locate your
error or warning messages in this file. If your source file
produces no errors, you are ready to link myprog.OBJ, the object
module file that the oompiler produced.
NOTE
During compilation, FORTRAN-86 creates and uses
several temporary "work files", deleting them
when compilation is complete. Because of this,
you should make certain that you have from 60K
to 80K free file space for a modest application
program.
Linking Your IGL FORTRAN Object File
Once you have successfully compiled your source file, you are
ready to link myprog.OBJ with the IGL and FORTRAN-86 library
files. Enter the following command:
RUN LINK86 myprog.OBJ,IGLA.LIB,IGLB.LIB,CEL87.LIB,&
or
RUN DEMO
This completes the set-up instructions for those 4170's with a
hard disk.
4170 INSTRUCTION
Rev, Mar 1984
7-79
SECTION 7
Programming Information
IGL WITH PLEXIBLE DISKETTES
Setup for Flexible Diskette Operation
When you receive IGL, FORTRAN and the 4170 Operating System, you
get each of these programs on flexible diskettes. To make
working with IGL convenient, you should use the PIP utility (with
the [OV] options) to redistribute the files on working diskettes
as follows:
NOTE
Whenever you change disks, you must log in
the new disk by typing CTRL-C.
1.
Put these files on Work Disk 1.
FORT86.LTL
RUN. CMD
2.
Put these files on Work Disk 2.
CEL87.LIB
IGLA.LIB
IGLB.LIB
Copy the DErI[O.FOR program from the distribution medium to
this disk (or place your own IGL application program on this
disk) .
3·
Put these files on Work Disk 3.
LINK86.LTL
RUN. CMD
F86RN3.LIB
F86RN4.LIB
8087.LIB
LARGE. LIB
4.
Put these files on Work Disk 4.
F86RNO.LIB
F86RN1 . LIB
F86RN2.LIB
EH87.LIB
7-80
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Compiling an IGL FORTRAN Application Source File
After you have created an IGL FORTRAN 77 source file (such as
DEMO.FOR) you will need to compile it with the FORTRAN-86
compiler. The compiler accepts your application source file as
input and produces a locatable object file suitable for linking
with the IGL library files, IGLA.LIB and IGLB.LIB.
Use this sequence of steps to compile your FORTRAN source
file:
1.
First make sure that the Work Disk 1 is in Drive A, Work Disk
2 is in Drive B and that both have been logged in. Assign
drive A to be the current drive (the prompt on the screen
will be A». Make certain that the disk drive latches are
closed.
2.
To compile your source file, type the following:
RUN FORT86 B:myprog.FOR NOTYPE NOLIST STORAGE(INTEGER*4)
After you press RETURN, the compiler runs for a length of
time that depends on the size of your source file. When the
compiler is finished, it outputs a message to the terminal
specifying how many errors and warnings it found in your
source file. If the compiler message indicates you have any
errors or warnings, you can use the TYPE command to examine
the myprog.LST file (on work Disk 2) that the compiler
creates. You can locate your error or warning messages in
this file. If your source file produced no errors or
warnings, you are ready to link myprog.OBJ, the object module
file that the compiler created.
NOTE
During compilation, FORTRAN-86 creates and
uses several temporary "work files", deleting
them when compilation is complete. Because
of this, you should make certain that the working
disk (in this example - Work Disk 1) has from
60K to 8DK free file.space~
Linking Your IGL FORTRAN Object File
Once you have successfully compiled your source file, you are
ready to link myprog.OBJ with the IGL and FORTRAN-86 library
files. Due to the diskette space limitations, the linking must
be done in two steps.
4170 INSTRUCTION
Rev, Mar 1984
7-81
SECTION 7
Programming Information
The following is a sequence of steps you can use to link
myprog.OBJ:
1.
Be certain that Work Disk 2 is still in Disk Drive B.
2.
Put Work Disk 3 in Drive A.
Assign to drive A (the prompt on
the screen will be A». Log in the drive by typing CTRL-C.
3·
To run the first link step, type in:
RUN LINK86 b:myprog.OBJ,B:IGLA.LIB,B:IGLB.LIB,B:CEL87.LIB &
to myprog.LNK PURGE NOMAP
NOTE
When the linker is finished, you will see the
following message:
WARNING 12: UNRESOLVED SYMBOLS
The linker outputs this message whenever you do a
two or more step linking job.
The unresolved
symbols should be resolved upon completion of the
final stage in the link job.
4.
After LINK86 creates the myprog.LNK file, remove Work Disk 2
from Disk Drive B and replace it with Work Disk 4.
Log Work
Disk 4 in by making the current drive B, then type in CTRL-C.
You will see the prompt B>.
Set Drive A to be the current
drive.
You will see the prompt A>.
5.
To run the second link step, type in:
RUN LINK86 myprog.LNK,B:F86RNO.LIB,B:F86RN1.LIB,B:F86RN2.LIB,&<
F86RN3.LIB,F86RN4.LIB,B:EH87.LIB,8087.LIB,LARGE.LIB TO &(CR)
B:myprog.LTL BIND PURGE NOMAP(CR)
Note the use of the ampersand character (&) to specify to the
linker that you have a continuation line.
Be sure to specify
Disk Drive B (B:) as shown above.
This causes the linker to
search the correct disk for the files.
ERROR 3: I/O ERROR
?Except1on 0029h too many entries in directory
7-82
Rev, Mar
1984
4170 INSTRUCTION
SECTION 7
Programming Infqrmation
This is an error message from CP/M-86. If you see it while you
are attempting to carry out one of the steps detailed above, a
likely cause is that your application program is too large to be
compiled and/or linked on a system with flexible diskettes as the
only storage medium. In this case the message should not be
taken literally but rather as an indication that diskette storage
capacity has been exceeded.
Running Your IGL FORTRAN Program
When you have successfully created myprog.ltl, you can execute
the .LTL file with the RUN.CMD file, a load-time locatable
program loader.
To load and run the linked FORTRAN object file myprog.ltl (or
demo.ltl if you have compiled and linked demo.for), enter the
command:
RUN B:myprog
or
RUN B:demo
4170 INSTRUCTION
Rev; Mar 1984
7-83
SECTION 7
Programming Information
GSX-86
INTRODUCTION
GSX~86
is a device-independeht graphics system fdr CP/M-86.' It
is provided to you on two diskettes. In aQdition to the
diskettes, you should have the GSX-86 Graphics Extension
Programmer's Guide that describes GSX-86 in';,detail.
---=::;;--,-----,._-----.
'
You should use the programmer's guide as the primary
documentation for GSX-86. This section describes the contents of
the GSX-86 diskettes, the FORTRANGSX~86 interface, how to run
the demonstration program, the extensions for advanced alpha
text-editing features, and device-specific information for the
Tektronix device drivers.
Diskette Contents
,
'.
Your GSX-86 diskettes contain these files:
o
GRAPHICS.CMD--this file enables GSX-86 and loads the
defaul t device driver.
" .,
o
ASSIGN.SYS--this is a sample device driver assignment table
file.
o
DD41XX.SYS--device driver for Tektronix 4100 Series
terminals (4105, 4107, 4109, 4112, 4113, 4114, 4115, and
4116); the 4112, 4113, and 4115 must have firmware version 6
or higher.
o
DD466X.SYS--device driver for Tektronix 4662/4663 plotters
(including the 4662 with the 8-pen Option 31).
o
GSX86.A86--assembly language source of the FORTRAN-toGSX-86 interface subroutine.
o
GSX86.0BJ--assembled object code of GSX86.A86.
o
GSXLIB.DOC--a documentation file for GSXLIB.FOR and GSXLIB.LIB.
o
GSXLIB.FOR--the FORTRAN source code.
o
GSXLIB.LIB--an object library of the FORTRAN source code.
o
GSXDEMO.FOR--a short GSX-86 demonstration program (this
program is used as an example later in this section).
7-84
Rev,Mar1984
,.
4170 INSTRUCTION'
SECTION 7
Programming Information
NOTE
On one of the GSX-86 diskettes are the
Tektronix-written device drivers DD41XX.SYS
and DD466X.SYS. This diskette also includes
some device drivers not written by Tektronix
that are included for your convenience. These
device drivers are provided "as is," without
warranty of any kind, either expressed or
implied, including, but not limited to, the
implied warranties of merchantability and
fitness for a particular purpose.
G81-86 FORTRAN IITERFACE
The files GSX86.A86 (source) and GSX86.0BJ (assembled object code)
contain a FORTRAN callable subroutine that enables a FOR~RAN program
to communicate directly with GSX-86. The calling
sequence for this subroutine is:
Call GSX86 (contrl, intin, ptsin, intout, ptsout)
where contrl, intin, ptsin, intout, ptsout are all integer*2 arrays.
NOTE
The arrays contrl, ptsin, and ptsout must be
explicitly declared as integer in FORTRAN.
These names are used for compatibility with
the GSX-86 Graphics Extension Programmer's
Guide.
The virtual device specification contained in the GSX-86
Graphics Extension Programmer's Guide describes the use of
these integer arrays. The fil e GSXLIB. }I'OR provides examples
using this subroutine to access most of the features of GSX-86.
The file GSXLIB.1IB is a library of the subroutines in GSXLIB.FOR
plus the interface subroutine GSX86.A86. A brief description of
each subroutine is in the file GSXLIB.DOC.
4170 INSTRUCTION
Rev, Mar 1984
7-85
SECTION 7
Programming Information
AN EXAMPLE: COMPILING, LINKING, AND RUNNING THE
DEMONSTRATION PROGRAM
The file GSXDEMO.FOR is a short, FORTRAN demonstration program
that uses the GSXLIB subroutines. It is first necessary to
compile the source program by typing the command:
RUN FORT86 GSXDEMO.FOR
Next, the object code produced by the compiler must be linked
with the GSXLIB subroutines and the FORTRAN run-time libraries.
Type the command:
RUN LINK86 GBXDEMO.OBJ, GBXLIB.LIB, CEL87.LIB, F86RNO.LIB, &
P86RN1.LIB, F86RN2.LIB, F86RN3.LIB, F86RN4.LIB, EH87.LIB, &
8087.LIB, LARGE.LIB TO GSXDEMO.LTL PURGE BIND NOMAP
This produces the file GSXDEMO.LTL.
NOTE
Use the STREAM or QS programs (supplied on
the Program Exchange diskette) to simplify
link operations with GSX-86. Type out the
STREAM.DOC or the QS.DOC files for more
information on how to use these programs.
Before the demonstration can be run, it is necessary to enable
GSX-86 by typing the command:
GRAPHICS
The GRAPHICS command reads in the default device driver (the
first one listed in the table in ASSIGN.SYS) and loads the
Graphics Device Operating System (GDOS). (See the Digital
Research manual, the GSX-86 Graphic Extension Programmer's
Guide.) The ASSIGN.SYS file furn"isheaon tfie crSX:.:s6OTsKettes
uses-the Tektronix 4100 series driver DD41XX.SYS as the default.
(These files must be on the current disk.)
Now, run the demonstration program by typing:
RUN GSXDEMO
The program displays menus and is self-explanatory.
7-86
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
TEKTRONIX EXTENSIONS TO GSX-86
GSX-86 provides the ESCAPE function to support device-dependent
features. Some ESCAPE functions are predefined to support
features found only in CRT terminals such as alpha cursor
addressing. ESCAPE functions 51-99 are available for extensions.
Tektronix has added 17 extensions (functions 51-68) that improve
performance of applications which involve lots of text-editing
and support the color features available in Tektronix terminals.
These functions are described in the following paragraphs. Alpha
cursor positioning and these extensions are not available when a
4114 or 4116 is used. The extensions are presented by function
number. The following list is an alphabetical listing of the
Tektronix extensions.
Extension Name
Escape Function Id
BOLD RENDITION ON
CLEAR HORIZONTAL TAB
DELETE CHARACTERS
DELETE LINES
INQUIRE ADVANCED EDITING FEATURES
INQUIRE ALPHA TEXT COLOR REPRESENTATION
INSERT CHARACTERS
INSERT LINES
INSERT MODE OFF
INSERT MODE ON
SCROLL DOWN
SCROLL UP
SET ALPHA TEXT COLOR INDICES
SET ALPHA TEXT COLOR REPRESENTATION
SET DEFAULT GRAPHICS RENDITION
SET HORIZONTAL TAB
SLOW BLINK ON
UNDERLINING ON
67
59
57
4170 INSTRUCTION
53
51
66
54
52
56
55
61
60
64
65
63
58
68
62
Rev, Mar 1984
7-87
SECTION 7
Programming Information
Inquire Advanced Editing Features
This extension returns availability of advanced features to
application program.
Input
contrl (1 )
contrl(2)
contrl(6)
Output
contrl(3)
contrl(5)
intout(1 )
intout(2)
intout(3)
intout(4)
intout(5)
intout(6)
intout(7)
intout(8)
intout(9)
intout(10)
7-88
5
Indicates ESCAPE function
°51
. Escape function id
o
12 Number of data items returned in Intout
INSERT LINE capability,0::::no,1::yes
DELETE LINE capability,0=no,1=yes
INSERT CHARACTERS capability,0=no,1=yes
INSERT MODE, =0 (no insert mode),1=yes
DELETE CHARACTERS capability,0=none,1=yes
HORIZONTAL TABS, =
(none),1=yes,setable,
n>1 (yes, but fixed at multiples of n columns)
SCROLL UP capability,0=no,1=yes
SCROLL DOWN capability,0=no,1=yes
GRAPHIC RENDITION FEATURES (e.g. reverse video,
underlining, bold, and blink)0=no,1=jes
ALPHA TEXT COLOR CAPABILITY
= 0 no' colors availab-le (monochrome device)
= 1 colored text available, but ail
characters on the screen must be the
same color, can't be changed on a
character by character basis (such
as Tektronix 4112, 4113 and 4115)
= 2 colored text available, and can be
changed on a character by character
basis (such as Tektronix 4105,4107
and 4109)
°
intout (11 )
NUMBER OF COLORS AVAILABLE FOR ALPHA TEXT
:= 2
monochrome (black and white)
> 2 color (note: number of colors for
alpha text may be less than number of
colors available for graphics (such as
the 4115)
intout(12)
SEPARATE ALPHA TEXT COLOR MAP
:= 0
color map for alpha text is the
same as for graphics (Tektronix
4112,4113 and 4115)
=
separate alpha text color map
(4105,4107,4109)
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Insert Lines
Thi~
routine inserts blank lines at the current cursor position.
Input
contrl(1 )
contrl(2)
contrl(6)
intin(1)
Output
contrl(3)
5
o
ESCAPE function opcode
52
function id
number of lines to insert
o
Delete Lines
This routine deletes the line containing the cursor and possibly
following lines if specified.
Input
contrl(1 )
contrl(2)
contrl(6)
intin( 1 )
Output
contrl(3)
5
o
ESCAPE function
53
function id
number of lines to delete
o
Insert Characters
This routine inserts the requested number of blank character
cells at the current cursor position. Text previously at the
cursor position is moved to the right and any characters shifted
beyond the right.margin are lost. The cursor position remains
the same.
Input
contrl(1 )
contrl(2)
contrl(6)
intin( 1 )
Output
contrl(3)
4170
INS~RUCTION
5
o
ESCAPE function
54
function id
number of blank characters to insert
o
Rev, :Mar 1984
7-89
SECTION 7
Programming Information
Insert Mode On
This routine causes the text at and following the current curSOr
position to be moved to the right when a character is received.
Any text shifted beyond the right margin is lost.
Input
contrl ( 1 )
contrl(2)
contrl(6)
5
o
55
contrl(3)
o
Output
ESCAPE function
function id
Insert Mode Off
This routine causes the received character to replace the character
at the current cursor position. It resets the effects of
INSERT MODE ON.
Input
contrl ( 1 )
contrl(2)
contrl(6)
Output
contrl(3)
5
ESCAPE function
56
function id
o
o
Delete Characters
This routine deletes the character at the current cursor position
and, if specified, characters following the cursor. Text
following the deleted characters is shifted to the left to fill
in the gap. Only characters on the current line are affected;
the cursor position is left unchanged.
Input
contrl ( 1 )
contrl(2)
contrl(6)
intin( 1 )
Output
contrl(3)
7-90
5
o
ESCAPE function
57
function id
number of characters to delete
o
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Set Horizontal Tab
This routine sets a tab stop at the current cursor position.
Input
contrl( 1 )
contrl(2)
contrl(6)
Output
contrl(3)
5
ESCAPE function
58
function id
o
o
Clear Horizontal Tab
This routine clears the tab stop at the current cursor position
or all tab stops.
Input
contrl ( 1 )
contrl(2)
contrl(6)
intin( 1 )
Output
contrl(3)
5
o
ESCAPE function
function id
59
1 to clear stop at current cursor position
2 to clear all tab stops
0
Scroll Up
This routine scrolls the alpha text region up. Blank lines are
inserted from the bottom and lines scrolled off the top are lost.
The alpha cursor maintains its position relative to the scroll,
but does not scroll up past row 1 (it never leaves the screen).
Input
contrl( 1 )
contrl(2)
contrl(6)
intin( 1 )
Output
contrl(3)
4170 INSTRUCTION
5
o
ESCAPE function
60
function id
number of lines to scroll
o
Rev, Mar 1984
7-91
SECTION 7
Programming Information
Bcroll Down
This routine scrolls the alpha text region down. Blank lines are
inserted from the top and lines scrolled off the bottom are lost.
The alpha cursor retains its position relative to the scroll, but
does not scroll off the bottom of the screen.
Input
contrl(1 )
contrl(2)
contrl(6)
intin( 1 )
Output
contrl(3)
5
o
ESCAPE function
61
function id
number of lines to scroll
o
Underlining On
This routine causes an underline to be drawn under all received
characters.
Input
contrl(1 )
contrl(2)
contrl(6)
o
contrl(3)
o
Output
7-92
5
ESCAPE function
62
function id
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Set Default Graphics Rendition
This routine turns off graphics renditions such as reverse video,
underlining, bold, and blink (giving no blink, no underscore, no
bold, positive video).
Input
contrl(1)
contrl(2)
contrl(6)
Output
contrl(3)
5
ESCAPE function
63
function id
o
o
Set Alpha Text Color Indices
This routine sets the color indices to be used for subsequent
characters. The wipe index value is the color of the alpha
screen when it is erased.
Input
contrl( 1 )
contrl(2)
contrl(6)
intin (1)
intin (2)
intin (3)
Output
contrl(3)
ESCAPE function
5
o
64
function id
character foreground index or -1 to not change
character background index or -1 to not change
dialog area wipe index or -1 to not change
o
NOTE
Some terminals cannot change the alpha text
character colors character by character (for
example, on the Tektronix 4110 series
terminals). On these terminals, this escape
function causes all text on the screen to be
changed to the specified indices.
4170 INSTRUCTION
Rev, Mar 1984
7-93
SECTION 7
Programming Information
Set Alpha Text Color Representation
This routine maps the specified color index to the color
specified in RGB. If the alpha text color representation and the
graphics color representations are the same, this command changes
both alpha and graphics representations.
Input
contrl(1 )
contrl(2)
contrl(6)
intin(1)
intin(2)
intin(3)
intin(4)
Output
contrl(3)
5
o
ESCAPE function
function id
65
color index
red color intensity (in tenths of a percent,
0-1000)
green color intensity (0-1000)
blue color intensity (0-1000)
o
Inquire Alpha Text Color Representation
This routine returns the representation of the specified index in
RGB units.
Input
contrl (1 )
contrl(2)
contrl(6)
intin( 1 )
Output
contrl(3)
intout(1)
intout(2)
intout(3)
intout(4)
7-94
5
o
ESCAPE function
function id
66
requested color index
o
color index
red intensity (in tenths of a percent, 0-1000)
green intensity (0-1000)
blue intensity (0-1000)
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Bold Rendition On
This routine causes subsequent alpha characters to be displayed
in color index 1.
Input
contrl( 1 )
contrl(2)
contrl(6)
Output
contrl(3)
5
ESCAPE function
67
function id
o
o
NOTE
On the Tektronix 4112 terminal, color index 5
is used instead of 1. Bold is turned off by
the Select Default Rendition escape function
(63).
Slow Blink On
This routine causes subsequent alpha characters to blinked slowly
on and off.
Input
contrl(1 )
contrl(2)
contrl(6)
Output
contrl(3)
5
o
ESCAPE function
68
o
DEVICE-SPECIFIC INFORMATION (FOR TEKTRONIX DEVICE DRIVERS)
Table 7-2 describes the device driver DD41XX.SYS and Table 7-3
describes the device driver DD466X.SYS.
4170 INSTRUCTION
Rev, Mar 1984
7-95
SECTION 7
Programming Information
Table 7-2
DEVICE DRIVER DD41XX.SYS INFORMATION
------------------------------------------------------ -----~----
: Characteristic
: Description
: Filename
: DD41XX.SYS
Terminals Supported
The TEKTRONIX 4105, 4107, 4109, 4112,
4113, 4114, 4115, and 4116. Firmware
version number 6 and higher is
required for the 4112, 4113, 4114,
4115, and 4116 terminals.
Device Index
: In the ASSIGN.SYS file included on the
: GSX-86 diskette, this driver is
: assigned index (workstation id) 1.
Escapes
: Cursor positioning, editing, and
: color. Escapes are not supported for
: the 4114 and 4116.
---------------------------------------------------------------Color
7-96
The 4114 and 4116 support only two
indices, O=background and 1=green;
indices greater than 1 are taken as
index 1. These may not be redefined.
The 4105 has 8 colors for graphics and
a separate 8 colors for dialog
characters. The 4107 and 4109 have 16
colors for graphics and 8 for dialog
characters. The number of colors
available on the 4113 and 4115 depends
on the number of bit planes of display
memory installed. Color indices 0-7
are mapped according to the
specification given in Appendix B of
the GSX-86 Programmers Guide; indices
greater than 7 map to the terminal
index. Color representation can only
be set and inquired upon for indices
from 0-15. On the 4112, the indices
0-7 map to the terminal's gray scale
values. It is possible to change the
default gray scales using the set
color representation function.
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Table 7-2 (cont)
DEVICE DRIVER DD41XX.SYS INFORMATION
I Characteristic
I Description
Graphic Input (GIN)
Two input devices are available: the
thumbwheels (or joydisk) and an
optional graphics tablet (except the
tablet is not available on the 4105).
For the 4107 and 4109, the 4957
graphics tablet must be connected to
the terminal's port p1.
I Generalized Drawing lOne GDP is available:
I Primitives (GDPS)
I
1=bar
Text
Continuous text scaling and rotation
is available, except for the 4105
which has a limited number of
character sizes and rotation in 90
degree increments only.
-----------~------------------------------------------ ----------
Linestyles
Fill Patterns
Eight linestyles are available (these
are the terminal linestyles).
Linestyle 1 is SOlid, and 2-8 are
combinations of dots and dashes.
I
I
I
I
Only "hollow" is available on the 4114
and 4116. On the other terminals, 16
patterns are available (these are the
terminal fill patterns).
I
I
I Markers
4170 INSTRUCTION
I Ten marker types are available.
Rev, Mar 1984
7~97
SECTION 7
Programming Information
Table 7-3
DEVICE DRIVER DD466X.SYS INFORMATION
i Characteristic
i Description
i
: DD466X.SYS
Filename
Device Index
Communications
The actual device index is determined
by the value used in the file
ASSIGN.SYS. For plotters, values
between 11 and 20 are recommended.
In
the ASSIGN.SYS furnished, index 11 is
used.
:
:
:
:
:
:
:
:
:
:
:
:
i
I
:
:
:
:
i
:
:
:
:
:
:
:
:
:
7-98
Rev, Nar 1984
The CP/M-86 logical devices AXI:
(auxiliary input) and AXO: (auxiliary
output) are used.
The CONFIG or
SETDEV utility should be used to set
one of the peripheral ports to the
CP/M-86 AXI and AXO logical device
with the proper baud rate.
The
maximum baud rate is 1200 for the 4662
and 9600 for the 4663.
The 4662 rear
switches should be set so that the GIN
terminator is CR (carriage return),
the device address is A, and DEL
IGNORE is NO; the baud rate, parity
and stop bits should be the same as
the corresponding 3PPI terminal
settings. For example: 0223 for 1200
baud, no parity, and 2 stop bits.
The
4663 parameter entry card should be
set for attention character = ESC,
serial address = A, command/response
format = 1, output terminator = CR,
and DEL IGNORE off.
The other serial
communications settings should be set
according to the terminal's values.
If Option 36 Media Advance is
installed, a Clear Workstation
function advances the paper when roll
mode is selected.
4170 INSTRUCTION
SECTION 7
Programming Information
Table 7-3 (cont)
DEVICE DRIVER DD466X.SYS INFORMATION
i Characteristic
i Description
Graphic Input
Colors
4170 INSTRUCTION
The only available device is the
joystick (default). On the 4662, the
prompt light is turned on when an
Input Locator function is called. A
point inserted by pressing the CALL
button momentarily (not held down
until it beeps). On the 4663, the
DRAW POINT light blinks on and off
during GIN. Either the MOVE POINT or
DRAW POINT button may be used to enter
a GIN point. The Input Locator
function returns a locator terminator
which has the value 32 if the plotter
pen is up during a GIN (or the MOVE
POINT button was hit on a 4663), or 33
if the pen is down (or the 4663 DRAW
POINT was hit).
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
Color index 0 is the background and is
never plotted. Indices greater than 0
map to a pen station: index 1
corresponds to pen station 1, index 2
to station 2, etc. One pen station is
available on a 4662, eight on a 4662
equipped with Option 31, and two on a
4663. When an index greater than the
highest available pen station is
specified, a message is printed on the
terminal requesting the operator to
load the pen corresponding to the
specified index and enter the pen
station number used (when more than
one station is available).
Rev, Mar 1984
7-99
SECTION 7
Programming Information
Table 7-3 (cont)
DEVICE DRIVER DD466X.SYS INFORMATION
-----------------------~------------------------------ ----------
: Characteristic
I Description
Line Styles
On a 4662, only one linestyle (solid)
is available. On a 4663, there are
four linestyles available in addition
to solid.
I Generalized Drawing lOne GDP is available:
: Primitives
I
1 -Bar (hollow only)
: Escapes
I
I
: Only escape 1--InCluire Addressable
: Character Cells-- is available.
I
I
: Continuous text scaling and rotation
: is available.
I
I
: 2:"+", 3:"*", 4:"0", and 5:"X".
: Text
---------------------------------------------------------------: Markers
: Five markers are available: 1:".";
7-100
Rev, Nar 1984
4170 INSTRUCTION
SECTION 7
Programming Informat·ion
DTI
The Direct Terminal Interface (DTI) for the 4170 is a set of
FORTRAN-86 subroutines that support the features of 4100 Series
terminals. Every 4100 Series terminal command has a
corresponding DTI routine.
The DTI is useful for applications that use the special features
of the Tektronix 4100 Series terminals (the 4105, 4107, 4109,
4112, 4113, 4114, 4115, and 4116). (GSX-86 is recommended for
applications that use other graphics devices, including
non-Tektronix devices for which a GSX-86 device driver is
available. Plot 10 IGL provides a device-independent set of
subroutines that provide higher-level graphics functions compared
to the DTI and GSX-86, and that support Tektronix graphics
devices. See the previous discussions of IGL and GSX-86.)
The FORTRAN source code is contained in the files FDTIA.FOR,
FDTIB.FOR, and FDTIC.FOR; CHARIO.A86, which is in Intel
assembly language, provides character input and output for DTI
subroutines. All these files are on the DTI/BIOS Source disk.
The file FDTI.LIB (on one of the FORTRAN diskettes) is an object
library of the FORTRAN source files.
USING THE DTI ON THE 4170
The discussion here summarizes the differences between using DTI
on a 4170 and using the DTI supplied with 4100 Series Local
Programmability. The 4110 Series DTI Programmers Reference
Manual, which is included with the Tektronix 4010C01 pLOT 10
IGL Users Manual, describes the use of the DTI supplied with
4TOQ-series Local Programmability. This discussion focuses on
4170 DTI and how it differs from 4100 Series DTI.
The principal difference between 4170 DTI and 4100 Series Local
Programmability DTI is how graphic input (GIN) reports and
terminal status and settings reports are handled. This is
discussed in more detail in the remainder of this section.
Another difference is that certain routines may not be present or
may cause undesirable results during execution, depending on the
type of 4100 Series terminal you are using. (This is because of
the differences in terminal features and is not the fault of 4170
DTI.) Table 7-4, which follows, charts the compatibility of
certain 4170 DTI routines against the various 4100 Series
terminals.
4170 INSTRUCTION
Rev, Mar 1984
7-101
SECTION 7
Programming Information
You should call the DTI routine LLINIT (DTI-Initialize) before
any other DTI routine. LLINIT initializes terminal
communications parameters (such as the EOL string, the
report-EOM-frequency, and the transmit delay), and it determines
and returns the terminal type. The terminal is then left in
Select Code TEK.
NOTE
The GIN decoding routines (LLGTGN, LLGTG4,
and LLGT10) will not work properly if the EOL
string is set to other than or if the
report-EOM-frequency is set to less frequent.
It is also recommended that you set the
transmit delay to a non-zero value. (LLINIT
initializes the EOL string to , the
report-EOM-frequency to more frequent, and
the transmit delay to 50 ms, so that the GIN
decoding routines should work properly.)
TERMINAL MODES
The DTI routines described in the 4110 Series DTI Programmers
Reference Manual do not set terminal modes. For example,
LLMOVE (move) does not cause the terminal to enter Vector mode.
This is not the most efficient way to send graphics information
to the terminal. For applications that send thousands of
vectors, there is a significant speed improvement when optimized
4014-style graphics are used.
Your 4170 DTI contains the routines LLMV14 (ix,iy) and LLDR14
(ix,iy), which do optimized graphics. LLMV14 causes the terminal
to enter Vector mode and must be called before LLDR14. To exit
Vector mode, use the DTI routine LLAMOD (DTI-Set-Alpha-Mode).
Markers may be drawn by first calling LLMMOD (DTI-Set-MarkerMode), followed by a sequence of LLDR14 for the remainder of
the markers. LLAMOD should be used to exit Marker mode.
7-102
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Most 4100 Series terminals are capable of understanding ANSI
X3.64 alpha editing escape sequences. (These include alpha
functions, such as cursor positioning, and deleting and inserting
characters, as well as visual attributes, such as underlining and
reverse video.) These escape sequences are not compatible with
4100 Series escape sequence commands. The command LLCODE (SelectCode) instructs the terminal to interpret escape sequences
according to either ANSI X3.64 standards or 4100 (TEK) format.
Because the DTI does not support the ANSI X3.64 escape sequences,
these can be sent using FORTRAN WRITE statements after LLCODE
places the terminal in ANSI X3.64 mode; the terminal must then be
put back into Select Code TEK before DTI routines can be used.
(LLINIT also sets Select-Code TEK.)
Graphic Input
Only 4010-style Graphic Input (GIN) is available on the 4105
terminal and only one point can be enabled at one time. Here is
a simple GIN input example using the DTI:
C * Example GIN for the 4105
Character*1 Keychr
Call Llinit (iterm)
C * enable 4010 style GIN using the joydisk
Call Llgn10
C * read the report from the terminal
Call Llgt10 (Keychr,Jx,Jy)
C * print out the results
Call Llmove (0,2850)
Write (6,10) Keychr,Jx,Jy
10
Format ('The key hit was "' ,A1, "', at the point:' ,15,
$
2x,I5)
End
Note that no signature characters can be defined for the
4105. Also, LLGT10 should be called once after each LLGN10.
4170 INSTRUCTION
Rev, Mar 1984
7-103
SECTION 7
Programming Information
For the other 4100 terminals, more than one point can be input at
a time, and segment picking and tablets can be used; because GIN
has more options, the GIN commands can be more complex. The DTI
routines LLENGN (Enable-GIN) and LLGTGN (DTI-Get-GIN-Report) are
used with 4100-style GIN. When GIN is enabled for more than one
point, the report signature characters should be set to non-null
values. This short program illustrates the process:
C * A simple etch a sketch GIN Demo Program
Character*1 Keychr, Sigchr
Call Llinit (iterm)
If (iterm.eq.4105) Stop '***cannot do this on a 4105'
C * Make a little dialog area
Call Lldaen (1)
Call Lldavs (0)
Call Lldaln (4)
Call Lldacl
Call Lldavs (1)
C * Set signature characters to "s" and "E"
Call Llrpsg (-1,83,69)
C * Enable rubberbanding from the gin display start point
Call Llrbgn (0,2)
C * Move the beam, the graphics cursor, and the gin-displayC *
start-point to about the middle of the screen
Call Llmove (2000,1000)
Call Lltnsg (0,2000,1000)
Call Llspgn (0,2000,1000)
C * Enable joydisk (or thumbwheel) gin for 100 points
Call Llengn (0,100)
C * If key "M" or "m", do a move; if "s" or "s", disable GIN
C * (and wait for the terminating-GIN-report); for any other
C * character, draw from the last point to the current point.
C *
100
Call Llgtgn (Sigchr,Keychr,Jx,Jy,Jsegno,Jpickid)
C *
C * Exit only when the terminating signature character is recei
If (Sigchr.eq.'E' .or. Sigchr.eq.'e') Go to 999
If (Keychr.eq. 'M' .or. Keychr.eq. 'm') Then
Call Llmove (jx,jy)
Else if (Keychr.eq.'S' .or. Keychr.eq.'s') Then
Call Lldsgn (0)
Else
Call Lldraw (Jx,Jy)
Endif
Go go 100
C * Exit
Print * , 'GIN Demo Over'
999
End
7-104
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
The DTI routine LLGTGN is only able to understand the GIN report
when GIN is enabled with LLENGN. The Report-EOM-Frequency must
be set to "more frequent"; this value is set by LLINIT.
The DTI routine LLCKGN (DTI-Check-for-GIN-Report) cannot tell
when a GIN-Report is waiting. It always returns a value of 1.
An application can read and parse GIN reports without using
LLGTGN.
NOTE
The GIN decoding routines LLGTGN and LLGTG4
do not correctly interpret terminal GIN
reports when the (Return) key is used to
enter a GIN report. can only be used
when known signature characters are used. A
user-written GIN decoding routine is
recommended if is used to enter GIN
reports.
Consult the programmers reference manual for your terminal for
more information on graphic input.
4170 INSTRUCTION
Rev, Mar 1984
7-105
SECTION 7
Programming Information
TERMINAL AND ROUTINE COMPATIBILITY
The 4170 DTIdoes n6t verify that the terminal used supports the
commands that are sent. It is the responsibility of the
applications programmer to avoid using 4170 DTI routines that the
target terminal cannot support.
Table 7-4 charts the compatibility of Tektronix 4100 Series
terminals against 4170 DTI routines. The entries in the columns
have these meanings:
blank
X
N
= The routine is not supported by that terminal.
= The DTI routine is present and useful for that
terminal.
= The routine is not supported by 4170 DTI, or
a no-op results.
= The routine supports 32-bit extended addressing;
on
other than a 4115, the coordinates must be 0-4095.
When 32-bit addressability is used on a 4115, the DTI
routine LLCORD (Set-Coordinate-Mode) should be used to
inform the DTI to use extended addressing and to send
the Set-Coordinate-Mode escape sequence to the 4115.
N/A = The compatibility question is not applicable; this is
used for some internal 4170 DTI routines.
E
In the "comments" column, the functional names of some 4170 DTI
routines are ~iven, followed by an asterisk (*). Routines with
the asterisk t*) are not documented in the 4110 Series DTI
Programmers Reference Manual; instead, you may look up tne
corresponding terminal command (under the functional name in the
"comments" column) in the terminal's programmers reference
manual. For example, for a description of the LLDNVM routine,
look up the "Define Nonvolatile Macro" command in the programmers
reference manual.
7-106
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Table 7-4
TERMINAL/4170 DTI COMPATIBILITY CHART
I DTI
I 4105 I 4107 I 4109 : 4112 : 4113 I 4114 : 4115 : Comments
:
:
:
:
I 4116 :
I
X
X
X
X
X
X
I Must be
I
I LLINIT Ii X
I
I called first. I
I
I
: Routine:
I Always
II LLCKGN:I
N
N
I LLSYNC:
N
N
N
N
N
N
N
I No-op
I LLGTFW I
N
N
N
N
N
N
N
I No-op
I LLKLFW I
N
N
N
N
N
N
N
I No-op
LLGTGN
X
X
X
X
X
X
X
Doesn't
if (CR)
is used
enter a
report
work
key
to
GIN
LLGTG4
E
E
E
E
E
E
E
Doesn't
if (CR)
is used
enter a
report
work
key
to
GIN
II LLGT10 II X
X
X
X
X
X
X
X
X
X
X
X
X
X
I LLGTRP I X
X
X
X
X
X
X
II LLKLRP II N
N
N
N
N
N
N
I LLGTCH:
X
X
X
X
X
X
X
I LLGTIN:
X
X
X
X
X
X
X
: LLGTXY:
X
X
X
X
X
X
X
I
N
N
N
N
: returns 1
I
I
I
LLXY10
I
N
I
70 INSTRUCTION
Rev, Mar 1984
I Gets a 4010
I GIN report
Not in 4100
Series DTI;
decodes 4010
xy-reports
I Not supported I
I on 4170 DTI
I
7-107
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
i DTI
I 4105 I 4107 I 4109 I 4112 I 4113 I 4114 I 4115 I Comments
I Routine:
I
:
I
I
I 4116 I
:
: LLGT14 I
E
E
E
E
E
E
E
I LLGTRL I X
X
X
X
X
X
X
LLABLK
X
X
X
X
: LLBFIL I
X
X
X
i LLBGCH :
X
X
X
X
X
X
: LLBHSG I
X
X
X
X
X
X
LLTB53
X
X
X
X
I LLEFIL :
X
X
: LLEGCH :
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
I LLBYPS : X
X
X
X
X
X
X
I LLMMOD:
X
X
X
X
X
X
X
I LLVMOD I X
X
X
X
X
X
X
I LLEMAC:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
: LLCLSG :
: LLAMOD I
X
I LLFRMT I
: LLTEXT :
7-108
X
X
Rev, Mar 1984
X
Requires
Option 13/14
(tablet
option)
X
X
: LLEPNL:
Requires
Option 01
(Half Duplex
& Block Mode)
X
X
X
4170 INSTRUCTION
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
: DTI
: 4105 : 4107 : 4109 : 4112 : 4113 : 4114 : 4115 : Comments
: Routine:
:
:
:
:
: 4116 :
:
: LLHCPY:
X
X
X
X
X
X
X
: LLIGDL:
X
X
X
X
X
X
X
: LLINSG :
X
X
X
X
X
X
: LLLFCR :
X
x
X
X
X
X
X
X
X
X
X
X
: LLLOAD :
: LLKBLK:
X
X
X
X
X
: LLVKLK I
X
X
X
X
: LLINPN :
X
X
X
X
X
X
X
X
X
X
X
X
X
I LLMOV4 : E
E
E
E
E
E
E
: LLMV14 :
X
X
X
X
X
X
X
LLPXCP
X
X
X
X
X
: LLMOVE:
X
X
: LLPXRP :
: 4105 requires
: pixel operaI tion ROMs
X
: LLPLOT :
X
X
X
X
X
X
--------------------------------------------------------------------------: LLPASG :
X
X
: LLPCPY :
: LLAPRM:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
: LLBLSG :
X
X
X
X
X
X
: LLBNSG I
X
X
X
X
X
X
X
X
X
X
: LLBPNL I
X
70 INSTRUCTION
X
Rev, Mar 1984
7-109
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
: DTI
: 4105 : 4107 : 4109 : 4112 : 4113 : 4114 : 4115 : Comments
: Routine:
:
:
:
:
: 4116 :
:
: LLBPN4:
E
E
E
E
E
E
LLBPX1
x
x
X
X
X
X
x
X
X
X
X
X
: LLOPSG :
: LLCNCL:
X
X
X
X
X
X
X
: LLDACL:
X
X
X
X
X
X
X
LLCOPY
X
X
X
X
X
X
X
: LLCRLF:
X
X
X
X
X
X
X
: LLDMAC:
X
X
X
X
X
X
X
LLDNVM
X
X
X
I LLDELF I
X
X
X
X
X
X
X
X
X
X
I LLDLSG I
I LLDLVW I
X
X
X
X
X
X
X
X
X
X
X
X
*
Available
devices are
terminal
dependent
I Define
I Nonvolatile
I Macro *
I LLDGCH I X
I LLDIR
I 4105 requires
I pixel operaI tion ROMs
X
X
X
This DTI routine is not documented in the 4110 Series DTI
Programmers Reference Manual. Refer to the programmers
reference manual for your terminal.
7-110
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
: DTI
: 4105 : 4107 : 4109 : 4112 : 4113 : 4114 l 4115 l Comments
l
Routine:
l
I I I
l
4116 l
l
I
L1DSGN
X
l
X
: 11DSMT :
X
X
X
X
X
X
X
X
l 11DRAW I X
X
X
x
X
X
X
l L1DRA4 I E
E
E
E
E
E
E
: L1DR14 l
X
X
X
x
X
X
X
I 11MRKR l X
X
X
X
X
X
X
l 11MRK4 l E
E
E
E
E
E
E
x
l L1REC4 l
X
X
X
X
X
x
X
X
X
X
X
X
X
X
X
lI L1GN10 Il X
X
X
l 11DAEN l X
~l
L1ENGN :
lI L1ENKE lI
I
I Enable Key
I Expansion *
I
I
X
X
X
x
X
X
X
X
X
X
I
I L1PROT I
11RASW
X
X
X
X
l Only style
I GIN for 4105
l 4105 requires
I
I
: 11RCFL:
X
I 11RENM :
*
X
X
X
X
X
X
pixel operation ROMs
X
X
X
This DTI routine is not documented in the 4110 Series DTI
Programmers Reference Manual. Refer to the programmers
reference manual for your terminal.
170 INSTRUCTION
Rev, Mar 1984
7-111
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
--------------------------------------------------------------------------I DTI
I 4105 I 4107 I 4109 I 4112 I 4113 I 4114 I 4115 : Comments
I Routine:
:
x
x
: LLRNSG I
I LLRNVW :
I
:
x
x
I
x
x
II LLQQRY II
I
: 4116 :
I
X
X
X
X
X
X
X
X
: Requires
I Option 09
Available
devices
terminal
dependent
I
LLJQRY
x
x
x
X
X
X
I LLKQRY:
X
X
X
X
X
X
X
: LLERRP I
N
N
N
N
N
N
N
X
X
X
X
I
I
I
I
I LLPTGN I
X
I Not supported I
I on 4170 DTI
I
------------------------------------------------------ --------------------~ I
I
LLPQRY
I
I
X
I
X
I
X
I
X
I
X
:
X
I LLSQRY I
X
X
X
X
X
X
I LLIQRY I
X
X
X
X
X
x
I LLST10 I
X
X
X
X
X
X
X
X
II LLHCRE II
I
X
I
I LLREST I
LLRUNW
X
X
X
X
X
X
X
X
X
X
I
I Requires
I Option 09
X
X
I 4105 requires
I pixel operaII tion ROMs
I
I LLRUN4 I
7-112
Rev, Mar 1984
E
4170 INSTRUCTION
I
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
: DTI
: 4105 : 4107 : 4109 : 4112 : 4113 : 4114 : 4115 : Comments
:
:
:
:
: 4116 :
:
: Routine:
x
: LLSAVE :
LLNVSV
x
x
x
x
x
x
: Save
: Nonvolatile
l Parameters *
x
l LLASZG l
: LLCODE:
X
X
X
X
X
X
l LLSFIL:
X
X
X
X
X
X
LLHCIN
X
X
X
X
X
X
X
X
X
X
X
X
X
: LLSLVW :
LLACI
X
4110
terminals
require
Option 09
l Set Alpha
: Cursor Index
*
II
: LLALSZ :
X
: LLBGCL :
X
X
: LLBGGR :
: LLBGIN :
: LLBAUD :
X
LLCBLK
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Requires
Option 01
(Half Duplex
& Block mode)
* This DTI routine is not documented in the 4110 Series DTI
Programmers Reference Manual. Refer to the programmers
reference manual for your terminal.
70 INSTRUCTION
Rev, Mar 1984
7-113
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
--------------------------------------------------------------------------: DTI
: 4105 : 4107 : 4109 : 4112 : 4113 : 4114 : 4115 I Comments
: Routine:
:
:
:
I
: 4116 :
:
LLEBLK
x
x
x
x
ReQuires
Option 01
(Half Duplex
& Block mode)
LLHBLK
x
x
x
x
ReQuires
Option 01
(Half Duplex
& Block mode)
LLBBLK
x
x
x
x
ReQuires
Option 01
(Half Duplex
& Block mode)
LLLBLK
x
x
x
x
ReQuires
Option 01
(Half Duplex
& Block mode)
LLMBLK
x
x
x
x
ReQuires
Option 01
(Half Duplex
& Block mode)
LLXBLK
x
x
x
x
ReQuires
Option 01
(Half Duplex
& Block mode)
LLPBLK
x
x
x
x
ReQuires
Option 01
(Half Duplex
& Block mode)
LLTBLK
x
x
x
x
: ReQuires
: Option 01
: (Half Duplex
I & Block mode)
x
x
: LLBORD :
'-114
x
Rev, Mar 1984
x
x
4170 INSTRUCTION
I
I·
I
I
I
I
I
I
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
: DTI
: 4105 : 4107 : 4109 : 4112 : 4113 : 4114 : 4115 : Comments
: Routine:
: 4116 :
: LLBKTM:
X
X
X
X
X
X
X
: LLBYCH:
X
X
X
X
X
X
X
: LLCHPA:
X
X
X
I
I
I
I
: LLHCDA :
I
X
I
I
: Set Character :
: Path "*
:
X
X
I
: Requires
: Option 09
---------~-------------------------------------------- ---------------------
: LLCLMD :
: LLHCSZ:
I
I
I
I
X
X
X
X
X
X
X
X
: Set Copy
: Size "*
: LLCORD :
X
: LLMTCL :
X
X
: LLDAAI :
: LLDABF:
X
X
X
: LLDACH :
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LLDACM
X
X
X
: LLDAIN:
X
X
X
X
X
: LLDALN:
X
X
X
X
X
X
X
X
X
X
X
: LLDAXY :
: Set Dialog
: Area Color
: Map "*
X
"* This DTI routine is not documented in the 4110 Series DTI
Programmers Reference Manual. Refer to the programmers
reference manual for your terminal.
70 INSTRUCTION
Rev, Mar 1984
7-115
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
i DTI
: 4105 i 4107 : 4109 : 4112 : 4113 i 4114 : 4115 I Comments
I Routine!
I
I
I
I
I 4116 :
:
x
x
I LLDASF :
x
------------------------------------------------------ --~--------~---------
------------------------------------------------------ ------------~--------
: LLDAVS :
X
X
X
X
X
X
X
i LLDAWM I X
X
X
X
X
X
X
X
X
LLDHCA
X
I Set Dialog
I Hardcopy
: Attributes
LLDMAB
X
*
: Requires
I Option 03
: (DMA)
: LLDRBM I
X
LLDUPX
X
X
X
X
I LLECHO I X
X
X
X
X
X
X
: 11EDCH:
X
X
x
x
X
X
X
: LLEOF
X
X
X
X
X
X
X
: L1E01
X
X
X
X
X
X
X
I LLEOM
X
X
X
X
X
X
X
: LLERTH:
X
X
X
X
X
X
X
X
X
X
X
X
X
I 11FXUP :
*
7-116
Requires
Option 01
(Half Duplex
& Block mode)
This DTI routine is not documented in the 4110 Series DTI
Programmers Reference Manual. Refer to the programmers
reference manual for your terminal.
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
I DTI
I 4105 I 4107 I 4109 I 4112 I 4113 I 4114 I 4115 I Comments
I Routine:
I
:
:
I
I 4116 I
I
I LLFLAG:
X
X
X
x
x
x
: LLARGN I
X
X
X
x
I LLCRGN I
X
X
X
x
x
x
x
x
I LLCLGN I
X
X
II LLGSPD II X
X
X
I LLSPGN I
X
X
X
x
x
x
I LLSPG4 :
E
E
E
E
E
E
I LLGRGN I
X
X
X
x
x
x
I LLGRG4 I
E
E
E
E
E
E
I LLIKGN I
X
X
X
x
x
x
x
I
X
I Set Gin CurI sor Speed *
I
x
x
-----------------------~------------------------------ --------------------X
X
X
x
X
I LLTBSF I
x
I LLWIGN I
X
X
X
x
x
x
I LLRBGN :
X
X
X
I LLWIG4 I
E
E
E
E
E
E
X
X
X
x
x
x
I LLGFNT I
X
X
X
x
x
x
I LLGGRD I
X
X
X
x
X
x
I LLGAWM:
X
* This DTI routine is not documented in the 4110 Series DTI
Programmers Reference Manual. Refer to the programmers
reference manual for your terminal.
4170 INSTRUCTION
Rev, Mar 1984
7-117
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
--------------------------------------------------------------------------I DTI
I 4105 I 4107 i 4109 I 4112 I 4113 I 4114 i 4115 I Comments
Routi nelI
I
I
I
I
I
I
I
I
I
I
I
I
4116
I
I
I
I
--------------------------------------------------------------------------X
X
X
X
X
X
I LLGPRC I X
LLGROT
X
X
X
X
X
X
I LLGSIZ I X
X
X
X
X
X
X
: LLGSI4 i
E
E
E
E
E
E
X
X
X
X
X
X
X
X
E
I LLGSLT I
II LLHCOR II
I
X
I
i LLKYEX I X
X
X
X
X
X
X
I LLLNIN I X
X
X
X
X
X
X
I LLLNST i X
X
X
X
X
X
X
: LLLNWD I
X
i LLMARG I
X
I LLMKTY i X
X
X
: LLHCPS i
X
X
X
i LLOVWI :
X
X
X
: LLOVW4 i
E
E
E
i LLPGFL i
X
X
i LLFPNL i
X
X
X
X
I
I
X
X
X
X
Rev, Mar 1984
X
X
: Requires
: Option 09
X
I
I
: LLPRTY:
-118
X
Angles
limited on
4105 to 0,
90, 180, 270
i Requires
i Option 09
X
X
X
X
4170 INSTRUCTION
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
: DTI
: 4105 : 4107 : 4109 : 4112 : 4113 : 4114 I 4115 I Comments
: Routine I
I
I
I
I
: 4116 i
I
i LLPVSG i
x
x
x
x
x
x
x
x
x
I LLPVS4 i
E
E
I LLPKAP :
i LLPKID i
x
x
x
x
x
x
x
x
E
E
E
E
x
LLPXBM
x
x
x
x
x
x
I 4105 requires
I pixel operaI tion ROMs
LLPXVW
x
x
x
x
x
x
I 4105 requires
I pixel operaI tion ROMs
LLPBAU
x
x
x
x
x
x
4110
terminals
require
Option 10
(3PPI)
LLPEOF
x
x
x
x
x
x
4110
terminals
require
Option 10
(3PPI)
LLPEOL
x
x
x
x
x
x
4110
terminals
require
Option 10
(3PPI)
LLPFLG
x
x
x
x
x
x
4110
terminals
require
Option 10
(3PPI)
4170 INSTRUCTION
Rev, Mar 1984
7-119
mCTION 7
?rogramming Information
Ta.ble 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
: DTI
: 4105 : 4107 : 4109 : 4112 : 4113 : 4114 : 4115 : Comments
: Routine:
:
:
:
:
: 4116 :
:
LLPPRY
x
X
X
X
X
X
4110
terminals
require
Option 10
(3PPI)
LLPBIT
x
X
X
X
X
X
4110
terminals
require
Option 10
(3PPI)
X
X
X
X
X
X
I LLSPRM:
X
------------------------------------------------------ --------~------------
: LLQSIZ:
X
X
X
X
X
X
X
: LLEOMF :
X
X
X
X
X
X
: LLRPMX :
X
X
X
X
X
X
: LLRPSG :
X
X
X
X
X
X
: LLCSSG I
X
X
X
X
X
X
I LLDTSG :
X
X
X
X
X
X
I LLPRSG I
X
X
X
X
X
X
: LLHISG :
X
X
X
X
X
X
: LLIMSG I
X
X
X
X
X
X
: LLIMS4 :
E
E
E
E
E
E
I LLTNSG :
X
X
X
X
X
X
: LLTNS4 :
E
E
E
E
E
E
I LLVISG :
X
X
X
X
X
X
7-120
Rev, Mar 1984
4170 INSTRUCTION
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
: DTI
: 4105 : 4107 I 4109 I 4112 I 4113 I 4114 : 4115 I Comments
: Routine:
I
:
I
I
I 4116 I
I
I LLWMSG I
x
x
x
X
X
X
I LLSNPY I X
X
X
X
X
X
X
I LLSTBT I X
X
X
X
X
X
X
I LLCLMP I X
X
X
X
X
X
I LLDFSF I
X
X
X
X
X
X
X
X
I LLGRSF I
: LLPRSF :
X
X
X
X
X
I LLVISF :
X
X
X
X
X
LLTBSZ
X
X
X
X
Requires
Option 13/14
(tablet
option)
LLTBHD
X
X
X
X
Requires
Option 13/14
(tablet
option)
LLTBSS
X
X
X
X
Requires
Option 13/14
(tablet
option)
II LLTABS II X
X
X
I LLTXIN I X
X
X
I
I Set Tab
I Stops *
I
X
X
X
X
* This DTI routine is not documented in the 4110 Series DTI
Programmers Reference Manual. Refer to the programmers
reference manual for your terminal.
~170
INSTRUCTION
Rev, Mar 1984
7-121
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
: DTI
: 4105 : 4107 : 4109 : 4112 : 4113 : 4114 : 4115 : Comments
: Routine:
:
:
I
:
I 4116 I
:
: LLXMTD :
: LLXMTL:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
: LLUSER :
I LLVWAT :
X
X
X
X
X
: LLVWDC :
X
X
X
X
X
: LLVWPT I
X
X
X
X
X
I LLWIND I X
X
X
X
X
X
I LLWIN4:
E
E
E
E
E
E
: LLAS14 :
X
X
X
X
X
X
X
: LLSPOL I
X
X
X
X
: LLESPL :
X
X
X
X
X
X
X
X
LLWAIT
: INTIX
I
I
I
X
: N/A
I
I
INRYIX
I
II STRIX
I
7-122
X
: N/A
I
I
I N/A I
X
II N/A
I
N/A
I
N/A
: N/A
I
I
I
N/A
: N/A
I
I
I
II N/A
: N/A
I
I N/A I
I
N/A
: In 4170 DTI,
: sends SYNC
: characters
N/A
I
I
: Internal 4170 :
: DTI Utilities:
Internal 4170
DTI Utilities
I
I
I
I
I
I
I
I
I
: N/A
: N/A
: N/A
: N/A
: N/A
II N/A
: N/A
I Internal 4170 :
I DTI Utilities:
I
I
I
I
Rev, Mar 1984
I
I
I
I
I
I
I
I
I
4170 INSTRUCTION
I
SECTION 7
Programming Information
Table 7-4 (cont)
TERMINAL/4170 DTI COMPATIBILITY CHART
i DTI
i 4105 i 4107 i 4109 : 4112 i 4113 i 4114 i 4115 : Comments
i Routine i i i
i
:
i 4116 i
i
---------------------------------------------------------------------------
XY1X
1
1
1
N/A
1
1
1
N/A
1
1
N/A
1
1
1
N/A
1
I
I
I
1
1
I
I
GETCHR
1
1
1
1
N/A
1
1
1
1
N/A
1
1
N/A
1
N/A
I
I
I
I
1
I
1
1
I
I
1
1
1
N/A
I
N/A
1
1
N/A
I
N/A
I
I
N/A
I
I
N/A
1
1
1
1
Internal 4170
DTI Utilities
I
I
I
I
I
I
Internal 4170
DTI Utilities
1
Internal 4170 II
DTI Utilities 11
1
I
I
I
--------------------------------------------------------------------------I
1
1
1
1
1
1
1
1
Internal 4170 II
I N/A
I
1 N/A
1 XY41X
1 N/A
1 N/A
1 N/A
I N/A
I N/A
1
I
1
1
1
1
1
1
I
I
1
1
I DTI Utilities
I
I
1
1
I
I
I
1
1
1
1
I
1
1
1
1
1
I
1
1
1
--------------------------------------------------------------------------1
1
1
1
1
1
1
1
1
1
1
1
1
PUTCHR
1
I
N/A
1
70 INSTRUCTION
1
I
I
N/A
1
1
1
N/A
1
1
I
N/A
I
1
I
N/A
I
I
1
N/A
I
I
I
N/A
Rev, Mar 1984
7-123
1
I
Seotion 8
SELF TEST
INTRODUCTION
This section describes the 4170's self test features. It is
divided into two subsections according to the intended reader. If
you are NOT a service technician, see "WHAT THE USER NEEDS TO
KNO\v." You need not bother with the rest of this section.
Service technicians should refer to "WHA~ THE SERVICE TECHNICIAN
NEEDS TO KNOi/J," later in this section.
WHAT THE USER NEEDS TO KNOW
The 4170 includes a variety of self-test routines. Some of these
("Power-Up Self Test") are performed automatically every time
power is applied. Others ("Extended Self Test" and "Adjustment
Self Test") are performed only on request. The Adjustment Self
Test is only for the service technician; it is described later in
this section.
POWER-UP SELF TEST
To perform the Power-Up Self Test, turn on the 4170, or (if it is
already turned O~), press the RESET switch on the 4170
front-panel keyboard.
If no errors are detected, Power-Up Self Test ends with "00"
displayed in the STATUS digits on the 4170 front panel and the
4170 proceeds to load the operating system.
If Power-Up Self Test detects an error it sounds the bell,
displays an error code in the STATUS digits, and turns on four
deci~al points immediately below those STATUS digits.
See "Error
Code Meanings," later in this section.
4170 INSTRUCTION
8-1
SECTION f3
SELF T~~ST
EXTENDED SELF TEST
run Extended Self Test, connect a terminal to Terminal Port
(also referred to as Port 0), set the terminal communications
parameters to the factory default values (see section 4,
Connecting Cables) and proceed as follows:
~o
1. On the 4170 front-panel keyboard, simultaneously press RESET
and 'I'EST.
2. Release the RESET switch, but continue to press TEST.
3. 'rhe STATUS display will display FF, then (very briefly) FE,
and then will display the following sequence: 01, 02, 04, 08,
10, 20, 40, 80. When this happens release the TBST switch.
4. The bell will sound, the LEDs will show FC, and the dots at
the bottom of the LEDs will blink. When this happens, press
any switch (except TEST or RESET) on the 4170 front panel.
5. The Extended Self Test will then continue. As it does, the
STATUS lights display a sequence of two-digit hexadecitlal
codes. (T~ese codes tell a service technician which part of
Extended Self ~est is being performed.)
6. If an error is detected, the bell will sound, an error code
will be displayed in the ~:;TATUS digits, and THEHE WILL BE
FOUR DECIMAL POINTS DISPLAYED IMMEDIATELY BELOW THE STATUS
DIGITS. If that happens, see ""Error Code ~'ieanings," the next
to"t;ic in this section.
(It is not an error code if the
decimal points are not displayed).
7. If no errors are detected, the test \v1 11 end wi th "00"
displayed in the STATUS lights on the 4170 front panel and
the 4170 will proceed to load the operating system.
ERROR CODE MEANINGS
When Power-Up Self Test or Extended Self Test detects an error,
the 4170 displays an error code in the STATUS lights on its front
panel, together with four decimal points immediately below the
S':'ATUS lights.
8-2
REV, OCT 1983
4170
Hr;)TRUCTIO['~
SECTION 8
SELF TEST
Sometimes several error codes will be displayed in sequence. The
first error code is the primary one, and is listed in the
following table.
Subsequent error codes are "submessages;" you
can invoke them by pressing the CONT key on the 4170 front panel.
The 4170 will display them anyway after a wait of about 20
seconds. Pay attention only to the FIRST error code.
NOTE
If the code in the STATUS lights is not
accompanied by four decimal points immediately
below, then it is NOT an error code.
ERROR CODE
POSSIBLE DEFECTIVE MODULE
("x" means
"any d igi t")
("X" marks the modules
which may be defective.)
I
I
I
I
I
I
I
I
I
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Opt. 45: Mass Storage Interface Board ---+
Opt. 44: Floppy Disk Controller Board ---+
Opt.10: Second 3PPI Board
Opt. 9: Color Copier Interface Board ----+ :
3PPI Board
ECC Memory Board --------------------~---+
Front Panel Keyboard
Processor Board
I
I
---------------+
------------------------------+
--------------------+:
-------------------------+ :
:: :
:
:
5x
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6x
: X :
00 · . uNo error" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8x
Bx
CE • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ••
EC
EE
DF
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X
:
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X
X
X
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X I X
X II II
II
FC .. "Waiting for you to press a key" ......... .
FD
X X
FE
X X II
II
Ex
· .......................................... .
4170 INSTRUCTION
1-0CT-83
I
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8-2A
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: X
1
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SECTION 8
SELF TEST
Table 8-1 lists the (primary) error codes that may be displayed
during Power-Up Self Test or Extended Self Test. For each code,
the table shows which modules in the 4170 may be at fault. Those
are the most likely modules to replace.
Error codes which point to the Disk Controller modules ("8x"
codes for the Option 44 Floppy Disk Controller, or "5x" codes for
the Option 45 Mass Storage Interface Board) may refer to errors
in the cabling to the disk drives or even the disk drives
themselves. However, most of these error codes are for tests
which exercise only circuitry on the disk controller board
itself.
4170 INSTRUCTION
1-0CT-83
8-3
SECTION 8
SELF TEST
Table 8-1
SELF-TEST SEQUENCE
Explanation
: Hex
:
: Digits :
: FF
: Beginning of test.
: Executed l
:
I
I
(a)
:
---
-------------------------~---~------------------------ ----
FE
: FD
Start of LED checking routine.
(During LED checking routine, LEDs
T1, T2, and T3 light in sequence,
followed by the displays 01, 02,
04, 08, 10, 20, 40, 80; then this
is repeated once again, more
rapidly.)
: End of LED checking routine.
FC
8-4
Front panel key check .. (the bell
sounds, a menu is displayed, and
the user is expected to press a
key on the front panel keyboard.)
SLF
: SLF
SLF
: SLF/PUP
: EF
: Timer check
: EE
:
: EC
: Processor board ROM check
: SLF/PUP
: DF
: Low 32K RAM/Bus address check
: SLF/PUP
: BF
: Low 32K RAM Walking ones check
: SLF
: BE
: Low 32K RAM Walking zero check
: SL:B'
: BD
: Low 32K RAM all ones check
: SLF/PUP
: BC
: Low 32K RAM all zeros check
: SLF/PUP
: B5
: RAM stack building
: SLF/PUP
: BA
: RAf>1/RGr1 memory map tables building : SLF/PUP
: DE
: Upper RAM bus check
: SLF/PUP
: B9
: Upper RAM walking ones check
: SLF
~imer
set up routine
: SLF/PUP
4170 INSTRUCTION
SECTION 8
SELF: TEST
Table 8-1 (cant)
SELF-TEST SEQUENCE
Explanation
I Hex
I
I Digits I
I Upper RAM memory delay check
I BB
I Executed I
I
(a)
I
I B8
: Upper RAM walking zero check
I SLF
I B7
: Upper RAM all ones check
I SLF/PUP
I B6
I Upper RAM all zeros check
I SLF/PUP
I CE
: System ROM checksums
I SLF/PUP
I EB
I Interrupt check
I SLF/PUP
I E9
: 8087 FPU test
: SLF/PUP
I DD
I Host port register check
: SLF/PUP
I DC
: Host port baud/character check
I SLF
I 6F
: 3PPI Board Register Check
I SLF/PUP
I 6D
: 3PPI Board Character Check
I SLF
: 67
: Option 10 Board Register Check
I SLF/PUP
: 65
I Option 10 Board Character Check
I SLF
: 5F
: Option 45 8089 ROM Checksum Test
I SLF/PUP
I SLF
I Option 45 8089 RAM Check Test
I SLF/PUP
: 5E
---------------------------------------------------------: Option 45 MSIB Read/Write
I SLF
: 5D
I
I
:
Verification
I
I
I 5C
I
I
II 5B
I
I Option 45 Flexible Disk Status
I Register Test
II SLF/PUP
I
I Option 45 Flexible Disk Controller : SLF
I Initialization
:
4170 INSTRUCTION
1-0CT-83
8-5
SECTION 8
SELF TEST
Table 8-1 (cant)
SELF-TEST SEQUENCE
I Hex
I
I Digits I
Explanation
I Executed :
:
(a)
I
II 5A
: Option 45 Flexible Disk Interrupt
\ Check
: SLF
I
I 59
I Option 45 8089 Processor Check
I SLF
:I 53
I Acknowledge Test
: Option 45 MSIB Automatic
I SLF
II
I Option 44 Board Status Register
I Check
\ SLF/PUP
I
: 8E
I Option 44 Disk Controller Check
I SLF/PUP
I
I Option 44 Drive Present Check
: SLF/PUP
I
I
I Option 44 Intersystem Interrupt
I Check
I
\ 8B
I Option 44 DMA Operation Check
: SLF
I
\ Option 44 DMA Addressing Check
\ SLF
I
8F
8D
\ 8C
8A
I
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I
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I
I SLF
I
(a) SLF means the test is performed during Self Test, while PUP
means the test is performed during the Power Up routine.
WHAT THE SERVICE TECHNICIAN NEEDS TO KNOW
NOTE
This is a preliminary manual. At the time it
went to print, not all information about Self
Test was available. Additional information
will be provided in the final version of this
manual.
The 4170 has three self test programs: Power-Up Self Test,
Extended Self Test, and the Adjustment Self Test.
8-6
4170 INSTRUCTION
SECTION 8
SELF TEST
POWER-UP SELF TEST
The 4170 ~erforms its Power-Up Self Test automatically whenever
it is turned on, or whenever the operator presses the RESET
switch on the front panel.
If the test reveals a fault in the 4170's circuitry, the test
halts with the following displayed:
(a)
A two-digit error code displayed on the 4170's
front panel; and
(b)
Four decimal points displayed below the two-digit code.
All the tests in the Power-Up Self Test are also performed in the
Extended Self Test. For info~mation about particular error codes,
see the following Extended Self Test description.
EXTENDED SELF TEST
Starting Extended Self Test
To start the Extended Self Test program, press and hold the TEST
switch while pressing and releasing the RESET switch. When the
front-panel LEDs begin to light sequentially (cycle), release the
TEST switch.
Initial Tests
The Extended Self Test program begins by testing the front-panel
indicators. The test starts by sequencing the three LEDs and the
two LED numeric displays. First the program turns off the LEDs
and dis!'lays "00" on the LED displays. Then, each LED (starting
with ~1) is turned on individually. Next, the LED displays show
the following series of numbers: 01, 02, 04, 08, 10, 20, 40, 80.
This series is repeated quickly.
Keyboard Test
Next, the 4170 tests its front-panel keyboard. At the same time,
you have a chance to select between (a) continuing the Extended
Self Test in its entirety, (t) continuing the Extended Self Test
but omitting the lengthy memory delay test, or (c) selecting the
Adjustment Self Test.
The Keyboard Test works as follows. The 4170 sounds its bell,
blinks the T1 LED on the front panel, and waits for a keystroke.
At this point, one of the following front panel keys should be
pressed:
4170 INSTRUCTION
8-7
SECTION 8
SELF TEST
Key Pressed
Result
CTRL-C
4170 starts the Adjustment Self Test (after PUP
tests are finished)
CTRL-D
4170 continues with the Extended Self Test
BUT OlVJ ITS THE HD10RY DELAY TEST
ANY OrrHER KEY
4170 continues with the Extended Self Test
(including the Memory Delay Test),
NOTE
If the test proceeds immediately (without
pressing a key), spurious keystrokes are
being generated. This could be caused by dirt
or corrosion in the keys or poor continuity
in the connecting cable.
If you wait more than about 20 seconds before pressing a front
panel switch, the test will continue as if you had selected the
"ANY OTHER KEY" option.
Remainder Of Extended Self Test
Provided the CTRL-D option was not selected, the 4170 continues
with the rest of Extended Self Test. As Extended Self Test
continues running, the seven-segment displays indicate the
hexadecimal code number of the particular test being run. If a
fatal error occurs during a test, the identifying error code
remains on the displays and the bell sounds twice.
NOTt~
Error codes on the seven-segment displays are
accompanied by four decimal points. Any
lingering codes that are not acco~panied by
these decimal points are NOT error codes.
The tables that follow list and define the error messages,
including submessages, giving an explanation for each error
condition and suggesting which part of the circuitry is
mal funct i ani ng. The tabl es are grouped togethe r accord i ng to the
hardware being tested. (This is not the order in which the tests
are performed.)
8-8
4170 INSTRUCTION
SECTION t3
SELF TEST
After the error code is displayed, most problems can be narrowed
through the use of submessages. First note the primary error
code. Then press CONT key and note the next error code
(submessage). If CONT is not pressed, the program times out after
20 seconds and displays the submessage. In some cases, there may
be several levels of submessages. The error code tables list the
submessages for each code.
After the display port (Port 0) has been checked, all error
are also shown on the screen of the companion terminal,
which must be s~t to 2400 baud. Such screen-displayed error
messages first print the name of the test or the hardware module
being tested. A submessage on the next line identifies the part
of the test that failed.
messa~es
KEYBOARD AND LED CHECK (FE, FD)
The following error codes may be displayed during the keyboard
tests. flor a description of these tests, see "Starting Extended
Self Test," earlier in this section.
Table 8-2
FRONT PANEL/PROCESSOR INTERFACE ERRORS
: Hex
: Explanation
: Digits :
: FE
I
I
: Error at beginning of keyboard LED test
: (LEDs cycle here)
: FD
: Error at end of keyboard LED test
CIRCUITS USED: Look for problems on the 4170 keyboard, the
keyboard interface on the Processor Board, and the keyboard
ribbon cable and connectors.
4170 INSTRUCTION
8-9
SECTION 8
SELF TEST
PROCESSOR CHECK (EX)
Extended Self Test now tests the 4170 Processor Board and Keyboard
functions. The processor and its related hardware are systematically
exercised.
Table 8-3
PROCESSOR BOARD ERRORS
: Hex
: Explanation
: Digits :
EF
Error detected during timer test. (NOTE)
Submessage Hex Digits: XX
Binary OOAB OOOC, where bits A, B, and C have
the following meanings:
A;1 Failed static test: ~est timer outputs
for high/low values.
B;1 Failed dynamic test. Tests timer for
correct count versus processor execution.
C;O Failure in timer 0 (I/O address OOE1).
C;1 Failure in timer
(I/O address 00E3).
NOTE -- Timer 2 cannot be tested at this
point, but is tested later durinr, the host
port check (Dx).
initializ~tion.
: EE
: Failure during timer
: EC
: Error during Processor board ROM checksum
: test.
I
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8-10
4170 INSTRUCTION
SECTION 8
SELl" TEST
Table 8-3 (cont)
PROCESSOR BOARD ERRORS
: Hex
: Explanation
: Digits :
EB
Error detected in interrupt handler check
(NO':'E)
Submessage Hex Digits: XX
First Submessage: Bits that cannot be set in
Interrupt Register (I/O base address OOEA).
Second Submessage: Level 5 interrupt
performed. Failed to reach interrupt vector
address: XX + (4 x 5). (Level 5 interrupt is
the easiest level of interrupt to force
(hence x5). Each time an increment of a level
is made, it moves up four bytes in memory
(hence the 4). XX equals the base interrupt
address.)
Third Submessage: A divide by 0 instruction
was performed, but did not vector through
location O. XX equals the base interrupt
address. (XX:OO most likely implies an
version of an 8086 processor IC that is not
acceptable for Processor Board operation.
NOTE -- Self-test cannot detect if either T1
or T2 inputs to the PIC are held at a TTL low
or if the interrupt outputs from the PIC are
held low. If these conitions are suspected,
check signals with an oscilloscope.
: 1<:9
I
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: Error detected during Math floating point
: Co-processor (FPU) tests
4170 INSTRUCTION
8-11
SECTION 8
SELF T}~ST
COMMUNICATIONS AND BUS CHECKS (DX)
Self Test now examines the operation of the main 4170 bus and the
host I/O port. This it does by writing to low RAM (located
between 0000 and 7FFF) using the a(ldress of a word as the data to
go in that word. It then reads this address back, using th~
comparison as a bus check. This assumes the RAMs are go6d . .
Table 8-4
RAM BUS AND HOST PORT ERRORS
l Hex
l Submessase l Explanation
: Digits l Hex Digits l
Problems with low bits of main 4170 bus or
addressing via this bus.
DF
xx
Submessage 1. XX i nd icates the base.
address of the RAM that caused the bus
problem: hexadecimal XXOOO.
yy
Submessage 2. YY is the Low data byte,
showing which bits are in error. If these
bit are all ones, address bit zero is
likely to be bad.
zz
Submessage 3. ZZ is the High data byte,
showing which bits are in error. If these
bits are all ones, BEEN (Byte High Enable)
is probably bad.
NOTE: If YY and ZZ are all ones, this
indicates a time-out problem while
attempting to access a RAM.
8-12
4170 INSTRUCTION
SECTION 8
SELF TEST
Table 8-4 (cont)
BUS AND HOST PORT ERRORS
l Hex
l Submessage l Explanation
l Digits : Hex Digits I
DD
I
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I
Error detected during host port I/O
address check.
: (On screen)
Submessage one: "Host Port .... Registers
Expect: XX Receive: II"
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: (On screen)
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This test checks the reset of the USART.
after resetting USART, it reads the data
at status I/O address (E2). It expects to
read XX. If instead it receives II (where
XX is not equal to II) this means the test
failed and the USART cannot be reset.
Submessage two: "Host Port-Register
Expect: XX-IY Receive: ZZ-AA"
The test checks USART latch (I/O address
EE), and USART Interrupt Request (I/O
add ress E8).
XX - Latch status expected; is 00 if no
bits are in error.
II - Interrupt request bits in error; is
00 if no bits are in error.
ZZ
Latch Status bits in error.
AA - Interrupt request bits in error.
4170 INSTRUCTION
8-13
SECTION 8
SELF TEST
Table 8-4 (cant)
BUS AND HOST PORT ERRORS
: Hex
: Submessage : Explanation
: Digits : Hex Digits :
I
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DC
I
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I
Error detected during host port
baud rRte/ character check.
I
: (On screen)
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Submessage:
"Host Port-Baud/Character
Baud: XXXX Expect: IY-AA
Receive: ZZ-BB"
The following table may be used to convert
the baud rate from a hexadecimal to a
dec imal numeral:
Hexadecimal
12C
25B
4BO
708
7DO
960
Decimal
300
600
1200
1800
2000
2400
Hexadecimal
E10
12CO
1C20
2580
4BOO
9600
Decimal
3600
4800
7200
9600
19200
38400
Self Test cannot check the following signals if they are tied to
a TTL low: MWTC; PFAIL; BCLK; INT1; INT2; INT3; IN?4; INT6; INT7;
BREQ;
E~-1
4
BGT.
4170 IhSTRUC?ION
SECTION 8
SELF TEST
Figure 8-1. Status Byte.
4170 INSTRUCTION
8-15
SECTION 8
SELF TEST
RAM CHECK (BX)
This set of tests perform .a systematic check of all system RAMs. Each
set of tests is grouped, and each such group uses the same type of
error reporting scheme.
In the following tests, the RAM Memory Delay Check (code BE) generates
a light code which may remain lit for as much as 14 seconds while the
test is running. This does not indicate an error. Errors are indicated
by the bell's sounding, tog~ther with four decimal points being
lit on the two-digit numeric display. The lengthy delay memory check
may be bypassed by entering CTRL-D during the earlier keyboard check.
NOTE
In the following table, "Low 32K RAW' refers·
to the RAM from hexadecimal address 0000 to
7FFF. "Uppe:r RAM" refer·s to RAIVI addressed
from 8000 through the upper limit of the RAM
installed.
Table 8-5
RAM TEST ERRORS
: Hex
: Digits
:
:
:
:
:
:
Submessage
Hex
Digits
Low 32K RAM, walking ones check. (Here
each bit is set and tested, in order from
left to right, hence the "walking ones" term.)
: B:B'
8-16
: Explanation
:
:
:
xx
Submessage one. XX indicates the address of
the RAM: "Problem at hexadecimal address XXOOO."
yy
Submessa~e two. YY is the Low Data byte, showing
which bits are in error.
zz
Submessage three. ZZ is the High Data byte,
showing which bits are in error.
4170
INSTRUC~ION
SECTION 8
SELF TEST
Table 8-5 (cont)
RAM TEST ERRORS
: Hex
: Sub: Digits : message
I
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I Hex
I
I
I
I Digits
BE
-
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I
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: Explanation
:
:
:
Error in "walking zeros" check; low 32K RAM.
xx
Submessage one. XX indicates the address of
the RAM: "Problem at hexadecimal address XXOOO."
yy
Submessage two. YY is the Low Data byte, showing
which bits are in error.
zz
Submessage three. ZZ is the High Data byte,
showing which bits are in error.
}<~rror
ED
in "all ones" check; low 32K RAM.
XX
Submessage one. XX indicates the address of
the HAM: "Problem at hexad ecimal ad dress XXOOO."
yy
Submessage two. YY is the Low Data byte, showing
which bits are in error.
ZZ
Submessage three. ZZ is the High Data byte,
showing which bits are in error.
BC
Error in "walking ones" check; low 32K RMJI.
XX
Submessage one. XX indicates the address of
the RM1: "Problem at hexadecimal address XXOOO."
yy
Submessage two. YY is the Low Data byte, showing
which bits are in error.
zz
Submessage three. ZZ is the High Data byte,
showing which bits are in error.
4170 INSTRuc'rION
8-17
SECTION 8
SELF TEST
Table 8-5 (cont)
RAM TEST ERRORS
: Hex
: Digits
:
:
:
:
:
:
Submessage
Hex
Digits
Error in RAM memory delay check; low 32K RAM.
During this check, data is held for 14 seconds,
and then rechecked. The light code will remain
lit for this time.
:BB
xx
Submessage one. XX indicates the address of
the RAM: "Problem at hexadecimnl address XXOOO."
yy
Submessage two. YY is the Low Data byte, showing
which bits are in error.
zz
Submessage three. ZZ is the High Data byte,
showing which bits are in error.
B9
Error in walking ones check; upper RAM.
XX
Submessa~e
YY
Submessage two. YY is the Low Data byte, showing
which bits are in error.
ZZ
Submessage three. ZZ is the High Data byte,
showing which bits are in error.
one. XX indicates the address of
the RAM: "Problem at hexadecimal address XXOOO."
Error in walking zeros check; upper RAM.
B8
8-18
: Explanation
:
:
:
XX
Submessage one. xi indicates the address of
the RAM: "Problem at hexadecimal address XXOOO."
YY
Submessage two. YY is the Low Data byte, showing
which bits are in error.
ZZ
Submessage three. ZZ is the High Data byte,
showing which bits are in error.
4170 INSTRUCTION
SECTION 8
SELF TEST
Table 8-5 (cont)
RAM TEST ERRORS
I Hex
I SubI Dilits I message
I
I Hex
I
I Dillts
B7
I Explanation
I
I
I
Error in all ones check; upper RAM.
xx
Submessage one. XX indicates the address of
the RAM: "Problem at hexadecimal address XXOOO."
yy
Submessage two. YY is the Low Data byte, showing
which bits are in error.
zz
Submessage three. ZZ is the High Data byte,
showing which bits are in error.
B6
Error in initialization (all zero) check;
upper RAM.
xx
Submessage one. XX indicates the address of
the RAM: "Problem at hexadecimal address XXOOO."
yy
Submessage two. YY is the Low Data byte, showing
which bits are in error.
zz
Submessage three. ZZ is the High Data byte,
showing which bits are in error.
I B5
4170 INSTRUCTION
I Error during RAM stack building.
8-19
SECTION 8
SELF TEST
3PPI CHECK (6X)
This test checks the operation of the 3PPI board. 3PPI error
codes are reported only on the 4170 front-panel display.
Table 8-6
3PPI ERRORS
I Hex
I Digits
I
I
I Sub -
I Explanation
I message I
I Hex
I
I Digits I
6F
Error detected in 3PPI port register check.
OP
Submessage one. An error has been been detected
in the register check for 3PPI port P. The first
digit of this error code is always 0, while the
second digit is 0 for port zero, 1 for port 1,
or 2 for port 2.
xx
First two hex digits (MSB) of the 3PPI control
register written.
YY
Second two hex digits(LSB) of the 3PPI control
register written.
zz
First two hex digits (MSB) of the expected
interrupt data.
AA
Second two hex digits (LSB) of the expected
interrupt data.
BB
First two hex digits (MSB) indicating the actual
interrupt data received.
CC
Second two hex digits (LSB) indicating the
actual interrupt data received.
Submessages two, three, and four describe the
control register pattern sent to the control
register for the 3PPI port named in submessage
one. The pattern sent to the register was XX,
the value expected to be read from the register
was YY, and the value actually read was ZZ.
8-20
4170 INSTRUCTION
SECTION 8
SELF TEST
Table 8-6 (cont)
3PPI ERRORS
i Hex
I Sub i Digits I message
i
I Hex
I
I Digits
6F
I Explanation
I
I
I
Error detected during 3PPI character check.
xx
Submessage two. First two hex digits of baud
rate.
YY
Submessage three. Second two hex digits of
baud rate.
zz
Submessage four. The character transmitted
during the character test.
AA
Submessages five. The character received during
the character test.
BB
Submessage six. The interrupt bits expected
during the character test.
CC
Submessage seven. The interrupt bits actually
read during the character test.
EXPLANATION: the baud rate at peripheral port P
was set to hexadecimal XXYY. The character
transmitted at that port was hexadecimal ZZ,
whereas the character received was hexadecimal
AA. The interrupt bits expected during the test
were hexadecimal BB, while those actually read
were hexadecimal CC.
(The Character Check test uses internal loopback
testing. There is no interaction between this
test and external equipment.
(Refer to the table earlier in this section to
convert the hexadecimal baud rates XXYY to
decimal numbers.)
4170 INSTRUCTION
1-0CT-83
8-21
SECTION 8
SELF TEST
Table 8-6A
3PPI ERRORS (OPTION 10)
-----------------------------------------------------------------------Explanation
: Hex
: Sub :I Digits
I
I
I
: Message
: (Hex
i Digits)
-----------------------------------------------------------------------67
"Optional Error detected during 3PPI port register check. :
3PPI Register
Register
XXXX
Expect:
YY-ZZ
Receive:
AA-BB"
65
"Optional
3PPI Character/Baud
The 3PPI control register XXXX on optional 3PPI I
board was written. Bytes yy andzz were
expected interrupt data but aa and bb were
received.
Error detected during 3PPI port character
check. The Baud rate was set to XXXX. During
the test the character sent was YY. The
character re~eived was ZZ. Interrupt bits
expected are AA. What was received was BB.
Baud:
XXXX
Expect:
YY-ZZ
Receive:
AA-BB
-------~----------------------------------------------------------------
8-22
1-0CT-83
4170 INSTRUCTION
SECTION 8
SELF TEST
OPTION 45 DISK CONTROLLER BOARD CHECK (5X)
The Optional Disk Controller Board (Option 45) controls (a) the
internal hard disk, (b) the MSIB (Mass Storage Interface Bus),
and (c) any Floppy (flexible) disk drives which may be installed.
Table 8-7 lists error codes related to this Disk Controller
Board.
Table 8-7
OPTIONAL DISK CONTROLLER BOARD ERRORS
l Hex
l Message On Screen Of Terminal
l Digits l
(and Submessages)
l 5F
l "8089 Rom Checksum In Error"
l 5E
: "8089 Ram Check Error"
5D
: 5C
:
:
:
:
:
"Invalid 8089 Write Operation"
or
"Invalid 8089" Read Operation"
: "Floppy Disk Status Register Test - "
"Initial HLDS-1 or HDSSSET-1 incorrect"
"HLDS-1 not set after 1 second"
"HLDS-1 not reset after 3.0 seconds"
"HDSSET-1 not reset after 35 milliseconds"
I
"HDSSET-1 not set after 75 milliseconds"
I
---------------------+------------------------------------: 5B
l "Floppy Disk Controller Initialization - "
:
:
:
:
:
:
:
l
I
II
I
I
:
5A
"Initial DIO-1 not reset"
"DIO-1 not set - write required"
"ROM-1 not setable"
"Cannot restore 765 protocol"
:
:
:
:
I
"Floppy Disk Present Check - "
765 Protocol Error"
:
DS4 through DS1 not in agreement"
I
4170 INSTRUCTION
1-0CT-83
8-22A
SECTION 8
SELF TEST
Table 8-7 (cont)
OPTIONAL DISK CONTROLLER BOARD ERRORS
: Hex
: Message On Screen Of Terminal
: Digits:
(and Submessages)
59
:I 58
,
53
"Floppy Disk Interrupt Check - "
"Initial 765 status incorrect"
"765 status incorrect after 1st RECAL byte"
"765 status incorrect after 2nd RECAL byte"
"Level 7 interrupt not present"
"765 status incorrect after SIS"
"STO data error"
"765 status incorrect after reading STO"
"Present track is not track A"
"765 status incorrect after reading present
track status"
"Level 7 interrupt not reset"
: "8089 Processor Test failed - "
:
"Invalid Data Transfer"
"MSIB Automatic Acknowledge Test - "
"AA-1
"AA-1
"AA-1
"AA-1
"AA-1
: 5n
not
not
not
not
not
reset after 1st write to CSCSIF"
set after write to RCS!JlWC"
reset after 2nd write to CSCSIF"
set after read from RCSMRC"
reset after 3rd write to CSCSIF"
: "Option 45 Not Respond.ing"
OPTION 44 DISK CONTROLLER CHECK (8X)
Hard and Soft Errors
When disk operations fail to execute properly, they are
classified as:
o
"Soft errors" -- recoverable and random in nature.
OR
o
"Hard errors" -- persist after several retries.
4170 INSTRUCTION
8-23
SECTION 8
SELF TEST
Soft Errore. Soft errors, relat~d tO,thed isk, happen
when R/W data does not ma.tch expected data. The mechanical
limitations of the diskett~ and d:rJve unit allows:'>temporary
misalignments, oxide dropout on the diskette, dirt particles
under the R/W head, etc. To keep these transitory problems from
hanging up the system, the 4170 processor reoogni~esthe
condition and retries the operation.
Hard Errore. Hard errors can occur when the disket~e or
drive unit is write-protected, or a s~milar operator oversight.
Disk Media
P~oblems
One of the first and easiest tests to make for disk related
problems is to remove the current diskette and replace it with a
known good diskette. Try writinf, to the good diskette and then
read it, to see if the problem persists. If the problem rema.ins,
it is in the drive unit, the Disk Controller board, the
connecting cables, or the power supply.
b-24
4170
INUTHUCTIOK
SECTION 8
SELF TEST
Table 8-8
OPTION 44 ERRORS
: Hex
:' Submessage (printed on terminal :. Explanatio~
: Digits : screen)
.
.:
. ,
8F
I
I
I
I
I
I
Board Status Register
Check
: "Disk -- Board Status Register"
These tests check each
bit in the BSR (Board
Status Register).
I
I
I
I
I
I
I
:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Wrote a 0 to ADR19 (D3
of FC01) and read back a
1•
"Disk -- ADH19-1 not :;r 1"
Wrote a 1 to ADR19, but
read back a O.
"Disk -- ADDR19-1 not reset,:;r1"
Wrote a 0 to reset ADR19
but read a 1.
"Disk -- INTE-O not working"
Did not read back what
vlas written at D6.
"Disk -- BUSW-O not working"
Did not read back what
was written at D5.
I
"Disk -- HDL3-0 not working"
Did not read back what
was written at D3.
I
"Disk -- HDL2-0 not working"
Did not read back what
was written at D2.
"Disk -- HDL1-0 not working"
Did not read back what
was written at D1.
"Disk -- HDLO-O not working"
Did not read back what
was .wr i tten at DO .
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
"Disk -- ADR19-1 not :;r 0"
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
4170 INSTRUCTION
Circuits Tested: Address
Decode. Input Data
Buffer, Board Status
Register, and the ADR19
Address Counter.
8-25
SECTION 8
SELl<' 'rEDT
Table 8-8 (cont)
OPTION 44 ERRORS
: Hex
: Submessage (printed on terminal : Explanation
: Digits : screen)
:
I
I
I
I
I
Initialize and check the
Disk Controller
,
,I
The FDC is put into its
command phase
(regardless of its
present state) via a
series of command reads
and writes. The
following bits are
tested for correct
state:
,,
I
,
,,
I
I
I
I
I
I
I
I
I
I
,,,
,
,
Under :B'COO -- D7 (EOC-1)
Under FCD8 -- D7 (RQM-1)
and D6 (DIO-1)
I
I
I
I
,,
A SPECIFY command is
then issued by the
processor.
I
,
I
,
,
,
,
I
I
I
I
I
"Disk -- Controller Protocol
EOC-O is 0 after init"
I
I
I
,
I
,
I
I
, "Disk -- DIO-1 is 0 -I
, Write required"
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
,
I
I
I
,,
8-26
"Disk -- DIO-1 is 1 -Read requi red"
"Disk -- DIO-1 is 1 after init"
FDC generates an
unexpected interrupt,
bit is in wrong state
after initialization.
FDC required a write to
it, while processor
expects to read from it.
FDC requires a read from
it, but processor
expects a write to it.
Bit D6 is in wrong state
after initialization.
4170 INSTRUCTION
SECTION 8
SELF TEST
Table 8-8 (cont)
OPTION 44 ERRORS
: Hex
: Submessage (printed on terminal : Explanation
: Digits : screen)
:
"Disk -- RQM-1 remains 0"
"Disk -- Cannot restore
Protocol"
FDC never sends RQM-1
(fails in 1000 tries).
Runs initialization
sequence, but cannot
put FDC into a known
state. (Processor cannot
determine what FDC is
doing.)
Circuits tested: FDC,
Board Status, Control
Strobes, Data MUX, and
Address Decode.
Drive present check
8D
The processor issues a
SENSE DRIVE 0 STATUS
(SDS) command. Drive 0
should be present. The
D7 (RQM-1) and D6
(DIO-1) are tested for
correct states before
and during the command.
"Disk -- FO: not present"
Drive 0 should always be
present. This message
means the FDC or Disk
Drive control cannot
find drive unit O.
NOTE: If cable is
connected to Controller
board but not to the
drives, this will still
detect "Drive ready".
4170 INSTRUCTION
8-27
SECTION 8
S:ELF TEST
Table 8-8 (cant)
OPTION 44 ERRORS.
----------------------------------------------------------------------.
.
.
: Hex
: Submessage (printed on t.erminal : Bxplana;tion
: Digits : screen)
.
:. .
------------------------------------------------------ --~-~------------
Circuits tested: FDC's
disk control rjF and
Disk Drive Control
circuits.
8C
Intersystem Interrupt
check
The following procedure
is used to generate an
interrupt: The drive
motors are turned off
and the processor issues
a RECAL DRIVE 0 command.
The.FDC does.not know
that the motors were
off, so it generates an
interrupt.
The processor then
issues the SENSE
INTERRUPT STA7US (SIS)
command to read the
results of the RECAL
command. The results of
the SIS command are
checked as well as RQM-1
Rnd DIO-1.
"Disk -- Intersystem Interrupt
Check"
"Disk -- Bad FCOO init"
Board Status Register
contains error·
(different state than
expected) .
"Disk -- Bad FC08 init"
FDe status register
contains an error
(different state th8n
expected) .
8-28
4170 INSTRUCTION
SECTION 8
SELF TEST
Table 8-8 (cont)
OPTION 44 ERRORS
I Hex
I Submessage (printed on terminal I Explanation
I Digits I screen)
I
.
I
II
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
II
, I
I
I
I
I
I
I
I
I
I
I
I
I
I
41 70
"Disk -- Bad FeOO RECAL-1
status"
"Disk -- Bad !<'C08 RECAL-1
status"
"Disk -- Bad FeOO RECAL-2
status"
"Disk -- Bad FC08 RECAL-2
status"
"Disk -- Level 7 interrupt not
present"
Error in Board Status
Register (BSR) after
first byte of RECAL
command written.
Error in FDC after first
RECAL byte written.
Error in BSR after
second RECAL byte
written.
Error in FDC after
second RECAL byte
written.
Expected interrupt not
present.
"Disk -- Bad FCOO SIS status"
Error in BSR after
Sense Interrupt status
byte written.
"Disk -- Bad }t'C08 SIS status"
Error in FDC after
Sense Interrupt status
byte written.
"Disk -- STO data error"
Error in STO, read at
FDC.
"Disk -- Bad FCOO STO status"
Error in BSR after STO
status byte read.
"Di sk -- Bad. }'C08 STO s ta tus"
Error in FDC after STO
status byte read.
IN~;':'RUCTI
ON
8-29
SECTION 8
SELF TEST
Table 8-8 (cont)
OPTION 44 ERRORS
: Hex
: Submessage (printed on terminal : Explanation
: Digits : screen)
:
"Disk -- Track error"
Error in track number
( PC N ), read at FDC.
"Disk -- Bad FCOO Track status"
Error in BSR after track
number read.
"Disk -- 13ad PC08
Error in FDC after track
numbe r read.
~rack
status"
"Disk -- Level '( interrupt
still present"
Interrupt still present.
Circuits tested: Address
Decode, Board Status,
Control Strobes, Data
IVIUX, A.nd FDC.
8B
DMA Operation check
"Disk -- DMA transfer failed"
Data ('80') not found at
current DMA address
(RAM only).
Circuits tested: DMA
State MA.chine, Data MUX,
Control Strobes, Address
Decode. Address
Counters, Input Data
Buffers, and Board
St atus b loC}~s.
8A
I
DMA Addressing check
Both this test and the
previous test must be
completed before the DNA
State Machine and the
DMA Address Counters are
fully tested; the
testing of one requires
the operation of the
other.
8-30
4170 INSTRUCTION
SECTION 8
SELF TEST
Table 8-8 (cont)
OPTION 44 ERRORS
: Hex
: Submessage (printed on terminal : Explanation
: Digits : screen)
:
The DMA Address Counters
are write only. The only
way to look at these
counters is to examine
the most significant bit
(MSB), which is at D4 of
the Board Status
Register (FCOO).
The twenty-bit counters
are subdivided into
three groups: High
Nibble (FC01), Middle
Byte (FC02), and Low
Byte (FC03). Each group
is tested individually
in the following manner:
HIGH NIBBLE TEST:
Test high nibble first
because all bits must
ripple through the high
nibble while testing the
middle and low bytes.
STEP
1.
2.
SET-UP
Load High Nibble
with O.
Does D4;O? (NOTE)
TEST
3.
4.
5.
Load Middle Byte
and Low Byte with
FF.
Step DMA.
Does D4;O?
TEST
4170 INSTRUCTION
8-31
SECTION 8
SELF TEST
Table 8-8 (oont)
OPTION 44'ERRORS
---------~----~-------~--~~------------~-----~-------- -----------------
:I Hex
: SubmessDDe
1
) - 0 (printed on terminal :I ' Explanation
.,
I Digits
I
screen
I "
----------------------------------------------------------------------.
.
6.
7.
8.
9.
Repeat steps 3-5
eight times.
On eighth try,
does D4:;::1?
Repeat another 8
times. (D4 should
=1 for these 8).
On sixteenth try,
does D4:0?
NOTE -- If D=1 an error
message is reported. All
"D:N?" steps will cause
an error unless the
number is as expected.
Error messages are in
the accompanyi ng tables.'
MIDDLE BYTE TEST
STEP
10.
11.
1 2.
SET-UP
Load High Nibble
with 7.
Does D4,.,0?
Load I>iiddle Byte
with FF.
TEST
13.
Load Low Byte with
FF.
14.
15.
16.
8-32
Step miA.
Does D4:0?
Heload Low Byte
wi th Flo' (leave
Middle Eyte since
it is beinr;
tested) •
4170
INSTRUC~ION
SECTION 8
SELF TEST
Table 8-8 (cont)
OPTION 44 ERRORS
: Hex
: Submessage (printed on terminal : Explanation
: Digits : screen)
:
17.
Repeat steps
13-15; on 256th
try does D4;:1?
(Does High Nibble
;:8? )
..
SET-UP
18.
1 9.
Reload High Nibble
with F.
Does D4;:1?
TEST
20.
21.
22.
Reload Lovi Byt e
with FF and Step
DMA.
Repeat step 19
256 times.
On 256th try does
D4;:0? (High Nibble
..,0)
.
LOW BYTE TEST
Same procedure as Middle
Byte test except the
Low Byte and Middle Byte
are reversed.
"Disk -- DNA Address Counters
ADR19-1 Error"
4170 INS'=?RUCTION
"Early 0-1 @ FC01"
Error detected at step 2
or 5 (Counter reached 8
too soon)
"No 0-1 @ FC01"
Error detected at step 7
"Early 1-0 @ FC01"
Error detected at step 8
"No 1-0 @ FC01"
Error detected at step 9
8-33
SECTION 8
S}iLF TEST
Table 8-8 (cont)
OPTION 44 ERRORS
: Hex
: Submessage (printed on terminal : Explanation
: Digits : screen)
:
"Early 0-1 @ FC02"
Error detected at step
11 or 1 5
"No 0-1 @ FC02"
Error detected at step
17
""Early 1-0
@
PC02"
Error detected at step
19
"No 1-0 @ FC02"
Error detected at step
22
"Early 0-1 @ FC03"
Same explanation as for
FC02 messages, except
substitute FC03 for
FC02 in explanation of
Middle Byte tests.
"No 0-1 @ FC03"
"Early 1-0 @ FC03"
"N'o 1 -0 @ FC03"
These tests check the
clocking and carries of
one counter to the next.
Circuits tested: Same
circuit blocks as tested
in the DMA Operation
Check, except the Data
MUX is not tested.
8-34
4170
Il~~~TRUCTION
SECTION 8
SELF TEST
ADJUSTMENT SELF TEST
Adjustment Self Test is the third diagnostic program that the
4170 uses to test itself. Adjustment Self Test is generally used
to aid in adjusting or troubleshooting the 4170. This program
requires that the technician select what pattern is to be
generated or what test is to be run. Some of the things that
Adjustment Self Test can do are:
o
Give the hexadecimal equivalent of the downstroke and
upstroke of each key on the 4170 front-panel keyboard.
o
Perform a Host Port check for the 4170. (This requires
attaching a loopback connector.)
o
Perform head movements of the flexible disk drives. (This
can aid in head alignment.)
o
Test the hard disk drive, if the 4170 is equipped with that
option.
a
Test each of the RS-232 peripheral ports (except "Terminal
Port") .
Starting Adjustment Self Test
To start Adjustment Self Test, connect a terminal to "Terminal
Port", set the terminal communication parameters to the factory
default values (see Section 4, Connecting Cables) and proceed as
follows:
1. Press and hold both the SELF TEST and RESET switches.
2. Release the RESET switch.
3. After the 4170 front-panel LEDs start of cycle, release the
SELF TEST switch. The terminal is now in Extended Self Test.
4. \l/hen the bell sounds ( at the "Keyboard Test" of Extended
Self Test), press the CTRL and C keys ON THE 4170 FRONT
PANEL at the same time. (Pressing CTRL-C on the companion
terminal won't work.)
5. The 4170 will pause a few seconds during the PUP tests and
then display a general menu on the attached terminal. The
4170 is now in Adjustment Self Test.
6. The General Menu tells you which key to press in order to
test one part of the 4170. All input to Adjustment Self-test
must be done through the 4170 front panel keyboard.
7. Oice one of the keys designated by the General Menu has been
pressed, a second menu will be displayed.
4170 INSTRUCTION
REV, OCT 1983
8-35
8
TEST
~)ECTION
~)ELF
o.
Any selection th8.t requires a humber to be entered (eg. "17"
for track seventeen) is entered with the function keys:
2nd key :r'1 = "0"
F1-P8;; "1-8"
2nd key It'8 = "9"
Any "numbers" entered in this fashion must be terminated
with the CONT key.
The General Menu
The General Menu is the first menu that Adjustment Self Test
displays. The exact form of this menu depends on which options
have been installed in the 4170. Two examples of this menu are
sho\,Tn below:
4170 Adjustment Self Test Menu
f1 3PPI
f2 Processor Board
f3 Flexible Disk - Option 44
Selection
*
4170 Adjustment Self Test
f1
f2
f4
f5
~enu
")PPI
Processor Board
MSIB - Option 45
Optional 3PPI
Selection
*
During Adjustment Self Test, pressing CTRL-C (on the 4170 front
panel) will always cause this General Henu to be displayed on the
screen.
8-36
4170 INS'_'nUCTION
SECTION 8
SELF TEST
Processor Board Menu
Once the General Menu has been displayed, the Processor Board
Menu can be selected from the General Menu by pressing function
key F2 on the 4170 front panel. Once F2 has been pressed, the
Processor Board Menu will be displayed. An example of this menu
is as follows:
Processor Board Menu
f1 CMOS Reset
f2 Keyboard
f3 Host Port
Selection
*
F1:CMOS Reset. The term CMOS Reset means that the setup
memory has been reset and must be restored to factory default
values. This is accomplished by completing self test and then
booting the operating system and executing the utility CONFIG,
using the file FACTORY. TXT.
Example:
A)CONFIG
The terminal must also be reset to 2400 baud (or 4105 factory
default values).
F2: Keyboard. From the Processor Board Menu, pressing
function key F2 will cause every key on the 4170 front-panel
keyboard to display two two-digit hexadecimal numerals. These
hexadecimal codes represent the 8-bit codes that the processor
generates for each upstroke and downstroke of a key. There is a
unique code for the upstroke and downstroke of each key. The
first number of the upstroke code is always 8 plus the first
number of the downstroke code. Figure 8-2 shows the keyboard
keycodes.
The only way to return to the Processor Board Menu is by pressing
CTRL-D.
4170 INSTRUCTION
10-0CT-83
8-37
~:rECTION
8
SELF TESrf
WRITE PROTECT
AO
eO
:--
STATUS
0:
c~~
El RPl
O~
.
o
E
CTL~46
r::::?I
41
42
O~
T2
F3
T3
F1
F4
~J3J
O@~~
F7
F8
s~
~-0D~~
~~
4685-68
F1sure 8-2. Keyboard Keyoodes.
8-38
4170 INSTRGCTION
SECTION 8
SELF TE8T
F3: Host Port. The Host Port routine checks the validity
of the data port by which the 4170 communicates with a remote
host computer. Bnter this routine from the Processor Board Menu
by pressing function key F3. Once this is done, the following is
displayed on the comp~nion terminal:
Host Port
Attach J.. oopback
Press CaNT key
Connect the special loopback connector (available as an optional
accessory) to the 4170's host port connector. Once the loopback
connector is attached, press the CaNT key (on the 4170 front
panel 'keyboard).
The test is repeated at various baud rates, from 19200 down to
300 bits per second. At each 1ata rate, the 4170 sends each ASCII
character (heiadecimal 7F down to hexadecimal 00) to the loopback
connector and receives that character back from that connector.
If no errors are detected, the end of the test is indicated by
the following message:
Complete
This message means the 4170 is ready to go on to the next test.
If there is an error during this test, the following submessage
appears on the screen of the companion terminal:
Host Port-Baud/Character
Baud: XXXX Expect: YY-AA
Receive: ZZ-BB
Here,
XXXX is the baud rate, expressed as a hexadecimal numeral
YY is the
AA is the
ZZ is the
BB is the
signal sent (for example, 7F)
expected bits in error, this should always read 00
signal received
bits in error.
3PPI Menu
The key used to select this 3PPI Menu from the General Menu may
depend on which options are installed in the 4170. Once that key
has been pressed (on the companion terminal or on the 4170 front
panel), the 3PPI Menu is displayed as follows:
4170 INSTRUCTION
8-39
SECTIO:J 8
SELl" TE~)T
3PPI [vlenu
f1 3PPI Ports
Selection
*
This routine is designed to check the RS-232 peripheral ports.
(Port PO cannot be tested here, as it is used for the companion
terminal on which the menus and messages are displayed.)
F1: 3PPI Ports. To start the test from the 3PPI Menu,
press F2. The following message is displayed on the companion
terminal:
*f1
Select Port (key f1.Port 1,
f2~2)
*
Connect an RS-232 cable from the 4170 host port to the peripheral
port to the he tested. Then type the number of the port (eg f1
for Port 1) to be tested, followed by COtTo If there are any
errors in the test, the following message may be displayed:
3PPI-Baud/Character
Sent: XXXX Expect: YY-ZZ Receive: AA-BB
Explanation: the baud ra.te was set to hexadecimal XXXX. During
the test, the character sent was hexadecimal YY. The character
received was hexadecinal ~Z. Interrupt hits expected are ZZ (00),
what was received was BB.
If no errors are found during the test, a prompt (asterisk) is
displayed.
Option 10 3PPI Menu. The followine menu is present when
an additional (Option 10) 3PPI is installed:
3PPI [-:enu
f1 Optional 3PPI Ports
Selection
*
To rerforf'l the test on the or-tional 3PPI ports, press f1 and
select the number of the port to be tested.
8-40
4170 INSTRUCTION
SECTION 8
SELF TEST
*f1
Select Port (Key f1*Port 3, f2*Port 4, f3*Port 5)
*
The test is run in the same manner as the standard 3PPI test and
the error messages are the same.
Option 44 Flexible Disk Menu
The Flexible Disk Menu may be obtained from the general menu by
pressing f3. This menu will only appear if Option 44 is
installed. As Self-test checks the circuitry on the Disk
Controller board, this routine checks the drive unit, also. This
menu is useful for drive unit head alignment. For this purpose a
special alignment diskette (not used in this functional check) is
required.
This is an example of the Disk Menu (items are self explanatory):
Flexible Disk -- Option 44
f1 No Operation
f2 Step Up One Track
f3 Step Down One Track
f4 Seek Track 0
f5 Seek Track 1
f6 Seek Middle Of Disk
f7 Select Head
f8 Seek Last Track
2nd f1 Motor On
2nd f2 Motor Off
2nd f3 Arms Write Mode
2nd f4 Writes Track 39 With a 2F Pattern
2nd f5 Select Your Own Track
2nd f6 Change Device Address
4170 INSTRUCTION
8-41
SECTION 8
SELF TEST
With the disk option installed, properly insert a diskette in the
drive unit before starting this test. Then make sure the WRITE .
PROTECT switch is set to the off position (the LED is not lit).
CAUTION
It is best to perform this part of the
functional check using a diskette fr~e of
data. Performing this test m~y' cause some
data to be written on the diskette. With the
, write-protect switch off, it f~ possible to
write over existing d~ta. Therefore, it is
best to use a new diskette or one that
contains un~anted data.
Press each of the disk menu keys in succession. No error messages
should be received on any of the tests, and the head should move
to the selected area on the diskette. After running through the
head ~ov~ments (in the m~nu), pre~s CTRL ~ to return to the
general menu.
NOTE
This is merely a check of the disk drive unit
to ensure that no error messages are received
and that the drive unit is operational. For a
full alignment procedure of the drive unit,
see the 4110 Series F42/43 Disk Options
Service Manual.
Option 45 Disk Menu
Some of the operations in the Option 45 Disk Meriu do not return ~
prompt when completed. These tests continue to check the
keyboard for further function key requests and will execute the
operations requested; however t if the user wants a menu displayed
(using control-C or control-D) or to exit adjustment self-test
(by pressing control-E), a function that produces a prompt must
be requested. Once self-test has generated a prompt (, ,) on the
attached terminal, a control key can be entered.
8-42
1-0CT-83
4170 INSTRUCTION
SECTION 8
SELF TEST
The following tests DO NOT respond with a prompt after completion:
f2 Step Up One Track,
f3 Step Down One Track,
f4 Seek Track 0,
f5 Seek Track 1,
f6 Seek Middle of Disk,
f7 Select Head,
f8 Seek Last Track,
Sh F1 Run Motor,
Sh F2 Read Current Track.
The following tests DO respond with a prompt after completion:
f1
f7
Sh
Sh
Sh
Sh
Sh
Sh
MSIB -- ID Verification
Select Head
F3 Arm Write Mode
F4 Write Current Track With a 2F Pattern
F5 Select Your Own Track
F6 Change Device Address
F7 No Operation
F8 MSIB -- External Peripheral Test
For example, if the user presses key F4, the current drive will
seek track zero and no prompt will be given to the attached terminal.
Even though there is no prompt, key F6 could be pressed and the
current drive would seek the middle of the disk. If key Sh F2
were pressed at this point, the current track would be read. Any
of the function keys could be pressed. If F7 were pressed, the
test would display the new head selected and would display a
prompt when completed. It is only at this point with a prompt
displayed that the control characters could be entered to request
menus or to exit Adjustment Self Test.
4170 INSTRUCTION
1-0CT-83
8-43
Section 10
GLOSSARY
This glossary pertains to this manual and is not intended to be a
universal reference. See CP/M 86 manual (included in package) for
more lists of terms and accompanying definitions.
3PPI
Three port peripheral interface.
ASCII character
Anyone of 128 characters contained in the character set used by
American Standard Code for Information Interchange.
ASCII code
Seven-digit binary numbers which express any of the 128 ASCII
characters.
Argument
An independent variable.
Back-up file
Any copy of a file located on an alternate storage medium, or
under a different user ident code, thus providing back-up
protection for the file~
Baud
Signaling units per second; an expression of serial data
trasmission bit rate.
Binary
A number system which uses two as its base.
and one appear in binary expressions.
Only the digits zero
Bit
Binary digIT.
Break
A signal sent from the terminal to the computer to interrupt
computer transmission in some installations. Also, the command
which intiates the action.
Byte
A group of adjacent binary digits operated on as a
unit and usually shorter than a computer word (frequently
denotes a group of eight or sixteen bits).
CTS
Clear to send.
4170 INSTRUCTION
10-1
SECTION 10
GLOSSARY
Concantenate
To link together in a series or chain.
Control character
k character whose occurence in a particular context, initiates,
modifies or stops a'control action.
DEL
Delete.
DIR
Directory.
DTI
Direct terminal interface.
DTR
Data terminal ready.
Duplex, full
Method of communication where each end may simultaneously transmit
and receive.
Duplex, . half,
Method of communication where each end may transmit and receive;
however, not simultaneously.
ECC
Error correcting code.
EMI
.,Electromagnetic interference.
Format, disk
A series of characters on a disk that enable it to be used.
address.
An
FPU
Numeric co-processor.
File
A collection of related records treated as a unit.
GIN
Graphic input.
GSX
Graphics system extensions
10-2
4170 INSTRUCTION
SECTION 10
GLOSSARY
lEO
International Electrotechnical Commission.
lGL
Interactive graphics library.
LPOS
Local Programmable Operating System.
Line voltage
90-130 V or 180-260 V, 47 to 400 Hz.
Modem
Modulator/Demodulator.
Used primarily for telephone interface.
Operating system
An aid in using the system.
PUT
Programmable Unijunction Transistor.
Simplex
One way transmission.
See
Duplex.
Snubber
Passive circuit waveshaping that allows primary current in a
flyback transformer to flow after the main switching transistor
is cut off.
Strap
A wire JOlnlng two contact points.
option or modification.
This is generally used for an
Transmission, parallel.
Used to identify a system wherein the information is fed in
parallel. Implies two or more transmission channels.
Transmission, serial.
Used to identify a system wherein the bits of a character occur
serially in time. Implies a single transmission channel.
Wild card
A character in a program or sub-program that accomplishes what
would normally take several keystrokes.
Write-protect
A system that protects information on disks from being written over.
4170 INSTRUCTION
10-3
SECTION 11
SERVICE SAFETY SUMMARY
FOR QUALIFIED SERVICE PERSONNEL ONLY
Refer also to the preceding Operators Safety Summary.
DO NOT SERVICE ALONE
POWER SOURCE
Do not perform internal service or adjustment of this product unless another person capable of rendering first aid and
resuscitation is present.
This product is intended to operate from a power source
that will not apply more than 250 volts rms between the supply conductors or between either supply conductor and
ground. A protective ground connection by way of the
grounding conductor in the power cord is essential for safe
operation.
USE CARE WHEN SERVICING
WITH POWER ON
Dangerous voltages may exist at several pOints in this product. To avoid personal injury, do not touch exposed connections and components while power is on.
HANDLING
Disconnect power before removing the power supply shield,
soldering, or replacing components.
Due to the wieght of the Display Module, and its component
subassemblies, at least two persons are required to perform
installatin or service to prevent injury to personnel or damage to the Display Module.
DO NOT WEAR JEWELRY
IMPLOSION PROTECTION
Remove jewelry prior to servicing. Rings, necklaces, and
other metallic objects could come into contact with dangerous voltages and currents.
Whenever the implosion shield is removed from the CRT,
protection against implosion hazard is reduced. Service
personnel should wear full face masks and protective clothing at any time the CRT is removed from the CRT module or
the implosion shield is not in place.
X-RADIATION
X-ray emission generated within this instrument has been
sufficiently shielded. Do not modify or otherwise alter the
high voltage circuitry or the CRT enclosure.
4170 INSTRUCTION
11 -1
Section 12
THEORY OF OPERATION
This section contains detailed theory descriptions for some
boards, and summary information for other boards/modules. Those
boards/modules that are documented in separate manuals are merely
referenced here. Any special application information about such
boards are included with the summaries.
OVERVIEW
The 4170 Local Graphics Processing Unit provides the needed
intelligence and storage capacity for local processing by a
connected terminal. This outboard unit acts as a host for the
terminal in the simplest applications or it may function with
other 4170s in a distributed processing situation. Also the 4170
may act as a host interface, between a terminal and a mainframe
computer (acting as the host).
The 4170 contains the following hardware modules/board, arranged
as indicated in Figure 12-1:
o
Motherboard/card-cage
o
Processor board
o
ECe RAM board
o
Disk Controller board
o
Peripheral Interface board (3PPI)
o
5-1/4 inch Flexible Disk Drive Units (2)
o
Front-panel (Controls/Indicators) Unit
o
Rear-panel connectors
o
Power Supply module
Optional components in the 4170 (also shown in Figure 12-1) are:
o
Optional Additional 3PPI board
o
Optional Additional ECC RAM board
o
5-1/4 inch Winchester Disk Unit (10 M Byte)
o
Color Copier Interface board
4170 INSTRUCTION
12-1
8U1
;:r::trj
f\)
t;r::l(")
I
01-3
1'0
XH
FRONT
PANEL
DISK DRIVE
UNIT(S)
~O
~
TERMINAL AND
PERIPHERAL
DEVICES
o
>:;:1-"
1'0
o
1-0
....
CJtl
~
trj
::;0
>-
s::"1
f-3
H
CD
-'"
I\)
I
-'"
o
HOST
COMPUTER
(if used)
RAM
CONTROLLER
BOARD(S)
PROCESSOR
BOARD
DISK
CONTROLLER
BOARD
z:
3PPI BOARD(S)
•
~
-'"
-.J
0
~
s::::s
()
~
....0
::s
Il'
~
b:I
~
0
()
~
COLOR COPIER
INTERFACE
BOARD
(optional)
t:::I
....
-P-
Il'
~
"1
-.J
0
t-1
Z
U1
8
~
•
COLOR
HARD COPY
UNIT
::D
c::
(")
8
H
0
Z
4685-40
SECTION 12
THEORY OF OPERATION
This eection describes the overall operation of the 4170 and
provides summary descriptions of each circuit board or module.
Many _of the circuit boards are documented in separate manuals, so
references are made to such manuals. Those boards/modules that
are only used in this instrument receive a full theory
description in this section.
CARD-CAGE/MOTHERBOARD
The main circuit boards plug into the Motherboard (Schematic
A1-1) in the back of the 4170 card-cage. This motherboard
contains seven slots, and each slot is an 80-pin connector that
accepts the mating edge-connection of a circuit board. The order
in which the circuit boards are inserted is determined by the
relative priorities of these boards as bus masters and slaves.
Figure 12-2 shows the layout of the Motherboard and the
recommended positioning of the inserted boards. Table 12-1 lists
the signal names and descriptions for each of the 80-pin
connections on the Motherboard.
4170
INSTijUC~ION
12-3
SECTION 12
THEORY OF OPERATION
:il
o(a:
a: W
0...1
a:...1
0(0
Oa:
ZIo(Z
.... 0
II)(J
:il
o(a:
a:W
...1...1
0(...1
zO
Oa:
-II-Z
0.0
O(J
a:
0
II)
II)
W
(J
0
a:
a.
ii:
a.
C')
0
a:
0(
0
Z
....0(II)
W
(J
0(
LL
a:
a: W
a:
W
...I
...I
0
a:
Iz
0
(J
~
II)
i5
ii:
a.
C')
...I
0(
Z
0
i=
a.
0
o!z
...1Oa:
(JW
...Iii:
0(0
Z(J
Qo
I-a:
0.0(
O:l:
D
4685-41
Figure 12-2. Physical Layout of the 7-s1ot Motherboard.
12-4
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Table 12-1
aO-PIN CONNECTOR SIGNALS
I Pin I
I
Signal I Description
1
: -12V
I
I
I 2
:I -12V
I
I
I
I
I
: 3
: GND
: 4
I
I
---
---
: Pin : Signal
: 41
: 42
: Description :
: BUSY-O
: Bus Busy
: CBRQ-O
: Common Bus
: Request
I
I
I
I
: Ground
: 43
: STEST-O : Self-Test
: GND
: Ground
: 44
I
I
: 5
: -5.2V
I
I
---
: 45
: BCLK-O
: Bus Clock
I 6
: -5.2V
I
I
---
: 46
: GND
: Ground
47
GND
Ground
PFAIL-O : Power Fail
: Warning
: Ground
7
I 8
: AGND
: Analog Ground : 48
:I 9
: IN 1'1'-0
: Initialize
I
I
I
I
: 10
: BHEN-O
I
I
: Byte High
: Enable
I ADRO-O
: Address Bus
I
I
: 11
I
I
I
I
I
: 12
: ADR 1-1
I
I
I
I
13
I
I
I
I
ADR2-1
I
I
I
I
14
I
I
I
I
ADR3-1
I
I
I
I
: (not used)
: Interrupt
: Request
50 : INT1-0
: Interrupt
: Request
: INT2-0
: Interrupt
: Request
: INT3-0
: Interrupt
: Request
I
I
I
I
INT4-0
I
I
I
I
Interrupt
Request
I
I
I
I
INT5-0
I
I
I
I
Interrupt
Request
I
I
I
I
: 51
I
I
: Address Bus
: 52
I
I
I
I
Address Bus
I
I
I
I
53
I
I
I
I
Address Bus
I
I
I
I
54
I
I
---
: (not used)
: INTO-O
: 49
I
I
I
I
I
I
---
I
I
I
I
I
I
--------------------------------------------------------------: 15
I
I
: ADR4-1
I
I
4170 INSTRUCTION
: Address Bus
I
I
:I 55
I
: INT6-0
I
I
: Interrupt
: Request
12-5
SECTION 12
THEORY OF OPERATION
Table 12-1 (co'nt)
80-PIlf CONNECTOR SIGNALS
: Pin:
Signal: Description
: Pin : Signal
: Description :
--------------------------------------------------------------.
. '
: 16
: 56
: INT7-0
1
1
1
1
: Interrupt
: Request
: Address Bus
: 57
: DATO-1
: Data Bus
: ADR7-1
: Address Bus
: 58
: DAT 1-1
: Data Bus
: ADR8-1
: Address Bus
: 59
: DAT2-1
: Data Bus
: ADR5-1
: Address Bus
1
1
1
,I
1
1
: 17
: ADR6-1
: 18
: 19
-------------------~---------------------------------- ---------
: 20
: ADR9-1
: Address Bus
: 60
: DAT3-1
: Data Bus
: 21
: ADR10-1
: Address Bus
: 61
: DAT4-1
: Data Bus
: 22
: ADR11-1
: Address Bus
: 62
: DAT5-1
: Data Bus
: 23
: ADR12-1
: Address Bus
: 63
: DAT6-1
: Data Bus
: 24
: ADR 13-1
: Address Bus
: 64
: DAT7-1
: Data Bus
: 25
: ADR14-1
: Address Bus
: 65
: DATS-1
: Data Bus
: 26
: ADR15-1
: Address Bus
: 66
: DAT9-1
: Data Bus
: 27
: ADR 16-1
: Address Bus
: 67
: DAT10-1
: Data Bus
: 28
: ADR 17-1
: Address Bus
: 68
: DAT11-1
: Data Bus
: 29
: ADR1 B-1
: Ad.dress Bus
: 69
: DAT12-1
: Data Bus
: 30
: ADR19-1
: Address Bus
: 70
: DAT13-1
: Data Bus
: 31
: INTA-O
: 71
: Data Bus
1
: Interrupt
: Acknowledge
: DAT14-1
1
1
1
1
1
1
1
1
1
-------------~---------------------~------------------ ---------
: 32
: INH-O
: Read Inhibit
: 72
: DAT15-1
: Data Bus
: 33
: AMWC-O
: Ad v. r~emory
: Write Crnd.
:1 73
: BREQ-O
: Bus Request :
1
1
1
1
1
12-6
1
1
1
1
1
1
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Table 12-1 (cont)
BO-PIN CONNECTOR SIGNALS
: Pin:
Signal: Description
: Pin : Signal
: Description :
: 34
: MWTX-O
I
I
: Memory Write
: Command
: 74
: BPRN-O
: Bus Grant
I
I
I
I
I
I
: 35
: MRDC-O
: Memory Read
: 75
: +5 V
I
I
: IORC-O
: I/O Read
: Command
: 76
I
I
: +5 V
I
I
I
I
I
I
I
I
I
: 37
: AIOWC-O : Adv. I/O
: 77
: Ground
I
I
---
: 38
: IOWC-O
: I/O Write
: 78
: Ground
I
I
---
:I 39
: ACK1-0
: Command
: 79
: Acknowledge 1 II
: +12 V
I
I
I
I
I
I
I
: 40
: ACK2-0
: Command
: 80
: Acknowledge 2 :
: +12 V
I
I
I
I
I
I
:I 36
I
I
I
I
4170 INSTRUCTION
I
I
I
I
---
---
---
---
12-7
SECTION 12
THEORY OF OPERATION
PROCESSOR BUS
The Processor board consists of circuitry that performs the
followine functions:
o
Processes system firmware commands and data along with
interrupt data from on and off the board.
o
Accepts interrupt signals from the host computer
communications port, the front panel, peripheral devices and
other circuitry connected to the System bus, and from other
circuitry on the Processor board itself.
o
Transmits and receives data from the System bus.
o
Stores the system firmware and the 4170 initialization
information.
o
Provides control and status signals primarily for the
microprocessor (MPU).
o
Communicates with the host computer using the RS-232
communication standard.
o
Communicates with the front panel.
Each of these functions is performed by the blocks shown in the
simplified block diagram of Figure 12-3.
12-8
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
PROCESSOR
BOARD
TO HOST 112l:!2~>1
COMPUTER '"
(If used)
RS-232
PORT
(RC1, SCD)
(A2-5)
CONTROL, STATUS,
AND TIMING BLOCKS
(BCG, BTD, MC,
TG, PT & BRG, SI,
BTL,ADE)
(A2-l,3,5)
INTERRUPT
CONTROLLER
(lC)
(A2-2)
AD10-ADS
INTERFACE
BETWEEN
LOCAL!
MPU BOARD
BUSSES
AND MAIN
PROCESSOR
BUS
(ADR,DD!R,
BCD)
MOTHER
BOARD
(Al,2)
(A2-2)
FRONT
1zm~~
PANEL '"
FRONT
PANEL
PORT
(FPC)
(A2-4)
MEMORY
(ROMS)
(A2-3)
I
I
I
I
I
I
(NVR)
(A2-4)
MICROPROCESSOR
AND
NUMERICAL
COPROCESSOR
(MPU, FPU)
(A2-l,2)
(4513)4685-42
Figure 12-3. Simplified Block Diagram of the Processor Board.
4170 INSTRUCTION
12-9
SECTION 12
THEORY OF OPERATION
MICROPROCESSOR (MPU) AND NUMERIC CO-PROCESSOR (FPU)
This block consists of the microprocessor (MPU), and the numeric
floating point co-processor (FPU). Both 16-bit processors
t ime-mul,tiplex their ADO-1 through AD19-1 lines; allowi ng the
lines to b~ used for either address or data information. The MPU
and FPU output three internal state identifiers (SO-O, S1-0, and
S2-0), which identify to the bus the type of processor cycle being
run and are used by blocks of circuitry on the Processor board to
synchronize their operations with the MPU and FPU. Inputs to the
block are primarily a clock signal, a reset signal, a ready
signal, and an interrupt signal to the MPU from the Interrupt
Controller.
INTERRUPT CONTROLLER
The Interrupt Controller circuitry consists primarily of the
Peripheral Interrupt Controller (PIC). This circuit determines
which of the eight possible interrupting sources is to be
serviced if more than one source requests servicing at one time.
Sources can be other boards in the 4170, such as the
Three-Port Peripheral Interface (3PPI) board, or internal
Processor board circuitry, such as the front panel port, FPU, or
host computer port. The MPU communicates with the interrupt
controller block through the Process data bus, DO-1 through D7-1.
The PIC is programmed by the MPU shortly after the 4170 is
powered up. The MPU cart also read the current status of the PIC
and change its mode of operation by reprogramming its internal
registers.
PROCESSOR AND SYSTEM BUS INTERFACE
The primary inputs to the Processor board and System Bus
Interface circuitry are the lines on the multiplexed Processor
address data bus (ADO-1 through AD19-1), which are connected
directly to the MPU and FPU. The ADO-1 through AD19-1 signal
lines carry, at different times, data and address information.
This block separates the data and address information into the
following four distinct buses: DO-1 through D15-1, the Processor
and Co-processor data bus; AO-1 through A19-1, the Processor and
Co-processor address bus; DATO-1 through DAT15-1, the System data
bus; and ADRO-1 through ADR19-1, the System address bus. This
block also outputs control and status signals onto the System
bus.
12-10
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
SYST~M
MEMORY
There are approximately 32-thousand bytes of ROM in the System
Memory circuitry on the Processor board. The Processor data and
address buses connect to this block. Memory is addressed using
the Processor address bus, and the selected data is placed on the
Processor data bus. The System Memory also includes non-volatile
RAM where setup parameters are retained when the 4170 power
is off.
CONTROL, STATUS, AND TIMING
This circuitry consists of MPU and FPU control, status detection,
and timing functions. Refer to the Processor board schematic
diagrams to reference the circuit descriptions that follow.
The MPU Control Logic generates the 4.9152 MHz clock signal for
the MPU and FPU. The block also synchronizes the reset signal and
ready signal inputs of the MPU and FPU.
The,Bus Transfer Logic provides signals that inform bus masters
and slaves whether they can use the System bus.
Priority-determining logic on the Motherboard works in
conjunction with this circuitry to establish bus mastership.
The Addr~ss Decoding circuitry creates signals from address bits
A12-1 through A7-1 and A9-1 through A19-1 which indicate what area
of I/O or memory address space that data is to be sent or
rece i ved .
The Bus Timeout Detector detects when a slave device fails to
respond with an acknowledge signal (ACK1-0) to a command from any
bus master device. If the circuitry does detect this failure to
respond, it drives its own acknowledge signal (ACK1-0) onto the
bus sets an error status bit, and causes an interrupt to be
generated. This action prevents the bus from "hanging", that is,
remaining in a state that cannot be responded to by any master or
slave device.
The Status Input circuitry allows the MPU to read two Processor
board status signals, LSO-O and OBIOD&F-O. This circuitry also
outputs STATEN-1 which is input to the Bus Timeout Detector.
The Bus Clock Generator produces a clock signal (BCLK-O) for the
System bus.
4170 INSTRUCTION
12-11
SECTION 12
THEORY OF OPERATION
The Microprocessor Timing Generator receives three signals from
the MPU and FPU (SO-O, 81-0, and 82-0) that indicate whether the
MPU is: acknowledging an interrupt; reading or writing to I/O or
memory space; fetching an instruction; in a halt state; or in a
no-bus-cycle state. This information synchronizes operations both
on and off the Processor board.
The Programmable Timer and Baud Rate Generator consists of a
Programmable Interval Timer that primarily provides variable
timing functions. This circuitry provides the transmit baud rate,
a firmware interval timer, the bus timeout interval, and the
RS-232 intercharacter delay.
HOST COMPUTER PORT
The Host Computer Port circuitry communicates with the host
computer by means of RS-232 signals. A programmable integrated
circuit accepts RS-232 control and data signals from the host
computer and then converts this information to parallel data and
interrupts for use by the MPU. In addition to various control and
status signals, this block outputs data on the Processor data
bus, DO-1 through D15-1.
The RS-232 State Change Detector is related to the Host Computer
Port. This circuit detects state changes on the incoming RS-232
status lines and generates interrupts if changes occur.
FRONT PANEL PORT
The Front Panel Port circuitry accepts data from the front panel.
The Peripheral Interface Microcomputer (PI MPU), dedicated to
servicing the front panel, processes this data and outputs it to
part of the Processor data bus, DO-1 through D7-1. The PI MPU
also out~uts various control signals, including an interrupt
(KBINT-O), which reaches the MPU after being processed by the
Interrupt Controller circuitry.
DETAILED PROCESSOR BOARD CIRCUIT DESCRIPTIONS
Circuitry that appears on the Processor board schematics is
described here. For each block, the description follows the same
format: Schematic number, Purpose, Signals (input and output),
Description, and Operation. The intent of this format is to give
the reader a clear understanding of each block. This formatting
also serves the purpose of quick reference once the circuitry is
understood.
12-12
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Refer to Figure 12-4 for an overall view of how the circuit blocks
communicate. Note that the Address Drivers and Data
Drivers/Receivers blocks perform similar tasks for the address
and data information that the r~lPU emits. They either output this
information to the System bus or the Processor bus, depending on
the state of control signals from the MPU and FPU.
In the description of some blocks of circuitry, parentheses are
used to enclose names that are pin assignments. These names are
usually taken from the input or output pin name of a Large Scale
Inte'7ration (LSI) circuit. Some examples are (CLK-1), (OSC-1),
and ,RDY-1) in the Microprocessor Control block.
Eight of the nineteen blocks have an LSI circuit as a main
component. Many of these are programmable and all are
multipurpose. The LSI circuits are used in a definite
configuration (and in some cases a definite mode) in the design
of the Processor board. The block descriptions do not give
complete accounts of the unused modes and/or configurations of
these LSI circuits. However, reference to further information,
along with the abbreviations used for these LSI circuits, is
given in Table 12-2.
Table 12-2
MANUFACTURERS' NOMENCLATURE FOR ICs
: NAME
: ABBREVIATION : NUMBER
: Programmable
: Interrupt Controller
: PIC
: 8259A (a) :
: Microprocessor
: fvIPU
: 8086 (a)
: Numerical Co-processor
: FPU
: 8087 (a)
: Clock Generator and Driver
: CGD
: 8284A (a) :
: Eus Controller
: BC
: 8288 (a)
: Front Panel Controller MPU
: FPC I"lPU
: 8041 A (a) :
: Programmable Interval Timer
: PIT
: 8253 (a)
: Programmable Communications Interface : PCI
: 2661 (b)
I
I
I
I
I
I
(a) Description in Intel Component Data Catalog 1982
(b) Description in Signetics Data Manual 1982
4170 INSTRUCTION
12-13
SECTION 12
THEORY OF OPERATION
Figure 12-4. Processor Board Block Diagram.
12-14
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
MPU (SCHEMATIC A2-1) AND FPU (SCHEMATIC A2-2)
The MPU controls the general-purpose reading and writing of data
and address information for the entire 4170 system in conjunction
with the FPU which performs numerical computations for the MPU.
The NPU gives up control of the System bus in favor of other bus
masters when necessary.
The input sip,nals are:
o
CLK-O (Clock). Di rect 4.9152 r·1Hz clock signal from the Clock
Generator. (a)
o
RST-1 (Reset). Di rectly input from the Clock Generator.
Causes the MPU or FPU to stop current activity, but restarts
execution when it p,oes false. RST-1 must be true for at
least four clock cycles to stor the MPU and FPU.(a)
o
RDY-1 (Ready). Directly input from the Clock Generator.
When true, RDY-1 signals that the addressed memory or I/O
device will complete its data transfer.(a)
o
TEST-O (Test). If TEST-O is true, execution continues. If
TEST-O is false, the ~PU inserts idle states between bus
cycles until TEST-O goes true. TEST-O may be driven by an
input from Test Connector J104 or by the BUSY-1 signal from
the F' PU . ( b )
o
NMI-O (Non-Haskable Interrupt). When true, the MPU stops
normal execution and jumps to a predetermined subroutine in
firmware. Software cannot disable this interrupt. NMI-O is
triggered on the low to high transition. This signal is
available only on Test Connector J104.(b)
o
INTR-1 (Interrupt). When true, after the last clock cycle of
the current instruction, the MPU enters an interrupt
acknowledge operation. INTR-1 may be disabled by software.
(a) Input to both the ~PU and FPU.
(b) Input to the ~iPU only.
4170 INSTRucrrrON
1.2-15
SECTION 12.
THEORY m' OPERATION
.
The output signals are:'
0'
ADO~1 through AD19-1 . (Processor Address Data Bus Bits 0
through 19). These bits carry both address and data
information at different times. The Address Drivers .
circuitry outputs this information to the Processor hus or
System bus according to its destination. (a)
o
LOCK-O (Lock). Prevents other bus masters from gaining
control of the System bus. LOCK-O is activated when special
lock prefixes are ~dded to firmware instructions.(b) .
o
RD-O (Read). When true, indicates that the MPU is performing
a memory or I/O read cycle, depend ing on whethe r 82-0 is
false (memory) or true (I/O).(b)
o
GSO-1 and QS1-1. Used to provide FPU with the following
status information from the MPU instruction queue: no
operation; first byte of op code from queue; empty the
queue; or subsequent byte from queue. These signals are also
available to the r.tlPU from Test Connector J1 04. (a)
o
RQ-O/GTO~O (Req~est/Gr~~t 0). Used by the FPU to gain
control of the local bus from the MPU for operand transfers.
Also available t.o the NPU from Test Connector Jl04. (a)
o
RQO/GT1-0 (Request/Grant 1). Not used in normal operation
but is avail able. on J104 to the l\1PU and on TP40 from FPU. (a)
o
SO-O, S1:-0, and 82-1 (Status Bits 0 through 2). These bits,
when taken together, show which of eight states the .MPU is
in: interrupt acknowledge; I/O read; I/O write; halt; code
access; memory read; I/O read; or passive. In the FPU, these
bits are used to show one of.three possible states: read
memory; ~rite memory; or passive.(a)
o
BHE-O (Byte High Enable). Duririg NPU or FPU State T1, 13HE-O
enables the high byte of data onto D8-1 through D15-1for
read, write, and interrupt acknowledge cycles.(a)
o
BUSY-1 (Busy). Output from the FPU to the MPU which is
tested by the MPU "Wait" instruction and is used to
synchronize the operation of the FPU with that of the
r,jPu. ( b)
o
12-16
INT-1 (Interrupt). Us ed to create a 1 evel 7 interrupt
through the Interrupt Controller when FPU generates an
exception (abnormal or error condition) .(c)
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
(a) Output of both MPU and FPU.
(b) Output of the MPU only.
(c) Output of the FPU only.
The MPU is a general-purpose microprocessor that has an address
space of one megabyte. It operates at 4.9152 l"'lHz and manipulates
data in 8-bit or 16-bit word sizes (Figure 12-5).
The FPU is a specially designed co-processor which performs
floating point numerical computations for the MPU. It also
operates at 4.9152MHz (Figure 12-6).
4170 INSTRUCTION
12-17
SECTION 12
THEORY OF OPERATION
BUS INTERFACE UNIT
EXECUTION UNIT
I
REGISTER FILE
DUTY CYCLE, una MHz.
1>".)
lOCK
(20)
I
SEGMENT
REGISTERS
AND
INSTRUCTION
POINTER
(5 WORDS)
DATA.
POINTER. AND
INDEX REGS
CLOCK INPUT. DIRECT INPUT FROM
elK ON CLOCK GENERATOR. 33%
RELOCATION
REGISTER FILE
WHEN LOW, PREVENTS OTHER BUS
MASTERS FROM CONTROLLING
THE SYSTEM BUS. SOFtWARE
ACTIVATED.
RESET, WHEN HIGH, MPU STOPS
RST
FDA FOUR CLOCK CYCLES, WHEN
LOW, RESTARTS EXECUTION.
(21)
READY, WHEN HIGH, MEMORY OR
ROY
IU}
Ri5
(32)
WHEN LOW, INDICATES A MEMORY
READ IS IN PROGRESS, IF 52 IS
HIGH, OR AN 110 READ, IF 52 IS
Ito ACKNOWLEDGES IT WILL
COMPLETE ITS DATA TRANSFER.
FIRMWARE "WAIT' INSTRUCTION
LOOKS AT TEST. IF HIGH, MPU
GOES INTO IDLE STATE. IF LOW,
EXECUnON CONTINUES.
TEST
NON-MASKABLE INTERRUPT. LOW
TO HIGH CAUSES AN INTERRUPT
AT END OF CURRENT
INSTRUCllON.
NM)
INTERRUPT. HIGH LEVEL
TRIGGERED AND SAMPLED DURING
LATEST CLOCK CYCLE OR EVERY
INSTRUCTION. SOFTWARE
MASKABLE.
INTR
(18)
iii!!Sr
LOW. FDA PROCESSOR BUS ONLY.
1a·BITALU
as..,
NOT USED.
RQIGTO-1
NOT USED.
(23)
so:2
(2e·28)
A19 /S e
A1~/S3
FLAGS
STATUS LINES. THESE INDICATE
THE EIGHT STATES OF UPU
BUS
INTERFACE
UNIT
DURING T1, T2, n. PASSIVE (1,1,1)
DURING T3, TW. BUS CONTROLLER
USES THESE TO GENERATE ALL I/O
AND MEMORY CONTROL SIGNALS.
PROCESSOR BOARD USES THEM
FOR LOCAL ACCESSES.
(171
BHE
(34)
BYTE HIGH ENABLE. USED TO
ENABLE 08-16 ON READ, WRITE,
AND INTERRUPT ACKNOWLEDGE
CYCLES.
A16-19
(39·35)
CARRY FOUR MOST StGMFtCANT
BITS OF A 2O-BIT ADDRESS
MEMORY OPERATtON.
INSIGNIFICANT IN A 16-BIT I/O
OPERATION.
A~15
TIME·MULTIPLEXED IfO/MEMORY
ADDRESS (DURING T1) AND DATA
(DURING T2, 13, TW, T4).
(18·2,38)
~f
AD ,5 -ADO
DTIR.DEN.ALE
a·BYTE
INSTRUCTION
QUEUE
~----~~----------~~------------,
.NT
NM.
HOLD
HlDA----~~~______~____~----_,----~~~
elK
A.
Pin Descriptions.
RESET
READY
MN/MX
OND
vee
B. Functional Block Diagram.
P1sure 12-5. MPU Functional Block Diagram and Pin Descriptions.
12-18
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
vee
vss
"4/014
A15/015
A13/013
A16/S3
A12/012
A17154
A11/011
A18155
A10/D10
A19/56
A9/01
SHE/51
A8/DI
RQ/GT1
A7/07
INT
A6/D8
RO/GTo
AS/05
He
A4/04
He
DATA"--"
so
A3/D3
1.1/01
ii
So
AOIDO
QS.
(7)
Ne
QS1
(6)
12/02
Ne
READY
vss
RESET
STATUS
Ne
= NO CONNECT
ADDRESS
ADDRESSING &
BUS TRACKING
EXCEPTION
POINTERS
I
I
I
L A.
T
A
G
BUSY
elK
Pin Descriptions.
B.
Functional Block Diagram.
(5)
(4)
REGISTER STACK
W
0
R
D
(3)
(2)
-
(1)
(0)
--
-
'-
80 BITS
-
-
-- -
-
-
~
'igure 12-6. FPU Functional Block Diagram and Pin Descriptions.
4170 INSTRUCTION
12-19
S:F~CTION 12
THEORY OF OPERATION
The Bus Cycle
The MPU bus cycle consists of a variable number of clock states
of approximately 200ns each. The different kinds of clock states
that can occur areT1, T2, T3, T4, Tw, and Ti. The minimum
duration bus cycle is T1, T2, T3, and T4, in that order and one
immediately after the other. However, some operations require
that one or more clock states be inserted between T3 and T4.
These states are Tw -- wait states. Also, sometimes states are
inserted between bus cycles. These are Ti -- idle states. The MPU
uses idle states for internal "housekeeping" operations. The :F'PU
operates is such a manner as to enhance the operation of the MPU
and greatly expand system capab il i ties and speed of operation.
However, the }<"PU is not available to the programmer as an
independent ~ntity, but rather as a part of the CPU module.
MPU Internal States
During normal operation, the MPU performs one of eight types of
bus cycles. These cycles are encoded in MPU outputs SO-O, S1-0,
and S2-0. The cycle that corresponds with each of the eight bit
patterns of SO-O, S1-0, and S2-0 is shown in Table 12-3, Status
Word and Bus Controller Commands. This cycle status information
is available durin a states T2, T3, and Tw. SO-O, S1-0, and S2-0
become binary 111 ~inactive) during 14 and last through any Ti
states. The FPU may perform two of the same bus cycles as the
TvIPU, read memory and wr i te memory. Dur ing these FPU cyc les, the
status of SO-O, S1-0, and S2-0 is the same as it would be during
the identical MPU cycles.
The major operations of the MPU or FPU are reading and writing to
memory or I/O address space, reset and initialization, and
interrupt operations.
Memory and I/O Address Space Access
During T1, the MPU or FPU outputs an address. The MPU state
information on SO-O, S1-0, and 82-0 becomes available and the
address is latched during T2. Also, during T2, if the operation
is a read operation, the direction of the data bus is changed.
Data is then read from or written to memory or I/O locations
during T2, T3, and Tw. The information on SO-O, S1-0, and 82-0 is
used by different functional blocks of circuitry on the Processor
board if the read or write access is local. Otherwise the SO-O,
S1-0, and S2-0 information is converted directly into the I/O and
memory access commands for the System bus by the Command Driver.
12-20
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Reset and Initialization
MPU and FPU reset occurs when (RST-1) from the Microprocessor
Control circuitry goes true. It must stay true for at least four
clock cycles. The MPU executes no operations as long as (RST-1)
is true. When (RST-1) goes false, an internal reset sequence is
triggered that lasts about ten clock cycles. After this, the MPU
and FPU fetch the instruction in location FFFFO. There must
be at least 50(micro)s between power-up and the high to low transition
of RST-1 .
Interrupt Operations
There are two hardware interrupts to the MPU -- NMI-O and INTR-1.
NMI-O is the non-maskable interrupt and INTR-1 is the maskable
interrupt request input.
Non-Maskable Interrupt. If NMI-O goes from low to high
and Non-Maskable Interrupt goes false for more than two clock
cycles, NMI-O is latched by the MPU and is serviced immediately
after the current instruction is completed. NMI-O is only
available on the processor Board Test Fixture Connector and is
not part of the System bus.
Maskable Interrupt. When INTR-1 goes true during the
clock Maskable Interrupt cycle preceding the end of the current
instruction, the MPU is triggered into a response sequence. The
MPU executes two consecutive interrupt acknowledge cycles (two
bus cycles). (See Interrupt Controller description.) LOCK-O is
held true from T2 of the first cycle to T2 of the second cycle.
During the second bus cycle, a byte is fetched from the PIC. This
byte specifies what source requires the interrupt and also
addresses a location in ROM from which the appropriate interrupt
service routine can be determined.
INTR-1 can be disabled by resetting a status bit in the MPU by
means of software instructions.
INTERRUPT CONTROLLER (SCHEMATIC A2-2)
The Interrupt Controller handles a maximum of eight System bus
and Processor board interrupt signals (INTO-O through INT7-0) and
determines the priority of each interrupt signal in relation to
the others. The Interrupt Controller also has the capability of
addressing eight other optional Programmable Interrupt
Controllers.
4170 INSTRUCTION
12-21
SECTION 12
THEORY OF OPERATION
The input signals are:
o
COMINT-O (Communications Interrupt). Signals that the RS-232
Communications Interrupt has just received a character.
o
TIMERINT-O (Timer Interrupt). Indicates that at least one of
these signals is active: TIMR1-1, (TXEfvIT-O), (TXRDY-O), a.n
RS-232 status change interrupt, or OUTO-1.
o
AWT-O (Advanced Write). Advanced write signal for Processor
board c i rcui ts .
o
INTO-O through INT7-0 (Interrupt 0 to 7). System bus
interrupt signals. (COMINT-O can generate INTO-O; KBINT-O
can genera.te INT4-0, BTINT-O and TIMERINT-O can generate
INT5-0, and FPU Interrupt can generate INT7-0).
o
BUSAEN-O (Bus Address Enable). Shows that the
master of the System bus.
o
INTA-O (Interrupt Acknowledge). Causes the Programmable
Interrupt Controller to place an interrupt routine address
("vectoring information") on the System data bus.
o
OBI08&A-0 (On-Board I/O 8&A). When true enables the
Programmable Interrupt Controller for communication with the
fvI PU .
o
RD-O (Read). Read signal from the MPU.
o
RST-O (Reset). Initializes logic during power-up and system
reset.
o
BTINT-O (Bus Timeout Interrupt). Indicates a Bus Timeout has
occurred.
12-22
~1PU
is bus
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The output signals are:
o
AD8-1, AD9-1, and AD10-10 (MPU Address/Data Bits 8 through
10). These carry the addresses of a maximum of eight other
optional Programmable Interrupt Controllers.
o
INTR-1 (Interrupt). Interrupt signal to the MPU.
o
1STINTA-0 (First Interrupt). Indicates to the MPU that no
data will be transferred.
o
OBINTA-O (On-Board Interrupt). Indicates that the
Programmable Interrupt Controller is placing data on DO-1
through D7-1. Also combines with other signals in the
Address Decoding circuitry to produce OBDEN-O.
The heart of the Interrupt Controller is the Programmable
Interrupt Controller (PIC) integrated circuit. The PIC receives
interrupt signals (INTO-O through INT7-0) and INTA-O from the
System bus, and control signals from other circuits on the board.
It receives and transmits data from the Processor data bus, and
it outputs INTR-1, OBINTA-O, and AD8-1 through AD10-1 (which can
carry addresses for eight other optional Pics). The other
circuitry in the Interrupt Controller inverts and buffers
INTO-O through INT7-0, provides enabling for the AD8-1 through
AD10-1 drivers, and produces 1STINTA-0. Also, BUSAEN-O and INTA-O
are NANDed for the INTA-O input of the PIC.
Programmable Interrupt Controller
This integrated circuit consists of five main blocks of
circuitry. They are the local data bus buffer, the interrupt
registers and logic, the control logic, the read and write logic,
and the cascade buffers and comparator (Figure 12-7 and Figure
12-8) .
4170 INSTRUCTION
12-23
SECTION 12
THEORY OF OPERATION
00-7
IR0-7
INTERRUPT
PRIORITY
LOGIC
AND
REGISTERS
INTA
CONTROL
LOGIC
CS
\/R
RO
"0
CASCADE
BUFFERS
AND
COMPARATOR
SP/EN
"08-1.0
INT
READ
AND
WRITE
LOGIC
(3820)4517-3
Figure 12-7. Programmable Interrupt Controller Block Diagram.
12-24
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
AO ADDRESS LINE. USED WITH
CS, WR, AND RD TO
COMMUNICATE WITH THE 8086.
AO
BIDIRECTIONAL DATA BUS,
CONTROL, STATUS, AND
INTERRUPT VECTOR DATA IS
SENT AND RECEIVED.
DO-07
INTERRUPT REQUESTS. A
REQUEST IS TRIGGERED BY A
LOW-TO-HIGH OR HIGH STATE.
IRO-IR7
INTERRUPT ACKNOWLEDGE
INPUT ENABLES VECTORING
DATA ONTO DO-D7.
INTA
CHIP SELECT. INPUT ENABLES
THE MPU TO READ AND WRITE PIC
COMMAND WORDS.
CS
WRITE. INPUT ALLOWS PIC
COMAND WORDS TO BE
RECEIVED FROM MPU.
WR
READ. INPUT ENABLES MPU TO
READ PIC STATUS RELEASED ON
DO-D7.
RD
SP/EN
INT
CAS2
CAS1
CASO
SLAVE PROGRAM/ENABLE
BUFFER. GOES LOW WHEN PIC
HAS DATA TO SEND.
INTERRUPT. HIGH ON RECEIVING
A VALID INTERRUPT REQUEST.
} CASCADE LINES. OUTPUT TO
AD8-AD1 0, USED FOR SLAVE
PICS ON OTHER BOARDS.
3820-11A
Figure 12-8. Programmable Interrupt Controller Pin Descriptions.
4170 INSTRUCTION
12-25
SECTION 12
THEORY OF OPERATION
Local Data Bus Buffer. Eight bits, DO-1 through D7-1,
are transmitted and received by this tri-state buffer. The system
firmware su~plies controlwo~ds and status infor~ation to the PIC
through this buffer. An internal bus connects the data bus buffer
to the Interrupt Priority Logic Registers circuitry.
Interrupt Priority Logic and Registers. There. are three
registers in addition to the priority logic in this circuitry.
The priority logic determines from the register holding INTO-O
through INT7-0 bits (that are requesting service) which bit has
the highest priority. This hit is strobed into the corresponding
bit position in th~ in-service register. Firmware uses the third
register to mask the INTO-O through INT7-0 bits in the requesting
service register. This masking changes the priority of the INTO-O
through INT7-0 ihtetrupt signals.
Control Logic. When the system signal INTA-O goes true,
it causes the control logic to transmit interrupt service routine
addresses to the System bus via the local data bus buffer. The
control logic also issues INTR-1 to the MPU if it receives a
signal from the priority logic.
Read and Write Logic. OBI08&A-0 goes true to enable
reading or writing access to the PIC. If RD-O gpes true, any of
the three registers and the interrupt level of the Interrupt
Priority Logic and Registers circuitry can be output to the
Processor data bus. If AWT-O goes true, firmware can write PIC
control words to registers in the Read and Write Logic circuitry.
AO-1 selects in conjunction with RD-O and AWT-O whether the
interrupt registers or the command word registers are read from
or written to.
Caloade Buffers and Comparator. If other PICs are added
to the system, this circuitry addresses them. These slave PICs
would be controlled by the master PIC on the Processor board.
ADS-1 through AD10-1 would carry the address of anyone of eight
add i ti onal PICs.
There are two phases of operation in the PIC. These are
initialization and normal operation. During initialization, soon
after the 4170 is powered up, the system firmware sends set-up
data and control words to the PIC. After initialization, the PIC
is ready to receive and prioritize the interrupt request signals
on INTO-O through INT7-0.
12-26
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The Interrupt Sequence
The following sequence of events occurs in the normal operation
of the Interrupt Controller circuitry.
1. One or more of the INTO-O through INT7-0 bits goes true.
This sets (because of the inverter) the correspondingbit(s)
in the "interrupt request" register in the Interrupt
Priority Logic and Registers circuitry in the PIC.
2. The PIC determines the priority of these INTO-O through
INT7-0 lines, and sends INTR-1 to the MPU if one of the
INTx-O lines is a higher priority interrupt request than any
currently being processed.
3. The
MPU receives the INTR-1
on its
IN~A
signal and responds with a low
line.
4. The PIC now sets the highest priority bit in its in-service
register and the corresponding interrupt request register
bit is reset. No signals are sent from the PIC at this time.
5. Now the IvlPU sends a second low on INTA-O. This causes the
PIC to place an eight-bit interrupt-service-routine
(vectoring) address on the Processor data bus, DO-1 through
D7-1 .
6. The MPU reads this vectoring address on the Processor data
bus and begins the service routine. The Interrupt Controller
is now done with this interrupt cycle.
If the duration of an interrupt request on INTO-O through INT7-0
is not long enough to be true at step 4, the PIC automatically
issues a vectoring address as if INT7-0 were true.
1STINTA-O and Cascade Addresses for Slave PICs
During the interrupt sequence, the MPU sends two INTA-O signals.
At the time of the first INTA-O, 1STINTA-0 is generated by a
toggling JK flip-flop and a NAND gate. At the time of the second
INTA-O, the cascade address (AD8-1 through AD10-1) of the slave
PIC is driven onto the Processor address data bus. This is
accomplished by the same toggling JK flip-flop and another NAND
gate.
ADDRESS DRIVERS (SCHEMATIC A2-2)
The Address Drivers latch 20 bits of address and BHEN-O, and then
drive these onto the Processor address bus during a local read or
write, or onto the System bus during a system read or write.
4170 INSTRUCTION
12-27
SECTION 12
THEORY OF OPERATION
The input signals are:
o
SO-O, S1-0, and 82-0 (Status 0, 1, & 2). Informs the
Processor board whether the MPU is in an interrupt
acknowledge, read I/O, write I/O, halt, code access, read
memory, or write memory state; or if the FPU is in a read or
write state.
o
ADO-1 through AD19-1 (Ad dress and Data Bi ts 0 through 19).
Output directly from the l\'IPU or FPU. ADO-1 through AD19-1
carries both address and data information in
time-multiplexed mode.
o
BHE-O (Byte High Enable
t1PU and FPU.
a
ALE-1 (Address Latch Enable). Enables the local address
latches.
o
BUSAEN-O (Bus Address Enable). Enables the outputs of the
system address latches.
Unbuffered). Directly from the
The output signals are:
a
1S0-0, 1S1-0, and 1S2-0 (1atched Status 0, 1, & 2). Informs
the system what internal state the MPU or FPU is in. Refer
to SO-O, S1-0, and S2-0.
o
AO-1 through A19-1 (Processor Address Bus). Carries address
information for the Processor board.
a
ADRO-1 through ADR19-1 (System Address Bus). Carries address
information for the system.
a
1BHE-O (Latched Byte High Enable). Processor board
equivalent of BHEN-O.
o
BHEN-O (Byte High Enable). Enables DATS-1 through DAT15-1 on
read, write, or interrupt acknowledge cycles.
The Address Drivers circuitry consists of six packages of D-type
latches. These form two sets of latches. One set outputs 1S0-0
through 1S2-0, LBHE-O, and the Processor bus address bits. The
other set outputs BHEN-O and the System bus address bits.
12-28
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
When the MPU or FPU outputs address information on ADO-1 through
AD19-1 and A1E-1 makes a high-to-low transition, the Processor
bus set latches this data. it also latches SO-O through S2-0 and
BHE-O. Since this set of latches is permanently enabled for
output, the latched data appears immediately as AO-1 through
A9-1, 1S0-0 through 1S2-0, and 1BHE-0.
The System bus set of latches operates like the Processor bus
set, except that the latches are not permanently enabled for
output. BUSAEN-O provides this enabling function.
DATA DRIVERS/RECEIVERS (SCHEMATIC A2-2)
The Data Drivers/Receivers transfer MPU or FPU data on ADO-1
through AD15-1 to or from either DO-1 through D15-1, the
processor data bus, or DATO-1 through DAT15-1, the System data
bus.
The input signals are:
o
ADO-1 through AD15-1 (JViultiplexed Address and Data Bits).
Address and data bits directly output from the MPU and FPU.
o
DT/R-O (Data Transmit/Receive). Data bus direction control.
o
DEN-1
o
SP/EN-O (Enable Buffer). Enabling signal from the PIC.
o
OBDEN-O (On-Board Data Enable).
(Data Enable) .
The output signals are:
o
DO-1 through D15-1
(Processor Data Bus Bi ts) .
o
DATO-1 through DAT15-1
(System Data Bus Bi ts) •
Four bus transceivers and one NAND gate make up the Data
Drivers/Receivers circuitry. The bus transceivers are divided
into two sets. One handles DO-1 through D15-1, the Processor data
bus, and the other set handles DATO-1 through DAT15-1, the System
data bus. Data bits are transmitted and received in each set.
If OBDEN-O goes true and DT/R-O is false, the data bits on ADO-1
through AD15-1 are transmitted to DO-1 through D15-1. But if
OBDEN-O is true and DT/R-O goes true, data on DO-1 through D15-1
is transmitted back through the transceivers and becomes ADO-1
through AD15-1, which is received directly by the MPU and FPU.
4170 INSTRUCTION
12-29
SECTION. 12
THEORY OF OPERATION
Data is transmitted to the System data bus, DATO-1 through
DAT15-1, when DT/R-O goes false, DEN-1 is true, and SP/EN-O is
false. If DT/R-O is true during data transmission, the System bus
bits become ADO-1 through AD15-1.
BUS COMMAND DRIVER (SCHEMATIC A2-2)
The Bus Command Driver decodes MPU and FPU status signals in
order to generate System bus read, write, and interrupt commands.
The Bus Command Driver also generates control signals for the
Processor board address and data drivers and latches.
~he
input signals are:
o
SO-O, S1-0, and 82-0 (Status 0 through 2). Three lines that
indicate what type of cycle the MPU is performing: I/O read,
I/O write, memory read, memory write, halt, or interrupt
acknowledge; or, in the case of the FPU, memory read or
memory write.
o
BUSAEN-O (Bus Address Enable). Shows that the MPU is System
bus master, when true.
o
OBADR-O (On-Board Address). When true, ind~cates that the
Processor board circuitry is being accessed. When false,
indicates that the System bus is being accessed.
o
CLK-1 (Clock). Synchronizing clock signal for the Processor
board.
12-30
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The output signals are:
o
DT/R-O (Data Transmit/Receive). Processor and System data
bus transmit and receive.
o
ALE-1 (Address Latch Enable). Enables the Processor and
System bus address latches.
o
(MCE-1) (Master Cascad e Enable). Clocks a JK fl ip-flop in
the Interrupt Controller circuitry that enables three line
drivers to output AD8-1 through AD10-1 (an address for one
of eight optional Interrupt Controllers).
o
(DEN-1) (Data Enable). Enables system data drivers if
OBINTA-O is false.
o
INTA-O (Interrupt Acknowledge). Signals the Interrupt
Controller to place vectoring data on the System data bus.
0
IOWC-O (I/O Write Command) .
0
AIOWC-O (Advanced I/O Write Command) .
0
IORC-O (I/O Read Command) .
0
MRDC-O (Memory Read Command) .
0
MWTC-O (Memory Write Command) .
0
AMWC-O (Advanced Memory Write Command).
The Bus Command Driver circuitry consists solely of the Bus
Controller. This device combines control logic, MPU status
decoder, control signal generator, and Command Generator
circuitry. Figure 12-9 shows the signal paths among these blocks
of circuitry. See also Figure 12-10.
4170 INSTRUCTION
12-31
SECTION 12
THEORY OF OPERATION
rOB
AEN
CEN
CLK
_____
~-.
CONTROL
LOGIC
1 - - - - - - 1 - - - - -__ DT IR-I/J
ALE
MCE
GENERATOR~-~----__ DEN
CONTROL
SIGNAL
~-~----__
COMMAND
GENERATOR
SI/J-2
MPU
STATUS
DECODER
rNTA
~----I-----
__ rOllc
~-~----
__
ArOIiC
rORC
~----I-----__ MRDC
1 - - - - - - 1 - - - - -__ MIITC
~----I-----__ AMIIC
(3820)4517.4
Figure 12-9. Bus Controller Block Diagram.
12-32
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
DT/R
DATA TRANSMIT/RECEIVE.
DETERMINES DIRECTION OF DATA
TRANSMISSION.
ALE
ADDRESS LATCH ENABLE.
STROBES ADDRESS INTO
LATCHES. LATCHING ON HIGH TO
LOW.
SO-2
MCE
MASTER CASCADE ENABLE.
PLACES CAS0-2 ON AD8-AD10
DURING AN INTERRUPT SEQUENCE.
CLK
DEN
DATA ENABLE. DATA TRANSCEIVER
ENABLE.
INTA
INTERRUPT ACKNOWLEDGE.
SIGNAL TO INTERRUPTING DEVICE
THAT IT CAN DRIVE VECTOR
INFORMATION ONTO BUS.
ADDRESS ENABLE. ENABLES
COMMAND OUTPUTS INTA, 10WC,
AIOWC, 10RC, MRDC, MWTC, AND
AMWC.
AEN
COMMAND ENABLE. ENABLES
ALL COMMAND OUTPUTS PLUS
DEN AND MCE.
CEN
STATUS INPUT 0-2. DECODED BY
THE BC TO PRODUCE COMMAND
AND CONTROL SIGNALS.
4.9152 MHz MPU CLOCK.
10WC
AIOWC
10RC
I/O WRITE COMMAND.
ADVANCED I/O WRITE COMMAND.
I/O READ COMMAND.
MRDC
MEMORY READ COMMAND.
MWTC
MEMORY WRITE COMMAND.
AMWC
ADVANCED MEMORY WRITE
COMMAND.
3820-13A
Figure 12-10. Bus Controller Pin Descriptions.
4170 INSTRUCTION
12-33
SECTION 12
THEORY OF OPERATION
Control Logic
IOB-1 is permanently tied low. This sets up the control logic
enabling the command generator to output command signals
(AIOWC-O, MWTC-O, MRDC-O, etc.) no earlier than 105ns after
BUSAEN-O goes true. When BUSAEN-O is false, the control logic
tri-states (places in a high impedance condition) the command
signal outputs.
OBADR-O also affects command signal output. When OBADR-O is true,
all command signal outputs in addition to the (DEN-1) and (fvICE-1)
outputs are inactive. If OBADR-O goes false, these same outputs
are enabled.'
CLK-1 synchronizes the operations within the Bus Controller.
Control Signal Generator
This part of the Bus Controller outputs DTIR-O, ALE-1, (MCE-1),
and (DEN-1). These signals control, respectively, direction of
data transmission, enabling of the address latches, enabling of
AD8-1. through AD10-1 (additional Interrupt Controller addresses),
and enabling of System bus data drivers if OBINTA-O is false.
When BUSAEN-O is true (MPU is bus master) and OBADR-O is false
(MPU is not accessing a device on the Processor board), the
Control Signal Generator activates its control outputs according to
whether SO-O through 82-0 indicate a read, write, or interrupt
cycle. See Figure 12-11 for the sequencing of these signals.
Notes. Notes 1 through 3 and A through V appear in
Figure 12-11.
Figure 12-11 shows five different cycle types -- memory read,
memory write, I/O read, I/O write, and interrupt acknowledge.
Only one type can occur at anyone time.
1. When this line is low, it indicates that one or more of the
status lines (SO-O, S1-0, or 82-0) is true.
2. ADO-1 through AD19-1 are not used by the Bus Controller, but
are drawn to show their relationship to 'ALE-1 (Address Latch
Enable) .
3. (HCE-1) (Master Cascade Enable) occurs only when all three
status lines are true. This signals the Interrupt
Acknowledge cycle.
12-34
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
A,B,C,D.
When the MPU or FPU drives at least one status line
true (SO-O through S2-0), and C1K-1 is false, the Bus
Controller generates A1E-1 and, during an interrupt
acknowledge (INTA-O) cycle, (MCE-1) to strobe the
address latches.
E,F,G
A1E-1 is removed and the data direction is switched
on write commands.
H,I,J,K
(MCE-1) is removed, commands are driven onto the bus,
and writing of data is enabled on a write command.
1,M
Reading of data is enabled on read or INTA-O cycles.
N,O
A write command is initiated on memory and I/O write
cycles. Note that the advanced write line (AIOWC-O
and AMWC-O) is already true.
P,Q,R,S
All commands are moved and the reading of data is
disabled.
T,U,V
Writing of data is disabled and data reverts back to
the MPU and FPU outputs in anticipation of the MPU or
FPU address output for the next cycle.
4170 INSTRUCTION
12-35
SECTION 12
THEORY OF OPERATION
MPU STATE
T4
Tl
T2
T3
T4
ClK
(FROM CLOCK
GENERATOR)
SrzJ-2
ill
ADrzJ-19
®
(FROM MPU) 1
WRITE
DATA VALID
(FROM MPU)
ALE
MRDC,IORC
INTA,AMWC,AIOWC
Q
~------~----
R
r--,f-----+-----
MWTC,IOWC
DEN
(ON READ, I NT A) ________-+__________~---;..~....,j
DEN (ON WRITE)
DT/R
MCE
(READ)
(INTA)
@
382111-14
Figure 12-11. Bus Controller Timing.
12-36
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
MPU Status Decoder
This circuitry decodes the SO-O through S2-0 signals from the MPU
and FPU. These lines indicate the eight different states that the
MPU can be in; or the three different states that the FPU can be
in. Table 12-3 shows for each bit combination what MPU or FPU
state corresponds to it. It also shows the corresponding command
signal for each bit combination. These command signals are output
only when the corresponding SO-O through S2-0 bit combination is
present.
Table 12-3
STATUS WORD AND BUS CONTROLLER COMMANDS
BUS
I
I
00
oJ
I
I
S1
PROCESSOR STATE
<::!2
I
I"
I
I
CONTROLLER COMMAND
: 0
: 0
: 0
: Interrupt Ack.
: INTA
: 1
: 0
: 0
: Read I/O Port
: IORC
: 0
: 1
: 0
: Write I/O Port
: IOWC, AIOWC
: 1
: 1
: 0
: Halt
: none
: 0
: 0
: 1
: Code Access
: MRDC
: 1
: 0
: 1
: Read Nemory
: MRDC (a)
: 0
: 1
: 1
: Write Memory
: MWTC, Ar1WC (a)
: 1
: 1
: 1
: Inactive
: none (a)
(a) Can be generated by the FPU.
Command Generator
This circuitry outputs the command signals: MRDC-O, MWTC-O,
10RC-0, Io\vC-O, ANWC-O, AIOWC-O, and lNTA-O. When BUSAEN-O is
true and OBADR-O is false, the Command Generator outputs the
command signals corresponding to the three bits of SO-O through
S2-0. See Table 12-3, Status Words and Bus Controller Commands,
for this correspondence.
4170 INSTRUCTION
12-37
SECTION 12
THEORY OF OPERATION
READ ONLY MEMORY (ROMS) (SCHEMATIC A2-3)
The ROMs hold a maximum of 32K bytes of system firmware and
outputs this to the Processor bus when addressed.
The input signals are:
o
A1-1 through A112-1 (Processor Address Bits 1 through 14).
A1-1 through A112-1 carry word addresses (A1-1 through A11-1)
and ROM bank selection information (A12-1 through A112-1).
o
ALE-1 (Address Latch Enable). ALE-1 is used to disable the
ROMs when the address is changing.
o
LS1-0 (Latched Status Bit 1). LS1-0 is a read/write status
bit and is used to enable the ROMs during a read operation.
The output signals are:
o
DO-1 through D15-1 (Processor Data Bi ts 0 through 15). rrhese
bits carry data information for the MPU and FPU.
ROM Configuration
The ROM circuitry is made up of eight ROM integ~ated circuits,
arranged in four banks of two RO~s each. rrhe four banks supply a
total of 32K bytes. Each bank contains 4K by 16 bits of memory
address space. The lower byte of each bank outputs DO-1 through
D7-1 and the upper byte outputs D8-1 through D15-1.
Firmware
Starting from
banks contain
(8PRm1s). The
patch code in
the leftmost bank on the schematic, the first three
system firmware in erasable/programmable ROHs
fourth bank contains a firmware jump table and
EPROMs.
Straps
There are three kinds of straps that affect the operation of the
ROMS circuitry: ROM type selection jumper straps, a ROM
wait-states cut strap, and two ROM address-decoding cut straps.
The ROMS circuitry is designed to accept a variety of different
ROM integrated circuit packages. A chart specifying these
different ROM types is found on the schematic itself (Schematic
A2-3). The chart also specifies the strap positions required
for each type of ROM.
12-38
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Cut-strap W475 selects the number of ROM wait states that the MPU
inserts between state T3 and T4. If the strap is not altered, the
MPU inserts one wait-state.' This allows the use. of ROMs wi th chip
select access time of a maximum 580ns. However, if all the ROMs
on the Processor board have an access time of 380ns or less,
strap W475 may be altered so that the MPU inserts no wait-states
between T3 and T4. This latter position increases the speed of
the MPU when executing on-board ROM firmware.
The straps at W126 allow some or all of the ROM memory address
space to be diverted from being used locally on the Processor
board to being used by the system. There are three positions for
the straps. See the appendix on straps to determine the settings
for each of the three positions. If the straps are not altered,
all 32K bytes of the Processor board ROMs are addressed in the
range F8000 to FFFFF. However, the straps may be altered to two
positions. In one position, only Processor board ROMs addressed
in the range FCOOO to FFFFF output data to the MPU or FPU. In the
other position, there is no Processor board ROM space -- all
memory space is accessed on the System bus.
The ROM circuitry receives an address from the MPU or FPU and
puts the data for that address on the Processor bus. The sequence
of events when the MPU or FPU reads from a ROM bank is the
following.
1. An address from the MPU or FPU is latched by the Address
Driver circuitry.
2. The Address Decoding circuitry determines whether it is a
Processor board ROM address, which is normally any address
in the range F8000 to FFFFF. If the address is in this
range, Address Decoding drives OEROM-O true.
3. The bank decoder selects one ROM bank in response to A13-1
and A112-1 in addition to A1E-1, 1S1-0, 1S2-0, and A15-1
through A19-1. See Figure 12-12, ROM Bank Decoder 10gic, and
Table 12-4, Selection Bits for ROM Banks for an exact
description of how the bank decoder works.
4. The two Ror~s in the selected ROM bank place their data on
the Processor data bus lines, DO-1 through D1-15.
5. The Data Drivers/Receivers pass this data on to the MPU or
FPU.
4170 INSTRUCTION
12-39
SECTION 12
THEORY OF OPERATION
Table 12-4
SELECTION BITS FOR ROM BANKS
-------------------------~~--------------------------- --------------------
ADDRESS BITS
EANKS
----------------------------------------~--------~-------------: A19-1 : A18-1 : A17-1 : A16-1 : A15-1 : A112-1 : A13-1 : A12-1 :
: F8000 : 1
: 1
: 1
: 1
: 0
: 0
: X (a)
---------------------~------~------------------------- --------------------
: FAOOO : 1
: 1
: 1
: 1
: 1
: 0
: 1
: X(a)
---------~~~-~------~-~--~-~-----------~-------------- --------------------
: FCOOO : 1
: X (a)
: 0
--------~------------~---------------------------------------------~~----: X( a)
: FEOOO .: 1
: 1
: 1
: 1
: 1
: 1
: 1
: 1
: 1
: 1
: 1
: 1
--------------~--------------------------------------- --------------------
(a) "x" is a "don't care" condition.
12-40
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
LS2-1/J
A19
---+---.
AlB
A17
A16
A15
ADDRESS DECODING
ROMS
+5 V
ALE-l
--------{J
--------Cr------/
P
LS1-1/J
~+-4--~-B
b
A14
~---~_+--4-A
A13
~_ _ _ _ _ _ _~___
3
I
I
I
BANK 3
~---~ FC000
2
BANK 2
~----4 FA000
1
P.
~----4
o
BANK 1
F8000
(3820)4517-5
Figure 12-12. ROM Bank Decoder Logic.
4170 INSTRUCTION
12-41
SECTION 12
THEORY OF OPERATION
NON-VOLATILE RAM (SCHEMATIC A2-4)
The Non-Volatile RAM stores various initialization and system
parameters in 512 bytes of CfvlOS RAM.
The input signals are:
~o
o
RD-O (Read). Allows the MPU
read from the CMOS RAM.
o
AO-1 through A8-1 (Processor Address Bi ts 0 through 8).
o
LBHE-O (Latched Byte High Enable). Allows the MPU to access
data bits DS-1 through D15-1.
o
AWT-O (Advanced Write). Allows the MPU or FPU to write to
the C~lOS RAf'1.
o
DT/R-O (Data Transmit or Receive) Causes the CMOS RAM to
accept data when false, and to output data when true.
o
OBRAM-O (On-Board RArJ]). When RAM on the Processor board is
addressed, OBRAM-O goes true.
The output signals are:
o
DO-1 through D15-1 (Processor Data Bus Bits 0 through 15).
o
CMD-1 (Command). Created in the Non-Volatile RArll circuit
block by the logical OR of AWT-O and RD-O.
Pour 10212-bit by 12-bit CNOS RA1VIs (of which only a 256-bit by
12-bit portion is used) combine to give a total memory capacity
of 512 bytes. Also included in this circuitry are six logic gates
that decode various input signals that control reading and
writing access.
When power to the 4170 is removed, the CMOS RAM retains its
contents. A 2.4 V rechargeable NiCad battery provides the voltage
to make this possible. A trickle charge circuit assures that the
battery remains fully charged.
12-42
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Read Access
This RAM occupies FEOO to FFFF in I/O address space. (See the
Address Decoding description to see how CMOS can be placed in
memory address space.) When the MPU or FPU presents an address in
this range to the Address Decoding circuitry, OBRAM-O goes true.
The IVIPU also causes RD-O to go true. At this point, AO-1 goes
false, if only the low order byte, DO-1 through D7-1, of the
Processor data bus is needed. These conditions on OBRAM-O, RD-O,
and AO-1 enable the two RAMs that output DO-1 through D7-1. Now
DT/R-O goes true, and the RAMs output DO-1 through D7-1 onto the
Processor data bus.
A read access of the high order byte, DS-1 through D15-1, is
accomplished in the same manner as the low order byte, except
that LBHE-O goes true.
Write Aooess
During a write access, AWT-O goes true instead of RD-O, and
DT/R-O goes false. OBRAM-O, LBHE-O, and AO-1 operate as they do
in a read access.
Note that INIT-O disables all RAMs if it goes true.
MICROPROCESSOR CONTROL (SCHEMATIC A2-1)
The Microprocessor Control generates the 4.9152 MHz clock signal
for the MPU an~ FPU. Also, it synchronizes the reset and ready
lines.
4170 INSTRUCTION
12-43
SECTION 12
THEORY OF OPERATION
The input signals are:
o
INIT-O (Initialize). Used by the Clock Generator to generate
(RST-l) for the MPU and !<'PU.
o
ACK1-0 (Acknowledge 1). When true, indicates that a device
on the System data bus is ready to receive data or has data
ready to transmi t.
o
ACK2-0 (Acknowledge 2). Has the same meaning as ACK1-0, but
allows the MPU and FPU to insert one wait-state (Tw) into
the bus cycle.
o
TIMR1-1 (Timer 1). A timer output £rom the Programmable
Timer & Baud Rate Generator circuitry.
o
TEST-O (Test). Enables the MPU to terminate an on-board or
off-board read or write operation. Also used by the MPU to
monitor the FPU BUSY-1 signal.
o
RDYAND-O (Ready AND). Disables the (RDY-1) line to the HPU
and FPU and causes MPU and FPU to enter a wait-state (Tw).
Input from Test Connector J104 and is used for testing only.
o
RDYOR-O (Ready OR). Enables the (RDY-1) line to the MPU and
FPU and causes MPU and FPU io exit a wait state (Tw). Iriptit
from Test Connector J104 and is used for testing only.
o
1STINTA-0 (First Interrupt Acknowledge). Goes true when the
MPU sends the first of its two INTA-O signals in the
interrupt sequence.
o
OBINTA-O (On-Board Interrupt Acknowledge). When true,
indicates that the PIC is placing data on the Processor data
bus.
o
OBRm~-O (On-Board ROIv'l). f.1ay cause (RDY1-1) to activate if
the cut strap W475 is altered, resulting in no ROM
w8.i t-states.
12-44
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The output signals are:
o
(OSC-1). TTL level, 14.7456 MHz square wave.
o
(CLK-1). 4.9152 MHz, 33% duty cycle clock signal which is
fed to MPU and FPU.
o
(RST-1). Resets the MPU and FPU when true and has similar
timing toINIT-O.
o
(RDY-1). When true, acknowledges that an addressed memory or
I/O device will complete its data transfer.
This circuitry consists of one D-type flip-floV, some logic
gates, and the Clock Generator and Driver (CGD). The CGD performs
three functions. It uses a frequency derived from an external
crystal to generate the (CLK-1) and (OSC-1) outputs. It
synchronizes INIT-O to produce (RST-1) and derives the
(RDY-1) output from (RDY1-1) and (AEN1-0) or from (RDY2-1) and
(AEN2-0) (Figure 12-13).
The crystal connected between (X1-1) and (X2-1) on the CGD is a
series resonant, fundamental mode type and has a frequency of
14.7456 MHz. The output of the oscillator circuitry in the CGD is
buffered and output on (OSC-1). The (F/C-O)invut is gated low to
select the crystal as the source of the (CLK-1) output frequency.
Hard wiring (CSYNC-1) to ground is necessary to use the internal
oscillator of the CGD.
The CGD reduces noise on the INIT-O signal by feeding it through
a Schmitt trigger and then synchronizes it with (CLK-1) by means
of a flip-flop.
Inside the CGD, (AEN1-0) is inverted and ANDed with (RDY1-1) as
is (AEN2-0) with (RDY2-1). The outputs of both ANDed pairs are
ORed and synchronized with (CLK-1) by a D-type flip-flop. The Q
output of the flip-flop is (RDY-1). So, if (AEN1-0) and (RDY1-1)
are true, (RDY-1) goes true. The same is true of (AEN2-0) and
(RDY2-1 ).
4170 INSTRUCTION
12-45
SECTION 12
THEORY OF OPERATION
RESET IN. ACTIVE LOW, USED TO
GENERATE RST.
RES
OSC
SQUARE WAVE OR 14.7456 MHz
WITH TTL LEVEL OUTPUT.
BUS READY. ACTIVE HIGH, MEANS
DATA IS RECEIVED OR AVAILABLE.
RDY2
CLK
1/3 DUTY CYCLE SQUARE WAVE OF
4.9152 MHz (1/3 OF 14.7456 MHz).
ADDRESS ENABLE. ACTIVE LOW,
VALIDATES RDY2.
AEN2
RST
RESET. OUTPUT FOR 8086 MPU;
ACTIVE HIGH.
SEE AEN2.
AEN1
RDY
SEE RDY2.
RDY1
READY. ACTIVE HIGH,
SYNCHRONIZED RDY1 OR RDY2
INPUT.
3820-16
Figure 12-1,. Clock Generator and Driver Pin Descriptions.
12-46
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Clock and Reset
When the 4170 is powered-up, the CGD begins operation and
generates the (OSC-1) and (CLK-1) signals until the 4170
power is removed.
INIT-O originates in the power supply and is initially true after
power-up. INIT-O goes false about 40 ms after power up. At the
next falling edge of (CLK-1), the (RST-1) output of the CGD goes
true, resetting the MPU and FPU.
Ready Signals
Essentially, (AEN1-0) and (RDY1-1) are the Processor board ready
signals and (AEN2-0) and (RDY2-1) are the off-board, or System
bus, ready signals. The (AENx-O) signals act as qualifying or
validating signals for the (RDYx-1) signals.
Processor Board Ready. The MPU and FPU receive a (RDY-1)
input if any of the following conditions occur:
o
RDYAND-O is false and OBINTA-O goes true.
o
RDYAND-O is false and 1STINTA-0 goes true.
o
RDYAND-O is false and, if cut-strap W475 is altered, OBROM-O
goes true.
o
RDYAND-O is false and OBADR-O is true while T3W12-1 goes
true.
o
RDYAND is false and TEST-O goes false while, TIMR1-1, and
T3\v 12-1 go true.
o
RDYAND is false and RDYOR-O goes true.
However, if RDYAND-O goes true all the before-mentioned
conditions are disabled and neither the MPU or FPU receive a
( RDY -1) in pu t .
4170 INSTRUCTION
12-47
SECTION 12
THEORY OF OPERATION
System Bus Ready. J<'or the MPU to receive a (RDY-1) input
from the System bus, the (AEN2-0) input must be true. This occurs
under the following conditions -- RDYAND-O is false and BUSAEN-O
is true and at least one of the following is true: INTA-O,
AIOWC-O, IORC-O, MRDC-O, or AMWC-O. Once (AEN2-0) is true, an
ACK1-0 going true triggers a (RDY-1) input to the MPU and FPU.
Or, if the device sends an ACK2-0 signal instead, the MPU and FPU
receive a (RDY-1) input on the next positive edge of the (CLK-1)
signal after ACK2-0 goes true.
BUS TRANSFER LOGIC (SCHEMATIC A2-1)
Bus Transfer Logic allows the Processor board to gain control of
the System bus to perform data transfers, and also to relinquish
control to other bus masters.
The input signals are:
o
OBADR-O (On-Board Address). When false, shows that a system
data transfer is to be done.
o
BUSY-O (System Bus Busy). When true, BUSY-O indicates that
another bus master is using the System bus for data
transfer.
o
CBRQ-O (Common Bus Request). CBRQ-O is used by a lower
priority bus master to assert that it has data to transfer
on the bus.
o
BUSGRT-O (Bus Grant). Input from Test Connector J104 used to
force Processor board control of the System bus for testing.
o
BCLK-O (Bus Clock). BCLK-O clocks all three flip-flops in
this circuitry.
o
BPRN-O (Bus Priority In). The response from bus arbitration
logic which grants bus mastership to the Processor board.
o
LOCK-O (Lock). LOCK-O is a firmware-initiated signal,
directly from the MPU, that prevents BUSY-O from going false
so that no other bus masters can gain control of the bus.
12-48
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The output signals are:
o
T4I-O (State T4 and Idle). Used here to signal when the MPU
or FPU leaves state T4 or the idle state.
o
BRQ-O (Bus Request). BRQ-O is immediately decoded according
to the priority of the Motherboard slot into which the
Processor board is inserted. BPRN-O goes true if no higher
priority BRQ-O signal is asserted at the time the Processor
board BRQ-O is asserted.
o
CBRQ-O (Common Bus Request). (See input signals.)
o
BUSGRT-1 (Bus Grant). Ind icates that the Processor board has
control of the bus when true.
o
BUSY-O. (See input signals.)
o
BUSAEN-O (Bus Address Enable). BUSAEN-O triggers the Bus
Command Driver to output read or write signals on the System
bus. It also enables the System bus address drivers.
The Bus Transfer Logic enables
the bus transfer protocol that
System bus must obey. (See the
protocol.) The Processor board
control the System bus.
the Processor board to respond to
all potential bus masters on the
description of bus transfer
is just one system device that can
There are three JK flip-flops whose Q or Q-not outputs are the
main output signals of this circuitry. (For the purpose of this
description, these flip-flops are called the BRQ-O, BUSAEN-O, and
BUSY-O flip-flops according to their Q or Q-not outputs.)
Note that three signals, CBRQ-O, BUSGRT-O, and BUSY-O, are both
inputs and outputs of this circuitry. This circumstance is made
necessary by the bus transfer protocol.
End-of-Data-Transfer Strap
Strap W455 in the Microprocessor Timing Generator selects one of
two signals that indicate the end of a current MPU data transfer.
W455 should be strapped to pins 2 and 3 only in a multi-processor
board system where the MPU is not the microprocessor supplying
the bus clock signal. (Note that strap W456 (BCLK-O) should be
open if the MPU is not supplying the bus clock signal.)
4170 INSTRUCTION
12-49
SECTION 12
THEORY OF OPERATION
When the MPU begins a memory, I/O, or interrupt cycle, the
Address Decoding circuitry drives OBADR-O true if the cycle is
transferring data on the Processor board internal bus. Since the
MPU is not accessing the System bus, BRQ-O is driven or remains
false.
However, if OBADR-O is driven high, BRQ-O goes true and the bus
transfer logic is enabled. At this point the MPU is in one of two
states; it either controls or does not control the System bus. If
it controls the bus, then, according to the protocol, the MPU has
already caused BUSY-O to go true and it proceeds with its data
transfer immediately, since it is currently bus master.
However, if the MPU does not currently control the bus, the
following sequence of events occurs:
1. The BRQ-O flip-flop toggles high and drives BRQ-O and CBRQ-O
both true onto the bus.
2. When BUSY-O goes false (bus is available) and BPRN-O goes
true (bus is granted to Processor board), the Bus Transfer
Logic makes BUSGRT-O true and BUSY-O active low (bus is busy
and unavailable).
3. At the same time, the BUSAEN-O fl ip-flop 1's preset by
BUSY-O. This enables the bus controller to begin driving
control signals onto the System bus.
4. BUSY-O remains true until the MPU is finished transferring
data. Then BUSY-O goes false if BPHN-O is false. There are
two ways to cause BPRN-O to go false:
o
A higher priority bus master requests bus control by
driving its BRQ-O signal true. If this happens, the bus
pr ior i ty logic on the Mo therboard causes the
BPRI~·-O
of
the Processor board to go false.
o
A lower priority bus master requests bus control by
making its CBRQ-O go true. This causes the BRQ-O
flip-flop to toggle, which makes BRQ-O go false. Thus,
the Processor board no longer requests the System bus.
If no other bus master requests the bus, the Processor board
maintains control. This eliminates the time delay that would be
caused by having to get control of the bus for every data
transfer.
12-50
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
ADDRESS DECODING (SCHEMATIC A2-3)
Address Decoding decodes an MPU address, consisting of A12-1
through A19-1, to determine which Processor board circuitry (or
the System bus) is currently being addressed.
The input signals are:
o
MDEN-1 (Master Data Enable). Disables all MPU data drivers
when true. MDEN-1 is used for testing.
o
T3W12-1 (State T3 Wait 4). When true, indicates that the MPU
is in state T3, T4, or Tw (WAIT). T3W12-1 enables on-board
data transceivers.
o
T4I-0 (State T4 Idle). True during the MPU T4 and TI (IDLE)
states, turning off the data transceivers during T4 in
on-board memory and 1/0 reads.
o
OBINTA-O (On-Board Interrupt Acknowledge). When true,
indicates that the Priority Interrupt Controller is
generating an interrupt vector address.
o
LSO-O, LS1-0, LS2-0 (Latched Status 0 through 2). When taken
together, these signals indicate which of eight states the
MPU is in -- interrupt acknowledge, 1/0 read, 1/0 write,
halt, instruction fetch, memory read, memory write, or no
bus cycle.
o
A12-1 through A7-1 and A9-1 through A9-1. (Processor Address
Bus Bits). These address the different areas of Processor
board circuitry.
4170 INSTRUCTION
12-51
S};CTION 12
THEORY OF OPERATION
The output signals are:
o
OBDEN-O (On-Board Data Enable). Enables the data
transceivers so that Processor board data is put on the
Processor data bus lines, DO-1 through D15-1.
o
OBADR-O (On-Board Address). When true, OBADR-O disables
the Bus Command Driver circuitry. No read, write, or
interrupt signals are output to the System Bus, allowing the
MPU to access only circuitry on the Processor board.
o
OBRAM-O (On-Board RAM). In conjunction with LBHE-O, AO-1, and
INIT-O, OBRAM-O enables the Non-volatile RAM block of the
Processor board.
o
OBROM-O (On-Board ROM). When true, OBROM-O enables the 32K
of ROM on the Processor board.
o
OBIOX&X-O. (On-Board (two byte) Input/Output Locations).
These eight signals basically act, sometimes in conjunction
with other signals, as enabling signals for two-byte I/O
space locations on the Processor board. For example, OBIOO&'2
and OBI04&6 together with CMD are chip enables for the PCI
in the RS-232 communications interface cirGuitry.
The Address Decoding circuitry consists of a number of logic
gates that decode the ranges of addresses shown in Table 12-5,
Processor Board Address Enabling Signals. A 3 to 8 line decoder
also forms part of the circuitry, and outputs the eight OBIOX&X-O
signals.
12-52
4170
INS~RUCTION
SECTION 12
THEORY OF OPERATION
Note that two sets of two multiple-input AND gates are marked off
by dashed lines on the schematic. Address Decoding is designed to
work with one or the other set installed, but not both. Both of
these sets of gates feed a three-input NAND gate which directly
produces OBRAM-O. Ordinarily, the set with the four-input AND
gates is present. This set decodes addresses in the range FEOO to
FFFF in 1,0 ADDRESS SPACE. Non-volatile RAM is located in this
range. If another MPU is added to the system, the set with
five-input AND gates would be present. This set decodes addresses
in the range 00000 to 001FF in MEMORY ADDRESS SPACE. This gives a
secondary MPU local RAM.
Table 12-5
PROCESSOR BOARD ADDRESS ENABLING SIGNALS (a)
: ADDRESSED CIRCUIT : SIGNAL
: SPACE
: 32K ROM
: OBROM-O
:
I Non-volatile RAM
: OBRAM-O
: I/O
: FEOO & FFFF :
: PCI
: OBIOO&2-0 : I/O
: OOEO & OOE2 :
: PCI
: OBI04&6-0 : I/O
: OOE4 & OOE6 :
: PIC
I OBI08&A-0 : I/O
I 00E8
&
OOEA I
: OBIOC&E-O : I/O
: OOEC
&
OOEE I
: PIT
: OBI01&3-0 : I/O
I OOE1
&
OOE3 I
: PIT
: OBI05&7-0 : I/O
I 00E5
&
OOE7 I
: RS-232 Interrupt I OBI09&B-0
: enable and Status I
I
I
A
M1~ORY
: ADDRESS
: F8000-FFFFF :
00E9 & OOEB
I/O
I
I
: Bus Timeout Reset : OBIOD&F-O : I/O
land Status B :
I
I OOED
I
I
&
OOEF :
I
I
I System Bus
I OBADR(-1) : MEMORY : OOOOO-F7FFF :
: System Bus
: OBADR-O
: I/O
: OOOO-OODF
: System Bus
: OBADR-O
: I/O
: OOFO-FDFF
: System Bus
: OBADR-O
: I/O
: 8000-FDFF'
(a) With all straps set to their normal positions.
4170 INSTRUCTION
12-53
SECTION 12
THEORY OF OPERATION
The MPU enters bus cycle T1 during which it outputs an address on
lines ADO-1 through AD19-1 and the MPU status signals SO-0,31-0,
and S2-02. The Address Drivers latch these signals on the
trailing edge of ALE-1. If the address falls in one of the ranges
of Processor board circuitry, the Address Decoding circuitry
generates one and only one of the output signals in ~qble 12-5
Processor Board Address Enabling Signals -- in addition to
OBADR-O true. Once OBADR-O goes true, it generates CBDEN-O in
conjunction with the timing signals T3W12-1 and T4I-0. ~3W12-1
essentially enables OBDEN-O and T4I-0 disables it. Note that a
Processor board interrupt by means of OBINTA-O can also cause
OBDEN-O to go true.
All of the OBIOX&X-O signals are generated by the 3 to 8 decoder.
Since all of the addresses for these signals fall in the range
OOEO to OOEF, the decoding gates examine bits A12-1 through A7-1
which carry the binary number 1110, which is hexadecimal E. The 3
to. 8 decoder has bits AO-1, A2-1, ann A3-1 as inputs, but NOT
bit A1-1. For example, the decoder cannot distine;uish between
OOEO and 00£2 and outputs the same OBIOX&X-O signal for either
address.
If MDEN-1 goes true, it disables both OBDEN-O a~d OBADR-D. This
implies that the MPU cannot access either Processor board or
System bus locations.
BUS TIMEOUT DETECTOR (SCHEMATIC A2-1)
The Bus Timeout Detector detects when a System bus slave device
fails to respond with an acknowledge signal (ACK1-0) to a command
from any master device. It drives ACK1-0 onto the System bus and
sets an error status bit (D8), which the ~PU can read by polling
the status. To alert the MPU that a bus timeout has occurred
without the necessity of polling, the Bus Timeout Detector also
causes an interrupt to be generated through the Interrupt
Controller on level 7.
12-54
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The input signals are:
o
OUTO-1 (Output 0). OUTO-1 is the output of a 16-bit down
counter in the Programmable Timer and Baud Rate Generator
circuitry.
o
OBIOD&F-O (On-Board I/O D and F). Along with an output from
the MPU Timing Generator, OBIOD&F-O resets the bus timeout
err 0 r fl i p- flop.
o
INTA-O (Interrupt Acknowledge). The MPU interrupt
acknowledge.
o
AIOWC-O (Advanced I/O Write Command).
o
IORC-O (I/O Read Command).
o
MRDC-O (Memory Read Command).
o
AMWC-O (Advanced Memory Write
o
BTIEN-1
the Bus
command
between
Co~mand).
(I'us Timeout Interrupt Enable). This signal enables
Timeout Interrupt circuit whenever one of the bus
lines goes true during a normal data transfer
any bus master and any slave device.
The output signals are:
o
ACK1-0 (Acknowledge 1). ACK1-0 is one of two acknowledge
signals in the System bus data transfer protocol~
o
DS-1 (Processor Data Bus Bi t 8). Used to carry error status
information.
o
BTINT-O (Bus Timeout Interrupt).
This circuitry consists of a 12-bit binary counter, aD-type
flip-flop, and some logic gates. The QD output of the binary
counter drives ACK1-0 through an open-collector driver. The Q
output of the error flip-flop drives the Bus Timeout Interrupt
signal, then becomes DS-1 after it passes through an
output-controlled line driver.
4170 INSTRUCTION
12-55
SECTION 12
THEORY OF OPERATION
During a normal data transfer between any bus master and any
slave device, one of the bus command lines goes true, enabling
the 12-bit counter to begin counting. Since the programmable clock
input signal, OUTO-1, has a period of 20ms, the bus command
would have to be held low continuously for 160ms before QD of
the counter would go true. If this bus timeout condition does
occur, QD sets the error flip-flop and drives ACK1-0 by means of
an open-collector driver. This completes the handshake sequence
for the non-responding or non-existent slave device.
If the bus commands are all less than 160ms, the counter is
always reset before it can drive QD high and no bus timeout
occurs.
Note that this circuit detects timeouts even when some other bus
master is controlling the bus. In a multiple-processor board
system, it may be desirable to disable the timeout function on
one or more of the Processor boards by cutting cut-strap W561 and
the BTINT-O strap at W470.
STATUS INPUT (SCHEMATIC A2-5)
Status Input allows the MPU to read Processor board status
signals -- BUSGRT-1, STEST-O, TIMR1-1, and bus timeout error.
The input signals are:
o
BUSGRT-1 (Bus Grant). Similar to BUSAEN-O but timed
differently.
o
STEST-O (Self Test). Goes true when the self-test switch on
the 4170 is pressed.
o
LSO-O (Latched Status 0). One of three status signals (SO-O,
S1-0, and SO-2) output by the MPU to show the current state.
o
OBIOD&F-O (On-Board I/O D&F). OBIOX&X-O signals inform the
MPU what areas of Processor board circuitry are addressed.
o
CMD-1 (Command). Shows whethe r a local read (RD-O) or wr i te
(AWT-O) operation takes place.
The output signals are:
o
12-56
STATEN-1 (Status Enable). Enables a tri-state input to a
buffer in the Bus Timeout Detector.
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The Status Input circuitry drives STATEN-1 true if CMD-1 is true,
180-0 is false, and OBIOD&F-O is true. If STATEN-1 goes true,
this enables two buffers, which output BUSGRT-1 as D11-1, STEST-O
as D10-1, Output 1 of the Programmable Interval Timer as D9-1,
and bus timeout error as D8-1 on the Processor data bus, DO-1
through D15-1.
BUS CLOCK GENERATOR (SCHEMATIC A2-1)
The Bus Clock Generator generates the 4.9152 MHz, 50% duty cycle
bus clock signal, BC1K-O, for the Processor board and System bus.
The input signals are:
o
OSC-O (Oscillator). Output of the Clock Generator in the
Microprocessor Control circuitry, which is a 14.7456 MHz
square wave.
o
C1K-1 (Clock). Output of the Clock Generator in the
Microprocessor Control circuitry, which is a 4.9152 MHz
square wave with a 33% duty cycle.
The output signals are:
o
BCLK-O (Bus Clock). A 4.9152 MHz square wave with a 50% duty
cycle. It synchronizes bus mastership transfers and provides
a stable clock for various functions on other circuit
boards.
o
UBC1K-1 (Unbuffered Bus Clock). Same as BC1K-0, but is used
only on the Processor board to drive the clock inputs of the
FPC I1PU and the PC 1.
The Bus Clock Generator consists of two JK flip-flops and two
logic gates. A four-input NAND gate which is a 50 ohm line driver
used to give extra drive to BC1K-0 for the System bus. The NOR
gate is simply an inverter for the clock input to one of the JK
flip-flops. (Cut-strap W456, if open, enables only one Processor
board to generate BC1K-O in a multiple Processor board system.)
This circuitry transforms a 50% duty cycle, 14.7456 MHz signal
(OSC-O output) and a 33% duty cycle, 4.9152 MHz signal (C1K-1 .
output) into two 50% duty cycle, 4.91 52 ~1Hz signals, UBC1K-1 and
BC1K-0. Figure 12-14, Bus Clock Generator Timing, shows the timing
relationships among the signals in the circuitry.
4170 INSTRUCTION
12-57
SECTION 12
THEORY OF OPBRATION
OSCIllATOR
OUTPUT
ClK
OUTPUT
U355A-5
UBClK
BClK
NOTES:
A,B
The trailing edge of OSC causes ClK to go high.
C,D,E
The trailing edge of OSC and a high on ClK cause Pin 5 of the U355A JK flip·flop to
go low.
C,F
The trailing edge of OSC causes ClK to go low.
G,H
A low level on U355A·5 causes UBClK to go high.
I,J,K
The trailing edge of OSC and a low level on ClK causes U355A·5 to go high.
l,M,N
The leading edge of OSC and a high level on U355A·5 causes UBClK to go low.
3820-17
Figure 12-14. Bus Clock Generator Timing.
12-58
4170 INSTRUCTION
I
SECTION 12
THEORY OF OPERATION
MPU TIMING GENERATOR (SCHEMATIC A2-1)
The MPU Timing Generator provides MPU timing information for
other circuitry on the Processor board.
The input signals are:
o
SO-0,S1-0, and S2-0 (MPU Status Bits 0 through 2). These
signals show the eight possible states of the MPU
interrupt acknowledge, I/O read, I/O write, halt,
instruction fetch, memory read, memory write, and no bus
cycle.
o
ALE-1 (Address Latch Enable). Clears Timing Generator D-type
flip-flop.
o
LS1-0 (Latched Status Bit 1). Refer to Address Driver
section for detailed information.
The output signals are:
o
T3W12-1 (State T3, TW, & T4). True when the MPU is in a T3,
TW (WAIT), or T4 state. T3W12-1 enables on-board data
transceivers.
o
T4I-O (State T4, TI (Idle)). True during MPU T4 and TI
(IDLE) states. It turns off data transceivers during T4 in
Processor board memory and I/O reads.
o
AWT-O (Advanced Write). Similar to the System Bus AIOWC-O
signal, but used for Processor board circuitry only.
The MPU performs memory and I/O transfers by going through bus
cycles. Each bus cycle consists of at least four clock states,
which are called T1, T2, T3, and T4. Sometimes, TW, or WAIT
states, are inserted between T3 and T4. Also, TI, or IDLE
states, are sometimes inserted between bus cycles. The MPU Timing
Generator makes this information available to other circuitry on
the Processor board.
The MPU Timing Generator comprises four logic gates and one
quadruple D-type flip-flop. The interconnections among the fou~
D-type flip-flops are shown in Figure 12-15.
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
o
4Q
c
(3820)4517-6
figure 12-15. MPU Timing Generator Circuitry.
12-60
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The circuit is basically a shift register. At the end of a bus
cycle, the D input of flip-flop #1 is a logical one. When the
next bus cycle begins, ALE-1 resets all four flip-flops during
T1. Next, T2 is entered and the Q output of flip-flop #1 becomes
logical one. This condition drives AWT-O true. During T3, the Q
output of flip-flop #2, which is T3W12-1, goes true, since it is
connected directly to the Q output of flip-flop #1. After T3, it
enters the TW state unless or until MPU status bits so-a, S1-0,
and S2-0 all become false. Then, in state T4, the Q-not output of
flip-flop #3, which is T4I-0, goes true. The MPU Timing Generator
stays in state TI until the MPU issues another ALE-1 during T1.
Table 12-6
MPU STATE AND MPU TIMING GENERATOR SIGNALS
SIGNAL NAME
MPU CLOCK STATE
I T1
I
I T3
I TW( a) : T4
: (T1, 2, 3, W)
: True
I True
: True
: True
I (T2, 3, W)
I
False
I
True
: True
I
True
I
False
I
: T3W 4-1
I
False
I
False
I
True
I
True
I
True
: False :
: T4I-0
: False : False I False : False I True
T2
: TI(a) :
I False : False I
False
I
: True
(a) Note that there may be multiple TW and TI states.
PROGRAMMABLE TIMER AND BAUD RATE GENERATOR (SCHEMATIC
A2-5)
The Programmable Timer and Baud Rate Generator has three
programmable counters contained in the Programmable Interval
Timer (PIT) that generate timing signals to produce:
o
Transmit baud rate in the RS-232 Communications Interface
logic.
o
TIMR1-1 that can generate an interrupt signal to the MPU.
o
OUTO~1 -- the primary firmware interrupting timer and timing
source for the bus timeout detector.
4170 INSTRUCTION
12-61
SECTION 12
THEORY OF OPERATION
The input signals are:
o
A1-1 and A2-1 (Processor Address Bi ts 1, 2). They address
tho three 16-bit down counters in the PIT and an internal
~ddress control word register.
o
AWT-O (Advanced Write). If true, enables the PIT to output
counter data.
o
EBCLK-1 (Buffered Bus Clock). A 4.9152 f"1Hz clock signal that
clocks a 12-bit counter.
o
OBI01&3-0 and OBI05&7-0 (On-Board I/O). Either signal, when
true, enables the PIT for read or write operation.
o
RD-O (Read). Processor bus read signal. The PIT inputs data
from DO-1 through D7-1 when RD-O is true.
o
RST-1 (Reset). Local reset signal derived from System bus
INIT-O. When true, clears the 12-bit counter.
The output signals for this block are:
o
DO-1 through D7-1 (Processor Data Bus Bits 0 through 7).
Carry three kinds of information:
o
Values to load into the PIT counters.
o
Values read from the PIT counters.
o
Data that programs the various modes of the PIT.
o
OUTO-1
(Output 0). Output of counter 0 in the PIT.
o
TH1R1-1
o
TXC-O (Output 2). Output of counter 2 in the PIT, inverted.
(Timer 1). Output of counter
in the PIT.
This circuitry consists primarily of the Programmable Interval
Timer (PIT). The PIT includes three internal 16-bit counters
(numbered 0, 1, and 2), a data buffer, and read/write circuitry
(Figure 12-16).
This circuitry also has one AND gate and one 12-bit binary
counter. The AND gate functions as an OR gate using OBI05&7-0 and
OBI01&3-0 to operate the chip select input of the PIT. The
counter produces two Signals by dividing the buffered bus clock
signal (BBCLK-1) by two and eight. BBCLK-1 divided by two is
input to the number 2 counter of the PIT and BBCLK-1 divided by
eight is input to the number 0 and 1 counters of the PIT.
12-62
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
ADDRESSES. SELECT ONE OF
THREE COUNTERS AND ADDRESS
CONTROL WORD REGISTER.
AO,A1
READ. IF LOW, 8086 INPUTS DATA
TO 8253 COUNTERS.
RD
WRITE. IF LOW, 8253 OUTPUTS
COUNTER OR MODE INFORMATION
DATA.
WR
CHIP SELECT. IF LOW, ENABLES
THE 8253.
CS
GATES 0,1,2. TIED HIGH TO
PERMANENTLY ENABLE THE
THREE COUNTER OUTPUTS
00,01,02.
GO,G1,G2
°
CLOCKS 0,1,2. CLOCKS COUNTER
0,1 CLOCKS COUNTER 1, AND 2
CLOCKS COUNTER 2.
00--07
PROCESSOR BOARD 00-07 BUS.
USED TO LOAD COUNTERS, READ
COUNT VALUES, AND PROGRAM
THE 8253 MODES.
00--02
COUNTER OUTPUTS 0,1,2. HIGH
WHEN COUNTER VALUE EQUALS
ZERO.
0,1,2
3820-19
Figure 12-16. Programmable Interval Timer Pin Descriptions.
4170 INSTRUCTION
12-63
SECTION 12
THEORY OF OPERATION
Programmable Interval Timer
There are three main blocks of circuitry in the PIT:
o
Three 16-bit down counters
o
An ,. S-:bit
buffer
' .data. .bus
, 'r
oRea~/wri telogic
The three counters operate independently and each has i ts'own
outP.'lt,,(OP,,'01, OZ) . ,...H.,.OW the counters o:perate is controlled
completely 'by comm'and,s from the system \ or possibly other)
firmware. Each counter is loaded with an initial value suppli~d
by firmware. Firmware commands can also read the counter value of
a counter at any time during its down count.
The data bus buffer is connected to DS-1 through D15-1, part of
the Processor data bus. Firmware commands, initial counter
values, and read-out counter values pass through this buffer.
The read/write logic is enabled by the chip select input to the
PIT. The local Processor signals, RD-O and AWT-O, control the
direction of data flow in the data bus buffer. Part of the
Processor address bus, A1-1 and A2-1, select which of the three
counters that commands and counter values are directed to .
. The PIT has two phases Qf operation: initialization and normal
operation. Initialization occurs shortly after power-up, though
initialization commands may be given after this time.
After power-up, the MPUinitializes the PIT as follows: either
OBI01&3-0 or OBI05&7-0 goes true and enables the PIT, and A1-1
and A2-1 select counter 0, 1, or 2. AWT-O goes true, enabling
firmware commands and counter values to program the selected
counter via D8-1 through D15-1. After all three counters are
programmed, initialization is done.
Note that there is no reset pin on the PIT, and that after the
System bus INIT-O signal goes false and before the MPU
initializes the PlT, outputs 01, 02, and 03 are undefined and may
be stable high, .sta.ble,low, or pulsing.
In normal operation, a count value may be read from one of the
counters. In this case RD-O goes true after the PIT and the
appropriate counter are selected. The counter value then appears
on DS-1 through D15-1.
12-64
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Also in normal operation, output 2 (02) produces the TXC-O baud
rate signal for the RS-232 Communications Interface, output 1
(01) produces TIMR1 that is used by the MPU Control circuitry in
combination with a number of other interrupt-type signals, and
output 0 (00) produces aUTO that serves as both the primary
interrupting firmware timer and as the clock source for the bus
timeout detector.
18-2'2 STATE CHANGE DETECTOR (SCHEMATIC A2-5)
The RS-232 State Change Detector detects state changes on the
incoming RS-232 status lines (DSR-1, DCD-1, SDCD-1, CTS-1, and
RING-1) and generates an interrupt (TIMERINT-O) when any of these
signals change state.
The input signals are:
o
DSR-1 (Data Set Ready). Informs the RS-232 Co~munications
Interface that the local modem is ready to operate.
o
DCD-1 (Data Carrier Detector). Informs the HS-232
Communications Interface that the carrier wave is being
received by the modem.
o
SDCD-1 (Secondary Data Carrier Detector). Informs the RS-232
Communications Interface that the secondary carrier wave
is being received by the modem.
o
CTS-1 (Clear To Send). Informs the RS-232 Commun icat ions
Interface that the modem is ready to transmit. This is a
response to RTS (Request To Send) from the RS-232
Communications Interface circuitry.
o
RING-1 (Ri ng Ind icator). Info rms the RS-232 Commun ic at ions
Interface that the local modem is receiving a ringing signal
from a remote modem.
o
RST-O (Reset). Clears the last state latch.
The output signals are:
o
4170
(Y-O) (State Change Detected Signal). Produces TIMERINT-O in
conjunction with other signals in the RS-232 Communications
Interface.
INS~RUCTION
12-65
DECTION 12
THEORY OF OPERATION
The circuitry consists of a 12-input line receiver, a 6-input
D-type flip-flop, a bus driver, a 6-bit comparator, and part of
another 12-input line receiver. (The five capacitors connected to
the line receivers prevent voltage spikes (glitches) on the
RS-232 status lines from being transmitted to the RS-232 State
Change Detector circuitry.)
The MPU interacts with the RS-232 State Change Detector in two
ways. It first receives an interrupt and then determines what
caused the interrupt.
The RS-232 status sienals (DSR-1, DCD-1, SDCD-1, CTS-1, and
RING-1) are input to the last state latch and to the comparator.
(Note also that the 00 output of the Programmable Interval Timer
in the Programmable Timer and Baud Rate Generator block makes up
a sixth input to the comparator and latch.) The six outputs of
the latch are routed to the bus driver and to the other half of
the magnitude comparator. The comparator compares the inputs and
outputs of the latch, and if any of the RS-232 status lines (or
the 00 output of the PIT) changes state, the comparator then
drives Y-O true which activates a NAND gate in the RS-232
Communications Interface. This causes TIMERINT-O to go true.
After TIMERINT-O is processed by the Interrupt Controller, the
MPU receives an interrupt.
At this point the MPU needs to determine which RS-232 status line
(or 00 from the FIT) caused the interrupt. To accomplish this the
MPU read~ either the current status or the new status. To read
the current status which exists at the outputs of the latch, the
r·1PU add resses the RS-232 St ate Change Detector, wh ic h cause s
OBI09&B-0 to go true. Also, A1-1 must be true. RD-O now strobes,
causing the bus driver to drive the status line data onto the
Processor bus. To read the new status, OBI09&B-0 goes true again,
but this time A1-1 goes false. Now, the latch is clocked, and the
bus driver drives the inputs (new status data) of the latch onto
the Processor data bus. At this point, firmware determines which
status line caused the TIIY1ERINT-0 interrupt.
RS-232 COMMUNICATIONS INTERFACE (SCHEMATIC A2-5)
The RS-232 Communications Interface transmits and receives RS-232
characters and control (handshake) signals. It contains the
receive Baud Rate Generator.
12-66
4170
INS~RUCTION
SECTION 12
THEORY OF OPERATION
The input signals are:
o
RDATA-O (Receive Data). Serial data from the host computer.
o
RCLK-1 (Receive Clock). External clock signal generated by
the local modem or other source. Can be used to clock data
into the Programmable Communications Interface (PCI).
o
TCLK-1 (Transmit Clock). External clock signal generated by
the local modem or other source. Can be used to clock data
out of the PC I.
o
DO-1 through D15-1 (Processor Data Bus Bi ts 0 through 15).
o
A1-1 and A2-1 (Processor Address Bus Bi ts 1 and 2). Carry
addresses that select internal registers in the PCl.
o
OBI09&B-0 (On-Board I/O 9 and B). True when data appears on
the Processor bus for the interrupt enable latch (with
inputs D8-1 through D15-1 ).
o
UBCLK-1 (Unbuffered Bus Clock). Clocks the Internal Baud
Rate Generator in the PCI.
o
LS1-0 (Latched Status Bit 1). When LS1-0 is true, the MPU is
in an interrupt acknowledge, I/O read, memory read, or
instruction fetch bus transaction.
o
OBIOO&2-0 and OBI04&6-0 (On-Board I/O Locations 0 & 2, and 4
6). Either signal going true enables the PCI if CMD-1 is
true.
&
o
Cf1D-1 (Command). \>lhen true, it indicates that the l\1PU is
doing a Processor board read or write.
4170 INSTRUCTION
12-67
SECTION 12
THEORY OF OPERATION
The output signals are:
o
SRTSA-t or SR~SC-1 (Secondary Request To Send A or· C) .
Half-duplex RS-232 handshaking signal. Can be strapped to A
or C depending on the type of modem used.
o
DTR-1 (Data Terminal Ready). Informs the modem that the
4170 is operational.
o
RTS-1 (Request To Sertd). Informs the modem that the 4170
is ready to transmit data.
o
~DATA-O (Transmit Data). Data is transmitted serially on
this line to the modem or directly to the host computer.
o
COMINT-O (Communications Intetrupt). CCMINT-O goes true when
a character is received by the PCI from the host computer.
o
TII'I'lER INT-O (Timer Interrupt). When TH'IERINT-O goes true, any
one of the following interrupts has occurred: PIT timer #1
(output 01), PCI TXEMT-O, PCI TXRDY-O, RS-232 status change,
or a PIT OUTO-1 (via RS-232 State Change Detector
circuitry) .
This circuitry consists pf a line driver, a line receiver, a '
number of logic gates, and the Programmable Communications
Interface (pcr). The PCI is the heart of this circuitry (Figure
12-17).
PrOlrammable Oommunications Interface
This integrated circuit performs the parallel-to-serial data
conversion for data sent to the host computer and also the'
serial-to-parallel conversion for data sent to the 4170. The
PCI internal Baud Rate Generator can also be programmed. In order
to perform these functions, the PCI has the circuitry shown in
Figure 12-18.
12"':'68
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Data Bus Buffer. DO-1 through D7-1 are input and output
via this 8-bit buffer. Firmware commands, status information,
and data are transferred through the buffer.
Modem Control. Two handshaking signals, DTR-1 and RTS-1,
are sent directly to the host computer or modem from this block.
(TXEMT-O/DSCHG-O) also originates here, and when true, indicates
that the transmitter has completed the parallel-to-serial
conversion of the last character loaded by the MPU. Note that
DSR-O, CTS-O, and DCD-O, which are generated in this circuitry,
are permanently tied low.
Control Functions. By responding to A1-1, A2-1, LS1-0,
OBIOO&2-0, OBI04&6-0, and CMD-1, this circuitry controls when the
PCI is written to or read from, and controls the overall PCI
internal operation. In addition, there are internal registers
whose contents can be manipulated by firmware commands.
4170 INSTRUCTION
12-69
SECTION 12
THEORY OF OPERATION
DTR
DATA TERMINAL READY. TO
MODEM.
RTS
REQUEST TO SEND. TO MODEM.
TXD
DATA TRANSMIT. SERIAL DATA
FROM THE TRANSMITTER,
NORMALLY A HIGH "MARK,"
"SPACE" IS A LOW.
DATA SET READY, CLEAR TO
SEND, DATA CARRIER DETECT.
TIED LOW, ALWAYS "ENABLED."
DSR,CTS,DCD
PROCESSOR BOARD DATA BUS.
DO--07
DATA RECEIVE. SERIAL DATA
INPUT TO RECEIVER.
RXD
RECEIVER CLOCK. EXTERNAL
CLOCK, MAY BE 1,16, OR 64
TIMES BAUD RATE.
RXC/BKDET
TXEMTIDSCHG
TRANSMITTER EMPTY/DSCHG.IF
LOW, TRANSMITTER HAS
SERIALIZED LAST CHARACTER
LOADED.
TRANSMITTER CLOCK.
CONTROLS TRANSMIT RATE (1,
16, OR 64 TIMES BAUD RATE).
TXC/XSYNC
TXRDY
TRANSMITTER READY. IF LOW, A
CHARACTER CAN BE LOADED BY
THE MPU. GOES HIGH AFTER THE
CHARACTER IS LOADED.
ADDRESS LINES. SELECT
INTERNAL PCI REGISTERS
A1,AO
RXRDY
READ/WRITE COMMAND.
RIW
RECEIVER READY. IF LOW A
CHARACTER CAN BE READ BY
THE MPU; GOES HIGH AFTER THE
CHARACTER IS READ.
CHIP ENABLE COMMAND.
CE
RESET. DOES A MASTER RESET,
CLEARS ALL REGISTERS, ENTERS
IDLE STATE UNTIL REINITIALIZED.
RESET
3820-20A
Figure 12-17. Programmable Communications Interface Pin Descriptions.
12-70
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
DTR
RTS
D0-7
A2
~
---------I~~
~
RST
~
A1
LS1
01l10fll&2
01110.01&11
:p--
CMD
UIICLK _ _ _ _ _----I~~
RCLK
~
CONTROL
FUNCT IONS
AND
PCI
NSTRUCTION
SET
REGISTERS
(illl5Y1
' - - - - -........
SHIFT
REGISTER
BAUD RATE
GENERA TOR
AND
CLOCK
CONTROL
RDATA ----.,...--------+-~I
TDATA
TRANSMITTER
HOLDING
REGISTER
SHIFT
REGISTER
(RXRDYI
RECEIVER
(3820)4517-7
Figure 12-18. Programmable Communications Interface Block Diagram.
4170 INSTRUCTION
12-71
SECTION 12
THEORY OF OPERATION
Baud Rate Generator and Clock Control. UBCLK provides
the source frequency for the internal baud rate generator.
Usually, the transmit baud rate is generated by output 02 from
the PIT and the receive baud rate is generated from the internal
Baud Rate Benerator and ~ software-sele~table register value.
However, 1X baud rate clocks from the modern may be selected for
either the receive rate, transmit rate, 6r both. For external
transmit clocks, TCLK-1 is converted to TTL levels, multiplexed
with the PIT 02, and input to (TXC-O). For external receive
clocks, RCLK-1 is converted to TTL levels, and input directly to
(RXC-O), where the signal is multiplexed with the Internal Baud
Rate Generator.
Transmitter. ~he holding register ~eceives data from the
MPU and passes it to the shift register. Start, stop, and parity
bits are added to the data according to the current communication
parameters. The data is then output serially and becomes TDATA-O.
Receiver. The shift register receives serial data on
RDATA. This passes to the holding register and bits or characters
are checked according to the current communication parameters.
The data is then output to the MPU during a read of the data
register.
Before the RS-232 Communications Interface can send and receive
data, its operating parameters must be- set by a combination of
firmware and software commands and values. Communications
parameters like synchronous or asynchronous mode, receive baud
rate, parity, and number of bits per character, are sent to the
PCI shortly after the 4170 is powered up. Once this programming of
values is completed, normal data communication begins.
3
~:
MPU Control
The MPU controls the PCI by activating A1-1, A2-1, LS1-0,
OBIOO&2-0, OBI04&6-0, and CMD-1. The states of A1 and A2
determine which of four registers in the control function
circuitry will be selected to be read from or written to. The
MPU first selects the PCI by causing OBIOO&2-0 or OBI04& 6-0 to
go true, and CMD-1 to go true. LS1-0 is true for a read operation
and false for a write operation.
12-72
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Data Communication
Serial data on RDATA-O is input on the RS-232 cable (via P102).
The data is then converted to TTL levels by the line receiver and
fed to the (RXD-1) input of the PIC. Serial data is output to the
line driver and becomes TDATA-O on the RS-232 cable (via P102).
The PIC determines when to output DTR-1 and RTS-1 for modem
control. These signals are also output on P102. SRTS-1 is
controlled by the MPU directly and is latched, inverted, and
level-converted before it reaches P102. (SRTSC-1 is the usual
strap setting.lt may be strapped to produce SRTSA-1 if the modem
requires it.)
Interrupts
The signals (TXEMT-O), (TXRDY-O), and (RXRDY-O) are status
signals from the PCI that can generate interrupts to the MPU. All
three signals are inverted and ANDed with interrupt enable-type
signals from the latch. This allows the MPU to disable the PCI
interrupts.
FRONT PANEL CONTROLLER (SCHEMATIC A2-4)
The Front Panel Controller scans the front panel port for key
change data and informs the FPC MPU if there is any activity. The
Front Panel Controller also handles the LED and bell signals.
4170 INSTRUCTION
12-73
SECTION 12
THEORY OF OPERATION
The input signals are:
o
A1-1 (Processor Address Line 1). Tells the FPC HPU whether
data on DO-1 through D7-1 is data or a comcand.
o
AWT-O (Advanced
FPC r'l PU.
o
RD-O (Read). Allows the MPU to read data from the Peripheral
Interface MPU.
o
OBIOC&E-O (On-Board I/O C and E). Enables the Peripheral
Interface IY1PU.
o
RST-O (Reset). Resets the FPC MPU.
o
UBCLK-1 (Unbuffered Bus Clock). 4.9152 I"lHz square wave input
to the FPC MPU.
o
KBT1-1 (Keyboard Test 1). Test input to the Peripheral
In t e r f ac e f'1 PU .
o
KDO-1 through KD7-1 (Keyboard Data 0 to 7). Key change
information appears on these lines from the front panel.
Write)~
Allows the MPU to write to the
The output signals are:
o
K'I'lR-O (Keyboard Write). Strobes KAO-1 through KA3-1 into the
LED and Bell Logic circuitry.
o
KSTRB-O (Keyboard Strobe). Latches KAO-1 through KA3-1 into
the LED and Bell Logic and Character Decoder circuits.
o
KBDINT-O (Keyboard Interrupt). Interrupt to FPC IVlPU v ia the
Programmable Interrup~ Controller.
o
KAO-1 through KA3-1 (Keyboard Address 0 to 3). Carry key
matrix column addresses for the Character Decoder
and LED on-off data for the LED and Bell logic.
The main component in this circuitry is an 8-bit Front Panel
Controller Microcomputer (FPC MPU). Firmware written in the
instruction set of the FPC MPU enables it to transmit key change
data to the Processor data bus. Also, front panel LED and bell
signals are transmitted from the Processor data bus to the front
panel.
12-74
4170
INSTRUC~ION
SECTION 12
THEORY OF OPERATION
Other components are: an 8-bit buffer, three inverters, and seven
open-collector buffer gates. The 8-bit buffer is always enabled
and buffers KDO-1 through KD7-1 for the FPC MPU.
Two of the Inverters are placed between UBCLK-1 and the clock
inputs, X1-1 and X2-1, to provide extra drive for the inputs. The
seven buffer gates drive KWR-O, KSTRB-O, KBDINT-O, and KAO-1
through KA3-1.
Front Panel Controller Microcomputer
This microcomputer consists of the following blocks of circuitry:
control logic, timing, test logic, I/O Ports 1 and 2, status
register, data-out buffer, data-in buffer, and one large block
that consists of all block that do not have direct inputs from or
outputs to the Front Panel Controller (Figure 12-19 and Figure
12-20) .
Control L08ic. This logic produces internal instructions
which accomplish a variety of internal control functions. The
signals that determine these internal control functions are A1-1,
AWT-O, RD-O, OBIOC&E-O, and RST-O. A1-1 enables the MPU to
indicate to the FPC MPU that information on DO-1 through D7-1 is
data or a command. When AWT-O is true, the MPU is enabled to
write data to the data in buffer. When D-O is true, the MPU is
enabled to read data from the status buffer or data-out buffer.
OBIOC&E-O enables the FPC MPU. RST-O resets various internal
counters and status flip-flops. (Note that the (SS-O) and (EA-1)
inputs: though they are inputs to the control logic, they are
disabled since they are tied high and grounded, respectively.)
4170 INSTRUCTION
12-75
SECTION 12
THEORY OF OPERATION
Al
AWT
RO
OBIOC&E
RST
ROL
LOGIC
01Zl-7
UBCLK
KBTl
KOIZl-7
TIMING
TEST
LOGIC
lK ROM,
ALU,
INSTRUCTION
DECODER,
TIMER,
64 BYTES
RAM, ETC.
I/O
PORT
I/O
PORT
~1
~2
KIIR
KSTRB
KBINT
KAIZl-3
(3820)4517-8
Figure 12-19. FPC MPU Block Diagram.
12-76
4170 INSTHUCTION
SECTION 12
THEORY OF OPERATION
[)o"D7
ADDRESS INPUT. USED BY MPU
TO SHOW FPC MPU WHETHER
00-07 IS DATA OR COMMANDS.
AO
1/0 WRITE.WHEN LOW, MPU
WR
P27
PART OF 1/0 PORT USED BY
FIRMWARE TO CARRY FRONT PANEL
WRITE INFORMATION (KWR).
RD
P26
PART OF I/O PORT USED BY
FIRMWARE TO CARRY FRONT PANEL
STROBE INFORMATION (KSTRB).
CHIP SELECT.WHEN LOW,
ENABLES THIS CHIP FOR MPU
READ OR WRITE.
CS
P24
PART OF I/O PORT USED BY
FIRMWARE TO CARRY FRONT PANEL
INTERRUPT (KBINT) TO MPU.
RESET.WHEN LOW, RESETS
INTERNAL STATUS REGISTER
AND ZEROS PROGRAM COUNTER.
i!iS'i'
CLOCK INPUTS.4.9152 MHz.
X1,X2
8-BIT KDO-KD7 PORT .INPUT
FROM FRONT PANEL, CARRIES
KEY PRESSED OR RELEASED
DATA.
P1O-P17
WRITES DATA AND COMMANDS
TO FPC MPU.
1/0 READ. WHEN LOW, MPU
READS DATA AND COMMANDS
FROM FPC MPU.
P20-P23
BIDIRECTIONAL OAT A BUS
CONNECTED TO PROCESSOR
BOARD 00-07 DATA BUS.
PART OF 1/0 PORT USED BY
FIRMWARE TO OUTPUT MATRIX
ADDRESS AND LED INFORMATION
TO FRONT PANEL.
(3820)4685·44
Figure 12-20. FPC MPU Pin Descriptions.
4170 INSTRUCTION
12-77
SECTION 12
THEORY OF OPERATION
Timing. UBCLK-1 provides the 4.9152 MHz clock for an
internal oscillator.
Test Logio. (Test 0) has been disabled by tying it high,
but (Test 1) is controlled by KBT1-1. If KBT-1 is true, firmymre
can read this condition in the FPC MPUduring testing.
I/O Ports 1 and 2. Although these ports can function as
input and output ports, I/O Port 1 functions, only as the input
port for KDO;"1 through KD7-1, and I/O Port 2 functions only as
the output port for KWR-O, KSTRB-O, KBDINT~O, and KAO-1 through
KA3~1 .
'
Status Register. This register, which is accessed by the
MPU through DO-1 thtoughD7-1, carries status information
informing th~ MPV what kind of data is in the data buffers and
whether it should read from or write to the FPC MPU. The MPU reads
the status register at I/O address OOEE.
Data-Out Buffer.'lhe MPU reads all data (key' codes and
thumbwheel position data) from the FPC lI1PU from this buffer. The
data-out buffer I/O address is OOEC.
Data-In Buffer.· The NPU wri tes data and commands to the
FPC MPU through this buffer. The data-in buffer'r/O address is
OOEC.
The FPC MPU has firmware routines masked into its 1K of ROM. These
routines cause the FPC MPU to operate independently of the MPU. In
addition to carrying out these routines, the FPC MPU responds to a
set of com~ands that the MPU issues to it. These commands cause
operations such as ringing the terminal bell, turning LEDs on and
off, enabling front panel interrupts, enabling and disabling the
timer interrupt, and resetting the FPC MPU.
The FPC MPU passes three kinds of data to the MPU: keycodes,
thumbwheel count values, and keyboard identification data. The
interactions between the MPU and FPC MPU are somewhat different for
each kind of data.
12-78
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Keycode Data
The FPC MPU has internal firmware that causes KAO-1 through KA3-1
to scan the character decoder. If the MPU has enabled the FPC MPU
interrupt and if a key is pressed or released, the Front Panel
Controller MPU reads a keycode from KDO-1 through KD7-1. The
keycode is placed in the data-out buffer and the FPC MPU issues
an interrupt on KBINT-O. The MPU then reads the status register
to determine which of the three kinds of data the FPC MPU has for
it. At this point, the MPU initiates a routine which reads the
8-bit keycode from the data-out buffer.
If a key is held down, The MPU recognizes whether this is a valid
repeating key and the HPU sends the command to enable the timer
if a repeat is sensed. The FPC MPU then starts a 500 ms delay. If
the MPU, within this delay, has not sent the command to disable
the timer, the FPC MPU interrupts the MPU every 100 ms until the
MPU sends the disable command (after the key has been released).
LED and Bell
The LED on-off state and bell-sounding are controlled by sending
commands to the FPC MPU. In order to turn an LED on or off, the MPU
sends to the FPC MPU the address of the LED and the on command or
the off command. The FPC MPU controls the timing once it gets the
address and on or off command. The bell sounds when its address
and the bell command is sent. The bell sounds once for every bell
command that is sent to the FPC MPU.
ECC RAM MEMORY
The term ECC RAM Memory describes an ECC RAM Controller with one
or two ECC RAM Array boards installed.
4170 INSTRUCTION
12-79
SECTION 12
THEORY OF OPERATION
The ECC RAM Memory board has the following features:
o
Error checking and correction (ECC). The ECC RAM Memory
board checks the accuracy of the data stored in memory and
corrects any single-bit errors that occur. Double and
multiple-bit errors are detected and can be logged by
firmware routines.
o
Dual port access. The ECC RAI~l l'1emory
4170 Processor bus access port (Port
additional synchronous port (Port A)
directly to R Processor board having
capability.
o
Memory density. The ECC RAM Memory board uses either 64K or
256K byte RAMs.
board has the standard
B), and also includes an
which can interface
additional port
For further information, refer to the ECC RM1 Service Manual.
THREE PORT PERIPHERAL INTERFACE (AND OPTION 10 3PPI)
The Three Port Peripheral Interface (3PPI) provides three
RS-232-C ports for attaching peripheral devices' to the 4170.
One 3PPI is standard in the 4170 and one optional 3PPI (Option
10) can be added for a total of six peripheral ports.
The 3PPI consists of:
o
A 3PPI circuit board
o
Three standard RS-232-C connectors (mounted on the rear
panel)
o
Cables from the 3PPI board to the RS-232-C connectors
For further information, refer to the Three Port Peripheral
Interface Service Manual.
12-80
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
OPTION 44 DISK CONTROLLER BOARD
The first part of this discussion shows how the disk drive units
work as a part of the 4170 Local Graphics Processing Unit for
storing and retrieving data on a flexible disk. The next part of
the discussion explains the disk formatting and disk data
organization scheme. An overview of the hardware used for typical
read and write operations follows. The section concludes with a
description of the major logic functions of the Disk Controller
board.
Signal names used in this theory section are identical to those
used on the scheml'ltics. These names are abbreviations of the
signal function.
SYSTEM CONFIGURATION
The Disk Subsystem consists of the disk drive units and the Disk
Controller board (installed in the 4170 card-cage). The major
logic functions contained on the Disk Controller board are the
following:
0
Disk Controller (FDC)
0
Clock Generation
0
Write Control
0
Read Recovery
0
Disk Drive Control
0
r:Lerminal Interface
0
ROf.1s
Figure 12-21 shows how the Disk Subsystem and the 4170 interact.
The diagram shows the general data flow from the RAM through the
Disk Controller board to the disk drive unit. A DMA control block
is shown, which allows the Disk Controller board to act as a
Processor bus master, accessing system RAMs directly. The heart
of the Disk Controller board is a Flexible Disk Controller IC
(FDC) .
4170 INSTRUCTION
12-81
SECTION 12
THEORY OF OPERATION
RS-232
COLOR
COPIER
HOST
COMPUTER
PROCESSOR
RAM
EXTRA
RAM
(Optional)
COPIER I/F
(Optional)
RS232
PORT
DISK
DRIVE
UNIT(S)
(3812)4685-45
F11ure 12-21. System Configuration Block Diagram.
12-82
4170
~NSTRUCTION
SECTION 12
THEORY OF OPERATION
BACKGROUND INFORMATION
Some background information (such as terminology and basic
concepts) is required in order to understand the actual theory of
operation. This discussion focuses on the type of media used by
disk drive units and examines disk data organization and
formatting.
Media
The flexible disk media, also called a floppy disk or
diskette, contains a thin, flexible plastic disk coated with
magnetic oxide. This disk is permanently enclosed and protected
by a square, hard paper jacket~ The magnetic disk is visible
through holes in the jacket provided for indexing and read/write
access.
Media Formatting
The diskette is divided into tracks and sectors (Figure 12-22).
As the diskette spins under the read/write (R/W) head, the head
traces a closed circular path around the disk. This path is where
the data is written and is called a track. As the R/W head
steps toward or away from the center of the disk, it traces
different tracks. There are 40 concentric tracks on one side of a
diskette. The lowest numbered track, 00, is on the outside of the
disk; the hiBhest numbered track, 39, is closest to the center.
An index hole that is read by a photocell (the Index Detector)
marks the beginning of each track. (1)
(1) The FDC also uses the index hole to tell when an entire track
has been scanned when seeking a particular data record. If the
data record is not found after a complete revolution of the disk,
the FDC aborts the search, notes an error, and goes on to the
next command. This prevents the FDC from being trapped in an
endless search.
4170 INSTRUCTION
12-83
SECTION 12
THEORY OF OPERATION
-
DIRECTION OF ROTATION
RELATIVE TO HEAD
INDEX HOLE
Figure 12-22. Flexible Disk Track and Sector Locations.
12-84
4170
INSTRUCTION
SECTION 12
THEORY OF OPERATION
The index hole also serves as a drive ready monitor. When the
Index Detector sees the hole twice, it knows a disk is in place
and ready.
Each track is divided into 8 separate data fields, called
sec tor s. En chi sid en t if i e d by its 0 wn ad d res slab e 1. Th i s
lAbel (called an Identifier Address Mark or ID AM) is
written and read by the same head that reads and writes the data.
This system of addressing by magnetic data is referred to as
soft-sectoring. An alternate system, not used by the 4170, is
called hard-sectoring. The hard-sectored diskette contains
holes, similar to the index hole, to mark the boundaries between
sectors.
Sectors having the same bit length vary in physical size
according to their distance from the center of the disk. Data
bits are naturally closer together on the higher numbered tracks.
Since a sector contains 512 bytes, an 8-sector track contains
4096 data bytes. Using 40 tracks and both sides of the diskette,
there is room for 327,680 data bytes per disk. These numbers
assume the standard double-sided, double-density encoded data
recording.
Sector Data Structure
During the formatting of a new diskette, the R/W head writes a
unique address label at the beginning of each track and sector.
At the same time, other bytes are written that allow the read
circuitry to synchronize with the sector and locate data
reliably.
Figure 12-23 shows how a sector is composed of identification
(address), synchronization, data, and separator fields. The top
line of the figure shows the pulse produced by the disk media
index hole passing under the Index Detector. The track header
follows this index mark, starting with a total of 92 bytes that
allow the read circuitry to synchronize for reading an address or
data. This header block contains GAP 1, which separates the track
header from the sector address (ID) field.
A similar gap (GAP
field. Another gap
thenext sector ID
sector (sector 8),
maik, replaces GAP
4170 INSTRUCTION
2) separates the track header from the data
(GAP 3) follows the data field p,nd precedes
field. However, if the sector is the last
GAP 4, which fills the space up to the index
3.
12-85
SBC~ION
12
THEORY OF OPERATION
At this point, the arrangement of eaps and fields is repeated,
startin~ around the next track (Figure 12-23). Each major segment
in the track-sector organization is shown as a rectangular box.
Each of these segments is then broken down further with its
subparts listed under the box. Refer also to ~able 12-7 for more
information.
12-86
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
n~
__________________n
I
I
I
I
I
TRACK HEADER
I
I
GAP 1
Preamble = 80 ByTes, 4E
(G4Al
Sync = 12 ByTes, 00
Index AM =3 BYTe.. C2
Gap 1 = 50 ByTes, 4E
I
I;;E;;:;:- SECTOR -
SECTOR ADDRESS
(ID FIELD)
~~~-
I
I
I
8
ISync = 12 ByTeS, 00
I
10 AM = 3 ByTes, AI
and 1 ByTe, FE
IseCTor*
GAP 2
Address 1.0. = 4 ByTeS
CRC = 2 ByTeS
22 ByTeS ,I
4E
1
I
I
I
I
DATA FIELD
t
OR
+
I
I
Sync = 12 ByTes, 00 I
DaTa AM = 3 ByTeS, AI
and 1 ByTe, FB I
Data = 512 Bytes
1
CRC = 2 By Tes
r:::-:-lI
~I
I
,.....---;
54 ByTes
4E
GAP 4
(POST AMBLE)
I ~ 768
...........- - - - - - - - - - SECTOR
-----------i..~1
Bytes
4E
* SecTor Address 1.0. Scheme'
Track No. = 00·27 = 00·39
SIde No. = :~ ~ ~~~: ~
SecTor No. = 01 t08 = 0 to 8
SecTor SIze = _51_2_ _ __
(3812)4685·47
Figure 12-23. Track-Sector Format.
4170 INSTRUCTION
12-87
SECTION 12
THEORY OF OPERATION
Table 12-7
IBM-COMPATIBLE MFM (a) FORMAT DESCRIPTION
: Major
: Segment : Description
: Segments : Parts
:
TRACK
HEADER
G4A
: Sync
I
I
Index
AN
Goes from physical index mark sync
allowing for physical index and
speed variations, and interchange
between disk drives.
: Is a fixed number of bytes for
: separator (b).
Is a unique byte that identifies
index field and is written with
special encoding rules (Figure
12-24b).
: GAP 1
I
I
ID FIELD
(Sector
Address)
Sync
Fixed number of bytes for separator
sync prior to the address mark. (b)
I D A!vI
A unique byte identifying the ID
field and written with special
encoding rules (Figure 12-24c).
ID
Is a four-byte address containing
track number, head number (two-sided
only), sector number, and sector
length.
: CRe
: Two bytes for CRe (cyclic redundancy:
: check).
:
I
I
GAP 2
12-88
: Goes from index address mark to ID
: field address mark sync.
Gap from ID CRe to data AM sync;
allows for speed variation,
oscillator variation, and erase core
clearance of ID CRC bytes prior to
write gate turn-on for an update
write.
4170
IllSTRUC~ION
~)ECTION 12
THEORY OF OPERATION
Table 12-7 (cont)
IBM-COMPATIBLE MFM (a) FORMAT DESCRIPTION
: Major
: Segment : Description
: Segments : Parts
:
: DATA
: FIELD
: Sync
I
I
: 12 bytes for Separator
: synchronization prior to an AM. (b)
A unique byte to identify the data
field and written according to
special encoding rules (see Figure
1 2-24d) .
: Data
: The area for user data storage.
: eRe
\ Two bytes for cyclic redundancy
I
check.
I
I
GAP 3
Gap from eRe to next ID AM sync.
Allows for: the erase core to clear
the data field eRC bytes; speed and
write oscillator variation; read
preamp recovery time; and system
turn-around time to read the
following ID field.
GAP 4
G4B is the last gap before physical
:
index and allows for speed and write :
oscillator variation (during format) :
and physical index variation.
:
(a) MFM stands for modified frequency modulation; see the
NF~1 Disk Encoding Nethod discussion.
(b) Includes a minimum of two bytes plus worst case separator
sync up requirements.
4170
IN~~TRucrrION
12-89
SECTION 12
THEORY OF OPERATION
A.
Jl~
__________________________________________________________________________________________ ____
GAP 4,0\
~
SYNC
INDEX
GAP 1
AM
CRC
ID
SYNC
GAP 2
DATA
SYNC
CRC
DATA
AM
GAP :3
~11~~~~
GAP 48
DATA FIELO
FORMAT
512 BYTES· 8 SECTORS
D.
1 SECTOR
LAST SECTOR
----BYTE 2
BYTE 1
CE~LI
B.
lAM = I NOEX AOORESS MARK
OATA = C2. CLOCK=14
,"
1
I
2
I
3
I
I
1
I
.2
I
3
IDAM = I D ADDRESS MARK
DATA = A 11 CLOCK= 0A
1
DATA = A1, CLOCK= 0A
5
I
CD I
"ICE~LI
DAM = DATA ADDRESS MARK
I
6
I
I
","
7
•
CELL
I
1
I
2
I
6
I
7
3
I ' I
I
3
I
4
I
5
I
ICE~LI
1
I
2
I
3
I
6
I
',"
7
•
I
1
I
2
I
6
I
7
• I
1
I
2
I
I
' I
4
I
I 0)
MISSING CLOCK TRANSISTIONS
5
I
6
I
7
Q2
5
I
6
I
7
ICE~LI
1
I
;t
•
ICELL
2
I
3
I ' I
5
I
6
I
7
• I CELL
0)
6
I
7
• I
1
I
2
I
3
I
---I
4
0)
;t
NO.
FLUX TRANS 1ST IONS
ICELL
I
NO.
----
;t
5
I CELL
FLUX TRANS 1ST IONS
"'
;t
~
3
CELL
I ,
3
I 0)
MISSING CLOCK TRANSISTIONS
CD
'-
I
~
ICELL
2
5
I 0)
MISSING CLOC!<: TRANSISTIONS
I ' I
----
D.
5
"-
ICE.LL
c.
,
0) I
----
BYTE :3
CELL
ICELL
5
I
6
I
7
• I CELL
NO.
FLUX TRANSISTIDNS
(3812)4685-48
Figure 12-24. Specially Encoded Field Separators.
12-90
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
MFM Disk Encoding Method
The disk unit uses MFM (modified frequency
which allows twice the storage capacity of
frequency modulation) encoding method. The
flux reversals on the diskette by changing
(north-to-south vs. south-to-north) of the
write head.
modulation) recording,
the usual (FM or
drive unit produces
the polarity
field applied by the
Looking at the FM system (Figure 12-25a) a flux reversal marks the
beginning of each bit cell, which is 4s long. An
additional flux reversal between clocks indicates a data bit
"one" in this cell. Conversely, a "zero" bit cell has no flux
reversals between clock pulses.
By comparison, the MFM system (Figure 12-25b) retains the
zer%ne coding but omits .the automatic clocks in each cell.
Instead, a clock reversal occurs only when two or more zeros
follow in succession; clocks are inserted at the boundaries of
these adjacent zero cells. Also, as in FM, a reversal occurs for
everyone cell. By eliminating clocks where data reversals exist,
the bit cells can be 2s long -- half the space needed for
FM encoding. This effectively doubles the storage capacity of the
MFM-encoded diskette.
4170 INSTRUCTION
12-91
SECTION 12
THEORY OF OPERATION
BIT
CELLS
o
o
o
o
FM
1 BIT CELL=
4 11 sec
__I 1--
1__
2 11 sec
4 11 sec
1F
2F
A. FM Encoding.
111111011101010111
MFM
1 BIT CELL=
2 11 sec
~ 2 1 2 1
2F
2F
4
1F
1 3 1 2 1 3
4/3F
2F
1_
11 sec
4/3F
B. MFM Encoding.
3812·17
Figure 12-25. Flexible Disk Encoding Formats.
12-92
41~O
INSTRUCTION
SECTION 12
THEORY OF OPERATION
Write Precompensation
Flux reversal locations are adjusted to maintain a uniform timing
of read pulses; this system is called write recompensation.
It is normal for magnetic flux reversals data to relax move)
into a stable location shortly after they are written on the
disk. This is caused by interaction of magnetic field forces in
close proximity. The extent and direction of these reversal
movements depends on the pattern of adjacent zer%ne bits in the
write stream. There are many combinations that cause a shift, but
only the worst cases require compensation in order for the read
head to sense the reversal where expected.
The write precompensation circuitry within the FDC looks at the
serial bit patterns before they are written on the disk. Then it
adjusts the write times as necessary up to +/-125 ns, depending
on the bit pattern. The resulting data on the diskette has
uniform bit cell spacing. This is called precompensation
because a correction is entered before the data is written,
rather than trying to correct the data stream when it is read.
OPERATION OVERVIEW
During operation, the main processor and the FDC talk to each
other. Of these, the terminal processor is the more intelligent
and can send commands asking the FDC to do certain jobs. The FDC
is slower and needs access to the system bus, so the FDC responds
to most commands from the processor by requesting the bus for
small time slices. The processor grants the FDC bus control and
waits for the FDC to complete the job. The FDC generates an
interrupt when it finishes the task. The interrupt tells the
processor that the FDC no longer needs the bus. The FDC then
waits for the next command from the processor.
Hardware operations (reads, writes, etc.) are based on the three
principle operating phases of the FDC chip:
o
Status/Command
o
Execution
o
Hesults
Figures 12-26 through 12-28 compare the various input signals
during the three operating phases.
4170 INSTRUCTION
12-93
------.--1
BIT 6 IN MAIN STATUS REG
BIT 7 IN MAIN STATUS REG
51
[;;1
~~
I~
~
"8
(~
08
a
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z
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......,
.-J
..... ;..:1
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">J-'
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----~1
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a
";c:
;c:
l>
Z
0
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rn
P'
:=s
REPEAT STEPS 3 THRU 6
UNTIL ALL BYTES IN INSTRUCTION
HAVE BEEN WRITTEN INTO 765
~
~
::r
P'
m
.....
CD
t-3
.....
a.....
LAST BYTE OF I NSTRUCTION WRITTEN INTO
765 BY PROCESSOR
I
I
I
I
I
I
I
· 1~~
,~
'~
~
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~~-:J ~.~~~--
:=s
.;::,..
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en
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o>Z
en
l>
!:rj
:::u
);>
..-3
rl
0
Z
SECTION 12
THEORY OF OPERATION
COMMAND PHASE -______
EXECUTION PHASE
-----_---~
RESULT PHASE - -
I
INT - - - - - - - - - -
,
ORO
n
rr
r(n
- - - - - - . J L--J ~j.J L-....,,~~I----:--------
STARTS
AUTQMATICAlL'Y
BECAUSE OF
EITHER
®OR
TC
®
--------,5L-1Lf~[_---:--_ _ _ _ _~rL
®
WR~flf*7~
RO~'lf*7/UlJ7lJlJ*1JlJ*
®
o ABNORMAL
•
•
•
•
TERMINATION
NO ADDRESS MARKS
CRC ERROR
LAST SECTOR ON TRACK
IMPROPER COMMAND
• READY LINE GOES lOW
• 2ND TIME INDEX HOLE
IS DETECTED DURING
EXECUTION PHASE
• OTHER
}j0/Y
010
CS
---u---::u
////
////"///
'---------~~----
Jr~
,, ,,
DMA MOIl£
NON- DMA MODE
l:::.
z
~
ir
~
z
*"
0
~
u
:>
~
~
~
~
:0
~~
[;;
m
0
Z
~
;;
~
;;
::I
::I
t:i:?
;:)i
~
~
III
121
IJI
(4)
~~
,.
NOTE EITHER RO (IF IT ISA READ INSTRUCTION)
OR WR (IF IT IS A WRITE INSTRUCTION) BUT ~ BOTH
I
4
~~
m~
STEP NO
i"
NOTE IN THE NQN-DMA MODE ROM GOES HIGH (I)
AT THE SAME TIME INT OCCURS, AND IF THE
PROCESSOR IS POLLING ON THIS BIT IN THE
STATUS REGISTER, IT MAY BE USED INSTEAD OF
THE INTURRUPT SIGNAL
151
161
171 181
191 1101
3812-124
Figure 12-27. Execution Phase Timing.
4170 INSTRUCTION
12-95
SECTION 12
THEORY OF OPERATION
-
EXECUTION PHASE - - - _ " 1 . 0 - - - -
RESULT PHASE
---
----~.I--.
I
COMMAND PHASE OF NEXT INSTRUCTlON-
I
INT
ORQ
----'II<------!fJi-L-----~
ff
~------------------~h~----------~--
1J
TC
nL-_ _ _ _ _-J,u!-L_ _ _ _-:--
71
r-u-r
*
EITHER Rli (IF IT IS A READ INSTRUCTION I
OR WR (If IT IS A WRITE INSTRUCTION I
BUT tID1B BOTH
010 ,
~
w
g.~ ~
"'~'"
>-w
~.
~
~:; ~ ~
a::
0 ~ ~.
~~ ~~
~:;tJ:
02: 0 0
croa::a::
a..a:;:a..l.L.
STEP NO
(11
( 21
8
~
z
::l
Q.
Q.
~
c
~~ t:;
N
Q.
t;; t;;
~
«
w
~
(31
t;
w
t;
w
:a
'"
(41
(51
:a
~
w
'"
3812·125
Figure 12-28. Result Phase Timing.
12-96
4170 IKSTRUCTION
SECTION 12
THEORY OF OPERATION
Status/Command Phase
The Status/Command phase begins with the processor reading the
disk firmware. The processor uses the information found in the
firmware to program the Disk Controller board hardware. The
processor then receives a request for a disk seek, read, or write
and assembles the set of instructions required for the operation.
All processor-to-disk communication is transmitted via the disk
I/O port in I/O address space FCOO to FC09 (Table 12-8).
Table 12-8
I/O PORT MEMORY MAP
: I/O Address
: Register
: Base address+O : Board Status
: J3ase address+1
: Eits A16 to A19 of D~1A starting address:
: Ease address+2
: Bits A8 to A15 of DMA starting address
: Base address+3
: Bits AO to A7 of DNA starting address
: Ease address+6
: FDC abort
: Ease address+7 : Step DMA
: Ease address+8 : FDC status
: Base address+9 : FDC Command/Result data
Figure 12-29 illustrates the steps the processor takes during the
Status/Command phase. The processor first programs the Board
Status Register (FCOO). Its contents determine the following
conditions:
o The interrupt enable (INT on the Control Eus) is set
o The DMA direction bit is set (read/write)
(The complete contents of this register are shown in Table 12-11,
under the Board Status Register circuit description.)
4170 INS';1RUCr;'ION
12-97
SECTION 12
THEORY OF OPERATION
4170 BUS
PROCESSOR
DISK
CONTROLLER
BOARD
FDC INTERNAL
STATUS REGISTER
CHECK - ROM
-DIO
I/O PORT
(FIgure 4-6B)
_F_C_DD--.t
BOARD STATUS
SET - HEAD LOAD
-INTERRUPTS
- READ vs.
WRITE
FCD?
STEP
DMA
DMA ADDRESS
STARTING
LOCATION
(3812)4685-49
Figure 12-29. Status Flow Sequence.
12-98
4170 IKSTRUCTION
SECTION 12
THEORY OF OPERATION
7he processor then goes to I/O address space FC01
FC03 where
it writes the memory location of the first Direct Memory Access
(between disk and RAM). Next, the processor reads a status
register located inside the FDC chip (Table 12-9) and polls two
bits of this register. The following information is expected:
(Bit 8) which means FDC is not busy and is listening
0
RQfv1-1
0
DIO-O (Bit 7) 'Nh i ch means the direction of data flow is into
the FDC
The processor can now write the first instruction byte to the
FDC Data Register. This corresponds to the process shown in
Figure 12-30.
4170 INSTRUCTION
12-99
SECTION 12
THEORY OF OPERATION
COMMAND
OUTPUT TO FOC
",--,
NO
/ FDC \
~ BUSY? )
"..........
/
>--N-O--ll~8
(OAT A 0 I RECTI ON
IN/OUT)
YES
NO
EXECUTION
PHASE
INTERRUPT
PROCESSOR
___________ .J
(3812)4685-50
Figure 12-,0. Command/Execution/Result Flowchart.
12-100
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Table 12-9
FDC STATUS BYTE
: Bit: Mnemonic: Type
: Description
D7
RQM-1
Read Only
This bit indicates that the
data register is ready to send
data to or receive data from
the processor. Both the RQf1-1
and DIO-1 bits should be used
to determine " ready" and
"direction."
D6
DIO-1
Read Only
This bit indicates the
direction of the data transfer
for the data register. A zero
indicates that data should be
written to the FDC and a one
indicates that data should be
read from the FDC. This bit is
only valid when RQM is true.
Read Only
This bit indicates whether the
FDC is in DMA mode or non-DMA
mode. The interface must use
the DMA mode; therefore, the
bit must be a zero.
D5
D4
CB-1
Read Only : This command indicates that
:
I the FDC is busy with a read or :
I write command.
I
: Read Only: This bit indicates that Drive
: 3 is in the seek mode.
: D3
: D3B-1
I
I
I
: D2
: D2B-1
I Read Only: This bit indicates that Drive
I
:
I
I
I
I
I
: 2 is in the seek mode.
: D1
: D1B-1
: Read Only: This bit indicates that Drive
:
: 1 is in the seek mode.
: DO
: DOB-1
: Read Only: This bit indicates that Drive
:
: 0 is in the seek mode.
I
I
I
I
I
I
I
I
4170 INSTRUCTION
12-1 01
SECTION 12
THJ~ORY OF OPERATION
Execution Phase
The execution phase consists of performing one of the following
o perat ions:
o
Pecal/Seek
o
Read
o
Write
o
Format
Most operations are a variation of a read or write. Therefore,
the execution phase is explained in terms of a typical disk write
operation. Later, you will see how the execution phase is
different for a read operations. In all operations but seek (read
and write), the hardware employs DMA (Direct Memory Access) to
the systeo RAMs. (1)
(1) Using DMA means the Disk Controller board becomes a bus
master, addressing RAM directly without involving the main
processor.
Write Operation. The write operation begins with the FDC
sending a DRQ (Dr~IA Request) to the DMA State Machine. The DMA
State Hachine sends a bus request (BREQ and CBRQ) , and examines
the BUSY and BPRN lines to see if the bus is busy serving another
bus master. If the bus is busy, the State Machine waits until the
bus is available, then asserts its own BUSY on the bus. The Disk
Controller board then becomes the temporary bus master.
At this time, the State Machine asserts DACK (DMA Acknowledge).
DACK is sent to the FDC, confirming that DMA is granted; the FDC
then removes DRQ. The DACK line also controls a Strobe switch,
and enables the Address Counter/Buffer.
When the Address Counter receives a DACK, the Counter places its
RAM address on the bus. This address with EHEN (Byte High Enable)
remains on the bus until the data is read by the FDC and DACK is
removed. When DACK is removed, the address is incremented (its
counter is decremented).
12-102
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
During the commflnd phase, the DMA direction bit is set. This has
the effect of setting the R/W line (which enters the Control
Strobes), causing'ihe 'Dt1AREAD line to connect to the bus via the
MRDC line; this connects the DMA WRITE line to the FDC WR
input. A WR causes the FDC to execute a single internal write
operation~ The R/W line also enters the DMA State Machine; when
the machine receives W (R/W-O), it eXflmines and waits for an ACK1
or ACK2 to be a~serted by the RAMs. (When the RAMs are finished
with a read or write cycle, they will respond with the proper
acknowledge, ACK1 or ACK2.) After the RAMs write the data onto
the bus, the WR is removed. At this transition the data byte is
written'into the rDC Data Register; then the MRDC is removed and,
as stated earlier, DACK goes away. ~hus the RAM address is
clear~d fro~'the b~s,and the address is incremented (Figure
12-31).
4170 INSTRUCTION
12-103
SECTION 12
THEORY OF OPERATION
RAM
PROCESSOR
t
A
U
~
DATA
~
.
'f
.~
A
.)
ADDRESS
..
I
A
.
rl
DMA R
STATUS
~
.....
~
DMA W
~
~
......
R/W
-r
DECODE
"'III ........ ~
0
......
RD
~
--{)
0
J
..
UI
MRDC
DMA
(STATE
MACHINE)
~
r----------.J
CONTROL
.,.",
......
WR
Foe
~
()
DACK
'1
DRIVE
UNIT
3612-20
Figure 12-31. Write to Disk Signal Flow.
12-104
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The data byte is then processed by the FDC internal processors
as follows:
o
Transformed from parallel to serial data.
o
Adjusted for write precompensation.
o
Written to the track-sector on the disk.
The execution process just described is repeated for each
additional byte of I/O data. When FDC instructions call for
writing data on a complete sector (in double-density), 512 DMA
byte transfers are executed per sector. Multiple sectors may be
transferred in one command. One byte is processed every
32s. The actual time when the DNA transfer is passing data
over the terminal bus is (approximately) 1s.
When the last byte transfer in the instruction set is completed,
the FDC generates an interrupt (EOC). This interrupt passes
through the Board Status Register and is placed on the Control
bus. The interrupt tells the processor that the FDC has completed
its work and is ready for the result phase to begin.
Read Operation. The previous discussion covered the DMA
control circuitry during a write operation. Here the same
circuitry is studied during a read operation.
During the command phase, DACK is set, and the R/W direction line
is set to READ. The R/W line then sets the Control Strobe
switches so the DMA WRITE line (from the State Machine) connects
to the terminal bus ViWTC and AMWTC lines. Also, the DMA READ
line connects to the FDC RD operation. The same timing and
addressing scheme used for FDC writes applies to FDC reads; thus
disk data is placed on the bus by the FDC and then accepted by
the RAMs (Figure 12-32).
4110 INSTRUCTION
12-105
S:FJCTION 12
THEORY OF OPERATION
PROCESSOR
RAM
t
A
fi
DATA
..
r
'f
.
A
ADDRESS
'f
A
(
,._~
CONTROL
I
---1
STATUS
~
0
DMA ....
-0
"
~
R/W
RD
~
",Jr
....R
FDC
~
0
I
DECODE
DMA R
I-
r
JJ I
M.... TC
~
.
_______ J
'f
DMA
(STATE
MACHINE)
r
j
'1
-0
DACK
t
DRIVE
UNIT
3812-21
Figure 12-32. Read from Disk Data Flow.
12-106
4170 INSTRUCTION
SECTION 12
THEORY 01" OPERATION
Resul t Phase
During the result phase the processor reads the Main Status
Register and waits for RQM and DIO to go high. The processor then
reads up to seven bytes of response/status data from the FDC and
w~its for RQM and DIO to go high after reading each byte. Each
status byte is read, one at a time, from an internal data
register. The number and selection of bytes read depends on the
instruction just executed. When the last byte is read, the Result
phase is completed, and the FDC is ready to service the next set
of instructions (disk operation) from the processor.
After the Result phase is completed, the processor again reads
the Hain Status Register and waits for ROM to go high. vlhen DIO
goes low, the processor then writes the first byte of the next
set of instructions, and the entire cycle starts over again.
After the status bytes are read, the Motor On timer is set
(enabled). This keeps the motor on for two seconds in case the
next operation also needs the motor to be on; this avoids
motor-turn-on delays.
CIRCUIT DESCRIPTIONS
This section focuses on the general operation of the hardware
rather than on program-dependent operating states. Figure 12-33
is a functional block diagram of the Disk Controller board logic.
'\
4170 INSTRUCTION
12-107
SECTION 12
THEORY OF OPERATION
DATA BUS
1111
4170
PROCESSOR
BUS
II
1111
BPRN,
BUSY.
ACK 1 ,
ACK2.
z
'j!
"
BelK
AI3-A3
OACK
ADDRESS
BUFFERS
INPUT
DATA
BUFFERS
BW/BR
*ALT. ORQ,
FOR TEST ONLY
HL0-3
'-----------------~1'4
'---------------------------------L---------------------~~'5
'---------------------------------------------------------~--_.~'B
FLEXIBLE
DISK UNITS
INTERFACES
DISK
CONTROLLER
WRITE GATE
r--:~:-_,r_----------------------------~RO~---.~23
READ DA TA
READ
/------------------------------'-1 RECOVERY
/ -________________________--=O"'A-"TA::....::W-,-I",NO",O",W,-,ooJ
vco SYNC
22
~(P~.L~.:L~.~)~~------~r-----------------~M~F~M-----I~:
~--------------~W~C~K----~2'
~-------L----------------------------------_B~M~H=Z---;~'9
L;3::;"p.,3::;;2:,:,3:,;.'_..J
1<===~======~======================::::::::::::::::~WDliA~,~P5~.L!~PS[jc:~/
(3812)4685-51
Figure 12-33. Disk Controller Board Block Diagram.
12-108
4170 INSTHUCTION
SECTION 12
THEORY OF OPERATION
Disk Drive Control
The Flexible Disk Controller (FDC) is a single IC that is the
mRin component of the Disk Drive Control (Schematic A3-4). The
FDC handles the following functions and operations:
a
Serial-to-Parallel Write data conversion from the 4170 Data
Bus to the Disk Drive Unit(s).
o
Calculation of the amount of Write Precompensation for each
combination of serial data bits and adjustment of the write
data stream accordingly.
a
Serial-to-Parallel Read data conversion from the Disk Drive
Unit(s) to the 4170 bus.
o
Disk Drive Unit(s) fu~ction controls: Head Select, Unit
Select, RW/Seek.
a
Disk Drive Unit(s) status: Ready, Write-Protect, Index,
Track 00.
o
DMA State Machine control.
To handle these functions, the FDC has two internal processors,
several data and status registers, and several buffers. The FDC
also has separate READ and WRITE control lines that come from the
Control Strobes.
4170
INS~RUCTION
12-109
~mCTION 12
THEORY OF OPERATION
INTERNAL
BUS
BOARD I/F
DATA BUS
BUFFER
DBI1J-7
DATA
REGISTER
STATUS
REGISTER
....- WR CLOCK
WR DATA
DMA TRANSFER (TERM I NAl )
COMPLETE
COUNT
~
SERIAL
INTERFACE
CONTROLLER
ORO
INT
WR ENABLE
PRE-SHIFT '"
PRE-SHIFT 1
RD DATA
READ DATA WINDOW
DATA OUT OF FDC-(RD).o
DATA INTO FDC-(WR) . 0
DATAl STATUS
REG SELECT - (AI1J)-I N IT - (RESET) __
READI
WRITEI
DMA
CONTROL
LOGIC
Veo SYNC
.... READy
INPUT ....WRITE PROTECTI
TWO SIDE
PORT .... INDEX
----It
CS _ _
ClK - -
Vee - GND __
....FAUlTI
TRACK 0
DRIVE
INTERFACE
CONTROLLER
OUTPUT
PORT
UN I T SELECT 0
UNIT SELECT 1
MFM MODE
RW/SEEK
HEAD LOAD
HEAD SELECT
LOW CURRENT I
DIRECTION
FAULT/RESETI
STEP
3812-23
Figure 12-34. FDC Simplified Block Diagram.
12-110
4170 IKSTRUCTION
SECTION 12
THEORY OF OPERATION
~he
FDC is programmable and is controlled by the terminal
processor. The firmware determines its operating modes and
parameters. Commands and instructions enter the F'DC through the
Data Register (FC09). The FDC has an 8-bit data bus and data
registers, while the processor uses 16-bit words. An external
multiplexer converts the 16-bit processor instructions into 8-bit
bytes, which the FDC can properly store and execute. A detailed
description of the data multiplexer appears in the FDC Data NUX
description.
~he FDC keeps its eight bits of status
information in a one-byte internal register. Only the FDC itself
can write into this status register. The processor nust read this
register before it can send or receive instructions to and from
the Data Registers. Table 12-9 defines the contents of the
status word contained in this register, accessed via FC08.
I/O Registers.
The Address Decoder translates addresses FC08 and FCOg into three
control lines: AO, UR-O, and RD-O; these lines determine whether
the data or status registers are enabled. Table 12-10 shows which
combinations are needed to access these internal registers.
Table 12-10
3-TO-1 DECODER
: Select :
: Inputs :
Input Selected
(X-Don't Care)
: Output
I
I
: A : B
: CO : C1 : C2 : C3 : Wr i te Data :
: 1 : 1
: 1
: X
: X
: X
: 1
: 1 : 1
: H
: X
: X
: X
: H
: H : 1
: X
: 1
: X
: X
: 1
: H : 1
: X
: H
: X
: X
: II
: 1 : H
: X
: X
: 1
: X
: 1
: 1 : H
: X
: X
: IT
: X
: H
: H : H
: X
: X
: X
: H
: H
4170 INSTRUCTION
12-111
SECTION 12
THEORY OF OPERATION
Timing Information. The timing of the FDC operations is
controlled by two external clocks which enter Pin 19 (4 MHz CLK)
and Pin 21 (WR CLOCK). ~he 4 MHz clock times all internal
operations except the write data output. The write data stream to
the disk is timed, synchronized, and set for MFM by the WR CLOCK.
A combination of FDC interrupts and processor timing determines
the rate of data flow to and from the 4170 bus. During disk data
transfers between the FDC and the processor, the FDC is connected
to the terminal bus and does a DMA transfer every 32s. If
the FDC is not serviced in time, it sets the OR (Over Run) flag
in the Status Register and terminates the current command.
Clocks
The Master Clocks and Write Clock circuits (Schematic A3-4)
generate the Master Clock and Write Clock signals (Figure 12-35).
12-112
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
MASTER CLOCKS
8MHz
TO WRITE
PRECOMPENSA TION
CIRCUITRY
CRYSTAL
OSCILLATOR
-- --~
J225
4MHz
To FOC
Clock Input
DIVIDE
BY TWO
250 ns
PULSE WIDTH
GATE
WRITE CLOCKS
2MHz
L..-
DIVIDER
COUNTER
lMHz
eI.SMHz
1\
L-J
WCK
To FOC
(3812)4685-52
Figure 12-35. Clock Circuits.
4170 INSTRUCTION
12-113
SECTION 12
THEORY OF OPERATION
Master Clocks. This circuit block generates the following
clock signals:
o
8 MHz for the Write Precompensation
o
4
o
~Hz
for FDC timing
r,1Hz for Wri te Clock
An r;3 ['Hlz, crystal-controlled oscillator circui t generates the
Master Clock signals. The oscillator output controls the Write
Precompensation IORic and also generates the Write Clocks.
Write Clock. The Write Clock logic provides the timing
signal WCK (Write Clock) for the FDC write data stream to the
disk. A divider/counter takes the Master Clock 8 fiIllz signal and
divides it by 4, 8, and 16. The outputs of the divider lQB, QC,
and QD) become 2 MHz, 1 MHz, and 0.5 MHz respectively. ~he
divider outputs are ANDed, producing a 0.5 MHz clock with a pulse
width of 250 ns -- determined by the 2-MHz input. The output
signal is called WCK. Refer to the Write Clock waveforms in
Fieure 12-36.
12-114
4170 INSTRUCTION
SEC TIOll 12
THEORY OF OPERATION
-j
r-
250 ns
1 2M Hz
2 1MHz
Q~
3 .5MHz
~
WCK
L
Jl
n
L . . . - - -_ _
IL
(3812)4685-53
Figure 12-36. Write Clock Waveforms.
4170 INSTRUCTION
12-115
SECTION 12
THEORY OF OPERATION
Write Control
The precompensation and write protection circuits are the only
blocks that affect the path of data written to the disk.
Write Precompensation. The \'lri te Precompensation lOGic
(Schematic A3-4) takes the serial stream of write data (WDA) and
adjusts each bit as needed (up to +/-125 ns) to compensate for
magnetic interactions on the disk. After the data is written and
relaxes into its stable position, the bit cells appear more
uniformly spaced on the disk, making the disk easier to read.
Refer to the Write Precompensation explanation earlier in this
section.
The FDC computes the compensation shift needed for each bit
pattern. It then tells this circuit block to adjust the bit
spacing accordingly. (Some bit patterns will not need Write
Precompensation.)
The write precompensation logic consists of an 8-bit Shift
Register and a 3-to-1 decoder. The FDC sends a stream of write
data (WDA) to both inputs of the shift register; thus no input
comparison is performed by this chip. Only three outputs from
this chip are used: the B output represents no relative shift,
and the A and C outputs represent late and early shifts relative
to B. The 8-t·1Hz clock input (from the 1'·1aster Clock block)
determines the time value of these shifts. The standard bit shift
(between normal and early or normal and late) is 125 ns (Figure
12-37).
12-116
4170 INSTRUCTION
SECTION 12
'l'HEOHY OF OPERATION
STANDARD 125 ns
~ ___
A _ _ _ _ _ _ _ _~/l~
~
___________.
/l~_
B
___C
____________~/l~
C2 EARLY
CO NORMAL
__________________
C1 LATE
(3812)4685-54
Figure 12-37. Bit Shift Selection.
4170 INSTRUC'l'ION
12-117
~)ECTION 12
THEORY OF OPERATION
The Write Control logic also chooses between the EARLY, 10R~AL,
and LATE lines and decodes them back into a s(~rial bit stream. To
do this, the 3-to-1 decoder accepts the Shift Register outputs
and selects the proper one as directed by the FDC.
The FDC determines whether a shift is needed (and whether it is
plus or minus). It then requests the shift via its PSO (Pre-Shift
0) and PS1 lines, which enter the decoder A and B select
inputs. Table 12-10 shows the combinations of A and B that are
needed to select EARLY, NORMAL, and LATE lines. The output is
cRlled WHITEDATA and is based on the timin~ of the NORMAL bit
line (Figure 12-38).
12-11(3
4170 IIJSTRUCTION
SECTION 12
THEORY OF OPERATION
WRITE PRECOMPENSATION
FDC
WRITE DATA
TO DISK
(3812)4685-55
Figure 12-38. Write Precompensation Block.
,
"
4170 INSTRUCTION
12-119
SECTION 12
THEORY OF OPERATION
Write-Protect Block. The Write-Protect (WP) logic
,
(Schematic A3-4) gathers all WP inputs (protected disk media and
WP switches), reports each drive unit WP status to the FDC, and
controls the Write Enable line (to the write heads) (Figure
12-39).
12-120
4170 INSTRUCTION
SEcrnON 12
THEORY OF OPERATION
Wop LEOS
AND SWITCHES
(FRONT PANEL)
o
o
Slo/l
'-r-'
,...
I
DRIVE UNIT
SELECTOR
(2 to 1 DECODER)
I
~------""'I---o....~ II -"
~------~I---1JO
SIo/f2J
D
II~~J--r-__----~--~
WRITE PROTECT/
TWO SIDED
MEDIA STATUS
'"
WRITE ENABLE
GATE
WRITE
ENABLE
Io/P
DISK DRIVE
UNITS 0 & 1
(3812)4685-56
Figure 12-39. Write-Protect Circuit.
4170 INSTRUCTION
12-121
SECTION 12
THBORY OF OPERATION
The presence of tape on the write-protect slot is detected by the
LED-photocell. Any disk media can be temporrrrily protected by
setting the WP switch (on the disk unit contAining that media) to
"protected." The adjacent LED will then light.
The WP switches are connected to a drive unit selector. The
2-to-1 decoder functions as rr drive unit selector. The decoder is
switched by the FDC usa (Unit Select 0) and US1 lines. The
protection status of a particular drive unit and its media is
sent to the Write Enable gate. This gate ANDs the FDC Write
:t~nable line wi th the decoder output and makes the WHITE GATE
line. This output operates with the Drive Select control lines to
enable the selected drive ONLY IF THAT DRIVE IS NOT
ltmIT i'~-PROTECT b-;D.
Read Recovery. The Read Recovery circuit (Schematic
A3-4) takes read data from the disk, stretches the pulses to a
uniform 100 ns, sends the data to the FDC, and sends clock pulses
to the FDC RDD input during a write to the disk.
Part of this logic also takes data or clock pulses and
synthesizes a constant pulse frequency; it creates a time window
that the FDC uses to discriminrrte between data and clock pulses
on the incominf, READ DATA stream from the disk.
The Read Recovery logic consists of Clock MUX (~ultiplexer), Data
MUX, Timing, Frequency Synthesizer, and Counter circuitry (Figure
12-40).
12-122
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
VCO SYNC
r----------------
l
0.5 MHz CLOCK
READ DATA
DATA
IN
i
11'sec
PULSE
I
..
r
~
DATA
MUX
FREQUENCY
SYNTHESIZER
(P.L.L.)
100 nsec
PULSE
STRETCH
RDD
DISK
CONTROLLER
CHIP
(.5MHz nom.)
DIV. BY 2
COUNTER
~
READ
DATA
WINDOW
(TIME DELAY)
(3812)4685-57
Figure 12-40. Read Recovery Circuit Block.
41 '70 INS'rRUCTION
12-123
SECTION 12
THEORY OF OPERATION
The Data NUX switches between the CLOCK input and the READ DATA
line (from the Drive Unit's read/write head). When reading valid
data from the disk, the Data NUX is in the READ DATA position.
During disk writes, "idle time," or while unwanted data or data
gaps are read, the incoming data frequency may vary drastically.
This means that when valid deta reappears, it may take longer for
the PLL (phase-locked loop) to come back to the right frequency
and sync on it. To overcome this problem, the Data MUX switches
the input to a constant 0.5 MHz, the CLOCK input. The 0.5 MHz is
very close to the normal data frequency.
~he Data NUX output connects to both the READ DATA path and the
Read Data Window path. The READ DATA path passes through 2
one-shot that stretches all incoming pulses to a uniform 100 ns
duration. This makes it easier for the FDC to synchronize on the
incoming data/clock pulses.
The other half of the Data MUX output enters another one-shot.
This 1000 ns one-shot gives a time delay before pulses
reach the frequency synthesizer ci.rcuit. 'l'he time de18_y
simulates the normal pulse duration for read data. The pulse
dura t i on is half the pe riod fa r the normal input frequency. Th e
shaped data stream then passes into the phase-locked loop
frequency synthesizer.
Pha.se-Locked Loop. The phase-locked loop allO'."s the
decoder to track directly on the raw data stream, thus
eliminating the jitter caused by magnetic interactions on the
disk.
Figure 12-41 shows the phase-locked loop diagram. This circuit
functions as a frequency synthesizer and stabilizer. The incoming
data stream first passes through a phase detector where it is
compared against an error signal on a feedback i~put. ~he
resulting difference is translated into an analog signal by the
charge pump. This signal is then integrated, to give a
picture of trends occurring over time, before entering the
voltage-controlled oscillator (VCO, not to be confused with the
VCO SYNC line from the FDC). The oscillator produces a digital
clock Signal that is shifted (plus or minus) according to the
error present (if any). This error signal is fed back into the
phase comparator, so the whole circuit acts like a
frequency-regulating servo. A counter in the feedback path
divides the oscillator frequency down to 0.5 MHz and sends it
back to the Detector Enable.
12-124
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
J200-6
DATA_.-__~__~R~~________~
IN
DETECTOR
ENABLE
Ul
PHASE
DETECTOR
01
UF
PU
PO
CHARGE
PUMP
us
VCO
U10SA
I
y
U20/U17
o
J10
J200-7
U1SB
0.5 MHz
+16(FMJ
COUNTER~------------~
READ DATA - - - - - - - - - - - -Roo-B
To O'--IY-ro-E-B-y----l...
2 COUNTER
/!In d
WINDOW
(3812)4685-58
Figure 12-41. Phase-Locked Loop.
4170 INSTRUCTION
12-1 25
SECTION 12
THEORY OF OPERATION
The Detector Enable circuit is comprised of a flip-flop array.
Ordinarily, the VeO/counter is feeding constant 0.5 MHz pulses
into the feedback input on the phase comparator. At the same time
data stream pulses, "it approximately 250 KHz, are entering the
main input of the Ph8.se Detector. Furthermore, there are times
when this MFM data stream goes several feedback pulses without
producing a clock or data pulse. This means that the feedback VCO
pulses are not always accompanied by a data/clock pulse; the
phase-locked loop misreads this as a drastic change in input
frequency. Consequently, the VCO tries to shift its output
accordingly, producing a large and unnecessary error correction.
The Detector Enable circuit solves this problem by interrupting
the feedback veo, unless there is a data pulse present for a
valid comparison. The circuit, comprised of flip-flops and
inverters, acts basically like a NAND gate. The purpose of the
inverters is to provide the necessary pulse width for the
fl i p- flops.
After this timing signal has made a complete loop through the
PLL, it is stabilized and extracted just prior to the Detector
Enable. This signal then passes through one more counter (a
divide-by-two) before entering the FDC ''is RDW (Read Data Window) .
The Read Data Window line provides the timing window for
data/clock separation.
Disk Drive Control
The Disk Drive Control circuitry (Schematic A3-4) buffers and
strobes the control lines ~oing between the FDC and the Disk
Drive Unit(s)(Figure 12-42;.
12-1 26
4170 INSTRUCTION
SEC TION 12
'rHEORY 01" OPERATION
( From
Bo~rd
St~tus
)
Block:
HU1J-HL3
>1
_________
-
.)
USIZJ-l
MOTOR ON
>
B_U_FF_E_R_~___
L __
DRIVE
SELECT
DECODE
EXTHDLDIZJ-3
.
DRIVE SELIZJ-3
(3812)4685-59
Figure 12-42. Disk Drive Control Block.
4170 INSTRUCTION
12-127
SEC~ION 12
THEORY OF OPERATION
The control lines are:
o
Motor On (managed by the processor instead of the FDC)
o
Unit Select
o
Direction (of the step, toward or away from the center)
o
Step (from one track to the next)
o
Side Select
The response or feedback lines from the drive unit(s) are:
o
Track 00 (location)
o
Write-Protect
o
Index (marker response)
The four Motor On lines (Figure 12-42) come from the Board Status
Register, are buffered, and go to the drive units.
The drive units are selected by the FDC via its Unit Select
lines. The 2-to-4 decoder makes USO and US1 into DRIVSEL-O
through DRIVSEL-3.
The remaining lines control and monitor the operation of the
drive units. These lines pass through buffers where muJ.tiplexing
also takes place. The RW/SEEK line and its complement alternately
strobe two sets of buffered control lines. The Side Select line
is only used with two-sided drive units. The Direction and Step
lines are multiplexed together.
Of the five monitor lir.es (from the disk), two are inverted but
not multiplexed: Index and Ready. The Write-Protect line is
multiplexed by RW, and the Track 00 and Two-Sided lines are
multiplexed by SEEK. Multiplexing these lines is necessary
because the FDC does not have enough input pins.
12-128
4170
INSTRUC~ION
SECTION 12
THEORY OF OPERATION
Terminal Bus Interface
The following logic controls handle the flow of data, addresses,
DMA control, FDC control, and disk control signals between the
4170 bus and the Disk Controller hoard:
o
Data MUX (Schematic A3-2)
o
Input Data Buffers (Schematic A3-3)
o
Address Counters (Schematic A3-3)
o
Address Decoder (Schematic A3-3)
o
Board Status (Schematic A3-3)
o
DMA State
o
Control Strobes (Schematics A3-2, -3)
~achine
(Schematic A3-2)
Data MUX. The Data MUX (Multiplexer) (Schematic A3-2)
takes the 16-bit data/instructions from the 4170 bus and converts
them to 8-bit bytes for the FDC internal data bus and registers.
Two transceivers function as a tri-state buffer between the 4170
bus and the FDC data bus. To accomplish the 16-to-B bit
multiplexing, the decoder acts as a switch which enables either
one or the other transceiver. BllEN on the decoder A input becomes
output Y2 (to the high byte transceiver), and AO on the B input
becomes Y1. Either a Read (RD-O) or Write (WR-O) input to the FDC
strobes this decoder/switch.
Input Data Buffer. 'l'he Input Data Buffers (Schematic
A3-3) take processor data from the 4170 data bus and store it
until it is loaded into the Address Counter ReBister and Board
Status Register.
The sixteen data lines are buffered by three tri-state
buffer/driver ICs. This circuit appears in the upper-left corner
of the Disk Controller board block diagram (Figure 12-33).
4170 INSTRUCTION
12-129
SECTION 12
THEORY OF OPERATION
Address Counters. 'l'he Address Counters (Schematic A3-3)
transforms DMA addresses sent by the processor from 16-bit data
bus format into 20-bit address bus format.
Figure 12-43 shows how the DMA address is first loaded into a set
of-counters. A 16-bit byte fills all but the top counter, so the
next address byte only contains four bits and it is loaded into
the top counter. The Address Decoder circuitry selectively
enables these counters to achieve this.
12-1 30
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
COUNTER
ADDRESS ...--_ _ _--'S;.;;;:E=LE;;;..;C;..;,T_ _____
~
DECODE
C~_~~,..--i~---,R
IDS-IllL...-
->
--!o!-I
J..--I
+
1----:---->
100-15
3-STATE
ADDRESS
BUFFER
COUNTER ~----->
a-BIT
.
DACK
____---It
INCREMENT
3812-32
Figure 12-43. Address Counters.
'i
I
4170 INSTRUCTION
12-131
SECTION 12
THEORY OF OPERATION
~his 20-bit address is then loaded into the tri-state buffers,
which are read by the 4170 address bus at the time of the next
Dr·1A transfer. The address remains in the counters until the next
DHA cycle, at which time the address is automatically incremented
by the DACK line.
This means that the processor establishes the starting location
in RAM for DNA transfers; then subsequent transfers automRtically
step through adjacent addresses in RAM.
Address Decoder. The Address Decoder (Schematic A3-3)
generates the control sienals that enable other cj. rcui t
functions. The Address Decoder tAkes addresses in the processor
Memory Address Space and converts them into:
o
ACK1 acknowledge to 4170 control bus
o
FDCR to FDC RD and WR inputs
o
FDCW to FDC HD and WR inputs
o
STROBE to Board Status output buffer
o
STATUS LATCH clock to the Board Status input latch
o
ADDRESS COUNTERS selects and enables to the three Address
Counters
o
ABORT to FDC TC (abort) input
o
SSDRQ to DMA request (test only)
Fieure 12-44 shows the functional groupings of this logic. An
address of FCOO (1) passes the NAND circuit and produces its
COMMON ENABLE output. This line is used along with specific
addresses to enable the following function gates.
(1) May be strapped to FC80, but this strap setting is not normally
used.
12-132
4170
INS~RUCTICN
SECTION 12
THEORY OF OPERATION
ADR10-15
MAIN
ADDRESS
DECODE
(NAND)
ADDRESS
~ FC04} NOT USED
C/)
:::)
i
m
~
1
FC05
C/)
C/)
w
a:
0
0
«
........0
'
ADDRESS
'.DECODE
IrD-
DATA
MUX
-,1
..... - .....
II
o 0
11. 0
11.
J1
RO
10
I
~:
FDC
WR
I
R/W
DIRECTION
FOR DI'1A
0
Dt1A/BUS
LISTEN
~
'-
DACI(
A. WRITE TO DISK.
<
0
BOARD
STATUS
0
BW/BR
0:
1:
J>
0
I-
=- ,--«
=- ......
o 0:
1:
-
0
I-
=-
1:
DMA
STATE
MACHINE
)-----------------j
---, r-
4170 BUS
ADDRESS
DECODE
'1° •
.10--
DHA W
R/W
DIRECTION
FORDHA
DATA
MUX
-,1
-- .....
II
o 0
11. 0
11.
.11
I
DHA R
~
RO
0
I
~:
WR
FDC
I
0
OI'1A/BUS
LISTEN
~
DAo\
B. READ FROM DISK.
(3812)4685-61
Figure 12-48. Control Strobes Equivalent Circuit.
4170 INSTRUCTION
12-143
SECTION 12
THEORY OF OPERATION
For a read from the disk, the DMA/Bus Listen switch remains in
the DMA position, but the other switch is toggled so it connects
the DMA READ line to the FDC RD input. The DMA Write part of the
swi tch is connected to the MvlTC (Memory Wr i te Command) Ii ne on
the 4170 bus (Figure 12-48B). This allows the FDC to read from
the disk and to write the data into the DMA area of system RAM.
The BW/BR line controls the DMA Read and Write Direction
switches, and the DACK line controls the DMA/Bus Listen switches.
NOTE
The gates that make the DMA READ and DMA
WHITE lines from DMA State Machine
uts
are shown as a part of
ROM (Not Used)
The several blocks of circuitry which together comprise the ROM
block (Schematic A3-1) are pictured in Figure 12-49.
12-144
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
ROMS
AI?J-A3
r-------~~~--------~
r--r--r--r---
TO MAIN
ADDRESS
DECODER
2
1
121
3
HIGH
A1-A11 )
/ A12 r
L-L~W-~
1
ROM
ADDRESS
r BUFFER
ADRI?J-14 )
r--
--
t-f--
r-
--
.
ROM
- - ~.i51
DATA
1?J-7
r" BUFFER
t--
DATI?JDAT15
A1-A 11 )
\
MRDC
A12
(CHIP ENABLE)
'\.
r--
-- -
ADR13-14
y,J
.... :-- ....
~
L.....:--
2-TO-4
MRDC ~ DECODER Y'3
READ NDT,t
INHIBITED
~
-
ACt<. 112
•
~DR15-19)
r
~
"-
ADDRESS
COMPARATOR
BOARD
ADDRESS
STRAPS
3812-38
Figure 12-49. ROM Circuitry.
4170 INSTRUCTION
12-145
SECTION 12
THEORY OF OPERATION
This section of circuitry can contain ROMs with
for FDC operations. This firmware is located in
Address Space between E8000 and EFFFF. The ROMs
via the 4170 address bus (ADRO - ADR19) and the
Command) control line.
32K of firmware
processor Memory
are accessible
MRDC (Memory Read
OPTION 45 MSIB CONTROLLER
The Option 45 Mass Storage Interface board (MSIB) is an interface
that connects the 4170 to an internal Winchester hard disk unit
or external mass storage devices on the mass storage interface
bus.
Option 45 includes:
o
Option 45 circuit board assembly
o
44-pin auxiliary edge connector and cable with MSIB
connector
The MSIB board plugs into the 4170 main bus. For further
information, refer to the 4110B Series Disk Options Service
Manual.
12-146
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
HARD DISK CONTROLLER
The Hard Disk Controller contains the following functional
blocks:
o
Host Interface. The Host Interface connects the Hard
Disk Controller internal data bus to the MSIB. The movement
of data through the Host Interface is controlled by the
State Machine.
o
Processor. All functions within the Hard Disk Controller
are under the general control of an 8-bit microprocessor.
o
State Machine. The State Machine synchronizes the
operation of the Host Interface, the
Serializer/Deserializer, and the Sector Buffer.
o
Serializer/Deserializer. The Serializer/Deserializer
converts parallel data coming over the internal data bus to
a NRZ (Non-Return to Zero) serial data stream suitable for
the Data Separator. It converts serial data coming from the
Data Separator to parallel format for transfer over the
internal data bus.
o
Data Separator. The Data Separator converts the serial
NRZ data stream coming from the Serializer/Deserializer to
serial MFM (fI
resistor per set. The values of the resistors determine the
discharge time of the capacitor after the power is turned off.
Main Power Converter
This circuit as shown in Figure 12-57 will oscillate due to the
180 phase shift of the transformer primary and the base
drive winding. An RC (resistor/capacitor) network (470 K and
100 F (approximate)) in the base circuit of the main
switching transistor, is outlined by a dotted line in Figure
12-57. This RC network is required to initiate oscillation.
\
I
4170 INSTRUCTION
12-161
SECTION 12
THEORY OF OPERATION
Figure 12-57. Main Power Converter (elementary form).
12-162
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
Once the supply is running, the RC network could be removed with
no effect on the oscillation. As shown, the converter would
operate with no regulating control.
A gating transistor (base drive transistor) is now added to
control the on time of the main switching device. An
appropriatelY-timed pulse applied to the base of the gating
transistor limits the conduction interval of the main transistor.
This regulates the amount of energy stored in the transformer,
hence the output power, on a cycle by cycle basis.
These pulses are generated using a unijunction transistor.
4170 INSTRUCTION
12-163
SEc':::rON 12
THEORY OF OPERATION
Figure 12-58. Pulse Generator.
12-164
4170
INSTRUC~IOh
SECTION 12
THEORY OF OPERATION
The base drive winding voltage, swinging positive, turns on the
main switching transistor. Coincidentally, the unijunction RC,
(shaded in Figure 12-58) begins charging toward the unijunction
trigger point. When the trigger voltage is exceeded, the
unijunction fires. This injects a pulse into the base of the
gating transistor. The base of the main switching transistor is
then pulled to ground, thus terminating its conduction time.
A potentiometer in the base of the unijunction trims the
unijunction RC time constant. This allows setting of the maximum
allowable on time, hence the maximum available power. Two zener
diodes, a resistor, and a potentiometer, all in series with the
dc supply and the base of the unijunction, form a network which
"measures" the primary input dc supply. A current proportional to
the raw dc is injected into the timing capacitor at the base of
the unijunction. This effectively reduces the transistor on
time as the line voltage increases. The net effect is constant
output power for all line voltages.
Abruptly terminating the current flow in the main transistor
initiates the energy transfer interval. Current continues to flow
in the transformer primary and the collector voltage of the main
transistor begins to rise. This voltage rise will also appear
across the secondary windings. The output diodes begin to conduct
and the energy stored in the transformer core is transferred into
the output capacitors.
Snubber
This energy transfer cannot occur instantaneously. This is due
largely to less than perfect coupling in the transformer. The
snubber network, an RC network contained in the collector circuit
of the main switching transistor, forms an interim path for the
primary current to flow. This network also limits the rate of
rise at the collector so that the current in the main switching
transistor is zero before the collector voltage begins to rise.
Control Loop Sense and Drive
The output structures are diode capacitor networks. A pi filter
follows this on each output.
The error signal feedback is accomplished across an opto-coupler.
Current flow in the secondary opto-diode is reflected in the
primary side optical transistor. This optical transistor sources
current in the timing capacitor (of the unijunction RC network).
This again controls the main switching transistor on time and
closes the regulating loop.
4170 INSTRUCTION
12-165
SECTION 12
THEORY OF OPERATION
Figure 12-59. Control Loop, Sense and Drive.
12-166
4170 INSTRUCTION
SECTION 12
THEORY OF OPERATION
The error amplifier itself is a differential pair with a voltage
follower output (as shown next).
The 12 and 5-volt output voltages are compared to a. fixed, minus
12-volt reference. The minus 12-volt regulator verifies the
accuracy. The differential pair amplifiers vary the current in the
opto-diodes, balancing the differential amplifiers and ensuring
accuracy of the 12-volt and 5-volt supplies.
This minus 12-volt reference is also the minus 12-volt output (in
addition to being the bias source for the differential amplifier).
4170 INSTRUCTION
12-167
Section 13
CHECKS AND ADJUSTMENTS
THE ADJUSTMENTS CONTAINED HEREIN ARE MEANT FOR QUALIFIED
TECHNICIANS ONLY. If no qualified technicians are available,
consult your local TEKTRONIX service center.
This section contains functional check, performance check, and
adjustment procedures for the 4170. The flexible-disk drive-units
are the only assemblies in the 4170 that have adjustment points
that can be changed in the field.
FUNCTIONAL CHECK PROCEDURE
The functional check procedure verifies that all major parts of
the 4170 function as defined in the operating procedures in this
manual. This functional check procedure is typically used to test
the 4170 after repair, or for initial acceptance testing by the
customer.
The adjustment procedures, later in this section, provide a means
for setting the 4170's performance in accordance with the
specifications in Section 2. Since the performance check
procedure is more time consuming, the functional check procedure
is often used to determine if the 4170 is operational.
The functional check procedure consists of two parts. The first
part is the power-up routine that runs each time the 4170 is
turned on. ~his routine does a cursory check of the major modules
and functions of the 4170. The second part of the functional
checks is the Self-test diagnostic program. If, after Self-test
is invoked, it runs to completion without stopping to display any
error codes, this means the 4170 has passed the full functional
check procedure. If Self-test stops and displays an error
message, observe that message and look it up in Section 8. This
will indicate where the fault is located. Near the end of
Self-test, you can cause it to go into Adjustment Self-test; skip
over this, as it is only used during the Performance Check and
the adjustment/calibration procedures. Upon completion of
Self-test (without errors), you will have verified that your 4170
functions properly.
4170 INTRODUCTION
13-1
SECTION 13
CHECKS AND ADJUSTMENTS
PERFORMANCE CHECK PROCEDURE
The performance check procedure verifies that the 4170 performs
according to the specifications in Section 2. Use the functional
check procedures, earlier in this section, to first determine the
overall functionality of the unit. Then, use the Performance
Check procedures to set the performance levels of the various
modules in the 4170. This procedure also uses the internal
Self-test diagnostic program, but it uses the adjustment
routines, as well as the diagnostics.
13-2
4170 INTRODUCTION
SECTION 13
CHECKS AND ADJUSTMENTS
PROCEDURE
1. Remove the 4170 side cover panel.
2. Check the 3PPI and the host ports at the I/O connectors
a. Attach the loopback connector
b. Enter Self-test
c. Perform the 3PPI and Host Port tests of Adjustment
Self-test program
FLEXIBLE DISK DRIVE ADJUSTMENTS
Introduotion
The following adjustment procedures apply only to the flexible
disk drives. To initiate these procedures, enter the Adjustment
Self-test program and select the disk menu. When this is done,
certain front-panel keys are programmed to exercise the drive
units. Table 13-1 gives the function for each key when programmed
for disk calibration.
,
\
J
4170 INTRODUCTION
13-3
SECTION 13
CHECKS AND ADJUSTMENTS
Table 13-1
FUNCTION KEY DEFINITIONS
I Key Name
I Function/Key-Definition
I F1
I
: F2
: Step up One Track
: F3
: Step Down One Track
: F4
: Seek Track 0
: F5
: Seek Track 1
: F6
: Seek Middle of Disk
: F7
: Select Head
I F8
: Seek Last Track
: 2nd F1
: Run Notor
I 2nd F2
I Read Current Track
~SIB
-- ID Verification Test
----------------~------------------------------------~ ------
: 2nd F3
: Arm Write Mode
I 2nd F4
: Writes Current Track With a 2F Pattern:
I 2nd F5
: Select Your Own Track
: 2nd F6
I Change Device Address
I 2nd F7
: Auto Load/Unload Head on Current Track:
: 2nd F8
I MSIB -- External Peripheral Test
13-4
4170 INTRODUCTION
SECTION 13
CHECKS AND ADJUSTIVlENTS
Tools and Equipment Required
The following tools/equipment are needed for servicing and
adjusting the flexible disk drives:
o
Formatted scratch diskette (in good condition).
o
Calibration/alignment diskette.
o
Oscilloscope have "External
with ADD).
o
Frequency counter '1.3261
: <0.3150
: 15' Set:
>1.2253
: <0.2405
: 18' Set:
>1.1159
: <0. 1689
Table 13-4
+21 MINUTES
: Set
: Ratio-(Burst #1/Burst#2) : Ratio-(Burst #4/Burst #3) :
: 12' Set:
<0.3150
: > 1 .3261
: 15 ' Set : <0.2405
: >1.2253
: 18' Set:
: >1.1159
<0.1689
6. Repeat for the other head.
7. If either head produces a waveform that is not within the
range shown, replace the disk drive unit.
13-14
4170 INTRODUCTION
SECTION 13
CHECKS AND ADJUSTMENTS
Head Amplitude Check.
Make certain that the scratch diskette used for this check is not
"worn" or otherwise shows evidence of damage on either side.
1. Install the scratch diskette.
2. Press function keys 2nd and F1 to start the drive unit
moto r .
3. Press function key F8 to seek the last track.
4. Set up the oscilloscope as follows:
a. Sync to TP-7 (+INDEX), EXT
b. Connect one probe to ~P-1 and the other to TP-2.
(Connect both probe grounds to TP-5).
c. Set the vertical deflection to 100 nV/div.
d. Set the time base to 20 ms/div.
e. Set the inputs to ADD, and invert one channel.
5. Press function key F7 to select Head O. Press keys 2nd and
F3 to arm the write mode. Press keys 2nd and F4 to write a
2F pattern on the track.
6. Read back the head amplitude. The average minimum
peak-to-peak amplitude should be 100 mV.
7. Repeat Steps 5 and 6 for Head 1.
8. If either head fails to meet the amplitude specification,
continue with Step 9. If both heads meet the specification,
proceed to the Track 0 Detector Assembly Adjustment in this
section.
9.
Insta~l
a different diskette and recheck.
10. Check the motor speed. (Refer to the Motor Speed Adjustment
in this section.)
4170 INTRODUCTION
13-1 5
SECTION 13
CHECKS AND ADJUSTMENTS
11. With the oscilloscope in CHOP mode, verify that an output
exists at both TP-1 and TP-2. If one test point has no
output (or significantly less output than the other), turn
the head cable connector over at J4. If the same test point
has little or no signal, repair the circuit board or replace
the disk drive unit. If the opposite test point shows the
problem, the head assembly is faulty and the disk drive unit
must be replaced.
Track Zero Detector Assembly Adjustment.
1. Install the alignment diskette.
2. Select drive and press function key F4 to seek Track O.
3. Set up the oscilloscope as follows:
a. Sync to TP-7, EXT, +.
b. Set the time base to 20 msec/div.
c. Connect one probe to TP-1 and the other to TP-2.
(Connect both probe grounds to TP-5.)
d. Set the vertical deflection to 200 mV/div.
e. Set the inputs to AC, ADD, and invert one channel.
4. A 125 kHz signal should be observed on the scope at this
time. (If the signal is not present, press function key F2 a
maximum of five times or press F3 as many times as necessary
until the signal is located.) When the 125 kHz signal is
present on the oscilloscope, the drive carriage is at Track
O.
5. Disconnect one scope probe and connect to TP-S -- Set input
to DC, vertical deflection to 2 V/div, and trigger from the
channel being used.
6. Press function key F5 to seek Track 1 and verify that TP-S
goes to 0 V.
7. If TP-S does not go to 0 V, loosen the Track 0 Detector
bracket (Figure 13-5). Adjust until TP-S goes to 0 V when
function key F5 is pressed and goes to +5 V when F4 is
pressed.
S. Tighten the Track 0 Detector bracket and recheck.
13-16
4170 INTRODUCTION
SECTION 13
CHECKS AND ADJUSTMENTS
Figure 1'-5. Track 0 Detector Bracket Mounting.
'\
/
4170 INTRODUCTION
13-17
SECTION 13
CHECKS AND ADJUSTfJIENTS
Index/Sector Timing Adjustment.
1. Insert the alignment oiskette.
2. Press function key F7 to select Head O.
3. Press F5 to seek Track 1.
4. Set up oscilloscope as follows:
a. Sync to TP-7, EXT, +.
b. Set time base to 50 sec!div.
c. Connect one probe to TP-1 and the other to TP-2.
(Connect both probe grounds to TP-5.)
d. Set the vertical deflection to 100 mV/div.
e. Set the inputs to AC, ADD, and invert one channel.
5. Verify that the timing between the start of the sweep and
the first data pulse is 200 (+200/-100) sec (Figure
13-6). If the timing is not within this specification,
proceed with Step 6. If the timing is within specification,
proceed to the Write-Protect Switch Adjustment in this
section.
6. Loosen the mounting screw in the index detector block until
the block can just be moved (Figure 13-7).
7. Adjust the index detector block until the specification is
met. Make certain that the detector assembly is against the
registration surface on the hub frame.
8. Tighten the mounting screw.
9. Recheck the timing.
10. Press function key F7 to select Head 1 and press F5 to seek
Track 1. Repeat the procedure for Head 1.
13-18
4170 INTRODUCTION
SECTION 13
CHECKS AND ADJUSTMENTS
Figure 13-6. Index Timing.
4170 INTRODUCTION
13-19
SECTION 13
CHECKS AND ADJUSTMENTS
Figure 1'-7. Index Detector Mounting.
13-20 .
4170 INTRODUCTION
SECTION 13
CHECKS AND ADJUSTMENTS
Motor Speed Adjustment.
NOTE
It is recommended that this adjustment not be
performed in the field.
1. Install a blank diskette in the drive unit.
2. Press function key F5 to seek Track 1.
3. Connect the frequency counter to TP-7.
4. Adjust the potentiometer on the motor circuit board to
obtain a reading of 5 +/- 0.05 Hz (Period 200 +/- 2 IDS).
Write-Protect Switch.
The write-protect switch can be
checked for proper operation by monitoring the voltage on TP-9
while inserting/removing a diskette that has the write-protect
notch open. The voltage on ~P-9 should go from 0 to 5 V as the
diskette is inserted/removed.
4170 INTRODUCTION
13-21
Section 14
MAIWTENANCE
This section
reQuired for
This section
the flexible
contains the disassembly and reassembly procedures
troubleshooting, adjustment, and repair of the 4170.
also contains preventive maintenance procedures for
disk drive units.
SAFETY SUMMARY
The operator section of this manual contains general safety
warnings. Many such warnings are obvious to the trained
technician or do not apply here (such as warnings against
removing doors and access panels). The following are general
service warnings that should be observed while working on this
instrument.
DO NOT SERVICE ALONE
Do NOT perform internal service or adjustment of this product
unless another person capable of rendering first aid and
resuscitation is present.
USE CARE WHEN SERVICING WITH POWER ON
Disconnect power before removing circuit boards, soldering, or
replacing components.
Exercise care so that tools and probes do not complete a
connection other than that intended. All jewelry that might
interfere or complete a circuit should be removed to prevent
injury.
No hazardous voltages are exposed within the 4170 cabinet.
voltages present are +5, +12 and -12.
The
POWER SOURCE
The 4170 draws power from a line voltage source and brings AC
voltages into the power supply and fan. Be sure the product is
grounded properly via a ground conductor in the power cord or an
insulated ground cable.
4170 INSTRUCTION
14-1
SECTION 14
MAINTENANCE
PREVENTIVE MAINTENANCE
The 4110 is designed to require a minimum of maintenance and
servicing. Once a year you should remove the side panel and look
for and correct the following:
o
Remove any dust accumulations
o
Loose screws, connectors, and switches
o
Inspect the flexible djsk drive heads for dirt deposits and
clean if necessary (the optional Hard disk drive unit
is a sealed module; therefore, its design does not allow
field maintenance)
o
Calibrate flexible disk drives (see checks and adjustment
section)
o
Excessive play in the fan motor shaft
~
Do not attempt to oil any of the motors in the
disk drive units. These motors have sealed bearings
and therefore do not require lubrication. Any oil
added will only catch dust and create a greater wear
problem.
PREVENTIVE MAINTENANCE PROCEDURES
DISK UNIT READ/WRITE HEAD CLEANING
The read/write head should be cleaned after each 12 months of
normal use. Use a cleaning disk to clean the disk unit
read/write head.
14-2 .
4110 INSTRUCTION
SECTION 14
MAINTENANCE
DISASSEMBLY/REASSEMBLY PROCEDURES
REMOVING THE FRONT COVER
The card cage is accessible via a cover on the front of the 4170.
This cover is attached by two screws (one in each bottom corner)
and a lip (that secures the top of the cover). First, unscrew the
two thumbscrews. Then, swing the cover out at the bottom. Finally,
allow the cover panel to drop free, releasing the retainer tab at
the top. See Figure 14-1.
4170 INSTRUCTION
14-3
SECTION 14
MAINTENANCE
F18ure 14-1. Removing the Front Cover.
14-4
4170 INSTRUCTION
SECTION 14
MAINTENANCE
REMOVING CIRCUIT BOARDS FROM THE CARD CAGE
Figure 14-2 shows the recommended arrangement of circuit boards
in the card cage. Use this diagram to determine the location of
the board(s) needing removal.
o
Remove the Front Cover (described earlier).
o
Determine which cables and wires (connecting to the front of
the circuit boards) need to be unplugged. Then, label these
cables, so you can easily reconnect them to their proper
connectors. Unplug the cables.
0
Read the name/label on the circuit board to be sure you are
removing the intended board.
0
Grasp the upper and lower ejectors as shown in Figure
14-3. Pull the ejectors out toward you.
0
Pull the board straight out of the slot.
Before reinserting any circuit boards, verify that you are
placing it in the proper slot according to Figure 14-2.
4170 INSTRUCTION
14-5
SECTION 14
MAINTENANCE
Figure 14-2. 4170 Circuit Board Locations.
14-6
4170 INSTRUCTION
SECTION 14
MAINTENANCE
Figure 14-'. Removing Card Cage Circuit Boards.
'\,
;
4170 INSTRUCTION
14-7
SECTION 14
MAINTENANCE
REMOVING THE SIDE COVER
The major modules in the 4170 (flexible drive units, power
supply, hard disk unit, control panel board, and fan) are
accessible via the side cover. To remove this cover,
refer to Figure 14-4 and do this procedure:
o
Remove the front cover (described earlier).
o
Place the 4170 on its left side.
o
Unscrew the two screws at the right edge of the front access
opening.
o
Unscrew the two
rear panel.
o
Lift the side cover away from the instrument (the
panel wraps over the top of the 4170).
14-8
screws from the left edge of the
4170 INSTRUCTION
SECTION 14
HAINTENANCE
Figure 14-4. Side Cover Removal.
4170 INSTRUCTION
14-9
SECTION 14
MAINTENANCE
REMOVING THE FLEXIBLE-DISK DRIVE UNIT(S)
The two flexible-disk drive units mount together on two common
brackets that are fastened to the side of the 4170. The common
brackets are L-shaped. One is located on the top of the two
drives and the other is located beneath the drives. Each common
brackets is attached to the side panel with two screws. To
remove the flexible-disk drives do the following:
a
Remove the side cover (earlier procedure).
o
Unplug the cables that go plug into the drive units.
o
Loosen (do not remove) the four screws that secure
the L-shaped brackets to the side panel.
a
Slide the drive-units assembly (both drives and the two
L-shaped brackets) to the rear until the screw heads are
free.
o
Lift the assembly away from the side panel.
DISASSEMBLING THE FLEXIBLE-DISK DRIVE ASSEMBLY
Since the two flexible-disk drive units are fastened together in a
common mounting bracket, it is necessary to fi,rst separate them for
most disk-unit repairs.
o
Remove the drive-units assembly from the 4170.
o
Remove the screws that mount the top and bottom L-brackets
to the drive units. This separates the two drive units.
14-10
4170 INSTRUCTION
SECTION 14
j\1A INTENANC E
REMOVING THE POWER SUPPLY MODULE
The Power Supply Module is secured to the side panel with four
screws. Remove the power supply by doing the following
procedure:
0
Remove the side cover (described earlier) •
0
Unplug P 11 from the mother board.
0
Unplug fan connector J62 from the power supply.
0
Loosen (do not remove) the four screws that fasten the power
supply to the 4170 side-panel.
o
Slide the power supply forward in the key slots.
o
As the screw heads reach the open end of the slot, lift
the power supply away from the 4170.
o
The dc power cable can then be easily unplugged from the
power supply jack, J61.
Reverse procedure for reassembly.
4170 INSTRUCTION
14-11
SECTION 14
MAINTENANCE
REMOVING THE OPTIONAL HARD-DISK MODULE
The optional hard disk drive module consists of the drive
unit (in a chassis-type enclosure), an interface board mounted on
the outside of the chassis, the MSI Bus ribbon cable, and power
cables. Refer to Figure 14-5 and perform the following procedure
to remove the optional hard-disk module:
o
Remove the side-cover.
o
Unplug the MSI Bus ribbon cables from
o
Unplug the dc power cable (P9) from the mother board and
plug P2 from the hard-disk drive.
o
Loosen (do not remove) the four screws that mount the drive
module to the side of the 4170.
o
Slide the disk module forward in the screw slots, then lift
out of the 4170.
o
Remove the interface board as needed: disconnect the
I/F board-to-drive unit cables, and unscrew the I/F board
mounting screws.
o
The hard disk unit is not a field-repairable item. This
manual does not include any preventive maintenance or repair
procedures for that unit. See TEKTRONIX manual 119-1644-00 Hard
Disk Service Manual.
14-12
the interfaee board.
4170 INSTRUCTION
SECTION 14
MAINTENANCE
CARD CAGE
Figure 14-5. Removing Hard-Disk Module.
'1
/
4170 INSTRUCTION
14-13
SECTION 14
MAINTENANCE
REMOVING THE CONTROL PANEL AND PANEL DOOR
The Control Panel contains several switches and two 7-segment
displays. During normal operation the two displays are the only
items visible to the operator; the switches and other components
are hidden by a pop-off door. Figure 14-6 shows how to remove
the pop-off door.
To remove the Control Panel circuit board, refer to Figure 14-7
and perform the following procedure:
o
Remove the side cover; this provides access to the
back side of the circuit board.
o
Label and unplug the wires that connect to the Control Panel
circuit board.
o
Unscrew the four small screws that secure the board to the
front panel.
o
Remove board.
14-14
4170 INSTRUCTION
SECTION 14
HAINTENANCE
Figure 14-6. Removing the Pop-Off Control Panel Door.
4170 INSTRUCTION
14-1 5
SECTION 14
MAINTENANCE
FLEXIBLE DISK
DRIVES
F11ure 14-7. Removing Control Panel Cirouit Board.
14-16
4170 INSTRUCTION
SECTION 14
!'vIA INTENANC E
ACCESSING/REMOVING REAR-MOUNTED COMPONENTS
The 4170 rear-panel contains several types of connectors and the
cooling fan. To replace any of these components, first remove the
side cover. The connectors are mounted with screws from the
outside, that thread into inserts in the connector panels. Label
all connected cables that must be removed to replace these.
connectors.
To replace the cooling fan, first unplug its power cable, then,
using a screwdriver and nut driver, unscrew the four mounting
screws.
TROUBLESHOOTING AND CORRECTIVE MAINTENANCE
USING SELF TEST
The primary troubleshooting aid for this product is the Self Test
diagnostic program that resides in firmware (or is loaded from
the disk/diskette at power-up). Section 8 provides a complete
description of all Self Test error messages and the module
testing sequence.
INITIAL/VISUAL CHECKS
Self-Test will isolate most system problems; however, if it does
not, go through the following procedures: A series of
initial/visual checks may help isolate a problem to the
module-level. First, try to determine whether the problem is
hardware or software related. Does the disk work OK? If one disk
is malfunctioning, try the other drive-unit; if the problem
persists, the cause is either a bad diskette or a fault in the
Disk Controller board. Some disk related problems are random and
recoverable; such are called "soft-errors." Other disk problems
persist after several tries, and are called "hard errors." Hard
errors do not necessarily imply a hardware problem; it may mean
the disk media is faulty. If the system is not host-connected and
fails to boot properly, try a backup version of the boot
diskette.
\
/
4170 INSTRUCTION
14-17
Section 15
REPLACEABLE
ELECTRICAL PARTS
PARTS ORDERING INFORMATION
Replacement parts are available from or through your local
Tektronix, Inc Field Office or representative
Changes to Tektronix instruments are sometimes made to
accommodate improved components as they become available,
and to give you the benefit of the latest circuit improvements
developed in our engineering department. It is therefore important, when ordering parts, to include the following information in
your order Part number, instrument type or number, serial
number, and modification number if applicable
If a part you have ordered has been replaced with a new or
improved part. your local Tektronix, Inc. Field Office or representative will contact you concerning any change In part number
Only the circuit number will appear on the diagrams and
circuit board illustrations. Each diagram and circuit board
Illustration is clearly marked with the assembly number
Assembly numbers are also marked on the mechanical exploded
views located in the Mechanical Parts List. The component
number is obtained by adding the assembly number prefix to the
circuit number
The Electrical Parts List IS divided and arranged by
assemblies in numerical sequence (e.g .. assembly A1 with its
subassemblies and parts, precedes assembly A2 with its subassemblies and parts)
Chassis-mounted parts have no assembly number prefix
and are located at the end of the Electrical Parts List
Change informallon, If any, IS located at the rear of this
manual
LIST OF ASSEMBLIES
A list of assemblies can be found at the beginning of the
Electrical Parts List. The assemblies are listed in numerical order
When the complete component number of a part is known, this list
will identify the assembly in which the part IS located.
CROSS INDEX-MFR. CODE NUMBER TO
MANUFACTURER
The Mfr Code Number to Manufacturer index for the
Electrical Parts List IS located immediately after this page. The
Cross Index provides codes, names and addresses of manufacturers of components listed in the Electrical Parts List.
TEKTRONIX PART NO. (column two of the
Electrical Parts List)
Indicates part number to be used when ordering replacement part from Tektronix
SERIAL/MODEL NO. (columns three and four
of the Electrical Parts List)
Column three (3) indicates the serial number at which the
part was first used. Column four (4) indicatestheserial numberat
which the part was removed. No serial number entered indicates
part is good for all serial numbers
ABBREVIATIONS
AbbreViations conform to American National Standard Y1 1.
COMPONENT NUMBER (column one of the
Electrical Parts List)
A numbering method has been used to Identify assemblies,
subassemblies and parts Examples of this numbering method
and typical expansions are illustrated by the following:
Example a.
NAME & DESCRIPTION (column five of the
Electrical Parts List)
In the Parts List, an Item Name is separated from the
description by a colon (). Because of space limitations, an Item
Name may sometimes appear as incomplete For further Item
Name identification, the U.S. Federal Cataloging Handbook H6-1
can be utilized where possible
component number
~
A23R1234
Assembly number
A23
R1234
~ ~
Circuit number
I ndicates the code number of the actual manufacturer of the
part. (Code to name and address cross reference can be found
immediately after this page.)
Read: Resistor 1234 of Assembly 23
Example b,
A23A2R 1234
,
component number
A23
ASSembIY~
number
A2
R 1234
Subassembly
number
Circuit
number
Read: Resistor 1234 of Subassembfy 2 of Assembly 23
4170 INSTRUCTION
MFR. CODE (column six of the Electrical Parts
List)
MFR. PART NUMBER (column seven of the
Electrical Parts List)
Indicates actual manufacturers part number.
15-1
REPLACEABLE ELECTRICAL PARTS
CROSS INDEX-MFA. CODE NUMBER TO MANUFACTURER
Mfr. Code
Manufacturer
Address
City, State, Zip
OOOHX
SAN-O INDUSTRIAL CORP
170 WILBUR PLACE
OOOIZ
OOOJB
00779
00853
01121
01295
DALE ELECTRONICS CORP.
STAR MICRONICS INC.
AMP. INC.
SANGAMO ELECTRIC CO .. S. CAROLINA DIV.
ALLEN-BRADLEY COMPANY
TEXAS INSTRUMENTS. INC.
SEMICONDUCTOR GROUP
PETERSEN RADIO COMPANY, INC.
GENERAL ELECTRIC COMPANY, SEMI-CONDUCTOR
PRODUCTS DEPARTMENT
AVX CERAMICS. DIVISION OF AVX CORP.
MOTOROLA. INC. SEMICONDUCTOR PROD DIV.
UNION CARBIDE CORPORATION. MATERIALS
SYSTEMS DIVISION
VIKING INDUSTRIES, INC.
FAIRCHILD SEMICONDUCTOR. A DIV. OF
FAIRCHILD CAMERA AND INSTRUMENT CORP.
AMPHENOL CARDRE DIV, BUNKER RAMO CORP.
ITT SEMICONDUCTORS
PO. BOX 3164
200 PARK AVE SUITE 08
P.O. BOX 3608
P.O. BOX 128
1201 2ND STREET SOUTH
BAHEMIA
LONG ISLAND, NY 11716
TEMPE, AZ 85282
NEW YORK, NY 10166
HARRISBURG, PA 17105
PICKENS, SC 29671
MILWAUKEE, WI 53204
P.O. BOX 5012
2800 WEST BROADWAY
DALLAS, TX 75222
COUNCIL BLUFFS, IN 51501
ELECTRONICS PARK
POBOX 867
5005 E MCDOWELL RD,PO BOX 20923
SYRACUSE, NY 13201
MYRTLE BEACH, SC 29577
PHOENIX, AZ 85036
11901 MADISON AVENUE
21001 NORDHOFF STREET
CLEVELAND, OH 44101
CHATSWORTH, CA 91311
464 ELLIS STREET
MOUNTAIN VIEW, CA 94042
LOS GATOS, CA 95030
01807
03508
04222
04713
05397
05574
07263
13511
14433
14752
15238
72982
73138
75915
80009
82389
82877
91637
96733
T1015
ELECTRO CUBE INC.
ITT SEMICONDUCTORS, A DIVISION OF INTER
NATIONAL TELEPHONE AND TELEGRAPH CORP.
SIGNETICS CORP.
BERG ELECTRONICS, INC.
NATIONAL SEMICONDUCTOR CORP.
MOLEX PRODUCTS CO.
BOURNS, INC., TRIMPOT PRODUCTS DIV.
ADVANCED MICRO DEVICES
INTEL CORP.
HEWLETT-PACKARD COMPANY
CENTRE ENGINEERING INC.
MATSUSHITA ELECTRIC, CORP. OF AMERICA
NICHICON/AMERICA/CORP.
GOULD INC. PORTABLE BATTERY DIV.
SPRAGUE ELECTRIC CO.
R-OHM CORP.
TUSONIX INC.
CENTRALABINC
SUB NORTH AMERICAN PHILIPS CORP
BELDEN CORP.
BUSSMAN MFG. DIVISION OF MCGRAWEDISON CO.
ERIE TECHNOLOGICAL PRODUCTS, INC.
BECKMAN INSTRUMENTS, INC .. HEll POT DIV.
LlTTELFUSE. INC.
TEKTRONIX. INC.
SWITCHCRAFT, INC.
ROTRON. INC.
DALE ELECTRONICS, INC.
SAN FERNANDO ELECTRIC MFG CO
MUSASHI WORKS OF HITACHI LTD
T1043
DALE ELECTRONICS CORP
18324
22526
27014
27264
32997
34335
34649
50434
51642
54473
55680
55857
56289
57668
59660
59821
70903
71400
15·2
3301 ELECTRONICS WAY
POBOX 3049
1710 S. DEL MAR AVE.
WEST PALM BEACH, FL 33402
SAN GABRIEL, CA 91776
P.O. BOX 168, 500 BROADWAY
811 E. ARQUES
YOUK EXPRESSWAY
2900 SEMICONDUCTOR DR.
5224 KATRINE AVE.
1200 COLUMBIA AVE.
901 THOMPSON Pl.
3065 BOWERS AVE.
640 PAGE MILL ROAD
2820 E COLLEGE AVENUE
1 PANASONIC WAY
6435 N PROESEL AVENUE
2777 EAGAN DALE BLVD
87 MARSHALL ST.
16931 MILLIKEN AVE.
2155 N FORBES BLVD
7158 MERCHANT AVE
LAWRENCE, MA 01841
SUNNYVALE, CA 94086
NEW CUMBERLAND; PA 17070
SANTA CLARA, CA 95051
DOWNERS GROVE, IL 60515
RIVERSIDE, CA 92507
SUNNYVALE, CA 94086
SANTA CLARA, CA 95051
PALO ALTO, CA 94304
STATE COLLEGE, PA 16801
SECAUCUS, NJ 07094
CHICAGO, IL 60645
EAGAN, MN 55121
NORTH ADAMS, MA 01247
IRVINE, CA 92713
TUCSON, AZ 85705
EL PASO, TX 79915
2000 S BATAVIA AVENUE
GENEVA. IL 60134
2536 W. UNIVERSITY ST.
644 W. 12TH ST.
2500 HARBOR BLVD.
800 E. NORTHWEST HWY
POBOX 500
5555 N. ELSTON AVE.
7-9 HASBROUCK LANE
P. O. BOX 609
1501 FIRST ST
1450 JOSUIHON-CHO
ST. LOUIS, MO 63107
ERIE, PA 16512
FULLERTON, CA 92634
DES PLAINES, IL 60016
BEAVERTON, OR 97077
CHICAGO, IL 60630
WOODSTOCK, NY 12498
COLUMBUS, NE 68601
SAN FERNANDO, CA 91341
KODAIRA-SHI
TOKYO. JAPAN
TEMPE. AZ 85282
PO BOX 3164
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
Serial/Model No.
Eft
Dscont
Name & Description
Mfr
Code
Mfr Part Number
CIRCUIT BOARD ASSEMBLIES
A1
A2
A3
A3
670-8119-00
672-1140-00
670-8148-00
CKT BOARD ASSY:MOTHER
CKT BOARD ASSY:PROCESSOR
CKT BOARD ASSY:DISK CONTROLLER
(OPTION 44 ONLY)
80009
80009
80009
670-8119-00
672-1140-00
670-8148-00
A4
670-8120-00
620-0324-00
119-1617-00
CKT BOARD ASSY:FRONT PANEL
CKT BOARD ASSY:POWER SUPPLY
CONTROLLER DISK:
(OPTION 03 ONLY)
CKT BOARD ASSY:INTERFACE
(OPTION 45 ONLY)
80009
80009
80009
670-8120-00
620-0324-00
119161700
80009
672-1163-00
80009
119-1644-00
80009
670-8139-00
80009
670-8138-00
80009
670-8304-00
80009
119-1636-00
80009
670-8392-00
80009
672-1173-00
A5
A6
A6
A7
A7
A8
A8
A9
A9
672-1163-00
011-0090-00
670-5291-XX
119-1644-00
670-8139-00
670-8138-00
670-8304-00
119-1636-00
670-8392-00
672-1173-00
TERMN.LlNE:
(OPTION 45 ONLY)
CKT BOARD ASSY:LOGIC EXTENDER
(NOT AVAILABLE.USE 067-1005-00)
DISK DRIVE:12.76M BYTES
(OPTION 03 ONLY)
(SEE APPROP SERV MANUAL FOR PARTS LIST)
CKT BOARD ASSY:RAM CONTROLLER
(SEE APPROP SERV MANUAL FOR PARTS LIST)
CKT BOARD ASSY:RAM ARRAY
(SEE APPROP SERV MANUAL FOR PARTS LIST)
CKT BOARD ASSY:3PPI
(STANDARD AND OPTION 10 ONLY)
(SEE APPROP SERV MANUAL FOR PARTS LIST)
CKT BOARD ASSY:FLEXIBLE DISK DRIVE
(SEE APPROP SERV MANUAL FOR PARTS LIST)
CKT BOARD ASSY:COLOR COPIER I/F
(OPTION 09 ONLY)
(SEE APPROP SERV MANUAL FOR PARTS LIST)
CKT BOARD ASSY:MASS STORAGE I/O
(OPTION 45 ONLY)
(SEE APPROP SERV MANUAL FOR PARTS LIST)
)
4170 INSTRUCTION
15-3
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
Serial/Model No.
Eft
Dscont
Name & Description
Mfr
Code
Mfr Part Number
80009
56289
04222
04222
670-8119-00
5020237
DG015E473Z
DG015E473Z
OOOHX
OooHX
OOOHX
OOOHX
OOOHX
OOOHX
SPI-5A
SPI-5A
SPI-5A
SPI-5A
SPI-5A
SPI-5A
OOOHX
00779
00779
00779
00779
00779
SPI-5A
3-530671-0
3-530671-0
3-530671-0
3-530671-0
3-530671-0
00779
00779
27264
27264
27264
3-530671-0
3-530671-0
09-61-1106
09-61-10B1
09-61-1045
Al MOTHER
Al
A1C34
A1C41
A1C42
670-8119-00
290-0779-00
283-0422-00
CKT BOARD ASSY:MOTHER
CAP.,FXD,ELCTLT:l0UF,+50-10%,50VDC
CAP.,FXD,CER DI:0.047UF,+80-20%,50V
CAP.,FXD,CER·DI:0.047UF,+80-20%,50V
A1Fll
A1F21
A1F24
A1F31
A1F32
A1F36
159-0059-00
159-0059-00
159-0059-00
159-0059-00
159;'0059-00
159-0059-00
FUSE,WIRE
FUSE, WIRE
FUSE, WIRE
FUSE, WIRE
FUSE.WIRE
FUSE.WIRE
A1F42
A1J1
A1J2
A1J3
A1J4
A1J5
159-0059-00
131-2059-01
131-2059-01
131-2059-01
131-2059-01
131-2059-01
FUSE. WIRE LEAD:5A.FAST-BLOW
CONN,RCPT.ELEC:EDGECARD.2 X
CONN.RCPT,ELEC:EDGECARD.2 X
CONN.RCPT.ELEC:EDGECARD.2 X
CONN.RCPT,ELEC:EDGECARD,2 X
CONN.RCPT.ELEC:EDGECARD.2 X
A1J6
A1J7
A1J8
A1J9
A1Jl0
A1J11
131-2059-01
131-2059-01
131-2528-00
131-2484-00
131-27B9-00
131-3056-00
CONN.RCPT.ELEC:EDGECARD.2 X 40,FEM.0.125
CONN.RCPT.ELEC:EDGECARD,2 X 40.FEM,O.125
TERM SET.PIN:10 MALE CONTACTS. POLARIZED
TERM.SET.PIN:8 PIN.INSULATED
CONN.RCPT,ELEC:HEADER.l X 4.0.156 SPACING
CONN.RCPT,ELEC:HEADER.l X 1B.0.156 SPACING
A1R12
A1R34
A1R35
A1R43
A1R45
A1R111
307-0675-00
315-0272-00
315-02'13-00
315-0201-00
315-0102-00
307-0596-00
RES NTWK.FXD FI:9,1K OHM.2%.1.25W
RES .• FXD.CMPSN:2.7K OHM.5%,O.25W
RES.,FXD.CMPSN:27K OHM.5%.0.25W
. RES.;FXD.CMPSN:2oo OHM.5%,O.25W
RES .• FXD.CMPSN: 1K OHM.5%,O.25W
RES NTWK.FXD FI:7.2.2K OHM.2%,1.0W
01121
01121
01121
01121
01121
91637
210Al02
CB2725
CB2735
CB2015
CB1025
MSPOBA01222G
A1R142
A1R143
A1R145
A1R212
A1R215
A1R241
315-0222-00
315-0222-00
307-0596-00
315-0221-00
307-0675-00
307-0675-00
RES .• FXD.CMPSN:2.2K OHM.5%,O.25W
RES .• FXD.CMPSN:2.2K OHM.5%,O.25W
RES NTWK.FXD FI:7.2.2K OHM.2%.1.0W
RES .• FXO,CMPSN:220 OHM.5%,O.25W
RES NTWK.FXD FI:9.1K OHM.2%,l.25W
RES NTWK.FXD FI:9.1K OHM.2%.1.25W
01121
01121
91637
01121
01121
01121
CB2225
CB2225
MSPOBA01222G
CB2215
210Al02
210Al02
A1R243
A1R245
A1R246
A1R312
A1R342
A1R344
315-0102-00
315-0511-00
315-0511-00
307-0596-00
307-0596-00
307-0596-00
RES .• FXD.CMPSN: 1K OHM.5%.0.25W
RES .• FXD,CMPSN:510 OHM.5%.0.25W
RES.,FXD.CMPSN:510 OHM,5%,O.25W
RES NTWK.FXD FI:7.2.2K OHM.2%,l.0W
RES NTWK.FXD FI:7.2.2K OHM.2%.1.0W
RES NTWK.FXD FI:7,2.2K OHM,2%.1.0W
01121
01121
01121
91637
91637
91637
CB1025
CB5115
CB5115
MSPOBA01222G
MSPOBA01222G
MSP08A01222G
A1U22
A1U25
A1U41
A1U45
156-1252-01
156-0541-02
156-1600-00
156-0094-02
MICROCIRCUIT.DI:B-LlNE-TO-3-LINE PRI ENCDR
MICROCIRCUIT.DI:DUAL 2 TO 4 LINE DCDR
MICROCIRCUIT,DI:DUAL RETRIG MONO MULTIVIB
MICROCIRCUIT.DI:DUAL 2-INP NAND DRVR
01295
01295
01295
01295
SN74LSl48(NP3 OR
SN74LS139NP3
SN74LS123NP3
SN75451(NP3 OR J
15·4
283~0422-00
LEAD:5A,FAST-BLOW
LEAD:5A,FAST-BLOW
LEAD:5A,FAST-BLOW
LEAD:5A,FAST-BLOW
LEAD:5A.FAST-BLOW
LEAD:5A.FAST -BLOW
40.FEM.0.125
40.FEM.0.125
40.FEM.0.125
40.FEM.0.125
40,FEM.0.125
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
Serial/Model No.
Eft
Dscont
Name & Description
Mfr
Code
Mfr Part Number
A2 PROCESSOR
A2
A2BT10
A2C11
A2C31
672-1140-00
146-0040-00
283-0421-00
283-0421-00
CKT BOARD ASSY:PROCESSOR
BATTERY,STORAGE:2.4V,70MAH,AAA CELL
CAP.,FXD,CER DI:0.1UF,+80-20%,50V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
80009
55857
04222
04222
672-1140-00
MS0702405333-002
DG015E104Z
DG015E104Z
A2C75
A2C135
A2C155
A2C170
A2C202
A2C216
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
DI:0.1UF,+80-20%,50V
DI:0.1 UF, + 80-20%,50V
DI:0.1 UF, + 80-20%,50V
DI:0.1 UF, + 80-20%,50V
DI:0.1 UF, + 80-20%,50V
DI:0.1 UF, + 80-20%,50V
04222
04222
04222
04222
04222
04222
DG015El04Z
DG015E104Z
DG015E104Z
DG015E104Z
DG015E104Z
DG015E104Z
A2C231
A2C270
A2C355
A2C360
A2C365
A2C401
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
DI:0.1 UF, +80-20%,50V
DI:0.1UF,+80-20%,50V
DI:0.1 UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
04222
04222
04222
04222
04222
04222
DG015E104Z
DG015E104Z
DG015E104Z
DG015E104Z
DG015E104Z
DG015El04Z
A2C455
A2C501
A2C502
A2C503
A2C504
A2C505
283-0421-00
283-0422-00
283-0422-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
DI:0.1 UF, +80-20%,50V
DI:0.047UF, + 80-20%,50V
DI:0.047UF, + 80-20%,50V
DI:0.1 UF, + 80-20%,50V
DI:0.1UF,+80-20%,50V
DI:0.1 UF, + 80-20%,50V
04222
04222
04222
04222
04222
04222
DG015E104Z
DG015E473Z
DG015E473Z
DG015E104Z
DG015El04Z
DG015E104Z
A2C511
A2C512
A2C513
A2C514
A2C525
A2C526
283-0422-00
283-0422-00
283-0421-00
283-0422-00
283-0421-00
283-0421-00
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
DI:0.047UF,+80-20%,50V
DI:0.047UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
DI:0.047UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
04222
04222
04222
04222
04222
04222
DG015E473Z
DG015E473Z
DG015E104Z
DG015E473Z
DG015E104Z
DG015El04Z
A2C536
A2C541
A2C551 .
A2C555
A2C560
A2C562
283-0421-00
283-0421-00
290-0745-00
283-0421-00
283-0421-00
290-0745-00
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
CAP.,FXD,ELCTLT:22UF, +50-1 0%,25V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
CAP.,FXD,ELCTLT:22UF, +50-1 0%,25V
04222
04222
54473
04222
04222
54473
DG015E104Z
DG015E104Z
ECE-A25V22L
DG015El04Z
DG015El04Z
ECE-A25V22L
A2C565
A2C570
A2C575
A2C576
A2CR9
A2CR10
283-0421-00
283-0421-00
283-0421-00
283-0421-00
152-0141-02
152-0141-02
CAP.,FXD,CER DI:0.1UF,+80-20%,50V
CAP.,FXD,CER DI:0.1 UF, + 80-20%,50V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
CAP.,FXD,CER DI:0.1 UF,+80-20%,50V
SEMICOND DEVICE:SILlCON,30V,150MA
SEMICOND DEVICE:SILlCON,30V,150MA
04222
04222
04222
04222
01295
01295
DG015E104Z
DG015E104Z
DG015E104Z
DG015E104Z
1N4152R
lN4152R
A2CR11
A2CR262
A2CR525
A2CR526
A2J61
A2J61
152-0141-02
152-0141-02
152-0141-02
152-0141-02
131-0608-00
SEMICOND DEVICE: SILlCON,30V, 150MA
SEMICOND DEVICE:SILlCON,30V,150MA
SEMICOND DEVICE:SILlCON,30V,150MA
SEMICOND DEVICE:SILlCON,30V,150MA
TERMINAL,PIN:0.365 LX 0.025 PH BRZ GOLD
(QUANTITY OF 2)
01295
01295
01295
01295
22526
1N4152R
1N4152R
1N4152R
1N4152R
47357
A2J62
A2J62
A2J63
A2J63
A2J103
A2J125
131 -0608-00
TERMINAL,PIN:0.365 L X 0.025 PH
(QUANTITY OF 2)
TERMINAL,PIN:0.365 LX 0.025 PH
(QUANTITY OF 2)
CONN,RCPT,ELEC:RT-ANGLE,2/10
TERMINAL,PIN:0.365 L X 0.025 PH
BRZ GOLD
22526
47357
BRZ GOLD
22526
47357
0.025 SQ PINS
BRZ GOLD
22526
22526
65268-008
47357
A2J125
4170 INSTRUCTION
131 -0608-00
131-1789-00
131-0608-00
(QUANTITY OF 2)
15-5
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
A2J150
A2J150
A2J155
A2J155
A2J226
A2J226
131-0608-00
A2J326
A2J326
A2J426
A2J426
A2J427
A2J427
131-0608-00
A2J522
A2J522
A2R9
A2R11
A2R12
A2R13
131-0608-00
131 -0608-00
131-0608-00
131-0608-00
131-0608-00
Serial/Model No.
Elf
Dscont
Name & Description
TERMINAL,PIN:0.365 L X 0.025 PH BRZ GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.365 LX 0.025 PH BRZ GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.365 LX 0.025 PH BRZ GOLD
(QUANTITY OF 5)
TERMINAL,PIN:0.365 LX 0.025 PH BRZ GOLD
(QUANTITY OF 5)
TERMINAL,PIN:0.365 LX 0.025 PH BRZ GOLD
(QUANTITY OF 5)
TERMINAL,PIN:0.365 LX 0.025 PH BRZ GOLD
(QUANTITY OF 5)
Mfr
Code
Mfr Part Number
22526
47357
22526
47357
22526
47357
22526
47357
22526
47357
22526
47357
22526
47357
315-0271-00
315-0361-00
315-0751-00
315-0751-00
TERMINAL,PIN:0.365 L X 0.025 PH BRZ GOLD
(QUANTITY OF 3)
RES.,FXD,CMPSN:270 OHM,5%,0.25W
RES.,FXD.CMPSN:360 OHM.5%.0.25W
RES.,FXD,CMPSN:750 OHM,5%,0.25W
RES.,FXD,CMPSN:750 OHM,5%,0.25W
01121
01121
01121
01121
CB2715
CB3615
CB7515
CB7515
A2R31
A2R55
A2R61
A2R62
A2R63
A2R158
307-0502-00
307-0650-00
315-0472-00
315-0472-00
315-0472-00
315-0511-00
RES NTWK,FXD,FI:(9) 1.8K OHM,20%,0.125W
RES NTWK,FXD,FI:9,2.7K OHM,5%,0.150W
RES.,FXD,CMPSN:4.7K OHM.5%.0.25W
RES.,FXD,CMPSN:4.7K OHM.5%,0.25W
RES.,FXD,CMPSN:4.7K OHM,5%.0.25W
RES.,FXD.CMPSN:510 OHM,5%,0.25W
91637
32997
01121
01121
01121
01121
MSP10AOl-182M
4310R-l01-272
CB4725
CB4725
CB4725
CB5115
A2R160
A2R175
A2R216
A2R250
A2R260
A2R350
315-0511-00
315-0272-00
307-0637-00
307-0650-00
315-0272-00
307-0650-00
RES.,FXD,CMPSN:510 OHM.5%.0.25W
RES.,FXD.CMPSN:2.7K OHM,5%,0.25W
RES NTWK,FXD,FI:5,2K OHM,2%,0.125W
RES NTWK,FXD,FI:9,2.7K OHM,5%,0.150W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES NTWK,FXD,FI:9,2.7K OHM,5%,0.150W
01121
01121
01121
32997
01121
32997
CB5115
CB2725
206A202
431 OR-l 01-272
CB2725
4310R-l01-272
A2R440
A2R525
A2R526
A2R550
A2U25
A2U35
307 -0446-00
315-0102-00
315-0102-00
307 -0446-00
156-0956-02
160-0843-00
RES,NTWK,FXD FI:l0K OHM,20%.(9) RES
RES.,FXD,CMPSN:1K OHM,5%,0.25W
RES.,FXD,CMPSN: 1K OHM,5%,0.25W
RES,NTWK,FXD FI:l0K OHM.20%,(9) RES
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:MICROCOMPUTER,PRGM,SCRN
91637
01121
01121
91637
01295
80009
MSPl OA01-l 03M
CB1025
CB1025
MSP10A01-103M
SN74LS244NP3
160-0843-00
A2U40
A2U45
A2U60
A2U65
A2U70
A2U75
156-1643-00
156-1416-00
156-0145-02
156-0385-02
156-0473-02
156-0479-02
MICROCIRCUIT,DI:HMOS.NUMERIC PROCESSOR EXT 34649
MICROCIRCUIT,DI:16 BIT UP,SCREENED
34649
MICROCIRCUIT,DI:QUAD 2-INP NAND BFR
01295
MICROCIRCUIT,DI:HEX INVERTER
01295
MICROCIRCUIT.DI:DUAL 5-INP NAND GATE,SCRN
27014
MICROCIRCUIT,DI:QUAD 2-INP OR GATE
01295
C 8087-3
08086
SN7438
SN74LS04
DM8092N/A+
SN74LS32NP3
A2U101
A2U115
A2U125
A2U130
A2U135
A2U145
156-0382-02
156-0041-05
156-0385-02
156-0469-02
156-0140-02
156-0478-02
MICROCIRCUIT.DI:QUAD 2-INP NAND GATE
MICROCIRCUIT,DI:DUAL D-TYPE FF,BURN-IN
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:3/8 LINE DC DR
MICROCIRCUIT,DI:HEX BUFFERS W/OC HV OUT
MICROCIRCUIT,DI:DUAL 4 INP & GATE.BURN-IN
01295
01295
01295
01295
27014
01295
SN74LSOO
SN7474
SN74LS04
SN74LS138NP3
DM8017NA+ IJA +
SN74LS21NP3
A2U150
A2U155
A2U165
A2U170
A2U175
A2U201
156-1065-01
156-1428-02
156-0694-02
156-0481-02
156-1059-01
156-0478-02
MICROCIRCUIT,DI:OCTAL 0 TYPE TRANS LATCHES
MICROCIRCUIT,DI:CLOCK GENERATOR & DRIVER
MICROCIRCUIT,DI:DCDR/3 LINE TO 8 LlNE.SCRN
MICROCIRCUIT,DI:TRIPLE 3 INP & GATE
MICROCIRCUIT,DI:DUAL J-K EDGE TRIGGERED
MICROCIRCUIT,DI:DUAL 4 INP & GATE,BURN-IN
34335
34649
07263
27014
01295
01295
AM74LS373
QD8284A
74S138DCQR
DM74LS11NA+
SN74LS109A
SN74LS21NP3
15-6
o OR
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Mfr
Code
Mfr Part Number
MICROCIRCUIT,DI:QUAD 2-INP NAND GATE
MICROCIRCUIT,DI:QUAD 2-INP NOR GATE
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:QUAD 2-INP NOR GATE
MICROCIRCUIT,DI:OCTAL D-TYPE FF W/CLEAR
MICROCIRCUIT,DI:PRGM INTERVAL TIMER
01295
01295
01295
01295
01295
34649
SN74LSOO
SN74LS02
SN74LS04
SN74LS02
SN74LS273NP3
QD8253
156-1172-01
156-0392-03
156-0385-02
156-1065-01
156-1065-01
156-0465-02
MICROCIRCUIT,DI:DUAL 4 BIT CNTR
MICROCIRCUIT,DI:QUAD LATCH W/CLEAR
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:OCTAL 0 TYPE TRANS LATCHES
MICROCIRCUIT,DI:OCTAL 0 TYPE TRANS LATCHES
MICROCIRCUIT,DI:8 INP NAND GATE
01295
01295
01295
34335
34335
01295
SN74LS393
SN74S175NP3
SN74LS04
AM74LS373
AM74LS373
SN74LS30NP3
A2U262
A2U265
A2U270
A2U275
A2U301
A2U325
156-0383-02
156-0382-02
156-0386-02
156-1258-01
156-1460-00
156-0467 -02
MICROCIRCUIT,DI:QUAD 2-INP NOR GATE
MICROCIRCUIT,DI:QUAD 2-INP NAND GATE
MICROCIRCUIT,DI:TRIPLE 3-INP NAND GATE
MICROCIRCUIT,DI:DUAL J-K NEG-EDGE TRIG FF
MICROCIRCUIT,DI:ENHANCED PRGM COMM INTFC
MICROCIRCUIT,DI:QUAD 2-INP NAND BFR,SCRN
01295
01295
27014
01295
18324
01295
SN74LS02
SN74LSOO
DM74LS10N
SN74LSl12
2661-21/CP2752
SN74LS38
A2U350
A2U355
A2U360
A2U365
A2U370
A2U401
156-1111-02
156-0118-03
156-0690-03
156-0722-02
156-1204-01
156-0391 -02
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
MICROCIRCUIT,DI:l DUAL J-K FF,BURN-IN
MICROCIRCUIT,DI:QUAD 2 INP NOR GATE,BURN IN
MICROCIRCUIT,DI:TPL 3-INPUT POS NAND GATE
MICROCIRCUIT,DI:INTERRUPT CONTROLLER,SCRN
MICROCIRCUIT,DI:HEX LATCH W/CLEAR
01295
01295
01295
04713
34649
01295
SN74LS245JP3
SN74S112JP3
SN74S02
SN74LS12NDS
QD8259A
SN74LS174
A2U415
A2U425
A2U450
A2U455
A2U460
A2U465
156-0845-02
156-0720-02
156-1111-02
156-0419-02
156-0955-02
156-0385-02
MICROCIRCUIT,DI:6 BIT COMPARATOR,BURN-IN
MICROCIRCUIT,DI:HEX DRVR,4 TO 2 LINE
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
MICROCIRCUIT,DI:DUAL 4 INP NAND LINE DRVR
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:HEX INVERTER
80009
01295
01295
07263
04713
01295
156-0845-02
SN74LS368
SN74LS245JP3
74S140
SN74LS241
SN74LS04
A2U470
A2U475
A2U501 .
A2U515
A2U525
A2U530
156-0140-02
156-0473-02
156-0878-01
156-0878-01
156-0879-01
156-0479-02
MICROCIRCUIT,DI:HEX BUFFERS W/OC HV OUT
MICROCIRCUIT,DI:DUAL 5-INP NAND GATE,SCRN
MICROCIRCUIT,DI:QUAD LINE RCVR,SCRN
MICROCIRCUIT,DI:QUAD LINE RCVR,SCRN
MICROCIRCUIT,DI:QUAD LINE DRIVER,SCRN
MICROCIRCUIT,DI:QUAD 2-INP OR GATE
27014
27014
80009
80009
80009
01295
DM8017NA+/JA+
DM8092N/A+
156-0878-01
156-0878-01
156-0879-01
SN74LS32NP3
A2U535
A2U536
A2U540
A2U541
A2U550
A2U555
156-1786-00
156-1786-00
156-1786-00
156-1786-00
156-1111-02
156-1111-02
MICROCIRCUIT,DI:CMOS,STATIC RAM, 1024 X 4
MICROCIRCUIT,DI:CMOS,STATIC RAM, 1024 X 4
MICROCIRCUIT,DI:CMOS,STATIC RAM, 1024 X 4
MICROCIRCUIT,DI:CMOS,STATIC RAM, 1024 X 4
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
Tl015
Tl015
Tl015
Tl015
01295
01295
HM4334P-3
HM4334P-3
HM4334P-3
HM4334P-3
SN74LS245JP3
SN74LS245JP3
A2U560
A2U565
A2U570
A2U575
A2Y155
A2Y155
156-1427 -01
156-1065-01
156-1065-01
156-1065-01
158-0135-00
MICROCIRCUIT,DI:BUS CONTROLLER,SCREENED
MICROCIRCUIT,DI:OCTAL D TYPE TRANS LATCHES
MICROCIRCUIT,DI:OCTAL 0 TYPE TRANS LATCHES
MICROCIRCUIT,DI:OCTAL 0 TYPE TRANS LATCHES
XTAL UNIT,QTZ:14.7456 MHZ,O.Ol%,SERIES
(CRYSTAL REQUIRES FOAM ADHESIVE)
34649
34335
34335
34335
01807
QD8288
AM74LS373
AM74LS373
AM74LS373
OBD
Component No.
Tektronix
Part No.
A2U202
A2U215
A2U216
A2U225
A2U226
A2U230
156-0382-02
156-0383-02
156-0385-02
156-0383-02
156-0865-02
156-1036-01
A2U235
A2U240
A2U245
A2U250
A2U255
A2U260
4170 INSTRUCTION
Serial/Model No.
Elf
Dscont
Name & Description
15-7
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
Serial/Model No.
Elf
Dscont
Name & Description
Mfr
Code
Mfr Part Number
A3 DISK CONTROLLER
A3
A3
A3C2
A3C5
670-8148-00
80009
670-8148-00
283-0065-00
283-0421-00
CKT BOARD ASSY:DISK CONTROLLER
(OPTION 44 ONLY)
CAP.,FXD,CER DI:0.001 UF,5%,100V
CAP.,FXD,CER DI:0.1 UF, + 80-20%,50V
59660
04222
0835-591 Y5E01 02J
DG015E104Z
A3C7
A3C15
A3C25
A3C35
A3C40
A3C55
285-1076-00
283-0421-00
283-0421-00
290-0746-00
283-0421-00
283-0421-00
CAP.,FXD.PLSTC:0.2UF,5%,100V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
CAP.,FXD,ELCTLT:47UF, +50-1 0%,16V
CAP.,FXD,CER 01:0.1 UF, +80-20%,50V
CAP.,FXD,CER DI:0.1 UF, + 80-20%,50V
14752
04222
04222
55680
04222
04222
230B1B204J
DG015E104Z
DG015E104Z
ULA 1C470TEA
DG015E104Z
oG015E104Z
A3C100
A3C102
A3C105
A3C108
A3C110
A3C120
283-0421-00
283-0333-00
283-0421-00
283-0635-00
283-0635-00
283-0421-00
CAP.,FXD,CER 01:0.lUF,+80-20%,50V
CAP.,FXD,CER DI:35PF,5%,1000V
CAP.,FXo,CER 01:0.1UF,+80-20%,50V
CAP.,FXo,MICA D:51PF,l%,100V
CAP.,FXo,MICA D:51PF,l%,100V
CAP.,FXo,CER 01:0.1 UF, + 80-20%,50V
04222
72982
04222
00853
00853
04222
oG015E104Z
838-534 A 350 >
oG015E104Z
0151E510FO
o151E510FO
DG015E104Z
A3C125
A3C135
A3C140
A3C155
A3C160
A3C170
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXD,CER
CAP.,FXo,CER
CAP.,FXo,CER
CAP.,FXo,CER
CAP.,FXo,CER
CAP.,FXo,CER
DI:0.1 UF, +80-20%,50V
DI:O.1UF, +80-20%,50V
DI:0.1UF,+80-20%,50V
01:0.1UF,+80-20%,50V
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
04222
04222
04222
04222
04222
04222
DG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
DG015E104Z
oG015E104Z
A3C205
A3C220
A3C230
A3C240
A3C250
A3C260
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXD,CER
CAP.,FXo,CER
CAP.,FXo,CER
CAP.,FXo,CER
CAP.,FXo,CER
CAP.,FXo,CER
DI:0.1UF,+80-20%,50V
01:0.lUF,+80-20%,50V
DI:0.1 UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
04222
04222
04222
04222
04222
04222
oG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
A3C270
A3C325
A3C330
A3C350
A3C360
A3C375
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXo,CER
CAP.,FXo,CER
CAP.,FXo,CER
CAP .. FXo,CER
CAP.,FXo,CER
CAP.,FXo,CER
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
DI:0.1UF,+80-20%,50V
DI:O.1UF,+ 80-20%,50V
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
04222
04222
04222
04222
04222
04222
oG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
A3C405
A3C415
A3C435
A3C450
A3C460
A3C475
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXo,CER
CAP.,FXo,CER
CAP.,FXD,CER
CAP.,FXo,CER
CAP.,FXo,CER
CAP.,FXD,CER
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
01:0.lUF,+80-20%,50V
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
04222
04222
04222
04222
04222
04222
OG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
oG015E104Z
A3C505
A3C515
A3C525
A3C535
A3C550
A3C560
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXD,CER
CAP.,FXo,CER
CAP.,FXD,CER
CAP.,FXo,CER
CAP.,FXo,CER
CAP .. FXo,CER
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
01:0.1UF,+80-20%,50V
01:0.1 UF, + 80-20%,50V
01:0.1UF,+80-20%,50V
01:0.1 UF, + 80-20%,50V
04222
04222
04222
04222
04222
04222
oG015E104Z
oG015E104Z
oG015E104Z
DG015E104Z
DG015E104Z
DG015E104Z
A3C570
A3C640
A3CR36
A3CR38
A3J10
A3J10
283-0421-00
290-0745-00
152-0066-00
152 -0066-00
131-0608-00
CAP.,FXo,CER 01:0.1 UF, + 80-20%,50V
CAP.,FXD,ELCTLT:22UF, + 50-1 0%,25V
SEMICOND DEVICE: SILlCON,400V, 750MA
SEMICONo DEVICE: SILlCON,400V, 750MA
TERMINAL,PIN:0.365 L X 0.025 PH BRZ GOLD
(QUANTITY OF 2)
04222
54473
14433
14433
22526
oG015E104Z
ECE-A25V22L
LG4016
LG4016
47357
15-8
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
A3J200
A3J200
A3J205
A3J206
A3J220
A3J220
131-0608-00
A3J225
A3J225
A3J260
A3J510
A3J510
A3J511
1 31 -0608-00
131-0589-00
131-0589-00
131-0608-00
131-0608-00
131-0608-00
131-0608-00
Serial/Model No.
Eft
Dscont
Mfr
Code
Mfr Part Number
TERMINAL,PIN:0.365 L X 0.025 PH BRl GOLD
(QUANTITY OF 10)
TERMINAL,PIN:0.46 L X 0.025 SQ
TERMINAL,PIN:0.46 L X 0.025 SQ
TERMINAL,PIN:0.365 L X 0.025 PH BRl GOLD
(QUANTITY OF 10)
22526
47357
22526
22526
22526
48283-029
48283-029
47357
TERMINAL,PIN:0.365
(QUANTITY OF 2)
TERMINAL,PIN:0.365
TERMINAL,PIN:0.365
(QUANTITY OF 5)
TERMINAL,PIN:0.365
LX 0.025 PH BRl GOLD
22526
47357
L X 0.025 PH BRl GOLD
L X 0.025 PH BRl GOLD
22526
22526
47357
47357
LX 0.025 PH BRl GOLD
22526
47357
22526
47357
Name & Description
22526
47357
315-0821-00
(QUANTITY OF 5)
TERMINAL,PIN:0.365 LX 0.025 PH BRl GOLD
(QUANTITY OF 5)
TERMINAL,PIN:0.365 L X 0.025 PH BRl GOLD
(QUANTITY OF 5)
RES.,FXD,CMPSN:820 OHM,5%,0.25W
01121
CB8215
A3R5
A3R27
A3R28
A3R29
A3R30
A3R32
315-0202-00
315-0121-00
315-0272-00
31 5-0272-00
315-0272-00
315-0121-00
RES.,FXD,CMPSN:2K OHM,5%,O.25W
RES.,FXD,CMPSN:120 OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:120 OHM,5%,0.25W
01121
01121
01121
01121
01121
01121
CB2025
CB1215
CB2725
CB2725
CB2725
CB1215
A3R33
A3R34
A3R35
A3R36
A3R38
A3R42
315-0121-00
315-0121-00
315-0121-00
315-0121-00
315-0121-00
315-0272-00
RES.,FXD,CMPSN:120 OHM,5%,0.25W
RES.,FXD,CMPSN: 120 OHM,5%,0.25W
RES.,FXD,CMPSN: 120 OHM,5%,0.25W
RES.,FXD,CMPSN:120 OHM,5%,0.25W
RES.,FXD,CMPSN:120 OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
01121
01121
01121
01121
01121
01121
CB1215
CB1215
CB1215
CB1215
CB1215
CB2725
A3R45
A3R46
A3R55
A3Rl00
A3Rl08
A3Rl09
315-0363-00
315-0272-00
31 5-0363-00
315-0102-00
321-0329-00
131-0566-00
RES.,FXD,CMPSN:36K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:36K OHM,5%,0.25W
RES.,FXD,CMPSN:l K OHM,5%,0.25W
RES.,FXD,FILM:26.1K OHM,1%,0.125W
BUS CONDUCTOR:DUMMY RES,2.375,22 AWG
01121
01121
01121
01121
91637
57668
CB3635
CB2725
CB3635
CB1025
MFF1816G261 01 F
JWW-0200EO
A3Rll0
A3R162
A3R260
A3R265
A3R335
A3R340
321-0236-00
315-0121-00
307-0502-00
315-0102-00
307-0650-00
307 -0650-00
RES.,FXD,FILM:2.8K OHM,l %,0.125W
RES.,FXD,CMPSN:120 OHM,5%,0.25W
RES NTWK,FXD,FI:(9) 1.8K OHM,20%,0.125W
RES.,FXD,CMPSN:l K OHM,5%,0.25W
RES NTWK,FXD,FI:9,2.7K OHM,5%,0.150W
RES NTWK,FXD,FI:9,2.7K OHM,5%,0.150W
91637
01121
91637
01121
32997
32997
MFF1816G28000F
CB1215
MSP10AOl-182M
CB1025
4310R-101-272
431 OR-l 01-272
A3R435
A3R500
A3R508
A3R512
A3U5
A3Ul0
307 -0445-00
31 5-01 02-00
315-0102-00
307 -0650-00
156-0124-02
156-0530-02
RES NTWK,FXD,FI:4.7K OHM,20%,(9) RES
RES.,FXD,CMPSN:1K OHM,5%,0.25W
RES.,FXD,CMPSN: 1K OHM,5%,0.25W
RES NTWK,FXD,FI:9,2.7K OHM,5%,0.150W
MICROCIRCUIT,DI:PHASE/FREQ DETECTOR,SCRN
MICROCIRCUIT,DI:QUAD 2-INP MUX,SCRN
91637
01121
01121
32997
80009
01295
MSPl OAOl-4 72M
CB1025
CB1025
4310R-l01-272
156-0124-02
SN74LS157P3
A3U15
A3U17
A3U20
A3U30
A3U40
A3U45
156-0617 -02
156-0385-02
156-0388-03
156-0385-02
156-0093-02
156-0140-02
MICROCIRCUIT,DI:DUAL 4 BIT CNTR,SCRN
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:DUAL D FLIP-FLOP
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:HEX INV BUFFER,BURN-IN
MICROCIRCUIT,DI:HEX BUFFERS W/OC HV OUT
01295
01295
07263
01295
27014
27014
SN74393NP3
SN74LS04
74LS74A
SN74LS04
DM8016
DM8017NA + /JA +
A3J511
A3J512
A3J512
A3J513
A3J513
A3R3
4170 INSTRUCTION
131-0608-00
131-0608-00
15-9
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
A3U55
A3U105
A3U110
A3U120
A3U120
A3U125
156-0093-02
156-0121-02
156-0733-02
119-0413-00
Serial/Model No.
Eft
Dscont
Name & Description
Mfr
Code
Mfr Part Number
27014
80009
04713
T1043
DM8016
156-0121-02
SN74LS221 N/J
XO-33C8
156-0480-02
MICROCIRCUIT,DI:HEX INV BUFFER,BURN-IN
MICROCIRCUIT,DI:DUAL VOLTAGE-CONT MV,SCRN
MICROCIRCUIT,DI:DUAL MONOSTABLE MV,SCRN
OSC,XTAL CLOCK:8 MHZ
(CRYSTAL REQUIRES FOAM ADHESIVE)
MICROCIRCUIT,DI:QUAD 2 INP & GATE
01295
SN74LS08NP3
A3U130
A3U135
A3U140
A3U145
A3U150
A3U155
156-0481-02
156-0388-03
156-0541-02
156-0530-02
156-0914-03
156-0798-02
MICROCIRCUIT,DI:TRIPLE 3 INP & GATE
MICROCIRCUIT,DI:DUAL D FLIP-FLOP
MICROCIRCUIT,DI:DUAL 2 TO 4 LINE DCDR
MICROCIRCUIT,DI:QUAD 2-INP MUX,SCRN
MICROCIRCUIT,DI:OCT SR BBR W/3 ST OUT
MICROCIRCUIT,DI:DUAL 14 TO 1 LINE SEL/MUX
27014
07263
01295
01295
27014
01295
DM74LS11NA+
74LS74A
SN74LS139NP3
SN74LS157P3
N74LS240N
SN74LS153
A3U160
A3U170
A3U225
A3U230
A3U235
A3U240
156-0798-02
156-0480-02
156-0391-02
156-0382-02
156-0914-03
156-0985-01
MICROCIRCUIT,DI:DUAL 14 TO 1 LINE SEL/MUX
MICROCIRCUIT,DI:QUAD 2 INP & GATE
MICROCIRCUIT,DI:HEX LATCH W/CLEAR
MICROCIRCUIT,DI:QUAD 2-INP NAND GATE
MICROCIRCUIT,DI:OCT SR BBR W/3 ST OUT
MICROCIRCUIT,DI:DUAL 5 INPUT NOR GATE,SCRN
01295
01295
01295
01295
27014
04713
SN74LS153
SN74LS08NP3
SN74LS174
SN74LSOO
N74LS240N
SN74LS260
A3U245
A3U250
A3U255
A3U260
A3U265
A3U270
156-0469-02
156-0651-02
156-0480-02
156-0382-02
160-2519-00
156-0866-02
MICROCIRCUIT,DI:3/8 LINE DCDR
MICROCIRCUIT,DI:8 BIT PRL-OUT SER SHF RGTR
MICROCIRCUIT,DI:QUAD 2 INP & GATE
MICROCIRCUIT,DI:QUAD 2-INP NAND GATE
MICROCIRCUIT,DI:32 X 8 PROM,PRGM
MICROCIRCUIT,DI:13 INP NAND GATES,SCRN
01295
01295
01295
01295
80009
80009
SN74LS138NP3
SN74LS164(NP3 OR
SN74LS08NP3
SN74LSOO
160251900
156-0866-02
A3U325
A3U330
A3U340
A3U350
A3U355
A3U360
156-0386-02
156-0383-02
156-1412-00
156-0479-02
156-0865-02
156-0385-02
MICROCIRCUIT,DI:TRIPLE 3-INP NAND GATE
MICROCIRCUIT,DI:QUAD 2-INP NOR GATE
MICROCIRCUIT,DI:SGL/DBL DENS FLOPPY DISC
MICROCIRCUIT,DI:QUAD 2-INP OR GATE
MICROCIRCUIT,DI:OCTAL D-TYPE FF W/CLEAR
MICROCIRCUIT,DI:HEX INVERTER
27014
01295
34649
01295
01295
01295
DM74LS10N
SN74LS02
D8272A
SN74LS32NP3
SN74LS273NP3
SN74LS04
A3U365
A3U370
A3U375
A3U425
A3U430
A3U435
156-041 2-02
156-0412-02
156-0385-02
156-0956-02
156-0385-02
156-0467 -02
MICROCIRCUIT,DI:SYN 4 BIT UP/DOWN CNTR
MICROCIRCUIT,DI:SYN 4 BIT UP/DOWN CNTR
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:QUAD 2-INP NAND BFR,SCRN
01295
01295
01295
01295
01295
01295
SN74LS193N3
SN74LS193N3
SN74LS04
SN74LS244NP3
SN74LS04
SN74LS38
A3U450
A3U455
A3U460
A3U465
A3U470
A3U475
156-0385-02
156-0093-02
156-0385-02
156-0412-02
156-0412-02
156-0412-02
MICROCIRCUIT,DI:HEX
MICROCIRCUIT,DI:HEX
MICROCIRCUIT,DI:HEX
MICROCIRCUIT,DI:SYN
MICROCIRCUIT,DI:SYN
MICROCIRCUIT,DI:SYN
01295
27014
01295
01295
01295
01295
SN74LS04
DM8016
SN74LS04
SN74LS193N3
SN74LS193N3
SN74LS193N3
A3U505
A3U510
A3U515
A3U520
A3U525
A3U530
156-0694-02
156-0956-02
156-0464-02
156-0956-02
156-0956-02
156-0382-02
MICROCIRCUIT,DI:DCDR/3 LINE TO 8 LlNE,SCRN
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:DUAL 4 INP NAND GATE
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:QUAD 2-INP NAND GATE
07263
01295
01295
01295
01295
01295
74S138DCQR
SN74LS244NP3
SN74LS20
SN74LS244NP3
SN7 4LS244N P3
SN74LSOO
A3U535
A3U540
A3U550
A3U555
A3U560
A3U565
156-1111-02
156-1111-02
156-0462-02
156-0539-01
156-0385-02
156-0914-03
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
MICROCIRCUIT,DI:HEX INVERTER,SCREENED
MICROCIRCUIT,DI:6 BIT UNIFIED BUS COMPTR
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:OCT SR BBR W/3 ST OUT
01295
01295
01295
80009
01295
27014
SN74LS245JP3
SN74LS245JP3
SN7414
156-0539-01
SN74LS04
N74LS240N
A3U570
A3U575
156-0914-03
156-0914-03
MICROCIRCUIT,DI:OCT SR BBR W/3 ST OUT
MICROCIRCUIT,DI:OCT SR BBR W/3 ST OUT
27014
27014
N74LS240N
N74LS240N
15·10
INVERTER
INV BUFFER,BURN-IN
INVERTER
4 BIT UP/DOWN CNTR
4 BIT UP/DOWN CNTR
4 BIT UP/DOWN CNTR
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
Serial/Model No.
Elf
Dscont
Name & Description
Mfr
Code
Mfr Part Number
M FRONT PANEL
A4
A4C103
A4C104
MC124
670-8120-00
283-0370-00
283-0238-00
283-0167-00
CKT BOARD ASSY:FRONT PANEL
CAP.,FXD,CER DI:0.027UF,5%,100V
CAP.,FXD,CER DI:0.01UF,10%,50V
CAP.,FXD,CER DI:0.1UF,10%,100V
80009
72982
72982
72982
670-8120-00
8131 N153X7R0273J
8121N075X7R0103K
8131N145X5R0104K
MC133
A4C510
A4C520
MC530
A4C605
MC608
283-0164-00
283-0422-00
283-0422-00
283-0422-00
290-0779-00
290-0779-00
CAP.,FXD,CER DI:2.2UF,20%,25V
CAP.,FXD,CER DI:0.047UF, +80-20%,50V
CAP.,FXD,CER DI:0.047UF,+80-20%,50V
CAP.,FXD,CER DI:0.047UF,+80-20%,50V
CAP.,FXD,ELCTLT:10UF,+50-10%,50VDC
CAP.,FXD,ELCTLT:10UF,+50-10%,50VDC
04222
04222
04222
04222
56289
56289
SR402E225MAA
DG015E473Z
DG015E473Z
DG015E473Z
5020237
5020237
MC620
A4C625
MC630
A4C635
A4D1
MD2
283-0422-00
283-0422-00
283-0422-00
283-0422-00
150-1078-00
150-1078-00
CAP.,FXD,CER DI:0.047UF, +80-20%,50V
CAP.,FXD,CER DI:0.047UF, + 80-20%,50V
CAP.,FXD,CER DI:0.047UF,+80-20%,50V
CAP.,FXD,CER DI:0.047UF,+80-20%,50V
LT EMITIING DIO:GREEN,565NM,20MA
LT EMITIING DIO:GREEN,565NM,20MA
04222
04222
04222
04222
50434
50434
DG015E473Z
DG015E473Z
DG015E473Z
DG015E473Z
HLMP 1502
HLMP 1502
A4D3
MD4
A4D5
A4DS109
A4DS124
A4J440
150-1078-00
150-1013-00
150-1013-00
150-1033-00
150-1 033-00
131-0608-00
LT EMITIING DIO:GREEN,565NM,20MA
LAMP,LED:READOUT
LAMP,LED:READOUT
LT EMITIING DIO:YELLOW,585NM,40MA MAX
LT EMITIING DIO:YELLOW,585NM,40MA MAX
TERMINAL,PIN:0.365 LX 0.025 PH BRZ GOLD
50434
01295
01295
50434
50434
22526
HLMP 1502
TIL311
TIL311
HLMP 1401
HLMP 1401
47357
22526
47357
22526
22526
65268-008
47357
MJ440
A4J441
MJ441
A4J443
A4J446
A4J446
131-0608-00
131-1789-00
131-0608-00
(QUANTITY OF 3)
TERMINAL,PIN:0.365 LX 0.025 PH BRZ GOLD
(QUANTITY OF 2)
CONN,RCPT,ELEC:RT-ANGLE,2/10 0.025 SQ PINS
TERMINAL,PIN:0.365 LX 0.025 PH BRZ GOLD
(QUANTITY OF 4)
A4LS125
A4Q122
A4Q130
MQ135
A4R101
A4R102
119-1427-00
151-0103-00
151-0301-00
151-0281-00
315-0223-00
315-0183-00
XDCR,AUDIO:6V,30MA,1-4.2 KHZ
TRANSISTOR: SI LlCON,NPN
TRANSISTOR:SILlCON,PNP
TRANSISTOR:SILlCON,NPN
RES.,FXD,CMPSN:22K OHM,5%,O.25W
RES.,FXD,CMPSN:18K OHM,5%,O.25W
OOOJB
80009
27014
03508
01121
01121
QMB-06
151-0103-00
2N2907A
X16P4039
CB2235
CB1835
A4R104
A4R105
A4R106
A4R107
A4R108
A4R121
315-0151-00
315-0151-00
315-0151-00
315-0151-00
315-0271-00
315-0222-00
RES.,FXD,CMPSN:150 OHM,5%,O.25W
RES.,FXD,CMPSN:150 OHM,5%,O.25W
RES.,FXD,CMPSN:150 OHM,5%,O.25W
RES.,FXD,CMPSN:150 OHM,5%,O.25W
RES.,FXD,CMPSN:270 OHM,5%,O.25W
RES.,FXD,CMPSN:2.2K OHM,5%,O.25W
01121
01121
01121
01121
01121
01121
CB1515
CB1515
CB1515
CB1515
CB2715
CB2225
A4R123
A4R125
A4R126
A4R127
MR128
A4R131
315-0271-00
315-0821-00
315-0821-00
315-0821 -00
31 5-0821-00
315-0271 -00
RES.,FXD,CMPSN:270
RES.,FXD,CMPSN:820
RES.,FXD,CMPSN:820
RES.,FXD,CMPSN:820
RES.,FXD,CMPSN:820
RES .. FXD,CMPSN:270
01121
01121
01121
01121
01121
01121
CB2715
CB8215
CB8215
CB8215
CB8215
CB2715
A4R132
A4R134
A4R135
A4R609
A4R610
315-0224-00
315-0200-00
315-0102-00
307-0422-00
315-0333-00
RES.,FXD,CMPSN:220K OHM,5%,O.25W
RES.,FXD,CMPSN:20 OHM,5%,O.25W
RES.,FXD,CMPSN: 1K OHM,5%,O.25W
RES.,FXD,FILM:15 RES. NETWORK
RES.,FXD,CMPSN:33K OHM,5%,O.25W
01121
01121
01121
73138
01121
CB2245
CB2005
CB1025
898-1-R2.4K
CB3335
4170 INSTRUCTION
OHM,5%,O.25W
OHM,5%,O.25W
OHM,5%,O.25W
OHM,5%,O.25W
OHM,5%,O.25W
OHM,5%,O.25W
15-11
REPLACEABLE ELECTRICAL PARTS
Mfr
Code
Mfr Part Number
ASSY:MOMENTAR,(
ASSY:MOMENTARY
ASSY:MOMENTARY
ASSY:MOMENTARY
ASSY:MOMENTARY
ASSY:MOMENTARY
80009
80009
80009
80009
80009
80009
263-0019-09
263-0019-09
263-0019-09
263-0019-09
263-0019-09
263-0019-09
ASSY:MOMENTARY
ASSY:MOMENTARY
ASSY:MOMENTARY
ASSY:MOMENTARY
ASSY:MOMENTARY
ASSY:MOMENTARY
80009
BOO09
BOO09
80009
BOO09
80009
263-0019-09
263-0019·09
263·0019·09
263·0019·09
263·0019·09
263·0019·09
263-0019·09
263-0019-09
263·0019·09
263·0019-09
263-0019-09
260-2163-00
SWITCH PB ASSY:MOMENTARY
SWITCH PB ASSY:MOMENTARY
SWITCH PB ASSY:MOMENTARY
SWITCH PB ASSY:MOMENfARY
SWITCH PB ASSY:MOMENTARY
SWITCH.PUSH:SPDT, 10 MA,24V
80009
BOO09
BOO09
80009
80009
263·0019·09
263·0019·09
263·0019·09
263-0019-09
263-0019-09
A4S19
A4U110
A4U510
A4U520
A4U530
A4U620
260-2163-00
156-0402-02
156-1065-01
156-0736-02
156-0153-02
156-0392-03
SWITCH.PUSH:SPDT, 10 MA.24V
MICROCIRCUIT,LI:TIMER,CHK
MICROCIRCUIT.DI:OCTAL D TYPE TRANS LATCHES
MICROCIRCUIT,DI:BCD TO DECIMAL DCDR
MICROCIRCUIT,DI:HEX INVERTER BUFFER
MICROCIRCUIT.DI:QUAD LATCH W/CLEAR
27014
34335
80009
27014
01295
LM555CN/A+
AM74LS373
156-0736-02
DM8006
SN74S175NP3
A4U625
A4U630
A4U635
156-0645-02
156-0B74-02
156-0B74-02
MICROCIRCUIT,DI:HEX INV ST NAND GATES,SCRN
MICROCIRCUIT.DI:B BIT ADDRESSABLE LCH
MICROCIRCUIT.DI:S BIT ADDRESSABLE LCH
01295
04713
04713
SN74LS14
SN74LS259
SN74LS259
Component No.
Tektronix
Part No.
A4S1
A4S2
A4S3
A4S4
A4S5
A4S6
263-0019-09
263-001 9-09
263-0019-09
263-0019-09
263-0019-09
263'0019-09
SWITCH
SWITCH
SWITCH
SWITCH
SWITCH
SWITCH
PB
PB
PB
PB
PB
PB
A4S7
A4SB
A4S9
A4S10
A4S11
A4S12
263-0019-09
263-0019-09
263-0019-09
263-0019-09
263-0019-09
263-0019-09
SWITCH
SWITCH
SWITCH
SWITCH
SWITCH
SWITCH
PB
PB
PB
PB
PB
PB
A4S13
A4S14
A4S15
A4S16
A4S17
A4S18
15-12
Serial/Model No.
Eff
Dscont
Name & Description
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
Serial/Model No.
Eft
Dscont
Name & Description
Mfr
Code
Mfr Part Number
80009
620-0324-00
56289
196D475X0050KA 1
56289
196D475X0050KA1
A5 POWER SUPPLY
A5
620-0324-00
CKT BOARD ASSY:POWER SUPPLY
A5A101
A5A102
118-3324-00
118-3324-00
SEMICOND DVC,DI:SCR,SWITCHING
SEMICOND DVC,DI:SCR,SWITCHING
A5A103
A5A201
A5A202
A5C101
A5C102
A5C103
118-3327 -00
118-3328-00
118-3328-00
11 8-3338-00
118-3338-00
118-3338-00
MICROCIRCUIT,DI:REG VOlT
ISOLATOR,OPTO:
ISOLATOR,OPTO:
CAPACITOR:0.47UF,250V
CAPACITOR:0.47UF,250V
CAPACITOR :0.47UF,250V
A5C104
A5C105
A5C106
A5C107
A5C108
A5C109
118-3333-00
118-3333-00
11 8-3333-00
118-3333-00
118-3338-00
11 8-3338-00
CAP.,FXD,ELCTLT:470UF,200V
CAP.,FXD,ELCTLT:470UF,200V
CAP.,FXD,ELCTLT:470UF,200V
CAP.,FXD,ELCTLT:470UF,200V
CAPACITOR:0.47UF,250V
CAPACITOR:0.47UF,250V
A5C110
A5C111
A5C112
A5C113
A5C114
A5C115
118-3331-00
11 8-3338-00
118-3341-00
118-3339-00
118-3491-00
290-0525-00
CAP.,FXD,ELCTLT: 100UF,1 OV
CAPACITOR:0.47UF,250V
CAP.,FXD,CER DI:0.0047UF,3KV
CAPACITOR:0.0033UF,1000V
CAP,FXD,PLASTIC:0.0047UF,1 KV
CAP.,FXD,ELCTLT:4.7UF,20%,50V
A5C116
A5C117
A5C118
A5C119
A5C120
A5C121
118-3334-00
118-3334-00
11 8-3334-00
11 8-3334-00
118-3334-00
11 8-3334-00
CAP.,FXD,ELCTLT:1 000UF,1 OV
CAP.,FXD,ELCTLT: 1000UF,1 OV
CAP.,FXD,ELCTLT:1 000UF,1 OV
CAP.,FXD,ELCTLT:1 000UF,1 OV
CAP.,FXD,ELCTLT:1 000UF,1 OV
CAP.,FXD,ELCTLT:1 000UF,1 OV
A5C122
A5C123
A5C124 .
A5C125
A5C126
A5C127
11 8-3334-00
11 8-3334-00
118-3332-00
118-3332-00
11 8-3331 -00
11 8-3338-00
CAP.,FXD,ELCTLT:1 000UF,1 OV
CAP.,FXD,ELCTLT: 1000UF,1 OV
CAP.,FXD,ELCTLT:6800UF,6.3V
CAP.,FXD,ELCTLT:6800UF,6.3V
CAP.,FXD,ELCTLT:100UF,10V
CAPACITOR:0.47UF,250V
A5C128
A5C129
A5C130
A5C131
A5C132
A5C133
11 8-3339-00
290-0525-00
118-3334-00
11 8-3334-00
118-3334-00
11 8-3334-00
CAPACITOR:0.0033UF,1000V
CAP.,FXD,ELCTLT:4.7UF,20%,50V
CAP.,FXD,ELCTLT: 1OOOUF,1 OV
CAP.,FXD,ELCTLT:1 000UF,1 OV
CAP.,FXD,ELCTLT:1000UF,10V
CAP.,FXD,ELCTLT:1 000UF,1 OV
A5C134
A5C135
A5C136
A5C137
A5C138
A5C139
11 8-3334-00
11 8-3334-00
118-3334-00
11 8-3334-00
118-3332-00
118-3332-00
CAP.,FXD,ELCTLT:1 000UF,1 OV
CAP.,FXD,ELCTLT: 1OOOUF,1 OV
CAP.,FXD,ELCTLT: 1000UF,1 OV
CAP.,FXD,ELCTLT:1000UF,10V
CAP.,FXD,ELCTLT:6800UF,6.3V
CAP.,FXD,ELCTLT:6800UF,6.3V
A5C140
A5C141
A5C142
A5C143
A5C144
A5C145
118-3335-00
11 8-3335-00
11 8-3335-00
118-3335-00
11 8-3329-00
118-3489-00
CAP.,FXD,ELCTLT:470UF,25V
CAP.,FXD,ELCTLT:470UF,25V
CAP.,FXD,ELCTLT:470UF,25V
CAP.,FXD,ELCTLT:470UF,25V
CAP.,FXD,ELCTLT:2200UF,10-16V
CAP.,FXD,MTLZD:330UF,35V
4170 INSTRUCTION
15-13
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
A5C146
A5C147
A5C148
A5C201
A5C203
A5C204
118-3330-00
118-3490-00
118-3492-00
283-0081-00
283-0081-00
118-3496-00
CAP.,FXD,ELCTLT:220UF,35V
CAP.,FXD,ELCTLT:TANTALUM,2.2UF,16V
CAP.,FXD,CER DI:0.0047UF,250V
CAP.,FXD,CER DI:0.1UF,+80-20%,25V
CAP.,FXD,CER 01:0.1 UF, + BO-20%,25V
CAP.,FXD,PLASTIC:0.01 UF,63VDC
A5C207
A5CR101
A5CR102
A5CR103
A5CR104
A5CR105
118-3337-00
118-3488-00
118-3488-00
118-3488-00
118-3488-00
118-3320-00
CAPACITOR:0.0068UF,63-100V
SEMICOND DVC,DI:PWR,400V,3A
SEMICOND DVC,DI:PWR,400V,3A
SEMICOND DVC,DI:PWR,400V,3A
SEMICOND DVC,DI:PWR,400V,3A
SEMICOND DVC,DI:ZENER
A5CR106
A5CR107
A5CR108
A5CR109
A5CR110
A5CR111
152-0400-00
11 8-3319-00
118-3319-00
11 8-3319-00
118-3319-00
118-3319-00
SEMICOND
SEMICOND
SEMICOND
SEMICOND
SEMICOND
SEMICOND
DEVICE:SILlCON,400V,1A
DVC,DI:SCHOTKY,RECT
DVC,DI:SCHOTKY,RECT
DVC,DI:SCHOTKY,RECT
DVC,DI:SCHOTKY,RECT
DVC,DI:SCHOTKY,RECT
A5CR112
A5CR113
A5CR114
A5CR115
A5CR115
A5CR116
118-3319-00
118-3319-00
118-3319-00
118-3319-00
152-0400-00
118-331 9-00
SEMICOND
SEMICOND
SEMICOND
SEMICOND
SEMICOND
SEMICOND
DVC,DI:SCHOTKY,RECT
DVC,DI:SCHOTKY,RECT
DVC,DI:SCHOTKY,RECT
DVC,DI:SCHOTKY,RECT
DEVICE:SILlCON,400V,1A
DVC,DI:SCHOTKY,RECT
A5CR117
A5CR118
A5CR119
A5CR120
A5CR201
A5CR202
118-3320-00
152-0691-00
118-3318-00
118-3409-00
152-0062-00
152-0062-00
SEMICOND
SEMICOND
SEMICOND
SEMICOND
SEMICOND
SEMICOND
DVC,DI:ZENER
DEVICE:ZENER, 1.0W, 10%,5.1 V
DVC,DI:PWR
DVC,DI:RECT,SCHOTKY
DVC,DI:SW,SI,100V,25NA - 20V
DVC,DI:SW,SI,100V,25NA - 20V
A5CR203
A5CR204
A5CR205
A5CR206
A5CR207
A5CR208
118-3321-00
118-3494-00
152-0066-01
152-0062-00
152-0062-00
118-3321-00
SEMICOND
SEMICOND
SEMICOND
SEMICOND
SEMICOND
SEMICOND
DVC,DI:ZENER
DVC,DI:ZENER,100V
DEVICE:SILlCON,400V,1A
DVC,DI:SW,SI,100V,25NA"'::" 20V
DVC,DI:SW,SI,100V,25NA - 20V
DVC,DI:ZENER
A5CR209
A5CR210
A5F101
A5F106
A5F107
A5F114
118-3321-00
152-0066-01
159-0014-00
118-3493-00
118-3493-00
118-3493-00
SEMICOND DVC,DI:ZENER
SEMICOND DEVICE:SILlCON,400V,1A
FUSE,CARTRIDGE:3AG,5A,250V,FAST-BLOW
FUSE:PICO,0.75A
FUSE:PICO,0.75A
FUSE:PICO,0.75A
A5J61
A5J63
A5J101
A5J104
A5L103
A5L104
118-3353-00
118-3567-00
131-2663-00
118-3352-00
118-3497-00
118-3497-00
CONN,RCPT,ELEC:RT ANGLE,18 PIN,GOLD PL
CONN,RCPT,ELEC:HEADER,RTANG,2 POSITION
CONN,RCPT,ELEC:PWR,3 MALE,250 VAC,6A
CONN,RCPT,ELEC:D TYPE
COIL:INDUCTOR,RADIAL
COIL:INDUCTOR,RADIAL
A5L105
A5L106
A5L106
A5L107
A5L108
A5L109
118-3497-00
118-3355-00
118-3497-00
118-3497-00
118-3497-00
118-3354-00
COIL:INDUCTOR,RADIAL
INDUCTOR:12-1I2 TURN
COIL:lNDUCTOR,RADIAL
COIL:INDUCTOR,RADIAL
COIL:INDUCTOR,RADIAL
INDUCTOR:
15-14
Serial/Model No.
Eft
Dscont
Name & Description
Mfr
Code
Mfr Part Number
59821
59821
2DDU69E104Z
2DDU69E104Z
80009
152-0400-00
80009
152-0400-00
80009
152-0691-00
15238
LG4012
15238
71400
LG4012
MTH5
70903
17265
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
ASP101
ASP203
AS0101
A50102
A50201
A50202
131·1234·00
11 8·332S·00
118·3322-00
118-3322-00
118·3326-00
11 8-3323-00
AS0204
A50205
A50206
AS0207
AS0208
AS0209
Mfr
Code
Mfr Part Number
CONN,RCPT,ELEC:PWR,FEMALE,2S0VAC,6A
TRANSISTOR:UJT
TRANSISTOR:NPN,SELECTED
TRANSISTOR:NPN,SELECTED
TRANSISTOR:UJT
TRANSISTOR:NPN
82389
EAC·30S
1S1-0103-00
151-0190-00
1S1-0190-00
1S1-0188-00
151-0190-00
1S1-0190-00
TRANSISTOR:SILlCON,NPN
TRANSISTOR:NPN,SI,TO-92
TRANSISTOR:NPN,SI,TO-92
TRANSISTOR:SILlCON,PNP
TRANSISTOR:NPN,SI,TO-92
TRANSISTOR:NPN,SI,TO-92
80009
04713
04713
04713
04713
04713
151-0103·00
SPS7969
SPS7969
SPS6868K
SPS7969
SPS7969
AS0210
AS0211
AS0212
ASR101
ASR101
ASR102
151-0188-00
151-0302 -00
151-0190-00
301·0241-00
344-0326-00
301-0241-00
TRANSISTOR:SILlCON,PNP
TRANSISTOR:NPN,SI,TO-18
TRANSISTOR:NPN,SI,TO·92
RES.,FXD,CMPSN:240 OHM,S%,O.SOW
CLlP,ELECTRICAL:FUSE,BRASS
RES.,FXD,CMPSN:240 OHM,S%,0.50W
04713
04713
04713
01121
7S91S
01121
SPS6868K
ST899
SPS7969
EB2415
102071
EB2415
ASR103
ASR104
A5R104
ASR104
A5R105
ASR108
301-0113-00
30S-0390·00
311-1S5S-00
RES.,FXD,CMPSN: 11 K OHM,S%,O.SOW
RES.,FXD,CMPSN:39 OHM,S%,2W
RES.,VAR,NONWIR:100K OHM,20%,0.SW
(SMALL CIRCUIT BOARD ONLY)
RES.,FXD,CMPSN:470 OHM,S%,O.SOW
RES.,FXD,WW:680HM,S%,5W
01121
01121
73138
EB1135
HB3905
91-77·0
01121
EB4715
01121
73138
EB2735
91-84-0
01121
EB6205
01121
EB4715
73138
91-77-0
301·0471·00
11 8-3568-00
Serial/Model No.
Eft
Dscont
Name & Description
RES.,FXD,FILM:1.10HM,S%,2W
RES.,FXD,CMPSN:27K OHM,S%,0.50W
RES.,VAR,NONWIR:2K OHM,20%,0.50W
(SMALL CIRCUIT BOARD ONLY)
RES.,FXD,CMPSN:62 OHM,5%,0.SOW
(PART NUMBER NOT AVAILABLE)
ASR109
ASRt10
ASR110
ASR110
ASR111
ASR112
11 8-3343-00
301-0273-00
311-1S62-00
ASR113
A5R115
A5R116
A5R116
A5R116
A5R117
301·0471·00
118-3344-00
118-3432-00
311.1S55-00
11 8-334S-00
RES.,FXD,CMPSN:470 OHM,5%,0.SOW
RES.,FXD,WW:33 OHM,5%,5W
RESISTOR:1.30HM,0.5W,5%
RES.,VAR,NONWIR:100K OHM,20%,0.5W
(SMALL CIRCUIT BOARD ONLY)
RES.,FXD,WW:51 OHM,S%,5W
ASR118
A5R119
A5R120
A5R121
A5R122
A5R122
315-0100-00
315-0150-00
31S-0100-00
31 5-0150-00
311-1562·00
315·0102-00
RES.,FXD,CMPSN:10 OHM,5%,0.25W
RES.,FXD,CMPSN:1S OHM,S%,0.2SW
RES.,FXD,CMPSN:10 OHM,5%,0.25W
RES.,FXD,CMPSN: 15 OHM,5%,0.25W
RES.,VAR,NONWIR:2K OHM,20%,0.50W
RES.,FXD,CMPSN:1 K OHM,S%,0.25W
01121
01121
01121
01121
73138
01121
CB100S
CB1S0S
CB1005
CB1505
91·84-0
CB102S
ASR126
A5R126
A5R142
A5R142
A5R201
A5R203
311.1222-00
32997
3386F-T04-101
32997
3386F. T04-1 01
31 S-01 01-00
31S-0470-00
RES.,VAR,NONWIR:100 OHM,20%,0.SOW
(SMALL CIRCUIT BOARD ONLY)
RES.,VAR,NONWIR:100 OHM,20%,0.50W
(SMALL CIRCUIT BOARD ONLY)
RES.,FXD,CMPSN:100 OHM,5%,0. 25W
RES.,FXD,CMPSN:47 OHM,S%,0.25W
01121
01121
CB1015
CB4705
301-0101·00
31S-0101-00
301-0101-00
31S-0101-00
315-0101-00
301·0621-00
RES.,FXD,CMPSN:100
RES.,FXD,CMPSN:100
RES.,FXD,CMPSN:100
RES.,FXD,CMPSN:100
RES.,FXD,CMPSN:100
RES.,FXD,CMPSN:620
01121
01121
01121
01121
01121
57668
EB1015
CB101S
EB1015
CB1015
CB101S
NTR501 E620E
ASR20S
ASR205
ASR207
A5R207
ASR208
A5R209
4170 INSTRUCTION
301·0620-00
311·1222-00
OHM,5%,0.50W
OHM,5%,0. 2SW
OHM,5%,0.SOW
OHM,S%,O. 2SW
OHM,5%,0. 25W
OHM,5%,0.SOW
15-15
REPLACEABLE ELECTRICAL PARTS
Name & Description
Mfr
Code
Mfr Part Number
315-0102-00
315-0102-00
301-0151-00
315-0151-00
315-0151-00
315-0241-00
RES.,FXD,CMPSN.l K OHM,5%,0.25W
RES.,FXD,CMPSN: 1K OHM,5%,0.25W
RES .. FXD,CMPSN:150 OHM,5%,0.50W
RES.,FXD,CMPSN: 150 OHM.5%,0.25W
RES.,FXD,CMPSN:150 OHM,5%,0.25W
RES .. FXD,CMPSN:240 OHM,5%,0.25W
01121
01121
01121
01121
01121
01121
CB1025
CB1025
EB1515
CB1515
CB1515
CB2415
A5R217
A5R218
A5R219
A5R220
A5R222
A5R223
315-0102-00
315-0102-00
315-0102-00
315-0102-00
315-0681-00
315-0151-00
RES.,FXD,CMPSN:l K OHM,5%,0.25W
RES.,FXD,CMPSN:l K OHM,5%,0.25W
RES.,FXD,CMPSN:l K OHM,5%,0.25W
RES.,FXD,CMPSN:l K OHM,5%,0.25W
RES.,FXD,CMPSN:680 OHM,5%,0.25W
RES .. FXD,CMPSN:150 OHM,5%,0.25W
01121
01121
01121
01121
01121
01121
CB1025
CB1025
CB1025
CB1025
CBB815
CB1515
A5R224
A5R225
A5R226
A5R227
A5R228
A5R229
315-0151-00
315-0820-00
315-0302-00
315-0103-00
315-0681-00
315-0302-00
RES.,FXD,CMPSN: 150 OHM,5%,0.25W
RES .. FXD,CMPSN:82 OHM,5%.0.25W
RES.,FXD,CMPSN:3K OHM,5%,0.25W
RES.,FXD,CMPSN: 1OK OHM,5%,0.25W
RES.,FXD,CMPSN:680 OHM,5%,0.25W
RES .. FXD,CMPSN:3K OHM,5%,0.25W
01121
01121
01121
01121
01121
01121
CB1515
CB8205
CB3025
CB1035
CBB815
CB3025
A5RV101
A5S101
A5S102
A5Tl0l
A5T102
A5T103
118-3347-00
118-3411-00
118-3348-00
118-3412-00
118-3413-00
118-3570-00
RES,V SENSITIVE:
SWITCH:
SWITCH:LlNE SELECT
TRANSFORMER:INDUCTOR,16.0 MHZ
TRANSFORMER:150W
TRANSFORMER:l00W
A5THR10l
118-3346-00
RES.,THERMAL:
Component No.
Tektronix
Part No.
A5R210
A5R211
A5R213
A5R214
A5R215
A5R216
15-16
Serial/Model No.
Elf
Dscont
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
Serial/Model No.
Eft
Dscont
Name & Description
Mfr
Code
Mfr Part Number
A6 CONTROLLER DISK
A6
A6
A6C51
A6C53
80009
119161700
290-0745-00
281-0820-00
CONTROLLER DISK:
(OPTION 03 ONLY)
CAP.,FXD,ELCTLT:22UF, +50-1 0%,25V
CAP.,FXD,CER DI:680PF,10%,50V
54473
05397
ECE-A25V22L
C114K6B1 K1 X5CA
A6R2
A6R3
A6R47
A6R4B
A61F
A61H
315-0101-00
315-0101-00
315-0103-00
315-0563-00
156-0388-03
156-0480-02
RES.,FXD,CMPSN:100 OHM,5%,O. 25W
RES.,FXD,CMPSN:100 OHM,5%,O. 25W
RES.,FXD,CMPSN:10K OHM,5%,O.25W
RES.,FXD,CMPSN:56K OHM,5%,O.25W
MICROCIRCUIT,DI:DUAL D FLIP-FLOP
MICROCIRCUIT,DI:QUAD 2 INP & GATE
01121
01121
01121
01121
07263
01295
CB1015
CB1015
CB1035
CB5635
74LS74A
SN74LS08NP3
A62J
A63A
A63B
A63J
A64A
A64H
156-0405-03
307 -084 7-00
156-0914-02
156-0462-02
156-0153-02
156-1 025-02
MICROCIRCUIT,DI:DUAL RETRIG MONOSTABLE MV
RES NTWK,FXD,FI: 12X220 OHM,12X330 OHM,5%
MICROCIRCUIT,DI:OCT ST BFR W/3 STATE OUT
MICROCIRCUIT,DI:HEX INVERTER,SCREENED
MICROCIRCUIT,DI:HEX INVERTER BUFFER
MICROCIRCUIT,DI:INVERTING QUAD BUS XCVR
07263
01121
01295
01295
27014
01295
9602
314E221331
SN74LS240
SN7414
DMB006
SN74LS242
A65A
A65H
A65J
A66J
A67J
A69A
156-0153-02
156-1025-02
307-0847-00
156-0153-02
156-0385-02
156-1681-00
MICROCIRCUIT,DI:HEX INVERTER BUFFER
MICROCIRCUIT,DI:INVERTING QUAD BUS XCVR
RES NTWK,FXD,FI:12X220 OHM,12X330 OHM,5%
MICROCIRCUIT,DI:HEX INVERTER BUFFER
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:QUAD DIFF LINE DRIVER
27014
01295
01121
27014
01295
34335
DM8006
SN74LS242
314E221331
DM8006
SN74LS04
AM26LS31 DCB
A610A
156-1315-00
MICROCKT,INTFC:QUAD DIFFERENTIAL RECEIVER
34335
AM26LS32
4170 INSTRUCTION
119-1617-00
15-17
REPLACEABLE ELECTRICAL PARTS
Component No,
Tektronix
Part No,
Serial/Model No,
Eff
Mfr
Dscont
Name
& Description
Code
Mfr Part Number
80009
672-1163-00
04222
04222
DG015El04Z
DG015El04Z
56289
51642
56289
04222
04222
04222
5C37Z5U475M050B
400-050-Z5U205M
5C37Z5U475M050B
DG015El04Z
DG015E104Z
DG015E104Z
A7 INTERFACE
A7
A7
A7C3
A7Cl0
283-0421-00
283-0421-00
CKT BOARD ASSY:INTERFACE
(OPTION 45 ONLY)
CAP"FXD,CER 01:0,1 UF, +80-20%,50V
CAP"FXD,CER DI:O,l UF, +80-20%,50V
A7C20
A7C23
A7C26
A7C60
A7C76
A7C100
283-0194-00
283-0212-00
283-0194-00
283-0421-00
283-0421-00
283-0421-00
CAP"FXD,CER
CAP"FXD,CER
CAP"FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
A7C106
A7C116
A7C123
A7C125
A7C126
A7C140
283-0421-00
283-0421-00
290-0755-00
283-0339-00
283-0421-00
283-0421-00
CAP.,FXD,CER DI:0.1 UF, + 80-20%,50V
CAP.,FXD,CER DI:0.1UF,+BO-20%,50V
CAP.,FXD,ELCTLT:1 OOUF, + 50-1 0%, 1OV
CAP.,FXD,CER DI:0.22UF.10%,50V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
04222
04222
55680
72982
04222
04222
DG015El04Z
DG015El04Z
ULA1AOHEA
8131 N075W5R224K
DG015El04Z
DG015El04Z
A7C150
A7C153
A7C170
A7C203
A7C213
A7C226
283-0421-00
290-0755-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXD,CER DI:O.l UF, +80-20%,50V
CAP.,FXD,ELCTLT: 1OOUF, +50-10%,1 OV
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
CAP.,FXD,CER DI:0.lUF,+80-20%,50V
CAP.,FXD,CER 01:0.lUF,+80-20%,50V
CAP.,FXO,CER DI:0.1UF,+80-20%,50V
04222
55680
04222
04222
04222
04222
DG015El04Z
ULA1AOHEA
DG015E104Z
DG015E104Z
OG015El04Z
OG015El04Z
A7C236
A7C250
A7C266
A7C300
A7C303
A7C310
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0204-00
283-0421-00
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXO,CER
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
DI:0.1 UF, + 80-20%,50V
DI:O.OlUF,20%,50V
DI:0.1 UF, +80-20%,50V
04222
04222
04222
04222
96733
04222
OG015El04Z
DG015El04Z
DG015E104Z
DG015El04Z
R2676
OG015E104Z
A7C316
A7C326
A7C333
A7C340
A7C360
A7C370
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
DI:0.1 UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
01:0.1UF,+80-20%,50V
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
04222
04222
04222
04222
04222
04222
DG015E104Z
DG015E104Z
DG015El04Z
DG015E104Z
DG015E104Z
OG015E104Z
A7C403
A7C413
A7C420
A7C426
A7C436
A7C450
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
283-0421-00
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXO,CER
CAP.,FXD,CER
DI:0.1 UF, +80-20%,50V
01:0.1 UF, +80-20%,50V
DI:0.1 UF, +80-20%,50V
01:0.lUF,+80-20%,50V
01:0.lUF,+80-20%,50V
OI:O.lUF, +80-20%,50V
04222
04222
04222
04222
04222
04222
OG015E104Z
OG015E104Z
DG015E104Z
OG015E104Z
OG015E104Z
OG015E104Z
A7C476
A7C506
A7C513
A7C530
A7C536
A7C540
283-0421-00
283-0421-00
283-0421-00
283-0421-00
290-0755-00
283-0421-00
CAP.,FXD,CER 01:0.1 UF,+80-20%,50V
CAP.,FXD,CER 01 :0.1 UF, + 80-20%,50V
CAP.,FXO,CER DI:0.1UF,+80-20%,50V
CAP.,FXO,CER DI:0.1 UF,+80-20%,50V
CAP.,FXO,ELCTLT: 100UF, +50-10%,1 OV
CAP.,FXO,CER DI :0.1 UF, + 80-20%,50V
04222
04222
04222
04222
55680
04222
DG015El04Z
DG015E104Z
DG015E104Z
OG015El04Z
ULA1AOHEA
DG015E104Z
A7C546
A7C556
A7C566
A7C576
A7F606
283-0421-00
283-0421-00
283-0421-00
283-0421-00
159-0114-00
CAP.,FXD,CER DI:O.l UF, +80-20%,50V
CAP.,FXO,CER 01:0.1 UF, +80-20%,50V
CAP.,FXD,CER 01:0.1 UF, +80-20%,50V
CAP.,FXD,CER DI:0.1 UF, +80-20%,50V
FUSE,CARTRIDGE: 1A, 125VAC,FAST-BLOW
04222
04222
04222
04222
71400
OG015E104Z
OG015E104Z
DG015E104Z
OG015E104Z
GFA 1
15-18
672-1163-00
DI:4,7UF,20%,50V
DI:2UF,20%,50V
DI:4,7UF,20%,50V
D.I:0.1 UF, +80-20%,50V
D1:0.1 UF, + 80-20%,50V
DI:O.l UF, +80-20%,50V
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Component No.
A7J106
A7J106
A7J110
A7J110
A7J132
A7J132
A7J160
A7J160
A7J166
A7J166
A7J167
A7J167
Tektronix
Part No.
131-0608-00
131-0608-00
131 -0608-00
131-0608-00
131 -0608-00
131-0608-00
A7J168
A7J166
A7J169
A7J169
A7J205
A7J205
131-0606-00
A7J206
A7J206
A7J216
A7J306
A7J306
A7J320
131 -0569-00
A7J320
A7J321
A7J321
A7J322
A7J322
A7J354
A7J354
A7J376
A7J376
A7Q520
A7R17
A7R16
131-0606-00
131-0569-00
131-2222-00
131 -0608-00
131 -0606-00
131-0606-00
131-0606-00
131 -0606-00
Serial/Model No.
Dscont
Eft
Mfr
Name & Description
Code
Mfr Part Number
22526
47357
22526
47357
22526
47357
TERMINAL,PIN:0.365 L X 0.025 PH BRl GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.365 L X 0.025 PH BRl GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.365 L X 0.025 PH SRl GOLD
(QUANTITY OF 2)
22526
47357
22526
47357
22526
47357
TERMINAL,PIN:0.365 L X 0.025 PH BRl GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.365 LX 0.025 PH BRl GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.46 LX 0.025 SQ
(QUANTITY OF 5)
22526
47357
22526
47357
22526
46263-029
TERMINAL,PIN:0.46 L X 0.025 SQ
(QUANTITY OF 5)
CONN,RCPT,ELEC:CKT BD,34 CONT,MALE
TERMINAL,PIN:0.365 LX 0.025 PH BRl GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.365 LX 0.025 PH BRl GOLD
22526
48283-029
00779
22526
2-66479-1
47357
22526
47357
22526
47357
22526
47357
22526
47357
TERMINAL,PIN:0.365 LX 0.025 PH BRl GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.365 LX 0.025 PH BRl GOLD
(QUANTITY OF 6)
TERMINAL,PIN:0.365 LX 0.025 PH BRl GOLD
(QUANTITY OF 2)
(QUANTITY OF 2)
TERMINAL,PIN:0.365 L X 0.025 PH BRl GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.365 LX 0.025 PH BRl GOLD
(QUANTITY OF 2)
TERMINAL,PIN:0.365 L X 0.025 PH BRl GOLD
22526
47357
151-0190-00
315-0272-00
315-0272-00
(QUANTITY OF 3)
TERMINAL,PIN:0.365 L X 0.025 PH BRZ GOLD
(QUANTITY OF 2)
TRANSISTOR:SILlCON,NPN
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
07263
01121
01121
S032677
CB2725
CB2725
A7R19
A7R20
A7R21
A7R22
A7R23
A7R46
31 5-01 05-00
315-0624-00
315-0121-00
315-0272-00
315-0105-00
31 5-0363-00
RES.,FXD,CMPSN:1M OHM,5%,0.25W
RES.,FXD,CMPSN:820K OHM,5%,0.25W
RES.,FXD,CMPSN:120 OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:1M OHM,5%,0.25W
RES.,FXD,CMPSN:36K OHM,5%,0.25W
01121
01121
01121
01121
01121
01121
CB1055
CB6245
CB1215
CB2725
CB1055
CB3635
A7R47
A7R46
A7R60
A7R61
A7R62
A7R115
31 5-0363-00
315-0272-00
307-0824-00
307-0824-00
307-0650-00
315-0272-00
RES.,FXD,CMPSN:36K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES NTWK,FXD,FI:4,150 OHM,2%,0.3W EACH
RES NTWK,FXD,FI:4,150 OHM,2%,0.3W EACH
RES NTWK,FXD,FI:9,2.7K OHM,5%,0.150W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
01121
01121
01121
01121
32997
01121
CB3635
CB2725
208B151
208B151
431 OR-1 01-272
CB2725
A7R119
A7R120
A7R121
A7R170
A7R205
A7R303
315-0272-00
315-0272-00
315-0624-00
315-0272-00
315-0272-00
315-0272-00
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:620K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
01121
01121
01121
01121
01121
01121
CB2725
CB2725
CB6245
CB2725
CB2725
CB2725
4170 INSTRUCTION
131 -0606-00
15-19
REPLACEABLE ELECTRICAL PARTS
Mfr
Code
Mfr Part Number
RES NTWK,FXD,FI:14,220 OHM,14,330 OHM,2%
RES ,FXD,CMPSN:2.7K OHM,5%,0.25W
RES ,FXD.CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:l K OHM,5%.0.25W
01121
01121
01121
01121
01121
01121
316E221331
CB2725
CB2725
CB2725
CB2725
CB1025
315-0272-00
315-0272-00
315-0511-00
315-0511-00
315-0272-00
315-0272-00
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:510 OHM,5%,O.25W
RES.,FXD,CMPSN:510 OHM,5%,O.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
01121
01121
01121
01121
01121
01121
CB2725
CB2725
CB5115
CB5115
CB2725
CB2725
A7R376
A7R403
A7R426
A7R502
A7R503
A7R510
315-0272-00
307 -0658-00
315-0272-00
315-0330-00
315-0272-00
315-0272-00
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES NTWK.FXD.FI:14.220 OHM,14,330 OHM,2%
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:330HM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
01121
01121
01121
01121
01121
01121
CB2725
316E221331
CB2725
CB3305
CB2725
CB2725
A7R516
A7R520
A7R530
A7R533
A7R573
A7U1
315-0272-00
315-0472-00
315-0272-00
315-0272-00
315-0272-00
156-0388-03
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:4.7K OHM,5%,0.25W
RES"FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
RES.,FXD,CMPSN:2.7K OHM,5%,0.25W
MICROCIRCUIT,DI:DUAL D FLIP-FLOP
01121
01121
01121
01121
01121
07263
CB2725
CB4725
CB2725
CB2725
CB2725
74LS74A
A7U3
A7U6
A7Ul0
A7U16
A7U30
A7U46
156-0798-02
156-1172-01
156-0651-02
156-0145-02
156-0798-02
156-0093-02
MICROCIRCUIT,DI:DUAL 14 TO 1 LINE SEL/MUX
MICROCIRCUIT,DI:DUAL 4 BIT CNTR
MICROCIRCUIT.DI:8 BIT PRL-OUT SER SHF RGTR
MICROCIRCUIT,DI:QUAD 2-INP NAND BFR
MICROCIRCUIT,DI:DUAL 14 TO 1 LINE SEL/MUX
MICROCIRCUIT,DI:HEX INV BUFFER,BURN-IN
01295
01295
01295
01295
01295
27014
SN74LS153
SN74LS393
SN74LSl64(NP3 OR
SN7438
SN74LS153
DM8016
A7U53
A7U60
A7U63
A7U66
A7U70
A7U76
156-0530-02
156-0462-02
156-1111-02
156-0865-02
156-0914-02
156-1412-00
MICROCIRCUIT,DI:QUAD 2-INP MUX.SCRN
MICROCIRCUIT,DI:HEX INVERTER,SCREENED
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
MICROCIRCUIT,DI:OCTAL D-TYPE FF W/CLEAR
MICROCIRCUIT,DI:OCT ST BFR W/3 STATE OUT
MICROCIRCUIT,DI:SGL/DBL DENS FLOPPY DISC
01295
01295
01295
01295
01295
34649
SN74LS157P3
SN7414
SN74LS245JP3
SN74LS273NP3
SN74LS240
D8272A
A7U100
A7U103
A7U106
A7U110
A7U113
A7U116
156-1258-01
156-0385-02
156-0385-02
156-1258-01
156-0798-02
156-0388-03
MICROCIRCUIT,DI:DUAL J-K NEG-EDGE TRIG FF
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:DUAL J-K NEG-EDGE TRIG FF
MICROCIRCUIT,DI:DUAL 14 TO 1 LINE SEL/MUX
MICROCIRCUIT,DI:DUAL D FLIP-FLOP
01295
01295
01295
01295
01295
07263
SN74LS112
SN74LS04
SN74LS04
SN74LS112
SN74LS153
74LS74A
A7U120
A7U123
A7U126
A7U130
A7U133
A7U136
156-1335-00
156-0479-02
156-0651-02
156-1335-00
156-1258-01
156-0541-02
MICROCIRCUIT,DI:DUAL RETRIG RESET MONO MV
MICROCIRCUIT,DI:QUAD 2-INP OR GATE
MICROCIRCUIT,DI:8 BIT PRL-OUT SER SHF RGTR
MICROCIRCUIT,DI:DUAL RETRIG RESET MONO MV
MICROCIRCUIT,DI:DUAL J-K NEG-EDGE TRIG FF
MICROCIRCUIT,DI:DUAL 2 TO 4 LINE DCDR
07263
01295
01295
07263
01295
01295
96LS02
SN74LS32NP3
SN74LSl64(NP3 OR
96LS02
SN74LSl12
SN74LS139NP3
A7U140
A7U143
A7U146
A7U150
A7U153
A7U160
156-0140-02
156-0382-02
156-0481-02
156-0480-02
156-1888-00
156-0385-02
MICROCIRCUIT,DI:HEX BUFFERS W/OC HV OUT
MICROCIRCUIT,DI:QUAD 2-INP NAND GATE
MICROCIRCUIT,DI:TRIPLE 3 INP & GATE
MICROCIRCUIT,DI:QUAD 2 INP & GATE
MICROCIRCUIT,DI:MOS,FLOPPY DISK DATA SEP
MICROCIRCUIT,DI:HEX INVERTER
27014
01295
27014
01295
DM8017NA + IJA +
SN74LSOO
DM74LS11NA+
SN74LS08NP3
01295
SN74LS04
Component No.
Tektronix
Part No.
A7R320
A7R324
A7R325
A7R330
A7R331
A7R336
307 -0658-00
315-0272-00
315-0272-00
315-0272-00
315-0272-00
315-0102-00
A7R351
A7R352
A7R357
A7R358
A7R359
A7R375
15·20
Serial/Model No.
Elf
Dscont
Name & Description
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Mfr
Code
Mfr Part Number
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:OUAD 2 INP & GATE
MICROCIRCUIT,DI:OUAD 2-INP EXCL OR GATE
MICROCIRCUIT,DI:DUAL D FLIP-FLOP
MICROCIRCUIT,DI:DUAL D FLIP-FLOP
01295
01295
01295
01295
07263
07263
SN74LS245JP3
SN74LS244NP3
SN74LS08NP3
SN74LS86
74LS74A
74LS74A
156-0383-02
156-0392-03
156-0865-02
160-2021-00
156-0865-02
156-0985-01
MICROCIRCUIT,DI:OUAD 2-INP NOR GATE
MICROCIRCUIT,DI:OUAD LATCH W/CLEAR
MICROCIRCUIT,DI:OCTAL D-TYPE FF W/CLEAR
MICROCIRCUIT,DI:512 X 8 EPROM,PRGM
MICROCIRCUIT,DI:OCTAL D-TYPE FF W/CLEAR
MICROCIRCUIT,DI:DUAL 5 INPUT NOR GATE,SCRN
01295
01295
01295
80009
01295
04713
SN74LS02
SN74S175NP3
SN74LS273NP3
160-2021-00
SN74LS273NP3
SN74LS260
A7U230
A7U233
A7U236
A7U240
A7U243
A7U246
156-0530-02
156-0383-02
156-0469-02
156-0469-02
156-0479-02
156-1 065-01
MICROCIRCUIT,DI:OUAD 2-INP MUX,SCRN
MICROCIRCUIT,DI:OUAD 2-INP NOR GATE
MICROCIRCUIT,DI:3/8 LINE DCDR
MICROCIRCUIT,DI:3/8 LINE DCDR
MICROCIRCUIT,DI:OUAD 2-INP OR GATE
MICROCIRCUIT,DI:OCTAL D TYPE TRANS LATCHES
01295
01295
01295
01295
01295
34335
SN7 4LS 157P3
SN74LS02
SN74LS138NP3
SN74LS138NP3
SN74LS32NP3
AM74LS373
A7U250
A7U253
A7U260
A7U266
A7U270
A7U273
156-0718-03
160-2020-00
156-1734-00
156-0382-02
156-0388-03
156-0383-02
MICROCIRCUIT,DI:TRIPLE 3-INP NOR GATE
MICROCIRCUIT,DI:16384 X 8 EPROM,PRGM
MICROCIRCUIT,DI:8192 X 8 PSUEDO STATIC RAM
MICROCIRCUIT,DI:OUAD 2-INP NAND GATE
MICROCIRCUIT,DI:DUAL D FLIP-FLOP
MICROCIRCUIT,DI:OUAD 2-INP NOR GATE
01295
80009
SN74LS27
160-2020-00
01295
07263
01295
SN74LSOO
74LS74A
SN74LS02
A7U276
A7UJOO
A7U303
A7U306
A7U310
A7U313
160-2153-00
156-0735-02
156-0382-02
156-1065-01
160-2022-00
156-0956-02
MICROCIRCUIT,DI:HEX 12 INP AOI GATE ARRAY
MICROCIRCUIT,DI:4 BIT BISTABLE LCH,BURN-IN
MICROCIRCUIT,DI:OUAD 2-INP NAND GATE
MICROCIRCUIT,DI:OCTAL D TYPE TRANS LATCHES
MICROCIRCUIT,DI:512 X 8 PROM,PRGM
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
80009
01295
01295
34335
80009
01295
160-2153-00
SN74LS75
SN74LSOO
AM74LS373
160-2022-00
SN74LS244NP3
A7U316
A7U323
A7U326
A7U330
A7U333
A7U336
156-0865-02
156-0994-02
156-0385-02
156-0388-03
156-0385-02
156-0865-02
MICROCIRCUIT,DI:OCTAL D-TYPE FF W/CLEAR
MICROCIRCUIT,DI:8 INPUT DATA SEUMUX
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:DUAL D FLIP-FLOP
MICROCIRCUIT,DI:HEX INVERTER
MICROCIRCUIT,DI:OCTAL D-TYPE FF W/CLEAR
01295
01295
01295
07263
01295
01295
SN74LS273NP3
SN74LS151NP3
SN74LS04
74LS74A
SN74LS04
SN74LS273NP3
A7U340
A7U346
A7U350
A7U360
A7U363
A7U370
156-0434-00
156-1111-02
156-1428-02
156-0140-02
156-0866-02
160-2018-04
MICROCIRCUIT,DI:8 X 16 I/O PROCESSOR,SCRN
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
MICROCIRCUIT,DI:CLOCK GENERATOR & DRIVER
MICROCIRCUIT,DI:HEX BUFFERS W/OC HV OUT
MICROCIRCUIT,DI:13 INP NAND GATES,SCRN
MICROCIRCUIT,DI:16384 X 8 EPROM,PRGM
01295
34649
27014
80009
80009
SN74LS245JP3
OD8284A
DM8017NA+/JA+
156-0866-02
160-2018-04
A7U370
A7U376
A7U376
A7U400
A7U406
A7U410
160-2015-00
160-2019-04
160-2017 -00
156-1065-01
156-0865-02
156-0914-02
MICROCIRCUIT,DI:16384 X 8 EPROM,PRGM
MICROCIRCUIT,DI:16384 X 8 EPROM,PRGM
MICROCIRCUIT,DI:16384 X 8 EPROM,PRGM
MICROCIRCUIT,DI:OCTAL D TYPE TRANS LATCHES
MICROCIRCUIT,DI:OCTAL D-TYPE FF W/CLEAR
MICROCIRCUIT,DI:OCT ST BFR W/3 STATE OUT
80009
80009
80009
34335
01295
01295
160-201 5-00
160-2019-04
160-2017 -00
AM74LS373
SN74LS273NP3
SN74LS240
A7U413
A7U416
A7U420
A7U423
A7U426
A7U430
156-091 4-02
156-0865-02
156-0111-02
156-0480-02
156-0480-02
156-0385-02
MICROCIRCUIT,DI:OCT ST BFR W/3 STATE OUT
MICROCIRCUIT,DI:OCTAL D-TYPE FF W/CLEAR
MICROCIRCUIT,DI:BCD TO DEC DCDR/DRVR,SCRN
MICROCIRCUIT,DI:OUAD 2 INP & GATE
MICROCIRCUIT,DI:OUAD 2 INP & GATE
MICROCIRCUIT,DI:HEX INVERTER
01295
01295
01295
01295
01295
01295
SN74LS240
SN74LS273NP3
SN74145NP3
SN74LS08NP3
SN74LS08NP3
SN74LS04
Component No.
Tektronix
Part No.
A7U163
A7U165
A7U170
A7U200
A7U203
A7U206
156-1111-02
156-0956-02
156-0480-02
156-0381-02
156-0388-03
156-0388-03
A7U210
A7U213
A7U216
A7U220
A7U223
A7U226
4170 INSTRUCTION
Serial/Model No.
Dscont
Eft
Name & Description
15-21
REPLACEABLE ELECTRICAL PARTS
Component No.
'Tektronix
Part No.
Mfr
Code
Mfr Part Number
A7U433
A7U436
A7U446
A7U450
A7U453
A7U456
156-0469-02
156-0480-02
156-0956-02
156-1111-02
156-1065-01
156-0956-02
MICROCIRCUIT,DI:3/8 LINE DC OR
MICROCIRCUIT,DI:QUAD 2 INP & GATE
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:OCTAl BUS TRANSCEIVERS
MICROCIRCUIT,DI:OCTAl 0 TYPE TRANS LATCHES
MICROCIRCUIT,DI:OCTAl BFR W/3 STATE OUT
01295
01295
01295
01295
34335
01295
SN74LS138NP3
SN74LS08NP3
SN74LS244NP3
SN74lS245JP3
AM74LS373
SN74LS244NP3
A7U460
A7U463
A7U466
A7U470
A7U473
A7U476
156-0956-02
, 56-0865-02
156- 1273-0 1
160-2143-00
156-0956-02
, 56-0866-02
MICROCIRCUIT,DI:OCTAl BFR W/3 STATE OUT
MICROCIRCUIT,DI:OCTAL OoTYPE FF W/CLEAR
MICROCIRCUIT,DI:8 BIT EQUAL TO COMPTR,SCRN
MICROCIRCUIT,DI:HEX 12 INP AOI GATE ARRAY
MICROCIRCUIT,OI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:13 INP NAND GATES,SCRN
01295
01295
80009
80009
01295
80009
SN74LS244NP3
SN74lS273NP3
156-1273-0 1
160-2143-00
SN74LS244NP3
156-0866-02
A7U500
A7U503
A7U506
A7U510
A7U513
A7U516
156-0914-02
156-0145-02
156-0145-02
156-0145-02
156-0645-02
156-0915-02
MICROCIRCUIT,DI:OCT ST BFR W/3 STATE OUT
MICROCIRCUIT,DI:QUAD 2-INP NAND BFR
MICROCIRCUIT,DI:QUAD 2-INP NAND BFR
MICROCIRCUIT,DI:QUAD 2-INP NAND BFR
MICROCIRCUIT,DI:HEX INV ST NAND GATES,SCRN
MICROCIRCUIT,DI:9 BIT ODD/EVEN PARITY GEN
01295
01295
01295
01295
01295
80009
SN74LS240
SN7438
SN7438
SN7438
SN74LS14
156-0915-02
A7U520
A7U523
A7U526
A7U530
A7U533
A7U536
156-0651 -02
156-0956-02
156-0145-02
156-0388-03
156-0382-02
156-1427 -01
MICROCIRCUIT,DI:8 BIT PRL-OUT SER SHF RGTR
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:QUAD 2-INP NAND BFR
MICROCIRCUIT,DI:DUAL 0 FLIP-FLOP
MICROCIRCUIT,DI:QUAD 2-INP NAND GATE
MICROCIRCUIT,DI:BUS CONTROLLER,SCREENED
01295
01295
01295
07263
01295
34649
SN74LS164(NP3 OR
SN74LS244NP3
SN7438
74LS74A
SN74LSOO
QD8288
A7U540
A7U543
A7U546
A7U550
A7U553
A7U556
156-0645-02
156-0435-00
156-0956-02
156-1111-02
156-1111-02
156-0956-02
MICROCIRCUIT,DI:HEX INV ST NAND GATES,SCRN
MICROCIRCUIT,DI:BUS ARBITER,BIPOLAR,SCRN
MICROCIRCUIT,DI:OCTAL BFR W/3 STATE OUT
MICROCIRCUIT,DI:OCTAl BUS TRANSCEIVERS
MICROCIRCUIT,DI:OCTAL BUS TRANSCEIVERS
MICROCIRCUIT,DIOCTAl BFR W/3 STATE OUT
01295
34649
01295
01295
01295
01295
SN74lS14
8289
SN74lS244NP3
SN74LS245JP3
SN74LS245JP3
SN74lS244NP3
A7U560
A7U563
A7U566
A7U570
A7U573
A7U576
156-1065-01
156-1065-01
156-0956-02
156-1065-01
156-0956-02
156-0956-02
MICROCIRCUIT,DI:OCTAl
MICROCIRCUIT,DI:OCTAL
MICROCIRCUIT,DI:OCTAl
MICROCIRCUIT,DI:OCTAl
MICROCIRCUIT,DIOCTAl
MICROCIRCUIT,DIOCTAL
34335
34335
01295
34335
01295
01295
AM74LS373
AM74lS373
SN74LS244NP3
AM74LS373
SN74LS244NP3
SN74LS244NP3
A7Y13
119-1408-00
OSC,XTAL ClOCK:16MHZ,0.01%
OOOIZ
XO-33B16
15·22
Serial/Model No,
Eft
Dscont
Name & Description
0 TYPE TRANS LATCHES
D TYPE TRANS LATCHES
BFR W/3 STATE OUT
0 TYPE TRANS LATCHES
BFR WI3 STATE OUT
BFR WI3 STATE OUT
4170 INSTRUCTION
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
Serial/Model No.
Eft
Dscont
Name & Description
Mfr
Code
Mfr Part Number
01121
316E221331
01121
316E221331
05574
80009
000201-5440
131-1606-01
80009
214-0579-00
A8 LINE TERMINATOR
A8
A8
ABJl
ABR10
011-0090-00
131-3142-00
307 -0658-00
TERMN,LlNE:
(OPTION 45 ONLY)
CONN,RCPT,ELEC:CKT BD,EDGE MNT,50 CONTACT
RES NTWK,FXD,FI:14,220 OHM,14,330 OHM,2%
ABR20
307 -0658-00
RES NTWK,FXD,FI:14,220 OHM,14,330 OHM,2%
A9 LOGIC EXTENDER
A9
670-5291-XX
CKT BOARD ASSY:LOGIC EXTENDER
A9
A9J611
A9J612
131-1346-00
131-1606-01
(NOT AVAILABLE,USE 067-1005-00)
CONNECTOR,RCPT,:40/80 DOUBLE ROW
CONNECTOR,RCPT,:W/22·44 CONTACTS
A9TP1-BO
A9TPl-80
4170 INSTRUCTION
214-0579-00
TERM,TEST POINT:BRS CD PL
(ALL TEST POINTS ARE THE SAME)
15-23
REPLACEABLE ELECTRICAL PARTS
Component No.
Tektronix
Part No.
Serial/Model No.
Eft
Dscont
Name & Description
Mfr
Code
Mfr Part Number
82877
13511
WR2A1
31-279
CHASSIS PARTS
81001
J3005
15-24
119-0026-00
131-0955-00
FAN,AXIAL:1.500 X 4.750 INCH,WHISPER
CONN,RCPT,ELEC:8NC,FEMALE
4170 INSTRUCTION
Section 16
DIAGRAMS AND SCHEMATICS
Symbols and Reference Designators
Electrical components shown on the diagrams are in the following units unless noted otherwise:
Capacitors = Values one or greater are in picofarads (pF).
Values less than one are in microfarads (p. F).
Resistors
=
Ohms (0).
Graphic symbols and class designation letters are based on ANSI Standard Y32.2-1975.
Logic symbology is based on ANSI Y32.14-1973 in terms of positive logic. Logic symbols depict the logic function performed and may
differ from the manufacturer's data.
Abbreviations are based on ANSI Y1.1-1972. Other ANSI standards that are used in the preparation of diagrams by Tektronix, Inc., are:
Y14.15,1966
Y14.2, 1973
Y10.5, 1968
Drafting Practices.
Line Conventions and Lettering.
Letter Symbols for Quantities Used in Electrical Science and Electrical
Engineering.
The following prefix letters are used as reference designators to identify components or assemblies on the diagrams.
A
AT
B
BT
C
CB
CR
DL
DS
E
F
FL
H
Assembly, separable or repairable
(circuit board, etc.)
Attenuator, fixed or variable
Motor
Battery
Capacitor, fixed or variable
Circuit breaker
Diode, signal or rectifier
Delay line
Indicating device (lamp)
Spark Gap, Ferrite bead
Fuse
Filter
HR
HY
J
K
L
M
P
Q
R
RT
Heat dissipating device (heat sink,
heat radiator, etc.)
Heater
Hybrid circuit
Connector, stationary portion
Relay
Inductor, fixed or variable
Meter
Connector, movable portion
Transistor or silicon-controlled
rectifier
Resistor, fixed or variable
Thermistor
S
T
TC
TP
U
V
VR
W
Y
Z
Switch or contactor
Transformer
Thermocouple
Test point
Assembly, inseparable or non-repairable
(integrated circuit, etc.)
Electron tube
Voltage regulator (zener diode, etc.)
Wirestrap or cable
Crystal
Phase shifter
The following special symbols may appear on the diagrams:
Plug to E.C. Board
Strap or Link - - - - - - - - - - - - - - - ,
Modified Component - See
Parts List (depicted in grey,
or with grey outline)
Cam Switch
Closure Chart
(dot indicates
switch closure)
Functional Block
Name
Box Identifies Panel
Controls, Connectors and
Indicators
Plug Index
Hanmonica Type Connector
(Square Pin Connector)
Test Voltage
+12V
Internal
Screwdriver
Adjustment
Pull-up Resistor
Found on Power
Page
SEL Value Selected
at Factory
+5V
14
\~--~~
CQ~12~~~JVVV--~~--_H
3
(-1
__- - - - - - - - -
)~~
JI3~~
--CD 2 0 PQ
Circuit Number_ U314
Circuit Type
74LS74A
AMPL
Coaxial Connector
~~J;"
)
II
H
•
I
_----=------------
-1 2V 3 ......
6~~I~~~nal BlOCk.....".•" •.....•..."•...•..•.•..'•....•..•._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...I~~----------Board Number
ASSEMBLY-SHEET,
BOARO~B70-XXXX-XX
BoardName---~
..
~
VERT leAL
BOARD
Off-page Signal
(Destination Page Number)
A2-3
(3 0 F
3 l ' -___-7-_-
Heat Sink
Decoupled or Filtered
Voltage
Etched Circuit Board
Outlined in Black
Assembly Number
Sheet Number
16-1
1. True High and True Low Signals
Signal names on the schematics are followed by
by -0.
~1
or a -0. A TRUE HIGH signal is indicated by -1, and a TRUE LOW signal is indicated
SIGNAL -1 = TRUE HIGH
SIGNAL -0 = TRUE LOW
2. Cross-References
Schematic cross-references (from/to information) are included on the schematics. The "from" reference only indicates the signal "source,"
and the "to" reference lists all loads where the signal is used. All from/to information will be enclosed in parentheses.
From J350 Pin 6 and
Assembly 1, Sheet 5 '-.....
/
D----1~~
(J350-6,A1-5) X-1:
(-6) V-1
/
-
"
/
.
INPUT SIGNAL
(TRUE HIGH)
xv-a
(A1-5,6,7)
,
OUTPUT SIGNAL
(TRUE LOW)
From Sheet 6
3. Component Number Example
COMPONENT NUMBER
~23
NUMBER
A2A R 123-+'
T T~CHEMATIC
LIE
ASSEMBLY
SUBASSEMBLY
NUMBER (IF USED)
CIRCUIT
NUMBER
CHASSIS-MOUNTED COMPONENTS HAVE NO ASSEMBLY NUMBER
PREFIX--SEE END OF REPLACEABLE ELECTRICAL PARTS LIST.
16-2
To Assembly 1 ,
Sheet 5, etc.
~J
.
..
....
....
....
..
···
K01-1
KDI2I-1
GND
KW'R-12I
+5 VOLTS
I
I
1;
~
~ RESET-12I
~ STEST-12I
~ PIN
"U';~"l,
'"
W
+12VOR ~
CNDOR ~
GND~
+5 VOLTS ~
+12 VOLTS~
SPADE
F
~
P03
I COl
• "2 PROCESSOR
~
~
F"N
'm-~
I
---{:=l
GND SENSE . . . - - .
RESTART-1Zl
J1211
~
E"'
"
'
I
+5 VOLTS
~
~
~
LINE
'5V S E N S E _
~ CH .... SSIS
J1
12!~
>'
>'
)-±.-..-
{:
:
<
•
<
<
<
<
<
g-<
' 1
,1 9-<
121
131
H!
lsi
101
+12 VOLTS
IDe OUTI
9
9
9
; 1 9
51 9
01 9
' 1 9
D:~I
",
9-<
9-<
9-<
9-<
9-<
9-<
g-<
9-<
~
.
,
,
,
1,
10
t=:}_'2
t=:
Bo.11
I
',5
,"
,"
,"
LJ
GND~
o
~
II A 1
J5
1
1
1
'
1
CONN
I
MOTHERBOARD
II
I1J
I
··
··,
pBrlZlN (ALL)
CONN
~GND
0
0
I
I
L
(-1 ,-t)
---------.. WPTCTI2I-l2!
1 ,
. - - - . . WPTCll -21
L.J
~
17,.RO
II
I
50
PIN~
CONN
A3 015K CONTROLLER
Bo.1
P215
r::--l
8-N
L-l
c,';;'I
~~a;;;;o;;;iiiii;lIOiiiiiii;iiI~~I&IiOiiii;II~~~~""""''''''''''''~ ____
NOTES.
%~
I
I
I
I
I
I
'12VDR
: : ~ ~( 7"-~ ~~~DR
~
iC ~
I A I
..
1
8-N
H
I
+5 VOLTS
L...,
I
I
Ie P~12I ~
pBIIZlN~
P2l2!6
,
~
I I
! I III
I
(ALLl
I I
P2
ItJ
~
.5 VOLTS
+5V SENSE
~}
~
+12 VOLTS
,
7
+5 VOLTS ~
GND
r=~===~~
I ~___-----;;-,I17~1~ ~
5 1
+5 VOLTS ~
~ GND SENSE +t2VDR ~
~ RESTART-1Zl
GNDDR ~
+5 VOLTS
L
I
- - -
~
II
9-2
9-2
?)'~:>-'-'- -: !
GNDDR ----.:
~
t=:}
E:E
1
·
pa
+12VDR~
VOLTS
I
L. ~ E~~~3
~~1Iii;j;;OiiiiI
IiiiOOiiiiiIr--I
,
I
,
2 N
2 N
9 2
GND-;
GND
m
GND
POWER SUPPLY MODULE
>0
>7 I
2 N
2 N
~
VOLTS
~
<
~ g-~
PANELlj
4170
17
I
AS POWER SUPPLY BO.
I
15
10
,
,
>'
1 NSTRUHENT
1;
.,
~ +12 VOLTS
~RE""R
~~
12
I,
+5 VOLTS
~GND
~-12
~GND
) 1" I
5 1
+5 VOLTS ~
POl
-12 VOLTS _ _ _ _
"-, "i C-} m { - - ""
81e11211~
,em'
I
p
I
~ +12 VOLTS
~W
III
(ALL)
CONN
)2 1
3 1
I
r~~~~~~ ~,
~~~I
..
"ssy.l,
I
<
~
pg
en
'5EAO"T£ CONTROL
~GNO
a.
P1i211
J3
a0
I"
FRONT PANEL 80.
~ GNDDR
~GND
~ +5 VOLTS
I
1,,-;
I
,,~
~ +12VDR
I,
I
~GND
I
12
L
II
~PIN
CONN
SHUGART DISK DRIVE
~r=iiiiI"""""'"
~
~
r =======',...
I, I
%
P2
I
~
~
I
~ GNDDR
1,
I
I
~GND
~ +5 VOLTS
,; Lp'r'~
L - I---~
~
a-N
+12VOR
1 2
'
P1
~
CONN
SHUG"RT DISK DRIVE so.
J
DI"GRAH:
-+885-11
%
G ===a "
FLEXIBLE DISK DRIVE
~=
BO';
MOTHERBOARD INTERCONNECT
\.
\.
I
~~~.., I""-~~~"""""-"""I
PI (212
(-S)GND
~
Jl1i1J2
':Ol
I
·
·
A'
3 ,
,
,,
(-7) DBB-a ~
[-5) GNO ~
(-7) DB1-12J ~
(-6) GND
(-7)
DB2-a
(-5) GND
(-7) 083-"
C-5)GNO
2'
~
~
~
C ,
o ,
~
~
5 ,
E ,
(-7) 09"'-0 ~
(-51GNO ~
(-7) DBS-a ~
,
F ,
··H'
7 j
~
(-7) DBB-1i1J ~
(-5JGND
~
(-7) 087-3 ~
C-SJGNO
(-5JGND
(-7)
K
~
N.C.~
GND~
(-5) { TERMPWR ~
GND~
(-7) REMOTE ON ~
GNO~
I.'
(-5JGNO
H"'tl1S8 J21
80 PIN -1-170 J5
(£?~~)
.........---(
~ B~O~~N
"TN-0
(-1,2,3,7)
(-5)
m MOTHERBOARD
A-i FD MSIB
L ,
"'
"'
12'
13'
P ,
.
,.,
,
GND
16'
25
,
:~:
17'
U ,
GND~
I.'
MSG-I2f~
GND~
SEL-0~
GND~
C/D-"~
GND~
REQ-"~
GND~
l/O-!ZI~
) ,viii:
INTERFACE BOARD
I
II
N ,
~
~
GND~
GND~
8SY-Ii1J~
GNO~
ACK-Ii1J~
GND~
RST-Ii1J~
,,
,,
J
~
CSP-1i1J ~
I
r------~~~-l
,,
II
28'
X ,
21 ,
~
~
4
~
I
I
I
I
I-N
2 N
2 N
2-N
2-N
2-N
2 N
2 N
Q-N
O-N
l-N
2 N
2 N
2 N
2 N
2 N
2 N
2 N
Q N
O-N
l-N
2-N
2-N
2-N
2-N
2-N
2-N
2-N
Q-N
O-N
l-N
2-N
2-N
2-N
2-N
2-N
2-N
2-N
Q-N
0-N
I-N
2-N
2-N
2-N
2-N
2 N
2 N
2 N
Q N
o N
,~
I
·····
···
··
····,
····
···
···
··
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J427)
Selects either 16K or 32K bit
ROHs, or disables all Processor
board Rm1s.
Normally strap for ONE wait
state. If all the ROMs on the
Processor board are fast enough,
this strap may be changed to
indicate ZERO wait states.
There is one set of straps for
each two-ROM bank of ROMs.
These straps configure the board
for the pin-out of the ROM being
used. See Figure A-2.
BLCK Source (W455
and \'1456)
Normally strapped to
"on-board." If more than one
Processor board is used in the
system, only one should be
strapped to "on-board;" all
others should be strapped to
"off-board."
Interrupt Level
Straps: (W470)
These Straps define the
interrupt priority levels of the
three different interrupts.
Factory strap settings are:
"host port receiver interrupts"
-- interrupt level 0; "keyboard
interrupts" -- interrupt level
4; "timeout interrupts" and
"timer interrupts" -- interrupt
level 5; and "8087 FPU
interrupts"-- interrupt level 7.
4170 INSTRUCTION
A-3
APPENDIX A
STRAP INFORMATION
Table A-1 (cont)
PROCESSOR BOARD STRAPS
: Strap Label
: Definition
Bus Timeout Enable:
(W561 )
Prevents the Processor board
from driving ACK1-0 on a bus
timeout. Used for
multi-processor board systems.
Test 1 and Test 2:
(J150 and J125)
Tests 1 and 2 disable clocks on
the Processor board for ATE
(Automated Test Equipment)
testing.
RS-232C/RS-232A:
(J522 )
This is normally set for
RS-232C. When restrapped for
RS-232A, the SRTS (Secondary
Request To Send) signal is sent
to Pin 11 of the 25-pin RS-232
connector rather than to Pin 19.
Test (J155)
Test disables RST-1 signal to
8086 and 8087 MPU and FPU for
ATE (Automated Test Equipment)
testing.
FPU Interrupt (J61)
Enables 8087 Numerical
Co-processor to actuate
interrupt when an exception
(abnormal or error) condition
occurs.
Mode 0 (J62)
A-4
: Indicates to operating system
: through status register the
: 8087 FPU is present.
4170 INSTRUCTION
APPEnDIX A
STRAP INFORMATION
Table A-1 (cont}
PROCESSOR BOARD STRAPS
: Stra.p Label
: Definition
: rIo de 1 ( J 63 )
: Not used. Do not install strap.
: High RAM Boot (W260) : Not used. Do not install strap.
Battery Grounding
Strap (W10)
Do not use.
~
Installing this strap
with power applied to
the circuit will result in
serious equipment damage.
4170 INSTRUCTION
A-5
APPENDIX A
STRAP INFORMATION
ROM TYPE SELECT
EPROMS
MASKED ROMS
DEVICE
TYPE
SIZE
STRAPPING
DEVICE
TYPE
SIZE
INTEL
2716
2K
6d
6d
1
INTEL
2332
4K
INTEL
2732A-3
INTEL
2758
T.!.
TMS2516
T. !.
TMS2532
•••••
1
6d6d
•••••
TMS4732
1K
6d 6d
1
MOTOROLA
MCM
68A332
4K
2K
6d 6d
1
SYNERTEK
SYC2332
4K
4K
1
4K
•••••
•••••
1
T.!.
STRAPPING
4K
1
6d6d
•••••
d36d
•••••
6d6d
•••••
6d6d
1 • •••••
1
6d63
•••••
(3812)4685-78
Figure A-2. ROM Type Strap Settings.
A-6
4170 INSTRUC TICN
APPENDIX A
STRAP INFORIvlATION
ECC RAM CONTROLLER BOARD STRAPPING
There are 22 different straps, divided into nine functional
groups, on the ECC RAM Controller Board. Both cut straps and
jumper straps are used.
Figure A-3 shows the ECC RAM Controller
Board strap locations and the following paragraphs describe the
nine functional groups.
4170 INSTRUCTION
A-7
APPENDIX A
STRAP INFORMATION
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