12661 90007_Digital_Voltage_Source_Programmer_Interface_Kit_Apr1971 90007 Digital Voltage Source Programmer Interface Kit Apr1971
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MANUAL
for
DIGITAL VOLTAGE
SOURCE PROGRAMMER
INTERFACE KIT H P 12661A
FOR
MODEL 2100 SERIES COMPUTERS
(HP PART NO. 12661-90004)
Microfiche No. 12661-90007
HEWLETT~PACKARD
974 E. Arques Ave., Sunnyvale, California
94086
Printed in U.s.A.
Pub.
APR 1971
CERTIFICATION
'fhe Hewlett-Packard Company certifies that this product was
thoroughly tested and inspected and found to meet its published
specifications when it was shipped from the factory. The HewlettPackard Company further certifies that its calibration measurements are traceable to the U.S. National Bureau of Standards to
the extent allowed by the Bureau's calibration facility.
AMD SYSTEM WARRANTY
All Hewlett-Packard electronic measuring systems, including the instruments, peripherals and software,
which are a part thereof, are warranted to be free from defects in material and workmanship for a period of
90 days. HP will repair or replace, at its option, without charge, any items which prove to be defective
during the warranty period. Warranty service will be performed on-site at the customer's facility in the
United States, Canada, Western Europe, and near other designated HP service facilities, except for locations which are inaccessible or not regularly served by suitable public transportation. On-site 90 day systems
warranty on all HP instruments is in lieu of the one year return-to-HP warranty described in the individual
instrument manuals. No other warranty is expressed or implied. HP is not liable for consequential damages.
PRODUCT SAFETY
STATEMENT OF POLICY
AUTOMATIC MEASUREMENT DIVISION
HEWLETT-PACKARD CO.
The Automatic Measurement Division (AMD) of Hewlett-Packard Company shall comply with safety standards published by the International Electrotechnical Commission (lEC) to the fullest extent possible.
Compliance with these standards is occasionally limited by the appropriateness of existing IEC Publications
to particular conditions found in system and subsystem units and certain special· applications thereof. To
minimize hazards which may occur as a result of insufficient standards, AMD does supplement IEC requirementS with certain nationally recognized United States Safety Standards. These standards principally are,
but shall not be limited to, the National Electric Code (NFP A-1971) and Underwriters Laboratories.
Complex computer-based system and subsystem units utilizing both active and passive electronic equipment
are presumed to contain reasonable hazards that cannot be further moderated at a cost compatible with
user needs. Where such hazards may exist, the safety and health of AMD's customers and employees shall be
protected to the fullest extent possible. This protection may take the form of, but not be limited to
properly placed WARNINGS and USER INSTRUCTIONS.
Unsafe materials, products or conditions resulting from buyer requirements, when these are not considered
as an integral part of the standard AMD product, shall be the sole responsibility of the buyer. This would include, but not be limited to, cables or connector accessories supplied at buyer request and intended to be
used to interface that standard AMD product with other materials and products, or under conditions not
controlled by AMD.
AMD maintains an active safety program to assure compliance with product safety standards to the fullest
extent possible. This program includes, but is not limited to, safety inspections using AMD procedures
AS9S1-0S32-S and AS9SI-0S33-S.
For further information or assistance on safety matters, contact your AMD Contracts Administrator.
12661A
Contents
TABLE OF CONTENTS
Section
I
II
Title
Page
GENERAL DESCRIPTION
1-1.
Introduction •
1-6.
Description
1-7.
Interrupt Capability
1-10.
Software Word Structure .
1-12.
Output Worris
1-13.
Input Word.
·
·······
··· ···· ·····
····
··
····
·····
····
·····
INSTALLATION AND PROGRAMMING
····
2-1.
Installation
·
·
·
·
·
····
·
·
·
2-2.
General
·
·
·
·
·
·
·
·
·
····
·
2-5.
Optional Jumpers
·
·
·
·
······
2-8.
Control Jumpers ·
·
·
·
·
·
Logic Level Jumpers
2-9.
·
· ·
2-11.
Output Jumpers.
········
2-12.
Alarm Jumpers. · ·
·
·
2-14. Programming
· · ·Flag,
· · SFS
· and SFC · · · ·
2-17.
Use of Command,
····
2-21.
Software Control of Interrupt Channel
·
····
2-33.
Program Example.
····
THEORY OF OPERATION.
····
·
3-1.
Introduction
·
····
3-3.
Control Signals ·
····
·
·
·
·
·
3-4.
Initialization
···
3-12.
Interrupt Operation
····
····
3-14.
Timing Mode.
·
·
·
···
·
3-15.
Alarm Mode
3-16.
I/o Interrupt.· ·· · · · · · ·· ·· ·· ·· · · · ·
Computer Power On •
3-22.
·
·· · · · · · · ·
3-26.
Select Code Address.
·
·····
3-28. Input Operations
·
·
·
·
·
·
·
·
·
3-29.
Data Input
······
3-32.
Alarms
··
·
·
3-37. Output Operations· ·
····
·
3-39.
First/Second Word Output
····
3-44.
Second Word Command
····
3-46.
System Clear .
······
·····
u
0
0
0
0
u
u
III
0
0
0
0
0
1-1
1-1
1-1
1-1
1-2
1-2
1n2
2-1
2-1
2-1
2-1
2-2
2-3
2-3
2-3
2-3
2,,4
2-4
2,,7
3-1
3-1
3,,1
3-1
3~2
3-3
3-3
3-3
3-5
3-5
3 .. 6
3-6
3-6
3-7
3-8
3-8
3-8
iii
12661A
Contents
TABLE OF CONTENTS (CONT'D)
Section
IV
Title
Page
..····.······•
·····
······
· ·
···
·
·
·······
·
····
· ···
········
···
····
REPLACEABLE PARTS
····
5-l.
Introduction. ·
···.······
MAINTENANCE
4-l.
Diagnostic Program Description
4-4.
Hardware Requirements •
•
4-6.
Software Requirements.
4-8.
Diagnostic Test Procedure •
4-13. Program Operation
4-15. Program Control
4-18. Error Codes
0
0
V
5-3.
APPENDIX A
Ordering Information
··
12661A DVS PROGRAM CARD DIAGNOSTIC
4-1
4-1
4-1
4-2
4-2
4-4
4-5
4-6
5-1
5-1
5-1
A-l
LIST OF TABLES
Table No.
1-I.
2-l.
4-1.
4-20
iv
Page
Title
DVS Program Card Specifications • . • • .
DVS Program Card 48- Pin Connections
.
Test Connectors. .
. . . . . . • . .
Error Codes . • • • . . . • .
<
•
•
•
•
•
D
•
•
•
•
•
1-4
2<>8
4-3
4':"P
12661A
lliustrations
LIST OF ILLUSTRATIONS
Figure No.
1-1
1-2
2-1
2-2
3-1
3-1
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
Page
Output Word structure. . . . . . . . .
Input Word structure. . . . . . . . . .
Recommended Method of Interconnecting
Power Supplies. . . . . . . . .
Software Control of Interrupt Channel
Logic Input (Sheet 1 of 3)
Logic Control (Sheet 2 of 3) .
Logic Output (Sheet 3 of 3) . . .
Timing Diagram for Error f1f1
Timing Diagram for Error f11
Timing Diagram for Error 02
Timing Diagram for Error 04
Timing Diagram for Error 05
Timing Diagram for Error 10
Timing Diagram for Error 12
Timing Diagram for Error 14
Timing Diagram for Error 16
Timing Diagram for Error 17
Timing Diagram for Error 34
Timing Diagram for Errors 35 through 44
Set Control Timing Diagram . . .
Mode Assignment Timing Diagram
DVS Program Card Parts Location
1-2
1-3
. .
2-9
2-10
3-9
3-10
3-11
4-11
4-12
4-12
4-13
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
v/vi
Section I
12661A
SECTION I
GENERAL DESCRIPTION
1-1.
INTRODUCTION.
1-2.
The HP 12661A Digital Voltage Source (DVS) Interface Kit provides
an interface between Hewlett-Packard Computers and Hewlett-Packard Digital
Voltage Sources or other suitable instruments that can utilize the Card's output bit structure.
1-3.
The DVS Program Card uses one I/O slot and address and can address
up to eight peripheral devices (with octal addresses 0 through 7) in random
sequence. The Card will monitor the eight peripheral devices noting the status
of each one and provide the computer with an alarm interrupt, if one should
fail.
1-4.
The standard HP 12661A DVS Interface Kit is wired to interface with
saturating (high-level) circuits. The HP 12661A, Option 01 DVS Interface Kit
is wired with optional jumpers to interface with non-saturating (low-level) IC
logic levels. Input and qutput specifications for both versions are listed in
Table 1-1.
1-5.
The HP 12661A DVS Interface Kit consists of the following components:
a. DVS Program Card (HP Part No. 12661-6001 for standard kit) or
(HP Part No. 12661-6002 for Option 01).
b.
48-Pin Connector Assembly (HP Part No. 02116-6178).
c.
Diagnostic Program Tape (HP Part No. 20436A).
1-6.
DESCRIPTION.
1-7.
INTERRUPT CAPABILITY.
1-8.
The DVS Program Card will recognize two modes of interrupt from the
peripheral devices it is programming. One interrupt mode is called Timing
(Flag) and sets the Flag Buffer FF. The DVS Program Card is assigned, by
software, to recognize interrupts from the Flag line. Up to eight peripherals
can be parallel connected to the Flag input. This means the DVS Program
Card could cause an interrupt whenever anyone of the peripherals has completed the instructions given to it by the computer.
1-1
12661A
Section I
1-9.
The second interrupt mode is called Alarms and sets the Alarm Buffer
FF. The DVS Program Card is assigned, by software, to recognize interrupts
from the Peripheral Status lines. The Status lines are jumpered to an OR gate
that can cause an interrupt if one of the Status lines goes down. Program examination of the eight Peripheral Status inputs (see Figure 1-2) will determine
the faulty unit only if the unit remains faulty. If the peripheral that caused the
alarm returns to normal, the Status Bits return to normal.
1-10.
SOFTWARE WORD STRUCTURE.
1-11. The DVS Program Card permits transfer of data between the HP Computer and peripheral devices. Two words are set by the computer for data or
control output. The first word contains 16-bits and the second word, 8-bits.
One II-bit word is used to transfer data from the DVS Program Card to the
Computer.
1-12. OUTPUT WORDS. Figure 1-1 shows the bit structure of the two output
words. The first 3-bits of the second word (0 through 2) are converted by the
DVS Program Cardto enable a device command line. These bits are decoded bya
4 Line (BCD) to 10 Line (decimal) converter which activates one of eight Command lines. Bit 7 of the second word is called a System Clear Bit and is activated when the computer is initially turned on. It is also possible to activate
the System Clear bit if one of the peripheral devices fails. See Section III,
System Clear for details.
1st
word
II""
"~"""'I
15: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 '11
,I II
.
2nd
word
I
76 5 I 4 I 32 I 1 I ~
System
Clear
I
~
Command and Line
Address, decoded to
one of eight line s.
Figure 1-1. Output Word Structure
1-13.
INPUT WORD. Figure 1-2 shows the bit structure of the input word.
a. Bits 0 through 7 are input status bits (I-bit per device) which show
peripheral device status but do not have storage capabilities.
b.
Bits 8 through 12 are not used.
1-2
12661A
Section I
c. Bit 13 is the mode of interrupt requested (see Paragraph 1-8). A "0"
indicates the Alarm mode. A "1" indicates the Timing (Flag) mode.
d. Bit 14 is the System Clear Command Status. A "0" indicates the
Clear Command is OFF. A "1" indicates the Clear Command is ON.
e. Bit 15 is the interrupt mode that has taken place. A "0" indicates
the Alarm mode. A "1" indicates the Timing (Flag) modeo
Not
, - -_
_Aused
...._ _.....
Mode Request FF Status
~--::-PeriPheral
Clear System Command Status
Status Bits
"'--- Mode Control FF Status
Figure 1-2. Input Word Structure
1-14. The DVS Program Card contains both a Mode Request FF (bit 13) and
a Mode Control FF (bit 15). The status of bits 13 and 15 correspond to the
state of these FF's. The Mode Request FF can differ from the Mode Control
FF when an interrupt is generatedo For example; the Alarm mode has been
previously set and you decide to change to Timing (Flag) mode. During this
mode change a peripheral fails before the change is completed. The Mode
Request FF would be set and the Mode Control FF would be reset. The mode
of interrupt would not change to Timing (Flag) until the Alarm was cleared or
recognized. If the peripheral fails during the transition from Timing (Flag)
mode to Alarm mode, the failure will set the Alarm Buffer FF which will cause
an interrupt as soon as the mode is changed to Alarm.
1-3
12661A
Section I
Table 1-1. DVS Program Card Specifications.
PERIPHERAL DEVICE
INTERFACE LEVELS
AND CODING
Level
Coded Data
Logic
Flag
+V
OV
o
False
True
Not Busy
Busy
OUTPUT CmCUITS
HP 12661A
NPN, emitter grounded, collector thru 22K
ohms to +12V. Maximum current to ground
18 mAo
HP 12661A,
NPN, emitter grounded, collector thru 22K
ohms to +4. 5V. Maximum current to ground =
18 mAo
Option 01
1
INPUT CmCUITS
HP 12661A
Open or +5. 5V to +12V = +V (False)
Short or -IV to +2. 8V = OV (True)
HP 12661A, Option 01
Open or +2. 5V to +5V
Short or -IV to +lV
CURRENT
REQUmEMENTS
1. 42 A
137 mA
60 mA
14 mA
=
=
+V (False)
= OV (True)
(+4.5V)
(+12V)
( -2V)
( -12V)
DIMENSIONS
Width
7-3/4 inches (196.8 mm)
Length
8-11/16 inches (220.7 mm)
WEIGHT
Net (Card)
10.5 oz.
298 gm.
Shipping (Kit)
4 Ibs.
1. 8 kg.
1-4
12661A
Section II
SECTION II
INSTALLATION AND PROGRAMMING
2-1.
INSTALLATION.
2-2.
GENERAL.
2-3.
Since the DVS Program Card is designed for use with several different
peripheral devices, an interconnecting cable must be prepared for your particular application. Use the 48-pin Connector Kit furnished and wire your
cable using Table 2-1 as a guide. If more than one peripheral is to be interfaced with this card, special attention must be given to the distribution of the
individual lines as well as the common lines. Figure 2-1 shows one method
that can be used to interconnect up to eight power supplies with the DVS Program Card.
2-4.
Install the card in the computer as follows:
a.
Turn off computer power.
b.
Open the computer for access to the I/O cards.
c. Plug the DVS Program Card into the I/O slot assigned for the
particular computer system.
d. Pass the interconnecting cable through the slot in the computer
and up to the card. Slide the 48-pin connector onto the card and close
the computer.
2-5.
OPTIONAL JUMPERS.
2-6.
The DVS Program Card contains optional jumpers that allow field selection of control logic, output logic levels, output bit capacity, and alarm functions.
2-7.
As shipped from the factory for use with both the 12661A and 12661A,
Option 01 DVS Interface Kit; the DVS Program Card jumpers are in place or
removed as listed below.
Control Jumpers
(Figure 3-1. Sheet 2, in place as shown)
W1
W2
W4
W5
W3
W6
2-1
Section II
12661A
Logic Level Jumpers
(Figure 3-1. Sheets 1, 2, & 3)
W7
WS
W9
WI0
12661A
:i!)
12661A, Opt. 01
WI0A
Output Jumpers
(Figure 3-1. Sheet 3, removed as shown)
Wll
W12
W13
W14
Alarm Jumpers
(Figure 3-1. Sheet 1, in place as shown)
MC74 0 through 7
MC73 A through D
2-S.
CONTROL JUMPERS. These jumpers are for special applications of
the card and are not normally changed from standard. Their functions are:
ao
WIA. This jumper used in conjunction with Wl1, W12, W13, and W14.
In position WIA, set side of Command Control FF is used as DVS Program
Card command line.
b. W2A and W3A. These jumpers reverse the output of the Timer FF
(MC77). Used when peripheral device Flag to card is high when busy and low
when not busy.
c. W4A, In this position the jumper will inhibit STF and CLF signals
to the Flag Buffer and Alarm Buffer FF' s, It will also inhibit 101 and 100
signals to the Mode Request FF and would normally be used in conjunction
with W5 and W6 to hard wire card for either Alarm or Timing (Flag) mode
interrupts.
d. W4 replaced by R7l (470Q resistor) to +4. 5V enables STF and CLF
signals to both Flag Buffer and Alarm Buffer FF's at all times. Use of this
resistor also enables 101 and 100 signals at all times but is nullified by ,W5
and W6.
e. W5 and W6. With W6Ainposition and W5 replaced by R72 (4700 resistor)
to +4. 5V, card is hardwired in the Alarm mode of interrupt. With W5A in position and W6 replaced by R73 (470Q resistor) to +4. 5V, card is hardwired in the
Timing (Flag) mode of interrupt.
2-2
Section II
12661A
2-9.
LOGIC LEVEL JUMPERSc These jumpers are in position W7, W8, W9
and W10 on the 12661-6001 DVS Program Card used in the 12661A DVS Interface Kit. These jumpers are in position W7A, W8A, W9A, and W10A on the
12661-6002 DVS Program Card used in the 12661A, Option 01 DVS Interface
Kit.
NOTE
W10 and W10A is the same position (-2V).
2-10. When jumpers W7, W8, W9, and W10 are moved to the "B" position, -12V
is applied to the inverter circuits. This requires replacing all inverter NPN
transistors with PNP transistors and reversing all associated diodes.
2-11. OUTPUT JUMPERS. These jumpers are not normally used. They can
be installed for 24 bits output to a single peripheral device. When these jumpers are installed, the Address Decoder (MC14) must be removed from the card.
a.
W11 becomes Bit 0 in second output word (see Figure 1-1).
b.
W12 becomes Bit 1 in second output word.
c.
W13 becomes Bit 2 in second output word.
d. W14 connects output of Command Control FF to Command 5 output.
It may be necessary to move W1 to its A position for correct polarity of command
line to peripheral device.
2-12. ALARM JUMPERS. Eight jumpers numbered 0 to 7 (MC74) are used to
connect Alarm interrupt capability to each Peripheral Status input bit. If an
Alarm interrupt is not desired on a particular input, remove the jumper. With
the Alarm interrupt circuits disconnected, the status of all peripheral devices
can still be monitored through program examination of the Peripheral Status
inputs.
2-13. Four jumpers lettered A to D (MC73) are used to form an OR circuit
that will set the System Clear bit whenever an Alarm condition occurs. Jumpers 0 to 3 must be in place for this option.
2-14.
PROGRAMMlNG.
2-15. In this text, the initials PSI will be used to represent
the DVS Program Card.
th~
select code of
2-16. Since the card is program selected by only one select code, simultaneous
input and output operations cannot be performed. The card plugs into any of the
interface card input/output (I/O) slots of the computer and assumes the lower
select code of that slot.
2-3
Section II
12661A
2-17.
USE OF COMMAND, FLAG, SFS, AND SFC.
2-18. When outputting a program to a peripheral device, two words are required. The card is first initialized by CLC PSI or CLC~. The structure
of the two words has been previously specified in Section I, Figure 1-1. After
outputting the second word, the following events occur in the sequence given;
each one depending upon the event preceding it.
NOTE
Use of CLC ~ will affect other devices being operated
under interruptD
a.
The Command line to the appropriate peripheral device goes true (OV).
bo
The peripheral device starts its assignment.
c.
The peripheral Flag goes Busy (OV)o
d.
The Command line to the peripheral device goes false (+V).
NOTE
If the peripheral does not have a "Flag", the Command
line can be cleared with C LC PSI.
e.
Peripheral device finishes assignment and settles or "times out".
f.
The peripheral Flag goes Not Busy (+V).
2-19. If an SFS instruction is executed, the next instruction will be skipped
only if the device Flag line is high (+V).
2-20. If an SFC instruction is executed, the next instruction will be skipped
only if the device Flag line is ground (OV).
NOTE
SFS and SFC are software commands whose only function
is to check status of peripheral device Flag. STF or CLF
commands do not enable or disable SFS and SFC commands.
2-21.
SOFTWARE CONTROL OF INTERRUPT CHANNEL (See Figure 2-2).
2-22. Figure 2-2 is a representation of Software control of the Interrupt Channel. The main points of Figure 2-2 are; how the DVS Program Card is assigned
2-4
12661A
Section IT
to the Timing or Alarm mode of interrupt; and once the assignment is made
why further instructions have "NO EFFECT" on the interrupt channel.
2-23. To disable the DVS Program Card interrupt capability prior to interrupt mode assignment, a CLC PSI or CLC 0 command is given. If an interupt request occurs during assignment, the card will not interrupt the eomputer.
The interrupt request will be stored in Flag or Alarm Buffer FF' s. Once the
interrupt mode is assigned, the stored interrupt request will cause an interrupt.
2-24. After the interrupt mode is assigned, either Timing or Alarms, an STF
PSI command followed by STC PSI will cause an immediate interrupt. If, instead of the STF PSI command, a CLF PSI command is given, followed by STC
PSI, the Timing or Alarm mode is enabled. Once DVS Card Interrupt is on,
OT A, B PSI or LIA, B/MIA, B PSI commands have "NO EFFECT" on the interrupt channel. See paragraph 2-33 for a short Example Program.
2-25. The follOWing description follows Figure 2-2 starting with a CLC PSI
or CLC 0 command.
CLC PSI
or
CLC 0
Interrupt control FF is cleared which disables the
interrupt capability and enables the mode of interrupt assignment.
2- 26. At this point a decision must be made on which mode of interrupt is
desired.
OTA/B PSI
or
LIA/B PSI
or
MIA/B PSI
Mode Request FF is set which assigns the interrupt
channel to a Timing Mode.
Mode Request FF is cleared which assigns the interrupt channel to an Alarm Mode.
2-27. After selecting either the Timing mode or Alarm mode, another decision may be made on requesting an immediate interrupt by setting the Flag
or Alarm Buffer FF's (STF PSI), or, clearing any previous interrupt requests
(CLF PSI). A third choice is possible which is not shown on Figure 2-20 The
command STC PSI can be given which will either cause an immediate interrupt
or enable the interrupt mode depending on the status of the Flag or Alarm Buffer FF's.
STF PSI
Flag or Alarm Buffer FF is set and a Timing or
Alarm interrupt is requested.
The next machine cycle will set the Flag FF.
2-5
Section II
12661A
STC PSI
This instruction will cause an immediate interrupt.
2- 28. If the decision is made to clear any previous interrupt requests, the
Flag or Alarm Buffer FF' s must be cleared.
CLF PSI
This instruction clears the Flag or Alarm Buffer
FF's which erases a Timing or Alarm interrupt
request.
At the same time the Flag and Interlock FF' s are
cleared. If an interrupt request still exists, the
next command (STC PSI) will gate it through.
STC PSI
This instruction enables the Timing or Alarm
interrupt.
2-29. Once the mode of interrupt has been set, the STC command enables the
interrupt and prevents OTA, B PSI or LIA, B/MIA, B PSI commands from
altering the mode. These commands are shown on Figure 2-2 as having "NO
EFFECT". At this point in the program these commands are used to output
or input data between the DVS Program Card and computer.
STC PSI
Interrupt Control FF is set which enables interrupt.
2-30. The next choice of commands, as shown on Figure 2-2, have "NO EFFECT"
on interrupt mode assignment.
OTA/B PSI
or
MIA/B PSI
or
LIA/B PSI
then
STF PSI
or
CLF PSI
At this point in program, used to input or output
data. See Figures 1-1 and 1-2.
No effect on Flag or Alarm Buffer FF's.
The Flag and Interlock FF's are cleared which
closes the interrupt priority string.
The Flag and Alarm Buffer FF' s are not affected.
2-31. If, after assigning the mode of interrupt, an interrupt should occur, it is
not necessary to recycle from CLC PSI. The instruction CLF PSI will clear the
Flag and Interlock FF's which again enables the interrupt. Upon initiation of an
interrupt, the Flag Buffer or Alarm Buffer FF's are cleared and the Interlock
FF is set by the Interrupt Acknowledge (IAK) Signal. The Interlock FF then prevents additional interrupts until cleared by software (CLF, PSI). A CLF PSI
instruction will not clear the Word Sequence FF's. Therefore, a new first word
cannot be programmed.
2-6
Section II
12661A
2-32. To clear the Word Sequence FF's it will be necessary to recycle from
CLC PSI. The DVS Program Card will now recognize the next OTA/B as afirst
word.
2-33. PROGRAM EXAMPLE.
2-34. The following sample program illustrates input and output programming through the DVS Program Card using HP Assembler Language.
Label
NOTE:
Operand
Explanation
CLC PSI, C
Enable interrupt assignment and initialize.
LIA PSI
Assign interrupt channel to alarms.
LDA WDI
Load A and B registers with 1 st and 2nd
LDB WD2
word output data from memory storage.
JSB OUTPT
Jump to output subroutine.
If LIA PSI in the above program were replaced by OTA PSI,
the interrupt channel would be assigned to timing.
OUTPT
NOP
Entry point OUTPUT subroutine.
CLC PSI
Initialize Word Sequence Counter.
STC PSI
Disable interrupt mode assignment and
Enable interrupt channel.
OTA PSI
Output 1st data word.
OTB PSI
Output 2nd data word and command
external device to accept the data.
SFS PSI
Is external device busy?
JMP
* -1
JMP OUTPT, I
Yes. Jump to previous instruction.
Exit this subroutine.
2-7
Section III
12661A
Table 2-1. DVS Program Card 48-Pin Connections.
Pin
-
Signal
Pin
-
Signal
Input
Word
status
Status
Status
status
Status
0
1
2
3
4
16
T
17
U
19
V
18
S
status 5
Status 6
Status 7
Flag
W
Output (First Word)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
7
D
5
4
K
9
10
L
E
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
11
8
9
10
11
12
13
14
15
M
N
12
R
14
13
P
Output (Second Word)
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 (System Clear)
Command 0
Command 1
F
J
8
6
15
H
2
Command
Command
Command
Command
Command
Command
Ground
2
3
4
5
6
7
C
7
3
A
1
B
BB,AA,Z,Y
24,23, 21,22
2-8
12661A
Section II
48-pin
Connector
Junction
Boxes
DVS
Program
Card
Power
Supply
I/O Cable
50-pin
Amphenol
Connectors
*
Up to 8 power supplies
c an be connected in
this manner.
Eighth power supply
does not require
junction box.
Power
Supply
Power
Supply
*
Figure 2-1. Recommended Method of Interconnecting
Power Supplies.
2-9
12661A
Section IT
The effect of an instruction( XXX PSI
)on a fliP-flOpl
XXXX F F
depends on the status of other flip-flops as shown.
MODE
REQUEST F
MODE
REQUEST F F
CLEARED
SET
r
I
rFLAG F
SET
L__
FLAG F F
CLEARED
I
FLA~E~
L
INTERLOCK
'F F CLEARED
..,
I
FLAG F F
CLEARED
_I
INTERRUPT
Figure 2-2. Software Control of Interrupt Channel
2-10
Seetion III
12661A
SECTION III
THEORY OF OPERATION
3-1.
INTRODUCTION.
3-2.
This section of the Manual is divided into three main parts. Figure 3-1
is the schematic diagram of the DVS Program Card and is divided into three
sheets. Control Signals; refer to Sheet 2: Input Operations; refer to Sheet 1:
Output Operations; refer to Sheet 3. Located within the main parts are other
operations such as Interrupt, Computer Power On, etc. Figure 3-2 is a typical Interrupt System Timing diagram to aid in describing Interrupt Operation.
PSI is used in this text to represent the Select Code of the DVS Program Card.
3-3.
CONTROL SIGNALS.
3-4.
INITIALIZATION.
3-5.
Refer to Sheet 2 of Figure 3-1. The DVS Program Card must be initialized by a C LC instruction with a Select Code of ~~ or with the Select Code
of the interface card. The lOG and Select Code signals gate through MC15 and
MC 16 pin 6 to enable the command gates of the card. Output instructions of
OTA and/or OTB follow to output 24 data bits from the A and/or B registers.
3-6.
When the card is given a CLC instruction through pin 21, Word Sequence
FF1 and FF2 are cleared. The reset output terminal for FF2 (pin 6, MC46)
goes high (+V). This allows the first 100 signal at pin 20 (caused by the first
OT A/B PSI instruction) to be gated through MC46 pin 8 and MC 56 pin 6 to the
Latch inputs of the First Output Word Registers (Sheet 3). This first 100 signal also sets Word Sequence FFI by pulling pin 13 MC36 low (OV) which causes
pin 11 of MC36 to go high. When the 100 pulse returns to its normally low
state, pin 13 of MC36 and pin 12 of MC35 go high. This makes pin 1 of MC46
low, which sets Word Sequence FF2 causing pin 12 of MC46 to go high.
3-7.
After the first OTA/B PSI instruction, both Word Sequence FF's are
set. The second 100 Signal is gated through inverting MC27 pin 11 and MC37
pin 4 to MC46 pin 13. Both inputs (12 and 13) to MC46 are now high which
causes pin 11 of MC46 to go low which causes pin 8 of MC56 to go high. The
second 100 Signal from MC56 pin 8 goes to the Latch inputs of the Second Output Word Registers (Sheet 3). When MC46 pin 11 went low, it pulled pin 12 of
MC65 low which set the Command Control FF.
3-1
12661A
Section III
3-8.
The first 100 signal to the card, as a result of the first OTA/B instruction, latches the First Word Output Storage Register FF's (see Sheet 3).
The first word data (16-Bits) is then available to the peripheral device. The
second 100 signal to the card (second OTA/B instruction) latches the Second
Word Output Storage Register FF's. The second word data (8-Bits) is then
available to the peripheral device and the Address Decoder. The Address
Decoder was enabled when the second 100 signal set the Command Control FF.
The signal from the Command Control FF, together with the address data bits
(second word bits 0, 1, 2 through the Address Decoder), cause a command to
be sent to one of the eight possible peripheral devices.
3-9.
As the commanded peripheral device is accepting data, it will make the
Flag (pin S) low which resets the Command Control FF. When the Command
Control FF resets, the Command line returns to its normally high (off) staten
When the peripheral device completes its operation, the Flag returns to its
normally high (off) state.
3-10.
The second 100 Signal sets the Command Control FF which, in turn,
sets the Status Flag FF (MC77). While the Status Flag is set, MC67 pin 5 is
low which disables the SFS PSI instruction (pin 25). SFS to the DVS Program
Card means skip the next instruction if the peripheral device Flag Line is
high (+V). When the Flag Line goes low, which resets the Command Control
FF, the Status Flag FF remains set. When the Flag returns to its high state,
the Status Flag FF is reset which makes MC67 pin 5 high and enables the SFS
PSI instruction. The Flag Line, in returning to its high state, generates a
pulse through MC67 pin 8 that makes MC55 pin 9 low and sets the Flag Buffer
FF. This would cause a "Timing (Flag) interrupt" if the interrupt system and
channel were enabled and assigned to "Timing".
3-11.
To output additional data to the peripheral devices, the card must receive a CLC PSI or CLC ¢ command to initialize the word sequence FF's. If
the card is not reset with a CLC instruction, then every output instruction
(OTA/B) will cause the card to react as if it were a second 100 signal. Erroneous data could then be received by one of the peripheral devices.
3-12.
INTERRUPT OPERATION.
3-13.
Refer to Figure 3-2. The card will recognize two types of interrupt
from the peripheral device it is programming. One interrupt method is called
Timing (Flag) and sets the Flag Buffer FF. This interrupt may request an
interrupt to the computer program to obtain new data from the computer. The
second interrupt method is called Alarms and sets the Alarm Buffer FF. This
interrupt is a signal to the computer that one of the peripheral devic es has
failed. Program examination of the Status inputs (see Figure 1-2) will determine the faulty unit only if the unit remains faulty. If the peripheral that caused
the Alarm returns to normal, the Status Bits return to normalo
3-2
12661A
Section III
3-14. TIMING MODE. The interrupt channel may be assigned to a "Timing
mode" using the Flag Buffer FF to generate interrupts. A CLC PSI or CLC f:}
instruction pulls MC36 pin 5 low which resets the Interrupt Control FF and
enables the channel assignment. If the Interrupt Control FF is reset, an 100
signal (from OTA/B instruction) will pull MC25 pin 4 low which sets the Mode
Request FF. This makes MC54 pin 2 high which, together with sm (T5) signal and the Flag FF being reset, sets the Mode Control FF. When the Mode
Control FF sets it makes MC25 pin 1 high which allows the Flag Buffer FF to
reset on an IAK (Interrupt Acknowledge) signal. In the reset condition~ a STF
command will set the Flag Buffer FF which pulls pin 9 of MC65 low and sets
the Flag FF. A C L F command will gate through MC 17 pin 3, pull pin 2 of
MC66 low and reset the Flag FF. In this "Timing mode", the Alarm Buffer
FF is disabled from the STF, CLF commands and the Flag FF.
3-15. ALARM MODE. The interrupt channel ma~r be assigned to an "Alarm
mode" using the Alarm Buffer FF to generate interrupts. If the Interrupt Control FF is not set, an 101 signal (from LIA/B., MIA/B instructions) will pull
MC15 pin 11 low which resets the Mode Request FF. This makes MC54 pin 2
low which, together with SIR (T5) signal and the Flag FF being reset, resets
the Mode Control FF. When the Mode Control FF resets, it makes MC35
pin 10 high which allows the Alarm Buffer FF to reset on an IAK signal. In
the reset condition, a STF command will set the Alarm Buffer FF which pulls
pin 9 of MC65 low and sets the Flag FF. A CLF command will gate through
MC17 pin 3, pull pin 2 of MC66 low and reset the Flag FF. In this "Alarm
mode", the Flag Buffer FF is disabled from the STF, CLF commands and the
Flag FF.
3-16. I/O INTERRUPT. To insure that input and output instructions do not
assign the interrupt channel to an incorrect mode., the Interrupt Control FF
must be set by a STC PSI instruction. With the Interrupt Control FF set, pin 6
of MC36 is low which inhibits MC25 pin 13 and MC17 pin 10. This prevents the
101 and 100 signals from changing the Mode Request and Mode Control FF's
which would change the interrupt channel assigpment. The STC command will
also inhibit pins 4,11 and 13 of MC26 and pin 2 of MC15 which will stop the STF,
CLF instructions from changing the Flag Buffer and Alarm Buffer FF's.
3-17,> To generate an interrupt request to the computer, the Interrupt Control
FF must be set by a STC PSI instruction; the I/O Interrupt system must be enabled by a STF 13 instruction (lEN High); the Flag FF and appropriate Buffer FF
must be set. Then if an interface card (device) of higher priority is not requesting an interrupt (PRH line high) the Interrupt Request FF {IRQ-FF} will be set.
3-18. The mQ FF output provides the FLG (Flag) signal through pin 9 MC87
and the mQ signal through pin 13 MC87 to the I/O Address Card. These'two
high signals cause a Service Request Address to be enabled to the computer.
3-3
12661A
Section III
The Flag signal forms an Interrupt signal which is sent to the computer. The
IRQ FF is reset by the ENF signal at time T2 in the computer cycle. This
allows a higher-priority device to request an interrupt. If the Flag FF and
appropriate Buffer FF are still set and no higher-priority devices have requested an interrupt, the IRQ FF will again be set at time T5 (SIR).
3-19. During Interrupt Phase 4, the computer decrements the P-register by
one to ensure that the proper location in the main program will be returned
to after the interrupt is processed. (The P-register was incremented by one
at time T7 of the last machine phase of the main program by the SPC (Step
Program Counter) signal.) Also, the computer places the Service Request
Address (which is always equal to the Select Code of the interrupting device)
from the I/O Address card into the M-register at time T7. This causes the
next instruction to be read from the memory location having the same number as the Service Request Address (Select Code) during the Fetch Phase
(Phase 1). This location in memory is referred to as the "interrupt location"
and is reserved for that particular device. Example: A device specified by
a Select Code of 10 will interrupt to (i. e., cause execution of the contents of)
memory location 00010. At time T3 of Phase 4, the interrupt system is inhibited by the false Enable Service Request Signal until the Fetch Phase follOWing the execution of the instruction at the interrupt location. This prevents
interrupts from occurring until at least one instruction has been executed (exc ept in the case of JMP, I and JSB, I instructio ns) .
3-20. At time T1 of Fetch Phase 1 the I/O Control Card sends an IAK (Interrupt Acknowledge) signal to the DVS Program Card. If the IRQ FF is set,
the IAK signal gates through MC 57 pin 8 and resets the appropriate Flag or
Alarm Buffer FF. Since the set-side output of the Buffer FF is ultimately
applied to MC73, resetting the Buffer FF prevents the setting of the IRQ FF
and causing another interrupt. The IAK signal also sets the Interlock FF by
pulling pin 1 of MC35 low and in so doing, disables the interrupt channel on
the DVS Program Card. The Buffer FF's may now be set without generating
an interrupt. A eLF PSI instruction will clear the Interlock FF and allow
the Buffer FF to initiate another interrupt signal. For the CLF PSI not to
clear the Buffer FF, the Interrupt Control FF must be set with a STC PSI
instruction.
3-21. At time T2, the ENF signal resets the IRQ FF. The computer fetches
the instruction in the interrupt location which will usually be a jump to a subroutine (JSB, I) instruction, although any legal instruction may be placed in the
interrupt location. The contents of the P-register plus one is stored in the
first location (X) of the subroutine. (Since the previous contents of the first
memory location are destroyed when P+1 is stored, the first instruction of the
subroutine should always be a no-operation (NOP) instruction or equivalent. )
The location of the subroutine (X+ 1) is placed in the P- and M-registers, and
the computer resumes normal subroutine operation. Thus, the instruction at
location X+ 1 is the first instruction of the subroutine to be executed. The
3-4
Section III
12661A
contents of the working registers that were in use in the main program should
be stored when entering the subroutine and restored before exit from the subroutine. The exit from the subroutine is made with a JMP, I to location X.
This places the address of the interrupted program instruction in the P- and
M-registers and normal program operation resumes.
3-22.
COMPUTER POWER ON,
3-23. When power is initially applied to the computer, the POPIO(B) and CRS
signals are received by the DVS Program Card from the I/O Control Card.
These signals establish initial conditions for the operation of the Card and
cause the SYSTEM C LEAR signal to appear on the output.
3-24.
The POPIO(B) signal (pin 17) performs these functions:
a.
Clears the Flag FF.
b.
Clears the Flag Buffer FF and Alarm Buffer FF.
c. Clears the Mode Request FF which clears the Mode Control FF and
assigns the interrupt channel to the Alarm mode.
d. Sets all output Storage Buffers to Logic '!on (lOBO is held Low during
this period).
e. ,Sets the SYSTEM CLEAR to a Logic "1" (output low).
3-25.
The CRS (Control Reset) signal (pin 13) performs these functions:
a.
Clears the Interrupt Control FF.
b.
Clears both Word Sequence FF's.
c.
Clears the Command Control FF.
3-26.
SELECT CODE-CARD ADDRESS.
3-27. A program instruction with the Select Code of the DVS Program Card
directs an Input/Output Command to the Card. The proper Select Code provides SCL (Select Code Least Significant Digit) and SCM (Select Code Most
Significant Digit) signals to the Card. These signals are enabled by the 10B(B)
(Input/Output Group Instruction (Buffered)) Signal. Refer to Volume Three of
the Computer Manuals INPUT/OUTPUT SYSTEM OPERATION, Figure 2-3,
to determine the Select Code number for the Interface Card slot used.
3-5
12661A
Section III
3-28.
INPUT OPERATIONS.
3-29.
DATA INPUT.
3-30. See Sheet 1 of Figure 3-1. The Input Storage Register FF's of the
DVS Program Card follow the status of the input lines from the peripheral
device. Each Input Storage Register is automatically set to the state of the
status line during each computer cycle. These input registers account for 8
of the 11 data bits that may be received by the computer from the Card. The
remaining 3 bits are status bits from the Mode Control FF (Bit 15), Mode Request FF (Bit 13), and System Clear (Bit 14).
3-310 The computer accepts data from the Card by an LIA, LIB, MIA, or
MIB instruction. These instructions generate an 101 signal (pin 24, Sheet 2)
which gates through MC17, MC16 pin 12 to MC97 pin 14 which enables the
data bits to the computer.
3-32.
ALARMS
0
3-33c The eight Input Storage Registers may be used to cause an IlAlarm Interrupt" if an alarm condition (peripheral failure) exists on any of the input
status lines. The appropriate alarm jumpers (0-7) to MC74 must be in
placeo When the input status line changes from its high (off) state to its low
(on) state, a pulse is generated through MC75 pin 4 that sets the Alarm Buffer
FF (MC55 pin 4)0 This will generate an Alarm interrupt if the interrupt system and'channel are enabled and assigned to "Alarms".
3-34. Peripheral status 0 line will be used as an example to explain how an
Alarm pulse is generated. When Status 0 line goes low, transistor Q31 turns
off and the input to Input Bit 0 FF (pin 2, MC103) goes high. When the latch
pulse from the sm line is received at pin 13 of MC103 at time T5 in the Computer Cycle, the set output of the FF (Q) goes high. Since the Alarm FF
(MC93) is not set, its reset output (Q) will also be high. These two high outputs will enable the input of MC83 making pin 11 low. If Alarm jumper 0 is
in place, pin 6 of MC74 will be low making pin 8 high. Pin 3 of MC75 is high
and pin 4 goes low. When MC75 pin 4 goes low, it pulls pin 4 of MC55 low
which sets the Alarm Buffer FF.
3-35. After Input Bit 0 FF is set at computer time T5, the input of Alarm 0
FF (pin 2 MC93) is high. The output of Alarm 0 FF will not change, however,
until the latch input (pin 13, MC93) receives a positive pulse from the ENF
line at time T2 in the next computer cycle. This latch pulse causes the reset
output of Alarm 0 FF (Q) to go low which makes the alarm at pin 11 of MC83
high. Since Alarm OFF is now set, the set output (Q)is high and lOBI 0 may be
enabled through MC106 by an 101 pulse from an LIA/B PSIorMIA/B PSI instruction.
3/69
3-6
Section III
12661A
3-36.
Before another Alarm pulse can be generated from the Peripheral
Status 0 line, both fuput Bit 0 FF and Alarm 0 FF must be reset. These FF's
are reset by the input line returning to its normally high state. IT the input
line again goes low, another alarm pulse will be generated beginning at time
T5 and extending to time T2 of the next Computer Cycle.
3-37.
OUTPUT OPERATIONS.
3-38.
Refer to Sheet 3 of Figure 3-1. The output data bits are transferred
from the Computer A or B Register to the DVS Program Card through the
lOBO (I/O Bus Output) lines. The lOBO signal levels are -0. 5V (Logic flOfl) ,
or +2. 5V to +4. 5V (Logic "I"). There are three types of output circuits: First
and Second Word Output Data Storage, Second Word Command Address, and
SYSTEM CLEAR. Each of these circuits will be explained.
3-39.
FIRST/SECOND WORD OUTPUT.
3-40.
First and second word output data storage will be explained using
lOBO 3 as an example. A Logic flO" from lOBO 3 (pin 45) is applied to the
inputs of both the output storage FF's (First Word Latch input = pin 7, MC43,
Second Word Latch input = pin 7, MC33). To transfer the Logic "0" to pin k
(first output word bit 3), a positive going latch pulse must be applied to pin 4
of MC43. To transfer the Logic "0" to pin F (second output word bit 3) a
positive going latch pulse must be applied to pin 4 of MC33.
3-41.
The positive going latch pulses originate from the Word Sequence FF's
or the POPIO (B) signal (pin 8, MC37) and are passed through pin 6 or pin 8 of
MC 56. When the pulse applied to the L input of the latches goes high, the output (Q) of the latch will reflect the inverse of the input. Since the input (pin 7
MC43 and MC33) is held high by lOBO 3 being low (Logic "Oil), the Q output
(pin 8, MC43 and MC33) will go low when the positive going latch pulse is
applied to the L input (pin 4, MC43 and MC33). The Q output (pin 8) will "latch"
in its low state when the latch pulse (L) goes low. When the Q output (pin 8) is
low, the output buffer transistor (Q17 or Q11) will be cut off and the output line
will go high (+V).
3-42.
A POPIO(B) signal will apply latch pulses to all the data output storage registers when all the lOBO lines are Logic "0". This Logic "Oil will be
transferred to the data output lines.
3-43.
A Logic "1" is transmitted to the output data line in the same manner.
When the
Latch pulse (L) goes high, the Q output (pin 8) will go high and latch when the
latch pulse falls. Since the output is high, transistor Q17 will saturate, causing pin k (Bit 3, first word) to go low (Logic "I", OV).
If lOBO 3 goes high (Logic "1"h. the input (pin 7 MC43) will go low.
3-7
12661A
3-44.
Section III
SECOND WORD COMMAND.
3-45. The command line
Address Code (second word output bits 0,1,2,
see Figure 1-1) is transferred to the input of the Address Decoder the same
way second word output data is transferred to the output lines. The Address
Decoder is a 4 Line (BCD) to 10 Line (decimal) converter. None of the Command 0 to Command 7 lines can be activated while pin 2 of MC14 is held high
since this enables a decimal 8 or higher coded output line. Pin 2 of MC14 is
held high while the Command Control FF is clear. When the Command Control FF is set (from the second 100 signal), pin 2 goes low and the binary
code from pins 1, 14 and 15 determines which output line is activated. The
output command line is held low (Logic "1 ") during the time the Command
Control FF is set. This sends a command signal to the proper peripheral
device.
3-46.
SYSTEM CLEAR.
3 -47. The System Clear output register is similar to the second word data
output registers except it has a Reset terminal (pin 13, MC54). If, through
a software instruction, lOBO 7 goes high, then pin 12 of MC54 goes low. The
second 100 signal (see paragraph 3-7) makes MC46 pin 11 (Sheet 2) low which
is applied to pin 11 of MC 54. The Q output (pin 8, MC 54) will go high saturating transistor Q29 which causes the SYSTEM C LEAR line to go low (OV).
3-48. A System Clear command is also generated by POPIO(B) signals when
the computer is initially turned on. Also an Alarm input from the input storage registers through jumpers A-D may generate a System Clear command.
The POPIO(B) signal and the alarm pulses are applied to pin 13 of MC54 (Reset terminal). This Reset Command causes pin 8 of MC54 to go high which
makes the SYSTEM CLEAR line low (OV).
3-8
Section
12661A
rA- - - - -
INPUT STORAGE REGISTER
~.5v - ~
PERIPHERAL
STATUS
16
1K
:1
~:p~r~......
~~,E
II'
o
v
Q31
v
R54F
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~
LYL
r '"liS- -12V
I
I
I
W7A
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--."---11
~
17
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Q 16
13
L
~ ALARM 0 FF
'1
BIT 0 FF
13
L
MC 103
MC 93
I
+4.5V
Q 16
3
Q 15
BIT 1 FF
ALARM 1 FF
13
L
MC 93
HL
MC 103
--,1------+~~64
LBIT
I
6
Q 10
2 FF
~ALARM 2 FF
L
MC 103
As A ....,1------+~-I47
LBIT
- -......_--11r SAME
R56A. B. C
I
1..!3~C~.~4..J
PERIPHERAL
STATUS
II: 93
Q
13
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12 MC
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R58A.B.C
I
~ALARM 3 FF
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MC 93
2
Q 16
BIT 4 FF
~ ALARM 4 FF
13
l_R~.~.~•...J
13
L
L MC 104
r-SAME-AS A ....,
1820-0069
1820·0131
1820-0070
19
5 - -.....
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I------+~-I BIT 5 FF
R57D.E.F.
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I
LR32:..C:z.:~....J
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1820-0132
1820-0301
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MC 94
1.
2.
3.
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30
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I
,
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IS EQUIVALENT TO
MC 94
9
7
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L ~.~.~5J
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MC 104
TO
(5)MC76
:t:=)-
(Sheet 2)
2
MC
75
1
6
L
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MC 94
MC 74/
0069
0070
0071
14
7
14
7
14
14
14
0077
0111
14
8
16
0132
14
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12
5
16
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7
9
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13
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10
80
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81
lOBI -6
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9 84
8
9
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1 3 _84 IOBI-7
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5 Me
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6
4
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75
3
8
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12
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6
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2
3
4
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MC
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.ill
3~
2
1
0
7
6
5
4
FROM
POSITION JUMPERS
W7A. W8A, W9A FOR
0956
12
lOBI -3
'-I..1L
5_
(8)MC54 _
(Shee.3)
6
0068
64
:R
"-
0054
13
21 MC
~2~A.b-_ _ _ _ _ _ _ _ _ _ _--,
TO
(4) MC5~
(Sheet 2)
HP NO. 1820GND. PIN NO.
Vee PIN NO.
Vee PIN NO.
8
4 84
SCHIillATIC DIAGRAM FOR RESISTOR
NETWORKS R59 TllRU R63
SCHEMATIC DIAGRAM FOR RESISTOR
NETWORKS R39 TllRU R58
MC
83
4 83
q~
MC73....::::::::1 'Uii\
ALL LOGIC IS POSITIVE-TRUE
=9-
L
1------+~--I4 LBIT 7 FF
..1.2..
10
8
Q
lOBI -2
6jMC
Q
~ ALARM 6 FF Q
MC 104
3
MC
83
~
q
6
Q 10
BIT 6 FF
lOBI -1
~
Q 10
3
13
V
6 - -••
PERIPHERAL
STATUS
11
-~
Q
~ALARM 5 FF Q
13
1820-0077
PERIPHERAL
STATUS
lOBI -0
Q 1-~
15 ________+--------_+~1:..4f>K:\ 13
,I. MC
12
PERIPHERAL
STATUS
lOBI -15
12
j
6~
9
7
9
Q~..--+---l
3 FF
MC 103
r-sAME As A -1-_ _ _ _ _+~.....:;2
W
4
I
83
L ~~?~3~Q~J
3U
79 IOBI-13
R70
1K
MC
9
PERSTIPHATUERSAL
9
18 3
I
1
WmASA
R550, E, F
~::..l..!~~C!...7.1
l@r-13:...._ _I-___
+4_._5_V_ _
'---:61_
.....
____ .J
R55A. B. C
TO~
FR(II
(2)MC54 (Shee,2)
14
L!':::~.~2...J
PERIPHERAL
STATUS
(Sheet 2)
+4. 5V
r SAME As A .....1-_ _ _ _ _+~~3
STATUS
(5)~~-
(Sheet 2)
I
I
I
T
PERIPHERAL
FROM
(12)MCI6 -
(Sheet 2)
:1
R540
1K
L
(Sheet 2)
I
I
1
(T2)
FROM
(8) MC47 -
"> R311
I I
I I
I
(T5)
FROM _
(6)MC47
m
5.
I 266IA.QPTlON 01
*
INDICATES SIGNALS FROM/TO EXTERNAL
DEVICE VIA 48-PIN CONNECTOR.
ALL OTHER
SIGNALS ARE FROM/TO COMPUTER VIA 86-PIN CONNECTOR.
Figure 3-1. DVS Card, Schematic
Diagram (Sheet 1 of 3)
3-9
Section ill
12661A
FRlII (2) MC75
(m-l)
TO (13) MC54
(Sheet J)
15'~6
TO (14) MC97
TO
FRlII
(8) MC97
(4) MC75
TO
INPUT
+4.5V
FF
(8)
TO
LATCHES
(Sheet 1)
(Sheot 1)
(Sheet I)
MCI07
1.68
(Sh,et 1)
470
(Sheet 1)
~
.. 2IMC85)il'l~3--------..,fi'''Z- !IRQ
I
13 Me75 12
4 '---'"
8
~~~------~9~Me37~8~__~--------------4-----------.--------------------+----~~------t-----------__________~--------------------__,
+4.5V
fiiODEREQijESTFFI
1
,'"+__-------:;11"i1lC37
10
4
~
~
I
"'+-__-------------------;1~2C
...........
~
~ll
13 MC17 1 13 MC16f+-++.9l:!.
-
:!i~:
i
1
I'FLAG BUFFER FF
1
_
91
I
I
I ~_
- -- .r,-
5
I
I
8
I~O
55
Me
6 1 7
9
3
r-----------~~8Me85;~~----~~ PIlL
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--...
l11l MC
9~ i ~W5A
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~
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------+l
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t12
r4...J
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fl.59
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~.-~--------------------~~~~~MeMe~11~73~,~4'--+_-~~--~~~~
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4
4
PC87..,1:.:3--------;~"'6-IRQ
_MC57 6 I CT
L _____ I
3~
SCL 16
SCM 1"'4....
. ~_--------5"I MC
IOG(II) 15
4
15
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470 -+4.5
6 5 MC16 6
~~°r-tr~O
L..-.L-..-'--2V.....-__________---I
STC
2Z
tI.
6O - Z
b...__---'~1""11MC37~1""3----_._--r4o::.6 ED
l,62
(T2)
-2
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t
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Ctc
21
cas
13
t
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r co:n;; I
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---
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Z Y
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9 11
L L../_ J
NOrB, POSITION JUMPERS W7A. WBA. W9A
2.2~f
+
C52
2.2~f
FOR 12661A-OI'TION 01
PINS wn1-I AN • ARE 'nIE
4~N
CONNECTOR
-12V
+4.5V
A.,
A..~W7A
IW7B
i.
+lZV
+4.5V
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lit
'('
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lit
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Zit
R54B
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R54A
'--________...;4:; L
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t- 3
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~____+-__~1~~
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7
156~
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I
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+
C39-49
(Sheet 3)
(Sheet J)
:
1
Z- - - - - ,
1 C 76 J
~h
70
(Sheet 3)
i!f';?r~Q.l)----+------+------------------.... ;:;~~)
J1r----~ttm.
9.r--...~~
I 121Mc49' 11
DEVICE S
rLAG
-12V
~
LATamS
r-------------------------------------~------i-------------~TO~~(~l~l)~TOt1~~
2
-2V
*
TO 2ND
r-----------------------------------------4-------+-------------------~
L./
1.59-2
-2V
100 20
FF
(_1)
5..--.
t1.6O - 3
-ZV
ALARM
.-----------~LATamS
TIMER
Mcn
FF
Q~
Ir',w<.'li
_,.....~=..""..,~15
9
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Me
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Y
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~ 1.61
1".-4
-ZV
Figure 3 -1. DVS Card, Schematic
Diagram (Sheet 2 of 3)
3-10
12661A
Section III
74
10BO_15
16
r-_ _ _ _ _....!2-rWiiNin:-;~
WD2-0 FF Q
WU
-
131
4
15
L...-I-IAO ADDRESS
;;,.....MC:;:::....:;Z4:....-...;Q:.J
LL
DECODER
10BO-13
3 ...------.15
,...----+--1
131L
~
WDZ-1 Fr
Q
_Q
MC 24
WlZ
4
-_
14
14
lOBO -12
~
10BO-11
Al
9 W13
Q
-Oor-
Q~
MC 14
2
-
9
2.1...;1+-+-4-~___- '
...---IAZ
7
4 I WDZ - 2 Fr
L
MCZ4
5
3 10
1
j
7
6 4
5 3
A3
1 12
o
13
16 I of4 .5V
.----0-_----1
W14
IOBO-I0
lOBO - 9
C~L:.WD~zMC~-7~S4~FF.;~~rllJ
lOBO - 8
I __-:~t;~~r8~----=-1_S r=
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lOBO - 7
FIUJM
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(5....' 2)
(11):
(Sh..,2)
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(Shee, 2)
(Sheot I)
lOBO - 6
1.FIUJM
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(5....' 2)
lOBO - 5
lOBO -4
42
1
lOBO -3
lOBO -2
~ R:6'21~vl_2'ti.
~
10
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MC .8~_4~+-I-++-_!...7r;;;;-;-;;:-QJ
44 )I
.41 BIT 3 Fr
QI
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13
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r
9
---<---1-1:
sAME AS -; -,
-Q 14
1 RIO :43A, B, C. 1
l2L~!:!M£.C123.L...s.J-------j CR1~
20...J
c.:£.
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61-6
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1
1 RB:42A,B,C, 1-1---<__-,lL:......!!M!£C~2~3_S.QJ------; ~,~.~...J
-2!3 MC •
R16. 51;734
•
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I
6
4
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7
WDZ-] Fr
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r- sAME-ASIi ...,
1D :~~T i AMPL
VOLTAGE
RANGE
CUUEIIT
LIMIT-
RAMGE
CURIlEIIT
LlMlT MBB
F
L---...;4~:L-2M~C~3~3__-~Qr-8------------11 ~~:~i~i~~I---..
--~-
5
--
QI
6
1 R12 :44A.B, C, 1-1- - - - Z
r----=l2:L2MC~J3~..sQLt"'------__1 CR1~
1
r SAllE
- -AS--,
B
~lL:""..!!MC~43!...~Qj-8-----;1~2~¥7...Jt-I------14 :~~TjAMPL
~2 BIT 2 FF Q I
r ~"";:S-; -,
,
35
10BO- 0
____
MC43
45
~
lOBO -1
:ll:.B_IT..!!£4.!Fr.L~~j-I_ll
~L
WD2-6 FF
13
CURIlEIIT
LIMIT LSB
NOI1!, POSITION JUMPERS
sAME"As-;-,
8
1 R7:42D,E,F, It--.--"" VOLT.AMPL
11L~!:!M:£C1213_S.QJ-------j CR2:cz!~ -J
BIT 0 (LSB)
W7 A. WBA. W9A FOR
1266IA.oPnONOI
...
-ZV
e STARTING WITH REVISION CODE
B-1031-6, THE CONNECTION OF THE IK RESISTORS
TO THE +4.5V BUS IS OPENED IN THE CIRCUITS FOR COMMANDS 0 THRU7. ~EVISION
CODE WAS A-902- 6.
Figure 3 -1. DVS Card, Schematic
Diagram (Sheet 3 of 3)
3-11
Section m
12661A
STF
MACHINE TIME
TO
TI
T2
T3
r6
T4
T5
16
T7
TO
TI
T2
T3
T4
* T6)
T5
(ANY INSTRUCTION
STC
T5
T6
11
TO
TI
T2
T3
T4
FETCH OR
EXECUTE
INTERRUPT PHASE 4
T7
TO
TI
T2
13
T4
T5
T6
T7 . TO
TI
T2
**
ENF
STF,
lEN
SIR
DEVICE FLAG
SIGNAL
FLAG FF
STC
PRl
IRQ SIGNAL
FLAG SIGNAL
ENABLE
SERV ICE REQUEST
INTERRUPT SIGNAL
IAK
lOG
I------"~.~
SPC
SET PHASE
200
L
nSEcl-
,
STF INHIBITS
I
liENABLE SERVICE REQUEST":
I
I
STC INHIBITS
I
"~ENABlE SERVICE REQUESTI"
I
I
I NTERRUPT SIGNAL
TO COMPUTER
NOTES:
STF, ClF, STC,ClC, JMPl, AND JSBI.
*** EXCEPT
EXECUTE IF A SINGLE CYCLE INSTRUCTION.
Figure 3-2. Interrupt System Timing
3-12
Section IV
12661A
SECTION IV
MAINTENANCE
4-1.
DIAGNOSTIC PROGRAM DESCRIPTION.
4-2.
The objective· of this progra'm is to check the DVS Program Card
and verify that it is operating correctly. This program may also be used
for troubleshooting and diagnostic tests on the card. A peripheral device
is not required for the tests.
4-3.
The program consists of a background control program which contains
four task routines. Information controlling message printout and task performance is supplied through the Teleprinter and Switch Register. The first
task routine inserts the address of the DVS Program Card into all I/o instructions. The second task routine (INITIAL TEST) checks the Card for
initial conditions and POPIO operation. The third task routine (BASIC TEST)
checks the flag, control, and interrupt circuitry on the card. The fourth task
routine (DATA BUFFER TEST) checks the data buffers and associated discrete
circuitry by outputting combinations of 8 bits, 5 bits and 3 bits. .
4-4.
HARDWARE REQUIREMENTS
4-5.
Hardware requirements to test the DVS Program Card are as follows:
a.
Any HP Computer (2114, 2115, 2116).
b.
Teleprinter (HP 2752A - modified ASR-33 or HP 2754A modified
ASR-3 5) and associated interface register.
c.
An input device to enter the program into memory (e.g., HP 2737
AlB Punched Tape Reader) and required interface. (Teleprinter may be used.)
d.
Four, 48 pin test plugs wired according to Table 4-1. HP Part No.
01251-0335 (not pre-wired).
e.
DVS Program Card with optional jumpers in the following positions
Control Jumpers
(Figure 3-1. Sheet 2, in place as shown)
WI
W2
W3
W4
W5
W6
Logic Level Jumpers
(Figure 3-1. Sheets 1, 2 and 3 as shown or Opt. 01)
W7 orA
W8 orA
W9 orA
WI0 (Sheet 3)
4-1
12661A
Section IV
Output Jumpers
(Figure 3-1. Sheet 3, removed as shown)
W11
W12
W13
W14
Alarm Jumpers
(Figure 3-1. Sheet 1, in place as shown)
MC74
MC73
0 to 7
A to D
4-6.
SOFTWARE REQUIREMENTS.
4-7.
Software requirements are as follows:
a.
A binary program tape (Diagnostic Test Software HP 20436A).
b.
System Input/Output Teleprinter Driver (for example, SIO 8K Memory
HP 20305A).
4-8.
DIAGNOSTIC TEST PROCEDURE.
4-9.
DVS Progr;;tm Card.
a.
Make sure jumpers conform to paragraph 4-5e.
b.
Install test plug number 1.
c.
Place interface card (with jumpers and plug) in an I/O slot of the
computer such that every slot of higher priority has either another I/O card or
a priority jumper card in it. If troubleshooting is to be done it is desirable to
use an extender card between the computer and the interface card.
4-10.
Teleprinter
a.
Place the Teleprinter Interface card in an appropriate I/O sloL
b.
Connect Teleprinter Interface card to the Teleprinter.
4-11.
Teleprinter Driver
a.
Load the SIO Teleprinter Driver tape into memory using the Basic
Binary Loader.
b.
Set Switch register to 000002.
c.
Press LOAD ADDRESS.
4-2
Section IV
12661A
Table 4-1. Test Connectors
Test Plug No. 1
Pins Shorted
Output Lines Tested
Command
Bit
Bit
BLt
Bit
Bit
Bit
Bit
Bit
0
0 (LSB)
1
2
3
4
5
6
7
H-S
D-16
5-T
4-17
K-U
9-W
10-19
L-V
E-18
Input Lines Tested
Flag Line Input
Peripheral Status
0
1
2
3
4
5
6
7
Test Plug No. 2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
8
9
10
11
12
13
14
15
(MSB)
11-16
M-T
N-17
12-U
R-W
14-19
13-V
P-18
Peripheral Status
0
1
2
3
4
5
6
7
Peripheral Status
0
1
2
3
4
Peripheral Status
0
1
2
3
4
5
6
7
Test Plug No. 3
Second Word
Bit
Bit
Bit
Bit
Bit
3
4
5
6
7
F-16
J-T
8-17
- 6-U
15-W
Test Plug No. 4
Command
Command
Command
Command
Command
Command
Command
Command
0
1
2
3
4
5
6
7
H-16
2-T
C-17
7-U
3-W
A-19
1-V
B-18
4-3
12661A
Section IV
d.
Set the Teleprinter I/O address into the switch register.
e.
Press RUN.
4-12.
DVS Program Card Verification Program.
a.
Load the program into memory using the Basic Binary Loader.
b.
Set switch register to 000100 (this is the starting address).
c.
Press LOAD ADDRESS.
d.
Press PRESET then RUN.
4-13.
PROGRAM OPERATION
4-14. The initial test will give valid results only when immediately following
computer power ON or PRESET. POPIO signals from the I/O backplane cause
the data buffers to be preset to the proper state. If the INITIAL TEST is performed after the other task routines have been entered, it will cause error
printouts. To perform the INITIAL TEST after the other routines have been
entered, push PRESET and restart the program at address 100. The INITIAL
TEST can be skipped by setting Switch Register Bit 3 up.
NOTE
2114A Computers, push Bit 3 to light.
a.
The Teletype will print: 12661A DIAGNOSTIC PROGRAM.
b.
The Teletype will print: I/O CHANNEL?
c.
The operator must type (using the Teleprinter keyboard) the address
(select code) of the DVS Program Card, followed by a line termination (CARRIAGE
RETURN, LINE FEED). To skip INITIAL TEST, set switch 3 up and go to step i.
d.
The INIT~L TEST starts at this point. All four test plugs are used.
The teletype will tell you when to change to the next plug. The Teletype will print:
CONNECT PLUG NO. 1 AND PUSH RUN.
e.
If an error occurs at any time in the INITIAL TEST, the Teletype will
print OUT PUT = XXXXXX INPUT = XXXXXX, and the computer will halt. Refer
to ERROR CODES (paragraph 4-18). To continue, you must push RUN. When
the first test using plug no. 1 has been completed, the Teletype will print, CONNEC1
PLUG NO.2 AND PUSH RUN.
4-4
12661A
Section IV
f.
When the second test using plug No. 2 has been completed, the
Teletype will print, CONNECT TEST PLUG NO.3 AND PUSH RUN.
g.
When the third test using plug No. 3 has been completed, the
Teletype will print, CONNECT TEST PLUG NO.4 AND PUSH RUN.
h.
At the completion of the INITIAL TEST, the Teletype will print,
CONNECT TEST PLUG NO.1 AND PUSH RUN.
i.
The BASIC TEST starts at this point. If an error occurs at any
time in the BASIC TEST, the Teletype will print ERROR OOOOXX, and the
computer will halt. Refer to ERROR CODES (paragraph 4-18). To continue,
you must push RUN.
NOTE
If error is not first corrected, sub-
sequent tests may be invalid.
j.
At the end of the BASIC TEST and the beginning of the DATA
BUFFER TEST, the Teletype will print: DATA BUFFER TEST PLUG NO. 1.
PUSH RUN. Since test plug 1 is already installed, it is only necessary to
push RUN. If an error occurs at any time in the DATA BUFFER TEST, the
Teletype will print, OUTPUT = XXXXXX INPUT = XXXXXX, and the computer
will halt. Refer to ERROR CODES (paragraph 4-18). To continue, you must
push RUN.
k.
The program now goes through the DATA BUFFER TEST routine,
printing error messages or instructions. Each of four test routines checks a
portion of the Output Buffers by outputting data through jumpers in the test
plugs to the Input Buffers and comparing data output with data input.
1.
The Teletype will print END OF DATA BUFFER TEST, and the
computer will halt. This statement is at the end of the DIAGNOSTIC PROGRAM.
If there were no error messages the DVS Program Card is good.
.
.
m.
To return to the beginning of the program, set Switch 0 up and push
RUN. The program will halt with 102000 in the "T" register (2114A- Memory
Data Register).
To start the program again, push RUN.
4-15.
PROGRAM CONTROL
4-16.
The program is controled by the Switch Register switches 0 to 4.
4-5
Section IV
12661A
Switch 0 Up
Throw this switch up at any time to halt at beginning
of program. The program will halt; A, B, and T REGS.
= 102000. (2114 - Memory Data Register) Pushing RUN
will enter Program Operation at 4-14b.
Switch 1 Up
This switch will cause a halt at the end of error loop
test.
Switch 2 Up
This switch will cause the program to loop around error
for oscilloscope testing.
Switch 3 Up
This switch will cause program to skip INITIAL TEST.
Switch 4 Up
This switch will cause the program to loop through
entire Basic Test.
4-17. Switches 1 and 2 should be used in conjunction. Switch 1 will allow the
operator to determine where he is in the program by observing the computer
program counter, and let him decide if he wants the next subroutine to loop or
not. Both of these aids can be bypassed by keeping the switches off.
4-1S.
ERROR CODES.
4-19. Initial Test Errors: If the data to the computer from the interface card
is not the same as an appropriate comparison number (internal to program),
the follo}Ving code is printed:
OUTPUT = XXXXXXs
INPUT
= XXXXXXS
OUTPUT is the comparison number and INPUT represents the initial status of
the data buffers. For test plugs 1, 2, and 4, OUTPUT will be 040000, and for
test plug 3, OUTPUT will be 040020. If the error is in bits 13, 14, or 15, it
should appear for all test plugs. These bits indicate errors as follows:
BITS 13, 15
If both are set it indicates that POPIO is not resetting
the Mode Request Flip- Flop (MC 15 pins 8 and 10).
If Bit 13 is set but Bit 15 is not, there is more than one
error. The other errors will be observed in the next
tests.
If Bit 15 is set but Bit 13 is not, this indicates an error
not related to POPIO and will be detected in the next tests.
BIT 14
If not set it indicates that POPIO is not resetting the
System Clear Flip- Flop (MC 54 pins Sand 13, MC 75
pins 12 and 13, and MC 76 pins 4 and 6).
4-6
12661A
Section IV
4-20. For test plug 3, the System Clear signal is applied to Bit 4. This Bit
should follow the pattern of Bit 14. If Bit 14 is set but Bit 4 is not, it is probably
a data buffer error which will appear in the Data Buffer Test. If Bit 14 is in
error but Bit 4 is set, it could be a data buffer error, or it could indicate
failure of MC 107 pins 2, 13 and 14.
4-21. In addition to these bits, the POPIO signal strobes zeros from the I/O
bus to both the first and second word latches. An error in these bits may
indicate a data buffer error or failure of MC 56 pins 1, 2, 6, S, 12 and 13.
4-22. Basic Test Errors: If an error occurs during the Basic Test, the
Teletype will print the following error code:
ERROR
OOOOXX
where XX is an octal number between 00 and 45. When an error number is
printed, refer to Table 4-2 for an explanation. Some error codes have correspondingly numbered timing diagrams. Use an oscilloscope to determine the
state of the test point. Approximately +4. 5V equals logic "1" and ground or
OV equals logic "0". The notations on the timing diagrams will inform the
operator of the procedure used to diagnose the error.
4-23. Data Buffer Test Errors: If an error occurs during the Data Buffer
Test, the Teletype will print the following error code:
OUTPUT = XXXXXXS
INPUT
= XXXXXXs
If this happens set the switch register to 3757 and press LOAD ADDRESS.
Then clear the switch register and set switches 1 and 2 to allow program looping.
Press RUN and observe data buffers with an oscilloscope. By noting which input
Bit is in error and checking Table 4-1, it can be determined which data buffer
circuit is bad. The oscilloscope should be triggered from either a CLC or a
CRS command. Refer to the schematic (Figure 3-1 Sheet 2) to determine a
convenient pickoff point for the trigger. The data buffer line should be reset
following the CRS signal and set followi ng the CLC Signal.
4-24. An interrupt from any other I/O device at any time will halt the program.
The address of the interrupting device is the last six bits of the T-Register
(2114 - Memory Data Register).
4-25. If an error printout occurs and the diagnostic test is continued without
first correcting the error, subsequent tests could be invalid.
4-26. Figure 4-1 in Section 4 is the component location of the DVS Program
Card. Use it as a guide in locating the IC packs for troubleshooting.
4-7
Section IV
12661A
Table 4-2
Error Codes
CODE
NUMBERS
EXPLANATION
,0,0
See timing diagram ,0,0
,01
See timing diagram ,01
,02
See timing diagram ,02
,03
This error should occur as ,01 or ,02. See timing diagram ,02
,04
See timing diagram ,04
,05
See timing diagram ,05
,06
In the halt condition check the following:
MC76-9; MC66-8, 10, 11; MC65-12, 13 are all high
MC76-10; MC66-9; MC65-11 are all low
This checks that*CCFF was reset with CLC command.
,07
This error should occur as ,01, ,02 or ,06.
1,0
See timing diagram 1,0
11
Set switch register to f.J'f.J'2642 and press LOAD ADDRESS. Clear
switch register then set switches 1 and 2 up and press RUN.
See timing diagram 1.0. Watch closely*(SFFF).
12
See timing diagram 12
13
Set switch register to DD2664 and press LOAD ADDRESS. Clear
switch register then set switches 1 and 2 up and press RUN. See
timing diagram 12. Watch closely:+(SFFF).
14
See timing diagram 14
15
This error should occur as 14 ..
16
See timing diagram 16
17
See timing diagram 17
2~
Set switch register to .0.02772 and press LOAD ADDRESS. Clear
switch register then set switches 1 and 2 up and press RUN. See
timing diagram 17. Watch closely~IFF).
21
This error checks as 2.0. IFF not resetting.
22
This error checked as 2.0. Watch closely IAK.
23
While computer is halted check that MC36-3 and MC66-4 is low.
MC66-3, 5 and 6 should be high.
4-3
Section IV
12661A
Table 4-2. (Cont'd)
Error Codes
CODE
NUMBERS
EXPLANATION
24
Set switch register to .0.02752 and press LOAD ADDRESS. Clear
swit ch register then set switches 1 and 2 and press RUN. See
timing diagram 16. Watch closely*ICFF.
25
This error checked as 20'. Should occur as 17. IFF not setting.
26
This error checked as 20'. Should occur as 21. IFF not resetting.
27
This error should occur as 16.
3,£1
This error should occur as 23.
31
In the halt condition check the following;
MC55-3, 4, 6; MC45-9, 10, 12, 13; MC35-8, 10; MC64-3, 4.5;
MC65-3, 4; MC54-6 are all high.
MC55-5; MC45-8; MC35-9; MC64-6; MC65-1; MC54-2, 5, 3 are
aU low.
32
This error checked as 2.0'. Should occur as 17. * IFF not setting.
33
This error checked as 2.0'. Should occur as 21. * IFF not resetting.
34
See timing diagram 34
35
See timing diagram 35
36
See timing diagram 36
37
See timing diagram 37
4~
See timing diagram 4~
41
See timing diagram 41
42
See timing diagram 42
43
See timing diagram 43
44
See timing diagram 44
45
This error should occur as 35 through 44. See paragraph 4-27.
* CC FF
* SFFF
* IC FF
:::: Status Flag Flip Flop
* IFF
:::: Interlock Flip Flop
:::: Command Control Flip Flop
:::: Interrupt Control Flip Flop
SET CONTROL - An aririitional test loop to check the set control
function. See page 4-21.
MODE ASSIGNMENT - An additional test loop to check the mode
assignment function. See page 4-22.
4-9
12661A
Section IV
4-27. Error 45 should not occur. At this point the program is creating alarm
signals on aU eight alarm inputs. Each input has been checked individually (as
errors 35 through 44) and should be caught there. If necessary this could be
checked as done by looking at all points referenced in Figure 4-12.
4-10
Section IV
12661A
PUSH RUN AND SCOPE CHECK THE FOLLOWING.
SET SWITCH REGISTER BITS I AND 2 UP.
I
(SKF); PIN 12: MC88-9.6.8;
MC57-11
1'9
II
I2
T~
T4
T5
T8
T7
TO
II
I2
'[3
o------~!
i - - - - - - - --------
MC37~13:
MC67·6
o
(SFS); PIN 25: "C87-'
o----------------~
OOG(A) ADO. ): MC67 -3;
MCI6-6: Me27-", 13
o------------------~
MCI6-5; MC15-6
o
OOG (Bll: MCI5-4; PIN 15
o---------------------!
o ____________....J
(SCI.): MCI5-3; PIN 16
(SCM); MCl5-5: PIN 14
o--------.....J
(SFFF): MC67-5: MC77-14
PINS 13.21.35.38.41:Q30-C:Q13-B:
o
I
Me?7 -3, 7.9: MC7fi-B. 2; Me37 -I. 5:
MC27-8,5, MC34-4,13,5;
MeI4-l,1", 15; MC24-B.14, 1
0
~i07_«;;~Q~Oi_~:r.:;;g-~i:?~~-~'s\O.II;1
---------------i---------------------;.------------
:g~~ =~:;: ~~~3::~~ 6~i~~14 -13. 2 ;0
Me6S-12.13; MC5f1-9.10;
MC46-11.6.2, 1. 5; MC35-11.12;
MC36-8.12.13.9; MC27-11: MC37-3
MC66-9:MC65-11;MC46-12.13.3.4;
MC35-13; MC36-1I.10: Me37-":
Me27-l2: PIN 20
(ENF(T2)): MC77-13: MC47-R:
MC37-13: PIN 46
0
I
O------------------T-------------------------~-------------
O------~~L~----------------------~--~
MC47-9.10.12. 13: Me37-12
o
(SIR(T5)): MC77-4: MC'7-6;
MC37-1I: PIN 32
LJ
O------------+--~~L--------7_------I
MC47-1.2.4, 5j MC37-10
o
I
I
I
I
LJ
I
(T3): MC76-1; PIN 11
O--------------~~L------------------------_7--------------
Figure 4-1. Timing Diagram for Error
flfl.
4-11
12661A
Section IV
SET SWITCH REGlSTER HITS 1 AND 2 UP.
TO
(SKt'l: PIN 12: MC86-9,6,8:
MCS7-1I; (SFHI: MC67-13:
MC77-IS
TI
T2
PUSH RUN AND SC:OPE CHECK THF. FOLLOWING.
T6
T4
T3
T7
TO
TI
T2
T3
0 ---------------------~----------------------------------------r--------------------(
MC57·12: MC67-12
o
(SFeI: PIN ;: MC67-1
L_
.--r----------,
o-----------------------~
(IOGenl ADD. I; MCS7-2
o -----------
Figure 4-2. Timing Diagram for Error ~1.
SET SWITCH REGJSTER BITS 1 AND 2 UP.
TO
TI
PUSH RUN AND SCOPE CHECK THE FOLLOWING.
T3
T2
T4
TS
T6
T7
TO
TI
TZ
T3
SET SWITCH REGISTER nITS 1. 2, 4, 7. 8, 10 (26261 UP AND LOAn ADDRESS. THEN CLEAR
SWITCH REGISTER AND SET BTTS 1 AND 2 UP.
FOLLOWING.
I
PUSH RUN AND SCOPE CHECK THE
MC4S-12,13,IO,3.4:MC37-4,1.5:
J
MC35-13; MC36-11.10; MC27-12.5.8:
0
PIN 13,20, and 21.
MC46-II.B.9.6.S.2.I;MC3S-II.12:
:g~~=~i~i~~9~~.;
MC37-2,6,3;
(IOG(R) ADD. ): MC27-4, 13,
-------------------~---------------------------..:.------------
J
0
o---------------~--~
I
OOWN
SET SWITCH REGISTER BIT 2
AND PUSH RUN (COMPUTER HALTS), SET SWITCH REGISTER BIT 2 UP,
PUSH RUN AND SCOPE CHECK T~E FOLLOWING.
MC46-II,B.12.3,4.S; MC3S-I2.\3; J
MC36-11.10, 9, 13; MC27-11, 9, 10. 6;
MC37-2.6.3.
0
MC46-13.10. 9,6, 2,1 j MC35-11 j
MC36-8,12j MC3'l-l, 5,4;
MC2'l-8, 5.12; PIN 13. 20 and 21.
I
J
o
Figure 4-3. Timing Diagram for Error ~2.
4-12
Section IV
12661A
SET SWI'l'CH REGIBTER BITS I AND 2 UP.
TO
TI
T2
,,
,
T3
SET SWI'l'CH REGISTER BITS 1 AND 2 UP.
(SKF); PIN 12; MC8S-9,6,8;
MCS7-11
PUSH RUN AND SCOPE CHECK THE FOLLOWING.
T4
T5
TS
T'I
TO
TI
T2
T3
PUSH RUN AND SCOPE CHECK THE FOLLOWING.
------------------0----------------7-----------------I
.
-.----.--~--------
MC57-13; MC67-6
_______________0
I
(SF'S); MC67-4; PIN 25
______________~O----------------~
I
(s"ffi); MC11-14; MC61·5
o -----------------"--------------------.--.. --.----i-----------------
MC1-7--3-;M-C-7-S--8,-10-;-(T-F-F)-;---...,.,I
MC77-8;Q30-B; (OF);
0
PIN 'H, 'S;QI3-C
(CCFF); MC7A-9; MCS6-8; MC76-2;
MC6S-13; (TFF); MC77-9. 7;Q30-C;
~:~-:s;. ~i,3~II,4.S,13; MCI4-2;
MC34-3;MCI4-13.I,14.15.S;
MC24-8,14.1,2,3,7;
MC34-2,12,6
I
0
--------------i------------------------.;.-------------
I
0
I
o
--------------~I
(ENF(T2ll;MC77-13;
MC47-8; MC37-13; PIN 46
r--I
0 ______________. 11
-------------------~
1,-,____________________
,
~~'- - - - - - - - - - -
Mcn-9, 10,12, 13;
MC37-12
---------------------I
(T3); MC76-1; PIN 11
,
o
; - 1- - - - ,
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
MeSS-9.l0,11; MC65-11 i MC76-3
_ _ _ _ _ _ _ _ _ _ _ ____
IF CCFF IS NOT SETTING THERE COULD BE TROUBLE WITH MC4S-II,I2, OR 13 NOT
GATING A PULSE THROUGH TO CCFF. TinS WOULD NOT BE APPARENT IN THIS LOOP.
Figure 4-4. Timing Diagram for Error ~4.
SET SWI'l'CH REGISTER BITS I AND 2 UP.
TO
(SKF); PIN 12; MC8S-9,6,6;
MC57-11
TI
T2
T3
PUSH RUN AND SCOPE CHECK THE FOLLOWING.
T4
TS
T6
T7
TO
T1
T2
T3
1
o-------------------~
------------~I
MC57-12; MC87-12
____________________
0
(SFC)j MC67-1; PIN 5
------------------1o----------------~
--------------------~------------------------~--------------(SFFF); MC67-13;
MC77-IS
OOG(B) ADD. ); MC67 -2;
MC16-6
0
1
0--------------------'
------------------
Figure 4-5. Timing Diagram for Error ~5.
4-13
12661A
Section IV
SET SWITCH REGISTER BITS I AND 2 UP.
OT
4
PUSH RUN AND SCOPE CHECK THE FOLLOWING.
OTA
4
(SKF): PIN 12; MC86-9.6.S;
1
_M_C_57_-_I_I____________________~O-------------7----------------------~--------------------____~------------------------~
I----------------------------~--------------------~------------------~
MC5'l-I3; MC67-S
,
o
1
(SFS): MC87-4; PIN 25
O----------~------------------~--------------------~
W
~----------~----------~r
O
~
----------------------~I
(SFFF); MC67-5; MC77-14
__________________
I
OOG(B) ADD. I; MC67-3;
I
_M_C_2_7_-1_3____________________~O-----------J
(ENF(T2)); MC37-13
__________________
I
~o
n'L-____________ n
------.J11I
.
.
L-T-----------~
~
~:,
,-;
. -____________~I
L
L
1
Me77 -3 j MC76-8
0----------'
----------------------1---------'
n
-(C-C-F-F-)-;M-C--65---II-;-M-C-6-6--9--------~~
~
(~): MC76-9; MC66-8;
MC65-\3: MC14-2
0
1
(T3); MC76-1
0
(TFF): MC76-2; MC77-9
(TFF); MC76-IO; MC77-8
(SIR(T5)); MC77-4
1
0
Q13-C; Me34-3;
0
000); MC27-12; PIN 20
M046-12,3.4.5; MeSS-13;
MC36-1I, 10, 9: MC66-10;
MC24-2. 3,7: MC34-2, 6, 12
n
1
1
000 ADD.); MC24-4, 13;
MC56-8; MC46-10.13, I;
MC37-4j MC35-11
,,
0
0
MC65-12j MeS6-9, 10;
MC46-11; MC37-3; MC27-11:
MC35-12; Me36-IS
I~________________________~
,
~__________~!lL____________~IlL____________~
,,
,,
1
(nF)' Q30-8' PIN *H "S'
MC66-11 j MC76-3
n
' -____________________....1
0
MC77 -7; Q30-C; MC34-4;
QI3-R
Mci4-13
'-'-____________________--';
~~rrL--------~--~IlL---------,
LJ
,
I,
~__________~~L-----------~
1
,
0
I
I
1
L -_ _ _ _ _ _ _ _
,U
U
,
0
:,, LJ
________
~'-Jr-lL-__________~______________~
rTI
0
ITl'----------~~~----------+-------------~
0
1
LU
:
~
I
0
MC46-9. 6, 2; MC36-8,12j
MC14-1. 14,15; MC24-1 ,8,14:;
MC34-1, 5.13; PIN 35. 38, 41
0
Figure 4-6. Timing Diagram for Error 1Ji1.
4-14
12661A
Section IV
aT SWITCH RECISTER ..TS I AND Z UP. PUSH RUN AND SCOPE CHECK THE FOLLOWING.
1314T51 e 171 0 II Iz 13141: I e 1710 I I I z 1 0 :
________________
I I
51 e
71 0 II I zl ,3T.1 51 61 710 II
_~
~
~
~
MC57·12; MC67·12
~
~------~r---
~~--------------------------~------------~I:
(SFC); Mce7·1; PIN 5
'~L
-------------~I
________________
21
~o
------------------~
(SFFF); MC67·13; MC77·IS
I
I '_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ "
;_
-___
___
__
_----;,
(SKF); PIN 12; Mele.l,e,a;
MC57·11
~O~r-----------------------------~----------~
J
nOG(B)ADD.);MCn.Z
___________
-=0I
L
L-J
,
I ---j
(CLC ADD. ); MCU·IO; Me4e·5
MC36·9; MC37·2; MCZ'l·e,9
I
I
o!--l
..JI
-(C-LC-)-,-f-CLC---A--DD-.-);-PI-N-21-~1
_M_C_3_7._I_;_M_C_Z'l_._8_,S_ _ _ _ _ _~0
~-------------------~----------~-------T_--
~l~~---------~!l~---------------~!l~~---------~!l~------------~rlL
(ENF(T2»; MC77·13
---------~I
MC77~3;
MC715-8
~~~~~~~~~O --~--------------------------~
(CCl'F); MC76·9; MCU·8; Me6S·13;
Q~I.~2':~~f:); Q30·B; PIN
I
'S, 'H;O
!-I_ _ _ _ _ _ _ _
(CCFF); MC6S·11; MCS6·S: Me34·4;
MC77·7;Q30·C;QI3·B·
I
0
---i--------------------------!.
(T3); MC76·1
_______________
I
n
~o
~
i,
I
(TFF); MC76·Z; MC77·9
------------------~~
n
~,----------~
m,
L -__________~
m,
~----------~
r
L -______~~~
"
--7----------------------!---...J
(fFr); MC76·IO; MC77·8
0
(SlR(T5»; MC77·4
~~~------~Il~------------~~Il~----~~Il~--~-
,
----------------~I
MC66-11; MC76-3
0
I
MC65-12j MeS6-9.ID: MC46-1l
o
MC56·4,5;MC46·8
________________
nOO ADD.); MC46·10,13;
MC37·4
U
I
~o
~~-------------~r-l~-------___~~L-------------7------------~-,
-------------~
MC35-12j Me3f1-13; MC3'1-3;
I
MC27-11
o
,
LJ
U
-rw-S-F-F-.-2)-;-M-C-4-6.-1-2-,3-,-4----~1 ~
____________________~o
rwSFF·Z); MC46.9,6,2
------------~
rwSFF·l); MC35·13: MC36·n,IO
I
__________________
rwSFF.l); MC31.a, 12
~,------------------~
r'---------------------,
o~
I
~o
I
_____________________0
I
I
,
~:--------------~
~
,
r'-----------------,
O~:
-(~-d-W-OR-D-LA-TC-H-)-;-----~I
MC46-1; MC35-11
Me56-a; MC24-4, 13
,
L---------~!l~----------------~--------~'n
0 __-!'_____________________~:
'-_______--,,-______---'___
Figure 4-7. Timing Diagram for Error 12.
4-15
12661A
Section IV
2, 7,
(2704)
SET SWITCH REGlsrER ruTS
e,
8 UP
AND LOAD ADDRESS,
CLEAR SWITCH REGISTER AND SET BITS 1 AND 2 UP.
PUll! RUN AND SCOPE CHECK THE FOLLOWING.
OTA
CLC,
1213141516171011121314 15181710 III
___________~~
~~_S_F_F_-I~);_M_C_38_-_11
(CRS); MC36-$; MC37-2,6;
MC27-IO
I
U
0
I
MC37.1,5j MC27-8; PIN 13
0
('r3), MC76-I, PIN 11
0
n
n
Figure 4-8. Timing Diagram for Error 14.
4-16
Section IV
12661A
SET SWlTCH REGISTER BITS I AND 2 UP.
CLC
(CRS)
°
OCFF); MC3S-3,4; MC66-4
PUSH RUN AND SCOPE CHECK THE FOLLOWING.
C
6IL_________:--______________________
...---1
~dt1T~~);~M~C~3~S~-S~,~2;~M~C~I~5~-2~;---:1
MC26-4,Il,13;MCI7-IO;
0
______________~
~W~C~2~~-~1~3
~
1 - ,LJ1
0
(CRS); MC36-5; MC37-2
--------------~I
----------------~----------------------------------_.U
(STC); MC36-1; MC27-3
0
n
,
--------------------~
(STC):
MC2'-I;
22 _ _---'0
1
_
__
_ _PIN
__
,
______________________-:-_____________'.I
OOG(S) ADD. ); MCI7-2,5,13;
MC27 -2,4, 13
0
000. ADD. ); MC25-12;
MC37-4
1
0------------------'.
MC25-11.4
o
(MRFF): MC25-6; MC54-2;
:g~=:.lO, 11; MC26-1,9j
1
n
1
~.- - - - - - - - - - - - - - - - - - - - - - - -
U
1 -----------------------,---------------------------------------------------.,----------------
0
n
(CLF);MC26-IO;MCI5-1;
1
_M_C_I_6-_4_;_M_C_17_-_I_;_Pl_N_·______-=0----------------------~----------____________________~
(~); MC54-6; MC35-IO;
~
______________________________
1 -----------------------'---------------------------------------------------~------------0
(FSFF); MCSS-S,13; MC45-5;
1
_M_C_S_S-_3_,4_;_M_C_7_3_-1_3________~O----------------------~-------------(MCFF); MC54-S; MC25-1;
MC5S-I; MC107-S
______________________________
U
1
~M~C~35~-,,5~;M~C~26--~8~;M~C~4~5~-~I~.,___~0
(FAFF); MC45-6, 2, 4; MC25-3;
:g:;:no,II,12;MC65-1,2;
L
L-J'
(MRFF); MC25-5: MCI5-B,13;
1
_MC
__2_6_-5_,2_,_3____________--;O----------------------~------------------------------------
MCI6-3; MCI7-3; MCSS-2;
L -_ _ _ _ __
____________________________________ ______________
~
1
0
1
_M_C_S_4_-S________________-.:
0 ---:--------------------,---------------------------------------------------~------------(FFF); MCS6-12,1; MC25-9;
MC6S-IO
1 -----------------~----------------------------------------------------
o
(SRQ); IFFF); MCSS-S; PiN 19
1
_M_C_6_6_-1_3_,_3_;M_C_8_S_-_2,_1_4_,_13__~0----------------------.-__________________________________________________~_____________
ISIRITS)); MC2S-IO; MC"-12;
MC54-3; MC73-IO
01
-----------;
~LJ
MC25-8; MC44-13
-(ABFF);
-------------=1
MC4S-8,
13,
12,10;
MC55-5j MC35-8 j MC15-12
0
h
n
n
W
u
u
r1l-______________.J
--1 1
n
u
,
-----------------+--------------------------------------~-----------
(ABFF); MC55-S,3,4: MC4S-.;
1
_M_C_6_4-_3_;_M_C_2S_-_S_;M
__
C_7S_-_4____~0----------------------~----------------__________________________________.,___-------------
-----------------;~I~------~n~~-----'n~----------'n~---------~n~~--------n
(ENFIT2)); MCS5-5
OAK); MCS7-9; PIN 10
0
MC51.8; Me44-!;
MC'5-1; OFF); MC3fi-S, 2;
1
JilCIii-j
0
MC44-2; MC25-2; MC3S-.;
OFF); MC3S-3,4
0
OEN); PIN 8; MCS6-5,S;
MC7S-.: MCB5-S
0
ldC~~-a'
1
1
1
MC75·8; MC73-12
0
;:~~\~~~ 7~;': MO~)8i
!PHLl' PIN 3, MCS7-I,2,6
(IltQFF); MC57-3,4,10;
MC87 -8, 14,.,13; (FLG);
PIN 4· a!!Sll' PIN 6
MC57-5; MC37-12j
Me47 -9,10,12,13
1
0
1
0
~J
u
u
u
u'
Lf
IF THE PROBLEM CANNOT BE FOUND HERE, THERE ARE TWO OTHER LOOPS AVAILABLE WHICH TEST MODE
SELECTION IN A MORE DYNAMIC WAY. THESE ARE OUTLINED AFTER ERROR 4S.
Figure 4-9. Timing Diagram for Error 16.
4-17
12661A
Section IV
(lCFF); MC36-3,4;MC66-4; (MRFF); MC25-6; MC1S-9, 10, 11;
MC28-1, 9; MC54-2; MC97-8; (PRH); Pin 23; MC73...9, 10; MC85-8
(iCF'F); MC36-6, 2; MCl5-2; MC26-4, 11, 13; MC17-10; MC25-13;
(MRfJ!)' MC25-5' MCl5-8 13' MC26-5 2 3
(lOG (B) Addr8ll8d); MC17-2. S, 13; MC27-2, 4,13
il:A
J~~r!51617101112hf4
C~i 516hl01112b
SET SWITCH REGISTER BITS 1 AND 2 UP, PUSH RUN AND SCOPE CHECK
THE FOllOWING,
011/2134
4T6161710111213
TIMING DIAGRAM 17
:r:
i~Ors
4 sI6hlold21a
(PHAf~
4)
416161710ld2T3 4fsI6171011
110,1
t~B
2h'f~'leI.h'l
I
0
I
0
1-
J:
0
I
(100, Addr8ll8d); MC25-12; MC37-4
0
MC25-11,4
0
(ClF); MC26-10; MCl5-1; MCl6-4; MC17-1; Pin 7
0
I
I
I
i
I
I
MCl6-3; MC17-3; MC66-2; MC35-6; MC26-8; MC45-1
0
I
(MCFF); MC54-6; MC25-1; MC107-8; (ABFF); Pin 8; MC45-8, 13, 12, 10;
MC66-6' MC35-8' MC16-12' (lEN)' MC66-S; MC55-1
0
(f.1fFJ!); MC54-6; MC35-10; MC64-6; (ABFF); MC55-8, 3, 4; MC46-8;
MC64-l;MC26-6;MC75-4
0
(FBFF); MC65-8, 13; MC46-6; MC66-3, 4; MC73-13
I
I
I
I
I
0
I
(Am; MC46-6; MC55-10, 12; MC66-2
0
MC55-9; MC67-8
0
(IFF); MC36-3, 4
0
I
I
I
I
I
I
I
I(lFF); MC36-6, 2; MCS6-2; MC64-4
(ENF (T2)); MC65-S; MC47-8; MC37-13; Pin 46
I
I
(m; MCS7-S; MC47...9, 10, 12, 13; MC37...12
0
I
~
h.J
I
I
I
I
I
I
,•
•I
I
I
I
I
I
I
I
I
I
I
I
I
MC65-8,9
0
(FFF); MC66-B; MC66-13,3; MCB5-2,14,13; (SRO); Pin 19;
MC75-B; MC73... 12
I
(m); MC66-12; MC66-10; MC26-9; MC86-6; MC76-9; (PRl);
MCB5-6,1,7,9jPin3
MC73-8; MC67-1
(lROFF); MC57-3, 4,10; MC87-8. 14.9,13; (FlG); Pin 4;
(I RO); Pin 6
(lROFF); MC57-6,2
I
0
(lAK); Pin 10; MC57-9; MC44-2; MC26-2; MC36-9
MC57...B; MC44-1; MC35-1; MC25-3; MC45-4
I
•
I
1-
0-
I
I
.
I
I
I
I
0
I
J
0
0
I
I
I
T5
,I
0
I-
,I
I
I
I
0
I
I
0
0
I
,
I
I
I
I
I
I
I
I
I
I
I
•
I
l
JI
,I
T5
I
I
I
L
t
I
:
J
I
I
I
I
I
I
I
Figure 4-10. Timing Diagram for Error 17.
4-18
12661A
Section IV
SET SWITCH REGISTER BITS 1 AND 2 UP. PUSH RUN AND SCOPE CHECK THE FOllOWING.
ClC
STF
ClF
STC
1314151617101112bl4151617101,12134151617101,1213 415161do!' 121
{lOG (B) ADD.);
MC17-2,5;
MC27-2.4
~J
(ClC, ADD.);
MC36-5;
MC37-2
~lJ
(lCFF);
MC36-3,4;
MC66-4
~l
(iCFi=); MC2fr4,
n. 13, MC15-2;
MC36-2,6
~J
(STF);
MC2&-3;
MC16-2
0
________
I
(STF);
MC55-3;
MC2&-6
LJ
0
I
(ClF);
MC15-1;
MC16-4
0
(ClF);
MC45-12;
MC15-12
0
(ABFF); MC55-6;
MC45-9;
MC64·3
0
(ABFF);
MC45-8;
MC55-5
I
0
(STC);
MC36-1;
MC27-3
I
~n~
LJ
LJ
L
__________________________
u
________~________~n~______~------_
u
0
u
Figure 4-11. Timing Diagram for Error 34.
4-19
12661A
Section IV
SET SWITCH REGISTER BITS 1 AND 2 UP AND PUSH RUN. THE ERROR MESSAGE SHOULD REPEAT.
PUSH RUN AGAIN AND SCOPE CHECK THE FOLLOWING.
TIMING DIAGRAMS
35 THROUGH 44
THIS TEST MAY ALSO BE DONE BY SINGLE CYCLING THROUGH THE LOOP.
THERE ARE 57 CYCLES IN THE LOOP SO SINGLE CYCLING TAKES TIME.
REFER TO TABLES BELOW FOR PIN NUMBERS AND TIMING.
PIN NUMBERS WITH AN ASTRICK (0) ARE THE 48-PIN CONNECTOR.
,
,
,
1SWord Latch, (100);
MC23-4,13; MC43-4,13
(11
0
1sWord Buffer Output
(1) Output & Input Bit
------
A
0
B
0
(T5), Input Bit Latch;
MC103-4,13; MC104-4,13 0
(1) Input Bit FF
,
,
,
,
,
,
,
0
(T2), Alarm FF Latch;
MC93-4,13; MC94-4,13
(1) Alarm FF
0
0
(1) Alarm FF Inverted
,
,
I
0
Alarm Signal, MC55-4;
MC75-4; (1) MC74 Input
0
Alarm Signal I nvertad;
MC75-3; MC74-S
0
(CLF); MC45-12; Me1512· MC16-3· M 1 -
0
(CLF); MC15-1; MC16-4
(ABFF); MC55-6;
MC64-3; MC45-9
., ,
C
,
' ,
D
,
E
0
ERROR NUMBER
(1 )
35
1 St
Word
BIT 0; MC23-8; 01·B;
l5uffer Output 031-C; MCl03-2
37
36
BIT 1; MC23014; 010-11;
032-C; MCl03-3
BIT 2; MC2301; a&a;
033-C; MCl03-6
40
41
BIT 3; MC43-8; 011-11;
BIT 4; MC43-11; 01Bo11
Q34-C; MCl03-7
Q3B-C; MC104-2
42
43
BIT 5; MC43-14; 02Q.B; BIT 6; MC43-1; 01Bo11;
Q37-C; MCl04-3
036.c; MC104..&
44
TIME
07-C; PIN 0 D;
PI N • 16; 031·B
01O-C; PIN 0 6;
PIN·T;Q32·B
0B.c; PI N
0 4;
PIN' 17; Q33-B
017-C; PIN' K;
PIN' U; Q34-B
0IB-C; PIN' 9;
PIN' W; Q3Bo11
02o.c; PIN' 10;
PIN' 19; Q37-11
01U; PIN' L;
PIN'V;036-B
Q9-C; PIN' E;
Input Bit
Flip-Flop
MCl03-16; MC93-2;
MC93-12
MCl03-16; MCS3-3;
MC93-2
MCl03-1D; MC93-6;
MCB3-S
MCl03-8; MCS3-7;
MCB3-4
MCl04-16;MC94·2;
MCB4·12
MC104-16; MCII4-3;
MCB4-2
MCl04-1D; MCII4-6;
MCB4-S
MCl04-9; MC94-7;
MCB4-4
Alarm
Flip-Flop
MCS3-16; MC1D6-B
MCS3-16; MC1D6-14
MC93-1D;MC96-8
MCS3-S; MC96-14
MC94·16; MC95-11
MC94-16; MC96·14
MC94-10; MCl06-11
MC84-B; MC1D6-14
Alarm FF
Inverted
MC93-1; MCB3-13
MCS3-14; MCB3-1
MCS3-"; MC83-10
MCS3·B; MCB3-5
MC94·1; MCB4·13
MC94·14;MCB4-1
MCB4-11; MCB4-1D
MC94-B; MCB4-6
MC74-B; MCB3-11;
MC73-2
MC74-4; MCB3-3;
MC73·1
MC74-12; MC83-B;
MC74·,,; MC83-B;
MC74-3;MCB4-11
MC74· 2; MC84-3
MC74-1; MC84-B
MC74-B; MCII4-6
MC73-5
MC73-4
PIN' lB; Q35-B
NUMBER
OF
MACHINE
f'Vf"
BIT 7; MC23-11; 09011;
Q36.c; MC 104-7
Output and
Input Bit
MC 74 Input
I
B
A
~~
TIME (MSEC)
FOR
~114 OR 2115
COMPUTERS
FOR
2116
COMPUTER
A
29
58.0
46.4
B
49
98.0
7S.4
C
5/8
1.25
1.0
D
77 3/S
154.75
123.S
E
25 3/4
51.5
41.2
F
1/S
.250
.200
Figure 4-12. Timing Diagram
for Errors 35 through 44.
4-20
12661A
Section IV
SET SWITCH REGISTER BITS 0, I, Z, 3, 6, 7, B, 10 UP (2717) AND LOAD ADDRESS. CLEAR SWITCH REGISTER AND
SET BITS I AND Z UP. PUSH RUN AND SCOPE CHECK THE FOLLOWING.
CLC 0 (CRS)
I 3 14 I 5 Is
(CRS); MC37-1, 5; MCZ7-B;
PIN 13
0
MC3e~5i
MC37-2.15;
MCZ7-10
0
(STC); MCZ7-1; PIN Z2
0
/7
CLF
10 II I 2 I 3 14 I 5 I 6 I
OTA
d
0 I I I 2 I 3 14 I 5 16 I
STC
do I 11 2
I3
Jl
lJ
________________________~h~______________
u
Me3S-l: MC27-3
0
0
l
0
J
0
________~n~______________+_--------------
(JCFF); MCSS-4; MC36-3,4
liCIT); MC25-13; MCI7-10;
MC26-13.11,4; MC15-2;
MC36-6.2
(CLF); MCZ6-10; MCIS-I;
MC16-4; MeI7-1; PIN 7
MC66-2; MC35-5; Met6-3;
MC17-3
0
MC3tl-12; MC36-13;
MC37-3; MC27-II,
MC2S-II,4
0
(MRFF); MC25-6; MCIS-9,10.II;
MC26-1, 9; MCS4-2; Meg7 -8;
(MCFF); MCS4-S; MC25-1;
MeSS-!; MCI07-8; MC25-9
(MRFF); MCI5-B,13; MC25-S;
MC26-5; (MCFF); MC54-6j
MC64-5; MC35-10
(SIR(TS)); MC54-3; MC44-12;
MC25-10; MC47-6; MC37-11;
PIN 32
u
L
________________~IlL______~----------------
u
0
(00); MC27-12; PIN 20
________________~IlL______
7_---------------
0
0
0
~
0
U
MC44-13; MC25-B; MC47-1, 2,4, 5;
(Ion; Me17-g, 12; MC16-12;
MC9'l-14,2j PIN 24
u
0
1100, ADD.); MC2S-12;
MC46-10,13
MC37-10
u
0
(JOG(B)); MC27-Z,4, 13;
MCI7-2,S, 13, MC16-6
LIB
4 15 I 6 I 7 10 II Iz I 3 14 I , I 61 71 0 II I 2 I
n
u
n
n
n
u
u
U
0
n
0
u
MCJ7-11; Me16-I3
MCI7-B
0
Figure 4-13. Set Control Timing Diagram
4-21
12661A
Section IV
SET SWITCH REGISl"ER BITS 0, 2, 3, 4, 6. 7. 8, 10 UP (2'135) AND LOAD ADDRESS. CLEAR SWITCH REGISTER AND
SET SWITCH REGISTER BITS 1 AND 2 UP. PUSH RUN AND SCOPE CHECK THE FOLWWING.
OTA
CLC,
LIB
o 1I 121 31.ls16171 0 1I 12 3 1.,
(CRS); MC37-I,S;
MC27 -8, PIN 13
MC36-5; MC37-2,6;
MC2?-IO
nCFF); MC66-4;
MC36-3,4
(ie""'; MC25-13; Mel7-tO;
MC26-13, 11,4; MC15-2;
MC36-S 2
0
0
I
n
I
U
I
0
I
MC37-3j MC27-11; MC2S-11,14
0
(100; MC17-9,12j Met6-12;
I
MC97-14,2; PIN 24
0
I
6
17
I I I
0
I
2
n
n
U
L
I
I
I
I
I
II
L---.J
I
I
0
I
(!dRFF); MClS-8,13; MC26-l5;
MC2,-S
0
('F"M'); MCS6-l2; MC65-1O;
MC25-9
0
(S1R(T5)); MC54-3; MC44-l2;
MC2S-,
0
(S1R(TS); MC54-3; MC44-12;
MC25-10; MC47-6j MC37-11;
PIN 32
1'
I
I
0
(MRFF); MC25-S; MC97 -R;
MC26-1,9, MCS4-2; MClS-9
3
I
nOll; MClS-ll; MC17-11,8;
MetS-I3
2
I
0
MC46-10,13
I
I
noo); MC27-l2; PIN 20
(100 ADD); MC35-12; MC36-13j
I I I I.
I
0
nTIOAIm); MC2,-12
0
I
I
0
I
71
I
0
nOGIR)); MC27 -2,',13;
MCI? -2, 5,13; MC 16-6
' I .1
I
I
I
0
I
I
n
n
n
u
u
U
I
I
(MCFF); MC54-S; MC55-1;
MC25-l
0
(Ml!i'l'); MC54-6; MC64-5;
Me3S-tO
0
I
Figure 4-14. Mode Assignment Timing Diagram
4-22
Section IV
12661A
- )
)
-
)
111111111111111111111111
Figure 4-15. DVS Program Card, Parts Location
4-23
12661A
Section V
SECTION V
REPLACEABLE PARTS
5-1.
5-3.
INTRODUCTION
5-2.
This section contains a list of information for
ordering replacement parts. Table 5-1 lists parts
alphanumerically by reference designation. It also
provides:
a.
b.
a.
Instrument model number.
b.
Instrument serial number.
c.
Description of the part.
d.
Function and location of the part.
A general description of the parts.
d. Man u fa c t u r e r 's part, stock, or drawing
number.
e.
5-4 . When ordering replacement parts, each part
must be identified by the Hewlett-Packard part number. To order a part that is not listed in the tables,
include the following information:
HP part numbers.
c. Typical manufacturer of the part expressed as
a five-digit code (a list of manufacturers and their
code numbers appears in Table 5-2).
Total quantities used.
ORDERING INFORMATION
5-5. Address your order or inquiry to your local
Hewlett-Packard Sales and Service OffIce (listed at
the rear of this manual).
5-6. If parts are ordered from the original manufacturer, a complete description should be included
with each manufacturer's part number. Many numbers listed are type numbers only, and descriptions
are needed to facilitate selection.
REFERENCE DESIGNATORS
A
B
BT
C
CP
CR
OL
OS
E
assembly
motor
battery
capacitor
coupler
diode
= delay line
device signaling
mise electronic part
F
FL
J
K
L
LS
M
MK
MP
fuse
Filter
jack
relay
inductor
loud speaker
meter
microphone
mechanical part
H
HOW
HEX
HG
HR
Hz
henries
hardware
hexagonal
mercury
hour(s)
Hertz
P
Q
R
RT
S
T
TB
TP
U
plug
transistor
V
resistor
thermistor
switch
VR
transformer
W
X
Y
Z
terminal board
test point
integrated circuit
ABBREVIATIONS
A
AFC
AMPL
BFO
amperes
automatic frequency
control
amplifier
BECU
BH
BP
BRS
BWO
beat frequency oscillator
berylllum copper
binder head
bandpass
brass
backward wave oscl1Jator
CCW
CER
CMO
COEF
COM
CaMP
COMPL
CONN
CP
CRT
CW
counterclockwise
ceramic
cabinet mount only
coefficient
common
composition
complete
connector
cadmium plate
cathode-ray tube
clockwise
DE PC
DR
deposited carbon
drive
ELECT
ENCAP
EXT
electrolytic
encapsulated
external
F
FH
FILH
FXO
farads
flat head
Fillister head
fixed
G
GE
GL
GRO
giga (l09)
germanium
glass
1II0und(ed)
IF
IMPG
INCO
INCL
INS
INT
K
LH
LIN
LKWASH
·LOG
LPF
N/C
NE
NIP!'
normally open
nominal
negative positive
NPN
ficient)
negative-positive-
=
=
unpregaated
incandescent
include(s)
insulation(ed)
internal
kilo = 1000
left hand
linear taper
lock washer
logarithmic taper
low pass filter
nano (10-9 )
normally closed
neon
nickel plate
RMO
RMS
RWV
zero (zero ternp~rature
intermediate freq
milli = 10- 3
M
rrieg = 106
MEG
METFLM
metal film
MET OX
metallic oxide
MFR
= manu facturer
MH •.
=; mega Hertz
MINAT
miniature
momentary
MOM
MOS
metalized
substrate
mounting
MTG
"mylar"
MY
N
N/O
NOM
NPO
coef·
negative
NRFR
NSR
OBO
OH
OX
not recommended
for field replacement
not separately
replaceable
order by
description
oval head
oxide
P
PC
PF
peak
printed circuit
picofarads = 10- 12
farads
PH BRZ; phosphor bronze
PHL
Phillips
PIV
peak inverse
PNP
P/O
POLY
PORe
pas
POT
PP
PT
PWV
RECT
RF
RH
voltage
positive-negativepositive
part of
polystrene
porcelain
position(s)
potentiometer
peak-to-peak
point
peak working voltage
rectifier
radio frequency
round head or
right hand
SoB
SCR
SE
SECT
SEMICON
SI
SIL
SL
SPG
SPL
SST
SR
STL
TA
TO
TGL
THO
Tl
TaL
TRIM
TWT
vacuum tube.
neon bulb,
photocell, etc.
voltage
regulator
cable
socket
crystal
tuned cavity.
network
rack mount only
root·mean square
reverse working
voltage
slow-blow
screw
selenium
section(s)
semiconductor
silicon
silver
slide
spring
special
Stainless steel
split ring
steel
tantalum
time delay
toggle
thread
titanium
tolerance
trimmer
traveling wave
tube
tl
micro = 10-6
VAR
VOCW
variable
dc working volts
WI
W
WIV
with
watts
working inverse
voltage
wirewound
without
WW
WIO
5-1
12661A
Section V
Table 5-2. Code List of Manufacturers
MFR. NO.
01121
01295
04404
04713
07263
12040
28480
56289
MANUFACTURER
Allen Bradley Co.
Texas Instruments Inc. , Semiconductor Components Div.
Hewlett-Packard Company, Automatic Measurement Div.
Motorola Semiconductor Prod. Inc.
Fairchild Camera & Inst. Corp., Semiconductor Div.
National Semiconductor
Hewlett- Packard Company
Sprague Electric Co.
ADDRESS
Milwaukee, Wis. 53204
Dallas, Texas 75231
Palo Alto, Calif. 94306
Phoenix, Ariz. 85008
Mountain View, Calif. 94040
Danbury, Conn. 06810
Palo Alto, Calif. 94304
N. Adams, Mass. 01247
5-3/5-4
12661A
Appendix A
APPENDIX A
LI STING
FOR
HP 20436 DIAGNOSTIC PROGRAM
FOR THE
MO DEL 12661A
DIG ITAL VOLTAGE SOURCE PROGRAMMER
INTERFACE KIT
PAGE 0001
ASM8,A,l,C
0001
**
NO ERROHS*
A-I
Appendix A
. 12661A
\,i0j()1*
~00~*12661A
0003*
~004*MAkCH
UVS
P~OGHAM
CARD
14. 1969
0016!::)*
~i606*~TAkTING
icJ007*
000~*lHi
~~09*
OCTAL ADDRESS
= 1160
FOLLOWING SWITCH HEGISTER SETTINGS
AWE USED FOR PROGHAM CONtROL
lOiD10*
0011**~IT j()
001~*~lT 1
0t113*~IT l
0014*~IT 3
0161~*~IT
DIAGNO~TIC
4
1&010*
=1
=1
=1
=1
=1
-> HALT AT BEGINNING Of PROGRAM
-> HALT AT THIS PT. IN PROGRAM
-> LOOP FOk
->
->
SCOPE-T~ST
SK1P INITIAL TURN-ON TEST
LOOP £NT1RE BA~IC TESt
1')1017*
"'IOIH*MAIN PHUGkAM
0li?1'1*
0162tt
~01i6ftj
01&21
~~101O
11)-,122
\6ii110,;)
00~j
100 1 i6!)
IIlkH 10
001::4
01625
ki0~b
"litH 1 t{)
ItllOlll
0"27
0028
1U~11!)
011129
00311:1
iii 1.1 3 1
02000
124115
00JJtD6
1/103440
\O~115
I/lc0t11O HH70t6
003~
~Jt::1D02
011133
01634
0(635
0036
0037
0k13b
~2011lj
062164
06b146
020~'+
1141fd2
"U~1c16
o/J~16167
1626fd13
j()62012
i603~
01£)4~
0041
0042
011143
0i044
004';)
0ib4c
00,+7
0iO'+H
0049
005\0
00!)1
0052
00!:13
"'0';)4
0055
005h
011157
A- 2
PAGE~
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06616~
11411112
0211'30 "Hb~11
k!J~i031 06241",
"'2032 ""b641t16
~t?033
114104
ORG 10ftJB
JMP 115~. I
ORG 105t:t
OH X
ORG IltiHi
DEF ERROR
OEf INTR
QRG 115~
OEF PAGE~
ORG 2001it~
CLC littC
JSB EOL
LOA ML.l
LOB MAUl
JSB 1028.1
JSB EOl
JMP *+5
LOA *+3
LOB *+2
CLC Ib.C
HLT 0
LOB M67
LOA HIS
STA *+l
LOA HI
STA 1108
ISZ *-1
INA
INB.SlB
..,2
JMP
J5B
LOA
LOB
JSB
JSI3
LOA
LOB
JSB
*-4
EOL
ML2
MAD2
ORIGIN OF A~SOLUTE PROGriAM
MAIN PROGRAM LINKAGE
fIRST AVAIL MEMORY AfTER PROGkA
OE.fINES INTERRUPT LINKAGE
ILLEGAL INTERRUPt
LEGAL INTERkUPT
MAIN PROGRAM LINKAGE
DEFINES STARTING PT.
PROGRAM STARTING PT.
INTERRUPT SYSTEM OfF
LINE fEED
PRINT 1ST M~SSAGE
12661A VERIFICATION
PROGRAM - TTY
LINE fEED
HALT AT ~EGINNING
OF' PROGRAM
1120ftJ0
PREPARE
tRAP
fOR
ILLEGAL
INtERRUPT
fkOM
ANY
DEVICE
102B. I
LINt. FEEO
PRINT
1/0 CHANNEL?
TTY LINKAGE
E.OL
RLI
RAOI
U4B.l
fo
0621
0622
0623
Qi624
03225 ·017272
~3226 102200
03227 027231
03230 011306
03231 017164
03232 063207
Qi3233 880010
03234 027226
03235 063206
03236 0080111>
03237 182OO0
03248 002411>'"
O3241 127212
SfC3
JSB
SF'C
JMP
JSB
JSB
LOA
SLA
JMP
LOA
SLA
HLT
CLA
JMP
ERAO
0
*.2
ERROR
MODE
I:U T2
SfC3
dIll
8625
"
0626
0627
ST~Fl,I
062ij*
0629*STATUS FLAG 2ND WO~D ROUTINE
8(311)*
0631 03242 '''0008O ~TAf2 NOP
JSB ERAO
0632 03243 11>17272
0633 03244 102380 ~fS4 SfS 0
,JMP *.2
0634 03245 027247
0635 03246 817306
JSB ERROR
0636 103247 017164
JSB MODE
0637 11>3250 063207
LOA BIl2
0638 03251 00011>1~
SLA
0639 03252 ~27244
JMP SfS4
0640 03253 06321/)6
LUA 8tll
0641 03254 00"'01~
SLA
8642 03255 1020"'~
HLT 16
0643 163256 017272
JSB E~AD
0644 03257 1~2200 SfC4 SfC II>
121645 11>3260 01731/)6
JSB ERROR
0646 ~3261 011164
JSB MODE
0647 ~3262 1163207
LOA BIl2
0648 03263 0000116
SLA
JMP SfC4
0649 03264 021257
0651/) 03265 0632166
LOA !:SlTl
SLA
0651 03266 0000116
0652 103267 1020016
HLT 0
0653 03;.:70 002401/)
CLA
0654 IrB271 127242
JMP ST~F2, I
0655*
0656* INCREMENT EHROH NUMBER ROUTINE
0657*
0658 03272 0000100 ERAO NOP
0659 103273 072430
STA ASI
0660 03214 076435
~TB BSl
LOA ERRI
0661 11>3275 06331214
STA EROAT
0662 11>3216 013337
iNA
121663 03277 002011>4
0664 103300 073304
STA ERRl
0665 03301 962430
l.OA ASl
0666 03j02 066435
LOB 8S1
JMP EHAO,I
0667 03303 127272
0668 103304 0000"'0 t:RRI OCT 0
0669 10 33tr!15 0000010 ~HRl OCT 16
0670*
0671*ERRORPHINTOUT HOUTINE
INCREMENT ERROR MESSAGE
IS STAtUS FLAG SET?
NO.
YES. SfC-SKIP-FLAG CLEAR-ERROR
STORE SWITCH REGISTER
LOOP fOR SCOPE TEST?
YES.
NO.
HALT?
YES.
EXIT SUBROUTINE
ENTER SUBROUTINE
INCREMENT-ERROR MESSAGE
IS StAtuS fLAG CLEAR?
NO.
YES. SfS-SKIP-fLAG SET-ERROR
STORE SWITCH REGISTEH
LOOP?
YES.
NO.
HALT?
YES.
NO. INC~EMENT ERROR
IS STATUS FLAG SET?
NO. Sft-NO-SKIP-fLAG SET-ERROR
YES.
LOOP?
YES.
NO.
HALT?
YES.
EXIT SUBROUTINE
INCREM~NT/ERROR STORE ROUTINE
STORE A
STORE tt
LOAD CURRENT ERROR
STORE
INCREMENT ERROR
STORE NEW HUMBER
~ESTORE A
REStORE e
EXIT
ERROR STORAGE
I NIT lAL -ERROR
A-IS
Appendix A
1266B
~67~it
0673
~)614
0b1~
0616
0677
~61ts
0619
k}ol:llll
06b1
0682
0683
0684
06t15
0686
0687
0688
061:lY
0690
\16<,11
069~
k)69]
0694
069':>
0696
!lJt:.97
I/:ltl'18
03306
033167
03310
03311
03312
03313
03314
03315
163316
03317
03320
163321
03322
1IJ3323
03324
03325
03326
03327
03331{)
tt.3331
03332
~3333
03334
0333!::i
03336
163337
000000
063207
000010
027336
1031011'
063337
01U 700
012413
017406
11'70353
063337
001127
001222
0174'tJ6
076354
001700
001222
017400
076355
062356
066347
114102
1063331
1020100
127306
000000
NOP
LDA IjlT t::
SLA
..JMP t:1
eLf o
LOA EHUll
ALf
AND MSK3
JSB .2NUM
STB "41:.59+3
LOA I:.HOAT
ALF,ALF
kAL,HAL
JSB .~NUM
E~kOR
SUBROUTINE
DISABLE INTt:.R~UPT SYSTEM
LOAD E~HOR NUMBER IN A
PACK
ERROH
NUMBER
AND
STORE
IT IN THE
ER~Ok
MESSAGE
SlB Mt:.!;)9+4
ALf
HAL,I' 001222
0716 03356 017406
0711 163357 107636-(
0718 03360 062436
0719 163361 00170'"
072v.'1 0J362 012413
0721 03363 1617406
0722 ",3364 076377
0723 103365 062436
0724 163366 0131727
1/)72':> 03367 010::)1222
0126 1t3310 017406
0727 03371 1676400
0728 03312 001700
A-16
OAT
~RINTOUT
NOP
STb B!;)2
STA AS4
ALf
AND MSK3
JSb .2NUM
ST8 MESI0+5
LDA AS4
ALF,ALf
HAL,RAL
JSB .2NUM
STb Mt:.!;)1.,+6
OUTPUT/INPUT PRINTOUT ROUTINE
STORE B
STORE A
PACK
OUTPUT
WORD
AND
STORE
IT IN
THE
ERROR
MESSAGE
ALf
RAL,~AL
JSt; .2NUM
STB Mt.S10+7
LOA t;S2
AL"-
AND MSK3
JSb .2NUM
SlB MES11I+1S
LOA JJS2
ALf,ALf
RAL,HAl.
..JSti .c?NUM
STB MI::Sll6+16
ALf
PACK
INPUT
WORD
AND
STORE
. IT IN
THE
ERkOR
MESSAGE
12661A
Appendix A
PAuE elm 7 "01
0729 O3373 001222
0730 03374 017406
o131 k)3315 076401
0732 03376 062402
0133 03117 0663~7
0134 03400 1141102
0135 03401 016417
0136 03402 102000
0137 03403 O62433
0138 03404 066436
0139 03405 127340
0140*
0741*PACK TwO ASCII
O142*
0743 03400 0k)0000
0144 03407 O12434
0745 ~J4h' 00132J
0746 ~3411 0013016
0747 1113412 01~412
O748 03413 O32414
014Y 03414 001127
075'" k)3415 0700-'1
O751 03410 062434
0152 03411 012412
0753 034216 0324i4
0754 03421 03101601
0755 163422 070001
0156 03423 06~434
0757 03424 127400
0758*
0759*
07616
~342!) 000000
0761 03426 11163432
0762 03427 .07i0000
0103 03430 90~401t)
0764 03431 121425
0765 03432 114110
0766*
0767*
0768 03433 000000
0769 103434 063't37
07716 03435 070000
0771 03436 127433
0712 03437 114111
0173*
0774*
0115 03440 001t)000
0716 03441 -'63440
0777 03442 0102004
0778 103443 1602004
0179 03444 0734416
0780 0344~ 127440
RAL,RAL
JSS .2NUM
5TS ME.S10+17
LOA ML10
LOB MAOIk)
JSB 1028,1
J5B EOL
HLT 0
LOA AS4
LOB BS2
JMP OAT,I
NUM~lkS
PkINT ERROR MESSAGE
ouTpUT •
INPUT •
LINE FEEO
HALT AFTER ERROR
RESTORE A
RE~TORE 8
EXIT SU8ROUTINE
SU~~OUTINE
.2NUM NOP
STA AS~
RAR,J(AR
RAR
AND MSK2
lOR Cl
ALF,ALF
!iTA 1LOA ASS
AND MSK2
lOR Cl
lOR 1
STA 1
LOA ASS
JMP .~NUM,I
ENTE~ SUBRO~TINE
NOP
LOA
STA1 STA
CLA
JMP
I:.RJMP JSB
EHJMP
0
ILLEGAL INTERRUPT ROYTIN~
STORE ERROR
.
ROUTINE IN OVSI ADDRESS
I8AOtl
1108, I
EXIT SUBROUTINE
IBAO STATEMENT
18AO
10K
STA2
S~OK
INTk
STORE A
FORMAT
FIRST
NUMBER
STORE IT IN 8 REG
FORMAT
~ECONO
NUM8ER
PACK BOTH
NUMBERS INTO B
RESTORE A
Exli SUBROUTINE
NOP
LOA S~OK
STA 0
JMP IOK,1
JSS 1118,1
LEGAL INTERRUPT ~OUTINE
STOHE LEGAL JUMP
ROUTINE IN OVSI ADDRESS
EXIT SUBROUTINE
10K STATEMENT
NOP
LOA II'4TR
INA
INA.
STA II'4TR
JMP INT~'I
LEGAL JUMP ROUTINE
EQUIVALENT
TO A
JMP •• 2
IN DVSI ADDRESS
EXIT TO NEW ADDRESS
07~1*
0782*
0783 0344b 000000
0784 03447 002400
0185 03450 1067itJ.0
CONTR NOP
CLA
CLC4 CLC 0
INTERRUPT CONTROL SUBROUTINE
USING STF ANO STC to tEST
A-17
Appendix A
I266IA
PAGE 0018 .,01
01~o
0181
0188
0189
01~~
01~1
01~2
\'i193
"1~4
0795
01Y6
!b797
079d
079'1
0~fI)\1
fl)801
fl)816c
vH:l03
fl)1j0,+
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fl)dfl)6
0HI01
Ir1dl"':i
i6H~~
",811.1
tl8l]
t::)8lc.:
03451
163452
03453
03454
03455
03456
163451
03460
103461
03462
I{)34b3
1113464
03465
eJ466
03461
I{)34116
\13'+71
03472
163473
103474
0347S
03476
03477
",35160
1035161
\135102
"'35~3
103100
102621
011272
017425
1021k)1O
000016k)
0""'01616
10210k)
1021016
017t.7t.
011433
h'J2700
1tl101tI16k)16
~1O!tl16101O
10113106
0(11)00(i1
102 }tI)i6
1011272
"17425
l1Ob71C11t
U21ttJIO
11t1t1100
0f1)k)0016
16(611)161616
1k)21f1)l0
k)17272
1611403)
10.j} 11)10
0dlJ
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~814
1035105 01010161010
fl)3S1I:)6 0f1)lI)t3k) 0
"'35107 1617306
1035116 1016010100
kl3S11 k)fI)lO~101O
103512 10~1101O
103513 0172"1'2
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03515 lk)6111)11)
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",35210 lI/l27k)1/)
",3521 0(11)V1 II) 10
0815
0H16
k>d17
k')1; 18
o/Jdl'1
k18210
01;21
0822
IOH23
~1j2'+
I{)8e'5
0~26
0821
'olI1::I2t1
k:..82~
08316
0831
083i
IOd33
0834
10835
0836*
!:>
!:>TF '"
rF 3
~fC7
CLF7
STC It?
NOP
NOP
STf II'l
JSI:i ~~AU
JSd 10K
CLF ~
NOP
NOI-JSH t.r
103634 06S741
1i)363S tll 7'::J 744
03636 ftJ71fJ742
~3637 071fJ74j
",912
1L'364v) ~b'::"''+c
~90H
0~"'9
1.1910
0913
(0914
~~"i
15
(O~lb
~136'+ 1 11lJ67k'!0
1&13642 106hltl!O
ItJ643 1 II.lb 0 w1t(l
~364'+ 11&127kH1
11'3645 ~ 11706
"'3646 10?:)1tJ~
ki3647 '(,72 .. 32
tll3650 kl17164
163651 tll6J21d7
!:>UOIC LUA ML6
LOH MAU6
J~1:l
::'111 CUMPI-<
1-'1J
CLC7
OTH~
urbo
::,TC11tJ
LUI:l uuT
CLC ItJ
Ulb !d
ufb 10
~TC
JS~
1b36S4 "'6.Jcl6o
tl92~
t030~'::i
1(,~1Ii{l1"
~LA
~926
"'J6~b
036~7
IItl~\lI01()
HLT
Lurl
LiJA
CPti
JMP
JSH
LUA
10k
CPA
JMP
0927
",92t!
11929
0930
0931
i£l93c
0933
~934
ib935
10936
0937
093H
0939
16940
0941
0942
0943
0944
0945
10946
0947
094H
0949
13950
0951
"'iil~01;tl
k':;6~J
'(It!.n';)l
I{Ji!.76b4
1013663 1U17.,;,+1U
0360'+ ;,)01743
~j66~ k-317!::Jl
iIl3666 1O~1 (47
eJ667 ,;27701
1()3672
011144
03074 VloC,14j
'1;3677 ~757'+c:
~3711
t
Hd~
'tJ"5742
09':>4
VJ371i!. ",o}l':jj
0955
03713 071(04
iO:s714 16'::J764
LOOP FOH Tt..S TI NGr
YES.
NO.
HALT/
Yt:.~.
A::i3
LOAU INPUT IN \j
LOAU OUTPUT COMPAHISON IN A
OUTPUT
INPUTi'
Y'E.S.
NO. t:.RROH PkiNTOUT
cH~
CPR
~+t!.
vAT
CUMPH
MSK'+
ENIU
F1NIS
I:lL~,tlL::>
0\11':>.u t: \0
103610 iUi05vli00
0Y52
SET UP AND
~TOI.H:. 1ST
OUTPuT FOH
COMPM5744
~3671/J
LIA
o.i
ut.LAY
JSI:l MOUE
LOA tH T2
;)LA
J"'ll-' ~12
LUA tH Tl
~66432
iIli:7640
ia6i!.3.JIU
l()o03V'1
114il()i!.
~371
037 lV? 1()0~741
0956
LlA2
IdJbbl
t0366~
1
J::>b t:.OL
11L1 J
LUH LOOPl
~Tt:l LOOP
LUI; I 1~ I T
~Tt:I CI-'W
~Ttj OUT
101.J17
V}-11b
0919
0920
.3921
\'1'122
\t'JY23
\t'J924
~36"2
lIt)~~,
-
ME.SSAuE
CONNt:.CT ~LU(j NO. 3
ANU PU!:>11 HUN
~HINT
~I!::J
tjLS
STb UUT
JM~ PTJ
LOA ML7
LOti MAU7
JS~ 11Oi!.B.l
JS~ t..UL
HLT 7
LUb LuOP2
STb LOOP
LOB INlT
~Tt1 uuT
LOA CMP8f
5TA AU(,;MP
LI)t:$ AUCMP, I
MASK BIT 4
STOHE IN OUTPUT COMPARI~ON
SHIFT COMPAwlSON
OUTpUT fROM ~OSITIONS
11'-4 TO 3-7 AND STOHt::
IN OUTPuT LOCATION
NE.XT OUTPUT
PHINT MESSAGE CONNECT pLUG NO. 4
AND PUSH RUN
HALT TU CONNECT PLUG NO. 4
TEST LOOP CONO IT ION
!:>t::T UP AND STORE
l~T OUTPuT wOHD
LOAD AOOHESS OF I~T
COMPARISON wOHD AND STOHE
LUAU OUTPUT COMPARISON INTO tt
Appendix A
12661A
PAGE
0957
0958
0959
09610
09b1
09b2
0963
0964
0965
0966
0~67
0968
0969
097111
0971
0972
0973
0974
097~
0976
0977
097ij
0979
09810
0981
0982
0983
0984
0985
0986
091:17*
0988
0989
099",
0991
1t1992*
0993
0994
099~
0996
e997
0998
",999
1O~21
,,01
03715 ~7':J7~~
11)3716 06~74~
1ei3117 1~6''1011)
1037210 116601010
03721 11066101r!l
037~2 10c71t1!o1
03723 017766
03724 102501t1
5TH
LOt;
(;LC11O CLC
OTb7 OTb
OHH~
OTH
~TClI STc
CPR
OuT
10
10
J5~
10
UlLA'f
LlAJ
LlA
III
07243~
~TA
A~d
03726 1017l 64
03727 "'63i' 10 7
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k'J3732 106J2it,6
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03746 Cb7'i7"+c.
'lJ37~7 1661704
037S1r!l 'lJ0211104
1lJ3751 -.}71764
'lJ3752 027714
JSti
LUA
SLA
JMP
LOA
SLA
HLT
LOB
LOA
CPtj
JMfJ
JS8
LOti
CPt!
JMP
INb
STb
LOA
INA
STA
JMP
MOUt:
HIl2
10372~
03753
1lI3754
03755
03756
10276'+10
(1)27714
1027t:J72
117716
LuOPI
LOOP2
LOOP3
CONu2
~3757
k)~6'+tOlt1
I-'T2
03760 licl67101t1
k13701 1"'b6~0
1d370~ IIt160"''''
~3703 1d00001t!l
0370"+ 0001.1130
1d3165 'lJ21'?7~
OT139
UTbllO
LuGI-'
III
LOAU
ANU
uUTPUT
21'40 wORD
OISABLl MODE ASSIGNMENT
TIME. OlLAY FOR BUFFERS TO SETTLt::.
PLACl;. lOtH wOHI) IN A REG
~TOI(E INPUT
LOOP FOR TlST1
PTt::
YE::~.
~l
10
AS3
CfJR
CPR
NO.
HAL T'?
'flS.
LOAD INPUT IN b
LOAD ouTPUT COMPAHISON IN A
INPUT1
OUTPuT
.+~
'fE~.
Tl
UAT
OuT
ENU)
uuIC,1
OUT
AUCMP
AUCMfJ
PTS
JMP PTJ
JMP I-'T':)
JMP PTl
J5jj T~T~tl
=
NO. f::RROR PHINTOUT
IS THIS THE LAST LlATA WORD?
EXI T SU8ROUTltiE
NO. INCHt:MENT
AND 5TORE
NEXT
COMPARISON
"'ORO
NE.Xl OUTPUT
CALL TE5T2
LOOP ENTRY fJOINT
(;U~
CL(;
OTB
III
0
OT~
10
To CLEAR THE::
DATA 8UFFERS
NOP
1'40P
JMP PTi
100~*
lt001*
1002
10~j
10104
100~
1"''to 6
10(1)7
1'IJ1lI~
1~1O'1
163706 1t)000~i/)
't03767 072432
03770 1t16377':J
03771 ~3~1Otr?1.1
fJ3772 027711
1£'3773 06~432
'l)J77~ 127766
1lI3775 1777bI/J
Ut-LA'f NOP
STA A~J
LOA TIME.
03776
lSTc:
ISZ
llMI:.
"
JMp *-1
LOA AS3
JMI-' LIt-LAY. I
uCT -~1t1
t:::NTER SUtiROUTINE
STORE A
LOAU lIME DELAY
COUNT TO TIME
THEN CONTINUE
RE~TORE A
10110*
1011*
1012
1"lJ
040016
0041t1~i/)
UEF TE.5 T~
ORG 4itl1ll0~
TE5T2 LINKAGE
ORIGIN OF TI::ST2
A-21
12661A
Appendix A
PAGE 1122 .01
1114
1015
1016
1017
1018
1019
10201021
1022·
1023
1024
102~
1026
1027
102~
~4000
04001
04002
04003
04004
040165
000000
065743
00~727
A-22
~LF.aLF
ROUTINE TO SHIfT lOBO BITS
fAOM POSITIONS '-1 TO .
POSITIONS 8-15
STOHE 10~0 IN OuTPUT STORAGE
STB ouf
CLl;
JMP TEST2,1
EXIT
x
Ec.tU -
FWAM - 1ST .,0 AYAIL MEM.
INIll
INIT
OUT
COMPH
CPR
CONDI
t.NIH
t.N02
t.NDJ
HSK.4
OCT
OcT
OCT
OCT
OCT
STA
OCT
OCT
OCT
OCT
uCT
01<(;
16000"
1216000
0000011)
0000160
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ELECTRONIC
SALES & SERVICE OFFICES
UNITED STATES
ALABAMA
8290 Whitesburg Dr., S.E.
P.O. Box 4207
Hunslville 35802
Te .. (205) 881-4591
TWX, 810-726-2204
ARIZONA
2336 E. MagnoUa St.
......nlx 85034
Te" (602) 244-1361
TWX, 910·951·1330
5737 East Broadway
Tucson 85711
Tel, (602) 298-2313
TWX, 910-952-1162
(Effeell.e Dec. 15. 1973)
2424 East Aragon Rd.
Tucson 85706
Tel, (602) 889-4661
CALIFORNIA
1430 East Oranlethorpe Ave.
'unertln 92631
Tef, (714) 870-1000
TWX, 910-592-1288
3939 Lankersblm Boulevard
Nort1l Hollywood 91604
Tef, (213) 877-1282
TWX, 910-499-2170
COLORADO
7965 East Prentice
ERIII.ood 80110
To" (303) 771-3455
TWX, 910-935-0705
MARYLAND
6707 Whitestone Road
Baltlmlre 21207
Te" (301) 944-5400
TWX, 710-862-9157
CONNECTICUT
12 Lunar Drive
New HaveR 06525
Tel, (203) 389-6551
TWX, 710-465-2029
20010 Century Blvd.
Germantown 20767
Tel, (31) 428-0700
FLORIOA
P.O. Box 24210
2806 W. Oakland Park Blvd.
Fl. IlIDderdale 33307
Tef, (305) 731-2020
TWX, 510-955-4099
P.O. Box 13910
6177 Lake Ellenor Dr.
Orlaado, 32809
Tel: (305) 859·2900
TWX, 810-850-0113
GEORGIA
P_O. Box 28234
450 Interstate North
Atlanta 30328
Tef, (404) 436-6181
TWX, 810-766-4890
6305 Arizona Place
Lo. Anples 90045
Tel, (213) 649-2511
TWX, 910-328-6148
HAWAII
2875 So. King Street
Honolulu 96814
Tel, (808) 955-4455
1101 Embarcadero Road
Palo Alto 94303
Tel, (415) 327-6500
TWX, 910-373-1280
ILLINOIS
5500 Howard Street
Skokie 60076
Tef, (312) 677-0400
TWX, 910-223-3613
2220 Watt Ave.
Sacrlmento 95825
Tel, (916) 482-1463
TWX, 910-367-2092
9606 Aero Drive
P.O. Box 23333
San Dlelo 92123
Tel, (714) 279-3200
TWX, 910-335-2000
INDIANA
3839 Meadows Drive
Indianapolis 46205
Tel, (317) 546-4891
TWX, 810-341-3263
LOUISIANA
P. O. Box 840
3239 WIlliams Boulevard
Kiliner 70062
Tel, (504) 721-6201
TWX, 810-955-5524
P.O. Box 1648
2 Choke Cherry Road
lockvllle 20850
Tel, (301) 948-6370
TWX, 710-828-9684
MA!lSACHUSETTS
32 Hartwell Ave.
Loxlqlon 02173
Tef, (617) 861-8960
TWX, 710-326-6904
MICHIGAN
23855 R8SB~rch Drive
Farmlnlton 48024
Tef, (313) 476-6400
TWX, 810-242-2900
MINNESOTA
2459 UniversitY Avenue
st. Paul 55114
Tel, (612) 645-9461
TWX, 910-563-3734
MISSOURI
11131 Colorado Ave.
...... CIIy 64137
Tel, (816) 763-8000
TWX, 910-771-2087
148 Weldon parkway
Maryland Helpb 63043
Tel, (314) 567-1455
TWX, 910-764-0830
'NEVADA
LIs VeIlS
Tel, (702) 382·5777
NEW JERSEY
1060 N. Kings Highway
Cherry Hili 08034
Tel, (609) 667-4000
TWX, 710-892-4945
NEW MEXICO
P.O. Box 8366
Stallon C
6501 lomas Boulevard N.E.
Albuquerque 87108
Te" (505) 265-3713
TWX, 910·989-1665
NORTH CAROLINA
P.O. Box 5188
1923 North Main Street
Hllh Polnl 27262
Te" (919) 885-8101
TWX, 510-926-1516
156 Wyatt Drive
Lis Craces 88001
Tel, (505) 526-2485
TWX, 910-983-0550
OHIO
25575 Center Ridge ROld
Cleveland 44145
Te" (216) 835-0300
TWX, 810-427-9129
NEW YORK
e Automation Lane
Computer Park
Alban, 12205
Tef, (518) 458-1550
TWX, 710-441-8270
1219 Campvllle Road
Endicott 13760
Tel, (607) 754-0050
TWX: 510·252·0890
New York Cily
Manhattan, Bronx
Contact Paramus, NJ Office
Tel, (201) 265-5000
BrooklS'n, Queens, Richmond
Contact Woodbury, NY Office
Tel, (516) 921-0300
82 Washington Street
Po.puep.l. 12601
Tel, (914) 454-7330
TWX, 510-248-0012
39 Saginaw Drive
Rochester 14623
Tel, (716) 473-9500
TWX, 510-253-5981
5858 East Molloy Road
Syracuse 13211
Tel, (315) 454-2486
TWX, 710-541-0482
1 Crossways Park West
WooOury 11797
Tel, (516) 921-0300
TWX, 510-221-2168
330 Progress Rd.
Doylon 45449
Tef, (513) 859-8202
TWX, 810-459-1925
6665 Busch Blvd.
CoIumb •• 43229
Tel, (614) 846-1300
OKLAHOMA
P.O. Sox 32008
Oklafto ... CIIy 73132
Tel, (405) 721-0200
TWX, 910-830-6862
OREGON
17890 SW Boones Ferry Road
T.alalln 97062
Tef, (503) 620-3350
TWX, 910-467-8714
PENNSYLVANIA
2500 Moss Side Boulevard
Monroeville 15146
Tef, (412) 271-0724
TWX, 710-797-3650
1021 8th Avenue
Klnl of Prussia IndUstrial Park
King of Prussia 19406
Tel, (215) 265-7000
TWX, 510-660-2670
RHODE ISLAND
873 Waterman Ave.
Elst Providence 02914
Tel, (401) 434-5535
TWX, 710-381-7573
"TENNESSEE
Memphis
Tel, (901) 274-7472
W. 120 Century Rd.
Paramus 07652
Te., (201) 265-5000
TWX, 710-990-4951
TEXAS
P.O. Box 1270
201 E. Arapabo Rd.
Richardson 75080
Te" (214) 231-6101
TWX, 910-867-4723
P.O. Box 27409
6300 Westpark Drive
Suite 100
HIU~Dn 77027
Tel, (713) 781-6000
TWX, 910-881-2645
231 Billy Mitchell Road
San Antoni. 78226
Tef, (512) 434-4171
TWX, 910-871-1170
UTAH
2890 South Main Street
Salt Lake City 84115
Tef, (801) 487-0715
TWX, 910-925-5681
VIRGINIA
P.O. Box~6514
2111 Spencer Road
Rlcbmond 23230
Tef, (804) 285-3431
TWX, 710·956-0157
WASHINGTON
Bellefleld Office Pk.
1203 - 114th SE
Bellevue 98004
Tef, (206) 454-3971
TWX, 910-443-2303
'WEST VIRGINIA
Charleston
Tef, (304) 345-1640
WISCONSIN
9431 W. Beloit Road
Suite 117
Milwaukee 53227
Tel, (414) 541-0550
FOR U.S_ AREAS NOT
LISTED:
Contact the rellonal office near·
est YOu: Atlanta, Georgia •••
North Hollywood, California ••.
Paramus, New Jersey ••• Skokie,
IlIInols_ Their complete addresses are listed above.
*Servlce Only
CANADA
ALBERTA
Hewlett·Packard (Canada) Ltd.
11748 Klngsway Ave.
Edmonten TSS OX5
Te" (403) 452-3670
TWX, 610-831-2431
BRITISH COLUMBIA
Hewlett-Packard (Canada) ltd.
837 E. Cordova St.
Vancouver 6
Tel, (604) 254-0531
MANITOBA
Hewlett·Packard (Canada) Ltd.
513 Century St.
Winnipeg
Tel, (204) 786-7581
TWX, 610-671-3531
Hewlett·Packard (Canada) ltd.
825· 8th Ave., S.W.
Suite 804
Calpry
Tel, (403) 262-4279
NOVA SCOTIA
Hewlett-Packard (Canada) ltd.
2745 Dutch Village Rd.
Suite 210
Nalifax
Tef, (902) 455-0511
TWX, 610-271-4482
ONTARIO
Hewlett·Packard (Canada) ltd.
1785 Woodward Dr.
Ottawa K2C OP9
Tel: (613) 255·6180, 255·6530
TWX, 610-562-8968
Hewlett-Packard (Canada) ltd.
50 Galaxy Blvd.
Rexclal.
Tel, (416) 677-9611
TWX, 610-492-4246
QUEBEC
Hewlett·Packard (Canada) ltd.
275 Hymus Boulevard
Pointe Claire H9R IG7
Tel, (514) 697-4232
TWX, 610·422-3022
Telex: 01-20607
Hewlett·Packard (Canada) Ltd.
2376 Galvanl Street
Sielay GIN 4G4
Tel, (418) 688-8710
FOR CANADIAN AREAS NOT
LISTED:
Contact Hewlett-Packard (Can·
ada) Ltd. in Pointe Claire.
CENTRAL AND SOUTH AMERICA
ARGENTINA
Hewlett·Packard Argentina
S.A.C.e.1
Lavalle 1171. 3 D
Buenos Aires
Te" 35-0436, 35-0627, 35-0341
Telex, 012-1009
Cable, HEWPACK ARG
BOLIVIA
Stambuk & Mark (Bolivia) LTDA.
Av. Mariscal, Santa Cruz 1342
La 'az
Tel, 40626. 53163. 52421
Telex: 3560014
Cable, BUKMAR
BRAZIL
Hewlett·Packard Do Brasil
I.E.C. Ltda.
Rua Frei Caneca 1119
01307·5ao 'aul..SP
Te" 288-7111, 287-5858
Telex, 309151/2/3
Cable: HEWPACK Sao Paulo
Hewlett·Packard Do Brasil
I.E.C. Ltda.
Praca Dom Feliciano, 78
90000-Porta Alegro-RS
Rio Grande do SuI (RS) Brasil
Tel, 25-8470
Cable, HEWPACK Porto Alegre
Hewlett-Packard Do Brasil
I.E.C. ltoa.
Rua da Matrlz, 29
20000-Rlo de Janelro·GB
Tel, 266-2643
Telex, 210079 HEWPACK
Cable: HEWPACK Rio de~Janelro
ECUADOR
Laboratorlos de Radio-Ingenlerla
Calle Guayaquil 1246
Post Office Box 3199
Quito
Te" 212-496; 219-185
Cable, HORVATH Quito
NICARAGUA
Roberto Terjn G.
Apartado Postal 689
Edificio Terin
Manllua
Tef, 3451, 3452
Cable: ROTERAN Managua
CHILE
H&ctor Calcagni y Cia, ltda.
Casilla 16.475
santiago
Tel, 423 96
Cable: CALCAGNI Santiago
EL SALVADOR
Electronic Associates
Apartado Postal 1682
Centro Comerclal Gigante
San salvador, EI Salvador C.A.
Paseo Escalon 4649-4° Piso
Tel: 23-44-60, 23·32·37
Cable, ElECAS
PANAMA
Electr6nico Balboa, S.A.
P.O. Box 4929
Ave. Manuel Espinosa No. 13-50
Bldg. Alina
Panama City
Tel: 230833
Telex: 3481103, Curunda,
Canal Zone
Cable: ELECTRON Panama City
COLOMBIA
Instrumentac;6n
Henrik A. Langebaek & Kier S.A.
Carrera 7 No. 48-59
Apartado Mreo 6287
lopta, 1 D.E.
Tel, 45-78-06, 45-55-46
Cable, AARIS Bogota
Telex, 44400INSTCO
COSTA RICA
lie. Alfredo Gallegos Gurdlfn
Apartado 10159
SIn JOte
Te" 21-86-13
Cable, GALGUR San Josi
GUATEMALA
IPESA
Avenida La Reforma 3·48,
Zona 9
liuatemala
Tel, 63627, 64736
Telex: 4192 TELTRO GU
MEXICO
Hewlett·Packard Mexicana,
SA de C.V.
Torres AdaJld No. 21, 11 0 Piso
Col. del Valle
Mexico 12, D.F.
Tef, 543-42-32
Telex, 017-74-507
PARAGUAY
Z. J. Melamed S.R.L.
Division: Aparatos y Equlpos
Medicos
Division: Aparatos y Equlpos
SCientiflcos y de
P.J~~~tlIJglon
Chile, 482, Edlficio Victoria
Asuncion
Tel, 4-5069, 4-6272
Cable, RAMEL
PERU
Compailia Electro M6dica S.A.
Ave. Enrique Canaual 312
San Isidro
Casilla 1030
lima
Tel, 22-3900
Cable: ELMED Lima
URUGUAY
Pablo Ferrando S.A.
Comercial e Industrial
Avenlda )talia 2877
Casilla de torreo 370
Montevld••
Te" 40-3102
Cable: RADIUM Montevideo
PUERTO RICO
San Juan Electronics, Inc.
P.O. Box 5167
Ponce de Leon 154
Pda. 3-PTA de Tierra
San Juan 00906
Tel, (809) 725-3342, 722-3342
Cable: SATRONICS San Juan'
Telex: SATRON 3450 332
VENEZUELA
Hewlett-Packard de Venezuela
C.A.
Apartado 50933
Edificio Serre
Tercera Transversal
Los Rulces Norte
Caracas 107
Tel, 35-00-11
Telex, 21146 HEWPACK
Cable: HEWPACK Caracas
FOR AREAS NOT LISTED,
CONTACT:
Hewlett·Packard
Inter·Americas
3200 Hillview Ave.
r::~ (~~~! ~3~!f~\a 94304
TWX, 910-373-1267
Cable, HEWPACK Palo Alto
Telex, 034-8300, 034-8493
E 11/73
EUROPE
AUSTRIA
Hewlett-Packard Ges.m.b.H
Handelska 52/3
P.O. Box 7
A-1205 Vienna
Tel, (0222) 33 66 06 to 09
Cable: HEWPAK Vienna
Telex: 75923 hewpak a
BELGIUM
Hewlett-Packard Benelux
S.A./N.V.
Avenue de Col-Vert,!.
(Groenkraaglaan)
B-1170 Brussels
Tel, (02) 72 22 40
Cable: PAlOBEN Brussels
Telex: 23 494 paloben bru
OENMARK
Hewlett·Packard A/S
Datavej 38
DK-3460 Blrkerod
Tel: (01) 81 66 40
Cable: HEWPACK AS
Telex: 166 40 hp as
Hewlett·Packard A/S
Torvet 9
OK·8600 Silkeborg
Tel, {O6) 82-71·66
Telex: 166 40 hp as
Cable: HEWPACK AS
FINLANO
Hewlett·Packard Oy
Bulevardi 26
P.O. Box 12185
SF-00I20 Helsinki 12
Tel, (90) 13730
Cable: HEWPACKOY Helsinki
Telex: 12-15363 hel
FRANCE
Hewlett-Packard France
Quartier de Courtaboeuf
Boue Postale No.6
F·91401 Drsay
Tel: (1) 907 78 25
Cable: HEWPACK Orsay
Telex: 60048
Hewlett·Packard France
Agenee Regional
4 Quai des Etroits
F-69321 Lyon Cedex 1
Tel, (78) 42 63 45
Cable: HEWPACK lyon
Telex: 31617
Hewlett-Packard France
Zone Aeronautique
Avenue Clement Ader
F-31770 Colomiers
Tel: (61) 86 81 55
Telex: 51957
Hewlett·Packard France
Agence Regionale
Boulevard Ferato-Gamarra
Boite Postale No. 11
F-13100 Luynes
Tel, (47) 24 0066
Telex: 41770
Hewlett-Packard France
Agency Regionale
63, Avenue de Rochester
F-35000 Rennes
Tel: (99) 36 33 21
Telex: 74912 F
Hewlett-Packard France
Agence Regionale
74, Allee de la Robertsau
F-67000 Strasbourg
Tel: (88) 35 23 20/21
Telex: 89141
Cable: HEWPACK STRBG
GERMAN FEDERAL
REPUBLIC
Hewlett-Packard GmbH
Vertriebszentrale Frankfurt
Bernerstrasse 117
Postfach 560 140
0·6000 Frankfurt 56
Tel: (0611) 50 04-1
Cable: HEWPACKSA Frankfurt
Telex: 413249 fra
Hewlett-Packard GmbH
Vertriebsburo Boblingen
Herrenbergerstrasse 110
D-7030 Biiblingen, Wurttemberg
Tel, (07031) 66 72 87
Cable: HEPAK BobJingen
Telex: 72 65 739 bbn
Hewlett-Packard GmbH
Vertriebsbiiro Dusseldorf
Vogelsanger Weg 38
0-4000 Dusseldorf
Tel, (0211) 63 80 31/38
Telex: 85/86533 hpdd d
Hewlett-Packard GmbH
Vertriebsburo Hamburg
Wendenstr. 23
0-2000 Hamburg 1
Tel, (040) 24 13 93
Cable: HEWPACKSA Hamburg
Telex: 21 63 032 hphh d
Hewlett-Packard GmbH
Vertriebsburo Hannover
MeJlendorfer Strasse 3
0-3000 Hannover·Kleefeld
Ter, (0511) 55 06 26
Hewlett-Packard GmbH
Vertriebsburo Nuremberg
Hersbruckerstrasse 42
0-8500 Nuremberg
Tel, (0911) 57 10 66
Telex: 623 860
Hewlett·Packard GmbH
Vertriebsbiiro Munchen
Unterhachinger Strasse 28
ISAR Center
0-8012 Ottobrunn
Tel: (089) 601 30 61/7
Telex: 52 49 85
Cable: HEWPACKSA Muchen
(West Berlin)
Hewlett-Packard GmbH
Vertriebsburo Berlin
Wilmersdorfer Strasse 113/114
0-1000 Berlin W. 12
Tel, (030) 3137046
Telex: 18 34 05 hpbln d
ITALY
Hewlett·Packard Italiana S.p.A.
Via Amerigo Vespucci 2
1-20124 Milan
TeJ: (2) 6251 (to lines)
Cable: HEWPACKIT Milan
Telex: 32046
Hewlett-Packard Italiana S.p.A.
Piazza Marconi, 25
'-00144 Rome - Eur
Ter, (6) 5912544/5, 5915947
Cable: HEWPACKIT Rome
Telex: 61514
Hewlett-Packard Italjana S.p.A.
Vicolo Pastori, 3
1-35100 Padova
Tel, (49) 66 40 62
Telex: 32046 via Milan
HewleU-Packard !taJiana S.p_A.
Via Colli, 24
1-10129 Turin
Tel: (11) 53 82 64
Telex: 32046 via Milan
LUXEMBURG
Hewlett-Packard Benelux
S.A./N.V.
Avenue de Col-Vert, 1,
(Groenkraaglaan)
B·1170 Brussels
Tel, (03/02) 72 22 40
Cable: PAlOBEN Brussels
Telex:, 23 494
GREECE
Kostas Karayannis
18, Ermou Street
GR-Atbens 126
Tel: 3230·303, 3230·305
Cable: RAKAR Athens
Telex: 21 59 62 rkar gr
NETHERLANDS
Hewlett-Packard Benelux/N. V.
Weerdestein 117
P.O. Box 7825
Nl-Amsterdam, 1011
Tel: 020-42 77 77, 442966
Cable: PAlOBEN Amsterdam
Telex: 13216 hepa nl
IRELAND
Hewlett-Packard ltd.
224 Bath Road
GB-Slough, Sll 4 OS, Bucks
Tel: Slough (0753) 33341
Cable: HEWPIE Slough
Telex: 848413
NORWAY
Hewlett-Packard Norge A/$
Nesveien 13
Box 149
N-1344 Haslum
Tel. (02) 53 83 60
Telex: 16621 hpnas n
Hewlett-Packard Ltd.
The Graftons
Stamford New Road
Altrincham, Cheshire
Tel, (061) 928·9021
Telex: 668068
PORTUGAL
Telectra-Empresa Tecnica de
Equipamentos Eh'ictricos S.a.r.l.
Rua Rodrigo da Fonseca 103
P,O. Box 2531
P-Lisbon 1
Tel, (19) 68 60 72
Cable: TElECTRA lisbon
Telex: 1598
SPAIN
Hewlett-Packard Espanola, S.A.
Jerez No 8
E-Madrid 16
Tel: 458 26 00
Telex: 23515 hpe
Hewlett-Packard Espanoia, S.A.
Milanesado 21·23
E·Barcelona 17
Tel, (3) 203 62 00
Telex: 52603 hpbe e
SWEOEN
Hewlett-Packard Sverige AB
Enighetsvagen 1-3
Fack
S-161 20 Bromma 20
Tel: (08) 98 12 50
Cable: MEASUREMENTS
Stockholm
Telex: 10721
Hewlett-Packard Sverige A8
Hagakersgatan 9C
5-431 41 Molndal
Tel: (031) 27 68 00/01
Telex: Via Bromma
SWITZERLANO
Hewlett Packard (Schweiz) AG
Zurcherstrasse 20
P.O. Box 64
CH-8952 Schlieren Zurich
Tel: (01) 98 18 21/24
Cable: HPAG CH
Telex: 53933 hpag ch
Hewlett-Packard (Schweiz) AG
9, Chemin louis-Pictet
CH-1214 Vernier-Geneva
Tel: (022) 41 4950
Cable: HEWPACKSA Geneva
Telex: 27 333 hpsa ch
TURKEY
Telekom Engineering Bureau
Saglik Sok No. 15/1
Ayaspasa·Beyoglu
P.O; Box 437 Beyoglu
TR-istanbul
Tel: 49 40 40
Cable: TElEMATION Istanbul
UNITEO KINGDOM
Hewlett-Packard ltd_
224 Bath Road
GB-Slough, Sll 4 OS, Bucks
Tel: Slough (0753) 33341
Cable: HEWPIE Slough
Telex: 848413
Hewlett·Packard ltd.
"The Graftons"
Stamford New Road
GB·Altrincham, Cheshire
Ter, (061) 928-9021
Telex: 668068
Hewlett·Packard ltd's registered
address for V.A.T. purposes
only:
70, Finsbury Pavement
London, EC2AISX
Registered No: 690597
SOCIALIST COUNTRIES
PLEASE CONTACT:
Hewlett-Packard Ges.m.b.H.
Handelskai 52/3
P.O. Box 7
A-1205 Vienna
Ph: (0222) 33 66 06 to 09
Cable: HEWPACK Vienna
Telex: 75923 hewpak a
ALL OTHER EUROPEAN
COUNTRIES CONTACT:
Hewlett·packard S.A.
Rue du Bois-du-lan 7
P.O. Box 85
CH-1217 Meyrin 2 Geneva
Switzerland
Tel: (022) 41 54 00
Cable: HEWPACKSA Geneva
Telex: 2 24 86
AFRICA, ASIA, AUSTRALIA
ANGOLA
Telectra·Empresa Tecnica
de Equipamentos Electricos
SARl
Rua de Barbosa, Rodrigues,
42_1°, DP
P.O. Box 6487
luanda
Cable: TElECTRA luanda
AUSTRALIA
Hewlett-Packard Australia
Pty. ltd.
22·26 Weir Street
Glen Iris, 3146
Victoria
Tel: 20-1371 (6 lines)
Cable: HEWPARD Melbourne
Telex: 31 024
Hewlett-Packard Australia
Pty. Ltd.
31 Bridge Street
Pymble,
New South Wales, 2073
Tel: 449 6566
Telex: 21561
Cable: HEWPARD Sydney
Hewlett-Packard Australia
Pty. ltd.
97 Churchill Road
Prospect 5082
South Australia
Tel: 44 8151
Cable: HEWPARD Adelaide
ETHIOPIA
African Salespower & Agency
Private ltd., Co.
P. O. Box 718
58/59 Cunningham St.
Addis Ababa
Tel: 12285
Cable: ASACO Addisababa
HONG KONG
Schmidt & Co. (Hong Kong) ltd.
P.O. Box 297
Connalight Centre
39th Floor
Connaught Road, Central
Hong Kong
Tel: 240168, 232735
Telex: HX4766
Cable: SCHMIDTCO Hong Kong
INDIA
Blue Star ltd.
Kasturi Buildings
Jamshedji Tata Rd.
Bombay 400 020
Tel: 29 50 21
Telex: 3751
Cable: BLUEFROST
Blue Star ltd.
Sahas
414/2 Vir Savarkar Marg
Prabhadevi
Bombay 400 025
Tel: 45 78 87
Telex: 4093
Cable: FROSTBLUE
Hewlett-Packard Australia
Pty. Ltd.
Casablanca Buildings
196 Adelaide Terrace
Perth, W.A. 6000
Tel: 25-6800
Cable: HEWPARD Perth
Blue Star ltd.
Band Box House
Prabhadevi
Bombay 400 025
Tel: 45 73 01
Telex: 3751
Cable: BlUESTAR
Hewlett-Packard Australia
Pty. ltd.
10 Woolley Street
P.O. Box 191
Dickson A.C.T. 2602
Tel, 49·8194
Cable: HEWPARD Canberra ACT
Blue Star ltd.
14/40 Civil lines
Kampur 208 001
Tel: 6 88 82
Cable: BLUESTAR
Hewlett-Packard Australia
Pty. ltd.
2nd Floor, 49 Gregory Terrace
Brisbane, Queensland, 4000
Tel: 29 1544
Blue Star, ltd.
7 Hare Street
P.O. Box 506
Calcutta 700 001
Tel: 23·0131
Telex: 655
Cable: BlUESTAR
CEYLON
United Electricals ltd.
P.O. Box 681
60, Park St.
Colombo 2
Tel: 26696
Cable: HOTP01NT Colombo
Blue Star ltd.
Blue Star House,
34 Ring Road
lajpat Nagar
New Delhi 110 024
Tel: 62 32 76
Telex: 2463
Cable: BLUESTAR
CYPRUS
Kypronics
19 Gregorios & Xenopoulos Road
P.O. Box 1152
CY-Nicosia
Tel, 45628/29
Cable, KYPRONICS PANOEHIS
Blue Star, ltd.
Blue Star House
U/11A Magarath Road
Bangalore 560 025
Tel: 55668
Telex: 430
Cable: BlUESTAR
Blue Star, Ltd.
1-1-117/1
Sarojini Devi Road
Secunderabad 500 003
Tel: 763 91, 7 73 93
Cable: BLUEFROST
Telex: 459
Yokogawa-Hewlett-Packard ltd.
Chuo Bldg.
Rm. 603 3,
2-Chome
IZUMI·CHO,
Mito, 310
Tel: 0292·25-7470
The Electronics Instrumentations Ltd. (TEll)
16th Floor Cocoa House
P.M.B. 5402
Ibadan
Tel: 22325
Cable: THETEll Ibadan
Blue Star, ltd.
23/24 Second line Beach
Madras 600 001
Tel: 23954
Telex: 379
Cable: BlUESTAR
KENYA
Kenya Kinetics
P.O. Box 18311
Nairobi, Kenya
Tel: 57726
Cable: PROTON
PAKISTAN
Mushko & Company, ltd.
Oosman Chambers
Abdullah Haroon Road
Karachi 3
Tel, 511027, 512927
Cable: COOPERATOR Karachi
Blue Star, ltd.
Nathraj Mansions
2nd Floor Bistupur
Jamshedpur 831 001
Tel: 38 04
Cable: BlUESTAR
Telex: 240
INDONESIA
Bah Bolon Trading Coy. N.V.
DlaJah Merdeka 29
Banduog
Tel: 4915, 51560
Cable: IlMU
Telex: 08-80:9
IRAN
Multi Corp International ltd.
Avenue Soraya 130
P.O. Box 1212
IR·Teberafi
Tel: 83 10 35-39
Cable: MUlTICORP Tehran
Telex: 2893 MCI TN
KOREA
American Trading Company
Korea,
I.P.O. Box 1103
Dae Kyung Bldg.. , 8th Floor
107 Sejong·Ro,
Chongro-Ku, Seoul
Tel: (4 lines) 73-8924-7
Cable: AMTRACO Seoul
LEBANON
Constantin E. Macridis
P.O. Box 7213
Rl·Beirut
Tel: 220846
Cable: ELECTRONUClEAR Beirut
MALAYSIA
MECOMB Malaysia ltd.
2 lorong 13/6A
Section 13
Petaling Jaya, selangor
Cable: MECOMB Kuala lumpur
ISRAEL
Electronics & Engineering
Div. of Motorola Israel ltd.
17 Amlnadav Street
Te'·Avlv
Tel, 36941 (3 lines)
Cable: BASTEt Tel-Aviv
Telex: 33569
MOZAMBIQUE
A.N. Goncalves, lta.
162, Av. D. Luis
P.O. Box 107
Lourenco Mar,ques
Tel: 27091, 27114
TeleK: 6-203 Negon Mo
Cable: NEGON
JAPAN
Yokogawa-Hewlett·Packard Ltd.
Obashl Building
1-59-1 Yoyogi
Shibuya-ku, Tokyo
Tel. 03-370-2281/92
Telex: 232-2024YHP
Cable: YHPMARKET TOK 23-724
NEW ZEALAND
Hewlett-Packard (N.Z.) ltd.
94-96 Dixon Street
P.O. Box 9443
Courtenay Place,
Wellington
Tel: 59-559
Telex: 3898
Cable: HEWPACK WeJ!ington
Yokogawa-Hewlett·Packard ltd.
Nisei Ibaragi Bldg.
2-2-8 Kasuga
Ibaragi·Shi
Osaka
Tel, (0726) 23-1641
Telex: 5332·385 YHP OSAKA
Yokogawa·Hewlett-Packard ltd.
Nakamo Building
No. 24 Kamlsasazima-cho
Nakamura·ku, Nagoya City
Tel. (052) 571-5171
Yokogawa·Hewlett-Packard ltd.
Nitto Bldg.
2-4-2 Shinohara-Kita
Kohoku-ku
Yokohama 222
Tel, 045-432-1504
Telex: 382-3204 YHP YOK
Hewlett-Packard (N.Z.) ltd.
Pakuranga Professional Centre
267 Pakuranga Highway
Box 51092
Pakuranga
Tel: 569-651
Cable: HEWPACK, Auckland
NIGERIA
The Electronics Instrumentations ltd. (TEll)
144 Agege Motor Rd., Mushln
P.O. Box 6645
lagos
Cable: THETEll lagos
Mushko & Company, Ltd.
38B, Satellite Town
Rawalpindi
Tel: 41924
Cable: FEMUS Rawalpindi
PHILIPPINES
Electromex, Inc.
6th Floor, Amalgamated
Development Corp. Bldg.
Ayala Avenue, Makati, Rizal
C.C.P.O. Box 1028
Makati, Rizal
Tel: 86-18·87, 87-76-77,
87-86-88, 87-18·45, 88-91-71,
83-81-12, 83-82·12
Cable: ELEMEX Manila
SINGAPORE
Mechanical & Combustion
Engineering Company Pte.,
ltd.
10/12, Jalan Kilang
Red Hill Industrial Estate
Singapore, 3
Tel: 647151 (7 fines)
Cable: MECOMB Singapore
Hewlett-Packard Far East
Area Office
P.O. Box 87
Alexandra Post Office
Singapore 3
TeJ: 633022
Cable: HEWPACK SINGAPORE
SOUTH AFRICA
Hewlett Packard South Africa
(PtY.),ltd.
Hewlett-Packard House
Daphne Street, Wendywood,
Sandton, Transvaal 2001
Tel: 407641 (five lines)
Hewlett Packard South Africa
(Pty.), ltd.
Breecastle House
Bree Street
cape Town
Tel, 2-6941/2/3
Cable: HEWPACK Cape Town
Telex: 0006 CT
Hewlett Packard South Africa
(Pty.), ltd.
641 Ridge Road, Durban
P.O. Box 99
Overport, Natal
Tel: 88-6102
Telex: 567954
Cable: HEWPACK
TAIWAN
Hewlett Packard Taiwan
39 Chung Shlao West Road
Sec. 1
Overseas Insurance
Corp. Bldg. 7th Floor
Taipei
Tel: 389160,1,2,375121,
Ext. 240-249
Telex: TP824 HEWPACK
Cable: HEWPACK Taipei
THAILANO
UNIMESA Co., ltd.
Chongkoinee Building
56 Suriwongse Road
Bangkok
Tel: 37956, 31300, 31307,
37540
Cable: UNIMESA Bangkok
UGANDA
Uganda Tele-Electric Co., ltd.
P.O. Box 4449
Kampala
Tel: 57279
Cable: COMCO Kampala
VIETNAM
Peninsular Trading Inc.
P.O. Box H-3
216 Hien-Vuong
Saigon
Tel: 20-805, 93398
Cable: PENTRA, SAIGON 242
ZAMBIA
R. J. Tilbury (Zambia) ltd.
P.O. Box 2792
Lusaka
Zambia, Central Africa
Tel: 73793
Cable: ARJAYTEE, lusaka
MEDITERRANEAN ANO
MIDDLE EAST COUNTRIES
NOT SHOWN PLEASE
CONTACT:
Hewlett-Packard
Co-ordination Office for
Mediterranean and Middle
East operations
Piazza Marconi 25
1-00144 Rome-Eur, Italy
Tel. (6) 59 40 29
Cable: HEWPACKIT Rome
Telex: 61514
DTHER AREAS NOT
LISTEO, CONTACT:
Hewlett-Packard
Export Trade Company
3200 Hillview Ave.
Palo Alto, California 94304
Tel. (415) 326-7000
(Feb. 71 493-1501)
TWX: 910·373·1267
Cable: HEWPACK Palo Alto
Telex: 034-8300, 034-8493
E 11173
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