245a_CDC_1604A_Reference_Manual_May1963 245a CDC 1604A Reference Manual May1963
245a_CDC_1604A_Reference_Manual_May1963 245a_CDC_1604A_Reference_Manual_May1963
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ReferenceManual
CONTROL DATA
1604-A COMPUTER
1 (iO4 -A I1 RI CTIONS
Page
Page
00
ZRO
(not used)
01
ARS
A Right Shift
02
QRS
Q Right Shift
40
SST
Seleetive Sut
2-33
2-13
41
SCL
Selective Clcar
2-34
2-13
42
8CM
Selective Complement
2-33
SSU
Selective Substitute
2-35
03
LRS
AQ Right Shift
2-13
43
04
ENQ
Enter Q
2-25
44
LDL
Load Logical
2-35
45
ADL
Add Logical
2-35
05
ALS
A Left Shift
2-13
06
QLS
Q Left Shift
2-14
46
SBL
Subtract Logical
2-35
07
LLS
AQ Left Shift
2-14
47
STL
Store Logical
2-35
10
ENA
Enter A
2-25
50
ENI
Enter Index
2-26
11
INA
Increase A
2-25
51
INI
Increase Index
2-26
Load A
2-10
52
LIU
Load Index, U
2-12
12
LDA
13
LAC
Load A, Complement
2-10
53
LIL
Load Index, L
2-12
14
ADD
Add
2-17
54
ISK
Index Skip
2-16
15
SUB
Subtract
2-17
55
IJP
Index Jump
2-16
16
LDQ
LoadQ
2-10
56
SIU
Store Index, U
2-12
SIL
Store Index, L
2-12
17
LQC
Load Q, Complement
2-10
57
20
STA
Store A
2-11
60
SAU
Substitute Address, U
2-15
21
STQ
Store Q
2-11
61
SAL
Substitute Address, L
2-15
22
AJP
A Jump
2-27,36
62
INT
Input Transfer
2-40
23
QJP
Q Jump
2-28,31
63
OUT
Output Transfer
2-40
24
MUI
Multiply Integer
2-18
64
EQS
Equality Search
2-36
25
DVI
Divide Integer
2-19
65
THS
Threshold Search
2-36
26
MUF
Multiply Fractional
2-20
66
MEQ
Masked Equality
2-37
27
DVF
Divide Fractional
2-20
67
MTH
Masked Threshold
2-37
30
FAD
Floating Add
2-20
70
RAD
Replace Add
2-38
31
FSB
Floating Subtract
2-21
71
RSB
Replace Subtract
238
32
FMU
Floating Multiply
2-22
72
RAO
Replace Add One
238
33
FDV
Floating Divide
2-23
73
RS()
Leplace Subtract One
2-39
34
SCA
Scale A
2-24
74
EXF
External Function
3-3
35
SCQ
Scale AQ
2-24
75
SLJ
Selective Jump
2-29,31
36
SSK
Storage Skip
2-32
76
SLS
Selective Stop
229,31
37
SSH
Storage Shift
2-32
77
SEV
(not used)
Reference Manual
CONTROL DATA
1604-A COMPUTER
245a
REV 5/63
lt
RECORD OF CHANCE NOTICES
C.
1
DAE
T
ORIGINATED
1
DATE
ENTERED
INITIALS
J
REMARXS
1
J 1 :3
11 1
•
Major Revision (May, 1963)
Address comrrwnts onerning ihis
This edition, publication 245a,
manual to
is a major revision and obsoletes
Control l)ata Corporation
publication 245.
Technical Publical jons Depa rtmenl
01963, Control Data Corporation
501 Park Avenue
Printed in the United States of Arnerjca
MinneapoHs 15, 1v1Iflfl(SOt1
ii
1
II
1
IH
PREFACE
This manual describes the characteristics,
instructions, and manual controls of the
CONTROL DATA* 1604-A Computer.
* Registered trademark of Control Data Corporation.
‚ii
1
CONTENTS
Chapter 1.
Chapter 3.
Description
Input/Output
3-- 1
1604-A Characteristics
1-1
Logical Description
1-2
High Speed Transfer Channel
3- 1
Storage Section
1-3
Buffer Channels
3-1
Control Section
1-3
Arithmetic Section
1-5
Input/Output
1-6
Program Compatibility
Chapter 2.
Methods of Data Exchange
Initiation and Control of Data
Exchange
1-6
Description of Instructions
Word Format
2-1
3-2
Transfer
3- 2
Buffer
3-2
Interrupt
3-7
Interrupt Subroutine
3-3
Real Time Ciock
3- iO
Operation Code
2-1
Index Designator
2-1
Typewriter
3-12
Execution Addresses
2-2
Paper Tape Reader
3-14
Address Modification
2-2
F ap er T ap e P u ne
3- 17
Console Input/Output Equipment
Execution of a Fair of Instructions 2-4
Instructions
Instruction Execution Time
1
3-12
Chapter 4. Operation
2-5
Description of Indicators and
Control Switches
2-6
Order of Instructions
2-7
Data Transmission
2-10
Shifting
2-13
Address Modification
2- 15
Arithmetic
2-17
No Address
2-25
Jumps and Stops
4- 1
Main Computer Controls
4-4
Reader and Punch Controls
4-6
Auto Load Control
4-7
Operation
4-0
Load Program Entering
40
2-27
Starting Operation With ProStored Load Program
4-0
Storage Test
2-32
Reader
4-0
Logical
2-33
Punch
4-10
Storage Search
2-36
Typewriter
4-11
Replace
2-38
Magnetic Tape Units
4-11
Transfer
2-39
606 Tape Unit
4-12
1607 Tape Unit
4-16
File Protection Ring
4-10
Emergency Pro cedures
4- 20
1
III
iv
1
ii.
-------------
4
1
GLOSSARY
APPENDIX SECTION
1
Number Systems
1
VI
EXF and Character Codes
29
II
Faults
19
VII
Magnetic Tape BCD Codes
39
III
Table of Powers of 2
21
VIII
Flexowriter Codes
40
fV
Octal-Decimal Integer Conversion Table
IX
Punched Card Codes
41
22
Octal-Decimal Fraction Conver26
sion Table
X
Input/Output Typewriter Codes 42
V
XI
1612 Printer Codes
43
4-3
Manual Controls
4-5
4-4
Reader, Punch, and Auto
Load Controls
4-6
4-5
Paper Tape Reader
4-9
4-6
Paper Tape Punch
4-10
47
Operator Control Panel
4-12
4-8
606 Tape Load and tJnload
Mechanics
4-14
FIGT RES
(:
•
klapter 1.
/nial 1604-A System
(hapter3.
3--12
Description
Input/Output
104-AFlowChart
3-6
Seven-Level Punched Paper
Tpe (Assembly Modes)
3-15
(hapter 4.
4-1
1-7
Operation
Center Panel ofConsole
4-1
4-9
1607 Tape Unit
4-18
Console Display
4-2
4-10 File Protection Ring
4-20
4-2
TABLES
(
1-1
-2
fiapl
1.
1-2
4-1
Arithmetic Properties of
Rvgi sters
Conditions Indicated by Console
Background Lights
4-3
1-5
4-2
Main Computer Controls
4-4
4-3
Reader and Punch Controls
4-6
4-4
606 Controls and Indicators
4-12
4-5
1607 Controls and Indicators
4-17
4-6
Emergency Procedure
4-20
)ical Interrupt Subroutine
ii
1
--
Input/Output
Iexupt Addresses
Ii
Abl
Operation
Registers of the Computer
(hapter 3.
I
Chapter 4.
Des eliption
3-8
3-9
LCOTROL
_1
CHAPTER 1
DESCRIPTION
The CONTROL DATA 1604-A is a stored-program, general-purpose digital computer
with a large storage capacity, fast computation and transfer speeds, and special provisions for input/output communication. The 1604-A is designed to handle large-volume
data processing and to solve large-scale scientific problems. The compact equipment,
eonstructed from solid-state components throughout, is suitable for use in a semipermanent office environnient.
0
1604-A CHARACTERISTICS
Stored-program general-purpose
digital computer
Parallel mode of operation
48-bit word, 2 instructions per word
Single address logic
Operation code
6 bits
Designator
3 bits
Base Execution Address 15 bits
Six 15-bit index registers
Indirect addressing
Magnetic core storage
3248-bit words
"
Two independent 16, 384 word banks
alternately phased
4 8 lasec effective cycle time
(representative program)
6. 4 iasec total cycle time
Program interrupt
Console, includes:
Photo-electric paper tape reader
Paper tape punch
Electric typewriter
Register contents displayed in octal
Flexible instructions
Fixed-point arithmetic
(integer and fractional)
Floating-point arithmetic
Logical and masking operations
Indexing
Storage seahng
Binary arithmetic
Parallel addition in 1.2 psec without
access 48
Modulus 2
- 1 (one's complement)
Real-time ciock
Completely solid-state
Diode logic
Transistor amplifiers
Input/output
Parallel transmission of 48-bit words
Three separate buffer input channels
Three separate buffer output channels
High-speed transfer channel (4. 8 psec per word)
*Registered trademark of Control Data Corporation
'1
LOGICAL DESCRIPTION
The 1604-A performs calculations and processes data in a parallel binary mode through
lt H
t.i
the step-by-step execution of individual instructions which are stored internally along
with the data.
Functionally, the computer may be divided into four major sections. Storage provides
internal storage for data and instructions; Control coordinates and sequences all Operations for executing an instruction by obtaining the instruction from storage and translating it into commands for the other sections; Arithmetic performs the arithmetic and
logical operations required for executing instructions; and Input/Output provides
communication btween the computer and the external equipment.
1
1
j
The registers in the computer are identified by letters (table 11). The arithmetjc
properties of the registers are detailed in table 1-2. The operational registers usually
hold the end result of an operation; their contents are displayed on the console and may
be changed manually.
TABLE 1-1. REGISTERS OF THE COMPUTER
R egister
A*
B1
through
B6*
P*
Function
Register
Function
Accumulator
U2
Auxiliary Program
Control
Auxiliary
A nt hmeti c
R
Address Buffer
Index registers
(six)
Program Address
CCR
CR 1
through
CR6
X
Program Control
Jj
\
1
?
J
Buffer Control
Exchange
•1
Il
ii
1
1
* Operational Registers
1
1-2
1
1
7 ,
_4
L1
STORAGE SECTION
The magnetic core storage section of the 1604-A computer provides high-speed,
-
random access storage for 32,768 words. lt consists of two independent storage units
each with a capacity of 16, 384 words. These units operate together during the
execution of a stored program and thus are considered as one 32, 768 word storage
system.
1
A word is 48 bits in length and is used in two ways: as two 24-bit instructions or as a
48-bit operand (data word). The location of each word in storage is identified by an
aignec number or address. When a word is taken (read) from or entered (written)
into storage, a reference is made to the storage address which holds the word. All
odd storage addresses are located in one storage unit, all even addresses in the other.
The cycle time, or time for a complete storage reference, is 6. 4 Psee. Since the
storage cycies of the two sections overlap one another in the execution of a program,
the average effective cycle time for random addresses is about 4. 8 Msec.
CONTROL SECTION
The control section directs the operations required to execute instructions and to
initiate the exchange of data with external equipment. lt also establishes the timing
relationships needed to perform the Operations Ifl the proper sequence.
The control section acquires a program word from storage, interprets it and sends the
necessary commands to other sections. A program word is a pair of 24-bit instruetions
which together occupy one storage location as a 48-bit word. The higher-order 24 bits
are the upper instruction; the remaining 24 bits, the lower instruction.
Instruction Format
f
(6 bits)
Operation
Code
m,y,ork
b
(3 bits)
(15 bits)
--
Base Execution
Address
Index
Designator
Each of the 62 instructions has a unique 6-bit operation code which specifies the
operation to be performed.
1-3
The index designator generaily specifies one of the six index registers whose content
is to be added to the execution address. This process is called address modification.
However, the index designator may also specify indirect addressing or a condition for
jump and stop instructions.
The execution address may be used in one of three ways: as an address, m, of an
operand; as an operand, y; or as a shift count, k.
The eight operational registers in the control section are P, U 1 and B through B 6 .
The program address register (P) is a two's complement additive counter. lt provides
program continuity by generating in sequence the storage addresses whjch contain the
individual program steps. Usually at the completion of each two instructions the count
in P is advanced by one to specify the address of the next program word.
The program control register (U 1 ) holds a program word while the two Instructions
contained in it are executed. The upper instruction is executed first followed by the
lower instruction.
After executing an instruction, a half exit, full exit, or jump exit is performed. A
half exit aliows the lower instruction of a program word to be executed. A full exit
advances the count in P by one and executes the upper instruction of the new program
word specified by the contents of P. A jump exit aliows a new sequence of instructions
to be executed; the storage location of the new instruction is specified by the execution
address of the jump instruction. The execution address, in this case, is entered into
P and specifies the starting location of a new sequence of program words.
The auxiliary pgram control register (U 2 ) is a 15-bit subtractjve accumulator used
primarily in the modification of the base execution address. The contents of the
specified index register are transmitted to the Address Buffer register (R), which has
provisions for counting, complementing and storing. The contents of R are then added
to the contents of U which holds the execution address.
Index registers B 1 through B 6 are 15-bit registers used to modify the base execution
address when relative addressing is used. The index registers are also used to designate the number of words in search and transfer iflstructions and for other indexing
operations.
1-4
1-
ARITHMETIC SECTION
The arithmetic section of the 1604-A Computer consists of two operational registers.
A and Q, and one secondary register, X.
TABLE 1-2. ARITHMETIC PROPERTIES OF REGISTERS
Register
No.
of Stages
A
48
2
Q
U
2
Complement
Notation*
Arithmetic
Result
-1
one's
subtractive
signed
48
2 48 -1
ones
15
2
p
15
R
15
Modulus
48
15
-1
2 15
215
signed
one's
subtractive
signed
two s
additive
unsigned
two's
subtractive
unsigned
The A register (Accumulator) is the principal arithmetic register. Some of the more
important functions of A are:
Arithmetic operation - A initially holds one of the operands in addition,
subtraction, multiplication and division. The result is usually held in A.
Shifting - A may be shifted to the right or left separately or in conjunction with
Q. Right shifting is open-ended; the lowest bits are discarded and sign
extended. Left shifting is circular; the highest order bit appears in the lowest
order stage after each shift; all other bits move one place to the left.
Control for conditional instructions - A holds the word which conditions jump
and search instructions.
The Q register is an Auxiliary Arithmetic register and is generaily used in conjunction
with the A register. The principal functions of Q are:
Providing temporary storage of contents of A while A is used for another
arithmetic Operation.
-
Forming a double-length register, AQ or QA.
Shifting to the right or left, separately or in conjunction with A.
Participating with the A register in multiplication, division and logical
product operations (masking).
Refer to Appendix
** The result of an arithmetic Operation in A satisfies A -1 47
since A always is
treated as a signed quantity. When the result in A is zero, it is always represented
by 000. . .00 except when 111. . . 11 is added to 111. . . 11 or 000.. .00 is subtracted
frorn lii... 11. In these cases the result is 111... 11 (negative zero).
1-5
-
The X (Exchange) register is used in the exchange of data between storage and the
arithmetic section. X provides one of the inputs to the accumulator borrow pyramid.
INPUT/OUTPTJT
The input/output section controls the flow of data to and from the computer. Data is
transmitted in one of twoways: High Speed Transfer or Buffering.
1
J
1
High speed transfer operations are controlled directly by the program (Search and
Transfer Sequence) and are used to transfer data between computers or between a
1604-A and high speed external equipment (e.g., a line printer). I/O channel number 7
is used for high spee transfer.
Buffering is an asynchronous transmission of data on I/O channels 1 through 6. Once a
buffer operation has been initiated by the program, buffering and program operations proceed concurrently. Computation continues while buffering takes place at rate dependent
on the external equipment. Buffering and program operations share access to computer
storage; bufei, High speed transfer is a program operation.
The buffer channels are paired with input on odd channels and output on even channels•
Output
Channel 2
Channel 4
Channel 6
Input
Channel 1
Channel 3
Channel 5
All six channels may be used concurrently. Each channel may be connected to several
external equipments (figure 1-1) but only one equipment may use a channel at any
instant. All I/O operations are parallel transmission of 48-bit words.
PROGRAM COMPATJBILITY
The 1604/1604-A switch enables the 1604-A to run programs written for the 1604. A
red background light in the leftmost digit of the P register indicates that the switch is
1
ii
itt
Ii
11
i
v
11
II
in the 1604 position.
Experience to date has shown only two areas of program incompatibiiity between the
1604 and the 1604-A:
In the 1604, the EXF code 74. 004001 locks out all interrupts; in the 1604-A
this code locks out only external interrupts. (See Appendix, page 29 for
1
internal interrupt codes).
In the 1604-A, when reading input words into buffer control word addresses
(e. g., Auto Load operation), the fast 1604-A control word registers require
that the upper address of the mnput word be the control word address plus one
1-6
1
1
1
1
1
riL
1
Fiuie 1-1. Typical 1604-A System
1-7
1
1
1
J
CHAPTER 2
V
DESCRIPTTON OF INSTRTJCTIONS
WORD FORMAT
A computer word consists of 48 bits and may be interpreted as one 48-bit data word or
two 24-bit instructions. Each instruction is composed of three parts or codes: Oper-
I :L
‚1
.1
Ii
II
II
ation code, index designator, and execution address. The higher-order 24 bits of the
word are called the upper instruction and the lower-order 24-bits are called the lower
instruction.
bit
47
bit
24
Operation
(Function)
Code
f
fl
1
Index
Designator
b,j
6
bits
3
bits
Code
Range
Operation
01 -
f
Index
Designator
0-7
b, j
1
I
I
Execution
Address
m, y, k
00000
through
77777
Execution
Address
1
m,y,k
T
15
bits
Specifiesthe operation to be performed.
A 00 VOM code is interpreted as a fault,
which stops computer operation.
Specifies the addressing mode, jump or
stop condition, index register or external
function depending on the operation code.
Used in one of three ways:
as a shift count, k
as an operand address, m
as an operand, y
OPERATION CODE
1
I I
The f portion of an instruction is the operation code which specifies which instruction is
to be done. The interpretation of the rest of the instruction is conditioned by f.
INDEX DESIGNATOR
The b or j portion of an instruction designates:
1) The addressing mode
b=0
direct addressing
b = 1-6 relative addressing
indirect addressing
b= 7
2-1
JL1
The condition for jump or stop instructions (see Jumps and Stops, page 2-27).
The type of EXF instruction
j=0
select
j = 1-6 activate
j7
sense
1
1
1
1
The index register in index instructions
EXECUTION ADDRESS
The base execution address may be used as: (1) a shift count, k; (2) an operand, y;
(3) an address of an operand, m, in storage; (4) an external function code (chapter 3).
The execution address may also be modified or unmodified depending on the instruction
and index designator. If unmodified, the address is represented by the lower-case
symbol k, y, or m; if the address is modified the symbols are capitalized. The following
examples point out the relationship between the unmodified and modifjed executjon
address.
The modified shift count K is represented by:
K = k + (Bb) where:
= modified shift count
K
k b = unmodified shift count (execution address)
(B ) = contents of index register b.
If the index designator = 0, then K = k.
The modified operand Y is represented by:
Y = y + (B b) where:
= modified operand
Y
y b = unmodified operand (execution address)
(B ) = contents of index register b.
If the index designator = 0, then Y = y.
The modified operand address M is represented by:
= modified address of operand
M
M = m + (Bb) where:
m
= unmodified address of operand (executjon address)
(Eb) = contents of index register b.
If the index designator = 0, then M = m. Note that (3) is the only case in which the
execution address is interpreted as an address of an operand.
ADDRESS MODIFICATION
The three possible modes of address modification are identjfjed by the In(Iex designa-
i -1
1I
II
I]
Ii
i
i
ii
i
ii
i
II
1
tors as follows:
1) b = 0 No Address Modification. In this mode the executjon addrcss is intnrpreted without modification; nothing is added to or subtractecl frorn lt.
(Direct addressing.)
IM
•
ii
1
(3 Relative Address Modification. In this mode the execution address is
2)
iyiodified and is equal to the initial execution address plus the contents
ot' the designated index register. One's complement arithmetic is used
in determining the modified execution address.
)b=7
Indirect Addressing. In this mode the base execution address specifies
the address of the operand address rather than the operand. The 48-bit
word is read from storage and the lower-order 18 bits of the word are
interpreted as the b designator (3 bits) and execution address (15 bits)
of the present instruction. The new Index designator may refer to any
one of the three modes.
amples:
) No Address Modification
m
f b
LDA 0 address
This instruction is interpreted as bad accumulator from the storage bocation designatecl by the sum of the execution address and the contents of the specified index
register, Bb. Since b = 0, no index register is designated and m specifies the
torage location whose contents are boaded into A.
f b
m
2) Relative Address Modification
LDA 6 address
(B ) = 000018
In this example, the accumulator is boaded from the storage location designated by
Ihe execution address plus the contents of index register 6. Therefore, the contents
ol the storage location named by the execution address plus 000018 is loaded into
the accumulator. M = m + (Bb).
Indirect Addressing
Current
Irs rution
f b
m
= [DA 7 00100
(00100) = FAD 0 00300 FMU200
(B6) = 00001 8
i 1e h 1 Iilo of the rurrerit instruction is 7, the mode is indirect -ddressing.
The lower 18 bits of the contents of the storage bocation designated by the execution
address, 00100, are read from storage into the U register where they are interpreted
as the index designator and execution address of the current instruetion.
2-3
The index designator is inspected again and because lt is not 0 or 7 the relative address
mode exists. (Note that the new index designator could reference any one of the three
modes of address modification.) The execution address, 00200, plus the contents of
B 6 , 000018 specify the storage location whose contents will be loaded into the
accumulator. M = 00200 8 + (00001 8 ) = 00201 8
EXECUTION OF A PAUl OF INSTRUCTIONS
Example:
m
f b m
(00300) = LDA 0 00310
ADD 1 00210
(00301) = STA 0 00400
SLS 0 00301
f b
(B 1 ) = 001018
The P register holds address 00300 (an even lowest bit indicates the address of the
program step is in the even storage unit). The storage reference
j5
initiated; the 48-
bit word is read from address 00300 and entered into U 1 . Computer Operation is now
dependent upon the interpretation of the 24-bit instruction in the upper half of U 1 .
The operation code, LIlA, and the index designator, 0, are translated. The function of
the upper instruction, LDA, is to bad the A register with the contents of the designated
storage location. Because the index designator is 0, the executjon address is not
modified. The translation of the operation code initiates the sequence of the commands
which execute the instruction and the operand in address 00310 is loaded into A.
The lower instruction in U 1 is transferred to U
1
upper and translated. The ADD
instruction causes the quantity in storage location M to be added to the contents of the
A register. Since the index designator is not 0 or 7, the contents of the index register
are added to the execution address to form M. M = m + (Bb)
00210 8 + 001018 =
003118. The contents of storage address 00311 are added to the contents of the A
register completing the instruction. The contents of the p register are increased hy
one and the pair of instructions at address 00301 is read from storage and cxecutEd
2-4
INSTRUCTTONS
The 62 computer instructions are described on the following pages (EXF instructions
are discussed in detail in chapter three). The title line contains the numeric code, the
mnemonic code and format, name, and average execution time of the instruction.
Abbreviations and symbols are defined as foliows:
Accumulator
A
The binary digit in position n of the A register
Transmit to
-
Index designator
Designated index register
Ixit (Full)
Proceed to upper instruction of next program step
Half exit
Proceed to lower instruction of same program step
j
The condition designator for jump and stop instructions
k
Unmodified shift count
K
Modified shift count.
LA
Lower address - execution address portion of lower instruction
of a program step
m
Unmodified operand address
M
Modified operand address.
(]3b)
K = k +
M = m + (Bb)
Contents of a register or storage location
)'
On&s complement of contents of a register or storage location
)f
Final contents of a register or storage location
)i
Initial contents of a register or storage location
Q
Auxiliary arithmetic register
UA
Upper address
X
Exchange register
y
Unmodified operand
Y
Modified operand.
Y = y + (Bb)
2-5
1! j
INSTRTJCTION EXECUTION TI1\iIE
The time needed to execute an instruction varies frorn application to apptication
because of the following factors.
1
j
If the instruction occupies the upper position in an instruction word, the time
needed to read the word from storage must be considered.
/
If consecutive storage references are made to the same storage unit (even-even
or odd-odd) the read access time from storage will be maximized.
If indirect addressing is specified, at least one additjonal reference will be
needed to complete the instruction.
(The new index designator rnay itself specify
1
indirect addressing.
If buffer operations are using storage, an instruction must wait until storage is
released.
If a storage reference is made at the end of the preceding instruction, executjon
of the next instructlon may ne aeiayeci.
The instruction execution times listed on the following pages were compiled by
averaging the times for a long list of the same instructions. The list was arrange(1
for typical values of the factors.
2-6
1
1
ORDER OF INSTRUCTIONS
Numeric
Code
Mnemonic
Code
Name
T iming*
DATA TRANSMISSION
12
LDA
LOAD A
13
LAC
LOAD A COMPLEMENT
16
LDQ
LOAD Q
17
LQC
LOAD Q COMPLEMENT
20
STA
STORE A
21
STQ
STORE Q
52
LIU
LOAD INDEX (UPPER)
53
LIL
LOAD INDEX (LOWER)
56
SIU
STORE INDEX (UPPER)
57
SIL
STORE INDEX (LOWER)
01
ARS
A RIGHT SHIFT
02
QRS
Q RIGHT SHIFT
03
LRS
AQ RIGHT SH[FT
05
ALS
A LEFT SHIFT
06
QLS
Q LEFT SH[FT
07
LLS
AQ LEFT SHIFT
7.2
SHIFTING
2.8 + 4s
ADDRESS MODIFICATION
60
SAU
SUBSTITUTE ADDRESS (UPPER)
7.2
61
SAL
SUBSTITUTE ADDRESS (LOWER)
7.2
54
ISK
INDEX SK[P
56
55
IJP
INDEX JUMP
4.4
Tirning is average execution time in isec
- N(i flhl)(IT of I)iacc- shiftvd
ARITHMETIC (Fixed)
ADD
14
ADD
7.2
SUB
SUBTRACT
7.2
24
MUI
MTJLTIPLY INTEGER
25.2 + .8n
25
DVI
DIVIDE INTEGER
65.2
26
MUF
MULTIPLY FRACTIONAL
25.2 + 8n
27
DVF
DIVIDE FRACTIONAL
65.2
15
ARITHMETIC (Floating)
30
FAD
FLOATING ADD
18.8
31
FSB
FLOATING SUBTRACT
18.8
32
FMU
FLOATING MULTIPLY
36. 0
33
FDV
FLOATING DIVIDE
56.0
34
SCA
SCALE A
2.8 + .4s
35
SCQ
SCALE AQ
2.8 ± 4*
04
ENQ
ENTER. Q
10
ENA
ENTER A
11
INA
INCREASE A
50
ENI
ENTER INDEX
51
INI
INCREASE INDEX
NO ADDRESS
3.0
JUMPS AND STOPS (Normal)
22
AJP
A JUMP
23
QJP
Q JUMP
75
SLJ
SELECTIVE JUMP
76
SLS
SELECTIVE STOP
7.2
JUMPS AND STOPS (Return)
22
AJP
A JUMP
23
QJP
Q JUMP
75
SLJ
SELECTIVE JUMP
76
SLS
SELECTIVE STOP
Number of ones in multiplier
= Number of positions shifted
2 -8
7.2
STORAGE TEST
3(3
SSK
STORAGE SKIP
8.8
37
SSH
STORAGE SHIFT
12.8
40
SST
SELECTIVE SET
42
SCM
SELECTIVE COMPLEMENT
41
SCL
SELECTIVE CLEAR
43
SSu
SELECTIVE SUBSTITUTE
44
LDL
LOAD LOGICAL
45
ADL
ADD LOGICAL
46
SBL
SUBTRACT LOGICAL
47
STL
STORE LOGICAL
64
EQS
EQUALITY SEARCH
65
THS
THRESHOLD SEARCI-1
66
MEQ
MASKED EQUALITY
67
MTH
MASKED THRESHOLD
70
RAD
REPLACEADD
71
RSB
REPLACE SUBTRACT
72
RAO
REPLACE ADD ONE
73
RSO
REPLACE SUBTRACT ONE
62
INT
INPUT TRANSFER
63
OUT
OUTPUT TRANSFER
LOGICAL
1
J
7. 2
7.4
7.2
STORAGE SEARCH
1LP LACE
4.0 + 3. 6r-
1
L
13.2
TRANSFER
- r - Number of repeaied executions
2-9
>
J
4.O4.8r
DATA TRANSMISSION
ulative addrussing does not take place during LIU, LIL, SJU or SIL instru(tionn.
Only direct and indirect addressing are recognized.
All modes of address modificafidn apply to the remaining data transmission
instructions.
During the execution of data transmission instructions, one storage referenc( i
made. If indirect addressing is designated, at least two storage references arc
enade.
LDAbm
12
LoadA
7.2sec
Replaces the contents of A with a 48-bit operand contained in storage locatiori M
The initial contents of A are changed during execution; the conteots of M remain
unchanged.
LAC bm
13
Load A Complement
7 2 Msec
Replaces the contents of A with the complement of a 48-bit operand contained in
storage location M. The initial contents of A are changed during execution; the
contents of M remain unchanged.
LDQbm
16
LoadQ
7.2Msec
Replaces the contents of Q with a 48-bit operand contained in storage location M.
The initial contents of Q are changed cluring execution: the contents of ad(lresn M
remain unchangcd.
LQC bm
17
Load Q Complernent
7.2 p sec
Replaces the contents of Q with the complement of a 48-bit operand contajned in
storage location M. The initial conteots of Q are changed during execution; tin
contents of address M remain unchanged.
2- 10
STAbm 2o
StoreA
7.2sec
Replaces the contents of the designated storage location, M, with the contents of
A. The initial contents of A remain unchanged.
STQbm
21
StoreQ
7.2Msec
Replaces the contents of the designated storage location, M, with the contents of
Q. The initial contents of Q remain unchanged.
LDA, LAC, LDQ, LQC, STA, and STQ
2- 11
L
~
S IFTING
,
All modes of address modification apply to these instructions.
If the modified shift count, K, is greater than 127, a fault indicator is set.
Regardiess of the magnitude of count, however, ih6 reqde1 number of shifts is
cxecuted. (K is reduced by one count for each shift executed and when K
=
0,
shifting stops.
Shifting must be completed before an input/output or interrupt request can be
processed. (See chapter three.
A RS bkoi
2.8 +
A Right Shift
.
4s* isec
Shifts contents of A to the right K places. The sign is ex±ended and the lower bits
are discarded. The largest practical shift count is 47 since the register is now
in extension of the sign bit.
l
t
QRSbk02
2.8 +
Q Right Shift
.
4s jsec
Khifts contents of Q to the right K places. The sign is extended and the lower bits
:Ire discarded. The largest prac-tical shift count is 47 since the register is now
10
an extension of the sign bit.
-
L RSbko3
Long Right Shift
2.8 + .4s psec
Shifts contents of AQ to the right K places as one 96-bit register. The A register
is considered as the leftmost 48 bits and the Q register as the rightmost 48 bits.
The sign of A is extended. The lower order bits of A replace the higher order
1
..
bits of Q and the lower order bits of Q are discarded. The largest practical shift
count is 95 since AQ is now an extension of the sign of A.
10
ALSbkO5
2.8 + .4s jisec
A Left Shift
AWW
Shifts contents of A to the left K places, left circular. The higher order bits of
A replace the lower order bits. The largest practical shift count 48 returns
10
the register to its original state.
Number of positions shifted
2-13
QLSbk
ob
Q LO± Sliift
Shifts contents of Q to the left K places, left circular. The higher order bus of
Q replace the lower order bits. The largest practical shift count 48 10 returns
the register to its original state.
LLSbk
07
Long Left Shift
Shifts contents of AQ to the left K places, left circular, as one 96-bit registt.
The higher order bits of A replace the lower order bits of Q and the higher
bits of Q replace the lower order bits of A. TOn
9610 ieturns AQ 10 its original state.
1IrOrl.
)t
OL
H
Ins t r u c t ion
1 in
L
pp er
Modify k to K
KrShift C'ount
t SIij fn
FauLt md.
fR >127io
AHS
________
QRS
LS
Shift A RT [ Shift Q RT Shift A Lft ift €Q
ft 1
1 Position
1 Position 1 Positi 1 Ptn
[
Count 0 6eduet Count = 0
Countbyl
Exit tu Nnst
Instru(tion
Shift Instructions
2-14
1 - ,1
ADDRESS MODIFICATION
IL
modes of address modification apply to SAU and SAL instructions.
L
1ative addressing cannot be used for ISK or IJP instructions. Only direct or
riHirect addressing are used.
4)uring execution of ISK and IJP instructions, no storage reference is made unless
1
•
•
ndirect addressing is specified which requires at least one reference. For SAU
and SAL instructions, one reference is always made. If indirect addressing is
(Iesignated, at least one additional reference will be needed to complete the
truction.
(;o 8 Z Z,'i4
t3
SAU b m
60
Substitute Address Upper
Yx
9Z4
‚t4'
X14'4
7. 2 psec
1eplaces the upper address portion of M with the lower-order 15 bits of A.
liemaining bits of M are not modified and the initial contents of A are unchanged.
SAL bm
61
Substitute Address Lower
7.2 jusec
Replaces the lower address portion of M with the lower-order 15 bits of A.
ilemaining bits of M are not rnodified and the initial contents of A are unchanged.
:
SAU and SAL
2-15
k
1 5K by
Index Skip
7.2 /LS(
Compares (Eb) with y. If the two quantities are equal, Bb iS cleared and a fu1I
b
exit is perforrned. If the quantities are unequal, B ) is increased one couni. in
the R register and a half exit is perforrned. Because the R register isatwos
complement subtractive counter, it is possible to count through negative zero and
positive zero. (See appendix.) If b = 0 and y 0, a half exit is taken. If b = 0
and y = 0, afull exit is taken. ISK is usually restricted to the upper instructjon.
If used as a lower instruction it will half exit upon itseif until the full cxli condilion
is satisfied; if b = 0 and
1 J P bm
y 1 0, the condition will never be satisfied.
7 2 psc
Index Jump
55
Examines (Bb) . If this quantity is not zero, the quantity is reduced one count and
a jump is executed to address m. The counting operation is perormd in the R
register but negative zero is not generated because i[JP terminates at positivo
zero. (See appendix.) The index jump can be used in the upper or lower
-
instruction without reservation; it executes a normal jump upon satisfactjon of
the jump condition.
Iristruction
in
Half
Exit
No
=O9
Yes
Fult
Exit
1S
e5
DoesbO?
Na
(Bb)
o
‚ ISK
IJP
Execute
Next
Instruction
Clear B b
Full
Exit
Subtract
(B b) frorn y
Irierease
(Bb) by 1
Half
Exit
ISK and IJP
2-16
\ Yes
UP
Reduce
(B ) by 1 ljp
Jump to
Address m
1
1
xecute
Next
Instruction
ARI THME TIC
1) All modes of address modification apply to these instructions.
) ()ne storage reference is made for each instruction unless indirect
[ddressing is designated. In this oase, at least two references
re made.
HXED
47
:) If the capacity of the A register ± (2 -1) is exceeded during the
('xecution of the instructions an arithmetic overflow fault is
)roduced. When executing the DVI or DVF instructions, if the
csult exceeds the capacity of the Q register ± (2-1) a divide
fault is produced. (Refer to appendix.)
ADDbm
14
7. 2 usec
Add
Adds a 48-bit operand obtained from storage location M to contents of A. A
negative zero may be produced by this instruction if (A) and (M) are initially
negative zero. The contents of storage address M remain unchanged.
SUBbm
15
7,2 psec
Suhtract
Obtains a 48-hit operand from storage location M and subtracts it from the initial
contents of A. A negative zero will be produced if the initial contents of A are
negative Zero and that of storage location M are positive zero. The contents of
address M remain unchanged.
ADD and SUB
2-17
I I
1•
AlUIbm
24 ,
Multiplylnteger
Forms a 96-bit produc± from two 48-bit operands. The multiplier must be
loaded into A prior to execution of the jflstructjon. The execution address
specifies the storage location of the multiplicand. The product is contained in
QA as a 96-bit quantity. The operands are considered as integers and therefore
the binary point is assumed to be at the lower order (right hand) end of the A
register.
T
1nstrctor
,in
U Upper
7
1
Reduce count
by 1
1
No
N„.
C
Add mull
loacd
T0 partal
produrt rt A
N.
Pos
L
Multipler to Q
Multiplica rid 10
X. Ctear
A
— — —
— —
-50
Yes
Multiplicand and
multrpiter San-re
slgn?
No
]
Complernent
Product
Set multlply
count: 48 (MUI)
47 (MUF')
Couct
Yes
MUI
MW
1
Exchange
and Q
PA
l:xecute
ccxl
‚St rurt Irr
MUI and MUF
* n = Numher of ones in m'iltiplier
2-18
0
----•
-
DVIbm
25
Dividelnteger
65.2sec
1)ivides a 96-bit integer dividend by a 48-bit integer divisor. The 96-bit
LLvidend must be formed in the QA register prior to executing the instruction.
IJ a 48-bit dividend is loaded into A, the sign of Q must be set.
That is, the sign
of the dividend in A must be extended throughout Q. The 48-bit divisor is read
Horn the storage location specified by the execution address. The quotient is
[orrned in A and the remainder is left in Q at the end of the operation. Dividend
etid rernainder have the same sign.
r -----------1
Ins truction
in
i
Upper
Mod fy
m to M
DIVIDE
Reduce divide
Countbyl
Read
(M) —X
Dividend and
divisor signs
the same
Shift AQ
Ieftl
Yes
-.
Neg.
Record sign
of divisor
A X
9
Com plement
Quotient
No
Yes
(();iipent
divisorNeg.
Subtract
(X) from (A)
Record sign
of dividend
Set
Q 00 to 1
Complemnent
Dividend
et divide
ount to 48
DVI
DVF
rXchae
Div ide nd
Negative?
Pos.
e
Q
o
Set divide
fault
indicator
2
L------------1
DVI and DVF
2-19
Corn plemerit
Remainder
I
No
Remainder
toQ
ecut e
next
instruction
/vIUF bm
26
Multiply Fractional
0 fl'
p( , (
Forms a 96-bit product from two 48-bit operands. The operands are treated as
fractions with the binary point immediately to the right of the sign bit. The
rnultiplier must be loaded into A prior to executing the instruction. The multiplicand is read into X from the storage location specified by M. The 96-bit product
is contained in AQ.
DVFbm
27
Divide Fractional
65.2 psec.
Divides
a 96-bit quantity by a 48-bit divisor. All operands are treated as
77
fractions with the binary point immediately to the right of the sign bit. The 96-bit
dividend must be loaded into AQ prior to executing this instruction. If a 48-bit
dividend is loaded into Q, the sign of Q most be extended throughout A. At the
end of this operation the quotient is left in A and the remainder in Q.
Remaincier
and dividend have the same sign.
Refer to appendix for a discussion of floating point format.
All modes of address modification apply.
3) One storage reference is made unless indireet addressing is
FLOAT ING
designated. In this case, at least two references are macle.
4) Floating point range faults (overflow-underflow) occur if the
exponent exceeds 210_ 1 in absolute value. Refer to appendix.
FAD bm
30
Floating Add
13. 8
Forms the sum of two operands packed in floating point format. A floating point
operand is read from storage location M and added to the floating point word in A
The result is normalized, rounded, and retained in A at the end of the Operation.
Q contains only the residue of the rounding operation at the end of the
= Number of ones in multiplier
2-20
se(jU('flC(
F S B bm3l
18. 8 isec
Floating Subtract
i'orms the clifference of two 48-bit operands in floating point format. The subtrahend is acquired from storage address M and is subtracted from the minuend in
A. The result is rounded and normalized if necessary and retained in A. The
rcsiducf rom the rounding operation is left in Q at the end of the sequence.
Thu basic steps cxecutcd in a FSB are the same as those for FAD except the
coefficientS are subtracted rather than added.
r-
Instruction
in
U 1 Upper
Complement
Addend
Ne
Complement
Augend
Equalize exp.
by shifting AQ
right (R)
Read Addend
X
(M)
Pos
Shift most significant bit to A35. Fa
left shifts reduce
U 2 . For riht shift
increase U-.
1
Put coefficients
m non-comp.
form and ADD
1
Augend in A
by previous inst.
1
Pos.
Yes
ROUND
I
Compare
1xponents
>
2 10 1?
No
i
Set exponent
fault indicalor
1
___ ______
Assemble exp
eN
i'lace larger
exponentinU2
ficient of
ller exp
r
Io' ; other to X
cxpl
Yes
1
YeSuhl
1'Iace differc-nce
in exp. in lt
T
- - - - - - - - - - - - l
NORMALIZE
1
Modify
mtoM
Ne .
1
1
L
1
L ----------FSB the coefficients
are subtracted
FAD and FSB
2-21
and
A coefficientl
-----
Execute
next
instructio1
______
FMU bm
36. 0 psec
Floating Multiply
32
Forme product of an operand in floating point format with the previous
contents of A also in floating point format. The operand is read from storage
location M. The product is rounded and normalized ii' necessary and retained
in A. The residue from the rounding Operation is left in Q at the end of the
s equ en c e.
Instruction
U Upper
Modify
m to M
Multiply
(See 2-18)
Multiplicand
Record
omuttiplicand
next
instruction
N
Round
(See 2-21)
Ii
Complement
Multipticand
Normalize
(See 2-21)
Read
X
(M)
Record sign
of multiplier
No
Ne
Multiplier and
multiplicand
Same sign?
Pos.
Complement
Product
Complement
Multiplier
Execute
next
inStruction
Add exponepts
sum to U
CoefficientS of
multiplier to Q
Multiplicand to X
Clear A
Irr
Set multiply
count to 36
FMU
2-22
FDVbm
33
Floating Divide
56.0 /isec
Forms the quotient of two 48-bit operands in floating point format. The dividend
must be loaded into A prior to executing this instruc±ion. The divisor is read
from the storage location specified by M. The quotient is rounded and normalized
if necessary and retained in A at the end of the operation. The residuc from the
rounding operation is left in Q at the end of the operation.
Instruction
U Upper
Div ide
(See 2-19)
Modify
m to M
Round
(See 2-21)
Div idenJy5
09
Execute
Next
Instruction
No
Normalize
(See 2-21)
Record signj N
of divdend
No
C orn plem e nt
Dividend
4yes
7(M)
Read
-X
Com plem ent
quotient and
remainder
Pos.
Ex ecu te
rJext
Instruction
Neg.
Record sign
of divisor
ment
!2Dvisor
Subtract exponents
Difference to U2
-.- '5
Set divide
coutit to 3t
I'DV
2-23
m.Addrcss mo(lification does not apply. lfathcr, the ndcx registu
S
used to preserve the scale factor.
If b = 0, scaling is executed but the scale factor is lost.
If b = 7, indirect addressing is used and at least one storag(
reference is made.
SCALE
If (A) i is already scaled or equal to positive or negative zero,
k Bb and scaling is not executed.
If the execution address is initially equal to 0, Bh is cleared and
no scaling takes place.
The shift fault indicator is not affected by this instruction.
SCAbk
34
ScaleA
.‚
', 2.8+.4s*sec
Shifts A left circularly urtfl the most signifcant digit** is to the right of the sign
bit or until k = 0. Shift count k is reduced by one for each shift and terminates
when k = 0 or the most significant digit is to the right of the sign bit. Upon
termination the count (scale factor) is entered in the designated Index register.
Scale AQ
5
2.8 + . 4s psec
Shifts AQ left circularly until the most significant digit is to the right of the sign
SCQ bk
bit. Shift count k is reduced by one for each shift. Operation termjnates when
k = 0 or the most significant digit is to the right of the sign bit. Upon terminatjon
the count (scale factor) is entered in the designated index register.
Ins tr uni ion
U lippen
No
Redu
sh
Shift (A)
Lft 1
position
Execute
Nest
Iristruntion
SCA
SCA and SCQ
= Numher of positions shifted
ii*When a negative number is being scaled,
hOrsu are significant digits
2-24
NO A.DDRESS
All mdes of adclress modification apply to ENQ, ENA, and INA instructjons.
Relative addressing cannot be used for ENI and INI instructions. Only direet and
indireet addressing are used.
-
No storage reference is made during these instructions unless indireot addressing
is designated. In this case, at least one storage reference is made.
ENQ by
Enter Q
04
3. 0 [tsec
The 15-bit operand, Y, is entered into Q and its highest order bit is extended in .
the remaining 33 bits. The largest positive 15-bit operand that can be entered
HQIT
bit will be duplicated in each of the remaining
into Q is 37777 (214_1) and its
8
: bits of Q. Negative zero will be formed in Q if:
b
1) (B ) = 77777 and y = 77777 or
:‚-
•
2)b0andy77777 8 .
ENAby
10
EnterA
3.0sec
The 15-bit operand, Y is entered into the A register and its highest order bit is
extended in the remaining 33 bits. The largest positive 15-bit operand that can
Q!
be entered into A is 37777 (2141) and the
bit will be duplicated in each of the
remaining 33 bits. Negative zero will be formed in A if:
(Bb) =
8
and y = 77777 or
b = 0 and y =
INAby
ii
3.0psec
IncreaseA
Adds Y to A. The 15-bit operand Y is placecl in X and its highest order bit is
extended in the remaining 33 bits. The operand in X is added to (A).
44
2j
e(t.-._
1
4.
4
2-25
64
Lyf?
-
E N 1 by
51
Enter Index
3. 0 psec
b ) with the operand y. If b = 0, this instruction becomes a pass (do
Replaces (B
50
nothing) instruction.
1 N 1 by
-
51
Increase Index
-„.
3.0 bisec
Increases (Bb) by the operand y. If the b designator is zero, this instructjon
becomes a pass (do nothing) instruction.
Instruetion
1 in
U Upper
ENI
INI
Modify
in to M
Add y to
(Bb)
INA
Extend Bit 15
in M. Add to
(A)
Transfer
mtoBb
ENQ1
ENA1
Extend Bit 15
in M. Place
M in Q.
Extend Bit 15
in M. Place
M in A.
Execute
Next
Instruction
No Address
2-26
JUMPS AND STOPS
Address modification does not apply to these instructions.
NORMAL
One storage reference is made.
A jump instruction causesa current program sequence to terminate and initiates a new
sequence at a different location in storage. The Program Address register, P, provides the continuity between program steps and always contains the storage location of
the current program step.
When a jump instruction occurs, P is cleared and a new address is entered. In all
jump instructions, the execution address, m, specifies the beginning address of the new
program sequence. The word at address m is read from storage, placed in U and the
1
upper instruction (first instruction of the new sequence) is executed.
Some of the jump instructions are conditional upon a register containing a specific
value or upon the position of an operators jump or stop key on the console. If the
criterion is satisfied, the jump is made to location m. If lt is not satisfied, the
program proceeds in its regular sequence to the next instruction.
A jump instruction may appear in either position in a program step. If the jump
instruction appears in the first (upper) part .of the program step and the jump is taken,
the second (lower) part of the program step is not executed. If the instruction appears
in the lower part, the upper part is executed in the normal manner.
AJPjm
22
AJump
7.2Msec
Jumps to m if the conditions of the A register speci.fied by the jump des ignator, j,
El
exist. If not, the nex± instruction is executed.
j = 0 Jump if (A) = 0
j = 1 Jump if (A) 0
j = 2 Jump if (A) = +
j = 3 Jump if (A) = -
2-27
t
When (A) is negative zero the interpretation is:
0 The jump is executed becausc, in this case, negative Zein
as positive Zero.
j
L5 F(
gi1
j = 1 The jump is not executecl.
j = 2 The jump is not executed because the sign bit is a '1'.
j = 3 The jump is executed because the sign bit is a
Instruction
1 in
U Upper
AJP
QJ P
S LJ
ecutentN O
nstruction
in current
routine
SLS
Is Stop
conditjon
satisfied?
1 sJump
co rid ition
satsfied 7
Yes
Yes /
M Stop
Continue
when Run/Step
key is moved up
or down
j=O-3
xecute upper
nstruction of 1 Normal
rOgram step Jump
m.
Store next address of current routine in
upper address
of program
step m.
Return
Ju mp
Execute lower
instruction of
program step
m.
AJP, QJP, SLJ, and SLS
QJPjm
23
QJump
7.2sec
Jumps to m if the condition of the Q register specified hy the rnp (InSignator,
exists. If not, the next instruction is executed.
j = 0 Jump if (Q) = 0
j = 1 Jump if (Q) 0
j 2 Jump jf (Q) = +
j = 3 Jump if (Q) = When (Q) is negative zero the AJP Interpretation applies.
2-28
S L J jm
75
Selective Jump
7. 2 p sec
Jumps to m if the condition of the jump keys specified by j exists. If not, the
next instruction is executed.
j = 0 Jump unconditionally
j = 1 Jump if jump key 1 is set
j = 2 Jump if jump key 2 is set
j = 3 Jump if jump key 3 is set
S L S jm
76
Selective Stop
7.2 psec
Stops at present step in the sequence if the condition of the stop key specified by j
exists. If the stop condition exists, the stop is executed, and the jump is executed
unconditionally when the Run/Step key is moved to the RUN or STEP position. If the
KtH)
(:uncI].tion is not satisfied, the jump is executed unconditionally.
j
= 0 Stop unconditionally
'Yj
j = 1 Stop if stop key 1 is set
1=2 Stop if stop key 2 is set
1
fL
2
j = 3 Stop if stop key 3 is set
RETURN JUMP
1) Address modification does not apply to these instructions.
2) One storage reference is made.
A return jump begins a new program sequence at the lower instruction portion of the
program step to which the jump is made. At the same time, the address portion of the
upper instruction of that program step is replaced with the address of the next program
step in the main program. This instruction aliows a return to the main program after
completing the subprogram sequence.
T3j
S
2-29
rOCI
AJP jm
22
7. 2 u su(-
A Jump
Executes a return jump to storage location m if the condition
o ' 1,hü
A
specified by j exists. If not, the next instruction is executeL
j = 4 Return jump if (A)
= 0
j = 5 Return jump if (A) 0
j = 6 Return jump if (A) = +
j
= 7 Return jump if (A) =
-
Note: If (A) = negative zero, refer to the AJP instruction.
MAIN PROGRAM
2ff~
00010
000 11
1 RETURN
1
1 JUMP TO
NST
00101
INSERT
ADDRESS OF
NEXT MAIN
PROGRAM
STEP (00011)
SUBPROGRAM A
UPPER
INST
75
0------
Ii 75 0 00101
Return Jump
2-30
tNSTRUCTION
SUBPROGRAM A
PROGRAM
RETURN tO
SUBPROG.
EXIT
INST
1
00101
RETURN TO NEXT INSTRUCTION
tN MAIN PROGRAM
LOWER
STEPS
-
(rr
QJPjm23
7.2sec
Qjump
Jxecutes a return jump to storage location m if the condition of the Q register
specified by j exists. If not, the next instruction is executed.
j = 4 Return jump if (Q)
0
j = 5 Return jump if (Q)
0
= 6 Return jump if (Q)
+
= 7 Return jump if (Q) = Note: If (Q) = negative zero, refer to the AJP instruction.
S L J jm
75
Selective Jump
7.2 Lisec
Executes a return jump to storage location m on condition j where condition j
represents the setting of the jump keys. If the condition is not satisfied, the next
instruction is executed.
j = 4 Return jump unconditionaily
j = 5 Return jump if jump key 1 is set
j = 6 Return jump if jump key 2 is set
j = 7 Return jump if jump key 3 is set
Note: The set position of a jump key is in the up position.
S L S jm
76
Selective Stop
7.2 jisec
Stops on condition j and executes a return jump to storage location m if the Runi
Step key is moved in the RUN or STEP position. If the stop condition is satisfied,
the stop is executed and the return jump is executed when the Run/Step key is
moved in either position. If the stop condition is not satisfied, the stop is not
executed and the return jump is executed unconditionaily.
j = 4 Stop unconditionally
j = 5 Stop if stop key 1 is set
j = 6 Stop if stop key 2 is set
j = 7 Stop if stop key 3 is set
2-31
-- --
- --
STORAGE TEST
All modes of address modification apply to these instructions.
At least one storage reference is made unless indirect addressing is designated in
which case at least two storage references are made.
SSKbm
Storage Skip
8.8 jtsec
Senses the sign bit of the operand in storage location M. If the sign is negative,
a full exit is taken. If the sign is positive, a half exit is taken. The contents of
the operational registers are left unmodified. SSK is usually restricted to an
upper instruction. Ifused as a lower instruetion and the sign of (M) is negative,
a full exit will be executed. If the sign is positive, it will half exjt upon itseif and
never execute a full exiL
SSHbm
7
StorageShift
12.8isec
Senses the sign bit of the quantity in storage location M. If the sign bit is negative
a full exit is taken, and if the quantity is positive a half exit is taken. In either,
case the quantity is shifted left circulariv one bit before the exit. This instructjon
is usually restricted to the upper position. If used as a lower instruction and the
sign of (m) is positive, the instruction will half exit upon itself until a negative
sign bit is found. The contents of the operational registers are left unmodjfied
1
Left Shift
(M) one place SSH Recorci sign
and return
of (M)
to storage
Reacl M
hfrorn storage
h
Modify
m to M
SSK
No
9)
Full
Exit
SSH and SSK
2-32
1 1
Half
1xit
Instruction
in
(Lo
LOGICAL
All müdes of address modification apply to these instructions.
The LDL, ADL, SBL and STL instructions achieve their result by forming a logical
product. A logical product is a bit by bit multiplication of two binary numbers
(logical AND condition):
0 x 0 0
1 x 0 0
0x1
lxi =1
0
) A logical product is used, in many cases, to select specific portions of an operand
für entry into another operation. For example, if only a specific portion of an
operand in storage is to be added to (A), as the operand passes through X it is
subjected to a mask comprised of a predeterminecl pattern of Olsh and is.
Jorming the logical product of (X) and the mask causes X to retain the Original
ls in the mask. When
(ontents only in those stages which have corresponding
oniy the selected bits rernain in X, the instruction proceeds to conclusion.
SSTbm
40
umw
SelectiveSet
Sets the individual bits of A to
word at storage iocation M.
7.2psec
1 where there are corresponding is in the
rQt
bits in the word at storage iocation M do not
riiodify the corresponding bits in A. In a bit by bit cornparison of (A) and (M)
there are four possihle combinations of bits.
1)
(A). = 1
2) (A). = 1
(M). = 1
(A). = 0
(A). = 0
(M). = 0
(M)
(M).
(A)f = 1
(A)f = 1
(A)f = 1
(A)f = 0
(M) f = 1
(M)f = 0
(M) f = 1
(M)f = 0
SCM bm
42
Selective Compiement
=1
0
7.2 isec
1 1
Individuai bits of A are compiemented where there are corresponding i s in the
word at storage location M. If the corresponding bits at M are OS, the
associated bits of A remain unchanged.
2-33
1)
2) (A). = 1
(A). = 1
3)
(A).
0
4)
(A).
0
1
(M). = 0
(M). = 1
(M). = o
(A)f = 0
(A)f = 1
(A) f = 1
(A)f = 0
1
(M) f = 0
(M) f = 1
(M)f = 0
(M) 1
(M)f
SC L bm 41
Selective Clear
,
7.2 psec
Clears individual bits of A where there are corresponding
storage location M.
If the corresponding bits at M are
115H
hüls,
in the word at
the associated biti
of A remain unchanged.
In a bit by bit comparison of (A) and (M) there are four possible combjnatjons of
bits.
1)
2) (A). = 1
0
(A). = 0
(M). = 1
(A)f = 0
(A)f = 1
(A)f = 0
(A)f
(M)f = 1
(M)f = 0
(M)f = 1
(M)f = 0
(A). = 1
(M)
= 1
(M).
3)
4)
(M). = 0
Instruction
U
im
tpp€r
‚!
2 :
+
M odify
m to M
(f))
*
c
Read (xl)
fro m
storage
SCM
‚SST
Superimose (rti)
and (A). 1s in
(Pvl) complement
corresponding
bits in (A).
SuperimposejY
and (A). l's in
(M) result in l's
in (A)
Execute
Next
Instruction
SCM, SST, and SCL
2-34
(A). = 0
SCL
[rimpe(M)
and (A). i's in
(M) result jn0s
in (A)
0
S S U hrn
Sckctive Substitute
7. 4 lisec
SubstituteS selected portions of an operand at storage address M into the A
register where there are corresponding ItlI in the Q register (mask). The
portions of A not masked by !11,r? in Q are left unmodified
L D L brn
,
44
Load Logical
7 4 jisec
Loads A with the logical product of Q and the contents of the designated storage
location, M. The operand can be in either Q or M.
ADL hrn
45
Add Logical
7.4 jsec
Adds to A the logical product of Q and the quantity in location M; the mask may
be in Q or storage. Once the logical product is formed addition foliows normal
rules (appendix).
S B L hrn
46
Subtract Logical
7. 4 psec
Subtracts from A the logical product of the Q register and the quantity in storage
location M. The mask may be in Q or storage. When the logical product is
formed, the subtraction proceeds in the normal manner. (See appendix.)
STL hrn
47
Store Logical
7. 2 jusec
Replaces the bits in storage location M with the logical product of Q and A
registers. Neither (A) nor (Q) are modified. The mask may be located in A or Q.
/1//
[susflos
1
- - Store
at addrcss
Id
I'ornn Logit-al
produst of
(Q) (A)
STL
lorm 1.ogical
produrt of
(M) 5 (Q)
StIL
ubt rast
frorn
(/t)
AJ)L
siti
0355 110) lor US
in lt. lOs -bar
bits of (Id) vhbh
will not h pla
in lt
Itead (Id)
fron
Storagr
1
Add
tu
(/0
Modify
m to \1
lI)l
1 oad
in
lt
(bar bits in
lt whb-b vill
]
{iiiituts
nasks (1) 0
-Ieared bits o
:xreuto
Next
Instrustion
ADL, LKL, SBL, SSU, and STL
2-35
1 t
--W,Nt
1
STORAGE SEARCH
If b = 0 in the following instructions only the word at storae 10citio11 in wil] }
searched.
If b = 7, indllrect acidressing is used to obtajn the ex(UtjOn addr
in] h
II (Bb) = 0 no seareh is made
z)
EQSbm64
Equality Seareh
14. 0 + 3 6r sec
Searches a list of operands to find one thatt 'it
üal to A. The number of items to
be searched is specified by Bb. These items are in sequential addresses
beginning at the location specified by m. Th& search begins with the last addresS,
m + Bb 1, Bb is reduced one count for each word that is searehed until an
b
operand is found that equals A or until B equals zero. If the search is terminatec]
by unding an operand that equals A. a full exjt is xnacle. The address of the
operand satisfying this condition is given by the sum of m and the final contents of
Bb . II no operand is found that equals A, a half exit is taken. Positive zero and
minus zero are recognized as the same quantity. When EQS is used as a lower
ircstruction, the next instruction will always be executed when the seareh terminates
THSbM65
Threshold Search
M>
4.0 + 3. 6r Msec
Searches a list of operands to find onethat is greater than A. The number of
items to be searched is specified by B . These items are located in sequential
addresseS beginning at the location specified by in. The search begins with the
last address, in + B - 1. The content of the index register is reduced by one for
each operand examined. The search continues until an operand is reached that is
greater than A or until Bb is reduced to zero. If the seareh is terminated by
finding an operand greater than the value in A , afullexjtjserformcd The
addreSs of the operand satisfying the condition is given by the sum of in and the
finalcontefltS of Bh. If no operand in the list is greater than the value in A, a
half exit is performed. If THS is used as a lower instruetion the next instruction
will he execcted wten search terminates. In the comparison made here positive
zero is considerdd as greater than minus zero.
= Number of words searched
2-36
1
1
1
0
1
0
1
1
2S's
---
L
MEQ kirn mw
66
Masked Equality Search
4. 0
4-
3. 6r sec
Scarches a list of operands to find one jizhIhat the logical product of (Q) and (M)
is equal to (A). This instruction, except for the rnask, operates in the Same
nanner as an equa]Jty search.
MTH hrn
Masked Thresholcl Search
67
4. 0 4- 3. 61, psec
Searches a list of operarids to find one such that the logical product of (Q) and (M)
is greater than (A). Except for the mask, this instruction operates in the same
na
11
ar as the tllre5h()Ld s
1115 tru
c t 1011
111
1
U upper
bO
Half
E xit
es
h
Is Search
No
Reduce
Searuh CuurIt
byl
Read (M)
from
Storage
A‚
Det Irin II C
(i\ddross, M»
Iword 10 be
searched - M
1 currerit
THS
I-QS
Is M
Lfl
MFQ
MTH
Is logical
product of
QY\T
I>A
Is Search
nOunt
0
rb
Full
Y es
Is logical
product nf
QM ' A 1
N.
5
tr
lnte
(loc<
Yeu
n
Search
= Number of words searched
2-37
1
r
REPLACE
1 1E
All modes of address modification apply to these instructions.
JE
During the execution of the replace instructions, two storage references are made.
If indirect addressing is designated, at least three references are made.
If the capacity of the A register ± (2
-1) is exceeded during the execution of the
following instructions, an arithmetic overflow fault is produced. (Refer to
appendix.)
RAD bm
[
Replace Add
70
17
13.2 lisec
Obtains a 48-bit operand from storage location M and adds it to the initial
contents of A. The sum is left in A and is also transmitted to location M.
RSB bm
Replace Subtract
71
13.2 psec
Subtracts (A) from (M) and places the result in both the A register and location M.
RAObm
Replace Add One
72
1
13 . 2 Msec
Replaces the operand in storage location M with its original value plus one. The
result is also placed in A.
F
Instruet Ion
1 in
U Upper
Read(M)
from
storage
RAO
Add
1 to(M)
IRAD
r
r
Modify
m to M
RSO
Add
(A)to(M)
Subtract
(A)from(M)
Store result
in A and
Address M.
Subtract
1 from(M)
Execute
Next
Instruct ion
1'
Replace
2-38
1
1i1
RSO bm
73
Replace Subtract One
13. 2 jsec
Replaces the operand in storage location M with its original contents minus one.
The difference is also left in A; the original contents of A and M are destroyed.
TRANSFER
Relative address modification is not used for the following instructions. Only direct
and indirect addressing can be used.
The index registers contain the number of words to be transferred into or out of
the computer via channel 7.
When a transfer is in progress all other computer operations stop except the
processing of input/output requests. A transfer is stopped temporarily to process
interrupter ciock requests.
•)
Ir 1) =
0, one word is transferrc'd to or frorn address m.
Ins t ru c t ion
im
U Upper
(B b
ZINK
)
=
Transfer Count
0
Tra nsfer Ye s
~
Process
Request and
Return
Reduce
Transfer
Count by 1
No
p
Store Input Word
at Address M
M = m + current
Transfer Count
Read Output Wor
from Address M
M = m + current
Transfer Count
Execute
Next
Instruction
No
Yes
there an
(I
lntcerrupt or
k Request
Is transferor
Yes
Transfer
2-39
-
-----------
AM
IN T bm
62
Input Transfer
4.0 + 4. 8r sec
Transfers a block of data from an external equipment into storage. The number
b
of words to be transferred is speci±ied by B . These words are stored in
sequential addresses heginning at the location specified hy the execution address,
m. The transfer begins by storing the first input word in the last address in the
sequence, m + Bb l. As each word is transferred, Bb is reduccd by one until
it is equal to zero.
OUT bm
63
Output Transfer
4 0 + 4. 8r lÄsec
Transfers a block of data from computer storage to an external equipment. The
number of words to be transferred is specified by Bb. The words to be
77
transferred are located in sequential addresses beginning at the locatjon
specified by the execution address, m. The transfer hegins by obtaining the first
output word from the last address, m + ßb -1. As each word is transferred Bb
is reduced by one until it is equal to zero.
(/
L'
ÜtC
' 35Q / coO
:
r
•'j
1
02;
LL
i10
= Number of words transferred
2-40
:
CHAPTER 3
INPUT/OtJTPUT
METHODS OF DATA EXCHANGE
The computer communicates with external equipment via a single transfer channel and
sixjLjtr channels. The transfer channel which provides for high speedommunication
is program initiated and controlled. The buffer channels provide for the normal exchange of data and, although program initiated, operate independently of the program.
HIGH SPEED TRANSFER CHANNEL
The high speed transfer channel (channel 7) handles both input and output communications between the Computer and high speed equipments. The transfer rate is usually
dependent on the speed of the external equipment as the computer can perform transfers
at a maximum (approximate) rate of one word every 4. 8 psec.
As many as five different equipments (optimum conditions) may be connected to the
transfer channel. However, only one equipment can use the channel at any given instant
and the current transfer Operation must be completed before a different equipment can
use the channel.
BUFFER CHANNELS
The six independent buffer channels are grouped in three pairs:
Input: Channel 1
Output: Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
All six buffer channels can communicate concurrently with external equipments. This
is accomplished by an auxiliary scanner which processes only one channel at a given
instant - so that when more than one channel is active each channel is given a turn in
rotation to buffer one word of information. The rate of data flow on each buffer channel
is determined by the operating speed of the external equipment connected to that channel.
A maximum of five equipments may be connected to a buffer channel-pair.
3-1
IN1TIATION AND CONTROL OF DATA EXCHANGE
TRANSFER
A transf er operation is initiated and controlled by the computer program. An INT or OUT
instruction transfers the number of words designated by the contents of an index register.
The starting storage location of the transfer is specified by the execution address of the
instruction. (See chapter 2 for a discussion of the INT or OUT instructions).
All computer operations, with the exception of previously initiated buffers and processing of interrupt or clock requests, stop while the transferring of words is in
progress (refer to page 3-6).
BUFFER
A buffer operation transmits a block of data to or from 1604-A core storage. The size
and location of the block of data is defined by a buffer control word.
Buffer Control Word
Each of the six buffer channels is assigned a buff er control word which controls operations on that channel. The lower address portion of a control word holds the terminal
address (one greater than the address of the last word to be buffered). Before a buffer
operation is initiated, the terminal address must be entered into the control word by a
write instruction (store, substitute, etc). The upper address of a buffer control word
holds the current address of a buffer operation. The starting address (address of first
(word buffered) is automatically entered into theupraddreof the control word by
the EXF Activate command. * After each word of a buffer operation is transmitted the
upper address portion of the control word is automatically increased by one; thus the
upper address is the current address (address of next word to be buffered). When the
upper and lower addresses of a control word are equal the buffer halts.
The buffer control words are assigned core storage addresses but the address portions
are held in 30-bit FF registers called Control registers (CR).
Channel
1
2
3
4
5
6
Control Register
1
2
3
4
5
6
Address of Control. Word
00001
00002
00003
00004
00005
00006
* When reading input words into buffer control word addresses (e. g., Auto Load Operation) the upper address of the input word must be the control Word address plus one.
3-2
f
CORE
STORAGE
ONLY
f
UPPER ADDRESS
b
b
CORE
STORAGE
ONLY
CONTROL REGISTER
AND CORE STORAGE
LOWER ADDRESS
CONTROL REGISTER
AND CORE STORAGE
BUFFER CONTROL WORD STRUCTURE
When a storage reference is made to one of the buffer control words (00001-6) the
address portion is read from or written into the corresponding CR. Because the addresses are contained in the FFs, the control words are destroyed when power is turned
off. For programming purposes the buffer control words (addresses 00001-6) are
treated as normal core storage addresses.
External Function (EXF) instructions
The EXF instructions initiate a buffer, sense for specified conditions, and select Operations and equipment. EXF codes are listed in appendix 6.
There are three kinds of external jnstructions•
Select
74 0
Sense
74 7
Activate
74 j XXXXX
xxxxx
xxxxx
where j = 1-6
The composition of an external function instruction is shown below.
Select and Sense
(EXE) EXTERNJAL FUNCTION CODE
iIIIiiIIliIIIiIl 11111111
OPERATION
CODE (74)
DESIGNATOR CHANNEL EQUIPMENT
0 OR 7
OPERATION
CODE (74)
DESIGNATOR,
1 -6
CONDITION
Activate
STARTING ADDRESS
OF BUFFER
3-3
‚
*—BIT
The 74 0 (EXF$Lect) instructions select the external equipment which is to communicate with the computer. Select instructions also select the mode of Operation of external equipment and various internal conditions (allow interrupts etc.). The select
instructions do not activate the buffer, but rather establish initial operating conditions
within the designated equipment so that information will be properly processed when
the buffer is activated.
The 74 7 (EX Sns&) instructions sense the condition of an external equipment or the
internal conditions of the computer and will execute a full exit or half exit depending on
the presence or absence of the condition.
The location of a 74 7 instruction within an instruction word determines whether a skip
or a wait will be performed.
When used in the upper instruction position (Example 1) a 74 7 is a skip instructiön.
Example 1:
(00010)
74 7 00010
75 0 40000
(00011)
53 1 00005
16 1 00032
In this example the translation of the upper instruction of a program step 00010 is Exit
on Channel 1 active. If channel 1 is active the next instruction to be executed would be
the upper instruction of step 00011, i. e., 53 1 00005. If channel 1 were inactive, the
lower instruction of step 00010 would be executed.
When used in the lower position (Example 2) a 74 7 is a wait instruction.
Example 2:
(00100)
74 2 00600
74 7 00021
(00101)
54 2 00005
75 0 00072
In this case, the transiation of the lower instruction of step 00100 is Exit on Channel 2
inactive. If channel 2 is inactive a full exit is performed to the next pair of instructions,
program step 00101. If, however, the channel is active, the instruction half exists and
repeats itseif until the channel becomes inactive. The sensing of coriditions in no way
alters the condition.
The 74
1
(EXF Activate) instructions activate buffer channel j where j equals 1-6. The
execution address of the instruction, m, must designate the starting address of the
region in storage. These instructions are the only iflStructjons which can initiate a_ buffe r.
3-4
L
Thc following steps should be completed prior to initiating a buffer operation.
Sense for channel inactive.
Select the external equipment and its mode of Operation.
Sense for equipment ready.
Store the terminal address in the buffer control word.
Sensing for equipment ready may involve a number of conditions and varies wjth the
different types of external equipments.
A buffer channel is active while data is being buffered. A buffer channel is inactive if
the previous input/output operation has been completed.
The buffer must be satisfied (current address = terminating address) to inactivate the
channel. This can be accomplished by activating the channel (74 j instruction) at the
terminal address. This makes the channel inactive but no additional information is
trans mitte d.
Auxiliary Scanner
After being initiated by the main program, data exchange on each buffer channel is controlled by the buffer control section. In order that one buffer channel may not monopolize buffer control, an auxiliary scanner is used to initiate each one word buffer. The
auxiliary scanner samples each buffer channel in the order: 1-3-2-6-4-5. When the
scanner detects an auxiliary request from one of the buffer channels it stops and
mi-
tiates a one-word buffer operation. Thus each channel has equal priority.
During a buffer operation the scanner can scan up to four more channels while the
present operation is being carried out. However, if another action request is detected,
another buffer Operation is initiated when the first is finished. This arrangement gives
buffer operations priority over program steps in requests for storage time. If no
action request is detected on the four channels, a storage reference may be made by a
program step and no auxiliary requests may be serviced until storage is released
(6. 4 sec)
PRT F1
IiO
-iS-
7'ic
3
L3Q
o
c
LL+
dOløO
‚coi'' 20ac6f
t/q
1 0(2—>
OOO!
3-5
o";O
FIJLL OR
HALF EXIT
READ NEXT
INSTRUCTION
/ SEARCH OR
TRANSFER
\. INSTRUCTION)
BUFFER
IN lT 1 ATE
C LO CX
REQUEST
\ YES
NO
INITIATE
BU F FE R
(
-
PROCESS
REQU EST
INTERRUPT
REQUEST
CLOCK
REQUEST
YES
YES
PROCESS
REQUEST
PROCES S
REQUEST
I1Q
PROCESS
REQUEST
NO
[BUFFER AcT:
AND
\.ux REQUESJ
ES
ES
1
\ NO
YES
PROCESS
REQUEST
ST
CLOCK
REQUEST
NO
PROCESS
REQUEST
INTERRUPT
REQUEST
CLOCI<
REQUEST
S
NO
NO
ES
EXECUTE
INSTRUCTION
NO
IYES
NO SEARCH OR
TRANSFER
COMPLETE
SEARCH OR
TRANSFER
ONE WORD
1
BUFFER
ONE WORD
NO
BUFFER
COMPLETE
Figure 3-1. 1604-A Flow Chart
3-6
HA LT
BUFFER
•
: •
INTERRUPT
In each external equipment and in certain computer control circuits conditions may
arise which require immediate action by the computer. The signals which notify the
computer of these conditions are called interrupts. Interrupts are controlled by the
computer program. If an interrupt is desired when a particular condition exists, an
external function instruction (74. 0) must be used to select the external equipment to
interrupt on that condition. Unless such a selection is made, no interrupt is produced
when the condition arises. 1604-A interrupts are divided into two classes: (1) interrupts which indicate a fault within the computer (Internal) and (2) interrupts which
indicate a fault in external equipment (External).
Internal Interrupts
Any one of six arithmetic faults may cause an internal (arithmetic) interrupt. These
conditions are controlled collectively by the select instruction: Allow (or Disallow)*
Interrupt on Internal (Arithmetic) Faults (see page 29 of appendix). Internal interrupts
have
tver external interrupts. When an internal interrupt occurs the com-
puter jumps to address 00007 and executes the lower instruction at that location.
External Interrupts
There are eight external interrupt signals for the 1604-A (one for each of the six buffer
channels and two for the high-speed transfer channel). Each of these interrupts may
be allowed or disall ow e d* by its own select code (see page 29 of appendix). In addition,
all external interrupts may be controlled by the instructions:
74 0 04000
74 0 04001
Allow Selected External Interrupts
(Set Master Interrupt Mask)
Disallow (Mask) All External Interrupts
(Clear Master Interrupt Mask)
‚
•
When an external interrupt occurs the computer automatically jumps to one of the
addresses 00010 - 00017 (see table 3-1) and executes the lower instruction.
* Even though an interrupt is disallowed, it may be sensed with a 74. 7 instruction.
3-7
J
TABLE 3-1. INTERRUFT ADDRESSES
Source of Interrupt
Interrupt Address
00007.
Internal (Arithmetic), 1. e.
Overflow fault,
Real Time Clock overflow,
Divide fault, Shift fault,
Exponent Overflow fault and
Exponent Underflow fault.
Channel 7 (Output Transfer)
00010
Channel 1
00011
Channel 2
00012
Channel 3
00013
Channel 4
00014
Channel 5
00015
Channel 6
00016
Channel 7 (Input Transfer)
00017
INTERRUPT SUBROUTINE
An interrupt address (0007-00017) normally contains two jump instructions:
75 0 XXXXX
75 0 YYYYY
When an interrupt occurs, the content of the P register is stored in the upper address
portion (XXXXX) of the interrupt address. This provides for return to the main program
after the interrupt has been processed. The lower instruction at the interrupt address
is a jump to the beginning address (YYYYY) of an interrupt routine. An interrupt
routine (table 3-2) senses for possible cause of the interrupt. When the cause of the
interrupt is determined, a jump is made to that portion of the routine which corrects
the fault (or notifies the operator). The interrupt routine must contain an instruction to
remove the interrupt indication.
TABLE 3-2. TYPICAL INTERRUPT SUBROUTINE
00007
75 0 XXXXX
75 0 yyyyy
Exit/Entrance
Address of next instruction in main program
yyyyy
74 7 00131
yYYYl
-747 ____
750
747 ____
750
74 7 _____
75 0
YYYYn
75 0 ovfo0
Sense Overflow
ovf 0 0
ovf0l
74 0 00070
75 0 00007
L
Clear Arithmetic
Faults
Process
r Overflow
Jump to
L Interrupt Address
After an interrupt has been processed the interrupt routine must provide a jump to
its
interrupt address (0000700017). The upper instructiori at the interrupt address is a
jump back to the main program. At least one instruction of the main program must be
executed before another interrupt can occur.
3-9
REAL TIME CLOCK
Address 00000 in core storage may be selected to provide a continuously operating
record of elapsed time. When the real time ciock is running, the 48-bit quantity stored
at 00000 is advanced by one every 1/60 of a second (accuracy is maintained by the 60cycle power source). The content of address 00000, which may be sampled at any
time, gives an indication of elapsed time from the start of the real-time clock operation.
The ciock may be started by the EXF instruction 74 0 01000 and stopped by 74 0 02000.
Starting the clock does not alter the information already in address 00000.
As shown in figure 3-1, a clock request (generated every 1/60 of a second) has priority
over interrupt requests and can break in between any two instructions.
INTERNAL SELECT INSTRUCTIONS
74 0
C0000
Clear All Channel C Selections
Clears all previous selections made on the designated
channel C except interrupt on channel C inactive.
00000
Allow Interrupt on Channel C Inactive
Selects interrupt when channel C becomes inactive.
C = 1 - 6
An interrupt signal is generated whenever the channel becomes
inactive.
More than one interrupt can be selected.
The
interrupt remains selected until cleared.
000C1
Disallow Interrupt on Channel C Inactive
Interrupt on channel C inactive selection cleared.
00100
Allow Interrupt on Internal (Arithmetic) Faults and Clock Overflow
Selects interrupt on occurrence of any arithmetic fault or ciock
overflow.
00101
Disallow Interrupt on Internal (Arithmetic) Faults and Clock overflow
Prevents arithmetic faults and ciock overflow from interrupting
pro gr am.
00070
Clear Arithmetic Faults and Clock Overflow
Removes all arithmetic and ciock overflow fault indications and
turns off fault background lights on console.
3-10
INTERNAL SELECT INSTRUCTIONS (Cont'd
1 H
01000
Start Real-Time Ciock
Begins process of adding one to contents of address 00000 each
16. 6 ms; address 00000 is not cleared by starting the ciock..
02000
Stop Real-Time Ciock
Haits process of increasing address 00000.
The contents of
00000 remain unchanged.
INTERNAL SENSE INSTRtJCTIONS
74 7
00000
Exit on Channel C Active
Full exit if channel C is active
000C1
Exit on Channel C Inactive
Full exit if channel C is inactive
74 7
001A0
Exit on Arithmetic Fault A
74 7
001A1
Exit on No Arithmetic Fault A
A
=
1: Divide
Shift
Overflow
Exponent overflow
5: . Exponent underflow
74 7
00000
Exit on Channel C Interrupt
74 7
00001
Exit on No Channel C Interrupt
C
=
1-6
74 7
00160
Exit on Channel 7 Output Interrupt
74 7
00161
Exit on No Channel 7 Output Interrupt
74 7
00170
Exit on Channel 7 Input Interrupt
74 7
00171
Exit on No Channel 7 Input Interrupt
74 7
00200
Exit if Next Main Program Instruction is Jpper
74 7
00201
Exit if Next Main Program Instruction is Lower
74 7
00300
Exit on Ciock Overflow
74 7
00301
Exit on No Ciock Overflow
3-11
CONSOLE INPUT/OUTPUT EQUIPMENT
Three input/output devices mounted on the console are standard equipment with the
1604-A computer. A Teletype BRPE 11 punch and a CONTROL DATA 350 reader provide for the processing of perforated paper tape. An electric typewriter provides for
direct keyboard entry of data and for printed copy output. The console input/output
uriits communicate with the central Computer via buffer channels 1 (input) and 2 (output).
Other input/output units may share these channels but console input/output units use
only these channels.
Data may be transmitted between the Computer and the console equipments in either the
character or ass embly mode. Keyboard input from the typewriter is in the jira.cter
er
modeonly.
In the character mode one character is buffered at a time. The typewriter uses 6-bit
characters. The reader and punch use 8-bit characters. When characters of less
than eight bits are desired for the punch and reader the upper bits of the 8-bit character
are 0! s hl.
A character occupies the lowest bit positions of a 48-bit composite word;
the upper bits are
In the assembly mode the 48-bit word, consisting of eight 6-bit characters, is buffered.
During an input buffer in the assembly mode eight successive characters are assembled
into a 48-bit word and sent to the computer. The first character occupies the upper
6 bits of the word; the last character occupies the lower order 6 bits.
For an output buffer in the assembly mode a 48-bit word from the computer is disassembled into eight characters, the upper 6 bits first.
TYPEWRITER
The typewriter may be used as a keyboard input device (character mode only) or as an
output device (either character or assembly mode) for producing printed copy; during
output it types approximately 10 characters per second.
All of the typewriter characters and functions are represented by unique combinations
of 6 bits. (Codes are in appendix X.) During a keyboard input operation, striking a
character key causes the coder to produce the code which is sent to the computer.
Space is the only coded typewriter control function which is sent to the computer. For
typewriter output, a 6-bit character code sent to the decoder causes the typewriter to
print the selected character or perform the designated control function.
3-12
-1
I
I
If the keyboard is selected by code 11140, the interrupt signal occurs for each carriage
1
return (CR).
If an illegal code (unlisted) is sent to the typewriter from the computer, the typewriter
hangs up. Striking the carriage return, backspace or shift keys will allow Operation to
-
r-
be resumed.
A zero code (all "0" bits) which constitutes a do-nothing code is used to fill out a 48-bit
word in the assembly mode.
TYPEWRITER CODES
1
74 0 00200
Clear Carriage Return or Tab FF
Select the Typewriter for Input and No Interrupt on Carriage
11100
Return
Selects keyboard (character mode only)
Interrupt selection cleared, Carriage Return indicator cleared
11140
Select the Typewriter for Input and Interrupt on Carriage Return
Selects keyboard (character mode only)
Interrupt selection set, Carriage Return indicator cleared.
Thenext carriage return, which is not output, will set the
Carriage Return FF and cause an interrupt. The interrupt
selection can be cleared by the external master clear or the
74 0 11100 select only.
OUTPUT SELECT
74 0 21100
Select the Typewriter for Output in the Assembly Mode
Selects keyboard to print*
21110
Select the Typewriter for Output in the Character Mode
Selects keyboard to print*
•
Will not change the Carriage Return FF nor the interrupt selection on channel 1.
The code 1!00u will be ignored; all other illegal codes will cause the typewriter to
hang up. lt is released by manually performing a function, usually spacing.
3-13
TYPEWRITER CODES (Cont'd)
SENSE (Input Channel Only)
74 7 11100
Full Exit if Carriage Return Performed on Input
If a carriage return (which was not the result of an output)
has been performed since the last input select, a full exit
is executed; if not, a half exit.
11101
Full Exit if No Carriage Return Typed on Input
If the Carriage Return indicator is not set, a full exit is
executed; if set, a half exit.
11140
Full Exit Lower Case
If the typewriter keyboard is in the lower case a full exit is
performed.
11141
Full Exit Tjpper Case
If the typewriter keyboard is in the upper case a full exit is
performed.
PAPER TAPE READER
The CONTROL DATA 350 Paper Tape Reader enters information into the Computer from
punChed paper tape. The reader, which is always connected to channel 1, operates at
a maximum rate of approximately 350 frames per second. A frame, which is across
the width of the tape, can store up to 8 bits of information (figure 3-2 shows a sevenlevel tape). The sprocket or feed holes between levels 3 and 4 generate signals to time
the reading of the tape. In the charaCter mode a tape Character may be 5, 6, 7, or 8
bits.
In the assembly mode a CharaCter is six bits and level seven is used as a control bit
(the eighth level is not used in assembly mode). The first of the eight characters in a
word is indicated by a hole in the Control level (figure 3- 2).
Manual Controls for the reader are on the punCh and reader Control panel of the Console
(figure 4-4). When the Reader Mode switch is raised to ASSEMBLY, the tape is positioned at the first frame in which the seventh level is punched (bad point). When the
mode switch is depressed to CHARACTER, the tape moves ahead one frame.
3-14
1
1
r 1
r
ORIENTATION
OF BITS
OF A COMPUTER WORD
CONTROL BIT
071
FEEDHOLES
7
DIRECT ION
-OF TAPE
MOVEMENT
0 0
LEVELS
1
I
1
Figure 3-2. Seven-Level Punched Paper Tape (Assembly Mode)
Reader tape rnotion stops On any one of three conditions:
When buffer Operation terminates (assembly or character mode).
When the bad point in assembly mode is reached.
3) Absence of a 7th level every 8th character in the assembly mode.
*
The reader End of Tape indicator is set on any of three conditions:
On a computer master clear.
Absence of a 7th level every 8th character in the assembly mode.
*
By a 74 0 11210 instruction. This instruction is used to indicate the end of
information in the character mode.
After reading all information on the tape in the assembly mode, tape motion
stops
and
the End of Tape indicator is set because the 7th level control bit is missing. In the
character mode, however, motion stops when the buffer operation is satisfied but the
End of Tape indicator remains cleared. A 74 0 11210 instruction may be programmed
to set the End of Tape indicator after the buffer termiriates. The state of the End of
Tape indicator, regardiess of the mode of operation, may be used to determine if all
information on the paper tape has been read.
*
Only after at least one seventh level bit has been read.
3-15
PAPER TAPE READER CODES
SELECT
74 0 11210
Select Paper Tape Reader and Set End of Tape Indicator
Selects Paper Tape Reader
Sets End of Tape indicator*
Clears interrupt on end of tape
11200
Select the Paper Tape Reader and No Interrupt on End of Tape
Selects the reader
Interrupt on end of tape cleared
11220
Select the Paper Tape Reader and Interrupt on End of Tape
Selects the reader
Interrupt on end of tape set. If the End of Tape indicator is
set, the interrupt will be immediate.
SENSE
74 7 11200
Full Exit on End of Tape Indicator Set
If the End of Tape indicator is set a full exit is performed;
if not, a half exit.
11201
Full Exit on No End of Tape Indicator Set
If the End of Tape indicator is not set a full exit is performed;
if set, a half exit.
11210
Full Exit on Assembly Mode
If the paper tape reader is in the assembly mode a full exit is
performed; if not, a half exit.
11211
Full Exit on Character Mode
If the paper tape reader is in the character mode a full exit is
performed; if not, a half exit.
* This select is usually used in character mode operation only. The End of Tape
indicates the logical end of tape, and can be cleared externally Only by moving the
swjtch (on the reader control) to the CHARACTER or ASSEMBLY position. Master
clear selects the paper tape reader and sets the End of Tape indicator. When the
End of Tape indicator has been set the reader is flot ready".
3-16
PAPER TAPE PUNCH
The punch which prepares paper tape output is always connected to buffer channel 2.
The operating rate is 110 characters per second. In character mode, the lower 8 bits
of each word sent are punched; the upper bits are ignored. In assembly mode, eight
6-bit characters are punched per word. The upper 6 bits are punched first, with the
7th level supplied automatically every eighth frame.
On the punch, the feedout lever provides for punching out leader. A microswitch is
mounted near the roll of paper tape in the punch. When the supply is low, the switch
cioses and provides an out of tape indication which may be sensed and which hights a
console background hight.
The paper tape punch is capable of punching 5, 6, 7, or 8 levels.
1
PAPER TAPE PUNCH CODES
SELECT
74 0 21200
Select the Paper Tape Punch, Assembly Mode
Selects the punch, sets mode to assembly
1'
Turns the punch motor on
21210
Select the Paper Tape Punch, Character Mode
Selects the punch, sets mode to character
Turns the punch motor on
21240
Turn the Punch Motor 0ff
SENSE
74 7 21200
Full Exit on Out of Tape
If the paper tape punch is out of tape, a full exit is performed;
if not, a half exit.
21201
Full Exit on Not Out of Tape
If the paper tape punch is not out of tape, a full exit is
performed; if out of tape, a half exit.
ft
UI
ii
3-17
CHAPTER 4
OPERATION
IJESCHIPTION OF INDICATORS AND CONTROL SWITCHES
All main computer controls and indicators are on the console. Functional significance
of console background lights is listed in table 4-1; computer controls are des cribed in
table 4-2.
Figure 4-1. Center Panel of Console
The indicators are lamp modules, each of which displays a single octal digit. The
lamps., in response to signals from the computer, display the contents of the operational
registers in octal form only when the computer is stopped; the display is blank when
the computer is running. Each indicator has three push buttons which are numbered
in the powers of two, from right to left, starting with zero. Pressing a push button
forces that particular stage of the register to the SET state. Each group of three
buttonS represents an octal digit. To aid in distinguishing between octal digits, the
buttonS for adjacent octal digits are different shades of blue.
At the right end of each register is a Clear push button (white). This button will clear
all the FFs within that register. Set and Clear push buttons should be used only when
the computer is stopped; otherwise errors may result.
4-1
Conditions which stop the computer are listed below. When these conditions exist
register contents may be altered by setting or clearing.
Illegal function codes 00 and 77
Selective Stops (instruction 76)
Breakpoint Stop
Pressing Start/Step switch
Pressing Clear switch (internal master clear)*
At some of the modules there are colored background lights which indicate certain
internal conditions (figure 4-2, table 4-1). A light is identified by the register in which
it is located and its position in the register. For example, AL-4 is fourth from the
left in A register left. In general, red lights signify faults and blue lights signify
special operating conditions. The background lights may be illuminated when the computer is running as well as when it is stopped.
009000000000000000000000
000000000009 090c,909oo, -
-
0 00000000000
0000000000000000
00000000000
00
0000000000000000
:1
0000000000000000
0000000000
L LL
00000000009!!
Figure 4-2. Console Display
*Pressing the Clear switch while the computer is running may destroy the contents of
the storage location being referenced
4-2
TABLE 4-1. CONDITIONS INDICATED BY CONSOLE BACKGROUND LIGHTS
Condition
Light
-
AL-1 (blue)
Interrupt Lockout
AL-2 (red)*
Internal Interrupt Request
AL-2 (blue)
External Interrupt Request
AL-3 (blue)
AL-4 (blue)
AL-5 (blue)
AL-6 (blue)
AL-7 (blue)
AL-8 (blue)
AR-1 (blue)
AR-2 (red)
AR-3 (red)
Computer is in interrupt routine.
\
J
Interrupt request signal is being
received from interrupt circuit.
- Channel 6 is in use for output buffer.
Channel 5 Active - Channel 5 is in use for input buffer.
Channel 4 Active - Channel 4 is in use for output buffer.
Channel 3 Active - Channel 3 is in use for input buffer.
Channel 2 Active - Channel 2 is in use for output buffer.
Channel 1 Active - Channel 1 is in use for input buffer.
Reader Ready - (1) Paper tape is at bad point, ready for an input
Channel 6 Active
buffer; or (2) input buffer paper tape is in progress.
- Punch tape reel is nearly empty.
Odd Storage Fault - Fault in sequence chain of odd storage unit;
Punch Out of Tape
storage unit is inoperative until master cleared.
AR-4 (red)
Even Storage Fault - Fault in sequence chain of even storage unit;
storage unit is inoperative until master cleared.
AR-5 (red)
Divide Fault
AR-6 (red)
Shift Fault
AR-7 (red)
Overflow Fault
-
- Improper divide instruction executed.
Shift count greater than 127 (decimal).
QR-8 (blue)
- Required sum or difference exceeds capacity of
A register.
Exponent Fault - In a floating-point instruction, exponent of result
is 210 or greater.
Storage Not Busy - Indicates when storage is not in use.
Deep End - Computer fails to complete operation in step mode.
PA-1 (red)
1604/1604-A Switch in 1604 position.
PA-5 (blue)
Lower Instruction
FUNCTION CODE
(blue) (3 lights)
Sweep
AR-8 (red)
QR-7 (green)
-
-
Lower instruction is indicated.
Computer is in sweep mode (Mode switch is down).
On both internal and external interrupt requests the light is yelbow.
4-3
Ii
MAIN COMPUTER CONTROLS
TABLE 4-2. MAIN COMPUTER CONTROLS
Function
Control
ON - green
Applies a-c and d-c power to Computer by
energizing contactor in primary power lines
of motor generator.
0FF - red
Removes d-c and a-c power from computer by
de-energizing contactor in primary power lines
of motor generator.
Storage
Test
MARGIN
Varies the bias applied to storage sense
amplifiers. Used for maintenance purposes
only; should be in neutral position at all other
time s.
Lever switch
locks in up,
down and
neutral P 0
tions.
MODE
Up: an instruction is executed repeatedly in
either the step or start mode.
Power
push button
Down: contents of consecutive storage locations
may be manually examined by pressing Step.
Consecutive half-words are displayed in functiori
code and execution address registers but are not
executed.
BreakpOint
Five 8-position switches
can be set to octal address
00000 through
Selective Jumps 1,
2, 3
Three lever switches lock in
upper positions, momentary
in down positions.
Selective Stops 1,
2, 3
Three lever switches lock in
upper position, momentary in
down positions.
Clear
Lever switch, momentary
in up and down positions.
Provides for selection of any storage address as
a breakpoint address. Computer stops when
program address and breakpoint address are
equal, just prior to performing the upper instruction at the breakpoint address.
Provide manual conditions for instructjon 75,
normal jumps, b = 1, 2 or 3, return jumps,
b = 5, 6 or 7.
Provide manual conditions for stopping the
computer on instruction 76, b = 1, 2, 3, 5, 6 or
7.
Up: master clears external equipment, causing
most of the registers and control FFs of the
external equipment to be cleared and the paper
tape reader to be selected.
Down: master clears the computer, clears all
operational registers and most control FFs.
May
destroy content of one storage location if pressed
while Computer is operating.
4-4
MAIN COMPUTER CONTROLS (Cont t d)
TABLi 4-2.
Function
Control
Start IStep
Lever switch, mornentary
in up and down positions.
Volume Control
START (up) selects high-speed mode in which
a program of instructions and auxiliary operations
proceeds until completed or stopped.
STEP (down) selects step mode. Each time
switch is pressed a single instruction is
executed and Computer stops (all buffer requests
are completed before operation stops). Step
selection overrides any previous selection of
start.
Controls volume of signal from console loudspeaker.
Black knob under
console desk
*The Set push buttons,
numbered in the powers of 2,
beginning with zero. EaCh
group of three is an octal digit.
Allow for manual entry of a quantity into a given
register. Forces that particular stage of
register to the set state.
*The Clear push buttons
Clear all FFs within that register.
1604/1604-A Switch
Enables 1604-A to run 1604 programs.
Mounted near console speaker
Figure 4-3.
Manual Controls
* Should be used only when the Computer IS stopped.
4-5
r
READER AND PUNCH CONTROLS
TABLE 4-3. READER AND PUNCH CONTROLS
Function
Switch
Punch Motor
Turns punch motor on or off.
(Motor may also be turned on under program control.
Select/Tape Feed
Select enables use of the punch.
Tape Feed causes leader to be punched.
Reader Motor
Turns reader motor on or off.
(Motor cannot he turned on by any other means.
Character/AsSemblY
In character mode each character is sent to Computer
separat ely.
In assembly mode eight consecutive characters are
assembled into a word to be sent to Computer.
Figure 4-4. Reader, Punch, and Auto Load Controls
4-6
/L9
H'
-Z9
1 Ct
1L
LLA)flf/
AUTO LOAD CONTROL
The Auto Load button initiates a bootstrap routine to read into memory (via channel 3)
the first record from magnetic tape #l, on 1615 or 1607 equipment #2.
I
Pressing the Auto Load button selects the tape and loads the bootstrap routine into
memory locations 00000 and 00001, and puts an address of 32000 (arbitrary and
> 00004) in the lower address of 00003.
The prograrn appears as:
(00000)
(00001)
(00002)
00003)
74 0 32005
Rewind the tape
74 7 32000
Wait for ready
4 3 00002
Activate, FWA = 00002
74 7 32000
Wait for ready
XX X XXXXX
Will be the first
XX X XXXXX
word read from tape
74 3 00002
74 7.32000
The routine will be executed unless Breakpoint is set to 00000 or 00001. The first
word read from tape will be read into location 00002 and be executed as soon as the
tape is ready again. The second word will be reacl into the control word address
(00003). The lower address of the second word sets the buffer terminating address;
the upper address must be 00004 (control word address plus one).
4-7
Ire
OPERATION
The 1604-A is a stored-program computer. To bad a program in the computer a bad
program (basic service library) is needed. The bad program is entered manually. A
paper tape reader, a paper tape punch, an electric typewriter, and a set of magnetic
tapes are some of the important external devices used for communicating with the
1604-A. The programmer, before operating any of these devices, should make himseif
familiar with instructions für these devices and they should be folbowed in the order
r e co mm ende d.
LOAD PROGRAM ENTERING
A bad program to be entered in storage is usualiy on bi-octal paper tape.
The folbowing procedure enters the bad program:
Turn on power.
Master clear, both internal and external.
Press Start/Step switch once.
Clear function code and set to 200.
Clear execution address and set to 00001.
Set terminal address of buffer in bowest five octal digits of A register right.
Press Start/Step switch once.
Load tape into reader.
Turn on reader motor (wait 10 seconds).
Raise reader Mode switch to ASSEMBLY position.
Clear function code and set to 741.
Clear execution address and set to initial address of buffer.
Press Start/Step switch once. Wait until tape boads (console lights come on).
Press Clear switch.
Perform steps 2 through 8 of operation with pre-stored program.
STARTING OPERATION WITH PRE-STORED LOAD PROGRAM
When a general boading program which provides für boading other programs is held in
storage, the starting procedure is as folbows:
Turn on power (Power 0n, figure 4-3).
Make required manual selections:
Selective Jumps
Selective Stops
Breakpoint
Set in operation the external device or devices selected to communicate with
the computer. (Follow the instructions for the devices given in this chapter.
Master clear, both internal and external (press clear, then raise it).
Set Program .Address register to address of first instruction of program.
Begin computer Operation (raise Start switch).
To shut down the equipment after the operation has stopped, follow the
instructions as given for each external device.
Press Power 0ff button, which disconnects power from all equipments.
READER
The reader is a CONTROL DATA 350 paper tape reader (figure 4-5). lt can read
either a 5-, a 7-, or an 8-level tape. For a bi-octal tape with the 7th level control
holes, assembly mode is selected; for a fiex or other code, character mode is selected.
Check if tape basket is at the proper place. Do not allow the tape to fall on
the floor.
Turn tape release lever clockwise to raise tape guide plate.
Select the desired tape level by mans of the tape level switch.
READ STAnON
VEWJNS WINDOW
TAPE E
LEVEL
TC H
IDLER
ROLLE
ENPUT
TAPE GUIDE
PLATE
TAPE WIDTH
GUIDE
Figure 4-5. Paper Tape Reader
4-9
j
Holding the tape guide down, slide it so that the marker rests above the proper
etched mark on the tape deck surface. The outer position is for 8-level tape,
the center for 7-level, and the inner for 5-level.
Insert tape as shown in figure 4-5. Make sure that the tape is properly
aligned.
Turn Tape Release lever counterclockwise to lower the tape guide.
Select the desired mode of Operation by the Mode switch (figure 4-4) on the
control panel.
Turn on Reader switch on control panel (figure 4-4).
After the reader has read the tape, remove paper tape from reader and
basket; rewind tapes.
Turn oft' reader motor.
PUNCH
The paper tape punch (figure 4-6) is mounted on a hinged rack at the rear of the right
wing of the console. Punch tape feeds out of a siot in the compartment door; the chad
box is just inside the door.
To ensure proper performance of the punch, always keep the chad box clean.
Set Punch switch to SELECT (control panel) and check for sufficient paper
in reel.
ll
Figure 4-6. Paper Tape Punch
4-10
1
1
1
1
1
I
1
3) If you have used the punch, generate a foot of leader by pressing tape feed;
remove feed; remove tape and wind it up.
4) Perform the following steps to replace a tape roll at
a) Remove the tape reel from cradle at side of punch.
b) Unscrew tape hold-down assembly, remove old roh, and place new roh
on reel. Replace hold-down assembly and mount reel in cradle.
Thread tape as shown in figure 4-6. Bring tape around lower roller and
into guides leading to punch block.
Turn on punch motor and advance tape through the punch block by pressing
the tape feed-out lever (top of punch block).
Bring leader out through siot in door. Swing punch back into compartment.
TYPEWRITER
The typewriter has all of the characters and functions of a standard electric machine.
As a keyboard entry device the typewriter is used only in the character mode. After
the program selects keyboard and initiates an input buffer, each striking of a key causes
a 6-bit coded character to be entered into the lower six positions of a computer word.
The remaining bits of the word are all !Q
If the keyboard is selected along with an
interrupt feature, each carriage return or tab sends an interrupt signal to the computer.
This notifies the program of the entry of data from the keyboard.
When the typewriter is used as an output device certain conditions cause it to hang up
until the space bar is struck: receipt of an illegal typewriter code, a code to shift up
when the carriage is already up, or a code to shift down when the carriage is already
down.
If the typewriter is to be used:
Place paper in it.
Set the switch beneath the righthand corner to ON.
MAGNETIC TAPE TJNITS
The tape units which can be used with 1604-A are CONTROL DATA 606 and CONTROL
DATA 1607. To use the 606, the CONTROL DATA 1615 Adapter is needed. The codes
for the adapter and the tape unit are given in appendix VI.
4-11
1
606 TAPE UNIT
Controls and Indicator
The manual controls and indicators for operating each tape unit are mounted on a panel
located below the front door of the unit (figure 4-7). The functions of the controls are
described in table 4-4.
READY
UNLOAD
DER SITY
UI
10
Figure 4-7. Operator Control Panel
TABLE 4-4. 606 CONTROLS AND INDICATORS
FUNCTION
NAME
Removes power from all Components and
power supplies.
POWER 0FF
Power is available to components and power
supplies.
FWD
CLEAR
S
Moves tape forward at 150 ips. Motion stops
when end of tape marker is sensed.
1
Tape is moving forward at 150 ips.
S
Master clears all previous settings and
conditions. Stops tape motion immediately.
New Manual selections are necessary to
reseleet tape unit and/or Operation required.
1
606 is cleared
*Switch
**Indjcator
4-12
TABLE 4-4. 606 CONTROLS AND INDICATORS (CONT'D)
NAME
ii
REV
FUNCTION
*S
Rewinds tape at 225 ips. Motion stops when
bad point marker is sensed.
Tape is moving in reverse direction at 150 or
225 ips.
JL1
tf'
WRITE
1
Write Operation is in progress.
UNLOAD
S
Moves tape at 225 ips to unload position (all
tape on supply reel). Tape bad procedure
must be performed to resume operation.
1
Tape is in unload status.
S
Moves tape forward at 150 ips to bad point
marker. Motion stops when marker is sensed.
1
Tape is at bad point marker.
S
Places 606 under external control.
1
Unit is under external control.
5
Changes density mDde selection.
1 (Hi)
1 (Low)
High density mode selected.
Low density mode selected.
READ
1
Read operation is in progress (not on when
reading for horizontal checking during write
operation).
UNIT
SELECTION
S
10-position switch; 0-7 provide input designation while two standby positions disconnect
unit from external control.
1 (White)
1 (Red)
Show selected number.
Fault Condition (power failure, tape not in
columns, etc. ).
1
File protection ring is on reel (unit can write)
and tape unit is not in the unboad position.
LOAD POINT
READY
i 11 11
I11 ,
4
DENSITY
.
OVERHEAD
LIGHTS
L
1
* Switch
** Indicator
',...
4-13
v
Tape Load_Procedure
Make sure that tape unit is properly encrgized.
Slide front glass door down to lowest position (figure 4-8).
Check that supply reel has been file protec±ed as necessary.
Mount reel on supply reel hub and tighten hub knob. For proper aligninerrt,
push reel firmly against hub stop before tightening knob.
Make sure that tape bad arms are in up position.
Pull sufficient tape from supply reel to reach take-up reel. Thread tape on the
outside of the supply tape bad arm, over the head ass embly, around the outsi(Ie
of the take-up bad arm and over the top of the take-up reel hub two or three
times.
Slide tape under head assembiy.
Snap tape bad arms down.
Unit Select Switch
and Status Lights
Overhead Light
Over}iead Light
Take Up Reel
Supply Reel
Tape Load Arry
Tape Load Arm
Glass Door
Figure 4-8. 606 Tape Load and Unload Mechanics
4-14
1
Set Unit Selection switch to one of ten positions (0-7 or standby) to assign a
logical program selection number.
Press Clear switch.
Press Load Point switch. Tape will drop in columns, move forward, and stop
on bad point marker. The Load Point light will turn on. (If the light does not
turn on, notify maintenance.) If tape continues moving forward for more than
3 or 4 seconds, ii indicates either no bad point marker was placed on the tape
or the operator manually wound the marker onto the take-up reel during step 5.
If the unit is to be controlled, press the Ready switch. If it is to be manually
operated and the Ready switch has been pushed, press the Clear
Raise the front glass door completely.
If the supply reel contains a file protection ring, the overhead lights should be on,
indicating that a write operation may be performed. If the lights are not on, notify
maintenance.
Tape Unload Procedure
Press Clear switch.
Press Unload switch. All tape will automatically be drawn from the take-up
reel and wound on the supply reel. The Unload indicator will light.
Slide down front door.
Loosen supply reel hub knob and remove supply reel.
Check if reel needs to be file protected and if it is labeled adequately prior
to storage.
Special Instructions
In order to simulate an unload condition without removing all tape from the take-up
reel, simultaneously press the Clear and Unload switches. The unload condition will
be simulated but tape will not move. In order to place the unit in operational status,
remove all tape from the vacuum columns by revolving the take-up reel clockwise and
the supply reel counterclockwise. Snap the tape bad arms down and press the Load
Point switch. The tape will move forward and stop on the nearest bad point marker.
The Load Point indicator will turn on.
4-15
1
1
If all tape is unwound from the supply reel:
Snap tape bad arms up, if necessary.
1
Guide tape around the tape bad arms, over the head assemhly, and wrap
approximately ten turns around the supply reel.
Slide tape under head assemhly.
-
Press the Load Point switch.
As soon as the Forward light turns on, press the Clear switch and then the
Reverse switch.
Tape will rewind on the nearest bad point marker.
The folbowing information is applicable when a number of bad point or end of tape
markers are used on a single tape.
To move forward from a reflective marker and stop at nearest end of tape marker,
press the Forward switeh.
To move forward off a reflective marker and stop at nearest bad point or end of tape
marker, press the Forward and then the Load Point switches.
Load Point indicator
will light if motion stops at bad point marker.
To reverse from a reflection marker and stop at nearest bad point marker, press the
TJnboad, Clear, and Reverse switches, in that order.
Tape motion may be stopped at any time by pressing the Clear switch.
An unboad
operation may be performed by pressing the tJnboad switch.
1607 TAPE UNIT
Controls and Indicators
Each tape unit is provided with push buttons für manual Operation.
mounted on a panel above the front door
These controls are
(figure 4-9, table 4-5).
poad Procedure
Open door to handler.
Check that file reel to be boaded has been file protected as necessary.
Mount the reel on the file reel hub and tighten the hub knob.
To insure proper
1
reel alignment push the reel firmly against the reel hub stop before tightening
the knob.
If the file protection ring has been removed from the reel, check
that the Write Lockout lamp turns on when the reel is boaded.
If the lamp does
not turn on caib maintenance.
4-16
1
-
-
-
-
TABLE 4-5. 1607 CONTROLS AND INDICATORS
Function
Control
Controls manual rewind to bad point.
REWIND
Indicates rewind in progress.
CHANGE TAPE
WRITE
LOCKOUT
1, 2, 3 or 4
REVERSE
STOP MANUAL
FORWARD
S
Drops any manual selection and places tape unit in
automatic or program control mode.
1
When lighted, indicates tape rewound under program
control and interbocked at bad point. The interlock
prevents Operation of the tape unit until the Stop
Manual switch is operated.
S
Drops power from unit and removes program
designation.
1
When lighted, indicates that tape unit is boaded with
a reel which does not contain a file protection ring.
The tape cannot be written as long as the light is on,
but may be read.
S
Designates program selection of unit and applies
power to unit. Each new unit designation cancels
an existing designation.
1
Indicates unit selection and power-on condition.
S
Initiates reverse tape motion during manual
operation.
1
Indicates reverse tape motion.
S
Drops unit from program control or drops forward
or reverse selection and places unit in manual mode.
1
Indicates manual mode and ready.
5
Initiates forward tape motion during manual mode.
1
Indicates forward tape motion.
*switch
* *indi cator
4-17
1 2 3 4
iREVERSE
FOR WARD
REWI ND
FILE REEL
REEL HUB
CHANGE
TA P E
WR lT E
LOCKOUT
LEADER
CLAMP
HUB KNOB
UPPER REEL
BRAKE
MECHANICAL
SPL ICE
TAKE UP
REEL
Figure 4-9. 1607 Tape Unit
4-- 18
Press upper Reel Brake pushbutton to release mechanical brake and check that
pulling tape from reel causes it to rotate clockwise. Pull sufficient tape from
reel to reach end of permanent machine leader held by leader ciamp.
Connect file tab to permanent machine leader.
Take up siack by turning file reel while pressing upper Reel Brake push button.
Lift leader ciamp and dose door.
Press one of the unit selection switches (1, 2, 3, 4) to apply power to the unit
and assign the unit a logical program selection number. Wait two minutes.
The Stop Manual lamp should turn on; if not, call maintenance.
Press Stop Manual.
•1
10) Press Rewind button. Unit is ready when Rewind lamp turns off. If Stop
Manual lamp remains on, unit is not ready; call maintenance.
Tape Unload Procedure
Press Stop Manual button to select manual mode.
Press Heverse button to move tape backwards to change tape position.
Open front door of tape unit.
To secure tape, lower leader ciamp.
Press the upper Reel Brake button to release the mechanical brake and pull
tape from file reel to provide slack.
I
6) Unfasten mechanical splice which connects the file tab to the permanent machine
Loosen file reel hub knob and remove the file reel.
Check if reel needs to be file protected and also if it is labelled adequately prior
If
to storage.
FILE FROTECTION RING
The back of the file reel has a siot near the hub which accepts a plastic file protection
ring (figure 4-10). Writing on a tape is possible only when the reel contains a file
protection ring. The ring should be removed from the reel after writing iS completed
to avoid accidental rewriting. Tape may be read either with the ring in place or without
it. On the 606 the overhead lights go on immediately after the tape bad procedure is
419
gqwj"
~ I',
Figure 4-10. File Protection Ring
executed if the file protection ring is in place. The Write Lockout light on the 1607 is
off if the file protection ring is in place.
EMERGENCY PROCEDURES
A fault indication, or a warning signal from the buzzer, may call for special procedures
on the part of the operator.
TABLE 4-6. EMERGENCY PROCEDURE
Procedure
Condition
Punch out of tape
Load new roll of tape in punch at end of current operation.
Odd Storage Fault
Master clear.
Restart program.
Even Storage Fault
Master clear.
Restart program.
Deep End
If all I/O operation has ceased, master clear
and restart program. If condition persists, notify
maintenance.
Sweep
Place Mode switch in neutral position.
Buzzer Signal
Notify maintenance engineer immediately.
Faults for which the program provides corrective action are: Divjde, Shift, Overflow
and Exponent Faults. (Refer to appendix.)
4-20
GLOSSARY
ABSOLUTE
ADDRESS
A specific storage location; contrast with relative address.
ACCESS TIME
The time needed to perform a storage reference, either read or
write.
ACCIJMULATOR
A register with provisions for the addition of another quantity to
its content. lt 15 also the name of the A register.
ADDRESS
A 15-bit quantity which identifies a particular storage location.
ALPHABETIC
CODING
A System of abbreviation used in preparing information for input
AND FUNCTION
A logical function in Boolean algebra that is satisfied (has the
value 11t) only when all of ifs terms are "l's'. For any other
into a computer, e. g., Q Right Shift would be QRS.
combination of values it is not satisfied and its value is O'.
A REGISTER
L
accumulator (modulus 248l).
BASE
A quantity which defines some system of representing numbers by
positional notation; radix.
1, 1
Ei
lt4
Principal arithmetic register; operates as a 48-bit subtractive
BIT
Binary digit, either 11 1" or
BLOCK
A specified area of storage to which or from which data is to be
trans mitted.
BOOTSTRAP
The coded instructions at the beginning of an input tape, together
with the manually entered instructions.
1
BORROW
In a subtractive counter or accumulator, a signal indicating that
in stage n, a 'l' was subtracted from a
The Signal is sent
to stage n+l which it complements.
BRANCH
A conditional Jump.
BREAKPOINT
The address at which a program may be stopped by the Breakpoint
switches on the computer console.
B 1 -B 6 REGISTERS Index registers used primarily for modification of execution
address.
' Elli
1
BUFFER
A device in which data is stored temporarily in the course of transmission from one point to another. To store data temporarily.
The
operation in which either a word from storage is sent to an external
equipment via an output channel (output buffer), or a word is sent
from an external equipment to storage via an input channel (input buffer).
BUFFER CONTROL WORD
Each of the six buffer channels is assigned a buffer control word
am
which controls buffer Operations on that channel. The lower address
holds the terminal address plus one of the buffer; the upper address
holds the current or starting address of the buffer.
CAPACITY
The upper and lower limits of the numbers which may be processed
in a register or the quantity of information which may be stored in a
storage unit.
If the capacity of a register is exceeded, an overflow
in
is generated
CARRY
In an additive counter or accumulator, a signal indicating that in
stage n, a '1" was added to a
U1r!
The signal is sent to stage n+ 1,
which it complements.
CHANNEL
Transmission path connecting the Computer to an external equipment.
CHARACTER
Two types of information handled by the Computer:
A group of 6 bits which represents a digit, letter or symbol.
In
assembly mode, eight 6-bit characters make up a computer word.
A group of 5 to 8 bits which represents an item of information.
In the character mode, this item is one 5 to 8-bit character with
Os " in the remaining (upper) bits of a 48-bit word.
CLEAR
A command that destroys the quantity in a register by placing every
stage of the register in the "0" state.
CLOCK
OVERFLOW
A ciock overflow occurs whenever the capacity of the A register is
exceeded during an advance clock instruction.
This condition is
indicated by a visible display, can be sensed by an EXF code, or
may be selected to cause an interrupt.
CLOCK PHASE
One of two outputs from the master ciock,
COMMAND
A signal that performs a unit operation, such as transmitting the
"even" or "odd".
content of one register to another, shifting a register one place to
the left or setting a FF.
2
ji
COMMON CONTROL A 30-bit register used to hold the initial and terminal addresses
REGISTER
(CRu and CRL) of the current buffer Operation while the comparator samples them. The CCR also has counting logic which is used
to advance the address from CRu.
COMPILER
A routine which automatically produces a specific program for a
particular problem.
The routine determines the meaning for
information expressed in a psuedo-code, selects or generates the
required subroutine, transforms the subroutine into specific
coding, assigns storage registers, and enters the information as
an element of the problem program.
COMPLEMENT
Noun: see One's Complement or Two's Complement.
Verb: a command which produces the one's complement of a
given quantity.
CONTENT
The quantity or word held in a register or storage location.
CONTROL
REGISTERS 1-6
30-bit registers used to hold the address portions of the buffer
ll
control words.
The upper address portion (CRu) is advanced
each time a word is buffered and is the current address for a
buffer Operation.
CORE
A ferromagnetic toroid used as the bistable device for storing a
bit in a memory plane.
COUNTER
A register with provisions for increasing or decreasing its
content by 1.
[
EVEN STORAGE
The storage unit which contains the 16, 384 even addresses.
EXECUTION
ADDRESS
The lower 15 bits of a 24-bit instruction.
specify the storage address of an operand.
Most often used to
Sometimes used as
the operand.
EXIT
Initiation of a second control sequence by the first, occurring
when the first is near completion; the circuit involved in exiting.
EXTERNAL
FUNCTION
i
I
External Function Select (74. 0) selects an external equipment
or establishes an internal or external condition.
External Function Sense (74. 7) sends a code to an external
equipment or internal circuit to sense its condition.
3
FAIJLT
Operational difficulty which stops Operation or sets an indicator.
FIXED POINT
A notation or System of arithmetic in which all numerical quantities are expressed by a predetermined number of digits with tue
binary point implicitly located at some predetermined position;
contrasted with floating point.
FLIP-FLOP (FF)
A bistable storage device. A 11 input to the set stde puts the
FF in the 1 state; a 1 input to the clear side puts the FF in
the
11
FLOATING POINT
TQII
state.
input.
The FF remains in a state indicative of its last
A stage of a register consists of a FF.
A means of expressing a number X by a pair of numbers, Y and Z,
such that X
=
Z is an integer, called the exponent or
characteristic; n is a base, usually 2 or 10; and Y is called the
fraction or mantissa.
FUNCTION CODE
The upper 6 bits of a 24-bit instruction which specifv the instru(tion to be executed.
INDEX CODE
A 3-bit quantity, bits 15, 16, and 17 of an instruction; usually
specifies an index register whose contents are added to the
execution address; sometimes specifies the conditions for
executing the instruction.
INSTRUCTION
A 24-bit quantity consisting of a function code, execution address,
and index designator.
INTERRUPT
MASKING
REGISTER (IMR)
Consists of eight FFs which are set or cleared by EXF select
INTERRUPT
REQUEST
A signal received from an external equipment or internal logic
INVERTER
A circuit which provides as an output a signal that is opposite to
codes to apply a mask to the interrupt lines.
If one of these FFs
is set it disaliows the corresponding external interrupt.
that may cause a special sequence of instructions to be executed.
An inverter output is "i fl only if all the separate OR
inputs are "0'.
its input.
JUMP
An instruction which alters the normal sequence control of the
computer and, conditionally or unconditionany, specifies the
location of the next instruction.
4
4
LOAD
To place a quantity from storage in a register.
LOCATION
A storage position holding one computer word, usually designated
by a specific address.
LOGICAL
PRODUCT
LOGICAL SUM
In Boolean algebra, the AND function of several terms. The product is '1 only when all the terms are 111; otherwise it is '0'.
Sometimes referred to as the result of 'bit-by-bit" multiplication.
In Boolean algebra, the OR function of several terms. The sum
is "1" when any or all of the terms are 11 1 1
all are "0".
LOOP
;
it is "0" only when
Repetition of a group of instructions in a routine.
LOWER ADDRESS The execution address portion of a lower instruction; bits 0 through
14 of a 48-bit register or storage location.
LOWER
INSTRUCTION
See Program Word.
MASK
In some instructions, one quantity may determine what part of the
other quantity is to be considered. If the first quantity, the
contains a "1", the corresponding bit of the second quantity is
considered.
-
A rank of eight FFs through which external interrupt signals enter
MASKED
INTERRUPT
REGISTER (MIR)
the 1604-A. The inputs to MIR can be masked (disallowed) by the
MASTER CLOCK
The source of standard signals required for sequencing computer
j
IMR.
operation. The clock determines the basic frequency of the
[
computer.
MASTER CLEAR A general command produced by placing the Clear switch up
(MC)
(external MC) or down (computer MC) which clears most of the
crucial registers and control FFs (some FFs are set by MC).
MASTER INTER- A FF for masking all external interrupts.
RUPT MASK (MIM)
MNEMONIC CODE A three-letter code which represents the function or purpose of an
instruction. Also called Alphabetic Code.
5
111
1
-
--
MODULUS
An integer which describes certain arithmetjc characteristics of
registers, especially counters and accumulators, within a digital.
computer. The modulus of a device is defined by r" for an opErnended device and r"-1 for a closed (end-around) device, where i is the base of the number System used and n is the number of dLil,
positions (stages) in the device. Generaily, devices with modu1u
rnl use twos complement arithmetic; devices with modulus rn_l
use onels complement.
NORMALIZE
To adjust the exponent and mantissa of a floating-point result so
that the mantissa lies in the prescribed standard (normal) rang.
NORMAL JUMP
An instruction that jumps from one sequence of instructjons to a
second, and makes no preparation for returning to the first
5 equ
enc e.
NUMERIC CODING A system of abbreviation in which all information is red000(I to
numerical quantities.
ODD STORAGE
The storage unit which contains the 16, 384 ocld addresses.
ONE'S
COMPLEMENT
With reference to a binary number, that number which resuits
from subtracting each bit of the given number from 11 1 1t . The
one's complement of a number is formed by complementing each
bit of it individually, that is, changing a "1" to "O' and a
to
a 1 . A negative number is expressed by the one's complement
t1Ot
of the corresponding positive number.
ON-LINE
OPERATION
A type of System application in which the input data to the System
OPERAND
Usually refers to the quantity specified by the execution address.
is fed directly from the external equipment to the computer.
This quantity is operated upon in the execution of the instruction.
OPERATIONAL
REGISTERS
Registers which are displayed on the Operator's console (B 1 -B 6 ,
A, Q, P, U 1 ).
OPERATION
CODE
The upper 6 bits of a 24-bit instruction which identify the instruction. After the code is translated, it conditions the computer for
execution of the specified instruction. This code, which is
expressed by two octal digits, is designated by the letter f.
6
L
01 - 4 REGISTERS Output registers 01, 2, are used for output buffer operations;
04 handles all high-speed output transfer operations.
OR FUNCTION
A logical function in Boolean algebra that is satisfied (has the
fl1I)
11l•
value
when any of its terms are
lt is not satisfied when
all terms are
Often called the 'inclusivet OR function.
0VERFLOW
The capacity of a register is exceeded.
PARITY CHECK
A summation check in which the binary digits in a character are
added and the sum checked against a previously computed parity
cigit; i. e., a check which tests whether the number of ones is
odd or even.
PARTIAL ADD
An addition without carries. Accomplished by toggling each bit
of the augend where the corresponding bit of the addend is a
P REGISTER
The Program Address Counter is a two's complement additive
15
register (modulus 2
) which generates in sequential order the
storage addresses containing the individual program steps.
PROGRAM
A precise sequence of instructions that accomplishes a computer
routine; a plan for the solution of a problem.
PROGRAM WORD
Two 24-bit instructions contained in one 48-bit storage address;
the higher-order 24 bits are the upper instruction, lower-order
24 bits, the lower instruction. A pair of instructions is read from
storage, and the upper instruction is executed first. The lower
one is then executed, except when the upper one provides for
skipping the lower one.
Q REGISTER
Auxiliary arithmetic register which assists the A register in the
more complicated arithmetic operations (modulus 248_1).
RANDOM ACCESS
Access to storage under conditions in which the next position
from which information is to be obtained is in no way dependent
on the previous one.
R REGISTER
Address Buffer register. Two's complement subtractive register
15
) which acts as an exchange register for trans(modulus 2
missions involving index registers.
READ
To obtain a quantity from a storage location.
7
'
t1
READY
1) An input/output control signal sent by the computer or an
external equipment. The ready signal indicates that a word or,
character is available for transmission.
2) A status response indicating that the external device being
addressed is ready for Operation.
RELATIVE
ADDRESS
Identifies a word in a subroutine or routine with respect to its
position. Relative addresses are translated into absolute addresses
by the addition of some specific reference address, usually that at
which the first word of the routine is stored.
REPLACE
In the title of an instruction, the result of the execution of the
instruction is stored in the location from which the initial operand
was obtained.
RESUME
The input/output control signal sent hy either the computer or an
external equipment to indicate that it is prepared to receive
another word (48 bits) or character (usually 6 bits).
The resume
signal is thus a request for data.
RETURN JUMP
An instruction that jumps from a sequence of instructions to initiate
a second sequence and prepares for returning to the original
sequence after the second is completed.
ROUTINE
The sequence of operations which the computer performs under the
direction of a program.
S 1 REGISTER
Storage Address register (even storage).
Selects the storage
address specified by the contents of the P register.
S 2 REGISTER
Storage Address register (odd storage).
Selects the storage
address specified by the contents of the P register.
SCALE FACTOR
One or more coefficients by which quantities are multiplied or
divided so that they lie in a given range of magnitude.
SCANNER
A circuit used to search for one of a number of possible conditions
and to initiate action when a condition is detected.
The auxiliary
scanner scans the six buffer channels for auxiliary requests; the
interrupt scanner looks for interrupt requests from external
equipments.
2
2,
SECONDARY
REGISTERS
Transient registers not displayed on the console (U2,
6
R, X, 01 0 ).
SFIIFT
To move the bits of a quantity right or left.
SIGN BIT
In registers where a quantity is treated as signed by use of one's
l,
complement notation, the bit in the highest-order stage of the
register.
Fron
If the bit is "1", the quantity is negative; if the bit is
the quantity is positive.
SIGN
EXTENSION
The duplication of the sign bit in the higher-order stages of a
SKIP
To omit the execution of a lower instruction in a program; occurs
register.
only if the upper instruction provides for skipping on a specified
condition, and the condition is met.
STAGE
The FFs and inverters associated with a bit position of a register.
STORE
To transmit information to a device from which the unaltered
information can later be obtained.
SUBINSTRUCTION
The index code specifies one of eight forms of the instruction
indicated by the Operation code. Such forms are called "subinstructions?I. Thus, 74. 0 is a subinstruction of instruction 74.
TOGGLE
To complement each bit of a quantity as a result of an individual
condition.
TRANSFER
High-speed data input/output transmission under direct program
co nt rol.
TRANSMISSION,
FORCED
A transfer of bits into a register which has not been cleared
TRANSMISSION,
ONES
A transfer of ones into a register which has been cleared.
TRANSMISSION,
ZEROS
A transfer of zeros into a register which has been set.
TWO'S
COMPLEMENT
Number that resuits from subtracting each bit of a number from
previously.
The two's complement may be formed by complementing each
bit of the given number and then adding one to the result, performing the required carries.
REGISTER
Program Control register. Holds a program step while the two
instructions contained in it are executed.
REGISTER
Auxiliary Program Control register. A 15-bit subtractive
accumulator (modulus 215_1) used primarily for modification
of the base execution address.
UPPER ADDRESS
The execution address portion of an upper instruction; bit
positions 24 through 38 of a 48-bit register or storage address.
UPPER
INSTRUCTION
See Program Word.
WORD
A unit of information which has been coded for use in the Computer
as a series of bits.
The normal word length 15 48 bits.
WRITE
To enter a quantity into a storage loCation.
X REGISTER
Exchange register.
Most internal transmissions between the
arithmetic section and the rest of the Computer are made through
X.
REGISTER
Storage Restoration register (even storage).
Holds the word to
be written into a given storage loCation.
REGISTER
Storage Restoration register (odd storage).
be written into a given storage location.
10
Holds the word to
L
APPENDIX SECTION
ii
‚ l ji
lii
ri
APPENDIX 1
NUMBER SYSTEMS
Any number systurn rnay he defined by two characteristics, the radix or base and the
moclulus. The radix or base is the number of unique symbols used in the system. The
decimal system has ten symbols, 0 through 9. Modulus is the number of unique
quantities or magnitudes a given system can distinguish. For example, an adding
machine with ten digits, or counting wheels, would have a modulus of 10 10 1. The
decimal system lias no modulus because an infinite number of digits can be written, but
the adding machine has a modulus because the highest number which can be expressed
is 9, 999, 999, 999.
Most number systems are positional, that is, the relative position of a symbol determines its magmtude. In the decimal system, a 5 in the units column represents a
different quantity than a 5 in the tens column. Quantities equal to or greater than 1 may
be represented by using the 10 symbols as coefficients of ascending powers of the base
10. The number 98410 j
9 x 10 2 = 9 x 100 = 900
+8 x 101 = 8 x 10 = 80
+4 x 100 = 4 x
4
1=
me
Quantities less than 1 may be represented by using the 10 symbols as coefficients of
ascending negative powers of the base 10. The number 0. 59310 may be represented as:
5 x 10
=5x.1
= .5
+9 x 10 2 = 9 x .01 = .09
+3 x 10
= 3 x .001 = .003
0.
BINARY NUMBER SYSTEM
Computers operate faster and more efficiently by using the binary number system.
There are only two symbols 0 and 1; the base = 2.
The following shows the posi-
tional value.
2
=32
2
=16
2
=8
22
=4
20
=l
21
=2
1
Binary point
1
The binary number 0 1 1 0 1 0 represents:
o
x 2
+1 x 2
= 0x
2 =
0
= 1 x 16 = 16
+1x2 3 =1x8
=
+0x2 2 =0x4
=
0
+1 x 21 = 1 x 2
=
2
+0x2 0 =0 x1
=
0
26 10
Fractional binary numbers may be represented by using the symbols as coefficients of
ascending negative powers of the base.
Binary Point
2 1
22
2
2
=1/2
=1/4
=1/8
=1/16 =1/32
2
The binary number 0.10 110 may be represented as:
1 x 2_1 = 1 x 1/2 = 1/2 = 8/16
=0
+0x2 2 =0x1/4 =0
+1x2 3 =1x1/81/82/16
+1 x 2
= 1 x 1/16 = 1/16 = 1/16
li/l u lO
= 0.6875
OCTAL NUMBER SYSTEM
The octal number system uses eight discrete symbols, 0 through 7 With the base eight
the positional value is:
8
8
8
32, 768
4,096
512
The octal number 5138 represents:
5 x 82 = 5 x 64 = 320
+1x8'
1 x 8 =
8
+3x8 0 =3x1 =
3
331 10
2
82 81 80
64
8
1
111
Fractional octal numbers may be represented by using the Symbols as coefficients of
ascending negative powers of the base.
8
1/8
8- 2
8
1/64
1/512
8
1/4096
The octal number 0. 452 0 represents:
4x8
= 4 x 1/8
= 4/8
= 256/512
+5 x 8
= 5 x 1/64 = 5/64 = 40/512
+2 x 8
= 2 x 1/512 = 2/512 =
2/512
298/512 = 149/25610 = .5811
AR.ITHME TIC
ADDITION AND STJBTRACTION
Binary numbers are added according to the following rules:
0+ 0 = 0
0+1 = 1
1+0=1
1 + 1 = 0 with a carry of 1
The addition of two binary numbers proceeds as foliows (the decimal equivalents verify
the result):
Augend
0111
(7)
Addend
+0100
+(4)
1011
(11)
Sum
SubtractiOn may be performed as an addition:
8 (minuend)
-6(subtrahend)
2 (difference)
1000 (minuend)
or
+1001 (one's complement of subtrahend)
0001 (partial sum)
1 (carry)
0010 (difference by addition)
3
On& s Complement
The 1604-A performs all arithmetic Operations in the binary onet s complement mode.
In this system, positive numbers are represented by the binary equivalent and negative
numbers in one's complement notation.
The one's complement representation of a number is found by subtracting each bit of
the number from 1. For example:
1111
-1001
9
0110
(one's complement of 9)
This representation of a negative binary quantity may also be obtained by substituting
'tjI" for tIOt s ? and "O's" for tTltst.
The value zero can be represented in one's complement notation in two ways:
0000 002
Positive (+) Zero
1111
Negative (-) Zero
112
The rules regarding the use of these two forms for computation are:
Both positive and negative zero are acceptable as arithmetic operands.
If the result of an arithmetic operation is zero, it will be expressed as positive
zero. The one exception to this rule is when negative zero is added to negative
zero.* In this case, the result is negative zero.
One's complement notation applies not only to arithmetic operations performed in A,
but also to the modification of execution addresses in the U register. During address
modification, the modified address will equal 77777 only if the unmodified execution
address equals 77777 and b = 0 or (B ) =
-1
Two's Complement
The counters in the computer use two's complement arithmetic. A counter is a register
1
with provisions for increasing its contents by one if it is additive (P register) or
decreasing its contents by one if it is subtractive (R register). A two's complement
counter is open-ended; there is no end-around carry or borrow.
* When a 1604-A instruction calls for subtracting positive zero from negative zero, the
computer complements the subtrahend and adds so that the actual Operation is the
addition of negative zero to negative zero and the result is negative zero.
-
4
r1
1-
Positive numbers have the same representation in both systems while negative values
ciiffer by one count.
2's comp. rep.
(ount
is comp. rep.
2
00010
00010
+1
00001
00001
0
00000
00000
-1
11111
11110
-2
11110
11101
The difference in the representation of negative values in these two systems is due to
the skipping of the all ones count in one's complement notation. In the ones complement system the end-around-carry feature of the register automatically changes a count
of all one's to all zeros. (Note exception under one's_complernent.)
As an example, if the content of a suhtractive counter is positive seven (0111) and is to
be reduced by one, add the two' s compkment expression of negative one. (1111), to 0111
as shown below. The result is six.
0111
+1111
0110
Note that the two's complement expression for a negative number may also be formed by
adding one to the one's complement representation of the number.
MULTIPLICA TION
Binary multiplication proceeds according to the following rules:
0 x 0 0
Dxl =0
1 xO = 0
lxi =1
Multiplication is always performed on a bit-by-bit basis. Carries do not result from
multiplication, since the product of any two bits is always a single bit.
5
Decimal example:
multiplicand
14
multiplier
12
partial products
28
14
(shifted one place left)
product
The shift of the second partial product is a shorthand method for wi ifin8 the true vahw
140.
Binary example:
multipUcand
(14)
1110
multiplier
(12)
1100
0000
0000
partial products
1110
1.
product
shift to place digits
in proper coumns
1110
10101000 2
( 168 10 )
The computer determines the running subtotal of the partial products. Rather than
shifting the partial product to the left to position it correctly, the Computer right shifts
the summatiori of the partial products one place before the next addition is made. When
the multiplier bit is
F 1,
the multiplicand is added to the running total and the results
are shifted to the right one place. When the multiplier bit is
the partial product
subtotal is shifted to the right (in effect, the quantity has been multiplied by 102).
DIVISION
The following example shows the familiar method of decimal divigjoiv
divisor
13
14
quotient
185
dividend
13
55
partial dividend
52
remainder
3
Ne
uin puter performs division in a sirnilar maniier (using binary equivaleuts):
1 101
divisor
1110
(iuotient
10111 001
dividend
(14)
1101
10100
1101
1110
partial dividends
1101
ii
remainder (3)
1-lowever, instead of shifting the divisor right to position it for suhtraction from the
partial dividerid (showo ahove), the computer shifts the partial dividend left, accomplishing the same purpose and permitting the arithmetic to be performed in the A
register. The computer counts the number of shifts, which is the number of quotient
digits tu he ohtained; after the correct numher of counts, the routine is terminated.
CONVERSIONS
0
The procedures that may he used when coriverting from one number system to another
are power addition, double dabble, and substitution.
Recommended Conversion Procedures (Integer and Fractional)
Conversion
Recommended Method
Binary tu Decimal
Power Addition
Octal tu Decirnal
Power Addition
Dcc imal to Binary
Double Dabble
Decimal to Qctal
Double Dabhle
Binary to Octal
Substitution
Octal to Binary
Substitution
GENERAL RULES
r. > r f : use Doub'e Dabble, Substitution
r. < r f : usc Power Addition, Substitution
r i = Radix of initial system
r f = Radix of final system
7
POWER ADDITION
To convert a number from r 1 to rf (r 1 < r f ) write the number in its expanded r. pol nomial form and syrnplify using rf arithmetic.
Binary to Decirnal (Integer)
EXAMPLE 1
010 1112 = 1 (2) +0 (2) + 1(22) + 1 (21) + 1 (20)
= 1 (16) + 0 (8) + 1 (4) + 1(2) + 1 (1)
=16
+0
+4
+2
+1
23 io
Binary to Decimal (Fractional)
EXAMPLE 2
.01012
= 0 (2 1 ) + 1(22) + 0 (2) + 1 (2)
+1/4
+0
1/16
= 5/1610 = 0.3125
Octal to Decimal (Integer)
EXAMPLE 3
3248
= 3 (8
2
) + 2 (81) + 4 (8)
= 3 (64) + 2 (8) + 4 (1)
= 192
=
EXAMPLE 4
+ 16
+ 4
212 10
Octal to Decirnal (Fractional)
= 4 (8) + 4 (8)
4/8
+ 4/64
= 36/6410 = 0. 5625
DOUBLE DABBLE
To convert a whole number from r. to r f (r. > rf ):
Divide r by r f using r. arithmetic
The remainder is the lowest order bit in the new expressjon
Divide the integral part from the previous Operation by r f
The remainder is the next higher order bit in the new expression
The process continues until the division produces Only a remainder which will
be the highest order bit in the r f expression.
To convert a fractional number from r. to r f :
Multiply r i by rf using r. arithmetic
The integral part is the highest order bit in the new expression
Multiply the fractional part from the previous operation by rf
The integral part is the next lower order bit in the new expression
The process continues until sufficient precision is achieved or the process
terminates.
EXAMPLE
Decimal to Binary (Integer)
1
45
22
11
5
2
1
2
2
2
2
= 22 remainder 1; record
= 11 remainder 0; record
= 5 remainder 1; record
= 2 remainder 1; record
2 = 1 remainder 0; record
2 = 0 remainder 1; record
Thus: 45 10 = 1011012
EXAMPLE 2
EXAMPLE 3
0
0
1
101101
Decimal to Binary (Fractional.)
.25 x 2 = 0.5; record
0
• 5 x 2 = 1. 0; record
1
.0 x 2 = 0.0; record
0
.010
Thus: . 25 io = . 0102
Decimal to Octal (Integer)
8 = 34 remainder 1; record
273
34 - 8 = 4 remainder 2; record
8 = 0 remainder 4; record
4
Thus: 27310 = 4218
1
2
4
421
EXAMPLE 4
Decimal to Octa (Fractional)
.55x8=4.4;record
4
.4 x 8 = 3.2; record
3
.2 x 8 = 1. 6; record
Thus:
431...
.431.. 8
SUBSTITUTION
This method permits easy conversion between octal and binary representations of a
number. If a number in binary notation is partitioned into triplets to the right and left
of the binary point, each triplet may be converted into an octal digit. Similarly each
octal digit may be converted into a triplet of binary digits.
EXAMPLE 1
Binary to Octal
Binary = 110 000 . 001 010
Octal =
EXAMPLE
2
6 0
1
2
Octal to Binary
Octat = 6
5
0
2
2
7
Binary = 110 101 000 . 010 010 111
KE
COM1vION PIJRE NOTATIONS
Decinial
F1inaiy
Octal
00
00000
00
01
00001
01
02
00010
02
03
00011
03
04
00100
04
05
00101
05
06
00110
06
07
00111
07
08
01000
10
09
01001
11
10
01010
12
11
01011
13
12
01100
14
13
01101
15
14
01110
16
15
01111
17
16
10000
20
17
10001
21
POWERS 01' COMMON NUMBER SYSTEMS
64
=
8
8
=
512
2
=
16
8
=
2'
26
=
32
=
64
8=
86 =
2
28
=
128
8
=
2,097, 152
=
256
8
=
16, 777, 216
2
2 10
=
512
11
=
1,000
4,096
10=
10, 000
32,768
10=
106 =
100,000
262, 144
103
1,000,000
rF
Ii
1
FLXED POINT I\ND FLOATING POINT NUMBERS
ny num.ber may be expressed in the form kB ° , where k is a coeffjcjent, II a base
numher, and the exponent n the power to which the base numher 1 s ra 1 sed.
A fixed point number assumes:
The exponent n = 0 for all fixed point numbers
The coefficient, k, occupies the same bit positions within the computer word for
all fixed point numbers.
The radix (binary) point remains fixed with respect to one end of the expression.
A 1604 fixed point number consists of a sign bit and coefficient as shown below. The
upper bit of any 1604 fixed point number designates the sign of the coefficient (47 lower
order bits). If the bit is 1 ‚ the quantity is negative since negative numbers are
represented in one's complement notation; a 0 sign bit signifies a positive coefficient.
¶
BIT NO.
47 46
SIGN
BIT
::i]L
001
COEFFICIENT
=
The coefficient may be an integer or fraction. The radix (binary) point, in the case of
an integer, is assumed to be immediately to the right of the lowest order bit (00). In
the case of the fraction, the point is just to the right of the sign bit.
LJ
In many instances, the values in a fixed point operation may be too large or too small to
be expressed by the computer. The programmer must position the numbers within the
word format so they can be represented with sufficient precision. The process, called
scaling, consists of shifting the values a predetermined number of places. The numbers
must be positioned far enough to the right in the registerto prevent overflow but far
enough to the left to maintain precision. The scale factor (number of places shifted) is
expressed as the power of the base. For example, 5, 100, 000 10 may be expressed as
0.051 x 10 8 , 0.0051 x 10
0.51 x 10
etc. The scale factors are 7, 8, and 9.
Since only the coefficient is used by the computer, the programmer is responsible for
rememberirig the scale factors. Also, the possibility of an overflow during intermediate
operations must be considered. For example, if two fractions in fixed point format are
12
-
multiplied, the result is a number < 1. If the same two fractions are added, subtracted,
or divided, the result may be greater than one and an overflow will occur. Similarly,
if two integers are multiplied, divided, subtracted or added, the likelihood of an overflow is apparent.
As an alternative to fixed point operation, a method involving a variable radix point,
called floating point, is used. This significantly reduces the amount of bookkeeping
required on the part of the programmer.
By shifting the radix point and increasing or decreasing the value of the exponent, widely
varying quantities which do not exceed the capacity of the machine may be handled.
Floating point numbers within the Computer are represented in a form similar to that
used in usCientifiCu notation, that is, a coefficient or fraction multiplied by a number
raised to a power. Since the Computer uses only binary numbers, the numbers are
multiplied by powers of two.
F
where: F = fraction
E = exponent
In floating point, different coefficients need not relate to the same power of the base as
they do in fixed point format. Therefore, the construction of a floating point number
includes not only the coefficient but also the exponent.
47
COEFFICIENT
SI GN
46
36 35 -------------00
EXPONENT
COEFFICIENT
The coefficient consists of a 36-bit fraction in the 36 lower-order positions of the floating
point word. The coefficient is a normalized fraction; it is equal to or greater than 1/2
but less than 1. The highest order bit position (47) is occupied by the sign bit of the
coefficient. If the sign bit is a 0, the coefficient is positive; a Ii! bit denotes a
negative fraction (negative fractions are represented in ones complement notation).
13
Exponent
The floating point exponent is expressed as an 11-bit quantity with a value ranging from
lt is formed by adding a true positive exponent and a bias of 20008
00008 to
true negative exponent and a bias of 17778. This results in a range of biased exponents
as shown below.
Biased
Exponent
True Positive
Exponent
True Negative
Exponent
Biased
Exponent
+0
2000
-0
2000
+1
2001
-1
1775
+2
2002
-2
1775
+1776
3776
-1776
0001
+17778
3777 8
_ 1777 8
0000
The exponent is biased so that floating point operands can be compared with each oth€'r
in the normal fixed point mode.
i\s an example, compare the unbiased exponents of +528 and +0. 02 8 (Example 1).
Number = +52
EXAMPLE 1
00
0
000
000
110
Exponent
Coefficient
Sign
(36 bits)
Coefficient
Number = +0.02
0
Coefficient
Sign
11
111
111
Exponent
011
(36 bits)
Coefficient
In this case +0.02 appears to be larger than +52 because of the larger exponent. if,
however, both exponents are biased, (Example 2) changing the sign of both exponents
makes +52 greater than +0. 02.
Minus zero is sensed as positive zero by the Computer and is therefore hiased by
20008 rather than 1777 8.
14
Number = +52 3
EXAMPLE 2
10
0
Co effic i ent
Sign
000
000
110
Exponent
(36 bits)
C oeffic i ent
Number = + 0 . 02 8
01
0
Coefficient
S ign
111
111
Exponent
011
(36 bits)
Coefficient
When bias is used with the exponent floating-point Operation is more versatile since
floating-point operands can be compared with each other in the normal fixed point mode.
CONVERSION PROCEDURES
Fixed Point to Floating Point
Express the number in binary.
Normalize the number. A normalized number has the most significant 1 positioned immediately to the right of the binary point and is expressed in the range
i/2k <1.
Inspect the sign of the true exponent. Tf the sign is positive add 2000 8 (bias) to
the true exponent of the normal.ized number. T.f the sign is negative add the bias
17778 to the true exponent of the normalized number. In either case, the
resulting exponent is the biased exponent.
Assemble the number in floating point.
Inspect the sign of the coefficient. J.f negative, complement the ass embled
floating point number to obtain the true floating point representation of the
number. If the sign of the coefficient is positive the assembled floating point
number 15 the true representation.
EXAMPLE
1
Convert +4. 0 to floating point
The number is expressed in octal.
Normalize. 4.0 = 4.0 x 8 = 0.100 x 2
Since the sign of the true exponent is positive, add 2000 8 (bias) to the true
exponent. Biased exponent = 2000 + 3.
15
Assembie riurnber in floatinotni
Co(-, fficient = 400 000 000 (00
Biased Exponent = 200 :3 8
ssembIed word = 2003 400 000 000 000
0
Since the sign of the coefficient. is positive, the floating point representation of
+4.0 is as shown. If, however, the sign of the coefficient were negative, lt
would be necessary to complernent the entire floating point word.
Convert -4.0 to floating point
The number is expressed in octal.
Normalize. -4.0 = -4.0 x 80 = -0.100 x 2
Since the sign of the true exponent is positive, add 20008 (hias) to the true
exponent. Biased exponent = 2000 + 3.
.Assemble number in floatirig point format.
EXMPLE 2
Coefficit.nt = 400 000 000 0008
Biased Exponent = 20038
Assernbied word = 2003 400 000 000 0008
Since the sign of the coefficient is negative, the assernbled floating point word
rnust be compiemented. Therefore, the true floating point representation for
-4.0 = 5774 377
EXAMPLE
Convert 0. 5 10 to floating point
3
Convert to octat. 0.5 lo = 0.4
Normalize. 0.4 = 0.4 x 8 = 0. 100 x 2
Since the sign of the true exponent is positive, add 20008 (bias) to the true
exponent. Biasecl exponent = 2000 + 0.
Assemb1e number in floating point format.
Coefficient = 400 000 000 0008
Biasecl Exponent = 20008
Assembled word = 2000 400 000 000 0008
Since the sign of the coefficient is positive, the floating point representation of
+0. 5
10 is as shown. If, however, the sign of the coefficient were negative, it
would be necessary to complement the entire floating point word. This example
is a special case of float Ing point since the exponent of the normaljzed number
is 0 and could be represented as -0. The exponent would then be hiased hy 17778
instead of 20008 because of the negative exponent. The 1604, however, recognizes -0 as -0 and biases the exponent by 20008.
16
EXMPLE 4
Convert 0. 04 to floating point
The number is expressed in octal.
Normalize. 004 0.04 x 8 0 = 0.4 x 8 1 = 0.100 x 2
Since the sign of the true exponent is negative, add 17778 (bias) to the true
exponent. Biased exponent = 17778 + (-3) = 17748.
Assemble number in floating point format.
Coefficient = 400 000 000 0008
Biased Exponent = 1774 8
Assembled word = 1774 400 000 000 0008
Since the sign of the coefficient is positive, the floating point representation of
0. 048 is as shown. 1±, however, the sign of the coefficient were negative, it
would be necessary to complement the entire floating point word.
Floating Point to Fixed Point Format
Lf the floating point number is negative, complement the entire floating point
word and record the fact that the quantity is negative. The exponent is now in
a true biased form.
If the biased exponent is equal to or greater than 20008 subtract 20008 to obtain
the true exponent. If less than 20008 subtract 17778 to obtain true exponent.
Separate the coefficient and exponent. If the true exponent is negative the binary
point should be moved to the left the number of bit positions indicated by the
true exponent. If the truc exponent is positive, the binary point shoud be moved
to the right the number of bit positions indicated by the true exponent.
The coefficient has now been converted to fixed binary. The sign of the
coefficient will be negative if the floating point number was complemented in
step one. (The sign bit must be extended if the quantity is placed in a register.)
Represent the fixed binary number in fixed octal notation.
EXAMPLE 1
Convert floating point number 2003 400 000 000 0008 to fixed octal
The floating point number is positive and remains uncomplemented.
The biased exponent > 2000, therefore subtract 20008 from the biased exponent
to obtainthe true exponent of the number. 2003 - 2000 = +3
Coefficient = 400 000 000 000 8 = . 100. Move binary point to the right 3 places.
Coefficient = 100. 02
17
The sgn of the coefficient is positive because the floating point number was
not complemented in step one.
Represent in fixed octal notation. 100.0 x 2 0 = 4.0 x d 0
EXAMPLE 2
Convert floating point number 577 ,1 377 777 777 7
tu fixed octa].
8
The sign of the coefficient is negative, therefore, complement the floating
point number.
Complement = 2003 400 000 000 0008
The biased exponent (in complemented form) > 2000 8 , therefore subtract
20008 from the biased exponent to obtain the true exponent of the number.
2003 - 2000 = +3
Coefficient = 4000 000 000 0008 = 0. 1002
Move binary point to the right 3 places.
Coefficient = 100 • 0 2
The sign of the coefficient will be negative because the floating point number
was originally complemented.
Corivert to fixed octal.
-100 . 0 2 = _ 4 . 0 8
Convert floating point number 1774 400 000 000 000 8 to fixed octal
The floating point number is positive and remains UflComplemented
EXAMPLE 3
The biased exponent <20008, therefore subtract 17778 from the biased
exponent to obtain the true exponent of the number. 17748 - 17778 =
Coefficient = 400 000 000 000 8 = . 100
Move binary point to the left 3 places.
Coefficient = . 000100 2
The sign of the coefficient is positive because the floating point number was
not complemented in step one.
Represent in fixed octal notation.
000100 2 = 04
18
APPENDIX II
FAULTS
Certain fault conditions may occur in the execution of a computer program which may
be sensed by EXF instructions. Thc occurrence of the fault does not Stop Operation
but sets an indicator that can be sensed. A fault is visually indicated on the console.
SHIFT FAULT
Any attempt to shift a register more than 127
10 (177 3 ) places right or left resuits in a
shift fault. If the fault exists, the indicator is set prior to execution of the shift
instruction and the shift fault background light on the console display panel is lighted.
The shifts will be performed regardless of the status of the fault indicator. If an
interrupt has been selected, the main program will he interrupted after executing the
shift instruction. The shift fault may be sensed hy 47 7 00120, 1.
L)IVIDE FAULT
A divide £aut occurs in fixed point divide instructjons (25 and 27) when the divisor is
zero or the required quotient exceeds the 47-bit capacity of the quotient register, Q.
The sign bit of Q is examined at the end of the division phase. If it is equal. to 1, a
divide fault has occurred. If an interrupt has been selected, the main program will be
interrupted after the divide instruction is completed. A divide fault is sensed by a
74 0 00110, 1.
OVERFLOW FAULT
An overflow fault results whcn the capacity of the A register (21) is exceeded. The
fault is detected at the time the Operation causing the overflow takes place.
If an interrupt on arithmetic faults has heen selected, the main program wil]. be
halted before another instruction can be executed.
An overflow may be sensed by a 74 7 00130, 1.
CLOCK OVERFLOW
A ciock overflow resuits if the capacity of the A register is exceeded during an
advance ciock operation. If an interrupt on arithmetic faults has been selected, the
interrupt will occur before an instruction can be executed after the advance ciock
operation. Clock overflow may be sensed by 74 7 00300, 1.
19
EXPONENT (Floating Point Range) FATJLT
The exponent fault occurs during floatirig point instructions when the exponent of the
result, after rounding and normalizing, is
~
2+10 (overflow) or 5 2_10 (underflow).
The exponent fault is sensed by a 74 7 00140, 1.
EVEN AND ODD STORAGE FAULTS
These faults indicate a failure in computer storage and turn on background lights on the
console display. The indicators may be cleared by an internal master clear. i± a
storage fault is produced, maintenance should be notified.
Kei
1
1
1
-1
APPENDIX III
TABLE OF POWERS OF 2
., 0
L
n
2
1
2
4
8
0
1
2
3
1.0
0.5
0.25
0.125
16
32
64
128
4
5
6
7
0.062 5
0.031 25
0.015 625
0.007 812 5
256
512
1 024
2 048
8
9
10
11
0.003 906 25
0.001 953 125
0.000 976 562 5
0.000 488 281 25
4 096
8 192
16 384
32 768
12
13
14
15
0.000 244 140 625
0.000 122 070 312 5
0.000 061 035 156 25
0.000 030 517 578 125
16
17
18
19
0.000
0.000
0.000
0.000
65
131
262
524
536
072
144
288
015
007
003
001
258
629
814
907
789
394
697
348
062
531
265
632
5
25
625
812 5
1 048 576 20 0.000 000 953 674 316 406 25
21
2 097 152
0.000 000 476 837 158 203 125
22
4 194 304
0.000 000 238 418 579 101 562 5
23
8 388 608
0.000 000 119 209 289 550 781 25
1
16 777 216
33 554 432
67 108 864
134 217 728
24
25
26
27
0.000 .000 059 604 644 775 390
0.000 000 029 802 322 387 695
0.000 000 014 901 161 193 847
0,000 000 007 450 580 596 923
000
000
000
000
003
001
000
000
725
862
931
465
625
312 5
656 25
828 125
268 435
536 870
1 073 741
2 147 483
456
912
824
648
28
29
30
31
0.000
0.000
0.000
0.000
290 298 461 914 062 5
645 149 230 957 031 25
322 574 615 478 515 625
661 287 307 739 257 812 5
4 294 967
8 589 934
17 179 869
34 359 738
296
592
184
368
32
33
34
35
0.000 000 000 232 830 643 653 869 628 906 25
0.000 000 000 116415 321 826934 814453 125
0.000 000 000 058 207 660 913 467 407 226 562 5
0.000 000 000 029 103 830 456 733 703 613 281 25
736
472
944
888
0.000 000 000 014 551 915 228 366 851 806 640 625
36
0.000 000 000 007 275 957 614 183 425 903 320 312 5
37
38 0.000 000 000 003 637 978 807 091 712 951 660 156 25
0.000 000 000 001 818 989 403 545 856 475 830 078 125
39
v.
fi
68 719
137 438
274 877
549 755
476
953
906
813
21
1
APPENDIX IV
OCTAL-DECIMAL INTEGE R CONVERSION TABLE
0000
to
0777
(Octal)
0000
to
0511
(DecinoI)
Octol Decimai
10000- 4096
20000- 8192
30000- 12288
40000-16384
50000 - 20480
60000 - 24576
70000 - 28672
0
1
2
3
4
5
6
7
0000
0010
0020
0030
0040
0050
0060
0070
0000
0008
0016
0024
0032
0040
0048
0056
0001
0009
0017
0025
0033
0041
0049
0057
0002
0010
0018
0026
0034
0042
0050
0058
0003
0011
0019
0027
0035
0043
0051
0059
0004
0012
0020
0028
0036
0044
0052
0060
0005
0013
0021
0029
0037
0045
0053
0061
0006
0014
0022
0030
0038
0046
0054
0062
0007
0015
0023
0031
0039
0047
0055
0063
0400 0256 0257 0258 0259 0260 0261 0262 0263
0410 0264 0265 0266 0267 0268 0269 0270 0271
0420'0272 0273 0274 0275 0276 0277 0278 0275
0430
0281 0282 0283 0284 0285 0286 0297
0440 0288 0289 0290 0291 0252 0293 0294 029
0450 10296 0297 0298 0299 0300 0301 0302 0315
0460 0304 0305 0306 0307 0309 0310 0311
0470 0312 0313 0314 0315 0316 0315 0318 0319
0100
0110
0120
0130
0140
0150
0160
0170
0064
0072
0080
0088
0096
0104
0112
0120
0065
0073
0081
0089
0097
0105
0113
0121
0066
0074
0082
0090
0098
0106
0114
0122
0067
0075
0083
0091
0099
0107
0115
0123
0068
0076
0084
0092
0100
0108
0116
0124
0069
0077
0085
0093
0101
0109
0117
0125
0070
0078
0086
0094
0102
0110
0118
0126
0071
0079
0087
0095
0103
0111
0119
0127
0500 0320 0321 0322 0323 0324 0325 0326 0327
0510 10328 0329 0330 0331 0332 0333 0334 0335
0520 j 0336 0337 0338 0339 0340 0341 0342 0343
0530 0344 0345 0346 0347 0348 0349 0350 0351
0540 0352 0353 0354 0355 0356 0357 0358 0359
05500360 0361 0362 0363 0364 0365 0266 0367
0560 0368 0369 0370 0371 0372 0373 0374 0375
0570 0376 0377 0378 0379 0380 0381 0382 0383
0200 0128
0210 0136
0220 0144
0230 0152
0240 0160
0250 10168
0260 0176
0270 0184
0129
0137
0145
0153
0161
0169
0177
0185
0130
0138
0146
0154
0162
0170
0178
0186
0131
0139
0147
0155
0163
0171
0179
0187
0132
0140
0148
0156
0164
0172
0180
0188
0133
0141
0149
0157
0165
0173
0181
0189
0134
0142
0150
0158
0166
0174
0182
0190
0135
0143
0151
0159
0167
0175
0183
0191
0600
0610
0620
0630
0640
0650
0660
0670
0384
0392
0400
0408
0416
0424
0432
0440
0385
0393
0401
0409
0417
0425
0433
0441
0388
0396
0404
0412
0420
0428
0436
0444
0389
0397
0405
0413
0421
0429
0437
0445
0390
0398
0406
0414
0422
0430
0438
0446
0391
0399
0407
0415
0423
0431
0439
0447
0192
0200
0208
0216
0224
0232
0240
0248
0193
0201
0209
0217
0225
0233
0241
0249
0194
0202
0210
0218
0226
0234
0242
0250
0195
0203
0211
0219
0227
0235
0243
0251
0196
0204
0212
0220
0228
0236
0244
0252
0197
0205
0213
0221
0229
0237
0245
0253
0198
0206
0214
0222
0230
0238
0246
0254
0199
0207
0215
0223
0231
0239
0247
0255
0700
0710
0720
0730
0740
0750
0760
0770
0448
0456
0464
0472
0480
0488
0496
0504
0449 0450 0451 0452
0457 0458 0459 0460
0465 0466 0467 0468
0473 0474 0475 0476
0481 0482 0483 0484
0489 0490 0491 0492
0497 0498 0499 0500
0505 0506 0507 0508
0453
0461
0469
0477
0485
0493
0501
0454
0462
0470
0478
0486
0494
0502
0455
0463
0471
0479
0487
0495
0503
0
1
2
3
4
5
6
7
0516
0524
0532
0540
0548
0556
0564
0572
0517
0525
0533
0541
0542
0557
0565
0573
0518
0526
0534
0542
0550
0558
0566
0574
0519
0527
0535
0543
0551
0559
0567
0575
0300
0310
0320
0330
0340
0350
0360
0370
1000
to
0512
to
1777
1023
(Octol) CDecimal)
0
1
2
3
4
5
67
r0280
0386
0394
0402
0410
0418
0426
0434
0442
0387
0395
0403
0411
0419
0427
0435
0443
0509
01fl 1511
0
1
2
3
4
5
6
7
1400
1410
1420
1430
1443
1450
1460
1470
0768
0776
0784
0792
0800
0808
0816
0824
0769
0777
0785
0793
0801
0809
0817
0825
0770
0778
0786
0794
0802
0810
0818
0826
0771
0779
0787
0795
0803
0811
0819
0827
0772
0780
0788
0796
0804
0812
0820
0828
0773
0781
0789
0797
0805
0813
0821
0829
0774
0782
0790
0798
0806
0814
0822
0830
0775
0783
0791
0799
0807
0815
0823
0831
1000
1010
1020
1030
1040
1050
1060
1070
0512
0520
0528
0536
0544
0552
0560
0568
0513
0521
0529
0537
0545
0553
0561
0569
0514
0522
0530
0538
0546
0554
0562
0570
0515
0523
0531
0539
0547
0555
0563
0571
1100
1110
1120
1130
1140
1150
1160
1170
0576
0584
0592
0600
0608
0616
0624
0632
0577
0585
0593
0601
0609
0617
0625
0633
0578
0586
0594
0602
0610
0618
0626
0634
0579
0587
0595
0603
0611
0619
0627
0635
0580
0588
0596
0604
0612
0620
0628
0636
0581
0889
0597
0605
0613
0621
0629
0637
0582
0590
0598
0606
0614
0622
0630
0638
0583
0591
0599
0607
0615
0623
0631
0639
1500
1510
1520
1530
1540
1550
1560
1570
0832
0840
0848
0856
0864
0872
0880
0888
0833
0841
0849
0857
0865
0873
0881
0889
0834
0842
0850
0858
0866
0874
0882
0890
0835
0843
0851
0859
0867
0875
0883
0891
0836
0844
0852
0860
0868
0876
0884
0892
0837
0845
0853
0861
0869
0877
0885
0893
0838
0846
0854
0862
0870
0878
0886
0894
0839
0847
0855
0863
0871
0879
0887
0895
1200
1210
1220
1230
1240
1250
1260
1270
0640
0648
0656
0664
0672
0680
0688
0696
0641
0649
0657
0665
0673
0681
0689
0697
0642
0650
0658
0666
0674
0682
0690
0698
0643
0651
b659
0667
0675
0683
0691
0699
0644
0652
0660
0668
0676
0684
0692
0700
0645
0653
0661
0669
0677
0685
0693
0701
0646
0654
0662
0670
0678
0686
0694
0702
0647
0655
0663
0671
0679
0687
0695
0703
1600
1610
1620
1630
1640
1650
1660
1670
0896
0904
0912
0920
0928
0936
0944
0952
0897
0905
0913
0921
0929
0937
0945
0953
0898
0906
0914
0922
0930
0938
0946
0954
0899
0907
0915
0923
0931
0939
0947
0955
0900
0908
0916
0924
0932
0940
0948
0956
0901
0909
0917
0925
0933
0941
0949
0957
0902
0910
0918
0926
0934
0942
0950
0958
0903
0911
0919
0927
0935
0943
0051
0059
1300
1310
1320
1330
1340
1350
1360
1370
0704
0712
0720
0728
0736
0744
0752
0760
0705
0713
0721
0729
0737
0745
0753
0761
0706
0714
0722
0730
0738
0746
0754
0762
0707
0715
0723
0731
0739
0747
0755
0763
0708
0716
0724
0732
0740
0748
0756
0764
0709
0717
0725
0733
0741
0749
0157
0765
0710
0718
0726
0734
0742
0750
0758
0766
0711
0719
0727
0735
0743
0751
0759
0767
1700 0960 0961 0962
1710 0968 0969 0970
1720 0978 0977 0978
84 0985 0986
L
17
92 0993 0994
00l 1002
00
08 1009 1010
7J 16 1017 1018
0963
0971
0979
0987
0995
1003
1011
0964
0972
0980
0988
0996
1004
1012
lolg 1020
0965
0973
0981
0989
0997
1005
1013
1021
0966
0974
0982
0990
0998
1006
1014
1022
0967
0975
0983
0991
0999
1007,
10151
1023j
22
OCTAL-DECIMAL INTEGER CONVERSION TABLE
r
2
34
4567
2400 1280 1281 1282 1283 1284 1285 1286 1287
2410 1288 1289 1290 1291 1292 1293 1294 1295
2420 1296 1297 1298 1299 1300 1301 1302 1303
[00 1024 1025 1026 1027 1028 1029 1030 1031
2010 1032 1033 1034 1035 1036 1037 1038 1039
20201040 1041 1042 1043 1044 1045 1046 1047
2030 1048 1049 1050 1051 1052 1053 1054 1055
204011056 1057 1058 1059 1060 1061 1062 1063
235011064 1065 1066 1067 1068 1069 1070 1071
20601072 1073 1074 1075 1076 1077 1078 1079
2070 1080 1081 1082 1083 1084 1085 1086 1087
2430
2440
2450
2460
2470
1304
1312
1320
1328
1336
1305
1313
1321
1329
1337
1306
1314
1322
1330
1338
1307
1315
1323
1331
1339
1308
1316
1324
1332
1340
1309
1317
1325
1333
1341
1310
1318
1326
1334
1342
1311
1319
1327
1335
1343
2100
2110
2120
2130
2140
2150
2160
2170
2500
2510
2520
2530
2540
2550
2560
2570
1344
1352
1360
1368
1376
1384
1392
1400
1345
1353
1361
1369
1377
1385
1393
1401
1346
1354
1362
1370
1378
1386
1394
1402
1347
1355
1363
1371
1379
1387
1395
1403
1348
1356
1364
1372
1380
1388
1396
1404
1349
1357
1365
1373
1381
1389
1397
1405
1350
1358
1366
1374
1382
1390
1398
1406
1351
1359
1367
1375
1383
1391
1399
1407
1158 1159
1166 1167
1174 1175
1182 1183
1190 1191
1198 1199
1206 1207
1214 1215
2600
2610
2620
2630
2640
2650
2660
2670
1408
1416
1424
1432
1440
1448
1456
1464
1409
1417
1425
1433
1441
1449
1457
1465
1410
1418
1426
1434
1442
1450
1458
1466
1411
1419
1427
1435
1443
1451
1459
1467
1412
1420
1428
1436
1444
1452
1460
1468
1413
1421
1429
1437
1445
1453
1461
1469
1414
1422
1430
1438
1446
1454
1462
1470
1415
1423
1431
1439
1447
1455
1463
1471
2300 1216 1217 1218 1219 1220 1221 1222 1223
2310 1224 1225 1226 1227 1228 1229 1230 1231
2700
2710
2720
2730
2740
2750
2760
2770
1472
1480
1488
1496
1504
1512
1520
1528
1473
1481
1489
1497
1505
1513
1521
1529
1474
1482
1490
1498
1506
1514
1522
1530
1475
1483
1491
1499
1507
1515
1523
1531
1476
1484
1492
1500
1508
1516
1524
1532
1477
1485
1493
1501
1509
1517
1525
1533
1478
1486
1494
1502
1510
1518
1526
1534
1479
1487
1495
1503
1511
1519
1527
1535
1
2
3
4
5
6
7
1088
1096
1104
1112
1120
1128
1136
1144
1089
1097
1105
1113
1121
1129
1137
1145
1090
1098
1106
1114
1122
1130
1138
1146
1091
1099
1107
1115
1123
1131
1139
1147
1092
1100
1108
1116
1124
1132
1140
1148
1093 1094 1095
1101 1102 1103
1109 1110 1111
1117 1118 1119
1125 1126 1127
1133 1134 1135
1141 1142 1143
1149 1150 1151
12200 1152 1153 1154 1155 1156 1157
22101160 1161 1162 1163 1164 1165
222011168 1169 1170 1171 1172 1173
2230 1176 1177 1178 1179 1180 1181
224011184 1185 1186 1187 1188 1189
22501192 1193 1194 1195 1196 1197
2260 1200 1201 1202 1203 1204 1205
2270 1208 1209 1210 1211 1212 1213
23201232 1233 1234 1235 1236 1237 1238 1239
23301240 1241 1242 1243 1244 1245 1246 1247
1234011248 1249 1250 1251 1252 1253 1254 1255
1
235011256 1257 1258 1259 1260 1261 1262 1263
23601 1264 1265 1266 1267 1268 1269 1270 1271
j1272 1273 1274 1275 1276 1277 1278 1279
~
0
3030 1560 1561 1562 1563 1564 1565 1566 1567
3400 1792 1793 1794 1795 1796 1797 1798 1799
3410800 1801 1802 1803 1804 1805 1806 1807
3420 1808 1809 1810 1811 1812 1813 1814 1815
3430 1816 1817 1818 1819 1820 1821 1822 1823
3040 1568 1569 1570 1571 1572 1573 1574 1575
3050 1576 1577 1578 1579 1580 1581 1582 1582
3060 1584 1585 1586 1587 1588 1589 1590 1591
3070 1592 1593 1594 1595 1596 1597 1598 1599
3440
3450
3460
3470
3100 1600 1601 1602 1603 1604 1605 1606 1607
3110 1608 1609 1610 1611 1612 1613 1614 1615
3500 1856 1857 1858 1859 1860 1861 1862 1863
3510 1864 1865 1866 1867 1868 1869 1870 1871
3520 1872 1873 1874 1875 1876 1877 1878 1879
3000 1536 1537 1538 1539 1540 1541 1542 1542
3010 1544 1545 1546 1547 1548 1549 1550 1551
3020 1552 1553 1554 1555 1556 1557 1558 1559
3120 1616 1617 1618 1l9 1620 1621 1622 1623
3130 1624 1625 1626 1627 1628 1629 1630 1631
3140 1632 1633 1634 1635 1636 1637 1638 1639
3150 1640 1641 1642 1643 1644 1645 1646 1647
3160 1648 1649 1650 1651 1652 1653 1654 1655
3170 1656 1657 1658 1659 1660 1661 1662 1663
3200 1664 1665 1666 1667 1668 1669 1670 1671
3210 1672 1673 1674 1675 1676 1677 1678 1679
3220 1680 1681 1682 1683 1684 1685 1686 1687
3230 1688 1689 1690 1691 1692 1693 1694 1695
3240 1696 1697 1698 1699 1700 1701 1702 1703
3250 1704 1705 1706 1707 1708 1709 1710 1711
3260 1712 1713 1714 1715 1716 1717 1718 1719
3270 1720 1721 1722 1723 1724 1725 1726 1727
3300 17281729 1730 1731 1732 1733 1734 1735
3310 1736 1737 1738 1739 1740 1741 1742 1743
3320 1744 1745 1746 1747 1748 1749 1750 1751
3330 1752 1753 1754 1755 1756 1757 1758 1759
3340 1760 1761 1762 1763 1764 1765 1766 1767
3350 1768 1769 1770 1771 1772 1773 1774 1775
3360 1776 1777 1778 1779 1780 1781 1782 1783
3370,1784 1785 17861787 1788 1789 1790 1791
1824
1832
1840
1848
1825
1833
1841
1849
1826
1834
1842
1850
1827
1835
1843
1851
1828
1836
1844
1852
1829
1837
1845
1853
1830
1838
1846
1854
1831
1839
1847
1855
3530 1880 1881 1882 1883 1884 1885 1886 1887
3540 1888 1889
3550 1896 1897
3560 1904 1905
3570 1912 1913
1890
1898
1906
1914
1894
1902
1910
1918
1895
1903
1911
1919
3600
3610
3620
3630
3640
3650
3660
3670
1920
1928
1936
1944
1952
1960
1968
1976
1921
1929
1937
1945
1953
1961
1969
1977
1922 1923 1924 1925 126
1930 1931 1932 1933 1934
1938 1939 1940 1941 1942
1946 1947 1948 1949 1950
1954 1955 1956 1957 1958
1962 1963 1964 1965 1966
1970 1971 1972 1973 1974
1978 1979 1980 1981 1982
1927
1935
3700
3710
3720
3730
3740
3750
3760
3770
1984
1992
2000
2008
2016
2024
2032
2040
1985
1993
2001
2009
2017
2025
2033
2041
1986
1994
2002
2010
2018
2026
2034
2042
1991
1999
2007
2015
23
1891
1899
1907
1915
1987
1995
2003
2011
2019
2027
2035
2043
1892
1900
1908
1916
1988
1996
2004
2012
2020
2028
2036
2044
1893
1901
1909
1917
1989
1997
2005
2013
2021
2029
2037
2045
1990
1998
2006
2014
2022
2030
2038
2046
1943
1951
1959
1967
1975
1983
2023
2031
2039
2047
2000
1024
80
tO
2777
1535
(Octal) (Decimol)
Octal Decimal
10000- 4096
20000- 8192
30000- 12288
40000-16384
50000 20480
60000- 24576
70000 -28672
-
3000
1 1536
to
to
3777
2047
(Octal) (Decimol)
OCTAL-DECIMAL INTEGER CONVERSION TABLE
2048
4000
tO
10
2559
4777
(Octol) )Deorool)
Octal Decimal
10000- 4096
20000- 8192
30000- 12288
40000- 16384
50000 - 20480
60000 - 24576
70000 - 28672
4000
4010
4020
4030
4040
4050
4060
4070
2048
2056
2064
2072
2080
2088
2096
2104
4100 2112 2113 2114 2115 2116 2117 2118 2119
4110 2120 2121 2122 2123 2124 2125 2126 2127
4120 2128 2129 2130 2131 2132 2133 2134 2135
4130 2136 2137 2138 2139 2140 2141 2142 2143
4140 2144 2145 2146 2147 2148 2149 2150 2151
14150 2152 2153 2154 2155 2156 2157 2158 2159
4160 2160 2161 2162 2163 2164 2165 2166 2167
4170' 2168 2169 2170 2171 2172 2173 2174 2175
2560
10
10
5777
(Octol)
3071
)Deci,00I)
4400
4410
4420
4430
4440
4450
4460
4470
0
1
2304
2312
2320
2328
2336
2344
2352
2360
2305
2313
2321
2329
2337
2345
2353
2361
2
3
4
5
6
7
2306 2307 2308 2309 2310 2311
2314 2315 2316 2317 2318 2319
2322 2323 2324 2325 2326 2327
2330 2331 2332 2333 2334 2335
2338 2339 2340 2341 2342 2342
2346 2347 2348 2349 2350 2351
2354 2355 2356 2357 2358 2350
2362 2363 2364 2365 2366 2367
4500 2368 2369 2370 2371 2372 2373 2374
4510 2376 2377 2378 2379 2380 2381 2382
4520 2384 2385 2386 2387 2388 2389 2390
4530 1 2392 2393 2394 2395 2396 2397 2398
4540:2400 2401 2402 2403 2404 2405 2406
45502408 2409 2410 2411 2412 2413 2414
45602416 2417 2418 2419 2420 2421 2422
4570 2424 2425 2426 2427 2428 2429 2430
2375
2383
2391
2399
2407
2415
2423
2431
4200 2176 2177 2178 2179 2180 2181 2182 2183
4210 2184 2185 2186 2187 2188 2189 2190 2191
4220 2192 2193 2194 2195 2196 2197 2198 2199!
4230 2200 2201 2202 2203 2204 2205 2206 2207
42401 2208 2209 2210 2211 2212 2213 2214 2215
4250 2216 2217 2218 2219 2220 2221 2222 22231
4260! 2224 2225 2226 2227 2228 2229 2230 2231'
4270 1 2232 2233 2234 2235 2236 2237 2238 22391
4600 2432 2433 2434 2435 2436 2437 2438 2439
46102440 2441 2442 2443 444 2445 2446 2447
4620 ! 2448 2449 2450 2451 2452 2453 2454 2455
4630 1 2456 2457 2458 2459 2460 2461 2462 2463
464012464 2465 2466 2467 2468 2469 2470 2471
4
2 2473 2474 2475 2476 2477 2478 2479
466 012480 2481 2482 2483 2484 2485 2486 2487
4670 1 248 8 2489 2490 2491 2492 2493 2494 2495
4300 2240 2241 2242 2243 2244 2245 2246 2247'
4310 2248 2249 2250 2251 2252 2253 2254 2255
4320: 2256 2257 2258 2259 2260 2261 2262 2263!
4330, 2264 2265 2266 2267 2268 2269 2270 2271
4340! 2272 2273 2274 2275 2276 2277 2278 2279
4350 2280 2281 2282 2283 2284 2285 2286 2287 '
4360 2288 2289 2290 2291 2292 2293 2294 2295,
4370! 2296 2297 2298 2299 2300 2301 2302 2303!
4700 2496 2497 2498 2499 2500 2501 2502 2503
1471012504 2505 2506 2507 2508 2509 2510 2511
47202512 2513 2514 2515 2516 2517 2518 2519
4730, 2520 2521 2522 2523 2524 2525 2526 2527
4740 2528 2529 2530 2531 2532 2533 2534 2535
4750 2536 2537 2538 2539 2540 2541 2542 2543
4760 2544 2545 2546 2547 2548 2549 2550 2551
025522553 2554 2555 2556 2557 2558 2559
0
5000
2049 2050 2051 2052 2053 2054 2055
2057 2058 2059 2060 2081 2062 2063
2065 2066 2067 2068 2069 2070 2071
2073 2074 2075 2076 2077 2078 2079
2081 2082 2083 2084 2085 2086 2087
2089 2090 2091 2092 2093 2094 2095
2097 2098 2099 2100 2101 2102 2103
2105 2106 2107 2108 2109 2110 2111
1
2
3
4
5
6
7
5000
5010
5020
5030
5040
5050
5060
5070
2560
2568
2576
2584
2592
2600
2608
2616
2561 2562 2563 2564 2565 2566 2567'
2569 2570 2571 2572 2573 2574 25751
2577 2578 2579 2580 2581 2582 2583
2585 2586 2587 2588 2589 2590 2591:
2593 2594 2595 2596 2597 2598 2599
2601 2602 2603 2604 2605 2606 260 7
2609 2610 2611 2612 2613 2614 26151
2617 2618 2619 2620 2621 2622 2623
5400 2816 2817 2818 2819 2820 2821 2822 2823
5410 2824 2825 2826 2827 2828 2829 2830 2831
5420 2832 2833 2834 2835 2836 2837 2838 2839
5430 2840 2841 2842 2843 2844 2845 2846 2847
5440, 2848 2849 2850 2851 2852 2853 2854 2855
5450 2856 2857 2858 2859 2860 2861 2862 2863
54601 2864 2865 2866 2867 2868 2869 2870 2871
54702872 2873 2874 2875 2876 2877 2878 2879
5100
5110
5120
5130
5140
5150
5160
5170
2624
2632
2640
2648
2656
2664
2672
2680
2625 2626 2627 2628 2629 2630 2631
2633 2634 2635 2636 2637 2638 2639'
2641 2642 2643 2644 2645 2646 264H
2649 2650 2651 2652 2653 2654 26551
2657 2658 2659 2660 2661 2662 26631
2665 2666 2667 2668 2669 2670 26711
2673 2674 2675 2676 2677 2678 2679
2681 2682 2683 2684 2685 2686 2687
5500 '2880 2881 2882 2883 2884 2885 2886 2887
5510 2888 2889 2890 2891 2892 2893 2894 2895
5520 2896 2897 2898 2899 2900 2901 2902 2903
5530 2904 2905 2906 2907 2908 2909 2910 2911
554012912 2913 2914 2915 2916 2917 2918 2919
55502920 2921 2922 2923 2924 2925 2926 2927
5560 2928 2929 2930 2931 2932 2933 2934 2935
557012936 2937 2938 2939 2940 2941 2942 2943
5200
5210
5220
5230
5240
5250
5260
5270
2688
2696
2704
2712
2720
2728
2736
2744
2689 2690 2691 2692 2693 2694 2695!
2697 2698 2699 2700 2701 2702 2703
2705 2706 2707 2708 2709 2710 2711
2713 2714 2715 2716 2717 2718 27191
2721 2722 2723 2724 2725 2726 2727
2729 2730 2731 2732 2733 2734 2735!
2737 2738 2739 2740 2741 2742 27431
2745 2746 2747 2748 2749 2750 27511
5600
5610
5620
5630
5640
5650
5660
5670
2944 2945 2946 2947 2948 2949 2950 2951
2952 2953 2954 2955 2956 2957 2958 2959
2960 2961 2962 2963 2964 2965 2966 2967
2968 2969 2970 2971 2972 2973 2974 2975
2976 2977 2978 2979 2980 2981 2982 2983
2984 2985 2986 2987 2988 2989 2990 2991
2992 2993 2994 2995 2996 2997 2998 2999
3000 3001 3002 3003 3004 3005 3006 3007
5300
5310
5320
5330
5340
5350
5360
5370
2752
2760
2768
2776
2784
2792
2800
2808
2753 2754 2755 2756 2757 2758 2759
2761 2762 2763 2764 2765 2766 2767 1
2769 2770 2771 2772 2773 2774 2775
2777 2778 2779 2780 2781 2782 2783
2785 2786 2787 2788 2789 2790 2791
2793 2794 2795 2796 2797 2798 2 7 9 9 1
2801 2802 2803 2804 2805 2806 2807
2809 2810 2811 2812 2813 2814 2815
5700
5710
5720
5730
5740
5750
5760
5770
3008 3009 3010 3011 3012 3013 3014 3015
3016 3017 3018 3019 3020 3021 3022 3023
3024 3025 3026 3027 3028 3029 3030 3031
3032 3033 3034 3035 3036 3037 3038 3039
3040 3041 3042 3043 3044 3045 3046 3047
3048 3049 3050 3051 3052 3053 3054 3055
3056 3057 3058 3059 3060 3061 3062 3063
3064 3065 3066 3067 3068 3069 3070 301
1
1
b
.
OCTAL-DECIMAL INTEGER CONVERSION TABLE
0
1
2
3
1
4
6000 13072 3073 3074 3075 3076 3077 3078 30791
6010 3080 3081 3082 3083 3084 3085 3086 3087!
6020 3088 3089 3090 3091 3052 3093 3094 30051
60303096 3097 3098 3099 3100 3101 3102 303
604013104 3105 3106 3107 3108 3109 3110 31111
60503112 3113 3114 3115 3116 3117 3118 3119 1
606013120 3121 3122 3123 3124 3125 3126 3127
60703128 3129 3130 3131 2132 3133 3134 3135'
1
2
3
-
5
4
7]
6
6 4001 3328 3329 3330 3331 3332 3333 3334
'6410' 3336 3337 3338 3339 3340 3341 3312
20 3344 3345 3346 3347 3348 3349 3350
6430,: 3352 3353 3354 3355 3356 3357 3358
1 6 4401 3300 3361 3362 3363 3364 3365 3366
16450 3368 3309 3370 3371 3372 3373 3374
6460 3376 3377 3378 3370 3380 3381 3382
0470 1 3384 3385 3386 3387 3388 3389 3390
1 84
6100 3136 3137 3138 3139 3140 3111 3142 3143'
6110 3144 3145 3146 3147 3148 3149 3153 3151
6120 3152 3153 3154 3155 3156 3157 3158 3159
6130 3160 3161 3162 3163 3164 3165 3166 31671
6140 3168 3169 3170 3171 3172 3173 3174 3175!
6150 3176 3177 3178 3179 3180 3181 3182 3l83
6160 13184 3185 3186 3187 3188 3189 3190 31911
617013192 3193 3194 3195 3196 3197 3198 31991
333
3343
3351
3359
33671
3383,
3391
65001 3392 3393 3394 3395 3396 3397 3398 3399!
lO ' 3400 3401 3402 3403 3404 3405 3406 3407
20 3408 3409 3410 3411 3412 3413 3414 3415
30 3416 3417 3418 3419 3420 3421 3422 3423
6540 3424 3425 3426 3427 3428 3429 3430 3431
6550 3432 3433 3434 3435 3436 3437 3438 34391
6560, 3440 3441 3442 3443 3444 3445 34463447
6570 3448 3449 3450 3451 3452 3453 3454 3455
1
6200 3200 3201 3202 3203 3204 3205 3206 3207
16210 3208 3209 3210 3211 3212 3213 3214 3215,
16220 '3216 3217 3218 3219 3220 3221 3222 3223,
16230 !3224 3225 3226 3227 3228 3229 3230 3231!
6240 3232 3233 3234 3235 3236 3237 3238 3239
6250 13240 3241 3242 3243 3244 3245 3246 32471
6260 3248 3249 3250 3251 3252 3253 3254 3255
6270 3256 3257 3258 3259 3260 3261 3262 3263
6600 3456 3457 3458 3459 3460 3461 3462 3463
6610 3464 3465 3466 3467 3468 3469 3470 3471
6620' 3472 3473 3474 3475 3476 3477 3478 3479
‚6030 3480 3481 3482 3483 3484 3485 3480 3487
‚'6640' 3488 3489 3490 3491 3492 3493 3494 3495
66 5 0 3496 3497 3498 3499 3500 3501 3502 3503
1 6660 3504 3505 3506 3507 3508 3509 3510 3511
6670 3512 3513 3514 3515 3516 3517 3518 3519
6300 3264 3265 3266 3267 3268 3269 3270 3271
6310 3272 3273 3274 3275 3276 3277 3278 3279
6320 13280 3281 3282 3283 3284 3285 3286 3287
6330 '3288 3289 3290 3291 3292 3293 3294 3295'
6340 3296 3297 3298 3299 3300 3301 3302 3303
6350 '3304 3305 3306 3307 3308 3309 3310 3311
63603312 3313 3314 3315 3316 3317 3318 3319
[37913320 33213322 3323 3324 3325 3326 3327
6700 3520 3521 3522 3523 3524 3525 3526 3527
6710 j 3528 3529 3530 3531 3532 3533 3534 3535
6720 3536 3537 2538 3539 3540 3541 3542 3543
6730 3544 3545 3546 3547 3548 3549 3550 3551
6740 3552 3553 3554 3555 3556 3557 3558 3559
6750 3560 3561 3502 3563 3564 3565 3566 3567
0760 3568 3569 3570 3571 3572 3573 3574 3575
6770, 3576 3577 3578 3579 358)) 3581 3582 3 5 831
0
13
0
1
2
4
5
6
3587
3595
3603
3611
3619
3627
3635
3643
3588
3596
3604
3612
3620
3628
3636
3644
3589
3597
3605
3613
3621
3629
3637
3645
3590
3598
3606
3614
3622
3630
3638
3646
7
0
1
3840 3841
2
3
4
5
6
7400
7410
7420
7430
7440
7450
7460
7470
3848
3856
3864
3872
3880
3888
3896
7100 3648 3649 3650 3651 3652 3653 3654 3655
7110 3656 3657 3658 3659 3660 3661 3662 3663
7120 3664 3665 3666 3667 3668 3669 3670 3671
7130 3672 3673 3674 3675 3676 3677 3678 3679
7140 3680 3681 3682 3683 3684 3685 3686 3687
7150 3688 3689 3690 3691 3692 3693 3694 3695
7160 3696 3697 3698 3699 3700 3701 3702 3703
7170 3704 3705 3706 3707 3708 3709 3710 3711
7500
7510
7520
7530
7540
7550
7560
7570
13904 3905 3906 3907 3908
3912 3913 3814 3915 3916
3920 3921 3922 3923 3924
3928 3929 3930 3931 3932
3636 3937 3938 3939 3940
3944 3945 3946 3947 3948
3952 3953 3954 3955 3556
3960 3961 3962 3963 3964
7200 3712 3713 3714 3715 3716 3717 3718 3719
7210 3720 3721 3722 3723 3724 3725 3726 3727
7220 3728 3729 3730 3731 3732 3733 3734 3735
7230 3736 3737 3738 3739 3740 3741 3742 3743
7240 3744 3745 3746 3747 3748 3749 3750 3751
7250 3752 3753 3754 3755 3756 3757 3753 3759
7260 3760 3761 3762 3763 3764 3765 3766 3767
7270 3768 3769 3770 3771 3772 3773 3774 3775
7600
7610
7620
7630
7640
7650
7660
7670
3968
3976
3984
3992
4000
4008
4016
4024
7300 3776 3777 3778 3779 3780 3781 3782 37831
7310 3784 3785 3786 3787 3788 3789 3790 3791,
7320 3792 3793 3794 3795 3796 3797 3798 3799
7330 3800 3801 3802 3803 3804 3805 3806 3807
7340 3808 3809 3810 3811 3812 3813 3814 3815
7350 3816 3817 3818 3819 3820 3821 3822 3823
7360 3824 3825 3826 3827 3828 3829 3830 3831
7370 3832 3833 3834 3835 3836 3837 3838 3839
7700 4
4033 4034 41)35 4036 4037 4038 4039
7710 4040 4041 4042 4043 4044 4045 4046 4047
3849
3857
3865
3873
3881
3889
3897
3969
3977
3985
3993
4001
4009
4017
4025
3842 3843 3844 3845 3846 3847
3850 3851 3852 3853 3854 3855
3858 3859 3860 3861 3862 3863
3866 3867 3868 3869 3870 3871
3874 3875 3876 3877 3878 3879
3882 3883 3884 3885 3886 3887
3890 3891 3892 3893 3894 3895
3898 3899 3900 3901 3902 3903
3970
3978
3986
3994
4002
4010
4018
4026
3971
3979
3987
3995
4003
4011
4019
4027
3909
3917
3925
3933
3941
3949
3957
3965
3910 3911
3918 3919
3926 3927
3934 3935
3942 3943
3850 3951
3958 3959
3966 3967
3972 3973 3974 3975
3980 3881 3982 3983
3988 3989 3990 3991
3996 3997 3998 3999
4004 4005 4006 4007
4012 4013 4014 4015
4020 4021 4022 4023
4028 4029 4030 4031
7720 4048 404)) 405)) 4051 4052 4053 4054 4055
7730 4056 4057 4058 4059 4060 4061 4062 4063
7740 4004 4065 4066 4067 4068 4069 407)) 4071
7750 4072 4073 4074 4075 4076 4077 4078 4079
7760 4080 4081 4082 4083 4084 4085 4086 4087
7770 4088 4089 4080 4081 4092 4093 4094 4095
25
3072
6777
3583
)Odol)
)0ecr,oI)
Octal Decimal
10000- 4096
20000- 8192
30000- 12288
40000- 16384
50000 - 20480
60000 - 24576
70000 - 28672
7
3591
3599
3607
3615
3623
3631
3639
3647
7000
7010
7020
7030
7040
7050
7060
7070
3584 3585 3586
3592 3593 3594
3600 3601 3602
3608 3609 3610
3616 3617 3618
3624 3625 3626
3632 3633 3634
3640 3641 3642
3
~
6000
7000
3584
7777
)OioI)
0incI)
4095
)
APPENDIX V
OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
.000
.001
.002
• 003
.004
.005
.006
.007
.000006
.001953
.003906
.005859
.007812
.009765
.011718
.013671
.100
.101
.102
.103
.104
.105
.106
.107
.125000
.126953
.128906
. 130859
.132812
.134765
.136718
.138671
.200
.201
.202
.203
.204
.205
.206
.207
.250000
.251053
.253906
.255859
.257812
.259765
.261718
.263671
.300
.301
.302
. 303
.304
.305
306
.307
375 000
.376953
.378906
380859
.382812
.384765
.386718
.388671
.010
.011
.012
.013
.014
.015
.016
.017
.015625
.017578
.019531
.021484
.023437
.025390
.027343
.029296
.110
.111
.112
.113
.114
.115
.116
.117
.140625
.142578
.144531
.146484
.148437
.150390
.152343
.154296
.210
.211
.212
.213
.214
.215
.216
.217
.265625
.267578
.269531
.271484
.273437
.275390
.277343
.279296
.310
.311
.312
.313
.314
.315
.316
.317
.390625
.392578
•394531
.396484
.398437
.400390
.402343
.404296
.020
.021
.022
.023
.024
.025
.026
.027
.031250
.033203
.035156
.037109
.039062
.041015
.042968
.044921
.120
.121
.122
.123
.124
.125
.126
.127
.156250
.158203
.160156
.162109
.164062
.166015
.167968
.169921
.220
.221
.222
.223
.224
.225
.226
.227
.281250
.283203
.285156
.287109
.289062
.291015
.292968
.294921
.320
.321
.322
.323
.324
.25
.326
.327
.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921
.030
.031
.032
.033
.034
.035
.036
.037
.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546
.130
.131
.132
.133
.134
.135
.136
.137
.171875
.173828
.175781
.177734
.179687
.181640
.183593
.185546
.296875
.298828
.300781
.302734
.304687
.306640
.308593
.310546
.330
.331
.332
.333
.334
.335
.336
.337
.040
.041
.042
.043
.044
.045
.046
.047
.140
.141
.142
.143
.144
.145
.146
.147
.187500
.189453
.191406
.193359
.195312
.197265
.199218
.201171
.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171
.340
.341
.342
• 343
.344
.345
.346
.347
.421875
.423828
.426781
.427734
.429687
.431640
.433593
.435546
• 437500
• 439453
441406
• 443359
• 445312
.447265
449218
451171
.00
.051
.052
.053
.054
.055
.056
.057
.062500
.064453
.066406
.068359
.070312
.072265
.074218
.076171
.078125
.080078
.082031
.083984
.085937
.087890
.089843
.091796
.230
.231
.232
.233
.234
.235
.236
.237
.240
.241
.242
.243
.244
.245
.246
.247
.150
.151
.152
.153
.154
.155
.156
.157
.203125
.209078
.207031
.208984
.210937
.212890
.214843
.216796
.250
.251
.252
.253
.254
.255
.256
.257
.328125
.330078
.332031
.333984
.335937
.337890
.339843
.341796
.350
.351
.352
353
.354
.355
.356
.357
.060
.061
.062
.063
.064
.065
.066
.067
.093750
.095703
.097656
.099609
.101562
.103515
.105468
.107421
.160
.161
.162
.163
.164
.165
.166
.167
.218750
.220703
.222656
.224609
.226562
.228515
.230468
.232421
.260
.281
.262
.26.3
.264
.265
.266
.267
.343750
.345703
.347656
.349609
.351562
.353515
.355468
.357421
.360
.361
.362
.363
.364
.365
.366
.367
.468750
470703
.472656
474609
476562
.478515
.480468
.482421
.070
.071
.072
.073
.074
.075
.076
.077
.109375
.111328
.113281
.115234
.117187
.119140
.121093
• 123046
.170
.171
.172
.173
.174
.175
.176
.177
.234375
.236328
.238281
.240234
.242187
.244140
.246093
.248046
.270
.271
.272
.273
.274
.275
.276
.277
.359375
.361328
.363281
.365234
.367187
.369140
.371093
.373046
.370
.371
.372
.373
.374
.375
.376
.377
.484375
.486328
.488281
.490234
.492187
• 494140
.496093
.498046
i
1
1
26
OCTAL.DEC.
453125
455078
.457031
458984
.460937
.462890
• 464843
.466796
•
•
1
)
OCTAL-DECIMAL
)
;
F
.000244
.000200
.000488
.000300
.000732
.000101
.000247
.000201
.000492
.000301
.000736
.000000
.000000
.000001
.000003
DEC.
.000007
.000102
.000251
.000202
.000495
.000302
.000740
.000003
.000011
.000103
.000255
.000203
.000499
.000303
.000743
.000004
.000015
.000104
000259
.000204
.000503
.000304
.000747
.000005
.000019
.000105
.000263
.000205
.000507
.000305
.000751
.000006
.000022
.000106
.000267
.000206
.000511
.000306
.000755
.000007
.000028
.000107
.000270
.000207
.000514
.000307
.000759
.000010
.000030
.000110
.000274
.000210
.000518
.000310
.000762
.000011
.000034
.000111
.000278
.000211
.000522
.000311
.000766
.000012
.000038
.000112
.000282
.000212
.000526
.000312
.000770
.000013
.000041
.000113
.000286
.000213
.000530
.000313
.000774
.000014
.000045
.000114
.000289
.000214
.000534
.000314
.000778
.000015
.000049
.000115
.000293
.000215
.000537
.000315
.000782
.000006
.000053
.000118
.000297
.000216
.000541
.000316
.000785
.000017
.000057
.000117
.000301
.000217
.000545
.000317
.000789
.000020
.000065
.000120
.000305
.000220
.000549
.000320
.000793
.000021
.000064
»000121
.000308
.000221
.000553
.000321
.000797
.000022
.000068
.000122
.000312
.000222
.000556
.000322
.000801
.000023
.000072
.000123
.000316
.000223
.000560
.000323
.000805
.000024
.000076
.000124
.000320
.000224
.000564
.000324
.000808
.000025
.000080
.000125
.000324
.000225
.000568
.000325
.000812
.000020
.000083
.000126
.000328
.000226
.000572
.000326
.000816
.000027
.000087
.000127
.000331
.000227
.000576
.000327
.000820
.000091
.000130
.000335
.000230
.000579
.000330
.000823
.000031
.000095
.000131
.000339
.000231
.000583
.000331
.000827
.000032
.000099
.000132
.000343
.000232
.000587
.000332
.000831
.000033
.000102
.000133
.000347
.000233
.000591
.000333
.000835
.000034
.000106
.000134
.000350
.000234
.000595
.000334
.000839
.000035
.000110
.000135
.000354
.000235
.000598
.000335
.000843
.000036
.000114
.000136
.000358
.000236
.000602
.000336
.000846
.000037
.000118
.000137
.000362
.000237
.000606
.000337
.000850
.000122
.000140
.000366
.000240
.000610
.000340
.000854
.000125
.000141
.000370
.000241
.000614
.000341
.000858
.000129
.000142
.000373
.000242
.000617
.000342
.000862
.000043
.000133
.000143
.000377
.000243
.000021
.000343
.000865
.000044
.000137
.000144
.000381
.000244
.000625
.000344
.000869
.000045
.000141
.000145
.000385
.000245
.000629
.000345
.000873
.000046
.000144
.000146
.000389
.000246
.000633
.000346
.000877
.000047
.000148
.000147
.000392
.000247
.000637
.000347
.000881
.000050
.000152
.000150
.000396
.000250
.000640
.000350
.000885
.000051
.000156
.000151
.000400
.000251
.000644
.000351
.000888
.000892
.000052
.000160
.000152
.000404
.000252
.000648
.000352
.000053
.000164
.000153
.000408
.000253
.000652
.000353
.000896
.000054
.000167
.000154
.000411
.000254
.000656
.000354
.000900
.000055
.000171
.000155
.000415
.000255
.000659
.000355
.000904
000056
.000175
.000156
.000419
.000256
.000663
.000356
.000907
.000057
.000179
.000157
.000423
.000257
.000607
.000357
.000911
.000000
.000183
.000160
.000427
.000260
.000671
.000300
.000915
.000061
.000180
.000161
.000431
.000281
.900675
.000361
.000919
.000062
.000190
.000162
.000434
.000202
.000679
.000362
.009923
.000063
.000194
.000163
.000438
.000263
.000082
.000363
.000926
.000064
.000198
.000164
.000442
.000264
.000686
.000364
.000930
.000005
.600202
.000165
.000446
.000265
.000690
.000305
.000934
.000066
.000205
.000166
.000450
.000266
.000694
.000366
.000938
.000067
.000209
.000167
.000453
.000207
.000698
.000387
.000942
.000070
.000213
.000170
.000457
.000270
.000701
.000370
.000946
.000071
.000217
.000171
.000481
.000271
.000705
.000371
.000949
.000072
.000221
.000172
.000465
.000272
.000709
.000372
.000953
.000073
.000225
.000173
.000469
.000273
.060713
.000373
.000957
000074
.000228
.000174
.000473
.000274
.000717
.006374
.000961
:000075
.000232
.000175
.006476
.000275
.000720
.000375
.000965
000076
.000236
.000176
.000480
.000276
.000724
.000376
.000968
000077
.000240
.000177
.000484
.000277
.000728
.000377
.000972
27
•1
OCTAL
.000002
.000042
/
.000100
OCTAL
.000041
/
DEC.
TABLE
OCTAL
DEC.
.000040
/
CONVERSION
DEC.
OCTAL
.000030
/
FRACTION
OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL
DEC.
OCTAL
DEC.
.001220
.001224
.001228
.001232
.001235
.001239
.001243
.001247
.000600
.000601
.000602
.000603
.000604
.000605
.000606
.000607
.001464
.001468
.001472
.001476
.001480
.001483
.001487
.001491
.000700
.000701
.000702
.000703
.000704
.000705
.000706
.000707
001708
.001712
.001716
.001720
.001724
.001728
.001731
.001735
.000510
.000511
.000512
.000513
.000514
.000515
.000516
.000517
.001251
.001255
.001258
.001262
.001266
.001270
.001274
.001277
.000810
.000651
.000612
.000613
.000614
.000615
.000616
.000617
.001495
.001499
.001502
.001506
.001510
.001514
.001518
.001522
.000710
.000711
.000712
.000713
.000714
.000715
.000716
.000717
.001739
.001743
.001747
.001750
.001754
.001758
.001762
.001766
.001037
.001041
.001045
.001049
.001052
.001058
.001060
.001064
.000520
.000521
.000522
.000523
.000524
.000525
.000526
.000527
.001281
.001285
.001280
.001293
.001296
.001300
.001304
.001308
.000620
.000621
.000622
.000623
.000624
.000625
.000626
.000627
.001525
.001529
.001533
.001537
.001541
.001544
.001548
.001552
.000720
.000721
.000722
.000723
.000724
.000725
.000726
.000727
.001770
.001773
.001777
.001781
.001785
.001789
.001792
.001796
.000430
.000431
.000432
.000433
.000434
.000435
.000436
.000437
.001068
.001071
.001075
.001079
.001083
.001087
.001091
.001094
.000530
.008531
.000532
.000533
.000534
.000535
.000536
.000537
.001312
.001316
.001310
.001323
.001327
.001331
.001335
.001338
.000630
.000631
.000632
.000633
.000534
.000635
.000636
.000637
.001556
.001560
.001564
.001567
.001571
.001575
.001579
.001583
.000730
.000731
.000732
.000733
.000734
.000735
.000736
.000737
.001800
.001804
.001808
.001811
.001815
.001819
.001823
.001827
.000440
.000441
.000442
.000443
.000444
.000445
.000446
.000447
.00109
.001102
.001106
.001110
.001113
.001117
.001121
.001125
.000540
.000541
.000542
.000543
.000544
.000545
.000546
.000547
.001342
.001346
.001350
.001354
.001358
.001301
.001365
.001369
.000640
.000541
.000642
.000643
.000644
.000545
.000646
.000647
.001586
.001590
.001594
.001598
.001602
.001605
.001609
.001613
.000740
.000741
.000742
.000743
.000744
.000745
.000746
.000747
.001831
.001834
.001838
.001842
.001846
.001850
.001853
.001857
.000450
.000451
.000452
.000453
.000454
.000455
.000456
.000457
.001129
.001132
.001136
.001140
.001144
.001148
.001152
.001155
.000550
.000551
.000552
.000553
.000554
.000555
.000556
.000557
.001373
.001377
.001380
.000050
.000651
.000652
.001384
.001388
.001392
.001396
.001399
.000653
.000654
.000555
.000656
.000657
.001617
.001621
.001625
.001628
.001632
.001636
.001640
.001644
.000750
.000751
.000752
.000753
.000754
‚000755
.000756
.000757
.001861
.001865
.001869
.001873
.001816
.001880
.001884
.001888
.000400
.000401
‚000462
.000463
.000464
‚001150
.001163
.001167
.001171
.001174
.001178
.001182
.001186
.000560
‚000561
.000562
.000563
.000564
.000565
.000560
.000660
.000661
.000662
.000663
.000064
.000665
.000666
‚001647
.001651
.001655
.001659
.001663
.001667
.001670
.001674
.000760
.000701
.000762
.000763
.000764
.000765
.000766
.001892
.001895
.001899
.001903
.001907
.000561
‚001403
.001407
.001411
.001415
.001419
.001422
.001426
.001430
.000767
.001918
.001190
.001194
.001197
.001201
.001205
.001209
.001213
.001216
.000570
.000571
.000572
.000573
.000574
.000575
.000576
.000577
.001434
‚001438
‚001441
.001445
.001449
.001453
.001451
.001461
.000670
.000671
.000672
.000673
.001678
.001682
.001686
.001689
‚001693
.001697
‚000770
Oe,9771
‚000772
.001922
001926
.001930
.000773
.000774
.000775
.000716
.001934
.001937
.001941
OCTAL
DEC.
(XTAL
DEC.
.000400
.000401
.000402
.000403
.000404
.000405
.000405
.000407
.000976
.000980
.000584
.000988
.000991
.000995
.000999
.001003
.000500
.000501
.000502
.000503
.000504
.000505
.000508
.000507
.000410
.000411
.000412
.000413
.000414
.000415
.000416
.000417
.001007
.001010
.001014
.001018
.001022
.001026
.001029
.001033
.000420
.000421
.000422
.000423
.000424
.000425
.000426
.000427
.000465
.000468
.000467
.000470
.000471
.000172
.000473
.000474
.000475
.000476
.000477
[
.000607
.000674
.000675
‚000676
.000677
28
‚001701
.001705
.000777
.001911
.001914
‚001945
.001949
APPENDIX VI
EXF and Character Codes
1604-A EXF CODES
SELECT INTERNAL
74 0
000co
Allow Interrupt on Channel C inactive
Disallow Interrupt on Channel C inactive
000ci
01000
Start Real-Time Ciock
02000
Stop Real-Time Clock
00070
Clear Arithmetjc Faults and Ciock Overflow
c0000
Clear All Channel C Selections
C=1-6
SELECT INTERRUPTS
74 0
74 0
•
00100
Allow Interrupt on Internal (Arithmetic) Faults or
ClockOverflow
00101
Disallow Interrupt on Internal (Arithmetic) Faults or
Ciock Overflow
03C00
Allow Interrupt on Channel C
03C01
Disallow (Mask) Interrupt on Channel C
C
-
74 0
=
1-6
Channel 1-6
C=0
Channel 7 Output
C=7
Channel 7 Input
04000
Allow Selected External Interrupts
04001
Disallow (Mask) All External Interrupts
SENSE INTERNAL
74 7
00000
Exit on Channel C Active
000C1
Exit on Channel C Inactive
C=1-6
001A0
Exit on Arithmetic Fault A
001A1
Exit on No Arithmetic Fault A
A = 1: Divide
2
:
Shift
3
:
Overflow
4: Exponent Overflow
5
:
Exponent TJnderflow
29
1
1
74 7
00000
Exit an Channel C Interrupt
74 7
0c001
Exit an No Channel C Interrupt
C
1-6
74 7
001T0
Exit on Channel T Interrupt
74 7
001T1
Exit on No Channel T Interrupt
T = 6 = Channel 7 - (Output)
T = 7 = Channel 7 - (Input)
74 7
00200
Exit if Next Main Program Instruction is Upper
74 7
00201
Exit if Next Main Program Instruction is Lower
74 7
00300
Exit an Ciock Overflow
74 7
00301
Exjt an No Ciock Overflaw
CONSOLE EQUIPMENT
(CHANNEL FAIR 1 and 2)
SELECT
INPUT
74 0 11140
100
Select Typewriter for Input, and Interrupt an Carriage Return
Select Typewriter for Input, and Na Interrupt an C. R.
200 Select Paper Tape Reader, and Na Interrupt an End af Tape
210
Select Paper Tape Reader and Set End af Tape Indicatar
220
Select Paper Tape Reader, and Interrupt an End af Tape
OUTPUT 74 0 21100 Select Typewriter for Output, Assembly Made
110
Select Typewriter far Output, Character Mode
200 Select Faper Tape Punch, Assembly Mode
210 Select Paper Tape Punch, Character Mode
240 Turn Paper Tape Punch Motor 0ff
SENSE
INPUT
74 7 11200
Exit an Paper Tape Reader, End of Tape
201 Exit an Paper Tape Reader, Na End af Tape
210 Exit an Paper Tape Reader in Assembly Mode
211 Exit on Paper Tape Reader in Character Mode
140 Exit an Typewriter in Lawer Case
141
Exit an Typewriter in Upper Case
100 Exit an Carriage Return or Tab from Typewriter
101 Exit on Na Carriage Return ar Tab from Typewriter
lt
L
1
OUTPUT
74 7 21200
201
L
Exit on Paper Tape Punch Out of Tape
Exit on Paper Tape Punch Not Out of Tap
1607 EXF CODES
(CHANNEL C, CABINET 2)*
SELECT
INPUT
74 0
C20N1
0N2
Select Read Tape N, Coded Mode
001
Read Selected Tape, Binary Mode
002
Read Selected Tape, Coded Mode
004
Interrupt When Selected Tape Ready
005
006
007
OUTPUT
74 0
Select Read Tape N, Binary Mode
C20N1
Rewind Selected Tape
Backspace Selected Tape
Rewind Selected Tape with Interlock
Select Write Tape N, Binary Mode
0N2
Select Write Tape N, Coded Mode
001
Write Selected Tape, Binary Mode
002
Write Selected Tape, Coded Mode
003
Write End of File Mark on Selected Tape
004
005
Interrupt When Selected Tape Ready
Rewind Selected Tape
006
Backspace Selected Tape
007
Rewind Selected Tape with Interlock
SENSE
INPUT
74 7
C2000
Exit on Ready to Read
001
Exit on Not Ready to Read
002
Exit on Read Parity Error
003
Exit on No Read Parity Error
004
Exit on Read Length Error
005
Exit on No Read Length Error
006
Exit on End of File Mark
007
Exit on No End of File Mark
* The equipment designator
(fourth octal digit from the right) in 1607 EXF codes may
be either 2 or 3. A switch in the rear of the 1607 cabinet determjnes which number
will be recognized as the designator for that cabinet.
31
OUTPUT
74 7 02000
Exit on Ready to Write
001
Exit on Not Ready to Write
002
Exit on Write Reply Parity Error
003
Exit on No Write Reply Parity Error
004
Exit on Write Reply Length Error
005
Exit on No Write Reply Length Error
006
Exit on End of Tape Marker
007
Exit on No End of Tape Marker
1608 EXF CODES
(CHANNEL 0)
C = 1-6
SELECT
INPUT
OUTPUT
74 0 C77N1
Select Read Tape N, Binary Mode
7N2
Select Read Tape N, Coded Mode
001
Read Selected Tape, Binary Mode
002
Read Selected Tape, Coded Mode
004
Interrupt When Selected Tape Ready
005
Rewind Selected Tape
006
Backspace Selected Tape
007
Rewind Selected Tape with Interlock
101
Turn 0ff
102
Set Low Density on Read Unit
103
Set High Density on Read Unit
104
Search File Mark Forward on Read Unit
105
Search File Mark Backward on Read Unit
106
Remove Interrupt Selection on Read Unit
74 0 C77N1
Tape Indicator" on Read Unit
Select Write Tape N, Binary Mode
7N2
Select Write Tape N, Coded Mode
001
Write Selected Tape, Binary Mode
002
Write Selected Tape, Coded Mode
003
Write End of File Mark on Selected Tape
32
It-
OUTPUT
1
J
[1
74 0 C7004
Interrupt When Selected Tape Ready
005
Rewind Selected Tape
006
Backspace Selected Tape
007
Rewind Selected Tape with Interlock
101
Turn 0ff
102
Set Low Density on Write Unit
103
Set High Density on Write Unit
104
Skip Bad Spot on Selected Write Unit
106
Remove Interrupt on Write Unit
' t Tape
Indicator" on Write Unit
SENSE
INPUT
•
1
•
4•
1
OUTPTJT
74 7 C7000
Exit on Ready to Read
001
Exit on Not Ready to Read
002
Exit on Read Parity Error
003
Exit on No Read Parity Error
004
Exit on Read Length Error
005
Exit on No Read Length Error
006
Exit on End of File Mark
007
Exit on No End of File Mark
106
Exit When Read Unit is Rewinding or at Load Point
107
Exit When Read Unit is Not Rewinding or is at Load Pojnt
74 7 C7000
Exit on Ready to Write
001
Exit on Not Ready to Write
002
Exit on Write Reply Parity Error
003
Exit on No Write Reply Parity Error
004
Exit on Write Reply Length Error
005
Exjt on No Write Reply Length Error
006
Exit on End of Tape Marker
007
Exit on No End of Tape Marker
106
Exit when Write Unit is Rewinding or at Load Point
107
Exit when Write Unit is Not Rewinding or is at Load Point
33
1610 EXF CODES
(CHANNEL C)
C = 1-6
SE LE C T
INPUT
OUTPUT
74 0 C4001
Select Primary Read Station
002
Seleet Secondary Read Station
003
Select Primary and Secondary Read Stations
005
Select Primary Read Station and Interrupt
006
Select Secondary Read Station and Interrupt
007
Seleet Primary and Secondary Read Stations and Interrupt
74 0 C4001
Select Printer
002
Select Punch
005
Select Printer and Interrupt
006
Select Punch and Interrupt
SENSE
INPUT
OUTPUT
74 7 C4002
Exit on Reader Ready
003
Exil on Reader Not Ready
004
Exit on 1604 Selected
005
Exit on 1604 Not Selected
74 7 C4002
Exit on Printer Ready
003
Exit on Printer Not Ready
004
Exit on Punch Ready
005
Exil on Punch Not Ready
010
Exit on 1604 Selected
011
Exit on 1604 Not Selected
34
4
-
1612 EXF CODES
(CHANNEL C)
C = 1-6
•1
SELECT
OUTPUT
(ONLY)
74 0
C6000
Select Printer
001
Single Space the Printer
002
Double Space the Printer
003
Select Format Channel 7
004
Select Format Channel 8
010
Clear Monitor Channels 1 - 6
01N
Select Monitor Channel N : N
1 - 6
SE NSE
OUTPUT
(ONLY)
74 7
C6000
001
11
Exit on Printer R.eady
Exit on Printer Not Ready
1615 FUNCTION CODES
(CHANNEL C, CABINET 2)*
OUTPUT
74 0
1
C20N1
Select Tape N to Write Binary
-
8
8
20N2
Select Tape N to Write Coded
2001
Prepare Selected Tape to Write Binary
2002
Prepare Selected Tape to Write Coded
2003
Write End-of-File Mark on Selected Tape
2004
Select Interrupt When Write Tape Next R.eady
2005
Rewind Selected Write Tape
2006
Backspace Selected Write Tape
2007
Rewind-Unload Selected Write Tape
2400
Clear Interrupt Selections on Write Tape
2401
Set Low Density on Selected Write Tape
2402
Set High Density on Selected Write Tape
2403
Skip Bad Spot on Selected Write Tape
2404
Select Interrupt on Next Error
*The equipment designator (fourth octal digit from the right) in 1615 EXF codes may
be either 2 or 3. A switch in the 1615 cabinet determines which number will be
recognized as the designator for that cabinet.
35
SENSE
747C
2000
Exit On Ready To Write
2001
Exit On Not Ready To Write
2002
Exit On Write Reply Parity Error
2003
Exit On No Write Reply Parity Error
2004
Exit On Write Reply Length Error
2005
Exit On No Write Reply Length Error,
2006
Exit an End Of Tape Marker
2007
Exit an Not End Of Tape Marker
2400
Exit an Ready To Select
2401
Exit an Not Ready To Select
2402
Exit an Load Point
2403
Exit an Not Load Point
2404
Exit an Interrupt an Write Tape
2405
Exit an No Interrupt an Write Tape
2406
Exit an Write Program Error
2407
Exit an No Write Program Error
20N1
Select Tape N To Read Binary ane Record
20N2
Select Tape N To Read Coded ane Record
22N1
Select Tape N To Read Binary ane File
22N2
Select Tape N To Read Coded ane File
2001
Prepare Selected Tape To Read Binary ane Record
2002
Prepare Selected Tape To Read Coded ane Record
2201
Prepare Selected Tape To Read Binary One File
2202
Prepare Selected Tape To Read Coded ane File
2003
Move Selected Read Tape Forward ane Record
2203
Search File Mark Forward
2004
Select Interrupt When Read Tape Next Ready
2005
Rewind Selected Read Tape
2006
Backspace Selected Read Tape
2206
Search Eile Mark Backward
2007
Rewind-Unload Selected Read Tape
2400
Clear Interrupt Selections an Read Tape
2401
Set Low Density an Selected Read Tape
2402
Set High Density an Selected Read Tape
2404
Select Interrupt an Next Error
INPUT
74 0
c
36
1
k
SENSE
74 7 C2000
II
1
1
J
Exit on Ready to Read
2001
Exit on Not Ready to Read
2002
Exit on Read Parity Error
2003
Exit on No Read Parity Error
2004
Exit on Read Length Error
2005
Exit on No Read Length Error
2006
Exit on End of Tape Marker
2007
Exit on Not End of Tape Marker
2400
Exit on Ready to Select
2401
Exit on Not Ready to Select
2402
Exit on Load Point
2403
Exit on Not Load Point
2404
Exit on Interrupt on Read Tape
2405
Exit on No Interrupt on Read Tape
2406
Exit on Read Program Error
2407
Exit on No Read Program Error
SATELLITE EXTERNAL FUNCTION CODES
1604-A EXTERNAL FUNCTION CODES
OUTPUT SELECT
74 0 C2500
2501
Release Direct Selections
Select Write Control for 160
ReLease Write Control to 1604
2503
2502
Select Direct 1604 to 160
2504
Select Action Request
2520
Clear Communication Flag 2
2540
Set Communication Flag 1
2560
Clear Communication Flag 1
OUTPUT SENSE
74 7 C2500
Exit on Write Control Available
2501
Exit on Write Control Not Available
2520
Exit on Communications Flag 2 Set
2521
Exit on Communications Flag 2 Not Set
2560
Exit on Communications Flag 1 Set
2561
Exit on Communications Flag 1 Not Set
37
II'IPUT SELECT
74 0 02501
Select Read Control for 160
2502
Release Read Control to 1604
2503
Seleet Direct 160 to 1604
2505
Release Interrupt
INFUT SENSE
74 7 02500
Exit on Read Control Available
2501
Exit on Read Control Not Available
2504
Exit on 160 Interrupt
2505
Exil on No 160 Interrupt
160 EXTERNAL FUN( TION CODES
WRITE SELECT
6050
Release Action Request
6051
Set Communications Flag 2
6052
Release Write Control to 1604
6055
Clear Communications Flag 1
6056
Clear Communications Flag 2
5051
Set Communications Flag 1
5052
Release Read Control to 1604
5053
Select Interrupt
READ SELECT
STATUS RESPONSE*
4XXX
Read Control Available
2XXX
Write Control Available
lxxx
Direct 160 to 1604
X4XX
Direct 1604 to 160
XXX2
160 Action Request
xxxi
Communications Flag 1 Set
* Bits may be superimposed; e. g., 6XXX means both read control and write control
available.
38
1
1
APPENDIX VII
Magnetic Tape BCD Codes
Character
Code
(Octal)
Character
Code
(Octal)
A
61
2
02
B
62
3
03
C
63
4
04
D
64
5
05
E
65
6
06
F
66
7
07
G
67
8
10
H
70
9
11
1
71
&
60
J
41
-
40
K
42
L
43
/
21
M
44
. (period)
73
$
53
‚ (comma)
33
1
(blank)
20
N
45
0
46
P
47
Q
50
R
51
13
S
22
14
T
23
u
v
w
x
24
y
30
group mark
77
Z
31
tape mark
17
54
34
111
0 (numerical zero)
74
12
25
record mark
32
26
0 (minus zero)
52
27
0 (plus Zero)
72
0
12
1
01
39
1
APPENDIX VtU
Flexowriter Codes
CODE
UC
LC
CODE
UC
LC
A
a
30
Y
y
25
b
23
1
a
21
C
c
16
0
59
D
d
22
1
1
74
E
e
20
2
2
70
F
f
26
3
3
84
G
g
13
4
4
62
H
h
05
s
5
66
1
14
6
72
j
32
7
7
60
K
k
36
8
a
33
L
1
11
e
9
37
M
m
07
-
52
N
n
06
/
44
o
o
03
(
)
54
P
p
15
+
‚
48
Q
q
35
•
42
R
r
12
:
50
S
s
24
T
t
01
CR
Upper Case (UC)
Lower Case (Lc)
Back Space (Bs)
Color Shift (cs)
Tabulate (TAB)
Stop
Space
Tape Feed
Delete
45
47
57
61
02
51
43
04
00
77
34
V
V
17
31
x
X
Note
27
Delete - Deleted character
Leader - Blank tape,
- Stop Flexowriter reader,
Stop
10, 40, 41, 53, 55, 63, 65, 67, 71, 73, 75, and76 - illegal
40
APPENDIX IX
Punched Card Codes
•1
Ch'
ard
+
-1
1
1
2
3
1
6
0
=
-
12
B
2
3
03
c
D
6
8
9
1
A
12
02
7
8
01
12
2
5
14
Oard K 2 Char Card BCD
PCD Cn
---
61
J
11
1
11
63
L
12
4
64
MU
4
65
N
12 66
0
2
'
06
F
o
G
12
67
p
11
10
H
1270
II
1
8,3
13
14
/
12
E
12
4-1
20
o
K
2
Card BCD
Lo
62
42
S
t3
T
1
o
2
21
22
23
2
2
45
V
25
6
w
26
47
x
27
Q
1150
Y
1271
R
11
z
±
12
-
•
12
72
77
5
51
)8,4
a
31
11
*
74
30
52
83
41
1
'-
05
°
8,4
6o
Char
114
4
'
8,3
33
(
84
34
APPENDIX X
Input/Output Typewriter Codes
CODE
CHARACTERS
LC
UC
A
a
30
B
b
23
c
r
16
D
d
E
CHARÄCTERS
UC
LC
X
CODE
x
27
7
25
Z
z
21
22
)
0
56
e
20
*
1
74
F
f
26
2
70
G
g
13
#
3
64
H
h
05
$
4
62
i
1
14
5
66
32
0
6
72
7
60
1
k
36
&
L
1
11
-
11
m
07
33
N
06
-
52
0
03
7/
46
15
54
35
+
46
•
42
R
r
12
S
0
24
50
T
t
01
40
u
u
34
02
v
tab
17
tab
apae
51
W
31
Backapace
61
Carriage Retrn
45
Lower Gaee
57
lJpper Caae
47
W
42
04
1
'1
APPENDIX XI
1612 Printer Codes
CODE
CI-IAR
CODE
F
66
V
25
12
0
67
W
26
1
01
11
70
X
27
2
02
1
71
Y
30
3
32
3
03
3
41
2
31
-
35
4
04
K
42
5
05
L
43
6
06
M
44
7
07
N
45
8
10
0
46
9
11
P
A
61
B
CIIAR
CODE
Blank
20
0
0
0
¶1
9
CHAR
CHAR
CODE
16
73
38
-
40
37
+
60
dlo
orv
52
13
$orT
53
(
34
t
55
47
)
74
Q
50
/
21
>
57
62
R
51
*
54
<
72
C
63
S
22
D
64
T
23
E
65
U
24
In last column, codes
scientific application.
:
56
33
75
00
78
14
77
% $ appearif business application, A V 1
43
for
1604-A INSTRUCTIONS
Page
Page
ADD
Add
14
2-17
MUF
Multiply Fractional
26
2-20
ADL
Add Logical
45
2-35
MUI
Multiply Integer
24
2-18
AJP
A Jump
22
2-27,30
OTJT
Output Transfer
63
2-40
ALS
A Left Shift
05
2-13
QJP
Q Jump
23
2-28,31
ARS
A Right Shift
01
2-13
QLS
Q Left Shift
06
2-14
DVF
Divide Fractional
27
2-20
QRS
Q Right Shift
02
2-13
2-38
DVI
Divide Integer
25
2-19
RAD
Replace Add
70
ENA
Enter A
10
2-25
RAO
Replace Add One
72
2-38
ENI
Enter Index
50
2-26
RSB
Replace Subtract
71
2-38
ENQ
Enter Q
04
2-25
RSO
Replace Subtract One
73
2-39
EQS
Equality Search
64
2-36
SAL
Substitute Address, L
61
2-15
EXF
External Function
74
33
SAU
Substitute Address, U
60
2-15
FAD
Floating Add
30
2-20
SBL
Subtract Logical
46
2-35
FDV
Floating Divide
33
2-23
SCA
Scale A
34
2-24
FMU
Floating Multiply
32
2-22
SCL
Selective Clear
41
2-34
FSB
Floating Subtract
31
2-21
SCM
Seective Complement
42
2-33
IJP
Index Jump
55
2-16
SCQ
Scale AQ
35
2-24
77
INA
Increase A
11
2-25
SEV
(not used)
INI
Increase Index
51
2-26
SIL
Store Index, L
57
2-12
INT
Input Transfer
62
2-40
SIU
Store Index, U
56
2-12
ISK
Index Skip
54
2-16
SLJ
Selective Jump
75
2-29,31
LAC
Load A, Complement
13
2-10
SLS
Selective Stop
76
2-29,31
LDA
Load A
12
2-10
SSH
Storage Shift
37
2-32
LDL
Load Logical
44
2-35
SSK
Storage Skip
36
2-32
LDQ
Load Q
16
2-10
SST
Selective Set
40
2-33
LIL
Load Index, L
53
2-12
SSU
Selective Substitute
43
2-35
LIU
Load Index, U
52
2-12
STA
Store A
20
2-11
LLS
AQ Left Shift
07
2-14
STL
Store Logical
47
2-35
LQC
Load Q, Complement
17
2-10
STQ
Store Q
21
2-11
LRS
AQ Right Shift
03
2-13
SUB
Subtract
15
2-17
2-36
MEQ
Masked Equality
66
237
THS
Threshold Search
65
MTH
Masked 'J'hreshold
67
2-37
ZRO
(not used)
00
501 PARK AVENUE, MINNEAPOLIS 15, MINNESOTA • FEDERAL 90411
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