29 394R02_M83 Series__8 32_Maintenance_Manual_Nov75 394R02 M83 Series 8 32 Maintenance Manual Nov75
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Publication Number 29-394R02
M83-SERIES MODEL. 8/32
MAINTENANCE MANUAL
CONSISTS OF:
GENERAL DESCRIPTION
General Description
29-394A12
PROCESSOR
Maintenance Specification
01-07SR01A21
WRITABLE CONTROL STORE
I nstallation Specification
Maintenance Specification
35-555F01 A20
35-555F01 A21
MEMORY
Main Memory System Maintenance Specification
32KB Memory Maintenance Manual
35-535R01A21
29-370R03
EXTENDED SELECTOR CHANNEL
I nstallation Specification
Maintenance Specification
02-32SR01A20
02-32SA21
DISPLAY PANEL
Hexadecimal Display Panel I nformation Specification
09-0S5R01A12
DRAWINGS
Back Panel Map
Processor CPU-A Schematic
Processor CPU-A Assembly
Processor CPU-B Schematic
Processor CPU-B Assembly
Processor CPU-C Schematic
Processor CPU-C Assembly
Processor IOU Schematic
Processor IOU Assembly
Processor ALU Schematic
Processor ALU Assembly
Memory Bus Controller (MBC) Schematic
Memory Bus Controller (MBC) Assembly
Local Memory Interface (LMI) Schematic
Local Memory Interface (LMI) Assembly
Extended Selector Channel Schematic
Extended Selector Channel Assembly
Hexadecimal Display Panel Schematic
Hexadecimal Display Panel Assembly
DMA Terminator Schematic
DMA Terminator Assembly
DMA Terminator Assembly
DMA Cable Assembly
Processor Bus Terminator Schematic
Processor Bus Terminator Assembly
LMB Terminator Assembly
I/O Bus Terminator Schematic
I/O Bus Terminator Assembly
Power Supply Schematic
Power Supply Assembly
01-07SR03DOS
35-53SR 17DOS
35-53SR 12E03
35-537R09DOS
35-537R09E03
35-555ROSDOS
35-555R04E03
35-539R15DOS
35-539R 11 E03
35-53SR05DOS
35-53SR05E03
35-535R 1100S
35-535R04E03
35-534ROSDOS
35-534R04E03
02-32SM02R01 DOS
35-50SM02R01 E03
09-OS5R01 DOS
35-519R03D03
35-54SCOS
35-54SB03
35-572B03
17-33SB03
35-569 DOS
35-569R01 C03
35-57SB03
35-433BOS
35-433R02B03
34-o24R02DOS
34-o24R01D03
THIS MANUAL CONTAINS PROPRIETARY INFORMATION AND IS SUPPLIED BY
INTERDATA FOR THE SOLE PURPOSE OF USING AND MAINTAINING INTER DATA
SUPPLIED EQUIPMENT AND SHALL NOT BE USED FOR ANY OTHER PURPOSE UNLESS
SPECIFICALLY AUTHORIZED IN WRITING_
eX:B.T-"'-::EI::EC,' • .AL.....
~
Subsidiary of PERKIN-ELMER
Oceanport, New Jersey 07757, U.S.A.
@ INTER DATA INC.,1975
All Rights Reserved
Printed in U.s.A.
November 1975
29-394A12
December 1974
M83 SERIES
MODEL 8/32. PROCESSOR
GENERAL DESCRIPTION
1.
INfRODUCTlON
The Model 8/32 Processor is a 32 bit micro-programmed minicomputer. By combining advanced circuits, packaging, and
micro-programming, INTERDATA gives the user a price/performance optimized machine. The Model 8/32 was developed
because of a need for a high-speed 32 bit minicomputer. Because of INTERDATAs experience with 16 bit minicomputers
and a user instruction format that is readily suited for a 32 bit machine, INTERDATA is able to provide a 32 bit machine.
The Model 8/32 is upward compatible with current INTERDATA Processors. Through micro-programming, the Model
8/32 Processor is able to provide present and future owners of INTERDATA's 16 bit minicomputers the ability to grow
into a 32 bit Model 8/32 without having to regenerate all the programs that were created on their 16 bit Processors.
The Model 8/32 has 148 instructions defined which include arithmetic and logical, operational, list processing, floating
point, cyclic redundancy checking, and bit and byte manipulation instructions. Double indexing is also allowed, along with
a multitude of branch instructions. There are 40 extended branch instructions (Mnemonics) defined which brings the total
instructions to 180. Through these instructions and direct addressing, coding and debugging time is reduced to a minimum.
The Model 8/32 offers 32 General Registers, each 32 bits wide in two sets of 16, (optionally expandable to 8 sets). Stack
set selection is controlled by bits in the Program Status Word. The multi-stack organization offers fast and simple context,
switching without the necessity of storing and restoring re/iister stacks. See 32 Bit Series Reference Manual. Publication
Number 29-365.
'
_.The Model 8/32 provides a flexible input/output system in addition to the conventional means of programmed I/O. The
Model' 8/32 can have up to 1,024 auto driver channels. These provide fast automatic character input/output operations, .
including automatic conversion from one character to another. Each character is transferred into or out of memory
without any effect on a running program except for a small amount of stolen time.
The Model 8/32 is capable of directly addressing up to 1,048,576 bytes of m~mory. Memory is constructed of 32KB
memory modules. Memory is addressable to the eight-bit byte level. No paging or indirect addressing is required by the user
instruction sets.
The Memory Access Controller (MAC) uses sixteen 32 bit hardware registers to allow segmentation, relocation, and
memory protection of user programs. There are five different ways memory may be protected.
I.
2.
3.
4.
5.
Address invalid-not accessible to user
Non-present address
Write-protected; read only
Write then interrupt
Instruction execution not allowed
The 8/32 Memory Bus Controller provides access to the extended Direct Memory Access Bus. The extended Direct Memory
Access Bus is a high quality, high speed bus that may have up to seven extended Direct Memory Access (DMA) devices on
the bus.
This information ,is proprietary and is supplied by tNTEROATA for the sole
purpose o-f using and maintaining INTERDATA supplied equipment end shall
not be used for any other purpoie unless specifically authorized in writing.
2.
SCOPE
This specification is intended to enable the digital technician to understand the INTERDATA documentation system. Number Notation, the Part Numbering System, and the Drawing System are described. A cross reference between INTERDATA
part numbers and standard industry part numbers for Integrated Circuits, Transistors, etc., is found in Appendix I. A list of
other publications which may be useful in the programming or trouble shooting of the Model 8/32 system is found in
Table 1.
TABLE 1. RELATED PUBLICATIONS
Title
Publication Number
32KB Memory Maintenance Manual
Multiplexor Bus Buffer Instruction Manual
Loader Storage Unit Users Manual
Paper Tape Reader/Punch Instruction Manual
Universal Logic Module Instruction Manual
1600 BPI Magnetic Tape Instruction Manual
Cassette Users Manual
7 Inch Teletype Manual
29-370*
29-267
29-308
29-291
29-311
29-309
29-298
29-288
*Will be included in this Manual.
BLOCK DIAGRAM
3.
A simplified block diagram of the Model 8/32 system is shown in Figure 1. The Processor logic is contained on three circuit
boards. The Memory Bus Controller (MBC), Local Memory Interface (LMI) and memory are contained on separate boards.
The Arithmetic/Logic Unit (ALU) and Input/Output Unit (IOU) are also separate boards.
Part Number
Description
Card File Position
~
35-534
Local Memory Interface
(LMI)
3T,6T
35-535
Memory Bus Controller
(MBC)
IT
35-536 .
Control Processor A
(CPA)
OT
35-537
Control Processor B
(CPB)
7B
35-538
Arithmetic Logic Unit
(ALU)
4B
35-539
Input/Output Unit
(IOU)
3B
35-555
Control Processor C
(CPC)
6B
Input/Output
2B,IB,OB
Memory
7T,5T,4T,2T
Options
5B
This information is proprietary and is supplied by I NTER OAT A for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
2
not be used for any other purpose unless specifically authorized in writing.
r- -,
8 TH 128 K8 MEMORY
(TOTAL OF 1 MB)
.1
r - --,
32 KB I
I
L....,_.J
L
32 KB
I
_,_J
,
I
r - --,
I
32 KB I
L ...., _.J
r ---,
I 32 KB I
L_._.J
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
2 NO 128 KB MEMORY
1 ST 128 KB MEMORY
MEMORY BUS CONTROLLER
DMA BUS
E:=l E:::::::3 ...I-----LOOKAHEAD STACK
~ E:::-:::l
( 2 X 64 BITS)
INSTRUCTION REGISTER
DISPLAY PANEL
OP CODE
I
Rl
I
X2
I
ADDRESS
16 DEVICES
PROGRAM STATU, WORD
MULTIPLEXOR BUS
MODEL 8/32 PROCESSOR
-8X16
UNIVERSAL
CLOCK
GENERAL
REGISTERS
DIGITAL
MULTIPLEXOR
CARTRIDGE
DISC
ANALOG
CONVERSION
EQUIPMENT
f
I
I
CARD
READER
32
CPU A
(MAC)
00
INTERTAPE
DUAL CASSETTE
CPU B
(ROM)
I
I
L
~-32
f32
+32
CPUC
(DCS")
1
I
---,
S BUS
f32
t
16
DOUBLE"
PRECISION
FLT. PT.
MODULE
I/O
MODULE
+
f32
}
32
1
I
I
ALU/FAU
MODULE
+
16
32
32
J3
A BUS
32
32
.16
32
I--
I
I
32
B BUS
MUX BUS
----~
• OPTIONAL
Figure 1. 8/32 Processor Block Diagram
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
21
3
4.
DOCUMENTATION
This section describes the style and conventions used with INTERDATA documentation.
4.1 Number Notation
The most common form of number notation used in INTERDAT A documentation is hexadecimal notation. In this system,
groups of four binary digits are represented by a single hexadecimal digit. Table 2 lists the hexadecimal characters
employed.
TABLE 2. HEXADECIMAL NOTATION DATA
Binary
Decimal
0000
0001
0010
0011
0100
0101
0
1
2
3
4
5
Hexadecimal
Binary
Decimal
O.
1
2
3
4
5
0110
0111
1000
1001
1010
1011
6
7
Hexadecimal
6
7
8
8
9
10
11
9
A
B
Binary
Decimal
Hexadecimal
1100
1101
1110
1111
12
13
14
15
C
D
E
F
To differentiate between decimal and hexadecimal numbers, hexadecirrial numbers are preceded by the letter "X", and the
number is enclosed in single quotation marks. Examples of hexadecimal numbers are: X'1234', X'2EC6', X'A340',
X'EEFA', and X'IOB9'.
4.2 Part Numbering System
INTERDATA parts, drawings, and publications employ a common numbering system. The part number and drawing
numbers for drawings which describe the part are related. The publication number is also often related to the part number
of the device or program described. Figure 2 shows the format used for INTERDATA part numbers. The fields are
described in the following paragraphs.
A
B
C
XX
YYY
CATEGORY
SEQUENCE
FNN
MNN
.
RNN
,FUNCTIONAL MANUFACTURING REVISION,
•
VARIATION
D
E
NN---I
•
,SIZE
TYPE,
DRAWING
Figure 2. Part Number Fonnat
4.2.1 Category Field. The two-digit Category number indicates the broad class or category to which a part
belongs. Typical examples of category number assignments are:
01 - Basic Hardware Systems
02 - Basic Hardware Expansions
03 - Basic Software Systems
04 - Software Packages
05 - Micro-programs
06 - Test Programs
07 - Subroutines of General Utility
10 - Spare Parts Packages
12 - Card File Assemblies
13 - Panels
17 - Wire and Cables
19 - Integrated Circuits
20 - Transistors
27 - Peripheral Equipment
29 - Manuals
34 - Power Supplies
35 - Assembled Printed Circuit Boards
36 - Electro-Mechanical Devices
This information is proprietary and is supplied by INTEROATA for the IOle
4
purpose of using and maintaining INTEAOATA supplied equipment and shall
not be used for any other purpose unlns specifically authorized in writing.
4.2.2 Sequence Field. The Sequence number identifies a particular item within the category. Sequence numbers
are assigned serially, and have no other significance.
NOTE
The Sequence Field, like all other part number
fields, may be lengthened as required. The field
lengths shown on Figure 2 are minimum lengths
(insignificant zeros must be added to maintain
these minimums).
A .part number must contain a Category number
and a Sequence number. All other fields are optional.
4.2.3 Functional Variation Field. The optional Functional Variation Field consists of the letter "F" followed by
two digits. The F field is used to distinguish between parts which are not necessarily electrically or mechanically equivalent, but which are described by the same set of drawings. For example, a power supply may be strapped internally to
operate on either 110 VAC or 220 VAC. Except for this strap, all power supplies of this type are identical. The strapping
option is easily described by a note on the assembly and test specification drawings. Therefore, this is a functional
variation.
4.2.4 Manufacturing Variation Field. The optional Manufacturing Variation Field consists of the letter "M"
followed by two digits.
The M Field is used to distinguish between parts which are electrically and mechanically equivalent (interchangeable), but
which vary in method of manufacture. For example, if leads are welded instead of soldered on an assembly, the M Field
changes.
An important exception to the meaning of the M Field exists for categories related to software. In software, the M Field
number, when used, indicates the form in which a particular program is presented. For example, derme a program as a set
of machine instructions. These same identical instructions may be presented on punched cards, paper tape, or magnetic
tape; and for any of these they could be in symbolic form or in relative or absolute binary form. Thus, there are many
ways to present the same identical program.
The format for the M field and its meaning for software is:
Mxy
where x identifies the media selection (i.e., paper tape, mag tape, cassette, etc.) and
y identifies object or source and the format.
Meaningofx
Meaning of y
Paper tape
Object program standard format 32 bit Processor
Cassette
2
4 Memory Image
Mag tape (800)
3
6 Object program standard format 16 bit Processor
Cards
4
7 Object non-standard format
Disc (2.5)
5
8 Object established task
9 Source program
The above numbers refer to the physical program placed on an approved media for INTERDATA Software. A paper tape
object program in standard format and for a 16 bit Processor has an Ml6 identifier. A magnetic tape object program in
standard format and for a 32 bit Processor has an M31 identifier.
In addition to the above, there are three unique M numbers which have special meaning:
M99 always refers to a documentation package.
MOO always refers to a conceptual object program divorced from any media. This reference is used for all parts lists
when object programs may be on any media.
M09 always refers to a conceptual source program and is used on all parts lists where any media may be used.
NOTE
MOO and M09 may only be used on parts lists
and never identify a physical program on any
media.
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shell
not be used for any other purpose unlns specifically authorized in writing.
'5
4.2.5 Revision Field. The optional Revision Field consists of the letter "R" followed by two digits. The R Field
is used to indicate minor electrical or mechanical changes to a part which do not change the part's original character. R
Field changes often reflect improvements. A part with a revision level HIGHER than the one specified will work. A part
with a revision level LOWER than specified should not be used.
4.2.6 Drawing Field. The optional Drawing Field consists of a letter from "A" to HE" followed by two digits.
The letter indicates the size of the original drawing. The sizes for each letter are:
A - 8%" X 11"
B - 11" X 17"
c - 17" X 22"
D - 22" X 34"
E - 34" X 44"
The two digits indicate the drawing type as follows:
01 - Parts List
13 - Program Listing
02 - Machine Details
14 - Abstracts
03 - Assembly Details
15 - Program Description
05 - Art Details
16 - Operating Instructions
06 - Wire Run List
17 - Program Design Specifications
08 - Schematic
18 - Flow Charts
09 - Test Specification
19 - Product Specification
10 - Purchase Specification
20 - Installation Specification
11 - Bill of Material
21 - Maintenance Specification
12 - Information
22 - Programming Specification
4.2.7 Examples. The following list provides examples of the part numbering system. The numbers were arbitrarily selected, and in most cases are fictitious.
35-060
The 60th printed-circuit board assigned a part number under this system.
35-060MOI
A printed circuit board electrically and mechanically interchangeable with the 35-060, but differing in
method of manufacture.
35-060FOI
A printed-circuit board not electrically and mechanically interchangeable with the 35-060, but described by the "Same set of drawings.
35-060ROI
A revised 35-060 printed-circuit board. Probably supercedes the 35-060.
35-060AOI
The 8% by 11 inch parts list for a 35-060.
35-060B08
The 11 by 17 inch schematic for a 35-060.
06-072
The 72nd utility program assigned a part number.
06-072AI3
An 8% by 11 inch listing of the 06-072 program.
06-072M03
An absolute binary deck of punched cards for the 06-072 program.
06-072AI2
An 8% by 11 inch information drawing on the 06-072 program. Probably a part of the program.
29-060
The 60th manual assigned a number under this system. Note that this number is not referenced in any
way to the part number of equipment described in the manual.
This information is proprietary and is supplied by INTEADATA for the lole
6
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
4.3 Drawing System
This section describes the drawings provided with INTERDATA equipment. Note that drawings provided with peripheral
devices and other purchased items may vary from the system described in this section.
A digital system may be divided into a collection of functionally independent circuits such as memory, Processor, and I/O
device controllers. These circuits mayor may not be saleable units in their own right, but in the electrical sense they are
essentially self contained and capable of performing their function with minimum dependence on other functional circuits
in the system. Hence a functional circuit is treated as a building block. Each schematic contains a variety of information
including type and location of discrete Integrated Circuits (IC's), pin connections, all interconnections within the schematic, connector pin numbers and connections to other schematics. Further, the schematics are drawn to reflect, in an
orderly fashion, all logical operations performed by the circuits. Generally, symbols used on schematics conform to
MIL-STD-806B.
Registers are named according to the following rules:
1. The register Mnemonic name has a maximum of three letters, excluding "I, 0, Q, and Z".
2. Each bit in the register is numbered, usually starting at 00 on the left, or most significant positions, and continuing
to N-l on the right, where N is the number of bits in the register.
3. The 00 bit is the Most Significant Bit and the N-l is the Least Significant Bit.
The IC's, mounted directly on the logic board, are represented on the schematic drawings by logic symbols. Each symbol
contains the reference designation, device part number (category and sequence), and symbol Mnemonic designation. Refer
to Figure 3.
r
I~
LI
SAME SHEET DESIGNTION
. _.
ANOTHER SHEET DESIGNATION ~
ENBLI
.,RD020
218-0/ .
117 0" RD031
-/.
114_0,RD061
01
02
04
05
llS
19-061
~{
06
NAMEO
SB
10Ml
12A2
18K4
/
Figure 3. Example of a Schottky Buffer
The designations, numbers, and references shown in Figure 3 are:
lIS -
This indicates the component location on the logic board. Figure 4 illustrates the method generally used to
determine component location on a logic board. With the logic board oriented so that the header connectors
(Conn 0 and Conn 1) are on the right, the components are numbered from left to right starting in the upper
left comer. That is, the first IC in the upper left comer is OOA and the first capacitor is Cl. Test points are
lettered right to left from A-Y (omitting I, 0, L, E).
19-061 - The number 19 is the category number of ICs, and the 061 is the sequence number of the component.
SB -
Indicates this component is a Schottky Buffer. Some other common designations used are:
P - Power Gate
SA - Schottky AND Gate
SB - Schottky Buffer
SG - Schottky Gate
SGO - Schottky Gate, Open Collector
HG - High Speed Gate
HPO - High Speed Power Gate, Open Collector
SFF - Schottky Flip-flop
.
L1 - This input lead is from area L1 on the same schematic sheet.
1aMI, 12A2, 18K4 - Indicate outputs to another logic schematic sheet.
218-0, 117-0, 114-0, - Indicate inputs from Connector O.
Note that the pin numbers (0 1, 02, 04, as and 06) correspond directly to the actual IC pin numbers.
Figure 4 also shows the locations of the header connectors (Conn 0 and Conn 1) and the cable connectors (Conn 2 and
Conn 3). All logic boards always contain Header Connectors 0 and 1, however, any combination (either, both, or none) of
cable connectors (Conn 2 and Conn 3) may be provided.
This information is proprietary and is supplied by INTERDATA for the role
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
7
vclDA
B
C
M
0
S
TOes
0"
1005 II OOT\41
D~
CONNECTOR 1
100AIIooB II OOC I
CONNECTOR 5
2
,001 01A.\
o
0
I I
I I
I I
I I
I I
I I
I I
I I
:ONNECTOR 4
I
00 o
2 1
2 1
~§]
o~
I
0
1 2
41
y
0
I
I
:ONNECTOR 3
r
CONNECTOR 0
0"
I
CONNECTOR 2
2
I
I
I
I
00
1
I
00 0
1
A
Figure 4. Example of a Logic Board Layout
Pocked devi~s, flip-flops and counters in particular, are drawn in a manner which indicates information concerning their
inputs. An input which has a circle adjacent to the pin designation implies a low active signal is required to perform the
specified operation. In addition, a rotated V at the clock input shoWs that the device changes state on an edge. Thus, if
po cirCle is present the chip is positive edge triggered. Refer to Fi~re 5 for examples.
.
Figure
6 provides the pin numbering scheme for the header and cable connectors. Header connectors always have 2 rows of
pins and 42 positions. Cable connectors always have 2 rows of pins but may vary in the number of positions.
FPSELI
.FPSELOA
19'()15
0
0
HG
19-045
19-089
HFF
SDFF
0
FPSELO
OFF
C
A. NEGATIVE EDGE TRIGGERED
B. POSITIVE EDGE TRIGGERED
Figure S. Examples of Oocked Devices
8
19-027
This infornwtion i. proprietary and il supplied by fNTERDATA for the IOIe
purpoH of using and maintaining INTER DATA supplied equipment and lhail
not be UMd for any other purpose un... specifically authorized in writing.
Of---
C. POSITIVE LEVEL TRIGGERED
"-.
16
15
14
0
0
0
0
0
0
24
23
22
114-5
0
0
0
0
0
_
122-3
241-1----;:::::::....,.,........
141-1
41
40
39
38
37
CONNECTO~'
202-5
02
01
00
24
23
22
02
01
00
0
0
0
0
0
0
2
1
0
0
0
0
102-5
02
01
00
16
.
15
14
122-4
222-4
02
01
102-4
0
0
0
0
2
1
00
202-3
102-3
203-1
103-1
o
o
0
0
0
0
0
0
0
0
0
0
2
1
0
0
0
0
0
0
114-2
0
0
202-2
102-2
0
0
0
o
2
1
1 2
0
o
03
02
01
00
1 2
241-0
141-0
0
o
o
o
203-0
103-0
-
o
o
0
0
0
0
0
0
0
41
40
39
38
03
02
01
00
Figure 6_ Connector Pin Numbering
.
A net is defined as an electrical connection between two or more points in a circuit_ Ordinarily, a net has an originating end
(usually an output where the signal is generated) and one or more terminating ends_ Often it is convenient to assign
descriptive mnemonic names to nets as a way of identifying them on schematics. Whether a net is named or not is
somet~s:s arbitrary. However, a net is always assigned a name if:
1. The net is contained on one drawing sheet but is not shown as a complete solid line on that sheet.
2. Part of the net appears on more than one sheet.
3. Part of the net connects with a different schematic.
4. Part of the net leaves a logic board_
If a net is named, the following rules are observed.
1. All mnemonic names are a maximum of six characters.
2. All decimal digits and upper case letters are permitted.
3. No other characters permitted_
4. Where possible, Mnemonics are descriptive. However, it should be recognized that descriptive names are not always
possible and a danger of misinterpreting a Mnemonic exists.
5. Mnemonic names are not repeated within a schematic.
6. Every Mnemonic is suffixed by a state indicator. This indicator consists of the digit" I" for the logically true state,
or the digit "0" for the 10'gically' false state. For example, the set side of a flip-flop would have the "I" state
indicator, while the reset side would have the "0" state indicator. The state indicator for a function changes each
time that function is inverted. Thus, the state indicator permits assigning the same Mnemonic to functions that are
identical except for an inversion.
7. When a logical function is inverted, an inversion indicator is added after the state indicator. This allows for
functionally equivalent, but electrically different nets to have the same Mnemonic name_ For example, assume a
signal NAMEI, NAMEI may be inverted to produce NAMEO. If NAMEO is then inverted, NAMEIA is produced_
NAMEl and NAMEIA are functionally equivalent, but physically different nets.
This information is proprietary and is supplied by INTERDATA for the IOle
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
9
Sometimes a net fans-out to many sheets in a schematic. It is also possible for a net to fan-out to sheets in
different schematics. In these situations, the net is assigned a mnemonic name. The net is also "zoned" from sheet
to sheet to allow for properly identifying the originating and terminating ends of the net. The originating end of a
net is defined as the collector at which a signal is generated. All other points to which the net connects are called
terminating ends. When a lead leaves a sheet at the originating end, it is zoned to each and every sheet on which
the net reappears, by indicating first the page number, followed by the schematic number that contains the page.
For example, assume that the gate shown on Figure 3 is on a schematic, Sheet 20. The output NAMEO, appears
on Sheets 10, 12 and 18 of the schematic. Note that thl ~ schematic number is implied. When a net enters a sheet
from another sheet, it is labeled, with the same Mnemodc name, and is zoned back to the originating end of the
net only. Thus, on Figure 3, the ENBLl may, however, have many other terminations in addition to the one
shown. Generally, then, when a net leaves the sheet where it originates, it is zoned to every other sheet where the
net terminates, while the terminating end is zoned only to the originating sheet. Note that in the Model 8/32
schematics, signals are co-ordinated between sheets only when the sheets are related to the same board. Whim a
signal leaves a board, the Back Panel Map must be used.
When a lead leaves a logic board, it usually does so through a logic board back panel connector pin. These
connector pins must be shown on the schematic even if the complete net is shown: on one drawing sheet. Only the
connector pin number need be indicated under the pin symbol, since the connector number itself is implied by the
logic board location number in the logic symbol or in the footnote. Thus, on Figure 3, RD061 enters the logic
board on Pin 114 of Header Connector O.
Figure 7 is a typical schematic sheet with call-outs illustrating many of the conventions described in this section.
The schematic drawings for the basic Digital System and some of the more common expansions are commonly
included in the rear of the appropriate Digital System Maintenance Manual. Schematic drawings for other
expansions are included with the expansion or with the publications that describe the expansion.
10
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be Uled for any other purpose unless specifically authorized in writing.
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APPENDIX 1
PART NUMBER CROSS REFERENCE TABLE
INTERDA T A Part Number
Type
JEDIC Number
19-001
Dual 4 Input Nand DTL
15861
19-002
Triple 3 Input Nand DTL
15863
19-003
Quad 2 Input Nand DTL
15849N
19-004
Hex 1 Input Nand DTL
15837N
19-005
Dual Power Gate DOC
8633N
19-006
Dual Buffer DTL
1582N
19-007
Flip- Flop DTL
15848N
19-008
Gate Expander Dual 4 Input DTL
15833N
19-009
8 Bit Stack DTL
9030!)9 (Fairchild)
19-010
Differential Compartor LIN
72710L
19-012
Dual 4 Input Buffer TTL
74H40H
19-013
Quad 2 Input
19-014
Dual J-K Flip-Flop DTL
158097N
19-015
Hex Inverter 1 Input
74H04H
19-016
Quad 2 Input TTL
74HOON
19-017
Triple 3 Input TTL
74H10N
19-018
Dual 4 Input TTL
74H20N
19-019
Single 8 Input TTL
MC3015 (Motorola)
19-020
Operational Amplifier LIN
Me 1709C (Motorola)
19-021
Quad 2 Input Power DOC
15858N
19-0:!2
Dual J-K Flip-Flop TTL
MC3061P (Motorola)
19-023
Selected Dual Buffer 19-006 with
20-30 nsec. delay DTL
15832N
19-024
Triple 3 Input AND TTL
74HllN
19-025
Dual 4 Input AND TTL
74H21N
19-026
2-2-2-3 Input AND-OR TTL
74H52
N~d
DTL
15846
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unleu specifically authorized in writing.
Al-l
JEDIC Number
INTERDA T A Part Number
19-027
4 Bit Latch TTL
74.75N
19-028
4 Bit Adder TTL
7483N
19-029
Quad Exclusive - OR TTL
7486N
19-030
4 Bit Shift Register TTL
7495N
19-031
One Shot TTL
7412lN
19-032
1 out of 10 Decoder TOC
74145N
5445
7445
19-033
Sense Amplifier LIN
7524N
19-034
Retriggerable One Shot TTL
74122N
19-035
4 Bit Counter TTL
74193N
19-036
Quad 2 Input Open Collector TTL
7438N
19-037
High Performance Operational Amp
7748393 (Fairchild)
19-038
Dual 4 line to 1 line Mux TTL
74153
19-039
4 Bit ALU TTL
74181
19-040
Look Ahead Carry TTL
74182
19-041
4 x 4 Register Stack TTL
74170
19-042
Dual Retriggerable One Shot TTL
74123N
19-043
Quad 2 Input Open Collector TTl
74HOIN
19-044
Hex Inverter Open Collector TTL
74H05N
19-045'
DlI:al J-K Flip-Flop TTL
74HI06
19-046
Quad RS-232C Line Driver
I\TC 1488L (Motorola)
19-047
Quad RS-232C Line Receiver
I\IC1489AL (Motorola)
19-048
8 Bit Shifter
74198N
19-050
8 Input Nand TTL
74H30
19-051
1024 Bit PROM TTL
741R7 (Fairchild)
19-055
Quad 2 Input Nand STTL
74S00
19-056
Quad 2 Input Nand Open Collector STTL
74S03
19-057
Hex 1 Input Inverter STTL
74S04
19-058
Triple 3 Input Nand STTL
74S10
19-059
Triple 3 Input AND STTL
74S11
19-060
Dual 4 Input Nand STTL
74S20
AI-2
This information is proprietary and is suppHed by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specificaliV authorized in writing.
INTERDATA Part Number
--
_~
JEDIC Number
19-061
Dual 4 Input Buffer 8TTL
74840
19-062
2-2-3-4 Input AND-OR Inverter 8TTL
74864
19-063
Dual D Edge Triggered Flip-Flop 8TTL
74874
19-064
Dual J-K Flip-Flop 8TTL
748112
19-065
Quad 2:1 Mux Non-inverting 8TTL
748157
19-066
Quad 2:1 Mux Inverting 8TTL
748158
19-067
4 Bit ALU 8TTL
748181
19-068
Carry Look Ahead 8TTL
748182
19-069
8 line to 1 line Mux STTL
74151
4 Bit Syncronous Counter TTL
74161
19-071
Quad D Edge Triggered Flip-Flop
74175
19-072
4 Bit Left/Right Shift Register TTL
74194
19-073
Dual 4:1 Mux Tri-8tate TTL
8214 (National)
19-074
8 Bit Priority Encoder TTL
9318 (Fairchild)
19-075
16 x 4 Register Stack TTL
3101A (Intel)
lfl-07fl
1024 Bit Memory MOS
Tl\l54062
19-077
256 Bit Memory TTL
6531 (Monolithic Memories)
Dual 4 Input Nand-OC
74S22
19-080
High-Speed PROM
82S29 (Signetics)
19-081'
Univ. Asynchronous Receiver/Transmitters
TR1042A (Western Digital)
19-082
2-2-3-4 Input AND-OR Invert Open
Collector 8TTL
74865
19-083
9 Bit Parity Generator/Checker STTL
82862 (Signetics)
19-085
Monolithic Timing Circuit
MC 1555 (Motorola)
NE555V (Signetics)
19-086
741 C DIP Operational Amplifier
U6A 7741393 (Fairchild)
19-087'
747 DIP Operational Amplifier
U7 A 774 (Fairchild)
19-088
737 C DIP Operational Amplifier
U6A773393 (Fairchild)
19-089
Dual D Edge Triggered Flip- Flop
74H74
19-090
High Speed (710) Differential Comparator DIP
U6A771093 (Fiarchild)
19-091
Retriggerable 8ingle One Shot
9600 (Fairchild)
19-070
'!.,-~ :~;
19-078
r"
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
AI-3
INTERDATA Part.----Number
JEDIC Number
19-092
Negative Voltages Regulator
MC1463R (Motorola)
19-093
Posilive Voltages Regulator
MC1469R (Motorola)
19-094
Voltage Regulator
U6A7723393 (Fairchild)
MC1723CL (Motorola)
19-095
Linea~
U9H7805393 (Fairchild)
19-096
First In- First Out Serial Memory
(;4 Word 4 Bit
3341.(Fairchild)
19-097
Amplifier
LH0002H (National)
19-098
Quad 2:1 Multiplexor Non-Inverting
74157
19-099
Dual Sense Amplifier
75234N
19-100
Driver
75452N
19-101
4-2 Input Buffer
7437N
19-102
6-1 Input Buffer OC
7407N
19-103
1 out of 10 Decoder
7442N
19-104
Current Switch
75325N
19-105
Dual Diffential Driver
Fairchild 9614
19-106
Dual Diffential Receiver
Fairchild 9615
19-107
Sense Amplifier
SN7520N
19-108
Quad 2 Input Nand
SN7400N
19-109.
Hex Inverter Open Collector
SN7406N
19-110
Hex Inverter
SN7404N
19-111
Dual 4 Input Nand
SN7440N
19-112
Optically Coupled Isolator
TIL-1l14N25
19-113
360 Dual Transmitter
TI 75123
19-114
360 Triple Receiver
TI75124
19-115
Quad 2 Input AND
74H08
19-116
Dual 4:2 Multiplexor STTL
74S153
19-117
4 Bit Magnitude Comparator STTL
74885
19-118
Quad Bus Transceiver TTL
26S12A
19-119
Expandable AND-OR Invert TTL
74455
19-120
Dual Timer
Signetics NE556
Al4
Positive Voltage Regulator
This information is proprietary and is supplied by INTEROATA for the IOle
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
INTERDA T A Part Number
JEDIC Number
19-121
Matched Pair 19-085 (P. S. Timing)
See 19-085
19-123
Dual Voltage Controlled Oscillator
74S124
19-124
Quad 2 Input Nand Buffer, STTL
74S37
19 -125
O.C. Quad 2 Input Nand Buffer, STTL
74S38
19-126
Dual 2 Wide-2 input AOI, STTL
74S51
19 -127
Quad Exclusive-OR, STTL
74S86
19 -128
12 Input Nand-Tri State, STTL
74S134
19 -129
3 to 8 Decoder, STTL
74S138
19 -130
Dual 4 in. Nand 50 Ohm Driver, STIL
74S140
19-131
Quad D Flip Flop, STIL
74S175
19 -132
Quad 2/1 Mux.-Tri State, STIL
74S258
19 -133
4 Bit Binary Adder, TTL
74283
19 -134 '
Hex Buffers/Inverts, TIL
8T98
19 -135
4 Bit Binary Counter, STIL
93S16
20-001
Transistor NPN High Speed Switch
2N3646
20-002
Transistor PNP 500 MA
MPS6534 (Motorola)
20-003
Transistor
2N3902
20-004
Transistor NPN
2N51R9
20-006
Transistor NPN 15 Amps lOOW T03
case
2N3055 (RCA)
20-007
Transistor NPN 3 Amps
TIP31A
20-008
Transistor PNP 3 Amps
TIP32A
20-009
Transistor Triac 2 Amps 100V
A03001 (Electronic Control
Corp).
20-010
Transistor NPN 500 MA Code Driver
2N5845
20-011
Transistor Photo
2N5777
20-012
Transistor PNP High Current Switch
2N2907
20-013
Transistor NPN
2N3303
20-014
Transistor NPN
2N4238
20-015
Transistor PNP
2N4235
20-016
Transistor PNP
2N3740
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
Al-5
INTER DATA Part Number
Type
JEDIC Number
20-017
Transistor NPN
2N3766
20-018
Transistor, Power Silicon Nl'N
2N3054
20-019
Transistor NPN Fast PWR Switch
2N6308 (Motorola)
20-020,
Transistor Switching 1 Amp T05 can
2N3725
20-021
Transistor NPN Silicon
MPS3646 (Motorola)
20-022
Transistor NPN
INI711
20-023
Transistor PNP
2N2905A
20-024
Transistor Switch
2N3776
20-025
PNP HI SPEED Switch
2N3467
20-026
Transistor Module, Quad
MPQ3725
20-027
Transistor·
2N2369
20-029
Transistor
21-025FOI
lK ohm-15 to Common DIP
898-1-IK ohm (Beckman)
21-025F02
470 ohm-15 to Common DIP
898-1-470 ohm (Beckman)
?1-025F03
330 ohm-15 to Common DIP
898-1-330 ohm (Beckman)
23-001
Diode High Speed-High Current
IN914
23-002
Diode 5. 1 V- Zener
IM5. lZS5 (Motorola)
23-003
Diode 10V Zener
IMI0ZS5 (Motorola)
23-004
Diode 6. 2 V Zener
IM6. 2ZS5 (Motorola)
23-007
Diode Mot Bridge
MDA962-2 (Motorola)
23-008
Diode Int. Rectifier
40HF-5R
23-009
Diode
IN4735
23-010
Diode Int. Rectifier
SIYlP
23-011
Diode Rectifier
2N681
23-012
Diode Thermister
KA31Jl (Fenwall)
23-013
Diode 9.4V
IN2163
23-014
Diode
IN3880
23-015
Diode
IN3889
23-016
Diode Bridge Recitifer
\'S448 (Varo)
23-017
Diode
IN2070
This information is proprietary and is suppHed by INTER DATA for the IOle
Al-6
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
INTEIWATA Part Number
Type
JEDIC Number
23-01S
Diode IS V Zener
1N4746A
23-019
Diode
1N3615
23-020
Diode S. 2V Zener
1N756A
23-021
Diode 9. 1 V Zener
1N757A
23-022
Diode 3. 3V Zener
1N746A
23-023
Diode Bridge Rectifier
KBH2506 (General Instrument)
23-024
Diode, Power Fast Rec. 30 Amps.
IN3909
23-025
Diod'3, Power r;1st nee. 3 Amps.
A1l5A (General Electric)
23-026
Triac 600V 30 Amps
2N6162
23-027
Diac 32V
1N5761
23-02S
Power SCR Thyristor
2N4441
23-029
Diode
1N4607
23-030
Diode
1N4156
23-031
Diode 6.6 V Zener
1N4736
23-032
Diode 8.8 V Zener
1N4739
23-033
. 16 Diode Array
·45190 (Litton)
30-01S
100 nsec. Delay Line 10 taps
30-01S (Princeton Advanced
Eng. )
30-019
50 nsec. Delay Line 10 taps
30-01S (Princeton Advanced
Eng. )
33-034
PR CKT Count Butt Contact
Push Button Switch ~ AMP SPDT
33-035
8 Pole Dip Switch AMP Part No. 4351665
.~
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
AI-7/AI-8
OI-078ROIA21
November 1975
MODEL 8/32. PROCESSOR
MAINTENANCE SPECIFICATION
TABLE OF CONTENTS
I. INTRODUCTION
1.1 Packaging
1. 2 Processor .
1.3 Control Store
1.4 Peripherals . .
2. INTERNAL ARCHITECTURE
2.1 Modules . . . . . . . .
2.2 Micro-Instructions
2.3 Interrupts . . .
2.4 Registers . . . .
2.5 Processor Timing
2
2
2
2
2
3. FUNCTIONAL DESCRIPTION OF THE BASIC PROCESSOR
3.1
3.2
3.3
3.4
3.5
3.6
Processor Busses
Registers . . . .
Interrupts
Control Store Memory
Micro-Programming .
Processor Block Diagram Analysis
4. CPA GENERAL DESCRIPTION . . .
4.1
4.2
4.3
4.4
4.5
CPA Block Diagram Description
Memory Addressing . . . . .
Memory Reference Operations
S Bus Operations .
B Bus Operations . . . . . . .
5. CPB FUNCTIONAL DESCRIPTION
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
2
2
4
4
4
5
13
17
17
19
24
34
35
36
36
State Counter and Control
Clock and Control
Control Store
Bus Selection .
Interrupts
PSW Register .
Branch Control .
A, B, and S Gating
Test Aids . . . . .
37
38
39
40
41
41
41
. 41
This information is proprietary and is supplied by INTEADATA for the IOle
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpole unless specifically authorized in writina.
6. CPC GENERAL DESCRIPTION . . . .
6.1
6.2
6.3
6.4
TABLE OF CONTENTS
(Continued)
. . . . . . . . . . . . . . . . . . . . . . . . . 42
A and B Stacks (ASTK and BSTK)
S Buffer (SBUFF) .
Stack Addressing . .
Read/Write Control
46
7. ALU
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
43
43
43
46
Arithmetic State Register (AS)
ALU Algorithms . . . . . . .
ALU Clock . . . . . . . . . .
Arithmetic Iterative Counter (ACNTOI :05)
Arithmetic Condition Code . . . . . . .
Arithmetic Elements and ROM Control
MQ Register . . . . . . . . . . .
AL Register and Shift Multiplexors
Exponent Arithmetic . .
48
48
57
58
58
59
59
61
61
8. I/O GENERAL DESCRIPTION
61
9. FUNCTIONAL DESCRIPTION
61
9.1
9.2
I/O Control Functions .
Machine Malfunction and Power Fail Hardware
10. MULTIPLEXOR CHANNEL (MUX) BUS
10.1
10.2
10.3
Multiplexor Channel IOU . . . . . . . . . . . . . . . .
Multiplexor Channel Timing . . . . . . . . . . . . . .
Multiplexor Channel and Multiplexor Operations (MUX)
11. BYTE MANIPULATION AND AUXILIARY FUNCTIONS
11.1
11.2
Byte Manipulation Functions
Auxiliary Functions
64
66
69
75
75
78
. . . . . . . 79
Block Diagram Analysis
Bus Communication and Address Circuits
Status and Commands
Timer Circuits
Data Output
Data Input . . .
Interrupt Circuit
Initialization ..
TTY Timer Adjustment
Machine Control Register (MCR)
Power Monitor and System Initialize
Primary Power Fail Check
Start Timer . . . . . . . . . . . . .
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
ii
64
79
79
79
79
79
Addressing Logic
Data Output
Data Input
Status Input
Control Logic
13. TELETYPE CONTROLLER
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
13.11
13.12
13.13
64
79
12. Dl SP LA Y COUNTER
12.1
12.2
12.3
12.4
12.5
6]
not be used for any other purpose unless specifically authorized in writing.
80
80
80
81
81
83
85
85
85
85
85
87
87
TABLE OF CONTENTS
(Continued)
14. IOU SAND D BUS ROM CONTROLLERS
14.1
14.2
14.3
IS.
..
IOU S Bus High ROM Controller (l9-142F4s)
IOU S Bus Low ROM Controller (l9-142F46)
IOU Bus ROM Controller (l9-142F47)
88
89
90
91
EXTENDER BOARD OPERATION
16. MNEMONICS . . . . . . . . . . . .
16.1
16.2
16.3
16.4
16.5
88
92
CPA Mnemonics, Schematic Drawing 35-536008
CPB Mnemonics, Schematic Drawing 3s-s37D08
CPC Mnemonics, Schematic Drawing 3s-sssD08
ALU Mnemonics, Schematic Drawing 3s-s38D08
IOU Mnemonics, Schematic Drawing 3s-s39D08
·92
·95
·99
100
104
ILLUSTRATIONS
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure SA.
Figure sB.
Figure SC.
Figure 6
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13A.
Figure 13B.
Figure 14.
Figure 15.
Figure 16A.
Figure 16B.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Model 8/32 Module Concept . . . . . . .
Control and Module Instructions . . . . .
CPU (CPA, CPB, and CPC) Block Diagram
CPA Block Diagram . . . . . . . . . . . .
Instruction Read, RR or SF Formats . . .
Instruction Read RXl, RX2 or RII Formats
Instruction Read RX3 or RI2 Formats
Second Halfword Oock Timing
Data Read Operation
Data Write Operations
CD Bus Interface ..
CPU State Diagram .
Simplified Oock Circuit
Simplified Control Store Diagram
Control Store Address Gating Low (CSAIO:l 5)
Control Store Address Gating High (CSA4:9)
CPC Block Diagram . . . . . . . . . .
A Stack Timing Diagram, 32-Bit Write
SBUFF Timing, 32-Bit Write
SBUFF Timing, 64-Bit Write
Stack Addressing Scheme ..
ALU Functional Block Diagram
ALU State Transistions . . . .
ALU Bus Timing - Immediate Response Functions (FSELOOO)
IOU Block Diagram . . . . . . . . . . . . . . . . . . .
Multiplexor Channel Timing . . . . . . . . . . . . . . . . .
Multiplexor Channel (Input) Timing ADRS and SR/DR
Multiplexor Channel (Output) Timing ADRS and CMD/DA
Multiplexor Circuit Generation Description
Cycle Counter . . . . . . . . . . . . . . . . . . . . .
Multiplexor Channel Timing, ACK . . . . . . . . . .
D Bus ROM Controller Data Gating for WD and WDA
ROM Controller Data Gating for RDH and RDHA
Serial ASCII Code U (Even Parity) ..
Teletype Controller Block Diagram . .
Write Mode (Output) Timing, Teletype
Read Mode (Input) Timing, Teletype .
3
5
15
18
27
28
29
30
31
32
33
36
37
39
40
40
42
44
44
44
45
47
48
49
63
66
67
68
70/71
72
74
77
78
79
82
83
84
This information is proprietary and is supptied by INTER DATA for the IOle
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
iii
TABLE OF CONTENTS
(Continued)
TABLES
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
FUNCTION CODES FOR CPU INSTRUCTIONS . . . .
MC FIELD . . . . . . . . . . . . . . .
INTERRUPT TRAPS . . . . . . . . . . . . . . . . .
EXTERNAL INTERRUPT ENABLE . . . . . . . . . . . . . . . .
REGISTER ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . ..
MODULE 1 (FIXED POINT) AND MODULE 3 (FLOATING POINT) OPERATION
I/O CONTROL FUNCTIONS . . . . . . . . . . . .
STARTING LOCATION JUMPERS . . . . . . . . .
MEMORY ACCESS INTERRUPT SIGNALS . . . .
MEMORY ACCESS INTERRUPTS . . . . . . . . .
MICRO COMMANDS . . . . . . . . . . . . . . . . .
INCREMENT MICRO-COMMANDS . . . . . . . . . .
S BUS SELECT DECODING . . . . . . . . . . .
CONTROL STATE LOGIC IMPLEMENTATION
ALU FUNCTION CODES . . . . . . .
STATE REGISTER LOGIC . . . . . . .
ALU ROM CONTROL . . . . . . . . . . . . . . . . .
FUNCTION MNEMONICS . . . . . .
I/O MODULE FUNCTION GATING .,
......... .
STB INSTRUCTIONS .. . . . . . . . . . . .
. . . . . . . . ..
. .......... .
TELETYPE STATUS AND COMMAND BYTE
. . . . . . . . . .
. .......... .
MCR BIT ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
8
9
9
10
11
14
21
23
24
24
34
35
37
47
49
60
62
76
76
80
86
'---
This information is proprietary and is supplied by INTER DATA for the IOle
purpose of using and maintaining INTERDATA supplied equipment and shall
iv
not be used for any other purpose unless specifically authorized in writing.
/ "
J
~-~
MODEL 8/32 PROCESSOR
MAINTENANCE SPECIFICATION
1.
INTRODUCfION
The INTERDATA Model 8/32 Digital System is a low cost, general purpose system, versatile enough to perform a wide
range of industrial control, data processing, and scientific computation. The Model 8/3-2 is well suited to the real-time
scanning of hundreds of instrument readings, process alarms, and pulse trains. It is particularly useful where larger amounts
of main Processor time are needed for computation.
1.1 Packaging
The Model 8/32 Processor is contained in a 19 x 14 inch RETMA card file allowing 16 card positions. The basic Processor
with 128KB of core memory uses 12 card positions and allows three positions for I/O expansion plus one for planned
Processor options.
1. 2 Processor
The basic Processor configuration is Model 8/32 with 128KB memory, Product Number M83-023. Other features such as
parity, additional memory, etc. are optional.
The Model 8/32 uses a technique commonly referred to as "emulation" to implement the standard INTERDATA user
repertoire. This technique requires a micro-processor, or sub-processor, not apparent to the user, employing one or more of
its micro-instructions in sequence to implement one user level instruction. The basic micro-program is contained in 1,280
words of Read-Only-Memory (ROM).
The Model 8/32 employs a 32-bit micro-instruction word and 32 bit internal bussing. The basic instruction time of the
micro-processor is 240 nanoseconds per micro-instruction.
1.3 Control Store
The basic Model 8/32 uses 1,280 words of control store which is mounted on the CPB board. The control store may be
further expanded by the Writable Control Store (WCS). Three user instructions are used for manipulating the WCS.
1.4 Peripherals
The Model 8/32 interfaces to, and is compatible with, all standard INTERDATA peripheral controllers and controllers
designed to the standard INTERDATA Multiplexor Bus. Any number of devices up to 1,024 can be accommodated, but a
maximum of 16 can be interfaced directly to the Multiplexor Bus or to the Selector Channel Bus.
2.
INTERNAL ARCHITECfU.RE
The architecture of the Model 8/32 encompasses a principle of modules communicating over a common bussing system,
directed by instructions from a control memory which specify the module to which an instruction is directed and the
function to be performed. In theory, the function of any module is arbitrary and the significance of various instructions
take meaning only when applied to a specific module. Thus, a computer achieves a capability and personality determined
by what functions can be performed by its complement of modules.
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
2.1 Modules
The Model 8/32 architecture accommodates eight modules which communicate over four Processor busses. The basic
Processor is comprised of three modules.
1.
Central Processing Unit (CPA, CPB, and CPC). The CPU contains the Processor registers. This module
controls the user memory, control memory, register gating, and sequencing of instructions.
2.
Arithmetic Logic Unit (ALU). The ALU provides the basic arithmetic/logical capability of the Processor.
3.
Input/Output Unit (IOU). The IOU provides the I/O capability of the Processor by generating the standard
INTERDATA Multiplexor (I/O) Bus for peripheral communications. It is capable of various byte manipulations of data presented on the busses. In addition, the I/O module contains the Display Console controller,
the Teletypewriter controller, the Power monitor, and the System Initialize circuits.
The architecture accommodates five additional arbitrary modules such as floating point, Boolean manipulators, or special
nature designs.
2.2 Micro-Instructions
The micro-instruction word is 32-bits long. In addition to the branch and write instructions, there are three types of
instructions to the modules. These minimally encoded instructions provide 112 combinations of module/function commands. The micro-instruction can simultaneously direct two operands and a result independently on three of the
computer's busses; generate 12-bit immediate field operands; select the address of the next micro-instruction; perform
encoded micro control of the computer's functions such as reading/writing main memory; incrementing user location and
memory address registers; controlling the user status register; and decoding the next user instruction.
2.3 Interrupts
The Model 8/32 has nine hardware priority interrupts, most of which can be masked by various bits of the Program Status
Word (PSW). The occurrence of a recognized interrupt causes the micro-program to trap to one of nine specific control
store locations associated with the interrupts.
.
2.4 Registers
The Model 8/32 can have up to 8 sets of 16 general registers, of which 15 in each set may be used as index registers. In
addition, there are 16 floating point registers, 8 additional general purpose registers, plus 5 registers associated with the
user level machine control that are available to the micro-programmer.
2.5 Processor Timing
Communications between modules are request/response. Timing' is completely asynchronous (rather than quantized) to
achieve maximum speeds. In addition, interlocks are provided between the control memories and the CPU to facilitate
programming the micro machine. The control module operates on a 120 nanosecond clock, allowing a minimum instruction execution in 240 nanoseconds. Internal timing within the other modules can be selected to best suit the needs of the
module.
.
3.
FUNCTIONAL DESCRIPTION OF THE BASIC PROCESSOR
3.1 Processor Busses
The functional characteristics of the Processor can best be described in terms of its registers, busses and related gating.
There are four busses which are the key to the modular design philosophy of the Model 8/32 architecture. Refer to Figure
1. An understanding of the bus structure is necessary to determine how each module of the Processor interrelates, and how
the registers and gating of each module contribute to the function of the module it is designed to serve.
3.1.1 Control Bus. The Control Bus of the computer is commanded by the control module and is, in essence,
a reflection of that segment of the micro-instruction selecting the function and module to be addressed, plus timing to
effect data transfers. Also included is a means for a module to transfer data to the Condition Code of the PSW. The
Control Bus signals are described in the following paragraphs:
Module Select Lines (MDSELOO:02). These three lines contain the address of a module for which the current
micro-instruction is intended. One of the eight arbitrary modules can be selected by the instruction to perform
some function. These three lines reflect Bits 0:2 of the micro-instruction.
Function Select Lines (FSELOO:03). These four lines reflect Bits 16:19 of the micro-instruction and normally
select 1 of 16 arbitrary functions to be performed by the selected module.
Start (STRT). STRT signals the modules that data on the busses is valid. It is, in effl;;ct, a request from the
control module for a response to a micro-instruction. Data is held static on the A and B Busses while STRT is
active. The control module holds STRT active until it recognizes a response on the Module Finished (MFIN) line
and has stored the results presented on the S Bus.
2
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
S BUS
I
t
USER
MEMORY I
I
REGISTERS
CONTROL
STORE
I
ALU
MODULE
ARBITRARY
MODULE
IOU
MODULE
MUX
PERIPHERALS
BUS
CPU
A BUS
B BUS
CONTROL BUS
Figure 1. Model 8/32 Module Concept
Module Finished (MFIN). MFIN is a response to the control module from a selected module indicating that it
has recognized STRT and completed the selected function. The selected module gates data and other responses
onto the S Bus prior to returning MFIN. The data and responses must be held on the busses until the control
module removes STRT. This time is indefinite and depends on events within the control module.
Module Signal (MSIG). This is a control signal manipulated by the selected module to indicate some arbittary
condition to the control module. It may be tested by the control module during a normal micro-instruction to
the selected device, to control a conditional branch in the micro-program.
Condition Code Bus (SCC, VCC, CCC, GCC, and LCC). SCC signals the control module that the selected module
wishes to manipulate the Condition Code of the Program Status Word. If the micro-programmer has enabled this
manipulation, the Condition Code is forced to a status specified by the selected module. The status is unconditionally forced into the CPU flags. This is done concurrent with a normal instruction to the selected module.
VCC, CCC, GeC, and LCC specify the status forced into CPU flags and the Condition Code of the Program
Status Word, and represent overflow, carry, greater than, and less than, respectively.
3.1.2. A, B, and S Busses. The A, B, and S Busses are the primary data links between the control module and
the selected module. Gating of data to/from each of these busses is controlled by the micro-instruction. Most of the
registers of the control module can be gated to/from these busses.
Data is selected by the micro-instruction from two independent sources and transmitted to a selected module over the A
and B Busses. The module is thus presented simultaneously with two operands. The resulting data is returned to the
control. module via the S Bus. The destination of the S Bus is selected by the micro-instruction.
3.1.3 Typical Bus Exchange. The use of the A, B, and S Busses can be summarized by the following example.
1.
The micro-instruction selects a module (MDSELOO:02) and directs it to perform some function
(FSELOO:03).
2.
The operands are selected from somewhere in the control module and gated onto the A and B Busses.
3.
The control module informs the selected module that all data on the busses is valid and that it may
begin (STRT).
4.
The selected module performs the function (S) = (A) F (B) and gates the results to the S Bus.
S.
The selected module may manipulate the Condition Code via SCC, VCC, GCC, LCC, and CCC.
6.
The selected module may signal, for example, that the result of the operation is zero by activatingMSIG.
7.
The selected module activates MFIN to signal the CPU module that the operation is complete and the
results are presented on the S Bus.
8.
The control module recognizes MFIN, gates the S Bus to the destination specified by the microinstruction, and then removes STRT.
9.
The selected module deactivates itself when STRT is removed.
""----
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
3
3.2 Registers
The following registers are part of the control module.
3.2.1 A Sta"k/B Stack. The A stack and B stack are redundant sets of register banks containing the general
purpose registers of the CPU. The registers are duplicated to allow simultaneous gating of any register in the stack onto
either the A Bus or the B Bus. These registers are gated onto the A and B Busses and are loaded from the S Bus under
control of the micro-instruction.
3.2.2 Memory Data Register (MDR). This register provides the data buffer between the CPU and the user level
memory. The MDR can be gated onto the B Bus and loaded from the S Bus under control of the micro-instruction. It is, of
course, also loaded under control of the memory when a memory read cycle is requested. Hardware interlocks are
employed to synchronize the memory to the CPU.
3.2.3 Memory Location Register (MLC). The MLC is a general purpose register which can be gated to the B Bus
and loaded from the S Bus, and can be incremented by the length of the emulated instruction to facilitate the emulation of
the user level repertciire. This register keeps track of the current instruction location of the emulated machine.
3.2.4 Memory Address Register (MAR). This register contains the address of the user memory that the
micro-programmer is reading or writing. The MAR can be loaded from the S Bus under control of the micro-instruction, or
incremented by four under micro-control. The least significant bit of the MAR is used to control byte steering for the
byte-oriented instructions of the user repertoire (refer to I/O Section ). As in the MDR, timing conflicts are resolved by
hardware interlocks.
3.2.5 Program Status Word (PSW). The Program Status Word is an 18-bit register which may be gated onto the
A Bus and loaded from the S Bus under control of the micro-instruction. Various bits of the PSW are used to enable
associated hardware interrupts. PSW Bits 28 :31 contain the Condition Code of the user level computer. These bits may be
compared and tested against corresponding bits of the user instruction under Module 0 micro-instructions to emulate user
branch instructions. In addition, they can be manipulated by any module designed to do so, if they are enabled by.the
micro-programmer.
3.2.6. User Destination Register, User Source Register (YD, YS). These two control registers store Bits 08: II
and 12: 15 respectively, of the current user level instruction being emulated, and allow the micro-programmer to indirectly
reference the general registers selected by the user instruction. The YD is compared to the PSW Condition Code on certain
micro-instructions to emulate user level branches. These registers can be examined by gating them onto the A and B Busses
under micro-instruction control. The YD can also be loaded from the S Bus.
3.2.7 User Instruction Register (UlR), Memory User Destination Register (UDR), and Memory User Source
Register (USR). These three registers are loaded with Bits 0:7, 8:11, and 12:15, respectively, of the next user level
instruction to be emulated. The 8-bit op-code stored in the UIR is used to vector to the emulation sequence for the next
user instruction. It is also used to interrogate a ROM which has been configured to decode privileged and illegal user level
instructions. The contents of the UDR and USR are transferred to the YD and YS at the beginning of the next emulation.
3.2.8 ROM Location Register (RLR). This register stores the current address of the control store instruction. It
is loadt)d from the ROM Address Gates (RAG) at the beginning of every instruction except interrupt trap instructions and
execute type instructions (explained in the section on micro-programming). The RLR is a 12-bit register allowing direct
addressing of the control store up to 4 K instructions.
3.2.9 ROM Instruction Register (RIR). This 32-bit register stores the current micro-instruction. The RIR is the
focus of control of the CPU.
3.3 Interrupts
The hardware of the computer provides nine priority interrupts. Each interrupt has a unique control store trap location
associated with it. Recognition of an interrupt causes the micro-instruction stored at its respective trap location to be
performed. The RLR contents are preserved to allow the address of the interrupted sequence to be saved, if desired, so that
control can be returned at the completion of the interrupt routine. Certain interrupts are enabled/disabled by bits of the
PSW.
3.4 Control Store Memory
The Model 8/32 can accommodate a maximum of 4K x 32 bits of control store memory. The computer allows data as well
as instructions to be retrieved from its control memory. This capability expands its versatility by allowing data such as sine
tables, translation tables, and matrices to be stored and operated upon efficiently by the micro-programmer.
On models so equipped, the Processor can alter its control store (write into its memory). This capability to store and
retrieve data provides the power of a hardware computer at micro-instruction speeds.
4
This informatIon is proprietary and is supplied by INTER DATA for the lole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
3.5 Micro-programming
The control store of the Model 8/32 is a 32-bit word memory which may be read indirectly by an instruction to retrieve
data, and may be writtpn into by an instruction if it is a writable memory. The basic Model 8/32 contains a 1,280 x 32
ROM array containing the user repertoire and support programs.
The basic instruction format provides the computer with a three address capability, but various options of the repertoire
can modify this to range from two to four. Figure 2 displays the different types of instructions and their modifiers.
The format of the micro-instruction specifies which module is to be addressed, allowing only one module of the computer
to be addressed at anyone time. All other modules must ignore the communications in process. Bits 0:2 of the instruction
selects the module to which the instruction is addressed.
CONTROL INSTRUCTIONS
ADDRESS LINK: FLAGS ARE TESTED AS PER F AND T, RLC--(S)
I F TEST PASSES: XFER TO ADDRESS.
26 27 28
o
3 4 5 6
11
14
o
LIxlTI
REGISTER
o
S
8R~NCH:
3 4 5 6
I
I
F
ADDRESS
MC
FLAGS ARE TESTED AS PER F AND T
IF TEST PASSES: XFER TO ADDRESS SPECIFIED BY (B)
11
14
20
25 26 27 28
MODULE iNSTR-UCTIONS
ROR XFER (A) F (B>-(S) IF C = 1 AND MSIG = 1 XFER TO NEXT INSTRUCTION OTHERWISE
XFER TO PAGE ADDRESS ON CURRENT PAGE
o
3
5 6
11
20
25 26
16
31
S
A
F
PAGE
ADDRESS
B
RR CONTROL (A)
o
3
5 6
S
I
A
RI IMMEDIATE (A) F IMMEDIATE-tS)
3 0. 5 6
11
o
IMODUL~
10
Id
20
16
S
I
A
I
MC
B
F
20
16
31
F
WRITE INSTRUCTION
R WRITE (Al-RAM ADDRESS SPECIFIED BY (B)
o
3
6
11
16
31
252627
IMMEDIATE
I
252627
31
0""
111
111
~~
A
F
20
B
SHOULD BE
NULL SELECTED
A
B
S
F
E
C
I
D
K
U
T
X
SELECTS REGISTER GATE TO A BUS
SELECTS REGISTER GATED TO B BUS
SELECTS REGISTER TO RECEIVE S BUS
SELECTS FUNCTION OF ADDRESSED MODULE
ENABLE SETTING OF CONDITION CODE
I F SET TRANSFER IS CONDITIONAL
B FIELD IS INDIRECT ADDRESS OF DATA
DECODE NEXT INSTRUCTION
FSEL EXTENSION
UNUSED
TESTED F FIELD FOR THE "TRUE" CONDITION
EXECUTE
MC FIELD DESIGNATIONS (MEMORY CONTROL)
0000
NO MEMORY ACTION
0001
INCREMENT MLC BY INSTRUC. LENGTH
0010
PRIVILEGED WRITE HALFWORD
0011
DATA WRITE HALFWORD
0100
NOT lISED
0101
INCREMENT MAR BY 4; WRITE DATA F W
0110
PRIVILEGED WRITE FULLWORD
DATA WRITE FULLWORD
0111
1000
READ HALFWORD AND SET BIT
1001
INCR. MLR BY INSTR. LENGTH; READ INSTR.
1010
PRIVILEGED READ H W
1011
DATA READ HALFWORD
1100
INSTRUCTION READ
1101
INCREMENT MAR BY 4, READ DATA F W
1110
PRIVILEGED READ F W
1111
DATA READ FULLWORD
Figure 2. Control and Module Instructions
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
5
3.5.1 Module O. Module 0 addresses the control module. As shown in Figure 2, instructions are interpreted
differently for Module 0 than the others. In the normal sequence of instructions (e.g., no branches), the hardware of the
control module controls the reading of its memories, and gates the registers specified by the instruction. When it is
addressed by an instruction, it is for the purpose of a conditional transfer. Module 0 does not manipulate the Condition
Code or Processor flag r vgister.
Branch/Execute Instructions. There are two types of transfers recognized by Module O. The most common is the Branch.
The Branch (BR) instruction conditionally transfers control of the CPU to a specified address of control memory and
proceeds sequentially from there. The second type of transfer, commonly called an execute, transfers control to a single
instruction at a specified address of control memory, then normally returns to the original sequence. Any type of
instruction may be executed including additional execute instructions to any depth. However, an execute which results in a
branch does not return to the continuing sequence. Bit 04 of the instruction determines whether the instruction is a branch
or execute type.
Address Link/Register Return. There are two type of Module 0 instructions; address link and register return. They are
selected by the state of Bit 03' of the instruction.
The linked transfer is similar in function to the user level Branch and Link (BAL) instruction, and can be used to transfer
to subroutines when they may be entered from more than one location. The location of the next sequential instruction,
following the transfer, is deposited in the register specified by the Link field of the instruction (Bits 11: 15), and a transfer
is conditionally executed to the effective address.
When the address link is selected, the transfer address is specified by Bits 14: 25 of the instruction.
The register return is used when the transfer address is contained in a register. In this instruction, a branch is taken to the
location contained in the register specified by Bits 20:24.
Conditional Branches. All transfers are conditional upon a state selected by the F field and T field of the instruction. By
selective coding of the F field, either the Condition Code of the user level machine or the status of the CPU can be tested.
The codes are shown in Table 1.
TABLE 1. FUNCTION CODES FOR CPU INSTRUCTIONS
X
T
F
MNEMONICS
"
-
OPERATION.
0
0
110
BAL
Branch and Link Unconditional
0
0
111
BALA
Branch and Link 'and Arm Interrupts
0
1
111
BALD
Branch and Link and Disarm Interrupts
0
0
000
BALZ
Branch and Link on CPU Zero
0
1
000
BALNZ
Branch and Link on Not CPU Zero
0
0
001
BALL
Branch and Link on CPU Less
0
1
001
BALNL
Branch and Link on CPU not Less
0
0
010
BALG
Branch and Link on CPU Greater
0
1
010
BALNG
Branch and Link on CPU not Greater
0
0
101
BALV
Branch and Link on CPU Overflow
0
1
101
BALNV
Branch and Link on No CPU Overflow
0
0
100
BALC
Branch and Link on CPU Carry
0
1
100
BALNC
Branch and Link on no CPU Carry
0
0
011
BALF
Branch and Link if the logical product of user Ml field and User's CC is Zero
0
1
011
BALTF
Branch and Link if the logical product of user M 1 field al"d User's CC is not Zero
0
1
110
BDC
Branch & Mask Console interrupt (no real branch is performed)
6
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTEADATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
3.5.2 Non-CPU Instructions. As stated previously, when the module number is not zero, the CPU does not
operate on the instruction, and the fields are interpreted differently. The module field (Bits 0 :2) and the F field (Bits
16: 19) are interrogated individually by the other modules. There are four types of non-CPU instructions selected by Bits 3
and 4 of the instruction. They are:
I.
RRX. The RRX is a Register-to-Register and Transfer instruction. It is effectively a four-address instruction in that it gives the register address of the two operands, the register address for the results, and the
location for the next sequential instruction.
The two operands are addressed by the A field (Bits 11: IS) and the B field (Bits 20 :24). The contents of
these two registers are gated, respectively, to thl' A Bus and B Bus of the computer.
The S field (Bits 6: I 0) selects the destination register to which the results are gated from the S Bus.
The page address field (Bits 26: 31) selects the low order address of the next instruction. The high order
bits are taken from the current location address. The C field (Bit 25) being true makes the transfer
conditional upon a signal returned by the addressed module at the completion of the instruction. (The
ALU, for example, returns the Carry flag as its signal.) If the module signal, which is designated MSIG, is
true, and Bit 25 of the micro-instruction is true, the branch does not occur, and the next sequential
instruction is executed. Any other condition causes the transfer to be effected.
2.
RRC. The RRC is a Register-to-Register Control type instruction. The interpretation of the instruction
fields is identical to that of the RRX, with the exception of Bits 25 :31 which contained the page address
within a RRX instruction. Bits 25 :31 of the RRC instruction provide the micro-control of the CPU and
are described in Section 3.5.3.
3.
RIM. The RIM instruction provides an immediate field for ease of generating constants and bit masks.
Immediate, is the term generally used to infer that the immediate contents is the actual operand rather
than the address where the operand is found. This 12-bit immediate 'field (RIR 20:31) is converted to a
16-bit operand by extending the sign bit (RIR 20) when gating onto the B Bus. The S field and A field of
the instruction are interpreted identically to that of the RRX and RRC instructions.
4.
RWT. The RWT is the Store or Write instruction of the repertoire if the CPU is equipped with a writable
control store. There are several notable differences pertaining to this instruction.
-Although the module number cannot be zero, it may be any other, as the CPU never communicates with
the other modules.
- The S field is not interpreted and should be null selected.
- The F field is not interpreted.
- The B field addresses the register containing the address to be written into.
- The A field addresses the register containing the data to be stored in control store.
Bits 25 :31 of the RWT instruction are interpreted as a control field, as in a RRC instruction.
3.5.3 Micro-Control (MC). To facilitate the emulation task of the CPU, certain instructions allow an order of
micro-control within the CPU. The instructions possessing this capability are the Module 0 (RRC and RWT) instructions.
MC Field. The MC field is the user memory micro-control which allows various controls over the user memory
instruction Location Counter (MLC), the user Memory Address Register (MAR), and the reading and writing
of the user memory. The significance of the bits of the MC field are shown in Table 2.
There are certain hardware connotations to the MC operations which are not made apparent by Table 2. They are:
-
I.
The micro-control specified by the MC field is conditional when used within Module 0 instructions. The
read memory is only effected if the operation does not result in a transfer. (This conditioning is used to
expedite the emulation of the user branch instruction.)
2.
All of the micro-control is effected before the STRT occurs with the exception of data read and data
write. This control is effected after completion of the instruction, which allows the micro-programmer to
use the MAR or MDR as a destination and begin a read/write data immediately. It also allows the
execution of the increment and the addressing of the MAR as the destination register simultaneously,
which has functional utility.
This information is proprietary and is supplied by INTER DATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
7
D Field (Decode Instruction). The D field bit informs the CPU to halt the sequential flow of microinstructions and begin to emulate the next user instruction. The Operation-Code (op-code) field of the new
user instruction is in the UlR and provides a vector to a control store address where the emulation sequence
begins. This implies that the micro-programmer must have done an instruction read in the current or a prior
instruction using one of the proper MC field designation'S. The execution of a decode is conditional when used
within Module 0 instructions, and, like the instruction fetch, is only performed if the operation does not
result in a transfer.
E Field. This field is used to Enable (E) or disable changing of the Condition Code (CC) of the PSW. When
changing is enabled, the Condition Code is changed under control of the module addressed until again disabled
by this field. (The ALU, for example, jams its C, V, G and L flags into the Condition Code upon completion
. of its function.) The meaning of the Condition Code is a function of the module addressed. Flags are disabled
at the beginning of an emulation sequence.
K Field. The K field of the micro-instruction is an extension of the F field of the instruction. It is available
only on the RRC and RWT instructions and constitutes the Control Signal (KSIG) to the modules. Its
meaning, just as the F field, is defined by the module addressed by the current RRC instruction. The ALU, for
example, reinterprets shifts to be halfword when KSIG is active. It is also used to extend the functions of the
I/O module.
TABLE 2. Me FIELD
,
BITS
MEANING
28
29
30
31
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
No Action
IL
PW2
DW2
No Action
14DW4
PW4
DW4
RAS
ILiR
PR2
DR2
IR
14DR4
PR4
DR4
Increment LOC by Instruction Length
Privileged Write Halfword (two bytes)
Data Write Halfword
Increment MAR by 4, Data Write Fullword
Privileged Write Fullword
Data Write Fullword
Read Halfword and Set Sign Bit
Increment LOC by Length and Read Instruction
Privileged Read Halfword
Data Read Halfword
Instruction Read
Increment MAR by 4, Data Read Fullword
Privileged Read Fullword
Data Read Fullword
IL
The Location Counter (LOC) is incremented by the length in bytes of the last user level instruction fetched.
PW2
The Memory Access Controller (MAC) is disabled and the halfword in MDR (Bits 16:31) is written into the addressed
location.
DW2
The halfword in MDR (Bits 16:31) is written into the addressed location. MAC is not disabled.
14DW4
The Memory Address Register (MAR) is incremented by four, then the fullword in MDR (Bits 0:31) is written into
the location addressed by MAR.
PW4
The MAC is disabled and the fullword in MDR (Bits 0:31) is written into the addressed location.
DW4
The fullword in MDR (Bits 0:31) is written into the addressed location.
RAS
The halfword at the addressed location is read then re·written with Bit 0 of the halfword set. The original value of the
halfword replaces MDR Bits 16:31. Bits 0:15 of the MDR are set equal to Bit 16 of MDR (sign extension).
ILiR
LOC is incremented by the length in bytes of the last user instruction fetched, then an Instruction Read is started from the
address specified by the new value of LOC.
PR2
The MAC is disabled and the halfword at the addressed location is read and copied to MDR Bits 16:31. Bits 0:15 of MDR
are set equal to MDR Bit 16.
DR2
The halfword at the addressed location is read and copied to MDR Bits 16:31. Bits 0: 15 of MDR are set equal to MDR Bit 16.
IR
An Instruction Read is started from the memory address specified by LOC.
14DR4
MAR is incremented by four, then the fullword at the location addressed by the new value of MAR is read and copied to MDR.
PR4
MAC is disabled, then the fullword at the location addressed by MAR is read and copied to MDR.
DR4
The fullword at the location addressed by MAR is read and copied to MDR.
8
This information is proprietary and is supplied by INTER DATA for the IOle
purpose of using and maintaining INTEADATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in Writing.
3.5.4 Control Store Data Storage. Data may be retrieved from the ROM or the Dynamic Control Store (DCS)
during execution of RRC, RRX, or RIM instructions when the I field bit (instruction Bit 5) is true. When the I field bit is
set, the data addressed onto the B Bus is used as the store address of the ROM or DCS, and causes the CPU to replace this
data with the addressed data before signaling the addressed module to begin its task.
3.5.5 Interrupts. The hardware of the computer provides nine priority interrupts. Each interrupt has a unique
trap location associated with it. Recognition of an interrupt causes the instruction stored at its respective trap location to
be performed. The RLR contents are preserved to allow the address of the interrupted sequence to be saved, if desired, so
that control can be returned at the completion of the interrupt routine. Certain interrupts can be disabled by bits of the
PSW as designated in Register Peculiarities and Tables 3 and 4. In addition, all interrupts can be enabled/disabled as a group
by a micro-instruction. All interrupts not masked by PSW bits are interrogated when a new user level instruction is
decoded, regardless of the status of the group enable. The group enable is automatically disabled at the beginning of a user
emulation, and must be enabled by instruction if the programmer wishes to recognize interrupts. Tables 3 and 4 list by
priority the pertinent information for each interrupt.
TABLE 3. INTERRUPT TRAPS
TRAP ADRS
(HEX)
INTERRUPT
Memory Access Controller (Instruction)
Memory Access Controller (Data)
Primary Power Fail
Machine Malfunction
Display Panel
External Interrupt Level 0
External Interrupt Level 1
External I nterrupt LeVEll 2
External Interrupt Level 3
Illegal Instruction
Privileged Instruction
1FE
207
206
205
204
203
202
201
200
208
208
GROUP
ENABLE
MASK
PSW21
NO
NONE
PSW18
NONE
YES
YES
YES
See
Table
3
NONE
PSW23
YES
N/A
N/A
PSW Bits 17 and 20 define the external I nterrupt enable status of the Processor as shown below:
PSW
BITS
17
20
0
0
1
1
0
1
0
1
All Levels Disabled
Higher Levels Enabled
All Levels Enabled
Current and Higher Levels Enabled
where the current level is a function of the currently active register set. See Table 4.
TABLE 4. EXTERNAL INTERRUPT ENABLE
EXTERNAL INTERRUPT ENABLED
PSWBITS
l.,EVELO
LEVEL 1
. LEVEL 2
LEVEL 3
17 20
25
26
27
0
0
X
X
X
NO
NO
NO
NO
0
1
0
0
0
NO
NO
NO
NO
0
1
0
0
1
YES
NO
NO
NO
0
1
0
1
0
YES
YES
NO
NO
0
1
0
1
1
YES
YES
YES
NO
0
1
1
0
0
YES
YES
YES
NO
0
1
1
0
1
YES
YES
YES
NO
0
1
1
1
0
YES
YES
YES
NO
0
1
1
1
1
YES
YES
YES
NO
1
0
X
X
X
YES
YES
YES
YES
1
1
0
0
0
YES
NO
NO
NO
1
1
0
0
1
YES
YES
NO
NO
1
1
0
1
0
YES
YES
YES
NO
1
1
0
1
1
YES
YES
YES
YES
1
1
1
0
0
YES
YES
YES
YES
1
1
1
0
1
YES
YES
YES
YES
1
1
1
1
0
YES
YES
YES
YES
1
1
1
1
1
YES
YES
YES
_ YES
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
9
3.5.6 Registers. The basic CPU has up to 8 sets of general registers each containing 16 user registers, 16 floating
registers, and 8 general purpose registers for use by the micro-programmer. In addition, the bulk of the remaining CPU
registers is also available to the micro-programmer.
A register is available to the micro-programmer if he can address it to one or more of the internal busses. Table 5 tabulates
the addressable registers and their respective address on the designated bus. Also listed are register mnemonics, descriptions, and the register peculiarities.
TABLE 5. REGISTER ADDRESSING
BUS ADDRESS (HEX)
S BUS
B BUS
A BUS
OO:OF (16 General Registers)
URn
URn
URn
10:17
MRn
MRn
MRn
18
YS
YS
YS
19
YO
YO
YO
1A
MLC
MLC
YX
1B
MDR
MDR
YDP1
1C
MAR
EFFECTIVE ADDRESS
10
PSW
YSI YO
1E
YDD
YDI YSI
1F
NULL
PSW
NULL
NULL
Register Mnemonics and Descriptions.
10
MNEMONIC
REGISTER
COMMENT
UR
User General Registers
16 registers manipulated by emulated
language
MR
Micro-level General Registers
8 additional GP registers available to
the micro-program
PSW
Program Status Word
16 bit register containing interrupt
enables and flags
MDR
Memory Data Register
MLC
Memory Location Counter
MAR
Memory Address Register
NULL
No register selected
Gates 0 to A and B Busses, S Bus data
is lost
YS
User Source Register
Register selected by Bits 12: 15 of
emulated instruction (contents of
USR)
YSI
User Source Register Immediate
Bits 12: 15 of the emulated instruction
(USR) gated onto B Bus
YX
User Index Register
Same as YS except NULL gated to A
Bus if field is 0 (contents of USR=O)
YD
User Destination Register
Register selected by Bits 8: 11 of
emulated instruction (contents of
UDR)
YDI
User Destination Register Immediate
Bits 8:11 of the emulated instruction
(UDR) gated onto the A Bus
YDP1
User Destination Register Plus 1
Register selected by Bit 8: 11 of
emulated instruction +1 (must be
odd)
YDD
User Destination Register Direct
S Bus 12:15 replaces UDR contents
Location
program
Counter
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
of
emulated
Register Peculiarities. The last four bits of the PSW contain the Condition Code of the emulated computer. In general,
these bits can be manipulated by any addressed module unless the PSW is the S Bus destination or their change has been
inhibited by the micro-instruction. The individual bits of the PSW which have hardware implications are:
PSW 17, 20, 25:27
PSW 18
PSW 23
PSW 25:27
PSW28
PSW29
PSW30
PSW31
ATN interrupt enable and level selection
Machine Malfunction enable
Privilege instruction/Memory Protect enable
User register set selection
C flag of Condition Code
V flag of Condition Code
G flag of Condition Code
L flag of Condition Code
The following additional registers have the indicated capabilities and connotations.
1.
The MDR receives data asynchronously from memory. It is used in the address calculation for RX3
instructions.
2.
The MDR, MAR, and MLC being addressed cause the Processor to interlock with memory when they are
the source or destinations of the current instruction and the Processor is requesting memory service.
3.
The MAR and MLC can be incremented by the micro-control.
4.
The MLC is used in the address calculation for RX2 instructions.
3.5.7 CPU Hags. The CPU contains a flag register which is independent of the PSW flags and is manipulated by
any module which attempts to affect the PSW Condition Code by activating the SCC control line of the CPU Control Bus.
When the SCC control line is active, the state of the VCC, CCC, GCC and LCC are unconditionally jammed into the CPU
flag register and conditionally into the PSW Condition Code. The changing of the PSW is controlled by the microprogrammer by the E field of the micro-instruction. The state of the CPU flags can be individually tested by the Module 0
instructions.
3.5.8 Arithmetic Module' (ALU/FALU) Programming. The Arithmetic Logic Unit (ALU) is a standard module
in the Model 8/32 hardware. It is addressed as Module I in the module field of the instruction for fixed point operations,
as Module 3 for floating point operations, and is capable of 27 functions. Refer to Table 6. Communication with the ALU
is asynchronous. By design, the ALU is never busy and for the majority of ALU functions, response is within 120 nanoseconds. (This allows most ALU referenced instructions to be completed in 240 nanoseconds.)
,,--,-'
TABLE 6. MODULE 1 (FIXED POINT) AND MODULE 3 (FLOATING POINT) OPERATION
MODULE' (FIXED POINT)
F FIELD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,
,
,
,
0
0
0
0
0
0
0
0
, ,
,
Subtract
Not used
Add
Load
0
Subtract with Carry
Subtract With Carry
Add With Carry,
Add With Carry
Not used
Not used
Logical AND
Compare
Logical Exclusive OR
Not used
,
, ,
,
,
, ,
,
,
, ,
,
,
, ,
,
,
,
, ,
, ,
, ,
0
0
0
0
0
0
MODULE 3 (FLOATING POINT)
0
0
0
Logical OR
Not used
* Logical Shift Right
Subtract
* Logical Sh ift Left
Add
Rotate Right
Not used
Rotate Left
Not used
* Arithmetic Shift Right
Compare and Equalize
* Arithmetic Sh ift Left
Not used
Signed Multiply
Multiply
Signed Divide
Divide
* When used in conjunction with the K bit of the R RC instruction, shifts are halfword ('6 bits).
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
11
For functions which require more than one ALU cycle (Le., shifts, rotates, and multiply/divide), the ALU does not
respon<;i with a finish signal until the completed results are on the S Bus.
Multiply/divide can be performed only on the 24 general registers and must address the same register pair on both the A
and S Busses. The samt: restrictions that apply to these operations at the user level must be adhered to at the micro level.
A user emulated multiply/divide instruction is micro-coded by selecting the ALU (Module 1); addressing the UDR on the S
Bus, the UDRPI onto the A Bus, the USR onto the B Bus, and the required function code for the operation. When the
ALU signals its completion, the results have already been deposited in the UDR.
To implement a shift or rotate instruction, the register to be manipulated is addressed onto the A Bus, the shift count is
put onto the B Bus (27 :31), and the S Bus is gated to the destination register.
The ALU generates valid CPU flags for all instructions except multiply/divide. The C flag is gated as MSIG.
3.5.9 I/O Module Programming. The I/O module performs a multiplicity of functions. In general, it is addressed
to communicate with the multiplexor channel. It has the additional capability of performing byte manipulations for the
CPU both in conjunction with an I/O exchange and without one. Furthermore, the I/O module contains the Machine
Control Register (MCR) which stores machine trouble conditions and interrupts the CPU. The contents of the MCR can be
sensed, tested and cleared. Module Number 2 has been assigned to the I/O module.
Multiplexor Channel. The Multiplexor Channel, generated on the I/O module, is operationally identical to the
standard INTERDATA Multiplexor Bus in all respects. The Multiplexor Bus is a byte or halfword-oriented I/O
system which communicates with up to 255 peripheral devices.
A single instruction from the CPU contains the device address, the encoded function, and up to 16 bits of
output data when needed. The Multiplexor Bus generator provides single or multi-cycle operation to address
the device, transmit the decoded function, send or receive over 16 bi-directional data lines, and synchronize
the exchange.
The normal byte or halfword operation consists of an address cycle and a data cycle. However, during a
Read/Write block sequence, the address cycle is not used. For halfword functions (RDH/WDH) with a byte
oriented device controller, two data cycles are used to transfer the halfword.
Byte Manipulation. The I/O module has the capability of performing byte manipulation both in conjunction
with an I/O operation and without one. The byte steering is under control of the least significant memory
address bit in the MAR and also the KSIG line. For halfword operations, this manipUlation is inoperative but
the double data cycle with packing/unpacking results when the Halfword (HW) Test line is inactive.
I/O Module Function Codes. The encoded I/O module functions and the byte manipulations are described in
Section 3.7.3.
.
Machine Control Register (MCR). The Machine Control Register (MCR) consists of four flip-flops, four straps,
and the Console Attention (CATN) and SNGL leads from the Display controller. MCR bit assignments are:
BIT
MNEMONIC
MEANING
15
14
13
12
11
10
09
08
07
05
04
EPF
IRLMP
DMPF
IA/STF
STF
CATN
RSET
spare
SNGL
BNKB
BNKA
Early Primary Power Fail
Instruction Read Local Memory Parity Fail
Data Memory Parity Fail
lllegal Address and/or Start Timer Fail
Start Timer Fail
Console Attention flip-flop (from Display Controller)
Register Sets Available
spare
(strap)
SNGL flip-flop (from Display Controller)
Bank B
(strap)
Bank A
(strap)
The IRLMP and DMPF flip-flops store signals received from the Memory Bank Controller (MBC). Signals to get the EPF
and STF bits are generated on the IOU board by the Power Monitor and Start Timer circuits. The composite bit (MCR12)
can be strapped to represent lA, STF, or both. MCRII is always set by STF. The testable straps are wired for logical ONE
or ZERO as required. A Machine Malfunction (MMF) interrupt is generated when any of Bits 12, 13, 14 or 15 are true. The
SMCR function gates MCRI2: 15 to the CC Bus, MCR08: 15 to S08: 15, and MCR04:05 to S04:05. The CMCR operation
clears MeRl1: 15 where there are ONES in B11: 15. This permits selective clearing of some bits while the rest of the MCR
continues to monitor other machl.ne functions without loss of data.
ThiS information is proprietary and is lupplied by INTER DATA for the sole
12
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
Start Timer (STRT). A 35 microsecond timer is started by the STRT signal and cleared by the MFIN signal
from any selected module. Should the timer run out before the MFIN signal arrives, a malfunction exits; Le.,
non-existant module. circuit trouble. or no SYN return from the Multiplexor Channel. If a D Bus function was
called for, the False SYNC code (OIOO/CVGL) is placed on the CC Bus and a pseudo MFIN signal is sent to
restart t\le CPU clock. Also, S16:3l is forced to X'0004' if the function required is of the Sense Status type.
For a non-D Bus operation, the Start Time Fail (STF) bit is set in the Machine Control Register (MCRll), and
a pseudo MFIN signal is sent to restart the CPU clock. If STF is strapped into MCRI2, the MMF interrupt is
also generated.
3.6 Processor Block Diagram Analysis
3.6.1 CPU (Figure 3). The architecture of the Processor is structured about four busses which provide intercommunication between the CPU and the remaining modules.
The CPU selects the module via the Control Bus (C Bus), specifies the function, and signals that data is available on the A
and B Busses. The addressed module signals when it has completed its function and transmits flag type data back over this
bus.
The A Bus and B Bus contain the two operands offered simultaneously to the addressed module to be manipulated. Most
of the CPU registers can be gated onto the A and B Busses.
Data from an addressed module is returned to the Processor via the S Bus.
The ROM Instruction Register (RIR) is a 32-bit register that latches the current instruction read from the control store
memory to provide the control gating for each instruction. Data can also be gated from the RIR onto the B Bus. for
indirect data fetches. One of the many functions performed by the encoded instruction is register gating. This is performed
by the select logic to encode the A, B, and S SEL lines, these lines determine which registers are gated onto the A and B
Busses, and which register is the S Bus destination.
The Control Store Address gates (CSA) select the address of the control store to be interrogated next. Inputs to the CSA
may be the ROM Location Counter (RLC) to select the next instruction, certain bits of the RIR for branching, the B Bus
for indirect addressing or branches, the translated vector for the next user instruction to be emulated (XLTR), or interrupt
trap address from the interrupt logic.
The ROM Location Register (RLR) preserves the address of the current instruction. It is loaded with the address of the
current instruction every time the RIR is loaded, except when the instruction is an interrupt or execute type which do not
alter the ROM Location Register. The RLR is gated to the RLC to.perform RLR+l for the next sequential instruction.
The general user registers and the 8 general micro-registers are contained in the A stack and B stack. This is a redundant
pair of registers, implemented as such to allow gating of any two registers of the machine simultaneously onto both the A
Bus and B Bus. Gating of these stacks is controlled by the A, B, and S SEL lines, just as the other A, B, and S source and
destin~tion registers.
The Program Status Word register (PSW) is an architectural feature of the user level machine. Certain bits of the PSW are
used to mask interrupts, control the privileged mode of the Processor, and to contain the Condition Code of the user level
program. This register can be gated to the A and from the S Busses. The Condition Code portion can also be loaded
independently of the register addressing.
The Memory Location Counter (MLC) aids the emulation capability of tht: Processor. It is used to contain the memory
location of the current user level instruction. In addition to being capable of being gated to/from the Band S Busses, this
register may be incremented by the length of the last emulated user instruction under micro-control of the programmer.
The Memory Address Register (MAR) contains part of the address to be used by the main memory for a read/write
operation. This register can be loaded from the S Bus, and may also be incremented by micro-control of the programmer.
The manipulation of this register is interlocked with the memory operation by hardware to remove timing restraints from
the micro-programmer.
The Memory Data Register (MDR) is loaded from the S Bus with data to be written into the main memory, or it is loaded
from the Memory Data Bus with the contents of the addressed memory on a memory read operation. This register may be
gated onto the B Bus of the Processor, and, like the MAR, hardware interlocks remove the timing considerations of the
memory system from the micro-programmer when this register is referenced.
The User Instruction Register (VIR) stores the 8-bit op-code of the next user instruction to be emulated. It is loaded from
memory when a Read operation is designated as an instruction fetch by the micro-code. The 8-bit op-code is translated to
a vector which designates the beginning address of the emulation sequence for a particular instruction. The 8-bit op-code is
also gated to a Privileged/lllegal ROM which is coded to detect these types of instructions and cause an interrupt to the
Processor.
This information is proprietary and is supplied by INTERDATA for the IOle
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
13
The memory User Destination Register (UDR) and memory User Source Register (USR) store the destination and source
fields of the next instruction to be emulated when it is read from memory. This data is transferred to the User Destination
Register (YDR) and User Source Register (YSR) at the beginning of a new emulation sequence to provide residual control
for the instruction.
.
Memory Control is effected by the micro-control field of the micro-instruction. The ability is provided to cause data read,
data write, and instruction read.
3.6.2 ALU. The ALU is a standard module of the Model 8/32 and provides the basic arithmetic/logic capability.
It communicates with the CPU over the A, B, S, and C Busses in a manner identical to other modules.
The ALU becomes active when it recognizes its address on the Control Bus (Module Number I or 3), and the CPU signals
start (STRT). The function to be implemented is determined from the Control Bus.
ALU functions may be of two types. The simple functions (add/subtract and logical) cause the ALU to immediately return
a Module Finished signal (MFIN). For these type of instructions, the A and B Busses are gated through the ALU, and the
required function is· performed and gated onto the S Bus.
For the complex type functions (multiply/divide, shift, and floating point) the ALU clock is enabled and a hardware
sequence is entered to perform the required operation. The shift gates are used to shift the A Bus or the Sum Bus right or
left back into the A latch and onto the A Bus again as determined by the ALU algorithms. In the case of fixed point
multiply/divide the ALU stores half of the completed results before signaling the CPU with MFIN. The other half is
dumped onto the A Bus from the MQ register and gated through the ALU onto the S Bus when MFIN is activated.
3.6.3 IOU Board. (Refer to the Block Diagram in IOU section.) The IOU board contains the I/O Control, the
Display controller, the TTY controiIer, the Machine Control Register (MCR), the Power Monitor, Initialize circuits and the
Start Timer.
The Display and TTY controllers have access to the CPU via the Multiplexor Channel D Bus and the I/O Control in the
same manner as other peripheral device controllers. The Display controller provides a visual display of the contents of all
system registers and any main memory location, together with the capability of manually entering data and programs. It
shares D BUs drivers/receivers with the TTY controller and signals the CPU directly with the Display (DSPLY) interrupt.
The Console Attention (CATN) signal appears as Bit 10 of the MCR.
The TTY controller, which supports the Model 33/35 Teletype, provides serial/parallel conversion and all standard TTY
control features. It contains a full character buffer in the receive mode to permit a program service interval of one
character time (100 milliseconds). The detailed descriptions of the Display and TTY controllers are covered in Sections 12
and 13 respectively.
I/O Control. The I/O Control performs a multiplicity of functions. The main function is to generate Multiplexor Channel D Bus from the CPU busses whenever it is addressed by Module Number 2 and the proper
function selections are made. The control also performs byte manipulation for the CPU both in conjunction
with an I/O operation and without. Common function decoders also generate signals to sense/clear the MCR
(which stores Machine Malfunction conditions), to set the system Stop flip-flop with a Power Down/Initialize
function (FPOW), and to gate 4-bits of the B Bus (12: 15) to the front terminal strip of the chassis for
external signaling purposes; e.g., multi-CPU operations.
Four function select lines together with the KSIG line pick 1 of 32 possible functions as shown on Table 7.
TABLE 7. I/O CONTROL FUNCTIONS
FSELOX
0
1
2
3
4
5
6
7
8
*
14
FUNCTION
0
1
2
3
KSIG=O
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RD
WD
SS
OC
RDH
WDH
ACK
*SMCR
RDA
WDA
9
SSA
A
OCA
B
RDHA
C
WDHA
D
*THW
E
*POW
F
Functions that do not require operation of the Multiplexor Channel D Bus.
This information is proprietary and is supplied by INTEADATA for the sale
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
KSIG=l
RDR
WDR
SSR
OCR
*STBR
*LBR
*LDWAIT
*CMCR
RDRA
WDRA
SSRA
OCRA
*STB
*LB
*EXB
*PQUT
~
dI
CD BUS- 32
I
8
b CMC-3
6
!3
a
CABUS-19
i
19
;.
Ig"
~
!"
i3:
P/I ROM
AND
INT. TRAPS
8
RIR
~
RLR
CONTROL .........._--1
STORE
12
t12
3t1 1' i
c;l~
USR
/4
i
RAG
YS
12 .L
~
I--f-
RLC
I
32
1 32
12
12
STATE
COUNTER ~I.~----~----~--------~
CLOCK
f'
I
4
l
~
..i
UIR
12
3~c
..-;
..
Y H-t
20.
MAC
TI
}
A/B/S
.L
J
1
15
I
SELECT
14
hCONTROL
BUS(MSE L1FSE L/MFI N/MSI~
UJ
~
SX2
.--
'---
BOO)'ZSUMO-ALOO
MQOO:30-MQOI:31
S31-MQOO
{
ALOO:30-ALOI :31
ifMO
ALOO-ALOO
MQOO:30-MQOI:31
AL3I-MQOO
ALOO:31-S00:31
MQOO:3 I-+ALOO:3 I
if GRWCO, AS031 -ASO 11
ASOII
ALOO:31- SOO:31
MFIN_I
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
51
Fixed Point Divide
The Fixed Point Divide algorithm is implemented by subtracting the divisor from the shifted dividend to determine if it is
greater or not. If the dividend is determined to be smaller than the divisor, the quotient digit for that test is made to be a
zero, and the dividend ;0 shifted left again to repeat the process. If the dividend is determined to be larger, the quotient
digit for that test is made to be a, one and the difference, shifted left, is stored as the new dividend. In the implementation
of signed divide, if the two operands are of unlike signs, the subtraction is performed by the addition of the unlike
operands and the I's complement of the quotient is accumulated. When the complemented quotient is formed, it is
corrected to the 2's complement in ASOll.
An obstacle in performing signed division using complementary arithmetic arises when the intermediate dividend is a
negative number and both the intermediate quantities (the absolute value of the dividend - divisor) and the remainder equal
zero because the logic does not detect the quotient digit of 'one'. When this case arises, the computed result = true
quotient -I, with the remainder equal to the divisor. To detect this case, a flip-flop (RZRO) (7FI) monitors this condition
and causes a correction cycle in ASOII.
Because of the difference in sc;tling of the divisor (2 63 ) and the dividend (2 31 ) and the fact that both the quotient and
remainder must be scaled (2 31 ), an extra division cycle is performed in AS031 to compute Q31. To properly scale the
remainder, the last summation is inhibited from shifting. Moreover, if the absolute value of the Q31 digit is 'I', the correct
remainder is on the S Bus during the first cycle of AS031 and remains there throughout AS031. Should the absolute value
of the Q31 digit be '0', the correct remainder is in the AL register, and ALU control is modified to force the transfer of AL
to the S Bus.
The least significant portion (remainder) of the result is written into the destination register in AS031, and the most
significant portion (quotient) is written into its destination register in ASOll.
The algorithm for Fixed Point Divide is:
AOO:31-MQOO:31
GRWC-O
if AOOeBOO, SUMO-l
if ~OOEaBOO, SUMI-I
O-ACNTOI :()5
O-RZROI
AOO:3 I-ALOO:3 I
ASOOI-AS02I' ,
if (FSTCNTl andIQI=l), DFLT-l
if ACRYI, AS021-AS031
ACNT
~
if SUMO,
I-ACNT
(AL~B)
if SUMI, (AUB)
!
1_MQ31
ifCOUTOOOe,BGOOI MQOI:31-MQOO:30
MQOO-AL31
ALOI :31-ALOO:30
O-MQ31
ifCOUTOOOEaBGOOI {MQOl:31-MQOO:30
MQOO-AL31
. 01:31-ALOO:30
52
This information is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
if SUMO, AL t:,. B
ifSUMI, AL
~
B
{
if COUTOOO EE>BGOOI
1-MQ31
MQOl :3l-MQOO:30
ifCOUTOOOEE>BGOOl {0-M Q3l
MQ01:3l-MQOO:30
if (MQ3l (9AXBl )'SUMO, (ALt:,.B)-SOO:31
if (MQ31 EE>AXBl)'SUM1, (AUB)-SOO:31
ifMQ31
ffi AXB 1, ALOO:3l-S00:3l
MQOO:3l-ALOO:3l
ifGRWCO, AS031-ASOll
ALOO:3l-S00:31
MFIN-l
Compare and Equalize
The Compare and Equalize instruction is always performed prior to a floating point Add/Subtract. The instruction
effectively aligns the exponents of the two operands by shifting the mantissa of the smaller operand.
To simplify the logic for determining the larger operand, BOO is inhibited (forced to a one) during ASOOI. The difference
of the two operands is taken (A-B), and the BGTR flip-flop (6C2) is loaded with the information (SBGTR1) determining
the larger operand. The logic for this determination (303) is:
SBGTRI = AOOI E9BOOI $SOOI
but since BOOI = 1,
SBGRTl = A000E9S001
If the BGTR flip-flop is set, B is the larger operand and A is shifted, or if BGTR is reset, A is the larger operand and B is
shifted. The exponential difference is computed simultaneously and this result becomes the hexadecimal shift count.
However, if this shift count exceeds 510, the operation is abandoned as significance is shifted out of the mantissa, the
result b'eing zero. The four bit magnitude comparator (812) compares the exponent difference to 510 and XOVFl (8N4)
determines if the shift count is less than 510. One additional problem occurs if the exponent of B is greater than the
exponent of A. The difference results in a 2's complement number and does not reflect a true shift count. Should this
occur, OCMPI (807) is active and complements the difference and inhibits ACNT for one shift cycle in AS021, yielding
the correct number of hexadecimal shifts.
During AS02l, either the A or B Bus is inhibited (forced to all ones) and a subtraction is performed. The net result is to
transfer the operand which is to be shifted into the AL register. Thereafter, the operand is shifted hexadecimally to the
right according to the shift count. When the shift is complete (ACRY1), the transition is made to ASOII where the result is
gated to the S Bus with the sign and exponent field zero filled. When the Add/Subtract instruction follows, the CPU always
gates the larger operand onto the A Bus and the shifted operand to the B Bus.
The algorithm for Floating Point Compare and Equalize:
SUMO-l
BGOOl--l
MB
AO 1:07 t:,.B0 1 :07
FXS05:07-ACNT05:07
if XOVFO, ASOO l-AS021
if XOVFl, ASOO l-ASO 11
This information is proprietary and is supplied by INTEROATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
53
AS021
if ACRYl, AS021-ASOll
if OCMPLl , ACNT-ACNT
{ ifOCMPLO, ACNT
~I-ACNT
ifBGTRl, AOO:31-ALOO:31
if FSTCNTI
ifBGTRO, BOO:3t-ALOO:31
ACNT ~ l-ACNT
{ 0-AL08:11
if FSTCNTO
AL08:27-ALl2 :31
ASOll
if XOVF1, O--SOO :31
ifXOVFO, 0-SOO:07, AL08:31--S08:31
MFIN--I
Floating Point Add/Floating Point Subtract
One additional characteristic of floating point arithmetic beyond that discussed in the Compare and Equalize algorithm
arises from floating point notation. The mantissa is represented by sign and magnitude. Positive numbers have a Sign bit
equal to zero and negative numbers have a Sign bit equal to one. However, unlike fixed point notation, negative numbers
are not represented in 2's complement format. Therefore, when performing an addition with unlike signs, a subtraction
must be performed to obtain the true sum. Similarly, when performing a subtraction with unlike signs, to obtain a true
difference an addition must be performed. This is accomplished by the FAXBI address bit to the ALU ROM. The FAXBI
flip-flop (9N6) is set during AS021 of the Compare and Equalize instruction and the logic for this bit is A001 EEl BOO 1.
In ASOOI, the mantissa's of A and B are added/subtracted and the exponent of A is presented to the exponent up/down
counters. If adding (SUMI), it is possible to overflow the resultant mantissa (COUT081) and a correction cycle is executed
in AS061. If subtracting (SUMO), it is possible that the result may not be normalized and a normalize shift is executed in
AS061. Should neither of these conditions arise, the transition to AS011 is direct and the result is gated to the CPU.
The algorithm for Floating Point Add is:
AS001
if FAXBO, SUM1-I,
A~B
if FAXB1, SUMO-I, MB
AOl:07-XSOl :07
SOO:31-ALOO:31
ifNRLZO·ZSUMO + COUT081·SUM1, ASOOl-AS061
if (NRLZI +ZSUM1 )·SUM1·COUT080, ASOO 1--ASO II
AS061
if SUMO{0-AL28:31
ALl2:31-AL08:27
0-AL08:1O
ifSUMl
{
I-ALl 1
AL08:27-ALl2:28
if NRLZ I, AS061-ASO 11
AS011
if ZSUM1, o-SOO:31
AL08:31-S08:31
{
if ZSUMO XS01:07--S01:07
AOO--SOO
!
MFIN~l
This information is proprietary and is supplied by INTERDATA for the IOle
purpose of using and maintaining INTER DATA supplied equipment and shall
54
not be used for any other purpose unless specifically authorized in writing.
The algorithm for Floating Point Subtract is:
ASOOI
if FAXBO, SUMO-I, MB
ifFAXBI, SUMI-l, ALB
SOO:31-ALOO:31
AOI :07-XSOI :07
if NRLZO'ZSUMO+COUTOSI'SUMI, ASOOI-AS061
if (NRLZ I +ZSUM I }'SUMI'COUTOSO, ASOOI-ASO 11
AS061
0-AL2S:31
if SUMO {
ALl2:31-ALOS:27
O-ALOS:IO
{
ifSUMI
I-ALl I
.
ALOS:27-ALl2:31
ifNRLZI, AS06I-ASOIl
ASOII
if ZSUMI, 0--SOO:31
AOO_500
{
if ZSUMO- XSO 1:07 -SO 1:07
ALOS:31--S0S:31
MFIN-l
Floating Point Multiply
The Floating Point Multiply, with minor differences, is implemented the same way as the fixed point multiply, The 24-bit
mantissas are multiplied by adding and shifting to obtain a resultant 24-bit fraction (the least significant part of the result
is discarded), The exponents are added to obtain the resultant exponent and the logic for the sign bit is AOOI + BOO I.
At the completion of the iterative cycles, it is possible for the resultant mantissa to be unnormalized, If this is the case, a
transition is made to AS061 where a normalize shift occurs, The results are gated back to the CPU in ASOll,
Exponent underflow/overflow may occur as a result of adding the exponents or as a result of the normalize shift (the
exponent is decremented for each hexadecimal digit shifted), Should exponent Overflow occur (OFLl), the V flag is set
and if Vnderflow occurs (UFLl) the V flag is set and G and L flags reset,
The algorlthm for Floating Point Multiply is:
SUM 1-1
AOO:3I-MQOO:31
0-ALOO:31
7 1O-ACNTOI:05
AOI :07LBOI :07-XSOI :07
ASOOI-AS021
AS021
if ACRYI'NRLZ1, AS021-ASOll
if ACRY1'NRLZO, AS02I-AS061
ACNTLI-ACNT
ALLB
This information is proprietary and is supplied by lNTEADATA for the sole
purpose of using and maintaining lNTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
55
I
S07:30-AL08:31
(AOO + BOO)·ZSUMO-ALOO
ifMl
MQOO:30-MQOl :31
S3l-MQOO
AL08:30... AL09:31
[ 0-AL08
ifMO
MQOO:30-MQOl :31
AL3l-MQOO
AS06l
ALl2:3l-AL08:27
0-AL28:31
(XSLll)-XS
ifNRLZl, AS06l-ASOll
ASOll
if·UFLO
AL08:3l-S08:3l
{ XSOI :07-S0l :07
AOOEOOOO-SOO
if UFLl, O-SOO :31
l-MFIN
Floating Point Divide
Floating Point Divide is implemented by continuously subtracting the mantissa of B from the mantissa of the shifted
partial remainder (AL) to ascertain which is the larger. If the partial remainder proves to be the larger, the quotient digit
(Q3l) is set to a one and the left shifted difference is taken as the new partial remainder. If the partial remainder is less
than the divisor, the partial remainder is shifted left and the cycle is repeated.
Since the mantissas are true magnitude, the larger mantissa is readily detected by COUT081. However, if significance is
shifted out of the nth partial remainder, the n+l partial remainder is, by definition, larger than the divisor. Therefore, the
true logic for the quotient digit is:
Q311=COUT08l + AL07l
where AL07l detects a one being shifted out of the partial remainder.
The exponent result is obtained by subtracting the divisor exponent (BOI :07) from the dividend exponent (AOl :07) and
the sign bit is derived from AOOI @BOOI.
On the first divide cycle, if COUT08l is detected, it is necessary to execute a correction cycle to be able to represent the
results in 24-bits plus the sign. The mantissa (of the partial remainder) is shifted right one hexadecimal digit and the
exponent is incremented. On the next clock, the ALU returns to AS02l and continues the divide iterations.
When the divide has been completed (ACRYl), the ALU goes to AS03l, and gates MQ to the AL register and then goes to
ASOIl.
The algorithm for Floating Point Divide is:
ASOOI
SUMD-I
AOO:31-ALOO:31
AO 1:07LlBO 1:07 -XSO 1:07
710-ACNT
ASOO I-AS02 1
if ACRYI, AS02 I-ASO I I
if FSTCNTl·Q311, AS021-AS061
ACNT~ l-ACNT
ALLlB
This information is proprietary and is supptied by INTEADATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
56
not be used for any other purpose unless specifically authorized in writing.
I-MQ31
if Q311
MQO 1:31-MQOO :30
0-AL31
ALOI :31-ALOO:30
0-MQ31
ifQ310
MQO 1 :31-MQOO:30
0 ...AL31
ALOI :31-ALOO:30
XSOI :07~ l-XSOI :07
AS061
0-AL08:1'0
AL07-AL11
AL08:27-AL12:31
AS06I-AS02I
MQOO:31-ALOO:31
AS031
AS031-ASO II
AL08:31-S08:31
ASOll
XSO I :07-S0 I :07
AOOOOOO"'SOO
MFIN_I
7.3 ALU Clock (Sheet 6)
The ALU clock is a gated oscillator whose basic frequency is detennined by a tapped delay line. The basic clock period is
factory adjusted for 60 nanoseconds. The clock is enabled for all complex operations (FSELOOl). It may be inhibited for
test purposes by removing the ground strap from Connector 7. With the ground strap removed, the ALU may be single
stepped through an instruction using the push button switch located at 16R. The enable logic at gate 13A06 is true when
the conditions ALSTRTl·FSELOOl·ASOlO are met. This results in a clock output at MQCLKO, ACLKl, ACLKO,
ALCLKAO, and ALCLKBO. The clock is inhibited during ASOll and the ALU becomes static until the CPU removes
STRT.
For shifts, the basic 60 nanosecond clock provides the ALU with enough time to perform the required operations.
However, for Multiply/Divide and other special cases, 60 nanoseconds is insufficient time to perfonn the required operation. For example, when dividing, both a subtraction and a shift must be performed in each iterative cycle. For these cases,
the ALU clock period is doubled. The disable logic at gate 13 B08 detennines if the 120 nanosecond clock is to be
generated. The cases when this is true are as follows:
1.
Always in AS031 to allow the CPU to write the first word of a double precision result (Multiply/Divide)
into the destination register.
2.
Always when dividing.
3.
In CAE on the first count of AS021 to permit the transfer of either operand (A or B) through the ALU
chips to the AL. (see CAE algorithm).
4.
When multiplying if the MI bit is set. If MI is set, both an add and shift are perfonned. If Ml is reset, only
a shift need be perfonned.
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
57
7.4 Arithmetic Iterative Counter (ACNTOI :05) (Sheet 4)
The iterative shifting of the ALU is controlled by a modulo 32 counter which is enabled during AS02l. It is in AS021 that
the iterative operations of shift and Multiply/Divide occur and this counter is used to determine completion of the
operation and, therefofP _ the time at which transition to the next arithmetic state should occur. The counter is used in four
different modes as described below.
I. Shifts.
For these operations, the counter is loaded with the 1's complement of the shift count which is taken from the B Bus and
loaded at the transition from ASOO I to AS021. The most significant bit is inhibited for halfword shifts if KSIG is set. The
transition from AS021 is enabled when the counter reaches a count of 30, as determined by the logic signal ACRYI (gate
09D06). Should a shift count of zero occur, this is detected in the Arithmetic State Register and the operation is aborted
by inhibiting the transition to AS021.
2. Fixed Point Multiply/Divide
For these two instructions, the counter is initialized to a count of zero and is enabled to count during AS02l. When the
counter reaches a count of 3110, the transition from AS021 to AS031 is enabled by ACRYl.
3. Floating Point Multiply/Divide
For these instructions, the counter is loaded with a count of 710 to allow for seven fewer iterations (the size of the
exponent field). For floating point Multiply, when the counter reaches a count of 3010 the transition is made from AS021
to A SOl I if the result is normalized, or to AS061 if the result is not normalized. For floating point Divide, when the
counter reaches a count of 3110, the transition from AS021 to AS031 is made.
4. Compare and Equalize
This instruction is always performed prior to execution of a floating point Add/Subtract instruction. It is used to align-the
exponents of the two operands by shifting the mantissa of the lesser operand. The smaller operand is shifted right
hexadecimally an amount determined by the difference of the two exponents. The shift count, therefore, is loaded from
FXS051 :071 which is the difference of the exponents. It is possible that this difference may result in a 2's complement
number. Should this occur, the l's complement of this result is loaded into the counter, and the counter is inhibited on the
first count of AS021. This is accomplished by the logic at gate 09C03. If this difference should result in a shift count
greater than 510, the operation is aborted since this would result in shifting significance out of the mantissa. Should this
occur, a signal called XOVFl forces a shift count of zero and the operation is aborted. When the shift is complete, the
counter reaches a count of 3110, and ACR YI forces the transition from AS021 to ASO II.
7.5 Arithmetic Condition Code (Sheets 2 and 3)
The ALU gates appropriate Condition Code flags to the CPU for all ALU functions. When the ALU senses its address and
receives a start (STRT) it signals the CPU with SCCO that a new Condition Code is available. Figure 18 (ALU Functional
Block Diagram) shows that the ALU Condition Code circuits consist of combinational logic which determines the resultant
condition of each instruction. These are latched in a register. The clock which latches the Condition Code is gated in one of
two ways. For the simple functions (FSELOOO), the clock results from STRT, delayed an appropriate amount of time to
allow the ALU to complete its function. For complex functions (FSELOOI), the clock is generated in ASOll at the
conclusion of an instruction. The Condition Code is then gated onto the bus through a tri-state multiplexor. The
.
representation of each flag is as follows.
1. VCCO (Arithmetic Overflow).
The logic for this flag is shown on Sheet 3 (SVCCO). It is enabled for fixed point Add, Subtract, and Divide; and floating
point Add, Subtract, Compare and Equalize, Multiply, and Divide. The flag is active for fixed-point Add/Subtract instructions when an overflow is determined by the logic:
ASIGNO"SOOl"(BGOOI +SUMl)ED ASIGN I "SOOO"(BGOO I E9SUMl).
The V flag is active for fixed point Divide on the first iteration of the Divide if the Quotient bit is determined to be a one.
This condition is called a Divide Fault (DFLT) and indicates that the result cannot be contained in 31 bits Elus sign. The V
flag also sets for fixed point Divide at the end of the divide algorithm if the calculated sign of the quotient is incorrect. For
floating point instructions, all mantissa overflow is correctable by shifting the mantissa and adjusting the exponent.
Therefore, floating point overflow/underflow is a function of exponent arithmetic alone. The V flag is set for the following
conditions:
OFLl = A'MOll"(BGOllElEMl)"FXSOllEDSOFLl
OFLl = CAEl"XOVF1+AMOlO"(BGOIIEDEMI)"FXSOIOEDSUFLl
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
58
not be used for any other purpose unless specifically authorized in writing.
2. CCCO (Carry).
The logic for this flag is shown on Sheet 2. It is enabled for fixed point Add/Subtract, Shifts, and Divide; and floating
point Compare, and Compare and Equalize. For fixed point Add/Subtract the logic is SUMI COUTOOI +SUMO COUTOOO
respectively. For floating point Compare, the logic is essentially, SLCCO, and is used to signal the larger of the two
numbers. The C flag is also active for fixed point Divide to signal a divide fault and for floating point Compare and
Equalize to signal B as the greater operand (BGTRO). For Shift type instructions, the C flag is the state of the last bit to be
shifted. This is selected by the eight to one (8/1) multiplexor whose select control lines are encoded to yield the proper bit
for every type shift. The selected bit is then latched by the flip-flop shown at 2E2.
It shoUld also be noted that the Module Signal (MSIGO) from the ALU is identical to CCCO.
3. LCC (Less Than Zero)
The L flag represents the sign of any arithmetic operation. For full word fixed point operations it is the sign of the result
and for halfword shifts it is the sign of Bit 16 (SI61). For floating point operations, it is the sign of the floating point
result except where exponent underflow occurs or if the floating point result is zero. For these cases the L flag is forced to
the inactive state. For floating point compare the logic [(AOO I + BOO 1) E9 COUTOOOj-ZSUMO.
4. GCCO (Greater Than Zero)
This flag logically represents the occurrence of not less than zero and results not equal to zero and not exponential
underflow. This can be logically represented as follows:
GeCO
= LCCO-ZSUMO-UFLO
7.6 Arithmetic Elements and ROM Control (Sheets 9: 17)
The heart of the ALU is built from the four bit arithmetic/logical elements (INTERDATA Part Number 19-067) and a
format ROM used to control them. Also used in conjunction with the ALU chips are a two level carry-look ahead scheme
(lNTERDATA Part Number 19-068).
As previously stated, the ALU is essentially controlled by a 256X4 bit ROM. FSELOOI :031 and MSELOII address the
ROM and determine the required control for the given instruction. ASIGNI, BSIGNI, and FAXB I provide needed
additional information to insure correct control for fixed point Multiply/Divide and for floating point Add/Subtract.
Shown in Table 17 is a listing of ALU control and the respective operations as a function of the address bits. One
additional control bit (ALOG I) is required to correctly specify logical operations from arithmetic operations. The logic for
this gate (12L2) is:
MSELO lO-FSELOOO-FSELO I I
and essentially decodes the logical operations as per the FSEL field.
There are two levels of gating beyond the ROM outputs on AMODOO:03. These are to provide two basic overide functions.
The fiI'$t is included for the Compare and Equalize instruction. The ROM is coded for a Subtract to obtain the difference
of A and B. However, once we determine which is smaller, we wish to load the smaller mantissa into the A latch where it
can be shifted. The bus which is not to be shifted is inhibited (forced to all one's) and the transfer into the A latch is
accomplished by forcing a carry in and modifying AMODOO:03 to perform an addition. The gate which provides this
over-ride to ROM control is located at 9H4.
The second override function provided is to transfer A to S. This is accomplished by XFRO (12M5). The cases for which
this is necessary are as follows.
1.
2.
3.
4.
In ASOOI for shifts and Multiply/Divide (fixed and float) to transfer operand from the A Bus to the A latch.
In ASO 11 to transfer contents of A latch to the S Bus.
In AS031 in fixed point multiply to transfer contents of A latch to the S Bus.
In AS031 of divide (fixed and float) to transfer contents of A latch to S Bus under certain conditions (see
divide algorithms).
7.7 MQ Register (Sheets 10: 17)
The Multiplier Quotient Register is used exclusively in Multiply/Divide instructions. It is comprised of eight MSI four bit
shift registers which are capable of shifting left or right.
Control for the MQ registers is located at 7N4. The A Bus is always loaded into MQ in ASOOI by forcing both SRI and
SLl high. This is accomplished by clearing the Control flip-flop (7K4) with STRTl. For multiply, SRI is active to perform
right shifts and SLl is inactive. The opposite is true for divide when shifts left are performed.
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
59
TABLE 17. ALU ROM CONTROL
I
~
~
~
t!l
Z
t!l
z
~
aI
X
«
u..
aI
en
en«
X
X
X
0
...J
w
(/l
00
~
...J
0...J
(/l
(/l
w
w
0
0
(/l
0
::iE
0
::iE
0
::iE
0
::iE
w
w
0
...J
(/l
~
N
M
0
0
...J
~
M
0
N
«
0
«
0
«
80
FUNCTION
COMMENTS
«
::iE
u..
u..
u..
u..
X
0
0
0
0
0
0
1
1
0
SUMO
SUBTRACT
X
X
0
0
0
0
1
1
0
0
1
SUM1
ADD
X
X
X
0
0
0
1
0
0
1
1
0
SUMO
SUB. WITH CARRY
X
X
X
0
0
0
1
1
1
0
0
1
SUM1
ADD WITH CARRY
X
X
X
0
0
1
0
1
1
1
0
1
A·B
LOGICAL AND
X
X
X
0
0
1
1
0
0
1
1
0
A@B
LOGICAL EX. OR
X
X
X
0
0
1
1
1
0
1
1
1
A+B
LOGICAL OR
0
0
0
0
0
A
LOG. SHIFT RIGHT
I
X
X
X
0
1
0
0
X
X
X
0
1
0
0
1
0
0
0
0
A
LOG. SHIFT LEFT
X
X
X
0
1
0
1
0
0
0
0
A
ROTATE RIGHT
X
X
X
0
1
0
1
,
0
0
0
0
0
A
ROTATE LEFT
X
X
X
0
1
1
0
0
0
0
0
0
A
ARITH. SHIFT RIGHT
X
X
X
0
1
1
0
1
0
0
0
0
A
ARITH. SHIFT LEFT
X
X
0
0
1
1
1
0
1
0
0
1
SUM1
MULT.: A POS.
X
X
1
0
1
1
1
0
0
1
1
0
SUMO
MULT.: A NEG.
0
1
1
0
SUMO
DIV.: SIGNS ALIKE
X
0
0
0
,
X
0
1
0
1
,
X
1
0
0
,
X
1
1
0
X
X
X
X
X
X
X
1
, ,
-
1
1
1
0
0
1
SUM1
DIV.: SIGNS DIFFER
1
1
1
1
0
0
1
SUM1
DIV.: SIGNS DIFFER
1
1
1
1
0
1
1
0
SUMO
DIV.: SIGNS ALIKE
1
0
0
0
1
1
0
0
1
FLT. PT. LOAD
X
1
0
0
1
0
0
,
SUM'
1
0
SUMO
FLT. PT. SUB. WITH CARRY
X
X
1
0
0
1
1
1
0
0
1
SUM1
FLT. PT. ADD WITH CARRY
X
X
1
0
1
0
1
0
1
1
0
SUMO
COMPARE
0
X
X
1
1
0
0
0
0
1
,
0
SUMO
FLT. PT. SUB. - SIGNS ALIKE
1
X
X
,
1
0
0
0
1
0
0
1
FLT. PT. SUB. - SIGNS DI FFER
0
X
X
1
1
0
0
0
0
X
X
1
,
SUM'
FLT. PT. ADD - SIGNS ALI KE
,
0
0
, ,
,
,
SUM1
0
1
1
0
SUMO
FLT. PT. ADD - SIGNS DIFFER
X
X
X
1
1
1
0
0
0
1
1
0
SUMO
COMPARE AND EQUALIZE
X
X
X
1
1
1
1
0
1
0
0
1
SUM1
FLT. PT. MULTIPLY
X
X
X
1
1
1
,
1
0
1
0
SUMO
FLT. PT. DIVIDE
-.
NOTE: SUM1 = SUM,
60
,
SUMO = DIFFERENCE
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEAOATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writilliJ.
7.8 AL Register and Shift Multiplexors (Sheets 10: 17)
The AL registers are comprised of eight MSI quad D type flip-flops with double rail output. They are used in all complex
functions (FSELOOI) as a holding register for shift type operations.
Shifts are performed by enabling one of four multiplexors depending on the type of shift to be performed. The
multiplexor outputs are OR - tied together and perform the following types of shifts.
I. n:
has SOOI:311 and MQOOI:311 as inputs. Does not shift; used for transferring MQ or A Bus to AL
register.
2. n+l:
has SOIl :311 and AL021 :311 as inputs. Performs left one shifts for Shift instructions and Divide
instructions. End points are determined by AGLOOI and AGL311 (Sheet 8).
3. n-I:
has SOOI :301 and ALOOI :301 as inputs. Performs right one shifts for Shift instructions and Multiply
instructions. End points are determined by AGROOI and SGROOI (Sheet 8).
4. n+4:
has AL121 :311 and AL081: 271 as inputs. Shifts left hexadecimally (n+4) to normalize and shift right
hexadecimally (n4) to correct overflow conditions or for Compare and Equalize instruction.
7.9 Exponent Arithmetic (Sheet 8)
Exponential arithmetic is accomplished through the use of two 19-067 4-bit arithmetic/logic elements. The exponent fields
(Bits 01 :07) of A and B are either added to or subtracted from each other, depending upon the instruction. The result is
loaded into an up-down counter, where the exponent may be incremented or decremented as required by post-normalization or overflow correction.
As previously mentioned (Section 3.2.4), in the €ompare and Equalize instruction, the exponent difference may result in a
2's complement number and it was necessary to take the I's complement of this for use as the shift count. This is
accomplished by the Exclusive-OR gates connected to the ALU chips a'lt-d the control signal OCMPI. The 4-bit magnitude
comparator is used to determine if the magnitu~e of the exponent difference is greater than 510. Should this be the case,
the Compare and Equalize instruction is aborted since significance would be shifted out of the mantissa. XOVFI detects
this case.
INTERDATA uses excess 64 notation to express floating point numbers. As a result of an exponent addition or subtraction, the-result becomes unbiased (i.e., the excess 64 is lost). To restore excess 64 notation to the exponent field in floating
point Multiply/Divide, the most significant bit of the exponent field is complemented. This is accomplished by the
Exclusive-OR gate whose logic is FXS01IE1lEMDl.
8.
I/O GENERAL DESCRIPTION
The 8/32 Input/Output Unit (IOU) performs a multiplicity of functions. Its main function is to communicate, via the
Multiplexor Channel, with up to 1,023 peripheral devices. It has an additional capability of performing byte manipulations
for the CPU both in conjunction with and without an I/O exchange. In addition, the I/O module contains the Machine
Controi Register (MCR), the Display Controller, the Teletype Controller, the Power Monitor and System Initialize circuit,
and the Start Timer. Module Number 2 is assigned to the IOU module.
9.
FUNCTIONAL DESCRIPTION·
9.1 I/O Control Functions
IOU communicates with both the CPU (via the A, B, S, and CPU Control Busses) and peripheral controllers (via the
Multiplexor Bus) using request/response signaling. Timing is completely asynchronous (rather than quantized) to achieve
maximum speeds.
IOU becomes active when it recognizes its address (Module Number 2) on the Memory Select (MSEL) lines from CPU and
STRTO goes active. The function decode logic then directs the control and gating logic to perform a required function,
encoded on Function Select lines (FSELOO:03) and KSIG. (Function Code Extension line). At the completion of the
operation, a MFIN signal is sent back to the CPU.
IOU control is capable of performing 32 functions shown in Table 18.
Functions in Table 18 are divided into three distinct categories.
1. Multiplexor Channel Operations (D Bus Operations).
2. Byte Manipulations.
3. Auxiliary Functions.
This information is proprietary and i. supplied by INTEROATA for the lole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in Writing.
61
TABLE 18. FUNCTION MNEMONICS
MNEMONIC
FUNCTION
COMMENT
RD/RDA
WD/WDA
OC/OCA
SS/SSA
READ DATA
WRITE DATA
OUTPUT COMMAND
SENSE STATUS
BYTE/INDEXED
BYTE/INDEXED
BYTE/INDEXED
BYTE/INDEXED
RDR/RDRA
WDRIWDRA
OCR/OCRA
SSR/SSRA
ACK
READ DATA
WRITE DATA
OUTPUT COMMAND
SENSE STATUS
ACKNOWLEDGE INTERRUPT
BYTE/REGISTER
BYTE/REGISTER
BYTE/REGISTER
BYTE/REGISTER
BYTE/REGISTER
RDH/RDHA
READ DATA HALFWORD
TWO DATA CYCLES FOR BYTE CONTROLLERS
WDH/WDHA
WRITE DATA HALFWORD
TWO DATA CYCLES FOR BYTE CONTROLLERS
THW
TEST HALFWORD
MSIG GENERATION
STB
LB
STBR
LBR
STORE BYTE
LOAD BYTE
STORE BYTE
LOAD BYTE
HALFWORD/INDEXED
BYTE/INDEXED
HALFWORD/REGISTER
BYTE/REGISTER
SMCR
CMCR
SENSE MACHINE CONTROL REGISTER
CLEAR MACHINE CONTROL REGISTER
EXB
LDWAIT
EXCHANGE B·BYTES
LOAD WAIT FLlP·FLOP
POW
POUT
RELEASE INITIALIZE RELAY
GATE OUTPUT PULSES
B 16 to FWAIT
9. L 1 Multiplexor Channel Operations. D Bus functions include: RD, RDR, WD, WDR, SS, SSR, OC, OCR,
RDH, WDH; ACK, RDA, RDRA, WDA, WDRA, SSA, SSRA, OCA, OCRA, RDHA, and WDHA (see Table 18).
When the I/O control is addressed and given a D Bus function code, it creates a one, two, or three cycle Multiplexor
Channel operation.
The device address on A Bus (22:31) (refer to 8/32 IOU Block Diagram Figure 21) is gated to D Bus (06:15) together with
the activating ADRS Control line whenever address type functions are specified. The addressed controller responds by
returning a SYN signal which terminates the address cycle and starts a data cycle.
Delay timing within each cycle insures that the relationship of the MUX Bus Control lines and D Bus signals meet the
Multiplexor Channel timing requirements.
The halfword functions (RDH/WDH) have a single data cycle when the Halfword (HW) Test line is active (communicating
with halfword-oriented controller). Two data cycles are required when HW is inactive (byte-oriented controller is being
addressed).
Output data is gated from the B Bus to the D Bus via the D Bus tri-state multiplexors controlled by ROM.
Input data coming from the D Bus is latched in the D Bus receivers and then gated onto the S Bus through S Bus
Multiplexors which are also ROM controlled. In a Sense Status operation, D Bus receiver Bits 12: 15 are also gated to the
Condition Code (CC) Bus via the CC Mux. During all other D Bus operations, four zeros are placed on the CC Bus together
with CC Strobe (SSCO).
At the end of the operation, the I/O control returns a Module Finished (MFIN) signal to restart the CPU c!ock.
62
This information is proprietary and is supplied by INTEROATA for the role
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing,
b
CONTROL BUS - CPU AND CC BUS
rJ'l
g
:i
UJ
en
L1.
C!).....
M
C/)
~
«
U
~i
TO CPU
E
~
=0
S BUS (16:31) - CPU
1
SMUX~
E
0
~
-
HIGH
SELSHO
;5
u;
'"
A(L)
BYTE HANDLING
& CONTROL
FCN'S
LOGIC
,
I
"0 -i
0
~
;~ ~
3
DECODE
"- 0
~
<
"-"0
~
a"
A(L)
;;;"
SELSLO
'TRI-STATE
MCR(L)
8f s,f 8~
~
~. ~
o , <
-g~' ~
:c:; zo..
-iv;'
i~~
l>CQ.
TO CPU
{b
~
~ ~[
T
A BUS (16:31)
~i;
~ [;:ri
;.~ ~
g.~. ~
FSEL(OO:03)
KSIG
CA31
~5.~
CYCLE COUNTE%
.
~:~~
B(H)--D(H)
D BUS
ROM
CONTROL
~~;'
II
B BUS (16:31)
:::;;'" C"
,
CONTROL
LINES
GENERATION
A(H)
;.~~
"'C
r
...J~
...J
W
W 0:
1O}~
MFIN
GENERATION
f.-
8
ccCl
B(L)--D(L)
A_D
16
..J
0
u
"""-
til
START
TIMER
~ II ':~~m
MCR AND
STRAPs
TIMING CONTR
FOR
MUX BUS FCNS,
CYCLE COUNTER I
0:
V
I ~
EPF
M
0
0
0
1'5
R
o
..J
U
0:..J
U
0
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
«....
0
"
0
..I
u,
J
INPUT CIRCUITS
GSTRT1
OSTRTO
OBEN
D--.:O::..:S:....:T..:..R:....:T....:.1_ _ _ _ _ _ }
SHEET 2
SYNO
KSYN1
SHEET 5
~~H~W~O----.----~~HW~l----~~~H~W~O~A~---------
~
O.
....
"
.... /
~
0
g
..JCl
:J
iii co
iii co
w-
-
is s:
~~ ~ :r
I'-
S BUS ROM
SILl AND S(~
MUXES
-I~
.... CONTROLLERS
AND ENABLE
LOGIC
'r::
!
a:
~~ I~I~
I~=U
:J~
o
KA1
KB1
OSYN1'
FSL030A
I
"\
rl19-059
J
-
119-059
SHEET 6
KOO
U
y'19-059
-
CLORO
FSEL011 :031
KSIG1
CA311
HW1
KAl
KB1
-
(T2 and T3)
OCKL1
0
0
15
1
2
3
4
7
6
5
u
w
DATA TO BE GATED
ON 0(00:15)
..J
:::>
u..
WOANO
WOA
w
W
Y2
Y3
Y4
12
11
10
9
PBUS CONTROLLEF
U
>u
o BUS CONTROLLER INPUTS
Y1
OUTPUTS
L
L
H
L
L
L
L
L
TO
DRIVERS IN H-Z
H
H
H
H
L
L
H
L
L
L
L
H
T3
WILL NEVER OCCUR
X
X
X
X
L
L
H
L
L
L
H
L
T1
A(22:31~0(~:15)
H
H
H
L
L
L
H
L
L
L
H
H
T2
0-0 00:05
O-O(H)
B(H)-O(L)
H
L
H
H
L
L
H
L
L
H
L
L
TO
DRIVERS IN H-Z
H
H
H
H
L
L
H
L
L
H
L
H
T3
WILL NEVER OCCUR
X
X
X
X
L
L
H
L
L
H
H
L
T1
H
H
H
L
L
L
H
L
L
H
H
H
T2
H
L
H
H
L
L
H
L
H
L
L
L
TO
DRIVERS IN H-Z
H
H
H
H
L
L
H
L
H
L
L
H
T3
WI LL NEVER OCCUR
X
X
X
X
L
L
H
L
H
L
H
L
T1
H
H
H
L
L
L
H
L
H
L
H
H
T2
L
H
L
H
L
L
H
L
H
H
L
L
TO
DRIVERS IN H-Z
H
H
H
H
L
L
H
L
H
H
L
H
T3
WILL NEVER OCCUR
X
X
X
X
L
L
H
L
H
H
H
L
T1
A_O
H
H
H
L
T2
B(H)-O(H)
BIU_OIU
L
H
L
H
L
L
H
L
H
H
H
H
A(22:31 )-0(06: 15)
0-0100:05)
O-O(H)
BIH)-O(L)
A(22:31) -0(06: 15)
0_0(00:05)
B(H)_O(H)
BIU_OIU
Figure 28. D Bus ROM Controller Data Gating for WD and WDA
This information is proprietary and is supplied bV INTEROATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
77
ROM ADDRESS SELECT
IDENTICAL FOR BOTH S BUS
':::'l\iiROLLERS
<:;
FUNCTION
0
-I
~
~
<:;
N
M
0
w
en
w
en
w
en
(!)
Ui
~
«
U
-I
0
-I
-I
~
~
M
~
DATA TO
BE GATED ON
S(H) = S(16:23)
S(H) ROM
CONTROLLER
OUTPUTS
B
C
A
Yl
Y2 Y3 Y4
Y1
DATA TO
BE GATED ON
S(H) = S(24:31)
SILl ROM
CONTROLLER
OUTPUTS
SEL
A B
C
:'(1
Y2 Y3 Y4
w
en
u.
u.
u.
u.
1
2
3
4
7
6
5
12
11
10
9
12
11
L
H
L
L
L
L
L
L
H
L
L
L
L
3:
J:
)'"
9
10
L
H
.,
L
H
L
L
L
L
L
H
RDH
H
L
L
L-
L'
L
H
DR(Ll--S(L)
DR(Hl--S(H
L
H
L
L
L
H
L
L
H
L
L
L-
L
L
H
L
H
L
L
L
H
H
L
H
L
L
L
L
L
H
H
H
L
L
L
L
L
L
H
L
L
L
L
L
H
H
H
L
L
L
L
H
L
H
L
L
L
L
L
H
DR(L~S(L)
DR(Hl--S(H)
RDHA
H
H
L
L
L
H
L
L
H
L
L
L
L
L
H
H
H
L
L
L
H
H
L
H
L
L
L
L
L
H
Figure 29. ROM Controller Data Gating for RDH and RDHA
11.2 Auxiliary Functions
(SMCR, CMCR, LOWAIT, THW, POW, and POUT - see Table 19).
These functions are described in this section. The SMCR function provides a means for sensing 16-bits of MCR, (Machine
Control Register) see Section
The SMCR function is decoded by a 3:8 decoder (7B7), MCRll: 15 is placed on the CC Bus by 2: 1 CC Bus MUX
(7E2). The SMCRO line also generates MFIN and the strobe for Condition Code. The contents of MCROO: 15 is gated onto
the SOO: 15 by the 19-132 S Bus Multiplexors (ROM controlled) shown on Pages 2 and 3 of the 35-539008 schematics.
The OMCR function is decoded by the 19-129 3:8 decoder, whose CMCRO output enables the four least
significant bits of the B Bus (7B2) to clear selectively four MCR registers. (Ones in B27:31 clear the corresponding MCR
registers. )
The LOWAIT function is decoded by the 19-129 3:8 decoder, it controls the indicator light on the Display
Console (ON or OFF) according to the state of B16.
The THW function is decoded by the 19-129 3:8 decoder (7B7) it generates MSIG according to the state of the
HW (Halfword) Test line.
The POUT function is decoded by the 19-1293:8 decoder it gates four bits (B27:31) to a set of board stakes for
external signalling purposes. These signals may be wired to the front chassis terminal strip by adding optional wires to the
Display Console connector at the IOU board. The MFIN signal to the CPU is delayed by a timer to set the output pulse
width at 1.0+0.3 microseconds.
.
The POW functions releases the System Gear relay, (see Section 10.11).
This information is proprietary and is supplied by INTEROATA for the sole
78
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
12. DISPLAY CONTROLLER
The display controller has access to the CPU via the Multiplexor Channel D Bus and the I/O control in the same manner as
other peripheral devicr controllers. The display controller provides a means for reading the contents of all the system
registers or any main memory location and transferring the data to the Display Console.
Data and programs can also be manually entered from the Display Console to the controller and then to the CPU. The
display controller signals the CPU directly via the Display (DSPLY) interrupt.
12.1 Addressing Logic
The Display Console device address is wired as (X'D f). The D Bus lines D08: IS are buffered and inverted to create double
rail Data Lines (Sheet 8). Two more bits of the D Bus (06:07) are used directly in address decoding logic on Page 9 of the
35-539D08 schematics.
The decoded Display Console address activates B1 line (9H4), which sets the ADB flip-flop (9M4) at the trailing edge of
the ADRSO Control line signal. Bl also generates ADSYNBO (lOK4) which generates the SYN signal and clears the CATN
flip-flop (10F6).
12.2 Data Output
The byte of data transferred between the display controller and the Display Console Makes use of 8-bidirectionallines
SOOO:07 (8H4). Data is placed on this SD Bus when the DAGBO line is active and is gated to one of the four display
registers in the Display Console, by one of the load signals, LA or LB (13J 5). LA and LB generation logic is shown on Page
13 of 35-534008 schematic. Two one-shot timers (13E2 and 1312) insure that the loading signals conform to Display
Console specifications. The XA flip-flop is reset by RSTO=ADRSI-INCRO·BI.
12.3 Data Input
XC flip-flop (I3E8) controls the SHIO and SLOO signals which gate the contents of the two least significant bytes of the
Console Switch Register to the Processor via SDOO:07. The RSTO signal clears the XC flip flop in the same manner as it
cleared XA.
12.4 Status Input
The Status byte encoding is shown in Chapter 6, Control Console; in the User's Manual, Publication Number 29-261.
12.5 Control Logic
Complimentary pulsed ESNOO and ESNCO signal from the console are fed into a deglitching R-S flip-flop (IOC5). ESNOO
and ESNCO are activated by depressing various keys of the Display Console keyboard (see Section 12.1). This results in
setting a CATN flip-flop and generating display controllers private interrupt to the CPU-DSPLY (I OJ8). DSPLY interrupt is
also generated by depressing the SNGL key on the Console keyboard, which sets the SNGL flip-flop. The SNGW flip-flop
(lOF8) can be sensed by CPU as MCR07. The INCR flip-flop (IOC2) which determines either incremental or normal mode
sets on the trailing edge of the CMGBO control line. All Control lines for the display controller (6N5-9) are derived from
the MUX Bus control lines by gating them with the output of the controllers Address flip-flop ADB (9M4). These Control
lines are also used for the Display Consoles SYN generation (7C8). The D Bus drivers and receivers, SYN generation logic,
and part of the address decode logic is shared with the Teletypewriter controller.
13. TELETYPE CONTROLLER
The built-in Teletype (TrY) device controller interfaces an ASR;K.SR 33 or 35 TrY to the Processor. It provides the
serial/parallel conversion required for data transfer between the parallel D Bus and the serial, eight level, start/stop ASCII
code signal used by the TTY (see Figure 30).
12345678
~STOP BITSIL....,~_ __
START BIT
A I-
DATA B I T S - 1
11 BITS
~
NEXT CHARACTER
START BIT
100 MS/CHARACTER
Figure 30.
Serial ASCII Code U (Even Parity)
This information is proprietary and is supplied by INTER DATA for the lole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
79
13.1 Block Diagram Analysis
Figure 31 is a block diagram of the TTY controller. The control circuits consist of the Command flip-flops (read or write,
etc.) which direct the flow of information, circuits to control ATN/ACK functions, and logic to generate the status bits
and control the timer.
The serial information received from the TTY is sampled by the timer and strobed into the Shift Register. When all the
data has been shifted in, the data in the Shift Register is transferred to the Buffer Register. It is then gated through D Bus
tri-state drivers on D08:15), by the Data Request signal (DRG), Status Request Signal (SR), and Address (ADRS) Control
lines. A bit-by-bit copy of the received data may also be sent to the TTY printer/tape punch when the Block flip-flop
(BLK) is cleared. In the Write or Send mode, the data byte is placed directly (parallel) into the Shift Register and then
shifted out (serially) to the TTY.
13.2 Bus Communications and Address Circuits
Communications between the Processor and the TTY controller is via the Control lines, Test lines, and the low order eight
bits of the D Bus. The bus receivers (Sheet 8) are shared with the display controller. The Data Lines D08: 15 are buffered
to form the DLOO:07 lines. When the wired address x'ot is detected, Line AO is active and the TTY address flip-flop
(ADA) (9M3) is toggled set on the trailing edge of the ADRSI signal (912). This enables the other Control lines for the
TIY controller (Sheet 10). While the ADRSI signal is active, the ASYNAO line goes low and generates the return SYNO
signal 01 G9).
The D Bus sent logic consists of 19-136 tri-state bus drivers (Sheets 8, 9, and 11) controlled directly by DRGAO, SRGAO
and ATSYNO TTY Control lines, which are derived from the corresponding MUX Bus control and TIY Address flip-flop
(Sheet 10).
NOTE:
For systems where X'02' has been assigned to another device, the
TTY controller may be strapped for X'82'. (see Sheet 7).
13.3 Status and Commands
The bit assignments for TTY status and command bytes is shown in Table 21.
TABLE 21. TELETYPE STATUS AND COMMAND BYTE
BIT
NUMBER
0
1
2
3
4
5
STATUS
BYTI:
ERR
*
BRK
*
BSY
EX
COMMAND
BYTE
DISABLE
ENABLE
UNBLOCK
WRITE
READ
BLOCK
6
*
1
DU
DISARM
* Unassigned status (will return zero).
STATUS BYTE
ERR
The Error bit is set when a character is not taken from the controller buffer before another character is
assembled.
BRK
The Break bit is set at the end of one character time when the line is held in the space condition for a
period greater than a character period.
BSY
Read Mode. The Busy bit is normally set and is reset when data is available for transfer to the Processor.
Write Mode. The Busy bit is normally reset and is set when data is being transferred to the terminal.
EX
The Examine bit is set when BRK or ERR is set.
DU
The Device Unavailable bit is set when the terminal is powered down or in Local mode.
80
This informatIon is proprietary and is supplied by INTEROATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
COMMAND BYTE
DISABLE
Disables device interrupts; allows queuing of interrupts.
ENABLE
Enables device interrupts.
Note that a command byte with both Bits 0 and I set, DISARMS the interface, no interrupt queuing.
UNBLOCK
Allows the Printer to print data entered via the keyboard or tape reader.
BLOCK
Disables the Unblock feature.
WRITE
The interface is placed in the Write mode.
READ
The interface is placed in the Read mode.
The command flip-flops EBL, ARM, BLK, and WT (9J7, 9L7) are loaded with the trailing edge of the CMGAO signal (9D7).
The contents of the flip-flops remain unchanged if the D input is low. The Write Storage flip-flop (WT) (9L7) unconditionally accepts the Read/Write signal from the Processor, however, the Write Execution flip-flop (WRT) (12DS) can only be
updated when the timer has stopped; i.e., when TMGO (12A4) is high.
The EBL and ARM flip-flops (l2J7) are loaded from DLOO and DLDI as described in Table 21. They control the action of
the Interrupt flip-flop (lNTR) (l2E8) and the interrupt line ATNO (l2G7).
The Block flip-flop (BLK) controls the serial feedback of data from the TTY receiver to· the TTY driver. When reading a
non-ASCII tape, it is inconvenient and undesirabie to permit the received data to reach the printer/stunt box and operate
the bell, line feed, form feed, etc., functions. This feedback is broken when the BLK flip-flop is set. Sending data to the
TTY from the Shift Register is not affected by the BLK flip-flop.
The Busy (BSY) status bit is controlled by the Write Execution flip-flop not the WT flip-flop. The Break bit remains set as
long as the Break key is depressed at the TTY. The Error bit (overflow) is cleared by either a Data Request, any command,
or the system initialize signal SCLRO.
13.4 Timer Circuits
The timer consists of the control flip-flop (TMG) (12D2), a 440 HZ multi-vibrator MTA (12H3) and MTB (12K3), a
two-stage clock counter MTC (12G4) and MTD (12H4), and a character counter (TA, TB, TC, and TD) (12L6). In the idle
or reset state with the TMG flip-flop cleared, TMGI (12D2) is low to disable MTA and MTB, to clear MTC and MTD, and
to preset the character counter to the count of five.
. ..
When the TMG flip-flop is toggled set at the end of DAGAO (12A2) in the Write mode; TMGI, TMGIA and DTMGI all go
high to enable the timer. The 440 Hz pulse train (MTBI) (l2L3) drives the two-stage counter (MTC and MTD) and a
decoder gate to generate the 110Hz train of clock pulses (CLKO and CLKI) (l2K4) and the shift pulses (SHFTI) (l2N4).
After the end of the ninth clock pulse, TB I, TCI, and TDi are all high, thus forcing FSTPO (12MS) low to terminate the
train of shift pulses. During the eleventh clock pulse, EOCO (l2A2) goes low, and the TMG flip-flop is toggled clear on its
trailing edge. This produces a train of eleven clock pulses and nine shift pulses having a period of 9.09 milliseconds (110Hz)
with the trailing edge of the first pulse occuring 9.09 milliseconds (one bit period) after TMG is set. The pulse width is
approximately 1.IS milliseconds (one-eighth of a bit period).
The idle timer is also started (by the direct set pulse STO) (12E3) when the received Start bit arrives from the keyboard or
tape reader or due to depression of the Break key. This is not dependent on the Read/Write mode since the BRK condition
must be detected in both modes. The width of the STO pulse is determined by delay Capacitor 02HCl (8G I) which
generates the delayed TMGO signal DTMGO (12C4). Since the MTD flip-flop is direct set STO, the first CLK/SHFTI pulse
occurs 4.S4S milliseconds (half of a bit period) after the TMG flip-flop is set; the period of the pulses is still 9.09
milliseconds. Received data is sampled/shifted at the center of each bit. The TMG flip-flop is toggled clear at the end of the
EOC and TTMG pulses as before.
13.S Data Output
The TTY controller is in the Write mode when both the WT and WRT flip-flops are set. To send data to the TTY, the
DAGAO line (liAS) goes low to load DLDO:07 into the Shift Register, clears the Start bit flip-flop (DRN) (11 N6) and
toggles set the Timing Gate flip-flop (TMG) (12D2). Note that if the timer was already running when the Data Available
Control signal is received, the DAGAO signal (II AS) would be blocked by TMGO (12D2) low, no return SYN would be
generated, and the false sync condition would be detected after 3S microseconds. For this reason the WDH instruction
must not be used with the TTY controller.
This informatIon is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
81
I
DATA LINES - HIGH 0(00:07)
r
00
DATA LINES - LOW 0(08:15)
tv
FROM CPU
OR PRIOR
CONTROLLER
I
IL LINES
I
~A~T~N~O______________________________+-~r-
________ __________
~
-+______________
~r-________________
SYNO
TA~
RACKO
2
8
I
~
•
I
DISPLAY
CONTROLLER
5
DATA LINE
RECEIVERS
1t8--
II CONTROL LINd
II RECEIVERS I
ARM1,EBL1,SATNO
I
I
ADDRESS
CIRCUIT
---+'1"""0~-1
I
~+----11
6
o
COMMAND
GATES
I
AND
CIRCUITS
I
.----1--__________-.!..I-R-R________________--.JT
~
[
~
000/1 :
z
I
TIMER
ISRGO,DRGO J
I
DAGO
;;j
:Il
D
"
-i
"
.
SHIFT 1
~
.
S
RECEIVE
SEND ~----I~I~
TE~~~;PE ~
CIRCUITS
i\...
I 0
T
000
I~LKO
I 1 1 2 13
I
I
~ ~
LrJ-DTO
-U-
I
I
LDBR1' •
•
•
: 01 1 1 2 1 3
DT1
R:~I~;ER
(1 1 ! 1 ! ! 1 1)
4 15 16 17
I
I
I
N
~ ~ ~ ~ ~
,
)
BUFFER
REGISTER
DATA BR(00:07)
DRNO
C:~LET~PEj
9
type
1
I ACK/ADRS
STRAPS
--r
DU1
l
STATUS
I
ATSYNO
0 BUS
DRIVERS
.
I
•
•
•
•
41 5 1 6 1 7
I
CONTROL
FLIP-FLOPS
I
I.,.
5.
I ATN/ACK
CIRCUIT
I
.g
TO
NEXT
CONTROLLER
When the timer starts, shift/clock pulses are generated as described earlier and shown on Figure 32. The bit stored in the
DRN flip-flop is connected to the transmit line (TNSB I) (16D2) by the high states on the device transmitting (DTO) and
the TMGI lines. Since the DRN flip-flop is initially cleared by DAGAO, TNSB I goes low, and the gate driving TNSO turns
off to send the open-100p Start bit condition. At the end of each shift pulse, as the eight data bits are sequentially
transferred into the DRN flip-flop, a high state at the serial input of the Shift Register (DXI) (II B2) gradually loads the
register with all ones (including the DRN flip-flop).
DAGAO
I
(~
TMGl
/
J
\r LIU-UlU-LSU-LJlU U-
BSYl
ClKl
FSTPO
r-~
!--
~ r-r-
r~
SHFTl
EOCO
hIy- LSLr U- LSLS
V
Q
TNSBl
l
•
~ ~ART
/
7
\
~-
)
(
(
~
U~ I"'\.
6
5
4
3
2
J
1
o 'II
I
1
STOP
BITS
BIT
100 MS
ONE CHARACTER PERIOD
.1
Figure 32. Write Mode (Output) Timing. Teletype
During the last two clock periods, after shifting has stopped, the ONE Level stored in the DRN flip-flop is sent out as the
closed-loop Stop bit condition. The EOC pulse clears the TMG flip-flop to generate the closed-loop idle condition.
With the WRT flip-flop set, the status bit BSYI (l2D6) is active when TMGI is active. Should a command which clears the
WT flip-flop (Read mode) be received while the timer is running, the WRT flip-flop (and the definition of BSY status) does
not change until the TMG flip-flop is cleared and TMGO (8F8) gates WTl into the WRT flip-flop.
13.6 Data Input
The timer circuit can be started from the TTY receive loop in either the Read or Write mode as described in Section 13.4.
This insures that the Break condition is always detected. However, serial data cannot enter the Shift Register (DXI)
(11 B2), unless the TTY controller is in the Read mode; i.e., the WRT flip-flop is cleared and WRTO high. The Load Buffer
Register pulses (LDBRI) (8G2) are generated only in the Read mode.
The Device Data line (DOl) (16G7) is high active when there is current flowing in the receive loop. This represents the
logic ONE level and also the idle loop condition. The signal from the receive loop is filtered by an RC network (180
ohms/2.2 mfd) (16J8) and then reshaped by the Schmidt Trigger circuit (composed of a pair of inverters and two resistors)
(lGE7) to generate the DDO and DDI signals.
When DDO and DOl first become active, the timer is started by the STO pulse (as described in Section 13.4) and the Device
Transmitting flip-flop (DT) (1lJ6) is set. This flip-flop forces the TNSBI line high and partially selects the TNSAI gate,
subject to a high level on the BLKO and DDO lines; i.e., the serial feedback circuit to the TTY Printer/Punch. The DT
flip-flop also arms the Line Check flip-flop (XLC) (11 M7) by placing a high level on the D input.
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83
As seen on Figure 32, the XLC flip-flop is toggled set at the end of the first SHFT pulse. During the first SHFT pulse, the
receive loop is checked to insure that the loop is still open; Le., a legitimate Start bit has started the timer. If the loop is
closed, DDl is high and the Start Glitch pulse (GLTCHO) (12B2), is generated to clear the TMG flip-flop at the end of the
SHFT pulse. The timer is reset, there are no EOC or LDBR pulses, the Buffer Active flip-flop (BA) (8E8) and the BSY
status are unchanged.
!
START
BIT
(2)
(3)
(4)
(5)
(6)
(7)
(8)
I
7
6
5
4
3
2
1
0
I:
!
~~ I
\1
Ii
:
t\.
1\
TMGl
Dn
STOP
BITS
(1)
DDl
STO
I
!I
I
1
:
_~r+II-4--~II-4----~--~--~----+---~--~----·+----r~:--~----
\1
~LI~
_ __
LJ
I
i
'--t~+f-___
~CLK1---+-1r .ri-Ln-Ln RJIl R-Ln-Ln-m-4~:7~SHFT.!........4-Ilrf---+-l.ri--Ln-Ln-Ln-ln-m-m-m
L
I
~
' " " - " ' + - I '
I
EOCO
II
Ii---f.----
~
i
~:
XLCl
I
~4~1~---------------------------100MS ------------------------------~
Note: Bit Designations (X) are Paper Tape Channel Numbers.
Figure 33. Read Mode (Input) Timing, Teletype'
The serial data at the Shift Register input (DXI) (II B2) is active when the DD I line is active. The nine SHTl pulses move
the received data into and along the Shift Register until the Start bit and the eight data bits occupy DRN and SROO:07.
Shifting occurs at the end of each SHFT pulse; Le., the center of each bit.
The TMG flip-flop toggles clear at the end of the EOC pulse and clears the DT flip-flop. The XLC flip flop is cleared by
EOC if the loop is closed due to a Stop bit, DDl high (16E7). In the case of a missing Stop bit (or Break condition), the
XLC flip-flop remains set after the EOC pulse has cleared the TMG flip flop. The function TMGO'XLCl causes BRKO
(8K7) to go low, and lines BRKl, EXl, and EXO to become active. The timer cannot restart on the open loop condition
since STO=DTMGO' DDO' XLCO.
The BRK condition continues until the receive loop is closed. The DDl·TMGO function then clears the XLC flip-flop.
In the Read mode, BSYI (l2D6) is low whenever the Buffer Active flip-flop (BA) (8E8) is set. The EOCl pulse generates
the LDBRl pulse to load the Buffer Register and toggle set the BA flip-flop. The DRGAO signal (8A9) clears the BA
flip-flop when the buffer is gated to the D Bus. An overflow or error state exists if the- LDBRl pulse finds the BA flip-flop
still set, the Overflow flip-flop (OV) (8G8) is then set. The OV and BA flip-flops are cleared by the DRG pulse, any CMG
pulse, or the initialize signal SCLROB.
84
This information is proprietary and is supplied by INTER DATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used tor any other purpose unless specifically authorized in writing.
13.7 Interrupt Circuit
The TrY controller generates an interrupt for a negative transition on BSYI. This transition toggle sets the DFBSYO
(l2E7) flip-flop which in tum direct sets the INTR flip-flop (l2E8). This forces ATNI high and ATNO low.
The Processor responds by executing an Acknowledge interrupt. When the TrY controller has first priority, the RACKO
lead goes low forcing RACKI and DRACKI high. With GATNI high, the TACKO gate is blocked and the ATSYNO line
goes low. This gates the controller address x'ot to the D Bus, generates the return SYNO, direct clears the DFBSY
flip-flop, and clears the INTR flip-flop at the end of ATSYNO.
When the system uses the Memory Protect and/or the Real Time Oock controllers, the RACKO/RACKO daisy-chain is
wired to the higher priority controllers before it reaches the TTY over the back panel.
As noted, in Section 13.3, the Disable command clears the EBL flip-flop forcing the EBLl (9H7) and GATNI lines low.
mterrupts may be queued by setting the INTR flip-flop. The Disatrtl command forces ttr~ ARM 1 lead (9H8) low to clear
the INTR flip-flops and hold them clear; interrupts are not queued.
13.8 Initialization
The system initialize signal SCLRO (l5K2) conditions the TrY controller by setting the BLK flip-flop and clearing all
other control flip-flops. This presets the controller in the Read mode with interrupts disarmed.
13.9 TrY Timer Adjustment
The only adjustment on the TTY controller controls the frequency of the 440Hz timing multivibrator. The adjustment is
made in the following manner:
I. Initialize the system.
2. Connect an oscilloscope to TP-TMGlA (located at the stake near Connector 2).
Vertical scale: 2 volts/centimeter
Horizontal scale: 1 milliseconds/centimeter
Sync: internal, negative
3. Generate a continuous stream of data from the TrY by ·reading a tape or by the Repeat function of the key.
board.
4. Adjust Potentiometer at location 14R(next to the test point TMGIA) for the waveform shown below.
LL
u t
0.2 ,;U;Eood
I
~ lI)()millisec:ondS~
13.10 Machine Control Register (MCR) (Sheet 7)
... A Machine Malfunction (MMF) interrupt is generated when Bit 11, 12, 13, 14, or 15 of the Machine Control Register
. (MCR) is set (7G4). The MCR bits are assigned and gated (with the SMCR function) as indicated in Table 22.
The CMCR function clears MCRII :15 where there are ONES in B27:31. The system Initialize (SCLRO) clears MCRIO:15
. - the straps are not affected. The SMCR function is described in Section 11.2.
13.11 Power Monitor and System Initialize
All circuits for the Power Monitor are on Sheet 15. The master reset signal SCLRO (l 5F2) is active when the Initialize
Relay Kl (1 5B9) is de-energized. During normal operating conditions, all voltages are present and the POWDNO line (l5G7)
is high. This allows the delay transistor and the Darlington circuit (l5A8) to conduct. As long as these transistors conduct,
the Initialize Relay KI remains energized and the SCLRO line is held high to +5 volts by a resistor (l5E2).
If any of the four items listed in Section 10.1 (CL070) occur, the STPFI line (1412) goes high and starts the one millisecond EPF timer (14K2). The leading edge of EPFO (l4L2) sets Bit 15 in the MCR (7G2), generating a Machine Malfunction (MMF) interrupt. In response to MMF, the user has an opportunity to do any necessary system resetting and data
storage.
.
This information is proprietary and il supplied by INTER DATA for the 101,
purpose of using and maintaining INTEADATA supplied equipment and shill
not be uHd for any other purpose unless specifically authorized in writing.
85
TABLE 22. MeR BIT ASSIGNMENT
BIT
MNEMONIC
MEANING
S·BUS
CONDITION
CODES
MCR15
EPF
EARLY MF
S31 and
LFCO
MCR14
IRMP
INSTRUCTION PARITY FAIL
S30 and
GFCO
MCR13
DMPFO
DATA PARITY FAIL
S29 and
VFCO
MCR12
APF
AUTO DRIVER PARITY FAIL
S28 and
CFCO
MCRll
STF
STRT TIME OUT FAIL
S27
MCR10
CATN
CONSOLE ATTENTION
S26
MCR09
RSTS
REGISTER
MCR08
SPARE
MCR07
SNGLI
DISPLAY CONTROLLER SNGL F-F
MCR05
BNKB
BANKB
(STRAP)
S21
MCR04
BNKA
BANKA
(STRAP)
S20
(STRAP)
S25
(STRAP)
S24
S23
--At the end of the
one millisecond EPF delay, the trailing edge of EPFO (14GS) toggle sets the Primary Power Fail flip-flop
(PPF) (14HS) causing the PPF interrupt (14K6) to be sent to the CPU and a low active signal on CL070 (14K6). PPFI also
starts another one millisecond timer XPF (14KS). When the PPF interrupt is detected, the micro-program stores the PSW
and register stack in the main memory and sends the POW function to the IOU. The Stop flip-flop (STP) (14NS) is either
toggled set by the trailing edge of XPFI or direct set by FPOWO (14N4), whichever occurs fIrst. When STPI goes high,
POWDNO goes low to turn off the transistors of the Darlington circuit and de-energize the Initialize Relay Kl. The GSTPI
lead (1517) is normally high. It is unused except in some multi-CPU systems.
Loss of AC or DC power also de-energizes the relay. POWDNO goes low when the -15 volt input (NlS) (1SD8) to the
inverter is lost. The Darlington circuit cannot operate the relay if either the +5 volt collector supply (PS) or the +15 volt
base supply (PIS) (1SB6) is missing. Should the AC input (ACI and AC3) (1SB2) be too low or missing, the Power Fail
Detector circuit removes the base drive to the Darlington circuit.
If the AC input is lost (or fluctuates enough) the potential at the base of 02BQ3 becomes more negative, 02BQ3 conducts
and supplies base drive to 02BQl. The 4.7K resistor (1SK4) provides positive feedback from 02BQl to 02BQ3 causing
these transistors to turn on. The emitter voltage of 02BQ3 drops, 02BQ4 turns off, 02BQ2 turns on and commences to
discharge the delay capacitors (1SB6). With 02BQ 1 conducting, its collector voltage approaches ground and generates the
low active signal PFDTO (1SK4). As described earlier, this starts the sequence which puts a low level on POWDNO and
completes the 'capacitor discharge. The Darlington circuit has no base drive so the relay is deenergized.
The Initialize Relay Kl is a dry reed unit with Single Pole Double Throw contacts. The normally closed contact of the
" de-energized relay (Kl) provides a metallic ground on the system Initialize line (SCLRO (1SK2).
For a sequence due to POFF, LSU, INHO, EXAO, or EXBO low (14A2) clearing STP allows the POWDNO lead to go high
and the delay capacitors (1SB6) to charge slowly through the base resistors of Transistor 03AQl. When the threshold of
the Darlington circuit is reached, the circuit conducts and the Initialize Relay KI is energized thereby removing the ground
from the SCLRO line.
In the case where Initialize is caused by a failure to PS, NlS, PIS or the AC supply" the Initialize Relay Kl de-energizes
'
and remains in that state until the fault is corrected.
This information is proprietary and is supplied by INTER DATA for the sole
86
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
13.1 2 Primary Power Fail Check
.-/
The Primary Power Fail Detector is located on the IOU board. The circuit is checked and adjusted as follows:
I.
Connect the Primary Power Cord of the CPU power supply into a variable voltage source (Variac or
equivalent).
2.
With the line voltage set at the nominal value of 115.0 VAC, turn the Power on.
3.
Adjust Potentiometer at location OOR to generate the Power Fail condition of CL070 (back panel Terminal
122-0) when the AC line voltage is set for 103.SV (I.e., 10% low). System Initialize line (SCLRO) Terminal
105-0 should become low active in less then 2 milliseconds after STPIA (Test Point 110-4) goes active.
4.
With nominal line voltage, load the Model 8/32 Test Program and depresS the RUN Key. While the program is
running, remove the AC line cord from the primary power source.
NOTE:
The TTY will run-open if connected into a different power source.
5.
Connect the AC line cord back into the power source. The TTY should stop cycling. Depress the EXEcute
switch and the test program should continue to run.
6.
Repeat Step 4, but turn the Console Power switch OFF instead of removing the AC line cord.
13.13 Start Timer
The Start Timer circuit is shown at location ISE6. With the timer-kill (KSTMI) (lSC7) in its normally low state, the
ungated STRTO signal (lSB8) enables the 30 microsecond timer STMA (lSE6). When the selected module generates a
MFINO (lSH8) signal, then it clears the timer and disables the timer flip-flop (STMB) (6F8).
The STRT Timer (30 microseconds) is activated whenever the CPU sends the STRT signal to the various system modules
(ALU, FAU, IOU, etc.) and is cleared by the MFIN signal from the module addressed by the MSEL (00:02) lines. Should
the time out occur before the MFIN signal arrives, one of the two things happen.
l. On non-MUX Bus operations, Bit II of the MCR is set, a pseudo MFIN signal restarts the CPU clock, and the MMF
interrupt is generated.
2. In the case time out occurs during a MUX Bus operation, the MCR is unchanged, the False Sync code (01 OO/CVGL) is
placed, on both Condition Code Busses and a pseudo MFIN restart the CPU clock. If the MUX Bus operation happens to be
of the sense type, X'004' is also gated onto S(l6:31).
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
87
14. SAND D BUS ROM CONTROLLERS
14.1 S Bus High ROM Controller (19-142F4S)
LLLL
LLL~
LLLL LLLL
~~LL
024-0~1
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
0~0-047
LLLL LLLL LLLL LLLL
048-055
LLHL LLHL LLHL LLHL LLLL LLLL LLLL LLLL
B72-079
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
0&0-087
HLLL HLLL LHLH LHLH LLLL LLLL LLLL LLLL
0~6-0;3
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
096--.LI7f3.
LLHL LLHL LU-iL LLHL HLLH HLLH Li-iLH Li-iLi-i
104-ii~
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
il~-.i.l~
LLLL LLLL LLLL LLLL LHLL Li-iLL LHLL Li-iLL
120-i27
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
128-~~5
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
1~6-14:
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
144-151
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
15~-159
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
~LLL
~LLL
LLLL
00~-0i3
~LLL
LLLL LLLL LLLL
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
168-173
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084RIZle:,F78
176-1.;:=';:::;'
LLLi.. LLLL U... LL LLLL LLLL LLLL LLLL LLLL
1 Si-e841':eeF 78
184-191
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
192-199
LLLL LLL( LLLL LLLL LLLL LLLL LLLL LLLL
212i'::'-2t:17
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
216-223
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
224-2~i
LLLL LLLL LLLL LLLL LLLLLLLL LLLL LLLL
23~-2~~
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
~40-247
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084Fi:t:10F78
248-25~
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084Fi:eeF78
This information is proprietary and is supplied by INTERDATA for the lole
88
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unf•• specifically authorized in writing.
19-084F.:0t:1F 78
14.2 S Bus Low ROM Controller (19-142F46)
LLLL LLLL LLLL LLLL LLLL LLLL LLLL
00~-~i~
LL.ll
62~-01i
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
646-055
HLL~
056-663
LLHH LLHH LLHH LLHH LLLL LLLL LLLL LLLL
07~-079
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
066-0;~
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
09~-101
HLLL HLLL HLLL HLLL LHLL LHLL HLLH HLLH
112-11;
LLLL LLLL LLLL LLLL LHLH LHLH LHLH LHLH
120-127
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
1~6-115
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
136-143
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
144-151
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
1~~-i5S
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
i60-j6~·
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
16';-.1 ;;".'
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
17':;-:i ;::,3.
i_LLL LLLL LLLL LLLL LLLL LLLL LLL.L LLLL
192-j5;
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
200-~6~
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
208-;i~
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
2i6-?2~
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
224-;~i
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
~~~-~j9
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
24~-247
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
248-?5~
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
HLLL
~LLL
HLLL LLLL LLLL LLLL LLLL
1:::<-1Zt84r::0IZtF7So
1 9-084R€1I21F"(:::<
i,9-1Zt84i":00F"('9
This information is proprietary and il supplied by INTEROATA for the IOle
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unleu .pecifically authorized in writing.
89
14.3 D Bus ROM Controller (l9-142F47)
i-ii-ii-ii-i t-ii-ii-iri U-iHt-i i-iHHH i-it-it-iH HHHH Li-ii-it-i i-ii-ii-iH
i-iriHi-i t-ii-ii-ii-i
~i-ii-ii-i
HLHL HHHi-i i-iHHi-i Li-ii-ii-i
i-iLi-i~
i-iHi-iH i-ii-iHi-i Li-ii-ii-i HHHH Hi-iHH HHHH LHHi-i i-iHHi-i
- _. -
,-
.....
1::,1:::ii:,-'"1;'1
-:r:~1
t-ii-ii-iH t-ii-iHH Lt-it-ii-i i-iHLH HHHt-i HHi-iH LHHi-i
.i.l.~:.-j
i-ii-i~i-i
.i ::;.
HHi-iH HHt-iH Lt-ii-ii-i i-iLHL HHHH HHHH LHt-ii-i i-iLriL
i-ii-it-i;.; HHi-ii-i i_.i-i;..;t-i HHHH Hi-iHH i-iHHH Lht-it-i i-ii-ii-ii-i
144-:U:51
HHHH HHHH i-iHi-iH HHi-iH HHHi-i HHHH Hi-ii-ii-i i-ii-it-iH
Hi-iH;"; Ht-iHH i-ii-iHH Ht-iHH i-iHHH Hi-iHH i-iHt-iH HHi-it-i
HHi-iH i-iLt-iH Li-iHi-i HHLh i-iHHH HHHH LHi-iH HLHL
HHHH HHHH i-iHi-iH i-ii-iHH HHHH HHHH HHi-ii-i HHi-iH
192-:1.99
i-iHHH i-iHi-ii-i i-ii-iHH HHi-ii-i HHHH i-iHi-iH HHi-iH i-ii-ii-iH
206-;:1?J;··
i-ii-iHH i-iHi-ii-i HHi-ii-i HHHi-i HHHH i-iHHH i-ii-ii-ii-i i-1i-ii-iH
i-ii-ii-ii-i HHi-ii-i i-iHi-ii-i i-iHi-iH i-iHi-iH i-iHi-ii-i i-iHi-iH i-ii-it-iH
HHHH i-iHi-ii-i HHi-ii-i i-iHHH HHHH HHHH HHi-iH HHHH
i9-084R60F80
i-ii-iHH i-iHHH i-1HHH i-ii-iHH HHHH HHHH HHHH i-iHHH
HHi-iH i-iHi-ii-i i-ii-iHi-i i-ii-iHi-i i-iHHi-i HHi-ii-i i-iHi-ii-i i-ii-ii-ii-i
HHHH HHi-iH HHHH HHHH HHHH HHHH HHHH i-iHHi-i
Hi-iHH HHi-ii-i i-ii-iHi-i i-ii-iHH HHHi-i HHHi-i HHHH i-ii-iHi-i
90
This information is proprietary and is supplied by INTERDATA for the IDle
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unlnl specifically authorized in writing.
is'-084R00F86
15. EXTENDER BOARD OPERATION
The following steps H,ust be taken to insure proper Extender Board operation when troubleshooting any of the Processor
boards on the Extender Board.
1.
Remove the 35-537 CPB (lower Slot 7) to modify the CPU Clock speed. An octal switch is located in
IC position I 5E for this purpose. Switch positions 4 and 8 are to be ON for Extender Board operation.
No other switch positions may be placed in the ON position.
2.
Place the 28-015 Extender Board in the card file slot of the board to be tested. Note that there are
two sets of backplane pins on the Extender Board. Plug the board to be tested into the upper set of
pins and plug the Extender Board terminator card (see Step 3) into the lower set of pins.
3.
One of two terminator cards must be used for Processor Extender Board operation. The 35-598
Terminator is to be used with the CPA board on the extender, and the 35-599 Terminator is to be
used with any of the following: CPB, CPC, ALU, and IOU. The terminator is to be installed as
described in Step 2.
4.
For Extender Board operation of the CPA, CPB, or CPC, 24 inch extender cables (17-362 and 17-363)
are required.
This information is proprietary and is supplied bv INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
91
16. MNEMONICS
The following lists provide a brief description of each mnemonic found in the Model 8/32 CPA Schematic
Drawing 35-536D08, CPB Schematic Drawing 35-537D08, CPC Schematic Drawing 35-555008, ALU Schematic
Drawing 35-538D08, and IOU Schematic Drawing 35-539. The source of each signal on the respective schematic
drawing is also provided.
16.1 CPA Mnemonics, Schematic Drawing 35-536D08
MNEMONICS
MEANING
SCHEMATIC
LOCATION
ADA281 :311
Add-one-Ioop outputs
Sheet 3
AEQBl
Segment number equality
6EI
BOOO:310
B Bus
Sheet 13
Base selection delay
6J5
Bit 16 propagate signal
12N9
B Mux Enable A - S Bus
12N7
BMXNBI
B Mux Enable B - MDR
12L5
BMXNCI
B Mux Enable C, MLC/CA
12N5
BMXSLAI
B Mux Select Line A - Halfword MDR
12J8
BMXSLBI
B Mux Select B - MLC
l2L5
BR040:270
Base Register outputs
Sheet 6
BRWRI
Base Register Write Command
7N7
BSELOOI :041
B Bus Source Address
12J4
COOl
COlO
Carry Commands
Sheet I
C3XO
Carry past segment boundary
l2G8
CA3l0
Address Bit 31
3B8
CAl 20:300
Memory Address Bus
Sheet 8
CACLRO
Buffered Gear
IN8
CCO
Second HW Clock
IF9
CDOOO:310
Memory Data Bus
Sheet II
CDWO
Write Conversion Command
7M5
CKIA
System Gock
4M3
CLINTO
Gear Interrupt flip flop
7R8
CLOCKO
System Gock
4AI
CMCOOO:020
Memory Command Bus
Sheet 2
CPCOll/00l
Increment Commands
2F5
CRDYO
Memory Ready (response)
lA2
CREQO
Memory Request
lR2
CSOOO
Control State 0
2G8
CSTAO
Gear Status Register
7R8
DREQO
Data Request
lR7
FSRO
Status Register flip flop
7G8
GTO/l
Greater Than segment limit
12G7
INCR021
Increment MLC by Two HW
IOM7
BDLYO
BIT161A
BITl61B
BMXNAI
1
COIl
This information is proprietary and i. supplied by INTEROATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
92
not be used for any other purpose unless specifically authorized in writing.
MNEMONICS
MEANING
SCHEMATIC
LOCATION
INCRI
Increment MLC by One HW
10M6
IRI
Instruction Read decode
2K7
IR27l:3ll
Status Register outputs
Sheet 7
IREQO
Instruction Request
IRS
LDMARO
Load MAR
2C7
LDMCLO
Load MLC
2B6
LDMDRO
Load MDR
2D8
LDUIRO
Load mR Clock
4M2
L1MEI
limit violation
6N6
MAIO
Memory Access Interrupt
7R4
MALX120:230
Address Multiplexor outputs
Sheet 8
MARl21 :311
Memory Address Register outputs
Sheet 3
MARPUl
Pull up resistor
Sheet 3
MCOOO:030
Microcontrol field
Sheet 2
MCLKO
Memory Data Clock
4F3
MDROOl:311
Memory Data Register outputs
Sheet 4
MDRCLO
Memory Cycle Clock
IB2
MDXOOI :ISl
MDR input Multiplexor
Sheet 11
MLC12l:311
Memory Location Counter outputs
Sheet 3
MSIGO
Module Signal
10RS
NWI
Write Inhibit
7M2
PROn
Enable Protect/Relocate
2G4
PSW210
Program Status Word Bit 21
2D4
RGENO
B Bus Register Enable
12N6
RHO
Read Halfword Command
2F8
RI02Q
R12 format
IOE3
RQFFO
Request flip flop
IN2
RRSFI
RR or SF format
IOD3
RSTR/O
Read Status Register
7R9
RXOOI
RX format
Sheet 10
RX2FO/l
RX2 flip flop
IOK4
RX3DO
RX3 Format decode
10RS
RX3ENI
RX3 decode enable
10KS
RX3Fl/0
RX3 flip flop
10KS
RXIDO
RXI decode
10M3
RXILO
RX3/RI2 format
10MS
SOUO:lSO
Part of S Bus
Sheet S
S160:310
Part of S Bus
Sheet S
S2BO
S Bus to B Bus Override Command
12G6
SCLRO
System Clear
U8
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
93
MNEMONICS
MEANING
SCHEMATIC
LOCATION
SDRI
Data Read Command
2N2
SDRDWI
Data Read/Write Command
2SS
SDWI
Data Write Command
2N2
SEGWEA/B
Base Register HW Write
Sheet 6
SIRI/0
Instruction Read Command
2J6
SMCOOO:030
Buffered MC field
Sheet 2
SROOO:310
S Register outputs
Sheet 5
SROOI :311
S Register outputs
Sheet 5
SRCKO
Status Register Oock
7CS
SRTRO
Status Register Trap
7N6
SSELOOI :041
S Bus Address Select Bus
2A7
STBO
Strobe
12M2
SM2X12l:31l
Summer two outputs
Sheet 9
SX280:310
Second Index Register Address
Sheet 11
UDR280:310
User Destination Register Address
Sheet 5
UIR240:310
User Instruction Register
SheetS
USR280:310
User Source Register Address
Sheet 5
XPUl
Pull up resistor
6ES
94
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
16.2 CPB Mnemonics Schematic Drawing 35-53 7D08
MEANING
MNEMONICS
SCHEMATIC
LOCATION
A140:270
A Bus Bits 14:27
Sheet 5
A280:A310
A Bus Bits 28:31
Sheet 4
AENO
Enables ASEL Multiplexor
3F5
ASELOOI :041
Selects Register containing A Operand
Sheet 3
ATNOOO:030
Interrupt Attention lines.
Sheet 12
AYDSI/O
ASEL Multiplexor select line
3E3
BOOO:310
B Bus Bits 00:31
Sheet 6
B280:310
B Bus Bits 28:31
Sheet 2
BALAO
Branch and Link, ARM Interrupts
14J9
BDCO
Branch and Disarm Console Interrupt
14J8
BENO
Enables BSEL multiplexor
317
BSELOOI :041
Selects Register containing B operand
Sheet 3
BYDSO
BSEL Multiplexor Select line
3K8
CIX071 :141
ROM Address: Traps or Op-Code pointers
Sheet 8
C2XIOl: 151
ROM Address: B Bus or ROM Instruction Register indirect field
Sheet 8
CCCO
Carry Condition Code
4D6
CCCLKO
Condition Code Clock loads PSW
4M7
CFLGI
Carry flag
4F6
CLKO
CPU Clock
13N4
CLKIA
CPU Clock
13N4
CLKIB
CPU Clock
13N3
CSOOO:030
CPU Control States
Sheet 14
CSA041 :091
ROM Address
Sheet 9
CSAljO
Counter State A
14M2
CSAIOO:150
ROM Address
Sheet 8
CSBI/O
Control State B
14M3
CSDOOI :311
ROM data
Sheet II
CSREFO
Denotes control store reference
5N3
CSWRTO
Control Store Write
IIG4
DI
Decode Bit
llN6
DREQO
Data Request
13A3
DSPYLO
Display Interrupt
12A4
EI
Execute Bit
llN5
ENFLGI
Enable PSW flags
llR3
ENPGOO:40
Page enable for ROM
Sheet 10
ENSMXO
Enables S Bus multiplexor
7F9
ENYSDXO
Enables YSI/YDI to B Bus
3S5
EXECI/0
Execute Bit of micro-code
5Nl
FLGCLKO
Flag Clock latches Condition Code
4K8
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
95
MNEMONICS
MEANING
SCHEMATIC
LOCATION
FSELOOO:030
Function Select lines
Sheet II
FYXO
User index enable
3D5
GBIMO
Gate Immediate field to B Bus
6D9
GCCO
Greater Than Condition Code
4D8
GENO
Generate interrupt
12K4
GFLGI
Greater Than flag
4F8
GPSWAO
Enables PSW selection
3M3
ILEGA
megal Instruction
12KI
ILEGB
megal Instruction
12K2
ILEGC
megal Instruction
l2K2
INCLKO
Oock Inhibit
13H1
IREQO
Instruction Request
13AI
INTI/O
Interrupt present
12N6
JB041 :151
Jam address Bits 04: IS
Sheet I
JUTYI
Discriminates between RXI, RX2, or RX3 Instructions
14AI
KLCLKO
Disables CPU clock for manual testing
lR8
KSIGO
Extension of FSEL field
llN5
LCCO
Less Than Condition Code
4D9
LFLGI
Less Than flag
4F9
MAl
Memory Access Controller
12B8
MB041: 151
Match Address Bits 04: 15
Sheet 1
MCOOO:030
Memory Control field
Sheet 11
MMFO
Machine Malfunction interrupt
12B5
MNCLKI/0
Manual Oock (P.B. switch)
Sheet 1
MODOOO/OOI
Module zero
5Ml
MPENO
Memory Protect enable
12H9
MSELOOO:020
Module Select lines
Sheet II
MSIGO
Module
MTCH
LED indicator signals address match
IS6
MTCHI
Stored xMATCHI
!
Do not ta~e branch
IM6
PASSI/O
si~al
14AI
14K8
i
PCLKO
CPUOoc~
13N3
PPFO
Primary Power Fail
12B6
PRIV
Privileged ftstruction
12Kl
I
I
I
PSW141 :271
PSW Bits 1:4:27
Sheet 5
PSW281 :311
PSW Bits 28:31
Sheet 4
PSWCLKI
PSWOock
4K9
RIROOO:310
ROM Instruction Register
Sheet 11
RIR201A
Bit 20; ROM Instruction Register
6D9
Thl. information i, proprietary and i, lupplied by INTER DATA for the IOle
96
purpose of using and maintaining INTERDATA IUPPUecI equipment and ,hall
not be used for any other purpo18 un'.' specifiCilly authorized in writing.
MNEMONICS
MEANING
SCHEMATIC
LOCATION
RIRCLKO
ROM Instruction Register Clock
IlH8
RLC041 :151
ROM Location Counter
Sheet 9
RLR041 :151
ROM Location Register
Sheet 9
RRXINHO
Inhibits transfer in RRX micro-instructions
14HI
RUN I/O
Run mode
Sheet I
RX3DO
RX3 instruction
2H3
SOO:310
S Bus Bits 00:31
Sheet 7
S2BI
Gates S Bus data to B Bus
14G4
SAMAI
ROM Address Select line
5R4
SAMBLl
ROM Address Select line
5N5
SAMBMI
ROM Address Select line
5N4
SAMCO
ROM Address Select line
5N2
SCCO
Signals new Condition Code available
4G8
SCLRI/O
System Oear
14A5
SETRLCO
Sets CPU to CS031 as a result of JAM
IM5
SINO
Single Step Oock switch:normally open contacts
118
SINC
Single Step Clock switch:normally closed contacts
119
SLMDRI
Select MDR
3E8
SLYDDl
Select YDD
4M2
SPSWI
PSW Select line
4M3
SR280:31O
Status Register Bits 28: 31
Sheet 4
SRCLKI
Status Register Clock
4H3
SSELOII :041
Destination Register Select lines
Sheet 4
STRTl/O
Module Start Signal
l4M5
SX280:31O
Second Index field
Sheet 2
SX2NZI
Secondary Index field is non-zero
3E8
SYNC-TP
Test Point: Match Address
lN6
TENO
Trap Address enable
12J4
TKILLO
External TP for inhibiting clock
13Ml
TRAP I 21
Interrupt Trap Bit 12
12H8
TRAPI30: ISO
Interrupt Trap Bits 13:15
Sheet 12
UlR240:31O
User op-code
Sheet 8
USR280:310
User Source Register Select lines
Sheet 2
VCCO
Overflow. Condition Code
4D7
VFLGI
Overflow flag
4F7
XMTCHI
ROM Address compares to Match Address
lH6
XS010:040
Destination Register Address
Sheet 4
YDCLKO
User Destination Register Oock
2E2
YDPIFO
YDPI enable
3E3
This information is proprietary and is supplied by lNTEROATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
97
MNEMONICS
MEANING
SCHEMATIC
LOCATION
YDX281:311
User Index field
Sheet 2
YS280:310
User Destination Register
Sheet 2
YSIXO
Selects YSI/YDI to B Bus
3SS
98
This information is proprietary and is supplied by I NTER OAT A for the IDle
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authori~ed in writing.
16.3 CPC Mnemonics, Schematic Drawing 3S-SSSD08
MEANING
MNEMONICS
SCHEMATIC
LOCATION
AOOO:310
A Bus
AADOOO:040
A Stack Address Bus
Sheet 4
AADOSI
A Stack Address Bit S
Sheet 4
AKLO
A Stack PSW suppress
4GI
ASELOOI :041
A Bus Select Bus
Sheet 4
ASTKNO
A Stack enable
4K4
BOOO:310
BBus
Sheet 2
BADOOO:040
B Stack Address Bus
Sheet 4
BADOSI
B Stack Address Bit S
4L2
BKLO
B Stack PSW suppress
4G2
BSELOOI :041
B Bus Select Bus
Sheet 4
BSTKNO
B Stack enable
4KS
M37XO
Floating-Point Module Select
4Al
PSW260
PSW Bit 26
SH6
PSW270
PSW Bit 27
5H7
RWCO
Read/Write Control
5A2
SOOO:310
SBus
Sheet 3
S2BO
S Buffer to B Bus Over-ride command
4A4
S37XO
Stored floating point Module Select
4A3
SBOOI :311
S Buffer outputs
Sheet 3
SODDO
S Bus Odd Register command
5F2
SSELOOI :041
S Bus Select Bus
Sheet 4
SSELXO
Stack Load Select
4G4
STWRTI
Start Write command
SA3
WSELt
Write Select
SK4
WSELlB
Write Select buffered
5N9
WCLKO
Write Oock
5H5
XCLKO
Buffered Oock
SC4
. Sheet I
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
·99
16.4 ALU Mnemonics, Schematic Drawing 35-538D08
MNEMONICS
MEANING
SCHEMATIC
LOCATION
AOOO:310
A Bus
Sheet 10
ACLKI/O
ALUClock
Sheet 6
ACLKA/BO
ALUOock
Sheet 6
ACNT051
Bit 5 of iteration counter
4N4
ACRYI
Carry from iteration counter
4R4
AGLOOI
Bit 0 A input to shift left multiplexor
8R7
AGL311
Bit 31 A input to shift left multiplexor
8H8
AGROOI
Bit 0 A input to shift right multiplexor
Sheet 8
AGR081
Bit 8 A input to shift right multiplexor
Sheet 8
AGRI61
Bit 16 A input to shift right multiplexor
Sheet 8
ALOOI:311
A latch outputs
Sheet 10
ALOGI/O
Logic mode
9M8
ALS080:11O
Shift multiplexor outputs Bit 8: II
Sheet 12
AMOOI :311
A multiplexor outputs
lOC5
AMODOOI :031
Function select control for ALU
Sheet 9
ARITHI/O
Arithmetic shift
lL6
ASOOO:030
Arithmetic State
Sheet 5
ASOOI
Arithmetic State
5F8
ASAI
Arithmetic State register A
5N5
ASBO
Arithmetic State register B
5N5
ASIGNI/O
Stored sign of A Bus operand
3G4
AWCI
Add with Carry instruction
IL2
AXBI
Stored Exclusive-OR of Sign bits of A and B operands
6E3
BOOO:310
BBus
Sheet 10
BGOOI :311
B gate outputs
Sheet 10
BGTRI/O
B Operand is Greater in CAE instruction
6D2
BSIGNI/O
Stored Sign of B Bus operand
6E3
CAEI/O
Floating Point Compare and Equalize instruction
ILl
cern
ce Bus -
C bit (carry)
2N8
CCCLKO
Condition Code Oock
2E3
270
Carry in Bit 27
230
Carry in Bit 23
190
Carry in Bit 19
CIN 030
Carry in Bit 3
ISO
Carry in Bit I 5
110
Carry in Bit II
310
Carry in Bit 31
This information is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining INTER DATA supplied equipment and shall
100
not be used for any other purpo,e unless specifically authorized in writing.
Sheet 9
MNEMONICS
MEANING
SCHEMATIC
LOCATION
COUTOOO
Carry out Bit 0
9H9
COUT080
Carry out Bit 8
9E8
DFLTO
Divide Fault
3E2
DVI/O
Divide instruction (fixed or floating point)
lL7
EAO
Floating Point Add instruction
IF2
EASI
Floating Point Add6Subtract instruction
IL2
ECOUTO
Exponent carry
8Dl
EDl/O
Floating-Point Divide instruction
ILl
ECI
Floating Point Compare instruction
lL3
EMI/O
Floating Point Multiply instruction
lL4
EMDl/O
Floating Point Multiply /Divide instruction
lL4
ESO
Floating Point Subtract instruction
IF2
FAXBI
Stored Exclusive-OR of A and B Sign bits
9N6
FDI/O
Fixed Point Divide instruction
lL8
FMl
Fixed Point Multiply instruction
IL8
FMDl/O
Fixed Point Multiply /Divide instruction
IL8
FSELOOO:020
Function Code from CPU
Sheet I
FSTCNTl/O
First Count of arithmetic state 2
6F8
FXS011
Bit I, exponent sum
8E6
FXS021 :071
Exponent ALU outputs
Sheet 8
GOO I
Carry generate Bit 0
IOF2
G041
Carry generate Bit 4
llF2
G081
Carry generate Bit 8
12F2
Gl21
Carry generate Bit 12
13F2
Gl61
Carry generate Bit 16
14F2
G201
Carry generate Bit 20
ISF2
G24l
Carry generate Bit 24
16F2
G281
Carry generate Bit 28
17F2
GATECCl
Gate Condition Code
3G3
GATEECl
Gate Floating point Condition Code
3R7
GCCO
CC Bus - G bit (greater than)
2RI
GLOWl
Carry generate Bits 16 to 31
9G3
Shift Multiplexor Output control
Sheet 7
GNPO
GNMO
GNO
}
GRWCO
GXO
Generate
~ead
Write control
I
Shift Multiplexor output control
.'
6K8
7H8
GXLSBO
Shift Multiplexor output control
7H8
INHAl
Inhibit A Bus
7E6
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
101
MNEMONICS
MEANING
SCHEMATIC
LOCATION
INHBO
Inhibit B Bus
7E6
INHXl/O
Inhibit exponent
7H5
KSIGO
Function Code Extension bit from CPU
lA7
LCCO
CC Bus - L bit (less than)
2Rl
LOGI
Logical shift
lLS
Ml/O
Multiply look-ahead bit
7R6
MDO
Multiply/Divide instruction (fixed or floating point)
lL7
MFINO
Module Finish signal
2J4
MQ001:311
MQ register outputs
Sheet 10
MQCLKO
MQ register Clock
6R7
MQGOOI
Bit zero input of MQ Shift register
7S8
MQG311
Bit 31 input of MQ shift register
7S9
MPO
Multiply instruction (fixed or floating point)
lL7
MSELOOO:020
Module Select code from CPU
Sheet 1
MSIGO
Module Signal (ALU=carry flag)
2R2
NLRZO
Normalize
SC4
OCMPI
Control signal (one's complement) for CAE instruction
8E2
OCMPLI
Stored Control Signal - one's complement
6E3
OFLl/O
Exponent Overflow
4E2
POOl
Carry propagate Bit 0
IOF2
1'041
Carry propagate Bit 4
llF2
1'081
Carry propagate Bit 8
12F2
Pl21
Carry propagate Bit 12
13F2
Pl61
Carry propagate Bit 16
14F2
P201
Carry propagate Bit 20
ISF2
P211
Carry propagate Bit 24
16F2
P281
Carry propagate Bit 28
17F2
PLOW 1
Carry propagate Bits 16 to 31
9G2
ROTI/0
Rotate shift
lL6
ROTRO
Rotate Right shift
lLS
RWCO
Read Write Control signal to CPU
6M8
RWCAI/O
Read Write Control
6F7
RZROI
Remainder Zero flip flop
7Gl
SOOI:311
ALUsum
Sheet 11
SOOO:310
Sum Bus
Sheet 10
SAPI/0
Shift multiplexor select control
7H4
SBGTRI/O
Set B Greater flip flop
3H3
SCOIO:OSO
Arithmetic Shift Count
Sheet 4
SELAOA/B
A multiplexor select control
8RS
SEPI/O
Shift Multiplexor select control
7ES
SETZAO
Inhibits Bits 0:8 in detection of zero sum (ZSUMl)
lOH2
This information is proprietary and is supplied by INTERDATA for the IOle
purpose of using and maintaining INTEAOATA supplied equipment and shall
102
not be used for any other purpose unl... specifically authorized in writing.
MEANING
MNEMONICS
SCHEMATIC
LOCATION
SGAETO
S Bus enable
7M2
SGCCO
Set Greater than Condition Code
3N7
SGROOI
Bit 0 S input to shift right multiplexor
8G9
SHFTl/O
Shift instruction
lL9
SLl
Shift Left control
7N4
SLCCO
Set Less than Condition Code
3N7
SOFLO
Set exponent overflow
8J8
SRI
Shift Right control
7N4
STRTO
Start signal from CPU
IA9
SUFLO
Set exponent underflow
8J8
SUMI/O
Add/Subtract mode
9K4
SVCCO
Set Overflow Condition Code
3LS
SWCO
Subtract with Carry instruction
lL2
TDFLTl
Toggle Divide Fault
6G9
UFLl/O
Exponent Underflow
4G6
VCCO
CC Bus - V bit (overflow)
2R2
XFRO
Forces S=A on ALU function control
9MS
XLOADO
Load pulse for exponent up/down counters
8G7
XOVFl
CAE Instruction; exponential difference is greater than five
8R4
XRPA/B/C/D
Pullup resister for unused logic inputs on IC's (1 k ohm to PS)
7Gl
SXOll :071
Expojent result (stored)
Sheet 8
XSIGNI
Sign of floating point result
3H6
ZSUMI/0
Sum is zero
IOJ4
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unl... specifically authorized in writing.
. 103
16.5 IOU Mnemonics, Schematic Drawing 35-539D08
MNEMONICS
MEANING
SCHEMATIC
LOCATION
AI
Output of address decoder for TTY
9H3
A160:3IO
A Bus low
Sheet 3
ACI/3
12 VAC inputs to Primary Power Fail Detector
15B2
ACKOOO:030
Acknowledge interrupt MPX Channel
Sheet 6
ADAI
Address flip-flop for TTY controller
9M3
ADBI
Address flip-flop for Display
9M4
ADRSO
Address Control line, MPX channel
6N4
ADSYNAO
Address SYNC for TTY controller
9L2
ADSYNBO
Address SYNC for Display controller
9L4
ARMI
Interrupt Arm flip-flop for TTY
917
ATNO
Interrupt Attention for TTY
12G7
ATSYNO
Attention SYNC pulse for ACK address
12N9
Bl
Output of address decoder for Display
9H4
B160:310
B Bus low
Sheet3
BAI/O
Buffer Active flip-flop (sets when buffer is loaded, cleared when
buffer unloaded)
8E8
BLKI/O
Serial feedback block flip-flop
9N6
BROOI :071
Buffer Register-eight stages, (active only in Read mode)
Sheet I I
BRKO
Break detect signal status Bit L
8H7
BSYI/O
Busy signal (Status Bit 4)
CA310
Least Significant Bit of address from CPU (byte steering bit)
IB5
CATNI/O
Console Attention flip-flop
lOGS
CCCO
CC Bus - C Bit
7R4
CL070
Primary Power Failure Control line
14K7
CLDRb
Gear line for D Bus receivers
5K5
CLKO/!
Timer clock pulses (11 for character)
12L4
CLRAO
Gear line for cycle counter
5R7
CLRCO
Gear line for timing, flip-flop
5H8
CLRSTO
Gear ST flip-flop
12E4
CMCRO
Gear MCRl I: I 5
7C7
Gear lines for Machine Control Register
Sheet 7
CMDO
Command Control line, MPX channel
6N4
CMGAO
Command line for TTY controller
ION4
CMGBO
Command line for Display controller
IONS
DOOO:150
DBus
Sheet 4
DAO
Data Available Control line, MPX channel
6N4
DAGAO
DA line for TTY controller
lONI
CMCRllO
}
CMCRI30:150
This information is proprietary and is supplied by INTERDATA for the sole
104
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
MNEMONICS
MEANING
SCHEMATIC
LOCATION
DAGBO
DA line for Display controller
ION9
DBENI
D Bus Enable
6G4
DCKHI
aock for D Bus receivers high
6AS
DCKLl
aock for D Bus receiver low
6B5
DOl 10
Device data signals from Schmidt Trigger receiving circuit
16E7
DFSTl/O
Timing Control flip-flop, Detects DSTRT
SES
DLOO:070
Buffered D Bus
Sheet 8
DLOOX
Strap to TTY address decoder
9E4
DMPFO
Data Memory Parity Fail (from MBC)
7E4
DRO
Data Request Control line, MPX channel
6H4
DROOl:lSI
D Bus receivers
Sheet 6
DRGAO
DR line for TTY controller
ION2
DRGBO
DR line for Display controller
ION8
DRNI/O
Start Bit stage of Shift Register (controls transmit line in Write mode)
llM6
DSPLYO
Display controller interrupt line to CPU
IOJ8
DSTRTO
Start D Bus operations
5H9
DSYNI
5D6
DTl/O
Device Transmitting flip-flop (set when RCV loop starts the timer)
llG7
DTMGO
Delayed TMG signal
12C4
DUl
Output of Device Unavailable detector-Active for TTY in DEF /local modes
16J5
DXl
Serial data input to Shift Register (line data in Read mode/all ones in
Write mode)
llB2
EBLl
Interrupt Enable flip-flop for TTY
9J6
EOCI/O
End of character (output of charader counter)
12N6
}
Enable signals for S Bus high
Sheet 2
}
Enable signals for S Bus low
Sheet 3
ENT30
Enter Time period T3
SN2
EPFI/O
Early PPF Timer (l millisecond)
14L2
Complimentary pulsed signals from Display Console
IOAS
Examine bit of TTY status
8J8
Auxiliary initialize inputs
14A3
FLSYNO
False SYNC signal (D Bus operation)
14K8
FPOWO
Decoded Power Down function
7C7
ENSHAO
ENSHBO
ENSHtO
ENSLAO
ENSLBO
ENSLCO
ESNCO
ESNOO
}
EXI
EXAO
EXBO
}
This information is proprietary and is supplied by I NTER OAT A for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
, 105
MNEMONICS
MEANING
SCHEMATIC
LOCATION
FSELOO:03
Function Select lines from CPU
Sheet 1
FSTPO
Stop function-terminates SHFf pulses
12M5
FfXI/O}
Displays controller SYNC generation flip-flops
Sheet 13
FWAITI/O
Flip-flop for load Wait function
7E8
GACKO
Gate Acknowledge function
6G2
GADRSI
Gate ADRS line
6R3
GeCO
FlY 110
CC Bus - G Bit
7R2
GeMDl
Gate Command
6M3
GDAI
Gate Data Available line
6M3
Gating on D Bus signals
Sheet 4
GDINI
Gate Data In
6K3
GDOUTI
Gate Data Out
6M3·
GDRI
Gate Data Request
6H3
GLABI
Gate LA and LB signals
13G4
GLITCHO
Start Glitch signal- clears TMGl
12B2
GPI/O
Gate POUT function
lK6
GPXO
POUT function finished signal
IN6
GSRI
Gate Status Request
6J3
GSTPI
Gate STP (test point)
15K8
GSTRTl
STRTO gated with IOU decoded address
IN8
HWI/O
Halfword test line - MPX channel
512,5K2
INCRI/O
Increment/Normal flip-flop
lOD2
INITO
INT key line from Console
14A3
INTRI
TTY interrupt flip-flop
12E8
IRLMPO
Instruction Read Local Memory Parity Fail (from MBC)
7E3
Cycle counter flip-flops
Sheet 5
KCO/l
Timing Control flip-flop, Control line timing
5F3,5H4
KDI/O
Timing Control flip-flop Control line timing
5M6
KSIGO
Function code line from CPU
184
KSYNI/O
Timing Control flip-flop, SYN stretch
5H8
KTl/O
Cycle counter-Terminate flip-flop
5N6
KTM
Test point. Ground to kill Start Timer
14B5
®mmo}
GDLBHO
GDLBCO
GDAO
. KA
KB
KY
KX
}
}
5L8
Johnson Counter flip-flops for address cycle
This information is proprietary and is supplied by I NTER OAT A for the sole
106
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
5M8
MNEMONICS
}
LBO
LAO
MEANING
SCHEMATIC
LOCATION
13J5
Signals controlling the loading of display registers
13J6
LCCO
CC Bus - L Bit
7R2
LDBRO/I
Load Buffer Register pulse (active in Read mode only)
8C7
LDWAITO
Decoded Load Wait Indicator function
7C8
LESYN1/0
Timing Control flip-flop Detects leading edge of SYNC
5H2
MCROOI:091
MCR straps
Sheet 2
MCR11O:150
Machine Control Registers
Sheet 7
MFINO
Module Finish line to CPU
7N8
MMFO
Machine Malfunction interrupt line to CPU
7G6
MSELOOO:020
Module Select lines from CPU
lC8
MSIGO
Module Finish line to CPU - Tests the state of HW line
7N9
MSYN1
SYNC from Display or TrY controllers
llD8
Master TTY Timer (440HZ Output)
12J3
Timer clock counter (110HZ Output)
12H4
Overflow error flip-flop
8G8
Pulse output functions (test points)
Sheet I
PFDTO
Power Fail Detector output
1403
PF1/0
Primary Power Fail flip-flop
14H5
POFFO
Power Off line from Console switch
14A3
POUTO
Pulse Out function
7C7
PPFO
Primary Power Fail interrupt line
14K6
RACKO
Receive Acknowledge interrupt signal
12F9
RDWDHI
Read-Write Data Halfword
6G4
RN
Negative side of RECEIVE loop
16H8
RP
Positive side of RECEIVE loop
16H6
RSTO
Reset line for Display controller
lOG3
S160:230
S Bus high
Sheet 2
S240:310
S Bus low
Sheet 3
scco
CC Bus - Strobe line
7R6
SCLRO/l
System initialize line MPX channel
15K2
SDOOI :071
Bi-Directional byte bus to Display Panel
Sheet 8
SELSHO/l
Select signal for S Bus high
2Nl
MTAO/l }
MTBO/1
}
MTC1
MTDl
OVI/O
PAO
PBO
PCO
PDO
)
This information is proprietary and is supplied bv INTERDATA for the IOle
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
107
MNEMONICS
SELSLl
SHIO
SLOO
}
MEANING
Select signal for S Bus low
Signals for sensing Display Console's Switch Register
SCHEMATIC
LOCATION
3F2
13J7
13J8
SHFTI/O
Shift Register pulses, nine per character
12N4
SKTl
Set KT flip-flop
SN3
SMCRO
Sense MCR 00: IS
7C7
SMFINO
B Bus operation finished signal
IL9
SNGLO/l
Single mode flip-flop
lOG8
SRO
Status Request Control line, MPX channel
6H4
SROOI :071
Shift Register-eight data stages
Sheet II
SRGO
SR for Display Panel
lON6
SRGAO
SR line for TTY controller
lON3
SRGBO
SR line for Display controller
ION7
SSGLl/O
SNGL key line from Display Console
lOA8
STO
Start idle Timer flip-flop
12E4
STCI
Start gating on S Bus (non-D Bus operation)
2H4
STCLKI
Oock for ST flip-flop
l2C3
STDI
Start gating on S Bus (D Bus operation)
2H5
STESI
Set TESYN flip-flop
STMAO
Start Timer
l4F5
STMBO/l
Start Timer flip-flop
14G8
STPI
System Stop flip-flop
14N5
STPIA
Buffered STPI (test point)
14NS
STPFI/O
Start Power Fail Timer latch
14H3
STPFRO
Start Power Fail routine
14F2
STRTO
Module Start line from CPU
IC7
STTl
Start display controller timer
13E3
SYNO
SYNC test line - MPX channel
SAS
SYNO
SYNC test line MPX channel
IlG9
TACKO
Transmit Acknowledge interrupt signal
12N8
TBO
Delay Control line, flip-flop
,SB4
TCI/O
Timing Control delay pulses
S9B
TDU
Device Unavailable line from TTY
16H4
TERM I
Timing Control flip-flop, Detect trailing edge of SYNC
SE6
THWO
Decoded Test Halfword function
7C7
TMGO/I
Timing gate control flip-flop
1201
TMGIA
Timing gate test point
12NI
TN
Negative side of SEND loop
16HI
TP
Positive side of SEND loop (TTY)
16H3
108
This information is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specificallV authorized in writing.
MNEMONICS
TRNSO
TXO!I
TYO/l
MEANING
Transmit signal to SEND loop
}
SCHEMATIC
LOCATION
16Fl
13G2
Display controller timer
1313
VCCO
CC Bus - V Bit
7R4
WAITl
WAIT light control
13J9
WRTl/O
Write mode execute flip-flop for TTY
12D3
WTl/O
Write mode storage flip-flop for TTY
9N7
XAI/O
Flip-flop for gating LA and LB
13FS
XCI/O
Flip-flop for gating SH, SL
13F7
XLCI/O
line check flip-flop (checks for START glitches and break conditions)
IlM7
XPFI/O
Power Fail stop timer
14LS
XRPA
Pull-Up resistor
13FS
XRPB
Pull-up resistor
SL7
XRPD
Pull-up resistor
9M3
XRPE
Pull-up resistor
7E8
XRPF
Pull-Up resistor
7Fl
This information is proprietary and is supplied by INTEROATA for the sale
purpose of using and maintaining INTEADATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
,.09
3S-SSSFOIA20
September 1975
MODEL 8/32
WRITABLE CONTROL STORE
INSTA.LLATION SPECIFIC.ATION
INTRODUCfION
The Writable Control Store (WCS) is an option which extends the flexibility of the user level Processor to that of the
micro-machine. The WCS has the capability of storing and retrieving data within the control store, plus the capability of
dynamically altering control store instructions. In effect, the micro-programmer has the full capability of the user level
machine at micro-processor speeds.
The WCS offers 2KB of control store, sufficient to contain 512 instructions or some com bination of instructions and data.
It is contained on the 8/32 CPC Processor board and requires typically 7 Amperes of SVDC for power.
This specification provides the necessary information for the installation of the 8/32 Writable Control Store (WCS) option.
PHYSICAL CHARACTERISTICS (3S-SSS Board also includes 8/32 CPC)
Dimensions - Board IS" x IS"
Weight - 6lbs. (approximately)
Power - SVDC at 10 Amperes maximum
Hardware
one
one
one
one
additional power supply regardless of expansion.
3S-SSSFOI Board
17-360 front edge ribbon cable
illegal instruction ROM on 8/32 CPB ROM.
UNPACKING·
When the WCS option is shipped with a system, it is installed at the factory. All cables and printed circuit boards should be
inspected to ensure proper seating.
INSTALLATION
Slot 6 of the Basic Processor lower chassis is used for the 8/32 WCS option. The WCS is mounted on the 3S-SSSFOI board
(the 8/32 Processor CPC board).
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized In writing,
Power
An additional power supply, regardless of configuration, has to be used to provide an extra 5VDe (P5) source for WCS. See
Figure I.
MODEL
8/32
JUMBO
Figure 1. 8/32 Basic Processor With wes and/or DFU Power Wiring
Cabling
The 17-360 cable connects Connector 4 on the CPB and cpe Processor boards.
Strapping
Refer to the Writable Control Store Maintenance Specification, 35-555FOIA21 for strapping details.
Testing
Upon completion of the installation, and before power is applied, all voltages should be checked for shorts between each
other and ground. Proper operation of the wes is tested by the execution of the WCS Test Program, 06-192.
Other
lllegal instruction ROM, 19-084F43, on the 8/32 ePB board (35-537) at Location ooe must be replaced by 19-084F48.
This information is proprietary and is supplied by INTEROATA for the IOle
2
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unle'SS specifically authorized in writing.
35-555FOIA21
September 1975
WRITABLE CONTROL STORE
MAINTENANCE SPECIFICATION
INTRODUCfION
The Writable Control Store (WCS) is an option which extends the flexibility of the user level Processor to that of the
micro-machine. The WCS has the capability of storing and retrieving data within the control store, plus the capability of
dynamically altering control store instructions. In effect, the micro-programmer has the full capability of the user level
machine at micro-processor speeds.
The WCS offers 2KB of control store, sufficient to contain 512 instructions or some combination of instructions and data.
It is contained on the unused half of the 8/32 CPC Processor board and requires typically 7 Amperes of 5VDC for power.
This specification describes the functional operation of the Model 8/32 Writable Control Store and provides information
necessary for its maintenance. This specification references CPC Functional Schematic 35-555008. INTERDATA schematic title, drawing number, and sheet number are located in the lower right corner of each sheet. Each sheet is zoned
alphabetically across the top and bottom margins and numerically down the side margins. These schematics are referenced
throughout the block diagram and functional analysis text to correlate specific locations on the schematics to the text.
When a specific location is referenced by the text, a number-letter-number is used to designate schematic sheet number,
and zone location within the sheet. For example, schematic reference (3B5) is found on Sheet 3, at the intersection of
Zone Band 5.
BLOCK DIAGRAM ANALYSIS
Data is stored in a 512 x 32 bit array subdivided into two pages, Le., A and B. Each page stores 256 fullwords of data. Each
page is further delineated as a high half which stores Data Bits CSDOOl:151, and a low half which stores Data Bits
CSD161 :311. Data to be written into the Writable Control Store is derived from the backpanel A Bus, buffered, and
fanned .out to Pages A and B. See Figure I.
The address to be read (or written) is derived from the Control Store Address lines (CSA) 04:15 originating on the 8/32
CPB board. The four most significant address lines (CSA 04:07) are strapped to enable a selectable address range for the
WCS. The eight least significant address lines are buffered directly as AO:A7, and select one out of 256 addresses within
each page.
FUNCTIONAL SCHEMATIC ANALYSIS
Storage Device
The basic storage element used in the WCS is the 19-077 static bi-polar Random Access Memory (RAM) employing tri-state
output, organized 256 words by one bit. It is intended for high speed memory applications where low input loading on
chip address decoding, and high capacitive drive capability are required. See Table I.
The three state output has the characteristic TTL totem pole output with active elements driving both the ONE and ZERO
output voltage levels, plus the capability to disable both driving elements to a high impedence state when the device is not
selected. The data output can then be tied to a common output bus which can be driven by only one active output or a
passive pull-up.
The memory device (19-077) is addressed with the AO-A 7 inputs which select one of 256 words. The chip is enabled by
making all Memory Enables, Pins 3, 4, and Slow. If any of the Memory Enables are high, the chip is in the high impedence
state. If the Write Enable Pin 12 is high and the chip is enabled, the stored data (complement of data applied at input
during write cycle) is read on the output pin. If the Write Enable Pin 12 is low and the chip is enabled, the data on the
input pin is written into the addressed word.
This information is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
CSA080:150
TIMING
AND
CONTROL LOGIC
ADDRESS
BUFFERS
"-
PCLKO
-
CSWRTO
...
I
.
CSA040:070
1
ADDRESS
STRAPS
u
u
,...
t---
0
u
Icc
t.i
0
«
0
0
«
0
3:
Z
w
';t;
0
0
III
0
>
w4
,...0
III
0
Ul
«
-
PAGE A
(EVEN)
HIGH HALF
0
0
Ul
U
I-
cc
3:
PAGE B
(ODD)
HIGH HALF
«0
«,...
«
«0
z
w
>
w
Ul
u
Icc
'~',}",.,.,"'i"""""""'~.~.·• • • .~.·• .•.,•-'
•.•',. ~'__ _ _ _ _ _ _ _..:..I_ _ _ _ _....,j~t-·-,.·• '. • .• •,• -\...;-.·.•· .' •-\-.t.....i}-,j(
--I
CSD
B
I-
===========~
-t
I.-
'., . .'. .'. .,.' . . . ·. . ~i~'-_'
C
--t
B
I--
_ _ _ _ _-i~""""
•.•. •,•.•.••-','.,
••,.,""""""'.'.'-.'
!..,.,......
,....... .
NOTE: CSWRTO Will STAY HIGH THRUOUT THE ENTIRE CS READ OPERATION
A= 10 ns MAX
D=85nsMIN
B = 10 ns MIN
E = 10 ns MIN
C= 10 ns MIN
F = 40 ns MIN
Figure 3. CPU/WCS Interface Timing Control Store Read Operations
The Read instruction is decoded in Control State O. The CPB gates the address on the busses prior to entering Control
State 2 as described in the section on writing into WCS. The CSWRTO is held high throughout the Read instruction. During
CS2, WCS deposits one 32-bit word on Control State Data bus (CSD) 001 :311. The data on the bus must be settled at least
10 nanoseconds before the negative going edge of PCLKO (see parameter C in Figure 3) which latches the data read from
the WCS in the Processor Register Stacks.
WCS Strapping
Address strapping.
The 8/32 WCS responds to the Control Store addresses within the X'800~'9FF' range.
ROUTINE MAINTENANCE
Routine maintenance consists of running the WCS Test Program 06-192.
This information is proprietary and is supplied by INTERDATA for the IOle
4
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
3S-S3SROIA21
November 197 S
MODEL 8/32 MAIN MEMORY SYSTEM
MAINTENANCE SPECIFICATION
1.
INTRODUCTION
This specification applies to the INTERDATA Model 8/32 Main Memory System components listed in Table 1.
TABLE 1. MODEL 8/32 MAIN MEMORY COMPONENTS
BOARD PART NO.
2.
MNEMONIC
FUNCTION
35-534
LMI
LOCAL MEMORY INTERFACE
35-535
MBC
MEMORY BUS CONTROLLER
SCOPE
This specification describes the overall operation of the Model 8/32 Main Memory System consisting of one MBC and two
LMI boards used in conjunction with the 3S-198 32 KB Memory Module or'the 3S-SS2 64 KB Memory Module. The Main
Memory System interconnection to the CPA Bus and the Extended Direct Memory Access (EDMA) port are covered by
this specification. The specification also provides a block diagram description, timing information, troubleshooting and
maintenance, and a mnemonic list for the MBC and LMI.
3.
SYSTEM BLOCK DIAGRAM
The basic organization of the Main Memory System is shown in Figure 1. Access to the memory system is made through
two ports; The CPU port which interfaces with the CPA board, and the EDMA port which interfaces with the Extended
Direct Memory Access Bus.
The Memory Bus Controller (MBC) board controls the two ports into the local memory and provides a third data path
which enables the CPA to directly access remote memory located on the EDMA Bus. The MBC also maintains a cache
memory of eight halfwords which is used to store instructions in a look-ahead fashion, and is equipped with circuits to
resolve ·contention between the CPU port, EDMA port, and look-ahead cache for access to Local Memory. The MBC
maintains the control logic for the EDMA Bus (QUEO, RPCO/TPCO, and SOTO as described in Section 7).
The Local Memory Interface (LMI) board provides all signals necessary to control the Local Memory Modules (LMMs) and
steers halfword data to the appropriate Memory Module bank for halfword operations. In addition, the LMI generates and
checks parity, on systems so equipped.
3.1 Memory System Organization
The Model 8/32 Memory System is organized into a pyramid structure which places four Memory Module banks in parallel
(see Figure 1). Note that each LMI controls two banks of Memory Modules, each 16 bits wide, which are accessed
simultaneously to give a 32 bit wide full word of data on each memory access cycle of an LMI. The MBC is connected via
the 32-bit Local Memory Bus to two LMI boards, each of which controls half of the available memory.
The addressing structure of the memory system is such that the two halves of memory controlled by separate LMI boards
are interleaved; Le., successive full words are controlled by alternate LMIs. Looking at the address format (Figure 2), only
19 of 20 address bits are used by the memory system. Bit 17, the full word bit, determines which of the two LMIs controls
the requested address; Bit 18, the halfword bit, determines which of the two banks controlled by the LMI contains the
requested halfword (used only for halfword operations). These bits are used only within each LMI to select the appropriate
memory bank and Bits 0; 16 are then sent to the memory bank to address the desired location within the selected bank.
Thus, addresses in which Bits 17 and 18 are both zero, are found in the bank with interleaving address 00 (Figure 1), and
similarly for the other three combinations of the two least significant bits.
The two important features of the Main Memory System organization are; 1. Fullword data paths, providing true fullword
access capability; 2. Fullword interleaving, reducing the effective memory cycle time for accesses to subsequent fullword
addresses.
This information is proprietary and is supplied by INTER DATA for the sale
purpose of using and maintaining INTEROATA supplied equipment and shell
not be used for any other purpose unless specifically authorized in writing.
CPA
V 32
h
tcpu PORT
EDMA BUS
~ ____ -.J
EDMA
PORT
16
I
:_
I
l I
t +
f----
/
-
-
1
.--.1-1
'MBC
i
•
I
-!
I
LOOK
AHEAD
CACHE
L ___
I
I
J
LOCAL MEMORY BUS
32
LMI
16
32 KB
MEMORY
MODULE
LMI
16
f----
16
32 KB
MEMORY
MODULE
32 KB
MEMORY
MODULE
f--
16
I--
32 KB
MEMORY
MODULE
' - - v - - - - ' INTERLEAVING
00
-
ADDRESSES
SEE TEXT
~
•
01
~
10
-
INTERLEAVING
ADDRESSES
SEE TEXT
Figure 1. Model 8/32 Main Memory System Block Diagram
This information is proprietary and is supplied by INTEAOATA for the sale
2
purpose of using and maintaining INTEAOATA supplied equipment and shall
not be used tor any other purpose unless specifically authorized in writing.
-
~
11
HALFWORD BIT
SELECTS INDIVIDUAL
/ ' MEMORY BANK
BITS 0:16 ADDRESS
ACTUAL LOCATIONS IN
MEMORY BANK
o
1
2.
III
•
•
•
• 16
17
18 1~
J)I I~
FULLWORD B I T - B Y T E BITSELECTS LMI
NOT USED
Figure 2. Address Format
4.
MEMORY SYSTEM PHYSICAL DESCRIPTION AND INTERCONNECTION
The basic configuration for the Main Memory System consists of one MBC, two LMI boards, and four 35-19832 KB 750
nanosecond cycle time Core Memory Modules with or without parity. These are arranged as shown in Figure 3. Expansion
of memory capacity beyond the basic 128 KB requires that Local Memory Modules in the basic chassis be removed and all
Memory Modules be located in the Memory Expansion chassis with interconnection via back panel cables. Refer to Model
'
8/32 Installation Specification, 01-078A20, for details of memory expansion.
4.1 Memory Bus Controller
The MBC consists of one INTERDATA standard size mother board which occupies upper card file Slot I. The MBC plugs
into back panel Connectors 0 and I for power, ground, and CPU, EDMA and LMB interfaces. A back panel waterfall cable
from Connector I of the MBC slot to Connector I of the lower card file Slot 2 provides the interconnection of the EDMA
Bus interface to the I/O slots.
4.2 Local Memory Interface
Each LMI board is one INTER DATA standard size mother board which occupies upper card file Slots 3 and 6. The LMI
boards should not be interchanged, as each board is strapped differently. The LMI plugs into Connectors 0 and 1 for
power, ground, and LMB and LMM interfaces.
~
UPPER HALF
OF JUMBO
BASIC CHASSIS
~
7
LMM-11
6
LMI
5
LMM-10
4
LMM-01
3
LMI
2
LMM-OO
1
MBC
0
7
6
5
Figure 3. Basic Configuration - Main Memory System
This information is proprietary and is supplied by INTEADATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
3
5.
COMPATIBLE MEMORY MODULES
NOTE
The descriptions in this section are not meant to limit future
memory expansion to the three types of Memory Modules
specifically mentioned. Future development may result in
additional compatible Memory Modules (for example, semiconductor memories) which meet the same interface
specifications and therefore can be accommodated.
The Main Memory System is designed to accommodate three different standard INTERDA TA modules within Local
Memory as follows:
35-198
35-198
35-552
32 KB 750 nanosecond cycle time Module
32 KB 1 microsecond cycle time Module
64 KB 1 microsecond cycle time Module
The standard configuration rules for the system are such that only one type of Memory Module may be used within Local
Memory; i.e., mixing memory types is not permitted except by special configuration. Provisions have been made in the
memory system design for special configurations where up to three pairs of LMIs can be connected to the LMB with each
pair accommodating a different type of standard INTERDATA Memory Module. That is, each pair of LMIs is strapped to
respond only to separate, contiguous blocks of memory address. Figure 4 shows a special configuration.
MBC
LOCAL
MEMORY BUS
256KB OF MEMORY
1 MICROSECOND 64KB MODULES
256KB OF MEMORY
1 MICROSECOND 32KB MODULES
...
512KB OF MEMORY
750 NANOSECOND 32KB MODULES
Figure 4. Example of a Memory System Special Configuration
Using the Maximum Number of LMI Boards.
6.
CPU!MBC INTERFACE
The CPU/MBC interface between the MBC and CPA boards consist of the following lines:
4
MNEMONIC
NAME
DIRECTION
CA120:300
CDOOO:310
CMCOOO:020
Control Address
Control Data
Control Memory Control
CPA-MBC
CPA:'MBC
CPA-MBC
CREQO
CRDYO
Control Request
Control Ready
CPA-MBC
CPA.... MBC
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
Data and Code lines
Address lines (Control Address-CAl 20:300)
These lines transfer the 19-bit address from the CPA to the MBC for all CPU memory accesses.
Data lines (Control Data-CDOOO:310)
The bi-direction Data lines transfer data between CPA and MBC for all CPU memory accesses. Halfword data is
always transferred on CDl60:310.
Control Code lines (Control Memory Control-CMCOOO :020)
The CMC lines carry a code from the CPA to the MBC indicating the type of memory access CPU is requesting. The
CMC code is shown in Table 2.
TABLE 2. CMC CODE
CMC BIT
000
FUNCTION
010
020
0
1
0
READ FULLWORD
0
0
0
INSTRUCTION READ
0
X
1
READ HALFWORD
1
0
0
WRITE FULLWORD
1
1
0
NO ACTION-NOT USED
1
0
1
WRITE HALFWORD
_1
1
1
NO ACTION-NOT USED
Control lines
CREQO
The Control Request line is pulsed low-active by CPA whenever the CPU is requesting a memory
access.
CRDYO
Control Ready is pulsed low-active by the MBC when data is valid during a read cycle, or when a
write cycle no longer requires valid CMC code and data from the CPU.
One other control line, DMFPO, is transmitted from the MBC to the IOU board and is maintained low active whenever a
memory error is detected from Local Memory or remote memory (on the EDMA Bus).
6.1 Types of CPU Memory Operations
The CPU can be serviced with five different types of memory operations as defined by the CMC code. Read fullword and
write full word are 32 bit data operations; read halfword and write halfword are 16 bit data operations. Instruction read
appears at the CPU interface to be a halfword read. However, the MBC responds differently to the instruction read code as
described in Section 11.3.
7.
MBC/EDMA INTERFACE
The interface of the MBC with the Extended Direct Memory Access (EDMA) Bus provides high speed interconnection
between the CPU and up to three remote memory systems, as well as between Local Memory and up to four EDMA
Channel controllers (DMAC). These DMACs can include Extended Selector Channels (ESELCH) and custom EDMA
controllers. In addition, the MBC interface supports the EDMA Bus control circuits.
The EDMA Bus control circuit maintained by the MBC consists of the following control lines:
QUEO
The Queue pulse resolves contention for the bus by freezing the request status at its leading edge.
RPCO/TPCO
Receive Priority Chain (RPC) and Transmit Priority Chain (TPC) are the low-active daisy-chain
priority signal which select the highest priority requesting device captured by QUEO.
SOTO
The negative going leading edge of Start of Transmit (SOT) enables the selected device to start
transmission over'the bus.
This information is proprietary and is supplied by INTERDATA for the IOle
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
5
The remaining lines which comprise the MBC/EDMA interface are:
DMA Data Bus lines
DMX120:150
DMAOOO:170
The DMA Data Bus contains 22 lines that carry multiplexed address and command code, write
data, and read data. Data Bus formats are shown in Figure 5.
Control lines
XREQO
Common Request line pulled low by any memory or DMAC requesting service.
LMRQO
Local Memory Request Queued is pulled low by a DMAC when it is selected by RPCO, if it is
requesting Local Memory.
LOADO
The negative going edge of Load gates the contents of the DMA Data Bus into the appropriate
receiving register of a memory interface on DMAC to memory transfers.
ANSO
The negative going edge of Answer Sync. loads the contents of the EDMA Data Bus into the
appropriate receiving registers on memory to DMAC transfers.
EOTO
End of Transmit is a high speed timing signal generated by the DMAC or memory at the end of
its last data bus pulse. It signals the bus control circuits on the MBC that one device is finished
with the bus and it may issue SOTO to the next user if a request is queued and ready.
MOBZO:M3BZO There is one MxBZO (Memory Busy) line associated with each of the four memory systems
connected to the bus (Local Memory plus three Remote Memories). MxBZO is pulled low by the
active DMAC as soon as it receives the SOTO pulse. It is released by the DMAC at the end of the
address pulse but is held down by the memory until the memory is capable of receiving the next
command.
BHO
The Bus Hold line is pulled low by an immediate response memory interface and is held low until
the answer is returned. This signals the bus control circuit on the MBC that no SOTO signal can
be generated to another device until the immediate response memory is finished with its cycle.
0
N
x
~
c
-x -x.., x
0
0
0
c
c
0
CO)
~
0
~
c
0
III
~
c
0
0
x x
~
~
c
• • •
:il r-.0
• • • ~« «
~
c
c
'I
II
ADDRESS
19 BIT HALFWORD ADDRESS
IR I W I F
I
~
DMA COMMAND CODE
SEE TABLE 3.
WRITE DATA
16 BIT WRITE DATA
PARITY BIT
ANSWER DATA
16 BIT ANSWER DATA
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
X
X
0
0
X
X
ANSWER FROM MEMORY 0
ANSWER FROM MEMORY 1
ANSWER FROM MEMORY 2
ANSWER FROM MEMORY 3
ANSWER CONTAINS PARITY ERROR
MEMORY MALFUNCTION (DATA UNDEFINED)
Figure 5. EDMA Data Bus Formats
7.1 EDMA Bus Control Logic
The EDMA Bus control logic is located on the MBC and is used to resolve contention of devices requesting service on the
EDMA Bus, queue the selected device (QUEO), establish an order of priority of requesting devices (RPCO/TPCO), and issue
a start command (SOTO), indicating that one device has the use of the bus and may begin transmission.
This information is proprietary and is supplied by INTERDATA for the sole
6
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unlesl specifically authorized in writing.
7.2 Types of EDMA Operations
Seven types of data transfer operations can occur over the EDMA Bus. Table 3 lists the operations and their identifying
command codes which are transmitted on the R, W, and F bits of the EDMA Data Bus address format (DMAI50, 160, and
170 respectively) in low active polarity (see Figure 5).
Read halfword and Write halfword are 16-bit data transfers. Read and Set halfword is a remote memory Read operation
which, in addition to reading the data, causes the most significant bit of the data halfword in the remote memory to be set
after the read is accomplished. Read fullword and Write full word are 32-bit data transfers in which the data is sent over the·
EDMA Data Bus in separate 16-bit halfwords.
.
Burst read and Burst write are block transfer operations in which a single EDMA request initiates a block of continuous
memory accesses to sequential fullword addresses.
TABLE 3. EDMA COMMAND CODE
8.
R
W
F
FUNCTION
1
0
0
READ HALFWORD
0
1
0
WRITE HALFWORD
1
1
0
READ AND SET HALFWORD
1
0
1
READ FULLWORD
0
1
1
WRITE FULLWORD
1
1
1
READ BURST
0
0
1
WRITE BURST
MBC/LMI INTERFACE
The MBC/LMI interface consists of the following lines:
MNEMONJC
NAME
DIRECTION
LMBOOO:310
LMRSO
LMDSO
LMRDYO
LMBSYAO}
LMBSYBO
LMBSYCO
Local
Local
Local
Local
MBC=LMI
MBC-LMI
MBC-LMI
MBC-LMI
Memory Bus
Memory Request Service
Memory Data Strobe
Memory Ready
Local Memory Busy A, B, and C
LMI~LMI
Data Bus LMBOOO:310
These bidirectionallines are time-multiplexed to transfer address and control data to the LMI boards at the start of
'a memory cycle and later to transfer data between the MBC and LMI boards, as shown in Figure 6, Halfword data
is always transferred on LMBI60:310.
~lJ
ADDRESS TIME
II I 11 r I 1II II I I 11 t
\1 I
I IJ
19 BIT ADDRESS
~
5 BIT CONTROL CODE'
-SEE TAB LE 4.
FULLWORD OPERATION
32 BIT DATA FIELD
DATA TIME
HALFWORD OPERATION
NOT USED
II
16BIT DATA FIELD
Figure 6. Local Memory Bus Formats
This information is proprietary and i, supplied by INTER DATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
7
Control Lines
LMRSO
Local Memory Request is made low-active when the MBC is requesting a memory cycle.
LMDSO
The leading edge of Local Memory Data Strobe clocks write data into the LMI Memory Data
Register during Write operations.
LMRDYO
The Local Memory Ready pulse is maintained low active when an LMI begins the requested
memory cycle and when data for a Read operation is valid on the LMB.
LMBSYBO}
LMBSYCO
Local Memory Busy A, B, and C communicate between LMI boards to synchronize their access
cycles for an instruction Read operation.
8.1 Types of Memory Operations
Five types of data transfer operations can occur over the Local Memory Bus. Table 4 lists the operations and their
identifying control codes. The control code is transmitted over LMB27 :31 during address time (see Figure 6) with
high-active polarity.
TABLE 4. LOCAL MEMORY CONTROL CODE
LMB27
LMB28
LMB29
LMB30
LMB3l
COOl
Call
C02l
EXl
SXl
a
x
1
X
a
WRITE FULLWORD
a
READ FULLWORD (FROM CPA or DMA)
READ FULLWORD (FROM DMA in BURST)
FUNCTION
1
a
1
x
1
1
1
1
a
a
1
a
WRITE HALFWORD
X
a
x
x
a
1
a
READ HALFWORD
1
1
1
a
a
INSTRUCTION READ (FROM CPA)
X
x
x
1
INSTRUCTION READ (FROM LOOK·AHEAD CACHE)
X
Write and Read full word are 32-bit data transfer operations. Note that two codes exist for read fullword-the LMI
responds identically to either code. Write and Read halfword are 16-bit data transfers over LMB 16 :31. An Instruction Read
request causes both LMIs to respond with a full word Read operation. This results in a double full word Read operation,
aligned on double full word boundaries. The first 32-bits transmitted to the MBC contain the actual instruction halfword
requested. 125 nanoseconds later, the second 32-bits of the aligned double fullword is transmitted by the other LMI. Both
full words are stored in the look-ahead cache.
Note that there are two Instruction Read· codes, depending on whether the CPU or the look-ahead cache initiated the
request. The LMI boards respond identically to either code.
9.
LMI/LMM INTERFACE
The LMI interface with the Local Memory Modules (LMMs) is defined by the following lines:
--,
8
~
---------_ ..-
MNEMONIC
NAME
DIRECTION
MSOOO:160
Memory Sense Bus
LMI~LMM
MDOOO:160
Memory Data Bus
LMI~LMM
MAX060, MAX070,
MAOO:14(O)
Memory Address
LMI-LMM
ERO
Early Read
LMI-LMM
INHO
Inhibit
LMI-LMM
EWRTO
Even Halfword Write
LMI-LMM
OWRTO
Odd Halfword Write
LMI-LMM
This information is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
Data lines MSOOO:160 and MDOOO:16*
These two bidirectional data busses carry 16 bits + parity of read data and write data between an LMI and its two
separate banks of memory. The MS Bus and associated memory bank handle the most significant (even) halfword
in an aligned full word, while the MD Bus and memory bank handle the least significant (odd) halfword (see Section
3). The two busses are then linked together within the LMI for a fullword of data (on fullword operations).
Address Lines MAX060, MAX070, MAOO:14, (0)
These lines carry the 17-bit address from the LMI to both banks of memory. Contrary to their mnemonic
designation, the LMI outputs high-active address information.
Control Lines
ERO
Early Read is a Memory Module control signal which initiates the readout phase of a core
memory cycle.
INHO
Inhibit is a Memory Module control signal which initiates the restore/write phase of a core
memory cycle.
EWRTO
Even Write is a Memory Module control signal which is maintained low-active when it is desired
to write into the even-halfword bank of memory.
OWRTO
Odd Write is a Memory Module control signal which is maintained low active when it is desired to
write into the odd-halfword bank of memory.
The Memory Module cycle is basically the same for any request type initiated by the MBC, the only difference is that one
or both of EWRTO/OWRTO are maintained low active if a Write operation is performed. It is important to remember that
an LMI cycles two Memory Modules (even and odd halfword) for every access cycle, whether the request is for a halfword
or full word operation.
10. MBC BLOCK DIAGRAM DESCRIPTION (See Figure 7.)
1.
The 19 CAXXO lines from the CPA are the memory address lines. They are stored in 19 tracking latches,
the CA ADDR Register.
2.
The STK ADDR Register contains the 17-bit address of the four halfwords in the stack with the lowest
double-fullword address. The STK A valid flip-flop indicates when this data is valid.
3.
STK B ~ is a 16-bit adder that effectively adds 1 to the stack address register to provide the address of the
four halfwords of data in the stack with a higher double-full word address. The STK B valid flip-flop
indicates when this data is valid.
4.
The comparators, CEQL and CEQU compare the 17 most significant bits of the CA ADDR Register to the
STK A and STK B data to determine if the address requested is contained in the stack.
5.
The Control Memory Control (CMC) analysis block decodes the Instruction Read code, data read and write
codes, and the null state code of the CMC bits.
6.
The Memory Contention (MC) circuit resolves contention for the memory between the Processor, the
EDMA Bus, and the look-ahead stack. In the case of more than one request to the memory, the Memory
Contention (MC) circuit also sets priority. The EDMA Bus has highest priority, the Processor second, and
the look-ahead stack lowest. This circuit enables the Local Memory Request Service signal (LMRS), holds
the Local Memory Bus Busy state, and is reset by the Cycle Complete (CYCOM) signal.
7.
The enabled LMRS logic generates LMRS with the appropriate delays and conditions.
8.
The Cycle Complete (CYCOM) logic generation indicates that the present access to memory using the Local
Memory Bus is completed.
9.
Counter F (CTR F) keeps track of the number of Local Memory Readys (LMRDY) required from the LMI
to steer the data and input to the CYCOM logic.
10.
The Local Memory Bus (LMB) is a 32-bit bidirectional bus that sends and receives the LMI data to and
from the LMIs.
* These bidirectional data busses should not be confused with the unidirectional MS and MD lines on the Memory
Modules. The MS and MD lines of the Memory Module are wired together and the combination is then connected to either
the LMI MS Bus or LMI MD Bus, as appropriate.
This information is proprietary and is supplied by INTEADATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
9
II.
When the LMRS signal is sent to the LMls, the LMB is used for address and control information. The LMB
is driven by tri-state multiplexors at each end and received by STTL gates. The address information is low
active on the bus while the control bits are high active. The first Local Memory Ready signal from the LMIs
indicate that the address has been accepted and the memory cycle has started. The LMB is then used for the
transfer of data. The data is high active on the LMB.
The LMB tri-state multiplexor puts the address on the LMB either from the Processor (CAF), the EDMA
(DAD), or from the stack request (STB). For Writ,! operations to memory this multiplexor is also enabled
and places either the Processor data (CD), or the EDMA data (DMF) on the LMB.
10
12.
The Instruction Stack contains eight halfwords. It has separate Read and Write select lines. It is loaded four
halfwords at a time, each time the Processor makes an Instruction Read memory access or each time the
stack makes a look-ahead access. The four halfwords come in two 32 bit passes on the LMB. The Write
select logic determines the stack address to be loaded and the CTR F logic creates the Load strobes. The
Read select lines come directly from the three least significant bits of the address from the Processor, CAF.
A tri-~tate multiplexor, CD B, places the data from the stack onto the CD lines to the Processor during an
Instruction Read from an address in local memory.
13.
Tri-state multiplexor CD A places data onto the CD Bus to the Processor during a data read from Local
Memory or during a read from memory on the EDMA Bus.
14.
The Address analysis logic looks at the address requested by the Processor on the CA lines and compares it
to four sets of straps to determine if the address is contained in Local Memory, or in one of the three
memories that can be placed on the EDMA Bus, or it is beyond the range of memory fitted in the particular
machine. The outputs MO, MI, M2, M3, and GTUU (Greater Than Unused) indicate in what region the
requested address lies. There are four straps in each set so the one megabyte of memory can be divided up
with a resolution of 64 K bytes.
IS.
Tri-state buffer A places the CAF information on the DMT lines (to DMA transmitters) for Processor
requests to memory on the EDMA Bus. Tri-state multiplexor, DMT A, places the data onto the DMT lines
when the request is a write to external memory.
16.
The DMA transceivers translate the TTL DMT levels into the EDMA Bus levels.
17.
The LM data register stores the LM data for answers to EDMA requests from Local Memory.
18.
The tri-state multiplexor, DMT B, places the correct half of the LM register onto the DMT lines for these
reads.
19.
The DXR and DMR lines are signals from the EDMA Receivers.
20.
The DMA address register counter stores (and increments when necessary), the 19-bits of address information from the EDMA Bus during accesses to Local Memory.
21.
The DMA CTRL register stores the three control bits.
22.
The DMA data register is a 32-bit register that stores the data from the DMA Bus that is sent to Local
Memory on a write, or stores the read data sent back to the Processor from external memory.
23.
The DCOMP A and the DCOMP B circuits are comparators that signal when the EDMA Bus is Writing into
memory over an address that is valid in the instruction look-ahead stack.
24.
The CPA SEL logic requests the EDMA Bus for transfers to external memory and gets the CPA selected as
the transmitting device on the EDMA.
25.
CTR B generates the Load and End of Transmit (EOT) signals for the EDMA when CPA is communicating
with external memory. It also helps create the signals for data steering and enabling.
26.
CTR D receives Load signals from the EDMA Bus and creates the load register signals. It counts the loads
and initiates action when required.
27.
The Bus Control logic with signals from CTR A, handles the requests for the EDMA Bus and generates the
Queue (QUE), Transmit Priority Chain (TPC), and Start of Transmit (SOT) for the bus.
28.
The CRDY logic generates CRDY back to CPA at the end of the CPA access.
This information is proprietary and is supplied by INTEROATA for the lole
purpose of usin"g and maintaintng INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
19
CAXXO
LMB
CAFI
CA
ADDR
REGISTE
DADI
LMB
TRI-5T
MUX
DMFO
COO
STBI
I
C M C X X 0 4 CMC
NALYSIS
CREQ
)>----
MEMORY
CONTEN-r----~::~~~~=t=====-~~~-iCONTROL
LOGIC
CTRA
figure 7. MBC Bloek Diagram
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
11
II. MEMORY BUS CONTROLLER (MBC) FUNCTIONAL DESCRIPTION
11.1 CPA to Local Memory Write Halfword of Fullword
11.1.1 Address Transfer Cycle. Refer to timing diagram Figure 8. The address bits from CPA come through
tracking latches (Sheet 6) which are tracking because the CREQF (6F6) is still reset. The address is analyzed by the
comparators (Sheet 9) and found to lie in the range of the Local Memory (Memory 0). The CMC bits (11 H6) are also
checked and it is found that this access is not an Instruction Read (IR).
The CREQ pulse is received from the CPA and stored in the CREQF (6F6). A delay line (14A7) is also started to give
delayed signals equivalent to CREQF. The setting of CREQF freezes the address in the tracking latch and signals the start
of the MBC response.
CTENDO (13E8) is the input to the Memory Contention circuit and it is created from MOl, IRO, CRQDOOI (CRQDOOI is
CREQ delayed zero time), and no resetting signal. The CTENDO signal is immediately sent when CREQ is received, the
access is not an Instruction Read (lRO), and the address is in the range of Local Memory (MO 1).
The LMB multiplexors (Sheet 3) enable and select the CAFxxl and CAFBxxl signals with a low active signal on DATTMI
(13M9) and a high-ilctive signal of EFBO. DATTMI is low active during address time except when the look-ahead stack is
requesting to be filled from memory (SMZO being low).
The address time ends when the Local Memory Bus Busy flip-flop is set. This occurs when the first Local Memory Ready is
received from the LMIs. The command code is also sent on the LMB at the same time as the address. Bit 27 on the LMB
(LMB270) is low at this time for write commands.
The AND-OR-Invert gate (13N7) creates Local Memory Request Service (LMRS). The CFI and EFO inputs indicate that
the Processor (C) and not the EDMA (E) is in control of the memory. LMRS is turned off by LMBBY being set. The D35 is
a delayed enable signal from the contention delay line and is discussed in the Memory Contention circuit.
Note in the timing diagram that the gap between CREQ to LM and the LMRSO from C could be caused by another cycle
presently in progress or a request from the EDMA Bus which has a higher priority. The gap between LMRSO and LMRDYO
is caused by the LMI being addressed while still being busy from a previous access.
CROOO
CRDVO
~M~OO~
__~~______~____~S·~~~__~S~S____________________~__________________
~
---------------iII'SEE NOTE
CREOFO
.
L-----~S%
-C-R-E-O-T-O-L-M--CO-.N-T-E-N-T-I-O-N------~I
CTENDO
LMRSO FROM C
§
Ls-
I
I
SS~------------------------~
S&~________________________~r--------------------:-1
I-.
ss
-L-M-R-D-V-O--------------s
s~ 50 ns
I
LMBBSVO
.
st05~
s~s--~ss~~I~I
=::i
__________________
--------------------~S);;----~S.~S--~----------,
LMDSO
SOns TVP --+40 ns
I-
-=I~-------------------
NOTE 1: This.Delay depends on whether or not th~ Memory is busy with an EDMA or Stack Request.
NOTE 2: This Delay depends on whether or not the requested LMI is busy.
Figure 8. CPA -
LM Write Timing Diagram
This information is proprietary and
12
i,
~
supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unles. specifically authorized in writing.
11.1. 2 Data Transfer Cycle. During the LMRS signal, a delay line (II L9) is being loaded with a low active signal
to generate the data strobes on the LMB and the Local Memory Data Strobe (LMDS).
The conditions necessary to load this delay line with a 0 are: 1. Not a stack request SMXO, 2. Local Memory Request
Service (LMRSl), and 3. Data write command code as indicated by a 1 on LMB271. When LMRS is disabled (caused by
the LMRDY signal from the LMI which sets the LMBBY flip-flop) the delay line (II L9) starts to reload with a 1 level.
Meanwhile, DATTMI (l3L9) has gone high active because of LMBBY, causing WDTMO (Write Data Time) to go low
(11 N7). Local Memory Data Strobe (LMDS) is also generated (11 NS) by this delay line and occurs during WDTM.
The LMB multiplexors (Sheet 3) are switched at data time because the address enabling signal, DATTMl, goes high and the
Write Data Time (WDTMO) signal goes low, enabling the CD lines onto the LMB and disabling the CAF lines. LMDS
indicates the end of the cycle and Cycle Complete (CYCOM). CYCOM is generated in parallel on the AND-OR-Invert gate
(II D8) by DA 701 and DA400. Cycle Complete (CYCOM) resets the Memory Contention circuit. The ready signal to the
Processor (CRDY) is generated by the AND-OR-Invert gate (14N8). LMDS causes CRDY through the gate (14K8) which is
the OR of LMDS or Instruction Read ready from Local Memory (lRWRT - Instruction Read or Write). The CREQ
flip-flop is reset in parallel by the same signal into the RCREQF circuit (l4RS). There is no distinction made in the MBC
between halfword and full word accesses to Local Memory.
11.2 CPA to Local Memory Read Halfword or Fullword
11.2.1 Address Transfer Cycle. Refer to timing diagram Figure 9. This cycle is the same as for the data writes to
Local Memory except that Bit 27 on the LMB (LMB271) is high at this time indicating a read command.
I-- 20 ns MIN--j
. LMRSO FROM C
325
'-LMRDYO
, LMBBSYO
CTRFA
: CTRFB
CTRFC
CYCOMO
NOTE 1:
This delay is a function of whether or not the memory is busy with an
EDMA or Stack-request.-
NOTE 2:
This delay is a function of whether or not Local Memory is busy .
. Figure 9. CPA-LM Read Timing Diagram
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing,
13
11.2.2 Data Transfer Cycle. The edge of the first LMRDY signal from the LMI indicates that the address has
been accepted and the data cycle follows. At this time the LMB multiplexors in the MBC are turned off waiting for the
LMI to send back the data. This is accomplished by DATTMI (l3M9) going to the I state when LMBBY (l3G9) is set.
Counter F, Stage A (CTF A) (lIE4) is set on the trailing edge of LMRDY. The LMI sends another LMRDY when it has the
data settled on the lines so Stage A of Counter F is used to differentiate between the first and the second LMRDY.
When the LMI sends data, it is placed on the CD lines through tri-state multiplexors (Sheet 4), CDA. At this time the Read
Data (RDDATO) signal is low (II H5). This is generated by the AND of CMCOO 1 (II F5) and not an Instruction Read from
Local Memory (STCDO) (lIC5). (STCDO - Stack to CD enable signal). RDDATO and STCDO enables the multiplexors,
and MOO (Memory Zero or Local Memory) or MBOO (Buffered Memory Zero) select the LMB lines.
Cycle Complete (CYCOMO) is generated by the second LMRDY when it is ANDed with CTF A and not an Instruction
Read and not a Stack Access (SMXO) to memory (AND-OR-Invert gate) (II D8). CRDY is generated in parallel by CTF A I
(14N8), LMRDY (delayed by 5 nanoseconds extra), and the output of a flip-flop which indicates that the access was not
an Instruction Read. The reset of the CREQF flip-flop is generated by CRDY (14R6).
11.3 CPA Instruction Read from Address in Local Memory
11.3.1 Instruction Valid in the Stack. The Control Address flip-flops (CAF) tracking latches are constantly
being compared against the ST A and STB signals. STA is the output of the register that stores the present base address of
the data in the stack (Sheet 7). STB is the output of the adder (Sheet 7) that adds I to STA, giving the address of the data
in the upper half of the stack. Note that there is no STB28 because this is the complement of STA28. This is the reason
there are 17-bits of STA but only 16-bits of the adder are needed to add I to it.
The comparisons are done on Sheet 8. Bit 17 is handled in both cases by Exclusive OR gates (8H9). Even if the address
compares in one of these two comparator circuits, other signals are needed to obtain an equal output. These signals are
STKA, which indicates that the lower half of the stack is valid, STKB, which indicates that the upper half of the stack is
valid; and SD200, which is a signal that permits the data in the stack to be loaded and settled from a stack access.
If either of these comparisons show up as equal by the time the CREQ signal reaches the 20 nanosecond tap on the CREQ
delay line (l4A7), then it is remembered in a cross coupled EQI flip-flop (l4D7). EQI, MOl, IRI, and CO (Instruction
Read, and Processor not accessing memory) combine in an AND gate to become EQIRCO (14G6). This combines with
CRQD30 (CREQ delayed 30 nanoseconds) to form the CRDY back to the Processor (l4M8). The equivalent of the Stack
Ready (STKRDY) is generated two other places, once as the true signal (STKRDYl) (l4G8) and once as the not signal at
(STKRDYO) (14G7). These are used to load the STA register with the present base address of data in the stack (1417) and
to reset STKB (14 L6) (indicator of the validity of the upper half of the stack) if the access is to the upper half of the stack,
and generate a request to memory at the same time to refill the stack with a Set Stack Request (SSREQA) (l4M6).
The data is delivered to the CD lines during this process from the stack (Sheet 5) through CD Multiplexor B, (Sheet 4).
These multiplexors are enabled by a STCDO signal (II C5). STCDO is low whenever the Processor is doing an Instruction
Read (lR) from Local Memory (MOl).
The correct word in the stack is addressed by the three least significant bits of the address.
.
11.3.2 Address Requested not in Stack or Stack not Valid. Refer to timing diagram Figure 10. If the comparators do not indicate an equal in either half of the stack and the address is in Local Memory (MO) then a request to Local
Memory is made. This is accomplished with CTENDO (l3D8) created from not CEQL, not CEQU, MO, and not any other
ready or complete presently being generate'd and the stack not being filled (SDSOO-Stack Delayed 50 nanoseconds).
The request and address transfer cycle to Local Memory is the same as for data reads or writes. The data cycle requires
transferring two 32-bit words as follows. The second LMRDY from the LMls indicates that the data full word containing
the requested halfword is on the LMB. This is enabled into the stack with the signal LDSTKO (II Cl). The delay line
(lIB2) creates the proper timing of this signal from the second LMRDY. CRDY (14R8) is generated at this time by the
AND of CTFBI and CTFCO. Counter F, Stage B is set during the second LMRDY and Counter F, Stage C is set at the
trailing edge of the second LMRDY. Reset CREQF is generated in parallel by IRWRTO (Instruction Read or Data Write)
(14R6). Cycle Complete (CYCOM) is generated by· the third LMRDY from the LMls by the AND of Counter F Stage C
(CTFC) and LMRDY at the AND-OR-Invert gate (11 C8).
When the Processor has to go to Local Memory for an instruction, the ST A register (Sheet 7) is loaded with the new base
Address (LDSTAl) (1417). The two flip-flops that indicate the valid state of the stack, STKA (14J4) and STKB (14L6), are
both reset by Cl LMRSO (14 G5). There are three other signals that can reset these flip-flops through the clear input. These
signals are System Gear (SCLR), writing into an address that is valid in the stack with a Write command from the EDMA
Bus (DEQ), and writing into an address that is valid in the stack from the Processor (from CMCOOO, and CI AND LMRS).
The STKA flip-flop is set again with the IRWRT signal (14H5) when ANDed with Cl (the Processor in charge of the Local
Memory) and IRI (a decode of the CMC bits that indicate an Instruction Read) (II H6). CI LMRSO also sets the Stack
Request flip-flop (13B5) to Local Memory to fill the upper half of the stack with another memory access.
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
14
not be used for any other purpose unless specifically authorized in writing.
Approximate
time in nanoseconds
o
1~
200
300
400
500
600
REQUEST TO FILL 2nd
HALF OF STACK.
LMRSO
.LMRDYO
.LDSTKO
.CRDYO
CYCOMO
LDSTKAl
,$TKAl
.s:rKBl
.STACK
Pr~~Edjp
, NOTE 1:
If Stack was valid but requested
instruction is not in Stack, Cl'LMRSO
will invalidate stack.
Figure 10. Instruction Read when Stack is Invalid or the Requested
Instruction is not Currently in Stack
The data is written through the stack on an Instruction Read by controlling the Write select lines to the stack. These signals
are STWBI (14Cl) and STWAI (14E2). The Sl and SMXO signals to this logic are from the Memory Contention circuit
indicating when the stack is accessing memory. At this time however, since the Processor (C for CPA) is accessing memory,
the stack is not. This leaves Sl low and SMXO high. This gates the state of STA280 through to STWBI and the state of
CAF290 clocked into the flip-flop on the first LMRS.
.
Stage B of Counter F first enables the true side of the flip flop and then the complement side through to STWAI.
Meanwhile STWBI is directly the inverse of STA280 (14B2) and is actually the equivalent of Bit-28 of the control address
from CPA. Recall that STA is the register that contains the base address of the data in the stack and it was just loaded with
the present address being requested by CPA (LDSTA1) (14J7) so it reflects the present state of CAF28 for this Instruction
Read.
For example, if CAF290 is high indicating a request to memory with an even fullword address, then the first data back
from the memory is from the even fullword LMI. Stage B of Counter F (CTF B) is still low when this data is indicated valid
by the second I:-MRDY, and STwAI is low for the first data fullword and high for the second data full word from memory.
11.4 Stack Control
- Stack request to memory
- Stack filled from memory
- Stack invalid-valid states
There are two ways that the stack may start a memory access. Since an Instruction Read from CPA fills the bottom half of
an empty or invalid stack, a stack request is required to fill the upper half. The Cl LMRSO signal (l4G5) is caused by a CPA
request. It is generated when the Processor is making an Instruction Read request to Local Memory. The other signal that
sets the Stack Request flip-flop (13C5) is SSREQAO (l4N6). This occurs whenever the CPA initiates an Instruction Read
to an address in the upper half of the stack. STKB flip-flop is also reset at this time to indicate that this half of the stack is
temporarily not valid. The leading edge of Stack Ready (STKRDYl) resets the STKB flip-flop if the address comparison
was in the upper half of the stack as indicated by C address Equal to Upper half of stack (CEQU). Note that the lower and
upper halves of the stack are defined by the address stored in STA register and not by the physical address in the stack.
That is, at one instant of time the bottom half of the stack may be Addresses 0:3 and at another time the bottom half of
the stack may be Addresses 4:7. (The data is not moved from one location in the stack to another. Only the STA Address
register is reloaded.) The STKA flip-flop refers to validity of the data in the stack that is from the memory loCation
indicated by the STA register, and the STKB flip-flop refers to validity of the data in the stack that is from a memory
location indicated by the STB adders.
.
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTEADATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
15
The address sent to the memory during the request from the stack is from the STB adders. This is put on the LMB
multiplexors (Sheet 3) by a Stack Busy signal (SBSYO) 14CI). Note that LMB310 is high indicating a Stack request to
memory. SBSYO is low when the stack is accessing memory (SI) until the Local Memory Bus Busy flip-flop is set
(LMBBYO) (indicating that the memory has accepted the address and the data transfer cycle is about to begin.
During the data cycle the LMIs pass back two 32-bit words of data the same as the Instruction Read to memory from the
CPA. The Load Stack signal (LDSTKO) (II CI) is generated the same as for the Instruction Reads from CPA since the
SXIR signal is the OR of Instruction Read from the CPA and Stack in control of the memory (II D6). Cycle Complete
(CYCOM) (II F8) is from the third Local Memory Ready (LMRDY) as indicated by the state of Counter F Stage C (CTF
C) the same as for Instruction Reads from CPA to memory.
The Write select lines to the stack to select the addresses that the data goes to are STWB and STWA (14A I) (the same as
described in CPA Instruction Reads to memory). The fact that this memory access is from the stack looking ahead to fill
the upper half, conditions these select lines. STWB I is the com plement of ST A281 since the stack fills the upper half from
the opposite double fullword address as the lower half. STWAI is always low for the first 32-bit data word in a stack access
because the even address fullword is always sent back first in a Stack request (recall in a CPA Instruction Read, the first
fullword sent back is the one that contains the halfword that was requested and could be the even or the odd full word).
This is done by SMXO (the signal that enables the Stack address onto the LMB through the LMB multiplexors) presetting
the flip-flop (l4B2).
The signal SD500 from the delay line (l3K6) is used to permit the data to settle in the stack before permitting CPA to use
it.
11.5 EDMA Bus Control Circuit (See Figure II.)
Approximate time in nanoseconds
o
I
XREO,
CXREO
35
I
105
I
245
I
175
I
385
315
455
525
I
I
~.--------------------------------------~
CTAA
CTAB:
CTAC
___________________r--
CTAD
CLK1A
OUEO
I
TPCO
, SOTO
COUNT
ON COUNTER A
-I
I
70ns
1
rI
2
3
4
5
COUNTER
MAYBE
, STOPPED
IN COUNT 4
Figure 11. EDMA Bus Control
16
This information is 'PI"oprietary and is supplied by I NTER OAT A for the sale
purpose of using and maintainil"l§ ,INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing,
6
7
The EDMA Bus control circuit generates the QUE, Transmit Priority Chain (TPC), and Start of Transmit (SOT) signals to
the bus. These signals are created from a 4-bit Johnson Counter which is labeled CTA (lOHI). The counter can be stopped
at either of two times by signals at the clock oscillator (lOCI). At Count zero, Stage A and Stage D of the counter (CTAA
and CTAD) are both high. At this time the counter is stopped unless there is a request from the EDMA Bus (XREQ) or a
request for the bus from the Processor (CXREQ). This condition is the output of the four input NAND gate (lOBI). When
one of these requests arrives, the counter clock starts and immediately sends out a QUEO (lON3). At Count two, the
Transmit Priority Chain (TPC) (which is actually the beginning of the priority chain) is sent out (lOR7). At Count 4, the
counter can again be stopped (CTAAI and CTADl both high) by the STHOLDl signal (lOK3). STHOLDl is generated by
the ORing of five signals. These signals are: I. DMAACTO, which indicates that the DMA is presently transmitting data and
another Start of Transmit (SOT) should not be sent at this time, 2. The Local Memory Request Received signal (LMRQRI)
(which indicates that the device queued up is requesting Local Memory) is ANDed with EFO, which is the EDMA selected
state of the Memory Contention circuit. This means that if the queued device is requesting Local Memory, Start of
Transmit (SOT) is not sent until the EDMA has control of Local Memory in the Memory Contention circuit, 3. BHO which
is the Bus Hold signal indicating that a memory is still using the bus and will momentarily send back answers, 4. A delayed
Bus Hold signal to inhibit false indications of Bus Hold being removed, or 5. EDMA Request and Burst Read (ERQBRDO)
which indicates that when a Burst Read operation is occurring, another SOT should not be transmitted until the Burst
Read access is completed.
. Count 5 (CTA Stage B high and CTA Stage A low) (lOL4) generates Start of Transmit (SOTO). SOTO sets the DMAACT
flip-flop indicating that the DMA is actively transmitting data at this time. End of Transmit or System Gear resets this
flip-flop as the ENDO signal (lOM9).
11.6 CPA Select on EDMA Bus (See Figure 12.)
. CREQ()
,QUEO
,XX1
.SOTR1
rSEU
70
105
175
i.
315 I
.
Approximate time in nanoseconds
Figure 12. CPA Request to EDMA Bus
When CPA makes a request to the MBC for an address that is not in Local Memory, the address analysis logic indicates if
the address is in Memory I, 2, 3, or not in the system. This is done by the comparators (Sheet 9). The strapping on the
comparators draws the division lines through the memory so that when an address (four most significant bits) is greater
than one set of straps, but less or equal to the next set of straps, then the address is in that block of memory. When the
address is found to be within the range of Memory I, 2, or 3, the MBC goes out to the EDMA Bus for the access. The
DREQ flip-flop (9L3) is set by a pulse when the address is not in the Local Memory addresses (MOO) and less than the
unequipped memory addresses (LTUUO). When the memory requested is no longer busy as determined by the AND-ORInvert gate (9J5) then the CXREQ signal is sent to request the EDMA Bus and the SQUEFI signal (9M5) sent to the select
logic (Sheet 10).
The first Select Logic flip flop (lOH6) is set on the leading edge of QUEO when the SQUEFI signal is present. This
information is transmitted to the second flip flop on the trailing-edge of QUEO. The leading edge of RPCRI clocks the
XXI flip-flop (lOK6) and the leading edge of Start of Transmit clocks this into the second Select Logic flip-flop (lON6)
(SELl).
When the SEL flip-flop (lON6) is set, the XXI flip-flop is reset, and the DREQ flip-flop (9L3) is also reset. This ends the
select sequence.
This information is proprietary and is luppied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
17
SOTO
LJ
I
~LM=S=E~L1______________~lrl---------------------'IL-
I
,LOADO
IU
I
U
I
CTDRl
,;LDMSHO
.LDLSHO .
LJ
LJ
fOro
JU)AORO -
____________________
I
U
LJ
LJ
WRTBUPl
,LMRSO
LMRDY.O
_CYCOMO
NOTE: THIS DELAY DEPENDS ON WHETHER-OR NOTMEMORY
IS BUSY WITH A CPA OR STACK REQUEST.
Figure 13. EDMA Bus Write to Local Memory
When LMRQRl is high with Start of Transmission, the Local Memory Selected flip-flop is set (LMSEL) (12D6). The Start
of Transmission (SOTO) initializes Counter D Stage A (CTD A), resets the Write Buffer Full flip-flop, and other flip-flops
used.
Counter D keeps track of the loads being received so that the fIrst load from the EDMA Bus loads the DMA Address
Counter Register (Sheet I). This register is loaded with a low on Address Finished (ADRFNI) (12H8) and a clock
(CDMADl) (11 G9). The low on ADRFNI is from Stage A of Counter D (CTD A) not being set yet. The clock signal is
from the Load Address input (LDADRO) (11G9). This is generated (12C7) by the first load from the EDMA Bus after
SOTO. At the trailing edge of this fIrst load, CTD A is set and the Address cycle is finished. On the second load, a Load
Most SignifIcant Half (LDMSH) of the DMF Data Register (Sheet I) is generated. This is the LDMSHO signal (12H8) that is
ORed (II M4) to actually load the register. Note that there is a load at the same time as the address load but it is of no
signifIcance because it is written over by the second one. The second load also toggles the Stage B flip-flop of Counter D
(CTD B) (l2F8). This enables the third load to set the Write Buffer Full flip-flop (WRTBUF) (12K8) and load the Least
SignifIcant Half (LDLSH) of the DMF Data Register with the LDLSHO signal.
.EHOLDO (11M6) goes high now and the memory access is started. The EDMA Address register (DADxx) is put on the
LMB by enabling the multiplexors (Sheet 3) with the DATTMI signal as described in the CPA write to Local MemQry, and
selecting the DADxx inputs with the EFBO signal from the Memory Contention circuit indicating that the EDMA is in
control of the Local Memory Bus.
t
The remainder of the operation is the same as for CPA writes to Local Memory except that the data multiplexors to the
LMB are selecting the DMF data inputs with the EFBO signal. The Local Memory Data Strobe is generated in the same
way.
This information is proprietary and is supplied by INTEADATA for the IOle
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unlns specifically authorized in writing.
19
The Local Memory Select flip-flop is reset with the End of Transmit signal but the operation is extended to the end of the
cycle on the Local Memory Bus by the cross coupled flip-flop (13B2). This flip flop is set by LMSELO, enabled to request
memory with the DMA control bit that indicated a write, DMMCOOO, and reset with Cycle Complete (CYCOM). This
flip-flop is another condition that delays Start of Transmit by holding the Bus Control counter with ERQWRTO (10H3).
For halfword writes to Local Memory, Stage B of Counter D is held high by the DMMC021 signal being low. This is the
control bit from the EDMA Bus, after it is stored in the register (1 K8), that indicates a halfword operation when it is low.
This control bit reiister was loaded at the same time as the address with the leading edge of LDDMC signal (l2D7).
11.10 EDMA Bus Read from Local Memory (See Figure 14.)
When the LMRQ signal is sent on the EDMA Bus, the bus control circuit does not send SOTO until the EDMA has control
of the Local Memory Bus in the same manner as for an EDMA write"to Local Memory.
SOTO and LMRQ set the Local Memory Select flip-flop (l2DS). The Address transfer cycle is the same as for the Write
operation. The SOTO signal initializes several circuits for the Read operation. These are the Read Buffer FuJI (RDBUFL)
flip-flop (12C2) and the Counter E Stages A and B (12H3 and 12K4).
The gate (11 KS) removes EHOLDO when the ADRFNI signal goes high. This occurs after the address is transferred to the
DAD Registers. At this time the Read Buffer is also empty, reset by SOTO, and not in a Burst Read operation, and
DMMCOOI is high because it is a Read operation.
,
Approximate time
in na"noseconds
0.
",
ISOTO. _
L.J
'LMSEb
I
'..l.OAOo.
~OTO F.ROM DEV.
60
,
120.
240.
360
480.
600
840.
L
u
u
FROM
LMROYO"
ROBUFL1
:CTEA1'
CTEB1 "
rC'tEtn'
ANSO" "
.'J1.MSEL4
'¥lAlFWORD" "
Figure 14. EDMA Bus Read from Load Memory
20
720.
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
un
The memory operation of Local Memory Request Service (LMRS) and two Local Memory Readys (LMRDYs) continue as
usual. The Cycle Complete (CYCOM) signal is generated as with any data read command. CYCOMO (12B2) is ANDed with
LMSEL to set the Read Buffer Full (RDBUFL). The other two inputs to the gate (12D2) are DMMCOOI and RDYDATI.
These are the command bits, indicating a Read operation, and a Ready for Data signal respectively, that can be low only
du·ring Burst Read operations. This gate therefore starts the delay line controlled clock for Counter E (12H2). This circuit
generates the Answers (ANSWTl) (1212) and enables and steers the LMB register (LMF) (Sheet 2) onto the EDMA Bus.
Note that Counter E Stage A enables the multiplexors (Sheet 2) and Counter E Stage B (CfE B) selects the most
significant half of the LMB register first and the least significant half second. Meanwhile the EDMA transmitters (Sheet 2)
are enabled with the DMA Enable signal (DMENBO). DMENBO is generated (10E9) by the OR of Counter E Stage A
(which is the controlling signal for reads at this time) or Counter B not being at Count 0 (see Sections 11. 7 and 11.S).
This description has implied fullword transfers. For halfword operations, DMMC021 is low and the gate (1213) causes
Stage B of Counter E to be set on the first clock. This transfers just the least significant half of the data word.
The gates (12D4 and 12E4) generate End of Transmit (EOTO) along with the second ANSO except when it is a Burst Read
operation. This EOTO resets LMSEL flip-flop (12DS) ending the cycle.
11.11 EDMA Bus Burst Write to Local Memory (See Figure 15.)
Approximate time in nanoseconds
o
I
60
120
1
I
I
240
360
o
I
I
I
60
120
I
I
360
240
I
LOADOU--U
LDLSHO
u
u
WRITE SUFFER
LMRSO
I
I
LMRDYO
lMDSO
u
ANSTBO
LS
____r
Figure 15. EDMA Burst Write to Local Memory
The Burst Write mode starts the same as the half or fullword write but continues on after the data is sent to memory.
The Burst Write mode to Local Memory operates by referring to the Write Buffer Full flip-flop (WRTBUF) (12KS). As the
data is written out to Local Memory, ANSTBO is generated (11 M6) to signal the device that it may send more data.
CYCOMO resets WRTBUF when the Local Memory Data Strobe is sent out. WRTBUF is set when the LDLSHO signal
(12LS) loads the least significant half of the EDMA Data Register (DMF) (Sheet 1).
This operation continues with each CYCOMO incrementing the EDMA address register counter (Sheet 1) with the
CDMADI signal (1IG9) until the device sends an EOTO.
11.12 EDMA Bus Burst Read from Local Memory
The Burst Read mode starts the same way as the half or fullword read. It does not send out an EOTO with the ANSO
because of the gate at 12DS that inhibits EOTO when Burst Read (BRSTRDl) is decoded from the DMMC bits (12Bl).
The next memory access is made as soon as the Read Buffer is empty, by raising EHOLDO (11 N6) with the RDBUFLl
signal going low (II NS). The Read Buffer is emptied at the end of the data transfer to the bus.
The other controlling signal is RDYDATl (12DI). The flip-flop that enables this signal (12B3) is set by the LOADO as
received from the EDMA Bus and reset as soon as CfEA~ is set. CfE A is~Stage A of Counted': that generates the ANSOs
to the EDMA Bus (12H3).
The gate (12D!) starts the clock for Counter E when the buffer is full, when the EDMA is ready for data, and when it is a
Read operation (DMMOOI being high). EHOLDO is removed and the memory access started when the Read Buffer (12C2)
is emptied. The operation continues until the device sends an EOTO. The MBC initiates an extra Read to Memory at this
time, which is not used.
This information is propnetary and is supplied by INTEADATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used far any other purpose unless specifically authorized in writing.
21
11.13 Memory Access Contention Control
Sheet 13 contains the Memory Access Contention Control logic. It handles requests from either of three inputs. These are
EREQEI (13CI), CfENDO (l3C3 and 13E8), and the Stack Request flip-flop (1305). EREQEI is the request from the
EDMA Bus and CfENDO is the request from CPA.
These request signals are low active at the inputs to the first rank of flip-flops (Sheet 13). They also OR into the delay line
(I3F7). The 5 nanosecond tap on this delay line clocks the requests into the first rank of flip-flops and the 25 nanosecond
tap clocks the requests into the second rank of flip-flops. It is at this second rank of flip-flops that the contention is
resolved. If the EDMA or EFI flip-flop is set it has control of the memory. The CFI flip-flop indicates that CPA has
control of the memory unless EFI is also set. The bottom flip-flop is the Stack request flip-flop. It is the lowest priority
and is reset if either the EDMA or CPA flip-flop is set.
The Stack Request flip-flop is set when CPA requests an instruction from the upper half of the stack (SSREQAO) or CPA
has gone to memory for an instruction because it wasn't in the stack (CILMRSO).
CfENDO is low (requesting the memory) when from top to bottom of the AND-OR-Invert gate (l3D7) I. ANDing MOl,
SD500, (CEQLO or CEQUO), and CRQD201 - 50 nanoseconds after request to go to memory for Instruction Reads. 2.
ANDing CRQD301, GTUUl, and CRQDOOI - make a dummy access to memory that is not in this system configuration,
to prevent Processor hang-up. 3. a-feedback latch to store CfENDO until CYCOMO, DMARDYO, or STKRDYO. 4.
ANDing MOl, IRO, and CRQDOOI - Access to memory quickly if the request is to Local Memory and is not an Instruction
Read.
EREQEl is the OR of three EDMA Bus signals or states. From top to bottom (Sheet 12) they are: I. LMREQRl - Local
Memory is Requested by the Queued device. 2. LMSEL and Burst Read code until the end of the next Cycle Complete
(CYCOM). 3. LMSEL stored until next Cycle Complete and the DMMC bit that indicates a write command.
These requests are reset or at least removed during the Cycle Complete signal.
Local Memory Request Service (LMRSO) is generated at l3M7. The inputs to the AND-OR-invert gate are from top to
bottom: I. SSI - Stack access after a delay to let the multiplexor settle. 2. Feedback to act as a flip-flop and store the
request for timing elsewhere. 3. EFI AND EHOLDO - EDMA request and EDMA ready to access memory. 4. EFO AND
CFl - EDMA not requesting, and CPA is requesting. The D35 signal is from the delay line at 13F7 to cover overlap of
flip-flops, etc. The LMBBYO (l3F8) signal indicates that the first Ready signal has been received from the Local Memory
and the address cycle is over.
12. LOCAL MEMORY INTERFACE (LMI) BLOCK DIAGRAM ANALYSIS
The LMI boards (two per system) control access to the Local Memory Modules (LMM) from the Memory Bank Controller
(MBO via the Local Memory Bus (LMB). Whenever a request is made by the MBC, the appropriate LMI sends address data
and control signals to its Local Memory Modules (LMMs). Halfword and fullword data is steered to or from the LMMs
according to the type of memory access. The LMI also contains the parity generation and check circuits for its LMMs.
12.1 LMI Block Diagram (See Figure 16.)
The LMI boards are idle until the Local Memory Request Signal (LMRSO) is generated by the MBC. The LMIs respond by
performing a memory cycle. The memory cycle is the same for each type of memory access. They differ in the data
steering required. The following steps outline a memory cycle.
1.
Examine the address data on the LMB to determine which LMI should respond (refer to Section 3 on
interleaved address organization).
2.
Latch address and control data into registers of the correct LMI and indicate the start of the cycle by
"
sending LMRDYO to the MBC.
3.
The LMI sends ERO to its LMMs to begin the cycle.
4.
If the memory access is a Write operation, load data from the MBC into the write data register on the LMI,
steer write data and WRTO to the LMMs.
If the memory access is a Read operation, accept data from LMMs and store in Restore Cycle Data
Registers. Relay this data and LMRDYO to the MBC.
5.
Generate or check parity as required for the type of memory cycle. Indicate parity errors to Processor via
DLMPO and IRLMPO.
6.
Send INHO to the LMMs to begin write/restore phase of cycle.
Note that if the memory access is an Instruction Read, both LMls respond to the request (LMRSO) and each performs a
memory cycle for its block of memory. This is explained in detail in Section 13.
The following paragraphs describe each functional block of Figure 16. Each block includes the pertaining schematic sheet
number.
This information is proprietary and is supplied by INTEROATA for the lole
22
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
'-'
I
I
LED
PARITY ERROR I" EPSENO
INDICATORHHEX S E L } - l
STORAGE
OPSENO
SHEET 12
SWITCH
REGISTER SH 12
SH 12
TO CPU
r
IRLMPO
PARITY
GEN/CHECK
SHEET 11
DLMpn
LMB
~"
TRILMBOO:15 STATE
MUX
SHEET 1
,
MSoo:15
EBCLRO
MEMORY
WRITE
DATA
-[::?,
MDROO:15
RESTORE
CYCLE
DATA
REGISTER
SH4, 5,11
':)c>---+.-----ofREGsTERI-------.;..::...-+7i16:----t
LMB
BUFFER
SHEET 1
~MBI
LMB
TRI:31 STATE
MUX
SHEET 2
MDRCK!
~
MSOO:16
16
~
LOCAL
MEMORY
BUS
--
00:15
r-:
,---'------<"'1 SHEET 1
WRITE
DATA
STEERING
GATES
SH 4,5,11
I-MDoo:15
MOOO:16
,16
It R~
--'O:.;B:.;C:.;L::.;R.:.;0'-4l...... RESTORE
CYCLE
DATA
ROSEL
~EGISTER
SH 3, 11
MEMORY
WRITE
DATA
MDR16:31
:)c1----.-+t-----IbEGISTER
LMB
MDRCKt
16:31
BUFFER
SHEET 2
SHEET 2
MBC
INTERFACE
WRITE
DATA
isTEERING
GATES
SH 3, 11
16
LMM
INTERFACE
ADDRESS
OMPAR-~
4
~
ATOR
SHEET 9
_ _ _.,MAX06
LMARF.
MEMORY
ADDRESS
REGISTER
SH 6,7,10
17
MEMORY
1-_ _ _--1-_ _-I-_ _ _-.lADDRESS
,
2
MAX07
MAOO:14
DRIVERS
SH 6 7
LMDSO
'------ CONTROLI-----,p5'-,
CODE
' -_ _ _ _----<... REGISTER
SHEET 10
"
lEPINHl
OPINHI
rROOPl
(EPSENO
OPSENO
~~:~I
.---------------:R=:D=:S:-:E:-::y-L
SH9,'0,nl
LMRSO
LMBSYI
~
•
20 MHZ
CLOCK
ERO
CONTROL~I~N~H~O~---.
EIGHT STAGE
I
TIMING
EWRTO
~
I -_ _ _~JOHNSON COUNTERII-_~ao~1:~0~8_-t" LOGIC
OWRTO
I
1
LL:M~R~D~Y~0~_~SH!:E~E~T~8~9~
..
_ _ _ _~1===SH~EE~T~8==~_ _ _....,..,~=:-I SH B,9,10 OPENI
LMBSYI 11,1,3,5
IRPENI
LMBSY AO,BO,CO
-
11 1
~
INTERFACE TO
OTHER LMI
Figure 16, Local Memory Interface Functional Block Diagram
This information is proprietary and is IUPP'ied by INTERDATA for the IOle
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
23
12.2 Local Memory Bus Tri-State Multiplexors
The LMI uses the LMB to transmit data from a memory Read operation to the MBC. These multiplexors serVe as the LMB
drivers for this function. The drivers are normally in a high-impedance state and are enabled for approximately 100
nanoseconds during a memory Read operation by RDENO.
Note that this function is represented on the diagram as two blocks; one block drives LMBOO: 15, the other block drives
LMB16:31. This shows the data steering function for halfword Read operations. LMB16:31 is used for transmitting all
halfword format data between the MBC and LMI. These lines have two possible sources of halfword data (e.g., MSOO: 15
and MDOO: 15) corresponding to the most significant (even) halfword and the least significant (odd) halfword, respectively,
within any given full word. The correct selection of the source is made by RDSEL.
12.3 LMB Buffers
These serve to reduce the normalized load on each LMB line to one.
12.4 Memory Write Data Register
The Memory Write Data Register (MDR) receives data from the LMB for use in memory Write operations only. Data is
strobed into the register by MDRCKl, which is the buffered and control gated back panel signal LMDSO. The MDR is
shown divided into two blocks, and all data for halfword Write operations is stored in MDR16:31.
12.5 Restore Cycle Data Register
The Restore Cycle Data Register is used to store the memory module output data during a Read operation so that it can be
written back into memory during the restore phase of a core memory cycle. This is required under two conditions; that is,
during any Read operation, when the registers function as described previously, and during a halfword Write operation,
when one LMM is being written into while the second is not. Recalling that two Local Memory Modules (LMMs) are cycled
in parallel whenever the LMI is active, a halfword Write operation requires that the module which is not being written into
be cycled through a Read operation, leaving its data unchanged.
The Restore Cycle Data Registers are normally in a tracking mode and follow the data lines. They are latched by the
EBCLRO and OBCLRO control signals when the Local Memory Module (LMM) output data becomes valid.
12.6 Write Data Steering Gates
This block steers data to the correct LMM during memory Write operations. Note that the steering gates for the even
halfword (MSOO: 15) have two possible sources of data. MDROO: 15 is selected for a full word Write operation. MDR16:31 is
selected if a halfword Write operation to the even halfword is required, since all halfword write data from the MBC is
stored in MDR16:31. Write data steering is controlled by four signals called WTEOO:03. All Write Data Steering Gates are
disabled for memory Read operations.
12.7 Memory Address Register
The Memory Address Register (MAR) stores the 19-bit memory address provided by the MBC. The devices used in the
MAR are the tracking latch type, permitting the address to be quickly relayed to the Local Memory Modules (LMMs). It
should be noted that the MAR does not latch up an address unless that particular LMI is required to respond to it.
12.8 Memory Address Drivers
The Memory Address Drivers are high current devices used in conjunction with terminated memory address lines to provide
good transmission characteristics on these lines. This becomes important in systems that have additional memory located in
a separate chassis.
12.9 Control Code Register
The Control Code Register (CCR) works in the same way as the MAR, and is used to store the 5-bit control code that
identifies the type of memory access to be made (see Section 8).
12.10 Address Comparator
The Address Comparator takes the four most significant bits of the address from the MAR and compares them against an
upper and lower address limit for that LMI which is selected by a strapping feature. The address must be within the
allowed limits for the comparator to generate ADVO, which allows the control clock to start a memory cycle.
12.11 Control Decode Logic
The Control Decode Logic accepts the 5-bit control code stored in the CCR, the two least significant bits of the address
stored in the MAR, and generates all the combinatorial logic outputs required for LMI control. The more important signals
are shown on the block diagram.
24
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in Writing.
12.12 Oock
The Oock is a gated 20 MHZ square wave oscillator that provides the time base for operation of the LMI and control of
the Local Memory Modules (LMMs). Operation of the clock is conditional on LMRS1, ADVl, STCLKAl, and STCLKBI
all being valid. .
12.13 Counter
The Counter is an eight stage Johnson Counter driven by the 20 MHZ clock described previously. The outputs of its eight
stages are decoded to provide directly the signal timing needed within the LMI and LMMs.
Note that a ninth stage is shown in the schematics. This stage is only used when the system is configured with 64 KB Local
Memory Modules (LMMs) and is described in Section 13.7.
12.14 Control Timing Logic
The Control Timing Logic accepts the output from the Counter and Control Decode blocks as inputs and develops all time
based control signals required by the LMI and the Local Memory Modules (LMMs). In addition, the Control Timing logic
block controls the synchronization of two LMIs for the instruction read cycle. The important signals are shown on the
block diagram.
.
12.15 Parity Generation and Check
The parity logic generates the parity bits during Write operations and checks for correct parity during Read operations.
One parity bit is provided for each halfword of memory.
If a parity error is detected during a Read operation, the parity logic signals the Processor via IRLMPO or DLMPO, which
indicates parity error in an Instruction Read, or parity error in a data read, respectively.
12.16 Parity Error Storage Register
During a parity fail indication (IRLMPO or DLMFO), the Parity Error Storage Register determines which of the Local
Memory Modules (LMMs) being accessed is the source of the parity error and sets a flag to identify that module. The parity
error storage register can monitor up to 16 Local Memory Modules (LMMs), which is the maximum number that one LMI
can accommodate.
12.17 Hexadecimal Selector Switch and LED Readout
These two blocks are used to read out the contents of the Parity Error Storage Register and determine which of the Local
Memory Modules (LMMs) is the source of the parity errors received.
13. LMI DETAILED FUNCTIONAL AND TIMING DESCRIPTION
,
This section describes in detail the timing of all memory operations referencing Functional Schematics 35-534D08. The
reader should be familiar with Sections 1 through 9 before reading this section. The timing given here is for a system using
750 nanoseconds cycle time with 32 KB memories, and assumes that the memory being accessed is not busy when the.
request is initiated. Timing differences required by other memory modules is explained in Section 13.5.
13.1 Fullword Write
(See Figure 17.)
A fullword Write operation begins with address and control data being placed on the LMB by the MBC. The memory
address, in low-active polarity, is placed on LMB Lines 00: 18; while the 5-bit control code is placed on LMB27 :31 in
high-active polarity. LMB polarity is thus mixed at this time. Approximately 20 nanoseconds after the LMB data is valid,
the MBC generates LMRSO and holds it low waiting for the LMI to respond.
The 17 most significant bits of the memory address pass through the address tracking latches (Sheets 6 and 7) and are
transmitted via the MA Bus to the Local Memory Modules (LMMs). The four most significant bits are also routed to the
address comparator (913) where they are compared against the prewired upper and lower address limits for the LMI. If the
ADRS is within limits, ADVO (9R3) goes low, forcing ADVI (8L3) high.
If Bit 18 of the 19-bit address is in the correct state, as determined by a strap at IOF8, FWDO (10J8) goes low, forcing
STCLKAI (8K2) high. Bit 18 determines which of the two LMIs controls the fullword location desired, since the LMIs are
interleaved on fullwords. The Control Decode Logic decodes INSRDI (9C2) as low, since this is not an Instruction Read
operation.
This forces STCLKBI (8K3) high.
--~
Since the MBC is holding LMRSO low, LMRSI (8Ft) is high, and LMRSl, STCLKAl, STCLKBl, and ADVI sets CMO
(8N2) low. CMO starts the clock running (8B5) and the buffered clock output CLO (8C5) drives the eight stage Johnson
Counter (Sheet 8), which is triggered by the clock's negative going edge. The ninth stage, QAl (8L8), does not enter into
the count sequence (see Section 13.5).
Two features of the counter are: a self-start feedback decode (SSFBO) (8R5) which is used in conjunction with a complete
decode of one counter state (9B2) to assure that the counter does not lock into an undesired sequence of states, and its
modified interconnection of stages Q2l (8M6) and Qll (8N6) which causes the counter to have only 15 states, instead of
the normal 16 (see Timing Diagram, Figure 17).
.
This information is proprietary and is supplied by INTER DATA for the lole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unl... specifically authorized in writing.
25
p
100
200
I
I
300
400
I
I
500
I
B?O
700
800
I
I
:s:e Note 1
"'*
--L-M-B-O-O:-3-1-J
-
~
~
______~S~e~e~N~o~t~e~2~________________________________________________~
,.____'__
...
M."..'1..,.Ytf,..,8....
Q·...,~,.".t..,..,X.,..,07"'X
X~---
- VAll D -
LMRSO
CMO
CLO
071
061
051
031
021
011
ONEO
LMARFl
RFl
LMRDYO
ERO
INHO
LMDSO
M RCKl
EWRTO
OWRTO
ULMARO
RSRO
NOTE 1:
During this time, LMBOO: 18 contains the low-active address, and LMB27:31 contains the
high-active control code.
NOTE 2:
During this time, LMBOO:31 contains 32 bits of high-active data.
Figure 17. Fullword Write Timing
This information is proprietary and
IS
supplied by INTEROATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
26
not be used for any other purpose unless specifically authorized in writing.
Approximate time in nanoseconds
The first clock edge causes ONEO (9F3) to be generated, which in turn sets LMARFI (lOCI) high and RFI (BA2)10w.
LMARFI latches the address and control data into the Memory Address Register (MAR) and Control Code Register (CCR)
respectively; RFI keeps STCLKAI, STCLKBI, and ADVI high, while its complement, RFO (BC2), latches the Local
Memory Request flip-flop (BD2) in the high state. These insure that CMO remains low-active for the duration of. the
memory cycle. In addition, ONEO causes LMRDYO (9K2) to be sent back to the MBC. Upon receipt of LMRDYO, the
MBC releases LMRSO. The first clock edge also causes ERO (BF9) to be sent to the Local Memory Modules (LMMs), thus
beginning the memory access cycle.
The MBC places 32-bits of high active data on the LMB to be written into memory. It sends LMDSO to the LMIs which
becomes MDRCKI (l R6) and strobes the data into the Memory Data Register (MDROO:31) (Sheets 2 and 3). In the
interim, wrEOOI (l0L2) and WfE021 (l0L3) go high, steering the data to the MS and MD Busses (Sheets 3, 4 and 5) and
into the memory modules. Approximately 200 nanoseconds after the leading edge of ERO, EWRTO (9G6), and OWRTO
(9G5) are sent to the Local Memory Modules (LMMs), inhibiting the data currently stored in the accessed address from
being placed on the MS and MD Busses. Approximately 325 nanoseconds after the leading edge of ERO, INHO (BH2) is
generated and sent to the Local Memory Modules (LMMs). This begins the write phase of the memory cycle.
After the write phase is completed, ULMARO (9RB) unlatches the Memory Address Register (MAR) and the Control Code
Register (CCR), allowing address and control data for a new memory cycle to be accepted. Approximately 20 nanoseconds
later, RSRO (9GI) resets RFI high, which unlatches the Local Memory Request flip-flop and frees STCLKAI, STCLKBI
and ADVI for a new cycle. The timing of RSRO is such that CMO goes high and disables the clock when the counter is in
the clear (all low) state, thus leaving the control logic ready to begin another cycle.
13.2 Halfword Write (See Figure lB.)
o
I
__________
LMBOO:31
100
I
200
I
Approximate time in nanoseconds
300
I
400
I
500
600
I
I
800
I
700
(
~te~e~~No-t-e-2-------------------------------------------------------
~
~r_----------------------------------------------------------u
_L_M_R_SO________
LMROYO
ERO
INHO
WTEOll
MORCK1
n
I
EWRTO
I
OBCLRO
L
u-
ULMARO
RSRO
NOTE 1:
.
.
.'
_.
-During this time, LMBOO:18 contains the low·active address, and LMB27:31
contains the high·active Control code ..
NOTE 2:
During this time, LMB16:31 contains the 16 bits of high-active data.
LS
Figure 1.8. Halfword Write Timing (MoSt Significant Halfword)
The halfword Write operation is very similar to a fullword write; the difference is essentially in steering the halfword of
data from the LMB to the appropriate Memory Module Bus (MS or MD) and restoring the data in the other unmodified
halfword of the full word actually being accessed. (A LMI board always accesses two Local Memory Modules in parallel.
When a halfword operation is specified, the other, unused, halfword of the accessed location must remain unchanged.) This
section describes a halfword write into the most significant (even) halfword. A least significant (odd) halfword write may
be extrapolated directly from the descriptIon.
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supptied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
27
The halfword write cycle begins the same as a fullword write. The description in Section 13.1 up to and including the
generation of ERO applies here. After the receipt of LMRDYO, the MBC places the 16-bits of high-active data on
LMB16:31 and sends LMDSO which becomes MDRCKl(lR6) and strobes the data into MDR16:31 (Sheets 1 and 3). (All
halfword data transmitted over the LMB is placed on LMBI6:31.) WTEOll goes high and steers the data in MDR16:31 out
to MSOO: 15 (Sheets 4 and 5). WTEOOI and WTE021 remain low. Approximately 200 nanoseconds after the leading edge
of ERO, EWRTO (9G6) is generated, inhibiting the data currently stored in the most significant halfword from also being
placed on MSOO: 15. Approximately 350 nanoseconds after the leading edge of ERO, OBCLRO (3 L8) goes high, allowing
the data read out of the least significant halfword to be stored in the Restore Cycle Data Register flip flops of MDOO: 15
(Sheet 3). Approximately 325 nanoseconds from ERO, INHO (8H2) is generated and sent to the Local Memory Modules
(LMMs). During the write phase initiated by INHO, new data is written into the most significant halfword on MSOO: 15,
while the old data read from the least significant halfword on MDOO: 15 and stored in the Restore Cycle Data Register is
rewritten without change.
After the write phase is completed, ULMARO (9R8) and RSRO (9Gl) reset the LMI for the start of another cycle as
described in Section 13.1.
13.3 Fullword Read (See Figure 19.)
o
100
I
I
Ssee
LMBOO:31
__
200
I
Approximate time in nanoseconds
4~0
3?0
Not~e_1_______________________
X ~ X_
,see
5~0
700
I
800
I
No~_te___2__________________________________
~
LMRSO
LMRDYO
ERO
INHO
RDENO
MSOO:15
and MDOO:15
EBCLRO
RDYAO
ULMARO
RSRO
NOTE 1: During this time, LMBOO:18 contains the low active address, and LMB27:31
contains the high·active control code.
NOTE 2: During this time, LMBOO:31 contains 32 bits of high-active data.
Figure 19. Fullword Read Timing
The Fullword Read cycle begins like a fullword write. The description in Section 13.1, up to and including the generation
of ERO, is applicable here. After the receipt of LMRDYO, the MBC releases the LMB and waits for the LMI to respond
with data. Approximately 250 nanoseconds from the leading edge of ERO, RDENO (lA8) goes low active, enabling the 2: 1
multiplexors which serve as LMB drivets (Sheets 1 and 2). RDSEL (lOK5) is low, which steers MSOO: 15 onto LMBOO: 15
and MDOO:15 onto LMB16:31 (Sheets I and 2). The output data from the Local Memory Modules (LMMs) appears on
MSOO: 15 and MDOO: 15 no later than 275 nanoseconds from the edge of ERO, and is steered to the LMB as described
previously. At 325 nanoseconds from ERO another LMRDYO pulse (9K2) is generated by RDYAO (9G3) which indicates
to the MBC that data is valid on the LMB. Approximately 25 nanoseconds later, EBCLRO (5H8) and OBCLRO (3L8) go
high, allowing the data on MSOO: 15 and MDOO: 15 to be stored in the Restore Cycle Data Register flip-flops. INHO (8H2) is
generated 325 nanoseconds from ERO, initiating the write phase of the Local Memory Module cycle. This causes the data
stored in the Restore Cycle Data Registers to be written back into memory.
28
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unlen specifically authorized in writing.
After the write phase is completed, ULMARO (9R8) and RSRO (9Gl) reset the LMI for the start of another cycle as
described in Section 13.1.
13.4 Halfword Read
In all halfword Read operations, the requested halfword is placed on LMB 16 :31 (Sheet 2). A halfword read cycle to access
the least significant (odd) halfword in a fullword is identical to the fullword read cycle described in Section 13.3. The MBC
is this case only uses the data on LMB 16: 31.
In a halfword read cycle to access the most significant (even) halfword, RDSEL (IOK5) is high. All other details of the
cycle are identical to a full word read (Section 13.3). When RDSEL is high, the data on MSOO: 15 is steered to LMB 16 :31
(Sheet 2), from which it is accepted by the MBC.
13.5 Instruction Read (See Figure 20.)
Approxi mate ti me in nanoseconds
?
LMBOO:31
100
I
C See Note 1
XJ
200
I
300
I
400
500
I
,
[See Note 2
K-_----_-)( J
600
700
800
I
I
I
[See Not-;.e...:3~_ _ _ _ _ _ _ __
X J X_
LMRSO
STCLKAl
STCLKBl
CMO
LMBSYCO
'">,--_.....,,_ _~
LMBSYl
Delay Due To
a Busy LMI.
LMRDYO
First
LMI*
Response
Second
LMI
Response
L-J-------------~L-J~--~L_J~---------
ERa
INHO
.
RDENO -First LMI*
I
RDENO-Second LMI
* The first LMI controls the address containing the instruction halfword requested by CPA.
Note 1: During this time, LMBOO: 18 contains the low active address, and LMB27:31 contains the high active control code
Note 2: During this time, LMBOO:31 contains a fullword of data from the first LMI. *
Note 3: During this time, LMBOO:31 contains a fullword of data from the second LMI.
Figure 20. Instruction Read Timing
The Instruction Read operation is a double fullword (64-bits) read, in which both LMI boards cycle in parallel and each
sends a full word over the LMB in sequence. Two important features of LMI operation during this type of request are: 1.
Both LMI boards must be quiescent (Le., not cycling) before the operation can begin, and 2. The first of the two fullwords
of data sent to the MBC contains the instruction halfword requested by CPA.
This cycle begins with address and control data placed on LMBOO:18 and LMB27:31 respectively, followed by LMRSO
from the MBC (see Section 13.1 for details). INSRDO (9E2) goes low, forcing STCLKAI (8K2) high. If the address is
within range, ADVI (8L3) goes high. Since INSRDI (9C2) is high, STCLKBI (8L3) does not go high unless LMBSYI (9G8)
is low. As shown in Figure 21, LMBSYI does not go low unless LMBSYCO (9H8) from both LMIs is high, indicating that
both LMI boards are quiescent. This ensures that the LMI boards will cycle in parallel. When LMBSY 1 goes low, STCLKB 1
goes high. CMO (8BS) is forced low and starts the clock, and each LMI begins a fullword Read operation.
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
29
----,
_...,,~BSYrn
_ _--I.....
LMBSY~
I
~
...._ _
~----
L.BS~I
1_--
I
~
~" " ':L; : M~B:': :S":"Y:;:';BO: - 4+~
LMBSYAO
~Y1
__
L
EVEN HALFWORD LMI
ODD HALFWORD LMI
Figure 21. LMBSY1 Logic
The LMI that controls the address containing the instruction halfword requested by CPA completes a normal full word read
cycle as described in Section 13.3. Thus, RDENO (lA8) goes low 250 nanoseconds from the leading edge of ERO (8F9).
This is followed by a full word of data not later than 275 nanoseconds from the leading edge of ERO, and LMRDYO (9K2)
generated by RDYAO (9G3) logic 325 nanoseconds from the leading edge of ERO.
The other LMI also completes a fullword read cycle, but delays placing the data on the LMB as follows: data is received on
MSOO: IS and MDOO: IS not later than 275 nanoseconds from the leading edge of ERO as before, but RDENO does not go
low until 400 nanoseconds from ERO, at which time the fullword of data is gated to the LMB (note that RDENO in the
first LMI has gone high, disabling the outputs). This is followed by a LMRDYO pulse at 450 nanoseconds from ERO,
generated by RDYBO logic (9E4). Data from each of the two LMI boards is received, a fullword at time, spaced by 125
nanoseconds.
13.6 Parity Generation and Checking
Parity bits MSI60 and MD160, correspond to the most significant (even) halfword and least significant (odd) halfwords
respectively. The parity bit is generated whenever its corresponding halfword is written. When a Write operation is
initiated, the parity generator/checker integrated circuits (II C7) used for the halfwords being written into are enabled via
EPINHI (II Dl) and/or OPINHI (II C7) (e.g., on an even halfword write, only EPINHI goes low and enable the I.Cs. The
data on MSOO:15 or MDOO:15 generates EPGENI or OPGENI respectively, which is gated onto MSI60 or MDI60 by
WTE031 (II HI) and written into memory. If the operation is only a halfword write, the parity bit of the other halfword
that is accessed is read out of memory, latched into the open-collector flip-flop of that line (lIB for MS160, IIK6 for
MD160) and rewritten into memory. These flip-flops function identically to those of the Restore Cycle Data Registers (see
Section 13.3.)
In a Read operation, the parity bit for each halfword is read out of memory, latched into the open-collector flip-flops of
MSl60 and MDl60 and rewritten into memory. As with parity generation, only the parity generator/checker integrated
circuits used for the halfwords being requested are enabled with EPINHI and/or OPINHI. RDOP8 (lOH2) goes high,
allowing the parity bit as well as the data bits to be checked. A parity error in one of the halfwords is indicated by
EPERRO (IIH4) or OPERRO (IIG6). These are ORed to become PERRI (IIJ4), which is then gated by either IRPENl
(1114) or DPENI (lIB) to become IRLMPO (Instruction Read Parity Error) or DLMPO (Data Read Parity Error) respectively. Both IRLMPO and DLMPO are 50 nanosecond pulses that occur approximately 400 nanoseconds from the leading
edge o~ERO.
13.7 Local Memory Module Capacity and Timing (32KB 750 nanoseconds, and 32 and 64KB I microsecond.)
In addition to the 32KB 750 nanosecond Local Memory Module (LMM) which the previous description is based on, the
LMI can also accept I microsecond 32KB and 1 microsecond 64KB Local Memory Modules (LMMs). Use of these modules
requires several changes in the previous description. They are explained in detail in this section.
Use of the 1 microsecond 32KB Local Memory Module (LMM) requires a different strapping arrangement on the LMI
(shown on Assembly Drawing 35-534 E03) as well as timing pulses MCROAI (IIR2) and MCROBO (9M8), which should
nominally be 500 and 400 nanoseconds wide respectively. These pulses are adjusted with potentiometers located at 14R
and OOR respectively on the LMI. The Difference in the previous descriptions are: I. INHO does not occur until 420
nanoseconds from the leading edge of ERO, and remains 300 nanoseconds wide. 2. LMARFI stays high for an additional
125 nanoseconds, thus the MAR and control code register are valid for that additional time. This implies that all
combinatorial outputs based on the control and address bits also remains valid. 3. LMBSYCO remains low-active for 950
nanoseconds. 4. STCLKCI (8L4) inhibits restarting of the clock until I microsecond after the beginning of the previous
memory cycle.
The 1 microsecond 64KB Local Memory Module also requires a different strapping configuration and timing pulses
MCROAl and MCROBO. Pulse widths are reduced to 450 and 350 nanoseconds respectively. Omission of a Pulldown strap
(8H4) adds stage QAI (8K8) to the counter, modifying the counter sequence by adding an extra state. This is to
accommodate the 64KB module's slower access time of 325 nanoseconds. The effects of these changes on the previous
descriptions are: I. The following signals are delayed 50 nanoseconds with no change in pulse widths - INHO (8HZ),
OBCLRO (3L8), EBCLRO (5H8), LMRDYO - except the first pulse (9K2), RDENO (lA8), ULMARO (9Fl), and RSRO
(9Gl). 2. LMARFI stays high an additional 125 nanoseconds, maintaining address, control code, and combinatorial
outputs based on them. 3. LMBSYCO remains low active for 950 nanoseconds. 4. STCLKCl inhibits restarting of the clock
until 1 microsecond after the beginning of the previous memory cycle.
This information is proprietary and is supplied by INTEROATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
30
not be used for any other purpose unless specifically authorized in writing.
14. MEMORY SYSTEM TEST FEATURES
14.1 Parity Error Source Indicator (LMI)
The Parity Error Source Indicator (Sheet 12) detects the occurrence of a parity error (DLMPO or RLMPO) and sets a flag to
indicate which of the 16 Memory Modules controlled by the LMI is the source of the data causing the parity failure. The
occurrence of DLMPO or IRLMPO causes the flip-flop (12Nl) to be set, lighting the LED (l2R2). The control logic (Sheet
12) resolves the source of the parity error to the particular halfword (hence the particular Memory Module) from which
the erroneous data was received. This causes EPSENO (12J6) or OPSENO (12J8) to go low, depending upon whether the
error source was an even or odd halfword respectively. MPI (12J6) goes high if either DLMPO or IRLMPO are activated.
When all three enable inputs on a 3 to 8 decoder (l2K7) are activated, it decodes the three Most Significant Address Bits;
MLOOl, MLX061, and MLX07l (12J6) and the corresponding PDXXO (12L7) output goes low. This sets one of the 16 flag
flip-flops (Sheet 12).
To find the source of an error, a Hexadecimal switch (12K4) is rotated so that its outputs select one input at a time to the
two 8 to 1 mUltiplexors (12E3), which turns ON an LED (12J2) whenever the selected flag flip-flop is set. The Hexadecimal switch positions correspond to Memory Module locations as shown in Figure 22. The module that is the source of
a parity error turns ON the LED (12J2) when the hexadecimal switch is at that module's position.
In a system using 64KB Memory Modules, a maximum of eight modules are connected to each LMI and the Hexadecimal
switch positions correspond to Memory Modules as shown in Figure 23.
I
I
LMB
r
----,
-----~-----l
LMI
I
I __________
.J
LMI
EVEN HALFWO RD
MEMORY MOD ULES
L
ODD HAL FWORD
MEMORY MODULES
0
1
2
3
INCREASING
MEMORY
ADDRESSES
4
to
0
0
(f)
:a;
5
-
to
0
0
Cl
:a;
6
7
8
9
A
B
C
~
E
~
D
-
F
HEXADECIMAL SWITCH POSITIONS CORRESPONDING TO
EACH MODULE ARE SHOWN WITHIN THE BOXES
Figure 22. Parity Error Source Indicator - Hexadecimal Switch Positions for 32KB Modules
This Information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
31
LOCAL MdMORY BUS
I
rI
LMI
s:
en
g
-'"
0,2
-_
-_
-I
_
..1. _ _ _ _ ,
LMI
I
- _______ ...1
L
s:
0
!;l
-'"
1,3
4,6
5,7
B,A
9,B
C,E
D,F
HEXADECIMAL SWITCH POSITIONS CORRESPONDING TO EACH
MODULE ARE SHOWN WITHIN THE BOXES.
Figure 23. Parity Error Source Indicator - Hexadecimal Switch Positions
for 64KB Memory Modules
14.2 Force Parity Error Strap (LMI)
A strap (11F5) is provided on the LMI which, when installed, causes the LMI to generate a parity error on each memory
read cycle. The type of access (instruction or data read) determines whether IRLMPO or DLMPO is activated.
MEMORY SYSTEM TEST PROGRAMS
The following test programs are recommended to check the Memory System operation:
1. 06-156
Memory Test Program Parts 1, 2, and 3
This program checks all available memory in
various ways, using only the CPU port of the MBC.
2. 06-159
System Exerciser
This program checks the EDMA port of the MBC
and operates it in contention with the CPU port.
This program requires an ESELCH.
16. TROUBLESHOOTING
16: 1 Extender Board Operation
Use of the 28-015 Extender board allows convenient troubleshooting of the Model 8/32 Main Memory. It allows extended
operation of the MBC or either LMI. To operate any board on the extender, the extender board must be plugged into the
card me flot corresponding to that board. Only one board should be extended from the chassis at a time.
NOTE
In order to operate the MBC on an extender a
35-597 Extender Board Terminator must be
plugged into the spare slot of the extender board.
16.2 Troubleshooting Checks
If trouble develops and the memory system is suspect, the following checks are recommended:
1.
OJ.eck for proper seating of all boards and cable connectors.
2.
With the Power switch ON, measure P5, P16, and Nl6 on all memory chassis.
3.
If parity errors are the source of the problem; check the LMI Parity Error Source Indicators to detennine if
the problem is isolated within a particular Memory Module, i.e., possibly a defective module.
4.
OJ.eck for correct data and control (handshaking) between the MBC and the LMI boards. This usually
isolates the problem to either the MBC or the LMI boards and Memory Modules.
5.
If the problem only occurs for one particular state of the full word address bit, it is associated only with the
corresponding LMI and its memory modules. If, in addition, the problem is also restricted to one state of
the halfword bit, then it is associated with only one LMI and one bank of memory modules (see Section 3).
--
--
-
_.
This information is proprietary and is supplied by INTEADATA for the sole
purpose of using and maintaining INTEADATA supplied equipment and shall
32
not be used for any other purpose unless specifically authorized in writing.
16.3 Timing Adjustment
A timing adjustment is performed on all LMI boards at the factory to set the speed of the control logic clock. If the clock
driver IC or the delay line in the clock circuit is replaced on an LMI board, the clock should be readjusted via the strap at
board location 14D as follows (see schematic location 8C3):
1.
Place a strap between Pins 14D05 and 14D15.
2.
Place Processor in any memory access loop that continually cycles that LMI.
3.
Measure clock period signal CLO on Sheet 8D5 at the second clock pulse or later (not the first pulse)
and adjust strap until the period is 49.5 to 51.5 nanoseconds.
17. INSTALLATION
Mechanical installation of Model 8/32 memories is covered by the Installation Specification, 01-078A20. After the
equipment is mounted and connected, the following checks should be performed:
1.
Unplug all Main Memory System boards (MBC, LMIs, and LMMs)
2.
Adjust the power supply voltages as follows:
P5 to +5.0 Volts
PIS to + 16.5 Volts
Nl5 to - 16.5 Volts
3.
Power down and plug in all boards
4.
Power up again and check voltages; readjust if necessary
5.
Run Memory Test 06-156.
18. MAIN MEMORY SYSTEM MNEMONICS
The following lists provide a brief description of each mnemonic found in the memory system. The source of each signal
on functional schematic 35-535D08 (MBC) and 35-534D08 (LM!), is also provided.
18.1 8/32 Memory Bus Controller (MBC) Functional Schematic 35-535D08.
MNEMONIC
MEANING
SCHEMATIC
LOCATION
ADRFNI
Address cycle of EDMA transfer finished
l2J9
ANSO
EDMA Bus Answer
512
ANSRI
Answer Received
5GI
ANSTBO
Answer signal to transmitters-B input
IlN6
ANSWTl
Answer to EDMA bus transmitter
1212
BRSTWRTl
Burst mode write decode of EDMA
IlM6
BURSTRDl
Burst read decode of DMA control bits
l2Cl
C28EBO
CPA address Bit 28 equal to upper address in stack
8J8
CA120:300
Control Address lines from CPA
Sheet 6
CAF120:300
Control Address flip-flops address register zero output
Sheet6
CAF121:151
True side of Control Address flip-flops
Sheet 6
CCYCOMO
C Selected and Cycle Complete
13C6
CDOOO:310
Control Data lines to/from CPA
Sheet 4
CDMADl
Oock DMA address register
IIG9
CEQLO
CPA address equal to lower address in stack
8K9
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
33
MNEMONIC
MEANING
... SCHEMATIC
LOCATION
CEQUO
CPA address equal to upper address in stack
8R9
CFl/O
CPA select flip-flop in memory contention circuit
13F3
ClIO
CPA selected in memory contention circuit.buffered
13K3
CILMRSO
CPA access to memory with instruction read and local memory
l4G5
request service
CLKlA
Oock to EDMA Bus control counter
10Fl
CLKlB
Oock to counter B
10£6
CMCOOO:020
Control Memory control code from CPA
Sheet 11
CRDYO
C Ready signal to CPA
l4S8
CREQO
Control Request from CPA
6G6
CREQF I/O
Control Request flip-flop
6Al
CPA Request Delayed 00, 10,20, etc. nanoseconds
Sheet 14
CTAAI
Counter A Stage A
1012
CTABI
Counter A Stage B
ION2
CTACI
Counter A Stage C
1OL2
CTBAI/O
Coun ter B Stage A
lOE6
CTBOOO
Counter B not at count time zero
IOC8
CTBBI/O
Counter B Stage B
lOF6
croAI/O
Counter D Stage A
12G6
CTADl/O
Counter A Stage D
lOJl
CTDAI-LMSEL
Counter D Stage A and local memory selected
12H6
CTEAl/O
Counter E Stage A
12J3
CTEBI/O
Counter E Stage B
12L4
CTFAI
Counter F Stage A
llE4
CfFBI/O
Counter F Stage B
1IG4
CTFCI/O
Counter F Stage C
1IB4
CTFCLK
Counter F Oock
lICI
CTMOUTO
CPA Request Time out
14N2
CXREQO
CPA Request to EDMA
9N5
CYCOMBO
Memory Cycle complete buffered
IlG9
C28EAO
CPA address Bit 28 equal to lower address in stack Bit 28
8J9
D28EAO
DMA address Bit 28 equal to lower address in stack Bit 28
8E8
D28EBO
DMA address Bit 28 equal to upper address in stack Bit 28
8E9
D35
Memory contention request delayed 35 nanoseconds
13G6
DAOOO
Data strobe delay line output 00 nanoseconds
IlK8
Data strobe delay line output 30 nanoseconds
lIK8
CRQD
001
101
201
301
501
601
DA300
..
This_ information is proprietary and is supplied by INTEROATA for. the IOle
purpose of ",sing and maintaining.INTEROATA supplied equipment and shall
34
not be used for any other purpose unless specifically authorized in Writing.
MNEMONIC
MEANING
SCHEMATIC
LOCATIQN
DA700
Data strobe delay line output 70 nanoseconds
llL8
DA400
Data strobe delay line output 40 nanoseconds
llL8
DADl21:301
DMA Address register counter
Sheet 1
DATTMI
Data Time on LMB
l3M9
DB700
Delay line 70 nanosecond tap
12Jl
DEQO
DMA address equal to address in stack and DMA writing to memory
14Hl
DEQLO
DMA address equal to lower address in stack
8C9
DEQUO
DMA address equal to upper address in stack
8G9
DLMPFO
Data Local Memory Parity Fail
14A3
DMAACTI/O
DMAActive
IOJ4
DMAFWO
Fullword access from CPA to EDMA
2M9
DMA160:170
EDMABus
IM9
DMARDY A/B
DMA Ready-creates CRDY
IlM5
DMARYO
DMA RDY to CPA
14K8
DMCAO
DMA control address time
IOC7
DMENBO
Enable DMA transmitters
IOE9
DMFOOI :311
DMA Data Register flip-flops
Sheet 1
DMMCOOO :020
DMA Memory Control code
lK9
DMPFO
Data Memory Parity Fail
14C4
DMTOOl:171
Signals to DMA Transmitter
Sheet 2
DMX120:150
EDMA Bus lines
5L2
DPFI
Data Parity Fail
14C3
DREQI/O
CPA request to EDMA Bus
9L4
DXR121:151
DMX signal out of receiver
Sheet 5
EFBO
EDMA flip-flop in memory contention circuit-buffered
13K2
EFI/O
EDMA selected flip-flop in memory contention circuit
13Gl
EHOLDO
EDMA Hold memory access
llN6
ENBO
Enable memory busy on EDMA Bus
ION8
ENDO
End selected condition
ION9
ENEOTl
Enable End of Transmit
IOF8
EOTO
End Of Transmit
12F4
EOTO
End Of Transmit
IOG9
EQI
CPA address equal to an address in stack
14E6
EQIRCO
Equal and instruction read and CPA not still accessing memory
14F6
EREQEl
EDMA request to memory contention circuit
l3El
ERQWRTO
EDMA request and write command
l3Cl
GTUUl
Greater Than Unused memory lower limit
9E2
GXXI
Combination of ready signals
14K2
IR 1/0
Instruction read decode of CMC bits
llH7
IRWRTO
Instruction read or data write:-ready
14K8
This information is proprietary and is supplied by INTEROATA for the 1018
purpose of using and maintaining INTERDATA supptied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
35
MEANING
MNEMONIC
LDADRO
Load from EDMA Bus receiver
12E7
LDDMCI
Load DMA control bit register
I2E7
LDLMF1
Load Local Memory flip flops-Data Register
lIG9
LDLSHO
Load Least Significant Half of DMA Data Register
12K8
LDLSHI
Load Least Significant Half of DMA Data Register
lIN3
LDMSHO
Load Most Significant Half of DMA Data Register
12J8
LDMSHI
Load Most Significant Half of DMA Data Register
lIN4
LDSTA1
Load Stack address register STA
14K7
LDSTKO
Load Stack
lICl
LMB27 1
Local Memory Bus Bit-27
11J7
LMBOOO:316
Local Memory Bus signals to Local Memory Interface
Sheet 3
LMBBY1/0
Local Memory Bus Busy
13G8
LMDSO
Local Memory Data Strobe
lIN5
LMFOOO:310
Local Memory Bus flip-flops Data Register
Sheet 2
LMRDYO
Local Memory Ready
lIA7
LMREQO
Local Memory Requested
IOC4
LMRSO
Local Memory Request Service
13N8
LMSELl/O
Local Memory Selected
12D5
LMTMOTO
Local Memory Time Out
14S4
LOADO
EDMA Bus Load
5J2
LOADR1
Load Received
5Gl
LOADTO
Load signal to EDMA transmitter
IOF7
MOO
Same as memory zero except local memory zero active
9G8
MOl
Memory Zero, Local Memory One active
9G7
MIBZRO
Memory 1 Busy from EDMA Bus receivers
9J4
'M2BZRO
Memory 2 Busy from EDMA Bus receivers
9J4
M3BZRO
Memory 3 Busy from EDMA Bus receivers
9J4
MBOO
Same as memory zero except buffered zero active
9G7
MSTPOA:3A
Memory Address strapping upper address of each memory
most significant bit
36
SCHEMATIC
LOCATION
Sheet 9
MSTPOB:3B
Same as MSTPOA:3A except next MSB
Sheet 9
MSTPOC:3C
Same as MSTPOB:3B except next MSB
Sheet 9
MSTPOD:3D
Same as MSTPOC:3C except next MSB
Sheet 9
P5RB
P5 through Resistor B
IN7
P5RX
P5 through Resistor X
8H6
P5RY
P5 through Resistor Y
9AI
P5RZ
P5 through Resistor Z
12B3
QUEO
Queue
ION3
RDBUFLl/O
Read Buffer Full
I2D2
RDDATO
Read Data
lIH5
RDYDAT
EDMA Ready for Data
12D1
This information is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
MNEMONIC
MEANING
SCHEMATIC
LOCATION
N
.
RPCI
Receive Priority Chain
IONI
RSREQO
Reset stack request signal
13B6
SI
Stack selected in memory contention circuit
13M5
SBSYO
Stack Busy on LMB
14CI
SCLRBO
System Gear buffered
IOH9
SDl
Stack select delayed
13M5
SELl 10
Selected (CPA)
ION6
SLMSELO
Set Local Memory Select flip flop
12D5
SOTO
Start Of Transmit
IOM4
SPECIRI
Special instruction read stored signal
14K9
SMXO
Stack multiplexor control
13J4
SSI
Stack Selected
13M5
SSREQAO
Set Stack Request
14N6
STl61 :311
Stack output data
Sheet 5
STA121:281
Stack Address register bottom of stack
Sheet 7
STA280
Stack Address register LSB
7N2
STBI21 :271
Stack Address - middle of stack
Sheet 7
STCDO
Stack to CD lines
II C5
STHOLD
Start of Transmit Hold
IOK3
STKA1/0
Valid status of half of stack that contains upper address
14M6
STKRDYI
Stack Request Ready to CPA
14J8
STWA1
Stack Write Select A
14E2
STWB1
Stack Write Select B
14C1
SQUEF1
Set Queue flip-flop
9N5
SXIR
Stack multiplexor control or Instruction read
IID6
TOOA
Time Zero from delay line
IOA3
T80A
Time 80 nanoseconds delayed from delay line input
IOB2
WDTMO
Write Data Time
11M7
WRTBUFI/O
Write Buffer Full
12L8
XREQO
EDMA Bus request
lOA 1
XX1/0
Ready to be started
IOL6
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
37
18.2 8/32 Local Memory Interface (LMI) Functional Schematic 35-534008
MNEMONIC
MEANING
SCHEMATIC
LOCATION
ADVO
Output of comparators (Sheet 9) indicating that requested
address is within block of memory controlled by this LMI.
9N3
COO1:021
Buffered CMC bits from CPA which are part of the control
code transmitted from the MBC to LMI boards indicating
CPU requests to local memory.
Sheet 10
CLO
aock Output-pulse train drives Johnson Counter on
Sheet 11.
8C6
CLl
Complement of CLO, used to time RSRO pulse.
8D5
CMO
Cycle Memory-enables the clock and is held low
throughout the memory cycle.
8Nl
DLMPO
This low-active pulse is generated when an LMI detects a
parity error on any operation except instruction read.
11N8
EBCLRO
Even Buffer aear-is normally low and is asserted high
during a Read operation to latch data into the Restore
Cycle Data Registers for the even (most significant)
halfword.
5H8
EPERRO
Asserted low-active when a parity error is detected on a
Read operation from the even halfword memory bank of
an LMI.
IIG4
EPINHI
High active to inhibit parity generator/checking logic for
even halfword memory bank of an LMI.
lIDl
ERO
Early Read control signal for local Memory Modules begin
the memory cycle read phase.
8F9
EWRTO
Even Halfword Write-is asserted low-active when it is
desired to write into an even-address halfword.
9G6
EXI/0
Bit 4 of MBC-LMI control code which indicates an EDMA
request for local memory.
IOC7
FWI/O
MAR output bit which selects the LMI controlling
requested address.
IOE8
FWDl/O
Strap-selected level function which is low-active when this
LMI is selected by FWI /0.
lOG8
HEXOll :041
The output of a Hexadecimal rotary switch which select a
particular PFxxlline for display on an LED.
Sheet 12
HWI/O
MAR output bit which is the least significant address bit
and is used to select one of the two halfword memory
banks controlled by an LMI on halfword memory
operations.
IOH6
10021
An intermediate combinatorial decode used in various
functions.
10H3
ID030
An intermediate combinatorial decode used in various
functions.
1OL4
ID041
An intermediate logical decode signal used in various
9F2
functions.
INHO
38
Inhibit control signal of Local Memory Modules begins the
restore/write phase of a memory cycle.
This information is proprietary and is supplied by INTEAOATA for the lole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
8H2
MNEMONIC
MEANING
SOiEMATIC
LOCATION
-l
"t.
INSRDl
Combinatorial decode indicates access is an Instruction
Read.
9C2
IRLMPO
This low-active pulse is generated when an LMI detects a
parity error during an instruction Read operation.
IIM4
LMARFI/O
Level signal which changes mode of memory address
register and control code register between tracking and
latched.
lOCI
LMBOOO:310
32 Bit wide bidirectional Local Memory Bus used to
transmit data and addresses between the MBC and LMI
boards.
Sheets I and 2
LMBSY AO}
BO
Three control lines used to synchronize LMI cycles for an
Instruction Read (double fullword read).
9G8
LMRDYO
Ready signal from LMI to MBC indicates that LMI has
responded to request and is ready to accept write data, or
that read data is valid on the LMB.
9K2
LMDSO
Local Memory Data Strobe-loads data transmitted from
the MBC into the MDR.
LMRSO
Request line from MBC-indicates that MBC is requesting
the memory to cycle.
80l
MAOOO:140
Memory Address bits-concatenated with MAX060 and
MAX070 to form the address sent from the LMI to the
memory modules.
Sheets 6 and 7
MAX060 and 070
Extended Memory Address bits-see MAOOO: 14.
MCLRO
Memory Gear-buffered System Gear which is sent to all
Local Memory Modules.
8E7
MCROAI
Timing pulse used to control signals only when
microsecond cycle time local Memory Modules are used.
IINI
MCROBO
Timing pulse used to control signals only when
microsecond cycle time local Memory Modules are used.
9M8
MDOOO:160
Memory Data-is the bidirectional data bus which
transmits data between the LMI and the least significant
halfword (odd) bank of Local Memory Modules (LMMs).
Sheet 3
MDROOI:311
Output of the Memory Data Register which store data for
memory write operations only.
Sheets 3 and 4
MLOOO:OlO
Latched Memory Address bits-output of MAR.
6C7
MLX060 and 070
Latched Extended Memory Address bits. Output of the
tracking latches used for the MAR.
Sheet 8
MPI
Memory Parity Fail-high active when either DLMPO or
IRLMPO are asserted.
12L1
MSOOO:160
Memory Sense-is the bidirectional data bus which
transmits data between the LMI and the most significant
halfword (even) bank of memory modules.
Sheets 4 and 5
MSTRPO
Timing pulse used to control signals only when I
microsecond cycle time Local Memory Modules are used.
9M9
NULMARO
Used to unload memory address register and control code
register at the end of the cycle for 750 nanoseconds cycle
time memories.
9FI
CO
This information is proprietary and is supplied by INTER DATA for the IOle
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specificaliV authorized in writing.
39
MEANING
MNEMONIC
OBCLRO
Odd Buffer Gear-is normally low and is asserted high
during a read operation to latch data into the Restore
Cycle Data Registers for the odd (least significant)
halfword.
3L8
ONEO
Decode of the first state of the counter (Sheet 8) used to
initiate various memory cycle signals.
9F3
OPERRO
Asserted low-active when a parity error is detected on a
Read operation from the odd halfword memory bank of
an LMI.
llG6
OPINHI
High active to inhibit parity generation/checking logic for
odd halfword memory bank of an LMI.
lIDS
OWRTO
Odd Halfword Write-is asserted low-active when it is
desired to write into an odd-address halfword.
9G5
PDOOO:150
Each of these decoder output lines correspond to one of
the up to 16 local Memory Modules than an LMI can
control. A line is asserted low-active when a parity error is
detected on a Read operation to its corresponding memory
module.
Sheet 12
PFOOl: 151
The 16 outputs of the Parity Error Storage register. A line
is set high active when a parity error is received from the
Local Memory Module that particular flip flop represents.
Sheet 12
QOIO:080
Output of Counter flip-flops stages I thru 8 (flip-flop Q
outputs).
Sheet 8
QOll :081
Same as above but complemented (flip-flop Q outputs).
Sheet 8
QA1/0
Output of an additional (ninth) stage of the Johnson
Counter, used only when memory modules are 64 KB, 1
microsecond cycle time type to accommodate longer
access time of this module.
8L8
RDENO
Read Enable-goes low to activate the multiplexors/drivers
of the LMB on Read operations.
lA8
RDOPI
This signal is asserted high-active on any type of Read
operation.
lOH2
RDSEL
Selects the correct data for placement on LMB16:31 at
LMB2: 1 multiplexors/driver (Sheet 2). RDSEL is high for
an even halfword read and low for an odd halfword or
full word read.
lOK6
RFO
Complement of RFI, Captures LMRSO in tracking latch.
8C2
RSRO
Initializes the LMI at the end of a memory cycle.
9Gl
SCLRO
System Gear
8A8
SSFBO
Counter Self-Start Feedback-insures counter does not
remain in an undesired stable sequence of statues.
8R5
SX1/0
Bit 5 of MBC-LMI control code which indicates an
Instruction Read initiated by the look-ahead cache on MBC.
lOC5
ULMARO
Pulse to Unlatch Memory Address register and control
code register at the end of memory cycle.
9R8
WTEOOI
This data steering signal is asserted high-active for a
halfword Write operation into the most significant (even)
halfword.
1OL2
This information is proprietary and is supplied by INTER DATA for the sole
40
SCHEMATIC
LOCATION
purpose of using and maintaining I NTER OAT A supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
MNEMONIC
MEANING
SCHEMATIC
LOCATION
WTEOll
This data steering signal is asserted high-active for a
full word Write operation.
1OL4
WTE021
This data steering signal is high-active for a halfword write
into the least significant (odd) halfword or for a fullword
write.
1OL3
WTE031
This signal is asserted high-active on all Write operations to
enable the appropriate parity bit(s) to be written into
memory.
11Hl
XRPC
Pullup Resistor C
8N5
XRPD
Pullup Resistor D
12K3
XRPG
Pullup Resistor G
9E4
This .nformatlon IS proprietary and 15 supplied by I NTER OAT A for the lole
purpose of USing and mal~taln,"g INTEROATA supplied equipment and shail
not be used for any other purpose unleu specifically authorized In writing.
41/42
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Source Exif Data:
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