29 394R85_M83_Series_8 32_8 32C_and_8 32D_Processors_Maintenance_Manual_1983 394R85 M83 Series 8 32 32C And 32D Processors Maintenance Manual 1983
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QUICK REFERENCE INDEX
,
To aid in quickly locating a particular section, the index marks on the edge of this page are aligned with
similar marks on the first"Page of each section.
GENERAL DESCRIPTION
PROCESSOR
Tesf jJ;d
CON
hoI;> 5. '1 (P, t3
WRITABLE CONTROL STORE
2K WRITABLE CONTROL STORE
MEMORY
EXTENDED SELECTOR CHANNEL
DISPLAY PANEL
DRAWINGS
)
Page
1 of 1
MANUAL UPDATE PACKAGE COVER SHEET
MANUl\L TITLE:
M83 SERIES MODEL 8/32, 8/32C, AND 8/320
PROCESSORS Maintenance Manual
PUBLICATION
OLD REVISION LEVEL: R81
NUMBI~R:
29-394
ECN NUMBERS:
4979 5105
4953 5304
NEW REVISION LEVEL: R82 R84
R83 R85
This package updates the old pages of the subject manual with the
new pages. Please discard old pages ..
OLD PAGES
Title Sheet, R81
NEW PAGES
Title Sheet/Disclaimer, R85
Sheet v, R85
01-078 R04D08, Sheets 1, 4
01-078 R05D08, Sheets 1, 4
01-098 R03D08, Sheet 1
01-098 R04D08, Sheet I
35-535 R23D08, Sheets 1, 4
35-535 R24D08, Sheets 1, 4
35-539 R28D08, Sheets 1, 4
35-539 R29D08, Sheets 1, 4
35-555 RIOD08, Sheets 1, 3,
35-555 R12D08, Sheets 1, 3,
5, 8
5, 8
35-555 R06E03, Sheet 1 of 1
35-555 R07E03, Sheet I of 1
35-663 R02D08, Sheets 1, 4, 6
35-663 R03D08, Sheets 1, 4, 6
35-663 R02E03, Sheet 1 of 1
35-663 R03E03, Sheet I of 1
PERKIN-ELMER
M83 SERIES MODEL 8/32,
8/32C AND 8/320 PROCESSORS
Maintenance Manual
Comists of:
GENERAL DESCRIPTION
General Description
29-394R03A 12
PROCESSOR
Maintenance Specification
01-078R09A21
WRITABLE CONTROL STORE
Installation Specification
Maintenance Specification
35-555F01A20
35-555FOl ROl A21
2K WRITABLE CONTROL STORE
Installation Specification
Maintenance Specification
35-663ROl A20
35-663A21
MEMORY
Main Memory System Maintenance Specification
35-535R02A21
EXTENDED SELECTOR CHANNEL
I nstallation Specification
Maintenance Specification
02-328R04A20
02-328R03A21
DISPLAY PANEL
Hexadecimal Display Panel Specification
09-065R03A12
DRAWINGS
Model 8/32 Backpanel Map
Model 8/32C Backpanel Map (with DFU)
Model 8/320 Backpanel Map (with DFU)
Processor CPU-A Schematic
01-078R05D08
01-098R04D08
01-103ROOD08
35-536R30D08
Processor CPU-A Assembly
Processor CPU-B Schematic
Processor CPU-B Assembly
Processor CPU-C Schematic
Processor CPU-C Assembly
Processor CPU-C Schematic W/2K WCS
Processor CPU-C Assembly W /2K WCS
Processor IOU Schematic
Processor IOU Assembly
Processor ALU Schematic
Processor ALU Assembly
Memory Bus Controller (MBC) Schematic
Memory Bus Controller (MBC) Assembly
Local Memory Interface (LMI) Schematic
Local Memory Interface (LMI) Assembly
Extended Selector Channel Schematic
Extended Selector Channel Assembly
Hexadecimal Display Panel Schematic
Hexadecimal Display Panel Assembly
DMA Terminator Schematic
DMA Terminator Assembly
DMA Terminator Assembly
DMA Terminator Assembly
Processor Bus Terminator Schematic
Processor Bus Terminator Assembly
LMB Terminator Assembly
I/O Bus Terminator Schematic
I/O Bus Terminator Assembly
8/32 Backpanel Terminator
35-536R20E03
35-537R17D08
35-537R13E03
35-555R 12008
35-555R07E03
35-663R03D08
35-663ROl E03
35-539R29D08
35-539R19E03
35-538R16D08
35-538R11E03
35-535R24D08
35-535Rl0E03
35-534R12D08
35-534R08E03
02-328M(11 R08D08
35-508MOl R08E03
09-065R03D08
35-519R05D03
35-548C08
35-548803
35-572803
17-336R01803
35-569008
35-569R01C03
35-578R01B03
35-433808
35-433R03B03
35-596R01C03
29·394R85
The information in this document is subject to change without notice and should not be
construed as a commitment by the Perkin-Elmer Corporation. The Perkin-Elmer Corporation assumes no responsibility for any errors that may appear in this document.
The hardware description in this document is intended solely for use in operation, installation, maintenance, or repair of Perkin-Elmer equipment. Use of this document for all other
purposes, without prior written approval from Perkin-Elmer is prohibited.
Any approved copy of this manual must include the Perkin-Elmer copyright notice.
The Perkin-Elmer Corporation, Data Systems Group, 2 Crescent Place, Oceanport, New Jersey
07757
©1974, 1975, 1976, 1977, 1978, 1979, 1980, 1981, 1983 by The Perkin-Elmer Corporation
Printed In the United Statol of America
PREFACE
This manual provides information to operate, install and maintain
the M83 Series Model 8/32 Processors.
Revision 85 includes revisions 82 through 85 and reflects changes
to a:ssembly and schematic drawings.
For information on the contents of all Perkin-Elmer 32-bit
manu,als, see the 32-Bit Systems User Documentation Summary.
29-394 R8S
v
GENERAL DESCRIPTION
29-394R03A12
May 1978
METRIC
M83 SERIES
MODELS 8/32, 8/32C,AND 8/320
PROCESSORS
GENERAL DESCRIPTION
1.
INTRODUCTION
'The M83-Series 8/32 Processors are 32 bit micro-programmed minicomputers. By combining advanced circuits, packaging,
and micro-programming, Interdata gives the user price/performance optimized machines. The Model 8/32 was developed
because of the need for a high-speed 32 bit minicomputer. Because of Perkin-Elmer's experience with 16 bit minicomputers
and a user instruction format that is readily suited for a 32 bit machine, Perkin-Elmer is able to provide a 32 bit machipe.
The Model 8/32 is upward compatible with other current Perkin-Elmer Processors. Through micro-programming, the Model
8/32 Processor is able to provide present and future owners of Perkin- Elmer's 16 bit minicomputers the ability to grow into
a 32 bit Model 8/32 without having to regenerate all the programs that were created on their 16 bit Processors.
The M83-Series consists of three models: the 8/32, the 8/32C, and the 8/32D. The basic Model 8(32 introduced the
M83-Series modular processor architecture. In addition to the Control and Input/Output modules whose operations are
similar in all models of the series, the basic 8/32 contained a combined ALU/FAU module which performed either fixed
point arithmetic or single precision floating point arithmetic. The basic 8(32 backpanel wiring is shown on Back Panel
~'1ap 01-078008. The basic Model 8/32 (M83-023) is no longer a current Perkin-Elmer product.
The Model 8/32C Processor (M83-Q25) includes provisions for a High Speed Data Handling option (HSDH) which upgrades
the operations of the processor Auto Driver channel, and provisions for a High Performance Floating Point option (OFU)
which performs both single and double precision floating point operations. In the Model 8/32C and the Model 8/32D, the
existing single-precision floating point ability of the ALU module is only available through the facilities of a Writable Control
Store option (WCS). The Model 8/32C is configured with 32KB 750 nanosecond core memory modules expandable through
two expansion chassis to one megabyte. The Model8/32C back panel wiring is shown on Back Panel Map 01-098008.
The Model 8/320 Processor (M83-030) is identical to the 8/32C except that it is configured with 64KB 750 nanosecond core
memory modules expandable through one expansion chassis to one megabyte, and the boards have different chassis slot positions (see chart on page 4). The Model 8/32D backpanel wiring is shown on Back Panel Map OI-103D08.
The Model 8/32 Processors have 148 instructions defined whieh include arithmetic and logical, operational, list processing,
floating point, cyclic redundancy checking, and bit and byte manipulation instructions. Double indexing is also allowed, along
with a multitude of branch instructions. There are 40 extended branch instructions (Mnemonics) defined which brings the
total instructions to 180. Through these instructions and direct addressing, coding and debugging time is reduced to a minimum.
The 8/32 Processors offer 32 General Registers, each 32 bits wide, in two sets of 16 (optionally expandable to 8 sets). Register
set selection is controlled by bits in the Program Status Word. The multi-set organization offers fast and simple context switching without the necessity of storing and restoring register sets. See 32 Bit Series Reference Manual, Publication Number 29-365.
29-394A12 R03 5/78
I
The 8/32 Processors cont.lin 1,280 words of micro-programmed Control Store in the Control Module. The Control Store may
be optionally expanded through a 512 word and/or a 2,048 (2K) word Writable Control Store (WCS).
The 8/32 Processors are capable of directly addressing up to 1,048,576 bytes of memory, through the Local Memory Bus.
Memory is constructed of 32KB or 64KB memory modules. Memory is addressable to the eight-bit byte level. No paging or
indirect addressing is required by the user instruction sets. A Multiport Memory option is available which allows multiple
processors to share memory. In addition, a Processor/Memory Parity Generation and Checking Hardware option is available.
The processors contain a Memory Access Controller (MAC) and a Memory Bus Controller (MBC). The MAC contains its own
sixteen 32 bit hardware registers to allow segmentation, relocation, and memory protection of user programs. The MBC provides access to both the Local Memory Bus (LMB) and the Extended Direct Memory Access Bus (EDMA). The EDMA Bus
is a high quality, high-speed bus that may have up to seven EDMA devices attached. These optional devices include the
Extended Selector Channel (ESELCH) which provides direct memory access to high speed peripherals at a transfer rate of 2
million bytes per second; the Buffered Selector Channel (BSELCH) with a EDMA transfer rate of up to 6 million bytes per
second; the Memory Access Multiplexor (MAM), a direct memory access port which provides interleaved block transfers of
data between multiple low and medium speed peripheral devices and memory; the EMAM, an enhanced version of the MAM;
and the EDMA Bus Universal Interface used in designing custom controllers. The ESELCH or BSELCH may have up to 16
devices attached, and may be extended for additional devices through the use of the I/O Switch.
The 8/32 Processors provide a flexible automatic input/output system through the processor Multiplexor Bus in addition to
the conventional means of programmed I/O. The Processors can have up to 1,023 auto driver channels, implemented through
the microcode instructions. These provide fast automatic character input/output operations including automatic conversion
from one character to another. Each character is transferred into or out of memory without any effect on a running program
except for a small amount of stolen time. The auto driver channel operations may be optionally enhanced through the
High-Speed Data Handling option. The Multiplexor Bus can have up to 16 peripheral controllers attached directly, but may
be optionally extended through the lise of the [/0 Switch.
2
29-394A12 R03 5/78
2. RELATED PUBLICATIONS
J
Table 1 contains a list of related Perkin-Elmer publications which may be useful in the programming or trouble shooting
of the M83-Series 8/32 Processors.
TABLE 1. RELATED PUBLICATIONS
Title
32 Bit Series Reference Manual
Series 32 Pocket Guide
Models 8/32, 8/32C, 8/32D Processors User's Manual
Installation Planning Guide
Model 8/32 Customer Installation Manual
Model 8/32 Installation Manual (for Perkin-Elmer Internal use only)
Models 8/32C and 8/32D Customer Installation Manual
Models 8/32, 8/32C, and 8/32D Processors Mi cro Instruction Reference Manual
Perkin-Elmer Model 8/32 Writable Control Store (WCS) User's Guide
Models 8/32C and 8/32D Communication Instruction Package Maintenance Manual
8/32 DFU Instruction Manual
32KB (750 ns) Core Memory Maintenance Manual
64KB (750 ns) Core Memory Maintenance Manual
Multipart Memory Instruction Manual
Shared Local Memory Interface (SLMl) Maintenan..:c Manual
EDMA Bus Universal Interface Instruction Manual
Extended Selector Channel (ESELCH) Programming Manual
Buffered Selector Channel (BSELCH) Maintenance Manual
Buffered Selector Channel (MOl) Maintenance Manual
Memory Access Multiplexor (MAM) Maintenance Manual
MemOlY Access Multiplexor (MAM) Programming Manual
EMAM Maintenance Manual
EMAM Programming Manual
Input/Output Switch Maintenance Manual
Input/Output Swi tch Programming Manual
Universal Clock Instruction Manual
Digital Multiplexor System Instruction Manual
High-Speed Paper Tape Reader/Punch Technical Manual
Paper Tape Reader Manual'
Teletype Interface Instruction Manual
Current Loop fnterface Maintenance Manual
Model 1100 Terminal User/Maintenance Manual
Model 1200 Terminal User/Maintenance Manual
Card Reader Manual
Intertape Cassette System Instruction Manual
N.S. Line Printer Maintenance Manual
Fully Buffered Line Printer 300 LPM Manual
Read After Write Magnetic Tape System Instruction Manual
1600 BPI Magnetic Tape System Instruction Manual
Dual Density Tape System Maintenance Manual
2-5 MD Disc Perkin-Elmer Maintenance Manual
10MB Disc Maintenance Manual
Removable Media Mass Storage Module (MSM) Maintenance Manual
Mini I/O System Instruction Manual
Micro I/O Bus Adaptor Instruction Manual
Analog Input Controller System Programming Manual
Analog Output Controller System Programming Manual
Digital I/O (DIO) Programming Manual
8/32 Test Display Instruction Manual
Publication Number
29-365
29-445
29-428
29-583
29-526
29-449
29-537
29-438
29-479
29-520
29-538
29-493
29-593
29-539
29-611
29-423
29-529
29-572
29-590
29-422
29-474
29-609
29-610
29-616
29-617
29-427
29-209
29-334
29-549
29-288
29-444
29-605
29-612
29-510
29-297
29-313
29-511
29'-295
29-309
29-559
29-487
29-486
29-644
29-443
29-597
29-475
29-476
29-477
29-525
..
29-394A12 R03 5/78
3
3.
BLOCK DIAGRAM
A simplified block diagram of the Model 8/32 system is shown in Figure 1. The Processor logic is contained on three circuit
boards. The Memory Bus Controller (MBC), Local Memory Interface (LMI) and memory are contained on separate boards.
The Arithmetic/Logic Unit (ALU) and Input/Output Unit (IOU) are also separate boards. The 8/32 Processors are contained
in a standard 16 slot Perkin-Elmer Twin Chassis which is divided into an Upper (U) 8 slots (numbered 0-7) and a Lower (L)
8 slots (numbered 0-7). Shown below are the chassis slots associated with specific processor boards.
Part Number
Description
8/32
Chassis Slot
8/32C
8/32D
35-534
Local Memory Interface
(LMI)
3U,6U
3U,6U
2U,5U
35-535
Memory Bus Controller
(MBC)
lU
lU
lU
35-536
Control Processor A
(CPA)
au
au
au
35-537
Control Processor B
(CPB)
7L
7L
7L
35-555
or
36-663
Control Processor C
(CPC)
6L
6L
6L
35-538
Arithmetic Logic Unit
(ALU)
4L
3L
3L
35-539
Input/Output Unit
(IOU)
3L
OL
OL
Floating Point*
(DFA)
--
5L
5L
Floating Point
(DFB)
-
4L
4L
Memory
2U.4U,5U,7U
2U,4U,5U,7U
3U,4U,6U,7U
*Optional
4
29-394A12 R03 5/78
I
510-1
32 KB
OR
r---, r---'I r--- . .
I
I
I
I
I
I
32 KB
OR
64 KB
I
I
L_.,.._..I•
32 KB
OR
64 KB
I
32 KB
L_..,..._.J
I
I
I
I
I
{ '8,,, 128 K8 OF MEM FOR
8/32 & 8/32C
4tl1 256 KEl OF MEM FOR
8/320 (1MB TOTAl)
:
OR
I
I
I 64 KB I
L_,-_..J
NOTE
32 KB MODULES FOR 8/32 & 8/32C
64 KB MODULES FOR 8/32D.
LOCAL MEMORY BUS
----------------~
MEMORY BUS CONTROl LER
IMBC}
EDMA BUS
F::::'--=1 E~~? ----LOO/(AIJE'AD STACK
E_3 E:":::::~3
() X
64 BITS I
ESELCH'
EDMA BUS
UNIVERSAL
INTERFACE'
OR
BSELCH*
16 DEVICES
MODI:L 832
MULTIPLEXOR BUS
....._ _ _ _ _'" CUSTOM
DEVICE
MAM'
PROC~:,S()f{
-~ 1--.= I~.-~~-I;l.- .-- ~~;~
1
~'\lEF.SAL
-
L-..!:LCCK
-
GENERAL
_
--
-
OR
EMAM*
REGISTERS
-
-
~
--
CARTRIDGE
DISC
-
-
63 MUX BUS
DEVICES
~~
Y
I/O
SWITCH*
r
1
~
r
SBU~.-
32
fCARD
L!EADER
32
32
32
32
r
MODULE 0
I
I
CPU A
(MAC)
_______-,___
CPU B
CPU C
(ROM)
(WCS')
MODULE 1
(AND 3')
MODULE 2
MODULE 6
lOR 6 & 4)
ALU
IOU
DFU'
HSDH'
-,.__.. 1_...,._...
1
32
32
:32
32
32/
A BUS
/
_ _ _ _ _ _---'-_ _ _ _- L - .
B BUS
--~---
MUX BUS
___
......l
*OPTIONAL EQUIPMENTS OR PROVISIONS
FOR USE WITH OPTIONAL EQUIPMENT
MINI I/O
SYSTEM'
MICRO
BUS
ADAPTER*
ANALOG
CONVERSION
EQUIPMENT'
I/O
SWITCH"
-!f ,
Figure 1. 8/32 Processor Block Diagram
29-394A12 R03 5/78
5
4.
DOCUMENTATION
nlis section describes the style and conventions used with Perkin-Elmer documentation.
4.1 Number Notation
The most common form of number notation used in Perkin-Elmer documentation is hexadecimal notation. In this system,
groups of four binary digits are represented by a single hexadecimal digit. Table 2 lists the hexadecimal characters
employed.
TABLE 2. HEXADECIMAL NOTATION DATA
Binary
Decimal
0000
0001
0010
0011
0100
0101
Hexadecimal
a
a
I
2
3
4
5
1
2
3
4
5
Binary
0110
0111
1000
1001
1010
1011
Decimal
Hexadecimal
Binary
Decimal
Hexadecimal
6
7
8
9
10
11
6
7
8
9
A
B
1100
1101
1110
1111
12
13
14
15
C
D
E
F
To differentiate between decimal and hexadecimal numbers, hexadecimal numbers are preceded by the letter "X" and the
number is enclosed in single quotation marks. Examples of hexadecimal numbers are: X' 1234', X'2EC6', X'AE40', X'EEFA',
and X'I OB9'. With 32 bit systems the letter Y may be used to distinguish between 16 and 32 bit references ( X for 16 bit, Y
for 32 bit notation).
I
4.2 Part Numbering System
I
Perkin-Elr~ler parts, drawings, and publications employ a common numbering system. The part number and drawing
numbers for drawings which describe the part are related. Figure 2 shows the format used for Perkin-Elmer part numbers.
The fields are described in the following paragraphs.
A
B
C
D
XX
YYY
CATEGORY
SEQUENCE
FNN
MNN
'--y----J
RNN
,FUNCTIONAL MANU~ACTURING,REVISION
VARIATION
E
~
,SIZE
TYPE
DRAWING
I
Figure 2. Part Number Format
4.2.1 Category Field. The two-digit Category number indicates the broad class or category to which a part
belongs. Typical examples of category number assignments are:
01 - Basic Hardware Systems
02 - Basic Hardware Expansions
03 - Basic Software Systems
04 - Software Packages
05 - Micro-programs
06 - Test Programs
07 - Subroutines of General Utility
10 - Spare Parts Packages
12 - Card File Assemblies
13 - Panels
17 - Wire and Cables
19 - Integrated Circuits
20 - Transistors
27 - Peripheral Equipment
29 - Manuals
34 - Power Supplies
35 - Assembled Printed Circuit Boards
36 - Electro-Mechanical Devices
6
29-394A12 R03 5/78
4.2.2 Sequence Field. The Sequence number identifies a particular item within the category. Sequence numbers
are assigned serially, and have no other significance.
NOTE
The Sequence Field, like all other part number
fields, may be lengthened as required. The field
lengths shown on Figure 2 are minimum lengths
(insignificant zeros must be added to maintain
these minimums).
A part number must contain a Category number
and a Sequence number. All other fields are optional.
4.2.3 Functional Variation Field. The optional Functional Variation Field consists of the letter "F" followed by
two digits. The F field is used to distinguish between parts which are not necessarily electrically or mechanically equivalent, but which are described by the same set of drawings. For example, a power supply may be strapped internally to
operate on either 110 V AC or 220 V AC. Except for this strap, all power supplies of this type are identical. The strapping
option is easily described by a note on the assembly and test specification drawings. Therefore, this is a functional
variation.
4.2.4 Manufacturing Variation Field. The optional Manufacturing Variation Field consists of the letter "M"
followed by two digits.
The M Field is used to distinguish between parts which arc electrically and mechanically equivalent (interchangeable), but
which vary in method of manufacture. For example, if leads are welded instead of soldered on an assembly, the M Field
changes.
An important exception to the meaning of the M Field exists for categories related to software·. In software, the M Field
number, when used, indicates the form in which a particular program is presented. For example, define a program as a set
of machine instructions. These same identical instructions may be presented on punched cards, paper tape, or magnetic
tape; and for any of these they could be in symbolic form or in relative or absolute binary form. Thus, there are many
ways 1to present the same identical program.
The format for the M field and its meaning for software is:
Mxy
where x identifies the media selection (i.e., paper tape, mag tape, cassette, etc.) and
y identifies object or source and the format.
Meaning of x
Meaning of.¥
Paper tape
Object program standard format 32 bit Processor
CasseUe
2
4 Memory Image
Mag tape (800)
3
6 Object program standard format 16 bit Processor
Cards
4
7 Object non-standard format
Disc (2.5)
5
8 Object established task
9 Source program
The above numbers refer to the physical program placed on an approved media for Perkin-Elmer Software. A paper tape
object program in standard format and for a 16 bit Processor has an M 16 identifier. A magnetic tape object program in
standard format and for a 32 bit Processor has an M31 identifier.
In addition to the above, there are several unique M numbers which have special meaning:
I
always refers to a software package reference document
M95
M99 always refers to a documentation package.
MOO always refers to a conceptual object program divorced from any media. TIlis reference is used for all parts lists
when object programs may be on any media.
M90 always refers to a conceptual source program and is used on all parts lists where any media may be used.
•
NOTE
MOO ana M90 may only be used on parts
lists and never identify a physical program
on any media.
29-394A12 R03 5/78
I
7
4.2.5 Revision Field. The optional Revision Field consists of the letter "R" followed by two digits. The R Field
is used to indicate minor electrical or mechanical changes to a part which do not change the part's original character. R
Field changes often reflect improvements. A part with a revision level HIGHER than the one specified will work. A part
with a revision level LOWER than specified should not be used.
4.2.6 Drawing Field. The optional Drawing Field consists of a letter from "A" to "E" followed by two digits.
The letter indicates the size of the original drawing. The sizes for each letter are:
A - 216 mm X 279 mm ( 8V2" X 11" )
B - 279 mm X 432 mm (11" X 17")
C - 432 mm X 566 mm (11" X 22")
D - 566 mm X 864 mm (22" X 34")
E - 864 mm X 1118 mm (34" X 44")
The two digits indicate the drawing type as follows:
01 - Parts List
13 - Program Listing
02 - Machine Details
14 - Abstracts
03 - Assembly Details
15 - Program Description
05 - Art Details
16 - Operating Instructions
06 - Wire Run List
17 - Program Design Specifications
08 - Schematic
18 - Flow Charts
09 - Test Specification
19 - Product Specification
10 - Purchase Specification
20 - Installation Specification
11 - Bill of Material
21 - Maintenance Specification
12 - Information
22 - Programming Specification
4.2.7 Examples. The following list provides examples of the part numbering system. The numbers were arbitrarily selected, and in most cases are fictitious.
35-060
The 60th printed-circuit board assigned a part number under this system.
35-060MOl
A printed circuit board electrically and mechanically interchangeable with the 35-060, but differing in
method of manufacture.
35-060FOI
A printed-circuit board not electrically and mechanically interchangeable with the 35-060, but described by the same set of drawings.
35-060RO 1
A revised 35-060 printed-circuit board. Probably supercedes the 35-060.
35-060AOI
The 216 mm X 279 mm (8V2" X 11") parts list for a 35-060.
35-060B08
The 279 mm X 432 mm (11" X 17") schematic for a 35-060.
06-072
The 72nd utility program assigned a part number.
06-072A13
An 216 mm X 279 mm (8V2" X 11") listing of the 06-072 program.
06-072M03
An absolute binary deck of punched cards for the 06-072 program.
06-072A12
The 216 mm X 279 mm (8Y2 X 11") information drawing on the 06-072 program. Probably a
part of the program.
29-060
The 60th manual assigned a number under this system. Note that this number is not referenced in any
way to the part number of equipment described in the manual.
8
29-394A12 ROO 12/74
4.3 Drawing System
This section describes the drawings provided with Perkin-Elmer equipment. Note that drawings provided with peripheral
devices an,d other purchased items may vary from the system described in this section.
A digital system may be divided into a collection of functionally independent circuits such as memory, Processor, and I/O
device controllers. These circuits mayor may not be saleable units in their own right, but in the electrical sense they are
essentially self contained and capable of perfonning their function with minimum dependence on other functional circuits
in the system. Hence a functional circuit is treated as a building block. Each schematic contains a variety of information
induding type and location of discrete Integrated Circuits (lC's), pin connections, all interconnections within the schematic, connector pin numbers and connections to other schematics. Further, the schematics are drawn to reflect, in an
orderly fashion, all logical operations performed by the circuits. Generally, symbols used on schematics conform to
MIL-STD-B06B.
Registers are named according to the following rules:
1. The register Mnemonic name has a maximum of three letters, excluding "I, 0, Q, and Z".
2. Each bit in the register is numbered, usually starting at 00 on the left, or most significant positions, and continuing
to N-I on the right, where N is the number of bits in the register.
3_ The 00 bit is the Most Significant Bit and the N-l is the Least Significant Bit.
The IC's, mounted directly on the logic board, are represented on the schematic drawings by )'ogic symbols. Each symbol
contains the reference designation, device part number (category and sequence), and symbol Mnemonic designation. Refer
to Figure 3.
~
LI
SAME SHEET DESIGNATION
ENBLI
.,RD020
218-0 RD031
117-0
114-0 RD061
ANOTHER SHEET
01
02
04
05
DESIGNATION-~
~{
1:r~9-061
06
NAMEO
sa
10M1
12A2
18K4
Figure 3. Example of a Schottky Buffer
The designations, numbers, and references shown in Figure 3 are:
lIS -
This indicates the component location on the logic board. Figure 4 illustrates the method generally used to
determine component location on a logic board. With the logic board oriented so that the header connectors
(Conn 0 and Conn 1) are on the right, the components are numbered from left to right starting in the upper
left corner. That is, the first IC in the upper left comer is OOA and the first capacitor is Cl. Test points are
lettered right to left from A-Y (omitting I, 0, L, E).
19-061 - The number 19 is the category number of les, and the 061 is the sequence number of the component.
SB -
Indicates this component is a Schottky Buffer. Some other common designations used are: _
P - Power Gate
SA - Schottky AND Gate
SB - Schottky Buffer
SG - Schottky Gate
SGO - Schottky Gate, Open Collector
HG - High Speed Gate
HPO - High Speed Power Gate, Open Collector
SFP - Schottky Flip-flop
L1 - This input lead is from area LIon the same schematic sheet.
10M 1, 12A2, 1BK4 - Indicate outputs to another logic schematic sheet.
2IB-0, 117-0, 114-0, - Indicate inputs from Connector O.
Note that the pin numbers (01, 02, 04, 05 and 06) correspond directly to the actual IC pin numbers.
Figure 4 also shows the locations of the header connectors (Conn 0 and Conn 1) and the cable connectors (Conn 2. and
Conn 3). All logic boards always contain Header Connectors 0 and 1, however, any combination (either, both, or none) of
cable connectors (Conn 2 and Conn 3) may be provided.
29-394A12 ROO 12/74
9
Y CIDA
0
16
B
C
o
S
M
[,06sJ 1DOT 141
100AI~loocl
2
I I
100~
CONNECTOR 1
0
24
CONNECTOR 4
00
00
2 1
~~
2 124
0
1
I
I
I
I
I
I
0
I
I
I
CONNECTOR 0
I
0
00
I
I
I
I
I
I
I
I
I
I
2
00
I
41 Y I'
,DO
2
:
I
2
CON~ECTOR 3
D 1~ONNECTOR
I I'
I I
CONNECTOR 5
I
I
I
~
J
2
A
Figure 4. Example of a Logic Board Layout
Clocked devices, flip-flops and counters in particular, are drawn in a manner which indicates information concerning their
inputs. An input which has a circle adjacent to the pin designation implies a low active signal is required to perform the
specified operation. In addition, a rotated V at the clock input shows that the device changes state on an edge. Thus, if
no circle is present the chip is positive edge triggered. Refer to Figure 5 for examples.
Figure 6 provides the pin numbering scheme for the header and cable connectors. Header connectors always have 2 rows of
pins and 42 positions. Cable connectors always have 2 rows of pins but may vary in the number of positions.
J
OS
FPSELI
FPSELOA
19-015
HG
19-045
HFF
0
OS
0
0
19-089
SDFF
FPSELO
C
19-027
OFF
C
0
DC
A. NEGATIVE EDGE TRIGGERED
B. POSITIVE EDGE TRIGGERED
C. POSITIVE LEVEL TRIGGERED
Figure 5. Examples of Clocked Devices
10
29-394A12 ROO 12/74
241-1-t~~.........
16
15
0
0
0
0
24
23
22
0
0
0
0
0
0
141-1
-
41
40
122-3
39
38
222-3
37
CONNECTO~1
203-1
202-5
02
01
00
0
0
0
0
0
0
2
1
0
0
0
0
102-5
02
01
00
0
0
0
0
0
0
2
1
0
0
0
0
0
0
-
102-3
103-1
0
0
o
0
03
02
01
00
gg
1 2
241-0
24
23
02
01
00
0
0
2
0
0
0
16
15
14
02
01
00
102-4
1
0
0
0
0
0
0
2
1
141-0
114-2
-
202-2
102-2
203-0
103-0
0
o
o
0
41
40
0
0
0
39
0
03
02
01
00
o
o
o
0
1
2
0
0
Figure 6. Connector Pin Numbering
A net is defined as an electrical connection between two or more points in a circuit. Ordinarily, a net has an originating end
(usually an output where the signal is generated) and one or more terminating ends. Often it is convenient to assign
descriptive mnemonic names to nets as a way of identifying them on schematics. Whether a net is named or not is
sometimys arbitrary. However, a net is always assigned a name if:
1. The net is contained on one drawing sheet but is not shown as a complete solid line on that sheet.
2. Part of the net appears on more than one sheet.
3. Part of the net connects with a different schematic.
4. Part of the net leaves a logic board.
If a net is named, the following rules are observed_
1. All mnemonic names are a maximum of six characters.
2. All decimal digits and upper case letters are permitted.
3. No other characters permitted.
4. Where possible, Mnemonics are descriptive. However, it should be recognized that descriptive names are not always
possible and a danger of misinterpreting a Mnemonic exists.
5. Mnemonic names are not repeated within a schematic.
6. Every Mnemonic is suffixed by a state indicator. This indicator consists of the digit" 1" for the logically true state,
or the digit "0" for the logically false state. For example, the set side of a flip-flop would have the "1" state
indicator, while the reset side would have the "0" state indicator. The state indicator for a function changes each
time that function is inverted. Thus, the state indicator permits assigning the same Mnemonic to functions that are
identical except for an inversion.
7 _ When a logical function is inverted, an inversion indicator is added after the state indicator. This allows for
functionally equivalent, but electrically different nets to have the same Mnemonic name. For example, assume a
signal NAME I, NAME 1 may be inverted to produce NAMEO. If NAMEO is then inverted, NAME 1A is produced_
NAME 1 and NAME 1A are functionally equivalent, but physically different nets.
29-394A12 ROO 12/74
11
Sometimes a net fans-out to many sheets in a schematic. It is also possible for a net to fan-out to sheets in
different schematics. In these situations, the net is assigned a mnemonic name. The net is also "zoned" from sheet
to sheet to allow for properly identifying the originating and terminating ends of the net. The originating end of a
net is defined as the collector at which a signal is generated. All other points to which the net connects are called
terminating ends. When a lead leaves a sheet at the originating end, it is zoned to each and every sheet on which
the net reappears, by indicating first the page number, followed by the schematic number that contains the page.
For example, assume that the gate shown on Figure 3 is on a schematic, Sheet 20. The output NAMEO, appears
on Sheets 10, 12 and 18 of the schematic. Note that the schematic number is implied. When a net enters a sheet
from another sheet, it is labeled, with the same Mnemonic name, and is zoned back to the originating end of the
net only. Thus, on Figure 3, the ENBLI may, however, have many other terminations in addition to the one
shown. Generally, then, when a net leaves the sheet where it originates, it is zoned to every other sheet where the
net terminates, while the terminating end is zoned only to the originating sheet. Note that in the Model 8/32
schematics, signals are co-ordinated between sheets only when the sheets are related to the same board. When a
signal leaves a board, the Back Panel Map must be used.
When a lead leaves a logic board, it usually does so through a logic board back panel connector pin. These
connector pins must be shown on the schematic even if the complete net is shown on one drawing sheet. Only the
connector pin number need be indicated under the pin symbol, since the connector number itself is implied by the
logic board location number in the logic symbol or in the footnote. Thus, on Figure 3, RD061 enters the logic
board on Pin 114 of Header Connector O.
Figure 7 is a typical schematic sheet with call-outs illustrating many of the conventions described in this section.
The schematic drawings for the basic Digital System and some of the more common expansions are commonly
included in the rear of the appropriate Digital System Maintenance Manual. Schematic drawings for other
expansions are included with the expansion or with the publications that describe the expansion.
12
29-394A12 ROO 12/74
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APPENDIX 1
PART NUMBER CROSS REFERENCE LIST
PERKIN-ELMER
PART NO.
19-001
19-002
19-003
19-004
19-005
19-006
19-007
19-008
19-009
19-010
19-012
19-013
19-014
19-015
19-016
19-017
19-018
19-019
19-020
19-021
19-022
19-023
19-024
19-025
19-026
19-027
19-028
19-029
19-030
19-031
19-032
19-033
19-034
19-035
19-036
19-037
19-038
19-039
19-040
19-041
19-042
19-043
19-044
19-045
19-046
19-047
TYPE
VENDOR/JEDEC
NUMBER
---
Dual 4 Input NAND DTL
Triple 3 Input NAND DTL
Quad 2 Input NAND DTL
Hex 1 Input NAND DTL
Dual Power Gate DTL
Dual Buffer DTL
Flip-Flop DTL
Gate Expander Dual 4 Input DTL
8 Bit Stack DTL
Differential Comparator LIN
Dual 4 Input NAND Buffer TTL
Quad 2 Input NAND DTL
Dual J-K Flip-Flop DTL
Hex Inverter I Input
Quad 2 Input NAND TTL
Triple 3 Input NAND TTL
Dual 4 Input NAND TTL
Single 8 Input NAND TTL
Operational Amplifier LIN
Quad 2 Input Power DTL
Dual J-K Flip-Flop TTL
Selected Dual Buffer 19-006 with
20-30 nanosecond delay DTL
Triple 3 Input AND TTL
Dual 4 Input AND TTL
2-2-2-3 Input AND/OR TTL
4 Bit Adder TTL
4 Bit Serial Adder TTL
Quad Exclusive - OR TTL
4 Bit Shift Register TTL
One Shot TTL
1 of 10 Decoder Open Collector
Dual Sense Amplifier LIN
Retriggerable One Shot TTL
4 Bit Up/Down Counter TTL
Quad 2 Input Open Collector TTL
High Performance Operational Amp
Dual 4 line to 1 line Mux TTL
4 Bit ALU TTL
4 Stage Look Ahead Carry TTL
4 x 4 Register Stack TTL
Dual Retriggerable One Shot TTL
Quad 2 Input NAND Open Collector TTL
Hexadecimal Inverter Open Collector TTL
Dual J-K Flip-Flop TTL
Quad RS-232C Line Driver
Quad RS-232C Line Receiver
861*
863
849
837
844*
832*
848*
833*
930*
710C
74H40
946
855*
74H04
74HOO
74HIO
74H20
9007*
1709*
1644*
3061*
932*
74Hl1
74H21
74H52
7475
7483
7486
7495
74121
74145
7524
74122
74193
7438
748393
74153
74181
74182
74170
74123
74HOI
74H05
74HI06*
MLl488
MC1489A
*Obsolete
29-394A 12 R03 5/78
Al-1
APPENDIX 1
PART NUMBER CROSS REFERENCE LIST (Continued)
PERKIN-ELMER
PART NO.
TYPE
VENDOR/JEDEC
NUMBER
~--
19-048
19-049
19-050
19-051
19-052
19-053
19-054
19-055
19-056
19-057
19-058
19-059
19-060
19-061
19-062
19-063
19-064
19-065
19-066
19-067
19-068
19-069
19-070
19-071
19-072
19-073
19-074
19-075
19-076
19-077
19-078
19-079
19-080
19-081
8 Bit Shifter 24 Pin Dip
1024 Bit PROM TTL
8 Input NAND TTL
1024 Bit PROM TTL
Dual 4 Input Buffer
4 2-line-to-l-line Da ta Sel. Mux
Quad 2 Input NAND STTL
Quad 2 Input NAND STTL
Quad 2 Input NAND Open Collector STTL
Hex 1 Input Inverter STTL
Triple 3 Input NAND STTL
Triple 3 Input AND STTL
Dual 4 Input NAND STTL
Dual 4 Input Buffer STTL
2-2-3-4 Input AND/OR Inverter STTL
Dual D Edge Triggered Flip-Flop STTL
Dual J-K Flip-Flop STTL
Quad 2: I Mux Non-Inverting STTL
Quad 2: I Mux Inverting STTL
4 Bit ALU STTL
4 Stage Carry Look Ahead Carry STTL
8 line to 1 line Mux STTL
4 Bit Synchronous Counter TTL
Quad D Edge Triggered Flip-Flop
4 Bit Left/Right Shift Register TTL
Dual 4: 1 Mux TIi-State TTL
8 Bit Priority Encoder TTL
16 x 4 Register Stack TTL
1024 Bit Memory MOS
256 Bit Memory TTL
Dual 4 Input NAND Open Collector
Comparator Dual
1024 Bit PROM TTL
Univ. Asynchronous Receiver/Transmitters
19-082
19-083
19-085
19-086
19-087
19-088
19-089
19-090
19-091
19-092
19-093
19-094
19-095
19-096
2-2-3-4 Input AND/OR Invert Open Collector STTL
9 Bit Parity Generator/Checker STTL
Timer
741 C DIP Operational Amplifier
747 DIP Operational Amplifier
733 C DIP Operational Amplifier
Dual D Edge Triggered Flip-Flop
High Speed (710) Differential Comparator DIP
Retriggerable Single One Shot
Negative Voltage Regulator
Positive Voltage Regulator
Positive Voltage Regulator
Linear Positive Voltage Regulator
First In-First Out Serial Memory 64 Word 4 Bit
74198
DM8587
74H30
74187
*832
74157/9322
7400
74S00
74S03
74S04
74SI0
74S11
74S20
74S40
74S64
74S74
74S112
74S157
74S158
74S181
74S182
74S151
74161
74175
74194
8214(NAT)
9318(F)
3101(1NT)
TM54062
6531(MON)
74S22
NE521
82S29(SIG)
TR 1042A(Western
Digital)
74S65
82S62(SIG)
MC1555
741
747
733
74H74
710
9600
1463
1469
723
805
3341
*Obsolete
AI-2
29-394A12 R03 5/78
APPENDIX 1
PART NUMBER CROSS REFERENCE LIST (Continued)
PERKIN-ELMER
PART NO.
19-097
19-098
19-099
19-100
19-101
19-102
19-103
19-104
19-105
19-106
19-107
19-108
19-109
19-110
19-111
19-112
19-113
19-114
19-115
19-116
19-117
19-118
19-119
19-120
19-121
19-122
19-123
19-124
19-125
19-126
19-127
19-128
19-129
19-130
19-131
19-132
19-133
19-134
19·135
19-136
19-137
19-138
19-139
19-140
19-141
19-142
19-143
19-144
19-145
19-145FOI
19-145F02
TYPE
Amplifier
Quad 2: 1 Multiplexor Non-Inverting
Dual Sense Amplifier Inverting
Dual Driver 8 Pin DIP
Quad-2 Input Positive NAND Buffer
6-1 Input Buffer/Buffer Open Collector
1 of 10 Decoder
Current Switch Memory Driver
Dual Differential Driver
Dual Differential Receiver
Dual Sense Amplifier
Quad 2 Input NAND
Hex Inverter Buffer Driver Open Collector
Hex Inverter
Dual 4 Input NAND Buffer
Optically Coupled Isolator
360 Dual Line Driver
360 Triple Line Receiver
Quad 2 Input AND TTL
Dual 4: 1 Multiplexor STTL
4 Bit Magnitude Comparator STTL
Quad Bus Transceiver TTL
Expandable AND/OR Invert TTL
Dual Timer
Matched Pair 19-085 (P.S. Timing)
1024 Bit PROM TTL
Dual Voltage Controlled Oscillator
4-2 Input NAND Buffer STTL
4-2 Input NAND Buffer STTL
Dual 2 Wide 2 Input AND/OR Inverter STTL
4-2 Input Exclusive OR STTL
13 Input NAND, 3-State STTL
3/8 Decoder STTL
2-4 Input NAND 50 Ohm Line Driver STTL
4D FF STTL
4 2/1 Mux STTL
4 Bit Binary Full Adder TTL
Hexadecimal Buffer/Inverter TTL
4 Bit Binary Counter STTL
1 of 10 Decoder HS & HV
Dual Peripheral Positive OR Driver 8 Pin DIP
Character General
Driver /Decoder
8 Bit Latch
Multi-Port Register
1024 Bit PROM TTL
4K x I NMOS RAM
4-Hystersic Rec
Voltage Regulator + 15 500 Milliamperes
Voltage Regulator + 12 500 Milliamperes
Voltage Regulator -15 500 Milliamperes
VENDOR/JEDEC
NUMBER
(RES)
74157
75234
75452
7437
7407
7442
75325
75114/9614
75115/9615
7520
7400
7406
7404
7440
4N25
75123
75124
74H08
74S153
74S85
26S12A
74H55
NE556
MC1555*
SEE 19-051
74S124
74S37
74S38
74S51
74S86
74S134
74S138
74S140
74S175
74S258
74283
8T98
(98516)
74145
75453 (SIG)
2513
7447AN
9334PCQM
9338PCQM
SEE 19-080
9050
8T380
78M15AUC
78M12AUC
LM340T-15
*Obsolete
29-394A12 R03 5/78
AI-3
APPENDIX I
PART NUMBER CROSS REFERENCE LIST(Continued)
PERKIN-ELMER
PART NO.
AI-4
VENDOR/JEDEC
NUMBER
TYPE
19-146FOO
19-146FOl
19-146F02
19-146F03
19-147FOI
19-147F02
Voltage Regulator -15 500
Voltage Regulator -12 500
Voltage Regulator -5 500
Voltage Regulator -5 500
8 Channel Analog Mux
8 Channel Analog Mux
Milliamperes
Milliamperes
Milliamperes
Milliamperes
19-148
19-149
19-150
19-151
19-152
19-153
19-154
19-155
19-156
19-157
19-158
19-159
19-160
19-161
19-162
19-163
19-164
19-165
19-166
19-167
19-168
19-169
19-170
19-171
19-172
19-173
19-174
19-175
19-176
19-177
19-178
19-179
19-180
19-181
19-182
19-183
19-184
19-185
19-186
19-187
19-188
19-189
19-190
19-191
Voltage Follower
High Speed Op Amp
2 Channel Analog Switch
Low Level Inst Amp
Linear Amp
4-2 Input NAND LPTTL
Hex Inverter LPTTL
3-3 Input NAND LPTTL
2-4 Input NAND LPTTL
8 Input NAND LPTTL
4-2 Input NOR LPTTL
4-2 Input OR LPTTL
4-2 Input AND LPTTL
3-3 Input AND LPTTL
2-4 Input AND LPTTL
4-2 Input NAND Schmitt Trigger LPTTL
4-2 Input NAND Buffer LPTTL
2-D FF LPTTL
2-JK FF LPTTL
4-D FF LPTTL
3 to 8 Decoder Demux LPTTL
Hex Inverter Open Collector LPTTL
4-2 Input NAND Open Collector LPTTL
Dual Multivibrator
4-2 Input Exclusive OR LPTTL
8 to 1 AND/OR Invert Mux LPTTL
4-2 Input AND/OR Mux LPTTL
4-2 Input AND/OR Mux LPTTL
4-2 Input Mux LPTTL
4-1 Input AND/OR Mux LPTTL
3-3-2-2 Wide AND/OR Inverter LPTTL
4-3-3-2 AND/OR Inverter LPTTL
4 Bit Counter LPTTL
4 Bit Up/Down Counter LPTTL
4 Bit Left/Right Shift Register TTL
2-Line Driver
4 Bit Micro Controller
4K-Bit ROM
4K-Bit PROM
Quad 2: 1 Mux with Storage LPTTL
ROM Chip Programmed In House 16 Bit LSU
ROM Chip Programmed In House 32 Bit LSU
Quad Comparator
Quad 2-lnput NOR Gate
79MI5/LM320T-15
79MI2/LM320T-15
79M05
7905 /LM3 20T-5
HI1-181A-5
Analog Devices
A07503JN
LM310D
HA2-2525-5
DG1828A
AD52lJD
BB3660J
74LSOO
74LS04
74LSI0
74LS20
74LS30
74LS02
74LS32
74LS08
74LSli
74LS21
74LS132
74LS37A
74LS74
74LS112
74LS175
74LS138
74LS05
74LS03
74LS123
74LS86
74LS 151
74LS257
74LS157
74LS258
74LS153
74LS51A
74LS54
74LS161
74LS193
74LS194
75110
AMD2901
N82S115
82S215N
74LS298
LM339
CD4001AE
29-394A12 R03 5/78
APPENDIX 1
PART NUMBER CROSS REFERENCE LIST (Continued)
PERKIN-ELMER
PART NO.
TYPE
19-192
19-193
19-194
19-195
19-196
19-197
19-198
19-199F03
19-200
19-201
19-202
19-203
19-204
19-205
19-206
19-207
19-208
19-210
19-213FOI
F02
20-001
20-002
20-003
20-004
20-005
20-006
20-007
20-008
20-009
20-010
Dual D Flip Flop
1024 Bit PROM TTL
2K PROM TTL
2K PROM TTL
Quad 2 Input 3 State Mux. Non Inverting
1024 B Dynamic RAM (NMOS)
Field Programmable Logic Array
Field Programmable Logic Array
16 x 4 First In-First Out (FIFO)
CPU
Peripheral Interface Adapter (PIA)
Sync Serial Data Adapter (SSDA)
lK RAM
2 Phase Clock
4 Input 3 State Line Transceiver
Error Checking, Polynomial Gen.
Dual VCO
CPU
5/16 Shift Control PLA
8/16E Shift Control PLA
Transistor NPN High Speed Switch
Transistor PNP 500 MA
Transistor
Transistor NPN
Transistor
Transistor NPN 15 Amps 100W T03 case
Transistor NPN 3 Amps
Transistor PNP 3 Amps
Transistor Triac 2 Amps 100V
Transistor NPN 500 MA Code Driver
20-011
20-012
20-013
20-014
20-015
20-016
20-017
20-018
20-019
20-020
20-021
20-022
20-023
20-024
20-025
20-026
20-027
20-029
20-030
20-031
Transistor Photo
Transistor PNP High Current Switch
Transistor NPN
Transistor NPN
Transistor PNP
Transistor PNP
Transistor NPN
Transistor, Power Silicon NPN
Transistor
Transistor Switching 1 Amp T05 can
Transistor NPN Silicon
Transistor NPN
Transistor PNP
Transistor Switch
PNP Hi Speed Switch
Transistor Module, Quad
Transistor
Transistor
Transistor
Transistor
29-394A12 R03 5/78
VENDOR/JEDEC
NUMBER
------CD40l3AE
SEE 19-051
N825131
SEE 19-051
74S257
MK4096N-16
82S00
9430
MC6800
MC6820
MC6852
MCM6810A
MC6870A
8T26/8T26A
MC8506P
MC4024P
2608-1/MCM6830P
2N3646
MPS6534
DT5-423/2N3902
2N5189/64493
2N3056
2N3055
TIP31A
TIP32A
A03001
2N5845/2N5845/
74659A
2N5777
2N2907/TS3413
2N3302
2N4238
2N4235
2N3740
2N3766
2N3054
2N6038
2N3725
MPS3646
2NJ 711
2N905A/J2N2905A
2N3776
2N3467
FSQ 1079 /FPQ3 724
2N2369
HPX002
2N3568
Al-5
APPENDIX 1
PART NUMBER CROSS REFERENCE LIST (Continued)
PERKIN-ELMER
PART NO.
Al-6
TYPE
VENDOR/JEDEC
NUMBER
SEE 2N6486 SPEC
KE4393
2N3904
2N3906
MP54356
D45H2
2N2520
2N222A
20-032
10-033
20-034
20-035
20-036
20-037
20-038
20-039
20-043
21-025FOI
Transistor NPN
Transistor
Transistor
Transistor
Transistor
Transistor
Transistor
Transistor
MaS FET
1K ohm-IS to Common DIP
21-025F02
470 ohm-IS to Common DIP
21-025F03
330 ohm-IS to Common DIP
23-001
23-002
23-003
23-004
23-007
23-008
23-009
23-010
23-011
23-012
23-013
23-014
23-015
23-016
23-017
23-0t8
23-019
23-020
23-021
23-022
23-023
23-024
23-025
23-026
23-027
23-028
23-029
23-030
23-031
23-032
23-033
23-034ROI
Diode High Speed-High Current
Diode 5. I V Zener
Diode IOV Zener
Diode 6.1 V Zener
Diode Mot Bridge
Diode Int. Redifier
Diode
Diode Int. Rectifier
Diode Rectifier
Diode Termistor
Diode 9.3V
Diode
Diode
Diode Bridge Rectifier
Diode
Diode 18 V Zener
Diode
Diode 8.2V Zener
Diode 9.1 V Zener
Diode 3.3V Zener
Diode Bridge Rectifier
Diode, Power Fast Rec. 30 Amps
Diode, Power Fast Rec. 3 Amps
Triac 600V 30 Amps
Diac 32V
Power SCR Thyristor
Diode
Diode
Diode 6.8 V Zener
Diode 9.1 V Zener
16 Diode Array
Switch Diode 600 ma
8981-1Kohm
(Beckman)
898-1-470 ohm
(Beckman)
898-1-330 ohm
(Beckman)
IN4150
IN4733A
IN4750A
IN4735A
MDA962-2
40HF-5R
IN4735
Sl YIP
2N681
ID2032
IN2163
IN3880
IN3889
YS448
IN2070
IN4746
IN36I5
IN756A
IN757A
IN746A
KDH250
IN3909
MR841/AI15A
2N6I62
IN576I
2N4441
IN4607
IN4I56A
IN4736A
IN4739
45190 (Litton)
TSCIN4607
23-035
23-036
23-037
23-041 FOO
Diode 40A
Diode
Zener Diode 2.4 V
Low Voltage Zener Diode
MBA4030
MPD-400
IN4370
LVA51A40114/
29-394AI2 R03 5/78
APPENDIX 1
PART NUMBER CROSS REFERENCE LIST (Continued)
VENDOR/JEDEC
NUMBER
PERKIN-ELMER
PART NO.
23-041F02
Low Voltage Zener Diode
23-042
23-043FOO
23-043FOI
23-043F02
30-013
30-013F02
30-013F03
30~Ot 8
Power Schottky
Zener Diode Avalanche 5.1 V
Zener Diode Avalanche S.6V
Zener Diode Avalanche 6.2V
4.7uH Inductor
1.5uH Inductor
2.2 uH Inductor
100 nan oseconds Delay Line 10 taps
30-019
50 nanoseconds Delay line 10 taps
33-032
Hexadecimal Switch
29-394A12 R03 5/78
LVA51 A2281 9
LVA62A22941/
LVA62A40212
SD41
30-018
(Princeton
Advanced Eng.)
30-018
(Princeton
Advanced Eng.)
Al~7 /AI-8
PROCESSOR
01-078R09A21
December 1978
METRIC
MODELS 8/32, 8/32C,AND 8/320
PROCESSORS
MAINTENANCE SPECIFICATION
TABLE OF CONTENTS
1. INTRODUCTION
1.1
1.2
1.3
1.4
Packaging
Processor .
Control Store
Peripherals . .
2. INTERNAL ARCHITECTURE
2. 1
2.2
2.3
2.4
2.5
Modules . . . . .
Micro-Instructions
Interrupts
Registers . . . .
Processor Timing
3. FUNCTIONAL DESCRIPTION OF THE BASIC PROCESSOR
3. 1
3.2
3.3
3.4
3.5
3.6
Processor Busses
Registers . . . .
Interrupts
Control Store Memory
Micro-Program ming
Processor Block Diagram Analysis
4. CPA GENERAL DESCRIPTION . . .
4.1
4.2
4.3
4.4
4.5
CPA Block Diagram Description
Memory Addressing . . . . .
Memory Reference Operations
S Bus Operations
B Bus Operations . . . . . . .
5. CPB FUNCTIONAL DESCRIPTION
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
State Counter and Control
Clock and Control
Control Store
Bus Selection
Interrupts
PSW Register
Branch Control
A, B, and S Gating
Test Aids
01-078A21 R09 12/78
2
2
2
2
2
3
3
5
5
5
6
15
19
19
21
26
36
37
38
38
39
40
41
42
43
43
43
43
I
TABLE OF CONTENTS
(Continued)
6. CPC GENERAL DESCRIPTION . . . .
44
A and B Stacks (ASTK and BSTK)
S Buffer (SBUFF)
Stack Addressing .
Read/Write Control
45
45
45
48
6.1
6.2
6.3
6.4
48
7. ALU
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Arithmetic State Register (AS)
ALU Flow Charts and Algorithms .
ALU Clock
Arithmetic Iterative Counter (ACNTOI :05)
Arithmetic Condition Code
Arithmetic Elements and ROM Control
MQ Register
AL Register and Shift Multiplexors
8. I/O GENERAL DESCRIPTION
:::rC?~.
9. FUNCTIONAL DESCRIPTION
9.1
9.2
I/O Control Functions .
Machine Malfunction and Power Fail Hardware
10. MULTIPLEXOR CHANNEL (MUX) BUS
10.1
10.2
10.3
Multiplexor Channel IOU . . . . .
Multiplexor Channel Timing . . .
Multiplexor Channel and Multiplexor Operations (MUX)
11. BYTE MANIPULATION AND AUXILIARY FUNCTIONS
11.1
11.2
Byte Manipulation Functions
Auxiliary Functions
i 2. DISPLAY CONTROLLER.
12.1
12.2
12.3
12.4
12.5
Addressing Logic
Data Output
Data Input
Status Input
Control Logic
13. TELETYPE CONTROLLER
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13 .8
13.9
13.10
13.11
13.12
13.13
ii
Block Diagram Analysis
Bus Communication and Address Circuits
Status and Commands
Timer Circuits
Data Output
Data Input . . .
Interrupt Circuit
Ini tializa ti on ..
TTY Timer Adjustment
Machine Control Register (MCR)
Power Monitor and System Initialize
Primary Power Fail Check
Start Timer . . . . . . . . . . . . .
50
50
63
64
64
64
65
66
. . . . . . . . . . . . . . . 66
66
66
69
69
69
.71
74
80
80
83
84
84
84
84
84
84
84
85
85
85
86
86
88
90
90
90
90
90
92
92
01-078A21 R08 11/78
TABLE OF CONTENTS
(Continued)
.93
14. SAND D BUS ROM CONTROLLERS . . . .
14.1
14.2
14.3
S Bus High ROM Controller (19-142F45)
S Bus Low ROM Controller (19-142F46)
D Bus ROM Controller (19-142F47) . . .
·93
.94
.95
IS.
EXTENDER BOARD OPERATION
96
16.
MNEMONICS . . . . . . . . . . . .
97
16.1 CPA Mnemonics, Schematic Drawing 35-536D08
16.2 CPB Mnemonics, Schematic Drawing 35-53 7D08
16.3 CPC Mnemonics, Schematic Drawing 35-555D08
16.4 ALU Mnemonics, Schematic Drawing 35-538D08
16.5 IOU Mnemonics, Schematic Drawing 35-539D08
APPENDIX 1. MODULE 3 OPERATIONS . . . . .
97
100
104
105
109
.Al-l
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure SA.
Figure 5B.
Figure 5C.
Figure 6
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figufl;! 11.
Figure 12.
Figure 13A.
Figure 13B.
Figure 14.
Figure 15.
Figure 16A.
Figure] 6B.
Figure 17.
Figure 18.
Figun~ 19.
Figur1i! 20.
Figure 21.
Figun~ 22.
Figur,e 23.
Figure 24.
Figure 25.
Figme 26.
Figme 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure A-I.
Model 8/32 Module Concept
Control and Module Instructions
CPU (CPA, CPB, and CPC) Block Diagram
CP A Block Diagram . . . . . . . . . . . .
Instruction Read, RR or SF Formats . . .
Instruction Read RXI, RX2 or RI I Formats
Instruction Read RX3 or RI2 Formats
Second Ha1fword Clock Timing
Data Read Operation
Data Write Operations
CD Bus Interface
CPU State Diagram
Simplified Clock Circuit
Simplified Control Store Diagram
Control Store Address Gating Low (CSA10:15)
Control Store Address Gating High (CSA4:9)
CPC Block Diagram . . . . . . . . . .
A Stack Timing Diagram, 32-Bit Write
SBUFF Timing, 32-Bit Write
SBUFF Timing, 64-Bit Write
Stack Addressing Scheme ..
ALU Functional Block Diagram
ALU State Transitions . . . .
ALU Bus Timing -- Immediate Response Functions (FSELOOO)
IOU Block Diagram . . . . . . . . . . . . . . . . . . .
Multiplexor Channel Timing . . . . . . . . . . . . . . . . .
Multiplexor Cllannel (Input) Timing ADRS and SR/DR
Multiplexor Cllannel (Output) Timing ADRS and CMD/DA
Multiplexor Circuit Gener~tion Descripilon
Cycle Counter . . . . . . . . . . . . . . . . . . . . .
Multiplexor Channel Timing, ACK . . . . . . . . . .
D Bus ROM Controller Data Gating for WD and WDA
ROM Controller Data Gating for RDH and RDHA
Serial ASCII Code U (Even Parity)
Teletype Controller Block Diagram ..
Write Mode (Output) Timing, Teletype
Read Mode (Input) Timing, Teletype .
ALU State Transitions, Including Module 3
01-078A21 R08 11/78
· 3
· 6
· 17
·20
· 29
· 30
· 31
· 32
· 33
·34
35
38
39
41
42
42
.44
·46
.46
·46
.47
·49
50
51
68
71
72
73
75
.77
· 79
· 82
83
· 84
· 87
·88
.89
. A1-1
iii
TABLE OF CONTENTS
(Continued)
TABLES
TABLE 1.
TABLE 2.
TABLE 3.
TABLE 4.
TABLE 5.
TABLE 6.
TABLE 7.
TABLE 8.
TABLE 9.
TABLE 10.
TABLE 11.
TABLE 12.
TABLE 13.
TABLE 14.
TABLE 15.
TABLE 16.
TABLE 17.
TABLE 18.
TABLE 19.
TABLE 20.
TABLE 2l.
TABLE 22.
TABLE A-I.
TABLE A-2.
TABLE A-3.
iv
FUNCTION CODES FOR CPU INSTRUCTIONS
MC FIELD . . . . . . . . . . . . . . .
INTERRUPT TRAPS . . . . . . . . .
EXTERNAL INTERRUPT ENABLE .
REGISTER ADDRESSING . . . . . .
MODULE 1 OPERATION . . . . . . . . . . . . . . . . . . . . . ..
I/O CONTROL FUNCTIONS . . . . . . . .
STARTING LOCATION JUMPERS . . . . . .
·
MEMORY ACCESS INTERRUPT SIGNALS
·
MEMORY ACCESS INTERRUPTS
MICRO COMMANDS . . . . . . . . . . . .
·
INCREMENT MICRO-COMMANDS . . . . .
·
BUS SELECT DECODING. . . . . . . . . .
.
CONTROL STATE LOGIC IMPLEMENTATION
.
ALU FUNCTION CODES .. .
.
STATE REGISTER LOGIC ..
ALU ROM CONTROL . . . . .
.
FUNCTION MNEMONICS . . .
.
I/O MODULE FUNCTION GATING .,
.
STB INSTRUCTIONS . . . . . . . . . .
.
TELETYPE STATUS AND COMMAND BYTE
.
.
MCR BIT ASSIGNMENT . . . . . . . . . . .
MODULE 3 (FLOATING POINT OPERATION) . . . .
. . . . ..
. .......
STATE REGISTER LOGIC, INCLUDING MODULE 3. . ..
. ...................
ALU ROM CONTROL FOR FLOATING POINT . . . . . . . . . . . . . . . . . . . . . . . . . . ' . .
01-078A21 R06 5/78
7
9
10
10
11
12
16
23
25
26
26
36
37
39
49
51
65
67
81
81
85
91
AI-2
AI-3
AI-IO
MOOELS8/32, 8/32C, AND 8/320
PROCESSORS
MAINTENANCE SPECIFICATION
1.
INTRODUCTION
The Perkin-Elmer M83-Series 8/32 Digital Systems are low cost, general purpose systems, versatile enough to perform a
wide range of industrial control, data processing, and scientific computation. The processors are well suited to the realtime scanning of hundreds of instrument readings, process alarms, and pulse trains. They are particularly useful where
larger amounts of main Processor time are needed for computation.
1.1
Packaging
Each 8/32 Processor is contained in a 483 mm X 356 mm (19" X 14") RETMA Twin Chassis allowing 16 board positions.
The basic Processor with 128KB of core memory in the 8/32 and 8/32C or 256KB of core memory in the 8/320 uses 12 board
positions and allows four positions for I/O expansion or planned Processor options.
1.2 Processor
The current basic Processor configurations are Model 8/32C with a basic 128KB memory and Model 8/320 with a basic 256KB
memory (Product Number M83-030). Other features such as parity, additional memory, etc. are optional. All references to
Model 8/32 in this specification apply to the 8/32, 8/32C, and 8/320 models unless otherwise specified.
The Model 8/32 uses a technique commonly referred to as "emulation" to impicment the standard Perkin-Elmer user repertoire. This technique requires a micro-processor, or sub-processor, not apparent to the user, employing one or more of
the micro-instructions in sequence to implement one user level instruction. The basic micro-program is contained in 1,280
words of Read-Only-Memory (ROM). The Model 8/32 employs a 32 bit micro-instruction word and 32 bit internal bussing. The basic instruction time of the micro-processor is 260 nanoseconds per micro-instruction.
1.3 Control Store
The Model 8/32 uses 1,280 words of control store which is mounted on the ePB board. The control store may be optionally
expanded by a 512 word and/or a 2,048 (2K) word Writable Control Store (WeS). Three user instructions are used for manipulating the WCS.
1.4 Peripherals
The Model 8/32 interfaces to, and is compatible with, all standard Perkin-Elmer peripheral controllers and controllers designed to the standard Perkin-Elmer Multiplexor Bus. Any number of devices up to 1,023 can be accommodated, but a
maximum of 16 can be interfaced directly to the Multiplexor Bus or the Extended Selector Channel Bus.
2.
INTERNAL ARCHITECTURE
The architecture of the Model 8/32 encompasses a principle of modules communicating over a common bussing system,
directed by instructions from a control memory which specify the module to which an instruction is directed and the
function to be performed. In theory, the function of any module is arbitrary and the significance of various instructions
take meaning only when applied to a specific module. Thus, a computer achieves a capability and personality determined
by what functions can be performed by its complement of modules.
01-078A21 R08 11/78
2.1 Modules
The Model 8/32 architecture accommodates eight modules which communicate over four Processor busses. The basic
Processor is comprised of three modules.
1.
'1
3.
Central Processing Unit (CPA, CPB, and CPC). The CPU contains the Processor registers. This control module
(module 0) controls the user memory, control memory, register gating, and sequencing of instructions.
Arithmetic Logic Unit (ALU). The ALU (module I) provides the basic arithmetic/logical capability of the
Processor.
Input/Output Unit (IOU). The IOU (module 2) provides the I/O capability of the Processor by generating the
standard Perkin-Elmer Multiplexor 0/0) Bus for pelipheral communications. It is capable of various byte
manipulations of data presented on the buses. In addition. the I/O module contains the Display Console
controller, the Teletypewriter controller, the Power monitor and the System Initialize circuits.
The architecture accommodates five additional arbitrary modules such as noating point, Boolean manipulators, or special
nature designs.
2.2 Micro-Instructions
The micro-instruction word is 32-bits long. In addition to the branch and write instructions, there are three types of
instructions to the modules. These minimally encoded instructions provide 112 combinations of module/function commands. The micro-instruction can simultaneollsly direct two operands and a result independently on three of the
computer's busses; generate 12-bit immediate field operands; select the address of the next micro-instruction; perform
encoded micro control of the computer's functions such as reading/writing main memory; incrementing user location and
memory address registers; controlling the user status register; and decoding the next user instruction.
2.3 Interrupts
The Model 8/32 has nine hardware ptiority interrupts. most of which can be masked by various bits of the Program Status
Word (PSW). The occurrence of a recognized interrupt causes the micro-program to trap to one of nine specific control
store locations associated with the interrupts. Among the nine interrupts are four priority levels of external interrupt all of
which are always available. Though available, the last three external interrupt priority levels are practical only if additional
optional register sets are installed.
2.4 Registers
The Model 8/32 can have up to 8 sets of 16 general registers each. Fifteen registers in each set may be used as index registers. In addition, there are 16 floating point registers, 8 additional general purpose registers, plus 5 registers associated with
the user level machine control that are available to the micro-programmer.
2.5 Processor Timing
Communications between modules are request/response. Timing is completely asynchronous (rather than quantized) to
achieve maximum speeds. In addition, interlocks are provided between the control memories and the CPU to facilitate
programming the micro machine. The control module operates on a 130 nanosecond clock, allowing a minimum instruction execution in 260 nanoseconds. Internal timing within the other modules can be selected to best suit the needs of the
module.
2
01-078A21 R08 11/78
3.
FUNCfIONAL DESCRIPTION OF THE BASIC PROCESSOR
3.1 Processor Busses
The functional characteristics of the Processor can best be described in terms of its registers, busses and related gating.
There are four busses which are the key to the modular design philosophy of the Model 8/32 architecture. Refer to Figure
1. An understanding of the bus structure is necessary to determine how each module of the Processor interrelates, and how
the registers and gating of each module contribute to the function of the module it is designed to serve.
3.1.1 Control Bus (C Bus). The Control Bus of the computer is commanded by the control module and is, in
essence, a reflection of that segment of the micro-instruction selecting the function and module to be addressed, plus timing
to affect data transfers. Also included is a means (the CC Bus) for a module to transfer data to the Condition Code of the
PSW. The Control Bus signals are described in the following paragraphs:
I
I
Module Select Lines (MSELOO:02). These three lines contain the address of a module for which the current
micro-instruction is intended. One of the eight arbitrary modules can be selected by the instruction to perform
some function. These three lines reflect Bits 0:2 of the micro-instruction.
Function Select Lines (FSELOO:03). These four lines reflect Bits 16:19 of the micro-instruction and normally
select I of 16 arbitrary functions to be performed by the selected module.
Start (STRT). STRT signals the modules that data on the bU'sses is valid. It is, in effect, a request from the
control module for a response to a micro-instruction. Data is held static on the A and B Busses while STRT is
active. The control module holds STRT active until it recognizes a response on the Module Finished (MFIN) line
and has stored the results presented on the S Bus.
S BUS
I
I
USER:
MEMOBY
Ir
"
rl
"
REGISTERS
CONTROL
STORE
t
"
_..
JI
II
1
ALU
MODULE
IJ
-,
ARBITRARY
MODULE
JI
It
~
MUX
IOU
MODULE
PERIPHERALS
BUS
CPU
..
A BUS
B BUS
---
,
-
CO'NTROL BUS
Figure 1. Model 8/32 Module Concept
01-078A21 R06 5/78
I
C13U5
3
Module Finished (MFIN). MFIN is a response to the control module from a selected module indicating that it
has recognized STRT and completed the selected function. The selected module gates data and other responses
onto the S Bus prior to returning MFIN. The data and responses must be held on the busses until the control
module removes STRT. This time is indefinite and depends on events within the control module.
Module Signal (MSIG). This is a control signal manipulated by the selected module to indicate some arbitrary
condition to the control module. It may be tested by the control module during a normal micro-instruction to
the selected device, to control a conditional branch in the micro-program.
Condition Code Bus (SCC, vcc, CCC, GCC, and LCC). SCC signals the control module that the selected module
wishes to manipulate the Condition Code of the Program Status Word. If the micro-programmer has enabled this
manipulation, the Condition Code is forced to a status specified by the selected module. The status is unconditionally forced into the CPU flags. This is done concurrent with a normal instruction to the selected module.
VCC, CCC, GCC, and LCC specify the status forced into CPU flags and the Condition Code of the Program
Status Word, and represent overflow, carry, greater than, and less than. respectively.
3.1.2. A, B, and S Busses. The A, B, and S Busses arc the primary data links between the control module and
the selected module. Gating of data to/from each of these busses is controlled by the micro-instruction. Most of the
registers of the control module can be gatcd to/from these busses.
Data is selected by the micro-instruction from two independent sources and transmitted to a selected module over the A
and B Busses. The module is thus presented simultaneously with two operands. The resulting data is returned to the
control module via the S Bus. The destination of the S Bus is selected by the micro-instruction.
3.1.3 Typical Bus Exchange. The use of the A, B, and S Busses can be summarized by the following example.
I
1.
The mkro-instruction selects a module (MSELOO:02) al'd directs it to perform some function
(FSELOO:03).
2.
The operands are selected from somewhere in the control module and gated onto the A and B Busses.
3.
The control module informs the selected module that all data on the busses is valid and that it may
begin (STRT).
4.
The selected module performs the function (S)
5.
The selected module may manipulate the Condition Code via SCC, VCC, GCC, LCC, and CCc.
6.
The selected module activates MFIN to signal the CPU module that the operation is complete and the
results are presented on the S Bus.
7.
The control module recognizes MFIN, gates the S Bus to the destination specified by the microinstruction, and then removes STRT.
8.
The selected module deactivates itself when STRT is removed.
= (A) F (B) and gates the results to the S Bus.
I
I
4
OI-078A21 R06 5/78
3.2 Registers
"Ole following registers are part of the control module.
3.2.1 A Stack/B Stack. The A stack and B stack are redundant sets of register banks containing the general
purpose registers of the CPU. The registers are duplicated to allow simultaneous gating of any register in the stack onto
either the A Bus or the B Bus. These registers are gated onto the A and B Busses and are loaded from the S Bus under
control of the micro-instruction.
3.2.2 Memory Data Register (MDR). This register provides the data buffer between the CPU and the user level
memory. The MDR can be gated onto the B Bus and loaded from the S Bus under control of the micro-instruction. It is, of
course, also loaded under control of the memory when a memory read cycle is requested. Hardware interlocks are
employed to synchronize the memory to the CPU.
/
3.2.3 Memory Location Register (MLC). The MLC is a general purpose register which can be gated to the B Bus
.
and loaded from the S Bus, and can be incremented by the length of the emulated instruction to facilitate the emulation of
the user level repertoire. This register keeps track of the current instruction location of the emulated machine.
/
3.2.4 Memory Address Register (MAR). This register contains the address of the user memory that the
micro-programmer is reading or writing. The MAR can be loaded from the S Bus under control of the micro-instruction, or
incremented by four under micro-control. The least significant bit of the MAR is used to control byte steering for the
byte-oriented instructions of the user repertoire (refer to I/O Section ). As in the MOR, timing conflicts are resolved by
hardware interlocks.
3.2.5 Program Status Word (PSW). The Program Status Word is an IS-bit register which may he gated onto the
A Bus and loaded from the S Bus under control of the micro-instruction. Various bits of the PSW are used to enahle
associated hardware interrupts. PSW Bits 28:31 contain the Condition Code of the user level computer. These bits may be
compared and tested against corresponding bits of the user instruction under Module a micro-instructions to emulate user
branch instructions. In addition, they can be manipulated by any module designed to do so, if they are enabled by the
micro-program mer.
3.2.6. User Destination Register, User Source R~ister (YD, YS). These two control registers store Bits 08: 11
and 12: 15 respectively, of the current user level instruction being emulated, and allow the micro-programmer to indirectly
reference the general registers selected by the lIser instruction. The YO is compared to the PSW Condition Code on certain
micro-instructions to emulate user level branches. These registers can be examined by gating thcm onto the A and B Busses
under micro-instruction control. The YD can also be loaded from the S Bus.
/.
3.2.7 User Instruction Register (UIR), Memory User Destination Register (UDR), and Memory User Source
Register (USR). These three registers are loaded with Bits 0:7,8:11, and 12:15, respectively, of the next user level
instruction to be emulated. The S-bit op-code stored in the UIR is used to vector to the emulation sequence for the next
user instruction. It is also used to interrogate a ROM which has been configured to decode ~riv~leged and illegal user l~vel /
.instrucltions. The contents of the UDR and USR are transferred to the YD and YS at the begmnmg of the next emUlatIOn/
3.2.8 ROM Location Register (RLR). This register stores the current address of the control store instruction. It
is loaded from the ROM Address Gates (RAG) at the beginning of every instruction except interrupt trap instructions and
execute type instructions (explained in the section on micro-programming). The RLR is a 12-bit register allowing direct
addressing of the control store up to 4K instructions.
3.2.9 ROM Instruction Register (RlR). This 32-bit register stores the current micro-instruction. The RIR is the
focus of control of the CPU.
3.3 Interrupts
The hardware of the computer provides nine priority intcrrupts. Each interrupt has a unique control store trap location
associated with it. Recognition of an interrupt causes the micro-instmction stored at its respective trap location to be
performed. The RLR contents are preserved to allow the address of the interrupted sequence to be saved, if desired, so that
control can be returned at the completion of the interrupt routine. Certain interrupts are enabled/disabled by bits of the
PSW.
3.4 Control Store Memory
The Model 8/32 can accommodate a maximum of 4K x 32 bits of control store memory. The computer allows data as well
as instructions to be retrieved from its control memory. This capability expands its versatility by allowing data such as sine
tables, translation tables, and matrices to be stored and operated upon efficiently by the micro-programmer.
On models so equipped, the Processor can alter its control store (write into its memory). This capability to store and
retrieve data provides the power of a hardware computer at micro-instruction speeds.
01-07SA21 R03 4/77
5
3.5 Micro-programming
I
The control store of the Model 8/32 is a 32-bit word memory which may read indirectly by an instruction to retrieve data,
and may be written into by an instruction if it is a writable memory. The Model 8/32 contains a 1,280 x 32 ROM array containing the user repertoire and support programs.
The basic instruction format provides the computer with a three address capability, but various options of the repertoire
can modify this to range from two to four. Figure 2 displays the different types of instructions and their modifiers.
The format of the micro-instruction specifies which module is to be addressed, allowing only one module of the computer
to be addressed at anyone time. All other modules mllst ignore the communications in process. Bits 0:2 of the instmction
selects the module to which the instruction is addressed.
CONTROL INSTRUCTIONS
ADDRESS LINK: FLAGS ARE TESTED AS PER F AND T, RLC - I S )
I F TEST PASSES: XFER TO ADDRESS.
26 27 28
o
11
14
o
F
S
MC
ADDRESS
REGISTER BRANCH: FLAGS ARE TESTED AS PER F AND T
IF TEST PASSES: XFER TO ADDRESS SPECIFIED BY (B)
o
3 4 5 6
11
14
20
25 26 27 28
Ft:0zU~
MODULE INSTRUCTIONS
RR XFER (A) F (B)-(S)
3
0
IMoDULEI
5 6
00
III
B
IF C = 1 AND MSIG = 1 XFER TO NEXT INSTRUCTION OTHERWISE
XFER TO PAGE ADDRESS ON CURRENT PAGE
11
16
20
25 26
31
S
A
F
Ici
B
PAGE
ADDRESS
RR CONTROL (A) F (B)-(S)
0
3
IMODULEI
5 6
01
III
11
S
I
16
A
RI IMMEDIATE (A) F IMMEDIATE-(S)
0
3
5 6
11
IMODULEI
10
III
S
I
A
I
20
F
16
111
~f{{d
A
B
IKIEIDI
20
F
WRITE INSTRUCTION
R WRITE (A)-RAM ADDRESS SPECIFIED BY (B)
o
3
6
11
16
111
I
25 2627
F
31
MC
I
31
I
IMMEDIATE
20
25 2627
I
31
B
SHOULD BE
NULL SELECTED
A
B
S
F
E
C
D
K
U
T
X
SELECTS REGISTER GATE TO A BUS
SELECTS REGISTER GATED TO B BUS
SELECTS REGISTER TO RECEIVE S BUS
SELECTS FUNCTION OF ADDRESSED MODULE
ENABLE SETTING OF CONDITION CODE
IF SET TRANSFER IS CONDITIONAL
B FIELD IS INDIRECT ADDRESS OF DATA
DECODE NEXT INSTRUCTION
FSEL EXTENSION
UNUSED
TESTED F FIELD FOR THE "TRUE" CONDITION
EXECUTE
MC FIELD DESIGNATIONS (MEMORY CONTROL)
0000
NO MEMORY ACTION
0001
INCREMENT MLC BY INSTRUC. LENGTH
0010
PRIVILEGED WRITE HALFWORD
0011
DATA WRITE HALFWORD
0100
NOT USED
0101
INCREMENT MAR BY 4;WRITE DATA F W
0110
PRIVILEGED WRITE FULLWORD
0111
DATA WRITE FULLWORD
1000
READ HALFWORD AND SET BIT
1001
INCR. MLR BY INSTR. LENGTH; READ INSTR.
1010
PRIVILEGED READ H W
1011
DATA READ HALFWORD
1100
INSTRUCTION READ
1101
INCREMENt MAR BY 4, READ DATA F W
1110
PRIVILEGE READ F W
1111
DATA READ FULLWORD
Figure 2. Control and Module Instructions
6
OI-078A21 R06 5/78
3.5.1 Module O. Module 0 addresses the control module. As shown in Figure 2, instructions are interpreted
differently for Module 0 than the others. In the normal sequence of instructions (e.g., no branches), the hardware of the
control module controls the reading of its memories, and gates the registers specified by the instmction. When it is
addressed by an instruction, it is for the purpose of a conditional transfer. Module 0 does not manipulate the Condition
Code or Processor flag register.
Branch/Execute Instructions. There are two types of transfers recognized by Module O. The most common is the Branch.
The Branch (BR) instruction conditionally transfers control of the CPU to a specified address of control memory and
proceeds sequentially from there. The second type of transfer, commonly called an execute, transfers control to a single
instruction at a specified address of control memory, then normally returns to the original sequence. Any type of
instruction may be executed including additional execute instmctions to any depth. However, an execute which results in a
branch does not return to the continuing sequence. Bit 04 of the instruction determines whether the instruction is a branch
or execute type.
Address Link/Register Return. There are two types of Module 0 instructions: address link and register return. They are
select~:d by the state of Bit 03 of the instruction.
The linked transfer is similar in function to the user level Branch and Link (BAL) instruction, and can be used to transfer
to subroutines when they may be entered from more than one location. The location of the next sequential instruction,
following the transfer, is deposited in the register specified by the Link Held of the instruction (Bits II: 15), and a tmnsfer
is conditionally executed to the effective address.
When the address link is selected, the transfer address is spcci fied by Bits 14: 25 of the instmction.
The register return is used when the transfer address is contained in a register. In this instruction, a branch is taken to the
location contained in the register specified by Bits 20 :24.
_Conditional Branches. All transfers are conditional upon a state selected by the F field and T field of the instruction. By
selective coding of the F field, either the Condition Code of the user level machine or the status of the CPU can be tested.
The codes are shown in Table 1.
TABLE 1. FUNCTION CODES FOR CPU INSTRUCTIONS
X
T
F
MNEMONICS
-
OPERATION.
0
0
110
BAL
Branch and Link Unconditional
0
0
111
BALA
Branch and Link and Arm Interrupts
0
1
111
BALD
Branch and Link and Disarm Interrupts
0
0
000
BALZ
Branch and Link on CPU Zero
0
1
000
BALNZ
Branch and link on Not CPU Zero
0
0
001
BALL
Branch and Link on CPU Less
0
1
001
BALNL
Branch and Link on CPU not Less
0
0
010
BALG
Branch and Link on CPU Greater
0
1
010
BALNG
Branch and Link on CPU not Greater
0
0
101
BALV
Branch aild Link on CPU Overflow
0
1
101
BALNV
Branch and Link on No CPU Overflow
0
0
100
BALC
Branch and Link on CPU Carry
0
1
100
BALNC
Branch and Link on no CPU Carry
0
0
011
BALF
Branch and Link if the logical product of user Ml field and User's CC is Zero
0
1
011
BALTF
Branch and Link if the logical product of user Ml field a nd User's CC is not Zero
0
1
110
BDC
Branch & Mask Console interrupt (no real branch is performed)
01-078A21 R065/78
,
7
3.5.2 Non-CPU Instructions. As stated previollsly, when the module number is not zero, the CPU does not
operate on the instruction, and the fields are interpreted differently. The module field (Bits 0 :2) and the F field (Bits
16: 19) are interrogated individually by the other modules. There are four types of non-CPU instructions selected by Bits 3
and 4 of the instruction. They are:
1.
RRX. The RRX is a Register-ta- Register and Transfer instruction. It is effectively a four-address instruction in that it gives the register address of the two operands, the register address for the results, and the
location for the next sequential instruction.
The two operands are addressed by the A field (Bits 11: 15) and the B field (Bits 20:24). The contents of
these two registers are gated, respectively, to the A Bus and B Bus of the computer.
The S field (Bits 6: 10) selects the destination register to which the results are gated from the S Bus.
The page address field (Bits 26:31) selects the low order address of the next instruction. The high order
bits are taken from the current location address. The C field (Bit 25) being true makes the transfer
conditional upon a signal returned by the addressed module at the completion of the instruction. (The
ALU, for example, returns the Carry flag as its signal.) If the module signal, which is designated MSIG, is
true, and Bit 25 of the micro-instruction is true, the hranch does not occur, and the next sequential
instruction is executed. Any other condition causes the transfer to be effected.
I
2.
RRC. The RRC is a Register-ta-Register Control type instruction. The interpretation of the instruction
fields is identical to that of the RRX, with the exception of Bits 25 :31 which contained the page address
within a RRX instruction. Bits 25 :31 of the RRC instruction provide the micro-control of the CPU and
arc described in Section 3.5.3.
3.
RIM. The RIM instruction provides an immediate field for ease of generating constants and bit masks.
Immediate, is the tefm generally lIsed to infer that the immediate contents is the actual operand rather
than the address where the operand is found. This 12-bit immediate field (RIR 20:31) is converted to a
16-bit operand by extending the sign bit (RIR 20) when gating onto the B Bus. The S field and A field of
the instruction arc interpreted identically to that of the RRX and RRC instructions.
4.
RWT. The RWT is the Store or Write instruction of the repertoire if the CPU is equipped with an optional
writable control store. There are several notable differences pertaining to this instruction.
-Although the module number cannot be zero, it may be any other, as the CPU never communicates with
the other modules.
- The S field is not interpreted and should be null selected.
- The F field is not interpreted.
- The B field addresses the register containing the address to be written into.
- The A field addresses the register containing the data to be stored in control store.
Bits 25 :31 of the RWT instruction arc interpreted as a control field, as in a RRC instruction.
3.5.3 Micro-Control (MC). To facilitate the emulation task of the CPU, certain instructions allow an order of
micro-control within the CPU. The instructions possessing this capability are the Module 0 (RRC and RWT) instructions.
MC Field. The MC field is the user memory micro-control which allows various controls over the user memory
instruction Location Counter (MLC), the user Memory Address Register (MAR), and the reading and writing
of the user memory. The significance of the bits of the MC field are shown in Table 2.
There are certain hardware connotations to the MC operations which are not made apparent by Table 2. They are:
•
8
1.
The micro-control specified by the MC field is conditional when used within Module 0 instructions. The
read memory is only effected if the operation does not result in a transfer. (This conditioning is used to
expedite the emulation of the user branch instruction.)
2.
All of the micro-control is effected before the STRT occurs with the exception of data read and data
write. This control is effected after completion of the instruction, which allows the micro-programmer to
use the MAR or MDR as a destination and begin a read/write data immediately. It also allows the
execution of the increment and the addressing of the MAR as the destination register simultaneously,
which has functional utility.
01-078A21 R06 5/78
D Field (Decode Instruction). The D field bit informs the CPU to halt the sequential flow of microinstructions and begin to emulate the next user instruction. The Operation-Code (op-·code) field of the new
user instruction is in the UIR and provides a vector to a control store address where the emulation sequence
begins. This implies that the micro-programmer must have done an instruction read in the current or a prior
instruction using one of the proper MC field designations. The execution of a decode is conditional when used
within Module 0 instructions, and, like the instruction fetch, is only performed if the operation does not
result in a transfer.
E Field. This field is used to Enable (E) or disable changing of the Condition Code (CC) of the PSW. When
changing is enabled, the Condition Code is changed under control of the module addressed until again disabled
by this field. (The ALU, for example, jams its C, V, G and L flags into the Condition Code upon completion
. of its function.) The meaning of the Condition Code is a function of the module addressed. Flags are disabled
at the beginning of an emulation sequence.
K Field. The K field of the micro-instruction is an extension of the F field of the instruction. It is available
only on the RRC and RWT instructions and constitutes the Control Signal (KSIG) to the modules. Its
meaning, just as the F field, is defined by the module addressed by the current RRC instruction. The ALU, for
example, reinterprets shifts to be halfword when KSIG is active. It is also used to extend the functions of the
I/O module.
TABLE 2. MC FIELD
BITS
MEANING
28
29
30
31
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
..
0
0
1
1
1
1
No Action
IL
PW2
DW2
No Action
14DW4
PW4
DW4
RAS
ILiR
PR2
DR2
IR
14DR4
PR4
DR4
Increment LOC by Instruction Length
Privileged Write Halfword (two bytes)
Data Write Halfword
Increment MAR by 4, Data Write Fullword
Privileged Write Fullword
Data Write Fullword
Read Halfword and Set Sign Bit
Increment LOC by Length and Read Instruction
Privileged Read Halfword
Data Read Halfword
Instruction Read
Increment MAR by 4, Data Read Fullword
Privileged Read Fullword
Data Read Fullword
IL
The Location Counter (LOC) is incremented by the length in bytes of the last user level instruction fetched.
PW2
The Memory Access Controller (MAC) is disabled and the halfword in MDR (Bits 16:31) is written into the addressed
location.
DW2
The halfword in MDR (Bits 16:31) is written into the addressed location. MAC is not disabled.
14DW4
The Memory Address Register (MAR) is incremented by four, then the fullword in MDR (Bits 0:31) is written into
the location addressed by MAR.
PW4
The MAC is disabled and the fullword in MDR (Bits 0:31) is written into the addressed location.
DW4
The fullword in MDR (Bits 0:31) is written into the addressed location.
RAS
The halfword at the addressed location is read then re-written with Bit 0 of the halfword set. The original value of the
halfword replaces MDR Bits 16:31. Bits 0:15 of the MDR are set equal to Bit 16 of MDR (sign extension).
ILiR
LOC is incremented by the length in bytes of the last user instruction fetched, then an I nstruction Read is started from the
address specified by the new value of LOC.
PR2
The MAC is disabled and the halfword at the addressed location is read and copied to MDR Bits 16:31. Bits 0:15 of MDR
are set equal to MDR Bit 16.
DR2
The halfword at the addressed location is read and copied to MDR Bits 16:31. Bits 0:15 of MDR are set equal to MDR Bit 16.
IR
An Instruction Read is started from the memory address specified by LOC.
14DR4
MAR is incremented by four, then the fullword at the location addressed by the new va rue of MAR is read and copied to MDR.
PR4
MAC is disabled, then the fullword at the location addressed by MAR is read and copied to MDR.
DR4
The fullword at the location addressed by MAR is read and copied to MDR.
OI-078A21 R03 4/77
9
I
3.5.4 Control Store Data Storage. Data may be retrieved from the ROM or the Writable Control Store (WCS)
during execution of RRC, RRX, or RIM instructions when the I field bit (instruction Bit 5) is true. When the I field bit is
set, the data addressed onto the B Bus is used as the store address of the ROM or WCS, and causes the CPU to replace this
data with the addressed data before signaling the addressed module to begin its task.
3.5.5 Interrupts. The hardware of the computer provides nine priority interrupts. Each interrupt has a unique
trap location associated with it. Recognition of an interrupt causes the instruction stored at its respective trap location to
be performed. The RLR contents are preserved to nllow the address of the interrupted sequence to be saved, if desired, so
that control can be returned at the completion of the interrupt routine. Certain interrupts can be disabled by bits of the
PSW as designated in Register Peculinrities and Tables 3 and 4. In addition, all interrupts can be enabled/disabled as a group
by a micro-instruction. All interrupts not masked by PSW bits are interrogated when a new user level instruction is
decoded, regardless of the status of the group enable. The group enable is automaticnlly disabled at the beginning of a user
emulation, and must be enabled by instruction if the programmer wishes to recognize interrupts. Tables 3 and 4 list by
priority the pertinent information for each interrupt.
TABLE 3. INTERRUPT TRAPS
TRAP ADRS
(HEX)
INTERRUPT
1FE
207
206
205
204
203
202
201
200
208
208
Memory Access Controller (Instruction)
Memory Access Controller (Data)
Primary Power Fail
Machine Malfunction
Display Panel
~ternal Interrupt Level 0
External Interrupt Leve I 1
External Interrupt Level 2
External Interrupt Level 3
Illegal Instruction
Privi leged Instruction
GROUP
ENABLE
MASK
PSW21
NO
NONE
PSW18
NONE
YES
YES
See
Table
3
NONE
PSW23
YES
YES
N/A
N/A
PSW Bits 17 and 20 define the external Interrupt enable status of the Processor as shown below:
PSW
BITS
17
20
0
0
1
1
0
1
All Levels Disabled
Higher Levels Enabled
All Levels Enabled
Current and Higher Levels Enabled
a
1
where the current level is a function of the currently active register set. See Table 4.
TABLE 4. EXTERNAL INTERRUPT ENABLE
EXTERNAL INTERRUPT ENABLED
PSW BITS
17 20
10
25
26
27
LEVEL 0
LEVEL 1
LEVEL 2
LEVEL 3
0
a
X
X
X
NO
NO
NO
NO
0
1
0
0
NO
NO
NO
NO
0
1
0
a
a
1
YES
NO
NO
NO
a
1
a
1
0
YES
YES
NO
NO
0
1
0
1
1
YES
YES
YES
NO
0
1
1
0
0
YES
YES
YES
NO
0
1
1
0
1
YES
YES
YES
NO
a
a
1
1
1
0
YES
YES
YES
NO
1
1
1
1
YES
YES
YES
NO
1
0
X
X
X
YES
YES
YES
YES
1
1
0
0
0
YES
NO
NO
NO
NO
1
1
0
0
1
YES
YES
NO
1
1
0
1
0
YES
YES
YES
NO
1
1
0
1
1
YES
YES
YES
YES
1
1
1
0
0
YES
YES
YES
YES
1
1
1
0
1
YES
YES
YES
YES
1
1
1
1
0
YES
YES
YES
YES
1
1
1
1
1
YES
YES
YES
YES
01-078A21 R06 5/78
3.5.6 Registers. The basic CPU has up to 8 sets of general registers each containing 16 user registers, 16 floating
registers, and 8 general purpose registers for use by the micro-programmer. In addition, the bulk of the remaining CPU
registers is also available to the micro-programmer.
A register is available to the micro-programmer if he can address it to one or more of the internal busses. Table 5 tabulates
the addressable registers and their respective address on the designated bus. Also listed are register mnemonics, descriptions, and the register peculiarities.
TABLE 5. REGISTER ADDRESSING
.-------------------...,...---.------r---.-----.- .------.. ---...
BUS ADDRESS (HEX)
S BUS
B BUS
A BUS
I==================t====;=======_----=...:.==-~:o_o_-=--__=
OO:OF (16 General Registers)
URn
10:17
MRn
=. :===c.co,_:=-===_
URn
URn
MRn
MRn
1-------------------+----_·__ ·_---;-------------------- ---------- ----.-------+---------------------18
YS
YS
YS
1---------------------+--·-----------4------------~--------
19
YD
YD
YD
1------------------+---------1--------------------lA
YX
MLC
MLC
1--------------_·_-_·_--_·_------ .------- -----1--------.. - - - - - - - .... --------- -.-- .--.. --.-- ...... -------1B
MDR
MDR
YDP1
1-----------·-------------- --.. . .--·--------r-------------------·--> ....· .--_.....- -.. -----1C
MAR
EFFECTIVE ADDRESS
10
PSW
YSI YD
1------_·_----_·_--------_·_- ------.---;-------------.-- -_.--..-.. -..PSW
- - . - - - - - - - - - - - - - - - - - . - - - - - - - - - - - - --------.- 1--------._------- .. _----- ...... -..-----... --- ..--....----.---.
YOI
1E
._----------_._--_._---_.-
NULL
1F
I
YDI YSI
- - - - - - + - -...-------------- r-- -
NULL
......_.- .. ----.---
NULL
Register Mnemonics and Descriptions.
MNEMONIC
REGISTER
COMMENT
UR
User General Registers
16 registers manipulated by emulated
language
MR
Micro.-level General Registers
8 additional GP registers available to
the micro-program
PSW
Program Status Word
16 bit register containing interrupt
enables and flags
MDR
Memory Data Register
MLC
Memory Location Counter
MAR
Memory Address Register
NULL
No register selected
Gates 0 to A and B Busses, S Bus data
is lost
YS
User Source Register
Register selected by Bits 12: 15 o(
emulated instruction (contents of
USR)
YSI
User Source Register Immediate
Bits 12: 15 of the emulated instruction
(USR) gated onto B Bus
YX
User Index Register
Same as YS except NULL gated to A
Bus if field is 0 (contents of USR=O)
YD
User Destination Register
Register selected by Bits 8: 11 of
emulated instruction (contents of
UDR)
YOI
User Destination RegIster Immediate
Bits 8: 11 of the emulated instruction
(UDR) gated onto the A Bus
YDPI
User Destination Register Plus 1
Register selected by Bit 8: II of
emulated instruction +1 (must be
odd)
YDI
User Destination Register Immediate
S Bus 28:31 replaces UDR contents
Ol-()78A21 R06 5/78
Location
program
Counter
of
emulated
I
11
Register Peculiarities. The last four bits of the PSW contain the Condition Code of the emulated computer. In general,
these bits can be manipulated by any addressed module unless the PSW is the S Bus destination or their change has been
inhibited by the micro-instruction. The individual bits of the PSW which have hardware implications are:
ATN interrupt enable and level selection
Machine Malfunction enable
Privilege instruction/Memory Protect enable
User register set selection
C flag of Condition Code
V flag of Condition Code
G flag of Condition Code
L flag of Condition Code
PSW 17, 20, 25:27
PSW 18
PSW 23
PSW 25:27
PSW 28
PSW 29
PSW 30
PSW 31
The following additional registers have the indicated capabilities and connotations.
I.
The MDR receives data asynchronously from memory. It is used in the address calculation for RX3
instructions.
2.
The MDR, MAR, and MLC being addressed cause the Processor to interlock with memory when they are
the source or destinations of the current instruction and the Processor is requesting memory service.
3.
The MAR and MLC can be incremented by the micro-control.
4.
The MLC is used in the address calculation for RX2 instructions.
3.5.7 CPU Flags. The CPU contain~ a flag register which is independent of the PSW flags and is manipulated by
any module which attempts to affect the PSW Condition Code by activating the SCC control line of the CPU Control Bus.
When the SCC control line is active, the state of the VCe, CCe, GCC and LCe are unconditionally jammed into the CPU
flag register and conditionally into the PSW Condition Code. 'TIle changing of the PSW is controlled by the microprogrammer by the E field of the micro-instruction. The state of the CPU flags can be individually tested by the Module a
instructions.
I
3.5.8 Arithmetic Module (ALU) Programming. The Arithmetic Logic Unit (ALU) in all 8/32 processors is optionally capable of performing both fixed poin t arithmetic and logical operations and single precision floating point arithmetic
operations. The 05-058FOI micro program of the basic 8/32 permitted the user to address the ALU as Module I for fixed
point operations, or as Module 3 for single precision floating point operations. The 05-058F02 micro-program of Models 8/32C
and 8/32D, however,normally permits the user to address the ALU only as Module I for fixed point operations. All single and
double precision floating point operations are available through the optional DFU unit. If the optional DFU is present, it is
addressed as Module 6: if two optional DUFs are present they arc respectively addressed as Modules 6 and 4. For information
concerning the DFU, see the 8/32 DFU Instruction Manual, publication number 29-538. In Models 8/32D, the Module 3
single precision floating point facilities of the ALU may be made available for special purposes through the use of the optional
Writable Contr01 Store (WCS). See Appendix I of this specification for more information concerning Module 3 operations.
The discussion of the ALU in this section is directed only to its fixed point operations. The ALU is capable of performing 15
operations. Refer to Table 6. Communication with the ALU is asynchronous. By design, the ALU is never busy and for the
majority of ALU functions, response is within 130 nanoseconds. (This allows most ALU referenced instructions to be completed in 260 nanose;;onds.)
TABLE 6. MODULE 1
c-----
MODULE 1 (FIXED POINT)
F FIELD
a
a
0
0
a
a
a
a
a
0
1
1
1
a
1
1
1
1
a
a
a
1
1
a
1
1
1
1
1
1
1
a
a
a
a
a
a
a
1
1
0
a
a
a
a
OPERATION
1
1
1
1
1
1
a
1
1
a
a
0
1
1
1
1
0
1
1
Subtract
Add
Subtract with Carry
Add with Carry
Not used
Logical AND
Logical Exclusive OR
Logical OR
'"Logical Shift Right
* Logical Shift Left
Rotate Right
Rotate Left
* Arithmetic Sh ift Right
* Arithmetic Shift Left
Signed Multiply
Signed Divide
* When used in conjunction with the K bit of the RRC instruction,
shifts are halfword (16 bits).
12
01-078A21 R08 11/78
For functions which require more than one ALU cycle (i.e., shifts, rotates, and multiply/divide), the ALU docs not
with a finish signal until the completed results are on the S Bus.
responl~
Multiply/divide can be performed only on the 32 general registers and must address the same register pair on both the A
and S Busses. The same restrictions that apply to these operations at the user level must be adhered to at the micro level.
I
A user emulated multiply/divide instruction is micro-coded by selecting the ALU (Module 1); addressing the UDR on the S
Bus, the UDRPI onto the A Bus, the USR onto the B Bus, and the required function code for the operation. When the
ALU signals its completion, the results have already been deposited in the UDR.
To implement a shift or rotate instruction, the register to be manipulated is addressed onto the A Bus, the shift count is
put onto the B Bus (27 :31), and the S Bus is gated to the destination register.
The ALU generates valid CPU flags for all instructions except multiply/divide. The C flag is gated as MSIG.
3.5.9 I/O Module Programming. The I/O module performs a mUltiplicity of functions. In general, it is addressed
to communicate with the multiplexor channel through the multiplexor bus. It has the additional capability of performing byte
manipulations for the CPU both in conjunction with an I/O exchange and without one. Furthermore, the I/O module contains
the ~~ister (MS~hich stores machine trouble conditions and interrupts the CPU. The contents of the
MCR can be sensed, testC'C'r'ai'1clcleared. Module Number 2 has been assigned to the I/O module.
Multiplexor Channel. The Multiplexor Channel, generated on the I/O module, is operationally identical to the
standard Perkin-Elmer Multiplexor Bus in all respects. The Multiplexor or Bus is a byte or halfword-oriented
I/O system which communicates with up to 255 peripheral devices.
A single instruction from the CPU contains the device address, the encoded function, and up to 16 bits of
output data when needed. The Multiplexor Bus generator provides single or multi-cycle operation to address
the device, transmit the decoded function, send or receive over 16 bi-directional data lines, and synchronize
the exchange.
The normal byte or halfword operation consists of an address cycle and a data cycle. However, during a
Read/Write block sequence, the address cycle is not used. For halfword functions (RDH/WDH) with a byte
oriented device controller, two clata cycles are used to transfer the halfword.
Byte Manipulation. The I/O module has the capability of performing byte manipulation both in conjunction
with an I/O operation and without one. The hYt5Ls1ccring is un9_eI.~ontrol of the Ica~t significant memory
address bit in the MAR ~nd also the KSIG line. For halfword operations, this manipulation is inoperativeDut
Hie '0011'61'(;' data cycle with packing/unpacking results when the Halfword (HW) Test line is inactive.
I/O Module Function Codes. The encoded I/O module functions and the byte manipulations arc described in
Section 3.7.3.
OI-078A21 R06 5/78
13
I
Machine Control Register (MCR). The Machine Control Register (MCR) consists of four flip-flops, four straps,
and the Console Attention (CA TN) and SNGL leads from the Display controller. MCR bit assignments are:
BIT
15
14 (8/32C, 8/32D)
(148/32 only)
(13 8/32 only)
13 (8/32C, 8/32D)
12
11
10
09
08
07
05
04
06
MNEMONIC
EPF
--BMP-F,·IRLMP
DMPF
IA/STF
STF
CATN
RSET
spare
SNGL
HWCRC
DFU
MCR061
MEANING
Early Primary Power Fail
Data/Instruction Memory Parity Fail
Instruction Read Local Memory Parity Fail
Data Memory Parity Fail
Unused
Illegal Address and/or Start Timer Fail
Starter Timer Fail
Console Attention flip-flop (from Display Controller)
Register Sets Available
spare (strap)
SNGL flip-flop (from Display Controller)
Hardware Assist CRC option (strap)
DFU option (strap)
INIT Button is being depressed
On the basic Model 8/32, the IRLMP flip flop stores the signal received from the Local Memory Interface (LM!), and the DMPF
flip flop stores the signal received from the Memory Bus Controller (MBC). On Models 8/32C and 8/32D, the DMPF flip flop
(bit 14) stores signals received from the MBC. Signals to get the EPF and STr bits are generated on the IOU board by the Power
Monitor and Statt Timer circuits. The composite bit (MCRI2) can be strapped to represent lA, STF, or both. MCRII is
always set by STF. The testable straps are wired for logical ONE or ZERO as required. A Machine Malfunction (MMF) interrupt is generated when any of Bits 12, 13, 14 or 15 are true. The SMCR function gates MCR 12: 15 to the CC Bus, MCR08: 15
to S08: IS. and MCR04:05 to S04:05. The CMCR operation clears MeRl1 :15 where there are ONES in BII :15. This permits
selective clearing of some bits while the rest of the MCR continues to monitor other machine functions without loss of data.
/
Start Timer (STRT). A 35 microsecond timer is started by the STRT signal and cleared by the MFIN signal
from any selected module. Should the timer run out before the MFIN signal arrives, a malfunction exits; i.e.,
non-existant module. circuit trouble, or no SYN return from the Multiplexor 01annel. If a D Bus function was
called for, the False SYNC code (0 1OO/CVGL) is placed on the CC Bus and a pseudo MFIN signal is sent to
restart the CPU clock. Also, if the function required is of the Sense Status type, X'04' replaces the proper
byte as determined by CA31l, and the other byte is gated to the S Bus unchanged. For a non-D Bus
operation, the Start Time Fail (STF) bit is set in the Machine Control Register (MCRIl), and a pseudo MFIN
signal is sent to restart the CPU clock. If STF is strapped into MCR I 2, the MMF interrupt is also generated.
14
01-078A21 R06 5/78
/
3,6 Processor Block Diagram Analysis
3,6,1 CPU (Figure 3), The architecture of the Processor is structured about four busses which provide intercommunication between the CPU and the remaining modules,
'nle CPU selects the module via the Control Bus (C Bus), specifies the function, and signals that data is available on the A
and B Busses, The addressed module signals when it has completed its function and transmits flag type data back over this
bus,
The A Bus and B Bus contain the two operands offered simultaneously to the addressed module to be manipulated. Most
of the CPU registers can be gated onto the A and B Busses,
Data from an addressed module is returned to the Processor via the S Bus.
'The ROM Instruction Register (RIR) is a 32-bit register that latches the current instruction read from the control store
memory to provide the control gating for each instruction, Data can also be gated from the RIR onto the B Bus for
indirect data fetches, One of the many functions performed by the encoded instmction is register gating. 111is is performed
by the select logic to encode the A, B, and S SEL lines, these lines determine which registers arc gated onto the A and B
Busses, and which register is the S Bus destination.
'nle Control Store Address gates (CSA) select the address of the control store to be interrogated next. Inputs to the CSA
may be the ROM Location Counter (RLC) to select the next instruction, certain bits of the RIR for branching, the B Bus
for indirect addressing or branches, the translated vector for the next user instruction to be emulated (XLTR), or interrupt
trap address from the interrupt logic,
'The ROM Location Register (RLR) preserves the address of the current instruction. It is loaded with the address of the
current instruction every time the RIRis loaded, except when the instruction is an interrupt or execute type which do not
alter the ROM Location Register. The RLR is gated to the RLC to perform RLR+I for the next sequential instruction.
The general register sets and the 8 general micro-registers ale contained in the A stack and B stack. This is a redundant
pair of register stacks, implemented as such to allow gating of any two registers of the machine simultaneously onto both
the A Bus and B Bus, Gating of these stacks is controlled by the A, B, and S SEL lines, just as the other A, B, and S
source and destination registers.
'The Program Status Word register (PSW) is an architectural feature of the user level machine. Certain bits of the PSWare
used to mask interrupts, control the privileged mode of the Processor, and to contain the Condition Code of the user level
program. This register can be gated to the A and from the S Busses. The Condition Code portion can also be loaded
independently of the register addressing.
'The Memory Location Counter (MLC) aids the emulation capability of the Processor. It is llsed to contain the memory
location of the current user level instmction, In addition to being capable of being gated to/from the Band S Busses, this
register may be incremented by the length of the last emulated user instruction under micro-control of the programmer.
The Memory Address Register (MAR) contains part of the address to he used by the main memory for a read/write
operation, This register can be loaded from the S Bus, and may also be incremented by micro-control of the programmer.
The manipulation of this register is interlocked with the memory operation by hardware to remove timing restraints from
the micro-programmer.
'The Memory Data Register (MDR) is loaded from the S Bus with data to be written into the main memory, or it is loaded
from the Memory Data Bus with the contents of the addressed memory on a memory read operation. This register may be
gated onto the B Bus of the Processor, and, like the MAR, hardware interlocks remove the timing considerations of the
memory system from the micro-programmer when this register is referenced.
The User Instruction Register (UIR) stores the 8-bit op-code of the next user instmction to be emulated, It is loaded from
memory when a Read operation is designated as an instruction fetch by the micro-code. The 8-bit op-code is translated to
a vector which designates the beginning address of the emulation sequence for a particular instruction. The 8-bit op-code is
also gated to a Privileged/Illegal ROM which is coded to detect these types of instructions and cause an interrupt to the
Processor.
Ol-078A21 R06 5/78
15
I
The memory User Destination Register (UDR) and memory User Source Register (USR) store the destination and source
fields of the next instruction to be emulated when it is read from memory. This data is transferred to the User Destination
Register (YDR) and User Source Register (YSR) at the beginning of a new emulation sequence to provide residual control
for the instruction.
Memory Control is effected by the micro-control field of the micro-instruction. The ability is provided to cause data read,
data write, and instruction read.
3.6.2 ALU. The ALU is a standard module of the Model 8/32 and provides the basic arithmetic/logic capability.
It communicates with the CPU over the A, B, S, and C Busses in a manner identical to other modules.
The ALU becomes active when it recognizes its address on the Control Bus (Module Number I), and the CPU signals
start (STRT). The function to be implemented is determined from the Control Bus.
ALU functions may be of two types. The simple functions (add/subtract and logical) cause the ALU to immediately return
a Module Finished signal (MFIN). For these type of instructions, the A and B Busses are gated through the ALU, and the
required function is performed and gated onto the S Bus.
For the complex type functions (multiply/divide and shift) the ALU clock is enabled and a hardware sequence is entered
to perform the required operation. The shift gates are used to shift the A Bus or the Sum Bus right or left back into the
A latch and onto the A Bus again as determined by the ALU algorithms. In the case of fixed point multiply/divide the ALU
stores half of the completed results before signaling the CPU with MFIN. The other half is dumped onto the A Bus from the
MQ register and gated through the ALU onto the S Bus when MFlN is activated.
3.6.3 IOU Board. (Refer to the Block Diagram in IOU section.) The IOU board contains the I/O Control, the
Display controller, the TTY controller, the Machine Control Register (MCR), the Power Monitor, Initialize circuits and the
Start Timer.
The Display and TTY controllers have access to the CPU via the MUltiplexor Channel D Bus and the I/O Control in the
same manner as other peripheral device controllers. The Display controller provides a visual display of the contents of all
system registers and any main memory location, together with the capability of manually entering data and programs. It
shares D Bu's drivers/receivers with the TTY controller and signals the CPU directly with the Display (DSPL Y) interrupt.
The Console Attention (CATN) signal appears as Bit 10 of the MCR.
The TTY controller, which supports the Model 33/35 Teletype, provides serial/parallel conversion and all standard TTY
control features. It contains a full character buffer in the receive mode to permit a program service interval of one
character time (100 milliseconds). The detailed descriptions of the Display and TTY controllers are covered in Sections 12
and 13 respectively.
11/0
Control. The I/O Control performs a multiplicity of functions. The main function is to generate Multiplexor Channel D Bus from the CPU busses whenever it is addressed by Module Number 2 and the proper
function selections are made. The control also performs byte manipulation for the CPU both in conjunction
with an I/O operation and without. Common function decoders also generate signals to sense/clear the MCR
(which stores Machine Malfunction conditions), to set the system Stop flip-flop with a Power Down/Initialize
function (FPOW), and to gate 4-bits of the B Bus (12: 15) to the front terminal strip of the chassis for /
external signaling purposes; e.g., multi-CPU operations.
Four function select lines together with the KSIG line pick 1 of 32 possible functions as shown on Table 7.
TABLE 7. I/O CONTROL FUNCTIONS
FSELOX
FUNCTION
0
1
2
3
KSIG=O
0
1
2
3
4
5
0
0
0
RD
O·
6
a
a
0
0
0
1
1
1
1
0
0
1
1
0
7
8
9
0
0
0
0
1
1
1
1
1
1
1
1
a
a
a
a
a
1
1
a
a
1
0
1
a
1
a
1
0
1
WD
SS
OC
RDH
WDH
ACK
*SMCR
RDA
WDA
A
1
SSA
1
1
B
OCA
1
C
0
RDHA
1
1
D
WDHA
*THW
1
E
1
*POW
1
1
1
F
* Functions that do not require operation of the Multiplexor Channel D Bus.
16
a
a
a
a
KSIG=l
RDR
WDR
SSR
OCR
*STBR
*LBR
*LDWAIT
*CMCR
RDRA
WDRA
SSRA
OCRA
*STB
*LB
*EXB
*POUT
01-078A21 R08 11/78
0
S
L
0
--l
00
>
tv
II
a
CD BUS - 32
~
CMC-3
8
I
UIR
~
8
1
I
w
~
-.J
h CA BUS - 19
~
' - - - - - - - - + - - - - - 1 - - - -....
3 }'
cr
DEC,
19
32
~I
It
v
I
I
-I
I
I
Ii 0"'1
RAG
4
USR
4
I
I
1
I
I
1
12
f.--f-
t-__t-~1=2711-~A~P~R~6~4~nE
4
I
YS
I'YI
CONTROL .......- . .
RLR
I-STORE
~D c: RI£6
v12
I,
I
12
I
0
..J:>.
R is (Figure 41- The following paragraphs provide
brief descriptions of the function and data interfaces of each of the blocks in' the MAC
MAC Base Registers (BR). The BRs are a set of 16 24-bit registers which store the relocation, limit and interrupt control data
for the Memory Access Control (MAC). BR receives a 4-bit address from the Base Register Address System (BRAD), is loaded
with :~4-bits of data from the M DR on command from the micro-program, provides an 8-bit limit field (BR04: II) to the Limit
Comparator (LIMIT), a 12-bit relocation field (BR 12: 23) to SUM 1 X, and a 4-bit interrupt control field (BR24 :27) to STA TR.
MAC Base Register Address System (BRAD). The BRAD contains a 4-bit register, two 4-bit multiplexors, a 4-bit adder.
and pwvides addresses to the BR from three sources: the Memory Address Bus CA.26:29 for loading, Mel 12: 15 for
instruction fetches, and MAlXI2: 15 (through the 4-bit register) for data operations. The 4-bit adder provides a carry
capability whenever MlC is incremented across a memory segment boundary.
MAC Status Register Unit (STATR). The STATR is a 5-bit Interntpt Status register with associated address decoding and
interrupt controls. STATR is disabled whenever PSW21 is inactive or whenever a privileged micro-control is effected. (Privileged in this context means that MAC relocation and protection an.' disabled, exactly as if PSW21 were made inactive.)
When relocation and protection are disabled, a decoder senses C A 12:31 and traps the locations assigned to the MAC. It is then
possible to load BR or to read the five bits of STATR using the same procedures that are used to read from or write to memory.
When relocation and protection are enabled, references to the trapped locations rl'sults in accesses to memory. The Memory
Access Interrupt logic is also activated, under control of BR24:27.
MAC ILimit Comparator (LIMIT). The Limit Comparator compares each memory address with the 8-bit limit field in BR
and, wlH:n the protect function is enabled. GIUSl'S an interrupt to be generated if an attempt is made to access a memory
address which is larger than the limit.
MAC' Summer 3 (SUM3X). The SUM3X monitors the MLC and anticipates when the incremented MlC (for RX and RI
instructions) passes a segment boundary. When this occurs. the BR address is incremented by one. and a delay is initiated
to allow time for a BR address change.
4 . 2 Memory Addressing (Refer to Functional Schematic 35-536008 for mnemonic location.)
The 8/32 memory address data is derived from MLC, MAR. MOR, thl' MAC BR, and two carry signals. Selection from among
these sources, and the computations used to arrive at the final address, are ddermined by the machine cycle (instruction fetch
or data operation), instruction format (RR, SF, RX, or RI), and status of the Memory Access Controller (MAC).
Ouring instruction fetches, which are initiated by particular states of the MCOO:03 Bus from CPB, the program memory address is taken from MlC. RX and RI instructions require increasing the effective address by two or four bytes to access the
second and third halfwords of the instruction. If relocation is enabled by PSW21, an additional 12-bit relocation field is added to MlC. The effective address is then:
CA
= MlC' + BR (MAC) + carries (2
or 4)
this addition occurs in SUMl X. (Sheet 8)
When memory is accessed for data operations in response to a user instruction, the effective address may be the sum of as
many as five parts: an absolute address, a relative displacement, a first index, a second index, and MAC relocation field.
For RXI instructions, the absolute address is contained in MDRI8:3I and the index in a user register addressed by the
contents of register YX in CPB. For RX2 instructions, the relative displacement is contained in MORI7:31, the reference
address in MLC (incremented by four) and the index in a user register addressed by the contents of register YX in CPB.
01-078A21 R08 11/78
21
I
For RX3 instmctions. the absolute address is contained in MDR 24:31. the first index in the user register addressed by the
contents of register YX in CPB. and the second index in the user register addressed by the contents of register SX in CPA.
Each of these program addresses can then be modified by the MAC relocation field from BR. The address calculations are:
RXI:
MAR
CA
(YX) + MDR
MAR + BR
RX2:
MAR
CA
(YX) + MDR
MAR + MLC + 4 + BR
RX3:
MAR
CA
(YX) + (SX)
MAR + MDR + BR
In each of these formats, the first addition is performed in the ALU and, the second addition is performed. simultaneously,
by hardware in the CPA.
4.2.1 CPA Address Computation Instruction Fctch Address Computation. (Sheets 3, 6 and 8) TIle computation
CA MLC + carries + BR is done in SUM I X as shown on Sheet 8. It consists of five 19-067 4-bit ALU ICs and one 19-068
Carry look-ahead IC which is connected across the 16 mos.t significant bits of the ALU. The "A" inputs to the ALU ICs are
connected to MALZl2 :31. For instruction fetches, SIR 1 is active. and the outputs of MALX 16 :31 are MLC 12 :31 (Sheet 3)
and the outputs of MALZ 12: 15 arc either M LC 12: 15 or arc open. depending on whether the MAC is enabled. If the MAC
is disabled PROTI (8 R.2) is inactive and MALX 1.2: 15 arc enabled. If MAC is enabled, PROTI is active (high) and MALX 12: 15
are inactive and effectively all zeros.
I
The "B"inputs to SUMI X28:30 (8D7) arc derived from Carry signals COO and COl (Sheet 1), and RX2Fl (Sheet 10). For
RXl, RX2, and RIl formats, MLC must be incremented by two bytes to read the second halfword of the instruction from
memory. COOl is made active, and both CO! 1 and RX2Fl arc inactive. Since the ALUs of SUMl X are operating on
low-active data, these conditions cause the B 1 input to be active (low) through the NAND gate (8B4), the B2 input to be
inactive (high), and a count of two bytes to be added to MLC28 :31 to produce CA28 :30. If a Carry (Cn +4) is produced by
the lowest-order ALU, this is propagated through the remaining bits of CA by means of the 19-068 Carry look-ahead IC
device.
For RX3 and RI2 instructions. which require that three halfwords be read from memory, COlI is made active after the
second halfword is read from memory. This clisables the Bl input to the ALU (807) and, through the AND-OR-Invert gate
(8B3), causes the B2 input to the ALU to become active, adding four bytes to the memory location from MLC.
I
When MAC is disabled, PROTI (8R2) is inactive. PROTO (8E6) is active (high) and the ALU is in the A only mode, producing
CA-- MLC + carries. When the MAC is enabled, PROTI is active, PROTO is inactive, and SUM 1X is placed in the A + B mode,
where the B inputs 1.0 SUMl X12:23 are BR120:230 (Sheet 6). producing CA-MLC + carries + BR.
Data Read/Write Address Computation (Sheets 3,4,6, 8 and 9)
TIle address computations required for data operations are determined by the instruction format, as shown previously in
Section 4.2.
For RXI instructions. the computation which must be performed in hardware is:
I
I
CA-MAR+BR
The following conditions exist at the inputs to the gates (8A3 and 8A4) which produce ALU inputs B 1 ancl B2; SDRDWO
is active, ancl COlI ancl RX2Fl are inactive. Both B I and B2 are thus held inactive, inhibiting any address carries into
SUM 1X. The Memory Address Bus CA12:30 is then equal to the outputs of MAMLX12:30, if the MAC is disabled, or the
sum of MAMLXI2:30 and BRl2:23 if the MAC is enabled.
MAMLX (Sheet 8) is a 20-bit wide, two-input multiplexor which switches the inputs to SUMIX between MLC and
SUM2X, depending on the machine cycle as indicated by SIRI. For data operations, SIRI is inactive, and
MAMLX -SUM2X.
SUM2X (Sheet 9) is a 20-bit ALU similar to SUMI X. The A inputs are MAR12:31. and the B inputs are MUXBI2:31. The
A inputs to MUXB are MLCI2:31, the B inputs to MUXB are MDR12:31 and the select input to MUXB is RX3Fl, so that
for RX3 instructions MUXB-MDR and for other formats MUXB-MLC. The control inputs to the ALU are RXIDOA
and RXIDOB, which are both active low for RXI instfilctions. This control condition cause the outputs of SUM2X to be
equal to the A inputs, or MAR 12: 31, and the address calculation for RX I instructions is correct.
22
01-078A21 R06 5/78
For RX2 instructions, the computation which must be performed in hardware is:
•
CA+-MAR + MLC+4 + BR
Since RXI DOA and RXI DOB are inactive (high) SUM2X is in the A plus B mode. The A inputs are MAR12 :31, and the B
inputs are MUXB12:31. The select input to MUXB (Sheet 9) is RX3Fl, which is inactive (low) for RX2 instructions.
MUXB12:31 are then connected to the A inputs, which are MLC12 :31. Thus SUM2X calculates MLC + MAR.
Since the RX2FI input to the AND-OR-Invert gate (8B4) is active, when the system control state reaches State O(CSOOI
active) a carry is enabled at the 4-bit AlU (8D7). This increments the output of the ALV (Sheet 8) by four. If the MAC
is enabled, BR12:23 are summed into the AlU and into the address. If the MAC is not enabled, the address output is
MAMLX + 4. Since SIRl (8C3) is inactive, MAMlXI2:31 is SUM2X12:31 and, as shown previously, this is MAR + MLC.
Thus, CA MAR + MLC + 4 + BR as required for RX2 instructions
I
For RX3 instructions, the computation which must be performed in hardware is;
I
CA..- MAR + MDR + BR
The calculation of MAR ,+' MDR is done in SUM2X by RX3Fl (9C2) becoming active and switching MUXB12:3l to
MDR12:31. The final calculation is done by the ALU (Sheet 8) as for RXI instructions.
Since MDR is used to provide part of the address for data reads and data writes, it is essential that the address be kept
stable during the memory operation. For data reads, MDR is used as a double-rank buffer. The data from memory is loaded
into the register (Sheet 4), by making both MClKO and the Load inputs on Pin 09 of the 19-070 Ie devices si.multaneously
active (low). The outputs MDROO:31 do not change until MCLKO becomes inactive, which occurs after memory has been
read and the address may change. For' data writes, where the data word must be loaded into MDR to write into memory,
the calculated address is first loaded into MAR, and then the data is loaded into MDR. This last operation is performed by
the micJfO~program.
4.2.2 Base Register Selection
I
The Base Registers (BR) are selected for loading or when MAC is enabled for relocation and protection. When selected for
loading, the registers are addressed in the same manner as memory locations and the associated mem ory locations receive
and store the same data as the BR. When the MAC is enabled, the BR is selected using the four most significant bits of the
program address: MLCI2: 15 for instruction fetches and SUM2XI2: 15 for data operations.
There are 16 Base Registers (BR), selected by the four address bits at Pins 01, 13,14, and 15 of the 19-075 IC devices
(Sheet 6). The I MB memory is segmented into 16 64KB segments, and the four most significant bits of the 20-bit program
address determine which segment, and therefore which Base Register (BR) is in use. For instruction fetches, the 4-bits are
taken from MLCI2:l5. For data reads or writes, the 4-bits are taken from SUM2XI2:] 5.
Base Register Selection fOf Loading. The Base Registers (BR) and the Status Register (STATR) (see Section 4.1.2) are
assigned a group of memory addresses starting with an odd multiple of X' 100' from '300' to '900', and ending at address
'43' within the group. The MAC is configured to trap all 256 addresses within the group. The particular group used is a
function of the system I/O requirements, and selection of the starting location of the group is by means of one or more
jumpers (7B8). Table 8 shows the required jumpers for various ~tarting locations.
TABLE 8, STARTING'lOCATION JUMPERS
STARTING LOCATION
01··078A21 R06 5/78
05J11 TO:
05J13 TO:
~
05J15 TO:
'300'
05J06_~
05J03
'500'
05J05
05J04
05J01
'700'
05J06
05J04
05J01
'gOO'
05J05
05J03
05J02
05JOl
'*
...
23
Whenever the MAC is disabled, by PSW21 being reset or a Privileged memory command present, P''''OTO (7 AS) is inactive,
and if any address within this trapped interval appears on the CA Bus, a SRTRI signal (7N6) is macle active. This signal
(6C8) causes a multiplexor to switch the address inputs of the 19-075 Base Register IC devices (Sheet 6) to CA26: 29. The
desired register is then selected. If the address is obtained because of a memory write command, a request pulse (CREQO) is
transmitted to memory and, simultaneously, an active pulse appears on RQFFO (7 A9). This causes the flip-flop (7F8) to be
set, making BRWRI active (7N7). This signal is gated with CA300, the halfword select bit of the memory address, and with
FWWRTO, a signal (2M7) which is active whenever a full word write is commanded, to produce SEGWEAO and/or
SEGWEBO. These in turn enable writing from MDX041 :271 into the odd or even halfwords of BR, or both.
Base Register Selection for Relocation and Protection (R and P). Whenever PROTO (7 AS) is active, due to PSW21 being set
and no privileged memory operation in the Micro-Control (MC) field of the micro-instruction, SRTRI (7N6) is made
inactive. This causes the 19-132 multiplexor at the address inputs to BR (Pins 01,13,14, and 15 of the 19-075 Base
Register IC devices) to be connected to the output of a 19-133 4-bit adder (6B6). The four address bits to BR then
depends on whether an instruction fetch or a data operation is being performed and also whether the carrys needed for
fetching the second and third halfwords of RX and RI instructions increment MLC beyond a segment boundary.
For instruction fetches, the segment number and therefore the Base Register (BR) address is determined by MLCI2: 15.
Whenever relocation and protection are enabled. and a data operation is not being performed, SRTR I (6A8) and SDRDWI
(6A4) are inactive, and the address inputs to BR is connected to MLCI2: IS through the multiplexors (Sheet 6).
If the program address for an instruction fetch is within one halfword of a segment upper boundary, and the instruction
format is RX or RI, the subsequent halfword carry causes the four most significant bits of the program address to
increment by one. MLCI2: IS does not change, so a simulated carry C3XO (6A5) is made active hy the circuits shown on
Sheet 12, which are discussed later. An active C3XO increments the output of the 19-133 IC Adder (6A6) by one and
causes the BR address to increase by one.
If the program address for an instruction fetch is with two halfworcls of a segment upper boundary and the instruction
format is RX3 or RI2, the second carry into the program address causes the four most significant bits of the program
address to increment by one. C3XO is made active and the BR address is incremented by the adder (6A6).
Sheet 12 shows the circuits which generate the simulated carry signal C3XO. The instruction location within the segment is
contained in MLCI6:30. For a carry to cause the instruction location to move to the next segment, all of the bits in MLC
from MLC29: 16 must be active. In addition. if MLC30 is active, the first carry of the instruction fetch sequence propagates
up to the Base Register (BR) select bits MLC'l2: IS.
If MLC16:23 are active, the input on Pin 05 of the C3XO gate is high, whenever SIRI is active (during an instruction
fetch). If, at the same time MLC24:29 arc active, the inputs on Pin 01 of the 19-058 gates at locations 12E5 and 12E6 are
active. If MLC30 is also active, and COOl becomes active, signals GTO, GTI, and C3XO all become active.
If MLC30 is inactive, COOl does not generate C3XO. However, if the instruction format is RX3 or RI2, COIlA becomes
active when the third halfword is read from memory. This causes GTO, GTI, and C3XO to become active, signalling that
the address has incremented beyond the segment upper boundary. GTO and GTI are used in limit checking and are
discussed later.
When a data operation is commanded by the micro-control bits. a SDRDWI signal (2S9) is decoded from MCOO :03 and
latched in a tracking latch (Sheet 2) when DREQ I becomes active at the start of the memory operation. This causes the
multiplexor outputs (6B4) to be connected to the inputs of a quad flip-flop (6B2). These flip-flops store the four most
significant bits of the most recent data operation, so that as soon as it is determined that a data operation is to be
performed, the Base Register (BR) address lines are switched to what is most likely the correct segment. If, however, the
new data address is in a different segment than the most recent data address. a 19-117 4-bit comparator (6C2) is enabled to
compare the new segment number on SUM2X 12:15 to the old segment number stored in the 19-131 quad flip-flop.
Approximately 100 nanoseconds after the start of the data operation a PI aONI pulse is gated into the quad flip-flop and
updates the, stored segment number. The output AEQBl of the comparator is used to cause an 80 nanosecond delay in
memory operation whenever the segment number changes, to allow time for the new base register to be accessed and the
address calculation to change.
4.2.3 Base Register Write Operation. As described in Section 4.2.2, the Base Registers (BR) are addressed from
CA26: 29 whenever relocation and protection are enabled and one of the trapped memory locations is addressed on the CA
Bus. If, at the same time the MC field of the micro instmction calls for a Write operation, a SDWI signal is decoded from the MC
field and appears active (7H8). Subsequently, a request is made to memory and a RQFFO signal (7 A9) becomes active for approximately 50 nanoseconds. The leading edge of RQFFO sets the flip-flop (7G8) and causes BR WR 1 (7N7 and 6H2) to become
active.
The Base Registers (BR) are addressed in exactly the same way as memory locations, so that the even halfword, the odd
halfword, or the fullword can be written into. If the memory command is Full Word Write, a FWWRTO signal (6J I)
becomes active. This gates BRWRI to SEGWEAO and SEGWEBO, the Write Enable inputs to the Base Register (BR).
SEGWEAO is active whenever f<-WWRTO or CA300 are active, and enables writing into the most significant, or even.
halfword of the Base Register BRI6: 27. SEWEBO is active whenever FWWRTO is active or CA300 is inactive, and enables
writing into the least significant, or odd, halfword of the Base Register, BR02: IS.
24
01-078A21 R08 11/78
Ibe data inputs to BR are connected to the outputs of multiplexor MDX04:27. For fullword write operations, MDX04:27
are switched to CD04:27, which in turn are connected to MDR04:27 (Sheet 4 and Sheet II). For halfword write
operations, the data to be written into BR is contained in MDRI6:31, whether the location to be written into is odd or
even. This data is brought to the odd halfword inputs toBR16:27 from MDR16:27 through tri-state gates (Sheet 11) to
CD16:27 and through MDX16:27 to BR. This data is also routed from MDR20:31 through tri-state gates (Sheet 11) to
CD20:31 and through gates (11 L4 to II L9) to MDX04: 15 and the inputs to BR04: 15. Thus, the halfword data is
presented simultaneously to the inputs to both the odd and even halfwords of BR. it is written into whichever halfword
has an active Write Enable i.e., SEGWEAO or SEGWEBO.
4.2.4 Status Register Selection, Read and Wrik Clear. As described in Section 4.2.2, memory references to the
locations assigned to the Base Registers (BR) and Status Register (STATR) are trapped by logic shown on Sheet 7. Whenever
the address is '---40' thru '-----43', and a memory reference is started so that the flip flop at 7F8 is set, a STATO signal (7M7)
becomes active. If the memory reference is a read reference, the SDR 1 signal (7K 9) is active, and when memory is read,
MDRCLK I (7L9) also becomes active. This causes RSTRO (7R9) to become active which connects the outputs of the Status
Register flip flops IR27 S I (sheet 7) to the CD Bus by means of five tri-state gates (Sheet 11). To insure that the CD Bus is
110t being driven from the memory at the same time that it is being driven from the Status Register, the STATO signal causes
the CMC Bus (2R9) to change from a Read command to a Write command so that the memory does not drive the CD Bus.
I
If the memory reference is for a Write operation, the Status Register is cleared. SDWI (7L7) is decoded from the
micro-instruction MC field and, when STATO is active, an active condition of RQFFO caused by the memory reference
makes CSTAO active which clears the Status Register flip-flops IR27:31.
4.2.5 Memory Access Interrupts. WheneVer the Memory Access Controller (MAC) is enabled, because PSW21
is set and a privileged memory reference is not in process, certain conditions may be detected which causes the CPA to signal
the CPB that an interrupt must be taken. This signal occurs in one or more of the following ways:
1.
For interrupt conditions which occur during data references to memory, a Memory Access Interrupt (MAIO)
signal is made active (7N4).
2.
For interrupt conditions which occur during instruction fetches, an ININTO signal is made active (7N2) and
the output of the User Instruction Register UlR24:31 (Sheet 5) is forced to . FF'.
~emory
I
Access Interrupt During Data Operations. There are four conditions which causes a Memory Access Interrupt
~t signal to become active during a data operation. These are each represented by a bit in the Status Register
IR27:30, as shown in Table 9. Also shown are the conditions of BR25:26 which enable the two Write Protect intermpts,
which are described as follows:
TABLE 9. MEMORY ACCESS INTERRUPT SIGNALS
-
..
BR25:26
1.
MEANING
IR BIT
---
27
INVALID ADDRESS
28
NON·PRESENT ADDRESS
Xl
29
WRITE PROTECT VIOLATION
10
30
WRITE/INTERRUPT CONDITION
--~-
-_...
-
Invalid Address Interrupt for Data Operation. An invalid address is an address which exceeds the upper limit
of a memory segment as determined by BR04: II (the Limit field). A pair of 19-117 comparators (Sheet 6)
continually compares these Base Register (BR) bits to the eight most significant bits of the un-relocated
program address MALXI6:23 and, when an attempt is made to address a location beyond the Limit field,
LIME1 (6N6) becomes active.
As soon as the memory reference is started, DREQI (7 AI) becomes active, so that the output of an AND gate
(7Cl) becomes active if LIME! is active due to an invalid address. This enables setting of the IR 27 flip-flop
(701) and, since SIRO is inactive (high) causes NWO and NWI (7K2) to become active, which enables setting
of the MAl flip flop (7M4).
.
As soon as an attempt is made to reference memory for a data operation to the invalid address, a RQFFO signal
(7 A9) becomes active for 50 nanoseconds. If the MAC is enabled, SPROTI (7 AS) is active. Because the MAC
is enabled, SRTRO (7 AS) is inactive (high), so that the leading edge of RQFFO sets the IR27 and the MAl flipflops.
If the memory reference is for a data write, SOWI (7J5) is active, and NW1 causes CDWO to become active.
COWO (2K8) causes the Write command to memory on CMCOO:02 to be converted to a Read command.
When DREQI becomes inactive at the end of the memory operation, NWI becomes inactive. However, since
IR27 is set, CDWO is maintained active as long as both the IR27 and MAl flip flops are set and SPROTIA is
active, or until the SDW1 signal is made inactive by another type of memory reference.
OI-()78A21 R08 11/78
25
I
I
As described in Section 4.2.4, the MAl flip flop is cleared whenever a read or write reference to the Status
Register (STATR) is made. This removes the CDWO signal, allowing memory Write operations to resume. Also
attempting to write into the Status Register clears IR27, making CDWO inactive and permitting Write operations to resume.
2.
Non-Present Address Interrupt for Data Operations. When BR27 is reset, and any memory reference is made,
the IR28 and MAl flip flops are set similarly to the invalid address interrupt described previously.
3.
Write Protect Violation. Whenever the MAC is enabled and BR26 is set, the IR29 flip flop (704) and the MAl
flip flop are set if an attempt is made to write to memory. All attempted Write operations are changed to reads
by CDWO until the MAl or IR29 flip flops are reset.
4.
Write/Interrupt Condition. Whenever the MAC is enabled, BR25 is set and BR26 is reset, the IR30 and MAl
flip flops are set, but writes are not changed to reads. This allows the program to continue while the Processor
is interrupted.
J
I
Memory Access Interrupts During Instruction Fetches from Memory
There are three conditions which cause MAIO to become active during an instmction fetch. These are shown in Table 10
together with the Status Register bits which represent the condition and the Base Register bit, if any, which enables the
interrupt.
TABLE 10. MEMORY ACCESS INTERRUPTS
MEANING
IR
BR24
._----- - - -
-
27
INVALID ADDRESS
-
-
28
NON·PRESENT ADDRESS
1
31
EXECUTE PROTECT VIOLATION
1.
Invalid Address Interrupt for Instruction Fetch. The Invalid Address Interrupt for Instructions is similar to
that for data operations except that CDWO is not made active, and the MAIflip flop is not set. Instead, a latch
(7M2) is set, causing IN INTO to become active. At the same time that IN INTO is made active to the CPB,
IN INTO A is made active (5A9), presetting the VIR to 'FF'. This simulated user operation code is used in CPB
to vector to a micro-code subroutine to process the interrupt while preventing the data at the invalid address
from being executed as an instruction. The active condition of ININTO is maintained until another instruction
fetch is started, at which time ISTBO (7L2) becomes active and resets the ININT latch. IR27 remains set until
the Status Register is cleared.
2.
Non-Present Address Interrupt for Instructions. When BR27 is reset and an instruction fetch is attempted,
IR28 and ININTO are set. Subsequent operation are similar to the Invalid Address interrupt (see 1).
3.
Execute Protect Violation. When BR24 is set, and an attempt is made to fetch and execute an instruction;
IR31, ININTO, and MAIO are made active. Any subsequent attempts to write into memory are changed to
reads until IR31 or MAl are reset. The VIR output to CPB is forced to 'FF' by IN INTO and remains so until
the next instruction fetch.
4.3 Memory Reference Operations
All Processor operations which require reference to memory begin with a specification in the MC field of the micro-instruction. Table 11 shows the interpretation of MCOO:03, and lists the micro commands in terms of the effect on memory
reference operations.
TABLE 11. MICRO COMMANDS
OPERATION
INSTRUCTION READ
DATA READ
DATA WRITE
26
MC 00:03
1001
1100
1X1X
1000
1101
OX1X
·0101
Ol-07SA21 R06 5/78
4.3.1 MC Field Decoding (Sheet 2). The MC Bus MCOO:03 is connected to the CPA via front cable Connector
2" The following commands are decoded directly from the MC field; providing that PASSIA is not active, signifying that a
branch is not occurring (for conditional micro-instructions, implementation of the MC field is inhibited whenever a branch
is allowed):
CPCOOl
CPCOll
IRI
DRDWI
RHO
-
Increment MLC by the length of the last command
Increment MAR by four
Instruction Read
Data Read/Write operation
Read Halfword
The following commands are decoded and stored in quad flip flops (Sheet 2):
SDRO
SPRaT 1
SRHO
SDWO
SIRI
-
Data Read
Relocation and Protection enabled
Read Halfword
Data Write
Instruction Read
These commands are stored whenever a new Memory Reference MC field is presented to CPA (as decoded by a 19-058 gate
at 2F9) and a system clock CKI A occurs while the Processor is in Control State 0 (2H8). Since a new micro-instruction is
read into the RIR of the CPB each time the Processor 'enters Control State 0, and a system clock·occurs at the following
transition from Control State 0, these flip flops always have stored the most recently commands to memory. The decoded
function DRDWI from a 19-116 decoder (2L4) is stored differently in a tracking latch (2N9). As long as no memory
references are in operation, SDRDWI tracks the decoded DRDWl. When a memory reference is started, DREQIA (2L5)
becomes active and remains active as long as memory is being interrogated. This signal freezes SDRDW so that the
Processor cannot start another memory operation until the nI'st is completed.
The Memory Command Bus CMCOO:02 is effectively stored in the quad flip-flop at 2J7. However, these signals are enabled
by DREQI in gates 2M7, and 2M8, and are modified by STATO and CDWO from the MAC. When STATO is active, which can
only occur when the Status Register is addressed, the memory is forced to a write condition, which causes the memory to
release the CD Bus so it can be driven by the Status Register. CDWO is active only when an illegal data write memory reference is commanded, which causes all memory Write operations to be converted to Read operations, by modifying Memory
Command Bits CMCOO:Ol.
I
1.3.2 Strobes and Delayed Clock. Each memory reference is started by one or more strobes. A NAND gate
(l2B 1) accepts System Clock (CLK 1A), the Instruction Read decoded command (lRl), a CSOO 1 signal which indicates
that a new micro-instruction is in the RIR and should be executed, and PASSOA from CPB which indicates that no branch
is taking place. This combination makes ISTBO and DSTBO active. DSTBI is the input to two cascaded 100 nanosecond
delay lines (Sheet 12). The quiescent levels of the delay line outputs are low, except when a pulse which propagates down
the delay tine causes the outputs to become high. The 20 nanosecond tap is connected to a gate at 1211 together with
DSTBO. The resulting output STBO is a 20 nanosecond wide negative pulse occurring after the trailing edge of DSTBO. This
pulse is used to reset the MCLKO latch (4A3).
When DSTBO becomes active, a flip-flop at 12K2 is preset and a flip flop at 12K3 is cleared. The outputs, both high, of
these flip flops are gated in an AND-OR-Invert gate (12M3) to produce DLCKO, which becomes active at the trailing edge
of CLKl, when SIR1 becomes active, or at the leading edge of CK1A when SDRDW becomes active.
The width of DLCKO is determined by whether an instruction or a data operation is in process and whether, in each case, a
change in memory segment, and therefore the Base Registers, is required.
During an instruction fetch, SIR1 is active and DLCKO terminates when the flip-flop at 12K2 is reset. The clock for this
flip flop occurs approximately 40 nanoseconds after the trailing edge of DCLKO. If, at this time, the MLC has been.
incremented and a carry is being propagated to the four most significant bits of MLC (MLC12:15), C7Xl and CKIA
(l2B 1) become active and the two gate latch at 12F3 is set. The output connected to the D input of the flip flop is high,
and the flip flop is not reset at the trailing edge of the 40 nanosecond clock.
If MLC12: 15 are not going to change, the Base Register (BR) selection does not change, and C3X1 remains low. The latch
is reset at the end of every memory operation by P180NO' P200Nl, the D input to the flip flop remains low, and DLCKO is
terminated approximately 60 nanoseconds after the trailing edge ofCK1A.
During a data operation, ISTBO is not generated, but DSTBO and STBO occur when CKIA, STRT1, and DRDW1 are all
active simultaneously, that is, during the system clock which is to initiate a data reference to memory. At this time,
SDRDWI is made active, and DLCKO terminates when the flip flop at 12K3 is set. The clock to this flip flop occurs
approximately 80 nanoseconds after the trailing edge of DSTBO. At this time, a 4-bit comparator (6C2) is comparing the
stored segment number with the desired segment number as indicated by SUM2X 12: 15, and, if the two are different,
AEQBl at the D input to the flip flop is low. The flip flop remains reset and DLCKO continues. If the actual and desired
segment numbers are the same, AEQBI becomes active, the flip flop is set and DLCKO terminates approximately 100
mmosetonds after the trailing edge of CK 1A.
01-078A21 R06 5/78
27
,;
.1
If DLCKO is not terminated at 60 nanoseconds for instructions or at 100 nanoseconds for data references, a pulse
generated by PISONO· P200NI direct clears the first flip flop and direct sets the second flip-flop, terminating DLCKO at
approximately ISO nanoseconds and allowing time for the memory address to settle before a memory request CREQO is
activated.
If the MAC is disabled, SPROTO (l2B4) is inactive. This gates POSONI and terminates DLCKO approximately SO nanoseconds for both instruction and data references.
4.3.3 Instruction Read (see Figures SA, SB, and SC, Instruction Read), When an MC field decodes to Instruction
Read, IRI (2NS) becomes active. Since the new MC field is stored in RIR during Control State 0, the conditions required
by the four-input 19-060 NAND gate (12B I) are met when the next system clock CKI A becomes active. This causes
ISTBO and DSTBO to become active. ISTBO (1 LS) causes the IREQ flip flop (1 LS) to be direct-set, making IREQO active,
and DISTBO (1 L6) makes DREQO active.
Following the trailing edge of DSTBO, a 20 nanosecond STBO pulse is made active (l2K2).
The negative-going DSTBO sets two flip-flops on Sheet 12. Since SIRI (2K7) is latched active at the trailing edge of CKI A,
DLCKO (12R3) becomes active at the trailing edge of DSTBO (and CK I A) (1 KS). DLCKO and STBO become active at the
same time, but DLCKO remains active longer than STBO. DREQI is made active before DLCKO, so that at the trailing edge
of DLCKO (which is variable depending on addressing conditions) a preset is applied to the CREQ flip flop (1 L2). This
preset pulse is only 20 nanoseconds wide because it is gated by SHPI from a 30-019 delay line (1 N4), which is pulsed by
the leading edge of DLCKO. After SO nanoseconds, the delay line output is inverted OR3) and clocks the CREQ flip flop
off, so that SO nanosecond CREQO and RQFFO pulses are generated.
CREQO is transmitted to the memory subsystem to request a memory operation in accordance with the Memory Command Bus CMCOO:02. At the same time RQFFO is made active (lAl), causing MDRCLKO and MDRCLKI to become
active.
Whenever memory is not being referenced, DREQI is inactive. This signal holds a two-stage Johnson Counter, consisting of
two flip flops (Sheet I), reset. As soon as DREQI becomes active, this counter is free to be clocked.
The leading edge of MDRCLKI causes the COO flip flop to be set, making COOl and COOO active. COOl and COlO are gated
by CDl70 (1 G7) in a 19-062 AND-OR-Invert gate. If CDI70 is inactive (high) for RR and SF formats, the D input to the
DREQ flip flop (1 M7) is low.
When the memory has completed the operation requested, CRDYO (1A2) becomes active for SO nanoseconds. This causes
MDRCLKI and MDRCLKO to become inactive. The trailing edge of MDRCLO resets DREQO if the D input is low, which
occurs if CDI70 is high. This condition results when the instruction format that is being read from memory is SF or RR.
The trailing edge of MDRCLKO also always resets IREQO. Thus, the memory operation terminates after one halfword if
the instruction is SF or RR.
[f CDI70 is low at the trailing edge of MDRCLKO, DREQI is not reset. A delayed MDRCLK propagates through the delay
network (l D2) and produces a positive pulse at the output of the AND gate at 1K3. Since DREQI and SHPI are both
active, the CREQ flip flop is direct set and another request to memory is started. The second RQFFO makes MDRCKLO
active, and the leading edge of MDRCLKI sets the COlI flip flop (l D6). When memory places the second halfword of the
instruction on the CD Bus, Bits CD16 and 17 and the operation code in VIR are examined (Sheet 10) to determine if the
instruction format is RX3 or R12. If it is, the RX[LO signal (1 E7) is made active. When CRDYO is returned by memory,
MDRCLKO becomes inactive. If RXILO is low, the D input to the DREQ flip flop is high, and DREQO remains active. If
the instruction format is RXI, RX2, or RIl. requiring only two halfwords from memory, RXILO is inactive and DREQO is
terminated at the trailing edge of MDRCLKO.
If DREQO remains active after the second CRDYO is received from memory, the second MDRCLKI propagates'through a
delay network at I D4 producing a delayed pulse DDI (113) which causes another CREQO, and causes the memory to read
another halfword - the third halfword of RX3 and RI2 instructions - onto the CD Bus. The leading edge of the third
MDRCLK 1 causes the COOl flip-flop to reset. The AND-OR-Invert gate (l GS) decodes COOO' DREQI and causes the D
input to the DREQ flip-flop to become low. The trailing edge of the third MDRCLKO then terminates DREQO.
In addition to sequencing out the correct number of halfwords for instruction fetches, the signals developed on Sheet 1
also control loading of the data into the VIR, VSR, VDR, and MDR. Whenever an instruction is fetched, the first halfword,
on CDI6:31, is always loaded into VIR (CDI6:23), UDR (CD24:27), and USR (CD2S:31) (Sheet S). The load pulse
LDVIRO (SA3) is obtained from a gate at 4M2 and consists ofMDRCLKO gated by IREQl, which is active only during the
first halfword out of memory.
The second halfword is loaded into both the most and least significant halfwords of the MDR (Sheet 4), The 19-070
devices used for the MDR require a simultaneous low at the Clock (Pin 2) and Load (Pin 9) inputs. Loading occurs on the
trailing edge of the Load input. The Clock input MCLKO is pulsed low at the beginning of each instruction fetch by STBO
setting a two-gate latch at 4B3, and remains low until DREQOA is terminated and at least one system clock CKOA has
occurred. This never occurs until the second and, if required, third halfwords have been loaded into MDR, since DREQOA
is active during the entire instruction fetch.
28
01-07SA21 ROS II/7S
GROVO
LOUI RO MORellO
COOl
C0170
Figure 5A. Instruction Read, RR or SF Formats
O}-078A21 R03 4/77
29
PClKO
CSOOl
SIRl
ISTBO
DSTBO
IREOO
DREOO
DlCKO
CREOO
CRDYO
lDUI RO, MDRClO
COOl
COll
RX110
Figure 5B. Instruction Read, RX1, RX2 or RI1 Formats
30
01-078A21 R03 4/77
PClKO
CS001
SIB1
ISTBO
DSTBO
IRI~OO
DREOO
Dl.CKO
CREOO
CRDYO
lDUI RO, MDRClO
COO1
C01Il
Figure 5C. Instruction Read, RX3 or RI2 Format
01-078A21 R03 4/77
31
While MCLCO is low, the second MDRCLKO is gated through AND-OR-Invert gates (Sheet 4) since IREQIA (4DI) and
CCO (412) are both low, causing the data at the inputs to MDROO:31 to be accepted. The data inputs to MDR16:31 are
received from CD16:31 through MDX16:31 (Sheet 4) since LDMDRO is high at this time. However, the 19-066 multiplexors to MDXOO: 15 (Sheet 4) are disabled because the control input CDXNO is inactive. CDXNO comes from an
AND-OR-Invert gate (lIC3), is inverted at 414, and is inactive when COlI is active, which occurs durin[the second and
third halfwords. At this time, tri-state gates (Sheet 11) connect MDXOO: 15 to CDl6 :31, so that the data on CD16:31 (the
second halfword) is written into both MDROO: 15 and MDRl6 :3l.
When the third halfword is available on CD16:31, CCO is inactive and no load pulse appears at MDROO:IS. However, a
second load pulse appears at MDRI6:31, and the new data on CD16:31 is written into MDR16:31, overriding the
previously written second halfword.
When DREQOA becomes inactive and a system clock has been generated, MCLKO terminates, and the data which had been
loaded into MDROO:31 appears in the outputs of the 19-070 devices.
Instruction Format Decoding and Storage. Since a possible micro-comm-.....- - - - - - - - - - - _ . -
I
DELAY
LINE
FASTA
ASYNCHRONOUS
STOP
lOGIC
FASTB
Figure 11. Simplified Clock Circuit
OI··078A21 R08 11/78
39
The basic oscillator is comprised of the delay line driver (Gate A), the delay line itself, three gates which are used to
dynamically select the desired delay (Gates C, 0, and E), and Gate G which provides the necessary inversion for oscillations.
The oscillator can be gated by additional inputs to Gate A. One input is provided by synchronous logical conditions which
would cause the clock to stop (i.e., MFIN, or memory interlocks). The second input is from asynchronous conditions (i.e.,
external stops, manual clock control) and is enabled and latched by Gates A and B to provide proper synchronism to the
oscillator. Gate F provides the primary clock for the CPU (PClKO) and is enabled by the oscillator and the two stop
functions. An additional input is a width control from the delay line to modify the duty cycle of the primary clock.
As mentioned, the taps of the delay line are dynamically selected by Gates C, 0, and E. The purpose of this is to provide
two basic clock frequencies to the CPU. The necessity of this is caused by decoding and access time of the control state
and address gating. Since this time is normally longer than one normal clock period, the address gating is decoded so that if
the normal transition of the CPU state for the instmction is from CSOO to CSO I, both states can be used to access the next
micro-instmction. However, if any other state is entered, only one state is provided to access the next instmction and the
clock is stretched out. The logic is designed such that if either Gate CorD is enabled, that state is provided the minimum
time period; if neither is enabled, the longer period is established.
The actual logic for the clock circuits is on Sheet 13 of the CPB schematics. There are, however, two delay lines cascaded
to provide the necessary delay. It should also be noticed in the actual circuit that an eight position switch allows selection
of four different taps for each delay for marginal. nominal, and slow clock adjustments. (Note that only one switch of each
set can be closed at one time.)
The logic represented by FASTA and FASTB on Figure 11 can be observed as CSOI and CSBO (MODOOO·RIR051 +
MODOQI· RIR031), which indicates that CSO 1 is always a fast clock unless there is a control store reference
(MODOOO· RIR051) or the instruction is a Register Link (MODOO 1· RIR031 ). CS02 and CS03 are always afforded a slower
clock.
I
The synchronous stop logic is provided by the 19-062 gate (13 [3). The following logical conditions can be observed at this
gate.
CSOll· 01· IREOl. This logic is used to stop the Processor in CSOll when the decode bit is set (use the op-code of the
instmction for a control store vector) and the memory has not completed the reading of the op-code (IREQl). The lC
delay network on IREQI is used to delay the response to IREQ to provide adequate access time of the control store when
IREQ is removed.
STRTI·CSOll· MODOOO· MFINO. This logic stops the Processor clock when communicating with the other modules until
MFIN is returned.
I
INTO·DREQI·CSOOI (MCOOI + MCOll + MC021 + MC031). This gate stops the Processor clock in CSOO if it is a valid instruction (INTO), if any memory control is selected, and memory is busy (DREQl).
The remaining gate stops the Processor clock at CSOO if it is not an immediate and the MDR is selected on the B Bus or at
CS01 if the MDR, MAR, or MlC are selected as S Bus destinations and the memory is busy (DREQl).
5.3 Control Store
The CPU is directed through its paces by instmctions fetched from control store and loaded into the ROM Instruction
Register (RIR). The sequential and non sequential (branch) flow of instmctions is controlled by the CPU logic by the
control store address selection which determines where the next instruction is coming from.
A simplified block diagram of this control is shown in Figure 12.
RIR. The ROM Instmction Register is loaded at the beginning of each instruction from the control store and holds the
instruction for interrogation by the control logic while data or the next instruction is accessed. The RIR and MC field logic
is located on Sheet 11 of the schematics.
Control Store. The control store holds the micro-program of the computer. Data may also be retrieved from the control
store. The maximum addressable range of control store is 4K words. The 8/32 micro-program is contained in 1,280 words
of control store (Sheet 10).
I
RLR. The ROM location Register stores the address of the current micro-instmction. It is loaded at the beginning of each
instruction from the control store address gates unless it is an intermpt or an execute type instruction. It is not changed on
an interrupt so that the address from the interrupted sequence can be preserved if desired (Sheet 9). Execute instructions
are described in the Micro Instruction Reference ManuaL 29-438.
RlC. The ROM location Counter is used to add one to the RLR on sequential instmctions. It is the RLR + 1 loaded back
into the RlR that causes the RLR to increment. The switch input from the test aid is a second input to the RlC. When it
is desired to JAM an address into the RLR, the test aid logic clears the RLR and gates the desired logic to the RlC and
through the address gates to select the desired starting address (Sheet 9).
40
01-078A21 R08 11/78
b.
~
SBUSO
r---C-O-N-T-R-O-L---
[
t------r--
STORE
_.
RIR
INSTRUCTION
REGISTER
I-
:::>
a..
Z
::c
u
I-
RLR
LOCATION
REGISTER
3:
en
RLC
LOCATION
COUNTER
CONT130L
STORE
ADDRESS LOGIC
en
~
co
a..
-
C2X
4:1
MUX
3 ....
-
PAGE
P--
A
REGLNK+CSREF
SAMCO
SAMAl
B
SAMBL1
SEL
r-
.r--
ENB
~
co
1
r--'
2: 1
MUX
SEL
INTl
C1X
10-0..
B
::;
0'"
0
U
:E
«
en
:E
«
en
en
L
L
X
NEXT (RLC)
H
L
X
UIR/TRAP
L
H
L
PAGE
L
H
H
REGLNK+CSREF
H
H
X
ADRS LNK
2:
«
FUNCTION GATED
SELA
SELB
ENB
Figure 13A. Control Store Address Gating Low (CSA10:15)
NEXT
CSA
0-
UIR/TRAP
REGLNK+CSREF
ADRS LNK
SAMA1
co
:;(
«
en
en
L
L
NEXT (RLC)
H
L
UIR/TRAP
SELB
L
H
REGLNK+CSREF
ENB
H
H
ADRS LNK
1
4:1
MUX
.r-
~
«
FUNCTION GATED
2
3
-
SELA
SAMBH1
~
Figure 138. Control Store Address Gating High (CSA4:9)
5.5 Interrupts
I
The Model 8/32 employs a hardware priority interrupt scheme which has nine vector traps. See the Micro Instruction Reference Manual, 29-438.
There are three different interrupt mechanisms.
1.
MAl interrupt. The MAl interrupt is an immediate interrupt and cannot be disabled. It is caused by a data
read/write violation in the Memory Access Controller (MAC) on CPA. When this interrupt is sensed, the next
instruction is interrupted and a trap to 207 is taken. It is the highest priority interrupt. In addition, all
registers are inhibited from changing until the interrupt is acknowledged. This is accomplished by the
TRAP120 term in the STRT logic (14J5).
A MAl interrupt is acknowledged when MAIO (l2B8) becomes active, setting the flip-flop at l2D8. This is
syncronized by the flip-flop at 12G8 which causes the flip-flop at 12M3 to set at the transition from CSOI or
CS03. This flip-flop (12M3) being set activates the INTI signal which tells the CPU logic that an interrupt is in
process (INTI causes the CPB logic to in effect, "throwaway" the current instruction without operating on it
while it fetches the next instruction from the interrupt trap). INTI stays active until the next transition from
CSOI or CS03 when the instruction at the trap address is loaded into the RIR. The flip-flop at 12G8 is also
input to the priority encoder (12H5) where it forces the trap adrlress "7" for the interrupt vector.
42
01-078A21 R06 5/78
2.
Group Interrupts. The second class of interrupts are second priority interrupts and are enabled/disabled as a
group by the flip-flop at 12M3. This flip-flop (l2M3) may be set/reset by Module 0 instructions, and is
automatically enabled at the end of an emulation sequence (Dl' PASSO'CSAO) to field all active interrupts and
disabled at the entry to a new emulation sequence (Dl·PASSO·CSAl). Interrupts in this group are also enabled
by PSW bits as described in Section 5.7.
Interrupts in this group are interrogated and latched in registers CSOI (l2D3 and 12D6). These registers are
prevented from changing while an interrupt trap is being processed to keep the address stable to the control
store. These interrupts are then conditioned by their respective PSW bits (note that ATNO:3 interrupts are
conditioned by a PROM addressed by several PSW bits at 12D2), and activate the priority encoder 12H4. If
this device is enabled by TENO tue next CSOl or CS03 sets the flip-flop at 12M6 causing the Processor to
activate INTI and begin an interrupt cycle.
3.
Priviledged/Illegal Interrupts. These interrupts are the lowest priority interrupts and are activated only at the
end of an emulation sequence if there are no other interrupts pending. All possible instructions are programmed as privileged, illegal, or neither in a PROM addressed by the UIR (Users Instruction Register). The
output of this PROM is then interrogated at the end of each emulation sequence (Dl·PASSO·CSAl) for
privileged or illegal instructions. An exception is the MAC instruction interrupt which disables the illegal
instruction interrupt and sends an op-code of 3FF as UIR24:31, and sets the flip flop at 12M7 thus activating
INTI and causing the CPU to begin the interrupt sequence.
5.6 PSW Register
The PSW register is an architectural feature of the user level machine and is used to enable interrupts, select register stach,
and contains the Condition Code for user level branch tests.
The PSW (Sheet 5) is loaded when it is addressed as the S Bus destination. A peculiarity of the PSW is that the Condition
Code (PSW28:31) can be modified by the current instruction if it is enabled by the microcode (see Section 3.5.3) and the
module selected is manipulating the CPU flag register (SCCO active). See Section 3.5.7. This logic is accomplished by
multiplexing the S BUS which is latched in SR28:31 (4C5) at the clock's leading edge with the data to be jammed into the
Processor flag register (4E7 and 4E8) from CCO, VCCO, GCCO, and LCCO at the multiplexor (4E5). A Composite Clock
CCCLKO (4K7) is generated for the PSW28:31 latch.
5.7 Branch Control
The PSW Condition Code (PSW28:31) (4K5) and the Processor flag register (4E7 and 4E8) can be tested for conditional
branches by Module 0 instructions.
The PSW Condition Code is compared to the YD register (14B7) for the BTC and BFC tests of the user level architecture
and, input to the 8: I multiplexor (14F5) along with the Processor flag register where the appropriate input is selected by
the F field of the instruction as an input to the PASS gate (14K8). PASSO and PASSI is tested throughout the CPB logic
where pertinent for branch decisions.
5.8 A, B, and S Gating
Various registers are gated to the A, Rand S Busses by the CPB.
YSI and YDI. These registers are gated to the B Bus by the multiplexor at 2H4.
PSW. This register is gated to the A Bus by the tri-state buffers (4M4, 5M3, 5M6, and 5M7) .
.RIR20l..!.: These bits are gated to the B Bus for immediate operands (with Bit 20 extended as the sign bit) (Sheet 6).
CSDOO~
The Control Store Data Bus is gated to the S Bus for control store data references (Sheet 7).
RLC04: 15. The RLC is gated to the S Bus for link addressing (Sheet 7).
5.9 Test Aids (Sheet I).
The folilowing test aids are incorporated on the CPB board.
5.9.1 Address Match/Stop/JAM. A control store address can be selected on the three hexadecimal rotary
switches located on the front edge of the CPB board (1 B2, I B4, and I B7) which can be used to sync on, stop on, or JAM
to the RLR for a starting address. These switches are compared to the Control Store Addresses (CSA04: IS) at the
comparators (lG2, IG4, and IG7) and produce an output which is ANDed with Clock (CLKIB) and CSOOO (lJ6) to
provide a scope SYNC at TP I 0 1-7 (1 M6). The output of these switches is also routed to the RLC to provide a way to force
a predetermined address. (Sec Section 5.3.)
Ol-()78A21 R06 5/78
43
I
&1-
0
ff
mJ4.rc I-(
').. - '5 J N b LS-
;, - JAm
5.9.2 MATCH/JAM/SNGL. A rotary switch in conjunction with a push button switch (1M?, and IM9) is used
to control three flip-flops for the purpose of stopping at a selected control store address (MATCH), JAMMING the RLR to
a desired address, and single stepping the CPB clock.
When the switch is in the SNGL mode (SNGL LED bit) (1 N?), every Processor clock resets the RUN flip-flop (1 LS) which
generates KLCLKO, an input to the CPU clock circuit. A subsequent toggle of the momentary push button sets the RUN
flip-flop and allows the clock to run and generate another clock, resetting the RUN flip-flop.
When the switch is in the JAM mode, a toggle of the push button sets the JAM flip-flop (1 L?) which enables JB041 :051 to
the RLC and causes SETRLCO (1 L5) to clear the RLR.
When the switch is in the MATCH mode, an address comparison sets the MTCH flip-flop (1 L6) which activates KLCLKO in
the same manner as SNGL and halts the Processor clock. Subsequently toggling the push button resets the MTCH flip-flop
causing the Processor to run until it once again gets an address comparison.
6.
CPC GENERAL DESCRIPTION (see CPC Block Diagram Figure 14).
Processor board CPC consist of the A Stack (ASTK), B Stack (BSTK), A Address Logic (AAD), B Address Logic (BAD),
Write Clock Timing Logic (WCLK) S Buffer Register (SBUFF), and Register Set Select Logic (RSSL).
ASTK is shown on Functional Schematic 35-555 Sheet 1, BSTK on Sheet 2, AAD and BAD on Sheet 4, WCLK on Sheet 5,
SBUFF on Sheet 3, and RSSL on Sheet 3 and Sheet 5.
ASTK is a 256X32 Read/Write Register array. The 32 inputs are connected to the outputs of SBUF (SBOOI :311) and the
32 outputs (AOOO:310) are connected to the A Bus which runs along the lower back panel. There are eight address inputs
(AADOOO:040, AAD051, PSW260A, and PSW270A), a Bus Enable control (ASTKNO), and a Write Clock (WCLKOA).
h
6
S BUS
I
32
I
I
XCLK1
1
psw
MSEL
1
I
'} 1
/
RSSL
L
I'
BSEL
SBUFF
~
I
I
l
J
-
I
/
/ 32
~
B
STK
~
BAD
WCLK
/
9
~~
8/
Iii
ASEL
,J
SSEL
/
~.
32
~--~
AAD
A
STK
-..,----
32
h
A BUS
h
B BUS
~
~
Figure 14. CPC Block Diagram
44
01-07SA21 R03 4/77
BSTK is identical to ASTK, except that it is connected to the B Bus (BOOO :31 0) and receives B Address inputs
(BADOOO:040, BAD051, PSW260B, and PSW270B) and B Bus Enable (BSTKNO).
ASTK and BSTK can be individually addressed to the A Bus and B Bus, but are always simultaneously selected for loading
from SBUFF.
RSSL receives three PSW bits (PS~260, .270 and 251), th:ee MOd~ ule Selec~ bits (MSELO~0:020), an,d .three internal signals
(AKLO, BKLO, and SKLO). AKLO IS actIve whenever a Mlcro-program RegIster (MRO:7) IS selected tor the A Bus independent of the state of the PSW bits. BKLO is similarly active for the B Bus. SKLO is active whenever MR is selected to receive
data from SBUFF. The four outputs of RSSL (PSW260A, 260B, 270A, and 270B) are used as stack address bits, together
with AADOSI and BADOSI, to select one of eight sets, from 16 registers each, in ASTK and BSTK for the 16 General Registers (GRO:F).
AAD receives a S-bit A Select Bus (ASELOO 1: 041), as-bit S Select Bus (SSELOO 1: 041), PSW Bit 251 from the CPB, and
control signals from WCLK and RSSL. ASTK address bits AADOOO:040 and AAD051 are decoded from these inputs.
I
I
BAD receives a 5-bit B Select Bus (BSELOOI :041), an S2BO signal, the other inputs to AAD (except ASEL), and produces
BSTK Address Bits BADOOO:040 and BAD051.
SBUFF is a 32-bit register having inputs connected to the S Bus (SOOO:31O) and having outputs (SBOOI :311) connected to
the data inputs of ASTK and BSTK. The clock input to SBUFF is SCLKI from WCLK.
WCLK produces the timing signals for CPe. Inputs froin CPB are PCLKO, the System Clock; STRTO, the Start command
for most operations; and SCLRO, the System Clear signal. An input from the ALU is RWCO, which initiates and times
64-bit register Read and Write operations. Outpu'ts from WCLK are WSELI, WSELlA, WSELO, WSELOA, WCLKO,
WCLKOA, SODD041, and DWCO. The latter two signals are also used in 64-bit Read and Write operations.
6.1 A and B Stacks (ASTK and BSTK).
Refer to Functional Schematic 35-555, Sheets I and 2. The A and B Stacks are functionally identical, so only the
operation of the A Stack is described.
The Stack (ASTK) consists of 32 19-077 256x 1 Read/Write memories. The data input terminal of each bit cell is
connected to the appropriate output of SBUFF (SBOO1:311). Whenever the enable signal ASTKNO is active (low) and a
Write Clock (WCLKO) is made active (low), the data levels" 1" or "0", present at each data input terminal is stored in the
bit location for that cell determined by the state of the eight address lines (AADOOO :040, AA 0051, PSW260A, and
PSW270A) which are common to all 32 cells. Thus, after a simultaneous active state of ASTKNO and WCLKO, lasting at
least 40 nanoseconds, the 32-bit output of SBUFF is stored in a specific location in ASTK.
When WCLKO is made inactive (high) and ASTKNO remains active, the stored data from the selected location is presented
at the ASTK outputs which are connected to the A Bus (AOOO:310).
When ASTKNO is made inactive (high) the ASTK outputs are placed in a high-impedance state, removing ASTK from the A
Bus.
Figure 15 shows the timing of the ASTK address signals, control signals, and outputs for a Write operation at the nominal
130 nanoseconds clock period. These are described in more detail in Section 6.4.
I
6.2 S Buffer (SBUFF)
Refer to Functional Schematic 35-555, Sheet 3. SBUFF consists of eight 4-bit 19-131 registers. The data input to each cell
of each register is connected to the appropriate S Bus signal (SOOO :31 0) and the data output of eaeh cell is connected to
the appropriate data input of ASTK and BSTK (SBOO] :311).
The clock inputs (SCLKl) are derived from a NAND gate at 5C5. For 32-bit operations, SCLKI is PCLKO inverted. For
64-bit operations, two SCLKI active states are generated; the first during the first WCLKO derived from RWCO and the
second SCLKI during the subsequent PCLKO. SBUFF is loaded on the leading edge of SCLKI.
Figure 16A shows SBUFF timing for a 32-bit write, and Figure 16B shows the timing for a 64-bit write.
6.3 Stack Addressing
(Refer to lFunctional Schematic 35-555 Sheet 4 and Figure 17).
The stack addressing scheme is described in terms of ASTK. To explain BSTK, substitute B for A.
6.3.1 Read Addressing. ASTK is addressed for reading to the A Bus with ASELOO 1: 041, MSELOOO :020, PSW
251, PSW260, and PSW270. There are 9 sets of 16 registers each of which are addressed as Fixed-Point General Register (GR)
Sr~ts 0:7, and Micro-programming Register (MR).
OI-078A21 R08 11/78
45
I
PClKO
STRTO
WSElO
SSELXO
ASEl
. ~
VALID FROM ASTK
Figure 15. A Stack Timing Diagram, 32-Bit Write
VALID
Figure 16A. SBUFF Timing, 32 Bit Write
PClKO
STRTO
Figure 16B. SBUFF Timing,
,~
Bit Write
I
The register sets are addressed by means of Select Bit ASELOO 1, the Module Select Bits MSELOOO :020, and PSW Bits
25:27. When Module I is selected (MSELOOO·MSELOlO·MSEL021) ASELOOI inactive (low) selects GR, and ASELOOI
active (high) selects MR.
I
One of the eight sets of GR is selected by decoding PSW25:27 in accordance with the coding shown on Figure 17. When
MR is selected, the PS Wbits are ignored.
46
01-078A21'R06 5/78
io-----AAD*PSW
0 1 2 3 4 5261A*27,A
---ASEL~
REGISTER SET
0
FIXED POINT
1 2
'-PSW'"
3 4 MOD25 26 27
0
0
0
0
1
0
0
1
2
1 15 14 11 10 9
7
0
0
0
1
1
0
1
1
0
0
0
1
1 X
S
E
2
T
3
I
I C PIN
ADDRESS INPUTS
0
1
0
0
1
1
X
X
X 0
GENERAL REGISTER
o
X
X
X
X
1
1---'
4
1
0
0
5
1
0
1
o
MICI~O
PROGRAMMING REGISTERS (MRO:7)
X
X
X
X 0
6
1
1
0
1
0
7
1
1
1
1
1
D
D
D
0
0
1 X
X
X
X
X
0
X
X
X
X
1
I
I
X = "1" or "0"
D = Don't Care
. Use: BSEL, BAD, PSW261 B, and PSW271 B
Figure 17. Stack Addressing Scheme
The address inputs to the memory elements are developed on Sheet 4 in accordance with Figure 17. When WSELO is active
and WSELl inactive, the following logical relations are obtained:
AADOOI
AADOIO:040
AAD050
PSW261A
PSW271A
ASELOOI + M37Xl·PSW251
ASELOIO:040
M37XO·ASELOOO
M7Xl + PSW261·ASELOOQ·M37XO
PSW271·ASELOOO·M37XO
I
The enable input ASTKNO to ASTK is developed on Sheet 4 as follows:
ASTKNO
= ASELOOl·ASELOll
64-Bit Read from ASTK. When pairs of registers are to be read for Double-Precision inst.ructions (Fixed-Point divide) the
addressed register location is always odd. When the first 32-bit word is read, RWCO is active (low) causing DWCO (4G5) to be
low, forcing AAD040 high, and converting the address to the next lower even register. RWCO is then made.inactive and the
second 32-bit word is read from the addressed odd location. The 64-bit read is only implemented for ASTK. BSTK does not
respond to RWCO.
6.3.2 Write Addressing. ASTK is addressed for writing from SBUFF with SSELOOI :041, MSELOOO:020,
PSW25 I , PSW26 1, and PSW271.
Selection at the register set for writing is similar to selection for reading, except that SSELOO 1 :041 are used in place of
ASELOOI :041, and S37Xl and S7XI are used in place of M37Xl and M7Xl. S37Xl is latched up with M37Xl on the
leading edge of CSOOl'CLKl, and S7Xl is similarly latched up with M7Xl.
01-078A21 R08 11/78
47
I
I
For 32-bit Write operations, when WSELl is active and WSELO is inactive, the address inputs to the memory elements are
developed on Sheet 4 in accordance with the following logical relations:
AADOOI
AADOIO:040
AAD050
PSW26lA
PSW271A
I
SSELOOI + S37XI·PSW251
SSELOI0:040
S3 7XO· SSELOOO
S7XI + PSW261·SSELOOO·S37XO
PSW27I·SSELOOO·S37XO
The enable input ASTKNO to ASTK is developed on Sheet 4 as follows:
ASTKNO
= SSELOOI'SSELOII
Write addressing of BSTK is similar to ASTK, with the substitution of B for A.
64-bit write into ASTK (Sheet~. When pairs of registers are to be written into for Umble-Precision instructions (FixedPoint Multiply and Divide) the addressed register is always even. During the read part of the read/write sequence, RWCO is
active (low), and if STRTO is also active, the flip-flop at 503 is set. This enables the present inputs to the WSEL flip-flops
(5D3), and when RWCO becomes inactive. these flip-flops are set and WSELl A is made active. Through the mechanism
described in Section 4, a WCLKO is generated which sets the flip-flop in 5 E I and resets the flip-flop in 503.
I
The preset signal which sets WSELl from RWCO becoming inactive, is ORd with PCLKO at 5C5,
to load SBUFF from the S Bus with the first 32-bit word of the 64-bit result.
a~d
produces SCLKl,
When the flip-flop in 5El is set by the trailing edge of the first WCLKO, SODD041 is made active although SSEL042 is
inactive because of an even register selection. The next time PCLKO becomes active. a second WCLKO is generated. The
second 32-bit word is then loaded into the register location which is one higher than the addressed location. At the trailing
edge of the second WCLKO, the latter flip-flop is reset.
Figure 16Bshows the timing for the 64-bit Read/Write operation.
6.4 Read/Write Control. (refer to Functional Schematic 35-555, Sheet 5.)
ASTK and BSTK are normally in the Read mode, since WSELl and WSELlA are inactive, and WSELO and WSELOA are
active. Referring to Section 6.3, this causes ASTK to drive the A Bus and BSTK to drive the B Bus from register locations
determined by the address select lines ASEL, BSEL; the PSW Bits 25, 26, and 27; and MSELOO:02.
If the CPU micro-program requires writing data into the register stacks, STRTO becomes active and either SSELOOI (for
MR selection) or SSELOll (for GR or FR selection) but not both, becomes active. SSELXO remains inactive (high) and the
.1 inputs to the WSEL flip-flops at 5G3 are enabled. At the leading edge of the following system clock (PCLKO) from CPB,
the flip-flops are set, causing WSELO and WSELOA to become low and WSELl and WSELl A to become high. (This chan~es
the stack addressing inputs to the SSEL Bus.) The high state of WSELl is propagated down a 100 nanosecond delay line at
5E5, and after the first 10 nanoseconds, WCLKO and WCLKOA are made active for 50 nanoseconds. At the end of WCLKO,
the WSEL flip-flops are reset through the direct clear input, terminating the Write operation and returning ASTK and
BSTK to the Read mode.
The 64-bit Read and Write operations are modification to the basic read/write cycle, and have been described previously.
7.
ALU (refer to Functional Schematic 35-538D08)
The ALU is a standard module of the Model 8/32 System which implements fixed point arithmetic/logical functions. The ALU
communicates with the CPU over the A, B, S, and C Busses with all communications being completely asynchronous. The ALU
becomes active when it recognizes its address on the Control Bus. The ALU is addressed as Module Number 1. The CPU signals
a Start (STRT) and the ALU performs the function as determined from the Control Bus (FSEL). Refer to Table 15. ALU
functions may be of two types. The simple functions (fixed point Add, Subtract, and logicals) causes the ALU to immediately
return a finish signal (MFIN) as these functions are completed within 130 nanoseconds. For these instructions (refer to Figure 18), the A and B Buses are gated to the ALU chips where the function is performed and the result is gated to the S Bus.
The ALU does not generate a clock for any of these functions and all gating is performed asynchronously.
For the complex functions (Multiply, Divide, and Shifts) the ALU clock is enabled and the hardware implementation of these
instructions is sequential. For these instructions the Multiplier/Quotient (MQ) shift register, the A Latch (AL) register, and
the three shift mUltiplexors are enabled to perform the iterative operation determined by the instruction. The shift multiplexors are used to shift A or S right or left into the A latch as outlined in the ALU algorithms. For these functions, the ALU
does not return MFIN until the operation is completed and the result is on the S Bus.
I
48
01-078A21 R08 11/78
TABLE 15. ALU FUNCTION CODES
OPERATION
FSEL(HEX)
MSEL=X'1'
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
SUBTRACT
ADD
SUBTRACT WliH CARRY
ADD WITH CARRY
UNUSED
LOGICAL AND
EXCLUSIVE OR
LOGICAL OR
*LOGICAL SHIFT RIGHT
*LOGICAL SHIFT LEFT
ROTATE RIGHT
ROTATE LEFT
*ARITHMETIC SHI FT RIGHT
*ARITHMETIC SHI FT LEFT
MULTIPLY
DIVIDE
*KSIG is an extension of the FSEL field and is used to signal halfword shifts.
KSIG is only valid for shift instructions and should not be set for any other instruction type.
r-tL-.....--_ABUS
_ _ __
r--
CONTROL BUS
MSEL
FSEL
KSIG
STRT
BBUS
~,~--------~-------
]
MFIN
MSIG
RWC
CONTROL
AND
TIMING
I
I
r---
* USED IN OPTIONAL
rL--.1,
I
EXP.
I
! ALU * I
~--r-.-..I
OPERATIONS. SEE
APPENDIX 1.
I
I
I
L
_--.
I
I
I
I
I
I
---.['-1
:
I n+4 ~ __ ...JI
I -
---1.:'J
CC BUS
S BUS
Figure 18. ALU Functional Block Diagram
Ol-078A21 R06 5/78
49
7.1 Arithmetic State Register (AS) (Sheet 5).
I
For Module I operations the ALU can be in one of four arithmetic states as designated by the conditions of the State Registers ASA, ASB, and ASC.
Asaa I
ASal1
ASa2l
ASa31
= ASAa-ASBa-ASCa,
= ASAI-ASBa-ASCO,
= ASAa-ASBl-ASCa,
= ASA I-ASB leASCa,
I
The State Register is direct cleared by STRTI, therefore ASaal is the quiescent state of the ALU. Furthermore, the ALU
remains in ASaal for the simple functions (FSELaaa) previously described and only makes state transitions for the
complex functions (FSELOal) when a clock is generated. The various transitions which are possible are described in the
ALU Algorithms section. The State Register is implemented in J-K type logic which is tempered with a clock (activated
only for FSELOa I). The transition diagram is shown in Figure 19 and the logic determining each transition is listed in
Table 16.
STRTO
;;
o
-I
UJ
en
LL
Figure 19. ALU State Transitions
I
7.2 ALU Flow Charts and Algorithms
I. Simple Functions (FSELaaa)
These arithmetic/logical functions do not require that the ALU clock be generated; they employ combinational logic to
perform the required function. When one of these functions is to be performed, ALSTRTI is used to gate MFINa back to
the CPU, relying on the basic CPU clock frequency to allow the operation to be performed by the hasic arithmetic/logical
elements and the result to appear on the S Bus before being strobed into the destination register. Shown in Figure 20' is a
timing diagram for the immediate response functions with respect to the CPU clock. Note that STRTa is precisely the
width of one CPU clock cycle or approximately 130' nanoseconds. Upon receipt of STRTa, the ALU immediately (:::::: 15
nanoseconds) returns MFINa to prevent inhibiting the CPU clock. As the CPU latches the S Bus on the leading edge of the
active clock, it is necessary for the ALU to complete its function and present the results to the S Bus within 70'
nanoseconds. On the trailing edge of the active clock, the CPU switches control states and releases STRTa. It is during this
next control state that the CPU writes the result into the destination register.
50'
a l-a78A21 RO'6 5/78
TABLE 16. STATE REGISTER LOGIC
TRANSI.
TlON
ASOOl
TO
ASOll
ASA LOGIC
ASB LOGIC
ASC LOGIC
COMMENT
J = ZSHFTl
ABORT SHI FT IF SHI FT COUNT IS ZERO.
1-'
ASOOl
TO
AS021
UNCONDITIONAL TRANSFER IF NOT
J = EASO'ASOOl
FLT. PT. ADD/SUB.
r-'
AS021
TO
ASOll
J = ACRYl
K
= ACRYl
J = ACRYl
SHIFT COMPLETE
---- r--------------..- - - - -...- .. -----..
r-'
AS021
TO
AS031
J = ACRYl
K
-.
FIX PT. MULT./DIV. COMPLETE.
= FMDO
.
-FIX MULT/DIVIDE-FmST HALF OF RESULT
AS031
TO
AS011
t--.
AS011
TO
ASOOl
_..- - - - - - -
WRITTEN INTO DESTINATION REGISTER.
K
RESET
:0
STRTl
= GRWCO'AS031
RESET = STRTl
RESET TO AS001 WHEN CPU REMOVES
RESET = STRTI
STRT1.
,
90n5
WRITE CYCLE
CPUCLK
STRTO
MFINO
I~-
CPU LATCHES S BUS
S BUS
CC BUS
Figure 20. ALU Bus Timing - Immediate Response Functions (FSELOOO)
Ol-078A21 R06 5/78
51
The fixed point simple functions are Subtract, Add, Subtract With Carry (SWC), Add With Carry (AWC), logical AND,
logical Exclusive OR, and logical OR. When the instruction to be performed is an Add/Subtract, the carry state into the
arithmetic element must be generated. This is done by the gate (9B8) 'whose output is labeled CIN310. Since the 19-067
device performs a subtraction by internal 1's complement addition, a carry must be generated for Subtract. Similarly, a
carry in is generated for Add With Carry (A+B+l) and suppressed for Subtract With Carry (A-B-l).
I
2. Complex Functions (FSELOOI)
Shift Instructions
I
The ALU can perform both halfword (l6-bits) and fullword (32-bit) shifts. When a shift is to be performed, the word to be
shifted is taken from the A Bus and the shift count is taken from the B Bus (B27:31). In ASOOI, the A Bus is transferred to
the AL register. If a halfword shift is to be performed, KSIG I is set, and the most significant 16-bits of the AL register are
inhibited by killing the clock to those devices. The shift occurs in AS021 , AL being continuously loaded from the proper
shift multiplexor. When the correct number of shifts have occurred, ACRYI forces the transition to ASOll. During
ASOll, the contents of the AL register are transferred to the S Bus, the flags are generated onto the CC Bus, and MFIN is
returned to cpu. Following are Shift Functions Flow Charts and Shift Function algorithms. The flow charts and algorithms
are complementary and may be !lsed together or individually, whichever is more convenient.
SHIFT FUNCTIONS FLOW CHART (SECTION 1 OF 3)
o
(FULLWORD)
1 (HALFWORD)
A BUS 16:31-.AL 16:31
0 - - " ALOO: 15
B BUS 28:31 .. COUNTER
A OO:31 ......ALOO:31
B 27:31.COUNTER
INCREMENT
COUNTER
BY 1
(LEFT)
52
ALOO:31--.S00:31
MFIN ACTIVATED
WHEN STRT IS
REMOVED,
GO TO ASO
o
(RIGHT)
01-078A21 R06 5/78
SHIFT FUNCTIONS FLOW CHART: SHIFT LEFT (SECTION 2 OF 3)
(HALFWORD)
SHIFT AL
LEFT 1 PLACE
SHIFT AL
LEFT 1 PLACE
YES
a. AL31
AL16.AL16
AL17.CCCa
ALaa .AL31
AL.Ol.ALOa
a.AL31
AL17.AL16
AL16.CCCa
a -AL31
ALOl -ALao
ALOO ... CCCO
a +AL3l
ALOO-ALOO
ALOl .... CCca
Ol-078A21 R06 5/78
53
SHIFT FUNCTIONS FLOW CHART: SHIFT RIGHT (SECTION 3 OF 3)
(HALFWORD)
SHIFT (AL)
RIGHT 1 PLACE
SHIFT (AL)
RIGHT 1 PLACE
YES
AL31 IS
LOADED INTO
ALOO
AL16-AL16
AL31-CCCO
O-ALOO
AL31-CCCO
ALOO-ALOO
AL31-CCCO
54
Ol-078A21 R06 5/78
The Shift Algorithms arc:
if KSIGO, AOO:31-ALOO:31
if KSIGI, AI6:31-ALl6:31, O-ALOO: 15
B27 :31 --ACNTO 1:05
ASOO I -AS021
if AeRY), AS021--ASOII
ACNT~I-ACNT
ALOO 30-ALOI 31
If ROTATF, AL3I--ALOO
if KSIGO
{
if LOGICAL, O-ALOO
if ARITH., A LOO-ALOO
if FSEL030
ALl6:30--AL17:31
if LOGICAL, 0-ALl6
{
if KSICI
if ARITH., AU6-ALIG
AL02:31-ALOI :30
ALOO-'-AUI
if ROTATE {
ALOI-ALOO
if KSIGO
O--AUI
if LOGICAL {
.
ALOI-ALOO
if ARlTH
if FSEL031
if KSICI
O-AUI
{ ALOO--ALOO
ALl8:31_AL.l7:30
O-AUl
if LOGlCAL
{ ALl7--ALl6
{
if ARITH.
O-AUI
{ ALltI·-ALl6
ALOO:31- SOO:31
MFIN-I
Fixed Point Multiply
The ALU performs signed multiplication on two 32-bit operands. The multiplicand is transferred from the A Bus to the MQ
register during ASOOI and the multiplier remains on the B Bus throughout the operation.
If the multiplicand is positive, a product is formed by adding the multiplier to the shifted product conditional upon the multiplier. If the multiplicand is negative, the product is fonned by subtracting the multiplier from the shifted partial product
conditional upon the 2's complement of the multiplicand.
Multiplication is accomplished by examining each successive bit of the multiplicand as it is shifted out of the MQ register. A
32-bit product is formed by shifting either AL (the partial product) or S (=AL~B) back into AL and into the MQ conditional
upon M1, the multiplicand bit. The logic gate for M I is located at 7N6. If SUM I is set (multiplier positive), M1 is simply
MQ311. If SUMO is set (multiplicand negative) M I becomes the 2's complement of the multiplicand. The 2's complement
fo the multiplicand is taken by detecting the first MQ bit which is set and thereafter complementing the remaining MQ bits.
This is accomplished by the complement flip-flop (717) and the M I logic gate.
Inherent in the Multiply algorithm is a look ahead feature which permits deciding in advance whether to add and shift, or
just shift the partial product. If Ml is set, AL is added to B and the sum is shifted into the AL and MQ registers. If MI is
reset, the: AL is shifted back into the AL and MQ registers. Since more time is required to perform hoth an add and shift
(Ml) the ALU clock is divided by two when Ml is set and permitted to run at its basic speed when not set (see Section
7.3 ALU Clock).
When tht! Multiply is completed, the most significant portion of the result is written into the destination register in AS031
and MQ is transferred to the AL. In ASO 11, the least significant portion is written into the destination register.
OI-078A21 R06 5/78
55
FIXED POINT MULTIPLY FLOW CHART (SECTION 1 OF 2)
(A BUS) .... (MO)
o ----+ (AL)
0--.. COUNTER
MULTIPLICAND IS ON A BUS
MULTIPLIER IS ON B BUS'
NO
SUM1 = 1
ADD
SUM1 = 0
SUBTRACT
(AL) __eo_ (S BUS)
(MO)--+ (AL)
REMOVE RWCO TO
WRITE INTO REG.
STACK. GO TO AS1.
(AL) - - + (S BUS)
MFIN ACTIVATED.
WHEN STRT IS
REMOVED, GO TO
ASO.
56
Ol-078A21 R06 5/78
FIXED POINT MULTIPLY FLOW CHART (SECTION 2 OF 2)
(SUBTRACT)
(ADD)
USE MO IN
2's COMPo
FORM
SHIFT (AL) & (MO)
RIGHT 1 PLACE
ALOO ..... ALOO
60 ns CLOCK
(AL) - (B BUS)
SHIFTED
RESULT ...... (AL)
SHIFT (MO)
RIGHT 1 PLACE
IF LI KE SIGNS,
o -ALOO
IF UNLIKE SIGNS,
1 ....... ALOO
120 ns CLOCK
01-078A21 R06 5/78
SHIFT (AL)&(MO)
RIGHT 1 PLACE
ALOO -ALOO
60 ns CLOCK
(AL) + (8 BUS)
SHIFTED
RESULT ...... (AL)
(SHIFT (MO)
RIGHT 1 PLACE
IF LIKE SIGNS,
o - AlOO
IF UNLIKE SIGNS,
l ...... ALOO
120 ns CLOCK
57
The algorithm for Multiply is:
AOO:31-MQOO:31
0-ALOO:31
O-ACNTOI :05
if AOOO, I-SUM I
irAOO\. O-SUMO
ASOOI -AS021
AS021
if AeRY\, AS021-AS031
ACNT
~I-ACNT
if SUMl,
AL~B
if SUMO, AUB
{
{
SOO:S30-ALOI :31
ifMI
(AOO<±> BOO)'ZSUMO-ALOO
MQOO:30-MQO 1 :31
S31-MQOO
ALOO:30-ALOI :31
ifMO
ALOO-ALOO
MQOO:30-.. MQOI :31
AL3I-MQOO
ALOO:31-S00:31
MQOO:31-ALOO:31
if GRWCO, AS031 -ASO 11
ASOII
ALOO:31-S00:31
MFII\_I
Fixed Point Divide
The Fixed Point Divide algorithm is implemented by subtracting the divisor from the shifted dividend to determine if it is
greater or not. If the dividend is determined to be smaller than the divisor, the quotient digit for that test is made to be a
zero, and the dividend is shifted left again to repeat the process. If the dividend is determined to be larger, the quotient
digit for that test is made to be (lone and the difference, shifted left, is stored as the new dividend. In the implementation
of signed divide, if the two operands are of unlike signs, the subtraction is performed by the addition of the unlike
operands and the 1's complement of the quotient is accumulated. When the complemented quotient is formed, it is
corrected to the 2's complement in ASOll.
An obstacle in performing signed division using complementary arithmetic arises when the intermediate dividend is a
negative number and both the intermediate quantities (the absolute value of the dividend - divisor) and the remainder equal
zero because the logic does not detect the quotient digit of 'one'. When this case arises, the computed result = true
quotient -1, with the remainder equal to the divisor. To detect this case, a flip-flop (RZRO) (7Ft) monitors this condition
and causes a correction cycle in ASO 11.
Because of the difference in ~crling of the divisor (263) and the dividend (2 31 ) and th~ fact that both the quotient and
remainder must be scaled (2 ), an extra division cycle is performed in AS03I to compute Q31. To properly scale the
remainder, the last summation is inhibited from shifting. Moreover, if the absolute value of the Q31 digit is '1', the correct
remainder is on the S Bus during the first cycle of AS031 and remains there throughout AS031. Should the absolute value
of the Q31 digit be '0', the correct remainder is in the AL register, and ALU control is modified to force the transfer of AL
to the S Bus.
The least significant portion (remainder) of the result is written into the destination register in AS031, and the most
significant portion (quotient) is written into its destination register in ASOIl.
58
OI-078A21 R06 5/78
FIXED POINT DIVIDE FLOW CHART (SECTION 1 OF 4)
LOAD AOO:31- MQOO:31
(LS FULLWORD)
ACTIVATE RWCO
LOAD AOO:31 -ALOO:31
(MS FULLWORD)
DIVISOR ON BOO:31
O-COUNTER
NO
SUM1=Q
SUBTRACT
SUM1=1
ADD
(SUBTRACT) Q
OI-078A21 R06 5/78
59
FIXED POINT DIVIDE FLOW CHART: LIKE SIGNS (SECTION 2 OF 4)
536
(NEGATIVE) -
+ (POSITIVE)
SUBTRACT
(AU-(B BUS)
SUBTRACT
(AU-(B BUS)
(AU
SHIFTED S BUS SHIFT (MO) LEFT
ONE PLACE
M031
IF FSTCNT _
DFLT
•
SHIFT (AU & (MO)
LEFT ONE PLACE
0 -M031
MOOO AL31
SHIFT (AU & (MO)
LEFT ONE PLACE
0 - M031
MOOO_AL31
SHIFTED S BUS . . (AU
SHIFT (MO) LEFT
ONE PLACE
M031
IF FSTCNT- DFLT
•
PERFORM ONE DIVIDE ITERATION
USING SAME FLOW AS IN AS2 EX·
CEPT DO NOT LOAD AL
o
REMAINDER IS IN A LATCH
(AU
• S BUS
STORE IN REG. STACK
REMOVE RWCO
(MO)
• (AU
GO TO ASl
60
REMAINDER IS LAST RESULT
ON S BUS
STORE IN REG. STACK
REMOVE RWCO
(MO)
• (AU
GO TO ASl
01-078A21 R06 5/78
FIXED POINT DIVIDE FLOW CHART: UNLIKE SIGNS (SECTION 3 OF 4)
537
(NEGATIVE) -
+ (POSITIVE)
ADD (AL) +
(B BUS)
SHIFTED S BUS (AL)
SHIFT MO LEFT
ONE PLACE
o
.. M031
MOOO _
AL31
IF FSTCNT -
ADD (AL) +
(B BUS)
SHIFT (AL)&(MO)
LEFT ONE PLACE
1 - M031
MOOO AL31
SHIFT (AL)&(MO)
LEFT ONE PLACE
1 - M031
MOOO AL31
SHIFTED S BUS
SHIFT MO LEFT
ONE PLACE
0 - M031
(AU
MOOO AL31
IF FSTCNT DFL T
DFLT
PERFORM ONE DIVIDE ITERATION
USING SAME FLOW AS IN AS2 EXCEPT DO NOT LOAD AL
o
REMAINDER IS LAST RESULT
ON S BUS
STORE IN REG. STACK
REMOVE RWCO
(MO)
• (AL)
GO TO AS1
01-078A21 R06 5/78
LAT~J
REMAINDER IS IN A
(AL) SBUS
STORE IN REG. STACK
REMOVE RWCO
(MO) (AL)
GO TO AS1
61
FIXED POINT DIVIDE FLOW CHART (SECTION 4 OF 4)
LIKE SIGNS
(All
• (S BUS)
MFIN ACTIVATED.
WHEN ?TRT IS
REMOVED. GO TO ASO.
UNLIKE SIGNS
(AL)+1
• (S BUS)
MFIN ACTIVATED.
WHEN STRT IS
REMOVED •. GO TO ASO.
The algorithm for Fixed Point Divide is:
AOO:31--MOOO:31
GRWC-O
if AooffiBOO, SUMO-I
if AOO-
0
11
0
:E:
t)
v2
5
1
1,
t)
0
C/l
8:
START
TIMER
t--
nON
PWR
t
9
/5
B(L)
B(H)
AIL)
GENERATION
MCR( L)
L---.....J--'-'------;ay "";;1a a a
b
TO CPU
~~
A BUS (16:31;
B BUS (16:31)
:J
iii
S
FSEL(OO:03)
i:
~
8
cry
10
B(H)-D(H)
KSIGTj
)
D BUS
ROM
CONTROL
CYCLE COUNTER 1
B(H)-o(L)
~
«
~r
li
A_D
''lL...._....-_..J
16
I
lJ
DR MUX
16
h
'"
1
......
, ---"
R
3
u
0;-
-I
t)
U)o
Z
t)
I-
«
~
l-
~
2
GENERATION
I
,1
4
ATN(TTY)
11---+_5_ _ _ _ __
t
2 [,
D BUS (16)
o
I
j
1"
00
>
0
0
0
ACK DECODE
AND
6
--.J
N
I
POUT AND
STRAPS
D R ECE I VERS . t-t-C.::;L:o;K-=--_----l
D MUX
B(L)-o(L)
EPF
5
J
0
•
t "I
r
L
TIMING CONTR
FOR
MUX BUS FCNS,
CYCLE COUNTER
l--------+---+--I--,~)
{o
CA31
MCR AND
STRAPS
CONTROL
LINES
AIH)
L-.=.SE.=.L:,;:S.::.LO:=...----.:I_ _---.! TRI-STATE
MONITOR
T
~
I---
nYAND
DISPLAY
CONTROLLER
Figure 21. IOU Block Diagram
f-------.-J
H
DISPLAY
CONSOLE
L....
r
CHASSIS
fRONT
TERM STRIP
I
I
II
The ACK function generates a single cycle on the D Bus during which it activates one of four ACK lines and gates 10-bits
of interrupting device address from the D Bus onto the S Bus.
All Multiplexor Channel functions are covered in detail in Section 10.
9.1.2 Byte Manipulations Functions. These include: STBR, LBR, STB, LB, and EXB (see Table 18). These
functions do not activate the D Bus since only selected bytes are gated from the CPU's A and B Buses back onto the CPU's
S Bus. This is achieved by ROM controlled S Bus Multiplexors. See Section 11.1 for more detailed description of these
functions.
9.1.3 Auxiliary Functions. These include: SMCR, CMCR, LDWAIT, THW, POW, and POUT (see Table 18).
The SMCR and CMCR functions provide a means for Sensing and Clearing the Machine Control Register (MCR).
The LDWAIT function controls the ON/OFF indicator light on the Display Console.
The THW function generates MSIG according to the state of the HW (Halfword) Test line.
The POW function releases the System Oear relay.
The POUT function gates 4-bits on the B Bus (27 :31) to a set of board stakes for external signaling purposes.
All auxiliary functions are covered in more detail in Section 11.2.
9.2 Machine Malfunction and Power Fail Hardware
Space is also provided on the 8/32 IOU board for a Machine Control Register (MCR), which stores machine trouble
conditions; a Power Monitor and System Initialize circuit, and a Start Timer. This additional IOU hardware is covered in
Section 10.11.
10. MULTIPLEXOR CHANNEL (MUX) BUS
10.1 Multiplexor Channel IOU
The main function of the IOU board is to provide a means for communicating with up to 1,023 peripheral device
controllers and interfaces, including Display Console and Teletypewriter. IOU accomplishes this by generating Multiplexor
Channel D Bus from the CPU busses whenever it is addressed by Module Number 2 and D Bus. operation is requested by
the CPU.
This byte of halfword oriented input/output system consists of 33 lines:
16 Bi-directional Data lines (also used for address).
6 Control lines (to identify the contents of the data line).
2 Test lines.
4 Interrupt lines.
4 Acknowledge lines (daisy-chains).
1 System Initialize line.
The 4 Interrupt lines terminate on the CPU-B (CPB) board and the 4 Acknowledge lines originate on the IOU module. The
Initialize line is available to all system modules, controllers, and the local memory. Only one Interrupt line and one
acknowledge daisy-chain is provided on a given I/O back panel. A single instruction from the CPU contains the 10 bit
device: address, the encoded function and up to 16 bits of output data when needed. The MUX Bus generator provides
single or multicyc1e operation to address the device controller, transmit the decoded function and send or receive over the
16 Bi-directional Data lines and synchronize the exchange. The normal byte or halfword operation consists of address
cycle, followed by a data cycle. During a Read/Write Block sequence, the address cycle is not used. For halfword functions
(e.g., RDH or WDH) with a byte oriented controller, two data cycles are used to transfer the halfword.
The following definitions apply to the lines in the MUX Bus:
16 Data Lines (DOO: 15)
The 16 Bi-directional Data lines are used to transfer one 8-bit byte or one 16-bit halfword between the CPU and the device
controller. Data Lines D08: 15 are used for byte transfer. The to-bit address sent from the CPU (or returned on an
Acknowledge operation) uses Data Lines D06: 15.
011-078A2l R03 4/77
69
Control Lines (Manipulated by the Processor)
SR
Status Reguest. The Processor signals the last addressed device controller to send the device status to Data
Lines 008: 15, followed by a SYN.
DR
Data Request. The Processor signals the last addressed device controller to present data to the Data lines,
followed by a SYN. (One byte or halfword of data is sent depending on whether the device is halfword or
byte oriented.)
DA
Data Available. The Processor signals the last addressed device controller that the data on the Data lines is
valid. The device controller accepts the low byte or the entire halfword and responds with a SYN.
CMD
Command. The Processor signals the last addressed device controller that the command byte on Data Lines
DOS: 15 is valid. The device controller accepts the command byte and responds with a SYN.
ADRS
Address. The Processor signals that it presented lO-bits of address on Data Lines 006:DI5. The device
controller that recognizes its address responds with a SYN.
If no device controller recognizes its address in approximately 30 micro-seconds, the IOU generates a False
SYN (FSYN).
CL070
This line is activated by the IOU whenever any of the following occur:
1.
2.
J.
4.
The Initialize key on the Display Console is depressed.
The key-operated ON/OFF/LOCK Power Switch on the Display Console is turned OFF.
The primary power input falls below minimum operating level.
Auxiliary initialize inputs are activated (e.g., from LSU).
Test Lines (Manipulated by device controllers).
HW
Halfword. The Halfword line is activated by a halfword oriented device controller whenever it is
communicating normally with the Processor (when its address flip-flop is set).
SYN
Synchronize. This signal is generated by the device to inform the Processor that it has properly responded to a
Control line.
Interrupt and Acknowledge Lines.
ATN 00:03 Attention. Any device controller desiring to interrupt the CPU, activates one of the four ATN lines and holds
that line until the corresponding ACK signal is received.
ACK 00:03 Acknowledge. The CPU acknowledges one of the four interrupts by asking the IOU to perform an ACK
function. The IOU in response activates one of the four ACK lines, selected by 2-bits of the B Bus (30 :31 ),
each of which can feed a daisy-chain priority wiring pattern. The responding device controller presents its
address on Data Line D06: IS, followed by a SYN signal.
Initialize ·Line
SCLR
System Gear. This is a metallic contact to ground that occurs during Power Fail, Power Up or Initialize. The
current carrying capability of the contact is limited. External circuits should not be connected directly to it.
Refer to the bus buffer or buffered I/O channel for these applications.
NOTE:
All Control lines, except ACK are connected in parallel to all devices.
These lines are activated by the Processor in response to an external
interrupt. The ACK line is connected in series with all devices. If no
interrupt is pending in the first controller when the ACK signal
arrives, the signal is passed on daisy-chain fashion to the next controller, and so on until it is captured by the interrupting controller.
See definition of ACK.
All busses are the false type (i.e., a low voltage level is active and a high voltage level is inactive.)
Each 'device controller is permitted one TTL load on any of the Data lines, Control lines, Acknowledge line, or the
Initialize line. Furthermore, each device controller is permitted one OR tie onto a Data line, Test line, or Interrupt line.
The controller bus driver must be either a high-power open-collector TTL gate or the tri-state equivalent.
A maximum of 16 I/O device loads can be driven from the IOU's unbuffered MUX Bus including Selector Channels, Bus
Buffers, Bus switches, and Sub-Channel Controllers.
70
01-07SA21 R03 4/77
10.2' Multiplexor Channel Timing
Input and output operations on the MUX Bus use request/response signaling. This allows the system to run at its maximum
speed. Timing for typical input/output operations are shown on Figure 22. Detailed timing is shown on Figures 23 and 24.
On output, the CPU places signals on Data Lines D08: 15, followed by an appropriate Control line signal. This Time delay
(tl) varies but it is guaranteed to be at least 100 nanoseconds. When the device controller has received the Data line
information, it sends the SYN signal to the CPU which terminates the Control line signal. The SYN Time delay (t2) should
be only long enough to guarantee proper reception of the output data. The Control line/Data line removal time (t3) is
guaranteed to be at least 100 nanoseconds. The SYN removal time (t4) should be minimized since the CPU does not
proceed until the SYN signal is removed.
It should be noted that the times shown are defined for signals on the MUX Bus. Within a given controller, one signal may
pass through more gates than another signal and these additional delays must be considered.
For the input operation, the CPU activates one of the input type Control lines and the currently addressed device
controller gates onto Data Lines D08: 15-keeping Time deiay (tl) at a minimum. Tne SYN Time delay (t2) must guarantee
that all the returned data is on the Data lines, considering the slowest data gates and the fastest SYN gates. The CPU
removes the Control line signal when SYN is received, with a minimum Time delay (t4) of 100 nanoseconds. The SYN
removal time (t3) should be minimized since the CPU does not consider the operation complete until the SYN signal is
removed. When the Control signal is ACK, Time delay tl includes the cumulative contention circuit delays for all the
controllers, between the responding controller and the CPU.
008'15 PROCESSOR ...- DEVICE
t6
ADRS, DA OR CMD CONTROL LINES
SYNC DEVICE -
t1}
t3
t5
12
t4
t.-.
PROCESSOR
t5
t2
-----
1 SEE TEXT
-
-------
t3
~
100 ns MINIMUM
..J_
t4
J
t6
350 MINIMUM.FOR ADDRESS. ALL OTHERS HAVE NO MINIMUM,
BUT DROP AFTER SYNC IS RETURNED.
(A.)
OUTPUT
()11 SR OR ACK CONTROL LINES
L
008:15 DEVICE -PROCESSOR
SYNC DEVICE t1
t2
t3
}
'.
PROCESSOR
SEE TEXT
~
~
t2
t4
t4
100 ns MINIMUM
(B.)
Figure 22.
OI-078A21 R03 4/77
INPUT
Multiplexor Channel Timing
71
534
~~~~~~~~~~~-Tl·~~~~~~~~~~~~~~~~~~i·~~~~TI'Fim~h~~~~,-,~·I~·~~~~~-n~~~~~~~~~i
~~~
__________
~,~G
____________________________________
..
__
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__
'j
~~~~')
I..
b
I
, ,
1
:
I
7/
1
I
,,1
I
1
I.
..
.~--_,~c_----------_________~I__n:
c
-""""",,,","-;--~-+-----""-:-----/'.,,~<~--------------------------------------------~
72
I
I
I", ,
\. \
--------~~,~----+---~--+I--~~~\~--~~
::~ffiRO
\
I
I
'
\ \
11; ,
\
:
I
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'1/ \ \ \.:~ \ \
!
I;'! ! \
Y
:
_ _ _ _ _ _ _ _~_ _ _ _~:~'_ _ _ __ _
~I.---=c-----l.ot-I.~.....::d=---------..I.~_-----.::e:....-~_,~..c;c~
'
~_I
//':
/I I
/
J~
T
II
,
.......
~! I ( ',\
f
~ \ i.' / \'i~\
~4----+------I~h
..I
I "" I
;1
II
c
: ' !:
____
\
~~r
,
V
/
1\
J
/ /
w-~~/
I--'
V
7';J--,
\
I
fp
_I
:
-----'/1--
I
:
L~
1'<
~-';" 'I - ,- -r:'~F- :
J
IJ/ 1/ :;P=-r-----+-
rI
-4_':
:.l--r-,- _- _
----+-
+---+--/
"
,
V/
"I
\~:~)~j----~--~'~'--~~
\IT; tr--------..-\~"..,~/
,u
~------t~--:f.A----I------+---J:
J\ \
~--+----:?~-+-----I-~~,\~\-"o-----'--~+-----I\~"
r------------~f
r
I
\"
W
=/
L
__
"=:
V~ r_f'.J_",--~f-
Figure 23. Multiplexor Channel (Input) Timing ADRS and SR/DR
01-078A21 R06 5/78
535
1 4- 4
---------Tl-AddressCycle
-----------11-1---------
T2-First Data Cycle
--------·----eot:1
~~RT~~-4------~~~:--------------------------------~i--------~~~:----------------~r--~~ ~~--'----------
:~: ~ 'iJ'l-----F:r-'f-,'========================::~=~i======;==~:::==01====~:::::::::~~::--iG---"-:-\~~.J--,-(-f-.~~~-_-_-_-_-_-_-_-_-_TB' \r-
V\
=!"
I,
'
:::\~~ y~:
:: J
,\
~
'\
.~
l
\ 7~ ~
L
I
r
~
~
r/
\
\
\
I \
\
.
0 \~~~ I~~~ -;~~~f~"i~\~ 'r~'\~~~ I~~) Y'f--Jr,\--t----'\r------~ 1[ k\ \ ~
1 f ~~ -\ \
r
(
ADRSO
J
,
\
"
\
\
~:~(,l_____\~--~r
-SYN-O- - - + - + - - - f , 'r-",
DSYNl
LESYNl
(A
1~~~-,--4\---~TI~~~~-\~-II~~-~\\~'r--~~\\~\\-+~--~/-r-+,/+-711~,,~~r\-y::\~~~~~~~~~~\
:TE=Sy.l.l.LN:':";"l====~~:-_-_-
\
\
/
/
i
i
I
\"
I
I
------J'rr-------
\
Ir--/-+---I'),"---+-:
~\
I
--t--------j---+---i~--t'L~1P
~~_-+-j
--+--f'.'
I
1
\
/
J
...,,-f",.A-_ _ _---+ _ _ _...,..,
#
J
J
/1/
'
J
'
~F-"-+1
__
1
1
-+1-+-_ _ _ __
J,
~::2_D-,OJD=:'\(!====~I-~.- ~-/J,:\~~~~~:I~~~:~j/t-t+_I:--------:--~~~--T-\":_\-""'-+-~-\~.\~~~~::~\.A::\-'\~~_tJ---t-----T"1\~-+-1
-:,,:?+~·/:~~-I'_
1
\
-
, \,
~KSYNl---+-~/~
J' \
\
~ ~_ \
Y
I" ~ • ~
~:
;;~
1
YL
I/o
-----t~--4---~---4--------..,rL-+J-----:-I--J" .Y
..,
~-----f-'
:MF:'N~O~---------~~~~~:~:~(----------------------------------------~i.--~:'~-.~i------------~~ ':~--_pl
KDRl
'F-'_ _
a = Asynchronous response of the controller to the activating of the address line.
b = Asynchronous response of the controller to the activating of the CMD or DA lines.
e = Time required by the processor to remove STRTO after sensing MFINO.
Ol-078A21 R03 4/77
=======
-+-_-+-tJ
'.I )
_ _ _ _ _ _ _ _ __
Figure 24. Multiplexor Channel (Output) Timing ADRS and CMD/DA
73
NOTE
With a SYN delay of 50 nanoseconds, device controllers must be
designed to accept a minimum width of 170 nanoseconds on all
Control lines and Acknowledge signals except ADRS, which is guaranteed to be 350 nanoseconds minimum. The SYN delay in the
device controller may be increased to effectively lengthen the
Control line signals if it is absolutely necessary. It is essential to
realize that the CPU does not proceed until the SYN signal is returned and removed. While the slower data transfer rates may not
affect a particular controller, the overall system performance is
degraded. Furthermore, if a device controller fails to respond with a
SYN signal within 25 to 35 microseconds, the CPU aborts the I/O
operation.
10.3 Multiplexor Channel and Multiplexor Operations (MUX)
Operational and circuit description also refer tn Section 9.1.1. This section covers the circuits which implement the D Bus
operations.
10.3.1 .MUX Channel Operation. MUX Channel is a byte or halfword oriented Input/Output system which
communicates with up to 1,023 peripheral device controllers or interfaces. When I/O control is addressed and given a D
Bus function code, it creates one, two, or three MUX Channel operations. The halfword functions (RDH/WDH) have a
single data cycle when the HW (Halfword) Test line is active and two data cycles when a HW is inactive (communicating
with byte-oriented controller).
10.3.2 Typical Output Case. (All cycles: Processor .... Devices). A device controller receives to-bits of address
(over Data Lines D06: 15) during the address cycle (Tl). In the following first data cycle (T2), an 8-bit Command byte. or
one byte of data (over Data Lines D08:l5), or a Halfword of data (over Data Lines DOO:15) is sent to the device.
For Halfword (HW) functions the cycle counter generates a second data cycle (T3) if necessary, in which case an additional
byte of the Processor data is sent to the device over Data Lines D08: IS (see Section to.3.1).
10.3.3 Typical Input Case. (Address Cycle: Processor-Device. Data Cycles: Device -Processor). A device
controller receives 10 bits of address (over Data Lines 006: 15) during the address cycle. In the following first data cycle,
an 8-bit device Status byte, or one byte of device data (over Data Lines D08:15), or a halfword of device data (over Data
Lines DOO: 15) is gated on the Processor's S Bus.
For Halfword (HW) functions, the cycle counter generates a second data cycle if necessary, in which case an additional
byte of the device data is sent to the Processor (see Section 10.3.0.
) 0.3.4 I/O Function Gating. Table 19 shows IOU function gating specifications.
A single instruction from the CPU contains the device address, the encoded function, and up to 16 output data when
needed.
D Bus functions may be performed with or without address cycle depending on the state of FSELOO.
KSIG is used to specify register type operations or to distinguish between Halfword (HW) functions (RDH/WDH) and some
non D-Bus operations (STB/LB).
For byte designation used in Table 19 refer to the following information.
B(H)
B(L)
A(H)
A(L)
S(H)
S(L)
D(H)
D(L)
MCR(L) =
MCR(H) =
refers to Bits
refers to Bits
refers to Bits
refers to Bits
refers to Bits
refers to Bits
refers to Bits
refers to Bits
MCR08:15
MCROO:07
16:23
24:31
16:23
24:31
16: 23
24:31
00:07
08: 15
from
from
from
from
from
from
from
from
the
the
the
the
the
the
the
the
corresponding
corresponding
corresponding
corresponding
corresponding
corresponding
corresponding
corresponding
B Bus.
B Bus.
A Bus.
A Bus.
S Bus.
S Bus.
D Bus.
D Bus.
Note that Bits 00: 15 of the Processor's A, B, and S Busses do not have an appearance on the IOU module (see block
diagram Figure 21). The contents of SOO: 15 is zero when bytes are gated to S(m and/or S(L).
74
01-078A21 R03 4/77
10.3.5 MUX Bus Generation. (Circuit Description and Internal Timing.) The circuits which generate the D Bus
and the companion Control Test lines are described in this section. Also a detailed description of one output function
(WDA), and one input function (RDHA) are used to explain the operation of the MUX generation circuits.
1. MUX Generation Circuits. As seen on Figure 25, there are five general circuit groups for MUX generation:
a.
b.
c.
d.
e.
Input circuits.
Cycle counter.
Contro1line logic and bus drivers.
D Bus gating and receiving logic.
Internal Timing Differentiation and control logic.
~
TCl
RDW[)Hl
FSLQ(>OA
FSLO()1A
ElEJEJ
DELAY LINE
[~ ~
SYNOA/l
FSLO :30A
DSYN 1
DSTR Tl
CYCLE
COUNTER
(SHEET 5)
I
FSLOOOA
FSL030A/1A
DFST 0/1
DFST
I
LESYN
I
I
DSTRTO
IKSYNI
B El
INTERNAL TIMING 01 FFERENTIATION
AND CONTROL LOGIC
(SHEET 5)
I=LSY NO
A.
B.
M
0
8
-I
(,!)
en
U5
w
u..
a;
«~
;::
~
~
0
~
U
~
~
DBENl
DECODE
LOGIC
RDWDHl
ex:
Cl
(,!)
a:
en
(,!)
CYCLE
GATING
LOGIC
0
~
:2
t!)
t!)
u
Cl
;::
::J
0
Cl
t!)
U;
2
Ci
t!)
a::
Cl
«
t!)
~
«
a..
ACK
GENERATOR
o
en
a::
Cl
«
~
,...o
o
-I
U
__________________________~~ ____________________________- J
MULTIPLEXOR CHANNEL CONTROL LINES
c.
Figure 25. Multiplexor Circuit Generation Description
01-078A21 R03 4/77
75
INPUT CIRCUITS
GSTRT1
D~[D~STRTO
DBEN
- - } SHEET 2
~:~1____________
)SYNO
----------------~._--4
1 DSYNl
KSYNl
KDO
SHEET 5
~rH-w-O----~.----D~H~W~l~----D~H~W~O~A~-------------
~
D.
S BUS ROM
CONTROLLERS
AND ENABLE
LOGIC
S(Ll AND S(
MUXES
co
(T2 and T3)
DCKL1
co
HIGH
SHEET 6
T2 and T3)
DCKL1
KDO
SHEET 6
CLDRO
FSELOll :031
KSIGl
CA311
HWl
KAl
KB1
D BUS
RECEIVERS
LOW
ENT30
o BUS
GATING
ROM
CONTROLLER
4
A(22:31)
B(16:31)
D BUS
GATING
LOGIC
(SHEET 4)
~------------~--~--.-.---~
E.
Figure 25. (Continued) Multiplexor Circuit Generation Description
76
Ol-078A21 R03 4/77
The two edge triggered D type flip··flops KA and KB, connected as a Johnson Counter, together with the KT flip-flop
(5N5) make up the cycle counter circuit. The sequence starts with DFSTO setting the KA flip-flop (5J6). When there is no
address cycle, OFSTI and FSLOOOA (5K5) also set the KB flip-flop (5L6). The counter advances on the trailing edge of the
DSYNI (5E7) signal which is stretched (if necessary) on the ADRS, CMD, and DA cycles. This insures that any byte gated
to the D Bus remains for at least 100 nanoseconds after the associated Control line signal is removed. The sequence stops
when the Terminate flip-flop (KT) (5N5) is set and the MFIN line to the CPU is activated. Operation of the KSYN flip-flop
(5G8) which provides the SYN stretch, is described later.
A timing chart for the cycle counter is shown on Figure 26. From the idle time period TO, the counter is preset into period
Tl or X2 depending upon the presence or absence of an address cycle. The sequence normally terminates at the end of T2
unles;, a halfword operation with a byte oriented device requires a second data cycle, T3 (ENT30) (5N7).
DFST.:.1_ _~
DSYN..:.11_-+_ _ _ _ _ _ _ __
KA1 _ _......
....-------.~~----.....,
KB1
-- -
~---------------------------~
O===_TO__
~~~------T-1------~I----~~~T2--------+--------T3--------+
~
SKIPT1
WHEN THERE IS NO
ADDRESS CYCLE
7
Figure 26.
3
TO
Cycle Counter
All D Bus operations begin when DBENI is gated by the GSTRTI signal (1 G8) to produce the DSTRTO and DSTRTI
signals (5G9). These signals in turn are used by the STRT timer (14H8), the cycle counter, and the timing control circuit.
The SYNO Test line is the main source of timing in the request/response signalling system used on the Multiplexor Channel.
It must be carefully terminated and deglitched before being presented to the cycle counter and timing control. The leading
edge of the Test line is gated by KDI (5G6) to direct set the OSYN flip-flop (5E7). When the Control line signal to the bus
is terminated, the KD flip-flop is cleared and the Test line is now connected to the clock input of the 0 type, edge
triggered, DSYN flip-flop where the trailing edge clears the flip-flop. Once the OSYN flip-flop has been set or cleared,
ringing or noise near the edges of the SYNO signal is ignored. The trailing edge of SYNO (5A6) is extended on output
operations by the high KSYNI signal (5A6). This is described in detail later.
TIle Halfword Test line (HWO) (512) produces the signals HWl and HWOA which control data gating on the D Bus and
indicate to the Multiplexor Channel circuits whether a byte oriented or halfword controller is in use.
The 10-bus drivers (Figure 25C), are the source of the Multiplexor Channel Control lines. Inputs are cycle gating and
function decoder signals. GDOUTI (6M2) is active for output functions. GDINI (6K3) is active for input functions.
Both contain the intra-cycle timing signals KCI (6N2) or KDl (6L2). When data is placed on the D Bus for ADRS/CMD, or
DA operations, the KCl pulse provides the Control line timing, delayed 100 nanoseconds from the beginning of the cycle.
For ACK, SR, or DR operations, the non-delayed KOI pulse gates the Control lines. Both KCl and KOI are removed 100
nanoseconds after SYNO is received, in accordance with Multiplexor Channel timing requirements. Only one out of four
ACK !lines is made active during any given ACK functions. The 19-129 3: 8 decoder (602) selects the active ACK line
according to the state of Bits 30 and 31. The signal CL070 (l4K7) goes low active when Primary Power Failure (PPFl) is
detecte~ high, or INIT, or POFF go high.
01-078A21 R03 4/77
77
The D Bus consists of 16 Bi-directional Data Lines terminated on the IOU board.
The 19-134 tri-state D Bus drivers multiplex lO-bits of A Bus and 16-bits of B Bus onto the D Bus. Their tri-state outputs
are tied together in two groups to form D Bus high and D Bus low. Only one output for each D Bus line is enabled at a
time, the others are in the high impedance state. This is achieved with the help of the D Bus ROM controller (4D3). Unlike
the static selection of the S MUX controller, the D Bus ROM controller address selection (hence enabling of D Bus drivers)
changes on every cycle of the sequence (KAI and KBI are used as address select onputs).
The 19-071 edge triggered D latches, used as D Bus receivers. load on the low to high transition of the clock leads DCKLI
and DCKHI (6A5). The high byte register normally receives data from DOO:07 during period T2 (KAI and KB I) gated
through the two-to-one MUX by ENT30 (6H6) in the high state. For the double data cycle, ENT30 is low active so that
the first byte on D08:15 enters both DROO:07 and DR08:15 during T2. The second byte on D08:15, during T3, is
registered in DR08: 15 only to overwrite the first byte. Oock logic for DCKLl and DCKHI (6A2) uses the common term
KB 1· DSYNI. FSL030A which is active for all input functions, including ACK during periods T2 and T3. Final gating with
KDO loads the registers at the moment the selected Control line signal is removed; i.e., about 100 nanoseconds after the
beginning of the SYN signal when the Data Lines have settled. The Data Register outputs feed the S MUX and the CC
MUX.
The timing and control circuits provide the intra-cycle timing and SYN stretching features mentioned in earlier sections.
These circuits consist of six edge triggered 1/K flip-flops, a two stage counter, an R/S flip-flop, a 100 nanosecond tapped
delay line, and the interconnecting logic. TIuee of the flip-flops, DFST (5E5), LESYN (5G2), and TESYN (5E6) detect the
transitions of the DSTRTO and DSYNI signals respectively, and feed the delay line R/S flip-flop combination.
The TB flip-flop (5B4) is set by a low signal on Terminal 1, 2 or 4. A low signal on Terminal 9, 10, or 12 clears the
flip-flop. When a momentary set pulse is applied, the high-to-Iow transition at TBO travels down the delay line emerging
after X nanoseconds as TCO (5C2) to clear the flip-flop. This produces pulses TCO and TC 1 which are X nanoseconds wide
and start X nanoseconds after the set TB pulse (where X is the tap delay plus the flip-flop transition times). Using the 50
nanosecond tap (Tem1inal 13 of the line), X is approximately 50 nanoseconds and the trailing edge of TCI occurs 100
nanoseconds after the set pulse. When the set pulse is long enough to still be present after the end of TCO, TBO again goes
low to generate another pulse; i.e., the circuit acts like a gated oscillator. As seen on the timing charts which follow, both
the single and multi-pulse modes are used.
The timing chart on Figure 26 shows a data output operation (CMD or DA) with an address cycle. The sequence starts with
period Tl when the KA flip-flop is set. At the end of the first SYN pulse, the KB flip-flop is set and period T2 starts. The
end of the second SYN pulse clears the KA flip-flop and sets the KT flip-flop. With KTO low, gating to the D Bus/Control
lines is suppressed (6Ll) and the pulse generator is killed (5C3).
On both address and data cycles, the data bytes must be on the D Bus at least 100 nanoseconds before the Control line
signal starts and must remain active for 100 nanoseconds after the Control line signal is removed. In addition, the Control
line must remain active for 100 nanoseconds after SYN arrives. The width of the ADRSO Control line pulse must be at
least 350 nanoseconds. This insures that the Address flip-flop on a controller, separated from the CPU by one or more bus
buffers, can be reliably cleared even with a fast SYN response from a local controller.
TIle DFSTI lead sets the Delay Line flip-flop (TB) (5B4) if it is either an output data cycle (FSL030A low) (5A4) or an
address cycle (FSLOOOA low) (5A4). The KD flip-flop (5G6) is always set by DFST. Flip-flop KC (5G5) toggles set at the
end of TCI since its J input DSYNO and direct clear (KDI) are both high. KCl sets the KSYN flip-flop (5H8) and gates the
Control lines as described earlier. The LESYN flip-flop (2G3) sets on the leading edge of DSYN and sets the TB flip-flop
again. The KD flip-flop toggles clear on the first TCI pulse after its K input goes high and in turn direct clears the KC
flip-flop. For non-address cycles, the K input to the KD flip-flop (KDKI) goes high as soon as SYN is received, the next
TCI pulse clears the KD flip-flop after 100 nanoseconds. On the address cycle (period Tl with the KB flip-flop cleared),
the TCI pulses are fed to a two stage 10hnson Counter, flip-flops KX and KY (5M8). The KDKl input to the KD flip-flop
is held low until after three TCI pulses have been registered on the KX and KY flip-flops. The next TCI pulse clears the
KD flip-flop. In this manner the minimum width of KCI and the ADRSO signal are equal to 300 nanoseconds plus the SYN
return delay (KDK I = KXO· DSYN I). The KSYN flip-flop is cleared 100 nanoseconds after the KD flip-flop is cleared since
its K input (KDO) is high when the next TCI pulse arrives. KSYN (5A5) forces SYNI and DSYNI high as long as the
KSYN flip-flop is set. This insures that DSYNI and SYNO remain active for at least 100 nanoseconds after KCI and the
Control line signals, gated by KCl, are ended. A fast SYN response from a device controller is not able to terminate the
cycle prematurely and violate the timing rules for the D Bus.
Note that the LESYN flip-flop remains set until the first TCI pulse after the KC flip-flop is cleared. This produces the
multi-pUlse mode of the delay line; i.e., a group of TCI pulses at 100 nanosecond intervals. Also note that while the KD
flip-flop is not used directly for Control line timing, it is part of the logic for the KC and KSYN flip-flops.
78
01-078A21 R03 4/77
The TESYN flip-flop (5E6) sets on the trailing edge of the DSYNI signal and sets the TB flip-flop again if an output data
cycle is required (FSL031 A) (5B5). The KD flip-flop is direct set by TESYN. Timing for the output data cycle is similar to
the ADRS cycle with two exceptions. First, the KX and KY flip-flops are not used to stretch the Control line signal and
second, a double data cycle may be generated for the WDH operation to a byte oriented device. During the T2 SYN pulse,
the logic that sets the KT flip-flop (5N6) also produces a low level on SKTO (5N3). This causes the TESYN flip-flop to
ignore the end of SYNI (since both the J and K inputs are low) and the TB flip-flop is not set. When a double data cycle is
neededl, the set KT logic does not become active until period T3. The TESYN flip-flop sets on the end of the T2 SYN
signal and thus pulses the TB/delay line circuit for timing control during period T3. It also applies to the ADRS and DR
operatJlons.
Figure 23 shows timing for a data input operation (SR or DR) with an address cycle. The TB flip-flop is set with DFST
since KCl is needed for Control line gating during the address cycle. It also applies to the ADRS and DR operations. The
KX and KY counter insure the minimum width of the ADRSO signal. TESYN sets the KD flip-flop at the end of period Tl
but does not set the TB flip-flop. KDI gates the Control lines for the input bytes. The KC and KSYN flip-flops are not
used on the data cycles. A double data cycle is produced for the RDH operation to a byte oriented device.
For non-address functions, the sequences start with period T2 since the KA and KB flip-flops are both set with DFST. The
data cycles on Figures 23 and 24 are essentially the same.
Timing for the ACK function is shown on Figure 27. It consists of a single data cycle (T2). TI1e KC and KSYN flip-flops
are not required. The TB flip-flop and the delay are pulsed only by LESYN to time the removal of the Control line signals.
DSTIRT1
---~
--_........ ,
DFsn
LESYN1
-----~~-_r~
TBO
TC1
-----r-------+--~
SYNO
DSYN1
--~~.---------KA1 _ _~_
KT1 _ _ _•_____________________________
MFIIN1
--------------------------------------------~
* One of ACKOO:03 selected by B30:31
Figure 27.
OI-078A21 R03 4/77
Multiplexor Channel Timing, ACK
79
On all timing charts, the KT flip-flop generates S Bus and CC Bus gating and eventually the MFINO signal. This restarts the
CPU clock causing the removal of STRTO, which in turn removes GSTRTI, DSTRT, and the MFIN signals.
A group of clear signals insures proper circuit states for initialize and other operations. CLRAO (SN6) is low for SCLROB
low or any non-D Bus operation (DSTRTI low). It clears the cycle counter and kills the pulse generator. CLRBO (SC8),
used by DFST and TESYN, cannot use DSTRTI for clearing due to a possible race condition when the DFST flip-flop
toggles set. It combines SCLROB, TCl/KDI (as per timing charts), and MFINOA a copy of the MFINO generated by the
IOU board.
CLRCO (5H8) is low whenever the IOU cycle timer is inactive (period TO). CLRDO (2C3) uses CLRCO or TCI /KCO (as per
timing charts) to clear the LESYN flip-flop.
2. Output Operations (WDA). (See Section 10.3.2 and Figures 2SE and 24.) A detailed description of the WDA
(Address, Write Data) operation is used as an example of output operations.
The cycle timer must generate two cycles to execute the WDA instruction. The address cycle (TI) starts when DSTRTO sets
• the DFST flip-flop (see Section 10.3.5). The 10-bits of address must be placed on the 0 Bus. This is accomplished by
the D Bus. controller outputs YI, Y2, Y3, and Y4 equal to HHHL whenever address cycle (Tl) is detected, see Figure 28,
which shows all possible D Bus gating situations for' WD and WDA instructions. The ADRS Control line is activated
approximately 100 nanoseconds after the beginning of the address cycle to inform the interrupting device controller that
the D Bus contains 10-bits of address. The trailing edge of KSYNI (SYN stretching signal) (SAS) starts the data output cycle
(see Figure 24), in which either:
O-D(H) }
{ B(H) ...... D(L)
for CA311=L
or
B(H)-D(H)} for CA31=H
{ B(L)-D(L)
has to be gated onto 000: IS. See Figure 28 and Table 19.
The DA Control line is activated about 100 nanoseconds after the beginning of the output data cycle (T2) to inform the
interrupting device controller that the output data is settled on the 0 Bus. Interrupting device controller latches the data
and responds with a SYN. The trailing edge of the KSYN (SYN stretching signal) (SAS) sets the KT flip-flop which
generates MFIN (Module Finished) signal.
3. Input Operations (RDHA). (see Section 10.3.3 and Figures 25E and 23.) A detailed description of the RDHA
(Address, Read Data Halfword) operation is used as (1n example of output operations. The cycle timer must generate three
cycles to execute the WDA instruction. See Figure 23. The address cycle is identical to the one described in Section 2.
I Output Operations (WDA). The trailing edge of KSYNI starts the first data input cycle (T2), in which 000: 15 is latched in
the D Bus Receivers DROO: 15. The Data Request (DR) Control line is activated at the start of the data cycle (T2) to signal
the controller to put the data on DOO: 15 and activates the SYN line. If HWO is active (Halfword oriented controller) only
one input data cycle is necessary. If HWO is high (byte-oriented controller) then it sends the most significant byte in T2
and the least significant byte (always via D08: IS) in T3, the second data cycle. The latching of the D Bus in the D
Receivers occurs approximately 100 nanoseconds after SYN is received (to insure settling the data).
The contents of the Data Receivers must be placed on SI6:31. This is accomplished by two ROM controllers which control
the multiplexing on the S Bus. See Figures 2SE and 29.
II. BYTE MANIPULATION AND AUXILIARY FUNCTIONS
11.1 Byte Manipulation Functions
(STBR, LBR, STR, LB, and EXB - see Tables 19 and 20.)
These functions do not activate the MUX Bus since there is only need to gate selected bytes from A and B Busses onto the
S Bus. Page 2 of the 35-539D08 schematics show the gating onto the S Bus High. The 19-132 tri-state S Bus 2: 1
Multiplexors are tied in two pairs of three each, to allow for effective 6: I Multiplexing (see Figure 21 block diagram).
Only one output of the three tri-states is enabled at a time. Enable and select inputs are generated from YI to /4 outputs
of S(H) ROM controller and from STCI line active for non-D Bus operations. The same concept is used for generating S
Bus low. (Page 3 of the 35-S39D08 schematics.) ROM controller's S Bus-generation for STB instruction is shown on Table
20.
Enable inputs of the S MUX low are used for MFIN generation for the case of byte handling operations (SMFIN is on Page
7 of the 3S-539D08 schematics). These lines also become active for D Bus and SMCR operation so that the additional
signals (SMCRO and STCI) (7G7) are needed to insure that SMFINO (7H8) goes active only for five byte handling
opera tions.
80
01-078A21 R06 5/78
TABLE 19. I/O MODULE FUNCTION GATING
HEX. EQUIV.
OF FSEL
~CTIONO
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
FSEL
M
l?
«u
S
0/1
X
0/1
X
0/1
X
0/1
X
X
X
X
X
X
X
X
X
0/1
X
0/1
X
0/1
X
0/1
X
X
0/1
X
0/1
X
X
X
X
X
X
X
X
X
X
X
X
0/1
X
0/1
X
X
X
X
X
X
X
X
X
X
X
X
X
0/1
X
0/1
X
X
X
X
X
U5
~
I
1 2 3
RD
0 0 0 o 0
RDR
0 0 0 0 1
0 0 0 1 0
WD
0 0 o 1 1
WDS
SS
0 0 1 0 0
SSR
. O. 0 1 0 1
OC
0 0 1 1 0
OCR
0 0 1 1 1
*RDH
o1 0 0 0
STBR
o 1 0 0 1
*WDH
0 1 o 1 0
LBR
0 1 0 1 1
ACK
0 1 1 0 0
LDWAIT o 1 1 0 1
SMCR
o 1 1 1 0
CMCR
0 1 1 1 1
RDA
1 0 0 0 0
RDRA
1 0 0 0 1
WDA
1 0 0 1 0
WDRJl.
1 0 0 1 1
1 0 1 0 0
SSA
SSRA
1 0 1 0 1
1 o 1 1 0
QCA
OCRA
1 0 1 1 1
*RDHA
1 1 0 0 0
STB
1 1 0 0 1
1 1 0 1 0
*WDHA
LB
1 1 0 1 1
THW
1 1 1 0 0
EXB
1 1 1 0 1
POW
1 1 1 1 0
POUT
1 1 1 1 1
CA31=1
OR
HW=l
CA31=0
OR
HW=O
OTHER
DESTINATION(H) DESTINATION(L) DESTINATION(H DESTINATION(L
D(L)~S(H)
B(H)---+S(H)
D(U-'S(L)
B(L)-S(U
ZERO-CC
D(L)-S(L)-ZERO-S(H)
ZERO-S(H)
D(U-'S(U
B(H)-D(H)
ZERO-D(H)
B(L)-D(L)
B(U-D(L)
ZERO-CC
B(H)-D(H)
8(H) ---+D(H)
B(U-D(U
Bill-DILl
D(L)---+S(H)
B(H)-S(H)
D(L)-S(U
B(L)-S(U
D(12:15)-CC
ZERO-S(H)
D(L)-S(U
ZERO-S(H)
D(L)-S(l)
D(12:15)-CC
B(H)-D(H)
B(L)-D(L)
ZERO-D(H)
B(HL-D(L)
ZERO-CC
B(H)----+D(H) 1-- B( U-=--"D( L)
B(H)---+D(H)
B(U-D(L)
D(H)---.S(H)
D(L)l~S(H)
D( L)2--.S( L)
D(U-.S(U
ZERO_CC
A( L)'':-'S( L)
B(H)-S(H)
B(H)---+S(H)
A( Ll---+S( U
B(L)-+D(L)
B(H) ---+D(L) 1 B(U-D(U2 B(H)-D(H)
ZERO_CC
ZERO-S(H)
B(L)-S(L)
ZERO-S(H)
B(LI-S(U
D(H)_S(H)
ZERo--CC
D(H)~S(H)
D(L)-S(U
D(L)-S(L)
-.--B(16)-FWAIT
NA
NA
NA
NA
MCR(H)-S(H)
MCR(12:15~CC
MCR(L1"S(L)
MCR(H)-S(H)
MCR(L~(L)
NA
NA B(27:31)CLEARS MCR(11:15)
NA
NA
SAME AS RD AND RDR BUT PRECEDED BY ADDRESS CYCLE
[A (22:31~D (06:150.
SAME AS WD AND WDR BUT WITH ADDRESS CYCLE
SAME AS SS AND SSR BUT WITH ADDRESS CYCLE
~
SAME AS OC AND OCR BUT WITH ADDRESS CYCLE
SAME AS RDH BUT WITH ADDRESS CYCLE
A(L)~Sn{[fBTL)_S(U
B(H) _S(H)
A(L)-S(U-SAME AS WDH BUT WITH ADDRESS CYCLE
B(L)-S(U-A(H)-S(U
ZERO-S(H)
NA
HW-MSIG
NA
B(H)_SiL)
B(L)---.S(H)
B(L)---.S(H)
B(H)-S(U
NA
RELEASE SCLR RELAY
NA
NA
NA
B(27 :31 )-CAB LE
NA
NA
NA
NA
ZERO-S(H)
TABLE 20 .. STB INSTRUCTIONS
ROM ADDRESS SELECT IDENTICAL
FOR BOTH S BUS CONTROLLERS
1
FUNCTION
;;
0
.-1
2
;;
3
..J
UJ
l?
(J)
(J)
LI..
LI..
~
fJ)
(J)
I.L
LI..
H
L
L
6
5
DATA TO BE
GATED ON
S(H) = S(16:23
M
0
N
..J
UJ
H
7
0
..J
UJ
UJ
4
U5
H
M
~
«
U
I
L
L
DATA TO BE
GATED ON
S(l)::S(24:31)
S(H) ROM.S
OUTPUTS
12
SEL
Y1
A
Y2
10
B
Y3
9
C
Y4
H
L
L
H
11
A(L)-S(H)
H
H
L
L
H
L
H
H
H
L
L
H
H
L
S(U ROM'S
OUTPUTS
12
SEL
Yl
11
A
Y2
10
B
Y3
9
C
Y4
L
L
H
L
L
L
H
L
H
L
L
H
H
L
L
H
B(L)-+S(U
H
L
L
H
H
L
H
L
STB
B(H)-+S(H)
H
H
L
01-078A21 R03 4/77
L
H
H
H
A(L)-+S(L)
H
L
H
L
81
IU
W
....J
w
(f.)
~
W
0:
z
1=
u
z
0
e
e
«
...
0
....J
w
W
I-
N
e
....J
w
M
e
....J
w
(f.)
CJ)
CJ)
LI.
LI.
LI.
(!)
en
~
«
...
M
<5
~
J:
~
...
~
l-
en
0:
w
z
::>
0
15
1
2
3
4
7
6
5
u
DATA TO BE GATED
ON 0(00:15)
w
....J
::>
LI.
WOANO
WOA
l-
(f.)
o BUS CONTROLLER
u
>u
INPUTS
Yl
Y2
Y3
Y4
12
11
10
9
p BUS CONTROLLER
OUTPUTS
L
L
H
L
L
L
L
L
TO
DRIVERS IN H-Z
H
H
H
L
L
H
L
L
L
L
H
T3
WILL NEVER OCCUR
X
X
X
H
H
H
L
H
L
H
H
H
X
---
L
L
H
L
L
L
H
L
T1
L
L
H
L
L
L
H
H
T2
A(22:31 r--0(06:15)
0-0 100:05)
O-O(H)
B(H)--O(L)
L
L
H
L
L
H
L
L
TO
DRIVERS IN H-Z
H
H
H
H
L
L
H
L
L
H
L
H
T3
WILL NEVER OCCUR
X
X
X
X
H
H
H
L
H
L
H
H
----
A(22 :31 )-0(06: 15)
0-0(00:05)
O--O(H)
BIH)-O(L)
L
L
H
L
L
H
H
L
T1
L
L
H
L
L
H
H
H
T2
L
L
H
L
H
L
L
L
TO
DRIVERS IN H-Z
H
H
H
H
L
L
H
L
H
L
L
H
T3
WI LL NEVER OCCUR
X
X
X
X
L
L
H
L
H
L
H
L
T1
H
H
H
L
L
L
H
L
H
L
H
H
T2
A(22:31)-0(06:15)
0_0(00:05)
B(H)_O(H)
BIU __ OIL)
L
H
L
H
L
L
H
L
H
H
L
L
TO
DRIVERS IN H-Z
H
H
H
H
L
L
H
L
H
H
L
H
T3
WILL NEVER OCCUR
X
X
X
X
L
L
H
L
H
H·
H
L
T1
A-O
H
H
H
L
T2
B(H)-O(H)
BIU--OIL)
L
H
L
H
L
L
H
L
H
H
H
H
--
Figure 28. 0 Bus ROM Controller Data Gating for WD and WDA
82
Ol-078A21 R03 4/77
ROM ADDRESS SELECT
IDENTICAL FOR BOTH S BUS
CONTROLLERS
FUNCTION
§
...J
0...I
LU
LU
N
0
cry
...I
0
...I
LU
LU
(/)
en
~
....
«
U
:J:
<.::l
M
~
DATA TO
BE.GATED ON
S(H) = S(16:23)
S(H) ROM
CONTROLLER
OUTPUTS
C
B
Y1
A
Y3 Y4
Y1
Y2
DATA TO
BE GATED ON
S(H) = S(24:31)
.J
S(L) ROM
CONTROLLER
OUTPUTS
B
C
SEL
A
Y4
Y1
Y2
Y3
~
(/)
(/)
u.
u.
1
2
3
4
7
6
5
12
11
10
9
12
11
L
H
L
L
L
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
H
L
H
L
L
L-
L'
L
H
u.
RDH
10
9
DR(Ll--S(L)
DR(H~(H)
L
H
L
L
L
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
H
H
L
H
L
L
L
L
L
H
H
H
L
L
L
L
L
L
H
L
L
L
L
L
H
H
H
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
L
H
L
L
L
H
DR(Lj.S(L)
DR(Hj.S(H)
RDHA
H
H
L
L
L
H
L
L
H
L
L
H
H
L
L
L
H
H
L
H
L
L
,.-
Figure 29. ROM Controller Data Gating for RDH and RDHA
11.2 Auxiliary Functions
(SMCR, CMCR, LDWAIT, THW, POW, and POUT - see Table 19).
'Ihese functions are described in this section. The SMCR function provides a means for sensing 16·,bits of MCR, (Machine
Control Register) see Section
The SMCR function is decoded by a 3:8 decoder (7B7), MCRII :15 is placed on the CC Bus by 2:1 CC Bus MUX
(7E2). The SMCRO line also generates MFIN and the strobe for Condition Code. The contents of MCROO: IS is gated onto
the SOO:15 by the 19-132 S Bus Multiplexors (ROM controlled) shown on Pages 2 and 3 of the 35-539D08.schematics.
The DMCR function is decoded by the 19-129 3:8 decoder, whose CMCRO output enables the four least
significant bits of the B Bus (7B2) to clear selectively four MCR registers. (Ones in B27 :31 clear the corresponding MCR
registers. )
The LDW AIT function is decoded by the 19-129 3: 8 decoder, it controls the indicator light on the Display
ConsoJ:e (ON or OFF) according to the state of B 16.
The THW function is decoded by the 19-129 3:8 decoder (7B7) it generates MSIG according to the state of the
HW (Halfword) Test line.
The POUT function is decoded by the 19-129 3 :8decoder it gates four bits (B27 :31) to a set of board stakes for
external signalling purposes. These signals may be wired to the front chassis terminal strip by adding optional wires to the
Display Console connector at the IOU board. The MFIN signal to the CPU is delayed by a timer to set' the output pulse
width at 1.0+0.3 microseconds.
The POW functions releases the System Clear relay, (see Section 10.11).
01-078A21 R03 4/77
83
12. DISPLAY CONTROLLER
The display controller has access to the CPU via the Multiplexor Channel D Bus and the I/O control in the same manner as
other peripheral device controllers. The display controller provides a means for reading the contents of all the system
registers or any main memory location and transferring the data to the Display Console.
Data and programs can also be manually entered from the Display Console to the controller and then to the CPU. The
display controller signals the CPU directly via the Display (DSPLY) interrupt.
12.1 Addressing Logic
The Display Console device address is wired as (X'OI '). The D Bus lines D08: IS are buffered and inverted to create double
rail Data Lines (Sheet 8). Two more bits of the D Bus (06 :07) are used directly in address decoding logic on Page 9 of the
35-539D08 schematics.
The decoded Display Console address activates BI line (9H4), which sets the ADB flip-flop (9M4) at the trailing edge of
the ADRSO Control line signal. B1 also generates ADSYNBO (I OK4) which generates the SYN signal and clears the CATN
flip-flop (1 OF6).
12.2 Data Output
The byte of data transferred between the display controller and the Display Console Makes use of 8-bidirectional lines
SDOO:07 (8H4). Data is placed on this SD Bus when the DAGBO line is active and is gated to one of the four display
registers in the Display Console, by one of the load signals, LA or LB (13J 5). LA and LB generation logic is shown on Page
13 of 35-534D08 schematic. Two one-shot timers (l3E2 and 1312) insure that the loading signals conform to Display
Console specifications. The XA flip-flop is reset by RSTO=ADRSI' INCRO' B 1.
12.3 Data Input
XC flip-flop (13E8) controls the SHIO and SLOO signals which gate the contents of the two least significant bytes of the
Console Switch Register to the Processor via SDOO:07. The RSTO signal clears the XC flip flop in the same manner as it
cleared XA.
12.4 Status Input
I
The Status byte encoding is shown in Chapter II, in the Model 8/32, 8/32C, 8/320 Users Manual, Publication Number 29-428.
12.5 Control Logic
Complimentary pulsed ESNOO and ESNCO signal from the console are fed into a deglitching R-S flip-flop (lOC5). ESNOO
and ESNCO are activated by depressing various keys of the Display Console keyboard (see Section 12.1). This results in
setting a CATN flip-flop and generating display controllers private interrupt to the CPU-DSPLY (10J8). DSPLY interrupt is
also generated by depressing the SNGL key on the Console keyboard, which sets the SNGL flip-flop. The SNGLO flip-flop
OOF8) can be sensed by CPU as MCR07. The {NCR flip-flop (lOC2) which determines either incremental or normal mode
sets on the trailing edge of the CMGBO control line. All Control lines for the display controller (6N5-9) are derived from
the MUX Bus control lines by gating them with the output of the controllers Address flip-flop ADB (9M4). These Control
lines are also used for the Display Consoles SYN generation (7C8). The D Bus drivers and receivers, SYN generation logic,
and part of the address decode logic is shared with the Teletypewriter controller.
13. TELETYPE CONTROLLER
The built-in Teletype (TTY) device controller interfaces an ASR;KSR 33 or 35 TTY to the Processor. It provides the
serial/parallel conversion required for data transfer between the parallel 0 Bus and the serial, eight level, start/stop ASCII
code signal used by the TTY (see Figure 30).
12345678
~STDP
START BIT
A ~
DATA
BITS~
11 BITS
I-.::-____
BITS ..
~
NEXT CHARACTER
START BIT
100 MS/CHARACTER
Figure 30.
84
Serial ASCII Code U (Even Parity)
01-078A21 R06 5/78
13.1 Block Diagram Analysis
Figure 31 is a block diagram of the TTY controller. The control circuits consist of the Command flip-flops (read or write,
etc.) which direct the flow of information, circuits to control ATN/ ACK functions, and logic to generate the status bits
and control the timer.
The serial infonnation received from the TTY is sampled by the timer and strobed into the Shift Register. When all the
data has been shifted in, the data in the Shift Register is transferred to the Buffer Register. It is then gated through 0 Bus
tri-state drivers on 008: 15), by the Data Request signal (DRG), Status Request Signal (SR), and Address (ADRS) Control
lines. A bit-by-bit copy of the received data may also be sent to the TTY printer/tape punch when the Block flip-flop
(BLK) is cleared. In the Write or Send mode, the data byte is placed directly (parallel) into the Shift Register and then
shifted out (serially) to the TTY.
13.2 Bus Communications and Address Circuits
Communications between the Processor and the TTY controller is via the Control lines, Test lines, and the low order eight
bits of the 0 Bus. The bus receivers (Sheet 8) are shared with the display controller. The Data Lines 008: 15 are buffered
. to form the DLOO:07 lines. When the wired address X'02' is detected, Line AO is active and the TTY address flip-flop
(ADA) (9M3) is toggled set on the trailing edge of the ADRSI signal (9J2). This enables the other Control lines for the
TTY controller (Sheet 10). While the ADRS1 signal Is active, the ASYNAO line goes low and generates the return SYNO
signal (11 G9).
Th(~ D Bus sent logic consists of 19-136 tri-state bus drivers (Sheets 8, 9, and 11) controlled directly by DRGAO, SRGAO
and! ATSYNO TTY Control lines, which are derived from the corresponding MUX Bus control and TTY Address flip-flop
(Sheet 10).
NOTE:
For systems where x'o2' has been assigned to another device, the
TTY controller may be strapped for X'82'. (see Sheet 7).
13.3 Status and Commands
The bit assignments for TTY status and command bytes is shown in Table 21.
TABLE 21. TELETYPE STATUS AND COMMAND BYTE
0
1
2
3
4
5
STATUS
BYTE
ERR
*
BRK
*
BSY
EX
COMMAND
BYTE
DISABLE
ENABLE
UNBLOCK
WRITE
READ
BIT
NUMBER
BLOCK
6
*
7
DU
DISARM
* Unassigned status (will return zero).
STATUS BYTE
ERR
The Error bit is set when a character is not taken from the controller buffer before another character is
assembled.
BRK
The Break bit is set at the end of one character time when the line is held in the space condition for a
period greater than a character period.
BSY
Read Mode. The Busy bit is normally set and is reset when data is available for transfer to the Processor.
Write Mode. The Busy bit is normally reset and is set when data is being transferred to the terminal.
EX
The Examine bit is set when BRK or ERR is set.
DU
The Device Unavailable bit is set when the terminal is powered down or in Local mode.
01-078A21 R03 4/77
85
COMMAND BYTE
DISABLE
Disables device interrupts; allows queuing of interrupts.
ENABLE
Enables device interrupts.
Note that a command byte with both Bits 0 and 1 set, DISARMS the interface, no intenupt queuing.
UNBLOCK
Allows the Printer to print data entered via the keyboard or tape reader.
BLOCK
Disables the Unblock feature.
WRITE
The interface is placed in the Write mode.
READ
The interface is placed in the Read mode.
The command flip-flops EBL, ARM, BLK, and WT (9J7, 9L 7) are loaded with the trailing edge of the CMGAO signal (9D7).
The contents of the flip-flops remain unchanged if the D input is low. The Write Storage flip-flop (WT) (9L7) unconditionally accepts the Read/Write signal from the Processor, however, the Write Execution flip-flop (WRT) (1205) can only be
updated when the timer has stopped; i.e., when TMGO (12A4) is high.
The EBL and ARM flip-flops (1217) arc loaded from DLOO and DLOI as described in Table 21. They control the action of
the Interrupt flip-flop (lNTR) (12E8) and the interrupt line ATNO (l2G7).
The Block flip-flop (BLK) controls the serial feedback of data from the TTY receiver to' the TTY driver. When reading a
non-ASCII tape, it is inconvenient and undesirable to permit the received data to reach the printer/stunt box and operate
the bell, line feed, form feed, etc., functions. This feedback is broken when the BLK flip-flop is set. Sending data to the
TTY from the Shift Register is not affected by the BLK flip-flop.
The Busy (BSY) status bit is controlled by the Write Execution flip-flop not the WT flip-flop. The Break bit remains set as
long as the Break key is depressed at the TTY. The Error bit (overflow) is cleared by either a Data Request, any command,
or the system initialize signal SCLRO.
13.4 Timer Circuits
The timer consists of the control flip-flop (TMG) (1202), a 440 HZ multi-vibrator MTA (l2H3) and MTB (I2K3), a
two-stage clock counter MTC (I2G4) and MTD (12H4), and a character counter (TA, TB, TC, and TD) (I2L6). In the idle
or reset state with the TMG flip-flop cleared, TMGI (l2D2) is low to disable MTA and MTB, to clear MTC and MTD, and
to preset the character counter to the count of five.
..
When the TMG flip-flop is toggled set at the end of DAGAO (12A2) in the Write mode; TMG1, TMGIA and DTMGl all go
high to enable the timer. The 440 Hz pulse train (MTBl) (l2L3) drives the two-stage counter (MTC and MTD) and a
decoder gate to generate the 110Hz train of clock pulses (CLKO and CLK!) (l2K4) and the shift pulses (SHFTl) (l2N4).
After the end of the ninth clock pulse, TB I, TCI, and TDI are all high, thus forcing FSTPO (12M5) low to terminate the
train of shift pulses. During the eleventh clock pulse, EOCO (l2A2) goes low, and the TMG flip-flop is toggled clear on its
trailing edge. This produces a train of eleven clock pulses and nine shift pulses having a period of 9.09 milliseconds (110Hz)
with the trailing edge of the first pulse occuring 9.09 milliseconds (one bit period) after TMG is set. The pulse width is
approximately 1.15 milliseconds (one-eighth of a bit period).
The idle timer is also started (by the direct set pulse STO) (12E3) when the received Start bit arrives from the keyboard or
tape reader or due to depression of the Break key. This is not dependent on the Read/Write mode since the BRK condition
must be detected in both modes. The width of the STO pulse is determined by delay Capacitor 02HCl (8Gl) which
generates the delayed TMGO signal DTMGO (l2C4). Since the MTD flip-flop is direct set STO, the first CLK/SHFTI pulse
occurs 4.545 milliseconds (half of a bit period) after the TMG flip-flop is set; the period of the pulses is still 9.09
milliseconds. Received data is sampled/shifted at the center of each bit. The TMG flip-flop is toggled clear at the end of the
EOC and TTMG pulses as before.
13.5 Data Output
The TTY controller is in the Write mode when both the WT and WRT flip-flops are set. To send data to the TTY, the
DAGAO line (lIAS) goes low to load DLOO:07 into the Shift Register, clears the Start bit flip-flop (DRN) (1IN6) and
toggles set the Timing Gate flip-flop (TMG) (12D2). Note that if the timer was already running when the Data Available
Control signal is received, the DAGAO signal (lIAS) would be blocked by TMGO (12D2) low, no return SYN would be
generated, and the false sync condition would be detected after 35 microseconds. For this reason the WDH instruction
must not be used with the TTY controller.
86
OI-078A21 R03 4/77
r~D~A~T~A~L~I~N~ES~-~H~IG~H~D~(~00~:~07~)______________~T~
o
__---------------------------------------------------------l
DATA LINES - LOW D(08:15)
FROM CPU
OR PRIOR
CONTROLLER
l IN
H~
LINES
TO
NEXT
CONTROLLER
ATNO
SYNO
- RACKO
It
2/
~
I
DISPLAY
CONTROLLER
~~
a
~
ADDRESS
CI RCUIT
/
I COMMAND
/ 6
GATES
I
I
TIMER
'
I
,
I
I
I
8
SRGO,DRGO
DAGO
DOO
SENK
SHIFT 1 (
-T
LDBR1
IBLKO
JOTl
TELETYPE
LINE
[----4~
CIRCUITS
lCJDTO
1 ill ! 1 ~ !
i
I
Jl
I 011
l
J ~ l ~ l
1 213
+ + + +
R:~I~;ER
1
101112134151617
+ + +J
DATA BR(OO:07)
,
/
>
TELETYPE
Fi 9ure 31. Tele type Controller Block Dia9ram
ATN/ACKI
CIRCUIT
-I
r-
ATSYNO
OBUS
DRIVERS
t
•
j
----i
BUFFER
4 1 5 1 6 1 7 1 REGISTER
.~
OU1
I
J
NJ
10RNO
00
--.J
/ -I
CONTROL
FLIP-FLOPS
AND
CIRCUITS
STATUS
RECEIVE
-' J
ARM1,EBL1,SATNO
--.
l
/ J
I
-
DATA LINE JICONTROL L1NEl
RECEIVERS
RECEIVERS
, 10 -,
DOO/1
T~
va
1r5
i
I
ACK/ADRS
STRAPS
I
When the timer starts, shift/clock pulses are generated as described earlier and shown on Figure 32. The bit stored in the
DRN flip-flop is connected to the transmit line (TNSB 1) (l6D2) by the high states on the device transmitting (DTO) and
the TMGl lines. Since the DRN flip-flop is initially cleared by DAGAO, TNSBl goes low, and the gate driving TN SO turns
off to send the open-loop Start bit condition. At the end of each shift pulse, as the eight data bits are sequentially
transferred into the DRN flip-flop, a high state at the serial input of the Shift Register (DXl) (11 B2) gradually loads the
register with all ones (including the DRN flip-flop).
DAGAO
TMG1
BSYl
ClK1
FSTPO
SHFT1
EOCO
TNSB1
6
5
4
3
2
STOP
BITS
100 MS
ONE CHARACTER PERIOD
.1
Figure 32. Write Mode (Output) Timing, Teletype
During the last two clock periods, after shifting has stopped, the ONE Level stored in the DRN flip-flop is sent out as the
closed-loop Stop bit condition. The EOC pulse clears the TMG flip-flop to generate the closed-loop idle condition.
With the WRT flip-flop set, the status bit BSYl (12D6) is active when TMGl is active. Should a command which clears the
WT flip-flop (Read mode) be received while the timer is running, the WRT flip-flop (and the definition of BSY status) does
not change until the TMG flip-flop is cleared and TMGO (8F8) gates WTl into the WRT flip-flop.
13.6 Data Input
The timer circuit can be started from the TTY receive loop in either the Read or Write mode as described in Section 13.4.
This insures that the Break condition is always detected. However, serial data cannot enter the Shift Register (DXl)
(11 B2), unless the TTY controller is in the Read mode; Le., the WRT flip-flop is cleared and WRTO high. The Load Buffer
Register pulses (LDBRl) (8G2) are generated only in the Read mode.
The Device Data line (DDt) (16G7) is high active when there is current flowing in the receive loop. This represents the
logic ONE level and also the idle loop condition. The signal from the receive loop is filtered by an RC network (180
ohms/2.2 mfd) (16J8) and then reshaped by the Schmidt Trigger circuit (composed of a pair of inverters and two resistors)
(1 GE7) to generate the DDO and DDI signals.
When DDO and DDt first become active, the timer is started by the STO pulse (as described in Section 13.4) and the Device
Transmitting flip-flop (DT) (11 J6) is set. This flip-flop forces the TNSBt line high and partially selects the TNSAI gate,
subject to a high level on the BLKO and DDO lines; i.e., the serial feedback circuit to the TTY Printer/Punch. The DT
flip-flop also arms the Line Check flip-flop (XLC) (11 M7) by placing a high level on the D input.
88
01-078A21 R03 4/77
As seen on Figure 32, the XLC flip-flop is toggled set at the end of the first SHFT pulse. During the first SHFT pulse. the
receive loop is checked to insure that the loop is still open; i.e., a legitimate Start bit has started the timer. If the loop is
closed, DDl is high and the Start Glitch pulse (GLTCHO) (12B2), is generated to clear the TMG flip-flop at the end of the'
SHFT pulse. The timer is reset, there are no EOC or LDBR pulses, the Buffer Active flip-flop (BA) (8E8) and the BSY
status are unchanged.
I
START
BIT
001
I
STOPd
BITS
(1 )
(2)
(3)
(4)
(5)
(6)
6
5
4
3
2
(7)
STO
(8)
o
1 - - - - '......
T
I
I
I
I
I
~~~~~~__~~____-+____~____~~__~____~~____r-____r-____~~L~~-----OIl
CLKl
SHFTl
EOCO
XLCl
I~~~~-----------------------------100MS
Note: Bit Designations (X) are Paper Tape Channel Numbers.
Figure 33. Read Mode (Input) Timing, Teletype
The serial data at the Shift Register input (DX!) (11 B2) is active when the DD I line is active. The nine SHTI pulses move
the received data into and along the Shift Register until the Start bit and the eight data bits occupy DRN and SROO:07.
Shifting occurs at the end of each SHFT pulse; i.e., the center of each bit.
The TMG flip-flop toggles clear at the end of the EOC pulse and clears the DT flip-flop. The XLC flip flop is cleared by
EOC if the loop is closed due to a Stop bit, DDI high (l6E7). In the case of a missing Stop bit (or Break condition), the
XLC flip-flop remains set after the EOC pulse has cleared the TMG flip flop. The function TMGO'XLCI causes BRKO
(8K7) to go low, and lines BRKI, EXI, and EXO to become active. The timer cannot restart on the open loop condition
since STO=DTMGO' DDO· XLCO.
The BRK condition continues until the receive loop is closed. The DDl·TMGO function then clears the XLC flip-flop.
In the Read mode, BSYI (12D6) is low whenever the Buffer Active flip-flop (BA) (8E8) is set. The EOCI pulse generates
the LDBlRI pulse to load the Buffer Register and toggle set the BA flip-flop. The DRGAO signal (8A9) clears the BA
flip-flop when the buffer is gated to the D Bus. An overflow or error state exists if the LDBRI pulse finds the BA flip-flop
still set, the Overflow flip-flop (OV) (8G8) is then set. The OVand BA flip-flops are cleared by the DRG pulse, any CMG
pulse, or the initialize signal SCLROB.
OI-078A21 R03 4/77
89
13.7 Interrupt Circuit
The TTY controller generates an interrupt for a negative transition on BSY1. This transition toggle sets the DFBSYO
(l2E7) flip-flop which in tum direct sets the INTR flip-flop (l2E8). This forces ATN 1 high and ATNO low.
The Processor responds by executing an Acknowledge interrupt. When the TTY controller has first priority, the RACKO
lead goes low forcing RACKI and DRACKI high. With GATNI high, the TACKO gate is blocked and the ATSYNO line
goes low. This gates the controller address x'o2' to the D Bus, generates the return SYNO, direct clears the DFBSY
flip-flop, and clears the INTR flip-flop at the end of ATSYNO.
When the system uses the Memory Protect and/or the Real Time Clock controllers, the RACKO/RACKO daisy-chain is
wired to the higher priority controllers before it reaches the TTY over the back panel.
As noted, in Section 13.3, the Disable command clears the EBL flip-flop forcing the EBLl (9H7) and GATNI lines low.
Interrupts may be queued by setting the INTR flip-flop. The Disarm command forces the ARM 1 lead (9H8) low to clear
the INTR flip-flops and hold them clear; interrupts are not queued.
13.8 Initialization
The system initialize signal SCLRO (15K2) conditions the TTY controller by setting the BLK flip-flop and clearing all
other control flip-flops. This presets the controller in the Read mode with interrupts disarmed.
13.9 TTY Timer Adjustment
The only adjustment on the TTY controller controls the frequency of the 440Hz timing multivibrator. The adjustment is
made in the following manner:
I. Initialize the system.
2. Connect an oscilloscope to TP-TMGIA (located at the stake ncar Connector 2).
Vertical scale: 2 volts/centimeter
Horizontal scale: 1 milliseconds/centimeter
Sync: internal, negative
3. Generate a continuous stream of data from the TTY by 'reading a tape or by the Repeat function of the keyboard.
4. Adjust Potentiometer at location 14R (next to the test point TMGIA) for the waveform shown below.
L-1--
4.5:'c 0.2
~
.
mnli"COd~
100 milliseconds .
13.10 Machine Control Register (MCR) (Sheet 7)
A Machine Malfunction (MMF) interrupt is generated when Bit 11, 12, 13, 14, or 15 of the Machine Control Register
(MCR) is set (7G4). The MCR bits are assigned and gated (with the SMCR function) as indicated in Table 22.
The CMCR function clears MCRl1 :15 where there are ONES in B27:31. The system Initialize (SCLRO) clears MCRIO:15
-- the straps are not affected. The SMCR function is described in Section 11.2.
13.11 Power Monitor and System Initialize
All circuits for the Power Monitor are on Sheet 15. The master reset signal SCLRO (15F2) is active when the Initialize
Relay K 1 (15B9) is de-energized. During normal operating conditions, all voltages are present and the POWDNO line (l5G7)
is high. This allows the voltage comparator output to remain high. As long as the voltage comparators output is high, the
Initialize Relay KI remains energized and the SCLRO line is held high to +5 volts by a resistor (15E2).
I
If any of the four items listed in Section 10.1 (CL070) occur, the STPFI line (1412) goes high and starts the one millisecond EPF timer (14K2). The leading edge of EPFO (14L2) sets Bit 15 in the MCR (7G2), generating a Machine Malfunction (MMF) interrupt. In response to MMF, the user has an opportunity to do any necessary system resetting and data
storage.
90
01-078A21 R07 9/78
TABLE 22. MeR BIT ASSIGNMENT
BIT
MNEMONIC
MEANING
S-BUS
CONDITION
CODES
f,---.
MCR15
EPF
EARLY MF
S31 and
LFCO
MCR14
IRMP
INSTRUCTION PARITY FAIL
S30 and
GFCO
MCR13
DMPFO
DATA PARITY FAIL
S29 and
VFCO
MCR12
APF
AUTO DRIVER PARITY FAIL
S28 and
CFCO
MCRll
STF
STRT TIME OUT FAIL
S27
MCR10
CATN
CONSOLE ATTENTION
S26
MCR09
RSTS
REGISTER
MCR08
SPARE
MCR07
SNGU
DISPLA Y CONTROLLER SNGL F-F
MCR05
BNK B
BANK B
(STRAP)
S21
MCR04
BNKA
BANK A
(STRAP)
S20
MCR06
MCR061
(STRAP)
S25
(STRAP)
S24
INIT BUTTON IS BEING DEPRESSED
S23
S22
At the end of the one millisecond EPF delay, the trailing edge of EPFO (l4G5) toggle sets the Primary Power Fail flip-flop
(PPF) (l4HS) causing the PPF interrupt (l4K6) to be sent to the CPU and a low active signal on CL070 (l4K6). PPFI also
starts another one millisecond timer XPF (l4K5). When the PPF interrupt is detected, the micro-program stores the PSW
and register stack in the main memory and sends the POW function to the IOU. The Stop flip-flop (STP) (l4N5) is either
toggled set by the trailing edge of XPFI or direct set by FPOWO (l4N4), whichever occurs first. When STPI goes high,
POWDNO goes low to turn off the transistors of the Darlington circuit and de-energize the Initialize Relay KI. The GSTPI
lead (15J7) is normally high. It is unused except in some multi-CPU systems.
Loss of AC or DC power also de-energizes the relay. POWDNO goes low when the -15 volt input (N 15) (15D8) to the
inverter is lost. The Darlington circuit cannot operate the relay if either the +5 volt collector supply (PS) or the +15 volt
base supply (PIS) (l5B6) is missing. Should the AC input (AC] and AC3) (15B2) be too low or missing, the Power Fail
Detector circuit removes the base drive to the Darlington circuit.
If the AC input is lost (or fluctuates enough) the potential at the base of 02BQ3 becomes more negative, 02BQ3 conducts
and supplies base drive to 02BQ1. The 4.7K resistor (15K4) provides positive feedback from 02BQI to 02BQ3 causing
these transistors to turn on. The emitter voltage of 02BQ3 drops, 02BQ4 turns off, 02BQ2 turns on and commences to
discharge the delay capacitors (l5B6). With 02BQI conducting, its collector voltage approaches ground and generates the
low active signal PFDTO (15K4). As described earlier, this starts the sequence which puts a low level on POWDNO and
completes the capacitor discharge. The Darlington circuit has no base drive so the relay is deenergized.
The Initial:lze Relay Kl is a dry reed unit with Single Pole Double Throw contacts. The normally closed contact of the
de-energized relay (Kl) provides a metallic ground on the system Initialize line (SCLRO (15K2).
For a sequence due to POFF, LSU, INITO, EXAO, or EXBO low (14A2) clearing STP allows the POWDNO lead to go high
and the de!lay capacitors (15B6) to charge slowly through the base resistors of Transistor 03AQI. When the threshold of
the Darlington circuit is reached, the circuit conducts and the Initialize Relay K 1 is energized thereby removing the ground
from the SCLRO line.
In the case where hlitialize is caused by a failure to P5, N15, .PIS or the AC supply,. the Initialize Rehty Kl de-energizes
.
and remains in that state until the fault is corrected.
OI-078A21 R03 4/77
91
13.12 Primary Power Fail Check
.-/
The Primary Power Fail Detector is located on the IOU board. The circuit is checked and adjusted as follows:
1.
Connect the Primary Power Cord of the CPU power supply into a variable voltage source (Variac or
equivalent).
2.
With the line voltage set at the nominal value of 115.0 VAC, turn the Power on.
3.
Adjust Potentiometer at location OOR to generate the Power Fail condition of CL070 (back panel Terminal
122-0) when the AC line voltage is set for 103.5V (i.e., 10% low). System Initialize line (SCLRO) Terminal
105-0 should become low active in less then 2 milliseconds after STPIA (Test Point 110-4) goes active.
4.
With nominal line voltage, load the Model 8/32 Test Program and depress the RUN Key. While the program is
running, remove the AC line cord from the primary power source.
NOTE:
The TTY will run-open if connected into a different power source.
5.
Connect the AC line cord back into the power source. The TTY should stop cycling. Depress the EXEcute
switch and the test program should continue to run.
6.
Repeat Step 4, but turn the Console Power switch OFF instead of removing the AC line cord.
13.13 Start Timer
The Start Timer circuit is shown at location 15E6. With the timer-kill (KSTMl) (15C7) in its normally low state, the
ungated STRTO signal (15B8) enables the 30 microsecond timer STMA (15E6). When the selected module generates a
MFINO (15H8) signal, then it clears the timer and disables the timer flip-flop (STMB) (6F8).
The STRT Timer (30 microseconds) is activated whenever the CPU sends the STRT signal to the various system modules
(ALU, FAU, IOU, etc.) and is cleared by the MFIN signal from the module addressed by the MSEL (00:02) lines. Should
the time out occur before the MFIN signal arrives, one of the two things happen.
I. On non-MUX Bus operations, Bit 11 of the MCR is set, a pseudo MFIN signal restarts the CPU clock, and the MMF
interrupt is generated.
2. In the case time out occurs during a MUX Bus operation, the MCR is unchanged, the False Sync code (OIOO/CVGL) is
placed on both Condition Code Busses and a pseudo MFIN restart the CPU clock. If the MUX Bus operation happens to be
of the sense type, X'04' is gated to the proper byte as determined by CA311 and the other byte is gated to the S Bus
unchanged.
92
01-078A21 R03 4/77
I
14. SAND D BUS ROM CONTROLLERS
]4.1 S Bus High ROM Controller (19-142F4S)
000-007
HLLL HLLL LHLH LHLH LLLL LLLL LLLL LLLL
19-084ROOF78
008-015>
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF78
016-023
HLLL HLLL LHLH LHLH LLLL LLLL LLLL LLLL
19-084ROOF78
024-031
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF78
032-039
LLHL LUI L LLHL LLfl L 1. HLH LHLH LHLH LHLH
19-084ROOF78
040-047
LLLL LLLL LLLL LLLL L1LL LLLL LLLL LLLL
19-084ROOF78
048-05:1
LLHL LLHL LLHL LLHL LLLL LLLL LLLL LLLL
19-084ROOF78
056-063-
LLHH LLHI-{ LT. t{ H LLHH LLLL LLLL LLLL LLLL
19-084ROOF78
064-071
HLLL HLLL LHLH LHLH LLLL LLLL LLLL LLLL
19-084RO!)F78
072-07g
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-0>34ROOF78
090-087
HLLL HLLL LHLH LHLH lLLL LLLL LLLL LLLL
13-084ROOF78
088-09:;
LLLL LLLL LLLL LLLL LLLL
LLL~
19-084ROOF78
096-10]
LLH L LL HL LL ~1 L LLH r.
HLI. :1 Lrl L H LHLH
104-111
LLLL LLLL LLLL LLLL LLLL LLLL LILL LLLL
19-0H4ROOF78
112-119
LLLL LLLL LLLL LLLL LHLL LHLL LHLL LHLL
19-0H4ROOF78
120-127
LI.LL LLLL LLLI. LLLL LLLL LLLL L1.LL LLLL
19-084ROOF78
128-135
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF78
136-143
LLLL LLLL LLLL L1LL LLLL LLLL LLLL LLLL
19-084ROOF78
144-151
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF78
152-159
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
1:}-084ROOF78
160-167
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF78
168-175
LLLL LLLL LLLL LI.LL LLLL LLI.L LLLL LLLL
19-084ROOF78
176-183
LLLL LLLL LLI.L LLLL LLLL LLLL LLLL LLLL
19-084ROOF78
184-19'1
LLLL LLLL LLLL 1.1LL 1.1.LL LLLL LLLL LLLL
19-084ROOF78
192-199
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
1~-084aOOF78
200-207
LLLL LLLL LLLL LLLL LLLL LLLI. LLLL LLLL
19-084ROOF78
20 8 - 2 1 :)
L L LI, L I, L L L LL L
r. I. L L 1. 1. LL LLLL LLLL LLLL
19-014ROOF78
216-223
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF78
224-231
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF78
232-239
LLLL LLLL LLLL L1.LL LLLL LLLL LLLL LLLL
19-084ROOF78
240-247
LLLL LLLL LLLL LLLL L1.LL LLLL LLLL LLLL
19-084ROOF78
248-255
LLLL LLLL LLLL LLLL LLLL I.LLL LLLL LLLL
19-034ROOF78
Ol-078A21 R03 4/77
If L LH
LLLL LLLL
19-0d4ROIJF79
93
14.2 S Bus Low ROM Controller (l9-142F46)
,0'00-007
LHLL LHLL HLLL HLLL HLLL HLLL HLLL HLLL
19-084ROOF79
008-015
LLLL LLLL LLLL LLLL LLLL LL1.L L1LL LLLL
19-084ROOF'79
016-023
LHLL LHLL HLLL HLLL HlLL HLLl H1LL HLLL
19-:)d4ROOF'79
024-031
LLLL L1L1 L1LL LLLL LLLL LLLL lLLL LLLL
19-084ROOF79
032- 039
HLLL HLLL HLLL HtLL IlLLH HL1" HL1.H HLLH
19-084ROOF79
040-047
LL1L LLLL LLLL LLLL LHLL LHLL LHLL LHLL
19-08 4!~ OOF7Q
048-055
!lLLL HLI.L HLLL HLLL LLLL LLLL LLLL LLLL
19-084ROOF79
056-053
LLH!! LLHH LLHH tLHH LLLL LLLL LLLL LLLL
19-:)84ROOF79
064-071
LHLL LHLL HLLL HLLL HLLL HLLL HLLL HLLL
19-034ROOF79
072-079
I.LLL t!.L!. T.T.I.L LLLL l.T.LL LLLL LLLL LLLL
19-:)B4HOOF79
080-087
LHL1 LHLL flLLL IILLL Ht.LL HLLL HLLL HLLL
19-084ROOF79
088- 09 5
T.LLL LLtL LLLL LLLL LLlL LLLL LLLL LLLL
19-084ROOF79
OQ6-103
fiLLL HLLL HLLL HLlL LHLL LHLI. Htf.H HLLH
19-084ROOF79
104-111
LI, LI. LLL1 LLL L LLLL L1. H1. LLil L LHLL LHLL
19-0H4~OOF79
112- 119
LLLL LLLL LLLL LLLl I.IILfi LH1'-1 LHLH LHLH
1i-084ROOF79
120-127
LLLL LLLt LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
128-135
LLLL LLL1 LLLL LLLL LLLL LLLL LLLL LLLL
19-J84ROOF79
136-143
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
144-151
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
152-159
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
160-167
LLLL LLLl LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
168-175
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
176-183
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
184-191
LLLT. LLLL LLLL LLl.L LLLL LLLL LLLL LLLL
19-084ROOF79
192-199
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
200-207
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
208-215
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
216-223
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
224-231
LLLI. LI. I. L Lt LL LLLL LLL1. 1. LLL LLLL LLLL
19-084ROOF79
232-239
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
240-247
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
248-255
LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL
19-084ROOF79
94
Ol-078A21 R03 4/77
14.3 D Bus ROM Controller (l9-142F47)
000-007
HHHH HHHH LHHH HHHH HHHH HHHH LHHH HHHH
19-084ROOF80
008-015
HHHH HHHH LHHH HHHH HHHH HHHH LHHH HHHH
19-084ROOF80
016-023
HHHH HHHH LHHH HHHH HHHH HHHH LHHH HHHH
19-0R4ROOF80
024-031
HHHH HHHH 1.IlHH IfHHH HHHH HAHH LHH.H HHHB
19-084ROOF80
032-0·~9
HHHH HHHH L\l iii!
19-084ROOF80
040-D47
flHHH
HHHH LHflH HLHL BHHH HHHH LHHH HLHL
H-084ROOF80
048-055
HIIHf! HHHH LHHH HLHL HHHH HHHH LHHB HLHL
19-084ROOF80
056-063
HHII H HHHH L HtI H HL HL HHHII HH1111 LWi H HL HL
19-084ROOF80
064-071
HHHH HHH:'{ I.lIHH HHHH
LHHH HHHH
1)-034ROOF80
072-079
HHHH HHIIH LHHH HHHH IIBHY HHHII LIlIiH HHHH
19-0U4ROOF80
080-087
HHHH HHWI LiHH
flHHH HHHH LHHH HHHH
19-084ROOF80
088-0'95
II HHH HH11 H L IFI H HHHH 1f!1 HII HHHH L HIi II HHHH
19-084ROOF80
096-103
l! HHH HHII II
T.ll HH II HL H II HHH HHH H L HHH HHL H
19-094ROOP80
104-111
HHHH
LHHH HUlL HtiHH HH!lH LilHH :-lUlL
13-~8!.JRoaF80
112-119
HHHH HHHH LHHH HLHL HHHH HHHH LHBH HLHL
19-084ROOF80
120-127
HHHH HHHH LHHH HI.HL HHHH HHHH LUHH llLHL
19-084ROOF80
128-135
HHHH HHUH LHHH HHHH IlHHH HHHH LHHH HHHH
19-084ROOFgO
136-143
HHHH HHHH LHtJH HHHH HHHH HHHH LHHH HHHH
19-0S4ROOF80
144-1'11
HHHH HHHH
HHHH HHHH HHHH HHHH HHHH
19-084ROOF80
152-159
!lUHH HHHH HHHH HHHH HHHH HHHH HHHH HHHH
19-084ROOF80
160-167
HHHH HLHf! LHHH HH!.H HHHn HHHH LHHH HUlL
19-0tl4ROOF80
168-175
HHHH HLHH LHHH flHLH HHHH HHHH LHHH HLlIL
19-084ROOF80
176-183
HHHH HHHH H:IHH HHHH HHHH HHHH HHHH HHHIf
19-084ROOF80
184-191
HHHIi II HHH HH1{ H HHHH II HHH HHfll~ HHHH HHHH
19-08 ,.. ROOfeO
192-199
i1 H HH H H!~ If
H HII H HII HH H H H H H HH H H HH H HH H H
19-081~ROOFBO
200-207
HHHfl II HHH Ill-l HH HHHH HHHH HHHH HHHH HHHH
19-084ROOF80
208-215
HHHH HHHH HHHH HHHH IlHHH
IIHHH
19-084ROOF80
216-223
'lHHH HHHH HHHH HHHH HHHH HHHH HHflH HHHH
19-084ROOF80
224-231
!lHHH HHHH HHHH HHHH HHHH HHflH HHHH HHHH
19-084ROOF80
232-2.39
HHHH HHHH HHHH HHHH HHHH HHIIH HH!IH HHHH
19-084ROOF80
HHHH
01-078A21 R03 4/77
HH~H
f(
HLH HHHH HH~1:-! LHHH HHL H
HHHH
HHH~l
HH~IH
~HHH
HHHH
95
15. EXTENDER BOARD OPERATION
The following steps must be taken to insure proper Extender Board operation when troubleshooting any of the Processor
boards on the Extender Board.
1.
Remove the 35-537 CPB (lower Slot 7) to modify the CPU Clock speed. An octal switch is located in
IC position 15E for this purpose. Switch positions 4 and 8 are to be ON for Extender Board operation.
No other switch positions may be placed in the ON position.
I
2.
Place the 28-015 Extender Board in the chassis slot of the board to be tested. Note that there are two sets
of backpanel pins on the Extender Board. Plug the board to be tested into the upper set of pins and plug
the Extender Board terminator board (see Step 3) into the lower set of pins.
I
3.
One of two terminator boards must be used for Processor Extender Board operation. The 35-598
Terminator is to be used with the CPA board on the extender, and the 35-599 Terminator is to be
used with any of the following: CPB, CPC, ALU, and IOU. The terminator is to be installed as
described in Step 2.
4.
For Extender Board operation of the CPA, CPB, or CPC, 610 mm (24") extender cables (71-362 and 17363) are required.
96
01-078A21 R06 5/78
16.
MNEMONICS
TIle following lists provide a brief description of each mnemonic found in the Model 8/32 CPA Schematic
Drawing 35-536D08, CPB Schematic Drawing 35-537D08, CPC Schematic Drawing 35-555D08, ALU Schematic
Drawing 35-538D08, and IOU Schematic Drawing 35-539. The source of each signal on the respective schematic
drawing is also provided.
16.1 CPA Mnemonics, Schematic Drawing 35-536D08
MNEMONICS
MEANING
SCHEMATIC
LOCATION
ADA28 I :311
Add-one-Ioop outputs
Sheet 3
AEQBl
Segment number equality
6El
BOOO:310
B Bus
Sheet 13
BDLYO
BIT16lA
BIT161 B
BMXNAI
Base selection delay
6J5
Bit 16 propagate signal
12N9
B Mux Enable A - S Bus
12N7
BMXNBI
B Mux Enable B - MDR
12L5
BMXNCI
B Mux Enable C, MLC/CA
12NS
BMXSLAI
B Mux Select Line A - Halfword MDR
12J8
1
BMXSLBI
B Mux Select B -- MLC
12L5
BR040:270
Base Register outputs
Sheet 6
BRWRI
Base Register Write Command
7N7
BSELOOI :041
B Bus Source Address
12J4
Carry Commands
Sheet I
C3XO
Carry past segment boundary
12G8
CA310
Address Bit 3 1
3B8
CA120:300
Memory Address Bus
Sheet 8
CACLRO
Buffered Clear
IN8
ceo
Second HW Clock
IF9
COOl
COlO
COIl
1
CDOOO:310
Memory Data Bus
Sheet II
CDWO
Write Conversion Command
7M5
CKIA
System Clock
4M3
CLINTO
Clear Interrupt flip flop
7R8
CLOCKO
System Clock
4AI
CMCOOO:020
Memory Command Bus
Sheet 2
CPCOII/OOI
Increment Commands
2F5
CRDYO
Memory Ready (response)
IA2
CREQO
Memory Request
IR2
CSOOO
Control State 0
2G8
CSTAO
Clear Status Register
7R8
DREQO
Data Request
IR7
FSRO
Status Register flip flop
7G8
GTO/I
Greater Than segment limit
12G7
INCR021
Increment MLC by Two HW
toM7
01-078A2I R03 4/77
97
MNEMONICS
INCR1
MEANING
Increment MLC by One HW
SCHEMATIC
LOCATION
toM6
IR1
Instruction Read decode
2K7
IR271 :311
Status Register outputs
Sheet 7
IREQO
Instruction Request
IRS
LOMARO
Load MAR
2C7
LOMCLO
Load MLC
2B6
LOMORO
Load MOR
208
LOUIRO
Load UlR Clock
4M2
LIMEl
Limit violation
6N6
MAIO
Memory Access Interrupt
7R4
MALX120:230
Address Multiplexor outputs
Sheet 8
MAR121:311
Memory Address Register outputs
Sheet 3
MARPUI
Pull up resistor
Sheet 3
MCOOO:030
Microcontrol field
Sheet 2
MCLKO
Memory Oata Clock
4F3
MOR001 :311
Memory Oata Register outputs
Sheet 4
MORCLO
Memory Cycle Clock
IB2
MOX001 :151
MOR input Multiplexor
Sheet 11
MLC121 :311
Memory Location Counter outputs
Sheet 3
MSIGO
Module Signal
toR5
NWI
Write Inhibit
7M2
PROTI
Enable Protect/Relocate
2G4
PSW2to
Program Status Word Bit 21
204
RGENO
B Bus Register Enable
12N6
RHO
Read Halfword Command
2F8
RI020
RI2 format
lOE3
RQFFO
Request flip flop
IN2
RRSFI
RR or SF format
1003
RSTR/O
Read Status Register
7R9
RX001
RX format
Sheet 10
RX2FO/l
RX2 flip flop
toK4
RX300
RX3 Format decode
10R5
RX3EN1
RX3 decode enable
lOKS
RX3F1/0
RX3 flip flop
10KS
RXIOO
RX1 decode
10M3
RXILO
RX3/RI2 fonnat
toM5
SOOO: 150
Part of S Bus
Sheet 5
S160:310
Part of S Bus
Sheet 5
S2BO
S Bus to B Bus Override Command
12G6
SCLRO
System Gear
118
98
01-078A21 R03 4/77
MNEMONICS
MEANING
------
SCHEMATIC
LOCATION
SDRI
Data Read Command
2N2
,SDRDWI
Data Read/Write Command
2S5
SDWI
Data Write Command
2N2
SEGWEA/B
Base Register HW Write
Sheet 6
SIRI/0
Instruction Read Command
2J6
SMCOOIO:030
Buffered MC field
Sheet 2
SROOO:310
S Register outputs
Sheet 5
SROOl:311
S Register outputs
Sheet 5
SRCKO
Status Register Oock
7C5
SRTRO
Status Register Trap
7N6
SSELOOI :041
S Bus Address Select Bus
2A7
STBO
Strobe
12M2
SM2X121 :311
Summer two outputs
Sheet 9
SX280:310
Second Index Register Address
Sheet 11
UDR280:31O
User Destination Register Address
Sheet 5
UlR240:310
User Instruction Register
Sheet 5
USR280:31O
User Source Register Address
Sheet S
XPUI
Pull up resistor
6ES
01-078A21 R03 4/77
99
16.2 CPB Mnemonics Schematic Drawing 35-537D08
MNEMONICS
SCHEMATIC
LOCATION
MEANING
A140:270
A Bus Bits 14:27
Sheet 5
A280:A310
ABus Bits 28:31
Sheet 4
AENO
Enables ASEL Multiplexor
3F5
ASELOOI :041
Selects Register containing A Operand
Sheet 3
ATNOOO:030
Interrupt Attention lines
Sheet 12
AYDSI/0
ASEL Multiplexor select line
3E3
BOOO:310
B Bus Bits 00:31
Sheet 6
B280:310
B Bus Bits 28:31
Sheet 2
BALAO
Branch and Link, ARM Interrupts
1419
BOCO
Branch and Disaml Console Interrupt
1418
BENO
Enables BSEL multiplexor
3J7
BSELOOI :041
Selects Register containing B operand
Sheet 3
BYDSO
BSEL Multiplexor Select line
3K8
CIX071 :141
ROM Address: Traps or Op-Code pointers
Sheet 8
C2XIOl: 151
ROM Address: B Bus or ROM Instruction Register indirect field
Sheet 8
CCCO
Carry Condition Code
4D6
CCCLKO
Condition Code Clock loads PSW
4M7
CFLGI
Carry flag
4F6
CLKO
CPU Clock
13N4
CLKIA
CPU Clock
13N4
CLK1B
CPU Clock
13N3
CSOOO:030
CPU Control States
Sheet 14
CSA041 :091
ROM Address
Sheet 9
CSAI/O
Counter State A
14M2
CSA100:150
ROM Address
Sheet 8
CSBI/O
Control State B
14M3
CSOOOI :311
ROM data
Sheet 11
CSREFO
Denotes control store reference
5N3
CSWRTO
Control Store Write
I1G4
01
Decode Bit
I1N6
DREQO
Data Request
13A3
OSPYLO
Display Interrupt
12A4
El
Execute Bit
llN5
ENFLGI
Enable PSW flags
llR3
ENPGOO:40
Page enable for ROM
Sheet 10
ENSMXO
Enables S Bus multiplexor
7F9
ENYSDXO
Enables YSI/YDI to B Bus
3S5
EXEC1/0
Execute Bit of micro-code
5Nl
FLGCLKO
Flag Clock latches Condition Code
4K8
100
01-078A21 R03 4/77
MNEMONICS
MEANING
SCHEMATIC
LOCATION
FSELOOO:030
Function Select lines
Sheet 11
FYXO
User index enable
3D5
GBIMO
Gate Immediate field to B Bus
6D9
GCCO
Greater Than Condition Code
4D8
GENO
Generate interrupt
12K4
GFLGI
Greater Than flag
4F8
GPSWAO
Enables PSW selection
3M3
ILEGA
Illegal Instruction
12Kl
ILEGB
Illegal Instruction
12K2
ILEGC
Illegal Instruction
12K2
INCLKO
Oock Inhibit
13Hl
IREQO
Instruction Request
13A1
INT1/0
Interrupt present
12N6
1B041: 151
Jam address Bits 04: 15
Sheet 1
JUTYI
Discriminates between RXl, RX2, or RX3 Instructions
14AI
KLCLKO
Disables CPU clock for manual testing
IR8
KSIGO
Extension of FSEL field
I1N5
LCCO
Less Than Condition Code
4D9
4F9
LFLG1
Less Than flag
MAl
Memory Access Controller
12B8
MB041: 151
Match Address Bits 04: 15
Sheet 1
MCOOO:030
Memory Control field
Sheet 11
MMFO
Machine Malfunction interrupt
12B5
MNCLK1/0
Manual Clock (P.B. switch)
Sheet 1
MODOOO/OOI
Module zero
5Ml
MPENO
Memory Protect enable
12H9
MSELOOO:020
Module Select lines
Sheet II
MSIGO
Module signal
14AI
MTCH
LED indicator signals address match
IS6
MTCHI
Stored XMA TCH 1
IM6
PASS1/0
Do not take branch
14K8
PCLKO
CPU Clock
13N3
PPFO
Primary Power Fail
12B6
PRIV
Privileged instruction
12Kl
PSW141 :271
PSW Bits 14:27
Sheet 5
PSW281:311
PSW Bits 28:31
Sheet 4
PSWCLKI
PSW Clock
4K9
RIROOO:310
ROM Instruction Register
Sheet 11
RIR20lA
Bit 20; ROM Instruction Register
6D9
01-078A21 R03 4/77
101
MEANING
MNEMONICS
SCHEMATIC
LOCATION
RIRCLKO
ROM Instruction Register Clock
llH8
RLC041 :151
ROM Location Counter
Sheet 9
RLR041 :151
ROM Location Register
Sheet 9
RRXINHO
Inhibits transfer in RRX micro-instructions
14Hl
RUN 1/0
Run mode
Sheet 1
RX3DO
RX3 instruction
2H3
SOO:310
S Bus Bits 00:31
Sheet 7
S2Bl
Gates S Bus data to B Bus
14G4
SAMAl
ROM Address Select line
5R4
SAMBLl
ROM Address Select line
5N5
SAMBMI
ROM Address Select line
5N4
SAMCO
ROM Address Select line
5N2
SCCO
Signals new Condition Code available
4G8
SCLRI/O
System Gear
14A5
SETRLCO
Sets CPU to CS03l as a result of JAM
IM5
SINO
Single Step Clock switch:nonnally open contacts
118
SINC
Single Step Clock switch:nonnally closed contacts
119
SLMDRl
Select MDR
3E8
SLYDD1
Select YDD
4M2
SPSW1
PSW Select line
4M3
SR280:3l0
Status Register Bits 28:31
Sheet 4
SRCLK1
Status Register Clock
4H3
SSEL011 :041
Destination Register Select lines
Sheet 4
STRTl/O
Module Start Signal
14M5
SX280:310
Second Index field
Sheet 2
SX2NZI
Secondary Index field is non-zero
3E8
SYNC-TP
Test Point: Match Address
IN6
TENO
Trap Address enable
12J4
TKILLO
External TP for inhibiting clock
13Ml
TRAP121
Interrupt Trap Bit 12
12H8
TRAPl30: 150
Interrupt Trap Bits 13:15
Sheet 12
UlR240:310
User op-code
Sheet 8
USR280:310
User Source Register Select lines
Sheet 2
VCCO
Overflow. Condition Code
4D7
VFLGI
Overflow flag
4F7
XMTCHI
ROM Address compares to Match Address
IH6
XSOI0:040
Destination Register Address
Sheet 4
YDCLKO
User Destination Register Gock
2E2
YDPIFO
YDP1 enable
3E3
102
01-078A21 R03 4/77
MNEMONICS
MEANING
SCHEMATIC
LOCATION
YDX28 I :311
User Index field
Shect 2
YS280:310
User Destination Register
Shect 2
YSIXO
Selects YSI/YDI to B Bus
3S5
OI-078A21 R03 4/77
103
16.3 CPC Mnemonics, Schematic Drawing 35-555008
MEANING
MNEMONICS
SCHEMATIC
LOCATION
AOOO:310
A Bus
Sheet I
AADOOO:040
A Stack Address Bus
Sheet 4
AAD051
A Stack Address Bit 5
Sheet 4
AKLO
A Stack PSW suppress
4Gl
ASELOOI :041
A Bus Select Bus
Sheet 4
ASTKNO
A Stack enable
4K4
BOOO:310
B Bus
Sheet 2
BADOOO:040
B Stack Address Bus
Sheet 4
BADOS1
B Stack Address Bit S
4L2
BKLO
B Stack PSW suppress
4G2
BSELOOI :041
B Bus Select Bus
Sheet 4
BSTKNO
B Stack enable
4KS
M37XO
Floating-Point Module Select
4Al
PSW260
PSW Bit 26
SH6
PSW270
PSW Bit 27
SH7
RWCO
Read/Write Con trol
SA2
SOOO:310
S Bus
Sheet 3
S2BO
S Buffer to B Bus Over-ride command
4A4
S37XO
Stored floating point Module Select
4A3
Sheet 3
SBOOI :311
S Buffer outputs
SODDO
S Bus Odd Register command
5F2
SSELOOI :041
S Bus Select Bus
Sheet 4
SSELXO
Stack Load Select
4G4
STWRTI
Start Write command
5A3
WSELI
Write Select
5K4
WSELIB
Write Select buffered
5N9
WCLKO
Write Clock
5H5
XCLKO
Buffered Oock
5C4
104
01-078A21 R03 4/77
16.4 ALU Mnemonics, Schematic Drawing 35-53SDOS
MNEMONJ[CS
MEANING
SCHEMATIC
LOCATION
AOOO:310
A Bus
Sheet 10
ACLKI/0
ALU Clock
Sheet 6
ACLKA/BO
ALU Oock
Sheet 6
ACNT051
Bit 5 of iteration counter
4N4
ACRYI
Carry from iteration counter
4R4
AGLOOI
Bit 0 A input to shift left multiplexor
SR7
AGL311
Bit 31 A input to shift left multiplexor
SHS
AGROOI
Bit 0 A input to shift right multiplexor
Sheet S
AGROSI
Bit S A input to shift right multiplexor
Sheet S
AGR161
Bit 16 A input to shift right multiplexor
Sheet S
ALDOl :311
A latch outputs
Sheet 10
ALOGI/0
Logic mode
9MS
ALSOSO: 110
Shift multiplexor outputs Bit 8: 11
Sheet 12
AMOOI :311
A multiplexor outputs
lOC5
AMODOOI :031
Function select control for ALU
Sheet 9
ARITHI/0
Arithmetic shift
lL6
ASOOO:030
Arithmetic State
Sheet 5
ASOOI
Arithmetic State
5FS
ASAI
Arithmetic State register A
5N5
ASBO
Arithmetic State register B
5N5
ASIGNI/O
Stored sign of A Bus operand
3G4
AWCl
Add with Carry instruction
lL2
AXBl
Stored Exclusive-OR of Sign bits of A and B operands
6E3
BOOO:310
B Bus
Sheet 10
BGOOI :311
B gate outputs
Sheet 10
BGTRI/0
B Operand is Greater in CAE instruction
602
BSIGNI/O
Stored Sign of B Bus operand
6E3
CAEI/0
Floating Point Compare and Equalize instruction
III
CCCO
CC Bus - C bit (carry)
2NS
CCCLKO
Condition Code Clock
2E3
270
Carry in Bit 27
230
Carry in Bit 23
190
Carry in Bit 19
CIN 030
Carry in Bit 3
150
Carry in Bit 15
110
Carry in Bit 11
310
Carry in Bit 31
01-078A21 R03 4/77
Sheet 9
105
MEANING
MNEMONICS
SCHEMATIC
LOCATION
COUTOOO
Carry out Bit 0
9H9
COUTOBO
Carry out Bit
B
9EB
DFLTO
Divide Fault
3E2
DVI/O
Divide instruction (fixed or floating point)
lL7
EAO
Floating Point Add instruction
IF2
EASI
Floating Point Add6Subtract instruction
IL2
ECOUTO
Exponent cany
8D1
EDI/O
Floating-Point Divide instruction
ILl
ECI
Floating Point Compare instruction
lL3
EMI/O
Floating Point Multiply instruction
lL4
EMDI/O
Floating Point Multiply /Divide instruction
lL4
ESO
Floating Point Subtract instruction
IF2
FAXBl
Stored Exclusive-OR of A and B Sign bits
9N6
FDI/O
Fixed Point Divide instruction
ILB
FMI
Fixed Point Multiply instruction
ILB
FMDI/O
Fixed Point Multiply /Divide instruction
lLB
FSELOOO:020
Function Code from CPU
Sheet I
FSTCNTI/O
First Count of arithmetic state 2
6FB
FXSOll
Bit 1, exponent sum
BE6
FXS021 :071
Exponent ALU outputs
Sheet
GOO 1
Carry generate Bit 0
IOF2
G041
Carry generate Bit 4
llF2
GOBI
Cany generate Bit
Gl21
Carry generate Bit 12
13F2
Gl61
Carry generate Bit 16
14F2
G201
Carry generate Bit 20
I5F2
G241
Carry generate Bit 24
16F2
G281
Carry generate Bit
2B
17F2
GATECCI
Gate Condition Code
3G3
GATEECI
Gate Floating point Condition Code
3R7
B
B
12F2
GeCO
CC Bus - G bit (greater than)
2Rl
GLOWI
Carry generate Bits 16 to 31
9G3
Shift Multiplexor Output control
Sheet 7
GRWCO
Generate Read Write control
6KB
GXO
Shift Multiplexor output control
7HB
GXLSBO
Shift Multiplexor output control
7H8
INHAI
Inhibit A Bus
7E6
GNPO
GNMO
GNO
106
}
01-07BA2l R03 4/77
MEANING
MNEMONICS
SCHEMATIC
LOCATION
INHBO
Inhibit B Bus
7E6
INHXI/O
Inhibit exponent
7H5
KSIGO
Function Code Extension bit from CPU
lA7
LCCO
CC Bus - L bit (less than)
2RI
LOGI
Logical shift
lL5
Ml/O
Multiply look-ahead bit
7R6
MOO
Multiply /Oivide instruction (fixed or floating point)
lL7
MFINO
Module Finish signal
2J4
MQOO1:3 1 1
MQ register outputs
Sheet 10
MQCLKO
MQ register Clock
6R7
MQGOOI
Bit zero input of MQ Shift register
7S8
MQG31 1
Bit 31 input of MQ shift register
7S9
MPO
Multiply instruction (fixed or floating point)
IL7
MSELOOO:020
Module Select code from CPU
Sheet 1
MSIGO
Module Signal (ALU=carry nag)
2R2
NLRZO
Normalize
SC4
OCMPI
Control signal (one's complement) for CAE instruction
8E2
OCMPLI
Stored Control Signal - one's complement
6E3
OFLl/O
Exponent Overflow
4E2
POOl
Carry propagate Bit 0
lOF2
P041
Carry propagate Bit 4
llF2
P081
Carry propagate Bit 8
12F2
PI21
Carry propagate Bit 12
13F2
PI61
Carry propagate Bit 16
14F2
P20t
Carry propagate Bit 20
lSF2
P211
Carry propagate Bit 24
16F2
P281
Carry propagate Bit 28
17F2
PLOW 1
Carry propagate Bits 16 to 31
9G2
ROTI/O
Rotate shift
IL6
ROTRO
Rotate Right shift
IL5
RWCO
Read Write Control signal to CPU
6M8
RWCAI/O
Read Write Control
6F7
RZROI
Remainder Zero flip flop
7Gl
SOOI :311
ALUsum
Sheet 11
SOOO:310
Sum Bus
Sheet 10
SAPI/O
Shift multiplexor select control
7H4
SBGTRI/O
Set B Greater flip flop
3H3
SCOlO:050
Arithmetic Shift Count
Sheet 4
SELAOA/B
A multiplexor select control
8R5
SEPI/O
Shift Multiplexor select control
7E5
SETZAO
Inhibits Bits 0:8 in detection of zero sum (ZSUMl)
IOH2
01-078A21 R03 4/77
107
MEANING
MNEMONICS
SCHEMATIC
LOCATION
SGAETO
S Bus enable
7M2
SGCCO
Set Greater than Condition Code
3N7
SGROOI
Bit 0 S input to shift right multiplexor
8G9
SHFTI/O
Shift instruction
1L9
SLI
Shift Left control
7N4
SLCCO
Set Less than Condition Code
3N7
SOFLO
Set exponent overflow
8J8
SRI
Shift Right control
7N4
STRTO
Start signal from CPU
1A9
SUFLO
Set exponent underflow
8J8
SUMI/O
Add/Subtract mode
9K4
SVCCO
Set Overflow Condition Code
3L5
SWCO
Subtract with Carry instruction
lL2
TDFLTI
Toggle Divide Fault
6G9
UFLI/O
Exponent Underflow
4G6
VCCO
CC Bus - V bit (overflow)
2R2
XFRO
Forces S=A on ALU function control
9M5
XLOADO
Load pulse for exponent up/down counters
8G7
XOVFI
CAE Instruction; exponential difference is greater than five
8R4
XRPA/B/C/D
Pullup resister for unused logic inputs on IC's (1 k ohm to PS)
7GI
SXOIl:071
Expojent result (stored)
Sheet 8
XSIGNI
Sign of floating poin t result
3H6
ZSUMI/O
Sum is zero
]OJ4
108
01-078A21 R03 4/77
16.5 IOU Mnemonics, Schematic Drawing 35-539D08
MEANING
MNEMONICS
SCHEMATIC
LOCATION
Al
Output of address decoder for TTY
9H3
AI60:3lO
A Bus low
Sheet 3
ACI/3
12 VAC inputs to Primary Power Fail Detector
15B2
ACKOOO:030
Acknowledge interrupt MPX Channel
Sheet 6
ADAI
Address flip-flop for TTY controller
9M3
ADBI
Address flip-flop for Display
9M4
ADRSO
Address Control line, MPX channel
6N4
ADSYNAO
Address SYNC for TTY controller
9L2
ADSYNBO
Address SYNC for Display can troller
9L4
ARMI
In terrupt Arm flip-flop for TTY
917
ATNO
Interrupt Attention for TTY
12G7
ATSYNO
Attention SYNC pulse for ACK address
12N9
Bl
Output of address decoder for Display
9H4
B160:3W
B Bus low
Sheet 3
BAI/O
Buffer Active flip-flop (sets when buffer is loaded, cleared when
buffer unloaded)
8E8
BLKI/O
Serial feedback block flip-flop
9N6
BROOI :071
Buffer Register-eight stages, (active only in Read mode)
Sheet 11
BRKO
Break detect signal status Bit L
8H7
BSYI/0
Busy signal (Status Bit 4)
CA310
Least Significant Bit of address from CPU (byte steering bit)
IB5
CATNI/O
Console Attention flip-flop
lOGS
CCCO
CC Bus - C Bit
7R4
CL070
Primary Power Failure Control line
14K7
CLDRO
Clear line for D Bus receivers
5K5
CLKO/ll
Timer clock pulses (11 for character)
121.4
CLRAO
Clear line for cycle counter
5R7
CLRCO
Clear line for timing, flip-flop
5H8
CLRSTO
Clear ST flip-flop
12E4
CMCRO
Clear MCRll: 15
7C7
Clear lines for Machine Control Register
Sheet 7
CMDO
Command Control line, MPX channel
6N4
CMGAO
Command line for TTY controller
lON4
CMGBO
Command line for Display controller
10N5
DOOO: 150
D Bus
Sheet 4
DAO
Data Available Control line, MPX channel
6N4
DAGAO
DA line for TTY controller
lONl
CMCRllO
}
CMCR130: 150
01-078A21 R03 4/77
109
MNEMONICS
SCHEMATIC
LOCATION
MEANING
DAGBO
DA line for Display controller
10N9
DBENI
D Bus Enable
6G4
DCKHI
Oock for D Bus receivers high
6A5
DCKLl
Oock for 0 Bus receiver low
6B5
DDI/0
Device data signals from Schmidt Trigger receiving circuit
l6E7
DFSTI/0
Timing Control flip-flop, Detccts DSTRT
5E5
DLOO:070
Buffered D Bus
Sheet 8
DLOOX
Strap to TTY address decoder
9E4
DMPFO
Data Memory Parity Fail (from MBC)
7E4
DRO
Data Request Control line, MPX channel
6H4
DROOl: 151
D Bus receivers
Sheet 6
DR GAO
DR line for TTY con troller
ION2
DRGBO
DR line for Display controller
ION8
DRNI/O
Start Bit stage of Shift Rcgister (controls transmit line in Write mode)
I1M6
DSPLYO
Display controller interrupt line to CPU
IOJ8
DSTRTO
Start D Bus operations
5H9
5D6
DSYNI
DTI/0
Device Transmitting flip-flop (set when RCV loop starts the timer)
IlG7
DTMGO
Delayed TMG signal
12C4
DUI
Output of Device Unavailable detector-Active for TTY in DEF /local modes
16J5
DXI
Serial data input to Shift Register (line data in Read mode/all ones in
Write mode)
I1B2
EBLl
Interrupt Enable flip-flop for TTY
9J6
EOCI/O
End of character (output of character counter)
12N6
}
Enable signals for S Bus high
Sheet 2
}
Enable signals for S Bus low
Sheet 3
ENT30
Enter Time period T3
5N2
EPFI/0
Early PPF Timer (1 millisecond)
14L2
Complimentary pulsed signals from Display Console
lOA5
Examine bit of TTY status
8J8
Auxiliary initialize inputs
14A3
FLSYNO
False SYNC signal (0 Bus operation)
14K8
FPOWO
Decoded Power Down function
7C7
ENSHAO
ENSHBO
ENSHCO
ENSLAO
ENSLBO
ENSLCO
ESNCO
ESNOO
}
EXI
EXAO
EXBO
110
}
01-078A21 R03 4/77
MNEMONICS
MEANING
------
SCHEMATIC
LOCATION
FSEL 00:03
Function Select lines from CPU
Sheet 1
FSTPO
Stop function-terminates SHFT pulses
12M5
FTXl/O}
Displays controller SYNC generation flip-flops
Sheet 13
FWAITI/O
Flip-flop for load Wait function
7E8
GACKO
Gate Acknowledge function
6G2
GADRSI
Gate ADRS line
6R3
GeCO
CC Bus - G Bit
7R2
GeMDI
Gate Command
6M3
Gate Data Available line
6M3
Gating on D Bus signals
Sheet 4
GDINI
Gate Data In
6K3
GDOUTI
Gate Data Out
6M3
GDRI
Gate Data Request
6H3
GLABI
Gate LA and LB signals
13G4
GLITCHO
Start Glitch signal - clears TMG 1
12B2
FTYI/O
GDAI
GDHBHO
GDLBHO
1
GDLBCO
GDAO
J
GPI/O
Gate POUT function
lK6
GPXO
POUT function finished signal
IN6
GSRI
Gate Status Request
6J3
GSTPI
Gate STP (test point)
15K8
GSTRTI
STRTO gated with IOU decoded address
IN8
HWI/O
Halfword test line - MPX channel
512,5K2
INCRI/0
Increment/Normal flip-flop
10D2
INITO
INT key line from Console
14A3
INTRI
TTY interrupt flip-flop
12E8
IRLMPO (only on Mod. 8/32)
Instruction Read Local Memory Parity Fail (from MBC)
7E3
Cycle counter flip-flops
Sheet 5
KCO/l
Timing Control flip-flop, Control line timing
5F3, 5H4
KDI/O
Timing Control flip-flop Control line timing
5M6
KSIGO
Function code line from CPU
IB4
KSYNI/O
Timing Control flip-flop, SYN stretch
5H8
KTI/O
Cycle counter-Terminate flip-flop
5N6
KTM
Test point. Ground to kill Start Timer
14B5
KA
KB
KY
KX
}
}
01-078A21 R03 4/77
5L8
Johnson Counter flip-flops for address cycle
5M8
111
I
MEANING
MNEMONICS
}
LBO
LAO
SCHEMATIC
LOCATION
13J5
Signals controlling the loading of display registers
13J6
LCCO
CC Bus - L Bit
7R2
LDBRO/I
Load Buffer Register pulse (active in Read mode only)
8C7
LDWAITO
Decoded Load Wait Indicator function
7C8
LESYNI/O
Timing Control flip-flop Detects leading edge of SYNC
5H2
MCROOl:09l
MCR straps
Sheet 2
MCRl10:150
Machine Control Registers
Sheet 7
MFINO
Module Finish line to CPU
7N8
MMFO
Machine Malfunction interrupt line to CPU
7G6
MSELOOO:020
Module Select lines from CPU
IC8
MSIGO
Module Finish line to CPU - Tests the state of HW line
7N9
MSYNI
SYNC from Display or TTY controllers
1108
MTAOII}
Master TTY Timer (440HZ Output)
1213
Timer clock counter (lIOHZ Output)
12H4
Overflow error flip-flop
8GB
Pulse output functions (test points)
Sheet I
PFDTO
Power Fail Detector output
l4D3
PFl/0
Primary Power Fail flip-flop
14H5
POFFO
Power Off line from Console switch
14A3
MTBO/l
MTCI
MTDI
}
OVI/O
PAO
PBO
PCO
PD~
}
POUTO
Pulse Out function
7C7
PPFO
Primary Power Fail interrupt line
14K6
RACKO
Receive Acknowledge interrupt signal
12F9
RDWDHI
Read-Write Data Halfword
6G4
RN
Negative side of RECEIVE loop
l6H8
RP
Positive side of RECEIVE loop
16H6
RSTO
Reset line for Display controller
IOG3
S160:230
S Bus high
Sheet 2
S240:31O
S Bus low
Sheet 3
seco
CC Bus - Strobe line
7R6
SCLRO/I
System initialize line MPX channel
15K2
SDOOI :071
Bi-Directional byte bus to Display Panel
Sheet 8
SELSHO/l
Select signal for S Bus high
2Nl
112
01-07BA21 R03 4/77
MEANING
MNEMONICS
-----SELSLl
SHIO
SLOO
Select signal for S Bus low
}
SCHEMATIC
LOCATION
3F2
1317
Signals for sensing Display Console's Switch Register
1318
SHFTI/O
Shift Register pulses, nine per character
12N4
SKTI
Set KT flip-flop
5N3
SMCRO
Sense MCR 00: 15
7C7
SMFINO
B Bus operation finished signal
IL9
SNGLO/1
Single mode flip-flop
10G8
SRO
Sta'tus Request Control line, MPX channel
6H4
SROOI :071
Shift Register-eight data stages
Sheet 11
SRGO
SR for Display Panel
ION6
SRGAO
SR line for TTY controller
ION3
SRGBO
SR line for Display controller
ION7
SSGLl/O
SNGL key line from Display Console
lOA8
STO
Start idle Timer flip-flop
12E4
STCt
Start gating on S Bus (non-D Bus operation)
2H4
STCLKll
Clock for ST flip-flop
12C3
STDt
Start gating on S Bus (D Bus operation)
2H5
STESI
Set TESYN flip-flop
STMAO
Start Timer
14F5
STMBO/l
Start Timer flip-flop
14G8
STPI
System Stop flip-flop
14N5
STPIA
Buffered STPI (test point)
14N5
STPFI/O
Start Power Fail Timer latch
14H3
STPFRO
Start Power Fail routine
14F2
STRTO
Module Start line from CPU
lC7
STTI
Start display controller timer
13E3
SYNO
SYNC test line - MPX channel
5A5
SYNO
SYNC test line MPX channel
lIG9
TACKO
Transmit Acknowledge interrupt signal
12N8
TBO
Delay Control line, flip-flop
5B4
Tel/O
Timing Control delay pulses
59B
TOU
Device Unavailable line from TTY
16H4
TERMI
Timing Control flip-flop, Detect trailing edge of SYNC
5E6
THWO
Decoded Test Halfword function
7C7
TMGO/I
Timing gate control flip-flop
12Dl
TMGIA
Timing gate test point
12NI
TN
Negative side of SEND loop
16Hl
TP
Positive side of SEND loop (TTY)
16H3
01-078A21 R03 4/77
113
TRNSO
TXO/I }
SCHEMATIC
LOCATION
MEANING
MNEMONICS
16Fl
TransmH signal to SEND loop
13G2
Display controller timer
1313
TYO!1
VCCO
CC Bus - V Bit
7R4
WAIt 1
WAIT light control
1319
WRTI!O
Write mode execute flip-flop for TTY
1203
WTI/O
Write mode storage flip-flop for TTY
9N7
XAI/O
Flip-flop for gating LA and LB
13FS
XCI/O
Flip-flop for gating SH, SL
13F7
XLC1!O
Line check flip-flop (checks for START glitches and break conditions)
IlM7
XPFI/0
Power Fail stop timer
14LS
XRPA
Pull-Up resistor
13FS
XRPB
Pull-up resistor
SL7
XRPD
Pull-up resistor
9M3
XRPE
Pull-up resistor
7ES
XRPF
Pull-Up resistor
7Fl
114
OI-07SA21 R03 4/77
APPENDIX 1. MODULE 3 OPERATIONS
The single precision floating point circuits of the ALU, called the FALU and addressed as Module 3, become active when the
FALU recognizes its address on the Control Bus, provided the proper strapping has been supplied through the optional Writable
Control Sitore (WCS). When the FALU becomes active the CPU signals start (STRT), and the function to be implemented is
determined from the Control Bus. For FALU functions, the ALU clock is enabled and a hardware sequence is entered to perform the required operation. The shift gates are used to shift the A Bus or the S Bus right or left back into the A latch and on
to the A Bus again as determined by the ALU algorithms.
The register stacks of the processor CPU-C board contain 16 32 bit single precision floating point registers (FRO: F).(MSELOOO.
MSELO 111.MSEL021) of the Module Select Bits in the micro-instruction select the FR registers. Table A-I shows the functions
perfonned by the FALU.
TABLE A-1. MODULE 3 (FLOATING POINT) OPERATION
MODULE 3 (FLOATING POINT)
F FIELD
0
0
0
0
Not used
0
0
0
1
Load
0
0
1
0
Subtract With Carry
0
0
1
1
Add With Carry
0
1
0
0
Not uSI3d
0
1
a
1
Compare
0
1
1
0
Not used
a
1
1
1
Not uSl3d
1
0
0
Subtract
1
0
a
a
1
Add
1
a
1
0
Not uSi3d
1
0
1
1
Not used
1
1
0
0
Compare and Equalize
1
1
0
1
Not uSi3d
1
1
1
0
Multip~y
1
1
1
1
Divide
When Module 3 is operable, an additional ALU arithmetic state is designated as shown in Figure A-I (Compare to state diagram,
Figure 19).
Ol-078A21 R06 5/78
Al-l
STRTO
EASl (NRLZ1+ZSUM1) + ZSHFTl
o
U
o
S
a:
C/)
«
w
(:;l
FMDl + EDl
Figure A-1. ALU State Transitions, Including Module 3.
The logic determing the floating point state transitions are listed in Table A-2.
AI-2
OI-078A21 R06 5/78
TABLE A·2. STATE REGISTER LOGIC, INCLUDING MODULE 3.
TRANSITION
ASOOl
TO
ASOll
ASA LOGIC
COMMENT
ABORT SHI FT IF SHI FT CaUNT IS ZERO.
FL T. PT. ADD/SUB. CO MP LETE IF NO
MANTISSA OVERFLOW A ND RESULT IS
NORMALIZED OR ZER O.
UNCONDITIONAL TRA NS FER IF NOT
FL T. PT. ADD/SUB.
J = EASO'ASOOl
J = EASHCOUT081 +
NRLZO'ZSUMO)
ASOOl
TO
AS061
ASOZl
TO
AS031
ASC LOGIC
J = ZSHFTl +
EAS1·COUT080·
(NRLZl + ZSUM1)
ASOOl
TO
AS021
AS021
TO
AS011
ASS LOGIC
J = EASHCOU081 +
N R LZO· ZSUMO)
FL T. PT. ADD/SUB. RES UL TS IN MANTISSA
OVERFLOW OR UN-NO RM ALiZED
MANTISSA
J = ACRY1'NRLZl
J = ACRY1'NRLZl
K = ACRY1'NRLZl
J = ACRY1'NRLZO
K = NRLZl
-----
---------
SH 1FT COMP LETE OR F LT . PT. MULT.
COMPLETE AND NORM AL IZED.
FIX PT. MULT./DIV. CO MP LETE.
K = FMDO+EDO
FL T. DIVIDE COMPLET E.
FLT.MULT.RESULTSI N lIN-NORMALIZED
AS021
TO
AS061
K = ACRY1'NRLZl
J = NR:LZO'ACRY1+
ED1'COUT081'
FSTCNTl
MANTISSA. FIRST ITEf~A TION OF FLT.
DIVIDE REVEALS DIVI DE ND LESS THAN
DIVISOR.
K = NRLZl
FIX MULT/DIVIDE-FIR ST HALF OF RESULT
AS031
TO
AS011
WRITTEN INTO DESTIN AT ION REGISTER.
FLT. DIVIDE - MQTRA NS FERRED TO AL.
K = GRWCO'AS031
AS061
TO
AS021
FLT. DIVIDE - DIVIDE ND HAS BEEN MADE
J = ED1·FSTCNTl
SMALLER THAN DIVIS()R . CONTINUE
DIVIDE.
-AS06'1
TO
AS011
AS011
TO
ASOOl
FL T. PT. RESULT HAS EI EE.N NORMALIZED.
J = AS061'NRLZl
K = NRLZl
RESET TO ASOOl WHEN
RESET = STRTl
RESET = STRTl
RESET = STRTl
c PU RENIOVES
STRT1.
The floating point simple functions arc Load (ELO), Subtract with Carry (ESWC), Add with Carry (EAWC), and Compare (EC).
These instructions are floating point instructions only in the sense that they manipulate floating point data. The hardware implementation is identical for that of the fixed point instructions and more of the exponent hardware is used.
OI-078A21 R06 5/78
Al-3
Floating Point Instructions
. Compare and Equalize
The Compare and Equalize instruction is always performed prior to a floating point Add/Subtract. The instruction
effectively aligns the exponents of the two operands by shifting the mantissa of the smaller operand.
To simplify the logic for determining the larger operand, BOO is inhibited (forced to a one) during ASOOI. The difference
of the two operands is taken (A-B), and the BGTR flip-flop (6C2) is loaded with the information (SBGTRl) determining
the larger operand. The logic for this determination (303) is:
SBGTRI
= AOO} Eb)BOOI
SBGRTI
= AOOOEb)SOOJ
$S001
but since BOO 1 = 1,
If the BGTR flip-flop is set, B is the larger operand and A is shifted, or if BGTR is reset, A is the larger operand and B is
shifted. The exponential difference is computed simultaneously and this result becomes the hexadecimal shift count.
However, if this shift count exceeds 510, the operation is abandoned as significance is shifted out of the mantissa, the
result being zero. The four bit magnitude comparator (S12) compares the exponent difference to 510 and XOVFI (SN4)
determines if the shift count is less than 510. One additional problem occurs if the exponent of B is greater than the
exponent of A. The difference results in a 2's complement number and does not reflect a true shift count. Should this
occur, OCMPI (807) is active and complements the difference and inhibits ACNT for one shift cycle in AS021, yielding
the correct number of hexadecimal shifts.
During AS021, either the A or B Bus is inhibited (forced to all ones) and a subtraction is performed. The net result is to
transfer the operand which is to be shifted into the AL register. Thereafter, the operand is shifted hexadecimally to the
right according to the shift count. When the shift is complete (ACRY1), the transition is made to ASOII where the result is
gated to the S Bus with the sign and exponent field zero filled. When the Add/Subtract instruction follows, the CPU always
gates the larger operand onto the A Bus and the shifted operand to the B Bus.
The algorithm for Floating Point Compare and Equalize:
ASOOI
SUMO-I
BGOOI-I
MB
AOI :07.6BOI :07
FXS05 :07-ACNT05 :07
if XOVFO, ASOO I-AS021
if XOVFI, ASOO I-ASO I I
AS021
if ACRYI, AS021-ASOll
{ if OCMPLI. ACNT-ACNT
ifOCMPLO, ACNT :EI-ACNT
ifBGTRl, AOO:31-ALOO:31
if FSTCNTI
ifBGTRO, BOO:31-ALOO:31
{
if FSTCNTO
ACNT~I-ACNT
0-AL08:1}
ALOS:27-AL12:31
ASOll
ifXOVFl, 0--SOO:31
if XOVFO, 0-SOO:07, ALOS:31--S0S:31
MFIN--I
Al-4
01-07SA21 R06 5/78
Floating Point Add/Floating Point Subtract
One additional characteristic of floating point arithmetic beyond that discussed in the Compare and Equalize algorithm
arises from floating point notation. The mantissa is represented by sign and magnitude. Positive numbers have a Sign bit
equal to zero and negative numbers have a Sign bit equal to one. However, unlike fixed point notation, negative numbers
are not represented in 2's complement format. Therefore, when performing an addition with unlike signs, a subtraction
must be performed to obtain the true sum. Similarly, when performing a subtraction with unlike signs, to obtain a true
difference an addition must be performed. This is accomplished by the FAXBl address bit to the ALU ROM. The FAXBl
flip-flop (9N6) is set during AS021 of the Compare and Equalize instruction and the logic for this bit is AOOI E9 BOO I.
In ASOOl, the mantissas of A and B are added/subtracted and the cxponent of A is presented to the exponent up/down
counters. If adding (SUMl), it is possible to overflow the resultant. mantissa (COUT081) and a correction cycle is executed
in AS061. If subtracting (SUMO), it is possible that the result may not be normalized and a normalize shift is executed in
AS061. Should neither of these conditions arise, the transition to ASO 11 is direct and the result is gatcd to the CPU.
The algorithm for Floating Point Add is:
ASOOI
if FAXBO, SUMI-l,
A~B
if FAXBl, SUMO-I, MB
AOI :07-XSOl :07
SOO:31-ALOO:31
if NRLZO·ZSUMO + COUT081·SUMl, ASOOI---AS061
if (NRLZl+ZSUMI )·SUMl·COUT080, ASOOl-e.-ASOll
AS061
if SUMOl 0-e.-AL28:3 I
All 2 :31---AL08 :27
XSOI :07-I-XSOI :07
0_AL08:10
if SUMl
I-All I
{
AL08:27---ALI2: 31
LXSOl: I :07+1-+XSOl :07
if NRLZ I, AS061---ASO 11
ASOll
if ZSUMI, 0-SOO:31
AL08:31_S08:31
if ZSUMO
01-078A21 R08 11/78
{
XSOI :07-S01 :07
AOO-SOO
AI-5
S07:3D--rALD8 :31
I
'
(ADD + BOD)' ZSUMD-ALDD
ifMI
{ MQDD:39-"MQDI :31
S31-M
fO
1'
ALD8:3Dr,: A. LD9:31
D-ALD
ifMD
{
MQOD:3~-MQDl :31
AL31-MQOD
ASD6l
ALl2:311...ALD8:27
D-AL2~:31
(XSt:.l )txs
if NRLZ ~, ASD61-ASD II
ASDII
ALD8 :31t-..SD8 :31
ifUFLO
{
XSD I
:07~SD 1:0.7
AD()$BD1---SDD
if UFLl. D-SDD:31
!
l-MFIN
Floating Point Divide
Floating Point Divide is implemented by continuously subtmc ing the mantissa of B from the mantissa of the shifted
partial remainder (AL) to ascertain which is the larger. If the p rdal remainder proves to be the larger, the quotient digit
(Q31) is set to a one and the left shifted difference is taken as h~ new partial remainder. If the partial remainder is less
than the divisor, the partial remainder is shifted left and the cycle is repeated.
Since the mantissas are true magnitude, the larger mantissa is r adily detected by COmD81. However, if significance is
shifted out of the nth partial remainder, the n+l partial remain et is, by definition, larger than the divisor. Therefore, the
true logic for the quotient digit is:
Q311=comD8l + ALD71
where AL07l detects a one being shifted out of the partial remaiJder.
r
The expolilent result is obtained by subtracting the divisor expolent (BDI :0.7) from the dividend exponent (ADI :0.7) and
the sign bit is derived from ADD 1 @BDDI.
;
On the first divide cycle, if COmD81 is detected, it is necessart to execute a correction cycle to be able to represent the
results in 24-bits plus the sign. The mantissa (of the partial r~mainder) is shifted right one hexadecimal digit and the
exponent is incremented. On the next clock, the ALU returns to .f\SD21 and continues the divide iterations.
When the divide has been completed (ACRY1), the ALU goes toiASD3l, and gates MQ to the AL register and then goes to
ASD11.
The algorithm for Floating Point Divide is:
ASDDI
SUMO-... 1
ADD :31-ALDD :31
AD 1:0.7 t:.BD 1:0.7 ....XSD 1 :0.'"/
71O-ACNT
ASDDI-ASD21
if ACRYl, ASD2l-ASDI]
if FSTCNTl'Q311, ASD21-ASD61
ACNT~
I-ACNT
ALt:.B
DI-D78A21 RD6 5/78
Al-7
rr-
MQ31
Moo1:31
if Q31I
MQOO:30
o-AL3l
ALOI :31
MQ31
MQOI:31
if Q310
MQOO:30
. 0 ...AL31
ALOI :3.1
AS061
XSOI
:07~
I-XSOI :07
O..... ALOB: 1'0
AL07-ALlI
ALOB:27 .....ALl1:3 )
AS061-AS02 I
AS031
MQOO:3 ) -ALOO:31
AS03 I-ASO I I
ASOIl
ALOB:3 I-SOB :31
XSOI :07--S01 :07
AOoomOO--soo
MFIN __ I
Arithmetic Iterative Counter (ACNTOI :05)
The iterative shifting of the ALU is controlled by a modulo 32 counter which is enabled during AS021. It is in AS021 that
the iterative operations of shift and Multiply/Divide occur and this cou ter is used to determine completion of the operation
and, therefore, the time at which transition to the next arithmetic stat should occur. For 'floating point operations, the counter
is used in two different modes as described below.
1. Floating Point Multiply/Divide
For these instructions, the counter is loaded with a count of 7} 0 0 allow for seven fewer iterations (the size of the
exponent field). For floating point Multiply, when the counter reache a count of 3010 the transition is made from AS021
to ASOll if the result is normalized, or to AS061 if the result is ot normalized. For floating point Divide, when the
counter reaches a count of 3110, the transition from AS021 to AS03} is made.
2. Compare and Equalize
This instruction is always performed prior to execution of a floating oint Add/Subtract instruction. It is used to align the
exponents of the two operands by shifting the mantissa of the 1 sser operand. The smaller operand is shifted right
hexadecimally an amount determined by the difference of the two xponents. The shift count, therefore, is loaded from
FXS051 :071 which is the difference of the exponents. It is possible that this difference may re' "It in a 2's complement
number. Should this occur, the 1's complement of this result is loade into the counter, and the counter is inhibited on the
first count of AS021. This is accomplished by the logic at gate 09 03. If this difference should result in a shift count
greater than 510, the operation is aborted since this would result in shifting significance out of the mantissa. Should this
occur, a signal called XOVFl forces a shift count of zero and the operation is aborted. When the shift is complete, the
counter reaches a count of 3110, and ACR YI forces the transition from AS021 to ASO II.
AI-B
01-07BA21 R06 5/7B
I
Arithmetic Condition Code
The ALU galtes appropriate Condition Code flags to the CPU for all ALU functions. When the ALU senses its address and
receives a start (STRT) it signals the CPU with SCCO that a new CO!dition Code is availahle. Figure 18 (ALU Functional
Block Diagram) shows that the ALU Condition Code circuits consist f combinational logic which determines the resultant
condition of each instruction. These are latched in a register. The cloc which latches the Condition Code is gated in one of
two ways. For the simple functions (FSELOOO), the dock results fr m STRT, delayed an appropriate amount of time to
allow the ALU to complete its function. For complex functions FSELOOI), the dock is generated in ASOII at the
conclusion of an instruction. TIle Condition Code is then gated onto the bus through a tri-state multiplexor. The
representation of each flag is as follows.
I . VCCO (Arithmetic Overflow).
The logic for this flag is shown on Sheet 3 (SVCCO). It is enabled fIr fixed point Add, Subtract, and Divide; and floating
point Add, Subtract, Compare and Equalize, Multiply, and Divide. he flag is active for fixed-point Add/Subtract instructions when an overflow is determined by the logic:
ASIGNO-SOOI·(BGOOl+SUMI $ASIGNI·SOOO-(BGOOI G)SUMl).
The V flag is active for fixed point Divide on the first iteration of t e Divide if the quotient bit is determined to be a one.
This condition is called a Divide Fault (DFLT) and indicates that th~'lreSUlt cannot be contained in 31 bits plus sign. The V
flag also selts for fixed point Divide at the end of the divide algorith if the calculated sign of the quotient is incorrect. For
floating point instructions, all mantissa overflow is correctable y shifting the mantissa and adjusting the exponent.
Therefore, floating point overflow/underflow is a function of expon Ilt arithmetic alone. The V flag is set for the following
conditions:
.
J
•
OFLl ::: AMOII.(BGOII~Mli)·FXSOI lE!lSOFLl
OFLl = CAEI-XOVFI +AMOI~).(BGOII$EMI )·FXSOlOOSUFLl
2. CCCO (Carry).
I
I
.
The logic for this flag is shown on Sheet 2. It is enabled for fixed point Add/Subtract, Shifts, and Divide; and floating
point Compare, and Compare and Equalize. For fixed point Add/S~lbtract the logic is SUMI COUTOOt +SUMO COUTOOO
respectively. For floating point Compare, the logic is essentially,! SLCCO, and is used to signal the larger of the two
numbers. 'The C flag is also active for fixed point Divide to sign4l a divide fault and for floating point Compare and
Equalize to signal B as the greater operand (BGTRO). For Shift type: instructions, the C flag is the state of the last bit to be
shifted. ntis is selected by the eight to one (8/1) mUltiplexor whosc,iselect control lines are encoded to yield the proper bit
for every type shift. The selected bit is then latched by the flip-flop ~hown at 2E2.
It shoUld also be noted that the Module Signal (MSIGO) from the A~U is identical to CCCO.
I
3. LCC (Less TI1an Zero)
The L flag represents the sign of any arithmetic operation. For fu~lword fixed point operations it is the sign of the result
and for halfword shifts it is the sign of Bit 16 (SI61). For floatir;tg point operations, it is the sign of the floating point
result except where exponent underflow occurs or if the floating P?int result is zero. For these cases the L flag is forced to
the inactive state. For floating point compare the logic [(AOOI + B001 )$COUTOOOj·ZSUMO.
4. GCCD (Greater Than Zero)
This flag logically represents the occurrence of not less than zero and results not equal to zero and not exponential
underflow. This can be logically represented as follows:
GCCO = LCCO·ZSUMO-UFLO
01-078A21 R06 5/78
Al-9
Arithmetic Elements and ROM Control (Sheets 9: 17)
The heart of the ALU is built from the four bit arithmetic/logical elements (Perkin-Elmer Part Number 19-067) and a
format ROM lIsed to control them. Also used in conjunction with the ALU chips are a two level carry-look ahead scheme
(Perkin~Elmer Part Number 19-068).
The ALU is esentially controlled by 256X4 bit ROM. FSELOOI :031 and MSELOll address the ROM and determine the required control for the given instruction. ASIGN I, BSIGN I, and FAXB I provide needed additional information to insure
correct control fOffixed point Multiply/Divide and for floating point Add/Subtract. Shown in Table A-3 is a listing of ALU
control for floating point and the respective operations as a function of the address bits. One additional control bit (ALOG I )
is required to correctly specify logical operations from arithmetic operations. The logic for this gate (l2L2) is:
MSELO I O-FSELOOO-FSELO II
and essentially decodes the logical operations as per the FSEL field.
There are two levels of gating beyond the ROM ou.tputs on AMODOD:03. These are to provide two basic overide functions.
The first is included for the Compare and Equalize instruction. The ROM is coded for a Subtract to obtain the difference
of A and B. However, once we determine which is smaller. we wish to load the smaller mantissa into the A latch where it
can be shifted. The bus which is not to be shifted is inhibited (forced to all one's) and the transfer into the A latch is
accomplished by forcing a carry in and modifying AMODOO:03 to perform an addition. The gate which provides this
over-ride to ROM control is located at 9H4.
The second override function provided is to transfer A to S. This is accomplished by XFRO (12MS). The cases for which
this is necessary are as follows.
1.
In ASOOI for shifts and Multiply/Divide (fixed and noat) to transfer operand from the A Bus to the A latch.
In ASOII to transfer contents of A latch to the S Bus.
In AS031 in fixed point multiply to transfer contents of A latch to the S Bus.
In AS031 of divide (fixed and float) to transfer contents of A latch to S Bus under certain conditions (sec
divide algorithms).
2.
3.
4.
TABLE A-3. ALU ROM CONTROL FOR FLOATING POINT
....
....
(;
....
N
0
N
0
w
(/)
u.
0
::2:
0
::2:
co
<
Ci5
a:l
~
(;
-l
w
(/)
::2:
X
X
X
1
0
0
0
1
X
X
X
1
0
0
1
X
X
X
1
0
0
X
X
X
1
0
0
X
X
1
1
X
X
0
X
1
t?
z
t?
0
-l
(;
-l
-l
M
0
M
z
0
-l
0
0
....
(;
0
8
0
FUNCTION
COMMENTS
0
0
«
<
«
1
0
0
1
SUMl
FL T. PT. LOAD
0
0
1
1
0
SUMO
FLT. PT. SUB. WITH CARRY
1
1
1
0
0
1
SUMl
FLT. PT. ADD WITH CARRY
1
0
1
0
1
1
0
SUMO
COMPARE
1
0
0
0
0
1
1
0
SUMO
FLT. PT. SUB. - SIGNS ALI KE
1
1
0
0
0
1
0
0
1
SUMl
FLT. PT. SUB. - SIGNS DI FFER
X
1
1
0
0
1
1
0
0
1
SUMl
FLT. PT. ADD -SIGNS ALIKE
X
X
1
1
0
0
1
0
1
1
0
SUMO
FLT. PT. ADD - SIGNS DIFFER
X
X
X
1
1
1
0
0
0
1
1
0
SUMO
COMPARE AND EQUALIZE
X
X
X
1
1
1
1
0
1
0
0
1
SUMl
FLT. PT. MULTIPLY
X
X
X
1
1
1
1
1
0
1
1
0
SUMO
FLT. PT. DIVIDE
X
U.
NOTE: SUMl
AI-IO
= SUM,
w
(/)
u.
w
(/)
u.
w
(/)
u.
SUMO
<
::2:
::2:
--
= DI FFERENCE
01-078A21 R06 5/78
MQ Register
Ine Multiplier Quotient Register is used exclusively in Multipl~/Divide instructions. It is comprised of eight MSI four bit
'
shift registers which are capable of shifting left or right.
Gontrol for the MQ registers is located at 7N4. The A Bus is always "loaded into MQ in ASOO I by forcing both SR 1 and
SLI high. This is accomplished by clearing the Control flip-flop (7K4) with STRT1. For multiply, SRI is active to perform
right shifts and SLI is inactive. The opposite is true for divide when shifts left are performed.
AL Register and Shift Multiplexors
The AL registers are comprised of eight MSI quad 0 type flip-flops with double rail output. They are used in all complex
functions (FSELOOl) as a holding register for shift type operations.
Shifts alre performed by enabling one of four multiplexors depending on the type of shift to be performed. The multiplexor
outputs are OR-tied together and perform the following types of shifts.
1. n:
has SOOl :311 and MQ001 :311 as inputs. Does not shift; used for transferring MQ or A Bus to AL
register.
2. n+1:
has SOlI :311 and AL021 :311 as inputs. Performs left one shifts for Shift instructions and Divide
instructions. End points are determined by AGLOO 1 and AGL311 (Sheet 8).
3. n-1:
has SOOI :301 and ALOOI :301 as inputs. Perfonns right one shifts for Shift instructions and Multiply
instructions. End points are determined by AGROOI and SGROOI (Sheet 8).
4. n+4:
has AL121 :311 and AL081 : 271 as inputs. Shifts left hexadecimally (n+4) to normalize and shift right
hexadecimally (n-4) to correct overflow conditions or for Compare and Equalize instruction.
Exponent Arithmetic
Exponential arithmetic is accomplished through the use of two 19-067 4-bit arithmetic/logic elements. The exponent fields
(Bits 01 :07) of A and B are either added to or subtracted from each other, depending upon the instruction. The result is
loaded into an up-down counter, where the exponent may be incremented or decremented as required by post-nonnalization or overflow correction.
As previously mentioned (Section 3.2.4), in the Compare and Equalize instruction, the exponent difference may result in a
2's complement number and it was necessary to take the I 's complement of this for use as the shift count. This is accomplished by the Exclusive-OR gates connected to the ALU chips and the control signal OCMP1. The 4-bit magnitude
comparator is used to determine if the magnitude of the exponent difference is greater than 510' Should this be the case,
the Compare and Equalize instruction is aborted since significance would be shifted out of the mantissa. XOVFI detects
this case.
Perkin-Elmer uses excess 64 notation to express floating point numbers. As a result of an exponent addition or subtraction, the result becomes unbiased (i.e., the excess 64 is lost). To restore excess 64 notation to the exponent field in floating
point Multiply/Divide, the most significant bit of the exponent field is complemented. This is accomplished by the
Exclusive-OR gate whose logic is FXSO 11 <±) EMD I.
OI-078A21 R06 5/78
A1-11/A1-12
Z
i~··.·
e
WRITABLE CONTROL STORE
35-555F01 A20
Scptem ber 1975
METRIC
MODEL 8/32
WRITABLE CONTROL STORE
INSTALLATION SPECIFICATION
INTRODlICTION
The Writable Control Store (WeS) is an option which extends the flexibility of the user level Processor to that of the
micro-machine. The wes has the capability of storing and retrieving data within the control store, plus the capability of
dynamically altering control store instructions. In effect, the micro-programmer has the full capability of the user level
machine alt micro-processor speeds.
lli WCS
offers 2KB...of control store, sufficient to contain 512 instructions or some combination of instructions and data.
H is contained on the 8/32 CPC Processor board and requires typically 7 Amperes of 5VDC for power.
This specification provides the necessary information for the installation of the 8/32 Writable Control Store (WCS) option.
PHYSICAL CHARACTERISTICS (35-555 Board also includes 8/32 CPC)
Dimensions - Board 381 mm x 381 mm (15" x IS")
Weight - 2.72 kilograms (16 pounds) approximately.
Power - 5VDC at 10 Amperes maximum
Hardware
one
one
one
one
additional power supply regardless of expansion.
35-555FOI Board
17-360 front edge ribbon cable
illegal instruction ROM on 8/32 CPB ROM.
UNPACKING
When the WCS option is shipped with a system, it is installed at the factory. All cables and printed circuit boards should be
inspected to ensure proper seating.
INST ALLATION
Chassis
Slot 6 of the Basic Processor lower chassis is used for the 8/32 WCS option. The wes is mounted on the 35-555FOI board
(the 8/32 Processor CPC board).
35-555FOI A20 ROO 9/75
Power
An additional power supply, regardless of configuration, has to be used to provide an extra SVDC (PS) source for WCS. See
Figure I.
MODEL
8/32
TWIN
CHASSIS
Figure 1. 8/32 Processor With WCS and/or DFU Power Wiring
Cabling
The 17-360 cable connects Connector 4 on the CPB and CPC Processor boards.
Strapping
Refer to the Writable Control Store Maintenance Specification, 3S-SSSFOIA21 for strapping details.
Testing
Upon completion of the installation, and before power is applied, all voltages should be checked for shorts between each
other and ground. Proper operation of the WCS is tested by the execution of the WCS Test Progra •. _ 06-192.
Other
Illegal instruction ROM, 19-084F43, on the 8/32 CPB board (3S-S37) at Location OOC must be replaced by 19-084F48.
2
35-555FOIA20 ROO 9/75
2K WRITABLE CONTROL STORE
~~"'
.,."",',
L:
t.~
35-555FOI ROI A21
January 1978
METRIC
WRITABLE CONTROL STORE
MAINTENANCE SPECIF ICATION
'2
k.e
INTRODUCTION
The Writable Control Store (WCS) is an option which extends the flexibility of the user level Processor to that of the
micro-machine. The WCS has the capability of storing and retrieving data within the control store, plus the capability of
dynamically altering control store instructions. In effect, the micro-programmer has the full capability of the user level
machine at micro-processor speeds.
The WCS offers 1. KB of can trol store, sufficient to contain 512 instructions or some com bination of instructions and data.
i't1SCOri"ta~d~he unused half of the 8/32 CPC Processor boa~d and requires typically 7 Amperes of 5YDC for power.
This specifIcation describes the functional operation of the Model 8/32 Writable Control Store and provides information
necessary for its maintenance. This specification references epc Functional Schematic 35-555008. Perkin-Elmer schematic title, drawing number, and sheet number are located in the lower right corner of each sheet. Each sheet is zoned
alphabetically across the top and bottom margins and numerically down the side margins. These schematics are referenced
throughout the block diagram and functional analysis text to correlate specific locations on the schematics to the text.
When a specific location is referenced by the text, a number-Ietter-num ber is used to designate schematic sheet num ber,
and zone location within the sheet. For example, schematic reference (3B5) is found on Sheet 3, at the intersection of
Zone Band 5.
BLOCK DIAGRAM ANALYSIS
Data is stored in a 512 x 32 bit array subdivided into two pages, i.e., A and B. Each page stores 256 fullwords of data. Each
page is further delineated as a high half which stores Data Bits CSD001: 151, and a low half which stores Data Bits
CSDI61 :311. Data to be written into the Writable Control Store is derived from the backpanel A Bus, buffered, and
fanned oU1t to Pages A and B. See Figure 1.
The address to be read (or written) is derived from the Control Store Address lines (CSA) 04: 15 originating on the 8/32
CPB board. The four most significant address lines (CSA 04:07) are strapped to enable a selectable address range for the
WCS. The eight least significant address lines are buffered directly as AO:A 7, and select one out of 256 addresses within
each page.
FUNCTIONAL SCHEMATIC ANALYSIS
Storage
Dt~vice
The basic storage element used in the WCS is the 19-077 static bi-polar Random Access Memory (RAM) employing tri-state
output, o:rganized 256 words by one bit. It is intended for high speed memory applications where low input loading on
chip address decoding, and high capacitive drive capability are required. See Table 1.
The three state output has the characteristic TTL totem pole output with active elements driving both the ONE and ZERO
output voltage levels, plus the capability to disable both driving elements to a high impedence state when the device is not
selected. 'DIe data output can then be tied to a common output bus which can be driven by only one active output or a
passive pull-up.
The memory device (19-077) is addressed with the AO-A 7 inputs which select one of 256 words. The chip is enabled by
making all Memory Enables, Pins 3, 4, and Slow. If any of the Memory Enables are high, the chip is in the high impedence
state. If the Write Enable Pin 12 is high and the chip is enabled, the stored data (complement of data applied at input
during write cycle) is read on the output pin. If the Write Enable Pin 12 is low and the chip is enabled, the data on the
input pin is wtitten into the addressed word.
35-555FOIA21 ROI 1/78
I
....
,
TIMING
AND
CONTROL LOGIC
ADDRESS
BUFFERS
CSA080:150
PCLKO
<
CSWRTO
....
""
I
..,
CSA040:070
1
ADDRESS
STRAPS
-
u
U
0
0
I"-
«
U
0
«
I"-
aJ
0
til
u
~
0
0
f0:
~
0
0
«
0
0
0
til
U
f-
z
0:
~
«
0
«
I"«
«
0
<.0
LU
>
f-
l"-
~
0
0
0:
«
LU
aJ
«
0
til
u
~
aJ
0
«
0
CD
0
Z
LU
>
LU ....
PAGE A
(EVEN)
HIGH HALF
~
16
PAGE B
(ODD)
HIGH HALF
L-...,
PAGE A
(EVEN)
LOW HALF
i.....+
I
PAGE B
(ODD)
LOW HALF
16
I
AB
BUFFER
HIGH
AB
BUFFER
LOW
..-
L.O
u:;
00
..-
0
0
0
«
til
U
M
M
co
co
0
«
u
til
I'
1\
"
..-
1\
Figure 1. 8/32 WCS Block Diagram
TABLE 1.
CHIP
SELECT
2
19~077
MEMORY DEVICE TRUTH TABLE
WRITE
ENABLE
I
OPERATION
OUTPUT
ALL
LOW
LOW
WRITE
UNDEFINED
ALL
LOW
HIGH
READ
COMPLIMENT
OF WRITTEN DATA
ONEOR
MORE HIGH
~ON'T
HOLD
HIGH IMPEOENCE
STATE
CARE
35-555FOIA21
ROO 9/75
Writing ill1to WCS
Refer to Figure 2, Timing Diagram. During Control Store Write operation, the Processor traverses Processor Control States
0, 2, and 3. The Write instruction is decoded in Control State O. The CPB deposits the WCS address on CSA 04: 15 lines at
least 10 nanoseconds before Control State 2 is entered. The CSA 070 determines which page is written into by activating
either O])DO or EVENO chip enable lines.
.---
*1.-----I
- -
I
....---_...
- - - - -___....
1.... -
- - - CSo - - - -....
CSo - --
CSWRTO
WRCSOA-()
j.-- K
I
--t
B
r-----------------~--aoI......-
- --
I+-
~~~~~~I~~I--------------------------~----------------------------~-A (000: 31 0) \~i::::::!:: .. ·.·!~
~,--~I~--------------------------~--~--------------------~I--~--------I E \4-
CSA(040: 150) ••
--tJ1 D t-:Ti}·i·.:ii:~r~:----------------~
. . :--:---:--:--:---.,..-.. . . ~~....;.._
-I
J)q""t.....................;.; ; .; ;.................................___~................~......==__........=~. . . . . . . . . . . . :J.:.~,..---
CSD(001:_.3_1_1) _ _ _ _ _ _ _ _
MAX in ns
A
24
MIN in ns
MIN in ns
8
G
I
10
H
90
0
8
K
70
58
10
L
/
40
M
/
50
B
I
C
58
D
/
E
/
10
/
95
F
MAX in ns
115
I
Figure 2. Control Store Write Operations
lne CSA 04:06 are factory strapped to inhibit the chip enable lines for any address outside the X'800'-'9FF' range. The
('SA 08:15 are buffered directly as AO:A7, and select one out of 256 addresses within each page. The CPB holds address
lines static at least 10 nanoseconds after Control State 2 to 3 transition. The data to be written into WCS is deposited on
the backpanel A Bus at least 10 nanoseconds before CSO .... CS2 transition.
This data is buffered on the WCS board and applied simultaneously to both pages of the WCS. Data is held static
throughout the CS2 state.
Writing of one 32-bit word is accomplished in Control State 2. Write operation is distinguished from a Read operation by
CSWRT going active. This signal is used to derive Write enable pulses WRCSOA-D. The width of WRCSO is guaranteed to be
50 nanoseconds minimum.
The 40 nanosecond delayed Processor Clock (PCLKO) is used to build the leading edge of WRCSO. This ensures that the
switchill1g noise on the leading edge of CSWRT signal is screened off. The trailing edge of WRCSO is generated by the
])PCLKOA signal (Processor Clock Delayed 20 nanoseconds).
Since PCLKO is high (inactive) for 85 nanoseconds minimum, the width of WRCSO is guaranteed to be 50 nanoseconds
minimum. The DPCLKOA input also ensures that a sufficient data and address hold time is allowed after the trailing edge
ofWRCSO.
35-:555F01A21 R01 1/78
3
Control Store Read
Refer to Figure 3.
- - - - CSOO
-----.+011.1------I
I
CS01 - - - - -
I
rl_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - .
...____~I...·~---D - - - -....~I--- F -=:I
PCLKO
--I A
-C-S-A~c~
. . • ~~~~~-• ~
•..•. ·~\~,)k
r.--
:
!
-I
E
I--
~r\~~~~--~
1---I B 14-------------~~>~. . ~~~~*~--------------~~~\~~-I
CSD
-I.
CS02
B
14-
--t
C
NOTE: CSWRTO WILL STAY HIGH THRUOUT THE ENTIRE CS READ OPERATION
I
A
~
10 ns MAX
D = 95 ns MIN
B _c 10 ns MIN
E = 10 ns MIN
C = 10 ns MIN
F ~ 40 ns MIN
Figure 3. CPU/WCS Interface Timing Control Store Read Operations
The Read instruction is decoded in Control State O. The CPB gates the address on the busses prior to entering Control
State 2 as described in the section on writing into WCS. The CSWRTO is held high throughout the Read instruction. During
CS2, WCS deposits one 32-blt word on Control State Data bus (CSD) 001 :311. The data on the bus must be settled at least
10 nanoseconds before the negative going edge of PCLKO (see parameter C in Figure 3) which latches the data read from
the WCS in the Processor Register Stacks.
WCS Strapping
Address strapping.
The 8/32 WCS responds to the Control Store addresses within the
XI800~9FF'
range.
NOTE
Strapping Address X'800 - 9FF' 21-25. 22-28,
23-30, 24-31,46-25,45-28,44-30,43-32.
ROUTINE MAINTENANCE
Routine maintenance consists of running the WCS Test Program 06-192.
4
35-555FOJA21 ROJ 1/78
35-663 ROIA20
June 1978
METRIC
MODEL 8/32
21{ WRITABLE CONTROL STORE
INSTALLATION SPECIFICATION
INTRODUCTION
The Writable Control Store (WCS) option extends the flexibility of the user level processor to that of the micro-machine.
The WCS has the capability of storing and retrieving data within the control store, plus the capability of dynamically
altering control store instructions. In effect, the micro-programmer has the full capability of the user level machine at
micro-processor speeds.
The WCS offers 8KB of control store, sufficient to contain 2048 instructions or some combination of instructions and
aara:lT1s contamed~'";i the 8/32 CPC Processor board and requires typically 10 Amperes of 5VDC for power.
This specification provides the necessary information for the installation of the 8/32 Writable Control Store (WCS) option.
PHYSICAL CHARACTERISTICS (35-663 Board also includes 8/32 CPC)
Dimensions - Board 381 mm x 381 mm (IS" x IS")
Weight 2.72 kilograms (6 pounds) approximately
Power - 5VDC at 15 Amperes maximum
Hardware
one additional power supply regardless of expansion.
one 35-663FOO board
one l7-360FOl front edge ribbon cable
one illegal instruction ROM on 8/32 CPB ROM.
UNPACKING
When the WCS option is shipped with a system, it is installed at the factory. All cables and printed circuit boards should be
inspected to ensure proper seating.
INSTALLATION
Chassis
Slot 6 of the lower chassis on a 356 mm (14") Basic Processor Twin Chassis is used for the 8/32 WCS option. The WCS is
mounted on the 35-633FOO board (the 8/32 Processor CPC board).
35-663A20 ROI 6/78
I
Power
A.n additional power supply, regardless of configuration, has to be used to provide an extrLl 5VDe (PS) source for wes. See
FIgure 1.
MODEL
8/32
TWIN
CHASSIS
Figure 1. 8/32 Processor with WCS and/or DFU Power Wiring
Cabling
I
The 17-360F01 cable connects Connector 4 on the ePB and epe Processor boards.
Testing
Upon completion of the installation, and before power is applied, all voltages should be checked for shorts between each
other and ground. Proper operation of the WCS is tested by the execution of the WCS Test Program, 06-192.
Other
I Illegal instruction ROM, 19-195F13, on the 8/32 CPB board (35-537FOl) at location OOC must be replaced by 19-195F14.
2
35-663A20 ROt 6/78
35-663A21
October 1977
METRIC
MODEL S/32
2K WRITABLE CONTROL STORE
MAINTENANCE SPECIFICATION
INTRODUCTION
The Wriltable Control Store (WCS) is an option which extends the. flexibility of the user level processor to that of the
micro-machine. The WCS has the capability of storing and retrieving data within the control store, plus the capability of
dynamically altering control store instructions. In effect, the micro-programmer has the full capability of the user level
machine at micro-processor speeds.
The WCS offers 8KB of control store, sufficient to contain 2048 instructions or some combination of instructions and
data. It lis contained on the unused half of the 8/32 CPC Processor board and requires typically 10 Amperes of 5VDC for
power.
This specification describes the functional operation of the Model 8/32 Writable Control Store and provides information
necessary for its maintenance. This specification references CPC Functional Schematic 35-663D08. Perkin-Elmer schematic title, drawing number, and sheet number are located in the lower right corner of each sheet. Each sheet is zoned
alphabetically across the top and bottom margins and numerically down the side margins. These schematics are referenced
throughout the block diagram and functional analysis text to correlate specific locations on the schematics to the text.
When a specific location is referenced by the text, a number-letter-number is used to designate schematic sheet number,
and zone location within the sheet. For example, schematic reference (3B5) is found on Sheet 3, at the intersection of
Zone Band 5.
BLOCK DIAGRAM ANALYSIS
Data is stored in a 2048 x 32 bit array subdivided into two pages, i.e., A and B. Each page stores 1024 fullwords of data.
Each page is further delineated as a high half which stores Data Bits CSDOO 1: 151, and a low half which stores Data Bits
CSDI61:311. Data to be written into the Writable Control Store is derived from the backpanel A Bus, buffered, and
fanned out to Pages A and B. See Figure 1.
The address to be read (or written) is derived from the Control Store Address (CSA) lines 04: 15 originating on the 8/32
CPB board.
FUNCTI[ONAL SCHEMATIC AN AL YSIS
Storage Device
The basic storage element used in the WCS is the 19-218 static bi-polar Random Access Memory (RAM) employing tri-state
output, organized 1024 words by one bit. It is intended for high speed memory applications where low input loading on
chip address decoding, and high capacitive drive capability are required. See Table 1.
The three state output has the characteristic TTL totem pole output with active elements driving both the ONE and ZERO
output voltage levels, plus the capability to disable both driving elements to a high impedence state when the device is not
selected. The data output can them be tied to a common output bus which can be driven by only one active output or a
passive pull-up.
TIle memory device (19-218) is addressed with the AO-A9 inputs which select one of 1024 words. The chip is enabled by
making the Memory Enable Pin 1 low. If the Memory Enable is high, the chip is in the high impedence state. If the Write
Enable, Pin 14, is high and the chip is enabled, the stored data is read on the output pin. If the Write Enable, Pin 14, is low
and the chip is enabled, the date on the input pin is written into the addressed word.
3S-663A21 ROO 10/77
LO
0
~
ADDRESS
GATES
CSWRTO
TIMING
AND
CONTROL
LOGIC
i5
< >< >< ><
~
~
~
a a a a
:::iE
ADDRESS
• •
I
•
19 BIT HALFWORD ADDRESS
'---v--'
DMA COMMAND CODE
SEE TABLE 3.
WRITE DATA
16 BIT WRITE DATA
PARITY BIT
ANSWER DATA
16 BIT ANSWER DATA
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
X
X
X
X
ANSWER FROM MEMORY 0
ANSWER FROM MEMORY 1
ANSWER FROM MEMORY 2
ANSWER FROM MEMORY 3
ANSWER CONTAINS PARITY ERROR
MEMORY MALFUNCTION (DATA UNDEFINED)
Figure 5. EDMA Data Bus Formats
7.1 EDMA Bus Control Logic
The EDMA Bus control logic is located on the MBC and is used to resolve contention of devices requesting service on the
EDMA lBus, queue the selected device (QUEO), establish an order of priority of requesting devices (RPCO/TPCO), and issue
a start command (SOTO), indicating that one device has the use of the bus and may begin transmission.
35-535A21 R02 5/78
7
7.2 Types of EDMA Operations
Seven types of data transfer operations can occur over the EDMA Bus. Table 3 lists the operations and their identifying
command codes which are transmitted on the R, W, and F bits of the EDMA Data Bus address format (DMAI50, 160, and
170 respectively) in low active polarity (see Figure 5).
Read halfword and Write halfword are 16-bit data transfers. Read and Set halfword is a remote memory Read operation
which, in addition to reading the data, causes the most significant bit of the data halfwor j in the remote memory to be set
after the read is accomplished. Read fullword and Write fullword are 32-bit data transfers in which the data is sent over the
EDMA Data Bus in separate 16-bit halfwords.
Burst read and Burst write are block transfer operations in which a single EDMA
memory accesses to sequential fullword addresses.
reque~;t
initiates a block of continuous
TABLE1 EDMACOMMANDCODE
8.
R
W
F
a
a
a
1
a
a
1
1
1
FUNCTION
READ HALFWORD
WRITE HALFWORD
READ AND SET HALFWOR D
1
a
1
READ FULLWORD
a
1
1
WRITE FULLWORD
1
1
1
READ BURST
a
a
1
WRITE BURST
MBC/LMI INTERFACE
The MBC/LMI interface consists of the following lines:
MNEMONIC
NAME
LMBOOO:310
LMRSO
LMDSO
LMRDYO
LMBSYAO}
LMBSYBO
LMBSYCO
Local
Local
Local
Local
Memory
Memory
Memory
Memory
DIRECTION
----Bus
Request Service
Data Strobe
Ready
Local Memory Busy A, B, and C
MBC~LMI
MBC-LMI
MBC-LMI
MBC--LMI
I
LMI~LMI
Data Bus LMBOOO :310
These bidirectional lines are time-multiplexed to transfer address and control data to the LMI boards at the start of
a memory cycle and later to transfer data between the MBC and LMI boards, as !:hown in Figure 6. Halfword data
is al~..Y~ trans!~~g..Q!1bM1H~P:31_Q..
F'c-,/{)/V C 6 b l{ 5-
I I I I I I I I I I I I I I I I I I I 11,1
II \;1 J,.!J2!;I.~'1
AL F I/YO f<"
~11
ADDRESS TIME
19 BIT ADDRESS
~
5 BIT CONTROL CODE
SEE TABLE 4.
FULLWORD OPERATION
32 BIT DATA FIELD
DATA TIME
HALFWORD OPERATION
NOT USED
II
16 BIT DATA FIELD
o
M
a:l
:2:
-'
Figure 6. Local Memory Bus Formats
8
35-535A21 R02 5/78
Control Lines
LMRSO
Local Memory Request is made low-active when the MBC is requesting a memory cycle.
LMDSO
The leading edge of Local Memory Data Strobe clocks write data into the LMI Memory Data
Register during Write operations.
LMRDYO
The Local Memory Ready pulse is maintained low active when an LMI begins the requested
memory cycle and when data for a Read operation is valid on the LMB.
LMBSYBO}
LMBSYCO
Local Memory Busy A, B, and C communicate between LMI boards to synchronize their access
cycles for an instruction Read operation.
8.1 Types of Memory Operations
Five types of data transfer operations can occur over the Local Memory Bus. Table 4 lists the operations and their
identifying control codes. The control code is transmitted over LMB27 :31 during address time (see Figure 6) with
high-active polarity.
TABLE~
LOCAL MEMORY CONTROL CODE
1lt.,,\IDfI/ '()\)e~
LMB27
LMB28
LMB29
LMB30
LMB31
COOl
CO 11
C02l
EXl
SXl
0
X
1
X
0
WRITE FULLWORD
1
0
1
X
0
READ FULLWORD (FROM CPA or DMA)
1
1
1
1
0
READ FULLWORD (FROM DMA in BURST)
0
1
0
X
0
WRITE HALFWORD
0
READ HALFWORD
FUNCTION
---
---
1
X
0
X
1
1
1
0
0
INSTRUCTION READ (FROM CPA)
X
X
X
X
1
INSTRUCTION READ (FROM LOOK-AHEAD CACHE)
Write and Read fullword are 32-bit data transfer operations. Note that two codes exist for read fullword-the LMI
responds id'entically to either code. Write and Read halfword are 16-bit data transfers over LMB 16 :31. An Instruction Read
request causes both LMIs to respond with a full word Read operation. This results in a double fullword Read operation,
aligned on double full word boundaries. The first 32-bits transmitted to the MBC contain the actual instruction halfword
requested. 125 nanoseconds later, the second 32-bits of the aligned double full word is transmitted by the other LMI. Both
full words alre stored in the look-ahead cache.
Note that 1there are two Instruction Read codes, depending on whether the CPU or the look-ahead cache initiated the
request. The LMI boards respond identically to either code.
9.
LMI/LMM INTERFACE
The LMI interface with the Local Memory Modules (LMMs) is defined by the following lines:
MNEMONIC
NAME
DIRECTION
MSOOO:160
Memory Sense Bus
LMI~LMM
MDOOO:160
Memory Data Bus
LMI~LMM
MAX060, MAX070,
MAOO:14(O)
Memory Address
LMI-LMM
ERO
Early Read
LMI-LMM
EWRTO
Even Halfword Write
LMI-LMM
OWRTO
Odd Halfword Write
LMI-LMM
35-535A21 R02 5/78
I
9
Data Lines MSOOO:160 and MDOOO:16*
These two bidirectional data busses carry 16 bits + parity of read data and write data between an LMI and its two
separate banks of memory. The MS Bus and associated memory bank handle the most significant (even) halfword
in an aligned full word, while the MD Bus and memory bank handle the least significant (odd) halfword (see Section
3). The two busses are then linked together within the LMI for a full word of data (on full word operations).
Address Lines MAX060, MAX070, MAOO:14, (0)
These lines carry the 17-bit address from the LMI to both banks of memory. Contrary to their mnemonic
designation, the LMI outputs high-active address information.
Control Lines
ERO
Early Read is a Memory Module control signal which initiates the readout phase of a core
memory cycle.
INHO
Inhibit is a Memory Module control signal which initiates the restore/write phase of a core
memory cycle.
EWRTO
Even Write is a Memory Module control signal which is maintained low-active when it is desired
to write into the even-halfword bank of memory.
OWRTO
Odd Write is a Memory Module control signal which is maintained low active when it is desired to
write into the odd-halfword bank of memory.
The Memory Module cycle is basically the same for any request type initiated by the MBC, the only difference is that one
or both of EWRTO/OWRTO are maintained low active if a Write operation is performed. It is important to remember that
an LMI cycles two Memory Modules (even and odd halfword) for every access cycle, whether the request is for a halfword
or full word operation.
10.
MBC BLOCK DIAGRAM DESCRIPTION (See Figure 7.)
1.
The 19 CAXXO lines from the CPA are the memory address lines. They are stored in 19 tracking latches,
the CA ADDR Register.
2.
The STK ADDR Register contains the 17-bit address of the four halfwords in the stack with the lowest
double-fullword address. The STK A valid flip-flop indicates when this data is valid.
3.
STK B ~ is a 16-bit adder that effectively adds I to the stack address register to provide the address of the
four halfwords of data in the stack with a higher double-fullword address. The STK B valid flip-flop
indicates when this data is valid.
4.
The comparators, CEQL and CEQU compare the 17 most significant bits of the CA ADDR Register to the
STK A and STK B data to determine if the address requested is contained in the stack.
5.
The Control Memory Control (CMC) analysis block decodes the Instruction Read code, data read and write
codes, and the null state code of the CMC bits.
6.
The Memory Contention (MC) circuit resolves contention for the memory between the Processor, the
EDMA Bus, and the look-ahead stack. In the case of more than one request to the memory, the Memory
Contention (MC) circuit also sets priority. The EDMA Bus has highest priority, the Processor second, and
the look-ahead stack lowest. This circuit enables the Local Memory Request Service signal (LMRS), holds
the Local Memory Bus Busy state, and is reset by the Cycle Complete (CYCOM) signal.
7.
The enabled LMRS logic generates LMRS with the appropriate delays and conditions.
8.
The Cycle Complete (CYCOM) logic generation indicates that the present access to memory using the Local
Memory Bus is completed.
9.
Counter F (CTR F) keeps track of the number of Local Memory Readys (LMRDY) required from the LMI
to steer the data and input to the CYCOM logic.
10.
The Local Memory Bus (LMB) is a 32-bit bidirectional bus that sends and receives the LMI data to and
from the LMIs.
* These bidirectional data busses should not be confused with the unidirectional MS and MD lines on the Memory
Modules. The MS and MD lines of the Memory Module are wired together and the combination is then connected to either
the LMI MS Bus or LMI MD Bus, as appropriate.
10
35-535A21 ROl 11/75
11.
When the LMRS signal is sent to the LMIs, the LMB is used for address and control information. The LMB
is driven by tri-state multiplexors at each end and received by STTL gates. The address information is low
active on the bus while the control bits are high active. The first Local Memory Ready signal from the LMIs
indicate that the address has been accepted and tht~ memory cycle has started. The LMB is then used for the
transfer of data. The data is high active on the LMB.
The LMB tri-state multiplexor puts the address on the LMB either from the Processor (CAF), the EDMA
(DAD), or from the stack request (STB). For Write operations to memory this multiplexor is also enabled
and places either the Processor data (CD), or the EDMA data (DMF) on the LMB.
12:.
The Instruction Stack contains eight halfwords. It has separate Read and Write select lines. It is loaded four
ha1fwords at a time, each time the Processor makes an Instruction Read memory access or each time the
stack makes a look-ahead access. The four halfwords come in two 32 bit pa~ses on the LMB. The Write
select logic detelmines the stack address to be loaded and the CfR F logic creates the Load strobes. The
Read select lines come directly from the three least significant bits of the address from the Processor, CAF.
A tri-state multiplexor, CD B, places the data from the stack onto the CD lines to the Processor duringan
Instruction Read from an address in local memory.
13.
Tri-state multiplexor CD A places data onto the CD Bus to the Processor during a data read from Local
Memory or during a read from memory on the EDMA Bus.
14.
The Address analysis logic looks at the address requested by the Processor on the CA lines and compares it
to four sets of straps to determine if the address is contained in Local Memory, or in one of the three
memories that can be placed on the EDMA Bus, or it is beyond the range of memory fitted in the particular
machine. The outputs MO, Ml, M2, M3, and GTUU (Greater Than Unused) indicate in what region the
requested address lies. There are four straps in each set so the one megabyte of memory can be divided up
with a resolution of 64 K bytes.
15.
Tri-state buffer A places the CAF information on the DMT lines (to DMA transmitters) for Processor
requests to memory on the EDMA Bus. Tri-state multiplexor, DMT A, places the data onto the DMT lines
when the request is a write to external memory.
16.
The DMA transceivers translate the TTL DMT levels into the EDMA Bus levels.
17.
The LM data register stores the LM data for answers to EDMA requests from Local Memory.
18.
The tri-state mUltiplexor, DMT B, places the correct half of the LM register onto the DMT lines for these
reads.
19.
The DXR and DMR lines are signals from the EDMA Receivers.
20.
The DMA address register counter stores (and increments when necessary), the 19-bits of address information from the EDMA Bus during accesses to Local Memory.
21.
The DMA CTRL register stores the three control bits.
22.
The DMA data register is a 32-bit register that stores the data from the DMA Bus that is sent to Local
Memory on a write, or stores the read data sent back to the Processor from external memory.
23.
The DCOMP A and the DCOMP B circuits are comparators that signal when the EDMA Bus is Writing into
memory over an address that is valid in the instruction look-ahead stack.
24.
The CPA SEL logic requests the EDMA Bus for transfers to external memory and gets the CPA selected as
the transmitting device on the EDMA.
25.
CTR B generates the Load and End of Transmit (EaT) signals for the EDMA when CPA is communicating
with external memory. It also helps create the signals for data steering and enabling.
26.
CTR D receives Load signals from the EDMA Bus and creates the load register signals. It counts the loads
and initiates action when required.
27.
The Bus Control logic with signals from CTR A, handles the requests for the EDMA Bus and generates the
Queue (QUE), Transmit Priority Chain (TPC), and Start of Transmit (SOT) for the bus.
28.
The CRDY logic generates CRDY back to CPA at the end of the CPA access.
35-535A21 ROJ 11/75
11
(P
/'JellJ ) F)!Jr -,
-->-
19
CA
ADDR
REGISTER
CAXXO
LMB
CAF1
DAD1
LMB
TRI-5T
MUX
DMFO
CAFO
CDO
STB1
I
CMCXX04 CMC
ANALYSIS
CREQ
)>----
MEMORY
CONTENTION
CIRCUIT
EREQ
~==::-t--t---~LMRSO
CRDY
LOGIC
CRDYO
32
DMF1
TRI
STATE
MUX
DMTA
CDOTO CPA
TRI-ST
BUFFA
CAFO
16
DMT1
19
16
DMA TRANSCEIVERS
TO DMA BUS
DMX,DMA
DMT
22
DXR1,DMR1
LOADO
)>-----
r--L-O'-A-D...... LDRCVR r - - - " ,
ANS
EOT
GEN/
RCVR
ANSO
EOTO
ANS GEN
CTRB.
LOAD,EOT
GEN
BUS
DAD1
DEQLO
DEQUO
>-~~~~CONTROL
LOGIC
CTRA
Figure 7. MBC Block Diagram
12
35-535A21 ROt 11/75
11. MEMORY BUS CONTROLLER (MBC) FUNCTIONAL DESCRIPTION
11.1 CPA to Local Memory Write Halfword of Fullword
11.1.1 Address Transfer Cycle. Refer to timing diagram Figure 8. The address bits from CPA come through
tracking latches (Sheet 6) which are tracking because the CREQF (6F6) is still reset. The address is analyzed by the
comparators (Sheet 9) and found to lie in the range of the Local Memory (Memory 0). The CMC bits (11 H6) are also
checked and it is found that this access is not an Instruction Read OR).
The CREQ pulse is received from the CPA and stored in the CREQF (6F6). A delay line (14A7) is also started to give
delayed signals equivalent to CREQF. The setting of CREQF freezes the address in the tracking latch and signals the start
of the MlBC response.
CfENDO (13E8) is the input to the Memory Contention circuit and it is created from MOl, IRO, CRQDOOI (CRQDOOI is
CREQ delayed zero time), and no resetting signal. The CTENDO signal is immediately sent when CREQ is received, the
access is not an Instruction Read (lRO), and the address is in the range of Local Memory (MO 1).
The LMB multiplexors (Sheet 3) enable and select the CAFxxl and CAFBxxl signals with a low active signal on DATTMI
(13 M9) and a high -active signal of EFBO. DA TTM I is low active during address time except when the look-ahead stack is
requesting to be filled from memory (SMXO being low).
The address time ends when the Local Memory Bus Busy flip-flop is set. This occurs when the first Local Memory Ready is
received from the LMIs. The command code is also sent on the LMB at the same time as the address. Bit 27 on the LMB
(LMB270) is low at this time for write commands.
The AND-OR-Invert gate (13N7) creates Local Memory Request Service (LMRS). The CF1 and EFO inputs indicate that
the Processor (C) and not the EDMA (E) is in control of the memory. LMRS is turned off by LMBBY being set. The D35 is
a delayed enable signal from the contention delay line and is discussed in the Memory Contention circuit.
Note in the timing diagram that the gap between CREQ to LM and the LMRSO from C could be caused by another cycle
presently in progress or a request from the EDMA Bus which has a higher priority. The gap between LMRSO and LMRDYO
is caused by the LMI being addressed while still being busy from a previous access.
.:.:":.:.:.:.:.:•...•1.:.:.•...
·····················rrr=-·1
:.:.:.:.:.:.:.:.:;:;::.....::::
CA VALID
@~s.~m~ij_CM_CV_AL_ID_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r~m~~n~@~ilij~@~M~M~oo~m
CREOO
CRDYO
~~----~----~------~,~~----~s~s-----------------------L-------------------
_ _ _ _ _ _ _ _ _~......... SEE NOTE ~
CREOFQi
CR EO
I
T,-D-L-M-C-O-N-T-E-N-T-IO-N------.~ I
,
CTENDO
LMRSO FROM C
t?:J 5
.
~------\~Sp-----~~,~SP-------------------------~
LMRDYO
'-
S5
~-1-----------
StO:~E2
SS
S
=i
50 ns
~-------
.....
I.
11/)t;
S S"r-----S~
I~
LMBBYO
LMDSO
--------------------~5\~S------~sl~s-----~----~--------~~----~-------~--------~----~---------------
I+- 60ns =+40 d
TYP
ns
NOTE 1: This Delay depends on whether or not the Memory is busy with an EDMA or Stack Request.
NOTE 2: This Delay depends on whether or not the requested LM I is busy.
Figure 8. CPA -
35-535A21 R02 5/78
LM Write Timing Diagram
13
I
11.1.2 Data Transfer Cycle. During the LMRS signal, a delay line (11 L9) is being loaded with a low active signal
to generate the data strobes on the LMB and the Local Memory Data Strobe (LMDS).
The conditions necessary to load this delay line with a 0 are: 1. Not a stack request SMXO, 2. Local Memory Request
Service (LMRSl), and 3. Data write command code as indicated by a I on LMB271. When LMRS is disabled (caused by
the LMRDY signal from the LMI which sets the LMBBY flip-flop) the delay line (11 L9) starts to reload with a I level.
Meanwhile, DATTMI (13L9) has gone high active because of LMBBY, causing WDTMO (Write Data Time) to go low
(11 N7). Local Memory Data Strobe (LMDS) is also generated (11 N5) by this delay line and occurs during WDTM.
The LMB multiplexors (Sheet 3) are switched at data time because the address enabling signal, DATTM1, goes high and the
Write Data Time (WDTMO) signal goes low, enabling the CD lines onto the LMB and disabling the CAF lines. LMDS
indicates the end of the cycle and Cycle Complete (CYCOM). CYCOM is generated in parallel on the AND-OR-Invert gate
(1108) by DA 701 and DA400. Cycle Complete (CYCOM) resets the Memory Contention circuit. The ready signal to the
Processor (CRDY) is generated by the AND-OR-Invert gate (14N8). LMDS causes CRDY through the gate (14K8) which is
the OR of LMDS or Instruction Read ready from Local Memory (IRWRT - Instruction Read or Write). The CREQ
flip-flop is reset in parallel by the same signal into the RCREQF circuit (14R5). There is no distinction made in the MBC
between halfword and full word accesses to Local Memory.
11.2 CPA to Local Memorl' Read
HaJ~Qt9. or
Fullwo.r.d
11.2.1 Address Transfer Cycle. Refer to timing diagram Figure 9. This cycle is the same as for the data writes to
Local Memory except that Bit 27 on the LMB (LMB271) is high at this time indicating a read command.
I-- 20 ns MIN-I
-'I.
~1~~~:~1 CA V All D
rotlil:~:~::1~~ll::f~:t~~t~:~:~:~1~lt~~fttt~1~:~tt:l:~mmmmmmmmmmm~1~:~:l:~:~11:~:~lM~1~mtf;lt~1~1~1~1~1~11:l:l:~:~:~:~:~:l:l:i:i:i:i:i:l:l:l:l(~:l~t:itif;l;l
I':::::::::::::::::!:::!:::::!:!:!:!:::!:!:!:!:!:!:::!:!:!:::!:
·TTnrr·········(·. . . . . . · · · · · · ·
~ •••••••••••:
CMC VALID
••••••••••••••••••••••••••••••fIl ••••••••••••••••
1_50ns--_
':r-----.
s
LMRSO FROM C
14-----------------~'Lbns
----------------------------------~~~
LMRDYO
LMBBSYO
CTRFA
CTRFB
CTRFC
s
CYCOMO
NOTE 1:
This delay is a function of whether or not the memory is busy with an
EDMA or Stack request.
NOTE 2:
This delay is a function of whether or not Local Memory is busy.
Figure 9. CPA--LM Read Timing Diagram
14
35-535A21 R01 11/75
11 ..2.2 Data Transfer CYcle. The edge of the first LMRDY signal from the LMI indicates that the address has
been accepted and the data cycle follows. At this time the LMB multiplexors in the MBC are turned off waiting for the
LMI to send back the data. This is a.ccomplished by DATTMI (l3M9),going to the L state when LMBBY (13G9) is set.
Counter F, Stage A (CTF A) (11 E4) is set on the trailing edge of LMRDY. The LMI sends another LMRDY when it has the
data settled on the lines so Stage A of Counter F is used to differentiate between the first and the second LMRDY.
When the LMI sends data, it is placed on the CD lines through tri-state multiplexors (Sheet 4), CDA. At this time the Read
Data (RIDDATO) signal is low (1IH5). This is generated by the AND of CMCOO 1 (11 F5) and not an Instruction Read from
Local Memory (STCDO) (11 C5). (STCDO - Stack to CD enable signal). RDDATO and STCDO enables the multiplexors,
and MOO (Memory Zero or Local Memory) or MBOO (Buffered Memory Zero) select the LMB lines.
Cycle Complete (CYCOMO) is generated by the second LMRDY when it is ANDed with CTF A and not an Instruction
Read and not a Stack Access (SMXO) to memory (AND-OR-Invert gate) (11 DS). CRDY is generated in parallel by CTFA1
(14NS), LMRDY (delayed by 5 nanoseconds extra), and the output of a flip-flop which indicates that the access was not
an Instruction Read. The reset of the CREQF flip-flop is generated by CRDY (14R6).
11.3 CPA Instruction Read from Address in Local Memory
11.3.1 Instruction Valid in the Stack. The Control Address flip-flops (CAF) tracking latches are constantly
being compared against the STA and STB signals. STA is the output of the register that stores the present base address of
the data in the stack (Sheet 7). STB is the output of the adder (Sheet 7) that adds 1 to STA, giving the address of the data
in the upper half of the stack. Note that there is no STB2S because this is the complement of STA28. This is the reason
there are 17-bits of STA but only 16-bits of the adder are needed to add 1 to it.
The comparisons are done on Sheet S. Bit 17 is handled in both cases by Exclusive OR gates (8H9). Even if the address
compares in one of these two comparator circuits, other signals are needed to obtain an equal output. These signals are
STKA, which indicates that the lower half of the stack is valid, STKB, which indicates that the upper half of the stack is
valid; and SD200, which is a signal that permits the data in the stack to be loaded and settled from a stack access.
If either of these comparisons show up as equal by the time the CREQ signal reaches the 20 nanosecond tap on the CREQ
delay line (14A7), then it is remembered in a cross coupled EQI flip-flop (14D7). EQl, MOl, IRI, and CO (Instruction
Read, and Processor not accessing memory) combine in an AND gate to become EQIRCO (14G6). This combines with
CRQD30 (CREQ delayed 30 nanoseconds) to form the CRDY back to the Processor (l4MS). The equivalent of the Stack
Ready (STKRDY) is generated two other places, once as the true signal (STKRDYl) (14GS) and once as the not signal at
(STKRDYO) (14G7). These are used to load the STA register with the present base address of data in the stack (1417) and
to reset STKB (14L6) (indicator of the validity of the upper half of the stack) if the access is to the upper half of the stack,
and generate a request to memory at the same time to refill the stack with a Set Stack Request (SSREQA) (14M6).
The data is delivered to the CD lines during this process from the stack (Sheet 5) through CD Multiplexor B, (Sheet 4).
These multiplexors are enabled by a STCDO signal (11 C5). STCnO is low whenever the Processor is doing an Instruction
Read OR) from Local Memory (MO I).
Ibe correct word in the stack is addressed by the three least significant bits of the address.
11.3.2 Address Requested not in Stack or Stack not Valid. Refer to timing diagram Figure 10. If the comparators do not indicate an equal in either half of the stack and the address is in Local Memory (MO) then a request to Local
Memory is made. This is accomplished with CTENDO (13DS) created from not CEQL, not CEQU, MO, and not any other
ready or complete presently being generate'd and the stack not being filled (SD500-Stack Delayed 50 nanoseconds).
Ibe request and address transfer cycle to Local Memory is the same as for data reads or writes. The da,ta cycle requires
transferring two 32-bit words as follows. The second LMRDY from the LMIs indicates that the data fullword containing
the requested halfword is on the LMB. This is enabled into the stack with the signal LDSTKO (11 Cl). The delay line
(11B2) creates the proper timing of this signal from the second LMRDY. CRDY (14R8) is generated at this time by the
AND of CTFBI and CTFCO. Counter F, Stage B is set during the second LMRDY and Counter F, Stage C is set at the
trailing edge of the second LMRDY. Reset CREQI: is generated in paral1el by IRWRTO (Instruction Read or Data Write)
(14R6). Cycle Complete (CYCOM) is generated by the third LMRDY from the LMls by the AND of Counter F Stage C
(CTFC)I and LMRDY at the AND-OR-Invert gate (11 CS).
When the Processor has to go to Local Memory for an instruction, the STA register (Sheet 7) is loaded with the new base
Address (LDSTAI) (1417). The two flip-flops that indicate the valid state of the stack, STKA (14J4) and STKB (14 L6), are
both reset by CI LMRSO (14 G5). There are three other signals that can reset these flip-flops through the clear input. These
signals are System Gear (SCLR), writing into an address that is valid in the stack with a Write command from the EDMA
Bus (DEQ), and writing into an address that is valid in the stack from the Processor (from CMCOOO, and Cl AND LMRS).
rThe STKA flip-flop is set again with the IRWRT signal (14H5) when ANDed with CI (the Processor in charge of the Local
Memory) and IRI (a decode of the CMC bits that indicate an Instruction Read) (11 H6). Cl LMRSO also sets the Stack
Request flip-flop (13B5) to Local Memory to fill the upper half of the stack with another memory access.
35-535A21 ROI 11/75
15
Approximate
time in nanoseconds
o
100
200
300
400
600
500
REQUEST TO FILL 2nd
HALF OF STACK.
LMRSO
LMRDYO
LDSTKO
CRDYO
CYCOMO
LDSTKAl
STKAl
STKBl
STACK
~EfPlW~Jp
NOTE 1:
If Stack was valid but requested
instruction is not in Stack, Cl· LM RSO
will invalidate stack.
Figure 10. Instruction Read when Stack is Invalid or the Requested
Instruction is not Currently in Stack
'Dle data is written through the stack on an Instruction Read by controlling the Write select lines to the stack. These signals
are STWBI (14Cl) and STWAI (14E2). The SI and SMXO signals to this logic are from the Memory Contention circuit
indicating when the stack is accessing memory. At this time however, since the Processor (C for CPA) is accessing memory,
the stack is not. This leaves SI low and SMXO high. This gates the state of STA280 through to STWBI and the state of
CAF290 clocked into the flip-flop on the first LMRS.
Stage B of Counter F first enables the true side of the flip flop and then the complement side through to STW AI.
Meanwhile STWB I is directly the inverse of ST A280 (14B2) and is actually the equivalent of Bit-28 of the control address
from CPA. Recall that STA is the register that contains the base address of the data in the stack and it was just loaded with
the present address being requested by CPA (LDSTAl) (1417) so it reflects the present state of CAF28 for this Instruction
Read.
For example, if CAF290 is high indicating a request to memory with an even full word address, then the first data back
from the memory is from the even fullword LMI. Stage B of Counter F (CTF B) is still low when this data is indicated valid
by the second LMRDY, and STWAI is low for the first data full word and high for the second data fullwordJrom memory.
11.4 Stack Control
-- Stack request to memory
-- Stack filled from memory
-- Stack invalid-valid states
There are two ways that the stack may start a memory access. Since an Instruction Read from CPA fills the bottom half of
an empty or invalid stack, a stack request is required to fill the upper half. The Cl LMRSO signal (14G5) is caused by a CPA
request. It is generated when the Processor is making an Instruction Read request to Local Memory. The other signal that
sets the Stack Request flip-flop (13C5) is SSREQAO (14N6). This occurs whenever the CPA initiates an Instruction Read
to an address in the upper half of the stack. STKB flip-flop is .also reset at this time to indicate that this half of the stack is
temporarily not valid. The leading edge of Stack Ready (STKRDYl) resets the STKB flip-flop if the address comparison
was in the upper half of the stack as indicated by C address Equal to Upper half of stack (CEQU). Note that the lower and
upper halves of the stack are defined by the address· stored in STA register and not by the physical address in the stack.
That is, at one instant of time the bottom half of the stack may be Addresses 0:3 and at another time the bottom half of
the stack may be Addresses 4:7. (The data is not moved from one location in the stack to another. Only the STA Address
register is reloaded.) The STKA flip-flop refers to validity of the data in the stack that is from the memory location
indicated by the STA register, and the STKB flip-flop refers to validity of the data in the stack that is from a memory
location indicated by the STB adders.
16
35-53SA21 ROI 11/75
The address sent to the memory during the request from the stack is from the STB adders. This is put on the LMB
multiplexors (Sheet 3) by a Stack Busy signal (SBSYO) 14C1). Note that LMB310 is high indicating a Stack request to
memory. SBSYO is low when the stack is accessing memory (S1) until the Local Memory Bus Busy flip-flop is set
(LMBBYO} (indicating that the memory has accepted the address and the data transfer cycle is about to begin.
During the data cycle the LMIs pass back two 32-bit words of data the same as the Instruction Read to memory from the
CPA. The Load Stack signal (LDSTKO) (11 C1) is generated the same as for the Instruction Reads from CPA since the
SXIR signal is the OR of Instruction Read from the CPA and Stack in control of the memory (11 D6). Cycle Complete
(CYCOM) (11 F8) is from the third Local Memory Ready (LMRDY) as indicated by the state of Counter F Stage C (CTF
C) the same as for Instruction Reads from CPA to memory.
The Write select lines to the stack to select the addresses that the data goes to are STWB and STWA (14AI) (the same as
described in CPA Instruction Reads to memory). The fact that this memory access is from the stack looking ahead to fill
the upper half, conditions these select lines. STWB 1 is the complement of STA281 since the stack fills the upper half from
the opposite double fullword address as the lower half. STWAI is always low for the first 32-bit data word in a stack access
because the even address fullword is always sent back first in a Stack request (recall in a CPA Instruction Read, the first
full word s~~nt back is the one that contains the halfword that was requested and could be the even or the odd fullword).
This is done by SMXO (the signal that enables the Stack address onto the LMB through the LMB multiplexors) presetting
the flip-flop (14B2).
The signal SD500 from the delay line (l3K6) is used to permit the data to settle in the stack before permitting CPA to use
it.
11.5 EDMA Bus Control Circuit (See Figure 11.)
Approximate time in nanoseconds
o
I
35
I
105
I
175
245
I
I
315
385
455
525
XREci~
CXREO
..
~ --------------------..
CTAA
CTAB
CTAC
~
CTAD
________________
~r__
TPCO
SOTO
COUNT
ON COUNTER A
-I
70n5
I
rI
2
3
4
5
6
7
COUNTER
MAYBE
. STOPPED
IN COUNT 4
Figure 11. EDMA Bus Control
35-535A21 ROI 11/75
17
The EDMA Bus control circuit generates the QUE, Transmit Priority Chain (TPC), and Start of Transmit (SOT) signals to
the bus. These signals are created from a 4-bit Johnson Counter which is labeled CT A (l OHI). The counter can be stopped
at either of two times by signals at the clock oscillator (lOCI). At Count zero, Stage A and Stage D of the counter (CTAA
and CTAD) are both high. At this time the counter is stopped unless there is a request from the EDMA Bus (XREQ) or a
request for the bus from the Processor (CXREQ). This condition is the output of the four input NAND gate (lOB1). When
one of these requests arrives, the counter clock starts and immediately sends out a QUEO (lON3). At Count two, the
Transmit Priority Chain (TPC) (which is actually the beginning of the priority chain) is sent out (lOR7). At Count 4, the
counter can again be stopped (CTAAI and CTADI both high) by the STHOLDI signal (lOK3). STHOLDI is generated by
the ORing of five signals. These signals are: 1. DMAACTO, which indicates that the DMA is presently transmitting data and
another Start of Transmit (SOT) should not be sent at this time, 2. The Local Memory Request Received signal (LMRQRl)
(which indicates that the device queued up is requesting Local Memory) is ANDed with EFO, which is the EDMA selected
state of the Memory Contention circuit. This means that if the queued device is requesting Local Memory, Start of
Transmit (SOT) is not sent until the EDMA has control of Local Memory in the Memory Contention circuit, 3. BHO which
is the Bus Hold signal indicating that a memory is still using the bus and will momentarily send back answers, 4. A delayed
Bus Hold signal to inhibit false indications of Bus Hold being removed, or 5. EDMA Request and Burst Read (ERQBRDO)
which indicates that when a Burst Read operation is occurring, another SOT should not be transmitted until the Burst
Read access is completed.
Count 5 (CTA Stage B high and CTA Stage A low) (l0L4) generates Start of Transmit (SOTO). SOTO sets the DMAACT
flip-flop indicating that the DMA is actively transmitting data at this time. End of Transmit or System Gear resets this
flip-flop as the ENDO signal (I OM9).
11.6 CPA Select on EDMA Bus (See Figure 12.)
CREGO
RE 1
GUEO
50
PRPCl
XXl
SOTRl
SEL1
o
70
105
175
315
I
Approximate time in nanoseconds
Figure 12. CPA Request to EDMA Bus
When CPA makes a request to the MBC for an address that is not in Local Memory, the address analysis logic indicates if
the address is in Memory 1, 2, 3, or not in the system. This is done by the comparators (Sheet 9). The strapping on the
comparators draws the division lines through the memory so that when an address (four most significant bits) is greater
than one set of straps, but less or equal to the next set of straps, then the address is in that blv~k of memory. When the
address is found to be within the range of Memory 1, 2, or 3, the MBC goes out to the EDMA Bus for the access. The
DREQ flip-flop (9L3) is set by a pulse when the address is not in the Local Memory addresses (MOO) and less than the
unequipped memory addresses (LTUUO). When the memory requested is no longer busy as determined by the AND-ORInvert gate (915) then the CXREQ signal is sent to request the EDMA Bus and the SQUEFI signal (9M5) sent to the select
logic (Sheet 10),
The first Select Logic flip flop (lOH6) is set on the leading edge of QUEO when the SQUEFI signal is present. This
information is transmitted to the second flip flop on the trailing edge of QUEO. The leading edge of RPCR 1 clocks the
XXI flip-flop (10K6) and the leading edge of Start of Transmit clocks this into the second Select Logic flip-flop (lON6)
(SELl).
When the SEL flip-flop (lON6) is set, the XXI flip-flop is reset, and the DREQ flip-flop (9L3) is also reset. This ends the
select sequence.
18
35-535A21 ROt 11/75
11.7 CPA Write to Remote Memory
When the Select (SEL) flip-flop is set, the delay line controlled clock at IOB3 is started. TOOA is the output of this clock
and it is counted in the 2-bit 10hnson Counter, Counter B (CTBA and CTBB-Counter B, Stages A and B) (10E6). The
LOADs and EOTs for these transfers are generated by Counter B (10F7).
The first operation is to transfer the address out to the EDMA Bus with a LOAD. Loads are generated whenever Counter B
is not at zero by ANDing the CTBOOO signal with the clock TOOA signal (1 OF7). The End of Transmit (EOT) is generated
with the first load if the operation is a read, with the second load if the operation is a half word write, and with the third
load for a full word write. The gate (10D7) looks at CMCOO 1 to determine if the operation is a read, if it is, it enables the
EOT signal. For halfword operations the counter is forced to skip Count 2 by the gates feeding the D input of CTBA
(IODS). This gives the EOT with the second LOAD.
When the Select flip flop is set, the Control Address (CAF) and CMC bits are sent out to the EDMA Bus by turning on the
tri-state buffers (Sheet 2), the transceiver at SK2 and the transceivers on Sheet 2. The latter transceivers are also left on if
the" operation is a write, to transmit the data.
Note that the CMC bits are transmitted with the address but are modified in the case of an Instruction Read to be just a
halfword read (2R8).
The signals that turn on these gates are DMCAO to enable the addresses (10C7). This is the decode of Count 1 from
Counter B. The signal that enables the transmitters is DMA Enable (DMENBO) (10E9) whenever Counter B is not in the
zero state. There is another input to enable the transmitters called CTEAO but this pertains to the EDMA Bus reading from
Local Memory.
After the address has been transmitted with the first LOAD then the data is enabled onto the DMA Transmit (DMT) lines
with the tri-state multiplexors (Sheet 2). These multiplexors are enabled by Counter B Stage B being set (Counts 2 or 3).
This signal is CTBBO. If the command is a fullword write, the most significant half is transmitted first and the least
significant half transmitted last. The select line to the multiplexors is from Counter B Stage A (CTBAO). Recall that for a
halfword operation, Count 2 of Counter B is skipped and therefore only the least significant half is transmitted.
The ready signal to the CPA is generated by the trailing edge of the End of Transmit (1114). Here the Enable End of
Transmit signal is ANDed with CMCOOO which indicates a write command and is used to set the DMRDYB flip-flop. The
setting signal (DMRDYA1) and the output of the flip-flop (DMRDYBl) (Sheet 11) are ANDed (1417) and after being
ORed with other signals becomes CRDY (14S8). They also reset the CREQ flip-flop by creating the RCREQF signal
(14S6).
11.8 CPA Read from Remote Memory
The request, select, and transfer of the address sequence is the same as for writes to remote memory. With the LOAD signal
that transmits the address however, is also an End of Transmit (EOT). This is generated (10D7) by ANDing the CMCOOO
signal with State A of Counter B (CTBAl). CMC001 is high whenever there is a read command.
When the answers are returned with the data on the EDMA Bus there is a 2-bit code to indicate from which memory it was
received. This code is decoded and ANDed with the address block decode from the address analysis block (Sheet 11). If
there is a match between the decoded address and the requested address, the answers are used to load the two halves of the
DMA Data Register (DMA flip-flops -DMF) (Sheet 1) with the Load Least Significant Half (LDLSH) and the Load Most
Significant Half (LDMSH) signals (11 N3). The flip-flop (11 N2) is reset on Start of Transmit and is toggled on each answer.
If the command is a full word read, the first answer loads the most signiticant half of the register and the second answer
loads the least significent half. In a halfword read, the answer counter is forced to load the least significant half first (since
there will not be a second load) by the s,ignal DMAFWO (DMA fullword not).
The Ready signal to the CPA is from the DMRDYAI and DMRDYBI signals, the same as for remote memory writes. The
source of these signals is the Load Least Significant Half signal (LDLSH) after checking to see that these answers were for
the CPA request with the NAND gate (11KS). The conditions on this gate are C Request Delayed 60 nanoseconds
(CRQD60l) and DREQO (DMA Request having been reset by Select).
The DMA Write Data Buffers, DMF Data Register, are gated onto the CD lines during this operation through the
multiplexors (Sheet 4). They are enabled by the RDDATO signal the same as a read from Local Memory but the
multiplexor selects the DMF inputs with the MOO and the MBOO (these are the outputs of the address analysis block and
they are high whenever the access is not to Local Memory).
11.9 EDMA Bus Write to Local Memory (See timing diagram Figure 13.)
Before the Start of Transmission (SOTO) is sent to the device that is queued on the EDMA Bus, it has sent back a Local
Memory Request signal if it wanted Local Memory. This LMRQO signal is used to initiate a request to the Memory
Contention circuit for EDMA control. SOTO is not sent unless control has been granted to the EDMA Bus as indicated by
the EFI signal in the Memory Contention circuit (13Hl). The memory request is not actually made yet. It is inhibited by
the EHOLDO signal. EHOLDO does not go high until the Write Buffer is full (WRTBUFl) and Direct Memory Memory
Control Bit 0 is high (DMMCOOO) (11 M6).
3S-53SA21 ROI 11/75
19
Approximate time in nanoseconds
0
7.0
lq5
l~O
I
210
2~0
I
I
3?O
I
4~0
~::~:E_oo_~_S~~;:J~~--~il~~$~M~$~@~m~M~m~m~M~M~ffi~~@:~:M~M~mm:~mlm~;mm~@~:1f:~q~:~~:;:~W~:~~~:;l~~/:;~:~t:~W~:w~tt~ml
SOTO
LJ
I
~L~MS~E~L~l______________~lrl-----------------------'IL
I
LOADO
I
I
LJ
LJ
_______________________
w
LJ
EOTO
CTDBl
LDADRO
LDMSHO
LDLSHO
I
I
LJ
w
L.J
WRTBUFl
LMRSO
LMRDYO
CYCOMG
NOTE: THIS DELAY DEPENDS ON WHETHER OR NOT MEMORY
IS BUSY WITH A CPA OR STACK REQUEST.
---u-
Figure 13. EDMA Bus Write to Local Memory
When LMRQRI is high with Start of Transmission, the Local Memory Selected flip-flop is set (LMSEL) (12D6). The Start
of Transmission (SOTO) initializes Counter D Stage A (CTD A), resets the Write Buffer Full flip-flop, and other flip-flops
used.
Counter D keeps track of the loads being received so that the first load from the EDMA Bus loads the DMA Address
Counter Register (Sheet I). This register is loaded with a low on Address Finished (ADRFNl) (12H8) and a clock
(CDMADl) (11 G9). The low on ADRFNI is from Stage A of Counter D (CTD A) not being set yet. The clock signal is
from the Load Address input (LDADRO) (11 G9). This is generated (12C7) by the first load from the EDMA Bus after
SOTO. At the trailing edge of this first load, CTD A is set and the Address cycle is finished. \....1 the second load, a Load
Most Significant Half (LDMSH) of the DMF Data Register (Sheet 1) is generated. This is the LDMSHO signal (12H8) that is
ORed (11M4) to actually load the register. Note that there is a load at the same time as the address load but it is of no
significance because it is written over by the second one. The second load also toggles the Stage B flip-flop of Counter D
(CTD B) (l2F8). This enables the third load to set the Write Buffer Full flip-flop (WRTBUF) (I2K8) and load the Least
Significant Half (LDLSH) of the DMF Data Register with the LDLSHO signal.
EHOLDO (11 M6) goes high now and the memory access is started. The EDMA Address register (DADxx) is put on the
LMB by enabling the multiplexors (Sheet 3) with the DATTMI signal as described in the CPA write to Local Memory, and
selecting the DADxx inputs with the EFBO signal from the Memory Contention circuit indicating that the EDMA is in
control of the Local Memory Bus.
The remainder of the operation is the same as for CPA writes to Local Memory except that the data multiplexors to the
LMB are selecting the DMF data inputs with the EFBO signal. The Local Memory Data Strobe is generated in the same
way.
20
35-535A21 ROI 11/75
The Local Memory Select flip-flQP is reset with the End of Transmit signal but the operation is extended to the end of the
cycle on the LocalMemory Bus by the cross coupled flip-flop (13B2). This flip flop is set by LMSELO, enabled to request
memory with the DMA control bit that indicated a write, DMMCOOO, and reset with Cycle Complete (CYCOM). This
flip-flop is another condition that delays Start of Transmit by holding the Bus Control counter with ERQWRTO (lOR3).
For halfword writes to Local Memory, Stage B of Counter D is held high by the DMMC021 signal being low. This is the
control bit from the EDMA Bus, after it is stored in the register (1 K8), that indicates a halfword operation when it is low.
This control bit register was loaded at the same time as the address with the leading edge of LDDMC signal (12D7).
11.10 EDMA Bus Read from Local Memory (See Figure 14.)
When the LMRQ signal is sent on the EDMA Bus, the bus control circuit does not send SOTO until the EDMA has control
of the Local Memory Bus in the same manner as for an EDMA write to Local Memory.
SOTO and LMRQ set the Local Memory Select flip-flop (12D5). The Address transfer cycle is the same as for the Write
operation. The SOTO signal initializes several circuits for the Read operation. nlese are the Read Buffer Full (RDBUFL)
flip-flop (12C2) and the Counter E Stages A and B (12H3 and 12K4).
The gate (II K5) removes EROLDO when the ADRFNI signal goes high. 1bis occurs after the address is transferred to the
DAD Registers. At this time the Read Buffer is also empty, reset by SOTO, and not in a Burst Read operation, and
DMMCOOI is high because it is a Read operation.
ApprOl
EDMA
BUS STARTS
HERE
CUT THE MULTIPLEXOR BUS
JUMPER RACKO/TACKO AS SHOWN, REMOVE
DASHED JUMPER.
THIS SECTION BECOMES THE PRIVATE SELECTOR
BUS ON THE CONNECTOR ONE (CONN1) SlOE ONLY.
ALL SLOTS ON THE CONNECTOR ZERO (CONN 0)
SIDE REMAIN AS STANDARD MULTIPLEXOR BUS
SLOTS.
@ IF REQUIREDhEXTEND THE SELECTOR CHANNEL
BUS TO OTHEM CHASSIS BY INSTALLING A CABLE
HERE.
-_-+_1_0_ _ Z2
11
14
4
12
15
Figure 2. 19-118 Transceiver
02-328A21 ROI 2/76
5
To communicate with the ESELCH, it must first be addressed. The ESELCH Address (X'OFO' preferred)
is placed on Data Lines D060:150 (2A5:2A8) and the Address control line is activated (ADRSO) (4K7). The
ESELCH Address is decoded by the eight input NAND gate (2H6) and the Address flip-flop is set (3M9).
The Address flip-flop set output (AD1) (3M8), when active, prevents the control signals on the MPX-Bus
from passing onto the private ESELCH Bus by holding the Control Line Gate inactive (CLGI and CLGA1)
(292). SGADO (4M7) controls the Private Address (PADRSO) (4N7) such that when the ESELCR is being
addressed, PADRSO does not become active. This allows the ESELCH to be addressed without resetting
the Address flip-flop on the active device on the private ESELCH Bus.
The loading of the Address Register (AR), Auxiliary Address Register (AAR), and the Final Address
Register (FAR) is accomplished by four or six consecutive Data AvaUables (DAs) from the Processor. The
Load/Unload Sequencer (6C3) controls the loading of these registers a~d the unloading of the Auxiliary Address Register. The Sequencer is set to its initial state by the termination of the last data transfer, a STOP
command, or" a System Clear (SCLRO) (3K9). The Address Registers on Sheet 6 (6Fl:6F8) and the Final
Address Registers (FX, FH, and FL) on Sheet 5 are connected as shown in Figure 3. If four consecutive
Data Availables to the ESELCH (DAs) are executed by the Processor, the first DAloads DA081:151 into the
Final Address Low Register (FL) and the second DA copies the contents of the FL Register into the Final
Address High Register(FH) and a new DA081:151 is loaded into the FL Register and so on. After the fourth
DA is executed, Bits 00:07 of the starting address are loaded in the Address High Register (AH) and Bits 08:
15 of the starting address are loaded in the Address Low Register (AL). Bits 00:07 of the final address
are loaded in the Final Address High (FH) Register and Bits 08:15 of the final address are loaded in the
.Final Address Low Register (FL). Counter A in the Load/Unload Sequencer is initially set at State 3
(0011). After four DAs are executed, Counter A is in State 7 (0111). At this time the p output of Counter
A is still low. When Command GO is executed, NAND Gate C generates a Page Zero (PGOO) signal to
clear the Address Extended Register (AX) and the Final Address Extended Register (FX). The Command
GO (3N6) generates a Set Auxiliary Address Register (SETAARO) (3N6) to copy the starting address into the
Auxiliary Address Register at 5B3:5N3. If six DAs to the ESELCH are executed by the Processor, the
first four DAs act exactly the same way as before except that the fourth DA also generates a Load Final
Address Extended (LFRXO) signal to load J:?A121:151 into Final Address Extended Register (FX). After
the fifth DA is executed, the Extended, High, and Low Starting Address bits and the Extended, and High
Final Address Bits are loaded in the AX, AH, AL, FH and FL Registers respectively. At this time,
.counterA in the Load/Unload Sequencer is at State 8 (1000) and the D output is high. This inhibits any
furth~r data from loading into the AX, AH t and AL Registers. After the sixth DA is executed, the Extended
Final Address bits in FH are thrown away and the High Final Address bits in the FL Register are copied
into the FH Register and the Low Final Address bits are loaded into the FL Register. At this time all the
address bits are loaded into the correct registers. The Command GO (3N6) generates a Set Auxiliary Address Register (SETAARO) (3N6) to copy the starting address into the Auxiliary Address Register at 5B3:5N3.
If the Extended Address Read Command bit is reset, two Data Requests (DRs) are required to read back the
final address from the Auxiliary Address Registers. Counter A145 (6C2) is initially set at State 3 (0011)
and the C input of the A157 Decoder is low (6C4) because the A54 (6C7) flip-flop is reset by resetting the
Extended Address Read Command-bit. The first DR decodes State 3 of Counter A145 and activates the Unload Auxiliary Address Register High (UAARHO) (Sheet 6). Outputs from the Auxiliary Address Register
(AAR04l:l11) (Sheet 3) pass through the Multiplexors at 3C4:3N4 and send the high bytes of the' final address to the Processor. The second DR increments the counter to State 4 (100). Since input C of Decoder
A157 (6C4) is set low, the zero state is decoded. It activates the UAARLO and sends the low bytes of the
final address to the Processor.
6
02-328A21 R01 2/76
--u-
CMDG01
0
t-:l
I
lCLK
PGOO
t-:l
'"
00
-=
:>
t-:l
D
C
B
A
D
I-'
P5
!:Jj
0
I-'
t-:l
"-::J
CLUSO
0:.
A
DAGO
1.S
DRGO
CNT
UP
LOAD
UNLOAD
SEQUENCER
P5
UAARLO
0
D 19032
C
B
B
PAGEOO
A
DAGOL.t
2
UAARHO
3
4
5
6
7
8
P5
UAARXO
LARH
LARL
LFRH
LARH
LARL
LFRL
DAG1
9
LARX
LFRX
LFRH
DAGO+DRGO
DAG1
A
I
B
C- - - - - '
D--------------------------------------~
Figure 3. Address Scheme Extended SELCH
LFRL
If the Extended Address Read Command bit is set, three Data Requests (DRs) are required to read back the
final address from the Auxiliary Address Register. In this case, flip-flop A54 (6C7) is set and input C of
Decoder Al57 (6C4) is high. The remainder of the operation is the same as described previously.
If a Memory Write operation is desired, an Output command with Bit 10 set must be issued to set the Write
flip-flop (4E6). Since the Write flip-flop is reset by the Data Available/ Requset Gate (DARGl) (4A6) when"ever a DA or DR is sent to the ESELCR (set up procedure), no command is' necessary to initiate a Memory
Read operation.
Data transfer commences with a GO command from the Processor, which is an Output command with Bit
11 set. The GO command sets both the BUSY (4E3) and MSC (4E4) flip-flops. The setting of the BUSY
flip-flop causes an End of Busy Set pulse (EBSl) (4N3) to be generated. This pulse is generated from the
falling edge of BSYO (4F3), and is used by the branch gate circuit to initiate the transfer cycle. The
busy latch circuit remains set until the ESELCH detects the termination of transfer and its state is presented to the program via Bit 12 of the Sense Status byte.
The Multiplexor ESELCR Control (MSC) flip-flop is reset by SCLROA (4A5) or by addressing the ESELCR
i. e., Set Gate active (SGADl) (4A5), when the Busy flip-flop is reset. The resetting of the MSC flip-flop,
MSCO active, clears any pending interrupt in the ESELCR (8C5).
4.3 Extended Direct Memory Access Bus Control Circuit
Extended Direct Memory Access Bus Control timing relationships are shown in Figures 4 and 5 timing
diagram for Memory Read Byte mode and Memory Write Byte mode respectively. An ESELCR request for
memory is started by activating Set Request (XREQO) (9M2). XREQO is activated by the branch gate circuit
(8Ml:8M8) when either the ESELCR bus has received a halfword of data from the device or, in the Memory
Read mode, whenever the Memory Data Register (MDR) is available to accept the next halfword.
If the Select flip-flop (9G2) A62 is reset, the memory is not busy (MOBZO:M3BZO) (9F6) and if REQl (9M3)
is active, XREQO is active. When the EDMA Bus receives the XREQO, a Queue pulse (QUEO) (9A2) is sent
to the ESELCR. The QUEO pulse resolves contention for the bus by freezing the request status (9C2:9E2)
It then sends a Receive Priority Chain pulse (RPCO) (9A3)".-- The QUEO pulse sets Contention flip-flop
A39 (9E2) in all requesting devices. The highest priority queued device then captures the RPCO pulse, sets
the A62 flip-flop (9D2), and does not p"ropagate the Transmit Priority Chain pulse (TPCO) (9R3) to the next
device. If the ESELCH is requesting local memory, Local Memory Request Queued (LMRQO) (9Gl) is sent
to the EDMA Bus at this time. If the EDMA Bus is not busy, a Start of Transmission pulse (SOTO) (9C9)
is sent to the ESELCR. SOTO then sets a Select flip-flop (9G2) which in turn removes XREQO and activates
Memory Busy (MXBZO) (9F6). Once the Select flip-flop is set, the SELO (9B7) enables the oscillator circuit
(9D6) and the counter (9D8) starts counting. If it is in the Memory Read mode, Address MAXl21:151 and
MA001:l5l (6Gl:6G8) is presented to the EDMA Bus as DMX120:150 and DMAOOO:l50 (6N1:6N7) and a
Load (LOADl) (9J8) signal strobes the address into the Processor. At the same time, an End of Transmission pulse (EOTl) (9L7) is sent to indicate to the EDMA Bus that the ESELCR has finished the transmission. EOTOA (9C4) fires a one-shot and resets the Select flip-flop and EDMA Bus control cycle is
finished. In the Memory Write mode the operation is the same as in the Memory Read mode except that
two consecutive LOADls (9J8) are sent. The first one is for the address and the second is for the data.
Figure 6 shows the EDMA Bus control timing.
8
02-328A2l ROI 2/76
XREQO
-_. __ ..
6
QUEO
RPCO
Lr.lRQO
SOTO
DATA
BUS
LOAOO
EO TO
"'REQO
""ClKI
~RO
MOBlO
BHO
ANSO
EMXI
BACTI
SXI
PSRO
PSYNO
DEVICE
BUSYI
OXI
ENGI
PDAO
EOXO
TAARO
AARI91
MCHI
COMMAND GO
DBSYI
--....,
EBSI
lOBO
lOBI
2
SEll
RBAI
SATNO
BSYI
_.~COMMAND
GC
;.;; I., PROCESSOR
Figure 4. ESELCH Memory Read Byte Mode, Transfer Five Bytes
9/10
DBSYI
COMMAND GO
EBSI
SXI
PSRO
PSYNO
DEVICE
BUSYI
DXI
ENGI
PDRO
EDXO
TAARO
AARI91
BACTI
LDRHO
LDRLO
LOBI
XREQO
QUEO
RPCO
LMRQO
SOTO
DATA
BUS
LOADO
EOTO
MOB~O
*REQO
*CLKI
*ERO
SELl
RBAI
MCHI
SATNO
BSYI
COMMAND GO
*'IN PROCESSOR
Figure 5. ESELCH Memory Write Byte Mode, Transfer Five Bytes
11/12
SOTO
SOTOA
SEll
'
Pl
A
B
LOAD1
ADDRESS
MEMORY
READ
Eon
NOTE: DOTTED LINES FOR MEMORY READ
Figure 6. Extended Direct Memory Access (EDMA) Control Timing
4.4 Address Register and Auxiliary Address Register
The Address Register (6Fl:6FS) and the Auxiliary Address Register (5B3:5N3) each consist of five four-bit
counters. These registers are loaded by the Processor from Data Lines DOSO:150 (2A5 and 2AS), under
control of the Load/Unload Sequencer (6C4) with the starting address from which the block transfers is to
begin. The contents of the Address Register is gated onto the EDMA Bus Data Lines DMX120:150 and
DMAOOO:150 (6Nl:6N7) whenever the ESELCR is selected (SELOA at 6L,1 controls). The Address Register
is incremented twice with each memory transfer by EOTOA and ENDO (6D6). The Auxiliary Address Register (5B3:5N3) keeps track of the transfer between the ESELCR and device. This register is incremented,
by one, for each byte of data transferred by Toggle Auxiliary· Address Register (TAARO)(5Bl). When the
transfer is in the Ralfword mode, TARRO is generated twice for each transfer. The outputs of the Auxiliary
Address Register are used by the match circuit to determine the end of the data blocks. It's contents may
be examined, via the program, by issuing two or three consecutive DRs to the ESELCR when the sequencer
is initialized. In addition, AAR191 (4RS) is used in the Byte Transfer mode to determine whether the byte
being transferred is odd or even, for byte steering. Carry Out from the most significant stage of the Auxilary Address Register (5Ml) terminates the transfer, clear Busy (4Fl), when a transfer is attempted past
the maximum address. This feature prevents 'wrap-around' in memory.
O~:-328A21 ROl 2/76
13
4. 5 Final Address Register
The Final Address Register (FAR) is implemented by five quad latches (5B5:5N5). The register is loaded
by SETAARO (5BI) when a GO cCimmand is executed. The outputs of this register are used exclusiyely
by the match circuit to determine when the final address of the transfer is reached.
4. 6 Memory Data Register and Data Buffer
The Memory Data Register (Sheet 7) is a 16-bit register composed of 16 edge triggered flip-flops. In the
Memory Read mode, the data is toggled on the leading edge of Controlled Answer (CANSO) (7 A9). During
'a Memory Write, data is toggled into the flip-flops on the trailing edge of the Load Data Register High
(LDRHO) (7A9) or Load Data Register Low (LDRLO) (7HS).
As soon as the Memory Data Register is loaded, if the Data Buffer is empty as determined by the inactive
state of the Buffer Active flip-flop (4G2), the contents of the Memory Data Register are loaded into the
'Data Buffer by Load Data Buffer (LDBI) (7 A9). Information present in the Data Buffer is, in turn, either
written into memory via EDMA Bus Data Lines DMAOOO:150 or sent to the device on Private Data-Lines
PDOOO:150.
4.7 Data Transfer Circuit
Refer to Figure 4 for Memory Read Byte mode timing diagram and Figure 5 for Memory Write Byte mode
timing diagram. Both timing diagram show the timing of five'byte transfer in the Byte mode.
A GO command to the ESELCH sets the Busy flip-flop (4E3) which generates the End of Busy Set pulse (EBSl)
(4N3).
In the Memory Read mode, XREQO (9M2) is generated by Command GO (CMDGO) (9K4), thus a request
for memory is initiated. When the halfword of data is present in the Memory Data Register, the End of
Memory Transfer pulse (ElVIXl) (SL7) becomes active and the branch gate circuit once again requests
memory and generates Set Status Transfer (SSXO) (SR4) and Load Data Buffer (LDBl) (9NS). These
signals initiate the transfer to the device and load the Data Buffer respectively.
SSXO sets the Status Request flip-flop (4C6) which activates the Private Status Request control line (PSRO)
(4F6) to the active device on the private ESELCR Bus. This Status Request examines the four least significant bits of the status byte. If JOY of the three least significant bits (EXt. EOM I or DUJJ-~.¥.1 the transfer is terminated by resetting the Busy flip-flop (4E2). Assuming that each of these status bits remain reset for the remainder of this discussion. With Bit 12 (Busy) of the status byte reset, the Data Transfer
flip-flop becomes set (4CS). Data transfer (DXO) (4DS) inhibits the generation of PSRO, which causes
Private Sync (PSYN1) (4N4) from the device to become inactive. This enables Engage to go high (ENG1)
(4GS), which allows the Private Data Available control line (PDAO) (4J6) to become active. -, The Private
Data Available/Request signal (PDARI) (4A6), generated whenever a Private Data Available (PDAO) or
Private Data Request (PDRO) signal is active, clears the Status Request flip....:flop~ Upon receipt of Sync
from the device, PSYNI active, the Data Transfer flip-flop becomes reset and ENGI goes low,- disabling
PDAO. When the Sync is removed by the device, an SO nanosecond End of Data Transfer pulse is generated
(EDXO) (4N9) which increments the Auxiliary Address Register and is used by the' branch gate circuit to
generate a SSXO which starts the sequence again. When EDXO and AAR191 are bo.th active, Reset Buffer
Active (I:t:SAO) (SR3) is generated" It resets the Buffer Active flip-flop (4G2) and requests the memory
again (9K4). This cycle continues until termination of the transfer is detected.
In the Memory Write mode, WTl active (4F5), EBSI (SK4) is used to generate SSXO, and the branch gate circuit
directs the loading of a halfword of data into the Data Buffer before a memory request 'is made. The trans':"
fer of data from the device is the same as described in the Memory Read mode, except that ENGI is used
to generate the Private Data Request control line (PDRO) (4J5) rather than PDAO. Data from the device
is loaded into the Memory Data Register on the trailing edge of either Load Data Register High (LDRRO)
(4KS) or Load Da.ta Register Low (LDRLO) (4J7), depending on which eight bits are being loaded. In the
Halfword Tl'ansfer mode, both LDRHO and LDRLO are generated simultaneously. With WTl active, the
generation of EDXl is delayed by activating the clear input to the oIle-shot (4L9) when the Buffer Active
flip-flop is set (BACT!) (4G9), if either the transfer to the device is on an odd boundary or when a Match
is detected (MCHO) (5H9). This prevents the reloading of the Data Buffer before the last halfword has
been written into memory.
14
02-328A21 ROI 2/76
4.8 RACKO/TACKO Contention Circuit
The ESELCR directs the propagation of the Acknowledge signal to lower priority devices on the Multiplexor
Channel Bus as well as devices on the private ESELCH Bus. If the ESELCR Attention flip-flop (8C5) is
set, the ESELCR captures the Receiver Acknowledge signal (RACKO) (8A4), places its device address on
~he data lines and returns Sync to the Processor, Attention Sync (ATSYNO) (8R3) active. If the Attention
flip-flop is reset, RACKO is propagated as either Private Transmit Acknowledge (PTACKO) (8G2) or Transmit Acknowledge (TACKO) (8GI). Since devices on the private ESELCR Bus have a higher interrupt priority
than devices below tlie ESELCR on the MPX Bus; if the Private Attention line is active (PATNO) (8A3),
PTACKO is generated rather than TACKO. Note that when MSCI is low (8C2), PATNO is disabled so that a
device on the private ESELCR Bus may not interrupt the Processor while the ESELCR is active.
4.9 Strap Options for Address Space Allocation
I
Address space allocation for the four memory banks is determined by strap options in the ESELCR. Each
memory bank's address space must be zero or a multiple of 64K bytes up to a maximum memory capability
of 1, 024K bytes for the 8/32 Processor, a maximum of 256K bytes for the 7/32 or 7/32C Processor, or a
maximum of 512K bytes for the 7/32C with the 35-527M02FOl Memory Access Controller. Address assignment must be contiguous and the four memory banks are assigned address space in ascending order.
In the ~SELCR printed circuit board, there are two decoders, A03 and A04, (8C6, 8C7) which decode the
extended address bits (four most significant address bits). Each output of the decoders allocates 64K bytes
of memory. The 16 outputs with wire wrap stakes are marked 0:15. The four wire wrap stakes next to
them are marked MOO, MIO, M20 and M30 (8D5, 8D8) denoting the four memory banks. The address space
alloe:ation should be strapped according to system configuration. All non-existent memory locations should
be strapped to the stake marked NE (Non-Existent) Memory. See Figure 7 for details.
5. INSTALLATION CHECKS
Before attemptIng any maint~nance or testing, insure that the necessary back panel modifications and
ESELCR board option strapping have been made in accordance with the 02-328A20 ESELCH Installation
Specification.
To insure a 2, 000, 000 Byte/Second transfer rate in the Ralfword Transfer mode, it is necessary to limit
the maximum delay between PDAO, PDRO, and PSRO and the return of Sync from the device (PSYNO) to 50
nanoseconds. In addition, the EDMA Bus must have only one active MAC (i. e., the ESELCR), the device I
must be ready for the next byte of data, Busy status bit reset, whenever a Status Request (SR) is made.
"Field testing of this device is contingent upon the user having the appropriate software and hardware available with which to exercise the ESELCRs. Refer to Test Program Description 06-161 a configured requirements. There are no adjustments associated with this device.
02-328A21 R03 9/78
15
ADDRESS
MOO
0
00
64K
BANKO
01
64K
A03
02
64K
64K
03
DECODER
256K-1
04
o M10
05
BANK"I
06
07
512K-1
M20
OS
BANK2
09
A04
10
11
76SK-1
DECODER
12
13
BANK3
1024K-1
MEMORY SYSTEM
14
NE
15
(NON-EXISTENT MEMORY)
STRAP OPTION
ADDRESS
00
0
64K
BANKO
01
64K
A03
02
64K
I
64K
03
256K-l
DECODER
04
64K
BANK1
MOO
M10
05
64K
06
512K-1
M20
64K
64K
BANK2
64K
64K
A04
768K-1
64K
M30
DECODER
BANK3
1024K-l
MEMORY SYSTEM
NE
STRAP OPTION
(NON-EXISTENT MEMORY)
Figure 7. Address Allocation
16
02-328A21 R02 5/78
ADDRESS
00
0
64K
MOO
01
64K
A03
02
64K
03
64K
DECODER
M10
64K
64K
BANKO
64K
64K
M20
704K-1
I
A04
BANK1
11
832K-1
BANK2
M30
DECODER
896K-1
BANK3
1024K-1
MEMORY SYSTEM
NE (NON-EXISTENT MEMORY)
STRAP OPTION
(FOR 8/32 ONL Y)
Figure 7. Address Allocation (Continued)
02-328A21 R02 5/78
17
6. MNEMONICS
The following list provides a brief description of each mnemonic found in the ESELCR. The source of each
signal on Functional Schematic 02-328D08 is also provided.
MNEMONIC
SCHEMA TIC LOCATION
MEANING
AAR001:191
Outputs from the Auxiliary Address Register
5A6-5N6
AD1
Address-active when ESELCR is addressed
3N9
ADDAO
Address and Data Control-in Memory Read mode,
LOADO strobes the address to the EDMA Bus.
In Memory Write mode, the first LOADO strobes
the address and the second LOADO strobes data to
the EDMA Bus.
9J9
ADRSO
Address control line from MPX- Bus
4K7
ANSO
Answer control line.,.sends data from memory to
ESELCH
6N9
ATNO
Attention-Attention to Processor
8E3
ATSYNO
A ttention Sync-generated by an Acknowledge Attention
from the Processor
8H3
BACT1
Buffer Active-indicates that valid data is present in the
data buffer
4H1
BSY1
Busy-indicates data transferred in progress
4F3
CANSO
Controlled Answer-to insure that the answer is
coming from the right memory.
8J6
CBSYO
Clear Busy-terminates transfer when a match
or a non-existent memory is detected
8R5
CL070
Power Failure Clear
4K5
CLG1
Control Line Gate-gates private control lines
CLGA1
Control Line Gate-same as CLG1 except used to
assure a 100 nanosecond delay between ADRS,
CMD, DA, and the Data Lines
2G2
CLUSO
Clear Load/Unload Sequencer-clears sequencer
4F2
CMDGOO
Command GO-starts the whole sequence
4H4
CMDO
Command control line from MPX-Bus
4K6
coo
Carry Out of the Auxiliary Address Register-Prevents memory wrap-around
5M1
DOOO:150
Data Lines from MPX-Bus
2A5-2A8
3A7-3A9
DAO
Data Available control line from MPX-Bus
4K6
DB001:151
Outputs from Data Buffer
7F1-7F8
7Nl-7N8
18
02-328A21 ROl 2/76
SCHEMA TIC LOCATION
MNEMONICS
DBSYl:
Delayed Busy-to insure that the memory cycle is
finished before sending out an interrupt
4Ll
DLGI
Data Line Gate-gates data line and private data lines
2R2
DMJ~000:170
EDMA Bus Data Lines
6N2-6N9
D:MX120: 150
EDMA Bus Extended Data Lines
6Nl
DRO
Data Request control line from MPX- Bus
4K5
DXl
Data Transfer-Data Transfer flip-flop
4DS
EBSI
End of Busy Set-signals the start of a ESELCH
transfer
4N3
EDXO
End of Data Transfer-signals the end of a device
transfer
4N9
EIVIXI
End of Memory Transfer-signals the end of a memory
transfer
SL7
ENGI
Engage-gates either PDAO or PDRO
4G8
EOTO
End of Transmission-to tell EDMA Bus that transmission is ended.
9L8
FHOOl:071
Final Address Register High- Final Address Bits
00:07
5G5-5K5
FLOOl:071
Final Address Register Low- Final Address Bits
OS:15
5A5-5E5
GETBUSO
ESELCR gets the EDMA Bus in Memory Read mode
8J5
LDJBl
Load Data Buffer-loads data into Data Buffer
8NS
LDHH
Load Data Register High-loads Data Bits 00:07
4K8
LDRLO
Load Data Register Low-loads Data Bits OS:15
4J7
LFRXO
Load Final Address Register Extended Bits 00:03
6D6
LMRQO
Local Memory Request Queued
9Gl
LOADO
Load control line-loads Data or Address to EDMA
Bus
6N9
MOO:30
Memory Banks 0:3
8D6-SD8
MOBZO:M3BZO
Memory Busy
9F6
MAOOl:151
Memory Address Bits
6G3-6G7
MAX121:151
Extended Memory Address Bits
6Gl
MeRl
Match-indicates a match between the Auxiliary
Address Register and Final Address Register
5K9
02-328A21 ROl 2/76
19
MNEMONICS
SCHEMATIC LOCATION
MEANING
MMFI
Memory Malfunction
7K3
MSCI
Multiplexor-ESELCH Control flip-flop
4F5
PADRSO
Private Address control line to ESELCH Bus
4N7
PAGEOl:ll
Pages Ol:ll-encode MOO:M30
8G6-8G7
PATNO
Private Attention from ESELCH Bus
8A3
PCL070
Power Failure Clear to ESELCH Bus
4N5
PCMDO
Private Command control line to ESELCH Bus
4N6
PDOOO:150
Private Data Lines- ESELCH Bus
2N5-2N9
3H7-3H9
PDAO
Private Data Available control Hne to ESELCH Bus
4J6
PDRO
Private Data Request control line to ESELCH Bus
4J5
PFI
Memory Parity Failure
7K4
PGOO
Page Zero-indicates that four WDs are used to Set up
Starting and Final Addresses, i. e., the Final Address
is no greater than 64K Bytes.
6Al
PHWO
Private Halfword control line from ESELCH Bus
2Dl
PSRO
Private Status Request control line to ESELCH Bus
4F6
PSYNO
Private Sync from the ESELCH Bus
4K4
PTACKO
Private Transmit Acknowledge to the ESELCH Bus
8H2
QUEO
Queue-to resolve contention for EDMA Bus
9A2
RACKO
Receive Acknowledge from MPX-Bus
8A4
RBAO
Reset Buffer Aptive-reset Buffer Active flip-flop
8R2
RBAOA
Controlled Reset Buffer Active-the leading edge clears
the Buffer Active flip-flop in Memory Read mode and
the trailing edge clears the Buffer Active flip-flop in the
Memory Write mode.
8R3
RPCO
Receive Priority Chain from EDMA Bus
9A3
SATNO
Set Attention flip-flop
4Nl
SBACTl
Set Buffer Active-set Buffer Active flip-flop
8R6
SCLRO
System Clear-initialize signal
3K9
SDXO
Set Data Transfer flip-flop-if no error status
4Fl
20
02-328A21 ROI 2/76
; MNEMONICS
SELl
MEANING
SCHEMA TIC LOCATION
Select-ESELCH gets the EDMA Bus
9H2
Selch Status Command Bi ts
4C3
SETAARO
Set Axuiliary Address Register
3R6
SGADO
Set Gate-sets Add.ress flip-flop
2J6
SOTO
Start of Transmission-to tell the ESELCH to start
transmitting an address and data to the EDMA Bus
9C9
SRO
Status Request control line from MPX-Bus
4K4
SSXO
Set Status Transfer-sets the Status Request flip-flop
8R4
SXl
Status Transfer-Status Request flip-flop
4D6
SYNO
Sync to MPX - Bus
3R7
TAARO
Toggle Auxiliary Address Register-increments Auxiliary Address Register
8N2
TACKO
Transmit Acknowledge-to lower priority device on the
MPX Bus
8H1
TPCO
Transmit Priority Chain from EDMA Bus
9J3
UAARHO
Unload Auxiliary Address Register High-unload
Auxiliary Address Register Bits 04:11
6D4
UAARLO
Unload Auxiliary Address Register Low-unload
Auxiliary Address Register Bits 12:19
6D4
UAARXO
Unload Auxiliary Address Register Extendedunload Auxiliary Address Register Bits 00:03
6D5
WT1
Write flip-flop
4F5
XREQO
Request-request EDMA Bus for service
9M2
. SELSTS1
02-328A21 ROI 2/76
21/22
DISPLAY PANEL
09-065R03A12
May 1978
METRIC
M71-102
HEXADECIMAL DISPLAY
INFORMATION SPECIFICATION
1.
INTRODUCTION
The optional Hexadecimal Display Panel provides a means to manually control the Processor, interrogate and display
various Processor registers and machine status, set and display Processor memory locations, and may be programmed
as an I/O device by the user.
This specification describes the 09-065F02 Hexadecimal Display Panel (Product Number M71-102). It is also applicable
to the 09-065FOl Binary Display Panel (Product Number M71-101), which is identical to the Hexadecimal Display Panel
except for the omission of the 'hexadecimal indicators. The Hexadecimal Display Panel provides the following functions:
Displays five bytes of programmable digital information.
Reg!isters and displays five hexadecimal digits of manually entered keyboard data.
Displays the WAIT and Power (PWH) indicators for the Processor.
Provides a 26 key control keyboard tor manual input to the display.
Provides two bytes of unbuffered Switch Register data to the Processor.
Provides one byte of status to the Processor.
Provides a three position OFF-ON- LOCK key type switch capable of switching three separate power supply controllines.
Provides a control signal to the Processor that the display requires micro-program support.
2. GENERAL DESCRIPTION
A complete description of the operation of the Hexadecimal Display Panel is provided in the appropriate User's Manual.
This specification describes the display from a maintenance view point. Figure 1 shows the Hexadecimal Display Panel.
09-065A12 R03 5/78
1
~
________________________
6
~
________________________
~)(~
_ _ _ _ _ _- A_ _ _ _ _ _
~,
-II
J3
12
14
15
II
5
16
II
17
18
~GiJD8B
19
OFF
..
0000 0000 0.000110000 0000 0000 0600
0000110000
,
MEMORY ADDRESS
MEMORY DATA
lal16
15
"1 9
SWITCH REGISTER
0'9
'!II
PROGRAM STATUS WORD
0' FUNCTION 19
"
GENERAL REGISTER
0' REGISTER I~Z
FLOATING REGISTER
"
09 REGISTER ).
'18
o.
{
IZ
SEl
Q;JQ;J~[Ja
~~~~EJDEJ
. ~~~[2JEJ
B66E3EJ
"
[
0
WAIT
0
POWER
[[Je
]
3
Figure 1. Hexadecimal Display Panel
Various parts of the Hexadecimal Display Panel in Figure 1 are numbered to correlate to the following descriptions.
1.
Control Keyboard. The keyboard is the operators manual input to the Processor.
The function of the specific
keys are:
DTA
The function of the Data (DTA) key is to clear the Switch Register, connect the Switch Register to
the display indicators, and enable hexadecimal data to be entered into the register. The Switch Register remains enabled and connected to the display indicators until any non-hexadecimal key other
than DTA is depressed.
Hexadecimal Keys 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F supply data to the Switch Register when it is enabled, and the function number or register number for the Processor supported
display (see Section 2.2).
ADD
The Address (ADD) key causes the Processor to read the five hexadecimal characters of the Switch
Register, store them in the address portion of the Program Status Word (PSW), and display PSW
32:63 on the indicators.
RD
The Fead (RD) key causes the Processor to read the memory location specified by the PSW, increment the PSW address by two, and display on the indicators the new address and the data read
from memory.
WRT
Depressing the Write (WR T) key causes the data contained in the Switch Register to be written into
the address specified by the PSW, the PSW to be incremented by two, and the new address and the
data written to be displayed on the indicators.
F'LT
Depressing the Floating-Point Register (FLT) key, followed by any hexadecimal key n, causes
Floating-Point Register n to be displayed on the indicators.
REG
Deptessing the Register (REG) key, followed by any hexadecimal key n, causes general register n to
be displayed.
FN
Depressing the Function (FN) key, followed by any hexadecimal key n, causes the Processor to perform "Function n" as described in the appropriate User's Manual.
SGL
Depressing the Single Step (SGL) key causes the Processor to execute one user instruction and display the last register or function selected.
RUN
Depressing the Run (RUN) key causes the Processor to enter the Run mode at the address specified
by the PSW.
INI
Depressing the Initialize (INI) key initializes the Processor.
SEL
Depress DTA, then 0 or F, for selection of Register Set 0 or 1 respectively. Then depress the
Function (FN) Key followed by SEL to enable the selected register set to be displayed.
NOTE
The display requires support from the micro-program for all
functions other than entering or displaying Switch Register data.
2
09-065A12 R02 1/75
2. OFF-ON-LOCK Key Operated Locking Switch. This switch controls the power to the Processor and allows
the keyboard to be completely disabled in the LOCK position.
3. Indicator Formats.
These formats aid the user in interpreting the display indicators.
4. Format Selectors LO:4. Light Emitting Diode (LED) indicators LO:4 determine the format to be used to interpret display indicators L5:40.
5. Display Indicators L5:40. These LED indicators aTe used to display the PSW, general registers, etc., as
described by the indicator formats.
6. Display Indicators 11:9. These indicators display the corresponding values displayed on L5:40 in the hexadecimal format.
7. WAIT and PWR.
to the Processor.
These indicators are illuminated when Processor is in the Wait state and Power is supplied
2. 1 Switch Register Entries
When the operator is manipulating the Switch Register, there is no interaction between the display and the Processor.
Data is entered into this register by first depressing the DTA key. This operation clears the Switch Register; connects
the Switch Hegister to L5:24 of the display, and allows subsequent hexadecimal keyboard entries to be left shifted into
the least sil~ificant digit of the resigter. The register is disconnected from the display and disabled when any nonhexadecimal key other than DTA is depressed. The register can be momentarily examined when it is disabled without
affecting the Processor operation by depressing any hexadecimal key.
2. 2 Processor Intervention
Depressing the following single keys causes the signals ESNCO and ESNOO to be complimentarily pulsed (ESNCO is a
positive going pulse):
ADD
RD
WRT
SGL
RUN
Depressing one of the following sequences of two keys causes a similar action:
FLT n
REG n
FN n
(n is any hexadecimal digit)
3. FUNCTIONAL DIAGRAM ANALYSIS AND CIRCUIT DESCRIPTION
Refer to Figure 2. Hexadecimal Display Panel Block Diagram and Functional Schematic 09-065DOB.
3.1 OFF-ON-LOCK Switch
This switch (2Kl) controls power to the Processor by completing the circuit between CONT2 and CONTI in the ON and
LOCK positllons. The switch is factory wired to provide one set of closures. This switch also provides a hard ground
to the Processor as POFFO in the OFF position which may be used as an early power down indication. When the switch
is in the ON position, LP5 (2Ll) is provided to the keyboard to enable the sensing of these switch closures.
3.2 Keyboard
The keyboard (Sheet 2) has a 5 x 5 switch array which is used to enter information to the Hexadecimal Display Panel logic,
plus an Initialize (INI) key used to transmit this condition to the Processor (2Gl). The keyboard is a self-contained unit
and connect8 to the 35-520 logic board by 27 stakes, 00-1 through 26-1. These normally open switches are encoded by
diode logic (Sheet 2) to form HEXOl:31 (2BB) and FUNOO:30 (2CB), plus a few additional control signals mentioned later
in this description. The switches are designed to be high active when a switch is depressed by biasing all receiving
gates low with a 220 ohm input resistor. A switch being depressed causes an input gate to go high by supplying LP5
through a current limiting resistor from the common input, Pin 0, if the OFF-ON- LOCK switch is in the ON pOSition.
There is no keyboard rollover protection and if more than one key is Simultaneously depressed, the result is unspeCified.
09-065A12 H02 1/75
3
'\/
0
::s
en
Z
0
Z
W
W
N
I--
u.
u.
0
Z
en
U
Z
0
CO
...J
0
0-
"v'
/
/
;'
/
,/
U
;:
I--
8
.S:
Z
~
~
LO:4
,
I
11 :5
I
L5:24
!
J
I
16:9
I
I
L25:40
I
t
LOAD DISPLAY
SHIFT REGISTER
AND LOGIC
ON/OFF
SWITCH
KEYBOARD
AND LOGIC
I
I
l
L41
FUN(0:3)
FHGX(0:3)
1
MULTIPLEXOR
DISPLAY
MODE
REGISTER
r
I
ff
L-
DISPLAY
REGISTER
t
t
-
I
DISPLAY
REGISTER
1
L
SRCLK
J
CLOCK
GENERATION
LOGIC
FTYPCL
FHEXCL
DISSWl
STATUS
REGISTER
LOW HALF
SWITCH
REGISTER
'L-
I
:cen
-
)
I
SRAG
LOGIC
I
ISRFGtJ
(!)
a:
en
0
...J
en
STATUS
REGISTER
HIGH HALF
IlJ
TO PROCESSOR
-
DOl :71
BIDIRECTIONAL DATA LINES
Figure 2. Hexadecimal Display Panel Block Diagram
3.3 Matrix Encoding
The diode matrix is encoded to drive signals HEX01:31 to the hexadecimal equivalent of the respective key O:F (HEX31 is
the LSB) when it is depressed. Depressing any function key other than DTA causes FUNOO:30 to yield the codes specified
by Table 1.
TABLE 1. FUNCTION KEY ENCODING (FUNOO:30)
Key Depressed
SGL
RUN
WRT
RD
FUNOO
0
1
1
FUN10
ADD
1
1
1
1
1
0
0
REG
FLT
FN
0
0
0
1
1
1
FUN20
1
1
0
1
0
1
0
1
FUN30
1
1
1
1
1
0
0
1
3.4 Clocking
Depressing any keyboard key other than DTA or INI generates one of three types of clocks used by the Hexadecimal Display Panel logic. This is accomplished by a positive transition of signal KEY1 (2FS) whenever one of these keys is depressed. The one shot triggered by this transition (2GS) is used to allow a one to two millisecond interval for switch
bounce to subside before triggering the second one shot STRB1 (2KS) which is used to generate one of the three clocks.
Since contact bounce is likely to retrigger these one shots when a key is released, the occurrence of signal KEYl (any
key depressed), HKEYI (2F9 a hexadecimal key depressed), or FKEYI (2H7 a function key depressed) being true in coineedence with the one shot is used to derive the clocks.
4
09-065A12 R02 1/75
3. 5 Switch Register Clocks
The Switch Hegister is enabled for clocking by depressing the DTA key. This is accomplished by direct clearing the
Switch RegiHter Enable flip-flop (SRENB) (2L6) when DTA is depressed and ANDing the zero output of the flip-flop plus
HKEYl and STRB1 to drive the Switch Register Clock (SRCLKO) (2M7). This clock is disabled by setting SRENB with
the occurrence of FKEY 1 when any function key is depressed.
3. 6 Status Register Clocks
Two different clocks are used to load the status register. FTYPCLO (2MS) is generated whenever any function key other
than DTA is depressed and is used to load FUNOO:30 into one half of the status register. The second clock FHEXCLO
(2NS) is generated whenever a hexadecimal key is depressed if the previously depressed key was FN, REG, or FLT.
In this case" the hexadecimal input would be the register number or function number desired and FHEXCLO is used to
clock HEX01:31 into the second half of the status register.
3. 7 Processor Intervention
The logic of the display signals the Processor that a response is necessary to a console function by signal ESNCO (2R7)
and its compliment ESNOO (2R7). These signals are complimentarily pulsed whenever a function key other than DTA,
FN, REG, or FLT is depressed, or whenever a hexadecimal key is depressed following FN, REG, or FLT (the occurrence of FHEXCLO).
3. S Swi tch Register Loading
The Switch Register (4B1, 4D1, 4Gl, 4J1, and 4M1) is loaded with a hexadecimal character with the occurrence of each
SRCLKO as mentioned previously. Data is entered into the least Significant character (4B1) from the switches (HEX01:
31) and left shifted through the register with each clock. The register is cleared whenever the DTA key is depressed.
3. 9 Status Register
The status register is loaded in two parts as described previously. One half is loaded from FUNOO:30 when a Function
(FN) key is depressed by the occurrence of FTYPCLO. The least significant bit of this register is re-circulated on SGL
or RUN and the second LSB is re-circulated on SSL to conform to the status codes indicated in Table 2. The second
half of the register is loaded from HEX01:31 with the occurrence of FHEXCLO. These registers are initialized by SCLRO
from the Processor.
TABLE 2. STATUS CODES
KEY
DL1 DL2
SGL
1
INITIALIZE
DL3 DL4
DL5 DL6
DL7 DLO
U
X
X
X
X
X
X
U
U
U
U
U
U
0
U
RUN
0
0
0
X
X
X
X
X
WRT
0
0
1
U
U
U
U
U
RD
0
1
0
U
U
U
U
U
ADR
0
1
1
U
Al
A2
A3
A4
REG n
1
0
0
1
n1
n2
n3
n4
FLT n
1
0
1
1
n1
n2
n3.
n4
FN n
1
0
0
0
III
Il2
Il3
Il4
A = Most Significant hexadecimal digit of Switch Register
U = Unspecified
X = Unchanged
n = Hexadecimal digit associated with function (see Section 6)
The display status is presented to the Processor on the data lines (DLOl:7l) for the duration of time that control s'ignal
SRGO is at a logical zero level. The data presented for status is in accordance with Table 2.
09-065A12 R02 1/75
5
3. 10 Display Register Loading
The Hexadecimal Display Panel registers and displays five bytes of data transmitted from the Processor. Two control
signals are transmitted from the Processor to direct the loading of these registers. LAO (2K5) is a low active pulse
which signifies that data is available on bi-directional Data Lines D01:71 and it is to be loaded into the least significant
byte of the display register. LAO is used to initialize a four bit shift register (2M4) to 1000 2 which is used to load
subsequ~nt bytes, and generate a load pulse LA 1 which is used to load the data into the LSB of the display register (2B6
and 3E6). Four subsequent LBO pulses sent from the Processor gates data from D01:71 into successive bytes of the
display register (3G6 and 3.16, 4C5 and 4E5, 4G5 and 4K5, 4N5 and 3N2). This is accomplished as each LBO pulse is
inverted and gated as LDB1, LDC1, LDDI and LDE1 (2N4) respectively as controlled by the sequencing shift register
(2M4) which is right shifted with each LBO pulse.
3.11 Display Indicators
The two least significant bytes of the display register are gated directly to LEDs L25:40 and the hexadecimal indicators
16:9 (Sheet 3). LEDs L5:24 and hexadecimal indicators I1:5 are used to display either the most significant bytes of
the display registers or the Switch Register. These sets of registers are selectE-d through the 2:1 multiplexors (4C6,
4E6, 4H6, 4K6 and 4N6) as determined by the state of the DISSW1 (2N6). DISSW1 is high whenever the Switch Register
is enabled (SRENB1) or a hexadecimal key is depressed (HKEYl).
3. 12 Processor Inputs
Data is gated to the Processor in response to control signals SHIO, SLOO or SRGO. SLOO gates the two least significant
digits of the Switch Register onto the bi-directional Data Lines D01:71 (4C3 and 4C4). SHIO gates the next two Switch
Register digits onto the bi-directional Data Lines D01:71 (4H3 and 4K3): SRGO causes the status register bits to be
gated (3D4)' as per Table 2. Note that either the most significant Switch Register character is gated (4N3) if DL11 is low
or the hexadecimal portion of the status register if DL11 is high (3H4).
4.
PROCESSOR INTERFACING
4.1 Processor Connector
Signals from the display are terminated at a 26-080F06 type connector per the following list:
SIGNAL
PIN
DOl
D11
D21
D31
D41
D51
D61
D71
POFFO
CONTI
CONT2
CONT3
SCLRO
109
110
111
112
202
204
205
208
105
DB1-C1 & 214
DB1-C2
DB-C3 & 213
107
4.2 Timing
PIN
SIGNAL
LAO
LBO
SHIO
SLOO
WAIT1
SRGO
ESNCO
ESNOO
INITO
SSGL1
GND
GND
GND
GND
*Xl-X4 Al-8 leads to front terminal strip of chassis.
*Xl-X4
203
Xl
X2
114
X3
200
X4
206
102
113
103
104
101
106
100-3
108
212 twisted with
201 twisted with
PIN
207
211
210
209
114
203
a. 50ns min.
DATA VALID ON (001:71)
~
DATA VALID
b. lOOns min.
c. 50n5 min.
LAO OR LBO
d. 50n5 max.
e. Ons min.
SLOO OR SHIO OR SRGO
f. 500ns±10%
ESNOO
g. 25ns
SSGLl
____--IF
h
-t
I
Figure 3.
6
~i=-,
I
~--------------------
h. lOOns
j. lOOns
Hexadecimal Display Panel Timing
09-065A12 R02 1/75
5. INSTALIJATION PROCEDURE
The Hexadeeimal Display Panel is connected to the Processor via a 17-305 9able. The 26-080F06 30-pin connector of
the Hexadecimal Display Panel plugs into the mating connector as shown in Figures 4, 5 and 6.
CNTL1, CN'TL2, P5, GND, LGND, +L jumpers go to corresponding lugs on the Processor chassis display terminal
strip as, shown in Figure 4.
6.
POWER
The Hexadeeimal Display Panel draws its power from the P5 and +L lugs on the Processor chassis display terminal
strip. See Figure 4.
11
13
12
16
15
14
0000 0000 0000 0000 0000
o
g:
ulZ'--_...!.'l!L5I,!..!!.._ _ _
17
~Ghl0[~B
19
18
o~~oo-=o-::o"--:o::-o:::-:::o--::o::--::o::-o:::-::o-::o::-l g]~~[Ja
---=M:.:.E~MO::,:.R:,:.Y~Ac::::DD:::R:=:E~SS'------'131ll!...o-:--_ _---:.:M;.:,EM::;;O::..:,R;..:.y..::D;..:.AT:..:.A'--____ ~ ~~~EJDEJ
S_W_IT_CH_RE_G_IS_TE_R_....:.P.:.:RO;:;:G::.;R:=;:AM~S;~IAT~U:;:S,;;W~OR~D'---------:-----;31 ~~~DB W?'T
FOUNCTION IOy--____
0' REGISTER I~Z
GENERAL REGISTER
BEJ6t36
;:
PO<2ER
~02:0tR=EG=IS=T=ER=I~O'-=-=-=-=-=======-::::::!'1~8====FL::O::A::TI=NG::R::::E::G=IST::::E:::R==========:::L__________ _
LOCK
ON
e
._----17-305
DISPLAY TERMINAL STRIP
- - ==:::::J
Q
Q
Q
CPU-LO 35-520
CPU-HI 35- 446
lat MEMORY
TERMINAL LUGS
FOR DISPLAY,
AUTOLOADER,AND
BASIC SWITCH
CONTROL PANEL
MATING CONNECT FOR
[5:11 ~~RD
MATING CONNECTOR FOR DISPLAY,
AUTO LOADER, AND BASIC SWITCH
CONTROL CABLES
o
-----=
DISPLAY MOUNTING
BRACKET
44.5mm (1%") FILLER
PANEL
MOUNTING STUO
Q
Front View
Figure 4. 7/16 Basic Display Installation
09-065A12 H02 1/75
7
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MATING CONNECTOR FOR DISPLAY,
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7/16 HSALU OR 7/32 TWIN CHASSIS INSTALLATION
Figure 5.
8
Model 7/16 HSALU or 7/32 Installation
09-065A12 R03 5/78
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11
13
14
15
16
0000 0000 0000 0000 0000 0
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o
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44.5mm (1 %") FILLER
PANEL
MOUNTING STUD
o
Front View
7/16 HSAlU INSTALLATION
Figure 6. Model 7/16 HSALU Installation 7" Chassis
09-0(;5A12 R02 1/75
9
. . .r------
17- 30!l
DISPLAY TERMINAL STRIP
I---=O_ _ _ _ _ _ _ _~O_ _ _ _ _ _ _ _ ____IQ"___"O"___ _ _ _ _ _ _ _O
____________~
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BRACKET
CPU-A
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ALU
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MATING CONNECTOR FOR OISPLAY
~-=-=-~~::-:-::.,,;l""'-
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Figure 7 a Model 8/32 Twin Chassis Installation
10
09-065A12 R03 5/78
._---------
7. MNEMONICS
The following list provides a brief description of each mnemonic found in the Hexadecimal Display Panel.
of each signal on Functional Schematic 09-065D08 is also provided.
MNEMONIC
The source
SCHEMATIC LOCATION
CONT1
12 VAC to turn on power supply
2L1
CONT2
12 VAC to turn off power supply
2M1
DISSW1
Controls Display Multiplexors for L5:24
2R6
ESNCO
Execute switch normally open
2R7
ESNOO
Execute switch normally closed
2R7
FTYPCLO
Function type status register clock
2N7
FHEXCLO
Hexadecimal type status register clock
2N8
FUNOO::3:0
Encoded functional keys
Sheet 2
HEX01:31
Encoded hexadecimal keys
Sheet 2
INITO
Initialize Processor
2H2
LAO
Low active Signal from Processor which initializes the loading
sequence and loads the least significant byte of the Hexadecimal
Display Panel
2K5
LBO
Low active Signal from Processor used to control loading of display registers by generating LDB1, LDC1, LDD1, LDE1
2L5
LDB11
LDC1
LDD1
Load display registers
2R3
2R4
2R4
LDE1
Loads display mode register and most significant hexadecimal
digit of the display
2R4
POFFO
Early power OFF failure
2K1
SCLRO
System Clear, initialize status registers
3J1
SDAO
DTA key depressed
2.12
SHIO
Switch Register high half gate command
2M2
SLOO
Switch Register low half gate command
2L3
SORO
SGL or RUN keys depressed
2K2
SRAG1
Switch Register most signifieant hexadecimal digit gate command
2R2
8RCLKO
Switch Register clock
2M7
8RFG1
Status Register Function high half gate command
2R2
SRG1
Status Register low half gate command
2M2
8SL1
SG L key depres.sed
2J6
WAIT1
Wait light control
2M6
09-·065A12 R02 1/75
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Publication Number H29-394R81
M83 SERIES MODEL 8/32,
METRIC
8/32C, AND 8/320 PROCESSORS
MAINTENANCE
MANUAL
Consists of:
GENERAL DESCRIPTION
29-394R!!3A12
Generai Descripilufl
PROCESSOR
Maintenance Specification
01-018R09A21
WRITABLE CONTROL STORE
Installation Specification
Maintenance Specification
35-555F01A20
35-555F01R01A21
2K WRITABLE CONTROL STORE
Installation Specification
Maintenance Specification
35-663ROtA20
35-663A21
MEMORY
Main Memory System Maintenance Specification
35-535R02A21
EXTENDED SELECTOR CHANNel
I nstallation Specification
Maintenance Specification
02-328R04A20
02-32SR03A21
DISPLAY PANel
Hexadecimal Display Panel Specification
09-065R03A 12
DRAWINGS
Model 8/32 Backpanel Map
Model8/32C Backpanel Map (with OFU/
Model S/32D Backpanel Map (with DFU)
Processor CPU-A Schematic
Processor CPU-A Assembly
Processor CPU-B Schematic
Processor CPU-B Assembly
Processor CPU-C Schematic
Processor CPU-C As~embly
Processor CPU-C Schematic W/2K WCS
Processor CPU-C Assembly W/2K WCS
Processor IOU Scllematic
Processor lOll A~oembly
Processor All: -'>cllematic
Processor AlU Assembly
Memory Bus Controller (MBC) Schematic
Memory Bus Controller (MBC) Assembly
local Memory Interface (lMIl Schematic
local Memory Interface (lMIl Assembly
Extended Selector Channel Schematic
Extended Selector Channel Assembly
Hexadecimal Display Panel Schematic
Hexadecimal Display Panel Assembly
DMA Terminator Schematic
DMA Terminator Assembly
DMA Terminator Assembly
DMA Terminator Assembly
Processor Bus Terminator Schematic
Processor Bus Terminator Assembly
1MB Terminator Assembly
I/O Bus Terminator Schematic
110 Bus Terminator Assembly
S/32 Backpanel Terminator
01-018R04DOS
01-098R03D08
01-103ROOD08
35-536R30D08
35-536R20E03
35-531Rl1DOS
;J5-531R13E03
35-555R10DOS
35-555R06E03
35-663R02D08
35-663R01E03
35-539R21D08
35-539R 19E03
35-53SR16DOS
35-538R11E03
35-535R23D08
35-535Rl0E03
35-534R12D08
35-534ROSE03
02-32SM01ROSDOS
35-508MOl R08E03
09-065 R03DOS
35-519R05D03
35-548COS
35-54S803
35-572B03
11-336R01B03
35-569D08
35-569R01C03
35-518R01B03
35-433B08
35-433R03B03
35-596R01C03
PERKIN-ELMER
Computer Systems Division
2 Crescent Place
Oceanport. N.J. 07757
Copyright @1978bY Perkin-Elmer Corporation Printed in U.S.A. June 1981
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