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Publication Number 29-438ROl
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MOIJEL 8/32 MICRO-INSTRUCTION
REFERENCE MANUAL
CONSISTS OF:
MICRO-PROGRAM DESCRIPTION
MICRO-PROGRAM LISTING
MICRO-PROGRAM LISTING
ROM MICRO-PROGRAM LISTING
05-058R01A 15
05-058R02A 13
05-058 F02A 13
05-059A13
THIS MANUAL CONTAINS PROPRIETARY INFORMATION AND IS SUPPLIED BY
INTERDATA FOR THE SOLE PURPOSE OF USING AND MAINTAINING INTERDATA
SUPPLIED EQUIPMENT AND SHALL NOT BE USED FOR ANY OTHER PURPOSE UNLESS
SPECIFICALLY AUTHORIZED IN WRITING .
•
=-:::arr-=-:-El::EC, I
.~...~
Subsidiary of PERKIN-ELMER
Oceanport, New Jersey 07757, U.S.A.
@ INTERDATA INC., 1975
All Rights Reserved
Printed in U.S.A.
May 1976
PAGE REVISION STATUS SHEET
29-438
PUBLICATION NUMBER
Model 8/32 Micro Instruction Reference Manual
REVISION
R01
DATE 5/76
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MODEL 8/32 MICRO-PROGRAM
DESCRII)TION
,1.
INTRODUCTION
Micro-programming is a means for implementing the control logic of a digital computer. At INTERDATA, microprogramming has been effectively used to maintain upward program compatability in a family of Processors whose internal
hardware varies from one member to the next ..
like its predecessors, the Model 8/32 is designed to execute micro-instructions stored in a Control Store Read-OnlyMemory (ROM). Each micro-inst:ruction causes one or more hardware functions to be performed, such as transferring the
content of one register to another, arithmetic or logical operations between registers, controlling input/output operations,
or initiating main memory accesses.
I
A series OIf micro-instructions is called a micro-program. The complete Model 8/32 micro-program is, by definition, an
emulator, causing the Model 8/32 micro-processor to react to a user program in main memory and to external events as
would the: Processor described in the Model 8/32 Processor User's Manual, Publication Number 29-428. Every user level
instruction, interrupt handling feature and Display Panel function is simulated by some portion of the Model 8/32 .
micro-program.
2.
BLOCK DIAGRAM ANALYSIS
Refer to the Block Diagram in Figure 1.
2.1 System Organization
The Mode:! 8/32 Processor is organized between three 32-bit busses. The A and B Busses are used to present the first and
second operand data respectively to the Arithmetic Logic Unit (ALU). The S Bus then transfers the ALU output to the
appropriate destination. The source and destination of data on the A, B, and S Busses, as well as the function performed by
the ALU is controlled by micro-instructions contained in the Control Store Memory.
2.2 Control Store Memory
The Control Store Memory is a high speed, solid-state, non-destructive memory organized into a maximum of 16 pages of
256 words each. Each word is 32-bits long and represents one micro-instruction. The first five pages (1,280 words) in the
Control Store Memory contain the entire Model 8/32 micro-program. Additional pages of writeable Control Store Memory
can be added to the basic Model 8/32, allowing the user to supplement the standard instruction repertoire with special
algorithms or application oriented functions without requiring hardware involvement.
Each micJrO-instruction read from the Control Store Memory is placed in the 32-bit ROM Instruction Register (RIR). Most
micro-instructions are executed in one machine cycle of 240 nanoseconds. At the conclusion of each micro-instruction, the
next micro-instruction to be performed is read out and placed in the RIR. The meaning of the micro-instruction word bits
is explained later.
Locations in the Control Store Memory are addressed by the 12-bit output from the ROM Address Gate (RAG). Inputs to
the RAG may be the ROM Location Counter (RLC) to select the next micro-instruction to be performed, certain bits of
the ROM Instruction Register (RIR) for branches and transfers, the B Bus for data addressing and branches, the user level
operation code for entering an emulation routine, or the interrupt control logic for entering interrupt service routines.
Micro-instructions are normally executed from sequential Control Store Memory locations. After a micro-instruction is
read into the RIR, the RLC is loaded with the address of the next sequential micro-instruction. When it becomes necessary
to jump to a different program sequence, the first micro-instruction in that sequence is addressed through the RAG from
ROM Instruction Register (RIR) bits or B Bus bits. The new address is also loaded into the RLC so that sequential
instructions can again be executed.
05-058A15 ROJ 5/76
This information is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
Figure 1.
2
Model 8/32 Block Diagram
This information Is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for .. ny other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
During user instruction decoding, the user's operation code times two is presented to the ROM Address Gate to address the
first instruction of the sequence that emulates that user's instruction. Again, the new address is also loaded into the RLC.
Xn response to an interrupt, the interrupt control logic presents an address to the RAG. If the address is that· of a branch
and link type instruction, the hardware has time to save the current RLC value plus one in the designated link register
before the RLC is updated from the ROM Address Gate. This way, the micro-code could return to the interrupted
sequence after servicing th~ interrupt, if desired.
The execute type instructions are the only class where RLC is not updated. After executing the selected instruction, the
next micro-instruction performed is the one following the Execute instruction.
2.3 Flag Register (FLR)
The Flag Register (FLR) is a 4-bit register containing the following flags: Carry (C), Overflow (V), Greater than Zero (G),
and Less than Zero (L). These flags are modified from the Condition Code Bus at the conclusion of arithmetic and logical
operations, and I/O operations to reflect the result of the operation.
2.4 Program Status Word (PSW)
The Program Status Word (PSW) is a 32-bit register used to indicate the system status relative to the user program being
emulated. Bits 0 :27 of the PSW define enabled interrupts and the operational status or mode of the user level Processor.
Some of the PSW bits have hardware significance while others are of significance only to the emulator. Bits 28 :31 of the
PSW make up the Condition Code field (CC) which reflects the result of the last user level instruction executed. The
Condition Code may be updated from the Condition Code Bus, or when the PSW is the specified destination register. Only
Bits 14:31 of PSW are implemented.
The Location Counter (LOC) is a 32-bit appendum to PSW, holding the address in main memory of the next user
instruction to be performed. During an instruction memory read, the LOC is used to address main memory. For all other
main memory accesses, the 32-bit Memory Address Register (MAR) is used.
Only the 20 least significant bits (Bits 12 :31) of LOC and MAR are implemented.
2.S.
M~lin
Memory
Main Memory consists of a number of 128 KB (Kilo-Byte) 750 nanosecond core memory modules, providing storage for
user instructions and data. Data read from or written into memory is buffered in the 32-bit Memory Data Register (MDR).
The micro-program initiates a main memory cycle by issuing a memory read or memory write command. After issuing a
memory command, the micro-program is free to do other instructions. The memory cycle is accomplished asynchronous of
other Proce:ssor activity. If the micro-program, however, attempts to use the contents of MDR after a memory read, or
attempts to load MAR or MDR, or issue another memory command before the current memory cycle is complete, the
Processor stops until the desired function can be performed.
After an instruction read has been issued, when the read-out becomes available, Bits 0:7 are placed in the register labeled
OP, Bits 8: 11 are placed in the register labeled YD, and Bits 12: 15 are placed in the register hlbeled YS. These three
registers-OlP, YD, and YS- comprise the user's instruction register.
The OP register, containing the user's operation code, is used to address the Privileged/Illegal ROM and the Control Store
Memory itsdf. Twice the user's operation code is the Control Store Memory address of the first micro-instruction of the
appropriate emulation sequence. The Privileged/Illegal ROM is a separate Read-Only-Memory containing 256 4-bit words.
This ROM is interrogated prior to entering the micro-sequence that emulates a user-level instruction. If the op-code is
illegal, or is that of a privileged instruction and PSW Bit 23 is set, the Illegal Instruction Interrupt is generated.
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
3
2.6 General Registers
The two to eight sets of user level General Registers each contain 16 32-bit registers. The register sets (stacks) are
duplicated for the A Bus and B Bus. Refer to Figure 1. Only one set of General Registers is active at a time, dependin'
upon PSW Bits 25, 26, and 27. See Table 1.
TABLE 1. REGISTER SET SELECTION
PSW Bits
25 26 27
0
0
0
0
1
I
1
I
0
0
1
I
0
0
1
1
0
I
0
1
0
1
0
I
Active
Register Set
0
1
2
3
4
5
6
F
The micro-program usually accesses the user's General Registers without caring which of the 16 registers in the active set it
gets. However, it does matter when the micro-program accesses a General Register for emulating a user instruction, that it
be the General Register specified in that user instruction. Since after the instruction read, the register addresses specified
by the user are in the YD and YS registers, the micro-program can access the appropriate General Register by specifying
the YD or YS register. The hardware then selects the General Register whose number is in the YD or YS register.
The user's General Registers are also directly addressable to the micro-program when it is necessary to access specific
registers.
2.7 Floating-Point Registers
The 16 32-bit floating-point registers are directly addressable or indirectly addressable (through YD or YS) by the
floating-point micro-instructions.
2.8 Micro- Registers
The eight 32-bit Micro-Registers (MRO:7) are available to the micro-program as general purpose registers.
2.9 Arithmetic Logic Unit (ALU)
The 32-bit A Bus holds the first operand for arithmetic and logical operations. The 32-bit B Bus holds the second operand.
The A and B Busses are input to the Arithmetic Logic Unit (ALU). The ALU performs Addition, Subtraction, Multiplication, Division, Shifting, and Boolean connect functions. The output of the ALU is the 32-bit S Bus.
2.10 Input/Output
Input/output (I/O) operations are accomplished by gating data from the A and/or B Busses onto the 16-bit I/O Bus and
gating data from the I/O Bus onto the S Bus.
The I/O Bus consists of 33 lines; 16 bi-directional data lines, 10 control lines to identify the type of data transfer, 6 test
lines and an initialize line. See Section 6.
2.11 Interrupt Control
•
The interrupt control logic provides rapid response to internal and external events. Nine priority interrupt lines are
available each with a unique trap location in the Control Store Memory. Recognition of an interrupt causes the microinstruction at the trap location to be performed. Certain interrupts can be disabled or enabled by bits of the Program
Status Word (PSW). Interrupts can also be disabled or enabled as a group by the micro-program. See Table 2.
4
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpoSa unless specifically authorized in writing.
05-058A15 ROI 5/76
TABLE 2. INTERRUPT TRAPS
TRAP ADRS
(HEX)
INTERRUPT
Memory Access Controller (Instruction)
Memory Access Con troller (Data)
Primary Power Fail
Machine Malfunction
Display Panel
External Interrupt Level 0
External Interrupt Levell
External Interrupt Level 2
External Interrupt Level 3
Illegal Instruction
Privileged Instruction
IFE
207
206
205
204
203
202
201
200
208
208
GRO
ENAB.
MASK
PSW2l
NO
NONE
PSW18
NONE
YES
YES
YES
see
table
3
YES
NONE
PSW23
N/A
N/A
PSW Bits 17 and 20 define the external Interrupt enable status of the Processor as shown below:
PSW
17
0
0
1
1
BITS
20
0
1
0
1
All Levels Disabled
Higher Levels Enabled
All Levels Enabled
Current and Higher Levels Enabled
where the current level is a function of the currently active register set. See Table 3.
TABLE 3. EXTERNAL INTERRUPT ENABLE
PSW BITS
EXTERNAL INTERRUPT ENABLED
17 20
25
26
27
0
0
X
0
0
0
0
1
1
1
1
X
0
0
1
I
0
0
1
1
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
I
0
1
1
I
1
1
1
1
1
0
1
I
1
1
1
1
X
0
X
0
X
0
0
0
0
1
1
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
. LEVEL 0
. LEVEL 1
. LEVEL 2
. LEVEL 3
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
YES
0
1
0
YES
YES
YES
YES
YES
1
YE~
NO
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
YES
YES
YES
YES
YES
2.12 Machine Control Register (MCR)
The 12-bit Machine Control Register (MCR) can be interrogated or cleared by the micro-program. The meaning of the
MCR bits is shown in Table 4.
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTER DATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
5
TABLE 4. MCR BIT DEFINITION
BIT
MNEMONIC
15
14
13
12
EPE
MM
MM
Unused
STF
CATN
RSET
Spare
SNGL
INIT
HWCRC
DFU
11
10
09
08
07
06
05
04
I
3.
MEANING
Early Power Fail Detect
}
Memory Malfunction (Parity Error)
Start Timer Failure
Console Attention
Register Sets Available
Spare (Strap)
Console Single Mode
Initialize Switch on console
Hardware Assist CRC option
DFU option
DATA AND INSTRUCTION FORMATS
3.1 Data Formats
All internal data paths except those to the Input/Output control are 32-bits wide. The basic machine operand is consequently a 32-bit fullword. Positive fixed-point data is expressed in true binary form with a Sign bit of zero. Negative
fixed-point data is expressed in two's complement notation with a Sign bit of one. Floating-point data is expressed as a
signed magnitude fraction with a signed exponent. The quantity expressed is the product of the fraction and 16 raised to
the power of the exponent. Each floating-point number requires a 32-bit full word; 8-bits are used for the fraction sign and
exponent, and 24-bits are used for the fraction.
Binary infonnation is represented in hexadecimal notation (base 16) for simplicity.
3.2 Instruction Formats
Model 8/32 micro-instmctions can be one of six formats designated Address Link, Register Link, Register to Register
Transfer, Register to Register Control, Register to Register Immediate, and Register Write. The instruction formats are
shown in Figure 2.
ADDRESS LINK
I
o
234 5 6
0 01 1 1 XITI
0
13 14
S
F
1
ADDRESS
MC
REGISTER BRANCH
I~
0
~1~1~liI6 NULL 10 111
MC
REGISTER TO REGISTER TRANSFER
A
15 16
1
F
19 20
1
B
2412~126
31
PAGE ADDRESS
REGISTER TO REGISTER CONTROL
~0_____2~3~14~1~5~6_______10~II_l___A___1_5~1_16___F____19~1_2_0__B___24_1~~_5~12_:~I~~_7~12_8_______M_C________~
REGISTER TO REGISTER IMMEDIATE
02345 6
DATA
REGISTER WRITE
I~
0
~1~11~r NULL.~1_0_11_1~_A~_15~1~1_6~F~_1_9~12_0~_B~24~1~~_I~~_61~~_7~12_8~~~M_C~~~~3~11
Figure 2. Instruction Word Formats
6
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROI 5/76
The basic. instruction format provides the micro-processor with a three address capability, but various options of the
repertoire can modify their range from two to four.
Bits 0, 1, and 2 of the micro-instruction, select the Processor module that will perform the specified function. The Address
Link and Register Link micro-instructions are the only ones that select Module 0, the control module. The other micro
instruction formats can be directed to any other module. The Model 8/32 Micro Code Assembler recognizes symbolic
operation codes directed to Modules 0 (the control module), 1 (the ALU module), 2 (the I/O module), and 3 (the
floating-point ALU module).
The meaning of the micro-instruction word fields is summarized in Table 5 and the following paragraphs.
TABLE 5. INSTRUCTION WORD FIELDS
FIELD
A
B
C
D
E
F
I
K
MC
S
T
X
MEANING
Selects Register to be used as first operand.
Selects Register to be used as second operand.
If set, transfer is conditional.
Decode next user instruction.
Enable setting of Condition Code.
Specifies function of addressed module.
B Bus data addresses actual data in Control Store.
F field extention.
Memory Control field.
Selects register to receive the result.
If set, item F must be true for transfer.
Execute
The F field in all formats specifies the function that the selected module is to perform. The X-bit in the Address Link and
Register Link formats distinguishes Execute and Link instructions from Branch and Link instructions. The T-bit specifies
whether the true or false state of the condition F is to be tested.
The S field selects the S Bus register to be loaded. The A field selects the first operand (A Bus) register. The B field selects
the second operand (B Bus) register.
Setting the I-bit causes the operand developed on the B Bus to be taken as a Control Store Memory address. The fullword
contents of the addressed location replaces the original B Bus data.
Setting the C-bit on Register to Register Transfer instructions makes the transfer occur only if no predefined signal is
returned from the addressed module. For the ALU module, the signal is carry, meaning no transfer occurs if a carry is
generated.
The K-bit is used as an extension of the F field, allowing more than 16 functions to be performed by the addressed
module.
The E-bit allows the Condition Code (CC) field to be updated from data on the CC Bus from the addressed module. Once
an instruction with the E-bit set has been performed, the Condition Code remains connected to the CC Bus until an
instruction with the E-bit reset is fetched.
The D-bit enables the Privileged/Illegal ROM and the instruction decoding hardware. Unless a branch is taken or an
interrupt occurs, a user instruction emulation sequence is entered.
The MC fiield controls main memory accesses, and MAR and LOC activities.
The most significant bit of the l2-bit immediate field on Register to Register Immediate instructions is propagated as the
most significant 20-bits on the B Bus. For example, the immediate operand '400' produces the value '00000400' on the B
Bus. The immediate operand '800' produces the value' FFFFF800' on the B Bus.
The 6-bit Address field on Register to Register Transfer instructions can specify any address within the local 64 word page.
For example, an instruction at address' 131 ' can transfer to any other instruction from address' 100' to '13F'.
3.2.1 Address Link. On the Address Link instructions, the incremented contents of the RLC are placed in the
selected :s Bus register. Then, if the condition specified by F and T is met, the next micro-instruction executed is the one at
the location specified by the l2-bit ADDRESS field. If not, the next micro-instruction in sequence is executed. In
addition, if the condition is met, any memory control or decode options specified are suppressed.
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
7
3.2.2 Register Branch. The Register Branch instructions are identical to the Address Link instructions except
the address to transfer to is taken from the register specified by B. The destination register must be specified as NULL.
3.2.3 Register to Register Transfer. These instructions perform function F using the contents of the register
specified by A as the first operand and an effective second operand specified by B. The result replaces the register specified
by S. Then, if the C-bit is reset, or if a special signal is not returned from the addressed module, the next micro-instruction
executed is from the Cpntrol Store Memory address specified by the PAGE ADDRESS field on the current page. If the
C-bit is set and the special signal is returned from the addressed module, the next micro-instruction in sequence is
executed. The PAGE ADDRESS field can only specify the least significant 6-bits of a Control Store Memory address. The
remaining address bits are taken from the high order 6-bits of RLC. This means that a transfer can only occur to a location
within the 64 word page defined by RLC Bits 4: 9. An exception is when the micro-instruction is at the end of a page
boundary (e.g., address '23F'). In this instance, the transfer occurs to the specified address on the next sequential page
(e.g., addresses '240' through '27F').
The effective second operand, BE, is the contents of the register specified by B if I =
o.
or the contents of the full word Control Store Memory location whose address is in the register specified by B if 1= 1.
3.2.4 Register to Register Control. These instructions perform function F using the contents of the register
specified by A as the first operand and an effective second operand specified by B. The result replaces the contents of the
register specified by S.
The effective second operand, BE, is the contents of the register specified by B if I
= 0:
or the contents of the fullword Control Store Memory location whose address is in the register specified by B if I
= I:
At the conclusion of the instruction, any specified MC or D options are peIformed.
3.2.5 Register to Register Immediate. The function specified by F is performed using the contents of the
register specified by A as the first operand and an effective second operand specified by the DATA field. The result
replaces the contents of the register specified by S.
The effective second operand, BE, is the 12-bit value of the DATA field with the most significant 20 bits equal to Bit 20 if
1=0:
or the contents of the full word Control Store Memory location whose address is DATA if I = I:
BE = [DATA]
3.2.6 Register Write. The Register Write instruction stores the contents of the register specified by A into the
Dynamic Control Store (DCS) location whose address is in the register specified by B. After the write, any specified MC or
D options are performed.
If the Processor is not equipped with DCS, only the MC or D options are performed.
3.3 Main Memory Control
The Processor's main memory is the source of user's instructions and data. Control over the main memory is provided in
the MC field of the Address Link, Register Link, Register to Register Control, and Register Write micro-instructions.
Table 6 and the following paragraphs describe the MC field options.
8
This information is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specificelly authorized in writing.
05-058A15 ROO 5/75
TABLE 6. MCFIELD
BITS
MEANING
28
29
30
31
0
0
0
0
0
0
0
0
I
1
1
0
0
0
0
1
1
1
1
0
0
0
0
I
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
I
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
I
0
I
0
1
No Action
IL
PW2
DW2
No Action
I4DW4
PW4
DW4
RAS
ILIR
PR2
DR2
IR
14DR4
PR4
DR4
Increment LaC by Instruction Length
Privitleged Write Halfword (two bytes
Data Write Halfword
Increment MAR by 4, Data Write Full word
Privileged Write Fullword
Data Write Fullword
Read Halfword and Set Sign Bit
Increment LaC by Length and Read IIlstruction
Privileged Read Halfword
Data Read Halfword
Instruction Read
Increment MAR by 4, Data Read Full word
Privileged Read Fullword
Data Read Fullword
IL
The Location Counter (LaC) is incremented by the length in bytes of the last user level instruction fetched.
PW2
The Memory Access Controller (MAC) is disabled and the halfword in MDR, Bits 16:31., is written into the
addressed location.
DW2
The halfword in MDR, Bits 16:31, is written into the addressed location. MAC is not disabled.
14DW4
The Memory Address Register (MAR) is incremented by four. Then the fullword in MDR, Bits 0 :31, is written
into the location addressed by MAR.
PW4
The MAC is disabled and the fullword in MDR, Bits 0:31, is written into the addressed location.
DW4
The fullword in MDR, Bits 0:31, is written into the addressed location.
RAS
The halfword at the addressed location is read then re-written with Bit 0 of the halfword set. The original value
of the halfword replaces MDR Bits 16:31. Bits 0:15 of the MDRare set equal to Bit 16 ofMDR (sign extension).
ILIR
LaC is incremented by the length in bytes of the last user instruction fetched. Then an Instruction Read is
started from the address specified by the new value of LaC.
PR2
The MAC is disabled and the halfword at the addressed location is read and copied to MDR Bits 16 :31. Bits 0: 15
of MDR are set equal to MDR Bit 16.
DR2
The halfword at the addressed location is read and copied to MD R Bits 16: 31. Bits 0: 15 of MD R are set equal to
MDR Bit 16.
IR
An Instruction Read is started from the memory address specified by LOe.
14DR4
:MAR is incremented by four. Then the fullword at the location addressed by the new value of MAR is read and
copied to MDR.
PR4
MAC is disabled. Then the fullword at the location addressed by MAR is read and copied to MDR.
DR4
The full word at the location addressed by MAR is read and copied to MDR.
05-058A15 ROO 5/75
This information is propriatary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
All Main Memory Control is conditional when used within Address Link and Register Branch micro-instructions. The
control is only affected if the instruction does not result in a transfer.
All increment functions are done before the micro-instruction terminates. Memory read and write functions do not start
until after the micro-instruction terminates. This allows the micro-program to use MAR or MDR as a destination and then
begin a memory read or write in the same micro-instruction.
4.
SOURCE AND DESTINATION REGISTERS
The Model 8/32 has 93 registers that are addressable by the micro-program. Most of these are available to the A, Band S
Busses. Table 7 and the following paragraphs explain the exceptions and special cases.
TABLE 7. REGISTER ADDRESSES
HEX
ADDRESS
SBUS
ABUS
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
11
11
11
12
13
14
15
12
13
14
15
12
13
14
15
10
MRO
MRI
MR2
MR3
MR4
MRS
MR6
MR7
YS
YD
LOC
MDR
MAR
PSW
YDI
NULL
MRO
MRI
MR2
MR3
MR4
MRS
MR6
MR7
YS
YD
YX
YDPI
MRO
MRI
MR2
MR3
MR4
MRS
MR6
MR7
11
12
13
14
15
16
17
18
19
lA
IB
lC
1D
IE
IF
PSW
NULL
BBUS
0
1
2
3
4
5
6
7
8
9
10
YS
YD
LOC
MDR
MAR
YSI
YDI
NULL
CATEGORY
USER'S
GENERAL
REGISTERS
MICRO
REGISTERS
SPECIAL
PURPOSE
Although the user's General Registers in the register set specified by PSW Bits 25, 26 and 27 can be addressed directly by
the micro-program, it is often more convenient to access the General Register specified in the user's instruction without
regard to its physical number. The symbolic addresses YD, YDP1, YS, and YX allow just that. Specifying YD causes the
General Register whose number appears in the YD field of IR (lR Bits 8: 11) to be selected. Specifying YDP1 causes the
odd member of the even-odd pair of General Registers, one of whose number appears in the YD field of IR, to be selected.
Specifying YS causes the General Register whose number appears in the YS field of IR (lR Bits 12:15) to be selected.
Specifying YX is the same as specifying YS except when the YS field of IR is zero. Then, all zeros are placed on the A Bus.
This automatic feature is used to develop the index value for the user level RIl, RI2, and RX format instructions.
On micro-instructions that address the Floating-Point Module, the corresponding floating-point register is selected instead
of a General Register.
10
This information i. proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
Specifying YDI or YSI as a source causes the corresponding field of IR - YD or YS - to be placed on Bits 28 :31 of the B
Bus. The upper 28-bits of the B Bus are zero.
Specifying; NULL as a source on the A or B Bus causes the corresponding bus to be set to zero. Specifying NULL as the S
Bus destination causes the data to be lost.
Specifying; MDR as a source after a memory read operation causes the Processor to wait until the memory data becomes
available. Following an Instruction Read and Decode function, MDR participates in the formation of the effective address,
if the user's instruction is one of the RX formats. Specifically, until MAR is loaded, any reference to MDR as a source
causes the second level index register (SX2) to be accessed if the instruction format is RX3. Otherwise, MDR is accessed.
Refer to Section 7 for details.
Specifying LaC, MAR, or MDR as a destination when a memory access is in progress causes the Processor to wait until the
memory access is completed.
I
Specifying MAR as a source, produces meaningful results on the B Bus only after an Instruction Read and Decode
function. Referring to the block diagram on Figure 1, when MAR is specified as the source, the output of the 20-bit adder
is presented to the B Bus instead of MAR. This output is the actual contents of MAR, or the sum of MAR and LaC, or the
sum of MAR and MDR, depending upon the format of the last user Instruction read. Refer to Section 7 for details.
/
The Condition Code field of PSW can be manipulated by any addressed module unless PSW is the explicit destination or a
Condition Code change was inhibited by the E-bit in a micro-instruction.
The bits of PSW that have hardware implications are:
PSWl7
PSWl8
PSW20
PSW21
PSW23
PSW25,26,27
PSW28:31
5.
Interrupt priority selection (see Table 3.)
Machine Malfunction interrupt enable
Interrupt priority selection (see Table 3.)
Relocation/Protection interrupt enable
Protect mode
Register Set Selection
Condition Code
INSTRUCTION REPERTOIRE
5.1 Introduction
The inst11lction repertoire has been grouped by function in this section. The operation of each instruction is presented in
the following format.
1.
An instruction word chart for each instruction including mnemonic operation code and operand designations in the
correct Assembler format. The format type and an instruction diagram with operation code and the location of all
fields is also provided.
2.
A description of instruction operation.
3.
A diagrammatiC representation of instruction operation.
4.
A chart showing the possible resultant flags.
5.
Thle execution time in nanoseconds. On all microinstructions, add 180 nanoseconds if I = 1.
6.
A programming note may be provided to add pertinen·t or clarifying information.
The symbols and abbreviations used in the instruction descriptions are defined as follows:
()
Parenthesis or brackets. Read as "the content of-;-."
[ ]
0lil---
A
B
S
(0:7)
Anrow. Read as "is replaced by -" or "replaces-"
The A field. First operand register specification.
The B field. Second operand register specification.
The S field. Destination register specification.
A bit grouping within a word. Read as "Bits 0 through 7 inclusive", etc.
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining I NTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
III
The effective second operand. If the instruction format is RR Control or RR Transfer, the effective second operand
is the contents of the register specified by B if the Indirect (I) bit is reset:
BE
BE = (B) ifl=O
If the Indirect bit is set, the effective second operand is the content of the fullword Control Store location whose
address is contained in the register specified by B:
BE=[(B)] if 1=1
If the instruction format is RR Immediate, the effective second operand is the 12-bit data field if the Indirect bit is
reset:
If the Indirect bit is set, the effective second operand is the contents of the full word Control Store location whose
address is the Data field:
BE=(DATA) if 1=1
12
This information is proprietary and i. supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
5.2 Logical Instructions
The instmctions described in this section are:
5.2.1
L
LX
LI
Load
Load and Transfer
Load Immediate
5.2.2
STR
Store
5.2.3
N
NX
NI
AND
AND and Transfer
AND Immediate
5.2.4
0
OX
01
OR
OR and Transfer
OR Immediate
5.2.5
X
XX
XI
Exclusive OR
Exclusive OR and Transfer
Exclusive OR Immediate
5.2.1 Load
S,B,I,E,D,MC
L
i
0
3
[RR CONTROL]
ill
5 6
Elo 111 I
I
11111
S
,1 0
25
20
16
I
o0
0
3
LI
11
II
S
16
1 1 1
I
o0
3
0
1
I
PAGE ADDRESS
B
[RR IMMEDIATE]
11
5 6
~itl okl
31
20
S,DATA,I
o
MC
[RR TRANSFER]
5 6
~lloolII
31
28
B
S,B,ADRS,I,C
LX
26 27
II
S
16
1 1 11000
31
20
I
DATA
The secoll1d operand is loaded into the register specified by S.
L,LI
LX
(S) ... BE
(S) ... BE
then (RLC 10: 15) ... PAGE ADDRESS
Resulting Flags
C VG L
0 000 Result is zero
0 001 Result is less than zero
o 0 1 0 Result is greater than zero
Programming Note
The Load instruction assembles as an Add instruction with a NULL A field.
Execution Times
L,LI,LX:
05-058A15 ROO 5/75
240
This information is proprietary and il supplied by INTEADATA for the sole
purpose of using and maintaining INTEADATA supplied equipment and shall
not be used for any other purpoSe unless specifically authorized in writing.
13
5.2.2 Store
STR
0
o0
[R WRITE]
A,B,E,D,MC
3
11
5 6
I11 IIII
1 1 1 1
I
16
10 000
A
25 26 27
20
I
28
31
MC
B
The content of the register specified by A is stored in the Control Store Memory location whose address is in the register
specified by B.
(A) .. [(B)]
STR:
Execution Time
STR:
420
5.2.3 AND
0
0 0
NX
0
•
[RR CONTROL]
S,A,B,I,E,D,MC
N
o0
3
5 6
16
11
II 0II ,I
I
S
A
I
25
20
I
0 1 0
B
0
o0
0 lEI
3
5 6
16
11
do 01, I
3
I
s
MC
20
o1
A
25
B
0
31
26
Ie I
I
PAGE ADDRESS
[RR IMMEDIATE]
5 6
III 0I, I
DI
[RR TRANSFER]
S,A,B,ADRS,I,C
S,A,DATA,I
NI
1
31
26 27 28
16
11
I
S
A
Io
31
20
1
o
1
I
I
DATA
The logical product of the first and second operand replaces the contents of the register specified by S. The 32-bit product
is formed on a bit-by-bit basis.
N, NI
NX
(S) ... (A) AND BE
(S) • (A) AND BE
Then (RLClO:15)'" PAGE ADDRESS
Resulting Flags
CV GL
o0 o0
o0 oI
o0 1 0
Product is zero
JProduct is not zero
Execution Times
N,NI,NX : 240
14
This information is proprietary end is supplied by INTERDATA for the lole
purpose of using and meintaining I NTER DATA supplied equipment and shall
not be used for any other purpose unle.. spacifically authorized in writing.
05-058A15 ROI 5/76
5.2.4 OR
0
S,A,B,I,E,D,MC
0
3
8
0
OX
5 6
II
I
3
8
0
01
S,A,DATA,I
8
11
I
S
16
A
Io
20
1 1 1
I
25
B
10
26 27 28
IE I I
S,A,B,ADRS,I,C
0
0
[RR CONTROL]
3
10
1
11
S
1
1
16
A
1
o1
1
20
1 1
I
25 26
B
Ie I
31
I
PAGE ADDRESS
[RR IMMEDIATE]
5 6
1
I
Me
[RR TRANSFlER]
5 6
oI I
D
31
11
I
S
16
A
I
0 1 I 1
20
1
31
DATA
1
The logical sum of the first and second operands replaces the contents of the register specified by S. The 32-bit sum is
formed on a bit-by-bit basis.
0,01
OX
(S) .. (A) OR BE
(S) .. (A) OR BE
then (RLClO:15)" PAGE ADDRESS
Resulting Flags
CV GL
o0 o0
o0 o 1
o0 1 0
Sum is zero
1
Sum:is not zero
Execution Times
O,OI,OX : 240
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining I NTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
15
5.2.5 Exclusive OR
S,A,B,I,E,D,MC
X
0
o0
XX
0
o0
XI
3
[RR CONTROL]
5 6
10 11 I I
11
S
16
A
20
Io 1 1 0
I
25 26
B
1 0 1
11
S
16
A
I0
20
1 1 0
25
00
3
111
B
1
Ie
1
II
31
PAGE ADDRESS
I
[RR IMMEDIATE]
5 6
0 I
I
MC
26
S,A,DATA,I
0
31
[RR TRANSFER]
5 6
dO+1
28
EI DI
S,A,B,ADRS,I,C
3
27
11
S
16
A
I
20
0 1 1 0 1
31
DATA
1
The logical difference between the first and second operands replaces the contents of the register specified by S. The 32-bit
difference is formed on a bit-by-bit basis.
X, XI
XX
(S).. (A) XOR BE
(S) .. (A) XOR BE
then (RLClO:15)" PAGE ADDRESS
Resulting Flags
CV GL
o0 o0
o0 o1
o0 1 0
Difference is zero
J Difference is not zero
Execution Times
X, Xf, XX
16
: 240
This information is proprietary and is supplied by INTERDATA for the IDle
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any Other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
5.3 Branch/Execute and Link Instructions
These instructions are programmed decisions providing entry to and return from subprograms, as well as testing the results
of arithmetic, logical, and other machine operations.
Most Processor operations result in setting the micro-flag register. The state of this flag register is testable with the
Branch/Execute and Link on condition instructions.
The Execute and Link instructions allow conditional execution of a single, non-sequential micro-instruction. No branch is
actually taken, and unless the instruction executed is a Branch instruction or otherwise results in a transfer, control returns
to the instruction following the Execute and Link.
The address plus 1 of the Branch/Execute and Link instruction is always saved in the specified link register, even if the
condition for doi;ng the Branch of Execute is not met.
The instmctions described in this section are:
5.3.1
BAL
BALA
BALD
BALZ
BALNZ
BALL
BALNL
BALG
BALNG
BALV
BALNV
BALC
BALNC
BALT
BALF
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
Branch and
5.3.2
EXL
EXLA
EXLD
EXLZ
EXLNZ
EXLL
EXLNL
EXLG
EXLNG
EX LV
EXLNV
EXLC
EXLNC
EXLT
EXLF
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
Execute and
05-058A15 ROO 5/75
Link
Link and Arm interrupts
Link and Disarm interrupts
Link on Zero
Link on Not Zero
Link on Less
Link on Not Less
Link on Greater
Link on Not Greater
Link on Overflow
Link on No Overflow
Link on Carry
Link on No Carry
Link on True CC Match
Link on False CC Match
Link
Link and Arm interrupts
Link and Disarm interrupts
Link on Zero
Link on Not Zero
Link on Less
Link on Not Less
Link on Greater
Link on Not Greater
Link on Overflow
Link on No Overflow
Link on Carry
Link on No Carry
Link on True CC Match
Link on False CC Match
This information is proprietary and i. supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
17
5.3.1 Branch and Link
[ADDRESS LINK]
ADDRESS (LINK),E,D,MC
F
o
,MC
ADDRESS
F
LINK
(B)(NULL),E,D,MC
F
o
3
[REGISTER LINK]
11
5 6
14
000
20
F
where F =
BALZ
BALL
BALG
BALF
BALC
BALV
BAL
BALA
BALNZ
BALNL
BALNG
BALT
BALNC
BALNV
BALD
0
0
0
0
0
0
0
0
I
I
1
I
I
1
1
25 26 27
B
1
T
31
26 27 28
14
11
356
28
31
MC
F
0
0
0
0
0
0
1
I
I
1
I
0
0
I
I
0
0 I
1 0
1 1
0 0
0 1
1 1
I
0
0
0
0
1
1
I
0
1
0
1
0
I
0
1
0
The address of the next sequential micro-instruction replaces the contents of the register specified by LINK, then a transfer
is conditionally taken to the address specified. In the Address Link format, the ADDRESS field of the instruction contains
the branch address. In the Register Link format, the branch address is contained in the register specified by B. This format
is used to return from subroutines.
Tested Condition True
(LINK)" (RLC4:15)+1
(RLC4:15) .. ADDRESS
(RLC4:15). (B)
[Address Link]
[Register Link]
Tested Condition False
(LINK). (RLC4:15)+1
( RLC 4:15)· ( RLC4:15)+1
Programming Notes
For the BALT and BALF instructions, a logical AND is performed between each bit in the Condition Code
field of PSW and the MI field of the user's instruction (IR8:11)' If any resultant bit is a ONE, the BALT
instruction will branch and the BALF instruction will not. If all resultant bits are ZERO, the BALF instruction will branch and the BALT instruction will not.
If any Memory Control function is specified in the MC field, the function is performed only if the branch is
not taken. Similarly, if the Decode bit is set, the Decode function only occurs if no branch is taken.
The BALA and BALD instructions are used respectively to Arm and Disarm the interrupt system.
Execution Time
240 nanoseconds
18
This information is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining I NTER DATA supplied equipment and shall
not ba used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
S.3.2-Execute And Link
ADDRESS. (LINK),E,D,MC
F
a
3
5 6
~oo _ll~ll~T~I L_IN_K~I
__
11
___F
__
[ADDRESS LINK]
~I
14
26 27 28
_____A_D_D__
RE_S_S____
~1~E~ID
__
I __
(B)(NULL),E,D,MC
F
a
3
5 6
11
EXLZ
EXLL
EXLG
EXLF
EXLC
EXLV
EXL
EX LA
EXLNZ
EXLNL
EXLNG
EXLT
EXLNC
EXLNV
EXLD
14
T
F
a
a
a
a
a
a
a
a
1
1
1
1
1
1
1
000
001
010
all
100
101
110
111
000
001
010
all
100
101
111
MC
[REGISTER LINK]
20
25
31
26 27 28
Goo .L. -.-.1-IloI~T
I _NULL_L--I_ F--L...~~''-.L.-_B~~~E
I D L--I
where F =
31
MC
The addre:ss of the next sequential micro-instruction replaces the contents of the register specified by LINK, then if the
condition is met, the instruction at the specified address is executed. Any instruction may be executed including other
Execute instructions. When the executed instruction is completed, the Processor continues with the micro-instruction
following the Execute and Link.
Tested Condition True
(LINK)" ( RLC4: I 5)+ 1
Do instruction at ADDRESS
Do instruction at (B)
( RLC 4: 15)" ( RLC 4: 15)+1
[Address Link]
[Register Link]
Tested Condition False
(LINK) .. (RLC4: 15)+ 1
( RLC 4:15)" ( RLC 4:15)+1
Programming Note
See Branch and Link
Execution Time
240 nanoseconds plus executed instruction
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
19
5.4 Shift/Rotate Instructions
The Shift and Rotate instructions provide for arithmetic and logical manipulation of information contained in tl -::
Processor registers. Bits shifted out of the high or low end of a register are passed through the Carry flag (C). After a shift
instruction, the last bit which was shifted out is contained in the Carry flag.
A shift of zero positions causes the G and L flags to be set properly with no alteration to the data contained in the register.
The Carry and Overflow flags are reset.
The instructions described in this section are:
5.4.1
SLL
·SLLX
SLLI
5.4.2
SLHL
Shift Left Halfword Logical
5.4.3
SRL
SRLX
SRLI
Shift Right Logical
Shift Right Logical and Transfer
Shift Right Logical Immediate
5.4.4
SRHL
Shift Right Halfword Logical
5.4.5
SLA
SLAX
SLAI
Shift Left Arithmetic
Shift Left Arithmetic and Transfer
Shift Left Arithmetic Immediate
5.4.6
SLHA
Shift Left Halfword Arithmetic
5.4.7
SRA
SRAX
SRAI
Shift Right Arithmetic
Shift Right Arithmetic and Transfer
Shift Right Arithmetic Immediate
5.4.8
SRHA
Shift Right Halfword Arithmetic
5.4.9
RR
RRX
RRI
Rota te Right
Rotate Right and Transfer
Rotate Right Immediate
5.4.10 RL
RLX
RLI
20
Shift Left Logical
Shift Left Logical and Transfer
Shift Left Logical Immediate
Rotate Left
Rotate Left and Transfer
Rotate Left Immediate
This information is proprietary and i. supplied bV INTERDATA for the lole
purpose of using and maintaining INTERDATA $upplied equipment and shall
not be used for any other purpose unless speciiically authorized in writing.
05-058A15 ROO 5/75
SAll.' Shift Left Logical
SLL
[RR CONTROL]
S,A,B,I,E,D,MC
11
I
s
SLLX.
16
A
I
100 1
I
MC
B
. S,A,B,ADRS,I,C
[RR TRANSFER]
11
I
S
SLLI.
31
20
1001
A
I
31
25 26
20
B
Ie I
I
PAGE ADDRESS
[RR IMMEDIATE]
S,A,DATA,I
II
I
S
31
16
A
I
1001
DATA
The contents of the register specified by A are shifted left the number of bit positions specified by the least significant 5
bits of the second operand. The result replaces the con tents of the register specified by S.
High order bits shifted out of Position 0 are shifted through the Carry flag, then lost. Zeros shift into the low order bit
position.
L
SLL,SLLI: (S) ....(A)
BE(27:31)
L
(S)....--(A)
BE(27:31)
then (RLC1O:15). PAGE ADDRESS if C = 0 or Carry = 0
(RLC4: 15). ( RLC4: 15)+1 if C = 1 and Carry = 1
SLLX
ReSUlting flags
CV GL
000
0 o 1
0 1 0
0
1
Result is zero
Result is less than zero
Result is greater than zero
Last bit shifted out was a zero
Last bit shifted out was a one
Execution Times (n = number of shifts)
. SLL,SLLI
:360+60n
SLLX (No transfer) :500+60n
SLLX (Transfer)
:360+60n
OS-058A15 ROO 5/75
This information is proprietary and is supplied by 'INTERDATA for the sole
purpose of using and maintaining I NTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
21
$.4.2 Shift Left Halfword Logical
S,A,B,I,E,D,MC
SLtIL
o
3
5 6
00
[RR CONTROL]
11
S
16
I
A
20
100 1
I
25
26 27
B
28
31
MC
The least significant 16-bits of the register specified by A are shifted left the number of bit positions specified by the least
significant 4-bits of the second operand. The result replaces the least significant 16-bits of the register specified by S. The
most significant 16-bits of the register specified by A replace the most significant 16-bits of the register specified by S. Bits
shifted out of Position 16 are shifted.through the Carry flag, then lost. Zeros shift into the low order bit position .
. SLHL:
(SO:15)
oil.
(AO:15)
(S16:31)·~(A16:31)
BE(28:31)
Resulting flags
CV GL
000
001
010
0
1
Halfword result is zero
Halfword result is less than zero
Halfword result is greater than zero
Last bit shifted out of bit-16 was a zero
Last bit shifted out of bit-16 was a one
Execution Times (n = number of shifts)
SLHL: 360+60n
22
This information il proprietary and is supplied by INTER DATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be uled for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
5.4:3 -Shift Right LoSical
BRL
0
3
SRLX
3
A
I
I
1000
I
B
10
"SRLI
11
I
S
II
E
D
16
A
I
20
1000
I
25
5
10
I
MC
B
Ic I
31
I
PAGE ADDRESS
[RR IMMEDIATE]
6
II I
I
26
S,A,DATA,I
3
31
26 27 28
25
20
[RR TRANSFER]
5 6
op I
~I
S
16
S,A,B,ADRS,I,C
8t i I
0
11
5 6
EIOI II I
0
[RR CONTROL]
S,A,B,I,E,D,MC
11
I
S
16
A
I
20
1000
I
31
I
DATA
The contents of the register specified by A are shifted right the number of bit positions specified by Bits 27: 31 of the
second operand. Low order bits shifted out of Position 31 are shifted through the Carry flag and then lost. Zeros shift into
, PositionO.
R
SRL,SRLI:
(S).
(A)
BE(27:31)
R
SRLX
(S) •
(A)
BE(27:31)
then (RLClO:1 5). PAGE ADDRESS if C=O or Carry=O
(RLC4:15). (RLC4:15)+1 ifC=1 and Carry=1
Resulting flags
CV GL
000
001
0 1 0
0
1
Result is zero
Result is less than zero
Resul t is greater than zero
Last bit shifted out was a zero
Last bit shifted out was a one
Execution Times
SRL,SRLI
SRLX (No transfer)
SRLX (Transfer)
05-058A15 ROO 5/75
(n = number of shifts)
360+60n
500+60n'
360+60n
This information is proprietary and ia supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment end shall
not be used for any other purpose unless specifically authorized in writing.
23
5.4:4 Shift
SRHL
0
Ri~ht
Halfword Lo&!cal
S,A,B,I,E,D,MC
3
5 6
tOOl 1011
I
I
[RR CONTROL]
16
11
S
I
A
I
20
1000
I
B
(15 (: (: (8
31
MC
I
The least significant 16-bits of the register specified by A are shifted right the number of bit positions specified by the least
significant 4-bits of the second operand. The result replaces the least significant 16-bits of the register specified by S. The
most significant 16-bits of the register specified by A replace the most significant 16-bits of the register specified by S. Bits
shifted out of Position 31 are shifted through the Carry flag, then lost. Zeros shift into Position 16.
SRHL : (SO:15)~ (AO:15)
(SI6:31)..
R
(AI6:31)
BE(28:31)
Resulting flags
CV GL
000
001
010
0
1
Halfword result is zero
Halfword result is less than zero
Halfword result is greater than zero
Last bit shifted out was a zero
Last bit shifted out was a one
Execution Times (n = number of shifts)
SRHL: 360+60n
24
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
5.4.5 Shift Left Arithmetic
SLA
S,A,B,I,E,D,MC
,0
3
5 6
~~I ~
1 F1
01
SLAX
11
S _
_
16
20
~~~
I
I
1
1 10 1
A
25 26,27
B_
_
3
Go
10 0 1I I
SLAI
I
S
16
,3
1'
110
A
I
1 1 01
I
31
PAGE ADDRESS
B
[RR IMMEDIATE]
5 6
I
S
I
A
I
31
20
Hi
11
I1
I
Me
25 26
20
S,A,DATA,I
0
31
[RR TRANSFER]
11
5 6
28
~'OI~E_D~1
S,A,B,ADRS,I,C
0
Go
[RR CONTROL]
1 10 1
I
DATA
, The contents of the register specified by A are shifted left the number of bit positions specified by the least significant
5-bits of the second operand. Only Bits 1: 31 participate in the shift, Bit 0 remains unchanged. High order bits shifted out
of Position 1 are shifted through the Carry' flag; then lost. Zeros shift into the low order bit position.
SLA,SLAI
: (SO)- (AO)
(Sl:31). L
(A1:31)
BE(27:31)
SLAX
(SO)4-(AO)
(Sl :31)..--!:- (AI :30
BE(27:31)
then (RLC10:15) ... PAGE ADDRESS if C=O or Carry=O
(RLC4: 15) .... (RLC4: 15)+ if C=l and Carry=l
Resulting flags
C VGL
000
001
0 1 0
0
1
Result is zero
Result is less than zero
Result its greater than zero
Last bit shifted out was a zero
Last bit shifted out was a one
Execution Times (n = number of shifts)
SLA,SLAI
: 360+60n
SLAX (No transfer) : 500+60n
SLAX (Transfer)
: 360+60n
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing,
25
5.4.6 Shift Left Halfword Arithmetic
S,A,B,I,E,D,MC
SLHA
o
3
5 6
001
[RR CONTROL]
11
S
16
A
20
110 1
25 26 27
B
28
31
Me
The least significant IS-bits of the register specified by A are shifted left the number of bit positions specified by the least
significant 4-bits of the second operand. The result replaces the least significant IS-bits of the register specified by S. The
most significant 17-bits of the register specified by A replace the most significant 17-bits of the register specified by S. Bits
shifted out of Position 17 are shifted through the Carry flag, then lost. Zeros shift into Position 31.
SLHA : (SO:I6)-(Ao:16)
(SI7:31)" L
BE(28:31)
(AI7:3})
Resulting flags
CV GL
000 Halfword Result is zero
001 Halfword Result is less than zero
0
I
010 Halfword Result is greater than zero
Last bit shifted out of Position 17 was a zero
Last bit shifted out of Position 17 was a one
. Execution Time
(n = number of shifts)
SLHA : 360+60n
26
Tllis information is proprietary and is supplied by INTER DATA for the sale
purpose of using 'Bnd maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless spacifically authorized in writing.
05-058A15 ROO 5/75
5.4.7 Shift Right Arithmetic
SRA
0
S,A,B,I,E,D,MC
3
5 6
~~JOI I"
SRAX
0
11
I
S
16
A
I
20
1 100
I
25
B
10
26 27
D
3
5
SRAI
6
I
16
A
I
25, 26
20
1 100
I
B
IcI
31
PAGE ADDRESS
S,A,DATA,I
3
5 6
~IIOld
1
[RR IMMEDIATE]
11
S
I
MC
[RR TRANSFER]
11
S
31
28
lEI I
S,A,B,ADRS,I,C
~Iooill
0
[RR CONTROL]
1
16
A
I
31
20
1 1 00
I
I
DATA
The contents of the register specified by A are shifted right the number of bit positions specified by the least significant
5-bits of the second operand. The result replaces the contents of the register specified by S. Only Bits 1 :31 participate in
the shift; Bit 0 remains unchanged and is propagated right into Position'! on each shift. Low order bits shift through the
Carry flag and are then lost.
SRA,SRAI : (SO) .--(AO)
(SI:31) .. R
(A1:31)
BE(27:31)
SRAX
(SO)04- (AO)
(SI :31) ~(Al :30
BE(27:31)
then (RLClO:15)" PAGE ADDRESS ifC = 0 or Carry
(RLC4:15)'" (RLC4:15)+1 ifC= 1 and Carry = 1
=0
Resul ting flags
CV GL
0 o0
001
0 t 0
0
1
Result is zero
Result is less than zero
Result is greater than zero
Last bit shifted out was a zero
Last bit shifted out was a one
Execution Times (n = number of shifts)
SRA,SRAI
: 360+6On
SRAX (No transfer) : 500+60n
: 360+60n
SRAX (Transfer)
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing,
27
5.4.8 Shift Right Halfword Arithmetic
S>A~B,I,E,D,MC
SRHA
[RR CONTR.OL}
o
The least significant IS-bits of the register specified by A are shifted right the number of bit positions specified by the least
significant 4-bits of the second operand. The result replaces the least significant IS-bits of the register specified by S. The
most significant i 7-bits of the register specified by A replace the most significant 17-bits of the register specified by S. Bit
16 is propogated right into bit Position 15 on each shift. Bits shifted out of Position 31 are shifted through the Carry flag
and then lost.
SRHA:
(SO: 16).-(Ao:16)
(SI7:30.
R
(AI7:3l)
BE(28:3l)
Resulting flags
CV GL
000
001
o10
0
1
Halfword result is zero
Halfword result is less than zero
Halfword result is greater than zero
Last bit shifted out was a zero
Last bit shifted out was a one
Execution Times (n = number of shifts)
SRHA:
28
360+60n
This information is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining.INTERDATA supplied equipmant and shall
not ba used for any othar purpose unless specifically authorized in writinll.
OS-058AlS ROO 5/75
5.4.9 Rotate Left
0
3
G~JOI
3
G~]OO
II I
I
S
16
A
5 6
II I
11
I
S
20
I
10 1 1
16
A
I
I
25
B
I
III
E
D
3
31
25 26
B
II
c
I
PAGE ADDRESS
[RR IMMEDIATE]
5 6
G~}OIII
I
MC
[RR CONTROL]
20
10 1 1
10
31
26 27 28
S,A,DATA,I
RLI
0
11
5 6
S,A,B,ADRS,I,C
RLX
0
[RR CONTROL]
S,A,B,I,E,D,MC
RL
16
11
I
S
A
I
31
20
10 1 1
I
I
DATA
The contents of the register specified by A are shifted left, end around, the number of bit positions specified by the least
significant 5-bits of the second operand. Bits shifted out of Position 0 are shifted into Position 31.
RL,RLI
RLX
: (SO:31)~(AO:31)
BE(27:31)
(SO:30....2:-(AO:31)
BE(27:31 )
:then (RLCI0: 15)'" PAGE ADDRESS
Resulting flags
CV GL
o0 o0
o0 o1
o0 1 0
Result is zero
J Result is not zero
Execution Times (n
= number of shifts)
RL,RLI,RLX: 360+60n
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining I NTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
29
S.4.10 Rotate Riaht
0
001
3
0
001
001
16
11
I
.S
A
25 26 27
20
I
1 0 10
I
B
10
I EI DI
3
100
II I
16
11
5 6
I
S
A
20
I
1010
I
25
110
B
31
Ic I
I
I
PAGE ADDRESS
[RR IMMEDIATE]
5 6
II
I
MC
26
S,A,DATA,I
3
31
28
[RR TRANSFER]
S,A,B,ADRS,I,C
RRI
0
5 6
101 11 I
RRX
I
[RR CONTROL]
S,A,B,I,E,D,MC
RR
16
11
I
S
A
I
31
20
10 10
I
I
DATA
The contents of the register specified by A are shifted right, end around, the number of bit positions specified by the least
significant 5-bits of the second operand. Bits shifted out of Position 31 are shifted into position O.
RR,RRI : (SO:30..-!:-(AO:31)
BE(27:31)
(So:3})~(Ao:31)
RRX
BE(27:3!)
then (RLCI0:15)'" PAGE ADDRESS
Resulting flags
CV
o 0
o 0
o 0
GL
o 0
o 1
I 0
Result is zero
JResult is not zero
Execution Times (n = number of shifts)
RR,RRI,RRX: 360+60n
30
This information is proprietary and is supplied by INTERDATA for the sol.
purpose of using and maintaining INTERDATA supplied equipment end shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
5.5 Fixed Point Arithmetic Instructions
The Fixed Point Arithmetic Instructions provide for addition, subtraction, multiplication and division of fixed point data
contained in the Processor registers. The instructions described in this section are:
5.5.1
A
AX
AI
Add
Add and Transfer
Add Immediate
5.5.2 .
AINC
AINCX
Add and Increment
Add and Increment and Transfer
S
SX
SI
Subtract
Subtract and Transfer
Subtract Immediate
SDEC
SDECX
Subtract and Decrement
Subtract and Decrement and Transfer
M
MX
MI
Multiply
Multiply and Transfer
Multiply Immediate
D
DX
DI
Divide
Divide and Transfer
Divide Immediate
5.5.3
5.5.4
5.5.5
5.5.6
05-058A15 ROO 5/75
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining I NTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
31
5.5.1 Add
[RR CONTROL]
S,A,B,I,E,D,MC
A
0
001
101
AX
II
I
S
16
I
A
I
20
0001
I
26 27
25
B
10
3
o1
5 6
100
Ii I
IEI I
D
16
I
A
I
(5 26
20
0001
I
B
Cl
31
,0
3
I 00
110
[RR IMMEDIATE]
5 6
II
I
I
PAGE ADDRESS
S,A,DATA,I
AI
I
MC
[RR TRANSFER]
11
S
31
28
S,A,B,ADRS,I,C
0
0
11
5 6
3
16
11
S
I
A
I
31
20
0001
I
DATA
il
The second operand is algebraically added to the first operand. The sum replaces the contents of the register specified by S.
A,AI
AX
(S).. (A) + BE
(S) .. (A) + BE
then (RLCI0: 15) .. PAGE ADDRESS if
C = 0 or Carry = 0
(RLC4: 15)" ( RLC 4: 15) + 1 if C = 1 and
Carry = 1
Resulting flags:
CV GL
o0
o1
1 0
1
1
Sum is zero
Sum is less than zero
Sum is greater than zero
Overflow
Carry
Execution Times:
A,AI
240
AX (No transfer): 380
AX (Transfer)
240
32
This information is proprietary and i. supplied by INTERDATA for the sole
purpose of u'ing and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless ,pecifically authorized in writing.
Os-058A15 ROO 5/75
5.5.2 Add and Increment
AINC
0
S,A,B,I,E,D,MC
3
II I
AINCX
0
11
5 6
~Iol
[RR CONTROL]
I
S
16
A
I
25 26 (7 rs
20
0011
I
B
I lED
0
S,A,B,ADRS,I
3
G;:loo II I
I
S
I
MC
[RR TRANSFER]
11
5 6
31
A
(
25
20
001 1
I
B
31
26
Ic I
PAGE ADDRESS
1
The second 'operand is algebraically, added with the first openmd and a forced carry in of one. The sum replaces the
contents of the register specified by S.
AINC
AINCX
(S) ... (A) + BE + ~
(S) ... (A) + BE + 1
then (RLClO:15)'" PAGE ADDRESS if C =0 or Carry
(RLC4: 15)'" ( RLC 4: IS) + I if C 1 and Carry 1.
=
=
=0
Resulting flags
CV GL
o 0 Sum is zero
o 1 Sum is less than zero
I 0 Sum is greater than zero
1
Overflow
I
Carry
Programming Note
Multiple precision addition operations require a carry forward from the least significant to the most significant .operands. The following example shows a double word add ~pe~~tion.
*
*
*
*
*
MRO AND MRI CONTAIN THE 64 BIT FIRST OPERAND
MR2 AND MR3 CONTAIN THE 64 BIT SECOND OPERAND
THE 64 BIT RESULT IS RETURNED IN MRO and MRI
START
*
*
*
SUM2
SUM3
AX
MRI,MRl,MR3,SUM2,C
AINCX
MRO,MRO,MR2,SUM3
A
MRO,MRO,MR2
SUM LOW OPERANDS FIRST
TRANSFER IF NO CARRY, ELSE
FALL THROUGH, SUMMING
HIGH OPERANDS THEN ADD ONE,
SKIP TO SUM3.
•
SUM HIGH OPERANDS
MRO,MRI = 64-BIT RESULT
Execution Times
AINC
240
AINCX (No transfer): 380
AINCX (Transfer)
240
05-058A15 ROl 5;76
This Information is proprietary and Is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shell
not be used for anv other pu~posa unless speclflcallv 8\lthorized in writing.
33
5.5.3 Subtract
S
S,A,B,I,E,D,MC
0
001
I:
I
I: (
[RR CONTROL]
16
11
S
I
A
1
0000
S,A,B,ADRS,I,C
SX
0
001
3
5 6
100
II I
16
11
S
I
A
1
r
B
I
(:(8
0
001
3
110
B
Icl
PAGE ADDRESS
I
I
[RR IMMEDIATE]
5 6
1I
1
31
25 26
S,A,DATA,I
SI
MC
[RR TRANSFER]
20
0000
(; 12:
31
11
S
I
16
A
I
31
20
0000
I
DATA
1
The second operand is algebraically subtracted from the first operand. The difference replaces the contents of the register
specified by S.
S,SI : (S) ... (A) - BE
SX : (S) .. (A) - BE
then (RLCIO:15) ... PAGE ADDRESS if C = 0 or Carry
( RLC 4: 15)" ( RLC4: 15) + 1 if C = 1 and Carry = 1
=0
Resulting flags
CV GL
o 0 Difference is zero
o 1 Difference is less than zero
1 0 Difference is greater than zero
1
Overflow
1.
Borrow
Execution times
S,SI
SX (No Transfer)
SX (Transfer)
34
240
380
240
This information il proprietary and is supplied by INTEROATA for the lole
purpose of using and maintaining INTEROATA supplied equipment and shall
not b. used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
5.5.4 Subtract and Decrement
S,A,B,I,E,D,MC
SDEC
0
3
~Ol
SDECX
0
[RR CONTROL]
5 6
I
1 1
11
S
I
16
A
I
25
20
0010
I
B
26 27
101 E ID
5 6
~OO II I
11
S
1
31
I
MC
[RR TRANSFER]
S,A,B,ADRS,I,C
3
28
I
16
A
I
0'010
1
31
25 26
20
B
Ic I
I
PAGE ADDRESS
The second operand and a forced carry in of one are subtracted from the first operand. The result replaces the contents of
the register specified by S.
SDEC
SDECX
(S) ... (A) - BE -' 1
(S) ... (A) - BE - 1
then (RLClO: 15) ... PAGE ADDRESS if C = 0 or Carry = 0
(RLC4: 15) ... (RLC4: 15) + 1 if C = 1 and Carry = 1
Resulting flags
CV GL
o0
o1
1 0
1
1
Difference is zero
Difference is less than zero
Difference is greater than zero
Overflow
Carry
Programming Note
See Add and Increment
Execution Times
SDEC
SDECX (No Transfer)
SDECX (Transfer)
05-058A15 ROO 5/75
240
380
240
This information is proprietary and is supplied by INTEROATA for the lole
purpose of using and maintaining I NTER OAT A supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
35
5.5.5 Multiply
M
I
S,A,B,I,E,D,MC
o
16
3
5 6
[RR TRANSFER]
11
01
MI
I
MC
B
S,A,B,ADRS,I,C
o
o
1110
A
S
001
MX
•
[RR CONTROL]
16
A
S
I
20
1 1 10
25
31
26
, PAGE ADDRESS
B
S,A,DATA,I
o
[RR IMMEDIATE]
356
16
11
S
001
A
31
1 110
DATA
The 32-bit second operand is multiplied by ,the contents of the first operand register. The 32 most significant product bits
replace the contents of the register specified by S. The 32 least significant product bits replace the contents of the first
operand register, the register specified by A. The S field must specify an even numbered register. The A field must specify
. the next sj3quential register, an odd number. The sign of the product is determined by the rules of algebra.
M,MI
MX
: (S,A) ... (A) * BE
: (S,A)'" (A) * BE
then (RLClO:15)'" PAGE ADDRESS
Resulting flags
Itltl
000 0
Execution Times
M,MI,MX:
36
2580/3480/4440
minimum/average/maximum
This information is proprietary and i. lupplied by INTERbATA fOr tHe IOle
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpole unless spa~ilicallv authorized in wliting,.
05-0S8AI5 ROl 5/76
5.5.6 Divide
S,A,B,I,E,D,MC
D
0
3
5 6
11
1···oO~)J III
S
16
A
1111
I
.3
B
I 0 IE ID I
DI
11
I
S
16
A
I
1111
I
31
25 26
20
B
I cl
3
[RR IMMEDIATE]
5 6
11
G;~}o II I
I
PAGE ADDRESS
S,A,DATA,I
0
MC
[RR TRANSFER]
. 5 6
~OOIII
31
25 26 27 28
20
S,A;B,ADRS,I,C
DX
.0
[RR CONTROL]
I
S
16
A
I
31
20
1111
I
I
DATA
The 32-bit second operand is divided into the 64-bit dividend contained in the registers specified by S and A, an eveil/odd
pair. The S field must specify an even numbered register and the A field must specify the next sequential odd register. The
resulting 31l-bit quotient with sign is contained in A and the 3 I-bit remainder with sign is contained in S. The sign of the
quotient is determined by the rules of algebra; the sign of the remainder equals the sign of the dividend.
(A)... (S,A)/BE
(S) ... Remainder
D,DI
DX
(A)";" (S,A)/BE
(S) ... Remainder
then (RLClO:15) .... PAGE ADDRESS
Resulting flags
CV GL
o0 o0
o1o0
Normal
Divide fault
Programming Note
A quotient that would be greater than '7FFF FFFF' or less than '8000 0000' causes the division to be
aborted with the V flag set and an unpredictable remainder in S. The register specified by A is unchanged.
Execution Times
D,DI,DX:
05-058A15 ROO 5/75
4560
This information is proprietary and is supplied by INTER DATA for the iole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any othor purpose unless specifically authorized in writing.
/ 37
5.6 Floating Point Instructions
These instructions provide for the manipulation of single precision floating point data and double precision floating point
data. A floating point quantity consists of a signed exponent and a signed magnitude fraction. The 7-bit exponent is
expressed in excess 64 notation and can range in actual value from +63 through zero to -64. The value of the exponent
field is that power of 16 that the fraction field is to be multiplied by. The 24 or S6 bit fraction is expressed as a
hexadecimal number having a radix point to the left of the high order fraction digit. Bit 0 of the full word or double word
is the sign bit of the fraction.
f
L~~____________~y,______________~1
Fraction Sign
Fraction
Fraction Sign
Fraction
The standard Model 8/32 has single precision floating point arithmetic capability included in the Arithmetic Logic Unit
(ALU). The micro instructions associated with this feature of the ALU provide for the manipulation of single precision
floating-point data. When the single precision floating point unit is addressed (Module Number 3), references to the user's
General Registers, either directly or by way of YO or YS, select the corresponding single precision floating point registers
instead. These registers are shown on the block diagram, Figure 1, as ERO through ERF. There are 16 32-bit floating point
registers, although in the user level architecture only the even numbered registers are actually used.
The optional precision floating point ALU (DFU), which is not shown on the block diagram, is also capable of performing
single precision floating point operations with greater accuracy than the standard single precision floating point unit. When
the DFU is installed, all of the existing single precision only floating point capability remains intact, including the 16
floating point registers. Thus the microcode can exclusively use the DFU or mix operations with the single precision unit.
The double precision floating point unit will be discussed in more detai11ater. First, the instructions associated with the
single precision only floating point unit, and described in this section are:
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
CE
CEQ
CEQX
AE
SE
AU
ME
DE
Compare
Compare and Equalize
Compare and Equalize and Transfer
Add
Subtract
Add Un normalized
Multiply
Divide
------------_.
38
ThIS information is proprietary and is supplied by INiERDATA for the .ole
purpose of using and maintaining INTERDATA supplied equipment ehd shall
not be used for any other purpo5e unless ,speoifically authorized in ,writi!,g.
05-058A15 ROl 5/76
5.6.1 Compare
CE
S,A,B,I,E,D,MC
[RR CONTROL]
~_:_I_LI:-L16___S____~ll_l___A__~1_16_0__1_0_1__~1_20___B____-L~_5~1_26_E~12_:_L12_8___
31
MC
The first operand is compared to the second operand. The comparison is algebraic, taking into account the sign, exponent
and fraction. The.result is indicated by the resultant flags. The S Bus should be NuLL selected.
, CE
(A):BE
Resulting flags
CV GL
o 0 o 0 First operand equal to second operand
I 0 o 1 First operand less than second operand
o 0 1 0 First operand greater than second operand
Execution Times
CE:
05-058A15
ROO 5/75
240
This inforrhation is proprietaty and is'supplied by INTER DATA for the soh'
purpose of using and maintaining I NTER DATA supplied equipment and shall
not be used to,r any other purpose unless specifU::ally authorized in writing.
39
Compar~
5.6,2
CEQ
S,A,B, l,E,D,MC
3
0
Io
11
0
11
5 6
101
CEQX
Io
and Equalize
II
I
[RR CONTROL]
11
S
I
16
A
I
20
1 100
I
25 26 27
B
10 IE
I
D
S,A,B,ADRS,I,C
3
5 6
100
II I
I
31
Me
1
[RR TRANSFER]
16
11
S
28
I
A
20
1 100
I
31
25 26
B
lei
I
PAGE ADDRESS
The first operand is compared to the second operand. The comparison is,magnitude only-the sign bits of the two operands
are ignored. The result of this comparisori-'isdndicated by the resultant flags.
,
,
The fraction field of the smaller of the two operands is shifted right hexadecimally (4-bits at a time) the number of times
indicated by the exponent difference of the two operands. The result fraction replaces the contents of the register specified
by S.
The affect of this instruction is to unnormalize the smaller number so that the radix points of the two arguments are
aligned.
In the RR Transfer format, if the C bit is set, a transfer occurs if the second operand is smaller than the first operand.
CEQ:
CEQX:
if (A 1 :3}) S BE (1 :31),
(S). (Ag :31)
X .... BEO :7) - (AI :7)
if(Al:30 >BE(1:31),
(S)+(BE (8:31)
X+(AI :7) - BE (1 :7)
R
then (S) +- (S)
4X
if (AI :31)~ BE (1 :31),
(S) .... (A8:30
X+SE (1 :7) -- (Al:7)
if(Al:31) >BE(1:31),
(S) ..... BE (8:31)
X+(AI :7) - BE (1 :7)
R
then (S)..-(S)
4X
•
if (AI :31) > BEO :31) or C = 0
(RLCIO:lS) ..... PAGE ADDRESS
•
if (A 1 :31) ~ BEO :31) and C = 1
( RLC4:15)i ..... ( RLC4:15)+1
Resulting flags_
CV
Gt
o0 o0
1 0 o1
o0 1 0
First operand equal to second operand
First operand less than second operand
First operand greater than second operand
ProgrammiI1:g Note
This instruction must precede the floating point Add or Subtract ihstructions to properly set-up the
second operand.
Execution Time (E = number of equalizitig shifts - maximum
CEQ:
480+60E
CEQX (no transfer):
660+60E
CEQ (transfer):
480+60E
40
=5)
'This information i. proprietary end Is suppliOCl by INTERDATA for ~he lola
purpose of using arid maintaining INTERDATA supplied equipment and shill
not be used for any other; purpdsl! unless speclfi,cally, authorized in iNriting.
OS-058A15 ROI 5/76
5.6.3 Add
[RR CONTROL]
S,A,B,I,E,D,MC
AE
o
3:
5 6
11
16
20
25 26 27 28
~1~111~I_B~I__A~I_IO_Ol~1_ B~lo~IEI~DI_
31
MC
Proper execution of this instruction requires that a Compare and Equalize instruction has been performed on the two
arguments and that the result of the Compare and Equalize-that is, the smaller of the two arguments-is on the B Bus.
The second operand fraction is algebraically added to the first operand fraction. The result replaces the contents of the
register specified by S.
If the addition of fractions produces a carry, the result fraction is shifted right one hexad~cima1 position and the result
exponent is incremented by one. If no carry was produced, the result fraction is normalized if necessary; 'the result
exponent is decremented by one for each normalization cycle required.
AE:
(S)
+--
(A)+BE
Resulting flags
CV GL
o0 o0
OX o 1
Result is zero
Result is less than zero
OX 1 0 Result is greater than zero
o 1 XX Exponent overflow
o 1 o 0 Exponent underflow
Programming Notes
In the event of exponent overflow, the result flags show the proper sign for the result, but the data returned
in the register specified by S is unpredictable. The microprogram should detect the exponent overflow case
and then OR a value of '7FFFFFFF' into the register specified by S.
In the event of exponent underflow, the entire result is set to zero.
The following program sequence shows the correct way to Add two floating-point numbers.
*
*
*
*
*
*
THE FLOATING POINT REGISTER SPECIFIED BY YD
CONTAINS THE FIRST OPERAND.
THE FLOATING POINT REGISTER SPECIFIE]) BY YS
CONTAINS THE SECOND OPERAND.
AER
*
*
*
*
*
*
*
*
AERI
*
CEQX
AE
AE
MRO,YD,YS,AERl,C
YD,YS,MRO,E
BALV
FAULT (NULL),ILlR,D
YD, YDjMRO,E
BALV
SMALLER OPERAND TO MRO
TRANSFER IF YS CONTAINED
THE SMALLER OPERAND
FALL THROUGH IF YD WAS
EQUAL TO OR LARGER
THANYS.
ADD SMALLER TO LARGER,
RESULT TO YD & SET CC
TO FAULt IF V FLAG, ELSE
INCR. LOC, FETCH & DECODE
NEXT USER INStR.
ADD SMALLER to LARGER
RESULT to YD &, SEt cc
FAULT (NULL),ILIR,D
*
Execution Times (n = number of normalize cycles)
AE:
05-058A15 ROO 5/75
360+60 n
This information is prop~iefary and is supplied by INTER DATA for the 101E!
purpose of usinb .rid maintaining INTERDATA suppliad ,equipment and s~all
not be usad for any other purpose unless .SPllcifically ~uthorlzed in llliriting.
41
5.6.4
Subtract
[RR CONTROL]
S,A,B,I,E,D,MC
SE
o
356
011
11
16
A
S
25
20
MC
B
1 000
31
26 27 28
Proper execution of this instruction requires that a Compare and Equalize instruction has been performed on the two
operands and that the result of the Compare and Equalize-that is, the. smaller of the two operands-is on the BBus.
The second operand fraction is algebraically subtracted from the fraction of the first operand. The result replaces the
contents of the re'gister specified by S.
If the subtraction of fractions produces a carry, the result fraction is shifted right one l:texa(\~ci1!lal position and the result
exponent is incremented by one. If no carry was produced, the result fraction is normalized i{necessary;theresulCex-=
ponent is decremented by one for each normalization cycle required.
SE
: (S)
.... (A)-BE
Resulting flags
CV GL
o0 o0
OX o 1
Result is zero
Result is less than zero
OX 1 0 Result is greater than zero
01 XX Exponent Overflow
o 1 o 0 Exponent Underflow
Programming Note
See Add
Execution Times
SE
(n
= number of normalize cycles)
: 360+6On
5.6.5 Add Unnormalized
S,A,B,I,E,D,MC
AU
o
3
5 6
[RR CONTROL]
16
11
I
A
I
000 1
20
I
25
26
B
31
27 28
MC
Thl" second operand is added to the first operand and the unnormalized result replaces the contents of the register specified
by 3. For this instruction, both arguments are assumed to be fixed-point 32-bit quantities. No Compare and Equalize
instruction is needed.
AU: (S) .... (A) + BE
Resulting flags
CV GL
o0 o0
o0 o1
o0 1 0
Result is zero
Result is less than zero
Result is greater than zero
Programming Note
This instruction is included to provide a means to access the floating point registers without using the
floating point arithmetic instructions.
Execution Time
AU : 240
42
This information is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpole uniesl specifically authorized in writing.
05-058Al5 ROO 5/75
5.6.6 Multiply
0
[RR CONTROL]
S,A,B,I,E,D,MC
ME
3
~Ial J1 I
16
II
5 6
S
I
A
I
25 26
20
1110
I
B
27 28
lalElol
31
I
MC
The exponents of the first and second operands are added and set aside as the exponent of the final result. The result sign
is detennined by the rules of algebra. The fractions of the firSt and second operands are then multiplied. If the product is
zero, the entire result, sign and exponent included, is set to zero. If non-zero, the product is normalized or corrected as
necessary. The sigp, exponent and result fraction are combined and replace the contents of the register specified by S.
ME: (S) ... (A)*BE
Resulting flags
CV GL
o 0 o 0 Result is zero
o X o 1 Result is less than zero
o X 1 0 Result is greater than zero
o 1 XX Exponent Overflow
o I o 0 Exponent Underflow
Programming Notes
In the event of exponent underflow, if the result 01 the multiplication of fractions is not zero, it is forced
to zero and the result exponent and sign are cleared.
In the event of exponent overflow, the result in the register specified by S has the proper sign bit, but the
exponent and fraction are not predictable. The microprogram should detect the exponent overflow
situation and OR a value of '7FFFFFFF' into the register specified by S.
Execution Times
ME:
1860/2580/3300
05-058AI5 ROO 5/75'
minimum/average/maximum
Thlsin'forination is proprietary and i& supplied by INT,EROATA for the soie
purpose of using and maintaining INTEROATA suppli,ed equipment and shall
not be used for any o\her purpose unless specifically a~thorlzed in writing.
43
5.6.7 Divide
DE
0
[RR CONTROL]
S,A,B,I,E,D,MC
3
5 6
o 1 1 10 1 1I
I
S
I
20
16
11
A
1
1111
The exponents of the first and second operands are
The result sign is determined by the rules of algebra.
If the result fraction is zero, the entire result is set to
necessary. The sign, exponent, and result fraction are
I
31
B
MC
subtracted and the result set aside as the exponent of the final result.
The second operand divisor is divided into the first operand dividend.
zero. If the result fraction is non-zero, it is normalized or corrected as
combined and replace the contents of the register specified by S.
DE: (S) .. (A)/BE
Resulting flags
CV GL
o0 o0
o Xo 1
oX1 0
Result is zero
Result is less than zero
Result is greater than zero
1 X X Exponent overflow
100 Exponent underflow
Programming Notes
The hardware does not check for attempted division by zero. The microprogram must detect a zero divisor
before doing the divide.
See Multiply.
Execution Times
DE :
44
3480/3540
Best/Worst
This information is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unlell~ specifically euthorlzed in writing.
05-058A15 ROO 5/75
The DFU'is a standard plug-in module to the 8/32. A unique set 0[24 microinstructions is provided to access the DFU
(Module Number 6).
Figure 3 shows a block diagram of the DFU. The DFU is situated between the 32-bit S Bus and the 32-bit B Bus. The A
Bus does not connect to the DFU. The DFU contains its own set of eight 32-bit single precision registers and eight 64-bit
double precision registers.
In microinstructions directed to the DFU, references to the user's General Registers, either directly or by way of the YD or
YS fields of the user's instruction, caUSe the corresponding single-precision floating point register or half (32-bits) of a
double precision floating point register to be accessed. The microinstruction itself distinguishes whether a single precision
or a double precision operation is to be performed. Single precision operations can only use the single precision registers
and double precis~on operations can only use the double precision registers.
The two hallves of a double precision register are selected on an even/odd addressing scheme. For example, accessing double
register 2 selects the most significant 32 bits of double register 2, and accessing double register 3 selects the least significant
32 bits of double register 2.
Note that the single precision registers in the pFU are separate and distinct from the single precision registers in the basic
processor.
e
~
S. BUS
e
q
CC.BUS
LOCAL S. BUS
(STAC K B)
(STACK A)
ERO 0
ERO 2
ERO 4
ERO 0
ERO 2
ERO 4
••
•
ERE
••
•
ERE
DRO
DRU
DR2
DOUBLE PAECISION
ALU
DR 2
DR4
DR 4
DRE
.DRE
LOCAL A BUS
----'--
-----
--------
o-
f
B. BUS
Figure 3. Double Precision Floating Point Unit Block Diagram
05-058A15 ROI 5/76
THis informiltion is propri.e.tary and is, supplied by INTEROATA for ihe sole
purpose of using a~d maintaining INTEROATA ,sppplied eqJipment and shall
not be. used for any ot~~r pU~pOse unless specilically authOrized. in writing.
'45
'The floating point ALU operates in a fully autonomous mode having its own internal A, B, and S Busses. Given a load, add,
subtract, multiply, or divide operation, the floating point module performs the function asynchronous of other Processor
activity. The microprogram is free to do other microinstructions while the floating point module is finishing its task. If the
microprogram attempts to test the result of an operation or begin another floating point operation before the last one is
completed, the processor stops until the old function is completed before starting the next.
This feature has an impact on determination of execution times. The execution time shown for Divide Single Precision, for
example, is 2920 nanoseconds. In practice, assuming the floating point module is not busy, the microinstruction that
initiates the divide takes only 240 nanoseconds. The processor immediately begins the next sequential microinstruction.
The floating point module is working on its own and will be busy for the next 2680 nanoseconds (2920-240). If this
microinstruction does not reference the floating point module, the instruction is performed and the next microinstruction
is begun. This continues until a microinstruction is fetched that does access the floating point module. At that time, the
processor must wait out any of the divide execution time remaining - 2680 nanoseconds minus the execution time of all
intervening microinstructions. If there was any time left at all, an additional 60 nanoseconds has to be added in for
resynchroniza ti on.
The instructions described in this section are:
5.6.8
5.6.9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
5.6.19
5.6.20
5.6.21
5.6.22
5.6.23
46
RCC
LE
LEX
LEI
RRE
RREX
CER
AER
SER
MER
DER
LW
LWX
LWI
LD
LDX
LDI
RRD
RRDX
CDR
ADR
SDR
MDR
DDR
Read Condition Code
Load Register Single Precision
Load Register Single Precision and Transfer
Load Register Single Precision Immediate
Read Register Single Precision
Read Register Single Precision and Transfer
Compare Single Precision
Add Single Precision
Subtract Single Precision
Multiply SIngle Precision
Divide Single Precision
Load Unnonnaliz'ed Double Precision
Load Unnormalized Double Precision and Transfer
Load Unnormalized Double Precision Immediate
Load Register Double Precision
Load Register Double Precision and Transfer
Load Register Double Precision Immediate
Read Register Double P:recision
Read Register Double Precision and Transfer
Compare Double Precision
Add Double Precision
Subtract Double Precision
Multiply Double Predsion
Divide Double Precision
This information i. pfopriei8ry and is slipplied by INTERDATA iot the loie
purpose of using and maintaining INTEF.l.OATA supplied equipment and shall
not be used for any other piJrpose urlikss specifically ~uih!,rized iii' Writing.
OS-O'58At5 ROt 5/76
5.6.8 Read Condition Code
RCC
S,B [,I,E,D,MC]
o
3
5
6
[RR CONTROL]
11
16
G'L-I°----L-b-LI_,_S,_L-I__~I_O
20
. L-I
,_0____
0 _0
125 26 27 28
31
1 I_MC-----'1
0 E,i...a....D_____
_B_--£_----L
This instruction is used to collect the flags that resulted from the last single precision or double precision floating point
operation.
RCC:
CCBUS+--Floating Point Flags
Resulting Flags
Determined by previous floating point operation
Programming Notes:
The Sand B fields are not used and should be NULL selected.
Execution Times
240
05-058A15 ROt 5/76
This iniorn\ation is proprieiary and is supplied by INTERDAT,A for ihe sole
purpose of using arid maintaining INTERDATA supplied equipment and sh~1I
not be us~ f?r any other purJ>i>se unless specifical,ly ,a\lthorized in writing.
47
5.6.9
Load Register Single Precision
A,B,I,K,E,D,MC
LE
0
3
11
010
LEX
5
6
11
I I 11
A
I
20
16
I0
0
0
B
I
3
0
10
5
0
I
A,DATA,I
0
3
11
0 II
5
IKIEIDI
MC
[RR TRANSFER]
11
6
I II
LEI
31
25 26 27 28
A,B,ADRS,I,C
0
II
[RR CONTROL)
16
A
I
I
20
00
0
!
31
25 26
B
lei
PAGE ADRS
[RR IMMEDIATE)
II
6
0 I I II
I I
16
A
I
00
20
0
I
31
DATA
I
The second operand is nonnalized, if necessary and then loaded into the floating point register specified by A. Normalization involves shifting the fraction field left four bits at a time until the most significant four fraction bits are not zero. For
each four place shift required, the exponent is decremented by one.
For the RR Control fonnat, setting the K bit causes normalization to be avoided. The second operand is copied directly
into the floating point register specified by A with no modification.
LE,LEI
LEX
(A)+B E
(A)+B E
then (RLC 10: 15y--AD RS
Resulting flags (Second operand also a floating point register)
Not Meaningful
Resulting flags (Second operand not a floating point register)
CV GL
o 0 o 1 Result is less than zero
o 0 1 0 Result is greater than zero
o 1 XX Fraction was not normalized
Programming Notes
A Load microinstruction where both first and second operands are floating point registers does not produce
meaningful flags. A Read Condition Code microinstruction is required if the flags need to be known. If the
second operand is not from a floating point register, if the V flag is reset, the argument was already
normalized. In this case the G and L flags are properly set. If the V flag does set, the argument fraction was
not normalized. An argument of zero is considered to be an un-normalized quantity for this test.
The normalization process continues autonomous of other processor activity. When finished,
Condition Code microinstruction will collect the final flags.
a
Read
Resulting flags (After Read Condition Code)
CV GL
o0 o0
o0 o1
o0 1 0
o 1 o0
Result is zero
Result is less than zero
Result is greater than zero
Exponent underflow
The A field must only specify a floating point register.
Execution Times
LE,LEX,LEI : 240+ lOOn
48
This information i. proprietary and i. supplied by INTERDATA for tho sola
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058AI5 ROI 5/76
5.6.10 Read Register Single Precision
RRE
o
S:,B,I,E,D,MC
3
S
[RR CONTROL]
r
6
S
RREX
S,B,ADRS,I,C
31
B
MC
I
[RR TRANSFER]
6
~ 3
S 1
1111
' 16
120
25 26
31
l~--,O-+I-I;----~S--------~_-------------l~I~O--O--O----+_------B-------~IC~I--_PAGEADRS
I
The contents of the floating point register specified by B are copied to the register specified by S.
RRE
RREX
(S)..-{B)
(S)"'(B)
then (RLC lO : 1S )+ADRS
!{esulting Flags
Not Meaningful
!'rogramming Notes
Floating point register selection is not affected by the least significant B address bit. If an odd numbered
register is specified, the next lower even numbered register is selected instead.
The S field may specify any register other than a floating point register.
Execution Times
RRE,RREX: 300
OS-OS8A15 ROt 5/76
This information is proprietary and is supplied by INTERDATA for tlie sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not
used for ,any oth""r purpose unless specific~lIy authori ed in writili,g.
be
49
5.6.11 Compare Single Precision
CER
o
A,B,I,E,D,MC
3
5
[RR CONTROL]
6
16
11
A
10 0
20
25 26 27 28
B
31
MC
The first operand is compared to the second operand. The comparison is algebraic, taking into account the sign, exponent,
and fraction. The result is indicated by the resulting flags.
CER: (A): BE
Resulting Flags after RCC
CV GL
o0 o0
1 0 o 1
o0 1 0
First operand equal to second operand
First operand less than second operand
First operand greater than second operand
Execution Times
CER: 400
50
This information i. proprietary and is supplied by INTERDATA for the !ole
purpose of using and maintaining INTERDATA supplied equipment and !hall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROI 5/76
5.6.12
AER
A,B,I,E,D,MC
0
I
Add Single Precision
3
0
1
0
5
[RR CONTROL]
6
11
I I 11
I
16
A
I
0
20
0
0
I
25 26 27 28
B
101 EI DI
31
I
MC
The first operand is compared to the second operand. The comparison is in magnitude only, ignoring the signs of the two
operands. TIle fraction field of the smaller of the two operands is shifted right hexadecimally (4-Bits at a time) the number
of times indiicated by the difference of the exponents of the two operands. This is called equalization. Note that because
the DFU has internal 56 bit arithmetic capability, hexadecimal digits shifted out of the low order end of the 24 bit fraction
field are not lost. In practice, only the last digit shifted out is saved. This digit is called a "guard" digit and is provided for
extended accuracy.
The affect of this process is to unnormalize the smaller operand enough so that the radix points of the two arguments are
aligned. If the exponent difference exceeds six, the smaller operand loses significance and a value of zero is substituted.
The equalized fraction with its guard digit and the fraction of the other operand with trailing zeros are then algebraically
added, taking into account the signs and order of the two operands. The result fraction with an exponent equal to that of
the larger operand replaces the contents of the floating point register specified by A.
If the addition of fractions produces a carry, the result fraction is shifted right one hexadecimal position and the result
exponent is incremented by one. If no carry was produced, the result fraction is nbrmalized if necessary. The result
exponent is decremented by one for each nonnalization cycle required.
AER: (A)+-(A)+BE
Resul ting Flags
CV GL
o 0 Result is Zero
o 1 Result is less than Zero
1 0 Result is greater than Zero
o 1 Exponent Overflow
1 0
o 0 Exponent Underflow
o0
o0
o0
o1
o1
oI
Programming Notes
In the event of exponent overflow, the proper sign bit is generated and the rest of the result is set to all
ones ± 7FFFFFFF.
In the event of exponent underflow, the entire result is set to zero.
Execution Times
AER: 750 + 100 (e+n)
e = Equalize Cycles
n = Normalize Cycles
worst case total of e+n = 6
05-058A15 ROI 5/76
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA .upplied equipment and shall
[ not be used for any pther purpose, unless sPecifically authorize~, in writing.
51
5.6.13 Subtract Single Precision
SER
A,B,I,E,D,MC
0
3
I
[RR CONTROL]
0
10
5
11
6
I[1
25 26 27 28
I
A
o
B
MC
TIle first operand is compared to the second operand. The comparison is in magnitude only, ignoring the signs of the two
operands. The fraction field of the smaller of the two operands is shifted right hexadecimally (4-Bits at a time) the number
of times indicated by the difference of the exponents of the two operands. Note that because the DFU has internal 56 bit
arithmetic capability, hexadecimal digits shifted out of the low order end of the 24 bit fraction field are not lost. In
practice, only the last digit shifted out is saved. This digit is called a "guard" digit and is provided for extended accuracy.
The affect of this process is to unnormalize the smaller operand enough so that the radix points of the two arguments are
aligned. If the exponent difference exceeds five, the smaller argument loses significance and a value of zero is substituted.
The equalized fraction with its guard digit anq the fraction of the other operand with trailing zeros are then algebraically
subtracted, taking into account the signs and order of the two operands. The result fraction with an exponent equal to that
of the larger operand replaces the contents of the floating point register specified by A.
If the subtraction of fractions produces a carry, the result fraction is shifted right one hexadecimal position and the result
exponent is incremented by one. If no carry was produced, the result fraction is normalized if necessary. The result
exponent is decremented by one for each normalization cycle required.
SER: (A)..-(A)+BE
Resul ting Flags
CV GIL
o0 o0
o0 oI
o0 I 0
o1o1
o110
o1 o0
Result is zero
Result is less than zero
Result is greater than zero
Exponent Overflow
l
Exponent Underflow
Programming Notes
See Add Single Precision
Execution Times
e = Equalize Cycles
n = Normalize Cycles
SER: 750+100(e+n)
worst Gase total of e+n = 6
52
This information i. proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining INTERDATA supplied equipment~ and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 R01 5/76
· 5.6.14
MER
Multiply Single Precision
A,B,I,E,D,MC
[RR CONTROL]
~'~I-~--I-+I-:~I-~----------I~I-1----A----~r-:------0-+r-0----B------~:-5r:I:128
Me
The exponents of the first and second operands are added then set aside as the exponent of the final result. The result sign
is determined by the rules of algebra. The fractions of the first and second operands are then multiplied. If the product is
zero, the entire result, sign and exponent included, is set to zero. If the product is non-zero, it is normalized or corrected as
necessary. The sign, exponent, and result fraction are combined and replace the contents of the floating point register
specified by A.
MER: (A)+-(A)* BE
Resulting Flags
CV GL
o 0 Result is zero
o 1 Result is less than zero
1 0 Result is greater than zero
o 1 xponent Overflow
1 0
o 0 xponent Underflow
o0
o0
o0
o1
o1
o1
~
Programming Notes
In the event of exponent overflow, the proper sign bit is generated and the rest of the result is set to all
ones ± 7FFFFFFF .
In the event of exponent underflow, the entire result is set to zero.
Execution Times
MER: 1170/1670/2170 Best/Average/Worst
05-058A15 ROI 5/76
This information is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
53
5.6.15 Divide Single Precision
DER
0
II
A,B,I,E,D,MC
3
1 0
5
Id
10
The exponents
The result sign
If the result is
necessary. The
specified by A.
[RR CONTROL]
6
11
I
1
I
16
A
I
0
20
25 26 27 28
B
MC
of the first and second operands are subtracted and the result set aside as the exponent of the final result.
is determined by the rules of algebra. The second operand divisor is divided into the first operand dividend.
zero, the entire result is set to zero. If the result fraction is non-zero, it is nonnalized or corrected as
sign, exponent, and result fraction are combined and replace the contents of the floating point register
DER: (A)+-(A)/BE
Resul ting ,flagS
CV IG L
o 0 Result is zero
o 1 Result is less than zero
1 0 Result is greater than zero
o Exponent Overflow
1 OJ
o 0 Exponent Underflow
1 1 o 0 Divisor was zero
o0
o0
o0
o1
oI
o1
11
Programming Notes
In
the event of attempted division by zerO, the result destination register is unchanged and the operation
aborts with a condition code of 11002'
See Multiply Single Precision
Execution Times
DER: 2950
54
This information is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROt 5/76
5.6.16 Load Unnonnalized Double Precision
LW
A,B,I,E,D,MC
0
3
5 6
I II
~ 10
LWX
0
111
I
16
A
11
000
A,B,ADRS,I,C
3
~olo
LWI
[RR CONTROL]
5
o
6
I II I
I
11
I
116
A
1
000
e
(0
B
3
5
MC
1
[RR TRANSFER]
31
25 26
B
A,DATA,I
o
L=oll o
I~(:(~I
31
II
c
PAGE ADRS
1
[RR IMMEDIATE]
6
1I1
(
16
A
11
000
(0
31
DATA
1
This microinstruction is required when the second operand for a double precision function is not resident in one of the
double precision registers. That is, the operand is contained in a pair of Micro Registers or in main memory or in the
Control Store memory.
This instruction specifies the most significant 32-bits of the desired argument. These 32 bits are copied into a holding
register in the floating point unit. A subsequent double precision microinstruction places the least significant 32-bits of the
operand on the B Bus and the operation is performed.
.
LW,LWI
LWX
FALU+-BE
FA LU.....BE
then (RLClO: 15)"'ADRS
Resulting flags
Unchanged
Programming Notes
The A field is not used and should be Null Selected.
If the subsequent double precision operation does specify a double precision register, the 32-bits presented by
the Load Word microinstruction are ignored and the operation is carried out using the 64-bits of the double
precision register specified.
Execution Times
LW,LWX,LWI: 240
OS-058A15 ROt 5/76
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using aod maintaining INTERDATA supplied equipment and shall
not be used fbr any other purpose unless specifically authorized in writing.
55
5.6.17 Load Register Double Precision
LD
A,B,I,E,D,MC
0
3
11
01 0
LDX
5
I
6
3
0
I
I 11
5
16
A
I
20
0
0
25 26 27 28
I
B
10
o
I
0
3
0
11
5
0
16
11
I
I 11
A,DATA [,1]
10
I
Eiol
3)
MC
[RR TRANSFER]
6
LDI
I
11
A,B,ADRS,I,C
0
11
[RR CONTROL]
A
I
20
0
0
I
31
25 26
B
II
C
PAGEADRS
1
[RR IMMEDIATE]
11
6
Id1
I
A
16
11 0
31
20
0
I
DATA
1
If the second operand is resident in one of the double precision registers, the second operand is normalized, if necessary,
and placed in the double precision register specified by A.
If the second operand is not resident in one of the double precision registers, prior to this instruction a Load Word
microinstruction has presented the most significant 32-bits of the 64-bit second operand to the floating point unit. This
instruction then places the least significant 32-bits of the second operand on the B Bus. The fitst 32-bits and the 32-bits of
B Bus data form the effective second operand. The second operand is normalized, if necessary, and placed in the double
precision register specified by A.
LD,LDI
LDX
(A)"BE
(A)"B
then (R\C lO : l5)"ADRS
Resul ting flags
o0
o0
o1
0 1 Result is less than zero
1 0 Result is greater than zero
X X Fraction was not normalized
Programming Notes
After a Load microinstruction, the V flag reset means that the argument was already normalized. In this case
the G and L flags are properly set. If the V flag is set, the argument fraction was not normalized. An argument
of zero is considered to be un-normalized for this test.
The normalization process continues autonomous of other Processor activity. When finished, a Read
Condition Code microinstruction will collect the final flags.
Resulting flags (after Read Condition Code)
CV GL
o0 o0
o0 o 1
o0 1 0
o1 o0
Result is zero
Result is less than zero
Result is greater than zero
Exponent Underflow
The A field may only specify a double precision floating point register.
Execution Times
LD,LDX,LDI : 320+100n
56
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any, other purpose unless specifically authorized in writing.
OS-058AlS ROt 5/76
5.6.18 Read Register Double Precision
RRD
S,B,I,E,D,MC
0
3
~olo
5
[RR CONTROL]
11
6
I1
s
I
RRDX
S,B,ADRS,I,C
0
3
5
1
16
t 1
1
20
0
o1 1
25 26 27 28
B
101 EI DI
31
MC
1
[RR TRANSFER]
6
16
11
~olo o 1I 1
s
I
1
20
0
0
1
25 26
B
I~I
31
PAGEADRS
The con1tents of the double precision floating point register half specified by B are copied into the register specified by S.
The flags generated by this instruction equal the result flags of the last floating point operation.
RRD:
RRDX:
(S)+-(B)
(S)+-(B)
then (RLC 10: IS)+- Page Address
Resulting Flags
Unchanged from last floating point operation.
Execution Times
RRD, RRDX: 240
When this instruction follows a floating pOint add, subtract, multiply, or divide, its effective execution times is 60
nanoseconds.
05-058A15 ROt 5/76
This information is proprietary and is SUllplied by INTERDATA for the sale
purpose of using and maintainin'g INTERDATA supplied equipment and shall
not be used for any other. purpo~e, unless specificallv authorized i~ writing.
57
5.6.19 Compare Double Precision
CDR
A,B,I,E,D,MC
0
3
5
10
II
0
II
6
I
[RR CONTROL]
11
I
16
A
11
31
0
B
MC
1
The first operand is compared to the second operand. The comparison is algebraic, taking into account the sign, exponent,
and fraction. The result is indicated by the resulting flags.
CDR: (A): BE
Resul ting Flags
CV G L
o 0 0 0 First operand equal to second operand
1 0 o 1 First operand less than second operand
o 0 1 0 First operand greater than second operand
Execution Times
CDR: 400
58
Thi' infOrmation is proprietary and is iupplied by INTEROATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writi~g.
05-058A15 ROt 5/76
5.6.20 Add Double Precision
ADR
o
A,B,I,E,D,MC
3
[RR CONTROL]
5 6
II
Gllo I
I
16
A
I
20
o
0
I
31
25 26 27 28
B
10 1E ID I
I
MC
The first operand is compared to the second operand. The comparison is in magnitude only, ignoring the signs of the two
operands. The fraction field bf the smaller of the two operands is shifted right hexadecimally (four bits at a time) the
number of times indicated by the difference of the exponents of the two operands.
The affect of this process is to unnormalize the smaller operand enough so that the radix points of the two arguments are
aligned. l[f the exponent difference exceeds thirteen, the smaller operand loses significance and a value of zero is substituted.
The equalized fraction and the fraction of the other operan.d are then algebraically added, taking into account the signs and
order of the two operands. The result fraction with an exponent equal to that of the larger operand replaces the contents
of the double precision floating point registers specified by A.
If the addition of fractions produces a carry, the result fraction is shifted right one hexadecimal position and the result
exponent is incremented by one. If no carry was produced, the result fraction is normalized if necessary. The result
exponent is decremehted by one for each normalization cycle required.
ADR: (A) ..... (A)+BE
Resul ting Flags
CV GL
o 0 Resul t is zero
o 1 Result is less than zero
1 0 esult is greater than zero
o 1 xponent Overflow
1 0
o 0 Exponen.t Underflow
o0
o0
o0
o1
o1
o1
~
Programming Notes
In the event of exponent overflow, the proper sign is generated and the rest of the result is set to all ones
+7FFFFFFFFFFFFFFF.
In the event of exponent underflow, the entire result is set to zero.
Execution Times
ADR: 750 + 100 (e+n)
e = eq ualize cycles
n = normalize cycles
worst case total of e+n = 13
05-058A15 ROI 5/76
This iriforrnation is proprietary and is supplied by INTERDATA for the sole
purpose of using aod rnaintairiing INTEROATA supplied equipment and shall
not be used, for any other purpose unless speCific"I,Iv, authorized in writing,
59
5.6.21 Subtract Double Precision
A,B,I,E,D,MC
SDR
[RR CONTROL]
o
16
A
I 0
o
B
MC
The first operand is compared to the second operand. The comparison is in magnitude only, ignoring the signs of the two
operands. The fraction field of the smaller of the two operands is shifted right hexadecimally (four bits at a time) the
number of times indicated by the difference of the exponents of the two operands.
The affect of this process is to unnormalize the smaller operand enough so that the radix points of the two operands are
aligned. If the exponent difference exceeds thirteen, the smaller operand loses significance and a value of zero is
substituted.
The equalized fraction and the fraction of the other operand are then algebraically subtracted taking into account the signs
and order of the two operands. The result fraction with an exponent equal to that of the larger operand replaces the
contents of the double precision floating point register specified by A.
If the subtraction of fractions produces a carry, the result fraction is shifted right one hexadecimal position and the,result
exponent is incremented by one. If not carry was produced, the result fraction is normalized if necessary. The result
exponent is decremented by one for each normalization cycle required.
SDR:
(A).--(A)+BE
Resulting Flags
CV
o0
o0
o0
o1
o1
oI
GL
o0
o1
o1 1
1 0
o0
Result is zero
Result is less than zero
Result is greater than zero
Exponent overflow
o!
Exponent underflow
Programming Notes
See Add Double Precision
Execution Times
SDR:
750 + 100 (e+n)
e = equalize cycles
n = normalize cycles
Worst case total of e+n = 13
60
This information is proptietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose urile . . . pecifically authorized in writing,
OS-OS8AlS ROI 5/76
5.6.22 Multiply Double Precision
MDR
0
G)
A,B,I,E,D,MC
3
10
5
1
[RR CONTROL]
11
6
Id
I
1
16
A
I
20
25 26 27 28
B
31
MC
The exponents of the first and second operands are added then set aside as the exponent of the final result. The result sign
is determined by the rules of algebra. The fractions of the two operands are then multiplied. If the product is zero, the
entire result, sign and exponent included is set to zero. If the product is non-zero, it is normalized or corrected as
necessary. The sign, exponent, and result fraction are combined and replace the contents of the double precision floating
point register specified by A.
MDR; (A) .... (A)*BE
Resulting Flags
CV GL
o 0 Resul t is zero
o I Result is less than zero
1 0 esult is greater than zero
o 1 xponent Overflow
1 0
o 0 Exponent Underflow
o0
o0
o0
o1
o1
oI
~
Programming Notes
In the event of exponent overflow, the proper sign bit is generated and the rest of the result is set to all
ones + 7FFFFFFFFFFFFFFF.
In the event of exponent underflow, the entire result is set to zero.
Execution Times
MDR: 1800/3000/4200
05-058A15 ROt 5/76
Best/ Average/Worst
This information is proprietary and is supplied by INTERDATA fOr tho sole
purpose Of usirig aod maintaining INTERDAfA supplied Qquipment arid shall
hOt, be u~l!d Ibr any otHar purpo,.e unless speo,ilically auth<>rized in writing:
61
5.6.23 Divide Double Precision
DDR
A,B,I,E,D,MC
a
356
1
[RR CONTROL]
16
11
a
A
25 26 27 28
20
B
MC
The exponents of the first and second operands are subtracted and then set aside as the result exponent. The result sign is
determined by the rules of algebra. The second operand divisor is divided into the first operand dividend. If the result is
zero, the entire result is set to zero. If the result fraction is non-zero, it is normalized or corrected as necessary. The sign,
exponent, and result fraction are combined and replace the contents of the double precision floating point register
specified by A.
DDR: (A)+-(A)/BE
Resu} ting Flags
CV GL
a a a a Result is zero
a a a 1 Result is less than zero
a a 1 a Result is greater than zero
a I a 1~'Exponent Overflow
a I 1 a~
a 1 a a Exponent Underflow
I 1 a a Divisor was zero
Programming Notes
In the event of attempted division by zero, the result destination register is unchanged and the operation
aborts with a condition code of 11002See Multiply Double Precision
Execution Times
DDR: 7420
This information is proprietary and i. supplied by INTERDATA for tho sole
purpose of using lind maintaining INTERDAtA supplied equipment and shall
62
not be used for ahy other purposd unless specifically authorized in writing.
05-058A15 ROt 5/76
Implementation Note:
The DFU is normally strapped to respond as Processor Module 6. Consequently, the DFU microinstructions assemble with
a module number of 6. If there are two DFUs in the system, the second DFU must be strapped to respond as Processor
Module 4. DFU Module 6 will be the primary unit used by the basic microcode. DFU 4 will then be the auxiliary unit
available to the WCS user. Since the two DFUs run in a fully autonomous mode, simultaneous calculations can be carried
out to greatly improve the overall speed of any heavy floating point algorithms.
In order to allow microcode to be assembled for a DFU strapped as Module Number 4, the Common Microcode Assembler
(MICROCAL) has a pair of special psuedo-operations that cause the module number of a DFU directed microinstruction to
be switched from Module 6 to Module 4 and vice versa.
The assembler is normally in the DFU Module 6 mode. Consequently, an AER microinstruction will normally assemble
with a module number of 6. The appearance in the source program of a DFU4 psuedo operation places the Assembler in
the DFU Module 4 mode until a DFU6 psuedo operation is encountered. While in the DFU Module 4 mode, all micro
instructions directed to the DFU (AER for example) will assemble with a module number of 4.
A psuedo operation is an instruction only to the assembler and, as such, causes no object code to be generated.
The following code sequence shows the use of two DFUs.'to calculate B=A2 + B + C.
where A, Band C are micro registers
DFU6
LE
MER
DFU4
LE
AER
O,A
0,0
O,B
O,C
SELECT DFU 6
LOAD EO IN DFU6 WITH A
FORM A SQUARED
SELECT DFU 4
LOAD EO IN DFU 4 WITH B
ADDC
*THE MULTIPLY STARTED IN DFU 6IS STILL IN PROGRESS
RRE
DFU6
RRE
AER
RRE
B,O
NULL,B
O,B
B,O
READ B+C RESULT INTO B
SWITCH BACK 1'0 DFU 6
WAIT FOR MULTIPLY TO FINISH
ADD B TO A SQUARED
FINAL RESULT TO B
In this example, the execution times of the microinstructions directed to DFU 4 (LU, AER & RRE) can be completely
ignored because their total does not exceed the time it took DFU6 to do the initial multiply. The total time, using average
execution times is 2.78 microseconds instead of 3.83 microseconds.
05-058A15 ROI 5/76
This informat;ori is proprietary and i~ supplied by INTEROATA for tna sole
purpose Of. using and maintaining. INTERDATA supplied equipment and 'hall
not be usetl for any other purpose un",." specifically authorized In writing.
63
5.7 Byte Handling Instructions
These instructions use the I/O module to perfonn byte manipulations on the least significant 16·bits of A, B, and S Bus
data. The instructions described in this section are:
5.7.1
LB
LBR
Load Byte
Load Byte Register
5.7.2
STB
STBR
Store Byte
Store Byte Register
5.7.3
EXB
Exchange Byte
5.7.1 Load Bl:te
LB
S,A,B,I,E,D,MC
0
010
3
. 16
11
10 1 II I
LBR
0
5 6
[RR CONTROL]
I
S
A
I
20
I
1 1 0.1
25
B
11
26 27 28
I EIDI
S,B,I,E,D,MC
3
01 II
11
I
MC
I
[RR CONTROL]
5 6
010 1
31
I
S
16
1 1 II}
I
20
o10
~
I
25 26
B
27 28
I IE ID
1
31
MC
1
Bits 16: 23 of the first operand or Bits 24: 31 of the second operand replace Bits 24: 31 of the register specified by S. The
most significant 2+bits of S are set to zero. For the LB instruction, whether the A or B operand is used depends upon the
state of Memory Address Bit 31. For the LBR instruction, the B operand is always used.
LB:
(SO:23) .. 0
(S24:31)'" (A}6:23) if MA3} =0
(S24:31)" BE(24:31) ifMA31 = 1
LBR: (SO:23)" 0
(S24:31>'" BE(24:31)
Resulting flags
ItlGILI
o
0 0 0
Execution Times
LB,LBR:
64
250
Thil Information II proprletlrV Ind II lupplied bV INTEROATA for the lole
purpol. of ullng and maintaining INTEROATA lupplied equipment and Ihall
not b. Uled for Inv other purpole unl ... lpeclflceliV authorized in writing.
05·058A15 ROO 5/75
5.7.2 Store BXte
STB
0
~
STBR
0
..
S,A,B,I,E,D,MC
3
16
11
5 6
10 1I,
[RR CONTROL]
I
S
I
A
I
25
20
110 0
I
B
26 27
11 IEID I
S,~;B,I,E)D,MC
3
5 6
S
I
MC
[RR CONTROL]
11
~ 10 1II I
31
28
I
16
A
Io
20
1 00
I
25 26 27
B
11
28
I EI I
D
31
I
MC
Bits 24: 31 of A are copied to Bits 24: 31 or Bits 16: 23 of the register specified by S. The byte position not loaded is
replaced by the corresponding byte position of the second operand. Byte steering on the STB instruction depends upon the
state of Memory Address Bit 31.
STB:
(SO: 15) ...... 0
(SI6:23) .... (A24:31) ]MA31 = 0
(S24:31) ..... BE(24:31)
(S16:23) ..... BE(16.:23)] MA = 1
(S24:30 .... (A24:30
31
STBR: (SO:15)·... 0
(SI6:23)'" BE(16:23)
(S24:31) .... (A24:31)
Resulting flags
ICIVIGILI
o0 0 0
Execution Times
STB,STBR:
05-0:58A15 ROO 5/75
250
This information Is ptoprietary and is supplie(j by INTEROATA for the lole
purpose Of using and maintaining INTEROATA slJPplied equlpmant and .hall
not be used, for any other purpose un,len specifically authorized In ~rit,inll,
65
5.7.3 Exchange Byte
0
010
[RR CONTROL]
8,B,I,E,D,MC
EXB
3
S 6
101
16
11
II
8
I
I
I I I 1I
I
25 26 27 28
20
I I 10
I
B
I II I
E
D
31
MC
The two low order bytes of the second operand are exchanged and loaded into the register specified by 8.
EXB:
(80: 1S) ... 0
(816:23) .... BE(24:31)
(824:31) .... BE(16:23)
Resulting flags
ItriLi
o
0 0 0
Execution Times
EXB
66
2S0
Thll information is propriEitary and il supplied by INTERDATA for the lole
purpOse of using end maintaining INTERDATA supplied equipment and shall
not be used for eny other purpoie unless specificelly authorized. in writing.
OS-oS8AIS :ROO S/75
1
5.8 Control Instructions
These in.structions allow testing and clearing the Machine Control Register, control over the console interrupt and the
console WAIT lamp, control over externally usable signals, and the Initialize relay. The instructions covered in this section
are:
.'
5.8.1
SMCR
SMCRX
Sense Machine Control Register
Sense Machine Control Register and Transfer
5.8.2
CMCR.
Oear Machine Control Register
5.8.3
LWFF
Load the Wait Flip-Flop
5.8.4
POUT
Pulse Output Lines
5.8.5
POW
Power Down
5.8.6
BDC
Branch and Disable Console
OS-058AlS ROO 5/75
This information i". proprietary and is supplied by INTERDATA for the sole
purpOse o.f using and maintaining INTERDATA supplied equipment and shall
not be used .for any other purpose urBess specifically authorized in writing.
67
5.8.1 Sense Machine Control Register
SMCR
0
010
[RR CONTROL]
S,B,I,E,D,MC
3
5 6
101
II I
SMCRX
11
I
S
16
1I I 11
Io
111
I
25
B
10
26 27 28
I: (
16
111111
S
MC
1
[RR TRANSFER)
11
1:0
31
IE ID 1
S,B,ADRS,I,C .
0
010
20
1
25 (6
20
011 I 1
B
I
C
31
PAGE ADDRESS
1
The contents of the Machine Control Register replace the contents of the register specified by S. Bits 12: 15 of the MCR
become available on the CC Bus and are copied into the micro flag register.
SMCR:
SMCRX:
(S) ... (MCR)
(S) ... (MCR)
then (RLC1O:15)"'PAGE ADDRESS
Resulting flags
VGL
I
rrrn
1 1
.
1
Unused
1Memory Error
Early Power Failure
Programming Notes
The B field is not used and should be NULL selected.
The meaning of the Machine Control Register bits is summarized' below.
I
04
05
06
07
DFU
HWCRC
INIT
SNGL
08
09
10
Spare
ARST (STRAP) Automatic Restart Option
CATN
Console Attention. This signal goes active when any
Display Panel function is selected and remains active
until the Hexadecimal Display Panel is addressed.
Start Time Failure. An addressed module (e.g., I/O
STF
Mod ule) has failed to respond within 35
micro-seconds.
Spare
MM
Memory Malfunction (e.g., parity error)
11
12
13
14
15
Double Precision Aoating Point ALU installed
Hardware Assist Cyclic Redundancy Check installed
Initialize Switch on Display Panel Depressed
Console Single Step. This signal goes active when the
SGL switch on the Hexadecimal Display Panel is
depressed and remains active until any other
functional switch is depressed.
J
1
MM
Early Power Failure.
EPF
Execution Times
SMCR,SMCRX
68
290
This information is proprietary and i, supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equ"ipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROI 5/76
5.8.2 Clear Machine Control Register
CMCR
o
[RR CONTROL]
S,B,I,E,D,MC
3
11
5 6
~1011II
16
111111 I 0111
s
25
20
I
B
I
31
26 27 28
IE
II
D
MC
The bits iln the Machine Control Register that correspond to 'ones' in the second operand are set to zeros. The S field is not
used and should be NULL selected.
CMCR: (MCR)'" (MCR) AND BE
Resul ting flags
ICIVIGILI
o0 0 0
Programming Note
The MCR bits that are straps cannot be modified.
Execution Times
CMCR:
240
5.8.3 Load the Wait Flip-Flop
LWFF
S,B,I,E,D,MC
[RR CONTROL]
11
111111
16
20
I 0110 I
25
B
31
26 27 28
I IE
I I
D
MC
Bit 16 of the second operand is copied into the Wait flip-flop. A 'one' sets the flip-flop and tums on the Console WAIT
lamp. A 'zero' resets the flip-flop and turns off the Console WAIT lamp.
LWFF: WAIT .. BE(16)
Resulting flags
ICIVIGIL!
000 0
Execution Time
LWFF:
05-058A1S ROO 5/75
·240
. THis irifbr~tion is proprietary and Is supplied bv INTERDATA for the .ole
iHirpOse of using and maintairiing INTEAr$A1:A ijupplied equipment alld ·shall
not be;' Used for an~ other purpOse ·utlle., .speciflcallv authorized in Writing.
- 69
5.8.4
POUT
0
010
Pulse Out~ut Lines
S,B,I,E,D,MC
3
5 6
101
II
I
[RR CONTROL]
S
11
16
111111
I
20
1111
I
25
B
26 27 28
I IE ID I
31
MC
I
The Model 8/32 I/O Module features four board stakes labeled PAO, PBO, pca and PDO to be used for external signalling
purposes. The POUT instruction generates a low active pulse on the PxO lines that correspond to ones in Bits 28 :31 of the
second operand.
POUT:
PA
PB
PC
PD
...
...
...
...
BE(Bit 31)
BE(Bit 30)
BE(Bit 29)
BE(Bit 28)
Resulting flags
nVIGILI
000 a
Programming Note
The width of the pulse output (controlled by a timer on the Input/Output Module) can be lengthened if
necessary by changing components. The execution times given are for the standard Input/Output Module
without system modifications.
Execution Times
POUT:
5.8.5
POW
o
1220
Power Down
S,B,I,E,D,MC
3
5 6
[RR CONTROL]
11
16
111111 11111
20
B
MC
The Power Down micro-instruction releases the System Clear relay and initializes the system. The S, Band MC fields are
not interpreted. The resulting Condition Code and execution time are meaningless.
When the System Clear relay is re-enabled, micro-code execution resumes at Control Store Memory address '001'
70
This information i. proprietary and i. supplied bv INTERDATA for the 'Ole
purPose of using and mainl8ining INTERDATA supplied equipmant and shall
not be used for any other purpose ·uriless specifically authorite'd in writing.
05-05SA15 ROO 5/75
5.8.6 Branch and Disable Console
BDC
[ADDRESS LINK]
ADRS(LINK),E,D,MC
31
14
I
BDC
ADDRESS
MC
[REGISTER LINK]
(B) (LINK),E,D,MC
11
LINK
I
110
B
MC
Interrupts from the Console (CATN or SNGL) are ignored for the inteIVal of this instruction so that interrupts of lower
priority can be detected. No branch is actually taken, so MC and D field functions can occur.
BDC:
(LINK) ... (RLC4: 15)+1
Execution Time
BDC:
240 nanoseconds
OS-OS8A1S ROO 5/75
This Information is proprietary and is supplied by INTEROATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
71
6.
INPUT/OUTPUT SYSTEM
This section discusses the Input/Output 0/0) System. There are several methods of communications between the Processor
and peripheral devices or other system elements. The methods vary in speed, sophistication, and the amount of attention
required by the Processor.
6.1 Multiplexor Bus
The Multiplexor Bus is a byte or halfword oriented I/O system which communicates with up to 1,023 peripheral devices.
The Multiplexor Bus consists of 33 lines - 16 bi-directional data lines, 10 control lines, 6 test lines and 1 initialize line. The
lines in the Multiplexor Bus are:
Data Lines
Control lines
Test lines
Initialize
DOO:15
SR
DR
CMD
DA
ADRS
ACKO
ACK1
ACK2
ACK3
CL07
ATNO
ATN1
ATN2
ATN3
SYN
HW
SCLR
(Processor ~Device )
···
·.
(
(
(
(
(
(
(
(
(
(
(
)
)
)
))
)
)
)
III
( ..
(
III
(
..
(
II
(
III
(
···
··
)
)
)
)
)
)
)
)
.)
16 lines
1 line
1 line
1 line
1 line
1 line
1 line
1 line
1 line
1 line
1 line
1 line
1 line
1 line
1 line
1line
1 line
1 line
6.1.1 Data Lines. The 16 bi-directional data lines are used to transfer one 8-bit byte, one 10-bit device address,
or one 16-bit halfword between the Processor and the device. In actuality, 16 bits are always transferred, and the device or
the Processor accepts as much of the data as is required for the particular operation.
6.1.2 Control Lines
ADRS
Address. The Processor presents a lO-bit device address on Data lines D06: 15. The device controller that
recognizes its address becomes the 'on-line' device and responds with a synchronize (SYN). Once a device
has been addressed, it remains addressed until a different device is addressed or a system initialize occurs. If
the device is halfword oriented, the Halfword test line (HW) is also active.
DA
Data Available. The Processor presents data to be transferred to the addressed device on Data lines
DOO: 15. The addressed device controller accepts the low order byte or the entire ha1fword and responds
with a SYN.
DR
Data Request. The addressed device controller presents data on Data lines D08:15 or DOO:15, followed by
aSYN.
SR
Status Request. The addressed device controller presents status information on Data Lines D08: 15,
followed by a SYN.
CMD
Output Command. The Processor presents a command byte on Data lines D08: 15 for the addressed device.
The addressed device controller accepts the command byte and responds with a SYN.
ACKO
ACK1
ACK2
ACK3
Acknowledge. The microprogram generates an Acknowledge signal on the appropriate line in response to an
active Attention (ATN) test line. The device controller nearest the Processor on the particular Acknowledge
line that is activating the corresponding ATN line presents its address on Data Lines D06: 15, followed by a
SYN. That device controller then removes ATN.
CL07
This Control Line is activated by the Initialize key, the PWR OFF switch or when the optional Power fail
detector determines that the Processor's primary power is failing. The line remains active as long as the PPF
interrupt line is active.
72
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
6.1.3 Test Lines
AT NO
ATNI
ATN2
ATN3
Attention. When so enabled, any device on one of the Attention lines desiring to interrupt the Processor
will activate the ATN x line and hold it active until an Acknowledge is received from the Processor.
HW
Halfword. Any halfword oriented device will activate the Halfword test line when it becomes addressed and
hold the line active for as long as the device is addressed. The HW line being active suppresses the byte
steering done in the I/O module on DA or DR operations.
SYN
Synchronize. This signal is generated by the device controller to inform the Processor that it is responding
to the active control line.
6.1.4 Initialize Line
SCLR
System Qear. This is a metallic contact to ground that occurs during Power fail or Initialize.
6.2. Input/Output Instructions
Communication over the Multiplexor Bus is on a request/response basis where each operation started by the Processor
must receive a SYN response to terminate the operation. If no SYN response is received within approximately 35
micro-seconds, a False Sync (FSYN) is automatically generated to terminate the operation.
Input/Output micro-instructions generate one, two, or three Multiplexor Bus operations. Each operation lasts until a SYN
is received from the device, meaning that the execution time on I/O instructions is solely device dependent.
NOTE
All I/O instruction execution times are given using the following
assum pti ons:
1. Average circuit delays, not max. or min.
2. SYN delay of 100 nanoseconds
3. No Bus Buffer delay in the system.
The instructions described in this section are:
6.2.1
AK
AKX
Acknowledge Interrupt
Acknowledge Interrupt and Transfer
6.2.2
SSA
SSAX
SSRA
Address and Sense'Status
Address and Sense Status and Transfer
Address and Sense Status Register
6.2.3
SS
SSX
SSR
Sense Status
Sense Status and Transfer
Sense Status Register
6.2.4
OCA
OCAX
OCAI
OCRA
Address
Address
Address
Address
6.2.5
OC
OCX
OCI
OCR
Output
Output
Output
Output
6.2.6
RDA
Address and Read Data
Address and Read Data and Transfer
Address and Read Data Register
RDAX
RDRA
6.2.7
Output Command
Output Command and Transfer
Output Command Immediate
Output Command Register
Command
Command and Transfer
Command tmmediate
Command Register
RDR
Read Data
Read Data and Transfer
Re'ad Data Register
WDA
WDAX
WDAI
WDRA
Address
Address
Address
Address
RD
RDX
6.2.8
and
and
and
and
05-058AIS ROO 5/75
and Write
and Write
and Write
and Write
Data
Data arid Transfer
Data Immediate
Datk Register
ThiS Information is proprletarv and is supplied bV INTER DATA for the sole
pllrpose of using and maintainirig INTEADATA supplied equipment and shilll
not b. used for any other purpdse unless specifically authorized ih writing,
73
6.2.9
WD
WDX
WDI
WDR
Write
Write
Write
Write
Data
Data and Transfer
Data Immediate
Data Register
6.2.10
RHA
RHAX
Address and Read Halfword
Address and Read Halfword and Transfer
6.2.11
RH
RHX
Read Halfword
.Read Halfword and Transfer
6.2.12
WHA
WHAX
Address and Write Halfword
Address and Write Halfword and Transfer
6.2.13
WH
WHX
Write Halfword
Write Halfworcl and Transfer
6.2.14
THWX
Test Halfword line and Transfer
6.2.1 Acknowledge Interrupt
S,B,I,E,D,MC
AK
0
0
3
0
010
11
5 6
I
101 I
S
1
11 I
111
16
20
1 o1 I 0
1
25
B
26 27 28
10 lEI
S,B,ADRS,I,C
AKX
0
[RR CONTROL]
3
00
1
5
11
S
1
MC
1
[RR TRANSFER]
6
II I
D
31
111111
16
1
20
o1 10
I
25 26
B
1c 1
31
PAGE ADDRESS
1
Bits 30 and 31 of the effective second operand select the desired ACK Control line. The device number of the interrupting
device replaces the contents of the register specified by S. The interrupt condition in the controller is cleared.
AK : (SO:21)-'-0
(S22:31 )....--DEVICE NUMBER
AKX
: (SO:21)+-0
(S22:30...-DEVICE NUMBER
then (RLClO:15)+-PAGE ADDRESS
Resulting flags
CV GL
o0 o0
o1 o0
Normal Execution
Instruction Time-Out (No Interrupts)
Programming Note
Each ACK Control line passes through the interrupt circuits on all of its assigned controllers in a 'daisy
chain' fashion. The execution time is increased by 100 nanoseconds fOr each controller between the
Processor and the interrupting controller.
Execution Time
AK,AKX
74
480
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied lKIulpmilnt and shall
not b. used for any othe~ purpose unless specifically authorized .in writing.
05~058A15
Rob 5/75
6.2.2 Address and Sense Status
SSA
o
S,A,B,I,E,D,MC
2
4 5
[RR CONTROL]
11
16
20
25 26 27 28
~~III--s~1--A~I-101-0~1--B~lo~IE~IDISSAX
S,A,B,ADRS,I,C '.
MC
[RR TRANSFER]
o 2. 4 5
11
16
20
25 26
~-+II-+I--s-----fI--A--+-1-1-0-1-O-+I---B----..:ll--c-II---P-A-G-E-A-DDRESS
o
[RR CONTROL]
S,A,B,I,E,D,MC
SSRA
2
4
5
11
~---l..-...LII_S---LI__
I
31
A
16
20
--,--I
--1..-11_0
10
25 26 27
-----L.I----L--IE--'----I..I
D 1_
_B
31
28
MC
The register specified by A contains the device address. The device is addressed and its 8-bit Status byte replaces the
contents of the register specified by S. The right most four bits of the Status byte are available on the CC Bus and are
. copied into the micro flag register.
SSA:
CC Bus .......DEVICE STATUS (4:7)
(SO: 15) ....... 0
(S16:23) ......-DEVICE STATUS} if MA3 1 = 0
(S24:31 )+-BE(24:31)
(S16:23) ......-BE(16:23)
} if MA3l = I
(S24:31) ......-DEVICE STATUS
SSAX: Same as SSA
then (RLCI0:15)---PAGE ADDRESS
SSRA CC Bus ...DEVICE STATUS (4:7)
(SO:15) .. 0
(S16 :23) .......-B E(16:23)
(S24:3}) .......-DEVICE STATUS
Resulting flags
VGL
1
Device Busy (BSY)
.Examine Status (EX) or TimtrOut
I
End of Medium (EOM)
I Device Unavailable (DU)
mJJ
I
Execution Times
SSA,SSAX,SSRA:
OS-058A15 ROO 5/75
1180
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
75
6.2.3 Sense Status
S,B,I,E,D,MC
SS
0
010
3
5 6
101
I, I
SSX
0
010
010
11
S
I
11111
16
I
20
0010
I
25 26 27
B
10
3
5 6
100
I, I
D
I
11111
16
I
20
5 6
101
I, I
I
0010
I
B
31
Ie I
PAGE ADDRESS
I
[RR CONTROL]
11
S
MC
25 26
S,B,I,E,D,MC
3
31
[RR TRANSFER]
11
S
28
IE I I
S,B,ADRS,I,C
SSR
0
[RR CONTROL]
11 1111
16
I
25 26 27
20
0010
I
B
11
IEI I
D
31
28
MC
I
The Sense Status instructions are identical to the Address and Sense Status instructions except that the address cycle is
avoided. Once addressed, a device controller remains addressed until a different device controller is addressed or a System
Clear occurs.
Execution Times
SS,SSX,SSR
76
480
This information i. proprietary and i. supplied by INTER DATA for the 10 Ie
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purposa unless specifically authorized in writing.
05-058A15 ROO 5/75
6.2.4 Address and Output Command
o
[RR CONTROL]
S,A,B,I,E,D,MC
OCA
3
5 6
11
~'---!-..--11
16
20
25 26 27 28
~I~I
8
I 1 _---I1_A_Il.....--1
0_
1 1--1--1._B
OCAX
o
5 6
~~I_I~I~
OCAI
o
E I-L--D
1 _ M _ C------II
[RR TRANSFER]
11
~I
16
__S____ ____A__
~I~I_0
20
__
1_1__
~1_____
B____
25 26
~I_C~I
3
[RR IMMEDIATE]
5 6
11
____ _____A__
~I
16
__l_0_l_l__
20
~I
31
____________D_A_T_A_______
S,A,B,I,E,D,MC
OCRA
3
31
_____
PA_G_E
__
A_D_DRESS
S,A,DATA,I
~~I_I~I~_S ~I
o
0
S,A,B,ADRS,I,C
3
31
5 6
[RR CONTROL]
11
16
~l~
20
~I
I I I,---s_I'---A-----I-I
1 0_
11
31
25 26 27 28
_ B-----+--1--,----,-I
E I----I---D
I _
MC
The register specified by A contains the device address. The device is addressed and the 8-bit second operand command
byte is sent to the device.
OCA,OCAI : DEVICE-BE(16:23) ifMA31=0
DEVICE-BE(24:31) if MA31 =1
OCAX
Same as OCA
then (RLClO:15)04-PAGE ADDRESS
OCRA
Resul ting flags
CV GL
o 0 0.0
o1 o0
Normal Execution
Instruction Time-Out
Programming Note
The S field is not used and should be NULL selected.
Execution Times
OCA,OCAX,OCAI,OCRA:
05-058A1l5 ROO 5/75
1280
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
[ not be used for any other purpose unless specifically euthorized in writing.
77
6.2.S Output Command
OC
S,B,I,E,D,MC
0
3
010
10 1
010
5 6
I, I
3
5 6
100
I, I
OCI
3
5 6
I 010
110
II I
0
010
16
I 11111 I
20
001 1
I
25
B
1
26 27 28
0 IE
16
11
s
I1 1 1 1 1 I
20
001 1
I
B
31
Ie I
PAGE ADDRESS
=1
[RR IMMEDIATE]
16
11
S
I
11111
I
20
001 1
31
I
16
11
S
J
DATA
[RR CONTROL]
5 6
I01 II I
31
MC
25 26
S,B,I,E,D,MC
3
I
0
1
[RR TRANSFER]
S,B, DATA, I
0
OCR
11
S,B,ADRS,I,C
OCX
0
[RR CONTROL]
111111
I
25 26 27 28
20
001 1
I
B
11
IE1
0
1
31
MC
l
The Output Command instructions are identical to the Address and Output Command instructions except that the address
cycle is avoided.
Execution Times
OC,OCX,OCI,OCR
78
580
This information is proprietary and is ,upplied by INTEADATA for the .ole
purpose of using and maintaining INTEADATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
6 . 2.6 Address and Read Data
RDA
0
S,A,B,I,E,D,MC
3
5 6
gl II
1
RDAX
0
11
I
S
20
16
I
A
1000
1
s
B
f;
12:
S,A,B,ADRS,I,C
3
[~o
RDRA
0
[RR CONTROL]
5 6
II
S,A,B,I,E,D,MC
3
5 6
~IIII
I
16
A
1
1
20
I
1000
31
25 26
B
Ic_1
I
PAGE ADDRESS
[RR CONTROL]
11
S
31
MC
[RR TRANSFER]
11
S
I:r
16
I
A
20
1000
1
31
25 26 27 28
·B .....--
II 1
E 1D
1
MC~
The register specified by A contains the device address. The device is addressed and a single 8-bit data byte is transferred
from the device to the register specified by S.
RDA:
(SO:15) ... 0
(S16:23)+-DEVICE DATA
(S24:31) +-BE(24:31)
(S 16 :23) --BE( 16 :23)
(S24:31)+-DEVICE DATA
1
IfMA31 = 0
}
If MA 31 = 1
RDAX:
Same as RDA
then (RLClO:15) ...--PAGE ADDRESS
RDRA:
(SO:15) +-0
(S16:23}+-BE(16:23)
(S24:30+-DEVICE DATA
Resulting flags
CV GIl.,
o 0 o 0 Nonnal Execution
o 1 00 Instruction Time-out
Execution Times
RDA,RDAX,RDRA
05-058A1:5 ROO 5/75
1180
This information is proprietary and i. supplied by INTERDATA for the sale
purpose of using and maintaining I NTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
79
6.2.7 Read Data
[RR CONTROL]
S,B,I,E,D,MC
RD
a
010
3
S 6
10 1
II I
010
S
I
11111
I
2S
20
0000
I
B
I0I I I
E
100
III
S
16
111111
I
25
20
a
3
0000
I
B
010
101 II I
S
31
II
I
PAGE ADDRESS
c
[RR CONTROL]
11
5 6
I
MC
26
S,B,I,E,D,MC
RDR
D
[RR TRANSFER]
11
S 6
3
31
26 27 28
S,B,ADRS,I,C
RDX
a
16
11
20
16
111111 I
0000
I
31
25 26 27 28
B
11
I II
E
D
MC
I
The Read Data instructions are identical to the Address and Read Data instructions except that the address cycle is
avoided.
Execution Times
RD,RDX,RDR
80
480
This information is proprietary and i. supplied by tNTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment end shall
not be used for any other purpose unless specifically authorized in writing.
OS-058A15 ROO 5/75
6.2.8 Address and Write Data
WDA
0
010
S,A,B,I,E,D,MC
3
10
0
3
S
WDAI
A
I
S
20
100 1
I
16
11
A
I
I
25 26 27
B
I
III
E
3
WDRA
25
11
I
S
B
31
II
c
I
PAGE ADDRESS
16
A
I
31
20
100 1
I
11
I
S
~
DATA
[RR CONTROL]
5 6
elII
I
MC
26
S,A,B,I,E,D,MC
3
D
[RR IMMEDIATE]
5 6
I
31
28
[RR TRANSFER]
20
100 1
10
S,A,DATA,I
LOIO~ I I
0
I
5 6
II
16
11
S,A,B,ADRS,I,C
~
0
5 6
II I
WDAX
[RR CONTROL]
16
A
I
20
100 1
I
25 26 27
B
II I I I
E D
31
28
MC
~
The register specified by A contains the device address. The device is addressed and a single 8-bit byte is transferred to the
device.
WDA,WDAI
WDAX
DEVICE40-BE(16:23) ifMA 31=0
DEVICE+-BE(24:31) ifMA 31=1
Same as WDA
then (RLCI0:15)+---PAGE ADDRESS
WDRA
DEVICE+-BE(24:31)
Resulting flags:
CV GL
o0 o0
o1 o0
Normal Execution
Instruction Time-Out
Programming Note
The S field is not used and should be NULL selected.
Execution Times
WDA,WDAX,WDAI,WDRA:
05-058A15 ROO 5/75
1280
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
81
6.2.9 Write Data
S,B,I,E,D,MC
WD
0
010
3
101
WDX
0
010
010
3
010
II I
5
100
S
I
16
11111
I
2S 26 27
20
0001
I
B
II I
S
3
5
110
16
I 11111 I
11
S
0001
I
16
11111
I
B
Ie I
I
31
PAGE ADDRESS
I
I
20
0001
31
I
S
I
DATA
[RR CONTROL]
11
5 6
10 1 II
~
25 26
20
S,B,I,E,D,MC
3
MC
[RR IMMEDIATE]
6
II I
I
[RR TRANSFER]
11
6
31
28
10 IE ID
S,DATA,I
WDR
0
11
6
S,B,ADRS,I,C
WDI
0
5
[RR CONTROL]
16
111111
I
25 26 27 28
20
0001
I
B
I I EI DI
31
MC
I
The Write Data instructions are identical to the Address and Write Data instructions except that the address cycle is
avoided.
Execution Times
WD,WDX,WDI,WDR
82
580
This information i. proprietary and Is supplied by INTER DATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically 8uthori%ed in writing.
OS-OSBAI5 ROO 5/75
6.2.10 Address and Read Halfword
RHA
0
S,A,B,I,E,D,MC
3
5
elII
RHAX
0
[RR CONTROL)
11
6
S
I
16
A
I
25
20
I
1 100
B
26 27 28
10 I E I D I
5 6
~ III
16
11
S
I
MC
[RR TRANSFER]
S,A,B,ADRS,I,C
3
31
I
A
I
25
20
I
1 100
B
31
26
Ic I
I
PAGE ADDRESS
The register specified by A contains the device address. The device is addressed and a 16-bit halfword is transferred from
the device to the register specified by S. The Read Halfword instructions can be used with both byte and halfword oriented
controllers. If the controller is byte oriented, the Halfword test line (HW) is inactive. The I/O module inputs two 8-bit
bytes, one after the other. If the controller is halfword oriented, the Halfword test Line (HW) is active. The I/O module
inputs one 16-bit Halfword in parallel.
RHA
(SO:15)-O
(S16 :23) ...... First Data Byte
}
(S24:30~Second Data Byte
(SI6:31)~Halfword of Data
Byte oriented Controller
Halfword oriented Controller
RHAX: Same as RHA
then (RLClO:15)+-PAGE ADDRESS
Resulting flags
CV GL
o0 o0
o1 o0
Normal Execution
Instruction Time-Out
Programming Note
The B field is not used and should be NULL selected.
Execution Times
RHA,RHAX
05-058A15 ROO 5/75
1400
1180
Byte oriented device
Halfword oriented device
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83
6.2.11 Read Halfword
0
010
3
010
11
6
10 1
II I
I
S
11111
16
I
0100
I
B
10
3
00
1
5
6
II
I
31
28
25 26 27
20
IE I I
D
MC
J
[RR TRANSFER]
S,B,ADRS,I,C
RHX
0
[RR CONTROL]
S,B,I,E,D,MC
RH
11
S
111111
16
I
0100
I
31
25 26
20
B
Ic I
PAGE ADDRESS
I
The Read Halfword instmctions are identical to the Address and Read Halfword instructions except that the address cycle
is avoided.
Execution Times
RH,RHX
84
700
480
Byte oriented device
Halfword oriented device
This information is proprletory and is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not b. used for any other purpos~ unless specifically euthorlzed in writing.
05-058A15 ROO 5/75
6.2.12 Address and Write Halfword
WHA
0
S,A,B,I,E,D,MC
3
~
0
11
S
16
A
1
I
24
110 1
I
25 26
B
1
00
1
11
S
I 1
DI
I
MC
[RR TRANSFER]
5 6
I
31
27 28
01 E1
S,A,B,ADRS,I,~
3
G
5 6
10 1 1I 1
WHAX
[RR CONTROL]
I
16
A
20
110 1
1
31
25 26
lei
B
1
PAGE ADDRESS
I
The register specified by A contains the device address. The device is addressed and a 16-bit Halfword is transferred from
the Processor to the device. The Write Halfword instructions can be used with either byte or halfword oriented controllers.
If the controller is byte oriented, the Halfword test line (HW) is inactive. The I/O module outputs two 8-bit bytes, one
after the other. If the controller is halfword oriented, the Halfword test line (HW) is active. The I/O Module outputs one
16-bit halfword in parallel.
WHA
: DEVICE+-BE(16:23)}
.
DEVICE..--BE(24:31) Byte onented controller
DEVICE4-BE(16:31)
Halfword oriented controller
WHAX: Same as WHA
then (RLCIO:lS)-PAGE ADDRESS
Resulting flags
CV GL
o0 o0
o 1 o0
Normal Execution
Instruction Time-Out
Programming Note
The S field is not used and should be NULL selected.
Execution Times
WHA,WHAX
05-058A15 ROO 5/75
1740
1280
Byte oriented device
Halfword oriented device
This information is proprietary and is supplied bV INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specificallv authorized in writing.
85
6.2.13 Write Halfword
0
010
[RR CONTROL]
S,B,I,E,D,MC
WH
3
5 6
10 I
II I
16
11
I
S
11111
I
25
20
010 1
I
B
10
IE ID I
0
3
010
00
1
I
S
1
16
11
5 6
II
MC
J
[RR TRANSFER]
S,B,ADRS,I,C
WHX
31
26 27 28
11111
o1 0
1
25
20
1
I
B
Ic
26
31
I
PAGE ADDRESS
I
The Write Halfword instructions are identical to the Address and Write Halfword instructions except that the address cycle
is avoided.
Execution Times
WH,WHX:
Byte oriented device
Halfword oriented device
1040
580
6.2.14 Test Halfword Line and Transfer
THWX
S,B,ADRS,I,C
,~: 1_0~1_:_0~1:~16
__
___S____
[RR TRANSFER]
~I_Il_1_1 1_1_1~1_16
__
1~20~
__
1_1_1_0___
__
B____
L(_:~1_26
____
P_A_G_E_A_D_D_R_E_S_S____
==J
This micro-instruction is provided so that the micro-program can test the state of the Halfword test Line (HW). The
Ha1fword test line is active for as long as any halfword oriented controller is addressed.
THWX:
(RLCIO: 15 )ot--PAGE ADDRESS if C=Q or HW=O
(RLC4: 15)-(RLC4: 15)+1 if C=1 and HW=1
Resulting flags
IclvlalLI
o
0 0 0
Programming Note
The Sand B fields are unnused and should be NULL selected.
Execution Times
THWX
86
(No transfer)
(Transfer)
360
240
This information is proprietary and is supplied by INTEROATA for the sola
purpose of using and maintaining I NTER OAT A supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
7.
INTERRUPT SYSTEM
The hardware priority interrupt structure provides rapid response to internal and external events that require special
program :attention. In the interrupt procedure, the micro-program is steered to a unique Control Store address for each of
the nine possible interrupts.
Certain interrupts can be individually enabled or disabled by bits in the PSW. All interrupts except the Memory Access
Controller can be collectively enabled or disabled by the Branch/Execute and Link and Arm, Branch/Execute and Link and
Disarm micro-instructions. Intenupts are automatically armed when a micro-instruction specifies the decode option so that
interrupt service can occur before starting the next user instruction. The interrupts are then dis-armed into the subsequent
emulation sequence until specifically armed by the micro-program.
When an interrupt occurs, the micro-instruction at its respective trap location is executed. The RLC is not changed so that
the micro-program could return to the interrupted program sequence if desired. The standard Model 8/32 micro-program
does not use this capability.
The interrupts with pertinen t enabling PSW bits and trap locations are shown in Table 2. The descriptions that follow are
oriented towards the emulator.
7.1 Internal Interrupts
Seven different internal interrupts may be generated. Of these, the Fixed-Point Divide Fault, Floating-Point Arithmetic
Fault, Queue Service, and Supervisor Call are created by the emulator and consequently do not have dedicated trap
addresses. The remaining three- Illegal Instruction, Memory Access Controller, and Machine Malfunction - are generated
in the hardware.
7.1.1 Illegal Instruction: Interrupt. The Illegal Instruction Interrupt is generated when an instruction not in the
user level instruction repertoire is attempted or when execution of a "Privileged Instruction" is attempted and PSW Bit 23
is set.
As a result of an Instruction Read, the main memory gates its read-out into the user's Instruction Register (lR). When the
Decode (D) option is also specified, at the conclusion of the present micro-instruction, the Processor waits until the next
user-instruction is available in IR, at which time the Prtvileged/Xllegal ROM is interrogated.
The Privileged/Illegal ROM is addressed by the Operation Code field of IR (lR Bits 0:7). There is a four-bit data entry in
the Privileged/Illegal ROM for each of the 256 possible user op-codes.
The occurrance of the Illegal Instruction Interrupt causes the micro-instruction at Control Store location '208' to be
executed.
7.1.2 Memory Access Controller Interrupt. The Memory Access Controller Interrupt, enabled by Bit 21 of the
PSW, occurs when the currently runmng program vlOlates any of the relocation and protection conditions in the Memory
Access Controller. In response to the Memory Access Controner Interrupt, the micro-instruction at Control Store location
'201' is executed for a data violation.
In addition, following an Instruction Read and Decode specification, if the instruction fetched is from a location that is
identified as invalid, nQn~present or execute protected by the Memory Access Controller, the op-code field of IR is jammed
to X'FF'. In this circumstance, op-code 'FF' is not interpreted as illegal, but rather as cause for a Memory Access
Controller Interrupt. When this occurs, the instruction at 'I FEU is executed in response to the Decode (D) option.
7.1.3 Machine Malfunction Interrupt. The Machine Malfunction Interrupt, enabled by Bit 18 of the PSW,
occurs on Memory Parity Errors or Early Power Fail detect. 'fhe emulator also generates a Machine Malfunction Interrupt
on Powe:r Up if PSW Bit 18 is set.
Specifically, the Machine Malfunction Interrupt occurs if any of the right-most three bits of the Machine Control Register
(MCR) are set. See Table 4.
In response to the Machine Malfunction Interrupt, the micro-instruction at Control Store location, '205' is executed.
Early Power Fail
The Early Power Fail bit sets if the Power Fail Detector determines that the primary line voltage is low, or when the
Initialize key is depressed or the key-operated Power switch is turned to the off position. When any of the above events
occurs, a one millisecond timer is started and the Early Power Fail bit in MCR is set. The user program may do any
necessary system shutdown procedures during this one millisecond interval. PSW Bit 18 may again be set to look for parity
errors Olr to prepare for the interrupt on Power Up. The Early Power Fail interrupt will not re-occur.
05-0S8AIS ROI 5/76
This information is proprietary end is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
87
I
At the end of the EPF one millisecond time-out, the Primary Power Fail (PPF) interrupt is generated. In response to the
Primary Power Fail interrupt, the micro-instruction at Control Store location '206' is executed. This instruction is a branch
to a micro-routine that saves the PSW and LOC and all the user's registers. After this, a Power Down (POW) micro-instnction is executed which releases the System Clear relay, holding the system in an initialized state until power is restored.
If all interrupts had been collectively disabled by the micro-program when the PPF signal occurred, after another one
millisecond interval, the hardware automatically releases the System Clear relay, initializing the system.
Memory Parity Error
If the Memory Parity option is present, the parity bit of each halfword in main memory is set or reset to maintain odd
parity. The parity bit is generated on every Data Write and checked on every Instruction Read or Data Read. If a parity
error occurs on an Instruction Read or on a Data Read, one of the Memory Malfunction bits in MCR is set.
If enabled by PSW Bit 18 and armed by the micro-program when the current micro-instruction is finished, the Machine
Malfunction Interrupt is taken.
7.2 External Interrupts
If individually enabled by the user, a peripheral device controller is allowed to request Processor service when the device
itself is ready to transfer data. The Processor has five priority interrupt lines related to peripheral device handling. These
are Display Console requests, and Interrupt requests occurring on Interrupt Lines 0:3. Whenever an External Interrupt
occurs, it remains pending until the Processor recognizes and services the interrupt.
7.2.1 Display Console. The Display Console generates an interrupt when an Address, Memory Read, Memory
Write, Examine RegIster, or Examine Floating-Point Register operation is initiated from the console or when a function is
selected, or Single Step or Run Mode is selected. The occurrance of any of the above causes the signal CATN to go active.
Selecting Single Step also causes the signal SNGL to go active.
The signal CATN remains active until the Display Console is addressed by the micro-program. The signal SNGL remains
active until a different operation is selected. The CATN and SNGL signals are copied in the Machine Control register so
that the micro-program can distinguish between the two signals.
The Display Console interrupt is only tested during the Decode option of a micro-instruction. The implication is that a
console interrupt can only be serviced at the end of a user's instruction. When the console interrupt is taken, the
micro-instruction at Control Store location '204' is executed.
The Branch and Disable Console Interrupt micro-instruction momentarily disables the Console Attention or Single Step
signal so that lower priority I/O interrupts can be examined. The interrupt is only disabled for this one micro-instruction.
7.2.2
Attention. The four I/O Attention lines are processed in the priority shown below:
Priority
First
Second
Third
Fourth
Atten tion Line
o
1
2
3
PSW Bits 17, 20, 26, and 27 affect the enable status of the four I/O Attention lines as shown in Table 3. The emulator
handles I/O Interrupts in one of two manners, depending upon data in main memory.
8.
INSTRUCTION EXECUTION
User instructions are maintained in the main memory. The user instruction to be executed next is at the Main Memory
address specified by the Location Counter (LOC). The micro-program begins to emulate that user instruction by doing an
Instruction Read. On the same micro-instruction or on a subsequent micro-instruction, the Decode option is specified.
Because the micro-program need not specify Instruction Read and Decode in the same micro-instruction, the instruction
fetch is discussed in two phases.
8.1 Instruction Read
In response to an Instruction Read, the halfword whose address is in the Location Counter is fetched and placed in the
user's Instruction Register (lR). Loading IR has no immediate affect on the YD and YS registers. These registers are not
modified until the Decode option is specified so that the micro-program can continue using YD and YS for selecting the
user's registers. See Figure 1.
88
This information i. proprietary and i. supplied by INTEROATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purposa unless specifically authorized in writing.
05-058A15 ROO 5/75
At the same time that the user~s Operation Code is loaded into IR, a decision is made, based on Bit 1 of the first nalfword,
whether or not additional halfwords must be fetched from memory to make up the complete instruction won!. As soon as
the IR is filled, the Format ROM is interrogated to determine the instruction format. The format ROM is a separate
Read-Only-Memory containing 256 4-bit words, one word for each possible user level operation code. The nature of the
data in 1the format ROM is shown below.
1 0 o0
o0 oI
oI o0
o0 1 0
RX format
Rli format
RI2 format
RR or short format
0 10 10 10 Undefined
•
The user level instruction formats are shown in Figure 3.
REGISTER TO REGISTER (RR)
0
7 8
t=
I
Op
11 12
15
I
Rl
I
R2
SHORT FORMAT (SF)
0
7 8
L
Op
1
11 12
Rl
15
N
1
1
REGISTER AND IMMEDIATE STORAGE (RIl)
0
t=
7 8
I
Op
11 12
Rl
15 16
I
X2
1
12
REGISTER AND IMMEDIATE STORAGE (RI2)
0
t=
7 8
Op
__
11 12
~_~
I
I
Rl
47
15 16
X2_
_
~_~
I
__
._I2~~Lj
REGISTER AND INDEXED STORAGE (RXl)
7 8
0
t=
I
Op
11 12
15 16 17 18
I
Rl
X2
10 '10
1
D2
REGISTER AND INDEXED STORAGE (RX2)
7 8
0
I
Op
C
I
RI
31
15 16 17
11 12
X2
11
I
D2
REGISTER AND INDEXED STORAGE (RX3)
o
7 8
11 12
---.1--1R _ I
C_O_p
15 16 17 1'8 19 20
23" 24
I
_FX2____0--,---,-111---,---",0
10 l_sx2-,---,1
'"""'--:-1
Figure 3. User Level Instruction Formats
05-058A15 ROI 5/76
This information is proprietary and is suppliad by INTERDATA for the sale
purpose of using and maintaining I NTER DATA suppliad equipment and shall
not be u,ad for any other purpose unloss specifically authorized in writing.
89
The Processor knows from the output of the format ROM and from Bits 16 and 17 of the second halfword, if a third
halfword, for RX3 and Rl2 formats, is required.
The hardware automatically fetches the appropriate number of halfwords so that after the instruction read is performed,
the user's Instruction Register contains the most significant 16-bits of the instruction and the Memory Data Register
(MDR) contains the information shown on Table 8. However, when the micro-program attempts to unload MDR to the B
Bus, the data shown on Table 9 is received instead of the actual MDR.
TABLE 8. STATE OF MDR AFTER INSTRUCTION READ
INSTRUCTION
CONTENTS OF MDR
FORMAT
0
RR or SF
RIl
RI2
RX1
31
UNDEFINED
I
I
0
15 16
31
I 12 FIELD OF INSTRUCTION I 12 FIELD OF INSTRUCTION I
0
31
12 FIELD OF INSTRUCTION
I
I,0.1 2
31
.1617.18
1010lD2 FIELD OF INSTRUCTION
o1
RX2
RX3
I
31
3 4
10100
I
7 8
SX2
I
D2 FIELD OF INSTRUCTION
D2 FIELD OF INSTRUCTION 111
111
0
I
D2 FIELD OF INSTRUCTION
10 10
16 17
31
I
A2 FIELD OF INSTRUCTION
j
TABLE 9. B BUS GATING AFTER INSTRUCTION READ
STATE OF B BUS WHEN UNLOAD MDR
INSTRUCTION
FORMAT
0
RR or SF
I
I
31
UNDEFINED
0
RIl
EXTENDED SIGN
0
RI2
I
I
I
I
0
RX3
90
I
12 FIELD OF INSTRUCTION
ZERO
1
II
I
0
31
D2 FIELD OF INSTRUCTION
16 17
EQUALS BIT 17
I
31
16 17 18
0
RX2
31
'12 FIELD OF INSTRUCTION
0
RX1
1
15 16
31
D2 FIELD OF INSTRUCTION
CONTENTS OF REGISTER SELECTED BY SX2
This information is proprietary and is supplied by INTER DATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specificelly authorized in writing.
I
1
31
1
05-058A15 ROO 5/75
For the Register and Immediate Storage-RIl-format, Bits 0: IS of MDR are set equal to the sign bit of the halfword in
Bits 16:31. For the RXI format, Bits 0: 16 of MDR are zero. For the RX2 format, Bits 0: 16 of MDR are set equal to Bit
17. For the RX3 format, until a micro-instruction is performed that loads the Memory Address Register (MAR), any
reference to MDR as a source will cause the contents of the General Register whose address is in the SX2 field of the
instruction to appear on the B Bus instead of MDR. See 8.3.
8.2 Decode Option
In response t-_Y_E_S_ _~ LOOP TIL ALL
4 SETS LOADE
(MAR) ...
(LOC)'" (MDR)
PRIVILEGED READ HALFWORD
(MDR)+---(MDR' '~OFF'
PRIVI LEGED WRITE HALFWORD
--jf
ZERO
SET
LDLOOP
.. DRl +-- (MDR)
(MAR)+---(MAR + 4
MEMORY READ FULLWORD
Rl FIELD+--Rl FIELD4(MR1)
NO
NO
ADDRESS THE
DISPLAY
SET
(MAR)"'O
MEMORY READ FULLWORD
(MR1)'" 'FFFFFFF2'
.. DRl =
DOUBLE PRECISION FLOATING POINT REGISTER
SPECIFIED BY Rl (32 BITS)
.. ERl
SINGLE PRECISION FLOATING POINT REGISTER
SPECIFIED BY Rl (32 BITS)
=
MMFINT
TWAIT
LOCDIS
Figure 4. Power Up (Continued)
94
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpoo;e unless specifically authorized in writing.
05-058Al5 ROl 5/76
If the LSU is present, the micro-program proceeds to read the first eight bytes of data from the LSU. The nature of this
data is as follows:
First two bytes
Second two bytes
Third two bytes
Fourth two bytes
Least significant
Least significant
Least significant
Least significant
l6-bits of a new PSW
l6-bits of a new LOC
l6-bits of a start address
l6-bits of an end address
The most significant l6-bits of PSW and LOC are set to zero. As a consequence, the Location Count value can only address
a location within the first 64 KB of main memory. The start and end addresses identify an area in the first 64KB of main
memory to be loaded with the' ninth and successive bytes of data from the LSU.
If the start address is initially greater than the end address, the IDLE Loop is entered. Otherwise, data bytes are read from
the LSU and stored at successive byte locations in main memory. The start address is incremented by one for each byte
read. Reading continues until the start address becomes greater than the end address, at which time routine TWAIT is
entered"
Routine POWRUP. Routine POWRUP is entered after power-up if no Loader Storage Unit is present. The halfword PSW
save pointer is fetched from absolute address '84' and set aside in Micro-Register 4. Note that after doing a halfword main
memory read, the halfword sign bit is propagated through the most significant 16 bits in MDR, necessitating 'ANDing' the
full word with' 0000 FFFF' to keep the resultant address within the first 64 KB of main memory.
The halfword General Register save pointer is fetched from absolute address '86' and copied into the Memory Address
Register (MAR). The register save pointer is the starting address in the first 64 KB of the General Register save area.
General Register Set a is restored, followed by Register Set 7 or Register Sets 1 through 7 depending on the state of MCR
bit 9. Then if MCR bit 4 is set, the 8 Double precision floating point Registers are restored from memory locations
immediately following the General Register Save area. After this, the eight even-numbered floating-point registers are
restored from absolute addresses 00 through 1F .
The saved PSW is fetched from the address retained in Micro-Register 4 and set aside in Micro-Register 1. The saved LOC is
fetched from the address plus four contained in MR4. The PSW and LOC are then restored.
-:* The byte location
at absolute address 28 is reset, then the saved Console status byte at absolute address 29 is fetched
and examined. If the console was not in the RUN mode before power went down, or if the initialize switch on the console
is depressed, the display is addressed and routine LOCDIS is entered. If the display was in the RUN mode, the Machine
Malfunction enable bit in PSW (PSW18) is tested. If set, routine MMFINT is entered. If reset, the user instruction whose
address is in LOC is fetched and executed unless the WAIT bit (Bit 16) of PSW is set, in which case routine WAIT is
entered.
9.2 Interrupt Support
Routine MMFINT. Routine MMFINT, shown on Figure 5, is entered when a memory parity error or an early power failure
is detected or if, after the normal power up sequence, the micro-code determines that the display had been in the Run
mode before power went down and the Automatic Restart option is present and PSW Bit 18 is set. The PSW is saved in
absolute location '20', the LOC is saved in absolute location '24', and a new PSW and LOC are fetched from absolute
locations '38' and '3c' respectively. The least significant three bits from the MCR are 'ORed' into the Condition Code field
of the new PSW, and routine TWAIT is entered.
Routine TWAn. This routine tests the WAIT bit of the current PSW (PSWI6). If set, the WAIT loop is entered. If reset, the
user instruction whose address is in LOC is fetched and executed.
WAIT Loop. The WAIT loop is a high speed loop consisting of a single micro-instruction branching to itself. The interrupts
are collectively armed and the occurrance of any interrupt will cause the micro-instruction at its respective trap location to
be executed.
Also shown on Figure 5 is a Common Interrupt routine (CO MINT) shared by Memory Access Controller interrupts, Illegal
Instruction interrupts, Arithmetic fault and Queue Service interrupts. The routine fetches a new PSW and LOC from
dedicated memory locations then saves the old PSW and LOC in General Registers 14 and 15 respectively of the register set
selected by th(~ new PSW.
The three instmctions capable of causing a System Queue interrupt are also shown on Figure 5. These are LPSW, LPSWR
and EPSR. After performing the instruction, Routine TESTI is entered. There the number of slots used, halfword at the
absolute address plus two of the full word address contained in absolute location '80', is examined. If the halfword is zero,
routine TWAIT is entered. If non-zero, the system queue is not empty. A new PSW and LOC are fetched from absolute
location '88'. The old PSW and LOC are saved in General Registers 14 and 15 of the register set selected by the new PSW
and the address of the System Queue is saved in General Register 13.
05-058A15 ROI 5/76
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
95
I
I
MACHINE
MALFUNCTION
ILLEGAL
INSTRUCTION
MACINT
(MR1)" '90'
I'
MMFl
(MAR) .'20'
(MDR)'" (PSW)
PRIVI LEGED WRITE FULLWORD
(MAR)'" '24'
(MDR)'" (LOC)
PRIVILEGED WRITE FULLWORD
(MAR). '38'
PRIVILEGED READ FULLWORD
(MAR) .'3C'
(PSW) ... (MDR)
SENSE MCR
CC· MCR12:15
I
CQMINT
(MRO)"'O
I~·~C-O-M--IN-O--------------------~
(MR2)'" (PSW)
(MAR)'" (MR1)
PRIVILEGED READ FULLWORD
(PSW) ... (MDR)
~
I~:~O-M--IN-l---------------------~
(MAR)" (MAR) + 4
PRIVILEGED READ FULLWORD
REG 14"'(MR2)
REG 15" (LOC)
(PSW) ..... (PSW) V (MRO)
(LOC) "'(MDR)
MCR"'O
(PSW) ... (PSW) V (MRO)
(LOC)" (MDR)
G)
ILLEGAL
(MR1)" '30'
t
I
~
RESET WAIT INDICATOR
SET
RESET
INSTRUCTION READ
DECODE NEXT
~
SET WAIT INDICATOR
~
ARM INTERRUPTS
"WAIT LOOP"
Figure 5. Interrupt Support
96
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTEROATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
IF DFU
IF NO DFU
~~ALTO
R1 ...
Y,FAULT
(jijiROl
I
FFAULT
--
R1 ... (MRO)
R1+1""(MR1)
~ ______________~
YES
I!~
(MRO)·.. O
(MRO)'" R1V '7FFFFFFF'
I
R1'" (MRO)
QEINT
FFALTI.
(MRO)"'S
I
(MR3)'" (MDR)
(MAR)'" (MDR) + 2
PRIVILEGED READ I-IALFWORD
(MR2)'" (PSW)
l·FAULT
( MR1)""3S'
YES
SET
NO
'S8'
(MRO) ... 0
PRIVILEGED READ FULLWORD
(PSW) ... (MDR)
REG 13'" (MR3)
FlESET
(LOC)"'(LOC) + LENGTH
(MAR)~
DECODE NEXT
~
COMINO
__
LP
...S_WJ
SUBROU~
~
(MR3)'" R2
(LOC)'" R2+1
(PSW) ... (M R3)
RD FU I=-=----.J
..b~
(MR3) ... (MDR)
(MAR)"'(IVIAR) +4
MEMORY READ FULLWORD
(PSW) ... (MR3)
(LOC)'" (MDR)
COMIN1
R1'" (PSW)
(PSW) ... R2
I
~--~~----------~
TESTl
(MAR)'" 'SO'
RESET
L_ _-"
SET
PRIVILEGED READ FULLWORD
6
TWAIT
QUEINT
Figure 5. Interrupt (Continued)
05-058A15 ROI 5/76
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
97
9.3 Console Support
The Routine CONSER handles all the console service functions. This routine is entered when a Console Attention is
generated, or at the conclusion of a user level instruction if the signal SNGL is active. (Refer to Figure 6.)
RESET WAIT INDICATOR
ADDRESS THE DISPLAY
OUTPUT COMMAND NORMAL
ADDRESS THE DISPLAY AGAIN
AND SENSE STATUS
(MR2) +-STATUS BYTE
ROTATE STATUS BYTE
IN (MR2) LEFT ONE PLACE
(MAR) '29'
PRIVILEGED READ HALFWORD
(MR4)+-(MDR)
(MDR 24:31 )+-( MR2 24:31)
PRIVILEGED WRITE HALFWORD
SET
FNDIS
SET
ADRMW
READ SWITCH REGISTER
(MDR)+ (DATA)
SET
MEMORY READ HALFWORD
MEMORY WRITE HALFWORD
SET
DISMEM
(MRO) + (MDR) .'OOOOFFFF'
(LOC)+ (LOC) + 2
RESET
( MROOO:15)+ (LOC16:31)
(MR1 28:31)+ (LOC12:15)
~
(PSW16)+ 0
RESET WAIT LAMP
(MR1) .... (MR1) V '80'
OUTDIS
ADRS
(LOC)- (MDR ~FFE'
(LOC12:15)+ (MR2 28:31)
6
LOCDIS
Figure 6. Console Support
98
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not ba used for any other purpose unless specifically authorized in writing.
05-058A15 ROt 5/76
c;lDIS
R1 IFIELD. (MR2)
<
SET
RESET
(MRO). R1
(MR1)''''20' + R1 FIELD
<
RESET
RESET
(MRO)4" FLOAT REG. R1
(MR1)''''10' + R1 FIELD
NO
IF FN2 in affect
Show Single Precision
IF FN3 in affect
Show half of a
Double Precision
Register.
Decision based
on (MR4), last
Status Byte
FNQ 123
YES
LOCDIS
(MRO) .... (LOC)
(MR1) .... '45'
8~-----~--=O:-:U=T=D7:IS:--------l---------·---L-----_----J
DISPLAY BYTE D1. (MR024:31)
CLRWT
DISPLAY BYTE D2· (MR016:23)
17 OR 20 SET
DISPLAY BYTE D4+(MROOO:oi)
BYTE LOCATION '0078'
--r- (M R224:31)
DISPLAY BYTE D.5 .... (MR1 24 : 31 )
8
·I~
SET WAIT LAMP
-0
0
YES
READ SWITCH REGISTER
(PSW) .... DATA
DISPLAY BYTE D3+(MR008:15)
(DEV).1
(LEVEL)·O
I
A'
M
\..:)
LO~
~IOINTX
CONSER
CLRWT
PPFINT
Figure 6. Console Support (Continued)
05-058AlS ROl 5/76
hiS information is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
~
99
The WAIT indicator on the console is reset, the display controller is addressed and the status sensed. The status byte is
copied into Micro-Register 2 and rotated left one position so that MR2 Bits 24:31 have the following significance:
I
27
X
X
X
X
Run
Memory Write
Memory Read
Address
24
0
0
0
0
25
0
0
1
1
26
0
1
0
1
Fixed Register
Floating Register
Function
1
1
1
u
U
1
0
0
1
1
0
0
28 29 30 31
X X X X
X X X X
X X X X
MS4
ADDRESS BITS
REGISTER NU.
REGISTER NO. } Single or Halt
FUNCTION NO.
MR2 is saved in the absolute byte location 29 so that the power-up sequence can determine what mode the console was
last placed in before power down.
The status byte in MR2 is then examined. If status Bit I is set (status Bit 1 corresponds to MR2 Bit 24), a register has been
selected for display or a function has been selected. Routine FNDIS is entered. If status Bit 1 is reset, Address, Memory
Read, Memory Write or Run mode has been selected. If Address or Memory Write, the least significant 16 switch register
bits are read into MDR. If it is 'Memory Write', the halfword in MDR is written into the main memory location whose
address is the contents of LOC. Routine DISMEM is entered.
If Address, Bits 28: 31 of MR2 are appended to the top of the halfword in MD R, becoming Bits 12: 15 of the new location
count value. This 20-bit address is forced even and copied to LOC. Routine LOCDIS is then entered.
If the status was Memory Read, the halfword whose address is the contents of LOC is read and Routine D [SMEM is
entered.
Routine DISMEM increments LOC then packs MRO and MR1 with the contents of MDR and LOC. Routine OUTDIS is
then entered.
Routine FNDIS determines if the selected function is legal. The only legal functions are 0, 1, 2,3, 4 and 5. If the function
is illegal, Routine LOCDIS is entered. If the function is zero, and PSW Bit 17 or 20 is set, an interrupt from Device Number
1 is simulated through Routine 10INTX. If the function is one, the least significant 16 switch register bits are copied into
the least significant 16-bits of PSW. The most significant 16-bits of PSW are unchanged. Routine PSWDIS is then entered.
If the function is 2 or 3, (MR2) is saved in byte. location 00028 and LOCDIS is entered. If the function is four, Routine
PSWDIS is also entered. There, the current PSW is copied to MRO and MRI is set to .44 . Routine OUTDIS is entered.
I
If the function is five, routine LOCDIS is entered. There, the current LOC is copied to MRO, and MRI is set to '45'.
Routine OUTDIS is entered.
I
Routine OUTDIS writes the contents of MRO and MR1, a total of five bytes, to the display.
Routine IDLE sets the WAIT indicator, then the high-speed Idle loop is entered. This loop can only be exited if a
power-fail is detected or another console attention is generated. If a power-fail occurs, routine' PPFINT is entered. If a
console attention is detected, MCR Bit 7 is tested. If reset, the console is not in single mode. The micro-program re-enters
routine CONSER. If MCR Bit 7 is set, the console is in single step mode. Routine CLRWT is entered.
Routine CLRWT resets PSW Bit 16, the wait bit, and an instruction read is performed from the address specified by LOC.
9.4 I/O Interrupts (Refer to Figure 7.)
The occurrance of one of the four I/O Interrupts causes the micro-instruction at the respective trap location to be
executed. Register "LEVEL" is set equal to the number of the interrupt line and the interrupt is acknowledged. The
returned device number is placed in register "DEV" and Routine 10lNTX is entered.
The device number in "DEV" is masked to the least significant 10 bit~. It is then doubled and added to X'DO', forming the
address of the appropriate interrupt service pointer. The halfword service-pointer table entry is fetched. The current PSW is
set aside in register "TEMP", then Bits 18 and 20 are set and all others reset. The register set number specified by register
"LEVEL" is copied to the register set select field of PSW. General Register 0 of the newly selected set is set equal to the
old PSW; General Register 1 is set equal to LOC, and General Register 2 is set equal to the device number. The device is
addressed and a sense status is performed. The device status byte is copied to General Register 3. The service-pointer table
entry, in MDR, is copied to LOC and the least significant bit is examined. If reset, an "immediate interrupt" is to be
performed. The user instruction whose address is LOC is fetched and executed. If the least significant bit of the servicepointer table entry is set, the service-pointer is the address in the first 64 KB of a Channel Command Block (CCB). Routine
CHANEL is entered.
100
This information i. proprietary and is suppliad by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be usad for any other purpose unle.. specifically authorized in writing,
05-058A15 ROt 5/76
~
~
(LEVEL) .. '00'
~
(LEVEL) .. "11'
~
(LEVEL) ... '22'
(LEVEL) ... 'FF'
~----~1~·-------~~-----~1
ACKNOWLEDGE INTERRUPT
ON APPROPRIATE LINE
(DEV) ... DEVICE NUMBER
8-
·IIOINTX
(DEV) ..... (DEV) • '3FF'
(OAT)" (DEV) + 'DO'
(MAR)'" (OAT) + (DEV)
PRIVILEGED READ HALFWORD
(TEMP). (PSW)
(LEVEL)'" (LEVEL) .'FO'
(PSW) .. (LEVEL) V'2800'
REGISTER 0" (TEMP)
REGISTER 1. (LOC)
REGISTER 2" (DEV)
ADDRESS THE DEVICE
AND SENSE STATUS
REGISTER 3 ... STATUS BYTE
(LOC). (MDR) .'OOOOFFFE'
RESET WAIT lAMP
I
CHANNEL
(MAR). (LOC)
MEMORY READ HALFWORD
REGISTER 4'" (LOC)
(CCW) ... (MDR)
NO
I
CC= 0
~
CC= 2
(OAT) .... STATUS MASK
EXSUB1
SET
NOT
ZEH~
S
EXSUB2
"BAD STATUS"
RESET
REA~
N0--GNFAST
INSTRUCTION
DECODE NEXT
"IMMEDIATE INTERRUPT"
(TEMP). (4) + 2
(MAR)" (TEMP)
MEMORY READ HALFWORD
(MAR)'" (TEMP) + 2
(COUNT)" (MDR)
YES~
UEXAUTO
MEMORY READ FULLWORD
(MAR)" (COUNT) + (MDR)
MEMORY READ HALFWORD
cb
Figure 7. I/O Interrupts
05-058A15 ROO 5/75
hiS information Is proprietary and is supplied by INTERDATA for the lole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
G
101
NO
YES
BYTEIO
~
DEVICE. (MDR)
YES
(MDR). DEVICE DATA
MEMORY WRITE HALFWORD
HRDWT
(COUNT). (COUNT) + 2
(MDR). DEVICE DATA BYTE
MEMORY WRITE HALFWORD
fWRIT
DEViCE ..... (MDR)
COMMON
(MAR) • (TEMP)
(MDR) • (COUNT)
MEMORY WRITE HALFWORD
£!ill.WI.
(COUNT) • (COUNT) + 1
NO
C2SUB2
YES
CC~(1)
EXSUB1
(MAR). (4) + 20
MEMORY READ HALFWORD
(LOC). (MDR) .'OOOOFFFE'
EXAUTO
(LOC). (1)
(PSW). (0)
(MRO). 8
SENSE MCR
YES
MMF1
TWAIT
Figure 7. I/O Interrupts (Contin~ed)
102
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be Uled for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
1
REDCHK
(MAR).(4)+8
MEMORY READ HALFWORD
(TEMP)," (2)
NO
YES
(TEMP) .. (8)
RESET
t NFAST1
SET
(MAR)..·(4)+(TEMP)
MEMORY READ HALFWORD
. ''(TEMP)''-(4)+(TEMP)
(MAR)".(TEMP)+2
(COUNT)·(MDR)
I~
(MDR)"(DAT) E!) (MDR)
MEMOHY WRITE HALFWORD
......---J
RTNCRC
(MAR).(TEMP)
(MDR).(COUNT)+1
MEMORY WRITE HALFWORD
EXAUTO
MEMORY READ FULLWORD
(LOC)+ (COU NT)+(MD R)
(MAH).(LOC)
MEMORY READ HALFWORD
NO
~
YES
NFWRIT
(DAT).(MDR) BYTE
EXAUTO
COMPLEMENT BUFFER
SWITCH BIT
INCCW
(MAR).(4)
(MDR).(CCW)
(DAT)'" DEVICE DATA
SAVE ...... (DAT)
MEMORY ~ HAlFWORD
NO
EXSUB
DEVICE. (DAT)
(MAR)" (LOC)
II
MEMORY IREAD HALFWORD
(MDR).BYTE FROM (DAT)
MEMORY WRITE HALFWORD
(DAT) ... SAVE
•
Figure 7. I/O Interrupts (Continued)
05-058A15 ROO 5/75
hiS information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
~
103
TRANSL
~
(MR1). 'OOOOA001'
(MR6).(DAT) .'FF'
(MR6). (MR6)(f)(MDR)
(MAR). (4) + 16
MEMORY READ FULLWORD
(MR6). (DAT) + (DAT)
(MAR). (MR6) + (MDR)
MEMORY READ HALFWORD
(MR6)".(MDR)
R
(MR6)" (MR6)
1
NO
NO
YES
(DAT)" (MR6).
'~OFF'
YES
(MR6)+ (MR6)G)(MR1)
RETURN
NO
YES
(MDR) .. (MR6)
MEMORY WRITE HALFWORD
RETURN
EXTRAN
(3). (DAT)
CC.O
(LOC)+(MR6) + (MR6)
Figure 7. I/O Interrupts (Continued)
104
This information is proprietary and i. supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not ba used for any other purpose unless specifically authorized in writing.
05-058A15 ROO 5/75
Routine CHANEL can perform a variety of functions, depending upon bits in the Chamlel Command Word (CCW) which is
the first halfword in the CCB. (See Figure 8.)
o
(I
7 8 9 10
STATUS MASK
4
8
10
12
16
20
11
12
C
B
BUFFER 0 BYTE COUNT
IE~
13
14
I -.1 R/W I T I
15
F
Channel Command Word
BUFFER 0 END ADDRESS
CHECK WORD
BUFFER I BYTE COUNT
BUFFER 1 END ADDRESS
TRANSLATION TABLE
ADDRES~
SUBROUTINE ADDRESS
Figure 8. Channel Command Block
The Channel Command Word is fetched and placed in a register labeled CCW. Setting of the Condition Code is enabled and
the 'EXECUTE' bit of CCW is tested. If reset, Routine EXSUBI is entered (the Condition Code is clear), if set, the G flag
sets. The micro-code then ANDS the status mask with the actual device status in General Register 3. If any bit matches, the
status check has failed. Routine EXSUB2 is entered. If the status test is good, the 'FAST' bit in CCW is tested. If not set,
Routine NFAST is entered for 'normal mode' CCB activities. If reset, the Buffer 0 byte count is fetched and copied to
register "COUNT". If the count is already positive, the assumption is that it has not yet been set up, so Routine EXAUTO
is entered. If the count is zero or negative, the Buffer 0 end Address is fetched and added to the count. The halfword
addressed is fetched and the halfword test line is examined. If inactive, routine BYTEIO is entered. If active, a halfword
device controller is addressed. A Read Halfword or Write Halfword, depending upon the state of the R/W bit in the CCW, is
performed and the count is incremented by two. Routine COMMON is entered. At Routine BYTEIO, a single byte is
transferred, the count is incremented by one and Routine COMMON is entered. There, the incremented count is restored
to the CCB and if not positive, Routine EX AUTO is entered. If the count is positive, Routine EXSUBI is entered.
Routine EXAUTO restores PSW and LOC to return control to the point in the user program where the interrupt occurred.
If a Machine Malfunction Interrupt is present, Routine MMFI is entered. If no MALF, the wait bit of PSW is tested. If set,
Routine WAIT is entered; or else the user instruction whose address is LOC is fetched and executed.
Routine EXSUB2 is entered if the device status is improper. There, the L flag in PSW is forced set and Routine EXSUB1 is
entered. There:. the subroutine address from the CCB is fetched and copied to LOC and an Instruction Read is performed.
At Routine NFAST, the buffer switch bit in the CCW is examined to determine which Buffer byte count and End address
to use. The appropriate Buffer byte Count is fetched and copied to Register "COUNT". If the count is already positive,
Routine EXAUTO is entered. If not positive, the byte count is added to the Buffer End address. The halfword addressed is
fetched from main memory.
The R/W bit in the CCW is tested to determine Input or Output. If Output, and the Translate bit in the CCW is set, the
byte to output is first translated by way of subroutine TRANSL. After returning from TRANSL the translated byte is
output to the device and Routine REDCHK is entered. There, depending upon the TYPE bit in the CCW, either a
longitudinal (Exclusive-OR) checksum is performed or a 16th order cyclic redundancy check is perfonned. The result is
returned to the check-word of the CCB. Routine NFRW is then entered.
If input, the data byte is input from the device and saved. If the Translate bit in the CCW is set, the byte is translated by
way of subroutine TRANSL. After returning from TRANSL, the translated byte is stored in main memory. Register DAT
is set equal to the saved un translated byte and Routine REDCHK is entered.
The~count is incremented by one and if not yet positive, Routine EXAUTO is entered. If the count has become positive,
the buffer switch bit in the CCW is complemented and Routine EXSUBI is entered.
9.5 Powe:r Fail Interrupt
In response to a power fail interrupt (PPF), the micro-program enters Routine PPFINT, shown on Figure 9. This routine is
a reversal of the power up routine. The PSW and LOC are saved in their power fail save locations, all sets of General
Registers and, if present, the eight Double Precision floating point Registers are saved in their power fail block of memory
and the eight single-precision floating-point registers are saved at memory locations 1000 I through 101 F : After this, the
Power Down micro-instruction is issued to release the system clear relay and initialize the system.
05-058A15 RO I 5/76
hiS information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
~
105
I
C2F'NT
(MAR) .'84'
PRIVILEGED READ HALFWORD
Rl FIELD.O
(MAR). (MDR) .'OOOOFFFF'
PRIVILEGED WRITE FULLWORD
(MAR) • (MAR) + 4
(MDR). (LOC)
PRIVILEGED WRITE FULLWORD
(MAR). '86'
PRIVILEGED READ HALFWORD
(PSW).O
(MRO). (MDR) .'OOOOFFFF'
(MAR). (MRO) - 4
(MR1). 'FFFFFFF1'
RESET
(MDR)+-DRl
(MAR)+-(MAR) +4
MEMORY WRITE FULLWORD
Rl FIELD+-Rl FIELD + (MR1)
STRLP
(MDR). Rl
(MAR). (MAR) + 4
MEMORY WRITE HALFWORD
Rl FIELD. Rl FIELD + (MR1)
(MAR) .'FFFFFFFC'
(MR1) .'FFFFFFF2'
§I.!!rr.
YES
(MDR). FLT REG:Rl
(MAR)'" (MAR) + 4
MEMORY WRITE FULLWORD
Rl FIELD" Rl FIELD + (MR1)
(PSW). (PSW) + '10'
NO
POWER DOWN
(PSW). (PSW) • '80'
NO
Figure 9. Power Fail Interrupt
106
Thi5 information i5 proprietary and is supplied by I NTER DATA for the 50le
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
05-058A15 ROI 5/76
INTlHDATA MOUlL U/32 MICROPROGRAM 0~-058R02Alj
OPT
SC~l,GO,CRUSS,SQCHK
*
**
~
*
*
COPYRl&Hl INT[RUATA
I~C.
SLPTEMBER,
1
PAGE
197~
SlPTlMblR q~ 1975
IRA bA8-BERT
*
*
* * * * * * * * * * * * * * * * * * * * * * * * * * *
*
PHOGRAM COMPHISLS THl fOLLOWING ROM CHIPS:
**
*
19-1~2HOO~Ol,lY-142ROOF02,19-142R02f03,19-142HOIF04
**
*
**
*
**
*
**
*
*
*
*
*
**
*
*
19-142kOUfU~~19-142RUIFO~~19-142R01~07,19-142HOOF08
19-142ROOFOY,lY-142kOOFI0,19-142ROIFII.19-142ROIF12
19-142ROOf13,19-142ROIF14,19-142ROOF15.19-142ROOF16
000
U01
32H IJO:,
17FD 0000
**
*
*
19-142HOOf25.19-142ROOF26,19-142ROOF27,19-142ROOF28 *
19-1~2HOOf29.19-142ROOf30.19-142ROOF31,19-142ROOF32 *
*
19-1~2RUlf33,lY-142ROlF34.19-142ROOF35.19-142ROlF36 *
19-142HOlf37.1Y-142RUlF38.19-142HOOF39.19-142ROlF40 *
* * * * * * * * * * * * * * * * * * * * * * * * * * **
*
*
*
*
R02
R02
R02
R02
IN ALL CAS~S WHlHl A BRANCH OR TRANSFER COULD OCCUR TO A
LIST!NG PAGl OTHlR THAN THl CURRENT LISTING PAGE. THE TARGET
PAb£ NUMRlH IS SHOWN IN PAKENTHESIS IN THE COMMENT FIELD.
OR AFTER
INITIALIZE. MICRO CODE
EXlCUTION BEGINS AT '001'
GO TO POWER UP ROUTINE (P.43)
ONPOWER~UP.
LI
RALU
MHO.~
TLSU(NULL)
*
* * * * * * * * * * * * * * * * * * * * * * * * * * *
** USLR_LlVLL _~NSIRUClrON lMULATION ENTRY-POINTS
* ~OLLOW. IN KESPONSE TO AN INSTRUCTION READ COMMAND
* THE HARDWAKE, RlADS THE NEXT USER INSTRUCTION FROM
*
*
19-1~2HUOf21,19-1~2ROOF22.19-142ROOF23,19-142ROOF24
*-
_*__
**
ROl.R02
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THE- f'JAINi"lE1"10RY LOCATl_ON_SPEClfIED BY (LaC) .JInlO.*
FUUR UK SIX HYTlS ARE HEAD. DEPENDING UPON THE
*
INSTRUCTION TYP~.
TWICE THE USER'S OPERATION COUE *
IS THt..STAHTINl::i AOQRLSS HJ ROM OF THE APPROPRIATE
*
EMULATION SlQUl~CE.
THE OP-CODE IS SHOWN IN THE
COMMENT FIELU AND THE USER'S MNEMONIC IS THE LABEL. *
* --- ---- ---..--
* * * * * * * * * * * * * *
*
lL
* **** ** * *** * **
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
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ha "~M fnr ::Ionv nfhpr nllrrYK:p Ilnl~~ .::nec:ificallv authorized in writinQ. ,
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83200060
83200070
8620008U
83200090
8320U100
83200110
83200120
83200130
83200140
83200150
83200160
83200170
83200180
8320019U
83200200
83200210
83200220
83200230
83200240
83200250
83200260
83200270
83200280
83200290
83200300
83200310
83200320
83200350
86200340
83200350
832U0360
83200370
832U0380
83200390
83200400
83200410
83200420
83200430
83200440
83200450
832004t)O
83200470
83200480
832.00490
83200500
83200510
83200520
83200530
83200540
832005!lO
83200560
lI\1TEKOAl {\ I'WUE.L R/32 MICKUPKOGKAM
*
*
BALK
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LOAD LOC (P.3)
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06
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(P.28)
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This information is proprietary and is supplied by INTERDATA for the sole
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not be used for any other purpose unless specifically authorized in writing.
83200580
83200590
83200600
63200610
83200620
83200630
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8320065U
83200660
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83200680
83200690
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83200750
83200760
83200770
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832008..30
83200840
83200850
832008bO
83200870
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83200890
83200900
83200910
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83200940
83200950
83200960
83200970
8320U980
83200990
83201000
83201010
83201020
83201030
832010 ... 0
INTlHJATA lViOUlL ,:\/.12 MICIWPHOGKAIV!
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PAGE
3
*
020
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*
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other pur~se unless specifically authorized In writing.
83201060
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83201130
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63201160
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83201190
83201200
83201210
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83201240
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832()1260
83201270
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83201290
83201600
83201310
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83201350
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83201500
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This information is proprietary and is supplied by INTERDATA for the sole
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832U1540
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83201560
63201570
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83201600
83201610
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83201650
83201660
83201670
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83201690
83201700
83201710
83201720
8321.J1730
83201740
83201750
83201760
83201770
83201780
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83201870
83201880
83201890
83201900
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83.201930
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83202000
83202010
83202020
83202030
83202040
83202050
832U2060
83202070
83202080
83202090
83202100
8320211(;
83202120
83202130
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ADD 4 FOR LOC INCRE..MENT
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This information is proprietary and is supplied by INTERDATA for the sole
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83202190
83202200
83202210
83202220
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83202250
83202260
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83202420
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832U2450
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INTEHDA1A \VIUDl.L tl/32 MI.C I{ Ut-' HQGH A\VI
05-058R021\16
PAGE.
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83202550
83202560
83202570
8320258U
83202590
83202600
83202610
83202620
83202630
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83202650
8320266U
83202670
83202680
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832U27bU
83202770
83202780
83202790
83202800
83202810
83202820
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83202840
83202850
83202860
83202870
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83203070
8320308U
83203090
83203100
83203110
83203120
83203130
83203140
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83203200
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83203260
83203270
83203280
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05~05BR02A16
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This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
8320876!J
8320877U
b320878U
83208790
83208800
83208810
PAGE.
UI
23L1 IF60
22F
4Bn H-8U
260
261
232
33'1f- UOO4
3231- OOOl
32H 1000
33';1F 102U
*
*
.::ilKt...t:..
*
cl/!J2. 1"1.1 CtWtJkUbkAi"i
1ll'lL
*+lCl\iULL)
Sl
I"IA~,NULL,4
1'-1 AK= ,
::>1
l"lkl,NULL.14
MR1='F~FFFFF2'
AU
MGK,Yu,NULL,I4DW4
TG1.MKl'YUl.STRt:..E,C
SAVE FLOATING POINT REGISTER
AX
POW
M[;R,NULL
POWER DOWN
Ll
1U2IJ
10U6
1038
L
H8l
L
339~
2h7~
33'::1~
21:lH
63'71-
LI
LI
11)3C
2bl+ 1116U
4AF-F 78M..
4AfF 113CO
2HBU 1800
2B~F 1080
2311
4l(NULL)
-':,':~~~,, _ ,"-,~')IIDr~
lJ!
NULL,l"fR2,'020'
AALNZ ADNMW(NULL),OR2
NI
NULL,MR2,t040'
bALNl [)1 Sl"lll": (NULL)
**
*
2bO
POlk 1 ,1
NULL,NULL
Mk2. I'm I, NULL
MK2 ,I"iK2 , ' F 00'
l"Ik2. I"IK2 • '80 '
Rll
LI
~08U
~L~_2'43Zi,:jJd9.~:
24C
24U
24£
24F
*
CONSER
LI
LWI-F
SSKA
323f- 10U1
4dtl- 61-CO
4A~)1 MCO
32::'2 7F UU
32:.:12 bC80
READ SWITCH REGISTEH 12:19
REAO SWITCH KEGISTEH 04:11
TEST STI\TUS AIT 2
AD[)kESS (P.24)
b62103~O
83210360
8.6210370
8321038U
83210390
83210400
83210410
83210420
83210430
83210440
83210450
B32-104bO
83210470
83210480
83210490
83210500
83210510
83210520
83210530
*
*
'" IUIEl"iOHY WHITl
'* DISPLAY MlMUHY PEGlSTERS
*UISMUJj L
MKO,M[)K
*
257
258
2~9
2~A
2~l3
25C
250
25[
2~F
260
2AH lU8U
3610 5017
2Ajl- 1UUO
33~1 1002
32~1 1UU2
3271 9010
2A10 798U
3231 8010
3261 708U
13Fb 9AUO
!\Il
L
til
1\1
SLLI
U
St-'~66
267
2AlI-
luBU
*
*
*AllRS
.5610 ~O.59
b2j2 5CUF
32.61 9U10
~H~l 78UO
'i:AH 1 {;OU
; 32M- lO4~
2be 94bf·f- 184U
269 .4bl-f26A _3.210
261:3'&l1:3f-f26C ~ 481-'"
260' 41:H- f-
IfjUU
b01U
lu40
-270
271
272
£73
274
275
321F onU1
6t;40
4AH- 1H80
1.1E...4 8&fCO
33F7 5U2U
13[U 9[80
27f,
33t-7
277
131.:.U 9llUU
13f8 9400
£78
2.79
27A
:as-
~lUU
2BOF 1GOO
33F2 5010
*
* llISPl flY
*
*
• LOC!H!:> L
*
*
*
*
*IULf..
inc
2Alf 1c80
32.3f 1020
2A31 7FOU
33f. 2 5020
1.3I:..U 9AUU
wl}
!"UH
LI
Get<
MKO.'811'
NULl.MRO
liS!
IUll1 , SMCK
bALL
1\11
BALl
'·.1
HALZ
HAL
*
* FUNCliON
*
*FNOlS L
NI
13E'-(}· Al80
BALZ
*
t'IK1t'4~"
NULL.I"RU
NULL .r"lKU
MkU.I"IHU.16 /-1 L ?l
NULL.MRO
NULL.MRO
NuLL .1"11(1
• lINl-f
j
,>
DISPLAY STTr 01
DISPLAY BYTE 02
DISPLAY BYTE 03
DISPLAY BYTE 01+
DISPLAY BYTt Do: 1N=FLT KEG N
2N=Gl:.N IU.G N
4N=FUNCTION N
8N=AORS/DATA
OUTPUT COMMAND NORMAL
f"IKO.NUlL.1
NULL .!"IRU
MK"T.Mt 8 ut- 3.f 6·0
2C6
2tBt- IP-lUJ
2:C7
221F 1f8tl
*DFAL Tl
LX
13t..U 83U.o
*
*
*
f-I-AULT
bALZ
t-fAL 11(NULL,)
z[t«,.o
AU
MRO.'Yt[l-tN:UL:L
IF OVERFLO,W
6A19 1f8D
3610 7138
bt3~O
AINC
YOl .. :NULL. YUI
L
YU,mAO
03f ~ ,Q/~U
Mt<~ .•
,,".DR .DR2
;Tn. '.t t
HAL'FWORP 80UNDARY,
AODRESS A HALF WORD IN
TH~ ARRAY & fETCH IT
M~K ~S "'·BITS TO TEST
A J:fI'T ,IN THE HALF WORD
FOJ3213580
83213590
83213600
8.3213610
8.3213620
83213630
8.32136-'0
83213650
8321566-0
8321-361'0
83213680
8321.36.90
8321'3700
83213710
83213720
-S32'1373fJ
OH RX3
832131~O
832137.50
8.3213760
83213770
83213180
83213790
8321380'0
83213810
OR RX3
IF RX2
LOAD ADURESS
l.OAD ADURESS
FETCH FULLWORD
R£TUHN TO CALL
8321·38-30
832138'10
:632138!lO
83213:860
832·1381-0
8.32.13880
83213890
8'3213900
8321.3910
LOAD HALF.Ot
=
MRl
RE.SULT SIGN
OP IN LARGEST POSSIBLE lXPON[NT
83216800
83216810
83216a20
83216830
832168~O
MRO.~RO.MR2'FLR6
MK1.I"iRl.1
,."n.ftI'U.8
I"IKO.MttUL1..)---.WI11TE IF.R/W;;l
2B~
lFaF
289'+ lD88
331-2 5-00'+
--36t... -17t,.U. -F l-CO
**
MOVE A -BYTE TO THE BtlFFER
.832.l.730 f)
8321731-0
.8m7.32.o
8-32-.17330
83217340
(READ)
. 832.1-135'4)
.. -*_.---
3BF
4B79C[lC3
-- 3C·0·· -2-41$· --1$ 8 ij.. ._.
3C1
*
. _.-.-k
--- ..uu ..uA-l- -.
8ALG
13E8 FOY9
83217360
MUH,rU,MDR,DW2
STB
8.321. 73-70
.832-1736.0
UST ..l NCaERE..NTEO-. c.ouN..:f
832173~O
RWSC1(NULL),ILIH,D
8.321~~OO
*
.. -1l32l..7;1J1
*
83217~.30
- .. -- ..----.-··-.--*·~t.-c,u.:J.f..:...~-~INSTRIIG·TleN ..lE_CDUN.T.J-JOt POSITI.llE..
832l.1~20
*
~ ..... .3{:--2-.. ~-5..o..o.1- ... -ti.-W-SG.l. --W-l· .. 13[0 F119
HALZ
;-~--33-1-2 ..-6.o.ua
*
... ~w.sc2--.---X-l.--
3C3
3C5
6C6
2B9F 1803
26fF 1F99
.. N:U1..L ....{;,cW.... f.Bl-l. .. --
RWSC2 (NULL >tILIH ,0
If "F.ASl-". MODE •..00
NEXT USER INSTRUCTION
. ~.cc.w.....BB-lt- - _ . ..:------IF -.co.uN.1-J:iAS.. . .G:Q.N.E.
post T~V£,
-
83217""'50
.-.
COMPLEMENT BUFFER SWITCH BIT
L
MAR.T[MP,DIN2
L
NlJLL.NULLtlLIR~O
832~.71f40
8321.7'+61)
83.2.17470
83217~80
83217'+90
8321750.0
3C7
2A3F 1080
3C9
2A7f 1980
13~8 F099
*WRTSC
L
O~V,MOR
L
UAT.UA1
RWSC1(NULL),ILIR,O
~OVE
A BYTE FROM THE
;_.-...3.C8..:..-1!B3.l... .o.o.cD--.... _--.-....Lti...... -- IDillf..ll::t.MUR.. _ _ _ _ .___ ...8.UF..F.£R.I.O .. .Rl ___ .._. ___ ._ __...
~CA
f-'"
- .. -- ...... _. _.._--_... -
RALG
.. _.,*-- - - - _ . _ . _ - - - - - - - - - - - - -
*
... -
TEST INCREM-ENTED COUNT
~- "'---'" ..- -...-....
-
--_... _.
.....
_. - .'-- --- .
EXECUTE. NEXT USE.R INSTRUCTION IF COUNT NOT POSITIVE
-----_.... _. - ..
-.-.. - _..
This information is p.-op.-ietary and is supplied by INTERDATA for the so'
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
r-----·
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _'__ _ _ _ __
~
832l151{)
8321752"0
.... 832.1:7.53.0. ..
832175'+0
8321755-0
.832.1 756.083217510
lNTEROATA MODEL 8/32 MICROPROGRAM
----- --3CB
32U9 503f
~---6CC
363-r -112-1
3(0
3CE.
2AU6 bLl6U
36U6 5017
*
-*--£-¥-€-Llt--RE~-¥-t~
*CKe12A
8AL
L
*
*CHelGA
3279 MIFf
HAL
28ff 1f99
L
363F
2M)3 603U
-x --
307
308
3606 5017
32FF 1001
NI
.
3DB
2206'8800
2A06 6880
-3GG--
·~-8Rl)f-
30E
2ADb
OAT,YO.'FF'
3DF
2206 8BEl
SKLX
---MN&+UA·T .flPR
MK6.MK6.LOHALF,l
MH7.1
MK6."Kb.~R7~*+2~C
..
-~ ~-.
SRLX
MR6.MK6.ftR7~*+2.C
X
"a6 ,"K6 ,run
GRGl--2B - SML·X--· .fU(o..JI'U(O -t--IJH7+*-+-2.e::
x
MH6.MKb.MRl
SRLX
2206 88E3
ZA06 6880
-~------2~-5---
2AD6
22U6
2AUb
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2A06
3t.5
3E6
3~7
3E8
3(9
3EA
SRLX
X
MK6,"Kb.I'IR7.*+2.C
- ----.-
.
~H6."K&.~7.*+2.C
~6."K6."Kl
SRt-X----~.f'm6_~7__......._2..oC-
6880
Xftt<6.t'lKb,flRl
8BE.7
SKLX
6880
813E9
6880
X
SRLX
17FC FA80
2tHf 1803
BALD
..-~-8-----O~-O-A.8-0---
8.321. 7121l
NULL.NULL.ILIR.D
.---.KG· ---2AU&----0-Ba-0--- . - --- --- ----X-----.- ---NoC:<:: cFVal"'if:,.~lIv J:1I.i'hnri7pn
in tlU'ri1"inn
e,
fl~
·~!1'0"
INTERUATA MOOtL 8/32
'+2~
--'I-2-A-
q.2B
."
6B3F 1080
1+2F
'+30
2ABF 1880
323f 10Ul
L
YO.NULL.MOR.I'+DR,+
na. !!IIM1. ~-t(UT-R£...c---
MAR.MHq.,DKI+
Ll
*
L
MAR,'28'
LOC.MUR.PR2
L
PSW.MRl
2A3F l[i80
33Fl 50£0
Ll
MK1.1
- SSRA --NYl..L' KR1 ...f\JUl:L
L
P'lH,l.MDR
NI
NULL.MK1.'OEO'
·1·1£U--993U
··---BA1-NZ ......QC.O..l S( NUL-L.J. . .
Jf.Bf 1
A~.cO
..... PAGE
05-058R02A13
--··-h--····-f'tR1-... ~ l"'9Rlf..
ln86·
339F 1028
2tjof 1D8A
;--.~--
*
2H9F lAOf
1+20
1+2l
'1032
'1033
HlSTHl AU
~-1-F-&9.. ---·------A-X-·--·---
Jf.2£--··-2A~·
:-----....a.·
MICRUPHO~HAM
'+'+
83218570
8321-8580
832185'30
83218600
83218610
83218620
83218630
832186 .. 0
83218650
83218660
83218670
63218680
632186'30
LOAD. THEN FETCH NEXT
.. - -
'n
"
••
FETCH SAVED PSW
FETCH SAVED ·L.OC
LOAD LaC. FETCH
SAVED CONSOL-E STATUS
LOAl) PSW
ADDRESS· -THE ·OISPLAY
TEST STATUS BITS 1.2.3
SHOW LOC. GO TO lOll (P.2-')
832~8100
*
..
'+35
'+36
37FD 5329
17E.O 8COO
.. 31
15f8 8fl+0
*
_..........
*
*
*
..
NULL.PSW.BIT18.1
Nl
8ALNZ MrtFINTlNULL)
HAL
lwAlllNULLJ
TEST MALF ENABLE
MACHINE MALFUNCTION «p.au
INT[RRUP·T If ENABLED
TE~T p~w WAIT BIT (P.22)
f, 'Z.2-
*
*.
;-_._._.- --._._--------- ._- --------------------- ---- ---'._---_._--_._- --- .-.
83218110
83218720
83218730
632187QO
83218750
83216160
83218770
83218780
83218790
63218800
83218810
83218820
-'
j
t -____ ..._____.__.___ ._ _ _
L
.-..
,.----
i,
L __
---.----'--'--~----
-----.,.-----------
This information is _ietary and is JdppIied by INTEADATA lor the sole
purpose of UIi. . and tR8intaining INTEflDATA supplied equipment alld .hall
not be . - l 10< MY other purpose unless specilical1v authorized in writing.
------
_._-_ ..
__
..._-- _._.
INTEkOATA MODEL 8/32 MICROPROGHAfl
-'--i
L
J
* AUT a o R 1 V E R
-,----,---_._---_. --,**--------
I
**
0010
0001t
0002
------------ - ----- --9-00-1-
832188ltO
C HAN N E L
--.a321-aasO -
83218860
8321887-0
EQU
EQU
EXLCUTE
CHECK TYPE
'80'
'10'
;.- --.--- --- -- - -·-G-l.l-Q-8------S&I,l-----E--QU---~------·---·- ..----
,
1t5
CCW BIT DESIGNATIONS
EblT
CBll
0080
PAGE
05-058R02A13
HWBIT
T6IT
EGU
EQU
FS-i-l--·
£-QY---;l{ll-l--
TEMP
DEV
.- BUE£-ER -S-W-l-UH-
READ/WRITE
TRANSLATE
'olt'
·02'
.tc-w
-
OAT
COUNT
---.' --- -- - --.---. -F-AST·KOO£
. -- ----R£T-URN-
332*888:(1
= MRO
= MR1
= 11R2
= KR3
= MR't
83218890
83218900
832-18910
83218920
8~21693-o
-=- MR5-
-8321-894 0.8321-8950
83'21-896-0
a321.a9-70
63218980
83218990
*
*
-_._'*--------
. -- -----_.-
4i38
1t39
289F lOOB
289F 1000
:...---4-3A----2-A-~·----lf+A.(}. ------.--
'1-38
'l-3c
If-3D
--.--'10-3£:--
'l-3F
,.._._-
---'- _. --- ... ----.-------
FElCH CHANNEL COMMANO WORD
REG '+
ADRS FORCED EVEN Of
-CHANEL LPlARtLOC,OR2
L
RIt,LOC
=
ItA7fE9ltO
*
EXB
- -N- - -
BALZ
NOT FAST MOOE
8321'Jl00
BAD ST-ATUS (P.'+6J
*
13£1 19'1-0
TES!IF-.FAST -Maot ..
. - TEST -D£V-lCE-S:TAWS--AGAIl\lST MASK
NULL .~3.DA.l
~~-~2-~1-----------··~·--~ .. f_:6_lT-
q.Q1
8:32:19010
83219020
S3219D30
832191)·It··O
8321-91)-50
83219.o.6D
83219070
83219080
B32l-"90"9 tl
ISOLATE STATUS MASK
DAT.CCW
BALNZ EXSUB2(NULLl
17E1 15ltO
-8~2l."OO
TEST THE EXt-CUTE BIT
NO EXECUTE, e-,c=o 'P~lt6)
IF FALL .Tt:mU,E=lg CC.:..O010
33F2 5080
NI
NULL'CCW-.EBIT
13E1 14DO
BALZ EXSUl:nCNULL)
. -,------- --- -""- ---,-*' -- ------- -_._--------------_. __. _--.- -_.~g(3_-5-98_(j - - - -
eca
----b-- --CC.w-..f'lOR-:.--E---- '--
NFAS1(NULLl
(~~~7i
83-2~91.10
*
,--,--".-..----- _.. , ._.._- ----,-*----.------------_ ...._-._. -_._*
;---.Jl~
~2v'"
*
-1-U-U2·---- - - -
q..lt3
q.1t1t
2B9F 180_6
3390 1002
Jt45-.
2A-~·-1-C8-U----
q.q.6
q.lt7
F A S T
13E9 16CF
2891t 108B
- . ·8321-9l-2tl
MUD l
-ADRS 'BUFFER
- -A-l-·------Tt:lW ~2- .. -- -- .-
L
AI
- ------ - - -b- - _ . -CUUN-'l-... MOli,--- ---
BALG
EXAU10(NULL).DR~
A:
MAR.COUNT.MDR.DR2
.*
~o
-BYTE £CUNY
FETCH IT
PlAR, TEMP,OR2
MAR,lEKP,2
EXIT. COUNT POSITIVE (P.lt6)
BUFFER END ADDRESS + COUNT
.
* S-UFFER 0 BYTt. COUNT II\; REGISTER nCOUNT"
;:-______-'- _____________1t.l1UEEE.:R.-U
* ADDRESS Of_fNO-AUliS_.i:...BUE.-CDlJMI_.l.N._!'MAR"
BUFFLROBYTE -COUNT IN "T,E-MP"
* BYTE/HALF~ORU TU TRANSFER IN "MDR"
.-
----_ ....- --- ------ - --,--*------_.._.- -------------_._-----..:.-------.- ----- --- --.. --------- ----..-. "-'-'- - .--.. _ .. _. ____ . _. .
q..lta
If-3FF EF07
i
L_ ,_ . _._"_"__ . . ._.__ _
THWX
**
NULL,NULL,BYTEIO.C
Fat L. THROUGH IF , UIE-lS-AC·TIV-E-
TEST HW LINE (P.'t61
_p _________
,
_______________
832-19130
832191q.-O
832.19150
8321--9,160
-832-1-9170
'-8321-9180
8321919U
83219200
8321'921.0
83219220
-83219230
.8321.9.2I+Q_ .
83219250
83219260
.8.3219270
83219280
83219290
__._.:B.3.2.19.3Q.n -- --
_
83219310
83219320
_ ____ 83219330.
r--...a4.!3-~2.5-OD--~
, Q4A 17£1 18CO
BALNZ HWRT1(NULL)
WRITE HW, RW=l (P.'+6)
832193ltO
83219350
*
4Y,S ~~----------Rl:i.--.
,Ula- Nt " I .DW2-_____ .____ JlEAnJ:lAI FWOaO
_________ . ____ _
_8.3219360
83219370
~q.C
3291t 1002 HRDWT Al
COUN1.COUNT,2
INCREMENT OF BUFFER 0 BYTE COUNT
83219380
q.q.D 2B9F 1800 CUMMON L
MAR.1EMP
RE-ADDRESS BUFFER BYTE COUNT
*
* - -.. ---WL-----lWU... lCt-W--t--RW-aI-L-____._ l£U __RLIL_.BLT ______ . __
.-------
r-~--2aU:
I
~QF
lAO~
17£:9 16CO
-L-..
MOa.CQtmn,OW2
BALNG EXAUTO(NULL)
--____ ._..._____ .__________ . ___ ... __.____., -
---'--p-
This information is proprietary and is supplied by INTEROATA for the sole
_.
•
- ~-,-,-- '''ITCCr'\ATA
."orv"Ioli~ ~lIinlTu:ant ;;"Id
-___ 8.32l.9.390
83219'+00
ExIT IF NOT POS.ITIVE (P.lt6)
shall
INTEHUATA HODE.l 8/32 MICROPROGRAM
PAGE
05-058R02A13
'+6
83219 .. 10
aa219 .. 20
83219 .. 30
83219 .. 40
83219 .. 50
8321.9.. 60
83219 .. 70
8321' .. 8t1
8321949:0
8321950e
83219510
8.321952.0
* XIT-·~O· -susHWTJ.-Nt-,--lF-·---GOON-T- -J.f.A.S BE COME: -POS1 T1 Vl
.*-t
*
*
,-
&f.50
&f.S1
q.b2&f.S3
&f.Stf.
33b&f. lO1&f.
2S ..... U6B
q.·55
338'0 5FFO
q.o~
2380 3f.«JO
1t-57
.... 58
459
*
t.XSUB1
Al
REG -It- = ADRS OF cca
FETCH SUBROUTINE ADDRESS
TEMP='ODOOFFFE'
L
I"IAR.t{1t-.20
NULl,NUll,OR2
lEJIIIP .. CF-FF£,1lOC • TEMP .-MoR
NULl.NULL,IR.D
NI
PSW, PSW.
AINCX P-SW...... SW4NULL.. EXSUSl
Cl.EAR CC THEN
8£T L FLAG (BA·O STATUS)
NULl,ceW.RWBIT
Nl
HAlNZ FWRIT(NULl)
TEST R/W BIT
WRITE BYTE IF
L
-LlN
3Etl:f'- 1(,)39
2850 5060
2BFF IF9C
*'
*lXStJB2
*
*
*
BYT£lO
33Ft! SOUit17El 1900
'FFO •
R~
832~95.30
8321954:0
83219550
832195611
a321'570
83219580
83219590
= 1
~3219(a0t)
*
It-elF- OU63
FETCH USER INSTRUCTION
RO
MUR.MOt<.OW2
8321961D
BYTE
REAO
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MODEL 8/32 WITH DPFP
PROG= 05.058F2
ASSEMBLED BY
0001
PAGE
05-058F02A13
3
8
9
10
11
12
13
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IFNZ DFU
ENDC
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COPYRIGHT INTERDATA INC.
DFU
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*
35
36
37
38
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PAGEl
PAGE2
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PAGE .... 5
... 5
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50
51
52
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55
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APRIL. 1976
TARGT 8/32
CROSS
33
3 ...
83200010
83200020
83200030
83200040
83200080
83200090
83200110
83200120
83200130
832001'+0
83200150
83200160
SYSGEN CARD
IRA GABBERT
1'"
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03-103ROOM~6
1
2
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ELSE
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PARTS
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PARTS
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PARTS
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1~-1'+2ROOF68.19-1'+2ROOF69.19-1"'2ROOF70.19-1'+2ROOF71
19-1'+2ROOF72.19-1'+2ROOF73.19-1'+2ROOF7 .... 19-1'+2ROOF75
19-1'+2ROOF16,19-1'+2ROOF77.1~-1'+2ROOF78.19-1'+2ROOF7~
19-1,+2ROOF80.19-1,+2ROOF81.19-1 ... 2ROOF82,19-1,+2ROOF83
19-1 ... 2ROOF8 .... 19-1 ... 2ROOF85.19-1'+2ROOF86.19-1'+2ROOF87
19-1,+2ROOF88.19-1,+2ROOF89.19-1,+2ROOF90.19-1'+2ROOF91
19-1'+2ROOF92.19-1 ... 2ROOF93.19-1 ... 2ROOF9 .... 19-1 ... 2ROOF95
19-1,+2ROOF96.19-1,+2ROOF97.19-1,+2ROOF98.19-1 ... 2ROOF99
19-195ROOF05.19-195ROOF06,19-195ROOF07,19-195ROOF08
19-195ROOF09,19-195ROOF10.19-195ROOF11.1~-195ROOF12
ENDC
IN ALL CASES WHERE A BRANCH OR TRANSFER COULD OCCUR TO A
L1STING PAGE OTHER THAN THE CURRENT LISTING PAGE. THE TARGET
PAGE NUMBER IS SHOWN IN PARENTHESIS IN THE COMMENT FIELD.
ON
i..I
MRO.5
BALD
TLSU(NULL)
POWER~UP.
OR AFTER
INITIALIZE, MICRO CODE
83200590
EXECUTION BEGINS AT '001'
GO TO POWER UP ROUTINE (p.,+~)
83200600
83200610
USER LEVEL INSTRUCTION EMULATION ENTRy-POINTS
FOLLOW. IN RESPONSE TO AN INSTRUCTION READ COMMAND
THE HARDWARE, READS THE NEXT USER INSTRUCTION FROM
THE MAIN MEMORY LOCATION SPECIFIED BY (LOC). TWO.
FOUR OR SIX BYTES ARE READ. DEPENDING UPON THE
INSTRUCTION TYPE. TWICE THE USER'S OPERATION CODE
IS THE STARTING ADDRESS IN ROM OF THE APPROPRIATE
EMULATION SEQUENCE. THE OP-CODE IS SHOWN IN THE
COMMENT FIELD AND THE USER'S MNEMONIC IS THE LABEL.
This information is proprietary and is supplied by INTERDATA for the sole
_ .. ~~ ............. ~ .... ; ...... "" ... ..-1
....."";nt ... ininn
83200350
83200360
83200370
83200380
83200390
83200400
83200'+10
83200'+20
83200 ... 30
83200'+"'0
83200 ... 50
83200 ... 60
83200470
83200'+80
83200'+90
83200500
83200510
83200520
83200530
832005,+0
83200550
832005'0
83200570
83200580
INTI=RnATA
C:;lInnli~
p'nuioment and shall
*
*
*
*
*
*
*
*
*
83200630
832006 ... 0
83200650
83200660
83200670
83200680
83200690
83200700
83200710
MODEL 8/32 wITH DPFP
05-056F02A13
COPYRIGHT INTERDATA INC.
002
003
2A1F lCOl
233F 1005
004
005
17EC OlOC3
23SF 1837
006
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13EC 01DC3
235F lC37
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2BF9 OC3C3
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13F4 8090
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2839 6C39
0001 0000
010
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283F lC39
q.EOO 0000
012
013
2B7F lCOO
23F9 6DBC
01q.
2839 lC3C3
FFFf' 0000
015
016
017
2B3C3 OC39
0000 FFFF
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1398 06CO
FOOO 0000
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13C38 D8CO
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2879 lOA3
2BFF lF9C3
0000 0000
2
APRIL. lC376
71
72
13
14
75
76
77
76
1C3
80
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PAGE
81
62
83
6'10
85
86
67
88
89
90
91
92
C33
91195
C36
97
98
C3C3
100
101
102
103
10'10
105
106
107
108
109
110
111
112
113
119
120
121
122
*
BAL.R
L
L.X
MRO,YS.IL
YD,LOC,8ALRl
SAVE BRANCH ADDRESS
INCREMENTED LaC TO YO
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BALRl
BALT
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BRR(NULL).ILIR,D
LOC.MRO,BC2
BRANCH IF MASK TRUE
LOAD LOC (P,3)
*
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BRANCH IF MASK FALSE
LOAD LOC (P.3)
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*
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LOAD
READ CC IF V FLAG (P.S)
A
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NULL,NULL,ILIR,D
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FETCH NEXT INSTRUCTION
HIHALF
*SR
*
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*
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*
AHMl
L
01
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*
02
*
*
03
*
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05
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06
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2ND OP TO MOR
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*
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*
*
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*
*
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*
*
OC
*
*
00
*
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83200730
63200740
83200750
83200760
832007.,0
63200780
83200790
83200800
63200810
83200820
8320'0830
832008~0
(P,28)
*
LR
L
CONSTANT DC
*AR
*
63200850
83200860
83200810
83200880
83200890
83200900
83200910
83200920
63200930
832009'+0
83200950
83200C360
83200910
63200980
83200990
83201000
83201010
63201020
83201030
832010'100
63201050
63201060
63201070
83201080
63201090
83201100
83201110
83201120
63201130
632011'+0
83201150
63201210
63201220
63201230
832012~0
MODEL 8/32 WITH DPFP
COPYRIGHT INTEROATA INC.
020
021
2839 8E89
0000 :.t800
124
125
4
"',
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038
039
2838 EC19
0000 FFFE
03A
038
2A1F lC89
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03D
03E
03F
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3219 COOl
3210 7001
2Al0 1830
161+
2B39 9E89
FFFF 7FFF
024
025
026
027
028
029
02A
028
02C
020
3210
3658
3652
3652
2A38
37F1
13EO
3210
283F
2BBD
02E
02F
2B3F lEOO
28FF lF9C
030
031
032
033
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2A7F
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13F8
0000
035
036
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6327
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3
APRIL 1976
127
128
12'3
130
131
132
133
134
135
136
137
138
159
140
141
142
143
144
1'+5
1'+6
147
148
149
150
151
152
153
15'+
155
156
157
158
lS9
160
161
162
1&3
022
023
PAGE
05-058F02A13
*
SRLS
O ....
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YD,YO,YSI,ILIR,E,D
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'cooo~eoo'
.......
*
10
*
*
11
*
*
12
*
83201280
SIGNS ALIKE (P.7)
PROPOGATE 1ST OP SIGN
FORCE SOME MAGNITUDE
83201290
83201300
83201310
83201320
83201330
83201340
83201350
83201360
83201370
83201380
832013'30
83201&f.00
83201410
83201420
83201430
83201'+40
83201450
83201'+60
83201'+70
83201480
83201'+90
83201500
83201510
83201520
83201530
832015&!-0
83201550
83201560
8320'1570
83201580
83201590
83201600
83201610
83201620
83201630
83201640
83201650
SET CONDITION COOE
83201660
SLLS
8IT160
SLL
DC
YD,YD,YSI,ILIR,E,D
'FFFF7FFF'
*
CHVR
NI
L
MRO,PSW,8
MR2.YS,HIHALF,I
MR2,MR2,BIT16,I
MR2,MR2,8IT16,I
MR1,YS,MR2.IL.IR
NULL.MR1.BIT15oI
CHVR1(NULL)
MRO,MRO,4
YO,MR2.E
0
PS~hPSW,MRO,D
SAVE PREVIOUS CARRY
SET MS 16 BITS
INVERT THE SIGN BIT
AND EXTEr\lD IT
RE-CREATE HW OVERFLOW BIT
BY COMPARING BITS 15 AND
16 OF R2
OVERFLOW IF DIFFER
LOAD RESULT, ADJUST G & L
OR IN C & V
L
L
YD.MAR
NULL,NULL,IR,D
ADDRESS VALUE TO Rl
FETCH NEXT INSTRUCTION
L
AINC
L
BAL
DC
MR3,YS
YDI,NULL,YSI
LOC,YD
TEST1(NULL)
0
SET NEW PSW ASIDE IN MR3
POINT TO R2+1
LOAD NEW LaC
(P.43)
A
L
MAR,YX,MDR,IL
LOC,MAR
NUL.L,NULL,IR,D
CALCULATE EFFECTIVE ADDRESS
LOAD NEt.} LOC
FETCH NEXT INSTRUCTION
01
XI
Al
X
NI
BALZ
01
CHVRl
*LA1
*
LPSWR
*
BCl
BC3
BC2
L
*MR
M
CFFFE
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YD,YDP1,YS,ILIR,D
'OOOOFFFE'
L
AX
MRO.YD,ILIR
MR1.YDP1.NULL.DRl
*
OR
*
C2
8ALNL CLl( NULL) .ILIR
SRAI MRO,YO.1
MRO,MRO.l
01
MRQ,MRO,MRO,E,Q
A
83201260
83201270
SAVE MS DIVIDEND
SAVE LS DIVIOfND (P.2)
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
*
18
*
*
lC
*
*
10
*
~,
MODEL 8/32 WITH DPFP
05-058F02A13
COPYRIGHT INTERDATA INC.
0'+0
0'+1
17EC 1059
221F OE83
0'+2
o If. 3
17EC 1159
2210 OE80
Olf.'+
13EC 1059
221F lE87
0'+5
0'+7
13EC 1159
2210 lE80
0'+8
0,+9
2B3F 1E89
221F lE2F
046
O'+A
0'+8
283F OE89
2B3F lCBO
O&f.C
0,+0
2B39 1EB9
2350 lDOF
0'+(
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050
2B39 OEB9
2BFF 1F9C
050
051
CBF9 2C29
13F8 1990
052
053
CBF9 3C09
CBFF OFBO
051+
CBF9 '+C29
C3FF OFA7
055
056
057
CBF9 5C29
C3FF QFA7
059
CBF9 6C09
l3F8 1980
05A
056
CBF9 7C09
13F8 1980
05C
05D
CAlF lCOO
13F8 £2'+0
05£
05F
361F 1011
13F9 35CO
058
PAGE
If.
APRIL 1976
166
167
168
169
170
171
172
173
17'+
175
176
177
178
179
180
181
182
183
18'+
185
186
187
188
189
190
191
192
193
19'+
195
196
197
198
199
200
201
202
203
20'+
205
206
207
208
209
210
211
212
213
21'+
2'+0
*
BTBS
BBS
* 20 *
BALT
SX
BBS(NULL).ILIR.D
MRO,NULL,YSI,BBSl
BRANCH IF ""ASK TRUE
DECREMENT BY TWICE R2
BALT
SX
BFS(NULL).ILIR,Q
MRO,MRO,YSI,DOSBR
BRANCH IF MASK TRUE
MRO=BYTE DISPLACEMENT
BFBS
BFS
BALF
AX
BBS(NULL).ILIR,D
MRO,NULL,YSI,BFSl
BRANCH IF MASK FALSE
INCREME~T BY TWICE R2
*
BFFS
BFS1
BALF
AX
BFS(NULL).ILIR,Q
MRO,MRO,YSI.OOSBR
BRANCH IF MASK FALSE
MRO=BYTE DISPLACEMENT
L
LX
YD,YSI,ILIR.E,D
MRO.MAR.CAORS3
EFFECTIVE AORS TO IWIRO (P.5)
LCS
S
L
YD,NULL.YSI,ILIR
YD,YO,E,O
SUBTRACT TO TWO'S COMP
SET G,L
*
AIS
OOSBR
A
AX
YD,YD,YSI.ILIR,E,O
LOC,MRO,LOC,OOSBR1
S
L
FETCH NEXT INSTR
IFNZ
rO,YO,YSI,ILIR,E,D
NULL,NULL,IR.D
DFU
LE
BAL
YO.YS,ILIR,E
EEXIT1(NULL).0
LOAD
READ CC (P.5)
CER
RCC
YD,YS.ILIR
NULL,NULL,E,O
COr1PARE
SET CONDITION CODE
AER
RCCX
YD,YS,lLIR,E
NULL,NULL,EEXIT2
ADO
COLLECT FLAGS (P.5)
SER
RCCX
YD.YS,lLIR.E
NULL,NULL,EEXIT2
SUBTRACT
COLLECT FLAGS (P.5)
MER
SAL
YD,YS.ILIR
EEXIT1(NULL)
MULTIPLY
TO COMMON EXIT (P.5)
OER
SAL
YD,YS.ILIR
EEXIT1(NULL)
DIVIDE
TO COMMON EXIT (P.5)
RRE
BAL
MRO,YS
FXR1(NULL)
ARGUMENT TO MRO
(P.39)
LI
SAL
ENOC
MRO,CONSTANT.I
FLR1CNULL)
r1RO=''+EOOOOOO'
(P.5&f.)
*
BTFS
BBS1
*
*
LIS
CAORS2
*
*
SIS
OOSBRl
*
LER
*
CER
*
AER
*
SER
*
MER
*
DER
*
FXR
*
FLR
*
21
*
*
22
*
* 23 *
*
2'+
*
* 25 *
* 26 *
FORM BRANCH ADDRESS
* 27 *
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERQATA supplied equipment and shall
not be used for any other purfX>se unless specificatly authorized in writing.
*
28
*
*
29
*
*
2A
*
* 2B *
* 2C *
* 20 *
*
2E
*
*
2F
*
83201680
83201690
83201700
83201710
83201720
83201730
832017'+0
83201750
83201760
83201710
83201780
83201790
83201800
83201810
83201820
83201830
832018'+0
83201850
83201860
83201870
83201880
83201890
83201900
83201910
83201920
83201930
832019'+0
83201950
83201960
83201970
83201980
83201990
83202000
83202010
83202020
63202030
832020'+0
83202050
83202060
83202070
83202080
83202090
83202100
83202110
83202120
83202130
83202140
83202150
83202160
83202'+20
MOCEL 8/32 WITH OPFP
05-058F02A13
COPYRIGHT INTERDATA INC.
061
2AOF lFOO
1399 '+5CO
062
062
063
CBF9 '+OA9
C3FF OFA7
064
065
1399 43CO
0&5
CBF9 5089
066
067
CBFF OFAO
1~F4 8190
068
069
3338 A010
2BFF 1e99
06A
061\
06B
CaF9 6089
13F8 1980
"''''2
~'T'"
06F
070
071
C8F9 AC29
l3Fe 1990
072
07~
CBF9 8C09
C8FF OF"80
074
075
e8F9 ee09
13F8 1980
076
077
CBF'3 DCO'3
13F8 1980
078
079
CBF9 EC09
13F8 1980
07A
078
CBF9 FC09
13F8 1980
07C
070
CAlF geoo
13F9 3000
07E
07F
361F 1011
13F9 32eo
ObE"
lDC9
1EOO
100'+
OBOO
*
IIOOC'C
I-IrQ"';'},
2~~
2~5
2~6
*
2~7
AEl
2'+8
252
253
25&1255
256
257
258
259
265
266
267
268
2&9
270
271
272
276
277
239A
2A1F
3210
03F8
06C
068
5
APRIL 1976
2~2
060
PAGE
278
279
280
281
282
283
28'+
285
286
287
288
289
290
291
292
293
29'+
295
296
297
298
299
300
301
302
303
30'+
305
*
PBR
SEl
*
EEXIT1
EEXIT2
*
EXHR
*
MEl
*
CAORS
CAoRS1
CADRS3
*
LOR
*
CDR
*ADR
*
SuR
*
MDR
*DoR
*
FXOR
*
FLDR
*
30
L
MR.6; YOI
SAVE Rl FIELD
SAL
MPSSR1(MAR)
(P.56)
IFNZ
AER
RCCX
ENOC
DFU
YO,MDR.ILIR,E
NULL,NULL.EEXIT2
AOo
COLLECT FLAGS
SAL
IFNZ
SER
PSR1(MAR)
OFU
YO,MOR.ILIR
SUBTRACT
RCC
BALV
ENOC
NULL,NULL,E
FFAUL T (NULl) ,0
TEST RESULT FLAGS. SET CC
ERROR IF V FLAG (P.2B)
RRl
L
Yo,YS.16
NULL,YO.ILIR,o
EXCHANGE HALFWOROS
IFNZ
MER
BAL
ENOC
OFU
YD,MoR.ILIR
EEXIT1(NULL)
MULTIPLY
AX
L
AI
SAL
COR
RCC
MAR.YX,MoR,CADRS2.C TRANSFER IF RXl OR RX3 (P.~)
MRO.MAR
o2+(X2)+(LOC) TO MRO
MRO.MRO.~
ADD '+ FOR LOC INCREMENT
(MR6)(NULL)
RETURN TO CALL
* 38
YD.YS,ILIR.E
LOAD
EEXIT1CNULL).o
READ CC
* 39
Yo,YS,ILIR
COMPARE
NULL,NULL,E,D
SET CONDITION CODE
AoR
SAL
YD,YS.ILIR
EEXIT1(NULL)
ADD
TO COMMON EXIT
SOR
SAL
YD,YS,Ii..IR
EEXIT1(NULL)
SUBTRACT
TO COMMON EXIT
MOR
SAL
yo.YS.ILIR
EEXIT1(NULL)
MULTIPLY
TO COMMON EXIT
DDR
SAL
Yo,YS,ILIR
EEXIT1(NULL)
DIVIDE
TO COMMON EXIT
RRO
SAL.
MRO,YS
FXDR1(NULL)
ARGUMENT TO MRO
(P.52)
LX
BAL
MRO,CONSTANT.I
FLDR1(NULL)
MRO=''+EOOOOOO'
(P.53)
LO
BAL
(P.55)
*
*
32
*
*
3~
*
83202~~0
83202~50
83202'+60
83202'+70
83202'+80
83202'+90
83202500
832025'+0
83202550
83202560
83202570
83202580
83202590
83202600
83202610
83202670
83202680
83202690
83202700
83202710
83202720
83202730
832027~O
This information is proprietary and is supplied by INTER DATA for the sole
purpJse of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized In Writing.
*
*
*
3A
*
*
38
*
*
3C
*
*
3D
*
*
3E
*
*
3F
*
83202780
83202790
83202800
83202810
83202820
83202830
832028~O
83202850
832"02860
83202870
83202880
83202890
83202900
83202910
83202920
83202930
832029~O
83202950
832029(,0
83202970
83202980
83202990
83203000
83203010
83203020
83203030
832030,+0
83203050
83203060
83203070
MOPEL 8/32 WITH OPFP
OS-OS8F02A13
COPYRIGHT INTERDATA INC.
080
081
1208 5E80
287F lC83
082
083
289A 1081
221F lE05
o8 If.
085
17EC 0059
233F 1007
086
087
13EC 0059
235F 181F
088
089
2B9A 108S
2839 5099
D8A
086
2B9A 108B
2BF9 0089
08C
080
2B9A 108B
2839 7089
08E
08F
2B9A 108B
2839 60B9
090
091
2B9A 108B
2B3F 1089
093
2B9A 108B
13F8 O'+CQ
09'+
095
289A 108B
2939 10B9
096
097
2B9A 1088
2839 ODB9
098
09~
299A 108B
13F8 0780
09A
09B
2B9A 108B
13F8 0980
Q9C
090
2A3B
2838
13F'+
2BFF
092
09E
09F
lF80
FD89
B090
lF9C
PAGE
6
APRIL 1916
307
308
309
310
311
312
313
311+315
316
317
318
319
320
321
322
323
321f.
325
326
327
328
329
330
331
332
333
331f.
335
336
337
338
339
3 If. 0
31+1
342
3'+3
31+-'+
3'+5
3'+6
3 If. 7
3'+8
31+-9
350
351
352
353
*
STH
*
1+-0
*
*
1+-1
*
BC1(NULL).IL.IR,0
YO.LOC,SAL2
BRANCH IF MASK TRUE (P.3) *
INCREMENTED LOC TO Rl
1+-2
*
8ALF
L.X
BC1(NULL),ILIR,D
LOC.MRO.SAL3
BRANCH IF MASK FALSE (P.3)*
LOAD NEW LOC
1f.3
*
A
MAR,YX.MOR.OR2
YO,YO,MOR,ILIR.E,O
*
'+'+
*
*
1f.5
*
*
'+6
*
*
'+7
*
*
1+-8
*
*
'+9
*
*
4A
*
*
'+8
*
*
'+C
*
*
'+0
*
SAL
L
STORE(MR6)
MOR,YO,OW2
COMMON ROUTINE (P.l1+-)
EXECUTEQ INSTR.
A
L.X
MAR,YX.MOR.IL
MRO.MAR,BAL1
CALCULATE EFFECTIVE ADDRESS
SRANCH ADDRESS TO MRO
*
8TC
BALl
BALT
LX
*
B.FC
8AL.2
*
NH
*
SAL
N
*
CLH
A
5
*OH
*XH
*
LH
A
0
MAR,YX.MDR,DR2
YO.YO,MDR,ILIR,E,O
A
X
MAR.YX,MDR,OR2
YO,YD,MOR,ILIR,E,O
A
MAR,YX.MOR.OR2
YO,MOR,ILIR.E.O
L
*
CH
*AH
*SH
*
MH
*
OH
*
DO
BAL
MAR,YX,MOR.OR2
Cl(NULL)
A
A
MAR,YX,MOR,OR2
YO,YO,MOR,ILIR.E,O
A
MAR,YX,MOR.OR2
S
YO.YO,MDR,I~IR.E.D
A
BAL
MAR.YX.MOR.OR2
MH1(NULL)
FETCH MULTIPLIER
(P.3?)
A
BAL
MAR,YX.MOR,OR2
OH1(NULL)
FETCH DIVISOR
(P.37)
A
MR1.l0Pl,NULL
YO,YDP1,MOR.ILIR
DFALTOCNULL).O
NULL,NULL,IR,D
(P.28)
A
0
BA~V
BAL3
MAR.YX.MOR.OR2
NULL,YO,MOR.ILIR.E.O
L
(P.2)
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83203090
83203100
83203110
83203120
83203130
832031lf.0
83203150
83203160
83203170
83203180
83203190
83203200
83203210
83203220
83203230
83203240
83203250
83203260
83203270
83203280
83203290
83203300
83203310
83203320
83203330
83203340
83203350
83203360
83203370
83203380
83203390
83203'+00
83203'+10
83203420
83203'+30
83203,+,+0
83203'+50
85203 .. 60
83203'+70
83203lf.80
83203'+90
83203500
83203510
83203520
83203530
832035'+0
83203550
MODEL 8/32 WITH DPFP
05",058F02A13
COPYRIGHT INTEROATA INC.
DAO
OAl
1208 ·SE60
2B7F lC87
OA2
OA3
OA~
1208 BCOC
2B79 lDA7
2BFF lF99
OAS
OAS
OA7
CBFF 8080
CBF9 ADA9
13F'+ 1990
OA8
OA9
2B9A 108F
2839 50B9
OAA
OAB
OAC
OAO
2B9A lOaF
2BF9 00B9
2B9A loaF
2839 7089
OAE
OAF
2B9A 108F
2B39 6089
OBO
OBl
289A lO8F
2B3F 10B9
082
083
2B9A loaF
13F8 O~CO
OB&f.
OBS
289A 108F
2839 10B9
OB6
OB7
289A loaF
2639 OOB9
OB8
OB9
2B9A lD8F
283B E099
aBB
2B9A loaF
221F lC'C
OBC
OBD
1208 BASQ
13FC F31+0
OBE
OBF
1208 BA8D
13FC F500
OBA
PAGE
7
APRIL 1976
355
356
357
358
359
360
361
362
363
*ST
*AM
*LOl
36~
365
366
367
368
369
370
371
372
373
37'+
375
376
377
378
379
380
381
382
383
38'+
385
386
387
388
389
390
391
392
3'13
39'+
395
396
397
398
399
'+00
'+01
'+02
*
*
N
*
Cl
Cll
*
0
*
X
*
L
*
C
*
A
*S
*
PI
MOR,YO,OW~
COMMQN ROUTINE
EXECUTED INSTR.
BAL
ROFULl(MR6)
FETCH FULlWORD (P.31)
A
MOR.YD,MOR'OW~lE
L
NULl.NUll,ILIR.O
lW
lO
BALV
NULL,MDR,Iq.DRq.
YO,MDR.ILIR,E
EEXIT1(NULL).0
A
N
MAR,YX.MOR,ORq.
YD,YO,MOR.ILIR.E.D
A
S
MAR.YX.MDR,OR4
NULL,YO,MOR,lLIR.E,D
A
0
MAR.YX,f/lOR.OR4
YO,YO,MOR.ILIR1E,O
A
X
MAR.YX,MOR,OR4YO,YO,MOR.ILIR.E,O
A
L
MAR,YX.MOR,OR'+
YO,MOR,ILIR.E,O
A
BAl
MAR.YX,MOR.OR,+
Cl(NULL)
A
A
MAR,YX,MOR.OR'+
YO,YO,MOR.ILIR,E.O
A
S
MAR,YX,MOR.OR'+
A
MAR,YX,MOR,OR'+
YO,rOP1.MOR,ILIR,O
M
*
0
*CRC12
*
CRC16
STORE(MR6)
BAl
l
(P.l~)
* so *
*
51
*
LOAD MS 32 BITS. FETCH LS 32
lOAD LS 32 BITS
TO COMMON EXIT IF V FLAG
*
5'+
*
*
55
*
*
56
*
*
57
*
*
58
*
*
59
*
*·5A
*
*
58
*
*
5C
*
*
50
*
* 5£
*
*
*
(P.2)
YO,YD.MOR,I~IR,E,D
A
MARtYX!P'lOR.DR~
LX
MRO.YO.oo
(P.6)
BAL
BALA
ROHALFCMR6)
CRC12ACNULL)
FETCH CHECKWORO (P.31)
ARM INTERRUPTS (P.'+2)
BA~
ROHALF(MR6)
BAlA
CRC16A(NU~L)
FETCH CHECKWORD (P.31)
ARM INTERRUPTS (P.~2)
This information is proprietary and is supplied by INTEROATA for the'
purpose of using and maintaining INTI;ROATA supplied equipment and shall
not be used for any othel" purpose unless specifically authorized in writing.
5F
83203570
83203580
83203590
83203600
83203610
83203620
83203630
832036q.O
83203650
83203660
83203670
83203680
832~3690
83203700
83203710
83203720
83203730
832037'+0
83203750
83203760
832(13710
83203780
83203790
83203800
83203810
a320-3820
83203830
832038'+0
83203850
83203860
83203870
83203880
83203890
83203900
83203910
83203920
83203930
832039~0
83203950
83203960
83203970
83203980
83203990
8320'+000
8320'+010
8320'+020
8320'+030
8320'+0'+0
MODEL 8/32 WITH OPFP
OS .. 058F02A13
COPYRIGHT INTERDATA INC.
OCO
OCl
OCl
1208 5E80
OC2
OC3
1208 BA80
13FB 0780
Ocq.
OC5
1208 BASO
13F9 '+200
OC6
OC7
1208 1800
1378 E6CO
OC8
OC9
CB7F le87
1208 cooo
13F8 c,+oo
OCA
OC8
120a COCO
13F8 C700
OCC
OCO
1208 COCO
13F8 OlCO
OCE
OCF
1208 COCO
13F8 O'fo'foO
000
000
001
269A loaF
13F-8 0700
2B9A l08F
13F8 '+6ao
00'+
005
2B'3A lOSf'
13F8 18S0
2S9A lOaF
13F8 19'+0
'to't
'tOS
'+06
-'+07
'tlO
411
... 12
_13
'+14
't15
... 16
417
... 18
'+19
..20
'fo21
2B9A loaF
13F8 lABO
008
OOC
289A 108F
CSF9 7089
13F8 19-80
000
0000 000-0
OOA
ODE
OOF
1~76
*
STE
*
AHfII
*
PS
*
LRA
*
ATL
-.. 22
.. 23
'+2'+
.. 25
426
't27
*
ASL
*
RTl..
~28
.. 29
.. 30
.. 33
~,3q.
'+35
1+36
1+37
438
'+39
..... 0
'+'+1
-.... 2
1+~3
RBL
·2BFF lF83
2BFF 1F',
*
I.E
CE
*AE
*S£
-1£ -
'*
....., -DE
«+77
EXECUTED-INSTRUCTION
832"164
FETCH R£SIDUAL -CHECKSUM (P.ll)
(P.55)
BAL
CALCULATE ADDRESS CP.-S)
tP.'O)
SAL
SAL
-ATSLIMR6l
ATL1(NULL)
COMMON OVERHEAD fP.32 )
(P.33)
SAL
BAL
ATSLH1R6)
ASL1(NU\.L)
COl'Vl.ON OVERHEAO fP.32)
SAL
SAL
RTBLU1R61
RTL1(NULL)
CaMMON -oVERHE-AO (P.3S)
SAL
SAL
IFNZ
RT8\.("R6)
RBL1CNULLl
A
.MAR.YX.MDR,ORq.
1..El(NULL)
DFU
·MAR. YX, PU1R, OR ..
A
. t£l (NULt.)
"AR. YX ,MQR ,OR'+
A£l(NULL)
A
-SAL.
fIIAR,YX,filOR,DR't
S£l(NULL)
A
A
-SAL
MAth YX ,MOR.DR4
-~l(NULL)
A
'MAR, YX .MDfhDR'+
OER . -'YD,MDR,lLIR
BAL -££)(1 Tl '( NULL )
:63
*
* fl4
*
*
:$
*
8320417.:0
a32~-UO
832()111~
832 Gft2JU)
832':Oft.21-G
3!20,.. 2.2tl
-83-2DI!e.30
83204:250
832D~6'O
*- 66
'*
*
-*
(P.36)
8320'+270
8320~&tJ
8320:U9-0
83~~OO
CO'U"ION OV£RHEAD (P-.35)
fP.36)
67
*6-8_
(P.21
FETCH COMPARAf.J1l
-69
*
--* 6A
*
* 68
*
-*
(P.l0)
FETCH ADDEnD
U''e5)
F£TCH SUBTRAHEND
(P.5)
F£T~H
8320ftlf+tl
83204150
812D~Jt.Q
65
(1;)~33)
832U4310
832:O~320
-832"3_30
-832:6"'3411
832.t)-'+350
8323f+.36tl
-&32;9_370
8320~
-832tt'+:!-,.o
a:32 0Itl+111)
832 0l+'+:!1l
:a32CO"2'-O
832&1f4a-.o
'832:o:q.ff49
832{)4'J50 .
8320,,%0
MULTIPL1ER
-* 6t -*
a32{)1t47 0
-* 60'*
U~'5{tO
Fi:TCH OlVIS-oR
DIVIDE
TO :COMO:N £XIT fP.5)
.l)
a32-0~1)
832-0__,..90
tP.l.O)
ENDC
*
* .62 '*
ROHALF(f1R6)
PB1CNULL)
CAORS(MR6)
. LRAl H10R )
8320'+:oan
832-0 't 0"90
8320'+12,0
83204130
61
SAL
SAL
SAL·
832-o't1l:6D
8320~"])
-*
*
BAt.
DC
476 ·--:CBT2
60 *
FETCH HA1.FWORO (,P.31)
(P.2l
SAL
-*
"*
ROHALFCMR6)
AHM1 ( NULi. )
SAL
ft.50
1+51
1+-52
1+-71+1+15
COMON ROUTINE (P.l'+)
SAL
BAL
*
-4 ....
1+-.. 6
..... 7
'+1+-8
BAL
STORECMR6)
IFNZ OFU
RRE
"MDR,YO.OW'+
ENDC-
-$
.. 31
q.q.5
oDe
00'
8
I
~32
002
003
006
007
APRIL
PAGE
8'32"51J)
83~~0
832·l)t+330
-832-04'54+1)
33211t7-6'O
-832-0'4710
L
' -NULL. NULL .-OW2
NULL.nULL~It.lR.O
-I..
STORE "'OOIFI-ED :alT
F-ErCH NEXT INSTRUCTION
: Thi&
in·formation is prbprietary ·-and is supplied bV IN'f.EI'lDA TA for til~
'-'Pol"" ... w ...... " I.""
FETCH CCW
POINT TO BUFFER o BYTE COUNT
TEST BUFFER SWITCH BIT
USE BUFFER 0
POINT TO BUFFER 1-BYTE COUNT
FETCH BUFFER BYTE COUNT
COUNT+1 TO "OAT"
IF COUNT IS POSITIVE
SET V FLAG & EXIT (P.32)
STORE INCREMENTED COUNT. SET CC
DISABLE CC UPDATE
FETCH BUFFER END ADDRESS
ADD COUNT & FETCH HALFWORO
TEST R/W BIT
WRITE IF R/W = 1
MOVE fJ. BYTE TO THE BUFFER (READ)
STB
MDR.YO,MOR,DW2
L
BALG
OAT,DAT
RWSC1(NULL),lLIR,O
** EXECUTE NEXT
*
*RWSCl
NI
*RWSC2
*
*WRTSC
TEST INCREMENTED COUNT
USER INSTRUCTIOtJ IF COUNT NOT POSITIVE
BALZ
NULl.,CCW.FBIT
RWSC2(NULL),ILIR.D
IF "FAST" MODE, DO
NEXT USER INSTRUCTION
XI
L
L
MOR.CCW.BBIT
fIIIAR,TEMP,DW2
NULL,NULL,ILIR.D
IF COUNT HAS GONE POSITIVE.
COMPLEMENT BUFFER SWITCH BIT
L
LB
DEV,MDR
YO,DEV,MDR
DAi,OAi
RWSC1(NULL),ILIR,D
MOVE A BYTE FROM THE
BUFFER TO Rl
i..
BALG
**
........
MR5.TEMP,2
CCW.MDR
NULL,CCW,B8IT
SCP2(NULL)
MR5.TEMP,10
MAR.MR5,OR2
DAT,NULL,MDR
COUNT,MOR
LSTOVF(NULL)
MDR.OAT,OW2,E
L
NULL ,NULL
L
MAR,MR5.2
Al
NULL.NULL,DRQ
L
MAR,COUNT.MOR,DR2
A
NULL,CCW,RWBIT
NI
BALNZ WRTSC(NULL)
AI
L
NI
BALZ
AI
L
AINC
L
BALG
83216~10
TEST INCREMENTED COUNT
EXECUTE NEXT USER INSTRUCTION IF COUNT NOT POSITIVE
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equIpment and shall
not be used for any other purpose unless specifically authorized in writing.
83216'+20
&3216'+~O
83216qf4.0
83216ij.50
83216'+60
832161+70
83216~80
83216q90
83216500
83216510
83216520
83216530
832165QO
83216550
83216560
83216570
83216580
83216590
83216600
83216610
83216620
83216630
832166 .. 0
83216650
83216660
83216670
83216680
83216690
83216700
83216710
83216720
83216730
832167 .. 0
83216750
83216760
83216770
83216780
83216790
83216800
83216810
83216820
83216830
832168 .. 0
J.
MODEL 8/32 WITH DPFP
05-058F02A13
COPYRIGHT INTERDATA INC.
3Ce
3CE
3CF
300
301
302
303
30 ..
305
306
3209
363F
2A06
3606
32FF
1288
2BFF
503F
1121
6080
5017
1001
F7CO
IF99
3279 50FF
12B8 F5CO
2BFF 1F99
307
308
309
30A
363F
2A03
3606
32FF
1123
6080
5017
1001
308
30C
300
3DE:
3DF
3EO
3E1
3E2
3E3
3EI+
3E5
3E6
3E7
3E8
3E9
3EA
2206
2A06
2206
2A06
22D6
2A06
2206
2AD6
2206
2AD6
2206
2A06
22D6
2A06
2206
2AD6
8BDD
6880
8BOF
6880
88El
6880
8BE3
6880
8BE5
6880
8BE7
6880
3EB
3EC
3ED
17FC FBOO
287F lB03
03F8 OA80
88E.9
6880
SBES
6880
PAGE
'+2
APRIL 1916
1690
1691
1692
1693
169'+
1695
1696
16'7
1698
1699
1700
1701
1702
1703
170"
1705
1106
1701
1708
1709
1110
1711
1712
1713
171'+
1715
1716
1717
1718
1719
1720
1721
1722
1723
172'+
1725
1726
1727
1728
1729
1730
1731
1732
* CYCLIC REDUNDANCY CHECK
*CRC12A
NI
LI
X
NI
LI
SAL
L
*
*
CRC16A
NI
BAL
L
MR6,YD,'3Ft
MR1,COF01.I
MR6,MR6.MDR
MR6.MR6.LOHALF,I
MR7,l
CRCI2B(RETURN)
NULL,NULl.ILIR,O
MASK 6 8lTS
POLY CHECK
XOR IN RESIDUAL
MASK LS 16 BITS
DAT,YD.'FF'
CRCI6B(RETURN)
NULL,NULL,ILIR,D
LOAD BYTE
TO COMMON ROUTINE
*
* SUBROUTINE SHARED BY AUTO DRIVER
*
CRC16B
MR1.CAOO1.I
LI
MR6.0AT,MOR
X
MR6.MR6,LOHALF,I
NI
MR7.1
LI
*
*
SRLX MR6.MR6.MR7,*+2.C
MR6.MR6.MRI
X
SRLX MR6.MR6.MR7.*+2.C
MR6.MR6,MR1
X
CRC128
SRLX ~R6,MR6,MR7.*+2,C
MR6,MR6,I'IR1
X
SRLX MR6.MR6.MR7.*+2.C
MR6.MR6,flltR1
X
SRLX MR6,MR6,MR7,*+2.C
MR6,MR6.flltRl
X
SRLX MR6.MR6.MR7.*+2,C
fIIIR6.MR6.fIIIRI
X
SRLX MR6,MR6,MR7.*+2,C
filR6. MRfu MR1
X
SRLX MR6.MR6.MR7.*+2,C
MR6.MR6.fIIIRl
X
*
BALD
L
SAL
*+1(NULL)
MDR.MR6.0W2
(RETURN) (NULL)
CHANNEL
POLY CHECK
XOR IN RESIDUAL
MASK LS 16 BITS
OATA
YES.
DATA
YES.
DATA
YES.
DATA
YES.
DATA
YES.
DATA
YES.
DATA
YES.
DATA
YES,
& RESIDUAL EQUAL?
XOR IN FEEDBACK
& RESIDUAL EQUAL?
XOR IN FEEDBACK
& RESIDUAL EQUAL?
XOR IN FEEDBACK
& RESIDUAL EQUAL?
XOR IN FEEDBACK
& RESIDUAL EQUAL?
XOR IN FEEDBACK
& RESIDUAL EQUAL?
XOR IN FEEDBACK
& R~SIDUAL EQUAL?
XOR IN FEEDBACK
& RESIDUAL EQUAL?
XOR IN FEEDBACK
STORE RESULT
RETURN
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83216860
83216870
83216880
83216890
83216900
83216910
83216920
83216930
832169 .. 0
83216950
83216960
83216970
83216980
83216990
83211000
83217010
83217020
83217030
832170'+0
83211050
83217060
83217070
83217080
83217090
83217100
83217110
83217120
83217130
832171 .. 0
83217150
83217160
83217170
83211180
83217190
83217200
83217210
83217220
83217230
832172,.0
83217250
83217260
83217270
83217280
MOOEL 8/32 WITH DPFP
COPYRIGHT INTEROATA INC.
3EE
3EF
3FO
3F1
3F2
3F3
2A1F
285F
339F
28BF
3370
13EO
1080
1080
1980
5200
880E
3F'J
3F5
3F6
3F7
3F8
3F9
321F
2A1F
2B90
2A5D
2BFF
13EO
1002
1080
108A
lF80
1080
S800
3FA
3FS
3FC
3FD
3FE
3FF
339F
2A1F
2BBF
339F
296F
13F8
1088
1F8E
1080
108C
198E
83CO
1080
PAGE
05-058F02A13
'+3
APRIL 1976
173'+
1735
1736
1737
1738
1739
17'+0
17'+1
17"'2
17'+3
17'+'+
17"'5
111+6
17'+1
111+8
171+9
1750
1151
1752
1753
175'+
17~5
* L 0 A0
*
P R 0 G RAM
S T AT US
W0 R D
MR3.MDR,Ilf.OR'+
SET PSW ASioE IN MR3
L
LOC.MOR
L
TESTl
Ll
MAR.'80'
PSW,MR3
LOAD NEW PSW
L
TEST IF QUEUE SERVICE ENABLED
Nl
MDR,PSW.'200'
BALZ TWAIT(NULL),PR'+
TEST WAIT IF NOT (P.21)
* QUEUE SERVICE IS ENABLED. TEST THE QUEUE
QUEINT
LI
MRO.2
MR3.MOR
SAVE ADDRESS OF QUEUE
L
MAR,MRO.MOR,PR2
FETCH NO. USED HALFWORO
A
A
MR2.PSW.NULL
SAVE PSW
NULL,I"IOR
TEST TALLY
L
EXIT IF ZERO (P.21)
BALl TWAIT(NULL)
* QUEUE IS NOT EMPTY, 00 INTERRUPT
ADRS OF QUEUE SERVICE NEW PSW
MAR,'88'
Ll
FETCH NEW PSW
L
MRO.NULL,PRI+
PSw,MOR
LOAD NEW PSW
L
Ll
MAR,'SC'
R13.MR3,PR'+
REG 13= AORS OF QUEUE
L
COMIN2(NULL)
TO COMMON ROUTINE (P.21)
BAL
LPSW1
This information IS proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83217300
83217310
83217320
83217330
832173'+0
83217350
83217360
83217370
83217380
83217390
832171+00
83217'+10
83217 ... 20
83217'+30
83217"''+0
83217'+50
83217'+60
83217'+70
83217'+80
83217'+90
83217500
83217510
,"
COPYRIGHT INTEROATA INC.
~OO
'+00
'+01
'+02
'+03
""0,,"
'+05
'+06
407
'+08
'+09
'40A
0'+00
'+AFF 7Fao
321F
3210
2210
321F
,,"B70
17F5
1208
900'+
2FC3
1005
AFCO
2780
~OE
339F
28BF
369F
2A9 ....
367F
2893
323F
280F
"'OF
410
2B3F 1080
2301 lFq.F
~OB
.... OC
'+00
~11
q.12
,.13
"'1q.
~15
'+16
q.17
q.18
"'19
4+1A
q.1S
~lC
'+10
108'+
lF8A
1011
5D8F
1017
5080
OOOF
lF8F
33BD 1010
33F7
17E1
33BD
33FO
13£1
323F
37F7
17E1
CBF9
CBFe
2301
0.... 10
2B9F
50q.0
05q.O
7070
5080
03CO
OOOE
532B
07~0
8080
ADeo
lF5A
lF8F
'tlE
~lE
CBF9 20CD
~lF
2301 lF5E
q.20
't21
'+22
q.23
2B9F
2A3F
339F
2B5F
lAOF
1080
1028
108A
APRIL 1976
1757
1758
1759
1760
1161
1162
1163
116,+
1765
1766
1768
176'
1170
1171
1112
1773
ORG
''+00'
EQU
SII'lCR *
MR7.NULL
COLLECT MACHINE CONTROL REGISTER
* TWO MILLISECOND DELAY FOR SCLRO TO BE RELEASED ON LMI
DELAY
LI
MRO.'2D8'
SLLI fIIRO,MRO.,+
MRO
8320
SDECX MRO,MRO,NULL ••• C
SINGLE INSTRUCTION LOOP
MRO,5
LOAD UP LSU DEVICE NUMBER
LI
SSRA MDR,MRO.NULL
ADDRESS & SENSE STATUS
BALNV LOADLSU(NULL)
LSU EXISTS IF NO FALSE SYNC (P.51>
TLSU
=
* NO LSU, NORfIIAL POWER UP
*
MARt'8,+'
POWRUP
LI
1775
1776
1777
1178
1779
1780
1181
1182
1783
178~
1785
1186
1787
1788
1789
1790
1791
1792
1793
119'"
1795
1796
1797
1798
1799
1800
1801
180q.
1805
1806
1807
1808
1809
1810
N
MR,+,MR,+.MDR.DR~
FETCH psw SAVE POINTER
USE ONLY L5 16 BITS
FETCH REGISTER SAVE POINTER
LI
N
SI
L
MR3,LOHALF,I
MAR,MR3,IIIIOR
MR1,NULL.15
YOI.NULL,OR ....
USE ONLY LS16 BITS
MRl
'FFFFFFF1'
SELECT RO, FETCH FIRST
L
YD.~DR,I"'DR~
L
Ll
177~
•LLOOP
SEQUENCE
AX
PSW,NULL,PR2
MRI+.LOHALF.I
=
LOAO ONE, FETCH NEXT
YDI'MR1,YDI.LLOOP,C BUMP Rl FIELD, LOOP FOR 16 REGS
•* ONE REGISTER SET LOADED
*
ENDSET
*
L.DLOOP
ENDOLD
*
RESTRE
*
INCREfiIIENT REGISTER SET NUMBER
TEST IF 2 OR 8 REGISTER SETS
NULL,MR7.,q.O'
MCR BIT 9 = 0 IF 2 SETS
NI
BALNZ *+2(NULL)
MCR BIT 9
1 IF 8 SETS
PSW,PSW,'70'
01
IF ZERO, FORCE LAST SET
NI
NULL,PSW,'80'
TEST IF LAST SET LOADED
BAL.Z LLOOP(NULL)
LOOP UNTIL. AL.L SETS LOADED
MR1='FFFFFFF2t
51
MR1,NULL.1,+
Nt
NULL,MR7,BIT20.1
TEST MCR BIT 4+
BALNZ ENODLOCNULL)
SKIP IF NO OFU
YO.MOR.I,+DR,+
LW
LOAD 32 BITS, FETCH NEXT
YDP1,MOR,I4+0R~tK
LD
LOAD LS 32 BITS
AX
YDI,MR1,YOI,LOLOOP,C POINT TO NEXT HALF REG, LOOP
EQU
*
L
MAR,NULL.ORIf.
FETCH FLOATING REGISTER 0
AI
PSW,PSW,'10'
=
IFNZ
LE
ENOC
AX
OFU
YD.MDR.lq.ORq.,K
L
MAR.MRIf..ORq.
MR1,MDR.l'+DR't
MAR,'28'
I.,.OC,MOR,PR2
L
LI
L
LOAD ONE, FETCH NEXT
YDI,MR1,YDI.RESTRE.C
FETCH SAVED PSW
FETCH SAVED LOC
LOAD LOC, FETCH
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83211530
832175'+0
83217550
83217560
83217570
83217580
83217590
83217600
83217610
83217620
832176'+0
83217650
83211660
83217610
83211680
83211690
83217700
83217710
83217720
83217730
83217140
83211750
83217760
83217770
83211780
83217790
83211800
83217810
832i1820
83217830
832178 .. 0
83217850
83217860
83211870
83217880
83217890
83217900
83217910
83211920
83217930
8321791+0
83211950
83217960
83217910
83218000
83218010
83218020
83218030
832180'+0
83218050
83218060
MODEL 8/32 WITH CPF?
COPYRIGHT INTEROATA INC.
'1026
1+27
'4028
1+29
'+2A
'1028
q.2C
1+20
'+2E
1+2F
13F8 8800
1811
1812
1813
181'10
1815
18Ui
1817
1818
1819
1820
1821
1822
1823
182'+
2873 6083
13F9 2000
1826
1827
1828
1829
1830
1+30
1+31
1880
CDC2
1001
AFCO
5200
9Bq.O
1080
50EO
98'100
5329
81+CO
'405
APRIL 1976
2BBF
I+B7F
323F
I+SFl
33F7
17EO
2A3F
33F1
17EO
37FO
17EO
'1024
1+25
PAGE
05-058F02A13
*
** LONGITUDINAL
*LRC
X
*
L
ST8
L.I
SSRA
NI
BALNZ
L
NI
BALNZ
NI
BAL.NZ
PSW,,.,Rl
MDR,NULL.MOR,PW2
MR1.1
NULL.,.,Rl.NULL
NULL.MR7.'200·
L.OCDISCNULL)
MR1.MDR
NULL,MR1,'OEO'
LOCDIS(NULL.)
NULL,PSW,BIT18,I
MMFINTCNULL)
BAL
TWAITCNULL)
BAL
TEST STATUS BITS 1.2.3
SHOW L.OC. GO TO IOLE (P.2'40)
TEST MALF ENABLE
MACHINE MALFUNCTION (P.21)
INTERRUPT IF ENABLED
TEST PSW WAIT BIT (P.21)
83218070
83218080
83218090
83218100
83218110
83218120
83218130
8321811+0
83218150
83218160
83218170
83218180
83218190
83218200
EXCL.USIVE OR CHECKSUM
(P.'409)
83218220
83218230
832182'100
83218250
83218260
SAVED CONSOLE STATUS
LOAD PSW
CLEAR HiGH BYTE OF '00028'
ADDRESS THE DISPL.AY
TEST MCR BIT 6
IDLE IF INITIAL.IZE SWITCH (P.2'40)
CHECKSUM
MOR,DAT.MDR.DW2
RTNCRC(NULL.)
This information is proprietary and is supplied by INTERDATA for the sole
Y'aall
purpose of using and maintaining INTERDATA supplied equipment and
not be used for any other purpose unless specifically authorized in Wfltlng.
MODEL 8/32 WITH DPFP
05-058F02A13
COPYRIGHT INTEROATA INC.
0080
0010
0008
000'+
0002
0001
'+32
'+33
'+3'+
'+35
'+36
289F
289F
2A5F
33F2
13E1
1008
1000
IDAD
5080
1280
'+37
'+38
'+39
'+A7F E9'+0
2BE3 5980
17El 13CO
'+3A
'+3B
33F2 5001
13E1 17CO
32Qq.
2B9F
3390
2A9F
13E9
2B9'+
1002
180B
1002
1080
15q.F
1D8B
'+'+2
'+3FF EFDl
'+'+3
'+'+'+
33F2 500'+
17E1 17'+0
'+6
APRIL 1976
1832
*
AUT 0
183'+
1835
1836
1837
1838
1839
18'+0
18'+1
* CCW
*EBIT
BIT DESIGNATIONS
18'+3
18'+'+
18'+5
18'+6
18'+7
18'+8
18'+9
1850
1851
1852
1853
185'+
1855
CHANEL
1857
'+3C
'+30
'+3E
'+3F
'+'+0
'+'+1
PAGE
1859
1860
1861
1862
1863
186'+
1865
1866
1867
1868
1869
1810
1871
1872
1873
187'+
1875
1876
1877
CBIT
BBIT
RWBIT
:rBIT
FBIT
*
*
o R I VE R
C HAN N E L
EQU
EQU
EQU
EQU
EQU
EQU
'80'
'10'
'08'
'0'+'
'02'
'01'
EXECUTE
CHECK TYPE
BUFFER SWITCH
READ/WRITE
TRANSLATE
FAST MODE
L
L
L
NI
BALZ
MAR.LOC,DRa
R'hLOC
Ctw,MDR.E
NULL.CCW.EBIT
£)(SU81CNULLJ
FETCH CHANNEL COMMAND WORD
REG '+
ADRS FORCED EVEN OF cca
OAT,CCW
NULL,R3,OAT
BALNZ EXSUB2CNULL)
EXB
N
*
83218?80
*
Nt
BALZ
NULL,CCW,FBIT
NFAST(NULL)
F AS T
*
AI
L
AI
L
BALG
A
-.
ISOLATE STATUS MASK
TEST DEVICE STATUS AGAINST MASK
BAD STATUS (P.lt7)
TEST IF FAST MODE
NOT FAST MODE (P.,+S)
*
ADRS BUFFER o ByTE COUNT
FETCH IT
EXIT, COUNT POSITIVE (P.'+7)
BUFFER END ADDRESS + COUNT
BUFFER 0 BYTE COUNT IN REGISTER "COUNT"
** ADDRESS OF BUFFER 0 BYTE COUNT IN "TEMP"
* BUFFER 0 END AORS + BYTE COUNT IN "MAR"
* BYTE/HALFWORD TO TRANSFER IN "MOR"
*
THWX NULL,NULL,BYTEIO,C TEST HW I.INE
** FALL THROUGH IF LINE IS ACTIVE
*
NULL.CCW,RWBIT
TEST R/W BIT
NI
*
=
TEST THE EXECUTE BIT
NO EXECUTE, Cc=o (P.'+7)
IF FALL THRU. £=1 & CC=0010
lit
BALNZ HWRT1(NULL)
= MRO
= MRl
= MR2
MR3
= MR'+
MR5
=
MOD E
TEMP,R,+,2
MAR,TEMP,DR2
MAR,TEPlP,2
COUNT,MOR
EXAUTOCNULL),DR,+
MAR,COUNT,MOR.DR2
TEMP
DEV
CCW
OAT
COUNT
RETURN
CP."7)
WRITE HW, RW=l (P.'+7)
This informatIon is proprietary and is supplied by INTERDATA for the sale
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83218300
83218310
83218320
83218330
832183'+0
83218350
83218360
83218310
83218390
83218'+00
83218 .. 10
83218'+20
83218'+30
83218,+40
832181+50
83218'+60
83218'+70
832181+80
83218'+90
83218500
83218510
83218530
83218550
83218560
83218570
83218580
83218590
83218600
83218610
83218620
83218630
832186'+0
83218650
83218660
83218610
83218680
8321869Q
83218100
83218710
83218720
83218730
MODEL 8/32 WITH DPFP
COPYRIGHT INTERDATA INC.
't&lo5
1+'+6
1+'+7
1+&108
1+'t9
'+B7F
3291+
2B9F
2B7F
17E9
I+F83
1002
1800
lA03
lSI+O
PAGE
05-058F02A13
47
APRIL 1976
1878
1879
1880
1881
1882
1883
188'+
HRDWT
COMMON
**
MOR,NULL,DW2
COUNT.COUNT,2
jiiiAR,TEjilP
i..
MDR,COUNT,DW2
L
BAlNG EXAUTO(NULL)
RH
AI
READ HALF WORD
INCREMENT OF BUFFER
o
BYTE COUNT
RE.ADORESS SUFFER BYTE ...,.."'118.'.
"''''''''
EXIT IF NOT POSITIVE
EXIT TO SUBROUTINE IF COUNT HAS BECOME POSITIVE
83218740
83218750
A2~
.. A"L'"
g\l
...... C;4 ... r
83218770
83218780
83218790
83218800
• !
q.q.f
'4050
3380 5FFO
23BO 3F8A
q.S1
'+52
33F2 SOOI+
17£1 1780
1896
1897
1898
'+53
itB7F 0083
1&99
'+5'+
2291+ 3F87
1900
1901
1902
*
*
FROWT
AINCX COUNT.COUNT,NULL.COMMON INC. BUFF
'4055
1+56
1+57
1+58
1+59
'+5A
q.SB
1+5C
2B5F 1080
2BBF 1000
321F 1008
I+AFF 7F8C
33F7 S007
17EO 8500
37FD 5327
17EO AFOO
190'+
1905
1906
1907
1908
1909
1910
1911
EXAUTO
I.
L
L.I
SMCR
450
'+3FF 5086
1913
191'+
1915
1916
HWRTl
WHX
WOX
I+SE
1+3FF 1094
E.XSUB1
AI
L
REG q. : ADRS OF CCB
FETCH SUBROUTINE ADDRESS
TEMP='OOOOFFFEo
3381+
2BFF
361F
2B50
28FF
1011+
IF8B
1039
S080
IF9C
1886
1887
1888
1889
1890
1891
1892
1893
189..
I'1AR,R 1h20
NULl,NULL.OR2
TEMP,CFFFE.I
LOC.TEMP,MOR
NULl,NULL.IR,D
1+1+ A
4 &loB
't'+C
,+ .. 0
q.q.E
LI
N
L
FETCH USER INSTRUCTION
*
*
EXSUB2
BYTEIO
*
.**
FWRIT
PSW,PSW.'FFO'
CLEAR CC THEN
AINCX PSW,PSW,NULL,EXSUBl SET I. FLAG (BAD STATUS)
''41
BYTE COUNT
83218920
83218930
8321891+0
83218950
83218960
83218970
83218980
RESTORE L.OC
RESTORE PSW
QUEUE C FLAG
SENSE MACHINE CONTROL. REG.
TEST FOR EPF OR PARITY ERR
MACHINE MALFUNCTION (P.21)
TEST WAIT BIT
TO WAIT IF SET (P.28)
83219000
83219010
83219020
83219030
832190&+0
83219050
83219060
83219070
NULL,MOR,HROWT
WRITE HAFLWORO
NULI.,MOR.FROWT
WRITE A BYTE
83219090
83219100
63219110
83219120
NUI.I.,CCW,RWBIT
NI
BAL.NZ FWR I TC NULL)
RC
83218820
83218830
832188... 0
83218850
83218860
83218870
83218880
83218890
83218900
MORiMORiOW2
LOC.Rl
PSW.RO
MRO.8
MR7.NULL.IR
NULL,MR7.7
NI
BAL.NZ ""F1CHULL)
NI
NULL,PSW.BIT16.1
BAI.NZ WAIT(NULL),O
TEST R/W BIT
WRITE BYTE IF RW == 1
READ BYTe:
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
o
~..,.~
MODEL 8/32 WITH OPFP
COPYRIGHT INTEAOATA INC.
'+5F
'+60
'+61
'+62
'+63
'+6'+
'+65
'+66
'+67
'+68
'+69
321F
33F2
13El
321F
298'+
2AO'+
3390
2A9F
13E9
285'+
2B9F
1002
5008
18CO
100A
180B
1800
1002
108F
15'+0
1080
100B
33F2 500'+
17E1 lCCO
'+6C
&fo60
'+6E
'+6F
'+A7F
2ABF
33F2
16EO
'+70
'+71
'+72
2B9F 100B
'+873 COC3
227F lABe
'+73
'+74
2A7F
'+A73
33F2
16EO
'ns
'+76
'+77
'+78
'+79
'+7A
OFCO
1980
5002
DF'+O
1080
OOCO
5002
OF'+O
'+BFF 19CO
338'+ 1008
2BFF IF8B
33F2 5010
PAGE
05-058F02A13
,+8
APRIL 1976
1918
*
1920
1921
1922
1923
192'+
1925
1926
1927
1928
1929
1930
1931
1932
1933
193'+
1935
1936
1937
1938
1939
19'+0
19'+1
19'+2
19'+3
19'+'+
19'+5
19'+6
19'+7
19'+8
19'+9
1950
NFAST
NOR MAL
*NFASTl
SET UP FOR BUFFER 0
TEST BUFFER SWITCH BIT
A
A
MAR,R,+.TEMP,DR2
TEMP,Rq..TEMP
MAR,TEMP.2
COUNT.MDR,OR'+
EXAUTO(NULL)
L.OC,COUNT,MOR
MAR,LOC.OR2
FETCH BUFFER BYTE COUNT
TEMP
AORS OF BUFFER BYTE COUNT
A
SET UP FOR BUFFER 1
=
FETCH BUFFER END ADDRESS
EXIT IF COUNT POSITIVE (P.'+7)
BUFFER END AORS + COUNT
BUFFER BYTE COUNT IN REGISTER "COUNT"
ADDRESS OF BUFFER BYTE COUNT IN "TEMP"
BUFFER END AORS + BYTE COUNT IN "~AR"
BYTE/HAL.FWORD TO TRANSFER IN "MOR"
NOTE: IN NON-FAST MODE, ONLY BYTE TRANSFERS ARE ALLOwED
*
*
19~1
1953
195'+
1955
1956
1957
1958
1959
1960
1961
1962
1963
196'+
1965
1966
1967
TEMP.2
NUL.L.CCW,BBIT
NFAST1(NULt..)
TEMP,10
L.
*
*
**
*
*
832191'+0
*
LI
NI
BALZ
LI
AI
L.
BAL.G
**
*
MOD E
NFWRIT
NI
NUL.L.CCW.RWBIT
BAL.NZ NFWRITlNUL.L)
TEST R/W BIT
WRITE A BYTE IF R/W
RDR
L.
OAT,NULL
RETURN.DAT
NI
NULL.,CCW.TBIT
BALNZ TRANSL(MR7)
INPUT THE BYTE
SAVE IT
TRANSLATION REQUlREO ?
DO IT (P.38)
L.
STB
LX
RE-FETCH HALFWORD
INSERT ByTE
OAT
UNTRANSLATED BYTE
MAR,L.OC.DR2
MOR.UAT.MDR.DW2
DAT,RETURN,REDCHK
OAT,MOR
LB
DAT.DAT.MDR
NI
NULL..CCW,TBIT
BALNZ TRANSL(MR7)
=
L
BYTE TO OUTPUT
TEST TRANSLATE BIT
DO IT (P,38)
** TRANSLATION NOT REQUIRED
*
WOR
NULL,OAT
OUTPUT THE BYTE
** ONLY THE BYTE ACTUALL.Y TRANSFERRED IS INCLUDED IN
* LRC OR CRC. SPECIAL CHARACTERS ARE NOT INCLUDED.
*REOCHK AI
MAR.RI+,8
L
NI
NULL,NUL.L,OR2
NULL.,CCW.CBIT
FETCH CHECK.WORO
CHECK TYPE BIT
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
THE
=1
83219160
83219170
83219180
83219190
83219200
83219210
83219220
83219230
832192'+0
83219250
83219260
83219270
83219280
83219290
83219300
83219310
83219320
83219330
832193'+0
83219350
83219360
83219370
83219380
83219390
83219'+00
83219'+10
83219'+20
832i9'+30
83219'+140
83219'+50
83219'+60
83219'+70
832191+90
83219500
83219510
83219520
83219530
832195'+0
83219550
83219560
83219570
83219580
83219590
83219600
83219610
83219620
83219630
MODEL 8/32 WITH DPFP
COPYRIGHT
INTERDAT~
'4-7B
13E1 OCOO
'4-7C
'4-70
'4-7E
1+7F
I+AFF 7Feo
'4-80
481
'+82
2B9F 1800
2871+ 3F83
17£9 15'f.0
483
'4-84
'4-85
3372 6008
2B9F 1203
13F9 1280
33F7 5'4-00
13E1 1+000
12B8 F5CO
PAGE
05-058F02A13
INC.
flo 9
APRIL 197&
1908
3.9&9
1970
1971
1972
1973
1975
1976
1977
1978
1979
1980
1981
BALZ
*
SMCR
Nt
BALZ
NOASSIST SAL
RTNCRC
*
LRC(NULL)
LONGITUDINAL CHECKSUM (P.1+5)
MR7.NULL
NULL.MR7.''+OO'
HWASSISTlNULL)
CRC168(RETURN)
TEST MCR BIT 5
IF ZERO. USE HW ASSIST
CYCLIC REDUNDANCY CHECK (P.1+2)
MAR.TEMP
L
AINC MDR.COUNT.NULL.DW2
BALNG EXAUTO(NULLl
XI
L
SAL
MDR.CCW.BBIT
MAR,RI+.DW2
EXSUB1(NULL)
INCREMENT & STORE COUNT
EXIT IF NOT POSITIVE (P.1+7)
COMPLEMENT BUFFER SWITCH BIT
RESTORE CCW
EXIT TO SUBROUTINE (P.'+7)
This information is proprietary and is supplied by INTERDATA for the sole
purfXJse of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in Writing.
8321961+0
83219650
83219060
83219670
83219680
83219690
83219710
83219720
83219730
83219740
83219750
83219760
83219770
MODEL 8/32 WITH OPFP
05-058F02A13
COPYRIGHT INTEROATA INC.
't86
32FF 1800
'tS7
't8S
2AF7 1FOO
03FS OB80
0~89
't89
'tSA
'tSB
'+SC
'+SD
't8E
'tSF
2B9F
3210
2A5F
3FF2
2A31
2021
28FF
l80F
OOO~
lD60
OSSO
2F80
2FC9
lF99
O~90
'+90
~91
~92
.. 93
.. 9Cf.
.. 95
.. 96
~97
.. 98
~99
'+9A
'+98
'+9C
Cf.90
289F
2F1F
3210
2A31
2063
2BFF
321B
2A10
2A38
2A5F
13E1
33F2
13El
17FC
lS00
1881
000 ....
2F80
2FDO
lF99
9002
lCOO
1C80
lFOO
22'+0
6002
2Cf.00
82Cf.0
PAGE
50
APRIL 1976
1983
198'+
1985
1986
1987
1988
1989
1990
1991
1992
199 ..
1995
1996
1997
1998
1999
2000
2001
2002
2003
200'+
2005
2006
2007
200S
2009
2010
2011
2012
2013
201'+
2015
2016
2017
2018
2019
2020
2021
2022
2023
202'+
2025
*
WRITABLE CONTROL STORE INSTRUCTIONS
*
** ENTER
*ECSl
*
CONTROL STORE
Ll
MR1,'800'
A
BAL
MR7.MR7,YDI
(MR7)(NULL)
* READ/WRITE
*
EQU
WDCS
CONTROL STORE
*
WDCSl
*MAR,MRO.DR'+
MRO,MRO."
MR2,MDR
L
MR2,MR1
STR
SDEC fIIIR1,MR1,NULL
SOECX 1,1,NULL,WDCS1.C
NULL,NULL,ILIR,O
L
L
SI
SELECT THE FIRST DCS
MODULE AT AORS '800'
ADO Rl FIEL.D
BRANCH TO ONE FIRST
SIXTEEN L.OCATIONS IN DCS
FETCH FUL.L.WORD
DECREMENT MEMORY ADDRESS
COpy DATA TO MR2
AND STORE IN DCS
DECREMENT DCS ADDRESS
DECREMENT COUNT
EXIT IF aONE
*
*
RDCS
RDCSl
EQU
*
MAR,MRO
MDR,MR1,I.DWCf.
MRO.MRO .....
SI
SDEC fIIIR1,MR1,NULL
SOECX 3,3.NULL.RDCS1,C
NULL.NULL,ILIR.D
L
L
L
*
** (Rl)=DCS ADORESS,(Rl+1)=COUNT.
*
*
CCSl
SLLI MRO,YDP1,2
A
A
A
BALZ
XI
BALZ
BALD
MRO.MRO.ys
MR1. YDPt. YO
MR2.NUL.L.YDI
WDCS(NULL)
NULL,MR2.2
RDCS(NULL)
ILEGALCNULL.)
MOVE DCS DATA TO MAIN MEMORY
DECREMENT MEMORY ADDRESS
DECREMENT DCS ADDRESS
DECREMENT COUNT
(R2)=MAIN MEMORY ADRS
'+X COUNT
PL.US MEMORY ADDRESS
MR1=COUNT PL.US DCS ADDRESS
TEST Rl FIELD
0= WRITE DCS
2= READ Des
IL.LEGAL FUNCTION (P.21)
83219790
83219800
83219810
83219820
83219830
832198'+0
83219850
83219860
83219870
83219S80
83219900
83219910
83219920
83219930
83219940
83219950
S3219960
83219910
83219980
83219990
83220000
83220010
83220020
83220030
83220040
832200!50
83220060
83220070
83220080
83220090
83220100
83220110
83220120
83220130
832201'+0
83220150
83220160
83220170
83220180
83220190
83220200
83220210
\
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically author~zed in writing.
MODEL 8/32 WITH DPFP
05-058F02A13
COPYRIGHT INTEROATA INC.
~,..~e
...
v ... ..,
nltO~
,#1(..
u""
339F
1209
2BBF
1209
2B5F
1209
2A5F
1209
~A6
q.A7
23Fl 0968
13F8 9D'f.O
'f.A8
'f.A9
'f.AA
'f.AB
'f.AC
'+AO
289F
4B7F
13F'+
2A52
23Fl
13F8
'0'+0
q.AE
'loAF
&JBO
&JB1
q.A30
'+A3F
q.A30
03F8
8FCO
E8CO
8880
OBOO
1001
2880
1880
2880
1880
2880
1880
2880
190B
0080
3F83
0968
8800
51
APRIL 1976
2027
2028
q.9E
'f.9F
q.AO
q.A1
q.A2
q.A3
'f.A4
'f.A5
PAGE
2030
2031
2032
2033
203'+
2035
2036
2037
2038
2039
20'100
20141
20'f.2
20'f.3
20q.,+
20'+5
* LOADER STORAGE
*
........ *
.. W"w ..
t
nAn. COil
~..,.
*AUTOl
AUT02
READIT
HDRA
EXB
20'+7
20'109
2D50
2051
2052
SX
BAL
L
RO
BALV
AINC
SX
BAL
20'+6
83220230
832202'100
E:"nll
LI
BAL
L
BAL
L
BAL
L
BAL
*
UNIT INPUT
ROA
BAL
83220250
MAR.1
READrT(MR6)
PSw.MRl
REAOIT (P4R6)
LOC,MR1
READIT(MR6)
MR2.MR1
REAOIT(MR6)
MRl
END ADDRESS
NULL,MRloMR2iAUT01,C COMPARE START & END
IDLE(NULL)
IDLE IF START NOT LESS (P.2'+)
THAN END AODRESS
MAR.MR2.DR2
MDR,MOR
INPUT DATA BYTE
IDLElNULL)
IDLE IF BAD STATUS (P.2'f.)
P'tR2.MR2.NULL.DW2
INCREMENT START ADRS
NULL,MR1,MR2.AUT01,C LOOP TILL REACH ENO ADDRESS
T~AIT(NULL)
TEST NEW PSW (P.21)
83220260
83220270
83220280
83220290
83220300
83220310
83220320
83220330
832203'+0
83220350
83220360
83220370
83220380
83220390
83220'+00
83220'+10
83220'+20
83220'+30
MR1.I"IRO,NULL
JIIIR1.MR1
MR1,MRO.JIIIRl
(MR6) (NULL)
83220'f.SO
83220'1060
83220'1070
83220'1080
PSW 16:31
LOC 16:31
START ADDRESS
=
INPUT filS BYTE
LEFT 8
INPUT LS BYTE
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
MODEL 8/32 WITH OPFP
05 .. 058F02A13
COPYRIGHT INTEROATA INC.
lEOO
9C87
3FOO
9C85
1F9C
'+B2
1+83
I+B'+
I+B5
'+B6
289F
CB7F
2BOF
CB7F
2BFF
I+B7
I+B8
'+B9
323F OOOF
1208 '+3CO
CB1F 9C85
'+BA
'+BB
'+BC
'+BO
'+BE
'+BF
CBF9
323F
CBFB
2BOl
13FO
13F9
8080
DOOE
ADCO
lFOO
'+'+80
2E80
'+CO
'+Cl
'+C2
'+C3
'+CI+
'+C5
'+C6
'+C7
'+C8
&f.C9
2ADF
2BOF
CA7F
3230
3273
3251
3273
2A52
2BOF
13FB
lFOO
3E80
9C80
8008
B008
5FOO
50FF
7980
1800
E2CO
PAGE
52
APRIL 1'76
205,+
2055
2056
2057
2058
205'
2060
2061
2062
2063
206'+
2065
2066
2067
206e
2069
2070
2071
2072
2073
207'+
2075
2076
2077
2078
2079
2080
ST01
MAR.MAR
MOR,YO,OWI+
VOI,NUlL,VOI
MDR.VO,I'+DWI+
NULL.NULL,IR,O
EFFECTIVE ADDRESS TO MAR
STORE MS 32 BITS
POINT TO LOW HALF
STORE LS 32 BITS
RRO
MR1.NULL,15
COMSTM(MR6)
MDR,VO.l'+OW'+
MR1=tFFFFFFFl t
TO COMMON ROUTINE (P.lO)
EXECUTEQ INSTRUCTION
LW
SI
LO
A
BALC
SAL
YD.MDR,I'+OR'+
MR1.NULL.l,+
YOPltMOR,K
VDI,MR1.VOI
EXLSTMlNULL).I,+OR,+
LMDl(NULL)
LOAD MS 32 BITS. FETCH LS 32 BITS
SET MRl = 'FFFFFFF2'
LOAD LS 32 BITS
INCREMENT Rl FIELD BV 2
EXIT IF FINISHED
ELSE, FETCH NEXT 32 BITS
L
AINC
RRO
RLI
RLI
NI
MR6,YOI
YOI,NULL,YSI
I"IR3,YD
I"IR1,MRQ.8
MR3.I'IIR3,8
MR2,MR1.'FOO·
MR3,fIIIR3,'OFF'
MR2.IIIR2.MR3
VDI,MR6
FXDR2(NULL)
POINT TO R2+l
MRO.MR3=ARGUI"IENT
ROTATE MS 32 BITS
ROTATE LS 32 BITS
FRACTION BITS 0:23
FRACTION BITS 2'+:31
COMBINED (8 HEX DIGITS)
RESTORE Rl FIELD
(P.39)
L
RRO
AINC
RRD
•
STMOl
*
L..,01
*
FXDRl
L
SI
BAL
NI
0
L
SAL
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized .A writing.
83220500
83220510
83220520
83220530
832205'+0
83220550
83220560
83220570
83220580
83220590
83220600
83220610
83220620
83220630
832206'+0
83220650
83220660
83220670
83220680
83220690
83220700
83220710
83220720
83220730
832207'+0
83220750
83220760
MODEL 8/32 WITH DPFP
COPYRIGHT INTERDATA INC.
'4oCA
'+C8
'+CC
'4oCD
'+CE
'+CF
'+00
'+01
CBF9
2A3F
13(1
13E9
3610
2A3F
CBF9
of.l.0 1
C~F8
8F80
1C29
3'+'+0
3'+00
1133
0880
8800
A890
PAGE
05-058F02A13
APRIL 1976
2082
2083
208'40
2085
2086
2087
2088
2089
2090
2091
2092
2093
209'+
*
*
*
CONVERT FIXED-POINT DATA TO FLOATING POINT
FLDR1
FLOR2
ZEROD
YD.NULL
MR1.YS.ILIR,E
ZEROD(NUL.L.)
FLOR2(NUL.L.)
MRO,MRO.8ITO,I
MR1.NULL,MR1
YO,MRO
*
YDP1,I'1Rl,D
*
* PART
*
SETV
2102
TS2
3380 7002
26BO 3F80
2BBD 3F90
'+05
2B7F 2F83
2cFF lF69
2103
...
2105
IFNZ
OFU
f.l.D7
NO-OP
ARGUMENT TO !I1Rl
EXIT IF ZERO
SKIP IF POSITIVE
CONSTANT BECOMES NEGATIVE
2'S COMP ARGUMENT
MS 32 8ITS
ARGUMENT=L.S 32 8ITS
NORMAL.IZE THE wHOLE THING
OF LRA INSTRUCTION
'+02
'+03
'+Df.I.
SETG
SETL.
83220780
83220790
t.l"'~",",Oft"
g",c;.c;.ucul,l
LW
L
BAL.Z
BAL.G
Al
S
LW
EQU
LO
2096
2097
2098
2099
2100
't06
53
= '2+
=
PSW,PSW,2
PSW,PSW,NULL
PSW,PSW,NULL.O
SET CC
SET CC
SOEC
MDR,NULL.NULL,Dw2
I
NULLiNULLiILIRiE~O
WRITE ALL ONES IF NOT SET
CLEAR CC; FETCH NEXT !NSTR
01
AINC
AINC
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTEADATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing
83220810
83220820
83220830
832208'+0
83220850
83220860
83220870
83220880
83220890
83220900
83220920
83220930
832209'+0
83220950
83220960
83220980
83220990
83221010
MODEL 8/32 WITH DPFP
05-058F02A13
COPYRIGHT INTEROATA INC.
~D7
~D8
~O9
~OA
~DB
~DC
~OD
2A3F
13E1
13£9
3610
2A3F
CBFF
CBF9
lC29
3780
3700
1133
0880
8800
2890
tBF9 2F90
5~
APRIL 1976
2107
2108
2109
2110
2111
2112
2113
211~
~DE
PAGE
2115
FLRl
FLR2
•ZEROE
L.
BALZ
BALG
AI
S
LW
L.t
MR1.YS,ILIR.E
ZEROE(NULL)
FLR2(NULL)
MRO.MRO,BITO.I
MR1.NULL.MR1
NULL..MRO
YO,MR1.D
L.t
YO.NULL,D
ARGUMENT TO MRl
EXIT IF ZERO
SKIP IF POSITIVE
CONSTANT BECOMES NEGATIVE
2'S COMP ARGUMENT
MS 32 BITS CONSTANT
ARGUMENT
LS 32 BITS
NORMALIZE THE WHOLE THING
ZERO RESULT
=
This Information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83221030
832210~O
83221050
83221060
83221070
83221080
83221090
83221100
83221110
MODEL
8/32
WITH DPFP
05-058F02A13
COPYRIGHT INTERDATA INC.
'+DF
500
501
502
0006
32DF 1006
32F2 8005
32F7 5001
50q.
505
506
503
't-BF6
q.BFF
q.SFF
q.e7F
507
13F9 2000
508
aaCe
5080
19CO
I+F83
3219 8010
SOA
3a3F 1006
'+BF1 1:$81+0
508
SOC
'+BFF 5080
ItSFF leca
500
'+B7F '+F83
50£:
28FF lF99
509
50F
510
321' 8010
323F 1006
Be'+o
511
~BFl
512
't-SFF 5COO
513
.. SFF lCC9
51'+
'15
516
'+A1F '+F80
3118 5015
2B18 7810
PAGE
55
APRIL 1976
2168
ENDC
21'10
ORG
2171
2172
2173
217't2175
2176
2177
2178
2179
2180
EQU
CRC
HWASSIST LI
SRLI
NI
2182
2183
218'+
2185
2186
2187
2188
2189
21'0
2191
2192
2193
219'+
2195
2196
* PROCESS BYTE
*
SRLI
PSl
2198
2199
2200
2201
2202
2203
220'+
2205
2206
2201
2208
2209
2210
2211
2212
2213
*
~Suu!
X'06'
MR6.CRC
MR7.CCW.5
MR7.MR7.1
OCRA NULL,MR6.MR7
. rtULL,Mf)R
WH
NULL,OAT
WOR
MOR,NULL,OW2
RH
RTNCRC(NULL)
SAL
RX
MRO.YD,16
*
*
*
*
*
*
LI
OCRA
MR1.CRC
NULL,MR1.MRO
WH
WOR
NULL.MDR
NULb,YO
RH
MDR,NULL,DW2
L
NULL,NULL,ILIR,D
* PROCESS BYTE
*
PBRl
S8l1
*
*
*
MRO,YD,16
LI
OCRA
MR1.CRC
NULL,MR1.MRO
WH
NULL.yS
WOR
NULL,YD,ILIR
RH
MRO,NULL
YS, YS,HIHAL.F. I
YS.YS,MRO,O
NI
0
83221780
BITS 8115 OF THE REGIST£R
SPECIFIED BY Rl CONTAIN A
CONTROL CODE INDICATING
TYPE OF ERROR CHECKING TO
BE PERFORfiIIEO. ADDRESS THE
CRC HARDWARE & OUTPUT THE
CONTROL INFORMATION TO IT.
OUTPUT OLD RESIDUAL
OUTPUT THE DATA BYTE IN R1
TO BE INCLUOE~·IN THE· ERROR
CHECK. INPUT THE RESULT
AND STORE IT.
FETCH NEXT INSTRUCflON
RR
*
*
*
HARDWARE ASSIST DEVICE NUMBER
(MR6J=CRC DEVICE NUMBER
POSITION CRC TYPE BITS
(MR7) ~ 0 IF CRC16
(MR7) = 1 IF SOLC
ADDRESS CRC ASSIST~ SEND CONTROL
OUTPUT OLORESIDUAL
OUTPUT NEW DATA BYTE
INPUT & STORE RESULT
(P."9)
832216 .. 0
83221660
83221670
83221680
83221690
8322170083221710
83221720
. &!221130
832217 .. 0
83221750
83221760
BITS 0115 OF lHEREGISTER·
SPECIFIED BY Rl CONTAIN A
CONTROL CODE INDICATING
TYPE OF ERROR CH[CKIN&'f&BE PERFORMED. ADDRESS THE
CRC HARDWARE & OUTPUT THE
CONTROL INFORMATION 10 IT
OUTPUT OLD RESIOUALFRO"
R2 BITS 16:31.
OUTPUT DATA eYTE· FROM R2
TO BE INCLUDED IN THE
ERROR CHECK. INPUT THE
RESULT ANO' STORE IN Ri 1&+31
WITHOUT CHANGING BITS O11~
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA .supplied equi~en~ and .s~1I
not be used for any other pur(X)Se unless specifically authOrized
In Writing.
83221790
83221800
81221810
83221820
83221830
832218 .. 0
83221850
83221860
83221870
83221880
8a.221S'O
83221900
83221'10
aa221920
832219 .. 0
83221950
83~l,"
83221910
83221980
·sa2t1"O
83222000
83222010
81222a2-O
83222030
832220'0
8!~2t&SO·
83222060
83222070
832220ao
83222090
MODEL 8/32 WITH DPFP
OS .. OS8F02A13
COPYRIGHT INTERDATA INC.
517
269F lC80
S18
519
51A
3306 1002
2A19 8FCO
13E'+ C3'+8
519
3610 5017
51C
510
51E
51F
520
521
522
523
52'+
525
526
527
528
3239
325F
33Fl
17E1
3306
'+~F2
'+BFF
3306
33Fl
13El
33Fl
15El
13F9
8010
1006
5'+00
5680
1003
M8Ca
5C80
1001
5800
5BtQ
5200
5080
'+A80
APRIL
2215
2216
2217
2218
2219
222Q
2221
2222
2223
2221+
2225
2226
2227
2228
2229
2230
2231
2232
2233
2231+
223!5
2236
2237
2238
2239
22'+0
221+1
22'+2
22'+3
PAGE
56
1~76
* MOVE
*
I"IPBSR1
*
*
*
*
*
'*
*
I'lPBSR2
*
*
AND PROCESS BYTE STRING
L
MAR.YO
AI
SRHL
BALL
YOI.MR6.2
MRO,YD,NULL
LSTOVF(NULL),DR2
Nl
MRO,MRO.LOHALF.1
SRLI
Ll
NI
BALNZ
AI
OCRA
WH
AI
MR1,YD.16
MR2.CRC
NULL,MR1.''+OO'
TRONLYlNULL)
YDI.MR6,3
NULL.MH2.MR1
NULL.YD
YOI.MR6.1
NULL,MR1.'800'
CKONLY(NULL)
NULL.MR1,'200·
CKTR(NULL)
TRCK(NULL)
NI
BALZ
Nt
BALZ
BAL
TH~ REGISTER SPECIFIED BY R1
CONTAINS THE START ADDRESS OF
BYTE STRING A. THE REGISTER
SPECIFIED BY R1+1 CONTAINS A
TRANSLATION TABLE ADDRESS.
THE REGISTER SPECIFIED BY R1+2
CONTAINS IN BITS 16:31, A
POSITIVE BYTE COUNT. COpy TO
"'RO. EXIT IF NEGATIVE (P.32)
ELSE, FETCH 1ST EVEN/ODD BYTE PAIR
BITS 0:15 OF THE REGISTER
SPECIFIED BY Rl+2 CONTAIN
CONTROL CODES TO IDENTIFY
THE ORDER IN WHICH TRANSLATION
AND ERROR CHECKING ARE TO BE
PERFORMEO.
TRANSLATE ONLY (P.59)
ELSE, POINT TO R1+3
OUTPUT CONTROL CODE TO CRC BOX
OUTPUT OLD RESIDUAL FROM R1+3
TEST CONTROL CODE
ERROR CHECK ONLY (P.60)
CHECK THEN TRANSLATE (P.58)
ELSE. TRANSLATE THEN CHECK (P.57)
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83222110
83222120
83222130
8322211+0
83222150
83222160
83222170
83222180
83222190
83222200
83222210
83222220
83222230
8322221+0
83222250
83222260
83222270
83222280
83222290
83222300
83222310
83222320
83222330
8322231+0
83222350
83222360
83222370
83222380
83222390
MODEL 8/32 WITH DPFP
PAGE
05 ... 058F02A13
COPYRIGHT INTEROATA INC.
57
APRIL 1976
22~5
* TRANSLATE THEN ERROR CHECK
22'+6
*
529
2B9F iSBB
22:t;
52A
528
52C
520
52E
52F
530
531
532
533
53'"
535
536
537
538
539
53A
538
53C
530
53E
53F
13FD
33D6
2A5F
'+A52
2A72
28<33
2BOF
17FO
2B9F
2ABF
17E5
'+BFF
2839
'+875
2AFF
3306
'+B3F
3318
3306
3339
2210
2B3F
"'ACO
1001
1080
ODCO
i900
lCBS
lBOO
'tC80
lCOO
1080
60'+B
lACO
3F80
CDC3
lC80
1003
If.F80
1001
1002
0001
2FE9
1800
22'+8
22'+9
2250
2251
2252
2253
225'+
2255
2256
2257
2258
225'
2260
2261
2262
2263
226'+
2265
2266
2267
2268
2269
540
28FF lF89
2270
.rlIo,,"VI
''''~f\'''
TRCK
....
"An_MD"'_fI\O~
n~f\'
no
J
'",oc.
~~
.. ,..u
r'-I"fl
t.Il:'vT
I .... ~I'\I
DVT~
U'II.:..
r>A'r'a
r", .. n
*+1(NULL)
ARM INTERRUPTS
yoI,MR6.1
POINT TO Rl+1
MR2,MoR
L
MR2,MR2.MoR
ISOL.ATE APPROPRIATE BYTE
LB
MR3.MR2.MR2
(MR3~=2X SOURCE BYTE
A
MAR,MR3,Yo.DR2
PLUS TRANSLATION TABLE AORS
A
YDI,MR6
FETCH TABLE ENTRY
L
BALD *+l(NULL)
DISARM INTERRUPTS
MAR,YS
(MAR)=DESTINATION ADDRESS
L
MR5,MOR
(MR5)=TABLE ENTRY
L
TO SUBROUTINE IF NOT MINUS (P.60)
BALNL SUBR(NULL),OR2
TRANSLATED BYTE TO CRC BOX
WDR
NULL.MR5
INCREMENT SOURCE ADDRESS
AINC YD,YD,NULL
MDR,t'lR5.MDR,DW2
INSERT , STORE BYTE
ST8
SAVE NEW SOURCE ADDRESS
MR7.YO
L
yoI.MR6,3
POINT TO Rl+3
AI
INPUT NEW CHECKWORD
YD.NULL
RH
INCREMENT DESTINATION ADDRESS
YS,YS.l
AI
YDI,MR6.2
POINT TO Rl+2
AI
YD.YD,l
DECREMENT COUNT FIEL.D
SI
SOECX MRO.MRO.NULL.,TRCKL,C DECREMENT & TEST COUNT
YD.MRO
SET AL.L OF Rl+2 TO ONES
l..
NUlL,NULL,ILIR,E,D EXIT' cc=oooo
L
BAL.A
Al
This information is proprietary and is supplied by INTEROATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any othef" purpose unless specifically authorized in writing.
83222'+10
83222'+20
83222430
83222'+'+0
83222'+50
83222'+60
83222'+70
83222'+80
83222'+'0
83222500
83222510
83222520
83222530
832225'+0
83222550
83222560
83222570
83222580
83222590
83222600
83222610
83222620
83222630
832226~O
83222650
8322266
...
MODEL 8/32 wITH OPFP
05-058F02A13
COPYRIGHT INTEROATA INC.
S'+l
5'+2
51.f.:3
5-'1+
51+5
5-'6
Sq.7
51+8
5-'9
Sq.A
5'+B
5-'C
~q.D
51.f.E
5q.F
550
551
552
553
55'+
555
556
557
558
2B9F
13FO
3306
2A5F
I+A52
2A72
2893
2BDF
17FO
2B9F
2ABF
17E5
'+8FF
2839
'+875
2AFF
3306
'+83F
2818
3306
3339
2210
2B3F
2BFF
188B
SUCD
1001
1080
ODCO
1900
1CSB
lBOO
5280
lcao
1080
60'+B
19'+0
3F80
CDC3
lC80
1003
q.F80
3F80
1002
0001
2FCl
1800
lFB9
PAGE
58
APRIL 1976
2272
2273
227'+
2275
2276
2271
2278
2279
2280
2281
2282
2283
2281.f.
2285
2286
2287
2288
2289
2290
2291
2292
2293
2291.f.
2295
2296
2297
* ERROR
*CKTRl
CKTR
CHECK THEN TRANSLATE
L
BALA
AI
L
LB
A
A
L
BALD
L
L
BALNL
WOR
AINC
STS
L
AI
RH
AINC
AI
SI
SOECX
L
L
MAR.MR7.0R2
FETCH NEXT BYTE PAIR
*+l(NULL)
ARM INTERRUPTS
YOI,MR6.1
POINT TO Rl+l
MR2.MDR
MR2,MR2.P'lDR
ISOLATE APPROPRIATE BYTE
MR3,MR2.MR2
MR3=2X SOURCE BYTE
MAR,MR3,YD.DR2
PLUS TRANSLATION TABLE ADDRESS
YDI,MR6
FETCH TABLE ENTRY
*+1(NULL)
DISARM INTERRUPTS
MAR,YS
(MAR)=DESTINATION ADDRESS
MR5,MDR
(MR5)=TABLE ENTRY
SUBR(NULL),DR2
TO SUBROUTINE IF NOT MINUS (P.60)
UNTRANSLATEO BYTE TO CRC BOX
NULL.MR2
YO.YO,NULL
INCREMENT SOUCE ADDRESS
MOR,MR5.MDR,DW2
STORE TRANSLATED BYTE
MR7.VO
SAVE NEW SOURCE ADDRESS
YDI,MR6.3
POINT TO Rl+3
YD,NULL
INPUT NEW CHECKWORD
YS,YS,NULL
INCREMENT DESTINATION ADDRESS
YDI,MR6,2
POINT TO Rl+2
YO,YO.l
DECREMENT COUNT FIELD
MRO,MRO,NULL,CKTRL,C DECREMENT & TEST COUNT
YO,MRO
SET ALL OF Rl+2 TO ONES
NULL,NULL.ILIR.E.O EXITa Cc=oooo
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83222680
83222690
83222700
83222710
83222720
83222730
832227'+0
83222750
83222760
83222770
83222780
83222790
83222800
83222810
83222820
83222830
8322281.f.0
83222850
83222860
83222870
83222880
83222890
83222900
83222910
83222920
83222930
MODEL 8/32 WITH OPFP
COPYRIGHT INTEROATA INC,
559
55A
55A
55e
550
S5E
55F
S60
561
562
563
561+
565
566
567
568
569
56A
56B
56C
560
2B9F lB88
13FO 56CO
3306 1001
2A5F 1080
I+A52 oOCO
2A12 1900
2893 lC88
280F 1BOO
17FD ~880
2B9F lCOO
2ABF 1080
l1E5 60&f.B
2839 3F80
2AFF lC80
'+875 CDC3
2818 3F80
3306 1002
3339 0001
2210 2F09
2B3F 1800
2BFF lFB9
PAGE
OS ... 058F02A13
59
APRIL 1976
2299
2300
2301
2302
2303
230ft.
2305
2306
2307
2308
2309
2310
2311
2312
2313
2311+
2315
2316
2311
2318
2319
2320
2321
*
TRANSLATE ONLY
*TRONLYL
TRONLY
L
BALA
Al
L
LB
A
A
L
BALD
L.
L
BALNL
AINC
L
STa
AINC
AI
SI
SoECX
L
L
MAR,MR1.0R2
FETCH NEXT BYTE PAIR
*+l(NULL)
ARM INTERRUPTS
yoI.MR6.1
POINT TO R1+1
MR2,MOR
MR2,MR2.JIIIDR
ISOLATE APPROPRIATE BYTE
MR3.MR2,JIIIR2
2X SOURCE BYTE
MAR.MR3,YO,OR2
PLUS TRANSLATION TABLE ADDRESS
YoI,MR6
FETCH TABLE ENTRY
*+l(NULL)
DISARM INTERRUPTS
MAR,YS
(JIIIAR)=DESTINATION ADDRESS
MRS,MOR
(MRS)=TABLE ENTRY
TO SUBROUTINE IF NOT MINUS (P,60)
SUBR(NULL).OR2
YD,YO,NULL
INCREMENT SOURCE ADDRESS
MR7,Yo
SAVE NEW START ADDRESS
MDR.MR5.MDR,DW2
STORE TRANSLATED BYTE
YS,YS,NULL.
INCREMENT DESTINATION ADDRESS
YDI,MR6.2
POINT TO Rl+2
YO.YD,l
DECREMENT COUNT FIELD
MRO.MRO,NULL.TRONLYL,C DEC REMENT & TEST COUNT
YD,MRO
SET Rl+2 TO ALL ONES
NULL,NULL,ILIR,E.o EXITI CC=OOOO
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining fNTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
83222950
83222960
ft~ft.l'\l'\a . . "
g;;;'CC.C7(U
83222980
83222990
83223000
83223010
83223020
83223030
832230'+0
83223050
83223060
83223070
83223080
83223090
83223100
83223110
83223120
83223130
832231 .. 0
83223150
83223160
83223170
MODEL 8/32 WITh DPFP
COPYRIGHT INTEROATA INC.
56E
56F
570
571
572
573
57'+
575
576
577
578
5713
57A
576
57C
570
57E
57F
580
581
582
583
581+
585
2B9F
13FD
2A5F
I+A52
269F
'+6FF
17FO
2BDF
3339
2AFF
3306
'+B72
'+B3F
2B18
330&
3339
2210
2B3F
2BFF
3306
2B3F
2855
2BFF
1686
5COO
1080
DOCO
lC06
191+0
50'+0
lBOO
1001
lC80
1003
CDC3
'+F80
3F80
1002
0001
2FEE
1800
lFB9
1001+
1000
lA80
1F9C
PAGE
05-058F02A13
60
APRIL 11376
2323
2321+
2325
2326
2327
2328
2329
2330
2331
2332
2333
233'+
2335
2336
2337
2338
2339
231+0
23'+1
23'+2
231+3
* ERROR CHECK ONLY
*
MAR,MR7.0R2
CKONLYL L
FETCH NEXT BYTE PAIR
CKONLY
BALA *+l(NULL)
ARM INTERRUPTS
MR2.MOR
L
MR2.MR2,P'lOR
ISOLATE APPROPRIATE BYTE
LB
MAR,YS.DR2
(MAR)=DESTINATION ADDRESS
L
WDR
NULL.MR2
SEND SOURCE BYTE TO CRC BOX
QISARM INTERRUPTS
BALD *+1(NULL)
YDI,MR6
L
POINT TO Rl
YO,YO,l
Al
INCREMENT SOURCE ADDRESS
MR7.YD
L
YDI.MR6,3
AI
POINT TO Rl+3
MDR,MR2.MDR.DW2
STB
INSERT & STORE BYTE
YD,NULL
RH
INPUT NEW CHECKWORD
AINC YS.YS,NULL
INCREMENT DESTINATION ADDRESS
YDI,MR6.2
Al
POINT TO Rl+2
YD,YO.1
DECREMENT COUNT FIELD
SI
SDECX MRO,MRO.NULL,CKONLYL,C DECREMENT & TEST COUNT
YD,MRO
SET Rl+2 TO ALL ONES
L
NULL,NULL,ILIR,E,D EXITI CC=OOOO
L
83223190
83223200
83223210
83223220
83223230
8322321+0
83223250
83223260
83223270
83223280
83223290
83223300
83223310
83223320
83223330
832233'+0
83223350
83223360
83223370
83223380
83223390
23'+5
23'+6
231+7
23'+8
23'+9
2350
2351
* EXIT TO SUBROUTINE
832231+10
832231+20
83223 .. 30
83223'+1+0
832231+50
83223 .. 60
83223'+70
*
SUBR
AI
L
A
L
END
YDI.MR6,1+
YO.LOC
LOC.MR5.MR5
NULl.NULL.IR.D
POINT TO Rl+1+
SAVE UNINCREMENTEO LOC
LOAD SUBROUTINE ADDRESS
This information is proprietary and is supplied by INTERDATA for the sole
purp:lse of using and maintaining INTER DATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
MODEL 8/32 WITH DPFP
PAGE
OS .. 058F02!U3
COPYRIGHT INTEROATA tNC,
61
APRIL 1976
NO ERRORS
A
ABl
A8l1
ABl2
ABl3
AD
ADl
AOOlT
ADR
ADRMW
AORS
AE
AEl
AER
AFAUlT
AM
AHI
AHM
AHA1
AI
AIS
Al
All
Al2
AM
AR
ATBl
ATBll
ATBL.2
ATL
ATll
AT1..2
AUTOl
AUT02
AUTOIO
B12.23
SAL
BALl
BAL2
BAl3
BAL.R
BAL.R1
BBIT
BBS
BBSl
Bel
BC2
Be3
BOCS
BFBS
BFC
BFCR
OOB'+
OOCA
031C
0321
032'+
OOF'+
OllC
0316
o o7 if.
025A
0268
000'+
0062
005'+
02C7
0094
019'+
00C2
001E
01F'+
OO'+C
OlAA
0156
015F
OOA2
001'+
0300
0303
030"
00C8
0310
031'+
0'+A8
Q'+AB
02AF
0009
0082
0085
0087
009F
0002
0005
0008
00'+1
00'+3
0035
0037
0036
OlCA
00'+'+
0086
0006
'+25
1'+29
511
1'+36
1070
1085
q.·U
1280
....
'+13
808
6SS
701
.. 21
1380
1382
'+2'+
.. 22
1'+05
2039
20'+6
1227
1634
312
315
318
73
1650
167
168
31'+
76
7'+4
1678
173
1921
1'7'
317
7'
7'+7
This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
MODEL 8/32 WITH DPFP
OS ... 058F02A13
COPYRIGHT INTERDATA· INC,
BFFS
8FS
6FSl
611720
BI1820
BITO
BIT15
BIT16
81T160
BIT17
8IT18
6IT19
BIT20
8lT21
BIT22
61T23
BIT2'+
BIT25
61T2&
BIT27
8IT28
BIT29
6IT30
81T31
8RR
SRW2
BRW3
6RW'+
RTABlE
BTBS
BTC
BTCR
BTFS
BXH
BXlE
RXlH
8XlHl
BXLH2
6XlH3
BXlH4
eYTEIO
C
COFOl
Cl
C2
CAOOl
CADRS
CADRSl
CADRS2
CADRS3
CASMD1
CASI'-lD2
CBIT
CBT
00'+6
00,+5
00'1-1
0021
0131
0133
OOOF
0327
0023
0326
0329
032A
0328
032C
0320
032E
032F
0330
0331
0332
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0335
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01'+F
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00B2
0121
0013
003C
0123
006C
006E
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0116
0117
0010
OOEE
PAGE
62
APRIL 1976
170
17'+
1208
12'10&
2089
136
133
1076
1621
'1289
103'+
116
2110
1'+72
13'+
1003
1511
38'+
171
917
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522
792
1518
1520
1521
1526
801
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8'+9
855
1529
1792
75
610
677
703
1335
18
680
7'103
895
653
865
868
746
187~
1693
336
91
1107
'+18
278
180
56'+
566
1967
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing .
..",..
1536
1910
MODEL 8/32 WITH DPFP
COPYRIGHT INTEROATA INC.
CBTl
C8T2
CCS
CCS1
CCW
OOEF
OOOE
CO
COl
COADSOMO
COR
CE
CEl
CER
CFFFE
CH
CHANEL
CHI
CHVR
CHVRl
Cl
CKONLY
CKONLYL
CKTR
CKTRl
Cl..
Cll
CLB
CLBl
CLH
CL,Hl
CLI
CLR
CLRWT
CMNBRW
CMSTML
COMBIT
COMBTl
COMBT2
COMINO
OOF2
02F8
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0072
0002
OllA
0052
0039
0092
01+32
0192
00214002C
01F2
056F
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OOAS
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0172
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0114-8
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020B
COMli\ll
0200
COMIN2
COMINT
COMLM
COJlilLJIiIL
COMMON
COMSTM
CONSER
CONSTANT
COUNT
CR
CRC
CRC12
CRC12A
CRC128
PAGE
05 .. 058F02A13
63
APRIL 1976
~99
~96
502
864+
1649
191+6
1650
1955
1662
1967
1675
1979
1678
2173
510
513
516
519
1255
1316
1888
1137
1209
1+95
1+98
0100
0""96
0012
020F
020A
0101
0100
014-~7
OlOF
02~3
0011
0011+
0012
0006
OOBC
03CO
030F
18~5
1814-6
1850
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1875
1896
1921
191+1
508,
501
q.38
1101+
1258
137
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2314-1
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2295
161
805
1078
652
561
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132141293
1755
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514-8
532
1902
536
953
213
1655
2172
399
1697
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501
552
514-0
1136
2061
30~
1661
1862
1861+
2188
22014-
2232
1879
1879
1881
1902
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in Writing.
1902
1928
1930
1976
"l
MODEL 8/32 WITH DPFP
COPYRIGHT INTEROATA INC.
OAT
OOBE
030&10307
OOBA
009C
0013
DO
DOl
DDR
DE
DElAY
OER
OEV
OOFA
0167
007A
OODA
0&1-01
005A
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DFALTO
OFALTl
DFLOAT
DFU
02C2
02C5
0288
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DH
DH1
DH2
DH3
DHR
OHRl
OIGITl
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EXAUTO
EXBR
EXBRl
EXHR
EXlSTM
EXSU81
EXSUB2
ExTLAT
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0067
0155
OLt-1O
OLt-ll
012A
0127
0'+55
0128
0160
0068
0112
OCf.Cf.A
OLt-Cf.F
0387
0385
PAGE
05 .. 058F02A13
6&1-
APRIL 197&
&1-02
1702
1973
396
12&1-0
1685
1'5'+
12'+1
1685
1960
125'+
1701
2178
1255
1708
1257
1829
1563
1850
1563
1851
1567
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1570
19,+5
165q.
1950
1657
1951
1669
1953
1669
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1210
1230
1233
1236
1239
1239
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1252
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572
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272
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290
293
296
299
365
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581
520
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3'+a
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177
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113
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199
676.
1793
193
638
202
698
205
707
2Cf.8
208
603
1863
1882
1929
1977
2068
189Cf.
1981
600
530
18'+7
1852
1555
1566
This information is proprietary and is supplied by INTE;:ROATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
MODEL 8/32 WITH OPFP
COPYRIGHT INTEROATA INC.
FBIT
FFALTl
FFAULT
FLDR
FLOR1
FLOR2
FLR
FLR1
FLR2
FN
FtllO
FNOl
FN0123
FNOIS
FROWT
FWRIT
FXOR
FXOR1
FXDR2
FXR
FXR1
FXR2
FXR3
1675
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O'l-CB
0'+00
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H\oJASSlST
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IDLE1
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HIHALF
65
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0001
02C6
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028E
02A5
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0389
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0'1-'+6
05uO
0'+50
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0277
0209
02A9
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02AC
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PAGE
05-058F02A13
185'+
'\c:a
305
2088
21'+
2109
11'+3
1196
118«3
1170
1067
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1897
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0280
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599
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1516
1230
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1227
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1230
1232
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1527
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15'+0
2212
1233
1235
1236
12",5
12"'5
20'+'+
2025
859
802
505
1796
q.35
1211
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
12'+6
1297
1299
MODEL 8/32 WITH DPFP
COPYRIGHT INTEROATA INC.
LHl
LHL
LHLl
Ll
LIS
LLOOP
LM
LMl
LMD
LM01
LME
LMEl
LOADLSU
LOCDIS
LOHAL.F
0190
00E6
02F6
OlFO
t.,PSW
LPSWl
LPSWR
LR
LRA
LRA1
LRA2
LRC
LSTOVF
018Cf.
03EE
0030
0010
00C6
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03A6
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0300
00B6
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0018
0008
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0058
0098
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0358
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0'+63
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MDR
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MPBSR1
MPBSR2
MR
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NFAST
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NH
NHI
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NR
0
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PAGE
05~058F02A13
66
APRIL 1976
1f-90
OOIf.!
OCf.oF
01A2
0109
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QCf.BA
00['+
010C
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1180
1790
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526
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1766
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1010
1709
1175
1019
1772
1193
1360
2228
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1820
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1'+80
11+91
750
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1630
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1388
1'+73
1656
2225
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511
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31+5
105
1909
95'+
1822
2'+'+.
1855
1922
19'+2
This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorizeci in writing.
1503
1505
1625
1695
MODEL 8/32 WITH DPFP
COPYRIGHT INTEROATA INC,
oeR
OH
OHI
f'lT
.......
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OR
OUTDIS
OVFl
PB
PB1
PBR
paRl
POWRUP
PPFINT
PPFSTD
PPFSTE
PSIalDIS
PWROWN
QutINT
Ro
Rl
R13
Rll+
R15
R2
R3
Rq.
R8
RBl
RB2
RBL
RBLl
RBR
RBT
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Rues
RoeSl
ROFULL
RDHALF
ROR
READIT
REDCHt<
RE"OV
REMOVl
RESTRE
RETURN
RFULLl
RFULL2
RH
RHALFl
RHALF2
RHR
RLL
RRL
PAGE
05~058F02A13
67
APRIL 1976
013e
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021+2
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02F3
02F ...
01B2
02EO
02EE
0132
0106
010'+
25'J
955
1131
1203
1035
121+9
1250
1309
979
980
1251
1252
1561
1905
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175'J
1310
1311
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1570
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1851
1859
1886
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1926
1965
1980
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525
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810
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359
398
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1951
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1'+98
1805
1697
1353
1355
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This information is proprietary and is supplied by INTERDATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
825
831
831+
MOOEL 8/32 WITH OPFP
COPYRIGHT INTEROATA INC.
RTBL.
RTBL.1
RTBL2
RTL
RTLl
RTL.2
RTNCRC
RWBIT
RWBRR
RW6RX
RWSCl
RWSC2
S
SBT
SCP
SCPl
SCP2
SO
SOl
SUR
Sf:
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SER
SETG
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SH
SHl
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SINT
SINTl
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SLL
SLLS
SR
SRA
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SRHL
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PAGE
OS.058F02A13
68
APRIL. 1976
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This information is proprietary and is supplied by INTER DATA for the sole
purpose of using and maintaining INTERDATA supplied equipment and shall
not be used for any other purpose unless specifically authorized in writing.
MODEL 8/32 WITH DPFP
COPYRIGHT INTEROATA INC.
STO
ST01
STE
STH
STM
STM1
STMO
STM01
STME
STMEl
STORE
STORE1
STORE2
STRDLP
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T8T
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OOEO
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THI
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TLATEl
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05.058F02A13
69
APRIL 1976
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1652
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1920
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1956
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OS .. OS8F02A13
COPYRIGHT INTERDATA INC.
70
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