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I

CONTROL DATI'fi} 9461
DISK STORAGE DRIVE
A12 AND ABOVE
B12 AND ABOVE

I

DIAGRAMS &
CIRCUITDESCRI PTION'
CARD PLACEMENT
WIRE LISTS

I~ONrHOI

IlArA

, CUSTOMER ENGINEERING' MANUAL

CONTROL DATA@ 9461
DISK STORAGE DRIVE
A12 AND ABOVE
B12 AND ABOVE

DIAGRAMS &
CIRCUIT DESCRIPTION
CARD PLACEMENT
WIRE LISTS

CONTROL DATA
CORPORATION

CUSTOMER ENGINEERING MANUAL

RECORD of REVISIONS
REVISION

NOTES

·A •
(2-14-69)

Manual released. This manual incorporates all change orders released prior to
2-14-69.

B
(6-2-69)

Engineering Change Order PM5534 incorporating the following:
ECO PM4243C affecting pages 1-1, 1-5, 1-7.
ECO PM4539B affecting pages 3-37, 3-40, 3-41, 3-42, 3-43.
ECO PM4645 affecting pages 1,:-13.
E:CO PM4677 affecting pages_ 3-26, 3-27.
ECO PM4772 affecting pages 3-47.
ECO PM4787 affecting pages 3.:-37, 3-40.
ECO PM4823 affecting pages 3-37, 3-38, 3-39, 3-40, 3-41, 3-42, 3-43, 3-44, 3-45.
ECO PM4843A affecting pages 1-1, 1-5.
ECO PM4914 affecting pages 3-24, 3-25.
ECO PM4949 affecting pages 1-9.
ECO PM4950 affecting pages 3-24, 3-25.
ECO PM5020 affecting pages 1-13, 3-37, 3-40, 3-41, 3-42.
ECO PM5033 affecting pages 1-13.
ECO PMS037 affecting pages 3-44, 3-45.
ECO PMS038 affecting pages 3-37, 3-40, 3-41.
ECO PM5279 affecting pages 1-5.
-

C
(7-31-69)

Engineering Change Order PE12154 incorporating the fo11owin~:
ECO PM4840B affecting pages 1-15.
~CO PM5186 affecting pages 1-3, 1-5, 1-11, 3-2, 3-9.
ECO PE12095 affecting pages 1-14, 1-15.

D

Engineering Change Order PE12524 incorporating the following:
FCO PM5354A/ECO PMS354B affecting pages 1-13, 3-28, 3-29.
FCO PE1210lA/ECO PE12101 affecting pages 1-1,1-9, 3-13.
FCO PE12005 affecting pages 1-9, 1-11, 3-13, 3-14.
FCO PE12126 affecting page 1-11.
FCO PE1213l affecting pages 1-13, 1-15.
EGO PE12054A affecting pages 3-44," 3-47.
ECO PE12074A affecting pages 1-9, 1-11, 3-13, 3-14.
ECO PE12078A affecting pa~es 1-13, 1-15, 3-37 thru 3-43.
EGO PE12211 affectin~ Ea~e I-S.
ECO PE12231 affecting page 3-32.
ECO PE12245 affecting~s' 1-9, 3-15.
ECO PE12328 affecting pages 1-1, 1-1~!3-1.

(1-13-70)

Pub No. 41248400
1969, 1970
by Control Data Corporation
Printed in United States of America
@)

\

Address comments concerning this
manual to:
Control Data Corporation
Technical Publications Department
4201 North Lexington Avenue
St. Paul, Minnesota 55i12
or use Comment Sheet in the back of
this manual.

RECORD of REVISIONS (CONT'D)

41248400
REVISION

F===l
E
(3-4-70)

NOTES
ECO PE12343 affecting pages 1-3, 1-5, 3-0,3-12.
ECO PE12370 affecting pages 3-20, 3-22.
ECO PE12461 affecting page 1-11.
Editorial Changes affecting pages. 1-26, 1-29, Forward.

Engineering Change Order PE12573 incorporating the following:
FCO PE12075, FCO PE12l69/ECO PE12074 affecting page 1-26.
ECO PE12515 affecting page's 3-37, 3-38, 3-39", 3-40, 3-41, 3-42, 3-43.
ECO PE12636 affecting page 1-13.

I

,

PREFACE
Customer Engineering material for the CONTROL DATA ~ 9461 (Mods
12 and above) Disk Storage Drive is contained in four separate
manuals, and provides all information required for installation,
operation, and maintenance.

PublLcation No.

41246800

General Description,
Operation, Installation
and Checkout, Maintenance

Publication No.

41248400

Theory of Operation,
Diagrams, Wire Lists

Publication No.

41245200

Illustrated Parts List

Publication No.

40826700

Disk Storage Drive (OEM)
1604 Logic Modules Manual

CONTENTS
Part 1. Diagrams &
Circuit Description

Part 3. Wire Lists

Description of Wire Lists
l-ii
1-1 Logic Wiring
1-3 R/W Logic
Control Panel
1-5
1-7 Actuator, Harness
1-9 Actuator, Misc.
1-11 Duo-Tyne Connector
Filter Box
1-13
1-17 Final Assembly I
1-18 Voltage Adj. (+20 VDC)
1-29 Voltage Adj. (-20 VDC)
Front Panel
D. C. Power Panel, Harness
Part 2. Card Placement
D. C. Power Panel, Misc.
Card Placement information is found
A. C. Power Supply, Harness
on page 1-11.
D. C. Power Supply, Harness
W3 Cable

Key to Logic
I/O Logic
Position Logic
Acces's Control
Motor Drive Logic
Read/Write
Card Pla'cement
Power Supply
Carriage Wiring
Flow Charts & Timing Diagrams
±12V. VOltage Regulator

3-ii
3-0
3-20
3-23
3-24
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-35
3-36
3-37
3-44

PART 1

DIAGRKMS & CIRCUIT DESCRIPTION

--:>'

Control delays may ha\'e multiple inputs and/or' IllLlltipl<: outputs,
('ontrol delay has multiple output terms 0,

t!.

J

When a
ot' N t(~I'lll),

lnore than on(! V. Y,

in the same mannel' as capacitive delays (~x('ept for th{! vl!r'tiral lines) unless
they arc used as delay lines.

circuit letters are present, pin numbers ai'" shown adjacent to the input and

each output term may have a separate conditioning input.

output art'ows.

STANDARD

A capacitive delay is used to delay the" 1" input to a logic dement.
are not affected by the delay,)

Capacitive ddays may be active Of' passive,

circuit.

2B29

points for the scope and probes var'y fOf' different ranis and should be detel'-

-{II

DELAY

Pin nUlllbers arc also shown when external wit'ing is

needed to connert the proper raparitance,

TWISTED- PAIR

CONNECTOR / "
NUMBER

Figure 12.

In the third

SECOND PIN
........... (NEGATIVE-

LINE)

FIRST
PI N
NUMBER
(POSITIVE -BIASED
LINE)

Inductive Delays

Figure
Voltage levels used to repn.!sent "1

3C16A- 5: 10, II

2C28A

~

2C27C

~

0.2 ,,"SEC

EJ

those used for' internal logic.

401

0,7 ,,"SEC

FIXED

l~.

Cable Connections

PLUGGABLE

2C16- 9,10
2012-7

Active Capacitive Delays

These cards may be considered as
The letter's commonly

capacitors, located on one or nlore capacitor cards, as an AND input to the
For this reason, all passive delays show pin numbers

SPECIAL LOGIC SYl\1ROLS

assoriated with these cards are L & M (1604) and ]{

/<.,

T (3000 Series).

Nonstandard elements (special logic and/or non-logic elements) are r'epresented by a special circuit symbol (generally a rectangle as shown in Figure

A

16).

The special circuit symbol always shows the symbol designation, jack

:lOOO Series Receiver may also be used to perform a logical inversion by

location, and the card type.

swapping the twisted pair wires.

This usage is indicated by a circle on the

such as in the case of special delay cards whirh indicate the delay period.

In Figure 13, "1 's" and "D's" have been added to

For detailed information refer to the specific car'd type in the appropriate

clarify the logic states; they are not pal·t of the symhol.

All passive capacitive ddays (Figure 10) are formed by wiring grounded
affected logic element.

and ,·O's!! on ('ables ar'c different frorn

inverting the signal electdcally, but not logically,

input side of the symbol.
Figure D.

IS"

The level shift to and from internal logir is

made by line dl'ivel's and line receivers.

4 MS

WITH EXTERNAL
CAPACITOR lSI

"I"

"I"

""

~~
"0"
"0"

to provide this ext cr'nal wiring data.

Figure 13.

Printed Circuit or Logic Module l\lanual.
"I"

"I"

"0"

~~

~>-+

Supplemental information may also be shown

SUPPLEMENTARY
INFORMATION

SYMBOL
DESIGNATOR

Typical Line Driver/ Receiver Symbols
CHASSIS
LOCATION

",.

..I.

~

Line Driver's / Receivers

cards.

",.

LINE

OUTPUTS

example, this wiring connects to capacitors located on two sepal'ate capacitol'

-'

TRANSMISSION

1 '- ~
BIA~~MDBER

3HI-A9, AIO

tN

In Figure q, the pluggable rielay

uses this wiring to connect to capacitors on the same card.

RETURN)

~~

~

t2
TIM ED

GROUND

M

OF

f~

tl

(COMMON

DELAY

I
to

Active delays may be recognized by the circ'uit lettel' always present as pal'!

INDUCTIVE

LINE

mined by referring to the Printed Cin,uit :'ITanual.

of the card location.

(SHOWING PIN "M"
CONNECTOR
2J12)

0,15 fLSEC
TAPPED

WIRE

2JI2

~

0.1 fLSEC

Delav periods are checked by using a dual-trace scope connerted to
The actual connectioll

SINGLE

DELAYS

~

depending upon whether or not transistor's ar'e used as part of the ddaying
the input and output of the delay produring elerne,,!.

INDUCTIVE

2H34D

("0" inputs

Cable connect ions are r'epr'esented by the MIL-STD-15 symbol and identified
as to connector' location and pins used, as shown in Figure 15.

Figul'e 12 shows both kinds of incluctive delays.

Capacitive Delays

CABLE IDEl'TlFICATION

On multi-section c[!I'cls where no identifying

3C2B-6,7

NON - LOGIC CONVENTION

~

~OBSOLETED
,1 ~ ~EPRESENTATION)

B fLSEC

13c2B-6,7

Figure 16.

signal voltage level from that used in internal logic,

The double bar appears

INPUT/OUTPUT DESIGNATIONS

on the input or output side of the symbol, depending on which side connects to
the non-logie-level signal.

Figure 10.

Symbol for Special Circuits

The use of the double vertical bar, as shown in Figul'e 13, denotes a shift in

Passive Capacitive Delays

No particular voltage level is implied by the

Where several pages of logic are involved, a symhol index and term list
(side cars) are incorporated within the manuaL

double bar - only that it is non-logic.

Also in certain instances

such as special card types or on equipments for which no equation SUlllmar.\

Capacitive delays may be adjustable or nonadjustable, depending on the card
t)pe and/or the external wiring connections on the cani.

sary to adjust the delay period in order to obtain specified circuit operation
(usually done by \'arying a potentiometer in the RC network), a diagonal arrow
is added to the delay symbol as shown in Figure 11.
2C2IA-5:11,12

3C2B- 12: 13

~.­
~

exists (as for peripheral devices) input and output pin num bel'S are indicated

JACK ASSIGNMENTS

When it is neces-

FOR
GAP

Each numbered term in the logic diagrams contains a Jack assignment show-

(circuit section) associaterl with it.

For some card types, the test point

letter is replaced by a pin number.

For these cases, a card extender must

no test point.

Adjustable Capacitive Delays

*CHASSIS NUMBER

~

II I

OUTPUT

TEST POINT

8

An inductive delay is used to delay either the" 1" or "0" input to a logic
element or as a tapped delay line for timing of operations.

The symbol fOI'

this delay is an elongated oval with a double vertic-al line just within the input
When used as a tapped delay line, the inductive delay is

terminated in its characteristic impedance.

Inductive delays are identified

K511

FUNCTION

.........

K401

(FORWARD) II04

!

INPUT SYMBOL DESIGNATOR

Figure 17.
HORIZONTAL (COLUMN)

2 D 12 A

Inductive Delays

end of the oval.

Figure 14 illustrates the

(BUSY) I203

OUTPUT PINS

\

OUTPUT SYMBOL

inverter J001, with 2D12A representing its jack assignment.
ORDINATE (ROW)

Figure 11.

Also, some symbols show

This is because the entire card is used for one purpose

(e. g. a single inverter, FF, or control delay).
3/4"

INPUT PINS

ing the physical location of that hardware element and the test point

be used in order to test that section of the card.

~
ADJ UST
RECORD

on each logic element as are the output destinations of the elements (Figure 17).

:'When most or all jack aSSignments are located on one chassis,
the chassis numbers for that chassis are omitted. All multichassis devices include a chassis number as part of each jack
assignment.
Figure 14.

Jack Assignment Scheme

Input /Output Designations

DESIGNATOR

::tJ

c::

~

8.

Set Cylinder

UNIT SELECT

1:'

The -Q set cylinder pulse applied to R009. indicates that
The controller can select anyone of eight disk storage
Jrives by applying a select module signal to receiver R012.
If the disk storage drive is on-line. the following lines are
returned to tne controller:

1.

Selected Module via T007.

This line is used by

the controller to check if the disk storage drive
is selected.
2.

the address and control bus contains head positioning information. This information is used to reset the disk storage
drive cylinder address register to the new cylinder address.
Set Head and Direction

Bit 7 - Head Advance, -Q level. Increments the head
address register so that the next head in order can
be selected.

This function can be used to select heads

sequentially on a cylinder for multiple track reading or
writing.

INDEX/SECTOR

The controller applies a -Q pulse to ROIO when the address
and control bus contains head select information and the
cylinder access direction. The head select information

Each cylinder is divided into 20 sectors. The controller
knows which sector is under the heads by means of a sector

loaded. this line indicates that the selected disk

(bits 4 thru 7) is gated into the head address register to

disk which rotates with the disks.

storage drive is available.

select which head shall read or write. Bit 0 of the bus is

notches in its outer rim.

applied to the Reverse FF (K214/215) to establish the direction

cover and uncover photocells to generate sector pulses.

Selected On Line. via T006.

When the heads are

The sector disk has 21

As the disk rotates, the notches

of the next seek.
ADDRESS AND CONTROL BUS

The starting, or reference, point is the index pulse.
Control Select

This pulse is generated by two notches close together on the

The address and control bus consists of eight input!
The -Q level control select signal is applied to ROll.
output lines which carry information between the controller When this signal is uP. the address and control bus contains
and the disk storage drive. The function of the signals
control information.
t--' carried on these lines is defined by one of the accompanying as follows:

•

C

select lines.

Bit assignments and their functions are

sector disk.

When light passes through both notches simul-

taneously, the output of 1028 goes to "1".

If the unit is se-

lect~d and on line. T004 returns a selected index. -Q ~lse.

1.

Bit 0 - Write Gate. -Q level. Commands a write
operation by enabling the write driver.

END OF CYLINDER

SELECT LINES

2.

Bit I - Read Gate, - Q level. Commands a read
function by enabling the read lines.

If the heads are selected sequentially on a cylinder, the
head address register is incremented by the Head Advance

Set Difference

3.

Bit 2 - Start Seek. -Q level.

the desired cylinder address, the controller applies a-Q
set difference pulse to ROOS.

Inititates carriage positioning Command. While heads 0 thru 9 are selected, none of the

according to that previously specified by the Set Head

After the controller has computed the difference between the disk storage drive current cylinder address and

and Direction tag.
4.

This indicates to the selected

Bit 3 - Reset Head, -Q level.

Reset head address to

:-·ero.

disk storage drive that the address and control bus contains
head positioning information.

Tbis information, indicating

5.

tracks-to-go to the desired cylinder, is then loaded into the
6.

de crement counter.

AND gates into 1026 are made.. When the next head advance
command is applied to R007 to advance the head address
register from 9 to 10, the gate into 1026 is completed.

Bit 4 - Erase Gate, -Q level. Commands an erase
function 1Jy enabling the erase driver.
Bit 5 - Head Set, -Q level. Enables the head indicated
by the head address register.

Bit 6 - Return to Zero Seek (RTZS), -Q level. Move
heads in reverse to the home position, th'!'n forward
to cylinder ze~o.
These signals are within ~,.~ followll1g "v~tage ranges:
7.

All input/output signals are Q or L levels or pulses.

iQ'" +3.5 to +0.65 vdc. -Q

= -0.5 to

-3.5 vdc. +L

= +6.28

to +2~0 vdc, and -L

= +0.3

T005

r'eturns a -Q level End of Cylinder signal to the controller to
inform it that the last head of a cylinder has been used.

to O.Ovdc.

.-;:,.

ITAG LINES

~

~1

~

.ar.·

,

KIIS

"'

~.~•.: .• ';""";~':';"'..:.,:,'~: '.~

.·;r~UIPY~~!l)
."

~~6t=1

TOM

IJA-_~

lIOn.

!;c!

ro



to the address and control bus.

(l)

The decrement counter is set by the Set Difference input
This select sets the counter

to the number of cylinders to go during a seek. Direction
of seek is controlled by the Set Head and Direction line.
As the heads move toward the new cylinder, the trailing
edge of each track pulse provides an enabling term to pulse
generator K160/161 and K162/163. This pulse generator
provides the two phase pulses necessary to decrement the
counter. As the counter counts down towards zero, inverter
1171, 1173, 11 74, 1177. and 11 78 decode the output of the counter
to indicate the number of tracks to go.

These lines. wi 11 be

used to control the speed of the carriage motor and, ultimately,
to stop the heads on the desired track.

too'
r
~

CYLINDER ADDRESS REGISTER
The cylinder address register is set by the Set Cylinder
input to the address and control bus. The number stored in
the register indicates which cylinder the heads are currently
positioned on.

.

.-",

r~~'~":'~~-'

.~~~T"'-~".... --~~_
- '","-7"'''''''''''-'--''--r-~---''''C--'''''--'-'-''~--'' 'r~,:,",~~_.~.~,
- - -~,' ..,.-~., ~+~-~-;-"" ,~.-.~.~.-.-

. .,. ,. . .-"".

~:.~,,.; ~-

DECREMENT
COUNTER

CYLINDER
ADDRESS
REGISTER

1\

ROOO
IE33-10)

r--"----..

JIOOIIOI
128

?'~?J:'"

o

o

f~~:)~
12

c

io~ROOZ
(E32-IZl
-

I

~

3

~

I

W

!F,RST

SEf~)3Ii_069) ~

c

~2
AI6
KII3
KII2

•11 .. 1123

I

KitS

KJl4

_I

K210

-+

+IMTR OFF) "'203
IA2S-7)

1162

2

1106

10
KI20
KI21
KI22
K 123
KI24

KI60

1015-2)
KI63

o

R
I"-

K 125

1015-11 )

KI26
KI27

1209
IC30-41

B

tl07

1100
1016-51

IA3i;;; -0

. _I

m

1120

10
10
"OJ"

I A14)

KIZe
KI29
KI30

K 131

IC30-3)
1100

K 132
K 133
KI34
KI35

,1016-4)

110
_ I I
17 I
II~

B

~ CYL SELECT)I~~251 ~~
007C

B09A
KI60

TaO
1217

K216

T-O

X08- 3
1101

--7)

KI40
K 142

J104-82

KI44

(SET CYLI R009
CE34-121
(SELIIOI8

iT7 0lIII1

lBO' -31

1~IY244

K 146
KI48
K 150
KI52
KI54

1013-91

1t.34-1I1

I HOME CELL) Y242
IA34-5)

A

I TRACK PULSE I 1203

(HEADS LOADED)I20T

IC35-61

KI41
.143
.'45
KI47
KI49

813

IB29-51
1107

KISI

IA~~~~ - 6 > - - - - - - - - - - - - '

KI53
KISS

(C30 -51

!:C

PRODUCT

1160

~

11611AIII

POSITION LOGIC

tJ
I'

4

3

t

SIZE

C

94 61

A

.
!I

r-----=~====~----===~--=--~-=~~~-=~-~----------..---.HOME CELL
The Slow FF is set when tracks-to-go are less than sixteen.

~

;.

.

.

The output of the FF acts on the motion circuit to prevent

fa~ter than 6 ips.

The home cell is a photocell which receives light if the
. heads are positioned on an illegal cylinder (less than cylinder
I 00 or more than 202). This signal is used to detect a seek
. error or to position the heads on cylinder 00 during a return

rI'

to zer" seek or first seek. ,-

the carriage from moving
cleared by any seek command.

The direction of carriage motion is controlled by the forward FF. The FF forces forward motion when it is set by
any of the following:

,I

I

1.

Heads unloaded and first seek.

2.

Home cell lights while driving in reverse.

3.

Mter a seek has been completed.

.... !The Forward FF is cleared by:
r1L. I

1.

Return to zero seek.

I!

2.

Revers~ seek command.

3.

After heads are loaded during first seek.

4.

When heads are unloaded with motor off.

The FF is

sent to the controller. it will be accompanied by a -Q level
Attention sent via T2 03.

Seek Error FF senses an error if the home cell is uncovered during a direct seek. The FF is cleared upon receipt of a return to zero seek command or power -off seek.

TRACK CELL
DETENT

The glass timing disk has 203 slots on its middle ring to
indicate cylinder position. As the heads move across the

i

The Detent FF (K212/213) controls the detent pawl which
locks the carriage on its specified track. When the FF is set,
cards L200 and L201 are turned off. This deenergizes the
detent coil. allowing the detent pawl to engage the gear.
the reverse seek or upon completion of the seek error recovery.'
Normally. the Detent FF is set by the trailing edge of the
last track pulse during a seek. It is also set when the disks
The RTZS (Return to Zero Seek) FF is set by a control
are
not up to speed and the carriage velocity is less than 2 ips.
\ I select from the controller. Setting the FF clears the Forward
This prevents head scoring.
,FF to enable reverse drive to the home cell. RTZS FF clears

;

The Reverse FF forces reverse motion by clearing the
l.J Forward FF. The Reverse FF. is set by a set head and direction
i i or if a forward seek error occurs. It is cleared at the end of
I··

'I
II

!I

~benthe home cell

light..

_.

Upon receipt of any seek command. the FF clears. This
completes the AND gate into card L201. Turning on the card

applies a high current through coil L210 to quickly pull the
pawl away from the gear teeth. After 2 ms. the Y312 term into
card L201 goes to zero. Card L200 then controls current
through coil L210 to hold the detent in its retracted position.

1

I

·-·-~---I

Stop FF commands the carriage to stop. As the decrement counter counts down during a direct seek. the output
of 11 77 goes to "1" on the trailing edge of the next to last
track pulse (that is. when '1'<2). On the leading edge of the
II SELECTED DRIVE READY
next track pulse. Y243 goes to "1" to complete the AND
, gate to set the FF. The FF is cleared by an any seek command
The selected drive ready signal informs the controller
I
or a motor off and heads unloaded condition.
that the heads have reached the addressed cylinder. This
-Q level is retur~ed to the controller ~ia T202 10.2 rns after
First Seek FF is used to initially load the heads. When
the Detent FF sets. The selected drive ready will be disabled
I the disks come up to speed. the FF sets. ThlS
. sets the f orand replaced by the seek incomplete signal. if the selected drive
ward FF. When the heads are loaded. the Forward FF clears. ready signal is not returned to the controller within 600 ms.
Note that the First Seek FF is also set if a seek error occurs
Seek incomplete is a -Q level sent to the controller via T204.
during a forward seek •
No matter which of the two previously mentioned signais is

",

! DIRECTION CONTROL

I

. .- - _._._. -

.- - - - - - - - - -.-.- - - - - --- - - - - - - -.- - - - - - -------.----.-. --". _-. .------.-----~----

"

disks. the timing disk rotates. Each time a slot passes the track
cell. allowing light to hit the cell. the output on ONA Y244 goes
to "0" and Y243 goes to "1". As the cell goes dark the input to
1203 from Y244 goes to a "1" after 4 usec. ANDing the outputs
of Y244 and 1203 provides a 4 usec trailin~ edge "I" pulse to
decrease the decrement counter and partially enable Detent FF.
The ONA outputs are also used to parially enab~e the ~top FF.

,

All input/output signals are Q or L levels or pulses. These signals are within the follOWing voltage J"anges:.
"-+Q .. +3.5 to +0.65 vdc, -Q" -0.5 to -3.5 vdc. +L" +6.28 to +2.0 vdc. and -L" +0.3 to 0.0 vdc.
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When tracks-to-go are less than 4, 1311 sets ~304/305.

Rate of motor acceleration is controlled by the Not

ro

: Max Drive FF (K212/213).



indicate speed of carriage motion.

I

As each slot permits .light

to hit the speed photocell, the leading edge of the pulse out of
composed ofFF's K300/301 and K302/303. The outputs of
, these ,FF's are applied to three UAB delay cards: Y305, Y306

I and Y307.

If the speed is low enough to allow one

o~

FF K306/307, V<6 FF K308/309, and V<15 FF K310/311.
~ontrol

than 2 ip&

since the Not Max Drive FF remains set.

celeration or, in the case where opposing current is enabled,

maintained in a hit and coast manner.

The

carriage motion.

The motor accelerates

~c

Detent FF sets on the trailing edge of the last track
pulse. The circuit conSisting of 1320 through 1324, and
delays Y330 through Y332 provide a motor stop pulse.

T (tracks-to-go) is less than 64 and V (carriage velocity)
At the s~me time, the ·"1" input

rent to flow thr,?ugh the H-switch.
rapidly braked to 15 ips.

delayed ,by Y331 from 1323 is applied through inverters to
cards L301 and L302 to stop the motor by the time the

IMax Drive FF sets to turn off high current.

The printed circuit motor which drives the carriage is
: controlled by an H- switch consisting of Q03 through Q06.
t---J
U

The

j motor drives forward when the AND gate into L300 is made.
Operation of the circuit during a forward seek is explained
below.

I'

p...
,

Upon receipt of a forward command, the Forward FF
(K206/207) is set; the Detent FF (K212/213) clears to pull
the detent pawl. The direction of seek is sensed by 1305 and
1309; all inputs to 1305 must be "0" to drive forward. Since
velocity is 0 ips at this time, 1305 outputs a "1" and forward
motion starts.

The motor is then

When V is less than 15, the Not

(I309 in the reverse circuit operates in a similar

manner; if all of its inputs are "0" the motor drives in reverse.)

The 15 ips

speed is maintained by serving the motor; 1305 and 1310
alternately output "1 's" and "O's" to maintain a constant
speed.

I

i

'

Operation of this circuit during a return to zero seek
is as follows:

'

6 ips, Not Max Drive FF sets, while Per Dy Brake FF
Speed is maintained in a "hit and coast" manner.

That is, 1305 turns on the motor when speed is less than

f

1.

With RTZS FF set and Forward FF cleared. reverse
drive is supplied by the "1" output of 1309. Acceleration is retarded since Not Max Drive FF is
set.
~

2.

Speed is maintained in a hit and coast manner at

@

6 ips by the V greater than 6 term that is applied to
1309.

i1

When tracks-to-go are less than 16, the slow FF sets.

,clears.

t

3.

When the home cell lights, the RTZS FF clears and
Forward FF sets.

The output of FF K314/315

forces forward drive back to cylinder 00.

6 ips, then turns it off when speed exceeds 6 ips.

r--'I

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*Less than 80 tracks to go for units with serial no.980 and
below not having FCO 1846 installed.

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detent pawl me'shes with its gear.

I

The Per Dy Brk (Permit Dynamic Braking) FF (which was
set at the start of the seek) enables the AND gate input to
1310 to again apply reverse current. At the same time.
Not Max Drive FF is again cleared. Therefore, the motor
is rapidly slowed to 6 ips: When the speed is less than

In

a forward seek, after the Detent FF sets, a 2 ms "0" pulse

to 1310 in the reverse drive circuit causes opposing curMOTION

Speed of.2 ips is

The trailing edge of the next to last track pulse causes
a stop command which combines with the leading edge of
the last pulse to set the Stop FF.

, to a full speed of approximately 35 ips until there are less
than 64'~ tracks to go. The output of 1305 goes to "0" when
is greater than 15 ips.

Note that the braking action is now low current

When a seek starts where tra('ks-

to-go exceed 4. the FF clears after delay Y312 times out;
I the delay permits the detent pawl to dear its gear.
Assume a full 199 track seek:

output a "1" to signify head speeds of less than 15 ips, 6 ips,
or 2 ips. These outputs are applied to the set inputs of V<2

The motor is again dynamically braked unt-il speed is less

sistor Q02 is turned on to permit high currerit flow through

more

their associated inverters will

outputs of these FF's in turn, are used to

I

the access motor's H-switch, this causes maximum acmaximum deceleration.

ONA Y321/322 is used to initiate a timing chain generator

Iof these delays to time out,

I

When the FF is cleared tran-

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NOTES
8,NOT IN LOGIC, FOR REFERENCE ONLY
J:... COARSE ADJUTMENT (FOR FINE TUNING
i l l SEE ADJU5TME NT PROCE DURE I
THE JUMPER WilliNG QN DELAyS Yl30
A"D Y331 IS OPTIONAL rF THE DELAY
IIANGE REQUIRED CA~;NOT BE OBTAINED
WITH JUMPE'\ 4 AND 7, IT MAY BE CHAN GED TO 5 AND T,

&: :.~~ :~: ~:9;5C:DA:~L~;OVE,
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HEAD ADDRESS REGISTER

FAULT

~

(I)

WRITE CHAIN

The Fault FF K400/401 is set if one of the following

<:

The head address register consists of FF A400/401

malfunctions occurs:

!l>

Erase enable is applied to AM- erase driver G410/411

through A416/417. _The output of the register is applied

lia 1440

In order to write. a write enable must be

to the 10 head select cards (G40-) to control which head

applied through 1442 to VKB toggle M415.

2.

Write current OR non-complement write current

will read. write. or erase.

in the form of - L level data pulses. is appli£.!d to UKB toggle
M415 via R400. The UKB switches state at the leading edge

Erase current AND no write current OR no non-

4.

complement write current (if condition exists for by means of the Set Head and Direction line. When this
more than 200 usee).
line is uP. the address and control bus directly sets up the
register to select the desired head.
Read. Write. OR Erase Gate AND no Selected

balance of the output voltages.

Drive Ready.

Y403 sets the Fault FF K400/401.)

6.

Write Gate AND no ac write

The register may be set in two ways. One method is

lected by the head address register. Outputs of both AMdrivers are applied to AND card Y403 to check for anl un-

If it is desired to select the heads sequentially on a

Write Gate OR Erase Gate AND Read Gate.
curr~nt.

cylinder the Control Select line and bit 3 of the address
bus is used to initially set the register to zero.

Thereafter.

a head advance signal may be applied to 1473 to increment
7.

Low voltage condition on disk storage ±20 vdc
or

8.

storage drive.

I
Q)

the register to the next head.

+ 36 vdc outputs.

Loss ofac line voltage (from controller) to disk

In either method. the timing pulse generator consisting

of FF K402/403 and K404/405 provides the enabling pulses
to transfer the count in rank I to rank IT of the register.

One or more of the above conditions will:
.I..

Generate a -Q level Drive Unsafe signal.

2.

Remove all write and erase current from the

READ CHAIN
heads.
3.
4.

The read chain consists of cards A440. A441. D400.

Disable the Set Head and Direction tag.
Set all Q-Ievel type output cards (except Drive
Unsafe and Selected Module) to the +Q level.

L402. and T401.

The analog output of the selected head

is·applied to the ATE gated read amplifier. then amplified
by the EUC differential amplifier A441.

Shaper D400 converts

the analog input from the heads to a square wave output.
5.

Light the SELECT LOCK switch/indicator.

If

the read mode has been selected. the OVA pulse shaper gates
the square wave output to T401 for transmission to the controller
in the form of +L pulses.

All input/output signals are Q or L levels or pulses. these signals are within the following voltage ranges:
+Q = +3.5 to +0.65 vdc. -Q = -0.5 to -3.5 vdc. +L = +6.28 to +2.0 vdc. and -L = +0.3 to 0.0 vdc •

........

Write information.

of each write data pulse; its output is applied to AMG G412/413.
Write current is then allowed to flow through the head se-

3.

5.

~

1441.

More than one head selected.

AND no erase current.

,..

an~

1.

(If there is anunba1ance.

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GENERAL
The power supply 1s completely solid state to provide
low dissipation and high reliability to the operating
system. The power supply provides an adjustable ~20
vdc to the logic chassis, +24 vdc and +20X vdc to the
access motor and detent solenoid, +20Y vdc and +36 vdc
to the power sequencing ci rcui t, +40 vdc to the Write
circuit and dynamic braking circuit, and 24 vac to
the brush motor circuit.
The main power supply is supplemented by an auxiliary
power unit which provides +5.7 vdc for the fiber optic source lamp.
These voltages are sequenced and coupled to the related circuit in such a way a6 to prevent Improppr
head loading, track accessing, or disk movement.

DC

P~ER

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The junction of resistor!. R07 and R08 is driven to
+24 vdc which is applied to the H switch and detent
circuits. R£'sistors R2~ and R41 develop +36 vdc at
their junction for power s£'indle
motor, M360. K04 contacts 1 and 4 open and apply an

in the fiber optics power supply. Rectifier diodes
CROIA and CROIB develop +5.7 vdc at their junction
and apply the VOltage to filter capacitors COl and
C02 and filter choke LOI. The filtered voltage is

CIRCUIT

The 208-volt input power is applied through th€' closed

t-'
N

Resistors R07 and R08 and resistors R25 and R41 form
vo I tage dividers. The +20Y vdc d,'veloped at diodes
CROIB and CR02B is appli(>d to r .. sistors R07 and R41.

S"qu£'ncing of power "ithin the pow!>r supply is accomplished by seven relays. This sequencing is necessary
to prevent damase to the heads and/or disks and to
ensure proper control of the actuator mechanism by the
logic.

latch solenoid (L201) when the disk pack is up to
speed.
At 80 percent of the rated speed, the logic completes
a circuit to .. nergiz .. relay K05A through J03-X. Wh£n
this relay .. nergizes contacts 1 and 4 op .. n and a signal is applied to the logic, indicating that thE' pack
is up to speed. This signal is applied to a 52-second
delay card which allows time for the air to bE' purged
from the disk pack area befor(' loading the h('ads and
for the brush assembly to complete a clean cycle of
the disk pack.
Contacts 1 and 7 of K05A close to provide +40 vdc to
the Write circuit and contacts 2 and 8 close to apply
power to thE' head latch (L200). Onc .. the heads are
loaded, the solenoid armature holds the heads loaded.

Motor sequence relay KOI is energized when the unit
receives a sequence in from either the control unit
or the previous storage drive on the line. If the
disk drive unit START switch is not lighted (5301
spt to Off), the sequence out leve 1 is applied to the
next storage drive. This se,:!uencing of the storage
drives is nE'cessary to prevent loading of the primary
power source.
As!'ume that a Power-On cOlTIIIBnd is received from the
control unit and the START switch (S301) is lighted.
The +36 vdc is applied through connector J03 to complete the path and energize relay KOI. When relay
KOI is en"rgized, contacts 1 and 7 close to energize
re 1ay K02. When K02 is energized, contacts JA and
3C close to supply +20 vdc to the logic chassis, and
contacts 4C and 4 .... close to supply -20 vdc to the
logic chassis.
Relay KOl aho completes the pl1th through contacts 3

POWER-OFF SEQUENCE

POwer in the disk storage drive can be cycled off 1n
any of three ways: from the START switch on the disk
storage drive operator control panel, by opening either top cover, or from the control unit.
It is assumed that the purpose for this Power-Off sequence
is to change packs. Thp sequence 1s initiated when
START switch S301 is pressed, opening the contacts
of S30lA and breaking the circuit that holds relays
KOJ and K04 energized. The following events occur:

1.

K03 contacts '}A/2e, lA/Je, and 4A./4C open and
remove power to the spindle motor, H360 (rotation begins to slow).
(continued)

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---- logic senses the spindle motor speed is less,
than 50 rpm it de-energizes relay K05B. This causes
the following events:
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2.

3.

K05B contacts 2 and 8 open to remove the +20X
voltage to the sector solenoid. (L30l) and
the access motor H switch (prevents further
movement of the carriage).
Contacts 3 and 6 close to energize the brake
solenoid (L300) so that the pawl on the spindle
lock assembly engages the spindle lock disk to
hold the spindle stationary.
Contacts 3 and 9 open, de-energizing relay K02.

When relay K02 de-energizes, contacts '3A/3C and 4A/4C
open, removing ~20 vdc to the logic chassis.

The holding current flows through resistor R13, reducing thl' current to approximately 2 amps. When the
detrnt command is recrivro, power is removed from the
base of QOl and current floH is stopped. In approximately 2 msE'C the spring-loaded pawl is pulled into
and engages the detent gear.

PRINTED CIRCUIT MOTOR HOrrON CONTROL
The printed circuit motor, which moves the carriage
drivE' and positioning mechanism, is controlled by a
5-transistor s,,,itching circuit. By controlling the
transistor selection and the amount of current through
thE'se transistors, the motor is driven fast or slow in
the revers£' or forward direction. Transistors Q03 and
Q06 arE' s",'itched on for a forward operation, causing
thE' printed circuit motor to drive the carriage for....ard. Transistors Q04 and Q05 are switched on for a
reverse operation, connecting the switching circuit
in such a manner as to allow motor current flow in
the reverse direction.
The five transistors (Q02 through Q06) ar'e normally
gated off by the +24 volts applied through resistors
to each base. Emitter voltage, applied to the PNP
transistors, is supplied by the +20X voltage source.
The base bias voltage is greater than the applied
emitter voltage to assure that the transistors are
cut off when not selected. When a move command is
appUed, the base resistors complete a voltage divider resulting in a forward-biased transistor.

not needed. 510'.. speeds are maintained by servoing
and not current limiting. Circuit breaker CB07 prevents sustained high-level currents from damaging
the printed c i rcui t motor.
Assume that a forward move corranand of greater than
64 tracks is received; ground is applied through pins
P and S of pO'~'E'r supply jack J03 to bias on the respectivf' transistors. The Fast command or ground
levE'l applipd to J03-P turns on Q02. The ground
lpvel appliE'd through J03-S fo!','ard biases Q06 and
Q03. Electron flO',,' is through parallel resistors
R32, R33, and R~4, through forward biased transistor
Q06 to the one side of the printed circuit motor.
From the motor, electron flow is through resistor
R20, fo!',ard biased Q03, and forward biased Q02 to
+20X vdc. I';ith electron flow through Q03 and Q06,
the motor is driven forward. Transistor Q02 shunts
resistor R17, resulting in maxinrum current flow
through the motor and consequently maximum motor
acceleration. w'hen the Decrement counter indicates
less than 64 tracks remaining, and if the carriage
velocity is greater than 15 inches per second, the
following occurs:
1.

2.

3.
Resistors R29 and R31 prevent overdrive of transistors
Q03 and Q05 respectively. This allows the amplifier
card inputs to the s'Jitching circuit to drive both
sHit ching transistors (Q05 and Q04, or Q03 and Q06)
in parallel, even though the emitter reference voltages are different. The values of R29 and R3l are
self'cted to provide equal drive to the parallelswitching transistors.

4.

5.

DETENT CIRCUIT
Upon receipt of any seek command, transistors QOl and
Q07 are forward biased and the transistors are gated
on. When the transistors are gated on a high current pulse is applied through the detent coil L210
which quickly pulls the detent pawl away from the
gear teeth. After approximately 2 msec transistor
Q07 is gated off. Transistor QOl remains gated on
to provide holding current for the detent coil until
a detent cO!!l1land is rE'ceived.

The magnitude of current in the printed circuit drive
motor is determined by the power supply voltage and
the total effective series resistance in the circuit.
The voltage supplied to the switching transistors is
fixed, but the total circuit resistance during th~
high current drive, excluding the saturation resistance of the swi.tching transistors" is approximately
2.5 ohms. After the current is reduced, the total
circuit resistance is approximately 12.5 ohms.
The use of series resistor R17 during s low speeds
f)revents excessive current and motor torque when

6.

7.

Q03 and QOb are s,,,itched off and Q04 and Q05
are s"itched on (Q02 remains on). The reverse
current through the motor causes the motor to
sl()l~ the carriage down.
When thE- carriage speed has slowed to 15 inchE's
pE'r second in the forward direction, Q02, Q04,
and Q05 are turned off.
From this time until the Decrement counter indicates less than 16 tracks remaining, current
pulses through the H s,yitch are used to sustain
15 inches per-second carriage speed.
With 15 tracks rE'maining, Q02, Q04, and Q05
turn on (Q03 and Q06 turn off), and again the
motor is us~d as a brake, s lowing the carriage
to 6 inches per second.
At 6 inches per second, Q02, Q04, and Q05 tum
off and current pulses (through R17, Q03, the
motor, and Q06) sustain a carriage velocity of
6 inches per second.
With 3 tracks remaining, Q02, Q04, and QOS tum
on and Q03 and Q06 turn off and slow the carriage to 2 inches per second.
At 2 inches per second, Q02, Q04, and Q05 turn
off and current pulses (through R17, Q03, the
motor, and Q06) sustain a carriage velocity of
2 inches per second.

When the selected track is reached, the spring-loaded
pawl is dropped.

,

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POWER SUPPLY
PART 2

NOT IN POWER SUPPLY,
~OR REFERENCE ONLY.

'2

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4

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2

TO HEAD SELECT
LINES IN LOGIC

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TO WRITE DRIVER
AND READ AMP

TO ERASE
DRIVER

I!i!JIDll!l!DJM;JJ
~.&i>r",-:·r.'~;';~
....

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DEVElOPMENT
DIVISION

TOTe<

CARRIAGE WIRING
MODIFIED 200 TRACK

DRIVE

RAil

~

(t)

<:
CO)'TROL I:NlT
POWER OS

~

SEQ RELAY (!tOll
El"ERGlZES ""'EXT U,,"'T

SEQ PICK
TO 1:!\1ToO

)m

,TO:

SPEED RELAY

POWER APPUED TO
SPf!\'OLE MOTOR

KOS PULLS

CAl( lAte_
E!\'ERGIZES

CUt DECCTR

t-I
I

60 SEC
DELAY

t-I
00

t1

CAl( LATCR

CUt IlETENT FF
CUt STOP FF
SET FWD FF

SET 1ST

SEEK FF

DROPS

FF

CARRIAGE MOVES
FWDf! G"'SEC

HEADS
LOAD

HEADS LOADED
APPROX TRACK

~

C ARRlAGE MOVES
REV {l 2" SEC

ISO

Q020FF LOW
CURRENT TO
ACCESS IITR

Q020N HI
CURRENT TO
ACCESS IITR

I

FWDFF
CLEARS

SW TRANSFERS

L....:.....--

1ST SI£EJt FF
CLEAIII

HOME CELL
LIGHTS

~

FWD FF

SETS

CARRIAGE

..wa

FWD{l 7' SEC

HOllIE CELL
OOESDARIt

NOTE

&

H

TRACItCELL
UGIITS

STOP FF
SETS

12 SECONDS FOIl UNITS WITHOUT
PACit CLEARING BRUSHES

TRACItCELL
OOESDARK

DETENT FF
SETS

ENAllLI: ON
CYLUNE
TO COh'TROLlZR

10 NRC DE LA Y FOR
SETTLE OUT nME

1......

D ... ADDU ..._ _ _

I
6.11

Fint .....

"""""'!"""

......
I
......

"TellO POll t."lGTI -n'II • If QIO AND IDWD
MDT IlAVIIER
AODRESSREG

PULSE ReVD

FROM CONTROLLER

SEICD t:NtT
SELECTED
TO CONTROLLER

• DE\"ELOP A.'''Y
SEEK PCLSE

C LE.U DETE:'.
FF

CUlSTOP

"
CLEAR FWD

"
ESABLE
RE\' DRI\·E

CLEAR RTZS
FF

DISABLE

SET FWD

ESABLE

FWD DRIVE

FF

FWD DRI\"E

DISABLE
RE\' DRI\"£

......
I

N

o

AT E~" or Pl:L5E
DISCOSTISt:E ALL
ACCESS ~1T1t Cl1UU:~-r,

SET STOP

FF

·SET DETE:.-r

FF

10 MSEC DEL>.Y
SETTLE n~IE

SESO OS CYLDIOER
TO CO~-rROLLER

DETE~-r

DROPS

. R.turll to Zero SHk

. .(';'''·'':··''''~'I':'''..~~'''

"~" ... - .... .,;)...... ···t......,

CARRIAGE MOVES
FWD{J 2 no; 'SEC

DETE~'
Pt:Ll~

Pt:SH
START SWITCH

HEAD LATCH
DEENERGlZES

CLEAR FWD
FF

ENABLE
REV DRIVE

CLEAR DETE?Io"T
FF

DETENT
PULLS

CARRIAGE RETRACTS
@ 2"'SEC

~20X

TO DETENT AND
ACCESS MOTOR
REMOVED

-40\' TOR 'w
REMOVED

..I

HEADS LOADED
SWITCH TRANSFERS

,J
..l

Pl"SH CO:o."TROL UNIT
POWER SWITCH

-20V APPLIED TO
SPI~nLE MOTOR
(D\"!\AMIC BRAKING)

-20V TO SPINDLE
MOTOR REMOVED

... 20Y APPLIED TO
BRAKE SOLENOID

SET DETENT
FF

+2OX TO SECTOR
SOLENOID REMOVED

SECTOR BLOCK
RETRACTS

CO:o.'TROLLER SEQ
PICK U:o."E
DISABLED

1ST UNIT SEQ
RELAY DROPS

1ST UNIT SEQ
HOlDOUT
DISABLED

~

NEXT UNIT SEQ
RELAY DROPS

UNIT SEQ HOlD
OUT DISABLED

SPL....nu LOCK PAWL
E!\G..-\GES LOCK DISK

LAST UNITS~
RELAY DROPS

SPINDLE
STOPS

LAST UNIT SEQ
HOlD OUT DISABLED

CONTROLLER POWER
RELAY DISABLED

IT>

~

~

414

Power OFF Seek

MOTOR ON

SPEED
II

HEADS LOADED

I'

<

FIRST SEEK
FORWARD

SLOW COMMAND
SLOW
STOP COMMAND

CLEAR DECREMEN'f - - - - . . . . ,
COUNTER
I

I

- - --- - - -- ..,I..------------r----------r-:-------I

STOP

I

I

DETENT

:I
II

REVERSE

I'I

ON CYLINDER

II

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MAX. DRIVE

II

FORWARD DRIVE

_

REVERSE OR IVE
V< 2

I'

"

V< 6

"

-

V< 15
HOME CELL Y241
HOME CELL

:r. 201

HOME CELL Y242

________________

I
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~.

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~II~~

~----------------~II

u

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ANY SEEK
12 SEC. FOR UNITS W!THOUT
PACK CLEANING BRUSHES.

~~~-----------

II
II
II
II

,. .: ., .: .,

.......- - , . .

::

~:------

II

II

Rev A

I~----------------~I~I----~~~~----_----

----------------~------~~~------------r-----------------~

HOME CELL 1200 - - - - - - - - - - - - - - . . , . . , :

L.!:l

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----------------~-------I~
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......--...:...:-------------'--II

:~ n'--____

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4J5.

FIRST SEEK

1-22

TRACK

00 TO TRACK 20

TRACK 198 TO TRACK 215
( SEEK ERROR)

FWD SEEK

n

n

ANY SEEK

n

DETENT

I

n
I

I
I

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FORWARD

I
I

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STOP COMMAND .

I
I

STOP

I
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T< 4

V< 6
V< 15

I

I

I
I
I

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I

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FWD DRIVE

I

REV DRIVE
MAX DRIVE
SEEK ERROR
ERROR RESET

HOME CELL
~ (DELAYED)
END OF SEEK
STOP PULSE

~

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01 REeT SEEK FORWARD

1.-23

Rev

---~E----rn____________________
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00

Cii------TRACK201O TRACK

REV SEEK
ANY SEEK
DETENT

TRACK 5 TO TRACK
(SEEK ERROR)

-5 - - - - - - - - -..
~I

~-------------------------___________________________

n____________________

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REVERSE
FORWARD
1st SEEK

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T<16
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STOP

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SEEK ERROR
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I

END OF SEEK
STOP PULSE
ON CYLINDER

rull:-------------------------------~n~-------

--------------------------~

~

_____________________,r_

_ I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

4J20

DIRECT SEEK REVERSE

Rev A

1-24

RTZS
ANY SEEK
RTZS FF
DETENT
REVERSE

n

n

II
I:
I
I

I
I

T< 64 (2)

II
I

T<16

II
I

T<4

II
U
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STOP COM
STOP FF
V<2
V<6
V<15

I

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I
I

'-::: :,:::]
L

I

FORWARD

t:::,:: -

FRO DRIVE

[~\~'_::_;-:::_::~]~

REV DRIVE
MAX. DRIVE

______

~n~

____ ______________________
~

I

~Il~

____

_______

I'

HOME CELL

(DELAYED)

--------------~~------~I_I-----------------

GATED TRACK
PULSE

____~________________-~IIlOO

I

1

I
'1

I

END OF SEEK
STOP PULSE

I

__________________--------~Il~------

'.;.'

I

ON CYLINDER

~--~:~------~--------------------~~
I
I

I·

NOTE:
(I) THE LENGTH OF THIS TIME IS DIRECTLY
DEPENDENT UPON POSITION OF CARRIAGE
PRIOR TO DOING A RTZS.

I

I
I
I

I

t'E-- (I ) ----+f

(2) T <80 FOR UNITS WITH SIN 980 AND
LOWER NOT HAVING FCO 1846 INSTALLED

4J21
RTZS

1..,25

Rev A

I

(

---.J

INDEX

J l - - - - - - - - Irc

CONTROL

~

GAP AREA ZEROS
31 BYTES

ADDRESS AR EA

Ie

-.::

READ
RECORD
FORMAT

JJ

GAP

27

! (

JJ

J)
( r

I

'DRIVE BUS 5 ~
(HEAD SELECT)
I

---!

I--

I

60 i'SEC MiN

JJ

r r.
JJ

rC

'

L

JJ
(

JJ

o

BIT VALUE

....

GAP
AREA

I '-

J J

( r

DRIVE BUS I
(READ GATE) _ _ _---J

I

DATA) JRECORD

AREA
BYTES

L
L

,

II'

0

READ DATA
(EXPANDED) 150--l
WRITE
RECORD
FORMAT

(±50)1
NSEC

-----------------------r-------------r----------------------~(~-.::----~~---------RECORD N
GAP AREA
RECORD N + I
II
I G'AP AREA
I

CONTROL

I

I

8

DRIVE BUS I
(READ G A T E ) - - - - - - - - - - - - - - - - - - - ,

BYTES--I
I

l-

I

I
I

I

I

I

DRIVE BUS 4
ERASE GATE

2 BYTES

-r';ITi:.

-----------~1--'j.:.~2 -i

'r'~~~------

~T7ITI:-

i-- T 4 - - ' -.....i-;~2-i

IlL.____________________:_____--'n. ._______

DRIVE BUS 0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...

1011------

WRITE GATE

T3 - - - - - - - - - - -•.-jl

o

BiT VALUE

}OOUBLE- FREQUENCY RECORDING
WRITE DATA·
(EXPANDED) 150-1

(:t 75 )'1

.

NOTE:

N SEC

--I

400 L
·1(.!'0~F>
NSEC'

' - - 800-../
(;to.3%)
NSEC

I

I

1.

Tl - ERASE GATE MUST COME ON COINCIDENT WITH WRITE GATE WITHIN 10 USEC.

2.

T2 - WRITE GATE MUST REMAIN ON FOR A MINIMUM OF 45 USEC.

3.

T3 - ERAS E GATE MUST BE DROPPED WITHIN A MAXIMUM OF 80 USEe.
AFTER WRITE GATE IS DROPPED.

4.

T4 - WRITE GATE MUST REMAIN OFF FOR A MINIMUM OF 12 USEC.

Read & Write Control & Data Timing

1=26

v < 2 IPS

6 XPS

'(

SPEED CELL TIMING

_10

-~l
j
'j

.

+IIW
..... 11,14

IlOI

IlOI
4TO

lin

lin

IP

'bI

+

001&

IIV

LOt

-

LOI

.-

+

&

cOt

1'0.1.

IIW

+
+

cot

lev

&

lIN
.'0

--& .

..

1t04

III.

I

" .i

. i
~

'j

" •••••7..........

..

--

~

2::!!-

-IOOUII

~
\b

.

.~:.'

011
• "OJ"

• IIAW

1C11101

+IIV

COlI
1'0.1"

COl

IIUP

........

IOOUM

IOOUII

1C1101

~~up

.

"I

...4.1

-IIV

.'I.',

+.

.IV

III.
-lOW

NI.I
"

i

·

I. ...., IIMIANIUM I0Il0101.
• ZDIIII 10140111.
. ..... IILICOII 101l0l00.

~

± 12V.

VOlTAGE REGULATOR
.1

41

L

. Rev- -D--..J

PART 2

CARD PLACDfENT

Card Placement information
for the 9461 will be found
on ~age 1-11 in this manual.

·

,

PART 3

WIRE LISTS

example at a switch or resistor.

A sequential advance in the second to the last digit

indicates additional inputs to the same card.
A sequential advance in the last digit indicates the interconnections of an AND input.
K1031D}
K10311
Three input AND to K1D3
K10312
K1032D - Single input OR to K1D3

Wire Length
This column gives the wire length in inches.
Wire 0 rigin Location
This column locates the origin of the wire on the logic chassis.
signal at two or more locations are interconnected in series.
three wires shown have a common signal.

Wires having a common

In the sample, the first

The Wire Destination Location of the first

wire becomes the Wire Origin Location-of the second so that the series string is from
A18 to B11 to B2D to B22.

Note that the first four characters of the Wire Identification

terms are the same for the three wires and that the sequencing is from 10 to 11 to 12
in the last two characters.
Wire Origin Pin Number
This column identifies the origin pin or terminal of the wire.
Component Code
This column identifies the components that are located in the Wire Origin Location
column.

o-

The code letters ar e identified as follows:
Logic Card

R - Miscellaneous Component (Switch, Resistor, etc.)

x-

Jack

Wire Destination Location
This column locates the destination of the wire on the logic chas sis.

Wire Destination Pin Number
This column identifies the destination pin or terminal of the wire.
Wire Size
This column identifies the size (AWG) of the wire.
Twisted Pair
When two successive wires have the same letter in this column, this identifies them
as a twisted pair.
Color Code
Multicolol~ed

Solid colored wires are identified by a one digit number in this column.
wires are identified by a number having two or three digits.
identifies one of the colors.

o-

Black

1 - Brown

Each digit of the number

The code numbers are identified as follows:

2 - Red

4 - Yellow

6 - Blue

8 - Gray

3 - Orange

5 - Green

7 - Violet

9 - White

S - Shield

Change Order
This column identifies the engineering, field, or publications change order that
affected and/ or altered that wire.

3-iv

WIRE LISTING

REMARKS

Wire lists other than logic are on a standard corporate form.

The remaining

columns of the form contain information NOT normally applicable to
field usage and therefore are not explained.
The other columns indicate:
Gauge (Ref)

- Size of conductor (AWG)

Color (Ref)

- Color information

Length (Approx) - Length of conductor in inches·
Origin

- 0 rigin point of conductor

Destination

- Destination point of conductor

Remarks

- Useful comments

In multi-digit color codes, the first digit denotes base color and the remaining digits
denote tracer colors.
for logic wiring.

The color codes for the non-logic lists are the same as those

')

--

,- -

.........

,;('

,-..._-.-

........... ~'-"'''--'''''
.,.

,

"

lW45587600

9461 OSO

..

•

A40010
A40 11 0
A 40"0 11

.

04

C09

01 0

02

C 09
COB

"1ft';','

"'t''',,j,,

C08

12

·946f-OS(j

04 0

CO 8

06

946....;:1=---.;..0....:;.S--=..0___________''_'"--_________.......:-............______

COo
COo
CI0

11

COB
C09

12 0
Ob 0
07 0

9461 050
9461 OSD
9461 OSO---------------""""-----

C09

07 0

COb

09

C09
C09
Cl2

10 0
'10 0
01 0

CIO
COb
C11

06
10
12

A40111

03
03

A40211
A40310
A40311
A40410

02
03
04

A40411

04

CII

12 0

C06

07

A40510

02

Cl2

04 0

Cll

06

9461 osn
9461 OSO
94610SD
9461 OSO
9461 05D
9461 DSD

A405l1

04 . C11

06 0

COb

08

9461'=---=O-=:S...::::.O_ _ _ _ _~_ _ _~_ _ _ _ __

A4021J._JL_~~~_ _1J

121210
03 A33
01 0 A31
06
_I.2J}.1!L __ ._Qi?_ ~_3_9 .. ___ 0 1_n_~.~~Jl6__ ._~4~.1_ v~n ________._______
121410
05 K2H
04 0 A2~
06
~461 usn
____ l~ 14J 1_ .. ____._ Q5 ... _82H __ .. l)~ _q.. _G2~ _ _Q.l> __ ...__ 946J_Jl~(~ ___.__._.___.__.
121510

06

C24

10 0

D1-'

06

'J4bl

f)~O

2~39

l2_ ...~Q5_. O~.Q_C.}_t}_ _()2 _ _!i.~_~~_Q.~L_. _ _ _ _ _ _ _ _ _ _ _~2024
07 C30
02 n c:;~
03
9461 050
2029

_._~~J? 1 (1 _. _. _ _

121611
_ _1_2.1.6 1.? __ . __
121613

121710

15___S.38. ___ .q 3 __Q___~)_Q}_ _~ .~.

12 n
07 0

D01
C35

10
12

C24
011

-f21711-·---0 4--·-·011----05--0 008

Y4_~J_[~~..)___ __

q461

9461

2539

DS!)

2~3CoJ

osn

1193

946"i-·Ds·rl-----·

12

11~3

C35
08 a C34
12
9461 Dsn
1"5-- G34--"--1 2·-"[) -·c-o~~--i·i---ij46 1-05-0-------··

03

121720
-I'z"i--'"2-i-121730

121131
121740
---i-218
-10·-.
121till

12
05

01...
OR

C35
C 31

09 0

05

C31

05

1.)·---'-33----1

os 0--·---·----- - ..-.---....-.--.--.-----------

-----Ob---C25

02

C3~

01 0

C3~-~-"12-

C35

1~

06

C2~

01 0

Clb

05

9461 nSf)

122010

02

~2H

07 0

H2~

10

9461 OSD

122110

08

C2Y

01 0

A36

12

~4h1

122510

09

C36

010

122611

03

A2H
11
Y461 050
C2 M--·-·()5---Y4-6I-f)S-O------C32
11
9~61 DSO

.n."

10 0

Y461 Dsn

f·--·--·'~f4"i)·1

9461 OSD
-.------ ,)461 ·OS-f) ----.----.---..-

. ·--fi1:~ 10--- ._ .."1 i-- 03-5--··-··--10 Ll-A-34--6"6--ci461-[)sT)----·-·

1522
------1522A

--t-i20-tl-··---oi·--B2cj---10···()--C3~--f2---(-i4-i:;1-0-5-0----····--

OSD

- I 22"ifo· ··---·61 0'·····--'--·'
146620
146621 ...
146630
146"-'1()'-

07

017

---·-···0~-·C06·-

it) -n

_

. DSf) - .-. . ------.---.-------.--.---.----.-01 0 C12
02
9461 OSD
·-01 ··O-·-·bo7 -"--05'--'-94'b l-os-rY---'-- ..----.--.-------.----.-.--------'- -.-- ---.-.-.
-C0'1------·08-----~4(,_1

05 COb
()2 0 H07
09
9461 DSO
----IO·--..C07--- -01 O--AO'2-'--Ob-- --.- -'1461-0Su------------------· -----.--------- . .-.... ------... ----- --10

07 0 003
12
9461 050
1350~
-- 07-n--fil1-·-os---Qzt61-·-lrStr--··--- .... - ---.----H06
OR 0 A02
08
9461 osn
08 0- -- Dlo ·----OA-----94f>1 D${y------··- .-.---.-.. ---- . . - ...---.----.. ---..-.------ .-----.. - .-.--.-

Bl1

--'-04"-~06

06

OY~06

09

03

1106
-~tj5

09 0

~.

-07

f)--

012
~

rl\ib"---

11

-12-

'1461
--·-···-·~461

DSI)

"1>5,1)'-------

----

_.'·M_.

-~

146810
03 H05
01 a
B04
06
9461 OSO
T46':i fu--------b-2-Ctil---C)4·--0---·Col--03··-Y461-tIS·u-.--.---147010
02 COl
10 0 COl
09
9461 OSO
1471'10"-- -.- ---02- Clli" --. o·'-rf--CU-i!----04
946"l-oSrf----·- ---.------------.------ --. -"_.147111
02 C02
()4 0
C03
04
Y4b1 nso
147112"- -------(YS··-CO 3"-' '-04() -'-lH)3--0'''- ------946-1--I.)S·f)----·-----·
147210
02 COl
01 U C02
03
Y461 DSU
-C4"-'I211----03-C02--03-·0-C02
10
(:f461-f)Slj--'147212
06 C02
10 0 803
06
9461 DSO'
T47310 .--- .-.- 03--- Aut
04 - 0 --- Aol--' 09 ------·9461-050 ..
147311
12 A02
09 0 010
09
9461 osn·
1'41"410-- .... --'--04--'1)03-- ···07·0---U10-----OS-··--Y4bl··nSn--- --- . --·------·---·------···-··-1350- -.
147411
11 010
05 0 E~l
04
9461 050
1350
T4T4"ZO-lr-D'O:r---o-s-'n Cl4
0-2---'l4oTliSn"
I 35UB-147 4 30
IH 003
09 0 A33
05
9461 oso
13508
T41510 -------08-n06-----"Q4·0 -·-liOr----OB·· - --9461-'OSiY-"'--' -.-.----- . - --147620
04 003
02 0 OUl
12
9461 OSO
141'710-- --03'----07 U -- 003---06-"-'---94-61"-OSO -"
--"----'---"---"--'-_ . ' --.. -.. -----.-.. -.. --.-....
oo~

147720
-14.-""{H"l-O

09

005

08 0

HOM

03

9461 OSO

03-·I)·(f6----·--rO-o---fruo--o-~r---'f4-6T-T)Sif----·

. ---- ----,

Kl0010
10 A17
01 0 C11
12
9461 DSU
Rlo(f:(cf" ··-----{l"t;----Al1---·-02---U·-- ,f11"---'---05--- ---94bl--0Sn--- ...
KI0021
06 B11
05 0 820
06
9461 OSO
K-f003'O ------Oz;-----A11-----0-3--0··-- ·A-fT--·--14-------~r4-bl-·- OS-I)---' -- .

-_ ..•..... __ ..

_._-_.

--_._-_._-------_._------

---------------_._---_._------------_. -----

Rpv A

3-6

~

~

~

-----.---------

--'

Rev'

J

LW45581600
Kll131
KIl2IO
K11220
KlI221
--KlliF22
Kl1230
--lfi-r:r10
K11311

-I{Tf3"f2

9461 DSO

11

09
05
03
06
04

"05

03

C1S
A23
A23
A16

10
01
02
11

0

E32
Gll

0

12
06

Alb~---1~1~--~9~4-6~~1~D~S~D----------------------------~

0
0
A23--02 0
A23
03 0

AIS
B25
A23

07
06
14
12
08

Ai3--67o--Alb
A16

0(')
06

A23

11

12

a

AI5

82~

.0-;;( 0

K11331

-K-l-14-Z 3
K11430

94-:-,6..::::..1-=--D-=-SO-=-~-----------------'---

9461 DSD

9461 DSD

9 46{--5'55----

10
05
03
03

C1S

11 0

E33

04

9461 Dsn

A24
A16
A24

02 0
09 0
02 0

A16
A15
825

09
05
04

9461 usc
9461 DSO
9461 DSD

04

A24

03 0

A24

14

A2.'4--0f'o-cTT-05---946'l--rjs-tJ - - - - - - - - - - - - - - -

-o2--~ri5--04-t)-Bib--(f3

94'(;lOsIi--------------9461 OSD

6-5-A-24--0'1 [)

Ai1,--lO

9461 D s - b - - - - - - - - " - - - - - - -

Kll5ll
K11512
Kl1513
K11520
Kl1530
K115 31
K12010

'03 Alb
05 A24
02 B25
06 A24
09 A24
11-C-18
04 820

A15
B25
826
A13
C18
E3 3
Al1

9461
9461
9461
9461
9461

Kl2110

Al1
06
9461 Dsn
(Ys-Af7'---"(Y6--o-'-A-rl--f2--94-61--0'SD--04 822
01 0 Altl
12
9461 OSO
oS--ATS---12-0--AT1--09-'- - 9 7 . t 6 - 1 - D S O - - - - - - - - - - - - - 06 B22
04 0 A18
06
9461 OSD

--Kff~rl0

---:-K-::-:l;-:;2011

-KIzlIT
Kl2210
(1)--"T2'2YI
~
K12310
K12311
K12410
-KIT4TI
K 1251 0
-

9461 DSO
'Jlt61D"S:::-c=-O---------------9461 DSO

12~--"J~4--;-6~1~D~S-:::-O----------------I

Kl1320
A23
08 0
A13
06
- - Krf3'3'(j'-----09-Ai3---0")---u"--·tI'B--·-ff

--K11'4:ro
Kl1420
K11421
Kl1422

9461 DSD
9461 OSD

10 0

07
05
08
09
12
01

o4-AI--t--rz
06

820

0
0
0
0
0
0

0
07 0

0
01 0

9461~l)·--------------

06

A 19

'06

9461 0 S0

A20
All
A20

12
05

All

12
11

9461 OSD
9461 oSD
9461 OSD
9461v'l"'"'ST"OO--------------9461 OSD
9461-.....0.5
... < " < " 0 - - - - - - - - - - - - - - -

06

9461 DSO

B2 1

0"1 0

-iIT2611
K12710

06

A20

06

B22

f2 0
10 0

623

01 0

B22

04

~79TI

~A2l--l}6

K13010

04

-KTIoTl

00

05

A21
823

lTl)
07 0

Al2
A2l

All
B24
01 0 A22
-';'2-2-.--1"2'-'U-]);12
B24
01 0 A2l
0

-1(13111

06

A'Z2

06 0

K13210
12--"K"'I-"'321: 1

04
06

825

01 0

A23

A23
B25

12 0

Al2

11

K13310

05

10

K133TI

Or--AZ3-~Ob

9

K13410
K13411

06

O'o-A2lT--Obo--AfI--06
05
06.

04

826

o~~-zt

~~4~6~I~D~S~O~-------------------------

9461 usn

Al 1-0-8
....-----.9"'4.---;>6--..1,--,.0·......5 " " 0 . - - - - - - - - - - - - - - -

01>0
07 0

--,..,K. . .l. . .z-sn
..
K12YI0

8

11--':T4-6-10S-5 - - - - - - - - - - - - - - -

05~r9-----r£O~1

A19

B21
A19

K13110

DSD
OSD
DSD
DSO
OSD
.1
'146 i OS=-:Oo--,------------1-,-.1,,--9---.3-'-'
~4bl Dsn

10
12
01

A~

04
05
05

K12810

06
05
12
09
12

Ail

o~-1~~6

......Kr..1C"'7"t2TI 1
K12610

~T27n

06
O~

946-,....1--....0.S
... - . . : : - 0 - - - - - - - - - - - - - - - 9461 DSO
09--9461 OSD
06
9461 OSD
10
9461 os.....o . . - - - - - - - - - - - - - - 12
9461 DSD
01
9461 OSO
06
9461 OSD
08
94OTlJ-..r-S7"<'"O-----'
12
9461 DSO
05
9461 'oso
12
12

Al2

07 0

A23

0

All

01 0

A24

12 0

All

7
---------------------------------------------------.~----------------

5

---

4,

3

--~R~e~v~A~------------------------~3--~8--------------------------'.,-1 •. ,....

"

,',.

_,'

','

,

~I-O---- 0-5---t\-2b---04-D~~4--0-6

K13511

01

A24

Ob 0

Al2

Ob

941il-nSD
DSO

~461

---;n401-rf----04----~rb---Or-O-812-_--1-2--946-1-iYs-D=----

K14011
13 B12
12 0 E30
O~
9461 osn
-1(1-4110------04-- -B 1 1:)-- "04 (Y-tfi ~-----r~r--9-4{,-r--OS{)-K14210
04 B16
01 0
B12
11
'9461 OS!)
-1<.-1421 r-----1-4----sIz--11-0-E3U--rO---li46T--bs 0 - - - K14310
03 Bib
10 0 Kl3
11
9461 usn
-K144-10
04 B17
01 0 B12 ,10
941)1 OSf)~---------------K14411
13 B12
10 0 E31
03
~461 oso
-1("1"4516-------- 03-- ijl T-04 --0------613--- 10------- 9461--osh -------:-----Kl'+610
04 B11
07 0 Bl2
09
9461 ()Sf)
~·i4-6fl-I-·-·--·14---~-li-·-09--·0-E-31-· 09"'---Y46-1
nslj------·----··--~-·-------·---------·---K14710
04 B17
10 0 B13
09
~461 OSO
K14810
----14 -Bl-a--01 0
E32
05
9461 osn
K14Hll
05 B18
01 0 B12
08
9461 050
-K-f4~t()
04---BIB--04(-}-HI-3
08--9461 OS-O--K15010
14 B18
07 0 E32
10
9461 OSO
-K-r"-Olf----04-A18---01-0~f2--01--ij4i;lOSO--

K15110

04

SIB

10 a

813

K15211

05

H19

01 0

B12

14

R19

07 0

E33

O~

t31Y

10 0

B13
C3?

-io"{--I 1-'----~461 O~[j--------------------------2-539
K21910
05 C15
07 0 1>11
04
9461 usn
--K21911
03
f) 11 - 04 0 010
07
- - 9461 OSD
K21920
05
Cl5
OH 0
01'1
04
')461 OSO _______________ _
-1<.3001004 --~32
01 U B3-'
03
94610S!"j
K30011
12 837
03 0 H14
11
9461 DSO
4103
~3()(jlt----11)H-32--hf-o
U3b
06----~-4611)~S-f)--------------,,-1=-10-=-3..,K30110
03 B32
07 0 H33
12
9461 OSO
--j(3{111:C------07---B33 - l2 0 A31
07 ---9461---l)S--O-----------------------------K30112
04 A37
01 0
A3Y
04
~4bl nSD
208~~
--K:30210
. 04 B33
01 () t~32
12
-9461 --OSIl --------- - - -------- -------------------K3U211
07 832
12 0 A~l
O~
~461 OSD
- - - - - ----------------j(303 l"o------- ()Z-----B33
0 -, 0
B32-----06----- --ij"i~-6-1-0S0-----K30311
05 832
06 0 A31
08
~461 OSO

~

--'(3041 0-----------01,---

01 - u----c4o--r2---9"4-l)1-1}s-JJ-------

~3~f-

09 B38
02 0 C2~
08
9461 D5D
--------05--B3-8- - 07-l1--ti30---1 r ------9-461---')S(i--------------------------------------------K30511
06 H38
07 0 C41
11
~461 DSD
--i(3052 0-- ----65--- ~3H---08 --IY--B ::fo--- fO----Y46"l--riso--------- --K30521
06 H3H
OH 0 C42
11
9461 OSO---------.--- -- --_._------------ --- - - K30522
16 C42
11 n 00H
03
~461 usa
K30610
04 C41
01 0 831
12
9461 DSO
------K30611--06 B37-- 12· () tl.3T--- Oil- -------- Y4-61---[)Srf-------------------------'------------

K30420

K30~)"lo

..

K30710

06

C41

07

n

B3b

-,r3071 1----04 - - t~3b---l1-n-~3-3

11
9461 OSO
06--9-461-CfST)
11
9461 DSO

K30712
03 R33
06 0 832
----'(30HI0
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MINNEAPOLIS, MINNESOTA

DOCUMENT NO.

TITLE

WL

R/W LOOIC CHASSIS ASSEMBLY
PRODUCT
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2

3

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WIRE LISTING

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