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8

CONTROL DATA

MULTIPLE DISK DRIVE
BM101-A/B
BM103-A/B

THEORY OF OPERATION
DIAGRAMS
MAINTENANCE AIDS
WIRE LISTS

CONTROL DATA
CORPORATION

CUSTOMER ENGINEERING MANUAL

REVISION RECORD
REVISION
01

DESCRIPTION
Preliminary Edition.
.:~.

(9 ~ 1-69)
A

Manual released.

(1-1-70)
B
(5 -15 -70)

Engineering Change Order PE21171 incorporating the

followin~:

FCO PEll090/ECO PEll090 affecting pages 4-21, 4-23, 9-5 thru 9-96.
FCO PEll099/ECO PEll099 affecting pages v, vi. vii, 5-26, 7-30, 7-31, 7 -42, 7 -42. I, 7 -43..
9~5

thru 9-96.

FCO PEll1l8A/ECO PEll1l8A affecting pages v, 4-30, 9-5 thru 9-96.
ECO PEl1l48A affecting pages 9 -5 thru 9 -96.
ECO PEll148B affecting pages 5-25, 5-26.
FCO PEll195/ECO PEl1195 affecting pages 5-18, 5-23, 5-42, 9-5 thru 9-96.
FCO PEll286/ECO PE1l286 affecting pages 5-17, 5-18, 5-23.
FCO PE1l290/ECO PE1l290B affecting pages 5-16, 5-17, 5-21, 5-24.
ECO PE1l332 affecting pages 5-17. 9-5 thru 9-96.
FCO PE1l426/FCO PE1l427/ECO PE21036 affecting pages 5-23, 5-37.
FCO PE1l446/ECO PE1l446 affecting pages 9-5 thru 9-96.
ECO PE1l451 affecting pages 9-5 thru 9-96.
ECO PE1l45lA affecting pages 9 -5 thru 9 -96.
FCO PE1l492/ECO PE1l446 affecting pages 5-15, 9-5 thru 9-96.
.FCO PE21475/FCO PE21476/ECO PE21047 affecting pages 5-23, 5-41, 9-5 thru 9-96.
FCO PE21103/ECO PE2ll03 affecting pages 5-19. 5-20, 5-23, 5 -36.
FCO PE21122/ECO PE21122 affecting pages 5-28.
ECO PE21168 affecting page 5-15.
ECO PE21269 affectineC

pal:le~

9-5 thru 9-96.

Editorial Changes affecting pages 5-2, 5-26.1, 5-26.2, 5-26.3, 5-26.4, 5-26.5.
Engineering Change Order PE21585 incorporating the following:

(9 -28 -70)

ECO PE21296 affecting pages vii, 9-50, thru 9-50.11.
ECO PE21362 affecting pages vii, 9-26.1 thru 9-26.21, 9-66, 9-67.
ECO PE21537 affecting pages 9-82. 9-85. 9-87. 9-88. 9-91. 9-92. 9-94.
Editorial Changes affecting pages 5-1, 5 -2. 9-50.12.

D

Engineering Change Order PE21295 incorporating the following:

(1-4-71)

ECO PE21253 affecting pages 9-26.1 thru 9-26.22. 9-50.1. 9-50.2.
FCO PE21367/ECOPE2J367 affecting pages 5-18, 5-23, 5-42.
ECO PE21504 affecting pages 5-19, 5-21, 5-23.
ECO PE21572 affecting page 5-41.
ECO PE21594 affecting pages 9-50.11.

Publication No.
41249000

Address comments concerning this
manual to:

© 1969. 1970. 1971

by Control Data Corporation
Printed in the United States of America

Control Data Corporation
Technical Publications Department
4201 North Lexington Avenue
St. Paul, Minnesota 55112
or use Comment Sheet in the back of
this manual.

REVISION RECORD (CONY'D)
DESCRIPTION

REVISION

FCO PE21647/ECO PE21647 affecting pages 5-17,5-20, 7-49, 9-26.1 thru 9-26.22.
FCC PE21803/ECO PE21647B affecting pages 5-17, 9-26. 1 thru 9-26.22.
ECO PE21665 affecting pages 9-82.
ECC PE21667 affecting pages 9-82 thru 9-95.
FCO PE21717 /ECO PE21717 affecting pages 5-26. 1, 9-82 thru 9-95.
Editorial changes affecting page 9-96.
E
(3-18-71)

Engineering Change Order PE24097 incorporating the followine:: Engineering Change Orders:
PE21421, PE21886, PE21933B affecting pages 4-23, 5-24.1, 5-24.2, 5-26.4 thru 5-26. 8
9-67, 9-96 thru 9-109.

F

(9-20-71)

Editorial Changes affecting pages v

vii

5-23

5-29

5-30

9-66

9-110.

Engineering Change Order PE24285

incorporating the following,
Engineering Change Orders; PE24130, PE24155D, PE24159. Field Change Orders; PE24028,
PE24155A, PE24156A, PE24157, affecting pages; v, vii, 5-20, 5-24, 5-24.1, 5-26.7 thru
5-26. 12, 9-110 thru 9-125.

G

(11-18-71)

Engineering Change Order PE24344 incorporating the followine:: Ene:ineering Change Orders;
PE21933B. Editorial changes. Affecting pages: vii, 4-7, 4-14. 1, 4-14.2, 4-15, 4-16,

PE21717A

4-16.1, 4-16.2, 4-17, 4-18, 4-19, 4-26, 5-5, 5-12, Comment Sheet.
H

Update manual to incorporate Engineering Change Orders PE24392

(3-13-72)

update affects pages 5-22, 5-25, 9-9, 9-14

J
(6-30-72)

Update manual to incorporate Engineering Change Order PE24213A,

•
PE24429. This

Comment Sheet.

This update affects pae:es vii
The following pages are added; 5-51 7-79 7-80 7-81 7-82
9-26.23 thru 9-26.49 and 9-50.12 thru 9-50.25 .

ix, 5-16, 5-17, 5-20, 5-22, 5-23.

.

Publication No.
41249000

PE24402

PREFACE
All available customer engineering installation, operation, and maintenance information for the CONTROL DATA BM101 and BM103 Multiple Disk Drive is in three
manuals:

41249000 A

Publication No. 41248900

General Description, Operation,
Installation and Checkout,
Maintenance

Publication No. 41249000

Theory of Operation, Diagrams,
Maintenance Aids, Wire List

Publication No. 41243700

Illustrated Parts List

iii

CONTENTS
4.

Acce ss Control

5-20

4-1

Head Selection and Fault
Detection

5 -21

First Seek

4-1

Head Gating and Read/Write

5 -22

Direct (Forward/ Reverse)Seek

4-10

Chassis Map

5 -23

Return to Zero Seek (RTZS)

4-12

Read/Write/ Erase

4-13

Signal Di stribution
MODS A04, B04 & below
MODS A05, B05
MODS ~06, B06 & above
Power Su~p y.
MOD A03, B03 & below
MODS A04, A05
MODS A06, & above
MODS B04 & above
Control Panel
Schematic Diagrams
Sector Preamp

THEORY OF OPERATION

Functions

Assemblies
Power Supply

4-14
4-14

AC / DC Di stribution

4-14

Power-On Sequence

4-16

Power-Off Sequence

4-18

Logic Chassis

4-20

Deck Assembly

4-20

Drive Motor Assembly

4-21

Spindle Assembly

4 -21

Hydraulic Pump

4-23

Carriage & Carriage
Mount

4-24

Transducers

4-29

Disk Cleaner Assembly

4-33

Hydraulic Actuator

4-34

Hydraulic Operations

4-36

5-24
5-24. 1
5-24.2
5 -25
5-26.1
5 -26.4
5-26.7
5-26.11
5 -27

Cylinder Preamp

5 -28

Detent Preamp

5 -29

8AFN Head Select Preamp

5-30

8AHN Head Selection

5 -31

8AJN Upper Difference
Counter

5-32

8AKN Addre ss Register

5 -33

9ALN Latency Counter

5-34

AANN Steering Unit Logic

5-35

DAPN Seek Error On
Cylinder and XDCR Amps

5 -36

I

Frame

4-48

Blower System

4-48

Filter Box

4-48

Disk Pack
5.

4-50

DIAGRAMS

Introduction

5 -1

Key to Logic Symbols

5 -14

I

8AQN / OAQN Solenoid Control
Control
5-37
8ARN Receiver

5 -38

BA SN RT ZS and Fault
Detection

5-39

8ATN Line Transmitter
BAUN Read Recovery

5-40
5-41

9A VN Sector Register

5-42

8A WN Lower Difference
Counter

5 -43

Input/Output Transmitters and
Receivers

5 -15

Addre ss Register and Control
Bus Steering

5 -16

9A YN Write Erase Circuits

5-44

Select and Reserve

5 -17

8AZN Terminator

5-45

Latency Overlap

5 -18

Difference Counter

5 -19

8F AN Analog Gate and
Amplifier

5-46

41249000

F

v

7.

8FBN Select and Reserve

5-47

Line Transmitter - LAA

7-24

AFEN Speed Detector and
Miscellaneous

Oscillator - MAA
Waveform Generator - MBA

7-27

5-48

8FFN Tester Card
BFGN Fault Status

5-49
5-50

Adjustable Waveform
Generator - MBC

9DMN Read/Write Test Card

5-51

Quantizing Detector - QAA

General

7-1

SPL Logic
Physical Description

7-1
7-1

Pin Assignment
Test Points

7-2
7-3
7-3
7-3
7-4

Use of Relative Level Indicators
AND Function
OR Function
Information Contained within
Logic Symbols
7-4
Discrete Component Circuits .7-4
Intebrid Circuits
Wired Functions

7-7
7-8

Quantizing Detector - QCA
Speed Detector - QDA
Or - QEA

7-30
7-33
7-33
7-35
7-37
7-39
7-39

Quantizing Detector - QFA
Quantizing Detector - QFB
Quantizing Detector - QFF
Line Receiver - RAA
Line Receiver - RBA
Switch Receiver - RDA
Switch Receiver - RCA
Line Receiver - RFA
Delay - UA- UBA
Delay Circuit - UCA

7-45
7-47
7-47
7-48
7-50

Delay Circuit - UCB

7-50

J

7-42
7-42.1
7-45

Standard /Non - Standard Logic
Level Indicator

7-9

Delay Circuit - UCC

7-50

Intebrid Circuit Descriptions

7-9

Delay
Delay
Delay
Delay

7-50
7-50
7-52
7-52

Discrete Component Circuit
Descriptions
Low Level Amplifier - FAB
Gated Intermediate Level
Amplifier - GJA

vi

7-30

Quantizing Detector - QBA

MAINTENANCE AIDS

7-29

7-9
7-10
7-12

High Level Amplifier - HAA
High Level Amplifier - HAB
High Level Amplifier - HJ A
Lamp Driver - IAA
Lamp Driver - rnA
Lamp Driver - ICA
Low Speed Driver - IDA
Write Driver - JAB

7-13
7-13
7-13
7-17
7-18
7-18
7-20
7-22

Erase Driver - JBB

7-24

Circuit - UCD
Circuit - UCE
- UDA
- UDB

Unidirectional Time Delay UEA
And - VAA
And - VAB
And/Or (Single Input) VAC 1 VJW

7-54
7-55
7-56
7-56

Power Driver - V JK
Power Driver - VJL
And - VJM
Or - VJN

7-59
7-60
7-61
7-62

And - VJP

7-63
41249000 J

Power Driver - VJR

7-64

Or - VJS

7-65

Or - VJT

7-65

And - VJU, VJV

7-66

And/Or - VJW

7-66

Flip-Flop - WBB

7-66

Toggle Flip-Flop - WBC

7-69

Pulse Shaper - XAA

7-70

Pulse Shaper - XAB

7-72

Pulse Shaper - XAC

7-72

Head and Disk Pack Replacement
Criteria

7-75

Head Replacement Criteria

7-75

Disk Pack Replacement Criteria

7-75

Disk Pack Runout Check

Logic Wire List
MODS 04 & below
MODS 05 thru 13
MODS 14 & above
Logic Chassis Harness Assy
MODS
MODS
MODS
MODS

03 & below
04, 05
06 thru 13
14 & above

MODS AOl, BOI
MODS A02, B02 & above

9-62

2X Final Assy

9-63

Control Panel
MODS A03, B03 & below
MODS A04, B04 & above

7-76

Filter Box Assy

Read/Write Tester Card

7-79

P owe r Supply As sy
MODS
MODS
MODS
MODS

WIRE LISTS
9-1

Logic Wire List

9-1

Non-Logic Lists

9-1

9-50.25
9-55

IX Final Assy

7-77

Description of Wire Lists

9-27
9-38
9-50
9-50.12

Deck Assy

Tester Card

9.

9-5
9-26.1
9-26.23

A03, B05 & below
A04, A05
A06 & above
B04 & above

Maintenance Panel Assy

9-65
9-66
9-68
9-69
9-82
9-96
9-110
9-125

FIGURES
4-1
4-2
4-3
4-4

4-4. 1

4-5

4-8

Input/Output Signal
Gating - 2X Cabinet

4-2

Select and Reserve
Sequence

4-3

Block Diagram - 2X
Cabinet

4-4

4-25

4-9

Head Loading Mechanism

4-27

4-10

Head/ Arm Assembly
Motion

4-29

4-11

Transducer

4-30

Power Supply - AC /DC
Distribution (Series Code
4-14. 1
05 And Below)

4-12

Detent Detection

4-31

4-13

Cylinder Detection

4-31

Power Supply - AC /nc
Distribution (Series Code
4-15
06 And Above)

4-14

Cylinder Position Detection 4-32
4-33
Index/Sector Detection

Power Supply - Sequencing
(Upper Deck Only) (Series
4- 16. 1
Code 05 And Below)

4-6

Power Supply - Sequencing
(Upper Deck Only) (Series
4-16.2
Code 06 And Above)
4-22
Deck Assembly

4-7

Spindle Assembly

4-5.1

Carriage / Carriage
Mount

41249000 J

4-23

4-15
4-16
4-17
4-18
4-19

Hydraulic Actuator Power Off

4-35

Hydraulic Actuator Hydraulic Home

4-38

Hydraulic Actuator Detent
Hydraulic Actuator Forward Fast

4-40
4-41
vii

4-20 Hydraulic Actuator Forward Intermediate

4-43

4-21 Hydraulic Actuator Forward Slow

4-44

4-22 Hydraulic Actuator Reverse Fast

4-45

4-23 Hydraulic Actuator Reverse Intermediate

4-46

4-24 Hydraulic Actuator Rever se Slow

4-47

4-25 Blower System

4-49

I

7-14 Lamp Driver - IBA, ICA

7 -19

7-15 Low Speed Driver - IDA

7 -21

7-16 Write Driver - JAB

7 -23

7-17 Erase Driver - JBB

7 -25

7 -18 Line Transmitter - LAA

7 -26

7 -19 Oscillator - MAA

7 -28

7-20 Waveform Generator - MBA 7-29
7 -21 Adjustable Waveform
Gene rator - MBC

7 -31

5-1

Power Onl First Seek Sequence 5-2

7-22 Quantizing Detector QBA

5-2

Power Onl First Seek Timing

5-3

7-23 Quantizing Detector -QCA

7-34

5-3

Deck or System Power Off
Sequence

7-24 Speed Detector - QDA

7 -36

5-4

7-25 On - QEA

7-38

5-4

Power Off Timing

5-5

System Power Sequence Lines 5-6

7-26 Quantizing Detector - QFA
7-27 Quantizing Detector - QFB

7-40

5-5

7-41

5-6

Direct Seek Sequence

5-7

7-28 Quantizing Detector - QFF

7-43

5-7

Direct Seek Timing

5-8

7-29

7 -44

5-8

Return to Zero Seek Sequence 5-9

5-9

Return to Zero Seek Timing

I

QAA~

7 -32

Line Receiver - RAA, RBA

5-10

7-30 Switch Receiver - RDA,
RCA

7 -46

5-10 Latency Overlap Timing

5 -11

7-31 Line Receiver - RFA

7 -48

5 -11 Typical Sector Format
Read/Write Timing

7-32 Delay - UA-, UBA

7 -49

5 -12

5 -12 Ground Scheme

5 -13

7 -33 Delay Circuit - UCA, UCB
DCC, UCD, UCE

7 -51

7-1

SPL Card

7-2

7-34 De lay - UDA, UDB

7 -53

7-2

AND Function

7 -3

7-3

OR Function

7-4

7-35 Unidirectional Time Delay 7-54
DEA

7-4

Truth Table

7 -5

7 -5

Discrete Component Circuit

7 -6

7 -6

IntebridCircuit

7 -7

7 -7

Wired Functions

7-8

7-8

Low Level Amplifier - FAB

7-11

7-9

Gated Intermediate Level
Amplifier. - GJ A

7 -12

7-36 And - VAA

7 -55

7 -37 And - VAB

7 -57

7-38 And/Or (Single Input) VAC, VJW

7 -58

7-39 Power Driver - VJK, VJS

7 -59

7-40 Power Driver - VJL

7 -60

7-41 And - VJM

7 -61

7-42 Or - VJN

7 -62

7-10 High Level Amplifier - HAA

7-14

7-11 High Level Amplifier - HAB
7-12 High Level Amplifier - HJA

7 -15
7 -16

7-43 And - VJP

7 -63

7-44 Power Drive - VJB

7-64

7 -13 Lamp Driver - IAA

7 -17

7-45 Or - VJT

7 -65

viii

41249000

B

7-46 And - VJU, VJV

7-67

7-51 Pulse Shaper - XAC

7-74

7-47
7-48
7-49
7-50

7-68
7-69
7-71
7-73

7-52 Disk Pack Runout Check
7-53 Logical Presentation of

7-77

Flip-Flop - WBB
Toggle Flip-Flop - WBC
Pulse Shaper - XAA
Pulse Shaper - XAB

Tester Card

7-78

7-54 Logical Presentation of
Read/Write Tester Card

7-55 Read Data Trace

7-80
7-82

TABLES

4-1

Input/Output Lines

41249000 J

4-5

ix

Information for these .sections is included in BMIOl
and BMI03 Multiple Disk Drive
Pub. No. 41248900

SECTION 1
GENERAL DESCRIPTION

SECTION 2
OPERATION

SECTION 3
INSTALLATION A.ND CHECKOUT

SECTION 4

THEORY OF OPERATION

THEORY OF OPERATION
Theory of operation for the MDD is divided into three parts.

The first part considers

the MDD in terms of the functions it performs and the signals exchanged with the controller.

The second part relates the major assemblies of the MDD to the previously

discussed functions.

The last part deals with the disk pack which is physically not a

part of the MDD, but figures functionally in all MDD operations.

FUNCTIONS
Overall capabilities of the MDD are best described by examining the functional blocks
of activity performed by a deck of the MDD.

The functions are as follows:

First Seek
Direct (Forward or Reverse) Seek
Return to Zero Seek (RTZS)
Read/Write / Erase
Each of these functions is further described by flow charts and timing diagrams in
Section 5 of this manual.
The above functions are performed by each deck of the MDD.

Normal operation is

such that a controller will generally be directing the functional activities of more than
one deck.

Figure 4-1 shows the method of selecting and gating input/ output data to a

particular deck.
gating.

Figure 4-2 details the sequence of events that establishes the link and

The signals that are then exchanged are described in Table 4-1 and are shown

relative to a point of origin on Figure 4-3.

FIRST SEEK
This function involves the activities that a deck must perform before it can effectively
respond to a read, a write, or a seek command from the controller.

This function

consists mainly of power supply relay sequencing and status checking by the deck logic.

41249000 A

4-1

As a result, no actual selection of the deck is required and very little MDD / controller
signal exchange occurs.

Successful progression of the function assumes that power

supply circuit breakers for the deck are on, power supply DC /OFF switch for the deck
is set to DC, power supply fuses are operational, related filter box panel UNIT POWER
circuit breaker is on, START indicators for deck are lighted, disk pack is installed on
spindle of deck, and the sector sensor is engaging the disk pack sector disk.
Initiation of the function occurs when the controller makes sequence power available to
the power supply for the deck.

Sequence power causes the power supply relay KOI

(KIOI for lower deck) to energize and the power supply performs a Power-On sequence

(refer to Power Supply under Assemblies in this section for a detailed description).

UPPER DECK
STEERING
LOG I,£.
UNIT SEl.
AND LOGIC

~~C.£..D~~
CONTROLLER

I/O

XMTRS

AND

RCVRS

f---T~

I

~

rt

I
I

I

I
I
UPPER DECK
LOGIC NO. COMPARE

I
f---- -~

REMAINING
UPPER
DECK
LOGIC

AND SELECT LOGIC

I

----

SIGNAL FLOW OF SELECT
SEQUENCE

I
I
I
L_-.

LOWER DECK
LOG I C NO. COMPARE 1 - - - AND SELECT LOGIC

-~

I
I

I

REMAINING
LOWER
DECK
LOGIC

I

'J..
LOWER DECK
STEERING
LOGIC

5C8I

Figure 4-1.

4-2

Input /Output Signal Gating - 2X Cabinet

41249000 A

~

,........
t\:)

~

CD

o
o
o
:P

b>

CONTROLLER
ISSUES UNIT SELAND LOGIC NO.
CODE FOR DESIRED
UNIT OR DEO

~OES

I
ISSI,Ln

LOGIC NO. AGREE
WITH lOGIC PLUG
1N LOWER DECK'
Yt:i

NO

ODES ISSUED
I. OG I C NO. AGREE
WITH LOGIC PLUG
IN UPPER DECK')

YES

UPPER DECK
SENDS UNIT
SELECTED TO
CONTROLL.ER

LOWER DECK
SENDS UNIT
SELECTED TO
CONTROLLER

GATE I/O
RECEIVERS
TO UPPER DECK

GATE I/O
t'(ECE I VERS TO
LOWER DECK

GATF UPPER
DECK TO I/O
TRANSMITTERS

G"T[ LOWER
DEC': TO I/O
TRANSMITTERS

-

~
I

W

Figure 4-2.

Select and Reserve Sequence

5C84

1/0

I/O

CABLf
A OM B

CABLES
A OR 8

r-

"Br

--r-·~B

I

PACK UNSAF~~

SAFETy
lOGIC

_

ONCYLINDER
SEEt<

ERROR

Sf ATUS

Sf NSE

UNIT READY

i,:;~T

~TIO'

~ .:• LINES

DE~::~:NT

--=-

LINE 7
LINE 0

SECTQA

i

I

"",,".1

UPPER
CYLINDER

18 LINE

AODR REG

I INDEX

II.. RK _ _ _ _ _ _ _ _ _ _ _ _. _ _

V

-.~------ ---+,.....---~-__irt+++~

ERROR

k

-

7

i

~CTQR M.'R-'t. _ _ _ _ _ _ _

~ ON SECTOII OR SEEK

LINE.

~'NE

DETENT
DETECTION

I

I

(I

UPPER.!

r.>r.' LINE 0

00

IN~~X~~YL,

- - - ; N O E X ISECTOR PULSES

: 5 LINES

~

!I

I
I

CYLINDER PULSES

COUNTER

.:!.

i

r
r

128

I,
I

IL,'.!!IN!!.E.JOl.--_+-_~--~rUPPiER"""-l UPPER
UP~ER
LOGIC PLUG

..,

: 4 LINES

SEllLOGIC
NO C

UPPER UNIT SEl

LINE 3
UNIT S£LECT

RELEASE

LINE

~ 18
~I:

L
°

l-or';";LO;;;W;<"ER""'-'f-!L",-OW,,-,Ec.::R....::Uc;.N:.c.IT....:cS=.;EL'+f--- ---~--­
SEL/LOGIC

NOCQIIIPIUIE

L
128

LOWER:
CYlINOER

LINES

AOOR REG

~tLiioE1-

~OWER

' - - - - - r - , L O G I C PluG

I

_~

. _________ SEC TOR liAR"

"""'" LINE 0

v

v
LOWEii""""'

~
INDEX, CYL.

(I

I

DETENT

DETECTION

DETENT

j

POSITION

LOWER

.--~

STATUS

SENSE

ON CYLINDER

SEE" ERROR _ _-+V-=l:.~>-_---'
UNIT READY

~

------ ---._._--

~

~~~,,!..9_
: ~ LINES

(OO~iNf4WRITE DATA

LOW(R

LOWER

HEAD
ADDM£SS

SAFTy

REGISTER

LOG

-

r---

,/

Ie

NOTE

"""LOWER R[FERS TO SPI .. Ol[ OR O[CK,
A IX CAIINET O()(S NOT USE" lOWfR
DECK

Figure 4-3.
4-4

Block Diagram - 2X Cabinet

41249000 A

TABLE 4-1.

INPUT/OUTPUT LINES

SIGNAL

FUNCTION

Bidirectional Lines

Information carried by the bidirectional lines is coupled

Address and Control

by six select (tag) signals.

The influencing tag signal

must be known before information on a bidirectional
line can be interpreted.
below under Input Lines.

The six tag signals are defined
The information coupled by

each tag signal is as follows:
Addressl

Control
bus

Read Cylinder Select,
Difference Select, or
Cylinder Select

Bit 0

1

Sector
Select

Head
Select

1

1

Control Select

w rite

Gate - A "1" input on

this line enables the write
drivers.

2

Bit 1

2

2

Read Gate - A "1" input on
this line enables the digital
read data line.

Bit 2

4

4

4

Seek Forward - A "1" input on
this line initiates forward
carriage movement.

Bit 3

8

8

8

Not Used

Bit 4

16

16

16

Erase Gate - A "1" input on
this line enables the erase
driver to pass current through
the head erase coil.

Bit 5

32

Not

Not

Used

Used

Seek Reverse - A "1" input on
this line initiates reverse
carriage movement.

41249000

A

4-5

I

TABLE 4-1.

INPUT /OUTPUT LINES (Cont'd)

SIGNAL
Address/
Control
bus

FUNCTION

Read Cylinder Select,
Difference Select, or
Cylinder Select

Bit 6

64

Sector
Select

Head
Select

Control Select

Not

Not

Return to Zero - A "1" input

Used

Used

on this line initiates carriage
movement to cylinder 00.

Bit 7

128

Not

Not

Used

Used

Not Used

Input Lines
Read Cylinder Select

A "1" input on this line enables the address and control
lines transmitter of the selected deck.

Information trans-

mitted to the control unit through these lines is the current cylinder address.
Difference Select

A "1" input on this line indicates that the addres sand
control lines contain the difference address from the
control unit.

This address is the difference between the

control unit's current cylinder request and the selected
dec k' s pres ent cylinder location.
Cylinder Select

A "1" input on this line indicates that the addres sand
control lines contain the control unit's current cylinder
request.

Sector Select

A "1" input on this line enables the address and control
lines to couple the sector information to the selected deck.

Head Select

A "1" input on this line indicates that the addres sand
control lines contain the head select information.

4-6

41249000

A

TABLE 4-1.

INPUT /OUTPUT LINES (Cont'd)
FUNCTION

SIGNAL
Control Select

A "1" input on this line indicates that the address and
control lines contain control information.

>: 26)
With the Forward Latch cleared and a T> 26 situation, the actuator enters into a fast
reverse access toward the rear stop (cushioned hydraulically).
times out, the RTZS FF clears and the T> 26 signal drops.

When the 300-ms delay

The clear output of the

RTZS FF sets the Forward Latch, Intermediate, and Slow FF's.

The hydraulic

actuator responds to this activity with a slow forward (2 ips) access.

As soon as the

leading edge of the first track pulse occurs, the Detent FF sets and the actuator removes pressure to the spring-loaded detent pawl.

Five ms after the detent transducer

indicates that the detent pawl has engaged the detent gear, the deck sends an On
Cylinder signal to the controller.

(If the period during which the pawl was disengaged

from the detent gear had exceeded 600 ms, a Seek Error signal would have replaced
the On Cylinder signal.) The deck is now ready to perform a Read, a Write, or a Seek
(Direct or RTZS) operation.

4-12

41249000 A

READ /WRIT E / ERASE
An On Cylinder signal indicates to the controller that the selected MDD deck has completed a seek operation and is awaiting further instruction.

If, however, the controller

initiated a seek operation in one deck and then in the interim selected another deck, the
first deck would make its status known via the On Sector interrupt signal.

In the latter

case, the controller would be required to precede a Read or a Write operation with the
selecting sequence (Figures 4-1 and 4-2).

The following paragraphs cover the sequence

of events involved in a Read or a Write operation.
A Write operation actually begins before the hydraulic actuator positions the heads to
the desired track; the controller Sector Select tag gates the address of the desired
sector into the Sector Address register and the Head Select tag gates the identifying
number of the head to be used into the Head Address register.

When the On Cylinder

signal occurs (received by the controller only if deck is selected), the compare logic
in the Latency Overlap section of the logic is enabled.

This logic compares the static

content of the Sector Address register with the cycling content of the sector counter
(accumulates sector transducer pulse count, recycling to zero once each revolution.
Content of counter exceeds, by one, the number of the last sector pulse to pass;
leading edge of sector pulse 3 increases counter content to four.).

When the contents

of the sector counter and the Sector Address register are equal, the deck sends an On
Sector interrupt signal.

If the controller has selected another deck meanwhile, this

deck will continue to send one On Sector pulse during each revolution of the disk pack
until such time as it is selected again.

In any case, the leading edge of the first Sector

Mark (available to controller whenever a deck is selected) following the On Sector
pulse causes the controller to respond with a Control Select tag that gates the Read
Gate signal (bit 1 of bidirectional lines) to the deck.

Read Gate disables the compare

logic and enables the read circuit logic to function with the previously selected head.
The selected head reads the record to the controller via the Read Data line.

(Refer to

Section 2 of this manual for detailed information relative to the read/write format. )
When the controller is satisfied that the address of the desired record is being read, it
drops the Read Gate and enables the Write Gate and Erase Gate (bits 0 and 4 of the bidirectional lines) with the Control Select tag.

This disables the read circuit and enables

the write circuit, and data from the controller is written via the Write Data line onto the
disk pack record.

The Erase Gate signal enables erase current to the erase coil during

the Write operation to ensure a clear writing surface.

41249000 A

4-13

A Read operation is performed in much the same manner as the Write operation.

The

difference is that the Write Gate and Erase Gate signals are never enabled (Read Gate
stays on throughout the entire record).

ASSEMBLIES

POWER SUPPLY
Each MDD cabinet has a self-contained power supply accessible via the rear door and
located behind the swingout logic chassis.

The power supply provides a fixed output

voltage of +40Y volts for use by the solenoids on the deck assemblies.

It also provides

adjustable output voltages of +40 vdc (to read/write logic), ±20 vdc (to logic), and +6
vdc (to logic).

Each voltage is duplicated within the power supply, so that the voltage

can be distributed separately to the upper deck and the lower deck or to row A and
row B of the logic chassis.
Basic on/ off power control and monitoring is provided at the front panel of the assembly.
The front panel is hinged so that access can be gained to adjust or perform maintenance.
The assembly is cooled by fans located on the top surface of the chassis.
AD/DC Distribution (Figure 4-4)
Input power is applied through the closed contacts of the MAIN POWER circuit breaker
(on filter box panel) to the primary of transformer TOL

The presence of the primary

input power at the power supply is indicated by the power supply MAIN BREAKER
indicator.
The input power is applied directly to the cooling fans in the power supply and the logic
chassis.

Input power will also be applied to the blower in the lower part of the cabinet.

but only when the power supply BLOWER circuit breaker is set to ON.

All other dis-

tribution of ac power is delayed until during the power-on sequence (described in a later
paragraph).

4-14

41249000 A

K04

t+:-

+20Y

I-'
~

,--+'1'

t+:-

eo

Q

~O~O

r=::-,

DC

~C/OFF

'I'
~

o
o
o

+ 20Y

0C

~~I------------------------~----------~---rSSSS;WO_O~4I

-

0B

~

1"1'1
~----+--+-I +-

TO BLOWER

0A

itA

TO UPPER DECK BRUSH MOTOR

L.-----,

~

GlC }

TO UPPER DECK

0B

DRIVE

MOTOR

0A
0A1:-

0B

I

fiLTER
BOX,

I

-----~----+--------------+- 0A

j

TO LO GI C CH ASS IS FAN S

0C

NEU T

MAIN
BREAKER

0A
0B

}

TO LOWER DECK
ORIVE

Dc/OFF

MOTOR

0C

K I 01

~____________~~_L~
+20Y-----i~oDC
K 104
+20Y----1~

IJJ"'V-I

0A

TO LOWER DECK BRUSH MOTOR

K05

~ -------l

-----1

r-------

BUCKING
XF M RAN D
FULL WAVE
BRIDGE

~~~--

f-----

RECTIFIER

~"~"~

BUCKING
XFMR AND
FULL WAVE

f-----

I

G~;~
-LC-TYPE

~---i f---

..-...

LOGIC

V

--+-------------------j

r--,

r-----~--___I RECTIFIER

TO LOWER DECK R/W LOGIC

+6V

TO ROW A LOGIC

+6V

TO ROW B LOGIC

+20Y TO OP PNLS AND PACK ON
AND SECTOR SWS

BOOSTING
f.-I

+40V

-------lK02f----KI02

TO I
TRANS FOR MER

::~LR W::~

+40V TO UPPER DECK R/W

K 105

f----------.j

B

E + 2 0 T TO LOGIC

XMTRS/RCVRS

K02

f-----

+20V TO ROW A LOGIC

KI02

----1 f-----

+20V TO ROW B LOGIC

r - - - - - - - -20T TO LOGIC XMTRS/RCVRS

I BOOST I NG

K02

XFMR AND~------1
'FULL WAVE
--~-- ----------4RECTIFIER
~

-+-----...,1 f-----

I

I

--_ __--§- 1 : ;
~

t+:-

FULL WAVE

I

BR I DG E
RECTIFIER

I-'

t+:-

TYPE

K06

FILTER

-20V TO ROW B LOGIC

f-----

+40Y

TO

+40Y

TO LOWER DECK SOLENOIDS

UPPER DECK SOLENOIDS

K 105

------!

'""'"

f-----

5elOI

t+:I

I-'
~

f-----

K05

-t+:-

-20V TO ROW A LOGIC

KI02

Figure 4-4.

Power Supply - AC / DC Distribution
Series Code 05 And Below

,.j::.

.....

+ 20Y
r--

I\.:l

~

*"coo

GlC }

~

~O~OOC

I

o

55'11 04 1

,10

TO UPPER DECK BRUSH MOTOR

GlC

DC/OFF
GlB
QlA

o

o

+ZOY

TO UPPER OECK
DRIVE MOTOR

TO BLOWER

IU.,B -iFiLTER
BOX

I

I

------~--~------_r

.,A

TO LOGIC CHASSIS FANS

j

"CNEUT-L-

[J

,I':

MAIN
BREAKER

L--_ _ _ _ _ _ _

::

GlA}

W

I- - - - - - - - - T

TO LOWER DECK
DRIVE MOTOR

DC/OFF
L.
KIO,I
..J'~DC~ _ _ _ _ _ _ _ _ _ _ _ _ _
+20Y-1 ~ (

T_
===--1 55 '11104 J

+20Y

fA

TO LOWER DECK BRUSH MOTOR

K05

"-------1 f--

+40V TO UPPER DECK RIW LOGIC

K 105

"---~-" -----1 f--

+40V TO LOWER DECK RIW LOGIC

K02

'"'-------1 f--

+6V

TO ROW A LOGIC

+6V

TO ROW B LOGIC

K 102

f--

r--.

L---

----1 f--

v------TOI
TRANSFORMER

BE

+20Y TO OP PNLS AND PACK ON
AND SECTOR SWS
+20T TO LOGIC XMTRS /RCVRS

K02

f--

L-~

L--..j BOOST I NG
XFMR AND
FULL WAVE
f - - - - - - - - - - - - - - I I RECTI FIER

1FULL
1---_ _---11

WAVE
BRIDGE
RECTIFIER

I

I
ILC - TYPE
r - - 1 FILTER

"

+20V TO ROW A LOGIC

KIOZ

f--

BE

+20V TO ROW B LOGIC

-20T TO LOGIC XMTRS/RCVRS

K02

f--

-lOY TO ROW A LOGIC

KI02

I

f--

K06

C - TYPE
FILTER

~

-20V TO ROW B LOGIC

K05

KI:~

+40Y TO UPPER DEI:K SOLENOIDS

Lv----~. f--

+40Y TO LOWER DECK SOLENOIDS

5CIOIA

*"
I

.....
CJl

Figure 4-4. 1.

Power Supply - AC IDC Distribution
Series Code 06 And Above

The dc power distribution begins with the application of main input power to the primary
of TOL

Voltages developed across the secondary windings are applied to five rectifier /

filter circuits.

Each of these circuits develops a separate dc voltage.

Through the use

of variable transformers, four of the five voltages are adjustable (+40Y solenoid power
is not adjustable).

The +20Y voltage is immediately available when T01 is energized.

This voltage is distributed to the operator panels and the pack on and sector in-place
switches.

The voltage is required to determine the status of these elements during a

power on sequence.

Distribution of the other dc voltages is controlled by circuit

breakers and/ or relay contacts.
Power-On Sequence
Power application to a deck is sequenced up by relays in the power supply (Figure 4-5).
Sequencing is required to prevent damage to read/write heads and/or disk packs.
A normal on line, power-on sequence begins when switch S501 on the operator panel is
pressed (actuating power supply panel START switch will also start the sequence).

The

progression of the sequence assumes that all power supply circuit breakers are on,
that all power supply fuses are operational, that the power supply DC / OFF switch is
set to DC, that a disk pack is installed, that the deck drawer is closed, and that
sequence voltage to relay K01 is available.
NOTE
Although steps 1 through 3 occur prior to actuating
S501, they should be considered a part of the power
on sequence.

I

1.

When filter box MAIN POWER circuit breaker was set to ON, +20Y voltage
became available, and K06 was energized, (Figure 4-4).

2.

When controller issued sequence voltage, K01 energized via pick line
(Figure 4-5).

The +20Y voltage was applied to solid-state switches SSWOl,

SSW02, and SSW03 (Figure 4-4).

This enabled the solid-state switches to

conduct their respective phase of ac power.

The upper deck drive motor and

time meter started.

4-16

41229000 G

*'"

1-£
~

~

c.o
o
o

PICK
FROM
CONTROLLER
OR PRECEDING
UNIT

o

o

{

HOLD

I~

~

KOI

K02

BLOWER

fj\

~

+ 20Y

+20

+6

- 20

OFF

~~CD~CD~ID~l~----'r-----'
T:t I
r------------,
~

PACK ON

I

START

9

I

KOI-

S50 I
0
~

SECTOR

IN STALLED

~

I
I

- - K05

I

IN PLACE I

IOFF

K04
~1~~I.1-9I
INSTALLED
0
I ~ 0---------_----; I

o

I

®

IN PLACE

L ___________

I KOI
-1

+20Y TO SSW04
(BRUSH MOTOR)

DC
SPEED

SPINDLE SPEED
STATUS FROM
LOGIC CHASSIS
(GRD = SPEED)

+20Y TO SSWOI THRU SSW03
(DR IVE MOTOR)
DRIVE

BRUSH MOTOR

MOTOR

NOTES:

CD
@

K05
AUXILIARY SWITCH CONTACTS
RELATED CI RCUIT BREAKER
(SHOWN IN OFF POSITION).
NOT

ON

-=

r -- -

PART OF POWER SUPPLY ASSEMBLY.

I IN PROGRESS
1

-------,
IN PROGRESS

~

I

H:::.

I

I
1-£

m

10

1-£

L

Figure 4-5.

BRUSH CYCLE

-=

I

I
I

STATUS TO LOGIC

I

_____ J

Power Supply - Sequencing (Upper Deck Only)
Series Code 05 And Below

BRUSH CYCLE

5C I 08

~

I
~

m
('V

FROM
{
CONTROLLER
OR PRECEDING
UNIT

. PICK -

l-

HOLD

~--

-=

K02

BLOWER

IT'

\:.,I

+20

-20

\:.,I

\:J.

+6

OFF

~~~~~Ko21
IT'
0
Ij'\
I DC

+ 20Y

\V

r-----------,

I
START

g.

o

PACK ON

I-

S501

I

~

I

SECTOR

I
I .

IN PLACE

I

INSTALLED

~

INSTALLED

T

KOI -

0

I

I

T1T

I

":"

I
I

K05

. 10FF

I.·~

I r----o-- (

®
IN PLACE I KOI
'- ___________ ...1

I

-

DC

SPEED

SPINDLE SPEED
STATUS FROM
LOG I C CHASSI S
(GRD = SPEED)

+20Y TO SSWOI THRU SSW03

(OR IVE MOTOR)

NOTES:

CD

®

K05
AUXILIARY SWITCH CONTACTS ON
RELATED CIRCUIT BREAKER
(SHOWN IN OFF POSITION).
NOT

PART OF POWER SUPPLY ASSEMBLY.

-=

r--

------:---,

I

I

IN PROGRESS

I I N PROGRESS

~

I

1

I

10
L __
~

STATUS TO LOGIC

I

BRUSH CYCLE

-=

BRUSH CYCLE

I

___ J

I5CI08A

~

('V

~

co

o
o
o

o

Figure 4-5. 1.

Power Supply - Sequencing (Upper Deck Only)
Series Code 06 And Above

3.

With circuit breakers on and DC /OFF switch set to DC, the closing contacts
of K02 caused the following:
a.

Distributed +6, +20, and -20, and -20 vdc to the A row of the logic chassis.

b.

Applied holding current to armature of relay KO 1.
NOTE
For units Series Code 05 and below use steps 4 thru
9, for units Series Code 06 and above use steps 10
thru 13.

4.

Press operator panel switch S501 (or actuate power supply START switch).

5.

The +20Y voltage energizes K03 (K05 does not energize because spindle speed
is zero).

6.

The +20Y voltage also energizes relay K04.
+20Y voltage to be applied to SSW04.
power and the brush motor starts.

Closing contacts of K04 cause

The solid-state switch conducts ac
Brush cycle switch transfers to the

in- progress position.
7.

When the logic chassis detection circuit determines that the spindle speed is
adequate, K05 energizes.
a.

The contacts of K05 cause the following:

The +40 voltage is distributed to the read/ write logic on the upper deck
(Figure 4-4).

b.

The +40Y voltage is distributed to the solenoids on the upper deck
(Figure 4-4).

c.

One of the grounds to K04 is removed, but K04 does not de- energize
since the brush cycle is still in progress.

8.

As the disk pack cleaning brushes return from sweeping the disk surfaces, the
brush cycle switch is mechanically transferred and de- energizes K04.

This

removes the enabling +20Y voltage to SSW04, and ac power to the brush motor
is dropped.
9.

Completion of the brush cycle allows the start of the First Seek (load heads)
function.

Upon completion of the First Seek operation the deck is ready to

respond to commands from the controller.

41249000 G

4-17

10. Press operator panel switch S50 1 (or actuate power supply START switch).
This will initiate operation of the brush cycle by enabling the +20Y voltage
to SSW04 thru the normally closed contacts of K05.
to the brush motor.

This allows ac power

Brush cycle switch transfers to the in-progress

position.
11. When the logic chassis detection circuit determines that the spindle is up to
speed, K05 energizes. The contacts of K05 cause the following:
a.

The +40 voltage is distributed to the Read/Write logic on upper deck
(Figure 4-4. 1).

b.

The +40Y voltage is distributed to the solenoids on the upper deck
(Figure 4-4. 1) thru K06.

c.

One of the grounds to SSW04 is removed but brush cycle remains in
progress due to brush cycle switch.

12.

As the disk pack cleaning brushes return from sweeping the disk surfaces,

the brush cycle switch is mechanically transfered and removes the ground
from SSW04.

The ac power to the brush motor is then dropped.

13. Completion of the brush cycle allows the start of the First Seek (load heads)
function.

Upon completion of the First Seek operation the deck is ready to

respond to commands from the controller.
Power- Off Sequence

A power- off sequence begins when the operator panel switch S501 is pressed.
The sequence is as follows:
1.

Press S501 (actuating power supply panel START switch will also initiate the
sequence) .
NOTE
For units Series Code 05 and below use step 2 (Figure 4-5)
For units Series Code 06 and above use step 3 (Figure 4-5. 1)

2.

Relays K03, K04, and K05 de-energize.

Contacts cause the following:

a.

K05 contacts disable +40 volts to read/write logic.

b.

K05 contacts disable +40Y voltage to hydraulic actuator solenoids and
head latch solenoid.

Read/write heads unload and the reverse biased

(hydraulically) carriage moves in reverse to retracted stop at 2 ips
(see Hydraulic Operations, Section 4 of this manual).
4-18

41249000 G

c.

K05 contacts also provide a path to ground for relay K04 in preparation
for next power- on sequence.

d.

The application of the +20, -20, and +6 voltages to logic chassis will
continue until the occurrence of one of the following: KO 1 drops because
sequence voltage was removed at controller, or K02 dr·ops because of
either the actuation of a power supply switch or breaker (DC / OFF,
+20, -20, +6, BLOWER) or removal of cabinet input power.

3.

Relay K05 de-energizes.

Contacts cause the following:

a.

+40 volts to Read/Write logic is disabled.

b.

+40Y voltage to hydraulic actuator solenoids and head latch solenoid
is disabled.

Read/Write heads unload and the reverse biased

(hydraulically) carriage moves in reverse to retracted stop at 2 ips
(see Hydraulic Operations, Section 4 of this manual).
c.

Provide a path to ground for SSW04 in preparation for the next poweron sequence.

d.

The application of the +20, -20, and +6 voltages to logic chassis will
continue until the occurence of one of the following: KO 1 drops because
sequence voltage was removed at controller, or K02 drops because of
either the actuation of a power supply switch or breaker (DC/OFF, +20,
-20, +6, BLOWER) or removal of cabinet input power.

41249000 G

4-19

LOGIC CHASSIS
The logic chassis assembly consists of a logic card section, a maintenance panel, and
an input/ output connector panel.

The assembly is accessible through the rear door

and is located at the top of the cabinet.
access to the power supply assembly.
of the assembly.

The assembly is mounted on hinges to allow
Three fans are mounted along the lower surface

These fans are energized whenever the filter box circuit breaker is

on, and they provide cooling air to the logic card section.

The back cover of the

entire assembly can be removed (four half-turn fasteners) to gain access to components
and wiring.
The logic card section contains the bulk of the SPL logic cards used in the cabinet
(four cards are located on each deck assembly).

The vertically mounted cards are

installed in two rows (A top row and B bottom row) at numerically identified locations.
Refer to Section 5 of this manual for a description of the logical functions performed
by the cards.

Section 9 contains a tabulation of the wiring connections in the chassis.

The maintenance panel contains a set of test point jacks, switches, and an indicator
for each deck in the cabinet.

These components function primarily to isolate the

occurrence of a fault on the related deck.

Specific information on each control or

indicator of this panel is provided in the Operation section for this equipment (see
Preface of this manual for publication number).
Connectors located on the input/output connector panel are involved only with signals
exchanged between a deck and the controller.
of these Signals.

Refer to Table 4-1 for a description

The Installation and Checkout section for this equipment covers

cabling and I/O connector pin assignments (see Preface of this manual for publication
number).

DECK ASSEMBLY
The deck assemblies (Figure 4-6) are responsible for the dynamic operations of an
MDD: driving the disk packs, and loading and positioning the read/write heads.

The

deck assembly consists of a deck plate on which are mounted a drive motor assembly,
a spindle assembly, a hydraulic pump, a carriage and carriage mount, three transducers, a disk cleaner assembly, and a hydraulic actuator.
4-20

41249000 A

The deck assembly mounts in the MDD cabinet on a drawer mechanism.

The drawer

may be extended out the front of the cabinet to load a disk pack, or extended out the
rear of the cabinet for maintenance purposes.
Drive Motor Assembly
The drive motor drives the spindle assembly and the hydraulic pump.
an induction type, 3/4 -hp unit.

The motor is

The motor is secured to a mounting plate which bolts

to the underside of the deck plate.

Power is transferred via a flat, smooth-surfaced

belt that threads over the pulleys of the spindle, hydraulic pump, and drive motor.
A spring-loaded idler pulley maintains a constant tension on the belt.
The temperature of the motor is monitored by a thermal protection switch.

To restore

operation after an over-temperature condition, the red, 1/ 4-inch button on the top end
of the motor must be manually reset (pressed).
Spindle As sembly
The spindle assembly is the physical interface between an MDD deck and a disk pack.
The conical surface of the spindle cone (Figure 4-7) mates directly with the coneshaped opening in the center of the disk pack.
Starting in the spindle cone and running through the center of the spindle assembly
is the vertically free -floating locks haft.

The upper end of the locks haft contains

internal threads that engage the external threads of a stud projecting from the disk
pack.

When the disk pack cannister cover handle is rotated clockwise, the spring-

loaded lockshaft is pulled upward and the disk pack is pulled down.

As a result, the

conical surfaces of the disk pack and the spindle cone are engaged by a force of
approximately 200 pounds.

A clutch mechanism protects the lockshaft from damage

that could occur fr01TI over tightening the disk pack.

When the disk pack is fully

engaged, a release mechanism in the canister handle frees the canister from the
disk pack.
A notched lock wheel secures to the bottom surface of the drive pulley.

The notches

of the wheel are engaged by the tip of the spindle lock pawl (Figure 4-6) when the
deck drawer is open.
a disk pack.
41249000

B

This locks the spindle, making it easier to install or remove

Opening the drawer of an operating deck will cause a loud ratcheting
4-21

I

DISK PACK
CANNISTER \

TRACK (CYLI NO.

CARRI~~~\CATOR\
MOUNT

G

DRIVE
MOTOR

/i

/

DRIVE
MOTOR
PULLEY
IDLER
PULLEY

PUMP
DRIVE
PULLEY

Figure 4-6.

5C80

Deck Assembly

4-22
41249000 A

(refer to Figure 2-2).

Closing the drawer will cancel the override.

The spindle drive

pulley is driven by a flat belt linking it to the drive motor pulley.
The Pack-On switch and ground spring are mounted at the lower end of the spindle
assembly.

The ground spring block is mounted so that it is always in contact with

the ground sleeve.

The Pack-On switch contacts transfer in response to the vertical

movement of the lockshaft.
are closed.

When the shaft is up (disk pack mounted), the contacts

When a pack is not installed, the shaft moves downward to deflect the

switch actuator and transfer the contacts.

DETAIL

LOwER

~~~~\
DRIVE
PULLfY

LOC"§HAFT

DETAIL

~[JfL·
L

~~ELP"
LOCKSHAFT
(FREE TO MOVE VERTICALLY)

SPINDLE LOCK FRICTION PLATE

RETAINING
WASHER ---':~=l~==J
RETAINING
.....- /
/'
RING
FRICTION

P

PLATE HUB/I
GROUND/
I
SLEEVE
I

~'
""

- - GROUND

SPRING

BLOCK

~~~~C~N

SWITCH
ACTUATOR

Figure 4-7.

5C99B

Spindle Assembly

Hydraulic Pump
The hydraulic pump is a positive-displacement type device capable of delivering 0.67
gpm at a nominal pressure of 200 psi.
41249000

E

4-23

The pump is located on the top of and at the rear of the deck assembly.

The pump is

seated on the pump drive assembly which functions to extend and couple the pump
shaft through the deck to the pump drive pulley.

A flat belt driven by the drive motor

turns the pump.
The input and output hydraulic connections at the pump both originate at the hydraulic
actuator.

The hydraulic fluid pump and all pressure control valves are located in the

hydraulic actuator.
A pressure sensing switch is installed on the pump output line.

The switch transfers

at a nominal output of 10 psi (approximately 50 rpm) and is used in conjunction with
an operator panel indicator (see Section 2).
Carriage and Carriage Mount
The carriage and carriage mount (Figure 4-8) combine to form the vehicle that supports
the read/write heads.

Movement of the carriage, within the carriage mount, is con-

trolled by the hydraulic actuator.
The carriage consists of an upper rail and a lower rail, separated by the receiver and
the coupler plate.

The rails contain bearing surfaces that interface with the various

bearings and rollers of the carriage mount.

Each rail has a rack gear that meshes

with a pinion gear on the detent gear shaft (mounted vertically in carriage mount).
The detent gear and the track position disk are mounted on the lower end of this same
shaft.

The ball tip of the hydraulic actuator drive rod is connected to the carriage by

the drive rod coupler.

When the hydraulic actuator extends or retracts the carriage,

the detent gear shaft (and detent gear and track position disk) rotates.
The cylinder transducer senses the passing of the slots and lands of the rotating
track position disk.

From the center of one slot to the center of an adjacent land is

recognized as a movement of one track.

The transducer output causes the difference

(decrement) counter content to decrease by one each time a track is crossed.

When

the logic determines that the next track to be crossed is the addressed track, it signals the detent solenoid to release the detent pawl.

The spring-loaded pawl is drawn

into the teeth of the detent gear and locks the carriage at the desired track.

The

detent transducer senses the pawl and gear engagement and signals the logic.

4 -24

41249000 A

A track indicator (top of detent gear shaft) provides a visual indication of the current
track location of the read/write heads.
A head loading mechanism mounts between the receiver and the coupler plate.

Oper-

ation of this mechanism and the heads loaded switches is covered in the following
paragraph.

Figure 4-8.

Carriage /Carriage Mount

Head Loading
The read/write heads must be loaded to the disk surfaces before exchanging data with
the controller.

The heads must be released from this position (unloaded) and driven

clear of the disk pack when power is removed to the deck or the disk pack velocity
falls below a predetermined rpm.

The carriage components involved in these opera-

tions are identified in Figure 4 - 9.

41249000 A

4-25

Head loading amounts to applying spring pressure to the back of the read/write head
so the aerodynamically shaped head face approaches the related disk surface.

When

the cushion of air that exists on the surface of the spinning disk is encountered, it
resists the further approach by the head.

Spring pressure is designed to just equal

the opposing cushion pressure (function of disk pack rpm) at the required height.
a result, the head flies.

As

However, if the spring pressure exceeds the cushion pressure

(as would happen if the disk pack lost enough speed), the head will stop flying and
contact the disk surface.

This could cause damage to the head as well as the disk

surface.
To prevent damage to the heads and/ or the disk pack during automatic operation,
loading occurs only after the disk pack is up to speed and the heads are over the disk
surfaces.

For the same reason, the heads unload automatically and are retracted if

the disk pack rpm drops out of tolerance.

During manual operations, heads should

never be loaded on a disk pack that is not rotating, nor should heads be loaded without
a disk pack being installed on the spindle.

(The Maintenance section for this equip-

ment provides instructions on how to disable the head loading mechanism.) Head

I

loading is a part of the First Seek function. As power to the deck is sequenced up,
the drive motor starts, a brush cycle (approximately 60 seconds) is initiated,
and the hydraulic pump begins operation. When the disk pack rpm reaches 2000,
the extend solenoid (and head latch magnet) energizes and the carriage moves from the
retracted position to the hydraulic home position.

Upon completion of the brush cycle

(brushes clear of disk pack), the hydraulic actuator forward solenoid energizes and the
carriage moves forward toward the spindle and the forward mechanical stop.

Head

loading occurs during this forward motion.
The cam follower (part of carriage) moves along the head loading cam (part of carriage
mount).

When the follower encounters the up-ramp of the cam, the linkage rod assem-

bly moves upward (Figure 4-9, part C).

This causes each of the ten torsion rods to

rotate which forces the 20 read/write heads toward the proper disk surface.

The

spring force of the torsion rod is opposed by the air layer on the disk surface and an
equilibrium is attained with the heads flying over the disks.
As the carriage nears the spindle, the head load pawl enters the notch in the linkage

and transfers the heads extended switch.

The head latch magnet holds the pawl in the

latched position until power (to magnet) is removed.

Forward carriage motion contin-

ues until the cam follower contacts the head load cam latch.
4-26

This contact frees the
41249000

G

A

C

B

MECHANISM

HEA OS UNLOADED

HEAD

5C83

Figure 4-9.
41249000 A

Head LoadIng
.
Mechanism

4-27

end of the cam and it rotates downward to transfer the heads loaded switches.

This

transfer signals the logic that loading is complete and causes the carriage to be
retracted and positioned to track 00.

The heads remain loaded and latched until power

is removed, the index (sector) transducer is displaced from sector disk of disk pack,
or disk pack rpm drops below tolerance.
Head unloading (Figure 4-9, part D), occurs when solenoid power is removed to the
head latch magnet.

The head load pawl pulls out of the linkage notch, the torsion

rods rotate to relieve the pressure to the back of the read/write heads, and the heads
unload or move away from their respective disk surfaces.

With solenoid power absent,

the reverse biased (hydraulically) actuator moves the carriage toward the retracted
mechanical stop.

As the carriage moves in reverse, the linkage rod assembly press-

ing down on the cam follower pivots the head loading cam so that the tip (of cam)
engages the head load cam latch.

This relatching occurs as the carriage moves from

hydraulic home to the retracted stop.
If the linkage malfunctions and fails to unload the heads, the upper roller assembly

(Figure 4-8) contacts the knock off pin (Figure 4-9, part D).

This contact forces the

knock off pin downward to forcibly rotate the head load pawl clear of the head latch
magnet pole face, the thereby unload the heads.

The knock off pin is contacted by

the roller somewhere between tracks - 7 and -12.
Head/Arm Assemblies
Twenty head/arm assemblies are mounted on the carriage of each deck.

A head/arm

assembly consists of a read/write and erase coil package (head assembly) mounted
at the end of a supporting arm structure.
The head assembly (Figure 4-10), which includes a cable and plug, is mounted on a
gimbal ring which in turn is mounted on a floating arm.

This method of mounting

allows the head assembly to move (independent of the arm) tangentially and radially
relative to a data track on the disk surface.

Such motion is required to compensate for

irregularities in the disk surface.
The arm structure consists of a floating arm secured to a. heavier fixed arm.
of the fixed arm opposite the head installs in the carriage receiver.

The end

The floating arm

is the mounting point for the head and is necessarily flexible so that it can respond to

4-28

41249000 A

the force applied (on load button) by the torsion rod/spring during head loading.

Each

tip of the Y -shaped torsion spring loads a head, moving one head up and one head down.
The freedom and mobility of the head are necessary elements to being able to function
with interchangeable disk packs.

During head loading the 10 torsion rods rotate in

unison to flex the 20 heads toward the air cushion of the spinning disk surfaces.

The

force applied by the torsion spring causes the heads to fly or float on the air cushion.
Vertical motion by a disk surface (due to warpage or imperfection) is countered by a
move in the opposite direction by the gimballed head and/or the floating arm.

As a

result, flight height remains nearly constant.

TORSION ROD
THIS FORCE
APPLIED WHEN TORSION
ROD ROTATES DURING
HEAD LDADING OPERATIONS

F~TI~~

t\/

ARM

,.

~A

."-~~BAL

/

GIMBAL SPRING
ALLOWS HEAD ASSY
. / MOTION ABOUT
./
THIS AXIS.

SPRING
ALLOWS HEAD ASSY
MOTION ABOUT
THIS AXIS.
'-,

DISK
ROTATION

\

~
Figure 4-10.

5C93

Head/Arm Assembly Motion

Transducers
Three transducers are used on each MDD deck: detent transducer, cylinder transducer, and index (sector) transducer.

41249000 A

A transducer is a potted assembly consisting

4-29

of a primary coil and two secondary coils (Figure 4-11).

The secondary and primary

coils are separated by a notched and movable metal plate.
ducer is excited by a 187-kHz oscillator.

The primary of the trans-

When a notch (air gap) is between the

secondary and primary windings, the output of the transducer secondary is maximum.
The secondary output is minimum when the metal plate is between the windings.

The

secondary outputs drive a preamplifier card.
The related preamplifier card plugs into the transducer.
processed in the logic chassis.

The preamplifier output is

The only adjustment required of this assembly amounts

to repositioning the transducer relative to the slotted metal plate.
Detent Transducer
The detent transducer senses the location of the slot in the detent flag.

When the

detent pawl engages the gear, the slot is nearer to the bottom secondary coil (Figure
4-12).

This causes the amplifier output to go negative.

filtering removes part of the 187-kHz signal.

The preamplifier card

The detection circuit converts the

negative signal to a "0".
If the detent pawl is disengaged from the gear, the flag slot moves nearer to the upper
coil.

This causes a positive amplifier output which is detected as a "1".

AIR GAP]

fi'IF----'~ OSC ILLAT-OR
('\J

,I'

( 187 KHZ, II .8V P- P)

pi

~

=-RI~,

\"'--

METAL PLATE

SECONDA:JJ: ~DARY

~SHIELO(COPPER)
5CI4A

Figure 4-11.

4-30

Transducer

41249000 B

TRANSDUCER

PREAMPLIFIER CARD

AMPL

LOGIC CHASSIS

DETEC-

FILTER

TOR

-v

DETENT
SIGNAL

SCIS

Figure 4-12.

Detent Detection

Cylinder Transducer
The cylinder transducer senses slots in the edge of the rotating track position disk.
The cylinder detection circuit (Figure 4-13) converts the analog output of the transducer to "l's" and "O's".
The slotted edge of the track position disk separates the primary of the transducer
from the secondaries.

As the disk rotates, the notches allow varying levels of

coupling between the primary and the secondaries.

Figure 4-14 shows rotational

positions of the track position disk and the resulting cylinder detection.

As the notch

passes over secondary A, maximum coupling of the primary is possible and the output
of secondary A is maximum.

Since secondary B is covered by a land, coupling to the

primary is minimum as is the output.

TRANSDUCER

~

LOGIC CHASS IS

SEC

A

>-

PRIMAR:~

PREAM Pl.1 FIER CARD

r

AMPL

FILTER

DETECTOR

CYLINDER

PULSES

-.-

:' SEC
~

B
SCIS

Figure 4-13.
41249000 A

Cylinder Detection
4- 31

o

TRACK POSITION
DISK

0

[

)]I1jl} \Jijl?
A
X:UC:R
SECS

};

A

B

A

B

B

•

DISK MOTION

LAND

NOTCH

TRANSDUCER

OUTPUT

-In. . ._____..Jn. . .______f"L

DETECTOR OUTPUT _ _ _

5C97

Figure 4-14.

Cylinder Position Detection

As the disk rotates, both secondaries become covered by a land.

Since the outputs

are equal, the transducer output is a null.
Further rotation of the disk uncovers secondary B allowing maximum coupling and
raising output B to the maximum.

Since secondary A is now covered by a land, output

A is a minimum.

Disk rotation continues until both secondaries are centered on a notch, but covered
by a land.

The outputs are again equal, so a null occurs in the output.

Each notch and each land nulls the transducer output.

The detection circuit generates

a pulse for each null in the transducer output.
Index (Sector) Transducer
This transducer senses notches in the edge of the sector disk (large disk at bottom of
each disk pack).

4-32

41249000 A

Each notch on the sector disk causes a differential input to the preamplifier card
amplifier (Figure 4-15).
each notch.

The detector generates a 55-J,lsec "1" pulse in response to

These pulses are further processed by the MDD logic to determine if

the disk pack speed is sufficient for continued operation.
All disk packs have two closely spaced notches called index.
the beginning of a revolution of the disk pack.

These notches indicate

Some disk packs have, in addition to

index, other notches equally spaced about the circumference of the sector disk.
These notches are related to data organization on the disk pack.
Disk Cleaner Assembly
The disk cleaner assembly sweeps the disk pack recording surfaces free of any
foreign materials.

The sweep cycle occurs just before the read/write heads are

loaded during the First Seek sequence.
The assembly consists of a motor, 10-comb-mounted brushes, a reset switch, motor
to comb linkage, and a mounting base.

The base mounts on the deck assembly and the

brushes are pivot mounted on the base.
motor, the linkage, and the switch.

Pivoting of the brushes is controlled by the

The motor is energized during the power on

sequence and starts a 60-second (approximately) cycle.

As the cycle proceeds, the

brushes sweep toward the spindle until the linkage causes a reversal in direction.
As the brushes return to the original position (clear of disk pack) the reset switch is
encountered and transfers.

This de-energized the Brush Motor relay and disables the

motor.
TRANSDUCER

PREAMPLIFIER CARD LOGIC CHASSIS

AMPL

DETEC-

TOR

INDEX /SECTOR
PULSES

sce8

Figure 4-15.
41249000 A

Index/Sector Detection
4-33

The brushes are mounted using a ball-slot detent mechanism.

If power is dropped

or lost during the brush cycle, the operator can override the detent and rotate the
brushes clear of the disk pack so that the disk pack can be removed from the spindle.
The brush cycle during the next Power-on sequence will be an incomplete cycle as
the brushes automatically reset themselves.

Subsequent cycles will be normal.

Hydraulic Actuator
The hydraulic actuator drives and locks the carriage mounted read/write heads to
anyone of 203 discrete positions or cylinders of data.

Activity of the hydraulic

actuator is regulated by five solenoid-controlled valves that direct the routing of
hydraulic fluid.

The solenoids are controlled from the MDD logic chassis.

Hydraulic

fluid at a pressure of approximately 200 psi is provided by the hydraulic pump.
The hydraulic actuator (Figure 4-16) consists of a piston and sump block in or on
which are mounted a valve block, two hydraulic fluid filters, an extend piston, a
drive piston, and five solenoid and valve combinations.
Valve Block
The valve block contains all valves and most of the related fluid passages of the unit.
The block mounts directly under the sump chamber of the piston and sump block.
Filters
The two fluid filters are located in the sump portion of the piston and sump block.
The primary filter is a large-particle screen in the pump suction outlet.

The second-

ary filter removes smaller particles from a bypass flow originating when the slow
solenoid is energized.
A third filter removes smaller particles and is located in the pump output pipe between

the pump and the hydraulic actuator.
Extend Piston
The extend piston is located in the rear cylinder of two concentrically bored cylinders
of the piston and sump block.

This piston is hydraulically positioned to either the

extend or the retracted position by the status of the extend solenoid.

4- 34

Whenever power

41249000 A

is applied to the deck, the extend solenoid is energized and the related valve is closed.
Hydraulic pressure on the larger rear face of the piston drives it forward to a positive
stop.

This is the extended position. and the piston remains in this position until

power to the deck is dropped. In the extended position the forward face of the extend
piston functions as a hydraulically cushioned stop for the drive piston and also establishes the hydraulic home position for the carriage.

When deck power is removed,

the extend solenoid de-energizes, the spring-loaded valve opens, and the piston moves
to the retracted position.

As a result, the effective operating chamber for the drive

piston is extended to the rear of the carriage and the carriage is retracted to a position where the .hea.ds are clear of the disk pack surfaces.

SUMP

REAR
CYL

CAP

SUMP

FWD DECELERATION
VALYE 3 PSI

FWD DECELERATION
CHECK VALVE

'------r.o /

5e71

Figure 4-16.

41249000 A

Hydraulic Actuator - Power Off

4- 35

Drive Piston
The drive piston operates in the smaller forward cylinder of the piston and sump
block.

This piston connects. via the ball tip. to the movable carriage (mounting

point of the read/write heads).

The drive piston is constantly biased in the reverse

direction by hydraulic pressure applied via the forward deceleration check valve and
the minimum pressure orifice.

Piston direction and rate of motion are controlled

by three solenoids and valves.
Solenoids and Valves
The hydraulic actuator uses five solenoid and valve combinations.

The function of

the extend solenoid and valve was discussed previously.
The detent solenoid and valve controls the routing of hydraulic pressure to the detent
actuator (not physically a part of the hydraulic actuator).

When hydraulic pressure

is available and the detent solenoid is de-energized, the pressure is applied to the
detent actuator to pivot the detent pawl out of the detent gear.

When the detent

solenoid is energized, the related valve opens to vent pressure to the sump. and the
detent pawl spring pulls the pawl into the gear.
Three solenoids and valves direct the routing of hydraulic fluid to the drive piston.
All solenoid activity is controlled by signals originating in the logic chassis.

The

solenoids are located in the sump chamber of the hydraulic actuator and the control
valves are located in the :valve block.
terminal at the rear of the actuator.
valve.

Electrical connections are via a solenoid
Each solenoid operates with at least one related

This valve is open when the solenoid is energized, and closed (spring-loaded)

when the solenoid is de-energized.

The forward/reverse. intermediate. and slow

solenoids each control an additional spring-loaded spool.

When the related solenoid

is de-energized. system pressure from the hydraulic pump overrides the spring
force and repositions the spool toward the spring.
Hydraulic Operations
The following paragraphs describe the configuration of the hydraulic actuator during
the various operational phases.

4-36

41249000 A

Power Off (Figure 4-16)
No power, electrical or hydraulic, is available to the deck during this phase.

As a

result, all spring-loaded valves or devices are positioned according to spring loading.
The extend and drive pistons are in the retracted position.

This positioning occurs

during removal of power to the extend solenoid during the preceding power shut down.
When the extend solenoid de-energizes, pressure to the rear of the extend solenoid
is vented to the sump.
is decreasing.

Pressure still exists in actuator, even though the pump rpm

The reverse biased drive piston under the influence of this pressure

moves in reverse, pushing the extend piston ahead of it, to the retracted position.
Hydraulic Home (Figure 4-17)
Hydraulic home is the physical location established when the extend piston moves
to the extend position.

The actuator moves to hydraulic home at the beginning of

each First Seek operation.

It is the starting point for the forward motion required

to load and latch the read/write heads.

The sequence of events for this phase is as

follows:
~OO

1.

Hydraulic pump delivers pressure increasing toward

psi.

2.

Increasing pressure and de-energized solenoids cause forward/reverse
and intermediate spools to move downward and slow spool to move to
right.

3.

De-energized extend solenoid vents pressure to sump.

Extend piston

stays in retracted position (Figure 4-16).
4.

When pump pressure reaches approximately 200 psi, detent actuator
pivots pawl out of detent gear and relief valves begin controlling
pressure.

5.

When disk pack exceeds required speed, power is applied to extend
solenoid.

Vent to sump is blocked, pressure moves extend piston

(and drive piston) to left, and heads move into disk pack to hydraulic
hom e position.

41249000 A

4-37

SEAL

CONNECTIN~
HOLES

~3

-EXTEND PISTON
SUMP
SUMP

1Ji2li~~~

REAR
CYL

CAP

DETENT GEAR

~.
~~~~

t

t
SUMP

FWD DECELERATION
VALYE 3 PSI

FWD DECELERATION
CHECK VALVE

~~·V
RELIEF
1O!i--.........=~~ VALVE

5en

Figure 4-17.

Hydraulic Actuator - Hydraulic Home

Detent (Figure 4-18)
The detent phase occurs at the end of each seek operation.

The operation consists

of removing pressure to the detent actuator so that the detent pawl spring pivots the
pawl to enga.ge the detent gear and lock the carriage to a track.

The sequence of

events for this phase is as follows:

4-38

41249000 A

1.

During a First Seek or a RTZS operation, the detent solenoid energizes
when the leading edge of the first track pulse is sensed as the carriage
moves forward from hydraulic home (after the heads have loaded during
First Seek).

During a forward Direct Seek operation, the detent solenoid

energizes when the leading edge of the first track pulse is sensed after
the decrement counter indicates less than 2 tracks to go to the desired
track.

The forward/reverse solenoid remains energized.

During a reverse Direct Seek operation, the detent solenoid energizes
when the leading edge of the first track pulse is sensed after the decrement counter indicates less than 2 tracks to go to the desired track.
This causes the forward/reverse solenoid to energize.

Changing the

direction of carriage motion at this point allows the detent pawl to
engage the gear in the same manner as for a forward seek.
2.

Energized detent solenoid vents pressure to sump.

Loss of pressure in

detent actuator causes spring to pivot detent pawl into detent gear.
3.

The 50 psi dump valve opens to vent system pressure to sump (via
forward/reverse solenoid valve).

This causes system pressure to

drop to 50 psi and thereby prevents excessive heating of hydraulic fluid.
4.

Slow solenoid remains energized.

Forward Operations
The length of the seek determines the forward operations to be used.

If the seek is

in excess of 26 tracks when the forward/reverse solenoid is energized, the read/write
heads move toward the center of the disk pack in the forward fast mode (26 ips).
This rate of access continues until the logic determines that there are less than 26
tracks to go to reach the desired track.

When this determination is made, the logic

energizes the intermediate solenoid which causes the access to continue in the forward
intermediate mode (7 ips).

When the heads are less than four tracks from the desired

track, the logic energizes the slow solenoid.

This reduces the access rate to 2 ips

(forward slow mode), which continues until the detent pawl engages the detent gear and
stops the heads at the desired track.

If the desired track is less than 26 tracks but

more than 3 tracks from the current location, the intermediate solenoid is energized
immediately.

In this case the seek would consist of a forward intermediate mode,

followed by a forward slow mode, and detent.
41249000 A

4-39

SEAL

CONNECTIN~
HOLES

~~

--EXTEND
SUMP

\l

SUMP

REAR
CYL

CAP

SUMP

FWD DECELERATION
VALYE 3 PSI

FWD DECELERATION
CHECK VALVE

Figure 4-18.

Hydraulic Actuator - Detent

For a seek of three tracks or less, both the slow and interm ediate solenoids would
energize immediately.

The seek would consist of a forward slow mode followed by

detent.
Forward motion is stopped by detenting, but there is a back-up method in the form of
a mechanical stop.

4-40

41249000 A

Forward Fast Mode (Figure 4-19): The sequence of events for this mode is as follows:
1.

With extend solenoid energized and detent solenoid de-energized, the
forward/reverse solenoid energizes.

2.

Open forward/reverse valve vents pressure to sump.

Resulting pressure

drop causes upward movement of spring-loaded forward / reverse spool.
NOTE
Pressures at left and right faces of drive piston are
equal. Drive piston moves to left because area of
face is greater

SEAL

CONNECTIN~
HOLES

~3

-EXTEND PISTON
SUMP
SUMP

~~~.~
EXTEND
REAR
CYL

CAP

SUMP

FWD DECELERATION
VALVE 3 PSI

FWD DECELERATION
CHECK VALVE

®©@

t.:;.>----n:::=I'J'(~!(~"'".j VALVE

DUMP VALVE

Figure 4-19.

41249000 A

Hydraulic Actuator - Forward Fast

4- 41

3.

Hydraulic fluid flows through hole in extend piston causing drive piston
to move left (forward) at 26 ips.

Forward Intermediate Mode (Figure 4-20): The sequence of events for this mode is
as follows:
1.

With extend solenoid energized and detent solenoid de-energized, forward/
reverse and intermediate solenoids energize.

2.

Open forward/reverse and intermediate valves vent pressure to sump.
Resulting pressure drop causes upward movement of spring-loaded
forward / reverse and intermediate spools.

3.

Hydraulic fluid flows past forward/ reverse spool and around interm ediate
spool.

It then branches into parallel paths through detenting velocity

orifice and slow spool, rejoining at and passing the intermediate spool.
From here it passes through hole in extend piston causing the drive
piston to move left at 7 ips.
Forward Slow Mode (Figure 4-21): The sequence of events for this mode is as
follows:
1.

With extend solenoid energized and detent solenoid de-energized, forward/
reverse, intermediate, and slow solenoids energize.

2.

Open forward/ reverse, intermediate, and slow valves vent pressure to
sump.

Resulting pressure drop causes upward movement of spring-

loaded forward/reverse and intermediate spools and slow spool moves
to left.
3.

Hydraulic fluid flows past forward / reverse spool and around interm ediate
spool.

It then flows through detenting velocity orifice, past intermediate

spool and out forward face of extend piston to rear of drive piston.
4.

Drive piston moves left at 2 ips.

Reverse Operations
As with forward operations, the length of the seek determines the mode(s) required
to complete the seek.

4-42

41249000 A

SEAL

CONNECTIN~
HOLES

~>

SU.-p-EXTEND

PISTr-;0~ " ~'C': " "':'~" ~. ,.;T1~
......

..."",
....""'. ..

SUMP

~]
~

@

DETENT GEAR

~

-1

l!~"",:..
......sr..:;;""""":=1l<"-:.J:.

SUMP

FWD DECELERATION
VALVE 3 PSI

FWD DECELERATION
CHECK VALVE

~ioLoi:;W"':iqfjoJ'V

5C75

Figure 4-20.

Hydraulic Actuator - Forward Intermediate

Reverse motion is stopped by switching to forward motion and then detenting or by the
drive piston encountering the hydraulic cushion on the front face of the extend piston.
Reverse Fast Mode (Figure 4-22): The sequence of events for this mode is as follows:
1.

With extend solenoid energized and detent solenoid de-energized,
forward/reverse solenoid de-energizes.

2.

Closed forward/ reverse and intermediate valves cause line pressure
to move related spools downward.

41249000 A

4-43

3.

Hydraulic fluid at rear face (right end) of drive piston flows past intermediate spool and returns to sump at lower end of forward/reverse
spool.

4.

Hydraulic fluid flows through minimum pressure orifice to left face of
drive piston and piston moves right at 26 ips.

Reverse Intermediate Mode (Figure 4-23): The sequence of events for this mode is
as follows:

1.

With extend solenoid energized and detent solenoid de-energized,
forward/ reverse solenoid de-energizes and intermediate solenoid
energizes.

SUMP

REAR
CYL

""

CAP

SUMP

.".

.,:......., ...

FWD DECELERATION
VALYE 3 PSI

FWD DECELERATION
CHECK VALVE

V

~~-----no=rno

RELIEF

11(!\----1.t:="I;U,.."d VALVE

SUMP

loou.,..-......---.'\=:::::J~~~~~~bE,..~·r.~···~a~~_~~,flj!··:i,::1Il·~rt·.•~.~~.~~-~',~.:]~:(i:~.-~.. ~.~·;:,'!iA.•~.~~..!i.~~4~';3·;·~~·~·~·~.

~~'i...~~-<

@,J.;zj'

DUMP VALVE
5C74

Figure 4-21.
4-44

Hydraulic Actuator - Forward Slow
41249000 A

2.

Closed forward/ reverse valve causes line pressure to move related
spool downward.

3.

Intermediate spool rises.

Hydraulic fluid at rear face of drive piston flows past intermediate spool
and branches into two parallel paths past slow spool and through detenting velocity orifice.

The paths rejoin to pass around the intermediate

spool and vent to sump at forward/reverse spool.
4.

Hydraulic fluid flows through minimum pressure orifice to left face
of drive piston and piston moves right at 7 ips.

SEAL

CONNECTIN~
HOLES

~~
"

-EXTEND PISTON

~.P /

~~.,~.=.'::"",~"'""""""

SUMP

EXTEND
REAR
CYL

CAP

;'

DETENT GEAR

Cd

SUMP

1~,~

•

MIN
-PRESS
ORIFICE

t

SUMP

1

SUMP

FWD DECELERATION
VALVE 3 PSI

FWD DECELERATION
CHECK VALVE

~~V

®©@
50 PSI

'\
DUMP VALVE
5C79

Figure 4-22.

41249000 A

Hydraulic Actuator - Reverse Fast

4- 45

1

SUMP

FWD DECELERATION
VALYE 3 PSI

RELIEF
~__~~~&dVALYE

5C78

Figure 4-23.

Hydraulic Actuator - Reverse Intermediate

Reverse Slow Mode (Figure 4-24): The sequence of events for this mode is as
follows:
1.

With extend solenoid energized and detent solenoid de-energized, forward/
reverse solenoid de-energizes and slow and intermediate solenoids
energize.

2.

Closed forward/reverse valve causes line pressure to move related
spool downward.

Open intermediate valve causes related spool to rise.

Open slow valve causes slow spool to move to left.

4-46

41249000 A

3.

Hydraulic fluid at rear face of drive piston flows past intermediate spool,
through detenting velocity orifice, over intermediate spool, and vents to
sump past forward/ reverse spool.

4.

Hydraulic fluid flows through minimum pressure orifice to ] eft face of
drive piston and piston moves right at 2 ips.

SUMP

1

SUMP

FWD DECELERATION
VALVE 3 PSI

FWD DECELERATION
CHECK VALVE

~~/

5e77

Figure 4-24.

41249000 A

Hydraulic Actuator - Reverse Slow

4-47

FRAME
The frame assembly consists generally of the structural members, drawer mechanisms,
and panels of the cabinet.

Two additional subassemblies are, by virtue of their loca-

tion, considered a part of the frame: blower system and filter box.
Blower System
The blower system (Figure 4-25) provides positive pressure at the center of a disk
pack mounted on the spindle of a deck assembly.

The presence of this elevated

pressure at the center of the disk surfaces results in an outward dispersion of air
over each disk surface.

This air flow greatly reduces possible contamination and

dam age of the disks and the read / write heads.
The system consists of a motor driven impeller that forces air through an absolute
filter (glass and asbestos) and related ducts upward to the spindles present in the
cabinet.

Much of the ducting is extendable to allow the deck drawers to be extended

out the front and rear of the cabinet.

Power to the blower drive motor is controlled

by the power supply BLOWER circuit breaker.
Filter Box
The filter box controls power to the cabinet in which it is located.

The box is located

in the bottom of the cabinet and is accessible by opening the cabinet rear door.

It

contains a circuit breaker (UNIT POWER) that controls application of main input
power to the cabinet power supply.

The power supply MAIN POWER indicator

monitors the status of the circuit breaker.

Frequency filters for the input power

lines are mounted inside the box.

4-48

41249000 A

~_ _.-l

~

~\~\~
___ EXTENDABLE

'

I J 1.... ....

DUCT

~.....-:::~!Y"

AIR BAFFLE

DISTRIBUTION
CHAMBER

~

BLOWER
IMPELLER

ABSOLUTE
FILTER
BLOWER ~
DRIVE MOTOR

5CI09

F"19ure 4-25

Blower System

41249000 A
4-49

DISK PACK
The disk pack is the recording medium for the MDD.

The disk pack consists of

eleven 14-inch, magnetic oxide coated disks center-mounted on a hub.

The recording

surface of each disk is coated with a layer (0.0002 inch) of magnetic iron oxide and
related binders and adhesives.
The 203 recording tracks are located in a 2-inch band near the outer edge of the
disk.

Track 202 has a diameter of approximately 9 inches, while the diameter of

track 00 is about 13 inches.

The tracks are spaced 0.010 inch apart.

The top and bottom disk surfaces are covered by protective non-recording disks.
The bottom protective disk is called the sector disk.
that are sensed by the index transducer.

This disk contains notches

The pulse outputs of the transducer are

used to determine disk pack rpm and to detect organizational segments of the disk
pack.
The lower hub of the disk pack contains a replaceable filter.
particles from the air supplied by the blower.

This filter removes

Keeping positive air pressure at

the center of the disks reduces the possibility of dust caused damage.
The disk pack has a two-piece container assembly.
simply by grasping and rotating the center hub.
,).

The bottom cover can be removed

The top cover is designed so that it

can be re-inoved only by installing the disk pack on the deck spindle assembly.

The

disk pack can be removed from the spindle only by using the top cover (see Section 2).
This design protects the disk pack from physical damage and greatly reduces the
possibility of contamination of the disk pack recording surfaces.

4-50

41249000 A

SECTION 5

DIA.GRAMS

DIAGRAMS
INTRODUCTION
This section contains diagrams that logically describe the MDD in terms of the
functions which the unit performs.

Figure 5 -1 through 5 -11 are flow charts# simpli-

fied circuits, and timing diagrams that describe the First Seek function. the Power
Off sequence, the Direct Seek (forward and reverse) function, the Return to Zero
function, and the Read/Write operations.

Figure 5-12 shows the cabinet ground

scheme.
The logic diagrams for the unit are provided on pages 5-14 through 5-23.

The MDD

signal distribution drawing is located on page 5-24. and the unit power supply schematic is found on pages 5 -25 through 5 -26. 3.

Schematic diagrams for the transducer

preamplifier cards and the SPL cards are found at the end of the section.

41249000

C

5 -1

V1
I

N

NO

~

t--I

N

~

\0

o
o
o

()

NOTES:

&.

DECK 0 DENOTES fiRST DE CK CctiNECTED TO CctiTROLl.£R
V I A POWER SEQ.lENCE LINES.
5C~71

.&

TH IS CONO I T I ctI MA INTAJNED BY MTR
OR SPEEO OR RTZS SIGNALS.

orr

OR HOS UNLD

Figure 5-1.

Power On/First Seek Sequence

SEQUENCE RELAY
K01/ K 101
DC POWER RELAY
K02/K102
SPINDLE DRIVE
MOTOR
BRUSH MOTOR

___---JF

60 SEC (APPROX)

4

L

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

I
SPINDL_E SPtED
RElAY KO,)/KIO'j
BRUSH CYCLE
SWITCH S301
FORWARD FF
HYD ACTLiATOR
E X TD~ 0 SOLE NO I D
INTERMED lATE
AND SLOW FF'S
I

FORWARD CARRIAGE HOT ION
HEADS LOADED

IP_S_~26

__________
2 __

HYDRAUI IC
HOME

IPS

-1'-___----'~2

I

+

I
~

________________~______________~F300 MS

[(I":S FF

I
CYlINOtR
PLd

(~RACKI

~L_ _ _ _ _ __ _
,PACK 00

-~~lrfill----f4-

S[~S

r-

----------~
RE '/[RSF,' A~­

R I AG>: He T IOf\j

!Ps-L

________________

~____________~F26 IPS1~_________
HYDRAULIC
HOME

Figure 5-2.
41249000 A

Power On/First Seek Timing
5-3

c.n
I

t+:-

NO

DECK POWER OFF

SYSITM POv.£R OFF

NO

NOITS:

& AL TIiOUGH

PCM:R IS REMOIlEO TO DECK. DECELERATING RPM OF"
SPINDLE IS AOEIlJ"TE TO OPERATE HYDRAULIC PUMP (VIA
DRIIIE BELT)"T A LEVEL SUF"F"lCIENT TO RETURN CARRI"GE
TO REAR STOP AND HOlD IT TIiERE.

t+:-

.&

1-6
t\j

DECK 0 DENOTES fiRST DECK C()jIECTED TO C()jTROLLER VIA
POWER SEIlJENCE LIlES.

t+:-

5C59

eo
o
o
o

:J>

Figure 5-3.

Deck or System Power Off Sequence

START SWITCH

S5 W01- SSW03
(RELAY K03/ KI03
- SER IES CODE 05
AND BELOW)
SP INDLE SPEED
RELAY KOs/KI05

HEAD LATCH

HYD ACTUATOR
SDLENOI DS

HEADS LOADED
SWITCH

REVERSE CARRIAGE
MOTION
NOTE:

(2) HOLDS
CARRIAGE ENCOUNTERS REVERSE POSITIVE STOP. RESIDUAL HYDRAULIC PRESSURE
CARRIAGE IN THIS POSITION. DETENT PAWL SPRING OVERRIDES FADING
PRESSURE TO PULL PAWL INTO DETENT GEAR.

c

5C60A

Figure 5-4. Power-Off Timing

41249000 G

5-5

P202 J202
"B" CABLES

SEQUENCE
PCJIIo£R
SWITCH

U

U

ON

I

OFF

t

I
I

ON

I
I
I

OFF
DC PCJIIo£R
RELAY

-

+20Y

V

V

V

W

W

W

-

t

U

LOCAL

T

=}0

K01

+---1 l-

I B

BI
I

I

-v---

I ~I

I

I

Q

-=

A5S501

507

K01

CD

REMOTE

"\.0

~02

+20Y

IX CABINET

501

I

I

~O5
'c
C
I----<
I

-...--<

-

X

X

X

z

z

z

Y

Y

Y

~

.

KlOl

Kl02

~

P202 J2n?
2X CABINET

-r20Y

t

--

U

U

U

'----

V

V

V

W

W

W

Q)

501
LOCAL

ORE MOTE

\.
K02
..........j

K01
507

K01
+20Y - - ' ....

TYPICAL
CONTROLLER

-=

A5S501

BI
I B
I ~I
I
I
I
I
I
I

~

~O5
C
C
I-UPPER
_D~C'i.

___

- -

LOWER
DECK

--------- -------

KlOl
K102

KlOl

H r---

,--

X

X

X

r - - f--

Z

Z

Z I---

Y f--

Y

Y

A6S501

5107
I

~

I

I

B

~

B:

~I

I

I

I

I
I

I

C

P202

KI05

I--

C

J20r)2~____________________________~~~~~~

2X CABINETC)

+20Y

-

..

-

f

U

U

V

V

V

W

W

W

501
LOCAL -"
\.

REMOTE
0

K02

---I ; t - - -.....- - - - - I
507
KOI

NOTES:

CD

A5S501 AND A6S501 UPPER AND LOWER DECK
OPERATOR PANEL START SWITCHES RESPECTIVELY.
ALL OTHER COMPONENTS IN CABINET POWER
SUPPLY,

2

K02 AND KI02 ARE DC POWER RELAYS

3

K05 AND K 105 ARE SPEED RELAYS

o

+20Y

----t f-

I B
B:
I 0----0 I

_

~C~

~

LOWER
DECK

_ _

_

I

I

I

I

_~_~05

.
UPPER

PINS X AND Z ON LAST DECK (OF LAST
CABINET) MAY BE USED TO HOLO CONTROLLER
PCJIIo£R ON UNTI L ALL DECKS HAVE POWERED DOWN

Figure 5-5.
5- 6

K01

A5S501

_

_

~C ~ I----<

_ _

_

_ _

...

_ _ _

_ _ _

_ _

_-;

. - . 1..

5C61

System Power Sequence Lines
41249000 A

~

I--'

t\J
~

co
o
o
o
J>

NCTr:

.&

UN!1 5fLfCT ACCOMPANIED BY TRANSMISSION

or

LOGlr

NUMBfR [ODE rOR DESIRED DECK.
bGb

.,.1

01
I
-J

Figure 5-6.

Direct Seek Sequence

REVERSE 0 I RECT SEEK FROM TRACK 60 TO 10, SELECT HEAD 01 AND SECTOR S

READ CYL I NDER
SELECT TAG

~~----t

DIFFERENCE
SELECT TAG

__

CYLINDER
SELECT TAG

~

~~n~

____________________

__~~n.~____________

NOTES:

t

SECTOR SELECT
TAG
HEAD SELECT
TAG

__~____~~n~___________
~~__~~~__~n~_______
t

CONTROL SELECT
TAG

CD

BIT 0 (1 )

CD

BIT



NO

NOTE :

&

tlNIT SELECT 4C.,ANIED BY TRANSMISSIDN OF

~DGIC

NUMBER CODE FOR DESIREO DECK,

CJl
I

CO

Figure 5-8.

Return to Zero Seek Sequence

BIT 6 OF TAG
CONTROL LINES

-1l~

____________________________-

I
CONTROL SELECT
TAG
RTZS FF

~~------------------------------JIE--- 300 MS ----~~L__________________
I

DETENT FF

~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

I
CLR DECREMENT
COUNTER
REVERSE CARRIAGE
FORWARD FF

I

----.J

~26 IPs----~~~I______________~----------I
L HYDRAULIC _ - - - - - - - - - - - - - - - ~~______________H_O_~__~
I

CYLINDER (TRACK)
PULSES
INTERMEDIATE
FF
SLOW FF

TRACK

nL----_ _
I 00

-Inn~Y' P_nnn
U

LJ U

I'-------~

~

------------~----------

I

IL-.-_ _ _ _

---I

I

FORWARD CARRI AGE MOTI ON
DETENT PAWL IN

___'______________~F~-----

2 IPS-----~~~_ _ _ _ ___

I

~~------------------------~I

I

I

ON CYLINDER

5 MS

~

~I
6G9

Figure 5-9.

5-10

Return to Zero Seek Timing

41249000 A

LATENCY OVERLAP-READ SECTOR 5
SECTOR SEGMENT
AT TRANSDUCER

10

~~______________________________________________________

INDEX PULSE-I346

SECTOR PULSES
1320 AND 1348

CONTENT OF SECTOR
COUNTER (RANK II)

o

1

2

3

4

5

6

7

8

9

10

11

ON CYLINDER

ON SECTOR OR
SEEK ERROR

COMPARE FF-I368

READ GATE
5C68
Figure 5-10.

41249000

A

Latency Overlap Timing

5-11

~n~~

INDEX OR SECTOR
MARK

~~-------------

0

INTERNAL HEAD
SELECT

~ FlO IlSEC
I

I
I

;;-E
A

I

I

J

ON CYLINDER

HEAD SELECT
TAG

________~nL

.J

READ GATE

F35 IlSEC (MAX)

0

I

W

I

READ GATE

R

I
I
I

T
E

~~

--I

GATE

~

25 IlSEC
(60 BITS) I

F2.5 jJ.SEC
I

I.L..L_ _ __

I

ERASE GATE

SECTOR FORMAT

"I"

"0"

J

1.-100

1+15,

~200

~25

-25)
NSEC

I.-

"0"

"0"

~400 ~

50

~

NSEC

NSEC

READ DATA TIMING
(AT I/O CONNECTOR)

"1"

HIlt

~100 ~ 200 ~
J20
NSEC

NSEC

± 1%

~400

NSEC

± 1%

"0"

--I

WRITE·DATA TIMING
(AT I/O CONNECTOR)

NOTES:

CD

o
o

~
o

TOLERANCE GAP 1 - 120 BITS - ACCOMODATES PHYSICAL READ/WRITE TO ERASE GAP
DISTANCE AND AllOWS HEAD SWITCHING AND READ AMPLIFIER STABILIZATION TH£.
SYNC PATTERN 1 - 112 BITS - INDICATES BEGINNING OF ADDRESS AREA. CONTROllER
MUST INITIATE SYNC BYTE (OR BIT) SEARCH MIDWAY THROUGH THIS PATTERN (REQJIRED
TO ENSUR[ THAT HEAD IS READING A KNOWN PATTERN EVEN UNDER WORST-CASE CONDITIONS
OF HEAD SKEW, RPM, AND INDEX TOLERANCES DUE TO DISK PACK INTERCHANGE).
ADDRESS - 36 BITS (TYPICAL) - TW£lVE-BIT UPPER ADDRESS, 12-BIT lOWER ADDRESS,
AND 12-B IT CHECKWORO.
HEAD GAP - 120 BITS - ACCOMMODATES PHYSICAL READ/WRITE TO ERASE GAP DISTANCE.

S

SYNC PATTERN 2 -

6

DATA FIE lD - 3864 B ITS PLUS 12 BIT CHECKWORD.

72 BITS -

INDICATES BEGINNING OF DATA FIELD.

7

POST AMBLE - 1 BIT -A PAD TO ENSURE THAT lAST BIT OF DATA IS NOT DESTROYED
DR DISTORTED.
TOLERANCE GAP 2 - 127 BITS - COMPENSATES FOR WORST-CASE CONDITIONS OF SPINDLE
SPEED AND OSC I LLA TOR TOLERANCES.

G) HEAD

SELECT TAG LINE SHOWN OCCURRING AT LATEST ACCEPTABLE TH£ RELATII.1:: TO
INDEX OR SECTOR MARK: NOT TO BE CONSIDERED A TYPICAL RELATIONSHIP.
5C70

Figure 5-11. Typical Sector Format Read/ Write Timing

5-12

41249000 G

POWER SUPPLY

LOGIC CHASSIS

DC
GROUND

TB 203

r--.- - - .,
1- .- ---'

r l

r

-I

L. -.J
TB02

I
I

I

I

I

1- ~~--.

I
I

Faoi'

1- ___I

r

CONN MTG
BI---

/'

Y'

SYMBOLS

EXAM~LES

*It INPUT ON PIN 41
Itlt OUTPUT ON PIN 41
** OUTPUT OF TERM EXITS CARD
OF CHANNEL I
OF CHANNEL I
9 OF ROW A ON PIN 6 SIGNAL
CONNECTOR J200
CONNECTOR J20 I
~~~E~S CARD 17 OF ROw A ON
*I-

@

A25-10

) >-

A21-24

KIOO

A50-14

A50ll,71

>--r:!i02 -0

KIOO

AZ6;2I I &J~!'5

_ I o:.:--A

-+)

nolt'..

,~

!15

TPC:

KI02
'/

... ,

"c:~

,..

@

A25-14
)i

>-

IJ202-£

KI02
1350

~;50

21

_

~

I

A26;55

I A5~117

A50~
56

A25-11

I~'

.1: .. "

@

>-

'" I,

AiU

-+>--A26-37

,.

A27-1
)>-

1

KI06
KI06

T

51

T022
~~:

21

50

1030~

A26-40

~02-HH

ON SECTOR OR SEEK
ERROR (LOWER)

~

@

An-IO
)>-

A2&;38{ AJ(~

AU-3' 26

TPI
I"

"21-41

51 _
,

IJ202-F

T'H
'I

&3~i5

A28;44 {

1137---+~

A30~
51

A28-42

~>AZl

III

KIOI
KI08

A26 -41

1137

-+)

51

~

'>'

., - •. ,"

)>-

1"...201-40

)>-

J

I I

A~~-21

I 35

(~-45
j

LOWER)
TP£

KilO

IJ200-4'

A29 , .

)>-

KII2

@
KII2

~~'5 KII4
@
- .. , .

)>-

KII4

l~@
I~®
IJ

zoo -

IJ202-JJ

A2'-21

IJ200-44

A27-22

)>--

1~

,.r-:.:.a, •

IJ~
IJ200-45
~

';' .v I."

52

IJ200-49

l~

u~-~

1220,1221

):>-,

~

,24

A2~-:!:

)>-

I I

AZ,- 22

)r---< ';' --

1225,1221

~>-

1225,1227

~

I"

IJ200-25

1.27-2'

HIO';"
IJZoo-aa

-+)

1346

IJ~
(
IJ200-27

, 1 IJIOI~M

INDEX

noo

IJ200-S1

1600
TP£

)>--

1513~~

HEAD SELECT

I513

TI'll

A28-26
~,

16,,,,-o

)>--

AZI;IIS"

~v"

;

T ~ •• A.-":

~

ON CYL

1.27-51

~I

1523
1525

A21-57

B)>--

IJ201-21

CONT SElECT

IJ200-1'

SECTOR SELECT

IJ;;;J

a

1.27-41

) >--

5,6
7,8

1330
1330

.1.27-42

)>-

1224
®M501
TPF

)>--

a

IJ200-50

A29-n

IJ201-50

)>--

==e3

XJZOO-II'

All-50

AU-U~'
~,>-~---+

A2I-52

A21-)4

TP'

.L

<;> /

A

)~

1224

~~M501

=:§J )>--

~

A:~\, 141 ;;;

III

1223
1223
UNIT SELECT

SEL

u~-~ 1227,1228

IJ:OI-.O

TPG

)>--

J

K203

81T I

R[AD

GUE
81T 2

RELEASE

SEEK
FWD

-

81T 6

64

CD

BIT 1

128

CD

IGATE
SEEK
REV

RETURN
000

CD

~

NOT USED.

~ PARTIAL INPUT SIGNAL SHOWN. SEE SHEET 7 fOR
COMPLETE GATING INFORMATION.
@ AOOITIONAL OUTPUTS SHOWN ON SHEET 3.
@ TO ENABLE DAISY CHAINING WITH 821 FILE.

3,4

B

A27-Z1

1221,1228

AI'-II
A!

U200 - 11

41249000

T

Au-alBaa

1346

~~---+--)>--

IJ200-72

CD

~

TPII

TPF

IJ2

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2N4258, 50211500

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28

&
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25

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93314010

~----------------------------------------------------------------~)21

1 ,. •

ALL

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ALL RESISTOR VALUES IN OHMS
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ALL CAPACITOR VALUES tlO'Y.
ALL DIODES SILlCON,92115021
ALL INTEGRATED PACKAGES SHOWN IN THE
SCHEMATIC HAVE A DECOUPLING CAPACITOR
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ALL C8 •• CAPACITORS ARE ASSOCIATED WITH
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TRANSISTOR, SILICON, PNP, 2N3640, 50210400.
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6

UNLESS OTHERWISE SPECIFIEO'
ALL RESISTOR TOLERANCES :!:5%.
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7.

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CR99A

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I'

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COMPONENT ASSY 50182502

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41249000 A

SCHEMATIC DIAGRAM
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_______________ ,

12

NOTES'

) 24

I.

USLESS OTHER'tVISE SPECIFIED:
A1..L RESISTOR TOLERANCES 1:. 5'"
ALL RES;STO" VALUES IN OHMS
ALL RESISTO':;;S RATED 1/4'11.
CAP~CITO~

ALL

&. TjU~SISTOR.

::

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ALL DI')::~S. SILIC"". 92115021
ALL TRANSISTO~S. SI:"ICO"'. NPN. 2N3;4S. 502i0300

+20V

)38

SILICON. PNP, 2N3640.

~02104CO.

ALL INTEGRATED PACI(AGES SHeW'1 I~ T\.IE S::!-!EMATn!
HAVE A CECCU':LlN~ CAPACITOR C:::'.:.::CTEj Tl PI~
8(+oVCC)AN) P''4 16 (G:::O) ALL C8 __ CA;:.1CIT~1S
A:;:: ASS'JCIATE WITH T~E r~TE':i:t.:. rEJ F':':K.!3E5.

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1.2K

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SECTION 6

MAINTENANCE
Information for this section is included in BM101 and
BM103 Multiple Disk Drive
Pub. No. 41248900

SECTION 7

.MAINTENANCE AIDS

MAINTENANCE AIDS

GENERAL
Section 7 contains information on logic circuits, the criteria used in determining the
further usability of read/write heads and disk packs, and the tester card used in the
Maintenance section.

SPL LOGIC
The logic used in this device is generally termed SPL (Silicon Peripheral Logic).
consists of two styles of circuits: discrete component and Intebrid.

It

Discrete com-

ponent circuits contain individually identifiable resistors, capacitors, transistors,
etc.

An Intebrid circuit is a chip containing an integrated circuit( s).

PHYSICAL DESCRIPTION
All components of the SPL cards are mounted on one side of a printed circuit board
(Figure 7 -1) which is 6 inches wide and 4-3/4 inches high.
The cards are pluggable and are restricted in vertical and horizontal movement by
card guide spacers when inserted into the panel connectors.

A card puller

(PN 84146900) which grips the upper and lower edges of the card is used for removing
the cards.

No special tools are required to insert a card.

Numerical deSignators (1 through 99) are etched on the non-component side of the
board to identify each transistor.

A 4-character alphanumeric designator is etched

on the non-component side of the board to identify the card type.
(alphanumeric) also appears on this side.

A matrix code

Non-amplifying components such as Intebrid

chips, resistors, capacitors, diodes, etc., are not marked.

41249000 A

7-1

G) MATRIX

CODE
(ETCHED)

TEST POINTS

2

o
o
o ~ '-

c:\

B

-I

VCIRCUIT
(CHIP)

I

E

COMPONENT SID E

o

I

I I

DISCRETE
COMPONENTS

I

-+- -t-:

fj\ INTEBRIO

;:::::::::r

o

3

END

NON-COMPONENT SIDE

NOTE:
INTEBRID CIRCUIT LOCATED AT 2B
(VIA MATRIX CODE)

Figure 7-1.

tiC 115

SPL Card

Pin Assignments
The module connector consists of a 37 -pin male blade connector mounted along the
4-3/4 inch board dimension on the component side of the board.
Connector pins are numbered from the top starting with pin 1 and continuing through
pin 50 on the bottom.

Thirteen pin positions are omitted.

These are 3, 7, 1 L

15, 19,

23, 27, 3 L 35, 39, 43, 47, and 49.
Six pins of the 37 -pin connector are reserved as follows:

7-2

Pin 2

Ground

Pin 4

-6v

Pin 6

-20v

Pin 46

+20v

Pin 48

+6v

Pin 50

Ground
41249000 A

Test Points
Test points are located near the edge of the module opposite the connector and in other
strategic places on the component side of the board.
betically starting with A on the top, outer edge.

Test points are assigned alpha-

In most cases, test points A and Z

are available for ground reference.

USE OF RELATIVE LEVEL INDICATORS
The relative level indicator is a small circle located at the origin or termination of a
signal line, and tangent to a logic symbol.

The presence or absence of this indicator

tells the conditions that are necessary to satisfy the function of the logic symbol.

The

presence of the circle indicates a 0 logic level on that line is needed to satisfy the
function.

The absence of the circle represents a logical 1 needed to satisfy the function.

AND FUNCTION
The relative level indicator used with an AND logic function may be interpreted in this
way: Only under the stated input conditions will the stated output condition occur.
Under all other input conditions, the stated output will not occur.

For example,

Figure 7 - 2 indicates that only when A and Bare 0 logic level (indicated by the circle
on their respective inputs) will the output of C be a logical 0 (indicated by the circle
on the output line).

Under all other input conditions, output C will be a logical 1.

ILZ.

Figure 7 - 2.

41249000 A

AND Function

7-3

OR FUNCTION
The relative level indicator used with an OR logic function may be considered as
follows: If one or the other, or both of the stated inputs are present, then the stated
output will occur.

Only when both of the stated inputs are not present will the stated

output be changed.

For example, Figure 7-3 indicates that if either A is a logical 0

(represented by the circle on its input) or B is a logical 1 (represented by no circle on
its input), or both A is a logical 0 and B is a logical 1, then output C will be a logical O.
Only when A is not a logical 0 and B is not a logical 1, will C not be a logical O.
A

_e___1.....

'R

F---

C
I L2 7

Figure 7 -3.

OR Function

A complete truth table for use with relative level indicators is given in Figure 7 -4.

INFORMATION CONTAINED WITHIN LOGIC SYMBOLS
Discrete Component Circuits
Figure 7 - 5 shows a schematic (as shown on card schematic diagram) and the logical
representation (as shown on logic diagrams) for the same discrete component circuit.
Four lines of information are contained within the logic symbol.

The top line is the

function identifier and de signates the broad logic function of that particular symbol.
In this case, PA represents a high level amplifier, the logic function performed by the
circuit.

The third line, also an alphabetic code, designates the circuit type being used

(HAB).

The circuit type is a subdivision of the function identifier (a specific high level

amplifier).

By using the circuit type designator, detailed information on that parti-

cular circuit can be derived in the following paragraphs (see Discrete Component
Circuit Descriptions).

7-4

41249000 A

:~ I
A

:~

A

F-

G

I
:=d AF-G
:=d~A

A

B

F

G

0

0

I

0

0

I

0

I

I

0

0

I

I

I

0

I

A

B

F

G

0

0

0

I

0

I

0

I

I

0

I

0

I

I

0

I

A

B

F

G

0

0

0

I

0

I

I

0

I

0

0

I

I

I

0

I

A

B

F

G

0

0

0

I

0

I

0

I

I

0

0

I

I

I

I

0

F

r

:=1 I
:=1 F-G
A

F

A

I

: _ _-:._ _
A.....

: _ _:

F-

__A.....

r

G

:=1 F:=1
ClR

ClR

G

I

:=d F-r
'R
:=d I
'R

G

:~ F:~ I
'R

F

tlR

3U5

Figure 7-4.
41249000 A

F

Tr'Jth Table

7-5

G

+20V

. . . - - - - - - - OUT

041

22

PA
A705
HAB
39
A22

R22A
R22D

-20V

41
40

~

-=
R22B

+20V
040

R22G
OUT

sello

+20V

Figure 7-5.

Discrete Component Circuit

The second line within the symbol is used to differentiate that particular symbol from
similar symbols that appear in the logic diagram.

It is called the logic term and con-

sists of a one-letter prefix and an assigned identification number (in this case, A 705).

The numbers on the input lines to the symbol indicate which transistor is driven by that
input line.

For example, the upper input has a number 22 on its line, showing that it

drives transistor number 22 (ie., Q22 on the card schematic diagram).
The output lines also have numbers associated with them.
which transistor directly feeds the output linc.

These numbers indicate

For example, the lower output line has

a number 40 above it, indicating that the output from transistor number 40 (Q40 on the

7-6

41249000 A

card schematic diagram) drives the lower output line.

For other circuits additional

transistor numbers may appear below the logic symbol.

These numbers refer to

internal transistors that are not directly connected to any input or output line, but are
a part of the circuit.
Intebrid Circuits
Figure 7 -6 shows the schematic version (as shown on card schematic diagram) and the
logical representation (as shown on logic diagrams) for the same Intebrid circuit.

The

first and second lines of information inside both blocks are the same, and have the
same meaning as for the discrete component circuit.
Line three identifies the Intebrid circuit type (D24), and on the logic symbol additionally identifies the section (B) of the circuit chip.

(Refer to the Key to Logic Symbols

sheet of the logic diagrams for detailed coverage of Intebrid circuit types being used
and the number of sections in each chip. )
The fourth information line in the block is for location information.

On the schematic

version, lC identifies the matrix block (Figure 7 -1) in which the chip is located and B
identifies the section of the chip.

The fourth line of the logic identifies the card

matrix location and it also identifies the logic chassis row (A) and the mating connector
in the row (13).

LOGIC

SCHEMATIC
CHIP
REFERENCE
/DESIGNATOR
ZIC -B
10 .....- ....

----4

FUNCTION
INPUT PIN~

I

10

OUTPUT PINS

CI RCUIT
TYPE

LOCATION (ON CARD)
AND SECTION

IDENTIFIER
LOGIC
TERM

t.:

OUTPUT PINS
(SHOWN AS CABLING)

CIRCUIT TYPE
AND SECTION

L CATION (IN LOGIC
CHASSIS AND ON CARD)

aCliz

Figure 7-6.

41249000 A

Intebrid Circuit

7- 7

Pin information for the schematic and logic versions are similar with two exceptions.
The logic version does not show unused chip pins, whereas the schematic version shows
all unused pins connected to ground.

Secondly, the schematic version shows a separate

origin for each chip output pin, while the logic version may show a single origin and
identify each pin as the line branches to its destination.

This scheme is termed

cabling and conserves space and preserves appearance.

WIRED FUNCTIONS
The logical representation for wired functions is shown in Figure 7 -7.

These functions

are used where circuits have the capability of being combined as an AND function by
having the outputs connected.

This is simply a physical connection and no electrical

or electronic components are involved.

However, the logical interpretation of the

wired function is consistent with the AND truth table in Figure 7-4.
used to depict logic flow into the gate.

Arrowheads are

The gate output has no arrowhead.

,
I

I

,

A
~

I

!SCI II

Figure 7 -7.

7-8

Wired Functions

41249000 A

STANDARD/NON-STANDARD LOGIC LEVEL INDICATOR
The input to a logic function at a voltage other than the standard logic level is represented by a slash across the non-standard level line.

Absence of the slash (or absence

of an A, see below) indicates a standard logic level on that line.

Figure 7-5 illus-

trates the use of this symbol.
When the input signal to a logic function is an analog signal. the input line will have
an A across it.

INTEBRID CIRCUIT DESCRIPTIONS
Detailed functional descriptions and schematic diagrams for Intebrid circuits are
provided in CDC Pub. No. 60201000.

DISCRETE COMPONENT CIRCUIT DESCRIPTIONS
Figures 7-8 through 7-51 are the schematic diagrams for the discrete component
circuits used in this device.

A verbal description supports each circuit diagram.

The order of presentation is in accordance with the 3 -letter alphabetical circuit type
designator.

41249000 A

7-9

Low Level Amplifier - FAB
The FAB circuit (Figure 7 -8) is a low level amplifier that am'plifies the analog read
signal from the head.

Input B is a gate input.

When input B is +20v, diodes CRNA, CRNB, CRNC, CRNU, CRNE and Cl{NF are
forward biased.

The voltage between CRNC and CRNE and between CRND and CHN F

is clamped at approximately +2. Ov.

With all diodes forward biased, the read signal

can pass to the amplifier.
When input B is ground, diodes CRNG and CRNH clamp the voltage at +0. 6v.
reverse biases the input diodes.

This

No read signal can enter.

The preamplifier is a three stage amplifier using an emitter follower output stage for
low output impedance.

The integrated preamplifier has discrete component ac and dc

feedback.
AC feedback is provided by CNE and RNH in the top half and CNF and RN.J in the lower
half of the circuit.

The signal is brought back to the emitters of the input stage to

increase input impedance.
DC feedback is provided by RNG, RNE and CNC (to ground) in the upper' half and HNK,
RNF and CND (to ground) in the lower half of the circuit.

This feedback helps to

stabilize the output.
Capacitors CNG, CNH and CNJ, and CNK filter' noise ft'om the +20v and -20v power'
supplies, respectively.

The electrolytic capacitors filter low frequency noise.

The'

paper capacitors filter high frequency noise.
Open loop gain in the amplifier is approximately 180.

Closed loop gain in the amplifier

is approximately 30.

7-10

41249000 A

+20V

8

OV

A ORC

1
n
~i

Q

D OR E

- I 20MV

CNG
15".F

+

+20V

~

RN H
6.81 K

CNC
lOOOPF

RNE

CNH
O.Ol".F

RNG
10K

CNE
lOOOPF

10K

ACRNA CRNC

CRNE

C NA
1000PF

- 20 V

CRN8 CRND

C RNF

r--.....- - - t

CNI

RNJ

1000 PF

6.IIK
RNF
10K

CNF
1000PF
RNK
10K

E

CND

.:::c lOOOPF

RNM
1.2 K

CNoI
O.O.".F

+

CNK
15".F

NOTEI VOLTAGE

AND COMPONENT VALUES

ARE

-20V
FOR REFERENCE ONLY.
5 c 31

Figure 7 -8.
41249000 1\

Low Level Amplifier - FAB
7 - 11

Gated Intermediate Level Amplifier - GJA
The GJA circuit (Figure 7-9) is an analog gate that is controlled by input B.
input B is +20v, both transistors are on.

All analog signals pass through the circuit.

Capacitors CNA and CNB ensure that only analog signals are passed.
noise spikes from the gating signal.

When

CNC filters

Dc power for the transistors is supplied by the

circuit in the next stage.
When input B is +0. 2v, both transistors are off.

A

• ~ I :~~AI
C

::

No signals pass through the circuit.

+20V

B

OV

If

~120MV

AORC

*

,
•

~120

E OR D

•
A

0

CNA
1500PF

I

-

)
RNA

C NC
1000 PF

ON

1.96K

D

E

RNa
1.96K

OP

C
O~--I~----~----------~
NOTEr

VOLTAGE AND

COMPONENT VALUES

ARE FOR REFERENCE

ONLY.

ICII

Figure 7 - 9.

7 -12

Gated Intermediate Level Amplifier - GJA

41249000 A

MV

High Level Amplifier - HAA
The HAA circuit (Figure 7 -10) is gated by an analog gate circuit (GJA) and provides
the load and biasing for that circuit.
The preamplifier, ac feedback and dc feedback are identical to the F AB circuit.
Capacitor CND is added to the output of the second stage to decouple high frequency
noise.
High Level Amplifier - HAB
Input to the HAB circuit (Figure 7 -11) is a balanced square wave.

Output is also a

balanced square wave that follows the input.
When input A is positive, B is at Ov.
QQ falls to near ground.

Transistor QN is on and QP is off.

Transistor QQ is off.

With QP off, QR turns on.

Output C rises to approximately +0. 7v.

Output D falls to ground.

When input B is positive, A is at ground.
and QR is off.

The base of

Output C is at ground.

Transistor QN is off, QP is on, QQ is on

Output B rises to +0. 7v.

High Level Amplifier - HJA
The HJA circuit (Figure 7-12) increases the input signal power to transmit over a
coaxial cable.

The input is a differential signal of approximately 3. 6v peak to peak.

The input signal across A and B is divided between resistors RNA and RNB.
sistors QN and QP are forward biased with a gain of 3.

Tran-

The -20v through resistor RNH

and diodes CRNA and CRNB and through resistor RNJ and diodes CRNC and CRND
forward biases QQ and QT, respectively.

Transistors QQ and QT are in a common

collector configuration to provide a current gain.
Transistors QR and QS are emitter followers that draw very little current from QQ
and QT.

They provide low impedance for discharging CNC and CND, thus reducing

delay time when crossing the zero volt point.
Output voltage is approximately the same as input voltage.

Output current is 20 rna

maximum.

41249000 A

7-13

A
HAA

MV

!
C

PA
B

f

~120

A OR B

TP

f

0

C OR 0

~3.6V

~
TP
CNF
15JLF

~+

CNG
O.OIJLF

-=

CNA
1000PF

r-1
CNK
O.OIJLF

A

+20V
RNG
1.2 K
TP

RNC
10K
RNA
10K RNO
6.81 K

C NC
3900P F

C

RNM
2 15

+20V

B

o

CNL
O.OIJLF

R NE

CN8
R NB
1000 P F l O I<

6. 8 II<
R NF
10K

CNE
3900PF

~~---+-J\'/\/\'---';---~

...L /

CNH
15JLF

~J

~'P
NOTE: VOLTAGE

TP
RNH
1.2 I<

- 20V
AND COMPONENT VALUES ARE FOR

REFERENCE

ONLY.

5C30

Figure 7 -1 O.

7-14

High Level Amplifier - HAA

41249000 A

+0.6 v
A

::

ov
+ 0.6 V
Ov
+ 0.7 V

B

1:: I :

C

8

C

Ov
+ 0.7 V
Ov

D
D

+ 20V

+20V
RNC
5.6K

......--A.,j~.....

-2 OV ......- -....

+20V
NOTE: VOLTAGE AND COMPONENT VALUES A RE

FOR

REFERENCE ONLY.
SC2S

Figure 7 -11.

41249000 A

High Level Amplifie r - HAB

7 -15

A-B

TP
A.

C
PA.

B

,
,*

3.6V

C-D

HJA

D

3.6V

VOLTAGE

TP

*
s::s20MA

C OR D

PEA K

CURRENT

RNK

270
+20V4--J~~-'----

__

C
~--+--Jvv~--~~--~O

RNF
2.15K

+20V
RNH
10K

R NE
1.5K

-20V

-20V

RNM

RNJ
10K

IK

os
RNP
CRNC

CN D

~__~__-JvIO~O~__O~.(IP#

CRND

TP
QT

NOTtl VOLTAGE AND COMPONENT

VALUES ARE

FOR

RE FERENCE

ONLY.

5C29

Figure 7-12.

7-16

High Level An1plifier - HJA

41249000 A

()

Lamp Driver - IAA
The IAA Circuit (Figure 7-13) sinks a current of 91 rna to drive a lamp.

Capacitor

CNB slows down switching time of QS and provides a ramp output to prolong the life of
the lamp. A" 1" input at either A or B or both lights the lamp.
Bare "0" is the lamp extinguished.

Only when both A and

3V
A OR B
OV

A

I:~: I

B

,
I

~

C

jE-20,..,SEC

I
SIMA

I

C

~

CURRENT

140MS

~

o

MA

t6V

RNA
1.21<

A

RNB
1.21<

RNE
1001<

OP

CRNA

C

B

os
R NF
3. SI<

RNC
1.2 J(

NOTE: VOLTAGE AND COMPONENT VALUES

Figure 7 -13.

41249000 A

ARE

RNH
'680

FOR ,REFERENCE ONLY.
5CI5

Lamp Driver - IAA

7 -17

A "1" at either or both inputs turns QN on.

CNA discharges through RND and QN.

The base of QP goes to ground.

Transistor QP is off, so the base of QQ (3. Bv) is

more positive than its emitter.

Transist~r QQ is on, causing current to flow through

RNJ.

The voltage drop across RNJ (approximately O. 7v) turns QR on.

QS turns on.

Transistor

Zener diode CRND clamps the voltage across RNL at 2. Ov, which is a

current of 91 rna.
A "0" at both inputs turns QN off.
QP on, QQ, QR and QS are off.

CNA charges through RNE until QP turns on.

With

No current flows in the lamp.

Lamp Driver - lBA
The lBA circuit (Figure 7-14) sinks a constant load current of 200 rna.

Capacitor CNA

ramps the output to prolong the life of the lamp connected to output B.
A "1" on input A turns QP on.

The base of QN is at ground.

The base of QR is clamped at +2. 7v by Zener diode CRNC.

Transistor QN is off.
Transistor QR is on.

A

2-volt drop across RNE assures a 200-ma current.
A ilO" on input A turns QP off.
base of QR goes to ground.

The collector clamps at +0. 7v when QN turns on.

Transistor QR is off.

The

No current flows.

Lamp Driver - lCA
The lCA circuit (Figure 7-14) functions as a switch supplying current to a lamp at
output B.

When input A receives a "0" (ground) signal, the lamp turns on.

When

input A receives a "1" (+3v) signal, the lamp turns off.
Output B is connected through a lamp to a voltage supply, typically +20v.
receives a "0" signaL transistor QN turns off.
bias transistor QR through resistor RND.

When input A

This allows the +6v supply to forward

Transistor QR turns on, conducting current

from the voltage supply. through the lamp and RNE to ground.
When input A receives a "1" signaL QN turns on.

The lamp lights.

Transistor QN conducts current

away from the base of QR, removing the forward bias.

Transistor QR stops conducting.

The lamp goes out.

7-18

41249000 A

+ 3V

A

r-

Td1
8

20V

I

VOLTAGE

~

OV

2.2V

-..f I-- Td

8

x8A

200MA

:rIA

OMA
+3V
A

OV

~
~CA

+20V

B

2.2 V

VOLTAGE

XC A

OMA

B

-liMA

CURRENT

®

RND
390

+6V

CHA

0.0

(i)

I"

B
F

RNC
1.2 Ie

RNA
1.21(

QR

r

-

-

-

-

--

®

QN

CRNC
2.7V

QP
RNI
1.21(

RNE
10

NOTES'
I.



VOLTAGE AND COMPONENT VALUES
FOR REFERENCE ONLY.

ARE

COMPONENT AND CONNECTING WIRES NOT
USED ON :rCA. DOTTED LINE SHOWS Q.N
BASE CONNECTION FOR :rCA. ENTIRE
CIRCUIT (LESS DOTTED LINE) FOR XIA.
5e 5

Figure 7 -14.
41249000 A

Lamp Driver - lBA, lCA
7-19

The voltage drop across RNE when QR conducts is directly proportional to the load
current.
of

QR

At a load current of 200 rna, the voltage across RNE is 2 volts.

cannot go more positive than +2. 7v because of Zener diode CRNC.

The base
Therefore,

QR starts losing its forward bias when the load current reaches 200 rna (2 volts across
RNE).

Transistor QR is thereby protected against a short circuit.

Low Speed Driver - IDA
The IDA circuit (Figure 7 -15) acts as a switch.

Outputs Band C are connected through

external resistors and a common load (typically a solenoid) to an external voltage
supply.

A" 1" at input A causes current to flow through the external load.

A" 0" at

input A shuts off the current flow.
A "0" at input A turns off transistor QN.

The emitter and base of QP are both at +6v.

Transistor QP is, therefore, not conducting, which keeps QT from conducting.

The

left side of capacitor CNA charges to +6v, while the right side is held at approximately
+0. 7v by resistor RNH and the base-emitter voltage drop across QQ.

Transistor QQ

is held on by the current through RNH, driving the base of QR to ground.
QR is off.

The base of QS is at ground and is off.

Transistor

No current flows through the

external load.
A "1" at input A turns on transistor QN.
on.

The base of QP goes to ground, turning QP

This allows the +6v supply to flow through RNE to the base of QT, turning it on.

Then, 200 rna of current flows through the external load and QT to ground.
When the collector of QN goes to ground, the left side of CNA also goes to ground.
This back biases the base-emitter junction of QQ by approximately 5. 3v (the original
voltage across CNA).

Transistor QQ turns off, allowing the base of QR to go positive.

Transistor QR turns on and drives the base of QS positive.

Transistor QS turns on

and allows an additional 850 ma of current through the external load and QS to ground.
The base of QQ then rises toward +6v through the charging action of resistor RNH on
CNA.

When the base of QQ reaches +0. 7v, QQ turns on and QR turns off.

the current flowing through QS by driving the base of QS to ground.

This stops

The 850 rna of

current through QS lasts approximately 7 ms.
CNB limits the rise and fall time of the 8S0-rna current pulse.
7-20

41249000 A

L;:~ ~

A

A~

::

C~
B

l ..

7 ......

-.-

·0·

r

+40V

... D
+40V

... D

~---------------.----.---.------.----~~----.-------.-~
RNA
1.2 K

RNa

IK

RNH
10K

+IV

CNC

::L O.OIf&F
QR

C".

O.O,*,F

.tlL

ZIO

NOTEI VOLTAGE AND COMPONENT VALUES ARE

FOR REFERENCE

ONLY.
ICI.

Figure 7 -15.

41249000 A

Low Speed Driver - IDA

7-21

Write Driver - JAB
The JAB circuit (Figure 7-16) provides current to the write heads so that data may be
recorded.

Outputs E and F are connected to opposite ends of the write head, which is

center tapped to ground.

When input A is positive, current flows through output E to

its half of the write head.

When input B is positive, current flows through output F to

its half of the write head.

When A is positive and the unit is writing, B is negative.

When A is negative and the unit is writing, B is positive.

Therefore, only one half of

the write head may be activated at anyone instant while the unit is writing.
With a positive charge on input A transistor QN is off.
the emitter of QS is positive.

The negative voltage at B turns transistor QT on.

drives the emitter of QR negative.
about -2v.
-2v.

The base of QR is positive and
This

Transistor QR conducts, driving the base of QQ to

Transistor QQ is an emitter follower, so the emitter of QQ is also near

The -2v on the base of QP turns QP off.

No current flows through output F (-20v

through resistor RNA only reverse biases an external diode).
QS goes slightly negative.

With QT on, the base of

Transistor QS is off, allowing the base of QU to go to +40v.

Transistor QU is an emitter follower, so the emitter of QU also goes to about +40v.
The +40v on the base of QV turns QV on.

Current now flows from a +40v supply con-

nected to output G through transistor QV and its half of the write head to ground.

A

resistor lies between output E and the write head to limit the current flow in the write
head.
When input A goes negative and B goes positive, QN and QS are on and QR and QT
are off.

On the bases of QQ and QU are currents of +40v and -2v, respectively.

emitter of QQ goes to about +40v.
QV is off.

The emitter of QU goes to about -2v.

No current flows through output E.

Transistor QP is on.

The

Transistor

Current flows

from the +40v source connected to output G through QP and its half of the write head
to ground.
Input D supplies a negative voltage when the unit is writing to reverse bias diodes
CRNA and CRNF.
negative.

If the unit is not writing, D is grounded and both inputs A and B go

This turns on QR and QS.

Transistors QP and QV are, therefore, off and

no current flows through the write head.

7-22

41249000 A

OV
A
-!.8V
OV
8
-!.8.V
A

E
POW

B
C

F
F
G

0

8.5 MA

CURRENT

OM A

E

8.5MA
OMA

F
G

:t

C

CNA
O.I""F

CRNe

CRNO

RNO
33K

-20~V____. -____~-+~

-20V

CRN A

CRNF

CRNB

CRNE

A

/f' CNC

~O.OI""F
B

-20V

o
l: NHIBIT
NOTE: VOLTAGE

AND

COMPONENT

VALUES

ARE

FOR

REFERENCE ONLY.
IICIIII

Figure 7-16.

41249000 A

Write Driver - .JAB

7-23

Erase Driver - JBB
The JBB circuit controls the current driving the erase heads.

When input E

(Figure 7-17) is a high voltage, output H provides current to erase heads.
When input E goes to a high voltage, capacitor CPA charges, causing a 10- psec delay
before transistors QR and QP turn on completely.
supply in a fault detect circuit.

Output G is connected to a +40v

When QR is on, current flows from G through QR to

the erase head connected to output H.

The ramp output protects the information on

neighboring tracks from being destroyed.
When E drops to Ov, CPA discharges through RPA.
off.

After 10 psec, QP and QR are

Output H is at Ov.

Line Transmitter - LAA
The LAA circuit (Figure 7 -18) provides a positive voltage output at C and a negative
voltage output at D when either A or B or both are a "1" input.

When A and Bare

both "0", the output is determined by the external load circuit connected to C and D.
If both A and Bare "0", QN is off.

The base of QP goes positive and QP conducts.

This causes the emitter of QQ to be more positive than its grounded base.
QQ conducts.

The collector voltages for QP and QQ will be approximately +0. 9v and

+0.2v, respectively.

The difference in collector voltage is due to the positive charge

on the base of QP and the grounded base of QQ.
sate for this voltage difference.
respectively.

J)

RNC is smaller than RND to compen-

The emitters of QR and QS will be at +2. 4v and -4. Ov,

The base of QR is held at about +4. 9v by RNF and RNE.

QS is held at about -4. 9v by RNG and RNH.
C and

Transistor

Both QR and QS are off.

The base of
The voltage at

is, therefore, dependent on any external voltage supply that may be present.

If either or both of the inputs go to "1", QN turns on.

base of QP turning QP off.

Current flows a way from the

Transistor QQ is, therefore, off.

are then forward biased and conduct about 25. 0 rna of current.

Transistors QR and QS
CRND and CRNE are

forward biased and the output at C goes positive, while the output at D goes negative.
The voltage of either output is determined by the current flow through the external
load, but n1ust be kept under 4. 9v.

7-24

41249000 A

59.4V

E
F

:I::: I :

E

G

I

OV
57.4 V

H

H VOLTAGE
~

OV
10,...S EC

I

H CURRENT

.....
F

I+-

40 M A

o

M A

10"" S EC

+ 40V
RNE
(RPB)

IK

G

E

.:r
-=

TP

CNS
(C PA)
2200PF

H

-20V
NOTESI

VOL TAG E AND COM PO N EN T

Figure 7 -17.

41249000 A

VA L U E S

ARE

FO R

R E FE R E N CEO N L Y.

Erase Driver - JBB

7-25

+ 2V

TP
A
B

~
L:A

A OR B

I F:

OV

C

D

6V
TOTAL POTENTIAL
OF C AND D

IV

+20V

+20V

R NB

RNJ
1.2 K

3.9K

RNE
1.2 K

RNL

1K

TP

RND
120

RNK
1.2 K

RNH
1.2 K

- 20V
NOTE :

VOLTAGE

AND

COMPONENT

VALUES

ARE

FOR

REFERENCE ONLY.
!5C Z 0

Figure 7-18.

7 -26

Line Transmitter - LAA

41249000 A

Oscillator - MAA
The MAA circuit (Figure 7 -19) produces an amplified, oscillating signal at a prescribed frequency.

The circuit description is divided into three parts: the D. C.

conditions throughout the circuit; the oscillator section of the circuit; and the amplifier circuit.
D. C. Conditions
CRNA, RNA, RNB and RND hold the base of QN at approximately +17 volts.
reverse biased by 3 volts and does not conduct.

CRNB is

The emitter of QN is held at about

+16v, producing a collector current in QN of about 16 rna.
The base-emitter voltage drop across QR holds the base of QR near +0. 7v.
current through RNH is then 5. 1 rna.
5. 1 rna must flow through RNJ.
QS must then be about +10v.
be near +10v.

The

With the base current of QR at a low level, the

The voltage at the junction of the emitters of QP and

To maintain this +10v, the collector voltage of QR must

The collector current of QR is, therefore, 5. 55 rna.

Oscillator
Transistor QN acts as an emitter follower yielding a high current gain with nearly no
voltage loss.

CNB, CNC, and LNA form a resonant network.

Near the resonant

frequency, the signal voltage at the junction of LNA and CNB can be much greater than
the voltage through RNE in the feed-back portion of the circuit.
loop formed by QN, RNE, CNB and LNA is greater than 1.
oscillates.

The gain around the

The system, therefore,

When the signal at the base of QN exceeds 6v peak to peak, QN approaches

saturation, thereby limiting the amplitude of the oscillation.
Amplifier
Transistor QR is a common emitter amplifier.
to the bases of QP and QS.
a low impedance output.

41249000 A

The output of QR is directly connected

Transistors QP and QS are emitter followers that provide

Capacitor CNF isolates dc voltages from the load.

7-27

OUTPUT

AT

A

f

rOScl. T?P AA
~

1I.8:!: I V

a

Ov

PEAK TO PE~

IE----

5.4 ~ 031'SEcj

+20V

RNK
1.8K

RNO
CRNA

470

6.2V

+

QP

RNB

470
CN F T P

~--.---+~I~~

RNA

IK

-20V
NOTE: VOLTAGE

AND

COMPONENT

VALUES

ARE

FOR

REFERENCE

ONLY.

5CI8

Figure 7-19.
7- 28

Oscillator - MAA
41249000 A

Waveform Generator - MBA
The MBA circuit (Figure 7-20) is a waveform generator whose output at C is normally
at "0" when both inputs A and B are at a "0".

When either or both of the inputs go to

a "1", a "1" pulse is created at output C for a predetermined length of time.
When both inputs are at "0" (ground), transistor QN is turned off.
forward biased by the +6v source through RNF.
from output C directly to ground.

Transistor QP is

Transistor QP then conducts current

The output is a "0".

During this period the left side

of CNA goes to about +5v, while the right side is held at +0. 7v by the base-emitter
voltage drop across QP.

3V
A
A

:1 ::. p~_C_

OV
3V

_8_ _

B

OV

f-

35p.SEC

3V

C

OV

+6V

RNF
6.8 K

IK
CRNB

A

C

RNA
1.2K
QN

+ 6V
B

CRNA

RNB
1.2 K
CRNe

RNC
IK

RNE
5.6 K

NOTE: VOLTAGE AND COMPONENT VALUES

ARE FOR

REFERENCE

ONLY.

5Cl7

Figure 7-20.
41249000 A

Waveform Generator - MBA
7-29

When either or both of the inputs experience a "l"~ QN turns on.
conducts current away from the left end of

CNA~

Transistor QN then

driving it to approximately ground.

The voltage across CNA cannot change immediately, so that base of QP goes to about
-4. 3v, turning QP off.

With QP not conducting the output goes to a "1" (voltage is

supplied by the circuit driven by MBA).
of QP reaches approximately +0. Bv.
output falls back to "0 ".

CNA now charges through RNF until the base

Transistor QP then begins to turn on and the

The pulse width in this case is about 35 usec.

When both inputs return to "0 ".

QN is again turned off.

The left side of CNA goes

toward +5v through the voltage divider formed by RND and RNE.

The right side of

CNA is again held at +0. 7v by the base-emitter voltage drop acrosS QP.
Adjustable Waveform Generator - MBC
The MBC circuit (Figure 7 -19) is a tuned amplifier which is rung by the negative clock
and data pulses present at input A.
The tank circuit connected to the collector of QN is tuned (and is adjustable) to twice the
frequency of the input data pulses (each data pulse falls between two clock pulses;
absence of a data pulse is interpreted as a zero).

The high Q of the circuit provi.des

a fly wheel effect and yields a sinusoidal signal that is almost totally free of peak shift.
Transistors QP and QR form a zero-crossing

detector~

emitter follower circuit that

provides high impedance so as not to distort the sine wave.

The circuit clips the

positive half of each sinusoidal excursion so that the signal at the TP is a half -wave
re ctifie d sine wave.
The transistor in the output load (next circuit) functions to clamp this rectified signal
and to provide what is nearly a square wave output at B.
Quantiz ing Dete ctor - QAA
The input at A to the QAA circuit (Figure 7 -22) is an AC signal.
positive, output B is a "0" or ground.

When input A is

When input A is a null, output B is a "1".

When input A is positive, transistor QN is off. The base of QR goes toward -20v, but
is held at about -0. 7 volts by CRNA. Transistor QR is, therefore, off. This allows
the base of QP to go positive.
7-30

Transistor QP turns on, leaving output B at ground.
41249000

B

ALL O'S PATTER N

ALL I'S PATTERN

_------J"'----_,

A

CLOCK

" I"

CLOCK

CLOCK

"0"

CLOCK

A

TP

TP

A-WG

A - - - 1 - - - 1 MBC I - - - - A - - B

+

B

O.7V
OV

+20 V 4-~~-------_,

CRNA

RND
2.2K

RNB
IK

TP

CNB
47PF

QP
B

A

NOTE: VOLTAGE AND COMPONENT VALUES

ARE

FOR REFERENCE ONLY.
5C '27A

Figure 7-21. Adjustable Waveform Generator - MBC
41249000 B

7-31

NULL

LEVEL

. ,II

A Ov

110 11

B
TP

COy

_C~!.~-41 ::A P?B

II III
B

11

+20V

0"

r~

+6V
TP

RNH
2.2 K

r

I
RNE
15 K

I

C

OR
~CNB

"'1'CND

-L6800PF

-.:!:-6800PF

":::I"

-

I

I

I

I

L ___ _

...J
RNG

2.7K
NOTES'
I. VOLTAGE

@

OAA

AND COMPONENT

USES ENTIRE

SCHEMATIC

SCHEMATIC.

ARE

DOTTED

FOR

REF~RENCE

ONLY.

LINE ENCLOSES

FOR QBA.

Figure 7-22.

7-32

VALUES

5 C 16

Quantizing Detector - QAA. QBA

41249000 A

_

..J

When the signal on input A drops to a null, QN turns on, applying a positive charge
across CNB.

CNB, LNA and CND filter the signal to remove any variations in the

envelop on the input signal (waveform A).
QR turns on.

When CND charges to a positive voltage,

This drives the base of QP to ground.

QP turns off, allowing current

to flow from the +6v source thr ough RN J to output B.

A" 1" (+3v) appears at B.

Quantizing Detector - QBA
The QBA circuit (Figure 7-22) gives a "0" output at B when input C is negative.

When

input C is positive, output B will be a "1".
With a negative input at C, the base of QR is negative.
to about -0. 7v by CRNA.

The negative voltage is limited

Transistor QR turns off, driving the base of QP positive.

Transistor QP, therefore, conducts current from the +6v source through RNJ to
ground.

Output B is at ground, or a "0".

With a positive signal at input C, the base of QR is positive.
current from the +6v supply through RNH to ground.
ground and QP is off.

Transistor QR conducts

The base of QP is, therefore, at

A voltage of +3v is therefore felt at output B (a "1 ").

Quantizing Detector - QCA
Inputs A and B of the QCA circuit (Figure 7-23) are connected to the outputs of a sector
transducer preamplifier.

Each time a sector is detected by the transducer, a 55-psec

"1" (+3v) pulse appears at output C.

The input at A and B is an analog signal.

The

output at C is a standard logic signal.
With a O-volt differential input across A and B, diode CRNA holds transistor QP off,
while transistor QN is on.
therefore, off.
RNJ.

The collector of QP is at about +19v.

Transistor QR is,

The base-emitter junction of QS is reversed biased through resistor

Transistor QS is off.

Transistor QT is turned on by the forward bias supplied

through resistor RNQ and diode CRND.

With QT on, diode CRNF is forward biased

and conducts current from output C through QT to ground.

The output is near ground,

or a "0".

41249000 A

7-33

A

TP

~::r-----L..I:.....J:p?c

B

Q

c
DI FFERENTIAL
INPUT
(B
A)

a

+20Y

RNK

10K
TP

RNN
1.8 K

RNL

10K
B

RNP

820

CRNE

C

-20Y
RNE
6.8 K

CRNF

RNJ
12 K

-20Y
NOTE: VOLTAGE AND COMPONENT

VALUES ARE FOR REFERENCE ONLY.
5C 22

Figure 7 - 23.

7-34

Quantizing Detector - QCA

41249000 A

When a sector mark appears, the differential voltage across inputs A and B rises with
B more positive than A.
+11 v.

Transistor QP turns on and its collector voltage falls to about

The drop in voltage is felt at the base of QR.

the voltage on the base of QS.

Transistor QR turns on, raising

Transistor QS turns on.

Transistors QS and QT com-

prise a single shot circuit whose pulse width is determined by resistor RNQ and
capacitor CNB.

Transistor QT turns off, reverse biasing diode CRNF.

rises to a "1" level.
QT.

Output C

After 55 psec, CNB charges sufficiently to turn on transistor

Diode CRNF is again forward biased and the output returns to a "0".

Resistor

RNP provides feedback to keep QS on while QT is off.
Speed Detector - QDA
The QDA circuit (Figure 7-24) monitors sector pulses to determine whether the spindle
is at a predetermined speed.

If the spindle is below speed, no output is present.

When

the spindle reaches the desired speed, an output current activates the speed relay
which signals the controller that the unit is up to speed.
Each time a sector is sensed, a short" 1" pulse is applied at input A.

Transistor QN

conducts and completely discharges capacitor CNA through RND to ground.
pulse is removed, CNA charges through RNC.
at the base of QR, QP and QQ turn off.
controlled rectifier CRM, turning it on.

When the

When the base of QP reaches the voltage

Transistor QR conducts current to silicon
CRM draws current from the base of QS

driving it to ground, and from the base of QR through RNK.

The base of QR falls to

about 9.03 volts. OR then turns on firmly and prevents "runt spikes" on the signal
to CRM.

Once CRM is turned on, CNB begins discharging through RNM and CRM.

CRM remains on until the discharge current from CNB falls below the holding current
of CRM (typically 1 rna).

With the base of QS near ground, QS conducts.

QT turns off, QU is on, and QV is off.

Transistor

No output signal is felt at B.

If the spindle is below speed, pulses arrive at the input at a low repetition rate.

CNA

repeatedly discharges and recharges to the point where QP and QQ are turned off.

The

output of QR is a series of positive pulses with a pulse width determined by
T=Tr-T c
where T r is the time between input pulses and T C is the time for CNA to change to the
point where QP is turned off.

The pulses repeatedly trigger CRM.

voltage at the base of QS below the point where QS can turn off.
on, QV is constantly off.
41249000 A

CRM holds the

Since QS is constantly

No output is felt at B.
7-35

TP

h .1
r
I

A
POW
- - -..... QDA

I

A

ov
B
B
~-----------

ov

+20V

RNF
4.7K
CRND

RNH
lOOK

RNL
82K
CRNF

RNP
4.7K

RNO
10K

RNS
3.3K

RNT
3.3K

CRNG
TP

OS

OR
+6V

CRM

RNG
560

NOTEI VOLTAGE AND COMPONENT

VALUES

RNJ
9.09K

ARE FOR

+CNB
3.3#

RNN
IK

REFERENCE

ONLY.
5C9

Figure 7-24.

7-36

Speed Detector - QDA

41249000 A

When the spindle reaches the required speed, the pulses at input A have the same
period as TC.

The pulse width out of QR becomes TI - T C = O.

Transistor QR never

emits a pulse.

With no pulses out of QR, CRM never turns on.

This permits CNB to

charge to the point where QS is constantly off.

The higher voltage at the base of QS is

fed back to the base of QR through RNK to raise the voltage required across CNA to
turn off QP.

This feedback prevents rapid fluctuation of the output when the spindle is

near the required speed.

With QS constantly off, QU is off and QV is on.

Current

flowing through QV activates the speed relay connected to B, and signals the controller
that the unit is up to speed.
Or - QEA
The QEA circuit (Figure 7-25) detects any decrease in voltage supply greater than 15%.
A fault condition will occur if:
1.

-20 supply decreases below -17. Ov

2.

+40v supply decreases below +34. Ov

3.

+20v supply decreases below +17. Ov

4.

+6v supply decreases below +5. Iv

If all positive supplies are normal, QQ, QR and QS are off.

Their emitters are held

at +5. 8v by Zener diode CRNE and the value of RNW (determined by testing to give a
precise collector voltage).
across resistor RPA.

Current is pulled through QT, causing a voltage drop

This voltage drop turns QV on.

Transistor QX turns off.

If

any of the voltage supplies drop below 15% of their operating values, the respective
transistor turns on.

Transistor QT will then be off.

Transistor QV turns off.

Tran-

sistor QX turns on, driving the output to ground.
The negative voltage segment of the circuit is similar to the positive section.
decrease in the -20v supply below 15% will turn QN on.
causing QU to turn off.
which turns QY on.

41249000 A

A

Transistor QP turns off,

Transistor QW turns on causing a voltage drop across RNM

The output drops to ground.

7-37

-20V
+40V

A

H

OR

+20V~ QEA

~E

+6V";;~-"""'--'"

RND
2.2K

-20V

- 20 V +---"./V'-'......---~

QN

R NJ
220
R NS
2.2K
RNZ

660
+6V
R PO
2.7K

RNP

IK
RNT

RPE
2.7K

RPA
220
NOTES:
.:

~

VOLTAGE
RESISTOR

AND COMPONENT VALUES
VALUE

TO

BE

FOR

SELECTED.

Figure 7-25.

7-38

ARE

REFERENCE ONLY
esC!!!

Or - QEA

41249000 A

E

Quantizing Detector - QFA
The QFA circuit (Figure 7-26) detects a fault in the write and erase drivers or in the
head select circuit.

If there is an open in the head, either of the drivers is non-

functional, or more than one head is selected, a fault signal occurs.
Inputs A and B are connected to the write and erase driver circuits and enter across a
voltage bridge to the base of QP.
diodes are forward biased.

Normally, both inputs are approximately 32v.

All

Voltage on the base of QP is 32v and the emitter is at 31. 4v

due to a reverse bias O. 6v base-emitter voltage across QP.

Transistor QP is off.

All input current goes to ground through RND.
If input A is higher than input B by 1. 4v, CRNB and CRNC are forward biased.

and CRND are reverse biased.

CRNA

The voltage on the base of QP becomes that of input B.

The emitter of QP is O. 7v higher than the base due to a O. 7v drop across CRNB.
Transistor QP'is on.
If input B is higher than input A by 1. 4v, CRNA and CRND are forward biased.

and CRNC are reverse biased.

The base of QP is at the voltage of input A.

emitter of QP is O. 7v higher than the base.

CRNB

The

Transistor QP is on.

Input C is connected to the head select circuits.

If more than one head is selected,

the drop in effective resistance (due to external resistors in parallel) results in an
increase in current through RNA.

This increases the voltage drop across RNA,

turning QN on.
If either QN or QP is on, QR turns on.

Output D goes to ground to signify a fault

condition.
Quantizing Detector - QFB
The QFB circuit (Figure 7-27) is used to amplify and shape an incoming wave.
input at A and B is a differential sine wave.

The

The output at C and D is an amplified

and clipped version of the input wave.

41249000 A

7-39

A
CNA

:::t O. I", F
QP

+20V

RNC

220K

+40V

C

RNA
348

NOTE:

VOLTAGE

AND COMPONENT

VALUES

ARE FOR

REFERENCE

ONLY.

5 C 27

Figure 7-26.

7-40

Quantizing Detector - QFA

41249000 A

TP
A

C

A-QD

o

QFB

B

A

TP

TP

TP

B

~---+------~~~------~-----T~----~-

+ 0.6 v

ov

C

+ 0.8 v 0

oV

I--__~

RNS

390
r-------------------~--~~----~--~~r_-.

+20V

TP
C
CRNC
CRNA

CRND

CRNB
R NP

51.1

RND

RNT

17.BK

2.2K

RNU

270

'-------------------+-------------------+---4--..J\!\Jf\r---+ -

20 V

CND

![15,..F

NOTEI

VOLTAGE AND COMPONENT

VALUES

ARE FOR

REFERENCE

ONLY.

!SCZ4

Figure 7-27.
41249000 A

Quantizing Detector - QFB
7-41

Transistor QR is the current source for the differential amplifier stage consisting of
QN and QP.

Capacitors CNA and CNB filter out dc and low frequency noise and pass

the input wave which alternately turns on QN and QP.

The output at the collectors of

QN and QP are clipped by diodes CRNA and CRNB to approximate a square wave.

This

square wave is fed to the bases of QS and QT for another stage of differential amplification.

The square wave output at the collectors of QS and QT is again clipped by

diodes CRNC and CRND.

The output at C and D is a clipped, square wave between Ov

and +0. 6v corresponding to the rise and fall of the sine wave at inputs A and B,
respectively.
Quantizing Detector - QFF
The QFF circuit (Figure 7 -26) produces a positive pulse output in response to a
positive input pulse.

The width of the output pulse is independent of the input and is

adjustable.
Assume a condition where QN is on.

With the collector of QN at ground, QP turns off

and CNC begins charging (through RNL to ground via QN and QS) toward Vcc volts.
The duration of the charging period is controlled by the time constant RNL x CNC.
When the base of QQ reaches O. 7 volts" QQ turns on, QS turns off, and the output goes
to ground.
With the circuit in the condition of the preceding paragraph, a no-signal state- will have
the following effect:
current is drawn

Ground level at base of QN turns it off.

thrOl~gh

the base of QP and turns it on.

Since QS is also off,

Current now flows through

QP charging CNC in the opposite direction (from preceding paragraph) to about -5. 3
volts (Zener diodes CRNe voltage minus the O. 7 base -emitter voltage of QQl.

As the

current increases and decreases (during charging period) through QP, the remaining
current still flows through RNL thereby keeping QQ on.
When a clock or data pulse is applied to the base of QN it turns on.

With the QN

collector at ground, QP turns off and a -5. 3v base -emitter voltage appears across
QQ, turyting it off.

Capacitor CNC again charges through the variable resistor RNL

until QQ turns on.
When the circuit has been adjusted so that the width of the output pulse exceeds that of
the input pulse, QS stays on (after the input drops) to hold the base of QP at ground.
7-42

41249000

B

Capacitor CND is a filter capacitor to provide a constant voltage across CRNC.

I

Line Receiver - RAA
The line receiver circuit, RAA, (Figure 7 -29) provides a "1" output at C and D when
the difference in input voltage (A minus B) is greater than +0. 6v.

Under any other

input conditions, the output will be a "0".
Diode C RNA is used to maintain the threshold level at +0. 6v.
threshold would be about +0. Iv.

Without CRNA the

That is, if input B were just O.lv less positive than

input A, the circuit would switch to an output of "1".
Resistor RNE supplies the emitters of QN and QP with a constant current of about
4. 25 rna.

If the current in one transistor increases; the current in the other transistor

must decrease by an equal amount.

If input B is more positive than input A (A minus B

is negative), QP will be turned on and QN will be turned off.

If the difference "A

minus B" is only slightly negative, QP will conduct more than QN, but both will be on.

41249000

B

7 -42.1/7 -42. 2

I+-IOO--.t.-IOO--..j
NSEC
NSEC

TP

I

I

I

0.7V
OV

i - - - -....

A

r-

A-QD

A--A-..... Q FF 1--'-'--+- B

B

CUTOFF POI NT
CONTROLLED BY RNL

-.--..;--- -,

O.75V
OV

VOL.TAGE SUPPLY
RNK

I

+20V~-vvv-+-----+---------.-----~

IK

+20V

RNL
5K

+20V

CND
0.01
p.F

TP

RNG

2.2 K

RNF

B

150

NOTE:VOLTAGE AND COMPONENT VALUES
ARE FOR REFERENCE ONLY
SCI28

Figure 7-28.

41249000 B

Quantizing Detector - QFF

7-43

HI

C

A ~--------~--------~--------~~--- OV

o
LO
B ~--------~---------+--------~~--- OV

3.5V

caD

OV

TP

-,

-

r

+20V

I

®

I

C

I

r

+20V

RNP

IK

RNU

IK
RNM
820

-,
I
I

CRNB

___ -1

L

I
_-.J@

NOTES:

I.

VOLTAGE AND COMPONENT

®

PORTION

@

eRN C

WITHIN

USE DON

VALUES

DOTTED LlNE
RBA

ARE

FOR

IS USEU FOR

REFERENCE ONLY.
RAA

ONLY.

0 N L Y.
5 CIO

Figure 7-29.

7-44

Line Receiver - RAA

41249000 A

The base of QR, therefore, becomes more negative than the base of QQ.
QR turns on, driving its collector and the bases of QS and QT positive.

Transistor
Transistors

QS and QT turn on, conducting current from the +20v supply through RNN and RNS,
respectively, to ground.

The output at C and D is near Ov or a "0".

If input A is at least +0. 6v more positive than input B (A minus B is greater than or

equal to +0. 6v), QN turns on and QP turns off.
than the base of QR.

The base of QQ is then more negative

Transistor QQ turns on conducting current from the +20v supply,

through RNK and RNL to ground.
current to their bases.

Transistors QS and QT are turned off as there is no

Current is then allowed to flow from the +20v supply, through

the load resistors to outputs C and D.

The value of the output voltage is tempered by

the resistors RNP and RNU to ground, and is held at a "1" level.

The output is a "1".

Line Receiver - RBA
The operation of the RBA circuit (Figure 7 -29) is identical to the RAA circuit, except
that output C and its related circuitry are omitted.

Output D remains intact (with the

addition of diode CRNC) and functions the same as output D in the RAA circuit.

For a

detailed discussion of the RBA circuit, refer to the discussion of the RAA circuit.
Switch Receiver - RDA
Switch Receiver RDA (Figure 7-30) produces a "1" (+3v) output at C when the grounded
switch connected to input A is open.

When the switch is closed a "0" (Ov) is felt at

output C.
A switch to ground is connected to input A.
approaches +6v and QN is shut off.

When this switch is open, capacitor CNA

Transistor QP is, therefore, on and conducts

current to the base of QQ through resistor RNF.
base of QR to ground.

Transistor QQ turns on, driving the

Transistor QR is off, which allows current to flow from the +6v

supply through RNK to output C.

The output is a positive voltage, or a "1".

When the switch is closed, the voltage across CNA rapidly increases through RNA and
the switch to ground because of the short time constant of RNA and
bounce on the switch will increase the discharge time.
decreases, QN begins to turn on.

Any contact

As the voltage across CNA

As QN conducts current to the base of QP, the

forward bias on QP is decreased and QP begins to turn off.

41249000 A

C~A.

As QR turns off, the

7-45

current through RND decreases due to the higher lead resistance (RNE) of QN compared
with QP (RNF).
across RND.
completion.

The current drop through RND causes a decrease in the voltage drop

The bias on QN is, therefore, increased.
Transistor QP is shut off.

causing QQ to shut off.
QR.

The cycle goes rapidly to

With QP off, the base of QQ is near ground,

This allows the +6v supply to flow through RNH to the base of

Transistor QR, therefore, conducts current away from output C and the output is

near ground or "0".

A ,
;

A

;

I
9
I~:: I
LSA

n n n

SWITCH
INPUT A
B

.1

RCA

I

OPE.N

U U LI

CLOSED
3V

B

OV

tE-

34~SEC ~
C

66~SEC4
3V

C

OV

+6V

r

------,

RNH
2.7K

C

RNL
2.7K

00

~

RNJ

~ 2.7K

I@
@

_ ..J

L
NO TES:
I.

VOLTAGE

AND COMPONENT VALUES

@

DO T.T ED CO NNE C T ION

~

C I R CUI T

ARE FOR REJrERENCE

AND RES 1ST 0 R R N JAR E

WIT H I N B R 0 KEN

LIN E BOX

FOR

1SAD DE D FOR

ONLY.

RCA 0 N L Y •
R0A

0 N L Y.

5 CI I

Figure 7-30.
7-46

Switch Receiver - RDA, RCA
41249000 A

When the switch is opened again. CNA charges slowly to +6v due to the long time constant of RNB and CNA.

Any contact bounce on the switch will hold CNA well below the

switching level of QN until the bouncing ceases.
QN begins to turn off.
of QN.

As the voltage across CNA increases.

Transistor QP begins to conduct current away from the emitter

Transistor QP turns on rapidly because of this positive feedback.

The output

then returns to "1".
Switch Receiver - RCA
The operation of the RCA circuit is similar to the RDA circuit. except that transistor
QR is omitted and the output is taken directly from the collector of QQ at B
(Figure 7-30).

The output is, therefore, opposite from the output of the RDA circuit

under the same switch condition.

When the switch is open, the output at B is a "0".

When the switch is closed, the output at B is a "1".

For a detailed discussion of this

circuit refer to the RDA circuit description.
Line Receiver - RFA
The RFA circuit (Figure 7-31) provides a non-standard "0" output at C when input A
is at least O. 6v more negative than input B;

Diode CRNA holds the threshold at O. 6v.

Under all other input conditions the output will be a non-standard "1".
If the differential input (A-B) is greater than O. 6v, transistor QP turns on and QN

turns off.

This drives the base of transistor QR more positive than the base of QQ.

Transistor QR conducts current from the -20v supply, through RNK to ground.

The

output at C is near Ov.
If the differential input (A-B) is less than O. 6v, QN turns on and QP turns off.

base of QQ goes more positive than the base of QR.

The

Transistor QQ conducts and a

negative voltage is felt at output C.
Since a "1" is defined in MDD logic as the most positive voltage, the Ov output in the
first case is interpreted as a non- standard level" 1".

The negative voltage output in

the second case is, therefore, a non-standard level "0".
The receiver is self-terminated with 56 ohms to ground on each line.

41249000 A

7-47

>

A-B

0.6V

0
A
B

:d

R

,C

2;8 MA

C CURRENT

~

RFA

o

M A

C

R NC
220

A

RNA

!S6
+20V
RNB

!S6

RND
220

QR

NOTEr VOLTAGE

AND COMPONENT

VALUES

Figure 7 -31.

ARE FOR

REFERENCE

ONLY.

Line Receiver - RFA

Delay - UA-, UBA
The capacitive delay circuit (Figure 7 -32) delays a "1" input at A for a specified period
of time before providing a "1" output at B.

The delay time for a "0" pulse is negligible.

The delay circuit consists of a capacitor connected to ground.
Assume that a "0" (ground) enters at A.
discharged.

If the capacitor is discharged, it remains

The output is an immediate "0".

If the capacitor is charged when the "0"

signal enters, it discharges almost instantaneously.

The "0" appears at output B with

no noticeable delay.
7-48

41249000 A

A

B

A

0

B

I
I

0
CNA

5 C 12

Figure 7-32.

Delay -

UA-, DBA

If a "1" (+3. Ov) enters at A, and the capacitor is discharged, the capacitor must first
charge to a minimum" 1" voltage (typically +0. 7v) before the" 1" appears at output B.
The time necessary to charge the capacitor to this minimum voltage is the delay time
of the circuit.

The charge time is dependent on the value of the capacitor, the value

of an external resistor between the source voltage and the delay circuit, and the
minimum voltage required to produce a "1" response.
Delay times for capacitive delays used in the MDD unit are as follows:
Delay

VAA
UAB
UAC
VAD
UAE
VAF
VAG
UAL
UAM
VAN
VBA
UAP
41249000

D

Time

o. 3

psec

O. 4 psec

O. 2 IJsec
1 psec

500 IJsec

2 IJsec
O. 1 IJsec
10 psec
8 IJsec

5 IJsec

15 psec
60 msec

I
7-49

Delay: Circuit - DCA
The DCA circuit (Figure 7 -33) provides a delayed "0" output signal at B a set time
after a "0" is felt at input A.

A" 1" signal is not delayed.

The operation of the DCA circuit is similar to the DDA circuit except the final transistor QD (Figure 7-33) is omitted for the UCA circuit.

This allows a "0" output when

transistor QT (Figure 7-33) conducts .. and a "1" output when QT is turned off.

For a

detailed discussion of this circuit, refer to the DDA circuit.
The time delay is still dependent upon the values of RNC and CNA.

The delay for a

DCA circuit will be slightly less than the delay for an identical DDA circuit due to the
extra time taken for transistor QD to turn on in the UDA circuit.
Delay: Circuit - UCB
The DCB circuit is identical in operation to the DCA circuit (Figure 7 -33).

The values

of RNC and CNA are changed to produce a different time delay.
Delay Circuit - DCC
The DCC circuit is identical in operation to the DCA circuit (Figure 7-33).
of CNA and several resistors are changed.

The values

In addition, a 10-ohm resistor is added in

series with the collector of QN to increase the discharge time of CNA when QN is
turned on.
Delay Circuit - DCD
The DCD circuit is identical in operation to the DCA circuit (Figure 7 -33).
of CNA and several resistors are changed.

The values

In addition, resistors RNA and RNB and

their connections are omitted, CRNA and CRNB are replaced by a lK resistor, and a
47-ohm resistor is added in series with the collector of QN to increase the discharge
time of CNA.
Delay Circuit - DCE
The DCE circuit is identical in operation to the DCA circuit (Figure 7-33). The values
of CNA, RNC and RNH are changed. In addition, a 47-ohm resistor is added in series
with the collector of QN to increase the discharge time of CNA. The feedback to the
base of QR through RNL is omitted. Resistor RNG is replaced by a 3. 6v Zener diode
to limit the voltage on the base of QR to +3. 6v.
7-50

41249000 A

3V
A
OV

UTDp

9

A

~

B

210~MC

IE3V

UC_

B
OV

+6V
RND
2.21(

RNC
2.71(

RNA
1.21(

RNM
1.2 I(

RNH
I.SIC

I

QN

@

+

CM
o. I".'

OT

RNI

RNG

II(

2.71(

ItNiN
1.2 I(

.GTII'I. VOLTAGE

@

CNA

AND COMPONENT VALUES ARE FOR

IS AN ELECTROLYTIC CAPACITOR FOR

REFERENCE ONLY.
UCA

AND UCE

CIRCUITS

ONLY.

SCI

Figure 7-33.

41249000 A

Delay Circuit - DCA, DCB, DCC, DCD, DCE

7-51

Delay - UDA
The UDA circuit (Figure 7 -34) provides a "1" output at B a set length of time after a

"0" enters at input A.

There is no delay for a "1" input signal.

The output is an

immediate "0".
When a "1" appears at input A, QN conducts current from the +6v supply, through
RNC to ground.

The base of QP, therefore, approaches ground.

The base of QR is

held at approximately +3. Bv by the voltage dividing action of RNG and RN J.
emitters of QP and QR are, therefore, held at approximately +3 volts.
The base and emitter of QS remain at +6 volts, so QS is off.
QT are both at ground.

Transistor QT is off.

The

QP is off.

The base and emitter of

The collector of QT goes to approxi-

mately +2. 4v due to the voltage dividing network formed by RNM, RNN and the baseemitter voltage drop across QU.

Transistor QU is turned on and the output is held

near ground, or a "0".
When a "0" (ground) appears at input A, QN turns off.
begin charging from the +6v supply through RNC.

This allows capacitor CNA to

When the voltage at the base of QP

reaches approximately +3. Bv, QP starts to conduct, drawing current away from the
base of QS.

Transistor QS starts to turn on, forward biasing the base of QT.

sistor QT starts conducting.

As the collector of QT approaches ground, the voltage

on the base of QR is drawn off through RNH.

This decreases the voltage on the

emitters of QR and QP and drives QP to saturation.
are also driven toward saturation.
ground.

Tran-

With QP saturated, QS and QT

When QT conducts, the base of QN goes toward

Transistor QU is cut off and the output voltage rises to a "1" level.

The time delay is determined by the values of RNC and CNA.
Delay - UDB
The operation of the UDB circuit is identical to that of the UDA except the size of
capacitor CNA (Figure 7-34) differs to cause a delay of 115 ±25 ms.

7-52

41249000 A

3V

A

A

9

UTD

ov

fE-300,..SEC~

B

UDA

3V
B

OV

RNA

RNC

RNO

RNG

RNM

1.2 K

22K

2.2K

1.5 K

1.2 K

B

QN

+
QT

CNA
15,.. F
RNB'

RNJ

1K

2.7K

NOTEa VOLTAGE

AND COMPONENT

VALUES ARE FOR REFERENCE

ONLY.

se7

Figure 7 -34.

41249000 A

Delay - UDA. UDB

7-53

Undirectional Time Delay - UEA
The UEA circuit (Figure 7-35) provides a O. I-fJsec delay between the time that a -3. 5v
signal appears at A and the time that transistor QP turns off.

Output at B is either

ground or an open circuit.
When input A is near ground, QN is off.

Transistor QP is on .. The output is ground.

When input A goes to -3. 5v, capacitor CNA begins charging.
of QN is sufficiently negative to turn QN on.

After O. 1 fJsec the base

Transistor QP turns off.

The output is

an open circuit.

OV

A

A

I

UTO
U EA

I

- 3.5V
~

B

~~O.IJLSEC

........- - - 4 -

OPEN -

1-1--

OV

B

.1---,.,..I

-20V

B
RNA
22K

A

CRNA

T
NOTE: VOLTAGE

CNA
220PF

ANO COMPONENT

VALUES

ARE

FOR

REFERENCE

ONLY.

ae 44

Figure 7-35.

7-54

Undirectional Time Delay - UEA

41249000 A

And - VAA
The VAA circuit (Figure 7-36) consists of a single NPN transistor. When all inputs
connected to A are at a "1" level, the output at B will be a "0". Any "0" appearing at
A will result in a "1" output at B.
When the input to A is a "0", A is held at about +0. 9v.
forward bias diodes CRNA and CRNB or transistor QN.
output at B is a "1".

This input is not sufficient to
Transistor QN is off.

The

When the input to A is a "1 ", A rises to about +2. 1v. This voltage forward biases
CRNA, CRNB and QN. Transistor QN turns on, conducting current away from B to
ground. Output B is left at about +0. 9v, or a "0".
Diodes CRNA and CRNB provide noise immunity up to 1. 4v. Resistor RNB connected
to ground turns off QN when the positive voltage is removed from A.

r----'

I
I

8

I

I

I I

A

I

_____ .JI

-----,
I

B
+6V

I

I

IL _____

+2.1 v (- I")
+0.9v ("0")

s:::s ov

r----- Vee

I
I

I I
I

Vee

I

I ____ .JI
L

+2.1 v (_I")
11
+O.tv (.0 )

=:SO V

DOTTED LINES FOR CIRCUIT WITHOUT LOAD
AT A OR B

NOTE: VOLTAGE AND COMPONENT VALUES
ARE FOR

REFERENCE ONLY.
!5C 21

Figure 7-36.
41249000 A

And - VAA

7-55

And - VAB
The V AB circuit (Figure 7 -3 7) consists of two silicon peripheral logic inverters whose
outputs share a common load resistor, RNE.
(ground), the output at C will be a "1" (+3v).
the output at C will be a "0".

When both inputs A and Bare "0"
If either or both of the inputs are a "1 ",

This is an AND gate for zeroes, or a NAND function.

When both A and B are at ground, QN and QP are off.
the +20v source through RNE.
logical

"1".

The output at C is supplied from

The output is a positive voltage, representing a non-

If input A experiences a positive voltage while B is at ground, QP turns

on and conducts current from the +20v supply through RNE to ground.
has no effect, as all the supply voltage is tapped to ground.
or a "0".

The situation is similar if A is "0" and B is "1".

The "0" on B

The output at C is ground,
The output is "0".

both A and B have positive voltage applied to them, QN and QP both conduct.

If

The

output is "0".
Capacitors CNA and CNB provide a one's delay on input B and output C, respectively.
They also maintain a noise barrier to isolate the circuit from stray pulses on the lines.
And/Or (Single Input) - VAC, VJW
The single input AND/OR or silicon peripheral logic (SPL) inverter (Figure 7-38)
provides an inversion from input A to output B: A "1" on A produces a "0" on B, or
a "0" on A produces a "1" on B.

The inverter's output may be connected to the output

of other inverters to form NAND functions or NOR functions.
The SPL inverter is a single NPN silicon transistor connected as a common emitter
amplifier.

When A is a "0" (between Ov and +0. 3v) the transistor is off.

current to flow from the +20v supply, through RNB to output B.

The output is a "1".

When input A is a "1" (between +0. 7v and +3. Ov) the transistor turns on.
conducts current from the +20v source, through RNB to ground.

This allows
The transistor

This leaves output B

near ground, or a "0".
Since the base-emitter threshold for a silicon transistor is approximately +0. 7v, the
circuit ignores up to O. 5v of transient noise.

7-56

41249000 A

20V
A
OV

j

B

3V
OV

,

A «
B

dV:•.1

20V
C

,C

OV

I

7.4 MA

C

OMA

CURRENT
+20V

RNC

TP

•. lee

C

OP

CNB
IOOOPF

.T
-

ON

-20V

NOTE: VOLTAGE

AND COMPONENT VALUES ARE FOR

REFERENCE ONLY.
5CI4

Figure 7 - 37 •

41249000 A

And - V AB

7-57

+4V

A
A

A

,
I

,
I

9

A

9

A

OV
B

VAC

+20V
B

ov

B

V.JW

+20V

B

NOTES;
I.

<&)

VOLTAGE AND COMPONENT VALUES
DOT TED

LI N E TO ... 20 V AND

ARE

RES 1ST 0 R

FOR
RN 8

REFE RENeE

ONLY.

F OR V.J WON L Y.

5CI!

Figure 7-38.

And/Or (Single Input) - VAC, VJW

If the circuit drives just one other transistor, the output may be connected directly to

the base of the driven transistor.

For a fan-out of 2 or more, a base isolation re-

sistor is required for each driven transistor.

This resistor ensures that the base

drive provided to each of the driven transistors will be nearly independent of differences in base-emitter voltages.

For a fan-out of 2 the collector load resistor must

be reduced by one-half its value for driving one transistor to provide for the additional
voltage drop across the isolation resistors.
Switching time for an inverter with a fan-out of 1 is typically 15 nsec.

7-58

41249000 A

Power Driver - V JK
The V JK circuit (Figure 7-39) is similar to the V JS circuit with the addition of
capacitor CNB and two outputs.
ramp output.

CNB slows the switching time of QN and provides a

Output B connects to the center tap of the head.

Output C contains a

10K resistor and is connected to a voltage supply in a fault detect circuit.

If two heads

The

are selected the effective resistance falls to 5K (two 10K resistors in parallel).
increase in current causes a Fault signal.

Output

l)

contains a diode that isolates each

Write Gate.

3V
A

A

:~:g
I

OV

B

~

C

OPEN

I,C,D

D

I

tYJK)

OY

--t t d t---

+40V

I
OR

A

I

V .. S

P

,

OV

tV .. S)

I

I

RNC
2.2K

I

+ 40V +-..JV\I\r-

®

RNC
10K

®rI

+20V

C

-0

-J\N'v-

D

CRNC

--M- --

-LcNa

-0

~6'PF
QN

RNa
22K

-

NOTES;
-20Y
I. VOLTAIE AND COMPONENT VALUES

@

USED FOR

(!)

USED FOR V"S ONLY.

V .. K ONLY.

Figure 7-39.

41249000 A

ARE

FOR

REFERENCE ONLY.

ICl4

Power Driver - V.IK

7- 5D

Power Driver - VJL
The V.JL circuit (Figure 7-40) is a gate used to bias an analog gate.
If +20v appears at A. QN turns on.
off.

The base of QP goes to ground.

Capacitor CNA charges through RND to +20v.

A +0. 2v signal at A turns QN off.
clamps at +0. 7v.

A

,I.

Output at B is a ramp to +20v.

When QP turns on, the collector voltage of QN

CNA discharges rapidly through QP.

I:~~I

B
;I.

Transistor QP is

Output B drops to ground.

+ 20V

A

OV

+ 20V

B

OV

+20V

RNA
6.8 K

A

C RNA

CRNB CRNC

RNB

22K

-20V
NOTE: VOLTAGE

AND COMPONENT VALUES

ARE FOR REFERENCE ONLY.
5CII

F i gu r c 7 - 40.

7-60

P owe r

J) r

i v er - V J L

41249000 A

And - VJM
The VJM circuit (Figure 7-41) gates a particular receiver into operation.

at A results in an "open" enable signal to the receiver.

A "0" input

A" 1" input at A disables the

receiver.
A "0" (Ov) input forward biases diode CRNA.

The +20v supply current is drawn through

RNA and CRNA, leaving the base of QN reverse biased.

Transistol' QN is off.

Output

is held at -0. 7v by the next stage.
A "1" input turns QN on.

The output goes to ground.

No receiver signal can pass into

the receiver.

+3V

A

ov

+O.sv

B

-0.7V

+20V

-20V
NOTE: VOLTAGE AND COMPONENT

VALUES

ARE FOR

REFERENCE ONLY.
5 C26

Figure 7-41.

41249000 A

And - V.JM

7 - 61

Or - V.TN
The V.JN circuit (Figure 7-42) is a NAND circuit that inverts the input signal.
is connected to the output of a receiver and to a gating circuit.
off, the base of QN is grounded.

Input A

If the Write gate is

The circuit is disabled.

When the write gate is on, QN turns on and the receiver inputs a "0".
turns on further and goes into saturation.

Transistor QN

Output voltage at B is approximately -0. 2v.

When the receiver inputs a "1". QN comes out of saturation.

Output at B is approxi-

mately -3. 5v.
Whenever the write gate is on. QN is on to some degree.

Only when the write gate is

off is the base of QN at ground and QN off.

TP

I:J~ FJ

_A_-I-/____

OV

A

- O. 7V

B

o

B

V

- 3.5 V

+20V

~
•

A

.@
RXA

151<

TP

RNB

2.21<
NOTES:

I.

®

-20V

VOLTAGE AND COM PONENT
RESISTOR AND

POWER

VALUES

ARE

FOR

SUPPLY EXTERNAL

RE FERENCE

ONLY.

TO VJN.
5C43

!"igUl'(' 7-42.

7 - 62

01' - V.IN

41249000 A

And-VJP
The V JP circuit (Figure 7 -43) is normally used as the input circuit to a toggle flipflop.

It ties two receiver outputs to a single-ended output.

Capacitor CNA is used to

reduce the input impedance for faster switching.
When input A is near ground the base of QN is at approxin1ately +0. 9v.
is off.

Transistor QN

Output at B approaches -20v, but is clamped at -3. 8v by a Zener diode in the

following circuit.
When input A is -3. 5v, QN turns on.

Output drops to approximately -0. 2v.

Input to A is short (l00 nsec), negative, data pulses.

Output B is also short pulses.
OV

A
- 3. 5V

A

,,

9

A

,
«

VJP

B

OV

B

-3.8 V

+ 20V
RNC
22K

RNA
IK

A

CNA
22PF

B

RNB
6.8K

-20V
NOTE: VOLTAGE

- 20V
AND

COMPONENT

VALUES

ARE

FOR

RE FERENCE

ONLY.

II C 42

Figure 7-43.
41249000 A

And - V.JP
7 -63

Power Driver - V.JR
The V.JH circuit (Figure 7-44) is a +40v switch.
output B. A "0" on input A stops current flow.

A "1" input turns QN on.

A "1" on input A produces +40v at

Transistor QN conducts current from the +40v supply,

causing a voltage drop across resistor HNB.

This voltage drop turns on QP.

Output

13 is at +40v.

A "0" input turns QN off. Since curTent no longer flows, the emitter and base of QP
arc at e4 ua1 voltage. Tr'ansistor QP is off. Output B goes to ground.

+3V
A

A

POW

I

,

l.

V"'R

OV

~ Td

B

I

f.-

+40V

B

OV

RNC

RNB

2.2 K

IK

NOTE:
VOLTAGE AND COMPONENT VALUES
ARE FOR REFERENCE ONLY.
ISC21

FigUl'(\

7 - 6 -+

7-4 . :1:.

PO\\'C'!' I)t'ivP!' -

\".JH

41249000 A

Or - VJS
The V JS circuit (Figure 7 -39) is a standard inverter with a capacitor delay at the input.
1\ "1" at input A pulls the output at B to ground.

A "0 'I produces a +40v output.

Or - VJT
The VJT Circuit (Figure 7-45) is a gate to the \VBB toggle flip-flop.
produces a ground at B, which keeps the flip-flop off.

A "1" input at A

A "0" input at A produces a

-3. 5v output at B, which releases the flip-flop and presets it in a given state.
When a "0" is applied to input A, the base of QN goes to gt'ound.
The base of QP is clamped at +0. 6v by diode CRNC.

Transistor QN is off.

Transistor QP is off.

Output B

is -3. 5v derived from the voltage dividing network of RNF and RNG.

+
A

3V

OV
~TdlE-

A

I :JRT

p

B
;

I

ov

I

- 3.5V

B

-20V

+20V

RNB

R NE

22K +20V

6.8K

B

RNA
2.2K

6.8 K

RNG
IK

A

'l'" C N A
-L IOOOPF
NOTE: VOLTAGE

AND

COMPONENT VALUES

ARE FOR RE FE RE NCE

ONL Y.

ISC4ts

Figure 7-45.

41249000 A

Or - V.TT

7- 6 5

When A goes to a "1 ", capacitor CNA charges.
positive enough to turn QN on.
Transistor QP turns on.

After a delay, the base of QN is

The base of QP goes negative through resistor RNE.

The output at B drops to ground.

And - V,JU, V.IV
The V,JU and V.IV circuits (Figure 7-46) are functionally identical.
standard inverter circuit with a capacitive filter input.

They consist of a

The capacitor also presents

a dclay.

A "1" on input A reverse biase s diode CRNA.

Capac itor CNA charges through RNA

until it is clamped at about 3 diode voltages (approximately 2. Iv).

QN turns on.

Output B falls to ground.
If input A is a "0", CNA discharges through CRNA.

Transistor QN turns off.

Output

B r'ises to a "1" level due to the clamping by a Zener diode.
And/Or - V.TW
l{cfcr to circuit descr'iption for circuit type VAC.
Flip-l·'lop - WBB
The WH B cit'cuit (Figure 7 -4 7) is a toggle flip-flop with gate and data inputs.
Input B holds both tr'ansistors off by grounding the bases when the circuit is off.

When

a \\' l'ite operation is tq be pe donned, the base of QP is l'eleased whilp QN is 8t ill
grounded by input C.

This sets an initial condition for the flip-flop:

(~P

is on. QN is

off.

After' tllP flip-flop is pre-set it is toggled through input A by a series of negative data

pulses.

T'he leading edge of the negative data pulse begins charging capacitor CNB.

\)ioc\(' C HN I) becon1cs fot'ward bias('d.

QP is on.

Output E is at ground.

of -3. 6v acr'oss Zenet' diound until

(~V

A current

is tUl'ned off.

CNB

The

OUT-

Uuring the short time that QV is off, a

negaiiv(' pulse appeal'S at output C.
Diodes CHNU and CHNE

pl~event

saturation of QR and QS.

As the collectors of QR and

qs appt'oach gt'ound, the negative voltage at the left ends of RNJ and
the

SUl11

RNK is lilnited to

of the voltagp drops act'OSs QH and CRNU or QS and CRNE, respectively.

I)iod<.' C UN F prf'vents Q\. fron1 saturating.

7-70

41249000 A

ov
- 4 v

A
A
B

:I

TP
SS

XAA

I?

,

OV

B

C

- 4 v

CNA
47PF

Ov
-4v

U

C

TP

CRNO

RNO
2.21<

RNP
IK

QR

ON
RNG
8.21<
RNB
II<

+20V

C
CRNB
RNO
3.3 I<

CRNA

-20V
CRNC
OS

~-~.IV'I,~_~

- 20 V

CNB
47PF

-20V
NOTE: VOLTAGE

AND COMPONENT VALUES ARE

FOR REFERENCE

ONLY.

5C 15

Figure 7-49.

41249000 A

Pulse Shaper - XAA

7-71

Pulse ShaRer - XAB
The input at A of the XAB circuit (Figure 7-50) is a balanced square wave between Ov
and +4v.

The output at B is normally positive, but drops to ground for a short time at

the leading edge of the ground portion of the input wave.
During the positive portion of the input wave, transistors QN and QP are on.
leaves the bases of QQ and QR near ground.

Transistors QQ and QR are off.

This
The

output at B is a positive voltage supplied through resistor RNE.
When the input wave goes to ground, transistors QN and QP turn off.
the base-emitter junction of QR is forward biased.
output at B drops to near ground.

With QP off,

Transistor QR conducts and the

With QN off, capacitor CNA charges toward +20v.

When the charge on CNA reaches a level sufficient to turn on QQ, the base of QR again
drops to ground.

Transistor QR turns off.

The output at B returns to the positive

level.
Pulse Shaper - XAC
The XAC circuit (Figure 7-51) produces a 100-nsec ground pulse at output C when the
inputs at A and B change state.

The output is normally positive.

Input A is connected

to the set side of a flip-flop and input B is connected to the clear side.
When the flip-flop is clear, the base of QR is positive.

Transistor QR conducts 10 rna

of current from the -20v supply through RND, RNC, QS, QR and RNB.
of QN is at +20v and the collector of QR is near +13v.

The collector

Transistors QT and QU are on

and QV and QW are off.
When the flip-flop sets, QR turns off and QN turns on.
+13v, which drives the base of QT to about -6v.
QV positive.

The collector of QN goes to

This turns QT off, driving the base of

QV turns on and the output at C goes to ground.

through RNE with a time constant of 135 nsec.
of QT has risen to +0. 7v and QT turns on.

Capacitor CNA charges

After 100 nsec the voltage at the base

This drives the base of QV to ground.

QV

turns off and the output at C returns to a positive level.
When the flip-flop clears again, a 100-nsec ground pulse is formed at C by QR, CNB,
QU and QW.

7-72

41249000 A

+

A
A

I I,
S5

iI.

XAB

I

40 v
Ov

B

+ 20 v

8

Ov

+20V

+20V

+20V

R NO
2.2 K

QQ

NOTE:

VO'LTAGE AND

COMPONENT VALUES

ARE

FOR REFERENCE ONLY.
IIC!I

Figure 7-50.

41249000 A

Pulse Shaper - XAB

7 -7'3

+4v

A

Ov
+4 v

B

GATE

Ov

+20 v

c

Ov

+ 20v
RNN

+20V

2.2K
C

+20V
QV

CNA

47 PF
RNE

RNH
680

2.87 K

RNK

+20V
RNM
6.8K

1.2K

RNF

RNI

2.87K

680

QU

+20V

RNL

- 20V

6.8K

+20V
NOTEI VOLTAGE AND COMPONENT VALUES ARE

GATE

FOR REFERENCE

ONLY.
5C6

FigUl'C' 7-51.

7 -7 -l

Pulse Shaper -

~AC

41249000 A

HEAD AND DISK PACK REPLACEMENT CRITERIA

HEAD REPLACEMENT CRITERIA
Heads of the MUD have been designed so that they should not need replacement if given
proper preventive maintenance and care.

If a head requires replacement refer to the

Preface of this manual for the publication containing the Maintenance section.
to that section for Head / Arm Replacement procedure.

Refer

A head is defective and needs

replacing if any of the following conditions exist:
1.

Consistent oxide buildup on head, indicating repeated head/ disk impact.

2.

Appreciable oxide buildup located primarily on the edge of the ferrite inse rt,
indicating a warped head.

3.

Oxide or wear over 1/2 of the head face surface.

4.

A head which is scratched over 1/2 of the head face surface.

5.

Concentric scratches on disk surface.

6.

Audible ping indicating that the head is hitting the disk surface.

Inspect the head for imbedded particles.

UISK PACK REPLACEMENT CRITERIA
The disk pack is designed to last the lifetime of the equipment.

Heplacement of the

disk pack is requirecl only if excessive t'unout (see Disk Pack Hunout Check) is
encountered or physical damage to the pack results in the loss of recording ability.
A '-,lisk pack is defective and needs rcplaCelTICnt if any of the following conditions exist:
1.

Damage to the disk pack resulting in a bent or broken disk.

If a disk is bent

perform Disk Pack Hunout Check procedure.
2.

Gouged or SCOl'pc\ disk surface causing the loss of stored data.

:~.

Imbedded particles in a disk surface that cannot be renlovecl by cleaning and
al'e causing danlage to the heads.

41249000 A

7-75

Disk Pack Runout Check
This procedure determines whether a bent disk pack may remain in use.

If the disk

pack fails to meet the requirements of the procedure. it should be returned to the
manufacturer for reconditioning.
1.

Extend the upper deck drawer forward.

2.

Release four half-turn fasteners securing right-hand shroud side cover.

Set

the side cover aside.
3.

Install the disk pack to be checked on the spindle of the upper dec k.

4.

Grasp the pack cleaning brushes. override the shaft detent n1echanisn1. and
rotate the brushes into the disk pack.

5.

Place the disk pack runout gage (PiN 84357600) base against the undersiele of
the upper deck shield and set the switch on the base of the gage to ON
(Figure 7 -52).

6.

Turn the bezel of the dial indicator to indicate zer'o.

Orient the dial indicator

so that the plastic tip is not only contacting a disk surface but is deflected for
an indication of approximately 0.020 inch.
position.

Tighten dial indicator in this

Turn the bezel to set the dial indicator to zero.
NOTE
A mirror is required to observe dial indicatol' when
SOlTIe disk surfaces are checked.

7.

lVlanually and'slowly rotate the disk pack one full revolution while cdl'efully
observing the dial indicator.

The

SUD1

of the deviations (to either' side of

ZE'l'o)

should not exceed 0.012 inch.
8.

If a total deflection of 0.012 inch is encountered in step 7. recheck the indica-

tion.

The total deflection must occur in a disk circumference of 4 inches or

morc.
9.

Hepcat steps 6 through 8 for the 1 D remaining di sk surfaces.

10.

Hotate the pack cleaning brushes clear of the disk surfaces.

11.

Remove the disk pack and the disk pack runout gage.

12.

Install the shroud side covet'.

7 -76

41249000 A

DETAI L

UPPER DECK
DRAWER (RIGHTHAND SHROUD
SIDE COVER
REMOVED)

\

DIAL INDICATOR
(PART OF DISK PACK
RUNOUT GAGE)

~DISK

PACK RUNOUT
GAGE (BASE ATTACHED
MAGNET I CALLY TO
UNDERSIDE OF UPPER
DECK SHIELD)

5CI16

Figure- 7-52.

Disk f:.>ack H,unout Check

TESTEH CAHD
The Tester Card (PIN 40072100) is a special tool used extensively in the n1aintenance
procedures of Section 6.

As an aid in using the card, the schematic diagram (8 F'FN)

is provided in Section 5 and Figure 7 - 53 is the logical portrayal of the same card.

41249000 A

7-77

1,2 I 5,6

-J
I

-J
00

1(414

32_ .c:412

~410

,,- K408

.I~'

ON

..........

3

lOIREc::,

~so.

I'~

A03CR10A

3,4

1(40C

31

1(404

~

1(402

.
..
r-_

300NSEe

CYLINDER

!7

.,

COhTlINUOUS SEEKI

K400

~I401
(i)@

•

1419

1421

&

1411

"'03-20

14

K511'
S£Et< ER ROR

p

F"'~

Cf

-

.1>

K003~

K005~
TI

...n

o

~~'::::::::::::=::[j-;----:---

~

------~

~

o

Y5C~

--

HIO

••

T510

TO COLLECTOR OF L ISTEO

TE~M.

&IOIRECTIONAL LINE.

Figure 7- 53.

AND

PRO~IOES

4.

LOGIC THIS SHEET DRAWN AS IF CARO WERE INSTALLED FeR LJPPH
SPINDLE (LOGIC ROW AI. TO USE WITH LOWER SPINDLE, CHAIoGE

5.

SEE

A ROW LOCATIONS

11100

A

~o

CONt.iECTIONS

LOGIC DRAWINGS

3,4 T 7,8

CO

1'1

CAPACITOR (YOOel ADDEO TO COLLECTOR (PIN 9.) OF 1001
A 2/OSEC DELAY ON OUTPUT PINS 12, " , AIoO 14 OF ICC-7.

o
o

::t>

.....

NOTESI

(i)
(i,

I

-.-h

1

II

I!-_____

KOO I

O.I~'

T3

~

-.J

A03 CI ••

T2

~

1522

(i)
fiTZS

-L-

......
t\:)

,

Logical Presentation of Tester Card

FOR

KEY

TO

TO

8.

SYIIIBOLS.

~6
7,8

READ/WRITE TESTER CARD

The read/write tester card (p/n 54014500) is used during maintenance procedures
that require reading or writing on a disk pack.

The card is also used in troubleshoot-

ing procedures involving the fault detection circuit logic.
As an aid in using the

card~

the schematic diagram (9DMN) is provided in Se ction 5.

The card is logically represented in Figure 7 -54.

Instructions for use of the card

follow.
INSTALLATION AND REMOVAL
1. Stop spindle motor for deck to be tested.
2. Set associated ON LINE/OFF LINE switch to OFF LINE.
3. Set associated power supply DC/OFF switch to OFF.
4. Remove 9DNN card from logic chassis location BOI (for upper deck) or AOI
(for lower deck).

Install read/ write tester card (pIn 54014500) in vacated

loc,ation.
5. Set tester card ENABLE switch to OFF.
6. Set associated power supply DC/OFF switch to DC.
7. Start spindle motor.

Deck will load heads and stop at track 00.

8. Ground test point on card at COlor D02 that corresponds to the number of the
head to be used in the read or write operation (selects head).
9. Position heads to track location specified by maintenance procedure.
10. Perform read or write operation specified by maintenance procedure according
to following applicable paragraph.
11. When maintenance procedure is

complete~

12. Set associated DC/OFF switch to OFF.

stop spindle motor.

Disconnect any oscilloscope connections.

13. Remove read/ write tester card from logic chassis location AOI or BOI and
install 9DNN card in vacated location.
14. Remove head selection jumper on card COlor D02.
15. Set a~sociated DC/ OFF switch to DC.

41249000 J

7-79

TPX

TPQ
TPV

TESTER WRITE DATA

801-38
801-

A3J205-45

~7

A(1205 - 48
1>----;.>---

R700
R700

5 MHZ

CS
SI

l

-----<)

HO

62

15

20
)

SELECT

3

TPU

1514-1346

CONTROL

HEAD

21

l
WRITE

::2

ERASE

24

I623
I624
I625
K500

> I625

)-

1623

~~ l0-=~=---~) 1624
BOI-05

NOTESI

I

LOGIC THIS SHEET DRAWN AS IF CARD WERE
INSTALLED FOR TESTING UPPER DECK (LOGIC
ROW B I, TO USE WITH LOWER DECK I CHANGE
B ROW LOCATIONS AND CONNECTIONS TO A.

2

SEE MOD LOGIC DRAWINGS FOR KEY TO
SYMBOLS
IICII.

OPEN

Figure 7-54'.

7-80

Logical Presentation of Read/Write Tester Card

41249000 J

WRITE
The following procedure commands an MDD deck to write a series of all

"1' S"

or

"0' s" (as selected) on a disk pack.
1.

'Set switches on card installed at BO 1 (upper deck) or AO 1 (lower deck) as
follows:
NOTE
A fault condition may occur if card switches are
manipula~ed

without first setting ENABLE switch

of OFF pos ition.
ENABLE switch to OFF
CS (Control Select) switch toggle up
RD (Read) switch toggle down
WT (Write) switch toggle up
ER (Erase) switch toggle up
PAT (Pattern) switch to 1 or 0 as desired
2.

When it is desired to write the selected pattern, set tester card ENABLE switch
to ON.

Disk pack is written on in first revolution.

3.

Return tester card ENABLE switch to OFF.

4.

Proceed with maintenance procedure.

Return to step 11 of Read/Write Tester

Card Installation and Removal procedure when maintenance procedure is
completed.
READ
The following procedure commands and MDD' deck to read data from the disk pack
track at which the heads are currently located.
1.

Set switches on card installed at :BOI (upper deck) or AOI (lower deck) as follows:

41249000 J

7-81

NOTE
A fault condition may occur if card switches are
manipulated without first setting ENA.BLE switch
to OFF position.
ENABLE switch to OFF
CS (Control Select) switch toggle up
RD (Read) switch toggle up
WT (Write) switch toggle down
ER (Erase) switch toggle down
, 2.

When it is desired to read, set tester card ENABLE Switch to ON.
perform read operation until ENABLE switch is set to OFF.

Deck will

NOTE
A.ll Section 6 maintenance procedures requiring
that data be read from the disk pack, specify the
required oscilloscope connections for that test or
adjustment. Do not deviate. If, however,
unspecified troubleshooting is being performed,
the read operation may be observed at test point H
(Read Data) of the card located at A28 (upper deck)
or A26 (lower deck). Observed data will be in
accordance with Figure 7-55,
3.

Proceed w.ith maintenance procedure. Return to step 11 of Read/W'rite Tester
Card Installation and Removal procedure when maintenance is completed.
~
~ 200NSEC

",'s"

PATTERN

"0 's" PATTERN

OSCI L.LOSCOPE (SUGGESTED);
VERT - I V/CM
HOR - O. 'J.&. SEC/CM
SYNC - INTERNAL

Figure 7- 55.

7-82

Rea~

• C 124

Data Trace
41249000 J

SECTION 8

PARTS DA.TA
Information for this section is included in BM101 and
BM103 Multiple Disk Drive
Pub. No. 41243700

SECTION 9

WIRE LISTS

WIRE LISTS

DESCRIPTION OF WIRE LISTS
The two types of wire lists are:

1.

The line printer format which shows logic wiring.

2.

The corporate (typed) form which shows non-logic wiring.

LOGIC WIRE LISTS
The following is an example of the logic wire lists with an identification, and an
explanation of the columns.

Wire
Identification

Wire Origin
Pin Number
Component
Code

Wire
Length

Wire Destination
Location

I

41249000 A

03
05
05
04
04
02
02
02
02
02

A14
A14
A14
A07
All
B06
B07
B08
B09
BIO

Color
Code

Wire Destination
Pin Number

Wire Origin
Location

AK50010
AK50020
AK50030
AK50210
AK50211
1100520
1100521
1100522
1100523
1100524

Wire
Size

28
25
14
10
16
48
48
48
48
48

o
o

o

o

o
R
R

R
R
R

Change
Order

I
A16
AOa
A09
All
A18
B07
B08
B09
BI0
B11

18
14
37
16
34
48
48
48
48
48

20
20
20
20
20

222
222
222
222
222

1234
5678

9-1

Wire Identification
If the identifier begins with a letter, the wire provides an input to a logic term; first

letter identifies the logic row of the term, second letter and the first three digits
identify the logic term receiving the input via this wire.

If the identifier begins with

a numeral, the wire is not directly providing an input to a logic term and is generally
classified as a miscellaneous jumper.

A sequential advance in the second to the last

digit indicates additional inputs to the same term.

.

AK50010 - single input OR to K500
AK50020 - single input OR to K500

A sequential advance in the last digit indicates the interconnections of an AND input.
AK50210
AK50211

}

Two input AND to K502

Wire Length
This column gives the wire length in inches.
Wire Origin Location
This column locates the origin of the wire on the logic chassis.

Wires having a

common signal at two or more locations are interconnected in series.
the fourth and fifth wires shown have a common signal.

In the sample,

The Wire Destination Loca-

tion of the first wire becomes the Wire Origin Location of the second so that the series
string is from A07 pin 10 to A 11 pin 16 to A 13 pin 34.

Note that the first four charact-

ers of the Wire Identification terms are the same for the three wires and that the
sequencing is from 10 to 11 in the last two characters.
Wire Origin Pin Number
This column identifies the origin pin or terminal of the wire.

9-2

41249000 A

Component Code
This column identifies the components that are located in the Wire Origin Location
and the Wire Destination Location columns. The code letters are identified as
follows:

o - When both ends

terminate at

a logic card

R - When one end terminates at a miscellaneous component (switch, resistor, etc.)
X - When one end terminates at a jack (or connector pin)

Wire Desitnation Location
This column locates the destination of the wire on the logic chassis.
Wire Destination Pin Number
This column identifies the destination pin or terminal of the wire.
Wire Size
This column identifies the size (A WG) of the wire.
Color Code
Solid colored wires are identified by repeating (3 times) the code number in this
column.

Multicolored wires are identified by a number having two or three digits.

Each digit of the number identifies one of the colors.

The code numbers are identi-

fied as follows:

o - Black

2 - Red

4 - Yellow

6 - Blue

8 - Gray

1 - Brown

3 - Orange

5 - Green

7 - Violet

9 - White

S - Shield

Change Order
This column identifies the engineering, field, or publications change order that affected
and/or altered that wire.

41249000 A

9-3

~ON-LOGIC

LISTS

WIRE USTING

Wire lists other than logic are on a standard corporate form.

The remaining

columns of the form contain information NOT normally applicable to
field usage and therefore are not explained.
The other columns indicate:
Gauge (Ref)

- Size of conductor (AWG)

Color (Ref)

- Color information

Length (Approx) - Length of conductor in inches
Origin
Destination
Remarks

- Origin point of conductor
Destination point of conductor
- Useful comm ents

In multi-digit color codes, the first digit denotes base color and the remaining digits
denote tracer colors.

The color codes for the non-logic lists are the same as those

for logic wiring.

9-4

41249000 A

_... ,-_., --

1-'

le.-

_.

-

---~

--

LOOIC CIoiASSIS

lW

IIJL T DiSk DRIVE

F

70811900

. / " SlIfE'

Ifly

....

teo

1 OF' 1

DI..

DAti

A'!

!P~INT OUT 70811900

[UiIt"

~~.1 ~:lJ~1

'-!

-.i..'

coa

J

NOHWlND:LE DIVI~"M

IDlN'

19333

I

SHEIT

1

or

1

-I

1 O~

I

70811900

OOCUIIIIIN' NO

70811900

I";:

NOTES:
1.

Z.

J.

FOR MECH ASSY AND PL SU 40016000,
40016001.

FOR CARO PLACEMENT LIST

III)

LOGIC SCHEMATIC

SE( SUB-FINAL ~SSy 4006I04Z, 40068142 (1X) OR
4 006824l , 4006834Z (ZX).
INSTAlL A SOliD alACk JUMPER WIRE, FIND
NO. 76.t_f'C* PIN 2 AND PIN 50 or OeH
C0NIIfC1UK. "'*BEf( l01 THAU A29 AHO BOl
THRU 829, 10 THE Cl.QSEST HOlE IN THE

CCM/eclUl MOUNTING BAR FOR GRO""'NG.
4.
S.

THESE WIRES

UNIT ONLY.

IN A DI.h\l Q4ANNEL
(LOGIC C~ASSIS 40016000).

THESl WIllS ME PRESENT IN A SiNGlE CHANNEL UNIT ONLY.
-

(LOG.e CHASS'S 40CH6001).

......
41249000

~RE PRESE~

--B

9 -5/9-6

"lW70811900

LOGIC CHASSIS

PAGE

REVISION F

1

AIIOOIO
04 A21
13 0 A2~
08
LOGIC CHASSIS
AI100II---"02--AXI---C3-0--A21--1a
lOGIC (HASSI S
NOTE5
AII0020
08 A21
12 0 825
08
LOGIC CHASSIS
-----------_._--------AI 10110--"--" 04---A21---1b- O---A"2~-----13
LOGIC CHASSIS
NOTE5
AIlOlll
02 A21
16 0 A2l
17
LOGIC CHASSIS
-AIfOf2Q--0-H--AZT-- -08-n-8"25---13
lOGIC cHAsSr..;.S-----------------AII0210
04 A21
10 [) A25
18
Ll.IGIC CHASSIS
A11 ()zYi----OZ-A it--"l O"--lJAZl-- -2-2 ---'-_()(7 fC"~C:-:-H;-:A-:S-:S-;-I-;::S-----------~N-;:::;:O-::;:T-;=E--;=-5
AI10220
09 A21
05 0 825
18
LOGIC C~H~A~S~S~I~S~---------------_---AIl0310----05A"21--14--0-A27
08
LOG-IC CHASSI S
AII0311
02 A21
14 0 A21
21
LOGIC CHASSIS
NOTE5
ATl0320
OR A21
09 a B27
08
LOG I C CHASS IS
AII0410
05 A21
33 0 A27
13
LOGIC CHASSIS
AI 10411-0 2"~21---3:3 -,j" -A 2 1
41
LO-=G-=-I=C-=C-'-'-H-=-A-=-S-='"S =-S--------------=NC":-:O=T=E;::-5:=-AI10420
08 A21
32 0 HZ-I
13
LOGIC CHASSIS
-A I 10510 ---- --05-- --A 2 1--3""O"-li--Ai "(---f H
L(H;
CH7~-S-~n·-';s'-------------AII0~11
02 A21
30 0 A21
42
LUGIC CHASSIS
NOTE5
A"IT0520
07 A21
40 0 D27
18
LOGIC CHASSI S
AII0610
06 A21
29 0 A29
08
LOGIC CHASSIS
AIl06fl
02 A21
29 a A21
44
LOGIC CHASSI S
NOTE5
AII0620
07 A21
38 0 829
08
LOGIC CHASSIS
tnT0710
06 A21
~6 a
A29
13
lOGIC CHASSIS
AII0711
02 A21
36 0 A21
45
LOGIC CHASSIS
NOTE5
i\CIO",?0---61l-i\-zT-'3'", I)' 1-\2l)
13
lI)I;IC C"H:-~A=-S=-S""-I-:-~--------------A I J.(Hi 1 n
0 'i
A (.1 1.
() 1 (1
AL 0
2'1
LI ) G lee H 1\ S SIS
A I 101} 10
02
I~ ~ 1
34 UA 19 - - 2 y
---C(J G- f C - CHA-SSC~-"- --- --- - - - - - - - - - - - - - AI11810
09 Alb
44!) 1125
38
LOGIC _C_H_/.\~SS~IS~"_______________.....,...,.-:~=-=-_
All1H11---------05 AI6----44-[)---'fC"-- 02
lOGfC CHASSIS
NOTE5
AIllf120
06 A16
45 n A2':J
3H
L()GIC CHASSIS
-;rI120 F)
0-4-- "-16
'+ 1 n
AIL
2 H.
U)(i ICC HAS SIS
AI12110
06 Al6
21 () A2/j
44
LOGIC CHASSIS
A I 1221 (J
-0')- A"t6
420----132-5- - 44-----LnT;TccHASSI s-·- - - - - - - - - - - - .
l\II2~ll
04 A16
42 (l Al6
02
LIJGIC CHASSIS
NOTES
'-Af [o-61b---oS-"A;-1-7--Z-[lfAl.Z--36
LnG"TI"C---";;'C"H"-A';;'S';;"S"TI.,...S------:....-----------AI20020
OR A17
25 0 A29
44
LOGIC CHASSIS
AI20110
11 A17
29
BLl)
44
LOGIC CHASSIS
Al201l1
02 A17
29 0 A17
02
LOGIC CHASSIS
NOTE5
-1\170[20
-or-A-l T-:---- -40-o-AI 7 2 I
LOGl',..C~C,.,.-HrTA-..S~S...,..Ir8,-6-AI21510
03 AlB
22 0 A20
25
LOGIC CHASSIS
AT21 71 0
04 A1 H
05 0 Al 9
29
'-l_b ICC HAS SIS
AI21H10
O':J A19
08 0 A25
24
LUGIC CHASSIS
-A" I 2 2 11 0
obl\ 11}
[2 () .t\ 2 7
24
'- 0 I.:,I C CHAS SIS
AI22310
07 A19
14 0 A2l)
32
LOGIC CHASSIS
ATZZ411J----(J3--- Al~----1-8T.J-~-zu-- -3Z-·--r[""7"'o.....b,. . ,.r. ,. C.--,. c'"T""H A"'-,.S.,. .S"TI. S
... - - - - - - - - - - - - - - AI22411
02 A19
18 0 AI')
02
LOGIC CHASSIS
NOTE5
-Ar:r2510
07 Af9
40 0 A2y
24
LO':;IC CHASSIS
Al22R10
07 A19
42 n A2Y
18
LOGIC CHASSIS
AI23010
03 A19
21 (J AlB
21
lOGIC CHi~A"""S"""S""I"""S-------------AI23210
02 A19
34 0 A20
26
LOGIC CHASSIS
·AT2""3"310--- --O-9--z\7.o---rys---(y- ~2~-24
LuG 1 C-CRASs I S
AI23410
02 A20
05 n Al~
09
LOGIC CHASSIS
A123420
02 A2 0 ----u-r-O -.rAT"l-;-;-l)----...-lO
. . -----..L--..("";";1\......
-' l C...----,C.....H.. .,A......S......S....,r.,.S..-----------------AI23430
02 A20
09 n AI~
05
LOGIC CHASSIS
A123440
02 A20
12 0 All)
17
LOGIC CHASSIS
AI23510
10 A20
10 U B27
24
LOGIC CHASSIS
-;-"1

rc--

°

r

u

r7

41249000

B

9-7

LW70S11900

K E V [ S IOi\! F

LOGIC CHASSIS

---_._---

AI23610
10
A20
22 0
~29
L\fZ37IO------{rZ---A20----·Ir-n----"AT9--·AI23RI0
10
A20
13 0
R29

- i~T23Y 10

()lj.-- A.-2(r--l-rO----AT-~

AI23Y20
04
A20
-AT2 3t} 30-- .---0 4- -- A-i()-AI23940

20 0

--140 --

A19

A 1 ')·----::3:-;-6---:-L-:::O:-::::G:-;I,-;:C~-:::C:-:-H-:-::A:-;:S;-;:S:-.;I:-;S:-----------------

04

A21)
16 11
A19
41
A-2(Y ----18-(}-1329~·--rH-

AI24110

02

A20

-

03-A~-

2

32
LOGIC CHASSIS
·"'3,..O--.-L..
U.I.:1. . ........I~C-.-CTTR-rA-"..S..,...S. .I
.. - " . . S - - - - - - - - - - - - - - 24
~UGIC CHASSIS
3.7r---,.:L"""'O'"""'G,....,.,I....".C,......-,.,C,..,..H,.-;A,..."S"'S,....,.I'"7S...---------------..
38
LOGIC CHASSIS

A I 24lrlO--------o cF
-tU2l~3-rO----

PAGE

29 0
Al~
37 ('---A-1Y--·

21

LOGIC CHASSIS
I_OS I C CHASS-·=-I- = - S - - - - - - - - - - - - LOGIC CHASSIS~'---------------__

-26---LOGTctf~fA-SS-I

S

45 n Al':J
13
LOGIC CHAS--=S,...."I.....,S_----------_",...-,-".--A-f24lJl0--A-I'i ·--Z4(1-Ar7--28
1_(j·(rrE~i·fASS IS
11286
AI25010
A20
41 0
A17
30
LOGIC CHASSIS
A 130110
OL)
A 10
09-o---A-o-ij---- 41-----IEii.';TC-CHA-SS--=I-=S------------AI30910
02
AIO
01 0
AO~
05
LUGIC CHASSIS
-AI 313 1()--_. oi- A1o---Zl"-n·- Al·1
22
LO~IC CH-A~S~S~I"'::'S-------------AI32010
02
A09
21 n
AI0
21
L()GIC CHASSIS
-AI32-Z10-----(f3---A09-44 0
A102=-~5--.:::.L..:..:.U..:;..G..:;..I..:;..C~C.....:.H..:.,..:A.:,:.S.:,:.S~I.:,:.S------------AI~4410

04
03
04

A20

AI33010
11
A09
28 0
A27
44
LOGIC CHASSIS
AI33()20
12 - - A09
29- (j--t327 ---44
LOSIC CHA-S-SI S
AI33021
03
A09
29 0
AU9
02
LOGIC CHASSIS
NOTE5
A1345-rO---b-6 .-. A--ur---3-S (~-~
42
LOG I C CH-ASS I-~S-----------~-AI34710
06
AIH
16 0
AI0
17
LOGIC· CHASSIS
·-AT34 1 i (- - ·--(f3-- .-- Ait) - --Cir""i --A 0 4 ---2 5:-----:L:-:(,-::-:)G~'I;-:C;::---:(~':H-:-A-=-S:-:-·s;o:-·~I:=""s- - - - - - - - - - - - - AI34l110
07
AIH
L~l 0
AOL)
16
LOGIC CHASSIS
--J\I36010
02 -A09-01 II
1\·10 - 12----ClL;Tt-- Crlt\SS-CS--AI36020
02
A09
09 0
AIO
05
LOGIC CHASSIS
",-AT36()30
02 -AO-9--~12-n
AIU---TO
LOGIC CHASS·~I~S~-------------AI36040
02
AUg
17 0
AIO
13
LOGIC CHASSIS

=

~~l~~rlo

b3--AO~-~·~

AIO~~2;-;:9~-~L~O~G~I~C~C~H~A~S~S~I~S~--------------

AI36120
02
A09
24 0
AlO
22
LOGIC CHASSIS
--AI36130
-CfZ---A-09 ------32o-ATu
36
LOSIC t-HA·SSI:-:S=-----------------AI36140
02
A09
36 0
AIO
33
LOGIC CHASSIS
-A 13 () 2 10
(Y3--- A09 -------3 irO-tffb~-4.,....,5;:-----;L,.....,('"'""'Jr;""'~-;-1C"'--C~H:-:-A~S=-S'-1= S - - - - - - - - - - - - - AI36220
02
A09
45 0
A10
40
LOGIC CHASSIS
AI36230
04
A09
34 ()
AI0
14
LOGIC CHASSIS
AI36RIO
06
A09
40 0
A19
32
LOGIC CHASSIS
11286
A I 36 H 11
02
A I c:j.~-- -----3-2-~(I---A2 0--- -3" 8
LO G f-CCHASS I'-:S:=-'-----------=-1.;::...12.,,-8..,-6-AI36820
03
A09
37 0
AOH
25
LOGIC CHASSIS
A"T400 10
11
At 2
05 0
t-3'~~-:-:?"-.-~3::-;2~--:-L-:C".....,)G::-:I:-:C::--:C::-H...,..-A~S:::-:S;:-:·I ; - : S = - - - - - - - - - - - - - - - Al40011
02
A12
05 f)
A12
02
LOGIC CHASSIS
Nl1TE5
Ai4()()~()
08
A12
080
A25
32
LOGIC CHASSIS
AI40110
05
A12
36 0
AOM
09
·LOGIC CHASSIS
1.\ I 40120
03
A1237--0-·- A 14--2 Y---[.T) l;-n:C:FfA S S 1 S
AI40730
04
A12
32 n 1\07
38
LOGIC CHASSIS
-AI40YIO
03
AL.f----Zl-n--- A12 ---CO
LUGIC CHASS·=-I=S---------------AI40911
04
A12
10 (1
AOd
20
LOGIC CHASSIS
Iz-Ar4 n5fo- ----()S---AF2--()Y--n----ACf8----21-LlV;
CHASS l'. . .s.,.-·
. -------------11 td41011
03
A12
090
Al::S
2.4
LOGIC CHASSIS
10 AI4121()
04
All
OHO
A12
40 -- .. Lo,·;rc ·l:i1ASSrs----·----·---------J AI41~11
04
A12
40 0
A13
13
LOGIC CHASSIS
8 ~AT41l~O
00-0 ,:>. Alf----05-(r-~-iflL---"4·-1
LOGIc-CHAS-S·'"I . - : S . , . . - - - - - - - - - - - - - - - 7 AI41221
04
A12
410
Al3
17
LUGIC CHASSIS
6 A I 4 1 3i-0----64--ATC--oTIf"·---;A:-:;l:-;-2-:------;:3~4~--:-L-:-O::-:-G~'I;-:C::---::C:.-:-H~A:-::S~S::-::Ir-;S::---------------5 AI41510
04
All
12 n A12
38
LOGIC CHASSIS

Ie

4

---------------------------------

.-----------------~-.--.-.----

41249000

B

. LW70A11900

LOGIC CHASSIS

REVISION F

AI41511

04

A12

38 0

AI 4 I 7 10

04

A13

It 5

PAGE

3

A13
09
LOGIC CHASSIS
A11
17
U )G ICC HAS SIS
ATI..t810
03
A13
41 n A I l
'2.9
LIlGIC CHASSIS
. 1\ TIt? i' 10 -.-- -. . I) '3 .. - ../\ 1. ;r-. --.- ~. 0 (f·· 1\ 1:1
{ Jt(.-.---- IJII--; Ie ell J\ SST ~) --.
" I 'I I I I ()
()',
1\ 1 ?
? 1 II
" 11
() 1
U It j( (: C111\ c.:. " I ~
AJL~;:>?3(Y . -- .. - u?
"l~
~l u·--·"1.1----- L}~---LJII;":--CIlI\S~TS-·1\142.110
04
A13
42 n
All
13
LUGIC CHASSI-,;-S_ _ _ _ _ _ _ _ _ _ _ __
··Af5t)yl(f----· ·(j4----A-OH
l60
Al2.
17
U}(;IC CHASS-ls
AI50920
04
A08
18 n A12
12
LUGIC CHASSIS
-A-I 5 (j 930--- --0 2-A-6 fI--l TIT A·~{)::..::Y=------;1::....:::4=---...::.L:..:;:n:...,;:G--:I...:::,C~C-:-:H-:-A~S~S~I= S - - - - - - - - - - - - - -

n

AI 5 1 3 1 0
05
A1 1
41 0
A0 -t
09
L f) G ICC HAS SIS
A I '51410
04.
A 11
2 1 fJ-A-O -t:---::2--:::5:---"':L:""":O-"::G-:'I"""":::C-=C":""":H-:""A-:::"S-::OS"-I= S - - - - - - - - - - - - - - AI52010
06
A07
20 n
A14
38
LDGIC C_H_A_S_S",....I",....S_ _ _ _ _ _ _ _ _ _ _ __
-ATi)2-C)ZO ···------·o7--Ao7---14-0--ifI-=i--14
LUG 1 C CHASS IS
AI52030
02
A07
21 0
AOh
09
LOGIC CHASSIS
-ATs-z 110
04
All
3-6(--)-A-a H
13
LUG ICC HAS 5:;....,I:-":S...--------------AI52210
04
A07
24 0
All
32
L8GIC CHASSIS
AI52220
02
A07
32 0
AOt{
25
LOGIC CHASSIS
AI52230
03
A07
30 n AOt{
16
LOGIC CHASSIS
A-f523 U)-- -"(.i"6 AOB
29 0
A 11
12
LOG I C CHASS IS
AI~2320
11
AOH
2A [)
A2·(
38
LOGIC CHASSIS
AT52330
13
AO-8---30 (J
t321
3H
U1GIC CHASSIS
AI52331
03
A08
30 0
AOH
50
LOGIC CHASSIS
"IOTE5
A I ') 2 :3 40
07
A0 b
32 0
A1 7 --;--1-;::"3-~I~_(=.)(:-::-;I:;-:C;::---:C~H-:-A:-;S::-;S::-;I"S,,--- - - - - - - - - - - - - AI60010
11
AOH
41 0
Art
:12
lllGIC CHASSIS
-A-I nO () 20-- .- -- T2--AOH--4 4-0--I~ 2·'-- ~"2 - -- . Lr.1 Grl:l:"H AS s"-""rr7ArrS. . S
.. · . . , . I - - r S - - - - - - - - - - - - - - AK40010
03
A13
32 0
A14
13
LOGIC CHASSIS
A1<4 0 2 10
0 Z A 13
~0 U
A 14
·.,. . 1~2----,L......t~)G~l.....,C-.c...,.H'T'lA.....S...,.S..,l...,S....--------------AK40410
02
A13
12 n
A15
08
LOGIC CHASSIS

-n

4124·9000

B

9-9

LW70811900

LOGIC CHASSIS

AK40610

--AK406~0

05
03

AI({)()(.,l{)

()it

REVISION F

PAGE

4

A13
05 n
A15
41
LOGIC CHASSIS
A13----30--o-A 12 1:--:3::-----:L-:I.:--:
G-:-:,I=-:C=---:C::-H--:-A-;-S:::--:S~I=-S;-:-'- - - - - - - - - - - - - AK40-( 1 0
03
Al 3
40 n
A12
26
L () G ICC HAS SIS
-AI(40Hll)----------O~A12-----2S--r-)---A14--16
U)Grr---=-C~H'-A-=S=S""""I""'S-------------I~K41010
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05
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45

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LENGTH
04
02

oq
04
02
OR
04
02

09
05
02
0'3
05

02
08

05
02
07
06
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04
02
05
09
06

04
06

AIl~?lO
AI12~11

09
04

AI20010
AI20020
AI2allO
AI?')111
AI?0120
AI21S1U
AI21710
AI21RIO

07
OB
11
02

02
03

04

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A21
A21
A21
A21
A21
A21
A21
A2l
A21
A21
A21
A21
A21
A21
A21
A21
A21
A21
A21
A2l
A21
A21
A21
A21
A21
A21
A16
A16
Al6
A16
A16
A16
Alb
Al7
Al7
Al7
A17
Al7
Al8
Ala
A19

SIZE/COLOR

S, DESTINATION TITLE

ORIGIN

13 0
13 0

12 0
16 0
16 0

OS
1 (l
1';
CiS
14

14
09
33

33
32
30

0
0
0
0
0
0
0
0
0
0
0
0

30
4a 0
29 0
29 0
38 0
36 0

36
37
01
34
44
44
45

0
0
0
0
0

0

0
41 0

21 0
42 0
42 0
21 0
25 0

29 0
29 0
40 0

22 0
05 0
08 0

A25
A21
B?5
A25
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A25
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825
A27
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08
18
08
13
17
13
18
22
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08
21
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18
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13
45
13

25
29
02
38
38

28
44
44
02

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42
44
44
02
21
25
29

A25

24

LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
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LOGIC
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LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
lOGIC
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CH~5SIS

CHASSIS
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CHASSIS
CHASSIS
CHAC;SIS

NOTE 5
NOTE 5

CHA~SIS
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CHASSIS
CHASSIS
CHASSIS

NOTE 5

CHA~SIS
CHA~SIS

CHAC;SIS
CHAC;SIS
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CHASSIS
CHASSIS
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CHASSIS
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NOTE 5
NOTE 5
NOTE 5

CH~!o\SIS

CHASSIS
CHASSIS
CH,~SSIS

NOTE 5

CHAC;SIS
CHA5SIS
CHA~SIS

CHA<\SIS
CHflSSIS
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CHASSIS
CHASSIS
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CHASSIS
CHASSIS
CHASSIS

NOTE 5

NOTE 5

10 NO
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AI22110

~

AI2~310

I:\j

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AI22410
AI2?411
AI22510
A122$110

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0
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AI~3010

AI23210
A123310
A123410
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AI23430
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AI31310
AI32010
A132210
A133010
AI33020
AI33021
AI34S10
A134710
AI34711
A134910
AI36010

LENGTH

ORIGIN

06 A19
07 A19
03 A19
02 A19
07 A19
01 A19
03 A19
02 A19
09 A20
02 A20
02 A20
02 A20
02 A20
10 A20
10 A20
02 A20
10 A20
04 A20
04 A20
04 A20
04 A20
09 A20
02 A20
03 A20
04 A20
03 .A 19
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03 A08
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02 A10
02 AI0
02 A09
03 A09
11 A09
12 A09
03 A09
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06 A18
03 AI0
07 A18
02 A09

12
14
18
18
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DESTINATION TITLE

0
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A29
A20
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0
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34 0
08 0
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01 0
09 0
12 0
10 0
22 0
21 0
13 0
11 0
20 0
14 0
16 0
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29 0
37 0

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24
41
38
09
01
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0
0
0
0
0
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0
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28 0

29 0
29 0

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18
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26
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17 0
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38 0

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24
18
21
26
24
09
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50
41
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22
21
25

44
44

02
42
11
25

16
12

LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC,
LOGIC·
LOGIC
LOGIC
LOGIC
LOGIC'
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGICLOGIC
LOGIC
LOGIC
LOGIC

SIZE/COLOR
CHASSIS
CHASSIS
CHASSIS'
CHASSIS
CHASSIS
CHASSIS
CHASSISCHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS'
CHASSIS .'
CHASSIS
CHASSIS

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NOTE 5

CHA~SIS'

CHASSIS..CHASSIS
CHASSIS
CHASSIS
CH4SSIS
CHASSIS
CHASSIS
CHASSIS
CHAC;SIS
CHA<;SIS
CHASSIS
CHASSIS
CHAC:;SIS
CHAC;SIS

LOGIC'CHA~SIS

LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOG.IC

CHAC;SIS
CHA~SIS

CHASSIS
CHASSIS
CHASSIS
CHASSIS

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10 NO
co
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AI3f,020
AI36030
AI36040
AI36110
AI36120
AI36130
AI36140
A136210
AI36220
AI36230
AI36 R IO
AI3f,All
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AI40011
AI40020
AI40710
AI4(721)
AI4073('
AI40910
AI40911
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AI41011
4141210
AI4i211
AI41220
AI41221
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A14~710

AI5n910
AI50920
A150930
AISi310
AISi410

LENGTH
02
02
02
03

02
02
02
03
02
04

06
02
03
11
02
O~

05
03
04
03
04

05
03
04
04
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04

04
04
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04
03

03
04

0'.
04
04
04
02
05

04

ORIGIN
A09
A09
A09
A09
A09
A09
A09
A09
A09
A09
A09
A19

A09
A12
A12
A12
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A12
A12
A13
A12
A12
A12
All
A12
All
A12
All
All
A12
A13
A13
A12
A12
A12
A13
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A08
A08
All
All

S

SIZE/COLOR

DESTINATION TITLE

09 0 . AIO
12 0 AIO
17 0 AIO
20 0 AIO
24 0 AIO
32 0 AlO
36 0 A10
38 0 AIO
45 0 AIO
34 0 AIO
40 0 A19
32 0 A20
37 0 AOa
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'Os 0 Al2
08 0 A25
36 0 A08
37 0 A14
32 0 A07
21 0 A12
10 0 A08
09 0 A08
09 0 A13
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05 0 A12
41 0 Al3
01 0 A12
12 a A12
38 a A13
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20 0 A13
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22 0 Al3
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16 0 A12
18 a A12
17 0 A09
41 0 Ao1
2i 0 A01

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20
13
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22
36
33
45
40
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32
38

25
32
02
32
09
29
38'
10
20
21
24
40
13
41
17
34
38
09
17
29
08
01
18
13

17
12
14
09

25

LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC,
LOGIC
LOGIC,
LOGIC,
LOGIC·
LOGIC·
LOGIC
LOGIC·
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
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LOGIC
LOGIc
LOGIC
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CHASSIS
CHASSIS
CHASSIS
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CHASSIS
CHASSIS
CHASSIS
CHASSIS
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CHA5SIS
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LOGIC CHA~SIS
LOGIC CHAC;SIS

LOGIC CHAc;SIS

LOGIC CHASSIS
LOGIC CHA~SIS
LOGIc CHASSIS
LOGIC CHASSIS

ECO

NOTE 5

10 NO
AIS2010
AIS?020
AI52030
AIS2110
AIS2210
AIS2220
AIS2230
AISZ310
AIS2320
AIS2330
AIS2331
AIS2340
AI6QOIO
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AI62510
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AK30210
AK30410
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AK30blO

AK30RIO
AK3S010
AK40010
AK40210

LENGTH

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ORIGIN

06 A07
07 A07
02 Ao7
04 All·'
04 -A07
02 A07
03 A07
06 A08
11 A08
13 A08
03 A08
07 A08
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12 Ao8
05 Ao8
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04 A16
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04 A16
05 A16
06 A16
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07 A19
09 A20
04 A09
04 A09
03 A09
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04 A09
03 A09
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04 A13

20
14
21
36
24
32
'30
29
28
30

30

0
0
0
0
0
0
0
0
0
0
0

SIZE/COLOR

DESTINATION .TITLE
' A14
A17
- AOB
AOB

All

.AOS
. AOS
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32 0
41 '0
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26 0
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13 0 eOI
16 0 'SOI
12 0 BO\.
33 0 A21
25 0 A21
22 0 A21
12 0 A21
37 0 A21
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08 0 A21
28 0 A20
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40 0 829
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32 0 A.'5
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38
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17
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21
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20
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LOGIC
LOGIC
LOGIC,
LOGICLOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGICLOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC

CH4SSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
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CHA!=tSIS
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CHAC)SIS
CHA~SIS

CH~5SIS

CHl\SSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS

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NOTE 5

NOTE 5

co

10 NO

LENGTH

5

ORIGIN

SIZE/COLOR

DESTINATION TITLE

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1:\:1
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1:\:1
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AK40410
AK40blll
AK40b20
AK4071<'
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LOGIC
LOGIC
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CHA~SIS

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CHASSIS
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CHAC:;SIS
CHASSIS
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CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASS'IS
CHASSIS
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CHASSIS
CHA<;SIS
CHASSIS
CHASSIS
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10 NO

LENGTH

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ORIGIN

SIZE/COLOR

DESTINATJON TITLE

ECO

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0
0
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ATOO410
ATOO420
ATOOSIO
AToo520

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09
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ATOO~lO

07
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ATOOb20
ATOO710
AT00720
ATOOBIO
ATOOAll
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AT014I0
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02
08
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AY30111
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30 a
32 0

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B20
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38
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30
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02
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A24
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A26
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36 0
37 0
4i 0
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A26
A26
A28
A28
A26
A26
AIO
AIO
Ala

36 0

A}8

37 0
17 0

81B
Al8
A26
BIB
A';!6
A}8
A?6
8)B
A,;>6
A2B
A22

18 0
2S 0

26 0
3:)

a

32 0
36 0
37
42
. 41
41
42
28

a
0

0
0
0
0

26 0
·24 0

A18
B}8
A18
818
A]9

AlB
8}9

B~2

A26
AIO
AIO
AlO

09
·09

16
14
16
14
01

01
08

26
OB
32
44
37
44
42
50

33
33

So

26

24
08

LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIc
LOGIC
LOGIC
LOGIC
LOGIC

CHASSIS
CHAC)SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS·
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS·
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS

CHASSIS
CHASSIS
CHAC;SIS
CHAC;SIS
CHAC:;SIS
CHaSSIS
CHAC;SIS
CH~SSIS

CHA<;SIS
CHAC;SIS
CHA~SIS

CHAC;SIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS

NOTE 5
NOTE 5

10 NO
co
I

~

;n
w

0

AV3011 3
AY30114
AY32010
AY36010
AY40410
AYS1S10
AYSlS11
AV60110
AY60410
AY60411
8110010
8110011
8110020
BIIo110
8110111
8110120
8110210
8111)211
Bl11)221'
8 I 1 I) 3111
BIl1')311
8110320
BII041(\
BIln411
8110420
BI1051(\
811,511
8110520
8110010
B11n611
B110620
8110110
8I1n711
BIIo1cO
8110~qO

~
f-'o

I:\:J
~

co

0
0
0

~

B1l()910
BIljAlO
8Ill All
8111820
8112010
8112110

LENGTH
02
03

03
04

05
03
06
03
04
03

08
02
04
0$3
02
04
OR
02
04

09
02
05

ORIGIN
AlO
AI0
A09
A09
.A13
A08

All
A17
A08
All
821
821
821
821
821
821
821
821
821
821
821
821

In

821

02

821
821
821
821
821

05

09
02
05
10
02

821

R21

06
10

821

02
06
04
02
09
OS
10
04

821
821

816
816
A16
816

08

816

821
A21
821

2A
34
30
18
10
24
20
10
37

S

DESTINATION TITLE

0:
0
0
0
0 .
0
0
0 .
0

AIO
AIO
AIO
All
A07
All
Al8
A14
All
A14·
A25

40 0

13 0
13 0
12'0
16 0
16 0
08 0
II' 0
10 0
05 0
14 0
14 0
09 0
33 0
33 0
32 0
3;; 0
30 0
4'; 0
29 0
29 0
38 0
36 0
36 0

821

825
A25
921
925
A25
821

34
44
18
44
08
20
37
09
40
33
10
18

10
14
17
14

A27
821
827
A?7

20
22
20
10
21
10
14

B21

41

827
A27
821

14
20
42
20
10
44

B25

827

A29
B?l

829
A29

10

821

4S

31 0

829

OJ" 0
34 0

820

14
25
29
40

44'0

44 0

4S 0
4j 0
21 0

819
825
815
A25
812
A25

14

02

40
28
45

LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC,
LOGIC
LOGIC,
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC

SIZE/COLOR

ECO

CHAC)SIS
CHASSIS
CHA~SIS

CHASSIS
CHASSIS
CHA~SIS

CHASSIS
CHASSIS
CHASSIS
Ct:fASSIS
CHASSIS
CHASSIS
CHASSIS
CHAc)SIS
CHASSIS

NOTE ·5
NOTE 5

CHA~SIS

CHA~SIS

CHASSIS
CHASSIS
CHASSIS

NOTE 5

CHA~SIS

NOTE 5

CHASSIS
CHA!=!SIS
CHASSIS
CHAC;SIS
CH4SSIS
CHAC;SIS
CHASSIS
CHASSIS
CHA~SIS

CHA5SIS
CHASSIS
CHASSIS
CHAC;SIS
CHASSIS
CHAC:;SIS
CHASSIS
CHA~SIS
CHA~SIS

CHASSIS
CHASSIS

NOTE 5
NOTE 5
NOTE 5

NOTE 5

NOTE 5

~
I-'
C\j

~

co
0
0
0

c:...r

10 NO
B1l~210

8112211
BI20010
8120020
8120110
BI2t)111
8120120
Bl~ls10

BI21710
B121AI0
8122110
8122310

co
I

C\j

;n
CAl
I-'

LENGTH
07
04
07
09
08
03
02
03
04
07
08
08

BI2~410

03

8122411
8122510
BI22AI0
8123010
8123210
B123310
8123410
B121420
BI23430
8123440
BI23510
BI23610
8123710

02

BI?3 R IO

07
04
04
04
04
07
02
03
04
03
03
03

8I23910
8I21920
8I23930
BI23940
8124010
8I24110
8 I 2431 ()
8I24410
8124910
8125010
8125110
9130110
BI30910
8131310

10
11
02
o~

OS
02
02
02
02
06
07
02

04

02
02

S

ORIGIN
B16
BIb
811
B17
B17
817
817
818

B18
B19
B19
819
819
B19
819
B19
B19
819
820
820
820
A20
820
820

820
B20
820
820
820
820

820
820
820
A20
A20
819
R20

B08
B10
Bl0

B10

42 0
42 0

825
816
21 O. BOB
25 0 A29
29 0 B29
29 0 B17'
40 0 B17
22 0 B20
05 0 B19
08 0 A25'
12 0 A27
14 0 A29
18 0 B20
18 0 B19
40 0 A29
42 0 A29
2i 0 B18
34 0 820
08 0 B25
05 0 819
oi 0 819
09 0 819
12 0 B19
If) 0
B21
22 0 Bi?9
21 0 819
13 0 829
17 0 819
20 0 819
14 0 819
16 0 819
19 0 829
29 0 819
37 0 919
45 0 919
.24·0 8j7
4i 0 B17
38 0 B09
09 0 809
. 01 0 B09

21

0

SIZE/COLOR

DESTINATION TITLE

B11

45

02
42
45

45
02
21
25
29
25
25
33

32
02
25
20
21
26
25
09

10
05
17
25

33
30
25

37
38
36
41
20

2\
26
13
28
30
50
41

05
22

LOGIC
LOGIC
LOGIC
LOGIC'
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC·
LOGIC
LOGIC
LOGIC
LOGIC'
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC

CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS',
CHASSIS"
CHASSIS
CHASSIS,
CHASSIS

ECO
NOTE 5

NOTE 5

CHA~SIS'

CHASSIS.
CHASSIS;
CHASSIS
CHA5SIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHAC;SIS
CHAc;SIS
CHA~SIS

CHASSIS
CHASSIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHAc;SIS
CHASSIS
CHA<;SIS
CHASSIS
CHhSSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS

NOTE 5 .

10 NO
co

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w
I:\:l

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.......

I:\:l
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co
0
0
0

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8132010
813~210

8133010
8133020
8133021
8134510
BI34710
8134711
8134910
8136010
8136020
8136030
8136040
8136110
8136120
BI36130
813"140
8136210
8136220
811f,230
BI36AIO
8136 All
6131)A20
B14f)01O
6140011
8140020
8I4071fl
B!4n720
8140730
8140910
814:1911
Bt41010
814}011
BI41210
8141211
8I4]220
8I4i221
BI4}310
814i510
8141511
8141710

LENGTH

ORIGIN

02 809
03 809
12 809
11 809
03· 809
06 818
06 818
03 B10
07 818
02 809
02 809
02 B09
02 809
03 809
02 809
02 809
02 809
02 809
02 809
04 809
07 809
02 819
03 809
09 B12
02 812
09 B12
05 FH2
03 812
04 A12
03 A13
812
04
05 812
03 812
A11
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04 912
05 811
04 B12
04 Bll
04 All
04 B12
04 B13

5

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44
28
29
29
38
16

0 ' 810
0

a
a

0
0

0
17 0
41 0

01
09
12
17
20
24
32
36
38
45
34
40
32
37
OS

os

08
36
37
32
21
10
09
09
08
40
05
'+1

0

0
0
0

a

0

810
A27
827'
809
B09,'
810
Bo9
B09
BI0
810
810
810
810
BI0 ..

0

B10

0
0
0

810
810

a
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0

0

0
01 0
12 0
38 0
45 0

SIZE/COLOR

DESTINATION TITLE

8]0
BI0
B19
820
B08
825
812
A25
B08
814
8n7
B12
BoB
B08
B13
812
8}3
812
B13
8}2
812
813

B11

LOGIC'
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
17 '.. LOGIC
LOGIC
25
LOGIC
16
LOGIC
12
LOGIC,
05
LOGIC
20
LOGIC·
13
LOGIC
29
LOGIC
22 '
LOGIC
36
LOGIC
33
LOGIC
45
LOGIC
40
LOGIC
14
LOGIC
32
LOGIC
38
LOGIC
25
33
LOGIC
LOGIC
02
LOGIC
33
LOGIC
09
LOGIC
29
LOGIC
38
LOGIC
10
LOGIC
20
LOGIC
21
LOGIC
24
LOGIC
40
LO(;IC
13
LOGIC
41
LOGIC
11
34
. LOGIC
38
LOGIC
09
LOGIC
17'
LOGIC
21
25
45
45
02
42 ..

CHASSIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS

ECO

NOTE 5

CHA~SIS

CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHA~SIS

CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA!-;SIS
CHASSIS
CHAC;SIS
CHA~SlS

CHASSIS
CHASSIS
CHAC;SIS
CHASSIS
CHASSIS
CHA~SIS

CHA<;SIS
CHtt~SIS

CHASSIS
CHASSIS
CHA~SIS
CHA~SIS

CHASSIS
CHASSIS
CHASSIS
CHASSIS

NOrE 5

10 NO

S

ORIGIN

LENGTH

SIZE/COLOR

DESTINATION'TITLE

ECO

I.J::>.
I-"
l.\j

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0
0
0

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812
B12

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22

A13

42

8152210
BI5:??20
8152230

04
04
04
02
05
04
06
07
03
04
04
03
03

BIS~310

Or,

BI5?320
BI5<331
B152331
BIS?3<+')
816(')010

12
11

0-

8142210
B14~220

B14?230
8142710
8150910
8150920
8150930
8151310
8151410
BI5?010
BI5~020

8152030
8I5~110

03

07
12
11
05

BI~o02r)

9160021

BI6n210
8161)61 0
8161210
8162210

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05
05

,

816~31n

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816;>410
BI6;>C;lO

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BKIOO1O
8 K10210

04
04
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41 0

03
03
04

BI41~10

8 KI0610

BKloRlO
8 KIIOIO
BK11210
8Kl141C
BK20210

•

05

04
04
05

2~

AOB

16

B08

18

B08
811
Bl1
R07
So7
807

17
41

2i
20
14
21
36

0
0
0
0
0
0
0
0

0
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Bl1
8)3
813
813
Bl1
B12

B12
B09
B07
B07
814

0
0
0

B17
B08
B08

B07
807
807
B08
B08
BoB
BoB
AoB
808

Z4 0
32 0

B11

8n8

44 0

Bn8
808
817
A27
B27
B08
B17
A27
B?7

B09

44 0

oi 0

807

815
A15
B17
B14
B14
814
814
816
B16

811

B16
B16

816
816

06

B16
816

03

819

30 0
29 0
28 a
30 0

30

0

32 0
41 0

26 0
22 0
05
13
16
12
33

25
22
12
37
29

0
0
0
0
0

0
0
0
0
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18 0
08 0
28 0

B08
B08

Bl1
B11
1\0'
AO~

AC;> "

821
821
821
B21
821

29
08
01
18
13
17

12
14
09
25
38
14
09
13

32
2S

16
12
40
40
50
13
33
33
02
33
40
36
44

-z2

24

2'18
17
22
21

821

41
42

821

44

821
820

45
44

LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
lOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC

CHA5SIS
CHAC;SIS
CHAc;SIS
CHAC;SIS
CHASSIS
CHA~SIS

CHASSIS
CHASSIS
CHASSIS
CH445SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS

CHASSIS
CHASSIS
CHASSIS
CHAc;SIS
CHASSIS
CHA"SIS
CHASSIS
CHASSIS
CHASSIS
CHA~S1S

CH"c;SIS
CHAc)SIS
CHAC:;SIS
CH4c.;SIS
CHI\SSIS
CHA~SIS

CHA5SIS
CHAC;SIS
CHASSIS
CHAC;SIS
CHASSIS
CHAC;SIS
CHA~SIS

CHASSIS
CHASSIS
CHASSIS

NOTE 5

NOTE 5

co

10 NO

LENGTH

ORIGIN

I

~

O':l

w

.,j:::.

8K20310
8K20510
8K30010
BK30210
BK30410
BK31)b10
BK30AIO
BK3S010
81<40010
BK4 0210
81(41)410
8K40610
8K40620
BK40710
BK40AIO
BK41010
8K41210
BK41410
BK50010
81(50020
8KSOl)30
8'<50210
BKS0211
8K5f')212
8 K 50310
BK50311
BKS0610
8 K50620
BK5a710
BKC;O~:qO

BKS0910
BK51110
BK51120

....

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co
0
0
0

<:...t

8~6f)OlO

8K 6 ') 21

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BK60410
BK6ntliO

BK6QRI0
8K6}010
BK6i210
BK6l410

819
A20
809
A09
809
809
809
809
04 813
04- 813
02 B13
05 813
03 813
03 813
04 812
04 B12
04 R12
04 812
03 814
05 814
II R14
04 807
04 All
04 A13
02 801
os 808
04 A07
04 807
05 R07
05 807
os 801
02 Bl1
03 B1l
04 815
02 A15
03 815
04 815
04 815
03 817
08
06
04
04
03
05
04
03

os
04

817
817

S

SIZE/COLOR

DESTINATION TITLE

22 0 . A29

CHA!;SIS

40
10
08
14
33
22
13
32

CHA~SIS

20
12
05
3';

40

25
17.
12
01
28

25
14
10
16
34
12
05
26
33
36

42
46
32
31

ns

18
08
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In
36
37
11

0
0

0
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0
0
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0
0
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0
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0
0
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0
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LOGIC
40
LOGIC
40
B29
LOGIC
32
813
LOGIC
B}3
20
LOGIC·
12
B13
LOGIC'
05
B13
B12
25 '" LOGIC
LOGIC
32
810
LOGIC
B15 _, Q5.
LOGIC·
815
18
LOGIC'
08
815
LOGIC
41
B15
13 .. LOGIC
B12
LOGIC
26
B12.
LOGIC
10
Bis'
LOGIC
29
B}6
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28
B14
LOGIC
816
08
LOGIC
18
B16
LOGIC
BoB
14
LOGIC
20
AOJ
LOGIC
16
Bl1
LOGIC
34
B13
LOGIC
42
Bl1
LOGIC
B08
05
LOGIC
28
813
LOGIC
14
811
LOGIC
808
13
LOGIC
09
Bll
LOGIC
811
13
LOGIC
Bl1
10
LOGIC
31
812
50
LOGIC
All
LOGIC
816
33
8;6
LOGIC
25
LOGIC
916
22
8}6
LOGIC
12
8}6
37
LOGIC
ai4
LOGIC
21
33
LOGIC
Bl1
LOGIC
814
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CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA!;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS'
CHASSIS
CHAc)SIS
CHASSIS
CHASSIS
CHA~SIS

CH4SSIS
CHf\SSIS
CHASSIS
CHA')SIS
CHASSIS
CHASSIS
CHASSIS
CHAC;SIS
CHA5SlS
CHA~SIS

CHAC;SIS
CHASSIS
CHA!;SIS
CHASSIS
CHI\C;SIS
CHAC:;SIS
CHASSIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS

ECO

..p..
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co
0
0
0

C-t

10 NO
BK6I R IO
8K62010
8TOOOI0
8100020
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0404910
0405010
0405110
0405210
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0405510
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0500110
0500210
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IJ201 46
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IJ201 47
IJ201 50
IJ201 58
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A29
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IIJ2001a
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t--ID_C_NT_,-+_N_O,-+_IR_EF_._,_t_IR-E-F.I_+(-A-PP-RD-XJ- ----O-RI-O-IN.,---ll FIND NO. ~ . DE STI NATION
fiND NO.
ll
1
26 7
t-_ _ _-t-0_
268
J204
20 ~ 9
tiTU203
4
j 15
t-2-6-9---t-~*~--t~'~-t-~--t----~T-B-2-0-3--+-7--~-15 r:J-2-0-4-----t-2-8~~1-9--+----------------""'i

_+_-1-6~-4-_+_-~J-T-U-2-0-3--+-3_, J!~~J20~-----I-1-8-i11'-9-_+---------_-_""'i

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270
271

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29
3

272

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274
275

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21.

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-

-

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22

28

16,17

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NO.

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J204

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66

23
24
25

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16

13

A4J205

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26

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27
41

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21

45

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29,30

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826

5
46

32
29,30

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29,30

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6
6

32

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7
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7

29.30
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66
67

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6
8

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8
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48
29,30

70

TB203

9

15@ A23

71

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29.30

9

32

72
73

T8203
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9
1<48

15 ~.o A10
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TB203

B17
TB203

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OAUOE
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11

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COLOR
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78

J"

79
80
-

81 - _.

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--

92

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13

T8203

16

15@

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36

27

A3TB202

6

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TB203

6
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85
86

A05
A05

48 29 .I 3~1 TB203
6 . 29,30~TB203

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It

T8203

88
89

11

20

4

A26
T8203

90

12

24

4

A3TBZO-4

92
93
9<4
95

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'ORM AAI6"

9-50.2

48 29 30 T8201
10 @ 826
1

24

...

22

J204

10

----

6

IIJ202
J20<4
DJ202

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50

14 i. J204
13 ~~IJ202
14 J20<4

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29.30

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;

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ACCESS.
FINO NO.

83
B4

87

1

SHEET

MINNEAPOUS. MINNESOTA
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NO.
IDENT.

liE MARKS

29 30
32

829
T8203

68
69

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OF

ACCESS.
FIND NO.

DESTINATION

TB203

I.

'

SHEET.5

61
62

7<4
75

DDtuM'OT

729)'71100

MINNEAPOUS. MINNESOTA
CONOUCTOR FINO
IDENT.
NO.

I

.

WL

WI~E LISTING

1<4

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0

'-

22

41249000

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DOCUMENT NO.

TITLE

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l

WL

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MINN~APOLIS.

MI:>INI!SOTA

CONDUCTOR FINO
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NO.

96
97

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(REF.)

COLOR
(REF.)

24

12
;4

~

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t

70

A3J205

39 I

1

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100

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101

68

102

4
45

7

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37

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104

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108

I

J204

15

J206

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J204

27

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109

~

110

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111

~

112

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14

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24

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11

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20

20
22

~

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37

~

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45 1\16 17

[j

A3J205

47

'i

Ij

20

DOCUMENT NO.

TIT I.E

\.

GAUGE
(REF. )

WL

WIRE LISTING

COLOR
(REF.)

'-

. 24

4

~~

~1.

LENGTH
(APPROXJ

116
;

67 ~

87

118

-

120

.

SHEET
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ORIGIN

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r-;o

A3J205

50

All

16

A3J205

52~~1

'1

,

119

A14

42

~J16, 17

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20

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A14

36 ~ 6,17

I

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ir

~ ACCESS.
FIND NO.

A14

8

16,17

A3J205

51

20

A14

20 1,16.17

j

A3J205

53

A14

37[16,17

A3J205

55

A15

42 16,17

A3J205

56

A15

45

~'6, 17

t1 A3J205

57

A3J205

58

II

rj

A 15

9 rP6,17

A3J205

59 11-;-0

I A15

20

29!~

124
125

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60

i

126

A15

13

~16, '7~iA3J205

A3J205

63

fj

127

Ii

128

U A15

129

1

no

133

,

A15

.1,

w

11

R

12

A3J205

24

4

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20:

40!~j

24~16,17
62(-'-20

A 15

22~16, 17

A3J205

64

~

20

33 16,17

20 t1 A 15

14~16,17 ij

A3J205

66

67 fi

20

A 15

28 1)16 17

34

A3J205

71'

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20

I

REMARKS

20

65[1

A3J205
A15

,A

8 OF'

20

121

123

72971100

~.sY:...

20

122

131
132

REMARKS

FIND NO.

-

1

:j~I;_J3..~4

A3J205

~~

115

Ii

"

All

MINNt!APOLIS. MINNt!SOTA
CONDUCTOR FINO
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NO.

26

A3J2QLAU
A3J205

~

r

l

~i16,
17
... ~

I
4'

24

12

t~1

liIi

113

114

A8

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!1

20

A

OF'

~I~~, ___ ~~i'6.'7

J204

103

106
107

II A4TP201

J204

'4

7297/100
7

WlU'll ACCESS.
DESTINATION

I!

98

105

fi-='

-- f~~ J204

A3TP201

99

ACCESS.

II FINO NO. ,1

ORIGIN

4

J.\

-

-; -a

LENGTH
(APPROXJil

SHEET

I-R~

20

A3J205

70~

A15

12 16,17

.

20

FORN A"'GG!I

41249000 C

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TITLE

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WIRE LISTING

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IDENT.
NO.

134

GAUGE
(REF.)

12

24

I'

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COLOR
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136

LENGTH
(APPAOXJ

r'E

j~

-

--

ACCESS,
• FIND NO,

~ 16,171 A3J205
73 I 20 ' A15
I!

72

20

20

16,17

~15

38 IP6,17, A3J205

74

20

137
138
139

A3J205
A15

75 t! 20
16 (16,17

36
76

16.17
20

A3J205

77

A15
A3J205
A15

17

16,17

140
141

A15
A4J205

25
39

16,17 II A3J205
20 188

78

142

87

13 ,,16,17

20
I

143
144

A4J205
A4J205

145

I
Ij

146

Ii A4J205

147
148

811
A4J205

88

;~

!

149

814

,I,

150
151

12

152

A4J205

4 .

24

! 817
A4J205

24
26

I

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1
28

rl

iJ,

20 llA4TB204

30 i16, 17

i

50
20P 614
16 ~16, 17 ~ A4J205
52
814

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-==-~ ACCESS,

7

153
154

12

24

~ MJ205

381~IB11
1 116,171' A4J205

MINNI!APOLIS. MINNESOTA

GAUGE
(REF.)

COLOR
(REF_)

LENGTH
(APPROXJ',

ORIOIN

814
A4J205

4

FIND NO.

42"~
54

20

36

16,17

A4J205

156

A4J205

56

157
158

815
A4J205

45 ~71 A4J205
58 ~ 20 n 815

159
160

815
A4J205

60

161

815

13

162
163

A4J205
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164

I

~

Ii

165

A4J205
B15

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il

12

24

20
16,17

47

20

8
51

16.17
20
16,17

4

~ A4J205

!~r A4J20S

63 ~-1f-,1.B15
40 II 16 ,~1 7 11" A4J205

I'

65
to
14 th6,17

SHEET
ACCESS.
FIND NO.

53
37
55

20 tl815

~~

I

10

OF

REMARKS

20
16,17

57
9

20
16,17

59
24

20
16,17

62

20

!-.2
64

16.17
20
- -.

28
70

815
A4J205

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20

815

67
34

A4J205

71 M 20 11 615

12 _16,17

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73 t~815
38 ~16,17 i A4J205

72

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33 11~, 17
66
20

II A4J205

11 16 ,17 11

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DOCUMENT NO.

20
16,17

42

--

Ii 615

I

WL 72..97/100

-

20 l815

29116, 17

h

166
167

171

22

DESTINATION

814

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170

1.,

37
45

20

lG
MJ205
814

155

20 -_._20
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16,17

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IDENT.
NO.

23

d

TITLE

1

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REMARKS

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21.

A3J205

,

I

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ORIOIN

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4

135

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214

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4

5

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7

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210

r

215
216

21

20

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21

20

218

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220

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CODE IDENT

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NO

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DOCUMENT NO.

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221

21

20

4

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4

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11

222

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11

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224
225
226
227
228
229
230
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243
244
245
246
247
248
249

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20

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NORMANOALE DIVISION

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I

CODE IDENT

19333

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263
264
265
266
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269
270
271

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294
295

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302
303
304

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311
312
313
314
315
316
317
318
319
320

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CODE IDENT

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357
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359
360

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NORMANDALE DIVISION

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(REF.)

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I

CODE IDENT

19333

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362

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12

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6

57

363

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12

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56

364

12

11

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53

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51
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366

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16

56

368

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5

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371

1

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372

52

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4

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373

54

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4

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58

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374
375
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1

379

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380

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41249000 F

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1

CODE IDENT

19333

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I

ACCESS

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I 7.32 /7~t!Jt:J Ie6DI /l
DOCUMENT NO.

SHEET

381
382
383

93

384

77

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385

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71.78

386

27

20

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3

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396

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41

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41

397

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398

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CODE IDENT

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lENGTH

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NO

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27

20

4

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41

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41

402

27

20

4

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43

403

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20

4

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415

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16

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18

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1

3

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REMARKS

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&

404
405
406
407
408
409
410
411
412
413
414

•

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417
418

t

419
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J

CODE IDENT

19333

DOCUMENT NO.

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23

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16

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19

8
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19

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424
425
426

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437
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441

15

16

4

442

J

,

443

4461

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447

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!

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15

I

CODE IDENT

19333

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DOCUMENT NO

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24

SHEET

ACCESS
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14 12

DESTINATION

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7

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13

4

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9

13

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5

C33

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13

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4

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13

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5

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9

13

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5

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13

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7

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445

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444

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71

76

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455
456
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NOTES:

1.

CO~tPONENTS

T06, l02 • • L03 USE EXISTING

LEADS.

"ME" DES IGNATE'i CONNECTION NEAR THE HDUNTED
END.

2.

FOR FN REFERENCE IN CONDUCTORS 1 THRU 55
SEE PL 40017800. D. C. PANEL HARNESS.

~IOUNTED

3.

FOR FN REFERENCED tN CONDUCTORS 77 THRU
148 SEE PL 70820900. A.C. HARNESS.

4.

FOR FN REFERENCED IN CONDUCTORS 153
THRU )S6 SEE PL 70723900. D.C. HARNESS.

5.

FOR FN REFERENCED IN CONDUCTORS 362
THRU 373 SEE PL 40011800. 01. MISC
D. C. PANEL.

6.

FOR FN REFERENCED IN CONOUCTORS
THRU 385 AND 456 THRU 461 SEE PL 70814101.
POWER SUPPLY ASST.

7.

A HEXAGON IN THE ACCESS FN COLUMN INDICATES
THAT THE CONDUCTOR IS ONE OF SEVERAL (ALL
WITH THE SAME NUM8ER IN THE HEXAGON) GOING
INTO THE SAME TERMINAL. THE NUM8ER IN
FRONT OF A HEXAGO. IS THE TERMI NAL FN.

••

FOR FN REFERENCED IN CONDUCTORS 386 THRU
403 SEE PL 70708100; FRONT PANEL ASSY.

,.

FOR FN REFERENCED IN CONDUCTOAS 415 THRU
435 SEE PL 70820100; A. C. PANEL ASST.

11.

FOR FN REFERENCED IN CONDUCTORS 440 THRU
451 SEE PL 70807i00, D.C. RELAY PANEL ASSY.

9-124

14.

=g~ ~~ER~rE,~~s~roA~ S~~DH~!~R1E~U

•

TERMINAL BOARD ASSY,

NOT '!N HARNESS.
110.

fOR fN REfERENCE IN CONDUCTORS .... S THROUGH
..67 SEE PL 7072'1600\ HG RELAY HARNESS ASSY.
fOR fN REfUENCE IN CONDUCTORS '1'2 THROUGH
SOl UE PL 70n0101\ COnpONENT n" AISV.

37"

10.

au ...

"OME" DESI GNATES CONNECTION OPPOSITE THE
END.

J.&.

FOR FIND HOAS REfERENCED IN CONDUCTORS
SiS THRU 5~~ SEE PL 73121100; SOFT
START HARNESS ASSV. .

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9-125

COMMENT SH'EET
MANUAL TITLE _C_O_N_T_R_O_L_D_A_T_A_B_M_1_0_1_A_ND
__
B_M-1-0_3_ _ _ _ _ _ _ __

Multiple disk drive Customer Engineering Manual
41249000

PUBLICATION NO. _ _ _ _ _ _ _ _ __

FROM:

REVISION _-_.....;;~___
-__

NAME: ________________________________________________________
BUSINESS
ADDRESS: _____________________________________________________

COMMENTS:
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