60043800D_3200_Computer_System_Ref Man_Aug65 60043800D 3200 Computer System Ref Man Aug65
60043800D_3200_Computer_System_RefMan_Aug65 60043800D_3200_Computer_System_RefMan_Aug65
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COM PUTER SYSTEM
REFERENCE MAN UAL
CONTROL DATA
CORPORATION
3200 CHARACTERISTICS
• Stored-program, solid-state, general-purpose computer.
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Diode logic.
Parallel mode of operation.
Single address logic.
Programmed inter-register transfers.
Address modification (indexing).
Indirect addressing.
Character and word addressing (4 characters per word).
28-bit storage word (24 data bits and 4 parity bits).
Nonvolatile magnetic core storage. Standard memory: 8,192 words/32,768 characters.
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Selected storage protection.
Storage sharing.
Complete cycle time: 1.25 microseconds.
Access time: 0.75 microsecond.
24-bit accumulator register and auxiliary-accumulator register.
Binary arithmetic: 224_1 modulus, one's complement for all single precision (24-bit) operations and
double precision (48-bit) addition and subtraction.
Instruction repertoire compatible with the 3100 and 3300 Computers.
Trapped instruction processing: executes double precision multiplication and division, floating
point, binary coded decimal (BCD) and an optional register transfer instruction if optional arithmetic logic is not present in a system.
64-word register file (0.5 microsecond cycle time)
Complete interrupt system.
Block control operations.
Logical and sensing operations.
Masked storage searches.
Three 15-bit index registers.
Real-time clock (1.0 millisecond incrementation).
Sit-down operator's console featuring:
• Octal register displays.
• Internal and external status displays.
• Instruction step control.
• Breakpoint thumbwheel control.
• Auto step control.
• Auto Load.
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• Auto Dump.
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• Detachable keyboard for manual entry and control of the computer.
Standard 3000 Series type 12-bit bidirectional data channel.
Data transfer rate up to 10 megabits/second.
Compatible I/O mediums include magnetic tape, disk file, punched cards, paper tape and printed
forms.
Options include:
• Memory expansion to 16,384 or 32,768 words.
• Additional 12-bit data channels or high-speed 24-bit data channels.
• Floating point and 48-bit precision multiply and divide hardware logic.
• BCD arithmetic hardware logic.
• On-line I/O monitor typewriter.
• Complete selection of peripheral equipment.
COM PUTER SYSTEM
REFERENCE MANUAL
CONTROL DATA
CORPORATION
60043800
Record of Revisions
REVISION
NOTES
B
Obsoletes all previous editio,ns
C
Minor corrections only
D
Obsoletes all previous editions
Pub. No. 60043800
August 1965
©1965, Control Data Corporation
Printed in the United States of America
Address comments concerning this manual to:
Control Data Corporation
Technical Publications Department
4201 North Lexington Avenue
St. Paul, Minnesota 55112
Or use Comment Sheet in back of this manual.
CONTENTS
Section 1.
SYSTEM DESCRIPTION
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1
COMPUTER MODULARITY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Main Control and Arithmetic Module ......................................... ,. . ..
Block Control and Interrupt Module. .... .... ..... . . .. . . ............ . .. .. . ... . .....
Storage Module ................................... ,. . ............. ...... ........
Input/Output Sub-Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Optional Arithmetic Module ..... , .............................. , ..... , ...........
Console. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Input/Output Typewriter ....................................... , ..... , ..... . .. . ..
Power Control Panel ............ , . .. ... . . . . .. .. .. . ...... . .. .. . .. ..... .. .... . .. ...
1-1
1-3
1-3
1-3
1-3
1-4
1-4
1-4
1-4
3200 PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-6
COMPUTER ORGANIZATION .......................................................
Computer Word Format..........................................................
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Bus and {S' Bus .............................................................
Block Control ...................................................................
Real-Time Clock .................................................................
Parity ..........................................................................
1-6
1-6
1-6
1-10
1-10
1-12
1-12
PERIPHERAL EQUIPMENT ........................................................ 1-13
Section 2.
STORAGE CHARACTERISTICS
STORAGE MODULE CONTROL PANEL. . . . . . .. . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
STORAGE REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
S Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
Z Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
READ/WRITE CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Single-Character Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Double-Character Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Triple-Character Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Full-Word Mode .................................................................
Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-2
2-2
2-2
2-2
2-2
2-2
STORAGE ADDRESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
STORAGE SHARING. . . . . . . . . . . . . .. . . . .. . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
STORAGE PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Permanent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Selective Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
No Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Section 3.
2-3
2-4
2-4
2-4
INPUT/OUTPUT CHARACTERISTICS
INTERFACE SIGNALS ............................................................. 3-1
I/O PARITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
Parity Checking with the 3206 ................................................. " 3-2
Parity Checking with the 3207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
III
AUTO LOAD/AUTO DUMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Preliminary Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Auto Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Auto Dump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-3
3-3
3-3
3-3
SATELLITE CONFIGURATIONS .................................................... 3-5
Section 4.
INTERRUPT SYSTEM
GENERAL INFORMATION. . . . . . .. . .. .. .. . .. .. .. .. .. . .. .. . .. . .. .. .. .. .. .. . .. .. . .... 4-1
INTERRUPT CONDITIONS. . . . . .. . .. .. .. .. .. .. . .. .. .. .. .. .. .. . .. . .. .. .. .. . .. .. .. ...
Internal Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Trapped Instruction Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Failure Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
I/O Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-1
4-1
4-2
4-2
4-3
INTERRUPT MASK REGISTER. . . . . .. . . . .. . .. .. .. .. .. . .. . . .. .. .. . .. . .. .. .. .. .. .. ... 4-3
INTERRUPT CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Enabling or Disabling Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interrupt Priority ...............................................................
Sensing Interrupts ...............................................................
Clearing Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-3
4-4
4-4
4-4
4-4
INTERRUPT PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
Section 5. CONSOLES AND POWER CONTROL PANEL
CONSOLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Register Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Console Loudspeaker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Status Indicators ................................................................
Swi tches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-1
5-1
5-4
5-4
5-7
POWER CONTROL PANEL ......................................................... 5-15
Switches ........................................................................ 5-15
Elapsed Time Meters ............................................................ 5-15
Section 6.
TYPEWRITER
DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1
OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Set Tabs, Margins, and Spacing ..................................... , .............
Clear ...........................................................................
Status Checking ........................................................... '.' . ..
Type In and Type Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Type Out and Type Dump ........................................................
6-2
6-2
6-2
6-2
6-3
6-3
CONSOLE SWITCHES AND INDICATORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
CHARACTER CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-5
Section 7.
INSTRUCTIONS
GENERAL INFORMATION. . . . . .. .. . . .. .. . .. .. .. . . . .. .. .. .. . . .. . .. .. .. .. .. . .. .. ....
Instruction Word Formats .................... " ..................................
Word Addresses vs. Character Addresses ................ , ..........................
Symbol Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Indexing and Address Modification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iv
7-1
7-1
7-2
7-3
7-3
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-4
Indexing and Addressing Mode Examples ....................................... ~ .. 7-5
Trapped Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-6
INSTRUCTION LIST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-7
Register Operations without Storage Reference ..................................... 7-12
Load ........................................................................... 7-20
Store ........................................... , ............................. 7-23
Inter-register Transfer, 24-bit Precision .......................................... 7-26
Inter-register Transfer, 48-bit Precision .......................................... '7-29
Stops and Jumps ................................................................ 7-30
Logical Instructions with Storage Reference ....................................... 7.37
Arithmetic, Fixed Point, 24-bit Precision .......................................... 7-38
Arithmetic, Fixed Point, 48-bitPrecision .......................................... 7-40
Trapped Instructions if Arithmetic Option is Not Present ........................... 7-42
Arithmetic, Floating Point ....................................................... 7-43
Trapped Instructions if FP/DP Arithmetic Option is Not Present ..................... 7-43
BCD ........................................................................... 7-46
Trapped Instruction if BCD Arithmetic Option is Not Present ........................ 7-46
Storage Shift, Searches, Compare and Register Shifts ............................... 7-50
Search .......................................................................... 7-56
Move ........................................................................... 7-58
Sensing ........................................................................ 7-60
Control ........................................................................ 7-63
Interrupt ....................................................................... 7-65
Input/Output .................................................................... 7-68
Section 8.
SOFTWARE SYSTEMS
GENERAL DESCRIPTION. . . . . . . . . . . . . . . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ...
3100, 3200, 3300 SCOPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3100,3200,3300 COMPASS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3100,3200,3300 Data Processing Package .......................................
3100,3200,3300 Utility .........................................................
3100, 3200, 3300 COBOL ..................................... '.' . . . . . . . . . . . . . . . ..
3100, 3200, 3300 FORTRAN. . . . . . . . . .. .. .. .. . . . .. .. .. .. .. . . .. .. .. .. . .. .. .. .. ....
Generalized Sort/Merge Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3100,3200,3300 BASIC System ..................................................
8-1
8-1
8-2
8-3
8-4
8-4
8-5
8-5
8-6
CODING PROCEDURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-7
Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-7
Pseudo-Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-9
Assembly Listing Format ........................................................ 8-17
Error Codes .................................................................... 8-18
APPENDIX A-Control Data 3100, 3200, 3300 Computer Systems Character Set
B - Supplementary Arithmetic Information
C - Programming Reference Tables and Conversion Information
GLOSSARY, INSTRUCTION TABLES AND INDEX
v
FIGURES
FIGURE
1-1 Typical 3200 Modular Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
1-2 3200 Console. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
1-3 Computer Word Character Positions and Bit Assignments. . . . . .... .. ....... ........ 1-6
1-4 Storage Addressing and Data Paths of Typical Installation .......................... 1-10
1-5 Block Control Scanning Pattern .................................................. 1-12
1-6 Parity Bit Assignments .......................................................... 1-13
2-1 Storage Module Control'Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
3-1 Principal Signals Between I/O Channel and External Equipment .................... 3-1
3-2 Satellite Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-4
5-1 Front View of 3200 Console Controls. . . . . . . . . . . . . . . . . . . . .. ....................... 5-2
5-2 EU EL Register Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
5-3 ED Register Display ................................................. , . . . . . . . . . .. 5-3
5-4 External Status Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4
5-5 Internal Status Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-5
5-6 Temperature Warning Designations for an Expanded 3200 Computer, Front View .... 5-6
5-7 Console Keyboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-8
5-8 Breakpoint Switch Examples .................................................... 5-13
5-9 Power Control Panel ............................... , ............................ 5-16
6-1 3192 Console Typewriter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1
6-2 Typewriter Control Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
7-1 Word-Addressed Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-1
7-2 Character-Addressed Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-2
7-3 Indexing and Indirect Addressing Routine Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-3
7-4 Operand Formats and Bit Allocations for MUAQ and DVAQ Instructions ............ 7-41
7-5 Operand Formats and Bit Allocations for Floating Point Arithmetic Instructions ..... 7-45
7-6 Search Operation .............................................................. 7-57
7-7 Move Instruction ............................................................... 7-59
7-8 73 I/O Operation with Storage ................................................... 7-73
7-9 741/0 Operation with Storage ................................................... 7-75
7-10751/0 Operation with Storage ................................................... 7-77
7-11 761/0 Operation with Storage ................................................... 7-79
7-12731/0 Operation with A ......................................................... 7-81
7-13741/0 Operation with A ......................................................... 7-83
7-1475 I/O Operation with A ........................................................ 7-85
7-1576 I/O Operation with A ........................................................ 7-87
8-1 COMPASS Coding Form ........................................................ 8-19
8-2 FORTRAN Coding Form ........................................................ 8-19
VI
TABLES
TABLE
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
4-1
4-2
4-3
5-1
5-2
5-3
6-1
6-2
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
8-1
8-2
Optional Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
Characteristics of 3200 Computer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
Register File Assignments ....................................................... 1-11
Buffer Groups .................................................................. 1-11
Absolute Addresses ............................................................. 2-3
Auto LoadlAuto Dump Reserved Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
Storage Protection Switch Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
Storage Protection Switch Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
Interrupt Mask Register Bit Assignments ......................................... 4-3
Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
Representative Interrupt Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
Keyboard Switch Functions ..................................................... 5-9
Console Main-Frame Switches ................................................... 5-10
Power Control Panel Switch Functions ........................................... 5-15
Console Typewriter Switches and Indicators ....................................... 6-4
Console Typewriter Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-5
List of Trapped Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-7
Instruction Synopsis and Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-8
Summary of Instruction Execution Times ......................................... 7-11
Interrupt Mask Register Bit Assignments ......................................... 7-61
Internal Status Sensing Mask ................................................... 7-62
Block Control Clearing Mask .................................................... 7-63
Pause Sensing Mask ............................................................ 7-64
Interrupt Mask Register Bit Assignments ......................................... 7-65
Modified I/O Instruction Words .................................................. 7-69
Instruction Interpretations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-8
COMPASS Coding Form Description ............................................. 8-18
VB
Section 1
SYSTEM DEseRI PTION
INTRODUCTION
The CONTROL DATA * 3200 is a medium-size, solid-state, general-purpose digital computing
system. Advanced design techniques are used throughout the system to provide expedient
solutions for scientific, real-time, and data processing problems. Modular packaging facilitates expansion of the basic 3200System to accommodate increasing customer needs.
The 3200 is compatible with the CONTROL DATA 3100 and 3300 Computer System; i.e., as
computation requirements exceed the capabilities of the 3200 System, the user may escalate
to a 3300 System without revising existing 3200 programs. Its input/output characteristics
are identical to the 3100, 3300, 3400, 3600 and 3800 Computer Systems-a fact which facilitates incorporating the 3200 into a SATELLITE* configuration.
Various software systems are available for the 3200 System. The SCOPE operating system
is used in 3200 Systems to provide efficient job processing. SCOPE requires a minimum of
storage and time requirements. COMPASS, operating under the control of SCOPE, is the
assembly system used to assemble relocatable machine language programs. Other applicable
software includes FORTRAN, COBOL, the Data Processing Package, Generalized Sort/
Merge and BASIC System. These systems are described in the Software Section of this manual.
Other software and hardware publications pertinent to 3200 Systems may be obtained from
the nearest Control Data sales office listed on the back cover of this manual.
A wide selection of peripheral equipment is available for use in a 3200 System. Equipment
that is applicable to 3200 Systems may be found in the 3000 Series Computer System Peripheral Equipment Reference Manual (Pub. No. 60108800).
This manual provides programming and operating information in conju~ction with a description of special features of the 3200. Reference information and supplementary information
may be found in the Appendix section.
COMPUTER MODULARITY
A 3200 Computer consists of various logic cabinet modules designed to perform specific
operations. If additional storage, input/output channels, or arithmetic capabilities are desired for an existing installation, an appropriate module is integrated into the system. Figure
1-1 illustrates and describes the modules of a typical 3200 computer with its external cabinet
panels removed.
*llegistered trademark of Control Data Corporation
1-1
V IU-
~
8K
STORAGE
MODULE
8K
STORAGE
MODULE
V
BLOCK
CONTROL
AND
INTERRUPT
MODULE
OPTIONAL
ARITHMETIC
CHASSIS
POWER
CO NTROL
PA NEL
MAIN CONTROL
AND
ARITHMETIC MODULE
r - - - ----, r------,
I
I
: I/ O MODULE:
CHANNELS I I I/ O MODULE:
2 AND 3
I : CHANNELS I
o ANO 1 I
(OPTIONAL ) I I
IL.. _ _ _ _ _ _ -1I IL _ _ _ _ _ _ -lI
I
I
I
-
./
"-
/
/'1
Figure 1 -1.
'J
Typical 3200 Modular Configuration
1-2
I
MAIN CONTROL AND ARITHMETIC MODULE
This module, standard in all 3200 systems, controls internal operations, executes 24-bit
precision fixed point arithmetic and 48-bit precision fixed point addition and subtraction
instructions. Boolean, character/word processing, and decision operations are also processed
by this module. Floating point, BCD, and 48-bit precision multiplication and division instructions are classified as trapped instructions if the optional arithmetic module is absent
from the system. Trapped instructions may be processed under control of an interpretive software routine.
BLOCK CONTROL AND INTERRUPT MODULE
Logic associated with this module controls Search and Move operations, external equipment and typewriter I/O, real-time referencing, and operations with the register file. Interrupt logic, also located in this module, processes Internal, I/O, Trapped Instruction, and
Power Failure interrupts.
STORAGE MODULE
An 8,192-word memory module is standard in every 3200 System. A customer may select
combinations of magnetic core storage (MCS) modules to increase the total storage capacity of his computer system to 16,384 or 32,768 words. The following optional storage modules
are available:
3209 - 8,192-word (32,768 characters) MCS memory module (requires additional
chassis).
3203 - 16,384-word (65,536 characters) MCS memory module (requires additional
chassis).
Memory configurations are shown in Table 1-1.
TABLE 1-1.
OPTIONAL MEMORY CONFIGURATIONS
Total Expanded
Memory Capacity
Memory Modules Required in
Addition t9 8K Memory in 3204
16K
32K
3109
3209 and 3203
INPUT/OUTPUT SUB-MODULES
Two types of I/O Channels are available:
3206 Communication Channel (12-bit)
3207 Communication Channel (24-bit)
3206
The 3206 is a bidirectional 12-hit parallel data channel. A maximum of eight 3206 channels
may be used in a 3200 System and up to eight peripheral controllers may he connected to
each channel. Cabinet space is provided for mounting two 3206 channels per I/O sub-module.
The two I/O channels are referred to as a 3206 Dual Communication Module. Channels 0 and
1 normally occupy the lower five logic rows of the storage module directly adjacent to the
block control and interrupt module and channels 2 and 3 occupy the lower five logic rows
of the adjacent storage chassis.
1-3
3207
The 3207 is a bidirectional 24-bit parallel data channel with twice the data transfer rate of
the standard 3206 I/O channel. One 3207 occupies the same cabinet space required for two
3206 channels. If a 3207 is installed in a system, the maximum number of 3206 channels is
limited to six. Only one 3207 may be used in a processor. Refer to Section 3 for additional
information.
OPTIONAL ARITHMETIC MODULE
The floating point/48-bit precision standard arithmetic option provides the necessary logic
to execute 36-bit precision coefficient floating point arithmetic. It also permits the 48-bit
precision multiply and divide instructions to be executed directly by the hardware. The BCD
standard arithmetic option permits decimal numbers to be added, subtracted, loaded, stored
or sensed directly without the use of interpretive software. If one or both options are absent,
the instructions pertaining. to the option(s) can be executed by entering a trapped routine
and utilizing the appropriate software.
CONSOLE
The 3200 sit-down console is standard on all 3200 systems and features:
•
•
•
•
•
•
•
octal readout displays
entry keyboard
various operator switches
thumbwheel breakpoint switch
internal and external status indicators
instruction Auto Step control
operator's chair
A full view of the 3200 Console appears in Figure 1-2 and detailed information is contained
in Section 5.
INPUT/OUTPUT TYPEWRITER
The I/O monitor typewriter is also standard on all 3200 systems. Data is transmitted and
received directly from storage, thus eliminating the need for an I/O channel. Operating
information and character codes are found in Section 6.
POWER CONTROL PANEL
The Power Control Panel enables the computer operator to initially connect power to the
main computer, typewriter, and groups of peripheral equipment. Semipermanent storage
protection switches are located on the upper section of this panel. Operating time and maintenance time meters and the main equipment circuit breakers are also mounted on the control panel. Detailed information pertaining to the Power Control Panel appears in Section 5.
1-4
~
. _ .. ---
:------
Figure 1-2.
--;-&.
3200 Console
1-5
3200 PROCESSORS
3204
Basic
Processor
The 3204 features 6-, 24-, and 48-bit modes, three index registers, indirect
addressing, register file, two 12-bit communication channels, 8,192 words or
32,768 characters of magnetic core storage, 3200 sit-down console, chair,
on-line I/O typewriter, and control for referencing up to 32,768 words of
storage and up to eight 12-bit or six 12-bit and one 24-bit communication
channels.
3205
Scientific
Processor
The 3205 includes all of the control, arithmetic, input/output and storage
functions of the 3204 Processor plus 48-bit floating point arithmetic logic
and logic for 48-bit fixed point multiply and divide.
3210
Data
Processor
The 3210 includes all of the control, arithmetic and input/output functions
of the 3204 Processor plus the BCD arithmetic logic for adding, subtracting,
loading, storing, shifting and sensing characters of variable field lengths.
3215
General
Processor
The 3215 is a truly general-purpose computer featuring word and character
addressing, binary and character manipulation, fixed and floating point
arithmetic and variable length character arithmetic. It includes all of the
features of the 3204, 3205. and 3210 Processors.
COMPUTER ORGANIZATION
COMPUTER WORD FORMAT
The standard 3200 computer word consists of 24 binary digits. Each word is divided into four
6-bit characters. In storage, an odd parity bit is generated and checked for each of the four
characters, lengthening the storage word to 28 bits. Figure 1-3 illustrates the bit assignments
of a computer word in storage.
27 26 25 24 23
18
Character 0
17
12
Character 1
11
06 05
Character 2
00
Character 3
~'~--------------------~y~--------------------~/
Panty bits
Figure 1-3.
Character designators
Computer Word Character Positions and Bit Assignments
REGISTER DESCRIPTIONS
A Register (Arithmetic)
The A register (accumulator) is the principal arithmetic register. Some of the more important
functions of this register are:
• All arithmetic and logical operations use the A register in formulating a result.
The A register is the only register with provisions for adding its contents to the
contents of a storage location or another register.
• A may be shifted to the right or left separately or in conjunction with Q. Right shifting
is end-off; the lowest bits are discarded and the sign is extended. Left shifting is endaround; the highest order bit appears in the lowest order stage after each shift; all
other bits move one place to the left .
• The A register holds the word which conditions jump and search instructions.
1-6
Q Register (Arithmetic)
The Q register is an auxiliary register and is generally used in conjunction with the
A register.
The principal functions of Q are:
• Providing temporary storage for the contents of A while A is used for another
arithmetic operation.
• Forming a double-length register, AQ.
• Shifting to the right or left, separately or in conjunction with A.
• Serving as a mask register for 06, 07, and 27 instructions.
Both A and Q may load or be loaded from any of the three index registers without the
use of storage references.
X Register (Arithmetic)
The X register is a transfer register, used only for internal instruction processing.
Contents of this register cannot be displayed by any external indicators.
F Register (Main Control)
The program control register, F, holds an instruction during the time it is being executed. During execution, the program may modify the instruction in one of three ways:
• Indexing (Address Modification)-A quantity in one of the index registers
(B b ) is added to the lower 15 bits of F for word-addressed instructions, or to
the lower 17 bits of F for character-addressed instructions. The signs of Bb
and F are extended for the addition process.
• Indirect Addressing-The lower 18 bits of F are replaced by new a, b, and m
designators from the original address M (modified if necessary, M = m + B b).
• Indirect Addressing (load and store index instructions)-Bits 00-14 and 17 of
F are replaced by new a and m designators from the original address M (no
modification possible).
After executing an instruction, a Normal Exit, Skip Exit or Jump Exit is performed.
F is displayed on the console whenever the keyboard is inactive and the computer is
not in the GO mode.
C Register (Main Control)
Quantities to be entered into the A, Q, B or P registers or into storage from the entry
keyboard are temporarily held in the Communication (C) register until the TRANSFER
switch is pushed. If an error is made while entering data into the Communication
register, the KEYBOARD CLEAR switch may be used to clear this register.
The C register holds words read from storage during a Sweep or Read Storage operation. The contents of C are displayed on the console whenever the keyboard is active.
P Register (Main Control)
The P register is the Program Address Counter. It provides program continuity by
generating in sequence the storage addresses which contain the individual instructions.
During a Normal Exit the count in P is incremented by 1 at the completion of each
instruction to specify the address of the next instruction. These addresses are sent via
the S (address) Bus to the specified storage module where the instruction is read. A
Skip Exit advances the count in P by 2, bypassing the next sequential instruction and
executing the following one. For a Jump Exit, the execution address portion of the jump
instruction is entered into P, and used to specify the starting address of a new sequence
of instructions.
1-7
Bb Registers (Main Control)
The three index registers, Bl, B2 and B3, are used in a variety of ways, depending on the
instruction. In a majority of the instructions they hold quantities to be added to the execution
address (M=m+ Bb). The Bb registers have no provision for arithmetic operations.
Data Bus Register (DBR-Main Control)
A 24-bit Data Bus register is used to temporarily hold the data received from storage, Communication register and other logic areas. It is a nondisplayed and nonaddressable register.
During character-addressed or input/output operations, data entering the DBR may be
shifted one, two, or three character positions during the transfer to reach the correct character
position within the DBR.
E Register
The optional arithmetic register, E, is present in a system whenever one of the two optional
arithmetic logic packages is present. Its characteristics and functions depend upon whether
it is being used for floating point/48-bit precision or for BCD operations.
During floating point/48-bit precision operations, the E register is divided into two parts,
EU and EL (EUpper and ELower) each composed of 24 bits. It is used as follows:
• 48-bit precision multiplication; holds the lower 48 bits of a 96-bit product.
• 48-bit precision division; initially holds the lower 48 bits of the dividend; upon
completion, holds the remainder .
• Floating point multiplication; holds the residue of the coefficient of the 48-bit product.
• Floating point division; holds the remainder.
During BCD operations the E register is designated the ED register (EDecimal)' The unique
decimal digits can be expressed in 4 bits, i.e., 810=108 and 910=118. Accordingly, ED is extended from 48 to 53 bits in order to handle 13 of these 4-bit characters, plus one sign bit.
This register is used in conjunction with storage to perform BCD addition and subtraction.
D Register
The D register is a field length register and is used in conjunction with loading, storing,
adding, and subtracting numeric BCD characters. This register is set to a field length of 1 to
12 characters by executing a SET (70.7) instruction. The field length remains the same until
it is changed by another SET instruction.
The D register is present only when the BCD arithmetic option is incorporated into a system.
The contents of the D register cannot be displayed.
5 Register (Storage)
The S register holds the address of the storage word currently being referenced. It is displayed
on the Storage Module control panel.
Z Register (Storage)
The Z register is the Storage Resoration and Modification register. Data stored or being
transferred to or from the address specified by the S register must pass through Z. The entire
storage word including the four parity bits is represented by the Z register and is displayed
on the Storage Module control panel.
1-8
TABLE 1-2. CHARACTERISTICS OF 3200 COMPUTER REGISTERS
REGISTER
DESIGNATION
FUNCTION
BIT
CAPACITY
MODULUS
COMPLEMENT
NOTATION
ARITHMETIC
PROPERTIES
RESULT
A
Main
Arithmetic
register
24
224-1
one's
Q
Auxiliary
Arithmetic
register
24
224-1
one's
additive
signed*
F**
Program
Control
register
24
224-1
***
***
***
C**
Communication
register
24
224-1
P
Program
Address
register
15
2 15'-1
B1, B2, 8 3
Index
registers
15
2 15 -1
S
Storage
Address_
register
13
213-1
Z
Storage
Data
register
28
(includes 4
parity bits)
224-1
X
Arithmetic
Transfer
register
24
224-1
EUpper and
ELower octal
register
48
2 48 -1
EU and EL
ED
ED
(BCD)
register
0
Field Length
register
additive
signed*
............
53 (include
sign and
overflow digit)
4
one's
additive
unsigned
****
±10 13
24-1
one's
additive
signed*
absolute
additive
signed
one's
............
Since the A, Q, and EUEL register cQntents are all treated as signed quantities, the capacity of these registers is limited to the following values:
A ~ 2 23 -1; Q~ 2 23 -1; EUEL:::::: 247-1. When the arithmetic result in A. Q, or EUEL is zero, it is always represented by positive zero.
Dual purpose register.
**
Only the lower 15 or 17 bits of F are modified depending on whether word or character addressing is being used. The results are unsigned.
***
**** Information' not applicable.
*
DATA BUS AND'S' BUS
The Data Bus provides a common path over which data must flow to the storage, arithmetic,
console typewriter and I/O sections of the computer. These sections are connected in parallel
to the Data Bus. During the execution of each instruction, Main Control determines which
data transfer path is activated.
An odd parity bit is generated for the lower byte of each word as it leaves the DBR during
I/O operations. In the case of a 3207 I/O Channel, parity for the upper byte of data is gener-
ated in the channel itself rather than in the Data Bus.
The S or Address Bus is a data link between Main Control and storage for transmitting
storage addresses. Inputs to the S Bus are from the P register, F register, Block Control and
the Breakpoint circuits. Figure 1-4 illustrates the relevance of the Data Bus and S Bus in
a typical 3200 installation.
Storage Address Bus
3209
Storage
Module
3209
Storage
Module
8K
8K
Computation
Section
~
3200
Console
1
I
3203
Storage
Module
16K
Console "I
Typewriter
I
I
Data Bus
I
I
3206
3206
I
I
-]
I
I
3206
3204 Basic Processor
3206
I
I
I
I
3206
I
I
I
1
I
I
I
3206
I
3206
I
3206
I
~
or 3207
Figure 1 -4.
Storage Addressing and Data Paths of Typical Installation
BLOCK CONTROL
Block control is an auxiliary control section within a 3200 series processor. In conjunction
with the register file and program control, it directs the following operations:
• External equipment I/O
• Search/Move
• Real-Time clock
• Console typewriter I/O
• High-speed temporary storage
Register File
The register file is a 64-word (24 bits per word) rapid access memory with a cycle time of 0.5
JLsec. Although the programmer has access to all registers in the file with the inter-register
transfer (53) instruction, certain registers are reserved for specific purposes (see Table 1-3).
All reserved registers may be used for temporary storage if their use will not disrupt other
operations that are in progress~
1-10
The contents of any register in the file may be viewed by selecting the register number with
the Breakpoint switch and pressing the Read STO button on the keyboard. The contents may
be altered by setting the Breakpoint switch, pressing the Write STO button, and entering a
new word from the entry keyboard.
TABLE 1-3. REGISTER FILE ASSIGNMENTS
Register
Numbers
00-07
10-17
Register Functions
Modified I/O instruction word containing the current character address (channel 0-7 control)
Modified I/O instruction word containing the last character address ±1, depending on the
instruction (thannel 0-7 control)
20
21
22
23
24-27
Search instruction word containing the current character address (search control)
Move instruction word containing the source character address (move control)
Real-time clock, current time
Current character address (typewriter control) *
Temporary storage
30
31
Instruction word containing the last character address +1 (search control)
32
.Real-time clock, interrupt mask
Instruction word containing the destination character address (move control)
Last character address +1 (typewriter control) *
33
34-77
Temporary storage
*The upper 7 bits of registers 23 and 33 should contain zeros.
Block Control Priority
Access to block control circuits is shared between the computer's program control and- block
control's own buffered functions. Functions within block control are divided into thr~e groups
(see Table 1-4). Five scanners provide the necessary priority network for this system. They are
the Program/Buffer scanner, the Group scanner, and the three Inner-Group scanners. Figure
1-5 is a diagram showing the search pattern of the scanners.
TABLE 1-4. BUFFER GROUPS
GROUP1
GROUP2
GROUP3
Channel 0 control
1
2
Channel 4 control
Real-time clock control
Console typewriter control
Register File Display
Search/Move control
3
5
6
7
A free-running scanner alternately checks for block control requests from program control,
and for functions within block control. This scanning.is done on an equal time basis. As soon
as a request from one source has been processed, the scanner is released so it can check the
other source for an active request.
Another free-running scanner checks the three groups for an active block control request.
After a request from one group has been processed, the scanner moves to the next group,
rotating through the groups in a 3,2, 1,3 order.
Each group has a four-position scanner. These scanners search from top to bottom of their
respective groups looking for active block control requests. After they find a request and it
has been processed, the scanners return to the top of their group before resuming their search.
1-11
•+
•+
•+
•
Channel 0 Control
2
3
•f
•f
•
•'"
4
5
6
7
Real-Time Clock Control
Console Typewriter Control
Register File Display
Search/Move Control
•+
•f
•+
•
Group 1
•
Buffer
Program
~
•
•
Group 2
•~ •
Group 3
Figure 1 -5. Block Control Scanning Pattern
REAL-TIME CLOCK
The real-time clock is a 24-bit counter that is incremented each millisecond to a maximum
period of 16,777,216* milliseconds. After reaching its maximum count, the clock returns to
zero and ~he cycle is repeated continuously. The clock, which is controlled by a 1 kilocycle
signal, starts as soon as power is applied to·the computer. The current time is stored in register 22 of the Register File. It is removed from storage, updated, and compared with the contents of register 32 once each millisecond. When the clock time equals the time specified by
the clock mask, an in terru pt is set. When necessary, the real-time clock may be reset to any
24-bit quantity including zero by loading A and then transferring (A) into register 22. Performing a Master Clear will not affect the clock count.
PARITY
Parity bits are generated and checked in 3200 systems for the following two conditions:
1 Whenever a data word is read from or written into storage.
2 When a data word is transferred via an I/O channel.
*16,777,216 milliseconds equals approximately 4 hours and 40 minutes.
1-1-2
Storage Parity
A parity bit is generated and checked for each 6-bit character of a storage word. Refer to
Figure 1-6.
27
26
25
24
23
18
17
12
11
06
05
00
3
Character designators
Parity bit for character
Parity bit for character
Parity bit for character
Parity bit for character
3
2
1
0
Figure 1 -6. Parity Bit Assignments
During each Write cycle, a parity bit is stored along with each character. When part or all of
a word is read from storage, parity is checked for a loss or gain of bits. Failure to produce
the correct parity during Read operations causes the PARITY FAULT indicators on the
Storage Module Control Panel and internal status lights to glow. As soon as a parity error
is recognized by Main Control, program execution is halted. Master Clearing the computer
clears the fault condition.
If the DISABLE PARITY switch has been depressed and is active, subsequent parity errors
will not cause parity error indications to glow and program execution will not be affected.
The total number of ul's" in a character, plus the parity bit, is always an odd number in the
odd parity system used in the 3200.
I/O Parity
The I/O Communication Channels provide parity lines in addition to the other signals that
interface with external equipment. Parity is checked in the I/O chann~ls to detect parity
errors during data transmission to the external equipment and errors when data is received
from external equipment. I/O parity errors can be detected by a sensing instruction; however,
the parity error indicator will not be activated. A complete description of I/O parity generation
and checking may be found in the I/O section of this manual.
PERIPHERAL EQUIPMENT
A large variety of peripheral equipment is available for use with the 3200 computer. All
peripheral equipment available for 3100, 3200, 3300, 3400, 3600 and 3800 systems may be
attached to a 3206 communication channel. For programming instructions, as well as a list
of function codes and status response codes, refer to the Control Data 3000 Series Computer
Systems Peripheral Equipment Reference Manual (Pub. No. 60108800).
1-13
Section 2
STORAGE CHARACTERISTICS
STORAGE MODULE CONTROL PANEL
Figure 2-1 shows the Storage Control Panel which is mounted at the top of each 3209 Storage
Module. The Drive Voltage Control is used to adjust the drive voltage to 22.5 volts, and not
exceeding 24 volts. The Z and S registers are displayed on this panel, as well as three storage
faults. The indicator lamps represent an x or y drive line voltage failure and a storage parity
fault. The Control Panel on the 3203 Module is similar to the 3209 Control Panel but is laid
out on a verticai plane.
DRIVE VOLTAGE
CONTROL
000000 000000
600000 OOOOOQ
'''.IS'EI
~
'w
CONTROL SELECT
0 0 0 (;)
123. fl' 1I1 .12 t
tII· 6
•••
IS·O'
'Alny
fAUl'TS
o 000 ()()() O()() O()<:)
12
n
10.
•
7
6
5
4
3
1
I
0
S lEGISTEI
Figure 2-1. Storage Module Control Panel
2-1
STORAGE REGISTERS
S REGISTER
The 13-bit S register contains the address of the word being currently processed. Bit
12 specifies field 0 or field 1 in the memory stack. Bits 00-11 specify the co-ordinates
of the word.
Z REGISTER
The 28-bit Z register is the storage restoration and modification register. All data that
is transferred to or from the storage module passes through Z.
READ/WRITE CHARACTERISTICS
During a normal memory cycle, all bits of a word referenced by (8)* are read out of core
storage in parallel, loaded into Z, used for some purpose, then written back into storage
intact. Five modes exist in the 3200 Computer for storage modification. In all cases, Z is
initially in the cleared state.
The Z register is only cleared at the beginning of each memory cycle (except in the
case of a Master Clear). If the program stops as the result of a parity error, the operator
can examine (Z) on the Storage Module Control Panel, Figure 2-1.
SINGLE-CHARACTER MODE
Anyone character may be ignored during the Read cycle. New data is then loaded
into the corresponding character position of Z and the whole (Z) is stored.
DOUBLE-CHARACTER MODE
The upper, middle, or lower half of a word is ignored during the Read cycle. New data
is loaded into the unfilled half of Z and the whole (Z) is stored.
TRIPLE-CHARACTER MODE
Either of the two possible triple-character groups may be ignored during the Read cycle.
New data is then loaded into the corresponding character positions of Z and the whole
(Z) is stored.
FULL-WORD MODE
The whole word is ignored during the Read cycle. A new word is entered into Z and
(Z) is stored.
ADDRESS MODE
The lower 15 or 17 bits of a word may be ignored during the Read cycle. A new word
or character address is then loaded into Z, and the whole (Z) is stored.
*The parentheses are an accepted method for expressing the words "the content(s) of" (in this case, "the
contents of S").
2-2
STORAGE ADDRESSING
Table 2-1 gives the absolute addresses for a specific storage capacity.
TABLE 2-1. ABSOLUTE ADDRESSES
Storage
Word
Capacity
Encompassing Addresses
8K
(8,192)
00000
16K
(16,384)
ALL PRECEDING ADDRESSES AND:
20000
~ 37777
32K
(32,768)
ALL PRECEDING ADDRESSES AND:
40000
:. 77777
~
17777
NOTE
If an address is referenced that exceeds the storage capacity of a system, the uppermost
digit is adjusted to conform to the available storage. No fault indication is given for this case.
Example: Address 67344 referenced.
Actual address referenced: 67344 - 32 K system
27344-16K system
07344- 8K system
STORAGE SHARING
Two 3200 computers may share the memory of a 3209 Storage Module. A switch on each
Storage Module Control Panel allows the operator to give exclusive control to the right or
left computer. A middle position on this switch actuates a two-position priority scanner.
Storage Control honors the requests in the order they are received. Neither computer has
priority over the other and the computer involved in the current storage cycle relinquishes
control to the requesting computer at the end of its cycle. Either computer Can therefore be
delayed a maximum of one storage cycle. A similar program delay may occur within either
computer when an internal scanner determines whether Main Control or Block Control has
access to the storage module.
Direct access to 3200 type storage modules is available for certain installations. The normal
I/O channel route is bypassed and the customer's special equipment interfaces directly with
the storage logic.
STORAGE PROTECTION
It is often desirable to protect the contents of certain storage addresses against alteration during the execution of a program. There are three catagories of addresses: those
that are always protected; those that are protected at the option of the programmer;
and those that are never protected during special sequences.
An attempt to write at a protected address is defined as an Illegal Write. No writing
actually takes place, however, and the attempt to write does not stop or interrupt the
execution of the program. An Illegal Write causes a console indicator to light and the
program may sense an Illegal Write as bit 05 of the internal status response code. An
Illegal Write is cleared by a Master Clear, an Internal Clear, or by sensing.
2-3
PERMANENT PROTECTION
The upper 40 8 memory locations reserved for Auto Load and Auto Dump programs are always
protected against alteration by a special storage protection circuit. The actual addresses
protected depend upon the memory size and encompass the addresses shown in Table 2-2.
TABLE 2-2. AUTO LOAD/AUTO DUMP RESERVED ADDRESSES
Memory
Size
Auto Load and Auto Dump
Reserved Storage Addresses
8K
17740-17777
16K
37740-37777
32K
77740-77777
Logic circuits sense the total storage capacity of the system and check each storage
address as it appears on the S (address) Bus to see if it is among the protected addresses.
If it is one of those to be protected, reading but no writing is allowed at that address.
The only time that this protection is disabled is when an operator presses the ENTER
AUTO PROGRAM switch on the console so that he may store a new Auto Load or
Auto Dump program. Refer to Section 3, Input/Output Characteristics, for additional
information on the Auto Load and Auto Dump features.
SELECTIVE PROTECTION
There are 15 three-position toggle switches mounted on the Power Control Panel. Each
switch corresponds to one bit of the 15-bit storage address. The operator may protect
an address or block of addresses in storage by setting each of the switches to one of its
three positions. A view of the Storage Protect switches on the Power Control Panel
appears in the Consoles and Power Control Panel section, and Table 2-3 describes the
switch positions.
Selective protection may be disabled by pressing the Disable Storage Protect switch
on the console. Table 2-4 gives examples of the switch settings needed to protect various
blocks of addresses.
NO PROTECTION
Addresses 00002 through 00005,00010 and 00011, which are used by the interrupt system,
are never protected during the interrupt sequence.
2-4
TABLE 2-3. STORAGE PROTECTION SWITCH DESCRIPTIONS
Output
Switch
Position
"1"
"N"
Center
"0"
Down
Up
Description
Each address protected will have a "1" in this bit position.
Each address protected may have either a "1" or a "0" in this position.
For example, when all switches are set to the neutral position, all storage
is protected, provided that the protect feature is enabled.
Each address protected will have a "0" in this bit position.
TABLE 2-4. STORAGE PROTECTION SWITCH SETTINGS
Examples:
Description of Protected Addresses
Addresses Protected (octal)
Settings - Storage
Protection Switches
Single storage address
000
000
000
001
111
00017
Two nonsequential addresses of a
group of 108. *
000
000
000
000
000
000
010
010
ONO
Nl0
00020 & 00022
00022 & 00026
Four nonsequential addresses of a
group of 108.*
000
000
000
010
NON
000
000
000
010
NNl
00020,
00024,
00021,
00025,
Four address block- may be the
upper or lower half of a group
of 108.*
000
000
000
000
000
000
100
100
aNN
lNN
00021 ,
& 00025
00023,
& 00027
00040-00043
00044- 00047
108 address block
000
000
000
010
NNN
00020-00027
208 address block
000
000
000
000
001
001
OON
11N
NNN
NNN
00100-00117
00160-00177
408 address block - may be the
upper or lower half of a group
of 1008.*
100
100
000
000
000
000
aNN
lNN
NNN
NNN
40000-40037
40040-40077
Numerous other groups and combinations of the above groups
may also be protected.
000
000
000
NNN
1 1a
NNN
NNN
NNN
NNN
111
NNN
NNN
001
NNN
NNN
00006, 00016,
00026 ... 00076
All XXXX7 addresses
All XX1XX addresses (0010000 1 77, 01 10001177, etc.)
* The first address of all groups of 108, 208, 408, 1008, etc., must have a lower octal digit of zero.
Blocks of 1008, 2008, 4008, 10008, 20008, 40008, etc., may be protected in the same manner as
blocks of 108, 208, & 408.
2-5
Section 3
INPUT/OUTPUT CHARACTERISTICS
Data is transferred between a 3200 Computer and its associated external equipment via a
3206 or 3207 Communication Channel. For programming purposes, the eight possible 3206
channels in a system are designated by numbers 0 through 7. A 3207 replaces the 3206 type
I/O channels 2 and 3 in expanded systems. It is programmed as Channel 2.
INTERFACE SIGNALS
Up to eight external equipment controllers may be attached in parallel to each 3206 Communication Channel. Figure 3-1 shows the principal $ignals which flow between a 3206 and its
external equipment. The 12 status lines are active only between the channel and the controller to which it has been connected by the CON (77.0) instruction. The eight interrupt lines,
designated 0-7, connect to all eight controllers attached to a channel. These lines match the
Equipment Number switch setting on each controller. For a complete description of the I/O
interface signals as well as an I/O timing chart, refer to the 3000 Series I/O Specifications
(Pub. No. 60048800).
Data Lines (12 for 3206; 24 for 3207)
Parity Lines (1. for 3206; 2 for 3207)
Connect
Function
3206 or 3207
Read
External
Communication
Write
Equipment
Channel
Data SiQnal
Controller
Master Clear
Clear External Interrupt
Channel Busv
Reply
Reiect
End of Record
External Parity Error
Status Lines (12)
Interrupt Lines (8)
Suppress Assemblv/Disassemblv
Word Mark
Sample Status Time
Figure 3-1. Principal Signals Between liD Channel and External Equipment
3-1
liD PARITY
PARITY CHECKING WITH THE 3206
The computer checks parity by one method for Connect, Function and Write operations,
and by a second method for Read operations.
Connect, Function and Write
During the Connect, Function and Write operations, the Data Bus circuit of the computation section generates a parity bit and sends it to the external equipment with each
12-bit byte of data via the I/O channel. The external equipment generates a second
parity bit and compares it with the parity bit from the computer. If an error exists, the
external equipment sends an External Parity Error signal back to the I/O channel.
This signal causes the logic within the channel to provide a "I" on sense line O. The
logic is cleared every time an attempt is made to execute a Connect, Function, Read,
or Write operation with this channel. It may also be channel-cleared by the program or
master-cleared by the operator. If a transmission parity error is received from a controller, the controller remains inactive until the I/O channel is cleared.
Read
During a Read operation, the external equipment generates a parity bit and sends it to
the I/O channel along with each 12-bit byte of data. The I/O channel holds the parity
bit while the data is forwarded to the computation section. The Data Bus circuit of the
computation section generates a second parity bit and sends it back to the I/O channel.
The channel compares this second signal with the parity signal which was generated by
the external equipment. If an error exists, certain channel logic is set by an enable from
the computation section. This logic provides a "I" on sense line O. The channel parity
logic is cleared every time an attempt is made to execute a Connect, Function, Read or
Write operation with this channel. It may also be channel-cleared by the program or
master-cleared by the operator. If a transmission parity error is channel-generated, it
must be sensed by the INS instruction. If the error is not sensed, the next channel operation will clear the error indication.
PARITY CHECKING WITH THE 3207
The computer checks parity in a 3207 in a slightly different manner than in a 3206.
Connect, Function and Write
During the Connect, Function and Write operations, the Data Bus circuit in the computation section generates a parity bit for the lower 12-bit byte of each data word. The
3207 generates a parity bit for the upper byte. Both parity bits are sent to the external
equipment via the I/O channel. The external equipment generates' parity bits and compares them with the parity bits from the computer. If an error exists, the external equipment sends an External Parity Error signal back to the I/O channel where it can set the
channel parity logic and provide a "I" on sense line O. Clearing the logic occurs in the
same way as it does in the 3206. If a transmission parity error is received from a controller, the controller remains inactive until the I/O channel is cleared.
Read
During a Read operation, the external equipment generates two parity bits per data
word, one for each 12-bit byte, and sends them to the 3207 along with the word. The
I/O channel holds the parity bit for the lower byte while it forwards the byte to the
computation section. The Data Bus circuit of the computation section generates a second
parity bit for this byte and sends it back to the I/O channel.
3-2
Simultaneously, the 3207 retains the parity bit for the upper byte of the data word. The
I/O channel generates a second parity bit for the upper byte as it forwards the byte to
the computation section.
The 3207 compares the two parity bits generated by the computer with the two parity
bits generated by the external equipment. If an error exists, the channel parity logic is
set by an enable from the computation section, thus providing a "I" on sense line O.
Clearing the logic also occurs the same way as it does in the 3206. If a transmission
parity error is channel-generated, it must be sensed· by the INS instruction. If the error
is not sensed, the next channel operation will clear the error indicator.
AUTO LOAD/AUTO DUMP
The Auto Load/Auto Dump feature allows the programmer 3210 storage addresses in
which to store two short routines. These routines are used generally to receive and
transmit data to external equipment. Assuming the routines are already in storage, the
operator can initiate these operations with the AUTO LOAD and AUTO DUMP switches
on the console.
PRELIMINARY CONSIDERATIONS
Addresses 77740 through 77777 are normally protected from being written into. To enter
Auto Load or Auto Dump routines, the operator presses the ENTER AUTO PROGRAM
switch on the console, enters the routine, then Master Clears the computer. Before pressing
the AUTO LOAD or AUTO DUMP switches, the operator must first Master Clear the
computer.
AUTO LOAD
The AUTO LOAD switch automatically sets (P) to address 77740. This group of 16
instructions may be used to bring in a program from a magnetic tape unit or other peripheral device. The last instruction in this routine should be a jump to the first address
of the newly stored program.
AUTO DUMP
The AUTO DUMP switch automatically sets (P) to address 77760. This group of 16
instructions is most often used to output a block of data to a magnetic tape unit or other
peripheral equipment. The last instruction in this routine may be a jump to any storage
area.
3-3
SATELLITE CONFIGURATIONS
Figure 3-2 shows three possible Satellite configurations that utilize one or more 3200
Computer Systems.
3200 Computer
3200 Computer
3206
Communication
Channel
3206
Communication
Channel
3682
Satellite
Coupler
System
System
..,
*
*
3200 Computer
3206
Communication
Channel
3682
3606
Satellite
Coupler
Data
Channel
System
System
*
3200 Computer
*
3206
3682
3681 Data
Communication
Channel
Satellite
Coupler
Channel
Converter
System
*
*
Figure 3-2. Satellite Configurations
*NOTE:
3600 Computer
May be connected to seven additional external equipments.
3-4
160/160-A
Computer
Section 4
INTERRUPT SYSTEM
GENERAL INFORMATION
The Interrupt Control section of the 3200 Computer is capable of testing for the existence
of certain internal and external conditions without having these tests in the main program. Examples of these conditions are internal faults and external equipment end-ofoperation. Near the end of each RNI cycle. a test is made for interruptible conditions.
If one of these conditions exists. execution of the main program halts. the contents of the
Program Address register are stored. and an interrupt routine is initiated. This interrupt
routine. initially stored in memory. performs the necessary functions for the existing
condition and then jumps back to the last unexecuted step in the main program. The
instruction being read when the interrupt is recognized is executed when the main program is resumed.
There are four categories of interrupts in the 3200 Computer: Internal Condition interrupts. Input/Output (I/O) interrupts. Trapped Instruction interrupts and a special Power
Failure interrupt. The store operations required for all four types of interrupts occur
regardless of the state or selection of the storage protection feature described in Section 2.
An additional manual interrupt is set by a switch on either the computer or typewriter
console. This interrupt is not masked since this switch is pressed only when an interrupt
is desired. The interrupt is recognized if the interrupt system is enabled. The interrupt
condition is automatically cleared after the interrupt is recognized.
INTERRUPT CONDITIONS
INTERNAL INTERRUPTS
Anyone of six internal conditions may cause an interrupt during the execution of a program. These conditions and their descriptions follow.
Arithmetic Overflow Fault
The Arithmetic Overflow fault is set when the capacity of the adder is exceeded. Its
capacity. including sign. is 24 or 48 bits for 24-bit precision and 48-bit precision. respectively.
Divide Fault
The Divide fault sets if a quotient. including sign. exceeds 24 or 48 bits for 24-bit precision
and 48-bit precision. respectively. Therefore. attempts to d~vide by too small a number.
including positive and negative zero. result in a Divide fault. A Divide fault also occurs
when a floating point divisor is either equal to zero or not in floating point format. The
results in the A. Q. and E registers are insignificant if a fault occurs. A Divide fault can
be correctly sensed only after the current instruction has been executed.
4-1
Exponent Overflow/Underflow Fault
During all floating point arithmetic operations, exponential overflow occurs if the ex-.
ponent exceeds +17778 or is less than -17778.
BCD Fault
A BCD Fault is set if:
1. The lower 4 bits of any character, except the least significant, exceeds lIs (910).
Characters are tested for legality only during the LDE, ADE, and SBE instructions. In all cases, if the value lIs (910) is exceeded, the value zero is used
for that character.
2. The upper 2 bits of any character, except the least significant, do not equal zero.
3. An attempt is made to set (load) the D register with 158, 16s or 178.
Search/Move Interrupt
The Search/Move control may be programmed to generate an interrupt during a 71 or
72 instruction for either of the following conditions:
1. Completion of an equality or inequality search.
2. Completion of a block move.
Real-Time Clock Interrupt
The Real-Time Clock interrupt is generated when the clock reaches a prespecified time
that has been stored in register 32 of the Register File.
TRAPPED INSTRUCTION INTERRUPTS
A translator within the 3200 Computer detects and traps the 55-70 instructions if the
appropriate option is not present in the system. Although they are not true interrupts,
trapped instructions are processed like interrupts once they have been detected. A conventional interrupt always takes priority over a trapped sequence. The following operations take place when a trapped instruction is recognized:
1. P + 1 is stored in the lower 15 bits of address 00010.
2. The upper 6 bits of F are stored in the lower 6 bits of address 00011; the upper
18 bits remain unchanged.
3. Program control is transferred to address 00011 and an RNI cycle is executed.
Further information on trapped instructions may be found in the General Information
paragraph of Section 7.
POWER FAILURE INTERRUPT
If source power to a 3200 Computer is removed, the failure is detected and the computer
program is interrupted; this interrupt is necessary to prepare for a controlled shutdown
and prevent the loss of data. This operation requires 16 ms for detection, and up to 4 ms
for processing a special Power Failure interrupt routine.
The Power Failure interrupt overrides any other interrupt (internal or 110), as well as
the trap sequence, regardless of the state of the interrupt control. Since this interrupt
overrides all others, the address where the present contents of P are stored and the
address to which program control is transferred must be different from that for a normal
interrupt. When a Power Failure interrupt occurs, the machine stores the contents of
P in the lower 15 bits of address 00002 and transfers program control to address 00003.
The normal interrupt system is disabled during a power failure sequence; i.e., the hardware simulates the execution of a DINT (77.73) instruction.
4-2
I/O INTERRUPTS
I/O Channel Interrupts
Any of the eight possible I/O channels may be programmed to generate an interrupt for either
of the following conditions:
1. Reaching the end of an input or output block.
2. Receiving an End of Record (Disconnect) signal from an external device.
I/O Equipment Interrupt
The I/O equipment interrupt is set when an interrupt signal is received from any of eight
peripheral equipment controllers connected to any of the eight possible I/O channels (there
may be a total of 64 interrupt lines). The interrupt remains set until the computer directs
the originating device to cancel it with a function code.
Associated Processor Interrupt
In a system of two or more processors (computers), each processor may interrupt the
processor to its left by executing an IAPR (77.57) instruction. The interrupting proceSior
must interrupt via its storage modules 0 and 1, which are storage modules 2 and 3 of the
processor being interrupted. This interrupt is not masked and becomes cleared as soon
as it is recognized.
INTERRUPT MASK REGISTER
The programmer can choose to honor or ignore an interrupt by means of the Interrupt
Mask register. All but two of the normal interrupt conditions are represented by the 12
Interrupt Mask register bits. The manual interrupt and the associated processor interrupt
are not masked. The mask is selectively set with the SSIM (77.52) instruction and selectively cleared by the SCIM (77.53) instruction. See Table 4-1 for Interrupt Mask
register bit assignments.
The contents of the Interrupt Mask register may be transferred to the upper 12 bits of the
A register for programming purposes with the COpy (77.2) or CINS (77.3) instructions.
TABLE 4-1. INTERRUPT MASK REGISTER BIT ASSIGNMENTS
Mask Bits
00
01
02
03
04
05
06
07
08
09
10
11
Interrupt Conditions Represented
Mask Codes
I/O Channel
0001
0002
0004
0010
0020
0040
0100
0200
0400
1000
2000
4000
(Includes interrupts
0
1 >- generated within the
2
channel and external
3
equipment interrupts.)
4
5
6
7
Real-time clock
Exponent overflow/underflow & BCD faults
Arithmetic overflow & divide faults
Search/Move completion
INTERRUPT CONTROL
A program can recognize, sense, and clear interrupts, and enable or disable interrupt
control through the use of certain instructions.
4-3
ENABLING OR DISABLING INTERRUPT CONTROL
Instruction EINT (77.74) enables the interrupt system and the DINT instruction (77.73)·
disables it. After recognizing an interrupt and entering the interrupt sequence, other
interrupts are disabled automatically. When leaving the interrupt subroutine, the interrupt must again be enabled by the EINT instruction, if awaiting interrupts or subsequent
interrupts are to be recognized by the system. After executing an EINT, one more Instruction may be performed before the interrupt enable takes effect.
INTERRUPT PRIORITY
An order of priority exists between the various interrupt conditions. As soon as an interrupt becomes active, the computer scans the priority list until it reaches an interrupt
that is active. The computer processes this interrupt and the scanner returns to the top
of the list where it waits for another active interrupt to appear. Table 4-2 lists the order
of priority.
TABLE 4-2.. INTERRUPT PRIORITY
Priority
Type of Interrupt
1
Arithmetic overflow or divide fault
Exponent overflow/underflow or
BCD fault
External I/O interrupts*
I/O channel interrupts**
Search/move interrupt
Real-time clock interrupt
Manual interrupt
Associated processor interrupt
2
3-66
67-74
75
76
77
78
SENSING INTERRUPTS
The programmer may selectively sense interrupts, independent of the Interrupt Mask
register, by using the INTS (77.4) instruction. Sensing the presence of internal faults automatically clears them. Channel interrupt lines that represent channels not present in
the system are always sensed as being active. However, the Interrupt Mask register bits
representing these missing channels may never be set; therefore, no interrupt can ever
occur.
CLEARING INTERRUPTS
I/O equipment interrupts may be cleared by:
• Pressing the EXTERNAL CLEAR button on the console.
• Pressing the entry keyboard MC button.
• Executing an IOCL (77.51) instruction, or
• Reselecting or disabling the interrupt with a function code, SEL (77.1) instruction.
Within a program, I/O channel interrupts must be selectively cleared by the INCL (77.50)
or IOCL (77.51) instructions.
*There are eight interrupt lines on each ofthe eight possible I/O channels, or 64 lines in alL On any given channel,
a lower numbered line has priority over a higher numbered line. Likewise, a lower numbered channel has priority
over a higher numbered channeL Example: line 0 of channel 0 has highest priority of all external I/O interrupts,
line 0 of channel 1 has second highest, and line 7 of channel 7 has the lowest.
** A lower numbered I/O channel interrupt has priority over a higher numbered I/O channel interrupt.
4-4
The Real-time Clock, Arithmetic, and Search/Move Completion interrupts may be
cleared by:
• Sensing, after which the interrupts are automatically cleared.
• Executing an IN CL (77.50) instruction, or
• Pressing the MC or INTERNAL CLEAR buttons.
In the INCL instruction, x represents the contents of the Interrupt Mask register. Even though
the Interrupt Mask register bits usually represent both I/O channel and I/O equipment
interrupts, an INCL instruction clears only internal I/O channel interrupts. In addition to
clearing a channel interrupt with an INCL instruction, the program must clear the I/O
equipment interrupt with a function code SEL (77.1) instruction. The manual and associated
processor interrupts are automatically cleared after they are recognized by the computer
during an RNI cycle.
INTERRUPT PROCESSING
Four conditions must be met before a normal interrupt can be processed:
1. With the exception of the Manual interrupt and the Associated Processor interrupt, a bit representing the interrupt condition must be set to "I" in the
Interrupt Mask register.
2. The interrupt system must have been enabled.
3. An interrupt-causing condition must exist.
4. The interrupt scanning logic (Refer to Table 4-2) must reach the level of the
active interrupt on the priority list.
When an active interrupt has met the above conditions, the following takes place:
1. The instruction in progress proceeds until the point is reached in the RNI cycle
where an interrupt can be recognized. At this time the count in P has not been
advanced nor has any operation been initiated. When an interrupt is recognized,
the address of the current unexecuted instruction in P is stored in address 00004.
2. A number representing the interrupt-causing condition is stored in the lower
12 bits of address 00005 without modifying the upper bits. Table 4-3 lists the
octal codes which are stored for each interrupt condition.
3. Program control is transferred to address 00005 and an RNI cycle is executed.
TABLE 4-3
REPRESENTATIVE INTERRUPT CODES
Conditions
Codes
External interrupt
liD channel interrupt
Real-time clock interrupt
Arithmetic overflow fault
Divide fault
Exponent overflow fault
BCD fault
Searchlmove interrupt
Manual interrupt
Associated processor interrupt
*OOLCh
010Ch
0110
0111
0112
0113
0114
0115
0116
0117
*L = line 0-7 and Ch = channel designator. 0-7
4-5
Section 5
CONSOLE AND POWER CONTROL PANEL
The 3200 desk console enables the computer operator to control and observe computer operation. This section describes the operator's controls and the significance of the visual indicators.
Also included in this section is a view of the Power Control Panel and a description of its
operation.
CONSOLE
REGISTER DISPLAYS
Communication Register
Data entered into any of the operational registers (except the ED register) must first pass
through the Communication register. Starting with the uppermost digit, data is entered into
the Communication register by first depressing a register switch and then depressing the
numeric keyboard switches. A blue Active Digit indicator light is superimposed on each
digit position of the Communication register as digit entry progresses. When data is to be
entered into the Bt, B2, B3 or P registers, the Active Digit indicator automatically starts
at the fifth digit position of the Communication register.
Depressing the TRANSFER switch causes the data to be transferred from the Communication register to the designated register. Depressing the TRANSFER switch again results
in transferring all zeros to the register.
E Register
The E register is 'displayed as either EU and EL or ED. Whenever the E register is being displayed, the A and Q registers cannot be displayed and vice versa. The register(s) currently
displayed is denoted by the illumination of one of the three register display indicators located
between the register displays.
Figure 5-2 illustrates specific digit functions when the EU EL register is displayed on the console. Figure 5-3 illustrates the digit functions when the En register is displayed.
NOTE
The ED register may be entered directly with any of the 10 numeric keyboard characters. As
each digit is entered, the preceding digit is shifted one digit position left, increasing its
significance. Each succeeding entry shifts the digits one position left and inserts the newly
entered digit into the lowest order position. After a maximum of 13 digits have been entered
(including the overflow digit) the uppermost characters are shifted end-off as additional
characters are entered. The EU EL register cannot be entered into by a keyboard operation.
Appropriate inter-register transfer instructions must be utilized for entry into this register.
5-1
1. External status indicators
2. Internal status indicators
3. Thumbwheel breakpoint switch
4 . Emergency power cutoff switch
5. Adjustable auto-step control
6. Octal register displays
7. Detachable keyboard
Figure 5-1. Front View of 3200 Console Controls
1563
1 565
vr------------------J
V
Octal digits 8 through 15
Octal digits 0 through 7
Figure 5-2 . EU EL Register Display
~--------------------------------v·--------------------------------~
Decimal digits 0 through 11
Overflow digit
Sign of ED
MSD of second operand
Sign of second operand
Figure 5-3. ED Register Display
Other Registers
The A, Q, P, Bl, B 2 and B 3 registers, described in the System Description Section of
this manual, are displayed on the Integrated Console in binary form.
CONSOLE LOUDSPEAKER
The console loudspeaker and its associated volume control are mounted underneath the
console table . The loudspeaker receives its input from the upper 3 bits of the A register.
An audible sound is produced when one or more of these bits are toggled at an audio rate.
Loudspeaker volume is controlled by rotating the volume control.
STATUS INDICATORS
External Status Indicators
The external status indicators display the existing conditions of I/O channels 0-7. Conditions displayed are Read , Write, Reject, Connect, Function, and Interrupt. Refer to
Figure 5-4.
Figure 5-4 . External Status Indicators
Internal Status Indicators
Six columns of internal status indicators are located on the display section of the consoles. Refer to Figure 5-5. When the particular indicator is glowing, the condition or
fault described below exists:
5-4
Figure 5-5. Internal Status Indicators
1. STORAGE ACTIVE 0-1-2-3
The Storage Active lights indicate the storage area currently being referenced. Digit 0
glows when the first 8K of storage is referenced. In expanded 3200 systems, digit 1 indicates that the second 8K storage section is referenced, digit 2 the third 8K section, and
digit 3 glows when the fourth 8K section is referenced.
2. CONDITIONS
STANDBY -Indicates that the main power switch is on but the individual logic supplies
are still off.
INTERRUPT DISABLED - Indicates the interrupt system has been disabled by executing
the DINT (77.73 ) instruction or by a Master Clear.
ILLEGAL WRITE - Glows whenever an attempt is made to write into the area of storage
currently being protected by the storage protect switches. This indicator will also glow
if an attempt is made to write into the Auto Load or Auto Dump storage areas. This condition is cleared by executing an INS (77.3) instruction or performing a Master Clear.
PARITY ERROR-Indicates that a parity error has occurred in storage. When the error
is detected, this indicator glows and program execution stops. Performing a Master Clear
clears the condition. Transmission parity errors do not affect this indicator.
3. CYCLE (RNI-RAD-ROP-STO)
These indicators represent the four program cycles: Read Next Instruction, Read Address,
Read Operand, and Store Operand. They are lit while the respective cycles are in progress.
4. FAULTS
This column of indicators represents the four arithmetic fault conditions:
ARITHMETIC OVERFLOW - The arithmetic overflow fault is set when the capacity of
the adder is exceeded. Its capacity, including sign, is 24 or 48 bits for 24-bit precision and
48-bit precision, respectively.
5-5
DIVIDE - The divide fault sets if a quotient, including sign, exceeds 24 or 48 bits for 24bit precision and 48-bit precision, respectively. Therefore, attempts to divide by too small
a number,' including positive and negative zero, result in a divide fault. During floating
point division, a divide fault occurs if division by zero or by a number that is not in floating
point format is attempted. If the divisor is not properly normalized a divide fault may also
occur. Refer to Appendix B for a description of normalization.
EXPONENT OVERFLOW/UNDERFLOW -This fault indicator glows when either an
exponent overflow (>+ 17778 ) or an exponE~nt underflow « -1777 8 ) condition exists.
DECIMAL-A decimal (BCD) fault is set if:
• The lower 4 bits of any character except the least significant exceed 118 (9 10), Characters
are tested for legality only during the LDE, ADE and SBE instructions. In all cases,
if the value 118 (910) is exceeded, the value zero will be used for that character.
• The upper 2 bits of any character except the least significant do not equal zero.
• An attempt is made to load the D register with 158, 168, or 178.
5. TEMPERATURE WARNING
If the upper temperature limit of the normal operating range within a section of the computer is exceeded, a corresponding TEMP WARNING indicator glows. The indicators correspond to computer sections illustrated in Figure 5-6.
6. FAULTS
This column of indicators represents abnormal operating conditions.
TEMPERATURE HIGH-If the TEMP WARNING indicators are glowing and an absolute
temperature is exceeded, the computer will automatically shut off logic power. The TEMP
HIGH indicator for the particular computer section continues to glow until the temperature drops below the absolute limit. Secondary power must be manually re-applied before
normal operation can resume.
If the THERMOSTAT BYPASS console switch is on, all four TEMP HIGH indicators glow
and the temperature protection feature is defeated.
CIRCUIT BREAKER-This indicator glows if the circuit breakers governing any of the
internal power supplies are off.
TERMINATOR POWER-If output power from the internal terminator power supplies
fails, this indicator glows.
Temperature
Indicator
2
16K Storage
and I/O
Logic
Temperature
Indicator
1
Block Control,
Interrupt,
and Optional
Arithmetic Logic
Temperature
Indicator
Temperature
Indicator
0
3
Main Control
and Arithmetic
Logic
16K Storage
and I/O
Logic
Figure 5-6. Temperature Warning Designations for an
Expanded 3200 Computer, Front View.
5-6
SWITCHES
Switches associated with a 3200 Computer _are classified as console switches and keyboard
switches. Console switches include the following:
• The EMERGENCY OFF switch.
• A group of operator/maintenance switches on the console main-frame.
• The Breakpoint switch assembly (Figure 5-8).
Keyboard Switches
The console keyboard switches are used for entering data manually into the computer and
for controlling its operation. A front view of the keyboard appears in Figure 5-7 and Table
5-1 describes the function of the keyboard switches.
Console Switches
EMERGENCY OFF SWITCH -This red rectangular momentary switch is used to remove
power from the whole computer system in case of a fire or other emergency. It should not
be used for a normal power shutdown. Refer to the SOURCE POWER OFF switch description in the Power Control Panel description of this section.
OPERATOR/MAINTENANCE SWITCHES -Table 5-2 describes the operator/maintenance
switches located on the console main-frame.
BREAKPOINT SWITCH ASSEMBLY -The Breakpoint switch is a six-section, eight-position, thumb-wheel switch. The left-hand wheel selects the operating mode, and the other
five wheels specify a register number or storage address. There are four mode positions
on the mode selector switch with an OFF position between each mode; these modes are
BPI, BPO, REG, and STO.
BPI and BPO Modes: The address on the S Bus is continually compared with the instruction or operand address specified by the Breakpoint digit switches. When the selector
switch is set to BPI, the computer stops if these values become equal during an RNI (Read
Next Instruction) sequence. When the mode selector switch is set to BPO, the computer
stops if these values become equal during an ROP (Read Operand) or STO (Store) sequence.
REG and STO Modes: In these two modes, the operator may either monitor the contents
of a register location or storage address specified by the thumb-wheel digit switches, or
he may store a word in these locations. To monitor a storage location:
1. Set the mode selector to REG (register file location) or STO (storage).
2. Set the Breakpoint switch to the desired register number or storage address.
3. Press the READ STO switch on the keyboard.
4. Adjust the Auto Step control to vary (he display rate.
The register or storage contents are repeatedly displayed in the Communication register
at the selected repetition rate ul)til another keyboard button is pressed to release READ
STO. To write a word in storage:
1 . Set the mode selector to RE G or STO.
2. Set the Breakpoint switch to the desired register number or storage location.
3. Press the WRITE STO switch on the keyboard.
4. Enter data into the Communication register by depressing the numeric switches
and finally the TRANSFER switch.
The data is entered into the desired storage location or Register File location at the end
of the instruction that is currently being executed by the computer. Pressing any other
register or mode selector switch releases WRITE STO operation.
5-7
Figure 5 -7 . Console Keyboard
NOTE
The upper two rows of keyboard switches are mechanically linked together. This feature
prevents more than one switch from being active at anyone time.
5-8
TABLE 5-1. KEYBOARD SWITCH FUNCTIONS
SWITCH NAME
ILLUMINATED
8 1 to 8 3
Yes
Enables data to be manually entered into Index registers 8 1 ,
B2, or B3 from the keyboard.
P
Yes
Enables an address to be manually entered from the keyboard
into the P register.
A
Yes
Causes both A and Q to be displayed, but permits entry only
into A.
D
Yes
Causes both A and Q to be displayed, but permits entry only
into Q.
EU*
Yes
Causes EU and EL to be displayed. Manual entry is not possible.
EL*
Yes
Same as EU.
ED*
Yes
Causes ED to be displayed and enables manual entry directly
into this register. Refer to ED register description.
KYBO
OFF
(Keyboa rd Off)
Yes
Deactivates all keyboard controls.
EN
(Enter)
Yes
Permits data to be manually entered into storage while the
computer is stopped. First address of sequence must be previousIyentered into P. Pressing the TRANSFER switch advances P.
SW
(Sweep)
Yes
Permits unexecuted instructions to be read from consecutive
storage locations. First address of sequence must be first entered into P. Pressing the TRANSFER switch advances P.
WRITE
STO
(Write Storage)
Yes
Permits keyboard entry into the storage location specified by the
thumb-wheel switches. Entry occurs each time the TRANSFER
switch is pressed whether the computer is in the GO mode or
stopped.
READ
STO
(Read Storage)
Yes
Permits the contents of the storage register location specified
by the thumb-wheel switches to be displayed. The display rate
is determined by the Auto-Step control.
KYBO CLR
(Keyboard Clear)
Yes
Clears the Communication register.
GO
Yes
Starts the program execution at the address specified by the
P register. Not used for Sweep or Enter operations.
SW/EN
CONT
(Sweep/Enter
Continuous)
Yes
Enables Sweep or Enter operations to proceed continuously
through storage without pressing the TRANSFER switch.
STOP
Yes
Stops the computer at the end of the current instruction.
TRANSFER
No
Transfers data in the Com'1lunication register to a selected
register or storage location.
MC
(Master Clear)
No
Performs both an internal and external clear. Disabled when GO
switch is depressed and the computer is in the GO mode.
No
These switches, when pressed one at a time, allow entry of that
particular digit into the Communication register in the binary
digit position denoted by the active digit indicator.
No
Depressing either of these switches permits entry of that digit
directly into the ED register. The option must be present in the
system and the ED register selection switch depressed.
No
Depressing either of these switches permits entry into the sign of
ED digit (refer to Figure 5-2) in the ED register. These switches
may be depressed at any time during the numeric entry of ED. The
sign of ED may be changed by depressing the opposite sign switch.
o through
7
8 and 9
+
or (Plus or Minus)
DESCRIPTION
*Depressing any of the switches associated with the arithmetic options when the optional logic is not present
produces equivocal results.
5-9
TABLE 5-2. CONSOLE MAIN-FRAME SWITCHES
SWITCH NAME
MANUAL
INTERRUPT
SELECT
STOP 1
SELECT
JUMP (1 through 6)
ENTER AUTO
PROGRAM
FUNCTION
Forces the computer into an interrupt routine if the computer is
in the GO mode. If the computer is stopped when the switch is
pressed, it will go into an interrupt routine as soon as the GO switch
is depressed.
Stops the computer when the SLS (77.70) instruction is read.
Switches are depressed in accordance with programs utilizing the
selective jump (SJ 1-6) instruction.
Allows the operator to enter the Auto Load and Auto Dump storage
areas (addresses 77740 to 77777) with different data.
EXTERNAL
CLEAR
Master clears all external equipments and the 1/0 channels.
INTERNAL
CLEAR
Master clears internal conditions and registers.
DISABLE
STO PROTECT
Disables the protection feature switch of the 15 storage protect
switches. This switch has no effect on the protected Auto Load and
Auto Dump storage areas.
DISABLE
ADVANCE P
Prevents the P register from being incremented. When the GO
switch on the keyboard is depressed, the same instruction is repeated.
THERMOSTAT
BYPASS
Allows computation to proceed regardless of unfavorable temperatures within the computer.
DISABLE
PARITY
Prevents recognition of parity errors from all storage modules.
INSTRUCTION
STEP
Enables the operator to step through the program instruction by instruction. An instruction is executed each time the switch is depressed.
BCD STEP
Enables the operator to step through a BCD instruction one sequence at a time.
STORAGE
CYCLE STEP
Enables the operator to step through an instruction one storage
cycle at a time, i.e. RNI. RAD, ROP, or STO.
AUTO STEP
Permits instructions to be executed in a slow speed GO mode. The
speed is regulated by the auto-step speed control on the console. There
are approximately 3 to 50 instructions executed per second.
AUTO LOAD
If the computer has been master cleared and t~e Auto Load switch is
depressed, the computer will automatically jump to address 77740
and execute the instruction stored there. Refer to Auto Load/Auto
Dump in Section 3.
TYPE LOAD
Permits the operator to enter a block of data from the typewriter.
The data is defined by the lower bounds in register 23 and upper
bounds in register 33 of the Register File. Refer to the Typewriter
Section for additional information.
AUTO DUMP
This switch performs the same function as the Auto Load switch with
the exception of jumping to address 77760.
TYPE DUMP
Similar to the Type Load operation, this switch causes a block of
data to be printed by the typewriter. The data in storage is defined
by registers 23 and 33.
5-10
Examples of Keyboard Switch Functions
1. To enter data into the A register:
a. Depress the A register switch.
b. Enter all eight digits of the Communication register by depressing the appropriate numeric key switches. *
c. Depress the TRANSFER switch.
d. Depress the KEYBOARD OFF switch.
2. To enter data into the Q register:
Depress the Q register switch and repeat steps b through d of example l.
3. To enter the Program Address Counter (P register) with a specific address:
a. Depress the P register switch.
b. Enter the lower five digits of the Communication register by depressing the
appropriate numeric key switches.
c. Depress the TRANSFER switch.
d. Depress the KEYBOARD OFF switch.
4. To enter an operand at a specific address**:
a. Perform step 3.
b. Depress the EN switch.
c. Enter all eight digits of the Communication register by depressing the appropriate numeric key switches.
d. Depress the TRANSFER switch.
e. The count in the Program Address Counter has now incremented by one. If
data is to be entered into this memory location, repeat steps c and d for as
many succeeding entries as required.
f. Depress the KEYBOARD OFF switch when all data has been entered into
the successive group of memory locations.
5. To read an operand from a specific storage address:
a. Perform step 3.
b. Depress the SW switch.
c. Depress the TRANSFER switch.
d. The contents of the specified storage address are now displayed in the Communication register. (The Program Address Counter is not incremented
when the TRANSFER switch is initially depressed.)
e. If the TRANSFER switch is depressed again, the Program Address Counter
is incremented by one, and the contents of the new address are displayed.
f. Depress the KEYBOARD OFF switch when all the desired memory locations within a successive group have been examined.
6. To enter zeros or another operand into all storage locations:
NOTE
Step 5 only permits the operator to examine the contents of specific storage locations. The
instructions are not executed during this operation.
*If all eight digit positions of the Communication register are not entered before the Transfer switch is
depressed, zeros will be entered into the remaining digit positions.
**The breakpoint switch may be used in lieu of this operation. Refer to example d, Figure 5-8.
5-11
a. Depress the EN switch.
b. Enter all eight digits of the Communication register by depressing the appropriate numeric key switches.
c. Depress the SWlEN CONT switch.
d. Depress the STOP switch.
e. Depress the KEYBOARD OFF switch.
7. The following procedure is applicable for sweeping storage during certain maintenance routines:
a. Depress the SW switch.
b. Depress the SWlEN CONT switch. The' switch remains depressed until the
STOP switch is depressed.
c. Depress the STOP switch.
d. Depress the KEYBOARD OFF switch.
Examples of Console Switch Functions
1. To enter a special routine into the Auto Load storage area:
a. Depress the MC (Master Clear) keyboard switch.
b. Holding down the keyboard STOP switch, depress the AUTO LOAD switch.
Release both switches. The P register should now read 77740. (Holding the
STOP switch down prevents the computer from entering the GO mode and executing the previous Auto Load routine.)
c. Depress the ENTER AUTO PROGRAM switch.
d. Depress the keyboard EN switch.
e. Enter the first instruction of the new routine at address 77740 by depressing
the appropriate numeric key switches.
f. Depress the keyboard TRANSFER switch.
g. Repeat steps e andf for addresses 77741 through 77757.
h. Depress the MC switch. This clears the registers and cancels the ENTER AUTO
PROGRAM function.
i. Depress the KEYBOARD OFF switch.
2. To enter a special routine into the Auto Dump storage area:
Repeat steps a through i of example 1 using the AUTO DUMP switch and filling
the storage area covered by addresses 77760 through 77777.
3. To execute the Auto Load. routine:
a. Depress the keyboard Me switch.
b. Depress the AUTO LOAD switch. The computer automatically executes the
Auto Load routine and stops when a stop or halt instruction is recognized. The
Auto Load function is automatically cleared when the computer stops.
4. To execute the Auto Dump routine:
Perform steps a and b in example 3 but use the AUTO DUMP switch instead of the
AUTO LOAD switch.
5. To execute a program at an Auto Step rate:
a. Set the P register to the first address of the program to be executed.
b. Depress the AUTO STEP switch.
c. Adjust the AUTO STEP display rate control.
d. When enough of the program has been executed, depress the AUTO STEP switch
again to cancel the function. The only way to exit from the Auto Step mode is
to depress the AUTO STEP switch again. In the Auto Step mode, halt and jump
instructions are executed but the computer will not stop. Neither will program
execution be affected by depressing the STOP switch. The computer will continue
cycling through memory until the AUTO STEP switch is again depressed.
5-12
EXAMPLE A
EXAMPLE B
The breakpoint switch is inoperative whenever an
OFF designator is displayed . An OFF designator
separates the REG , STO , BPI and BPO positions .
During the normal execution of a program, the
computer stops when an RN I is attempted at memory location 05443 . A jump to this location also
causes the computer to stop. If the program references memory location 05443 for an operand, the
computer ignores the Breakpoint switch .
EXAMPLE C
EXAMPLE D
The computer stops only when an attempt is made to
read or store a n opera nd at address 00413.
If the WRITE STO switch on the keyboard switch is
depressed and data has been entered into the
Communication register, the data is transferred
to memory location 00104 when the Transfer switch
is depressed.
Figure 5-8. Breakpoint Switch Examples
5-13
EXAMPLE E
EXAMPLE F
If the WRITE STO switch on the keyboard is de pressed and data ha s been entered into the Com municati on registe r, the data will be transferred to
register 77 when th e TRANSFER switch is depress ed . (Only th e lower two digits are recognized
when the designator switch is in the REG position .
The progra mmer mu st use caution when writing
into the Registe r Fil e to prevent destruction of
other data . Refer to Section 1, Table 1-3 .)
If the READ STO switch on the keyboard is de pressed, the contents of memory location 27004
are displayed in the Communication register at a
repetition rate determined by the auto step control.
(If the memory location depicted by the breakpoint
switch exceeds the storage capacity of the system,
the computer selects the address that corresponds
to the storage capacity of the system .)
EXAMPLE G
If the READ STO switch on the keyboard is depressed , the contents of register 22 are displayed
in the Communication register at a repetition rate
determined by the Auto Step control. (Only the
lower two digits are of consequence when the REG
designator is displayed. In this case register 22,
the real time clock, is being referenced .)
Figure 5-8 . Breakpoint Switch Example5 (Cant .)
5-14
POWER CONTROL PANEL
Power for the 3200 Computer System is controlled by the Power Control Panel, mounted
on the right side of the main cabinet assembly. The switches, circuit breakers, indicators
and meters associated with the panel are shown in Figure 5-9. Refer to the 3200 Customer
Engineering manual for detailed maintenance information concerning the Power Control
Panel.
SWITCHES
Table 5-3 lists the switches and their functions. Refer to Section 2 for a description of the
Storage Address Protection switches.
ELAPSED TIME METERS
Two elapsed time meters and a key-operated, two-position switch are located on the control
panel. Turning the key-operated Maintenance Mode switch to ON connects the Running Time
meter to the computer to indicate maintenance time. Removing the key connects the Operating Time meter to the computer to indicate normal operating time. Only one of the two
meters can operate at anyone time. Either meter logs time for a minimum of one second
when a storage cycle occurs.
TABLE 5-3. POWER CONTROL PANEL SWITCH FUNCTIONS
SWITCH NAME
FUNCTION
CONTROL
POWER
When this switch is depressed, the Blower switch and Peripheral Group
switches can be activated.
BLOWERS
ON
Depressing this switch turns on cabinet blowers, power supply blowers
and furnishes power for the peripheral equipment blowers. This switch
must be on before the power supplies can be activated. The Control
Power switch must be on before this switch can be activated.
POWER
SUPPLIES
ON
When this switch is depressed and the Control Power and Blowers
switches are on, the motor generators are turned on. These sets furnish
operating power for the logic power supplies.
PERIPHERAL
GROUP I
ON
If the Control Power switch is on and this switch is depressed, ope rating power is sent to all the equipment connected to the Peripheral
Group I power distribution bus.
PERIPHERAL
GROUP II
ON
If the Control Power switch is on and this switch is depressed, ope rating power is sent to all of the equipment connected to the Peripheral
Group II power distribution bus.
NOTES
1. The switches are active only when main power is present at the control panel
and the applicable circuit breakers are closed (ON position). The individual
circuit breakers are located directly below the switch panel.
2. Except for the Blowers switch, the OFF switches remove power immediately.
If the Power Supplies OFF and the Blowers OFF switches are depressed in
close succession, an automatic five minute delay will keep the blowers operating.
The Power Supplies OFF switch must be depressed a minimum of half a second.
5-15
STORm AllflR£SS PRlIrECTl1lH SWltCIIES
1
.~
'I
. ~ !. ~
f} f} ~
"
I
POWER
BLOWERS
UNIT r OR II --,
, - - - - - - - - UNIT 1 - - - - - - - - - - - . I
LOGIC
T£RMIIiATOR
r - 60"'---"1
, . . - - - - - - UNIT Y - - - - - ,
lOCIC
MAIN
POWER
STORAGE
I
CINTRIL POWER - ,
JItIMAIY
SEefiIlIAlY
I
r-- UNIT II ---,
lOGIC
STORAGE
1
60",---,
MAIN
CONSOLE
f
60"'---,
TYPEWRITER
CONSOLE
r - - PERIPIIERAL GROUP 1I - - - ,
ItDWERS
Figure 5 -9. Power Control Pane l
5-16
1
PERIPHERAL
GROUP 11
PERIPHERAL
GROUP I
SUPPlIES
.;:::w
I
MAINTENANCE
TIM£
MAINTENANCE
MODE
TI ME
III
j
I
l
0
OPERATI NG
LOGIC
~ fJ ti
POm
SUPPliES
Section 6
TYPEWRITER
DESCRIPTION
The 3192 Console Typewriter (Figure 6-1) is an on-line input-output (110) device; i.e. it
requires no connection to a communication channel and no function codes are issued. The
typewriter receives output data directly from storage via the lower 6 bits of the Data Bus.
Inputs to storage are handled in the same manner.
The console typewriter consists of an electric typewriter and a typewriter control panel
mounted on a desk console.
Figure 6-1. 3192 Console Typewriter
6-1
Used in conjunction with block control and the Register File, the typewriter may be used
to enter a block of internal binary-coded characters into storage and to print out data
from storage. The two storage addresses that define the limits of the block must be
stored in the register file prior to an input or output operation. Register 23* contains the
initial character address of the block, and register 33 contains the last character address,
plus one. Because the initial character address is incremented fdr each storage reference,
it always shows the address of the character currently being stored or dumped. Output
operations occur at the rate of 15 characters per second. Input ooerations are limited by
the operator's typing speed.
OPERATION
The general order of events when using the console typewriter for an input or output
operation is:
1. Set tabs, margins and spacing. Turn on typewriter.
2. Clear.
3. Check status.
4. Type out or type in.
SET TABS, MARGINS, AND SPACING
All tabs, margins, and paper spacing must be set manually prior to the input or output
operation. A tab may be set for each space on the typewriter between margins.
CLEAR
There are three types of clears which may be used to clear all conditions (except Encode
Function) existing in the typewriter control. These are:
• Internal Clear or a Master Clear.
This signal clears all external equipments, the communication channels, the
typewriter control, and sets the typewriter to lower case.
• Clear Channel, Search/Move Control, or Type Control instruction (77.51).
This instruction selectively clears a channel, the S/M control, or, by placing
a "I" in bit 08 of the instruction, the typewriter control, and sets the typewriter to lower case.
• Clear Switch on typewriter.
This switch clears the typewriter control and sets the typewriter to lower case.
STATUS CHECKING
The programmer may wish to check the status of the typewriter before proceeding. This
is done with the Pause instruction. Status response is returned to the computer via two
status lines.
The typewriter control transmits two status signals that are checked by the Busy Comparison Mask using the Pause instruction. These status signals are:
Bit 09 Type Finish
Bit 10 Type Repeat
An additional status bit appears on sense line 08. This code is Type Busy, and is transmitted
by block control in -the computation section when a typewriter operation has been selected.
If the programmer is certain of the status of the typewriter, this operation may be omitted.
*The upper nine bits of registers 23 and 33 should be "0".
6-2
TYPE IN AND TYPE LOAD
The Set Type In instruction or pressing the TYPE LOAD switch on the console or typewriter
permits the operator to enter data directly into storage from the typewriter. When the TYPE
LOAD indicator on the console or typewriter glows, the operator may begin typing. The
Encode Function switch must be depressed to enable backspace, tab, carriage return, and
case shifts to be transmitted to the computer during a typewriter input operation.
Input is in character mode only. As each character is typed, the information is transmitted via the Data Bus to the storage address specified by block control. This address
is incremented as characters are transmitted. When the current address equals the terminating address, the TYPE LOAD indicator goes off and the operation is terminated.
Data is lost if the operator continues typing after the TYPE LOAD indicator goes off.
TYPE OUT AND TYPE DUMP
The typewriter begins to type out when the computation section senses a Set Type Out
instruction or the operator presses the TYPE DUMP switch on the console or typewriter.
Single 6-bit characters are sent from storage to the typewriter via the lower 6 bits of the
Data Bus. When the current address equals the terminating address, the TYPE DUMP
indicator goes off and the operation is terminated.
During a Type Out operation, the keyboard is locked to prevent loss of data in the event
a key is accidentally pressed.
CONSOLE SWITCHES AND INDICATORS
Figure 6-2 shows the switch arrangement of the typewriter control panel. The function
of each switch appears in Table 6-1. A rocker switch on the typewriter unit is used to
apply power to the typewriter motor.
Figure 6-2. Typewriter Control Panel.
6-3
TABLE 6-1. CONSOLE TYPEWRITER SWITCHES AND INDICATORS
Name
Switch (S)
Indicator (I)
Description
HIGH
TEMP
I
This indicator glows when the ambient temperature within
the typewriter cabinet exceeds 110° F.
BUSY
I
This indicator shows that the TYPE LOAD or TYPE DUMP
switch has been pressed and the operation is in progress.
POWER ON
I
This indicator shows that power is applied to the typewriter.
S& I
This switch is in parallel with the TYPE DUMP switch on the
console and causes the computer to send data to the typewriter for print-out. It is a momentary contact switch that is
illuminated until the last character in the block has been
printed or the CLEAR button is pressed.
S&I
This switch is in parallel with the TYPE LOAD switch on the
console and allows the computer to receive a block of input
data from the typewriter. The TYPE LOAD indicator remains
on until either the FINISH, REPEAT or CLEAR button is
pressed, or until the last character of the block has been
stored. If the program immediately reactivates the typewriter,
it may appear that the light does not go off.
S&I
This switch is pressed during a Type Load operation to indicate that a typing error occurred. This switch deactivates
busy sense line 10 (see PAUS instruction). If the computer
does not respond, this light remains on.
FINISH
S&I
This switch is pressed during a Type Load operation to indicate that there is no more data in the current block. This
action is necessary if the block that the operator has entered
is smaller than the block defined by registers 23 and 33. This
switch also deactivates busy sense line 09. If the computer
does not respond, this light remains on.
INTERRUPT
S& I
This switch is in parallel with the MANUAL INTERRUPT
switch on the console and is used to manually interrupt the
computer program.
ENCODE
FUNCTION
S & I
This switch enables the typewriter to send to storage the
special function codes for backspace, tab, carriage return,
upper-case shift, and lower-case shift.
CLEAR
S& I
This switch clears the typewriter controls and sets the typewriter to lower case but does not cancel Encode Function.
TYPE
DUMP
TYPE
LOAD
REPEAT
6-4
CHARACTER CODES
Table 6-2 lists the internal BCD codes, typewriter printout and upper- or lower-case shift
that applies to the console typewriter. All character transmission between the computation section and the typewriter is in the form of internal BCD. The typewriter logic makes
the necessary conversion to the machine code.
NOTE
Shifting to upper case (57) or lower case (32) is .not necessary except on keyboard letters
where both upper and lower cases are available. The standard type set for the 3192 has two
sets of upper case letters and no lower case letters. This eliminates the need for specifying
a case shift.
TABLE 6-2. CONSOLE TYPEWRITER CODES
Print-out
-
J
K
L
M
N
0
p
Q
R
o
(degree)
$
*
#
%
Case
L
U or L
U or L
U or L
UorL
UorL
U or L
UorL
U or L
U or L
U
U
U
U
U
(Shift to UC)
(Space)
I
S
T
U
V
W
X
Y
Z
&
(
(Tab)
(Backspace)
(Carriage return)
L
U or L
U or L
U or L
UorL
U or L
U or L
U or L
U or L
U
U and L
U
Internal BCD Code
Print-out
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
Case
o
L
1
L
2
L
3
L
4
5
6
L
L
7
L
L
00
01
02
03
04
05
06
07
10
L
8
9
L
11
±
U
L
12
13
14
15
16
17
20
21
L
22
L
L
23
24
25
26
27
30
31
32
33
34
35
36
37
L
U
U
L
?
+
A
B
C
D
E
F
G
H
I
(Shift to LC)
U
U
U or
U or
U or
U or
U or
U or
U or
U or
U or
L
L
L
L
L
U and L
U
L
6-5
Internal BCD Code
@
U
!
L
Section 7
INSTRUCTIONS
GENERAL INFORMATION
INSTRUCTION WORD FORMATS
The standard 3200 machine coded instruction is 24 bits in length and generally classified
into one of two formats: word or character oriented.
Word oriented instructions are the most common of the instruction formats. Fifteen bits
are allocated for an unmodified storage address, operand, or shift count. Indirect addressing is usually available. Figure 7-1 illustrates a word oriented instruction and the significance of the first 15 bits when they represent an unmodified word address om' .
i
Bit position
18~14
23
I
(6 bits)
00
I( 1 bit) I(2 bits) I
(15 bits)
I
"--~
~'---y--/ ' - - - - - - - - - - - . .y . . . - - - - - - - - - /
- --.
---y--......--
a
f
d
b
j
I
m
k
y
Symbol designators
(See Symbol Definitions)
m
Word Address
00
Storage Field
Module
0-3
0-1
Co-ordinate Address
within field
0000-77778 (4096)
Figure 7 -1. Word-Addressed Instruction Format
Character oriented instructions allocate 17 bits for unmodified character addresses or
extended operands. Indirect addressing is not available for these instructions; however,
address modification is permissible by referencing a specific index register. Figure 7-2
illustrates the format of a character oriented instruction word and the significance of the
first 17 bits when they represent an unmodified character address 'r'.
7-1
18
23
I
'-
16
14
15
I( 1 bit) I
(6 bits)
Y
17
/~
b
I
(17 bits)
"-
/.1
Y
I
d
f
00
r
z
I
1
00 1
116
r
Character Address
I
I
1
I
1
1
116 15
I
,
14
02 01
13
I
I
I
I
~'-/'
Storage Field
Module
0-3
0-1
00
/~
Y
Co-ordinate Address
within field
0000-77778 (4096)
Character
0-3
Figure 7 -2. Character-Addressed Instruction Format
Characters in a data word are always specified in the following manner:
23
I
18
0
17
I
12
11
I
06 05
2
I
00
3
WORD ADDRESSES VS. CHARACTER ADDRESSES
It is often desirable to convert a word address and character position to its corresponding
character address or vice versa. The following procedure is a technique used for this purpose:
To convert a word address to a character address:
• Octally multiply the word address by four. (During program execution, this
operation is simulated by a left shift of two binary places.)
• Add the character position to the product.
The sum will be the character address.
EXAMPLE: Given: Word address 12442, character position 2
Find:
Corresponding character address.
1.
12442
~
52210
2.
~
52212
=
character address
To convert a character address to a word address:
• Octally divide the character address by four.
The quotient will be the word address and the remainder is the character position. No
remainder indicates character zero.
7-2
EXAMPLE:
Given: Character address 03442
Find:
Word address and character position.
00710
~03442
~
4
£
2 = remainder = character position 2.
NOTE
Octal multiplication and division
tables may be found in the appendix
section of this manual.
Instruction word formats that differ
from word and character orientation
are described in the instruction listing.
SYMBOL DEFINITIONS
The following designators are used throughout the list of instructions. Additional special
symbols are used in SearchlMove and certain I/O instructions and are defined where
they are used.
a = addressing mode designator (a=O, direct ~ddressing; a=l, indirect addressing)
b = index designator (unless otherwise stated)
c = d'enotes a character code or field
ch = denotes an I/O channel (0-7)
d = special operation designator (see individual instructions).
f = function code (6 bits, octal 00 to 77)
H = instruction modifier for INPC or OUTC indicating 6 or 12 bit I/O operation
i = interval designator (decrement quantity)
j = jump, stop, or skip condition designator (see individual instructions)
k
=
m
n
r
s
S
=
=
=
=
=
shift count (unmodified)
word execution address (unmodified)
same as m, but the word address of the second operand
character execution address (unmodified)
same as r, but the character address of the second operand
instruction modifier denoting sign extension
S present, bit 17="1", sign extended
S absent, bit 17 = "0", sign not extended
v = a specific register (00-77) within the Register File.
x = connect code or interrupt mask
y = 15-bit operand
z == 17-bit operand
IIIIIIII = indicates zeros should be loaded into a particular area of an instruction.
INDEXING AND ADDRESS MODIFICATION
In some instructions, the execution address 'm' or 'r', or the shift count 'k' may be modified
by adding to them the contents of an index register, Bb. The 2-bit designator 'b' specifies
which of the three index registers is to be used. Symbols representing the respective
modified quantities are M, R, and K.
M=m+(B b)
R = r + (B b) the sign of Bb is extended to bit 16 (217_1)
K =k +(B b)
In each case, if b=O, then M=m, R=r and K=k.
7-3
ADDRESSING MODES
Three modes of addressing are used in the computer: No Address, Direct Address, and
Indirect Address.
No Address
This mode is used when an operand 'y' or a shift count 'k' is placed directly into the lower
portion of an instruction word. Symbols 'a' and 'b' are not used as addressing mode and
index designators with any of the no address instructions.
Direct Address
The direct addressing mode is used in any instruction in which an operand address 'm'
is stored in the lower portion of the initial instruction word. This mode is specified by
making 'a' equal to O. In many instructions. address 'm' may be modified (indexed) by
adding to it the contents of register B b , M=m + (B b ).
Indirect Address
It is possible to use indirect addressing only with instructions that require an execution
address 'm'. For applicable instructions, indirect addressing is specified by making 'a'
equal to 1. Several levels (or steps) of indirect addressing may be used to reach the execution address; however, execution time is delayed in direct proportion to the number
of steps. The search for a final execUtion address continues until 'a' equals o. It is important to note that direct or indirect addressing and address modification are two distinct and independent steps. In any particular instruction, one may be specified without
the other. Figure 7 -3 shows the indirect addressing routine for a 3200 Computer.
Go to address M.
Acquire new
terms a, b, & m.
No
Original instruction
possibly containing
Execute instruction
using address M.
'a' and/or 'b'
No
Add the
b
(B ) to m.
Figure 7 -3. Indexing and Indirect Addressing Routine Flow Chart
NOTE
Unless it is otherwise stated, indirect addressing follows the above routine throughout the list of instructions.
7-4
INDEXING AND ADDRESSING MODE EXAMPLES
The following examples utilize the LDA (20) instruction; however, the process applies
to any of the instructions with an 'a' and/or 'b' designator.
LDA
23
I
18
20
17
I
16 15
14
00
m
a
a = addressing mode designator
b = index register designator
EXAMPLE 1
(ADDRESS MODIFICATION-(indexing) ONLY)
1
i
P=OOOOO
20 2
~
(8')
~ 13342
Add this address to (B2)
Indicates Dirtct Address
mode and address modification
by 8 2
J30
+ 13342
20 2 67772~ This address is replaced +--67772
temporarily in the
original instruction
LDA with the 24-bit quantity stored at address 67772
p=
67771
67772
77700000 ......... This quantity is loaded into the A register
67773
EXAMPLE 2
(INDIRECT ADDRESSING ONLY)
I
1
204~
P=00001
+
Indicates Indirect Addressing
mode but no address modification
(indexing).
Go to this address and acquire
new address and designator before
executing instruction.
[-----
- -
I
--
54427
54430
54431
310
77111
::::?-----'l
This portion of operand is replaced temporarily
in the original instruction.
~
200~
t
Indicates Direct Address mode and no address modification. LDA with the 24-bit
operand stored at address 77111. (If this digit would have indicated additional indirect
addressing and/or address modification this must be done before the LDA instruction
is executed.)
7-5
EXAMPLE 3
(INDIRECT ADDRESSING AND ADDRESS MODIFICATION)
P
=
00002
20
I
5~
Indi~tes
Indirect Address
mode and address modification. By B1.
(B')~00512
Add this address to (B1) .
•
54430
+00512
55142
t
Go to this address and acquire
~~~~~~~~~~~~~~~~~~~~~~~~~-new address and designatOr befora
executing instruction.
55141
55142
55143
7~:~ 1
This portion of operand is replaced
temporarily in the original instruction.
~
20 0 37777
Indicates direct tddress mode and no
address modification. LDA with the 24-bit
operand stored at address 37777. (If this
digit would have indicated additional indirect
addressing and/or address modification, this must
be done before the LDA instruction is executed.)
Trapped Instructions
The instructions appearing in Table 7-1 are executed by the Utility System under the
control of SCOPE. The Basic Utility software system also is capable of executing these
instructions.
The computer detects the 55-70 instructions as they appear in the F register and traps
them if the BCD and Floating Point 48-bit Precision hardware is absent. Trapped instructions are processed as interrupts once they are detected. A conventional interrupt
always takes priority over the trap sequence. The following operations occur when a
trapped instruction is detected:
1. P + 1 is stored in the lower 15 bits of address 00010.
2. The upper 6 bits of F are stored in the lower 6 bits of address 00011; the upper
18 bits remain unchanged.
3. Program control is transferred to address 00011 and an RNI cycle is executed.
7-6
TABLE 7-1.
L.IST OF TRAPPED INSTRUCTIONS
Operation Field
55
56
57
60
61
62
63
64
65
66
67
70
- - - -
MUAQ
DVAQ
FAD
FSS
FMU
FDV
LDE
STE
ADE
SSE
SFE
EZJ,EQ
EZJ,LT
EOJ
SET
Interpretation
I. R.T., 48-bit precision
Multiply AQ, 48-bit precision
Divide AQ, 48-bit precision
Floating point add
Floating point subtract
Floating point mUltiply
Floating point divide
Load ED
Store ED
Add to ED
Subtract from ED
Shift ED
ED zero jump, ED = 0
ED zero jump, ED < 0
ED overflow jump
Set D register
INSTRUCTION LIST
Each group of instructions is introduced with an index and, whenever necessary, a group
description. Individual instructions are all presented in the same basic format:
• Heading, which includes the assembly language mnemonic and instruction
name
• Machine code instruction format
• Instruction description
• Comments (when necessary)
• Approximate instruction execution time (add 1.25 usec for each step of indirect addressing)
The abbrev:iation, RNI, is used throughout the list of instructions to indicate the Read Next
Instruction sequence. This is a sequence of steps taken by the control section to advance the
computer to its next program step. For an extensive description of this sequence, consult
the 3200 Customer EngineerinK Manual (Pub. No. 60100900).
Table 7-2 identifies the instructions and indicates on which page explicit instruction descriptions may be found. Table 7-3 is a summary of the instruction execution times. In addition to
these tables, three additional tables are provided at the end of this manual for cross reference
of the instruction list.
7-7
TABLE 7-2. INSTRUCTION SYNOPSIS AND INDEX
PAGE
INSTRUCTION
MNEMONIC
ADA. I
ADAQ, I
add to A
add to AQ
7-40
ADE
7-47
AEU
add to E
transmit (A) to E upper
AlA
transmit (A)
ANA. S
logical product (AND) of y and (A)
ANI
logical product (AND) of y and (B
ANQ, S
logical product (AND) of y and (Q)
7-18
AQA
transmit (A)
(Q) to A
transmit (AQ) to E
7-26
AQE
7-38
+
7-29
b
(B ) to A
7-26
7-18
b
)
7-18
+
7-29
jump if (A) =
AQJ, EQ
Q
7-36
~ Q
7-36
jump if (A)
~
Q
7-36
jump if (A)
<
Q
7-36
jump if (A)
NE
compare A with Q
{
GE
LT
ASE, S
skip next instruction, if (A)
=
y
ASG, S
skip next instruction, if (A)
~
y
jump if (A) = 0
jump if (A) ~ 0
jump if (A) ~ 0
AZJ, EQ
NE
GE
LT
7-13
7-14
compare A with zero
{
jump if (A)
<
0
7-35
7-35
7-35
7-35
CINS
copy internal status
7-62
CON
COpy
connect
copy external status
7-70
7-60
CPR, I
within limits test
7-53
CTI
set console typewriter input
7 -71
CTO
set console typewriter output
7-71
DINT
disable interrupt control
7-67
DVA, I
DVAQ, I
EAQ
divide AQ (48 by 24)
divide AQE (96 by 48)
transmit (E upper) to A and (E lower) to Q
ECHA. S
enter A with 17-bit character address
EINT
ELQ
enable interrupt control
transmit (E lower) to Q
ENA
enter A
ENI
ENQ
enter index
enter Q
7-39
7-42
7-29
7-15
7-60
7-29
7-15
7 -15
7-15
7-49
7-29
7-64
7-49
7-49
7-43
7-44
7-44
7-44
EOJ
jump to m on E overflow
EUA
transmit (E upper) to A
EXS
sense external status
EZJ, EQ
compare E with zero; jump if E
=
0
<
0
FAD, I
compare E with zero; jump if E
floating add to AQ
FDV, I
floating divide AQ
FMU, I
floating multiply AQ
FSB, I
floating subtract from AQ
LT
7-8
TABLE 7-2. INSTRUCTION SYNOPSIS AND INDEX (CONTINUED)
PAGE
INSTRUCTION
MNEMONIC
HLT
unconditional stop; read next instruction
from location m
b
transmit (B )
(A) to Bb
7-30
IAI
IAPR
interrupt associated processor
7-66
IJD
index jump; decrement index
7-34
IJI
index jump; increment index
7-33
+
7-26
INA
increase A
7 -16
INAC,INT
character-addressed input to A
7-80
INAW,INT
word-addressed input to A
7-82
INCL
clear interrupt
7-65
INI
increase index
7 -16
INPC, INT, B, H
character-addressed input to storage
INPW, INT, B, N
INQ
word-addressed input to storage
increase Q
7-72
7-74
INS
sense internal status
7-62
INTS
sense interrupt
clear 1/0, typewriter, and S/M
7-61
10CL
7-63
index skip; decrement index
7-19
ISD
ISE
skip next instruction, if (B
ISG
skip next instruction, if (B
lSI
index skip; increment index
LACH
load A character
LeA, I
LCAQ, I
load A complement
load AQ complement (double precision)
LDA, I
LDAQ, I
load A
load AQ (double precision)
LDE
load E
load index
LDI. I
LDL, I
LDQ, I
b
b
y
7 -13
2 Y
7 -14
) =
)
load logical
load Q
LPA, I
logical product with A
LQCH
load Q character
MEQ
masked equality search
MOVE,INT
move
MTH
masked threshold search
MUA, I
MUAQ, I
multiply A
OTAC,INT
OTAW,INT
character-addressed output from A
word-addressed output from A
OUTC, INT, B, H,
character-addressed output from storage
OUTW, INT, B, N
word-addressed output from storage
PAUS
I
7 -16
characters from r to s
mUltiply AQ
7 -19
7-20
7-21
7 -21
7-20
7 -21
7-48
7-22
7 -21
7-22
7-37
7-22
7-54
7-58
7-55
7-39
7-42
7-84
7-86
7-76
7-78
7-64
QEL
pause
transmit (Q) to E lower
QSE, S
skip next instruction, if (Q) =
QSG, S
RAD, I
skip next instruction, if (Q) 2 Y
7 -13
7-14
replace add
7-38
RTJ
return jump
7-32
7-9
7-29
y
TABLE 7-2. INSTRUCTION SYNOPSIS AND INDEX (CONTINUED)
MNEMONIC
INSTRUCTION
PAGE
SACH
store character from A
7-23
SBA, I
subtract from A
7-39
SBAQ, I
subtract from AQ
7-40
SBCD
set BCD fault
7-67
SBE
subtract from E
7-47
SCA, I
selectively complement A
scale AQ
7-37
SCAQ
SCHA. I
store 17-bit character address from A
7-25
SCIM
selectively clear interrupt mask
7-66
SEL
select function
7-70
SET
7-46
SFE
set D to value of y
shift E
SFPF
set floating point fault
7-67
SHA
shift A
7-50
SHAQ
shift AQ
7-52
SHQ
shift Q
7-52
SJ1
jump if key 1 is set
jump if key 2 is set
7 -31
SJ3
jump if key 3 is set
7-31
SJ4
jump if key 4 is set
7-31
SJ5
jump if key 5 is set
SJ6
jump if key 6 is set
7-31
7-31
SLS
selective stop
7 -31
SQCH
store character from Q
7-24
SRCE, INT
search character equality
7-56
SRCN,INT
7-56
SSA, I
search character inequality
selectively set A
SSH
storage shift
7-50
SSIM
selectively set interrupt mask
7-66
STA, I
STAQ, I
store A
store AQ
STE
store E
store index
7-23
7-24
7-48
SJ2
STI. I
STQ, I
7-52
7-49
7 -31
7-37
7-25
store Q
7-24
store 15- bit word address from A
transmit (A) to Bb
7-25
7-28
TIM
transmit (A) to high speed memory
b
transmit (B ) to A
b
transmit (B ) to high speed memory
TMA
transmit (high speed memory) to A
7-28
TMI
transmit (high speed memory) to Bb
7-28
TMQ
TQM
transmit (high speed memory) to Q
transmit (Q) to high speed memory
7 -27
7-27
SWA, I
TAl
TAM
TIA
7-27
7-27
7-28
UCS
unconditional stop
7 -31
UJP, I
unconditional jump
7-32
XOA, S
exclusive OR y and (A)
b
exclusive OR y and (B )
7-17
exclusive 0 R Y and (Q)
7-17
XOI
XOQ, S
7-10
7-17
TABLE 7-3. SUMMARY OF INSTRUCTION EXECUTION TIMES, .usee.
INSTRUCTION
MNEMONIC
ADA
ADAQ
ADE
AEU
AlA
ANA
ANI
ANQ
AQA
AQE
AQJ
ASE
ASG
AZJ
CINS
CON
COpy
CPR
CTI
CTO
APPROXIMATE
EXECUTION
TIME
EAQ
ECHA
EINT
ELQ
ENA
ENI
ENQ
EOJ
EUA
EXS
EZJ
1.3*
IAI
IAPR
IJD
IJI
INA
INAC
INAW
INCL
INI
INPC
INPW
APPROXIMATE
EXECUTION
TIME
1.3
1.3-1.7
1.3-1.7
1.3
1.9
1.9
1.9
1.9
2.5
2.5
3.8
2.5
3.8
8.0*
2.5
2.5
2.5
2.5
2.5
LACH
LCA
LCAQ
LDA
LDAQ
LDE
LDI
LDL
LDQ
LPA
LQCH
1.3-1.7
***
1.3-1.7
2.5-3.4
1.3
1.3
1.3
11.25
22.5*
HLT
INQ
INS
INTS
IOCL
ISD
ISE
ISG
lSI
2.5
3.8
11.5*
1.3*
1.3
1.3
1.3
1.3
1.3
1.3*
1.9
1.9
1.9
1.9
DINT
DVA
DVAQ
FAD
FDV
FMU
FSB
INSTRUCTION
MNEMONIC
MEQ
MOVE
MTH
MUA
MUAQ
1.3
OTAC
o TAW
OUTC
OUTW
1.3
1.3*
1.3
1.3
1.3
1.3*
1.3*
1.3-1.7
1.3*
PAUS
10.0-12.0*
20.0*
14.0-18.0*
10.0-12.0*
1.3
**
1.9
1.9
1.3
***
***
1.3
1.3
3.3
3.3
3.3
3.3
3.3
3.3
2.0 us-40 ms
1.3*
1.9
1.9
RAD
RTJ
3.8
2.5
n = number of words searched .
• = Trapped instruction in computers without the appropriate optional hardware package .
•• = Dependent upon interrupt response .
••• = Dependent upon a variable signal response time from an external source of equipment.
7-11
7.8-11.0
16.0-21.0*
QEL
QSE
QSG
SACH
SBA
SBAQ
SBCD
SBE
SCA
SCAQ
SCHA
SCIM
SEL
SET
SFE
SFPF
SHA
SHAQ
-
+ 4.2n
3.3
4.2 + 4.2n
4.2
2.5
2.5
3.8
1.3
11.5*
2.5
1.9-3.9
2.5
1.3
***
1.3*
1.3-4.3*
1.3
1.3-2.7
1.3-2.7
TABLE 7-3. SUMMARY OF INSTRUCTION EXECUTION TIMES, J.lsec. (CONTINUED)
INSTRUCTION
MNEMONIC
SHQ
SJ1-6
SLS
SOCH
SRCE
SRCN
SSA
SSH
SSIM
STA
STAO
STE
STI
STO
SWA
APPROXIMATE
EXECUTION
TIME
INSTRUCTION
MNEMONIC
1.3-2.7
1.3
1.3
2.5
3.3
3.3
2.5
3.8
1.3
2.5
3.8
8.0*
2.5
2.5
2.5
APPROXIMATE
EXECUTION
TIME
TAl
TAM
TIA
TIM
TMA
TMI
TMQ
TOM
1.3
1.8
1.3
1.8
1.8
1.8
1.8
1.8
UCS
UJP
1.3
XOA
XOI
XOQ
1.3
1.3
1.3
-
n = number of words searched.
Trapped instruction in computers without the appropriate optional hardware package.
*=
** =
*** =
Dependent upon interrupt response.
Dependent upon a variable signal response time from an external source of equipment.
REGISTER OPERATIONS WITHOUT STORAGE REFERENCE
Operation Field
Interpretation
Address Field
=
=
=
ASE, S
OSE, S
ISE
04
Y
y
y, b
Skip next Instruction If (A)
Skip next instruction if (0)
Skip next instruction if (Sb)
ASG,S
OSG,S
ISG
05
y
y
y, b
Skip next instruction if (A) ~ y
Skip next instruction if (0) ~ y
Skip next instruction if (Sb) ~ Y
ENA,S
y
y
Y
14
y
Enter A with y
ECHA, S 1 1
r
Enter A with 17 -bit character address
ENO,S
ENI
14
y
Enter 0 with y
Enter index with y
INA,S
INO,S
INI
15
XOA, S
XOO,S
XOI
16
ANA,S
ANO,S
ANI
17
lSI
ISD
SHA
SHO
10
SHAO
SCAO
13
y, b
Increase A by Y
Increase 0 by Y
I ncrease index by y
y
y
y, b
Exclusive OR of A and y
Exclusive OR of 0 and y
Exclusive OR of index and y
Y
y
y, b
12
Y
y, b
AND of A and y
AND of Q and y
AN D of index and y
y,
y,
y,
y,
Index skip, incremental
Index skip, decremental
Shift A
Shift 0
y
b
b
b
b
Shift AO
Scale AO
y, b
y, b
7-12
18 17 16 15 14
23
04
10
00
(Approximate execution time: 1.9 j.Lsec.)
I
y
b
b = index register designator
Instruction Description: If (B b ) = y, skip to address P
+
2; if not, RNI from address P
+
1.
Comments: If b=O, y is compared to zero.
ASE Skip Next.
Instruction if (A) =Y
18 17
23
15 14
00
(Approximate execution time: 1.9 j.Lsec.)
y
6
04
Instruction Description: If (A) = y, skip to address P
+
2; if not, RNI from address P
+
1.
Comments: Only the lower 15 bits of A are used for this instruction.
AS E.S Skip Next ,
Instruction if (A) =y
18 17
23
15 14
00
(Approximate execution time: 1.9 j.Lsec.)
04
4
y
Instruction Description: Same as ASE except the sign of y is extended. All 24 bits of A are
recognized.
aSE Skip Next
Instruction if (0) .=Y:
18 17
23
15 14
00
(Approximate execution time: 1.9 .j.Lsec.)
04
y
7
Instruction Description: If (Q)=y, skip to address P
+ 2; if not, RNI from address P + 1.
Comments: Only the lower 15 bits of Q are used for this instruction.
OS E.S Skip Next
Instruction if (Q) =y
18 17
23
15 14
00
(Approximate execution time: 1.9 j.Lsec.)
04
5
y
Instruction Description: Same as QSE except the sign of y is extended. All 24 bits of Q are
recognized.
7-13
23
18 17 1 6 1 5 14
I~G
$kipNext
II1$tructi(m if (8 b) 2: y
05
10
I
00
(Approximate execution time: 1.9 j.lsec.)
y
b
b = index register designator
Instruction Description: If (B b ) are equal to or greater than y, skip to address P
not, RNI from address P + 1.
Comments: If b = 0, y is compared to zero.
23
18 17
15 14
+
2; if
00
(Approximate execution time: 1.9 j.lsec.)
05
y
6
Instruction Description: If (A) are equal to or greater than y, skip to address P
RNI from address P + 1.
Comments: Only the lower 15 bits of A are used for this instruction.
23
18 17
15 14
+
2; if not,
00
(Approximate execution time: 1.9 j.lsec.)
05
y
4
Instruction Description: Same as ASG except the sign of y is extended. All 24 bits of A are
recognized. Positive zero (00000000) is recognized as greater than negative zero (77777777).
23
18 17
05
15 14
00
(Approximate execution time: 1.9 j.lsec.)
y
7
Instruction Description: If (Q) are equal to or greater than y, skip to address P
RNI from address P + 1.
Comments:
Q$~~~.SklP.Nij)(t
~tnstru;ction .if:(Qf 2; y
On~y
+ 2;
if not,
the lower 15 bits of Q are used for this instructIon.
23
18 17
05
15 14
5
00
y
(Approximate execution time: 1.9 ,Usec.)
Instruction Description: Same as QSG except the sign of y is extended. All 24 bits of Q are
recognized. Positive zero (00000000) is recognized as greater than negative zero (77777777).
7-14
23
18 17 16 1 5 14
ENI Enter Index with y
14
00
(Approximate execution time: 1.3 }1sec.)
I0 I
y
b
b = index register designator
Instruction Description: Clear index register Bb and enter y directly into it.
Comments: If b = 0, this is a no-operation instruction.
18 17
23
15 14
00
(Approximate execution time: 1.3 }1sec.)
14
y
6
Instruction Description: Clear the A register and enter y directly into A.
23
18 17
15 14
00
(Approximate execution time:
14
1.3 }1sec.)
y
4
Instruction Description: Same as ENA except the sign of y is extended.
23
18 17 16
00
(Approximate execution time: 1.3 }1sec.)
z
d = 0 for no sign extension
d = 1 for sign extension
Instruction Description: Clear A; then enter a 17 -bit operand z (usually a character address)
into A.
15 14
18 17
23
00
(Approximate execution time: 1.3 }1sec.)
14
7
y
Instruction Description: Clear the Q register and enter y directly into Q.
23
ENQ.S Enter Q with V
18 17
14
15 14
00
(Approximate execution time: 1.3 }1sec.)
5
y
Instruction Description: Same as ENQ except the sign of y is extended.
7-15
23
00
18 17 16 15 14
15
(Approximate execution time: 1.3 ,usec.)
I
10
y
b
b = index register designator
Instruction Description: Add y to (B b ).
Comments: If b = 0, this is a no-operation instruction. Signs of
23
18 17
and Bb are extended.
00
15 14
6
15
y
(Approximate execution time: 1.3 ,usec.)
y
Instruction Description: Add y to (A).
23
18 17
4
15
00
15 14
(Approximate execution time: 1.3 ,usec.)
Y
Instruction Description: Same as INA except the sign of
23
18 17
y
is extended.
00
15 14
(Approximate execution time: 1.3 ,usec.)
7
15
Instruction Description: Add
23
y
to (Q).
18 17
15
y
00
15 14
5
y
(Approximate execution time: 1.3 ,usec.)
Instruction Description: Same as INQ except the sign of
7-16
y
is extended.
,~~I,i'.• .,', : ~ ,
y
Instruction Description: Same as ANA except the sign of y is extended.
18 17
23
17
00
15 14
7
(Approximate execution time: 1.3 fJ,sec.)
y
Instruction Description: Enter the logical product (the AND function) of y and (Q) back
into the Q register.
18 17
23
00
15 14
ANQ,S AND of'Q;'andy
(Approximate execution time: 1.3 fJ,sec.)
17
5
y
Instruction Description: Same as ANQ except the sign of y is extended.
7-18
23
lSI Index Skip.
Incremental
00
18 17 16 15 14
(Approximate execution time: 1.9 J..Lsec.)
10 10 I
y
b
b = index register designator
Instruction Description: If(Bb)=y, clear Bbandskipto address P
and RNI from address P + 1.
+ 2; if not, add one to (B b)
Comments: The 10.0 instruction is a SSH (storage shirt) instruction. described later in this
chapter.
Instruction in F
IV
Increment (Bb) by 1
and
RNI@P+1
--
Yes
No
(Bb) = Y ?
"'
00
18 17 16 15 14
23
10
\1
I
Clear Bb
and
RNI@P+2
.,.
y
b
(Approximate execution time: 1.9 J..Lsec.)
b = index register designator
Instruction Description: If (B b) = y, clear Bb and skip to address P
from (B b) and RNI from address P + 1.
+
2; if not, subtract one
Comments: When b=O, RNI from P + 1 if y ~ 0; RNI from P +.2 if y
=
o.
Instruction in F
,
Decrement (Bb) by 1
and
RNI @ P + 1
--....
No
(Bb) = Y ?
7-19
Yes
..
~
Clear Bb
and
RNI@P+2
LOAD
Operation Field
LOAI
LACH
LeA.l
LOLl
LOAQ,I
LCAQ,I
LOQ,I
LQCH
LOU
20
22
24
27
25
26
21
23
54
Address Field
Interpretation
m,b
r,8'
m,b
m,b
m,b
m,b
m,b
r,8 2
m,b
Load
Load
Load
Load
Load
Load
Load
Load
Load
A
A Character
A Complement
A Logical
AQ
AQ, Complement
Q
Q, Character
Index
NOTE
The LDE instruction is described in the BCD section of the instructions.
23
18 17 16 1 5 14
00
(Approximate execution time:
2.5,usec.)
m
a = addressing mode designator
b = index register designator
b
m = storage address; M = m+(8 )
Instruction Description: Load A with a 24-bit quantity from the storage address specified by M.
Comments: Indirect addressing and address modification may be used.
23
00
18 17 16
22
(Approximate execution time: 2.5 ,usec.)
Ib I
I
i
I
;'6
I
02 01 00
00000-77777
I 0-3
.
'~--~v~----/~
word address
character
designator
If b = 1. r is modified by index
register 8'; R=r
(8').
If b = 0, r is not modified (r = R).
+
Instruction Description: Load bits 00 through 05 of A with the character from storage
specified by character address R. The A register is cleared prior to the load operation.
Comments: Indirect addressing may not be used. Characters are specified in storage as follows:
23
18 17
12 11
06 05
00
,7
character designators
NOTE
Since the sign of Bb is extended during character address modification, it is possible
to only reference within ± 16,38310 characters.
7-20
LeA· Load A,
23
·Complement
00
18 17 16 15 14
24
Ia I
(Approximate execution time: 2.5 f.lsec.)
b
m
a = addressing mode designator
b = index register designator
b
m = storage address; M = m +(B )
Instruction Description: Load A with the complement of a 24-bit quantity from storage address M.
Comments: Indirect addressing and address modification may be used.
23
00
18 17 16 1 5 14
(Approximate execution time:
2.5 f.lsec.)
m
a = addressing mode designator
b =index register designator
Instruction Description: Load A with the logical product (the AND function) of (Q) and the
24-bit quantity from storage address M.
23
00
18 17 16 1 5 14
25
Ia I
(Approximate execution time:
b
3.8 f.lsec.)
m
a = addressing mode designator
b = index register designator
m = storage address; M = m (B b)
+
Instruction Description: Load the A and Q registers with the 24-bit quantities from addresses
M and M +1, respectively.
Comments: Addresses 77776 and 77777 should be used only if it is desirable to have M and
M + 1 as non-consecutive addresses, since one's complement arithmetic is used to form M + 1.
23
00
18 17 16 15 14
(Approximate execution time: 3.8 f.lsec.)
m
a = addressing mode designator
b = index register designator
b
m = storage address; M = m (B )
+
Instruction Description: Load registers A and Q with the complement of the 24-bit quantities from addresses M and M + 1 , respectively.
Comments: Addresses 77776 and 77777 should be used only if it is desirable to have M and
M + 1 as non-consecutive addresses, since one's complement arithmetic is used to form M + 1.
7-21
23
18 17 16 15 14
00
(Approximate execution time:
m
2.5 fJ,sec.)
a = addressing mode designator
b = index register designator
m = storage address; M = m +
(B
b
)
Instruction Description: Load Q with a 24-bit quantity from storage address M.
Comments: Indirect addressing and address modification may be used.
23
18 17 16
00
H
23
:16
I
I
I
(Approximate execution time: 2.5 f.1.sec.)
020100:
00000-77777
I
0-3
~~----~y------/'-y-/
word address
character
designator
If b = 1, r is modified by
index register B2; R=r+(B2).
If b = 0, r is not modified (r = R).
NOTE
Since the sign of Bb is extended during character address modification, it is possible
to only reference with ± 16,38310 characters.
Instruction Description: Load bits 00 through 05 of Q with the character from storage
specified by character address R. The Q register is cleared prior to the load operation.
Comments: Indirect addressing may not be used. Characters are specified in storage as
follows:
18 17
23
o
23
,
I
12 11
,/
1
00
06 05
2
3
~
character designators
18 17 16 15 14
00
(Approximate execution time: 2.5 fJ,sec.)
m
a = addressing mode deSignator
b = index register designator
m = storage address (indexing not permitted)
Instruction Description: Load the specified index register, B b , with the lower 15 bits of the
operand stored at address m.
Comments: Indirect addressing may be used but address modification is not possible. During
indirect addressing only a and m are inspected. Symbol b from the initial instruction specifies which index register is to be loaded with the lower 15-bits from the storage address.
7-22
STORE
Operation Field
Address Field
Interpretation
STA,I
SACH
STAQ,I
STQ,I
SQCH
STU
SWA,I
SCHA
m,b
r,B2
m,b
m,b
r,B'
m,b
m,b
m,b
Store
Store
Store
Store
Store
Store
Store
Store
40
42
45
41
43
47
44
46
A
A, character
AQ
Q
Q, character
index
15-bit word address
17-bit character address
NOTE
The STE instruction is described in the BCD instruction section.
23
00
1 8 1 7 1 6 1 5 14
40
Ia I
(Approximate execution time:
2.5 ~sec.)
m
b
a = addressing mode designator
b = index register designator
b
m=storage address; M=m+(B )
Instruction Description: Store (A) at the storage address specified by M. The (A) remains
unchanged.
23
00
18 17 16
(Approximate execution time: 2.5 ~sec.)
42
: 16
I
02 01 00
I 0-3
00000-77777
i
I
~~----~v~----/~
word address
character
designator
If b = 1, r is modified by
index register B2; R=r+(B2).
If b = 0, r is not modified (r = R).
Instruction Description: Store the contents of bits 00 through 05 of the A register in the
specified character address. All of (A) and the remaining three characters in storage remain
unchanged.
Com ments: Indirect addressing may not be used. Characters are specified in storage as follows:
23
18 17
06 05
12 11
~ character
~
~
designators
00
~
NOTE
Since the sign of Bb is extended during character address modification, it is possible
to only reference within ± 16,38310 characters.
7-23
23
I
1 8 1 7 1 6 1 5 14
45
Ia I
00
(Approximate execution time: 5.8 }lsec.)
m
b
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Store (A) and (Q) in the storage locations specified by address M
and M + 1, respectively. The (A) and (Q) remains unchanged.
Comments: Addresses 77776 and 77777 should be used only if it is desirable to have M and
M + 1 as non-consecutive addresses, since one's complement arithmetic is used to form M + 1.
18 17 16 15 14
23
I
41
IaI
00
(Approximate execution time:
2.5 }lsec.)
m
b
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Store (Q) at the storage address specified by M. The (Q) remaIns
unchanged.
23
18 17 16
00
(Approximate execution time: 2.5 }lsec.)
43
: 16
I
02 01 00:
I 0-3
00000-77777
I
~~----~y~----/~
word address
character
designator
If b = 1. r is modified by
index register B'; R = r
(B').
If b = O. r is not modified. (r = R)
+
Instruction Description: Store the contents of bits 0 through 5 of the Q register in the specified character address. All of (Q) and the remaining three characters in storage remain unchanged.
Comments: Indirect addressing may not be used. Characters are specified in storage as follows:
23
18 17
12 11
06 05
00
NOTE
Since the sign of Bb is extended during character address modification, it is possible
to reference only within ± 16,38310 characters.
7-24
23
00
18 17 16 1 5 14
(Approximate execution time:
m
2.5 J.lsec.)
a = addressing mode designator
b = index register designator
m = storage address (indexing not permitted)
Instruction Description: Store the contents of the specified index register, B b , in the lowe!
15 bits of storage address m. The upper 9 bits of m and (B b ) remain unchanged.
Com ments: Indirect addressing may be used, but address modification is not possible.
During indirect addressing only a and m are inspected. The b designator from the initial
instruction specifies the index register that will have its contents stored. If b = 0, zeros
are stored in the lower 15 bits of m.
23
00
18 17 16 15 14
44
Ia I
(Approximate execution time: 2.5 J.lsec.)
m
b
a = addressing mode designator
b = index register designator
b
m = storage address; M = m +(B )
Instruction Description: Store the lower 15 bits of (A) in the designated address M. The upper
9 bits of M and all of (A) remain unchanged.
23
00
18 1 7 16 1 5 14
(Approximate execution time: 2.5 J1sec.)
m
a = addressing mode designator
b = index register designator
m = storage address; M =m+(B~
Instruction Description: Store the lower 17 bits of (A) in the address designated by M. The
upper 7 bits of M and all of (A) remain unchanged.
7-25
INTER-REGISTER TRANSFER, 24-BIT PRECISION
Operational Field
AQA
AlA
IAI
TIA
TAl
TMQ
TOM
TMA
TAM
TMI
TIM
Address Field
Interpretation
b
b
b
b
v
v
v
v
v,b
v,b
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
53
I
+
+
+
(Q) to A
(A)
b
(A)
(B ) to A
b
(B )
(A) to Bb
b
(B ) to A
(A) to Bb
(Register v) to Q
(Q) to Register v
(Register v) to A
(A) to Register v
(Register v) to Bb
b
(B ) to Register v
General Instruction Description
The 53 instruction is used to move data between the A and Q registers, the index registers, and the
Register File. The contents of the transferring register remain unchanged.
'A:Q.A 'trsns.ter fA)'
(Q).to A.
23
+
18 1 7 15 14 12 11
53
0
4
00
~
(Approximate execution time: 1.3 J1sec.)
Comments: (Q) remains unchanged. Bits 00 through 11 should be loaded with zeros.
23
18 17 16 15 14 12 11
53
101
b
1
4
00
(Approximate execution time: 1.3 J1sec.)
"
b = index register designator
Comments: The sign of (B b) is extended prior to the addition. Bits 00 through 11 should be
loaded with zeros.
':;;·:'&';.)l'ranst("· .CA)
1
«;>:£:(8 ,. .to
ah
23
18 1 7 16 1 5 14 12 11
53
111
b
00
14"
(Approximate execution time:
1.3 J1sec.)
b = index register designator
Comments: The sign of the original (B b ) is extended prior to the addition. The upper 9 bits
of the sum are lost when the sum is transferred to the index register. Bits 00 through 11
should be loaded with zeros.
7-26
18 17 16 15 14 12 11
23
b
53
00
1 1_
(Approximate execution time: 1.3 J,Lsec.)
0
b = index register designator
Comments: No sign extension on Bb. Prior to the transfer, (A) is cleared. If b= 0, zeros are
transferred to A. Bits 00 through 11 are loaded with zeros.
00
1817 16 15 14 12 11
23
(Approximate execution time:
1.3 J,Lsec.)
53
b = index register designator
Comments: The (A) remains unchanged. If b=O, this becomes a no-operation instruction.
Bits 00 through 11 should be loaded with zeros.
23
18 17 16 15 14 12 11 06 05 QO
5310.
v
=
•
v
I
(Approximate execution time: 1.8 J,Lsec.)
Register File number, 00- 778
Comments: Bits 06 through 11, 15 and 16 should be loaded with zeros.
23
"
"To.M
18 17 16 1 5 14 12 11 06 05 00
(Approximate execution time:
to ,Register- .v
531
• •
v
v = register file number, 00-778
Comments: Bits 06 through 11, 15 and 16 should be loaded with zeros.
7-27
1.8 J,Lsec.)
23
1 8 1 7 1 6 1 5 14 1 2 11 06 05 00
53
10_
2
_
v
(Approximate execution time: 1.8 ,Usec.)
v = register file number. 00-778
Comments: Bits 06 through 11, 15 and 16 should be loaded with zeros.
23
_v
18 17 16 15 14 12 11 06 05 00
531_
v
=
2
(Approximate execution time: 1.8 ,Usec.)
register file number. 00-778
Comments: Bits 06 through 11, 15 and 16 should be loaded with zeros.
23
1 8 1 7 1 6 1 5 14 12 11 06 05 00
53
10
I
(Approximate execution time: 1.8 ,Usec.)
b
3
_
v
b = index register designator
v = register file number. 00-778
Comments: Lower 15 bits of v are transferred to Bb. Bits 06 through 11 should be loaded
with zeros.
23
18 1 7 16 15 14 12 11 06 05 00
53
lib
(Approximate execution time: 1.8 ,Usec.)
3
_
v
b = index register designator
v = register file number. 00-778
Comments: Upper nine bits of v remain cleared. Bits 06 through 11 should be loaded with
zeros.
7-28
INTER-REGISTER TRANSFER, 48-BIT PRECISION
Operation Field
ELQ*
QEL*
EUA*
AEU*
EAQ*
AQE*
55
Address Field
Interpretation
- - - - -
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
- - - - - - - - - - -
(EL) to Q
(Q) to EL
(EU) to A
(A) to EU
(E) to AQ
(AQ) to E
*Trapped instruction if the Floating Point/Double Precision (FP/DP)
option is not present.
TRAPPED INSTRUCTIONS IF FP/DP ARITHMETIC OPTION IS NOT PRESENT
23
18 17
55
1 5 14
00
~
1-7
(Approximate execution time: 1.3
J,Lsec.) option present.
Instruction Description: The 48-bit E register is split into halves-Eu and EL. With the 55
instruction, data may be moved as a 48-bit word between E and AQ, or in halves between
A and EU or Q and EL.
Comments: Bits 00 through 14 should be loaded with zeros. 55.0 and 55.4·are no-operation
instructions, even with the option present.
7-29
STOP AND JUMPS
Operation Field
Address Field
Interpretation
HLT
SLS
UCS
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
RTJ
UJP,I
IJI
IJD
AZJ,EQ
NE
GE
LT
AQJ,EQ
NE
GE
LT
m
Unconditional stop; RN I from address m
Selective stop
Unconditional stop
Jump if key 1 is set
Jump if key 2 is set
Jump if key 3 is set
Jump if key 4 is set
Jump if key 5 is set
Jump if key 6 is set
Return jump
Unconditional jump
Index jump; increment index
Index jump; decrement index
Compare A with zero; jump if (A) = 0
Compare A with zero; jump if (A) ~ 0
Compare A with zero; jump if (A) ~ 0
Compare A with zero; jump if (A) < 0
Compare A with Q; jump if (A) = (Q)
Compare A with Q; jump if (A) ~ (Q)
Compare A with Q; jump if (A) ~ (Q)
Compare A with Q; jump if (A)< (Q)
00
77.70
77.77
m
m
m
m
m
m
m
m,b
m,b
m,b
m
01
02
03
m
NOTE
Two additional Jump instructions, EZJ and EOJ, are described under the BCD instructions.
A Jump instruction causes a current program sequence to terminate and initiates a new sequence
at a different storage location. The P register provides continuity between program steps and
always contains the storage location of the current program step. When a Jump instruction occurs,
a new address is entered into P. In most Jump instructions, the execution address m specifies the
beginning address of the new program sequence. The word at address m is read from storage,
placed in F, and the first instruction of the new sequence is executed.
Some of the Jump instructions are conditional upon a register containing a specific quantity or
upon the status of the Jump key on the console. If the condition is satisfied, the jump is made to
location m. If not, the program proceeds in its normal sequence to the next instruction.
23
18 17
00
00
15 14
a
(Approximate execution time:
m
indeterminate)
Instruction Description: Unconditionally halt at this instruction. Upon restarting, RNI from
address m.
Comments: Indirect addressing and address modification may not be used.
7-30
23
18 17
77
12 11
00
I~
70
(Approximate execution time: 1.3 p,sec.)
Instruction Description: Program execution halts if the Select Stop switch on the console
is set. RNI from address P + 1 when restarting.
Comments: Bits 00 through 11 should be loaded with zeros.
23
18 17
77
12 11
00
FI~A1
77
(Approximate execution time:
indeterminate)
Instruction Description: This instruction unconditionally stops the execution of the current
program. RNI from address P + 1 when restarting.
Comments: Bits 00 through 11 should be loaded with zeros.
23
18 17
15 14
00
(Approximate execution time: 1.3 p,sec.)
00
m
j
= jump
keys
to 6
Instruction Description: Jump to address m if Jump key j is set; otherwise, RNI from ad-
dress P
+
1.
Comments: Indirect addressing and address modification may not be used.
Instruction
in F
,
RNI from
address P
+
No
1
Jump key
j set?
7-31
Yes
Jump to
address m
23
18 17
00
00
15 14
7
(Approximate execution time: 2.5 ,usec.)
m
Instruction Description: The address portion ofm is replaced with the return address, P
Jump to location m + 1 and begin executing instructions at that location.
Comments: Indirect addressing and address modification may not be used.
+ 1.
+
Store address P
in the address
portion of (m)
Begin subroutine
with instruction
at address m
1
+
Return to m
for address P
+
23
00
18 17 16 15 14
(Approximate execution time: 1.3 ,usec.)
m
a = addressing mode designator
b = index register designator
m = storage address; M = m
(B b)
+
Instruction Description: Unconditionally jump to address M.
Comments: Indirect addressing and indexing may be used.
7-32
23
18 17 16 15 14
02
10
I
b
00
(Approximate execution time: 1.9 ,usec.)
m
b = index register designator
m = jump address
Instruction Description: If b = 1, 2, or 3, the respective index register is examined:
If (B~ = 00000, the jump test condition is not satisfied; RNI from address P + 1.
2. If (B b ) ~ 00000, the jump test condition is satisfied. One is added to (B~; jump to addres~
1.
m and RNI.
+ 1. Indirect
addressing and jump address modification may rwt be used. The counting operation is done
in a one's complement additive accumulator. Negative zero (77777) is not generated because
the count progresses from: 77775, 77776, to 00000 (positive zero) and stops. If negative zero
is initially loaded into B b , the count progresses: 77777, 00001, 00002, etc. In this case, the
counter must increment through the entire range of numbers to reach positive zero.
Comments: If b= 0, this is a no-operation instruction; RNI from address P
Instruction in F
RNI from
address P
+1
Jump to address
'm'; RNI
7-33
',JDlndexJump.
De~rementar
23
00
18 1 7 16 1 5 14
02
11
I
(Approximate execution time: 1.9 ,Usee.)
b
m
b = index register designator
m = jump address
I nstruction Description: If b = 1, 2 or 3, the respective index register is examined:
1. If (B b) = 00000, the jump test condition is not satisfied; RNI from address P
+ 1.
b
2. If (Bb)~OOOOO, the jump test condition is satisfied. One is subtracted from (B ); jump to
address m and RNI.
Comments: If b=O, this is a no-operation instruction; RNI from address P + 1. Indirect
addressing and jump address modification may not be used. If negative zero (77777) is initially loaded into B b , the count will decrement through the entire range of numbers to
reach 00000 before the program will RNI from P + 1.
Instruction in F
RNI from
address P
1
+
No
Subtract one
from (Sb)
Jump to address
'm'; RNI
7-34
, ':,¢~n'~ijl~~:c,Qmp~re
23
~lt~ero~:!JLJmt:r ':,
18 17 16 15 14
03
10
00
(Approximate execution time: 1.9 J.q:;ec.)
I
m
= jump designator (0-3)
m = jump address
I nstruction Description: The operand in A is algebraically compared with zero for an equality, inequality, greater-than or less-than condition (see table). If the test condition is
satisfied, program execution jumps to address m. If the test condition is not satisfied, RNI
from address P + 1.
Comments: Positive zero (00000000) and negative zero (77777777) give identical results when
j = 0 or 1. When j = 2 or 3, negative zero is recognized as less than positive zero. Indirect addressing and address modification may not be used.
Condition
Mnemonic
Jump
Designator j
Test Condition
EQ
NE
GE
LT
0
(A)=(O)
1
(A)~(O)
2
3
(A) ;::::(0)
(A)«O)
Instruction in F
,
RNI from
address P
+
No
1
""-
Is test condition
satisfied?
7-35
Yes
-'"
Jump to
address m'; RNI
~~(1~'~~~~ncUtj()n . . Compare
A;~j1h,QiJump .•.
23
00
18 17 1 6 1 5 14
03
m
\1 \
(Approximate execution time: 1.9 ,Usec.)
j = 0-3 jump designator (0-3)
m = jump address
Instruction Description: The quantity in A is algebraically compared with the quantity in
Q for equality, inequality, greater-than or less-than condition (see table). If the test con-
dition is satisfied, program execution jumps to address m. If the test condition is not satisfied, RNI from address P + 1.
Comments: This instruction may be used to test (Q) by placing an arbitrary value in A for
the comparison. Positive and negative zero give identical results in this test when j = 0
or 1. When j = 2 or 3, negative zero is recognized as less than positive zero. Indirect addressing and address modification may not be used.
Condition
Mnemonic
Jump
Designator j
EQ
o
(A)
=
NE
GE
1
2
3
(A)
-¥: (0)
LT
Test Condition
(0)
(A) ~ (0)
(A)
<
(0)
Instruction in F
,~
RNI from
address P
+
No
1
01
Is test condition
satisfied?
7-36
Yes
Jump to
address 'm'; RNI
LOGICAL INSTRUCTIONS WITH STORAGE REFERENCE
Operation
Field
SSA,I
SeA,1
LPA,I
35
36
37
23
Address
Field
Interpretation
m,b
m,b
m,b
Selectively set A
Selectively complement A
Logical product A
00
18 17 1 6 1 5 14
(Approximate execution time: 2.5 J.1sec.)
m
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Selectively set the bits in the A register to "1's" for all corresponding "1's" in the quantity at address M.
23
00
18 1 7 1 6 1 5 14
36
IaI
(Approximate execution time: 2.5 J.1sec.)
m
b
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Selectively complement the bits in the A register that correspond
to the set bits in the quantity at address M.
23
00
18 17 16 15 14
(Approximate execution time: 2.5 J.1sec.)
m
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Replace (A) with the logical product of (A) and (M).
7-37
ARITHMETIC, FIXED POINT, 24-BIT PRECISION
Operation Field
Address Field
Interpretation
ADA,I
RAD,I
SBA,I
MUA,I
30
34
31
50
m,b
m,b
m,b
m,b
Add to A
Replace add
Subtract from A
Multiply A
DVA.I
51
m.b
Divide A
18 17 16 15 14
23
I
30
Ia I
00
(Approximate execution time: 2.5 ,usec.)
m
b
a = addressing mode designator
b = index register designator
b
m =storage address; M = m
(B )
+
Instruction Description: Add the 24-bit operand located at address M to (A). The sum re-
places the original (A).
23
00
18 17 16 1 5 14
(Approximate execution time: 3.8 ,usec.)
m
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Replace the quantity at address M with the sum of (M) and (A).
The original (A) remains unchanged.
7-38
23
00
18 17 16 15 14
SBA Subtract from A
31
Ia I
b
(Approximate execution time: 2.5 flsec.)
m
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Subtract the 24-bit operand located at address M from (A). The
difference is transferred to A.
23
00
18 17 16 15 14
50
II
a
(Approximate execution time:
flsec.)
m
b
7.8-11.0
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Multiply (A) by the operand located at address M. The 48-bit product
is displayed in QA with the lowest order bits in A.
23
00
18 17 16 15 14
(Approximate execution time: 11.25 flsec.)
m
a = address mode designator
b = index register designator
m = storage address; M = m
+ (B
b
)
Instruction Description: Divide the 48-bit operand in AQ by the operand at storage address
M. The quotient is displayed in A and the remainder with sign extended is displayed in Q.
If a divide fault occurs, the operation halts and program execution advances to the next
address. The final (A) and (Q) are meaningless if a divide fault occurs.
7-39
ARITHMETIC, FIXED POINT, 48-BIT PRECISION
Operation Field
ADAQ,I
SBAQ,I
*MUAQ,I
*DVAQ,I
32
33
56
57
Address Field
Interpretation
m,b
m,b
m,b
m,b
Add to AQ
Subtract from AQ
Multiply AQ
Divide AQ
*Trapped instruction if arithmetic option is not present.
This group of instructions may use indirect addressing and address modification. The A and Q
registers function as a single 48-bit register with the highest order bits in A. Address 77777 is not
recommended for use with this group of instructions.
23
32
a
b
m
00
18 17 1 6 1 5 14
=
IaI
b
addressing mode designator
register designator
b
storage address; M = m
(B )
= index
=
(Approximate execution time: 3.8 J.Lsec.)
m
+
Instruction Description: Add the 48-bit operand located in addresses M and M
+
1 to
(AQ). The sum is displayed in AQ.
Comments: The upper 24 bits of the 48-bit operand in memory are contained at address M.
23
18 1 7 1 6 1 5 14
00
(Approximate execution time: 3.8 J.Lsec.)
m
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Subtract the 48-bit operand located in addresses M and M
from (AQ). The difference is displayed in AQ.
7-40
+
1
HOLDS THE LOWER 48 BITS OF A 96-BIT
DIVIDEND PRIOR TO EXECUTING A DVAO
INSTRUCTION
DIVIDE:
HOLDS A 48-81T REMAINDER AFTER
EXECUTING A DVAQ INSTRUCTION
MULTIPLY:
HOLDS THE LOWER 48 81TS OF A PRODUCT
AFTER EXECUTING AN MUAO INSTRUCTIDN
47
UPPER 48 BITS OF A - - - - - - - - - - - - - - - 96-BIT DIVIDEND
95
01 V IDE - - - - - - - - - - - - - - - - -
48-BIT DIVISOR
47
48
00
I
I
23
00
.,'
·~v.~. :.~~ :t~~4~. .·;·.g. htt.~
x•.......
f
A.x ..... :...;.
23
I
23
·.}i{flld~I'I1J.t'~.~~ii!!flW~Im'i~t.ij~;
4B-BIT MULTIPLICAND.
AFTER EXECUTING AN MUAQ INSTRUCTION - - - - - - - - - - - AO HOL OS THE UPPER 48 BITS OF THE
96-BIT PRODUCT
. ~...t~ .'
MU L TIP L Y
- - - - - - - - - - - - - - - 4B-BIT MULTIPLIER
Figure 7 -4. Operand Formats and Bit Allocations for MUAQ and DVAQ Instructions
00
i. -... ':; .. ,':.;.: . .~~ .
I
TRAPPED INSTRUCTIONS IF FP/DP ARITHMETIC OPTION IS NOT PRESENT
23
MUAQ Multiply AQ
I
00
18 17 16 15 14
56
Ia I
b
m
(Approximate execution time:
16.0-21.0 j..Lsec.)
a = addressing mode designator
b = index register designator
b
m = storage address: M = m
(B )
+
Instruction Description: Multiply (AQ) by the 48-bit operand in addresses M and M
The 96-bit product is displayed in AQE.
Comments: Refer to Figure 7-4 for operand formats.
23
DVAQ
57
Ia I
1.
00
18 1 7 16 1 5 14
Dlv·ide AQ
+
(Approximate execution time: 22.5 j..Lsec.)
option present.
m
b
a = addressing mode designator
b = index register designator
b
m = storage address: M = m
(B )
+
Instruction Description: Divide (AQE) by the 48-bit operand in addresses M and M + 1.
The quotient is displayed in AQ, and the remainder with its sign extended is displayed in E.
Comments: If a divide fault occurs, program execution advances to the next address. The
final contents of AQ and E are meaningless if a divide fault occurs. Refer to Figure 7-4 for
operand formats.
7-42
ARITHMETIC, FLOATING POINT
Operational Field
Address Field
Interpretation
*FAD.I
60
*FSB.I
*FMU,I
*FDV,I
61
62
m.b
m,b
m,b
m,b
FP
FP
FP
FP
63
addition to AQ
subtraction from AQ
multiplication of AQ
division of AQ
*Trapped instruction if Floating Point/Double Precision FP/DP arithmetic option is
not present.
GENERAL FLOATING POINT /OOUBLE PRECISION NOTE
Figure 7-5 illustrates operand format and bit allocations for floating point instructions. Refer to
the Floating Point section of Appendix B for additional floating point considerations and examples.
TRAPPED INSTRUCTION IF FP/DP ARITHMETIC OPTION IS NOT PRESENT
23
18 17 16 1 5 14
60
IaI
b
00
I
m
(Approximate execution time:
10.0-12.0 ,usee.) option present.
a = addressing mode designator
b = index register designator
b
m = storage address; M = m
(B )
+
Instruction Description: Add the 48-bit operand located in addresses M and M + 1 to (AQ).
The rounded and normalized sum is displayed in AQ.
Comments: The higher order bits of E hold the portion of the operand,that was shifted out of AQ
during exponent equalization.
Refer to Figure 7-5 for operand formats.
7-43
TRAPPED INSTRUCTIONS IF FP/DP ARITHMETIC OPTION IS NOT PRESENT
23
00
18 17 1 6 1 5 14
(Approximate execution time:
m
10.0-12.0,usec.) option present.
a = addressing mode designator
b = index register designator
b
m = storage address: M = m
(B )
+
Instruction Description: Subtract the 48-bit floating point operand located at storage addresses
M and M + 1 from the floating point operand in AQ. The rounded and normalized difference is displayed in AQ.
Com ments: The upper order bits of E hold the portion of the operand that was shifted out of AQ
during the equalization of exponents. Refer to Figure 7-5 for operand formats.
23
I
00
18 17 16 15 14
62
IaI
b
(Approximate execution time:
14.0-18.0 ,usec.) option present.
m
a = addressing mode designator
b = index register designator
b
m = storage address: M = m
(B )
+
Instruction Description: Multiply the 48-bit floating point operand in AQ by the floating
point operand located at storage addresses M and M + 1. The rounded and normalized
product is displayed in AQ.
Comments: Bits of 12-47 of E hold the lower 36 bits of the 72-bit unnormalized product. Refer
to Figure 7-5 for operand formats.
23
00
18 17 1 6 1 5 14
m
(Approximate execution time: 20.0 ,usec.)
option present.
a = addressing mode designator
b = index register designator
b
m = storage address: M = m
(B )
+
Instruction Description: Divide the floating point operand in AQ by the 48-bit floating point
operand located at storage addresses M and M + 1. The rounded and normalized quotient is
displayed in AQ. The remainder with sign extended appears in the E register.
Comments: The sign of the remainder is the same as that of the dividend. Refer to Figure
7-5 for operand formats.
NOTE
The divisor must be properly normalized or a divide fault will result. Refer to Interrupt
conditions, Section 4.
7-44
THIS BIT
RECEIVES
47 46
24 23
I
{
I
I
I
I
00 23
0100
i
I
4746
3635
1
I (
00
I
I
I
1
1
23 22 21
1
I
I
I
I
I
00 23
12 II
00
I
I
I
~---_v----J"'----------------------v_--------------------J
, ''-----------------,,.------------------1
1 ,I
I
EXPONENT
BIAS BIT
I
I
23 22 21
:[1
\
0100
I
I
I
}
ROUNDING
WHEN
APPLICABLE
EXPONENT
BIAS BIT
11_ B IT EXPONENT
36-BIT COEFFICIENT
36-BIT COEFFICIENT
11- BIT EXPONENT
SIGN BIT
{SIGN BIT (COMPARED
TO BIT 47 OF E FOR
ROUNDING TEST)
1
FP
OPERAND
----------------------~.I
~I.-------------------------FP
(EXPONENT AND FIRST 36 COEFFICIENT
BIT RESULTS OF ALL FLOATING
POINT OPERATIONS)
OPERAND FROM
STORAGE
----------------------------~.I
1
.... ' - - - - - - - - - - - - - - E REGISTER - - - - - - - - - - - - - - - - + 1 . 1
I
I
1
~I'-------------- EU-----------------~·+I·r-------------EL---------------~·I
1
I
1
1
:47 146
1
24 123
121"
I
I
I
I
I
I
00 23
12 II
001
I
I
00
I
I
--__0.0+01,>---------------
REMAINDER FOR FDV
------------------..I.j
I
MAGNITUDE BIT (COMPARED TO}
BIT 47 OF AO FOR ROUNDING
TEST)
"'1"--------------
LOWER 36 COEFFICIENT BITS ---------~~I
FROM FMU OPERATION
I
1
~
"'1'------------
~
I
MEANINGLESS
RESULTS FOR
I
F~DO::RBA:I~~S
THAT PART OF THE OPERAND SHIFTED INTO --------.~I
THE E REGISTER DURING FAD OR
FSB EXPONENT EQUALIZATION
Figure 7 -5. Operand Formats and Bit Allocations for Floating Point Arithmetic Instructions.
BCD
Operational Field
*SET
*ADE
*SBE
*LDE
*STE
*SFE
*EZJ,EQ
*EZJ,LT
*EOJ
Address Field
70
66
67
64
65
70
Interpretation
Set D register
Add to E
Subtract from E
Load E
Store E
Shift E
E zero jump, E = 0
E zero jump, E < 0
E overflow jump
Y
m,b 3
m,b 3
m,b'
m,b 2
k,b
m
m
m
*Trapped instruction if BCD arithmetic option is not present.
GENERAL BCD INSTRUCTION NOTE
Refer to the BCD arithmetic section of Appendix B for additional BCD considerations and examples.
TRAPPED INSTRUCTIONS IF BCD ARITHMETIC OPTION IS NOT PRESENT
23
18 17
70
04 03 00
15 14
7
y
(Approximate execution time: 1.8 J-lsec.)
option present.
'-~
only the lower 4 bits
are recognized.
y=field length designator
Instruction Description: Load the lower 4 bits of y into the 4-bit D register.
Comments: (D) remains the same until replaced by a new 4-bit operand. In LDE and STE
operations dealing with equal size fields, the D register is loaded only once with a SET instruction. If y = 0, subsequent LDE, STE, ADE and SBE instructions are processed as no-ops. Refer
to the BCD section of Appendix B for an example of a SET instruction execution.
7-46
TRAPPED INSTRUCTIONS IF BCD ARITHMETIC OPTION IS NOT PRESENT
23
00
1B 17 16
66
Ib I
(Approximate execution time: 11.5 J,Lsec.)
option present.
If B = 1, r is modified by
=r
(B3).
If b = 0, r is the unmodified
direct address (r = R).
+
(8 3); R
Instruction Description: A maximum field of 12 BCn numeric characters in storage may be
added to (En). The sum is displayed in En.
Comments. The characters in storage are in consecutive character positions. R specifies the
most significant character (MSC) of a field. The 4-bit D register specifies field length. The
(ED) are always right justified, i.e. the lowest significant digit of the operand is always in the
digit zero position.
NOTE
Since the sign of Bb is extended during character address modification, it is possible
to reference only within ± 16,38310 characters.
23
00
18 17 16
67
(Approximate execution time: 16.1 J,Lsec.)
option present.
Ib I
If b = 1, r is modified by (B3);
R= r
(B3).
If b = 0, r is the unmodified
direct address (r = R).
+
Instruction Description: A maximum field of 12 BCn characters in storage is subtracted
from (En). The difference is displayed in ED.
Comments: The characters in storage that comprise the subtrahend are located in consecutive
character positions. R specifies the most significant character of a field. The 4-bit D register
specifies the field length. The (ED) are always right justified, i.e. the lowest significant digit of
the operand is always in the digit zero position.
NOTE
Since the sign of Bb is extended during character address modification, it is possible to reference only within ± 16,38310 characters.
7-47
TRAPPED INSTRUCTIONS IF BCD ARITHMETIC OPTION IS NOT PRESENT
00
18 17 16
23
(Approximate execution time:
option present.
LDE LOild ED
64
I
8.0
f..lsec.)
I
:16
I
02 01 00:
I 0-3
00000-77777
,
~~-----y~----_/~
word
address
character position
within the word
+
If b = 1. r is modified by (B1); R=r
(B1).
If b = 0, r is the unmodified direct address.
Instruction Description: Load the ED register with a maximum field of 12 numeric BCD characters from storage.
Comments: Characters are loaded consecutively, starting with the least significant character
(LSC) at address R + (D-1) and continuing until the most significant character at address R is in
ED' (ED) is shifted right as loading progresses. The sign of the decimal operand is acquired
along with the LSC. Prior to executing this instruction, the field length must be specified with a
SET (70.7) instruction. The (ED) and always right justified, i.e., the lowest significant digit of
the operand is always in the digit zero position.
Refer to the BCD section of Appendix B for an LDE instruction execution example.
NOTE
Since the sign of Bb is extended during character address modification, it is possible to reference only within ± 16,38310 characters.
23
18 17 16
65
00
(Approximate execution time:
option present.
Ib I
8.0 f-Lsec.)
If b = 1, r is modified by the
(B2); R=r
(B2)
If b= 0, r is the unmodified
direct address (r = R).
+
Instruction Description: Store a maximum field of 13 numeric BCI> characters from the ED
register into storage.
Comments: Characters are stored, beginning with the least significant character (LSC)
and the sign of the stored operand is acquired with this character. (ED) is shifted right as
the Store operation progresses, end off, until the entire field of characters is stored.
Prior to executing this instruction the field length must be specified with a SET (70.7)
instruction.
NOTE
Since the sign of Bb is extended during character address modification, it is possible to reference only within ± 16,38310 characters.
7-48
TRAPPED INSTRUCTIONS IF BCD ARITHMETIC OPTION IS NOT PRESENT
23
00
18 17 16 1 5 14
70
10
I
b
I
(Approximate execution time:
1.3-4.3 J,Lsec.) option present.
k
b = index register designator
k = shift designator
Instruction Description: This instruction shifts BCD characters within the ED register in
single character (4-bit) shifts.
Comments: k is added to (B b) to modify the shift designator; K = k + (B b). The sign of Bb is
extended. The computer senses bits 00-03 and 23 of the sum. A left shift is performed if
bit 23 is zero; and a right shift if it is one. Shifts are end-off in both directions. For a left
shift, the complement of the lower 4 bits of the sum specify the shift magnitude.
Examples:
If K = 00000006, shift left 6 character positions.
If K = 77777771, shift right 6 character positions.
23
18 17
4
70
00
15 14
(Approximate execution time: 1.3 J,Lsec.)
option present.
m
m = jump address
Instruction Description: This instruction compares (ED) with zero. If (ED) = 0, jump to
address m; if not, RNI from address P + 1.
23
70
00
15 14
18 17
5
(Approximate execution time: 1.3 J,Lsec.)
option present.
m
m = jump address
Instruction Description: This instruction compares (ED) with zero. If (ED) < 0, jump to
address m; if not, RNI from address P + 1.
23
15 14
18 17
70
6
m
00
m
=
(Approximate execution time: 1.3 J,Lsec.)
option present.
jump address
Instruction Description: Jump to address m if the overflow digit (digit 13) of the ED register receives a character indicating that ED had overflowed. The overflow condition is also true where
an ADE or SBE causes an end-off carry in the overflow digit. If overflow has not occurred, RNI
from address P + 1.
7-49
STORAGE SHIFT, SEARCHES, COMPARE AND REGISTER SHIFTS
Operation Field
SSH
SHA
SHQ
SHAQ
SCAQ
CPR.I
MEQ
MTH
Address Field
10
12
Interpretation
m
y,b
y,b
y,b
y,b
m,b
m,i
m,i
13
52
06
07
23
18 17
Storage shift
Shift A
Shift Q
Shift AQ
Scale AQ
Compare (within limits test)
Masked equality search
Masked threshold search
15 14
00
(Approximate execution time: 3.8 ,usec.)
100m
m = storage address
Instruction Description: Sense bit 23 of the Quantity stored at address m. Shift (m) one
place left, end around, and replace it in this same storage location. Ifbit 23 = "0" (positive),
RNI from P + 1; if negative ("I"), RNI from P + 2.
Comments: Address modification may not be used.
23
00
18 17 16 15 14
12
I I
0
b
(Approximate execution time:
I
k
1.3-2.7 ,usec.)
b = index register designator
b
k=shift count; K=k
(B )
+
Instruction Description: (B b ) and k, with their signs extended, are added. If b=O, the sign of
k is still extended. The sign and magnitude of the 24-bit sum determine the direction and
magnitude of the shift. The computer senses only bits 00-05 and 23 of the sum for this information. For left shifts, the shift magnitude is placed in k; to shift right, the complement
of the shift magnitude is placed in k.
Examples: (b=O in both cases):
Shift left six positions:
k = 00006
Shift right six positions:
k = 77771
Comments: During left shifts, bits reaching the upper bit position of the A (during SHA)
or Q (during SHQ) registers are carried end around. Therefore, a left shift of 24 places results in no change in (A) or (Q). A left shift that exceeds 24 places results in an effective
shift of K-24 (or K-48) places.
During right shifts, the sign bit is extended and the bits are shifted end-off. A right shift
of 23 or more places results in (A) or (Q) becoming all "O's'" or all "I's", depending upon the
original sign.
7-50
SHA/SHQ FLOW CHART
Instruction in F
Yes
No
Sign of k is
extended
"0"
Uppermost
bit of result equals
"0" or "1 "?
"1"
Shift will
be right
Shift will
be left
"0"
"1"
Shift A
RNI from
address P
+
7-51
23
00
18 17 16 15 14
12·
\ 1 \
(Approximate execution time:
k
b
1.3-2.7 J,lsec.)
b = index register designator
b
k = shift count; K = k
(B )
+
Instruction Description: Refer to SHA description.
23
00
18 17 16 15 14
13 10 1
(Approximate execution time: 1.3 J,lsec.)
b
k
b = index register designator
b
k=shift count; K=k
(B )
+
Instruction Description: (B b ) and k, with their signs extended, are added. If b=O, the sign of
k is still extended. The sign and magnitude of the 24-bit sum determine the direction and
magnitude of shift. The computer senses only bits 00-05 and 23 of the sum for this information. For a left shift, the magnitude is placed in k; to shift right, the complement of the
shift magnitude is placed in k.
Examples: (b = 0 in both cases):
Shift left three places:
Shift right three places:
k=00003
k=77774
During left shifts bits reaching the upper bit position of the A register are
carried end around to the lowest bit position of Q. Therefore, a left shift of 48 places results in no change in (AQ). A left shift exceeding 48 places results in an effective shift of
K -48 places.
During right shifts, the sign bit is extended and the bits are shifted end-off. A right shift
of 47 or more places results in (AQ) becoming all "O's" or all "l's", depending upon the
original sign.
Comments:
23
00
18 17 16 1 5 14
13 11 1
(Approximate execution time: 1.3 ,usec.)
b
k
b = index register designator
K = k minus the shift count
K---t Bb
Instruction Description: (AQ) is shifted left, end around, until the 2 highest order bits (46 and
47) are unequal. If (AQ) should initially equal positive or negative zero, 4810 shifts are executed before the instruction terminates. During scaling, the computer counts the number
of shifts. A quantity K, called the residue, is equal to k minus the shift count. If b = 0, this
quantity is discarded; ifb= 1,2, or 3, the residue is transferred to the designated index register.
7-52
~~,~,,~?'~pa~~. ""
23
,J
,iyVithin'L~",i,ts 'T,e$lt
18 17 16 15 14
00
(Approximate execution time:
2.5-3.4 fJ,sec.)
'
m
a = addressing mode designator
b = index register designator
m = storage address
Instruction Description: The quantity stored at address M is tested to see if it is within the
upper limits specified by A and the lower limits specified by Q. The testing proceeds as follows:
1. Subtract (M) from (A). If (M)
2. Subtract (Q) from (M). If (Q)
3. RNI from address P
+
> (A), RNI from address P
+
1; if not.
> (M), RNI from P + 2; if not,
3.
Comments: The final state of the (A) and (Q) registers remains unchanged. (A) must be
~
(Q) initially or the test cannot be satisfied. 77777777 is not sensed as negative zero. The
following table is a synopsis of the CPR test:
Test
Sequence
(Q)
>
>
(A)
~
(M)
(A)
(M)
(M)
Jump Address
if Test Satisfied
~
P+1
P+2
P+3
(Q)
CPR Instruction
in F
Subtract (M)
from (A)
Is (M)
>
(A) ?
Yes
·1
,
RNI from
P+1
No
Subtract (Q)
from (M)
Is (Q)
>
(M) ?
Yes
No
RNI from
P + 3
7-53
RNI from
P + 2
1
23
18 17
00
15 14
m
06
(Approximate execution time: 4.2+4.2n*
,usec.)
i = interval designator, 0 to 7
m
=
storage address
Instruction Description: (A) is compared with the logical product of (Q) and (M). This instruction uses index register Bl exclusively. m is modified just prior to step 3 in the test below.
Instruction Sequence:
1. Decrement (Bl) by i. (Refer to table below.)
2. If (Bl) changed sign from positive to negative, RNI from P + 1; if not,
3. Test to see if (A) = (Q) • (M). M = m+(Bl). If (A) =(Q) • (M), RNI from P
+ 2; if not,
4. Repeat the sequence.
Comments: i is represented by 3 bits, permitting a decrement interval selection from 1 to 8.
Address modification may not be used. Positive zero and negative zero are recognized as equal
quantities.
Designator
i
Decrement
interval
1
1
2
3
4
5
2
3
4
5
6
7
0
6
7
8
Initial Program Entry
Decrement
(8 1 ) by 'i'
RNI from
P+l
RNI from
P+2
*n = number of words searched
7-54
23
18 17
15 14
00
07
(Approximate execution time:
4.2+4.2n* p-sec.)
m
i = interval designator, 0 to 7
m = storage address
Instruction Description: (A) is compared with the logical product of (Q) and (M). This instruction uses index register B2 exclusively. m is modified just prior to step 3 in the test below.
Instruction Sequence:
1. Decrement (B2) by "1". (Refer to table below.)
2. If (B2) changed sign from positive to negative, RNI from P + 1; if not,
3. Test to see if (A) ~ (Q) • (M). M = m + (B2). If (A) ~ (Q) • (M), RNI from P +
2; if not,
4. Repeat the sequence.
Comments: i is represented by 3 bits, permitting a decrement interval selection from 1 to 8.
Address modification may not be used. Positive zero and negative zero are recognized as equal
quantities.
Designator
i
Decrement
interval
1
2
3
1
2
3
4
5
6
7
0
4
5
6
7
8
Initial program entry
Decrement
(8') by 'i'
RNI from
P+1
RNI from
P
*n = number of words searched
7-55
+2
SEARCH
Operation Field
Address Field
Interpretation
71
c,r,s
c,r,s
Search for character equality
Search for character inequality
SRCE,INT
SRCN,INT
GENERAL SEARCH/MOVE NOTE
The SEARCH and MOVE instructions are mutually exclusive. Attempts to execute
one while the other is in progress will cause a reject and a skip to address P + 2.
23
P
71
23
P+1
00
18 17 16
IINTI
s
30
register
20
Ie I
23
P + 2
(Approximate execution
time: 3.3 J,Lsec.)
00
18 17 16
c
register
00
Reject Instruction
= "0" for SRCE, equality
e
=" 1" for SRCN, inequality
e
INT = "1" for interrupt upon completion
s
= last character address ofthe search
block, plus one
c
=00-778, BCD code of search character
= first (current) character address of
the search block
Instruction Description: This instruction initiates a search through a block of character
addresses in storage looking for equality or inequality with character c. It is composed of
three words, including the two main instruction words plus a reject instruction.
As a Search progresses, r is incremented until the search terminates when either a comparison occurs between the search character c and a character in storage, or until r= s. If a
comparison does occur, the address of the satisfying character !hay be determined by inspecting r. To do this, transfer the contents of register 20 to A with instruction TMA
(53 0 20020).
Register 20 of the register file is reserved for the second instruction word which contains
the current character address of the search block. Register 30 is reserved for the first instruction word which contains the last character address, plus one of the search block.
Figure 7-6 is a flow chart of steps that occur during a search operation.
7-56
Load (address
P + 1) into Data
Register
Transfer (Data
Bus re gister)
to register 20
Transfer (F)
to register
30
Release R. F.
Initiate
Search
.--_ _ _ _ _ _--, Await
Priority
Search Control
Generates Block
Control Request
Read Up
Register 20
(Address P +
Restore
Register 20
1)
L.-_ _ _ _~
No increment
for first
character
e
=0
INT = 1
No
Yes
Figure 7 -6. Search Operation
(P)
Transfer
(S2) to
S Bus
I-~~"'"
Transfer r to
S2 register.
Load Search
Character C
into Data Bus
Register
Read Up
Regi,ster
Release Data
Bus; RNI from
Address P + 3
Restore
Register 30
(P)
MOVE
Operation Field
72
Address Field
MOVE,INT
Interpretation
l.r,s
72
23
l
characters from r to s
00
18 17 16
23
P
Move
(Approximate execution
time: 3.3 ,usec.)
s
IINTI
17 16
00
P+1
23
P+2
00
Reject Instruction
INT = "1" for interrupt
s
= first address of character block
destination
= field length of block, 0-1 778 *
= first address of character block
source
Instruction Description: This instruction moves a block of data, l characters long, from one
area of storage to another. It is composed of three words, including the two main instruction words, plus a reject instruction.
As a Move operation progresses, rand s are incremented and l is decremented untill = O.
128 characters or 32 words may be moved. When bits 00 and 01 of rand s are "0", and the
field length is a multiple of four characters, data is moved word by word. This reduces move
time by 75% over a character by character move.
Register 21 of the Register File is reserved for the second instruction word which contains
the first address of the character block source. Register 31 is reserved for the first instruction word which contains the first address of the character block destination.
Figure 7-7 is a flow chart of steps that occur during a Move operation.
* = 1-177s represents a field length of 1 to 127 characters; 0 represents a field length of 128 characters.
7-58
Load (Address
p + 1) into Data
Bus Register
Transfer (Data
Bus Register)
to Register 21
Transf~r (F)
to Register 31
Establish Word
or Character
Move
Establish First
Word or Character
Release R. F.
Initiate Move
Release Data
Bus RNI From
Address P +- 3
Increm ent L
Read Up
Register 21
(Address P + 1)
f---..-+i by 1 for
Character Move
Increment L
by 4 for
Word Move
No Increment
for First Word
or Character
Restore Register
31 (Save in restoration register)
Set Character
Address in S2
for correct
shift
Figure 7-7. Move Instruction
SENSING
Operation
Address
Interpretation
77.2
EXS
COpy
x,ch;x~O
Sense external status
X,cn;x = 0
Copy external status
77.4
INTS
x,ch
Sense interrupt
77.3
INS
CINS
x,ch;x~O
Sense internal status
Copy internal status
x,ch;x=O
23
18 17 15 14 12 11
77
2
I
ch
I
00
(Approximate execution time: 1.3-1.7 f..tsec.)
x
ch = liD channel designator, 0-7
x = external status sensing mask code
(see Comments below)
Instruction Description: When a peripheral equipment controller is connected to an 110
channel by the CON (77.0) instruction, the EXS instruction can sense conditions within
that controller. Twelve status lines run between each controller and its 110 channel. Each
line may monitor one condition within the controller, and each controller has a unique set
of line definitions. To sense a specific condition, a "I" is placed in the bit position of
the status sensing mask that corresponds to the line number. When this instruction is recognized in a program, RNI at address P + 1 if an external status line is active when its
corresponding mask bits are "I". RNI at address P + 2 if no selected line is active.
Comments: Refer to the 3000 Series Computer Systems Peripheral Equipment Codes manual
(Pub. No. 60113400) for a complete list of status response codes.
23
18 17 15 14 12 11
77
2
I
ch
I
00
(Approximate execution time: 1.3-1.7 f..tsec.)
0000
ch = liD channel designator, 0-7
Instruction Description: This instruction performs the following functions:
The external status code from 110 channel ch is loaded into the lower 12 bits of A. See
EXS instruction.
2. The contents of the Interrupt Mask register are loaded into the upper 12 bits of A. See
Table 7-4.
3. RNI from address P + 1.
1.
7-60
TABLE 7-4. INTERRUPT MASK REGISTER BIT ASSIGNMENTS
Mask Bit
Positions
Mask Codes (x)
Interrupt Conditions Represented
0001
0002
0004
0010
0020
0040
0100
0200
0400
1000
2000
4000
00
01
02
03
04
05
06
07
08
09
10
11
23
External equipment interrupt line 0 active
1
2
3
4
5
6
7
Real-time clock
Exponent overflow/underflow & BCD faults
Arithmetic overflow & divide faults
Search/Move completion
00
18 17 15 14 12 11
77
4
I
ch
I
x
(Approximate execution time: 1.3-1.7 ,usec.)
ch = I/O channel designator, 0-7
x = interrupt sensing mask code
Instruction Description: Sense for the interrupt conditions listed in Table 7-4. RNI from P
+ 1 if an interrupt line is active and the corresponding mask bit is a "I". If none of the selected lines is active, RNI from P + 2. Internal faults are cleared as soon as they are sensed.
7-61
I NS, Sense Internal
23
00
18 1 7 15 14 12 11
Status
77
3
I
ch
(Approximate execution time: 1.3-1.7 J,Lsec.)
I
x
ch = I/O channel designator, 0-7
x = internal status sensing mask code.
Instruction Description: Table 7-5 lists the bit definitions of the internal status sensing
mask. Bits 00-04 and 06-07 represent conditions within I/O channel ch. Bits 05 and 08-11,
which represent internal faults, may be sensed without regard to channel designation.
To sense a specific condition, load a "I" into the bit position of the mask that corresponds
to the condition. When this instruction is executed, RNI from address P + 1 if an internal
status line is active and the corresponding mask bit is a "1". RNI from address P + 2 if
none of the selected lines is active. Logic associated with the faults marked by an asterisk
in Table 7-5 is cleared as soon as these conditions are sensed.
TABLE 7-5. INTERNAL STATUS SENSING MASK
Mask Bit
Positions
Mask Codes (x)
00
01
02
03
04
05
06
0001
0002
0004
0010
0020
0040
0100
07
0200
08
09
10
11
0400
1000
2000
4000
Condition Represented
Parity error on channel ch
Channel ch busy reading
Channel ch busy writing
External reject active on channel ch
No-response reject active on channel ch
*lIlegal write
Channel ch preset by CON or SEL but no reading
or writing in progress
Internal I/O channel interrupt on channel ch. upon:
1) completion of read or write operation, or
2) end of record
*Exponent overflow/underflow fault (floating point)
* Arithmetic overflow fault (adder)
*Divide fault
*SCD fault
* Refer to INS instruction description.
23
00
19 17 15 14 12 11
77
3
I
ch
I
(Approximate execution time: 1.3-1.7 J,Lsec.)
0000
ch = I/O channel designator, 0-7
Instruction Description: The CINS instruction performs the following functions:
The internal status code is loaded into the lower 12 bits of A. See INS instruction.
2. The contents of the Interrupt Mask register are loaded into the upper 12 bits of A. See
Table 7-4.
3. RNI from address P + 1.
1.
7-62
CONTROL
Operation
Field
77.51
77.6
Address
Field
10Cl
PAUS
Interpretation
Clear liD, typewriter, and SearchlMove
Pause
x
x
23
18 17
77
12 11
00
x
51
(Approximate execution time: 1.3 J.lsec.)
x = block control clearing mask
Instruction Description: This instruction may be used to clear the I/O channels. It also
clears all associated peripheral equipment, the typewriter or the Search/Move control
according to bits set in the block control clearing mask. (Table 7-6).
TABLE 7-6. BLOCK CONTROL CLEARING MASK
Mask Bits
00
01
02
03
04
05
06
07
08
09
10
11
Mask Codes (x)
Controls Cleared
0001
0002
0004
0010
0020
0040
0100
0200
0400
1000
2000
4000
I/O channel 0
1
2
3
4
5
6
7
Typewriter
(see note)
(see note)
Search/Move
NOTE
If bits 09 and 10 are both set or both clear, the channel(s) specified by bits 00 through 07 of the
mask are cleared i.e. Read or Write, Status, and Channel Interrupt are cleared. A 5.5 p..sec.
Clear signal is also sent to the peripheral equipment and controllers connected to the selected
channel( s).
If bit 09 is clear and bit 10 is set, the instruction will clear the channel(s) only and the 5.5
p..sec. Clear signal is not transmitted. Bit 08 clears the typewriter as well as the Type Load or
Type Dump logic in block control.
7-63
23
p
00
18 17 15 14 12 11
77
6.
(Approximate executi.on time:
2.0 f.1sec. to 40 ms.)
x
00
23
P+1
Reject Instruction
x = pause sensing mask code
Instruction Description: This instruction allows the program to halt for a maximum of 40 ms
if a condition (excluding typewriter- see note) defined by the pause sensing mask exists. See
Table 7-7. If a HI" appears on a line that corresponds to a mask bit that is set, the count in P will
not advance. If the advancement of P is delayed for more than 40 ms, a reject instruction is read
from address P+ 1. If none of the lines being sensed is active, or if they become inactive during
the pause, the program immediately skips to address P + 2. If an interrupt occurs and is enabled
during a PAUS, the pause condition is terminated, the interrupt sequence is initiated and the
address of the PAUS instruction is stored as the interrupted address.
Comments: Bits 12 through 14 of the instruction at P should be loaded with zeros.
NOTE
If either bit 08, 09 or 10 (or any combination of these bits) is set and the sensed condition exists,
a pause will not occur and the instruction at P + 1 is read up immediately. If these bites) are set
but the condition(s) does not exist, the program immediately skips to P + 2. For all other bits,
the normal PAUS routine is followed.
TABLE 7-7. PAUSE SENSING MASK
Mask Bits
Mask Codes
00
01
02
03
04
05
06
07
08
09
10
11
0001
0002
0004
0010
0020
0040
0100
0200
0400
1000
2000
4000
Condition
Notes
1/0 channel 0 busy
1
2
3
4
Channel read or write operation in
progress, or the External MC logic
within the channel is set
5
6
7
Typewriter busy
Typewriter NOT finish
Typewriter NOT repeat
SearchlMove control busy
7-64
Typewriter input or output in progress
Finish logic not set
Repeat logic not set
Search or Move operation in progress
INTERRUPT
Operation Field
77.50
77.52
77.53
77.57
77.71
77.72
77.73
77.74
Address Field
INCL
SSIM
SCIM
IAPR
SFPF
SBCD
DINT
EINT
Interpretation
x
x
x
23
18 17
Clear interrupt
Selectively set interrupt mask
Selectively clear interrupt mask
Interrupt associated processor
Set floating point fault
Set BCD fault
Disable interrupt control
Enable interrupt control
12 11
00
(Approximate execution time: 1.3 f,Lsec.)
50
77
x
x = interrupt mask register codes
Instruction Description: This instruction clears the interrupt faults defined by the mask
codes in Table 7-8. Note that only internal I/O channel interrupts are cleared by this
instruction.
TABLE 7-8. INTERRUPT MASK REGISTER BIT ASSIGNMENTS
Mask Bits
00
01
02
03
04
05
06
07
08
09
10
11
*
Mask Codes (x)
Interrupt Conditions Represented
I/O Channel 0 (includes interrupts gener1 ated within the channel
2 and external equipment
3 interrupts)
0001
0002
0004
0010
0020
0040
0100
0200
0400
1000
2000
4000
4
5
6
7
Real-time clock
Exponent overflow/underflow & BCD faults
Arithmetic overflow & divide faults
Search/Move completion
*Mask hits 00-07 represent internal and external I/O interrupts for all instructions except INCL.
7-65
23
Ou
12 11
18 17
(Approximate execution time: 1.3 f.,Lsec.)
77
52
x
x = interrupt mask register codes
Instruction Description: This instruction selectively sets the Interrupt Mask register ac-
cording to the interrupt mask code x. For each bit set to "I" in x, the corresponding bit
position in the Interrupt Mask register is set to "I" (see Table 7-8). Bit positions representing missing or nonavailable I/O channels cannot be set.
23
12 11
18 17
00
(Approximate execution time: 1.3 f.,Lsec.)
77
53
x
x = interrupt mask register codes.
Instruction Description: This instruction selectively clears the Interrupt Mask register according to the interrupt mask code x. For each bit set to "I" in x, the corresponding bit
position in the Interrupt Mask register is set to "0" (see Table 7-8).
23
18 17
77
12 11
00
(Approximate execution time: interrupting
5 7 - ' processor: 1.3 J..Lsec.)
Instruction Description: The processor (computer) executing this instruction sends an interrupt to an associated processor on its left, via storage modules 0 and 1. The interrupt
remains active in the receiving computer until it is recognized.
Comments: Bits 00 through 11 should be loaded with zeros.
7-66
23
18 1 7
77
1 2 11
71
00
~
(Approximate execution time: 1.3 J,Lsec.)
I nstruction Description: The floating-point fault logic sets when a floating point fault occurs.
This instruction is used when the optional floating point arithmetic logic is not present in
a system. An interpretive software routine should recognize any conditions which would
have caused a fault if the operation had been executed by the optional hardware.
Comments: Bits 00 through 11 should be loaded with zeros.
23
18 17
77
1 2 11
72
00
~
(Approximate execution time: 1.3 J,Lsec.)
Instruction Description: The BCD fault logic sets when a BCD fault occurs. This instruction
is used when the optional BCD arithmetic is not present in a system. An interpretive software routine should recognize any condition which would have caused a fault if the operation had been executed by the optional hardware.
Comments: Bits 00 through 11 should be loaded with zeros.
23
18 1 7
77
12 11
73
00
I~I
(Approximate execution time: 1.3 J,Lsec.)
Instruction Description: This instruction disables the interrupt control system. The system
remains disabled until an EINT instruction is executed. Selected interrupts may still be
sensed ..
Comments: Bits 00 through 11 should be loaded with zeros.
23
18 17
77
1 2 11
74
00
~I
(Approximate execution time: 1.3 J,Lsec.)
Instruction Description: This instruction enables the~ interrupt control system. After executing this instruction, one more instruction will be executed before any interrupt can
be recognized.
Comments: Bits 00 through 11 should be loaded w~th zeros.
7-67
INPUT/OUTPUT
Operation Field
77.0
77.1
77.75
77.76
73
74
75
76
CON
SEL
CTI
CTO
INPC.INT.B.H
INAC.INT
INPW.INT.B.N
INAW.INT
OUTC.INT.B.H
OTAC,INT
OUTW,INT,8,N
oTAW, INT
Address
Field
Interpretation
x.ch
x.ch
Connect to external equipment
Select function
Set console typewriter input
Set console typewriter output
Character-Addressed Input to storage
Character-Addressed Input to A
Word-Addressed Input to storage
Word-Addressed Input to A
Character-Addressed Output from storage
Character-Addressed Output from A
Word-Addressed Output from storage
Word-Addressed Output from A
ch.r.s
ch
ch.m.n
ch
ch.r.s
ch
ch,m,n
ch
I/O operations with storage, unlike operations with A, are buffered. Main computer control relinquishes
control of the I/O operations and returns to the main program as soon as Read or Write signals have
been activated.
During the execution of word-addressed I/O instructions, the addresses m and n are shifted left two
places to the upper 15 bits of the 17 -bit address positions. From this time on, they are treated as character addresses.
Registers 00-178 of the Register File are reserved for I/O operations. The lowest order octal digit (X)
of the register designator corresponds to the I/O channel ch being used. Registers 00-078 are used to
hold the instruction word which contains the current character address; 10-178 hold the instruction
word which contains the last character address ±1, depending on the operation. The Register File
controls modify bits 21-23 of the first and second I/O instruction words. The modified values, listed in
Table 7-9, are predictable. Bits 18 through 23 of register file locations 00, 01, 02 and 03 are used by
block control during each I/O transfer-thus, alteration of these bits by a programmer is not recommended. In cases where the addresses require modification to obtain dynamic I/O operations, care
should be taken to provide proper read-out and restoration of the control bits. If the instruction cannot
be executed, program control jumps to the reject instruction.
If the bit reserved for Interrupt Upon Completion (lNT) is a nl" and the mask bit for the affected I/O
channel is a ((I" and the interrupt system is enabled, the control logic receives a channel-generated
interrupt when the output operation is completed. I/O efficiency can be increased by utilizing this bit
when applicable.
7-68
TABLE 7-9, MODIFIED 1/0 INSTRUCTION WORDS
Instruction
73
....
INPC
~
'i
c::::
Q)
C)
74
INPW
0
75
OUTe
0
76
«
73
OUTW
INAC
74
INAW
75
OTAC
Q)
76
OTAW
Q.
0
1
2
,S!
to...
1
2
CI)
c::::
1
2
~
....
1
2
Q)
'i
1
2
co
~tn
Q.
1
2
.
,2
.... ....
CI)
Instruction
Word
1
2
1
2
Relative
Location
P
P+ 1
P
P+ 1
p
- - -
-
- - -
-
7 - - - - - - 7 - - - - - - 4 - - - - - - 4 - - - - - - 5 - - - - - - 5 - - - - - - 6 - - - - - - 6 - - - - - - -
1X
OX
1X
OX
1X
OX
1X
OX
a
a
-
-
- - - -
- - - - - - - - - - -
P+ 1
P
P+ 1
P
P +
P
P+
P
P+
P
p+
'X represents an I/O channel designator ch, 0 through 7.
7-69
1
1
1
-
1X
OX
1X
OX
1X
OX
1X
OX
3
3
- - 1 - - 1 - - 2 - - 2 - - -
1
Register*
Designator
Modified
Code
- - - - - - -
-
-
-
-
23
P
00
18 17 15 14 12 11
77
o
ch
(Approximate execution
time: indeterminate)
x
00
23
P+1
Reject Instruction
ch = 1/0 channel designator, 0-7
x = 12 bit connect code. Bits 09-11
select one of eight controllers which
may be attached to channel ch. Bits
00-08 select the peripheral units
connected to the controller.
Instruction Description: This instruction sends a 12-bit connect code along with a connect
enable to an external equipment controller on I/O channel ch. If a Reply is received from
the controller within 100 ,usec, the next instruction is read from address P + 2. If a Reject
is received or there is no response within 100,usec, a reject instruction is read from address
P + 1. If the I/O channel is busy, a reject instruction is read from address P + 1.
23
P
77
ch
(Approximate execution
time: indeterminate)
x
00
23
P+1
00
18 17 15 14 12 11
Reject Instruction
ch = 1/0 channel designator, 0-7
x = 12-bit function code. Each piece of
external equipment has a unique
set of function codes to specify operations within that device. Refer
to the 3000 Series Computer Systems Peripheral Equipment Codes
publication No. 60113400 for a
complete list of function codes.
Instruction Description: This instruction sends a 12-bit function code along with a function enable to the unit connected to I/O channel ch. If a Reply is received from the unit
within 100 ,usec, the next instruction is read from P + 2. If a Reject is received or there is
no response within 100 J.Lsec, a reject instruction is read from address P + 1. If the 110 channel is busy, a reject instruction is read from address P + 1.
The following conditions or combination of conditions will result in a Reject:
1) No Unit or Equipment Connected: The referenced device is not connected to the system
and cannot recognize a Function instruction. If no response is received within 100 ,usec,
the Reject signal is generated automatically by the I/O channel.
2) Undefined Code: When the Function code x is not defined for the specific device, a Reject
may be generated by the device. However, in some cases an undefined code will cause the
device to generate a Reply although no operation is performed. (Refer to the reference
manual for the specific device.)
3) Equipment or Unit Busy or Not Ready: The device cannot perform the operation specified
by the function code x without damaging the equipment or losing data. For example, a
Write End of File code is rejected by a tape unit if the tape unit is rewinding.
4) Channel Busy: The selected data channel is currently performing a Read or Write
operation.
7-70
23
18 17
77
12 11
75
00
FlIed'
(Approximate execution time: 1.3 JLsec.)
I nstruction Description: This instruction, like the TYPE LOAD switch, permits a block of data
to be entered into storage as soon as the Type Load indicator lights. If a block of data smaller
than the one defined by registers 23 and 33 is to be typed, the FINISH switch should be depressed
when the typing is completed. If more data is entered than the defined block can hold, the excess
data is lost. If a typing error occurs, the REPEAT button should be depressed. When either the
FINISH or REPEAT switches are depressed, the typewriter input operation is terminated and
the appropriate status bits (09 and 10) may be sensed with the PAUS instruction. Refer to page
7-64 for additional information on the PAUS instruction.
Comments: Bits 00 through 11 should be loaded with zeros.'
23
18 17
77
12 11
76
00
~.,
(Approximate execution time: 1.3 JLsec.)
Instruction Description: This instruction, like the TYPE DUMP switch, causes the typewriter
to print out the block of data defined by the character addresses in registers 23 and 33.
Comments: Bits 00 through 11 should be loaded with zeros.
NOTE
The CTI and CTO instructions are mutually exclusive. Any attempt to execute one
while the other is being executed will be ignored by the computer. Typewriter busy
should be checked before these instructions are used and before registers 23 and 33
are altered.
7-71
18 17 16
23
00
10 I
73
s
23 21 20 19 18 17 16
00
23
00
(Approximate execution time:
3.3,usec.)
Reject Instruction
B
ch
H
H
INT
=
=
=
=
=
=
s
=
"1" for backward storage
110 channel designator. 0-7
"0" for 6- to 24-bit assembly
"1" for 12- to 24-bit assembly
"1" for interrupt upon completion
first character address of 1/0 data block;
becomes current address as 1/0 operation progresses
last character address of input data
block. plus one (minus one. for backward storage)
Instruction Description: This instruction transfers a character-address block of data, con-
sisting of 6-bit characters or 12-bit bytes, from an external equipment to storage. During
12- to 24-bit assembly, the lowest bit of each character address is forced to remain a "0"
in register OX. This ensures that assembled bytes are in either the upper or the lower
half of the word being stored.
INSTRUCTION SEQUENCE
REQUEST
BLOCK
CONTROL
(P)~F
START
(FCN REG)
/
f
READ
(P
+
1)
CHANNEL
BUSY?
LOAD
+ 1)~ZO
(P
(P)~Zl
YES
REJECT
TO
WAIT FOR BLOCK CONTROL.
THEN S BUS PRIORITY.
P+2
&
STORE Zo (P+ 1)
ACTIVATE READI
WRITE ON 1/0
CHANNEL O~ 7
OPERATION
WITH A?
IN ONE REGISTER
STORE Z1 (P)
.. IN ONE REGISTER
(OO~ 07)
NO
I---~
(10~
RNI
FROM
P+3
7-72
17)
RELEASE BLOCK
CONTROL AND
SCANNER
kD
Await
Reply
Reply
From
Controller
I/O Channel
Generates
Data Signal
I/O Channel
Generates
Block Control
Request
Await
Priori tY;r-----....,
Read Up
Register
Transfer
r to S2
OX
A or NC = 1
Restore
Register
OX
Request
Core
Storage
Await
Priority Deliver
(S2) to
S Bus
Input One
Or Two
Characters
To r
Set External
To Internal BCD
Conversion
Read Up
Register
lX
x = I/O Channel Ch
(0-7)
H
=0
Increment
r by 1
'------~
Terminate
Input
B=O
H = 1
INT = 1
H
Interrupt
=0
Decrement
r by 1
Decrement
r by 2
Figure 7 -8. 1/0 Operation with Storage
IN'W :~()r~;;'A,~~r!~j~'
l"p~,~,t',S~oras,.,,{' :: ;/,'"
23
18 17 16
00
74
(Approximate execution time:
3.3 p,sec.)
n
23 21 20 19 18 17 16
00
m
23
00
Reject Instruction
B = "1" for backward storage
ch = 110 channel designator. 0-7
INT = "1" for interrupt upon completion
N = "0" for 12- to 24-bit assembly
N = "1" for no assembly
m = first word address of I/O data block;
becomes current address as I/O operation progresses
n
= last word address of input data block.
plus one (minus one. for backward
storage)
Instruction Description: This instruction transfers a word-addressed data block from an external equipment to storage. Transferring 12-bit bytes or 24-bit words depends upon the type of
I/O channel used. The 3206 utilizes 12-bit bytes and the 3207 uses 24-bit words.
During forward storage and 12- to 24-bit assembly, the first byte of a block of data is stored
in the upper half of the memory location specified by the storage address. Conversely, during
backward storage, the first byte is stored in the lower half of the memory location.
I/O OPERATION WITH STORAGE
INSTRUCTION SEQUENCE
REQUEST
BLOCK
CONTROL
(P)~F
START
(FCN REG)
/
f
READ
CHANNEL
+
BUSY?
(P
1)
LOAD
+ 1)~ZO
(P
(P)~Zl
YES
REJECT
TO
WAIT FOR BLOCK CONTROL.
THEN S BUS PRIORITY.
P+2
STORE Zo (P+ 1)
IN ONE REGISTER
(00 ~ 07)
ACTIVATE READI
-+ WRITE ON I/O
CHANNEL
o~
7
OPERATION
WITH A?
NO
)---"",*
STORE Zl (P)
,. IN ONE REGISTER
(10~ 17)
RNI
FROM
P+3
7-74
RELEASE BLOCK
CONTROL AND
SCANNER
40
Await
I/O Charmel
Generates
Data Signal
Reply
Await
Reply From
Controller
Vo Channel
Generates
Block Control
Request
Priority Re ad Up
Register
OX
A or NC
Await
Restore
Register
OX
Request
Core
Storage
Priority Deliver
(S2) To
S Bus
Transfer
m to S2
Input One
Word Tom
Read Up
Register
IX
=1
Set External
To Internal
BCD Conversion
N = 0
....
__
r-..
.....
Increment
m by2
B=O
x
Terminate
Input
N = 1
= I/O Channel Ch (0-7)
Increment
m by4
INT
=1
N
Interrupt
=0
Decrement
,..---. .............. 01
by 2
Decrement
m by4
Figure 7 -9. 74 I/O Operation with Storage
~..-~
OUTC Character~Addressed
Output from Storage
23
18 17 16
00
s
75
23 21 20 19 18 17 16
00
23
00
(Approximate execution time:
3.3 J.Lsec.)
Reject Instruction
B
= "1" for backward storage
ch = I/O channel designator, O~ 7
H = "0" for 24- to 6-bit disassembly
H = "1" for 24- to 12-bit disassembly
INT =" 1" for interrupt upon completion
= first character address of I/O data block;
becomes current address as I/O operation progresses
s
= last character address of output data
block, plus one (minus one, for backward output)
Instruction Description: This instruction transfers a character~addressed block of data,
consisting of 6~bit characters or 12~bit bytes, from storage to an external equipment.
1/0 OPERATION WITH STORAGE
INSTRUCTION SEQUENCE
REQUEST
(P)~F
START
BLOCK
(FCN REG)
CONTROL
/
f
READ
CHANNEL
+
BUSY?
(P
1)
LOAD
+ 1)~ZO
(P
(P)~Zl
YES
REJECT
WAIT FOR BLOCK CONTROL.
THEN S BUS PRIORITY.
TO
P+2
-+
STORE Zo (P+ 1)
ACTIVATE READ/
WRITE ON 110
CHANNEL O~ 7
OPERATION
WITH A?
STORE Zl (P)
, IN ONE REGISTER
(OO~ 07)
NO
IN ONE REGISTER
(10 ~ 17)
iL..__
R...;.N_I_---'~3
FROM
P+3
~
7~76
RELEASE BLOCK
:: CONTROL AND
SCANNER
~
Await
Priority,..-----Re ad Up t--e--'!M Transfer I--"'--{
Register
r to S2
I/O Channel
Generates
Blo ck Control
Request
H = 0 r-------.
Increment
)-.........-{
r by 1
OX
B =0
A or NC
=1
H= 1 , . . - - - - - - - ,
Increment
Restore
r by 2
I--~~ Re gis ter
Set Internal
To External BCD
Conversion
H
OX
=0
Decrement
r by 1
x = I/O
Channel Ch (0-7)
Decrement
r by 2
Await
Reply
r-----.... Await
Request
Core
Storage
Priority Deliver
S2 To
S Bus
Output One
Or Two
Characters
From r
INT
No
Read Up
Register
lX
llies
r
= s?
Reply
From
Controller
I/O Channel
Generates
Data Signal
Yes
Set Channel
Terminate
Terminate
Output
Figure 7 -10. 75 I/O Operation with Storage
=1
Interrupt
18 17 16
23
J)UTW Word-Addressed
iii'Q\ltput from Storage
00
76
(Approximate execution time:
3.3 J.Lsec)
n
:~
< rf :
rf : use Radix Arithmetic, Substitution
use Power Addition, Substitution
rj = Radix of initial system
rf = Radix of final system
B-5
POWER ADDITION
To convert a number from ri to rf (ri < rf) write the number in its expanded ri polynomial
form and simplify using rc arithmetic.
EXAMPLE 1
Binary to Decimal (Integer)
010 1112=1 (24) +0(2 3 )+1(2 2 )+1(2 1 )+1(2 0 )
= 1 (16) +0(8) + 1 (4) + 1 (2) + 1 (1)
=16
+0
+4
+2
+1
=2310
EXAMPLE 2
Binary to Decimal (Fractional)
.01012 =(2 .1)+1(2.2 ) +0(2 .3) +1(2 .4)
=0
+1/4
= 511610
+0
+1/16
EXAMPLE 3
Octal to Decimal (Integer)
3248=3(8 2 ) +2(8 1) +4(8 0 )
:;::3(64)+2(8) +4(1)
=192 +16 +4
=21210
EXAMPLE 4
Octal to Decimal (Fractional)
.448 =4(8. 1 )+4(8. 2 )
=4/8
+4/64
=36/6410
RADIX ARITHMETIC
To convert a whole number from ri to rc (ri > rc):
1.
Divide ri by rc using ri arithmetic
2. The remainder is the lowest order bit in the new expression
3. Divide the integral part from the previous operation by rc
4.
5.
The remainder is the next higher order bit in the new expression
The process continues until the division produces only a remainder which will
be the highest order bit in the rf expression.
To convert a fractional number from ri to rf:
1.
Multiply ri by rf using ri arithmetic
2. The integral part is the highest order bit in the new expression
Multiply the fractional part from the previous operation by rc
4. The integral part is the next lower order bit in the new expression
5. The process continues until sufficient precision is achieved or the process
terminates.
3.
B-6
Decimal to Binary (Integer)
EXAMPLE 1
45
22
11
5
2
22
11
5
2
1
0
2
2
2
2
2
2
Thus: 4510 =
1;
0;
1;
1;
0;
1;
record
record
record
record
record
record
1011012
1
0
1
0
1
101101
Decimal to Binary (Fractional)
EXAMPLE.2
.25 x 2
.5 x 2
.0 x 2
remainder
remainder
remainder
remainder
remainder
remainder
0.5; record
1.0; record
0.0; record
Thus: .2510
=
.0102
o
1
O·
.010
Decimal to Octal (Integer)
EXAMPLE 3
273 -+- 8
34 -+- 8
4 -;- 8
34 remainder 1; record
4 remainder 2; record
o remainder 4; record
Thus: 27310
=
1
2
~
421
EXAMPLE 4
4218
Decimal to Octal (Fractional)
.55 x 8 = 4.4; record
.4 x 8 = 3.2; record
.2 x 8 = 1.6; record
4
3
.431 '"
Thus: .5510
.431 ... 8
SUBSTITUTION
This method permits easy conversion between octal and binary representations of a
number. If a number in binary notation is partitioned into triplets to the right and left
of the binary point, each triplet may be converted into an octal digit. Similarly, each
octal digit may be converted into a triplet of binary digits.
EXAMPLE 1
Binary to Octal
Binary = 110 000
Octal =
6 0
EXAMPLE2
Octal
Binary
001 010
1
2
Octal to Binary
= 6
5
a
= 110 101 000
B-7
227
010 010 111
SUPPLEMENTARY INSTRUCTION INFORMATION
FIXED POINT ARITHMETIC
24- B it Precision
Any number may be expressed in the form kB n , where k is a coefficient, B a base number, and the exponent n the power to which .the base number is raised.
A fixed point number assumes:
1. The exponent n = 0 for all fixed point numbers.
2. The coefficient, k, occupies the same bit positions within the computer word
for all fixed point numbers.
3. The radix (binary) point remains fixed with respect to one end of the expression.
A fixed point number consists of a sign bit and coefficient as shown below. The upper
bit of any fixed point number designates the sign of the coefficient (23 lower order bits).
If the bit is "1", the quantity is negative since negative numbers are represented in
one's complement notation; a "0" sign bit signifies a positive coefficient.
23
SIGN
BIT
00
22
COEFFICIENT
The radix (binary) point is assumed to be immediately to the right of the lowest order
bit (00).
In many instances, the values in a fixed point operation may be too large or too small
to be expressed by the computer. The programmer must position the numbers within
the word format so they can be represented with sufficient precision. The process, called
scaling, consists of shifting the values a predetermined number of places. The numbers
must be positioned far enough to the right in the register to prevent overflow but far
enough to the left to maintain precision. The scale factor (number of places shifted) is
expressed as the power of the base. For example, 5,100,00010 may be expressed as 0.51 x
107 , 0.051 X 108 , 0.0051 X 109 , etc. The scale factors are 7, 8, and 9.
Since only the coefficient is used by the computer, the programmer is responsible for
remembering the scale factors .. Also, the possibility of an overflow during intermediate
operations must be considered. For example, if two fractions in fixed point format are
multiplied, the result is a number < 1. If the same two fractions are added, subtracted,
or divided, the result may be greater than one and an overflow will occur. Similarly, if
two integers are multiplied, divided, subtracted or added, the likelihood of an overflow
is apparent.
48-Bit Precision (Double Precision)
The 48-bit Add, Subtract, Multiply and Divide instructions enable operands to be
processed. The Multiply and Divide instructions utilize the E register and therefore are
executed as trapped instructions if the applicable arithmetic option is not present in a
system. Figure 7-4 in the Instruction Section illustrates the operand formats in 48-bit
precision Multiply and Divide instructions.
B-8
FLOATING POINT ARITHMETIC
As an alternative to fixed point operation, a method involving a variable radix point,
called floating point, is used. This significantly reduces the am:ount of bookkeeping required on the part of the programmer.
By shifting the radix point and increasing or decreasing the value of the exponent, widely
varying quantities which do not exceed the capacity of the machine may be handled.
Floating point numbers within the computer are represented in a form similar to that
used in scientific notation, that is, a coefficient or fraction multiplied by a number raised
to a power. Since the computer uses only binary numbers, the numbers are multiplied
by ·powers of two.
F • 2E
where:
F = fraction
E=exponent
In floating point, different coefficients need not relate to the same power of the base as
they do in fixed point format. Therefore, the construction of a floating point number
includes not only the coefficient but also the exponent.
NOTE
Refer to Figure 7-5 in the Instruction Section for the operand format and bit functions for specific floating point instructions.
Coefficient
The coefficient consists of a 36-bit fraction in the 36 lower order positions of the floating
point word. The coefficient is a normalized fraction; it is equal to or greater than ~ but
less than 1. The highest order bit position (47) is occupied by the sign bit of the coefficient. If the sign bit is a "0", the coefficient is positive; a "I" bit denotes a negative
fraction (negative fractions are represented in one's complement notation).
Exponent
The floating point exponent is expressed as an II-bit quantity with a value ranging from
0000 to 37778. It is formed by adding a true positive exponent and a bias of 20008 or a true
negative exponent and a bias of 17778. This results in a range of biased exponents as
shown below.
True Positive
Exponent
Biased
Exponent
True Negative
Exponent
+0
+1
+2
2000.
2001
2002
-0
-1
-2
---
- - -- - --
--
+1776
+17778
3776
37779
-1776
-17779
46
--
Biased
Exponent
2000*
1776
1775
----------0001
OOOOs
00
36 35
COEFFICIENT
EXPONENT (INCLUDING BIAS)
The exponent is biased so that floating point operands can be compared with each other
in the normal fixed point mode.
*Minus zero is sensed as positive zero by the computer and is therefore biased by 20008 rather than 17778.
B-9
As an example, compare the unbiased exponents of +528 and +0.028 (Example 1).
EXAMPLE 1
Number =
a
a a
Coefficient
Sign
000
+52
000
11 0
Exponent
Number =
o
111
Coefficient
Sign
(36 bits)
Coefficient
+0.02
111
011
(36 bits)
Coefficient
Exponent
In this case +0.02 appears to be larger than +52 because of the larger exponent. If,
however, both exponents are biased (Example 2), changing the sign of both exponents
makes +52 greater than +0.02.
EXAMPLE 2
Number =
o
o
Coefficient
Sign
000
Coefficient
Sign
000
110
Exponent
Number
o
+528
o
=
111
(36 bits)
Coefficient
+0.028
111
Exponent
011
(36 bits)
Coefficient
When bias is used with the exponent, floating point operation is more versatile since
floating point operands can be compared with each other in the normal fixed point mode.
All floating point operations involve the A, Q, and E registers, plus two consecutive
storage locations M and M + 1. The A and Q registers are treated as one 48-bit register.
Indirect addressing and address modification are applicable to this whole group of instructions.
Operand Formats
The AQ register and the storage address contents have identical formats.
In both cases the maximum possible shift is 64 (778) bit positions. Since the coefficient
consists of only 36 bits at the start, any shift greater than 36 positions will, of course,
always result in an answer equal to the larger of the two original operands.
B-IO
(47)
23
(46)
22
(36)
12
(35)
11
(24)
00
(A) and (M)
Coefficient
exponent including
bias
23
(0) and (M
+
1)
00
\
\~----------------------~
Lower 24 bits of'{perand coefficient
Exponents
The 3100, 3200, 3300 Computers use an II-bit exponent that is biased by 20008 for floating point operations. The effective modulus of the exponent is ± 17778 or ± 102310.
Exponent Equalization
During floating point addition and subtraction, the exponents involved are equalized
prior to the eperation.
1. Addition - The coefficient of the algebraically smaller exponent is automatically shifted right in AQE until the exponents are equal. A maximum of 778
shifts may occur.
2. Subtraction - If AQ contains the algebraically smaller exponent, the coefficient
in AQ is shifted right in AQE until the exponents are equal. If (M) and (M + 1)
have the smaller exponent, the complement of the coefficient of (M) and (M + 1)
is shifted right in AQE until the exponents are equal or until a maximum of
778 shifts are performed.
Rounding
Rounding is an automatic floating point operation and is particularly necessary when
floating point arithmetic operations yield coefficient answers in excess of 36 bits.
Although standard floating point format requires only a 36-bit coefficient, portions of
the E register are used for extended coefficients. Refer to individual instruction descriptions for E register applications.
Rounding modifies the coefficient result of a floating point operation by adding or subtracting a "I" from the lowest bit position in Q without regard to the biased exponent.
The coefficient of the answer in AQ passes through the adder with the rounding quantity
before normalization. The conditions for rounding are classified according to arithmetic
operation in Table B-2.
B-ll
I
~----------------------~}
TABLE B-2. ROUNDED CONDITIONS FOLLOWING ARITHMETIC OPERATION
!
Arithmetic
OPERATION
ADD
or
SUBTRACT
Bit 23 of the
A Register
Bit 47 of the E Register
or
(Ratio of Residue/Divisor
for Divide Only)
Applicable
Rounding
a*
a*
a
No
1
Add "1"
1·
a
Subtract" 1 "
1*
1
No
Comments: Rounding occurs as a result of inequality between the sign bits
of AQand E.
MULTIPLY
a
a
a
1
Add "1"
1
a
Subtract" 1 ,.
1
1
No
No
Comments: A floating point multiplication yields a 76 bit coefficient. Comparison between the sign bits of AQ and E indicates that the lower 36
bits are equal to or greater than 112 of the lowest order bit in AQ.
I
DIVIDE
a
a
;;:::: 112 (absolute)
Add "1"
.:::; 112 (absolute)
No
1
;;:::: 112 (absolute)
Subtract" 1 ..
1
.:::; 112 (absolute)
No
Comments: Rounding occurs if the answer resulting from the final residue
division is equal to or greater than 112
i
*Condition of bit 23 of the A register immediately after equalization. (Refer to Exponent Equalization on preceeding
page).
Normalizing
Normalizing brings the above answer back to a fraction with a value between one-half
and one with the binary point to the left of the 36th bit of the coefficient. In other words,
the final normalized coefficient in AQ will range in value from 236 to 237.1 including sign.
Arithmetic control normalizes the answer by right or left shifting the coefficient the
necessary number of places and adjusting the exponent. It does not shift the residue
that is in E.
Faults
Three conditions are considered faults during the execution of floating point instructions:
1. Exponent overflow (> + 17778)
2. Exponent underflow « - 17778)
3. Division by zero, by too small a number, or by a number that is not in floating
point format.
These faults have several things in common:
1; They can be sensed by the IN S (77.3) instruction
2. Sensing automatically clears them
3. The program should sense for these faults only after the floating point instructions have had sufficient time to go to completion
4. They may be used to cause an interrupt.
B-12
FIXED POINT/FLOATING POINT CONVERSIONS
Fixed Point to Floating Point
1. Express the number in binary.
2. Normalize the number. A normalized number has the most significant 1 posi-
tioned immediately to the right of the binary point and is expressed in the
range liz ::; k < 1.
3. Inspect the sign of the true exponent. If the sign is positive add 20008 (bias)
to the true exponent of the normalized number. If the sign is negative, add the
bias 17778 to the true exponent of the normalized number. In either case, the
resulting exponent is the biased exponent.
4. Assemble the number in floating point.
5. Inspect the sign of the coefficient. If negative, complement the assembled
floating point number to obtain the true floating point representation of the
number. If the sign of the coefficient is positive, the assembled floating point
number is the true representation.
EXAMPLE 1
Convert
+4.0 to floating point
1. The number is expressed in octal.
2. Normalize. 4.0 = 4.0 x 8 0 = 0.100 x 2 3
3. Since the sign of the true exponent is positive,'
add 20008 (bias) to the true exponent. Biased
exponent = 2000
3.
+
4. Assemble number in floating point format.
Coefficient = 400 000 000 0008
Biased Exponent = 20038
Assembled word = 2003 400 000 000 0008
5. Since the sign of the coefficient is positive, the
floating point representation of. +4.0 is as
shown. If, however, the sign of the coefficient
were negative, it would be necessary to complement the entire floating point word.
EXAMPLE 2
Convert -4.0 to floating point
1. The number is expressed in octal.
2. Normalize. -4.0 = -4.0 x 8 0 = -0.100 x 2 3
3. Since the sign of the true exponent is positive,
add 20008 (bias) to the true exponent. Biased
exponent = 2000
3
+
4. Assemble number in floating point format.
Coefficient = 400000000 OOOa
Biased Exponent = 20038
Assembled word = 2003400000000 OOOa
5. Since the sign of the coefficient is negative,
the assembled floating point word must be
complemented. Therefore, the true floating
point representation for
-4.0
=
57743777777777778.
B-13
EXAMPLE 3
Convert 0.510 to floating point
== 0.48
0.4 x 8 0 = 0.100 x 2 0
1. Convert to octal. 0.510
2.
No~malize.
0.4
=
3. Since the sign of the true exponent is positive,
add 20008 (bias) to the true exponent. Biased
exponent = 2000
O.
+
4. Assemble number in floating point format.
Coefficient = 400000 000 0008
Biased Exponent = 20008
Assembled word = 20004000000000008
5. Since the sign of the coefficient is positive, the
floating point representation of +0.510 is as
shown. If, however, the sign of the coefficient
were negative, it would be necessary to complement the entire floating point word: This
example is a special case of floating point
since the exponent of the normalized number
is and could be represented as -0. The exponent would then be biased by 17778 instead
of 2000s because of the negative exponent.
The 3100 and 3200, however, recognize -0
as
0 and bias the exponent by 20008.
a
+
EXAMPLE 4
Convert 0.048 to floating point
1. The number is expressed in octal.
2. Normalize. 0.04
0.100 x 2'3
=
0.04 x 8 0
=
0.4
X
8,1
3. Since the sign of the true exponent is negative, add 17778 (bias) to the true exponent.
(-3) = 17748
Biased exponent = 1777s
+
4. Assemble number in floating point format.
Coefficient = 400 000 000 OOOs
Biased Exponent = 17748
Assembled word = 1774400 000 000 0008
5. Since the sign of the coefficient is positive, the
floating point representation Of 0.048 is as
shown. If, however, the sign of the coefficient
were negative, it would be necessary to complement the entire floating point word.
B-14
Floating Point to Fixed Point Format
1. If the floating point number is negative, complement the entire floating point
2.
3.
4.
5.
word and record the fact that the quantity is negative. The exponent is now
in a true biased form.
If the biased exponent is equal to or greater than 20008, subtract 20008 to obtain-the true exponent; if less than 20008, subtract 17778 to obtain true exponent.
Separate the coefficient and exponent. If the true exponent is negative, the
binary point should be moved to the left the number of bit positions indicated
by the true exponent. If the true exponent is positive, the binary point should
be moved to the right the number of bit positions indicated by the true exponent.
The coefficient has now been converted to fixed binary. The sign of the coefficient will be negative if the floating point number was complemented in step
one. (The sign bit must be extended if the quantity is placed in a register.)
Represent the fixed binary number in fixed octal notation.
Convert floating point number
2003400000000 OOOs to
fixed octal
EXAMPLE 1
1. The floating point number is positive and remains uncomplemented.
2. The biased exponent> 20008: therefore. subtract 20008 from the biased exponent to obtain the true exponent of the number. 2003 -
2000
=
+3
3. Coefficient = 400 000 000 0008 = .1002.
Move binary point to the right three places.
Coefficient = 100.02.
4. The sign of the coefficient is positive because
the floating point number was not complemented in step one.
5. Represent in fixed octal notation.
100.0 x 2°
EXAMPLE 2
=
4.0 x 8°.
Convert floating point number
57743777777777778 to fixed octal
1. The sign of the coefficient is negative; therefore. complement the floating point number.
Complement = 2003 400 000 000 0008
2. The biased exponent (in complemented form)
20008: therefore. subtract 20008 from the
biased exponent to obtain the true exponent
of the number. 2003 - 2000 = +3
>
3. Coefficient = 4000000 000 0008 = 0.1002.
Move binary point to the right three places.
Coefficient = 1 00.02
4. The sign of the coefficient will be negative
because the floating point number was originally complemented.
5. Convert to fixed octal. -100.02
B-15
=
-4.08
Convert floating point number
EXAMPLE 3
1774400 000 000 OOOs
to fixed octal
1. The floating point number is positive and
remains uncomplemented.
2. The biased exponent < 2000s; therefore. subtract 1777s from the biased exponent to obtain the true exponent of the number. 1774s-
1777s =-3
3. Coefficient = 400 000 000 OOOs = .1002.
Move binary point to the left three places.
Coefficient = .000 1002
4. The sign of the coefficient is positive because
the floating point number was not complemented in step one.
5. Represent in fixed octal notation .
.0001002 = .04s
BINARY CODED DECIMAL (BCD) ARITHMETIC
General
The Binary Coded Decimal (BCD) option expands the arithmetic capabilities of a 3100, 3200,
or 3300 Computer by providing the necessary logic for loading, storing, shifting, adding and
subtracting binary coded decimal characters. A standard 24-bit data word is comprised of
four 6-bit BCD characters. The general format for a BCD word and the bit function within a
typical character are illustrated in Figure B-l. Tables B-3 and B-4 define the significance of
binary data within a character.
Figure B-2 depicts the En register and the other digits displayed on the 3200 Console.
23
18 17
o
12 11
I
06 05
2
I
00
3
~~Character
" positions
.1 ~~
BCD Character
Figure B-1. BCD Word and Character Format
B-16
I
TABLE B-3. BCD SIGN BIT POSITIONS
Sign of BCD
Character*
Relative Bit Positions
+
+
-
+
6
5
0
0
1
1
0
1
0
1
TABLE B-4. DECIMAL/BCD CHARACTER FORMAT
Decimal
Number**
0
1
2
3
4
5
6
7
8
9
BCD Character Relative Bit
Positions
1
4
3
2
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
\. . -. '--,.__
5 ',--'.,-4--,-1_'-:-3---,-_'-:-2--,;-1_,_,--"-_,O_'--9_.L....-8---"~ E D ~1'-_7_-'---_6----'-_5-----'_4_-'---3_~_2_'-------'__O---J.)
I
I,-_t_tL...-~
_____-_-~_-_ Overflow
BCD character
digit
1.....
______________
I
digits
Sign of ED register
I . . . . . - - - - - - - - - - - - - - - - - - M S D of second operand
1.....-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Sign of second operand
Figure B-2. ED Register and Supplemental Digits
*The Lowest Significant Digit of a given BCD field contains the sign of the operand in relative bit positions
5 and 6. A fault is indicated ifrelative bits 5 and 6 in the remaining characters contain anything other than
zeroes; however, the current instruction will continue to be executed.
** A fault is also indicated if an illegal character is sensed in bits 1 through 4 (1010, 1011, 1100, 1101, 1110 or 1111).
B-17
Formats: These instructions handle 4-bit BCD characters rather than whole 24-bit
words. These characters are placed into the ED register and storage in,the following ways:
1) ED Register
52
51
-11
/'
-4
/'
Sign
of E
00
'-_ _ _ _ _ ____. ____- - - - - - - - /
y
Overflow
character
position
BCD Characters
The 53-bit ED register can hold 12 regular BCD characters plus one
overflow character.
2) Storage
23
(M)
=
18 17
a
12 11
I
06 05
2
00
3
Each 24-bit storage word may be divided into four character positions of 6 bits each.
The lower 4 bits of each position may hold any BCD character, 0-9; the upper 2 bits
are reserved for the sign designator, one per field. For each field the sign accompanies
the least significant character. 10xxxx specifies negative; any other combination, positive (refer to Table B-3). The upper 2 bits' of all other characters in the field must equal
zero. The most significant character precedes the least significant character of a field
in storage.
Field Length: The field length is specified by the contents of the 4-bit D register. Any
number 1-12 (0001-1100) is legal. *
Illegal Characters: By definition, any BCD characters other than 0-9 are illegal. Characters are tested for legality during:
1. Loading into E (LDE), and
2. Addition (ADE) and subtraction (SBE). If the translation of the lower four
bits of a character exceeds 9, the value zero will be used for that character.
BCD Fault: The BCD fault will occur if:
1. A sign is present in any character position other than the least significant, or
2. An illegal character other than the lowest MB is sensed during the execution
of LDE, ADE, SBE
3. The contents of D exceed 12 (will set only during a SET instruction).
*Although a fault will occur, D may equal 13 for storing 13 characters. The following sequence should be followed in storing 13 characters:
1) Set D (BCD fault will occur)
2) Sense for BCD fault (this clears the BCD Fault indicator)
. 3) Execute STE instruction.
If the BCD fault is disregarded and there is an attempt to load, add, or subtract 13 characters, only the lower
12 characters will be used. No additional fault will occur.
B-18
BCD Instruction Example
70 7 00011
64 0 00005
EXECUTED INSTRUCTIONS:
ADDRESSES:
CONTENTS OF ADDRESS
MSC
00001
05
(Q])
00002
~
~
@
@
&-
@~.J___
-118=910
-108=810
~2
00003
4
5
LSC
10 0 101
'-v-' '---v--/
5
NOTE
Only the LSC is analyzed for the sign of the
field. A BCD fault occurs if anything other
than zeros are in the upper two bits of the
remaining characters.
ANALYSIS:
70 7 00011
instruction sets the field length register (D) with 118
64 0 00005
instruction specifies an LDE with successive BCD characters starting with
the least significant character (LSC) at address R (0-1) of 00005 = address 0001, character position 1. 118 characters are loaded into ED. The
final contents of ED are shown below.
+
ED
=
-0000849109825
!
character cannot
(A BCD
be loaded
into the 13th digit. A zero will always
be entered here during a 64 instruction.)
B-19
Appendix C
Programming Reference Tables
and
Conversion Information
TABLE OF POWERS OF TWO
1
2
4
8
0
1
2
3
1.0
0.5
0.25
0.125
16
32
64
128
4
5
6
7
0.062
0.031
0.Q15
0.007
5
25
625
812 5
256
512
1 024
2 048
8
9
10
11
0.003
0.001
0.000
0.000
906
953
976
488
25
125
582 5
281 25
4
8
16
32
096
192
384
768
12
13
14
15
0.000
0.000
0.000
0.000
244
122
061
030
140
070
035
517
625
312 5
156 25
578 125
65
131
262
524
536
072
144
288
16
17
18
19
0.000
0.000
0.000
0.000
015
007
003
001
258
629
814
907
789
394
697
348
062
531
265
632
5
25
625
812 5
048 576
2 097 152
4 194 304
8 388 608
20
21
22
23
0.000 000 953 674
0.000 000 476 837
QOOO 000 238 418
o.oOd 000 119 209
316
158
579
289
406
203
101
550
25
125
562 5
781 25
16
33
67
134
777
554
108
217
216
432
864
728
24
25
26
27
0.000
0.000
QOOO
0.000
000
000
000
000
059
029
014
007
604
802
901
450
644
322
161
580
775
387
193
596
390
695
847
923
625
312 5
656 25
828 125
268
536
1 073
2 147
435
870
741
483
456
912
824
648
28
29
30
31
0.000
0.000
0.000
0.000
000
000
000
000
003
001
000
000
725
862
931
465
290
645
322
661
298
149
574
287
461
230
615
307
914
957
478
739
062
031
515
257
5
25
625
812 5
4
8
17
34
294
589
179
359
967
934
869
738
296
592
184
368
32
33
34
35
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
232
116
058
029
830
415
207
103
643
321
660
830
653
826
913
456
869
934
467
733
628
814
407
703
906
453'
226
613
25
125
562 5
281 25
68
137
274
549
719
438
877
755
476
953
906
813
736
472
944
888
36
37
3S
39
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
014
007
003
001
551
275
637
818
915
957
978
989
228
614
807
403
366
183
091
545
851
425
712
856
806
903
951
475
640
320
660
830
625
312 5
156 25
078 125
1
2
4
8
099
199
398
796
511
023
046
093
627
255
511
022
776
552
104
208
40
41
42
43
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000 909 494 701
000 454 747 350
000 227 373 675
boo 113 686 837
772
886
443
721
928
464
232
616
237
118
059
029
915
957
478
739
039
519
758
379
062
531
766
882
5
25
625
812 5
17
35
70
140
592
184
368
737
186
372
744
488
044
088
177
355
416
832
664
328
44
45
46
47
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
056
028
014
007
843
421
210
105
418
709
854
427
860
430
715
357
808
404
202
601
014
007
003
001
869
434
717
868
689
844
422
711
941
970
485
242
406
703
351
675
25
125
56a 5
781 25
281
562
1 125
2 251
474
949
899
799
976
953
906
813
710
421
842
685
656
312
624
248
48
49
50
51
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
003
001
000
000
552
776
888
444
713
356
178
089
678
839
419
209
800
400
700
860
600
250
125
062
929
464
232
616
355
677
338
169
621
810
905
462
337
668
334
667
890
945
472
236
625
312 5
656 26
328 125
4
9
18
36
503
007
014
028
599
199
398
797
627
264
509
018
370
740
481
963
496
992
984
968
52
53
64
55
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
222
11.1
055
027
044
022
511
755
604
302
151
575
925
462
231
615
031
515
257
628
308
654
827
913
084
042
021
510
726
363
181
590
333
166
583
791
618
809
404
702
164
082
541
270
062
031
015
501
5
25
625
812 6
72
144
288
576
057
115
230
460
594
188
376
752
037
075
151
303
927
855
711
423
936
812
744
488
56
57
58
69
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
013
006
003
001
877
938
469
734
787
893
446
723
807
903
951
475
814
907
953
976
456
228
614
807
755
377
188
094
295
647
823
411
395
697
848
924
851
925
962
481
135
567
783
391
253
626
813
906
906
953
476
738
1 152 921 504 606 846 976
60
0.000 000 000 000 000 000 867 361 737 988 403 547 205 962 240 695 953 369 140 625
C-l
25
125
662 5
281 2~
DECIMAL/BINARY POSITION TABLE
Largest Decimal
Integer
1
2
4
8
17
35
70
140
1
2
4
8
17
34
68
137
274
549
099
199
398
796
592
184
368
737
1
2
4
8
16
33
67
134
268
536
073
147
294
589
179
359
719
438
877
755
511
023
046
093
186
372
744
488
1
2
4
8
16
32
65
131
262
524
048
097
194
388
777
554
108
217
435
870
741
483
967
934
869
738
476
953
906
813
627
255
511
022
044
088
177
355
1
3
7
15
31
63
127
255
511
023
047
095
191
383
767
535
071
143
287
575
151
303
607
215
431
863
727
455
911
823
647
295
591
183
367
735
471
943
887
775
551
103
207
415
831
663
327
Decimal
Digits
Req'd*
Number
of
Binary
Largest Decimal Fraction
Digits
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
.5
.75
.875
.937
.968
.984
.992
.996
.998
.999
.999
.999
.999
28
.999
.999
.999
.999
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
~99
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
~99
~99
.999
.999
.999
.999
.999
.999
.999
~99
.999
.999
.999
.999
.999
.999
.999
5
75
375
187
093
046
023
511
755
877
938
969
984
992
996
998
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
5
75
875
437 5
718 75
859 375
929 687
964 843
482 421
741 210
370 605
185 302
092 651
046 325
523 162
761 581
880 790
940 395
970 197
985 098
992 549
996 274
998 137
999068
999 534
999 767
999 883
999 941
999 970
999 985
999 992
999 996
999 998
~99 999
999 999
999 999
999 999
999999
999 999
999 999
999 999
5
75
875
937 5
468 75
734 375
367 187
683 593
841796
420 898
710 449
355 244
677 612
838 806
419 403
709 701
354 850
677 425
338 712
169 356
584 678
792 339
896 169
448 034
724 042
362 021
181 010
090 505
545 252
772 626
886 313
943 156
971 578
985 789
992 894
5
75
875
437
218
609
304
152
076
538
769
384
692
346
173
086
543
771
385
192
596
298
649
324
162
581
290
145
572
5
75
375
687
343
171
085
042
521
260
130
065
532
266
633
816
908
454
227
113
556
278
139
569
284
642
5
75
815
937
968
484
742
371
185
592
296
148
574
287
143
071
535
767
383
191
595
797
398
5
75
375
187
093
546
773
386
193
096
048
524
762
881
940
970
985
992
996
998
5
75
875
437
718
359
679
339
169
084
042
521
260
130
565
282
141
5
75
375
687
843
921
960
480
240
620
310
155
577
288
5
75
875
937
468
234
117
058
029
514
757
5
75
375
187
593
296
648
324
5
75
875
437 5
218 75
*Larger numbers within a digit group should be checked for exact number of decimal digits required.
Examples of use:
1. Q. What is the largest decimal value that can be expressed by 36 binary digits?
A.68,719,476,735.
2. Q.
How many decimal digits will be required to express a 22-bit number?
A. 7 decimal digits.
C-2
OCTAL ARITHMETIC MATRICES
ADDITION-SUBTRACTION
2
3
4
5
6
7
10
3
4
5
6
7
10
11
4
5
6
7
10
11
12
5
6
7
10
11
12
13
6
7
10
11
12
13
14
7
10
11
12
13
14
15
11
12
13
14
15
16
MULTIPLICATION-DIVISION
2
3
4
5
6
7
2
4
6
10
12
14
16
3
6
11
14
17
22
25
4
10
14
20
24
30
34
5
12
17
24
31
36
43
6
14
22
30
36
44
52
7
16
25
34
43
52
61
C-3
CONSTANTS
~'11
7r
V3
VTO
e
In 2
In10
10glO 2
log1O e
log10 log1O e
log1O 7r
1 degree
1 radian
log1O(5)
7!
8!
9!
10!
11 !
12 !
13 !
14!
15 !
16!
~
.::.
C; .. ;{S'3IfjS3 fCC)7 I 7 '1Srlb q76r£ 5-"jj8'{'? b G.5-5~fcx:J
3.14159 26535 89793 23846 26433
1.732 050 807 569
3.162 277 660 1683
2.71828 18284 59045 23536
0.69314 71805 599453
2.30258 50929 94045
0.30102 99956 63981
0.43429 44819 03251
9.63778 43113 00537
0.49714 98726 94133
0.01745 32925 11943
57.29577 95131 degrees
0.69897 00043 36019
68402
82765
85435
radians
362,880
3,628,800
39,916,800
479,001,600
6,227,020,800
87,178,291,200
1,307,674,368,000
20,922,7P9,888,000
0.01745 32925
19943 29576
~2
2.4674 01100 27233
96
(;l
3.8757
74
84585 03747
t-H4
kj5
6
t-H
t-H7
(-H8
37.0645
72481
52567
57
~9
58.2208
97135
63712
59
(;yo
91.4531
71363
36231
53
(;}2
(;}3
(;}4
50
5040
40320
180
(;t
83279
6.0880 68189
9.5631
62515 20
15149 54004 49
15.0217 06149
61413 07
23.5960 40842 00618 62
143.6543 05651
31374 95
225.6516
55645
350
354.4527
91822
91051
556.7731
43417
624
C-4
47
92369 07684 9
CONSTANTS (Continued)
7r 2
27r 2
37r2
47r 2
57r 2
67r 2
77r 2
87r 2
97r 2
9.86960
19.73920
29.60881
39.47841
49.34802
59.21762
69.08723
78.95683
88.82643
V2
1
(1
(1
(1
(1
(1
(1
(1
(1
(1
+0
+ 0)2
+ y2)4
+ V2)6
+ V2)8
+ y2)10
+ 0)12
+ V2)14
+ V2)16
+ 0)18
=
=
=
=
44010
88021
32032
76043
20054
64065
08076
52087
96098
1.414
2.414
5.828
33.970
197.994
1153.999
6725.999
39201.999
228485.999
1331713.999
7761797.999
213
213
427
562
949
. 133
851
974
995
999
999
89358
78717
68075
57434
46793
36151
25510
14868
04227
562
562
124
748
366
448
323
491
622
246
884
61883
23766
85680
47533
09417
71300
33184
95067
56950
373
373
746
477
116
220
208
027
956
711
751
Sin .5
Cos .5
Tan .5
0.47942 55386 04203
0.87758 25618 90373
0.54630 24898 43790
Sin 1
Cos 1
Tan 1
0.84147 09848 07896
0.54030 23058 68140
1.55740 77246 5490
Sin 1.5
Cos 1.5
Tan 1.5
0.99749 49866 04054
0.07073 72016 67708
14.10141 99471 707
C-5
43909
87819
31729
75639
19549
63459
07369
51279
95189
9988
9976
9964
9952
9940
9928
9916
9904
9892
095 048 801 688
095 048 801 688
18
08
30
72
02
40
38
OCTAL-DECIMAL INTEGER CONVERSION TABLE
5
6
7
0266
0274
0282
0290
0298
0306
0314
0259
0267
0275
0283
0291
0299
0307
0315
0260
0268
0276
0284
0292
0300
0308
0316
0261
0269
0277
0285
0293
0301
0309
0317
0262
0270
0278
0286
0294
0302
0310
0318
0263
0271
0279
0287
0295
0303
0311
0319
0321
0329
0337
0345
0353
0361
0369
0377
0322
0330
0338
0346
0354
0362
0370
0378
0323
0331
0339
0347
0355
0363
0371
0379
0324
0332
0340
0348
0356
0364
0372
0380
0325
0333
0341
0349
0357
0365
0373
0381
0326
0334
0342
0350
0358
0366
0374
0382
0327
0335
0343
0351
0359
0367
0375
0383
0384
0392
0400
0408
0416
0424
0432
0440
0385
0393
0401
0409
0417
0425
0433
0441
0386
0394
0402
0410
0418
0426
0434
0442
0387
0395
0403
0411
0419
0427
0435
0443
0388
0396
0404
0412
0420
0428
0436
0444
0389
0397
0405
0413
0421
0429
0437
0445
0390
0398
0406
0414
0422
0430
0438
0446
0391
0399
0407
0415
0423
0431
0439
0447
0700
0710
0720
0730
0740
0750
0760
0770
0448
0456
0464
0472
0480
0488
0496
0504
0449
0457
0465
0473
0481
0489
0497
0505
0450
0458
0466
0474
0482
0490
0498
0506
0451
0459
0467
0475
0483
0491
0499
0507
0452
0460
0468
0476
0484
0492
0500
0508
0453
0461
0469
0477
0485
0493
0501
0509
0454
0462
0470
0478
0486
0494
0502
0510
0455
0463
0471
0479
0487
0495
0503
0511
0
1
2
3
4
6
7
0519
0527
0535
0543
0551
0559
0567
0575
1400
1410
1420
1430
1440
1450
1460
1470
0768
0776
0784
0792
0800
0808
0816
0824
0769
0777
0785
0793
0801
0809
0817
0825
0770
0778
0786
0794
0802
0810
0818
0826
0771
0779
0787
0795
0803
0811
0819
0827
0772
0780
0788
0796
0804
0812
0820
0828
0773
0781
0789
0797
0805
0813
0821
0829
0774
0782
0790
0798
0806
0814
0822
0830
0775
0783
0791
0799
0807
0815
0823
0831
0582
0590
0598
0606
0614
0622
0630
0638
0583
0591
0599
0607
0615
0623
0631
0639
1500
1510
1520
1530
1540
1550
1560
1570
0832
0840
0848
0856
0864
0872
0880
0888
0833
0841
0849
0857
0865
0873
0881
0889
0834
0842
0850
0858
0866
0874
0882
0890
0835
0843
0851
0859
0867
0875
0883
0891
0836
0844
0852
0860
0868
0876
0884
0892
0837
0845
0853
0861
0869
0877
0885
0893
0838
0846
0854
0862
0870
0878
0886
0894
0839
0847
0855
0863
0871
0879
0887
0895
0645
0653
0661
0669
0677
0685
0693
0701
0646
0654
0662
0670
0678
0686
0694
0702
0647
0655
0663
0671
0679
0687
0695
0703
1600
1610
1620
1630
1640
1650
1660
1670
0896
0904
0912
0920
0928
0936
0944
0952
0897
0905
0913
0921
0929
0937
0945
0953
0898
0906
0914
0922
0930
0938
0946
0954
0899
0907
0915
0923
0931
0939
0947
0955
0900
0908
0916
0924
0932
0940
0948
0956
0901
0909
0917
0925
0933
0941
0949
0957
0902
0910
0918
0926
0934
0942
0950
0958
0903
0911
0919
0927
0935
0943
0951
0959
0709
0717
0725
0733
0741
0749
0757
0765
0710
0718
0726
0734
0742
0750
0758
0766
0711
0719
0727
0735
0743
0751
0759
0767
1700
1710
1720
1730
1740
1750
1760
1770
0960
0968
0976
0984
0992
1000
1008
1016
0961
0969
0977
0985
0993
1001
1009
1017
0962
0970
0978
0986
0994
1002
1010
1018
0963
0971
0979
0987
0995
1003
1011
1019
0964
0972
0980
0988
0996
1004
1012
1020
0965
0973
0981
0989
0997
1005
1013
1021
0966
0974
0982
0990
0998
1006
1014
1022
0967
0975
0983
0991
0999
1007
1015
1023
0
1
2
3
4
0
1
2
0000
0010
0020
0030
0040
0050
0060
0070
0000
0008
0016
0024
0032
0040
0048
0056
0001
0009
0017
0025
0033
0041
0049
0057
0002
0010
0018
0026
0034
0042
0050
0058
0003
0011
0019
0027
0035
0043
0051
0059
0004
0012
0020
0028
0036
0044
0052
0060
0005
0013
0021
0029
0037
0045
0053
0061
0006
0014
0022
0030
0038
0046
0054
0062
0007
0015
0023
0031
0039
0047
0055
0063
0400
0410
0420
0430
0440
0450
0460
0470
0256
0264
0272
0280
0288
0296
0304
0312
0257
0265
0273
0281
0289
0297
0305
0313
~258
0100
0110
0120
0130
0140
0150
0160
0170
0064
0072
0080
0088
0096
0104
0112
0120
0065
0073
0081
0089
0097
0105
0113
0121
0066
0074
0082
0090
0098
0106
0114
0122
0067
0075
0083
0091
0099
0107
0115
0123
0068
0076
0084
0092
0100
0108
0116
0124
0069
0077
0085
0093
0101
0109
0117
0125
0070
0078
0086
0094
0102
0110
0118
0126
0071
0079
0087
0095
0103
0111
0119
0127
0500
0510
0520
0530
0540
0550
0560
0570
0320
0328
0336
0344
0352
0360
0368
0376
0200
0210
0220
0230
0240
0250
0260
0270
0128
0136
0144
0152
0160
0168
0176
0184
0129
0137
0145
0153
0161
0169
0177
0185
0130
0138
0146
0154
0162
0170
0178
0186
0131
0139
0147
0155
0163
0171
0179
0187
0132
0140
0148
0156
0164
0172
0180
0188
0133
0141
0149
0157
0165
0173
0181
0189
0134
0142
0150
0158
0166
0174
0182
0190
0135
0143
0151
0159
0167
0175
0183
0191
0600
0610
0620
0630
0640
0650
0660
0670
0300
0310
0320
0330
0340
0350
0360
0370
0192
0200
0208
0216
0224
0232
0240
0248
0193
0201
0209
0217
0225
0233
0241
0249
0194
0202
0210
0218
0226
0234
0242
0250
0195
0203
0211
0219
0227
0235
0243
0251
0196
0204
0212
0220
0228
0236
0244
0252
0197
0205
0213
0221
0229
0237
0245
0253
0198
0206
0214
0222
0230
0238
0246
0254
0199
0207
0215
0223
0231
0239
0247
0255
0
1
2
3
4
5
1000
1010
1020
1030
1040
1050
1060
1070
0512
0520
0528
0536
0544
0552
0560
0568
0513
0521
0529
0537
0545
0553
0561
0569
0514
0522
0530
0538
0546
0554
0562
0570
0515
0523
0531
0539
0547
0555
0563
0571
0516
0524
0532
0540
0548
0556
0564
0572
0517
0525
0533
0541
0549
0557
0565
0573
0518
0526
0534
0542
0550
0558
0566
0574
1100
1110
1120
1130
1140
1150
1160
1170
0576
0584
0592
0600
0608
0616
0624
0632
0577
0585
0593
0601
0609
0617
0625
0633
0578
0586
0594
0602
0610
0618
0626
0634
0579
0587
0595
0603
0611
0619
0627
0635
0580
0588
0596
0604
0612
0620
0628
0636
0581
0589
0597
0605
0613
0621
0629
0637
1200
1210
1220
1230
1240
1250
1260
1270
0640
0648
0656
0664
0672
0680
0688
0696
0641
0649
0657
0665
0673
0681
0689
0697
0642
0650
0658
0666
0674
0682
0690
0698
0643
0651
0659
0667
0675
0683
0691
0699
0644
0652
0660
0668
0676
0684
0692
0700
1300
1310
1320
1330
1340
1350
1360
1370
0704
0712
0720
0728
0736
0744
0752
0760
0705
0713
0721
0729
0737
0745
0753
0761
0706
0714
0722
0730
0738
0746
0754
0762
0707
0715
0723
0731
0739
0747
0755
0763
0708
0716
0724
0732
0740
0748
0756
0764
5
6
6
7
7
C-6
3
4
5
0000
to
0777
(Octal)
0000
to
0511
(Decimal)
Octal
Decimal
10000· 4096
20000· 8192
30000 . 12288
40000 . 16384
50000 . 20480
60000· 24576
70000 . 28672
1000
to
1777
0512
to
1023
(Octal)
(Decimal)
OCTAL-DECIMAL INTEGER CONVERSION TABLE (Cont'd)
2000
1024
to
to
2777
1535
(Octall
(Decimall
Octal
Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
3000
1536
to
to
3777
2047
(Octal I
(Oecimall
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
2000
2010
2020
2030
2040
2050
2060
2070
1024
1032
1040
1048
1056
1064
1072
1080
1025
1033
1041
1049
1057
1065
1073
1081
1026
1034
1042
1050
1058
1066
1074
1082
1027
1035
1043
1051
1059
1067
1075
1083
1028
1036
1044
1052
1060
1068
1076
1084
1029·
1037
1045
1053
1061
1069
1077
1085
1030
1038
1046
1054
1062
1070
1078
1086
1031
1039
1047
1055
1063
1071
1079
1087
2400
2410
2420
2430
2440
2450
2460
2470
1280
1288
1296
1304
1312
1320
1328
1336
1281
1289
1297
1305
1313
1321
1329
1337
1282
1290
1298
1306
1314
1322
1330
1338
1283
1291
1299
1307
1315
1323
1331
1339
1284
1292
1300
1308
1316
1324
1332
1340
1285
1293
1301
1309
1317
1325
1333
1341
1286
1294
1302
1310
1318
1326
1334
1342
1287
1295
1303
1311
1319
1327
1335
1343
2100
2100
2120
2130
2140
2150
2160
2170
1088
1096
1104
1112
1120
1128
1136
1144
1089
1097
1105
1113
1121
1129
1137
1145
1090
1098
1106
1114
1122
1130
1138
1146
1091
1099
1107
1115
1123
1131
1139
1147
1092
1100
1108
1116
1124
1132
1140
1148
1093
1101
1109
1117
1125
1133
1141
1149
1094
1102
1110
1118
1126
1134
1142
1150
1095
1103
1111
1119
1127
1135
1143
1151
2500
2510
2520
2530
2540
2550
2560
2570
1344
1352
1360
1368
1376
1384
1392
1400
1345
1353
1361
1369
1377
1385
1393
1401
1346
1354
1362
1370
1378
1386
1394
1402
1347
1355
1363
1371
1379
1387
1395
1403
1348
1356
1364
1372
1380
1388
1396
1404
1349
1357
1365
1373
1381
1389
1397
1405
1350
1358
1366
1374
1382
1390
1398
1406
1351
1359
1367
1375
1383
1391
1399
1407
2200
2210
2220
2230
2240
2250
2260
2270
1152
1160
1168
1176
1184
1192
1200
1208
1153
1161
1169
1177
1185
1193
1201
1209
1154
1162
1170
1J78
1186
1194
1202
1210
1155
1163
1171
1179
1187
1195
1203
1211
1156
1164
1172
1180
1188
1196
1204
1212
1157
1165
1173
1181
1189
1197
1205
1213
1158
1166
1174
1182
1190
1198
1206
1214
1159
1167
1175
1183
1191
1199
1207
1215
2600
2610
2620
2630
2640
2650
2660
2670
1408
1416
1424
1432
1440
1448
1456
1464
1409
1417
1425
1433
1441
1449
1457
1465
1410
1418
1426
1434
1442
1450
1458
1466
1411
1419
1427
1435
1443
1451
1459
1467
1412
1420
1428
1436
1444
1452
1460
1468
1413
1421
1429
1437
1445
1453
1461
1469
1414
1422
1430
1438
1446
1454
1462
1470
1415
1423
1431
1439
1447
1455
1463
1471
2300
2310
2320
2330
2340
2350
2360
2370
1216
1224
1232
1240
1248
1256
1264
1272
1217
1225
1233
1241
1249
1257
1265
1273
1218 1219
1226 1227
1234 1235
1242 1243
1250 .1251
1258 1259
1266 1267
1274 1275
1220
1228
1236
1244
1252
1260
1268
1276
1221
1229
1237
1245
1253
1261
1269
1277
1222
1230
1238
1246
1254
1262
1270
1278
1223
1231
1239
1247
1255
1263
1271
1279
2700
2710
2720
2730
2740
2750
2760
2770
1472
1480
1488
1496
1504
1512
1520
1528
1473
1481
1489
1497
1505
1513
1521
1529
1474
1482
1490
1498
1506
1514
1522
1530
1475
1483
1491
1499
1507
1515
1523
1531
1476
1484
1492
1500
1508
1516
1524
1532
1477
1485
1493
1501
1519
1517
1525
1533
1478
1486
1494
1502
1510
1518
1526
1534
1479
1487
1495
1503
1511
1519
1527
1535
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
3000
3010
3020
3030
3040
3050
3060
3070
1536
1544
1552
1560
1568
1576
1584
1592
1537
1545
1553
1561
1569
1577
1585
1593
1538
1546
1554
1562
1570
1578
1586
1594
1539
1547
1555
1563
1571
1579
1587
1595
1540
1548
1556
1564
1572
1580
1588
1596
1541
1549
1557
1565
1573
1581
1589
1597
1542
1550
1558
1566
1574
1582
1590
1598
1543
1551
1559
1567
1575
1583
1591
1599
3400
3410
3420
3430
3440
3450
3460
3470·
1792
1800
1808
1816
1824
1832
1840
1848
1793
1801
1809
1817
1825
1833
1841
1849
1794
1802
1810
1818
1826
1834
1842
1850
1795
1803
1811
1819
1827
1835
1843
1851
1796
1804
1812
1820
1828
1836
1844
1852
1797
1805
1813
1821
1829
1837
1845
1853
1798
1806
1814
1822
1830
1838
1846
1854
1799
1807
1815
1823
1831
1839
1847
1855
3100
3110
3120
3130
3140
3150
3160
3170
1600
1608
1616
1624
1632
1640
1648
1656
1601
1609
1617
1625
1633
1641
1649
1657
1602
1610
1618
1626
1634
1642
1650
1658
1603
1611
1619
1627
1635
1643
1651
1659
1604
1612
1620
1628
1636
1644
1652
1660
1605
1613
1621
1629
1637
1645
1653
1661
1606
1614
1622
1630
1638
1646
1654
1662
1607
1615
1623
1631
1639
1647
1655
1663
3500
3510
3520
3530
3540
3550
3560
3570
1856
1864
1872
1880
1888
1896
1904
1912
1857
1865
1873
1881
1889
1897
1905
1913
1858
1866
1874
1882
1890
1898
1906
1914
1859
1867
1875
1883
1891
1899
1907
1915
1860
1868
1876
1884
1892
1900
1908
1916
1861
1869
1877
1885
1893
1901
1909
1917
1862
1870
1878
1886
1894
1902
1910
1918
1863
1871
1879
1887
1895
1903
1911
1919
3200
3210
3220
3230
3240
3250
3260
3270
1664
1672
1680
1688
1696
1704
1712
1720
1665
1673
1681
1689
1697
1705
1713
1721
1666
1674
1682
1690
1698
1706
1714
1722
1667
1675
1683
1691
1699
1707
1715
1723
1668
1676
1684
1692
1700
1708
l716
1724
1669
1677
1685
1693
1701
1709
1717
1725
1670
1678
1686
1694
1702
1710
1718
1726
1671
1679
1687
1695
1703
1711
1719
1727
3600
3610
3620
3630
3640
3650
3660
3670
1920
1928
1936
1944
1952
1960
1968
1976
1921
1929
1937
1945
1953
1961
1969
1977
1922
1930
1938
1946
1954
1962
1970
1978
1923
1931
1939
1947
1955
1963
1971
1979
1924
1932
1940
1948
1956
1964
1972
1980
1925
1933
1941
1949
1957
1965
1973
1981
1926
1934
1942
1950
1958
1966
1974
1982
1927
1935
1943
1951
1959
1967
1975
1983
3300
3310
3320
3330
3340
3350
3360
3370
1728
1736
1744
1752
1760
1768
1776
1784
1729
1737
1145
1753
1761
1769
1777
1785
1730
1738
1746
1754
1762
1170
1178
1786
1731
1739
1747
1755
1763
1771
1179
1787
1732
1740
1748
1756
1764
1772
1780
1788
1733
1741
1749
1757
1765
1773
1781
1789
1734
1742
1750
1758
1766
1774
1782
1790
1735
1743
1751
1759
1767
1775
1783
1791
3700
3710
3720
3730
3740
3750
3760
3770
19B4
1992
2000
200B
2016
2024
2032
2040
19B5
1993
2001
2009
2017
2025
2033
2041
19B6
1994
2002
2010
201B
2026
2034
2042
19B7
1995
2003
2011
2019
2027
2035
2043
19BB
1996
2004
2012
2020
2028
2036
2044
19B9
1997
2005
2013
2021
2029
2037
2045
1990
1998
2006
2014
2022
2030
2038
2046
1991
1999
2007
2015
2023
2031
2039
2047
C-7
7
OCTAL-DECIMAL INTEGER CONVERSION TABLE (Cont'd)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4000
4010
4020
4030
4040
4050
4060
4070
2048
2056
2064
2072
2080
2088
2096
2104
2049
2057
2065
2073
2081
2089
2097
2105
2050
2058
2066
2074
2082
2090
2098
2106
2051
2059
2067
2075
2083
2091
2099
2107
2052
2060
2068
2076
2084
2092
2100
2108
2053
2061
2069
2077
2085
2093
2101
2109
2054
2062
2070
2078
2086
2094
2102
2110
2055
2063
2071
2079
2087
2095
2103
2111
4400
4410
4420
4430
4440
4450
4460
4470
2304
2312
2320
2328
2336
2344
2352
2360
2305
2313
2321
2329
2337
2345
2353
2361
2306
2314
2322
2330
2338
2346
2354
2362
2307
2315
2323
2331
2339
2347
2355
2363
2308
2316
2324
2332
2340
2348
2356
2364
2309
2317
2325
2333
2341
2349
2357
2365
2310
2318
2326
2334
2342
2350
2358
2366
2311
2319
2327
2335
2343
2351
2359
2367
4100
4110
4120
4130
4140
4150
4160
4170
2112
2120
2128
2136
2144
2152
2160
2168
2113
2121
2129
2137
2145
2153
2161
2169
2114
2122
2130
2138
2146
2154
2162
2170
2115
2123
2131
2139
2147
2155
2163
2171
2116
2124
2132
2140
2148
2156
2164
2172
2117
2125
2133
2141
2149
2157
2165
2173
2118
2126
2134
2142
2150
2158
2166
2174
2119
2127
2135
2143
2151
2159
2167
2175
4500
4510
4520
4530
4540
4550
4560
4570
2368
2376
2384
2392
2400
2408
2416
2424
2369
2377
2385
2393
2401
2409
2417
2425
2370
2378
2386
2394
2402
2410
2418
2426
2371
2379
2387
2395
2403
2411
2419
2427
2372
2380
2388
2396
2404
2412
2420
2428
2373
2381
2389
2397
2405
2413
2421
2429
2374
2382
2390
2398
2406
2414
2422
2430
2375
2383
2391
2399
2407
2415
2423
2431
4200
4210
4220
4230
4240
4250
4260
4270
2176
2184
2192
2200
2208
2216
2224
2232
2177
2185
2193
2201
2209
2217
2225
2233
2178
2186
2194
2202
2210
2218
2226
2234
2179
2187
2195
2203
2211
2219
2227
2235
2180
2188
2196
2204
2212
2220
2228
2236
2181
2189
2197
2205
2213
2221
2229
2237
2182
2190
2198
2206
2214
2222
2230
2238
2183
2191
2199
2207
2215
2223
2231
2239
4600
4610
4620
4630
4640
4650
4660
4670
2432
2440
2448
2456
2464
2472
2480
2488
2433
2441
2449
2457
2465
2473
2481
2489
2434
2442
2450
2458
2466
2474
2482
2490
2435
2443
2451
2459
2467
2475
2483
2491
2436
2444
2452
2460
2468
2476
2484
2492
2437
2445
2453
2461
2469
2477
2485
2493
2438
2446
2454
2462
2470
2478
2486
2494
2439
2447
2455
2463
2471
2479
2487
2495
4300
4310
4320
4330
4340
4350
4360
4370
2240
2248
2256
2264
2272
2280
2288
2296
2241
2249
2257
2265
2273
2281
2289
2297
2242
2250
2258
2266
2274
2282
2290
2298
2243
2251
2259
2267
2275
2283
2291
2299
2244
2252
2260
2268
2276
2284
2292
2300
2245
2253
2261
2269
2277
2285
2293
2301
2246
2254
2262
2270
2278
2286
2294
2302
2247
2255
2263
2271
2279
2287
2295
2303
4700
4710
4720
4730
4740
4750
4760
4770
2496
2504
2512
2520
2528
2536
2544
2552
2497
2505
2513
2521
2529
2537
2545
2553
2498
2506
2514
2522
2530
2538
2546
2554
2499
2507
2515
2523
2531
2539
2547
2555
2500
2508
2516
2524
2532
2540
2548
2556
2501
2509
2517
2525
2533
2541
2549
2557
2502
2510
2518
2526
2534
2542
2550
2558
2503
2511
2519
2527
2535
2543
2551
2559
1
2
4
5
6
7
0
1
2
3
4
5
6
7
0
3
5000
5010
5020
5030
5040
5050
5060
5070
2560
2568
2576
2584
2592
2600
2608
2616
2561
2569
2577
2585
2593
2601
2609
2617
2562
2570
2578
2586
2594
2602
2610
2618
2563
2571
2579
2587
2595
2603
2611
2619
2564
2572
2580
2588
2596
2604
2612
2620
2565
2573
2581
2589
2597
2605
2613
2621
2566
2574
2582
2590
2598
2606
2614
2622
2567
2575
2583
2591
2599
2607
2615
2623
5400
5410
5420
5430
5440
5450
5460
5470
2816
2824
2832
2840
2848
2856
2864
2872
2617
2825
2833
2841
2849
2857
2865
2873
2818
2826
2834
2842
2850
2858
2866
2874
2819
2827
2835
2843
2851
2859
2867
2875
2820
2828
2836
2844
2852
2860
2868
2876
2821
2829
2837
2845
2853
2861
2869
2877
2822
2830
2838
2846
2854
2862
2870
2878
2823
2831
2839
2847
2855
2863
2871
2879
5100
5110
5120
5130
5140
5150
5160
5170
2624
2632
2640
2648
2656
2664
2672
2680
2625
2633
2641
2649
2657
2665
2673
2681
2626
2634
2642
2650
2658
2666
2674
2682
2627
2635
2643
2651
2659
2667
2675
2683
2628
2636
2644
2652
2660
2668
2676
2684
2629
2637
2645
2653
2661
2669
2677
2685
2630
2638
2646
2654
2662
2670
2678
2686
2631
2639
2647
2655
2663
2671
2679
2687
5500
5510
5520
5530
5540
5550
5560
5570
2880
2888
2896
2904
2912
2920
2928
2936
2881
2889
2897
2905
2913
2921
2929
2937
2882
2890
2898
2906
2914
2922
2930
2938
2883
2891
2899
2907
2915
2923
2931
2939
2884
2892
2900
2908
2916
2924
2932
2940
2885
2893
2901
2909
2917
2925
2933
2941
2886
2894
2902
2910
2918
2926
2934
2942
2887
2895
2903
2911
2919
2927
2935
2943
5200
5210
5220
5230
5240
5250
5260
5270
2688
2696
2704
2712
2720
2728
2736
2744
2689
2697
2705
2713
2721
2729
2737
2745
2690
2698
2706
2714
2722
2730
2738
2746
2691
2699
2707
2715
2723
2731
2739
2747
2692
2700
2708
2716
2724
2732
2740
2748
2693
2701
2709
2717
2725
2733
2741
2749
2694
2702
2710
2718
2726
2734
2742
2750
2695
2703
2711
2719
2727
2735
2743
2751
5600
5610
5620
5630
5640
5650
5660
5670
2944
2952
2960
2968
2976
2984
2992
3000
2945
2953
2961
2969
2977
2985
2993
3001
2946
2954
2962
2970
2978
2986
2994
3002
2947
2955
2963
2971
2979
2987
2995
3003
2948
2956
2964
2972
2980
2988
2996
3004
2949
2957
2965
2973
2981
2989
2997
3005
2950
2958
2966
2974
2982
2990
2998
3006
2951
2959
2967
2975
2983
2991
2999
3007
5300
5310
5320
5330
5340
5350
5360
5370
2752
2760
2768
2776
2784
2792
2800
2808
2753
2761
2769
2777
2785
2793
2801
2809
2754
2762
2770
2778
2786
2794
2802
2810
2755
2763
2771
2779
2787
2795
2803
2811
2756
2764
2772
2780
2788
2796
2804
2812
2757
2765
2773
2781
2789
2797
2805
2813
2758
2766
2774
2782
2790
2798
2806
2814
2759
2767
2775
2783
2791
2799
2807
2815
5700
5710
5720
5730'
5740
5750
5760
5770
3008
3016
3024
3032
3040
3048
3056
3064
3009
3017
3025
3033
3041
3049
3057
3065
3010
3018
3026
3034
3042
3050
3058
3066
3011
3019
3027
3035
3043
3051
3059
3067
3012
3020
3028
3036
3044
3052
3060
3068
3013
3021
3029
3037
3045
3053
3061
3069
3014
3022
3030
3038
3046
3054
3062
3070
3015
3023
3031
3039
3047
3055
3063
3071
C-8
4000
to
4777
(Octal)
2048
to
2559
(Decimal)
Octal Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
5000
to
5777
(Detail
2560
to
3071
(Decimal I
OCTAL-DECIMAL INTEGER CONVERSION TABLE (Cont'd)
6000
to
6777
(Detail
3072
to
3583
(Decimall
Octal Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
7000
to
7777
(Octall
3584
to
4095
(Decimall
5
6
7
3332
3340
3348
3356
3364
3372
3380
3388
3333
3341
3349
3357
3365
3373
3381
3389
3334
3342
3350
3358
3366
3374
3382
3390
3335
3343
3351
3359
3367
3375
3383
3391
3393 3394 3395
3401 3402 3403
3409 3410 3411
3417 3418 3419
3425 3426 3427
3433 3434 3435
3441 3442 3443
3449 3450 3451
3396
3404
3412
3420
3428
3436
3444
3452
3397 3398
3405 3406
3413 3414
3421 3422
3429 3430
3437 3438
3445 3446
3453 3454
3399
3407
3415
3423
3431
3439
3447
3455
3456
3464
3472
3480
3488
3496
3504
3512
3457
3465
3473
3481
3489
3497
3505
3513
3458
3466
3474
3482
3490
3498
3506
3514
3459
3467
3475
3483
3491
3499
3507
3515
3460
3468
3476
3484
3492
3500
3508
3516
3461
3469
3477
3485
3493
3501
3509
3517
3462
3470
3478
3486
3494
3502
3510
3518
3463
3471
3479
3487
3495
3503
3511
3519
3520
3528
3536
3544
3552
3560
3568
3576
3521
3529
3537
3545
3553
3561
3569
3577
3522
3530
3538
3546
3554
3562
3570
3578
3523
3531
3539
3547
3555
3563
3571
3579
3524
3532
3540
3548
3556
3564
3572
3580
3525
3533
3541
3549
3557
3565
3573
3581
3526
3534
3542
3550
3558
3566
3574
3582
3527
3535
3543
3551
3559
3567
3575
3583
0
1
2
3
4
5
6
7400
7410
7420
7430
7440
7450
7460
7470
3840
3848
3856
3864
3872
388(0
3888
3896
3841
3849
3857
3865
3873
3881
3889
3897
3842
3850
3858
3866
3874
3882
3890
3898
3843
3851
3859
3867
3875
3883
3891
3899
3844
3852
3860
3868
3876
3884
3892
3900
3845
3853
3861
3869
3877
3885
3893
3901
3846
3854
3862
3870
3878
3886
3894
3902
3847
3855
3863
3871
3879
3887
3895
3903
3655
3663
3671
3679
3687
3695
3703
3711
7500
7510
7520
7530
7540
7550
7560
7570
3904
3912
3920
3928
3936
3944
3952
3960
3905
3913
3921
3929
3937
3945
3953
3961
3906
3914
3922
3930
3938
3946
3954
3962
3907
3915
3923
3931
3939
3947
3955
3963
3908
3916
3924
3932
3940
3948
3956
3964
3909
3917
3925
3933
3941
3949
3957
3965
3910
3918
3926
3934
3942
3950
3958
3966
3911
3919
3927
3935
3943
3951
3959
3967
3718
3726
3734
3742
3750
3758
3766
3774
3719
3727
3735
3743
3751
3759
3767
3775
7600
7610
7620
7630
7640
7650
7660
7670
3968
3976
3984
3992
4000
4008
4016
4024
3969
3977
3985
3993
4001
4009
4017
4025
3970
3978
3986
3994
4002
4010
4018
4026
3971
3979
3987
3995
4003
4011
4019
4027
3972
3980
3988
3996
4004
4012
4020
4028
3973
3981
3989
3997
4005
4013
4021
4029
3974
3982
3990
3998
4006
4014
4022
4030
3975
3983
3991
3999
4007
4015
4023
4031
3782
3790
3798
3806
3814
3822
3830
3838
3783
3791
3799
3807
3815
3823
3831
3839
7700
7710
7720
7730
7740
7750
7760
7770
4032
4040
4048
4056
4064
4072
4080
4088
4033
4041
4049
4057
4065
4073
4081
4089
4034
4042
4050
4058
4066
4074
4082
4090
4035
4043
4051
4059
4067
4075
4083
4091
4036
4044
4052
4060
4068
4076
4084
4092
4037
4045
4053
4061
4069
4077
4085
4093
4038
4046
4054
4062
4070
4078
4086
4094
4039
4047
4055
4063
4071
4079
4087
4095
6
0
1
2
3
4
5
0
1
2
3
6000
6010
6020
6030
6040
6050
6060
6070
3072
3080
3088
3096
3104
3112
3120
3128
3073
3081
3089
3097
3105
3113
3121
3129
3074
3082
3090
3098
3106
3114
3122
3130
3075
3083
3091
3099
3107
3115
3123
3131
3076
3084
3092
3100
3108
3116
3124
3132
3077
3085
3093
3101
3109
3117
3125
3133
3078
3086
3094
3102
3110
3118
3126
3134
3079
3087
3095
3103
3111
3119
3127
3135
6400
6410
6420
6430
6440
6450
6460
6470
3328
3336
3344
3352
3360
3368
3376
3384
3329
3337
3345
3353
3361
3369
3377
3385
3330
3338
3346
3354
3362
3370
3378
3386
3331
3339
3347
3355
3363
3371
3379
3387
6100
6110
6120
6130
6140
6150
6160
6170
3136
3144
3152
3160
3168
3176
3184
3192
3137
3145
3153
3161
3169
3177
3185
3193
3138
3146
3154
3162
3170
3178
3186
3194
3139
3147
3155
3163
3171
3179
3187
3195
3140
3148
3156
3164
3172
3180
3188
3196
3141
3149
3157
3165
3173
3181
3189
3197
3142
3150
3158
3166
3174
3182
3190
3198
3143
3151
3159
3167
3175
3183
3191
3199
6500
6510
6520
6530
6540
6550
6560
6570
3392
3400
3408
3416
3424
3432
3440
3448
6200
6210
6220
6230
6240
6250
6260
6270
3200
3208
3216
3224
3232
3240
3248
3256
3201
3209
3217
3225
3233
3241
3249
3257
3202
3210
3218
3226
3234
3242
3250
3258
3203
3211
3219
3227
3235
3243
3251
3259
3204
3212
3220
3228
3236
3244
3252
3260
3205
3213
3221
3229
3237
3245
3253
3261
3206
3214
3222
3230
3238
3246
3254
3262
3207
3215
3223
3231
3239
3247
3255
3263
6600
6610
6620
6630
6640
6650
6660
6670
6300
6310
6320
6330
6340
6350
6360
6370
3264
3272
3280
3288
3296
3304
3312
3320
3265
3273
3281
3289
3297
3305
3313
3321
3266
3274
3282
3290
3298
3306
3314
3322
3267
3275
3283
3291
3299
3307
3315
3323
3268
3276
3284
3292
3300
3308
3316
3324
3269
3277
3285
3293
3301
3309
3317
3325
3270
3278
3286
3294
3302
3310
3318
3326
3271
3279
3287
3295
3303
3311
3319
3327
6700
6710
6720
6730
6740
6750
6760
6770
0
1
2
3
4
5
6
7
7000
7010
7020
7030
7040
7050
7060
7070
3584
3592
3600
3608
3616
3624
3632
3640
3585
3593
3601
3609
3617
3625
3633
3641
3586
3594
3602
3610
3618
3626
3634
3642
3587
3595
3603
3611
3619
3627
3635
3643
3588
3496
3604
3612
3620
3628
3636
3644
3589
3497
3605
3613
3621
3629
3637
3645
3590
3598
3606
3614
3622
3630
3638
3646
3591
3599
3607
3615
3623
3631
3639
3647
7100
7110
7120
7130
7140
7150
7160
7170
3648
3656
3664
3672
3680
3688
3696
3704
3649
3657
3665
3673
3681
3689
3697
3705
3650
3658
3666
3674
3682
3690
3698
3706
3651
3659
3667
3675
3683
3691
3699
3707
3652
3660
3668
3676
3684
3692
3700
3708
3653
3661
3669
3677
3685
3693
3701
3709
3654
3662
3670
3678
3686
3694
3702
3710
7200
7210
7220
7230
7240
7250
7260
7270
3712
3720
3728
3736
3744
3752
3760
3768
3713
3721
3729
3737
3745
3753
3761
3769
3714
3722
3730
373B
3746
3754
3762
3770
3715
3723
3731
3739
3747
3755
3763
3771
3716
3724
3732
3740
3748
3756
3764
3772
3717
3725
3733
3741
3749
3757
3765
3773
7300
7310
7320
7330
7340
7350
7360
7370
3776
3784
3792
3800
3808
3816
3824
3832
3777
3785
3793
3801
3809
3817
3825
3833
3778
3786
3794
3802
3810
3818
3826
3834
3779
3787
3795
3803
3811
3819
3827
3835
3780
3788
3796
3804
3812
3820
3828
3836
3781
3789
3797
3805
3813
3821
3829
3837
7
C-9
4
7
OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL
DEC.
OCTAL
.000
.001
.002
.003
.004
.005
.006
.007
.000000
.001953
.003906
.005859
.007812
.009765
.011718
.013671
.100
.101
.102
.103
.104
.105
.106
.107
.010
.011
.012
.013
.014
.015
.016
.017
.015625
.017578
.019531
.021484
.023437
.025390
.027343
.029296
.020
.021
.022
.023
.024
.025
.026
.027
DEC.
OCTAL
DEC.
OCTAL
DEC.
.125000
.126953
.128906
.130859
.132812
.134765
.136718
.138671
.200
.201
.202
.203
.204
.205
.206
.207
.250000
.251953
.253906
.255859
.257812
.259765
.261718
.263671
.300
.301
.302
.303
.304
.305
.306
.307
.375000
.376953
.378906
.380859
.382812
.384765
.386718
.388671
.110
.111
.112
.113
.114
.115
.116
.117
.140625
.142578
.144531
.146484
.148437
.150390
.152343
.154296
.210
.211
.212
.213
.214
.215
.216
.217
.265625
.267578
.269531
.271484
.273437
.275390
.277343
.279296
.310
.311
.312
.313
.314
.315
.316
.317
.390625
.392578
.394531
.396484
.398437
.400390
.402343
.404296
.031250
.033203
.035156
.037109
.039062
.041015
.042968
.044921
.120
.121
.122
.123
.124
.125
.126
.127
.156250
.158203
.160156
.162109
.164062
.166015
.167968
.169921
.220
.221
.222
.223
.224
.225
.226
.227
.281250
.283203
.285156
.287109
.289062
.291015
.292968
.294921
.320
.321
.322
.323
.324
.325
.326
.327
.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921
.030
.031
.032
.033
.034
.035
.036
.037
.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546
.130
.131
.132
.133
.134
.135
.136
.137
.171875
.173828
.175781
.177734
.179687
.181640
.183593
.185546
.230
.231
.232
.233
.234
.235
.236
.237
.296875
.298828
.300781
.302734
.304687
.306640
.308593
.310546
.330
.331
.332
.333
.334
.335
.336
.337
.421875
.423828
.425781
.427734
.429687
.431640
.433593
.435546
.040
.041
.042
.043
.044
.045
.046
.047
.062500
.064453
.066406
.068359
.070312
.072265
.074218
.076171
.140
.141
.142
.143
.144
.145
.146
.147
.187500
.189453
.191406
.193359
.195312
.197265
.199218
.201171
.240
.241
.242
.243
.244
.245
.246
.247
.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171
.340
.341
.342
.343
.344
.345
.346
.347
.437500
.439453
.441406
.443359
.445312
.447265
.449218
.451171
.050
.051
.052
.053
.054
.055
.056
.057
.078125
.080078
.082031
.083984
.085937
.087890
.089843
.091796
.150
.151
.152
.153
.154
.155
.156
.157
.203125
.205078
.207031
.208984
.210937
.212890
.214843
.216796
.250
.251
.252
.253
.254
.255
.256
.257
.328125
.330078
.332031
.333984
.335937
.337890
.339843
.341796
.350
.351
.352
.353
.354
.355
.356
.357
.453125
.455078
.457031
.458984
.460937
.462890
.464843
.466796
.060
.061
.062
.063
.064
.065
.066
.067
.093750
.095703
.097656
.099609
.101562
.103515
.105468
.107421
.160
.161
.162
.163
.164
.165
.166
.167
.218750
.220703
.222656
.224609
.226562
.228515
.230468
.232421
.260
.261
.262
.263
.264
.265
.266
.267
.343750
.345703
.347656
.349609
.351562
.353515
.355468
.357421
.360
.361
.362
.363
.364
.365
.366
.367
.468750
.470703
.472656
.474609
.476562
.478515
.480468
.482421
.070
.071
.072
.073
.074
.075
.076
.077
.109375
.111328
.113281
.115234
.117187
.119140
.121093
.123046
.170
.171
.172
.173
.174
.175
.176
.177
.234375
.236328
.238281
.240234
.242187
.244140
.246093
.248046
.270
.271
.272
.273
.274
.275
.276
.277
.359375
.361328
.363281
.365234
.367187
.369140
.371093
.373046
.370
.371·
.372
.373
.374
.375
.376
.377
.484375
.486328
.488281
.490234
.492187
.494140
.496093
.498046
C-IO
OCTAL-DECIMAL FRACTION CONVERSION TABLE (Cont'd)
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC .
.000000
.000001
.000002
.000003
.000004
.000005
.000006
.000007
.000000
.000003
.000007
.000011
.000015
.000019
.000022
.000026
.000100
.000101
.000102
.000103
.000104
.000105
.000106
.000107
.000244
.000247
.000251
.000255
.000259
.000263
.000267
.000270
.000200
.000201
.000202
.000203
.000204
.00"0205
.000206
.000207
.000488
.000492
.000495
.000499
.000503
.000507
.000511
.000514
.000300
.000301
.000302
.000303
.000304
.000305
.000306
.000307
.000732
.000736
.000740
.000743
.000747
.000751
.000755
.000759
.000010
.000011
.000012
.000013
.000014
.000015
.000016
.000017
.000030
.000034
.000038
.000041
.000045
.000049
.000053
.000057
.000110
.000111
.000112
.000113
.000114
.000115
.000116
.000117
.000274
.000278
.000282
.000286
.000289
.000293
.000297
.000301
.000210
.000211
.000212
.000213
.000214
.000215
.000216
.000217
.000518
.000522
.000526
.000530
.000534
.000537
.000541
.000545
.000310
.000311
.000312
.000313
.000314
.000315
.000316
.000317
.000762
.000766
.000770
.000774
.000778
.000782
.000785
.000789
.000020
.000021
.000022
.000023
.000024
.000025
.000026
.000027·
.000061
.000064
.000068
.000072
.000076
.000080
.000083
.000087
.000120
.000121
.000122
.000123
.000124
.000125
.000126
.000127
.000305
.000308
.000312
.000316
.000320
.000324
.000328
.000331
.000220
.000221
.000222
.000223
.000224
.000225
.000226
.000227
.000549
.000553
.000556
.000560
.000564
.000568
.000572
.000576
.000320
.000321
.000322
.000323
.000324
.000325
.000326
.000327
.000793
.000797
.000801
.000805
.000808
.000812
.000816
.000820
.000030
.000031
.000032
.000033
.000034
.000035
.000036
.000037
.000091
.000095
.000099
.000102
.000106
.000110
.000114
.0001; 8
.000130
.000131
.000132
.000133
.000134
.000135
.000136
.000137
.000335
.000339
.000343
.000347
.000350
.000354
.000358
.000362
.000230
.000231
.000232
.000233
.000234
.000235
.000236
.000237
.000579
.000583
.000587
.000591
.000595
.000598
.000602
.000606
.000330
.000331
.000332
.000333
.000334
.000335
.000336
.000337
.000823
.000827
.000831
.000835
.000839
.000843
.000846
.000850
.000040
.000041
.000042
.000043
.000044
.000045
.000046
.000047
.000122
.000125
.000129
.000133
.000137
.000141
.000144
.000148
.000140
.000141
.000142
.000143
.000144
.000145
.000146
.000147
.000366
.000370
.000373
.000377
.000381
.000385
.000389
.000392
.000240
.000241
.000242
.000243
.000244
.000245
.000246
.000247
.000610
.000614
.000617
.000621
.000625
.000629
.000633
.000637
.000340
.000341
.000342
.000343
.000344
.000345
.000346
.000347
.000854
.000858
.000862
.000865
.000869
.000873
.000877
.000881
.000050
.000051
.000052
.000053
.000054
.000055
.000056
.000057
.000152
.000156
.000160
.000164
.000167
.000171
.000175
.000179
.000150
.000151
.000152
.000153
.000154
.000155
.000156
.000157
.000396
.000400
.000404
.000408
.000411
.000415
.000419
.000423
.000250
.000251
.000252
.000253
.000254
.000255
.000256
.000257
.000640
.000648
.000652
.000656
.000659
.000663
..000667
.000350
.000351
.000352
.000353
.000354
.000355
.000356
.000357
.000885
.000888
.000892
.000896
.000900
.000904
.000907
.000911
.000060
.000061
.000062
.000063
.000064
.000065
.000066
.000067
.000183
.000186
.000190
.000194
.000198
.000202
.000205
.000209
.000160
.000161
.000162
.000163
.000164
.000165
.000166
.000167
.000427
.000431
.000434
.000438
.000442
.000446
.000450
.000453
.000260
.000261
.000262
.000263
.000264
.000265
.000266
.000267
.000671
.000675
.000679
.000682
.000686
.000690
.000694
.000698
.000360
.000361
.000362
.000363
.000364
.000365
.000366
.000367
.000915
.000919
.000923
.000926
.000930
.000934
.000938
.000942
.000070
.000071
.000072
.000073
.000074
.000075
.000076
.000077
.000213
.000217
.000221
.000225
.000228
.000232
.000236
.000240
.000170
.000171
.000172
.000173
.000174
.000175
.000176
.000177
.000457
.000461
.000465
.000469
.000473
.000476
.000480
.000484
.000270
.000271
.000272
.000273
.000274
.000275
.000276
.000277
.000701
.000705
.000709
.000713
.000717
.000720
.000724
.000728
.000370
.000371
.000372
.000373
.000374
.000375
.000376
.000377
.000946
.000949
.000953
.000957
.000961
.000965
.000968
.000972
C-ll
.000p44
OCTAL-DECIMAL FRACTION CONVERSION TABLE (Cont'd)
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
.000400
.000401
.000402
.000403
.000404.
.000405
.000406
.000407
.000976
.000980
.000984
.000988
.000991
.000995
.000999
.001003
.000500
.000501
.000502
.000503
.000504
.000505
.000506
.000507
.001220
.001224
.001228
.001232
.001235
.001239
.001243
.001247
.000600
.000601
.000602
.000603
.000604
.000605
.000606
.000607
.001464
.001468
.001472
.001476
.001480
.001483
.001487
.001491
.000700
.000701
.000702
.000703
.000704
.000705
.000706
.000707
.001708
.001712
.001716
.001720
.001724
.001728
.001731
.001735
.000410
.000411
.000412
.000413
.000414
.000415
.000416
.000417
.001007
.001010
.001014
.001018
.001022
.001026
.001029
.001033
.000510
.000511
.000512
.000513
.000514
.000515
.000516
.000517
.001251
.001255
.001258
.001262
.001266
.001270
.001274
.001277
.000610
.000611
.000612
.000613
.000614
.000615
.000616
.000617
.001495
.001499
.001502
.001506
.001510
.001514
.001518
.001522
.000710
.000711
.000712
.000713
.000714
.000715
.000716
.000717
.001739
.001743
.001747
.001750
.001754
.001758
.001762
.001766
.000420
.000421
.000422
.000423
.000424
.000425
.000426
.000427
.001037
.001041
.001045
.001049
.001052
.001056
.001060
.001064
.000520
.000521
.000522
.000523
.000524
.000525
.000526
.000527
.001281
.001285
.001289
.001293
.001296
.001300
.001304
.001308
.000620
.000621
.000622
.000623
.000624
.000625
.000626
.000627
.001525
.001529
.001533
.001537
.001541
.001544
.001548
.001552
.000720
.000721
.000722
.000723
.000724
.000725
.000726
.000727
.001770
.001773
.001777
.001781
.001785
.001789
.001792
.001796
.000430
.000431
.000432
.000433
.000434
.000435
.000436
.000437
.001068
.001071
.001075
.001079
.001083
.001087
.001091
.001094
.000530
.000531
.000532
.000533
.000534
.000535
.000536
.000537
.001312
.001316
.001319
.001323
.001327
.001331
.001335
.001338
.000630
.000631
.000632
.000633
.000634
.000635
.000636
.000637
.001556
.001560
.001564
.001567
.001571
.001575
.001579
.001583
.000730
.000731
.000732
.000733
.000734
.000735
.000736
.000737
.001800
.001804
.001808
.001811
.001815
.001819
.0(}1823
.001827
.000440
.000441
.000442
.000443
.000444
.000445
.000446
,000447
.001098
.001102
.001106
.001110
.001113
.001117
.001121
,001125
.000540
.000541
.000542
.000543
.000544
.000545
,000546
.000547
.001342
.001346
.001350
.001354
.001358
.001361
,001365
.001369
.000640
.000641
.000642
.000643
.000644
.000645
,000646
.000647
.001586
.001590
.001594
.001598
.001602
.001605
.001609
.001613
.000740
.000741
.000742
.000743
.000744
.000745
,000746
.000747
.001831
.001834
.001838
.001842
.001846
.001850
,001853
.001857
.000450
.000451
.000452
.000453
.000454
,000455
.000456
.000457
.001129
.001132
.001136
.001140
.001144
,001148
.001152
.001155
.000550
.000551
.000552
,000553
.000554
,000555
.000556
,000557
,001373
.001377
.001380
,001384
.001388
.001392
.001396
,001399
,000650
.000651
.000652
,000653
,000654
.000655
.000656
,000657
.001617
.001621
.001625
.001628
.001632
.001636
.001640
.001644
,000750
.000751
.000752
.000753
.000754
.000755
.000756
,000757
.001861
.001865
.001869
.001873
.001876
.001880
.001884
.001888
.000460
,000461
.000462
.000463
.000464
,000465
.000466
.000467
.001159
.001163
.001167
.001171
.001174
.001178
.001182
.001186
.000560
.000561
.000562
.000563
,000564
.000565
.000566
.000567
.001403
.001407
.001411
.001415
,001419
.001422
.001426
.001430
.000660
.000661
.000662
.000663
.000664
.000665
,000666
.000667
.001647
.001651
.001655
.001659
.001663
,001667
,001670
.001674
.000760
,000761
.000762
.000763
.000764
.000765
,000766
.000767
.001892
,001895
,001899
,001903
.001907
.001911
,001914
.001918
.000470
.000471
,000472
.000473
.000474
.000475
,000476
.000477
.001190
.001194
.001197
.001201
.001205
.001209
,001213
.001216
.000570
.000571
.000572
.000573
.000574
.000575
.000576
.000577
.001434
.001438
.001441
.001445
.001449
.001453
.001457
.001461
.000670
,000671
.000672
.000673
.000674
,000675
.000676
,000677
.001678
,001682
.001686
,001689
,001693
.001697
,001701
.001705
.000770
.000771
.000772
.000773
.000774
.000775
.000776
.000777
,001922
,001926
.001930
.001934
.001937
,001941
.001945
.001949
C-12
GLOSSARY, INSTRUCTION TABLES and INDEX
GLOSSARy ....................................................................... 1
INSTRUCTION TABLES ........................................................... 7
(See Section 7 for detailed instruction and designator descriptions.)
Table 1. Octal Listing of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7
Table 2. Alphamnemonic Listing of Instructions ................................... 12
Table 3. Function Listing of Instructions .......................................... 17
INDEX ............................................................................ 23
GLOSSARY
A REGISTER - Principal arithmetic register; operates as a 24-bit additive accumulator
(modulus 224-1).
ABSOLUTE ADDRESS- Synonymous with Address.
ACCESS TIME - The time needed to perform a storage reference, either read or write.
In effect, the access time of a computer is one storage reference cycle.
ACCUMULATOR - A register with provisions for the addition of another quantity to
its content.
ADDER-A device capable of forming the sum of two or more quantities.
ADDRESS-A 15-bit operand which identifies a particular storage location; a 17-bit
operand which identifies a particular character location in storage.
ADDRESS MODIFICATION -Normally tlie derivation of a storage address from the
sum of the execution address and the contents of the specified index register.
AND FUNCTION -A logical function in Boolean algebra that is satisfied (has the value
"1") only when all of its terms are "1 's". For any other combination of values it is
not satisfied and its value is "0".
ARGUMENT-An operand or parameter used by a program or an instruction.
ASSEMBLER-A program which translates statements to machine language. Normally,
one source language statement results in the generation of one line of object code.
BASE - A quantity which defines some system of representing numbers by positional
notation; radix.
BINARY-CODED DECIMAL (BCD)-A form of decimal notation where decimal digits
are represented by a binary code.
BIT-Binary digit, either "I" or "0".
BLOCK - A sequential group of storage words or characters in storage.
BOOTSTRAP - Any short program which facilitates loading of the appropriate system
executive.
BRANCH-A conditional jump. Refer to Jump.
BREAKPOINT-A point in a routine at which the computer may be stopped by manual
switches for a visual check of progress.
Bl, B2, B3 REGISTERS- Index registers used primarily for address modification
and/or counting.
BUFFER - Any area that is used to hold data temporarily for input or output, normally
storage.
BYTE-A portion of a computer word.
CAPACITY -The upper and lower limits of the numbers which may be processed in
a register, or the quantity of information which may be stored in a storage unit. If
the capacity of a register is exceeded, an overflow is generated.
CHANNEL-An Input/Output (110) transmission path that connects the computer
to an external equipment.
CHARACTER-A group of 6 bits which represents a digit, letter or symbol from the
typewriter.
1
CLEAR - An operation that removes a quantity from a register by placing every stage
of the register in the "0" state. The initial contents of the register are destroyed by
the Clear operation.
COMMAND - Synonymous with Instruction.
COMPILER - A program with the compatability to generate more than one line of
machine code (instruction or data word) from one source language statement.
COMPLEMENT - Noun: See One's Complement or Two's Complement. Verb: A command which produces the one's complement of a given quantity.
CONTENT-The quantity or word held in a register or storage location.
CORE - A ferromagnetic toroid used as the bi-stable device for storing a bit in a
memory plane.
COUNTER- A register or storage location, the contents of which may be incremented
or decremented.
D REGISTER-A 4-bit field length register used for BCD operations.
DOUBLE PRECISION - Providing greater precision in the results of arithmetic operations by appending 24 additional bits of lesser significance to the initial operands.
ENTER - The operation where the current contents of a register or storage location are
replaced by some defined operand.
EQUALIZE-Adjusting the operand of the algebraically smaller exponent to equal the
larger, prior to adding or subtracting the floating point coefficients.
EXCLUSIVE OR-A logical function in Boolean algebra that is satisfied (has the value
"I") when any of its terms are "I". It is not satisfied when all its terms are "I" or
when all its terms are "0".
EXECUTION ADDRESS-The lower 15 or 17 bits of a 24-bit instruction. Most often
used to specify the storage address of an operand. Sometimes used as the operand.
EXIT - Initiation of a second control sequence by the first, occurring when the first is
near completion; the circuit involved in exiting.
F REGISTER-Program Control register. Holds a program step while the single 24-bit
instruction contained in it is executed.
FA UL T - Operational difficulty which lights an indicator or for which interrupt may be '
selected.
FIXED POINT-A notation or system of arithmetic in which all numerical quantities
are expressed by a predetermined number of digits with the binary point implicitly
located at some predetermined position; contrasted with floating point.
FLIP-FLOP (FF)-A bi-stable storage device. A "I" input to the set side puts the FF
in the "I" state; a "I" input to the clear side puts the FF in the "0" state. The
FF remains in a state indicative of its last "I" input. A stage of a register consists of a FF.
FLOATING POINT - A means of expressing a number, X, by a pair of numbers, Y and
Z, such that X = Yn Z • Z is an integer called the exponent or characteristic; n is a base,
usually 2 or 10; and Y is called the fraction or mantissa.
FUNCTION CODE - See Operation Code.
INCREASE - The increase operation adds a quantity to the contents of the specified
register.
INDEX DESIGNATOR-A 2-bit quantity in an instruction; usually specifies an index
register whose contents are to be added to the execution address; sometimes specifies
the conditions for executing the instruction.
2
INDIRECT AODRESSING-A method of address modification whereby the lower 18
bits of the specified address become the new execution address and index designator.
INSTRUCTION - A 24- or 48-bit quantity consisting of an operation code and several
other designators.
INTEGRATED REGISTER FILE - The upper 6410 locations of core storage. Reserved
for special operations with block control.
INTERRUPT-A signal which results in transfer of control, following completion of the
current instruction cycle, to a fixed storage location.
INTERRUPT REGISTER-A 24-bit register whose individual bits are set to "I" by
the occurrence of specific interrupt conditions, either internal or external.
INTERRUPT MASK REGISTER-A 24-bit register whose individual bits match those
of the Interrupt register. Setting bits of the Interrupt Mask register to "l's" is one
of the conditions for selecting interrupt.
INVERTER-A circuit which provides as an output a signal that is opposite to its
input. An inverter output is "1" only if all the separate OR inputs are "0".
JUMP-An instruction which alters the normal sequence control of the computer and,
conditionally or unconditionally, specifies the location of the next instruction.
LIBRARY - Any collection of programs (routines) and/or subprograms (subroutines).
LOAD-The Load operation is composed of two steps: a) The register is cleared, and
b) The contents of storage location M are copied into the cleared register.
LOCATION - A storage position holding one computer word, usually designated by a
specific address.
LOGICAL PRODUCT-In Boolean algebra, the AND function of several terms. The
product is "I" only when all the terms are "I"; otherwise it is "0". Sometimes
referred to as the result of bit-by-bit multiplication.
LOGICAL SUM - In Boolean algebra, the OR function of several terms. The sum is
"I" when any or all of the terms are "1"; it is "0" only when all are "0".
LOOP - Repetition of a group of instructions in a routine.
MACRO CODE-A method of defining a subroutine which can be generated and/or
inserted by the assembler.
MASK- In the formation of the logical product of two quantities, one quantity may
mask the other; i.e., determine what part of the other quantity is to be considered.
If the mask is "0", that part of the other quantity is unused; if the mask is "I", the
other quantity is used.
MASTER CLEAR-A general command produced by pressing one of two switches:
a) Internal Master Clear- Clears all operational registers and control FF's in the
processor. b) External Master Clear - Clears all external equipments and the communication channels.
MNEMONIC CODE-A three- or four-letter code which represents the function or
purpose of an instruction. Also called Alphabetic Code.
MODULUS-An integer which describes certain arithmetic characteristics of registers,
especially counters and accumulators, within a digital computer. The modulus of a
device is defined by rn for an open-ended device and rn-1 for a closed (end-around)
device, where r is the base of the number system used and n is the number of digit
positions (stages) in the device. Generally, devices with modulus rn use two's complement arithmetic; devices with modulus rn-1 use one's complement.
3
NORMALIZE-To adjust the exponent and mantissa ofa floating point result so that
the mantissa lies in the prescribed standard (normal) range.
NORMAL JUMP-An i~struction that jumps from one sequence of instructions to a
second, and makes no preparation for returning to the first sequence. Also referred
to as an Unconditional Jump.
NUMERIC CODING- A system of abbreviation in which all information is reduced to
numerical quantities. Also called Absolute or Machine Language coding.
OBJECT PROGRAM-The machine language version of the source program.
ONE'S COMPLEMENT- With reference to a binary number, that number which
results from subtracting each bit of a given number from "1". The one's complement
of a number is formed by complementing each bit of it individually, that is, changing
a "I" to "0" and a "0" to a "I". A negative number is expressed by the one's complement of the corresponding positive number.
ON-LINE OPERATION-A type of system application in which the input or output
data to or from the system is fed directly from or to the external equipment.
OPERAND- Usually refers to the quantity specified by the execution address.
OPERATION CODE (Function Code)-A 6-bit quantity in an instruction specifying
the operation to be performed.
OPERATIONAL REGISTERS- Registers which are displayed on the operator's section of the console.
OR FUNCTION - A logical function in Boolean algebra that is satisfied (has the value
"1") when any of its terms are "1". It is not satisfied when all terms are "0". Often
called the inclusive OR function.
OVERFLOW - The capacity of a register is exceeded.
PARAMETER-An operand used by a program or subroutine.
PARITY CHECK-A summation check in which the binary digits in a character are
added and the sum checked against a previously computed parity digit; i.e., a check
which tests whether the number of ones is odd or even.
P REGISTER- The Program Address Counter (P register) is a one's complement
additive register (modulus 215 _1) which defines the storage addresses containing the
individual program steps.
PROGRAM-A precise sequence of instructions that accomplishes the solution of a
problem. Also called a routine.
PSEUDO CODE - A statement requesting a specific operation by the assembler or compiler.
Q REGISTER-Auxiliary 24-bit arithmetic register which assists the A register in the
more complicated arithmetic operations.
RADIX- The number of different digits that can occur in a digit position for a specific
number system. It may be referred to as the base of a number system.
RANDOM ACCESS-Access to storage under conditions in which the next position from
which information is to be obtained can be independent of the previous one.
READ - To remove a quantity from a storage location.
REGISTER-The internal logic used for temporary storage or for holding a quantity
during computation.
REJECT - A signal generated under certain circumstances by either the external equipment or the processor during the execution of Input/Output instructions.
4
REPLACE - When used in the title of an instruction, the result of the execution of the
instruction is stored in the location from which the initial operand was obtained.
When replace is used in the description of an instruction, the contents of a location
or register are substituted by the operand. The Replace operation implies clearing the
register or portion of the register in preparation for the new quantity.
REPL Y - A response signal in I/O operations that indicates a positive response to some
previous operation or request signal.
RETURN JUMP - An instruction that jumps from a sequence of instructions to initiate
a second sequence and prepares for continuing the first sequence after the second is
completed.
ROUTINE - The sequence of operations which the
program.
compu~er
performs, also called a
SCALE FACTOR - One or more coefficients by which quantities are multiplied or
divided so that they lie in a given range of magnitude.
S REGISTER-The 13-bit S register displays the address of the word.
SHIFT - To move the bits of a quantity right or left.
SIGN BIT - In registers where a quantity is treated as signed by use of one's complement notation, the bit in the highest order stage of the register. If the bit is "1", the
quantity is negative; if the bit is "0", the quantity is positive.
SIGN EXTENSION - The duplication of the sign bit in the higher order stages of a
register.
SOFTW ARE - Programs and/or subroutines.
SOURCE LANGUAGE-The language used by the programmer to define his program.
STAGE - The FFs and inverters associated with a bit position of a register.
STATUS-The state or condition of circuits within the processor, I/O channels, or
external equipment.
STORE - To transmit information to a device from which the unaltered information can
later be obtained. The Store operation is essentially the reverse of the Load operation. Storage location M is cleared, and the contents of the register are copied into M.
SUBROUTINE - A set of instructions that is used at more than one point in program
operation.
SYMBOLIC CODING-A system of abbreviation used in preparing information for
input into a computer; e.g., Shift Q would be SHQ.
TOGGLE-To complement each specified bit of a quantity, i,e.: "I" to "0" or "0" to "I".
TRANSMIT (Transfer) - The term transfer implies register contents are moved; i.e.,
the contents of register 1 are copied into register 2. Unless specifically stated, the
contents are not changed during transmission. The term transmit is often used
synonymously with transfer.
TWO'S COMPLEMENT-Number that results from subtracting each bit of a number
from "0". The two's complement may be formed by complementing each bit of the
given number and then adding one to the result, performing the required carries.
UNDERFLOW -An illegal change of sign from - to +, e.g., subtracting from a quantity
such that the result would be less than - (2n-l), where n is the modulus. In floating
point notation, this occurs where the value of the exponent becomes less than
2 -10
+ 1 (- 17778).
5
WORD - The content of a storage location. It can be an instruction or 24 bits of data.
WRITE - To enter a quantity into a storage location.
X REGISTER - An arithmetic transfer register. Nonaddressable and nondisplayed.
Z REGISTER - A 28-bit storage data register. Receives the data and parity bits as
they are read from storage or written into storage. Nonaddressable but displayed
on the 'T' panel in the storage module.
6
TABLE 1. OCTAL LISTING OF INSTRUCTIONS
OCTAL
OPERATION
CODE
MNEMONIC
CODE
PAGE
NO.
INSTRUCTION DESCRIPTION
ADDRESS
FIELD
00.0
HLT
in
Unconditional stop. RN I @ m upon restarting
7-30
00.1
SJl
m
7-31
00.2
SJ2
m
If jump key 1 is set. jump to m
If jump key 2 is set. jump to m
00.3
SJ3
m
If jump key 3 is set. jump to m
7-31
00.4
SJ4
m
If jump key 4 is set. jump to m
7-31
00.5
SJ5
m
If jump key 5 is set. jump to m
7-31
00.6
SJ6
m
If jump key 6 is set. jump to m
7-31
00.7
RTJ
m
7-32
01
UJP.I
m.b
No operation (see 14.0)
P + 1 ----t m (address portion). RN I @ m + 1. return
to m for P + 1
Unconditional jump to m
02.0
02.1-3
7-31
7-32
IJI
m.b
02.4-7
IJD
m.b
03.0
AZJ.EQ
m
If (Sb) = O. RNI @ P + 1; if (Sb) ~ O. (Sb) - 1 ----t S~
RNI @ m
If (Sb) = O. RNI @ P + 1; if (Sb) r!= O. (Sb) - 1 ----t B~
RNI @ m
If (A) = O. RNI @ m. otherwise RNI @ P + 1
03.1
AZJ.NE
m
If (A) ~ O. RNI @ m. otherwise RNI @ P + 1
7-35
03.2
AZJ.GE
m
If (A) ~ O. RNI @ m. otherwise RNI @ P + 1
7-35
03.3
AZJ.LT
m
If (A)
If (A) = (0). RNI @ m. otherwise RNI @, P + 1
7-36
If (A) ~ (0). RNI @ m. otherwise RNI @, P + 1
7-36
7-36
< O.
RNI @ m. otherwise RNI @ P + 1
7-33
7-34
7-35
7-35
03.4
03.5
AOJ.EO
AOJ.NE
m
m
03.6
AQJ.GE
m
If (A) ~ (0). RNI @ m. otherwise RNI @ P + 1
03.7
AOJ.LT
m
If (A)
RNI @ m. otherwise RNI @ P + 1
7-36
04.0
ISE
7-13
04.1-3
ISE
Y
y.b
If y = O. RNI @ P + 2. otherwise RNI @ P +1
04.4
ASE.S
y
04.5
QSE.S
y
04.6
ASE
y
04.7
OSE
y
05.0
ISG
< (0).
If y =
(8\ RNI
@
P + 2. otherwise RNI
@ P+ 1
If y = (AL RNI @ P + 2. otherwise RNI @ P + 1.
Sign of y is extended
If y = (Q). RNI @ P + 2. otherwise RNI @ P + 1.
Sign of y is extended
If y = (A). RNI @ P + 2. otherwise RNI @ P + 1.
Lower 15 bits of A are used
Ify=(Q). RNI @ P+2. otherwise RNI @ P+1.
Lower 15 bits of Q are used
If y
~
O. RNI @ P + 2. otherwise RNI @ P + 1
05.1-3
ISG
Y
y.b
05.4
ASG.S
y
If (A) ~ y. RNI @ P + 2. otherwise RNI @ P + 1.
y
Sign of y is extended
If (Q) ~ y. RNI @ P + 2. otherwise RNI @ P + 1.
05.5
OSG.S
05.6
ASG
05.7
QSG
y
y
06.0-7
MEQ
m.i
07.0-7
MTH
m.i
1.0.0
SSH
m
10.1-3
lSI
y.b
(B
b
)
~ y. RNI @ P + 2. otherwise RNI @ P + 1
7-13
7-13
7-13
7-13
7-13
7-14
7 -14
7-14
7-14
Sign of y is extended
If (A) ~ y. RNI @ P + 2. otherwise RNI @ P + 1
7-14
If (Q) ~ y. RNI @ P + 2. otherwise RNI @ P + 1
7-14
(S') - i ----t S'; if (S') negative. RNI @ P + 1; if (B1)
positive. test (A) = (0) A. (M). if true RNI @ P + 2;
if false. repeat sequence
(B2) - i ----t S2; if (8 2) negative. RNI @ P + 1; if (S2)
positive. test (A) ~ (0) A. (M). if true. RNI @ P + 2;
if false. repeat sequence
Test sign of (m). shift (m) left one place end around
and replace in storage. If sign negative. RNI @ P
2:
otherwise RNI @ P + 1
If (Sb) = y. clear Sb and RNI @ P + 2; if (Sb) ~ y.
(8 b)
1 ----t 8 b. RN I @ P
1
7-54
7-55
+
+
+
7
7-50
7-19
TABLE 1. OCTAL LISTING OF INSTRUCTIONS (CONTINUED)
OCTAL
OPERATION
CODE
10.4-7
MNEMONIC
CODE
ADDRESS
FIELD
ISO
y,b
NO.
b
If lB )
(B ) -
11.0
11.4
12.0-3
ECHA
ECHA,S
SHA
z
z
y,b
12.4-7
SHO
y,b
13.0-3
SHAQ
y,b
13.4-7
SCAQ
y,b
14.0
14.1-3
14.4
14.5
14.6
14.7
15.0
15.1-3
15.4
15.5
No operation
ENI
ENA.S
ENO,S
ENA
ENQ
No operation
INI
15.6
15.7
16.0
16.1-3
16.4
16.5
16.6
16.7
17.0
17.1-3
17.4
INA
INQ
No operation
XOI
XOA.S
XOQ,S
XOA
XOQ
No operation
ANI
ANA.S
ANQ,S
17.5
17.6
17.7
20
21
22
23
24
INA.S
INQ,S
ANA
ANO
LOA,I
LOQ,I
LACH
LQCH
LCA,I
y,b
y
y
y
Y
y,b
y
PAGE
INSTRUCTION DESCRIPTION
=
y, clear Bb and RNI @ P
1 ~ Bb and RNI @ P
1
+
+ 2;
b
if (B ) ¢ y,
z ~ A. lower 17 bits of A are used
z ~ A, sign of z extended
b
Shift (A). Shift count K = k
(B ) (signs of k and Bb
extended). If bit 23 of K = "1 ", shift right; complement of lower 6 bits equal shift magnitude. If
bit 23 of K = "0", shift left and lower 6 bits equal
shift magnitude. Left shifts end around; right shifts
end off
b
Shift (0). Shift count K = k
(B ) (signs of k and Bb
extended). If bit 23 of K = "1 ", shift right; complement of lower 6 bits equal shift magnitude. If
bit 23 of K = "0", shift left; lower 6 bits equal shift
magnitude. Left shifts end around; right shifts end off
b
Shift (AQ) as one register. Shift count K = k
(B )
(signs of k and Bb extended). If bit 23 of K = "1 ",
shift right; complement of lower 6 bits equal shift
magnitude. If bit 23 of K = "0", shift left; lower 6
bits equal shift magnitude. Left shifts end around;
right shifts end off
Shift (AQ) left end around until upper 2 bits of A are
unequal. Residue K = k - shift count. If b = 1, 2,
or 3, K ~ Bb; if b = 0, K is discarded
No operation (COMPASS assembled NOP)
Clea r B b, enter y
+
+
+
Clear
Clear
Clear
Clear
A.
Q,
A.
0,
enter
enter
enter
enter
y, sign extended
y, sign extended
y
y
b
7-19
7-15
7-15
7-50
7-52
7-52
7-52
7-15
7-15
7-15
7-15
7-15
Y
Increase (B ) by y, signs of y and Bb are extended
Increase (A) by y, sign extended
Increase (Q) by y, sign extended
7-16
7-16
7-16
Y
Y
Increase (A) by y
Increase (Q) by Y
7-16
7-16
y,b
y
y
y V
y V
y V
y V
Y
y
y
y,b
y
Y
y
Y
m,b
m,b
r,1
r,2
m,b
V (Bb)~Bb
(A) ~ A.
(Q) ~ Q.
(A) ~ A,
(Q) ~ Q,
Sign of
Sign of
no sign
no sign
y extended
y extended
extension
extension
A (B b) ~ Bb
y A (A) ~ A, sign of y extended
Y A (Q) ~ Q, sign of y extended
y
y /\ (A) ~ A. no sign extension
Y /\ (Q) ~ Q, no sign extension
(M)~A
(M)~Q
(R) ~ A. Load lower 6 bits of A
(R) ~ O. Load lower 6 bits of 0
(M)~A
8
7-17
7-17
7-17
7-17
7-17
7-18
7-18
7-18
7-18
7-18
7-20
7-22
7-20
7-22
7-21
TABLE 1. OCTAL LISTING OF INSTRUCTIONS (CONTINUED)
OCTAL
OPERATION
CODE
MNEMONIC
CODE
INSTRUCTION DESCRIPTION
ADDRESS
FIELD
(M)~A,
(M +
l)~Q
25
26
27
30
31
32
33
34
35
LOU
ADA,I
SBA,I
AOAQ,I
SBAQ,I
m,b
m,b
m,b
m,b
m,b
m,b
m,b
RAO,I
SSA,I
m,b
m,b
36
SCA,I
m,b
37
40
41
42
43
44
45
46
47
50
LPA,I
STA,I
STQ,I
SACH
SQCH
SWA,I
STAQ,I
SCHA,I
STI,I
MUA,I
m,b
m,b
m,b
r,2
51
52
DVA,I
m,b
R
R
~ (MOO-14)
(AQ)~(M,M + 1)
(AOO-16) ~ (MOO-16)
b
(B ) ~ (MOO-14)
Multiply (A) by (M) ~QA. Lowest order bits of
product in A
(A) +- (M) ~ A, remainder ~ Q
CPRI
m,b
(M)
53.1-3
53.40-70
53.01
53.41
53.02
53.42
53.(0+b)3
LDAQ,I
LCAQ,I
r,1
m,b
m,b
m,b
m,b
m,b
TIA
TAl
TMQ
TQM
TMA
TAM
TMI
b
b
v
v
v
v
v,b
53.(4+b)3 TIM
AQA
53.04
53.(0+b)4 AlA
53.(4+b)4 IAI
v,b
54
55.0
55.1
55.2
55.3
55.4
55.5
55.6
55.7
LOLl
No operation
ELQ
EUA
EAQ
No operation
QEL
AEU
AQE
b
b
m,b
(Ivi)~A, (M + 1)~Q
(M) A (Q)~A
Add (M) to (A)~A
(A) minus (M) ~ A
Add (M,M + 1) to (AQ) ~ AQ
(AQ) minus (M,M + 1) ~ AQ
Add (M) to (A) ~ (M)
Where (M) contains a "1" bit, set the corresponding
bit in A to "1"
Where (M) contains a "1" bit, complement the corresponding bit in A
(M) 1\ (A) ~A
(A)~(M)
(Q)~(M)
(AOO-05)
(QOO-05)
(AOO-14)
~
~
+
> (A), RNI @ P 1
}
(Q) > (M), RNI @ P + 2
(A) ~ (M) ~ (Q), RNI @ P + 3
b
Clear (A).(B ) ~ AOO-14
(AOO-14) ~ Bb
7-21
7-21
7-21
7-38
7-39
7-40
7-40
7-38
7-37
7-37
7-37
7-23
7-24
7-23
7-24
7-25
7-24
7-25
7-25
7-39
7-39
(AI and (Q)
7-53
are unchanged
(v)~Q
(Q)~v
(v)~A
(A)~v
(VOO-14) ~ Bb
b
(B ) ---tVOO-14
Add (A) to (Q) ~ A
b
Add (A) to (B ) ~ A
b
Add (A) to (B ) ~ Bb. Sign of Bb extended prior to
addition
All other combinations of 53.00-77 are undefined
and will be rejected by the assembler
(MOO-14) ~ Bb
(ELl~Q
PAGE
NO.
7-27
7-27
7-27
7-27
7-28
7-28
7-28
7-28
7-26
7-26
7-26
7-22
(EUEL)~AQ
7-29
7-29
7-29
(Q)~EL
7-29
(A)~EU
7-29
7-29
(EU)~A
(AQ)~
EUEL
9
TABLE 1. OCTAL LISTING OF INSTRUCTIONS (CONTINUED)
OCTAL
OPERATION
CODE
MNEMONIC
CODE
ADDRESS
FIELD
56
57
MUAQ,I
DVAQ
m,b
m,b
60
61
62
FAD.I
FSB,I
FMU.I
m,b
m,b
m,b
INSTRUCTION DESCRIPTION
+
MUltiply (AQ) by (M.M
1) ~ AQE
(AQE) -;- (M,M
1) ~ AQ and remainder with sign
extended to E. Divide fault halts operation and program advances to next instruction
Floating point addition of (M,M
1) to (AQ) ~ AQ
Floating point subtraction of(M,M 1) from (AQ)~AQ
Floating point multiplication of (AQ) and (M.M
1)
+
+
+
+
~AQ
63
FDV,I
m,b
64
LDE
r.1
PAGE
NO.
+
Floating point division of (AQ) by (M.M
1) ~ AQ,
remainder with sign extended to E
Load E with up to 12 numeric BCD characters from
storage. BCD field length is specified by (D). Characters are read consecutively from least significant
character at address (R
(D) - 1) until the most
si.gnificant character at address R is in E. (E) is shifted
right as loading progresses. The sign of the field is
acquired along with the least significant character
Store up to 13 numeric BCD characters from E. Least
significant character is stored at R
(D) - 1 continuing back to most significant character stored in R
Up to twelve 4-bit characters (most significant character at address R) are added to (E). Sum appears in
E. (D) register specifies field length
Up to twelve 4-bit characters (most significant character at address R) are subtracted from (E). Difference
appears in E. (D) specifies field length
Shift E in one character (4 bit) steps. Left shift: bit
23 = "0", magnitude of shift = lower 4 bits of K = k
b
(B ). Right shift: bit 23 = "1", magnitude of shift
= lower 4 bits of complement of K = k (B b )
(E) = O. jump to m; (E) rf= 0, RNI @ P
1
(E) < 0, jump to m; (E) ~ 0, RNI @ P
1
7-42
7-42
7-43
7-44
7-44
7-44
+
65
STE
r,2
66
ADE
r,3
67
SBE
r,3
70.0-3
SFE
y.b
+
+
+
+
+
70.4
70.5
70.6
70.7
71 ***
EZJ,EQ
EZJ,LT
EOJ
SET
SRCE,INT
m
m
m
y
c.r,s
71 ****
SRCN.INT
c.r,s
72
73.0**
MOVE,fNT
INPC,INT,
B,H
INAC.INT
c.r,s
ch,r,s
74.0**
INPW.INT,
B.N
ch,m,n
74.1*
INAW.INT
ch
75.0**
OUTC.INT.
B,H
ch,r,s
75.1*
OTAC,INT
ch
Character from lower 6 bits of A is sent to a peripheral
device, (A) retained
76.0**
OUTW.INT
B.N
ch.m,n
Words read from storage to a peripheral device
73.1~*
ch
*7 -bit operation code. bit 17 = "1 "
**7 -bit operation code. bit 17 = "0"
7-48
+
Jump to m if E overflows, otherwise RNI @ P
1
Set (D) with lower 4 bits of y
SeCM'ch for equality of character c in a list bEfginning
at location r until an equal character is found, or until
character lo~ation s is reached; 0 ~ c ~ 6310
Same as SRCE except search condition is for inequality
Move c characters from r to s; 1 ~ c ~ 12810
A 6- or 12-bit character is read from peripheral device
and stored in memory at a given location
(A) is cleared and a 6-bit character is transferred from
a peripheral device to the lower 6 bits ot'A
Word address is placed in bits 00-14. 12- or 24-btt
words are read from a peripheral device and stored
in memory
(A) is cleared and a 12- or 24-bit word is read from a
peripheral device into the lower 12 bits or all of A
(word size depends on 110 channel)
Storage words disassembled into 6- or 12-bit characters
and sent to a peripheral device
10
H*7 -bit operation code. bit 17 in P
****7 -bit operation code. bit 17 in P
7-48
7-47
7-47
7-49
7-49
7 .. 49
7-49
7-46
7-56
7-56
7-58
7-72
7-80
7-74
7-82
7-76
7-84
7-78
+1=
+,=
"0"
"'"
TABLE 1. OCTAL LISTING OF INSTRUCTIONS (CONTINUED)
OCTAL
OPERATION
CODE
MNEMONIC
CODE
76.1 ***
OTAW,INT
ch
Word from lower 12 bits or all of A (depending on
type of liD channel) sent to a peripheral device
77.0
CON
x,ch
77.1
SEL
x,ch
77.2
EXS
x,ch
If channel ch is busy, reject instruction, RNI @ P + 1
If channel ch is not busy, 12-bit connect code sent on
channel ch with connect enable, RNI @ P + 2
If channel ch is busy, read reject instruction from
P + 1. If channel ch is not busy, a 12-bit function
code is sent on channel ch with a function enable,
RNI @ P+4
Sense external status if "1" bits occur on status lines
in any of the same positions as "1" bits in the mask,
RNI @ P + 1. If no comparison. RNI @ P + 2
77.2
COpy
ch
77.3
INS
x,ch
77.3
77.4
CINS
ch
x,ch
77.50
77.51
INCl
10Cl
INTS
ADDRESS
FIELD
x
x
77.52
SSIM
x
77.53
SCIM
x
77.54-56
77.57
No operation
IAPR
77.6
PAUS
x
PAGE
NO.
INSTRUCTION DESCRIPTION
7 -86
7-70
7-70
7-60
External status code from liD channel ch ~ lower
12 bits of A, contents of interrupt mask register ~
upper 12 bits of A; RNI @ P + 1
Sense internal status if "1" bits occur on status lines
in any of the same positions as "1" bits in the mask,
RNI @ P + 1. If no comparison, RNI @ P + 2
Interrupt mask and internal status to A
7-60
7-62
7-62
Sense for interrupt condition; if "1" bits occur simultaneously in interrupt lines and in the interrupt mask,
RNI @ P + 1; if not, RNI @ P + 2
Interrupt faults defined by x are cleared
Clears I/O channel or search/move control as defined
by bits 00-07, 08 and 11 of x.
7-63
Selectively set interrupt mask register for each "1"
bit in x. The corresponding bit in the mask register
is set to "1"
Selectively clear interrupt mask register for each "1"
bit in x. The corresponding bit in the mask register
is set to "0"
7-66
7-66
Interrupt associated processor
Sense busy lines. If" 1 " appears on a line corresponding to "1" bits in x, do not advance P. If P is inhibited
7-66
for longer than 40 ms, read reject instruction from
P + 1. If no comparison, RNI @ P + 2
Program stops if Selective Stop switch is on; upon
restarting, RNI @ P+1
Set floating point fault logic
Set BCD fault logic
Disables interrupt control
Interrupt control is enabled, allows one more instruction to be executed before interrupt
77.70
SlS
77.71
77.72
77.73
SFPF
SBCD
DINT
77.74
EINT
77.75
CTI
Set Type In }
77.76
eTO
Set Type Out
77.77
UCS
Unconditional stop.
11
Beginning character address must be
present in location 23 of register file
and last character
address + 1 must be preset in location 33 of the file
Upon restarting, RNI @ P + 1
7-64
i
7-31
7 -67
7 -67
7 -67
7-67
7-71
7 -31
TABLE 2. ALPHAMNEMONIC LISTING OF INSTRUCTIONS
MNEMONIC
CODE
ADA,I
ADAQ,I
OCTAL
OPERATION
CODE
ADDRESS
FIELD
m,b
m,b
r,3
·ADE
30
32
66
AEU
AlA
ANA
ANA.S
ANI
ANQ
ANQ,S
AQA
AQE
AQJ,EQ
AQJ,GE
AQJ,LT
AQJ,NE
ASE
55.6
53.(0+b)4
17.6
17.4
17.1-3
17.7
17.5
53.04
55.7
03.4
03.6
03.7
03.5
04.6
ASE.S
04.4
y
ASG
ASG,S
05.6
05.4
y
y
AZJ,EQ
AZJ,GE
AZJ,LT
AZJ,NE
CINS
CON
03.0
03.2
03.3
03.1
77.3
77.0
m
m
m
m
ch
x,ch
COpy
77.2
ch
CPR.I
52
m,b
CTI
77.75
CTO
DINT
DVA,I
DVAQ
77.76
77.73
EAQ
ECHA
ECHA.S
EINT
55.3
11.0
11.4
77.74
51
57
INSTRUCTION DESCRIPTION
Add (M) to
(A)~A
Add (M,M +
7-38
7-40
1) to (AQ)~AQ
Up to twelve 4-bit characters (most significant character at address R) is added to (E). Sum appears in E.
(D) specifies field length
(A)~EU
b
y
y
y,b
y
y
Add (A) to (Sb) ~ A
y /\ (A) ~ A. no sign extension
y /\ (A) ~ A, sign of y extended
y /\ (B b) ~ Bb
y /\ (Q) ~ Q, no sign extension
y /\ (Q) ~ Q, sign of y extended
Add (A) to (Q) ~ A
(AQ)~EUEL
m
m
m
m
y
If (A) = (Q). RNI @ m, otherwise RNI @ P + 1
If (A) 2 (Q). RNI @ m, otherwise RNI @ P + 1
If (A) < (Q). RNI @ m, otherwise RNI @ P + 1
If (A) ~ (Q), RNI @ m, otherwise RNI @ P + 1
If y = (A). RNI @ P + 2, otherwise RNI @ P + 1
lower 15 bits of A are used
If y = (A). RNI @ P + 2, otherwise RNI @ P+ 1
Sign of y is extended.
If (A) 2 y, RNI @ P + 2, otherwise RNI @ P+ 1
If (A) 2 y, RNI @ P + 2, otherwise RNI @ P+ 1
Sign of y is extended
If (A) = 0, RNI @ m, otherwise RNI @ P + 1
If (A) 2 0, RNI @ m, otherwise RNI @ P + 1
If (A) < 0, RNI @ m, otherwise RNI @ P + 1
If (A) ~ 0, RNI @ m, otherwise RNI @ P + 1
I nterrupt mask and internal status to A
If channel ch is busy, reject instruction, RNI @ P + 1
If channel ch is not busy, 12-bit connect code sent on
channel ch with connect enable, RNI @ P + 2
External status code from I/O channel ch to lower
12-bits of A. contents of interrupt mask register to
upper 12-bits of A. RNI @ P + 1
+
(M) > (Aj, RNI @ P
1
}
(Q) > (M). RNI @ P + 2
(A) ~ (M) ~ (Q). RNI @ P + 3
PAGE
NO.
(A) and (Q)
are unchanged
7-13
7-13
7-14
7-14
7-35
7-35
7-35
7-35
7-62
7-70
7-60
7-53
Set Type In }
m,b
m,b
Beginning character address must be
preset in location 23 of register file
and last character address + 1 must
Set Type Out be preset in location 33 of the file
Disables interrupt .control
(A) -;- (M)~A. remainder ~ Q
(AQE) +(M,M + 1) ~ AQ and remainder with sign
ex.tended to E. Divide fault halts operation and program advances to next instruction
7-47
7-29
7-26
7-18
7-18
7-18
7-18
7-18
7-26
7-29
7-36
7-36
7-36
7-36
(EUEU~AQ
z
z
z ~ A. lower 17 bits of A are used
z ~ A, sign of z extended
Interrupt control is enabled. Allows one more instruction to be executed before interrupt
12
7-71
7-67
7-39
7-42
7-29
7-15
7-15
7-67
TABLE 2. ALPHAMNEMONIC LISTING OF INSTRUCTIONS (CONTINUED)
MNEMONIC
CODE
OCTAL
OPERATION
CODE
INSTRUCTION DESCRIPTION
PAGE
NO.
(Ell ~ Q
Clear A. enter y
Clear A. enter y. sign extended
b
Clear B , enter y
Clear Q. enter y
Clear Q. enter y. sign extended
Jump to m if E overflows. otherwise RNI @ P + 1
7-29
7-15
7-15
7-15
7-15
7-15
7-49
7-29
ADDRESS
FIELD
ElQ
55.1
ENA
ENA.S
ENI
ENQ
ENQ.S
EdJ
EUA
EXS
14.6 I
14.4
14.1-3
14.7
14.5
70.6
55.2
77.2
Y
Y
y.b
y
y
EZJ.EQ
EZJ.lT
FAD.I
FDV.I
70.4
70.5
60
63
m
m
m.b
m.b
FMU.I
62
m.b
m
(EU)~A
Sense external status if "1" bits occur on status lines
in any of the same positions as "1" bits in the mask.
RNI @ P + 1. If no comparison. RNI @ P + 2
(E) = O. jump to m; (E) ~ O. RNI @ P + 1
(E) < O. jump to m; (E) ~ O. RNI @ P + 1
Floating point addition of (M.M + 1) to (AO) ~ AQ
Floating point division of (AO) by (M.M + 1) ~ AQ
Remainder with sign extended to E
Floating point multiplication of (AO) and (M,M + 1)
x.ch
7-60
7-49
7-49
7-43
7-44
~AQ
FSB.I
HlT
IAI
61
00.0
53.(4+b)4
IAPR
IJD
77.57
02.4-7
m.b
IJI
02.1-3
m.b
INA
INA.S
INAC.INT
15.6
15.4
73 *
y
y
ch
INAW.INT
74 *
ch
77.50
15.1-3
INPC.INT.S.H 73 **
x
y.b
INPW.INT.S.N 74.0**
ch.m.n
INCl
INI
INO.S
INS
y
y
x.ch
INTS
77.4
c.ch
10Cl
77.51
7-26
7-66
7-34
7-33
7-16
7-16
7-80
7-82
7-65
7-16
A 6- or 12-bit character is read from a peripheral
device and stored in memory at a given location
Word Address is placed in bits 00-14, 12- or 24-bit
words are read from a peripheral device and stored
in memory
Increase (Q) by y
Increase (0) by y. sign of y is extended
Sense internal status if "1 .. bits occur on status lines
in any of the same positions as "1" bits in the mask.
RNI @ P + 1. If no comparison. RNI @ P + 2
Sense for interrupt condition; if "1" bits occur simultaneously in interrupt lines and in the interrupt mask.
RNI @ P + 1; if not. RNI @ P + 2
ch.r.s
15.7
15.5
77.3
INQ
7-44
7-44
7-30
Floating point subtraction of (M.M + 1) from (AO)~AO
Unconditional stop. RNI @ m upon restarting
Add (A) to (B b) ~ Bb. Sign of Bb extended prior to
addition
Interrupt associated processor
If (B b) = O. RNI @ P + 1; if (Sb) ~ O. (Sb) - 1 ~ Sb.
RNI @ m
If (Sb) = O. RNI @ P + 1; if (Sb) ~ O. (Sb) + 1 ~ Sb.
RNI @ m
Increase (A) by y
Increase (A) by y. sign of y is extended
(A) is cleared and a 6-bit character is transferred from
a peripheral device to the lower 6 bits of A
(A) is cleared and a 12- or 24-bit word is read from
a peripheral device into the lower 12 bits or all of A
(word size depends on I/O channel)
Interrupt faults defined by x are cleared
Increase (Sb) by y. signs of y and Sb are extended
m.b
m
b
x
7-72
7-74
7-16
7-16
7-62
7-61
Clears I/O channel or search/move control as defined
by bi.ts 00-07, 08, and 11 of x.
7-63
I
* 7 -bit operation code. bit 17 in P
**7-bit operation code. bit 17 in P
=
=
"1 "
"0"
13
TABLE 2. ALPHAMNEMONIC LISTING OF INSTRUCTIONS (CONTINUED)
MNEMONIC
CODE
OCTAL
OPERATION
CODE
ADDRESS
FIELD
ISO
10.4-7
y.b
ISE
ISE
ISG
ISG
04.0
04.1-3
05.0
05.1-3
y
y,b
lSI
10.1-3
y,b
LACH
LCA,I
LCAQ,I
22
r.
m,b
m,b
LOA.I
LDAQ.I
LOE
y
y,b
24
26
20
25
64
m.b
m,b
r.1
PAGE
NO.
INSTRUCTION DESCRIPTION
If lBb) =y. clear Bb and RNI @ P + 2; if (Bb)~y,
(B )-1~B\RNI @ P
1
If y = O. RNI @ P + 2, otherwise RNI @ P + 1
b
If y=(B ), RNI @ P + 2, otherwise RNI @ P + 1
If y ~ 0, RNI @ P + 2, otherwise RNI @ P
1
b
If (B ) ~ y, RNI @ P
2, otherwise RNI @ P
1
b
b
If (B ) = y. clear Bb and RNI @ P
2; if (B ) ~ y,
b
(B )
1 ~ Bb. RNI @ P
1
(R) ~ A; load lower 6 bits of A
+
+
+
+
+
+
+
(M)~A
(M) ~ A, ("lVI=FT) ~ Q
(M)~A
+
(M)~A,
(M
1)~Q
Load E with up to 12 numeric BCD characters from
storage. BCD field length is specified by (D) register.
Characters are read consecutively from least significant character at address (R
(D) -1) until the most
significant character at address M is in E. (E) is shifted
right as loading progresses. The sign of the field is
acquired along with the least significant character
(MOO-14) ~ Bb
7-19
7-13
7-13
7-14
7-14
7-19
7-20
7-21
7-21
7-20
7-21
+
LOU
LOL,I
LOQ,I
LPA,I
LQCH
MEQ
23
06.0-7
m.b
m,b
m,b
m,b
r,2
m,i
MOVE,INT
MTH
72
07.0-7
c,r.s
m.i
54
27
21
37
(M) " (Q) - t A
(M)~Q
(M) 1\ (A)
~A
(R) ~ Q; load lower 6 bits of Q
(B') - i ~ B'; if (B') negative, RNI @ P + 1; if (B')
positive. test (A) = (Q) 1\ (M); if true. RNI @ P + 2.
if false, repeat sequence
Move c characters from r to s; I S c S 128,0
(B2) - i ~ B2; if (B2) negative, RNI @ P
1; if (B2)
positive, test (A) ~ (Q) " (M); if true, RNI @ P
2;
if false, repeat sequence
Multiply (A) by (M) ~ QA; lowest order bits of product in A
Multiply (AQ) by (M,M
1) ~ AQE
Character from lower 6 bits of A is sent to peripheral
device, (A) retained
+
50
m.b
MUAQ,I
OTAC,INT
56
75*
m,b
ch
OTAW,INT
76*
ch
OUTC,
INT,B,H
OUTW,
INT,B,H
75
76 **
ch,m,n
Words read from storage to peripheral device
PAUS
77.6
x
Sense busy lines. If" 1" appears on a line corresponding to "1" bits in x, do not advance P. If P is inhibited
for longer than 40 ms, read reject instruction from
P
1. If no comparison, RNI @ P
2
QEL
QSE
55.5
04.7
y
QSE,$
04.5
y
QSG
05.7
y
ch,r,s
+
Word from lower 12 bits or all of A (depending on
type of I/O channel) sent to a peripheral device
Storage words disassembled into 6 or 12-bit characters
and sent to a peripheral device
+
* 7 -bit operation code, bit 17
+
(Q)~EL
=
"1 "
If Y = (Q), RNI @ P + 2, otherwise RNI @P+1;
lower 15 bits of Q are used
If y = (Q), RNI @ P + 2, otherwise RNI @ P
1
Sign of y is extended
If (Q) ~ y, RNI @ P
2. otherwise RNI @ P + 1
+
+
14
7-21
7-22
7-37
7-22
7-54
7-58
+
MUA,I
**
7-48
7-22
7-55
7-39
7-42
7-84
7-86
7-76
7-78
7-64
7-29
7-13
7-13
7-14
**7 -bit operation code, bit 17
=
"0"
TABLE 2. ALPHAMNEMONIC LISTING OF INSTRUCTIONS (CONTINUED)
MNEMONIC
CODE
OCTAL
OPERATION
CODE
ADDRESS
FIELD
OSG,S
05.5
y
RAD,I
34
m,b
RTJ
00.7
m
SACH
42
r,2
SBA,I
31
SBAO,I
SBCD
33
77.72
m,b
m,b
SBE
67
r,3
SCA,I
36
SCAD
13.4-7
INSTRUCTION DESCRIPTION
PAGE
NO.
If (0) ~ y, RNI @ P + 2, otherwise RNI @ P + 1
Sign of y is extended
Add (M) to (A) -----t (M)
7-14
P + 1 -----t M (address portion) RNI @ m +
to m for P + 1
(Aoo-os) -----t R
(A) minus (M) -----t A
(AO) minus (M, M + 1)
-----t
1, return
AO
7-32
7-23
7-39
7-40
Set BCD fault logic
Up to twelve 4-bit characters (most significant character at address m) is subtracted from E. Difference
appears in E. (D) register specifies field length.
7-47
m,b
Where (M) contains a "1" bit. complement the corresponding bit in A
7-37
y.b
Shift (AD) left end around until upper 2 bits of A are
unequal. Residue K = k-shift count. If b = 1, 2, or 3,
K -----t Bb; if b = 0, K is discarded
7-52
7-25
SCHA,I
46
m,b
(AOO-16)
SCIM
77.53
x
SEL
77.1
x,ch
SET
70.7
y
SFE
70.0-3
k,b
SFPF
77.71
SHA
12.0-3
Selectively clear Interrupt Mask Register for each
"1" bit in x. The corresponding bit in the mask register
is set to "0"
If channel ch is busy, read reject instruction from
P + 1. If channel ch is not busy, a 12-bit function
code is sent on channel ch with a function enable,
RNI@P+2
Set (D) with lower 4 bits of y
Shift (E) in one character (4-bit) steps. Left shift: bit
23 = "0", magnitude of shift = lower 4 bits of K = k
b
+ (B ). Right shift: bit 23 ="1 ", magnitude of shift=
b
lower 4 bits of complement of K = k + (B )
Set floating point fault logic
b
Shift (A). Shift count K = k + (B ) (signs of k and Bb
extended). If bit 23 of K = "1 ", shift right; complement of lower 6 bits equal shift magnitude. If bit 23
of K = "0", shift left; lower 6 bits equal shift magnitude. Left shifts end around; right shifts end off
Shift (AO) as one register. Shift count K = k + Bb
(signs of k and Bb extended). If bit 23 of K = "1 ", shift
right and complement of lower 6 bits equal shift magnitude. If bit 23 of K = "0", shift left and lower 6 bits
equal shift magnitude. Left shifts end around; right
shifts end off
Shift (O)' Shift count K = k + (Bb) (signs of k and Bb
extended). If bit 23 of K = "1 ", shift right; complement of lower 6 bits equal shift magnitude. If bit 23
of K = "0", shift left; lower 6 bits equal shift magnitude. Left shifts end around; right shifts end off
If jump key 1 is set, jump to m
If jump key 2 is set, jump to m
If jump key 3 is set. jump to m
If jump key 4 is set, jump to m
y,b
SHAO
13.0-3
y,b
SHO
12.4-7
y,b
SJ1
00.1
m
SJ2
00.2
m
SJ3
SJ4
00.3
m
00.4
00.5
m
m
00.6
m
SJ5
SJ6
7-38
-----t
(MOO-16)
If jump key 5 is set. jump to m
If jump key 6 is set, jump to m
15
7-67
7-66
7-70
7-46
7-49
7-67
7-50
7-52
7-52
7-31
7-31
7-31
7-31
7-31
7-31
TABLE 2. ALPHAMNEMONIC LISTING OF INSTRUCTIONS (CONTINUED)
MNEMONIC
CODE
OCTAL
OPERATION
CODE
ADDRESS
FIELD
INSTRUCTION DESCRIPTION
Program stops if Selective Stop switch is on; upon
restarting RNI @ P + 1
(000-05) ~ R
SLS
77.70
SOCH
SRCE,INT
43
r,1
71*
c,r,s
SRCN,INT
71**
c,r,s
SSA,I
35
m,b
SSH
10.0
m
Test sign of (m), shift (m) left one place, end around
and replace in storage. If sign negative, RN I @ P + 2;
otherwise RNI @ P + 1
SSIM
77.52
x
Selectively set interrupt mask register for each "1"
bit in x. The corresponding bit in the mask register is
set to "1 "
STA,I
40
m,b
(A)~(M)
STAQ,I
45
STE
65
m,b
r,2
STU
STQ,I
47
41
m,b
m,b
SWA,I
44
53.40-70
m,b
(AOO-14)
TAl
b
(AOO-14) ~ Bb
TAM
TIA
53.42
53.1-3
TIM
TMA
53.(4+b)3
53.02
TMI
TMQ
53.(0+b)3
53.01
TQM
Search for equality of character c in a list beginning
at location r until an equal character is found, or until
character location s is reached; 0 ::; c ::; 6310
Same as SRCE except search condition is for inequality
Where (M) contains a "1" bit, set the corresponding
bit in A to "1"
(AQ)~(M,M
+ 1)
Store up to 13 numeric BCD characters from E. Least
significant character stored at R +(0) -1 continuing
back to most significant character stored at R
b
(B ) ~ (MOO-14)
(Q)~(M)
~
(MOO-14)
v
(A)~v
b
v,b
b
Clear (A), (B ) ~ AOO-14
b
(B ) ~VOO-14
PAGE
NO.
7-31
7-24
7-56
7-56
7-37
7-50
7-66
7-23
7-24
7-48
7-25
7-24
7-25
7-27
7-28
7-27
7-28
7-28
v
v,b
(v)~A
v
(v)~Q
7-28
7-27
v
(O)~v
7-27
Unconditional stop. Upon restarting RNI @ P + 1.
XOA
53.41
77.77
01
16.6
7-31
7-32
7-17
XOA,S
XOI
16.4
16.1 -3
XOQ
XOQ,S
16.7
16.5
y
y,b
y
USC
UJP,I
(VOO-14) ~ Bb
m,b
Unconditional jump to M
y V (A) ~ A, no sign extension
y V (A) ~ A, sign of y is extended
y V (Bb)~ Bb
y
y V (Q)
y V (Q)
y
~
~
Q, no sign extension
Q, sign of y is extended
*7 -bit operation code, bit 17 in P + 1 = "0"
**7 -bit operation code, bit 17 in P
+1=
"1 "
16
7-17
7-17
7-17
7-17
TABLE 3. FUNCTION LISTING OF INSTRUCTIONS
FUNCTION
Transfers
MNEMONIC
CODE
AEUttt
AlA
ANAt
PAGE
NO.
INSTRUCTION DESCRIPTION
(A)~EU
7-29
Add (A) to (B b) ~ A
y /\ (B b) ~ Bb
7-26
7-18
7-18
ANlt
y /\ (0) ~ 0, sign of y extended
y /\ (B b) ~ Bb
ANOt
ANO,S
y A (0)----+ 0, no sign extension
y /\ (0)
Q, sign of y extended
EAOttt
ELOttt
(EU EL)~AQ
7 -18
7-18
7-29
7-29
ENA
ENA,S
7-15
ENI
Clear A, enter y
Clear A, enter y, sign extended
b
Clear 8 , enter y
ENO
ENO,S
Clear 0, enter y
Clear 0, enter y, sign extended
7-15
EUAttt
LCA,lt
(EU)~A
7-29
7-21
LCAO,lt
LDA,I
(M)~A,
LDAQ,I
(M)~A,
LDEt
Load E with up to 12 numeric BCO characters from storage.
BCD field length is specified by (0) register. Characters are read
consecutively from least significant character at address (R
(0)-1) until the most significant character at address R is in E.
(E) is shifted right as loading progresses. The sign of the fi~ld is
acquired along with the least significant character
(MOO-14) ~ Bb
ANA,S
7-18
(EL)~O
7-15
7-15
7-15
(M)~A
(M
+ 1)~0
(M
+
7-21
7-20
7-21
(M)~A
1)~0
+
LDLI
LOUt
LDO,I
LPA,lt
SSA,lt
STA,I
(M) /\ (O)~A
7-21
7-22
(M)~O
(M)/\(A)~A
Where (M) contains a "1" bit, set the corresponding bit in A to "1"
(A)~(M)
+ 1)
STAO,I
(AQ)~(M,M
STEttt
Store up to 13 numeric BCO characters from E. Least significant
character stored at R
(0)-1 continuing back to most significant character stored in R
7-37
7-37
7-23
7-24
+
b
(B ) ~ (MOO-14)
STLI
STO,I
(O)~(M)
SWA,I
(AOO-14) ~ (MOO-14)
TAl
TAM
(AOO-14) ~ Bb
TIA
TIM
TMA
7-48
7-22
7-25
7-24
7-25
7-27
7-28
(A)~v
b
Clear (A), (B ) ~ AOO-14
b
(B )
7-48
~ vOO-14
(v)~A
~ Bb
7-27
7-28
7-28
7-28
TMI
(vOO-14)
TMO
TOM
XOAt
XOA,St
XOlt
(v)~O
7-27
(O)~v
Y V (A) ~ A, no sign extension
y V (A) ~ A, sign of y is extended
y V (B b) ~ Bb
7-27
7 -17
7-17
7 -17
XOOt
y V (0) ~ 0, no sign extension
7 -17
t Requires additional operation prior to transfer.
tt Trapped Instruction if optional floating point/48-bit precision hardware is absent.
ttt Trapped Instruction if optional BCD hardware is absent.
17
TABLE 3. FUNCTION LISTING OF INSTRUCTIONS (CONTINUED)
FUNCTION
Transfers
(Continued)
Character
Operation
Arithmetic
MNEMONIC
CODE
INSTRUCTION DESCRIPTION
PAGE
NO.
XOO,St
y V (0)
MOVE,INT
Move c characters from r to s; I :::; c :::; 12810.
OEL ttt
(0)
SACH
(AOO-05)
SCA,I
Where (M) contains a "1" bit. complement the corresponding
bit in A
7-37
SETttt
Set (D) with lower 4 bits of y
7-46
ECHA
ECHA,S
Z --,> Aoo-16
7-15
LACH
(R) -----; AOO-05
7-20
LOCH
( R)
SOCH
(000-05)
--,>
(R)
7-22
7-24
--,>
(MOO-16)
--7
Z --,>
--,>
0, sign of y is extended
7-17
7-58
EL
--,>
7-29
(R)
7-23
A sign extended
--7
7-15
000-05
SCHA,I
(AoO-16)
ADAI
ADAO,I
Add (M) to (A)
ADEttt
AOA
Up to twelve 4-bit characters (most significant character at
address R) is added to (E). Sum appears in E. (D) register specifies field length
Add (A) to (0) --7 A
7-47
7-26
AOEttt
(AO)
7-29
OVAl
(A) -7- (M)
DVAOtt
(AOE) -7- (M,M
1) --7 AQ and remainder with sign extended
to E. Divide fault halts operation and program advances to next
instruction
FADtt
Floating point addition of (M,M
FDV,ltt
Floating point division of (AO) by (M,M
with sign extended to E
FMU,ltt
Floating point multiplication of (AQ) and (M,M
AQ
7-44
FSB,ltt
Floating point subtraction of (M,M
1) from (AO) --7 AQ
b
Add (A) to (B ) --7 Bb. Sign of Bb extended prior to addition
7-44
IAI
Add (M,M
--7
+ 1)
--,>
7-25
A
7-38
to (AO)
--7
AO
7-40
(EU EL)
--7
A, Remainder --,> 0
7-39
+
+ 1) to
(AQ)
+
--7
AQ
7-42
7-43
1) --7 AO, remainder
+
+
7-44
1)
--7
7-26
INA
INA,S
Increase (A) by y
7-16
Increase (A) by y, sign extended
7-16
INI
Increase (B ) by y, signs of y and Bb are extended
7-16
INO
Increase (0) by Y
7-16
INO,S
Increase (0) by y, sign extended
Multiply (M) by (A) --7 OA. Lowest order bits of product in A
7-39
MUAI
b
+
7-16
MUAO,ltt
Multiply (AO) by (M,M
RAD,I
Add (M) to (A)
SBAI
SBAO,I
(A) minus (M)
SBEttt
Up to twelve 4-bit characters (most significant character at
address R) is subtracted from E. Difference appears in E. (D)
register specifies field length
Jumps and
HLT
Unconditional stop; RN I @ m upon restarting
Stops
SJ1
If jump key 1 is set. jump to m
7-30
7-31
SJ2
If jump key 2 is set, jump to m
7-31
SJ3
SJ4
If jump key 3 is set, jump to m
7-31
If jump key 4 is set. jump to m
7-3)
SJ5
If jump key 5 is set. jump to m
If jump key 6 is set, jump to m
7-31
SJ6
--7
--7
(AQ) minus (M,M
1)
--7
AQE
(M)
A
+
18
7-42
7-38
7-30
1)
--7
AQ
7-40
7-47
7-31
TABLE 3. FUNCTION LISTING OF INSTRUCTIONS (CONTINUED)
FUNCTION
Jumps and
MNEMONIC
CODE
SLS
Stops
(Continued)
UCS
UJP,I
RTJ
PAGE
NO.
INSTRUCTION DESCRIPTION
Program stops if Selective Stop switch is on; upon restarting,
RNI Ci1 P
1
Unconditional stop. Upon restarting, RNI Ci1 P
1
7 -31
Unconditional jump to m
7-32
+
P
+
1
----->
+
+
m (address portion). RNI ~ m
1, return to m for
7-32
P+1
Decision
7-31
+
+
P +
P +
AOJ,EO
If (A) = (0). RNI ~ m, otherwise RNI ~ P
1
AOJ,GE
If (A) 2:: (0). RNI Ci1 m, otherwise RNI ~ P
1
7-36
7-36
AOJ,LT
If (A)
AOJ,NE
If (A) ¥- (0). RNI Ci1 m, otherwise RNI ~
1
1
7-36
7-36
ASE
Ify = (A). RNI Ci1 P
bits of A are used
+
2, otherwise RNI Ci1 P
ASE,S
Ify = (A). RNI Ci1 P
extended
+
2, otherwise RNI Ci1 P
ASG
If (A) 2:: y, RNI ~ P
+
2, otherwise cg P
ASG,S
If(A) 2:: y, RNI Ci1 P
of y is extended
AZJ,EO
If (A)
<
=
(0). RNI ~ m, otherwise RNI Ci1
+
+
1. Lower 15
7 -13
+
1. Sign of y is
7 -13
7 -14
1
+
2, otherwise RNI Ci1 P
0, RNI (g m, otherwise RNI (g P
~,
+
m, otherwise RNI cg P
1. Sign
+
+
1
7-14
7-35
7-35
+
1
1
7-35
7-35
1
AZJ,GE
If (A) 2:: 0, RNI
AZJ,LT
AZJ,NE
If (A) < 0, RNI @, m, otherwise RNI ~ P
If (A) ¥- 0, RN I (g, m, otherwise RN I (g P
CPR,I
(M) > (M).
(0) > (M).
(A) :::::. (M) :::::. (0)
EOJttt
Jump to m if E overflows, otherwise RNI (g P
EZJ,EOttt
(E)
EZJ,L Tt t t
0, jump to m; (E) 2:: 0, RNI ~ P + 1
b
b
b
b
If (B ) = 0, RNI @, P
1; if (B ) ¥- 0, (B ) -1 ---> B , RNI (g m
b
b
b
b
If (B ) = 0, RNI Ci1 P
1; if (B ) ¥- 0, (B )
1 ---> B , RNI Ci1 m
b
b
b
If (B ) = y, clear Bb and RNI ~ P
2; if (B ) ¥- y, (B ) -1 -----> Bb
and RNI (g P
1
IJD
IJI
ISO
ISE
ISE
ISG
ISG
lSI
(E)
=
RNI (g P
RNI @, P
RNI (g P
+
+
+
1
1
2
(
3 )
(A) and (0) are
unchanged
0, jump to m; (E) ¥- 0, RNI Ci1 P
<
+
7-33
7-49
7-49
1
1
+
+
+
0, RNI ~ P
2, otherwise RNI (g
b
If y = (B ). RNI (g P
2, otherwise RNI
If y
2:: 0, RNI Ci1 P
2, otherwise RNI
b
If (B ) 2': y, RNI ~ P
2, otherwise RNI
=
+
+
+
b
If (B ) = y, clear Bb and RNI Ci1 P
B b, R N I @, P
1
----->
+
+
+
+
If y
+
+
+ 2;
+1
(g P + 1
Ci1 P + 1
P
~ P
+1
b
b
if (B ) ¥- y, (B )
+
7-49
7-34
7-33
7 -19
7 -13
7 -13
7-14
7-14
1
7-19
SRCE,INT
Search for equality of character c in a list beginning at location r
until an equal character is found, or until character location 5 is
reached; 0 ~ c ~ 6310
7-56
SRCN,INT
Same as SRCE except search condition is for inequality
7-56
SSH
Test sign of (m), shift (m) left one place end around and replace
in storage. If sign negative, RNI ~ P
2; otherwise RNI ~ P
1
7-50
MEO
(B1) -i----B1;if(Bl)negative,RNI(g P+ 1; if(B1) positive, test
(A) 2:: (0) 1\ (M). if true, RNI~ P
2, if false, repeat sequence
7-54
MTH
(B2 - i ---- (B2); if (B2) negative, RNI fu P
1; if (B2) positive, test
(A) 2:: (0) 1\ (M); if true, RNI ~ P + 2; if false, repeat sequence
Sense busy lines. If "1" appears on a line corresponding to "1"
bits in x, do not advance P. If P is inhibited for longer than 40 ms,
read reject instruction from P
1. If no comparison, RNI (g
PAUS
+
+
+
+
7-55
+
7-64
P+2
19
TABLE 3. FUNCTION LISTING OF INSTRUCTIONS (CONTINUED)
FUNCTION
Decision
(Continued)
MNEMONIC
INSTRUCTION DESCRIPTION
CODE
OSE
OSE,S
OSG
OSG,S
PAGE
NO.
+ 2; otherwise RNI @ P + 1. lower 15 bits
If y = (0). RNI @ P + 2. Otherwise RNI @ P + 1. Sign of y is
extended
If (0) 2 y, RNI @ P + 2, otherwise RNI @ P + 1
If (0) 2 y, RNI @ P + 2, otherwise RNI @ P + 1. Sign of y is
Ify = (0). RNI @ P
of 0 are used
extended
Shifts
SHA
SHAO
SHO
+
+
+
SCAO
Shift (AO) left end around until upper 2 bits of A are unequal.
Residue K = k-shift count. If b = 1 , 2, or 3, K - t B b; if b = 0, K is
discarded
SFEttt
Shift E in one character (4-bit) steps. left shift: bit 23 = "0",
magnitude of shift = lower 4 bits of K = k
(B b). Right shift: bit
23 = "1 ", magnitude of shift = lower 4 bits of complement of
+ (B b )
External status code from 1/0 channel ch to lower 12-bits of A
+
contents of interrupt mask register to upper 12-bits of A. R N I
@P+1
Set Type In ~ Beginning character address must
be preset in location 23 of
register file and last character
Set Type out) address
1 must be preset in
location 33 of the file.
Sense external status if "1" bits occur on status lines in any of
the same positions as "1" bits in the mask, RN I @ P
1. If no
comparison, RNI
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