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Control Data®3100 Computer System
Preliminary Reference Manual
3100 Computer Instruction Index
Mnemonic &
Octal Code
Name
Page
Mnemonic &
Octal Code
Name
Page
Unconditional Stop
5-4
SBAO
33
Subtract from AO
5-19
SJl-6
Selective Jump 1-6
5-4
RAD
34
Replace Add
5-18
RTJ
Return Jump
5-5
SSA
35
Selectively Set A
5-13
Unconditional Ju'mp
5-5
SCA
5-5
LPA
Selectively Complement A
Logical Product A
5-13
Index J.ump, Incremental
36
37
Index Jump, Decremental
5-5
40
Store A
5-15
Compare A with Zero
5-6
STA
STO
41
Store 0
5-15
Compare A with 0
5-7
SACH
42
Store A, Character
5-16
= y
Skip if (0) = y
b
Skip if (B ) = y
5-9
SOCH
43
Store 0, Character
5-16
5-9
SWA
44
Store Word Address
5-16
5-9
STAO
45
Store AO
5-16
Skip if (A) ~ y
5-9
SCHA
46
Store Character Address
5-16
Skip if (0) ~ y
Skip if (Bb)~ y
5-9
STI
47
Store Index
5-16
5-9
MUA
50
Multiply A
5-18
HLT
UJP
IJI
00
01
02
IJD
AZJ
03
AOJ
ASE
04
OSE
ISE
ASG
05
OSG
Skip if (M
5-13
ISG
MEG
06
Masked Equality Search
5-11
OVA
51
Divide A
5-18
MTH
07
Masked Threshold Search
5-12
CPR
52
Compare
5-13
SSH
lSI
10
Storage Shift
5-12
---
Index Skip, Incremental
5-8
5-8
LDI
MUAO
53
54
56
Inter-Register Transfers, 24 Bit
Load Index
Multiply AO
5-17
5-15
5-19
5-19
ISO
ECHA
SHA
Index Skip, Decremental
11
12
Enter A, Character Address
Shift A
Shift 0
5-8
DVAO
57
Divide AO
5-10
FAD
Floating Point Add
5-20
5-10
60
61
Floating Point Subtract
5-20
13
Shift AO
5-11
FSB
*FMU
62
Floating Point Multiply
5-20
5-11
*FDV
63
5-9
*LDE
64
Floating Point Divide
Load E
5-20
14
Scale AO
Enter A
ENO
Enter 0
5-9
*STE
Enter Index
5-9
*ADE
Store E
Add to (E)
5-22
ENI
65
66
Increase A
5-9
*SBE
67
Subtract from (E)
5-23
Increase 0
*SFE
*EZJ
70
Increase Index
5-9
5-9
Shift E
E Zero Jump
5-21
5-22
SHO
SHAO
SCAO
ENA
INA
1~
INO
INI
5-22
5-22
Exclusive OR of A and y
5-9
*EOJ
E Overflow Jump
5-22
XOO
Exclusive OR of 0 and y
5-9
*SET
Set 0 Register
XOI
Exclusive OR of Index and y
5-9
SRCE
AND of A and y
5-9
SRCN
AND of 0 and y
AND of Index and y
5-9
5-22
3-6
3-6
3-7
3-8
3-8
3-8
3-8
3-8
XOA
ANA
16
17
ANO
ANI
71
Search Character Equality
MOVE
72
Move Data
5-9
INPC
73
Input. Character Block to Storage
Search Character Inequality
LOA
20
Load A
5-14
INAC
LOO
21
Load 0
5-14
74
LACH
22
Load A, Character
5-14
INPW
INAW
LOCH
23
Load 0, Character
5-14
OUTC
75
LCA
24
Load Complement A
5-15
OTAC
LDAO
25
Load AO
5-15
LCAO
26
Load Complement AO
5-15
OUTW
OTAW
LDL
ADA
27
Load A Logica I
Add to A
5-15
---
Subtract from A
Add to AQ
5-18
SBA
ADAQ
30
31
32
*Trapped instructions. See also Chapters 3 and 5.
5-18
5-19
Input. Character to A
Input. Word Block to Storage
Input, Word to A
Output. Character Block from Storage
Output. Character from A
3-8
76
Output. Word Block from Storage
Output. Word from A
3-8
3-8-
77
Sense, Select Interrupt and Control
functions
5-24
Control Data® 3100 Computer System
Preliminary Reference Manual
Record of Revisions
REVISION
NOTES
Address comments concerning this Manual to:
Control Data Corporation
Pub. No. 60108400
July, 1964
©1964, Control Data Corporation
Printed in the United States of America
Technical Publications Department
4201 North Lexington
St. Paul, Minnesota 55112
or use Comment Sheet located in the
rear of this book.
CONTENTS
CHAPTER 1.
SYSTEMS HARDWARE DESCRIPTION
System Concepts...................................
Summary of 3100 Characteristics...............
CHAPTER 2.
1-1
1-1
3100 Computer System ............................ 1-2
Peripheral Equipment ............................... 1-7
SYSTEMS SOFTWARE DESCRIPTION
3100 SCOPE ....................................... 2-1
3100 FORTRAN .................................... 2-3
3100 COMPASS .................................... 2-1
3100 Data Processing Package ................... 2-2
3100 COBOL ........................................ 2-3
3100 Generalized Sort/Merge Program......... 2-4
PROGRAMMING FEATURES
CHAPTER 3.
Program Interrupts.................................
Special Power Failure Interrupts.................
Trapped Instructions...............................
CHAPTER 4.
3-1
3-3
3-3
Integrated Register File............................
Real-Time Clock....................................
Block Operations......... .... .... . .. .. . . .. . . ..... ..
3-4
3-5
3-5
OPERATING FEATURES
Displays and Indicators............................ 4-1
CHAPTER 5.
Basic System....................................... 2-4
Switches " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-3
REPERTOIRE OF INSTRUCTIONS
General Information ................................
5-1
Instructions.. . ... .. .. .. . .. .. .... . . .. . ... . .. ...... . ..
5-3
APPENDIXES
A.
B.
C.
D.
3100 Compass
E.
Octal-Decimal Integer Conversion Table
BASIC Assembler Coding Procedure
Number Systems
Table of Powers of Two
F.
G.
Octal-Decimal Fraction Conversion Table
H.
I.
3100 System Character Set
Definition of 1/0 Interface Signals
Peripheral Equipment Code
FIGURES
1- 1
1-2
1-3
1-4
1-5
3-1
3-2
3-3
3-4
3-5
CONTROL DATA 3101 Desk Console
Parity Bit Assignment ..................
Word Addressed Instruction Format ..
Character Addressed Instruction Format
Storage addressing and Data Paths
of Typical installation .................
Search Operation .......................
Move Operation .........................
Initial Steps of 1/0 Sequence .........
Input, Character or Word to A ...... "
Output. Character or Word from A ...
1-3
1-3
1-4
1-4
1-6
3-6
3-7
3-8
3-9
3-9
3-6
Input Character Block to Storage .... 3-11
3-7
3-8
3-9
4-1
4-2
Input, Word Block to Storage ......... 3-11
Output. Character Block from Storage 3-12
Output. Word Block from Storage .... 3-12
Integrated Console ...................... 3-1
4-3
5-1
Temperature Warning Designations for
Fully Expanded 3104, Front View ... 4-3
3104 Console Keyboard ................ 4-5
General Machine Code
5-2
Instruction Formats ................... 5-1
Indirect Addressing Routine ........... 5-2
TABLES
1- 1
Optional Memory Configuration .......
1-2
Properties of Arithmetic and
Control Registers .. . .. . ... . ........ . ...
1-2
1- 6
1- 10
Line Printer Characteristics ... .... . ....
1- 1 1
Printer Controller Characteristics . .. .
1-8
3-1
Interrupt Mask Bit Assignments . .. . . . .
3-2
1- 8
_ 1-3
Tape Transpo rt Characteristics ..... . ..
1-7
3 -2
Interrupt Priority................. . ..... ..
3-2
1-4
Tape Transport Controllers .. . ........ ..
1-7
3-3
Representative Interrupt Codes ...... ..
3 -3
1-5
1- 6
Card Reader Characteristics ... .. ... .. .
1-7
3-4
List of Trapped Instructions .... . .. . .. . .
3-3
3-5
Integrated Register File Assignments .
3 -4
3 -6
4-1
4 -2
4 -3
4 -4
Block Operations .... .. .. . . . . .. . . . . .. ....
3-5
Card Reader Controller
Characterist ics . . . . . .. . . .. . . . .. . .....
1- 8
1- 7
Card Punch Characteristics.. ... . .. .. ...
1-8
1- 8
Card Punch Controller Characteristics
1-8
1- 9
Paper Tape Reader Punch
Characteristics ..... ... ........ .
~
-- - -
---
1- 8
Register Displays .... . ..... ... .... . ......
4 -2
Main Console Operator Switches. . . ..
4-4
Keyboard Switches .......... .. . . ... ... .
4 -6
Maintenance Switches . . ..... . .... . . . ..
4-7
---
---------
7
1
Systems Hardware Description
System Concepts
The CONTROL DATA* 3100 is a mediumsize, solid-state, general-purpose digital computing system. Advanced design techniques used in
the system provide for fast solutions to data processing, scientific and real-time problems. Modular
construction is utilized by 3100 computers to permit adaptation to the design requirements of exacting installations.
The 3100 is program compatible to the CONTRoL DATA 3200 computer system and is consistent with the Input/Output Specification for the
3000 computer series. An integrated register file
and block control system are used in all 3100 computers and trapped instructions include those pertinent to BCD, floating point, and 48-bit precision
multiply and divide.
A complete line of peripheral equipment may
be incorporated into a 3100 system, including the
following:
-CONTROL DATA 601, 604 and 607 Tape
Transports which are Ih-inch magnetic tape
units that can handle binary or BCD data, recording at densities up to 800 bits per inch with
tape speeds from 37.5 inches/second to 150
inches/second reading forward or backward.
-CONTROL DATA 405 Card Reader which
reads cards at a 1200 card per minute rate.
-CONTROL DATA 501 Line Printer which
prints 136 character lines at up to 1000 lines per
minute.
Also available are a paper tape reader/punch,
a medium speed line printer, and an I/O typewriter.
Summary of 3100 Characteristics
GENERAL
-Stored-program, general-purpose computer
- Parallel mode
-Solid-state logic
- Real time clock
- Program interrupt
-1.0 J.lsec storage access time
- Indirect addressing
INPUT/.UTPWT
-Standarel
one 12-bit bidirectional I/O channel
-Optional
3 additional 12-bit channels, or
2 additional 12-bit channels and
1 additional 24-bit channel
-Data transfer rate up to 3.3 megabits/second
-Mediums
magnetic tape, punched cards, paper tape,
printed forms
COMPUTER
-Complete repertoire of instructions, word and
character oriented
- Three index registers
- Arithmetic
fixed point 24-bit precision
fixed point 48-bit precision add and subtract
fixed point 48-bit precision multiply and divide.
(trapped)
floating point with 36-bit coefficient biased
exponent and 1-bit coefficient sign (trapped)
BCD (trapped)
- Typical instruction execution time
fixed point 24-bit addition, 3.5 J.ls with storage
access
CONSOLES
-Standard
integrated console with binary displays and detachable keyboard
-Optional
separate desk console including detachable keyboard and on line typewriter
STORAGE
- Magnetic core memory
-Word size
24-bit words with four characters per word
4 parity bits, one per character
-4,096 words/16,384 characters, basic memory
size; expandable to 8,192, 16,384, or 32,768
words
-1.75 J.lsec complete cycle time
SOFTWARE
-Operating system: 3100 SCOPE
-Assembly program: 3100 COMPASS
- Basic System (3104 4K memory oriented)
-3100 Data Processing Package used with the
assembly program under the operating system;
business and I/O Macros
- Business language compiler: 3100 COBOL
-Scientific language compiler: 3100 FORTRAN
*Registered Trademark of Control Data Corp.
1-1
3100 Computer System
A 3100 computer system consists of combination logic modules selected by the customer to
best fit his needs.
3104 COMPUTER
The 3lO4 computer contains arithmetic and control logic to perform 24-bit precision fixed point
arithmetic, 48-bit precision fixed point addition
and subtraction, Boolean, character and word
handling, and decision making operations. The
computer win also execute BCD, floating point
and 48-bit precision multiply and divide as trapped
instructions.
The 3lO4 computer uses a panel type console
integrated with the main frame of the computer.
The panel is mounted at one end of the cabinet
and is equipped with binary displays, control
switches, monitor loudspeaker and removable
keyboard to facilitate remote operation.
A 4,096 word memory and a 12-bit bidirectional data channel are also incorporated in the
3104.
COMMUNICATION CHANNELS (I/O)
The following I/O channels are available for
3100 computing system.
31, 06 Com munications Channel
The 31.06 is a bidirectional, 12-bit, parallel data
channel. Up to eight peripheral equipment controllers may be .connected in parallel to one channel. One module may be installed in the main
computer cabinet. Additional modules must be
contained in adjacent cabinets. A maximum of four
3106 channels may be used with any 3100 system.
3107 Communications Channel
In lieu of two 3106 channels, one 3107 may be
used. The 3107 is a bidirectional, buffered 12- or
24-bit data exchange communication channel. It
features 12 to 24 bit assembly, disassembly and
permits attachment of one to eight peripheral controllers to a 3100 system. Only one 3107 can be
used per 3100 computer system.
CONSOLES
Two consoles are available for use in the 3100
computer system. They are electrically compatible;
however, only one type may be used in a system.
1-2
I ntegrated Console
The integrated console, standard on a 3104 computer, is a panel type mounted on the end of the
main computer frame. This console features binary
displays monitor loudspeaker and a removable
keyboard for remote operation. The 3192 on-line
monitor typewriter which connects directly to the
computer, is ordered separately when the integrated console is used in a system.
3101 Desk Console
The 3101 desk console is electrically identical to
the integrated console but features a condensed
display and control unit mounted above an on-line
monitor typewriter included with this console. The
3101 is optional in 3100 systems. Figure 1-1 illustrates a 310 1 desk console.
OPTIONAL STORAGE
A customer may select a combination of magnetic core storage (MCS) modules to increase the
total storage capacity of his 3104 computer system
to 8,192, 16,384 or 32,768 words. The following
storage modules are available:
3108 -Optional 4,096 word (16,384 characters)
MCS memory module.
3109-0ptional 8,192 word (32,768 characters)
MCS memory module.
3103-0ptionaI16,384 word (65,536 characters)
MCS memory module.
Memory configurations are shown in table 1.
Table 1-1. Optional Memory Configurations
Total Expanded
Memory Capacity
Memory Modules Required in
Addition to 4K Memory in 3104
8K
16K
32K
3108
3108 and 3109
3108,3109 and 3103
STORAGE CHARACTERISTICS
Storage modules in a 3104 computer system are
composed of fields, consisting of 4,096 words, 28
bits per word. A particular system may have 1, 2,
4, or 8 such fields. These fields operate together as
one large storage system during the execution of
stored programs.
Figure 1-1.
Control Data 3101 Desk Console
Storage Word
Storage words contain 28 bits. Twenty-four of
these are for information; four are for parity.
Parity
For parity checking purposes, each storage
word is broken into four 6-bit groups, each of
which has one parity bit associated with it.
Figure 1-2 shows parity bit assignments .
During each write cycle, a parity bit is stored
along with each group. When part or all of a
27
26
25
24 23
18 17
Character 0
word is next read from storage , the appropri ate parity bit(s) accompany the word to the
control section of the chassis where it is
checked for a loss or gain of bits. The 3100
uses odd parity. That is, the total number of
"1 's" in a character, plus the parity bit, is
always an odd number. Any failure to produce
the correct parity during read operations
causes a memory fault indication that is followed by an immediate program halt. This
halting may be avoided by use of the Disable
Parity switch. An indicator light on the storage
module control panel indicates a parity error.
06 05
12 11
Character 1
00
Character 2
" ' - - - - - - - - - - - - - - - - - - - - Parity
"'---------------------Parity
" ' - - - - - - - - - - - - - - - - - - - - - - Parity
" ' - - - - - - - - - - - - - - - - - - - - - - - Parity
bit
bit
bit
bit
for
for
for
for
character
character
character
character
Character 3
3
2
1
0
Figure 1-2. Parity Bit Assignments
1-3
Storage Addressing
Storage Sharing
Two 3104 computers may share the use of a
common storage module. A switch on each storage
module control panel allows the operator to give
exclusive control to the right- or to the left-hand
computer. A middle position on this switch actuates a two-position priority scanner. The requests
are honored by storage control on a nonpriority
basis. Neither computer has priority over the other.
The computer being serviced by the current storage
cycle relinquishes control to the awaiting computer
at the end of the cycle. Either computer can there-
Most instructions used with the 3100 computer refer to a unique storage word or to a
character within a particular word.
Word Addressing
Figure 1-3 shows the format of a word addressed instruction.
Character Addressing
Figure 1-4 shows the format of a character
addressed instruction.
23
18 17 16
15 14
00
Designators
'14
13 12 11
Module Field
0-3
0-1
Co-ordinate Address
within field
0000-77778 (4095)
Figure 1-3. Word Addressed Instruction Format
23
18 17 16
00
m
Designators
Function/
/
Operation (or it may
specify a particular
index)
I
1
116
I
15 14 13
02 01
00,
W---.y..----kYJ
Module Field
0-3
0-1
Co-ordinate Address
within field
0000-77778 (4095)
Character
0-3
Figure 1-4. Character Addressed Instruction Format
fore be delayed a maximum of one storage cycle.
A two-position scanner within each computer determines whether main control or block control
has access to the storage module; thus a similar
program delay may occur within either computer.
Registers Associated with Storage
Two registers are associated with each storage
1-4
module: Sand Z.
• The 13-bit S Register contains the address
of the word being currently processed. Bit 12
specifies field 0 or field 1. Bits 00-11 specify
the co-ordinates of the word.
• The 28-bit Z Register is the storage restoration and modification register.
Read/Write Control
During a normal memory cycle, all bits of a
word referenced by the (S) are read out of core
storage in parallel, loaded into Z, used for some
purpose, then written back into storage, intact.
Five modes exist in the 3100 computer for storage
modification. In all cases, assume that Z is initially
in the cleared state.
Single-Character Mode. Anyone character may be
inhibited during the read cycle. New data is then
loaded into the corresponding character position
of Z and the whole (Z) is stored.
Double-Character Mode. The upper, middle, or
lower half of a word is inhibited during the read
cycle. New data is loaded into the unfilled half of
Z and the whole (Z) is stored.
Triple-Character Mode. Either of the two possible
triple-character groups may be inhibited during the
read cycle. New data is then loaded into the corresponding character positions of Z and the whole
(Z) is stored.
Full- Word Mode. The whole word is inhibited during the read cycle. A new word is entered into Z
and the (Z) is stored.
Address Mode. The lower 15 or 17 bits of a word
may be inhibited during the read cycle. A new word
or character address is then loaded into Z, and the
whole (Z) is stored.
After all write cycles, Z is cleared unless the
computer has stopped as the result of a memory
parity error.
2 Shifting - A may be shifted to the right or
left separately or in conjunction with O. Right
shifting is open-ended; the lowest bits are
discarded and the sign is extended. Left shifting is circular; the highest order bit appears
in the lowest order stage after each shift; all
other bits move one place to the left.
3 Control for conditional instructions - A holds
the word which conditions jump and search
instructions.
The Q register is an allxiliary register and is
generally used in conjunction with the A register.
The principal functions of Q are:
1 Providing temporary storage for the contents
of A while A is used for another arithmetic
operation.
2 Forming a double-length register, AO.
3 Shifting to the right or left. separately or in
conjunction with A.
4 Serving as a mask register for 06, 07, and
27 instructions.
Both A and Q may load, or be loaded from any
of the three index registers without the use of
storage references.
CONTROL SECTION
The control section contains five operational
registers. As in the arithmetic section, these registers are displayed on the console and loaded from
the entry keyboard. They are the:
F - program control register
p- program address counter
B 1 through B3 - index registers
ARITHMETIC SECTION
The arithmetic section of the 3100 computer
consists of two operational registers. They are displayed on the console and each may be loaded
from the entry keyboard. These registers are the:
A - arithmetic register
a-
auxiliary arithmetic register
The A register (accumulator) is the principal
arithmetic register. Some of the more important
functions of A are:
1 All arithmetic and logical operations use the
A register in formulating a result. The A register is the only register with provisions for
adding its contents to the contents of a storage location or another register.
The program control register, F, holds an instruction during the time it is being executed. After
executing an instruction, an exit, jump exit, or
skip exit is performed. An exit advances the count
in P by one and executes the next instruction specified by the contents of P. A jump exit executes the
instruction at the storage location specified by the
execution address of the jump instruction. The
execution address is, in this case, entered into P
and used to specify the starting location of a new
sequence of instructions. A skip exit advances the
count in P by two, bypassing the next sequential
instruction and executing the following one.
The P register is the program address counter.
It provides program continuity by generating in
sequence the storage addresses which contain the
individual instructions. Usually at the completion
1-5
Table 1-2. Properties of Arithmetic and Control Registers
Register
No. of Stages
Modulus
Complement
Notation
A
24
224_1
one's
additive
signed*
Q
24
224_1
one's
additive
signed
Result
Arithmetic
F
24
224_1
**
**
**
p
15
2 15 _1
one's
additive
unsigned
BLB3
15
2 15 _1
one's
additive
unsigned
of each instruction, the count in P is advanced by
one to specify the address of the next instruction.
The three index registers, BI through B3, provide storage for quantities which are used in a
variety of ways, depending on the instruction. The
B registers have no provisions for arithmetic operations. In a majority of instructions they hold
quantities to be added to the execution address. All
address modifications are performed in the Adder.
Table 1-2 is a summary of the properties of the
A, Q, F, P, and B registers.
A sixth operational register, closely related to
the control section, is the communications register.
Quantities to be entered into any of the above
registers or into storage from the entry keyboard
-
I
are temporarily held in the communications
register until the transfer button is pushed. If a
mistake is made while entering data into the
communications register, the Keyboard Clear
button may be used to clear this register.
COMPUTER ORGANIZATION
All modules of the 3100 computer except the
console are connected in parallel to a common
bidirectional data bus. The address registers of all
storage modules are connected in parallel to main
control by the address bus. Figure 1-5 is a block
diagram of storage addressing and data paths within a typical computer installation.
Storage Address S Bus
T
3108
Storage
Module
(4K)
-
I r
3106
1-
I
,-----,
I
3104
Computer
(Includes Standard
4K Memory)
.-------.l
I
I
3101
I
I
Desk
Console I
(Optional) :
L _ _ _ _ _ _ ...J
Data Bus
I
3106
3106
3109
Storage
Module
(8K)
-
r
I
3106
4 bidirectional data channels
Figure 1-5. Storage Addressing and Data Paths of Typical Installation
*NOTE: The result of an arithmetic operation in A
satisfies A S; 2 23 _1, since A always is treated as a
signed quantity. When the result in A is zero, it is
always represented by 00000000.
1-6
**NOTE: Only the lower 15 or 17 bits of F are modified, depending on whether word or character addressing is being used. The results are unsigned.
Peripheral Equipment
Peripheral equipment is available for handling
magnetic tape, punched cards, punched paper
tape, and printed forms. Other pieces of equipment for the 3100 computer system are a program
controlled I/O typewriter, an incremental plotter,
and a Satellite coupler. For details on any particular piece of peripheral equipment, refer to the
reference manual concerning that equipment.
MAGNETIC TAPE
Magnetic tape is processed on either the
CONTROL DATA 601, 604 or 607 Tape Transports. A variety of tape transport controllers IS
available, each with a different capability.
Tape Transports
Table 1-3 lists the operating characteristics of
the 601, 604 and the 607 Tape Transports. Tapes
may be read forward or backward with both models.
Tape Transport Controllers
Tape transport controllers are differentiated by
the number of read/write controls they contain
and by the number of tape transports that they can
control. Eight types are available (see table 1-4).
The tape transport controllers marked by a dagger (t) will most commonly be selected for a 3100
computer system. A multi-channel controller 'may
be used for buffered communication between two
or more computers in a multi-computer installation.
Table 1-3. Tape Transport Characteristics
Characteristic
601
604
607
Tape length
2400 feet
2400 feet
2400 feet
Tape width
~
~
Tape speed
Word size including one parity bit
Bit density
Maximum bit transfer rate
-inch
37.5 inches/sec
7 bits
200. or 556 bpi
7.5 or 20.85 kc
Table 1-4. Tape Transport Controllers
Model Number
No. of Read
Write Controls
Maximum No. of
Tape Transports
t3127
t3228
t3229
3621
3622
3623
3624
3625
3626
1
1
1
2
2
4
4
3
3
4
4
8
8
16
8
16
8
16
-inch
75 inches/sec
7 bits
200. 556. or 800 bpi
15. 41.65. or 60 kc
~
-inch
150 inches/sec
7 bits
200, 556. or 800 bpi
30. 83.3. or 120 kc
PUNCHED CARDS
Cards are read with a Control Data 405 Card
Reader and punched with an IBM 523 or 544
Card Punch.
Card Reader. Table 1-5 lists the operating characteristics of the 405 card reader.
Card Reader Controllers. Two card reader controllers are available. Table 1-6 lists the characteristics
of each. Both types of controllers are mounted on
chassis within the 405 cabinet.
Table 1-5. Card Reader Characteristics
Speed - 80 column cards
1200 cpm
Speed - 51 column cards
1600 cpm
Reading method
photo-electric. column-by-column
Verification method
double read - comparison
Card separation and picking method
pneumatic
Card capacity- main tray
4000 cards
240 cards
Card capacity - reject tray
1-7
Table 1-6.
Card Reader Controller Characteristics
Characteristics
BCD Conversion
Checking
Full card buffer
No. of read controls
3248
3649
Yes
Yes
No
1
Yes
Yes
Yes
2
Card Punches. Table 1-7 lists the operating characteristics of the 523 and 415 card punches.
Card Punch Controllers. Two types of card punch
controllers may be used. Each type is mounted in
its own peripheral equipment cabinet. Table 1-8
lists the controller characteristics.
PUNCHED PAPER TAPE
A unit frequently used for reading programs into
storage and for recording data from storage is the
3691 Paper Tape Reader Punch. Table 1-9 lists the
characteristics of this device.
Table 1-7. Card Punch Characteristics
Characteristics
523
415
Speed-80 column cards
Card hopper capacity
100 cpm
800 cards
250 cpm
1200 cards
Punch method
Mechanical.
row-by-row
Table 1-8.
Card Punch Controller Characteristics
Characteristics
Checking
Full card buffer
No. of Write controls
3245
3644
No
No
1
Yes
Yes
2
all 3100 computer systems. The printer and con:troller characteristics are listed in Tables 1-10
and 1-11.
Table 1-10. Line Printer Characteristics
Table. 1-9.
Paper Tape Reader Punch Characteristics
501
Characteristics
Printing speed
Reading speed
Punching speed
No. of read/write controls
350 characters/sec
110 characters/sec
64
No. of columns
120
1
PROGRAM CONTROLLED
I/O TYPEWRITER
The 3692 Program Controlled I/O Typewriter
has one read/write control. It differs from the online 3192 typewriter in that it must be connected to
the computer via a 3106 Communication Channel.
INCREMENTAL PLOTTER
The 3293 Incremental Plotter can make 300 .01
inch steps per second. Form width is 11 inches.
PRINTED FORMS
The 501 High Speed Line Printer is available for
1-8
1000lpm
No. of characters
Table 1-11. Printer Controller Characteristics
Characteristics
No. of write controls
Full line buffer
3256
3659
1
2
Yes
Yes
SATELLITE COUPLER
The 3682 Satellite Coupler permits direct connection between any two standard 12-bit bidirectional channels, or channel converters. With the
addition of a 3681 Data Channel Converter, a
160-A Computer may be used as a satellite to the
3100 computer system.
2
Systems Software Description
There are various programming language techniques which facilitate
writing programs for the CONTROL DATA 3100 Computer System.
The following pages contain a synopsis of the methods listed below.
e
3100SCOPE
Monitor System
e
3100 COMPASS
Assembler
e
3100 DATA PROCESSING PACKAGE
e
3100 COBOL
Macro Instructions, Generalized 1/0
Business Language Compiler
e
3100 FORTRAN
Scientific Language Compiler
e
3100 GENERALIZED SORT/MERGE PROGRAM
Operates Under 3100 SCOPE
e
BASIC SYSTEM
Basic Assembler, Basic FORTRAN II
3100 SCOPE
SCOPE is the operating system for the CONTROL DATA 3100 Computer. Modular in structure, the system provides efficient job processing
while minimizing its own memory and time requirements. Programming with the operating
system is simplified by the use of control cards
which are included with program decks. Among
the functions performed by SCOPE are the following:
EQUIPMENT ASSIGNMENTS
• logical unit references
• physical unit assignment at run time
• drivers for all standard peripheral equipment
• system units which facilitate job processing
and minimize monitor programming
DEBUGGING AIDS
• extensive diagnostics
JOB PROCESSING
• processes stacked or single jobs
• controls I/O and interrupt requests
• monitors compilations and assemblies
• loads and links object subprograms
• stores accounting information
• initiates recovery dumps
• prepares overlay tapes
• octal corrections
• snapshot dumps
• recovery dumps
LIBRARY PREPARATION AND EDITING
• prepare a new library
• edit an existing library
• list the contents of a library
3100 COMPASS
COMPASS is the comprehensive assembly system for the CONTROL DATA 3100 Computer.
Operating under 3100 SCOPE, it assembles relocatable machine language programs. The program
may consist of subprograms, each of which may be
independently assembled. Refer to Appendix A for
3lO0 COMPASS coding procedures. COMPASS
source language includes the following features:
Operation codes
Machine operations are written
as one or more mnemonic or
octal subfields.
Addressing
Expressions, used as addresses,
may represent either word or
character locations. Expressions
consist of symbols, constants,
and special characters connected
by
and -.
+
Data storage
A data area. shared by subprograms, may be specified and
loaded with data in the source
program.
Common storage
A common area may be designated to facilitate communication among subprograms.
Data definitions
Constants may be defined as
octal. decimal. double-precision,
integer or floating-point numbers; BCD words, BCD characters; or contiguous strings of bits.
Library access
Library routines may be called
by reference to their entry points
or by inclusion of macros in the
source program (data processing
macros).
Listing control
The format of the assembly listing may be controlled by pseudo
instructions.
Diagnostics
Diagnostics for source program
errors are included with the output listing.
Macro instructions
Macros may be defined in the
source program or entered into
the library; the sequence of instructions will be inserted whenever the macro name appears
in the operation field.
THE ASSEMBLER
The 3100 COMPASS assembly program converts programs written in 3100 COMPASS source
language into a form suitable for execution under
the 3100 SCOPE operating system. Source program
input may be on punched cards or in the form of
card images on magnetic or paper tape. The output
from the assembler includes an assembly listing
and a relocatable binary object program on punched
cards or magnetic tape.
2-1
EQUIPMENT CONFIGURATION
The assembly system, which is stored on the
SCOPE library tape, is designed to operate on a
3100 computer with a minimum of 8,192 words of
storage. In addition to the SCOPE library unit, the
following input! output equipment is required:
Input unit: card reader, magnetic tape, or paper
tape
Scratch unit: magnetic tape (may also be used
for output)
Listable output unit: magnetic tape or printer
Object program output unit: magnetic tape or
card punch
PROGRAM STRUCTURE
Source programs may be divided into subprograms which are assembled independently. All
location symbols except COMMON and DATA
symbols are local to the subprogram in which they
appear, unless they are declared as external symbols. Locations which will be referenced by other
subprograms are declared as entry points. For example, if subprogram IGOR references locations
KIEV and MINSK in subprogram DEMETRI,
KIEV and MINSK must be declared external symbols in subprogram IGOR and entry points in
subprogram DEMETRI.
The links among subprograms are associated by
the SCO PE loader. As each subprogram is loaded,
all external symbols and entry points are entered
into a symbol table. When an external symbol is
found which matches an entry point already entered in the table, or an entry point is found which
matches an external symbol, linkage between the
two points is established.
If any external symbols are not matched with
entry points after the last subprogram is loaded,
the library tape is searched for routines with the
names of unmatched symbols. If these routines
are found, they are loaded and linked to the other
subprograms. If external symbols remain for which
there has been no corresponding entry, the job is
terminated and an error message written by the
system.
3100 Data Processing Package
The Data Processing Package is composed of a
set of data processing routines and a generalized
input/ output system.
DATA PROCESSING ROUTINES
The data processing routines, called macros, are
used in COMPASS assembly language programs
to do particular data handling jobs; included are
the following:
TRANSM IT Transmits any string of up to 4.095
characters from one place in memory to another.
COMPARE Compares any string of up to 4.095
characters with any other string and
sets a register to indicate whether
the first string is lower, equal. or
higher than the second.
EDIT
Moves a numeric field to a receiving
field with report editing.
MULTIPLY Multiplies two BCD numbers and
stores the result in a third.
DIVIDE
Divides one BCD number by another
and stores the result in a third.
GENERALIZED INPUT/OUTPUT SYSTEM
The 3100 Generalized Input/Output System is
a series of library routines which provide complete
2-2
input/ output control for data processing. These
routines are used in COMPASS assembly programs;
they simplify programming while offering versatile
data handling and optimum usage of internal storage_space and processing time. Complete, partial
or no buffering may be designated, depending upon
the amount of storage the programmer has available; multi-file reels or multi-reel files may be read
or written; fixed or variable length logical or physical records may be processed; and magnetic tape,
paper tape, cards or printer may be used for input!
output units. Both labeled and unlabeled tapes
may be handled. The input/output macros perform
the following functions:
OPEN I
Opens an input file
OPENO
Opens an output file
READ
Reads one logical record into the
record area
WRITE
Writes one logical record from the
record area
READI
Reads one logical record into a specified area in memory
WRITEF
Writes one logical record from a
specified area in memory
CLOSE
Closes a reel or file
In addition to the input/output operations, the
programmer also describes the files to be processed
through use of macros.
FIELDESC
Defines logical records, buffers, logical units, recording density and rerun requirements.
LABELING
Describes file label and tape retention time (prevents accidental destruction of tapes).
VARIABLE Indicates whether the size of a variable length record is determined by
a record mark or a key field.
SHAREBUF Allows user to let files share the
same areas in storage.
MULTIFIL
Defines multi-file reels.
The I/O System interprets each set of instructions, refers to the file description, and then initiates the requested operation; it controls buffering,
transmission errors, and logical-physical record
divisions.
3100 COBOL
CO BO L is a programming system designed to
facilitate the solution of business data processing
problems. To use COBOL, the programmer describes the problem in a language resembling
English; the 3100 COBOL processor translates this
source language input into relocatable machine
language for program execution.
The 3100 COBOL language contains the elements set forth in the official Department of Defense Report Describing COBOL 1961, plus many
of the features defined as elective COBOL.
A COBOL source program is specified in four
divisions: IDENTIFICATION, ENVIRONMENT,
DA T A, and PROCEDURE. The IDENTIFICATION division identifies the name, author, date,
and so forth of the program. The ENVIRONMENT
division defines the computer configuration re-
quired for both compilation and execution. The
DATA division describes the format of the data
files which the program is to process. The PROCEDURE division contains a sequence of statements which describe the processing to be performed.
The 3100 COBOL compiler is a three-pass system. No object code is produced until the entire
source program has been thoroughly analyzed.
Wherever possible, in-line coding is produced. Depending on the needs of the program, the compiler
provides an input/output system which allows
variable length records, up to two buffer areas per
file, multi-file reels, multi-reel files, rerun procedures, and so forth. In general, the features of the
3100 COBOL input/output system correspond to
those described for the Data Processing package.
3100 FORTRAN
The 3100 FO R TRA N system incorporates a
problem-oriented language that facilitates simple
algebraic solution of mathematical or scientific
problems.
3100 FORTRAN programs are written as a sequence of statements, using familiar arithmetic
operations and English expre~sions. Large programs may be written independently in sections,
the sections tested, then executed together.
Statements are available to reserve areas of
memory for variables and arrays. Strings of values
may be loaded with the program for reference
during the program execution. Equivalence statements allow the same areas of memory to be identified with different variables and arrays during the
execution of a program.
Type statements specify the mode in which values
are to be stored. The possible types include: REAL,
INTEG ER, and CHARACTER. The programmer
may also declare a special mode, type OTHER, to
handle information which does not conveniently
conform to the standard modes.
Arithmetic expressions are indicated by arithmetic sign and algebraic names. For example,
A+B-C means add A to B and subtract C. Logical and relational operators are available for use
in expressions which may be true or false.
Statements are usually executed in sequence.
However, control statements may be used to transfer to another part of the program.
Sets of statements which are to be executed several times with minor changes or increments may
be written once with a statement to indicate how
many times they are to be repeated, and if they
are to be changed each time.
Input/ output operations provide a means to read
2-3
information into the machine from various sources
and to record results on a selected output device.
If buffered input/output operation is specified,
other operations may continue while information
is read in or out.
Facilities are also available to transfer a num-
ber of characters from one area of memory to
another, and to test machine conditions through
calls to 3100 FORTRAN library functions.
The 3100 FORTRAN compiler produces machine language programs which may be executed
immediately or stored for execution at a later date.
3100 Generalized Sort/Merge Program
The GENERALIZED SORT/MERGE PROG RAM organizes data on magnetic tape into one
continuous predetermined order. SORT/MERGE
operates under the 3100 SCOPE operating system.
Control cards, read from the standard input unit,
contain file descriptions and SORT/MERGE
specifications.
SORT /MERGE orders fixed or variable length
tape records, blocked or unblocked, written in
either BCD or binary mode, according to a specified collating sequence. BCD and binary collating
sequences are provided within SORT/MERGE,
or the user may specify his own. The resultant
output file may be merged with other presorted files
in a final merge pass, or, if a number of presorted
files exist, the merge phase only can be performed.
The SORT/MERGE can transfer to user prepared subroutines which perform the following
functions:
• edit acceptable records
• reject records
• check nonstandard labels
• modify nonstandard labels
• generate messages for the operator
• write secondary output file (edit sorted records)
• prepare summary file (summarize sorted records)
• terminate the sort process
The SO R T /MER G E checks standard header and
trailer labels and provides rerun dumps.
The SORT/MERGE contains an internal sort
phase and a merge phase. The sort uses the tournament replacement technique which makes maximum use of available core storage and takes advantage of existing bias in the data. The method of
merging, which is selected by the user; can be
normal balanced or polyphased with either forward or backward reading.
Basic System
The BASIC system is designed for the CONTROL DATA 3104 computer with a standard 4K
internal storage memory. This system may also be
used with the 3104 computers equipped with expanded memory modules up to 32K. Appendix B
provides coding procedures for the BASIC Assembler. Included in the BASIC system are:
BASIC ASSEMBLER
BASIC LOADER
BASIC FORTRAN "
BASIC ASSEMBLER AND LOADER
The BASIC Assembler language forms a subset
of the COMPASS language. Although designed
primarily for use on the 3104 with a 4K memory,
it can readily be used on larger systems. Object
programs produced by the BASIC Assembler are
loaded by the BASIC Loader or can be loaded by
3100 SCOPE. Source language programs must be
prepared as complete entities if they are to be
loaded by the BASIC loader. As a result, facilities
for referencing external storage areas (COM M 0 N,
DATA) and external program elements (ENTRY,
EXT, macros) are not used in BASIC Assembler
2-4
language, nor are a few of the more complex pseudo
instructions (VF, IF). All other features of the
language are similar: operation codes, addressing,
data definitions, listing control, and s·o forth.
To assemble a BASIC Assembler program, the
following configuration is required:
4K words of storage
Input unit: card reader, magnetic tape or paper
tape (used for source language input, library, and
BASIC Assembler)
Listable output unit: printer, magnetic tape, paper
tape, typewriter
Object program output unit: card punch, magnetic
tape, paper tape, typewriter (all output may be
written on one tape unit if desired)
BASIC FORTRAN II
BASIC FORTRAN II is a problem-oriented
language that performs familiar mathematical
operations in arithmetic expressions and replacement statements. The source language provides
substantial power and flexibility through a variety
of statements. BASIC FORTRAN II is compatible
with other FORTRAN II systems and provides
many of the features incorporated in 3100
FORTRAN.
2-5
3
Programming Features
This chapter discusses the following programming features of
the 3100 computer system:
•
program interrupts
•
special power failure interrupt
•
trapped instructions
•
integrated register file
•
real-time clock
•
block operations
Program Interrupts
The interrupt control section of the 3104 computer provides for testing whether certain internal
and external conditions exist without having these
tests in the main program. Examples of these conditions are internal faults and external equipment
end-of-operation. Near the end of each RNI cycle,
a test is made for these conditions. If one of the
conditions exists, execution of the main program
halts. The contents of the Program Address register, P, are stored and an interrupt routine is initiated. This interrupt routine, which has been initially
stored in memory, takes the necessary action for
the condition and then jumps back to the next
unexecuted step in the main program.
There are three major types of interrupts in the
3100 Computer System-normal interrupts (including internal and external conditions), trapped
instruction interrupts, and a special power failure
interrupt.
Normal interrupts are the only interrupts that
are completely under the programmer's control.
These interrupts are of two types-internal and external. The following paragraphs describe the interrupt causing conditions, the Interrupt Mask
register, interrupt control, and interrupt processing.
INTERNAL INTERRUPTS
Seven internal conditions may be set to cause
an interrupt. These conditions and their definitions
are:
• Arithmetic Overflow Fault
The Arithmetic Overflow fault is set when the
capacity of the adder is exceeded. Its capacity,
including sign, is 24 or 48 bits for 24-bit
precision and 48-bit precision, respectively.
• Divide Fault
The divide fault sets if a quotient, including
sign, exceeds 24 or 48 bits for 24-bit precision
or 48-bit precision, respectively. Therefore,
attempts to divide by too small a number result in a divide fault.
• Exponent Overflow/Underflow Fault
During a trapped floating point mUltiplication
and division, the Exponent Overflow/Underflow is set if the exponent exceeds 21°-1.
• BCD Fault
A BCD Fault is set if a BCD Trapped instruction is executed.
• 110 Channel Interrupts
Any of the four possible I/O channels will generate an interrupt:
1) Upon reaching the end of an input or output block, or
2) Upon receiving an End of Record (Disconnect) signal from an external device.
• Search/Move Interrupt
The Search/Move interrupt is generated during a 71 or 72 instruction:
1) Upon the completion of an equality or inequality search, or
2) Upon the completion of a block move.
• Real- Time Clock Interrupt
The Real-Time Clock interrupt is generated
when the clock reaches a prespecified time
that has been stored in register 32 of the
register file.
EXTERNAL INTERRUPTS
Three external conditions may cause interrupts.
These are:
• External I/O Interrupts
The External I/O interrupt is set when an Interrupt signal is received from any of eight
peripheral equipment controllers connected to
any of the four possible I/O channels (there
may be a total of 32 lines). The interrupt remains set until the computer directs the originating device to turn it off.
• Manuallnterrupt
The Manual interrupt is set by a switch on the
computer console. This interrupt is not masked
because it is assumed that this switch will be
pressed only when an interrupt is desired.
• Associated Computer Interrupt
If two computers are sharing a storage module, either computer may interrupt the other
by executing a 7757xxxx instruction. This interrupt is not masked. It clears out as soon as
it is recognized.
INTERRUPT MASK REGISTER
The programmer can choose to honor or ignore
an interrupt by means of the Interrupt Mask register. All but two of the normal interrupt conditions
are represented by the 12 Interrupt Mask register
bits. The mask is selectively set with instruction
7752xxxx, and selectively cleared by instruction
7753xxxx. See Table 3-1 for mask bit assignments.
3-1
Table 3-1. Interrupt Mask Bit Assignments
Mask Bit
Conditions Represented
00-07
External Interrupts on Channel 0-3,
and I/O Channel Interrupts, Channels
0-3
Table 3-2. Interrupt Priority
Priority
1
Arithmetic Overflow or Divide fault
Exponent Overflow or BCD fault
08
Real-Time Clock Interrupt
2
3-66
67-74
09
Exponent Overflow and BCD Faults
75
10
Arithmetic Overflow and Divide Faults
11
Search/Move Completion
76
77
78
As previously explained, the Manual Interrupt
and the associated computer interrupt are not
masked. The contents of the Interrupt Mask register may be transferred to the upper 12 bits of the A
register for display purposes with instruction
772cOOOO or 773cOOOO.
INTERRUPT CONTROL
Through use of the 3104 computer repertoire of
instructions, the program can recognize, sense, and
clear interrupts, and enable or disable interrupt
control.
Enabling or Disabling Interrupt Control
The programmer has master control over normal interrupts. Instruction 7774---- enables the
system; instruction 7773---- disables it. After recognizing an interrupt and entering the interrupt sequence, other interrupts are disabled automatically,
just as if a 7773---- had been executed. When leaving the interrupt subroutine, the interrupt must
again be enabled by the 7774---- instruction. After
7774----, one more instruction may be performed
before the interrupt enable takes effect.
INTERRUPT PRIORITY
An order of priority exists between the various
interrupt conditions. As soon as an interrupt becomes active, the computer scans the priority list
until it reaches an interrupt that is active. The
computer processes this interrupt and the scanner
returns to the top of the list where it waits for
another active interrupt to appear. Table 3-2 lists
the order of priority.
Sensing Interrupts
The programmer may selectively sense interrupts, independent of the Interrupt Mask register,
by using instruction 774cxxxx. Sensing the presence
of internal faults automatically clears them.
3-2
Type of Interrupt
External I/O Interrupts*
I/O Channel Interrupts**
Search/Move Interrupt
Real- Time Clock Interrupt
Manual Interrupt
Adjacent Computer Interrupt
NOTES:
*There are eight interrupt lines on each of the four
possible I/O channels, or 32 lines in all. On any given
channel. a lower numbered line has priority over a
higher numbered line. Likewise a lower numbered
channel has priority over a higher numbered channel.
Summarizing, line 0 of channel 0 has highest priority
of all external I/O Interrupts, and line 7 of channel 3
has the lowest.
** A lower numbered I/O channel interrupt has priority
over a higher numbered I/O channel interrupt.
Clearing Interrupts
I/O channel interrupts must be selectively cleared
by instruction 7750xxxx. The real-time clock, arithmetic, and search/move completion interrupts may
be cleared by:
• Sensing, after which the interrupts are automatically cleared.
• Using instruction 7750xxxx.
• Master clearing.
In instruction 7750xxxx, xxxx represents the
mask. The manual and associated computer interrupts are automatically cleared when they are recognized.
INTERRUPT PROCESSING
Four conditions must be met before a normal
interrupt can be processed:
• With the exception of the manual interrupt
and adjacent computer interrupt, a bit representing the interrupt condition must be set to
"1" in the Interrupt Mask register.
• The interrupt system must have been enabled.
• An interrupt-causing condition must exist.
• The interrupt scanner must reach the level of
the active interrupt on the priority list.
When an active interrupt has met the above
conditions, the following takes place:
• The instruction in progress proceeds until the
point is reached in the RNI cycle where an
interrupt can be recognized. At this time the
count in P has not been advanced nor has any
operation been initiated. When an interrupt is
recognized, the address of the current unexecuted instruction in P is stored in address
00004.
• A number representing the interrupt-causing
condition is stored in the lower 12 bits of
address 00005 without modifying the upper
bits. Table 3-3 lists the octal codes which are
stored for each interrupt condition.
•
Table 3-3. Representative Interrupt Codes
Representative Codes
Conditions
External interrupt
1/0 channel interrupt
Real-time clock interrupt
Arithmetic overflow fault
Divide fault
Exponent overflow fault
BCD fault
Searchlmove interrupt
Manual interrupt
Adjacent computer interrupt
OOLC*
010C
0110
0111
0112
0113
0114
0115
0116
0117
*L=line 0-7
*C = channel numbers 0-3
Program control is transferred to address
00005 and an RNI cycle is executed.
Special Povver Failure Interrupts
Failure of primary power is detected by the computer, and a special routine is executed prior to
shutdown so that no data will be lost. This operation takes 30 ms; 16 ms detection and 14 ms for
processing a special power failure interrupt.
NATURE OF THE INTERRUPT
The Power Failure interrupt overrides any other
interrupt (internal or external), regardless of the
state of the interrupt control.
PROCESSING THE INTERRUPT
Since this interrupt overrides all others, the address in which the present contents of P are stored
and the address to which the program control is
transferred must be different than that for a normal
interrupt. When a Power Failure interrupt occurs,
the machine stores the contents of P in address
00002 and transfers program control to address
00003.
Trapped Instructions
Table 3-4. List of Trapped Instructions
The 3104 computer processes 3200 type BCD,
floating point, and 48-bit precision multiply and
divide instructions by means of implemented software. These instructions, listed in table 3-4 and in
Chapter 5 are called trapped instructions.
The following operations take place when a
trapped instruction is detected:
• (P
+
1) is stored in address 00010
• The upper 6 bits of F are loaded into the lower
6 bits of address 00011; the upper 18 bits
remain unchanged.
•
Program control is transferred to address
00011 and an RNI cycle is executed.
Machine
Code
56
57
60
61
62
63
64
65
66
67
70
Mnemonic
Code
MUAQ
DVAQ
FAD
FSB
FMU
FDV
LDE
STE
ADE
SBE
SFE
EZJ, EO
EZJ, LT
EOJ
SET
Instruction Function
Multiply AQ, 48-bit Precision
Divide AO, 48-bit Precision
Floating Point Add
Floating Point Subtract
Floating Point Multiply
Floating Point Divide
Load E
Store E
Add to E
Subtract from E
Shift E
E Zero Jump, E=O
E Zero Jump, E < 0
E Overflow Jump
Set D Register
3-3
Integrated Register File
The Integrated Register File is a 64 word (24 bits
per word) memory located in the upper 64 addresses of storage. Although the programmer has
access to all registers in the file with the 53 instruction, certain registers are reserved for specific pur-
poses (see table 3-5). All reserved registers may be
used for temporary storage if their use will not
disrupt other operations that are in progress.
The contents of any register in the file may be
inspected by transferring them to the A register.
Table 3-5. Integrated Register File Assignments
Register
Numbers
00-03
10-13
20
21
22
23
24
Reserved For
Current character or word address
(channel 0-3 control)
Last character or word address ± 1
depending on the instruction (channel
0-3 control)
Current character address (search control)
Source address (move control)
Clock, current time
Current character address (type control)
Current character address (auto-Ioad/
dump control)
Register
Numbers
25-27
30
31
32
33
34
35-77
Reserved For
Temporary storage
Last character address
1 (search
control)
Destination address (move control)
Clock interrupt mask
Last character address
1 (type control)
Last character address
1 (auto-Ioad/
dump control)
Temporary storage
+
+
+
NOTE: Register numbers correspond to upper 64 word locations in memory. Unused registers, located between register assignments are used for temporary storage.
3-4
Real-Time Clock
The real-time clock is a 24-bit counter that is
incremented each millisecond and has a penod of
16,777,216* milliseconds. The clock, which is controlled by a 1 kilocycle signal, starts as soon as the
Run button on the console has been pushed. The
current time is stored in register 22 of the register
file. I t is removed from storage, updated, and com-
pared with the contents of register 32 once each
millisecond. When the clock time equals the time
specified by the clock mask, an interrupt is set.
When necessary, the real-time clock may be reset to any 24-bit quantity including zero by loading
A, then entering (A) into register 22.
Block Operations
Block operations are of three types - Search,
Move, and Input/Output. These operations use
the computer block controls and, with the exception of those operations dealing with the A register,
certain reserved registers in the register file. Block
operations, with the exception of inputs to A and
outputs from A, are buffered. After the Search/
Move or I/O control has been activated, the computer can return to its main program and continue
until an interrupt is generated or the program
senses for block operation completion. This section
presents all block operations (see table 3-6) and
includes machine code instruction formats, Instruction descriptions, and flow charts.
Table 3-6. Block Operations
SRCE
SRCN
MOVE
Search/Move instructions, character addressed and buffered
INAC
INAW
Character input
Word input
aTAC
OTAW
Character output
Word output
INPC
INPW
Character input
Word input
aUTC
aUTW
Character output
Word output
Unbuffered input to, and output from A
Buffered input to, and output from storage
* 16,777,216 milliseconds equals approximately 4
hours and 40 minutes.
3-5
SEARCH
SRCE, SRCN
Search
F =
71
This instruction initiates a search through a
block of character storage addresses looking for
equality or inequality with character 'c'. It is composed ofthree words, including the two main block
instruction words plus a one word reject instruction.
23
18
17
As a search operation progresses, m i is incremented until the search terminates when either a
comparison occurs between the search character
'c' and a character in storage, or until m i = m 2 •
If a comparison does occur, the address of the
satisfying character may be determined by inspecting mI. To do this, transfer the contents of register
20 to A with instruction 53 (see figure 3-1).
16
00
l-
23
(P
+
I z I
71
(P)
18
c
1)
17
I
e
I~register
m2
16
00
I
\...--.register 20
m'
23
(P
I NT
m2
c
e
e
m'
+
2) =
I
00
I
Reject instruction
~----------------------------------------------------------~
"1" for interrupt upon completion
last character address of the search block, plus one
00-778, BCD code of search character
"0" for SRCE, search for character equality
"1" for SRCN, search for character inequality
first character address of the search block
INSTRUCT ION
WAIT FOR BLOCK CONTROL,
THEN S BUS PRIORITY.
OPERATION
INT= I
*
WRITE(MI+I)
INTO
REGISTER 20
Figure 3-1. Search Operation
Note: Instructions 71 and 72 are mutually exclusive.
Attempts to execute one while the other is in progress
will cause a reject to P
2.
+
3-6
30
REGISTER 20 IS ADDRESS XXXX20 IN
THE HIGHEST 64 WORDS OF MEMORY.
MOVE
= 72
This instruction is used to move a block of data,
'c' characters long, from one area of storage to
another. It is composed of three words.
As a move operation progresses, m! and m 2 are
incremented and 'c' IS decremented until c = 0
f
23
18
1)
(P
+
2)
I NT
m2
c m1
00
72
~~~~
I z I _________m_2_________~I~regi~er31
I~______
17
23
+
16
l-
(P)
(P
17
(see figure 3-2). 128 characters or 32 words may be
moved. When bits 00 and 01 of m! and m 2 are "0"
and field length is a multiple of four characters,
data is moved word by word. This reduces move
time by 75% over a character by character move.
I~
16
00
c
m_1___________
_ _ _ _ _ _ _ _L -_ _ _ _ _ _ _ _ _ _
~)~register 21
Reject Instruction
"1" for interrupt
first address of character block destination
field length of block, 0-1778*
first address of character block source
INSTRUCTION
CONTROL,
THEN
S BUS
PRIORITY.
OPERATION
INCREMENT BY 4
FOR WORD MOVE
WAIT FOR BLOCK
THEN
S BUS
CONTROL,
PRIORITY.
OR I FOR CHARACTER
MOVE. DECREMENT
C BY I OR 4
CHANNEL
REQUEST
* REGISTER
HIGHEST
21 IS ADDRESS XXXX21
64 WORDS OF MEMORY.
IN THE
CHANNEL
REQUEST
*1-1778 represents a field length of 1 to 127 char-
Figure 3-2. Move Operation
acters; 0 represents a field length of 128 characters.
3-7
those that deal with storage. They all begin with
the series of steps shown in figure 3-3. See the 77
instruction in chapter 5 for details on the preliminary operations-connecting to I/O equipment
(77.0), sensing status of I/O equipment (77.2), and
selecting function of I/O equipment (77.1).
INPUT/OUTPUT
Instructions 73 through 76 enable the computer
to communicate with peripheral equipment via the
I/O channels. These instructions are of two distinct types: those that deal with the A register and
~S_T_A_R_T----lH~~_:_~_:_~_p_)---,H,--R_(E_:_D_+_~_:_--,k)
Figure 3-3. Initial Steps of liD Sequence
Operations with A
Operations with A are unbuffered. They have a
common machine code format.
INAC
f =
Input, Character to A
channel in use. A is cleared previous to an input
and in the case of a 12-bit input, the upper 12 bits
remain cleared (see figure 3-4).
OTAC Output, Character from A
73
OTAW Output, Word from A
f = 74
INAW Input, Word to A
I V77/ / / / / / / / / / / / 7\
(P)
e
23
+
1)
21 20
Ch
17
I~ /7 71 ~ I /
/ / /
23
(P
+ 2)
=/
7 / / / / / / 7/ / / I
00
R_e_ie_c_t_l_n_st_r_u_ct_io_n_ _ _ _ _ _ _ _ _------l1
L-_ _ _ _ _ _ _ _ _ _
f = operation code 73-76
I NT = "1" for interrupt on completion
Ch
1/.0 channel x; where x = 0-3
NC
"1" for no BCD conversion
e - "1" for operations with A
3-8
f =
18 17
23
75
76
A word from the lower 12 bits or from all of A
is sent to a peripheral device. Word size depends
upon the type of I/O channel in use (see figure 3-5).
(A) is retained.
A 12 or 24-bit word is read from a peripheral
device and loaded into the lower 12 bits or into all
of A. Word size depends upon the type of I/O
(P
f =
A character from the lower 6 bits of A is sent
to a peripheral device (see figure 3-5). (A) is retained.
A 6-bit character is read from a peripheral device
and loaded into the lower 6 bits of A. A is cleared
previous to the input and the upper 18 bits remain
cleared (see figure 3-4).
INSTRUCTION
LOAD
(P+I)~ZO
(p)~ZI
~--'!>01
ACTIVATE READ/
WRITE ON I/o
CHANNEL 0....;.3
WAIT FOR BLOCK CONTROL,
THEN S BUS PRIORITY.
RELEASE BLOCK
CONTROL AND
SCANNER
OPERATION
NC= 0
I/O
MODULE
GENERATES DATA
SIGNAL (INPUT
REQUEST)
WAIT
FOR REPLY
NC=I
Figure 3-4. Input. Character or Word to A
INSTRUCTION
SAME~TRUCTI~FORMAT~ 1~I~R~R~ WORD TO A {FIGURE 3-~
OPERATION
NC: 0
WAIT
FOR
REPLY
I/O MODULE
GENERATES DATA
SIGNAL (OUTPUT
READY)
!L-lr-R-E-p-L-y---'H TERMI NATE
~....
_ _ _ _......I
OUTPUT
HEX
IT
RNI AT P+3
NC: I
Figure 3-5. Output. Character or Word from A
3-9
Operations with Storage
These operations are buffered. Main computer
control relinquishes control of the I/O operations
and returns to the main program as soon as Read
or Write has been activated. They have a common
machine code format.
During the execution of word addressed I/O
instructions, the addresses m! and m 2 are shifted
left two places to the upper 15 bits of the 17 -bit
address positions. From this time on, they are
treated as character addresses.
Registers 00-178 of the register file are reserved
for buffered I/O operations; the last octal digit of
the register designator corresponds to I/O channel
x through which data is being transferred. 00-07
hold the current character or word address, and
10-178 hold the last character or word address,
± 1, depending on the operation.
INPC Input, Character Block to Storage
f= 73
This is a character addressed instruction; 6 or
12-bit characters are read from peripheral equipment and stored in memory (refer to figure 3-6).
IfH=O, there is 6 to 24-bit assembly. If H= 1,
there is 12 to 24-bit assembly. During this 12 to
24-bit assembly, the lowest bit of each character
address is not read. This ensures that assembled
characters are in either the upper or the lower half
of a storage word.
M2 = last character address of input data block,
plus one (minus one, for backward storage).
INPW Input. Word Block to Storage
f =
74
This is a word addressed instruction with the
addresses initially placed in the lower 15 bits of the
23
(P)
+
1)
+
2)
21 20 19 18 17 16
OUTW Output. Word Block from Storage
f = 76
This is a word addressed instruction with the
addresses initially placed in the lower 15 bits of the
instruction words. Words are read from storage
and sent to a peripheral device (refer to figure 3-9).
If N = 0, there is 24 to 12-bit disassembly. If
N = 1, there is a straight 12 or 24-bit data transfer
depending on the I/O module capabilities. If an
attempt is made to send 24 bits over a 12-bit I/O
channel, the upper 12 bits will be lost.
M2 = last word address of output data block,
plus one (minus one for load backward).
00
~I~mgi~er1X
00
_c_h_",-I_~--,-I_B--JIL-:_°...1-I_e--LI_________m_l_ _ _ _ _ _ _---.JI~register OX
1
L....
00
=1~__________R_e_je_c_t_l_n_st_r_uc_t_io_n_ _ _ _ _ _ _ _ _----'1
f = operation code 73-76
INT
"1" for interrupt
m2
(see individual instruction)
Ch
1/0 channel X; where X = 0-3
NC
"1" for no BCD conversion
B
"1" for store backward
HorN = (see individual instruction)
e = "0" for operations with storage
m 1 = first character or word address of 1/0 data block; becomes current address as 1/0
operation is carried out.
3-10
75
This is a character addressed instruction. Storage words are disassembled into 6 or 12-bit characters and sent to a peripheral device (refer to
figure 3-8).
If H = 0, there is 24 to 6-bit disassembly. If
H = 1, there is 24 to 12-bit disassembly.
M2 = last character address of output data
block, plus one (minus one for load backward).
m_2_ _ _ _ _ _ _ _
23
(P
OUTC Output. Character Block from Storage f =
I~______~I_i~I_________
23
(P
18 17 16
instruction words.
Depending upon the I/O module capability, 12
or 24-bit words are read from a peripheral device
and stored in memory (refer to figure 3-7).
IfN = 0, there is 12 to 24-bit assembly. The first
word of a block is stored in the upper half of a
storage address for store forward and in the lower
half for store backward.
If N = 1, there is no assembly; a straight 12 or
24-bit data transfer occurs. A 12-bit word will be
stored in the lower half of a storage address.
M2 = last word address of input data block,
plus one (minus one, for backward storage).
INSTRUCTION
SAME
INSTRUCTION
FORMAT
AS
I NPUT ,CHARACTER
OR WORD TO A (FIGURE 3-4)
OPE RATION
H=O
I/O
MODULE
GENERATES REQUEST
IF NOT TERMINATED
WAIT
FOR BLOCK
THE N S BUS
CONTROL,
P RIO R I TY •
TESTS
NO
STORE BACKWARD?
12-;..24 BIT ASSEMBLY?
NO BCD CONVERSION?,
YES
INT=O
RELEASE BLOCK
CONTROL AND
SCA NNER
=I
I NT
-*
BCD
CONVERSION IF
NC=O
Figure 3-6. Input, Character Block to Storage
INSTRUCTION
SAME
INSTRUCTION
FORMAT
AS
INPUT ,CHARACTER
OR WORD TO A (FIGURE 3-4)
OPE RATION
N=O
I/O MODULE
GENERATES REQUEST >----...- -..........
IF NOT TERMINATED
WAIT
FOR BLOCK CONTROL,
THEN
S BUS
PRIORITY.
TESTS
NO
STORE BACKWARD?
NO ASSEMBLY? .
NO BCD CONVERSION?,
YES
INT =0
RELEASE BLOCK
CONTROL AND
SCANNER
I NT
*
BCD
CONVERSION IF
=
I
NC=O
Figure 3-7. Input Word Block to Storage
3-11
INSTRUCTION
SAME INSTRUCTION
FORMAT AS
I NPUT ,CHARACTER
OR WORD TO A (FIGURE 3-4)
OPERATION
H=O
I/O
MODULE
GENERATES REQUEST~-""1r----iOJ
IF NOT TERMINATED
WAIT FOR BLOCK CONTROL,
THEN S BUS PRIORITY.
TESTS
NO
STORE ---eAc'KWARD ?
'24~12 BIT DISASSEMBLY?
NO BCD CONVERSION?
YES
INT=O
RELEASE BLOCK
CONTROL AND
SCANNER
I NT
*
BCD
CONVERSION IF
=I
NC=O
Figure 3-8. Output, Character Block from Storage
INSTRUCTION
SAME
INSTRUCTION
FORMAT AS
I NPUT ,CHARACTER OR WORD TO A (FIGURE 3-4)
OPERATION
N=O
I/O MODULE
GENERATES REQUEST
IF NOT TERMINATED
WAIT FOR BLOCK CONTROL,
THEN S BUS PRIORITY,
~
NO
STORE BACKWARD?
NO DISASSEMBLY::> .
NO BCD CONVERSION?
YES
INT = 0
I NT
*
BCD
CONVERSION IF
=
I
NC=O
Figure 3-9. Output, Word Block from Storage
3-12
4
Operating Features
Two consoles, functionally identical to each other, are available for the 3100
computer system - the standard Integrated Console or the Optional 3101 Desk
Console. This chapter defines the switches and indicators used on these consoles
as well as explains the use of the entry keyboard. The basic differences in these
consoles lie in their physical structures; they are electrically and logically identical.
Displays and Indicators
the register displays. The 3101 desk console is electrically and logically identical to the integrated
console; however the displays and switches are located above the on-line monitor typewriter.
Seven rows of indicator lights are used to display
the operational registers of the 3104 on the integrated console. Status lights, manual controls and
a keyboard are also provided. Figure 4-1 is a view
of the integrated console and table 4-1 describes
Ul IHI . t I l t
o
A
U·'I$ I f .
IQ8o \Q8Q!o8QIQ 8oI9891c;>8 9IoSc;>io'Sol
o
IQ8;i~g~'1~8oIQ8olo8~IQ8oi ~g~i c;>891
@-=-;;-l~~~1 QQQ IQQQI O'O'QiOO'OIQQQI
•
IQQQIQQQIQO'QiQQQIOQQl
f :t.;:=..
-- IQQQ IQQQ"QQQiOQQ IQQQI
Figure 4-1. Integrated Console
4-1
Table 4-1. Register Displays
Binary
Capacity
Description
Program
Address
Counter
15 bits
Program Address register display panel.
Indexes
15 bits
Index register display panels.
Instruction
register or
Communications
register
24 bits
1) When one of the Step modes of operation
is used, the contents of the Instruction
register are shown.
2) In Stop mode, when the keyboard is active,
the contents of the Communication register
are shown.
3) In Run mode, when the keyboard is active,
the contents of the Communication register
are shown.
A and Q
registers
48 bits
Register
B'-B3
Displays the contents of each register.
On the integrated console, three indicator lights
represent each digit. The digit configuration is as
follows:
\ 1/
0
0
\1/
0
TT
4-2
(supernumeric bit)
\1/
0
IL bit 0
bit 1
bit 2
3 Cycle
Four cycles are represented: Read Next Instruction, Read Address, Read Operand, and
Store Operand. These indicators are lit whenever the cycles are in progress.
EXTERNAL STATUS INDICATORS
The external status indicators display the existing condition of I/O channels 0-3. Conditions
displayed are Read, Write, Reject, Connect,
Function, and Interrupt.
4 Faults
This column represents the four arithmetic
faults: Arithmetic Overflow, Divide, Exponent
Overflow, and Decimal (BCD-always occurs
when a BCD instruction is executed).
INTERNAL STATUS INDICATORS
Six columns of internal condition indicators are
mounted on the consoles.
Storage Active
For addressing purposes, all possible word
sections of memory are designated by digits
0-3. Digit zero indicates 4K or 8K storage.
Digits 0 and 1 indicate 16K storage and 0 to 3
32 K storage. Whenever one of these storage
sections becomes active, the corresponding
indicator light is lit.
2 Conditions
Standby means that the main power switch
is on, but individual supplies are still off.
Interrupt Disabled is lit whenever interrupt is
disabled by the 77 instruction.
5 Temp Warning, and
6 Temp High
Looking at the front of a fully expanded 3104
computer, the cabinet sections are designated by
digits 0-3 (see figure 4-2). The Temp Warning lights
indicate that the section in question is approaching
the upper limit of the normal operating temperature range of the computer. This is only a warning;
the computer is not disabled. The Temp High indicators light when the safe operating temperature
is exceeded in the sections they represent. At the
same time, the power will be cut off unless the
Thermostat Bypass switch has been pressed.
Temperature
Indicator
Temperature
Indicator
Temperature
Indicator
Temperature
Indicator
2
1
0
3
Block Control,
Interrupt,
4K Memory
and I/O
Logic.
Main Control
and Arithmetic
Logic
8K Memory,
and I/O
Logic
16K Memory
and I/O
Logic
Power
Panel
Figure 4-2. Temperature Warning Designations for Fully Expanded 3104, Front View
Svvitches
The console switches are divided into two groups
-those used for normal operation of the computer
and those used primarily for maintenance purposes.
OPERATOR SWITCHES
Operational switches are found on the mam
console and the entry keyboard.
Main Console: Table 4-2 lists and describes the
main console operator switches.
Entry Keyboard: The entry keyboard at the console
replaces the Set and Clear push buttons that are
on most CONTROL DATA computers for the
manual entry of information. Figure 4-3 shows the
3104 console keyboard. Table 4-3 lists and describes
the keyboard switches.
4-3
Table 4-2. Main Console Operator Switches
Switch Name
Quan.
Ilium.
Description
Emergency Off
(momentary)
1
Removes power from the whole system.
Breakpoint
Address
Selector
Run Mode
Selector
1
Lefthand dial of the six section, eight position
switch. Permits the selection of two modes:
2) Run Mode
1 ) Breakpoint Mode
e) OFF
a) OFF
f) Register
b) Instruction
Number*
Address
g) OFF
c) OFF
h) Storage
d) Operand Address
Address
*Registers 00000-00077 only.
Breakpoint
Address,
Register File
Number, or
Storage Address
5
Five eight position thumb-wheel switches can be
set to octal addresses 00000-77777 for modes
1 or 2 above.
Auto Load
(momentary)
1
Auto Dump
(momentary)
1
Type Load
(momentary)
1
Type Dump
(momentary)
1
Select Stop 1
1
Manual Interrupt
(momentary)
1
Select Jump 1-6
6
External Clear
(momentary)
1
Internal Clear
(momentary)
1
4-4
yes
Provides for the automatic loading of storage
from a designated device. Active whether machine
is running or stopped.
yes
Provides for the automatic dumping of storage
into a designated device. Active whether machine
is running or stopped.
yes
Provides for the loading of storage from the online liD typewriter. Active whether machine is
running or stopped.
yes
Provides for the dumping of storage into the online 1/0 typewriter. Active whether machine is
running or stopped.
yes
yes
yes
yes
Stops the computer when the Selective Stop
instruction is read.
Forces the computer into an interrupt routine if
the computer is in Run. If the computer is stopped
when the switch is pressed, it will go into an interrupt routine as soon as it is restarted.
Provides the manual conditions for executing a
program jump on the Selective Jump instruction.
Master clears all external equipments, the I/O
channels to which they are attached, and all
controls in the data channels.
Master clears internal conditions and registers.
yes
Figure 4 -3 . 3104 Console Keyboard
4-5
Table 4-3. Keyboard Switches
Operational Control Switches
Switch Name
Keyboa rd Off
Ilium.
Yes
Deactivates all keyboard controls. Disables Keyboard Active
indicator.
Clears the Communications register and keyboard control
settings.
Yes
Starts the computer at address to which P register has been
set. Indicator is lit while computer is executing instructions.
Not used for Sweep or Enter.
Yes
Enables sweep or enter operations to proceed through storage.
Yes
Brings the computer to a halt at the end of the current instruction. Indicator is lit when computer is forced to a Halt or Stop.
Keyboard Clear
(momentary)
Go
(momentary)
SW/EN
Go
(momentary)
Stop
(momentary)
Description
Transfer
(momentary)
Enables the transfer of data between the Communications
register and a selected register or storage location.
MC
(momentary)
Performs both an internal and external master clear. Disabled
when computer is in Go mode.
Register Selection Switches
Switch Name
Ilium.
Description
B1-B3
Yes
Enables the manual entry of data from the keyboard into index
registers 8'-8 3 .
P
Yes
Enables the manual entry of an address from the keyboard into
the P register.
A
Yes
Causes both A and Q to be displayed, but enables entry only
into A.
Q
Yes
Causes both A and Q to be displayed, but enables entry only
into Q.
Mode Selector Switches
Switch Name
Ilium.
Description
Enter *
Yes
Enables the manual entry of information into storage while
machine is stopped. First address of sequence is first entered
into P. Pushing Transfer advances P.
Sweep *
Yes
Enables instructions to be read from consecutive storage locations; they are not executed. First address of sequence is
first entered into P. Pushing Transfer advances P.
Write
Storage
Yes
Enables keyboard entry into the storage location specified by
the thumb-wheel switches. Entry occurs each time the Transfer key is pressed whether the computer is running or stopped.
Read
Storage
Yes
Causes the display of the contents of the storage register
location specified by the thumb-wheel switches. The word is
displayed when the Transfer key is pressed whether the
computer is running or stopped.
4-6
Table 4-3. Keyboard Switches (cont'd)
Digit and Sign Selector Switches
Switch Name
ilium.
Description
0-7
All of these buttons, when pressed one at a time, allow entry
of that particular digit into the Communications register.
(momentary)
*
All register selection switches are disabled when either the Enter or Sweep switch is depressed.
MAINTENANCE SWITCHES
Maintenance switches are all located on the
main console. Table 4-4 lists and describes the
maintenance switches.
Table 4-4. Maintenance Switches
Switch Name
Ilium.
Description
Disable Storage
Protect
Yes
Disables the circuitry that normally protects the contents
of storage.
Disable Advance P
Yes
Disables advancement of the count in the P register. When
the Go button on the keyboard is pressed, the same instruction is repeated. Press a second time to release function.
Thermostat Bypass
Yes
Allows computation to proceed regardless of unfavorable
ambient temperatures.
Disable Parity
Yes
Disables the recognition of parity errors from all storage
modules.
Instruction Step
Yes
Enables the operator to step through the
by instruction.
Storage Cycle Step
Yes
Enables the operator to step through an instruction one
storage cycle at a time.
Auto Step
Yes
Enab.les many instructions to be executed in a low speed
Run mode. The speed is regulated by the Auto Step Speed
control on the console.
~rogram
instruction
4-7
5
Repertoire of Instructions
General Information
INSTRUCTION WORD FORMATS
Instructions 00-70 and 77 use one 24-bit word
each; instructions 71-76 use two 24-bit words. In
general, the upper 6 bits hold the identifying func-
tion code 'f'. Instruction formats are of two types
-word and character. Figure 5-1 shows the general
formats for word and character oriented instructions. Instructions 70-77 use several additional
symbols that are defined when they occur.
j
rr---~A..---~
23
181716
1514
00
1",--~:.---LiID,,---------b
15
Word
a
f
1
v
d
m
k
y
23
Character
I
\
18
17
16
15 14
W
6
v
f
d
b*
00
1
17
v
r
z
Figure 5-1. General Machine Code Instruction Formats
SYMBOL DEFINITIONS
+ (B
r + (B
M =m
a = addressing mode designator (a = 0, direct addressing; a = 1, indirect addressing)
b = index designator (unless otherwise stated)
R =
K = k
b
)
b
+
)
b
(B )
In each case, ifb=O, then M=m, R=r and K=k.
d = operation designator (see individual instructions)
=
function code (6 bits, octal 00 to 77)
=
interval designator
=
jump, stop, or skip condition designator (see individual instructions)
k = shift count
m = word execution address
=
}
ADDRESSING MODES
Three modes of addressing are used in the 3100
computer: no address, direct address, and indirect
address.
unmodified
character execution address
y = 1 5-bit operand
z = 17 -bit operand
In some instructions, the execution address 'm'
or 'r', or the shift count 'k' may be modified by
adding to them the contents of an index register,
Bb. The 2-bit designator 'b' specifies which of the
three index registers is to be used. Symbols representing the respective modified quantities are M,
Rand K.
*When used in this position, 'b' calls for the use of a
specific index register.
No Address. This mode is used when an operand
'y' or a shift count 'k' is placed directly into the
lower portion of an instruction word. Symbols 'a'
and 'b' are not used as addressing mode and index
designators with any ofthe no address instructions.
Direct Address. A direct address instruction is any
instruction in which an operand address 'm' is
stored in the lower portion of the initial instruction
word. This mode is specified by making 'a' equal
to zero. In many instructions, address 'm' may be
modified (indexed) by adding to it the contents of
register Bb; M = m + (B b).
5-1
Indirect Address. It is possible to use indirect addressing only with instructions that require an execution address 'm'. For applicable instructions,
indirect addressing is specified by making 'a' equal
to one. Several levels (or steps) of indirect addressing may be used to reach the execution address;
however, execution time is delayed in direct proportion to the number of steps. The search for a
final execution address continues until 'a' equals
zero. I t is important to note that direct (or indirect)
addressing and address modification are two distinct and independent steps. In any particular instruction, one may be specified without the other.
Figure 5-2 shows the indirect addressing routine
for a 3100 computer.
Go to address M.
Acquire new
terms a, b, & m.
No
Original instruction
possibly containing
'a' and/or 'b'
Execute instruction
using address M.
No
Note: Unless it is otherwise stated, indirect addressing follows the above routine throughout the repertoire
of instructions.
Figure 5-2. Indirect Addressing Routine
READ NEXT INSTRUCTION
SEQUENCE (RNI)
An abbreviation, RNI, is used throughout the
repertoire of instructions to indicate the read next
instruction sequence. This is a sequence of steps
taken by the control section to advance the computer to its next program step. For an extensive
description of this sequence, consult the 3100
Customer Engineering Manual.
INDEX OF INSTRUCTIONS
In this chapter the instructions are grouped and
arranged in the following order. Those marked
with an asterisk are trapped instructions.
5-2
Each group of instructions is introduced with
an index as well as a group description whenever
it is necessary. Individual instructions are all presented in the same basic format:
Heading, which includes the assembly language
mnemonict and instruction name.
Machine code instruction format
Instruction description
Comments (when necessary)
Approximate instruction execution time. Add
1.75 J,lsec for indirect addressing. Instructions
shown without execution times are indeterminate at this time.
00-03
04-05,10-17
06-07, 10, 52
35-37
20-27, 54
40-47
STOP AND JUMPS
REGISTER OPERATIONS WITHOUT STORAGE REFERENCE
STORAGE TEST
LOGICAL INSTRUCTIONS WITH STORAGE REFERENCE
LOAD
STORE
INTER-REGISTER TRANSFER
24-bit Precision
53
30-31, 34, 50-51
32-33, *56-57
*60-63
*64-70
71-76
77
ARITHMETIC, FIXED POINT, 24-BIT PRECISION
ARITHMETIC, FIXED POINT, 48-BIT PRECISION
ARITHMETIC, FLOATING POINT
BCD OPERATIONS
BLOCK OPERATIONS
MISCELLANEOUS OPERATIONS
tSome assembly code mnemonics may be modified
by one or more ofthe following codes:
S
Extend sign of operand; use full 24-bit
register in skip instructions
EO
Equal
B
Backward read or write
GE
Greater than or equal
H
Half assembly or disassembly (12-24)
Indirect addressing
INT
Interrupt when completed
LT
Less than
N
No assembly or disassembly (24-24)
NE
Not equal
NC
No internal BCD conversion
Instructions
STOP AND JUMPS
Operation Field
00
HLT
SJ 1
SJ2
SJ3
SJ4
SJ5
SJ6
RTJ
Address Field
m
m
m
m
m
m
m
m
Interpretation
Unconditional stop; RN I from address 'm'
Jump if key 1 is set
Jump if key 2 is set
Jump if key 3 is set
Jump if key 4 is set
Jump if key 5 is set
Jump if key 6 is set
Return jump
01
02
UJP, I
m, b
Unconditional jump
IJI
m, b
m, b
Index jump; increment index
Index jump; decrement index
03
AZJ, EO
NE
GE
LT
AOJ, EO
NE
GE
LT
m
Compare
Compare
Compare
Compare
Compare
Compare
Compare
Compare
IJD
m
A
A
A
A
A
with
with
with
with
with
A with
A with
A with
zero; jump
zero; jump
zero; jump
zero; jump
0; jump if
0; jump if
0; jump if
0; jump if
if (A)
o
if (A) -F 0
if (A) :2: 0
if (A) < 0
(0)
(A)
(A) -F (0)
(A) :2: (0)
(A) < (0)
NOTE: Two additional Jump instructions, EZJ and EOJ, are described under the BCD instructions.
5-3
A Jump instruction causes a current program
sequence to terminate and initiates a new sequence
at a different location in storage. The Program
Address register, P*, provides the continuity
between program steps and always contains the
storage location of the current program step.
When a Jump instruction occurs, P is cleared
and a new address is entered. In most jump instructions, the execution address 'm' specifies the
beginning address of the new program sequence.
The word at address 'm' is read from storage,
placed in F, and the first instruction of the new
sequence is executed.
23
o
Format:
0
o
m
23
j
=
+
No
1
o
0
m
1 to 6
Instruction Description: Jump to address Om' if Jump
key j is set; otherwise, RNI from address P + 1.
Indirect addressing and address modification are not
applicable. (Approximate execution time: 1.8 J.ls.)
Jump key
j set?
*Throughout this manual. the term (P) refers to the
contents of the word addressed by P. This term shall
be used because the more descriptive term, ((P)).
becomes awkward when used frequently.
5-4
00
18 17 15 14
Instruction
in F
RNI from
address P
00
Instruction Description: Unconditionally stop at
this instruction. Upon restarting, RNI from address
'm'. Indirect addressing and address modification
are not applicable. (Approximate execution time:
1.8 f.1s.)
Format:
Some of the Jump instructions are conditional
upon a register containing a specific value or upon
the position of the Jump key on the console. If the
criterion is satisfied, the jump is made to location
'm'. If it is not satisfied, the program proceeds in
its regular sequence to the next instruction.
18 17 15 14
Yes
Jump to
address 'm'
o
Format:
00
18 17 15 14
23
0
Instruction Description: If b = 0, this becomes a
no-op instruction; RNI from address P + 1. If
b ~ 0, (B b) is examined.
m
7
Instruction Description: The address portion of (m)
is replaced with the return address P + 1. Jump to
location m + 1 and begin executing instructions
at that location. Indirect addressing and address
modification are not applicable. (Approximate
execution time: 3.5 f.1s.)
If (Sb) = 0, the jump test condition is not
satisfied; RNI from address P
1.
+
2 If (B ) ~ 0, the jump test condition is satisfied.
b
One is added to (B ); jump to address 'm'
and RNI.
b
Indirect addressing and jump address modification are not applicable. (Approximate execution
time: 2.6 f.1s.)
Comments: The counting operation is done in a
one's complement additive accumulator. Negative
zero is not generated because the count progresses
... , 77775, 77776, 00000, stopping at positive zero.
If negative zero is initially in Bb , the count progresses 77777, 00001, etc. In this case, the counter
must pass through its entire range to reach positive
zero.
I nstruction in F
,
p+
1 in
Store
address portion
of (m)
,
Instruction in F
Begin subroutine
with instruction
at address m
1
+
RNI from
address P
+
~
Return to 'm'
for address P
+
23
Format:
1 8 1 7 1 6 1 5 14
01
Ia I
b
00
m
Instruction Description: Unconditionally jump to
address M. Indirect addressing and indexing are
available. (Approximate execution time: 1.8 f.1s.)
23
Format:
00
18 17 16 1 5 14
02
Id I
d = 0
b = 1-3
m = jump address
b
Jump to address
'm'; RNI
m
23
Format:
00
1 8 1 7 16 15 14
02
Id I
b
m
d = 1
b = 1-3
m = jump address
5-5
Instruction Description: If b =0, this becomes a
no-op instruction; RNI from address P + 1. If
b ~ 0, (B b) is examined.
Comments: If negative zero is initially in Bb , the
count must be decremented from 77777 to 00000
before the program will RNI from P + 1.
b
1 If (B ) = 0, the jump test condition is not
satisfied; RNI from address P
1.
+
2 If (B ) ~ 0, the jump test condition is satisfied.
b
One is subtracted from (B ); jump to address
'm' and RNI.
b
Indirect addressing and jump address modification are not possible. (Approximate execution
time: 2.6 J.Ls,)
23
Format:
00
1 8 1 7 1 6 1 5 14
03
Id I
m
d=O
j = 0-3
m = jump address
Instruction in F
Instruction Description: The quantity in A is compared algebraically with zero for an equality, inequality, greater than or less than condition (see
table). If the test condition is true, the program
jumps to address 'm'. If the test condition is not
true, RNI from address P + 1. Indirect addressing
and address modification are not applicable. (Approximate execution time: 2.6 J.Ls.)
RNI from
address P
1
+
Condition
Mnemonic
EQ
NE
GE
LT
Subtract one
'from (B b)
Jump to address
'm'; RNI
j
Test Condition
°
(A)=±
(A)~±
1
2
3
(A)~+
(A)<+
Comments: Positive and negative zero give identical
results in this test when j = 0 or 1.
Instruction in F
RNI from
address P
+
5-6
No
1
°
°°
°
Is test condition
satisfied?
Yes
Jump to
address m'; RNI
23
Format:
18 17 1 6 1 5 14
Id I
03
and address modification are not applicable. (Approximate execution time: 2.6 J..ts.)
00
m
Condition
Mnemonic
d=1
j = 0-3
m = jump address
EQ
NE
GE
LT
Instruction Description: The quantity in A is compared with the quantity in Q for an equality, inequality, greater than or less than condition (see
table). If the test condition is true, the program
jumps to address 'm'. If the test condition is not
true, RNI from address P + 1. Indirect addressing
j
Test Condition
0
1
(A)=(Q)
(A) r!: (Q)
2
3
(A)«Q)
(A)~(Q)
Comments: This instruction may be used to test
the contents of Q by placing an arbitrary value
in A for the comparison. Positive and negative zero
give identical results in this test when j =0 or 1.
Instruction in F
~
RNI from
address P
+
No
1
""-
Is test condition
satisfied?
Yes
,.
Jump to
address 'm'; RNI
5-7
REGISTER OPERATIONS WITHOUT STORAGE REFERENCE
Interpretation
Address Field
Operational Field
04
ASE, S
QSE,S
ISE
y
y
y, b
Skip next instruction if (A) = y
Skip next instruction if (Q) = y
b
Skip next instruction if (B ) = y
05
ASG,S
QSG,S
ISG
y
y
y, b
Skip next instruction if (A) ~ y
Skip next instruction if (Q) ~ y
b
Skip next instruction if (B ) ~ y
14
ENA, S
ENQ,S
ENI
y
y
y, b
Enter A with y
Enter Q with y
Enter index with y
15
INA, S
INQ,S
INI
y
y
y, b
I ncrease A by Y
Increase Q by Y
Increase index by y
16
XOA, S
XOQ,S
XOI
y
y
y, b
EXCLUSIVE OR of A and y
EXCLUSIVE OR of Q and y
EXCLUSIVE OR of index and y
17
ANA, S
ANQ,S
ANI
y
y
y, b
AND of A and y
AND of Q and y
AN 0 of index and y
10
lSI
ISO
y, b
y, b
Index skip, incremental
I ndex skip, decremental
11
ECHA, S
y
Enter A with 17 -bit character address
12
SHA
SHQ
y, b
y, b
Shift A
Shift Q
13
SHAQ
SCAQ
y, b
y, b
Shift AQ
Scale AQ
(B b) and RNI from address P
execution time: 2.6 f..ts.)
23
Format:
d
=
b =
I
1 8 1 7 1 6 1 5 14
10
Id I
b
I
+
1. (Approximate
00
y
0
18 17 16
23
1 to 3
Format:
I
11
00
z
Instruction Description: If (B b) = y, clear Bb and
skip to address P + 2; if not, add one to (B ) and
RNI from address P + 1. (Approximate execution
time: 2.6 f..ts.)
b
23
Format:
18171615 14
10
Id I
b
00
y
I
d=l
b = l to 3
Instruction Description: If (B b) = y, clear Bb and
skip to address P + 2; if not, subtract one from
5-8
Instruction Description: Clear A, then enter a 17-bit
quantity'y' (usually a character address) into A.
When d = 1, the sign is extended. (Approximate
execution time: 1.8 f..ts.)
Instructions 04, OS, and 14-17 all refer to a register. Table 5-1 indicates the register and includes
the corresponding operation codes, assembly
mnemonics, and designators. When both 'd' and
'b' equal zero in instructions 04 and OS, zero is
compared with 'y' and the instructions proceed just
as if (B b) was zero. Instructions 14-17 are no-ops
when both 'd' and 'b' equal zero.
Table 5-1. Register Summary
Operation Codes and Mnemonics
04
14
05
15
16
17
d
b
Register
ISE
ISG
ENI
INI*
XOI
ANI
0
1-3
b
B , no sign extended on Bb or 'y'
ASE,S
ASG,S
ENA,S
INA,S
XOA,S
ANA,S
1
to
A, sign extension on 'y'
QSE,S
OSG,S
ENQ,S
INO,S
XOO,S
ANQ,S
1
t 1
0, sign extension on 'y'
ASE**
ASG**
ENA
INA
XOA
ANA
1
t2
A. no sign extension on 'y'
QSE**
OSG**
ENQ
INO
XOQ
ANO
1
t3
0, no sign extension on 'y'
*Sign extension on 'y' and Bb
**Only the lower 15 bits of A or Q are used.
t When d = 1, 'b' does not serve in its usual role of index designator.
23
Format:
04
I
d
I
b
Format: \
y
15
Instruction Description: If the register contents
equal 'y'; skip to address P + 2; if not, RNI from
address P + l. (Approximate execution time:
2.6 f.ls.)
00
18 17 16 15 14
05
Id I
b
Instruction Description: If the register contents are
equal to or greater than 'y' skip to address P + 2;
if not, RNI from address P + 1. (Approximate
execution time: 2.6 f.ls.)
Format:
I
18 17 16 15 14
14
Id I
b
00
18 17 16 1 5 14
16
Id I
b
y
Instruction Description: Enter the selective complement (the EXCLUSIVE OR function) of 'y' and
register contents into the register. (Approximate
execution time: 1.8 f.ls.)
23
Format:
y
See table 5-1 for 'b', 'd', and register.
y
See table 5-1 for 'b', 'd', and register.
23
b
Instruction Description: Add 'y' to the register contents. (Approximate execution time: 1.8 f.ls.)
23
Format:
\ d [
See table 5-1 for 'b', 'd', and register.
See table 5-1 for 'b', 'd', and register.
23
00
18 17 16 15 14
23
00
18 17 16 15 14
00
y
See table 5-1 for 'b', 'd', and register.
Instruction Description: Clear the register and enter
'y' directly into the register. (Approximate execution time: 1.8 f.ls.)
00
18 1 7 1 6 1 5 14
Format:
y
See table 5-1 for 'b', 'd', and register.
Instruction Description: Enter the logical product
(the AND function) of 'y' and the register contents into the register. (Approximate execution
time: l.8 f.ls.)
5-9
the complement of the magnitude of shift is placed
in ok'.
23
Format:
d
d
b
=
=
=
I
Examples: (b = 0 in both cases):
00
1817161514
k
12
O,SHA
1. SHQ
index designator; K
Shift left six positions:
k
=
00006
Shift right six positions:
k =
77771
(Approximate execution time: 1.8 to 3.8 f.ls.)
=
k
+
(B
b
).
Instruction Description: (B b) and k, with their signs
extended, are added. (Even if b=O, the sign of ok'
is still extended.) The sign and magnitude of the
24-bit sum determine the direction and magnitude
of shift. The computer only senses bits 00-05 and 23
of the sum for this information. To shift left, the
magnitude of shift is placed in 'k'; to shift right,
Comments:
During left shifts, bits reaching the top of the A
or Q register are brought end around. Therefore,
a left shift of 24 places results in no change in (A)
or (Q); a left shift of greater than 24 places results
in an effective shift of K-24 (or K-48) places.
During right shifts, the sign bit is extended and the
low order bits are discarded. A right shift of 23 or
more places results in (A) or (Q) becoming all "O's"
or all .. 1's", depending on the sign.
Instruction in F
No
Yes
b
Add (B ) to k
with sign ext.
Sign of k is
extended
"0"
Uppermost
bit of result equals
"0" or "1 "?
"1"
Shift will
be left
Shift will
be right
"0"
"1"
RNI from
address P
+
5-10
23
Format:
I
00
18 17 16 1 5 14
Id I
13
I
b
d=O
b = index designator; K = k
k
+ (B b )
Instruction Description: The contents of A and Q
are shifted together as one 48-bit register. (B b) and
'k', with their signs extended, are added. (Even if
b = 0, the sign of ok' is still extended.) The sign
and magnitude of the 24-bit sum determine the
direction and magnitude of shift. The computer
only senses bits 00-05 and 23 of the sum for this
information. To shift left, the magnitude of shift
is placed in ok'; to shift right, the complement of the
magnitude of shift is placed in 'k'.
Examples: (b = 0 in both cases):
Shift left three places:
k = 00003
Shift right three places:
k = 77774
(Approximate execution time: 2.6 to 5.1 J.ts.)
Comments:
During left shifts, bits reaching the top of the A
register are brought end around to the lowest bit
of Q. Therefore, a left shift of 48 places results in
no change in (AQ); a left shift of greater than 48
places results in an effective shift of K-48 places.
During right shifts, the sign bit is
the low order bits are discarded. A
47 or more places results in (AQ)
"O's" or all '"I 's", depending on the
I
00
1817161514
23
Format:
extended and
right shift of
becoming all
sign.
k
13
d=1
b = index designator
K = k-shift count; (K~ B
b
)
Instruction Description: (AQ) is shifted left end
around until the highest 2 bits (46 and 47) are unequal. If (AQ) should initially equal positive or
negative zero, 48 decimal (60 octal) shifts are executed before the scale instruction terminates.
During scaling, the computer makes a shift count.
A quantity 'K', called the residue, equals ok' minus
the shift count. If b = 0, this quantity is discarded;
ifb = 1 to 3, the residue is placed in index Bb. (Approximate execution time: 2.6 to 5.1 J.ls.)
STORAGE TEST
Operation Field
Address Field
Interpretation
Masked equality search
06
07
MEQ
m, bl
MTH
m, b2
Masked threshold search
10
SSH
m
Storage shift
52
CPR,1
m, b
Compare (within limits test)
If A = Q.M, RNI from P
quence.
18 17 15 14
23
Format:
I
I
06
I
00
(Approximate execution time: 3.5 J.lS + n*-l.8 J.ls.)
Instruction Description: This instruction uses index
m + (HI). (A) is compared
with the logical product of (Q) and (M).
Instruction Sequence:
Comments: 'i' is represented by 3 bits allowing a
decrement interval selection of 1 to 8.
B1 exclusively. M =
Decrement (Bl) by T.
Test to see if (Bl) changed sign from positive to
negative.
*n
=
+
1; if not. test to see if A=Q.M.
number of words searched
2; if not. repeat se-
m
i = 0 to 7, interval designator
m = unmodified storage address
If so, RNI from P
+
interval
1
1
2
3
2
3
4
4
5
6
7
0
5
6
7
8
5-11
Decrement
(8 2 ) by 'j'
Decrement
(B1) by 'j'
RNI from
P+1
RNI from
P+1
RNI from
P
23
Format:
18171514
07
Yes
A;:::::O·M
+2
23
00
Format:
m
i = 0 to 7, interval designator
m = unmodified storage address
RNI from
P+2
18171514
10
o
00
m
m = storage address
Instruction Description: This instruction uses index
B2 exclusively. M = m +·(B2). (A) is compared with
the logical product of (Q) and (M).
Instruction Sequence:
Decrement (B2) by 'i'.
Instruction Description: Sense bit 23 of (m). If (m)
is negative, RNI from P + 2; if positive, RNI from
P + 1. In both cases, shift (m) one place left, end
around, and replace it in storage. (Approximate
execution time: 5.3 j.l.s.)
Test to see if (8 2 ) changed sign from positive
to negative.
If so, RN I from P + 1; if not, test to see if
A;:::::O.M.
If A;::::: O. M,
sequence.
RNI from P+2; if not repeat
(Approximate execution time: 3.5 j.l.S
j.l.s.)
+
n*-1.8
RNI from
P+2
Comments: 'i' is represented by 3 bits allowing a
decrement interval selection of 1 to 8.
interval
1
1
2
3
2
3
4
5
6
4
5
6
7
o
7
8
*n = number of words searched
5-12
RNI from
P+1
Shift m) one
Place left end
around, and replace
23
Format:
00
18 17 16 15 14
52
Ia I
b
m
a = addressing mode designator
b = index designator
m = storage address
Instruction Description: (M) is tested to see if it is
within the limits specified by A (upper limits) and
Q (lower limits). The sequence of comparisons and
the action taken are as follows:
Subtract (M) from (A) and place the difference
in A. If A is negative, R N I from address P
1;
if not,
+
2 Subtract (Q) from (M) and place the difference
in A. If A is negative, R N I from address P 2;
if not,
+
3 RNI from address P
+ 3.
Final State of Registers: (A) and (Q) remain unchanged. The address to which control proceeds,
upon completion of the instruction is given by the
following table:
LOGICAL INSTRUCTIONS WITH
STORAGE REFERENCE
Operation
Address
Field
Field
Interpretation
35
SSA I
m, b
Selectively set A
36
SCA I
m, b
Selectively complement A
37
LPA I
m, b
Logical product A
23
00
18 1 7 1 6 1 5 14
Ia I
Format: r=;5
m
b
a = addressing mode designator
b = index designator
b
m = storage address: M = m
(B )
+
Instruction Description: Selectively set" 1's" in A
for all "1 's" at address M. (Approximate execution time: 3.5 f.1s.)
23
Format:
18 1 7 1 6
00
1 5 14
-LI_a-L1__b__~______m______~
3_6__
L I_ _ _
a = addressing mode designator
b = index designator
b
m = storage address; M = m
(B )
+
Condition
Control
Given To
(M»(A)
(Q) >(M)
(A) :2: (M):2: (Q)
Instruction Description: Selectively complement
corresponding bits in A for all HI's" at address M.
(Approximate execution time: 3.5 f.1s.)
P+3
23
Format:
00
18 17 16 15 14
37
m
a = addressing mode designator
b = index designator
b
m = storage address; M = m
(B )
+
Instruction Description: Replace A with the logical
product of (A) and (M). (Approximate execution
time: 3.5 f.1s.)
5-13
LOAD
Interpretation
Address Field
Operation Field
m, b
Load A
LOO,I
m, b
Load 0
LACH
m,8 1
Load A, Character
23
24
25
LOCH
m, 8 2
Load 0, Character
LACM,I
m, b
Load A. Complement
LOAQ,I
m, b
Load AQ
26
27
54
LAOC, I
m, b
Load AO, Complement
LOL.l
m, b
Load A, Logical
LOl.l
m, b
Load Index
20
21
LOA. I
22
23
Format:
00
18 1 7 16 1 5 14
20
m
Instruction Description: Load bits 0 to 5 of A with
the character from storage specified by character
address R. A is cleared prior to the load operation.
(Approximate execution time: 3.5 f..Ls.)
Comments: Indirect addressing is not applicable.
Characters in storage are specified in the following
manner:
a = addressing mode designator
b = index designator
b
m = storage address; M = m
(8 )
+
23
Instruction Description: Load A with a 24-bit quantity from storage address M. (Approximate execution time: 3.5 f..Ls.)
12 11
18 17
o
Ia I
Format:
b
23
m
:16
+
l. ._0_0_00_0_-....,7:~7_77
Comments: Indirect addressing and address modification are available.
18 17 16
00
22
02 01 00:
word address
b = index designator. If b
b = index designator. If b = 1, 'r' is modified by
index register 8 1 ; R = r
5-14
+ (8
1
).
~
character
designator
modified by
+ (8 2 ).
Instruction Description: Load bits 0 to 5 of Q with
the character from storage specified by character
address R. Q is cleared prior to the load operation.
(Approximate execution time: 3.5 f..Ls.)
Comments: Indirect addressing is not applicable.
Characters in storage are specified in the following
manner:
23
character
designator
= 1, r is
index register 8 2 ; R = r
18 17
12 11
06 05
v
word address
020100:
__
Instruction Description: Load Q with a 24-bit quantity from storage address M. (Approximate execution time: 3.5 f..Ls.)
Format:
00
18 17 16
a = addressing mode designator
b
b = index designator; M = m
(8 )
m = storage address
23
3
00
18 1 7 1 6 1 5 14
21
I
2
23
Format:
00
~~
/~
character designators
Comments: Indirect addressing and address modification are available.
23
06 05
o
2
I
00
3
~~/~
character designators
23
00
18 1 7 16 1 5 14
Format:
24
Ia I
b
m
Instruction Description: Load registers A and Q
with the complement of the two words from addresses M and M + 1, respectively. (Approximate
execution time: 5.2 J.ls.)
a = addressing mode designator
b = index designator
m = storage address; M = m + (B b )
23
Instruction Description: Load A with the complement of a 24-bit quantity from storage address M.
(Approximate execution time: 3.5 J.ls.)
Comments: Indirect addressing and address modification are available.
Format:
00
18 17 16 15 14
23
25
Format:
00
18 1 7 16 1 5 14
26
I
Ia I
27
I
b
m
a = addressing mode designator
b = index designator
Instruction Description: Load A with the logical
product (the AND function) of (Q) and the contents of address M. (Approximate execution time:
3.5 J.ls.)
m
a = addressing mode designator
b = index designator
b
m = storage address; M = m + (B )
Instruction Description: Load registers A and Q
with the two words from addresses 'M' and M + 1,
respectively. Address 77777 should not be used.
(Approximate execution time: 5.2 J.ls.)
23
Format:
00
18 1 7 1 6 1 5 14
Ia I
Format:
00
18 1 7 16 1 5 14
54
Ia I
b
I
m
a = addressing mode designator
b = index designator
m = storage address
Instruction Description: Load index register Bbwith
the lower 15 bits of storage address 'm'. (Approximate execution time: 3.5 J.ls.)
Comments: Indirect addressing, but no address
modification, is possible. During indirect addressing only 'a' and 'm' are inspected. Symbol 'b' from
the initial instruction specifies which index register
is to be loaded with the storage address contents.
m
b
23
a = addressing mode designator
index designator
m = storage address; M = m + (B b )
b=
STORE
Operation Field
40
41
42
43
44
45
46
47
a
=
STA, I
STQ, I
SACH
SQCH
SWA,I
STAQ,I
SCHA
STI.I
=
m, B2
m, B1
m, b
m, b
m, b
m, b
00
40
m
addressing mode dflsignator
storage address; M
Store
Store
Store
Store
Store
Store
Store
Store
m, b
b = index designator
m
Interpretation
m, b
18 17 16 15 14
23
Format:
Address Field
=
m
+
b
(B )
Instruction Description: Store (A) in storage address
M. (Approximate execution time: 3.5 J.ls.)
a
b
m
=
=
=
I
00
18 17 16 15 14
23
Format:
A
Q
2.5 J.lsec
A, character
Q, character
1 5-bit word address
AQ
)- 3.8 J.lsec
17 -bit character address}
index
2.5 J.lsec
41
Ia I
b
I
m
addressing mode designator
index designator
b
storage address; M = m + (B )
Instruction Description: Store (Q) in storage address M. (Approximate execution time: 3.5 fJ,s.)
5-15
23
Format:
00
18 17 16
4_2__
L I_ _ _
23
_____________________~
~I_b~I
Format:
I
r
I
116
020100
1
!iJ
'-----y===:;9
character
designator
Instruction Description: Store the contents of bits
to 5 of the A register in the specified character
address. All of A and the remaining three characters
in storage remain unchanged. (Approximate execution time: 3.5 f.ls.)
°
o
~
12 11
1
I
2
45
1
00
43
: 16
8
02 01 00
[00000-:7777
word address
I
Instruction Description: Store the contents of bits
to 5 of the Q register in the specified character
address. All of Q and the remaining three characters in storage remain unchanged. (Approximate
execution time: 3.5 f.ls.)
°
Comments: Indirect addressing is not applicable.
Characters in storage are specified in the following
manner:
18 17
12 11
0605
00
I,----------=:-o---,---I------::-1----,--I------,,2---'---~~3
-------char~ d~tors
------l
5-16
a
=
b
=
m
=
)
Ia I
b
00
m
18 17 16 15 14
46
1
a
1
b
00
m
addressing mode designator
index designator
b
storage address; M = m + (B )
Instruction Description: Store the lower 17 bits of
(A) in the designated address M. The upper bits of
M remain unchanged. (Approximate execution
time: 3.5 f.ls.)
character
designator
b = index designator. If b = 1, r is modified by
index register 8 1 ; R = r + (8 1 ).
23
b
Instruction Description: Store the contents of registers A and Q in storage addresses M and M + I,
respectively. Address 77777 should not be used.
(Approximate execution time: 5.2 f.ls.)
Format:
Format:
(8
a = addressing mode designator
b = index designator
b
m = storage address; M = m + (8 )
~3
18 17 16
m
b
18 17 16 15 14
23
23
1
= addressing mode designator
Format:
00
06 05
a
b = index designator
23
Comments: Indirect addressing is not applicable.
Characters in storage are specified in the following
manner:
18 17
I
00
Instruction Description: Store the lower 15 bits of
(A) in the designated address M. The upper 9 bits
of M remain unchanged. (Approximate execution
time: 3.5 f.ls.)
b = index designator. If b = 1, r is modified by
index register 8 2 ; R = r+ (8 2 ).
23
44
m = storage address; M = m +
00000-77777
word address
a
18 17 16 15 14
23
Format:
18 17 16 15 14
47
00
m
a = addressing mode designator
b = index designator
m = storage address
Instruction Description: Store the (B b) in the lower
15 bits of storage address 'm'. The upper 9 bits of
om' remain unchanged. (Approximate execution
time: 3.5 f.ls.)
Comments: Indirect addressing, but no address
modification, is possible. During indirect addressing only 'a' and Om' are inspected. Symbol 'b' from
the initial instruction specifies which index register
is to have its contents stored. If b = 0, zeros are
stored in m.
INTER-REGISTER TRANSFER 24-Bit Precision
53
Interpretation
Address Field
Operational Field
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
b
b
m
m
m
m
m. b
m. b
TIA
TAl
TMO
TOM
TMA
TAM
TMI
TIM
AOA
AlA
b
b
IAI
b
(B ) to A
(A) to Bb
(Register m) to 0
(0) to Register m
(Register m) to A
(A) to Register m
(Register m) to Bb
b
(B ) to Register m
(A)
(0) to A
b
(A)
(B ) to A
b
(B )
(A) to Bb
+
+
+
The 53 instruction is used to move data between
the A and Q (arithmetic) registers, the index registers, and the register file.
23
Format:
18 17 16 15 14 12 11
23
Format:
I
00
18 1 7 1 6 1 5 14 12 11
53
23
3
I
Format:
18 17 15 14 12 11
53
23
23
Format:
18 1 7 16 1 5 14 12 11 06 05 00
53
v
Format:
v
18 17 16 15 14 12 11
53
Id 1-- - I 2 I
O,TMA; d = 1,TAM
register number. 00-77
00
4
53
23
18 1 7 1 6 1 5 14 12 11
4
Instruction Description: The sign of (B b) is extended.
O. TMO; d = 1. TOM
register number. 00-77
23
o
00
b = index designator. 1 to 3
Format:
d
v =
I
53
Comment: No sign extension.
Format:
b
00
d = 0, TMI; d = 1. TIM
b = index designator, 1 to 3
v = register number. 00-77
d= O. TIA; d = 1. TAl
b = index designator. 1 to 3
d
v -
Id I
06 05
06 05
00
v
18 17 16 15 14 12 11
53
00
4
b = index designator. 1 to 3
Instruction Description: The sign of the original
(B b ) is extended prior to the addition. The upper 9
bits are lost when the sum is placed in Bb.
5-17
ARITHMETIC, FIXED-POINT, 24-BIT PRECISION
Operation Field
Address Field
Interpretation
30
ADA I
m, b
Add to A
31
SBA I
m, b
Subtract from A
34
RAD, I
m, b
Replace add
50
MUA I
m, b
Multiply A
51
DVA I
m, b
Divide A
Format:
00
18 1 7 16 15 14
23
30
Ia I
b
I
m
Instruction Description: Replace the quantity in M
with the sum of (M) and (A). The original (A)
remain unchanged. (Approximate execution time:
5.2 f.1s.)
a = addressing mode designator
b = index designator
b
m = storage address; M = m
(B )
+
Instruction Description: Add a 24-bit quantity
located at address M to (A). The sum appears in
A. (Approximate execution time: 3.5 f.1s.)
Format:
00
18 17 16 15 14
23
Ia I
50
m
b
a = addressing mode designator
b = index designator
b
m = storage address; M = m
(B )
+
23
Format:
00
18 1 7 16 1 5 14
31
Ia I
m
b
Instruction Description: Multiply (A) by the quantity at address M. The 48-bit product appears in
QA with the lowest order bits in A. (Approximate
execution time: 14.5 f.1s.)
a = addressing mode designator
b = index designator
b
m = storage address; M = m
(B )
+
Instruction Description: Subtract a 24-bit quantity
located at address M from (A). The difference appears in A. (Approximate execution time: 3.5 f.1s.)
23
Format:
00
18 1 7 1 6 15 14
34
IaI
m
b
a = addressing mode designator
b = index designator
m = storage address; M = m
+ (B
b
18 17 16 15 14
23
)
Format:
51
lal
b
m
a = addressing mode designator
b = index designator
b
m = storage address; M = m
(B )
+
Instruction Description: Divide the 48-bit quantity
in AQ by the quantity at storage address M. The
quotient appears in A and the remainder with its
sign extended appears in Q. If a divide fault occurs,
this operation halts and the program advances to
the next instruction. The final contents of A and Q
are meaningless if this happens. (Approximate
execution time: 15.0 jLs.)
ARITHMETIC, FIXED-POINT, 48-BIT PRECISION
Operation Field
5-18
Address Field
00
Interpretation
32
ADAQ, I
m, b
Add to AQ
33
SBAQ, I
m, b
Subtract from AQ
56
MUAQ, I
m, b
Multiply AQ {
57
DVAQ, I
m, b
Divide AQ
\
Trapped
Instructions
Comments: Instructions 56 and 57 are trapped in
3100 computer systems.
Instruction Description: Subtract the 48-bit combined contents of addresses M and M + 1 from
(AQ). The difference appears in AQ. (Approximate
execution time 5.2 f.,ls.)
Registers A and Q serve together as a 48-bit
register with the highest order bits in A.
23
Format:
23
Format:
a
b
m
=
=
=
I
00
18 1 7 16 15 14
32
Ia I
00
18 17 16 15 14
Ia I
56
b
I
m
a = addressing mode designator
b = index designator
m = storage address; M = m
(Sb)
+
m
b
Instruction Description: M uitiply (AQ) by the 48bit operand in M and M + 1. The 96-bit product
appears in AQE.
addressing mode designator
index designator
storage address; M = m
(Sb)
+
Instruction Description: Add the 48-bit contents of
addresses M and M + 1 to (AQ). The sum appears
in AQ. (Approximate execution time: 5.2 f.,ls.)
23
Format:
00
18 17 1 6 1 5 14
57
Ia I
m
b
a = addressing mode designator
b = index designator
m = storage address; M = m
(Sb)
+
23
Format:
a
b
m
I
18 17 16 15 14
33
Ia I
b
00
I
m
addressing mode designator
index designator
= storage address; M = m
(Sb)
=
=
+
Instruction Description: Divide (AQE) by the 48bit contents of addresses M and M + 1. The
answer appears in AQ and the remainder with its
sign extended appears in E. If a divide fault occurs,
this operation halts and the program advances to
the next instruction. The final contents of AQ and
E are meaningless if this happens.
ARITHMETIC, FLOATING POINT
Operational Field
Address Field
Interpretation
60
FAD, I
m, b
FP addition to AQ
61
FSB, I
m, b
FP subtraction from AQ
62
FMU, I
m, b
FP multiplication of AQ
63
FDV, I
m, b
FP division of AQ
This group of instructions is trapped in 3100
computer systems. The E and 0 registers are simu-
lated in 3100 memory by appropriate software and
are not separate physical entities.
Comments: All floating point operations in the 3100
computer involve the A and Q registers plus two
consecutive storage locations, 'm' and m + 1. The
A and Q registers are treated as one 48-bit register.
Operand Formats: The AQ register and the storage
address contents have identical formats.
5-19
(47)
(46)
(36)
(35)
(24)
23
22
12
11
00
(A) and (M)
11-bit o¥and
exponent including
bias
Sign of
Coefficient
Upper 1Ybits of
operand coefficient
23
(Q) and (M
+
00
I
1)
I
\~----------~-------------- ~----------------------------}
Lower 24 bits o~erand coefficient
Exponent Equalization: During floating point addition and subtraction, the exponents involved are
equalized prior to the operation. The coefficient of
the algebraically smaller exponent is automatically
shifted right until the exponents are equal.
Rounding: Rounding modifies the coefficient answer by adding one to AQ for positive answers or
by subtracting one for negative answers. Rounding
is necessary since the coefficient answer may contain more than 36 bits. The condition for rounding
is inequality of the sign bits of AQ and E. This
means that the next lower significant bit to the right
of the number in AQ is equal to or greater than
one-half. Coefficient arithmetic may, yield rounded
answers from zero to 237.
Normalizing: Normalizing brings the above answer
back to a fraction from one-half to one with the
binary point to the left of the 36th bit. The magnitude of the final normalized number in AQ will
range from 236 to 237_l. Normalizing is performed
by either a right shift or the required number of left
shifts for add and subtract or a one place right or
left shift for multiply and divide. The exponent is
corrected for every shift. The residue in E is not
shifted.
Exponent Overflow: It is possible to sense exponent
overflow and/or to use this overflow to cause an
interrupt. Sensing this fault automatically clears
the Exponent Overflow indicator.
23
Format:
60
Ia I
b
I
m
a = addressing mode designator
b = index designator
m = storage address; M = m
(Sb)
+
5-20
00
18 1 7 1 6 1 5 14
Instruction Description: Add the contents of M and
M + 1 to (AQ). The rounded and normalized sum
appears in A Q.
23
Format:
I
18 17 16 15 14
00
m
61
a = addressing mode designator
b = index designator
m = storage address; M = m
(Sb)
+
Instruction Description: Subtract the 48-bit contents of 'M' and M + 1 from (AQ). The rounded
and normalized difference appears in AQ.
23
Format:
00
18 17 16 15 14
62
Ia I
m
b
a =
b =
rn
addressing mode designator
index designator
= storage address; M = m
(Sb)
+
Instruction Description: Multiply (AQ) by the 48bit contents of 'M' and M + 1. The rounded and
normalized product appears in AQ.
23
Format:
[63
00
1 8 1 7 1 6 1 5 14
Ia I
m
b
a = addressing mode designator
b = index designator
m = storage address; M = m
(Sb)
+
Instruction Description: Divide
bit contents of M and M + 1.
normalized quotient appears in
der with sign extended appears
(AQ) by the 48The rounded and
AQ. The remainin the E register.
BCD
Address Field
Operational Field
Interpretation
70
SFE
EZJ, EQ
EZJ, LT
EOJ
SET
k, b
m
m
m
y
Shift E
E zero jump, E = 0
E zero jump, E < 0
E overflow jump
Set D register
64
LDE
m, b 1
Load E
b2
65
STE
m,
66
ADE
m, b 3
Addition to E
67
SBE
m, b 3
Subtraction from E
Store E
This group of instructions is trapped in 3100
computer systems. The E and D registers are simulated in 3100 memory by appropriate software
and are not separate physical entities.
Formats: These instructions handle 4-bit BCD
characters rather than whole 24-bit words. These
characters are placed into the simulated E register
and into storage in the following ways:
Illegal Characters: By definition, any character
greater than 9 (or lIs) is illegal. Characters are
tested for legality during:
1 Loading into E,
2 Storing as they leave E, and
3 Addition and subtraction as they leave E and
storage for processing by the adder.
BCD Fault: The BCD fault will occur if:
1 ED Register (Simulated Configuration).
53 51
I±
..
00
11 3 11 211 1 11 0
+'
I 91817161 5 1413121
y
Sign Overflow
of E character
position
2 An illegal character is sensed during the execution of an instruction, or
/
3 The contents of D exceed 12 (will set only
BCD Characters
during a SET instruction).
The simulated 53-bit ED register can hold 12
regular BCD characters plus one overflow
character. The ED register can never be displayed on the consoles.
2 Storage
23
(M) =
A sign is present in any character position
other than the least significant, or
18 17
12 11
06 05
00
IL-_O_-l-I_-.l..._2------L1----;-3-----i
"'"
~ Character
/
Positions
/
Each 24-bit storage word may be divided into
four character positions of 6 bits each. The
lower 4 bits of each position may hold a 4bit character; the upper 2 bits are reserved
for the sign designator, one per field. For each
field, the sign accompanies the least significant character. 10xxxx specifies negative;
any other combination, positive. The upper 2
bits of all other characters in the field must
equal zero. The most significant character
precedes the least significant character of a
field in storage.
Field Length: The field length is specified by the
contents of the simulated 4-bit D register. Any
number 1-12 (0001-1100) is legal.*
23
Format:
00
18 1 7 1 6 1 5 14
70
Id I
b
k
d= 0
b = index designator
k = shift designator
Instruction Description: This instruction shifts BCD
characters within the E register in one character
(4-bit) steps. 'k' and the contents of index Bb are
added to modify the shift designator; K = k + (B b).
The computer senses bits 00-03 and 23 of the sum.
*Although a fault will occur, D may equal 13 for the
storage of 13 characters. The following sequence
should be followed in storing 13 characters:
1 Set D (BCD fault will occur)
2 Sense for BCD fault (this clears the BCD Fault
indicator
3 Issue STE instruction
If the BCD fault is disregarded and there is an attempt
to load, add, or subtract 13 characters, only the lower
12 characters will be used. No additional fault will
occur.
5-21
Direction of Shift: Shifting is left if bit 23 is zero;
right if it is one. Shifts are end off in both directions.
Magnitude of Shift: For a left shift, the lower 4 bits
of the sum specify the shift magnitude; for a right
shift, the lower 4 bits of the complement of the sum
specify the shift magnitude.
23
Format:
Examples:
If K =
until a new quantity is entered. In other words,
during a series of load and store operations dealing
with equal size fields, (D) need only be set once.
00
18 17 16
Ib
64
I
00000006, shift left 6 character positions.
If K = 77777771, shift right 6 character positions.
Character
position
within the
word
If b=O, r is the unmodified direct address.
If b=l, r is modified by (B1); R=r+(B1).
Word
Address
23
Format:
I
00
18 1 7 16 1 5 14
Id I
70
m
d=l
j = jump test designator
m = jump address
Instruction Description: This instruction compares
(E) with zero. If the test condition is true, jump to
address m; if not, RNI from address P + 1. See the
table below for test conditions.
Mnemonic
Test Condition
o
EQ
Instruction Description: Load the 53-bit ED register
(includes sign of ED) with a field of up to 12 numeric BCD characters from storage. Characters
are read consecutively, starting with the least significant character (at address R + (D - 1) and
continuing until the most significant character (at
address R) is in ED. (ED) is shifted right as loading
progresses. The sign is acquired along with the
least significant character. Before executing this
instruction, specify field length with a SET (70.7)
instruction.
(E) = 0
LT
(E)
<0
23
Format:
23
Format:
!
70
I
65
Ib I
If b=O, r is the unmodified direct address.
If b=l, r is modified by the (B2); R=r+ (B2).
m
6
I
00
00
15 14
18 17
18 17 16
m = jump address
Instruction Description: Jump to address 'm' if digit
13 of the ED register receive a character indicating
that ED has overflowed; if not, RNI from address
P + 1.
23
Format: I
18 17
70
15 14
7
00
23
y
y = field length designator
Instruction Description: Place the lower 4 bits of 'y'
in the simulated 4-bit D register. (D) remains set
5-22
Instruction Description: Store a field of up to 13
numeric BCD characters from the 53-bit ED register (includes sign of ED). Storage begins with the
least significant character and the sign. As it continues, (E~) is shifted right, end off, until the field
is stored. Before executing this instruction, specify
field length with a SET (70.7) instruction.
Format:
I
18
66
17
16
Ib I
If b = 0, r is the unmodified direct address.
If b=l, r is modified by (B3); R=r+(B3).
00
Instruction Description*: A field of up to 12 stored
numeric characters may be added to (ED). The sum
appears in ED. Stored characters are in consecutive
character positions of adjacent storage addresses.
'R' specifies the most significant character of a field.
The 4-bit D register specifies field length.
23
Format:
18
17
00
16
67 I b I
If b=Q, r is the unmodified direct address.
If b= 1. r is modified by (B3); R=r
(B3).
+
Instruction Description*: A field of up to 12 stored
numeric characters may be subtracted from (ED).
See instruction 66 for remainder of description.
BLOCK OPERATIONSSEARCH, MOVE, AND I/O
Operation Field
Address Field
Interpretation
71
SRCE,INT
SRCN,INT
c, m
c, m 1 , m 2
72
73
MOVE,INT
c, m 1 • m 2
INPC,NC.INT,B,H
INAC,NC.INT
ch, m
ch
74
INPW,NC,INT,B,N
INAW,NC.INT
ch, m 1 , m 2
ch
Input, word block to storage
I nput, word to A
75
OUTC,NC.I NT,B.H
OTAC,NC,INT
ch. m 1 , m 2
ch
Output, character block from storage
Output, character from A
76
OUTW.NC,INT.B,H
OTAW.NC,INT
1•
m2
1•
m
Search character equality
Search character inequality
Move c characters from m 1 to m 2
2
Input, character block to storage
Input, character to A
Output, word block from storage
Output, word from A
Comments: These instructions have the following
characteristics in common:
They are composed of three words, including
the two main block instruction words plus a
one word reject instruction.
2 Addresses required for the execution of the
instruction set are located within the instruction set.
3 Constants such as field lengths and BCD codes
for search characters are within the instruction set.
4 They can all be set to cause an interrupt upon
completion.
See chapter 3, Programming Features, for a
description of the Block instructions.
*The A and Q registers are not used for these instructions.
5-23
SENSING, CONTROL AND INTERRUPT
Operation Field
Address Field
Interpretation
77.0
CON
x. ch
connect
77.1
SEl
x. ch
select
77.2
COpy
x. ch; x = 0
copy external status
77.2
EXS
x. ch; x
77.3
CINS
x. ch; x = 0
77.3
INS
x. ch; x
77.4
INTS
x. ch
interrupt sense
77.50
INCl
x
interrupt clear
77.51
10Cl
x
1/0 clear
77.52
SSIM
x
selectively set interrupt mask
77.53
SCIM
x
selectively clear interrupt mask
77.57
IAPR
77.6
PAUS
pause
77.70
SlS
selective stop
77.71
SFPF
*set FP fault
77.72
SBCD
*set BCD fault
77.73
DINT
77.74
EINT
enable interrupt control
77.75
CTI
console typewriter in
~
~
0
external sense
copy internal status
internal sense
0
interrupt associated processor
disable interrupt control
77.76
CTO
console typewriter out
77.77
UCS
unconditional stop
Comments: 77 is an instruction that handles sensing, selecting, interrupt and control functions not
covered by instructions 00-76.
23
18
Format:
15
17
14
The general format for all sub-divisions of the
77 instruction is:
12
11
0-7
Operation
Code
0000-7777
Channel designator
or special usage
Operation
Code
Modifier
Comparison mask.
function code. etc.
Throughout this instruction, the term Busy may
mean:
channel writing.
channel reading.
1/0 equipment Reject on channel.
last Connect on channel not yet recognized. or
last Function on channel not yet recognized.
*Used for software simulation of the optional arithmetic packages.
5-24
00
23
Format:
00
18 17 1 5 14 12 11
77
o
c
xxxx
c-= 1/0 channel designator 0-3.
xxxx = 12-bit connect code. Bits 09-11 select one
of eight controllers which may be attached
to the selected channel. Bits 00-08 select
one of a possible 512 units which may be
connected to the .selected controller.
Instruction Description: Channel c is checked for
Busy. If Busy is present, a reject instruction is read
from address P + l. If channel c is not Busy, a 12bit connect code is sent on channel c along with a
connect enable; then the next instruction is read
from address P + 2.
23
Format:
23
c
xxxx
=
=
c
xxxx
I/O channel designator 0-3.
12-bit function code. Each piece of peripheral equipment has a unique set of function
codes to specify operations within that device. Refer to the individual peripheral
equipment manuals for these codes.
Instruction Description: Channel c is checked for
Busy. If Busy is present, a reject instruction is read
from address P + 1. If channel c is not Busy, a 12bit function code xxxx is sent on channel c along
with a function enable; then the next instruction is
read from address P + 2.
mask. Bits 00-03 of the mask represent interrupt lines from the designated I/O
channel; bits 08-11 represent internal interrupt conditions.
Instruction Description: Sense for the interrupt
conditions listed in table 5-4. If" 1" bits appear on
the interrupt lines in any of the same positions as
"1" bits in the mask, RNI from address P + 1. If
comparison does not occur in any of the bit positions, skip to address P + 2. Internal interrupts
are cleared as soon as they are sensed.
Table 5-4. Interrupt Sensing Mask
Comparison Mask
Bit Positions
Definitions
I/O line 0-3 interrupt active
00-07
Clock interrupt
*08
1817
23
Format:
I
77
I
2
1514
1211
I
I
ch
00
xxxx
= sense
00
18 1 7 1 5 14 12 11
77
77
ch = I/O module, channels 0-3.
xxxx
Format:
00
18 17 15 14 12 11
*09
Exponent overflow or BCD fault
*10
Arithmetic overflow or divide fault
* 11
Search/move completion interrupt
0000
ch = I/O channel designator 0-3
Instruction Description: This is a dual purpose instruction:
A The external status code from I/O channel C is
loaded into the lower 12 bits of A.
B The contents of the Interrupt Mask register are
loaded into the upper 12 bits of A. See Table 5-4.
RNI from address P
1.
+
23
Format:
00
18 17 15 14 12 1 1
77
5
o
xxxx
Instruction Description: The interrupt faults defined
by xxxx are cleared (see table 5-5). N ate that only
internal I/O channel interrupts are cleared by this
instruction.
Table 5-5. Interrupt Mask Register
Bit Positions
Format:
I
77
I
3
I
ch
I
00-07
0000
ch = I/O channel designator 0-3
Instruction Description: This is a dual instruction:
A The internal status code of the computer is
loaded into the lower 12 bits of A.
B The contents of the Interrupt Mask register are
loaded into the upper 12 bits of A. See Table 5-4.
RNI from address P
1.
+
Definitions
00
18 17 15 14 12 11
23
08
I/O channel 0- 7 interrupts
(internal and external)
Clock interrupt
09
Exponent overflow or BCD fault
10
Arithmetic overflow or divide fault
11
Search/move completion interrupt
* FFs associated with these faults are cleared as soon
as the conditions are sensed.
5-25
23
Format:
I
00
18 17 15 14 12 11
xxxx
77
23
Format:
Instruction Description: Selectively sets the Interrupt Mask register according to xxxx. For each" 1"
bit in xxxx, the corresponding bit position in the
Interrupt Mask register is set to "1" (see table 5-5).
I
18 17 15 14 12 11
77
Instruction Description: This instruction exists for
the same reason as 77.71. In this case the BCD
Fault flip-flop is set.
23
23
Format:
I
00
18 1 7 1 5 14 12 11
77
5
I
3
I
18 17 1 5 14 12 11
77
Format:
Format:
Format:
I
77
5
7
Format:
I
18 17 15 14 12 11
77
7
00
I
Instruction Description: The floating-point fault
flip-flop is set to indicate that a floating point fault
has occurred. This instruction is used when floating-point arithmetic is simulated and causes a flipflop to set whenever a fault is sensed. The setting
of this flip-flop causes bit 09 to be set in the Interrupt register and permits a normal hardware
interrupt.
5-26
I
18 17 1 5 14 12 11
77
I
7
I
4
00
I
00
Instruction Description: This instruction sends an
int.errupt signal to a processor (computer). The
interrupt remains active until it is recognized.
23
3
7
Instruction Description: Interrupt control is enabled.
This instruction allows one more instruction to
be executed before any interrupt can take place.
23
18 17 15 14 12 11
00
xxxx
Instruction Description: Selectively clears the Interrupt Mask register according to xxxx. For each" 1"
bit in xxxx, the corresponding bit position in the
Interrupt Mask register is set to "0" (see table 5-5).
23
00
Instruction Description: Interrupt control is enabled.
This instruction allows one more instruction to
be executed before any interrupt can take place.
Appendix A
3100 Compass
This appendix describes the capabilities of the 3100 COMPASS assembly system and is not
intended as a final system description.
This information is preliminary and subject to change without notice.
Coding Procedures
3100 COMPASS subprograms are written on
standard coding sheets. A subprogram consists of
symbolic or octal machine instructions and pseudo
instructions. Symbolic machine instructions are alphabetic mnemonics for each of the 3100 machine
instructions. Pseudo instructions are COMPASS
instructions used for the following operations:
subprogram identification and linkage
ADDRESS FIELD
The address field begins before column 41 anywhere after the blank which terminates the operation field and ends at the first blank column. It is
composed of one or more subfields, depending
upon the instruction. Subfields, which are separated by commas on the coding form, specify the
following quantities:
data definition (constants conversion)
m or n
word address
data storage
r or s
character address
system calls
y
operand (1 5-bit)
assembler control
z
operand (17 -bit)
output listing control
b or i
index register or interval quantity
macro definition
c
character
INSTRUCTION FORMAT
A COMPASS instruction may contain location,
instruction, address, comment, and identification
fields.
LOCATION FIELD
A symbol in the location field (LOCN) is placed
in columns 1-8. A symbol identifies the address of
an instruction or data item.
Location field symbols may be blank or consist
of one to eight alphabetic or numeric characters;
the first character must be alphabetic. Embedded
blanks are ignored in location symbols. The following are examples of location symbols:
A
H3
ABCDEFGH
P1234567
A single * in the location field signifies a line of
comments.
OPERATION CODE FIELD
The operation code field (OP) consists of any of
the 3100 mnemonic or octal instruction codes with
modifiers, or any macro or pseudo instructions.
The field begins in column 10 and ends at the first
blank column. If a modifier is used, a comma must
separate the operation code from the modifier; no
blank columns may intervene. A blank operation
field or a blank in column 10 results in a machine
word with zeros in the operation field.
v
register file location
ch
channel
x
function code or comparison mask
The interpretations of the address subfields for
each set of 3100 instructions are described in the
table on page A-2.
An m, n, r, s, y or z subfield may contain:
•
a location symbol
•
the symbol ** which causes each bit in the
subfield to be set to one
•
the symbol * which causes the assembler to
insert the relocatable address of that instruction in the address field
•
an integer constant
•
an arithmetic expression
•
a literal
b SUBFIELD- The index field (b) specifies an index
register 1-3; or a symbol or expression which results in one of these digits may be used. Some
instructions require a particular index register. If
the b subfield is used with the octal operation
codes, 0-7 may be used.
c SUB FIE LD - The character field may con tain any
. octal or decimal number, expression, or a symbol
which is equivalent to a 6-bit binary number. Octal
numbers must be suffixed with the letter B.
ch SUBFIELD- The
channel field may contain one
digit 0-3 to designate an input! output channel, or
a symbol equated to one of these digits, or an
expression resulting in one of the digits.
A-I
x SUBFIELD- The code field may contain any of
the interrupt or input! output codes or comparison
mask. Either decimal numbers, octal numbers suffixed with the letter B, symbols, or expressions
resulting in constants may be used.
v SUBFIELD- The register file subfield specifies a
location which may be 008-778. Any legal coding
which results in a value 008-778 may be used.
i SUBFIELD-In the MEQ and MTH instructions,
this subfield specifies a decrement interval quantity
of 1-8.
COMMENTS FIELD
Comments may be included with any instructions. A blank column must separate them from
the last character in the address field and they may
extend to column 72. Comments have no effect
upon compilation, but are included on the assembly listing.
INSTRUCTION
00-70
m,n
71 (Search)
72 (Move)
73-77 (1/0)
first word
address, last
word address
word
address
b
index register
y or z
operand
+1
operand
F
character
c
E
r
L
D
character
address
s
address of first
character
first character
address of
source field
first
character
address
address of last
character
1
first character
address of
receiving field
last
character
address
+
+
1
ch
channel
x
1/0 or interrupt code
i
Interval quantity
IDENTIFICATION FIELD
Columns 73-80 may be used for sequence num-
bers or for program identification. This field has
no effect upon assembly.
Pseudo-I nstructions
MONITOR CONTROL
The following pseudo instructions provide communication between 3100 COMPASS subprograms
and the monitor. Some are required in every subprogram; others are optional. Unless otherwise
noted, each instruction may have a location field
and an address field.
IDENT m -appears at the beginning of every
COMPASS subprogram. The address field con-
A-2
tains the name of the subprogram, which may be
a maximum of eight alphanumeric characters, the
first being alphabetic. A symbol in the location
field is illegal and will result in an error flag (L)
on the listing.
END m -marks the end of every subprogram.
When a program (consisting of one or more subprograms) is assembled for execution, one of the
subprogram END cards must contain a location
symbol in the address field to indicate the first
instruction to be executed in the program. Only
one END card can contain an address field symbol. A term in the location field is ignored.
FIN IS -terminates an assembly operation. It is
a signal to the assembler that no more programs
are to be assembled. The FINIS card is placed
after the last END card of the last subprogram
in the source program.
SYMBOL ASSIGNMENTS
The pseudo instructions, EQ U; EQ U, C; ENTRY;
and EXT define symbols as equal to other symbols,
or values or identify symbols used to communicate with subprograms. Linkage between symbols
in separate subprograms is provided by the monitor system. These pseudo instructions may appear
anywhere between an IDENT and an END pseudo
instruction.
EQU m - assigns the result of the expression in the
address field to the symbol in the location field.
The result is a 15-bit address.
The following forms are allowed:
symbol
EQU
symbol
symbol
EQU
constant (octal or decinal)
symbol
EQU
expression (address arithmetic)
Example:
ENTRY
SYM 1. SYM2, SYM3 can now be referenced by
other subprograms.
EXT m - Symbols used by a subprogram defined
in another subprogram are declared as external
symbols by placing them in the address field of an
EXT pseudo instruction. Only word-location symbols (I5-bit) may be used. For example, to use the
external symbols SYMI, SYM2, SYM3 in subprogram A, the following pseudo instruction would
be written in subprogram A:
EXT
SYM 1.SYM2.SYM3
These symbols must be declared as ENTRY
points in some other subprogram or subprograms
which are loaded for execution with subprogram
A. The address field may be extended to column
72; symbols are separated by commas. No spaces
(blanks) can appear in a string of symbols. The
location field of an EXT must be blank.
Address arithmetic cannot be performed on external symbols.
Example:
FFI
Example:
OUT EQU JUMP + 2
If JUMP is assembled to address 00100, OUT
will be assigned the value 00102.
Numerical constants must follow the rules for
symbolic instructions. Address arithmetic is permitted. A location field symbol may be equated
to a decimal or octal constant.
EQU, C m -is similar to EQU, except that the
result is a 17-bit address.
ENTRY m -defines location symbols which are
referenced in other subprograms. These symbols,
called entry points, must be placed in the address
field of an ENTRY pseudo instruction. Any number of locations may be declared as entry points in
the same ENTRY instruction. If two or more names
appear in the address field, they must be separated
by commas. No spaces (blanks) can appear within
a string of symbols. The address field of the
ENTR Y pseudo instruction may be extended to
column 72 and the location field must be blank.
Only word-location symbols (I5-bits) may be used.
SYM 1,SYM2.SYM3
IDENT
CAIRO
ENTRY
DEED. FFI
EXT
ABE. DAVID
SJ 1
**
•
BEN
EQU
DEED
LDA
HAKIM
•
ABE
•
•
•
RTJ
DAVID
•
•
END
END
FFI
FINIS
LISTING CONTROL
The pseudo instructions which provide listing
control for assembly listings are shown below.
These instructions will not appear on the assembly
listing and may be placed anywhere in a program.
SPACE -controls line spacing on an assembly
listing. A decimal constant in the address field
designates the number of spaces to be skipped
before printing the next line. If the number of
A-3
spaces to be skipped is greater than the number
of lines remaining to be printed on a page, the
line printer skips to the top of the next page. A
symbol in the location field is ignored.
EJECT -causes the line printer to skip to the top
of the next page when the assembled program is
listed. A symbol in the location field is ignored.
REM -is used to insert program comments in an
assembly listing. The address field can be extended
to column 72. Any standard key punch character
can be used in the comments. If the comments are
to be written on more than one line, successive
REM pseudo instructions must be used. A symbol
in the location field is ignored.
NOLIST-causes the assembler to discontinue
writing a listing of the program, starting with this
instruction.
LIST -causes the assembler to resume listing the
program. This instruction is used after a NOLIST
instruction; it is not necessary to use it to obtain
a complete listing of a program.
MACRO INSTRUCTIONS
MACRO -defines the beginning of a sequence of
instructions that will be inserted by the assembler
in the source program whenever th~ location symbol of the MACRO instruction appears in an operation field. The end of the sequence of instruction
is marked by an ENDM pseudo instruction. For
example, if the sequence
HOPE
MACRO
(PAMA)
LOA
PA
INA
24B
STA
MA
ENOM
were defined and the following instructions appeared in the same program
STA
GARAGE
HOPE
(OW21 06)
LOA
FARM
the assembled output would be
STA
A-4
GARAGE
LOA
OW21
INA
24B
STA
06
LOA
FARM
EN OM - defines the end of a macro sequence.
LI B M - names library macros.
NAME (p1, ... ,pn)-is used to reference macros. The
parameters pI, ... ,p2 are used by the routine, and
name is a system defined macro.
DATA STORAGE ASSIGNMENTS
The following pseudo instructions reserve storage areas for blocks of data. BSS reserves storage
blocks within the subprogram in which it appears.
If these storage areas are to be referenced by other
subprograms, the name assigned to the block is
declared as an entry point in the program containing the block, and as an external symbol in the program referencing the block. Only work location
symbols may be used. COMMON identifies storage
areas to be referenced by more than one subprogram. DATA specifies special areas which may
be preloaded with data; EXT and ENTRY are
not needed to reference COMMON or DATA
areas. Address arithmetic may be used, but all
symbols must have been defined before the instruction is encountered.
BSS m - reserves a storage area of length m in a
subprogram on a common or data storage area.
The address field may contain any expression which
results in a constant. The resultant constant specifies number of words to be used. The address field
of the first word of the reserved area is assigned
the location field term of the BSS instruction. Other
words or characters in the area may be referenced
by addressing arithmetic or by indexing.
BSS, C m - reserves a character storage area of
length m in a subprogram. The address field is
similar to the address field of BSS pseudo instruction. However, the resultant constant specifies the
number of character positions to be reserved.
COMMON -assigns location terms following it to
a common storage block until a DATA or PRG
pseudo instruction is encountered. ORGR, BSS
and BSS, C are the only pseudo instructions which
may follow a COMMON pseudo instruction.*
Location and address fields of a COMMON pseudo
instruction should be blank. COMMON may not
be preset with data. The following example illustrates the foregoing pseudo instructions:
*Occurrence of any other machine or data definition command causes the command and its successors to be assembled into the subprogram area.
Example:
IDENT
During execution, one area in storage is assigned
as common. All common storage may be filled repeatedly during program execution. A storage
location assigned to the nth word in COMMON
in subprogram 1 is the same location assigned to
the nth word in common in subprogram 2. If the
two subprograms in the above example were loaded
together, the memory assignments would be as
shown in the following table:
BURKE
COMMON
A
BSS
20
B
BSS
10
C
BSS
6
•
•
•
END
IDENT
SPINOZA
COMMON
MARKET
BSS
STREET
BSS
13
SINGER
BSS
4
5
END
Locations in
memory relative
to the beginning
of common
Name in
subprogram
BURKE
Name in subprogram
SPINOZA
1-5
A
MARKET
) MARKET+4
6-18
A+5~A+17
STREET
) STREET+12
19-20
A+18~A+19
SINGER
) SINGER+1
21-22
B
SINGER+2
) SINGER+3
)A+4
)B+1
23-30
B+2
)B+9
31-36
C
)C+5
DA TA - assigns all location symbols following it
to a data block until a COMMON or PRG pseudo
instruction is encountered. Data described by
OCT; BCD; BCD,C; DEC; DECD and VFD
pseudo instructions may be assembled into a DATA
block. Areas may be reserved within a DATA
block by the BSS and BSS,C pseudo instructions.
The following is an example of a DATA pseudo
instruction coded within a subprogram:
Example:
•
•
•
LOA
APRESMOI
DATA
CONS
OCT
10,11,12,13
PRG
*
STA
LEDELUGE
A data area named CONS would be reserved
and the octal constants 10, 11, 12, and 13 loaded
into the four words in this area. In the source
program, STA LEDELUGE would appear in the
next location after LDA APRESMOI.
PRG -terminates the definition of a COMMON
or DATA area.
CONSTANTS
Octal, decimal, and BCD constants may be inserted in a 3100 COMPASS program by using the
pseudo instructions listed below. Location terms
may be used and the address field may extend to
column 72, if necessary.
OCT m1 ,m2, ... ,mn -inserts octal constants into
consecutive machine words. A location term is
optional; ifpresent, it will be assigned to the first
word. The address field consists of one or more
consecutive subterms, separated by commas. Each
subterm may consist of a sign (+ or - or none),
followed by up to eight octal digits. Each constant
is assigned to a separate word. If a location term
is present, it will be assigned to the first word. If
less than eight digits are specified, the constant is
right justified in the word and leading zeros inserted.
A-5
DECD ml,m2, ... ,mn-converts decimal constants to
equivalent 48-bit binary values and stores them in
consecutive groups of two machine words. Each
constant may be written in either fixed or floating
point format.
The decimal numbers to be converted are written in the address field of the DECD instruction
as follows:
Floating point constant consists of a signed or unsigned decimal integer of 14 digits. It is identified
as a floating point constant by a decimal point
which may appear anywhere within the digital
string. A binary scale factor or decimal scale factor
(indicated by B ± b or D ± d, respectively) is
permitted. The result after scaling must not exceed
the capacity of the hardware (approximately
10
±308).
Fixed point constant format is similar to that of the
DEC single precision constants. Up to 14 decimal
digits may be specified, expressing a value the magnitude of which is less than 247. Decimal and binary
scale factors may be used. Low order bits are not
lost; the signed 48-bit binary result is stored in two
consecutive computer words.
No spaces may occur within a number, including
its associated scale factors, as a space indicates
the end of the constant. Plus signs may be omitted.
Any number of constants may appear in a DECD
instruction. Successive constants are separated by
commas.
Examples:
LOCN
Op
CONST A
DECO
-12345.
FLOATING PT CONST
CONST B
DECO
+ 12345
FIXED PT CONST
CONST C
DECO
-12345.0+5
FLOATING PT CONST, OECSCALE
CaNST 0
DECO
123450-3
FIXED PT CaNST, OECSCALE
Address Field
CONST E
DECO
+ 12345B+8
FIXED PT CONST, BINSCALE
CaNST F
DECO
+12345.012B-18
FLOATING PT CaNST, OECBIN SC
DEC ml ,m2, ... ,mn - inserts 24-bit decimal integer
constants in consecutive machine words. The D
and B scaling is identical to the DECD scaling,
but only positive integer values less than 233 may
be used. If a location term is present, it is assigned
to the first constant.
BCD n,clc2, ... ,c4n-inserts binary-coded decimal
characters into consecutive words. If a location
term is present, it will be assigned to the first word.
The address field consists of a single digit n, which
specifies the number of four-character words needed
to store the BCD constant, followed by a comma
and the BCD characters. The next 4n character
positions after the comma will be stored. Any character string which terminates before column 73
may be used; n is restricted accordingly.
BCD,C n,C1C2, ... ,Cn -places n characters in the next
available m character positions in memory. If the
previous instruction were also a BCD,C instruction, the next character position is defined as the
one which follows the last position used by the
previous instruction. If a location symbol is used,
it will be assigned to the first character position in
this field. If the previous instruction were not a
BCD,C instruction, the next character position
A-6
Comments
would be the first character position (0) of the next
available word. Any character string which terminates before column 73 may be used; n is restricted accordingly.
VFD mln1/vl .. ./mpnp/vp-assigns data in continu-
ous strings of bits rather than in word units. Octal
numbers, character codes, program locations and
arithmetic values may be assigned consecutively in
memory, regardless of word breaks. The address
field consists of one or more data fields. In each
data field m specifies the mode of the data, n the
number of bits allotted: and v the value. Four
modes are allowed:
o
Octal number. If it is preceded by a minus
sign, the one's complement form is stored.
H
Hollerith character code. The field length
must be a mUltiple of six. Any printable
character may appear in the v field except
blanks or commas. Either a space or comma
immediately succeeds the last character.
A
Arithmetic expression or decimal constant.
The v field consists of an expression formed
according to the rules for address field arithmetic, with the following restrictions:
I vi ::;;
n
1 n must be ~ 24 and
2 - 1-1 unless a
relocatable expression is used, in which
case, n = 1 5 for word addresses and n = 1 7
for character addresses.
must be placed in the correct position in
the address portion of a word to insure
that it will be relocated by the loader.
C
Character Expression.
2 When a relocatable expression is used, it
Example:
VFD 012/-737,A27/A-X+B,H24/+A3 ,A15/NAME+2,H12/BQ
A X, and B are non-relocatable symbols. Four words are generated, with the data placed as follows:
23
I 70
12
0
40
I
[A*
14
23
I-x +
B
I
3
0
[NAME +
0
21
I
0
WORD 2
14
60
I
20
WORD 1
23
8
2]
23
I
I
ADDITIONAL PSEUDO INSTRUCTIONS
Additional lines of coding may be generated by
the following pseudo instructions:
I FZ m,n - n succeeding lines of coding will be assembled if m is zero. The integer n must be a positive numerical integer and m may be a symbol, an
address arithmetic symbol, or a literal. If m is
nonzero, n succeeding lines of coding will be bypa~sed by the assembler.
I FN m,n - n succeeding lines of coding will be as
sembled if m is nonzero; n must be a positive
numerical integer and m may be a symbol, address
arithmetic symbol or literal. If m is zero, n succeeding lines of coding will be bypassed by the
assembler.
The pseudo instructions, 1FT and IFN, may be
used within the range of a MACRO definition only.
1FT m,n,p - p succeeding lines of coding will be
generated if character string m equals character
string n. The integer p must be a positive numerical
integer and m and n may be a formal parameter
or a literal. If m ~ n, p succeeding lines of coding
will be bypassed.
IFF m,n,p-p succeeding lines of coding will be
generated if m ~ n. The integer p must be a positive integer and m and n may be a formal parameter
or a literal. If m = n, p succeeding lines of coding
will be bypassed.
B
Q
0
I
a
0
0
I
0
WORD 4
WORD 3
The YFD address field is terminated by the first
blank column not within a Hollerith field.
12
ORGR m -the value in the address field will be
assembled as the beginning location for subsequent
instructions. The value may be in program, data
area, or common area mode. The occurrence of a
mode change pseudo operation, COMMON,
DATA or PRG, terminates ORGR and subsequent instructions are assembled in the new mode.
NOP-No operation. An ENI y, 0 instruction is
inserted.
the information beginning in the address
field is printed at the head of each page of the
output listing which follows. The first page of listing may be titled by presenting the TITLE card
immediately following the IDENT card.
TITLE -
ASSEMBLY LISTING FORMAT
An assembly listing contains the source program instructions and the corresponding octal
machine instructions. The addresses assigned to
each subprogram are relative addresses only. Absolute addresses are assigned when the program is
loaded by the monitor loader. All common blocks
are assigned consecutively, starting at relative location 00000. The range of locations assigned to the
machine instructions (first word address and last
word address plus one) are given at the beginning
of each subprogram. Following this is a list of all
entry points and external symbols, and the address
assignments for all COMMON and DATA pseudo
instructions. References to external symbols are
strung together by the assembler. The monitor
loader assigns the proper absolute addresses.
A-7
The address of each instruction word is the leftmost field for each instruction in the assembled
listing. (Error codes appear to the left of this field.)
External address field symbols are indicated by an
X immediately to the left of the octal address field
of each instruction. P indicates Program Relocatable, and C indicates Common. Subsequent next
fields from left to right on the listing are an 8-digit
location contents field, a 2-digit operation code, a
I-digit b-subfield, a 5-digit address, and a I-digit
character position. The remaining fields correspond
to those in the symbolic source program. Listing
format:
location
location
contents
op
5 or 6
8
2
b
addr
5
char
pos
source
line
o
Same symbol used in more than one location field term. Only the first symbol is recognized; the remainder are ignored. A list of
doubly defined symbols appears on the assembled listing.
F
Symbol table is full. No more location field
symbols will be recognized. Also designates
overflow of MACRO parameter table.
D
Illegal operation code. Zeros are substituted
for the operation code.
U
Undefined symbol. The assembler assigns the
symbol to a region following the last program
entry. A list of undefined symbols will appear
on the output listing.
C
An attempt was made to preset COMMON.
L
A symbol appears in the location field when
not permitted, a symbol is missing in the
location field when one is required, or an
illegal location symbol appears.
80
digits
ERROR CODES
The following error codes may appear as the
leftmost field on an assembled listing:
Code
A
A-8
M A modifier appears in the location field when
not permitted, a modifier is missing in the
operation field when one is required, or an
illegal modifier appears in the operation field.
T
Illegal character or expression in the address field.
A character address symbol was used in an
address subfield requiring a word symbol;
significant bits are lost.
TABLE A-1
3100 COMPASS and BASIC ASSEMBLER MACHINE INSTRUCTIONS
Operation Field
00
Instruction
Address Field
RTJ
m
m
m
m
m
m
unconditional stop; read next instruction
from location m
jump if key 1 is set
jump if key 2 is set
jump if key 3 is set
jump if key 4 is set
jump if key 5 is set
jump if key 6 is set
return jump
01
UJP. I
m. b
unconditional jump
02
IJI
IJD
m. b
m. b
index jump; increment index
index jump; decrement index
03
AZJ. EO
NE
GE
LT
AOJ. EO
NE
GE
LT
m
HLT
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
04
ASE.S
OSE. S
ISE
m
m
compare A with zero;
m
compare A with 0;
y
y
y. b
{
jump
jump
jump
jump
jump
jump
jump
jump
{
if
if
if
if
if
if
if
if
(A)
(A)
(A)
(A)
(A)
(A)
(A)
(A)
ASG.S
OSG.S
ISG
y. b
skip next instruction. if (A) ~ y
skip next instruction. if (0) ::; y
b
skip next instruction. if (B ) ~ y
06
MEO
m. i
masked threshold search
07
MTH
m. i
masked equality search
10
lSI
ISO
SSH
y. b
y. b
m
index skip; increment index
index skip; decrement index
storage shift
11
ECHA. S
z
enter A with 17 -bit character address
12
SHA
SHQ
y. b
y. b
shift A
shift Q
13
SHAO
SCAO
y. b
y. b
shift AO
scale AO
14
ENA
ENI
ENO
Y
y. b
enter A
enter index
enter 0
y
15
INA
INI
INO
y
y. b
16
XOA. S
XOO. S
XOI
Y
Y
ANA. S
ANO. S
ANI
y
17
Y
y. b
y
y. b
0
~ 0
::; 0
=
(0)
~ (0)
~ (0)
::; (0)
skip next instruction. if (A) = y
skip next instruction. if (0) = y
b
skip next instruction. if (B ) = y
05
Y
Y
=
~ 0
increase A
increase index
increase 0
exclusive OR y and (A)
exclusive OR y and (0)
b
exclusive OR y and (B )
logical product (AND) of y and (A)
logical product (AN D) of y and (0)
logical product (AND) of y and (Bb)
A-9
TABLE A-1 - (cant.)
Operation Field
Instruction
20
LDA, I
m. b
load A
21
LDQ. I
m. b
load Q
22
LACH
r. 1
load A character
23
LQCH
r. 2
load Q character
24
LCA, I
m. b
load A complement
25
LDAQ.I
m. b
load AQ (double precision)
26
LCAQ.I
m. b
load AQ complement (double precision)
27
LDL. I
m. b
load logical
30
ADA. I
m. b
add to A
31
SBA, I
m. b
subtract from A
32
ADAQ.I
m. b
add to AO
33
SBAO. I
m. b
subtract from AO
34
RAD. I
m. b
replace add
35
SSA, I
m. b
selectively set A
36
SCA, I
m. b
selectively complement A
37
LPA, I
m. b
logical product with A
40
STA, I
m. b
store A
41
STQ. I
m. b
store Q
42
SACH
r. 2
store character from A
43
SQCH
r. 1
store character from 0
44
SWA. I
m. b
store 15-bit word address from A
45
STAQ. I
m. b
store AO
46
SCHA. I
m. b
store 17 -bit character address from A
47
STI. I
m. b
store index
50
MUA, I
m. b
multiply A
51
DVA, I
m. b
divide AQ (48 by 24)
52
CPR. I
m. b
53
TIA
TAl
TMA
TAM
TMO
TOM
TMI
TIM
AQA
AlA
IAI
b
b
v
v
v
v
v.b
v.b
b
within limits test
b
transmit (B ) to A
transmit (A) to Bb
transmit (high speed memory) to A
transmit (A) to high speed memory
transmit (high speed memory) to 0
transmit (Q) to high speed memory
transmit (high speed memory) to Bb
b
transmit (B ) to high speed memory
transmit (A)
(0) to A
b
transmit (A)
(B ) to A
b
transmit (B )
(A) to Bb
54
LDI. I
m. b
load index
56*
MUAQ. I
m. b
multiply AQE (96 by 48)
57*
DVAO. I
m. b
divide AQE (48 by 48)
b
+
+
+
60*
FAD. I
m. b
floating add to AQ
61*
FSB. I
m. b
floating subtract from AQ
*Trapped instructions.
A-lO
Address Field
TAB LE A-1 - (cant.)
Operation Field
Address Field
Instruction
62*
FMU, I
m, b
floating multiply AQ
63*
FDV, I
m, b
floating divide AQ
64*
lDE
r, 1
load E
65*
STE
r, 2
store E
66*
ADE
r, 3
add to E
67*
SBE
r, 3
subtract from E
70*
SFE
EZJ, EQ
IT
EOJ
SET
y, b
m
shift E
compare E with zero; jump if E
compare E with zero; jump if E
jump to m on E overflow
set D to value of y
m
y
<
0
0
search character equality
search character inequality
c, m1, m2
c, m1, m2
71
SRCE, INT
SRCN, INT
72
MOVE,INT
Lr, s
move
73
INPC, INT, B, H, A or NC
INAC, A or NC
ch, r, s
ch
input character block to memory
input character to A
74
INPW, INT, B, N, A or NC
INAW, A or NC
ch, m, n
ch
input word block to memory
input word to A
75
OUTC, INT, B, H, A or NC
OTAC, A or NC
ch, r, s
ch
output character block from memory
output character from A
76
OUTW, INT, B, N, A or NC
OTAW, A or NC
ch, m, n
ch
output word block from memory
output word from A
77.0
CON
x, ch
connect
77.1
SEL
x, ch
select
77.20
COPY
x, ch
x=o
copy status
77.2
EXS
x, ch
x~o
external sense
77.3
INS
x, ch
x~o
internal sense
77.30
CINS
x=o
copy internal status
77.4
INTS
x, ch
interrupt sense
77.50
INCl
x
interrupt clear
77.51
10Cl
x
1/0 clear
77.52
SSIM
x
selective set interrupt mask
77.53
SCIM
x
selective clear interrupt mask
77.57
IAPR
x
interrupt associated processor
77.6
PAUS
x
pause
77.70
SLS
selective stop
77.71
SFPF
set floating point fault
77.72
SBCD
set BCD fault
77.73
DINT
disable interrupt control
77.74
EINT
enable interrupt control
77.75
CTI
console typewriter in
77.76
eTa
console typewriter out
77.77
UCS
unconditional stop
f characters from r to s
*T rapped instructions.
A-II
Appendix 8
BasIc Assembler Coding Procedures
Basic Assembler Coding Procedures
BASIC Assembler programs are written in a
manner similar to 3100 COMPASS programs. Each
program is a complete entity and may be designed
for any 3100 equipment configuration. Object programs produced by the BASIC Assembler for the
3104 4K storage configuration are loaded by the
BASIC Loader; those for 8K or larger configurations are loaded by 3100 SCOPE.
INSTRUCTION FORMAT consists of the
following fields:
LOCATION FIELD -from one to six alphabetic or
numeric characters; the first character must be alphabetic.
OPERATION FIELD-any of the 3100 mnemonic
instruction codes with modifiers, or the BASIC
Assembler pseudo instructions.
ADDRESS FIELD -from one to six character location symbols, the special ** or * symbol, an integer
constant, or an expression (address arithmetic)
consisting of two terms.
COMMENTS FIELD -may be included with any
instruction. A full line of comments may be inserted by placing an asterisk in the location field.
IDENTIFICATION FIELD -sequence numbeT or
program identification.
Pseudo-I nstructions
PROGRAM IDENTIFICATION is provided
for each program.
IDENT m
appears atthe beginning of a BASIC
Assembler program. The address
field contains the name of the subprogram.
END m
marks the end of the program. The
address field may contain a symbol
which is used as the entry point to
the program.
DATA STORAGE ASSIGNMENTS
BSS m
reserves a block of words of length m.
BSS, C m
reserves a block of characters of
length m.
DATA DEFINITION
OCT m
inserts an octal constant into a machine word.
DEC m
inserts a single precision decimal
constant into a machine word. Decimal and binary scaling is permitted.
DECO m
inserts a double precision decimal
constant into two consecutive machine words. Floating or fixed point
numbers are allowed, also decimal
and binary scaling.
SYMBOL ASSIGNMENTS for each program.
EQU m
equates an undefined symbol to a
defined word address symbol.
EQU, C m
equates an undefined symbol to a
defined character address symbol.
ORGR m
assembles the value specified in the
address field as the beginning location for subsequent instructions. A
symbol in the address field must
be defined elsewhere in the program.
NOP m
inserts a "do-nothing" instruction.
The address field may contain a
symbol.
LISTING CONTROL for assembly listings.
SPACE
controls line spacing.
EJ ECT
moves the line printer to the top of
the next page.
REM
is used to insert program comments.
NOLIST
suppresses the output listing lines.
LIST
resumes printing after a NOLIST
instruction.
BCD
n,C1C2 ... C4n
BCD,
Cn,c1c2 ... Cn
inserts binary-coded decimal
characters into consecutive
words.
inserts binary-coded decimal
characters into the next
available n character positions in storage.
ASSEMBLY LISTING FORMAT
An assembly listing contains the source program
and corresponding octal machine instructions. The
program may be loaded absolutely, beginning at
location 00000 or relocated into memory relative
to some location other than 00000. Error codes
correspond to 3100 COMPASS error codes; A, D,
F, L, M, 0 and T codes are included.
B-1
Appendix C
Number Systems
• ARITHMETIC
• CONVERSIONS
• FIXED POINT AND
FLOATING POINT
NUMBERS
Number Systems
Any number system may be defined by two characteristics, the radix or base and the modulus. The
Ox2 5 =Ox32= 0
+ 1 X 24 = 1 x 16 = 16
+1x,2 3 =1x8
8
+Ox2 2 =Ox4
0
+1x21=1x2
2
+Ox2° = Ox 1
_0__
radix or base is the number of unique symbols used
in the system. The decimal system has ten symbols,
o through 9. Modulus is the number of unique
quantities or magnitudes a given system can distinguish. For example, an adding machine with
ten digits, or counting wheels, would have a modulus of 10 10 _1. The decimal system has no modulus
because an infinite number of digits can be written,
but the adding machine has a modulus because
the highest number which can be expressed is
9,999,999,999.
Fractional binary numbers may be represented
by using the symbols as coefficients of ascending
negative powers of the base.
2 1
= 1;2
Binary Point
Most number systems are positional, that is, the
relative position of a symbol determines its magnitude. In the decimal system, a 5 in the units
column represents a different quantity than a 5 in
the tens column. Quantities equal to or greater
than 1 may be represented by using the 10 symbols
as coefficients of ascending powers of the base 10.
The number 98410 is:
9 x 10 2 = 9 x 100 = 900
+8 X 10 1 = 8 x 10 = 80
1
4
+4 x 10° = 4 x
98410
Quantities less than 1 may be represented by
using the 10 symbols as coefficients of ascending
negative powers ofthe base 10. The number 0.59310
may be represented as:
5x 10- 1 = 5x.1
+9x10- 2 =9x.01
2 3x10- 3 = 3x.001
BINARY NUMBER SYSTEM
Computers operate faster and more efficiently
by using the binary number system. There are only
two symbols 0 and 1; the base = 2. The following
shows the positional value:
24 2 3 22
21 20
=16 =8 =4 =2 =1
Binary point
The binary number 0 I I 0 I 0 represents:
2- 2
= %
2- 3 2- 4
= Va = 1/16
2- 5 ...
= 1/32
The binary number 0.10 110 may be represented
as:
= 1 x 112 = 112
= Ox 1/4 = 0
= 1 x 118 = 1/8
8/1 6
0
+1x2- 3
2/1 6
+1x2 4=1x1/16=1/16= J1l6
11/1610
1x2-
+Ox2-
1
2
OCTAL NUMBER SYSTEM
The octal number system uses eight discrete symbols, 0 through 7. With base eight the positional
value is:
85
32,768
84
83
82
4,096
512
64
8°
1
The octal number 5138 represents:
5 x 8 2 = 5 x 64 = 320
+1x8 1 =1x8
8
+3 x 8° = 3 x 1
__
3_
.5
.09
.003
0.59310
25
=32
2610
33110
Fractional octal numbers may be represented by
using the symbols as coefficients of ascending negative powers of the base.
8- 1
1/8
8-
3
1/512
8- 4
1/4096
The octal number 0.4520 represents:
1
4x8- =4x1/8 =4/8 =256/512
+ 5x8 - 2 = 5x 1/64 = 5/64 = 40/51 2
+2x8- 3=2x1 1512 =2/512 =
21512
298/512 = 149/25610
C-l
Arithmetic
ADDITION AND SUBTRACTION
Binary numbers are added according to the following rules:
as follows (the decimal equivalents verify the
result):
Partial Sum
Carry
( 11 )
Subtraction may be performed as an addition:
+4 (1 O's complement of subtrahend)
2 (difference - omit carry)
The second method shows subtraction performed
by the "adding the complement" method. The omission of the carry in the illustration has the effect of
reducing the result by 10.
One's Complement. The 3100 performs all arithmetic and counting operations in the binary one's
complement mode. In this system, positive numbers
are represented by the binary equivalent and negative numbers in one's complement notation.
The one's complement representation of a number is found by subtracting each bit of the number
from l. For example:
0110
(7)
+(4)
8 (minuend)
or
2 (difference)
1111
-1001
1011
Sum
The addition of two binary numbers proceeds
8 (minuend)
-6 (subtrahend)
0111
+0100
0011
1
Augend'
Addend
0+0=0
0+1=1
1+0=1
1 + 1 = 0 with a carry of 1
MULTIPLICATION
Binary multiplication proceeds according to the
following rules:
OxO
Ox 1
1 xO
1x1
=
0
= 0
= 0
= 1
Multiplication is always performed on a bit-bybit basis. Carries do not result from multiplication,
since the product of any two bits is always a single
bit.
Decimal example:
9
(one's complement of 9)
This representation of a negative binary quantity may also be obtained by substituting" l's" for
"O's" and "O's" for" I 's".
The value zero can be represented in one's complement notation in two ways:
14
12
multiplicand
multiplier
partial products
<
28
14
(shifted one place left)
16810
product
The shift of the second partial product is a shorthand method for writing the true value 140.
Binary example:
0000--'002
1111--.112
Positive (+) Zero
Negative (-) Zero
The rules regarding the use of these two forms
for computation are:
Both positive and negative zero are acceptable
as arithmetic operands.
2 If the result of an arithmetic operation is zero,
it will be expressed as positive zero.
One's complement notation applies not only to
arithmetic operations performed in A, but also to
the modification of execution addresses in the F
register. During address modification, the modified
address will equal 777778 only if the unmodified
execution address equals 777778 and b = 0 or (B b)
=
777778.
C-2
multiplicand
multiplier
(14)
(12)
partial products {
product
( 16810)
1110
1100
0000
0000
1110
1110
shift to place
digits in proper
columns
101010002
The computer determines the running subtotal
of the partial products. Rather than shifting the
partial product to the left to position it correctly,
the computer right shifts the summation of the partial products one place before the next addition is
made. When the multiplier bit is "1", the multi-
plicand is added to the running total and the results
are shifted to the right one place. When the multiplier bit is "0", the partial product subtotal is
shifted to the right (in effect, the quantity has been
multiplied by 102).
1110
divisor
1 1 01 \1 0 11 1 001
1101
10100
1101
1110
1101
11
DIVISION
The following examples shows the familiar
method of decimal division:
,.-1'---4-=---_ q u oti e nt
13\185
dividend
13
divisor
55
52
3
partial dividend
remainder
The computer performs division
manner (using binary equivalents):
In
a similar
quotient (14)
dividend
partial dividends
remainder (3)
However, instead of shifting the divisor right to
position it for subtraction from the partial dividend (shown above), the computer shifts the partial
dividend left, accomplishing the same purpose and
permitting the arithmetic to be performed in the A
register. The computer counts the number of shifts,
which is the number of quotient digits to be obtained; after the correct number of counts, the
routine is terminated.
Conversions
The procedures that may be used when converting from one number system to another are power
addition, double dabble, and substitution.
Recommended Conversion Procedures
(Integer and Fractional)
Recommended Method
Conversion
Binary to Decimal
Octal to Decimal
Decimal to Binary
Decimal to Octal
Binary to Octal
Octal to Binary
Power Addition
Power Addition
Double Dabble
Double Dabble
Substitution
Substitution
GENERAL RULES
rj
rj
>
<
rf : use Double Dabble, Substitution
rf : use Power Addition, Substitution
rj = Radix of initial system
rf = Radix of final system
POWER ADDITION
To convert a number from rj to r fer j < rr) write
the number in its expanded rj polynomial form
and simplify using r f arithmetic.
EXAMPLE 1
Binary to Decimal (Integer)
010 1112=1 (24) +0(2 3 )+1(2 2)+1(2 1 )+1(2 0 )
=1 (16) +0(8) +1(4) +1(2) +1(1)
=16
+0
+4
+2
+1
=2310
EXAMPLE 2
Binary to Decimal (Fractional)
.01012 =(2- 1)+1(2- 2) +0(2- 3 ) +1(2- 4 )
=0
+1/4
+0
+1/16
= 5/1610
EXAMPLE 3
Octal to Decimal (Integer)
3248=3(8 2 ) +2(8 1) +4(8 0 )
=3(64)+2(8) +4(1)
=192 +16 +4
=21210
EXAMPLE 4
Octal to Decimal (Fractional)
.448 = 4( 8 - 1) + 4 (8- 2)
=4/8
+4/64
=36/6410
DOUBLE DABBLE
To convert a whole number from
~
to r f (r j > r f ):
1 Divide ri by rf using ri arithmetic
2 The remainder is the lowest order bit in the
new expression
3 Divide the integral part from the previous operation by rr
4 The remainder is the next higher order bit in
the new expression
5 The process continues until the division prodUces only remainder ~hich will be the highest order bit in the rf expression.
a
C-3
To convert a fractional number from
1 MUltiply
ri
by rr using
ri
fi
to n:
EXAMPLE 4
arithmetic
2 The integral part is the highest order bit in the
new expression
Decimal to Octal (Fractional)
.55 x 8 = 4.4; record
.4 x 8 = 3.2; record
.2 x 8 = 1.6; record
3 Multiply the fractional part from the previous
operation by rf
4 The integral part is the next lower order bit in
the new expression'
4
3
.431 ...
Thus: .5510
.431 ... 8
5 The process continues until sufficient precision
is achieved or the process terminates,
Decimal to Binary (Integer)
EXAMPLE 1
45
22
11
5
2
-;-
-;-
-;-
22 remain~er 1; record
11 remainder 0; record
5 remainder 1; record
2 remainder 1; record
1 remainder 0; record
0 remainder 1 ; record
2
2
2
2
2
2
Thus: 4510
1011012
0.5; record
1.0; record
0.0; record
Thus: .2510
.0102
EXAMPLE 3
273 -7- 8
34 -7- 8
4
-7-
8
This method permits easy conversion between
octal and binary representations of a number. If a
.number in binary notation is 'pa-rtitioned into triplets to the right and left of the binary point, each
triplet may be converted into an octal digit. Similady each octal digit may be converted into a
triplet of binary digits.
0
.1
0
101101
Decimal to Binary (Fractional)
EXAMPLE 2
.25 x 2
.5 x 2
.0 x 2
SU BSTITUTION
1
0
EXAMPLE 1
0
Binary to Octal
Binary =
Octal =
.010
110 000
001 010
6 0' . 1
2
Decimal to Octal (Integer)
34 remainder 1; record
4 remainder 2; record
o remainder 4; record
Thus: 27310 =
1
2
4421
EXAMPLE 2
Octal to Binary
Octal =
6
5
0
Binary = 110 101 000
4218
227
010 010 111
Fixed Point and Floating Point Numbers
(The following information is for reference only and does not necessarily imply-computer capability).
Any number may be expressed in the form kB n ,
where k is a coefficient, B a base number, and the
exponent n the power to which the base number
is raised.
A fixed point number assumes:
The exponent n = 0 for all fixed point numbers.
2 The coefficient, k, occupies the same bit positions within the computer word for all fixed
point numbers.
BIT NO.
23
A 3100 fixed point number consists of a sign bit
and coefficient as shown below. The upper bit of
any 3100 fixed point number designates the sign of
the coefficient (23 lower order bits). If the bit is
"1", the quantity is negative since negative numbers are represented in one's complement notation;
a "0" sign bit signifies a positive coefficient.
I 22
I~_~_I?_TN~I
C-4
3 The radix (binary) point remains fixed with respect to one end of the expression.
____________________
00
~~~~
_____
C_O_E_FF_IC_I_E_N_T______________
I
~I
The radix (binary) point is assumed to be immediately to the right of the lowest order bit (00).
In many instances, the values in a fixed point
operation may be too large or too small to be
expressed by the computer. The programmer must
position the numbers within the word format so
they can be represented with sufficient precision.
The process, called scaling, consists of shifting the
values a predetermined number of places. The
numbers must be positioned far enough to the right
in the register to prevent overflow but far enough
to the left to maintain precision. The scale factor
(number of places shifted) is expressed as the power
of the base. For example, 5,100,00010 may be expressedasO.5I x 10 7,0.051 X 108,0.0051 X 10 9, etc ..
The scale factors are 7, 8, and 9.
Since only the coefficient is used by the computer,
the programmer is responsible for remembering
the scale factors. Also, the possibility of an overflow during intermediate operations must be considered. For example, if two fractions in fixed poin.t
format are multiplied, the result is a number < 1.
If the same two fractions are added, subtracted,
or divided, the result may be greater than one and
an overflow will occur. Similarly, if two integers
47
I
46
F = fraction
E = exponent
In floating point, different coefficients_ need not
relate to the same power of the base as they do in
fixed point format. Therefore, the construction of
a floating point number includes not only the coefficient but also the exponent.
00
I
'-
/
V
COEFFICIENT
SIGN
True Positive
Exponent
+0
+1
+2
---
+1776
+ 17778
I
'-
v
.
Biased
Exponent
/
COEFFICIENT
EXP'NENT
(INCLUDING BIAS)
Coefficient. The coefficient consists of a 36-bit fraction -in the 36 lower-order positions of the floating
point w.ord. The coefficient is a normalized fraction;
it is equal to or greater than 1/2 b~t less than 1.
The highest order bit position (47) is occupied by
the sign bit of the coefficient. If the sign bit is a
"0", the coeffiCient is positive; a "1" bit denotes a
negative fraction (negative fractions are represented
in one's complement notation).
Exponent. The floating point exponent is expressed
as an II-bit quantity with a value ranging from
00008 to 37778. It is formed by adding a true positive exponent and a bias of20008 or a true negative
exponent and a bias of 17778. This results in a
range of biased exponents as shown below.
True Negative
Exponent
Biased
Exponent
2000
2001
2002
- - --
-0
-1
-2
2000*
1776
1775
--
------
- - --
--
------
3776
37778
-1776
-17778
0001
00008
*Minus zero is sensed as positive zero by the computer and is therefore biased by 20008 rather than
17778.
where:
36 35
I
"---y---/
are multiplied, divided, subtracted or added, the
likelihood of an overflow is apparent.
As an alternative to fixed point operation, a
method involving a variable radix point, called
floating point, is used. This significantly reduces
the amount of bookkeeping required on the part
of the programmer.
By shifting the radix point and increasing or decreasing the value of the exponent, widely varying
quantities which do not exceed the capacity of the
machine may be handled.
Floating point numbers within the computer are
represented in a form similar to that used in "scientific" notation, that is, a coefficient or fraction
multiplied by a number raised to a power. Since
the computer uses only binary numbers, the numbers are multiplied by powers of two.
C-5
The exponent is biased so that floating point
operands can be compared with each other in the
normal fixed point mode.
Number =
EXAMPLE 1
o
o 0
000
As an example, compare the unbiased exponents
of +528 and +0.028 (Example 1).
+52
(36 bits)
110
000
Coefficient
Exponent
Coefficient
Sign
Number =
o
111
+0.02
111
(36 bits)
011
Coefficient
Exponent
Coefficient
Sign
In this case +0.02 appears to be larger than +52
because of the larger exponent. If, however, both
exponents are biased, (Example 2) changing the
sign of both exponents makes +52 greater than
+0.02.
EXAMPLE 2
+528
Number =
o
o
Coefficient
Sign
000
Number =
o
Coefficient
Sign
000
(36 bits)
110
Exponent
o
111
Coefficient
+0.028
111
011
(36 bits)
Exponent
When bias is used with the exponent, floatingpoint operation is more versatile since floatingpoint operands can be compared with each other
in the normal fixed point mode.
.
CONVERSION PROCEDURES
Fixed Point to Floating Point
Coefficient
4 Assemble the number in floating point.
5 Inspect the sign of the coefficient. If negative,
complement the assemble~ floating point
number to obtain the true floating point representation of the number. If the sign of the
coefficient is positive the assembled floating
point number is the true representation.
1 Express the number in binary.
2 Normalize the number. A normalized number
has the most significant 1 positioned immediately to the right of the binary point and is
expressed in the range 1/2 :s:: k < 1.
3 I nspect the sign of the true exponent. If the
sign is positive add 20008 (bias) to the true
exponent of the normalize.d number. If the
sign is negative add the bias 17778 to the
true exponent of the normalized number. In
either case, the resulting exponent is the
biased exponent.
C-6
EXAM PLE 1
Convert +4.0 to floating point
1 The number is expressed in octal.
2 Normalize. 4.0
= 4.0
x 8°
= 0.100 x 23.
3 Since the sign of the true exponent is positive,
add 20008 (bias) to the true exponent. Biased
exponent = 2000 + 3.
4 Assemble number in floating point format.
Coefficient = 400 000 000 0008
Biased Exponent = 20038
Assembled word = 2003 400 000 000 0008
5 Since the sign of the coefficient is positive, the
floating point representation of +4.0 is as
shown. If, however, the sign of the coefficient
were negative, it would be necessary to complement the entire floating point word.
1 The number is expressed in octal.
2 Normalize. -4.0 = -4.0 x 8° = -0.100 x 2 3
3 Since the sign of the true exponent is positive,
add 20008 (bias) to the true exponent. Biased
exponent = 2000 + 3.
4 Assemble number in floating point format.
Coefficient = 400000000 OOOa
Biased Exponent = 20038
Assembled word = 20034000000000008
5 Since the sign of the coefficient is negative,
the assembled floating point word must be
complemented. Therefore, the true floating
point representation for
-4.0 = 57743777777777778
EXAMPLE 3
Convert 0.510 to floating point
2 Normalize. 0.4 = 0.4 x 80 = 0.100 x 20
3 Since the sign of the true exponent is positive,
add 20008 (bias) to the true exponent. Biased
exponent = 2000 + O.
4 Assemble number in floating point format.
Coefficient = 400000000 0008
Biased Exponent = 2000a
Assembled word = 2000 400 000 000 0008
5 Since the sign of the coefficient is positive, the
floating point representation of +0.510 is as
shown. If, however, the sign of the coefficient
were negative, it would be necessary to complement the entire floating point word. This
example is a special case of floating point
since the exponent of the normalized number
is 0 and could be represented as -0. The exponent would then be biased by 17778 instead
of 20008 because of the negative exponent.
The 3200, however, recognizes -0 as +0 and
biases the exponent by 20008.
Convert 0.048 to floating point
0.100 x 2-
2 If the biased exponent is equal to or greater
than 20008 subtract 20008 to obtain the true
exponent. If less than 20008 subtract 17778
to obtain true exponent.
3 Separate the coefficient and exponent. If the
true exponent is negative the binary point
should be moved to the left the number of bit
positions indicated by the true exponent. If the
true exponent is positive, the binary point
should be moved to the right the number of
bit positions indicated by the true exponent.
fixed binary. The sign of the coefficient will be
negative if the floating point number was complemented in step one. (The sign bit must be
extended if the quantity is placed in a register.)
5 Represent the fixed binary number in fixed
octal notation.
EXAMPLE 1
Convert floating point number
2003400000000,0008 to
fixed octal
The floating point number is positive and remains uncomplemented.
2 The biased exponent> 20008, therefore subtract 2000a from the biased exponent to obtain the true exponent of the number. 2003 -
2000 = +3
3 Coefficient = 400 000 000 0008 = .1002.
Move binary point to the right 3 places. Coefficient = 100.02.
4 The sign of the coefficient is positive because
the floating point number was not complemented in step one.
5 Represent in fixed octal notation.
1 The number is expressed in octal.
2 Normalize. 0.04 = 0.04 x 80 = 0.4 x 8 -
If the floating point number is negative, complement the entire floating point word and
record the fact that the quantity is negative.
The exponent is now in a true biased form.
4 The coefficient has now been converted to
Convert to octal. 0.510 = 0.48
EXAMPLE 4
shown. If, however, the sign of the coefficient
were negative, it would be necessary to complement the entire floating point word.
Floating Point to Fixed Point Format
Convert -4.0 to floating point
EXAM PLE 2
5 Since the sign of the coefficient is positive, the
floating point representation of 0.048 is as
1
100.0 x 2° = 4.0 x 8°.
3
3 Since the sign of the true exponent is negative, add 17778 (bias) to the true exponent.
Biased exponent = 17778 + (-3) = 17748.
4 Assemble number in floating point format.
Coefficient = 4000000000008
Biased Exponent =17748
Assembled word = 17744000000000008
EXAMPLE 2
Convert floating point number
5774377 777 777 7778 to fixed octal
The sign of the coefficient is negative, therefore, complement the floating point n\Jmber.
Complement = 2003 400 000000 0008
2 The biased exponent (in complemented form)
> 20008, therefore subtract 20008 from the
C-7
biased exponent to obtain the true exponent
of the number. 2003 - 2000 = +3
The floating point number is positive and
remains uncomplemented.
3 Coefficient = 4000 000 000 0008 = 0.1002
Move binary point to the right 3 places.
Coefficient = 100.02
2 The biased exponent < 20008, therefore subtract 17778 from the biased exponent to obtain the true exponent of the number. 17748-
4 The sign of the coefficient will be negative
because the floating point number was originally complemented.
5 Convert to fixed octal. -100.02 = -4.08
EXAMPLE 3
=
-3
Convert floating point number
4 The sign of the coefficient is positive because
the floating point number was not complemented in step one.
1774 400 000 000 0008
S Represent in fixed octal notation .
to fixed octal
C-8
17778
3 Coefficient = 400000000 0008 = .1002
Move binary point to the left 3 places.
Coefficient = .0001002
.0001 002
=
.048
Appendix D
Table of Powers of Two
TABLE OF POWERS OF TWO
2n
n
2-n
1
2
4
8
0
1
2
3
1.0
0.5
0.25
0.125
16
32
64
128
4
5
6
7
0.062
0.031
0.015
0.007
5
25
625
812 5
256
512
1 024
2 048
8
9
10
11
0.003
0.001
0.000
0.000
906
953
976
488
25
125
562 5
281 25
4
8
16
32
096
192
384
768
12
13
14
15
0.000
0.000
0.000
0.000
244
122
061
030
140
070
035
517
625
312 5
156 25
578 125
65
131
262
524
536
072
144
288
16
17
18
19
0.000
0.000
0.000
0.000
015
007
003
001
258
629
814
907
789
394
697
348
062
531
265
632
5
25
625
812 5
1
2
4
8
048
097
194
388
576
152
304
608
20
21
22
23
0.000
0.000
0.000
0.000
000
000
000
000
953
476
238
119
674
837
418
209
316
158
579
289
406
203
101
550
25
125
562 5
781 25
16
33
67
134
777
554
108
217
216
432
864
728
24
25
26
27
0.000
0.000
0.000
0.000
000
000
000
000
059
029
014
007
604
802
901
450
644
322
161
580
775
387
193
596
390
695
847
923
625
312 5
656 25
828 125
268
536
1 073
2 147
435
870
741
483
456
912
824
648
28
29
30
31
0.000
0.000
0.000
0.000
000
000
000
000
003
001
000
000
725
862
931
465
290
645
322
661
298
149
574
287
461
230
615
307
914
957
478
739
062
031
515
257
5
25
625
812 5
4
8
17
34
294
589
179
359
967
934
869
738
296
592
184
368
32
33
34
35
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
232
116
058
029
830
415
207
103
643
321
660
830
653
826
913
456
869
934
467
733
628
814
407
703
906
453
226
613
25
125
562 5
281 25
68
137
274
549
719
438
877
755
476
953
906
813
736
472
944
888
36
37
38
39
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
014
007
003
001
551
275
637
818
915
957
978
989
228
614
807
403
366
183
091
545
851
425
712
856
806
903
951
475
640
320
660
830
625
312 5
156 25
078 125
D-l
Appendix E
Octal-Decimal I nteger Conversion Table
OCTAL-DECIMAL INTEGER CONVERSION TABLE
0
1
2
3
4
0
1
2
3
4
5
6
7
0000
0010
0020
0030
0040
0050
0060
0070
0000
0008
0016
0024
0032
0040
0048
0056
0001
0009
0017
0025
0033
0041
0049
0057
0002
0010
0018
0026
0034
0042
0050
0058
0003
0011
0019
0027
0035
0043
0051
0059
0004
0012
0020
0028
0036
0044
0052
0060
0005
0013
0021
0029
0037
0045
0053
0061
0006
0014
0022
0030
0038
0046
0054
0062
0007
0015
0023
0031
0039
0047
0055
0063
0400
0410
0420
0430
0440
0450
0460
0470
0256
0264
0272
0280
0288
0296
0304
0312
0257
0265
0273
0281
0289
0297
0305
0313
0258
0266
0274
0282
0290
0298
0306
0314
0259
0267
0275
0283
0291
0299
0307
0315
0260
0268
0276
0284
0292
0300
0308
0316
0261
0269
0277
0285
0293
0301
0309
0317
0262
0270
0278
0286
0294
0302
0310
0318
0263
0271
0279
0287
0295
0303
0311
0319
0100
0110
0120
0130
0140
0150
0160
0170
0064
0072
0080
0088
0096
0104
0112
0120
0065
0073
0081
0089
0097
0105
0113
0121
0066
0074
0082
0090
0098
0106
0114
0122
0067
0075
0083
0091
0099
0107
0115
0123
0068
0076
0084
0092
0100
0108
0116
0124
0069
0077
0085
0093
0101
0109
0117
0125
0070
0078
0086
0094
0102
0110
0118
0126
0071
0079
0087
0095
0103
0111
0119
0127
0500
0510
0520
0530
0540
0550
0560
0570
0320
0328
0336
0344
0352
0360
0368
0376
0321
0329
0337
0345
0353
0361
0369
0377
0322
0330
0338
0346
0354
0362
0370
0378
0323
0331
0339
0347
0355
0363
0371
0379
0324
0332
0340
0348
0356
0364
0372
0380
0325
0333
0341
0349
0357
0365
0373
0381
0326
0334
0342
0350
0358
0366
0374
0382
0327
0335
0343
0351
0359
0367
0375
0383
0200
0210
0220
0230
0240
0250
0260
0270
0128
0136
0144
0152
0160
0168
0176
0184
0129
0137
0145
0153
0161
0169
0177
0185
0130
0138
0146
0154
0162
0170
0178
0186
0131
0139
0147
0155
0163
0171
0179
0187
0132
0140
0148
0156
0164
0172
0180
0188
0133
0141
0149
0157
0165
0173
0181
0189
0134
0142
0150
0158
0166
0174
0182
0190
0135
0143
0151
0159
0167
0175
0183
0191
0600
0610
0620
0630
0640
0650
0660
0670
0384
0392
0400
0408
0416
0424
0432
0440
0385
0393
0401
0409
0417
0425
0433
0441
0386
0394
0402
0410
0418
0426
0434
0442
0387
0395
0403
0411
0419
0427
0435
0443
0388
0396
0404
0412
0420
0428
0436
0444
0389
0397
0405
0413
0421
0429
0437
0445
0390
0398
0406
0414
0422
0430
0438
0446
0391
0399
0407
0415
0423
0431
0439
0447
0300
0310
0320
0330
0340
0350
0360
0370
0192
0200
0208
0216
0224
0232
0240
0248
0193
0201
0209
0217
0225
0233
0241
0249
0194
0202
0210
0218
0226
0234
0242
0250
0195
0203
0211
0219
0227
0235
0243
0251
0196
0204
0212
0220
0228
0236
0244
0252
0197
0205
0213
0221
0229
0237
0245
0253
0198
0206
0214
0222
0230
0238
0246
0254
0199
0207
0215
0223
0231
0239
0247
0255
0700
0710
0720
0730
0740
0750
0760
0770
0448
0456
0464
0472
0480
0488
0496
0504
0449
0457
0465
0473
0481
0489
0497
0505
0450
0458
0466
0474
0482
0490
0498
0506
0451
0459
0467
0475
0483
0491
0499
0507
0452
0460
0468
0476
0484
0492
0500
0508
0453
0461
0469
0477
0485
0493
0501
0509
0454
0462
0470
0478
0486
0494
0502
0510
0455
0463
0471
0479
0487
0495
0503
0511
0
1
2
3
4
5
0
1
2
3
4
6
7
1000
1010
1020
1030
1040
1050
1060
1070
0512
0520
0528
0536
0544
0552
0560
0568
0513
0521
0529
0537
0545
0553
0561
0569
0514
0522
0530
0538
0546
0554
0562
0570
0515
0523
0531
0539
0547
0555
0563
0571
0516
0524
0532
0540
0548
0556
0564
0572
0517
0525
0533
0541
0549
0557
0565
0573
0518
0526
0534
0542
0550
0558
0566
0574
0519
0527
0535
0543
0551
0559
0567
0575
1400
1410
1420
1430
1440
1450
1460
1470
0768
0776
0784
0792
0800
0808
0816
0824
0769
0777
0785
0793
0801
0809
0817
0825
0770
0778
0786
0794
0802
0810
0818
0826
0771
0779
0787
0795
0803
0811
0819
0827
0772
0780
0788
0796
0804
0812
0820
0828
0773
0781
0789
0797
0805
0813
0821
0829
0774
0782
0790
0798
0806
0814
0822
0830
0775
0783
0791
0799
0807
0815
0823
0831
1100
1110
1120
1130
1140
1150
1160
1170
0576
0584
0592
0600
0608
0616
0624
0632
0577
0585
0593
0601
0609
0617
0625
0633
0578
0586
0594
0602
0610
0618
0626
0634
0579
0587
0595
0603
0611
0619
0627
0635
0580
0588
0596
0604
0612
0620
0628
0636
0581
0589
0597
0605
0613
0621
0629
0637
0582
0590
0598
0606
0614
0622
0630
0638
0583
0591
0599
0607
0615
0623
0631
0639
1500
1510
1520
1530
1540
1550
1560
1570
0832
0840
0848
0856
0864
0872
0880
0888
0833
0841
0849
0857
0865
0873
0881
0889
0834
0842
0850
0858
0866
0874
0882
0890
0835
0843
0851
0859
0867
0875
0883
0891
0836
0844
0852
0860
0868
0876
0884
0892
0837
0845
0853
0861
0869
0877
0885
0893
0838
0846
0854
0862
0870
0878
0886
0894
0839
0847
0855
0863
0871
0879
0887
0895
1200
1210
1220
1230
1240
1250
1260
1270
0640
0648
0656
0664
0672
0680
0688
0696
0641
0649
0657
0665
0673
0681
0689
0697
0642
0650
0658
0666
0674
0682
0690
0698
0643
0651
0659
0667
0675
0683
0691
0699
0644
0652
0660
0668
0676
0684
0692
0700
0645
0653
0661
0669
0677
0685
0693
0701
0646
0654
0662
0670
0678
0686
0694
0702
0647
0655
0663
0671
0679
0687
0695
0703
1600
1610
1620
1630
1640
1650
1660
1670
OB96
0904
0912
0920
0928
0936
0944
0952
OB97
0905
0913
0921
0929
0937
0945
0953
OB9B
0906
0914
0922
0930
0938
0946
0954
OB99
0907
0915
0923
0931
0939
0947
0955
0900
0908
0916
0924
0932
0940
0948
0956
0901
0909
0917
0925
0933
0941
0949
0957
0902
0910
0918
0926
0934
0942
0950
0958
0903
0911
0919
0927
0935
0943
0951
0959
1300
1310
1320
1330
1340
1350
1360
1370
0704
0712
0720
0728
0736
0744
0752
0760
0705
0713
0721
0729
0737
0745
0753
0761
0706
0714
0722
0730
0738
0746
0754
0762
0707
0715
0723
0731
0739
0747
0755
0763
0708
0716
0724
0732
0740
0748
0756
0764
0709
0717
0725
0733
0741
0749
0757
0765
0710
0718
0726
0734
0742
0750
0758
0766
0711
0719
0727
0735
0743
0751
0759
0767
1700
1710
1720
1730
1740
1750
1760
1770
0960
0968
0976
0984
0992
1000
1008
1016
0961
0969
0977
0985
0993
1001
1009
1017
0962
0970
0978
0986
0994
1002
1010
1018
0963
0971
0979
0987
0995
1003
1011
1019
0964
0972
0980
0988
0996
1004
1012
1020
0965
0973
0981
0989
0997
1005
1013
1021
0966
0974
0982
0990
0998
1006
1014
1022
0967
0975
0983
0991
0999
1007
1015
1023
5
6
6
7
7
5
0000
0000
to
to
0777
(Octal)
0511
(Decimal)
Octal
Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
1000
to
1777
(Detail
0512
to
1023
(Decimal)
E-l
OCTAL-DECIMAL INTEGER CONVERSION TABLE
2000
to
2777
(Octall
1024
to
1535
(Decimall
Octal Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
3000
to
3777
(Detail
E-2
1536
to
2047
(Decimal!
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
2000
2010
2020
2030
2040
2050
2060
2070
1024
1032
1040
1048
1056
1064
1072
1080
1025
1033
1041
1049
1057
1065
1073
1081
1026
1034
1042
1050
1058
1066
1074
1082
1027
1035
1043
1051
1059
1067
1075
1083
1028
1036
1044
1052
1060
1068
1076
1084
1029
1037
1045
1053
1061
1069
1077
1085
1030
1038
1046
1054
1062
1070
1078
1086
1031
1039
1047
1055
1063
1071
1079
1087
2400
2410
2420
2430
2440
2450
2460
2470
1280
1288
1296
1304
1312
1320
1328
1336
1281
1289
1297
1305
1313
1321
1329
1337
1282
1290
1298
1306
1314
1322
1330
1338
1283
1291
1299
1307
1315
1323
1331
1339
1284
1292
1300
1308
1316
1324
1332
1340
1285
1293
1301
1309
1317
1325
1333
1341
1286
1294
1302
1310
1318
1326
1334
1342
1287
1295
1303
1311
1319
1327
1335
1343
2100
2100
2120
2130
2140
2150
2160
2170
1088
1096
1104
1112
1120
1128
1136
1144
1089
1097
1105
1113
1121
1129
1137
1145
1090
1098
1106
1114
1122
1130
1138
1146
1091
1099
1107
1115
1123
1131
1139
1147
1092
1100
1108
1116
1124
1132
1140
1148
1093
1101
1109
1117
1125
1133
1141
1149
1094
1102
1110
1118
1126
1134
1142
1150
1095
1103
1111
1119
1127
1135
1143
1151
2500
2510
2520
2530
2540
2550
2560
2570
1344
1352
1360
1368
1376
1384
1392
1400
1345
1353
1361
1369
1377
1385
1393
1401
1346
1354
1362
1370
1378
1386
1394
1402
1347
1355
1363
1371
1379
1387
1395
1403
1348
1356
1364
1372
1380
1388
1396
1404
1349
1357
1365
1373
1381
1389
1397
1405
1350
1358
1366
1374
1382
1390
1398
1406
1351
1359
1367
1375
1383
1391
1399
1407
2200
2210
2220
2230
2240
2250
2260
2270
1152
1160
1168
1176
1184
1192
1200
1208
1153
1161
1169
1177
1185
1193
1201
1209
1154
1162
1170
1178
1186
1194
1202
1210
1155
1163
1171
1179
1187
1195
1203
1211
1156
1164
1172
1180
1188
1196
1204
1212
1157
1165
1173
1181
1189
1197
1205
1213
1158
1166
1174
1182
1190
1198
1206
1214
1159
1167
1175
1183
1191
1199
1207
1215
2600
2610
2620
2630
2640
2650
2660
2670
1408
1416
1424
1432
1440
1448
1456
1464
1409
1417
1425
1433
1441
1449
1457
1465
1410
1418
1426
1434
1442
1450
1458
1466
1411
1419
1427
1435
1443
1451
1459
1467
1412
1420
1428
1436
1444
1452
1460
1468
1413
1421
1429
1437
1445
1453
1461
1469
1414
1422
1430
1438
1446
1454
1462
1470
1415
1423
1431
1439
1447
1455
1463
1471
2300
2310
2320
2330
2340
2350
2360
2370
1216
1224
1232
1240
1248
1256
1264
1272
1217
1225
1233
1241
1249
1257
1265
1273
1218
1226
1234
1242
1250
1258
1266
1274
1219
1227
1235
1243
1251
1259
1267
1275
1220
1228
1236
1244
1252
1260
1268
1276
1221
1229
1237
1245
1253
1261
1269
1277
1222
1230
1238
1246
1254
1262
1270
1278
1223
1231
1239
1247
1255
1263
1271
1279
2700
2710
2720
2730
2740
2750
2760
2770
1472
1480
1488
1496
1504
1512
1520
1528
1473
1481
1489
1497
1505
1513
1521
1529
1474
1482
1490
1498
1506
1514
1522
1530
1475
1483
1491
1499
1507
1515
1523
1531
1476
1484
1492
1500
1508
1516
1524
1532
1477
1485
1493
1501
1519
1517
1525
1533
1478
1486
1494
1502
1510
1518
1526
1534
1479
1487
1495
1503
1511
1519
1527
1535
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
3000
3010
3020
3030
3040
3050
3060
3070
1536
1544
1552
1560
1568
1576
1584
1592
1537
1545
1553
1561
1569
1577
1585
1593
1538
1546
1554
1562
1570
1578
1586
1594
1539
1547
1555
1563
1571
1579
1587
1595
1540
1548
1556
1564
1572
1580
1588
1596
1541
1549
1557
1565
1573
1581
1589
1597
1542
1550
1558
1566
1574
1582
1590
1598
1543
1551
1559
1567
1575
1583
1591
1599
3400
3410
3420
3430
3440
3450
3460
3470
1792
1800
1808
1816
1824
1832
1840
1848
1793
1801
1809
1817
1825
1833
1841
1849
1794
1802
1810
1818
1826
1834
1842
1850
1795
1803
1811
1819
1827
1835
1843
1851
1796
1804
1812
1820
1828
1836
1844
1852
1797
1805
1813
1821
1829
1837
1845
1853
1798
1806
1814
1822
1830
1838
1846
1854
1799
1807
1815
1823
1831
1839
1847
1855
3100
3110
3120
3130
3140
3150
3160
3170
1600
1608
1616
1624
1632
1640
1648
1656
1601
1609
1617
1625
1633
1641
1649
1657
1602
1610
1618
1626
1634
1642
1650
1658
1603
1611
1619
1627
1635
1643
1651
1659
1604
1612
1620
1628
1636
1644
1652
1660
1605
1613
1621
1629
1637
1645
1653
1661
1606
1614
1622
1630
1638
1646
1654
1662
1607
1615
1623
1631
1639
1647
1655
1663
3500
3510
3520
3530
3540
3550
3560
3570
1856
1864
1872
1880
1888
1896
1904
1912
1857
1865
1873
1881
1889
1897
1905
1913
1858
1866
1874
1882
1890
1898
1906
1914
1859
1867
1875
1883
1891
1899
1907
1915
1860
1868
1876
1884
1892
1900
1908
1916
1861
1869
1877
1885
1893
1901
1909
1917
1862
1870
1878
1886
1894
1902
1910
1918
1863
1871
1879
1887
1895
1903
1911
1919
3200
3210
3220
3230
3240
3250
3260
3270
1664
1672
1680
1688
1696
1704
1712
1720
1665
1673
1681
1689
1697
1705
1713
1721
1666
1674
1682
1690
1698
1706
1714
1722
1667
1675
1683
1691
1699
1707
1715
1723
1668
1676
1684
1692
1700
1708
1716
1724
1669
1677
1685
1693
1701
1709
1717
1725
1670
1678
1686
1694
1702
1710
1718
1726
1671
1679
1687
1695
1703
1711
1719
1727
3600
3610
3620
3630
3640
3650
3660
3670
1920
1928
1936
1944
1952
1960
1968
1976
1921
1929
1937
1945
1953
1961
1969
1977
1922
1930
1938
1946
1954
1962
1970
1978
1923
1931
1939
1947
1955
1963
1971
1979
1924
1932
1940
1948
1956
1964
1972
1980
1925
1933
1941
1949
1957
1965
1973
1981
1926
1934
1942
1950
1958
1966
1974
1982
1927
1935
1943
1951
1959
1967
1975
1983
3300
3310
3320
3330
3340
3350
3360
3370
1728
1736
1744
1752
1760
1768
1776
1784
1729
1737
1745
1753
1761
1769
1777
1785
1730
1738
1746
1754
1762
1770
1778
1786
1731
1739
1747
1755
1763
1771
1779
1787
1732
1740
1748
1756
1764
1772
1780
1788
1733
1741
1749
1757
1765
1773
1781
1789
1734
1742
1750
1758
1766
1774
1782
1790
1735
1743
1751
1759
1767
1775
1783
1791
3700
3710
3720
3730
3740
3750
3760
3770
1984
1992
2000
2008
2016
2024
2032
2040
1985
1993
2001
2009
2017
2025
2033
2041
1986
1994
2002
2010
2018
2026
2034
2042
1987
1995
2003
2011
2019
2027
2035
2043
1988
1996
2004
2012
2020
2028
2036
2044
1989
1997
2005
2013
2021
2029
2037
2045
1990
1998
2006
2014
2022
2030
2038
2046
1991
1999
2007
2015
2023
2031
2039
2047
7
OCTAL-DECIMAL INTEGER CONVERSION TABLE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4000
4010
4020
4030
4040
4050
4060
4070
2048
2056
2064
2072
2080
2088
2096
2104
2049
2057
2065
2073
2081
2089
2097
2105
2050
2058
2066
2074
2082
2090
2098
2106
2051
2059
2067
2075
2083
2091
2099
2107
2052
2060
2068
2076
2084
2092
2100
2108
2053
2061
2069
2077
2085
2093
2101
2109
2054
2062
2070
2078
2086
2094
2102
2110
2055
2063
2071
2079
2087
2095
2103
2111
4400
4410
4420
4430
4440
4450
4460
4470
2304
2312
2320
2328
2336
2344
2352
2360
2305
2313
2321
2329
2337
2345
2353
2361
2306
2314
2322
2330
2338
2346
2354
2362
2307
2315
2323
2331
2339
2347
2355
2363
2308
2316
2324
2332
2340
2348
2356
2364
2309
2317
2325
2333
2341
2349
2357
2365
2310
2318
2326
2334
2342
2350
2358
2366
2311
2319
2327
2335
2343
2351
2359
2367
4100
4110
4120
4130
4140
4150
4160
4170
2112
2120
2128
2136
2144
2152
2160
2168
2113
2121
2129
2137
2145
2153
2161
2169
2114
2122
2130
2138
2146
2154
2162
2170
2115
2123
2131
2139
2147
2155
2163
2171
2116
2124
2132
2140
2148
2156
2164
2172
2117
2125
2133
2141
2149
2157
2165
2173
2118
2126
2134
2142
2150
2158
2166
2174
2119
2127
2135
2143
2151
2159
2167
2175
4500
4510
4520
4530
4540
4550
4560
4570
2368
2376
2384
2392
2400
2408
2416
2424
2369
2377
2385
2393
2401
2409
2417
2425
2370
2378
2386
2394
2402
2410
2418
2426
2371
2379
2387
2395
2403
2411
2419
2427
2372
2380
2388
2396
2404
2412
2420
2428
2373
2381
2389
2397
2405
2413
2421
2429
2374
2382
2390
2398
2406
2414
2422
2430
2375
2383
2391
2399
2407
2415
2423
2431
4200
4210
4220
4230
4240
4250
4260
4270
2176
2184
2192
2200
2208
2216
2224
2232
2177
2185
2193
2201
2209
2217
2225
2233
2178
2186
2194
2202
2210
2218
2226
2234
2179
2187
2195
2203
2211
2219
2227
2235
2180
2188
2196
2204
2212
2220
2228
2236
2181
2189
2197
2205
2213
2221
2229
2237
2182
2190
2198
2206
2214
2222
2230
2238
2183
2191
2199
2207
2215
2223
2231
2239
4600
4610
4620
4630
4640
4650
4660
4670
2432
2440
2448
2456
2464
2472
2480
2488
2433
2441
2449
2457
2465
2473
2481
2489
2434
2442
2450
2458
2466
2474
2482
2490
2435
2443
2451
2459
2467
2475
2483
2491
2436
2444
2452
2460
2468
2476
2484
2492
2437
2445
2453
2461
2469
2477
2485
2493
2438
2446
2454
2462
2470
2478
2486
2494
2439
2447
2455
2463
2471
2479
2487
2495
4300
4310
4320
4330
4340
4350
4360
4370
2240
2248
2256
2264
2272
2280
2288
2296
2241
2249
2257
2265
2273
2281
2289
2297
2242
2250
2258
2266
2274
2282
2290
2298
2243
2251
2259
2267
2275
2283
2291
2299
2244
2252
2260
2268
2276
2284
2292
2300
2245
2253
2261
2269
2277
2285
2293
2301
2246
2254
2262
2270
2278
2286
2294
2302
2247
2255
2263
2271
2279
2287
2295
2303
4700
4710
4720
4730
4740
4750
4760
4770
2496
2504
2512
2520
2528
2536
2544
2552
2497
2505
2513
2521
2529
2537
2545
2553
2498
2506
2514
2522
2530
2538
2546
2554
2499
2507
2515
2523
2531
2539
2547
2555
2500
2508
2516
2524
2532
2540
2548
2556
2501
2509
2517
2525
2533
2541
2549
2557
2502
2510
2518
2526
2534
2542
2550
2558
2503
2511
2519
2527
2535
2543
2551
2559
1
2
4
5
6
7
0
1
2
3
4
5
6
7
0
3
5000
5010
5020
5030
5040
5050
5060
5070
2560
2568
2576
2584
2592
2600
2608
2616
2561
2569
2577
2585
2593
2601
2609
2617
2562
2570
2578
2586
2594
2602
2610
2618
2563
2571
2579
2587
2595
2603
2611
2619
2564
2572
2580
2588
2596
2604
2612
2620
2565
2573
2581
2589
2597
2605
2613
2621
2566
2574
2582
2590
2598
2606
2614
2622
2567
2575
2583
2591
2599
2607
2615
2623
5400
5410
5420
5430
5440
5450
5460
5470
2816
2824
2832
2840
2848
2856
2864
2872
2817
2825
2833
2841
2849
2857
2865
2873
2818
2826
2834
2842
2850
2858
2866
2874
2819
2827
2835
2843
2851
2859
2867
2875
2820
2828
2836
2844
2852
2860
2868
2876
2821
2829
2837
2845
2853
2861
2869
2877
2822
2830
2838
2846
2854
2862
2870
2878
2823
2831
2839
2847
2855
2863
2871
2879
5100
5110
5120
5130
5140
5150
5160
5170
2624
2632
2640
2648
2656
2664
2672
2680
2625
2633
2641
2649
2657
2665
2673
2681
2626
2634
2642
2650
2658
2666
2674
2682
2627
2635
2643
2651
2659
2667
2675
2683
2628
2636
2644
2652
2660
2668
2676
2684
2629
2637
2645
2653
2661
2669
2677
2685
2630
2638
2646
2654
2662
2670
2678
2686
2631
2639
2647
2655
2663
2671
2679
2687
5500
5510
5520
5530
5540
5550
5560
5570
2880
2888
2896
2904
2912
2920
2928
2936
2881
2889
2897
2905
2913
2921
2929
2937
2882
2890
2898
2906
2914
2922
2930
2938
2883
2891
2899
2907
2915
2923
2931
2939
2884
2892
2900
2908
2916
2924
2932
2940
2885
2893
2901
2909
2917
2925
2933
2941
2886
2894
2902
2910
2918
2926
2934
2942
2887
2895
2903
2911
2919
2927
2935
2943
5200
5210
5220
5230
5240
5250
5260
5270
2688
2696
2704
2712
2720
2728
2736
2744
2689
2697
2705
2713
2721
2729
2737
2745
2690
2698
2706
2714
2722
2730
2738
2746
2691
2699
2707
2715
2723
2731
2739
2747
2692
2700
2708
2716
2724
2732
2740
2748
2693
2701
2709
2717
2725
2733
2741
2749
2694
2702
2710
2718
2726
2734
2742
2750
2695
2703
2711
2719
2727
2735
2743
2751
5600
5610
5620
5630
5640
5650
5660
5670
2944
2952
2960
2968
2976
2984
2992
3000
2945
2953
2961
2969
2977
2985
2993
3001
2946
2954
2962
2970
2978
2986
2994
3002
2947
2955
2963
2971
2979
2987
2995
3003
2948
2956
2964
2972
2980
2988
2996
3004
2949
2957
2965
2973
2981
2989
2997
3005
2950
2958
2966
2974
2982
2990
2998
3006
2951
2959
2967
2975
2983
2991
2999
3007
5300
5310
5320
5330
5340
5350
5360
5370
2752
2760
2768
2776
2784
2792
2800
2808
2753
2761
2769
2777
2785
2793
2801
2809
2754
2762
2770
2778
2786
2794
2802
2810
2755
2763
2771
2779
2787
2795
2803
2811
2756
2764
2772
2780
2788
2796
2804
2812
2757
2765
2773
2781
2789
2797
2805
2813
2758
2766
2774
2782
2790
2798
2806
2814
2759
2767
2775
2783
2791
2799
2807
2815
5700
5710
5720
5730
5740
5750
5760
5770
3008
3016
3024
3032
3040
3048
3056
3064
3009
3017
3025
3033
3041
3049
3057
3065
3010
3018
3026
3034
3042
3050
3058
3066
3011
3019
3027
3035
3043
3051
3059
3067
3012
3020
3028
3036
3044
3052
3060
3068
3013
3021
3029
3037
3045
3053
3061
3069
3014
3022
3030
3038
3046
3054
3062
3070
3015
3023
3031
3039
3047
3055
3063
3071
4000
2048
to
to
4777
2559
(Octal)
(Oecimal)
Octal
Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
5000
2560
to
to
5777
3071
(Octal)
(Decimal)
E-3
OCTAL-DECIMAL INTEGER CONVERSION TABLE
6000
to
6777
10ctal)
3072
to
3583
IDec:imal)
Octal Dec:imal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
7000
to
7777
10ctal)
E-4
3584
to
4095
IDecimal)
0
1
2
3
4
6000
6010
6020
6030
6040
6050
6060
6070
3072
3080
3088
3096
3104
3112
3120
3128
3073
3081
3089
3097
3105
3113
3121
3129
3074
3082
3090
3098
3106
3114
3122
3130
3075
3083
3091
3099
3107
3115
3123
3131
3076
3084
3092
3100
3108
3116
3124
3132
3077
3085
3093
3101
3109
3117
3125
3133
3078
3086
3094
3102
3110
3118
3126
3134
3079
3087
3095
3103
3111
3119
3127
3135
6100
6110
6120
6130
6140
6150
6160
6170
3136
3144
3152
3160
3168
3176
3184
3192
3137
3145
3153
3161
3169
3177
3185
3193
3138
3146
3154
3162
3170
3178
3186
3194
3139
3147
3155
3163
3171
3179
3187
3195
3140
3148
3156
3164
3172
3180
3188
3196
3141
3149
3157
3165
3173
3181
3189
3197
3142
3150
3158
3166
3174
3182
3190
3198
6200
6210
6220
6230
6240
6250
6260
6270
3200
3208
3216
3224
3232
3240
3248
3256
3201
3209
3217
3225
3233
3241
3249
3257
3202
3210
3218
3226
3234
3242
3250
3258
3203
3211
3219
3227
3235
3243
3251
3259
3204
3212
3220
3228
3236
3244
3252
3260
3205
3213
3221
3229
3237
3245
3253
3261
6300
6310
6320
6330
6340
6350
6360
6370
3264
3272
3280
3288
3296
3304
3312
3320
3265
3273
3281
3289
3297
3305
3313
3321
3266
3274
3282
3290
3298
3306
3314
3322
3267
3275
3283
3291
3299
3307
3315
3323
3268
3276
3284
3292
3300
3308
3316
3324
0
1
2
3
7000
7010
7020
7030
7040
7050
7060
7070
3584
3592
3600
3608
3616
3624
3632
3640
3585
3593
3601
3609
3617
3625
3633
3641
3586
3594
3602
3610
3618
3626
3634
3642
7100
7110
7120
7130
7140
7150
7160
7170
3648
3656
3664
3672
3680
3688
3696
3704
3649
3657
3665
3673
3681
3689
3697
3705
7200
7210
7220
7230
7240
7250
7260
7270
3712
3720
3728
3736
3744
3752
3760
3768
7300
7310
7320
7330
7340
7350
7360
7370
3776
3784
3792
3800
3808
3816
3824
3832
5
6
7
0
1
2
3
6400
6410
6420
6430
6440
6450
6460
6470
3328
3336
3344
3352
3360
3368
3376
3384
3329
3337
3345
3353
3361
3369
3377
3385
3330
3338
3346
3354
3362
3370
3378
3386
3331
3339
3347
3355
3363
3371
3379
3387
3143
3151
3159
3167
3175
3183
3191
3199
6500
6510
6520
6530
6540
6550
6560
6570
3392
3400
3408
3416
3424
3432
3440
3448
3393
3401
3409
3417
3425
3433
3441
3449
3394
3402
3410
3418
3426
3434
3442
3450
3206
3214
3222
3230
3238
3246
3254
3262
3207
3215
3223
3231
3239
3247
3255
3263
6600
6610
6620
6630
6640
6650
6660
6670
3456
3464
3472
3480
3488
3496
3504
3512
3457
3465
3473
3481
3489
3497
3505
3513
3269
3277
3285
3293
3301
3309
3317
3325
3270
3278
3286
3294
3302
3310
3318
3326
3271
3279
3287
3295
3303
3311
3319
3327
6700
6710
6720
6730
6740
6750
6760
6770
3520
3528
3536
3544
3552
3560
3568
3576
4
5
6
7
3587
3595
3603
3611
3619
3627
3635
3643
3588
3496
3604
3612
3620
3628
3636
3644
3589
3497
3605
3613
3621
3629
3637
3645
3590
3598
3606
3614
3622
3630
3638
3646
3591
3599
3607
3615
3623
3631
3639
3647
3650
3658
3666
3674
3682
3690
3698
3706
3651
3659
3667
3675
3683
3691
3699
3707
3652
3660
3668
3676
3684
3692
3700
3708
3653
3661
3669
3677
3685
3693
3701
3709
3654
3662
3670
3678
3686
3694
3702
3710
3713
3721
3729
3737
3745
3753
3761
3769
3714
3722
3730
3738
3746
3754
3762
3770
3715
3723
3731
3739
3747
3755
3763
3771
3716
3724
3732
3740
3748
3756
3764
3772
3717
3725
3733
3741
3749
3757
3765
3773
3777
3785
3793
3801
3809
3817
3825
3833
3778
3786
3794
3802
3810
3818
3826
3834
3779
3787
3795
3803
3811
3819
3827
3835
3780
3788
3796
3804
3812
3820
3828
3836
3781
3789
3797
3805
3813
3821
3829
3837
4
5
6
7
3332
3340
3348
3356
3364
3372
3380
3388
3333
3341
3349
3357
3365
3373
3381
3389
3334
3342
3350
3358
3366
3374
3382
3390
3335
3343
3351
3359
3367
3375
3383
3391
3395
3403
3411
3419
3427
3435
3443
3451
3396
3404
3412
3420
3428
3436
3444
3452
3397
3405
3413
3421
3429
3437
3445
3453
3398 3399
3406 3407
3414 3415
3422 3423
3430 3431
3438 3439
3446 3447
3454 3455
3458
3466
3474
3482
3490
3498
3506
3514
3459
3467
3475
3483
3491
3499
3507
3515
3460
3468
3476
3484
3492
3500
3508
3516
3461
3469
3477
3485
3493
3501
3509
3517
3462
3470
3478
3486
3494
3502
3510
3518
3463
3471
3479
3487
3495
3503
3511
3519
3521
3529
3537
3545
3553
3561
3569
3577
3522
3530
3538
3546
3554
3562
3570
3578
3523
3531
3539
3547
3555
3563
3571
3579
3524
3532
3540
3548
3556
3564
3572
3580
3525
3533
3541
3549
3557
3565
3573
3581
3526
3534
3542
3550
3558
3566
3574
3582
3527
3535
3543
3551
3559
3567
3575
3583
0
1
2
3
4
5
6
7
7400
7410
7420
7430
7440
7450
7460
7470
3840
3848
3856
3864
3872
3880
3888
3896
3841
3849
3857
3865
3873
3881
3889
3897
3842
3850
3858
3866
3874
3882
3890
3898
3843
3851
3859
3867
3875
3883
3891
3899
3844
3852
3860
3868
3876
3884
3892
3900
3845
3853
3861
3869
3877
3885
3893
3901
3846
3854
3862
3870
3878
3886
3894
3902
3847
3855
3863
3871
3879
3887
3895
3903
3655
3663
3671
3679
3687
3695
3703
3711
7500
7510
7520
7530
7540
7550
7560
7570
3904
3912
3920
3928
3936
3944
3952
3960
3905
3913
3921
3929
3937
3945
3953
3961
3906
3914
3922
3930
3938
3946
3954
3962
3907
3915
3923
3931
3939
3947
3955
3963
3908
3916
3924
3932
3940
3948
3956
3964
3909
3917
3925
3933
3941
3949
3957
3965
3910
3918
3926
3934
3942
3950
3958
3966
3911
3919
3927
3935
3943
3951
3959
3967
3718
3726
3734
3742
3750
3758
3766
3774
3719
3727
3735
3743
3751
3759
3767
3775
7600
7610
7620
7630
7640
7650
7660
7670
3968
3976
3984
3992
4000
4008
4016
4024
3969
3977
3985
3993
4001
4009
4017
4025
3970
3978
3986
3994
4002
4010
4018
4026
3971
3979
3987
3995
4003
4011
4019
4027
3972
3980
3988
3996
4004
4012
4020
4028
3973
3981
3989
3997
4005
4013
4021
4029
3974
3982
3990
3998
4006
4014
4022
4030
3975
3983
3991
3999
4007
4015
4023
4031
3782
3790
3798
3806
3814
3822
3830
3838
3783
3791
3799
3807
3815
3823
3831
3839
7700
7710
7720
7730
7740
7750
7760
7770
4032
4040
4048
4056
4064
4072
4080
4088
4033
4041
4049
4057
4065
4073
4081
4089
4034
4042
4050
4058
4066
4074
4082
4090
4035
4043
4051
4059
4067
4075
4083
4091
4036
4044
4052
4060
4068
4076
4084
4092
4037
4045
4053
4061
4069
4077
4085
4093
4038
4046
4054
4062
4070
4078
4086
4094
4039
4047
4055
4063
4071
4079
4087
4095
Appendix F
Octal-Decimal Fraction Conversion Table
OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL
DEC.
OCTAL
DEC.
.125000
.126953
.128906
.130859
.132812
.134765
.136718
.138671
.200
.201
.202
.203
.204
.205
.206
.207
.250000
.251953
.253906
.255859
.257812
.259765
.261718
.263671
.300
.301
.302
.303
.304
.305
.306
.307
.375000
.376953
.378906
.380859
.382812
.384765
.386718
.388671
.110
.111
.112
.113
.114
.115
.116
.117
.140625
.142578
.144531
.146484
.148437
.150390
.152343
.154296
.210
.211
.212
.213
.214
.215
.216
.217
.265625
.267578
.269531
.271484
.273437
.275390
.277343
.279296
.310
.311
.312
.313
.314
.315
.316
.317
.390625
.392578
.394531
.396484
.398437
.400390
.402343
.404296
.031250
.033203
.035156
.037109
.039062
.041015
.042968
.044921
.120
.121
.122
.123
.124
.125
.126
.127
.156250
.158203
.160156
.162109
.164062
.166015
.167968
.169921
.220
.221
.222
.223
.224
.225
.226
.227
.281250
.283203
.285156
.287109
.289062
.291015
.292968
.294921
.320
.321
.322
.323
.324
.325
.326
.327
.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921
.030
.031
.032
.033
.034
.035
.036
.037
.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546
.130
.131
.132
.133
.134
.135
.136
.137
.171875
.173828
.175781
.177734
.179687
.181640
.183593
.185546
.230
.231
.232
.233
.234
.235
.236
.237
.296875
.298828
.300781
.302734
.304687
.306640
.308593
.310546
.330
.331
.332
.333
.334
.335
.336
.337
.421875
.423828
.425781
.427734
.429687
.431640
.433593
.435546
.040
.041
.042
.043
.044
.045
.046
.047
.062500
.064453
.066406
.068359
.070312
.072265
.074218
.076171
.140
.141
.142
.143
.144
.145
.146
.147
.187500
.189453
.191406
.193359
.195312
.197265
.199218
.201171
.240
.241
.242
.243
.244
.245
.246
.247
.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171
.340
.341
.342
.343
.344
.345
.346
.347
.437500
.439453
.441406
.443359
.445312
.447265
.449218
.451171
.050
.051
.052
.053
.054
.055
.056
.057
.078125
.080078
.082031
.083984
.085937
.087890
.089843
.091796
.150
.151
.152
.153
.154
.155
.156
.157
.203125
.205078
.207031
.208984
.210937
.212890
.214843
.216796
.250
.251
.252
.253
.254
.255
.256
.257
.328125
.330078
.332031
.333984
.335937
.337890
.339843
.341796
.350
.351
.352
.353
.354
.355
.356
.357
.453125
.455078
.457031
.458984
.460937
.462890
.464843
.466796
.060
.061
.062
.063
.064
.065
.066
.067
.093750
.095703
.097656
.099609
.101562
.103515
.105468
.107421
.160
.161
.162
.163
.164
.165
.166
.167
.218750
.220703
.222656
.224609
226562
.228515
.230468
.232421
.260
.261
.262
.263
.264
.265
.266
.267
.343750
.345703
.347656
.349609
.351562
.353515
.355468
.357421
.360
.361
.362
.363
.364
.365
.366
.367
.468750
.470703
.472656
.474609
.476562
.478515
.480468
.482421
.070
.071
.072
.073
.074
.075
.076
.077
.109375
.111328
.113281
.115234
.117187
.119140
.121093
.123046
.170
.171
.172
.173
.174
.175
.176
.177
.234375
.236328
.238281
.240234
.242187
.244140
.246093
.248046
.270
.271
.272
.273
.274
.275
.276
.277
.359375
.361328
.363281
.365234
.367187
.369140
.371093
.373046
.370
.371
.372
.373
.374
.375
.376
.377
.484375
.486328
.488281
.490234
.492187
.494140
.496093
.498046
DEC.
OCTAL
.000
.001
.002
.003
.004
.005
.006
.007
.000000
.001953
.003906
.005859
.007812
.009765
.011718
.013671
.100
.101
.102
.103
.104
.105
.106
.107
.010
.011
.012
.013
.014
.015
.016
.017
.015625
.017578
.019531
.021484
.023437
.025390
.027343
.029296
.020
.021
.022
.023
.024
.025
.026
.027
OCTAL
DEC.
F-l
OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL
F-2
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
.000000
.000001
.000002
.000003
.000004
.000005
.000006
.000007
.000000
.000003
.000007
.000011
.000015
.000019
.000022
.000026
.000100
.000101
.000102
.000103
.000104
.000105
.000106
.000107
.000244
.000247
.000251
.000255
.000259
.000263
.000267
.000270
.000200
.000201
.000202
.000203
.000204
.000205
.000206
.000207
.000488
.000492
.000495
.000499
.000503
.000507
.000511
.000514
.000300
.000301
.000302
.000303
.000304
.000305
.000306
.000307
.000732
.000736
.000740
.000743
.000747
.000751
.000755
.000759
.000010
.000011
.000012
.000013
.000014
.000015
.000016
.000017
.000030
.000034
.000038
.000041
.000045
.000049
.000053
.000057
.000110
.000111
.000112
.000113
.000114
.000115
.000116
.000117
.000274
.000278
.000282
.000286
.000289
.000293
.000297
.000301
.000210
.000211
.000212
.000213
.000214
.000215
.000216
.000217
.000518
.000522
.000526
.000530
.000534
.000537
.000541
.000545
.000310
.000311
.000312
.000313
.000314
.000315
.000316
.000317
.000762
.000766
.000770
.000774
.000778
.000782
.000785
.000789
.000020
.000021
.000022
.000023
.000024
.000025
.000026
.000027
.000061
.000064
.000068
.000072
.000076
.000080
.000083
.000087
.000120
.000121
.000122
.000123
.000124
.000125
.000126
.000127
.000305
.000308
.000312
.000316
.000320
.000324
.000328
.000331
.000220
.000221
.000222
.000223
.000224
.000225
.000226
.000227
.000549
.000553
.000556
.000560
.000564
.000568
.000572
.000576
.000320
.000321
.000322
.000323
.000324
.000325
.000326
.000327
.000793
.000797
.000801
.000805
.000808
.000812
.000816
.000820
.000030
.000031
.000032
.000033
.000034
.000035
.000036
.000037
.000091
.000095
.000099
.000102
.000106
.000110
.000114
.000118
.000130
.000131
.000132
.000133
.000134
.000135
.000136
.000137
.000335
.000339
.000343
.000347
.000350
.000354
.000358
.000362
.000230
.000231
.000232
.000233
.000234
.000235
.000236
.000237
.000579
.000583
.000587
.000591
.000595
.000598
.000602
.000606
.000330
.000331
.000332
.000333
.000334
.000335
.000336
.000337
.000823
.000827
.000831
.000835
.000839
.000843
.000846
.000850
.000040
.000041
.000042
.000043
.000044
.000045
.000046
.000047
.000122
.000125
.000129
.000133
.000137
.000141
.000144
.000148
.000140
.000141
.000142
.0001-43
.000144
.000145
.000146
.000147
.000366
.000370
.000373
.000377
.000381
.000385
.000389
.000392
.000240
.000241
.000242
.000243
.000244
.000245
.000246
.000247
.000610
.000614
.000617
.000621
.000625
.000629
.000633
.000637
.000340
.000341
.000342
.000343
.000344
.000345
.000346
.000347
.000854
.000858
.000862
.000865
.000869
.000873
.000877
.000881
.000050
.000051
.000052
.000053
.000054
.000055
.000056
.000057
.000152
.000156
.000160
.000164
.000167
.000171
.000175
.000179
.000150
.000151
.000152
.000153
.000154
.000155
.000156
.000157
.000396
.000400
.000404
.000408
.000411
.000415
.000419
.000423
.000250
.000251
.000252
.000253
.000254
.000255
.000256
.000257
.000640
.000644
.000648
.000652
.000656
.000659
.000663
.000667
.000350
.000351
.000352
.000353
.000354
.000355
.000356
.000357
.000885
.000888
.000892
.000896
.000900
.000904
.000907
.000911
.000060
.000061
.000062
.000063
.000064
.000065
.000066
.000067
.000183
.000186
.000190
.000194
.000198
.000202
.000205
.000209
.000160
.000161
.000162
.000163
.000164
.000165
.000166
.000167
.000427
.000431
.000434
.000438
.000442
.000446
.000450
.000453
.000260
.000261
.000262
.000263
.000264
.000265
.000266
.000267
.000671
.000675
.000679
.000682
.000686
.000690
.000694
.000698
.000360
.000361
.000362
.000363
.000364
.000365
.000366
.000367
.000915
.000919
.000923
.000926
.000930
.000934
.000938
.000942
.000070
.000071
.000072
.000073
.000074
.000075
.000076
.000077
.000213
.000217
.000221
.000225
.000228
.000232
.000236
.000240
.000170
.000171
.000172
.000173
.000174
.000175
.000176
.000177
.000457
.000461
.000465
.000469
.000473
.000476
.000480
.000484
.000270
.000271
.000272
.000273
.000274
.000275
.000276
.000277
.000701
.000705
.000709
.000713
.000717
.000720
.000724
.000728
.000370
.000371
.000372
.000373
.000374
.000375
.000376
.000377
.000946
.000949
.000953
.000957
.000961
.000965
.000968
.000972
OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL
DEC.
.000400
.000401
.000402
.000403
.000404
.000405
.000406
.000407
OCTAL
.000976
.000980
.000984
.000988
.000991
.000995
.000999
.001003
DEC.
.000500
.000501
.000502
.000503
.000504
.000505
.000506
.000507
OCTAL
.001220
.001224
.001228
.001232
.001235
.001239
.001243
.001247
DEC.
.000600
.000601
.000602
.000603
.000604
.000605
.000606
.000607
.001464
.001468
.001472
.001476
.001480
.001483
.001487
.001491
.000700
.000701
.000702
.000703
.000704
.000705
.000706
.000707
.001708
.001712
.001716
.001720
.001724
.001728
.001731
.001735
.000410
.000411
.000412
.000413
.000414
.000415
.000416
.000417
.001007
.001010
.001014
.001018
.001022
.001026
.001029
.001033
.000510
.000511
.000512
.000513
.000514
.000515
.000516
.000517
.001251
.001255
.001258
.001262
.001266
.001270
.001274
.001277
.000610
.000611
.000612
.000613
.000614
.000615
.000616
.000617
.001495
.001499
.001502
.001506
.001510
.001514
.001518
.001522
.000710
.000711
.000712
.000713
.000714
.000715
.000716
.000717
.001739
.001743
.001747
.001750
.001754
.001758
.001762
.001766
.000420
.000421
.000422
.000423
.000424
.000425
.000426
.000427
.001037
.001041
.001045
.001049
.001052
.001056
.001060
.001064
.000520
.000521
.000522
.000523
.000524
.000525
.000526
.000527
.001281
.001285
.001289
.001293
.001296
.001300
.001304
.001308
.000620
.000621
.000622
.000623
.000624
.000625
.000626
.000627
.001525
.001529
.001533
.001537
.001541
.001544
.001548
.001552
.000720
.000721
.000722
.000723
.000724
.000725
.000726
.000727
.001770
.001773
.001777
.001781
.001785
.001789
.001792
.001796
.000430
.000431
.000432
.000433
.000434
.000435
.000436
.000437
.001068
.001071
.001075
.001079
.001083
.001087
.001091
.001094
.000530
.000531
.000532
.000533
.000534
.000535
.000536
.000537
.001312
.001316
.001319
.001323
.001327
.001331
.001335
.001338
.000630
.000631
.000632
.000633
.000634
.000635
.000636
.000637
.001556
.001560
.001564
.001567
.001571
.001575
.001579
.001583
.000730
.000731
.000732
.000733
.000734
.000735
.000736
.000737
.001800
.001804
.001808
.001811
.001815
.001819
.001823
.001827
.000440
.000441
.000442
.000443
.000444
.000445
.000446
.000447
.001098
.001102
.001106
.001110
.001113
.001117
.001121
.001125
.000540
.000541
.000542
.000543
.000544
.000545
.000546
.000547
.001342
.001346
.001350
.001354
.001358
.001361
.001365
.001369
.000640
.000641
.000642
.000643
.000644
.000645
.000646
.000647
.001586
.001590
.001594
.001598
.001602
.001605
.001609
.001613
.000740
.000741
.000742
.000743
.000744
.000745
.000746
.000747
.001831
.001834
.001838
.001842
.001846
.001850
.001853
.001857
.000450
.000451
.000452
.000453
.000454
.000455
.000456
.000457
.001129
.001132
.001136
.001140
.001144
.001148
.001152
.001155
.000550
.000551
.000552
.000553
.000554
.000555
.000556
.000557
.001373
.001377
.001380
.001384
.001388
.001392
.001396
.001399
.000650
.000651
.000652
.000653
.000654
.000655
.000656
.000657
.001617
.001621
.001625
.001628
.001632
.00.1636
.001640
.001644
.000750
.000751
.000752
.000753
.000754
.000755
.000756
.000757
.001861
.001865
.001869
.001873
.001876
.001880
.001884
.001888
.000460
.000461
.000462
.000463
.000464
.000465
.000466
.000467
.001159
.001163
.001167
.001171
.001174
.001178
.001182
.001186
.000560
.000561
.000562
.000563
.000564
.000565
.000566
.000567
.001403
.001407
.001411
.001415
.001419
.001422
.001426
.001430
.000660
.000661
.000662
.000663
.000664
.000665
.000666
.000667
.001647
.001651
.001655
.001659
.001663
.001667
.001670
.001674
.000760
.000761
.000762
.000763
.000764
.000765
.000766
.000767
.001892
.001895
.001899
.001903
.001907
.001911
.001914
.001918
.000470
.000471
.000472
.000473
.000474
.000475
.000476
.000477
.001190
.001194
.001197
.001201
.001205
.001209
.001213
.001216
.000570
.000571
.000572
.000573
.000574
.000575
.000576
.000577
.001434
.001438
.001441
.001445
.001449
.001453
.001457
.001461
.000670
.000671
.000672
.000673
.000674
.000675
.000676
.000677
.001678
.001682
.001686
.001689
.001693
.001697
.001701
.001705
.000770
.000771
.000772
.000773
.000774
.000775
.000776
.000777
.001922
.001926
.001930
.001934
.001937
.001941
.001945
.001949
OCTAL
DEC.
F-3
Appendix G
Definition of liD Interface Signals
DEFINITION OF liD INTERFACE SIGNALS
This appendix defines the signals that are exchanged between the 3106 Data Channel and
external equipment. There are three classes of signals: bidirectional, 3106 to external
equipment, and external equipment to 3106.
Bidirectional Signals
Data Bits
The 12 lines which carry data are bi-directional. and perform
as follows:
1. I n a Read (input) operation, data is transmitted from the
external equipment to the 3106.
2. In a Write (output) operation, data is transmitted from the
3106 to the external equipment.
3. The Connect and Function codes are transmitted from the
3106 to the external equipment via the 12 data lines.
Parity Bit
A parity bit accompanies each 12 bits of data transmitted
between the 3106 and external equipment. Odd parity is
used; thus the total number of "1 's" transmitted is always
an odd number.
3106 to External Equipment
Read
Static" 1 " signal produced by 3106 during a Read operation.
Write
Static" 1" signal produced by 3106 during a Write operation.
Connect
Static" 1 " signal sent to external equipment when 12-bit
Connect code is available on data lines. Signal drops when
external equipment returns Reply or Reject.
Function
Static" 1" signal sent to external equipment when 12-bit
Function code is available on data lines. Signal drops when
external equipment returns Reply or Reject.
Data Signal
Static" 1 " signal sent to external equipment during both
Read and Write operations. Signal drops conditionally when
Reply is received from external equipment.
1. I n a Read operation, Data Signal indicates that 3106 is
ready to accept a 12-bit word from external equipment.
2. I n a Write operation, Data Signal indicates the 3106 has
placed a 12-bit word on the data lines.
G-l
3106 to External equipment (Cont.)
Master Clear
"1" signal from computer which returns channel and external
equipment to zero initial conditions and disconnects external
equipment.
Computer Running
Static" 1 " when computer is operating.
External Equipment to 3106
Reply
Static "1" signal produced by external equipment in response
to a Connect. Function, or Data Signal. Signal drops when
Connect. Function, or Data Signal drops.
1 . If connection can be made when Connect signal is
received, external equipment connects and returns a
Reply.
2. If specified function can be performed when Function
signal is received, external equipment initiates function
and returns a Reply.
3. I n a Read operation, external equipment sends a Reply as
soon as it has placed a 12-bit word on the data lines in
response to the Data Signal.
4. In a Write operation, external equipment sends a Reply
as soon as it samples the data lines in response to the
Data Signal.
G-2
Reject
Static" 1 " signal produced by external equipment in response
to a Connect or Function signal, if the connection cannot be
made or the function cannot be performed at the time that
the external equipment receives the respective signal.
End of Record
Static" 1" signal produced by external equipment during a
Read operation. This signal is produced in response to the
Data Signal, if the end of the specified block of data has
been reached.
Parity Error
Static" 1" signal produced if the total number of "1 's"
in the 12 data bits plus the parity bit is not an odd number.
Status Bits
The external equipment uses the 12 status lines to indicate
its condition.
Interrupt Lines
A "1" signal on an interrupt line indicates that an external
equipment has reached a predetermined condition. A 3106
may communicate with a maximum of 8 external equipments, and each external equipment uses 1 interrupt line.
Appendix H
31 00 System Character Set
3100 SYSTEM CHARACTER SET
Int.
Ext.
Char.
BCD
BCD
Holi.
o
00
12
o
01
01
2
02
02
3
03
4
Char.
Int.
Ext.
BCD
BCD
Holi.
p
47
47
11-7
Q
50
50
11-8
2
R
51
51
11-9
03
3
S
62
22
0-2
04
04
4
T
63
23
0-3
5
05
05
5
u
64
24
0-4
6
06
06
6
V
65
25
0-5
7
07
07
7
W
66
26
0-6
8
10
10
8
X
67
27
0-7
9
11
11
9
y
70
30
0-8
A
21
61
12-1
z
71
31
0-9
B
22
62
12-2
13
13
3-8
C
23
63
12-3
-(dash)
14
14
4-8
o
24
64
12-4
20
60
12
E
25
65
12-5
+
+0
32
72
12-0
F
26
66
12-6
33
73
12-3-8
G
27
67
12-7
34
74
12-4-8
H
30
70
12-8
-(minus)
40
40
11
31
71
12-9
-0
52
52
11-0
J
41
41
1 1-1
$
53
53
11-3-8
K
42
42
11-2
*
54
54
11-4-8
L
43
43
11-3
(space)
60
20
blank
M
44
44
11-4
/
61
21
0-1
N
45
45
11-5
73
33
0-3-8
o
46
46
11-6
74
34
0-4-8
I,_----'-----------'-_----'--_~----'--------'----'---------'
H-l
Appendix I
Peripheral Equipment Codes
Peripheral Equipment
FUNCTION AND STATUS RESPONSE CODES
The following tables list the function and status response codes for the 3248/405 Card
Reader and the 322X and 362X Magnetic Tape Controllers.
Function and status response codes for other 3200 peripheral equipments can be found
in the reference manuals of these equipments.
3248/405 CARD READER CODES
FORMAT AND OPERATIONAL
FUNCTION CODES
0001
0002
0004
0005
Negate Hollerith to Internal BCD Conversion
Release Negate Hollerith to Internal BCD Conversion
Gate Card to Secondary Station
Function Clear
0020
0021
0022
0023
0024
0025
Interrupt on Ready and Not Busy
Release Interrupt on Ready and Not Busy
Interrupt on End of Operation
Release Interrupt on End of Operation
Interrupt on Abnormal End of Operation
Release Interrupt on Abnormal End of Operation
INTERRUPT FUNCTION CODES
STATUS REPLIES
XXXl
XXX2
XXX4
XX1X
XX2X
XX4X
X1XX
X2XX
X4XX
lXXX
2XXX
Reader Ready
Reader Busy
Binary Card
End of File ~Card)
Stacker Full or Jammed or Fail to Feed
Hopper Empty
End of File ~Switch)
Interrupt - Ready and Not Busy
Interrupt - End of Operation
Interrupt - Abnormal End of Operation
Read Compare or Pre-read Error
322X AND 362X MAGNETIC TAPE CONTROLLERS
FORMAT FUNCTION CODES
0000
0001
0002
0003
0004
0006
0005
0041
0040
Release
Binary
Coded
556 BPI Density
200 BPI Density
800 BPI Density
Clear
Reverse Read
Clear Reverse Read
TAPE MOTION FUNCTION CODES
0010
0011
0012
0013
0014
0015
0016
Rewind
Rewind Unload
Backspace
Search End of File Mark Forward
Search End of File Mark Backward
Write End of File Mark
Skip Bad Spot
INTERRUPT FUNCTION CODES
0020
0021
0022
0023
0024
0025
Interrupt On Ready and Not Busy
Release Interrupt on Ready and Not Busy
Interrupt on End of Operation
Release Interrupt on End of Operation
Interrupt on Abnormal End of Operation
Release Interrupt on Abnormal End of Operation
XXXl
XXX2
XXX4
XX1X
XX2X
XX4X
X1XX
Ready
Read/Write Control and/or Busy
Write Enable
File Mark
Load Point
End of Tape
Density
in bit 6 indicates 556 BPI.
"0" in bit 6 and bit 1 indicates 200 BPI)
Density ("1" in bit 1 indicates 800 BPI)
Lost Data
End of Operation
Transverse or Longitudinal Parity Error
STATUS REPLIES
X2XX
X4XX
lXXX
2XXX
r'1"
1-1
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Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Modify Date : 2018:05:07 12:46:23-07:00 Create Date : 2018:05:07 12:46:23-07:00 Metadata Date : 2018:05:07 12:46:23-07:00 Format : application/pdf Document ID : uuid:fe5490cf-82f8-f847-a2fa-2cbf7b0bf74b Instance ID : uuid:bb21f258-3b1c-9f47-81e6-c3835b028272 Page Layout : SinglePage Page Mode : UseOutlines Page Count : 113EXIF Metadata provided by EXIF.tools