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COMPUTER SYSTEM
REFERENCE MANUAL

CONTROL DATA
- . -.

. .

3300 CHARACTERISTICS

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Stored-program, solid- state, scientific and business data proces sing computer
Time- sharing and multiprogramming features
Parallel mode of operation
Diode logic
Character and word addressing (4 characters per word)
Address modification (indexing)
Indirect addressing
28-bit storage word (24 data bits and 4 parity bits)
Nonvolatile magnetic core storage
Complete cycle time: 1.25 microseconds
Access time: 0.75 microsecond
Storage sharing
Selected storage protection
Instruction repertoire compatible with the 3100, 3200, and 3500 Computers
Business oriented Moves, Searches, Edit, Compare, Conversion, arid BCD
arithmetic instructions
.
Logical and sensing operations
Masked storage searches
Block control operations
Trapped instruction processing
24-bit accu;mulator register and auxiliary accumulator register
Binary arithmetic: 227L 1 modulus, one's complement for all single precision (24-bit) operations and double precision (48-bit) addition and subtraction
64-word register file (0.5 microsecond cycle time)
Complete interrupt system
ASCII to BCD conversion (and vice versa) and 4-bit/6-bit packing
Real-time clock (1.0 millisecond incrementation)
Sit-down operator's console featuring: On-line typewriter and complete
display and control system
Upward compatability with 3100 and 3200 co-mputer systems
Standard 3000 Series type 12- bit bidirectional data channel
Compatible I/O mediums include magnetic tape, disk file, punched cards,
paper tape, and printed forms
Options include:
•
Memory expansion to 262,144 words (over 1 million characters)
•
Additional 12-bit data channels or high-speed 24-bit data channels
•
Floating point and 48-bit precision multiply and divide hardware logic
•
Multiprogramming hardware module
•
Business Data Processor
•
Complete selection of advanced peripheral equipment

I"

COMPUTER SYSTEM
REFERENCE MAN UAL

RECORD of REVISIONS
REVISION

NOTES

01 (11-16-65)

Original printing.

A (5-13-66)

Publications Change Order CA13641.

Complete revision.

All previous editions obsolete.

Publication Change Order 14387, no Product Designation change.

B

(9-12-66)

The follbwing pages were

revised or added: iii, v, vii, 1-3, 1-13, 1-14, 2-4, 2-5, 3-1 through 3-8, 4-3, 4-5, 4-8, 4- 9,
5-2, 5-7, 5-12, 5-13, 5-16, 5-18, 5-21, 5-22, 5-30, 5-41, 5-42, 5-68, 5-69, 5-73, 5-75, 5-76,
5-79, 5-80, 5-82, 5-95.0, 5-95.1, 5-96.0, 5-96.1, 5-98 through 5-103, 5-105, 5-106, 5-114
through 5-123, 5-129 through 5-137, 5-140 through 5-147, 5-149, 5 -151, 5-153, 5-154, 5-155,
C-7, E-10 through E-13, Instruction Tables 6, 7, 8, 11, 12, 13, 14, 16, 17, 18, 19, 22, 24, 25,
and 30, Index-I, Index- 2 and Index- 3.

C

Publication Change Order 15865, no Product Designation change.

(2-23-67)

The following pages were

revised or added: iv, v, 1-1, 1-10, 1-13, 1-14, 2-6, 3-3, 3-5, 3-6, 4-2, 4-3, 4-4, 4-5, 4-6,
4-7, 4-8, 4-9, 4-10, 4-11, 5-26, 5-68, 5-69, 5-84, 5-87, 5-89, 5-91, 5-92, 5-94, 5-112, 5-116,
5-117, 5-122, 5-144, 5-147, 5-149, 5 -151, 5-155, Section 6, A-3, A-4, F-7, Index-I, Index-2,
and Index- 3.
1

Engineering/Publications Change Order 16076. The following pages were revised or addeid: v,

D
(6-14-67)

2-5, 2-6, 2-7, 2-8, 2-9 and 5-81.
The following pages were revised

Field Change Order 16164, new Product Designation 3312-A12.

E
(6-14-67)

or added: 5-18, 5-21, 5-82, 5-82.0, D-10, Instruction Tables 8 and 22.
Publications Change Order 16626, no Product Designation change.

F
( 6-14- 67)

revised or added: iii v
5-17

G (10-2-67)

5-20

5-21

5-22

1-8

2-1

2-5, 2-6, 3-6, 3-7

5-25, 5-28, 5-32, 5-33, 5-40, 5-112, 5-113, C-9, D-5, D-6, D-9, D-10,

F-7 Instruction Tables 10 11 12 13 19 21 27 28 and Index- 3.
Publication Change Order 17622. Page 5-155 revised and page 5-156 added.
Publication Change Order 19253, no Product Designation change.

H

(4-4-68)

J
(3-26-69)

The following pages were

4-4, 4-11, 4-12, 5-3, 5-12, 5-13, 5-16,

Pages iii, 1-13, 1-14, 1-15,2-6,

4-6,5-19,5-127,5-147,5-155,C-11,C-12,C-13, Instruction Tables 2, 14, 16 and 26 revised.
Manual revised; includes Engineering Change Order 21959, publication change only. Pages iii,

-.

K
(3-2-70)

4-12,_~::14

5-52 .5.-:.5Ji, 5-68, 5-69, 5-92, 5-98, 5-100, 5-123, 5-125, 5-127 and 5-138 revised.

Manual revised; mcludes Engineering Change Order 24827, publication change only. Pages iii
iv,
vi" 1-3, 1-4, 1-13, 1-14, 1-15, 1-16, 4-6, 4-12, 5-12 through 5-18, 5-21, 5-60, 5-68
through 5-168, Instruction Tables 1-22, Index 1,2,3, Comment Sheet, Quick Reference Instruction

v,

Index revised.

Appendix D, E, F, instruction Tables 23- 33 removed.

Section 8 added.

....ID
I

.-

Address com~ents concerning this
manual to:

Pub No. 60157000

© 1966, 1967,1968,1969, 1970
by Control Data Corporation
Printed in United States of America

Control Data Corporation
Technical Publications Department
4201 North Lexington Avenue
St. Paul, Minnesota 55112
or use Comment Sheet in the back of
this manual.

CONTENTS
1.

General Systems Description

Introduction

1-1

Computer Modularity
Central Processing Unit
Business Data Processors
Optional Business Data
Processing Unit
Storage Modules
Input/ Output Modules
Floating Point Module
Multiprogramming Module
Operator's Console
Power Control Panel

1-2
1- 3
1- 3

Internal Organization
Central Processing Unit
Moves and Edits
Searches
Code Conversion Features
Arithmetic Functions
Peripheral Equipment
2.

Input/Output Relocation

3-7

Auto Load/ Auto Dump

3-7

Interrupt System

General Information
Interrupt Conditions
Internal Condition Interrupts
Input/Output Interrupts
Executive Interrupt
Storage Parity Error Interrupt
Illegal Write Interrupt
Trapped Instruction Interrupts
Power Failure Interrupt

i3
1-14

4-1
4-2
4-2
4-3
4-3
4-4
4-4
4-5
4-6

1

i=

1-15
1-15
1-16

Storage System
2-1

Storage Modules

2-1

Storage Registers

2-1

Storage Word

2-4

Character Modes
Single - Character Mode
Double - Character Mode
Triple - Character Mode
Full - Word Mode
Address Mode

2-4
2-4
2-4
2-4
2-4
2-5

Addressing

2-5

Multiprogramming and Relocation

2-5

Storage Protection
Permanent Protection
Selective Protection
Program Protection
No Protection

2- 5
2-6
2-6
2-9
2- 9

Storage Sharing

2-9

Input/Output System

General Information

3-1

Interface Signals

3-3

3306 and 3307 Communication
Channels

3-4

I/O Parity
Parity Checking with 3306
Parity Checking with 3307

3-6

4.

1- 3
1- 3
1-4
1-4
1-4
1-4
1- 5

General Information

3.

Transmission Rates

;}-4
3-4
3-5
iii

Interrupt Control
4-7
Enabling or Disabling Interrupt
Control
4-7
Interrupt Priority
4-7
Sensing Interrupts
4-8
Clearing Interrupts
4-8

Interrupt Processing
Interrupt Mask Register
Interrupts During Executive Mode
Interrupts During BDP Instructions
5. Instructions
General Information
Instruction Parameters
Instruction Word Formats
Word Addressing vs. Character
Addressing
Indexing and Address Modification
Addressing Modes
Indexing and Indirect Addressing Examples
Trapped Instructions
Instruction List
N 0- Opera tion Instructions
Instruction Execution Times
Halt and Stop Instructions
Enter Instructions
Increase Instructions
Skip Instructions
Inter-Register Transfer
Instructions
Jump Instructions
Load Instructions
Store Instructions
Shift and Scale Instructions
Arithmetic Instructions
Logical Instructions
Masked Search and Compare
Instructions
Rev K

4-8
4-9
4-11
4-12
5-1
5-1
5-4
5- 5
5-6
5-7

5- 9
5-11

5-11
5-18
5-19
5-24
5-25
5-27
5-28
5-32
5-41
5-49
5- 53
5-57
5-60
68
5-

5-73

1

Instructions (Cont'd)
Condition Test Instructions
Sensing Instructions
Pause Instructions
Interrupt Instructions
Input / Output Instructions
Relocation Control Instructions
Multiprocessing Control Instructions
Character Search Instructions
Move Instructions
Business Data Processing Instructions
6.

5-77
5-78
5-82
5-84
5-87
5-109
5-110
5-111
5-115
5-117

Input / Output
RESPOND /MSOS
MSIO
SIPP

6-5
6-6
6-6
6-6

Applications
PERT/TIME
PERT/COST
SORT
Mass Storage SORT
REGINA-I
ADAPT

6-6
6-7
6-7
6-7
6-7
6-7
6-8

7.

Software Systems

Console and Power Control Panel

General Information

General Information

6-1

Operating Systems
Real-Time SCOPE
MASTER
MSOS
SCOPE Utility Routines

6-1
6-2
6-2
6-2
6-2

Languages
FORTRAN-32
Mass Storage FORTRAN
COBOL 32
COBOL 33
Mass Storage COBOL
ALGOL
COMPASS-32
COMPASS-33
Data Processing Package
Report Generator

6-3
6-3
6-3
6-3
6-4
6-4
6-4
6-4
6-5
6-5
6-5

Console
7-2
Register Displays
7-2
Instruction and Communication
Registers
7-2
Instruction State and Operand
State Registers
7- 3
Data Interchange Display
7-3
Status Display
7- 4
Switches and Controls
7- 6
Typewriter
7-19
Power Control Panel
Elapsed Time Meters
Storage Protect Switches
8.

I

B.
C.

Rev. K

Executive Mode
Monitor State
Program State
Multiprogramming and Relocation
Page Structure
Address Relocation
E- Exclusion Bit
Page Zero Consideration

CONTROL DATA 3100, 3200, 3300 Computer Systems Character Set
and BCD/ASCII Code Conversions
Supplementary Arithmetic Information
Programming Reference Tables and Conversion Information
GLOSSARY, INSTRUCTION TABLES, AND INDEX

iv

7-24
7-24
7-24

Multiprogramming and Relocation
Features

APPENDIXES

A.

7-2

8-1
8-1
8-1
8-2
8-3
8-3
8-10
8-14

FIGURES
1-1
1- 2
1-3
1-4
2-1
2-2
3-1
3-2
3-3
5-1
5-2
5-3
5-4
5-5
5- 6
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18

1- 2 7-1
3300 Modularity Example
3300 Console
7-1
7-2
Computer Word Character
Register Display Area
7-2
ISR and OSR Display and
Positions and Bit Assignments 1-5 7-3
Binary Entry Switches
Block Control Scanning Pattern 1-11
7-3
1-12 7-4 Data Interchange Display
Parity Bit Assignments
7-3
Status Display
3300 Storage Modules
2-2 7-5
7-4
7-6
Condition Switches
Optional Protect Scheme
7-7
Access Keyboard Switches
3-2 7-7
3300 I/O System
7-9
7-8
I/O Channel Power Panel
Upper Console Switch Panel
7-10
7-9
Principal Signals Between I/O
Breakpoint Switch Examples
7-17
Channel and External Equipment 3 - 3 7-10 Console Typewriter Control
Word-Addressed Instruction
Switches
7-19
Format
5-4 7-11 Power Control Panel
7-25
Character-Addressed Instruc8-1 Address Relocation Process
8-4
tion Format
5-4
8-2 Word Addressing
8-5
Business Oriented Instruction
8-3 Character Addressing
8-5
5-6
Format
8-4 Program Address Group
8-6
Indexing and Indirect Address8-5 Example of Page Index
5-8
ing Routine Flow Chart
Referencing
8-7
Operand Formats and Bit
8-6 Page Index File Address
Allocations for MUAQ and
:md Hardware Structure
8-8
DV AQ Instructions
5-64 8-7 Relocation System lllustrates
Operand Formats and Bit
Memory Protection with
Allocations for Floating Point
Fully Expanded Memory
5-67
Arithmetic Instructions
(262K)
8-9
77 Connect Operation
5-91
-8 Page Index Format
8-10
&-93
77 Select Function Operation
-9 Relocation Chassis Display
596
Panel
73 I/O Operation with Storage
8-10
-10 Storage Address Buses
74 I/O Operation with Storage 5- 98
8-11
75 I/O Operation with Storage 5-10 -11 Page Length Subdivisions
8-11
76 I/O Operation with Storage 5- 10 -12 Quarter Page in Relation to
5-10
PP Designator
73 I/O Operation with A
8-12
5- 10 - 13 Starting Quarters
74 I/O Operation with A
5- 106
Relative Quarters
75 I/O Operation with A
8-13
5-10
76 I/O Operation with A
5-112
SRCE Operation
5-114
SRCN Operation
5-118
Move Instruction

TABLES
1-1
1-2
2-1
2-2
2-3
4-0

Register File Assignments
Buffer Groups
Storage Protection Switch
Descriptions
Storage Protection Switch
Settings
Optional Storage Protection
Example
Parity Error Interrupt Codes

1-10 4-1
1-11
2-6

4-2

2-7

4-3
4-4
4-5

4-5

v

4-6

Trapped Instruction for
Non-Executive Mode without a
3310 or 3312 Module System
No-Operation Instruction for
Non-Executive Mode
Interrupt Priority
Representative Interrupt Codes
Interrupt Mask Register Bit
Assignments
Condition Register Bit
Assignments
Rev K

4-6
4-6
4-8
4-10
4-11

5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9

RevK

Instruction Synopsis and Index
Summary of Instruction
Execution Times
Interrupt Mask Register Bit
Assignments
Bit Assignments for Interrupt
Sensing Conditions
Internal Status Sensing Mask
Pause Sensing Mask
Interrupt Mask Register Bit
Assignments
Modified 110 Instruction
Words
Block Control Clearing Mask

5-1215-10
5_19 5 - 11
7-1
5--79
7-2
5-79
5-80 7-3
5-82
7-4
7-5
5-85
5-88
5-90

vi

7-6
8- 1

1

BDP Instruction Set
Editing Examples
Data Interchange Indicator
Description
Status Display Indicator
Descriptions
Condition Switches De-=
scription
Access Keyboard Switches
Console Typewriter
Switches and Indicators
Console Typewriter Codes
Upper Three Address Bits

5-117
5-136
7-4
7-5
7-7
7-10
7-21
7-23
8-6

FOREWORD
This manual provides information for the machine language use of the 3300 computer
system.

Its intention is to describe the capabilities and programming restraints of

the hardware.
COMPASS mnemonics are used to abbreviate titles of instructions; however, no software
systems are used in describing instructions.
systems are included in Section 6.

Brief descriptions of these software

Detailed descriptions for those systems in operation

are available in the appropriate software reference manuals.
Programming information for most available peripheral equipments is contained in the
3000 Series Peripheral Equipment Reference Manual, Pub. No. 60108800.

vii

Rev. B

CONTROL DATA 3300 COMPUTER SYSTEM

1. GENERAL SYSTEMS DESCRIPTION
INTRODUCTION
The CONTROL DATA* 3300 is an advanced design general-purpose computing
system providing high performance time-sharing with multiprogramming features to satisfy present and future needs of business and scientific users. Advanced design techniques are used throughout the 3300 to provide expedient
solutions for scientific, real-time, and business data processing problems.
Time-sharing and multiprogramming features of the 3300 enable a user to
enter many programs and receive processed results without the delays incurred
in single-job batch processing systems. This feature not only reduces turnaround time but also provides a considerable saving in computer usage and
personnel time. Multiprocessing of programs further enhances system performance when additional central processors are integrated into a total system.

Software systems for the 3300 take full advantage of the time-sharing and
multiprogramming capabilities of the hardware and include the MASTER,
Real-Time SCOPE, and MSOS operating systems, and the Mass Storage
Input/Output (MSIO) system. A synopsis of each of these systems and other
software is included in Section 6 of this manual.
All existing programs written for CONTROL DATA 3100 and 3200 systems can be
processed by a 3300. I/O characteristics for the 3300 are identical to the
3100, 3200, 3400, 3500, 3600, and 3800 line of Control Data computers - a fact
which facilitates incorporating the 3300 into a SATELLITE* configuration.
Included in the expanded repertoire of 3300 instructions is a complete list of
business data processing instructions. These extend the flexibility of the 3300
by performing field searches, moves, compares, tests, conversions, arithmetic
operations, and complete COBOL editing while utilizing the time-sharing feature
of the 3300.
A wide selection of proven peripheral equipment is available for use in a 3300
system including many new and advanced equipments.
*Registered trademark of Control Data Corporation
1-1

Rev.

C

This manual describes the various features of the 3300 and provides programming and operation information. Reference and supplementary information may
be found in the Appendixes.

COMPUTER MODULARITY
A 3300 computer consists of various logic cabinet modules designed to perform
specific operations. If additional storage, input/output channels, or arithmetic
capabilities are desired for an existing installation, an appropriate module is
integrated into the system. Figure 1-1 illustrates and describes the modules
of a typical 3300 computer.

-

K

J

I

H

®

Central Processing Unit (CPU)

@

2-3306 Input/Output (I/O)
channels or 1-3307 channel
and 1-3306 channel (Channels
o and 1)

©

B

A

G

C

E

D

F

2-3306 I/O channels or 1-3307
channel and 1-3306 channel

®

Power controls for I/O channels

©@®

©

3310 Floating Point module

2-3306 I/O channels or 1-3307
channel and 1-3306 channel

®

3311 Multiprogramming module

2-3306 I/O channels or 1-3307
channel and 1-3306 channel

CD
GD

Power Control Panel for@

®

3309-SK Storage Module

Figure 1-1.

@

3309-SK Storage Module

3300 Modularity Example
NOTES

® , CD, and 0 .
items GD and ® .

1.

A minimum 3300 configuration consists of items @ ,

2.

A 3302 16K storage module may be substituted for

(Cont'd on n.ext page)
Rev. A

1-2

@.

3.

Additional storage modules are added to the left of item

4.

The 3312 BDP (not shown) is a "stand-alone" cable connected unit. Additional
storage modules may also be stand-alone units to conform to installation space.,
Separate BDP cabinets similar to the 3312 are included as a part of 3304-2 and
3304-3 Business Data Processors.

5.

3307 I/O channels are always designated an even channel number, i. e., 0,2,
4, or 6.

Central Processing Unit
The 3304 Central Processing Unit (CPU) performs the following functions:
lID

Controls and synchronizes most internal operations of the computer.

lID

Processes all 24-bit precision fixed point arithmetic.

lID

Processes 48-bit precision addition and subtraction.

s

Executes Boolean instructions.

lID

Character and word loading and storing.

..

Executes decision instructions.

..

Controls standard search and move operations, external equipment and
typewriter I/O, real-time clock referencing, and register file operations.

..

Recognizes and processes all interrupts.

If the Business Data Processor (BDP) is present in a system, the CPU relin-

quishes control to it until the business oriented instructions(s) have been processed.

Business

Data

Processors

Two expanded central processors, the 3304 -2 and 3304-3 Business Data Processors,
are available. These processors provide a comprehensive set of variable fieldlength business data processing instructions in addition to all of the basic computing functions described for the 3304 CPU. The 3304 -2 and 3304 -3 provide
somewhat different sets of business data processing instruction sets. Otherwise,
the two processors are identical. The basic instruction set is the same as the
3304 CPU. Physically the 3304 -2 and 3304 -3 consist of two units: a basic central
processor and a business data processing unit.

Optional

Business

Data

Processing

Unit

The 3312 Business Data Processing unit is an add-on device that can be connected
by cables to the basic 3304 CPU. The composite 3304/3312 processor provides
the same instruction set as the 3304-2 Business Data Processor.

Storage Modules
The magnetic core storage (MCS) available for 3300 systems ranges from a minimum of 8,192 (32,768 characters) to 262, 144 (1,048,576 characters) words. An
MCS system is expanded in 16,384 word increments after two initial 8, 192 word
storage modules are installed in the system. Up to 131, 072 words of MCS may
be included in a system without the multiprogramming option present.

1-3

RevK

I

The following optional storage modules are available:
Model 3309 - 8, 192 word (32,768 characters) MCS memory module
Model 3302 - 16,384 word (65,536 characters) MCS memory module
The word "storage" is used synonymously with "memory" in this text and both
refer to MCS unless otherwise stated. Additional information pertaining to the
3300 storage system may be found in Section 2.

Input/Output Modules
Two types of Input/Output (I/O) modules are available for use in 3300 systems.
These are the 3306 and 3307 Communication Channels.
The 3306 is a bidirectional 12-bit parallel data channel and conforms to the standare I/O specifications for all CONTROL DATA 3000 Computers. A maximum of
eight 3306 channels may be incorporated in a single system with up to eight
peripheral controllers connected to each channel. Space is provided for mounting
two 3306 channels per module. Figure 1-1 shows the placement of the channels
in a maximum I/O channel configuration.
The 3307 is a bidirectional 24-bit parallel data channel and also conforms to the
Control Data 3000 I/O specification. In each 3307 channel 12-to 24-bit assembly/
disassembly is included. A maximum of four 3307 channels in addition to four
3306 channels may be present in a single system.
Additional information pertaining to the 3306 and 3307 I/O channels may be found
in Section 3.

Floating Point Module
The optional 3310 Floating Point Module permits a user to directly execute
floating point addition, subtraction, multiplication, and division instructions
utilizing 48-bit precision floating point operands. This option also permits
direct execution of 48-bit precision multiplication and division instructions.
Multiprogramming Module

I

The optional 3311 Multiprogramming Module provides capability to relocate
program instructions, data, and I/O in MCS. This option implements the 3300
memory page system and provides inherent memory protection as well as relocation and MCS extension to 262, 144 words. If the 3311 is not present in a
system, the maximum number of words is 131, 072. Refer to Section 8 for
additional information.

Operator's Console
The operators desk console includes:
Octal register displays
Built-in on-line typewriter
Built-in entry keyboard and control switches
Complete status monitoring system
Operator's chair

RevK

1-4

A complete description of the console, examples of manual operations, and a
picture of the console can be found in Section 7.
Power Control Panel
A power control panel is provided to control secondary logic power to the CPU,
floating point module, and I/O channels 0 and 1. Other modules have their own
power control panels. Primary power for the entire computer system is controlled by a group of switch boxes mounted on a nearby wall.

INTERNAL

ORGjl~NIZATION

Central Processing Unit
Computer Word Format
The standard 3300 computer word consists of 24 binary digits. Each word is
divided into four 6-bit characters. In storage, an odd parity bit is generated
and checked for each of the four characters, lengthening the storage word to
28 bits. Figure 1-2 illustrates the bit assignments of a computer word in
storage.
23

I

1817

I

0

\

0605

12 II

2

\

/

I

00
3

I

/

Character Designators

Figure 1-2.

Computer Word Character Positions and Bit Assignments

Register Descriptions
A Register (Arithmetic): The A register (accumulator) is the principal arithmetic register. Some of the more important functions of this register are:
CD

Most arithmetic and logical operations use the A register in formulating a result. The A register is the only register with provisions
for adding its contents to the contents of a storage location or
another register.

CD

The A register may be shifted to the right or left separately or
in conjunction with the Q register. Right shifting is end-off; the
lowest bits are discarded and the sign is extended. Left shifting
is end-around; the highest order bit appears in the lowest order
stage after each shift; all other bits move one place to the left.

Ell

The A register holds the word which conditions jump and search
instructions.

Q Register (Arithmetic): The Q register is an auxiliary accumulator register
and is generally used in conjunction with the A register.

1-5

Rev. A

The principal functions of Q are:
..

Providing temporary storage for the contents of A while A is used
for another arithmetic operation.

•

Forming a double-length register, AQ.

..

Shifting to the right or left, separately or in conjunction with A.

..

Serving as a mask register for 06, 07, and 27 instructions.

E Register (Arithmetic): The optional arithmetic register E is present in a
system whenever the 3311 Floating Point option is present in a system. During
floating point/ 48- bit precision operations, the E register is divided into two
parts, EU* and EL'~, each composed of 24 bits. It is used as follows:
•

48- bit precision multiplication; holds the lower 48 bits of a 96-bit
product.

•

48-bit precision division; initially holds the lower 48 bits of the
dividend; upon completion, holds the remainder.

•

Floating point multiplication; holds the residue of the coefficient
of the 48- bit product.

s

Floating point division; holds the remainder.

P Register (Main Control):

The P register is the Program Address Counter.

It provides program continuity by generating in sequence the storage addresses

which contain the individual instructions. During a Normal Exit the count in P
is incremented by 1 at the completion of each instruction to specify the address
of the next instruction. These addresses are sent via the S (address) Bus to the
specified storage module where the instruction is read. A Skip Exit advances
the count in P by 2, bypassing the next sequential instruction and executing the
following one. For a Jump Exit, the execution address portion of the jump instruction is entered into P and used to specify the starting address of a new
sequence of instructions.
Bb Registers (Main Control): The three index registers, B1, B2, and B 3 , are
used in a variety of ways, depending on the instruction. In a majority of the
instructions they hold quantities to be added to the execution address, M:=m+Bb.
The index registers may be incremented or decrelnented.
C Register (Main Control): Quantities to be entered into the A, Q, B, or P
registers or into storage from the entry keyboard are temporarily held in the
Communication (C) register until the TRANSFER switch is pushed. If an error
is made while entering data into the Communication register, the KEYBOARD
CLEAR switch may be used to clear this register.
The C register holds words read from storage during a Sweep or Read Storage
operation. The contents of C are displayed on the console whenever the keyboard is active.
~':'*The contents of register 33 should have the following format:
23

Slashed area should

1716

00

\

c~tain "0' sIt

Last character address plus one

Block Control Priority: Access to Block Control circuits is shared between the
computer's main program control and block control buffered functions. Functions
within Block Control are divided into three groups (Refer to Table 1-2.) The
five scanners that provide the priority access network for the system are the Program/Buffer scanner, the Group scanner, -and the three inner group scanners.
Figure 1-3 illustrates the scanning pattern of the priority network.

Rev. C

1-10

The Program/Buffer scanner alternately checks for Block Control requests from
Program Control and any Group requests. Group requests have priority over
Prograrn requests and as long as Group requests are presen't, they will be serviced before a Program request. When all Group requests have been serviced, a
Program request can be recognized.
Another free running scanner checks the three groups for an active Block
Control request. After a request from one group has been processed, the
scanner moves to the next group, rotating through the groups in a 3, 2, 1, 3
order.
Each group has a four-position scanner. These scanners search from top to
bottom of their respective groups looking for active Block Control requests.
Mter they find a request and it has been processed, the scanners return to the
top of their group before resuming their search.

TABLE 1-2.

BUFFER GROUPS

Group 1

Group 2

Group 3

Channel 0 Control
1

Channel 4 Control
5

2
3

6
7

Real-time clock control
Console typewriter control
Register File Display
Search/Move Control

CHANNEL 0 CONTROL

2

3

4

5

6
7

REAL-TIME CLOCK CONTROL
CONSOLE TYPEWRITER CONTROL
REGISTER FILE DISPLAY
SEARCH / MOVE CONTROL

Figure 1-3.

!~

r~
~~

• GROUP I

BUFFER
• GROUP 2

• GROUP

PROGRAM

~

•

•

3

Block Control Scanning Pattern
1-11

Rev. A

Real- Time Clock
The real-time clock is a 24-bit counter that is incremented each millisecond to
a maximum period of 16, 777, 216'~ milliseconds. After reaching its maximum
count the clock returns to zero and the cycle is repeated continuously. The
clock, which is controlled by a 1 kilocycle signal, starts as soon as power is
applied to the computer. The current time is stored in register 22 of the Register File. It is removed from storage, updated, and compared with the contents of register 32 once each millisecond. When the clock time equals the
time specified by the clock mask, an interrupt is set. When necessary, the
real-time clock may be reset to any 24-bit quantity including zero by loading A
and then transferring (A) into register 22. Performing a Master Clear does not
affect the clock count.
For a special case involving the real-time clock, refer to the Priority Pause
(PRP) instruction in Section 5.
Parity
Parity bits are generated and checked in 3300 systems for the following two
conditions:
1.

Whenever a data word is read from or written into storage.

2.

When a data word is transferred via an I/O channel.

Storage Parity: A parity bit is generated and checked for each 6-bit character
of a storage word. Refer to Figure 1-4.

2726252423

18 17

12 II

I

0605

2

I

00

3

CHAR~CTER DES~NATORS ~

PARITY
PARITY
PARITY
PARITY

Figure 1-4.

BIT
81T
BIT
BIT

FOR
FOR
FOR
FOR

CHARACTER
CHARACTER
CHARACTER
CHARACTER

:3
2
I
0

Parity Bit Assignments

During each Write cycle, a parity bit is stored along with each character.
When part or all of a word is read from storage, parity is checked for a loss or
gain of bits. Failure to produce the correct parity during read operations
causes the PARITY FAULT indicators on the storage module control panel and
internal status lights to glow. As soon as a parity error is recognized and the
PARITY STOP switch on console is active, program execution is halted. Master
clearing the computer clears the fault condition.
If the PARITY INTERRUPT switch is active and an interrupt is recognized, the

computer enters a special interrupt routine (see Section 4).
~'16,

777,216 milliseconds equals approximately 4 hours and 40 minutes.

Rev. A

1-12

The total number of "l's" in a character, plus the parity bit, is always an odd
number in the odd parity system used in the 3300.
I/O Parity: The I/O communication channels provide parity lines in addition to
the other signals that interface with external equipment. Parity is checked in
the I/o channels to detect parity errors during data transmission to the external
equipment and errors when data is received from external equipment. I/O parity
errors can be detected by a sensing instruction; however, the parity error
indicator is not activated. A complete description of I/O parity generation and
checking may be found in Section 3 of this manual.
Business Data Processing Units
The business data processing instructions provided by the 3304-2 and 3304-3
Business Data Processors and the optional 3312 BDP add-on unit perform operations on variable length fields of 6 -bit characters. Some typical operations are:
1.

Move a block of 6-bit characters from one region in memory to another.

2.

Add two fields of BCD digits.

3.

Search a field of BCD characters for a specific value.

4.

Compare to fields of characters for equality.

5.

Convert a field of BCD digits to a binary number.

The major characteristics of the BDP instructions are summarized below.

MOVES

AND

EDITS

The following capabilities are features of this instruction category:
•

Ability to transfer variable length data fields from one area of storage
to another.

•

Both fields may specify any 6-bit character location in storage as the
beginning address

•

Both fields may be independently

•

Up to 4095 characters may be moved

•

Operations may be terminated by specifying lengths of fields or
delimiting characters.

•

Data moved from a source field to a receiving field may be manipulated
and/ or modified as follows:

ind~xed

..... Single character or block of characters transferred without
modification
~

Move with blanks inserted in any unfilled character positions
in the receiving field

.,., Move with zeros inserted in any unfilled character positions
in the receiving field
.,., Move with leading zeros replaced with blanks and zone
(sign) bits stripped during the transfer

1-13

RevK

~

Move with edit functions performed: insertion of commas,
decimal point with suppression of leading zeros, or complete
formatted edit with insertion of character set as defined in
DOD COBOL-61 Extended specification

Instructions in this group are particularly useful in data processing applications
involving character manipulation, formatting for printing of integer quantities,
point alignment problems, etc. Editing functions are accomplished by hardware
rather than a complex subroutine, resulting in fast processing times.
SEA~~CHES

The following capabilities are features of this category of instructions:
•

Any 6-bit character location in storage may be specified as the location
of the first character of a field to be searched.

•

Up to 4095 characters may be examined

•

Indexing may be accomplished on the search field

,.

Search key (character) specified by programmer and contained in
instruction word

..

Search may be terminated by:
Locating object character
Examining a specified number of characters without locating
object character
Encountering delimiter character specified in a Search instruction.

•

At conclusion of search operation, an index register holds number of
characters searched to aid in determining location of character meeting
search condition.

•

Program control at search termination branches to either of two points,
depending on result of search

•

Searches may be of the following types:
Search successive character locations (either left to right or
right to left) in a field for an object character equal to the
search key
Search successive character locations (either left to right or
right to left) in a field for an object character unequal to the
search key
Search successive character locations (from left to right) in
a field for an object character equal to the search key and
jump; jump is to normal termination point plus the number
of characters searched

RevK

1-14

CODE CONVERSION

FEATURES

The following conversion operations can be performed on fields of 6 -bit
characters.
•

Convert BCD to binary

•

Convert binary to BCD
Translate to ASCII
Translate from ASCII

}

Available in 3312 optional BDP unit
and 3304-2 BDP only

•

Pack (convert numeric 6 -bit BCD characters into 4 -bit characters)

•

Unpack (convert numeric 4-bit BCD characters into 6 -bit characters)

ARITHMETIC

FUNCTIONS

The following capabilities are features of this category of instructions:
•

Add or subtract two fields of 6-bit numeric BCD characters

•

Both fields may specify any 6-bit character location in storage as the
beginning address

•

Both fields may be independently indexed

•

Algebraic sign control

..

Arithmetic overflow fault indicator provided

..

Compare two fields of numeric characters to determine which field
contains the largest number.

..

Compare two fields of alpha-numeric characters to determine which
field ranks highest in a collating sequence.

..

Test instructions examine field for: greater than zero,
zero, or less than zero. The result of the test sets a
BCD condition register to +, 0,. or -

•

Jump instructions in the CPU may be used to examine arithmetic
result flags in the BDP

Detailed information on the BDP instructions is included near the end of
Section 5.

1-15

RevK

PERIPHERAL EQUIPMENT
A wide variety of peripheral equipment is available for use with the 3300 computer. All peripheral equipment available for 3100, 3200, 3300, 3400, 3600,
and 3800 systems may be attached to a 3306 communication channel. For programming instructions, as well as a list of function codes and status response
codes, refer to the Control Data 3000 Series Computer Systems Peripheral
Equipment Reference Manual (Pub. No. 60108800).

I

Rev K

1-16

2. STORAGE SYSTEM
GENERAL INFORMATION
The 3300 Magnetic Core Storage (MCS) system receives and transmits storage
words to the CPU (and BDP if it is in the system). Each storage module provides parity checking and visual address and data displays. Each storage (or
memory) reference requires 1. 25 usec
within the storage module referenced.

STORAGE MODULES
A minimum storage configuration consists of one 3309 8, 192 word Storage
Module. An additional 3309 Storage module brings the total storage capacity
to 16,384 words. Further storage expansion is provided by adding model 3302
16,384 word Storage modules. If the 3300 is equipped with a 3311 Multiprogramming module, 3302 Storage Modules may be added to bring the total MCS
capacity to 262,144 words. If the 3311 is not in the system, the maximum MCS
is 131,072 words. The 3309 and 3302 Storage modules are shown in Figure 2-1
along with an enlarged view of their control panels.

STORAGE REGISTERS
S Register - The S register receives and holds the storage address, enabling
address translation for the word currently being referenced. The register
consists of 13 bits and 14 bits, respectively, in the 3309 and 3302 storage
modules.
Z Register - The 28- bit Z register is the storage restoration and modification
register. All data that is transferred to or from the storage module passes
through Z.

2-1

Rev.F

Dual 3309 16K Storage Module

3309 8K Storage Module

a·

:.', :."
.

V.

~
"

urJ,.~

~~~

., •
I

:@),.
:.:a

••

.~.
•

.

q.q.q.q,q,Q. q,q,q,q,q,Q.
a.a.a.a.a.q,,~,Q>a.o.a.a.(),

fS

.,.-"".,,.~

.. --

......"
Q,~~aoo'Q6O, .
W-'"~o.Q.l,Q>a

Dual 3309 Storage Module Control Panel
Figure 2-1.

Rev. A

3300 Storage Modules

2-2

"

ii1"lt

.. •

•

ooaooo
000000

000000
000000

@)

oq90

@

000

3302 Storage Module

0

6

0
0

0 ¢ 0
6 9" .. ,9

b ¢ 6 6
0 0 0 0

b 6

0

9",9

6

0

6

0

0

0

6

0006600
6 0 6SPIT,I,t,"
0000

3302 Storage Module Control Panel

Figure 2-1.

3300 Storage Modules (Cont'd)
2-3

Rev. A

STORAGE WORD

A storage word is 28 bits in length of which four bits are used for parity
checking the remaining 24 bits. The 24 bits, labeled 00 through 23 from right
to left, may be a single 24- bit instruction, part of a two or three word instruction, a zero to 24- bit operand, or part of a larger operand. The storage corresponds to the standard computer word and its format as described in Section
1.

CHARACTER MODES

During a read storage operation, all bits of a word referenced by (S) are read
out of core storage into the Z register (in parallel) and are restored without modification at the same address. For a write storage operation, five basic modes
exist for modifying (Z) prior to restoration. Any characters not modified are
restored unchanged. Write Character Designators from the computer or other
access devices specify the type of write operation to be performed.

Single-Character Mode
New data is entered into anyone of the four characters prior to restoring the
word in core.

Double-Character Mode
New data is entered into any two adjacent characters (character 0 ane! 1, 1 and 2,
or 2 and 3) prior to restoring the wore! in corc.

Triple-Character Mode
New data is entered into either of the two possible three-character groups (characters 0, 1, and 2, or characters 1, 2, and 3) prior to restoring the word in core.

Full-Word Mode
New data is entered into characters 0-3 prior to restoring the word in core.

Rev. B

2-4

Address Mode
New data is entered into the lower 15 bits (word address) or the lower 17 bits
(character address) prior to restoring the word in core.

ADDRESSING
The S bus, as described under Bus Systems in Section 1, carries the address of
the memory location being referenced to the proper storage module. During
Executive mode, the (ISR)':' or (OSR)':' are appended to a 15-bit basic address (as
displayed in the P register) to form an 18-bit address. The upper 3 bits of address are forced to zero during non- Executive mode to limit storage addressing
to 32,768 words.
If a storage reference is made for an address contained in a non-existent

memory module, a high priority interrupt may be entered. Refer to the Storage
Parity Error-No Response Interrupt in Section 4 for details.

MULTIPROGRAMMING AND RELOCATION
The 3311 Multiprogramming Module permits the instructions of many programs
to be sequentially executed and relocated in MCS under the control of a monitor
program. The available MCS in a 3300 system is grouped into "memory p::tges"
consisting of 2,048 absolute memory locations. By using a Page Index File and
advanced logic circuits, the 3311 makes optimum use of memory pages as they
become available during program execution.
Appendix E includes detailed information on multiprogramming and relocation
concepts as applied to the 3300.

STORAGE PROTECTION
It is often desirable to protect the contents of certain storage addresses against

alteration during the execution of a program. There are four categories of addresses: those that are always protected, those that are protected at the option
of the programmer, those that are protected by the multiprogramming and relocation features, and those that are never protected during special sequences.
If any attempt is made to write at a protected address during non- Executive mode,
the illegally addressed location remains unaltered (Write is changed to a Read),
the console illegal Write indicator lights, and program execution continues. The
illegal write condition is recorded by setting bit 05 of the internal status sensing
network. The condition is cleared by a Master Clear, an Internal Clear, or by
sensing.
,~

Only the numbers 0, 1, 2 and 3 in the ISR or OSR can be used in the Multiprogramming option is not in the system.
2-5

Rev.F

During Executive mode, a protected address remains unaltered (Write is changed
to a Read) during all write operations, except those occuring in Monitor State
and during Block Control operations. The condition is not recorded on the status
line. Refer to the illegal Write intE;:rrupt discussion in Section 4 for additional
information.

Permanent Protection
The upper 32 memory locations of the existing MCS are reserved for Auto Load
and Auto Dump programs when operating in the non-Executive mode. These
addresses are always protected against alteration by a special storage protection circuit. The actual protected addresses depend upon the number of MCS
locations in a system but always utilize the upper 32 locations in any system.
Logic circuits sense the total storage capacity of the system and check each
storage address as it appears on the S (address) Bus to see if it is among the
protected addresses. If it is one of those to be protected, reading, but no writing, is allowed at that address. The only time that this protection is disabled
is when an operator presses the ENTER AUTO PROGRAM switch on the console
to enter a new Auto Load or Auto Dump program.
When operating in Executive mode, the Auto Load and Auto Dump storage areas
encompass addresses 003700 through 0037778 and are protected when refec::'enced
8
through Page Index Zero. Refer to Section 3 for additi anal information on the
Auto· Load and Auto Dump features.
.
Selective Protection

3304- A Central Processor
Two different selective protect schemes are available with the 3304- A; one being
standard and the other available by option, In the standard protect scheme, 15
three-position toggle switches, corresponding to the basic 15-bit storage address,
are set to selectively protect individual addresses or a block of addresses. The
switches are located on the power control panel as shown in Section 7.
Table 2-1 describes the three switch positions and Table 2-2 lists examples of
switch settings. The switches are automatically disabled during execution of the
BDP instructions (64-70), In Executive mode, the switches apply to an address
range of which the upper 3 address bits (ISR) or (OSR) are equal to zero,
TABLE 2-1.

STORAGE PROTECTION SWITCH DESCRIPTIONS

Output

Switch
Position

Description

"I"

Up

Each address protected will have a Ill" in this bit position.

l1N 11

Center

Each address protected may have either a 11111 or a "a" in
this position. For example, when all switches are set to
the neutral position, all storage is protected, provided
that the protect feature is enabled.

"a"

Rev. H

Down

;

Each address protected will have a "0" in this bit position.

2-6

TABLE 2-2.

STORAGE PROTECTION SWITCH SETTINGS

Description of Protected Addresses

Examples:
Settings -Storage
Addresses
Protection Switches
Protected (octal)

Single storage address

000 000 000 001 111

00017

Two nonsequential addresses
of a group of 108. ':'

000 000 000 010 aNa
000 000 000 010 N10

00020 & 00022
00022 & 00026

Four nonsequential addresses
of a group of 108. ':'

000 000 000 010 NON

00020,
00024,
00021,
00025,

000 000 000 010 NN1

00021,
& 00025
00023,
& 00027

Four address block - may be the
upper or lower half of a group of
10 8,*

000 000 000 100 aNN
000 000 000 100 INN

00040-00043
00044-00047

108 address block

000 000 000 010 NNN

00020-00027

208 address block

000 000 001 OON NNN
000 000 001 lIN NNN

00100- 0011 7
00160- 001 77

408 address block - may be the
upper or lower half of a group
of 1008.'~

100 000 000 aNN NNN
100 000 000 1 NN NNN

40000-40037
40040- 40077

Numerous other groups and combinations of the above groups
may also be protected.

000 000 000 NNN 110

00006, 00016,
00026 '" 00076
All XXXX7 addresses
All XX1XX addresses (0010000177, 01100all 77, etc. )

NNN NNN NNN NNN 111
NNN NNN 001 NNN NNN

'~The

first address of all groups of 108, 208, 408, 1008 etc., must have a lower octal digit of zero. Blocks of 1008, 2008, 4008, 10008, 20008, 40008, etc.,
may be protected in the same manner as blocks of 108, 208, & 408.

The optional protect scheme allows two independent blocks of locations within a
designated 32K of storage to be protected during non- Executive or Executive
mode. With this feature, protection can be given to the resident monitor program
and to another program that may be operating.
The area increasing in address from address 00000 may be protected in multiples
of 512 10 locations. The area decreasing from address 77777 can similarly be
protected. The number of locations protected in an area is determined by setting
the six toggle switches associated with that area; each of the 77 Ii possible settings
represents one multiple of 512 locations. The six switches labeled 9 through 14
select the lower protected area; those labeled a through 5 select the upper
protected area (refer to Figure 7-11). Figure 2- 2 illustrates the protection
scheme. Table 2-3 gives examples of switch settings and their corresponding
protected areas.
2-7

Rev.D

Switch settings for both schemes are disabled by pressing the DISABLE STO
PROTECT switch on the console.
ADD RES S

7 7 7 77 , - - - - - - - - - - - - - - - - ,
PROTECTED

B XX

(77 7) 1 - - - - - - - - - - - - - - 1

UNPROTECTED

Cxx

(000) 1 - - - - - - - - - - - - - - 1
PROTECTED

ADD RES S

00 0 0 0 1 - - - - - - - - - - - - - - 1

Bxx = 6 switches to select upper area address boundary, lower 9 bits of which
are always "lis"
Cxx = 6 switches to select lower area address boundary, lower 9 bits of which
are always "OIS"
Figure 2- 2.
TABLE 2-3.
Bxx
Setting

Rev. D

Optional Protect Scheme

OPTIONAL STORAGE PROTECTION EXAMPLES
Locations Protected
(Upper and Lower areas)

76

01000

75

02000

74

03000

67

10000

57

20000

40

37000

37

40000

36

41000

8
8
8
8
8
8
8

8

Cxx
Setting

=

512

01

=

1,024

02

=

1,536

03

=

4,096

10

=

8, 192

20

=

15,872

37

=

16,384

40

=

16,896

2-8

I

41

3304-B Central Processor
The basic 3304-B Central Processor contains no standard storage protection.
Storage protection is available by option and operates the same as the optional
protection which is available on the 3304- A processor.

Program Protection
When the 3300 is operating in the Program State of Executive mode, the relocation features of the 3311 Multiprogramming module are used by the monitor
program to protect certain addresses from being altered.
If the exclusion bit of a particular Page Index is a "1" and PL, t PA, t or PP t
is a quantity other than zero, PA defines a memory area where only reading is permitted. If the exclusion bit is "1" and PL, PA,and PP are all equal to zero,
neither reading nor writing is permitted.

The monitor program controls the relocation process and uses the paging
system to provide efficient use of memory while processing various programs.
Appendix E explains in detail the 3300 paging and relocation processes.

No Protection
Addresses 00002 through 00005, 00010, 00011, 00014, 00015, 00020, and
00021, which are used by the interrupt system, are never protected during the
interrupt sequence.

STORAGE SHARING
Two 3300 computers may share the memory of a storage module. A switch on
each storage module control panel allows the operator to give exclusive control
to the right or left computer. A middle position on this switch actuates a twoposition priority scanner. Storage control honors the requests in the order
they are received. Neither computer has priority over the other and the computer involved in the current storage cycle relinquishes control to the requesting computer at the end of its cycle. Either computer can therefore be delayed
a maximum of one storage cycle. A similar program delay may occur within
either computer when an internal scanner determines whether Main Control or
B lock Control has ac ces s to the storage module.
Direct accpss to 3300 type storage modules is available for certain installations.
The normal Ilo channel route is bypassed and the customer's special equipment
interfaces directly with the storage logic.

tRefer to Appendix E for designator descriptions.
2-9

Rev. D

3. INPUT/OUTPUT SYSTEM
GENERAL INFORMATION
Data is transferred between the 3300 Central Processor and its associated peripheral equipment via a 3306 or a 3307 Communication Channel. The 3306 utilizes
a 12-bit parallel-transfer byte and the 3307 provides a 24-bit byte. A maximum
of eight 3306's or four 3307's and four 3306's may be linked to a single system.
Both the 3306 and the 3307 are bidirectional and each channel may communicate
with a maximum of eight peripheral controllers. A data channel can communicate
with only one device at a given time, however. Each peripheral controller in
turn may be attached to a number of peripheral devices. Figure 3-1 is a simplified block diagram of a 3300 Communication System.
For programming purposes, the eight possible I/O channels are designated by
numbers 0 through 7. A 3307 channel will always be an even channel. The total
number of channels must always be even. Depending upon the user's needs, any
combination of 3306's and 3307's may be present provided all the forenamed rules
are followed.

A basic 3300 system includes two 3306 Communi cation Channels or one 3307
channel and one 3306 channel. Figure 1-1 indicates the location of thes e channels
in a fully expanded system.
Channels 0 and 1 derive their operating power from the CPU. Power for all other
channels is controlled through the I/O Channel Power Panel shown in Figure 3-2
and as F in Figure 1-1. The two voltage controls should be adjusted to produce
00/0 reading on the meters when the 400 cycle power circuit breaker is turned ON.

3-1

Rev. B

Data Channel

r-------------'A~----------_,

Block
Control

o

A maximum configuration of data channels. A smaller configuration may be
obtained by removing the channels in pairs of odd and even. Any 3307 may be
replaced by a 3306. but not vice versa.
Each channel may connect to a maximum of eight equipments. The number of
devices connected to an equipment depends upon'the equipment.

Figure 3-1.

3300 I/O System

..........- - - - - VOLT METER

......
- - - - - - VOLTAGE CONTROL

.......
- - - - - VOLT METER

...........- - - - - VOLTAGE CONTROL

..........- - - - - 400 CYCLE POWER CIRCUT BREAKER

Figure 3-2.
Rev. B

I/O Channel Power Panel
3-2

INTERFACE SIGNALS
Figure 3- 3 shows the interface signals between a data channel and its external
equipment. The twelve status lines are active only between the channel and the
controller to which it has been connected by a CON (77.0) instruction. Since a
Connect instruction causes all controllers on the specified channel to disconnect
except the one to which it is directed, only one controller may be connected to a
channel at one time. Thus to check status the program must first Connect the
device.
There are eight interrupt lines, one to each controller. A controller need not be
connected to return an interrupt signal to the data channel. These lines are
designated as 0-7 and match the Equipment Number switch setting on each controller. For a complete description of the I/O interface signals as well as an I/O
timing chart, refer to the 3000 Series Input/Output Specifications Manual, Pub.
No. 60048800.
DATA LINES ( 12 FOR 3306; 24 FOR 3307 )
PARITY LINES ( I FOR 3306; 2 FOR 3307 )
CONNECT
FUNCTION
READ
WRITE
DATA SIGNAL
MASTER CLEAR
CLEAR EXTERNAL
3306 OR 3307
COMMUNICATION
CHANNEL

CHANNEL

INTERRUPT
EXTERNAL
EQUIPMENT

BUSY

REPLY

CONTROLLER

REJECT
END OF

RECORD

EXTERNAL
STATUS

PARITY ERROR

LINES (12)
LINES (8)

INTERRUPT
SUPPRESS

ASSEMBLY

I

DISASSEMBLY

WORD MARK
SAMPLE STATUS TIME
NEGATE CHANNEL INTERRUPT LOCKOUT
24 BIT DEVICE PRESENT (3307 )
COMPUTER RUNNING

Figure 3-3.

Principal Signals Between I/O Channel and External Equipment
3-3

Rev. C

3306 AND 3307 COMMUNICATION CHANNELS
Communication channels provide a buffer between the computation section and
various peripheral controllers, thus preventing a tie-up of the computation section
while awaiting a response from an external equipment. Since an I/O section contains no manual controls or indicators, all operations must be initiated by program
via the computation section of the computer. Prior to actual data exchange the
program must execute several instructions which connect the equipment to the
channel, specify operating conditions, check status conditions, and initiate the
Read orWrite operation. After the Cent ral Processor initiat es the Input or Output
operation, a comlnunication channel can exchange data between the peripheral
device and core storage independent of the Central Processor,
All assembly and disassembly for the 3306 12-bit channel is done by block control,
not the 3306. Two memory references are necessary to store or transmit a 24bit word when doing a word addressed I/O instruction with 12- to 24-bit assembly.
In contrast, the 3307 contains its own assembly/disassembly feature. The assembly feature allows the channel to receive two 12- bit bytes from an external equipment and assemble them into a 24-bit word before storing in memory. The disassembly feature permits the channel to accept a 24- bit word from storage and
transmit it to an external equipment in 12- bit bytes,
The 3307 also facilitates a convenient interface with a 24- bit 1/ a device. The
24-bit transfers between memory and the 3307 reduce to one the number of memory references necessary to execute a word addressed I/O instruction. Thus the
3307 is adapted for use with high-speed 12- and 24-bit I/O devices. When doing
character addressed instructions, it acts as a 3306,

I/O PARITY

Parity Checking With the 3306
The computer checks parity by one method for Connect, Function, and Write
operations and by a second method for Read operations. External equipment
responds differently to parity errors for a Connect than for a Function, Read,
or Write. For details on external equipment responses to parity errors see
3000 Series Peripheral Equipment Reference Manual, Pub. No. 60108800.
Connect, Function, and Write
During the Connect, Function, and Write operations the Data Bus circuit of the
computation section generates a parity bit and sends it to the external equipment
with each 12- bit byte via the 1/ a channel. The external equipment generates a
parity bit and compares it with the parity bit from the computer.
Connect: If a parity error exists in a Connect instruction, the external equipments:
do not connect
disconnect if already cOID1.ected

Rev. B

3-4

..

do not return an External Parity Error signal

..

generally light a Parity Error indicator on the external equipment, and

o

return neither a Reply nor a Reject signal.

After 100 usec the computer issues an Internal Reject.
Function and Write: If a parity error exists in a Function or Write instruction,
the connected external equipment sends an External Parity Error signal back to
the I/O channel. This signal causes the logic within the channel to provide a "1"
on sense line zero. This logic is cleared every time an attempt is made to execute a Connect, Function, Read, or Write operation on this channel; however,
these operations do not necessarily clear the logic in the external controller that
transmits the External Parity Error signal. Thus to guarantee clearing this
sense line the external equipment must also be cleared. Both the I/O channel
and the external equipment may be channel cleared by the program or master
cleared by the operator. If a transmission parity error is received from a controller, the controller remains inactive until both the external equipment and the
I/O channel are cleared. A new I/O sequence must be initiated to continue or
repeat the I/O operation.
Read
During a Read operation, the external equipment generates a parity bit and sends
it to the I/O channel along with each 12-bit byte of data. The I/O channel holds
the parity bit while the data is forwarded to the computation section. The Data.
Bus circuit of the computation section generates a second parity bit and sends It
back to the I/O channel. The channel compares this second signal with the Parity
signal which was generated by the external equipment. If an error exists, certain
channel logic is set by an enable from the computation section. This logic provides
a "1" on sense line zero. The channel parity logic is cleared every time an attempt
is made to execute a Connect, Function, Read, or Write operation with this channel. It may also be channel cleared by the program or master cleared by the
operator. If a transmission parity error is channel generated, it must be sensed
by the INS instruction. If the error is not sensed, the next channel operation
clears the error indication.

Parity Checking With the 3307
The computer checks parity with a 3307 in a slightly different manner than with a
3306.
Connect, Function, and Write
During the Connect, Function, and Write operations the Data Bus circuit in the
computation section generates one parity bit for the lower 12ibit byte of data and
one parity bit for the upper 12- bit byte. Both parity bits are sent to the external
equipment via the I/O channel. The external equipment generates parity bits and
compares them with the parity bits from the computer. The remainder of the
parity checking is identical to that of the 3306 for Connect and for Function and
Write.

3-5

Rev. C

Read
During a Read operation, the external equipment generates two parity bits per
data word (one for each 12-bit byte) and sends them to the 3307 with the word.
The 3307 holds the parity bits as the data is forwarded to the Data Bus circuit
of the computer. Parity is generated in the Data Bus circuit and is sent back
to the 1/0- channel where a comparison is made with the parity bits received
from the external equipment.
If a parity error exists, the channel parity logic is set by an enable from the

computation section, thus providing a "1" on sense line zero. Clearing the logic
also occurs the same way as it does in the 3306. If a transmission parity error
is channel generated, it must be sensed by the INS instruction. If the error is
not sensed, the next channel operation clears the error indication.

TRANSMISSION RATES
The rate of transmitting each 12- bit word of I/O information depends upon the
number of channels active, interregister transfers, the use of pause instructions
to block out main control or the real-time clock, the length of connecting cables,
and the use of multiprogramming. The 3000 Series Input/Output Specifications
Manual, Pub. No, 60048800, describes in detail the measurement of these transfer
rates using a variable-speed channel execiser. The exerciser measures the transfer rate by indicating a Lost Data condition when its speed exceeds that of the data
channel. Word addressed I/O instructions with 12- to 24-bit Assembly/Disassembly were used.
Assuming a safe maximum transfer rate to the 10 percent slower than the average
of the rates at which a Lost Data condition occurred, the following cases serve as
examples of realizable transfer rates.
Maximum Transfer Rate
(12-bit word)
Without multiprogramming:

Rev. F

1.

Using a 3307 on channel 4, doing
I/O only, blocking main control
and the real-time clock with a
Priority Pause instruction.

2.

Standard rate, no restrictions on
program, channel 0 and 1 active,
channel 0 1s a 3307, channel 1 is
a 3306.

3-6

2.0 usec

8.0 usec (channel 0)
20.0 usec (channell)

With multiprogramming

1.

Using a 3306 on channel O~
doing I/O only, blocking main
control and the real-time clock
with a Priority Pause.

2.

Standard rate, no restrictions
on program, channels 0 and 4
active, both are 3306's.

4. 2 usec

16.0 usec (channel 0)
16. 0 usec (channel 4~

The measured transfer rates when doing relocation were O. 2-. 3 usec greater.

IN PUT/OUTPUT RE:LOCATION
Data may be transmitted to or from several block locations in storage by using
relocation. When an I/O instruction is encountered while executing a program in
Executive Mode, Program State, an Executive Interrupt returns the computer to
Monitor State. When a 3311 is present in the system the relocation of I/O information now occurs in the same manner as the relocation of a program. The monitor recognizes and assigns the appropriate I/O channels and devices. Whether
or not relocation occurs, the largest block of data which may be transferred by
a single I/O instruction is 32K 24- bit words.

AUTO LOAD / AIUTO DUMP
The Auto Load and Auto Dump feature of the computer allows the programmer
two groups of continuous storage locations for storing frequently used subroutines. These subroutines may be used whenever it is desirable to call in a
particular tape unit or some other function that initiates an operation.
By depressing the AUTO LOAD console switch when the computer is stopped
and in the non-Executive mode, the computer automatically jumps to address
77740 and exe cutes the instruction stored there. The Auto Load routine is
allotted sixteen addresses, 77740 through 77757.
Depressing the AUTO DUMP switch under the same conditions as Auto Load
causes the computer to jump to address 77760 and execute the instruction stored
there. Sixteen addresses, 77760 through 77777. may be used for the Auto Dump
routine.
Although these storage areas may be used for any routine, the Auto Load area
is generally used to bring in a program from a magnetic tape unit or other
peripheral device. The last instruction in this routine should be a jump to the
first address of the program just called in.
The Auto Dump area is most often used to output a block of data to a magnetic
tape unit or other peripheral equipment and the last instruction in this routine
can be a jump to any storage area within the confines of the system.

3-7

Rev. F

When the computer is operating in Executive mode, the Auto Load routine is
stored in thirty-two locations encompassing addresses 003700 through 003737.
The Auto Dump likewise has thirty-two locations ranging from address 003740
through 003777. The PA and PP designators of the page index associated with
Page Index File zero are always zero thus providing a definitive area of storage
(page zero) where the Auto Load and Auto Dump routines may be stored. The
Auto Load and Auto Dump addresses are always protected in Non-Executive mode.
Examples of entering programs into the Auto Load and Auto Dump storage
areas are given in Section 7.

Rev. B

3-8

4. INTERRUPT SYSTEM
GENERAL INFORMATION
The Interrupt System of a 3300 Computer can sense for the presence of certain
internal and external conditions without having these tests in the main program.
Examples of these conditions are internal faults and external equipment end-ofoperation. Near the end of each RNI cycle, a test is made for interruptible
conditions. If one of these conditions exists, and the interrupt system is enabled; execution of the main program halts, the contents of the Program Address register are stored, and an interrupt routine is initiated. This interrupt
routine previously stored in memory, performs the necessary functions for the
existing condition and then jumps back to the last unexecuted step in the main
program. The instruction being read when the interrupt is recognized is executed when the main program is resumed.
There are seven categories of interrupts in the 3300 Computer: Internal Condition interrupts, I/O interrupts, Executive interrupt, Parity Error interrupt,
Illegal Write interrupt, Trapped Instruction interrupts, and Power Failure interrupt. The store operations required for all types of interrupts occur regardless of the settings of the storage protection switches described in Section 2.
An additional programming feature is the MANUAL INTERRUPT switch on the
operator's console. This interrupt is not masked since this switch is activated
only when it is desirable to interrupt the computer, however, the interrupt
system must be first enabled. The manual interrupt condition is automatically
cleared after the interrupt is recognized.
When the 3300 is operating in the Program State of Executive mode, any interrupt that is recognized causes the processor to revert to the Monitor State. An
Executive interrupt (described later in this section) also causes the processor
to revert to the Monitor State if an attempt is made to execute one of several
particular instructions.

4-1

Rev. A

INTERRUPT CONDITIONS
Internal Condition Interrupts

Anyone of six internal conditions may cause an interrupt during the execution
of a program. These conditions and their descriptions follow.
Arithmetic Overflow Fault
The Arithmetic Overflow fault is set when the capacity of the adder is exceeded.
Its capacity, including sign, is 24 or 48 bits for 24- bit precision and 48- bit
precision, respectively.
Divide Fault
The Divide fault sets if a quotient, including sign, exceeds 24 or 48 bits for
24-bit precision and 48-bit precision, respectively. Therefore, attempts to
divide by too small a number, including positive and negative zero, result in a
Divide fault. A Divide fault also occurs when a floating point divisor is either
equal to zero or not in floating point format. The results in the A, Q, and E
registers are insignificant if a fault occurs. A Divide fault can be correctly
sensed only after the current instruction has been executed.
Exponent Overflow /Underflow Fault
During all floating point arithmetic operations, exponential overflow occurs if
the exponent exceeds + 1777 8 or is less than -17778" The fault is also set if
the SFPF (77.71) instruction is executed.
BCD Fault
The BCD fault is generated by the BDP module if:

1.

The lower 4 bits of any character in field A (except the sign character)
exceed 118 during a numeric character operation.

2.

The lower 4 bits of the sign character in field A exceed
numeric character operation.

3.

The upper 2 bits of any character in field A (except the sign character)
do not equal 00 during a numeric character operation.

4.

An arithmetic carry out of the highest order character of field C occurs
during an ADM or SBM instruction.

5.

Field length § 1 > § 2 for an ADM or SBM instruction.

6.

Field length §1 # §2 for a FRMT instruction, including provision for
insertion characters.

7.

A carry occurs out of the 14th character position during a CVBD
instruction.

8.

A field (§ 1) of more than 14 BCD characters is specified during a CVDB
instruction.

9.

Bits 05 and 06 of an ASCII character are both 11's" or both "O'S" during
the execution of an A TD instruction.

128 during a

The BCD Fault may also be set by executing the SBCD (77. 72) instruction.
Rev. C

4-2

Search/ Move Interrupt
The Search/ Move control may be programmed to generate an interrupt during
a 71 or 72 instruction for either of the following conditions:
1.

Completion or satisfaction of an equality or inequality search instruction (SRCE or SRCN).

2.

Completion of a block move (MOVE instruction).

Real-Time Clock Interrupt
The Real-Time Clock interrupt is generated when the clock reaches a time
previously stored in register 32 of the Register File.

Input/Output Interrupts
I/O Channel Interrupts
Any of the eight possible I/O channels may be programmed to generate an interrupt for either of the following conditions:
1.

Reaching the end of an input or output block.

2.

Receiving an End of Record (Dis connect) signal from an external
device.

I/O Equipment Interrupt
The I/O equipment interrupt is set when an interrupt signal is received from
any of eight peripheral equipment controllers connected to any of the eight
possible I/O channels (there may be a total of 64 interrupt lines).
Associated Processor Interrupt
In a system of two or more processors (computers), each processor may interrupt, or be interrupted by, one other processor by executing an IAPR (77.57)
instruction. This interrupt is not masked and becomes cleared as soon as it is
recognized.

Executive Interrupt
The Executive Interrupt can only occur when the computer is operating in the
Program State of Executive mode. An attempt to execute one of the following
instructions then generates an Executive interrupt.
1.

Halt instruction (00.0)

2.

Inter-register transfer instructions with the Register File locations 00
through 37, [l}3. (4-7) (1--3) (XXOO-XX37[J

4-3

Rev. C

3.

Instructions with octal codes 71 through 77 except the 77.71 SFPF and
77. 72 SBCD instructions

This interrupt is not masked and has priority over all of the internal condition
interrupts. When the Executive interrupt has been recognized and the computer
has reverted to the Monitor State, any of the instructions in the three categories
above can be executed.

Storage Parity Error-No Response Interrupt
A Storage Parity Error interrupt has the highest priority of all interrupts and
can occur if either a storage parity error is detected or if a storage module does
not respond when referenced. The interrupt condition is recognized during the
RNI and RADR sequence for an instruction.
The PARITY INTERRUPT switch on the console must be active for the interrupt
to occur. If the PARITY STOP switch is active, the computer stops when a
parity error or no-response condition is detected. The two switches cannot be
simultaneously active, and pressing the PARITY STOP switch overrides the
Parity Interrupt condition.
If Block Control has storage priority at the time of interrupt, the address of the
next instruction to be executed is stored in the lower 15 bits of location 00020.
The appropriate register file location contains the approximate address where
the error occurred. An interrupt during Main Control priority causes the address
of the current instruction to be stored in location 00020. If the error condition
is detected during any of the RNI's for the BDP instructions, (P) is always stored
at location 00020. Detecting the condition during either RNI for the 71 - 76 instructions results in either (P), (p + 1), cir (p + 2) being stored.

A code representing conditions within the processor at the time of interrupt is
automatically stored in the lower 12 bits of location 00021. A RNI is then performed at location 00021. The stored address and code enable the interrupt
routine to isolate the storage area where the error occurred and aid in program
recovery. Table 4-0 lists the various codes and their interpretations.
The instruction in progress when the interrupt is detected may be executed although the results are not necessarily correct. Once the parity error or noresponse condition is detected, additional errors are not recognized until a DINT
(77. 73) instruction is executed.

Rev. F

4-4

TABLE 4-0.

Reason for Interrupt

PARITY ERROR INTERRUPT CODES
Type of Operation or
Sequence in Progress

Code

No- Response

Block Control - (73-76)

ooxo

X= ch

Parity Error

Block Control - (73-76)

00X2

X= ch

No- Response

Block Control - 71, 72, or
typewriter I/O

01XO

(X=O, Srch),
(X=l, Move) ,
(X=3, TWR)

Parity Error

Block Control - 71, 72, or
typewriter I/O

01X2

(X=O, Srch),
(X=l, Move),
(X=3, TWR)

No- Response

Main Control - RNI or RADR

00X1

(X=O, RNI)
(X=2, RADR)

Parity Error

Main Control - RNI or RADR

00X3

(X=O, RNI)
(X=2, RADR)

No-Response

Main Control - ROP or STO

0005

Parity Error

Main Control - ROP or STO

0007

Illegal Write Interrupt

This interrupt has priority over all interrupts except the Storage Parity Error
interrupt. The interrupt condition may result during a RNI, RADR, ROP, or
STO sequence; however it is recognized only during RNI or RADR. When the condition is recognized, the interrupt system is disabled, (P) are automatically
stored at address 00014, and an RNI is performed at address 00015.
The system must be in Program State of Executive mode to recognize the interrupt. The interrupt is disabled during Monitor State and during Search/Move and
I/O cycles. The conditions for the interrupt are listed below. (Conditions 3
through 6 apply only if the 3311 Multiprogramming Module is present in the system. )

1.

A Write operation into an area protected by the Storage Protect
switches (Program State 0).

2.

A Keyboard Write operation into the Executive Auto Load/ Auto Dump
area (addresses 03700 through 03777).

3.

A Read or Write operation when bits 9 and 10 of the original address
specify a quarter page equal to or greater than PL, when PL 1 O.

4.

A Read or Write operation if the 'E' designator for any referenced
index equals "I" and PA, PL, and PP are equal to zero.

5.

A Write operation if the 'E' designator for any referenced index equals
"I" and P A, PL, or PP is not equal to zero.

6.

A double precision instruction if the first operand is to be read from
the last available memory location specified by PL, or if from the
last memory location when PL specifies a full page and the next index
to be used contains 4000.
4-5

Rev. C

Bit 05 of the internal status sensing network is set on an Illegal Write interrupt
only if the condition occurred during a RNI or RADR sequence. If the condition
occurred during a ROP or STO sequence, the interrupt is generated but bit 05 is
not set. If one of the 66.0 - 66.5 instructions is interrupted by an Illegal Write,
the instruction always restarts at the beginning when the main program resumes.
Other BDP instructions restart from the point of interrupt.

Trapped Instruction Interrupts
If an attempt is made to execute one of the instructions listed in Table 4-1 and
the system is not equipped with a 3310 Floating Point module or 3312 BDP, the
instruction becomes trapped. Only those instructions preceded by an asterisk
(,:,) are trapped if the 3312 BDP is not present in the system and the 3310 Floating
Point module is present.

TABLE 4-1. TRAPPED INSTRUCTIONS FOR NON-EXECUTIVE MODE
WITHOUT A 3310 OR 3312 MODULE IN SYSTEM (MNEMONIC LISTING)
ELQ
EUA
EAQ
QEL
AEU
AQE
MUAQ
DVAQ
FAD
FSB
FMU
FDV

I

':'MVE
':'MVE,DC
':'MVBF
':'MVZF
':'MVZS
':'MVZS, DC
':'ZADM
':'FRMT
':'EDIT
':'SCAN, LR, EQ
':'SCAN, LR, EQ, DC
':'SCAN, LR, NE

':'SCAN, LR,
':'SCAN, RL,
':'SCAN, RL,
':'SCAN, RL,
':'SCAN, RL,
':'CVDB
':'CVBD
':'DTA
':'DTA, DC
':'ATD
':'ATD,DC
':'PAK

NE, DC
EQ
EQ, DC
NE
NE, DC

':'UPAK
':'ADM
':'SBM
':'CMP
':'CMP,DC
':'TST
':'TSTN
':'JMP, HI
':'JMP, LOW
':'JMP, ZRO
':'SBR
':'LBR

NOTE
DT A, DT A dc, A TD and A TD dc instructions are
available in 3312 and 3304-2 only.
Each instruction listed in Table 4-2 is processed as a no-Operation instruction,
(refer to Section 5) if an attempt is made to execute one of them while operating
in the non-Executive mode.
TABLE 4-2. NO-OPERATION INSTRUCTIONS FOR
NON-EXECUTIVE MODE (MNEMONIC LISTING)
ACI
AIS
AOS
APF
CIA

ISA
JAA
OSA
PFA
-R€H-

RIS

RevK

4-6

ROS
SBJP
c.J2.;R SD L

AcR

~

TMA V

Although they are not true interrupts, trapped instructions are processed like
interrupts once they have been detected. A conventional interrupt always takes
priority over a trapped sequence.
The following operations take place when a trapped instruction is recognized:
1.

The address of the next sequential program step, P + 1, is stored in
the lower 15 bits of address 00010.

2.

The upper 6 bits of the instruction in the F register are stored in the
lower 6 bits of the operand stored at address 00011. The upper 18
bits of this operand remain unchanged.

3.

Program execution commences at address 00011.
EXAMPLE:

MUAQ (56) Instruction execution attempt without the
Floating Point/Double Precision hardware option in the
system.

Address P

0 30390

Address P + 1

00010
00011
At this point the MUAQ operation may be simulated
by software and re-entry to the main program is
possible by a jump to the contents of address 00010.

Power Failure Interrupt
If source power to the computer system fails, the power failure is detected and

the computer program is interrupted. This interrupt is necessary to prepare a
controlled shutdown and prevent the loss of data. The operation requires 16 ms
for detection, and up to 4 ms for processing the special Power Failure interrupt
routine.
The Power Failure interrupt overrides any other interrupt except the Illegal
Write and Storage Parity Error interrupts, regardless of the state of interrupt
control. Since this interrupt overrides all others, the address where the present contents of P are stored and the address to which program control is transferred must be different from that for a normal interrupt. When a Power
Failure interrupt occurs, the machine stores the contents of P in the lower 15
bits of address 00002 and transfers program control to address 00003.
The normal interrupt system is disabled during a power failure sequence; i. e. ,
the hardware simulates the execution of a DINT (77.73) instruction.

4-7

Rev. C

INTERRUPT CONTROL
Through the use of certain instructions, a program can recognize, sense, and
clear interrupts, and enable or disable the interrupt system.

Enabling or Disabling Interrupt Ccmtrol

Instruction EINT (77. 74) enables the interrupt system and the DINT instruction
(77. 73) disables it. After recognizing an interrupt and entering the interrupt
sequence, other interrupts are disabled automatically. When leaving the interrupt
subroutine, the interrupt system must again be enabled by the EINT instruction if
interrupts that are waiting or subsequent interrupts are to be recognized by the
system. Refer to the EINT (77. 74) instruction in Section 5 for special conditions
regarding the actual interruption of the CPU.

Interrupt Priority
An order of priority exists between the various interrupt conditions. As soon as
an interrupt becomes active, the computer scans the priority list until it reaches
an interrupt that is active (not necessarily the interrupt that initiated the scanning) .
The computer processes this interrupt and the scanner returns to the top of the
list where it waits for another active interrupt to appear. Table 4-3 lists the
order of priority.
TABLE 4-3.
PRIORITY
1
2
3
4
5
6

7

INTERRUPT PRIORITY

TYPE OF INTERRUPT
Storage Parity Error
illegal Write
Power Failure
Executive
Arithmetic Overflow
Divide Fault
Exponent Overflow /
Underflow

PRIORITY
8
9-72
73-80
81
82
83
84
85

TYPE OF INTERRUPT
BCD Fault
I/O Equipment (External)*
I/O Channel*~~
Search/Move
Real-time Clock
Manual
Associated Processor
Trapped Instruction

* There are eight interrupt lines on each of the eight possible I/O channels, or
64 lines in all. On any given channel, a lower numbered line has priority
over a higher numbered line. Likewise, a lower numbered channel has
priority over a higher numbered channel. Example: line 0 of channel 0 has
highest priority of all external I/O interrupts, line 0 of channell has second
highest, and line 7 of channel 7 has the lowest.
*"~ A lower numbered I/O channel interrupt has priority over a higher numbered

I/O channel interrupt.
Rev. C

4-8

Sensing Interrupts
The programmer may selectively sense interrupts by using the INTS (77.4)
instruction. Sensing the presence of internal faults automatically clears them.
Interrupt lines representing channels not present in the system are sensed as
being active. The interrupt system need not be enabled for sensing.

Clearing Interrupts
Internal condition interrupts are cleared by:
•

Sensing with an INTS (77. 4) or INS (77. 3), after which interrupts are
automatically cleared,

•

Executing an INCL (77. 50) instruction

•

Executing an IOCL (77.51) instruction - clears only Search/Move interrupt, or

•

Pressing the MC or INTERNAL CLEAR buttons.

I/O channel interrupts are cleared by:
•

Executing an INCL (77. 50), IOCL (77. 51), or CLCA (77. 512) instruction,
or

•

Pressing the MC or EXTERNAL CLEAR buttons.

I/O equipment interrupts are cleared by:
•

Executing an IOCL (77. 51) instruction,

•

Reselecting or releasing the interrupt with a SEL (77. 1) instruction, or,

•

Pressing the MC or EXTERNAL CLEAR buttons.

The manual and associated processor interrupts are automatically cleared upon
recognition by the computer.

INTERRUPT PROCESSING

Four conditions must be met before an Internal Condition, Executive, or I/O
interrupt can be processed:

1.

A bit representing the interrupt condition must be set to "I" in the Interrupt Mask register (except for Manual, Associated Processor, and
Executive interrupts) .

2.

The interrupt system must have been enabled (except for Executive Interrupt).

3.

An interrupt-causing condition must exist.

4-9

Rev. C

4.

The interrupt scanning logic (Refer to Table 4-3) must reach the
level of the active interrupt on the priority list.

When an active interrupt has met the above conditions, the following takes
place:
1.

The instruction in progress proceeds until the point is reached in the
RNI or RADR cycle where an interrupt can be recognized. At this time
the count in P has not been advanced nor has any operation been initiated.
When an interrupt is recognized, the address of the current unexecuted
instruction in P is stored in address 00004.

2.

A number representing the interrupt-causing condition is stored in the
lower 12 bits of address 00005 without modifying the upper bits. Table
4-4 lists the octal codes which are stored for each interrupt condition.

3.

Program control is transferred to address 00005 and an RNI cycle is
executed.

TABLE 4-4.

REPRESENTATIVE INTERRUPT CODES

Conditions

Codes

External interrupt
I/O channel interrupt
Real-Time Clock interrupt
Arithmetic overflow fault
Divide fault
Exponent overflow fault
BCD fault
Search/move interrupt
Manual interrupt
Associated processor interrupt
Executive Interrupt

':'OOLCh
010Ch
0110
0111
0112
0113
0114
0115
0116
0117
0120

*L = line 0-7 and Ch = channel designator, 0-7

INTERRUPT MASK REGISTER
The programmer can choose to honor or ignore an interrupt by means of the
Interrupt Mask register. All but three of the normal interrupt conditions are
represented by the 12 Interrupt Mask register bits. The Manual, Associated
Processor and Executive interrupts are not masked. The mask is selectively
set with the SSIM (77.52) instruction and selectively cleared by the SCIM (77.53)
instruction. See Table 4-5 for Interrupt Mask register bit assignments.
The contents of the Interrupt Mask register may be transferred to the upper 12
bits of the A register for programming purposes with the COpy (77.2) or CINS
(77. 3) instructions.

Rev. C

4-10

TABLE 4-5.
Mask Bits

INTERRUPT MASK REGISTER BIT ASSIGNMENTS
Mask Codes

00
01
02
03
04
05
06
07
08
09

0001
0002
0004
0010
0020
0040
0100
0200
0400
1000

10
11

2000
4000

Interrupt Conditions Represented
I/O Channel 0. .
1
2
(Includes interrupts
3 >generated within the
4
channel
and external
5
equipment interrupts. )
6
7;
Real-time clock
Exponent overflow / underflow and BCD
faults
Arithmetic overflow and divide faults
Search/ Move completion

INTERRUPTS DURING EXECUTIVE MODE
Although all interrupts can be recognized during Executive mode, special
consideration must be given to handling these interrupts. During Executive
mode, the Condition register records current operating information that must
temporarily be stored in the event of interrupt to enable proper recovery.
Table 4-6 lists the Condition register bit assignments.
TABLE 4-6.
Bit

CONDITION REGISTER BIT ASSIGNMENTS
Condition Represented

-

00

Boundary Jump

01

Destructive Load A -

02

Operands Relocated Using OSR
Program State Jump-

03
04
05

Interrupt System
Enabled
Program State

-

Set by SBJP (77. 62) instruction.
Cleared by next jump instruction.
Set by SDL (77. 624) instruction.
Cleared by next LDA instruction.
Set by ROS (55.4) instruction.
Cleared by RIS (55. 0) instruction.
Set by any jump during Program State.
Cleared when jumping to Program State.
Set by EINT (77. 74) instruction.
Cleared by DINT (77.73) instruction.
Set when jumping to Program State.

To insure the processing of stacked interrupts, it is necessary to transfer these
conditions to the A register at the start of the interrupt routine by executing a
CRA (77. 63) instruction. At the completion of the interrupt routine, these
conditions must be restored by executing a ACR (77.634) instruction.

4-11

Rev. F

Upon interrupt recognition, the interrupt system is automatically disabled and
the Central Processor enters the Monitor State. The Condition register and all
interrupts, except Trapped Instruction interrupts, are disabled during the intervals between interrupt recognition and CRA instruction execution, and between
execution of the ACR instruction and the jump instruction normally used to exit
from an interrupt routine.
The Condition register is cleared as the transfer to A is completed; the interrupt
system remains disabled until a EINT (77.74) or ACR instruction is executed.

INTERRUPTS DURING

I

I

BOP

INSTRUCTIONS

Interrupts are recognized near the end of the first RNI of all instructions.
However, after the first RNI of BDP instructions, Main Control continually
tests for active interrupt conditions. If a selected interrupt (or Abnormal
interrupt) condition becomes active, an Interrupt Stop signal is sent to the BDP
section. The BDP relinquishes control after the current character operation
is completed. The interrupt is actually recognized as Main Control rereads
the instruction at P, or at the address of the next instruction if the current
instruction was completed.
The BDP records interrupt recovery conditions (refer to the LBR instruct ion),
and enables operating information to the B3 register. If recovery from
interrupts is desired, the interrupt routine used must contain a SBR instruction to store the recorded interrupt recovery conditions, and a LBR instruction to return the recovery conditions to the BDP once the interrupt processing
is completed. These conditions normally enable a restart to be made from
the point of interrupt. Exceptions to the recovery start are: the 66. 0 and 66. 1
instructions always restart from the beginning if interrupted, and if the
interrupt is because of an illegal Write, the instructions 66.2 through 66.5
(3312 and 3304-2) and 66.4 and 66.5 (3304-3) also restart from the beginning.
The (B3) register has the fOllowing significance when a BDP instruction is
interrupted:
Bits 00 - 11, record the count of the Field C characters processed prior
to interrupt.
Bit 12

=:

"1", if a second pass (complementing operation) was in progress.

Bit 13 =: "1", if an arithmetic carry was generated on a ADM or SBM
instruction.
Bit 14

RevK

=:

"1", if a BCD fault occurred.

4-12

5. INSTRUC:TIONS

GENERAL INFORMATION
A 3300 machine coded instruction word is 24 bits in length and may require up
to three sequential words for a particular function. Although there are 24 distinct instruction formats, as illustrated in Appendix D, there are several that
are used more frequently than others. These formats (word oriented, character
oriented, and business oriented) are shown in the following pages along with
their appropriate instruction param eters.

Instruction Parameters
The following parameters are used in the 3300 instruction list. A capitalized
letter generally indicates a modified parameter, however, this is not always
the case and the specific instruction should be consulted. Some parameters are
general in nature, i. e., specifying a character address, but in some instances
may indicate a high order address and in others a low order address. The
parameter descriptions listed below each instruction format should be checked
for the explicit memory of the parameters for that particular instruction.
If an octal number appears in the format of a specific instruction, only that
number must be placed in the exact position as indicated. In cases where only
a single binary position is involved, a "1" or "0" is used depending upon the
instruction. The following parameters are used throughout the 3300 instruction
list:
(1) variable length field of characters designated field A
in BDP instructions; usually the transmitting field.

A

(2) A is used in the descriptions for instructions (other
than those for BDP) to indicate the A register.

a

addressing mode (a = "0" for direct addressing, a = "1"
for indirect addressing)

B

"1" for backward storage

b

=

index register designator 1, 2, or 3.

5-1

Rev. A

index register flag for a field in certain BDP instructions.
The flag indicate s which index register will have its contents added to the unmodified address 1m I. M:= m + [Bm]
for these instructions only.
index register flag for a field in certain BDP instructions
where both fields are specified by word addresses. The
flag indicates which index register will have its contents
added to the unmodified addre ss In I.

B

index register flag for field A in most BDP instructions
(refer to individual instruction descriptions). Initial
character address of field A is defined: R = r + [ Br]' If
Br = 1 or 3, use (B1); if Br = 2, use (B2); if Br = 0, no
indexing is performed and R = r.

r

index register flag for field C in most BDP instructions
(refer to individual instruction descriptions). Initial
character address of field C is defined: ,8 = s + [Bs] .
If Bs = 1 or 3 use (Bl); if B s:= 2, use (B2); if Bs := 0, no
indexing is pe dormed and 8 = s.
variable length field of characters designated field C in
BDP instructions. Usually the re cei ving field.

C

ch

:=

denotes I/O channel (0 through 7).

DC

indicates delimiting character position within the instruction
word or mnemonic. Generally, a delimiting character of 6
or 8 bits is specified in an instruction and if a character is
recognized, during the particular operation, that equals the
delimiting character, the operation is terminated.

G

"111 for word count control with the INPC and INPW instructions.

H

indicates special Assembly/ Disassembly operation in
certain character oriented I/O instructions.

INT

"111 for interrupt upon completion in certain I/O instructions.

I

assembly language designator indicating indirect addressing.

i

=

internal parameter (decrement or increment).

j

Jump designator.

k

(1) unmodified shift count for 8HA, 8HQ, and SHAQ
instructions.
(2) scale factor for SCAQ instruction.
(1) modified shift count, K = k + (B b ) for SHA, SHQ,
and SHAQ instructions.
(2) residue quantity for 8CAQ instruction.

K

field length of data block for MOVE instruction.
number of characters in BDP field A (character count).
number of characters in BDP field C (character count).

Rev. B

5-2

m

=

unmodified 15- bit storage word address.

M

=

modified 15-bit storage address.

n

=

same as 'm', but the word address of the second operand
for certain I/O instructions.
indicates special Assembly/Disassembly operation in
certain word oriented I/O instructions.

N
r

=

unmodified 17-bit character address.
modified 17-bit character address:
R = r + (B r ) for BDP instructions. (Refer also to 'Br '. )
R = r + (Bb) for all other instructions.

R

s

b
M = m + (B ).

=

same as 'r', but the character address of the second operand for certain I/O instructions.
(1) modified 17-bit character address of field C for BDP
instructions only. S = 's + (B s )' (Refer also to 'Bs '. )

S

(2) also used to denote sign extension for certain instructions.
SC

6-bit comparison scan character used in search instructions.
May be used with DC.

v

a specific register number (00-77) within the Register
File.

w

7-bit Page Index File address. (Refer to APF and PFA
instructions and Appendix E for additional information. )

x

=

connect code or interrupt mask.
15- bit operand

y

z

=

17- bit operand

/1//1/

=

slashing indicates a particular area of an instruction that
should be loaded with zeros although the particular area is
not used for the instruction.

In addition to the instruction parameters, various abbreviations are used in the
instruction descriptions that refer to various registers and operations. These
abbreviations and their literal meanings are listed here:
ISR
OSR
CIR
CR
BCR
PIF

=
=

Instruction State register
Operand State register
Channel Index register
Condition register
BDP Condition register
Page Index File
contents of the lower 3 bits (00, 01, and 02) of the A register
contents of the index register as defined by the value of the
Br flag.

5-3

Rev. F

in "less

mn
m>n
men
(m)-+n

than" n

m "greater than" n
m I, greater than or equal to' I n
logical product of m and n
contents of m, transferred to n
Exclusive OR function
AND function

V
/\

Instruction Word Formats
Word oriented instructions are the most common of the instruction formats.
Fifteen bits are allocated for an unmodified storage addre ss, operand, or shift
count. Indirect addressing is usually available. Figure 5-1 illustrates a word
oriented instruction and the significance of the first 15 bits when they repre sent
an unmodified word addre ss 'm'.

BITS_23

IS
(6 BITS)

r-"----.
17
16
1514

00
(15 BITS)

IOSIT)I(2 BITS)I

L---~v
FUNCTION CODE

'~~'L-----------------'vr----------------~
a
b
m

k
y

Symbol designators
(See Symbol Definitions)
Figure 5-1.

Word-Addressed Instruction Format

Character oriented instructions allocate 17 bits for unmodified character addresses or extended operands. Indirect addressing is not available for these
instructions; however, address modification is permissible by referencing a
specific index register. Figure 5-2 illustrates the format of a character
oriented instruction word and the significance of the first 17 bits when they represent an unmodified character address 'r'.
IS

23

17

16

00

(6 BITS)

1(1 BIT)I

( 17 BITS)

v

''-..r--l'

v

FUNCT ION

CODE

b

z

Characters in a data word are always specified in the following manner:
23

I
~

0605

12 II

1817

o

2

\

00

3

1/

character designators
Figure 5-2.
Rev. A

Character-Addressed Instruction Format
5-4

Word Addressing/Character Addressing
It is often desirable to convert a word address and character position to its

corresponding character address or vice versa.
technique used for this purpose.

The following procedure is a

To convert a word address to a character address:
II

Octally multiply the word address by four. (During program execution,
this operation is simulated by a left shift of two binary places.)

•

Add the character position to the product.

The sum is the character address.

EXAMPLE:
Given:

Word address 12442, character position 2

Find:

Corresponding character address

1.

12442
x4
52210
+2
52212 = character address

2.

To convert a character address to a word address:
lID

Octally divide the character address by four

The quotient is the word address and the remainder is the character position.
No remainder indicates character zero.
EXAMPLE:
Given:

Character address 03442

Find:

Word address and character position
00710

-±J 0 3442
34
4
4

2

remainder = character position 2
NOTE

Octal multiplication and division tables may be found in
Appendix C of this manual.
Instruction word formats that differ from word and character orientation are described in the instruction listing.
Business oriented instructions require three instruction words to completely
define an operation. These instructions are executed only by the BDP. These
subinstruction words are always located at consecutive memory locations,
nominally designated P, P+1, and P+2.
5-5

Rev. A

r - " I " FOR DELIMITING WHEN AVAILABLE
18

23

17

(17 BITS)

L-----,vr----~I
FUNCTION

23

P+I

00

16

(6 BITS)

P

I

\~------------------~Vr-------------------J

CODE

21 20

r OR m (15 BITS)

19 IB

00

17 16

(3 BITS) 1(2 BITS)I(2 BITS)I

(17 BITS)

I

~~~\~---------------'vr----------------~I
SU~OD~CN Br OR Bm BsOR Bn

s OR m OR n (15 BITS)

00

12 II

23

I

p+21

\~-------------'v,------------~!lL------------,v'------------~

~~

S2
(6 BITS)

\'-------,v
DC

OR

(B BITS)
L-------~vr--------~

OR

(6 BITS)

DC

~

V

SC

OR

I

I
\

(6 BITS)

V

I

1\

SC

Figure 5-3.

I

(6 BITS)

1

V
DC

Business Oriented Instruction Format

Indexing and Address Modification
In some instructions, the execution address 'm' or 'r', or the shift count 'k'
may be modified by adding to them the contents of an index register, Bb. The
2- bit designator 'b' specifies which of the three index registers is to be used.
Symbols representing the respective modified quantities are M, R, and K.
M = m + (Bb)
R = r + (Bb) the sign of Bb is extended to bit 16 (2 17 _1)
K = k + (Bb)

In each case, if b = 0, then M

Rev. A

= m,

5-6

R = rand K

= k.

SpeCial index considerations apply to BDP instructions where an index register
flag is pre sent. A flag defines which index register is used for indexing:
EXAMPLE:

Bs = 2, and (B2 = 00364, then S = s + [Bs] or "the
modified address'S' equals the unmodified address's' added to the
contents of the index register as defined by Bs".

If s = 00413,

Thus:

= s + [ Bs]
S = 00413 + (B2)
S = 00413 + 00364
S

S = 00777
Some BDP instructions, i. e. , PAK, CVBD, DTA, etc. utilize both word and
character addresses in their formats. Although the first two bits preceding the
address are unused and not part of the word address, the lower 15 bits of this
word are added to the contents of the specified index register. The lower two
bits of the specified index register must be set to "1' s" to allow for an endaround carry during the index addition.
EXAMPLE:
'61514

020100

n

,
I
I

L-------~vr----------~I

[Bn] are added to
the first 15 bits

Addressing Modes
Three modes of addressing are used in the computer: No Address, Direct Address, and Indirect Address.
No Address
This mode is used when an operand 'y' or a shift count 'k' is placed directly into the lower portion of an instruction word. Symbols 'a' and fbi are not used as
addressing mode and index designators with any of the no address instructions.
Direct Address
The direct addressing mode is used in any instruction in which an operand address 'm' is stored in the lower portion of the initial instruction word. This
mode is specified by making 'a' equal to O. In many instructions, address 'm'
may be modified (indexed) by adding to it the contents of register Bb, M = m +
(EO).

5-7

Rev. B

Indirect Address
It is possible to use indirect addressing only with instructions that require an
execution address 'm'. For applicable instructions, indirect addressing is
specified by making 'a' equal to 1. Several levels (or steps) of indirect addressing may be used to reach the execution address; however, execution time is
delayed in direct proportion to the number of steps. The search for a final execution address continues until 'a' equals O. It is important to note that direct
or indirect addressing and address modification are two distinct and independent steps. In any particular instruction, one may be specified without the
other. Figure 5-4 shows the indirect addressing routine.
GO TO ADDRESS M.
ACQUIRE NEW
TERMS 0, b, AND m

NO

ORIGINAL
INSTRUCTION
POSSIBLY
CONTAINING
'0' AND/OR 'b'

NO

EXECUTE
INSTRUCTION
USING
ADDRESS M

ADD THE
(Bb)TOm

Figure 5-4.

Indexing and Indirect Addressing Routine Flow Chart
NOTE

Unless it is otherwise stated, indirect addressing follows the
above routine throughout the list of instructions.

Rev. A

5- 8

Indexing and Indirect Addressing Examples
The following examples utilize the LDA (20) instruction; however, the process
applies to any of the instructions with an 'a' and/or 'b' designator.
EXAMPLE 1:
(ADDRESS MODIFICATION - (indexing) ONLY)

1

I

202~

P = 00000

t

Indicates Direct Address
mode and address modification
by B2

(B2) " 13342

Add this address to (B2)

~

54430
+13342
20 2 67772 0 or + }

JMP, ZRO

Jump if BDP register

JMP, LOW

Jump if BDP register < 0 or -

LACH

Load A character

5-49

LBR

Load BDP Condition register

5-167

LCA, I

Load A complement

5-50

LCAQ, I

Load AQ complement (double precision)

5-51

LDA, I

Load A

LDAQ, I

Load AQ (double precision)

5-49
5-50

LDI, I

Load index

5-52

LDL, I

Load logical

LDQ, I

Load Q

5-50
5-51

LPA, I

Logical product with A

5-71

LQCH

Load Q character

5-52

MEQ

Masked equality search

5-73

MOVE,INT

Move (S) characters from r to s

MTH

Masked threshold search

MUA, I

Multiply A

5-115
5-74
5-62

MUAQ, I

Multiply AQ

5-63

MVBF

Move and blank fill

5-125

MVE

Move

5-123

MVE, DC

Move, delimiting character possibility

MVZF

Move and zero fill

5-124
5-126

MVZS

Move and zero suppress

5-127

MVZS,DC

Move and zero suppress, delimiting character
possibility

=0

5-40
5-42

OSA

Transmit (OSR) to A

5-128
5-37

OTAC,INT

Character-addressed output from A

5-106

OTAW,INT

Word-addressed output from A

5- 107

OUTC, INT, B, H

Character-addressed output from storage

5- 99

OUTW, INT, B,N

Word-addressed output from storage

5-101

PAK

Pack 6 bit BCD characters into 4 bit BCD
characters

5-152

5-15

Rev. K

I

I

I

TABLE 5-1.

INSTRUCTION SYNOPSIS AND INDEX (Cont'd)

Mnemonic

I
I

I

Instruction

Page No,

PAUS

Pause

5-82

PFA

Transmit (PFI) to A

5-39

PRP

Priority pause

5-83

QEL

Transmit (Q) to EL

5-36

QSE

Skip next instruction if (Q)

5-29

QSE,S

Skip next instruction if

QSG

Skip next instruction if (Q):::: y

QSG,S

Skip next instruction if (Q) :::: y, sign extended

RAD, I

Replace add

5-29
5-30
5-30
5-60

RIS

Relocate to instruction state

5-109

ROS

Relocate to operand state

RTJ

Return jump

5-109
5-47

SACH

Store character from A

5-54

SBA, I

Subtract from A.

5-61

SBAQ, I

Subtract from AQ

5-61

SBCD

Set BCD fault

5-86

SBJP

Set boundary jump

SBM

Subtract field A from fie lel C

;)-109
;)-156

STIR

St

SCA, I

Selectively complement A

OJ'('

H 1)1)

SCAN, LR, EQ, DC

=Y
(Q) = y, sign extended

;i-168

Condition register

5-70

left to right, stop

Oll

5-139

=

stop on f

SCAN, LR, NE, DC
Scan

<

SCAN, RL, EQ, DC

right t:J left, stop on =
'-

5-141
Delimiting
character
possibility

5-143

stop on f

5-145

SCAN, LR, EQ

left to right, stop on =

5-138

SCAN, LR, NE

stop on f

5-140

SCAN, RL, EQ

right to left, stop on =

5-142

SCAN, RL, NE

stop on f

5-144

SCAN, RL, NE, DC

Scan

SCAQ

Rev. K

5-59

Scale AQ

5-16

TABLE 5-1.

INSTRUCTION SYNOPSIS AND INDEX (Cont'd)
Instruction

Mnemonic

Page No.

SCHA, I

Store 17- bit character address from A

5- 56

SCIM

Selectively clear interrupt mask

5-85

SDL

Set destructive load

5-110

SEL

Se lect function

5-92

SFPF

Set floating point fault

5-86.

SHA

Shift A

5-57

SHAQ

Shift AQ

5-59

SHQ

Shift Q

5-59

SJ1

Jump if key 1 is set

5-41

SJ2

Jump if key 2 is set

5-41

SJ3

Jump if key :3 is set

5-41

SJ4

Jump if key 4 is set

5-41

SJ5

Jump if key 5 is set

5-41

SJ6

Jump if key 6 is set

5-41

SLS

Selective stop

5-24

SQCH

Store character from Q

5-55

SRCE,INT

Search character equality

5-111

SRCN,INT

Search character inequality

5-113

SSA,.I

Selectively set A

SSH

Storage shift

5-70
5-57

SSIM

Selectively set interrupt mask

5-85

STA, I

Store A

5-53

STAQ, I

Store AQ

5-54

STI, I

Store index

5-56

STQ, I

Store Q

5-55

SWAt I

Store 15-bit word address from A

5- 56

TAl

Transmit (A) to Bb

5-33

TAM

5-34

TJA

Transmit (A) to high speed memory
b
Transmit (B ) to A

5-33

TIM

Transmit (Bb) to high speed memory

5-35

TMA

Transmit (high speed memory) to A

5-34

5-17

Rev. K

I

I
I

TABLE 5-1.

INSTRUCTION SYNOPSIS AND INDEX (Cont'd)

Mnemonic

I

I
I

I

Instruction

Page No.

TMAV

Test memory availability

5-77

TMI

Transmit (high speed memory) to Bb

TMQ

Transmit (high speed memory) to Q

TQM

Transmit (Q) to high speed memory

TST
TSTN
UCS
UJP, I
UPAK

Test field A for +, -, 0
Test field A for numeric
Unconditional Stop
Unconditional Jump

5-35
5-34
5-34
5-165
5-166
5-24
5-41
5-153

XOA
XOA,S
XOI
XOQ

Unpack 4 bit BCD characters into 6 bit BCD
characters
Exclusive OR y and (A)
Exclusive OR y and (A) , sign extended
Exclusive OR y and (Bb)
Exclusive OR y and (Q)

XOQ,S

Exclusive OR y and (Q) , sign extended

I ZADM

Zero and add

5-69

5-129

No-Operation Instructions

When ~n attempt is made to execute one of the following instructions at the
current execution ~ddress, P, the computer recognizes. them as No-Operation
(NO-OP) instructions and advances to the next execution address, P + 1. In
mnemoniCs a No-Operation instruction is written as: NOP.
NO-OPERATION
OCTAL CODES

02
14
15
16
17

0
0
0

0
0

During non- Executive mode operation each of the following instructions are recognized as No-Operation instructions if an attempt is made to execute one of
them. Also refer to Trapped Instruction processing, Section 4.
ACI
AIS
AOS
APF
CIA

Rev. K

ISA
ROS
JAA
SBJP
OSA
SDL
PF A
SR:t\=
-RCRTMAV
RIS f',,,:.:\L

5-18

eX A

Instruction Execution Times
Except for the 64.0 through 77. 1 instructions, an actual instruction execution
time consists of the base execution time listed plus the time for an RNI cycle.
If indexing or indirect addressing is used, their execution times must be added
to base instruction time.
Relocation time is added only if the RNI or RADR cycle preceding the RNI or
RADR currently in progress was in a different Iuemory page or if the ROP or STO
cycle preceding the ROP or STO in progress was in a different memory page.
That is, by programming RNI's and RADR's in the same page and ROP's and
STO's in the same page, relocation processing time can be minimized.
Table 5-2 is an octal list of all 3300 instructions with their base execution
times. During certain multiple cycle instructions, it is possible to execute
other instructions concurrently, thus no additional execution time is required.
TABLE 5-2.

SUMMARY OF INSTRUCTION EXECUTION TIMES, USEC

Instruction
Processing Operation
RNI cycle

Time Added to Base
Execution Time (usee)

1. 375

Indexing (address modification)

.375

Relocation

.250*

Indirect addressing

.

1. 375

':'The time added to base execution time is O. 150 usee if the Multiprogramming
Module is present and no relocation is performed.

5-19

Rev. H

Basic
Octal
Code

Mnemonic
Code

TABLE 5-2 (Cont'd)
Execution
Basic
Time
Octal
Mnemonic
(usee)
Code
Code

Execution
Time
(usee)

00

HLT

0.000

17

ANI

0.000

00

SJI-6

0.000

17

ANA

0.000

00

RTJ

I, 375

17

ANQ

0.000

01

UJP

0.000

20

LDA

1. 375

02

IJI

0.000

21

LDQ

1.375

02

IJD

0.000

22

LACH

1. 375

03

AZJ

0.625

23

LQCH

1. 375

03

AQJ

0.625

24

LCA

1. 375

04

ISE

0.625

25

LDAQ

2.625

04

ASE

0.625

26

LCAQ

2.625

04

QSE

0.625

27

LDL

1. 375

05

ISG

0.625

30

ADA

1. 375

05

ASG

0.625

31

SBA

1.375

05

QSG

0.625

32

ADAQ

2.625

06

MEQ

2.375

+ 2. 5n

33

SBAQ

2.625

07

MTH

2.375 + 2. 5n

34

RAD

2.625

10

SSH

2.625

35

SSA

1. 375

10

lSI

0.625

36

SCA

1. 375

10

ISD

0.625

37

LPA

1. 375

11

ECHA

0.000

40

STA

1. 375

12

SHA

O. 000 to 1. 375

41

STQ

1.375

12

SHQ

O. 000 to 1. 375

42

SACH

1. 375

13

SHAQ

O. 000 to 1. 375

43

SQCH

1. 375

13

SCAQ

o. 875

44

SWA

1. 375

14

ENI

0.000

45

STAQ

2.625

14

ENA

0.000

46

SCHA

1. 375

14

ENQ

0.000

47

STI

1. 375

15

INI

0.000

50

MUA

6.875 to 9. 875

15

INA

0.000

51

DVA

10.250

15

INQ

0,000

52

CPR

1. 375 to 2. 625

16

XOI

0.000

53

TIA

O.ClOO

16

XOA

0,000

53

TAl

0,000

16

XOQ

0.000

53

TMQ

0,625

Rev,F

to 2. 250

5-20

TABLE 5-2 (Cont'd)
Basic
Octal
Code

Mnemonic
Code

Execution
Time
(usee)

Basic
Octal
Code

Execution
Time
(usee)
CD 9+3. 1'd+ O. 75 S2

53

TQM

0,625

53

TMA

0.625

53

TAM

0.625

67

53

TMI

0.625

67

t

CMP

10.7 + O. 9S 2
10.7 + O. 9T

53

TIM

0.625

67 t

CMP

16.4 + .9n

53

AQA

0, 000

67

CMP,N

10.7 + .9T

53

AlA

0.000

67

TST

53

IAI

O. 000

09.4
CD 8. 5 + 0, 9 S 1

54

LDI

1. 375

67

TSTN

CD8.5 +0. 9 Sl

55

RIS

0.000

56

MUAQ

57

DVAQ

60

FAD

4.850 to 6.250

70
70
70
71
71

61

FSB

4.850 to 6.250

62

FMU

16.0

73

LBR
JMP
SBR
SRCE
SRCN
MOVE
INPC

63

FDV

19.0

73

INAC

-"~-

64

MVE

10.7 + O. 9 S

74

INPW

::;::

64

MVBF

74

INAW

:::::

64

MVZF

10,7 + O. 9S 2
12. 9 + O. 9S 2

75

OUTC

-,--"

64

MVZS

75

OTAC

-,-w

64

FRMT

76

OUTW

::::::

64

EDIT

10.7+ O. 9S 2
10.7 + O. 9S
2
(i)9+3. 1'd+ O. 75S2

76

OTAW

CD 13+3. 1 'd+1. 65 S2

16.

a to

67

Mnemonic
Code
ADM & SBM

013+3. 1'd+ 1. 65 S2

,

a

19.

25.5

72

ZADM

it

4. 9
1. 44
4. 9
::!:::

-,-

,~

-","
:1.~

77

CON

-'-,--,--,-

65

SCAN

8.5 + O. 9 S2

77

SEL

-,-

66

CVBD

17.9+ 0.92 [Q' (1+M) +
{3M +8N +20N +28N ]
1
2
1
3

77

EXS

0.000

77

COpy

0.000

66

CVDB

CD 13. 7 + O. 92 (3N 1 +
6N2 + 8N3)

77

INS

0.000

77

CINS

0.000

77

INTS

0.000

77

INCL

0.000

'77

IOCL

0.000

77
77

CILO

0.000

CLCA

0.000

77

SSIM

0.000

77

SCIM

0.000

CD 13, 7 + O. 92 (4N 1 +
ION 2 + 14N 3 - 1)

t
66 t

DTA

10. 7 + 1. 1 S

ATD

10.7 + 1. 1 S

66

PAK

10.7

66

'UPAK

66

-+-

0.9 Sl

10.7+ O. 9S

1

I

~-

t3312 and 3304-2
only

1t 3304-3

5 -21

I

RevK

1

TABLE 5-2 (Cont'd)
Basic
Octal
Code

Mnemonic
Code

Execution
Time
(usec)

Basic
Octal
Code

Execution
Time
(usec)

Mnemonic
Code

77

ACI

0.000

77

AOS

0.000

77

CIA

0.000

77

AIS

0.000

77

JAA

0.000

77

OSA

0.000

77

IAPR

0.000

77

ISA

0.000

77

PAUS

40 ms

77

SLS

0.000

77

PRP

40 ms

77

SFPF

0.000

77

TMAV

77

SBCD

0.000

77

SBJP

0.000

77

DINT

0.000

77

SDL

0.000

77

EINT

77

CRA

0.000

77

CTI

0.000
....

77

ACR

0.000

77

CTO

77

APF

0.000

77

UCS

77

PFA

0.000

n

=

a to
o. a to
O.

1. 375 or 6.375 us

'"

*

0.000

number of characters searched
number of characters in source field (A)
number of characters in result field (C)
number of most significant 4-bit binary groups (in the lower 24 bits to be
converted) which have a zero value
number of most significant 4-bit binary groups (in the upper 24 bits to be
converted) which have a zero value (see example)
number of characters up to and including three in number (For the CVBD
instruction, the term character defines a binary group of 4 bits to the
right of any consecutive lead groups which are all zero.
See example.)
number of characters from three, up to and including seven in number.
(See example.)
number of characters greater than seven in number (For the CVBD
instruction, the term character defines a binary group of 4 bits to the right
of any consecutive lead groups which are all zero. See example.)

S

=

number of characters in the smaller of fields Sl and S2'

= O.
one or more of the upper 24 bits to be converted is a "1", 13 = 1, if not

If all upper 24 bits to be converted are zero,

'd

Rev. F

= 1; if not

Q'

If
{3 = O.

{3
T

Q'

=

number of characters in the longer of fields Sl and S2'

=

Dependent upon a variable signal response time from an external equipment
or internal source; i. e., Block Control.

=

number of 4 character groups in field ~2 :
5-22

CD

®
CD
CD
®
®

G)

=

best case (no second pass)

=

worst case (second pass required)

=

best case (no carry propagation)

=

worst case (maximum carry propagation)
worst case (maximum carry propagation and second pass required)

=

best case (field t= zero)

=

worst case (entire field

= zero)

SPECIAL P ARAME TER EXAMPLES

M1

= 2 in this case

23 20 19 16 15 12 11 08 07 04 03 00

(M)

=

I I
0

I

0

I

5

I

6

I

7

3

I

~-----------.vr-------------~

N3
N3 = 3

23 20 14 16 15
(M+ 1) =

I

2

I

1

I

v

12 11 08 07
3

I

1\

N2

0

I

04 03
4

I

00
5

I

v
Nl

N2 = 4

Nl = 3

Data words are divided into six 4 -bit groups internally by the CPU and are shown here
only to illustrate the parameters necessary for determining the instruction execution
time.
.

5-23

Rev. A

Halt and Stop Instructions

Operation Field
HLT
SLS
UCS

HLT·
Halt

Address Field

Interpreta tion

m

Halt
Selective stop
Unconditional stop

00
77
77

23

18 17

15 14

0

00

00

I

m

Instruction Description: Unconditionally halt at this instruction.
ing, RNI from address m.

Upon restart-

Comments: Indirect addressing and address modification may not be used.

SLS
Selective Stop

23

1817

I

77

70_
12 II

00

Instruction Description: Program execution halts if the SELECT STOP switch
on the console is set. RNI from address P + 1 upon restarting.
Comments: Bits 00 through 11 should be loaded with zeros.

UCS
Unconditional Stop

23

7

18 17

12 II
77

Instruction Description: This instruction unconditionally stops the execution of
the current program. RNI from address P + 1 upon restarting.
Comments: Bits 00 through 11 should be loaded with zeros.

Rev. A

5-24

Enter Instructions

Operation Field
ENI
ENA
ENA,S
ENQ
ENQ, S
ECHA
ECHA, S

14
14
14
14
14
11
11

ENI

Address Field

Interpretation

y, b
Y
Y
Y
Y
z
z

Enter
Enter
Enter
Enter
Enter
Enter
Enter
23

index b with y
A with y
A with yand extend sign of y
Q with y
Q with y and extend sign of y
A with z
A with z and extend sign of z

18 17 16 15 14

00

y

Enter Index with y

b = index register designator

Instruction Description: Clear index register Bb and enter y directly into it.
Comments: If b = 0, this is a no-operation instruction.

ENA

23

Enter A with y

18 17
14

15 14

I I
6

00

y

Instruction Description: Clear the A register and enter y directly into A.
ENA, S

23

Enter A with y, .
Sign Extended

18 17

1514

00

y

14

Instruction Description: Same as ENA except the sign of y is extended.

ENQ

23

1817

7

14

Enter Q with y

1514

I

00

y

Instruction Description: Clear the Q register and enter y directly into Q.
ENQ, S
Enter Q with y,
Sign Extended

23

1817
14

I

1514
5

00

y

Instruction Description: Same as ENQ except the sign of y is extended.
5-25

Rev.F

ECHA
Enter Character
Address into A

23

18 17 16

II

H

00

z

Instruction Descriftion: Clear A; then enter a 17-bit operand z (usually a
character address into A.
ECHA,S
Enter Character
Address into A, Sign Extended

23

181716

00

z

Instruction Description: Clear A; then enter a 24- bit operand (17-bit z plus
7 bits of sign extension) into A.

NOTE
If is often desirable to perform operations with the A or Q registers

using a negative operand. By using the sign extension feature of certain instructions, 14-bit negative operands become available. This
feature eliminates the need, in many instances, to reference prestored
operands.
The following examples illustrate the use of sign extension in some instructions:
EXAMPLE A:

To enter negative zero into Q, execute a 14 5 77777.

EXAMPLE B:

To increase (A) by -17

J

execute a 15477760 instruction.

(A) = 00066667 (arbitrary value)

(end around carry)

77777760
00066647
1
00066650 =(A) after instruction execution

In all cases of sign extension, bit 14 for 15-bit y operands and bit 16 for 17-bit
z operands determines the sign of the quantity.

Rev. C

5-26

Increase Instructions

Opera tion Fie ld
INI
INA
INA, S
INQ
INQ, S

15
15
15
15
15

INI
Increase Index by y

Interpreta tion

Address Field
y, b
Y
y
Y
y

Increase
Increase
Increase
Increase
Increase

23

index by y
A by Y
A by y, sign extended
Q by Y
Q by y, sign extended

1817161514

~~lo~lb~I

00

_____Y_ _ _ _~1

b = index register designator
Instruction Description: Add y to (B b ).
Comments: If b = 0, this is a no-operation instruction.
extended.

INA
Increase A by y

23

I

1817
15

I

Signs of y and Bb are

1514
6

I

00

Y

Instruction Description: Add y to (A).
INA, S
Increase A by y,
Sign Extended

23

C!5

1817

00

1514

Y

Instruction Description: Same as INA except the sign of y is extended.

INO
Increase

0 by y

23

1817

00

1514

C!,_5~1_7~1

______Y______~

Instruction Description: Add y to (Q).
INO, S
Increase

0 by y,

Sign Extended

23

~

1817

1514

00

Y

Instruction Description: Same as INQ except the sign of y is extended.

5-27

Rev. A

Skip Instructions

Operation Field

Address Field

ISE
ASE
ASE,S

04
04
04

y,b
Y
Y

QSE
QSE,S

04
04

Y
Y

ISG
ASG
ASG, S

05
05
05

y,b
Y
Y

QSG
QSG, S

05
05

Y
Y

lSI
ISD

10
10

y, b
y,b

Interpreta tion
Skip next instruction if (Bb) = Y
Skip next instruction if (A) = y
Skip next instruction if (A) = y. Sign of
y is extended.
Skip next instruction if (Q) = Y
Skip next instruction if (Q) = y. Sign of
Y is extended.
b
Skip next instruction if (B ) 2: y
Skip next instruction if (A) 2: y
Skip next instruction if (A) 2: y. Sign of
y is extended.
Skip next instruction if (Q)2: y
Skip next instruction if (Q) 2: y. Sign of
y is extended.
Index skip, incremental
Index skip, decremental

NOTE
The SSH (10. 0) instruction, which also uses
a Skip exit, is described in the Shift and Scale
Instruction group.

ISf

23

18 17 16 15 14

Skip Next
b
Instruction if (B ) = Y

00

y

b

= index

register designator

b
Instruction Description: If (B ) = y, skip to address P+2; if not, RNI from address P+1.
Comments: If b = 0, Y is compared to zero.

Rev. F

5-28

ASE
Skip Next
Instruction if (A) = Y

23

IB 17

~

1

00

1514

y

6

Instruction Description: If (A) = y, skip to address P+2; if not, RNI from address P+l.
Comments: Only the lower 15 bits of A are used for this instruction.

ASE,S
Skip Next
Instruction if (A) = y, Sign E)(tended

IB 17

23

~

15 14

00

__~1_4__~_______Y________~

Instruction Description: Same as ASE except the sign of y is extended.
24 bits of A are recognized.
QS';

Skip Next
Instruction if (Q) = y

23

IB 17

~

All

00

15 14

y

7

Instruction Description: If (Q) = y, skip to address P+2; if not, RNI from address P+1.
Comments: Only the lower 15 bits of Q are used for this instruction.

QSE, S
Skip Next
Instruction if (Q) = y, Sign E)(tended

23

IB 17

04

15 14

00

y

Instruction Description: Same as QSE except the sign of y is extended.
bits of Q are recognized.

5-29

All 24

Rev. A

ISG
Skip Next
Instruction if (B b) ~ Y

23

1817161514

00

y

= index

b

register designator

b
Instruction Description: If (B ) are eq:bal to or greater than y, skip to address
P+2; if not, RNI from address P+1. (B) and yare 15- bit positive numbers.
Comments: If b

= 0,

ASG
Skip Next
Instruction if (A)

Y is compared to zero.
23

~

18 17

00

1514

y

05

Y

Instruction Description: If (A) are equal to or greater than y, skip to address
P+2; if not, RNI from address P+1. Only the lower 15 bits of A are used.
Comments: (A

L15

) and yare considered 15-bit positive numbers.

ASG,S
Skip Next
Instruction if (A) ~ y, Sign Extended

1817

23

1514

00

y

05

Instruction Description: Same as ASG except the sign of y is extended. All 24
bits of A are recognized. Positive zero (00000000) is recognized as greater
than negative zero (77777777).
QSG

Skip Next
Instruction if (0)

23

1817

1514

~

00

y

05

y

Instruction Description: If (Q) are equal to or greater than y, skip to address
P+2; if not, RNI from address P+1. Only the lower 15 bits of Q are used.
Comments: (QL15) and yare considered 15-bit positive numbers.
OSG,S
Skip Next
Instruction if (Q) ~ y, Sign Extended

23

L

18 17

05

00

15 14

5

y

Instruction Description: Same as QSG except the sign of y is extended. All 24
bits of Q are recognized. Positive zero (00000000) is recognized as greater
than negative zero (77777777).
Rev. B

5-30

151
Index· Skip,
Incremental

23

00

1817161514

y

b = index register designator
b
Instruction DescriRtion: If (B ) = y, clear Bb and skip to address P+2; if not,
add one to (Bb) and RNI from address P+1.
Comments: The 10.0 instruction is a SSH (storage--shift) instruction, described
later in this section.

ISI INSTRUCTION
TRANSLATED

INCREMENT (Bb)

NO

YES
(Bb)

BY I AND
RNI @ P+I

ISO
Index Skip,
Oecremental

=Y?

CLEAR Bb AND
RNI @

23

P +2

00

1817161514

y

b = index register designator
b
Instruction DescriIIlion: If (B ) = y, clear Bb and skip to address P+2; if not,
subtract one from (BO) and RNI from address P+1.
Comments: When b = 0, RNI from P+1 if y f 0; RNI from P+2 if y = O.

ISD INSTRUCTION
TRANSLATED

DECREMENT (Bb)
BY I AND
RNI @ P+I

NO
(Bb)::

5-31

y ?

YES

CLEAR Bb AND
RNI @ P+2

Rev. A

Inter-Register Transfer Instructions

Operation Field
AQA
AIA
IAI
TIA
TAl
TMQ
TQM
TMA
TAM
TMI
TIM
ELQ
EUA
EAQ
QEL
AEU
AQE
AIS
ISA
AOS
OSA
ACI
CIA
APF
PFA
CRA
ACR
JAA

Address Field

53
53
53
53
53
53
53
53
53
53
53
55
55
55
55
55
55
77
77
77
77
77
77
77
77
77
77
77

b
b
b
b
v
v
v
v
v,b
v, b

w,b
w,b

Interpreta tion
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer

AQA
(A) + (Q)--? A

23

(A) + (Qb to A
(A) + (B ) to A
(Bb) + (A) to Bb
(Bb) to A
(A) to Bb
(Register v) to Q
(Q) to Register v
(Register v) to A
(A) to Register v
(Register v) to Bb
(Bb) to Register v
(EL) to Q
(EU) to A
(EUEL) to AQ
(Q) to EL
(A) to EU
(AQ) to EUEL
(AOO- 02) to ISR
(ISR) to AOO-02
(AOO-02) to OSR
(OSR) to AOO-02
(AOO- 02) to CIR
(CIR) to AOO-02
(AOO-ll) to PIF location 'Wi
(PIF location 'Wi) to AOO-ll
(CR) to AOO-05
'

0

,

18 17
70

I

00

15 14

m

I

m = jump address
Instruction Description: Sense the status of the BCR (BDP Condition Register).
If the result from the preceding BDP operation was zero, jump to address m.

Comments: If the console BDP switch is not active or if the BDP is not present
in the system, this instruction is trapped. (Refer to Section 4.)
23

JMP, HI

Jump i(result is

+ or high

18 17

70

I

00

15 14

m

0

m = jump address
Instruction Description: Sense the status of the BCR (BDP Condition Register),
If the result from the preceding BDP operation was positive or greater than
zero, jump to address m.
Comments: If the console BDP switch is not active or if the BDP is not present
in the system, this instruction is trapped. (Refer to Section 4.)

23

Jump if resu{fi{':"-

or low

1817

70

00

1514

2

I

m

m = jump address
Instruction Description: Sense the status of the BCR (BDP Condition Register).
If the result from the preceding BDP operation was negative or less than zero,

jump to address m.
Comments: If the BDP is not in the system, or the console BDP switch is not
active, this instruction is trapped. (Refer to Section 4. )

Rev. B

5-42

III
Index Jump, Incremental

23

00

IBI7i61514

m

b = index register designator
m = jump address
Instruction Description: If b = 1, 2, or 3, the respective Index register is examined:

1. If (Bb) = 00000, the jump test condition is not satisfied; RNI from address
P+1.
b
b
2. If (B ) f 00000, the jump test condition is satisfied. One is added to (B );
jump to address m and RNI.
Comments: If b = 0, this is a No-Operation instruction; RNI from address
P+1. Indirect addressing and jump address modification may not be used. The
counting operation is done in a oners complement additive accumulator. Negative
zero (77777) is not generated because the count progresses from: 77775, 77776,
to 00000 (positive zero) and stops. If negative zero is initially loaded into Bb,
the count progresses: 77777, 00001, 00002, etc. In this case, the counter must
increment through the entire range of numbers to each positive zero.

INSTRUCTION IN F

RNI FROM
ADDRESS
P+I

YES
b=O?
NO
YES

\

(Bb)= O?
NO

ADD ONE
TO (Bb)

JUMP TO
ADDREss'm';
RNI

5-43

Rev. A

23

/JD
Index Jump, Decremenfal

[

1817161514
02

00

II I I

m

b

b = index register designator
m = jump address
Instruction Description: If b = 1, 2,or 3, the respective Index register is examined:
b
1.
If (B ) = 00000, the Jump Test condition is not satisfied; RNI from address
P+1.
2,

If (Bb) :f 00000, the Jump Test condition is satisfied.
from (Bb); jump to address m and RNI.

One is subtracted

Comments: If b = 0, this is a no-Operation instruction; RNI from address
P+1. Indirect addressing and jump address modification may not be used. If
negative zero (77777) is initially loaded into Bb, the count decrements through
the entire range of numbers to reach 00000 before the program will RNI from
P+1.

INSTRUCTION IN F

RNI FROM
ADDRESS
P+I

YES

\

b=O?
NO

YES
(Bb)= 0

?

NO

SUBTRACT ONE
FROM (Bb)

JUMP TO
ADDRESS 'm';

RNI

Rev. A

5-44

I

AZJ
Condition Compare
A with Zero, Jump

23

1817161514

03

101

00

m

j = jump designator (0-3)
m = jump address
Instruction Description: The operand in A is algebraically compared with zero
for an equality, inequality, greater-than or less-than condition (see table).
If the test condition is satisfied, program execution jumps to address m. If the
test condition is not satisfied, RNI from address P+1.
Comments: Positive zero (00000000) and negative zero (77777777) give identical results when j = 0 or 1. When j = 2 or 3, negative zero is recognized as
less than positive zero. Indirect addressing and address modification may not
be used.
Condition
Mnemonic

Jump
Designator j

EQ
NE
GE
LT

Test Condition
(A) = 0
(A) f 0
(A) ~ 0
(A) < 0

0
1
2
3

INSTRUCTION IN F

1
RNI FROM
ADDRESS
P+ I

NO

IS TEST CONDITION
SATISFIED?

5-45

YES

JUMP TO
ADDRESS Im' j
RNI

Rev. A

-AQJ
Condition Co,rtp(J~e
A with QsJump

23

18 17 16 15 14

I

03

00

m

\11

j = 0-3 jump designator (0-3)
m = jump address
Instruction Description: The quantity in A is algebraically compared with the
quantity in Q for equality, inequality, greater-than or less-than condition (see
table). If the test condition is satisfied, program execution jumps to address
m. If the test condition is not satisfied, RNI from address P+1.
Comments: This instruction may be used to test (Q) by placing an arbitrary
value in A for the comparison. Positive and negative zero give identical results
in this test when j = 0 or 1. When j = 2 or 3, negative zero is recognized as
less than positive zero. Indirect addressing and address modification may not
be used.
Condition
Mnemonic
EQ
NE
GE
LT

Jump
Designator j

Test Condition
(A)
(A)
(A)
(A)

0
1
2
3

= (Q)

f (Q)
:2: (Q)

< (Q)

INSTRUCTION IN F

J
RNI FROM
ADDRESS

P+I

Rev. A

NO

IS T EST CONDITION
SATISFIED?

5-46

YES

JUMP TO
ADDRESS
RNI

'm;

RTJ
Return Jump

23

CO0

18 17

00

15 14

7

I

m

m = jump address
Instruction Description: The address portion of m is replaced with the return
address, P+1. Jump to location m+l and begin executing instructions at that
location.
Comments: This instruction should not be used to transfer control from Monitor
State to Program State. If an R TJ instruction is executed and the Boundary Jump
flag is set (refer to SBJP instruction) J the STO cycle is executed in Monitor State J
i. e. address 'PI is stored at address 'm' of the monitor program. Indirect
addressing and address modification may not be used. An example of an executed
RTJ instruction is illustrated on the following page.
J

INSTRUCTION

IN F

1
STORE ADDRESS P+I
IN THE ADDRESS
PORTION OF (m)

1
BEGIN SUBROUTINE
WITH INSTRUCTION
AT ADDRESS m + I

1
RETURN TO m
FOR ADDRESS P + I

5-47

Rev. A

8

EXECUTE THIS INSTRUCTION

00500 00 7 33444

CURRENT

P+I
P+2

@Y---00502

RTJ INSTRUCTION AUTOMATICALLY
CAUSES ADDRESS OF P+ 1,0050 I ,
TO BE PLACED IN LOWER 15 BITS
OF M,33444,AND EXECUTES THE
ADDRESS AT Mtl,33445

INSTRUCTION AT M
IS USUALLY A JUMP
BACK TO MAIN PROGRAM
WITH PROGRAM EXECUTION
COMMENCING AT Pt I ,00501

,

MEMORY
ADDRESSES

M

33444

M+I

33445

E

M+2 33446
M+3 33447 01 0 3 3 3

CAUSES JUMP BACK TO
M AND INSTRUCTION
AT MIS EXECUTED

RTJ EXECUTION EXAMPLE
Rev. A

5-48

load Instructions
Opera tion Field
LDA, I
LACH
LCA, I
LDL, I
LDAQ, I
LCAQ, I
LDQ, I
LQCH
LDI, I

Interpreta tion

Address Field

20
22
24
27
25
26
21
23
54

m,b
r, B1
m, b
m, b
m,b
m, b
m, b
r, B2
m, b

Load
Load
Load
Load
Load
Load
Load
Load
Load

23

LOA

A
A, Character
A, Complement
A, Logical
AQ
AQ, Complement
Q
Q, Character
Index

00

18 1716 1514

m

Load A

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Load A with a 24- bit quantity from the storage address
specified by M.
Comments: Indirect addressing and address modification may be used.
18 1716

23

I

LACH
Load A, Character

00

22
I
I

02 0100:
00000-77777

I

word address

I
character
designator

If b = 1, r is modified by index
register B1; R = r + (B1).
If b = 0, r is not modified (r = R).

Instruction Description: Load bits 00 through 05 of A with the character from
storage specified by character address R. The A register is cleared prior to
the Load operation.
Comments: Indirect addressing may not be used. Characters are specified in
storage as follows:
23
1817
1211
06 05
00

I

0

I

I

'character
" \
5-49

2

I

3

I

! /
designators
Rev. A

NOTE

Since the sign of Bb is extended during character address modification,
it is possible to only reference within ± 16,383
characters.
10
LCA
Load A, Compfement

23

~

18 1716 1514

00

m

24

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Load A with the ones complement of a 24-bit quantity
from storage address M.
Comments: Indirect addressing and address modification may be used.

LDL
Load A, Logical

23

18 17 16 1514

00

m

a = addressing mode designator
b = index register designator
m = storage addre ss; m=m+(Bb)
Instruction Description: Load A with the logical product (the AND function) of
(Q) and the 24-bit quantity from storage address M.

LDAQ
Load AQ

23

00

18 17 16 1514

m

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Load the A and Q registers with the 24- bit quantities
from addresses M and M+1, respectively.
Comments: Addresses 77776 and 77777 should be used only if it is desirable to
have M and M+l as non-consecutive addresses, since one l s complement arithmetic is used to form M+1.

Rev. A

5-50

00

IB 1716 1514

LCAQ
Load AQ, Complement

m

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Load registers A and Q with the complement of the
24-bit quantities from addresses M and M+l, respectively.
Comments: Addresses 77776 and 77777 should be used only if it is desirable to
have M and M+ 1 as non- consecutive addresses, since one! s complement arithmetic is used to form M+1.

LDQ

23

00

IB 1716 1514

m

Load Q

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Load Q with a 24-bit quantity from storage address M.
Comments: Indirect addressing and address modification may be used.

5-51

Rev. A

00

181716

23
23

LQCH
Load Q, Character

020100:
00000-77777

word address

I

I

character
designator
If b = 1, r is modified by

index register B2; R = r + (B 2).

If b = 0, r is not modified (r = R).
NOTE

Since the sign of Bb is extended during character address modification,
it is possible to only reference within':::= 16,383
characters.
10
Instruction Description: Load bits 00 through 05 of Q with the character from
storage specified by character address R. The Q register is cleared prior to
the load operation.
Comments: Indirect addreSSing may not be used. Characters are specified in
storage as follows:
23
IB 17
12 II
06 05
00
o

I

2

\

!

3

/

character designators

WI
Load.lnclex

23

1817161514

00

m

a = addressing mode designator
b = index register designator
m = storage address (indexing not permitted)
Instruction Description: Load the specified index register, Bb, with the lower
15 bits of the operand stored at address m.
Comments: Indirect addreSSing may be used, but address modification (indexing)
is not possible anywhere within the indirect address. If indexing in the indirect
address is specified, it is totally ignored.

Rev.

J

5-52

Store Instructions

Operation Field
STA, I
SACH
STAQ, I
STQ, I
SQCH
STI, I
SWA, I
SCRA

40
42
45
41
43
47
44
46

STA

Interpreta tion

Address Field
m, b
r, B2
m, b
m, b
r, B1
m, b
m, b
m, b

Store
Store
Store
Store
Store
Store
Store
Store

23

A
A, character
AQ
Q
Q, character
index
15- bit word address
17- bit character address

00

18 1716 15 14

m

Store A

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Store (A) at the storage address specified by M.
(A) remain unchanged.

5-53

The

Rev. A

23

181716

00

SACH
Store A, Character

020100:
00000-77777

word address
character
designator
If b = 1, r is modified by
index register B2; R = r + (B2).
If b = 0, r is not modified (r = R).

Instruction Description: Store the contents of bits 00 through 05 of the A register in the specified character address. All of (A) and the remaining three
characters in storage remain unchanged.
Comments: Indirect addressing may not be used.
storage as follows:
23

1817

12 II

o

Characters are specified in

0605

00

2

3

"character
'\ designators
!
/

NOTE
Since the sign of Bb is extended during character address modification,
it is possible to only reference within ± 16,383
characters.
10

STAQ
Store AQ

23

18 171615 14

00

m

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Store (A) and (Q) in the storage locations specified by
address M and M+1, respectively. The (A) and (Q) remain unchanged.
Comments: Address 77776 and 77777 should be used only if it is desirable to
have M and M+1 as non- consecutive addresses, since one's complement arithmetic is used to form M+1.

Rev. A

5-54

srQ

23

00

18 17 16 15 14

m

Store Q

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Store (Q) at the storage address specified by M.
(Q) remain unchanged.
181716

23

SQCH
Store Q Character

I

The

00

43
1

1

0201001
00000-77777
~------~vr--------~

word address
character
designator
If b = 1, r is modified by
index register B 1; R = r + (B 1).
If b = 0, r is not modified. (r = R).

Instruction Description: Store the contents of bits 0 through 5 of the Q register
in the specified character address. All of (Q) and the remaining three characters in storage remain unchanged.
Comments: Indirect addressing may not be lJ,sed.
storage as follows:

Characters are specified in

1817

23

0605

12 II

I

o

\

2

00

3

/

character designators

NOTE
Since the sign of Bb is extended during character address modification,
it is possible to reference only within ± 16,383
characters.
10

5-55

Rev. A

STI
Store Index

23

~

00

18 17 16 15 14
47

a
b
m

lal

b

I

m

= addressing mode designator
= index register designator
= storage address (indexing not

permit-

ted)
Instruction Description: Store the contents of the specified index register, Bb,
in the lower 15 bits of storage address m. The upper 9 bits of m and all of
(Bb) remain unchanged.
Comments: Indirect addressing may be used, but address modification (indexing)
is not possible anywhere within the indirect address. If indexing in the indirect
address is specified, it is totally ignored.

SWA

23

00

18 17 16 15 14

m

Store Word Address

a = addressing mode designator
b = index register designator
b
m = storage address; (M = m + (B )
Instruction Description: Store the lower 15 bits of (A) in the designated address M. The upper 9 bits of M and all of (A) remain unchanged.
SCHA

23

Store
Character Address

00

1817161514

m

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Store the lower 17 bits of (A) in the address designated
by M. The upper 7 bits of M and all of (A) remain unchanged.

Rev. J

5-56

Shift and Scale Instructions
Operation Field
SSH
SHA
SHQ
SHAQ
SCAQ

10
12
12
13
13

Address Field

Interpretation

m
k,b
k,b
k,b
k,b

SSH
Storage Shift

Storage shift
Shift A
Shift Q
Shift AQ
Scale AQ

23.

18 17

r===m
m

I

00

15 14

m

0

= storage

address

Instruction Description: Sense bit 23 of the quantitlt stored at address m. If bit
23 - "Oil (positive), RNJ from P + 1; if negative ell I), RNJ from P + 2. Shift (m)
one place left, end around, and replace it in this same storage location.
Comments: Address modification may not be used.

SHA
Shift A

23

1817161514

00

k

b = index register designator
k = unmodified shift count; K = k + (Bb)
Instruction Description: (Bb) and k, with their 3igns extended, are added. If
T,he sign and magnitude of the 24-bit sum
determine the direction and magnitude of the shift. The computer senses only
bits 00-05 and 23 of the sum for this information. For left shifts, the shift
magnitude is the lower 6 bits of K ; for right shifts, the complement of the lower
6 bits of K equals the shift magnitude.

b - 0, the sign of k is still extended.

Examples:
Shift left six positions:
Shift right six positions:

K
K

00000006
77777771

Comments: During left shifts, bits reaching the upper bit position of the A
(during SHA) or Q (during SHQ) registers are carried end- around. Therefore,
a left shift of 24 places results in no change in (A) or (Q). A left shift that exceeds 24 places results in an effective shift of K-24 (or K-48) places.
During right shifts, the sign bit is extended and the bits are shifted end-off. A
right shift of 23 or more places results in (A) or (Q) becoming all "0 I S II or all
I I 1 IS' I, depending upon the original sign.

5-57

Rev. A

SHA/SHQ FLOW CHART

SHA OR SHQ
INSTRUCTION IN F

1
EXTEND THE SIGNS OF 'k'
AND (B b ) AND ADD

...-_ _ _ _"_0_'_'--I BIT 23 OF SUM

II

I

It

EQUALS"O" OR"I"

YES

~
I

~

END AROUND
ACCORDING TO
LOWER 6 BITS
OF 'K'

SHIFT (Q) LEFT
END AROUND
ACCORDI NG TO
THE

RN I

AT

5-58

P

\

SHA
IN

F?

~
)

"-----_..../

SHIFT IQ) RIGHT,

SHIFT (A) RIGHT

END OFF
ACCORDING TO

END OFF
ACCORDING TO

COMPLEMENT OF
LOWER 6 BITS
OF 'K'

COMPLEMENT OF
LOWER 6 BITS
OF 'K'

LOWER 6 BITS
OF 'K'

r

Rev. A

~
I

IN F?
)
'-----_.../

SHIFT IA) LEFT

THE

SHA

\.

+

I

k

12

Shift Q

b
k
Instruction Description:

SHAQ
Shift AQ

Shift (Q).

00

18 17 1615 14

23

SHQ

= index

= shift

register designator
count: K = k + (Bb)

Refer to SHA description.

23

00

18 17 16 15 14

k

b = index register designator
k = unmodified shift count; K

= k+(Bb)

b
Instruction Description: Shift (AQ). (B ) and k, with their signs extended, are
added. If b = 0, the sign of k is still extended. The sign and magnitude of the 24bit sum determine the direction and magnitude of the shift. The computer senses
only bits 00-05 and 23 of the sum for this information. For left shifts, the shift
magnitude is the lower 6 bits of K; for right shifts, the complement of the lower
6 bits of K equals the shift magnitude.
Examples:
Shift left three places:
Shift right three places:

K = 00000003
K = 77777774

Comments: During left shifts, bits reaching the upper bit position of the A register are carried end-around to the lowest bit position of Q. Therefore, a left
shift of 48 places results in no change in (AQ). A left shift exceeding 48 places
re sults in an effective shift of K -48 place s. During right shifts, the sign bit is
extended and the bits are shifted end-off. A right shift of 47 or more places
results in (AQ) becoming all "OIS" or all " 1 Is", depending upon the original sign.

SCAQ
Scale AQ

23

00

18 17 16 15 14

k

b = index register designator
k = scale factor
K = residue = k minus the number of shifts.
Ifb = 1,2, or 3, thenK _B b
Instruction Description: (AQ) are shifted left, end-around, until the 2 highest
order bits (46 and 47) are unequal. If (AQ) should initially equal positive or
negative zero, 4810 shifts are executed before the instruction terminates. During
scaling, the computer counts the number of shifts. A quantity K, called the residue, is equal to the scale factor 'k I minus the number of shifts made. If b = 0,
this quantity is discarded; if b = 1,2, or 3, the re sidue is transferred to the
deSignated index register.
5-59

Rev. A

Arithmetic Instructions

Operation Field

,

ADA, I
RAD, I
SBA, I
ADAQ, I
SBAQ, I
MUA, I
DVA, I
MUAQ, I
DVAQ, I
FAD, I
FSB, I
FMU, I
FDV, I

30
34
31
32
33
50
51
56
57
60
61
62
63

ADA
Add to A

Address Field

In terpreta tion

m, b
m,b
m,b
m,b
m,b
m, b
m,b
m,b
m, b
m,b
m,b
m,b
m, b

Add to A
Replace add
Subtract from A
Add to AQ
Subtract from AQ
Multiply A
Divide A
Multiply AQ
Divide AQ
FP addition to AQ
FP subtraction from AQ
FP multiplication of AQ
FP division of AQ

23

I

1817161514

30

/aI b I

00

m

a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb)
Instruction Description: Add the 24-bit operand located at address M to (A).
The sum replaces the original! A).

RAD
Replace Add

23

18 17 1615 14

00

m

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Replace the 24-bit operand at address M with the sum
of (M) and (A). The original (A) remain unchanged.

Rev. K

5-60

SBA
Subtract from A

23

00

18 17 16 15 14

m

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Subtract the 24-bit operand located at address M from
(A). The difference replaces the original (A).

ADAQ

23

00

1817161514

m

Add to AQ

a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb)
Instruction Description: Add the 48-bit operand located in addresses M and
M+1 to (AQ). The sum is displayed in AQ.
Comments: The upper 24 bits of the 48-bit operand in memory are contained
at address M.

SBAQ
Subtract from AQ

23

00

1817161514

m

a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb)
Instruction Description: Subtract the 48- bit operand located in addresses M
and M+1 from (AQ). The difference is displayed in AQ.

5-61

Rev. A

MUA

23

Multiply A

00

18 17 16 15 14

50

\al b J----m-----.

a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb)
Instruction Description: Multiply (A) by the operand located at address M.

NOTE
The 48-bit product is displayed in QA.
the lower order bits are in A.

DVA

23

The higher order bits are in Q and

00

18 17 161514

m

Divide A

a = addressing mode designator
b
index register designator
m = storage address; M = rn + (Bb)
Instruction Description: Divide the L!8- bit operand in AQ by the operand at
storage address M. The quotient is displayed in A and the remainder with sign
extended is displayed in Q. If a divide fault occurs, the operation halts and
program execution advances to the next address. The final (A) and (Q) are
meaningless if a divide fault occurs.

Rev. A

:~-62

MUAQ
Multiply AQ

23

00

18 17 161514

m

a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb)
Instruction Description: Multiply (AQ) by the 48-bit operand in addresses M
and M+1. The 96-bit product is displayed in AQE.
Comments: Refer to Figure 5-5 for operand formats.

00

DVAQ
Divide AQ

m

a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb)
Instruction Description: Divide (AQE) by the 48-bit operand in addresses M
and M+l. The quotient is displayed in AQ, and the remainder with its sign extended is displayed in E.
Comments: If a divide fault occurs, program execution advances to the next
address. The final contents of AQ and E are meaningless if a divide fault
occurs. Refer to Figure 5-5 for operand formats.
NOTE
Figure 5- 5 illustrates operand format and bit allocations for all floating
point instructions. Refer to the Floating Point section of Appendix B
for additional floating point considerations and examples.

5-63

Rev. A

~
CD

<:

~

f:r:j
t-'.

crq

,!GU:'S j HL: LOWEn 48 BIT:; r,F A
96~ BIT DIVIDEND PRIOR TO
EXECUTING A DVAQ IN$TRtlCTlO~l

~
t-j

CD

DIVIDE:
HOLDS A 48-61T REMAINDER
AFTER EXECUTING A DVAQ
INSTRUCTION

C,Jl

1-1,1

ot-j.C,Jl

;S;:O

d'U

MULTIPLY:

~CD

C,Jl

I

en
fl::>

.D~
Pl ::s
::s 0..

HOLDS THE LOWER 48 81TS OF
A PROQUCT AFTER EXECUTING
A MUAQ INSTRUCTION

---(E) REGISTER

o..f:r:j

tJo
<:t-j

~8

.D~
H

::s

Ul

UPPER 48 BITS
OFA96-BIT
OIVlOEND

Ul

Pl

::s

- - - - - - - - - - - - - 01 V I DE - - - - -

95

q-o..
~td

('J t-'.
rt-rtt-'.

[ ( A ) REGISTER

(0) REGISTER

4 B

,..---------_.

00'

I

'rl

- - - - - - 48-61T DIViSOR

47

"

{loll

r=-

o~

::s ,. . . .

Ul,.......

0
('J

Pl

rtt-'.

0

::s

Ul

48 ~ SIT MULTI PLICANO.
AFTER EXECUTING AN MUAQ INSTRUCTION
AD HOLDS THE UPPER 48 BITS OF THE

96 - BIT PRODUCT

- - - - - - - - - - MULTIPLY

48-BIT MULTIPLIER

00'
(M+1l

FAD

FP Addition to AQ

23

ao

1817161514

~----Lla-,-Ib........I___
m_---'

a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb)
Instruction Description: Add the 48-bit operand located in addresses M and
M+l to (AQ). The rounded and normalized sum is displayed in AQ.
Comments: The higher order bits of E hold the portion of the operand that was
shifted out of AQ during exponent equalization.
Refer to Figure 5- 6 for operand formats.

FSB

23

00

18 17 16 15 14

m

FP Subtraction from AQ

a = addressing mode designator
b = index register designator
IT\ = storage address; M = m + (Bb)
Instruction Description: Subtract the 48-bit floating point operand located at
storage addresses M and M+l from the floating point operand in AQ. The
rounded and normalized difference is displayed in AQ.
Comments: The upper order bits of E hold the portion of the operand that was
shifted out of AQ during the equalization of exponents. Refer to Figure 5-6 for
operand formats.

5-65

Rev. A

FMU
FP Multiplication of AQ

23

00

IBI7 161514

m

a = addressing mode designator
b
index register designator
m = storage address; M = m + (Bb)
Instruction Description: Multiply the 48-bit floating point operand in AQ by the
floating point operand located at storage addresses M and M+1. The rounded
and normalized product is displayed in AQ.
Comments:
Bits 12-47 of E hold the lower 36 bits of the 72-bit unnormalized
product. Refer to Figure 5- 6 for operand formats.

FDV
FP Division of AQ

23

00

IB 17 161514

m

a = addressing mode designator
b
index register designator
m = storage address; M = m + (Bb)
Instruction Description: Divide the floating point operand in AQ by the 48- bit
floating point operand located at storage addresses M and M+1. The rounded
and normalized quotient is displayed in AQ. The remainder with sign extended
appears in the E register.
Comments: The sign of the remainder is the same as that of the dividend.
Refer to Figure 5-6 for operand formats.

NOTE
The divisor must be properly normalized or a divide fault will result.
Refer to Interrupt conditions, Section 4.

Rev. A

5-66

THIS BIT
RECEIVES

APPLlCA'LE

47 46

24,23

I

I

,

I

I

,

I

I

....,~

o

ti

ti

0100

3635

I
I

,
,

00 23

Ii r: I 'i; :JAlREGISTER:%i: i":<::: :, <:;;:<:;~?:0[fg:f ;~;-":::C;1QfREGISTER::,:

dllltl:l

::

:l, l
:

,

,,

I

00

24 23
1
I

I
I

I

,

ZJZ2.21

~

\

36 35
1

,I {

1

aq-

}

ROUNDING
WHEN

EXPONENT
BIAS BIT

(M+

11

,
I

~"~-------------------------y------------------------~
i
11- BIT EXPONENT
'6- BIT C6:FFlClENT

I

:

I

,

I,

I

~,

3S':B1TCOEFFICIENT

11- BIT EXPONENT

(!)

~'f

00')
Pl

,

I

,

SIGN 81T (COMPARED
TO BIT 47 OF E FOR
{ ROUNDING TE5T I

SIGN BIT

rt-

""-0
Jg>o
(!)

'l:Jti
Pl

o
c.n

0'I)

.....:]

I'

FP OPERANO
t EXPONENT AND FIRST 36 COEFFICIENT
BIT RESULTS OF ALL FLOATING
POINT OPERATIONS I

1<---------------------------- F P OPERAND
FROM -----------------------------01
STORAGE

51

,...- ::s
g.o..
:»~

ti 0
,..._ti

rt-8

8~

E REGISTER

(!) !)J
rt-

,...-Pl

1-10..

I

,
,I

,,

I

I

rt-

,

23 22

~:»

EL

I
I

36 135

:47 146

~t:d
rt- ,...-

I-j

II

Eu

() ::s

24 123

12,"

I

I

,

00,

,
,
,

,,

1211

1211

00

,......

()
rt- ,......

o""-0
()

::s

!)J

Pl

rt-

,...-

0

::s

!)J

I

/4"---

SIGN EXT
FOR REMAINDER

JI..

REMAINDER FOR FOV --------------------~

MAGNITUDE BIT t COMPARED}
TO BIT 41 OF AQ FOR
ROUNDING TEST I
LOWER 36 COEFFICIENT BITS ------------~
FROM FMU OPERATION
I

I
~ MEANINGLESS-;oj
I

]0---------------- THAT

PART OF THE OPERAND SHIFTED
INTO THE E REGISTER DURING FAD OR
FSB EXPONENT EQUALIZATION

:;:0
(!)

<:

:»

I
I

RESULTS FOR

F~~Ob:iRBAT~~~S

logical Instructions

Operation Field

Address Field

XOI
XOA
XOA,S

16
16
16

y,b

XOQ
XOQ, S

16
16

y
y

ANI
ANA
ANA, S
ANQ
ANQ, S
SSA, I
SCA, I
LPA, I

17
17
17
17
17
35
36
37

Interpretation
Exclusive OR of index and y
Exclusive OR of A and y
Exclusive OR of A and y, sign of y extended
Exclusive OR of Q and y
Exclusive OR of Q and y, sign of y extended
AND of index and y
AND of A and y
AND of A and y, sign of y extended
AND of Q and y
AND of Q and y, sign of y extended
Selectively set A
Selectively complement A
Logical product A

Y
Y

y, b
Y
Y
Y

y
m,b
m, b
m, b

NOTE
The LDL(Load A, Logical) instruction may be found in the LOAD INSTRUCTIONS subsection.

The following two examples use logical instructions and illustrate the Exclusive
OR and AND functions:
(Binary Equivalents)

EXAMPLE A:
(A) = 23456701
Execute: 16 4 50321

=
=

(XOA, S)

010 011 100 101 110 111 000 001
111 111 111 101 000 011 010 001
101 100 011 000 110 100 010 000

Final (A)

=

54306420

(Q) = 23456701
Execute: 17 7 771 70

=
=

010 011 100 101 11 0 111 000 001
000 000 000 111 111 001 111 000

EXAMPLE B:

000 000 000 101 11 0 001 000 000

(ANQ)
Final (A)

I

RevK

000

5-68

5

6

1

0

0

XOI

23

00

1817161514

Exclusive OR of Bb and y

y

b

= index register designator

Instruction Description: Enter the selective complement (the Exclusive OR
function) of y and (Bb) back into the same index register.
Comments: If b = 0, this is a no-operation instruction.

XOA

~17

23

00

1514

y

Exclusive OR of A and y

Instruction Description: Enter the selective complement (the Exclusive OR
function) of y and (A) back into the A register.
XOA,5

Exclusive OR of A and y
5igl1 Exte,{ded

23

I

1817
16

00

1514
4

I

y

Instruction Description: Same as XOA except the sign of y is extended.

XOQ

Exclusive OR of Q ariel y

23

I

1817
16

1514

I I
7

00

y

Instruction Description: Enter the selective complement (the Exclusive OR
function) of y and (Q) back into the Q register.
XOQ,5

Exclusive OR of Q and y
5ign .Extended

23

I

1817
16

1514
5

I

00

y

Instruction Description: Same as XOQ except the sign of y is extended.

5-69

Rev K

I

23

SSA
Selectively Set A

00

18 17 16 15 14

m

a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb)
Instruction Descri~tion: Selectively set the bits in the A register to "l's" for
all corresponding I' s II in the quantity at address M. Initial "I' s" in A remain
unchanged.
EXAMPLE:

(A) = 23456710 = 010 011 100 101 110111 001 000
(M) = 76345242 = 111 110 011 100 101 010 100 010

Final (A) = 111 111 111 101 111 111 101 010
7
7
7
5
7
752

SCA

23

00

18 17 16 15 14

Selectively
Complement A

m

a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb)
Instruction Description: Selectively complement the bits in the A register that
correspond to the "1" bits in the quantity at address M.
EXAMPLE:

(A) = 23456710 = 010 011 100 101 110 111 001 000
(M) = 20341573 = 010 000 011 100 001 101 111 011

Final (A) = 000 all 111 001 111 010 110 011

o

,

Rev K

3

7

5-70

1

7

2

6

3

23

LPA
Logical Product A

00

1817161514

m

a = addressing mode designator
b = index register designator
b
m = storage address; M = m + (B )
Instruction Description: Replace (A) with the logical product of (A) and (M).
EXAMPLE:

(A) = 23456710 = 010 all 100 101 110 111 001 000
(M) = 45210376 = 100 101 010 001 000 all 111 110
Final (A)

= 000
a

ANI
,AND of Bb and y

001 000 001 000 all 001 000
1
a
1
031
a

23

18 1716 1514

00

y

b = index register designator
Instruction Description: Enter the logical product (the AND function) of y and
(Bb) back into the same index register.
Comments: If b = 0, this is a no-operation instruction.

ANA
. AND of A and y

23

1817

1514

Y_----',
00

L _ 1 7---I.'_6-J..'_ _

Instruction Description: Enter the logical product (the AND function) of y and
(A) back into the A register.
ANAS
AND orA and y,
Sign Extended

23
,

1817
17

I

1514
4

,

00

y

Instruction Description: Same as ANA except the sign of y is extended.

5-71

Rev K

I

23

ANQ

[

AND ofQ ond y

1817
17

1514
7

I

00

y

Instruction Description: Enter the logical product (the AND function) of y and
(Q) back into the Q register.

..,ANQ,${;,i
.. ANDofiQ~pclYi

·~;9n ~Xi~n~~W

r

23
[

1817
17

1514

I I
5

00

y

Instruction Description: Same as ANQ except the sign of y is extended.

I

RevK

5-72

Masked Searches and Compare Instructions
Opera tion Field
MEQ
MTH
CPR, I

Address Field

06
07

Interpretation

m, i
m, i
m, b

52

Masked equality search
Masked threshold search
Compare (within limits test)

I
MEQ
Masked
Equality Search

23

18 17

06

I

15 14

00

m

I

i = interval designator, 0 to 7
m = storage address
Instruction Description: (A) is compared with the logical product of (Q) and (M).
This instruction uses index register Bl exclusively. m is modified just prior
to step 3 in the test below. Instruction sequence follows:

1.
2.
3.

Decrement (Bl) by i.

(Refer to table below. )

If (Bl) changed sign from positive to negative, RNI from P + 1; if not,

Test to see if (A) = (Q) .. (M).

M = m + (Bl).

If (A) = (Q) .. (M), RNI from P+2; if not,

4.

Repeat the sequence.

Comments: i is represented by 3 bits, permitting a decrement interval selection from 1 to 8. Address modification always utilizes (Bl). Positive zero and
negative zero are recognized as equal quantities.
READ MEQ INSTRUCTION
DESIGNATOR
I

DECREMENT
INTERVAL

I
2
3

I
2
3

4
5
6
7
0

4
5
6
7
8

AT ADDRESS P

DECREMENT
(BI) BY "i"

DID SIGN OF B I

YES

CHANGE POSITIVE
TO NEGATIVE?

RNI FROM
P+I

NO

MODIFY:

M=m+(B I )

NO

YES
(A)=(Q)e(M)

RNI FROM
P+2

5-73

Rev K

MTH
Masked
Threshold Search

23

I

18 17

15 14

00

m

07

i = interval designator, 0 to 7
m = storage address
Instruction Description: (A) is compared with the logical product of (Q) and
(M). This instruction uses index register B2 exclusively. m is modified just
prior to step 3 in the test below.
Instruction Sequence:

1.
2.
3.
~.

Decrement (B2) by "i". (Refer to table below.)
If (B2) changed sign from positive to negative, RNI from P + 1; if not,
Test to see if (A) ~ (Q) • (M). M = m + (B2).
If (A) ~ (Q) • (M), RNI from P + 2; if not,
Repeat the sequence.

Comments: i is represented by 3 bits, permitting a decrement interval selection
from 1 to 8. Address modification always utilizes (B2). Positive zero and negative
zero are recognized as equal quantities.

DESIGNATOR

i

READ MTH INSTRUCTION
AT ADDRESS P

DECREMENT
INTERVAL

I

I

2
3
4
5
6
7
0

2
3
4
5
6
7
8

DECREMENT
(6 2 ) 6Y "i"

~
DID SIGN OF 6 2
CHANGE POSITIVE
TO NEGATIVE?

YES

RNI FROM
P+I

NO

MODIFY:

NO

,

Rev K

5-74

M=

m + (6 2 )

YES
(A):2:;(Q)e(M)

RNI FROM
P+ 2

CPR
Compare
(Within Limits Test)

23

00

18 17 16 15 14

m

a = addressing mode designator
b = index register designator
m = storage address; M=m+(Bb)
Instruction Description: The quantity stored at address M is tested to see if it
is within the upper limits specified by A and the lower limits specified by Q.
The testing proceeds as follows:

1.
2.
3.

Subtract (M) from (A). If (M) > (A), RNI from address P + 1; if not,
Subtract (Q) from (M). If (Q) > (M), RNI from P + 2; if not,
RNI from address P + 3.

Comments: The final state of the A and Q registers remains unchanged.
(A) must be ~ (Q) initially or the test cannot be satisfied. 77777777 is not sensed
as negative zero. The following table is a synopsis of the CPR test:

Jump Address
if Test is Satisfied

Test
Sequence
(Q)

> (A)
> (M)

(A)

~

(M)

(M)

~

P+1
P+2
P+3

(Q)

5-75

RevK

I

CPR INSTRUCTION
IN F

!
SUBTRACT (M)
FROM (A)

IS (M) >(A) ?

YES

RNI FROM
P +1

YES

RNI. FROM
P + 2

NO

SUBTRACT (0)
FROM (M)

!
IS (0) >(M)

?

NO

RNI

FROM

P+3

CPR FLOW CHART

,

Rev K

5-76

Condition Test Instructions
Operation Field
TMAV

Address Field

,

Interpreta tion
Test memory availability

77

TMAV
Test
Memory Availability

23

00

12 II

18 17

71

61

0000

Instruction Description: This instruction is used to test core storage for the
presence of a particular address.
Comments: Prior to executi¥ this instruction, the lower 15 bits of the testing
address must be formed in B. The upper 3 bits of the address will be zeros
unless the OSR has been previously selected by the (ROS) 55.4 instruction.
If a storage reply is received within 5 microseconds after executing the instruction, the address does exist, and the next instruction is read from P + 2. If a
reply does not occur within 5 microseconds, the address does not exist in the
system and the next instruction is read from P + 1. The contents of the test
address are not returned to the CPU and are of no L:onsequence during the test.

TMAV INSTRUCTION
IN F

J
SEND TEST ADDRESS
TO APPROPRIATE
STORAGE MODULE

t
RNI @P+2

YES

STORAGE REPLY
RECEIVED WITHIN
5 MICROSECONDS

NO
RNI @

P+ I

?

5-77

Rev K

Sensing Instructions
Operation Field

*

EXS
COpy
INTS
INS
CINS

Address Field

77

77
77
77

77

Interpretation

x, ch;xf=O
x, ch;x=O
x,ch
x, ch;xf=O
x, ch;x=O

Sense external status
Copy external status
Sense interrupt
Sense internal status
Copy internal status

GENERAL NOTES
Refer to the ACI instruction for special considerations regarding the 'ch' designator in these instructions. Refer to the SSIM instruction in the Interrupt group
for a method of program testing for the presence of I/O channels in a system.

EXS
Sense
External Status

23

1817

1514

12 II

00

x

ch = 1/ a channel designator, 0-7
x = external status sensing mask code
(see Comments below)
Instruction Description: When a peripheral equipment controller is connected
to an I/O channel by the CON (77. O) instruction, the EXS instruction can sense
conditions within that controller. Twelve status lines run between each controller and its 1/ a channel. Each line may monitor one condition within the
controller, and each controller has a unique set of line definitions. To sense a
specific condition, a "1" is placed in the bit position of the status sensing mask
that corresponds to the line number. When this instruction is recognized, RNI
at address P + 1 if an external status line is active when its corresponding mask
bit is "1 ". If no selected line is active, RNI at address P + 2.
Comments: Refer to the 3000 Series Computer Systems Peripheral Equipment
Codes manual (Pub. No. 60113400) for a complete list of status response codes.
COpy·

23

18 17

Copy

77

External Status

2

I

00

12 II

15 14

ch

0000

ch = I/O channel designator, 0-7
Instruction Description:

1.
2.
3.
,

Rev K

This instruction performs the following functions:

The external status code from I/O channel ch is loaded into the lower
12 bits of A. (See EXS instruction. )
The cohtents of the Interrupt Mask register are loaded into the upper
12 bits of A. (See Table 5-3.)
RNI from address P + 1.

5-78

TABLE 5-3.
Masked Bit
Positions

INTERRUPT MASK REGISTER BIT ASSIGNMENTS

Mask Codes (x)

Interrupt Conditions Represented

0001
0002
0004
0010
0020
0040
0100
0200
0400
1000
2000
4000

I/O Channel 0 (includes interrupt gener1 ated within the channel
2 and external equipment
3 interrupts)
4
5
6
7
Real-time clock
Exponent overflow /underflow & BCD faults
Arithmetic overflow & divide faults
Search/Move completion

00
01
02
03
04
05
06
07
08
09
10
11

23

INJS
Sense Interrupt

IS 17
77

1514
4

00

12 II

I ch

)(

ch = I/O channel designator, 0-7
x = interrupt sensing mask code
Instruction Description: Sense for the interrupt conditions listed in Table 5-4,
RNI from P + 1 if an interrupt line is active and the corresponding sensing mask
bit is a "I" . If none of the selected lines are active, RNI from P + 2. Bits
08-11 represent conditions that may be sensed without regard to channel designation.
TABLE 5-4.
Mask Bit
Positions
00
01
02
03
04
05
06
07
08
09
10
11

BIT ASSIGNMENTS FOR INTERRUPT SENSING CONDITIONS
Mask Codes (x)

Interrupt Conditions Represented

0001
0002
0004
0010
0020
0040
0100
0200
0400
1000
2000
4000

External equipment interrupt line 0 active
1
2
3
4
5
6
7
*Real-time clock
*Exponent overflow /underflow & BCD faults
* Arithmetic overflow & divide faults
*Search/Move completion

* Internal faults are cleared as soon as they are sensed.
5-79

RevK

.INS

2.3

18 17

Sense Internal Status

77

15 14

3

I

00

12 II

ch

I

x

ch = 1/ a channel designator, 0-7
x = internal status sensing mask code
Instruction Description: Table 5- 5 lists the bit definitions of the internal status
sensing mask. Bits 00-04 and 06-07 represent conditions within I/O channel
Bits 05 and 08-11, which represent internal faults, may be sensed without regard to channel designation.
To sense a specific condition, load a "1" into the bit position of the mask that
corresponds to the condition.
When this instruction is executed, RNI from
address P + 1 if an internal status line is active and the corresponding mask
bit is a "1". If none of the selected lines is active, RNI from address P + 2.
TABLE 5-5.
Mask Bit
Positions

INTERNAL STATUS SENSING MASK

Mask Codes (x)

Condition Represented

04
05
06

0001
0002
0004
0010
0020
0040
0100

07

0200

08

0400

09
10
11

1000
2000
4000

Parity error on channel ch
Channel ch busy reading
Channel ch busy writing
External reject active on channel ch
No-response reject active on channel ch
*Illegal write
Channel ch preset by CON or SEL, but no
reading or writing in progress
Internal I/O channel interrupt on channel
ch upon:
1) completion of read or write operation, or
2) end of record
*Exponent overflow / underflow fault (floating
point)
*Arithmetic overflow fault (adder)
*Divide fault
*BCD fault

00
01
02
03

"-

"'Internal faults are cleared as soon as the c<;mdition is sensed.

I

Rev K

5-80

CINS

23

IB 17

77

Copy Internal Status

I

15 14

3

00

12 II

ch

0000

ch = I/o channel designator, 0- 7
Instruction Description:
1.
2.

3.

This instruction performs the following functions:

The internal status code is loaded into the lower 12 bits of A. (See
INS instruction. )
The contents of the Interrupt Mask register are loaded into the upper
12 bits of A. (See Table 5- 3. )
RNI from address P + 1.

5-81

Rev K

I

Pause Instructions

Operation Field
PAUS
PRP

Address Field

Interpreta tion

x
x

77
77

Pause on condition
Priority pause
23

I

77

X

:::

00

12 II

1817

I

PAUS
Pause

60

I

x

pause sensing mask code

Instruction Description: This instruction allows the program to halt for a maximum of 40 ms if a condition (excluding typewriter - see note) defined by the
pause sensing mask exists. (See Table 5- 6.) If a "1" appears on a line that
corresponds to a mask bit that is set, the count in P will not advance. If the
advancement of P is delayed for more than 40 ms, the next instruction is read
from address P + 1. If none of the lines being sensed are active, or if they become inactive during the pause, the program immediately skips to address
P + 2. If an interrupt occurs and is enabled during a PAUS, the pause condition
is terminated, the interrupt sequence is initiated and the address of the PAUS
instruction is stored as the interrupted address.
NOTE
If either bit 08, 09 or 10 (or any combination of these bits) is set and
the sensed condition exists, a pause will not occur and the instruction at P + 1 is read up immediately. If these bit(s) are set but the
condition(s) does not exist, the program immediately skips to P + 2.
For all other bits, the normal PAUS routine is followed. TYPE
FINISH and/ or TYPE REPEAT are cleared if bit 9 and/ or 10 are set
and the sensed condition(s) does not exist.

TABLE 5- 6.
Mask Codes

Condition

Notes

00
01
02
03
04
05
06
07
08

0001
0002
0004
0010
0020
0040
0100
0200
0400

I/O channel 0 busy
1
2
3
4
5
6
7
Typewriter busy

Channel read or write operation in progress, the
External MC logic within
the channel is set, or a
Reply or Reject from a
previous operation is still
present at the channel

09

1000

10

2000

11

4000

Typewriter NOT
finish
Typewriter NOT
repeat
Search/Move control busy

Mask Bits

I

Rev K

PAUSE SENSING MASK

5-82

Typewriter input or output
in progress
Finish logic not set
Repeat logic not set
Search or Move operation
in progress

PAUS

IN

INSTRUCTION

RNI @ P+I IMMEDIATELY

F

YES
ARE ANY
10 OF

OF BITS 8.9. OR

IS A "I" ON A BUSY LINE
CORRESPONDING TO "I" OF AN Y
BIT IN THE PAUSE SENSING MASK?

YES

THE PAUSE SENSING

MASK SET TO "I"

?

NO

NO

IS A "I" ON ANY LINE. OTHER
THAN 8.9. OR 10 CORRESPONDING
TO THE PAUSE SENSING MASK?

NO

RNI @ P + 2 IMMEDIATELY

YES
YES
DO NOT ADVANCE ~
AND DO NOT RNI

HAVE ALL "I" BUSY LINES
CHANGED TO "0" ?
NO

NO
NO
HAVE 40 MS ELAPSED

?

HAS AN INTERRUPT OCCURED
AND WAS IT ENABLED?
YES

YES

P IS STORED AT ADDRESS
00004 AND INTERRUPT
ROUTINE INITIATED

RNI @ P + I

PRP
Priority Pause

23

18 17

77

00

12 II
61

x

x = pause sensing mask code
Instruction Description: This instruction performs the same operation as the
preceding PAUS (77. 6) instruction, however, the real-time clock is prevented
from incrementing during the pause.
Comments: Preventing the real-time clock from incrementing enables block
control to continue an I/O operation without being referenced by the clock.
This provides a more efficient I/O transfer operation.

5-83

Rev K

I

Interrupt Instructions

Operation Field
EINT
DINT
INCL
SSIlvI
SCIlvI
CILO
SFPF
SBCD

Address Field

Interpretation

77

Enable interrupt control
Disable interrupt control
Clear interrupt
Selectively set interrupt mask
Selectively clear interrupt mask
Channel interrupt lockout
Set floating point fault
Set BCD fault

77
77

77
77
77
77

x
x
x
cm

77
EINT
Enable
Interrupt Control

23

18 17

-

00

12 II
74

77

Instruction Description: This instruction enables the interrupt control system.
One additional instruction at P + 1 is executed before the processor is interrupted,
provided that the additional instruction requires no more than one Read Address
(RADR) cycle. If the EINT instruction is executed at P, the earlie st possible
interrupt will occur at P + 2. For an instruction containing more than one RADR
cycle, the earliest possible interrupt can occur during its second RADR cycle.
Comments: Bits 00 through 11 should be loaded with zeros.
DINT
Disable
Interrupt Control

1817

23

I

1211

00

7 3 _

77

Instruction Description: This instruction disables the interrupt control system.
The system remains disabled until an EINT instruction is executed. Selected
interrupts may still be sensed.
Comments: Bits 00 through 11 should be loaded with zeros.

INet
Clear Interrupt

23

I

18 17
77

12 II
50

00

x

x = interrupt mask register codes
Instruction Description: This instruction clears the interrupt faults defined by
the mask codes in Table 5 -7. Internal I/O channel interrupts are cleared by this
instruction and although the Interrupt Clear is sent to peripheral equipment. not
all equipments drop their interrupt lines. Refer to the Peripheral Equipment
Reference Manual, Pub. No. 60108800, for information of specific equipment.

I

Rev K

5-84

TABLE 5-7
INTERRUPT MASK REGISTER BIT ASSIGNMENTS
Mask Bit
Positions
Mask Codes (x)
Interrupt Conditions Represented
00
01
02
03
04
05
06
07
08
09
10
11

0001
0002
0004
0010
0020
0040
0100
0200
0400
1000
2000
4000

SSIM
Selectively
Set Interrupt Mask Register

I/O Channel 0 (includes interrupts gener1 ated within the channel
2 and external equipment
3 interrupts)
4
5
6
7
Real-time clock
Exponent overflow / underflow & BCD faults
Arithmetic overflow & divide faults
Search/Move completion
23

I

1817

77

I

00

12 II

52

I

x

x = interrupt mask register codes
Instruction Description: This instruction selectively sets the Interrupt Mask
register according to the interrupt mask code x.'~ For each bit set to "1" in x.
the corresponding bit position in the Interrupt Mask register is set to "1" (see
Table 5-7). Bit positions representing non-existent I/O channels cannot be set.
Comments: A program test for the existence of I/O channels for a system is
as follows:
1.

Set the interrupt mask bits to all "l"s by executing a SSIM
(77 5 27777) instruction.

2.

Execute either a COpy or CINS instruction and examine the
upper 12 bits of A.

3.

As bits representing non-existent I/O channels cannot be set, a
"0" in bits 00-07 of the Interrupt Mask register indicates a nonexistent I/O channel.

SCIM
Selectively Clear
Interrupt Mask Register

23

1817
77

00

1211
53

x

x = interrupt mask register codes
Instruction Description: This instruction selectively clears the Interrupt Mask
register according to the interrupt mask code x.'~ For each bit set to "1" in x.
the corresponding bit position in the Interrupt Mask register is set to "a" (see
Table 5 -7).
'~The

Interrupt Mask register must not be set or cleared while the interrupt system
is enabled to prevent extraneous interrupts from occuring.

5-85

Rev K

I

ClLO

Channel Interrupt Lockout

23

18 17

I

cm

12 1110090807
51

77

~

I

~

00

em

= channel mask

Bits 08 and 11 should be loaded with zeros.
Instruction Description: Disables all external interrupts on channel{s) cm while
the channel{s) are busy. Termination of the 1/ a operation clears the disabling
function.
Comments: Bit 00 corresponds to channel 0, bit 01 corresponds to channel 1, etc.
More than one channel may be set to "1" for multiple channel interrupt lockout.
The mask is cleared by termination of the I/O' operation, by clearing the channel{s),
and by a Negate Channel Interrupt Lockout signal from certain peripherals.
SFPF
Set Floating
Point Fault

23

18 17
77

12 II

00

7 1 _

Instruction Description: The floating point fault logic sets when a floating point
fault occurs. This instruction is used when the optional floating point arithmetic logic is not present in a system. An interpretive software routine should
recognize any conditions which would have caused a fault if the operation had
been executed by the optional hardware.
Comments: Bits 00 through 11 should be loaded with zeros.

SBCD
Set BCD Fault

23

1817
77

1211

00

7 2 _

Instruction Description: The BCD fault logic sets when a BCD fault occurs.
This instruction is used when the optional BCD arithmetic is not present in a
system. An interpretive software routine should recognize any condition which
would have caused a fault if the operation had been executed by the optional
hardware.
Comments: Bits 00 through 11 should be loaded with zeros.

I

Rev K

5-86

Input/Output Instructions

Operation Field

A~
~

\~

l

~
;:,

CLCA
IOCL
CON
SEL
CTI
CTO
INPC,INT,
B,B" A
INAC,INT
INPW,INT,
B,N,A
INAW,INT
OUTC,INT,
B,B

77
77
77
77
77
77
73

OTAC,INT
OUTW,INT,
B,N
OTAW,INT

75
76

73
74
74
75

76

Address Field

Interpreta tion

cm
x
x, ch
x,ch

Clear I/O channel(s)
Clear I/O channel(s) and equipment
Connect to external equipment
Select function
Set console typewriter input
Set console typewriter output

ch,r,s
ch

Character-Addressed Input to storage
Character-Addressed Input to A

ch, m, n
ch

Word-Addressed Input to storage
Word-Addressed Input to A

ch, r, s
ch

Character- Addressed Output from
storage
Character-Addressed Output from A

ch, m, n
ch

Word-Addressed Output from storage
Word-Addressed Output from A

Unlike I/O operations with A, I/O instructions with storage are buffered. As soon
as Read or Write signals are activated, Main Control relinquishes control of the
storage I/O operation and returns to the main program.
Registers 00 through 178 of the Register File are reserved for I/O operations.
Registers 00 through 07 are used for storing the modified instruction words containing the current character addresses. (Refer to Table 5-8). Registers 108
through 17 hold the modified sub-instruction words containing the last character
addresses (± 1 depending upon the instruction parameters). In cases where
addresses require modification to obtain dynamic I/O operations, care should be
exercised to provide proper readout and restoration of the modified control bits.
During the execution of word addressed storage I/O instructions, the addresses
'm' and 'n' are shifted left two bit positions. From this time on and when they
are stored in the Register File, they are recognized as character addresses.
Before executing an I/O instruction in Executive mode, the desired program state
number (0 through 7) must be loaded into the lower three bits of the A register.
The program state number is automatically transferred to the upper digit of Register File location OX for referencing during buffered I/O tasks, thus enabling the
A register to be used for other operations.
Table 5-8 and its accompanying example illustrate the relationship between the
Register File addresses, their contents, and the individual instructions. Each
I/O instruction should be referenced for a description of its particular parameters
and a flowchart of the overall operation. The ACI instruction, described elsewhere in this section, should be consulted for special I/O channel considerations.

5-87

Rev K

I

When performing I/O operations with peripheral equipment not equipped with a
12 to 6-bit disassembly feature, character oriented instructions should not be
used, thus preventing erroneous transmission parity errors.

TABLE 5-8.

Instruction

Register
Relative location
of instruction words
File
(See individual instructions) location

73 (INPC)
!=I 00

o ~
:;:jo

Hlfl

- -

-

-

- -

-

*

- - -

-

-

-

74 (INPW)

P
P+l

IX
OX

75 (OUTC)

P
P+l

IX
OX

P
P+l

IX
OX

73 (INAC)

P
P+l

IX
OX

7 - - - - - -

P
P+l

IX
OX

4

74 (INAW)
75 (OTAC)

P
P+l

IX
OX

76 (0 TAW)

P
P+l

IX
OX

- - - - - - 6 - - - - - - "i\ - - - - - - -

0''-<

[3

3

IX
OX

cd+>

Q)..c
o.+>

Contents of Register
File location

P
P+l

Q)

U]

MODIFIED I/O INSTRUCTION WORDS

76 (OUTW)

0 -

-

-

- - - - -

-,- - - - - - - .,..
1 - - - - -

:;:::

2
-,-

.-,-

- - -

- - -

- - -

-

- - -

- - -

- - - - - - -

U]

!=I

.S

cd..c

H:;::

~[3
0

X
~"'1"

= An I/O channel designator "ch" , 0,
- The program number (lowest 3 bIts

1 , 2, 3, 4, 5, 6, or 7.
of the ,A , RegIster)

-

-

- - - - - - - - - - - - -

5 - - - - - -

\

Upper digit position
(Blanks indicate
digits unaltered by
control logic)

EXAMPLE:
Execute the following INPW instruction.
P =
74 003200
P + 1 = 20 003100
P + 2 = 01 003300
ANAL YSIS:

(A)

= 00000001
3306 I/O Channel

I/O Channel 2 is specified; thus Register File location 12 is
used to store 04015000 and location 02 holds 10014400.
This instruction specifies 12- to 24-bit assembly. no interrupt
upon completion, forward storage, and an unconditional jump
to address 03300 ~s a reject instruction.

,

RevK

5-88

The first word address (m) of the block of storage assigned to
receive data from an external equipment is m = 03100.
The last word address (n) of the assigned storage area (plus
one) is n = 03200.
The first 12-bit byte is stored in bits 12 through 23 at address
003100, the second byte in bits 00 through 11, etc.

CLCA
Clear Channel Activity

23

IBI7

I

12 II 10090B07
51

77

~

2

00

~

em

cm = channel mask
Bits 08 and 11 should be loaded with zeros.
Instruction Description: Clear only the selected I/O channel(s).
Comments: The peripheral equipment associated with the selected channel(s)
are not cleared by executing this instruction. Bit 00 corresponds to channel 0,
bit 01 corresponds to channel 1, etc. More than one channel may be set to "1'1
for multiple channel clearing.

tocL

23

IB 17

Clear I/O, Typewriter,
and Search/Move

77

x

= block

12 II
51

00

x

control clearing mask

Instruction Description: This instruction may be used to clear the I/O channels.
It also clears all associated peripheral equipment, the typewriter or the Search/
Move control according to bits set in the Block Control clearing mask. (See
Table 5-9.)

5-89

Rev K

I

TABLE 5-9.
Mask Bits
00
01
02
03
04
05
06
07
08
09
10
11

BLOCK CONTROL CLEARING MASK
Mask Codes (x)

Controls Cleared
I/O channel 0
1
2
3
4
5
6
7
Typewriter
(see note)
(see note)
Search/Move

0001
0002
0004
0010
0020
0040
0100
0200
0400
1000
2000
4000
NOTE

If bits 09 and 10 are both set or both clear, the channel(s) specified by
bits 00 through 07 of the mask are cleared, i. e., Read or Write, Status,
and Channel Interrupt are cleared. A 5.5 usec Clear signal is also
sent to the peripheral equipment and controllers connected to the selected
channel{s).
If bit 09 is clear and bit lOis set, the instruction will clear the
channel(s) only and the 5.5 usec Clear signal is not transmitted. Bit
08 clears the typewriter as well as the Type Load or Type Dump logic
in Block Control.
23

18 17
77

15 14
0

I ch

12 II

00

x

ch = I/O channel designator, 0-7
x = 12 bit connect code. Bits 09-11
select one of eight controllers which
may be attached to channel ch. Bits
00-08 select the peripheral units
connected to the controller.
Instruction Description: This instruction sends a 12-bit connect code along with
a connect enable to an external equipment controller on I/O channel ch. If a
Reply is received from the controller within 100 usec, the next instruction is
read from address P + 2. If a Reject is received or there is no response within
100 usec, a reject instruction is read from address P + 1. If the I/O channel is
busy, a reject instruction is read from address P + 1.

I

Rev K

5 .. 90

Hefluest

(PI -. I:
(1,'(':\

Program Priority
In Block Control

neg. )

~

.....

Await Program

()'q
~

'"'$
C1l

CJl
1

m

CJl
1

CD
I-'

-:J
-:J

0

aJ:j
J:j

C1l

EquIpment \fulllbel'

Switch = E,
Unit Switch

= T!

'1

()

<+

0

"d

1\0

Yes

C1l
'"'$

III

.....

<+

a

J:j

No Response

Equipment
Disconnects

Channel Generate
~ Internal Reject

100 Usec Delay

::D
C1l

0

Byte To r

H = I

(1)

I-j

Pl

M-

1-'-

0

:::s

::g

B = 1

H

=0

1-'-

M-

cY

Decrement
~rbyl

(f}
M-

0
I-j

Pl

(J'q
(1)

(O-7)

H = 1

INPW
Word-Addressed
Input to Storage

23
74

I

lo~

n

ch

B
ch
INT
N
N
m

~IBH~~

I
00

2120191817161514

23

P+1

00

1817 16 15 14

P

m

= "1" for backward storage
= 1/
channel designator, 0-7
= "1" for interrupt upon completion

a

= "0" for 12- to 24-bit assembly
= "1" for no assembly
= first word address of I/O data block;

becomes current address as 1/ a
operation progresses
n = last word address of input data block,
plus one (minus one, for backward
storage)
A = "1" for word count control
Bits 15 and 16 at P and P + 1 should be
loaded with zeros.

Instruction Description: This instruction transfers a word-addressed data block
from an external equipment to storage. Transferring 12-bit bytes or 24-bit
words depends upon the type of I/O channel used. The 3306 utilizes 12-bit bytes
and the 3307 uses 24-bit words.
During forward storage and 12- to 24-bit assembly, the first byte of a block of
data is stored in the upper half of the memory location specified by the storage
address. Conversely, during backward storage, the first byte is stored in the
lower half of the memory location.
If channel 'ch' is not busy, the buffered I/O operation with storage commences
while Main Control performs an RNI at P + 3. Main Control continues executing the
main program while the I/O operation occurs Simultaneously. If channel 'ch' is
initially busy, Main Control performs an RNI at P + 2 and the I/O operation does
not occur.

NOTES
When bit 20 of the subinstruction word at P + 1 is "1 ", the word count
control feature allows this I/O operation to continue beyond an End-ofRecord signal. In practice, when an End-of-Record signal is sent, the
Read line drops but the buffer operation does not terminate. The Read
signal sent to the external equipment then reappears until the word
count is satisfied. This signal appears as a new input instruction to the
external equipment, but as a continue Read to the 1/ a channel.
If N = 1 and a 3306 is used, the upper 12 bits of each storage word will
be unchanged. If N = 1 and a 3307 is used with a 12-bit device, the upper
12 bits will be zeros.

5-97

Rev K

I

~
('[)

<:

-

~
Activate Read
On 1/0
Channel 0-7

Then S Bus Priority

I:rj

,....

crq

s::
'"'!

Await
Priority

1/0 Channel

Store 21 (P)
in One Register

Generates
Block Control
Request

(10-17)

('[)
(.)1

I

CD

x

=

I/o

Channel CH (0-7)

-.J

>J:>.

(.)1

I

CD
CO

H

---0

Increment
m by 2

OX

0

'"d

('[)

N = 1

'"'!
III

r+,....

0

::l
~
,....
r+-

B=1

::>'

Decrement

(/).

m by 2

r+-

0
'"'!
III

crq

Restore

~-""'--'~'" Register

N = 1

('[)

Decrement
m by 4

N=O
3307

"See text for differences between 3306 and 3307.

Request

MCS

(~1t~,:[er
S Bus

OUTC

181716

23

Character-Addressed
Output from Storage

P

75
23

.~.----

P+1

IaI

212019181716

ch

00
S

I
00

~BH~I

B = "1" for backward storage
ch = I/O channel designator, 0-7
H = "0" for 24- to 6-bit disassembly
H = "1" for 24- to 12-bit disassembly
INT = "1" for interrupt upon completion
r = first character address of 1/ a data
block; becomes current address as
I/O operation progresses
s = last character address of output data
block, plus one (minus one, for back- '
ward output)
Bit 20 at P + 1 should be loaded with a "0"
Instruction Description: This instruction transfers a character-addressed block
of data, consisting of 6- bit characters or 12- bit bytes, from storage to an external equipment. During 24- to 6-bit disassembly (H = 0), the first character is
transferred from character address r. The next character is transferred from
(r + 1) if forward storage (B = 0), from (r - 1) if backward storage (B = 1). During 24- to 12- bit disassembly (H = 1), the first byte will be transferred from the
upper or lower half of the storage word, depending upon character address r. If
B = 0, the next byte is transferred from (r + 2); if B = 1, the next byte is transferred from (r - 2).
If channel 'ch' is not busy, the buffered I/O operation with storage commences
while Main Control performs an RNI at P + 3. Main Control continues executing
the main program while the I/O operation occurs simultaneously. If channel 'chi
is initially busy, Main Control performs an RNI at P + 2 and the I/O operation
does not occur.

NOTE
If H = "1", an even character count tnust be used.
the last character will be lost.

5-99

If the count is odd,

Rev K

I

~
C1l

<:

-

~

(P) -

Request

F

Read

Block
Control

(FCN Reg)

Wait For Block Control
Then S Bus Priority

I'l:j

,.....

Activate
Write On I/O
Channel 0-7

(P+l)

Store ZI (P+l)
In One Register
(00-07)

f:~zl

Yes

0"Cl
~
I-j

C1l
CJl
I
f-'

0

Store Zl (P)
in One Register
(10 - 17)

Release

RNI

Block Control
and Scanner

From
P+3

-J
CJl

f-'

-

0
0

'"d

CJl

H

Await
r:1-:-::--=---=--CPriOrity
-,~ ~,
Read Up
Register

=0

OX
B =0

1--1

0
0

X = I/O Channel Ch (0-7)

C1l
I-j

III

,.....

ri-

0

::s
::il
,.....
ri-

::r
U1
ri-

O

I-j

III
0"Cl
C1l

B = 1

Decrement
r by 2

OUTW
Word-Addressed
Output from Storage

P

L;6
23

P+1

00

1817161514

23

lo~

n
00

2120191817161514

Ich~BH~~

m

B = "1" for backward storage
ch = I/O channel designator, 0-7
INT = "1" for interrupt upon completion
m = first word address of I/O data block;
becomes current address as 1/ a
operation progresses
N = "0" for 24- to 12-bit disassembly
N = "1" for straight 12- or 24-bit data
transfer
n = last word address of output data block,
plus one (minus one, for backward
output)
Bits 15 and 16 at P and bits 15 .. 16,and 20 of
P + 1 should be loaded with zeros.
Instruction Description: This instruction transfers a word-addressed block of
data consisting of 12-bit bytes or 24-bit words from storage to an external
equipment.
With no disassembly, 12 or 24- bit transfer capability depends upon whether a
3306 or 3307 I/O channel is used. If an attempt is made to send a 24-bit word
over a 3306 I/O channel, the upper byte will be lost.
If channel 'ch' is not busy, the buffered I/O operation with storage commences
while Main Control performs an RNI at P + 3. Main Control continues executing
the main program while the I/O operation occurs simultaneously. If channel 'ch'
is initially busy, Main Control performs an RNI at P + 2 and the I/O operation
does not occur.

5-101

Rev K

I

:;0
(1)

<:

-

~

Start

Request

(P) -F
(FCN Reg)

Block
Control

\1

l\ctivate

Read

Wait For Block Control
Then S Bus Priority

Store ZI (P+l)
In One Register

Write On I/O
Channel 0-7

(P+l)

(00-07)

Yes

I"lj

,..,-

3306
N • 0

(J'q

~

"i
(1)

CJ1
I

0-----j
1

Store ZI (P)
In One Register
(10-17)

.

f-L
f-L

-.;J

en

CJ1
I
f-L

0
N

H

0
0

'"d
(1)

"i
III

ri,..,-

0

:=i

N'1

~
,..,ri-

P"'
INT

UJ
ri-

O
"i

III

(J'q
(1)

'~See

text for differences between 3306 and 3307.

=1

(~).':~1

INAC

23

181716

Input

00

_IL......IoI:I~~"""""'~~~

p

C,7_3

Character to A

23

21 20

18 17 16

00

p+1~lol~~
ch = 1/ a channel designator, 0-7
"1" for interrupt upon completion
INT
Bits 00 through 16 at P and P + 1 should be loaded
with zeros.
Instruction Description: This instruction transfers a 6-bit character from an
external equipment into the lower 6 bits of the A register. (A) are cleared prior
to loading, and the upper 18 bits remain cleared. When the I/O operation with A
is completed, RNI at P + 3. If channel Ichl is busy and the operation cannot be
performed, RNI at P + 2.

(P) - F
(FCN Reg)

Activate Read
On I/O
Channel 0-7

Request

Block
Control

Wait For Block Control
Then S Bus Priority

Release Block
Control and
Scanner

Store ZI(P+1)
In One Register
(00-07)

Await
Reply

t:;\

INT = 1

/,--

r

~

I/O Channel
Generates
Data Signal

Reply From
Controller

Terminate
Input

x

= I/O Channel Ch (0-7)

Figure 5-12.

I

73 I/O Operation with A

5-103

Rev K

INAW
Input

Word

23

p

to A

I

1 -

21 20

I 1
ch

00

,

74

23

P+ 1

181716

0

1817 16

00

I~_

ch = I/O channel designator, 0-7
INT = "1 II for interrupt upon completion
Bits 00 through 16 at P and P + 1 should be loaded
with zeros.
Instruction Description: This instruction transfers a 12- bit byte into the lower
12 bits of A or a 24-bit word into all of A from an external equipment. Transferring 12 or 24 bits depends upon whether a 3306 or 3307 I/O channel is used.
(A) is cleared prior to loading and, in the case of a 12- bit input, the upper 12
bits remain cleared. When the I/O operation with A is completed, RNI at P + 3.
If channel I chi is busy and the operation cannot be performed, RNI at P + 2.
NOTE
Bits 18, 19, and 20 may be all "0' s" when a 3306 Data
Channel is used. However, when bit 18 = "1", bit 19 = "0"
or "1", and bit 2 0 = "0", this instruction can be used with
either a 3306 or ;;307 (when the 12- to 24-bit assembly feature
is not utilized). This eliminates the need to alter a program
when a 3307 is selected in place of a 3306 or vice versa.
If the assembly feature of the 3307 is utilized, bits 18, 19,

and 20 take on the following significance:
• For 12- to 24-bit forward assembly, bits 18, 19, and 20 = 0
• For 12- to 24-bit backward assembly, bits 18, 19, and 20 = 2

I

Rev K

5-104

(P)-F

(FCN Reg)

Load

Request
Block
Control

(P + 1)-1'0
(P)

-z

Wait For Block Control
Then S BUB Priority

Activate Read!

Write On I/O
Channel 0-7

Store ZO (P + 1)
In One Register
(00- 07)

Release Block
Control And
Scanner

Await
Priority

/,---,
Read Up
Registers
OX& IX

X - I/O Channel Ch (0 - 7)

Figure 5-13.

I

74 I/O Operation with A

5-105

Rev K

OTAC
Output
Character from A

23

181716

00

P
23

P+1

I

2120

ch

181716

0

00

I~-

ch = I/O channel designator, 0-7
INT "I" for interrupt upon completion
Bits 00 through 16 at P and P + 1 should be loaded
with zeros.
Instruction Description: This instruction transfers a character from the lower
6 bits of A to an external equipment. The original (A) are retained. When the
I/O operation with A is completed, RNI at P + 3. If channel 'chI is busy and the
operation cannot be performed, RNI at P + 2.

(P)- F

(FCN Reg.)

Request

Read
(P+l)

Block
Control

Yes

Wait for Block Control
Then S Bus Priority

Activate Read/
Write on I/O
Channel 0 - 7

Store zO (P + 1)
in One Register
(00 - 07)

Store Zl (P)
in One Register
(10-17)

x

I

Figure 5-14.

Rev K

RNI at
P +2
(Reject)

Release Block
Control and
Scanner

= I/O Channel Ch (0-7)

75 I/O Operation with A

5-106

I/O Channel
Generates
Block Control
Request

orAW
Output
Word from A

23

P
23

161716

00

161716

00

7611~
2120

p+1EIOI~~

ch = I/O channel designator, 0-7
INT = "1" for interrupt upon completion
Bits 00 through 16 at P and P + 1 should be loaded
with zeros.
Instruction Description: This instruction transfers the lower 12 bits of A or
(A) to an external equipment, depending upon the type of I/ a channel (3306 or
3307) that is used. The original (A) remain unchanged. When the I/O operation
with A is completed, RNI at P + 3. If channel 'ch' is busy and the operation
cannot be performed, RNI at P + 2.

NOTE
Bits 18, 19, and 20 may be all "0' s" when a 3306 Data
Channel is used. However, when bit 18 = "1", bit 19 = "0"
or "I", and bit 20 = "0", this instruction can be used with
either a 3306 or 3307 (when the 24- to 12- bit disassembly
feature is not utilized). This eliminates the need to alter
a program when a 3307 is selected in place of a 3306, or
vice versa.
If the disassembly feature of the 3307 is utilized, bits 18,

19, and 20 take on the following significance:
• For 24- to 12-bit forward disassembly, bits 18, 19, and 20 = 2
• For 24- to 12-bit backward disassembly, bits 18, 19, and 20 = 0

5-107

Rev K

I

Request

(P) -F
(FCN REG)

Load

(p+ 1)

Block
Control

Yes

Wait For Block Control
Then S Bus Priority

Activate Read/
Write on I/O
Channel 0 -7

x = I/O

I

Store zO (P+ I)
In One Register
(00 - 07)

R~lease

Block
Control And
Scanner

Channel CH (0-7)

Figure 5-15.

Rev K

HNI I!!'
P +2
(Reject)

Store Zl (P)
In One Register
(10-17)

76

Ilo

5-108

0

(P + 1)-Z
(p)_ZI

Read

Operation with A

Relocation Control Instructions

Operation Field
RIS
ROS
SBJP

Address Field

Interpreta tion
ReloGate with (ISR)
Relocate with (OSR)
Set boundary jump

55
55
77

RIS
Relocate
with Instruction State

23

C""55

18 17

1

15 14
0

00

_

Bits 00 through 14 should be loaded with zeros.
Instruction DescriRtion: Clear bit 02 of the Condition:t'egister, enabling (ISR) to
be used as the upper 3 bits of address for all storage references during Program
State.
Comments: A Master Clear produces the same effect as this instruction.
ROS
Relocate with
Operand State

23

IB 17

15 14

00

5 5 \ 4 _

Bits 00 through 1_4 should be loaded with ~eros. __
Instruction DescriRtion: Set bit 02 of the Conditi0n:t'egister, enabling (OSR) to
be used as the upper 3 bits of address for all operand references in Executive
mode.

,

,

Comments: Refer to Interrupts During Executive Mode in Section 4 for
additional information.
SBJP
Set
Boundary Jump.

Instruction Description:
tion register).

23

I

IB 17
77

12 II
62

00
0000

Set a boundary jump condition flag (bit 00 of the condi-

Comments: When the next jump instruction is executed, the boundary jump
condition flag is cleared and the processor enters Program State. The (ISR) are
appended to the jump address (m) for the RNI that follows. The (ISR) are used
for both the STO and the RNI if the jump instruction is an RTJ (00.7).
If the computer is interrupted, the condition is cleared as the CRA instruction

used in interrupt processing is executed.

5-109

Rev K

Multiprocessing Control Instructions

Opera tion Fie ld
IAPR
SDL

Address Field

Interpreta tion

77
77

IAPR
Interrupt
Associated Processor

Interrupt associated processor
Set destructive Load condition
23

II

18 17

77

57_
12 II

00

Bits 00 through 11 should be loaded with zeros.
Instruction Description: The processor (computer) eXecuting this instruction
sends an interrupt to an associated processor via a special cable. The interrupt remains active in the receiving computer until it is recognized.
SDL
Set
Destructive Load

23

I

18 17
77

12 II
62

09 08
4

I

00
000

Instruction Description: Set the destructive load condition flag (bit 01 of the CR).
Comments: After this instruction is executed, the next Load A (LDA) instruction senses the flag and causes the following operations to occur:

1.

Load (M) from LDA instruction into A and restore 77777777 into
(M).

2.

Clear the destructive load condition flag when executing the LDA
instruction.

Refer to 'Interrupts During Executive Mode' in Section 4 for additional information.
This instruction is useful in controlling multiple CPU's during multi-processing
instructions.

,

Rev K

5-110

Character Search Instructions
Operation Field
SRCE,INT
SRCN,INT

Address Field

71
71

SRCE
Search for
Character Equality

Interpreta tion

SC, r, s
SC, r, s

Search for character equality
Search for character inequality

23

P

I

P+1

[

00

181716
71

23

I~ I

5

18 17 16

sc

I

0

1 1

I
00

I

INT = "1" for interrupt upon completion
s = last character address of the
search block, plus one
SC = 6-bit BCD scan character
r = first (current) character address
of the search block
Instruction Description: This instruction initiates a search through a block of
character addresses in storHge looking for equality with the scan character, SC.
If Search/Move control is not busy, the buffered search operation commences
while Main Control performs an RNI at P + 3. Main Control continues executing
the main program while the search operation occurs simultaneously. If Search/
Move control is initially busy, Main Control performs an RNI at P + 2 and the
search operation does not occur.
As a search progresses, r is incremented until the search terminates when either
a comparison occurs between the scan character 'SCI and a character in the
storage field, or until r=s. If a comparison does occur, the address of the satisfying character may be determined by inspecting r. To do this, transfer the contents of register 20 to A with instruction TMA (53 0 20020).
Register 20 of the register file is reserved for the second instruction word which
contains the current character address of the search block. Register 30 is reserved for the first instruction word which contains the last character address
of the search block, plus one.
Figure 5 -15 is a flow chart of steps that occur during a search operation.
Comments:
Before executing this instruction in Executive mode, the desired program state
number (O through 7) must be loaded into the lower three bits of the A register.
This number is then automatically transferred to the upper 3 bits of Register
File location 2X for referencing during the buffered operation. The OSR is not
used.

5-111

Rev K

I

I

-;:d
('I)

<

;;;:
Load (p + 1)
into Data Bus
Register (VBR)

Transfer (F)
fa Register 30

Rl'lC'asp Data

Bus; Ri':l at

P +::i

~

.....

aq
~

Ii
('I)

CJ1

Search Control
Gene ra te 5 Block
Control Request

Read Up
Register 20
(P + 1)

I

,...,.
CJ1

m

I
,...,.

,...,.
N

UJ.

;:d

n

trJ

~
('I)

Ii

Pl

<"i.....

o
:::1

Load Search
Character se
into DBR

No

SRCN
Search for
Character Inequality

23

00

1817 16

P

71

23

I~ I
III

5

00

181716

P+1

sc

INT = "I" for interrupt upon completion
s = last character address of the
search block, plus one
SC = 6-bit BCD scan character
r = first (current) character address
of the search block
Instruction De scription: This instruction initiate s a search through a block of
character addre sse s in storage looking for inequality with scan character SC.
If Search/ Move control is not busy the buffered search operation occurs
simultaneously. If Search/ Move control is initially busy Main Control performs
an RNI at P + 2 and the search operation does not occur.
J

J

As a search progresses, r is incremented until the search terminates when
either an unequal character comparison occurs between the search character SC
and a character in storage, or until r = s. If an unequal character comparison
does occur, the address of the satisfying 'character may be determined by inspecting r. To do this, transfer the contents of register 20 to A with instruction TMA (53 0 20020).
Register 20 of the register file is reserved for the second instruction word
which contains the current character address of the search block. Register 30
is reserved for the first instruction word which contains the last character address, plus one of the search block.
Figure 5-16 is a flow chart of steps that occur during a search operation.
Comments:
Before executing this instruction in Executive mode, the desired program
state number (0 through 7) must be loaded into the lower three bits of the
A register. This number is then automatically transferred to the upper 3
bits of Register File location 2X for referencing during the buffered operation.

5-113

RevK

I

~

-

CD

<:

~
Await

Load (P + 1)
into Data Bus
Register (lJBR)

Transfer (F)
To Register :W

Rl'lpusp Data
Bus; H:-:I at

P + ::i

I-J:j

,...-

()'q

~
t-j

CD
CJ1
I

CJ1
I
I--'
I--'
..,..

.....

Search Control
Read Up
Generates Blockr----1J----., Register 20
(P + 1)
Control Request

-J
•

Ul
~

n

z
o
'd
CD

t-j

p:l

<+
,...-

o
i::l

Load Search
Character SC
into DBR

:-/0

MOVE INSTRUCTION
Operation Field
MOVE, INT 72

Interpretation

Address Field

23

MOVE
MoveS
Characters from r to s

--

Move characters from r to s

S, r, s

00

IB 17 16

P

72

23

I~ I

I

5

00

17 16

S

P+1

INT
s

= "1" for interrupt upon completion
= first addre ss of character block
destination

S = field length of data block, 0-177 8 ':'
r

characters
addre ss of character block
source

= first

Instruction Description: This instruction moves a block of characters from one
are"a of storage to another. If Search/Move control is not busy, the buffered move
operation commences while Main Control performs an RNI at P + 3. Main
Control continues executing the main program while the move operation occurs
simultaneously. If Search/Move control is initially busy, Main Control performs
an RNI at P + 2 and the move operation does not occur.
As a move operation progresses, rand s are incremented and S (number of
characters) is decremented until S = O. 128 characters or 32 words may be
moved. When bits 00 and 01 of rand s are zero, and the field length is a multiple
of four characters, data is moved word by word. This reduces the move time by
75o/c over a character by character move.
Register 21 of the Register File is reserved for the second instruction word
which contains the first address of the character block source. Register 31 is
reserved for the first instruction word which contains the first address of the
character block destination.
Figure 5-17 is a flow chart of steps that occur during a move operation.
Comments:
Before executing this instruction in Executive mode, the desired program
state number (0 through 7) must be loaded into the lower three bits of the
A register. This number is then automatically transferred to the upper 3
bits of Register File location 2X for referencing during the buffered operation.

*=

1- 177 8 represents a field length of 1 to 127 characters; 0 represents a field
length of 128 characters.
5-115

RevK

~
ct>

<:

~

":tj
1-',

~
'1

ct>

C)1

I

C)1

I

.....
.....
0')

.....

.

00

~
0
<:
ct>

S'
r:n
M-

'1

~
(J
M-

I-'.

0
i:::!

Business Data Processing Instructions
Two somewhat different sets of BDP instructions are available in 3300 systems.
The 3312 optional Business Data Processing Unit and 3304-2 Business Data
Processor execute the same instruction set. The 3304-2 Business Data Processor
executes the second instruction set. The main differences between the two instruction sets are:
1.

The 3312 and 3304-2 have instructions for BCD to ASCII conversion (66.2)
and ASCII to BCD conversion. These instructions are not available in
the 3504-3.

2.

The Compare instructions (67.3) are quite different in the two BDP's.

3.

There are minor differences in several other instructions.

The following table lists all of the BDP instructions and indicates where differences
exist between the two instruction sets.
Table 5-10. BDP INSTRUCTION SET
Operation Field

Address Field

Interpretation

MVE

64.0

MVE, dc

64.0

r, B r , Sl' s, Bs' S2
r,B r ,s,B s ,S2

MVBF

64.1

r, B r , Sl' s, Bs' S2

Move field A to field C and
blank fill

MVZF

64.2

r, B r , Sl' s, Bs' S2

Move field A to field C and
zero fill

MVZS

64.3

r, B r , Sl' s, Bs' S2

Move field A to field C and
suppress zeros

MVZS, dc

64.3

r, B r , s, Bs' S2

Move field A to field C and
suppress zeros with
delimiting

ZADM':":":'

67.2

r, B r , Sl' s, Bs' S2

Move field A to field C and
add zeros

FRMT

64.4

r, B r , Sl' s, Bs' S2

Move field A to field C and
format with commas and
decimal point

EDIT

64.4

r, B r , Sl' s, Bs' S2

Move field A to field C and
perform complete COBOL
edit

SCAN, LR, EQ

65.0

r, B r , S2' sc

Scan field (left to right) for
equal condition

Move field A to field C
Move field A to field C with
delimiting

':'3312/3304-2 Only
':":'3304-3 Only
':":":'Minor differences between 3312/3304-2 and 3304-3.
descriptions.
5-117

See instruction

Rev K

Table 5-10. BDP INSTRUCTION SET (Cont'd)
Address Field

Operation Field

Interpretation

SCAN, LR, EQ, de

65.0

r, B r , S2' sc

Scan field (left to right) for
equal condition with delimiting

SCAN, LR, NE

65.2

r, B r , S'2' sc

Scan field (left to right) for
unequal condition

SCAN, LR, NE, de

65.2

r, B r , S'2' sc

Scan field (left to right) for
unequal condition with
delimiting

SCAN, RL, EQ

65.1

r, B r , S2' sc

Scan field (right to left) for
equal condition

SCAN, RL, EQ, de

65.1

r, B r , S2' sc

Scan field (right to left) for
equal condition with delimiting

SCAN,RL, NE

65.3

r, B r , S2' sc

Scan field (right to left) for
unequal condition

SCAN, RL, NE, de

65.3

r, B r ,

~;2'

CVDB

66.0

r,Br ,

~;l,m,Bm

Convert BCD field to binary
field

CVBD

66.1

m, B

, n, B

Convert binary field to BCD
field

DTA':'

66.2

r, B r , 4;. 2' m, B m

Convert BCD field to ASCII
field

DTA, de':'

66.2

r,B , S2,M,B
r
m

Convert BCD field to ASCII
delimiting

ATD':'

66.3

m, Bm' S2' s, Bs

Convert ASCII field to BCD
field

ATD, de':'

66.3

m, B m , S2' s, B s

Convert ASCII field to BCD,
delimiting

PAK

66.4

r,B r , S2,m,B m

Convert 6-bit BCD to 4-bit
BCD

UPAK

66.5

m, Bm' s, Bs' S2

Convert 4-bit BCD to 6-bit
BCD

ADM':":":'

67.0

Add field A to field C

SBM':":":'

67.1

r, B r , Sl' s, Bs' S2
r, B r , Sl' s, Bs' S2

CMP':'

67.3

Compare field A to field C

CMP, de':'

67.3

r,B r , Sl,s,B s ' S2
r,B ,s,B , Sl
r
s

CMP':":'

67.3

r, B r , Sl' s, Bs' S2

Collating compare of field A
with field C

m

sc

n

Scan field (right to left) for unequal condition with delimiting

Subtract field A from field C
Compare field A to field C
delimiting

':'3312/3304-2 Only
':":'3304-3 Only
':":":'Minor differences between 3312/3304-2 and 3304-3.
descriptions.
Rev K

5-118

See instruction

Table 5-10.

BDP INSTRUCTION SET (Cont'd)

Operation Field

Address Field

Interpretation

CMP, n':":'

67.3

r,B r , Sl,s,B s ' S2

Numeric compare of field A
with field C

TST

67.4

r, B r , Sl

Test field A for sign

TSTN
LBR::::::::::::::::::

67.4

Test field A for numeric

70.6

r, B r , Sl
m

SBR

70.7

m

Store BDP

Load BDP

';'3312/3304-2 Only
':":'3304-3 Only
':":":'Minor differences between 3312/3304-2 and 3304-3.
descriptions.

See instruction

NOTE
All instructions in this group (except LBR and SBR)
are unconditionally trapped when the BDP MODE switch
is OFF or the optional BDP is not present. LBR and
SBR are also trapped if the switch is OFF during NonExecutive mode or Program state of Executive mode.
However, during Monitor state, they are No-Ops.
Whenever one of the 64 - 70 instructions is read from memory during execution
of a program, the Main Control section signals the BDP section of the Central
Processor to assume control for the instruction. Main Control performs all
required index and memory operations. Generally, the BDP instructions involve
operations with variable length data fields and certain guidelines should be
followed while programming.
In those instructions using two variable length data fields, care must be taken in
assigning these fields to memory so that overlapping of processed data of the
result field over unprocessed data of the source field does not occur. If overlapping occurs the results will be unpredictable.
Interrupts During BDP Instructions
Interrupts are recognized near the end of the first RNI of all instructions. However, after the first RNI of BDP instructions, Main Control continually tests for
active interrupt conditions. If a selected interrupt (or Abnormal interrupt) condition becomes active, an Interrupt Stop signal is sent to the BDP section. The
BDP relinquishes control after the current character operation is completed. The
interrupt is actually recognized as Main Control rereads the instruction at P, or
at the address of the next instruction if the current instruction was completed.

5-119

Rev K

The BDP records interrupt recovery conditions (refer to the LBR instruction),
and transfers operating information to the B3 register. If recovery from
interrupts is desired, the interrupt routine used must contain a SBR instruction
to store the recorded interrupt recovery conditions, and a LBR instruction to
return the recovery conditions to the BDP once the interrupt processing is
completed. These conditions normally enable a restart to be made from the
point of interrupt. Exceptions to the recovery start are: the 66.0 and 66. 1
instructions always restart from the beginning if interrupted, and if the interrupt
is because of an Illegal Write, the instructions 66.4 and 66.5 also restart from
the beginning.
The B3 index register has the following significance when a BDP instruction is
interrupted:
Bits 00 - 11, record the count of the Field C characters processed prior
to interrupt.
Bit 12 = "1", if a second pass was in progress.
Bit 13 = "1 ", if an arithmetic carry was generated on an ADM or SBM instruction during the iteration preceeding interrupt. This is an internal status
bit used to enable interrupt recovery and does not indicate an Arithmetic
Overflow at instruction completion.
Bit 14 = "1", if a BCD fault occurred.
BDP Condition Register
The BDP Condition register (BCR) is a 2-bit register that is set to indicate conditions existing directly after a business data processing instruction has been
executed. The BCR is cleared upon execution of the next BDP instruction. The
(BCR) can be sampled to condition jumps to address 'm' by the three jump instructions: JMP, ZRO: JMP, HI: JMP, LOW. Refer to the Jump Instructions
group earlier in Section 5 for these instructions and the BCR codes.
Numeric Fields
Six-bit numeric BCD characters consist of a numeric portion (lower 4-bits) and
a zone portion (upper 2 bits), the latter of which specifies sign for the character.
When considering variable-length numeric fields, the convention followed is to
designate the field sign with the sign of the lowest order (right-most) character
in the field. This lowest order character is hereafter referred to as the sign
character. The zone bits for all other characters in the field must equal zero.
The sign of fields in packed BCD (4-bit) is specified by two special 4-bit sign
cha7',:"cters (1010 - positive, and 1011 - negative) in the lowest order character
2
2
pOSItIon.
The Significance of zone bits and the numeric portion of 6-bit BCD characters
are shown below:
Relative Bit Positions
6
5

Sign of BCD
Field

+
+
-

+
Rev K

5-120

0

0

0
1
1

1
0
1

NUMERIC BCD CODES (Lower 4 Bits)
Decimal
Number
4

EXAMPLE:

BCD Character Relative Bit
Positions
1
2
3

0

0

0

0

0

1

0

0

0

1

2

0

0

1

0

3

0

0

1

1

4

0

1

0

0

5

0

1

0

1

6

0

1

1

0

7

0

1

1

1

8

1

0

0

0

9

1

0

0

1

Following is an example illustrating execution of a MVZF
(64.2, D = 0)':' instruction:
P
64000202
P + 1 = 27003000
P + 2 = 00140017

Analysis:

(B~) = 00200
(B ) = 01000

1.

The unmodified character address 'r' is 00202.

2.

Br = 3, requiring (Bl) be added to r. If (Bl) = 00200 then
R = 00402 which equals word address 00100 character
position 2. This is the true address of the highest order
character in field A.

3.

Bs = 2, requiring (B2) be added to the unmodified character address 's', 03000. If (B2) = 01000, then S = 04000.

4.

The length of the A field is 148 characters and the alloted
length of the C field is 178 characters. The last three
characters of field C will be filled with zeros. The last
character of field C (a zero) will also contain the sign of
the field.
(continued on next page)

':'This instruction moves a string of 6-bit characters from field A to field C. If
field C is longer, its remainder is filled with zeros. Refer to the BDP instruction
descriptions later in this section for a more thorough explanation.

5-121

Rev K

Character Positions
'A' Field
Word Addresses

o0
o0
o0
o0

0

1 1

100

10

101

I2

13

I

01

06
11

02

04

102

06

03

11

10

103

05

51

04

07

Highest order
character in
Field A

Operand specified
in Field Aequals
-431924639859

Lowest Order
Character in
Field A

101001

'-y-I"--v--'

~dicates

I

Indicates
negative field

character
is 118 = 910

The operation proceeds as follows:
First character stored is
highest order character at
word address 01000, char-

'c' Field
Word Addresses
o0 7 7 7

o 1 000
o 100 1
o10 0 2
o 1 003

00
02
11

04
10

00

00

01
06
05

T

Lowest order character
in Field C contains the
sign of Field C (minus)
and a zero character.
RevK

5-122

03
11
07

acter as the lowest
order character of
Field C is now character position 2 of
word address 01003.
Operand now stored
in Field C equaJs
-431924639859000

MVE
Move FieldA to
Field C

23
64
23

P+1

lei

2120191B 1716

00

I I I I
0

Br

S

Bs

23

P+2

00

IB 1716

P

12 II

I

51

00
S2

r = unmodified address of the highest order character in field A. R = r + [ Br J
Er = index register flag for field A
If Br = 1 or 3, use index register B1
If Br = 2, use index register B2
If Br = 0, no indexing
s = unmodified address of the _highest order character in field C. S = s + [BsJ
Bs = index register flag for field C (same
bit functions as Br>
S 1 = number of characters 'in field A to be
moved
S 2 = number of available character positions in field C
Instruction Description: Move a field of up to 4095 6-bit alphanumeric characters
from field A to field C, left to right. If field lengths are unequal, the length of
the shorter field terminates the move and the remainder of the longer field is not
moved or changed.

I

Comments: The BDP Condition register is set to the sign of field A if the sign
character is moved. It is set to 00 for a positive sign (or no sign transferred)
2
and to 10 for a negative sign.
2

I

Index register B3 (bits 0-11) records the number of characters moved.

5-123

Rev K

MVE, DC
Move Field A to
Field C, Delimited

181716

00

III
I
I II I

00

23

P

64

212019181716

23

P+l

0

8r

23

P+2

S

Bs

12

1817

I~

r

DC

I

00
S2

= unmodified addres s of the highest order character in field A.

R = r + [Brl

Br = index register flag for field A
If Br = 1 or 3, use index register Bl
If Br = 2, use index register B2
If Br = 0, no indexing
s = unmodified address of the-highest order character in field C. S = s + [BsJ
Bs = index register flag for field C (same
bit functions as B r )
S 2 = number of available character positions in both field A and field C
DC = 6- bit delimiting character compared
against the characters in field A
Bits 18 through 23 of P + 2 should be loaded with
zeros.
Instruction Description: Move a field of up to 4095 6-bit alphanumeric characters from field A to field C, left to right,
Comments: The length of field C, S2' terminates the move operation. If the
delimiting character is recognized at any time during the character move, the
operation is terminated after the delimit character has been moved.

I

The BDP Condition register is not used for this instruction (always set to 002)'

Rev K

5-124

MVBF
Move Field A to
Field C and Blank Fill

23

P

64
23

P+1

0

1 1

21 20 19 18 17 16
I

I

Br

00

5

I85 1

23

P+2

00

18 17 16

12 II

L

SI

00
S2

r ;; unmodified address of the highest order character in field A. R = r + [Br]
Br

= index

register flag for field A
If Br = 1 or 3, use index register B1
If Br = 2, use index register B2
If Br = 0, no indexing

s = unmodified address of the highest order character in field C. S = s + [Bs]
Bs = index register flag for field C (same
bit functions as Br)
S 1 = number of characters in field A to be
moved
S 2 = number of available character positions in field C
Instruction Description: Move a field of up to 4095 6-bit alphanumeric characters from field A to field C, left to right. If field lengths are unequal, the
length of the shorter field terminates the move. If field C is longer, its
remainder is filled with blanks. The sign is contained in character last moved
from field A.
Comments: The BDP Condition register is set to the sign of field A if the
sign character is moved. It is set to 002 for a positive sign (or no sign
transferred) and to 102 for a negative sign.
Index register B3 (bits 0 -11) records the field C character count as the
instruction progresses.

5-125

RevK

MVIF
Move Field A to Field
C and Zero Fill

23

18 17 16

I

P

64

23

P+l

I

00

/0/

212019181716
2

1

8r

00
S

I Bs I
12 II

23

P + 2

SI

00

S2

r = unmodified address of the highest order character in field A. R = r + [ Br]
Br = index register flag for field A
If Br = 1 or 3, use index register B1
If Br = 2, use index register B2
If Br = 0, no indexing
s = unmodified address of the highest order character in field C. S = s + [Bs]
= index register flag for field C (same

bit functions as B r )
of characters in field A to be
moved
= number of available character positions in field C

= number

Instruction Description: Move a field of up to 4095 6 -bit BCD numeric characters
from field A to field C, left to right. If field lengths are unequal, the shorter
field terminates the move. If field C is longer, its remainder is filled with
zeros.
Comments: The zone bits of all field A characters are forced to zero when
moved to field C, as is any field A character containing a 128 - 178 code.
The sign from field A is always transferred to the BDP Condition register and
to the lowest order character in field C (which may be a zero-filled character),
even if h > ~ 2.
Index register B3 (bits 0 -11) records the field C character count as the instruction progresses.
A BCD fault is generated if one of the following conditions occur;

1.
2.
3.

Zone portion of any character in field A (except sign character) does
not equal zero.
Numeric portion of any character in field A contains a BCD code greater
than 118, except the sign character where a 128 code is legal.
The sign character contains a 728 code.

Operation continues despite any BCD fault.

RevK

5-126

MVZS
Move Field A to Field
C and Zero Suppress

23
64
23

P+1

00

1B 1716

P

0

1 1

2120 19 1B17 16
3

00

I I I
Br

S

BS

23

12 11

P+2

SI

00

S2

r = unmodified address of the highest order character in field A. R = r + [ BrJ
Br = index register flag for field A
If Br = 1 or 3, use index register B1
If Br = 2, use index register B2
If Br = 0, no indexing
s = unmodified address of the highest order character in field C. S = s + [BsJ
Bs

index register flag for field C (same
bit functions as Br)
S1 = number of characters in field A to be
moved
S2 = number of available character position in fie ld C

Instruction Description: Move a field of up to 4095 6 -bit alphanumeric characters in field A to field C, left to right, and replace all leading zeros
occurring in field A with blanks in field C. If field lengths are unequal, the
shorter field terminates the move and the remainder of the longer field is
not moved or changed.
Comments: If field A is longer than field C, the sign bits in field C may be
invalid since sign bits are not checked or modified and consist of the zone bits
of the last character moved.
The BDP Condition register contains the sign of the A field if the sign is moved
(Le., S'I4 8

Resultant Field C
Edited Data

$99

$ 4 8

$99.99

$ 4 8

4 8 3 4

9,999

4

2 9 2

+999

+

2 9 2

~2

+999

-

2 9 2

999-

2 9 2

4

THE SIGN IS
CONTAINED IN

Field C
Editing Data

THE LOWEST ORDER
CHARACTER. ONLY
MINUS SIGNS ARE
SHOWN HERE

RevK

8 3 4

2 9

"2

3 4

8 3 4

-

THE

11

FIGURE
A BLANK

~INDtCATES

2 9 2

999-

2 9 2 D.

2 4 3 2 1

$BB999.99

$ D. D. 2 4 3

2

1

2

1

POSITION

2

4

3 2 1

$00999.99

$ 0 0 2 4 3

1

1

3 4

99.99CR

1

1

3 4 C R

1

1 3 4

99.99CR

1

1

3 4 D. D.

2 3 7 "6

99.99DB

2

3

7 6 D B

2 3 7 6

99. 99DB

2

3

7 6 D. D.

0 0 9 2 3

ZZ999

D. 4 9 2 3

0 0 9 2 3

ZZZ99

D. D. 9 2 3

0 0 0 0 0 0

ZZZZ.ZZ

D. D. D. D. D. D. D.

0 0 9 2 3

$***.99

$ * * 9

0 0 0 8 2 4

$$$$9.99

D. D. D. $ 8

0 0 5 2 6

---9.99

D. D.

-

5

3 2 6 5

$$$.99

$ 3 2

.

5-136

2 3
2 4
2 6
6

5

Field A Data
o 0 0 0 1 234

Field C
Editing Data
$ZZZ, ZZZ. 99

Resultant Field C
Edited Data

$

~

~ ~

~

1 2

3 4

001 2 345 6

$

* *

1

234

5 6

1 234 5 634

$ 1 2 3

456

3 4

$ZZZ, ZZ9. 99CR

$ 1 2 3

456

2 4 C R

001 2 340 0

$$$$,$$9.99

~

234

o

o

0 0 0 0 0

$$$$,$$$.99

o

0 0 0 1 256

----, ---. 99DB

o

0 0 0 1 2

1 234 5 6 2

~

-ZZZ,ZZZ

4"

~

$ 1

0

5 6 D B

*

1.

Only one replacement character of the set Z
$ + and - can be used within
a single editing C field even though it may be specified more than once.

2.

If one of the replacement characters Z or

3.

A plus sign and a minus sign may not be included in the same editing C field.

4.

A leftmost plus sign and a dollar sign may not be included in the same
editing C field.

5.

A leftmo st minus sign and a dollar sign may not be included in the same
editing C field.

6.

The character 9 may not be specified to the left of a replacement character.

7.

Symbols which may appear only once are:

8.

The decimal point may not be the rightmost character in an editing C field.

~~ is used with one of the
insertion characters $ + or -, the plus sign or the minus sign may be
specified as either the leftmost or rightmost character in the editing C
field.

5-137

decimal point, CR, and DB.

RevK

I

SCAN, LR, EQ
Search Field A Left
to Right for Equality

23

P

IS 17 16

I
23

p+11

10 1

2120191S
0

IS 17

23

P+2

00

I
Isr_
65

00

12 II

00

sc

r ;:: unmodified address of the highest order character in field A. R;:: r + [Br]
Br ;:: index register flag for field A
If Br ;:: 1 or 3, use index register B1
If Br ;:: 2, use index register B2
If Br ;:: 0, no indexing
SC ;:: 6- bit scan character compared against
characters in field A
S2 ;:: number of characters to be searched
Bits 00 through 18 of P + 1 and bits 12 through 17
of P + 2 should be loaded with zeros.
Instruction Description: Search field A from left to right beginning with the
6- bit character at location Rand RNI at P + 4 if a character is found that is
equal to the scan character, SC. If a character is not found that equals the SC
after the entire field defined by S2 has been searched, RNI at P + 3.
Comments: If a character comparison occurs during the search, the number of
searched characters is transferred to the lower 12 bits of B3. If an unsuccessful
search is made, then (B3) ;:: S2. The upper 3 bits of B3 are of no consequence
in this instruction. BCD codes o~ 12 , 32 , and 528 do not compare equal to
8
8
zero for this instruction.

I

The BDP Condition register is not used (always set to 00 2 ).

RevK

5-138

SCAN, LR, EO, DC
Search Field A Left to
Right for Equality, Delimited

P

I

23

00

18 17 16

23

65

I

III

21201918

00

p+110IBr~
23

P +2

18 17

sc

12

II

00

DC

r = unmodified address of the highest order character in field A. R = r + [ Br]
Br = index register flag for field A
1
If Br = 1 or 3, use index register B
If Br = 2, use index register B2
If Br = 0, no indexing
SC = 6-bit scan character compared against
characters in field A.
S 2 = number of characters to be searched.
DC = 6- bit delimiting character compared
against characters in field A
Bits 00 through 18 of P + 1 should be loaded with
zeros.
Instruction Description: Search field A from left to right beginning with the
6- bit character at location Rand RNI at P + 4 if a character is found that is
equal to the scan character, SC. If a character is not found that equals the SC
after the entire field defined by S2 has been searched or if a character is found
that equals the delimiting character, DC, RNI at P+3. (If SC equals DC and comparison with field A occurs, RNI at P + 4).
Comments: If a character comparison is found during the search, the number
of characters searched is transferred to the lower 12 bits of B3. If an unsuccessful search is made, then (B3) = S2. The upper 3-bits of B3 are of no
consequence in this instruction. BCD codes of 12 , 32 , and 528 do not compare
8
8
equal to zero for this instruction.

I

The BDP Condition register is not used (always set to 00 2 ).

5-139

RevK

SCAN, LR,

NE

Search Field ALeft
to Right for Inequality

23

16 17 16

00

P
23

p+ll

21201916

23

P+2

00

zI B r _
16 17

sc

12 II

00

~

r = unmodified address of the highest order character in field A. R = r + [Br]
Br = index register flag for field A
1
If Br = 1 or 3, use index register B
If Br = 2, use index register B2
If B = 0, no indexing
SC
scarf character which is compared
against characters in field A.
S 2 = number of characters to be searched
Bits 00 through 18 of P + 1 and bits 12 through 17
of P+ 2 should be loaded with zeros.
Instruction Description: Search field A from left to right beginning with the 6bit character at location R, and RNI at P + 4 if a character is found that is not
equal to the scan character, SC.
If a character is not found that is not equal
to the SC after the entire field defined by S2 has been searched, RNI at P + 3.

Comments: If an unequal character comparison is found during the se~ch, the
number of characters searched is transferred to the lower 12 bits of B. If all
characters searched are equal to the SC, then (B3) = S2' The upper 3 bits of B3
are of no consequence in this instruction. BCD codes of 128, 328, and 528 do not
compare equal to zero for this instruction.

I

The BDP Condition register is not used (always set to 00 2 ),

Rev K

5-140

SCAN, LR, NE, DC

Search Field A· Left to
Right for Inequality, Delimited

23

P

I

I

II I

65

23

P+l

00

181716

21201918

00

121sr_
23

18 17

P +2

SC

12

I

00

DC

r = unmodified address of the highest order character in field A. R = r + [Br]
Br

= index register flag for field

A
If Br = 1 or 3, use index register Bl
If Br = 2, use index register B2
If Br = O. no indexing

SC = scan character which is compared
against characters in field A.
S 2 = number of characters to be searched
DC = 6- bit delimiting character compared
against the characters in field A
Bits 00 through 18 of P + 1 should be loaded with
zeros.
Instruction Description: Search field A from left to right beginning with the
6- bit character at location R. and RNI at P + 4 if a character is found that is
not equal to the scan character, SC.
If a character is not found that is not
equal to the SC after the entire field defined by S2 has been searched or if a
character is found that equals the delimiting character, DC, RNI at P + 3.
(If SC equals DC and an unequal comparison with field A occurs, RNI at P + 4),
Comments: If an unequal character comparison is found during the search, the
number of characters searched is transferred to ~he lower 12 bits of B3. If all
characters searched are equal to the SC, then (B ) = S2. The upper 3 bits of B3
are of no conseque~ce in this instruction. BCD codes of 12 8 , 328 and 528 cause
an unequal comparIson to zero.

I

The BDP Condition register is not used (always set to 00 ),
2

5-141

Rev K

SCAN, RL, EO

Search Field A Right
to Left for Equality

23

P

I

18 17 16

23

23

P +2

00

_
18 17

sc

r

I

21201918

1118 r

P+1

00

10 1

65

12 II

00

~

= unmodified

address of the lowest order character in field A. R = r + [B r ]

Br

= index

SC

= scan

register flag for field A
If Br = 1 or 3, use index register B1
If Br = 2, us e index register B2
If Br = 0, no indexing

character which is compared
against characters to be searched.
S2 = number of characters to be searched

Bits 00 through 18 of P + 1 and bits 12 through 17
of P + 2 should be loaded with zeros.
Instruction Description: Search field A from right to left beginning with the 6-bit
character at location Rand RNI at P + 4 if a character is found that is identical to
the scan character, SC. If a character is not found that equals the SC after the
entire field defined by S2 has been searched, RNI at P + 3.

I

Comments: If a character comparison is found during the sgarch, the number of
characters searched is transferred to the lower 12 bits of B. If an unsuccessful
search is made, then (B3) = S. The upper 3 bits of B3 are of no consequence in
this instruction. BCD codes 0112 , 32 , and 528 do not compare equal to zero.
8
8
The BDP Condition register is set to the sign of field A.

RevK

5-142

.S'

SCAN, RL, EO, DC
Search· Field A Right

23

181716

00

P

.. to Left. for ~quality, Delimited.

23

P+1

21201918

00

Illsr_
23

P + 2

IBI7

sc

12 II

00

DC

r = unmodified address of the lowest order character in field A. R = r + [Br]
Br = index register flag for field A
If Br = 1 or 3, use index register B1
If Br = 2, use index register B2
If Br = 0, no indexing
SC = scan character which is compared
against characters in field-A.
S2 = number of characters to be searched
DC = 6- bit delimiting character compared
against the characters in field A
.Bits 00 through 18 of P + 1 should be loaded with
zeros.
Instruction Description: Search field A from right to left beginning with the 6bit character at locations Rand RNI at P + 4 if a character is found that is
equal to the scan character, SC. If a character is not found that equals the SC
after the entire field defined by S2 has been searched or if a character is found
that equals the delimiting character, DC, RNI at P + 3 (if SC equals DC and an
equal comparison with field A occurs. RNI at P + 4),
Comments: If a character comparison is found during the search, the number of
characters searched is transferred to the lower 12 bits of B3. If an unsuccessful
search is made, then (B3) = S 2. The upper 3 bits of B3 are of no consequence in
this instruction. BCD codes of 12 8 , 32 8 , and 528 do not compare equal to zero.

I

The BDP C;ondition register is set to the sign of field A.

5-143

Rev K

SCAN, RL, NE

Search FielcJrA Right

23

P

I

P+1

1

to Left for Inequality

1817 16

65

23

r_
00

I

0

11

2120 19 18

3

23

P+2

00

1B

18 17

sc

12 II

00

~

r = unmodified address of the lowe st order character in field A. R = r + [Br]
Br = index register flag for field A
If Br = 1 or 3, use index register B1
If Br = 2, use index register B2
If Br = 0, no indexing
se = scan character which is compared
against characters in field A
S2 = number of characters to be searched
Bits 00 through 18 of P + 1 and bits 12 through 1 7
of P + 2 should be loaded with zeros.
Instruction Description: Search field A from right to left beginning with the 6bit character at location Rand RNI at P + 4 if a character is found that is not
equal to the scan character, SC. If a character is not found that is not equal
to the se after the entire field defined by S2 has been searched, RNI at P + 3.

I

Comments: If an unequal character comparison is found during the search, the
number of characters searched is transferred to the lower 12 bits of:]33. If all
characters searched equal se, then (B3) = S2. The upper 3 bits of B are of no
consequ.ence in this instruction. BeD codes 12 8 , 32 8 , and 528 cause an unequal
comparIson to zero.

I

The BDP Condition register is set to the sign of field A.

Rev K

5-144

SCAN, RL, NE, DC
Search Field A Right
to Left for Inequality, Delimited

00

ISI716

23

P
23

P+l

2120191S

131sr_
I
I
23

.P+2

00

IS 17

SC

12 II

00

DC

r = unmodified address of the lowe st order character in field A. R = r + [Brl
Br = index register flag for field A
If Br = 1 or 3, use index register Bl
If Br = 2, use index register B2
If Br = 0, no indexing
SC = scan character which is compared
against character s in field A
S 2 = number of characters to be searched
DC = 6- bit delimiting character compared
against the characters in field A
Bits 00 through 18 of P + 1 should be loaded with
zeros.
Instruction Description: Search field A from right to left beginning with the 6bit character at location Rand RNI at P + 4 if a character is found that is not
equal to the scan character, SC. If a character is not found that is not equal
to the SC after the entire field defined by S2 has been searched, or if a character is found that equals the delimiting character, DC, RNI at P + 3 (If SC equals
DC and an pnequal comparison with field A occurs, RNI at P + 4).
Comments: If an unequal character comparison is found during the search, the
number of characters searched is transferred to the lower 12 bits of B3. If all
characters searched equal SC, the (B3) = S2' The upper 3 bits of B3 are of no
consequence in ~his instruction. BCD codes of 12 , 32 , and 528 cause an
8
8
unequal companson to zero.

I

The BDP Condition register is set to the sign of field A.

I

5-145

Rev K

CVDB
Convert'
BCD to Binary

23

181716

P

66
23

P+1

21201918 1716

I I I
SI
I
0

23

P+2

00

0
1 1

Br

020100

m

Bml
1211

~
00

~

r = unmodified address of the highest order
BCD character in field A. R = r + [ Br]
Br = index register flag ~or field 1>:.
1
If Br = 1 or 3, use mdex regIster B
If Br = 2, use index register B2
If Br = 0, no indexing
m = unmodified address of the highe st order
bits in binary field C. M = m + [Bm]
Bm = index register flag for binary field C.
(same bit functions as B). Bits 02-14
of the index register arerused for word
address indexing (13 bit index-sign
extended). Bits 00 and 01 must be set
to "l's".
Sl = number of BCD characters to be converted.
Bits 00 and 01 of P + 1, and bits 00 through 11 ofP + 2 should be loaded with zeros.
Instruction Description: Convert a BCD number of up to 1410 numeric characters
in magnitude (including sign) into its binary equivalent in one's complement notation and store the result in locations M and M + 1.
Comments: The resultant binary number is placed into the words at locations M
and M + 1. The sign of the binary number is always stored in bit 23 of M. The
maximum positive BCD number (fourteen 9's) is equal to 2657142036437777 ,
8
The complement of this number in M and M + 1 equals a negative field of fourteen
9's.
The BDP Condition register is set to the sign of field A.
a count of the BCD characters converted.

The B3 register contains

A BCD fault is generated if one of the following conditions occur:

Zone portion (upper 2 bits) of any character (except sign character) does
not equal zero.
2. Numeric portion (lower 4 bits) of any character in field A contains a BCD
code greater than 11 8 , except the sign character where a 128 code is legal.
3. The sign character contains a 728 code.
4. More than 14 10 BCD characters are specified by Sl'
Operation continues despite any BCD fault.
1.

I

Rev K

5-146

CVBD
Convert
Binary to BCD

020100

181716

23

P

m

66
23

020100

212019181716

P+l

n
00

23

P+2
m

= unmodified

address of the highest order bits in binary field A.
M = m+ [Bm]
Bm = index register flag for field A.
1
If B m = 1 or 3, use index register B
If B
= 2, use index register B2
If B: = 0, no indexing
Bits 02-14 of the index register are used for word address
indexing (13 bit index-sign extended). Bits 00 and 01
must be set to "1' S".
n

= unmodified

address of the highest order BCD character in field C.
N = n + [Bn]
Bn = index register flag for field C.
(same bit functions as Bm)
Bits 00 and 01 of P, bits 00 and 01 of P + 1, and bits 00
thr-ough 23 of P + 2 should be loaded with zeros.
Instruction Description: Convert the 48-bit binary number (including sign) at M
and M + 1 into its signed, numeric BCD equivalent and store in field C.
Comments: (M) and (M + 1) are always analyzed for the binary number to be converted. This is true even if the binary number does not utilize all of the bit positions of M. The sign of the original binary number is located in bit 23 of M. The
sign of the binary number is stored in the field C sign character and is set in the
BDP Condition register.

I

A BCD fault is generated if the conversion results in a number of more than 14

BCD characters.

10
characters will be correct.
Highest Order BCD
Zeros are always stored here
Character Position

However the lower 14

10

A

(N) =

(N+1)=

12

II

10

BCD character positions
6
7
8
(N+2)=
appear in this order.
(This character position------------------~~
always contains the sign
3
4
2
of the field. )
The original contents of index register B3 is destroyed.
zeros.
5-147

9

5

Bits 0-11 are set to all
Rev K

I

DTA
Convert
BCD to ASCII

I

23

181716

I

P

66

23

NOTE
This instruction is available only in the 3312 and
3304-2.

P + 1 I

00

10 1

212019181716

2

I Br 18 m I

23

m
12 II

00

P+2_

r = unmodified address of the highest order character in BCD field A.
R = r + [Br]
Br = index register flag for field A.
1
If Br = 1 or 3, use index register B
If Br = 2, use index register B2
If Br = 0, no indexing
m = unmodified word address of the highest
order characters in ASCll field C.
M = m + [Bm]
B
index register flag for field C
(same bit functions as B ). Bits
m
r
02-14 of the index register are
used for word address indexing (13
bit index- sign extended). Bits 00
and 01 must be set to "1' s".
S 2 = number of characters to be converted
Bits 00 and 01 at P + 1 and bits 12 - 23 of
P + 2 should be loaded with zeros.
Instruction Description: Convert a field of up to 4095 6- bit BCD characters in
field A into the 8- bit American Standard Code for Information Interchange
(ASCII) in field C.
Comments: Conversion proceeds from left to right (Refer to Appendix A for a
comparative listing of BCD and ASCII codes. )

I

If the last ASCll character stored occupies bits 12-19, zeros are stored in bits
00-07. The BCD codes of 128, 328, and 528 are not treated as zero for this
instruction. The count in the B3 register upon completion equals four times the
number of 24-bit words stored. The BDP Condition register is not used (always
set to 00 ),
2

The first ASCII character is always placed in this character position of the word
specified by M.
08 07

M
20 19

M+1
Rev K

00

SECOND ASCII
CHARACTER

5-148

THIRD ASCII
CHARACTER

00
FOURTH ASCII
CHARACTER

DTA, DC
Convert BCD
to ASCII, Delimited

NOTE
This instruction is available only in the 3312 and
3304-2.

23

P

181716
66

I
23

P+1

I

III

2120 19 18 17 16

I

2

23

P+2

00

02 0100

I Br IBm I
12 II

IB 17

~

r
Br

m
B
m

S2
DC

DC

I

~

m

00

Sz

= unmodified

address of the highest order character in BCD field A.
R = r + [Brl.
= index register flag for field A
If Br = 1 or 3, use index register B1
If Br = 2, use index register B2
If Br = 0, no indexing
= unmodified address of the highest order word in ASCII field C.
M = m+ [Bm]
= index register flag for field C
(same bit functions as B r ). Bits
02-14 of the index register are used
for word address indexing 03-bit
index-sign extended). Bits 00 and
01 must be set to ones.
= number of characters in ASCII field C
= 6- bit delimiting character compared
against characters in field A.

Bits 18 through 23 at P + 2 and 00 and 01 at P + 1
should be loaded with zeros.
Instruction Description: Convert a field of up to 4095 6-bit BCD characters in
field A into the 8- bit American Standard Code for Information Interchange (ASCIn
in field C. The conversion proceeds from left to right. The operation is terminated when the number of characters specified byS2 has been converted or the
delimiting character is recognized in field A. A character equal to the delimiting
character is converted when encountered.
~ommer;ts: The BCD c~des of ~28' ~2JP and 528 are n~t treated as zer? for this
lnstruchon. The count in the B register upon complehon equals four hmes the
number of 24-bit words stored. The BDP condition register is not used (always
set to 002)'
The first ASCII character is always placed in this character position of the word
specified by M.
\
~__Z~0~1~9~~~~~~~0~BTO~7~~~~~0~0
FIRST Ascn
CHARACTER

M

00

M+1
5-149

THIRD ASCII
CHARACTER

FOURTH ASCII
CHARACTER

RevK

I

ATD
Convert·
ASCII. to BCD

23

181716

I

P

23

I

NOTE
This instruction is available
only in the 3312 and 3304-2.

I

P+1

020100

101

66

~

m

212019181716
3

8m

1

l

8

s

00

I

s

I

23

1211

00

~~

P+2

I

S2

m

unmodified word address of the highest
order characters in ASCn field A.
M=m + B
(Refer to diagram below. )
m
Bm = index register flag for field A
1
If B
= 1 or 3, use index register B
m
If B
m = 2, use index register B2
If B
= 0, no indexing
BitsIlQ2-14 of the index register are
used for word address indexing 03-bit
index-sign extended>. Bits 00 and 01
must be set to ones.
s = unmodified address of the highest order
character in BCD field C. S = [s + Bs]
Bs = index register flag for field C
(same bit functions as B:m)
S2 = number of characters in BCD field C
Bits 00 and 01 of P and bits 12-23 of P + 2 should be
loaded with zeros.

Instruction Description: Convert a field of up to 4095 8-bit American Standard
Code for Information Interchange (ASCID characters in field A into 6- bit BCD
characters in field C2-. The conversion proceeds from left to right. The operation
is terminated when S2 is exhausted.

I

Comments: A BCD fault is generated if bit positions 05 and 06 for any character
contain both "l's" or both "a's" (an illegal character). An illegal character is set
to zero in field C and conversion continues to completion. The B3 register indicates the number of BCD characters stored. The BDP Condition register is not
used (always set to 002)'

I

The first ASCII character is always located in this character position of the word
specified by M. Shaded areas are not used.
23

12 II

20 19

0807

00

~7r.~~F~IR-S~T-A~S-CI-I~~~~-S-E-CO-N-D-A-S-C-II~
CHARACTER
CHARACTER

M

00

M

+1

FOURTH ASCII
CHARACTER

I

I

etc.
RevK

5-150

I

etc.

ATD, DC
Convert ASCII
to BCD, Delimited

23

P

IB 1716

I
I I

66

23

NOTE

P+1

This instruction is available only in the 3312 and
3304-2.

Bml Bs

Bm

s
Bs
S2
DC

00

I

I

s

2019

~
m

~

m

III

2120 191B 1716

3

23

P+2

020100

1211

00

I

DC

I

S2

= unmodified word address of the highest
order characters in ASCII field A.
(Refer to diagram below. )
Bm
M = m +
= index register flag for field A
1
If B
=
1
or
3,
use
index
regist.er
B
m
If B
= 2, use index register B~
m
If B
= 0, no indexing
Bits:rro2-14 of the index register are
used for word address indexing (13-bit
index-sign extended>. Bits 00 and 01
must be set to "1' s".
= unmodified address of the highest order
character in BCD field C. S = [s + BsJ
= index register flag for field C.
(same bit functions as Bm)
= number of characters in BCD field C
= 8-bit delimiting character compared
against characters in field A

Bits 20 through 23 at P + 2 and 00 and 01 at P
should be loaded with zeros.
Instruction Description: Convert a field of up to 4095 8-bit American Standard
Code for Information Interchange (ASCII) characters in field A into 6-bit BCD
characters in field A. Conversion proceeds from left to right. The operation
is terminated when S2 is exhausted or an ASCII character equal to the delimiting
character is recognized. A character equal to the delimiting character is converted when encountered.
Comments: A BCD fault is generated if bit positions 05 and 06 for any character
contain both "l's" or both "O's" (an illegal character). An illegal character is
set to zero in field C and conversion continues to completion. The B3 register
indicates the number of BCD characters stored. The BDP Condition register is
not used (always set to 002).
The first ASCII character is always derived from this character position of the
word specified by M. Shaded areas are not used.
23

M

20 19

t
FIRST ASCII
CHARACTER

12 II

OB 07

00

SECOND ASCII
CHARACTER

M+1
5-151

RevK

I

PAK
Convert·6-Bit
BCD 'to4-Bit. BCD

18 17 16

00

212019181716

0201 00

23

I

P

23

66

H

P+1
23

00

1211

S2

P+2
r

= unmodified

address of the lowest order character in the A field.
R = r + [Brl
Br = index register flag for field A
1
If Br = 1 or 3, use index regis~r B
If Br = 2, use index re gister B
If Br = 0, no indexing
m = unmodified address of the lowest order word in field C.
M

= m + [B:ml

Bm = index register flag for field C
(same bit functions as B )
Bits 02-14 of the index i~gister are
used for word address indexing (13-bit
index-sign extended). Bits 00 and 01
must be set to "1' s".
S2 = number of 6-bit characters in field A
to pack.
Bits 00 and 01 or P + 1, and bits 12 through 23 of
P + 2 should be loaded with zeros.

I
I

1

Instruction Description: Convert from right to left, a field of numeric 6-bit BCD
characters in field A into 4-bit BCD characters and store the result in field C.
The zone (upper 2) bits of all 6-bit characters are removed.
Comments: The sign of field A is converted into a 4-bit sign character (10102 positive, 10112 - negative) and is placed in the low order character position of
field C prior to packing BCD characters. Any A field character with a 128 - 178
code is forced to a zero in field C. A full word store is used. Any unfilled 4-bit
characters in the highest order word are stored as zeros. The B3 register contains a count equal to four times the number of 24-bit words stored. The BDP
Condition register is not used (always set to 00 ),
2
A BCD fault is generated if one of the following conditions occur:

1.
2.

I

3.

Zone portion (upper 2 bits) of any character (except sign character) does
not equal zero.
Numeric portion (lower 4 bits) of any character in field A contains a BCD
code greater than 11 8 , except the sign character where a 128 code is legal.
The sign character in field A contains a 728 code.

Operation continues despite any BCD fault.

RevK

5-152

23

UPAK
Convert 4-Bit
BCD to 6-Bit BCD
-------.----.~--

1817 16

P
,

---~-----.--

66
23

P+1

I

101

~

212019181716

5

23

P+2

020100

m

00

I l I
8m

s

Bs

12 II

~~

00
S2

]

m =

unmodified address of the lowest
order word in field A.
M = m + [BrJ
= index register flag for field A
1
If Bm = 1 or 3, use index register B
If Bm = 2, use index register B2
If Bm = 0, no indexing
Bits 02-14 of the index register are
used for word address indexing
(13-bit index-sign extended).
Bits 00 and 01 must be set to 11'S".
s = unmodified address of the lowest order
character in field C. S = [s + Bs J
= index register flag for field C
B
s
(same bit functions as Bm)
number of characters resulting in
field C.
Bits 00 and 01 of P and bits 12 through 23 should
be loaded with zeros.
Instruction Description: Convert from right to left, a field of packed numeric
4-bit BCD characters in field A into 6-bit BCD characters and store the result in
field C. Zone bits of new 6-bit characters are set to '00' except in the lowest
order character which receives the algebraic sign from the 4-bit sign character
in field A. Field C contains one less character than field A due to the elimination
of the 4- bit sign character.
Comments: The conversion commences with the sign character of the 4-bit BCD
field. If the sign is positive (10102), '00' zone bits are stored in the field C sign
character; if negative (10112)' a '10' is stored. A result sign character code
(zone and numeric) of 408 is converted to 528' Any A field character (other than
the sign character) containing a 128-178 code results in a zero in field C.
The B3 register indicates the number of 6-bit characters stored in field C.
BDP Condition register is not used (always set to 002)'

The

A BCD fault is generated if one of the following conditions occur:
1.

2.

The sign character in field A is other than 1010 or 1011 (the sign of
2
2
field C is then set to zero), or
Any other character in field A contains a 12 8 -17 8 code, except the
second lowest character where a 128 code is legal.

Operation continues despite any BCD fault.

5-153

RevK

ADM
Add Field A to· Fi~/d C

I

I

This description applies
conly to the 3312 and 3304-2.
See next page for 3304-3.

67

101

I I I I
I
0

Br

s

BS

23

P+2

00

212019181716

23

P+l

00

181716

23

P

51

r

s

00

1211

S2

I

unmodified address of lowest order
character in field A. R = r + [Br]
= index register flag for field A
1
If B = 1 or 3, use index register B
r
If B = 2, use index register B2
If B ~ = 0, no indexing
unmodified address of lowest order
character in field C. S = s + [Bs]
index register flag for field C (same
bit functions as Br)
= 12-bit character count specifying the
length of the A field
= 12-bit character count specifying the
length of the C field

Instruction Description: Add the BCD contents of field A (addend) to field C
(augend) proceeding from right to left. The sum appears in field C. The lowest
order character of each field specifies sign. The sign of the sum is contained in
the character defined by the original address S.
Comments: Field A may be shorter than field C as carries can be set into progressively higher order positions of field C. If any character position of either
field contains a 128 - 178 code, it is converted to zero before the add operation.
The BDP Condition register indicates a positive sign (00) or negative sign (10)
according to the result in field C. A zero result may have either a positive or
negative sign.
Index register B
progresses.

3

(bits 0-11) records the C field character count as the instruction

A BCD fault is generated if one of the following conditions occur:
1.

2.

3.
4.
5.

An arithmetic carry is attempted out of the upper limit of field C.

SI > S2

Zone portion (upper 2 bits) of characters in either field (except sign
character) does not equal zero.
Numeric portion (lower 4 bits) of characters in either field contains a
BCD code greater than 11 8 , except the sign character where a 128 code
is legal.
The lowest code character (sign character) in either field contains a 728
code.

Operation continues despite any BCD fault.

Rev K

5-154

ADM
Add Field A to Fi~ld C

67

I

P+1

101

0

1

8

r

r

s
B

s

00

1211

SI

I
I

s

I BS I

23

P +2

00

212019181716

23

Applicable to 3304-3
only. See previous
page for 3312 and 3304-2.

00

181716

23

P

I

S2

unmodified address of lowest order
character in field A. R = r + [Br]
= index register flag for field A
1
If Br = 1 or 3, use index register B
If Br = 2, use index register B2
If B r = 0, no indexing
unmodified address of lowest order
character in field C. S = s + [B ]
index register flag for field C s
(same bit functions as B r )
= 12-bit character count specifying
the length of the A field
12 -bit character count specifying
the length of the C field

=

Instruction Description: A[ld the BCD contents of field A (addend) to field C
(augend) proceeding from right to left. The sum appears in field C. The lowest
order character of each field specifies sign. The sign of the sum is specified
by the character defined by the original address lSI.
Comments: Field A may be shorter than field C as carries can be set into progressively higher order positions of field C. This instruction normally terminates
when the C field is exhausted; however, an early exit occurs prior to this time
when the following conditions are present:
1.
2.
3.
4.

I

A field exhausted,
ADD and signs alike,
No carry, and
The current cumulative arithmetic result is not zero.

A 608 code (blank) encountered in either field is treated as a 008 code. A sign
character code of 408 in the result field is converted to a 528, the code for magnetic tape character negative zero. If any character position 0f either field contains a 128 - 178 code, it is converted to zero before the add operation.
The BDP Condition register indicates a positive sign (00) or negative sign (10)
according to the result in field C. A zero result will always be positive.
Index register B3 (bits 0-11) records the field C character count as the instruction
progresses.
A BCD fault is generated if one of the following conditions occurs:
1.
2.
3.

An arithmetic carry is attempted out of the upper limit of field C.
§1 > §2
Zone portion of characters in either field (except sign character) does
not equal zero.
4. Numeric portion of characters in either field contains a BCD code greater
than 11 8 , except the sign character where a 128 code is legal.
5.
The sign character in either field contains a 728 code.
Operation continues despite any BCD fault.
5-155

Rev K

23

SSM

P

Subtrod Field
A from Field C '

23

I

P+1

I

Applicable to 3312 and 3304-2
only. See next page for 3304-3. P+2

I

101

I

00

5

18r I BS I
12 II
51

s

00

21 201918 17 16

23

r

I

18 17 16
67

00
52

unmodified address of the lowest
order character in field A.
R = r + [Br]
= index register flag for field A
1
If Br = 1 or 3, use index register B
If Br = 2, use index register B2
If Br = 0, no indexing
= unmodified address of the lowest
order character in field C.
S = s + [B ]
= index regiSster flag for field C
(same bit functions as Br)
12 -bit character count specifying
the length of the A field
12-bit character count specifying
the length of the C field

Instruction Description: Subtract the BCD contents of field A (subtrahend) from
field C (minuend) proceeding from right to left. The difference appears in
field C. The lowest order character in fields A and C contain the algebraic sign
of their respective fields. The sign of the difference appears in the lowest order
character in field C.
Comments: 51 must be
subtraction.

:5 52

since field C must accommodate the result of the

If any character position of either field contains a 128 - 178 code, it is converted

to zero before the subtract operation.
The BDP Condition register indicates a positive sign (00) or a negative sign (10)
according to the result in field C. A negative zero result will never occur.
BCD codes 128 - 178 in the lowest order character in either field are converted
to zero.
Index register B
progresses.

3

(bits 0-11) records the field C character count as the instruction

The conditions for generating a BCD fault are identical to those for the ADM
instruction.

RevK

5-156

23

SBM
Subtract Field
A from Field C .
Applicable to 3304-3 only.
See previous page for
3312 and 3304-2.

18 17 16

I

P

67

23

I

P+l

1 1

21 201918 17 16
I

I
r

s

00

1 8 r I Bs I

23

P+2

00

0

s
12 II

SI

00
S2

I

unmodified address of the lowest
order character in field A.
R = r + [Br]
index register flag for field A
If Br = 1 or 3, use index regist er Bl
If Br = 2, use index register B 2
If Br = 0, no indexing
= unmodified address of the lowest
order character in field C.
S = s + [Bs]
= index register flag for field C
(same bit functions as Br)
12-bit character count specifying
the length of the A field
12-bit character count specifying the
length of the C field

Instruction Description: Subtract the BCD contents of field A (subtrahend) from
field C (minuend) proceeding from right to left. The difference appears in
field C. The lowest order character of each field specifies sign. The sign of
the difference appears in the lowest order character in field C.

I

Comments: Sl must be :::. S2 since field C must accommodate the result of the
subtraction. This instruction normally terminates when the C field is exhausted;
however, an early exit occurs prior to this time when the following conditions
exist:
1.
2.
3.
4.

A field exhausted,
SUBTRACT and signs alike,
No carry, and
The current cumulative result is not zero.

A 60 S code (blank) encountered in either field is treated as a OOS code. A sign
character code of 40 S in the result field is converted to a 52S, the code for
magnetic tape character negative zero. If any character position of either field
contains a 12S - 17 S code, it is converted to zero before the subtract operation.

I

The BDP Condition register indicates a positive sign (00) or a negative sign (10)
according to the result in field C. A zero result will always be positive.
Index register B3 (bits 0-11) records the field C character count as the instruction
progresses.
The conditions for generating a BCD fault are identical to those for the ADM
instruction.
5-157

RevK

I

67

23

I

\0\
00

212019181716

I I I I

P+l

3

NOTE
This description applies
to the 3312 and 3304-2
only. See next page for
3304-3.

00

181716

23

P

Br

BS

I

I

5,

52

I

unmodified address of the highest
order character in field A

r

R = r

s

00

1211

23

P+2

s

+ (B r )

index register flag for field A
If Br = 1 or 3, use index register B1
If Br = 2, use index register B2
If Br = 0, no indexing
unmodified address of the highest
order character in field C.
S = s + (Bs)
= index register flag for field C (same
bit function as B r )
12 bit character count specifying the
length of the A field
12 bit character count specifying the
length of the C field

Instruction Description: Compare characters in field A with field C proceeding
from left to right. Terminate the operation when an unequal character comparison occurs and RNI at P + 3. If the comparison condition is not satisfied when
one of the fields has been completely examined. the remainder of the other field
is examined for blanks (60 codes). If the remaining characters are all blanks.
the compare operation is terminated as an equal comparison and the next instruction is read from P + 4. If the remainder of the larger field does not contain all
blanks and:
If Sl > S 2' then an A > C comparison condition exists.
If S2 > S l' then an A < C comparison condition exists.

Comments: The result of the comparison is entered into the BCD Condition
register as described in the table below. If the fields are unequal, the next
instruction is read from P + 3. If the fields are equal, the next instruction is 3
read from P + 4. The count of C field characters processed is placed in the B
register upon completion of the instruction.

I

I
RevK

Comparison
Condition

Contents of
BDP Condition Register

A=C

00

A>C

01

AC

01

A S2' then an A > C condition is recorded
S2 > S1' then an A < C condition is recorded
The user can establish any collating sequence he wishes in the storage table. The
table is located in absolute addresses 00040S - 00057S (character addresses
00200 S - 002778) in main core storage. It contains 64 character locations, one
for each of the 64 possible 6-bit BCD code combinations that can appear in the
A or C field. Each 6-bit BCD code selects one character location in the table
as follows:
code OOS references location 00040S, character 0
code 01 references location 00040, character 1
code 02 references location 00040, character 2
code 03 referenc.es location 00040, character 3
code 04 references location 00041, character 0

code 04 references location 00057, character 3
The contents of each character location in the table is a 6-bit quantity that
represents the rank of the corresponding code within the collating s~quence.
The character address corresponding to any 6-bit code can be determined by
adding the 6-bit code to 00200S. For example, the character address referenced
by code 17S is 00217S.
Example
Assume two fields of equal length, to be ordered according to the USASCII
collating sequence pre-stored in the storage table:
Field A = 3N374

03

Field C = 3N3X2

03

I 45
I 45

03

07

04

03

54

02

Step 1 - A character by character compate is performed; inequality
between the two fields is detected at the 4th character.

RevK

5-160

Step 2 - The table is referenced to obtain the two corresponding ASCII
collating positions for the unequal characters. The table addressing is
automatically done by adding the table base address (002008) to the 6-bit
code:
Field A table character address:::: 00200 + 07 :::: 00207
Field C table character address:::: 00200 + 54 :::: 00254
00040 (200 - 203)

120

21

22

23

00041 (204 - 207)

124

25

26

27

00053 (254 - 257)

112

03

74

36

Table containing
ASCII collating
sequence

The table indicates that code 07 (from field A) ranks 27th within the collating
sequence while code 54 (from field C) ranks only 12th. Thus an A > C result is
recorded in the BDP Condition register as (01 ),
2
Step 3 - Perform an RNI at P + 3. B3 register would contain a
character count of 4 upon the exit.

5-161

Rev K

CMP, "DC
•. ', . .•. . .
Compare 'Field kto 'f··
"Field' C:/D~lim;ted

!'/.:.!

NOTE

I

This description applies to
the 3312 and 3304-2 only.
See next page for 3304-3.

23

191716

00

23

2120 1919 1716

00

P

P+l

s
23

1917

P+2

12 II

00

DC

r

=

unmodified address of the highest
order character in field A.
R = r

Br

+

(B r )

= index register flag for field A
If Br
If Br
If Br

s
==

==

==
==
==

1, or 3, use index register B

2, use index register B2
0, no indexing
unmodified address of the highest
order character in field C.
S == s + (Bs)
index register flag for field C (same
bit functions as Br)
6-bit delimiting character
12-bit character count specifying the
length of field C

Field A always contains the same number of
characters as field C during a delimited compare
operation. Bits 18 through 23 of P + 2 should be
loaded with zeros.
Instruction Description: Compare characters in field A with field C proceeding
from left to right. Terminate the operation when: 1) an unequal character comparison occurs (the magnitudes of the unequal characters are noted - see table
below), 2) all of the characters in the fields have been examined, 3) a character
in either the A or C field equals the delimiting character. RNI at P + 3 for an
unequal field comparison; RNI at P + 4 for an equal field comparison.
Comments: The count of the characters processed is placed in the B3 register
upon completion of the instruction. The following table describes the state of the
BDP Condition register when the operation is terminated:

I

Terminating Comparison Condition

RevK

Contents of BDP
Condition Register

A = C (through entire field or through
delimiting character)

00

A>C

01

AC

01

A C condition.
Edit flag indIcating a floating character is forced or compare
flag indicating C > A condition.
Operand equals zero.
Signs of operands unlike on ADM or SBM, or incorrect on
EDIT.
Interrupt occurred during BDP operation.
Number of characters or words for Field A already processed.

Comments: This instruction must be used to load recovery conditions into the
BDP before restarting a previously interrupted BDP instruction. The recovery
information must have been stored in address m by a SBR (70.7) instruction
immediately after the interrupt occurred. The LBR instruction is trapped if the
BDP MODE switch is OFF, except during Monitor state of Executive mode when
it is a No - OP.

5-167

RevK

I

I

23

I

00
70

m = storage address.
permitted.

m

Indexing not

I

This description applies to the
3312 and 3304-2 only. See
previous page for 3304-3.

I

Instruction Description: Load the BDP Condition Register and set interrupt
recovery conditions within the BDP as defined by (m). The 24 bits of (m) have
the following significance:
POSITION

I

00 and 01
02
03
04

05
06
07
08
09
10
11
12 - 23

FUNCTION
Contents of the BDP Condition Register
Edit flag indicating a (DB) or (CR) character detected.
Zero suppression operation in progress.
Edit flag indicating a floating sign ($, +, -) operation is in
progress.
Edit flag indicating a $ sign is forced.
Edit flag indicating a + sign is forced.
Edit flag indicating an sign is forced.
Edit flag indicating a floating character is forced.
Operand equals zero
Signs of operands unlike on ADM or SBM, or incorrect
on EDIT.
Interrupt occurred during BDP operation.
Number of characters of words for Field A already processed.

*

Comments: This instruction must be used to load recovery conditions into the
BDP before restarting a previously interrupted BDP instruction. The recovery
information must have been stored in address m by a SBR (70.7) instruction
immediately after the interrupt occurred. The LBR instruction is trapped if the
BDP MODE switch is OFF, except during Monitor state of Executive mode when
it is a NO - OP.
23

I
I

00
70

m = storage address.
permitted.

m

Indexing not

Instruction Description: Store various operating conditions from within the BDP
section at address 1m I. Refer to the LBR instruction for the bit functions of (m).
Comments: Execution of this instruction does not clear the operating conditions
within the BDP. This instruction is trapped if the BDP MODE switch is OFF,
except during Monitor state when it is a No-Op.

RevK

5-168

6. SOfTWARE SYSTEMS
GENERAL INFORMATION
Control Data supports its lower 3000 Series Computers with a library of excellent
standard software products effectively covering a wide range of computer
applications.
•

Operating Systems exercise supervisory control

•

Languages are oriented toward programming needs

•

Utility routines perform tasks for user's programs

•

Applications systems are specialized programs

This section briefly describes available software systems and also references
obtainable documents. To obtain these documents, refer to the Literature
Distribution Catalog for the correct Publication numbers.

OPERATING SYSTEMS
Operating systems provided by Control Data make efficient use of various hardware configurations. These operating systems provide automatic job monitoring
and supervisory control during compliation, assembly, and execution of user's
programs. Systems storage requirements are kept at a minimum and operator
intervention reduced significantly by job stacking, automatic accounting and
storage allocation, automatic assignment of input/ output functions, and by operator messages produced on the standard output comment unit. Operating systems
include the following:
.,

Real-Time SCOPE

•

MASTER

•
•

MSOS
SCOPE Utility Routines

6-1

Rev.C

Real-Time SCOPE
An operating system which provides backgrounding, stacked job processing, and
priority interrupt handling. Time is shared between a background program and
the stacked jobs. The standard SCOPE features are included: I/O and status
operations, debugging facilities, and library maintenance.
Documents
General Information
Real- Time SCOPE Operator's Manual
Real-Time SCOPE Reference

MASTER
A multiprogramming system that is adaptable to applications involving multiaccess on-line input/ output with and without real time calculations as well as to
conventional and batch processing applications. MASTER uses mass storage for
system storage and temporary storage of user programs, as well as for storage
of user files. MASTER allocates tasks to available equipment and handles
communication among tasks. The tasks are processed on a priority basis.
Documents
General Information
Reference

MSOS
Provides utilization of mass storage devices. The operating system, the related
software packages and library, and user data areas are allocated to disk or
similar storage. Time is shared between a background program and the stacked
jobs. Background programs may operate in real time. The system also includes
priority interrupt handling, I/O and status operations, debugging facilities, and
library maintenance.
Documents
General Information
MSOS Reference
MSOS Operator's Manual
PRELIB MSOS

SCOPE Utility Routines
An open- ended peripheral processing package which allows transfer of data
between peripheral units and storage media.
Documents
Reference

Rev.C

6-2

LANGUAGES
Programmers can choose the language best suited to the needs of their particular
problems. Control Data has implemented programming languages which range
from machine mnemonics to problem-oriented systems which closely resemble
the natural expressions in particular fields of application. The languages include:
e

FORTRAN

e

COBOL

e

ALGOL

e

COMPASS

e

Data Processing Package

e

Report Generator

FORTRAN-32
A versatile mathematical compiler. Most programs written in FORTRAN II and
FORTRAN IV are compilable with FORTRAN-32.
Documents
General Information
Reference
Instant- FOR TRAN
Library Routines
Library Functions

Mass Storage FORTRAN
Provides all the features of FORTRAN-32 and allows compilation and execution
using mass storage devices.
Documents
General Information
Reference
FORTRAN/MASTER
Instant FOR TRAN
Library Routines
Library Functions

COBOL 32
A data processing language based on the specifications set forth in the DOD
reference of COBOL-61. Extended. This language provides fast compilation
speeds and efficient object code.

6-3

Rev.C

Documents
General Information
Reference
Compatible COBOL
Version 2.0 Extensions and Revisions
Instant COBOL

COBOL 33
Provides all the features of COBOL 32 and utilizes the Business Data Processing
hardware during execution of the COBOL object programs.
Documents
Reference

Mass Storage COBOL
Provides all the features of COBOL 32 and uses mass storage for compilation.
Version 2 of Mass Storage COBOL contains mass storage statements and allows
object programs to use mass storage.
Documents
General Information
Reference
Version 2.0 Extensions and Revisions

ALGOL
A compiler accepting an algorithmic language defined in the ALGOL- 60 Revised
Report in the Communication of the ACM, 1963, Vol. 6. Input/output procedures
are those of the IFIP set and the complete ACM set.
Documents
General Information
Reference
Instant ALGOL
Functional Description ALGOL Compiler
Abnormal Object Time Termination Dump

COMPASS-32
A comprehensive assembly system, providing mnemonic machine operation codes,
symbolic addressing, assembly-directing pseudo instructions, and programmerdefined macro instructions.

Rev.C

6-4

Documents
General Inform a tion
Compatible COMPASS Language Reference Manual
COMPASS/Tape SCOPE COMPASS/Disk SCOPE
Programming Guide
Instant COMPASS
COMPASS/Real-Time SCOPE. COMPASS/MSOS

COMPASS-33
An extension of COMPASS-32 designed to process coding for the Control Data 3300.
Documents
Compatible COMPASS Language Reference Manual
Instant COMPASS
COMPASS/Real- Time SCOPE. COMPASS/MSOS
COMPASS/MASTER
Data Processing Package

Consists of a set of input/output and file description macro instructions. The set
also includes macros to perform certain data manipulation and mathematical
functions.
Documents
General Information
Reference
Report Generator

Facilitates the preparation of programs which produce a variety of reports from
an input file.
Documents
General Information
Reference
Instant Report

INPUT/OUTPUT
Input/ output control routines are included in the software library to provide access
to a number of different I/O media through efficiently preprogrammed library
routines.

6-5

Rev.C

1/ a control programs include:
II»

RESPOND/MSOS

..

MSIO

IIiI

SIPP

RESPOND/MSOS
A multi-access software package which operates as a background program under
MSOS and provides users at remote terminals with the ability to access files of
information contained on mass storage at the central computer site. Files may be
submitted to the operating system for foreground processing. Records within a file
may be added, deleted, modified, or displayed by action of the terminal operator.

MSIO
A file oriented input/ output system consisting of two sections. One section
provides physical I/O features for mass storage files. The other section provides
logical record processing facilities such as blocking, deblocking, buffering,
updating, inserting, and deleting for files on mass storage.

SIPP
Enables simultaneous execution of data transfer operations involving several
peripheral units. If permitted by the operating system, SIPP can operate as a
background program.
Documents
Reference

APPLICATIONS
Applications programs are tested working programs which perform specialized jobs
in industry, business, and research. Applications programs include:
GIl

.
.

PERT/TIME
PERT/COST
SORT

•

Mass Storage SORT

GIl

REGINA-I

GIl

ADAPT

Rev.C

6-6

PERT/TIME
Utilizes a time-oriented network structure to provide a variety of reports
reflecting the actual and scheduled progress of a project.
Documents
PERT General Information
Reference
Version 2.0 Extensions and Revisions
PERT/COST

Utilizes a cost-oriented breakdown structure to provide a variety of reports on
actual and estimated costs over the life of a project.
Documents
PERT General Information
Reference
SORT

Produces a sequenced file of data records from random input. The internal phase
makes use of the replacement selection sorting technique; the external phase may
be either a balanced or poly-phase merge. The user has the option to enter owncode subroutines during the program.
Documents
General Information
Reference
Mass Storage SORT

Similar to the tape SORT except that disk storage is used during intermediate
merge processing. The SORT may optionally employ a tag sorting method.
Documents
General Information
Reference
REGINA-I

A linear programming system; it provides an integer solution to the set of
equations.
Documents
General Information
Reference
6-7

Rev.C

ADAPT
A system that prepares instructions for numerically controlled machine tools.
The ADAPT language allows specification of the geometric properties of a part to
be machined and the operations involved in producing the part. ADAPT is a subset
of the more complex APT system.
Documents
General Information
Reference

Rev.C

6-8

7. CONSOLE AND POWER CONTROL PANEL

CD
CD
CD
CD

Typewriter
Typewriter Switches
Data Interchange Display
Index, or LJA, or cm
Register
CD P Register or Page Index
File Address

CD A and Q, or E Register
CD Instruction State Register
(ISR)
CD Operand State Register
(OSR)
CD F or C Register
® Status Dis play

Figure 7 -1.
7-1

(ii) ISR and OSR Entry Switches
(ii) Step Rate Control

® Emergency Off Switch
® Access Keyboard Switches
® Console Condition Switches
@

Breakpoint Switch
Assembly

3300 Console
Rev. A

GENERAL INfORMATION
The 3300 desk console shown in Figure 7-1 enables the computer operator to
control and observe computer operation. This section describes the operator's
controls and the significance of the visual indicators. Also included in this
section is a descrjption of the Power Control.Panel.

CONSOLE
The console provides an operator with visual displays to monitor the current
status of computer, controls for setting certain conditions and performing
operations, and a typewriter for direct input and output communications with the
computer. Each of these areas are described in the following pages to familiarize the operator with the functions of the console.

Register Displays
Figure 7-2 shows the display locations of the operational registers described in
Section 1. Entering data into the Communication register, Instruction State
Register, or Operand State register is described below.

Figure 7-2.

Register Display Area

Instruction and Communication Registers
The Instruction register (F register) and Communication register (C register)
share the same display area on the console. The F register is displayed when
the access keyboard switches are inactive and the computer is not in the GO
mode. The C register is displayed when data is being entered via the access
keyboard switches.
Data entered into the A or Q registers must first pass through the Communication register. Starting with the uppermost digit, data is entered into the
Communication register by first depressing a register switch and then depre ssing the numeric keyboard switches. A blue Active Digit indicator light is
superimposed on each digit position of the Communicati~n refister as digit
entry progresses. When data is entered into the Bl, B , B , or P registers, the Active Digit indicator automatically starts at the fifth digit position of
the Communication register.

Rev. A

7-2

Depressing the TRANSFER switch causes the data to be transferred from the
Communication register to the designated register. Immediately depressing the
TRANSFER switch again results in transferring all zeros to the register.

Instruction State and Operand State Registers
The contents of the ISR or OSR may be changed by first clearing the register(s}
and then depressing binary position switches to form the desired octal number.
The switches may be depressed simultaneously or individually. The white
register clearing switch and blue binary position switches are shown in Figure
7-3.

Figure 7-3.

ISR and OSR Display and Binary Entry Switches

Data Interchange Display
The Data Interchange Display, shown in Figure 7-4, enables the console operator
to determine the status of each of the eight I/O channels (0 through 7). Each
channel has its own set of Input, Output, Reject, Interrupt,and Parity Error
indicators. Transient conditions may not be seen on the display due to the response time of the indicators.

Figure 7-4.

Data Interchange Display

7-3

Rev. A

TABLE 7-1.

DATA INTERCHANGE INDICATOR DESCRIPTIONS

INDICATOR
NAME
INPUT

FUNCTION
Glows when data is being received by the computer on the
channel indicated.

OUTPUT

Glows when data is being transmitted by the computer on the
channel indicated.

REJECT

Glows when a Reject signal is received from a peripheral
equipment on the channel indicated.

INTERRUPT

Glows when an Interrupt is received from a peripheral
equipment on the channel indicated. Indicator glows until
the interrupting condition is cleared.

PARITY
ERROR

Glows when a transmission parity error has occurred on the
channel indicated. Indicator glows until the condition is
recognized.

Status Display
The Status Display provides the operator with visual indications of the internal
status of the computer. Operating status, fault conditions, and physical malfunctions are the general status areas associated with the Status Display indicators. Figure 7-5 shows the arrangement of the indicators on the Status
Display and the function of each indicator is described in Table 7-2.

Figure 7- 5.
Rev. A

Status Display
7-4

TABLE 7-2.

STATUS DISPLAY INDICATOR DESCRIPTIONS

INDICATOR
NAME

FUNCTION
Indicator is

STORAGE
ACTIVE

Indicates a storage reference is in progress.
common to all storage modules.

MONITOR
STATE

Indicates the computer is operating in the Monitor State of
Executive mode.

PROGRAM
STATE

Indicates the computer is operating in the Program State of
Executive mode.

INTERRUPT
ENABLED

Indicates the interrupt system has been enabled by executing
an EINT (77.74) instruction.

READ NEXT
INSTRUCTION

Indicates the computer is reading the next instruction of the
program it is currently executing. Usually referred to as
the RNI cycle.

READ
ADDRESS

Indicates the computer is reading the lower 18 bits at a
storage location to form a new address for indirect addressing. Usually referred to as the RADR cycle.

READ
OPERAND

Indicates the computer is reading a 24-bit operand from
storage for use with the instruction being executed. Usually
referred to as the ROP cycle.

STORE
OPERAND

Indicates the computer is storing a 24-bit operand that has
been previously processed into a selected storage module.
Usually referred to as the STO cycle.

TEMP
WARNING

Indicates the temperature within the computer is abnormally
high and is at least 80 0 F.

ARITHMETIC
OVERFLOW

DIVIDE
FAULT

EXPONENT
FAULT

Indicates the capacity of the adder has been exceeded. Its
capacity, including sign, is 24 or 48 bits for 24-bit precision or 48- bit precision, respectively.
The divide fault indicates a quotient, including sign, exceeds
24 or 48 bits for 24-bit precision or 48- bit precision,
re spectively. Therefore, attempts to divide by too small a
number, including positive and negative zero, result in a
divide fault. During floating point division, a divide fault
occurs if division by zero or by a number that is not in
floating point format is attempted. If the divisor is not
properly normalized a divide fault may also occur. Refer to
Appendix B for a description of normalization.
Indicate s either an exponent overflow (> + 17778) or an exponent underflow « - 1 7778) has occurred during a floating
point arithmetic operation.
(Continued)

7- 5

Rev. A

TABLE 7-2.

STATUS DISPLAY INDICATOR DESCRIPTIONS (Cont'd)

INDICATOR
NAME

FUNCTION

BCD
FAULT

Indicates a BCD fault has occurred within the BDP module
or a SB CD (77.72) instruction has been executed. Refer
to Section 4, Interrupt System, for additional information.

ILLEGAL
WRITE

Indicates an attempt has been made to write into a protected storage location or read from certain locations
while operating in Executive mode. Refer to Section 4,
Interrupt System, for additional information.

PARITY
ERROR

Indicates a parity error occurred during a memory
reference. Transmission parity errors do not affect this
indicator.

TERMINATOR
FAULT

Indicates that the internal terminator power supplies are
not functioning properly.

CIRCUIT
BREAKER

Indicates that one or more of the power system circuit
breakers are open.
If the TEMP WARNING indicators are glowing and an
absolute temperature of 110 0 F is exceeded, the computer

TEMP
HIGH

automatically shuts off logic power. The TEMP RIG H
indicator for the particular computer section continues
to glow until the temperature drops below the absolute
limit. Secondary power must be manually reapplied before
normal operation can resume.

Switches and Controls
Condition Switches
The condition switches are used mainly to set various operating and programming conditions. These 24 switches are located on both sides of the access
keyboard switches and are shown in Figure 7-6 and described in Table 7-3.
The typewriter control switches, located on the extreme left side of the console
are described later in this Section.

Rev. A

7-6

Figure 7 - 6.
TABLE 7-3.

Condition Switche s

CONDITION SWITCHES DESCRIPTION

SWITCH
NAME
SELECT
JUMP (1-6)

FUNCTION
Switche s are actuated in accordance with programs
utilizing the Selective Jump instruction (SJ 1- 6 OOj).

SELECT
STOP

Stops the computer when the SLS (77.70) instruction is read.
When the computer enters the GO mode again, the program
re surne s with the next instruction.

PARITY
STOP

Causes the computer to halt when a storage parity error is
detected.

PARITY
INTERRUPT

Causes the computer to process the interrupt subroutine
when a storage parity error is detected. Refer to Section
4, Interrupt System, for additional information.

EXECUTIVE
MODE

Permits the computer to operate in the Executive mode.
Initial state of Executive mode is always the Monitor State.
Reactuating this switch permits the computer to operate in
the non-Executive mode.
If the computer has been Master Cleared and the AUTO LOAD

AUTO
LOAD

AUTO
DUMP

switch is actuated, the computer automatically jumps to
address 77740 if in the non-Executive mode or address
003700 in Executive mode and executes the instruction stored
there. Refer to Auto Load/Auto Dump in Section 3.
This switch performs the same function as the AUTO LOAD
switch with the exception of jumping to address 77760 if in
the non-Executive mode or address 003740 in Executive
mode.
(Continued)

7-7

Rev. A

TABLE 7-3.

CONDITION SWITCHES DESCRIPTION (Cont'd)

SWITCH
NAME
BDP MODE
(Business
Data
Processor)
AUTO
STEP

FUNCTION
Actuating this switch with the BDP module in the system
permits the BDP to directly execute the business oriented
instructions. If the switch is not On, thes e instructions are
trapped. Refer to Section 5, Instructions, for a list of the
BDP instructions.
Permits instructions to be executed in a slow speed GO
mode. The speed (3 to 50 instructions per second) is regulated by a variable Step Rate control on the Upper Console
Switch Panel.

STORAGE
CYCLE STEP

Enables the operator to step through an instruction one
storage cycle at a time, i. e., RNI, RADR, ROP, or STO.

INSTRUCTION
STEP

Enable s the operator to execute a program, instruction by
instruction. One instruction is executed each time the
switch is pressed.

THERMOSTAT
BY PASS

Allows computation to proceed regardless of abnormal
temperatures within the computer.

DISABLE
STO PROTECT
ENTER AUTO
PROGRAM
LJA
(Last Jump
Address)
CHANNEL
INDEX REG
(Channel Index
Register)

Disables the protection feature of the 15 storage protect
switches. This f;3witch has .no effect on the protected
Auto Load and Auto Dump or program protected storage
areas.
Allows the operator to enter the Auto Load and Auto Dump
storage areas with different data.
Actuating this momentary switch when the conputer is
stoppe·d causes the storage address of the last jump
instruction to be displayed on the console.
Pressing this switch when the computer is stopped causes
the contents of the 3-bit Channel Index register to be displayed.

DISABLE
ADVANCE P

Prevents the P register from being incremented. When the
GO switch on the keyboard is pressed, the same instruction
is repeatedly executed.

MANUAL
INTERRUPT

Forces the computer into an interrupt routine if the computer is in the GO mode. If the computer is stopped when
the switch is pressed, it goes into an interrupt routine as
soon as the GO switch is pressed.

INTERNAL
CLEAR

Master clears internal conditions and registers.

EXTERNAL
CLEAR

Master clears all external equipments and the I/O
channels.

Rev. A

7-8

Access Keyboard
Figure 7-7 shows the access keyboard switches, used for manually entering
and retrieving data from the computer and controlling its operation. Table 7-4
describes the individual keyboard switch functions.
Upper Console Switch Panel
The upper console switch panel shown in Figure 7-8 is used for:
e

Selecting Index register Bl, B2, or B3 for display

e

Operating the Breakpoint switch

e

Entering data into the ISR or OSR

4&

Adjusting the Step Rate control

4&

Immediately removing computer power in the event of an
emergency by depressing the EMERGENCY OFF switch

The Index register switches on the access keyboard are used for entering data.
To display one of the three index registers, the appropriate upper console index
register switchmustbe depressed. A complete description of the Breakpoint switch
follows the access keyboard switch descriptions.

Figure 7-7.

Access Keyboard Switches

7-9

Rev. A

Figure 7-8.

TABLE 7-4.

Upper Console Switch Panel

ACCESS KEYBOARD SWITCHES

SWITCH
NAME

FUNCTIONS

A

Cause s both A and Q to be displayed, but permits entry
only into A.

Q

Causes both A and Q to be displayed, but permits entry
only into Q.

E

Causes EU and EL to be displayed.
possible.

P

Enables an address to be manually entered from the keyboard into the P re gister.

B1, B2, or B3

Enable s data to be manually entered into Index registers
B1, B2, or B3 from the keyboard. Appropriate Index
register switch on the upper console switch panel must be
depressed for register display.

EN
(ENTER)

Permits data to be manually entered into storage while the
computer is stopped. First address of sequence must be
previously entered into P. Pressing the TRANSFER
switch advances P.

ENTER
PF

SW
(SWEEP)
SWEEP
PF
SW/EN
CONT
(SWEEP / ENTER

Permits data to be manually entered into the Page Index
File while the computer is stopped. First address of
sequence must be previously entered into the lower 7 bits
of the P register.
Permits unexecuted instructions to be read from consecutive storage locations. First address of sequence must be
previously entered into P. Pressing the TRANSFER switch
advances P.
Permits page indexes to be read from consecutive Page
Index File locations. First address of sequence must be
previously entered into the lower 7 bits of the P register.
Enables Sweep or Enter operations to proceed continuously
through storage or the Page Index File without pressing the
TRANSFER switch.

CONTINUOUS)
Rev. A

Manual entry is not

7-10

TABLE 7-4.
SWITCH
NAME

ACCESS KEYBOARD SWITCHES (Cont'd)

FUNCTION
Permits keyboard entry into the storage location specified
by the thumb-wheel switches. Entry occurs each time the
TRANSFER switch is pressed whether the computer is in
the GO mode or stopped.

WRITE STO
(WRITE
STORAGE)

Permits the contents of the storage register location
READ
specified by the thumb-wheel switches to be displayed.
STO
(READ STORAGE) display rate is determined by the Step Rate control.

The

GO

Starts the program execution at the addre ss specified by
the P register. Not used for Sweep or Enter operations.

STOP

Stops the computer at the end of the current instruction.

o THROUGH

7

TRANSFER

These switches, when pressed one at a time, allow entry
of that particular digit into the Communication register.
Transfers data in the Communication register to a selected
register or storage location.

Performs both an internal and external clear. Disabled
MC
When GO switch is depressed and the computer is in the
(MASTER CLEAR)
GO mode.
KYBD CLR
(KEYBOARD
CLEAR)
KYBD
OFF
(KEYBOARD
OFF)

Clears the Communication register.

Deactivates all access Keyboard controls.

Breakpoint Switch
The Breakpoint switch is a six-section, eight-position, thumb-wheel switch ..
The left-hand wheel selects the operating mode, and the other five wheels
specify a register number or storage address. There are four mode positions
on the mode selector switch with an OFF position between each mode; these
mode s are BPI, BPO, REG, and STO.
BPI and BPO Modes: The address on the S Bus is continually compared with
the instruction or operand address specified by the Breakpoint digit switches.
When the selector switch is set to BPI, the computer stops if these values become equal during an RNI (Read Next Instruction) sequence. When the mode
selector switch is set to BPO, the computer stop s if the se value s become equal
during an ROP (Read Operand) or STO (Store) sequence.

7-11

Rev. A

REG and STO Modes: In these two modes, the operator may either monitor the
contents of a register location or storage address specified by the thumb-wheel
digit switches, or he may store a word in these locations. To monitor a storage
location:
•

Set the mode selector to REG (register file location) or STO (storage).

•

Set the Breakpoint switch to the desired register number or storage
address.

•

Press the READ STO switch on the keyboard.

•

Adjust the Step Rate control to vary the display rate.

The register or storage contents are repeatedly displayed in the Communication
register at the selected- repetition rate until another keyboard button is pressed
to release READ STO. To write a word in storage:
.,

Set the mode selector to REG or STO.

tt

Set the Breakpoint switch to the desired register number or storage
location.

•

Press the WRITE STO switch on the keyboard.

CD

Enter data into the Communication register by depressing the numeric
switche s and finally the TRANSFER switch.

The data is entered into the desired storage location or Register File location
at the end of the instruction that is currently being executed by the computer.
Pressing any other register or mode selector switch releases WRITE STO
operation.
Emergency Off Switch
This red momentary switch is used to remove power from the whole computer
system in case of a fire or other emergency. It should not be used for a normal
POnler shutdown. Refer to the SOURCE POWER OFF switch description in the
Power Control Panel description of this section.
Console Loudppeaker Volume Control
The console loudspeaker and its associated volume control are mounted underneath the console table. The loudspeaker receives its input from the upper 3 bits
of the A register.
Sound is produced when one or more of these bits are toggled
at an audio frequency. Loudspeaker volume is controlled by rotating the volume
control knob.
Examples of Keyboard Switch Functions:
1.

To enter data into the A register:
a.

Rev. A

Depress the A register switch.

7-12

2.

b.

Enter all eight digits of the Communication register by depressing
the appropriate numeric key switches. ;"

c.

Depress the TRANSFER switch.

d.

Depress the KEYBOARD OFF switch.

To enter data into the Q register:
Depress the Q register switch and repeat steps b through d
of example 1.

3.

4.

5.

To enter the Program Address Counter (P register) with a
specific address:
a.

Depre ss the P register switch.

b.

Enter the lower five digits of the Communication register by
depressing the appropriate numeric key switches.

c.

Depress the TRANSFER switch.

d.

Depress the KEYBOARD OFF switch.

To enter an operand at a specific address:**
a.

Perform example 3.

b.

Depress the EN switch.

c.

Enter all eight digits of the Communication register by
depressing the appropriate numeric key switches.

d.

Depress the TRANSFER switch.

e.

The count in the Program Address Counter has now incremented by one. If data is to be entered into this memory
location, repeat steps c and d for as many succeeding
entries as required.

f.

Depress the KEYBOARD OFF switch when all data has
been entered into the successive group of memory
locations.

To read an operand from a specific storage addre ss:
a.

Perform example 3.

b.

Depress the SW switch.

c.

Depress the TRANSFER switch.

d.

The contents of the specified storage address are now displayed
in the Communication register. (The Program Address Counter
is not incremented when the TRANSFER switch is initially
depressed. )

':'If all eight digit positions of the Communication register are not entered
before the Transfer switch is depressed, zeros will be entered into the
remaining digit positions.
':":'The Breakpoint switch may be used in lieu of this operation. (Refer to
Example d, Figure 7-9.)

7-13

Rev. A

e.

If the TRANSFER switch is again depressed, the Program
Address Counter is incremented by one, and the contents of
the new address are displayed.

f.

Depress the KEYBOARD OFF switch when all of the desired
memory locations within a successive group have been
examined.
NOTE
Step 5 only permits the operator to examine
the contents of specific storage locations.
The instructions are not executed during
this operation.

6.

7.

8.

9.

Rev. A

To enter zeros or another operand into all storage locations:
a.

Depre ss the EN switch.

b.

Enter all eight digits of the Communication register by
depressing the appropriate numeric key switches.

c.

Depress the SW/EN CONT switch.

d.

Depress the STOP switch.

e.

Depress the KEYBOARD OFF switch.

The following procedure is applicable for sweeping storage during
certain maintenance routines:
a.

Depress the SW switch.

b.

Depress the SW/EN CONT switch. This switch remains
engaged until the STOP switch is depressed.

c.

Depress the STOP switch.

d.

Depress the KEYBOARD OFF switch.

To enter a 12-bit operand into a specific Page Index File (PIF)
address:
.
a.

Set P to a specific PIF address (000-177) as outlined in
example 3. (Only the lower 7-bits of P are recognized.)

b.

Depress the ENTER PF switch.

c.

Enter the lower four digits of the Communication register by
depressing the appropriate numeric key switches.

d.

Depress the TRANSFER switch.

e.

The PIF address in the Program Address Counter has now
incremented by one. If data is to be entered into this PIF
location, repeat steps c and d for as many succeeding
entries as required.

f.

Depress the KEYBOARD OFF switch when all data has been
entered into the successive group of PIF locations.

To read an index from the PIF:
a.

Perform step a

of example 8.

b.

Depress the SWEEP PF switch
7-14

10.

11.

c.

Depress the TRANSFER switch.

d.

The specified index of the PIF is now displayed in the lower
12-bits of the Communication register. (The Program Address
Counter is not incremented when the TRANSFER switch is
initially depressed.)

e.

If the TRANSFER switch is again depressed, the Program
Address Counter is incremented by one and the index of the
new PIF address is displayed.

f.

Depress the KEYBOARD OFF switch when all of the desired
indexes within a successive group have been examined.

To enter zeros or another operand into all indexes of the PIF:
a.

Depress the ENTER PF switch

b.

Enter the lower four digits of the Communication register by
depressing the appropriate numeric key switches.

c.

Depress the SW/EN CO NT switch. This switch remains
engaged until the STOP switch is depressed.

d.

Depress the KEYBOARD OFF switch.

The following procedure is applicable for sweeping all indexe s of
the PIF during certain maintenance routine s:
a.

Depre ss the SWEEP PF switch

b.

Depress the SW/EN CONT switch. This switch remains
engaged until the STOP switch is depressed.

c.

Depress the STOP switch.

d.

Depress the KEYBOARD OFF switch.

Examples of Console Switch Functions:
1.

To enter a special routine into the non-Executive mode Auto Load
storage area:
a.

Depress the MC (Master Clear) keyboard switch.

b.

Holding down the keyboard STOP switch, depress the AUTO
LOAD switch. Release both switches. The P register should
now read 77740. (Holding the STOP switch down prevents the
computer from entering the GO mode and executing the previous Auto Load routine. )

c.

Depress the ENTER AUTO PROGRAM switch.

d.

Depress the keyboard EN switch.

e.

Enter the fir st instruction of the new routine at addre s s
77740 by depressing the appropriate numeric key switches.

f.

Depress the keyboard TRANSFER switch.

g.

Repeat steps e and f for addresses 77741 through 77757.

h.

Depress the MC switch. This clears the registers and cancels
the ENTER AUTO PROGRAM function.
7-15

Rev. A

i.

2.

Depress the KEYBOARD OFF switch.

To enter a special routine into the non-Executive mode
Auto Dump storage area:
Repeat steps a through i of example 1 using the AUTO DUMP
switch and filling the storage area covered by addresses 77760
through 77777.

3.

4.

To execute the Auto Load routine:
a.

Depress the keyboard Me switch.

b.

Depress the AUTO LOAD switch. The computer automatically
executes the Auto Load routine and stops when a stop or halt
instruction is recognized. The Auto Load function is automatically cleared when the first I/O operation is completed.

To execute the Auto Dump routine:
Perform steps a and b in example 3 but use the AUTO DUMP
switch instead of the AUTO LOAD switch.

5.

To execute a program at a Auto Step rate:
a.

Set the P register to the first address of the program to be
executed.

b.

Depress the AUTO STEP switch.

c.

Adjust the STEP RATE display control.

d.

Depress the AUTO STEP switch again to cancel the function
and stop program execution. The only way to exit from the
Auto Step mode is to depress the AUTO STEP switch again.
In the Auto Step mode, halt and jump instructions are
executed,but the computer does not stop. Neither will program
execution be affected by depre ssing the STOP switch. The
computer continues cycling through memory until the AUTO
STEP switch is again depressed.
NOTE
To load or execute a subroutine in the Auto
Load or Auto Dump areas while in Executive
mode, perform the same operations as for
non-Executive mode except that the addresses
for the respective areas will be as follows:

Rev. A

Auto Load:

003700 through 003737

Auto Dump:

003740 through 003777

7-16

EXAMPLE B

EXAMPLE A

The Breakpoint switch is inoperative
whenever an OFF designator is displayed. An OFF designator separate s the REG, STO, BPI and BPO
positions.

During the normal execution of a
program, the computer stops when
an RNI is attempted at memory location 05443. A jump to this location also causes the computer to stop.
H the program reference s memory
location 05443 for an operand, the
computer ignores the Breakpoint
switch.

EXAMPLE C

EXAMPLE D

The computer stops only when an
attempt is made to read or store an
operand at address 00413.

Figure 7 - 9.

If the WRITE STO switch on the keyboard is depressed and data has been
entered into the Communication register, the data is transferred to
memory location 00104 when the
TRANSFER switch is depressed.

Breakpoint Switch Example s

7-17

Rev. A

EXAMPLE E

EXAMPLE F

If the WRITE STO switch on the
keyboard is depressed and data has
been entered into the Communication register, the data will be
transferred to register 77 when the
TRANSFER switch is depressed.
(Only the lower two digits are recognized when the designator switch
is in the REG position. The programmer must use caution when
writing into the Register File to
prevent destruction of other data.
Refer to Section 1, Table 1- 3. )

If the READ STO switch on the keyboard is depressed, the contents of
memory location 27004 are displayed
in the Communication register at a repetition rate determined by the Step
Rate control. (If the memory location
depicted by the Breakpoint switch exceeds the storage capacity of the system, the computer selects the address
that corresponds to the storage capacity of the system.)

EXAMPLE G

If the READ STO switch on the keyboard is depressed, the contents of
register 22 are displayed in the
Communication register at a repetition rate determined by the Step
Rate control. (Only the lower two
digits are of consequence when the
REG de signator is displayed. In
this case register 22, the real time
clock, is being referenced.)

Figure 7-9.
Rev. A

Breakpoint Switch Examples (Cont'd)
7-18

Typewriter
The console typewriter is an on -line inputloutput (I/O) device; i. e. , it require s
no connection to a communication channel and no function codes are issued. The
typewriter receives output data directly from storage via the lower 6 bits of the
Data Bus. Inputs to storage are handled in the same manner.
Used in conjunction with Block Control and the Register File, the typewriter may
be used to enter a block of internal binary-coded characters into storage and to
print out data from storage. The two storage addresses that define the limits of
the block must be stored in the register file prior to an input or output operation.
Register 23 contains the program state number and the initial character address
of the block. Register 33 contains the last character address, plus one {refer to
Section 1, Table 1-1 notes for Registers 23 and 33 operand formats}. Because
the initial character address is incremented for each storage reference, it always
shows the address of the character currently being stored or dumped. Output
operations occur at the rate of 15 characters per second. Input operations are
limited by the operator1s typing speed.
The console tyoewriter control switche s are shown in Figure 7 -1 0 and their
functions are described in Table 7-5.

Figure 7-10.

Console Typewriter Control Switches
7 -19

Rev. A

The general order of events when using the console typewriter for an input or
output operation is:
•

Check status

•

Set registers 23 and 33 of the Register File to the appropriate
addresses

•

Set tabs, margins and spacing; turn on typewriter

•
•

Clear
Type out or type in

Status Checking
The programmer may wish {o check the status of the typewriter before proceeding. This is done with the Pause instruction. Status response is returned
to the computer via two status lines.
The typewriter control transmits two status signals that are checked by the Busy
Comparison Mask using the Pause instruction. These status signals are:
Bit 09

Type Finish

Bit 10

Type Repeat

An additional status bit appears on sense line 08. This code is Type Busy and
is transmitted by block control in the computation section when a typewriter
operation has been selected. If the programmer is certain of the status of the
typewriter, this operation may be omitted.
Set Registers 23 and 33
Registers 23 and 33 define the limits of the typewriter I/O operation. These
registers are set by instruction or by entering the registers via the Breakpoint
switch.
Set Tabs, Margins, and Spacing
All tabs, margins, and paper spacing must be set manually prior to the input or
output operation. A tab may be set for each space on the typewriter between
margins.
Clear
There are three types of Clears which may be used to clear all conditions (except Encode Function) existing in the typewriter control. The se are:
•

Internal Clear or a Master Clear
This signal clears the typewriter control and sets the typewriter to lower case.

Rev. A

7-20

TABLE 7-5.
SWITCH

ENCODE
FUNCTION

TYPE
LOAD

TYPE
DUMP

REPEAT

CONSOLE TYPEWRITER SWITCHES AND INDICATORS
SWITCH (S)
INDICA TOR (I)

FUNCTION

S/I

This switch enables the typewriter to send
to storage the special function codes for
backspace, tab, carriage return, uppercase shift, and lower-case shift.

S!I

This switch allows the computer to receive
a block of input data from the typewriter.
The TYPE LOAD indicator remains on until
either the FINISH, REPEAT, or CLEAR button is pressed, or until the last character of
the block has been stored. If the program
immediately reactivates the typewriter, it
may appear that the light does not go off.

S/I

This switch causes the computer to send
data to the typewriter for print-out. lt is a
momentary contact switch that is illuminated
until the last character in the block has been
printed or the CLEAR button is pressed.

S!I

This switch is pressed during a Type Load
operation to indicate that a typing error
occurred. This switch deactivates busy
sense line 10 (see PAUS instruction). If
the computer does not respond, this light
remains on.

FINISH

S/ I

CLEAR

S/I

This switch is pressed during a Type Load
operation to indicate that there is no more
data in the current block. This action is
necessary if the block that the operator
has entered is smaller than the block defined by registers 23 and 33. This switch
also deactivates busy sense line 09. If the
computer does not respond, this light
remains on.
This switch clears the typewriter controls
and sets the typewriter to lower case but
does not cancel the ENCODE FUNCTION
switch.

7-21

Rev. A

•

Clear Channel, Search/Move Control, or Type Control
instruction (77.51).
This instruction selectively clears a channel, the S/M control,
or, by placing a "I" in bit 08 of the instruction, the typewriter
control, and sets the typewriter to lower case.

•

Clear Switch on Typewriter
This switch clears the typewriter control and sets the
typewriter to lower case.

Type In and Type Load
Executing the CTI (77.75) instruction or pressing the TYPE LOAD switch on the
console or typewriter permits the operator to enter data directly into storage
from the typewriter. When the TYPE LOAD indicator on the console glows, the
operator may begin typing. The Encode Function switch must be depressed to
enable backspace, tab, carriage return, and case shifts to be transmitted to the
computer during a typewriter input operation.
Input is in character mode only. As each character is typed, the information
is transmitted via the Data Bus to the storage address specified by block control.
This address is incremented as characters are transmitted. When the current
address equals the terminating address, the TYPE LOAD indicator goes off and
the Jperation is terminated. Data is lost if the operator continues typing after
the TYPE LOAD indicator goes off.
Type Out and Type Dump
The typewriter begins to type out when the computation section executes aCTO
(77.76) instruction,or when the operator presses the TYPE DUMP switch on the
console. Single 6-bit characters are sent from storage to the typewriter via the
lower 6 bits of the Data Bus. When the current address equals the terminating
address, the TYPE DUMP indicator goes off and the operation is terminated.
During a Type Out operation, the keyboard is locked to prevent loss of data in
the event a key is accidentally pre ssed.
Table 7-6 lists the internal BCD codes, typewriter printout and upper-or lowercase shift that applies to the console typewriter. All character transmission
between the computation section and the typewriter is in the form of internal
BCD. The typewriter logic makes the necessary conversion to the machine
code.

Rev. A

7 -22

NOTE
Shifting to upper case (57) or lower case (32)
is not necessary except on keyboard letters
where both upper and lower cases are available. The standard type set has two sets of
upper case letters and no lower case letters.
This eliminates the need for specifying a
case shift.
TABLE 7 - 6.

PRINTOUT
0
1
2
3
4
5
6
7
8
9
±
=
II

:
;
?

+
A
B
C
D
E
F
G
H

I
(Shift to LC)
)
I

@

!

*L

CASE
L*
L
L
L
L
L
L
L
L
L
U*
L
U
U
L
U
U
U or
U or
U or
U or
U or
U or
U or
U or
U or

CONSOLE TYPEWRITER CODES

PRINTOUT

INTERNAL
BCD CODE

-

00
01
02
03
04
05
06
07
10
11

L
L
L
L
L
L
L
L
L

U and L
U
L
U
L

12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

J
K
L
M
N
0

P
Q

R
o (degree)

$
-'.,.

#
0/0

CASE
L
U
U
U
U
U
U
U
U
U
U
U
U
U
U

or
or
or
or
or
or
or
or
or

L
L
L
L
L
L
L
L
L

(Shift to UC)
(Space)

/
S
T
U
V
W
X
Y
Z
&

,
(

(Tab)
(Backspace)
(Carriage
Return)

L
U or L
U or L
U or L
U or L
U or L
U or L
U or L
U or L
U
Uand L
U

INTERNAL
BCD CODE
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77

= Lower Case; U = Upper Case

7-23

Rev. A

POWER CONTROL PANEL
The Power Control Panel module shown in Figure 7-11 controls the logic power
supplied to the CPU and the first I/O module. Adjusting the +20 and -20 controls for 00/0 indication on. their respective meters provides exactly the proper
operating power. The following illustration shows which part of the computer
the Compute One and Compute Two controls govern.

r- -

-

-

I

I

FLOATING
POINT
MODULE

CPU

I
I
I

I/O

I/O

MODULE

MODULE

L __ _

....I
'------,vr----J{\\...----'v,...------POWER
POWER
CONTROLLED
CONTROLLED
BY

COMPUTE

BY

2

COMPUTE

The two main circuit breakers must both be On before the system CPU is
operative. Refer to the 3300 Customer Engineering manual for detailed maintenance information.

Elapsed Time Meters
Two elapsed time meters and a key-operated, two-position switch are located
on the control panel. Turning the key-operated Maintenance Mode switch to ON
connects the Maintenance Time meter to the computer to record the amount of
time the computer is used during a maintenance period. Removing the key connects the Operating Time meter to the computer to record normal operating
time. Customer s renting the computer are often billed according to the time
recorded on this meter. The sum of the times recorded on both meters indicates the total computer running time. Only one of the two meters can operate
at anyone time. Either meter is active for a minimum of one second when a
storage cycle occurs.

Storage Protect Switches
The 15 Storage protect switches are described in Section 2.

Rev. A

7-24

STORAGE ADDRESS pr:.:OT~£C::.:TI::O":.:S:::Wi:::TC:::H:::ES~_ _ _ _ _~1

j

\'it.
:ttI .fl;
!
I.

13

I~

~

\1) @ \:{t;

11

•

OP£ltATING
TIME

Figure 7-11.

In

9

•

~!!)
~

G

MAINTENANCE
MDOE

till \if; (iJ. ~'fi!l
,

,

1

2

I

\~
II

I

•

MAINTENANCE
TIM<

Power Control Panel

7-25

Rev. A

8.

MULTIPROGRAMMING

I

AND RELOCATION fEATURES

Multiprogramming in the 3300 Computer System enables the instructions of
many programs to be sequentially executed by controlled time-sharing
operations within a processor. With the Control Data Multiprogramming
Modules, throughput is very high due to efficient use of hardware and optimum
program scheduling. This feature is very desirable at installations where
numerous jobs are run and computing time must be kept at a minimum. Systems
equipped with the relocation feature can compute many programs on a timeshared basis or be switched into the non-Executive mode and process jobs
according to control card job assignments.

EXECUTIVE

MODE

A system equipped with relocation hardware and operating in the Executive
Mode functions in either the Monitor State or the Program State.
Monitor

State

The Monitor State is the initial operating state of a master cleared processor.
The processor also reverts to this state if interrupted for any condition. All
instructions may be executed in the Monitor State.
Program

State

The Program State permits all but the following instructions to be executed:
1.

A Halt instruction (00.0)

2.

Any of the instructions with function codes in the 71-77 range including
the DCS, except the SFPF (77.71) and SECD (77.72) instructions.

3.

An inter-register transfer instruction that attempts to alter registers
00 through 37 of the register file.

8-1

Rev K

I

If an attempt to execute one of these instructions occurs, an Executive interrupt

is generated and operating control is transferred back to the Monitor State. The
Executive interrupt is not masked and the interrupt system need not be enabled
to recognize the interrupt when it occurs. Upon recognition, the Executive
interrupt transfers program control to the Monitor State. The instruction that
caused the interrupt is not executed. The following flow chart describes the
sequence of events involved when an Executive Interrupt occurs.

EXECUTIVE

INTERRUPT

SEQUENCE

Attempt is made to execute an instruction at
Address P, that will cause an Executive Interrupt.

1
1

Program control is transferred to the Monitor State.

Address P is stored in the lower 15 bits of address
000004 of the Monitor State.

1

Interrupt code 0120 is stored in the lower 12 bits of
address 000005 of the Monitor State.

1

Instruction at address 000005 of the Monitor State is
executed.

MULTIPROGRAMMING

AND

RELOCATION

If the 3311 Multiprogramming option is not present in a 3300 system, the maximum
number of MCS words is 131,072. The actual addre ss referenced is as follows:
17 BIT ADDRESS

I
0100

(ISR)~[

rn
, ,

"
14

\
00

'I- - - - ( - P - )- - - - ,

: OR :

tll DO'

(OSR)~[rn

I

i:

OR :
~'OO"1

Refer to Table 8 -1 for conditions
when (ISR), (OSR), or zero is
appended to address Po

I
Upper Bit of ISR

or OSR is ignored

I Rev K

8-2

If the APF (77.64) or PFA (77.65) instructions are executed they become no-

operation instructions when the 3311 is not present. The keyboard sweep and enter
functions with the Page Index File are also disabled. All other operating conditions
are the same whether or not the 3311 is in the system.
A 3300 CPU can access up to 262,144 words of core storage when the 3311
Multiprogramming option and appropriate storage modules are present in the
system. This is accomplished by augmenting the basic 15-bit address P with a
3-bit state number. The state number,along with a portion of the 15-bit address,
becomes the direction path into a relocation path. From the Page Index File the
correct page address is obtained for actual memory addressing.
Page

Structure

Each page of memory is assigned 2,048 absolute memory locations. A fully
expanded system contains 128 of these pages. Individual pages may be subdivided into four partial pages. A 1/4 page consists of 512 address locations.
Programs may be allocated full pages, 3/4 page, 1/2 page or 1/4 page of
memory.
To facilitiate addressing with the paging scheme, a word organized core
matrix is used. This core matrix, called the Page Index File, is referenced
by a program during a memory reference to obtain the physical page address
or partial page address and provide memory protection.
Address

Relocation

Figure 8-1 illustrates address bits at various stages of the relocation process.
Those portions of the diagram accompanied by circled numbers are further
described in the following numbered paragraphs.

CD

,

Program Address and Program Address Group

Any program executed by a 3300 is processed within the confines of a 15-bit
program address structure. These 15 bits define the program or operand
address related to the routine or subroutine being processed at a given instant.
Figures 8-2 and 8. - 3 illustrate the significance of these bits in the instruction
words for both word addressing and character addressing.
The 15 bits used in word addressing define an absolute address assignment
ranging from 00000 to 77777 8 , Any program or group of programs within this
range of addresses which can be compiled and loaded without conflicting addresses can be considered part of a program address group. Figure 8-4 is
illustrative of a program address group consisting of five non-conflicting
programs.

8-3

RevK

I

I

I

7-BIT
PAGE FILE
ADDRESS
(INPUT)
UPPER 3
ADDRESS
BITS

I

® {0!2Ittt
::II::

FROM ISR,OSR,
OR REG FILE

::::::::::::

I BIT'--+f::PI
PAGE
LENGTH
CONTROL

2 BI

®
PAGE
INDEX
FILE

ILLEGAL WRITE

12 BIT
PAGE INDEX
(OUTPUT)

7BI

00:':;::;::
2 BITC> ..........I::Dc:l----l_

@
IS-BIT
RELOCATED
MEMORY
ADDRESS
PROGRAM
ADDRESS

(REF TO TEXT FOR
ADDITIONAL INFORMATION
ON NUMBER AREAS)

RELATIVE BIT POSITION

I

\RevK

Figure 8-1.

Address Relocation Process

8-4

A program address group may be considered apart from the physical memory
structure since it is a group of sequentially numbered addresses representing
one or more programs within 32,768 words of storage and not a discrete
physical device. Many program address groups may be contained in storage; however, eight such groups are used in the 3300 to best optimize the memory system.

23

18 17
FUNCTION
CODE

II+---

6 BITS

15 14

I

--*- 3

00
WORD
ADDRESS

I

~E

15 BITS

I

~I

BITS

Figure 8 -2.

FUNCTION
CODE

IoE--- 6

BITS

CHARACTER
ADDRESS

II

~IE!!II'"

Figure 8-3.

®

00

18 17 16

23

I

Word Addressing

17 BITS

~I

I

Character Addressing

Upper Three Address Bits

The upper three address bits select 1 of 8 32K program address groups. The
ISR and OSR define the specific program address group for all memory references
except I/O and Search/Move operand references. The program address group
being referenced for instructions and operands can assume anyone of eight discrete values by modifying the contents of these 3-bit registers. By transferring
dissimilar numbers into these registers, instructions and operands may reference
different program address groups.

I
I

In I/O and Search/Move instructions a 32K program address group for operand
references is selected by the lower three bits of the A register. The address
group number must be entered into the A register before the I/O or Search/Move
instruction is executed. When the operation starts, the address group number is
transferred to a register file location that holds the updated 18-bit operand
address throughout the operation.
Table 8 -1 shows the source of the upper three address bits for the various operating
modes.

8-5

Rev K

,

00000

PROGRAM A

PROGRAM B

PROGRAM C

ADDRESSES

PROGRAM

D

PROGRAM E
77777

Figure 8-4.

I

,

TABLE 8 -1.

Program Address Group

UPPER THREE ADDRESS BITS
Instruction
Address

Operand':'
Address

Initial Monitor State

Zero

Zero

Monitor State and 55.4 (relocate
to operand state) instruction
executed

Zero

Contents of OSR

Operational State of the Processor

Transition from Monitor State to
Program State

Contents of ISR

Contents of ISR

Program State and 55.4 (relocate
to operand state) instruction
executed

Contents of ISR

Contents of OSR

Program State and 55.0 (relocate
to instruction state) instruction
executed

Contents of ISR

Contents of ISR

Any interrupt condition to
Monitor State

Zero

Zero

':'EXCEPTIONS:

I

Rev K

1.

I/O and Search/Move instructions - Upper 3 bits of operand address
originate in bits 0-3 of A register regardless of operating mode.

2.

77.75 (Set Typewriter Input) and 77.76 (Set Typewriter Output) instructions - Upper 3 bits of operand address must be preset in Register File
33 (bits 21-23).

®

Page Index File

The Page Index File is functionally divided into eight distinct reference areas.
One area is associated with each of eight possible numbers appearing in the ISR
and OSR. Because of this direct relationship, each of the eight program address
groups is permanently assigned a reference area in the Page Index File.
Each of the eight reference areas within the Page Index File consists of sixteen
12-bit Page Index Registers. This provides each of the program address groups
exclusive use of 16 of these registers. By using the upper 4 bits of the program
address for direction to the respective Page Index Registers, a direct and
sequential relationship is established between the addresses in a program address group and a specific set of 16 Page Index registers. The Page Index File
is actually constructed of 64 24-bit Page Index registers with dual 12-bit indexe s. Only one of the 12 -bit indexe s is used during any specific reference.
Figure 8-6 depicts the page indexes within the Page Index File and Figure 8-7
illustrates the relationship between program address groups, Page Index File,
and a fully expanded core memory.
Bit 11 of the original 15-bit address determines which of the two page indexes
at the Page File location will be used. Figure 8-5 shows a specific page index
being referenced.

(ISR)
02

PROGRAM ADDRESS (P)
14 12 II 10

00

I

I

00

~-------I

L.:....LL _______ -.J
' - - - INDICATES ODD PAGE
INDEX AT LOCATION 23

123
21

I PAGE
I

SECTION OF PAGE FILE
12 II
INDEX 21

o

I

221 PAGE INDEX 22

oI

231 PAGE INDEX 23

o

241 PAGE

INDEX 24

o

~\

001

PAGE INDEX

21

PAGE INDEX 22

I

I
I

Il

I'

~(~E

INDEX 24

\\

\\

I

h.',
,, , ,
, ,
"-

\ \

\)

PAGE INDEX 2 3

"-

"-

"- ,

,,

I

I

v

The contents of this Page Index (E,
PL, PA, and PP) are used to form
the relocated' address. The format
of a page index is shown below.
..

10

oe 08

II I
E

Figure 8-5.

PL

02 01
PA

00

I I
PP

Example of Page Index Referencing
8-7

I
Rev K

I

BIT II OF ORIGINAL
ADDRESS (PI

(THIS DIGIT INDICATES

I r-""".

"'H ".'"

23

PAGE

00

12
INDEX 00

II

0----:

I
PAGE

01

INDEX 01

0

~
O~I
PAGE INDEX
PAGE INDEX

01

I

PAGE INDEX

02

I

PAGE INDEX

03

I

:I

PAGE INDEX

04

I

I

PAGE INDEX

05

I

PAGE INDEX

06

I

I

PAGE INDEX 07

I

~

PAGE INDEX

10

I

PAGE INDEX

"

I

PAGE INDEX 12

I

PAGE

I

I

00

I
PAGE

02

INDEX

02

0

I

I
03

PAGE

INDEX 03

0

04

PAGE

INDEX

04

0

05

PAGE

INDEX

05

0

I

I
PAGE INDEX

06

06

0

I

I

PAGE INDEX
FILE
HARDWARE
LOCATIONS

07

PAGE INDEX .07

0

10

PAGE

INDEX

10

0

I I

PAGE INDEX

II

0

12

PAGE INDEX

12

0

13

PAGE INDEX

13

0

!
~

:
I

'--

r-------

-

INDEX 13

~

-----

I

I
PAGE INDEX 71

7 I

0

I

PAGE INDEX 71

I

PAGE INDEX 72

I

PAGE INDEX 73

I

PAGE INDEX 74

I

PAGE INDEX 75

I

I
PAGE INDEX· 72

72

0

I

I
PAGE INDEX 73

73

0

I
I

PAGE INDEX 74

74

0

I

I
PAGE INDEX 75

75

0

I

I
76

PAGE INDEX 76

0

I

PAGE INDEX 76

I

77

PAGE INDEX 77

0

:

PAGE INDEX 77

I

~----------~vr----------~/~'------------~V~------------~
EVEN PAGE INDEX FILE
ADDRESSES

I
I

Figure 8 ·6.
Rev K

ODD PAGE INDEX FILE
ADDRESSES

Page Index File Address and Hardware Structure
8-8

PAGE INDEX
REGISTERS EACH PAGE INDEX ~_ _ _ _ _ _ _ _ _ _ _...,
MAY ACCESS ANY
...-_ _ _--, PAGE IN ME MORY

~-.....,---MONITOR
PROGRAM

PROGRAM
ADDRESS
GROUP I
L-_ _--J

---{
-----------------------------------~

EACH PRO...--_ _--, _ _ _ _ _
GRAM ADDRESS
GROUP CONSISTS PROGRAM
OF ONE OR MORE ADDRESS
INDIVIDUAL PRO- GROUP 2
GRAMS WITHIN
32,768 ADDRESSES
PROGRAM
ADDRESS
GROUP 3

PROGRAM
ADDRESS
GROUP 4

PROGRAM
ADDRESS
GROUP 5

PROGRAM
ADDRESS
GROUP 6

PROGRAM
ADDRESS
GROUP 7

PAGE 0
16
PAGE INDEX "";::::-_ _ _ _ _ _
REGISTERS ..

~} =-_-_-_-_-_~:::===::::
ADDRESS GROUP
HAS ACCESS TO
16 UNIQUE PAGE
INDEXES

MEMORY

=-_-___
--=-=-.;...-_--=-

MEMORY
PAGE I

MEMORY
PAGE 2

- _-.:_-_-_

=-------16
PAGE INDEX
REGISTERS

16
PAGE INDEX
REGISTERS

MEMORY
PAGE 3

MEMORY
PAGE"

MEMORY
PAGE 5

MEMORY
PAGE 6
16
PAGE INDEX
REGISTERS

16
PAGE INDEX
REGISTERS

16
PAGE INDEX
REGISTERS

MEMORY
PAGE 122

MEMORY
PAGE 123

MEMORY
PAGE 124
16
PAGE INDEX
REGISTERS

- - - - 1-_----'

MEMORY
PAGE 125

MEMORY
PAGE 126

MEMORY
PAGE 127

Figure 8-7.

I

Relocation System Illustrating Memory Protection
with Fully Expanded Memory (262K)

8-9

Rev K

I

@

I

Page Index

Each page index has the same basic format. The significance of each designator
during the relocation process is described below. Figure 8-8 shows the format
for a page index while Figure 8-9 shows a view of the display panel on the relocation chassis.
II 10
OR

09 08

OR

OR

23 22

OR OR

21 20

14 13

II I
E

E
PL
PA
PP

ACTUAL BITS DEPEND
OO}
UPON WHETHER THE
OR
EVEN OR ODD PAGE
12
INDEX IS REFERENCED

0201

OR

PL

PA

PP

I

= EXCLUSION BIT (I BIT)
= PAGE LENGTH DESIGNATOR

= PAGE

ADDRESS
= PARTIAL PAGE

1

(2 BITS)
DESIGNATOR (7 BITS)
DESIGNATOR (2 BITS)

Figure 8 -8.

E - Exclusion

Page Index Format

Bit

This designator may have one of three meanings:
1.

If E = "0", the quantity expressed by PA defines a page*

where either reading or writing is permitted.
2.

If E = "1", and PL, PA or PP is a quantity other than

zero, PA defines a page * where only. reading is permitted. If a write is attempted, an Illegal Write interrupt is generated.
3.

= "1" and PL, PA or PP are all equal to ·zero~
an unaddressable page is defined and an Illegal Write
interrupt is generated by the Page Index File.

If E

* Refer to descriptions of PL and PP designators for page restrictions.

CPU S-BUS

2 0,-:

9666696<29
Zill

PF ADDRESS

l

_0_0-=-'4---19

BUS

PP

"co
"'

E

I

I

PL

1

ll1lDD

I

PA

Figure 8 -9.

Rev K

6660

MODULE SELECT

EVEN

6 66 6666666 66
L..-J

ST0 S-BUS

L--....J

6 66 6600000 00
L..-.l

E

PP

I

PL

Relocation Chassis Display Panel

8-10

J

L--J

PP

PA - Seven bits are used to define the actual memory module being referenced.
As stated earlier in this manual, there may be 128 segmented pages in a
3300 system with 262, 144 words of core storage.
Each page has
a unique page address and addresses 000 through 1778 define all of the
possible pages.
A 3300 system with a fully expanded storage network has two address
busses. Each bus has access to 131,072 words of the total 262,144
storage words. The uppermost bit of PA (bit 17 in the relocated address)
determines which bus (right or left) is selected. This bit will be a "1"
when the left bus is used and a "0" when the right bus is selected. Figure
8 -10 depicts the bus address system.

I

MULTIPROGRAMMING
OPTION

LEFT
BUS

131,072 WORDS OF
CORE STORAGE IN
32,768 BANKS

RIGHT
BUS

\

!

BI T I 7 OF
PA =" I"

Figure 8-10.

131,072 WORDS OF
CORE STORAGE IN
32,768 BANKS

BIT 17 OF
PA="O"

Storage Address Buses

f

000000
512
000777
001000

512
QUARTER PAGE
ADDRESSES FOR
PAGE 0

001777
002000

- 512

002777
003000

LOCATIONS

- - - - -LOCATIONS

- -

- -

I

1/4 PAGE

~

1/2 PAGE

~

3/4 PAGE
FULL PAGE

LOCATIONS

- - - -- 512 LOCATIONS

003777
NOTE: PP = 0 FOR THIS EXAMPLE
PL = 0 FOR FULL PAGE
PL

=

I FOR 1/4 PAGE

Figure 8 -11.

PL
PL

=2
=3

FOR 1/2 PAGE
FOR 3/4 PAGE

I

Page Length Subdivisions
8-11

Rev

KI

PL -

I

Each page has 2,048 memory locations and is subdivided into quarters of
512 locations each. The PL designator defines how many quarters of a
page can be referenced (beginning with the starting quarter specified by
PP)' A program is assigned the number of quarter pages it needs to reside in memory. Figure 8-11 illustrates the quarter sections of a page
and the significance of the PL bits.

PP -

The Partial Page designator is the address of the physical quarter page
that will serve as the starting point of the page. Example A (Figure 8 -12)
shows the quarter page referenced for each of the PP designators. The
significance of the PP designator in selecting the respective quarter page
for addressing is described below.
EXAMPLE A

PHYSICAL
QUARTER
DESIGNATOR

STARTING QUARTER

~

PP=O

STARTING QUARTER

~

PP = I

PP= 2 STARTING QUARTER ~

PP= 3
STARTING QUARTER

I
IRev K

Figure 8 -12.

~

t

RELATIVE QUARTER
IN RESPECT TO THE
STARTING QUARTER

!

1ST

QUARTER

2ND

QUARTER

2

3RD

QUARTER

3

4TH QUARTER

4

1ST

QUARTER

4

2ND

QUARTER

3RD

QUARTER

2

4TH

QUARTER

3

1ST

QUARTER

3

2ND QUARTER
3 RD QUARTER

4

4TH

QUARTER

2

1ST

QUARTER

2

2ND QUARTER

3

3RD

QUARTER

4

4TH

QUARTER

Quarter Page in Relation to PP Designator
8-12

If PP = 0, the relative page begins in the 1st physical quarter
If PP = 1, the relative page begins in the 2nd physical quarter
If PP = 2, the relative page begins in the 3rd physical quarter
If PP = 3, the relative page begins in the 4th physical quarter

®

Partial Page Adder

A special adder is used to combine the PP designator from the page index with
bits 9 and 10 of the original address. The partial sum indicates the address of the
physical quarter in which referencing will begin. Example B and Figure 8 -13
I
show the actual quarter page in which addressing occurs for specific PL, PP, and
bits 9 and 10 values.
EXAMPLE B
PL = 0
PP

=1

Bits 9 and 10 = 2
Analysis:

A full page (PL = 0) is allocated, the relative page
begins in the second physical quarter, and referencing begins in the fourth physical quarter, (physical
quarter address 3).
RELATIVE

STARTING QUARTER

PP

=I

1ST

QUARTER

2ND

QUARTER

3 RD

QUARTER

2

4 TH

QUARTER

3

QUARTERS

4

~

BITS9ANDIO=2

/

ADDRESSING STARTS IN THE
THIRD RELATIVE QUARTER
(FOURTH PHYSICAL QUARTER)

Figure 8 -13.

Starting Quarters versus Relative Quarters

It should be noted that if bits 9 and 10 of the original address specify a quarter

page equal to or greater than that of the PL designator when PL f zero, an Illegal
Write interrupt -will occur. An example of this condition would be a 1 14 page
allocated but bits 9 and 10 equal to 3, thus specifying an address in the fourth
quarter.
This interrupt will not occur during Monitor State or

8-13

Ilo

operations.

Rev K

I

®

Relocated Address

The 18-bit relocated address defines the actual core storage location being
referenced.
The PA portion of the page index fills the upper seven bits of this address (8)
bus to use and select the appropriate storage module. Bits 9 and 10 receive the
output of the adder previously described and indicate the physical quarter page
being referenced. The lower nine bits are unaltered from the original address
and comprise the remainder of the relocated address.
Page

Zero

Consideration

If page Index File address zero is referenced in either the Program or Monitor
state, the PA and PP designators for this page index will always be zero. As
a result of this condition, page zero, which encompasses addresses 000000
through 003777, can be accessed and used for storing the Auto Load and Auto
Dump routines. The Auto Load routine is contained in addresses 003700
through 003737 and the Auto Dump routine is stored in addresses 003740 through
003777 .

I

Rev K

8-14

APPENDIX A

CONTROL DATA 3100, 3200, 3300 COMPUTER SYSTEMS
CHARACTER SET AND
BCD/ASCII CODE CONVERSIONS

CONTROL DATA 3100, 3200, 3300 COMPUTER SYSTEMS
CHARAC TER SE T
INTERNAL
BCD
CODES

EXTERNAL
BCD
CODES

CONSOLE TYPEWRITER
CHARACTERS (USES
INTERNAL BCD ONLY)

MAGNETIC
TAPE UNIT
CHARACTERS

PUNCHED
CARD
CODES

00

12

o (zero)

o (zero)

0

01

01

1

1

1

02

02

2

2

2

03

03

3

3

3

04

04

4

4

4

05

05

5

5

5

06

06

6

6

6

07

07

7

7

7

10

10

8

8

8

11

11

9

9

9

12

(illegal)

±

--

2,8

13

13

=

#

3,8

14

14

II

@

4,8

15

15

---

5, 8

16

16

,

---

6,8

17

17

?

(file mark)

7,8

20

60

+

&

12

21

61

A

A

12, 1

22

62

B

B

12,2

23

63

C

C

12,3

24

64

D

D

12,4

25

65

E

E

12, 5

26

66

F

F

12, 6

27

67

G

G

12,7

30

70

H

H

12,8

31

71

I

I

12,9

32

72

(Shift to
lower case)

+0

12,0

33

73

. (period)

34

74

)

):t

12,4,8

35

75

---

12, 5, 8

36

76

'(apostrophe)
@

---

12, 6,8

37

77

!

---

12, 7, 8

A-1

-

12, 3,8

(Continued on next page)
Rev. A

INTERNAL
BCD
CODES

EXTERNAL
BDC
CODES

CONSOLE TYPEWRITER
CHARACTERS (USES
INTERNAL BCD ONLY)

MAGNETIC
TAPE UNIT
CHARACTERS

PUNCHED
CARD
CODES

40

40

-(minus)

-(minus)

41

41

J

J

11, 1

42

42

K

K

11,2

43

43

L

L

11, 3

44

44

M

M

11,4

45

45

N

N

11,5

46

46

a

a

11,6

47
50

47
50

P

P

11, 7

51

Q
R

11,8

51

Q
R

11,9

52

52

o

-0

11,0

53
54

53

$

$

11, 3, 8

54

'"

11,4,8

55

55

*

....

#

11,5,8

56

56

%

57

57

(Shift to
upper case)

-------

60

20

(space)

(blank)

(blank)

61

21

/

/

0, 1

62
63

22

S

S

0,2

23

T

T

64

24

U

U

0,3
0,4

65

25

V

V

0, 5

66

26

W

W

0, 6

67

27

X

X

0, 7

70

30

Y

Y

0, 8

71

31

Z

Z

0, 9

72

32

&

---

0,2,8

73
74
75

33

, (comma)

34
35

(

(tab)

76

36

(backspace)

77

37

(carriage return)

Rev. A

(degree)

A-2

11

II, 6, 8
11, 7,8

, (comma)

0,3,8

%

0,4,8

--

---

0, 5, 8
0, 6, 8

---

0, 7, 8

-

BCD/ ASCII CONVERSION TABLE
6-BIT
BCD CODE

8-BIT
ASCII
CHARACTER

BINARY STATUS OF ASCII CHARACTER
(BIT POSITIONS
2
1
4
5
3
6
7*

0

00

0

0

0

1

1

0

0

0

0

01

1

0

0

1

1

0

0

0

1

02

2

0

0

1

1

0

0

1

0

03

3

0

0

1

1

0

0

1

1

04

4

0

0

1

1

0

1

0

0

05

5

0

0

1

1

0

1

0

1

06

6

0

0

1

1

0

1

1

0

07

7

0

0

1

1

0

1

1

1

10

8

0

0

1

1

1

0

0

0

11

9

0

0

1

1

1

0

0

1

0

0

1

1

1

0

1

0

12
13

=

0

0

1

1

1

1

0

1

14

1

0

0

1

0

0

1

1

1

15

&

0

0

1

0

0

1

1

0

16

0

0

1

0

0

1

0

1

17

0/0
[

0

1

0

1

1

0

1

1

20

+

0

0

1

0

1

0

1

1

21

A

0

1

0

0

0

0

0

1

22

B

0

1

0

0

0

0

1

0

23

C

0

1

0

0

0

0

1

1

24

D

0

1

0

0

0

1

0

0

25

E

0

1

0

0

0

1

0

1

26

F

0

1

0

0

0

1

1

0

27

G

0

1

0

0

0

1

1

1

30

H

0

1

0

0

1

0

0

0

31

I

0

1

0

0

1

0

0

1

32

<

0

0

1

1

1

1

0

0

0

0

1

0

1

1

1

0

33
34

)

0

0

1

0

1

0

0

1

35

A

0

1

0

1

1

1

1

0

36

11

0

0

1

0

0

0

1

0

0

0

1

1

1

0

1

1

37

J

':'ASCII bit 7 is unassigned and "0" for all codes.
A-3

Rev. C

BCD/ ASCII CONVERSION TABLE (Cont'd)
6-BIT
BCD CODE

8-BIT
ASCII
CHARACTER

BINARY STATUS OF ASCII CHARACTER


0

0

1

1

1

1

1

0

60

Blank

0

0

1

0

0

0

0

0

61

/

0

0

1

0

1

1

1

1

62

S

0

1

0

1

0

0

1

1

63

T

0

1

0

1

0

1

0

0

64

U

0

1

0

1

0

1

0

1

65

V

0

1

0

1

0

1

1

0

66

W

0

1

0

1

0

1

1

1

67

X

0

1

0

1

1

0

0

0

70

Y

0

1

0

1

1

0

0

1

71

Z

0

1

0

1

1

0

1

0

72

]

0

1

0

1

1

1

0

1

73

Comma

0

0

1

0

1

1

0

0

74

(

0

0

1

0

1

0

0

0

75

'"

0

1

0

1

1

1

0

0

76

-

0

1

0

1

1

1

1

1

77

?

0

0

1

1

1

1

1

1

':'Ascn bit 7 is unassigned and "0" for all codes.
Rev. C

A-4

APPENDIX B

SUPPLEMENTARY ARITHMETIC INfORMATION

B,

SUPPLEMENTARY ARITHMETIC INFORMATION

NUMBER SYSTEMS
Any number system may be defined by two characteristics, the radix or base
and the modulus. The radix or base is the number of unique symbols used in
the system. The decimal system has ten symbols, 0 through 9. Modulus is
the number of unique quantities or magnitudes a given system can distinguish.
For example, an adding machine with ten digits, or counting wheels, would
have a modulus of 10 10 -1. The decimal system has no modulus because an
infinite number of digits can be written, but the adding machine has a modulus
because the highest number which can be expressed is 9, 999, 999, 999.
Most number systems are positional; that is, the relative position of a symbol
determines its magnitude. In the decimal system, a 5 in the units column
represents a different quantity than a 5 in the tens column. Quantities equal
to or greater than 1 may be represented by using the 10 symbols as coefficients
of ascending powers of the base 10. The number 98410 is:
9 x 10 2
+8 x 10 1
+4 x 10 0

=9 x
8 x
4 x

100
900
10 = 80
1
4
984 10

Quantities less than 1 may be represented by using the 10 symbols as coefficients of ascending negative powers of the base 10. The number 0.59310
may be represented as:
5 x 10- 1 = '5 x .1
.5
+9 x 10- 2 9 x .01 == . a9
+3 x 10- 3 = 3 x .001
.003
0.593 10
Binary Number System
Computers operate faster and more efficiently by using the binary number
system. There are only two symbols, 0 and 1; the base = 2. The following
shows the positional value:
25
24
23
22
21
20
32
16
8
4
2
1
Binary point
B-1

Rev. A

The binary number 0 1 1 0 1 0 represents:
o x 2 5 = 0 x 32 = 0
+1 x 24 = 1 x 16 = 16
+1 x 2 3 = 1 x 8 = 8
+0 x 22 = 0 x 4
0
+1 x 21 = 1 x 2
2
+0 x 20 = 0 x 1
0
26 1 0
Fractional binary numbers may be represented by using the symbols as coefficients of ascending negative powers of the base.
2 -1
2 -2
2 -3
2 -4
2 -5 ...
Binary Point 1 / 2
1 /4
1 /8
1 /16.
1 /32
The binary number 0.10 110 may be represented as:
1 x 2
+Ox2
+1 x 2
+1 x 2

-1
-2
-3
-4

= 1 x 1/2
/
=Ox14
= 1 x 1/8
= 1 x 1/16

= 1/2
=0
= 1/8
= 1/16

= 8/16
=0
= 2/16
= 1/16
iT7T610

Octal Number System
The octal number system uses eight discrete symbols,
eight the positional value is:
85
82
84
83
32,768
64
4,096
512

o through

7.

With base

The octal number 5138 represents:
5 x 8 2 = 5 x 64 = 320
+1 x 8 1
1 x 8
8
+3 x 8 0 = 3 x 1 =
3
331 10
Fractional octal numbers may be represented by using the symbols as coefficients of ascending negative powers of the base.
8 -1
8- 2
8- 3
8- 4
1/8
1/64 1/5121/4096
The octal number 0.4520 represents;
4 x 8 -1 = 4 x 1/8
256/512
+5 x 8 - 2 = 5 x 1/64 = 40/512
+2 x 8 -3 = 2 x 1 / 512 =
2/512
298/512 = 149/25610

Rev. A

B-2

ARITHMETIC
Addition and Subtraction
Binary numbers are added according to the following rules:
0+0==0
a+1 1
1

+a

1 + 1

1

a with a carry of 1

The addition of two binary numbers proceeds as follows (the decimal equivalents
verify the result):
Augend
Addend
Partial Sum
Carry
Sum

0111
+0100
0011
1
1011

(7)

+(4)
(11)

Subtraction may be performed as an addition:
8 (minuend)
-6 (subtrahend)
2 (difference)

or

8 (minuend)
+4 (la's complement of subtrahend)
2 (difference - omit carry)

The second method shows subtraction performed by the "adding the complement II
method. The omission of the carry in the illustration has the effect of reducing
the result by 10.
One's Complement: The computer performs all arithmetic and counting
operations in the binary one's complement mode. In this system, positive
numbers are represented by the binary equivalent and negative numbers in ones'
complement notation.
The one's complement representation of a number is found by subtracting each
bit of the number from 1. For example:
1111
-1001
0110

9
(one's complement of 9)

This representation of a negative binary quantity may also be obtained by substituting 11's" for "O's" and "O's" for 11'S".
The value zero can be represented in one's complement notation in two ways:
0000 - 002
1111 - 112

Positive (+) Zero
Negative (-) Zero

The rules regarding the use of these two forms for computation are:
•

Both positive and negative zero are acceptable as arithmetic operands.

.. If the result of an arithmetic operation is zero, it will be expressed as
positive zero.

B-3

Rev. A

One IS complement notation applies not only to arithmetic operations performed
in A, but also to the modification of execution addresses in the F register.
During address modification, the modified address will equal 777778 only if the
unmodified execution address equals 777778 and b = 0 or (Bb) = 777778.
Multiplication
Binary multiplication proceeds according to the following rules:

ox
ox

0
1

0
0

1 x 0 0
1 xlI
Multiplication is always performed on a bit-by-bit basis. Carries do not result
from multiplication, since the product of any two bits is always a single bit.
Decimal example:
Multiplicand
Multiplier
Partial Products

1

14
12

28

14
(shifted one place left)
168 10

Product

The shift of the second partial product is a shorthand method for writing the
true value 140.
Binary exam pIe:
Multiplicand (14)
Multiplier
(12)

Partial Products
Product (168

10

)

t

1110
1100
0000
shift to place
0000
1110
digits in proper
1110
columns
101010002

The computer determines the running subtotal of the partial products. Rather
than shifting the partial product to the left to position it correctly, the computer right shifts the summation of the partial products one place before the
next addition is made. When the multiplier bit is "1", the multiplicand is
added to the running total and the results are shifted to the right one place.
When the multiplier bit is "0 If, the partial product subtotal is shifted to the
right (in effect, the quantity has been multiplied by 102)'
Division
The following examples shows the familiar method of decimal division:

Rev. A

B-4

Divisor

13

14

Quotient
Dividend

55

Partial Dividend

f185
11
.Q.£
3

Remainder

The computer performs division in a similar manner (using binary equivalents):
Divis or

11 0 1

1110
1:-:0:-:1"'""'1"'""'1"""0"""0""'1
1101
10100
1101
1110
1101
--11

rI

Quotient (14)
D i vi d en d

Partial Dividends
Remainder (3)

However, instead of shifting the divisor right to position it for subtraction from
the partial dividend (shown above), the computer shifts the partial dividend left,
accomplishing the same purpose and permitting the arithmetic to be performed
in the A register. The computer counts the number of shifts, which is the
number of quotient digits to be obtained; after the correct number of counts, the
routine is terminated.

CONVERSIONS
The procedures that may be used when converting from one number system to
another are power addition, radix arithmetic, and substitution.

TABLE B-1.

RECOMMENDED CONVERSION PROCEDURES
(INTEGER AND FRACTIONAL)
Recommended Method

Conversion

Power Addition
Power Addition
Radix Arithmetic
Radix Arithmetic
Substituti on
Substitution

Binary to Decimal
Octal to Decimal
Decimal to Binary
Decimal to Octal
Binary to Octal
Octal to Binary

GENERAL RULES
r.

r~1

>

: use Radix Arithmetic, Substitution
: use Power Addition, Substitution
r. = Radix of initial system
r~ = Radix of final system

r

< r ff

B-5

Rev. A

Power Addition
To convert a number from ri to rf (ri < rf) write the number in its expanded r·
polynomial form and simplify using rf arithmetic.
1
EXAMPLE 1

Binary to Decimal (Integer)
010 1112 = 1(24) +0(2 3 ) +1(22) +1(2 1 ) +1(20)
= 1(16) +0(8) +1(4) +1(2) +1(1)
16
+0
+4
+2
+1
23 10
EXAMPLE 2
Binary to Decimal (Fractional)
1
.0101 = 0 (2- ) +1(2-2) +0(2- 3 ) +1(2- 4 )
2
=0
+1/4
+0
+1/16
= 5/16
10
EXAMPLE 3
3248 =
=
=
=

Octal to Decimal (Integer)
2
3 (8 ) +2(8 1 ) +4(8 0 )
3 (64) +2(8) +4(1)
192 +16
+4
212 10

EXAMPLE 4

Octal to Decimal (Fractional)
.44 8 = 4(8- 1 ) +4(8- 2 )
= 4/8
+4/64
36/64 10
= 9/16 10

Radix Arithmetic
To convert a whole number from ri to rf (ri >rf):
• Divide ri by rf using ri arithmetic
•

The remainder is the lowest order bit in the new expression

•

Divide the integral part from the previous operation by rf

•

The remainder is the next higher order bit in the new expression

• The process continues until the division produces only a remainder
which will be the highest order bit in the r f expression.
To convert a fractional number from ri to r(
• Multiply ri by rf using ri arithmetic
•

The integral part is the highest order bit in the new expression

• Multiply the fractional part from the previous operation by rf
•

The integral part is the next lower order bit in the new expression

•

The process continues until sufficient precision is achieved or the
process terminates.

Rev. A

B-6

EXAMPLE 1
45 -:22 -:11 -:5 -:2 -71 -7Thus:

2
2
2
2
2
2

= 22
= 11
=5
= 2
= 1
= 0
45 10

Decimal to Binary (Integer)

remainder
remainder
remainder
remainder
remainder
remainder
= 101101 2

EXAMPLE 2

1;
0;
1;
1;
0;
1;

record
record
record
record
record
record

EXAMPLE 3

1

o

.010

Decimal to Octal (Integer)

EXAMPLE 4

x 8

o

1
101101

o

273 -:- 8 = 34 remainder 1; record
34 -:-8 = 4 remainder 2; record
4 +8 = 0 remainder 4; record
Thus: 273 10 = 4218

. 2

1

1

Decimal to Binary (Fractional)

. 25 x 2 = 0.5; record
.5 x 2 = 1. 0; record
.0 x 2 = 0.0; record
Thus: .25 10
.010 2

.55 x 8
.4 x 8

1

o

1
2
4
421

Decimal to Octal (Fractional)

4.4; record
3.2; record
1. 6; record

4

3
1

.431 ...

Thus:

.55

.431. .. 8

10

Substitution
This method permits easy conversion between octal and binary representations
of a number. If a number in binary notation is partitioned into triplets to the
right and left of the binary point, each triplet may be converted into an octal
digit. Similarly, each octal digit may be converted into a triplet of binary digits.
EXAMPLE 1

Binary to Octal

Binary = 110 000
Octal
6
0
EXAMPLE 2
Octal
Binary

001 010
1'. 2

Octal to Binary
6

= 110

5
101

0
2
2
000. 010 010

B-7

7
111

Rev. A

FIXED POINT ARITHMETIC
24-Bit Precision
Any number may be expressed in the form kBn, where k is a coefficient, B a
base number, and the exponent n the power to which the base number is raised.
A fixed point number assumes:

= a for

..

The exponent n

all fixed point numbers.

•

The coefficient, k, occupies the same bit positions within the computer
word for all fixed point numbers.

.. The radix (binary) point remains fixed with respect to one end of the
expression.
A fixed point number consists of a sign bit and coefficient as shown below. The
upper bit of any fixed point number designates the sign of the coefficient (23
lower order bits). If the bit is "I", the quantity is negative since negative
numbers are represented in one's complement notation; a "0" sign bit signifies
a positive coefficient.
23 22

II

00

COEFFICIENT

I

SIGN

BIT

The radix (binary) point is assumed to be immediately to the right of the lowest
order bit (00).
In many instances, the values in a fixed point operation may be too large or too
small to be expressed by the computer. The programmer must position the
numbers within the word format so they can b~ represented with sufficient preCISIOn. The process, called scaling, consists of shifting the values a predetermined number of places. The numbers must be positioned far enough to
the right in the register to prevent overflow but far enough to the left to maintain precision. The scale factor (number of places shifted) is expressed as the
power of the base. For examRle, 5,100, 0001Q may be expressed as 0.51 x
10 7 , O. 051 x 10 8 , O. 0051 x 10 9 , etc. The sca.le factors are 7, 8, and 9.
Since only the coefficient is used by the computer, the programmer is responsible for remembering the scale factors. Also, the possibility of an overflow during intermediate operations must be considered. For example, if two
fractions in fixed point format are multiplied, the result is a number
1. If
the same two fractions are added, subtracted, or divided, the result may be
greater than one and an overflow will occur. Similarly, if two integers are
multiplied, divided, subtracted or added, the likelihood of an overflow is
apparent.

<

48-Bit Precision (Double Precision)
The 48-bit Add, Subtract, Multiply and Divide instructions enable operands to
be processed. The Multiply and Divide instructions utilize the E register and
Rev. A

B-8

therefore are executed as trapped instructions if the applicable arithmetic
option is not present in a system. Figure 5-5 in the Instruction Section illustrates the operand formats in 48-bit precision Multiply and Divide instructions.
FLOA TING POINT ARITHMETIC
As an alternative to fixed point operation a method involving a variable radix
point, called floating point, is used. This significantly reduces the amount of
bookkeeping required on the part of the programmer.
By shifting the radix point and increasing or decreasing the value of the exponent,
widely varying quantities which do not exceed the capacity of the machine may
be handled.
Floating point numbers within the computer are represented in a form similar
to that used in scientific notation, that is, a coefficient or fraction multiplied
by a number raised to a power. Since the computer uses only binary numbers,
the numbers are multiplied by powers of two.
F • 2E

where:

F = fraction
E = exponent

In floating point, different coefficients need not relate to the same power of the
base as they do in fixed point format. Therefore, the construction of a floating
point number includes not only the coefficient but also the exponent.
NOTE
Refer to Figure 5 - 6 in the Instruction Section for the operand format and
bit functions for specific floating point instructions.
Coefficient
The coefficient consists of a 36-bit fraction in the 36 lower order positions of
the floating point word. The coefficient is a normalized fraction; it is equal to
or greater than 1/2 but less than 1. The highest order bit position (47) is
occupied by the sign bit of the coefficient. If the sign bit is a "0 ", the coefficient is positive; a "1" bit denotes a negative fraction (negative fractions are
represented in one's complement notation).
Exponent
The floating point exponent is expressed as an ll-bit quantity with a value
ranging from 0000 to 37778' It is formed by adding a true positive exponent
and a bias of 20008 or a true negative exponent and a bias of 17778. This results in a range of biased exponents as shown on the following page.

B-9

Rev. A

True Positive
Exponent

True Negative
Exponent

Biased
Exponent

Biased
Exponent

+0
+1
+2

2000
2001
2002

-0
-1
-2

2000':<
1776
1775

---

-------

---

---- ---

+1776
+17778

3776
37778

-1776
- 1777 8

0001
00008

47 46

00

36 35

EXPONENT (INCLUDING

L- SIGN

BIAS)

COEFFICIENT

BIT

'~Minus

zero is sensed as positive zero by the computer and is therefore
biased by 20008 rather than 17778.
The exponent is biased so that floating point operands can be compared with
each other in the normal fixed point mode.

As an example, compare the unbiased exponents of +528 and +0.028 (Example 1).
EXAMPLE 1
Number

o

o0

Coefficient

000

= +52 8
000

110

(36 bits)

Coefficient

Exponent

Sign
Number = +0.02

o

1 1

111

111

8
011

Coefficient

Exponent

Coefficient

(36 bits)

Sign
In this case +0.02 appears to be larger than +52 because of the larger exponent.
If, however, both exponents are biased (Example 2), changing the sign of both
exponents makes +52 greater than +0.02.
EXAMPLE 2
Number

o

1 0

000

= +52 8
000

110

(36 bits)

Exponent

Coefficient

o

Number = +0.02 8
o 1 111 111 011

(36 bits)

Coefficient

Exponent

Coefficient

Coefficient
Sign

Sign
Rev. A

B-I0

When bias is used with the exponent, floating point operation is more versatile
since floating point operands can be compared with each other in the normal
fixed point mode.
All floating point operations involve the A, Q, and E registers, plus two consecutive storage locations M and M + 1. The A and Q registers are treated as
one 48-bit register. Indirect addressing and address modification are applicable
to this whole group of instructions.
Operand Formats
The AQ register and the storage address contents have identical formats.
In both cases the maximum possible shift is 64 (778) bit positions. Since the
coefficient consists of only 36 bits at the start, any shift greater than 36
positions will, of course, always result in an answer equal to the larger of the
two original operands.
(47)
23
(A) and (M)

(46)
22

(36)
12

(35 )

11

(24)
00

I
//~====~y~=-=-=-=-~~I~\====~V~==~
11-bit operand
exponent including
bias

Sign of
Coefficient

Upper 12 bits of
operand coefficient

23

00

(Q) and (M + 1)
~------------------.vr-------------------~

Lower 24 bits of operand coefficient
Exponents
The 3100, 3200, 3300 Computers use an 11-bit exponent that is biased by 2000 8
for floating point operations. The effective modulus of the exponent is
17778
or
102310'

±

±

Exponent Equalization
During floating point addition and subtraction, the exponents involved are
equalized prior to the operation.
• Addition - The coefficient of the algebraically smaller exponent is
automatically shifted right in AQE until the exponents are equal. A
maximum of 778 shifts may occur.

B-11

Rev. A

.. Subtraction - If AQ contains the algebraically smaller exponent, the
coefficient in AQ is shifted right in AQE until the exponents are equal.
If (M) and (M + 1) have the smaller exponent, the complement of the
coefficient of (M) and (M + 1) is shifted right in AQE until the exponents
are equal or until a maximum of 778 shifts are performed.
Rounding
Rounding is an automatic floating point operation and is particularly necessary
when floating point arithmetic operations yield coefficient answers in excess
of 36 bits.
Although standard floating point format requires only a 36-bit coefficient,
portions of the E register are used for extended coefficients. Refer to individual instruction descriptions for E register applications.
Rounding modifies the coefficient result of a floating point operation by adding
or subtracting a "I" from the lowest bit position in Q without regard to the
biased exponent. The coefficient of the answer in AQ passes through the adder
with the rounding quantity before normalization. The conditions for rounding
are classified according to arithmetic operation in Table B-2.
TABLE B-2.
Arithmetic
OPERATION

ADD
or
SUBTRACT

ROUNDED CONDITIONS FOLLOWING ARITHMETIC OPERATION
Bit 23 of the
A Register

Bit 47 of the E Register
or
(Ratio of Residue /Divisor
for Divide Onlv)

0':'
0':'
1 ':'
1':'

0
1
0
1

Applicable
Rounding

No
Add "I"
Subtract "I I
No

Comments: . Rounding occurs as a result of inequality between
the sign bits of AQ and E.

MULTIPLY

0
1

0
0
1
1

a
1

No
Add "I"
Subtract II"
No

Comments: A floating point multiplication yields a 76 bit
coefficient. Comparison between the sign bits of
AQ and E indicates that the lower 36 bits are equal
to or greater than 1/2 of the lowest order bit in AQ.

DIVIDE

0
0
1
1

>
<
>
<

1/2 (absolute)
1/2 (absolute)
1/:2 (absolute)
1/2 (absolute)

Add "I"
No
Subtract 1
No

Comments: Rounding occurs if the answer resulting from the
final residue division is equal to or greater than 1/2.
':'Condition of bit 23 of the A register immedIately after equallzatlOn.
to Exponent Equalization on preceeding page).
Rev. A

B-12

(Refer

Normalizing
Normalizing brings the above answer back to a fraction with a value between
one-half and one with the binary point to the left of the 36th bit of the coefficient.
In other words, the final normalized coefficient in AQ will range in value from
236 to 2 37 -1 including sign. Arithmetic control normalizes the answer by right
or left shifting the coefficient the necessary number of places and adjusting the
exponent. It does not shift the residue that is in E.
Faults
Three conditions are considered faults during the execution of floating point
instructions:
..

Exponent overflow

(> + 17778)

" Exponent underflow (

<-

1777 8 )

" Division by zero, by too small a number, or by a number that is not
in floating point format
These faults have several things in common:
" They can be sensed by the INS (77. 3) instruction
" Sensing automatically clears them
•

The program should sense for these faults only after the floating point
instructions have had sufficient time to go to completion

" They may be used to cause an interrupt
FIXED POINT /FLOATING POINT CONVERSIONS
Fixed Point To Floating Point
" Express the number in binary .
•

Normalize the number. A normalized number has the most significant
1 positioned immediately to the right of the binary point and is expressed
in the range 1 /2
k
1.

< <

" Inspect the sign of tne true exponent. If the sign is positive add 2000 8
(bias) to the true exponent of the normalized number. If the sign is
negative, add the bias 17778 to the true exponent of the normalized
number. In either case, the resulting exponent is the biased exponent.
II

e

Assemble the number in floating point.
Inspect the sign of the coefficient. If negative, complement the
assembled floating point number to obtain the true floating point representation of the number. If the sign of the coefficient is positive,
the assembled floating point number is the true representation.

B-13

Rev. A

EXAMPLE 1

Convert +4.

a to floating point

.. The number is expressed in octal.
.. Normalize 4. a = 4. a x 8 0 = O. 100x2 3
..

Since the sign of the true exponent is positive, add 20008
(bias) to the true exponent. Biased exponent = 2000 + 3.

• Assemble number in floating point format.
Coefficient = 400 000 000 0008
Biased Exponent = 2003 8
Assembled word = 2003 400 000 000 0008
.. Since the sign of the coefficient is positive, the floating point
representation of +4. a is as shown. If, however, the sign of
the coefficient were negative, it would be necessary to complement the entire floating point word.
EXAMPLE 2
•
..
•

Convert -4.

a to floating point

The number is expressed in octal.
3
Normalize -4. a = -4. a x 8 0 = -0. 100 x 2
Since the sign of the true exponent is positive, add 2000 8
(bias) to the true exponent. Biased exponent = 2000 + 3.

.. Assemble number in floating point format.
Coefficient = 400 000 000 0008
Biased Exponent = 2003 8
Assembled word = 2003 400 000 000 000 8
.. Since the sign of the coefficient is negative, the assembled
floating point word must be complemented. Therefore, the
true floating point representation for
-4.0 = 5774 377 777 777 777 ,
8
EX-A.MPLE 3

Convert 0.510 to floating point

Convert to octal 0.5 10 = 0.48
• Normalize 0.4 = 0.4 x 8 0 = O. 100 x 20

•
•

Since the sign of the true exponent is positive, add 2000 8
(bias) to the true exponent. Biased exgonent = 2000 + O.

• Assemble number in floating point format.
Coefficient = 400 000 000 0008
Biased Exponent = 2000 8
Assembled word = 2000 400 000 000 000 8
.. Since the sign of the coefficient is positive, the floating point
representation of +0. 5 10 is as shown. If, however, the sign
of the coefficient were negative, it would be necessary to
complement the entire floating point word. This example is a
special case of floating point since the exponent of the normalized number is. a and could be represented as -0. The
exponent would then be biased by 17778 instead of 20008 becaus e
of the negative exponent. The 3100 and 3200, however, recognize
-0 as +0 and bias the exponent by 20008'
Rev. A

B-14

EXAMPLE 4

Convert O. 048 to floating point

" The number is expressed in octal.

" Normalize 0.04 = 0.04 x 8 o = 0.4 x 8 -1 = 0.100 x 2 -3 .
" Since the sign of the true exponent is negative, add 17778
(bias) to the true exponent. Biased exponent
1777 8 +
(-3) = 17748
" Assemble number in floating point format.
Coefficient = 400 000 000 000 8
Biased Exponent = 17748
Assembled word = 1774 400 000 000 0008
" Since the sign of the coefficient is positive, the floating
point representation of 0.04 8 is as shown. If, however, the
sign of the coefficient were negative, it would be necessary
to complement the entire floating point word.
Floating Point to Fixed Point Format
" If the floating point number is negative, complement the entire floating

point word and record the fact that the quantity is negative.
ponent is now in a true biased form.
e

The ex-

If the biased exponent is equal to or greater than 2000 8 , subtract 2000 S
to obtain the true exponent; if less than 2000S, subtract 1777S to obtain
true exponent.

" Separate the coefficient and exponent. If the true exponent is negative,
the binary point should be moved to the left the number of bit positions
indicated by the true exponent. If the true exponent is positive, the
binary point should be moved to the right the number of bit positions
indicated by the true exponent.
• The coefficient has now been converted to fixed binary. The sign of the
coefficient will be negative if the floating point number was complemented
in step one. (The sign bit must be extended if the quantity is placed in a
register. )
• Represent the fixed binary number in fixed octal notation.
EXAMPLE 1

Convert floating point number 2003 400 000 000 OOOS
to fixed octal

" The floating point number is positive and remains uncomplemented.
" The biased exponent> 2000 S ; therefore, subtract 2000 S from the
biased exponent to obtain the true exponent of the number.
2003 - 2000 = +3.
Coefficient = 400 000 000 OOOS
. 1002' Move binary point
to the right three places. Coefficient = 100. O2 ,
• The sign of the coefficient is positive because the floating
point number was not complemented in step one.
•

" Represent in fixed octal notation.
100.0 x 2 0 = 4.0 x SO.
B-15

Rev. A

EXAMPLE 2
o

The sign of the coefficient is negative; therefore, complement
the floating point number.
Complement = 2003 400 000 000 000 8

o

The biased exponent (in complemented form)
20008; therefore, subtract 2000 8 from the biased exponent to obtain the
true exponent of the number 2003 - 2000 = +3.

o

>

Coefficient = 4000 000 000 0008 = O. 1002. Move binary
point to the right three places. Coefficient = 100.0 2 ,

o

The sign of the coefficient will be negative because the floating
point number was originally complemented.

•

Convert to fixed octal. -100.0 2

EXAMPLE 3

Rev. A

Convert floating point number
5774 377 777 777 777 8 to fixed octal

= 4.0 8 ,

Convert floating point number
1774 400 000 000 000 8 to fixed octal

o

The floating point number is positive and remains uncomplemented.

o

The biased exponent <20008; therefore, subtract 17778
from the biased exponent to obtain the true exponent of the
number. 17748 - 17778 = -3.

o

Coefficient = 400 000 000 000 8 = • 100 2 , Move binary
point to the left three places. Coefficient = .000100 2 ,

o

The sign of the coefficient is positive because the floating
point number was not complemented in step one.

o

Represent in fixed octal notation .
. 000100 2 = .048 ,

B-16

APPENDIX C

PROGRAMMING REfERENCE TABLES AND
CONVERSION INfORMATION

TABLE OF POWERS OF TWO

2
4
8

o
1
2
3

1.0
0.5
0.25
0.125

16
32
64
128

4
5
6
7

0.062
0.031
0.015
0.007

5
25
625
812 5

256
512
1 024
2 048

8
9
10
11

0.003
0.001
0.000
0.000

906
953
976
488

25
125
562 5
281 25

4
8
16
32

096
192
384
768

12
13
14
15

0.000 244
0.000 122
0.000 061
0.000030

140
070
035
517

625
312 5
156 25
578 125

65
131
262
524

536
072
144
28a

16
17
18
19

0.000
0.000
0.000
0.000

015
007
003
001

258
629
814
907

789
394
697
348

062
531
265
632

5
25
625
812 5

1
2
4
8

048
097
194
388

576
152
304
608

20
21
22
23

0.000 000
0.000000
0.000 000
0.000 000

953
476
238
119

674
837
418
209

316
158
579
289

406
203
101
550

25
125
562 5
781 25

16
33
67
134

777
554
108
217

216
432
864
728

24
25
26
27

0.000
0.000
0.000
0.000

000
000
000
000

059
029
014
007

604
802
901
450

644
322
161
580

775
387
193
596

390
695
847
923

625
312 5
656 25
828 125

268
536
1 073
2 147

435
870
741
483

456
912
824
648

28
29
30
31

0.000
0.000
0.000
0.000

000
000
000
000

003
001
000
000

725
862
931
465

290
645
322
661

298
149
574
287

461
230
615
307

914
957
478
739

062
031
515
257

5
25
625
812 5

4
8
17
34

294
589
179
359

967
934
869
738

296
592
184
368

32
33
34
35

0.000 000 000
0.000000000
0.000 000 000
0.000 000 000

232
116
058
029

830
415
207
103

643
321
660
830

653
826
913
456

869
934
467
733

628
814
407
703

906
45J
226
613

25
125
562 5
281 25

68
137
274
549

719
438
877
755

476
953
906
813

736
472
944
888

36
37
38
39

0.000
0.000
0.000
0.000

014
007
003
001

551
275
637
818

915
957
978
989

228
614
807
403

366
183
091
545

851
425
712
856

806
903
951
475

640
320
660
830

625
312 5
156 25
078 125

1
2
4
8

099
199
398
796

511
023
046
093

627
255
511
022

776
552
104
208

40
41
42
43

0.000000000000 909
0.000000000000454
0.000000 000 000 227
0.000000 000 000 113

494
747
373
686

701
350
675
837

772
886
443
721

928
464
232
616

237
118
059
029

915
957
478
739

039
519
759
379

062
531
765
882

5
25
625
812 5

17
35
70
140

592
184
368
737

186
372
744
488

044
088
177
355

416
832
664
328

44
45
46
47

0.000 000
0.000 000
0.000 000
0.000000

000
000
000
000

000
000
000
000

056
028
014
007

843
421
210
105

418
709
854
427

860
430
715
357

808
404
202
601

014
007
003
001

869
434
717
858

689
844
422
711

941
970
485
242

406
703
351
675

25
125
562 5
781 25

281
562
1 125
2 251

474
949
899
799

976
953
906
813

710
421
842
685

656
312
624
248

48
49
50
51

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

003
001
000
000

552
776
888
444

713
356
178
089

678
839
419
209

800
400
700
850

500
250
125
062

929
464
232
616

355
677
338
169

621
810
905
452

337
668
334
667

890
945
472
236

625
312 5
656 25
328 125

000
000
000
000

000
000
000
000

000
000
000
000

726
363
181
590

333
166
583
791

618
809
404
702

164
082
541
270

062
031
015
507

5
25
625
812 5

395 851
697 925
848 962
924481

135
567
783
391

253
626
813
906

906 25
953 125
476 562 5
738281 25

000
000
000
000

000
000
000
000

4
9
18
36

503
007
014
028

599
199
398
797

627
254
509
018

370
740
481
963

496
992
984
968

52
53
54
55

0.000 000
0.000 000
0.000000
0.000 000

222
111
055
027

044
022
511
755

604
302
151
575

925
462
231
615

031
515
257
628

308
654
827
913

084
042
021
510

72
144
288
576

057
115
230
460

594
188
376
752

037
075
151
303

927
855
711
423

936
872
744
488

56
57
58
59

0.000 000 000 000 000 013
0.000 000 000 000 000 006
0.000 000 000 000 000 003
0.000000000000000001

877
938
469
734

787
893
446
723

807
903
951
475

814
907
953
976

456
228
614
807

755 295
377 647
188 823
094411

152 921 504 606 846 976

60

0000 000 000 000 000 000 867 361 737 988 403 547 205 962 240 695 953 369 140 625

C-l

Rev. A

DECIMAL/BINARY POSITION TABLE

Decimal
Digits

Largest Decimal
Integer

1
2
4
9
18
36
72
144
288
576
1 152

Req'd*

1
2
4
8
17
35
70
140

1
2
4
8
16
33
67
134
268
536
1 .073
2 147
4 294
8 589
17 179
34 359
68 719
137 438
2H 877
549 755
099 511
199 023
398 046
796 093
592 186
184 372
368 744
737 488

1
2
4
8
16
32
65
131
262
524
048
097
194
388
777
554
108
217
435
870
741
483
967
934
869
738
476
953
906
813
627
255
511
022
044
088
177
355

1
3
7
15
31
63
127
255
511
023
047
095
191
383
767
535
071
143
287
575
151
303
607
215
431
863
727
455
911
823
647
295
591
183
367
735
471
943
887
775
551
103
207
415
831
663
327

281
562
125
251
503
007
014
028
057
115
230
460
921

474
949
899
799
599
199
398
797
594
188
376
752
504

710
421
842
685
370
740
481
963
927
855
711
423
846

655
311
623
247
495
991
983
967
935
871
743
487
975

976
953
906
813
627
254
509
018
037
075
151
303
606

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

..

18

Number
of

Largest Decimal Fraction

Binary
Digits
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

.5
.75
.875
.937
.968
.984
.992
.996
.998
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999

5
75
375
187
093
046
023
511
755
877
938
969
984
992
996
998
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999

5
75
875
437
718
859
929
964
482
741
370
185
092
046
523
761
880
940
970
985
992
996
998
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999
999

5
75
375
687
843
421
210
605
302
651
325
162
581
790
395
197
098
549
274
137
068
534
767
883
941
970
985
992
996
998
999
999
999
999
999
999
999
999

5
75
875
937
468
734
367
683
841
420
710
355
677
838
419
709
354
677
338
169
584
792
896
448
724
362
181
090
545
772
886
943
971
985
992

5
75
375
187
593
796
898
449
244
612
806
403
701
850
425
712
356
678
339
169
034
042
021
010
505
252
626
313
156
578
789
894

5
75
875
437
218
609
304
152
076
538
769
384
692
346
173
086
543
771
385
192
596
298
649
324
162
581
290
145
572

5
75
375
687
343
171
085
042
521
260
130
065
532
266
633
816
908
454
227
113
556
278
139
569
284
642

5
75
875
937
968
484
742
371
185
592
296
148
574
287
143
071
535
767
383
191
595
797
398

5
75
375
187
093
546
773
386
193
096
048
524
762
881
940
970
985
992
996
998

5
75
875
437
718
359
679
339
169
084
042
521
260
130
565
282
141

5
75
375
687
843
921
960
480
240
620
310
155
577
288

5
75
875
937
468
234
117
058
029
514
757

5
75
375
187 5
593 75
296 875
648 437 5
324218 75

48
49
50
51
52
53
54
55
56
57
58
59
60

.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999
.999

999
999
999
999
999
999
999
999
999
999
999
999
999

999
999
999
999
999
999
999
999
999
999
999
999
999

999
999
999
999
999
999
999
999
999
999
999
999
999

996
998
999
999
999
999
999
999
999
999
999
999
999

447
223
111
555
777
888
944
972
986
993
996
998
999

286
643
821
910
955
977
488
244
122
061
530
265
132

321
160
580
790
395
697
848
424
212
106
553
276
638

199
599
299
149
074
537
768
384
192
096
048
524
262

499
749
874
937
968
484
742
371
185
092
046
023
011

070
535
767
383
691
345
172
086
543
771
385
192
596

644
322
661
830
915
957
978
489
244
622
811
905
452

378
189
094
547
273
636
818
409
704
352
176
588
794

662
331
665
332
666
833
416
208
604
302
151
075
037

.

.

'Larger numbers wlthm a dIgIt group should be checked for exact number of deCImal dIgIts reqUIred .

Examples of use:
1. Q. What is the largest decimal value that can be expressed by 36 binary digits?

A. 68,719,476,735.
2. Q. How many decimal digits will be required to express a 22-bit number?

A. 7 decimal digits.

Rev. A

C-2

109
054
527
763
381
190
595
297
148
074
037
518
759

375
687
343
671
835
917
458
729
864
432
216
608
304

5
75
875
937
968
984
492
746
373
186
093
046

5
75
375
187
093
046
523
261
630

5
75
875
437 5
718 75
859 375

OCTAL ARITHMETIC MATRICES

ADDITION-SUBTRACTION

2

3

4

5

6

7

10

3

4

5

6

7

10

11

4

5

6

7

10

11

12

5

6

7

10

11

12

13

6

7

10

11

12

13

14

7

10

11

12

13

14

15

11

12

13

14

15

16

M U l TlPLICATION-DIVISION

7

2

3

4

5

6

7

4

6

10

12

14

16

6

11

14

17

22

25

10

14

20

24

30

34

12

17

24

31

36

43

14

22

30

36

44

52

16

25

34

43

52

61

C-3

Rev. A

CONSTANTS

e
In 2
In 10
IOg102
10glO e
10glO 10glO e
10glo 7r
1 degree
1 radian
loglO(5)

3.14159 26535
1.732 050 807
3.162 277 660
2.71828 18284
0.69314 71805
2.30258 50929
0.30102 99956
0.43429 44819
9.63778 43113
0.49714 98726
0.01745 32925
57.29577 95131
0.69897 00043

7!
8!
9!
10!
11 !
12!
13!
14!
15!
16!

5040
40320
362.880
3.628.800
39.916.800
479.001.600
6.227.020.800
87.178.291.200
1.307.674.368.000
20.922.71:'9.888.000

7r

V3

VTO

~

180

23846 26433 83279 50

23536
68402
82765
-10
85435
radians

0.01745 32925 19943 29576 92369 07684 9

Hj2

2.4674 01100 27233 96

tf13

3.8757 84585 03747 74

tf14

6.0880 68189 62515 20

H1

9.5631

5

15149 54004 49

tf16

15.0217 06149 61413 07

~7

23.5960 40842 00618 62

~8

37.0645 72481

52567 57

k19

58.2208 97135 63712 59

( ;}o

91.4531

(;t

(;}2
(;t
(1714

Rev. A

89793
569
1683
59045
599453
94045
63981
03251
00537
94133
11943
degrees
36019

71363 36231

143.6543 05651

53

31374 95

225.6516 55645 350
354.4527 91822 91051
556.7731

C-4

43417 624

47

CONSTANTS (Continued)

7r 2
27r 2
37r 2
47r 2
57r 2
67r 2
77r 2
87r 2
97r 2

V'2
1 + v'2'
(1 + yl2)2
(1 + yl2)4
(1 + V2)6
(1 + V2)8
(1 + V 2 )'0
(1 + V2)12
(1 + V2)14
(1 + V2)16
(1 + V'2')18

Sin .5

9.86960
19.73920
29.60881
39.47841
49.34802
59.21762
69.08723
78.95683
88.82643

=
=
=
=

44010
88021
32032
76043
20054
64065
08076
52087
96098

1.414
2.414
5.828
33.970
197.994
1153.999
6725.999
39201.999
228485.999
1331713.999
7761797.999

213
213
427
562
949
133
851
974
995
999
999

61883
23766
85680
47533
09417
71300
33184
95067
56950

89358
78717
68075
57434
46793
36151
25510
14868
04227

562
562
124
748
366
448
323
491
622
246
884

373
373
746
477
116
220
208
027
956
711
751

Cos .5
Tan .5

0.47942 55386 04203
0.87758 i5618 90373
0.54630 24898 43790

Sin 1
Cos 1
Tan 1

0.84147 09848 07896
0.54030 23058 68140
1.55740 77246 5490

Sin 1.5
Cos 1.5
Tan 1.5

43909
87819
31729
75639
19549
63459
07369
51279
95189

9988
9976
9964
9952
9940
9928
9916
9904
9892

095 048 801 688
095 048 801 688
18
08
30
72
02
40
38

0.99749 49866 04054
0.07073 72016 67708
14.10141 99471 707

C-5

Rev. A

OCTAL-DECIMAL INTEGER CONVERSION TABLE

0000
0010
0020
0030
0040
0050
0060
0070

0

1

2

3

4

0000
0008
0016
0024
0032
0040
0048
0056

0001
0009
0017
0025
0033
0041
0049
0057

0002
0010
0018
0026
0034
0042
0050
0058

0003
0011
0019
0027
0035
0043
0051
0059

0004
0012
0020
0028
0036
0044
0052
0060

5

6

0005
0013
0021
0029
0037
0045
0053
0061

0

1

2

3

0256
0264
0272
0280
0288
0296
0304
0312

0257
0265
0273
0281
0289
0297
0305
0313

0258
0266
0274
0282
0290
0298
0306
0314

0259
0267
0275
0283
0291
0299
0307
0315

7

0006
0014
0022
0030
0038
0046
0054
0062

0007
0015
0023
0031
0039
0047
0055
0063

0400
0410
0420
0430
0440
0450
0460
0470

4
0260
0268
0276
0284
0292
0300
0308
0316

5
0261
0269
0277
0285
0293
0301
0309
0317

6

7

0262
0270
0278
0286
0294
0302
0310
0318

0263
0271
0279
0287
0295
0303
0311
0319

0100
0110
0120
0130
0140
0150
0160
0170

0064
0072
0080
0088
0096
0104
0112
0120

0065
0073
0081
0089
0097
0105
0113
0121

0066
0074
0082
0090
0098
0106
0114
0122

0067
0075
0083
0091
0099
0107
0115
0123

0068
0076
0084
0092
0100
0108
0116
0124

0069
0077
0085
0093
0101
0109
0117
0125

0070
0078
0086
0094
0102
0110
0118
0126

0071
0079
0087
0095
0103
0111
0119
0127

0500
0510
0520
0530
0540
0550
0560
0570

0320
0328
0336
0344
0352
0360
0368
0376

0321
0329
0337
0345
0353
0361
0369
0377

0322
0330
0338
0346
0354
0362
0370
0378

0323
0331
0339
0347
0355
0363
0371
0379

0324
0332
0340
0348
0356
0364
0372
0380

0325
0333
0341
0349
0357
0365
0373
0381

0326
0334
0342
0350
0358
0366
0374
0382

0327
0335
0343
0351
0359
0367
0375
0383

0200
0210
0220
0230
0240
0250
0260
0270

0128
0136
0144
0152
0160
0168
0176
0184

0129
0137
0145
0153
0161
0169
0177
0185

0130
0138
0146
0154
0162
0170
0178
0186

0131
0139
0147
0155
0163
0171
0179
0187

0132
0140
0148
0156
0164
0172
0180
0188

0133
0141
0149
0157
0165
0173
0181
0189

0134
0142
0150
0158
0166
0174
0182
0190

0135
0143
0151
0159
0167
0175
0183
0191

0600
0610
0620
0630
0640
0650
0660
0670

0384
0392
0400
0408
0416
0424
0432
0440

0385
0393
0401
0409
0417
0425
0433
0441

0386
0394
0402
0410
0418
0426
0434
0442

0387
0395
0403
0411
0419
0427
0435
0443

0388
0396
0404
0412
0420
0428
0436
0444

0389
0397
0405
0413
0421
0429
0437
0445

0390
0398
0406
0414
0422
0430
0438
0446

0391
0399
0407
0415
0423
0431
0439
0447

0300
0310
0320
0330
0340
0350
0360
0370

0192
0200
0208
0216
0224
0232
0240
0248

0193
0201
0209
0217
0225
0233
0241
0249

0194
0202
0210
0218
0226
0234
0242
0250

0195
0203
0211
0219
0227
0235
0243
0251

0196
0204
0212
0220
0228
0236
0244
0252

0197
0205
0213
0221
0229
0237
0245
0253

0198
0206
0214
0222
0230
0238
0246
0254

0199
0207
0215
0223
0231
0239
0247
0255

0700
0710
0720
0730
0740
0750
0760
0770

0448
0456
0464
0472
0480
0488
0496
0504

0449
0457
0465
0473
0481
0469
0497
0505

0450
0458
0466
0474
0482
0490
0498
0506

0451
0459
0467
0475
0483
0491
0499
0507

0452
0460
0468
0476
0464
0492
0500
0508

0453
0461
0469
0477
0485
0493
0501
0509

0454
0462
0470
0478
0486
0494
0502
0510

0455
0463
0471
0479
0487
0495
0503
0511

0

1

2

3

4

5

0

1

i

3

4

6

7

1000
1010
1020
1030
1040
1050
1060
1070

0512
0520
0528
0536
0544
0552
0560
0568

0513
0521
0529
0537
0545
0553
0561
0569

0514
0522
0530
0538
0546
0554
0562
0570

0515
0523
0531
0539
0547
0555
0563
0571

0516
0524
0532
0540
0548
0556
0564
0572

0517
0525
0533
0541
0549
0557
0565
0573

0518
0526
0534
0542
0550
0558
0566
0574

0519
0527
0535
0543
0551
0559
0567
0575

1400
1410
1420
1430
1440
1450
1460
1470

0768
0776
0784
0792
0800
0808
0816
0824

0769
0777
0785
0793
0801
0809
0817
0825

0770
0778
0786
0794
0802
0810
0818
0826

0771
0779
0787
0795
0803
0811
0819
0827

0772
0780
0788
0796
0804
0812
0820
0828

0773
0781
0789
0797
0805
0813
0821
0829

0774
0782
0790
0798
0806
0814
0822
0830

0775
0783
0791
0799
0807
0815
0823
0831

1100
1110
1120
1130
1140
1150
1160
1170

0576
0584
0592
0600
0608
0616
0624
0632

0577
0585
0593
0601
0609
0617
0625
0633

0578
0586
0594
0602
0610
0618
0626
0634

0579
0587
0595
0603
0611
0619
0627
0635

0580
0588
0596
0604
0612
0620
0628
0636

0581
0589
0597
0605
0613
0621
0629
0637

0582
0590
0598
0606
0614
0622
0630
0638

0583
0591
0599
0607
0615
0623
0631
0639

1500
1510
1520
1530
1540
1550
1560
1570

0832
0840
0848
0856
0864
0872
0880
0888

0833
0841
0849
0857
0865
0873
0881
0889

0834
0842
0850
0858
0866
0874
0882
0890

0835
0843
0851
0859
0867
0875
0883
0891

0836
0844
0852
0860
0868
0876
0884
0892

0837
0845
0853
0861
0869
0877
0885
0893

0838
0846
0854
0862
0870
0878
0886
0894

0839
0847
0855
0863
0871
0879
0887
0895

1200
1210
1220
1230
1240
1250
1260
1270

0640
0648
0656
0664
0672
0680
0688
0696

0641
0649
0657
0665
0673
0681
0689
0697

0642
0650
0658
0666
0674
0682
0690
0698

0643
0651
0659
0667
0675
0683
0691
0699

0644
0652
0660
0668
0676
0684
0692
0700

0645
0653
0661
0669
0677
0685
0693
0701

0646
0654
0662
0670
0678
0686
0694
0702

0647
0655
0663
0671
0679
0687
0695
0703

1600
1610
1620
1630
1640
1650
1660
1670

0896
0904
0912
0920
0928
0936
0944
0952

0897
0905
0913
0921
0929
0937
0945
0953

0898
0906
0914
0922
0930
0938
0946
0954

0899
0907
0915
0923
0931
0939
0947
0955

0900
0908
0916
0924
0932
0940
0948
0956

0901
0909
0917
0925
0933
0941
0949
0957

0902
0910
0918
0926
0934
0942
0950
0958

0903
0911
0919
0927
0935
0943
0951
0959

1300
1310
1320
1330
1340
1350
1360
1310

0704
0712
0720
0728
0736
0744
0752
0760

0705
0713
0721
0729
0737
0745
0753
0761

0706
0714
0722
0730
0738
0746
0754
0762

0707
0715
0723
0731
0739
0747
0755
0763

0708
0716
0724
0732
0740
0748
0756
0764

0709
0717
0725
0733
0741
0749
0757
0765

0710
0718
0726
0734
0742
0750
0758
0766

0711
0719
0727
0735
0743
0751
0759
0767

1700
1710
1720
1730
1740
1750
1760
1770

0960
0968
0976
0984
0992
1000
1008
1016

0961
0969
0977
0985
0993
1001
1009
1017

0962
0970
0978
0986
0994
1002
1010
1018

0963
0971
0979
0987
0995
1003
1011
1019

0964
0972
0980
0988
0996
1004
1012
1020

0965
0973
0981
0989
0997
1005
1013
1021

0966
0974
0982
0990
0998
1006
1014
1022

0967
0975
0983
0991
0999
1007
1015
1023

Rev. A

6

7

C-6

5

0000
to
0777
10ctal)

OODO
to
0511
lDecimal)

Octal

Decimal

10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672

1000
to
1777
10ctal)

0512
to
1023
IOecimal)

OCTAL-DECIMAL INTEGER CONVERSION TABLE (Cont'd)

2000

1024

10

10

2777
10claii

1535
10eCimal)

Octal

10000·
20000 .
30000 .
40000·
50000·
60000·
70000·

3000

Decimal

4096
8192
12288
16384
20480
24576
28672

1536

10

to

3777
10claii

2047
10ecimal)

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

2000
2010
2020
2030
2040
2050
2060
2070

1024
1032
1040
1048
1056
1064
1072
1080

1025
1033
1041
1049
1057
1065
1073
1081

1026
1034
1042
1050
1058
1066
1074
1082

1027
1035
1043
1051
1059
1067
1075
1083

1028
1036
1044
1052
1060
1068
1076
1084

1029
1037
1045
1053
1061
1069
1077
1085

1030
1038
1046
1054
1062
1070
1078
1086

1031
1039
1047
1055
1063
1071
1079
1087

2400
2410
2420
2430
2440
2450
2460
2470

1280
1288
1296
1304
1312
1320
1328
1336

1281
1289
1297
1305
1313
1321
1329
1337

1282
1290
1298
1306
1314
1322
1330
1338

1283
1291
1299
1307
1315
1323
1331
1339

1284
1292
1300
1308
1316
1324
1332
1340

1285
1293
1301
1309
1317
1325
1333
1341

1286
1294
1302
1310
1318
1326
1334
1342

1287
1295
1303
1311
1319
1327
1335
1343

2100
2110
2120
2130
2140
2150
2160
2170

1088
1096
1104
1112
1120
1128
1136
1144

1089
1097
1105
1113
1121
1129
1137
1145

1090
1098
1106
1114
1122
1130
1138
1146

1091
1099
1107
1115
1123
1131
1139
1147

1092
1100
1108
1116
1124
1132
1140
1148

1093
1101
1109
1117
1125
1133
1141
1149

1094
1102
1110
1118
1126
1134
1142
1150

1095
1103
1111
1119
1127
1135
1143
1151

2500
2510
2520
2530
2540
2550
2560
2570

1344
1352
1360
1368
1376
1384
1392
1400

1345
1353
1361
1369
1377
1385
1393
1401

1346
1354
1362
1370
1378
1386
1394
1402

1347
1355
1363
1371
1379
1387
1395
1403

1348
1356
1364
1372
1380
1388
1396
1404

1349
1357
1365
1373
1381
1389
1397
1405

1350
1358
1366
1374
1382
1390
1398
1406

1351
1359
1367
1375
1383
1391
1399
1407

2200
2210
2220
2230
2240
2250
2260
2270

1152
1160
1168
1176
1184
1192
1200
1208

1153
1161
1169
1177
1185
1193
1201
1209

1154
1162
1170
1178
1186
1194
1202
1210

1155
1163
1171
1179
1187
1195
1203
1211

1156
1164
1172
1180
1188
1196
1204
1212

1157
1165
1173
1181
1189
1197
1205
1213

1158
1166
1174
1182
1190
1198
1206
1214

1159
1167
1175
1183
1191
1199
1207
1215

2600
2610
2620
2630
2640
2650
2660
2670

1408
1416
1424
1432
1440
1448
1456
1464

1409
1417
1425
1433
1441
1449
1457
1465

1410
1418
1426
1434
1442
1450
1458
1466

1411
1419
1427
1435
1443
1451
1459
1467

1412
1420
1428
1436
1444
1452
1460
1468

1413
1421
1429
1437
1445
1453
1461
1469

1414 1415
1422 1423
1430 A431
1438 1439
1446 1447
1454 1455
1462 1463
1470 1471

2300
2310
2320
2330
2340
2350
2360
2370

1216
1224
1232
1240
1248
1256
1264
1272

1217
1225
1233
1241
1249
1257
1265
1273

1218
1226
1234
1242
1250
1258
1266
1274

1219
1227
1235
1243
1251
1259
1267
1275

1220
1228
1236
1244
1252
1260
1268
1276

1221
1229
1237
1245
1253
1261
1269
1277

1222
1230
1238
1246
1254
1262
1270
1278

1223
1231
1239
1247
1255
1263
1271
1279

2700
2710
2720
2730
2740
2750
2760
2770

1472
1480
1488
1496
1504
1512
1520
1528

1473
1481
1489
1497
1505
1513
1521
1529

1474
1482
1490
1498
1506
1514
1522
1530

1475
1483
1491
1499
1507
1515
1523
1531

1476
1484
1492
1500
1508
1516
1524
1532

1477
1485
1493
1501
1519
1517
1525
1533

1478
1486
1494
1502
1510
1518
1526
1534

1479
1487
1495
1503
1511
1519
1527
1535

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

3000
3010
3020
3030
3040
3050
3060
3070

1536
1544
1552
1560
1568
1576
1584
1592

1537
1545
1553
1561
1569
1577
1585
1593

1538
1546
1554
1562
1570
1578
1586
1594

1539
1547
1555
1563
1571
1579
1587
1595

1540
1548
1556
1564
1572
1580
1588
1596

1541
1549
1557
1565
1573
1581
1589
1597

1542
1550
1558
1566
1574
1582
1590
1598

1543
1551
1559
1567
1575
1583
1591
1599

3400
3410
3420
3430
3440
3450
3460
3470

1792
1800
1808
1816
1824
1832
1840
1848

1793
1801
1809
1817
1825
1833
1841
1849

1794
1802
1810
1818
1826
1834
1842
1850

1795
1803
1811
1819
1827
1835
1843
1851

1796
1804
1812
1820
1828
1836
1844
1852

1797
1805
1813
1821
1829
1837
1845
1853

1798
1806
1814
1822
1830
1838
1846
1854

1799
1807
1815
1823
1831
1839
1847
1855

3100
3110
3120
3130
3140
3150
3160
3170

1600
1608
1616
1624
1632
1640
1648
1656

1601
1609
1617
1625
1633
1641
1649
1657

1602
1610
1618
1626
1634
1642
1650
1658

1603
1611
1619
1627
1635
1643
1651
1659

1604
1612
1620
1628
1636
1644
1652
1660

1605
1613
1621
1629
1637
1645
1653
1661

1606
1614
1622
1630
1638
1646
1654
1662

1607
1615
1623
1631
1639
1647
1655
1663

3500
3510
3520
3530
3540
3550
3560
3570

1856
1864
1872
1880
1888
1896
1904
1912

1857
1865
1873
1881
1889
1897
1905
1913

1858
1866
1874
1882
1890
1898
1906
1914

1859
1867
1875
1883
1891
1899
1907
1915

1860
1868
1876
1884
1892
1900
1908
1916

1861
1869
1877
1885
1893
1901
1909
1917

1862
1870
1878
1886
1894
1902
1910
1918

1863
1871
1879
1887
1895
1903
191 J
1919

3200
3210
3220
3230
3240
3250
3260
3270

1664
1672
1680
1688
1696
1704
1712
1720

1665
1673
1681
1689
1697
1705
1713
1721

1666
1674
1682
1690
1698
1706
1714
1722

1667
1675
1683
1691
1699
1707
1715
1723

1668
1676
1684
1692
1700
1708
1716
1724

1669
1677
1685
1693
1701
1709
1717
1725

1670
1678
1686
1694
1702
1710
1718
1726

1671
1679
1687
1695
1703
1711
1719
1727

3600
3610
3620
3630
3640
3650
3660
3670

1920
1928
1936
1944
1952
1960
1968
1976

1921
1929
1937
1945
1953
1961
1969
1977

1922
1930
1938
1946
1954
1962
1970
1978

1923
1931
1939
1947
1955
1963
1971
1979

1924
1932
1940
1948
1956
1964
1972
1980

1925
1933
1941
1949
1957
1965
1973
1981

1926
1934
1942
1950
1958
1966
1974
1982

1927
1935
1943
1951
1959
1967
1975
1983

3300
3310
3320
3330
3340
3350
3360
3370

1728
1736
1744
1752
1760
1768
1776
1784

1729
1737
1745
1753
1761
1769
1777
1785

1730
1738
1746
1754
1762
1770
1778
1786

1731
1739
1747
1755
1763
1771
1779
1787

1732
1740
1748
1756
1764
1772
1780
1788

1733
1741
1749
1757
1765
1773
1781
1789

1734
1742
1750
1758
1766
1774
1782
1790

1735
1743
1751
1759
1767
1775
1783
1791

3700
3710
3720
3730
3740
3750
3760
3770

1984
1992
2000
2008
2016
2024
2032
2040

1985
1993
2001
2009
2017
2025
2033
2041

1986
1994
2002
2010
2018
2026
2034
2042

1987
1995
2003
2011
2019
2027
2035
2043

1988
1996
2004
2012
2020
2028
2036
2044

1989
1997
2005
2013
2021
2029
2037
2045

1990
1998
2006
2014
2022
2030
2038
2046

1991
1999
2007
2015
2023
2031
2039
2047

C-7

Bev. B

OCTAL-DECIMAL INTEGER CONVERSION TABLE (Cont'd)

0
4000
4010
.020
4030
4040
4050
4060
4070

2048
2056
2064
2072
2080
2088
2096
2104

2

2049
2057
2065
2073
2081
2089
2097
2105

2050
2058
2066
2074
2082
2090
2098
2106

3
2051
2059
2067
2075
2083
2091
2099
2107

4

5

2052
2060
2068
2076
2084
2092
2100
2108

2053
2061
2069
2077
2085
2093
2101
2109

6
2054
2062
2070
2078
2086
2094
2102
2110

7
2055
2063
2071
2079
2087
2095
2103
2111

4400
4410
4420
4430
4440
4450
4460
4470

0

1

2

3

4

5

6

7

2304
2312
2320
2328
2336
2344
2352
2360

2305
2313
2321
2329
2337
2345
2353
2361

2306
2314
2322
2330
2338
2346
2354
2362

2307
2315
2323
2331
2339
2347
2355
2363

2308
2316
2324
2332
2340
2348
2356
2364

2309
2317
2325
2333
2341
2349
2357
2365

2310
2318
2326
2334
2342
2350
2358
2366

2311
2319
2327
2335
2343
2351
2359
2367

2372
2380
2388
2396
2404
2412
2420
2428

2373
2381
2389
2397
2405
2413
2421
2429

2374
2382
2390
2398
2406
2414
2422
2430

2375
2383
2391
2399
2407
2415
2423
2431

4100
4110
4120
4130
4140
4150
4160
4170

2112
2120
2128
2136
2144
2152
2160
2168

2113
2121
2129
2137
2145
2153
2161
2169

2114
2122
2130
2138
2146
2154
2162
2170

2115
2123
2131
2139
2147
2155
2163
2171

2116
2124
2132
2140
2148
2156
2164
2172

2117
2125
2133
2141
2149
2157
2165
2173

2118
2126
2134
2142
2150
2158
2166
2174

2119
2127
2135
2143
2151
2159
2167
2175

4500
4510
4520
4530
4540
4550
4560
4570

2368
2376
2384
2392
2400
2408
2416
2424

2369
2377
2385
2393
2401
2409
2417
2425

2370
2378
2386
2394
2402
2410
2418
2426

2371
2379
2387
2395
2403
2411
2419
2427

4200
4210
4220
4230
4240
4250
4260
4270

2176
2184
2192
2200
2208
2216
2224
2232

2177
2185
2193
2201
2209
2217
2225
2233

2178
2186
2194
2202
2210
2218
2226
2234

2179
2187
2195
2203
2211
2219
2227
2235

2180
2188
2196
2204
2212
2220
2228
2236

2181
2189
2197
2205
2213
2221
2229
2237

2182
2190
2198
2206
2214
2222
2230
2238

2183
2191
2199
2207
2215
2223
2231
2239

4600
4610
4620
4630
4640
4650
4660
4670

2432
2440
2448
2456
2464
2472
2480
2488

2433
2441
2449
2457
2465
2473
2481
2489

2434
2442
2450
2458
2466
2474
2482
2490

2435
2443
2451
2459
2467
2475
2483
2491

2436
2444
2452
2460
2468
2476
2484
2492

2437
2445
2453
2461
2469
2477
2485
2493

2438
2446
2454
2462
2470
2478
2486
2494

2439
2447
2455
2463
2471
2479
2487
2495

4300
4310
4320
4330
4340
4350
4360
4370

2240
2248
2256
2264
2272
2280
2288
2296

2241
2249
2257
2265
2273
2281
2289
2297

2242
2250
2258
2266
2274
2282
2290
2298

2243
2251
2259
2267
2275
2283
2291
2299

2244
2252
2260
2268
2276
2284
2292
2300

2245
2253
2261
2269
2277
2285
1293
2301

2246
2254
2262
2270
2278
2286
2294
2302

2247
2255
2263
2271
2279
2L:!7
2295
2303

4700
4710
4720
4730
4740
4750
4760
4770

2496
2504
2512
2520
2528
2536
2544
2552

2497
2505
2513
2521
2529
2537
2545
2553

2498
2506
2514
2522
2530
2538
2546
2554

2499
2507
2515
2523
2531
2539
2547
2555

2500
2508
2516
2524
2532
2540
2548
2556

2501
2509
2517
2525
2533
1541
2549
2557

2502
2510
2518
2526
2534
2542
2550
2558

2503
2511
2519
2527
2535
2543
2551
2559

1

2

4

5

6

7

0

1

2

3

4

5

6

7

0

Rev. A

1

3

5000
5010
5020
5030
5040
5050
5060
5070

2560
2568
2576
2584
2592
2600
2608
2616

2561
2569
2577
2585
2593
2601
2609
2617

2562
2570
2578
2586
2594
2602
2610
2618

2563
2571
2579
2587
2595
2603
2611
2619

2564
2572
2580
2588
2596
2604
2612
2620

2565
2573
2581
2589
2597
2605
2613
2621

2566
2574
2582
2590
2598
2606
2614
2622

2567
2575
2583
2591
2599
2607
2615
2623

5400
5410
5420
5430
5440
5450
5460
5470

2816
2824
2832
2840
2848
2856
2864
2872

2817
2825
2833
2841
2849
2857
2865
2873

2818
2826
2834
2842
2850
2858
2866
2874

2819
2827
2835
2843
2851
2859
2867
2875

2820
2828
2836
2844
2852
2860
2868
2876

2821
2829
2837
2845
2853
2861
2869
2877

2822
2830
2838
2846
2854
2862
2870
2878

2823
2831
2839
2847
2855
2863
2871
2879

5100
5110
5120
5130
5140
5150
5160
5170

2624
2632
2640
2648
2656
2664
2672
2680

2625
2633
2641
2649
2657
2665
2673
2681

2626
2634
2642
2650
2658
2666
2674
2682

2627
2635
2643
2651
2659
2667
2675
2683

2628
2636
2644
2652
2660
2668
2676
2684

2629
2637
2645
2653
2661
2669
2677
2685

2630
2638
2646
2654
2662
2670
2678
2686

2631
2639
2647
2655
2663
2671
2679
2687

5500
5510
5520
5530
5540
5550
5560
5570

2880
2888
2896
2904
2912
2920
2928
2936

2881
2889
2897
2905
2913
2921
2929
2937

£882
2890
2898
2906
2914
2922
2930
2938

2883
2891
2899
2907
2915
2923
2931
2939

2884
2892
2900
2908
2916
2924
2932
2940

2885
2893
2901
2909
2917
2925
2933
2941

2886
2894
2902
2910
2918
2926
2934
2942

2887
2895
2903
2911
2919
2927
2935
2943

5200
5210
5220
5230
5240
5250
5260
5270

2688
2696
2704
2712
2720
2728
2736
2744

2689
2697
2705
2713
2721
2729
2737
2745

2690
2698
2706
2714
2722
2730
2738
2746

2691
2699
2707
2715
2723
2731
2739
2747

2692
2700
2708
2716
2724
2732
2740
2748

2693
2701
2709
2717
2725
2733
2741
2749

2694
2702
2710
2718
2726
2734
2742
2750

2695
2703
2711
2719

2944
2952
2960
2968
2976
2984
2992
3000

2945
2953
2961
2969
2977
2985
2993
3001

2946
2954
2962
2970
2978
2986
2994
3002

2947
2955
2963
2971
2979
2987
2995
3003

2948
2956
2964
2972
2980
2988
2996
3004

2949
2957
2965
2973

2735
2743
2751

5600
5610
5620
5630
5640
5650
5660
5670

2989
2997
3005

2950
2958
2966
2974
2982
2990
2998
3006

2951
2959
2967
2975
2983
2991
2999
3007

5300
5310
5320
5330
5340
5350
5360
5370

2752
2760
2768
2776
2784
2792
2800
2808

2753
2761
2769
2777
2785
2793
2801
2809

2754
2762
2770
2778
2786
2794
2802
2810

2755
2763
2771
2779
2787
2795
2803
2811

2756
2764
2772
2780
2788
2796
2804
2812

2757
2765
2773
2781
2789
2797
2805
2813

2758
2766
2774
2782
2790
2798
2806
2814

2759
2767
2775
2783
2791
2799
2807
2815

5700
5710
5720
5730'
5740
5750
5760
5770

3008
3016
3024
3032
3040
3048
3056
3064

3009
3017
3025
3033
3041
3049
3057
3065

3010
3018
3026
3034
3042
3050
3058
3066

3011
3019
3027
3035
3043
3051
3059
3067

3012
3020
3028
3036
3044
3052
3060
3068

3013
3021
3029
3037
3045
3053
3061
3069

3014
3022
3030
3038
3046
3054
3062
3070

3015
3023
3031
3039
3047
3055
3063
3071

2727

C-8

i981

4000

2048

to

10

4777
Wctall

2559
!DeclmaO

Oclal DeCImal
10000· 4096
20000· 8192
30000 . 12288
40000 16384
50000 20480
60000· 24576
70000· 28672

5000

2560

10

10

5777
10ciaii

3071
to'Cimal1

OCTAL-DECIMAL INTEGER CONVERSION TABLE (Cont'd)

0
6000
to
6777
!Delall

3072
to
3583
!Decima!)

Octal DecImal
10000· 4096
20000· 8192
30000 12288
40000 16384
50000 20480
60000· 24576
70000· 28672

7000
to
7777
(Octal)

3584
10

4095
!Decimal!

,

2

3

4

5

6

,

0

7

2

3

4

5

6

7

6000
6010
6020
5030
6040
6050
6060
6070

3072
3080
3088
3096
3104
3112
3120
3128

3073
3081
3089
3097
3105
3113
3121
3129

3074
3082
3090
3098
3106
3114
3122
3130

3075
3083
3091
3099
3107
3115
3123
3131

3076
3084
3092
3100
3108
3116
3124
3132

3077
3085
3093
3101
3109
3117
3125
3133

3078
3086
3094
3102
3110
3118
3126
3134

3079
3087
3095
3103
3111
3119
3127
3135

6400
6410
6420
6430
6440
6450
6460
6470

3328
3336
3344
3352
3360
3368
3376
3384

3329
3337
3345
3353
3361
3369
3377
3385

3330
3338
3346
3354
3362
3"70
3378
3386

3331
3339
3347
3355
3363
3371
3379
3387

3332
3340
3348
3356
3364
3372
3380
3388

3333
3341
3349
3357
3365
3373
3381
3389

3334
3342
3350
3358
3366
3374
3382
3390

3335
3343
3351
3359
3367
3375
3383
3391

6100
6110
6120
6130
6140
6150
6160
6170

3136
3144
3152
3160
3168
3176
3184
3192

3137
3145
3153
3161
3169
3177
3185
3193

3138
3146
3154
3162
3170
3178
3186
3194

3139
3147
3155
3163
3171
3179
3187
3195

3140
3148
3156
3164
3172
3180
3188
3196

3141
3149
3157
3165
3173
3181
3189
3197

3142
3150
3158
3166
3174
3182
3190
3198

314J 1
3151
3159
3167
3175
3183
3191
3199

6500
6510
6520
6530
6540
6550
6560
6570

3392
3400
3408
3416
3424
3432
3440
3448

3393
3401
3409
3417
3425
3433
3441
3449

3394
3402
3410
3418
3426
3434
3442
3450

3395
3403
3411
3419
3427
3435
3443
3451

3396
3404
3412
3420
3428
3436
3444
3452

3397
3405
3413
3421
3429
3437
3445
3453

3398
3406
3414
3422
3430
3438
3446
3454

3399
3407
3415
3423
3431
3439
3447
3455

6200
6210
6220
6230
6240
6250
6260
6270

3200
3208
3216
3224
3232
3240
3248
3256

3201
3209
3217
3225
3233
3241
3249
3257

3202
3210
3218
3226
3234
3242
3250
3258

3203
3211
3219
3227
3235
3243
3251
3259

3204
3212
3220
3228
3236
3244
3252
3260

3205
3213
3221
3229
3237
3245
3253
3261

3206
3214
3222
3230
3238
3246
3254
3262

3207
3215
3223
3231
3239
3247
3255
3263

6600
6610
6620
6630
6640
6650
6660
6670

3456
3464
3472
3480
3488
3496
3504
3512

3457
3465
3473
3481
3489
3497
3505
3513

3458
3466
3474
3482
3490
3498
3506
3514

3459
3467
3475
3483
3491
3499
3507
3515

3460
3468
3476
3484
3492
3500
3508
3516

3461
3469
3477
3485
3493
3501
3509
3517

3462
3470
3478
3486
3494
3502
3510
3518

3463
3471
3479
3487
3495
3503
3511
3519

6300
6310
6320
6330
6340
6350
6360
6370

3264
3272
3280
3288
3296
3304
3312
3320

3265
3273
3281
3289
3297
3305
3313
3321

3266
3274
3292
3290
3298
3306
3314
3322

3267
3275
3283
3291
3299
3307
3315
3323

3268
3276
3284
3292
3300
3308
3316
3324

3269
3277
3285
3293
3301
3309
3317
3325

3270
3278
3286
3294
3302
3310
3318
3326

3271
3279
3287
3295
3303
3311
3319
3327

6700
6710
6720
6730
6740
6750
6760
6770

3520
3528
3536
3544
3552
3560
3568
3576

3521
3529
3537
3545
3553
3561
3569
3577

3522
3530
3538
3546
3554
3562
3570
3578

3523
3531
3539
3547
3555
3563
3571
3579

3524
3532
3540
3548
3556
3564
3572
358IJ

3525
3533
3541
3549
3557
3565
3573
3581

3526
3534
3542
3550
3558
3566
3574
3582

3527
3535
3543
3551
3559
3567
3575
3583

0

,

2

3

4

5

6

7

0

,

2

3

4

5

6

7000
7010
7020
7030
7040
7050
7060
7070

3584
3592
3600
3608
3616
3624
3632
3640

3585
3593
3601
3609
3617
3625
3633
3641

3586
3594
3602
3610
3618
3626
3634
3642

3587
3595
3603
3611
3619
3627
3635
3643

3588
3596
3604
3612
3620
3628
3636
3644

3589
3597
3605
3613
3621
3629
3637
3645

3590
3598
3606
3614
3622
3630
3638
3646

3591
3599
3607
3615
3623
3631
3639
3647

7400
7410
7420
7430
7440
7450
7460
7470

3840
3848
3856
3864
3872
3880
3888
3896

3841
3849
3857
3865
3873
3881
3889
3897

3842
3850
3858
3866
3874
3882
3890
3898

3843
3851
3859
3867
3875
3883
3891
3899

3844
3852
3860
3868
3876
3884
3892
3900

3845
3853
3861
3869
3877
3885
3893
3901

3846
3854
3862
3870
3878
3886
3894
3902

3847
3855
3863
3871
3879
3887
3895
3903

7100
7110
7120
7130
7140
7150
7160
7170

3648
3656
3664
3672
3680
3688
3696
3704

3649
3657
3665
3673
3681
3689
3697
3705

3650
3658
3666
3674
3682
3690
3698
3706

3651
3659
3667
3675
3683
3691
3699
3707

3652
3660
3668
3676
3684
3692
3700
3708

3653
3661
3669
3677
3685
3693
3701
3709

3654
3662
3670
3678
3686
3694
3702
3710

3655
3663
3671
3679
3687
3695
3703
3711

7500
7510
7520
7530
7540
7550
7560
7570

3904
3912
3920
3928
3936
3944
3952
3960

3905
3913
3921
3929
3937
3945
3953
3961

3906
3914
3922
3930
3938
3946
3954
3962

3907
3915
3923
3931
3939
3947
3955
3963

3908
3916
3924
3932
3940
3948
3956
3964

3909
3917
3925
3933
3941
3949
3957
3965

3910
3918
3926
3934
3942
3950
3958
3966

3911
3919
3927
3935
3943
3951
3959
3967

7200
7210
7220
7230
7240
7250
7260
7270

3712
3720
3728
3736
3744
3752
3760
3768

3713
3721
3729
3737
3745
3753
3761
3769

3714
3722
3730
3738
3746
3754
3762
3770

3115
3723
3731
3739
3747
3755
3763
3771

3716
3724
3732
3740
3748
3756
3764
3772

3717
3725
3733
3741
3749
3757
3765
3773

3718
3726
3734
3742
3750
3758
3766
3774

3719
3727
3735
3743
3751
3j'59
3767
3775

7600
7610
7620
7630
7640
7650
7660
7670

3968
3976
3984
3992
4000
4008
4016
4024

3969
3977
3985
3993
4001
4009
4017
4025

3970
3978
3986
3994
4002
4010
4018
4026

3971
3979
3987
3995
4003
4011
4019
4027

3972
3980
3988
3996
4004
4012
4020
4028

3973
3981
3989
3997
4005
4013
4021
4029

3974
3982
3990
3998
4006
4014
4022
4030

3975
3983
3991
3999
4007
4015
4023
4031

7300
7310
7320
7330
7340
7350
7360
7370

3776
3784
3792
3800
3808
3816
3824
3832

3777
3785
3793
3801
3809
3817
3825
3833

3778
3786
3794
3602
3810
3818
3826
3834

3779
3787
3795
3803
3811
3819
3827
3835

3780
3788
3796
3804
3812
3820
3828
3836

3781
3789
3797
3805
3813
3821
3829
3837

3782
3790
3798
3806
3814
3822
3830
3838

3783
3791
3799
3807
3815
3823
3831
3839

7700
7710
7720
7730
7740
7750
7760
7770

4032
4040
4048
4056
4064
4072
4080
4088

4033
4041
4049
4057
4065
4073
4081
4089

4034
4042
4050
4058
4066
4074
4082
4090

4035
4043
4051
4059
4067
4075
4083
4091

4036
4044
4052
4060
4068
4076
4084
4092

4037
4045
4053
4061
4069
4077
4085
4093

4038
4046
4054
4062
4070
4078
4086
4094

4039
4047
4055
4063
4071
4079
4087
4095

C-9

7

Rev. F

OCTAL-DECIMAL FRACTION CONVERSION TABLE

DEC.

OCTAL

OCTAL

DEC.

OCTAL

DEC.

.000
001
.002
003
004
005
006
007

000000
001953
003906
005859
007812
009765
011718
013671

100
101
.102
103
104
105
106
107

125000
126953
128906
130859
132812
134765
136718
138671

200
201
202
203
204
205
206
207

250000
251953
253906
255859
257812
259765
261718
263671

300
301
302
303
304
305
306
307

375000
376953
378906
380859
382812
384765
386718
388671

010
011
012
.013
.014
015
016
017

015625
.017578
019531
.021484
.023437
.025390
027343
.029296

110
111
112
113
114
115
116
117

140625
142578
.144531
146484
148437
150390
152343
154296

210
211
212
213
214
215
216
217

265625
267578
269531
271484
273437
275390
277343
279296

310
311
312
313
314
315
316
317

390625
392578
394531
396484
398437
400390
402343
404296

020
021
.022
.023
.024
025
026
.027

031250
.033203
035156
.037109
039062
.041015
.042968
044921

.120
.121
122
.123
124
.125
126
.127

.156250
.158203
.160156
.162109
164062
.166015
.167968
.169921

220
221
222
223
224
225
226
227

281250
283203
285156
287109
289062
.291015
.292968
.294921

320
321
322
323
324
325
326
327

406250
408203
410156
.412109
414062
416015
417968
.419921

.030
.031
.032
.033
.034
.035
036
037

.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546

.130
.131
.132
133
.134
.135
.136
137

.171875
.173828
.175781
.177734
.179687
.181640
.183593
.185546

.230
.231
232
233
234
.235
236
237

296875
298828
.300781
.302734
.304687
306640
308593
.310546

.330
.331
.332
333
334
335
.336
337

.421875
423828
425781
.427734
429687
.431640
.433593
435546

.040
.041
.042
.043
.044
.045
.046
.047

.062500
.064453
.066406
.068359
.070312
.072265
.074218
076171

.140
.141
.142
.143
.144
.145
.146
.147

.187500
.189453
.191406
.193359
.195312
197265
199218
201171

240
241
.242
.243
244
.245
.246
247

.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171

340
341
342
343
344
345
346
347

.437500
.439453
441406
443359
445312
447265
449218
451171

.050
.051
052
053
.054
.055
.056
.057

.078125
.080078
.082031
.083984
.085937
.087890
.089843
.091796

.150
.151
.152
.153
.154
.155
.156
.157

.203125
.205078
.207031
.208984
210937
.212890
.214843
216796

.250
251
252
253
.254
255
.256
.257

'.328125
.330078
332031
333984
335937
337890
.339843
341796

350
351
352
353
.354
.355
356
357

453125
455078
457031
458984
460937
462890
.464843
.466796

.060
.061
.062
.063
.064
.065
.066
.067

.093750
095703
.097656
.099609
.101562
.103515
.105468
.107421

.160
.161
162
.163
164
165
.166
.167

.218750
.220703
.222656
.224609
.226562
.228515
230468
232421

260
261
262
263
264
265
266
267

343750
345703
347656
.349609
351562
353515
355468
357421

.360
361
362
363
364
365
.366
367

468750
470703
472656
474609
476562
478515
480468
482421

.070
.071
.072
.073
.074
.075
.076
.077

.109375
.111328
113281
115234
.117187
.119140
.121093
.123046

170
.171
172
.173
174
.175
.176
177

234375
.236328
238281
240234
242187
244140
246093
248046

270
271
272
273
274
275
276
277

359375
361328
363281
365234
367187
369140
371093
373046

370
371
.372
373
374
.375
.376
.377

484375
486328
488281
490234
.492187
.494140
.496093
.498046

OCTAL

Rev. A

DEC.

C-IO

OCTAL-DECIMAL FRACTION CONVERSION TABLE

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

.400
.401
.402
.403
.404
.405
.406
.407

.500000
.501953
.503906
.505859
.507812
.509765
.511718
.513671

.500
.501
.502
.503
.504
.505
.506
.507

.625000
.626953
.628906
.630859
.632812
.634765
.636718
.638671

.600
.601
.602
.603
.604
.605
.606
.607

.750000
.751953
.753906
.755859
.757812
.759765
.761718
.763671

.700
.701
.702
.703
.704
.705
.706
.707

.875000
.876953
.878906
.880859
.882812
.884765
.886718
.888671

.410
.411
.412
.413
.414
.415
.416
.417

.515625
.517578
.519531
.521484
.523437
.525390
.527343
.529296

.510
.511
.512
.513
.514
.515
.516
.517

.640625
.642578
.644531
.646484
.648437
.650390
.652343
.654296

.610
.611
.612
.613
.614
.615
.616
.617

.765625
.767578
.769531
.771484
.773437
.775390
.777343
.779296

.710
.711
.712
.713
.714
.715
.716
.717

.890625
.892578
.894531
.896484
.898437
.900390
.902343
.904296

.420
.421
.422
.423
.424
.425
.426
.427

.531250
.533203
.535156
.537109
.539062
.541015
.542968
.544921

.520
.521
.522
.523
.524
.525
.526
.527

.656250
.658203
.660156
.662109
.664062
.666015
.667968
.669921

.620
.621
.622
.623
.624
.625
.626
.627

.781250
.783203
.785156
.787109
.789062
.791015
.792968
.794921

.720
.721
.722
.723
.724
.725
.726
.727

.906250
.908203
.910156
.912109
.914062
.916015
.917968
.919921

.430
.431
.432
.433
.434
.435
.436
.437

.546875
.548828
.550781
.552734
.554687
.556640
.558593
.560546

.530
.531
.532
.533
.534
.535
.536
.537

.671875
:673828
.675781
.677734
.679687
.681640
.683593
.685546

.630
.631
.632
.633
.634
.635
.636
.637

.796875
.798828
.800781
.802734
.804687
.806640
.808593
.810546

.730
.731
.732
.733
.734
.735
.736
.737

.921875
.923828
.925781
.927734
.929687
.931640
.933593
.935546

.440
.441
.442
.443
.444
.445
.446
.447

.562500
.564453
.566406
.568359
.570312
.572265
.574218
.576171

.540
.541
.542
.543
.544
.545
.546
.547

.687500
.689453
.691406
.693359
.695312
.697265
.699218
.701171

.640
.6.41
.642
.643
.644
.645
.646
.647

.812500
.814453
.816406
.818359
.820312
.822265
.824218
.826171

.740
.741
.742
.743
.744
.745
.746
.747

.937500
.939453
.941406
.943359
.945312
.947265
.949218
.951171

.450
.451
.452
.453
.454
.455
.456
.457

.578125
.580078
.582031
.583984
.585937
.587890
.589843
.591796

.550
.551
.552
.553
.554
.555
.556
.557

.703125
.705078
.707031
.708984
.710937
.712890
.714843
.716796

.650
.651
.652
.653
.654
.655
.656
.657

.828125
.830078
.832031
.833984
.835937
.837890
.839843
.841796

.750
.751
.752
.753
.754
.755
.756
.757

.953125
.955078
.957031
.958984
.960937
.962890
.964843
.966796

.460
.461
.462
.463
.464
.465
.466
.467

.593750
.595703
.597656
.599609
.601562
.603515
.605468
.607421

.560
.561
.562
.563
.564
.565
.566
.567

.718750
.720703
.722656
.724609
.726562
.728515
.730468
.732421

.660
.661
.662
.663
.664
.665
.666
.667

.843750
.845703
.847656
.849609
.851562
.853515
.855468
.857421

.760
.761
.762
.763
.764
.765
.766
.767

.968750
.970703
.972656
.974609
.976562
.978515
.980468
.982421

.470
.471
.472
.473
.474
.475
.476
.477

.609375
.611328
.613281
.615234
.617187
.619140
.621093
.623046

.570
.571
.572
.573
.574
.575
.576
.577

.734375
.736328
.738281
.740234
.642187
.744140
.746093
.748046

.670
.671
.672
.673
.674
.675
.676
.677

.859375
.861328
.863281
.865234
.867187
.869140
.871093
.873046

.770
.771
.772
.773
.774
.775
.776
.777

.984375
.986328
.988281
.990234
.992187
.994140
.996093
.998046

C-ll

Rev H

OCTAL-DECIMAL FRACTION CONVERSION TABLE (Cont'd)

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC .

OCTAL

DEC.

.000000
.000001
.000002
.000003
.000004
.000005
.000006
.000007

.000000
.000003
.000007
.000011
.000015
.000019
.000022
.000026

.000100
.000101
.000102
.000103
.000104
.000105
.000106
.000107

.000244
.000247
.000251
.000255
.000259
.000263
.000267
.000270

.000200
.000201
.000202
.000203
.000204
.000205
.000206
.000207

.000488
.000492
.000495
.000499
.000503
.000507
.000511
.000514

.000300
.000301
.000302
.000303
.000304
.000305
.000306
.000307

.000732
.000736
.000740
.000743
.000747
.000751
.000755
.000759

.000010
.000011
.000012
.000013
.000014
.000015
,000016
,000017

.000030
.000034
.000038
.000041
.000045
.000049
,000053
.000057

.000110
.000111
.000112
.000113
.000114
.000115
,000116
.000117

.000274
.000278
.000282
.000286
.000289
.000293
.000297
.000301

.000210
.000211
.000212
.000213
.000214
,000215
,000216
.000217

.000518
.000522
.000526
.000530
.000534
.000537
,000541
,000545

.000310
.000311
.000312
.000313
.000314
,000315
.000316
,000317

.000762
.000766
.000770
.000774
.000778
,000782
,000785
,000789

,000020
,000021
.000022
,000023
.000024
,000025
.000026
.000027

,000061
,000064
,000068
,000072
,000076
.000080
,000083
.000087

,000120
.000121
,000122
,000123
,000124
.000125
,000126
,000127

.000305
.000308
,000312
,000316
,000320
,000324
,000328
.000331

,000220
.000221
,000222
.000223
,000224
,000225
,000226
,000227

,000549
.000553
.000556
,000560
,000564
.000568
.000572
.000576

,000320
,000321
,000322
.000323
,000324
,000325
.000326
.000327

,000793
,000797
,000801
,000805
,000808
,000812
,000816
,000820

,000030
,000031
,000032
,000033
.000034
.000035
,000036
.000037

,000091
,000095
.000099
,000102
.000106
.000110
,000114
.000118

,000130
,000131
.000132
.000133
,000134
,000135
,000136
,000137

,000335
,000339
,000343
,000347
.000350
.000354
,000358
.000362

,000230
,000231
,000232
,000233
,000234
,000235
,000236
,000237

,000579
.000583
.000587
.000591
,000595
,000598
.000602
,000606

.000330
.000331
,000332
,000333
.000334
,000335
.000336
,000337

,000823
,000827
.000831
,000835
.000839
.000843
,000846
,000850

.000040
.000041
,000042
.000043
.000044
,000045
,000046
,000047

.000122
,000125
,000129
,000133
,000137
.000141
,000144
,000148

,000140
.000141
.000142
,000143
.000144
,000145
,000146
,000147

,000366
.000370
,000373
.000377
,000381
.000385
,000389
.000392

.000240
,000241
.000242
.000243
,000244
,000245
,000246
.000247

,000610
,000614
,000617
,000621
.000625
,000629
,000633
.000637

,000340
,000341
,000342
,000343
,000344
,000345
,000346
,000347

,000854
.000858
.000862
.000865
,000869
,000873
,000877
,000881

,000050
.000051
,000052
,000053
,000054
,000055
.000056
,000057

,000152
,000156
,000160
,000164
.000167
,000171
,000175
.000179

,000150
.000151
.000152
.000153
.000154
,000155
.000156
.000157

,000396
.000400
,000404
,000408
,000411
,000415
.000419
.000423

,000250
.000251
.000252
,000253
,000254
.000255
.000256
,000257

,000640
,000644
,000648
.000652
,000656
.000659
.000663
.000667

,000350
,000351
,000352
,000353
,000354
.000355
.000356
.000357

,000885
,000888
,000892
.000896
.000900
.000904
.000907
.000911

.000060
,000061
,000062
,000063
,000064
,000065
,000066
,000067

.000183
,000186
,000190
,000194
,000198
.000202
.000205
,000209

.000160
.000161
,000162
,000163
,000164
,000165
,000166
,000167

.000427
.000431
.000434
,000438
.000442
,000446
.000450
.000453

.000260
.000261
.000262
.000263
.000264
,000265
,000266
,000267

.000671
.000675
.000679
,000682
,000686
,000690
,000694
.000698

.000360
.000361
.000362
,000363
,000364
,000365
,000366
,000367

.000915
.000919
,000923
.000926
.000930
,000934
,000938
,000942

,000070
,000071
,000072
,000073
,000074
,000075
,000076
,000077

,000213
.000217
.000221
,000225
,000228
,000232
,000236
,000240

,000170
,000171
,000172
.000173
,000174
,000175
,000176
.000177

,000457
.000461
.000465
.000469
,000473
.000476
.000480
.000484

.000270
.000271
.000272
,000273
.000274
,000275
,000276
,000277

.000701
,000705
,000709
,000713
.000717
.000720
,000724
.000728

.000370
,000371
.000372
,000373
.000374
.000375
.000376
,000377

,000946
,000949
.000953
.000957
,000961
,000965
,000968
,000972

Rev H

C-12

OCTAL-DECIMAL FRACTION CONVERSION TABLE (Cont'd)

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

.000400
.000401
.000402
.000403
.000404
.000405
.000406
.000407

.000976
.000980
.000984
.000988
.000991
.000995
.000999
.001003

.000500
.000501
.000502
000503
.000504
.000505
.000506
.000507

.001220
.001224
.001228
.001232
.001235
.001239
.001243
.001247

.000600
.000601
.000602
.000603
.000604
.000605
.000606
.000607

.001464
.001468
.001472
.001476
.001480
.001483
.001487
.001491

.000700
.000701
.000702
.000703
.000704
.000705
.000706
.000707

.001708
.001712
.001716
.001720
.001724
.001728
.001731
.001735

.000410
.000411
.000412
.000413
.000414
.000415
.000416
.000417

.001007
.001010
.001014
.001018
.001022
.001026
.001029
.001033

.000510
.000511
.000512
.000513
.000514
.000515
.000516
.000517

.001251
.001255
.001258
.001262
.001266
.001270
.001274
.001277

.000610
.000611
.000612
.000613
.000614
.000615
.000616
.000617

.001495
.001499
.001502
.001506
.001510
.001514
.001518
.001522

.000710
.000711
.000712
.000713
.000714
.000715
.000716
.000717

.001739
.001743
.001747
.001750
.001754
.001758
.001762
.001766

.000420
.000421
.000422
.000423
.000424
.000425
.000426
.000427

.001037
.001041
.001045
.001049
.001052
.001056
.001060
.001064

.000520
.000521
.000522
.000523
.000524
.000525
.000526
.000527

.001281
.001285
.001289
.001293
.001296
.001300
.001304
.001308

.000620
.000621
.000622
.000623
.000624
.000625
.000626
.000627

.001525
.001529
.001533
.001537
.001541
.001544
.001548
.001552

.000720
.000721
.000722
.000723
.000724
.000725
.000726
.000727

.001770
.001773
.001777
.001781
.001785
.001789
.001792
.001796

.000430
.000431
.000432
.00'0433
.000434
.000435
.000436
.000437

.001069
.001071
.001075
.001079
.001083
.001087
.001091
.001094

.000530
.000531
.000532
.000533
.000534
.000535
.000536
.000537

.001312
.001316
.001319
.001323
.001327
.001331
.001335
.001338

.000630
.000631
.000632
.000633
.000634
.000635
.000636
.000637

.001556
.001560
.001564
.001567
.001571
.001575
.001579
.001583

.000730
.000731
.000732
.000733
.000734
.000735
.000736
.000737

.001800
.001804
.001808
.001811
.001815
.001819
.001823
.001827

.000440
.000441
.000442
.000443
.000444
.000445
.000446
.000447

.001098
.001102
.001106
.001110
.001113
.001117
.001121
.001125

.000540
.000541
.000542
.000543
.000544
.000545
.000546
.000547

.001342
.001346
.001350
.001354
.001358
.001361
.001365
.001369

.000640
.000641
.000642
.000643
.000644
:000645
.000646
.000647

.001586
.001590
.001594
.001598
.001602
.001605
.001609
.001613

.000740
.000741
.000742
.000743
.000744
.000745
.000746
.000747

.001831
.001834
.001838
.001842
.001846
.001850
.001853
.001857

.000450
.000451
.000452
.000453
.000454
.000455
.000456
.000457

.001129
.001132
.001136
.001140
.001144
.001148
.001152
.001155

.000550
.000551
.000552
.000553
.000554
.000555
.000556
.000557

.001373
.001377
.001380
.001384
.001388
.001392
.001396
.001399

.000650
.000651
.000652
.0.00653
.000654
.000655
.000.656
.000657

.001617
.001621
.001625
.001628
.001632
.001636
.001640
.001644

.000750
.000751
.000752
.000753
000754
.000755
.000756
.000757

.001861
.001865
.001869
.001873
.001876
.001880
.001884
.001888

.000460
.000461
.000462
.000463
.000464
.000465
.000466
.000467

.001159
.001163
.001167
.001171
.001174
.001178
.001182
.001186

.000560
.000561
.000562
.000563
.000564
.000565
.000566
.000567

.001403
.001407
.001411
.001415
.001419
.001422
.001426
.001430

.000660
.000661
.000662
.000663
.000664
.000665
.000666
.000667

.001647
.001651
.001655
.001659
.001663
.001667
.001670
.001674

.000760
.000761
.000762
.000763
.000764
.000765
.000766
.000767

.001892
.001895
.001899
.001903
.001907
.001911
.001914
.001918

.000470
.000471
.000472
.000473
.000.474
.000475
.000476
.000477

.001190
.001194
.001197
.001201
.00120.5
.001209
.001213
.001216

.000570
.000571
.000572
.000573
.00.0574
.00.0575
.000576
.000577

.001434
.001438
.001441
.001445
.001449
.001453
.001457
.001461

.000670
.000671
.000672
:000.673
.000674
.000675
.000676
.000.677

.001678
.001682
.001686
.001689
.001693
.001697
.001701
.001705

.000770
.000771
.000772
.0.0077)
.000774
.000775
.000776
.0.00777

.001922
.001926
.001930
001934
.001937
.001941
.001945
.001949

C-13

Rev H

APPENDIX D

INSTRUCTION fORMATS AND NOTES

D.

INSTRUCTION FORMATS AND NOTES

The formats below correspond to the mnemonic instructions listed in Table D-l.
23

FI

I
23

F2

I
23

F3

I
23

F4

I
23

F5

I
23

F7

I
23

F8

I
23

F9

I
23

FlO

I
23

Fll

00

I I

I

181716

00

I

II
181716 1514

II

I

1817

I
12 II

00

I

I
1817

00

1514

I

12 II

00

I
18 1716 1514

12 II

00

I

II
1817

12 II

I

0908

00

I I

1817

I

12 1110090807

I
I
II I

1817

181716 1514

1817

00

I

II II
121110

0706

II

I

12 II

00

I

0605

I

00

I

12 II

00

1514

12 II

00

I

I

I
23

Fl2

1514

I
23

F6

1817

1817

I
D-I

I
Rev. A

F13

F14

F15

{

{
{

P

I

I
23

P

I
2.3

2.3

I
2.3

P+1

I
2.3

F16

{

P

I
2.3

P+1

I
I

2.3

P

2.3

F17

P + 1

00

181716

00

I

I
2.3

F18

P+l

I

181716

00

I

181716

00

II

I

2.12.019181716

00

I
I

IIIII
181716

00

II
1716

00

I

I

181716

00

I

II
2.12.01918

00

I

I I
12.11

I

I
2.3

P

I

II
2.12.0

2.3

P+2

I

I II

P+1
P

II
II

181716

23

P+1

00

181716

2.3

181716

I
I

II

00

I
12 II

2.3

I
00

2.12.01918 1716

I

00

00

I

P+2
23

181716

23

212019181716

II

P
F19

P + 1

I
23

P+2

Rev. A

00

I

I L
I
1817

D-2

00

12 II

00

23

1817 16

23

21 20 1918 17 16

II

P
F20

020100

00

P + 1
23

00

P + 2
23

18 17 16

23

212019181716

F21

020100

I I

II

P

00

P+l
23

12 II

00

P+2
23

18 1716

23

21 20 19 18 17 16

II

P
F22

020100

00

I

I I I

P + 1
23

20 19

12 II

00

P+2
23

181716

23

212019181716

II

P
F23

00

02 0100

P+l
23

12 II

00

P+2
23

18 17 16

23

212019181716

F24

00

II

P

0201 00

P+l
23

18 17

23

1817

12 II

00

P+2
00

P
23

F25

2120

00

P+l
23

12 II

00

P+2

D-3

Rev. A

23

23

21 20 19 18

00

P+l
23

1817

P+2

Rev. A

00

II

P
F26

18 17 16

D-4

12 11

00

TABLE D-l,
Mnemonic
Code

INSTRUCTION FORMATS

Basic
Octal Code

Instruction Format

Page No.

ACI
ACR
ADA, I
ADAQ, I
ADM
AEU
AlA

77
77
30
32
67
55

F4
F7
F3
F3
F18
F1

5-38
5-40
5-60
5-61
5-68
5-36

53

F6

5-33

AIS
ANA

77
17

5-37
5-73

ANA,S
ANI

17
17

F7
F1
F1
F3

ANQ

17

F1

5-74

ANQ, S

17

F1

5-74

AOS

77

F4

5-37

APF

77

F9

5-39

AQA

53

F5

AQE

55

F1

5-32
5-36

AQJ, EQ

03

F3

5-46

AQJ, GE

03

F3

5-46

AQJ, LT

03

F3

5-46

AQJ, NE

03

F3

5-46

ASE

04

F1

5-29

ASE,S

04

F1

5-29

ASG

05

F1

5-30

ASG, S

05

5-30

ATD

66

F1
F21

5-119

ATD,D

66

F22

5-120

AZJ, EQ

03

F3

5-45

AZJ, GE

03

F3

5-45

AZJ, LT

03

F3

5-45

AZJ, NE

03

F3

CIA

77

F4

5-45
5-38

CILO

77

F8

5-91

D-5

5-73
5-73

Rev. F

TABLE D-l.
Mnemonic
Code

INSTRUCTION FORMATS (Cont'd)

Basic
Octal Code

Instruction Format

Page No.

CINS

77

F5

5.,..'86

CLCA

77

F8

5-94

CMP

67

F18

5-79

CMP, DC

67

F19

5-80

CON
COpy

77

F12

5- 95

77

F5

CPR, I
CRA
CTI
CTO
CVBD
CVDB
DINT
DTA
DTA,DC
DVA, I

52
77
77
77
66
66
77
66
66
51

F3
F4
F4
F4
F20
F23
F4
F23
F24
F3

5-83
5-77
5-40
5-97
5-97
5-116
5-115
5-89
5-117
5-118
5-62

DVAQ, I

57

F3

5-63

EAQ
ECHA

55
11

5-36
5-26

ECHA, S

11

Fl
F2
F2

EDIT

64

F18

5-149

EINT

77

F4

5-89

ELQ

55

F1

5-36

ENA

14

F1

5-25

ENA, S

14

F1

5-25

ENI

14

F3

5-25

ENQ

14

F1

ENQ,S

F1

EUA

14
55

5-25
5-25

Fl

5-36

EXS

77

F5

5-83

FAD, I

60

F3

5-65

FDV, I

63

F3

5-66

Rev. F

,

D-6

5-26

TABLE D-l.
Mnemonic
Code

INSTRUCTION FORMATS (Cont'd)

Basic
Octal Code

Instruction Format

Page No.

FMU,I

62

F3

5-66

FRMT

64

F18

5-147

FSB, I

61

F3

5-65

HLT

00

Fl

5-24

IAI

53

F6

5-33

IAPR

77

F4

5-113

IJD

02

F3

5-44

IJI

02

F3

5-43

INA

15

Fl

5-27

INA, S

15

Fl

5-27

INAC,INT

73

F14

5-106

INAW,INT

74

F14

5-107

INCL

77

F4

5-89

INI

15

F3

5-27

INPC, INT, B, H, G

73

F15

5-98

INPW, INT, B, N, G

74

F15

5-100

INQ

15

Fl

5-27

INQ, S

15

Fl

5-27

INS

77

F5

5-85

INTS

77

F5

5-84

IOCL

77

F4

5-94

ISA

77

F7

5-37

ISD

10

F3

5-31

ISE

04

F3

5-28

ISG

05

F3

5-30

lSI

10

F3

5-31

JAA

77

F4

5-40

JMP, HI A

70

Fl

JMP, LOW A

70

Fl

5-42
5-42

JMP, ZRO A

70

Fl

LACH

22

F2

5-42
5-49

LBR

70

Fl

5-155

D-7

Rev. A

TABLE D-l.
Mnemonic
Code

INSTRUCTION FORMATS (Cont'd)

Basic
Jctal Code

Instruction Format

Page No.

LCA, I

24

F3

5-50

LCAQ, I

26

F3

5- 51

LDA,I

20

F3

5-49

LDAQ, I

25

F3

5-50

LDI, I

54

F3

5-52

LDL,I

27

F3

5-50

LDQ,I

21

F3

5- 51

LPA, I

37

F3

5-73

LQCH

23

F2

5-52

MEQ

06

Fl

5-75

MOVE, INT

72

F16

5-138

MTH

07

Fl

5-76

MUA,I

50

F3

5-62

MUAQ, I

56

F3

5-63

MVBF

64

F18

5-142

MVE

64

F18

5-140

MVE,D

64

F19

5-141

MVZF

..64
'

F18

5-143

MVZS

64

F18

5-144

MVZS, D

64

F19

5-145

OSA

77

F4

5-37

OTAC, INT

75

F14

5-109

OTAW, INT

76

F14

5-110

OUTC, INT. B. H

75

F15

5-102

OUTW. INT. B, N

76

F15

5-104

PAK

66

F18

5-121

PAUS

77

Fll

5-87

PFA

77

F9

5-39

PRP

77

Fll

5-88

QEL

55

Fl

5-36

QSE

04

Fl

5-29

QSE,S

04

Fl

5-29

.

Rev. A

D-8

TABLE D-1.
Mnemonic
Code

INSTRUCTION FORMATS (Cont'd)

Basic
Octal Code

Instruction Format

Page No.

QSG

05

F1

5·30

QSG, S

05

F1

5-30

RAD, I

34

F3

5-60

RIS

55

F1

5-112

ROS

55

F1

5-112

RTJ

00

F1

5-47

SACH

42

F2

5-54

SBA, I

31

F3

5-61

SBAQ, I

33

F3

5-61

SBCD

77

F4

5- 91

SBJP

77

F4

5-112

SBM
SBR

67
70

F1B
F1

5-69
5-155

SCA, I

36

F3

5-72

SCAN, LR, EQ, DC

65

F26

5-130

SCAN, LR, NE, DC

65

F26

5-132

SCAN, RL, EQ, DC

65

F26

5-134

SCAN, RL, NE, DC

65

5-136

SCAN, LR, EQ

65

F26
F26

SCAN, LR, NE

65

F26

5-131

SCAN, RL, EQ

65

F26

5-133

SCAN, RL, NE

65

F26

5-135

SCAQ

13

F3

5-59

SCRA, I

46

F3

5-56

SCIM

77

F4

5-90

SDL

77

F7

5-113

SEL

77

F12

5-96

SFPF

77

F4

5-91

SRA

12

F3

5-57

SRAQ

13

F3

5-59

D-9

5-129

Rev. F

TABLE D-l,
Mnemonic
Code

INSTRUCTION FORMATS (Cont 'd)

Basic
Octal Code

I nstruction Format

Page No.

SHQ

12

F3

5-59

SJ1

00

F1

5-41

SJ2

00

F1

5-41

SJ3

00

F1

5-41

SJ4

00

F1

5-41

SJ5

00

F1

5-41

SJ6

00

F1

5-41

SLS

77

F4

5-24

SQCH

43

F2

5-55

SRCE,INT

71

F13

5-125

SRCN,INT

71

F13

5-127

SSA, I

35

F3

5-72

SSH

10

F1

5-57

SSIM

77

F4

5-90

STA, I

40

F3

5-53

STAQ, I

45

F3

5-54

STI, I

47

F3

5-56

STQ, I

41

F3

5-55

SWA, I

44

F3

5-56

TAl

53

F6

5-33

TAM

53

FlO

5-34

TIA

53

F6

5-33

TIM

53

FlO

5-35

TMA

53

FlO

5-34

TMAV

77

F4

5-81

TMI

53

FlO

5-35

TMQ

53

FlO

5-34

TQM

53

FlO

5-34

TST

67

F17

5-82

TSTN

67

F17

5-82.0

UCS

77

F4

5-24

UJP, I

01

F3

5-41

Rev. F

D-10

TABLE D-l,
Mnemonic
Code

INSTRUCTION FORMATS (Cont'd)

Basic
Octal Code

Instruction Format

Page No.

UPAK

66

F18

5-122

XOA

16

F1

5-71

XOA,S

16

F1

5-71

XOI

16

Iq

5-71

XOQ

16

F1

5-71

XOQ,S

16

F1

5-71

ZADM

67

F18

5-146

D-ll

Rev. A

APPENDIX E

MULTIPROGRAMMING AND RELOCATION
SUPPLEMENTARY INFORMATION

E.

MULTIPROGRAMMING AND RELOCATION
SUPPLEMENTARY INFORMATION

Multiprogramming in the 3300 Computer System enables the instructions of
many programs to be sequentially executed by controlled time-sharing
operations within a processor. With the Control Data Multiprogramming Modules, throughput is very high due to efficient use of hardware and optimum
program scheduling. This feature is very desirable at installations where
numerous jobs are run and computing time must be kept at a minimum. Systems
equipped with the relocation feature can compute many programs on a timeshared basis or be switched into the non-Executive mode and process jobs
according to control card job assignments.

EXECUTIVE MODE
A system equipped with relocation hardware and operating in the Executive
Mode functions in either the Monitor State or the Program State.
Monitor State
The Monitor State is the initial operating state of a master cleared proces sor.
The processor also reverts to this state if interrupted for any condition. All
instructions may be executed in the Monitor State.
Program State
The Program State permits all but the following instructions to be executed:
1.

A Halt instruction (00. 0)

2. Any of the instructions with function codes in the 71-77 range including the
UCS, except the SFPF (77.71) and SBCD (77.72) instructions.
3.

An inter-register transfer instruction that attempts to alter registers
00 through 37 of the register file.

E-1

Rev. A

If an attempt to execute one of these instructions occurs, an Executive interrupt

is generated and operating control is transferred back to the Monitor State. The
Executive interrupt is not masked and the interrupt system need not be enabled
to recognize the interrupt when it occurs. Upon recognition, the Executive
interrupt transfers program control to the Monitor State. The instruction that
caused the interrupt is not executed. The following flow chart describes the
sequence of events involved when an Executive Interrupt occurs.
EXECUTIVE INTERRUPT SEQUENCE
Attempt is made to execute an instruction at
Address P, that will cause an Executive Interrupt.

1
Program control is transferred to the Monitor State.

1

Address P is stored in the lower 15 bits of address
000004 of the Monitor State.

1
Interrupt code 0120 is stored in the lower 12 bits of
address 000005 of the Monitor State.

1

Instruction at address 000005 of the Mo~itor State is
executed.

MULTIPROGRAMMING AND RELOCATION
If the 3311 Multiprogramming option is not present in a 3300 system, the maximum
number of MCS words is 131,072. The actual address referenced is as follows:
17 BIT ADDRESS
Ir----------~A~

0100

(ISR) - - [

CO
,

14

________~\
00

r---------(-P-)- - - - - - - . . ,

,

: OR :
0100,

(OSR)--[CO

:
1

OR :

\'00'"

Refer to Table E-1 for conditions
when (ISR), (OSR), or zero is
appended to address P.

Upper Bit of ISR
or OSR is ignored

Rev. A

E-2

If the APF (77.64) or PFA (77.65) instructions are executed they become no-

operation instructions when the 3311 is not pre sent. The keyboard sweep and enter
functions with the Page Index File are also disabled. All other operating conditions
are the same whether or not the 3311 is in the system.
A 3300 CPU can access up to 262,144 words of core storage when the 3311
Multiprogramming option and appropriate storage modules are present in the
system. This is accomplished by augmenting the basic 15-bit address P with a
3-bit state number. The state number~along with a portion of the 15-bit address,
becomes the direction path into a relocation path. From the Page Index File the
correct page address is obtained for actual memory addressing.
Page Structure
Each page of memory is assigned 2,048 absolute memory locations. A fully
expanded system contains 128 of these pages. Individual pages may be subdivided into four partial pages. A 1/4 page consists of 512 address locations.
Programs may be allocated full pages, 3/4 page, 1/2 page or 1/4 page of
memory.
To facilitiate addressing with the paging scheme, a word organized core
matrix is used. This core matrix, called the Page Index File, is referenced
by a program during a memory reference to obtain the physical page address
or partial page address and provide memory protection.
Address Relocation
Figure E-1 illustrates address bits at various stages of the relocation process.
Those portions of the diagram accompanied by circled numbers are further
described in the following numbered paragraphs.

CD

Program Address and Program Address Group

Any program executed by a 3300 is processed within the confines of a 15-bit
program address structure. These 15 bits define the program or operand
address related to the routine or subroutine being processed at a given instant.
Figures E-2 and E- 3 illustrate the significance of these bits in the instruction
words for both word addressing and character addressing.
The 15 bits used in word addressing define an absolute address assignment
ranging from 00000 to 77777 8 . Any program or group of programs within this
range of addresses which can be compiled and loaded without conflicting addresses can be considered part of a program address group. Figure E-4 is
illustrative of a program address group consisting of five non-conflicting
programs.

E-3

Rev. A

0
7-BIT
PAGE FILE
ADDRESS
(INPUT)

I BIT
PAGE
LENGTH
CONTROL

2 BITS

ILLEGAL WRI TE

®
® {021·:::::::::::
:::

(ISR)

OR?:::

(OSR)

00:.::

PAGE
INDEX
FILE

7 BITS

>:.:.:-:-:.

2 BIT

@
18-BIT
RELOCATED
MEMORY
ADDRESS
PROGRAM
ADDRESS

(REF TO TEXT FOR
ADDITIONAL INFORMATION
ON NUMBER AREAS)

RELATIVE BIT POSITION

Figure E-l.

Rev. A

Address Relocation Process

E-4

A program address group may be considered apart from the physical memory
structure since it is a group of sequentially numbered addresses representing
one or more programs within 32, 768 words of storage and not a discrete
physical device. Many program address groups may be contained in storage; however, eight such groups are used in the 3300 to best optimize the memory system.

23

I

18 17
FUNCTION
CODE

IE--

15 14

I

WORD
ADDRESS

I

6 BITS ~ 3 ~IE
BITS

15 BITS

Figure E-2.

FUNCTION
CODE
1E--6 BITS

00
CHARACTER
ADDRESS

II

*:.1<

Figure E-3.

I

~I

Word Addressing

18 17 16

23

®

00

17 BITS

~

Character Addressing

Instruction State Register (ISR) and Operand State Register (OSR)

The ISR and OSR define the specific program address group currently being
accessed by a processor. The program address group being referenced for
instructions and operands can assume anyone of eight discrete values by
modifying the contents of these single digit registers. By transferring dissimilar numbers into these registers, instructions and operands may reference different program address groups.
The contents of these registers can only be changed by the Executive routine in
the Monitor State.
The program address group that is currently valid for memory references is
selected by the contents of the ISR or OSR. Table E-l describes the selecting
conditions.

E-5

Rev. A

00000

PROGRAM A
PROGRAM B

PROGRAM C

ADDRESSES

PROGRAM D

PROGRAM E
77777

Figure E-4.

TABLE E-l.

Program Address Group

INSTRUCTION AND OPERAND REFERENCING

Operational State of the Processor

Instructions
Referenced With:

Operands
Referenced With:

Initial Monitor State

Zero

Zero

Monitor State and 55.4 (relocate
to operand state) instruction
executed

Zero

Contents of OSR

Transition from Monitor State to
Program State

Contents of ISR

Contents of ISR':'

Program State and 55.4 (relocate
to operand state) instruction
executed

Contents of ISR

Contents of OSR

Program State and 55.0 (relocate
to instruction state) instruction
executed

Contents of ISR

Contents of ISR

Any interrupt condition to
Monitor State

Zero

Zero

':'Transition from Monitor State to Program State does not change the operand
address mode.

Rev. A

E-6

®

Page Index File

The Page Index File is functionally divided into eight distinct reference areas.
One area is associated with each of eight possible numbers appearing in the ISR
and OSR. Because of this direct relationship, each of the eight program address
groups is permanently assigned a reference area in the Page Index File.
Each of the eight reference areas within the Page Index File consists of sixteen
12-bit Page Index Registers. This provides each of the program address groups
exclusive use of 16 of these registers. By using the upper 4 bits of the'program
address for direction to the respective Page Index Registers, a direct and
sequential relationship is established between the addresses in a program address group and a specific set of 16 Page Index registers. The Page Index File
is actually constructed of 64 24-bit Page Index registers with dual 12-bit indexes. Only one of the 12-bit indexes is used during any specific reference.
Figure E-6 depicts the page indexes within the Page Index File and Figure E-7
illustrates the relationship between program address groups, Page Index File,
and a fully expanded core memory.
Bit 11 of the original 15-bit address determines which of the two page indexes
at the Page File location will be used. Figure E- 5 shows a specific page index
being referenced.

(ISR)
02
00

PROGRAM ADDRESS (P)
14 12 II 10

00

~-------I

L:l.:...L _______ - l
' - - - - INDICATES 000 PAGE
INDEX AT LOCATION 23

123
21

I PAGE
I

SECTION OF PAGE FILE
12 II
INDEX 21

221 PAGE INDEX 22
231 PAGE INDEX 23
241 PAGE INDEX 24

o

I

PAGE INDEX 21

o I PAGE
o ~\
o

001

INDEX 22

I

I
I

Il

I'

~~~FE

INDEX 24

\\

I

~" " "

"" """

"" """ , "-

\\

\ \

\)

PAGE INDEX 23

I

"

~I

v
The contents of this Page Index (E,
PL, PA, and PP) are used to form
the relocated' address. The format
of a page index is shown below.
II

10

0808

II I
E

Figure E-5.

PL

0201
PA

00

I I
PP

Example of Page Index Referencing
E-7

Rev. A

I r"00". "'" """

BI T " OF ORIGINAL
ADDRESS (P)

(THIS DIGIT INDICATES

23

PAGE

00

INDEX 00

"~

12

00

PAGE INDEX

0:;\

PAGE INDEX

01

I

I

PAGE INDEX

02

I

0------;

I
PAGE

01

INDEX 01

0

I
PAGE

02

INDEX

02

0

I
03

PAGE

INDEX 03

0

I

PAGE INDEX

03

I

04

PAGE

INDEX

04

0

:I

PAGE INDEX

04

I

05

PAGE

INDEX

05

0

I

PAGE INDEX

05

I

PAGE INDEX

06

I

I
PAGE INDEX

06

06

0

I

I

PAGE INDEX
FILE
HARDWARE
LOCATIONS

07

PAGE

INDEX .07

0

I

PAGE INDEX 07

I

10

PAGE

INDEX

10

0

~

PAGE INDEX

10

I

I I

PAGE INDEX

II

0

iI

PAGE INDEX

II

I

12

PAGE INDE X

12

0

I

PAGE

INDEX

12

I

13

PAG E INDEX

13

0

:I

PAGE

INDEX 13

I

--------- -

-

~-

I
I

71

PAGE INDEX 71

0

72

PAGE INDEX 72

0

I
I

PAGE INDEX 71

I

I

PAGE INDEX72

I

PAGE INDEX 73

I

I
I

PAGE INDEX 74

I

I

PAGE INDEX 75

I

PAGE INDEX 76

I

PAGE INDEX 77

I

I
PAGE INDEX 73

73

0

I
I

74

PAGE

INDEX 74

0

75

PAGE INDEX 75

0

I
PAGE INDEX 76

76

0

I

I
PAGE INDEX 77

77

0

I

~----------~vr----------~I\L----------~vr-------------J

EVEN PAGE INDEX FILE
ADDRESSES

Figure E-6.
Rev. A

ODD PAGE INDEX FILE
ADDRESSES

Page Index File Address and Hardware Structure
E-8

PAGE INDEX
REGISTERS EACH PAGE INDEX . .--_ _ _ _ _ _ _ _ _ _ _-,
MAY ACCESS ANY

r---~----

---{
r------,---------------MONITOR
PROGRAM

PROGRAM
ADDRESS
GROUP I

r - - - - - - , PAGE IN ME MORY

PAGE 0
16
PAGE INDEX
REGISTERS

1;;::---__ _

~} =-_-_-_-_-_~:::::::::::
=-_-_-_-_ADDRESS GROUP
HAS ACCESS TO
16 UNIQUE PAGE

- _-_-_-_-_-

~ ~~~~:::.

EACH ADDRESS
PROGRAM
GROUP CONSISTS PROGRAM
OF ONE OR MORE ADDRESS
INDIVIDUAL PRO- GROUP 2
GRAMS WITHIN
32,168 ADDRESSES

16
INDEX
REGISTERS

MEMORY
PAGE I

MEMORY
PAGE 2

MEMORY
PAGE 3

PA~E

PROGRAM
ADDRESS
GROUP 3

16
PAGE INDEX
REGISTERS

PROGRAM
ADDRESS
GROUP 4

16
PAGE INDEX
REGISTERS

PROGRAM
ADDRESS
GROUP 5

16
PAGE INDEX
REGISTERS

PROGRAM
ADDRESS
GROUP 6

MEMORY

MEMORY
PAGE 4

MEMORY
PAGE 5

MEMORY
PAGE 6

16
PAGE INDE'X
REGISTERS

MEMORY
PAGE 122

MEMORY
PAGE 123

MEMORY
PAGE 124

- - - - 1------1
r - - - .....

PROGRAM
ADDRESS
GROUP 1

- - - -

16
PAGE INDEX
REGISTERS

----L--_----'

MEMORY
PAGE 125

MEMORY
PAGE 126

MEMORY
PAGE 121

Figure E-7.

Relocation System Illustrating Memory Protection
with Fully Expanded Memory (262K)

E-9

Rev. A

@

Page Index

Each page index has the same basic format. The significance of each designator
during the relocation process is described below. Figure E-S shows the format
for a page index while Figure E-9 shows a view of the display panel on the relocation chassis.
II

10

09 08
OR

OR

OR OR

23 22

21 20

14 13

II
E

E
PL
PA
PP

ACTUAL BITS DEPEND
OO}
UPON WHETHER THE
OR
EVEN OR ODD PAGE
12
INDEX IS REFERENCED

0201

Oil OR

PL

PA

= EXCLUSION

PP

I

BIT (I BIT)

= PAGE LENGTH DESIGNATOR (2 BITS)
= PAGE ADDRESS DESIGNATOR (7 BITS)
= PARTIAL PAGE DESIGNATOR (2 BITS)

Figure E-S.

Page Index Format

E - Exclusion bit
This designator may have one of three meanings:
1.

If E = "0", the quantity expressed by PA defines a page:'

where either reading or writing is permitted.

= "1", and PL, PA or PP is a quantity other than
zero, PA defines a page ':' where only reading is permitted. If a write is attempted, an Illegal Write interrupt is generated.

2.

If E

3.

If E = "1" and PL, PA br PP are all equal to zero,
an unaddressable page is defined and an Illegal Write
interrupt is generated by the Page Index File.

* Refer to descriptions

of PL and PP designators for page restrictions.

CPU S-BUS

ST0 S-BUS

2 0L..:_0_'50_ 9. ." 6 6 6 0

9666696(29
'eel

PF ADDRESS

_4_

PP

BUS

MODULE SELECT

~ 0DD

it EVEN

6 66 6666666 66
L--J

E

PL

1

I

PA

Figure E-9.

Rev" B

'----1

PP

6 66 6600060 00
L--..J

E

PL

!

I

PA

Relocation Chassis Display Panel

E-IO

l...--.J

pp

PA - Seven bits are used to define the actual memory module being referenced.
As stated earlier in this manual, there may be 128 segmented pages in a
3300 system with 262, 144 words of core storage.
Each page has
a unique page address and addresses 000 through 1778 define all of the
possible pages.
A 3300 system with a fully expanded storage network has two address
busses. Each bus has access to 131,072 words of the total 262,144
storage words. The uppermost bit of PA (bit 17 in the relocated address)
determines which bus (right or left) is selected. This bit will be a "I"
when the left bus is used and a "0" when the right bus is selected. Figure
E-10 depicts the bus address system.

MULTIPROGRAMMING
OPTION

131,072 WORDS OF
CORE STORAGE IN
32,768 BANKS

LEFT
BUS

RIGHT
BUS

\

!

BIT 17 OF
PA:"I"

Figure E-I0.

BIT 17 OF
PA:"O"

Storage Address Buses

T

000000
512
000777
001000
001777
002000

- 512

002777
003000

LOCATIONS

- - - - - 512

QUARTER PAGE
ADDRESSES FOR
PAGE 0

131,072 WORDS OF
CORE STORAGE IN
32,768 BANKS

LOCATIONS

- -

- -

1/4 PAGE

i

1/2 PAGE

~

3/4 PAGE
FULL PAGE

LOCATIONS

- - - -- 512

LOCATIONS

003777
NOTE: PP

=0 FOR THIS EXAMPLE

PL : 0 FOR FULL PAGE

PL: 2 FOR

PL: I FOR 1/4 PAGE

PL: 3 FOR 3/4 PAGE

Figure E-l1.

1/2

PAGE

Page Length Subdivisions
E-ll

Rev. B

PL -

Each page has 2,048 memory locations and is subdivided into quarters of
512 locations each. The PL designator defines how many quarters of a
page can be referenced (beginning with the starting quarter specified by
PP)' A program is assigned the number of quarter pages it needs to reside in memory. Figure E-11 illustrates the quarter sections of a page
and the significance of the PL bits.

PP -

The Partial Page designator is the address of the physical quarter page
that will serve as the starting point of the page. Example A (Figure E-12)
shows the quarter page referenced for each of the PP designators. The
significance of the PP designator in selecting the respective quarter page
for addressing is described below"
EXAMPLE A

PHYSICAL
QUARTER
DESIGNATOR

STARTJ NG QUARTER

~

PP=O

STARTING QUARTER

~

PP = I

PP = 2 STARTING QUARTER ~

PP= 3
STARTING QUARTER

Figure E-12.
Rev. B

~

!

RELATIVE QUARTER
IN RESPECT TO THE
STARTING QUARTER

!

1ST

QUARTER

2ND

QUARTER

2

3 RD

QUARTER

3

4 TH

QUARTER

4

1ST

QUARTER

4

2ND

QUARTER

3 RD

QUARTER

2

4 TH

QUARTER

3

1ST

QUARTER

3

2ND QUARTER
3 RD QUARTER

4

4 TH

QUARTER

2

1ST

QUARTER

2

2ND QUARTER
3 RD QUARTER

3

4 TH

4

QUARTER

Quarter Page in Relation to PP Designator
E-12

If PP = 0, the relative page begins in the 1st physical quarter
If PP = 1, the relative page begins in the 2nd physical quarter
If PP = 2, the relative page begins in the 3rd physical quarter
If PP

®

= 3,

the relative page begins in the 4th physical qu.arter

Partial Page Adder

A special adder is used to combine the PP designator from the page index with
bits 9 and 10 of the original address. The partial sum indicates the address of the
physical quarter in which referencing will begin. Example B and Figure E-13
show the actual quarter page in which addressing occurs for specific PL, PP, and
bits 9 and 10 values.
EXAMPLE B
PL = 0
PP

=1

Bits 9 and 10
Analysis:

=2

A full page (PL = 0) is allocated, the relative page
begins in the second physical quarter, and referencing begins in the fourth physical quarter, (physical
quarter address 3).
RELATIVE
1S T

QUARTER

2ND

QUARTER

3 RD

QUARTER

2

4 TH

QUARTER

3

QUARTERS

4

STARTING QUARTER ~

PP

=I

BITS9ANDIO=2

/

ADDRESSING STARTS IN THE
THIRD RELATIVE QUARTER
(FOURTH PHYSICAL QUARTER)

Figure E-13.

Starting Quarters versus Relative Quarters

It should be noted that if bits 9 and 10 of the original address specify a quarter
page equal to or greater than that of the PL designator when PL 1- zero, an Illegal
Write interrupt will occur. An example of this condition would be a 1 I 4 page
allocated but bits 9 and 10 equal to 3, thus specifying an address in the fourth
quarter.

This interrupt will not occur during Monitor State or

E-13

Ilo operations.

Rev. B

®

Relocated Address

The 18-bit relocated address defines the actual core storage location being
referenced.
The PA portion of the page index fills the upper seven bits of this addre s s (S)
bus to use and select the appropriate storage module. Bits 9 and 10 receive the
output of the adder previously described and indicate the physical quarter page
being referenced. The lower nine bits are unaltered from the original address
and comprise the remainder of the relocated address.
Page Zero Consideration
If page Index File address zero is referenced in either the Program or Monitor
state, the PA and PP designators for this page index will always be zero. As
a result of this condition, page zero, which encompasses addresses 000000
through 003777, can be accessed and used for storing the Auto Load and Auto
Dump routines. The Auto Load routine is contained in addresses 003700
through 003737 and the Auto Dump routine is stored in addresses 003740 through
003777.

Rev. A

E-14

APPENDIX F

BUSINESS DATA PROCESSING SUPPLEMENTARY INFORMATION

F.

BUSINESS DATA PROCESSING SUPPLEMENTARY INFORMATION

The performance of a 3300 computing system is further enhanced by the addition
of a 3312 Business Data Processor (BDP) which eliminates the need for simulating
subroutines. Business-oriented moves and edits, searches, code conversions and
translations as well as BCD arithmetic operations are executed directly by the
BDP. Since the BDP is designated as an integral part of the computer system and
interfaces directly to the magnetic core storage modules, the instructions are
executed with great speed. The BDP expands the basic instruction repertoire to
cover instructions inherent to business data processing applications.
The logical organization of the BDP and its comprehensive instruction repertoire
emphasizes its usefulness as a logical field processor. This organization permits truly efficient processing of highly structured data files. Some examples
of applications which exploit these features are data collection, production control, inventory accounting, and financial and accounting systems.

CHARACTERISTICS OF BDP
The following are characteristics of the 3300 Business Data Processor:
•

Character addressing and manipulation
internal BCD 6-bit characters
24-bit words

•

Manipulation of data organized in variable or fixed length fields

•

Memory to memory operations

•

Field limits expressed by either programmer-defined delimiter
or by length

•

COBOL specification compatibility

•

Error indications on arithmetic overflow and illegal characters

•

Algebraic sign control

F-l

Rev. A

•

Extremely fast and comprehensive data processing instruction set
move s and edits
searches
ASCII/ BCD code conversions and translations
arithmetic functions

•

System interrupt capability retained without loss of data

Business data processing instructions are listed in Section 5. A general description of each of the instruction categories is listed below:

MOVES AND EDITS
The following capabilities are features of this instruction category:
•

Ability to transfer variable length data fields from one area
of storage

•

Both fields may specify any 6-bit character location in storage
as the beginning address

•

Both fields may be independently indexed

•

Up to 4095 characters may be processed

•

Operations may be .terminated by specifying lengths of fields
or by encountering delimiting characters; field lengths may
differ

•

Data moved from a source field to a receiving field may be
manipulated and/ or modified as follows:
....

Single character or block of characters transferred without
modification

....

Move with blanks inserted in any remaining character
positions in the receiving field

....

Move with zeros inserted in any remaining character
positions in the receiving field

....

Move with leading zeros replaced with blanks and zone
(sign) bits stripped during the transfer

....

Move with edit functions performed: insertion of commas,
decimal point with suppression of leading zeros, or complete
formatted edit with insertion of character set as defined in
DOD COBOL-6l Extended specification

Instructions in this group are particularly useful in data processing applications
involving character manipulation, formatting for printing of integer quantities,
point alignment problems, etc. Editing functions are accomplished by hardware
rather than a complex subroutine, resulting in extremely fast processing times.

Rev. A

F-2

SEARCHES
The following capabilitie s are features of this category of instructions:
e

Any 6-bit character location in storage may be specified as
the location of the first character to be searched

..

Up to 4095 characters may be examined

«I

Indexing may be accomplished on the search field

..

Search key {character} specified by programmer and contained
in instruction word

..

Search may be terminated by:
~

Locating object character

~.

Completing specified number of searches without
locating object character

~

Encountering delimiter -character without locating
object character

"

At conclusion of search operation, an index register holds number of
characters searched to aid in determining location of character meeting
search condition; this information placed in Central Processor Index
register

..

Program control at search termination branches to either of two points,
depending on result of search

"

Searches may be of the following types:
~

Search successive character locations {either left to right
or right to left} in a field for an object character equal to
the search key

~

Search successive character locations {either left to right
or right to left} in a field for an object character unequal
to the search key

~

Search successive character locations {from left to right}
in a field for an object character equal to the search key and
jump; jump is to normal termination point plus the number
of characters searched

CONVERSIONS AND TRANSLATIONS
Instructions in the category provide conversion and translation abilities to efficiently process data of varying formats. Translating codes prepares data for
various operations preliminary to the actual data processing. Translations to
and from the American Standard Code for Information Interchange {ASCII} code
provide compatibility with other systems data handling schemes. An ASCII to
BCD conversion table can be found in Appendix A.

F-3

Rev. A

The following conversions and translations may be effected with this category of
instructions:
•

Convert BCD to binary

•

Convert binary to BCD

•

Translate to ASCn

•

Translate from ASCn

•

Pack (convert numeric 6-bit digits into 4-bit BCD characters)

•

Unpack (convert numeric 4-bit digits into 6-bit characters)

ARITHMETIC FUNCTIONS
The following capabilities are features of this category of instructions:
•

Arithmetic performed on 6-bit BCD characters

•

Both fields may specify any 6-bit character location in storage
as the beginning address

•

Both fields may be independently indexed

•

Algebraic sign control

•

Arithmetic overflow fault indicator provided

..

Arithmetic operations from right to left

GIl

Compare - comparisons of two fields for equal, unequal
~

Compare left to right

~

Delimiter or number of characters (up to 4095)
specifies number of characters to be compared

~

High -low indication held in condition re gister
for examination by Jump instructions

•

Test instructions examine field for: greater than zero,
zero, or less than zero. The result of the test sets a
BCD condition register to +, 0, or-

o

Jump instructions in the CPU may be used to examine
arithmetic re sult flags in the BDP

Consult the individual business data processing instructions in Section 5 for
detailed information pertaining to each type of instruction.

BCD CHARACTERS AND ALGEBRAIC SIGN POSITIONS
Six-bit BCD characters are used during most BDP operations. The following
diagrams, example, and tables show the character placements and sign positions:

Rev. A

F-4

06' 05

12 11

18 17

23

o

2

~C

,~

'\

I

00
3

~

--........... haracter positions ~
BCD Character

Figure F-l.

BCD Word and Character Format

TABLE F-l.

BCD SIGN BIT POSITIONS

Sign of BCD
Field

Relative Bit Positions
6
5

+
+

0

0

0

1

-

1

0

+

1

1

TABLE F-2.

DECIMAL/BCD;CHARACTER FORMAT

Decimal
Number
4

BCD Character Relative Bit
Positions
2
3

1

0

0

0

0

0

1

0

0

0

1

2

0

0

1

0

3

0

0

1

1

4

0

1

0

0

5

0

1

0

1

6

0

1

1

0

7

0

1

1

1

8

1

0

0

0

9

1

0

0

1

F-5

Rev. A

EXAMPLE:
P

Execute the MVZF instruction at P, P + 1

J

and P + 2.

= 64000202
27003000

(B1) = 00200

P+2=00140017

(B2) = 01000

P+1

Analysis:

1.

The unmodified character addre ss 'r' is 00202.

2.

Br = 3, requiring (B1) be added to r. If (B1) = 00200 then
R = 00402 which equals word address 00100 character position
2. This is the true address of the highe st order character in field A.

3.
4.

Bs = 2, reqUirin~(B2) be added to the unmodified character address
's', 03000. If (B ) = 01000, then S = 04000.
The length of the A field is 14R characters and the alloted length of the C
field is 178 characters. The fast three characters of field C will be
filled with zeros. The last character of field C (a zero) will also contain
the sign of the field.
Character Positions

'A' Field
Word Addresses

o0
o0
o0
o0

100

Highest Order
1
~2
3
C~aracter in
'-----'----'Fl eld A
10 06 04 03

I I I

o

101

01110204

102

06031110

1 0 3

05

0407

1

Operand Specified
in Field A Equals
-431924639859

Lowest Order
Character in
Field A

I

~
5

1

1 0 100 1

'-v-' '--v--'
Indicates a
/
Negative Field

Rev. A

\ndicates Character
Is 118 = 910

. F-6

The operation proceeds as follows:
First Character Stored Is
Highest Order Character At
Word Address 01000, Character Position Zero.
'C' Field
Word Addresses
00777"

o 1 000
o 100 1
o 100 2
o 100 3

/:: ~~ ~
r
02

04

06

111005

00

00

2
Sign Is No Longer Stored
l / I n This Character As The
Lowest Order Character
o3
Of Field C Is Now Char1 1
acter Position 2 Of Word
Address 01003.
o7

Lowest Order Character
In Field C Contains the
Sign of Field C (minus)
and a Zero Character.

Operand N ow Stored
In Field C Equals
-431924639859000

F-7

Rev. F

GLOSSARY

The definitions of terms in this glossary are general, and are oriented toward
their application to the 3300 computer. The definitions should not be construed as
absolute or applicable for all Control Data products.
A REGISTER - Principal arithmetic register; operates as a 24-bit additive
accumulator (modulus 224-1).
ABSOLUTE ADDRESS - An address at a specific memory location.
ACCESS TIME - The time needed to perform a storage reference, either read
or write. In effect, the access time of a computer is one storage reference
cycle.
ACCUMULATOR - A register with provisions for the addition of another quantity
to its content.
ADDER - A device capable of forming the sum of two or more quantities.
ADDRESS - A 15-bit operand which identifies a particular storage location; a
17-bit operand which identifies a particular character location in storage.
ADDRESS MODIFICATION - Normally the derivation of a storage address from
the sum of the execution addre ss and the contents of the specified index
register.
AND FUNCTION - A logical function in Boolean algebra that is satisfied (has
the value "I") only when all of its terms are 111'sl1. For any other combination of values it is not satisfied and Its value is 110 11 .
ARGUMENT - An operand or parameter used by a program or an instruction.
ASCII CODE - American Standard Code for Information Interchange 8-bit
character code (eighth bit is actually unassigned).
ASSEMBLER - A program which translates statements to machine language.
Normally, one source language statement results in the generation of one
line of object code.

Glossary - 1

Rev. A

B1, B2, B3 REGISTERS - Index registers used primarily for address modification and/ or counting.
BASE - A quantity which defines some system of representing numbers by
positional notation; radix.
BDP - (l) Business Data Processor (3312); provides the necessary hardware
to execute business oriented instructions. Contains its own translation
and control logic but must be used with CPU.
(2)

Business Data Processing; processing business oriented data.

BINARY CODED DECIMAL (BCD) ~ A form of decimal notation where decimal
digits are repre sented by a binary code.
BIT - Binary digit, either "1" or "0".
BLOCK - A sequential group of storage words or characters in storage.
BOOTSTRAP - Any short program which facilitates loading of the appropriate
system executive.
BREAKPOINT - A point in a routine at which the computer may be stopped by
manual switches for a visual check of progress.
BUFFER - Any area that is used to hold data temporarily for input or output,
normally storage.
BYTE - A portion of a computer word, usually 6 or 12 bits.
CAPACITY - The upper and lower limits of the numbers which may be processed
in a register or the quantity of information which may be stored in a storage
unit. If the capacity of a register is exceeded, an overflow is generated.
CHANNEL - An input/ output (I/O) transmission path that connects the computer
to an external equipment; 3306 or 3307.
CHARACTER - A group of bits whicll represents a digit, letter, or symbol
from the typewriter.
CLEAR - An operation that removes a quantity from a register by placing every
stage of the register in the "0" state. The initial contents of the register
are destroyed by the Clear operation.
COMMAND - A control signal; also used synonymously with Instruction.
COMPILER - A program with the capability to generate more than one line
of machine code (instruction or data word) from one source language
statement.
COMPLEMENT - Noun: See One's Complement or Two's Complement. Verb:
A command which produces the one's complement of a given quantity.
CONTENT - The quantity or word held in a register or storage location.

Rev. A

Glossary - 2

CORE - A ferromagnetic toroid used as the bi - stable device for storing a bit in
a memory plane.
COUNTER - A register or storage location, the contents of which may be incremented or decremented.
CPU - Central Processing Unit; controls all sequential operations within the
computer. See Main Control.
D - Delimiting indicator (refer to Delimiting).
DELIMITING - During a BDP character operation, character delimiting may
sometimes be used where the operation is terminated if during the course
of the operation a character is recognized as equal (or unequal in some
instructions) to a fixed comparison (or delimiting) character.
DOUBLE PRECISION - Providing greater precision in the results of arithmetic
operations by appending 24 additional bits of lesser significance to the
initial operands.
ENTER - The operation where the current contents of a register or storage
location are replaced by some defined operand.
EQUALIZE - Adjusting the operand of the algebraically smaller exponent to
equal the larger prior to adding or subtracting the floating point coefficients.
EXCLUSIVE OR - A logical function in Boolean algebra that is satisfied (has
the value "1") when any of its terms are "1". It is not satisfied when all
its terms are "1" or when all its terms are "0".
EXECUTION ADDRESS - The lower 15 or 1 7 bits of a 24-bit instruction. Most
often used to specify the storage addre ss of an operand. Sometimes used
as the operand.
EXECUTIVE MODE - An operating mode in which address relocation may occur.
An efficient operating mode consisting of two possible states: Monitor
State and Program State.
EXIT - Initiation of a second control sequence by the first, occurring when the
first is near completion; the circuit involved in exiting.
F REGISTER - Program Control register. Holds a program step while the
single 24-bit instruction contained in it is executed.
FAULT - Operational difficulty which lights an indicator or for which interrupt
may be selected.
FILE MANAGER - A software system operating in conjunction with MSIO and
providing a central repository for all data accruing in a particular data
center, i. e. , a system which creates a file for the user.
FIXED POINT - A notation or system of arithmetic in which all numeric quantities are expressed by a predetermined number of digits with the binary
point implicitly located at some predetermined position; contrasted with
floating point.
Glossary - 3

Rev. A

FLIP-FLOP (FF) - A bi-stable storage device. A "1" input to the set side
puts the FF in the "1" state; a "1" input to the clear side puts the FF in
the "0" state. The FF remains in a state indicative of its last "1" input.
A stage of a re gister consists of a FF.
FLOATING POINT - A means of expressing a number, X, by a pair of numbers.
Y and Z, such that X = Yn z . Z is an integer called the exponent or
characteristic; n is a base, usually 2 or 10; and Y is called the fraction or
mantissa.
FUNCTION CODE - See Operation Code.
INCREASE - The increase operation adds a quantity to the contents of the
spe cified re giste r.
INDEX DESIGNATOR - A 2-bit quantity in an instruction; usually specifies an
index register whose contents are to be added to the execution address;
sometimes specifies the conditions for executing'the instruction.
INDIRECT ADDRESSING - A method of address modification whereby the lower
18 bits of the specified address become the new execution address and
index de signa tor.
INSTRUCTION - A 24- or 48-bit quantity consisting of an operation code and
several other designators.
INTEGRATED REGISTER FILE - The upper 6410 locations of core storage; reserved for special operations with Block ControL
INTERRUPT - A signal which results in transfer of control, following completion of the current instruction cycle, to a fixed storage location.
INTERRUPT REGISTER - A 24-bit register whose individual bits are set to "1"
by the occurrence of specific interrupt conditions, either internal or
external.
INTERRUPT MASK REGISTER - A 24-bit register whose individual bits match
those of the Interrupt register. Setting bits of the Interr_lpt Mask register
to "lis" is one of the conditions for selecting interrupt.
INVERTER - A circuit which provides as an output a signal that is opposite to
its input. An inverter output is 11111 only if all the separate OR inputs are
110 11 .
ISR - Instruction State Register; 3-bit register defining the program address
group being referenced for instructions.
JUMP - An instruction which alters the normal sequence control of the computer and, conditionally or unconditionally, specifies the location of the
next inst:ructio n.
LIBRARY - Any collection of programs (routines) and/ or subprograms
(subroutine s).

Rev. A

Glossary - 4

LOAD - The Load operation is composed of two steps: a) the register is
cleared, and b) the contents of storage location M are copied into the
cleared register.
LOCATION - A storage position holding one computer word, usually designated
by a specific address.
LOGICAL PRODUCT - In Boolean algebra, the AND function of several terms.
The product is "I" only when all the terms are "1"; otherwise it is "0".
Sometimes referred to as the result of bit-by-bit multiplication.
LOGICAL SUM - In Boolean algebra, the OR function of several terms. The
sum is "I" when any or all of the terms are "I"; it is "0" only when all
are "0".
LOOP - Repetition of a group of instructions in a routine.
MACRO CODE - A method of defining a subroutine which can be generated
and/or inserted by the assembler.
MAIN CONTROL - The sequence of events within the CPU controlling the
various operations of program execution; synonomous with Program
Control.
MASK - In the formation of the logical product of two quantities, one quantity
may mask the other; i. e., determine what part of the other quantity is to
be considered. If the mask is "0", that part of the other quantity is unused; if the mask is "111, the other quantity is used.
MASTER - Multiple Acce ss, Shared Time, Executive Routine; an advanced
time-sharing operating system for 3300 and 3500 computers equipped with
the 3311 multiprogramming option.
MASTER CLEAR - A general command produced by pressing one of three switches;
a) Internal Master Clear - clears all operational registers and control
FFs in the processor; b) External Master Clear - clears all external equipments and the communication channels; c) Master Clear - a keyboard switch
that performs both an Internal and External clear.
MCS - Magnetic Core Storage; see CORE.
MNEMONIC CODE - A three-or four-letter code which represents the function
or purpose of an instruction. Also called alphabetic code.
MODULUS - An integer which describes certain arithmetic characteristics of
registers, especially counters and accumulators, within a digital computer.
The modulus of a device is defined by rn for an open-ended device and rn-1
for a closed (end-around) device, where r is the base of the number system
used and n is the number of digit positions (stages) in the device. Generally,
device s with modulus rn use two 1s complement arithmetic; device s with
modulus rn-1 use one IS complement.
MONITOR STATE - An operating state under Executive mode in which all 3300
instructions may be executed. If the 3311 Multiprogramming option is in a
system, address relocation is possible.
Glossary - 5

Rev. A

MSIO - Mass Storage Input/ Output; a basic file oriented I/O program for
operating with mass storage devices and magnetic tape units.
MULTI - PROCESSING- Simultaneous instruction processing; multi -processing
is accomplished in the 3300 by using an additional CPU.
MULTIPROGRAMMING - Alternately servicing instructions from two or more
programs as opposed to completing one job at a time. Multiprogramming
utilize s the time - sharing capabilitie s of the computer under the guidance
of an executive monitor.
NON-EXECUTIVE MODE - An operating mode in which instructions are
sequentially executed and which permits a 3300 to perform identically to a
3200.
NO-OP - No-Operation.
NO-OPERATION - Usually an undefined octal code that produces no useful
function. Some 3300 instructions are No-Operation (NO-OP) instructions
if execution is attempted in non-Executive mode.
NORMALIZE - To adjust the exponent and mantissa of a floating point result so
that the mantissa lies in the prescribed standard (normal) range.
NORMAL JUMP - An instruction that jumps from one sequence of instructions
to a second and makes no preparation for returning to the first sequence.
Also referred to as an unconditional jump.
NUMERIC CODING - A system of abbreviation in which all information is reduced to numerical quantities. Also called absolute or machine language
coding.
OBJECT PROGRAM - The machine language version of the source program.
ONE'S COMPLEME;:\TT - With reference to a binary number, that number which
results from subtracting each bit of a given number from" 1". The one's
complement of a number is formed by complementing each bit of it individually, that is, changing a "1" to "0" and a "0" to a "I". A negative
number is expressed by the one's complement of the corresponding positive
number.
ON-LINE OPERATION - A type of system application in which the input or
output data to or from the system is fed directly from or to the external
equipment.
OPERAND - Usually refers to the quantity specified by the execution address.
OPERATION CODE (Function Code) - A 6-bit quantity in an instruction
specifying the operation to be performed.
OPERATIONAL REGISTERS - Registers which are displayed on the operator's
section of the console.

Rev. A

Glossary - 6

OR FUNCTION - A logical function in Boolean algebra that is satisfied (has
the value "1 ") when any of its terms are" 1". It is not satisfied when all
terms are "0". Often called the inclusive OR function.
OSR - Operand State Register; 3-bit register defining the program address group
being referenced for operands.
OVERFLOW - The capacity of a register is exceeded.
P REGISTER - The Program Address Counter (P register) is a one's complement additive register (modulus 2 15 -l) which defines the storage addresses
containing the individual program steps.
PAGE - 2,048 absolute memory locations which may be subdivided into four
partial pages. Storage allocation is made in whole number multiples of
quarter pages.
PAGE INDEX FILE - A word-organized core matrix consisting of 12-bit page
indexes. The contents of the page indexes are used during address
relocation.
PARAMETER - An operand used by a program or subroutine.
PARITY CHECK - A summation check in which a group of binary digits
are added and the sum checked against a previously computed parity digit;
i. e. , a check which tests whether the number of ones is odd or even.
PICTURE - A compact way of describing a data item.
specify are size, class, sign, and editing.

Among the things it may

PROGRAM - A precise sequence of instructions that accomplishes the solution
of a problem. Also called a routine.
PROGRAM ADDRESS GROUP - A group of sequentially numbered addresses
representing one or more programs within 32,768 words of storage. It
is not a discrete physical device.
PROGRAM ADDRESS REGISTER - Synonomous with P register.
PROGRAM CONTROL - Synonomous with Main Control.
PROGRAM STATE - A highly efficient operating state of Executive mode in
which all 3300 instructions may be executed except those instructions that
call for I/O operations, alter certain register file locations, or halt the
computer.
PROGRAM STATE l\TUMBER -'One of seven Program Address Groups.
PSEUDO CODE - A statement requesting a specific operation by the assembler
or compiler.

Q REGISTER - Auxiliary 24-bit arithmetic register which assists the A register
in the more complicated arithmetic operations.

Glossary - 7

Rev. A

RADIX - The number of different digits that can occur in a digit position for a
specific number system. It may be referred to as the base of a number
system.
RANDOM ACCESS - Access to storage under conditions in which the next
position from which information is to be obtained can be independent of the
previous one.
READ - To remove a quantity from a storage location.
REGISTER - The internal logic used for temporary storage or for holding a
quantity during computation.
REJECT - A signal generated under certain circumstances by either the external equipment or the proce s sor during the execution of I/O instructions.
RELOCATION - Making efficient use of all memory locations by reassignment
through the use of a memory paging system under control of a monitor
program.
REPLACE - When used in the title of an instruction, the result of the execution
of the instruction is stored in the location from which the initial operand was
obtained .. When replace is used in the de scription of an instruction, the
contents of a location or register are substituted by the operand. The
Replace operation implies clearing the register or portion of the register
in preparation for the new quantity.
REPLY - A response signal in I/O operations that indicates a positive response
to some previous operation or reque st signal.
REPORT GENERATOR - Ii language and compiler to reduce the programming
necessary to generate reports.
RETURN JUMP - An instruction that jumps from a sequence of instructions to
initiate a second sequence and prepares for continuing the first sequence
after the second is completed.
ROUTINE - The sequence of operations which the computer performs; also
called a program.
S REGISTER - The 13-bit S register displays the address of the storage word
currently being referenced.
SCALE FACTOR - One or more coefficients by which quantities are multiplied
or divided so that they lie in a given range of magnitude.
SCAN - Synonomous with Search.
SEARCH - Searching a field of characters for a certain condition or a specific
character.
SHIFT - To move the bits of a quantity right or left.

Rev. A

Glossary - 8

SIGN BIT - In registers where a quantity is treated as signed by use of one's
complement notation, the bit in the highest order stage of the register. If
the bit is "1", the quantity is negative; if the bit is "0", the quantity is
positive.
SIGN CHARACTER - A unique character that indicates the algebraic sign (positive
or negative) of a given field of characters. The upper two bits of a normal
6-bit character may be used or in some instances a specially formed 4-bit
character exits.
SIGN EXTENSION - The duplication of the sign bit in the higher order stages of
a register.
SOFTWARE - Programs and/or subroutines.
SOURCE LANGUAGE - The language used by the programmer to define his
program.
STAGE - The FFs and inverters associated with a bit position of a register.
STATUS - The state or condition of circuits within the processor, I/O channels,
or external equipment.
STORAGE CONTROL - The sequence of events within a particular storage
module, controlling various internal storage operations.
STORE - To transmit information to a device from which the unaltered information can later be obtained. The Store operation is essentially the reverse of the Load operation. Storage location M is cleared, and the contents of the register are copied into M.
SUBROUTINE - A set of instructions that is used at more than one point in
program operation.
SYMBOLIC CODING - A system of abbreviation used in preparing information
for input into a computer; e. g. , Shift Q would be SHQ. (See Mnemonic)
TOGGLE - To complement each specified bit of a quantity; i. e.,
" 0" to "1".

"1" to "0" or

TRANSMIT (Transfer) - The term transfer implies register contents are
moved; i. e. , the contents of register 1 are copied into register 2. Unless
specifically stated, the contents are not changed during transmission. The
term transmit is often used synonymously with transfer.
TWO'S COMPLEMENT - Number that results from subtracting each bit of a
number from "0". The two's complement may be formed by complementing
each bit of the given number and then adding one to the result, performing
the required carries.
UNDERFLOW - An ille gal change of sign from - to +, e. g., subtracting from a
quantity so that the result would be less than - (2 n -1), where n is the
modulus. In floating point notation, this occurs where the value of the
exponent becomes less than 2- 10 + 1 (- 17778).
Glossary - 9

Rev. A

WORD - The content of a storage location; it can be an instruction or 24 bits of
data.
WRITE - To enter a quantity into a storage location.
X REGISTER - An arithmetic transfer register, nonaddressable and not
displayed.
Z REGISTER - A 28-bit storage data register; receives the data and parity bits
as they are read from storage or written into storage. Nonaddre ssable but
displayed on the IT I panel in the storage module.

Rev. A

Glossary - 10

TABLE 1. OCTAL LISTING OF INSTRUCTIONS
Octal
Code

Mnemonic
Code

Instruction Description

Address
Field

Page
No.

00.0 HLT

m

Unconditional halt, RNI @ m on restarting

5-24

00.1

SJ1

m

If jump key 1 is set, jump to m

5-41

00.2

SJ2

m

If jump key 2 is set, jump to m

5-41

00.3

SJ3

m

If jump key 3 is set, jump to m

5-41

00.4 SJ4

m

If jump key 4 is set, jump to m

5-41

00.5

SJ5

m

If jump key 5 is set, jump to m

5-41

00.6

SJ6

m

If jump key 6 is set, jump to m

5-41

00.7

RTJ

m

P+1 .... m (address portion) ,RNI @ m+1,
return to m for P+1

5-47

Unconditional jump to m

5-41

m,b

01

UJP,I

02.0

No Operation

m,b
02.1- IJI
3
02.4 No Operation

I

02.5- IJD
7

m,b

If (B b ) = 0, RNI @ P+1; if (Bb) t= 0, (Bb) +

1 _B o , RNI @ m

5-43

b
If (Bb) = 0, RNI @ P+1; if (B ) t= 0, (Bb) 1-Bb,RNI@m

5-44

03.0

AZJ ,EQ

m

If (A) = O,RNI @ m, otherwise RNI @ P+1

5-45

03.1

AZJ,NE

m

If (A)

f O,RNI @ m, otherwise RNI @ P+1

5-45

03.2

AZJ,GE

m

If (A) ;? 0, RNI @ m, otherwise RNI @ P+1

5-45

03.3

AZJ,LT

m

If (A)

03.4

AQJ,EQ

m

If (A) = (Q), RNI @ m, otherwise RNI @ P+1

5-46

03.5

AQJ,NE

m

If (A) t= (Q),RNI @ m,otherwiseRNI@P+1

5-46

03.6

AQJ,GE

m

If (A) ;?(Q),RNI @ m,otherwise RNI@P+1

5-46

03.7 . AQJ,LT

m

If (A)

@m,otherwiseRNI@ P+1

5-46

Y
y,b

If y = O,RNI @ P+2, otherwise RNI @ P+1

5-28

y

If y = (A), RNI @ P + 2, otherwise RNI @

04.0

ISE

04. l- ISE
3
04.4 ASE,S

04.6
04.7

QSE,S
ASE
QSE

RNI @ m, otherwise RNI @ P+1

< (Q),RNI

Sign of y extended.

Y

If Y = (Q), RNI @ P + 2, otherwise RNI @

Y

If y = (A), RNI @ P + 2, otherwise RNI @

Y

5-45

If y = (Bb),RNI @ P+2,otherwiseRNI@P+1 5-28

P+1.
04.5

< 0,

P+1.
P+1.

Sign of y extended.
Lower 15 bits of A are used.

5-29
5-29
5-29

If Y = (Q), RNI @ P + 2, otherwise RNI @

P+1.

Lower 15 bits of Q are used.

Instruction Tables - 1

5-29

Rev K

TABLE 1.
Octal
Code

Mnemonic
Code

OCTAL LISTING OF INSTRUCTIONS (Cont 1d)
Instruction De scription

Addre ss
Field

Page
No.

Y

If y = 0, RNI @ P+2, otherwise RNI @ P+1

5- 30

05.1-3 ISG

y,b

(Bb) ?y,RNI@P+2,otherwise RNI @ P+1

5-30

05.4

Y

If (A) ?y, RNI @ P+2, otherwise RNI @
P+1. Sign of y is extended

5- 30

If (Q) ?y, RNI @ P+2, otherwise RNI @
P+1. Sign of y is extended

5- 30

05.0

05.5

ISG
ASG ,S
QSG,S

y

05.6

ASG

y

If (A) ?y, RNI @ P+2, otherwiseRNI@P+l 5-30

05.7

QSG

y

If (Q)?y,RNI @ P+2,otherwise RNI@ P+1

06

MEQ

m,i

(B1) - i --+B1; if (B1) negative,RNI @P+1;
if (Bl) positive,test (A) = (Q) f\ (M); if
true, RNI @ P+2; if false, repeat sequence 5-73

07

MTH

m,i

(B2)-i--+B2; if (B2) negative RNI @ P+1; if
(B2) positive, te st (A) ? (Q) f\ (M); if true,
RNI @ P+2; if false, repeat sequence
5-74

SSH

m

Test sign of (m), shift left one place, end
around, replace in storage. If sign negative, RNI @P+2; otherwise RNI @ PH

10.0

10. 1-3 lSI
10.4-7 ISD

y,b
y,b

5-30

5-57

b

If {B )= y, clear Bb and RNI @ P+2; if
(Bb) f- y, (Bb) + 1 ->- B b , RNI @ P+1

5- 31

If (Bb) = y, clear Bb and RNI @ P+2; if
(BD) f- y, (Bb) - 1 ->- B b , RNI @ P+l

5-31

11. 0-3 ECHA

z

z -+A, lower 17 bits of A are used

5-26

11. 4 - 7 E CHA , S

12.4-7 SHQ

k,b

13.0-3 SHAQ

k,b

z-+A, signofzextended
Shift (A). Shift count K=k+(B b ) (signs of k
and Bb extended.)If bit 23 of K=11111, shift
right; complement of lower 6 bits equals
shift magnitude. If bit 23 of K=11011 , shift
left; lower 6 bits equals shift magnitude.
Left shifts end around;right shifts end off.
Shift (Q). Shift count K=k+(Bb)(signs of k
and Bb extended. If bit 23 of K=111!1,shift
right;complement of lower 6 bits equals
shift magnitude. If bit 23 of K=11011 , shift
left;lower 6 bits equals shift magnitude.
Left shifts end around;right shifts end off.
Shift (AQ) as one register. ShifL count K=
k+(Bb) (signs of k and Bb extended). If
bit 23 of K= 11111 , shift right; complement of
lower 6 bits e quaIs shift magnitude. If bit
23 of K=11011,shift left;lower 6 bits equal
shift m?-gnitude. Left shifts end around;
right shifts end off.

5-26

12.0-3 SHA

z
k,b

Rev K

Instruction Tables - 2

5- 57

5- 59

5- 59

TABLE 1.
Octal
Code
13.4-7

OCTAL LISTING OF INSTRUCTIONS (Cont'd)
Instruction De scription

Mnemonic Address
Code
Field
SCAQ

k,b

Shift (AQ) left end around until upper 2 bits
of A are unequal. Re sidue K = k - shift
count. If b = 1,2, or 3, K - Bb; if b = 0, K
is discarded.

Page
No.
5-59
5-59

y,b

No operation (COMPASS assembled NOP)
b
Clear B , enter y

5-25

ENA,S

Y

Clear A, enter y, sign of y extended

5-25

14.5

ENQ,S

Y

Clear Q, enter y, sign of y extended

5-25

14.6

ENA

Y

Clear A, enter y

5-25

14.7

ENQ

Clear Q, enter y

5-25

15

Y
No Operation

15.1-3

INI

y,b

b
Increase (B ) by y, signs of y and Bb
extended

5~ 27
5-27

15.4

INA,S

y

Increase (A) by y, sign of y extended

5-27

15.5

INQ,S

Y

Increase (Q) by y, sign of y extended

5-27

15.6

INA

Y

Increase (A) by y

5-27

15.7

INQ

Increase (Q) by Y

5-27

16.0

Y
No Operation

16.1-3

XOI

y,b

16.4

XOA,S

16.5

XOQ,S

Y
y

16.6

XOA

16.7

XOQ

17.0

No Operation

17.1-3

ANI

y,b

17.4

ANA,S

Y

17.5

ANQ,S

17.6

ANA

Y
y

17.7

ANQ

20

14.0

No Operation

14. 1-3

ENI

14.4

Y
y

Y v (Bb) ~Bb
Y v (A) -A, sign of y extended
y v (Q) -Q,

sign of y extended

5-69
5-69
5-69

y v (A) -A

5-69

y v (Q) -Q

5-69

b
Y /\ (Bb) _B
y/\ (A) -A, sign of y extended

5-71

y/\ (Q) -Q, sign of y extended

5-72
5-71

y

Y /\ (A) -A
y /\ (Q) -Q

LDA,I

m,b

(M) -A

5-49

21

LDQ,I

m,b

(M) -Q

5-51

22

LACH

r,l

(R) -A. Load lower 6 bits of A

5-49

23

LQCH

r,2

(R) -Q. Load lower 6 bits of Q

5-52

Instruction Tables - 3

5-71

5-72

RevK

TABLE 1.

OCTAL LISTING OF INSTRUCTIONS (Cont'd)
Instruction Description

Octal IMnemonic Address
Field
Code Code

Page
No.
5-50

24

LCA,I

m,b

(M) -A

25

LDAQ,I

m,b

(M)

26

LCAQ,I

m,b

(M) -A, (M + 1)

27

LDL,I

m,b

(M)

(Q) -A

5-50

30

ADA,I

m,b

Add (M) to (A) - A

5- 60

31

SBA,I

m,b

(A) minus (M)

32

ADAQ,I

m,b

Add (M,M + 1) to (AQ) -AQ

33

SBAQ,I

m,b

(AQ) minus (M, M + 1)

34

RAD,I

m,b

Add (M) to (A) -.. (M)

5-60

35

SSA,I

m,b

Where (M) contains a "1" bit, set the corre sponding bit in A to "1"

5- 70

36

SCA,I

Where (M) contains a "1" bit, complement
the corre sponding bit in A

5- 70
5- 71

1

m,b

~A,

f\

(M + 1)-Q

5-50

~Q

5-51

5-61

~A

~

5-61
5-61

AQ

37

LPA,I

m,b

(M)

40

STA,I

m,b

(A)

(M)

5-53

41

STQ,I

m,b

(Q) -- (M)

5-55

42

SACH

r,2

(AOO-05) - R

5-54

43

SQCH

r,l

(QOO-05) -.. R

5-55

44

SWA,I

m,b

(AOO-14) -(MOO-14)

5-56

45

STAQ,I

m,b

(AQ)

5-54

46

SCHA,I

m,b

5-56

47

STLI

m,b

(AOO-16) ~(MOO-16)
b
(B ) -..(MOO-14)

50

MUA,I

m,b

Multiply (A) by (M) -.. QA; lowest order bits
of product in A

5-62
5-62

51

DVA,I

m,b

(AQ)+ (M) - A, remainder ..... Q

5-62

52

CPR,I

m,b

(M) >(A), RNI @ P+l
(Q)
(A)

(A)-A

f\
~

->-

(M ,M + 1)

> (M),

5-56

}

(A) and (Q) are
5- 75
unchanged

53. (0-3)0

TIA

b

53. (5-7)0

TAl

b

RNI @ P+2
~ (M) ~ (Q), RNI @ P+3
b
Clear (A), (B ) -.. AOO-14
b
(AOO-14)-" B

53. (0-3)1

TMQ

v

(v) -Q

5-34

53. (4-7)1

TQM

v

(Q) - v

5-34

53. (0-3)2

TMA

v

(v) -A

5-34

53. (4-7)2

TAM

v

(A) - v

5-34

Rev K

Instruction Tables - 4

5-33
5-33

TABLE 1.

OCTAL LISTING OF INSTRUCTIONS (Cont'd)
Instruction De scription

Octal Mnemonic Address
Field
Code Code
53. (1-3)3

TMI

v,b

53.43

TIM

v,b

53.04

AQA

53. (1-3)4

AIA

53. (5-7)4

IAI

54

LDI,I

55.0

RIS

b
b

m,b

b
(VOO-14) - B
b
(B ) ->- vOO-14
Add (A) to (Q) - A
Add (A) to (Bb) -+ A

Add (A) to (Bb) -+ Bb.
prior to addition

Page
No.
5-35
5-35
5-32
5-33

Sign of Bb extended

All other combinations of 53 are undefined
and will be rejected by the assembler
b
(MOO-14) -B
Use (ISR) in address relocation for
operands. RELOCATE TO INSTRUCTION
STATE
(E

5-33

5-52

5-109
5-36

55.1

ELQ

55.2

EUA

) -Q
L
(EU) -+ A

55.3

EAQ

(EUE L ) -AQ

55.4

ROS

Use (OSR) in address relocation for
operands. RELOCATE TO OPERAND
STATE

5-109

5-36
5-36

55.5

QEL

(Q) - EL

5-36

55.6

AEU

(A) -EU

5-36

55.7

AQE

5-36

56

MUAQ,I

m,b

(AQ) -EUEL
Multiply (AQ) by (M,M + 1) -AQE

5-63

57

DVAQ,I

m,b

(AQE) ... (M,M + 1) -+AQ and remainder
with sign extended to E. Divide fault halts
operation and program advances to next
instruction

5-63

Floating point addition of (M, M + 1) to
(AQ) -AQ

5-65

Floating point subtraction of (M, M + 1)
from (AQ) - AQ

5-65

Floating point multiplication of (AQ) and
(M,M + 1) .... AQ

5- 66

Floc;l.ting point division of (AQ) by (M,M
-+ AQ, remainder with sign extended
to E

5-66

Move characters from fld A -fld C according to parameters given

5-

60
61
62
63

64.0

FAD,I

m,b

FSB,I

m,b

FMU,I

m,b

FDV,I

m,b

MVE

r, B r ,
Sl, s,
BSJ S2

+ 1)

Instruction Tables - 5

12~

Rev K

I

TABLE 1.

OCTAL LISTING OF INSTRUCTIONS (Cont'd)

64. 0

MVE, DC r, B r ,
s, B s ,
$2

64.1

MVBF

r ,B r ,
§1' s,
B s ' S2

Page
No.

Instruction De scription

Octal Mnemonic Addre ss
Code Code
Field

Move characters from fld A - fld C
according to parameters given. Delimiting
character possibility
5-124
Move characters from fld A - fld C; if
fld C fld A, blank fill

5-125

>

64.2

MVZF

Move characters from fld A -fld C; if
fld C > fld A, zero fill

5-126

64.3

MVZS

Move characters from fld A - fld C; suppress leading zeros

5-127;

64.3

64.4

Move characters from fld A -fld C; suppress leading zeros. Delimiting character
5-1281
po ssibility

MVZS,DC

Fld A - fld C with COBOL type of editing
specified by picture previously stored in
fld C

EDIT

64.4

FRMT

65.0

SCAN,
LR,EQ

5-132

Fld A - fld C with editing specified by
picture previously stored in fld; limited
to specific types of editing to allow processing in a single scan.

r, B r ,
S2, SC
r, B r ,
S2, SC

Scans fld A from left to right, stop on =
condition

5-138

SCAN,
LR, EQ,
DC

65. 1

SCAN,
RL,EQ

r, B r ,
S2, SC

Scans fld A from right to left, stop on =
condition

5-142

65. 1

SCAN,
RL, EQ,
DC

r, B r ,
S2, SC

Scans fld A from right to left, stop on =
condition. Delimiting character
possibility

5-143

65. ~

SCAN,
LR,NE

r, B r ,
S2, SC

Scans fld A from left to right, stop on
condition

5-140

65.2

SCAN,
LR,NE
DC

r, B ,
r
S2, ;:;C,

Scan fld A from left to right, stop on f
condition. Delimiting character possibility 5-141

65.3

SCAN,
RL,NE

r, B r ,
S2,SC

Scans fld Afrom right to left, stop on
condition

RevK

i

Scans fld A from left to right, stop on =
condition. Delimiting character possibility 5-139

65.0

Instruction Tables - 6

=1=

f
5-144

TABLE 1.

OCTAL LISTING OF INSTRUCTIONS (Cont'd)

Octal Mnemonic Address
Field
Code Code
65.3

SCAN, RL, r,B r ,
S2, SC,
NE,DC

66.0

CVDB

66.1

CVBD

66.2

DTA*

66.2

DTA, DC:-

66.3

ATD*

66.3

ATD,DC*

66.4

PAK

Instruction Description

Scans fld A from right to left, stop on :/:
condition. Delimiting character possibility

r, B r ,
Convert BCD fld A to binary fld --+ C
Sl, m,
Bm
m, B m , Convert binary fld A to BCD ->- fld C
n, Bn

Page
No.

5-145
5-140

5-147

r, B r ,
S2, m,
Bm
r, B r ,
S2 ,m.
Bm
m,B m ,
S 2, s,
Bs
m,B m ,
S2 , s,
Bs

Translate BCD fld A to ASCII -fld C

5-148

Translate BCD fld A to ASCII ->-fld C with
delimiting character possibility

5-149

Translate ASCII fld A to BCD -dId C

5-150

Translate ASCII fld A to BCD ->- fld C with
delimiting character possibility

5-151

r, Br
S2, m,

Pack 6-bit BCD fld A into 4-bit BCD fld C

5-152

Bm
66.5

UPAK

67.0

ADM

57. 1

SBM

67.2

ZADM

m,B m ,
s, B s ,
S2
r, B r ,
Sl' s,
B s ' S2
r, B r ,
Sl, s,
B s ' S2
r, B r ,
Sl' s,
B s , S2

Unpack 4-bit BCD fld A into 6-bit BCD fld C 5-153

Add fld A to fld C ->- fld C

5-154

Subtract fld A from fld C ->- fld C

5-156

Clear fld C; fld A -fld C, right justify

5-129

I

':'Available in 3312 and 3304-2 only.

Instruction Tables - 7

Rev·K

TABLE 1.

OCTAL LISTING OF INSTRUCTIONS (Cont'd)

Basic Mnemonic Address
Octal
Code
Field
Code

I

Instruction Description

Page
No.

5-158

67.3

CMP*

r, B r ,
S 1> s,
B s ' S2

Compares fld A to fld C, exits upon
encountering -f characters

67.3

CMP, DC*

r, B r ,
s, B s ,
S2

Compares fld A to fld C, exits upon encountering :f. characters; delimiting
character possibility

5-162
5-159

67.3

CMP':":'

r, B r , Sl'
s, Bs, S2

Collating Compare of Field A with
Field C

67.3

CMP, N':":'

Numeric compare of Field A with
Field C

5-159

67.4

TST

Test fld A, +, -, or 0

5-165

67.4

TSTN

Test fld A for numeric

5- 166

70.0

JMP, HI

r, B r , Sl'
s, Bs' S2
r, Br,
Sl
r, B r ,
Sl
m

Jump if BDP condition register > 0 or +

5-42

70.1

JMP, ZRO m

Jump if BDP condition register = 0

5-42

70.2

JMP,LOW m

Jump if BDP condition register < 0 or -

5-42

70.6

LBR

m

Load BCR and restore BDP conditions
from data at 'm'

5- 167

70.7

SBR

m

Store (BCR) and BDP conditions at 'm'
for interrupt recovery.

5- 168

71

SRCE,
INT

SC, r, s

Search for equality of scan character
'SC' in a field beginning at location r
until an equal character is found, or
until character location s is reached;

5- 111

Same as SRCE except search condition i!
for inequality

5- 113

71

SRCN,
INT

SC, r, s

72

MOVE,
INT

S, r, s

Move (S) characters from r to s

5- 115

73.0-3 INPC, INT
B,H,G

ch, r, s

A 6- or 12-bit character is read from
peripheral device and stored in memory
at a given location

5- 95

73.4-7 INAC,
INT

ch

(A) is cleared and a 6- bit character is
transferred from a peripheral device to
the lower 6 bits of A

5- 103

74.0-3

ch, m,
n

Word address is placed in bits 00-14,
12- or 24-bit words are read from a
peripheral device and stored in memory

5- 97

INPW,
INT, B, N,
G

*Available in 3312 and 3304-2 only.
in 3304-3 only.

'~'~Available

Rev K

Instruction Tables - 8

OCTAL LISTING OF INSTRUCTIONS (Cont 1d)

TABLE 1.

Instruction Description

Basic Mnemonic Address
Octal Code
Field
Code

Pa,ge
No.

74.4-7

INAW,
INT

ch

(A) is cleared and a 12-or 24-bit word is
read from a peripheral device into the lower
12 bits or all of A (word size depend s on
I/O channel}
5-104

75.0-3

OUTC.
INT,B,H

ch,r, s

Storage words disassembled into 6- or 12bit characters and sent to a peripheral
device

5-99

Character from lower 6 bits of A is sent to
a peripheral device,(A) retained

5-106

75.4-7
76.0-3
76.4-7

77

OTAC,
INT

ch

OUTW,
INT, B, N

ch,m,n Words read from storage to a peripheral
device

OTAW,
INT

ch

CON

x, ch

5-101

Word from lower 12 bits or all of A (depending on type of I/O channel) sent to a
peripheral device

5-107

If channel ch is busy, reject instruction
RNI @ P + 1. If channel ch is not busy, 12bit connect code sent on channel ch with
connect enable, RNI @ P + 2

5-90

77.1

SEL

x, ch

If channel ch is busy, read reject instruction
from P + 1. If channel ch is not busy, a
12 - bit function code is sent on channel ch
with a function enable, RNI @ P + 2
5-9'2

77. 2 ch, X;
X# 0

EXS

x, ch

Sense external status if 11111 bits occur on
status lines in any of the same positions as
11111 bits in the mask, RNI @ P + 1. If no
comparison, RNI @ P + 2

77 . 2 ch, X;
X =0

COpy

ch

External status code from I/O channel ch -+
lower 12 bits of A, contents of interrupt
mask register -upper 12 bits of A; RNI @
P

77. 3 ch, X;
X#O

77.3 ch. X;
X = 0
77.4

77.50

INS

x, ch

5-78

+1

5-78

Sense internal status if 11111 bits occur on
status lines in any of the same positions as
11111 bits in the mask, RNI @ P + 1. If no
comparison, RNI @ P + 2

5-80

CINS

ch

Interrupt mask and internal status to A

5-81

INTS

x, ch

Sense for interrupt condition: If 11111 bits
occur simultaneously in interrupt lines and
in the interrupt mask, RNI @ P + 1; if not,
RNI @ P + 2

5-79

Interrupt faults defined by x are cleared

::5-84

INCL

x

Instruction Tables - 9

Rev K

TABLE 1.

OCTAL LISTING OF INSTRUCTIONS (Contld)
Instruction Description

Basic Mnemonic Address
Field
Octal Code
Code
77.51
77.511

Page
No.

IOCL

x

Clears I/O channel or search/move control
as defined by bits 00-07, 08, and 11 of x.

5- 89

CILO

x

Lockout external interrupt on masked
channels (x). until channel(s) is not busy.

5- 86

77.512

CLCA

x

Clear the specified channel, but not external
5- 89
equipment. CLEAR CHANNEL ACTNITY

77.52

SSIM

x

Selectively set interrupt mask register for
each 11111 bit in x. The corresponding bit
in the mask register is set to 11111

5- 85

Selectively clear interrupt mask register
for each 11111 bit in x. The corresponding
bit in the mask register is set to 11011

5- 85

AOO-02 ~ CIR
A TO CHANNEL INDEX REGISTER

5-38

77.53

77.54

SCIM

x

ACI

77.55

CIA

Clear A; Channel index register - AOO-02

5-38

77.56

JAA

Last executed jump address - A
JUMP ADDRESS TO A

5-40

Interrupt associated processor

5- 110

Sense busy lines. If 11111 appears on a line
corresponding to 11111 bits in x, do not advance P. If P is inhibited for longer than
40 ms, read reject instruction from P + 1.
If no comparison, RNI @ P + 2

5- 82

Same as PAUS except real-time
clock cannot increment during the pause
PRIORITY PAUSE

5- 83

Initiate memory request. If reply occurs
within 5 usec, RNI @ P + 2; if not, RNI @
P + 1. Storage address is (B2) with (OSR)
or zero appended. TEST MEMORY
A V AILABILITY

5- 77

,
77.57

IAPR

77.60

PAUS

77.61X PRP
X =f. 0
77.61X TMAV

X = 0

77.62

77.624

SBJP

SDL

x

Transfers system from Monitor State to
Program State when next jump instruction
is executed. SET BOUNDARY JUMP

5- '109

Cause s next LDA instruction to:
1. (M) -A
2. Store 77777777 @ M
SET DESTRUCTIVE LOAD

5-110

77.63

CRA

Clear A; Condition

77.634

ACR

AOO-05

Rev K

-+

register~

Condition register

Instruction Tables - 10

AOO-05

,

5-40
5-40

i

TABLE 1.

OCTAL LISTING OF INSTRUCTIONS (Cont'd)

Instruction Description
Basic Mnemonic Address
Field
Octal Code
Code
APF
w,2
77.64
A OO - l l to page file
A TO PAGE FILE
77.65
77.66
77.664

PFA
AOS
AIS

w,2

77.674
77.70

OSA
ISA
SLS

No.

5-39

Clear A, page file index -A OO l l
PAGE FILE TO A

5-39

AOO-02 -+ OSR
A TO OPERAND STATE REGISTER

5-37

A OO - 02

-+

ISR

A TO INSTRUCTION STATE REGISTER
77.67

Page

Clear A; OSR

5-37

OO 02
OPERAND STATE REGISTER TO A

5-37

Clear A; ISR -+ AOO-02
INSTRUCTION STATE REGISTER TO A

5-37

Program stops if Selective Stop switch is
on; upon restarting, RNI @ P + 1

5-24

-+

A

77.71

SFPF

Set floating point fault logic

5-86

77.72

SBCD

Set BCD fault logic

5-86

77.73

DINT

Disables interrupt control

5-84

77.74

EINT

Interrupt control is enabled, allows one more
5-84
instruction to be executed before interrupt

77.75

CTI

Set Type In

Beginning character address
must be preset in location 23
of register file and last
character addre ss + 1 must
be preset in location 33 of
the file

77.76

CTO

Set Type Out

77.77

UCS

Unconditional stop.
@ P + 1

5-94

Upon restarting, RNI

Instruction Tables - 11

5-24

Rev K

TABLE 2.

ALPHAMNEMONIC LISTING OF INSTRUCTIONS

Mnemonic Basic Address
Octal Field
Code
Code
77
ACI
ACR

77

ADA,I

30

m,b

ADAQ, I
ADM

32
67

m,b
r, B r , Sl,
s, B s ' S2

AEU

55

AIA

53

AIS

77

b

Instruction Description

Page
No.

AOO-02 ->- crn
A TO CHANNEL INDEX REG I STER
AOO-05 to Condition register
Add (M) to (A) ->- A

5-38
5-40

Add (M, M + 1) to (AQ) ->- AQ
Add fld A to- fld C -+ fld C

5-6l
5- 15i\:

(A) -EU

5-36

Add (A) to (Bb) - A

5-33

AOO-02 -ISR
A TO INSTRUCTION STATE REGISTER

5-37

5-60

ANA

17

Y

Y fI (A) -A

5-71

ANA,S

17

Y A (A) .... A, sign of y extended

5-71

ANI

17

Y
y,b

Y

fI

(Bb) .... Bb

5-71

ANQ

17

y

y

fI

(Q) -Q

5-72

ANQ,S

17

y

y A (Q) -Q, sign of y extended

5-72

AOS

77

AOO-02 -OSR
A TO OPERAND STATE REGISTER

5-37

AOO-11 -page file
A TO PAGE FILE

5-39

APF

77

w,2

AQA

53

Add (A) to (Q) - A

5-32

AQE

55

5-36

AQJ ,EQ

03

(AQ) -EUEL
If (A) = (Q), RNI @ m, otherwise RNI @
P+1

AQJ ,GE
AQJ ,LT
AQJ ,NE
ASE
ASE,S
ASG

Rev K

03
03
03
04
04
05

m

5-46

If (A)
P+1

?

m

If (A)
P + 1

< (Q),

m

If (A) t= (Q), RNI @ m, otherwise RNI @
P+1

~-46

Y

If y = (A), RNI @ P + 2, otherwise RNI @
P + 1. Lower 15 bits of A are used.

5-29

Y

If y = (A), RNI @ P + 2, otherwise RNI @
P + 1, sign of y is extended

5-29

Y

If (A)
P+1

m

(Q), RNI @ m, otherwise RNI @
5-46
RNI @ m, otherwise RNI @
5-46

?

y, RNI @ P + 2, otherwise RNI @

Instruction Tables - 12

5-30

I

TABLE 2.

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Cont'd)

Mnemonic Basic Address
Code
Octal Field
Code
ASG,S

05

Y

Page
No.

Instruction Description

If (A) ? y, RNI @ P + 2, otherwise RNI @
P + 1, sign of y is extended

5-30
5-150

ATD

66

InE 1n ,
52' s,
Bs

Translate ASCII fld A to BCD

ATD,DC

66

In,B 1n ,
52' s,
Bs

Translate ASCII fld to BCD ->- fld C with
delimiting character possibility

m

If (A)
P+l

= 0,

If (A)
P+l

?

If (A)
P+l

< 0,

If (A)
P+l

f

AZJ ,EQ

03

AZJ,GE

03

AZJ,LT

m

03

AZJ,NE

m

03

m

CIA

77

CILO

77

x

-+

fld C

5-151

RNI @ m, otherwise RNI @
5-45

0, RNI @ m, otherwise RNI @
5-45
RNI @ m, otherwise RNI @
5-45

0, RNI @ m, otherwise RNI @
5-45

Clear A; Channel index register ->-AOO-02

5- 38

Lockout external interrupt on masked
channels (x), until channel(s) is not busy

5- 86

CINS

77

ch

Interrupt mask and internal status to A

5-81

CLCA

77

x

Clear the specified channel, but not external equipment. CLEAR CHANNEL
ACTIVITY

5-89

CMP':'

67

r,B r ,
51, s,
B s , 52

Compare s fld A to fld C, exits upon encountering f characters

5-158

r, B r ,
s, Bs
52

Compares fld A to fld C, exits upon encountering f characters; delimiting
character possibility

5-162

67

CMP,DC:'

67

CMP':":'
CMP,

CON

77

COpy

77

CPR,I

52

CRA

r, B r , S1' Collating compare of Field A with Field C
s, B s ' S2

67

N'~

I

77

r, B r , S1; Numeric compare ofField A with Field C
s, B s ' S2
If channel ch is busy, reject instruction,
x,ch
RNI@P+1. If channel ch is not busy,
12-bit connect code sent on channel ch
with connect enable, RNI @ P+2.
External status code from IIO channel ch
ch
to lower 12-bits of A, contents of interrupt mask register to upper 12-bits of
A RNI @ P+l
(M) > (A), RNI @ P+l
} (A) and (Q)
m,b
are
(Q) > (M), RNI @ P + 2
(A) > (M) > (Q), RNI @ P+:1 unchanged

I

,

-

-

I Condition register to AOO-05

5-159

5-159

5-90

5-78
5-75
5-40

I

':'~L\vailable in 3312 and 3304-2 only
':":'Available in 3304-3 only

Instruction Tables - 13

Rev K

TABLE 2.

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Cont'd)

Mnemonic Basic Address
Code
Octal Field
Code

I

Instruction Description

Page
No.

Beginning character address must be preset in
location 23 of register
file and last character ad- 5-94
dre ss + 1 must be pre set
in location 33 of the file

CTI

77

Set Type In

CTO

77

Set Type Out

CVBD

66

r, B r ,
m,B m

Convert binary fld A to BCD -fld C

5-147

CVDB

66

m, Bm.
Sl, s,
Bs

Convert BCD fld A to binary - fld C

5-146

DINT

77

Disable s interrupt control

5-84

DTA

66

Translate BCD fld A to ASCII -fld C

5-148

DTA,DC

66

r,B r ,
S2, m,
Bm
r, B r ,
S2,m,
Bm

Translate BCD fld A to ASCII - fld C with
delimiting character possibility

5-149
5- 62

DVA,I

51

m,b

(AQ)+ (M)

DVAQ,I

57

m,b

(AQE) + (M,M + 1) -AQ and remainder with
sign extended to E. Divide fault halts operation and program advances to next
instruction
5- 63

EAQ

55

ECHA

11

z

z - A, lower 17 bits of A are used

5-26

ECHA,S

11

z

z - A, sign of z extended

5-26

EDIT

64

r, B r ,
Sl, s ,>
Bs, S2

Fld A - fld C with COBOL type of editing
specified by picture previously stored in
fld C

5-132

Interrupt control is enabled. Allows one
more instruction to be executed before
interrupt

5-84

(EL) ->-Q

5-36

EINT

(EUEL)

77

->-

A, remainder

->-

Q

~AQ

5-36

ELQ

55

ENA

14

y

Clear A, enter y

5-25

ENA,S

14

Y

5-25

ENI

14

y,b

Clear A, enter y, sign of y extended
Clear B b , enter y

ENQ

14

y

Clear Q, enter y

5-25

Rev K

Instruction Tables - 14

5-25

TABLE 2.

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Cont'd)

Mnemonic Basic Address
Octal Field
Code
Code
ENQ,S

14

Y

EUA
EXS

55
77

x,ch

FAD,I

60

m,b

FDV,I

FMU,I
FRMT

FSB,I
HLT
IAI
IAPR
IJD
IJI

63

62
64

61
00
53

Instruction Description

Clear Q, enter y, sign of y extended

5-25

(EU) -A
Sense external status if "1" bits occur on
status line s in any of the same positions
as "1" bits in the mask, RNI @ P+1. If
no comparison RNI @ P+2.
Floating point addition of (M, M + 1) to
(AQ) -AQ

5-36

5-78

5- 66

Floating point multiplication of (AQ) and
(M,M + 1) -AQ

5- 66

Fld A -fld C with editing specified by
picture previously stored in fld; limited to
specific types of editing to allow processing in a single scan.

5-130

m,b

Floating point subtraction of (M,M + 1)
from (AQ) ->- AQ

5-65

m

Unconditional halt, RNI @ m upon restarting

5-24

m,b
r, Br,
Sl' s,
B s , S2

b

Add (A) to (Bb) -to Bb.
prior to addition

02

If (Bb) = 0, RNI @ P + 1; if (Bb) t= 0, (Bb)
- 1 -o-B b , RNI @ m
If (Bb)
0, RNI @ P + 1; if (B b ) t= 0, (Bb)
+ 1 -B . RNI @ m

m,b

5-33
5-110
5-44

b

5-43

INA

15

Y

Increase (A) by Y

5-27

INA,S

15

Increase (A) by y, sign of y extended

5-27

INAC,
INT

73

Y
ch

(A) is cleared and a 6-bit character is
transferred from a peripheral device to
the lower 6 bits of A

5-103

INAW,
INT

74

ch

(A) is cleared and a 12- or 24-bit word is
read from a peripheral device into the
lower 12 bits or all of A (word size depends
5-104
on 110 channel}

INCL

77

x

Interrupt faults defined by x are cleared

5-84

INI

15

y,b

Increase (Bb) by y, signs of y and Bb
extended

5-27

Instruction Tables - 15

I

Sign of Bb extended

Interrupt associated processor
m,b

I

5- 65

Floating point division of (AQ) by (M, M +
1) ->- AQ, Remainder with sign extended to
E.

m,b

77

02

Page
No.

Rev K

I

TABLE 2.

,

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Cont'd)

Mnemonic Basic Address
Octal Field
Code
Code
'INPC,
73
ch,r,s
INT,B,
H,G

Instruction Description

Page
No.

A 6- or 12-bit character is read from a
peripheral device and stored in memory
at a given location

5-95

INPW,
INT,B,
N,G

74

ch,m,
n

Word Address is placed in bits 00-14, 12or 24-bit words are read from a peri5-97
pheral device and stored in memory

INQ

15

Y

Increase (Q) by Y

5-27

INQ,S

15

Increase (Q) by y, sign of y extended

5-27

INS

77

Y
x,ch

Sense internal status if "1" bits occur on
status line s in any of the same positions
as "1" bits in the mask, RNI @ P + 1.
If no comparison, RNI @ P + 2

5-80

INTS

77

c,ch

Sense for interrupt condition; if "1" bits
occur simultaneously in interrupt lines
and in the interrupt mask, RNI @ P + 1;
if not, RNI @ P + 2

5-79

Clears I/O channel or search/move control as defined by bits 00-07, 08, and 11
of x.

5- 89

Clear A, ISR ..... AOO-02
INSTRUCTION STATE REGISTER TO A

5-37

IOCL

ISA

77

77

ISD

10

ISE

04

ISE
ISG
ISG
lSI

x

04
05
05
10

y,b

If (Bb)
if (Bb)

= y,

clear Bb and RNI @ P + 2;
-+ Bb, RNI @ P + 1

t- y, (Bb) - 1

= 0,

5-31

Y

If y

P+1

5-28

y,b

If y = (B b ), RNI @ P + 2, otherwise RNI
@P + 1

5-28

= 0,

RNI @ P+2, otherwise RNI @

Y

If y

y,b

If (Bb) ?: y, RNI @ P + 2, otherwise RNI
@P + 1
b ) = y, clear Bb and RNI @ P + 2; if
If
(B ) t- y, (Bb) + 1 -- Bb, RNI @ P + 1

5-31

Last executed jump addre ss - A
JUMP ADDRESS TO A

5-40

y,b

RNI @ P + 2, otherwise RNI @

P+1

5-30
5-30

bB

JAA

77

JMP, HI

70

m

Jump if BDP condition register> 0 or +

5-42

JMP,
LOW

70

m

Jump if BDP condition re gister

c::::::

5-42

JMP,
ZRO

70

m

Jump if BDP condition register

=0

Rev K

Instruction Tables - 16

0 or -

5-42

TABLE 2.

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Cont'd)

Mnemonic Basic Address
Octal Field
Code
Code

Instruction Description

Page
No.

LACH

22

r, 1

(R) - A; load lower 6 bits of A

5-49

LBR

70

m

5-167

LCA,I

24

m,b

Load BCR and restore BDP conditions
from data at 'm'
(M) -A

LCAQ,I

26

m,b

(M) -A, (M + 1) --Q

5- 51

20

m,b

(M) -A

5-49
5-50

LDA,I
LDAQ,I

25

m,b

LDI,I

54

m,b

(M) -A, (M + 1) -Q
b
(M OO - 14 ) -B

5-50

5- 52

LDL,I

27

m,b

(M) A (Q)-A

LDQ,I

21

m,b

(M) -Q

5- 51

LPA,I

37

m,b

(M) A (A)-A

5-71

LQCH

23

r,2

(R) - Q; load lower 6 bits of Q

5-52

MEQ

06

m,i

(B1) - i - B1; if (B1) negative, RNI @
P + 1; if (B1) positive, test (A) = (Q) A
(M); if true, RNI @ P + 2, if false, repeat
sequence

MOVE,
INT

72

S,r,s

Move (S) characters from r to s

5-73
5-115

MTH

07

m,i

(B2) - i. -+ B2, if (B2) negative, RNI @ P +
1; if (B2) positive, test (A) > (Q) A (M);
if true, RNI @ P + 2; if false,repeat sequence

5-74

Multiply (A) by (M) -QA; lowest order
bits of product in A

5- 62

MUA,I

50

m,b

MUAQ,I

56

m,b

Multiply (AQ) by (M,M + 1) -AQE

5- 63

MVBF

64

r,B r ,
S1, s,
B s ' S2
r, B r ,
h, s
B s ' S'2

Move characters from fld A - fld C; if
fld C > fld A, blank fill

5-125

Move characters from fld A - fld C according to parameters given

5-123

r, B r ,
s, B s '
S2
r, B r ,
S1, s,
Bs, S2

Move characters from fld A - fld C according to parameters given. Delimiting
character possibility

5-124

Move characters from fld A -fld C; if
fld C > fld A, zero fill

5-126

MVE

MVE.DC

MVZF

64

64

64

Instruction Tables - 17

I

5-50

Rev K

I

I

TABLE 2.

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Cont'd)

Mnemonic Basic Address
Code
Octal Field
Code

I

MVZS

64

MVZS,DC

I

OSA

64

77

OTAC,
INT

75

OTAW,
INT

76

OUTC,
INT,B,

75

ch
ch

ch, r, s

H

OUTW,
INT ,B,N
PAK
PAUS

I

PFA
PRP

76
66

w,2

77

I
QEL

55

QSE

04

QSE,S
QSG
QSG,S
~

______

Rev K

04
05
05
~k~

__

Page
No.

Move characters from fld A - fld C;
suppress leading zeros

5-127

Move character s from fld A -+ fld C; suppress leading zeros. Delimiting character
possibility

5-128

Clear A; OSR - AOO-02
OPERAND STATE REGISTER TO A

5- 37

Character from lower 6 bits of A is sent
to peripheral device ,(A) retained

5-106

Word from lower .12 bits or all of A
(depending on type of I/O channel) sent to
a peripheral device

5-107

Storage words disassembled into 6 or 12bit characters and sent to a peripheral device

5-99

ch, m,n Words read from storage to peripheral
device
r, Br ,SZ Pack 6-bit BCD fld A into 6-bit BCD
m, Bm fld C

77

77

Instruction Description

y
y

5-152

Sense busy lines. If "1" appears on a line
corresponding to "1" bits in x, do not advance P. If P is inhibited for longer than
40 ms, read reject instruction from P + 1.
If no comparison, RNI @ P + 2

5- 82

Clear A, page file index
PAGE FILE TO A

5-39

->-

AOO -11

Same as PAUS except real time clock
cannot increment during the pause
PRIORITY PAUSE

5-83

(Q) -EL

5-36

+ 2, otherwise RNI @
P + 1; lower 15 bits of Q are used

5-29

+ 2, otherwise RNI @
P + 1, sign of y is extended

5-29

If y = (Q), RNI @ P
If y = (Q), RNI @ P

y

If (Q) ?:y, RNI @ P

y

If (Q) ?:y, RNI @ P

.~

5-101

+ 2, otherwise RNI

@

+ 2, otherwise RNI

@

P + 1

5-30

P + 1, sign of y is extended

______· l -__________________________________

Instruction Tables - 18

5- 30
~

__

~

TABLE 2.

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Corlc'd)
Page
No.

Mnemonic Basic Address
Instruction Description
Code
Octal Field
Code
RAD,I
34
m,b
Add (M)to (A)-(M)

5-60

RIS

55

Use (ISR) in address relocation for operands
RELOCATE TO INSTRUCTION STATE
5-109

ROS

55

Use (OSR) in address relocation for operands. RELOCATE TO OPERAND STATE

5-109

P + 1 -+ M (address portion) RNI @ m + 1,
return to m for P + 1

5-47

RTJ

00

m

I

SACH

42

r,2

SBA,I

31

m,b

(AOO-05) - R
(A) minus (M)

SBAQ,I

33

m,b

(AQ) minus (M,M + 1) -AQ

5- 61

SBCD

77

Set BCD fault 10 gic

5-86

I

SBJP

77

Transfers system from Monitor State to
Program State when next jump instruction
is executed. SET BOUNDRY JUMP

5-109
5-156

I

5-54
-+

A

5-61

SBM

67

r, B r ,
Sl> s,
B s ' S2

Subtract fld A from fld C

SBR

70

m

Store (BCR) and BDP conditions at 'm' for
interrupt recovery

5-168

Where (M) contains a "1" bit, complement
the corresponding bit in A

5-70

Scans fld A from left to right, stop on =
condition. Delimiting character possibility

5-139

SCA, I

36

SCAN, LR,
EQ,DC

65

SCAN, LR
NE, DC

65

SCAN, RL,
EQ,DC

65

SCAN, RL,
NE, DC

65

SCAN, LR,
EQ

65

SCAN, LR,
NE

65

m,b

-+

fld C

r ,B r, S2 Scans fld A from left to right, stop on t
SC
condition. Delimiting character possibility

5-141

r, B r ,
S2, SC

Scans fld A from right to left, stop on =
condition. Delimiting character possibility

5-143

r, Br,
S2' SC

Scans fld A from right to left, stop on t
condition. Delimiting character possibility

5-145

r, Br,
S2, SC

Scans fld A from left to right, stop on =
condition

5-138

r, B r ,
§ 2, SC

Scans fld A from left to right, stop on
condition

Instruction Tables - 19

t
5-140

Rev K

TABLE 2.

,
I

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Cont'd)

Mnemonic Basic Address
Code
Octal Field
Code

Page
No.

SCAN,
RL.EQ

65

r, B r ,
52, SC

Scans fld A from right to left, stop on ==
condition

5- 142

SCAN,
RL,NE

65

r, B r ,
52, SC

Scans fld A from right to left, stop on::f=
condition

5-144

SCAQ

13

k, b

Shift (AQ) left end around until upper 2 bits
of A are unequal. Resigu~ K == k shif~ count.
If b == 1, 2, or 3, K ..... B ; If b == 0, K IS
5-59
discarded

SCHA,I

46

m,b

(AOO-16) ..... (MOO-16)

SCIM

77

x

Selectively clear Interrupt Mask Register for
each "1" bit in x. The corre sponding bit in
the mask register is set to "0".
5-85

SDL

77

Cause s next LDA instruction to:
1. (M) ..... A
2. Store 77777777 @ M
SET DESTRUCTIVE LOAD

I
SEL

I

Instruction De scription

SFPF
SHA

SHAQ

SHQ

Rev K

77

x,ch

77
12

13

12

k, b

k,b

5-5E

5-110'

If channel ch is busy, read reject instruction
from P + 1. If channel ch is not busy, a 12-

bit function code is sent on channel ch with
a function enable RNI @ P + 2

5-92

Set floating point fault logic

5-86

Shift ~). Shift count K==k + (Bb) (si~ns of k
and B extended). If bit 23 of K=="l' , shift
right; complement of lower 6 bits equals
shift magnitude. If bit 23 of K == II 0", shift
left; lower 6 bits equal shift magnitude.
Left shifts end around; right shifts end off

5-57

Shift (AQ) as one register. Shift count K == k

+ Bb (signs of k and Bb extended). If bit 23

k, b

of K == "1", shift right and complement of
lower 6 bits equals shift magnitude. If bit 23
of K == "0", shift left and lower 6 bits equal
shift magnitude. Left shifts end around;
right shifts end off

5-59

Shift ~Q), Shift count K==k + (Bb) (signs of k
and B extended). If bit 23 of K == "1", shift
right, complement of lower 6 bits equals
shift magnitude. If bit 23 of K == "0", shift
left, lower 6 bits e qual shift magnitude.
Left shifts end around; right shifts end off

5-59

Instruction Tables - 20

TABLE 2.

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Cont'd)

Mnemonic Basic Address
Octal Field
Code
Code

Instruction De scription

Page
No.

SJ1

00

m

If jump key 1 is set, jump to m

5-41

SJ2

00

m

If jump key 2 is set, jump to m

5-41

SJ3

00

m

If jump key 3 is set, jump to m

5-41

SJ4

00

m

If jump key 4 is set, jump to m

5-41

SJ5

00

m

If jump key 5 is set, jump to m

5-41

SJ6

00

m

If jump key 6 is set, jump to m

5-41

SLS

77

SQCH

43

r,l

(QOO-05) -R

5-55

SRCE,
INT

71

SC, r, s

Search for equality of scan character SC in
a field beginning at location r until an equal
character is found, or until characte r location s is reached.

5-111

Same as SRCE except search condition is
for inequality

5-113

Where (M) contains a "1" bit, set the corre sponding bit in A to "1"

5-70 i

Test sign of (m), shift (m) left one place,
end around and replace in storage. If sign
negative, RNI @ P + 2; otherwise RNI @
P+1

5-57

Selectively set interrupt mask register for
each" 1" bit in x. The corre sponding bit in
the mask register is set to "1"

5-85

SRCN,
INT

71

SSA,I

35

SSH

SSIM

10

77

Program stops if Selective Stop switch is on;
5-24
upon restarting RNI @ P + 1

SC,r,s
m,b
m

x

1

STA,I

40

m,b

(A) - (M)

5-53

STAQ,I

45

m,b

(AQ) ..... (M, M + 1)

5-54

STI,I

47

m,b

5-56

STQ,I

41

m,b

(Bb) - (MOO-14)
(Q) -(M)

SWA,I

44

m,b

5-56

TAl

53

b

TAM

53

v

TIA

53

b

(AO O- 14 ) ..... (M OO - 14 )
(A OO - 1 4) ..... B b
(A) -v
Clear (A), (B b ) ..... AOO-14
(B b ) ..... vOO - 1 4
(v) -A

5-35

Instruction Tables - 21

Rev K

TIM

53

v,b

TMA

53

v

5.,..55
5-33
5-34
5- 33
5-34

I
I

TABLE 2.

ALPHAMNEMONIC LISTING OF INSTRUCTIONS (Cont'd)

Mnemonic Basic Address
Code
Octal Field
Code
TMAV

Initiate memory request. If reply occurs
within 5 usec, RNI at P + 2; if not, RNI at
P + 1. Storage address is (B2) with (OSR)
or zero appended. TEST MEMORY
A V AILABILITY

77

TMI

53

TMQ

53

TQM

Instruction De scription

Page
No.

5-77
5-35

v

(vOO-14) - Bb
(v) ..... Q

53

v

(Q) - v

5-34

TST

67

TSTN
UCS

67
77

UJP, I
UPAK

01
66

XOA

16

r, B r , Test fld A, +, -, or 0
5-165
Sl
5-166
r, B r , Sl Test fld A for numeric
Unconditional stop. Upon restarting RNI @
5-24
P+1
5-41
m,b
Unconditional jump to M.
m,B m , Unpack 4- bit BCD fld A into 6- bit BCD
5-153
s, B s , S2 fld C
5- 69
Y V (A) -A,
Y

XOA,S

16

Y

XOI

16

y,b

Y V

XOQ

16

y

y v (Q) -Q

5- 69

XOQ,S

16

y

y v (Q)

5- 69

ZADM

67

r, B r ,
Sl, s,
B s , S2

Clear fld C; fld A - fld C, right justify

RevK

Y V (A)

A, sign of y extended
(Bb) _B b
-I'

->-

Q, sign of y extende d

Instruction Tables - 22

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5-34

5- 69
5- 69

5- 129

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INDEX

A register, 1-5
display, 7-1, 7-2
manual entry, 7-12
Access keyboard, 7-2, 7-9, 7-10
Accummulator, see A register
Active Digit indicator, 7 - 2
Adapt, 6-6, 6-8
Address modification, 5-6
examples, 5-9
Addressing, 2-5
character, 5-4, 5-5
conversion, 5-5
Direct, 5-7
Indirect, 5-8, 5-9
modes 2-4 2-5 5-7
relocation, ',8-3 '
word, 5-4, 5-5
see also Indexing, Address Modification
ALGOL, 6-3
Applications software, 6-6
Arithmetic,
BCD, 1-15
functions, 1- 15
interrupt, 4-2, 4-8
Overflow fault, 4- 2
Reference information, B-1
register, see A register
ASCII. 1-14
conversion table, A-3
Associated Processor interrupt, 4-3, 4-7, 4-8
Auto Dump, 3-7, 4-4
address protection, 2- 6
execution, 7 -16
switch description, 7-7
Auto Load, 3-7, 4-4
address protection, 2-6
execution, 7-16
switch description, 7-7

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B~ckgrl'JUnding,

6- 2
registers, 1-6, 5-6
display, 7-1, 7-2
BCD, t-15
conversion table, A-3
fault, 4-2
internal, external codes , A-I
word and character format, F-5
BCR, see Business Data Processor Condition register
Binary number system, B-1
Block cGmtrol, 1-9, 2-8, 7-19
priority, 1-10
s ca=ing pattern, 1-11
Breakpoint switch, 1- 9, 7-11
examples, 7-17, 7-18
Business Data Processor,
Condition register, 5- 3
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description, 1-4
instruction format, 5-6
instruction list, 1-13
Mode switch, 7-8
trapped instructions, 4-6
B

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Index-l

C register, 1-6
display, 7-1, 7-2
CR, see Condition register
Central Processor Unit (CPU), 1-3
internal organization, 1-5
operation in Executive Mode, 1- 9
module location, 1- 2
Channel, see Input/Output
Channel Index register, 1-7, 5-3
Character addressing, 5-4, 5-5
designators, 1-5
modes, 2-4, 2-5
set, A-I
crn, see Cha=el Index register
COBOL, 1-1, 6-3, 6-4
Coefficient, B- 8
COMPASS, 6-3, 6-4, 6-5
Condition register, 5-3
Co=ect, 3-4, 3-5, 5-90, 5-91
Console, 1-4, 7-1
Constants, C-4, C-5
Conversion tables,
BCD / ASCII, A - 3
Octal-Decimal Integer, C-6
Octal- Decimal Fraction, C-I0
Conversions,
address, 5-5
Fixed Point/Floating Point, B-13
procedure, B-5
DC, see delimiting character
Data,
bus, 1-8, 7-19, 7-22
Bus register, 1-8
entry, 7-2
Interchange Display, 7-4
processing, 1-3
Processing Package, 6-3, 6-5
Decimal/Binary position table, C-2
Decimal/Octal conversion,
procedures, B-5
table, C-6
Delimiting, 1- 4,
character, 5-2, 5-6
Divide fault, 4-2
interrupt code, 4-10
priority, 4-8
Division,
binary, B-4
Floating Point, B- 9
Double Precision Arithmetic, B-8

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E Bit, see Exclusion bit
E register, 1-6, 4-2, 7-10
Emergency Off switch, 7-1, 7-9, 7-12
Exclusion bit, 4-4, 8-10
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Executive Mode, 1-7
addressing, 2-5
description, 1- 9
interrupt, 4-1, 4-3

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Monitor State, 8-1, 8-6
Program State, 8 -1, 8-6
switch, 7-7
Exponent,
Fault, 4-2, 4-8, 4-10, B-13
floating point, B- 9

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Trapped, 5-11
Interface signals, 3-3, 7-8
parity, 1-13
Internal organization, 1-5
Interrupt,
clearing, 4-9
codes, 4-10
conditions, 4- 2
lines, 3-3
Mask register, 4-10, 4-11
priority, 4-8
processing, 4- 9, 4-10
sensing, 4-9
system information, 4-1

F register, 1-7, 1-9
display, 7-1, 7-2
Fixed Point Arithmetic, B-8
Floating Point,
arithmetic, B-9
fault, 4-2, 4-8, 4-10, B-13
module, 1-4
E register, 1- 6
FORTRAN, 6-3
Function, 3-4, 3-5, 5-92, 5-93
codes, see instruction

ISR, see Instruction State register
illegal Write, 2-5
indicator, 7-6
interrupt, 4-1, 4-4, 4-5, 4-6, 8-10
Indexing,
examples, 5-9
see address modification
Index registers, 1-6, 1-14, 5-2, 5-6, 5-7
Indirect Addres sing,
parameters, 5-1
also see addressing
Input / Output,
channels, 3-1, 3-4
disk, 6-2
interface signals, 3- 3
interrupts, 4-1, 4-3
modules, 1-3
parity, 1-12, 1-13, 3-4
software, 6-5
system description, 3-1, 3-2
Instruction State register, 1-7, 2-5
display, 7-1, 7-3
Instructions, 5-1
Arithmetic, 5- 60
BDP, 5-117
Character Search, 5-111
Condition Test, 5-77
Enter, 5-25
execution times, 5-19
B formats, 5-4, 5-6,
Halt and Stop, 5 - 2 4
Increase, 5- 27
I Input/Output, 5-87
Inter-Register Transfer, 5-32
I Interrupt, 5-84
Jump, 5-41
list (BDP), 1-13
Load, 5-49
Logical, 5-68
Masked Search and Compare, 5- 73
Move, 5-115
Multiprocessing Control, 5-110
No-Operation, 5-18
parameters, 5-1
Pause, 5-82
Relocation Control, 5- 109
Sensing, 5- 78
Shift and Scale, 5- 57
Skip, 5-28
Store, 5-53
synopsis and index, 5-12

Jump,
switches, 7-7
see instructions
Languages, 6-3, 6-4, 6-5
Last Jump Address switch, 7-8
Library tape, 6-1, 6-2
Loudspeaker, 7-12

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Rev. C

MCS, see storage
MSIO, 1-1, 6-6
MSOS, 6-1, 6-2
Main Control, 1-6, 2-8
Manual interrupt, 4-1
Mass Storage COBOL, 6-3, 6-4
Mass Storage SORT, 6-6, 6-7
MASTER, 1-1, 6-1, 6-2
Meters,
elapsed time, 7-24
storage control, 2 - 3
Modules, 1-2, 1-3, 2-5
Modulus, B-1
Monitor State, 1-9, 4-1, 4-4, 4-5, 8--1
indicator, 7-5
Multiplication,
binary, B-4
fixed point, B-8
floating point, B- 9
Multiprogramming, 1-1
module, 1-2, 1-4, 2-5, 8-1

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No-Operation instructions, 4-6, 5-18
Non-Executive Mode, 1-9, 2-5, 3-7, 4-4
description, 1- 9
trapped instructions, 4-5
Normalizing, B-13
Number Systems, B-1
OSR, see Operand State register
Octal arithmetic matrices, C-3
Octal number system, B- 2
Operand State register, 1-7
application, 8 -2, 8-4, 8-5
display, 7-3
Operating systems, 6-1, 6-2
Overflow fault, 4-2, B-13

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Index-2

P register, 1-6, 2-5
display, 7 -1, 7 - 2
PIF, see Page Index File
Page,
Index File, 8-7

Index registers, 8-7
Length (PL), 8-12
memory, 2-5, 8-3
Partial (PP), 8 -12
structure, 8-3
Zero, 8 -14
Parameters, see instructions
Parity, 1-12
Error indicator, 7-4, 7-6
Error interrupt, 4-1, 4-4, 4-5, 4-6
Error signal, 3-5
Interrupt switch, 7-7
I/O, 1-13, 3-4, 3-5, 3-6
storage, 1-12, 2-4
Stop switch, 7-7
Peripheral equipment, 1- 16
PERT, 6-6, 6-7
Power Control Panel, 1-5
Powerfail interrupt, 4-1, 4-7
Program,
Address Group, 8 - 3
protection, 2-7
State, see Monitor State

S register, 1-8, 2-1
SCOPE
Real-Time, 6-1, 6-2
Utility Routines, 6-1, 6-2
Search, 1-14
Search/Move interrupt, 4-3
codes, 4-10
priority, 4-8
SIPP, 6-6
Software, 6-1
SORT, 6-6
Stacked jobs, 6-2
Status, display, 7-1, 7-4
Storage, 2-1
access switches, 7-11
addressing, 2-5
Control panel, 2-2
modules, 1-3, 2-1
module photographs, 2-2, 2-3
parity, 1-12
parity error, 4- 4
protection, 2-5
registers, 1-8, 2-1
sharing, 2-8
word, 2-4
Switches, see console

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Q register, 1-5
display, 7 -1, 7 - 2

Time-Sharing, 1-1, 6- 2, 8-1
Trapped instructions, 4- 6, 5 -11
interrupts, 4-6, 4-7
Typewriter, 7-1, 7-19
codes, 7-23
control switches, 7-19, 7-21

REGINA-I, 6-6, 6-7
Radix, B-1
Read next instruction (RND, 5-11
Real-Time Clock, 1-10, 1-11, 1-12
interrupt, 4-3, 4-8, 4-10
Real-Time SCOPE, 6-1, 6-2
Register File, 7-19
Assignments, 1-10
breakpoint operation, 7-12, 7-17
description, 1- 9
Registers,
abbreviations, 5-3
des cription, 1- 5
Relocation, 2-5, S-7, 8-1
Report Generator, 6-3, 6-5
RESPOND /MSOS, 6- 6
Rounding, B-12

Underflow fault, 4-2, B-13
Word Addressing, see Addressing
Word format, 1-5
Write, 3-4, 3-5
Z register, 1-8, 2-1

S bus, 1-8, 2-5

Index-3

Rev_ F

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COMMENT SHEET
MANUAL TITLE

_C_O_N_T_R_O_L_D_A_T_A_3_3_0_0_C_O_M_P_U_T_E_R_S_Y_S_T_E_M
_ _ _ _ __

Reference Manual
PUBLICATION NO.

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NO POSTAGE STAMP NECESSARY IF MAILED IN U. S. A.
FOLD ON DOTTED LINES AND STAPLE

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ATTN: TECHNICAL PUBLICATIONS DEPT.
PLANT TWO

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QUICK REFERENCE INSTRUCTION
Instruction Category

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Applicable Pages

NO-OPERATION

5-19

HALT and STOP

5-24

ENTER

5-25 through 5-26

INCREASE

5-27

SKIP

5-28 through 5-31

INTER- REGISTER TRANSFER

5-32 through 5-40

JUMPS

5-41 through 5-48

LOAD

5- 49 through 5- 52

STORE

5- 53 through 5- 56

SHIFT and SCALE

5-57 through 5-59

ARITHMETIC

5-60 through 5-67

LOGICAL

5- 68 through 5- 72

SEARCH

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INDEX

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5-73, 5-74, and 5-111 through 5-114

COMPARE

5-73 through 5-76

TEST

5-77

SENSING

5-78 through 5-81

PJ1USE

5- 82 through 5- 83

INTERRUPT

5-84 through 5-86

INPUT / OUTPUT

5-87 through 5-108

RELOCATION CONTROL

5-109

MULTI-PROCESSING CONTROL

5-110

MOVE

5-115 through 5-116

BUSINESS DATA PROCESSING

5-117 through 5-168

ADDITION A L INSTR DC TION INFORMA TION
Instruction Parameters
Register and Function Abbreviations

5-1 through 5- 3

5- 3

Octal Instruction Listing

5-19
Instruction Tables 1 through 11

Alphamnemonic Instruction Li.sting

Instruction Tables 12 through 22

Execution Time Table

Trapped Instruction Listing

4-5

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CONTROL DATA
CORPORATION

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CORPORATE HEAOQUARTERS. 8100 34th AVE. SO .• MINNEAPOLIS. MINN. 55440
SALES OFFICES ANO SERVICE CENTERS IN MAJOR CITIES THROUGHOUT THE WORLD

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