60158800A_3300_Training_Manual_Volume_2_Aug68 60158800A 3300 Training Manual Volume 2 Aug68
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CONTROL DATA
EDUCATION INSTITUTES
SECOND EDITION
TRAINING MANUAL
Volume
n
3300 COMPUTER TRAINING MANUAL
SECOND EDITION
FOR TRAINING PURPOSES ONLY
This manual was compiled and written
by ins tructional personnel of
CONTROL DATA INSTITUTE
CONTROL DATA CORPORATION
Publication Number e0158800A
August, 1968
This manual obsoletes the 3300 Computer Training
Manual, Volumes II and III, Publication Number
60158800, Printed November, 1965.
Copyright 1968, Control Data Corporation
Printed in the United States of America.
CONTENTS
CHAPTER 4.
STORAGE . . . . . . . . . . . . . . .
Description and General Information
Storage Capacity . • . . .
3309 Storage Module. •
3302 Storage Module.
Storage Word Format . . .
Storage Parity . . . . . .
Storage Module Description
Storage Registers . .
Read/Write Controls .
Storage Module Control Panel.
Buss ing System.
. . . . •
S Bus . . . . • .
Data Bus . . . .
Storage Protection .
3309 Theory of Operation
Control Select
• . . . .
Scanner. . . . • . .
Delay Line . . . . • . .
Delay Line Timing.
Memory Planes and Wafers .
Memory Stack . . • . . . • .
Drive Lines . . . . . .
Stack Construction (Field 0, 4K).
Drive Compensator .
Inhibit Lines. . . . .
Inhibit Compensator. •
Sense Lines . . . . . .
S Register . . . . . . • .
Line Driver Selection .
Address Translation.
Drive Line Selection. •
0
67
67
67
67
67
68
68
70
70
70
70
71
71
74
74
74
76
76
78
78
79
80
82
82
84
84
84
85
85
85
87
91
iii
CONTENTS (continued)
1\
94
95
Storage Address Selection \Vorksheet.
Read/Write Storage . . . . . . . . • . . . .
Z Register and Read/Write Controls . .
Z Register . .
Read Control . . . . . • • . . . . . . .
Write Control. . . . • . . .
Read/Write Timing Worksheet.
Read Storage Timing . .
Write Storage Timing . . . . . •
Interface . . • • . . . . . . . . .
3300 Memory Power Supply
3302 Storage Module . . . .
Storage Worksheet #1 . . . . . .
Storage Worksheet #2 • . . . . .
Self-Evaluation Quiz on Chapter 4
109
110
112
112
114
118
122
CHAPTER 5.
MULTIPROGRAMM£NG MODULE . .
General Information. . . . .
Word-Organized Memories . .
Two Core Bits
Organization . . . . . . . . .
Stack . . . . . . . . . . . . .
Read and Write Drivers
Logic Translator
S Register . . . . . • . . .
Sense Amplifiers
Z Register . . . • .
Overall Selection
Timing . . . . . . .
Theory of Operation. .
Write Page Index . . .
Read Page Index. . . .
Illegal Storage Reference Detection . .
Read Page Index O.
Partial Page Adder
Storage Request . .
Special Cycle . . .
No Change . . . . .
Self-Evaluation Quiz on Chapter 5
123
125
125
126
128
128
132
133
133
133
134
134
135
142
142
142
144
145
145
146
146
146
146
CHAPTER 6.
LOGIC TIMING AND KEYBOARD ENTRY
Computer Timing . . . . . . . . .
Master Clock and Clock Pyramid.
Resynchronizing . .
Resync Counter
Start. . . .
Test Mode . . .
Static Controls.
Keyboard Entry Controls
Register Selection .
Entry of Data into C
Timing for 24-Bit Entry.
Timing for l!1-Bit Entry into B1, B2, B3, or P* . . . .
Ivlanual Entry Timing \Vorksheet . . . . .
147
147
147
148
148
148
149
150
150
152
153
153
156
158
96
96
96
96
108
109
CONTENTS (continued)
Manual Timing Chain. . . . . . . . .
Review of Transfer Sequence . .
Keyboard Entry Worksheet .•
Manual Read Storage. . • • . . . . . . . • . .
Manual Write Storage . . . • . . .
Questions on Manual Read/Write Operation.
Self-Evaluation Quiz on Chapter 6 . . . .
160
162
163
164
166
170
171
CHAPTER 7.
READ NEXT INSTRUCTION SEQUENCE
Four Major Functions
Detailed Timing
Entrance to RNI
Initiate RNI. • •
Update P • • • • .
Obtain Bus Priority . .
Address (8) Bus .
Reply from Storage. . . . • . •
Release Bus System . .
Breakpoint Stop .
Enable Data Bus to F Register. . .
Decode Instruction. . . . .
.... .
Interrupt Recognition
End RNI . .
Summary . . . . .
Review . . . . . .
RNI Worksheet.
Self-Evaluation Quiz on Chapter 7 . .
173
173
176
176
177
178
180
180
182
184
184
184
186
186
186
187
188
189
192
CHAPTER 8.
READ ADDRESS SEQUENCE • . .
Description. . . • . . . . . . .
Detailed Timing . . . . . . • .
Read Address Storage Reference
Read Address Sequence . . . . .
KOOO/001 (Request Bus FF) .
Reply from Storage. . . . . . . .
Release the Bus . . . . . . . . . .
Enable Data Bus to Lower F Register . .
Redecode Instruction.
End RADR . • . . . • • • • . . . .
Review . . . . . • • • • . . • • • .
Self-Evaluation Quiz on Chapter 8.
193
193
194
197
197
197
199
200
200
202
202
203
204
CHAPTER 9.
READ OPERAND SEQUENCE .
Introd.uction. . . . . . . . . . .
Detailed Timing . . . . . . . .
Start ROP; Request Bus System . .
Request Storage . . . .
Reply from Storage . . . . . . . . .
Release Bus System . . . . . . . •
Enable Data Bus to DBR and Start Arithmetic
Self- Evaluatio1J. Quiz on Chapter 9.
205
205
206
208
209
211
212
213
217
CHAPTER 10.
STORE OPERAND SEQUENCE . .
Introd.uction. . . • . . . . • . .
Detailed Timing . • . • . . . . .
Start STO; Request Bus System.
219
219
220
223
v
CONTENTS
vi
(co~tinued)
Request Storage and Start Arithmetic .
Start Arithmetic . . . . . . . .
Request Storage . . . . . . . . . . . . . .
Write Signal and Illegal Write. .
Write Designators . .
Word to Bus . . . . . . . . . . . . . .
Reply from Storage. . . . . . . . . .
Storage Reply Resync Circuit . . .
Release Bus System
End STO. . . . . . . . . . . . . . .
Review . . . . . . . . . . . . . . . . .
Self-Evalu:ltio:1 Quiz on Ch:lpter 10
223
223
225
226
226
228
230
230
231
231
232
234
CHAPTER 11.
SEQUENCE PROGRESSIONS . .
Sequences Worksheet.
Clues . . . . . . . . . . .
235
243
246
CHAPTER 12.
ARITHMETIC CONTROLS
General Description
Al Register
Q1 Register
A2 Register
Q2 Register
X Register . . .
Inverter Ranks .
Adder . . . . . . .
Binary Arithmetic
Theory of the Adder
Stage-Generated Signals.
Gro'.lp-Gen.erated Signals
Multiple-Gro'.lp Pass an:l Carry Generation . .
End-Aro:md Carry.
Group Carry Inp·.lts . . . . .
Stage Carry Inp·lts . • . • . .
Generation of Fimil. OutP'.lts .
Adder Worksheet . . • .
Double-Precision EAC
Logical Product . . .
Arithmetic Controls .
F2 Register . . . . . .
Address Modification (F ADR) . . . • .
Op9rations in the Arithmetic Section . .
Jump and Skip Instructions (02-05; 10.1-10.7)
A, Q, Bb Jumps and Skips (03-05). . . • . .
Incremental/Decremental Index Jumps and Skips
(02.1-02.3; 02.5-02.7; 10.1-10.7) . . .
Copy Instrllctio'ls (77.2 ch 000; 77.3 ch 000)
Single-Precision Interregister Transfer (53)
Storage Shift (10.0) . . . . . .
Enter Ins tructions (11, i4). .
LDA (20) Instruction. . .
LACH (22) Instruction.
LCA (24) Instruction . .
LDAQ (2;:») Tnstrl1ctio'1 .
LCAQ (26) Instruction . .
LUL (~7) InstrlJction . . . .
249
249
250
250
250
251
252
252
252
253
253
253
254
254
255
255
255
255
256
257
257
258
258
259
261
262
262
262
263
263
264
265
265
265
265
265
265
265
CONTENTS (continued)
CHAPTER 13.
LDQ (21) Instructio'J.. .
LDCH (23) Instruction.
LDI (54) Instrllctio'J. . .
ST A (40) Instrllction . .
SACH (42) Instruction
SW A (44) Instruction. .
SCHA (46) Instruction
STAQ (45) Instruction .
STQ (41) Instruction ..
SQCH (43) Instruction .
STI (47) Instruction . .
Ari thmetic Ins tructions. . .
. . . . .
ADA (30) Instruction. .
. ..... .
SBA (31) Instructio'J.. .
. ......•.
ADAQ (32) Instrllction .
. ......... .
SBAQ (33) Instrllction .
. ...••.
Static Enables and Timed Transfers Worksheet #1
Static Enables and Timed Transfers Worksheet #2
Static Enables and Timed Transfers Worksheet #3
Static Enables and Timed Transfers Worksheet #4
Static Enables and Timed Transfers Worksheet #5 .
Static Enables and Timed Transfers Worksheet #6
Static Enables a'J.d Timed Transfers Worksheet #7
Static Enables and Timed Transfers Worksheet #8
CPR Compare (within Lim,its Test)
..... .
MEQ Masked Equality Search.
. ........... .
MTH Masked Threshold Search . .
Shift Instruction. . . . . . . . . . .
Timing for Shift Instructions . . . . . . . . . . . . . .
Single-Precision Multiply . .
Timing for Multiply A Instruction. .
Complement and/or Swap. . . . . . . .
. . . . .
• .'
Swap Cycle. . . . . . . . . . . . . . .
. .......•.
Comparison of Main CO'J.trol and Arithmetic~ Timing
Multipfy Timing Worksheet. . . . . . . .
Single-Precision Divide . • . • • • . • . •
Timing for the Divide A Instruction . .
General Arithmetic Timing for Divide
Self-Evaluation Quiz on Chapter 12 . . . .
267
267
267
267
267
267
267
267
267
267
267
272
272
272
272
273
274
274
275
275
276
276
277
277
278
279
279
284
285
287
289
291
291
292
292
293
296
297
298
FLOATING POINT/DOUBLE PRECISION OPTION
Enabling the 4S-Bit Adder • • .
DO'J.ble-Precision Multiply . . .
Instruction Description . . . . .
Six-Bit Example for Multiply . .
Detailed Timing . . . . . . . . .
Detailed Timing for Initialize
FADR . . . . . . • •
Multiply Step . . . . . . • .
Complement Step . . . . . .
Double-Precision Divide .•
Instruction Descriptio'J.
Six-Bit Example for Divide.
Detailed Timing . . . . . . . .
Detailed Timing for Initialize .
299
299
302
302
302
303
303
303
307
307
308
308
308
309
309
vii
CONT ENTS (continued)
CHAPTER 14.
viii
FADR . . . . .
Divide Step . .
Complement.
Floating-Point Multiply.
Instruction Description
Detailed Timing. . . . . . . . .
Phase 1 . . . . . . . . . .
Phase 2: First Arithmetic Pass. .
Phase 2: Second Arithmetic Pass.
Phase 3: Initialize. . .
Phase 3: Multiply Step. . . .
Round . . . . . . . . . . . . .
Adder Output from Round .
Floating-Point Divide . . . .
Instruction Description
Detailed Timing . . . . . . . . . . . . . .
Phase 1 . . . . . . . .
Phase 2: First Arithmetic Pass. . . .
Phase 2: Second Arithmetic Pass.
Phase 3: Initialize. . . . . . .
Divide Step . . . . . . . . . . . . .
Swap AQ and E: First Pass . . .
Swap AQ and E: Second Pass
Round . . . . . . . . . . . . . .
Floating-Point Add . . . . . . .
Instruction Description
Detailed Timing . . . . . . .
Phase 1 . . . . . . . .
Phase 2: First Arithmetic Pass . .
Phase 2: Second Arithmetic Pass.
Phase 3: Initialize. . . . . . .
Phase 3: Equalize Exponents
Phase 3: Add Coefficients.
Phase 3: Round . . . .
Floating-Point Subtraction.
Instruction Description
Detailed Timing . . . . . .
Phase 1 . . . . . . . .
Phase 2: First Arithmetic Pass.
Phase 2: Second Arithmetic Pass.
Phase 3: Initialize. . . . . . . .
Phase 3: Equalize Exponents . .
. . • . • .
Phase 3: Subtract Coefficients . . . . .
Phase 3: Round . . . . . • . . . .
Phase 3: Common Timing: Normalize
Phase 3: Adjust Exponent .
Phase 3: Merge . . . . .
Phase 3: Complement. . . .
Problems . .
Self-EvaluaLiou Quiz Oil Chapter 13
311
313
315
315
315
316
316
316
319
319
320
321
321
322
322
323
323
323
325
325
326
327
329
329
329
329
330
330
332
334
334
335
335
336
337
337
339
339
339
341
342
342
343
344
344
346
346
347
347
INTERRUPT . . . .
General Description
Types . . . . . . . .
Abnormal Interrupts
349
349
349
348
34D
CONTENTS (continued)
Normal Interrupts . . . . . .
Trapped Instruction Interrupt . . . . . . . . . .
Abnormal Interrupt Sequence. .
Interrupt on Storage Parity or Storage Not Available.
Illegal Storage Reference Interrupt . .
Power Fail Interrupt . . . . . . . . . .
Abnormal Interrupt Sequence Timing
Normal Interrupt Sequence. . . .
Executive Interrupt. . . . . . . .
Optional Arithmetic Interrupts. .
Floating-Point Fault . . . . . •
BCD Fault . . . . . . . . . .
Interrupt Adj acent Processor
Internal Interrupts . .
External Interrupts. . . . . .
Interrupt Selection . . . . . . .
Normal Interrupt Sequence Timing. . .
Trapped Instruction Interrupt . . . . .
Trap Sequence Timing .
Interrupt Sensing . . . . . . . . .
Pause Instruction. .
Clearing Interrupt .
Interrupt Worksheet
Self-Evaluation Quiz on Chapter 14
350
350
350
350
350
350
351
352
353
353
353
353
353
353
354
354
357
358
359
360
360
361
362
363
CHAPTER 15.
BLOCK CONTROL . . . . . . . . .
Registers. . . . . . . . • . . . . .
. ..•.
CIR (3-Bit Channel Index Register) . .
SO, Sl (6-Bit Double Rank Register)
S2 (20-Bit Current Address Register). . .
Zl (27-Bit Register) . .
Z 0 (24-Bit Register). .
Block Operations . .
Requests
Priority . .
Timing . .
Busy . .
Block Operations . . . . . . .
Input/ Output . . .
I/O Operations with Storage.
I/O Operations with A
Typewriter . . . . . . .
Timing . . . . . . . . .
I/O Word Modification . .
Block Control Worksheet . .
Timing Charts . . . . . . .
. . . • •
. . . • .
Timing for Activate Search or Move Buffer (71 or 72 Instructions). .
Self-Evaluation Quiz on Chapter 15 . . . . . . • . . .
365
366
366
366
366
366
366
366
367
367
368
368
368
369
369
371
371
371
380
381
382
384
386
CHAPTER 16.
COMMUNICATION MODULES .
General Description . . . . . .
3306 Communications Channel .
Functional Description.
Operation . . . . . . . .
Programming. . . .
Theory of Operation
Data Paths . . . . .
387
387
388
388
388
388
389
389
ix
CONTENTS (continued)
Theory of Operation . . . . . . . . .
Connect or Function Operation . . . • .
Write Operation . . . . . . • . . .
Output Buffer Cycle. . . . • . . . • .
Block Control Services A Request.
Operation Complete . • • . • . • .
Reply from External Equipment. .
Read Operation
Word Count Control. • • • • • •
Status Operation . . . .
Status Checking. . . .
Internal Status . •
External Status.
Parity Checking . .
Connect, Function, and Write . .
Read . . . . . . • • • •
Interrupts. . . . . . . . . . • •
External I/O Interrupts .
I/O Channel Interrupts.
Clearing Circuits . . • . . . •
Input/Output Channels Worksheet #1.
Input/Output Channels Worksheet #2.
Theory of Operation for 3307 Communication Channel
3307 Timing for Write No Assembly/Disassembly: Instructions (75)
(H = 0+1) or (76) (N = 1) . .
Activate I/O Operation. . • • . . . . . . •
Buffer Cycle . . . • . .
If Operation Complete . . .
If Operation Complete . .
General Flow for a 3-Word Output on a 76 (24 to 12) Disassembly
(Forward) . . . . . . . . • . . . . . . . . . • • . . . . . . . . . • .
3307 Timing for Write Disassembly: Instruction (76) (N = 0) Forward •.
Activate I/O Operation
Buffer Cycle . .
First Reply. . .
Second Reply. . .
Buffer Cycle . •
Third Reply • . .
Buffer Cycle . .
Fourth Reply. . .
Fifth Reply. . •
Sixth Reply. • .
. • . . •
3307 Timing for Read No Assembly/Disassembly: Instructions (73)
(H = 0 + 1) or (74) (N = 1) • •
• ••••
Activate I/O Operation.
. ....
First Reply . .
Buffer Cycle .
Second Reply. .
Buffer Cycle .
Operation Complete Signal.
No Operation Compiete Signal. .
Number 1 . . . . • • . . . . . . .
Number 2 . . . . • • . . . . .
Read and 12 to 24 Assembly Forward .
Self-Evaluation Quiz on Chapter 16 •.
x
APPENDIX A.
ANSWERS TO QUESTIONS IN VOLUl\IE II
391
391
396
398
398
400
400
401
404
404
406
406
406
406
407
408
408
409
409
409
411
411
412
412
412
412
412
412
413
413
413
413
414
414
414
414
414
415
415
415
415
415
416
416
416
416
416
41G
417
417
417
4~4
A-I
ILLUSTRATIONS
Title
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
3309 Storage Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3302 Storage Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8K Storage Module Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16K Storage Module Control Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use of Control Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8K Storage Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . .
Bus Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function of S-Bus Bits when Referencing 3302 . . . . . . . . . . . . . . . . . . . . . .
Function of S-Bus Bits when Referencing 3309 . . . . . . . . . . . . . . . . . . . . . .
S-Bus Scheme if Multiprogramming Module Present . . . . . . . . . . . . . . . . . .
S-Bus Scheme if Multiprogramming Module Not Present . . . . . . . . . . . . . . .
System Power Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Reference Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Select Switch and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Left and Right Address Bus to S-Control Logic . . . . . . . . . . . . . . . . . . . . .
S-Register Input Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Generator, Activate Read, and Gate Logic • . . . . . . . . . . . . . . . . . . .
Busy FF and Left Address Bus to S-Control Logic • . . . . . . . . . . . . . . . . . .
3309 Master Clear Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .
8K Memory Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .
Memory Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
X-Drive Line Configuration (Front View) • . . . . . . . . . . . . . . . . . . . . . . . .
Y -Drive Line Configuration (Rear View) . . . . . . . . . . . . . . . . . . . . . . . . .
Even Memory Core Array, Field 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Even Memory Core Array, Field 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Wafer - Inhibit Stripes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified Sense Quadrant . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . .
Storage Address Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
X Gates and Transformer Drivers . . . . . . . . . . • . . . . . . . . . . . . . . . . . .
Page
68
69
69
70
71
71
72
72
73
73
73
74
75
76
76
77
78
79
79
79
80
80
81
81
83
83
84
85
86
86
xi
ILLusTRATIONS (continued)
Figure
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
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120
121
122
123
124
125
126
127
~nn
.L'::;C
129
130
131
132
133
;~1J.
Title
Transformer Card with Pin Numbers . . .
X Drive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . . ..
Y Drive Line . . . . . . . . . . .
Y Gates . . . . . . . . . . . . . .
Field Selection . . . . . . . . . .
Y Transformer Drivers . . . .
Drive Line Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . .
Simplified Gate and Transformer Circuits. . . . . . . . . . . . . . . . . . . . . . . . .
Drive Transformer Operation for Read. . . . . . . . . . . . . . . . . . . . . . . . . . .
Drive Transformer Operation for Write . . . . . . . . . . . . . . . . . . . . . . . . . .
K760/761 FF . . . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . .
Delay Line Time B4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . .
Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z-Register Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • . . .
Delay Line Time B6 . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . .
Strobe-Shaper Network . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . .
Delay Line Time B7 . . . . . . . . . . . • . . . . • . . . . . . . . . • . . . . • . . . . . . •
Partial Write Bits . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . .
Possible Methods for Setting the Z Register . . . . . . . . . . . . . . . . . . . . . . •
Delay Line Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Line Times . . . . . . . . . . . . . . . • . . . . . . • . . . . . . . . . • . . . . • . . .
Inhibit Scheme for Bits 2 and 3 in Detail. . . . . . . . . • . . . . . . . . . • . . . . .•
Inhibit Selection Logic. . . . . . • . . . . . • . . . . . . . . . . . • . • . . • . . . . . . ..
Partial Listing of Inhibit Line Selection .. . . . . . . • . . . . . . . . . • . . . . . ..
Parity Bit Inhibit Selection. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . • . •.
Dummy Load Enables . . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . . • .
Write Cycle Turn On . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . ..
Parity Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • • . .•
Circuitry Showing Method Used to Determine if a Parity Bit must be Stored ..
Write Designator Bit Clear Enable. . . . . . . . . . . . . . • . . . . . . . . . . . . . ..
Data Bus Transmitters Off . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .•
Data Bus Transmitter Enables . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . .
Clear Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • .
Clear "s" Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver Discharge Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver Discharge Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . •.
Busy Clear Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • •
Storage Reference Timing . . . . . . . . . . . • . . . . . . • . . • . . . • • . • . . . . • .
8K Memory Module Flexprint Assignments . . . . . . . . . . . . . . . . . . . . . . .•
Additional 3300 Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
16K Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . • . ..
Troubleshooting Flow Chart =In • . • . . • . . • • • . • . • • . • • • • . • . • • . . . . •.
Troubleshooting Flow Chart #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3311 Multiprogramming Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Inqex File Block Diagram . . . . . . . . . . . . . . . . . . . . . • . • . . . . . . .
3300 Physical Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . ..
Word-Organized Memory Matrix. . . . . . . . . . . . . . . . . . . . . . . . • . . . . .•
Matrix of Two-Core Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
,!'wo-Core Bits· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Close-Up of Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register File Block Diagram
. . . . . . . . . . • . . . . . . •.
\Vo1'<:1 Line \Viring . . . . . . . . . . . . . . . • . . • . • . . • . .
87
88
89
90
90
91
92
92
93
93
95
95
95
96
96
96
96
97
98
99
99
100
101
101
101
102
102
102
103
104
104
105
105
106
106
106
107
110
111
112
113
117
121
123
124
125
125
127
127
128
128
129
129
ILLUSTRATIONS (continued)
Figure
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
Title
Digit and Sense Line Wiring • . . . . . . . . . . . • . . . . . . . . . . . . . . • . . • .
Word Line Selection . . . . . . . . . . . • . . . . . . . . . • . . . . . . . . . • . . . . .
Logic Representation of Drive Line Selection . • . . . . • . . . . . . • . • . . • .
Gate and Driver. . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . . . . . . • . . .
Logic Translator (Section) . . . . • . . • . • . . • . . . . . . . . . • . . . . . . . . . •
Sense Amplifier . . . . . . . . . . • . . . . . . . . . . . . • . . . . • . • . . • . . . . •
Digit Driver . . . . . . . . • . . . . . . . • . . . . . . • . . • . . . . • . . . . • . . . . •
Timing Figure . . . . . . . . . . . . . . . . • . . . . . . . • . • . . . . . . • • . . . . •
Page Index File Assembly and Designations . . . . • . . . . . . . . . . . . . . . .
Register File Operation Example . . . . • . . • . . . . • . . . . . . . . . . . . . . .
Read Board Schematic Type 24419200 . . • . . . . . . . . . • . • . . • . • . . . . .
Write Board Schematic Type 24419500 . . • . . . . . . • . . • . • . . . . . . . • .
Register File Test Points . . . . . . . . . . . . . . . . • . . . . • . . . . . . . . . • .
Logic Translator Schematic Type 24418700 . • . . . . . . . . . . . . . . • . . . .
Diode Matrix Schematic Type 24418900 . . . . . . . . . . . . . • . . . . . . . • . .
Data and Control Signal Transmissions for Write Page File . • . . . . . . . .
Address Flow for Executive Mode . . . . . . . . • . . . . . . . . . . . . . . • . . . .
liZ Even" Illegal Write Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . .
E Bit nlegal Write Test . . . . . . . . • . . . . . . . . . • . . . . • . . • . . . . . . •
Z Even Page Length Test . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . ..
Page Index Zero Test . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . • . .
Partial Page Adder Addition Chart . . . . . . . . . . . . . . . . . . . . . . • . . . .
Special Cycle Bit 24 Test . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . • . .
Resync . . . . . . . . .
Resync Input
Resync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Go Logic . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . • . . . . . . . • . . . .
Time 2 of Resync Timing .. . . . . . . . . • . . . . . . . • . . . . . . . . . • . . • .
Digit Counter . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • . . . .
C Register Enables . . . . . • . . . . . . . • . . . . . . . . . • . . . . • . • . . . . • .
C Register Digit Enables . . • . • . . • . . . . . . • . . • . . . . • . . . . • . . • . •
Digit Sequence . . • . . . . • . . . . . . . • . . . . • . . . . . . • . . . . • . . . . . . •
Sequence Counter . • . . . . • . . . . • . . . . • . . . . • . . . . • . • . . . . . . . ••
Last Digit Logic . . . . . . . . . . . . . . . . . . • . . . . • . . . . • . . • . • . . • . •
12- or 15-Bit Override Logic . . . • . . . . • . . . . • . • . . . . . . . • . • . . • •
Manual Entry into A . . . . • . • . . • . . . . . . . . . . . . . . . . • . . . . . • • .
C Register Display for Digit 7 . . . • . . • . . . . . . • . . . . • . . • . • . • • . • .
Keyboard . • . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . • . . • . • . . . . .
Register Selection Logic . . . • . • . . • . • . . • . . . . • . • . . • . • . . . . • . . .
Waveform Timing for 24-Bit Entry . . • . • • . • . . . . • . . • . • . . . . • . . . .
Waveform Timing for 15-Bit Entry . • . • . . • . • . . • . • . . • . • . . • . • . . •
Transfer Logic . . . . . . . . . . . • . . . . . . . • . • . . • . • . . • . • • . • . . ..•
Keyboard Bus Priority . . . . . . . . • . . . . . . . . . • . . • . • • . . . . . . • . • •
C Register Enables. . . . . . . • . . • . • . • • . • . . • . • . • • . • . • • . • . . •.•
DBR Enables . . . . . . . . . • . • . . • . • . . . . . . • • . • . • • . . . • • . • . . • .
AQ Entry Logic . . . . . • . . • . • • . . . • • . • . • . . • . • • . • . • • • • . • . . • •
Manual Timing Chain . . . . . . • . . . . . . . . . • . . . . . . . . . • . . . . • . • . •
B Register Entry Logic . • • . • . . . . . . • . . • . • . . • . • . • . . • . • • . • . .
B Register Enables. . . . . • . . • . • . • . . • . • . . • . • . . . . • . . • . • . . • . •
P Register Entry Logic. . . . . . . .•.•.••.•.••.•.••••.•.••.•••
P Register Enables. . • . . . . • . . • . • . . • . • . . • . • . • • . • . . • . • . . • . •
Sweep Page Index File . . . . • . . . • • . • . . • . • • . • . • . • • . • . • • . • . • .
Data Flow Path • . . • . • . • • . • . . • . • . . • . • . • • . • . • • . • . • •.•.•.•
3300 Address Flow . . • . • • . • • • • . • • • • . • . • • . • . • • . • . • . . • . • • . .
Page
130
131
131
132
133
134
134
134
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136
137
138
139
140
141
142
143
144
144
145
145
145
146
148
148
148
149
149
150
150
151
151
152
152
152
152
152
153
153
155
158
159
159
159
160
160
160
161
161
161
162
169
174
175
xiii
ILLUSTRATIONS (continued)
Figure
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
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214
215
216
217
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220
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223
224
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229
230
231
232
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238
239
240
241
xiv
Title
Flow Chart . . . . . . • . . . . • .
Major Timing of RNI Sequence. • . . . . . . . . . . . . • . . . . • . . . . • . . . . .
Entry to RNI Sequence . . • . • . . . . . . . . . • . . . . • . . . . . . . . . • . • . . .
Initiate RNI Logic. . . . • . . • . • . . • . . . . • . • • . • . • . . • . • . • • • • • . . .
Update P (+1, +2) Logic . • . . . . • . . . . • . . . . . . • . . . . • . . . . . . . . . .
Jump Logic. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . . . . . .
Bus Priority Logic. . . . . . . . . . . . . . . . • . . . . . . . . . • . . . . . . . . . . .
Address Transmission Logic. . . • . . . . • . . . . . . . . . • . . . . . . . • . . . .
Storage Request Logic .•. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Breakpoint Logic . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . .
Resync Logic . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • . . . .
Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release Bus System . . • . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . .
F1 to F2 Logic . • . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .
Instruction Data Path. . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . •
Data Flow for RNI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
Decode Instruction and Sense Interrupt . . • . . . . . . . . . . . . . . . . . . . . .
Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . .
End RNI . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .
RNI Big Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indirect Addressing Routine. . . . . . . . . . • . . • . . . . • . . . . . . . . . . . . .
Data Flow for RADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3300 Address Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flow Chart of RADR Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Major Timing of RADR Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Transmission for RADR . • . . . . . . . . . . . . . . • . . . . • . . . . . .
Bus Priority Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Request Logic . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • . •
Reply Resync Logic . . . . . . . . . . . • . . . . . . . . . • . . . . • . . . . . . . . . •
Clear Bus Request . . . . • . . . . . . . • . • . . . . • . . . . . . . . . . . . • . • . . •
F Register Enables . • . . . . • . . . . . . • . . • . . . . • . . . . • . . • . • . . • . •
V008 Time . . . . . . . . . . • . . . . . . . • . • . . • . • . . . . • . . • . . . . . . . . .
RADR Data Path ".. . • . . . . . . . • . . . . . . • . . . . • . . • . . . . • . • . . • .
Data Transmission for RADR. • . . • . • . • . . • . • . . • . • • . • . • . . . . • . .
End RADR:' Time . . • . . . . • . . . . • . . . . . . . . . . . . . . . . • . . • . . . . . .
Sequence Controls Advance . • . . • . • . . • . . . . • . • • . • . • • . • . . . . • . .
RADR Big Picture . . . . . • . . . . • . . . . • . • . . . . • . . • . • . . . . • • . • . .
Data and Address Flow. • . • . . . . . . . . . . . . • . . . . . . . . . . . . . . • . . .
3300 Address Flow. . . . . . . . • . . . . . . . . . . . • . . . . . . . . . . . . . . • . .
Flow Chart of ROP Sequence . • . . . . . . . • . . . . . . . . . . . • . . • . . . . • .
Major Timing of ROP Sequence . . • . . . . . . . . . . . . . . . . . . . • . . . . . .
Sequence Progression from End of RADR . . . . . . . • . . . . • . • . . . . • . .
Bus Priority . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .
Address Flow . . . . . . . . . . . . . . . . . . . . • . . . . . . . • . • . . . . . . . . . .
Storage Request . . • . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . • . . .
Breakpoint Tests . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . • . .
Reply Resync Logic . . • . . . . . . . . . • . . . . . . . . . . . • . . • . . . . • . . . .
Breakpoint Tcsts Stop. . . . . . . . . . . . . . . . . . . . . . . _ _ , , , . , , , , , . ,
DBR Enables, . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . .
Receiver to DBR Circuits Showing Possible Shifts. . . . . . . . . . . . . . . . .
DBR Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
Data Flow for ROP. . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
Start Arithmetic on ROP • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . , ,
176
177
177
178
179
179
180
181
181
182
183
183
184
185
185
185
186
187
187
188
194
195
196
197
197
198
199
199
199
200
201
201
201
202
202
203
204
206
207
208
208
209
209
210
211
211
211
212
212
213
214
215
215
ILLUSTRATIONS (continued)
Title
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
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277
278
279
280
281
282
283
284
285
286
287
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289
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291
292
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Page
End ROP Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... .
ROP Big Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
Detailed Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3300 Address Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flow Chart of STO Sequence . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Major Timing of STO Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STO Sequence Initiation • . • . . . . . . . . . • . • . . • . . . . • . . . . • . . . . • . .
Arithmetic Start on STO . • . . . . • . . . . • . • . . . . . . . • . • . . . . • . . • . •
Address Transmission for STO . . . . . . . . . . • . . . . . . . . . . . . . . • . . .
Storage Request on STO . . • . . . . . . . • . • . . . . . . . . . . . . . . . . . . . • •
Write Signal Path . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
Partial Write Bit Transmission . . • . • . . . . . . • . . • . . . . . . . . . . . • . .
Breakpoint and Illegal Write Test . • . . . . • . . . . . . . • . • . . . . . . . . . . .
DBR Transfers . . • . . . . . . . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . •
Operand Transmission for STO Sequence . • . • . . . . • . • • . • . . . . • . • . .
Data Transmission for STO . . . . . . . • . • . . . . • . • . . • . . . . • . • . . . . •
Storage Reply Resync Circuit . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .
Breakpoint Stop Logic . • . . . . • . . . . . . . . . . . . . . • . . . . . . . . . . . • .
Release the Bus System . . . . . . . . . . . . • . . . . . . . . . . . . • . . . . . . . .
End STO Timing . . . . . . . • . . . . . . . . • • . . . . . . • . . . . . . . . . • . . . .
STO Big Picture . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . • . • . . .
Block Diagram of Sequence Progressions . . • . • . • . . • . . . . • . • . . . . •
Example of Bus System Usage • . • . . . . . . . . . • . . . . . . • • . . . . • . • . .
3300 Block Diagram . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . . • .
System Block Diagram • . . . . . . . . . . . • . . . . . . . • . . . . • . . . . •.•..
Arithmetic Inputs and Outputs . . . . . . . . • . . . . . . . . . . . . . . • . . . . . •
Standard Arithmetic . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . . . . . • .
Adder Pyramid . • . . . . . . . . . • . . . . • . • . . • . . . . • . • . . . . • . '•..•.
Logic for End-Around Carry . . . • . . . . . . . • . . . . . . • . . . . . . . • . • . .
Logical Product Generation • . . . . . . • . . • . . . . . . . . . . . . . . • . . . . • .
Selective Complement Generation . . . . . . • . . . . . . . • . • • . • . . . . . . . •
Fl to F2 Logic . . . . . . . . . . • . . • . • . . • . • . . • . • . . . . • . . • . • . . . .
F 1 to F2 Duplication . . . • . • . . • . • . . . . • . . • . • . . • . • . . . . • . • • . •
Arithmetic Timing Chain (Simplified). • . • . • . . • . • . . • . • . . • . • • . • . •
KI00/I0l or KI04/105 Set . . . • . • • . • . • • . • . • . . • . • . . • . • • . • . • . •
Flow Path for FADR . • . • . • . . . . . . . • . • . . • . • . . • . • • . . . . . . • . • •
Load Instructions, Sequences, and Data Paths. . • • . • . • • . • . . •.•.•.•
Store Instructions, Sequences, and Data Paths • . • . • . . . . • • . • . . . . •.
CPR Compare . . . • . • . • • . . . . • . • . • . . . . • • .
Flow Chart for CPR Compare .••.•. • . . . . • . • . . . . • • . • • . • . • . . •
MEQ . . . . . . . . . . . . . . • . • . . . . . . . . . • . . • . . . . • . • . • • . • . . • . .
MTH • . . • . . • . • . . . . • . • • . • . . • . . . . • . • . • • . • • • • • • • • • . • . • .
Flow Charts for 06 and 07 Instructions . • . . . . • . • . . • . • . . • . • • . • . .
Data Path for Forming Shift Count . . . • . • • . • . • . • • . • . • • • • . . • . • •
Shifting Paths for A . . • . . . . • . • . . • . . . . • . • • . • . • . . . . • . • . . • . •
Shifting Paths for Q . • • . • . . . . . . • . . • . • • . • . • • • • . • . • • . • • • • . •
Flow Charts for Multiply A . . • . • . . . . . . . • . • . . • . • . . • . • . . • . . . .
Data Flow for Multiply Step . . . • . • . . . . • . • . . . . • . . • . • • . • . . . • • .
Short Cycle Timing . . . . . • . . . . . . • . • . . • . . • . • . • . . • . • • . • . • • • •
Data Flow for Complement Cycle . . • . • . . • . • . . • . • . • • . . • . • . . . • •
Data Flow for Swap Cycle . . • . . • . • . . • . . . . • . • . . • . • . . • . • . . • • •
Divide Flow Charts . . . . • . • . • • . • . . • . • . • • • • . • • • • . • • • . . • . • • •
Data Flow for Initialization . • . . • . • . . . . • . . • . • • . . . • . •
Data Flow for Divide Step • . . . . . . • . • . . • . • . . • . . . . . . • . . • .•.••
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xv
ILLUSTRATIONS (continued)
Title
Figure
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I1.A!")
tJ':ttJ
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AV L
Path for Quotient Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Physical Location of the FP/DP Option . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram of Arithmetic Section with Floating POint/Double Precision
Option Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Enabling the 48-Bit Adder . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . .
Operand Format for Double-Precision Multiply . . . . . . . . . . . . . . . . . . .
Flow Chart for Double-Precision Multiply . . . . . . . . . . . . . . . . . . . . . . .
Graphic Representation of Parallel Timing for 56. X . . . . . . . . . . . . . . . .
Data Flow for Initialize Multiplier to E 1 . . . . . . . . . . . . . . . . . . . . . . . .
AQ Negative (Positive Form of Multiplicand to A1Q1) . . . . . . . . . . . . . . .
Multiplicand to X2X1 . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .
Enables for Multiply Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operand Format for Double-Precision Divide . . . . . . . . . . . . . . . . . . . .
Flow Chart for Double-Precision Divide . . . . . . . . . . . . . . . . . . • . • . . •
Parallel Timing for 57. X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divisor to X2X1. . . . . .
Complement AQE . . . . . .
Enables for Divide Step .
Quotient Bit Translations
Operand Format for Floating-Point Multiply . . . . . . . . . . . . . . . . . . . . .
Pencil and Paper Example of Floating-Point Multiplication
Parallel Timing for 62. X . . . . . . . . .
Enabling the II-Bit Adder . . . . . . . . .
Enables for Add Exponents . . . . . . . . .
(AQE) After Multiply Step . • . . . . . . . . . . . .
Enables for Round . . . . . . . . . .
Plus 1 Logic for Round . . . . . . . . .
FDV Operand Format . . . . .
Pencil and Paper Example of Floating-Point Divide .•.
Parallel Timing for 63. X .
Enables for Divide Step . . . . . . . . . . . . .
Example of Divide Step .
Terminating Divide Step.
Quotient to AQ
Operand Format for Round . . . . . . .
Pencil and Paper Example of Floating-Point Addition . • . . . . . . . . . • . . .
Parallel Timing for 60. X . . . . . . . . . . . . . . . . . • • . • . . . . . . . . . . . . .
Enabling the II-Bit Adder . . . . . . . . . . . . . . . . . • . •
Data Flow for Subtract Exponents ..
Enables for Add Coefficients .
Operand Format for Floating-Point Subtraction.
Pencil and Paper Example of Floating-Point Subtraction . . . • . . . . .
Parallel Timing for 61. X . . .
Enabling the II-Bit Adder
Enables for Difference of Exponents to SCR ..
Enables for Subtract Coefficients. . . . . . . . . . . .
Enabling 10's Shifts o .
Power Failure Detection . . . .
Interrupt Cycle Flow Chart
Interrupt Recognition Flow Chart
Trapped Instruction Detection ..
Sensing Network
Block Control, Front View
Block Control, Block Diagram .•
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356
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365
366
ILL USTRATIONS (continued)
Figure
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358A
358B
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Title
Timing for Register File Enables . . . . . . . . . . . . . . . . . . . . . . . . . .. .
Flow Chart for Updating Real Time Clock . . . . . . . . . . . . . . . . . . . . . .
Flow Chart for Connect (77. OC) and Function (77. lC) Instructions . . . . . .
Flow Chart for Activate Search (71) or Move (72) Instructions . . . • . . • •
Flow Chart for Output Buffer Cycle . . . . . . . . . . . . . . . . . . . . . . . . ..
Flow Chart for Input Buffer Cycle . . . . . . . . . . . . . . . • . . . . • . • . . . .
Flow Chart for Character Search Buffer Cycle . . . . . . . • . . . . . . . . . . .
Flow Chart for Move Buffer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flow Chart for IRT with Register File . . . . . . . . . . . . . . . . . . . . . . . . .
Contents of OX Register . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . .
Contents of IX Register . . . . . . . . . • . • . . • . . . . . . • . . . . • . . . . . . .
Communications Modules . . . . • . . . . . . . . . . . . . . . . . . . . . . • . . . . .
3300 Computer Physical Layout . . . . . . . . . . . . . . . • . . . . . . • . . . . . .
3300 Communications Module Block Diagram . . . . . . . . . . . . . . . . . . . .
Generalized Flow Chart of Operations . . . . . . . • . . . . . . . . . • . . . . . ..
Detailed Flow Chart of Sequence Operation . . . . • . . . . . . . . . . . . . . . .
Data Bus Transmitter Logic . . . . . . . . . . • . . . . . . . . . . . . . . • . . . . . .
3304 Processor with Data Bus Emphasized . . . . . . • . • . . . . . . . . . . . .
I/O Data Flow . . . . . . . . . . . . . . . . . . . . . . . • . . . • . . . . • . . . . . . .
Connect Sequence . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
Function Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . .
o Register Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
Channel Busy to Processor • . • . . • . • . . • . • . . . . • . . • . • . . . . • . . . .
Clear 0 Register Enable . • • • . . • . . . . . . • . . . . . . . . . . . . . . . . . . . .
Clear 0 Register Enable . . • . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . .
Bus to 0 Register Enable . • . . . . • . . . . • . • . . . . . . . • . • . . . . • . . . .
Channel Preset Status . . . • . . . . . . • . • . . . . • . . • . • . . . . • . . . . • . .
Reject and Parity Error Clear Enables . • . . . . • . . . . . . . . . • . . . . • . .
o Register to External Equipment Enables . . . . . . . . . . . . . • . . . . . . • .
Connect and Function Signals . . . . . . • . . . . . . . • . • . • . . . . . . . • . • . .
Channel Preset Enables . . . . . • . . • . • . . . . . . . . . • . . . . . . • . . • . . .
Channel Preset Status . . • . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
Reply on Connect or Function. . . . . . . • . . . . . . . . . . . • . . • . . . . • . . .
External Reject on Connect or Function . . . . • . • . . . . . . . • . • . . • . . .
External Reject Status . . . . . . . . . . . . . . . . . . . . . . • . • . . • . . . . • . .
Reject Signal to CPU . . . . . . . . . . . . . • . . . . . . • . . . • . • . . • . . . . • . .
External Reject Enables . . . . . . . . . . . . . • . . • . • . • . . • . • • . • . • . . .
No Response Reject FF . . . . . . . . . • . • . . . . • . • • . • . • . . • . • . . • . •
Channel Enable . . . . . . . . . . . . . . . • . . . . . . . . . • . . . . • . . . . . . . . .
Block Control Request upon Activate Write . . . . . . . . . . • . • . . • . • . . .
Timing for Connect or Function for Even Channel (70.0 + 77.1) ••.•.••.
Write FF and Transmitter . . . . . . • . . . . . . • . • . . • . • . . • . • . . . . . .
Channel Preset Clear Enable . . . . . . . . . . . . . . . • . . . . • . • . . • . • . • .
Graphic Representation of a Write Operation . • . . . . • . . . . • . . • . . . • .
Clearing the Block Control Request .. • . . • . • . • . . • . • . . • . • . . . . . .
Data Signal FF Enables . . . . . . . . • . . . . • . . . . • . • • . • . • . • • . • • . .
o Register to External Equipment Enables . . . • . . • . . . . . . • . • . . • . • •
Data Signal Transmitter . . • . . . . . . . . . • . • . . • . • . • . . • . • . . • • • • .
Terminate FF Enables . . . . . . . . • . • . . • . • . . • . • . • • . • . • . . • . • . .
Data Signal Transmitter . . • . . . . • . • . . • . • . . • . • • • • . • . • . . • . . • •
Block Control Request upon Reply . • . . • . . . • . . • . • • • • . • • . . . • . . .
o Register to External Equipment Enable . . • . . • . • . • • . • . • • . • . • • .
o Register to External Equipment Enables . . • . • • . • . . • . • . • • . • . • • •
Read Operation . . . . . . . • . . . . • . • . . • . . . . • . • . . • • • . . • . • . • • • .
Page
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xvii
ILLUSTRATIONS (continued)
Title
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406
407
408
409
410
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412
413
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415
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417
418
419
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xviii
Channel Enable
Enables . . . . . . . . . . . . . . . • . . . . . . • . • . . . . . . . . . • . .
Clear Channel Preset FF Enable . . . . . . . . . . . . . • . • . . . . . . . . . • . .
Read Signal to Controller . . . . . . . . . . • . . . . . . . . . • . . . . . . . . . . . .
Data Signal Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .
External Equipment to 0 Register Enables . . . . • . . . . . . . . . . . . . . . . .
Block Control Request upon Reply. . . . . . . . . . . . . . . . . . . . . . . . . • . .
Block Control Request Lockout Enable. . . . . . . . . . . . . . . . . . . . . . . ..
o Register to Bus Enable ... . . . . . . . . . . • . . . . • . . . . . . • . . . . • . .
Clear 0 Register Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminate Enable upon Operation Complete . . . . . . . . . . . . . . . . . . . . .
Channel Terminate Signal to CPU . . . . . . . . . . . . . . . . . . . . . . • . . . . .
Blocking Block Control Requests upon Termination . . • . • . . . . • . • . . . .
Terminate Enable upon End of Record . . . . . . . . . . • . . . . . . • . . . . • . .
Status and Sense Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Graphic Representation of a Sense Operation . . . . . . . . . . . . . . . . . . . •
Internal Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .
External Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
Parity Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .
Internal Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .
Channel Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . •
Interrupt Signal Circuitry . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .
Clearing Circuits . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . • . . . . . .
External I/O Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3307 Data Flow on Output (Without Disassembly) . • . . . . . . . . . . . . . . . .
3307 Data Flow on Output (With Disassembly) . . . . . . . . . . . . . . . . . . . .
3307 Data Flow on Input (Without Disassembly) . . . . . . . . . . . . . . . . . . .
3307 Data Flow on Input (With Assembly) . . . . . . . . . . . . . . . . . . . . . .
I/O Signals on Read (Assembly) with 3307 . . • . . . . . . • . . . . . . . . . • . .
I/O Signals on Write (No Disassembly) with 3307 . • . . . . . . . . . . . . . . . .
I/O Signals on Read Buffer Cycle (Assembly) with 3307 . • . . . . • . . . . • . .
I/O Signals on Activate Read (Assembly) with 3307 . . . . . . . . • . . . . • . .
I/O Signals on Write Buffer Cycle (Disassembly) with 3307 . . . . . . • . . . .
I/O Signals on Write Buffer Cycle (Disassembly) with 3307 . . • . . . . . . . .
3306 Forward (73 OR 74) Data Flow . . . • . . . . • . . . . • . . . . . . . . . . . •
3306 Forward (75 OR 76) Data Flow . . . . . . . . . . . . . . . . . . . . . . . • . •
3307 Forward (73 OR 74) Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . .
3307 Forward (75 OR 76) Data Flow . . . . . . . . . . . . . • . . . . . . . . . . . .
o Register
402
402
402
403
403
403
403
403
403
403
404
404
404
404
405
405
406
407
407
408
408
409
409
410
410
412
413
415
417
418
419
420
421
422
423
424
425
426
427
TABLES
Table
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Title
Drive Transformer Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Partial Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . .
Interface Signals . . . . . . . . . . . . . . . . • . . . . • . • . . • . • . . • . . . . . . .
Digit Position Selection . . . . . . . . . . . • . . . . . . . . . • . • . . . . . . . • . .
Read Storage Timing Chart . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . .
AND Gates for Sequence Progression . . • . . . . • . • . . . . • . . . . . . . . . .
Inverter Rank Transfer Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A, Q, and Bb Jump and Skip Instructions . . . . . . . . . . . • . . • . . . . . . . •
MTH Count Example. . . . . • . . . . • . . . . . . . . . • . • . . . . . . • • . • . • . .
SCR Count Example . • . . . . . . . . . . . . . . . . . . . • . . . . • . • . . . . . . . .
Floating-Point/Double-Precision Instructions • . . . • . . . . . . . • . . . . . . •
Representative Interrupt ID Codes . . . . . . • . • . . . . . . . . . • . • . . . . . .
Parity Error Interrupt Codes • . . . . . . . • . • . • . . • . . . . • . • . . . . • . . .
Interrupt Mask Register Bit Assignments . . . . . . • . . • . • . • • . • . . . . .
List of Trapped Instructions. . . . . . . . . . . . . • . . . . . . . . . . • • . • • . • .
Busy Comparison Mask. . . . . . . . . . • . • . . . . • • . • . • . . • . • • . • . • . .
Clear Instructions - Mask Bit Assignments . . . . . . • . • . . . . • • . • . • • .
Register Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
Scanner States . . . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . • . . • . . . •
Input/ Output Instructions. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3300 I/O Related Instructions . • . . . . . . . . . . . . . . . . . . . • . . . . . . . . .
Bidirectional Signals. . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
Signals from Channel to External Equipment . . . . . . . . . . • . . . . . . . . . .
Signals from External Equipment to Channel. . • . . • . . . . • . . . . . . . . . .
87
98
110
151
164
239
252
262
279
285
300
352
353
354
358
360
362
366
367
369
388
428
428
431
xix
CHAPTER 4
DESCRIPTION AND GENERAL INFORMATION
STORAGE
STORAGE CAPACITY
The maximum internal storage capacity of a 3300
Computer System is 262,084 28-bit words.
The
minimum internal stor age capacity is 8, 192 28-bit
words. The storage capacity of an 8K system may
be increased to 16,384 words by adding an additional
8K module to the basic system. Any additional increments beyond 16, 384 words must be made by adding
16K modules. Therefore, there are two types of
storage modules available, the 3309 Storage Module
(8K) and the 3302 Storage Module (16K).
3309 Storage Module
One 3309 (8K storage) is included as part of each
processor. No more than two 3309 1 s maybe attached
to anyone system. Figure 51 shows the 3309 Storage
Module
0
3302 Storage Module
A 3302 provides 16,384 words of storage capacity;
it has a 16K stack, not two 8K stacks. Therefore in
this text the 3309 and 3302 must be treated separately. Figure 52 shows the 3302 Storage Module.
67
Figure 51.
3309 Storage Module
STORAGE WORD FORMAT
The 28-bit storage word (figure 53) contains 24
bits of data, which may be exchanged with the processor, and four parity bits, which are generated and
checked only in the storage module. The storage
word can be considered to be four 6-bit characters
ann fonr parity hite:; (one p~t'ity bit associated '.vith
each character).
STORAGE PARITY
Each character within a storage word has one
68
parity bit associated with it (figure 53). During each
write cycle, a parity bit is stored along with each
character. When part or all of a word is next read
from storage, parity is checked for a loss or gain of
bits. The 3300 uses odd parity; that means the number of l' s in a character, plus the parity bit, always
totals an odd number. Any f:J.ilure to produce cor-'
rect parity read operations cuases a memory fault
indication on the storage module control panel and
the console, followed immediately by a program halt.
If the console PARITY STOP switch is inactive, parity
Figure 52.
27
26
25
24
3302 Storage Module
18
23
CHARACTER 0
17
12
CHARACTER
06
II
CHARACTER
PARITY
BIT
FOR
CHARACTER
3
PARITY
BIT
FOR
CHARACTER
PARITY
BIT
FOR
CHARACTER
PARITY
BIT
FOR
CHARACTER
2
I
0
2
05
CHARACTER
00
3
Figure 53. Storage Word Format
69
will still be generated, but the program will not halt
because of a parily error.
The storage module control panels, figures 54 and
55, contain lights which display each bit of the current storage word, including four lights for display
of the parity bits.
Complete the following table. Show whether the
parity bits of each character is a 1 or a O.
24-Bit
Word To
Be Stored
01234567
20356016
10667201
00010233
60731065
06731026
Parity Bit Parity Bit Parity Bit Parity Bit
for
for
for
for
Char 1
Char 3
Char 0
Char 2
STORAGE MODULE DESCRIPTION
Storage Registers
Two registers, Sand Z, are associated with each
storage module.
1. S Register - The S register contains the address
of the word currently being processed. The 3309
has a 13-bit S register; the 3302 has a 14-bit S
register. The address is transmitted from the
processor or the multiprogramming module.
2. Z Register - The 2S-bit Z register is the storage
restoration and modification register. A storage
word may be read into Z and the 24 bits of data
transmitted to the processor via the data bus or
the processor may send a new 24-bit word (or
portion of a word) over the data bus to storage
where the word is placed in Z, then written into
storage with the correct parity.
Read/Write Controls
During a normal memory read cycle, all bits of a
word referenced by (S)* are read out of core storage
in parallel, loaded into Z, used for some purpose, and
written back into storage intact.
A memory write cycle is performed just like a read
cycle except that certain groups of bits are blocked
from Z register initially and new data from the processor is placed in these bits of Z (Z) is then written back into storage. The correct parity for the new
data is also generated and written into storage.
Five modes of storage modification (partial writes)
are possible in t.he 3203/3209. In all cases, assume
that Z is clear. Z regisLel' is cleared only aL the beginning of each memory cycle (except when master
cleared). lfthe program stops as the result ofa parity error the operator can examine (Z) via the storage
module control panel (figure 54).
The storage modification mode s are:
1. Single-Character Mode - Anyone 6-bit character
may be ignored during read cycle. New data is
then loaded into the corresponding character position of Z and the whole (Z) is stored.
2. Double-Character Mode - The upper, middle, or
lower half (12 bits) of a word is ignored during read
cycle. New data is loaded into the unfilled half of
Z and the whole (Z) is stored.
3. Triple-Character Mode - Either of the two possible
triple -character groups may be ignored during read
cycle. New data is then loaded into the corresponding character positions of Z and the whole (Z) is
stored.
4. Full-WordMode - The whole 24-bit wordisignored
during read cycle. A new word is entered into Z
and (Z) is stored.
5. Address Mode - The lower 15 or 17 bits of a word
may be ignored during read cycle. A new word or
character address is then loaded into A and the
whole (Z) is stored.
0
*Parentheses signify "contents of. "
70
Figure 54. SK Storage Module Control Panel
Storage Module Control Panel
Figurc 51 shows thc storage control panel which
is mounted at the top of each SK storage module.
Figure 55 shows the storage control panel for the 16K
slorage module.
The drive voltage control permits the adjustment
of the drive voltage to 26v. The drive voltage meter
Figure 55. 16K Storage Module Control Panel
indicates drive voltage. It reads ,:t20% and is adjusted to read 0% (most modules require approximately
22. 5v to provide the best margins).
The panel contains indicator lamps to display the
contents of the S register, the contents of the Z
register (including the four parity bits), and three
storage faults: x or y drive line voltage failures and
storage parity fault.
The panel also contains a three-position switch
labeled CONTROL SELECT (figure 56). The storage
module may communicate with one or both of the processors (or pieces of special equipment), depending
on the setting of the CO~TROL SELECT switch. The
switch settings are:
10 The storage module communicates with the processor located to the left (as you face the control
panel) of the module. Refer to figure 56 and note
that the arrow for setting 1 points to the left.
2. The storage module communicates with the processor located to the right of the module. Note
that the arrow for setting 2 points to the right.
3. The storage module may be shared by both processors. Note that arrows point in both directions
for this switch setting (figure 56).
PROCESSOR
PROCESSOR
3209
Figure 56.
Use of Control Select Switch
A two-position scanner determines whichprocessor
communicates with the storage module at any given
time. If the storage module is being used by one processor, a request from the other processor must
wait. Control is then surrendered to the waiting processor at the end of the current cycle.
When a storage module is to be used by one processor only, the CONTROL SELECT switch should be set
to point toward that processor. This disables the
scanner and locks out the unused access path.
BUSSING SYSTEM
Figure 57 is a hlock diagram of an 8K storage module and shows the signaJ..g exchanged with aprocessor.
In figure 57 the dotted lines represent control operations while the solid lines represent transmissions. The heavy solid lines represent data transmissions.
Information and control signals are exchanged between a processor and storage modules over a system
of twisted-pair wires known as the bus system. Figure 58 is a photograph of bus wires in chassis 1.
S Bus
The S bus system is an I8-bit bus which supplies
a Storage Request Signal and a 17 -bit address to
storage. The 17 -bit address consists of a 3-bit
Module Select code and a 14-bit Coordinate address
71
x
DRIVE
(&'1 LINES)
r - - - ..
I
L -_ _ _ _ _ _~
,
,
,
I
I
I
,
,
r----'
I
L_
--
,
,
I
,
,
Y DRIVE
164 LINES
PER FIELD)
.
SENSE
FIELD 0
FIELD 0
LF
rL
(409& WORDS)
FIELD I
SENSE
FIELD I
(40S& WORDS)
I
I
I
I
I
I
I
I
PARITY
I
t
r
---,
L_
s
i
INHIBIT
I
I
REGISTER
J
' - - . - -_ _ _{_13_B_ITS_)_ _~----'
I
r----------------~
I
I
I
I
I
I
I
I
I
I
t~ -----l· ----------- STO~AGEO
I
LEfT S BUS
Z REGISTER
f-----
CONTROL
RIGHT S BUS
I
-----~44-/~'-' _..:)~,L
(24 BITS)
r
LEFT DATA
BUS
RIGHT DATA
BUS
RIGHT
LEFT
BUS
MAIN CONTROL _
STORAGE _
STORAGE
MAIN CONTROL
BUS
{
REQUEST. READ OR WRITE, MASTER
CLEAR, WRITE CHARACTER DESIGNATORS.
DISABLE PARITY
REPLY, IIUSY, PAR,n
for referencing a 3302. For referencing a 3309, the
lower 17 bits of the S bus contain a 4-bit Module
Select code and I3-bit Coordinate address. If the
Multiprogramming module is not present in a 3300
system the following characteristics exist:
1. Maximum internal storage capacity is 131K.
2. Only one bus system exists.
3. The storage address and storage request go
directly from the processor to storage.
If the Multiprogramming module is present the
following characteristics exist:
1. Maximum internal storage capacity is 262K.
2. Two distinct buses exist, one defined as the
right bus (allows access to addresses 000000
through 377777), the other defined as the left
bus (which allows access to addresses 400000
through 777777).
3. The storage address and storage request are
placed on the storage S bus by the Multiprogramming module.
72
fAt"_~
Figure 57.
8K Storage Block Diagram
BUS WIRES
Figure 58.
Bus Wires
Figure 59 graphically represents the S bus scheme
if the Multiprogramming module is not present
whereas figure 60 represents the S bus scheme if the
Multiprogramming module is present.
117 16
In figures 61 and 62, notice that any address
placed on the storage S bus becomes available to all
stor age modules in the system; however, Storage
Request (bit 17) goes only to the right or to the left.
14 13
00
I
~~--------------,~----------------~I
L
14 BIT COORDINATE
ADDRESS
3 BIT MODULE SELECT
I
CODE
Figure 59. Function of S Bus Bits
When Referencing 3302
STORAG E REQUEST
13 12
/17 16
~
001
1\~------------~vr----------------~I
L13
BIT COORDINATE
ADDRESS
I
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...
Figure 60.
Function of S Bus Bits
When Referencing 3309
4 BIT MODULE SELECT
CODE
STORAGE REQUEST
CPU
CPU
S BUS
LOW CORE
MULTIPROG.
MODUL
TORAGE
MODULE
TORAGE
MODULE
,----
....
)~STORAGE
S BUS
STORAG
MODULE
MODULE
HIGH CORE
Figure 61.
S Bus Scheme if Multiprogramming Module Present
73
CPU
"
IS-BIT S BUS
STORAG
MODULE
MODULE
STORAG
MODULE
TORAG
MODULE
Figure 62. S Bus Scheme if Multiprogramming Module Not Present
For a unique module to honor a storage request, the
Module Select code must match the setting of MODULE
SELECT switches.
Data Bus
The data bus transmits 24 bits of data to and from
the processor and storage register Z. As in the case
of the S bus, the data bus is tied in parallel to all storage modules and is also tied into each communication
channel. However, the data bus is used only by the
module which receives a request from the processor.
that prevents alteration of a block of storage addresses.
When logic in the computation section has determined
that a reference is about to be made to a protected location, it changes the write signal (previously sent to
storage but not yet used) into a read signal. Therefore, the contents of that location are not altered.
The storage module is given no other indication that
any addresses are being protected. Figure 63 shows
the system power panel with the STORAGE PROTECT
switches.
STORAGE PROTECTION
Storage protection is the feature of the 3200 System
3309 THEORY OF OPERATION
Two processors may share use of a storage module.
To reference storage a processor sends the address
of the word desired accompanied by a request signal.
A scanner determines which computer has first access
to the storage module. The request lines are monitored consecutively, insuring that each processor will
be acknowledged in turn, free from interference. If
only one processor is used the CONTROL SELECT
switch locks the scanner to continually monitor only
the right or left bus.
¥/hen tl request is received storage control gates the
Lj;..blt address trom tile S bus Into the SregIsterwhere
it is translated to select the proper drive lines for a
memory reference.
Each of the two memory operations--read from memory and write into m~mory - -consists 0[:
74
1. A read phase, during which a word of information
is removed from an addre s s in memory, followed by
2. A write phase, during which a word of information
(either the same word or a new word) is written
into memory at the same address.
The processor will specify either read from mem0ry or write into memory.
1. Read from memory. Memory performs a read/re-
store cycle in which a word is taken from memory,
entered into Z register, and re -stored in its original memory location. While the word is in Z register it is also transmitted to the equipment via
the data bus.
2. Write into memory. Memory performs a read cycle, with entry to Z register blocked for all or certain portions of the word from storage. The por-
Figure 63. System Power Panel
tions of the word to be blocked from Z are determined by the type of partial write mode selected
(selection depends on the instruction or cycle being
executed}.
The processor transmits updated information via
the data bus into Z register and then into the original
memory location.
Figure 64 maps out the theory of operation. It shows
the basic steps in one complete memory cycle:
1. Set busy FF.
2. Turn on read current.
3. Gate the contents of a storage cell into Z register
via the sense amplifiers.
4. Turn off read current.
5. Turn on inhibit current. (Prepare for re-storing
information. )
6. Turn on write current. (Re-store information.)
7. Strobe for parity errors. (Parity is only checked
early in the write cycle.)
8. Turn off write and inhibit currents. (Re-storing
is completed.)
9. Clear busy FF. (Cycle completed.)
Information access time for memory is approximately 750 nsec. A complete storage reference cycle
takes 1. 25 usec. There are other timing pulses in the
memory cycle but the ones listed above are most important.
75
v
~
---~
TIME~
3
12
4
t---
5
/
1\
6
8
7
The next portion of the chapter analyzes circuitry
in each portion of the memory cycle.
CONTROL SELECT
As described earlier, a storage module may communicate with a proce s sor via the right bus or left bus,
or the module may be shared by two processors, one
using the right bus and one using the left bus. The
CONTROL SELECT switch (figure 65) is used to select
right bus, left bus, or priority (a scanner controls use
of right bus or left bus in this case).
In the logic shown in figure 65, CONTROL SELECT
places a ground on the input ot one of the G18x terms,
allowing it to output a 1 to indicate which bus is se1ected. Note that the Yl8x: terms are sections of a
filter card (HAI7) and only remove noise from the signal. They do not delay or invert. The following discussion of the scanner explains the use of the signals
from G18x.
Scanner
Two processor modules may share a storage module. One processor communicates with the storage
module via the left bus, the other processor communicates with storage via the right bus. Storage requests are serviced on a first-come, first-served basis
by the storage module. A two-position scanner determines which computer has access to the storage module at any given instant. The scanner first checks one
line, then the other for a request. When a request is
detected (R620 or R621 = 0), the scanner is disabled.
K792/793 is then held clear for a left bus request or
held set for a right bus request. (See figure 66.)
If the scanner recognizes a left bus request and the
busy signal is not present, inverters G070-G072 output l's, gating the address on the left address bus into
S register where it is translated. G072 sets:
~
Figure 64.
Storage Reference Cycle Timing
9
1. K796/797 - indicates left bus selected.
2. Reply, K780/781 - indicates acknowledgement of
request.
3. Pulse generator, K750/751 - starts storage reference sequence.
When a right bus request is recognized and busy is
down, inverters G080-G082 output 1 's which gate an
address from the right address bus to S register. The
1 from G082 sets:
1. Reply, K780/781, and
2. Pulse generator, K750/751.
It also clears K796/797 to indicate right bus selected.
The scanner reactivates when the request is dropped
(which occurs under central processor control after it
receives the reply pulse from the storage module).
The scanner is active only when CONTR OL SE LECT
is set to priority. If only one processor is being used
CONTROL SELECT should be set to select the related
bus. This will disable the scanner.
Review the circuitry that has been covered so far by
reading these statements:
1. Control select circuitry causes the following scanner actions according to switch settings:
Position 1 disables the scanner (K792/793 clear,
K794/795 clear) and selects left bus (G182 sends
constant clearing input to K792/793).
Position 2 disables the scanner (K792/793 set,
K794/795 set) and selects right bus (G183 sends
constant setting input to K792/793).
Position 3 causes the scanner to flip back and
forth constantly and to lock when a request comes
from the processor. Receivers R620 and R621
statically have 0' s out which will allow the scanner
to run. Receipt of either request, left or right,
causes the output of G176 or G177 to drop to a
zero, stopping and locking out the scanner to one
of the following positions:
~41B
1S40C
1S25A
SELECT
SWITCH
LEFT BUS
~41A
~40B
~PR'OR!TY
i:¥I'~,~l'A,~S.ElE~J
~~~q;'4;;tc;<:,-htf:< .A!!~;.;&;,'~",;,:<~~<,
m"
~:
'".',
RIGHT BUS
,"";J;~,\;;,~
Figure 65.
75
Control Select Switch and Logic
Gl82
~
[8--11
R614
I
LEFT ADDRESS BUS ----.. S
LEFT BUS
REQUEST
*T65-
B---l
G070~
GI83 - RIGHT BUS
SCANNER
G080
K777
K794
037
*T65RIGHT BUS
REQUEST
K795
G072
K'796
LEFT BUS
027
G----l
G082
K797
RIGHT BUS
GI82 - LEFT BUS
RIGHT ADDRESS BUS
G()'!2
-+ S
0082
E3I2
Gl71
~
K792
LEFT BUS - GI82
K773
Gl83
GI76
GI77
0.1 usee.
Figure 66.
Left and Right Address Bus ---+ S Control Logic
l!. left request (G176 output going to a zero), the
scanner will not set K792/793, leaving it
cleared. K794/795 is also clear and the scanner remains that way until the request drops.
This stopped position is thatwhich the scanner
assumes if CONTROL SELECT is in position 1.
2. The scanner locks into a position and a left or
right request allows the outputs of G070, 071,
072, or G080, 081, 082 terms to come to al
leveL This allows the address (13 bits) on the
S bus to enter the S register.
Assume Bit 00 is to be set. The central
processor holds the 13-bit address on the S
bus line (either left or right). When G070 or
G080 outputs 1, information is transferred
from the S bus via the receiver cards to the S
register. The S register is cleared at the end
of a memory cycle if there was no parity er-
ror or if parity error recognition has been
disabled.
3. The output of G072 going to 1 sets the left/
right bus FF (K796/797). The output of G082
going to 1 clears the left/right bus FF (K796/
797). The output of either G072 or G082 sets
the reply FF (K790/791). The reply FF informs the processor that storage has received
and is processing the request. Within the
CPU, the reply signal drops the request to
storage and causes sampling of the data bus if
necessary. With the request dropped, the
scanner again runs if CONTROL SELECT is
in the priority position.
Outputs of either G072 or G082 going to a 1
also cause the memory cycle delay line to
start.
77
BIT 00
T600
8000
8001
BIT 01
T601
8010
8011
BIT 02
T602
8(l20
8021
BIT 03
T603
8030
8031
BIT 04
T604
8040
8041
BIT 05
T605
8050
8051
G090 Clear 8
G070
G080
Left Bus to 8 Right Bus to 8
Figure 67. S Register Input Logic
DELAY LINE
The memory delay line supplies necessary time
intervals to accomplish reading out of information
from memory and writing back of information into
memory.
Before proceeding, review the major timing intervals of a storage reference cycle (figure 64).
The 3300 Computer System uses coincident storage
principles. When read or write current is turned on,
a previous gating or selecting process must be used to
select the X and Y drive lines that will carry read or
write current. These and other operations will be devdvp(;d dS a puls~ is follO\\~ed down the delay 1in'~.
Each operation will be covered when the pulse
reaches that point in the delay line. Considerable time
will be spent in each area and all circuitry involved
then will be covered.
It is a good idea to "step back" occasionally to keep
track of our objective, which is to read the contents of
a memory location and re-store it in memory. It is
also a good idea to review operations and circuitry
previously discussed 0
Assume, for example, that the processor needs to
use storage 0 Our study of the circuitry has shown:
1. How the request was received.
20 How storage notified the processor that the request
had been received and was being processed (reply).
3. How the necessary information from the S bus, the
field and coordinate address, was sent to S register 0
Now let s take a look at the actual memory cycle delay line.
I
Delay Line Timing
The timing for a storage reference cycle is provided
by a pulse traveling down a delay line. Signals are
available at various taps on the line as the pulse passes
by them. These signals are used to time the storage
reference cycle. The input to the delay line is normally held at a steady 1 by D150 (see figure 68A) .When
the pulse generator FF is set (by either G072 or G082),
its set output drops the output of D150 (a CA08 card) to
a 0, starting a pulse down the delay line. (For further
information refer to 3000 Printed Circuits,Manual. The
clear output of the pulse generator simultaneously
causes Z to clear.
The first tap (A3) from the delay line (time 1 of
figure 64) will:
1. Set Activate Read FF (K700/701, figure 68B)
which enables the 8elected line drivers.
2. Set Gate FF (K710/711, figure 68C) which enables the selected gates to the drive transformers to begin the read phase of the cycle.
3. Set Busy FF (K770/771) which turns on the
storage active status display.
The Busy FF (K770/771) clear output is inverted by
K773 and disables the B07x and G08x inverters to
prevent a new address from being transferred off
bus to S. This can be seen in figure 66.
Figure 69 is a circuit within the 3309 that generates
a Master Clear if the module has been busy longer
than two microseconds. This logic also prevents
Master Clears from occurring during a memory cy cleo The output of Gl69 will be a 1 only if storage is
Not Busy (Busy) or if the Busy signal has been up
longer than 2 usec.
Return for a moment to the Activate Read FF (K700/
701, figure 68). When this FF sets, the selected line
drivers are turned on. Gate FF (K710/711) turns on
the gates. How the drivers and gates were selected
is the next topic to be discussed.
ADDRESS SELECTION
Information stored in memory is held in cores located at intersections of X and Y half-current drive
GI82
K773
K793
G072 ------. Pulse
G082
E300
A.
G173
LEFT BUS -
Activate
Read
E303
GI82
GI76
N06A
GI77
r;;;:;AA-i----<___~ K704
K706
026A
E314
lines. The 4096-word memory module has 64 X and
64 Y drive lines. In order to reference a location, the
13-bit address in Sregistermust be translated so that
one X and one Y drive line are energized.
The outside appearance of an SK memory stack is
shown in figure 71. An SK stack is made up of two
identical 4K fields. In figure 71 visually follow the
cable coming up from the lower right corner and note
the flanged area immediately behind it. This flange
separates the two fields. They can be disassembled
by removing the cables and then the connecting bolts.
MC G171 - - - - '
B.
HOlLl<.
E303
H02A
E334
G171 _ _...J
MEMORY PLANES AND WAFERS
The wires threading the memory cores are strung
across the center areas of square mounting frames to
form memory planes. The wires used to drive and
sense the cores are also used to hold the cores in place.
A memory plane is a matrix of 4096 cores representing one bit of the 2S-bit computer word. Each
plane has 64 X drive lines passing through 64 columns
of cores with each drive line threading all 64 cores in
one column. The Y drive lines are threaded similarly
but at a 900 angle to the X drive lines.
G01A
G01B
C.
Figure 68. Pulse Generator, Activate Read,
and Gate Logic
004A
Figure 69. Busy FF and Left Address Bus -... S
Control Logic
2!04B
BUSY K771
MASTER CLEAR
M40A
40.0 mSEC.
g)30D
POWER ON
M.C.
Figure 70. 3309 Master Clear Control Logic
79
A memory wafer is formed by wiring a four-section
frame so that it contains four distinct bit planes (figure 72). Each memory plane contains one bit of a word,
so a wafer contains four bits.
MEMORY STACK
The cubic memory stack is formed by nine wafers
mounted one behind another. The front wafer, the input or terminal wafer, serves as a terminal point for
the X and Y drive lines. The bit plane wafers follow
and may be numbered sequentially from front to back
beginning with O. Bits 0-23 are contained in the first
six bit plane wafers (0-5). Wafer 6 contains the bit
planes for the four parity bits. The last wafer serves
as a transposition plane where X and Y drive lines are
transposed from one section of the stack to another.
The 64 X or Y drive lines are arranged in four stripes
of 16 lines each, eight even and eight odd. Each stripe
is associated with one inhibit line. To reduce noise
the odd drive lines within each stripe are transposed
at the transposition wafer. The first four odd drive
lines change relative positions with the last four so
they return to the input wafer threaded between different even-numbered drive lines. Exploded views of
the stack are shown in figures 73 and 74.
Figure 71.
8K Memory Stack
XOO (OR I VE FROM
TRANSFORMERS)
XOO COMING BACK UP
~THROUGH THE FIELD.
BIT I
ro~
BIT 0
~
~
TERMINAT~I~O~Nr---~--------------~~~---------+--------------~~~--~,YOO COMING
~
"
J UP THROUGH
THE FIELD
CO-ORDINATE_----J'-
,
"0000"
BIT 3
BIT 2
I
THREADS
THROUGH
THE
1/
~,----+'--------------~l~~~'--------~l-.--.-------.---"--. .-..--"----~~~~~"4J----~I~~~~::;~:~~-
Figure 72.
Memory Wafer
TO fiELD I
80
THREADS DOWN
THROUGH THE FIELD
Figure 73. X Drive Line Configuration
(Front View)
N
32 EVEN X DRIVE LINES
l FROM 32 TRANSFORMERS)
TERMINAL WAFER
l\NPUTjOUTPUT)
EVEN CORE
BITS
(~~)
ODD CORE ARRAY
BITS
(~ ~)
EVEN CORE ARRAY
BITS
(91\ 108)
ODD CORE ARRAY
BITS (13
32 ODD X DRIVE LINES
(FROM 32 TRANSFORMERS)
12)
14
15
/
EVEN CORE ARRAY
BITS (17 16)
19 18
ODD
CORE ARRAY
BITS
(21
23
X DRIVE THEN GOES TO THE INPUT
WAFER OF FIELD I AND THROUGH
FIELD I TO THE TERMINATING
RESISTORS.
20)
22
EVEN
CORE ARRAY
BITS
(25 24)
27 26
TRANSPOSITION
WAFER
32 ODD X DRIVE
TERMINATING RESISTORS
w
(THE EVEN X DRIVE TERMINATING
RESISTORS ARE NOT SHOWN)
E
TRANSPOSITION
WAFER
EVEN CORE ARRAY
BITS (25 24)
\27 26
~
ODD CORE ARRAY
BITS (21
20)
\23 22
~
Figure 74. Y Dr.ive Line Configuration
(Rear View)
EVEN CORE ARRAY
BITS (17
19
~
16)
18
ODD CORE ARRAY
BITS (13
12)
15 14
EVEN CORE ARRAY
BITS
~
C~ I~)
0 DO CORE ARRAY
BITS
(~
:)
EVEN CORE ARRAY
BITS
(~ ~)
TERMI NAL WAFER
~ (INPUT/OUTPUT)
_
32 ODD Y DRIVE LINES
(FROM 32 TRANSFORMERS)
32 ODD Y DRIVE
TERMINATING RESISTORS
(THE EVEN Y DRIVE TERMINATING
RESISTORS ARE NOT SHOWN)
32 EVEN Y DRIVE LINES
(FROM 32 TRANSFORMERS)
s
81
Two 4096-word stacks (fields 0 and 1) are mounted
face to face, making one 8192-word stack. These memories work together with common X drive lines and separate Y drive lines. Although the two stacks are physically identical, for easier wiring the bit planes of field 1
are rotated 900 clockwise from those of field O. The X
drive lines of field 1 are inverted from those of field 0
(figures 75 and 76). The odd Y drive lines enter fields
o and 1 from the left. The even Y drive lines enter
fields 0 and 1 from the right (figures 75 and 76).
Terminating resistors for the X drive lines are
mounted on me rear panel of the stack and those for
the Y drive lines are on the side panels.
Figure 72 is a simplified layout of four bits and the
selection method via X and Y coordinates in field O.
Note that the Y drives terminate in this field (0) while
the X drive line continues into the next field (1).
Separate connections are made to the sense and inhibit lines of each memory bit plane. Each sense line extends to a pair of tabs at a corner ofthe memory board.
These tabs are connected to the sense amplifier circuits
by twisted -pair wiring. Each inhibit line is brought out
to a pair of tabs on the memory board. The se tabs are
connected to the inhibit circuits by twisted -pair wiring.
Drive Lines
The 64 X drive lines enter the two right planes of
wafer 0 from the terminating wafer and thread through
all the cores in the 14 right planes. Each drive line
threads all the cores in one columnof a plane, then is
jumpered to the corresponding column of cores in the
next plane.
At the last wafer the X drive lines are transposed
and returned to the input wafer through the left planes
of the memorywafers. The X drive lines are common
to fields 1 and O.
Fields 1 and 0 have separate Y drive lines. Only the
Y drive lines for the selected field are energized at any
one time. These lines thread the wafers in much the
same manner as the X drive lines are threaded. The
Y drive lines in field 0 run from input wafer to transposition wafer through the lower two planes and return
through the upper two planes. The Y drive lines for
field 1 are threaded from input wafer to transposition
wafer through the upper two planes and return through
the lower two planes.
For easier construction the even -numbered drive
lines enter one side of a wafer while the odd-numbered
drive lines enter from the opposite side (figures 75
and 76).
The half-current drive lines are energized in the
same manner as transmission lines. Characteristic
impedance of ;l drive line is approxima.tely 130Q, so
each line is terminated with a 130Q, lOw, nonillductive
resister. The lines are energized by pulses of 22-25v
and the lesulting half currents are about 340 rna.
82
STACK CONSTRUCTION (field 0, 4K)
1. Each connector on the north (top) side of field 0
serves the following purpose:
A. Odd X drive to
CHASS IS
field 1
S I DE
B. Even
CD 0
@&
c9
NORTH
X dri ve s
from transformers
C. Inhibit stripes 2
and 3 (28 wires)
D. Inhibit stripes 0
and 1 (28 wires)
E. Sense (7 twisted
pairs)
2. Each connector on the east (right) side of field 0
serves the following purpose:
e
A. Even
@G
Y drive
lines input from
transformers
B. Inhibit stripes 2
and 3
C. Inhibit stripes 0
and 1
D. Sense
CHASS IS
SIDE
(oJ
EAST
3. Each connector on the south (bottom) side of field 0
serves the following purpose:
A. Even X drive output to field 1
(!) @ @
CD CD
CHASS IS
SIDE
SOUTH
B. Odd X drive from
transformers
C. Inhibit stripes 0
and 1
D. Inhibit stripes 2
and 3
E. Sense
4. Each connector on the west (left) side of field 0
serves the following purpose:
CHAS SI S
SIDE
II~I( \ I
~'VI
WEST
A. Odd Y drive lines
from transformers
B. Inhibit stripes 0
and 1
Inhibit t:>tripes
and 3
D. Sense
'\....I.
1.
ODD X DRIVE
ODD X DRIVE
(FROM CORE ARRAY I)
(FROM FIELD 0 VIA INPUT WAFER)
INHIBIT STRIPE 2 INH IBIT STRIPE I
SENSE BIT 3
INHIBIT STRIPE 3
INHIBIT STRIPE 0
S
INHIBIT
SENSE BIT
INHIBIT STRIPE
4096 CORES
(64 X 64)
ODD Y DRIVE
(FROM 32
FTORR~NESRS
INHIBIT STRIPE 2
VIA INPUT INHIBIT STRIPE 3
WAFER)
BIT PLANE 3
4096 CORES
(64 X 64) 1 4 - + - - - - - - - EVEN Y DRIVE
(FROM 32 XFORMERS
VIA INPUT WAFER)
BIT PLANE I
INHIBIT STRIPE
ODD Y DR IVE - - - - - - - 1 - - + 1
(FROM CORE ARRAY I)
SENSE BIT
24--~
4096 CORES
(64 X 64)
0
INHIBIT STRIPE
4096 CORES
(64 X 64)
~t-------
EVEN Y DRIVE
INHIBI';F~~MpC£FW ARRAY I)
BIT PLANE 2
INHIBIT STRIPE 3
INHIBIT STRIPE 3
SENSE BLT 0
INHIBIT STRIPE I
INHIBIT STRIPE: 2
EVEN X DRIVE
EVEN X DRIVE
(FROM CORE ARRAY I)
(FROM FIELD 0 VIA INPUT WAFER)
Figure 75. Even Memory Core Array, Field 0
EVEN X DRIVE
EVEN X DRIVE
(FROM CPRE ARRAY I)
(FROM 32 XFORMERS VIA INPUT WAFER)
INHIBIT STRIPE 2
INHIBIT STRIPE I
INHIBIT STRIPE 3
I HIBIT STRIPEO
SENSE BIT 0
~-L~~~~N~__~~~~
INHIBIT STRIPE 3
SENSE BIT I
ODD Y DR IVE ------------+~
(FROM CORE ARRAY I)
4096 CORES
(64 X 64)
4096 CORES
(64 X 64)
BIT PLANE I
BIT PLANE 0
INHIBIT STRIPE 2
1 4 - + - - - - - - - EVEN Y DRIVE
~---'INHIBIT
(FROM CORE ARRAY I)
STRIPE I
INHIBIT STRIPE 0
INHIBIT STRIPE 3
INHIBIT STRIPE 2
ODD Y DRIVE
f~~~s :"2
-------+-~
INHIBIT STRIPE
FORMERS
VIA INPUT INHIBIT STRIPE 0
WAFER)
4096 CORES
(64 X 64)
BIT PLANE 3
4096 CORES
14-+------EVEN Y DRIVE
(64 X 64)
(FROM 32 TRANSFORMERS VIA INPUT
BIT PLANE 2
~--+SENSE BIT 2
WAFER)
INHIBIT STRIPE 0
INHIBIT STRIPE I
INHIBIT STRIPE 2
ODD X DRIVE
ODD X DRIVE
(FROM CORE ARRAY I ) (FROM 32 TRANSFORMERS VIA INPUT WAFER)
SENSE BIT 3
Figure 76. Even Memory Core Array, Field 1
83
Drive Compensator
In order to hold a constant load on the memory power
supplies, load compensator circuits are enabled when
the memory drive circuits are not carrying current.
When neither read nor write is being performed the
X and Y drive lines are turned off and the load compensator is enabled. The load compensator consists
of two C03 line driver cards (two sections per card).
Each section drives a current of approximately 400 rna
through a 50Q, lOw, noninductive load resistor.
line threads 1024 cores in a 4K field. Inhibit stripes
are common to fields 1 and 0; thus, each inhibit stripe
threads 2048 cores in an 8K stack.
Four inhibit lines are needed to thread the 4096 cores
for each plane (figure 77). The inhibits are not jumpered together and each inhibit winding appears in one
plane only.
Use of four stripes per plane reduces the number of
cores disturbed by an inhibit pulse, thus reducing noise
generated in the sense amplifier windings.
Inhibit Line s
Since the drive lines affect simultaneously all 28
cores in a selected storage location it is necessary to
negate those lines affecting any bit position which must
remain in the clear state. The inhibit line carries a
340 rna current parallel to one of the half-current drive
lines, but in a direction opposite to the half-write current. Therefore, if the inhibit current is flowing duringwrite phase it will cancel one of the half-write currents and will prevent any core through which it passes
from being switched to the set state.
The inhibit lines in each plane are arranged in four
groups or stripes. Each stripe is 16 cores wide and
extends all the way across the plane; thus, each inhibit
Inhibit Compensator
As in the case of the drive lines, load compensator
circuits are enabled during times when the inhibit
circuits are not carrying current. This holds a constant load on the memory power supplies.
The inhibit circuits include a load compensator for
each plane in the inhibit driver selection scheme. Four
inhibit driver circuits are required per plane and a
fifth circuit is included as a compensator. This fifth
circuit is an inhibit compensator, card type C09. The
inhibit circuits are selected one at a time through translations from Sand Z registers. When all four inhibits
to a plane are turned off, the inhibit compensator is enabled. The compensator circuit drives 340macurrent
TO INHIBIT GENERATORS
~
______~A~______~
....
....
x
0
40
x
....
0
x
x
10
V
..,....
x
0
N
x
....
INHIBITS OPPOSE X DRIVE IN BIT
PLANES I, 5, 9, ETC. AND 2, 6, 10, ETC.
0
x 0x
NO TE:
UPPER 2 BITS OF
DRIVE LINE DESIGNATOR INDICATES
INHIBIT STRIPE.
Y77
E
~
STRIPE 3
16 LINES
..,
00
wW
o.Z
~::J
1-40
00_
N
00
WW
o.:!:
~-'
1-40
00_
- VI
W
WZ
0.-
~-'
1-40
00-
0 00
wW
o.~
~-'
1-10
(/j-
Y60
STRIPE 2
16 LINES
Y57
STRIPE I
16 LINES
Y37
STRIPE 0
16 LINES
YI7
Y4 o
Y20
YO o
PLANE 0
I NHIBITS OPPOSE Y
DR IVE IN BIT PLANES
0, 4,8, ETC AND
3, 7, II, ETC.
Y77
STRIPE 3
16 LINES
Y60
TO
INHIBIT
GENERATORS
000
wW
o.~
~-'
1-10
00-
I
YOO
I
I
IIIIII
III! 11111
~ .............. J~~]!I
x
x
~
I
The inhibit stripes in planes 0 and 3 oppose
the Y drive lines while the inhibit stripes in
planes 1 and 2 oppose the X drive lines.
Figure 77. Memory 'Wafer-Inhibit Stripes
through a 133Q, 25w, noninductive resistor. The 133Q
resistor is approximately equal to the sum of the 13Q
DC resistance and 120Q terminating resistance of an
inhibit line.
Sense Lines
A simplified example of a sense winding is shown in
figure 78. One sense line threads all cores in a memory plane. The ends of this continuous line are extended to terminals near a corner of the plane.
The rapid flux change which occurs when a core
switches state induces a voltage of approximately 35
mv on the sense line. This voltage appears across the
differential amplifier inputs of the sense amplifier
(card type HAI8) and results in a logical 1 at the amplifier output terminals. This output occurs when any
core in the plane switches state in either direction, but
the output is sampled only during read phase.
The flux density of half-selected cores is changed
slightly by a read drive pulse and induces noise voltage
on the sense line. Noise voltage is reduced by threading
the sense line through the cores of a plane so that noise
signals from half-selected cores cancel each other.
Using the previous material as an introduction to
physical characteristics of a memory stack, we now
come to the actual electronics of the stack. Each circuit will be studied completely and actual prints will
be used to show selections.
HALF-C URRENT DRIVE LINES
44 V, 340 rna
Half-current
Drive Lines
44 V, 340 rna
SENSE
AMP
\
1 output
when the
core
switches
TWISTED PAIR
1
INHIBIT LINES, 40 V, 340 rna
Figure 78. Simplified Sense Quadrant
S Register
The S (storage address) register holds the storage
address during a storage reference. The r~gister consists of 13 single-rank flip-flop stages and has no properties other than storage An address may be entered
into S from either the right or the left address bus.
These addresses are gated into S (by the G070, G080
terms) at the same time a signal is sent to begin delay
line timing. S is cleared at the end of each memory
cycle if there is no parity error.
0
Line Driver Selection
Three bits from S register select the line driver
circuits (figure 79:) and either read or write. Bits 0,
3, and 5 select the two circuits in the X coordinate.
Bits 6, 9, and 11 select the circuits in the Y coordinate.
The translation is such that the selected pair of line
driver circuits will have all 0 inputs.
The circuitry in figure 80 selects the X drivers and
gates: Bits 0-5 of S register determine which X line
is selected. For the time being, it will require persistence to get the outputs from the terms in the X gates
and X transformer drivers. Inverters G300-G305 must
output O's to be considered turned on(assume E336 is
0). The X gate inverters (GOOO-G007) must have O's
85
X GATES
Y GATES
Y
x
DRIVERS
DRIVERS
S REGISTER
The storage address converts directly,
giving the selected drive line numbers in
octal. Bits 00 through 05 select the X
drive line; bits 06 through 11 select the
Y drive line; bit 12 selects the Field.
Figure 79. storage Address Bit Assignment
in to turn. on. The X transformer drivers (DOOO-DOI5)
also need all O's in to turn on. One gate and two drivers must be turned on to select a drive line.
G302 =
G303 =
G300 =
G301 =
3. Which X transformer drivers would be outputting
logical l' s? (K700 has been discussed previously
and K730 will be discussed later. For this problem, K700 will be 0 and K730 will be 1.)
and
Work the following problem through the circuitry for
address 03765:
1. Which X gate card would output a I? (The K712 and
K715terms are from the outputs of gate FF, K710j
711, discussed earlier.)
----
Carry these outputs to the following circuits, showing the X drive transformer. Determine which T card
will turn on. To turn it on, you will need the X gate
and two X transformer drivers.
You should have arrived at T326. If you did not,
check yourwork. There are Y drive lines to consider
yet, and we may as well enter into these.
2. What would be the outputs of these terms? (The
K701 term comes from activate read FF discussed
earlier. The K731 term comes from activate write
FFwhich will be presented later; for now consider
the output of K731 to be 0.)
x
X GATES
~H07A
ACTIVATE
T-eJ
G3~0
GATE UI3
G304
G305
"EAD'
ACTIVATE WRITE
TRANSFORMER DRIVERS
--+-..1
K70.
- . . . . -_ _ _ _ _ _ _
'73.
-+--,--_ _ _ _ _ _j-.-.J
~H08A
:l GOOI
f
I~
Kl13
~A
f---- J
~--
G002
1
G35'
I-'04A
5000
5030
I~
G3~2
K713
I
036 • DRIVER DISCHARGE
r
UHIOA
::J G003
f
6353
GATE K 715
635.
~HIIA
04
f
l-S-l
-aJ
K113
SOOO
S031
5001
5030
)( TRANSFORMER
DRIVER SELECTION
S REGISTER
BITS 05,03,00
nHI2A
J6oo5
1
;~
K715
5001
5031
G355
SO~O
GHI3A
J GOO6
T
K71~
-aJ
5051
G3~6
nHI4A
....., G007
"T
~f-tl-t-I-tl---+--+-.-.J
I
5L 151.
5040
11
5020
."
I
I"':;A~ ~I'='-:~A:-:-:TE:-:G:-: 'T= -E
SIJ~I
50~O
5010 ,
'------..vr-----J1
x
8305
K701 ~ ACTIVATE
GATE SELECTIO N
5 REGISTER
BITS 04,02.01
~1'31
!
I
I
REAO
': ACTIVATE WRITE
G303
Figure 80.
86
~b'
X Gates and Transformer Drivers
G305
G302
Address Translation
Logical translation is such that the number of the
selected X drive line is identical to the number contained in bits 0-5 of the 13-bit storage address. Bits
6 -11 specify the Y drive line number. This may easily
be seen by converting to octal. Bit 12 of the storage
address selects the field to be used. Bit 12 is a 1 to
select field 1 and a 0 to select field O.
Look at the top of T326 again. On the right side at
the top you will find a 53 (decimal) and a 65 (octal).
The same will be true for any address line for either
Xor Y.
To further break the transformer card down, a circuit is described in figure 81. It is a transformer
card with the pins numbered.
HI ADDRESS
LO ADDRESS
GATE
TRANSFORMER
Input Pins
Addresses
1 and 15
10 and 6
1 and 6
10 and 15
Read 10
Write 10
Read hi
Write hi
TRANSFORMER
I{)
DRIVERS
15
DRIVERS
Figure 81. Transformer Card with Pin Numbers
GATE
Gate numbers are quickly determined by lifting out
the specific bits that select the gate and aligning them
in binary, then reading them in octal. The example
that was worked through used G006. Take bits 4, 2,
and 1 from S register for the address we want (65)
and consider what they represent:
Table 10 shows that driver A is always on during a
read operation and driver B is always on during a write
operation. C or D determines whether a Hi or Lo
address is read or written.
IS
110
I
Bit 4
1
101
c
1\
Bit 2 Bit 1
1
0
G)
If)
(!)
= 6 or G006
[till
m
-
-
If)
0
0
<:)
0
0
C
CD
If)
~
<:)
i "a"f
-----
You should have had T437, GI07 for both read and
write, Dl12, Dl15for read, Dl13, Dl14 for write. If
you didn't, check yourself by working the actual circuit.
The only aspect of circuitry left to simplify is finding some easy way of determining which transformer
drivers will be turned on. The following table will help,
if you remember Hi and Lo address lines (Lo =00-37,
Hi = 40-77).
It)
0
0
0
0
m
If)
~
<:)
f f
"0"
Table 10. DRIVE TRANSFORMER SELECTION
OPERATION
DESIRED
Transformer for read _ _ (Were you in the right field?)
for write
Gate for read
--(Were you inthe right field?)
for write
Transformer drivers for read _ _ _ _ and _ _ __
for write
and _ _ __
N
"e"
"A"
Find the transformer number that will be used for
Y lines for address 03765. Use the following circuitry
and the octal shortcut:
[00
15
-
0
Read Lo address
Write Lo address
Read Hi address
Write Hi address
TRANSFORMER DRIVERS ON
A
D
C
B
Yes
No
Yes
No
No
Yes
No
Yes
No
Yes
Yes
No
Yes
No
No
Yes
It can be seen in the table that Driver A is always
on in a Read operation, and Driver B is always on in
a Write operation. If Driver A is always on for a
Read operation, the difference between reading a Hi
or Low address is determined by the selection of C
or D. The same prinCiple applies to writing. B is
always on during a Write operation and Hi or Lo is
controlled by C and D.
87
23
27
31
37
55
67
1 T
T T
ij
GI8B
1
HI4A
~
r
J
21
~
GI8A
B-1 r
J
17
21
J'1
49
61
8--f
'r
J
T324
L
GI7A
r
7
~
8-f
r
T322
J
'f..
,J
3
I,:j
GI58
I
B-1
'r
'J
01
J
I
J-,
GI5A
1
T
I~
\...
J
l
h
45
T
1332
JI
T
l
l
J
HI1A
i
43
II
~
h
TT
h
T331
HIS8
i
9
II
41
51
,T1330Tl
II
I
HI6A
I
i
r
, I
«[fljJ_
0 0
(l)
Figure 82.
C)(:71
47
T333
13
~
UU
r
HI7B
T TL
T32(.)
[
HI8A
~.
33
41
I
T334
Tf
I
f T
H08A
T Il
35
T321
57
71
i
r
8--1
i
31
GI6A
H09A
h
HI8B
15
h
1
5
59
T335
J-,
39
GIGB
'I'
-:J
J
[
T323
,J
r
25
31
1
YT
HilA
[
HI9A
~
T T
~
I
T336
1 T
h
I
J
I
Ir
J,
27
GI7B
,r
f,Jr
I
51
T325
8---f
I
TT
I.
TT
~
I
61
75
r
19
HI2A
H07A
i
I
HI3A
IGOOO
HI9B
29
T326
1
T337
53
TT
J
HIOA
~
h
T327
63
77
0
0
~
I I
«[ill]1O
-
~
10
«[ill]'
-
!II
10
o -
(l)
I
0
I
N
0
0
N
I
0
0
I
!II
X Drive line
-
-
0
0
0
-
!II
0
3i
63
77
31
37
37
63
77
H38A
H38A
~~------------~--+-----~
~
Z9
35
~~-------------+~~--~
61
75
H37A
H37A
~~------~~------------~
Z7
33
~~------4--+----------~
59
73
H36A
H36A
~~------;--+--~--+-----~
Z5
31
~~------~~--~~;-----~
Z5
31
57
71
57
71
H35A
H35A
~~------~-+------------~
15
17
~~------~~~----------~
47
57
H34A
H34A
~~------~~--~-+----~
13
15
~~------~~--~~4-----~
45
55
H33A
H33A
~~------~4-----------~
II
13
~~-------+~~----------~
43
53
H3ZA
H3ZA
~~------+--+---+--~----~
9
\I
~~-------+--~--~~-----9
II
41
51
41
51
H31A
H31A
~
~
C[
..,
N
CI
~
0
..,
0
CD
N
,....,
C[
of"
on
CD
C[
C)
C)
0
0
C)
H
..,
..,,..
Figure 83.
CD
N
CD
(II
N
N
0
0
CD
CD
N
H
..,~
H
CD
;;;
H
Y Drive Line
89
E338 Y DRIVER DISCHARGE
H22A
5060
5090
+--o-~
H22B
5060
5091
-J--...---o-~
H23A
Y TRANS FORME
DRIVER SELECTION 5 RE
t--_ _ _ _ _~~BITS 11,06,09
H-t--t-t--.l~~
5061
5090
5061
5091
K731
5110
5111
K731
5111
110
K701 "ACTIVATE READ
K731" ACTIVATE WRITE
5101 SOBI S071 I K714 ACTIVATE GATE
5100 5080 5070
v
Y GATE SELECTION
5 REGISTER
BITS 10,08.07
SELECT FIELD 0
L21A
Figure 84.
Y Gates
G071 (LEFT BUS'" 5)
1 - - - - - - 0 - - - - - - - . MEMORY FI ELD
,SELECT BIT 12
5120 r - - - - - - - - - - - . J
t-----(}--~
SELECT FIELD I
L21B
Ll7
(RIGHT BUS-+S) G081
Figure 85.
90
Field Selection
G091
CLEAR 5
,
L20B
~'SI25l
Y TRANSFORMER
Y
FIEL 0 0
5123
DRIVERS
TRANSFORMER
FIELD I
5122
DRIVERS
JI32
lG38 A
K704
~OIOOJ --Activate Read - - - K704
J 0101 J
K734
W
--Activate Write--
G38
1
-K734
]
:J
0117 ,
-.J
:J
~,
o---J
I
~
~I
o---J
0107
G26A
H2-;"B
lH30 A
0126
WJ
J
~G3IB
1
..J
J
G32B
1
H30 B
ln6
G32A
0113
W
71
0127 '
W
~
1
0123 ,
0125
G31A
0111
I43 A
0122 ,
:J
~
U
G26B
~IIOJ
.1
.1
B
lH25 A
1 DI09
1
I
0121 ,
U1:43B
~
W
B8 A
0120
]
8
1
I
~
lH44A
J
,
0119
1
J
0105
.. H39 B
I I
I37 A
0118
~B
G43 B
lH39A
J
I32 B
1
G43 A
DI03
W
Oll~
W
~
A
.:I
A
0128 1
0129
1
U1:26B
~
G37A
A
~
~B
0130
0115
:J
0131
U1:3IB
5125
5124
FIELD I
FiELOO
G310
G310
G311
G311
G312
G312
G313
G313
G314
G314
G315
G315
Figure 86. Y Transformer Drivers
Drive Line Selection
Drive line transformers, card type CIO, can drive
anyone of the four X and Y drive lines. Two C03 line
driver cards (two sections per card) and two COS gate
cards are needed to select the four drive lines which
may be energized by one drive line transformer card.
One gate card selects one of the .two sections of the
drive line transformer card, and two line driver sections select one of the two lines in that section.
In figure 86, if the lines marked with an X are selected, -44v will appear at pin 3 of the CIO card and
drive line 32 (408) will be energized.
91
4 CIO CARDS
NOTE: THE TWO CRCUITS IN THE
SELECT 16 DRIVE
LINES FOR READ
OR WRITE
DASl-ED BOX ARE BOTH
CONTAINED ON ONE CIO CARD
r-
'--,--...'-r--
~
TO 6 ADDITIONAL
C05 GATE CARDS
BIT IN S
4
S041
2 S021
T SOlO
(EACH C05 GATE CARD
SELECTS ONE OF THE
TWO CIRCUITS ON A
CIO CARD.)
~_r-L--~_ _ _ _ _ _ _ _ _ _ _ _r-+-r-~__- 4__~~~r-+-~
TO 3 ADDITIONAL
CIO TRANSFORMER
CIRCUITS
C05 GATE CARD
6
4
2
S041
S021 ~~~--~~X~---------+__r-______~______-4~~~
SOli
X
X
K712
ACTIVATE GATE
0
0
r-
:.:
0
ex
III
It:
III
l-
~
i=
~
III
I-
~
~
III
I-
~
i=
ex
0
10 110
I-
I-
Selection is shown for the X coordinate;
Y coordinate is similar.
*S050
S051
=
=
m m
LO WHEN A"O"
HI WHEN A "I"
Figure 87. Drive Line Selection
• •
340 Me
MEMORY STACK
~
DRIVERS EITHER
CONNECT OR
CONNECT TO
GROUND
Figure 88. Simplified Gate and Transformer Circuits
Since this manual is not devoterl to hask electronics,
operation of gate cards and transformer cards will be
covered very simply. To study the actual circuitry
refer to Printed Circuits Manual, #60042900.
Figure 88 oepicts simply the operation of gate and
transformer cards.
92
TERMINATING
RESISTOR
CIRCUITS CONTAINED
ON ONE SECTION OF
A CIO CARD
-
r
1
450 Mo
~_____L~~9~0~0__
M_Q____~____~____~+
D+
DB
Figure 89. Drive Transformer Operation for Read
If DA and DD and the gate are on, current will flow
in the primary and secondary of the transformers as
shown. The winding in the secondary that is tied to
pin 2 would actually be series winding, thus the -44v.
The other winding is actually series opposing, thus
there is little or no voltage or current.
,
I
OUTPUT PIN 2 = -44V, 340 Mo
ON READ LOW
+
•
OUTPUT PIN 3
L
r
CIRCUITS CONTAINED
ON ONE SECTION OF
A CiO CARD
•
I
+
+20 V
900 Ma
-,
•
PIN 4
).
+
+
+
Figure 90. Drive Transformer Operation for Write
450 Ma
450 Ma
If DB and DC and the gate are on, current will flow
in the primary and secondary of the transformer as
shown. The winding tied to pin 2 is now series aiding,
thus +44v. The winding tied to pin 3 is now acting as
series opposing, thus there is little or no current.
r
- •
+
L...-_--«:+
+
•
+
•
1
OUTPUT PIN 2
= +44V
I
WRITE LOW
OUTPUT PIN 3
L _ _ _ _ _ _ _ _ _ -.1
93
Worksheet: STORAGE ADDRESS SELECTION
1. During an RNI cycle with (P) =01571, indicate the terms that would be used within storage module 0 by filling
in the following table:
X Gate
Y Gate
X Xformer
Y Xformer
X Drivers
Y Drivers
Read phase
Write phase
2. During an RAD cycle with (F) = 20425673 and 16K storage, indicate the terms that would be used within the
appropriate module by filling the following table: (Assume that the system contains two 3309 Storage modules. )
Y Gate
X Xformer Y Xformer
X Drivers
X Gate
Y Drivers
Read phase
Write phase
3. During an ROP cycle with (F) = 30057434 and 32K storage, indicate the terms that would be used within the
appropriate module by filling in the following table: (Assume that the system contains four 3309 Storage modules.)
X Gate
Y Gate
X Xformer Y Xformer
X Drivers
Y Drivers
Read phase
Write phase
4. During an STO cycle with (F) = 40073746 and 32K storage, indicate the terms that would be used within the
appropriate module by filling in the following table: (four 3309 modules)
X Gate
Y Gate
X Xformer
Y Xformer
X Drivers
Y Drivers
Read phase
Write phase
5. For questions 2, 3, and 4, what changes would have to be made in the selected terms if the systems had contained only 8K storage? _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
r
TIME -+
II
12
\_----~~/
Up to this point, we have:
1. Set busy FF.
2. Turn on read current.
K795
PULSE
GENERATOR M39A
WRITE - LEFT BUS
E30
READ
STORAGE
K760
WRITE - RIGHT BUS
M33A
DELAY
LINE
A2
AI
GI73
L37
K796
K761
WRITE
STORAGE
CLEAR R/W G091
Figure 91. K760/76l FF
When E303 (A3) outputs a 1, the Activate Read, Gate
and Busy FF's Set.
The first tap off the delay line feeds E
(HAI2
card), a delay line amplifier. Statically 1 the delay
line is fed a constant 1 (-IOv) and thus the constant
outputs of the delay line amplifiers are O's. Now,
however, we will have a 1 out of the delay line amplifier because 0 (near ground) has been put into the
delay line by the inverted set output of pulse generator FF.
As the pulse travels down the delay line the following signals are produced:
E300, tap A4, 50 nsec
1. E300 clears pulse generator FF, thus defining the
trailing edge of the delay line pulse.
E309, tap AlO, 200 usec. 2. K760/761 (read/write storage) is set for any read
or remains clear for any write. This flip-flop is
set at this time if the memory cycle is a write into
a protected area. (Main control senses this and
changes write to read.) The protected area could
be the auto load/ auto dump area or an address block
protected by the STORAGE PROTECTION ADDRESS
switches. Attempting to set K760/761 at E
allows sufficient time for address comparison (protected addresses compared to actual addresses referenced). Setting the flip -flop at this time is necessary because K760/761 is forced clear by a pulse
occurring later along the delay line.
Figure
93. Data Bus
Read/Write Storage
Read/write storage FF (K760/761) is set by a read
signal transmitted from either processor via the right
or left bus. It is cleared at the end of a storage cycle.
The set output of this flip-flop is used as an input to Z
to data bus FFto determine whether or not the data in
Z is to be gated to a data bus.
The clear (write) output is used to determine whether
or not data is to be gated from either data bus to Z.
When K760, E312, and K797 are all 1 's, left data bus
to Z is enabled. K760, E312, and K796 enable right
data bus to Z. The clear output of read/write storage
is ANDed with G174 and inverted to provide a clear
input to the write designator bit FFs.
M38B
300-
DELA Y
LINE
~
BUS. BUS
-+
Z
Figure 92. Delay Line Time B4
Tap B4, E312:
10 Enables (Z) to the transmitters that lead to the data
bus register. (Although the information has not yet
been read into Z register, it will be read into Z
long before the data bus is sampled by the central
processor. )
2. Clears the reply FF.
Z-+ BUS, BUS-+Z E312
READ K761
TRANSM ITTERS OFF
Z
E 330
MC 6171
SELECT LEFT BUS K797
K796 SELECT RIGHT BUS
GI40
K29A}
GI41
K29B
GI42
K30A
-+-..........~--:-l
GISO
Z-+LEFT DATA BUS
M29A}
GISI
M29B
GIS2
K30B
Z~RIGHT
DATA BUS
95
""'~
AMP
F03
G401
FIELD 0 - 1
G411
FIELD 1 - - 1
G041
LEFT BUS __ 1
G051
GI51
1 __ RIGHT BUS
Figure 94. Z-Register Inputs
GI41
G061
CLEAR 1
M34A
350-
DELAY
LINE
** STROBE FIELD
0 (FEEDS
1 __ LEFT BUS
E343)
Figure 95. Delay Line Time B6
Tap B5, E310:
Partially enables G40- gates to gate the contents of
field 1 sense amplifiers to Z (only if field 1 is being
referenced). E311 is a C07 card (emitter follower)
fh
which does not invert. E343 is a C85 card which feeds
R774 (a receiver). These two cards form a strobeshaper network (figure 96). R774 outputs 0 for approximately 50 nsec during the sense -.Z time.
-0.6:"1"
L
-IOV: "0"
Jf----1 "0"
LUlU
PULSE FROM
DELAY LINE
Figure 96.
375-
DELAY
LINE
** STROBE
FIELD I (FEEDS
C5O=l
-I.IV : "0"
-I
---1"" ;~'L-.
-5.BV ="I"
Strobe-Shaper Network
E344)
Figure 97. Delay Line Time B7
Tap B6, E311:
Partially enables G41- gates to gate the contents of
field 1 sense amplifiers to Z (only if field 1 is being
referenced). E311 is a C07 card (emitter follower)
and does not invert. E344 and R775 (receiver for field
1) also form a strobe-shaper network. The theory of
its operation is the same as that of E 343 and R 77 4.
Z REGISTER AND READ/WRITE CONTROLS
Z Register
The 28-bit Z register is the storage re-storing and
modifying register. Data can be entered into Z from
field 0 or field 1 sense amplifiers and the left or right
data bus.
Read Control
During a normal memory cycle all bits of the word
referenced by (S) are rean ont of "ore storage in parallel and gated from the sense amplifiers into Z. Data
from field 0 is gated to Z by the G40X inverters while
data from field 1 is gated by the G41X inverters. The
word in Z is placed on the selected data bus, then is
written back into the storage location under reference.
9R
Write Control
When a new word is to be written into storage, (Z)
must be modified during the read phase of the write
cycle. The modified word in Z is then written back
into storage during the write phase. Five modes of
storage modification (partial writes) are possible:
1. Single -character mode - anyone of the four characters (six bits per character) of the word in Z may be
replaced by a new character.
2. Double-character mode - the lower, middle, or
upper two characters of a word in Z may be replaced by new data.
3. Triple-character mode - the upper three or lower
three characters of the word in Z may be replaced
by new data.
4. Full-word mode - a complete new word (four characters) may be plac~d in Z, then written into storage. The previous contents of this storage location
are discarded.
5. Address mode - the lower 15 or 17 bits of the word
in Z may be replaced by a new address
Storage is modified (partial write) by blocking the
input sense gates to Z for a character or group of characters during a read cycle, thus holding the corres0
LEFT
T(o(oO +\R'40
I I
J..o
I ---5.)-----_,
1<760
E312
1<797
CHAR 3
T640
B
\R""
I-I----::o---~
BUS~Z
1<740
L22
1<741
J642
CHAR 2
1<742
Jf04.1
L23
1<743
1<745
1<749
J""
CHAR
I
J'-45
1<744
L24
L27B
1<745
J ..4 ..
1<745
1<748
---------+~_+-~~I__,
CHAR 0
JM7
-------_+-~__!}-+__+___+I 1<746
L25
1<747
J .....
-------+--::0-+--+-+---,
ADDRESS
J .. 49
---------+-_+---£H>----~ 1<748
L26
1<749
G072
LEFT S BUS S
RIGHT S BUS -
*
TERM LOCATED IN MAIN CONTROL - CHASSIS I
NOTE: The Gxxx terms on this page are not gates, but
inverters whose outputs need to beT" s to enable
an input into z.
S G082
11126B
Me
WRITE
GI74
1<760
PARTIAL WRITE CLEAR E323
ponding bits of Z in clear. New data is then gated from
the data bus into unfilled bits of Z and the whole (Z) is
stored.
Write character signals determine storage modification by entering storage via R64x rank of receivers.
Table Ilshows the signals necessary for various partial writes. These signals set write designator bit FFs
(K74x/74x). The outputs of these flip-flops determine
the gating of data to Z register by selectively enabling
and blocking input gates to Z. The flip-flop outputs
control G40x inverter rank which gates data from field 0
Figure 98.
Partial Write Bits
to Z, G41x rank which gates field 1 to Z, G04x rank
which gates information from the left data bus to Z,
and G05x rank which gates the right data bus to Z.
In a full-word re-store cycle all 24 bits are read
and returned thus:
= Core
storage
(24 bits)
= Z register
97
Table 11. PARTIAL WRITES
I PARTIAL WRITE
I
BITS
WRITE CHAR 3 WRITE CHAR 2 WRITE CHAR 1 WRITE CHAR 0 WRITE ADDR
R642-R643
R640-R641
R644-R645
R646-R647
R648-R649
00-05
06-11
12-17
18-23
X
00-11
06-17
12-23
00-17
06-23
00-23
X
00-14
Word address
Character address 00-16
Character
Character
Character
Character
3
2
1
0
Lower 12 bits
Middle 12 bits
Upper 12 bits
Lower 18 bits
Upper 18 bits
All bits
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FIELD 0
~z
K741
G410
FIELD I - Z
G040
LEFT BUS_Z
G050
RIGHT BUS _
Z
Z_
G060
CLEAR Z
6150
RIGHT BUS
GI40
Z - LEFT BUS
G21 B
K743
In a read cycle, with one character changed by instruction execution, 24 bits are read. However, the
lower character (3) is not allowed to feed Z register.
Instead, the character from the data bus is allowed to
enter Z register and during the re -store cycle the
newly created 24-bit word will be stored.
-+--1~
K745 - + - - l - - ,
K 74 9
-+---i~
G23B
K 765 -+--l--t
= Core storage
(24 bits)
F36A
= Z register
F36B
K 74 7 -i-+---t
The write designator FFs are set by the central processor, depending on what instruction or cycle is being executed
The following circuitry represents the write designator FF and enabling of either the sense amplifier or
the data bus to Z register.
.. _..
.•...
'roo", ,,--_+__-_ _____+____+--___+__+_-~
·f
{}
--------------'f.,.
I'
7
\J pP e
.s ~
fl
rr~'
131
word line. To select anyone of these word lines a
driver and a gate must be enabled. To select address
74, for example, a logic translator would enable read
gate 4 while another enabled read drive 7. When the
current is applied, it will flow from -2Ov (read drive
7), through diode B along the word line, tarn i ilisiile
Ih
g !lie
I lj;jJL, through diode ·A to +2Ov (read
gate 4). When the write current is applied, write gate
4 and write drive. 7 are enabled, allowing current to
flow through the word line from diode D to diode C.
Diodes A and B are the same diode matrix as are diodes C and D. The other diode matrix serves in the
same manner except that they are connected to all of
1
the odd address word lines.
Read and Write Drivers
Mounted on either side oj' the register file (figures
130 and 131) are the read and write drive boards. The
circuits for the two are identical except for pin numbering. Figure 137 illustrates a driver and a gate.
The control signal input is the output of a logic translator. The logic translator will enabie a path from
ground to the +2Ov connected to the primary of the interstage transformer and force the transistor into conduction. The conduction of the transistors will allow
the drive current to flow from the -2Ov at the driver
+
+ 20V
4000pf
I.
TP
20V
100
22pf
J'\-
4
CONTROL
SIGNAL
IN
DRIVE
CURRENT
...,.
n------
".,
10K
GATE
-20V
+ 20V
+ 20V
15 }LH
10K
TP
4000pf
I.
8P.
f
.I.
~---~----o
DRIVE
CURRENT
....
CU'4
CONTROL
SIGNA L
IN
o~·~·
-20V
Figure 137. Gate and Driver
DRIVER
132
through the diode matrix (one diode), through the stock,
through the diode matrix (the other diode of the pair),
and through the gate to +2Ov .
conducts, Cl will bypass the current-limiting network
and allow a large initial flow of current. At this time
the current will be limited by the inductance of the
transformer
The base circuitry, R 1, R2, and C R5, provide s bias ing for the transistor and level shifting for operating
from -1. Iv and -5. 8v logic leve Is . The diode s CR 1,
CR2, and CR4 provide a means of translating S register
0
LOGIC TRANSLATOR
Four identical logic translators are used in the register file. Their purpose is to decode the output of S
register in order to enable the proper gate and driver.
A section of the logic translator is shown in figure
contents. The biasing is arranged such that if a logical
appears at the cathodes of all the diodes, a
positive voltage is applied to the base of Ql and it conducts. If the cathodes of any of the diodes have -5. 8v
(1) on them, the transistor will remain cut off. The
arrangement of the diodes and the transistor is known
as a NOR circuit. Therefore, the inputs to the trans1ator will be data.
o (-l.lv)
138.
Transistor Ql is used as a switch to allow current
to flow from +2Ov through the primary of the gate or
driver transformer to ground. Resistors R4, R5, and
R6 form a current-limiting network for the circuit,
while R3 reduces the collector voltage to prevent the
transistor from burning out. When the transistor first
o
2 - ....-----,
CRI
+20V
CR2
+
20V
1
I
-'_
I",~
I
'- - -" c- - +~,
"'I. ,~
-"t ;-~
\.
0- -
"
- _~' ~ - - -
"-
I
.... /
t
t
L -
CR3
QI WILL
CONDUCT IF THE DIGIT TRANSLATED IS A
6 AND THE GATE INPUT IS AT A ZERO LEVEL.
GATE-------~
CR4
Figure 138. Logic Translator (Section)
S REGISTER
The 6 -bit double -ranked S register (Logic Diagrams,
page 1-95) is used to hold the address to be referenced.
The first rank (SI) will send its outputs to the read logic
translators and to the second rank (S2). S2 will hold
the address for the write logic translators. The lower
three bits of SI and S2 send their outputs to the logic
translators that enable the gates while the upper three
bits go to the driver translators.
The function of S register in regard to individual instructions is explained later in this chapter.
SENSE AMPLIFIERS
The 24 sense amplifiers are type HA16 cards.
A
detailed description of their function is found in the
Printed Circuits Manual, Publication #60042900.
133
A logical representation of the sense amplifier is
shown in figure 139. The sense amplifier detects and
amplifies the O.lv output from a switching core. A
strobe pulse (sense ZI) may be applied through aninverting circuit to the AND gate in order to gate the sense
amplifiers to the Z register. If pin 4 is positive relative to pin 5 when the strobe pulse is applied, the AND
,- I
Sense line _ _~~
DIGIT DRIVERS
The 24 digit drivers are type HA14 cards. A detailed
description of their function is found in Printed Circuits
Manual. A logical representation of the digit driver is
shown in figure 140.
If transistors A and D are switched on, current will
flow from pin 14 through the digit line to pin 13. If
transistors Band C are turned on, current will flow
from pin 13 through the digit line to pin 14. In this
manner the digit driver is able to provide a bidirectional
output on the digit line. The digit drivers are in Logic
Diagrams, page 1-98.
Differential
amplifier
Inverter
Sense to ZI
-
gate will be made. Making the AND gate will send a 1
to the corresponding flip-flop in ZI register. If pin 4
is negative relative to pin 5, the AND gate will not be
made and the output of the sense amplifier will be a O.
The sense amplifiers are in Logic Diagrams, page
1-98.
-..J
Figure 139. Sense Amplifier
c
A
y
I
+
20V
.,/
I DIGIT
I
I
-20V
LINE
Figure 140. Digit Driver
o
B
Z REGISTER
Z register is a 24-bit double-ranked register that
is used for moving data into or out of the Page Index
file. Pages 1-99 through 1-102 of Logic Diagrams
show the two ranks of Z register.
Zl receives its inputs from:
1. The sense amplifiers (for reading data out of the
register file).
2. The data bus (for writing in new data).
from driver to gate but in the opposite direction.
Read
IlL...----.-J
Word li:;.:;:n~e_---I
current
Write .....------
Sense line
0
11-.-_
-----I
OVERALL SELECTION
The lower three bits of Sl are sent to a logic translator which in turn activates a gate. On the other side
of the word line a driver has been activated by a translator which received its input from the upper three bits
of :::11. Read dnve current flows from the driver to the
gate.
When the write portion of the cycle is started, the
lower three bits of S2 have enabled a gate the upper
thre~ bits have enabled a driver. Again current flows
134
Sense
l~
1
Digit current, writing a
~
Core B
0
!
!
-COreA --
Core A
.-----,
Digit current, writing a~
Figure 141. Timing Figure
1
Core B
rl----
TIMING
Figure 141 shows the overall timing and current directions for a memory cycle.
When read current is applied to the word line, the
sense amplifier will receive an input as shown onfigure
141. Note that the sense line voltage is the same magnitude for a 1 as for a 0 but in the opposite direction.
At the conclusion of the read operation the fields of the
cores at the selected address are in R direction (figure
FROM s2
REGISTER
(LOWER 3 BITS)
129).
When write current is applied the digit drivers will
also be turned on. The direction of the digit current
will determine which core will be returned to the R
state (figure 129). When writing a 0, core B receives
inhibiting digit current and core A receives augmenting
digit current. When writing a 1, core B receives the
augmenting digit current and switches while core A
does not.
FROM DIGIT
DRIVERS
FROM sl
REGISTER
(LOWER 3 BITS)
I
WRITE
BOARD
READ
STACK
FROM
s2
TO SENSE
AMPS.
REGISTER
(UPPER 3 BI TS)
FROM 51
REGISTER
(UPPER 3 BITS)
NOTE:
I. J9-J12 ARE CDC 24549707
2. J13-J16 ARE CDC 24554802
3. J17-J18 ARE CDC 24554801
Figure 142. Page Index File Assembly and Designations
135
I'OWIIIt
IIUIITOII
IDOnia.
COl 14111410
CURRENT
COMPENSATION
.. I
I
.. I
I
I
1'0
I
I
I,.
* iliAD
-
CONPU .... TOII 0"
:~~ITTf D~~:;~N::~::"O::TOII
I
I
1"
I .....
I
t:-;"'~TI
Cilil
I
TOTAL
r--T-----T----------ly
~:--------r--::-l--l
I
TWO CIRCUIT' UIID '011 0.' AM .. ""
:~~l C~~:~~~T~I~:I~O:O:·;.:~'::IIIIIT:TTAO\AL
0"
II
T"
L ____ ____ -=~D~"~N~~M~'__ ______ ~
Sit'",,";.
..
I
i
IIIIIITOfI
lOll
10.
I +lOv
I 1
04:~1
II
I
I
I
I
I
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I
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I
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+~~I
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.
IT
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CIIN
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COl'
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-lOY
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CDC!"554IZ'
IOnIO_
POW!II
IIUIITOIII
COCZ.Sl410.
I
"'.In lOW
I
I
I.
IIVZUIU:
CDCI4IU700'
IEKIf! _ Z '
I..
-~
____________
I..
'.'VZlKU
COC:Z4U4IOO
---!~
_ _ _......._ _....J
I
I
I
__________ --.J
------...:.:.:.'----'- (1
R22.!
,l",~L'
014
+?ClV
.-20"
t
TI4
/t-.~
13 r > - - - - - - I - - - ,
4
~
L'-+-----o
. TPll
12
33~--------~------------+-----~---4-~~
~n~l6~~~.~)~~~~~44
R?3
i
TPI4
+20V
-t.
20V
015
15 r > - - - - - + - - ,
Tl5
:
II ~
'--+------
>
~~
2
+
E.4
E;
(!)
LOGIC TRANSLATOR TEST POINT
(ADDRESS 01,11,21, .. ··711
I
~5
~
E/
~2
e·
TP~
e·EJ
TP02
TP04
2.4
e·G
2.6
e·EJ
~O
3~
~2
3.3
3:
3;
3.6
3/
Ef
Q2
04
07
-
TP07
II
e·E] -:G·8
e·E] !EJ·e
E)·a ~EJ· e
-
TPI2
TPII
13
-15
TPI4
TPI3
17
TPI5
~G·e
El
E!O
".0
Z.5
E.4
2/
7,5
".'
~6
E/
".3
E.e
".2
E.9
".5
".4
DRIVERS
".5
4,,3
E!O
".4
".6
Ell
"l
"l
E!2
4,.G
~I
E!2
1,0
~
".2
TPI7
E~I
READ
E;
TP05
:EJ·B
TPIO
E,.G
e
E.2
E/
WRITE GATE
TEST POINT
E:
.
EI3
READ DRIVER TO
DIODE MATRIX
CONNECTIONS
BOARD
WRITE GATE TO
DIODE MATRIX
CONNECTION
TPOO
6·EJ!- GJ8
Q9
01
T9_
TP;I
00
6
~~r8
TP02
P03
TP03
iit
TP06
~
7,1
e
EJ· e
T2 •
003~
~
-
~5
E.4
WRITE
REM GATE TO
DIODE MATRIX
CONNECTION
~~.0
~
TPOI
19
7,3
Ei6
E!5
REM GATE
TEST POINTS
READ
~o
LOGIC TRANSLATOR TEST POINT
(ADDRESS 01,11,21,· .. • 711
_
05
TP04
TP05
07
TP06
TP07
-
8·6 :' EJ·G
8·6: B·e
8·8 -: Ere
8·EJ~ EtG
8 .EJ~ Ere
TPII
TPI3
TPI5
-
GATES
II
TPIO
13
TPI2
3.z
TPI4
3.4
-~
17
1,0
~3
~5
DRIVERS
3l
3j
8·EJ~
,'P17
E~4
WRITE DRIVER TO
DIODE MATRIX
CONNECTION
DIODE MATRIX
WRITE
TYPICAL TRACE AT
BOARD
£ffi EI m
~~:~ ~~;:TSH"HIH~~O.OV
SCOPE
SETTINGS
20 V/CM - INVERTED
0.1 USEC/CM
(CHASS IS 1
20V / CM - INVERTED
NORTH
J07
~
0.1 USEC /CM
000
ADDRESS
ODD
ADDRESS
READ
~ WRITE
II)
II)
a:
~
a:
Joe
. ~
0
a:
WEST
0
III
'"
~
a
g
A4
AIO
AI2
f-
z
J05
~
EAST
.'"
0
..J
0..
EVEN
ADDRESS
WRITE
AI
'"z
I'
\
is in Executive mode.
4. The 3311 is chassis
-"'---5. The 3311 connects to the CPU via flex jumpers.
6. The 3J.J1 relays the Storage Request signal to
high aIm low core.
7. The 3311 is referenced during each storage
·f
reference if the system is in Executive mode.
" 8. The Page Inoex Fil e segments storage into 2K
pages.
9. The Page Index File is a word-organized storage unit.
)0. An advantage of all word-organized storage
x:,
units is that the same number of cores switch
P11.
12.
r:
146
F 14.
r 15.
'1 16 .
(
17.
18.
1
19 .
20.
/,
for every storage reference.
There are 24 cores on each word line.
There are .~ i.f
cores on each digit drive
line.
t :J..
The Page Index File stack consists of a cubic
matrix containing ~ x ;>., x ~ bits.
A current of 21 is necessary to switch a core.
Odd parity is used in the 3311.
Each word line passes through a given core
twice.
Two read/write cycles occur each time the~"
Page Index File is referenced.
',J
The 3311 samples ,
bits of the data bus.
If an Illegal Write is sensed by the 3311, the
Write signal is converted to a Read signal.
The address of the page index to be referenced
is obtained from the lower seven bits of the S
bus for either read or write page file.
*
:1?"
CHAPTER 6
LOGIC TIMING AND KEYBOARD ENTRY
COMPUTER TIMING
All computer operations must be timed and signals
must occur in the proper sequence. Timing is provided
by the clock and -clock pyramid and by the resynchronizing circuits which are timed by the -clock.
MASTER CLOCK AND CWCK PYRAMID
The master clock operates continuouslywhen power
is applied to the computer; it provides the timing pulses
used throughout the computer. Timing of all -signals is
determined directly or indirectly by this clock.
The Clock system :consists of a master oscillator
feeding four ranks of clock amplifiers in an oscillatoramplifier pyramid
The oscillator and amplifiers
are contained on the type COl card. The pyramid
connection and -circuit operation are discussed in the
Printed Circuits Manual, publication no. 60042900.
The oscillator operates at 8 megacycles and provides
four sine wave outputs. Two of these are 180 degrees
out of phase with the remaining two. One set of outputs
is designated even raw clock, the other set is odd raw
clock. The raw clock outputs used for timing logic are
available only from the clock amplifiers in the fourth
rank of the pyramid
Clock signals are placed on one -way AND gates as
well as mUltiple input AND gates to time the output of
control delays and single inverters. These are always
deSignated as HXXX, VXXX, or NXXX terms. When
0
o
147
the raw clock signal goes to a 0 (-3v to +lv), the inverter outputs a logicall for 62.5 nsee. The inverter
circuits clip the raw clock signal to convert the sine
wave to a rectangular wave. All odd numbered NXXX
and VXXX terms have an odd raw clock input. The
logical 1 from these terms occurs at odd time. Likewise, even numbered NXXX and VXXX terms are fed
by even raw clock and output a logical 1 at even time.
The master clock and pyramid must be tuned to a
frequency of 8 megacycles. Procedure for tuning the
clock pyramid is presented in Printed Circuits Manual.
Ranks 1, 2, 3, and 4 are ranks of amplifiers. In
terms of hardware, the circuits are the same for both
the amplifiers and the master oscillator. The master
oscillator drives two amplifiers and each amplifier may
drive four more amplifiers.
RESYNCHRONIZING
External equipment and switches provide signals
which are asynchronous to the timing of the computer
and must be resynchronized. This involves insuring
that only one synchronized pulse results from an asynchronous signal, regardless of the duration of such a
signal. In addition, resynchronization prevents the
possibility of marginal timing due to the occurrence
of runt pulses.
Resync Counter
The resync counter is composed of a free -running
chain of four control delays. This chain begins counting
when the first odd clock pulse is produced by the clock
pyramid. A 62.5 nsec pulse is produced by one of the
control delays each phase time (figure 158). Each
control delay produces a pulse every quarter microsecond.
The resync pulses synchronize signals by conditioning AND gates throughout the computer. An asynchronous signal is sampled tv form a synchronous (62.5
nsec) 1 when a resync pulse completes the AND gate.
A synchronous pulse is not produced when a runt pulse
is sampled, for this type of signal does not have sufficient amplitude to definitely indicate 1 or O. The resync
pulse occurs again in 0.25 usec. If the input has settled
to a steady 1 by this time, a synchronous pulse is produced.
INPUT TO
H070
H070
V070
H071
V071
H072
V072
H073
V073
___ = LOGICAL
ONE
Figure 160. Resync Timing
Figure 158. Resync
The first control delay of the timing chain has a threeway ANDed input.
1. N053: Odd clock slave outputs a logical one 62.5
nsec every odd phase time.
2. H071 and H072: These are outputs from the A side
of the H07X term. Their output will go to
o for 2 Y' times after the H07X term receives
an input. This is true of all control delays.
N053
H071
H072
Figure 159. Resync Input
14~
H070
V070
V074
Start
The RNI sequence provides for most manual and pro gram starts and stops. The computer may be started
by pressing GO switch if normal program operationis
desired, or by pressing SW /EN CONT switch if a sweep
or enter operation is to be performed. These switches
are mutually exclusive although they both set Initiate
Go FF (K304/305). The output of Initiate Go is timed
with a resync pulse to set the, Go sync FF. The output
of this FF then sets Go (K090/091) and the output of Go
allows a start pulse to begin an RNI to read the first
instruction of a program. (The logic discussed above
is found in Logic Diagrams, page 2-15).
The computer may also ~ started from halt by
pressing CYCLE STEP, INSTRUCTION STEP, or AUTO
STEP switches on the console. Operation of the computer in these modes is discussed elsewhere in this
manual.
D.
J302 SW
+
EN
SW7ENCoiiT - 7
08
~K070
~K012
SW/EN CONT-7
Operator
V071 (tl):
(t2)
(t3)
V070 (to):
(tl)
N072 (t2):
V073 (t3):
pushes GO, set K304/30S.
Set K078/079 (go sync).
Set K090/091 (go).
Outputs a logical 1. This is the start pulse
for the processor.
Set K092/093 (go lockout).
K090
Go Logic
H073
H072
V071
Figure 161.
V072
V076
- - - - . . I N072
K093
N072 will have only a lout at t2 after setting of
K090/091 and before setting K092/093.
GO
LOCKOUT
Figure 162. Time 2 of Resync Timing
TEST MODE
Test mode is available with the 3300 Computer for
the convenience of maintenance personnel; it performs a three-step operation consisting of Stop, Master Clear, and Go.
The repetition rate of this three-step operation
may be switch-selected at a 1 msec. rate or at an
auto-step rate. TEST MODE switches are at location 1 T23 in the main frame. The C section of the
switch card controls the repetition rate; the D section enables Test mode.
L
Stop - . MC - . Go
L-.
_ _ _ _ _--\~
J
)r---------
Turn on Test Mode
M338 and M339 = 1. Clear Go Initiate FF (K304/305)
and stop FF (K306/307).
Real Time clock (J793 = 1) or Auto Step (Y859 = 1)
Set K386/387
~M329 = 1. Set Stop FF (K306/307).
~M339 = O. Remove clear from Stop FF.
T
after 2 msec duration:
~M337 = 0, M309 = 1 (Master Clear)
I A~er 5 msec duration:
Set K388/389
~ M328 = 1. Set Fo Initiate FF (K304/305).
M339 = 1. Clear Stop FF (K306/307).
M338 = O. Remove clear input from Go
Initiate FF (K304/305).
M329 = O. Remove output of M309 from
input to J280, dropping Master Clear.
Next V071, Set Go Sync FF (K078/079).
Next V070, Set Go FF (K090/091).
Continue in
~ Go condition for time deter,
mined by Real Time Clock or
after 5 msec duration:
Clear K386/387, K388/389
M328 = O. Remove set input to Go Initiate FF (K304/305).
M338 = 1. Clear Go Initiate FF (K304/
305).
149
STATIC CONTROLS
The static controls are used to enter data from the
keyboard. These include the keyboard entry controls
and the breakpoint controls.
KEYBOARD ENTRY CONTROLS
The keyboard entry controls are used to control (1)
entry of data into C register from the keyboard, and
(2) transfer of this data to the various registers.
COMMUNICATIONS REGISTER CONTROLS
Entry of data from the keyboard to C register is controlled by C register controls which include the digit
counter, the sequence counter, the digit sequence
chain, and various timing networks.
J943
M314 -12 BIT
"'05
"Sl7
J,IO
Figure 163. Digit Counter
The digit counter is a chain of six flip -flops which
controls the entry of successive digits into C. The
counter operates by moving a combination of setting
and clearing inputs down the chain.
The various combinations are translated by the J320
to J327 translators. A translator outputs a 0 when its
inputs are satisfied. This allows a corresponding J340
to J347 term to output a 1 to turn on the proper light
driver card to light the blue background indicator in the
desk console display. This background indicator shows
the digit position to be filled next.
DIGIT
K3Z7
K;!I28
K;!I31
K329
K331
K329
K331
K;!I2~
K327
K;!I29
K325
K3Z!I
K327
Inputs
from the
digit counter
Additional digit counter
translators
K323
K3Z!I
K336
K;!IZI
K3Z3
L850 to L857 are the
light drivers for the
field digits of C register.
K321
K322
~;,'i~--
K 320
\...
K336
,j
Digit counter translators ./
J320-J327
Figure 164. C Register Enables
150
The flip-flop combinations necessary to select each
digit position are shown below.
IH301
I H303
From digit
counter
tr anslators
Table 13. DIGIT POSITION SELECTION
Flip-flops in Set State
Digit Position
7 (First to be filled for
a 24-bit entry)
6
All flip-flops clear
First flip-flop in the
chain, K320/321
First and second
Second and third
5
4 (First to be filled for
a 15-bit entry)
3 (First to be filled for
a 12-bit entry)
2
1
0
J320
J321
J322
J323
J324
J32S
J326
J327
N301
N303
N30S
N307
N309
N311
N313
N31S
N301 gates digit key
to digit 0 position of the
{ C register.
N31S gates digit key
to digit 7 position of the
{ C register.
Figure 165. C Register Digit Enables
Third and fourth
logical O. This output is used to permit gating the digit
from the pressed digit key into C register.
Fourth and fifth
Fifth and sixth
Sixth
Depending on the state of the digit counter, one of
the J32X (digit counter translators) terms nrool1ces a
J368
2A2
EI-E7
READ STO
LAST DIGIT
_
SW
KBYD ACTIVE
K336
V076
J311
J314
Removing the blocking input to the N3XX gate which
then comes up and gates the digit position in C register.
The digit sequence is a chain of three flip -flops and
a control delay.
The control delay, H301, H303 is drawn complete in
figure 166.
DIGIT SEQUENCE
DIGIT KEY
DEPRESSED
V070
K309
K312
I---o-~
DIGIT
Figure 166. Digit Sequence
Whena digit key is pressed, K300/301 (digit key depressed FF) is set. The signal is advanced down the
chain to pulse H301 which then clocks out a pulse to set
the selected digit in the digit position indicated by the
digit counter and as translated by the digit counter
translators.
The sequence counter is a pair of flip -flops which
indicate whether an odd or even number of digits has
been entered into C. When the digit key is pressed, the
first flip -flop is set or cleared depending on the state
of the second flip -flop. After the first flip -flop has
stabilized, its state is copied by the second flip - flop.
Both flip-flops are set to indicate an odd number of
digits entered.
N308 and N310 translate the state of the sequence
counter FFS. After each digit is entered in C, a pulse
is clocked from one or the other of these inverters to
advance the digit counter.
When the last digit has been loaded into C the last
SET SELECTED
DIGIT
K312
K313
J309
digit FF is set. This prevents the end -around entry of
C by breaking the input to the digit key pressed FF The
set output of last digit is gated to control delay H30S
which clears the digit counter. Last digit is cleared
Selection of a IS-bit register may be overridden by
selection of a 24-bit register. K3S4/3SS is set when
a IS -bit register is selected. If a 24 - bit register se1ection is then made before C has been fully loaded,
K3S6/3S7 sets to complete anAND gate to H30S. H30S
then clears the keyboard controls. Clearing of keyboard controls will reset the digit counter. This will
reset the digit designator field light.
when the contents of C are transferred to the selected
register. It is also cleared by a keyboard clear or a
master clear. When last digit flip-flop has set, the
pressing of any digit key or keys will not affect the
contents of C register and all digit designator field
lights will be out.
0
151
SEQUENCE
COUNTER
K334
K334
K309
K333
K335
K333
K335
N331
V076
K300
K333
K335
K332
K334
Figure 167. Sequence Counter
15
ow. . . "
Figure 168.
Last Digit
Logic
liT .I.[CTJOII
JM4
'ION
\1074
12 .IT + 'I liT J!OJ
ii'7"iI"To?
Figure 169.
12 or 15 Bit
Override Logic
V317
.1365 ."ITE STO
Register Selection
Data may be entered from the keyboard into P, BI,
B2, B3, A, and Q registers via the communications
register.
A register is selected by pressing one of the register switches on the keyboard. Selecting a register
enables the keyboard active signals, the digit indicators
(blue background lights), and the console display of C
register.
In this exam pIe manual
entry is being made
into A register.
Figure 170. Manual
Entry into "A"
152
Selecting A register
enabled the indicator
for digit 7 of C register
0
Figure 171. C Register
Display for Digit 7
Except for P register, a register may be selected
only when the machine is stopped. P register may be
selected when the machine is running or stopped and
will be displayed in both cases. When the computer is
running and P has not been selected, all keyboard
switches but STOP, READ STO, WRITE STO, and KYBD
C LEAR are disabled.
Consider manual entry into A register as an example
of register entry. This will be a 24 -bit entry, as A is a
24 -bit register. (Bl, B2, B3 and Pare IS-bit entries.)
Entry into A register will be discussed in two parts.
1. Digits from digit keys to C register
2. Transfer ofC register to Selected register (A regis
rer in example)
Entry of Data into C
Entry of data into C is performed using keyboard
switches and C register controls.
Manual entry timing is as follows:
1. Computer must be stopped in order to perform
manual register entry.
2. Press the keyboard clear switch to clear K366/
337 (last digit FF), the digit counter FFs, K332/
333 (sequence counter 1 FF), and C register.
Note: N310 = 1.
A keyboard clear is performed to initialize the C
register controls.
The A, Q, EU, or E L register (24-bit registers)
switch on the console keyboard is pressed to select
the register and activate the keyboard.
The A register is selected for the example.
Since a 24 -bit register has been selected, all digit
counter FF s are in the clear state. The digit counter
translation drops 1327 to a 0, allowing 1347 to output a
1 to the L8S7 light driver. This light driver lights the
blue background light in digit position seven of the C
register console display.
Selecting a register causes a keyboard active indication. This is required for the following timing
to take place.
Note that selecting a register will not cause a keyboard active condition if the computer is running. The
AND gate into 1313 will be broken as 1090 = 0 when the
computer is running.
READ 5TO J368
>>-
Figure 172. Keyboard
KY'BO
ACTIVE
2R&2C
15-9ITII310~~
81
I T&SA
12-81T
Tj-7~
116
M314-~--:t"i'5~
iTT
15 BIT J294
J369
.. 753
ITS5F
i2-7~
2A2
85
u
ITC5E
I T66C
i5"iiT-7
i3-7>---EJ
.1369 REAO ... WRiTE 5TO
11753 REG
Figure 173. Register Selection Logic
The following timing chart shows the entry of a single
digit into C. Format will be that of the command
timing charts. This will aid in understanding the
commanding timing charts for the instruction set of
3300 Computer. (Refer to 3300 CE Diagrams, page
2-21. )
TIMING FOR 24-BIT ENTRY
TIME
Async*
V076(t2)
TERM
COMMAND
Start
YS50
K330/301 Set digit key
pressed FF
CONDITION
REMARKS
One of the digit keys (0-7) is pressed.
Provides 30 ms delay.
(Sweep) (Last Digit)
(t3)
(to)
V071(tl)
K30S/309 Set digit sequence 1
(t2)
V073 (t3)
V070(to)
When K309 = 1, set K332/333 (first FF of the
sequence counter).
N30S = 0, N310 = 0; disables advance of digit
counter.
K312/313Iset digit sequence 2
H301
Set selected digit
153
TIMING FOR 24-BIT ENTRY (Cont)
TERM
TIME
COMMAND
CONDITION
REMARKS
Locks out double pulses. N315 outputs a 1 at
odd time to set the selected digit in position
7, (flip-flops C930/931, C920/921, and C910/
911, or digit 5, 3, or 1 if not first pass).
Operator releases digit switch.
V071(tl)
K30S/309
(Odd time)
Async
K300/301
V074 (to)
(tl)
V076(t2)
K334/335
Clear digit key
pressed FF
Set second F F of
sequence counter
When this flip-flop sets, the translation of the
sequence counter is such that N308 outputs a
1. All digit counter FFs are clear so J315
and J317 also = 1. These terms are ANDed
to set K320/321, the first flip-flop of the digit
counter.
Digit counter translation drops J326 to a 0,
allowing J346 to output a 1 to the LS56 light
driver. This moves the indicator from digit
seven position to the digit six position (or 5
to 4 or 3 to 2 or 1 to 0).
K312/313
V073 (t3)
Clear K312/313
Next digit may now be entered.
One of the digit switches (1-7) is pressed.
Provides 30 ms delay.
Async
Y850
K300/301
V076 (t2)
(t3)
(to)
V071(tl)
(t2)
V073 (t3)
Set digit key
press FF
K30S/309
Set digit sequence 1
K312/313
Set digit sequence 2
V070(to)
H301
Set selected digit
V071(tl)
K30S/309
Clear digit sequence 1
(Sweep) (Last digit)
WhenK309 = 1, clear K332/333 (first flip-flop
of the sequence counter); N30S = 0, N310 = O.
Locks out double pulses. N313 (for digit 6)
outputs a 1 at odd time to set the selected
digit in position 6 or position 4, 2, or 0 if
not first pass.
When the last digit is entered (digit 0) K336/
337 (last digit FF) is set. This prevents the
end-around entry into C register.
Operator releases digit key.
Async
V074(to)
K300/301
(tl)
V076 (t2)
K334/335
. V073(t3)
. K312/313
I
I
Clear digit key
pressed FF
Clear second flipflop of sequence
counter
IClear digit sequence 2 I.
When this flip-flop clears, translation of the
sequence counter is such that N310 outputs a
1. Advnace digit counter.
I
I Return to * for next odd digit if K336/337 is
I clear.
154
I
I'
TIMING FOR 24-BIT ENTRY (Cont)
TIME
V070(tO)
H305
REMARKS
CONDITION
COMMAND
TERM
Input occurs if K336/337 (last digit) is set.
The indicator in C register will have moved
right one digit position and disappear after
entering digit 0 position.
Clear C register
Clears digit counter
and sequence counter
N331
At this time C register will hold the data to obe placed
in A register. If the operator made an error, KYBD
CLEAR will clear C register and controls. The logic
will be initialized to the same state as when A register
was first selected.
If the data in C register is correct, the next opera-
KYBD
Sel
CLEAR A
Digit
7
P
Digit
6
Digit
5
RPRPR
Digit
4
tion required is transferring (C) to the selected register (A in this case). Figure 174 is the waveform
timing for 24-bit entry. This could be the first part
of manually enter A or Q. This will be the same also
for enter or write storage which will be discussed later.
Digit
3
PRP
Digit
2
Digit
1
RPRP
Digit
0
RPR
K320/321
K322/323
K324/325
0A-_I-_-+_ _-+_--I Digit counter
K326/327
K328/329
K330/331
~
K332/333
Jquence counter
K334/335
Last digit flip -flop
K336/337
N308
'~_~_.v
~
'/,;j...-_-I
j
N310
lJ
J315
J316
Additional digit counter
translators
J317
P =digit key pressed
R = digit key released
Sequence counter translators
~ flip -flop
set or a term r s output is 1.
Figure 174. Waveform Timing for 24-hit Entry
155
Entry of a 15 -bit quantity into C is similar to 24 -bit
entry. The major difference is that the digit counter
is set to enter the first digit in digit position 4. This
is done by setting K322/323 and K324/32S when a 15bit register is selected.
1. The computer must be stopped in order to perform
manual entry into the registers.
2. Press KYBD CLEAR switch to clear K336/337
(last digit), the digit counter FFs, K332/333 (sequence counter 1), and C register. Not e t hat
N310 = l.
3. Select P, Bl, B2, or B3 at the keyboard.
Clear
K334/33S (sequence counter 2) at 12. Set K332/
323 (digit counter FF); N308 = 1.
Set K324/32S
(digit counter FF) and set K3S4/3SS (IS-bit selection record).
TIMING FOR 15-BIT ENTRY INTO B1, B2, B3, or P*
TERM
TIME
COMMAND
CONDITION
One of the digit keys (0-7) is pressed.
Provides 30 ms delay.
**Async
V076 (t2)
YS50
K300/301
(t3)
(to)
V071(tl)
K30S/309
Set digit
sequence 1
V073 (t3)
K312/313
V070(to)
V071(tl)
H301
K30S/309
Set digit
sequence 2
Set selected digit
Clear K30S/309
Async
V074 (to)
K300/301
Clear digit key
pressed
(tl)
V076 (t2)
K334/335
V073 (t3)
K312/313
Set second flipflop of sequence
counter
Clear digit sequence 2
Set digit key
press FF
(Sweep) (Last digit)
When K309 = 1, set K332/333 (first flip-flop
of the sequence counter).
N30S = 0, N310 = 0, disables advance of digit
counter.
(t2)
V070(tO)
Lacks out double pulses. N30X term gates
M33X terms to digit position 4, 2, or 0 in C
register.
Set K336/337 (last digit) if entering digit O.
Operator releases digit key.
N310
= 1,
advance digit counter
The next digit may now be entered if K336/
337 (last digit) not set.
Input occurs if K336/337 (last digit) set.
Clear C register control
H305
V305
Async
Clear digit counter and sequence counter.
Operator presses digit key.
Provides 30 ms delay.
Y850
K300/301
V076 (t2)
REMARKS
Set digit key
Press FF
(Sweep) (Last digit)
(t3)
(to)
Iv071 (U)
1
K308/309
(t2)
V073(t3)
K312/313
V070(tO)
H301
156
I
Set digit sequence 1
Set digit sequence 2
Set selected digit
¥lh~n K~oq
= 1 01~::t-r K~~2/~~~ (fi-rRt flip-I
flop of the sequence counter).
.
N308 = 0, N310 = O.
I'
TIMING FOR 15-BIT ENTRY INTO B1, B2, B3, or P* (Cont)
TIME
V071(tl)
TERM
K30S/309
COMMAND
Clear digit sequence 1
Async
V074(tO)
K300/301
Clear digit
key pressed
(t1)
V076(t2)
K334/335
Clear second flipflop of sequence
counter
CONDITION
REMARKS
Locks out double pulses. N3 OX term gates
M33X terms to digit position 3 or 1 in C register.
Operator releases digit key.
When this flip-flop clears, the translation of
the sequence counter is such that N30S outputs
a 1 advance digit counter.
The indicator in the C register will have moved
right one digit position.
Return to ** for next digit •
...
157
MANUAL ENTRY TIMING Worksheet: IS-Bit Register
In the following chart indicate state of flip-flops and output of the terms listed as five digit keys are pressed
sequentially.
Digit 4
Me
Sel P
P
Digit 3
R
P
Digit 2
R
P
Digit 1
R
P
Digit 0
R
P
R
K320/321
K322/323
K324/32S
K326/327
K330/331
K332/333
K334/33S
K336/337
N30B
N310
J31S
J316
J317
P = Digit key pressed
R = Digit key released
~
= flip-flop set or a term's output is 1.
Figure 175. Waveform Timing for 15-hit Entry
158
Transfer Sequence
After data has been entered into C, it must be transferred to the selected register. Pressing TRANSFER
initiates the transfer sequence. This sequence is performed using the manual timing chain and the keyboard
controls (Logic Diagrams, page 2-19).
.AIT
PR lOR I TY
Figure 176. Transfer Logic
1/074
J
For transfer to A or Q; press TRANSFER to set
transfer FF. The signal then passes down the chain
of flip-flops to set keyboard bus priority.
V071 (tl): Set K302/303 (transfer).
(t2)
(t3)
V074 (to): Set K310/311 (transfer lockout).
(tl)
V076 (t2): Set K358/359 (wait priority).
V073 (t3): Set K314/315 (enable C register).
The processor must be stopped for manual entry
into a register. Main control will not be using the bus
system at the time but the block control could be using
it. An input or output operation could be taking place
even with the processor stopped. Since DB register
will be used during the transfer sequence, it will be
necessary to request the bus system and wait until
priority is granted.
Priority granted is indicated by setting of K342/343
(keyboard bus priority).
(to)
V075 (tl)
If K210/211 (block control bus priority) is
set, test again at resync tl. If K210/2ll
is clear, set K342/343 (keyboard bus pri0rity) and continue. When K342/343 is
set, gate (C) to the C7X2 inverters. Force
the EXX2 inverters to l' s •
301
J 332 = (go )(SW+EN)(block control priority )(wait priority)(read + write storage).
The flow for manual entry to A register is: Digit
keys to C to C7X2 to Ui3R to r4 to X to adder to rO to A
register. Trace this path on the block diagram.
Setting of K342/343 (keyboard bus priority) drives
I975
1657 STORE INTERRUP~
TRANSLATION
READ
+
.R'TE
STO J369
Figure 178. C Register Enables
J332 is the setting input
that will be used.
V01!5
-u-----<-----< KYIO IuS ,..tlORITY
oI'S32:
Z351
N051
.1350
~2.10
1(341
use
J348 to a logical O. J350 will output a logical 1 enabling the clear side of C register (C) to the C7X2 inverter rank.
The J350 term's output of a logicall will disable the
inputs to the EXX2 inverter rank, the output of which
will be logical l' s. N440 will be one of the gating terms
which gate C7X2 inverters to DB register.
Figure 177. Keyboard Bus Priority
159
I'~O
(INTE,UWPT
TRANSLATION)
Select A
Select Q
Me
oJ••'
Figure 180. AQ Entry Logic
,
a-J
(t2)
V073 (t3):
V310:
I
I
i
~
Input to H310.
Clear K310/ 311 (transfer lockout) and
K358/359 (wait priority); setK568/569 (enter A) or K566/567 (enter Q) and K570/571
(F1 to F2).
Setting of enter A FF or enter Q FF will force a 20
or 21 into arithmetic register F2. The arithmetic section will simulate a load A or load Q instruction.
Figure 179.
DBR Enables
MANUAL TIMING CHAIN
V073
J361 - READ
J332
+
WRITE STO
J308
Figure 181. Manual Timing Chain
V311
V312
V313:
V314:
V126:
V315:
V316:
160
Input H400, Input H126.
Input H401 (clear DBR)
Set KI04/105 (start arith 2)
Clear DBR, Input H440.
EXX2· C7X2 in DBR. The arithmetic section
will execute a load A or load Q sequence, DBR
to X to A or DBR to X to Q. (Arithmetic timing is discussed in chapter 12.)
J331
J361
V317:
Clear K342/343 (keyboard bus priority),
clear C register and its associated controIs, and clear K336/337 (last digit).
Async:
Operator releases TRANSFER.
V071 (t1):
(t2)
V073 (t3):
Clear K302/303 (transfer).
Clear K314/315 (enable C to selected register.
If the register selected is Bl, B2, or B3 the timing
for the transfer sequence will be the same to V310
time.
The following timing is for manually entering a B
(index) register during V3I0 through V3I7 time.
Operator presses TRANSFER. Transfer timing is
the same as for A register.
R E-AO S TO SYNC J207
C--2~Bb
'5 BIT ..1294
K"IBD ACTIVE J396 oo01~---li
2~75
V312
C102
F354
1:001
C112
ClERR Bb Fe. 08
11018
..1285
!'Ie
-o>-+-,- - - - - - ,
ClR Bb
BKPT l.OCKOUT K136
Rap K085
11006
(511 .0-511.3 J FII20
(AFlITH BUSY)
F356 ~2~96
N295 2~73e
F021
-O-r;::t:====~41l Z~O
1:002
C1U
ii1
f351
B2
F353
F031
IOO'
C1U
V3I0: Input H24I (clear B).
N240
N270
Figure 183.
N211---....J
7ci
F368
IU.SUIIE 195Z
BOP V9e. 0
RES'1NC
F355
If the register selected is P, timing for the transfer
will be the same as manually enter A to V310 time.
The following timing is for manually enter P register
from V3I0 to V317 time.
i3
Figure 182. B Register Entry Logic
One of the terms F35I, F353, or F355 will have a
o for its output. This is caused by pressing the respective Bl, B2, or B3 button on the keyboard when
selecting the register.
V311:
V312:
V313:
V314
V315
V3I6
V3I7:
B Register Enables
N241 - - - - - - -
Clear B (index register).
Input H245 (C to Bb).
C7X2 to Bb. Static enable for
Same as for enter A register.
C to
C7X2.
V310
V311
V312: Input H2I5 (clear PI).
V313: Clear PI, input H210 (complement to PI).
V314: C7X2 to PI (static enable for C to C7X2). Input H221 (PI to P2).
V315: PI to P2 is a forced transfer to equalize a tworank register.
V3I6
V3I7: Clear K342/343 (keyboard bus priority), clear
C register and its associated controls, and
clear K336/337 (last digit).
KYBD ACTIVE J314
P SELECTED M318 - - - - , _ - -_ _ _ _ _ _ _ _ _ _ _---,
READ STO SYNC J207
K957
N060
K959
J711
MC J281
V075
AUTO LOAD + AUTO DUMP J050
AUTO LOADI DUMP SYNC K038
N232
N221
N223
N225
N227
MC J285
Figure 184. P Register Entry Logic
N229
Figure 184
161
Bit 0
Bit 0
PI
C702~ POOO
N210
N277
POOl
P2
H
P500
......-------
'-----~
P501
"-------'
N221
Figure 185. P Register Enables
Review of Transfer Sequence
After data has been entered into C, it must be transferred to the selected register. Pressing TRANSFER
initiates the transfer sequence. This sequence is performed using the manual timing chain and the keyboard
controls (Logic Diagrams, page 2-19).
For transfer to Bl, B2, B3, or P, press TRANSFE R switch to set transfer FF. The signal then passes
down the flip -flop chain to set keyboard bus priority.
H3I0 is pulsed to start the manual timing chain. As
162
the signal passes down the timing chain: DB register
is cleared. Bb (if selected) is cleared. Contents of C
is gated to DB register. PI (if selected) is cleared.
Contents of C are gated to PI or to selected B register.
PI is gated to P2 (if P is selected), C register and controIs are cleared.
For Transfer to A or Q: Press TRANSFER to set
transfer FF. The signal passes down the flip -flop chain
to set keyboard bus priority. H3I0 is pulsed to start
the manual timing chain. As the signal pas se s down the
timing chain: Enter Al FF is set and F2 register is
forced to a 20 (function code for load A) or enter Ql FF
is set and F2 is forced to a 21 (function code for load Q).
DB register is cleared; (C) is gated to DB register. The
arithmetic timing chain is started. X and A2 registers
are cleared. DB register is gated through 14 to X; nothing is gated to A2. (X) and (A2) begin to propagate
through the adder. C register and its controls are
cleared. Al or Ql is cleared. (X) is gated through II to
Ql or the STI:Infrom the adder is gated to Al through 10 .
KEYBOARD ENTRY Worksheet
1. Indicate the state of the digit counter FFs for each position of C register by filling in the following chart.
K320j321
Digit
Digit
Digit
Digit
Digit
Digit
Digit
Digit
K322/323
K324/325
K326/327
K328/329
K330/331
7
6
5
4
3
2
1
0
2. Indicate three manual operations which will cause
C register to be cleared.
9. What is the significance of the preceding answer
during manual register entry operations performed
at the keyboard?
3. With a select register key pressed on the keyboard,
what condition must exist in order to obtain_ a keyboard active status?
10. With the computer stopped and a keyboard master
clear already performed, list the sequence of
switches that must be pressed to place the quantity 03,000,000 into Q register.
4. What is the function performed by K336/337 (last
digit FF)?
11. What prevents simultaneous selection of more
than one register at the keyboard?
5. Briefly describe the need for flip-flops K354/355
and K356/357.
6. What function is performed by the flip -flop specifled at the times given?
P Register
Previously Selected
Resync
Resync
Resync
Resync
Resync
A Register
Now Selected
T2
T3
TO
Tl
T2
12. Why is it necessary to obtain bus priority during
a transfer sequence (i. e ., what malfunction could
occur if bus priority were omitted)?
13. List the operations that occur within the program
control section as a result of performing a master
clear at the keyboard. (Assume that the machine
is stopped.)
14. Under what conditions can go FF be set?
7. What are the transfer operations between C register and the register selected at the keyboard?
8. With the keyboard active after the computer has
been stopped and A register selected, what would
occur if TRANSFER were pressed and released
twice in succession?
14. Under what conditions can go F F be cleared? (Inelude the output translation for J071.)
-----------------------163
MANUAL READ STORAGE
Read storage enables the operator to monitor the
contents of one particular storage location while the
computer is either running or stopped.
During a read storage operation the storage location
set on the BREAKPOINT Address Selector switches is
read and its contents displayed in C register. This
location is continually monitored at a rate determined
by the auto step oscillator.
The command timing chart on the following page is
for a manual read operation. Refer to Logic Diagrams
as you progress through the operation.
To perform read storage:
1. Set the address to be referenced on the BREAKPOINT
Address Selector switches. This is an address in
either main memory or one of the 64 locations in
register file memory.
2. Set the Mode Selector switch to STO if referencing
main memory or to RE G if referencing register
file memory.
3. Press keyboard switch READ STO.
4. When the auto step oscillator puts out a signal,
transfer FF is set. If the computer is running there
is a delay while the current instruction is executed;
if the computer is stopped there is no delay. The
contents of the designated location are read and
displayed in the C register by use of the manual
timing chain and controls. When the data has been
displayed, normal operation continues. (If the
computer is not running, nothing occurs.) When
the signal from the oscillator again comes up, the
cycle is repeated. The designated location is continually monitored at the auto step rate until another keyboard switch is pressed to release READ
STO.
Table 14. READ STORAGE TIMING CHART
TERM
TIME
COMMAND
CONDITION
REMARKS
Set the BREAKPOINT Address Selector
switches to the address to be referenced.
(This may be a main memory address or one
of the 64 registers in the register file.)
Set the Mode Selector switch to STO to reference main memory or to REG to reference
register file memory.
I
Async
Press keyboard switch READ STO
V073,
N319
K316/317
Transfer FF clear
Set read storage sync (puts J368 to a 1).
V071
K302/303
M358 = 0
Set transfer when the auto step oscillator signal goes to 1.
V074
K310/311
K314/315 clear
Set transfer lockout.
V076
K358/359
K314/315 clear
Set wait priority .
-----
Computer running
Wait until the instruction currently being processed is completed.
CUlllpULCl
RNI next.
Set K340/341 viet J301
or
via keyboard bus request.
Computer stopped.
Set K340/341 via 1357.
----
V082,
V084,
V086
V072
161
IK340/341
0
K340/341
I
Ull1llng •
READ STORAGE TIMING CHART (Cont)
TIME
COMMAND
TERM
V073
K314/315
Odd
time
K342/343
CONDITION
Set enable C to selected register.
K210 = 1
Set keyboard bus request if block control does
not have bus priority.
Transmit read via T655.
Gate breakpoint address (M6XX and M7XX)
to EXXS, from EXXS to T6XX transmitters.
Hl17
K212/213 clear,
no register
selected
Keyboard operation obtains bus priority.
Clear
K310/311
K342/343 set
Clear transfer lockout.
Request bus
Transmit read
Transmit storage
address on S bus
N050
and
V074
Clear
K35S/359
Vl17
REMARKS
Clear wait priority.
Set
K212/213
Set
Kl16/117
Even
time
N050
Hl15
Vl15
K012/013
Transmit a storage request to the selected
module via one of the T65X transmitters.
Enable data bus
Set K012/013 to lock out multiple pulses.
---1--------
Main control now waits for the selected storage module to provide a reply.
Async
R555
Reply received and used as an input to the
resync circuit.
V061
H310
Reply
Resynchronized reply provided to start the
manual timing chain.
V310
V311
K004/005
V314
K340/341
Set address mode
(word)
V311-V314 provide idle time while the word
is read from storage and placed on the data
bus.
Clear keyboard bus request.
V315
V316
H317
Clear C and controls
V316
H401
Clear DB register
165
READ STORAGE TIMING CHART (Cont)
!
I TIME
TERM
V317
K012/013
Clear storage request lockout.
V317
Clear
Kl16/117
DB and C registers are cleared. Clear storage request.
N401
H410
EXX2 to DB register
V317
Clear
K342/343
H318
Direct
COMMAND
REMARKS
CONDITION
E XX2 to C
Clear keyboard bus priority.
N41X
Gate the data from the bus into DB register
(EXX2 to DB register).
N32X
Gate the data from the bus into C register
(EXX2 to C).
=0
V071
Clear
K302/303
Y858
V073
Clear
K314/315
K302/303 clear
Clear transfer when the auto step oscillator
signal goes to a O.
Clear enable C to selected register.
If processor is running when K342/343 is
cleared (V317 time), program control may
obtain the bus and continue processing instructions. Read storage again occurs on the
next cycle of the auto step oscillator and will
continue until a keyboard switch is pressed
to realease READ STO.
MANUAL WRITE STORAGE
Write storage enables the operator to store information in one particular storage location in main memory
or in register file memory. Write storage may occur
while the computer is either running or stopped.
During a write storage operation, information contained in C register is stored in the location specified
by the BREAKPOINT Address Selector switches. Storage occurs when TRANSFER is pressed.
The command timing chart on the following page is
for a manual write operation. Refer to T,ogic Diagrams
as you progress through lhe operation. Then answer
the questions following the chart.
To perform write storage:
1. Set the address to be entered on the BREAKPOINT
Address Selector switches. This is either an address in main memory or one of the 64 locations in
166
register file memory.
2. Set the Mode Selector switch to STO if referencing
main memory or to REG if referencing register file
memory.
3. Press keyboard switch WRITE STO.
4. Load the data to be stored into C register.
5. Press TRANSFER.
6. If the computer is running there is a delay until the
current instruction has been executed; if the computer is stopped, there is no delay.
The manual timing chain and controls are used to
store the data in the designated storage location. Then
normal operation continues. Write storage may be
performed again by pressing TRANSFER. Another
keyboard selector switch must be pressed to release
WRITE STO.
WRITE STORAGE TIMING CHART
TIME
TERM
COMMAND
CONDITION
REMARKS
The address to be referenced must be set on
the BREAKPOINT Address Selector switches.
The Mode Selector switch must be set to STO
or REG.
WRITE STO is pressed.
V073,
N319
K318/319
Transfer clear
Set write storage sync (puts J365 to a 1).
Async.
The data to be stored is loaded into C register.
Async.
Press TRANSFER.
V071
K302/303
V070-4
K310/311
V072-6
K358/359
Set transfer.
K314/315 clear
Set transfer lockout.
- - - - r------ - -
Computer running
Set wait priority.
Wait until the instruction currentlybeingprocessed is completed.
V082,
K340/341
V084, or
V086
Computer running
RNI next
K358/359 set
Set K340/341 via J301
or
via keyboard bus request
V072
K340/341
Computer stopped
Set K340/341 via J357.
V073
K314/315
Odd time K342/343
N051
Even
time
N050
H117
V117
K212/213
Set
K116/117
/V070-4
Clear
K310/311,
Set enable C to selected register.
Request bus
K340/341 set
K210 = 1
Obtain bus priority if block control does not
have bus priority.
Transmit write
Transmit a write signal to storage via T655.
Transmit write character designators
Transmit write character designators to storage via the T66X transmitters.
Transmit storage
address on S bus
Gate the breakpoint address to EXX8, EXX8
to T6XX transmitters.
No register selected
Storage request
Transmit a storage request.
Clear transfer lockout.
167
WRITE STORAGE TIMING CHART (Cont)
I TIME
TERM
COMMAND
CONDITION
Clear wait priority.
K358/359
Even
time
N050
Hl15
Vl15
K012/013
H400
KOO4/005
REMARKS
Set lockout to prevent multiple pulses.
Set address mode.
N400
H401
Clear DB register
N407
H440
CXX2 to DB register
DB register is cleared.
N440
CXX2 is gated to the DB register «C) to CXX2
was enabled earlier), (DBR) to the T5XX data
bus transmitters. Force EXX2 to output Is.
----
Wait for a reply.
Async
R555
V061
H310
Reply received by resync circuit.
Reply
Resynchronized reply provided to start the
manual timing chain .•
V310-V314 provide idle time while the data
on the bus is being accepted by the storage
module.
V310
iV314
Clear keyboard bus request.
K340/341
V315
V317
Clear
K012/013
Kl16/117
Release bus
Drop storage request
V317
Clear
K342/343
Clear keyboard bus
priority
Program control may now continue normal
program execution if the processor is running.
Clear C
N33X
READ STO, SW, EN, KYBD OFF, or a register switch must be pressed to release
WRITE STO.
Async
V073
1.68
Clear
K318/319
K302/303 clear
Clear write storage sync.
TRANSfER
GO
SWEEP
GO
SW
.1092
K353
EN K350
SW K352
~V316
.1356
N072
K353
NH2
N 224
BLOCK P
N 226
CIR. pi
N228
KEYBOARD BUS
PRIORITY
SWEEP
K353
H 31S
N320 }
N 322
N 333
N335
N 337
l N 339
}
CI.
N 324
C
N 326
E XX2- C
Questions on Manual Read/Write Operation
1. List the steps necessary to allow you to observe the
contents of location 20603 while the computer is
running and while the computer is stopped.
Running
Stopped
Enter Page Index File Sequence -- timing begins
with Enter PF switch depressed and C equal to the
quantity to be entered.
Depress TRANSFER
V07l: Set K302/303 (Transfer)
V072
V073
V070/V074: Set K3l0/3ll (Transfer Lockout FF)
V07l
V072/076: Set K358/359 (Wait Priority FF)
N072/K35l: Set K340/34l (Keyboard Bus Request FF)
(if Go) (start here for Go)
*N05l/V073: Set K3l4/3l5, Set K342/343 (Keyboard
Bus Priority FF)
N050: Input Hl17
Vl17: Set Kl16/ll7 (Storage Request FF) Set K2l2/2l3
(Block Control Priority 2 FF)
N050: Input Hl15
Vl15: Set K012/0l3 (Storage Request Lockout FF)
Input H400
170
2. If you want to change the contents of location 23 in
the register file, what steps must be performed?
List in order the buttons that must be pushed and
the operations that must be performed.
N400:
N40l:
N440:
N4ll:
Input H40l
Clear DBR, Input H440
C7X2 to DBR, Input H4ll
Set K2l4/2l5 (DelayedSTORequest FF) Transmit a Storage Request to the Multiprogramming
module.
V06l: Resynced Storage Reply, Input H3l0
V3l0: Clear Block P K200/20l (first time)
V3ll
V3l2
V3l3
V3l4: Clear K340/34l
V3l5
V3l6: Input H307
N239/V3l7: AdvanceP2, Clear: K012/0l3, K116/ll7,
C; Input H308; Clear: K2l4/2l5, K2l2/2l3,
K342/343; Input H220.
N220/V308: P2 to Pl, Set K340/34l if Go and return
to *.
SELF-EVALUATION QUIZ ON CHAPTER 6
TRUE OR FALSE OR FILL IN THE BLANKS
1. A different card type is used for the master
clock and the clock amplifiers.
2. One cycle of the master clock defines one phase
time.
3. The clock outputs are available any time power
is on.
4.
The output of the resync network is available
only when the computer is running.
5. For a sweep continuous operation the Go FF will
be set.
6.
The correct sequence for Test mode is Master
Clear, Go, then stop.
7.
The Test mode repetition rate is switch-selectable at 1 ms or at an auto-step rate.
8.
If a change in selection is made from a 15-bit
register to a 24-bit register, the background
indicator will move from digit position 8 7 to 84 •
9.
The C register is part of the transfer path for all
keyboard operation.
10. The presence of the background indicator specifies which digit position will be entered when the
digit key is depressed.
11. The C register is the only register whose contents may be displayed when the computer is running.
12. When K342/343 is set, the keyboard has bus priority.
13. During the B2 manual entry sequence,
----will be a 0 to allow gating from C to B2.
14. A P1 to P2 transfer is not necessary during manual entry into P.
15. The Arithmetic timing chain is not started for
manual entry into A or Q.
171
CHAPTER 7
READ NEXT INSTRUCTION SEQUENCE
FOUR MAJOR FUNCTIONS
The 3300 Computer has four major storage sequences' RNI, RADR, ROP, and STO. The first seque nee , RNI (read next instruction) has four main
functions:
1. To read an instruction word from storage and place
the instruction in F register.
2. To insure proper updating of P register.
3. To sense for all types of interrupts.
4. To start/stop.
Let's consider the first function of RNI, to read an
instruction word from storage and place it in F .
In order to visualize the data flow path for the address look at figure 188. Notice the heavy black line
originating at the P register. This line defines data
flow for the address.
Now let's consider the data flow path for the instruction word coming from storage. Again look at figure
187, but this time notice the heavy dashed line originating at Z register of module o. This line defines
the data flow path for the instruction word.
The second function of RNI is to insure proper updating of P register. P may be updated at times other
than when in RNI, but RNI must always update P. Four
cases to be considered in updating Pare:
1. P + 1.
2. P + 2. (SKIP)
3. Jump.
4. Block advance P.
173
BLOCK CONTROL
MAtti CONTROL
10 :IIO CHAMS
CHANNEL
REQUEST
"""
A
8
!
E
E'
COIITIK
c~u~~
ADD!! 'ITS
0'-10
Z.
•
IE
I flTEll""T IUS
Figure 187. Data Flow Path
Each case will be discussed in detail at V014 time of
RNI sequence in this text.
The third function of RNI is to sense for all types of
interrupts. This includes powerfail, illegal write,
STOparity error, normal interrupt, andtrap sequence,
all of which will be discussed in detail in chapter 11.
Note that RNI timing assigns priority to Interrupts.
The RNT times associated \vith these are:
1. V004 - Sense for illegal storage reference, STO
parity error
2. V006 - Sense for power fail
3. NOlO - Sense for normal interrupt
4. V080 Sense for trap
174
The fourth function of RNI is start/stop. When GO
on the keyboard is pressed an RNI is normally the first
sequence entered. The computer may be stopped by
clearing go FF • With the exception of a stop during
cycle step or after a storage parity error, all stops
are m::loe at the end of an instruction. A stop will occur:
1. When a program stop is required.
2. After one instruction is executed i.n jnstruction step
mode.
3. When breakpoint stop occurs.
4. When the ge sync FF is cleared by pressing STOP
on the console keyboard.
5, After. one memory sequence is executed in cycle
step mode.
F
REGISTER
I/O CYCLE
BK PT SWITCHES
[lPROG. STATEl][( RNI+ RAORl+
(ROP+STO + BOP OP. CY.)(O=-~SR=-=S:-::E""'L=EC?!c:=
+ (STO 8
RTJ)]
EXECUTIVE
+
MONITOR [(RNI+RADR)+(ST08RTJ)+
(ROP+STO+ BOP OP. CY.)(OSR SELECTED)~
===::::....,::===""~~10::O::::9~~'""=8.::.::.::.::.::.::.:::;:.::.::.::.::.::-=oq3,
INPUT TO RELOCATION
PAGE FILE
23
00
12 "
000
001
z.
Zo
176 L . -_ _- ._ _- - ' -_ _- - ._ _--..II77
I~--+_--- ADDER (NO END AROUND CARRY)
:::-:::::;~=:::==::::::;:::=====09~
TO
MODULE
OUTPUT FROM RELOCATION
8K
SELECT
COORDINATE
SWITCHES
ADDRESS
~-----~>
STORAGE
REQUEST
RIGHT OR LEFT
Figure 188.
STORAGE
S BUS
---6) + 01.0 +
~;~~ (77.5X)(.55)+(77.6)
VOIl
(XI.X)+77.7+55.0(XOO)
VI20 V960 BDP RESYNC
10.1-10.7
_ _ _ _ F510
GO LOCKOUT K092
~~~~RNI LOCKOUT
K002
2S12A
2SIIA
K0031------.
F558 77.0 + 77.1
VI71 BLOCK CONTROL REPLY
INITIATE RNI
VI03
01. (I-3)+ (03-05)+(10.1-10.7)+(13.4 - 13..7)
F416
HOl6
_~~~=;::====L=_=_=_=-=-=-=-=-=-=:-fI~.r~::H~0~1~2~_-_-_-~--1
02+(l1-133)+(l4-17)+53X(XOO)+[55.(XOO)+70J[TRA~ F510
BDP"INST
NI51
J 140
F701
2POI
2P04
2P05
2Q02A
2QIOA
END OF ROP
10.0+34
START FROM {N072
DEAD STOP
~r~~
INT+ PWRFL+TRAP JI40
RNI K081
'"'"'KY-:-::B=D-::B=-U--S--'RE~Q K 340
REQUEST
,..-L--L-....L..:;BUS
KOOO
2Q44A
F311 01 INDEXED
F500 RNI NEXT
voa2 END RADR
KI02
2Q45BA
KI03
NOOO
Figure 192. Initiate RNI Logic
UPDATE P
o
o
Initiate RNI, Request the Bus System
Update P.
The P register holds the address of the current instruction or the address of the first instruction at V014
time. At this time RNI must insure proper updating
of P register. The four cases to be considered are:
1. p + 1.
2. P+2(skip).
3. Jump.
4. Block advance P.
To execute a P+l, refer to figure 193 and consider
this tiilling:
17R
V014: Set KOOO/OOl, input H23l.
N231: Advance P2 (+1), input H220.
N220: P2" Pl.
To accomplish a P + 2 the skip FF (K10S/109) must
be setbefore V014 time. Instructions 04 to 10.7, 52,
71 to 76, 77.0 to 77.4, and77.6 provideforP + 2when
a certain condition exists. For all but the 7X instructions the skip translators (logic diagrams 2-13) determine if a skip condition exists. For the 7X instructions the skip condition is tested in the interrupt or
block control sections. When a skip condition exists
during the execution of an instruction with skip capabilities, skip FF will be set. To understand a P + 2
refer to figure 193 and consider the timing below. Note
that a skip (P + 2) adds 4 0 times to the RNI sequence.
V014:
N239:
N226:
N229:
V014:
KIOS/I09 (skip) is set.
Do not set KOOO/OOl; input H23l.
Advance P2 (+1), input H220.
P2 - . PI, input H229.
Clear KI08/l09 (skip); input H012.
Set KOOO/OOl; input H23l.
SKIP
KIIS
-
r-.
KIOS
f-+
KI09
REQUEST
BUS
r--a.
KOOO
NOOO- ~ KOOI
INITIATE
RNI
4
ADVANCE
HOl2
p2
p2~pl
H307
~.
H014
I VOl4
BLOCK pT·
K200
JUMP KI06
~H220
H23J
N239
N231
K200
KI20
(~H217
1
N220
INTERRUPT SYNC
f--
N207
N222
N233
N224
N235
N226
f---
N237
Figure 193.
Update P (+1, +2) Logic
N239: Advance P2, input H220.
N226: P2 - . Pl.
next RNI. To understand how a jump is accomplished
refer to figure 194 and consider the timing below:
To accomplish a jump, the jump FF (Kl06/l07) must
be set before V014 time. The instructions OO.X-03.X
and 70.(4 to 6) have jump capabilities. For setting of
jump FF refer to Logic Diagrams, page 1-3. Executing a jump will not increase the time required for the
V014: Set KOOO/OOl, input H2ll.
N211: S~t PI, input H230.
P3.
N230: Fl ..... Pl, input H221. P2
N22l: Pl~P2.
BLOCK P
K2o-0
K201
LI~
HOl2
HOl2
F ----'pl
SET -pI
START RNI
VOl4
pi -----'p2
9 H221
:J H230
N211
N230
N221
N213
N232
N223
N225
p2 ----.p3
JUMP
KI06
J080
KI07
K952
KI07
t
N207 CLR
N227
~ H750
F
Figure 194. Jump Logic
179
To accomplish a block advance P the block P FF
(K200j201) must be set before V014 time. Block P will
be set for:
1. Master clear.
2. Manual entry into P register.
3. Console switch DISABLE ADVANCE P pressed.
4. Instructions 06 and 07 .
When block P sets, inputs to H231 and H2l1 (Logic
Diagrams, page 2-47) will be disabled. Therefore,
P + 1, and P + 2, cannot be accomplished.
1. P register - The address in P specifies location of
instruction to be read in an RNI sequence. The address from P will always be a word address.
2. F register - The contents of F specify location of
the operand for an ROP sequence J location of the
address for an RADR sequence, or address at which
a word is to be stored in an STO sequence. (Each
sequence is discussed in detail in its own chapter
in this manual.)
3. S2 (current address register) in block control - An
address is provided for block control access to
storage.
Obtain Bus Priority
NaSI: Set Kala/all (main control priority) if block
control does not have priority. Input to H220
and advance P2 (Logic Diagrams, p. 2-47) except first time after a master clear, jump, etc.
If K211 = 1, repeat preceding test at the next
NOSl time because block control has priority"
If K209= 1: Set KOI0/0ll (program or main
control priority), gate PI to EXXS to T6XX to
S bus. This places an address on the S bus.
Gate EXXS to EXX7 to EXX6. This allows for
generation of the proper module request.
T655 (READ) is off. (This absence of a write
signal is in fact a read signal to storage. )
NaSa: Input to H 117 .
4. M6XX - M7XX inverter rank - The BREAKPOINT
Address Selector switch provides an address via
this rank during a read / write storage operation.
Breakpoint operations are discussed elsewhere.
Either a character address or a word address may
be provided by Fregister. P and M6XX-M7XXmay
provide only a word address. S2 will always provide a character address.
Addresses from these four sources are brought into
the EXX8 inverter rank. The address is gated into
EXX8 from the desired source by the WOXX gates. The
complement of the storage address is then transmitted
from EXXS to the relocation chassis via the T6XXtransmitter rank.
Setting Kala/all indicates that main control has bus
priority. Setting KOIO/OII enables (P) to the S bus (see
figure 204for the flow path). The address on the S bus,
now available to storage, is the address of the next instruction. (Note that if block control were using the
bus system Kala/all would not be set until block control lost its priority and released the bus by clearing
K20S/209. )
REQUEST STORAGE
CD Initiate RNI, request the bus system
Address (S) Bus
The S bus (Logic Diagrams, page 1-19) provides a
path for transmission of a storage address from main
control to a storage module.
DISABLE
PARITY
+
@ Update P.
CD Request storage.
PARITY ERROR
MOVE CYCLE I
REQUEST BUS
JOl2
Z356
KOOI
MAIN
CONTROL
PRIORITY
KOIO
N005
KOII
REGISTER SELECTED J335
KYBD BUS PRIORITY K34-:;-3~;P-...-L---, VI17
Figure 195. Bus Priority Logic
N050
K212
Q40A
FOR RNI, P REGISTER- POOl
FOR RADR, ROP, STO _ _ _... .f00 I
F REGISTER
FOR INPUT/OUTPUT OPERATI~S201
CURRENT ADDRESS REG. S
FOR READ/WRITE STORAGE • .. M601
BKPT SWITCHES
POll
FOil
J981
S211
M611
P021
F021
S221
KYBD BUS PRIO J242
RNI J290
M621
J299-----....-..,
SW+EN J395
J002
MCPRiO
DISABLE
SHOWN ARE BITS 0 TO 2 OF THE EXX8 INVERTER
RANK AND THE S BUS TRANSMITTERS.
Figure 196. Address Transmission Logic
PARITY
pARI I Y ERROR
JOl2
REQUEST BUS KOOI
BC PRIORITY
K208
MOVE CYCLE I 2356
Vl17:
2R46A
Set Kl16/117(storagerequest); transmit a request to the appropriate storage module.
1030B
J335 RE G SEL
K343 KYBD BUS
MAIN
CONTROL
PRIORITY
J973 (ENTER PAGE FILE) (EXEC)
K351 ENTER
J300 KYBD BUS PRIORITY
2M38A
R/W
MC
PRIOR
2P54A
BLOCK
CONTROL
PRIORITY I
2P54A
L-...L..Jo"'----------,
N050
F654
JOII
K087
1---o-_J290 RNI
J060
KYBD BUS PRIO J242
MAIN CONT PRIO KOIO
BC BUS REQ KI51
K208
PF
VI25
STORAGE
REQUEST
2R85A
1 - - - + - - - - - - - - - - - + - - - 0 - - - + 1 K 116
2Q57
2Q50
K209
STORkGE REQUEST
VI17
N051
BLOCK
BLOCK
CONTROL
CONTRO
PRIORITY 3
PRIORITY 2
L...().--+-~ K210
~----o-~ K212
2R51B
2M50
2R50B
NI52
--4-~
K211
N005
NI52
V317
K213
Figure 197. Storage Request Logic
181
While main control waits for the reply from storage,
it will compare the breakpoint address with the address
transmitted to storage for equality .
NOSO: Input to HIlS.
VIIS: Set K012/013 (request lockout) and K004/00S
(word address mode). Input H116.
V116: Test for breakpoint comparison if BPI is selected and K136/137 is clear. (If breakpoint
stop were selected and a stop occurred on previous RNI, K136/137 would now set. )
To review what has occurred so far fill in the blanks:
CD------------
1.
CD--------------------CD--------------------------------------2. What is on the bus system at this time?
3. What is the state of main control at this time?
K012/013 (enable data bus) is set by VIIS. The purpose of this flip-flop is to break the inputs to HIlS
while K2I2/2I3 (priority delay) breaks the input to
HII7, thus preventing multiple outputs from the control delays. They are fed by NOSO, a raw clock which
comes up every other phase time.
K004/00S (word address mode) is set unconditionally
during RNI. It is used during ROP and STO and will be
discussed at that time.
K134/13S (breakpoint stop) will set if the address on
the S bus matches the breakpoint address, BPI is selected, and breakpoint lockout is not set. K136/137
(breakpoint lockout) being clear indicates that this is
not the first storage reference after a breakpoint stop.
NOTE: !fit is the first storage reference after a breakpoint stop, K134/13S (breakpoint stop FF) will be prevented from setting to allow the computer to continue
with the program. To say it another way, K134/13S
will not be set during the comparison to prevent stopping the second consecutive time on the same address.
Main control then waits for the selected storage
module to signal a reply. The waiting time varies
with the status of the memory module.
N050
4. Considering major timing of the RNI sequence, what
should occur next?
REPLY FROM STORAGE
Refer to figure 188 to reinforce your concept of how
the logic accomplished the previous steps of RNI.
1
CD Initiate RNI, request the bus system
CD
Update p.
CD Request storage.
o
BREAKPOINT COMPARISON
BREAKPOI NT LOCK OUT
Reply from storage.
E279
JI36
NO 50
J090
BREAKPOINT STO
KII7
STORAGE
REQUENCE
BREAKPOINT LOCKOUT
1----(>-...... KI36
VI15
VII6
KI35
ENABLE
DATA BUS
iKOl3
1
CLEAR DATA
BUS REGISTER
N400
Figure 198. Breakpoint Logic
lS2
EVE N TIM E
GO
KI37
STORAGE SUPPLY
OR PSEUDO
REPLY
IP56A
R5551
IQ56C
1
·JJ06S
I
I
IQ52
,. H060
IQ53A
A
IQ55A
H061
V061
~
10498
C493
H062
B
H064
C
H066
D
H06S
E
-..
-..
j
IQ56B
N071:
Figure 199. Resync Logic
Main control was hung up until the reply signal came
from storage. The S bus held the contents of P register, waiting for pickup by the storage module.
The processor must wait for the reply signal from
the storage module. The reply signal indicate s that
storage is processing the request and will have the
information on the data bus after a predictable delay.
(This delay time can be predicted because it is known
that when the storage module sends the reply signal
it is also referencing the location desired, and the
time for a memory cycle is known.)
R555 (storage reply) ~receiver)
V061 (resynced storage reply)
Reply signal R55S indicates that the storage module
is processing the request and after access time the
instruction will be available on the data bus.
A reply from anyone of four storage modules is
received by RSS5. The asynchronous reply (logical 1)
is fed to H060 along with a timing pulse from N07!.
H060/62/64/66/68 and H061 convert the reply to alogic
signal which produces a I output from V061 during an
odd clock phase. This output is 62. S nsec long and is
not repeated regardless of duration of input.
The timing pulse is produced by C493, an independently tuned clock amplifier. This amplifier is fed by
the clock pyramid but must be individually tuned so
that an output from V061 occurs exactly at odd time.
The procedure for tuning this amplifier is presented
in the 3300 Printed Circuits Manual.
The resynchronized storage reply signals the main
timing chain, the manual timing chain, or the block
control timing chain that the storage module is processing the request and will accept a word during a
write operation, or that the storage module will place
a word on the data bus during a read operation.
VOOO-VOOS: Clear KOOO/OOI (request bus) gives the
storage module access time to store the information from the data bus.
The timing from VOOO to VOOS is called "time -out
for aceess". Its purpose is to permit storage to reference an address and place a word on the data bus.
MAIN CONTROL
HAS THE BuS
Figure 200. Access Time
One of the first things to occur after the reply signal has been received by the processor is the clearing
of request bus FF. Clearing request FF neither clears
nor releases the bus system. If main control needs
the bus system, it requests it via KOOO/OOI (request
bus FF). If the bus system is not busy main control
is given bus priority and sends a request for storage.
Storage acknowledges the request by signaling that the
request has been received and is being processed.
However, the request for storage must be completely
processed before storage can transmit the requested
information. Essentially one might say that main control needs the bus, requests it, and storage starts
processing the request. At that point the bus request
--not the bus system--will be released.
Clearing KOOO/OOI (request bus) allows block control
the possibility of requesting the bus now. It is important to note that releasing the bus request is not the
same as releaSing the bus system. Main control still
needs the bus system to get the information that is
coming from the storage module, thus the bus system
itself has not been released. After the access time-out
and after main control has received the information it
requested from storage, then the bus system will be
released.
183
RE LEASE BUS SYSTEM
During an RNI sequence, if the storage address matches
the breakpoint address, breakpoint stop FF (K134/135)
is set. Kl35 is ANDed with V003 to clear the go FF
and stop the computer. K135 also holds V007 to 0,
disabling the main timing chain.
CD
ENABLE DATA BUS TO F REGISTER
Initiate RNI, request the bus system
o
Update P.
CD
Request storage.
o
o
Reply from storage.
Refer to figure 188 and review all previous steps.
Release bus system.
K086
STO
Figure 20l.
Relea8e Bus System
V006: Input to H201 (Logic Diagrams, page 2-29 if
J138 = 1. Test for powerfail (see chapter 11).
V007, NOOS: Clear KOIO/OII (main control priority),
FI, K212/213 (priority delay), K116/117 (storage request), and K012/013 (request lockout);
input H200.
NOSO: Clear K122/123 (initiate storage request).
Operations depending on V007 will not occur if the
breakpoint stop condition exists.
After access time has ela sed and as the information from storage is taken, from the bus system, main
control will release the bus system.
Releasing the bus system as soon as possible is important because block control and main control share
the same bus system. If the othe r control area needs
the bus system, the sooner it is released the sooner
it L:dll oc Ubt::U. Further discussiun of thi6 bus-sharing
operation is supplied in chapter 15.
Breakpoint Stop
When BPI is selected the breakpoint address is continually compared to the storage address on the S bus.
o
o
o
o
o
o
Initiate RNI, Request the Bus System
Update P.
Request storage.
Reply from storage.
Release bus system.
Enable the instruction to the F register
V007: Set K572/S73 (wait function).
(N209)
V008: Set K570/571 (F1
F2 enable)
(N208) EXX2 to F1
These two flip-flops are used in the arithmetic section of the processor and will be discussed in chapter
12.
The output of N208 and N209 setting K570/571 (copy
code FF) and KS72/S73 (wait function FF) occurs during each RNI sequence. The names of the flip-flops
describe their functions. Near the end of RNI, after
the instruction has been placed in F 1 register, the
upper nine bits of Flare duplicated in F2 in the standard arithmetic section of the processor.
Since the arithmetic section can run independently
during some arithmetic operations, F2 register provides the only source for the function translations.
The function translations are needed to provide enables
and permit gating during, for example, the mUltiply
and divide operations.
The data bus to receivers to EXX2 is a static enable. See figure 204 for the block diagram flow. See
figure 202 for the simplified logic. Note on figure 204
that EXX2 10 iii tItt! flU'vv path fi'UW btOidgt:: to llHiln
control as well as to the standard arithmetic section.
EXX2 could actually be considered the first branching
point for the flow. In this case EXX2 feeds F register.
Note that EXX2 a] so feeds the OB register.
CLR
--"" " ""
/
FI
~
,,-----------------------_/
,,- ------ - --
WAIT FUNCTION
K572
ODD TIME 1-2
VI09
INITIATE FI- F 2
t---...()...-.... H 518
K570
K571
K573
I~N=T=E=R...;"..R-,.U'='P=T----"S""""y""""'N"""C V 5 18
V519
TRAP SYNC
POWERFA1L
1-35
N55N554
V520
IIIAt-N CONTROL
Circuitry shown below the dotted line is discussed
in greater detail in chapter 12.
Figure 202.
OAT.
BUS
F1 to F2 Logic.
R
E
x
X
X
2
-TO
TO Xl
TO
OIR
VIA
17
Figure 203. Instruction Data Path
STORAGE
Figure 204. Data Flow
for RNI.
TR
6 lilTS
CPU~P
ADOII BITS
011-10
z,
Z£
•
INTERRUPT IUS
185
Transfer to DB register occurs during all RNI sequences but is only used on the second RNI sequence
for the 71 to 76 instructions. These instructions are
48 bits long and occupy two sequential memory addresses. Reading 71 to 76 instructions from memory
follows this sequence during RNI:
1. First half of the 71 to 76 instruction is placed in F
register and also in DB register.
2. The instruction in F register is translated and another RNI sequence is initiated.
3. P register is advanced and, during the second RNI
sequence, the second half of the instruction word
is read and placed in DB register. (The enable from
storage to F register is not present during the sec0nd RNI of 71 to 76 instructions.)
These are the reasons for transfer to DB register
during the RNI sequence. The execution of these 48bit instructions will be discussed in chapter 15.
DECODE INSTRUCTION
o
o
Initiate RNI, request the bus system.
Update P.
CD Request storage.
® Reply from storage.
o
Interrupt Recognition
An interrupt signal, generated by an external equipment or the control section of the computer, is a request for special action to handle a special condition
which has occurred. The main program is suspended
temporarily while a special routine of instructions is
performed. The interrupt request may be acknowledged and an interrupt routine initiated during RNI
or the RADR sequences.
An interrupt may be sensed only at NOlO time of the
RNI sequence. When arithmetic section is not busy
NOlO time will automatically come up only once in the
cycle 1 ~ time after an RNI pulse enters HOlO. This
would mean that an interrupt could be sensed only during the one time NOlO was up. K008j009 remedies
this situation.
Suppose the RNI pulse enters HOlO; 1 ~ time later
it senses for an interrupt and there is none. The RNI
pulse continues down the timing chain and sets Kl12/ll3
but cannot enter HllO because the arithmetic section
is busy.
Now, assume an interrupt Signal occurs after the RNI
pulse has reached this point. K008j009 permits the
computer to accomplish an interrupt sequence while
waiting for arithmetic to complete an operation.
If an interrupt is active NOlO will set K120j 121 (interrupt sync, see chapter 11) which will allow the interrupt to be processed. K008j009 would not have been
set at V009 time if the arithmetic section were not
busy, therefore NOlOwould have tested for an interrupt
active only once. Figure 206 shows a flow chart of
interrupt recognition.
END RNI
Release bus system.
® Enable the instruction to the F register.
G) Decode instruction.
V009: Set K008/009 (sense interrupt during arithmetic) if arithmetic section is busy.
VOlO, NOlO: Test for an interrupt condition.
VOll: Input to H080.
1(01!l6 Sfi)
I I~TE"RUPT
o
Initiate RNI, request the bus system.
CD Update P.
CD
Request storage.
o
Reply from storage.
@
Release bus system.
~
,SYNC
l"'f<; I
~
Figure 205. Decode Instruction and Sense Interrupt
IS6
o
~ F,n~hlp thp inf:1trlldion to thp 'F rpgigtpr,
0) Decode instruction.
®End RNI.
Is arithmetic
section busy?
Yes
V009 sets K008/009 to
allow constant sample
for interrupt actives
(NOlO) until arithmetic
section is bus •
NOlO samples for
interrupt active.
Clear K008/009 if
arithmetic goes 'iii'SY.
Yes
Process the interrupt
via program
Yes
Continue
sequence.
Figure 206. Interrupt Recognition
The arithmetic section would also be started
if address modification were necessary. Address modification is called FADR (form address) and is discussed in chapter 12.
Figure 207. End RNI
RAOR
NEXT
ROP
NEXT
V080: Progress to next storage
reference according to
(Fl). NOTE: V080 could
start the arithmetic section if necessary -- for example, RNI to RNI
progressions such as shift or enter operations.
STO
NEXT
V080 may initiate a trap sequence if the instruction
just re ad up is trans lated as floating point, double precis ion multiply or divide, or a BCD instruction (55 to
70), and the respective option is not present in the
system.
The trap sequence does not execute these instructions. It performs an operation similar to return jump
to a software routine that simulates the execution of
the instruction. The trap sequence is discussed in
chapter 14.
SUMMARY
This completes your excursion through the RNI sequence. So that you can see the forest in spite of the
trees let's review the four major functions of RNI.
1. Read an instruction word from storage and place
the instruction in F register.
2. Insure proper updating of P register.
3. Sense for all types of interrupts.
4. Start/ stop.
187
e
AD NEX,
INSTRUCTION
RNI
REVIEW
Scan the by-now-familiar RNI sequence diagram
and fill in the blanks without referring back to the
text.
INITIATE
A STORAGE
REFERENCE
OBTAIN
BUS
USAGE
CD------------------Q)-----------------------
CD--------------------CD--------------------
CD------------------------0--------------------
CD--------------------CD-------------------
STORAGE READ
CONTENTS OF ADORES
SIGNED BY (S) ARE
AD INlO Z
ez)", 9JS+EXX2+OBR
EXX2
GATED TO
Now refer to figure 208, a different representation
of RNI sequence. We will supplement this figure in
the chapters on RADR, ROP, and STO so that you can
visualize the areas unique to each sequence and common to all.
The next couple of pages provide a handy list of problems to fill your leisure hours.
lse
F
Figure 208. RNI Big Picture
RNI Worksheet
1. Define the purpose and application of block P FF,
(K200/201) .
11. Would less time be required to execute a selective
jump instruction if the switch were set than if it
were not set?
------------------
2. Why must the PI to P2 transfer always follow gating
of F to P?
12. At best, the selective jump instruction requires
~times)
usec, to accomplish its execution.
------
13. Is the arithmetic section used for the ]3b =I 0 decision of the index jump instruction?
3. During the RNI sequence at address 15000, what
ranks of inverters, transmitters, and receivers
provide a path from Z register to F register?
a. Storage
Z register
b. Transmitters
c. Receivers
d. Inverters
e. Main control
14. Does the increment / decrement of the 02. X instruction lengthen its execution time?
15. At best, the index jump instruction requires
______ ~times,
usec, to accomplish its execution.
16. Does execution of a 03.5XXXXX require starting
of the arithmetic section to accomplish its exe cution?
4. At best, how much time is necessary for an RNI
sequence from initiation (VO 14) to end RNI (V080)?
~ times)
usec.
17. Does the 03.5 XXXXX instruction take more time
for execution than the 03.2 XXXX instruction?
5. What two factors can delay the amount of time it
takes to complete an RNI sequence?
a.
18. At best, the 03. X instruction requires
----~ times,
usec, to be executed.
------
b.
6. What would the console indication be if a reply signal didn It come back to the processor?
7. List as many items as you can that could prevent
the reply signal from returning and entering HOOO?
a.
b.
c.
d.
e.
8. What is the purpose for releasing the bus system
at V007 time rather than at the end of RNI?
9. After executing a 00. 015000 instruction located in
memory at location 10077, what are the contents
of the following registers?
(F) =
(P) = _ _ _ _ __
10. What registers, if any, will instruction 00.015000
affect besides P and F?
The following problems are imaginary malfunctions
in the RNI sequence. Study each carefully and, after
analyzing the indications, list areas that should be
checked. Use LogicDiagrams, 3200CommandTiming
Charts, and this manual for references. NOTE: Consider each of the problems separately.
19. Indications:
a. F register does not get cleared of the old instruction.
b. Z register in the storage module shows that a
new instruction was read out of storage.
c. The following flip-flops remain set during the
RNI sequence:
KOOO/OOI (request bus)
K080/081 (RNI); RNIconsole indicator stays lit
K002/003 RNI lockout FF remains set
KOIO/Oll (main control priority)
K212/213 (priority 3)
Kl16/l17 (storage request)
K122/l23 (initiate storage request)
K012/0l3 (enable data bus)
There are at least four possible circuits that could
give these indications. Ust each one with the
reason why it could be at fault.
189
Ao _ _ _ _ _ _ _ _ because _ _ _ _ _ __
B. - - - - - - - - - because ---------
C. __________ because ___________
D.
----------- because -----------
CLUES: Did you request storage?
Did you get a reply back from storage?
If the reply did get back, did the processor recognize it?
20. Indications:
a. F register does not get cleared of the old instruction.
b. Z register in storage shows that the new instruction was read out.
c. The following flip-flops remain set during the
RNI sequence:
K080/081 (RNI)
K002/003 (RNI lockout)
KOIO/OII (main control priority)
K212/213 (priority delay)
K116/117 (storage request)
K122/123 (initiate storage request)
K012/013 (enable data bus)
d. KOOO/OOI (request bus) is clear.
The area of trouble that would give these indications must be between H
and V
-----
CLUES: Was a storage request initiated?
Did a reply come back from storage?
Did the processor acknowledge the reply?
If the reply did get back and the processor
acknow ledged it, how far did it get?
21. Indications:
a o F register receives the new instruction e
be The following flip-flops are clear:
KOIO/OII (main control priority)
K012/013 (storage request lockout)
K122/123 (initiate storage request)
K116/117 (storage request)
K212/213 (priority 3)
c. K002/003 (RNI lockout) is set.
The area of trouble must be from H
V
to
----
CLUE: Storage was requested and the reply Signal
must have come back with the information
or else F would not have received the new
instruction.
220 Indications:
a o RNI FF stays set.
be The old instruction stays in F register.
Co Z register in storage contains the data from
the last storage reference.
de The following flip-flops stay set during RNI
sequence:
KOOO/OOI (request bus)
K002/003 (RNI lockout)
KOIO/OII (main control priority)
K122/123 (initiate storage request)
K116/117 (storage request)
K212/213 (priority 3)
K012/013 (storage request lockout)
The area of trouble must be from H
B
. (No clues for this problem.)
to
-~--
NOTE: The times given for these answers were figured from the simplified logic page included
in this chapter. If your answer does not agree
exactly with the answer given here, consider
the time for transmitter and receiver cards,
flip-flop settings and clearings, etc.
190
Some instructions are executed during RNI to RNI.
A few of these are shown on this page with their flow
charts. Read the flow charts and trace the instructions
throughonthelogicdiagrams, using the 3300Command
Timing Charts as a guide.
00.0 Unconditional stop and jump to "m" upon restart:
RNI and
decode
Set SE LECT JUMP
and clear go
Manual
NOTE: This instruction is executed regardless of the state of the arithmetic section.
J-------{~-___I
00.1 to 00.6 Selective jump:
Adv P
RNI and
decode
NOTE: This instruction is executed regardless of the state of the arithmetic section.
RNI
Set P
02 Index jump:
Adv P
NOTE: This instruction
will not execute unless
the arithmetic section is
busy. Notice that the
arithmetic operationoccurs parallel to RNI.
RNI
Set P
Yes
~ANDGate
Arith busy
Sum to Bh
03 A jump·
--
Arith busy
RNI and
decode
N0
- (A) + -
...
(Q)
..
\
...-
Adv P
Condition
met?
Yes
Sense adder
or (A) or
(A) and (Q)
1
l
RNI
...-
Set P
NOTE: This instruction will n ot execute unless
the arithmetic section is busy. The arithmetic
operatIOn must occur before RNI may be initiated.
191
SELF-EVALUATION QUIZ ON CHAPTER 7
TRUE OR FALSE:
1. P register may be updated only during RNI.
2. Updating P register by 2 adds 4
tion execution.
~
9.
The CPU sends an absolute address directly to
storage if the system is in Executive mode and
the Multiprogramming module is present.
10.
The function of the Breakpoint Lockout FF is to
insure that a restart may be accomplished after
a breakpoint stop.
times to instruc-
3. Setting KOOO/001 gives main control priority of the
bus system.
4. The block advance P FF is set by a master clear
to insure that the first RNI is at the address in P .
5. The execution of ajump adds 4 ~ times to instructions for which the jump is optional.
11. The reply from storage starts the main timing
chain and indicates in all cases that storage has
acknowledged the storage request.
12.
F1 to F2 transfer is necessary because the Arithmetic Section can run independently.
TRUE OR FALSE OR FILL IN BLANKS
13. Main control receives Data from storage during
RNI.
6.
The P3 register holds the last jump address
(Program State).
7.
If the system is in Non-executive mode, the upper
3 bits of the S bus, as sensed at the output of
the T cards, will be _ _ _ _ __
15. Interrupt is sensed every VOIO time if the RNI
FF is set.
The
rank of inverters has 2 inputs
to the T6XX cards so that
to
______ address conversion may be accomplished.
&ore yourself:
Missed none or one? Excellent!
Missed two? Below average
Missed three or more? Too bad--you've failed!
14. The transfer of EXX2 to Fl occurs for every RNI.
8.
CHAPTER 8
READ ADDRESS SEQUENCE
DESCRIPTION
The read address (RADR) sequence is used when indirect addressing, used only with instructions that use
execution address m, is required. After an RNI (and
possibly indexing), an RADR sequence is used to procure the execution address of an instruction. Several
levels (or steps) of indirect addressing may be used
to reach the execution address. Indirect addressing
is specified for applicable instructions when bit 17 is
a 1. Figure 209 shows the indirect addressing routine
for the 3300.
Figure 210 is a system block diagram. The heavy
black line originating at Fregister indicates the transfer path for the lower 15 bits ofthe address. The upper
3 bits of the address will be O's if the system is non
executive or in monitor state. The upper 3 bits of the
address will be (ISR) if in program state. Originating
at Z register of module 0 represents transfer path for
data from storage.
Steps in the RADR sequence are:
1. At the end of RNI request bus priority.
2. Obtain bus priority.
3. Transmit aread signal. Transmit storage address
4. Transmit storage request. Wait for selected storage module to reply. (Waiting time varies depending
on memory module status.)
5. Receive and resync storage reply; use this signal
to start main timing chain.
6. Clear lower 18 bits of F and clear DB register.
7. Gate data from the bus to F and DB register.
8. Test for interrupt.
193
9.
End RADR. Set the correct storage sequence control FF to execute the neA"i appropriate sequence.
Ifanother step of indirect addressing is required,
RADR remains set and another RADR sequence is
executed.
End of
RNI
RADR is nearly identical to RNI. The flow of information is identical. The only differences are that
the storage address comes from F register instead of
P, and informa tion from storage goe s to only the lower
18 bits of F instead of all of F •
Original instruction may
contain a and/or b.
1
No
This operation,
FADR (form address), is covered
in chapter 10.
Add the contents of
to m to obtain M.
a = 1 for indirect addressing
b = index designator
m = unmodified execution address
Bh
No
This operation
is handled by
RADR sequence.
Yes
Go to address M; acquire
Execute the instruction
using address M.
new terms a, b, * and mo
*The b designator is not changed
on a 47 or 54 instruction.
DETAILED TIMING
To read an address from storage, several operations
must occur:
1. Request bus system. (F lower 15 bits is the address
to be referenced. )
2. Obtain bus priority.
3. Transmit address in the lower 15 bits of F to storage via the S bus.
4. Do not transmit write signal. (Absence of a write
signal is a read signal.)
5. Transmit storage request.
6. Do not test for breakpoint stop.
7. Wait and resync reply from storage.
b. Clear request bus.
9. Time out access to allow storage to read and place
word on data bus.
191
Yes
Figure 209.
Indirect Addressing Routine
10.
11.
12.
13.
Sense for interrupt
Clear "F" lower
Gate data bus to "F" lower
Test for stop (cycle step mode, or instruction step
and end of instruction, or STOP pressed and end of
instruction) .
14. Advance storage reference controls to RNI + RADR
+ Rap + STO.
15. Progress to next storage reference if not stop.
NOTE: The lower 18 bits of F are cleared and EXX2
is gated to these bits for all instructions requiring indirect addressing exr.ept 47 and 54. For thcDC LI,VU
instructions only, bits 0-14 and 17 are cleared and
replaced with respective bits from memory.
BLOCK CONTROL
CHANNEL
REQUEST
MAIM CONTROL
If;
4
~
.
6
7
CPU~P
ADDR lilTS
09-10
Z.
•
Z£
1NTERIIUPT IUS
Figure 210.
Data Flow for RADR
195
F
REGISTER
110 CYCLE
BK PT SWITCHES
[
1
l
I
STORAGE
REQUEST
RIGHT OR LEFT
----------+
r--
V007
N005
f-
J280 MC
ENABLE
DATA BUS
KOl2
N40~ KOl3
RE LEASE
BUS SYSTEM
STORAGE
REQUEST
KII6
~
I
~
CLR.II F JI
""H
~ 201
N201
N203
KI34
JI44
RNI +RADR
KII7
N205
MAIN
CONTROL PRIORITY
r
KOIO
N207
N209
JIOO (RNI +
~ KO"
PRIORITY
DELAY
K212
KOSO (RNI)
, 6 +F) (Me)
Note: N208 and N209 will not emit a
pulse this time, leaving the
original function or upper 6
bits of F1 the same.
--. K213
Figure 219. F Register Enables
V008: EXX2 to the lower 18 bits of Fl; EXX2 to DB
register; test interrupt
be considered the first branching point for data flow.
In this case EXX2 feeds F register. You will note
EXX2 feeding DB register also, but the transfer is not
used for this sequence
0
lSTO) K086
~
Figure 220. V008 Time
DATA
BUS
The data bus to receivers to EXX2 path is maintained
by a static enable. Note on the block diagram that
EXX2 is in the flow path from storage to main control
as well as to standard arithmetic. EXX2 could actually
R
5
X
X
-
E
X
X
~
2
F
Figure 221. RADR Data Path
201
VA'M CONTROL
TO xl
TO
DaR
VIA
11
Figure 222. Data Transmission for RADR
REDECODE INSTRUCTION
1
READ ADDRESS SEQUENCE
CD Start RADR,
o
CV
o
G)
o
request bus system
V009: Input to H082, test stop.
(RAORl "'3
V008:
~
r~
_
H082
Figure 223. End
RADR Time
Reply from storage.
Redecode time is less than decode time from RNI
because function translation is static; the only new bit
that can affect the translators is bit 17. Bit 17 is translated rapidly (fewer inverters) and will be translated
by V082 time.
Re1f~Ase
END RADR
Request storage.
hm: system.
Enable data bus to lower F register a
Redecode instruction.
o
CD
o
o
Start RADR, request bus system
Request storage.
o
o
Redecode instruction.
EndRADR
Reply from storage.
Release bus system.
CD Enable data bus to lower F register.
V082: Progress to the next storage reference cycle
according to the (Fl).
V082 will set Kl12/113 (no
index) \vhich \vill allow another sequence to be initiated o Which sequence is
initiated depends on which
sequence control FF is set.
ABNORMAL INT. JI42
RADR FF will not be cleared
+
INTE R RUPT SYNC.
if another RADR sequence
+
is required. After RADR
TRAP
sequence the sequence progression can occur in any of the following ways:
(RADR) K083
V082
NEXT
MEMORY
REFERENCE
RNI
RNI F50(l---+-~~ K080
NEXT
K081
RADR
RADR to RADR if another level of indirect addressing
is required; RADR to RNI if the instruction was initially a 01.4; RADR to ROP or RADR to STO for all instructions which use ROP + sro and can use RADR.
K082
K083
RADR F501
NEXT
ROP
ROP F400
NEXT
-+-~aI
REVIEW
You should be able to fill in the blanks without referring back to the text.
1
0-----------------------
K084
K085
STO F402
NEXT
--~aI
K086
K087
Figure 224. Sequence Controls Advance
GJ----------------------0----------------------0---------0--------0----------------------G)----------------------203
SELF-EVALUATION QUIZ ON CHAPTER 8
E
NE)(~
6B
REA
AD
INSTRUCTION
ADDRESS
RADR
RNI
TRUE OR FALSE:
1. RADR sequence is available for all instructions
in the 3300 repertoire.
INITIATE
A STORAGE
2. RADR sequence may be entered only from RNI
sequence.
REFERENCE
3.
If the system is in Program state, the upper three
bits of address are supplied by ISR.
4.
For a 47 or 54 instruction, RADR does not modify bits 15 and 16 of F.
5.
An illegal write signal may never occur during
RADR.
OBTAIN
BUS
USAGE
6. Interrupts are not sensed during RADR at VOI0
time.
7. During RADR, storage places only the lower 18 bits
of the selected address on the data bus.
STORAGE READ
CONTENTS OF ADORES
[ESIGNED BY (51 ARE
READ INTO Z
8. If indexing and RADR are both specified by the
instruction in F, indexing will occur first.
9. Indexing will never occur after RADR.
(Z). BUS+EXX2+0BR
10. More than one level of indirect addressing is permissible with the 3300.
EXX2
GATED TO
F
EXX2
GATED 10
FL
Notice the similarity between
RNI and RADR.
Figure 225. RADR Big Picture
~U4
.Score yourself:
You should not have missed a single one.
If you missed one, you probably were careless.
If you missed two or more, you'd better study the
chapter again.
CHAPTER 9
READ OPERAND SEQUENCE
INTRODUCTION
During the read operand sequence the lower 15 bits
of address is obtained from Flower 15 while the upper 3 bits may be obtained from OSR, ISR, or they
maybe Os depending on the Mode and State of the computer. In many cases the lower 15 bits of address
may be modified by indexing. For more information
about specific instructions refer to the 3300 Reference
Manual.
The steps in ROP sequence are:
1. At the end of RNI or RADR or a previous ROP
sequence, start ROP and request ,bus priority.
2. Obtain bus priority.
3. Transmit a READ signal and transmit the storage address via the CPU S bus.
4. Transmit a storage request.
5. Test breakpoint. Set Breakpoint Stop if BPO is
selected and the breakpoint address equals the
operand address. (Main control waits for the
selected storage module to reply. )
6. Receive and resynchronize a storage reply; use
this signal to start the main timing chain.
7. Stop if Breakpoint Stop is set.
S. Clear the DBR.
9. Gate data from the bus to the DBR.
10. Start arithmetic section. Arithmetic section then
performs the operation specified by F code.
11. End ROP. Set the correct storage sequence control FF to execute the appropriate sequence next.
If another ROP is necessary, as after the first
cycle of a 4S-bit precision load, ROP remains
set and another ROP sequence is performed.
205
Figure 226 is a System Block Diagram. Note the
heavy black line originating at the F register which
illustrates the transfer path for the address to storage. Also note the heavy dashed line originating at
the Z register of the Storage module. This line which
terminates at the A register depicts the transfer path
for data if we were doing a Load A instruction.
Figure 227 is a simplified Address Flow diagram
for the 3300 if relocation is to take place.
DETAILED TIMING
Rap is used for load, add, subtract, multiply, and
divide instructions.
To read an operand from storage, several steps
must occur:
1. Request Bus System (KOOO/OOl) (F Lower holds
address of the operand.)
2. Obtain Bus Priority (KOI0/0ll).
3. Transmit Address in FLower on S Bus to the
Mul tiprogramming module.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Do not transmit Write signal (T655 = 0).
Transmit Storage Request (Kl16/117).
Test for breakpoint stop if BPO (K134/135).
Wait and resync reply from storage (V061).
Clear request bus (KOOO/OOI by NOOO).
Time out access to allow storage to read and place
word on data bus.
Clear DB register (V007).
Stop if BPO.
Gate data bus to DB register (bus to EXX2 to DB
register) • Set start arith 2.
Test for stop (cycle step mode 0r instruction step
and end of instruction or STOP pressed and end of
instruction) .
Advance storage reference controls to RNI + Rap
+ STO.
Progress to next storage reference if not stop.
MAIN CONTROL
BASIC ARITHMETIC
STORAGE
Figure 226.
Data and Address Flow
F
REGISTER
I/O CYCLE
BK PT SWITCHES
DPROG. STATE>}[( RNI+ RAOR)+
{ROP+STO+BOP OP. CY.HO=--=SR=--==S""'E"....L=EC?:s::=
+ (STO 8RTJ)]
EXECUTIVE
+
MONITOR [(RNI+RADR)+{ST08RTJ)+
(ROP+STO+ BOP OP. CY.)(OSR SELECTED)]
~=:::::.-:;===I:;I,~~=09;-08~,
'"======::;======_oq:::;,
INPUT TO RELOCATION
PAGE FILE
23
00
12 II
001
000
Ze
Zo
176'--_ _, -_ _---1..._ _--,.._ _- - 1 177
CPU ADOR.
~
I~--+---- ADDER (NO END AROUND CARRY)
t
~~rr----"------,
I
~
13
'-----v-----"
100908
09 OUTPUT FROM RELOCATION
,
I
TO
MODULE
SELECT
SWITCHES
"----STORAGE
REQUEST
RIGHT OR LEFT
STORAGE
S BUS
------}[< RNI+ RADRl+
(ROP+STO+BDP OP. CY.)(O~":'SR~S:-::E'"""L=EC?!o:=
+ (STO S RTJ1]
EXECUTIVE
+
MONITOR [(RNI+RADR)+(STOSRTJ)+
(ROP+STO+ BOP OP. CY.)(OSR SELECTED)]
==::::::.-:;.===11;-,~~=09~~~8======::;:======oq:;,
INPUT TO RELOCATION
PAGE FILE
23
00
12 11
000
001
z.
zo
176 L-----r----L.----.---~ 177
I~--+_---
,
'-----,~j
I
~
13
ADDER (NO END AROUND CARRY)
O~ OUTPUT FROM RELOCATION
10 0908
~~J.,~======~======~,
I
TO
MODULE
SELECT
SWITCHES
L
COO::'OATE
->
ADDRESS
~-----~>
STORAGE
S BUS
STORAGE
REQUEST
RIGHT OR LEFT
Figure 245.
Address Flow
221
11. Clear request bus (KOOO/OOI).
12. Time out access to allow storage module to store
word.
13. Stop if BPO.
14. Advance storage reference controls to RNI + STO.
15. Progress to next storage reference if not stop.
Figure 246 graphically shows the STO sequence of
events.
During STO main control must place an operand on
the data bus, making it available to storage. Main control will start the arithmetic section about the same
time as storage is requested.
The arithmetic section will move the contents of A
or Q register to X register from where it will be enabled to 17 to EXX2 and then gated to DB register.
To store an operand in core, several steps must
occur:
1. Request bus system (KOOO/OOl); set start arith.
Lower F holds address of operand.
2. Obtain bus priority (KOIO/OII).
3. Transmit address from lower F on S bus to storage.
4. Transmit write signal and write designators (T655
= 1).
5. Transmit storage request (KI16/117).
6. Enable DB register to bus.
7. Test for breakpoint stop if BPO (KI34/135); drop
write signal if breakpoint stop.
8. Clear DB register.
9. GateEXX2 to DB register. 17 is enabledtoEXX2.
10. Wait and resync reply from storage (V061).
Storage
reply
Bus priority
granted
From
RNI + RADR
+ROP +STO
sequence
--.
Request
bus priority
~l-~
~
Start
arithmetic
if replace
F register
to S bus
via EXX8
~
Transmit
storage
request
.--b-
Clear bus
request
-
1
"
Transmit write
signal and
designators
Test for
....... BPO stop and ......
illegal address
Drop write if
BPO or illegal
address
~,
Enable DB
register to bus f-+ Clear DB ~ EXX2-+DB
register
register
IXX7-+EXX2
BPO stop -
Access
time-out
Release bus,
drop request
for storage
and write
Step + stop
-
Advance
sequence
controls
FL + I-+F L
first cycle of
double precision
Initiate next storage cycle (RNI + STO)
as determined by the instruction in F
Figure 246. Flow Chart of STO Sequence
G) Start store (STO); request bus system.
i CD
I
Request storage; start arithmetic.
G) Word to bus.
}iguJ:tJ :::;'i I.
i'viajul Timing ui STO Sequence
er> Reply from storage.
CD Release bus system.
o
222
End STO.
START STO; REQUEST BUS SYSTEM
o
Start store (STO); request bus system.
V380/V080 (end of RNI) or V082 (end of RADR) or
V084 (end of ROP): Set K086/087 (STO); clear K084/
085 (ROP); set Kl12/113 (RNI Index). Note
that the end of any previous sequence could
start STO.
VI09: Input to HII0
V210: Set KOOO/OOI (request bus); clear Kl12/113
input to HI05.
If no address modification is needed, Kl12/ll3 (no
index) will set at the end of RNIor RADR or for the two
replace instructions at the end of ROP.
Notice that STO is the third sequence which requires
V210 to set request bus FF. What were the other two
sequences? _________________________________
What term did the one remaining sequence, STO, require to set KOOO/OOI (request bus)? ____________
Input to HllO cannot be made if the arithmetic section is busy from a previous instruction.
VI09 ARITH BUSY
K572 WAIT FUNCTION
REQUEST BUS
KO 0 0
(VO BO)RNI-+STO
(VOB2) RADR.STO
(VOB4) ROP--' STO
1-----4--CJ-Ia.!
KII3
KOOI
{V080)RNI ---'STO
{VOS2)RADR ~STO
(V084)ROP ~STO
H 106
VI05
H 126
Figure 248. STO Sequence Initiation
REQUEST STORAGE AND START ARITHMETIC
Start Arithmetic
N05l:
1
o
STORE OPERAND SEQUENCE
SJ
Start store (STO); request bus system.
CD Request storage; start arithmetic.
Set KOIO/Oll (p. l-3*)if K208 =1. If K209 =1,
repeat this test at next N05l time: Whenpriority is granted (indicated by setting of K010/0Il)
gate Fl to EXX8 to T6XX to S bus; gate EXX8
to EXX7 to EXX6; T655 (read) is on; transmit
write designators of 011112.
V126: Set KI04/105; start arith 2.
The arithmet1c, once started, will transfer the contents of A register or Q register to X register. Main
control can cause the enables for X to 17 to EXX2.
* Logic Diagrams
223
ODD RAW
CL.OCK
MAIN CONTROL
PRIORITY
I~EQUEST
BUS
K 000/001
r-----------------------------l
KOIO
I
Arithmetic timing will be covered in chapter 12.
KOII
K208
Z356
JOl2
V2'IO
~
crq.
~
"i
CD
t...:l
~
MAIN CONTROL
MOVE CYCLE I
PARITY ERROR
PRIORITY
+
PARITY
I
VI05
VI06
;0
>
~.
c+
::T
S
CD
DISABLED
START
ARITH 2
KI04
34+ 10.1 F503
---r~
STO J087
VI26
c+
o·
VI09 ARITH BUSY
K572 WAIT FUNCTION
I
~
"i
:;::$
r:n
J-3
V511
__ II
r:n
0
I~X{A-X)
I
VI04
c+
c+
STORE
USING 0
a
,----------------I
A2
V510
0
START
V521
ARITH I
KIOO
WAIT FUNCTION
STORE
USING A
.K573
--~
r-------
'--O--I"HI-O
----I
'
I~~-_OJ
~------~
IHI- I
----,
ARITHMETIC
~------,
'r+i HI I
I~~~J
SECTION
5
----I
I
I
I~~~J
6
"
TIMES
t
I
I
I
I
L _________________________________________________________________
JI
ISII+O!
CIR+S(
INT NA
STAT'
ID
t
TO Fl.
SUi
lOP ADO
C~U~P
ADDR BITS
09-10
Z.
•
Z£
IIITEIt.UI'T BUS
ST':' _
Figure 250. Address Transmission for STO
Request Storage
N050: Input to Hl17; at this time V126 is setting K104/
105 (start arith 2).
Vl17: Set K212/213 (Priority 2). Set Kl16/117 (storage request). Transmit a request to the Multiprogramming module.
What has happened up to this point of the STO sequence?
1. Arithmetic --section has been started and is gating
(A) to X register.
2. A storage request has been transmitted along with
a write signal and the write designators to the storage module.
3. Main control is comparing the breakpoint address
with that on the S bus for possible SPO stop.
4. The address on S bus is being compared with the
STORAGE PROTECT switches; checking for illegal
write. The Multiprogramming module will also
check for illegal write.
225
STORAGE
REQUEST
J217
J214
EVEN RAW
CLOCK
ODD RAW
CLOCK
MAIN
CONTROL
PRIORITY
REQUEST BUS
STORAGE
REQUEST
KI16
KOOO
KI17
KOOI
K212
K208 BLOCK CONTROL PRIORITY
Z356 MOVE CYCLE I
JOl2 PARITY ERROR + PARITY DISABLED
Figure 251. Storage Request on STO
Write Signal and Illegal Write
During a storage reference in which data is to be
stored, the storage module receives a write signal
which is generated in the CPU and relayed by the
Multiprogramming module. If this write reference is
illegal, the write signal will be changed to a read signal. If the system is in Executive mode when an illegal write occurs, an abnormal interrupt will be generated. In the CPU, J132 senses for an illegal write;
in the Multiprogramming module, J440 senses for an
illegal write.
J132 goes to 0 when:
1. (Exec) (DIsable Storage Protect) (storage protect
C.P.U.
switches compare with the Address on the CPU S
bus).
2. (Exec) (address on the CPU S bus is in the Auto
Load or Auto Dump Area).
3. (Program State 0) (Disable Storage Protect) (storage
protect switches compare with the lower 15 bits on
the CPU S bus).
4. (Exec) (Keyboard Bus Priority) (address on the CPU
S bus is in the Executive Auto Load or Auto Dump
area).
J440 goes to 0 when:
1. E=1.
2. Bits 09 and 10 of the CPU S bus :> PL.
I MULTI-PROGRAMMING
STORAGE
MODULE
K796
RIGHT BUS
WRITE JI30
STORAGE
.-------,
K760
I LLEGAL WRITE JI32
M.C.
+
T1050· PARITY ERROR
K761
WRITE STORAGE
Figure 252. Write Signal Path
\\irite Design?-tors
ForlI1.structlons using character addressing, the
character translations from E008, E018, E208, and
E218 determine the write character designators (0-3)
which are transmitted to storage to determine the
character (s) to be written during a store character
226
operation.
Referring to figure 25~ ~ During 81'0 sequence of a
word-addressed instruction, T660to T663 transmitters
will he turned on. This will be a full-word write of
all four character positions. The J295 to J298 terms
will have their inputs all at a zero level.
J292 Zl- BIT 19+EN CH 0+2+4+6
2HI
2R88B
F5 F6
MC PRI0+2ND STO CYCLE JI28
r
~~?g
CHAR
2 ;,
RB1~~!~E
>-L~
3
F5,F6
DES'GNATORSl
~~?g --c>----+-~
CHAR ADDR+ RNI WI51---+--...----'
B C - 24 BIT J773 - - - 1 1 - - - - - - - '
WR!TE
MC PRIO+CPU WAIT 1981
Z838 Zl-BIT 19
J980 EN CH 0+2+4+-6
EOl8 -<'l---~
E20S
CHAR
DESIGNATORS
EOOS -c___+-~
EOt8
JOII MC PRIO
F425 (46){2ND STO CYCLE)
WI51
EN CH 0 +2+4+6
I
m3
J129
15 BIT WRITE F609
2R89A
2~RJ
F7,F8
. WRITE
2H2
ADDR
~LB
F7,F8
F609 15 BIT WRITE
JOII MAIN CONTROL PRIORITY
F425 t46)(2ND STO CYCLE)
Figure 253. Partial Write Bit Transmission
For a store A character, the position at which the
character is to be stored determines the transmitter
that will be turned on. E008 and E018 are the complement of the character position. E208 and E218 are
character position.
The other terms are used with store word address,
store character address, interrupt sequences, or input operations
If BPO is set, the address on the digit switches is
compared to the address on the S bus. If these addresses are equal during STO, the computer will stop.
Sensing of Breakpoint Stop takes place at VI16 time.
K134/I35 (Breakpoint Stop) sets if: The address on
the S bus compares with the address in the Breakpoint switch, BPO is selected, and Breakpoint Lockout is not set. If K136/I37 (Breakpoint Lockout) is
not set this indicates this is not the first storage reference after a breakpoint stop. Note: If it is the first
storage reference after a breakpoint stop, setting of
K134/I35 (Breakpoint Stop FF) is blocked to prevent
stopping a second time at the same address.
The character translators also determine setting or
clearing of E204/205 and E214/215. During a write
character operation, the outputs of these flip-flops
determine the character transposition necessary to
gate a character from the EXX2 to the lower bit positions of DB register. EXX2 is also fed by the r7 rank
of the processor. This provides a path for transmission of data from the processor to DB register.
The data from EXX2 is gated into DB register.
Character shifting is performed between the EXX2
rank and DB register. Data can be transferred directly
227
or right shifted (end-around) one, two, or three character positions. These shifts are controlled by the
H4XO control delays. During character addressing,
one of these delays is pulsed on the basis of the translation of the lower two bits of the character address.
This then gates the selected character from EXX2 into the lower six bit positions of DB register.
N050: Input to Hl15
Vl15: Set K012/013 (request lockout) and K004/005
(word addressing mode); input to H400. Set
K042/043.
V116: Test for breakpoint comparison if BPO has been
selected and K136 = 1; input to H401.
N401: Clear DB register; input to H410 (if 24-bit
store).
J272 ILL WRITE 00.7 STO CYCLE
R312 ILLEGAL WRITE
.-------,
FROM PAGE FILE
RADR
K083
SAMPLE STO PROTECTV216
EXEC J223
ILLEGAL
WRITE I
KI32
F845
CLR ILL. WRITE
BREAKPOINT
STOP
N050
K116/117 -..(")----.t
BREAKPOINT
LOCKOUT
KI34
KI36
KI35
KI37
N050
E279 BKPT
K090 GO
COMPARISON
CLR DBR
KOl2
\ - - - - H4XO (EXX2 TO DBR)
KOl3
Figure 254.
Breakpoint and Illegal Write Test
WORD TO BUS
1
o
o
o
22R
STORE OPEH.AND SEQUENCE
Start Store (STO); request bus system.
Request storage; start arithmetic.
Word to bus.
N410: Gate EXX2 to DB register (static enable of X
to 17 to EXX2); transmit the contents of DB register on the data bus. Clear K042/043.
The transfer from EXX2 to DB register may be
straight or end-around right one, two, or three characters.
The store sequencefor a word-addressed instruction
will always be a straight or direct transfer from EXX2
to DB register (as, for example, in 40, 41, and 44-47
instructions) •
N40X-------,
E - -2 --- DBR STRAIGHT TRANSFER
E204
LOWEST
TWO BITS
OF "S" BUS
E205
E214
~
CHAR POSITION
TRANSLATORS
E--2 ...... DBR RIGHT SHIFT 3
CHAR POSITIONS
K005- WORD ADDRESSING
Figure 255. DBR Transfers
Character-addressed instructions may require any
of four possible transfers between EXX2 and DB register. Which transfer path is used is determined by
the position into which the character will be stored.
Examples of the four possible transfers are shown below. The store A character is used but store Q character would be the same.
TO POS
2
TO POS I
TO POS 0
TO POS 3
Figure 256. Operand Transmission for STO Sequence
DBR to the T5XX and T7XX transmitter enables is
turned on when K012/013 (Enable Data Bus FF) sets.
Figure 257. Data Transmission
for STO
LOW
IQ
~Err
STORAGE
TERIII.
CABLE
TERM·
3 BITS
C.SL~
HIGH
U
I L.el
229
Review the progress of STO to this time:
0---------0---------0---------Main control is hung up at this point. It cannot accomplish anything else until the reply signal arrives
from the storage module.
1
Start Store (STO); request bus system.
Request storage; start arithmetic.
Word to bus.
Reply from storage.
V061 (resynced storage reply)
VOOO-V005: Clear KOOO/OOI (request bus) gives the
storage module access time to store the information from the data bus.
Storage Reply Resync Circuit
A reply from anyone of four storage modules is received by R555. The asynchronous reply (logical 1) is
fed to H060 along with a timing pulse from N071. H060/
62/64/66/68 and H061 convert the reply to a logic signal which produces a 1 output from V061 during an odd
clock phase. This output is 62.5 nsec long and is not
repeated regardless of duration of input.
REPLY FROM STORAGE
STORE OP[l
o
CD
o
o
SEQUENCE
R555
.. i
"[CEIVE A
REPLY F"O
ANY STORAGE
MODULE
J068 1
.
-
CARD TYPE
CA65
CARD TYPE
CA64
H060
CARD TYPE
CA66
,
H062
H061
H064
V061
f---+
PRODUCES 62.5 nSEC. "I"
(RESYNCHRONIZED REPLY)
AT 000 TIME
H066
H06S
C493
N071
~
THE RESYNC ORCUIT USES
POSITIVE LOGIC LEVELS.
SPECIALLY TUNED
CLOCI< AMPLI FIER
Figure 258. Storage Reply Resync Circuit
KOII MAIN CONTROL PRIORITY
Me
J280
REQUEST BUS
GO
KOOO
KOO I
I
I I
BREAKPOINT LOCKOUT
BREAKPOINT STOP JI35
BREAKPOINT
I
STOP.
KI34
BREAKPOINT
LOCKOUT
K090
KI36
K091
BREAKPOINT STOP
KI34
I"
KI37~1"::"_""
Figure 259.
230
KI37
Breakpoint Stop Logic
The time from VOOO to VOOS is called "time-out for
access". It permits storage to reference the data bus
and to store the information One of the first things
to occur after the reply signal has been received by
the processor is clearing of request bus FF. Clearing request bus FF neither clears nor releases the bus.
Main control and block control share the same bus
system. Main control needs the bus system, requests
it via KOOO/OOI (request bus FF), and storage starts
processing the request. After the requested information is returned the bus request is released, but bus
priority is retained.
V003 time will clear K090/091 (go FF) if a breakpoint stop is required. When BPO is set, the breakpoint address is continually compared to the storage addre-ss on the S bus. During an STO sequence, if
the storage address matches the breakpoint address,
breakpoint stop (KI34/13S) is set. Kl3S is ANDed with
V003 to clear go and stop the computer.
0
STORAGE
REOUEST
IIIAIN CONTROL
PRiORITY
Figure 260
Release the Bus System
PRIORITY
DELAY
END STO
RE LEASE BUS SYSTEM
.TORE
011 1
~QUENCE
1
CD Start Store (STO); request bus system.
CD Request storage; start arithmetic.
CD Word to bus.
o
Start Store (STO); request bus system
o
CD
o
o
Request storage; start arithmetic.
Word to bus.
Reply from storage.
Release bus system.
V006
V007: Input to H086; clear KOIO/OII, KI16/117, and
KOI2/013; test stop; end transmission of the
DB register to Storage; clear K212/213.
After storage ,reply and access time has elapsed,
main control will release the bus at V007 time. Releasing the bus system as soon as possible is important.
Block control and main control use the same bus systern The enable set up earlier (DB register to storage) will drop out now.
0
o
@
o
Reply from storage.
Release bus system.
EndSTO.
V086: Clear K086/087 (STO); set K080/081 (RNI); input to H087.
V087: Input to HOI4; perform RNI if computer is going.
K340/341 blocks the progression from STO to RNI
during manual store operation. For a discussion of
manual store operation and timing see chapter 6.
The input from V007 to HOl4 must make it through
the AND gate with K081 (RNI FF). This AND gate can
be made if the next sequence is RNI. Other inputs that
come into H087 (not illustrated) require the AND gate
for other operations (discussed elsewhere in this manual).
231
The sequence progression FFs are always affected
the same way at the end of the STO sequence. STO is
cleared and RNI is set. There is no other progression
path possible except STO to RNI, unless it is a double-
precision operation which would be RNI - STO - STO RNIat which time J063 tD~ will be a 1 blocking the output
of V086 until the double -precisIOn operation is complete.
INITIATE
r:(J
~HO~
HOl4
'1081
'1014
K341
STO
Figure 261.
REVIEW
You should be able to fill in the blanks without referring back to the text.
End STO Timing
G)----------------------(0------------------------
G)------------------------ CD----------------------G)----------------------- Q)-----------------------
232
6B
e
BASIC
ADDRESS
RNI
Figure 262 is a graphic representation of all four basic sequences. Note the areas unique
to each sequence and common
to all.
CONTROL SEQUENCE
EA
EAD NEXj
INSTRUCTION
RADR
OPERAND
EREAD,
ROP
6
TORE
,
OPERAND
STO
STORAGE READ
CONTENTS OF ADORES
DESIGNED BY (5) ARE
READ INTO Z
(Z) .. BUS*EXX2+DBR
EXX2
GATED TO
F
2
GATED TO
ft.
DATA TRANSMISSION
TO STORAGE
IS DROPPED
lPON RElEASE
THE BUS
Figure 262. STO Big Picture
233
SELF-EVALUATION QUIZ ON CHAPTER 10
TRUE OR FALSE
1. The STO sequence may be entered from RNI,
RADR, ROP, or another STO sequence.
9. The only exit from STO is to RNI.
10. For a store character 2 operation, gatingof EXX2
2. If the system is in the Monitor state and operand
relocation is not selected, ISR will be referenced
for the upper three address bits during STO.
3. If the system is in the Monitor state an illegal
write cannot occur during STO.
4. The Write signal, which is generated by main
control during STO, is relayed to storage by the
Multiprogramming module.
5. If an illegal Write is sensed during STO, storage
reference is aborted and a pseudo-reply is generated.
6. If the system is in the Program state, storage
protect switches can be used to protect logical addresses OXXXXXS'
7. For character store operations, it is the responsibility of main control to properly position the
character to be stored.
S. For every STO, main control must send a Write
signal and Write Designators to storage.
234
to DB register will be right 3.
11. During STO, main control sends Data to storage
via the data bus cable.
12. A BPO is possible on the second STO of a store
AQ instruction.
13. If the system is in Non-Executive mode, an STO
in the upper 40 S locations of available storage
would be an illegal write.
14. If the system is in Executive mode, an STO in the
upper 100S locations of page 0 would generate an
illegal write.
15. A storage request is always sent to storage as
soon as Kl16/117 sets during STO.
Score yourself:
After studying chapters 5, 6, and 7 you shouldn't have
missed any questions.
If you missed one or more, you've failed!
CHAPTER 11
SEQUENCE PROGRESSIONS
This chapter lists all possible cycle progressions
for the 3300 Computer. It will be to your advantage to
use 3300 Command Timing Charts and 3300 Computer
System Logic Diagrams in conjunction with this chapter. You will find that sequences of the 3300 will take
on more meaning if you try a few sample cases of sequence progression.
SEQUENCE PROGRESSIONS
Chapters 7 through 10 individually covered the sequences, RNI, RADR, ROP, and STO. This chapter
emphasizes the progression of sequences used during
execution of instructions. Some instructions use only
one sequence, others use two or more, and one instruction could use all four sequences.
The following pages are groupings of instructions
that use a definite sequence progression in their execution.
235
These instructions use only RNI:
Stop
00.0
Unconditional stop
Jumps
00
02
03
Miscellaneous jump
Index jump (IJ)
AQ jump (AZJ, AQ])
Skips
04
05
10
A, Q, or nb = Y*, skip
A, Q, or Bb = Y, skip
Index skip
Shift or scale
(may be indexed)
12
Shift A (SHA)
Shift Q (SHQ)
Shift AQ (SHAQ)
Scale AQ (SCAQ)
13
No address,
arithmetic, enter,
or logic
11
14
15
16
17
Enter A with 17 -bit address
Enter A, Q, or Bb with Y
Increase A, Q, or J3h by Y
Selective complement (exclusive OR) of A, Q, or Bb with Y
Logical product (AND) of A, Q, or Bh with Y
IRT
53
55
55.0
55.4
Interregister transfer (24-bit precision)
Interregister transfer (48-bit precision)
Select ISR
Select OSR
BCD-shift E,
E jump, set 0
60
Shift E, E zero jump, set D
77 instruction* *
77
Sensing, selecting, interrupt, and control functions
These instructions use RNI to RNI.
second instruction word.
Block operations
71
72
73
74
75
76
The first RNI reads the first instruction word, the second RNI reads the
Search
Move
Input, character
Input, word
Output, character
Output, word
The instruction progression in one instruction is RNI to RADR.
IJnconditional jump
01.4
Unconditiona 1 jump
*y = operand (lower 15 bits of the instruction word)
**77.64 (Write PF) and 77.65 (Read PF) fall in this group only if Multiprogramming module is not present.
77.610000 (Test Memory Availability) is excluded from this group.
236
These instructions use RNI to ROP progression. The RADR sequence is optional and depends on the programmer's
choice. Indexing may be used to modify the indirect address and/or the execution address.
Loads
20
21
22
23
24
27
54
Arithmetic
or logical
30
31
35
36
37
50
51
52
77.61
77.65
Load
Load
Load
Load
Load
Load
Load
A (LDA)
Q (LDQ)
A character (LACH)
Q character (LQCH)
A complement (LCA)
logical (LDL)
index (LDI)
Add (ADA)
Subtract (SBA)
Selective set (SSA)
Selective complement (SCA)
Logical product (LPA)
Multiply (MUA)
Divide (DVA)
Compare (CPR) (within limits test)
Test memory availability
Read Page File
These instructions use RNI to STO progression. The RADR sequence is optional for the 4X instructions but
neither indexing nor RADR is possible for the 00. 7 instruction. Indexing may be used to modify the indirect
address and/or the execution address.
00.7
Store
40
41
42
43
44
46
47
77.64
Return Jump
Store A (STA)
Store Q (STQ)
Store A character (SACH)
Store Q character (SQCH)
Store lower 15 bits (SWA)
Store lower 17 bits (SCHA)
Store index (STI)
Write Page File (APF)
One instruction uses RNI to ROP to STO sequence progression.
struction. The instruction is:
Storage shift
10.0
Indirect addressing does not apply to this in-
Storage shift (SSH)
One instruction has a sequence progression of RNI to RADR to ROP to STO. Inclusion of RADR is for indirect
addressing. It would not always be necessary; it depends on programmer's choice. Indexing maybe used to
modify the indirect and/or execution address.
Replace add
34
Replace add (RAD)
237
Double-precision load instructions use RNI to ROP to ROP sequence progression. RADR sequence could be used
with indirect addressing. Indexing may be used to modify the indirect and/or execution address. The instructions are:
Load or
arithmetic,
48-bit precision
25
26
32
33
57
Load AQ (LDAQ)
Load AQ, complement (LCAQ)
Add to AQ (ADAQ)
Subtract from AQ (SBAQ)
Multiply AQ (MUAQ)
Divide AQ (DV AQ)
60
61
62
63
Floating-point
Floating-point
Floating-point
Floating-point
56
Floating-point
arithmetic
addition to AQ (FAD)
subtraction from AQ (FSB)
multiplication of AQ (FMU)
division of AQ (FDV)
There is one double-precision store instruction. It uses RNI to STO to STO sequence progression. RADR sequence could be used with indirect addressing. Indexing may be used to modify the indirect and/or execution
address. The double-precision store instruction is:
48-bit store
45
Store AQ (STAQ)
Two instructions have optional sequence progressions. Normal progression is RNI to ROP to ROP ... to Rap
during the search operations; however, if an interrupt occurs, the Rap to Rap sequence is broken and RNI is
initiated. These two instructions are:
Search
06
07
Masked Equality Search (MEQ)
Masked Threshold Search (MTH)
Figure 263 is a block diagram of the possible sequence progressions for instructions in the 3300 Computer.
There are several AND gates (A through R) shown
on figure 263. These AND gates (based on instruction
function translators) determine which sequence pro-
gression will be used by the instruction being executed.
Table 15 is a worksheet based on figure 263, the 3300
Computer System Logic Diagrams, and the previous
pages of this chapter. NOTE: AND gates A and C have
been filled in for you and are meant to serve as a guide
in filling out the other AND gates.
0
~
,
~ (
L l1
STO
Q
J
P
or
Figure 263. Block Diagram of Sequence Progressions
?3B
STO
d
Table 15. AND GATES FOR SEQUENCE PROGRESSIONS
TRANSLATION
GATE
LOGIC TERM
Arithmetic not busy
A
LOGIC PAGE
VlO9
2-7
FSS8 and V17l
2-5
B
C
D
E
71 throUlrh 76
F
G
H
I
J
K
L
M
N
0
P
Q
R
The following information traces one instruction
through its entire execution. Check it for accuracy
against the prints in Logic Diagrams and answer the
questions.
Timing for a replace add instruction with one indirect
address:
RNI
N072
V087
V014
NOSI
NOSO
Vl17
NOSO
VIIS
Vl16
NOSI
NOSO
V06l
VOOO
VOOI
VOO2
VOO3
VOO4
VOOS
VOO6
VOO7
VOO8
VOO9
VOlO
VOll
V080
Resynced manual start
Input to RNI
Request bus on RNI
Obtain bus priority
Address stabilization
Request storage
Breakpoint comparison timing
Breakpoint comparison timing
Test BPI
Storage reply
Drop bus request
Access time -out
Access time-out
Access time -out
Access time-out
Access time-out
Access time-out
Clear F and release bus
Instruction to F
Instruction decode
Test interrupt
Instruction decode
End of RNI
RADR
VlO9
VllO
NOSI
NOSO
Vl17
NOSO
VIIS
Vl16
NOSO
NOSI
V061
VOOO
VOOI
VOO2
VOO3
VOO4
VOOS
VOO6
VOO7
VOO8
VOO9
V082
Arithmetic not busy
Request bus on RADR
Obtain bus priority
Address stabilization
Request storage
Storage reply
Drop bus request
Access time-out
Access time-out
Access time-out
Access time-out
Access time-out
Access time-out
Clear lower F and release bus
Bus to lower F via EXX2
F decode
End of RADR
239
Arithmetic not busy
Request bus on ROP
Obtain bus priority
Address stabilization
Request storage
Breakpoint comparison timing
Breakpoint comparison timing
Test BPO
ROP
VI09
VllO
NOSI
NOSO
Vll7
NOSO
VIIS
Vl16
NOSI
NOSO
V061
VOOO
VOOI
V002
VOO3
V004
VOOS
V006
VOO7
VOOS
V009
VOS4
Storage reply
Drop bus request
Access time-out
Access time -out
Access time-out
Access time-out
Access time-out
Access time-out
Clear DB register and release bus
Bus to DB register and start arithmetic
N691
End of ROP
VSOO
STO
VI09
VllO
NOSI
NOSO
Vl17
NOSO
VIIS
Vll6
NOSI
NOSO
V061
VOOO
VOOI
V002
V003
V004
VOOS
V006
V007
VOS6
Arithmetic not busy
Request bus on STO
Obtain bus
Address stabilization
Request storage
Breakpoint comparison timing
Breakpoint comparison timing
Test BPO; N400
N401 (Clear DBR)
N41X (EXX2 -+-DBR, direct)
Storage reply;
Drop bus request;
Access time-out
Access time-out
Access time -out
Access time-out
Access time -out
Access time-out
Release bus
End of STO
2. At best, RADR requires
usec.
3. At best, ROP requires
usec.
VSOI
VS02
VS03
VS04
VSOS
VS30
VS31
VOS7 Input to RNI
V014 Request bus on RNI
For problems 1 through 14 assume Multiprogramming
module not present and system not in Executive mode.
1.
At best, RNT rE"qllirPR _ _ _ _ _ _ _~_0 timeR.
______ usec.
240
~
times,
~
times,
~ times,
4. At best, STO requires
usec.
~ times,
S. At best, the total is
usec.
-----6. Without indirect address ing the total is _ _ _ __
~ times,
usec.
7. At best, bus priority per cycle is _ _ _ _ __
~ times,
usec.
S. Would the best time you determined for RNI apply
to all RNI sequences?
9. Would the best time you determined for RADR apply
to all RADR sequences? _ _ _ _ _ _ _ _ __
10. Would the best time you determined for ROP apply
to all ROP sequences? _ _ _ _ _ _ _ _ _ __
II. Would the be st time you determined for STO apply
to all STO sequences?
12. At best, how much more time wOl}ld be added to
the execution ofthe replace add il\"$t\-uction if two
levels of indirect addressing were u·sed? _ _ __
Three levels? _ _ _ _ _ _ _ __
13. Question S asks what the best total time would be
for an RAD instruction. What different factors
could make the total time longer, not counting
RADR sequences?
a. Obtaining the bus during RNI.
b. Storage reply.
c. Arithmetic busy at entry to ROP sequence.
d.
e.
f.
g.
14. Whywould obtaining the bus cause so much delay?
15. How much time would the use of the relocation
feature of the 3300 Computer add to a sequence?
Remember, there is only one bus system. It is
shared by program control and block control, each
having equal priority to obtain it. Figure 264 shows
how the bus system could be used.
It is important to keep in mind that figure 264 is only
meant to show how the bus system could be used. It
is not meant to show all the uses of the system; the bus
system never follows that type of progression.
Main control ~
has the bus
to accomplish
an RNI
sequence.
Block control
has the bus
to accomplish
or process
an input.
~
Main control ~ Block control ~ Main control --. Main control
has the bus
has the bus
has the bus
has the bus
to accomplish
to accomplish
to accomplish
to accomplish
an RADR
anROP
an output.
anSTO
sequence.
sequence.
sequence.
Figure 264.
Example of Bus System Usage
241
CTiii
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SEQUENCES Worksheet
Assume that the Multiprogramming module is not
present and the system is not in Executive mode for
this problem.
You, the maintenance man, are sum)TIoned to the console by the computer operator. He tells you that the
load Q instruction from memory location 14063 is not
operating properly . He executes a21 0 14063 and says,
"See, the uppermost bit, bit 23, always comes up a O. "
(Q) is 12106034 is all the information he can supply.
One of the first things a good maintenance man would
do would be to verify that a load Q will not work.
Figure 265, (page 242) is an unmarked block diagram
of the system. Draw in the data flow path for an operand moving from storage to Q register Do this first,
then continue.
Study the block diagram, then list the steps of the
operation you would perform to verify the trouble.
Reread the problem, make another choice (from
a to d above), and follow the directions given.
(2) After execution of the
(9
0
This knowledge is important!
What circuitry is common to both a load A and
a load Q? (List the common flow paths. )
The following list contains some logical first steps,
one of which you might possibly have written above.
Look through the list for the operation you would have
performed. If the operation you listed is there, follow the directions given.
@ a.
b.
c.
d.
e.
You entered (via keyboard to storage) a load A
from location 14063 (the same address referenced by the load Q) . You then executed the
load A. If load A was your choice, go to step
2, item a.
You manually entered (via keyboard) all 7s to
Q register (at least to the upper digit position).
If this was your choice, go to step 2, item b.
You swept contents.:pf location 14063 to C register for observation'. If this was your choice,
go to step 2, item c ..You entered (via key'board) ~11 7s into A register and stored the contents" of A in memory .
Then you executed a load A from that location
in storage. If this was your choice, go to step
2, item d.
If the operation you performed was not listed
above perhaps your choice was not one of the
most logical ones you could have made. Analyze your operation. What help is it to you in
verifying that a load Q does not work? Perhaps
the operation you chose would have helped you
and it was just not listed above.
Either way, now that you have read through
the list of logical choices supplied above, which
one of them do you feel is the most logical?
load A from memory location 14063 the contents of A register is 12106034.
Knowledge gained: The uppermost bit coming
to A register as a 0 could be significant. How do
you knO~lJ that t.lJe uppermost bit (bit 23) in memory is a I? You do not know, do you? You possibly wasted a bit of time here, especially if the bit
in memory is a O!
All is not wasted though. It's possible that you
have learned some important things, even if they
are not obvious to you at this point. If an error
does exist it has to be in some circuitry that is
common to both a load A and a load Q instruction.
You should have listed storage, transmitters,
receivers, EXX2, DB register, r4, and Xl. Study
the block diagram in figure 265 and verify that
these are the only common circuits. Keep in mind
what you might have learned in this step, go back
to step 1, and make another choice. Remember,
you are trying to verify the existence of an error.
(2)
After keyboard entry of all 7 s to Q register, (Q)
~ is 37777777. C register contained all 7s when
TRANSFER was pushed.
Knowledge gained: Q itself could be bad. The
flip-flop for bit 23 possibly does not hold a 1 even
if it gets there. There is circuitry other than Q
involved during keyboard entry to Q. List the steps
of the flow path for keyboard entry to Q. Use figure 265 for reference.
It is known that an error exists. Further, it is
known that the error has to be in one of the following circuits in the Q flow path: Keyboard, MXXX,
C, C7X2, DB register (EXX2 enable), 14 , Xl, II,
or Ql. Because the 7s got to C correctly, three
circuits can be eliminated. On figure 265 draw a
line through the circuits that can be eliminated.
243
The original problem was a load Q not operating. It is known that an error exists now because
manual entry failed. C7X2 is used on the manual
entry to Q path, but not on a load Q, thus C7X2
can be eliminated also. (It should be crossed out
on figure 265, as should M33X and C register.
The error must exist in one of the following circuits: EXX2, DB register, 14, Xl, Ll and Ql.
It is also known that storage is okay (unless there
are two errors) because keyboard entry does not
involve storage; the enter operation is failing, thus
the error could not be in storage. Go to step 3 .
(2) After you swept the contents of location
0"
14603 to
C register for observation you found that C contained 52106034.
Knowledge gained: You know memory contains
a 1 bit in position 23. You also know that the path
from storage to C register is okay. Referring to
figure 265, what is the path for information traveling from storage to C?
You should have listed storage, transmitters,
receivers, EXX2, and C. You now know there is
a fault. Further, you know it is not in the storage
circuits because the information comes to C register correctly. What would be a logical choice
of operations now?
Look through the following list for the operation
you chose and for the directions given:
1) You entered (via keyboard to storage) a load A
from location 14063 (the same address referenced by the load Q) . You then executed the
load A. If load A was your chOice, go to step
5 •
2) You manually entered (via keyboard) all 7s to
Q register (at least to the upper digit position).
If this was your choice, go to step 2 , item b.
3 ) You entered (via keyboard) all 7 s into A register and stored (A) in memory. Then you executed a load A from that location in storage.
If-{;fl:iH-was- YOUr "ehuiee, go~tosteP" -:2 ,":item" d •
If the operation you performed was not listed
above perhaps your choice was not one of the most
logical ones you could have made.
Analyze your operation. What help is it to you?
Perhaps the operation you chose would have helped
you, but it was just not listed above. Either way,
now that you have read through the list of logical
choices supplied above, which one of them doyoil
feel is the most logical? Reread the problem,
make another choice (from a to c above), and follow the directions given.
G) As you enter (via keyboard) all 7s to A register
@5 you notice that A always comes up with a 37777777,
yet C is always all 7s at the time of transfer.
There is no need to do the store A or load A because something is wrong in the path from the
keyboard to A, and this path does not use storage.
Referring to figure 265, list the steps in the flow
path for keyboard entry to A register.
It is known that an error exists. Further, it is
known that the error has to be inone of these circuits in the A flow path: keyboard, MXXX, C,
C7X2, DB register (EXX2 enable), 14 , Xl, adder,
10 , AI. Because the 7s got to C correctly, three
circuits can be eliminated. On figure 265, draw
a line through the three that can be eliminated.
The original problem was a load Q not operating
properly. It is known that an error exists now because manual entry failed. C7X2 is used on the
manual entry to A path but not on the load Q path,
thus C7X2 can be eliminated also. The error must
exist in one of the following circuits: EXX2, DB
register, 14, Xl, adder, 10 or AI.
The adder is used for entry to A but not for a
load Q, thus the adder can be eliminated, as can
10 and AI. This leaves just EXX2, DB register, 14,
or Xl. Go to step 4 .
CD enter
You know an error exists because you executed an
to (via keyboard) and it did not function
Q
properly. You have already localized the problem
and started eliminating circuitry.
You know the error has to be in one of the following circuits: EXX2, DB register, 14 , Xl, II,
or Ql.
What operation could you perform that would
eliminate II and QI?
-----------------------
To inject a thought here - -why not try keyboard
entry to A with all 7s? If it fails, then the fault
could not be II or Ql; instead it would have to be
in some circuitry common to both an enter to A
o
and an enter to Q. If it does not fail, then the error has to be in either II or Ql.
Assuming that you tookthe bait, when you tried
to enter to A, C got all 7s but A got 37777777. II
and Ql cannot be faulty. Cross them out on Figure 265.
Now it is known that both an enter to A and an
enter to Q fail. The error has to be in circuitry
common to both. The following common circuitry
could be at fault: C7X2, DB register (EXX2 enable), 14 , and Xl.
C7X2 was eliminated in step 2, item b. EXX2
can be eliminated for a slightly different reason.
EXX2 is in the load Q path, but not in the enter
path which also fails, therefore EXX2 could not
be at fault. (Cross it out on figure 265.) This
leaves DB register, 14 , and Xl to be eliminated.
Go to step 6 .
You know an error exists because you executed
an enter to A (via keyboard) and it did not function
proper ly . You have already localized the problem
and started eliminating circuitry •
You know the error has be be in one of the following circuits: EXX2, DB register, 14 , Xl.
EXX2 can be eliminated for a reason similar to
the one for which C7X2 was eliminated earlier
EXX2 is in the load Q path, but it's not in the
enter to A path which also failed. Therefore,
EXX2 could not be at fault. This leaves DB register, 14 , and Xl to be eliminated.
Go to step 6 .
0
@ After execution of the load A from memory location 14063, (A) is 12106034.
Knowledge gained: The uppermost bit coming
to A register as a 0 has eliminated considerable
circuitry. An error does exist and it has to be in
some circuitryconunQ';tO both a load A and a load
Q instruction. This knowledge initself is important.
What circuitry is common to a load A and a load
Q? (List the steps in the common flow path.)
o
Go to step 6 .
The bad circuit has been narrowed down to DB register, 14 , or Xl.
Keep in mind that the fastest troubleshooting
procedure is to eliminate as much circuitry as
possible with operations executed from the console.
What operation could be performed to point at
or to eliminate Xl?
-------------------------
Another hint: X is fed by inverter ranks 2, 3,
4, and 6. (Look at figure 265.) It doesn't figure
that X could be eliminated if an oper ation that used
X also used 14; so choose an operation that does
not use 14. Ranks 1, 2, and 3 are in the A and Q
circuits, and so far it has not been possible to get
bit 23 into either of these registers, so that pretty
much leaves you with 16 •
16 feeds Xl and 16 is fed by the B boxes and IS •
IS seems like a good bet. Enter an enter Q instruction with a negative number and sign extension,
then execute it.
Doing an enter Q leaves all 7s in Q. Xl must
be okay (cross it out on figure 265), leaving DB
register and 14 as possibles.
Go to step 7 .
(2) Some more facts are known.
The error has to be
in either DB register or 14.
It is possible to get all 7s into Q via the enter
instruction with sign extension.
Considerable benefit comes from being able to
get all 7s into the register. Now the 7 s can be
stored from Q and further circuits can be eliminated.
When a store is followed by a sweep to C, all
7 s return to C. Which circuit, DB register or I~,
can be eliminated?
Cross it out on figure 265. DB register should be
okay because the path for a store Q is:
-------------------------
Ql ~13--'Xl~ 7-. EXX2-. DBR-.storage
Ql, 13 , Xl, 17, and storage are not involved in
You should have listed storage, transmitters,
receivers, EXX2, DB register, 14 and Xl.
Study figure 265 and verify that these are the
only common circuits.
The sweep operation that you performed ear lier
eliminated the storage circuits and an inverter
rank. What three circuits have not been eliminated?
the circuits that are to be eliminated.
error has to be in
Go to step 8 .
Thus the
------------------------
CD YEP!
14.
Now what? Locate the logic card and replace it.
What manual would you use to find the physical location of the 23rd bit of 14?
------------------
-----------------------------------245
The logic diagrams for the 3304 Basic Processor
would be a good bet. Look in the table of contents
for 14 (standard arithmetic section). Turn to that
page in the diagrams and locate the 23rd bit and
list its physical location.
You should have 2K88A. Go ahead, replace that
card and try a load Q from location 14063. After
execution, Q contains a 52106034, which is correct. Congratulations for fixing the trouble.
There were many steps to this problem. You
possibly did not agree with the sequence of steps
through which you were led in diagnosing the problem but if you remember these important things,
you'll do well.
1. Always prove or disprove the first assumption
before you fix anything.
2. Localize the problem to one area of the system
as rapidly as possible by performing operations
that use common circuits.
3. First try to eliminate all possible commoncircuitry via the console. It's faster than probing
around with a scope. Besides, if you can push
a few buttons, you make a better impression
than when you state it must be so-and-so and
replace it without even using a scope.
4. Repair the faulty component.
Only a very few instructions in the entire repertoire
may be executed. All other instructions" die" leaving
the console in the following configuration depending
on which sequence the failing instruction would use to
accomplish its execution. If RADR, ROP, or STO
sequence were required, the console would be dark
except for the appropriate sequence indicator being lit.
Instructions that can be executed are all common to
RNI sequence:
Stops
Jumps
Skips
Shifts or scale
No-address arithmetic instructions, enters
or logic
Intraregister transfers
77 series (connect, senses, etc.)
It is also possible to initiate block operation.
It should be already apparent that RNI is okay. Whatever is wrong must be common to all other sequences.
CLUES:
1. C01Jld stQX~ge be at fault?
If th~_prQgram were written so that all of the instructions
were in storage module 0 and all operands were in
module 1, could storage be at fault? _ _ _ _ __
24R
2. This problem is common to several sequences.
The most logical place to look for the fault would
be in control. Most of the common circuitry for
the sequences is shown on page _ _ _ _ _ _ __
of Logic Diagrams.
3. Could the arithmetic section be at fault? ____
If RADR and RNI worked and only ROP and STO
failed, could the arithmetic section be at fault? _ _
Why? ___________________________
In your own words relate what you think would be at
fault: __________________________
In diagnosing a problem you have discovered the
following facts:
1.
2.
3.
4.
The arithmetic area works; it adds, subtracts,
multiplies and divides. It also shifts correctly.
You can store and retrieve information from memory because you keyed in a ST A and a LDQ instruction and they both operated correctly.
The computer reads and executes instructions correctly. Proof is in item 2.
Instruction address modification works because
you b-modified an instruction and it worked.
From the facts you have learned in the four operations
you performed you feel quite sure the error is in one
sequence.
What sequences are checked by item 2? _____
and
What sequence is checked by item 3?
------and
----Are any additional sequences checked by item 4?
-----
What sequence has not been checked?
----Supply one instruction that will check the remaining
sequences.
It appears that a modified load A instruction is not
operating correctty. The instruenoii arrives iii F
register properly, in program control.
When the instruction is executed the number that
arrives in A register is not the proper one. Listed
below are the internal sub-sections of the 3300 processor. If the sub-section could be at fault, write in yes.
If not, write no.
explain why.
Block Control?
Whether your answer is yes
~
no
---------------, because ---------Multiprogramming module? _ _ _ _ _ _ _ _ _ __
because _________________________________
Program Control? _____________ , because
I/O? _____________ , because __________
Standard arithmetic, first pass?
be cause_________________________
S bus? _________, because _________
Standard arithmetic, second pass? _________
because ________________________________
D bus? _________, because _ _ _ _ _ _ __
Storage? _______________ , because _________
247
STORAGE ADDRESS BUS
I
STORAGE
COMPUTATION
MODULE
SECTION
H
CONSOLE
I
DATAlaus
I
1
COMMUNICATIONS
MODULE
PROCESSOR
Figure 266. System Block Diagram
CHAPTER 12
ARITHMETIC CONTRa LS
GENERAL DESCRIPTION
The standard arithmetic section of the processor
is located within the computer section of the system
(figure 266).
The system block diagram of the 3204 Processor is
shown in figure 267. Note the inputs to and outputs
from the standard arithmetic section.
Figure 268 shows the detailed block diagram of the
standard arithmetic section. Throughout this chapter
references are made to figures 267 and 268. Study
them now and refer back to them each time they are
mentioned.
The arithmetic section performs all loads, stores,
shifting, scaling, logical, and arithmetic operations.
This chapter discusses the logical operation of the
arithmetic registers, the adder pyramid, the arithmetic timing controls, and the arithmetic sensing fog1:c ..
Figure 268 is a block diagram of the arithmetic
section which shows all paths for data exchange within the arithmetic section.
REGISTERS
The arithmetic registers provide temporary storage
for the operands used in program execution. The arithmetic section has five registers: A1, A2, Q1, Q2, and
X. The contents of A1 and Q1 are normally displayed
on the console when the computer is stopped.
As each register is described in the following discussions, refer to figure 268 to place it in the proper
perspective to the entire section. Also, refer to it in
3300 Logic Diagrams to see all hits represented.
249
BASIC ARITHMETIC
9;I~S
~
MC
E~ (FP)
FORCED
F'
~
,-
20+21
(KVat) EIITRY
OFAOItQ\
SH
CT
RE6
RK 1
Figure 267.
Arithmetic Inputs and Outputs
Al Register
The 24-bit Al (arithmetic) register is used in nearly
all arithmetic and logical operations. (AI) may be
transferred to A2 and (A2) added to the contents of a storage location or the contents of another register. The
sum is then placed in Al or it can be placed in storage. (AI) may be shifted right or left, and separately
or in conjunction with Ql. Al may also hold a control
quantity which conditions certain jump, skip and search
instructions.
Inputs to Al are made from:
1. J4XX inverters andM4XX FFs. These inputs transfer the internal status code to bits 00-11 of A1 and
the contents of the interrupt mask register to bits
12-23.
2. 1 0 inverter rank. The sum from the main adder,
sum from the optional adder, and (Q2) are transferred through 10 into Al directly. (A2) is transferred through 10 into Al either directly, left
shifted (end-around) one place, or right shifted
(end-off, sign extended) one place.
3. II inverter rank. Bit 23 of II feeds bit 0 of Al
. qt!rtnga J~ft .sbHtAQQrJ.eft .shift. A.
4. E175-E177 and E185-187 inverters. These inputs
are used to transfer the contents of the condition
register, ISR, and OSR to AL.
Refer to Logic Diagrams, page 2-127, for bits 0-7
of Al register and 10 inverter rank.
250
QI Register
The 24-bit QI register (auxiliary arithmetic) assists
Al register in performing arithmetic and logical operations. (QI) may be shifted right or left, separately
or in conjunction with AI. QI may also be used with
Al register to form double-length register AQ. QI
serves as a mask register for certain instructions.
Inputs to QI are made from:
1. E L (optional arithmetic) register. The inputs are
E4XX, E5XX, and E6XX.
2. I I inverter rank. The sum from the main adder
and (X) are transferred through I I directly into QI.
(Q2) and (A2) are transferred through II into QI
either directly, left shifted (end-around) one place,
or right shifted (end-off, sign extended) one place.
3. 10 inverter rank. This rank is used together with
the II rank when shifting Q or AQ.
Refer to 3300 Logic Diagrams, page 2-133, for bits
0-7 of Q1 register and 11 inverter rank.
A2 Register
The 24-bit A2 regh::ter is used pr-imarily as one of
l-itt;; tt~.f fei;:HJe:i:o" Qui;l:i piti:CtHin AZ cHiU XiHiHieHi ~
ately begins to propagate through the adder. A2 is
also used in conjunction with Al register for operations
involving a shift of A or AQ and to allow an exchange
of (A) and (Q) during the execution of multiply and divide instructions.
POSITIVE
INTERRUPT MASK
I/O STATUS,CIR,
CR,ISR,OSR
a
ZERO
ARITHMETIC SECTION
NEGATIVE
(OPTIONAL)
RIGHT I
LEFT I
RIGHT I
LEFT I
INVERTERS
OPT ADDER
UI24 ~U147
"02
~ A2~
A2
X
ADDER
(OPTIONAL) I85X -+---<)--1
RIGHT lOa
LEFT lOa
RIGHT lOa
LEFT lOa
POSITIVE
OPTIONAL
x"Wl'ie-reasme' aOde:rlrotll1()"STomerControi
Data computers are subtractive accumulators.
There are 24 stages in the adder, one stage associated with each bit in the tWG> feeder registers, A2 and
X. Inputs to the adder are made only from these regis2!i2
INVERTER RANKS
Most of the parallel transmission paths between
registers involve a rank of inverters. The major
parallel transmission paths and inverter ranks of the
arithmetic section are shown in figure 268.
10, 11, 12 , 13 , and 14 are the arithmetic section
inverter ranks which serve as the main feeders to
registers AI, QI, A2, Q2, and X.
The various transfer paths for the inverter ranks
are listed in table 16.
Al (direct, left 1, or right 1);
shift count register;
bit 23. bit 0 of QI;
bit O.bit 23 of QI;
lower 15 or 17 bits to F1
index registers BI, B2, B3
QI (direct, left 1, or right 1);
bit 23 . . bit 0 of Al
X, A2 (direct, left lOS, or right lOS);
bits l6-23.bit 0-7 of Q2;
bits 0-7.bits 16-23 of Q2
X, Q2 (direct, left lOS or right lOS);
bits 16-23... bits 0-7 of A'l.
X
ters. The data is gated into the feeder registers.
Operations within the adder are not clocked, so four
phase times (including the time that data is being
placed in the feeders) are allowed for adder propagation before the output of the adder is sampled.
0<•. The 3300 Adderis-'Clesigne'a so that Timely
tended in size to 4S bits without increasing adder propagation time. The optional f]oating-point/douhle-precision hardware package contains the logic necessary
to do this.
be ex-
The expanded adder is used only for the floatingpoint/double-precision instructions. When any other
instruction is being executed the optional adder is disregarded. * One operation that occurs quite frequently
in the 3300 computer is that of using the adder as a
data path in which case a value is added to zero. The
sum (equal to original value) is transferred to A register (example-the LDA lnst.)o No real addition has
occurred but DATA has been moved. *Note: The double precision add or subtract do not require optional
hardware.
BINARY ARITHMETIC
The binary number system is the basis for the representation and manipulation of all information within
the computer. The 3300 Computer uses l's complement binary arithmetic.
The adder forms the sum of two numbers by adding
them directly. For example:
0111
+0100
0011
1
1011
augend
addend
partial sum
carry
sum
Subtraction is performed by the "adding the complement" method. The difference of two numbers is
found by first complementing the number to be subtracted, then adding the complement of the subtrahend
to the minuend.
For example:
1100
- 0010
1010
minuend
subtrahend
difference
The computer performs the subtraction thus:
1100 minuend
+ 1101 complement of the subtrahend
1001 partial difference
+
1 end -around carry
1010 difference
These references contain a further description of
number systems, including binary arithmetic: 3300
Reference Manual (see appendix section) and An Introduction to Digital Computers.
THEORY OF THE ADDER
The adder generates and recognizes the carry signals '
which occur when two numbers are added.
There are four cases which must be considered in
binary addition. These are:
*The double-precision add or subtract do not require
0ptional hardware.
2. Pass
1. Satisfy
Augend
Addend
Sum
a
a
+0
+1
1
o
3. Pass
1
+0
4. Generate
1
+1
a with a carry of 1
to the next higher stage
1
Satisfy: For case 1, the stage will satisfy an incoming
carry. That is, the stage does not generate a carry
during addition and, if a carry input is received, it
will not be passed on to the next higher stage.
Pass: For cases 2 and 3, a carry input cannot be
satisfied within the stage and must be passed on to the
next higher stage. Thus, a pas s is generated by all
stages with unlike input signals from A2 and X.
Generate: For the addition of 1 + 1, case 4, a partial
sum of 0 is obtained and a carry is generated and passed
on to the next higher stage. A carry input is not satis fied by a stage of this type for it always generates a
carry of its own.
Signals within the adder form a double pyramid as
shown in figure 269. The adder has 24 input stages,
one for each bit of A2 and X. These stages are combined into eight 3-bit groups Stages and groups are
checked for carry generation and ability to pass a
carry. Multiple-group generate and pass signals are
then formed. Group carry inputs and stage carry inputs
are generated next. Finally, the stage-generated
signals are compared with the carry input signals at
a rank of output inverters. These inverters produce
the complement of the sum of X and A2.
The generation of individual signals is treated more
fully in the discussion which follows.
If the double-precision/floating point option is present, an identical 24 bit adder unit is wired to the left,
or above the standard arithmetic adder.
This provides: 48 stages (0-47)
16 groups (0-15)
4 sections (0-3)
The standard arithmetic adder is sometimes referred to as the right adder and the expanded adder as
the left adder. In any case the adder works as a 48 -bit
adder, the output of which is always
0
sum.
Stage -Generated Signals
During addition* the first level of adder translation
*The description to follow is concerned with the use of
the adder in true addition only. The adder can also
form the logical product and the selective complement
of two numbers, but this is discussed elsewhere.
253
Outputs to 24 stages of 10
24 stages (0 to 23)
Stage outputs
Stage carry inputs
Group carry inputs
(including end -around carry)
Section pass
and carry generation
8 groups (0 to 7)
3 stages per group
2 sections (0 and 1)
4 groups per section
Figure 269. Adder Pyramid
occurs at the individual stages. All 24 input stages
generate three types of signals:
1. Generate: A stage carry is generated by the LOXX
terms (where XX is the number of the stage) when
the corresponding bits of A2 and X are both 1 's.
L)
Bit 0- A2 A500
Bit 0- X
XOOO
Stage 0
LOOO
Pass
Group 0
Generate
2. Group Generate: A group carry is generated
(L40X = 1) only if one of the stages within that group
generates a carry and no higher stage within the
group generates a satisfy .
Stage 2 Carry L002
Stage 1 Carry L001
Stage 2 Pass U002
Stage 0
Like
3. Like: The U2XX inverters output a 1 when the
corresponding bits of A2 and X are both alike. There
is no distinction made between both l' s or both 0 's.
In this case, the bit in the true sum will be a 0 unless a carry input is made.
Group-Generated Signals
Second-level translations are made on eight groups
of three stages each. Two types of translations are
made:
1. Group Pass: A group pass (U3XX = 1) occurs only
when there is no satisfy within the group. If both
bits of any stage within the group are 0, U300 is
driven to a O. There is then a group satisfy.
254
Group 0
Stage 1
Stage 2
2. Unlike: The UOXX inverters output a 1 when the
corresponding bits of A2 and X are unlike. This
signifies a stage pass condition. In this case, this
bit in the true sum will be a 1 unless a carry input
is made.
A501
X001
Stage 0
Generate
Group 0
Stage 0 Carry LOOO
Group 0 Pass U300
MUltiple-group Pass and Carry Generation
Third-level translations are made on multiples of
groups. The translations are:
1. Multiple-group Pass: The U6XX inverters generate mUltiple-group pass signals. These indicate
that several consecutive groups contain no satisfy .
I
Pass Group 1 U401
~ U612
Pass
Pass Group 2
U402--.l
. Groups 1-2
2. Group Generate and Multiple-group Pass: The
eight groups are considered as two sections, one
containing groups 0-3, the other containing groups
4-7. Pass translations from groups 8 -15 are present
Generate Group 0
Pass Group 1 U401
Pass Group 2
L300
U402
Pass Group 3
order groups in that section pass the carry_
Generate
Group 0
and Pass
Groups 1-3
End-Around Carry
An end-around carry is generated when any group
produces a carry and that carry is passed by all higher
groups, including group 7 (group 15 for floating-point/
double-precision). Figure 270 shows the logic which
recognizes and inserts the end -around carry .
Special logic is required to handle the end -around
carry for 48 -bit precision add and subtract (32 and
33 instructions) .
U403
only when floating-pointjdouble-precision hardware
is in the computer. The L50X inverters come up
only when a group generates a carry and all higher
FADRl +32+73
F99a
F'iUiRl
J521
CARR~ fROM £liP !lDDER U702{J) F!i97
CARRY
lNH! 1
FROf'l GR01JP
'
(!
LSDoa'
1
L5C1
2
'.sO;: ,
U 00
l
U304
PASS GRPS
\l -7
U3CS
UJ06
J
2D1~B
K535
U6l'0
(II)
U30"1
I
PASS
L15S
in
5:~(~
U200
I
L7.
5T5
° uooc
[a)
UNLIKE
51G 0 ,
PA5SUOOO
SHIGE
°
+1
LOOO '
SUI'!
=
4 -15
~32+3J)(FADR1J
>i
cWfl-----t-l-------~~-,
Cs=
L',~~13A _______ --<.t----@0aA
I
I
2009'1
I
f
(FP 6U5~)(~)US01
(Fp
6
L403---r7-'--------J
2012B
3~
-LA-~~~ [~:~~~RDUND
'I
(
1(5
-D
BUSY)(PASS 12-1S)US02
Ol
DP
FI'IDR 1
J521
END-I'IROUND
CI'IRR'f
+1
'I
LS04
5
L505
6
LS06
7
L407-------'
GENERATE
PASS UDOl
1
2
f----------G--HlU102
IOP
U700
U701
1
1
F9 98
TII1E 5
GEN LflOl
V595
l
1- --=-EN=D----:-:I'IR:-::-O:-::UN=D-,C-I'I-=-:RR=..,
CRRRY
FROM
i
INPUT GROUP
-
-
-
-
(9)
r
__1'
GROUP
STRGE
CRRRY--CRRRY- - iNPUT
INPUT
Figure 270.
Group Carry Inputs
The fanout of adder signals begins with these fourthlevel translations. The carries and group pass signals
have now been determined. Atthis level, the multiple ..
group pass and generate signals are translated for each output group by inverter networks (shown in the diagrams), to determine if that group has an incoming
carry from a lower group. The end-around carry is
the group carry input for group O. (See figure270).
Stage Carry Inputs
Carry inputs are made to the rank of output inverters.
These are compared with the original stage translations
to determine the final sum.
The group carry input is inserted into the lower
stage of each group, thus effectively serving as the
stage carry input.
A stage carry input to the second stage of each group
is made if the lower stage generates a carry or passes
an incoming group carry .
A stage carry input to the third stage of each group
is made if the lower stages generate and pass a carry,
or if they pass an incoming group carry.
stage carry translators are shown in figure 270 (L10X,
L20X).
~L002
LIKE
-
--
-
SiAGE
GEN
2
j
-SUM
Logic for End-Around Carry
Generation of Final Outputs
The output of the adder is obtained from the UIXX
inverter rank (figure 270).. This output is the complement of the true sum.
The determination of the final output is made at this
rank. The original stage translations, like and unlike,
are compared with the group and stage carry translations.
Four possible cases must be translated (two AND
gates required) to determine the output.
Two conditions produce a true sum of 1 (UIXX = 0):
1. A2 and X unlike (UOOO =1), no carry input (LI00 = 1).
2. A2 and X like (U200 = 1), carry input (L200 = 1).
Stage
o
Group 0 Carry
Unlike
LI00
UOOO
Stage
o
Group 0 Carry
Like
L200
U200
J
UiOO
The other two possible conditions produce a true sum
of 0 (UI00 = 1):
1. A2 and X unlike (UOOO = 1), carry input (L100=0).
2. A2 and X like (U200 = 1), no carry input (L200=0).
Note that the last two conditions will cause both gates
into U100 to be disabled by zeros.
255
ADDER Worksheet
The following two programs are intended to provide
static additions that will help in troubleshooting the
adder. All of the terms in each rank will provide the
same output under normal conditions. Indicate the
SIGNAL
output for each rank for each program by filling in the
table below.
Master clear and press GO for each of the following
separate programs.
PROGRAM #1
00000: 14.400000
00001: 15.400000
00002: 77. 770000
PROGRAM #2
00000: 14.400000
00001: 15.477777
00002: 77.777070
LOXX: Stage generate
UOXX: Stage unlike
U2XX: Stage like
L3XX: Not group generate
L4XX: Group generate
U3XX: Group pass
U4XX: Not group pass
L5XX: Section generate
U5XX: Not groups pass
U6XX: Groups pass
U7XX: Not group carry input
L2XX: Group carry input
Stage carry input
L1XX: Not group carry input
Not stage carry input
U1XX: Not sum
IOXX:
Sum
This worksheet will familiarize the student with the
adder and, when completed, the sheet will aid in
troubleshooting adder malfunctions.
Referring to Logic Diagrams (Adder, pages2-119to
2-125 and the previous discussion in this chapter, circle
the proper answers for each question based on the
following problem.
Problem: Add 77777777
to 77777777
1. All LOXX terms will be outputting 1 's/O's because
all stages/groups are/are not generating.
2. The UOXX terms will be outputting 1 's/O's because
all bits are/are not the same.
3. The U2XX terms will be outputting l's/O 's
all stage s are I are not identic al .
becaus~
4. The U3XX terms will be outputting 1 's/O's because
they are/are not satisfying in the stages/groups.
5. The L50X terms have 1 's/O 's out because all/none
of the stages/groups are/are not generating.
DOUBLE-PRECISION EAC
A special case of end-around carry is double-precision add or subtract explained below.
A 48-bit add or subtract is performed using two,
three, or four passes through the adder. The steps
necessary for the add portion of the instructions are:
LOGICAL PRODUCT
The adder is used to form the logical product (AND
function) of two numbers for instructions 17, 27, 37,
and the search 2 cycle of the 06 and 07 instructions.
The logical product is formed according to the following rules:
1. The upper 24 bits of the two 48-bit operands [(A)
and (M)] are added during the first pass through
the adder. An end-around carry is blocked because
the +1 FFisclear, holdingL200to a 0 (figure 269).
Ifanend-around carry occurs (U700 or U701 = 0)"
EAC (end-around carry) FFand the +1 FF are set.
2. On the second pass through the adder the lower 24
bits of the two operands [(Q) and (M+1)] are added.
A carry from the upper bits (if present) is inserted
into group 0 of the adder (+1 FF is set, so L200 =
1). This addition may also produce an end-around
carry. If so, EAC and +1 are set; otherwise they
are cleared.
3. A third pass through the adder then begins, but is
allowed to continue only if an end-around carry has
occurred. On this pass, +1, the carry from the
lower 24 bits is added to the upper 24 bits of the
48 - bit sum. Once again this addition can produce
an end around carry. EAC and +1 are allowed to
remain set if carry occurs, or cleared if it does
not occur.
4. A fourth pass is now made. The carry from the
upper bits is added to the lower 24 bits of the sum.
There can be no more carries so EAC and +1 are
cleared. A fifth adder pass begins but it is blocked.
An example of 48 -bit addition thattakes four passes
through the adder is shown below;
A2
X
Logical product
o
o
o
0
1
1
o
1
1
o
0
1
The translation of a 17, 27, or 37 allows r070 _I078
to output l's (figure 271). All stage and gnmp carry
inputs are held to 0 by these inverters, locking out all
interaction between the 24 stages. The logical product
is determined then only by input stage translations.
As shown in figure 271, a bit in the logical product
is a 1 only if a carry is generated by the input stage.
Bit 0
Final
Output
Rank
Input
Stage 0
A2 and X = 1
A500
XOOO
LP
Generate
Sel.
Comp ..
1080
F979
17+27+37
+ Search 2 Cycle
Figure 271. Logical Product Generation
Upper 24 bits
777777778
000000008
777777778
Lower 24 bits
777777778
000000018
First Pass
000000008 Second Pass
Carry +18 /
Third Pass
Carry 18 000000008
I
Carry +18
000000008 Fourth Pass
00000000
000000018 Final Sum
SELECTIVE COMPLEMENT
The adder is used to form the selective complement
(exclusive OR function) for instructions 16 and 36. Ex..,.
clusive OR means one term or the other but not both).
The selective complement is formed according to
the following rules:
A2
X
Selective complement
0
0
0
0
1
1
1
0
1
1
1
0
The translation of a 16 or 36 allows 1080_1082 to
output l's (figure 272). These inverters prevent input
carrygenerationby holding all LOXX (generate) terms
to O. Since stage carries are locked out, there is no
interaction between adjacent stages.
257
As shown in figure 2 7~, a bit in the selective com pIe ment is a 1 only if A2 and X are unlike. Adder output
is the complement of the selective complement.
Bit 0
Generate
16+36
F97I
Selective Complement
)--+-I~:':"::....J-_...;;U~n1=i=k=e....V"t...:..::..:..:.J SC
A2 +X
A500
XOOO
Carry input
LIOO
Figure 272. Selective Complement Generation
ARITHMETIC CONTROLS
All arithmetic operations must be timed and signals
must occur in proper sequence. Timing and sequencing is determined by arit~metic controls which include
F2 register, arithmetic function translators, arithmetic timing chain, shift cycle timing chain, complement and swap cycle timing chain, inverter enables,
flip-flop translations, and the shift count register.
Although the arithmetic section contains independent
timing logic, it is directed by the main control section.
Main control reads an instruction from storage and, if
the execution of that instruction involves an arithmetic
operation, main control sends a start pulse to the arith metic section at the proper time.
Once indexing and/or indirect addressing have been
performed, the final execution of enter, shift, increase,
logical, load, and arithmetic instructions is performed
entirely by the arithmetic section with no aid from main
control. This frees main control to read the next
instruction while arithmetic simultaneously completes
the current instruction.
A relatively long time is required to process certain
instructions. It is possible that main control will have
read another instruction before arithmetic has finished
processing the current one. Therefore arithmetic busy
FF is set ¢ormultiply, divide, shift, BCD, and floatingpoint and some double -precision instructions) to lock
out . all¥--fw:thcI .sta.r.t. _..pu.ls.cs_- . Jf.-tr..c-IlCW--lr..suuction
requires use of the arithmetic section, operations in
main control halt after RNI and do not continue until
arithmetic operations are finished and arithmetic busy
signal drops. If an arithmetic reference is not required
258
by the new instruction, main control continues to operate and will execute that instruction.
F2 REGISTER
The contents of the upper nine bits of F 1 are duplicated in F2 arithmetic register when an instruction is
read from memory. This takes place during every RNI.
F2 register which controls the arithmetic enables is
decoded separately from the main control function
translations. To understand the necessity for using F2
for arithmetic function translations consider this case:
1. Main control reads an instruction which requires a
lengthy arithmetic operation.
2. Main control duplicates (F 1) in F2 and starts the
arithmetic timing chain. Main control has no further
operations to perform in executing this instruction.
3. Therefore main control initiates a memory reference for a new instruction word while the arithmetic
se~tion is executing the present instruction.
4. The new instruction word is received by main control and gated into F 1 while the arithmetic section
is still executing the previous instruction. (F 1) is
not duplicated in F2 until the arithmetic section has
completed execution of the previous instruction.
Note that step 3 effectively decreases program execution time, while step 4 insures proper instruction
execution of the new instruction in F 1.
The function code in FI is duplicated in F2 by the
logic shQwn in figure 273. The gating signal which
transfers the new word into F 1 (N206) also sets initiate
Fl-+F2 and the wait function. Wait function locks
out a start arithmetic pulse until the upper nine bits of
F 1 have been duplicated in F2 and decoded.
Figure 273. Fl to F2 Logic
During the first odd time after initiate F 1 ..... F2 FF
is set, a pulse H518 begins the F code transfer. However, this pulse is blocked under two conditions:
1. Interrupt sync, trap sync, or powerfail FFs are set.
The current instruction is superseded by one of
these operations and is reread when the interrupt
has been processed.
2. Arithmetic is busy (V 109 = 0). F 1 ~F2 is blocked
until busy signal drops. If main control must start
arithmetic before doing the next RNI~ it hangs up
~.atk.~-~1.tf~~ u.RtU~-d:ro.ps,.1l1""E2
occurs, and wait function is cleared. This hangup
occurs at the N6XX terms (start arithmetic).
If it is not necessary to use arithmetic, main control
continues instruction execution (figure 274).
Shown are three bits of F2 which duplicate bits 18,
19, and 20 of F1 register. N550 is the gating term.
N552 gates bits 21, 22, and 23. N554 gates bits 15,
16, and 17. Thus, every RNI sequence will cause F1
to be duplicated in F2. the contents of the upper nine
bits of F1 are put into F2 whether or not the arithmetic section is to be used.
F'as
FZ03
Figure 274.
F1 to F2 Duplication
As the signal passes down the chain (figure 275) the
control delay slave inverters gate F 1 ~ F2. The timing
chain consisting of H518, H519, and H520 serves to
initialize the arithmetic section.
Initializing of the arithmetic section involves clearing shift count register and sensing the signs of A and Q
registers. If (A) or (Q) were negative the fact would
be recorded in flip-flops.. This initializing of arithmetic occurs each RNI sequence even if arithmetic is not
to be used.
The arithmetic section function translators (F8XX
and F9XX) translate the 6-bit function code (from F2)
and the three designator bits. The results of the translations are used to gate the commands which carry out
the required arithmetic operations. (See Logic Diagrams, page 1-35.)
The major arithmetic timing consists of six control
delays. In most cases one pass for arithmetic timing
will be six ~ times long.
Shown are some of the common transfers that are
part of arithmetic timing. Note that clearing of registers occurs at an even time and transfer occurs at an
odd time. Only in a few special cases will you find the
opposite.
N691
(CLR A2X
ADDER-FEEDERS
CLR Q2)
~ATE
I~TO A2
10 X
CLR AI ,Q I GATE
19 TO AI
11 TO Qj
I TOQ2
Figure 275. Arithmetic Timing Chain (Simplified)
The arithmetic timing chain can be started by main
control, block control, or manual timing. In any case,
to start the arithmetic timing chain one of two flip-flops
must be set. Either KIOO/I0l (gtartarith .1) or KI04/105
(start arith 2) will be ~et to cause the start pulse from
N687, N691, N693, and N659 (figure 276). K100/101(startarith 1) andK104/105 - (start arith 2) are shown
in Logic Diagrams, page 2-7.
~+---+--f H5'1
INT
+ TRAP + POWEItf'AIL
K~13
.1140
.1506
.1319
.OU
WAIT FUNCTION
KYBD ACTIV[
i+"'Q
START
iOlOciOOl
Figure 276 .
K100/101 OR K104/105 Set
ADDRESS MODIFICATION (FADR)
There are two uses for the F ADR cycle. The first is
the adding together of address portion of an instruction
word and contents of an index register (Bb ) to form a
new address. The sum of m and Bb is gated back to
the lower portion of the F register to be used as the
address for a storage reference.
m+sb=M
The index register to be used can be determined by
the b designator of the instruction word (e .g., 20.1 or
20~2) or by the function code (e.g., fixed-index instructions 22.4 or 42. 4) •
Indexing may be required for a RADR, ROP, or STe:>
sequence. Thus, indexing will be initiated only at the
end of RNI or RADR sequence.
Address modification will be referred to as FADR
(form address).
F or the FADR operation there will be a function translation of indexing. This will cause a static enable of
the designated Bindex (clear side) to the 16XX inverter
rank in main control. There will also be a static enable
of the lower 15 or 17 bits of F 1 register to 15XX inverter
259
rank. These enables will be static during the FADR
operation (figure 277).
r-------------,
---+bc
Bb ---+ I6
I
~Adder---..IO__+!FL
FL~ I5~?
:
I
I
I
I
L_Ar~~~~ic s:.c~~_J
The lower 15 bits of Fl register are used for a wordaddressed instruction and the lower. .l7 bits are used
with a character -addressed instruction. For all F ADRs
main control will extend the sign on the value from :sb
and FL:
Example:
Values added
B1 = 34567
00034567 = B1 with sign
F = 20.177760
77777760 = F L with sign
Figure 2'77. The Flow Path for FADR
TIMING FOR FADR
TIME
V080 or
V082
TERM
K100/101
COMMAND
Start arith 1
CONDITION
Indexing
REMARKS
Provides entry to the indexing sequence at the end of
RNI or RADR.
When KIOl=l, it will set K536/
537 (FADR 1) and K596/597
(FADR 2) FFs.
The arithmetic section will perform the same operation determined by translation of the instructions function code. If F 1 and F2 registers hold a 50.2 the trans1ators tell arithmetic to do a mUltiply. This is not what
N691
N691
HI00
H510
V5IOjV530
H501
Clear X and A2
V100
H57l
H54l
KIlO/Ill
Clear
KlOO/lOl
KIlO/Ill
V501
H502
(Arith busy)
(Wait function)
X and A2 are cleared.
A2 is cleared by N520, N522, and N524 (Logic Diagrams, page 1-29). The output of the HXXX terms on
the AND gate to these N52X terms is a logical 1 in a
stable state. H510 going to a 0 because of its input will
V530
V530
VIOO
V100
arithmetic should do to form address M for anFADR.
When set, the purpose of FADR 1 and FADR 2 FFs is
to cancel function translations for the arithmetic sections. The flip-flops remain set during FADR.
permit N520, N522, and N524 to output 1 's, clearing
A2 at the next even time (effectively, V500).
N640, N642 and N644 will clear X register.
At the same time the following is taking place:
15XX to A2
16XX to Xl
I OXX to F
Enable 10 to F
Clear start arith. I .
Permits gating sum (M)
to FL later.
I6XX is gated to X and I5XX is
gated to A2.
x=sb with sign extension and
A2 = FL with sign extension
The sum of A2 and X will be formed by the adder.
A static enable from the adder IS output to the 10 inverter
260
rank is caused by J825, J826, andJ827 (Logic Diagrams,
page 1-34).
TllvlING FOR F ADR
COMMAND
REMARKS
CONDITION
TllvlE
TERM:
VS02
VS02
H503
H201
VS03/VS23
VS23
HS04
HIIO
V554
VS04
VIIO
VIIO
K596/597
HSOS
KOOO/OOI
H271
VIIO
HIOS
H271 (IO to F, 1-10)
VSOS
VIOS
NOSI
HI02
HI06
KOIO/Oll
Gate rOXX to F; FL = M = m+Bb
End arithmetic at V 505 time.
Indexing is completed and the
selected sequence is continued.
VI02
Clear
KS36/S37
Clear
KIlO/Ill
VI06
H201, clear F, 1-10*
Clear F (lower
15 or 17 bits).
Word address-- Lower 15 bits of F are cleared.
Character] __ ~ .-- Lower 17 bits of F are cleared.
address
Clear FADR 2 FF
Set request bus
IOXX to F L
Initiate a storage reference.
Set main control
priority
Clear FADR I
Clear enable IO~F
While the arithmetic section was doing FADR, main
control was awaiting arithmetic time 3 (VS23) to input
HIIO. VIIO is required to setKOOO/OOI (request bus)
TllvlE
20 1XXXXX (FADR)
COMMAND
V080
N691
VSOO
Set start arith I
Start arithmetic pulse
Clear A2 and X (adder feeders)
VSOI
IS to A2 JE to IS static)
16 to X (J3b to 16 static)
whether FADR has or has not been completed.
Let's compare the major points of timing for the
20.IXXXXX and 20. OXXXXX instructions
0
20 OXXXXX (FADR)
n
0
TIM:E
COMMAND
V080
VI09
VIIO
-r--
Set Kl12/113
Input HllO
Set KOOO/OOI
~~
4 ~ times
difference
VS02
VS03
VS04/VIIO
VSOS
Clear FL and input HIIO
Set KOOO/OOI (request bus)
10 to FL (adder to 10 static)
Four phase times are added to the instruction execution time for each FADR. How many microseconds
isthis? _____________________________________
This process involves adding +1 to (FL) to form an
address M+ 1.
The second operation is the forming of the second
operand address for the 32 and 33 instructions (also
for double-precision and floating-point arithmetic if
the option is present).
OPERATIONS IN THE ARITHM:ETIC SECTION
Instructions for the 3300 may be divided into several
groups in which the instructions require similar arithmetic operations. These are, in order of complexity:
jumps and skips, copy, interregister transfer, storage
shift, enter, load, increase, logical, replace add,
store, masked search, compare, shift and scale, add,
* Logic Diagrams
261
subtract, multiply, and divide.
The arithmetic operations required by each of these
groups are discussed in this chapter. In most cases
the main control operations involved for each instruction are not detailed, as it is assumed that you
have read about main control.
The 3300 command timing charts provide a complete
phase -time by phase -time description of the execution
of each instruction.
The instructions in the optional DeD and floatingpoint/double -precision packages also require use of
the standard arithmetic section.
JUMP AND SKIP INSTRUCTIONS (02 -OS, 10.1-10.7)
During execution of jump and skip instructions the
arithmetic section is used to add two operands to form
a quantity which conditions certain operations. The
addition performed here is not for the purpose of forming a usable sum; rather, a comparison is made by
using the addition process. These instructions are
executed during RNI, so indexing and indirect addressing cannot be performed at that time.
A, Q, Bb Jumps and Skips (03-05)
The jump and skip instructions listed in table 17
require one pass through the adder during instruction
Table 17.
CODE
execution. The general steps for executing these instructions and the arithmetic operation for each is
shown in table 17.
1. Jump or skip instruction is obtained from storage
and decoded during RNI.
2. Start arithmetic.
3. Clear X and A2 (adder feeders).
4. Gate operands to be added to form control quantity
(listed for each instruction in table 17 into A2 and X.
5. Form sum in adder. (Sum is actually difference
because the complement of one operand is gated
into X.)
6. Test sum for required condition. Set jump FF or
skip FF if test is satisfied. Sum is not gated from
adder but is tested by jump or skip sensing network.
7. Perform a jump or skip exit to next RNI if condition
is satisfied. Normal exit is made to next RNI if
test condition is not satisfied.
Incremental/Decremental Index Jumps
and Skips (02.1-3, 02.5-7, 10.1-7)*
The index jump and index skip instructions are conditional on the contents of a selected index register.
*02.0 and 02.4 are no-ops.
A, Q, AND sb JUMP AND SKIP INSTRUCTIONS
INSTRUCTION
CONTROL QUANTITY
FORMED BY ADDER
TEST MADE
03 .. (0-3)
Compare A with
zero, jump
Test* for (AI)
equal, unequal,
greater, or less
than zero.
Arithmetic timing chain is started,
but adder is not used. (AI) is sensed
directly.
. (4 -7)
Compare A with
Q, jump
Test* for (AI)
equal, unequal,
greater, or less
than (Q1).
Sum = (AI) + (Ql)
(£) = equal
+ = greater than
- = less than
(Bb) - Y ::;: O?
(AI) -.y ::;: O?
(Q1) - Y ::;: O?
Sum
Sum
Sum
(Bh) - y ::;: O?
(AI) - y ::;: O?
(QI) - Y = ()?
Sum = (sb) + Y
Sum = (AI) + v**
Sum::;: (QI) + y**
04.
.(0-3)
.(4,6)
• (5, 7)
05.
.(0-3)
.(4-6)
.(5-7)
Skip next instruction if
(sb) = y
(A) = y
(Q) = y
Skip next
instruction if
(sb) = y
(A) = y
(Qf==y
*Test condition determined by designator j, bits 15-17.
**y is sign extended for XX. 4 and XX. 5.
262
= (sb) +y
= (AI) + y**
= (Q1) + r*
The state of this index register is sensed to determine
if a jump or skip is to be taken, and also if an increment/
decrement index operation should be performed.
Index Jump: (Bb) is sensed for equality with zero.
If (Bb) = 0, the test condition is not satisfied and a
normal RNI from P+1 is performed. If (sb) f 0, sb is
incremented (02 .1-02.3) or decremented (02.5 -02. 7),
and a jump to address m is performed.
The steps in execution of index jump are:
1. Instruction is obtained from storage and decoded
during RNI.
2. Set jump FF if Bb f O. (State sb is sensed by indexsensing networks.)
3. Start arithmetic timing (occurs regardless of state
of sb).
4. RNI from address m if (sb) f a and jump FF is set.
RNI from P+1 if (sb) = O. Arithmetic section now
completes execution of index jump while main control simultaneously performs RNI.
5. Clear X and A2.
6. Gate (Bb ) to X via 16 . Gate output of IS to A2 (+1 for
incrementalindex jump ~ -1 for decremental jump).
7. Form sum.
8. Clear Bb. (This command is blocked when jump FF
is not set.)
9. Gate sum through 10 into sb. (This command also
is blocked when jump is clear.)
Index Skip: (Bb) is compared with y for an index
skip. If (13b) = y, Bb is cleared and a skip to P+2 is
performed. If (Bb) :f y, Bb is incremented (10 .1-10.3)
or decremented (10.5-10.7) and an RNI is made from
P+1. (This instruction will skip only if y = 00000 or if
y = 77777 for 10.4.)
The steps in execution of index skip are:
1. Instruction is taken from storage and decoded during and RNI enable.
2. (F). IS and (Bb) "16 .
3. Start arithmetic timing.
4. Clear X and A2.
5. Gate F L into A2 via IS; gate (Bb) into X via 16 •
6. Add (Bb) andy. Yis FL. (Both F and Bb are sign
extended). This operation subtracts (y) from (Bb);
If sum = 0, they were equal.
7. Enable +1 (incremental skip) or -1 (decremental
skip) from IS •
8. Set skip FF if sum = a(Bb = y). Output of adder is
sensed by skip-sensing network.
9. Set skip 2 FF is skip FF is set.
10. Start arithmetic.
11. RNI from P+1 if skip condition is not met «Bb ) f
y), from P+2 if skip condition is met
= y).
Arithmetic simultaneously completes execution of
index skip.
12. Clear X and A2.
13. Gate (Bb) into X via 16 . Gate +1 (incremental skip)
or -1 (decremental skip) into A2 via IS.
14. Form the sum of (Bb) + 1.
15. Clear Bb.
(sO
16. Gate the sum from adder to Bb via 10 . (This command is blocked when skip 2 is set.)
COPY INSTRUCTIONS (77.2 ch 0000, 77.3 ch 0000)
The copy instructions load the contents of interrupt
mask register into the upper 12 bits of Al and the
external status code for 77.2 (ch) 0000 instruction or
internal status code for a 77.3 (ch) 0000 instruction
into the lower 12 bits of AI.
The steps in executing copy instructions are:
1. Obtain instruction from storage.
2. Set status~A FF.
3. Clear AI.
4. Gate contents of interrupt mask register and status
to AI. (External status code from I/O channel ch
for 77 .2 (ch) 0000, internal status code for 77.3
(0000).
5. Clear status ~ A FF 0
6. RNI from P + 1.
SINGLE-PRECISION INTERREGISTER TRANSFER(53)
The interregister transfer instruction is used to
move data between Al and Ql registers, index registers, and register file.
The single -precision interregister transfer instruction is composed of eleven subinstructions, each of
which performs a separate transfer.
These instructions and the steps in their execution
are:
1. Transfer (sb) to Al (53.0 (1-3) 0).
2. Obtain instruction from storage (RNI).
3. Start arithmetic, then RNI from P+1 while arithme tic completes execution of instruction.
4. Clear X and A2.
5. Gate (Bb) to X via 16 . A2 remains clear.
6. Form sum, (Bb) + 0 = (sb)o
70 Clear AI.
80 Gate sum, (Bb), into Al via 10 •
9. Transfer (AI) to )3b (53.1 (1-30) 0).
10. Obtain instruction from storage.
11. Start arithmetic, then RNI from P+l while arithmetic completes execution of instruction.
12. Clear X and A2.
13. Gate (AI) into X via 12. A2 remains cleared.
14. Form sum.
15. Clear Bb.
16. Gate sum, (AI), into Bb via 10 •
17. Transfer (register m) to Q (53. 01).
18. Obtain instruction from storage.
19. Start arithmetic, then RNI from P+1 while arithmetic completes execution of instruction.
20. Register file reads (register m) into ZO.
21. Clear DB register.
22. Gate (ZO) through 17 and EXX2 into DB register.
23. Clear X and A2.
24. Gate (DBR) and (register m) into X via 14.
25. Clear Ql.
263
26. Gate (X) into Ql via II. Ql now contains (register m).
27. Transfer (Q) to register m (53.41).
28. Obtain instruction from 1:)torage.
29. Start arithmetic.
30. Clear X and A2.
31. Gate (Ql) into X via 13 . Meanwhile, block control
prepares register file to receive word by loading
address into S, issuing a register file write, and
starting delay line timing.
32. RN1 from P+1 while block control simultaneously
completes execution of instruction.
33. Clear DB register.
34. Gate (X) into DB register via 17 and EXX20 «Ql)
now in DB register.)
35. Clear Zl (block control register).
36. Gate (DBR) into Z1.
37. Write word, (Ql), from ZI into register m.
38. Transfer (register m) to Al (53.02).
39. Obtain instruction from storage.
40. Start arithmetic, then RNI from P+ 1 while arithmetic completes execution of instruction.
41. Register file reads (register m) into ZOo
42. Clear DB register.
43. Gate (ZO) into DB register via 17 and EXX2.
44. Clear X and A2.
45. Gate (DBR) into X via 14.
46. Clear AI.
47. Gate (X) through the adder to 1° and AI. Al now
contains (register m).
48. Transfer (A) to register m (53.42).
49. Obtain instruction from storage.
50. Start arithmetic.
51. Clear X and A2.
52. Gate (AI) into X via 12. Meanwhile, block control
prepares register file to receive word by loading
address into S, issuing a register file write, and
starting delay line timing.
53. RNI from P+1 while block control simultaneously
completes execution of instruction.
54. Clear DB register.
55. Gate (X) into DB register via 17 and EXX2. (AI)
now in DB register.)
56. Clear Z 1 (block control register).
57. Gate (DBR) into Zl.
58. Write word, (AI), from Z1 into register m.
59. Transfer (register m) to sb (53. (1-3) 3).
60. Obtain the instruction from storage.
61. Start arithmetic, then RNI from P+l while arithmetic and block control complete execution of instruction.
62. The register file reads (register m) into ZO.
O~. Gate (ZO) into DB register via 17 and EXX2.
64. Clear X and A2.
65. Gate (DBR) into X via 14 0 A2 remains cleared.
66. (X) propagates through ackler and is statically enabled to 10.
67. Clear Bb.
264
Gate s urn into Bb via 10 0 sb now contains (register m).
69. Transfer (sb) to register m (53. (5-7) 3).
70. Obtain instruction from storage.
71. (Bb) to 16 , 16 to 17 , 17 to EXX2 are statically enabled.
720 Start arithmetic (arithmetic timing not used for
this instruction), then RNI from P+l while block
control completes execution of instruction.
73. Clear DB register.
74. Gate (sb) from EXX2 into DB register.
75. Clear Zl.
76. Gate (DBR) into Z1.
77. Write word, (sb), from Zl into register m.
78. Transfer (A) plus (Q) to A (53.04).
79. Obtain instruction from storage.
80. Start arithmetic, then RNI from P+1 while arithmetic completes execution of instruction.
81. Clear X and A2.
82. Gate (Ql) to X via 13 Gate (AI) to A2 via 12
83. Form sum.
84. Clear AI.
85. Gate sum into Al via 10 • Al now contains (AI)
+ (Ql).
86. Transfer (A) plus (Bh) to A (53. (1-3) 4).
87. Obtain instruction from storage.
88. Start arithmetic, then RNI from P+1 while arithmetic completes execution of instruction.
89. Clear X and A2.
90. Gate (sb, -sign extended) into X via 16 . Gate (AI)
into A2 via 12.
91. Form sum.
92. Clear AI.
93. Gate sum into Al via 10 . Al now contains (sb)
+ (AI).
94. Transfer (A) plus (sb) to sb (53. (5-7) 4).
95. Obtain instruction from storage.
96. Start arithmetic, then RNI from P+l while arithmetic completes execution of instruction.
97 . Clear X and A2.
98. Gate (sb, -sign extended) into X via 16 . Gate (AI)
into A2 via 12
99. Form sum.
100. Clear Bb
101. Gate sum into sb via 10 . Bb now contains (AI)
+ (Bb).
68.
0
0
0
STORAGE SHIFT (10.0)
The storage shift instruction reads a word (m) from
storage, senses the sign bit and sets skip if the sign
is negative, shifts the word one place left (end -around),
then replaces it in storage.
The next instruction is read· fr()m P+ 1 if the sign is
positive. If the sign is negative and skip is set, a skip
to P+2 is performed.
The steps in the execution of the storage shift are:
1. Instruction is obtained during RNI. ROP is then
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
performed to read word at location m. This word
is placed in DB register.
Begin STO.
Start arithmetic. While arithmetic completes shift
of (m), main control prepares for return of word
to storage by obtaining bus priority and transmitting a write and the storage address to memory .
Clear X and A2.
Gate (DBR) to X via 14.
Set skip if the sign of (m) is negative. (Sign was
checked in DBR).
Gate (X) into Q2left. This transfer always places
(X) shifted one place end -around into Q2.
Clear X and A2.
Gate (Q2) into X via 14. This places (m - left 1)
back in X ready for return to storage.
Enable (DBR) to data bus transmitters.
Clear DB register.
Gate (X) into DB register via 17 and EXX2. Because
(DBR) has already been enabled to transmitters,
(m - left 1) is immediately transmitted to storage.
Main control then waits until reply from storage
starts storage time -out chain.
Drop bus priority and storage request.
RNI from P + 1 if skip is clear (original sign of (m)
positive), or RNI from P+2 if skip is set (sign of
(m) negative).
ENTER INSTRUCTIONS (11, 14)
The 14 instructions place a quantity y (lower bits of
the instruction word) into AI, Ql, or:sb. The 11 instruction places a quantity r (lower 17 bits of the instruction word) into Al .
The steps in execution of enter character address
into A (11) are:
1. Instruction is obtained and decoded during RNI.
2. Start arithmetic, then RNI from P+l while arithmetic completes execution of instruction.
3. Clear X and A2.
4. Gate lower 17 bits of F (sign extended for bit 17 = 1)
into A2 via IS. X remains cleared.
5. Form sum (FLI7).
6. Gate sum, (F L), into Al via 10 •
The steps in execution of enter A, Q, or sb with y
(14) are:
1. Instruction is obtained and decoded during RNI.
2. Start arithmetic, then RNI from P+l while arithmetic completes execution of instruction. (Arithmetic timing occurs but is not used for enter Bb
with y.)
3. Clear X and A2.
To execute enter A with y (14.4 or 14.6), gate y,
lower 15 bits of F (sign extended for 14.4), intoA2 via
IS. X remains clear. Form sum. (This is done in all
cases, but output of adder is used only for enter A.)
To execute enter Q with y (14.5 or 14.7), gate y,
lower 15 bits of F (sign extended for 14.5), into lower
X v;ia 16 • A2 remains clear.
Enter sb with y (14.0-14.3). Clear she
Enter
Enter
Enter
Enter
Enter
Al with y (14.4 or 14.6). Clear AI.
QI with y (14. 5 or 14.7). Clear QI.
Bb with y. Gate lower 15 bits of F into Bb.
Al with y. Gate sum, (F L)' into Al via 10 .
QI with y. Gate (X) and (F L) into Ql via II.
LDA (20) Instruction
Setting of KI04/I05 (start arith 2 FF) at V008 time
will cause N691 to start the arithmetic timing chain,.
The arithmetic timing chain will enable:
Clear to A 2 - - - - -......
}
DBR to 14 to XI
Sum to 10 to Al
_ _- J
LACH (22) Instruction
Identical to LDA (20) instruction with one exception:
I4 L6 to X instead of I4 to X. (Referto Logic Diagrams,
page 2-93). F967 will knock down N643, N645, and
N647.
LCA (24) Instruction
Identical to LDA (20) instruction with one exception:
DBR~ 14 instead of DBR to 14
(Refer to Logic Diagrams, page 2-151). F802, F823,
and F882 input a 1 to 1904, knocking it down and causing an output from 1905 to 1908.
0
LDAQ (25) Instruction
In this instruction we are concerned with an ROP to
ROP. In the first ROP two things occur:
1. ClearA2~
DBR to 14 to
X~
Sum to 10 to A
2. An FADR operation is started by setting KIOO/IOI
(start arith 1 FF) at V002 time. K060/061 enabled
setting of KIOO/IOI and also forced 16 to output
a +1. FADR consists of adding +1 to M to form
the address for loading (QI).
In the second ROP, DBR to 14 to Xl to II to QI is
caused by setting of KI04/I05 at V008 time. NOTE:
K502/503 (originally called loadop, now LDAC + LDAQ)
helps to enable data paths on the second ROP.
LCAQ (26) Instruction
Identical to LDAQ (25) instruction with one exception:
DBR to 14 instead of DBR to 14. (Refer to Loglc Diagrams, page 2-151.) F802, F823, and F882 input a 1
to 1904, knocking it down and causing an output from
1905 to 1908.
LD L (27) Instruction
Identical to the LDA (20) instruction with two exceptions:
1. QI to 12 to A2 instead of O' s to A2. (Refer to Logic
Diagrams, page 2-139.) K5II, F940, F915, and
265
RADR
RNI and decode
F ;;: 20, 21, 24, 25, 26, 27
,.
....
~
No
.....
Yes
b = 07
....
~~
a = 07
No
.....
RNI and decode
F = 22, 23
..
Yes
FL15 + sb to FL15
~
m+sb=M
....
..
.
F L15 + Bl to FLI5
m+sb=M
RNI and decode
F = 54
54****
20
22*
24**
25
26**
27***
LDQ
LQCH 21
23* }
LDAQ 25
LCAQ 26**
ROP
Clear A2 _ _ __
~-
DBR to 14 to
Xl~
Sum to 10 to Al
DBR to 14 to Xl to II to Ql
Substitute:
*14 L6 to X4
**DBR to 14
***~I to ~2 to A2
lI'>i (A), RNI from addreSR P + 1; if not,
2. Subtract (Q) from (1\:1). If (Q) > (1\:1), RNI from
P + 2; if not,
3. RNI from address P + 3.
Comments: The final state of the (A) and (Q) registers remains unchanged. (A) must be > (Q) initially
or the test cannot be satisfied. 77777777 is not sensed
as negative zero.
means more
It should be noted that the symbol
90sitive than for this instruction.
This Advance P is a Special
Case for This Instruction.
Advance P Occurs Normally
in RNI not ROP.
ROP
Advance P
(A) - (M)
no
If Sum Positive
(A)
> (lVI)
yes
Is Sum
Negative?
If Sum Negative
(1\1) was> (A)
(M) - (Q)
no
Is Sum
Negative?
p
yes
Set
Skip
RNI
at p-r- 1
RNI
at P+2
If Sum was Negative
(Q)
> (M)
RNI
at P";"3
'---___ J
(A»
(M»
(Q)
The following items are of note for a 52 instruction:
1. At V004 time of ROP, H231 is pulsed to advance P.
<,
started to perform (A) - (1\1). If the sum is negative but! not -0, (IVl) is greater than (A). This is
sensed by the hard\vare by K584/585 (CPR Out of
Limits) remaining set at Arithmetic time 5. III
this case the Block P FF will be set and an RNI
278
Figure 281.
Flow Chart for CPR Compare
will be initiated at P + 1.
3. If (1\:1) ~ (A) a second Arithmetic pass, which is
the sum is negative but not -0, (1\1) is less than (Q).
This is sensed by the hardware by K584/585 (C PR
Out of Limits) remaining set at Arithmetic time 5.
In this case a normal exit to RKI is performed and
RNI will occur at P + 20
Instruction Description: (A) is compared with the
logical product of (Q) and (M). This instruction uses
index register B2 exclusively. m is modified just
prior to step 3 in the test below.
4. If the sum is positive or -0 at time 5 of the second
Arithmetic pass (M) is within limits. In this case
the Skip FF is set and an RNI is performed at P + 3.
5. If (1\1)
(A) the second Arithmetic pass is blocked
at the input to H501 byK584/585 (CPR Out of Limits) being set.
6. The CPR Out of Limits FF is set at time 4 of each
Arithmetic pass. It is cleared at time 5 if a within limits condition exists by J564 and V585.
Instruction Sequence:
1. Decrement (B2) by 1. (Refer to table belmv. )
2. If (B2) changed sign from positive to negative, RNI
from P + 1; if not,
3. Test to see if (A) >- (Q) ,. (lVI). 1\1 = m + (B2). If
(A)'::: (Q) • (M)~ RNI from P + 2; if not,
4. Repeat the sequence.
MEQ MASKED EQUALITY SEARCH
23
18 17
15 14
00
m
06
i = interval designator, 0 to 7
m = storage address
Figure 282.
Comments: i is represented by 3 bits permitting a
decrement interval selection from 1 to 8. Address
modification may not be used.
MEQ
Instruction Description: (A) is compared with thE'
logical product of (Q) and (M). This instruction uses
index register Bl exclusively 0 M is modified just
prior to step 3 in the te st below.
Table 18.
Instruction Sequence:
MTH COUNT EXAMPLE
Designator
i
Decrement
interval
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
10 Decrement (Bl) by L
(Refer to table below. )
20 If (Bl) changed sign from positive to negative, RNI
from P + 1; if not,
3. Test to see if (A) = (Q)
(M). M = m + (Bl). If
(A) = (Q)
(M), RNI from P + 2; if not,
4. Repeat the sequence.
Comments: i is represented by 3 bits, permitting
a decrement interval selection from 1 to 8. Address
modification may not be used.
MTH MASKED THRESHOLD SEARCH
23
18 17
15 14
07
i
m
The following is a brief summary of the first five
arithmetic passes for an 06 or 07 instruction. They
do not include a pass for indexing which could be
specified by the instruction. The data flow and set
times of important FFs are noted.
00
m
= interval designator, 0 to 7
= storage address
Figure 283.
MTH
VIII
V080 End RNI
V500
First pass
V501
V502
(B ) + F L 15 to F L 15
>
ign Ext
C
FLI5~I5 A2
I
K006/K007 Disable Storage Request
Adder~IO
V503 Bb~J6Cxl
Sign Ext
V504
279
Start
RNI
at
P+l
RNI
and
Decode
FL ~ Bl-----.
FL (06)
FL-'-B2~
IF
Once ROP started
decrement Bb
occurs
simultaneousl
Decrement
FL
Start ROP
07
yes
06 = Decrement Bl
07 = Decrement B2
( 1
no
Logical
Product of
(Q) and (M)
RNI
at
PT2
Figure 284.
Second pass
V500
V501
V502
Flow Charts for 06 and 07 Instructions
(the 06 uses Bl and the 07 uses B2)
>
Sig.ll Ext
r
2
FLI5~I ~A
-
5
i~J6l-X
Adder- 10
Is Ext
K576/K577 Arithmetic Search 1
V503
V505
Third pass
V500
r
Is Ext
V501 1_I5~A2
V502
Bh- 16~X
Adder~IO
V503
V504 IO~ Bb
V505
2RO
J
V505
l
The next two pas se s
are made only if
(Bb - i = pos or ~O)
KD16/0l7 Search Decrement Index
V500
Fourth pass
V50l DBR ....... I4~ Xl
Logical product
V502 QL_~I2 .... A2
of (Ql) & (M)
V503
KDlS/K019 Wait Compare if B - i = pos or:::-O
I
~
I
V504 Adder (logical product)
V5D5 f3_Q2
Fifth pass
K500/K50l
V5DO
V5Dl Al .......
V5D2 Q2~
I2~A2
>
I~
K5DD/K50l
I
K562/K563 Diable Logical Product
Adder
ti- Xl
I
I
K574/K575 Arithmetic Search 2
V503
V5D4
[ Sense re suIt for
se arch met note
+0 = -0.
.J
V5D5
These clear on the next Bb + FL15 of the
0.6 or 07 or on the next F 1 - . F 2 transfer.
Timing for Search instructions, 06 and 0.7, beginning with VOOS of RNI. These instructions provide
a static indexing translation, (F604 = 1) and F424 = 1).
VD97.:
Set K5727573
VODS: EXX2 ..... Fl
Set K570/571
V009 : If Arith Busy, set KDDS/OD9
Vl09: If Arith Busy, input to H518
Vo. 10.: Test interrupts, clear Ko.02/ 0.0.3
V5lS: Fl ~ F 2 , clear K57D/571
VDil: InputHDSO, set KOD6/0D7
V5l9:
Vo.SD:. Clear KDSo./DSl, set Ko.S4/o.S5,
set Klo.o./IDl
V52D: Clear K572/573
Vl09: Input HlOO if Arith
1st Arith pass
13iiSY
VlOO: Clear KlDD/lDl, set KllD/lll
N659: Start Arith, input H5DD and H5ID,
set K536/537 FADR 1, set K596/
597 FADR 2
V5DD: Clear Xl and A2' input H541, H57l
2Sl
V50l:
:r5 ..... A2
r6
(Bb )+F L15
to F L15
(F .... 15 )
~Xl (B l ~r6 if 06)
(B-2 .... 16 if 07)
Clear K574/575, set K576/577 Arithmetic
Search 1
2nd Arith pass
(F L 15) - i
to FL15
Input H20l if Breakpoint stop
V502:
N20l: Clear F L15 , input HllO
V503:
VllO-V2l0: Input H449, Hl05, Block
setting of KOOO/OOI Request Bus
FF
V504: Clear K596/597 FADR 2
Vl05: IO~ F L15 if sum =
Hl02, input Hl14
V505-V585:
:to,
input
Vl06-Vl02-V202-Vl14: Clear KllO/
111, clear K006/007, set KIOO/
101, input Hl03
Clear K536/537 FADR 1
Vl03-Vl09: Input HIOO
N659: Start Arith, input H500 and H5l0,
set K536/537 FADR 1, set K596/
597 FADR 2
VlOO: Clear KlOO/lOl, set KIlO/Ill
V500: Clear Xl and A2 , input H54l, H57l
i
Is ext
+ F L15 sign ext
Input H20l
V502:
N20l: Clear F L 15 ' input HllO, input
H018 as K006/007 is clear
V503-V523:
VllO - V2l0 - V018: Input H019, set
KOOO/OOI Request Bus (to start
the ROP), input H449
V504: Clear K596/597 F ADR 2
V019-Vl05: IO~ F 15 if sum -:} :to,
input H126 ank Hl02, set KOIO/
011, transmit F L15 on S bus
V505-V585:
Vl02-V202-V126: Clear KIlO/Ill, set
K 1 04/105 Start Arith 2, set
K016/0l7, input Hl17 and Kl03
Clear K536/537 FADR 1
( Vl09 - Vl03 - Vl17:
!
(FL15 ~I5)
V50l: :r5~A2 si~
eXt
r6~ Xl (Is ext (i ..... r6) as J018 = 0,
this forces F52l and F522 to output
Is which in turn forces J28l and
J282 to output Os blocking a Bb --:r6
Input Hl04,
set
N659: Start Arith, input H500 and H5l0
Kll fl/117 ~pnrl Rtnr~?:p RPflllPRt
T650 = 1
Vl04-N050: Input Hl15, Clear Kl04/
105
282
V500: Clear Xl and A2 , input H54l and
H57l
j
3 rd Arith pas
(Bb ) - i to Bb
Vl15: Set K012/013
i
1s ext
+ Bb Os ext
V501: 15 ~ A2 Is ext (i
r6 ..... Xl Os ext ]31
rS)
B2
r6
16 if 06
if 07
Vl16: Test Breakpoint Stop if BPO selected K134/135
V502:
V061: Resynced storage Reply, input
H018, input HOOO
V503-V523:
VOOO-V018: Clear KOOO/OOI Request
Bus, input H241, input H019
V504:
V001-V019: Clear Bb , input H244, input H102
V505-V585: Clear K576/577 Arithmetic
Search 1
V002 - V102 - V202: rO~ Bb if sum
±O, input H103
I
V003-V103: If (Bb) -i = positive result
(+0 = -0), set K018/019 Wait
Compare
ROP
V004:
V005:
V006: Input H401
V007-N005-N401: Clear KO 10/011,
Kl16/117, K012/013, clear DBR,
input H410
V008-N410: Set K104/105 if (B b ) - i,
Result was positive (K018/019
set) EXX2 DBR
l
4th Arith pass
V009: Input H084 End ROP
V109: Input H104
N659: Start Arith, input H500
and H510
V084: Occurs only if K018/
019 was clear, clear
K084/085 and K01B/
017, set K080/081,
input H087
V104: Clear K104/105, J063
blocks V084
V500: Clear Xl and A2 , input
H531 and H551
V087: Input H014
V014: RNI @ P + 1 if field
exhausted
V502: Set K500/5011ogical product M . Q1
V503: Input H512
V504: Clear Q2, input H513 if
result 1-0
283
l
V5l3-V505-V585: r3 ~ Q2(Adder ~ 13 ), set K574/575
Arith Search 2, input
H5l0
Input H102
5th Arith pass
Vl02: Clear K016/0l7, input Hl03
V5l0-V530: Clear Xl and A2 ,
input H50l, H55l and
H53l, set K562/563,
Disable Logical Product
Vl09: Clear K018/0l9
V50l: 12 ~ A2 (AI ~ I2)
t1 ~Xl (Q2~ ti)
V502:
Compare Al
to Ql . M
V503: Clear K500/50l
Al
(Ql • M)
Sum
V504:
V505-V585:
fuput Hl02
(Search met) (No interrupt)
(Search met) (futerrupt)
Search met
(NOTE: +0 = -0)
Vl02: Input Hl03
Set K088/089
Vl03:
fuput Hl14 (Short cycle ROP ROP) Block
input H084
fuput H084
fuput H084
Vl14: Set KlOO/lOl
V084: Set K080/08l,
Clear K084/085, set
K200/20l Block P
V084: Set K 0 8 0/081,
Clear K 084/085, set
Kl08/l09 Skip
RNI@ P
RNI @ P + 2
Return to Decrement FL Sequence
SHIFT INSTRUCTION
There are a number of instructions which require
shifting such as shift, scale, multiply: and divide. The
instructions to be discussed here will be the 12.0 to
13.3 series. This includes shift A, shift Q, and shift
AQ. The shift instructions are described in the refere nee manual.
Execution of a shift instruction can be divided into
1. Forming the shift count.
a. Number of places to shift a register.
b. Direction of shift, left or right.
2. The shift cycle.
284:
Forming shift count is similar to F ADR .
Form shift count: K = k + :sb
FADR: M = m + Bb
The lower 15 bits of the instruction are k. Bb and
k will be totaled in the adder and both k and Bb will be
sign extended.
The shift count may come from 10 to SC register or
from thp 8rlrlpr to SC rpp-iRtpr. Whirh m'lth iR t::1kpn
depenci~ on th~ sum~f 1<: :nd
Bb.
. -- ". .. -
--
Referring to figure 241, you will note that the SC
register will hold the complement of the shift count.
This is true for shift instructions 12.0 to 13.3.
F L15 toI5toA2~
Bf5 to 16 to X~
Adder to IO------~
)e---
Sum pos
Figure 2S5. Data Path for
Forming Shitt Count
Translations are made from SC register to determine when the shift is complete.
As an example: Instruction 12.000001 is executed,
a shift of one place. The value that would go to SC
register would be 76 which is the 6-bit complement of
the shift count. When the shift 1 takes place, SC register is advanced by 1 and then holds a 77 which indicates
shift complete. Shift count register is a 6 -bit counter,
but for the shift instructions is considered as two 3 -bit
counters.
In Logic Diagrams, page 2-115, the left -hand group
of flip-flops (B700/701 to B722/723) is the 1 's counter.
When the contents of a register is shifted 1 place left
or right, this counter will be advanced by 1. When the
1 's counter holds 7 it indicates that the 1 's shifts are
complete.
The right-hand flip-flops (same page) are the lOs
counter (B730/731 to B752/753). When the contents of
a register is shifted lOS octal places, this counter will
be advanced by 1.
Using the shift cycle timing chain, shifting will be
accomplished by a numb2r of passes through the shift
cycle.
One pass can shift a quantity 1 place, 109 places or
lIS places. There is no other combination possible.
As you go through the timing which follows, refer
to figures 242 and 243 and Logic Diagrams. Verify
the paths. Look for the end -around path for left shift
A and Q and AQ. Also trace the path for drawing sign
on the right shift.
An example of how SCR counts is significant. For
the example assume a desired shift of 13 s o The count
shown for SCR is the count that would exist at the end
of that pass.
Table 19. SCR COUNT EXA-MPLE
SCR
64
75
76
77
77
Comments
Initial
1st pass--Shift lIS
2nd pass--Shift 1
3rd pass--Shift 1
4th pass--used to clear Arith Busy FF
Note that only three passes were needed to complete the shifting. The additional pass is a "housekeeping" pass and would occur any time a Is shift
occurs as the last shift.
Shift Count
Register
Sum neg
(SCR is on p .2-115in Logic Diagrams. )
Timing for Shift Instructions
The RNI sequence for a shift instruction has taken
place.
V3S0 (End RNI): Set KIOO/lOl (start arith 1).
N6S7, N691, N693: Start arithmetic, input H500 (start
arithmetic timing chainL Input H510 (clear A2
and X).
V500: Clear adder feeders A2 and X. Input H541
(1 6 to X) and H571 (IS to A2).
V501: Gate IS to A2 (static enable F to IS). Gate 16
to X (static enable Bb to 16).
If the instruction is 12.0 or 13.0 (no index) the output of 16 will be D's.
VS02
V503: Set K546/547 (transfer lOs enable).
Shift count is gated to rank: 10f SC register and then
must be transferred to rank: 2 so that advance SC register will take place properly. Transfer of 1 's always
happens at the first time of shift cycle, and on the
first pass transfer of lOs must also take place to initialize the lOs counter.
VS04
V50S:
If K is positive, gate adder to SC register (p.
1-3 ). SetK512/513 (shift left) or, if K is negative, gate 10 to SC register. Set K510/511
(shift right). Input H600 and H610 (start shift
cycle). Bit 23 of the sum is sensed to determine left or right shift.
Shift Cycle
V600: Clear A2 and Q2. Transfer l's count, transfer lOs count first pass only. Set K560/561
(busy), set K57S/579 shift cycle. If SCR f. 7X,
lOs complete. Input to H561 OR H523. If SCR
= 7X, lOs complete. Input to H551 OR H513.
In Logic Diagrams, page 2-99, note the inputto H561
(12 to A2 shifted). This input will be made if lOs is
not complete and the instruction is shift A or shift AQ
The input to H523 (1 3 to Q2 shifted) will be made if
lOs is not complete and the instruction is shift Q or
shift AQ.
The lOs shift takes place between 12 , A2 and/or 13 ,
Q2. If lOs is complete the transfer from 12 13 to A2Q2
0
2S5
10 to Al RS1 ----___
_+_'
l' s complete
1(2) Al direct
transfer
.........--'--. no shift
&~""""I---4---- II to Q1 RS1
1 's complete
II Ql direct
transfer-no
shift
Sign of A2 - - - - - - -.. . .
A2
Q2
12 to A2 RS10S-----.........1-"
lOs complete
direct transfer
Sign of A1------J
Figure 286. Shifting Paths for A
Al
r-'--"'-1
Ql
10 to Al-----4f--+---H.
' - t - - - - t - - - - I 1 to Q 1
LS 1
~~--l's complete ------I~-(
LS 1
..-L-~.....,
direct transfer
'--------1023
no shift
A2
Q2
12 to A2
LS lOS
'---+------
13 to Q2
LS lOS
~----I215-1223
Al
Q1
Fig-ure 2R7,
Rhifting Paths for Q
will be direct. See page 2-95 for inputs to H551 and
H513.
V601: If lOs complete, advance lOs counter and gate
12 to A2 (enable Al to 12) and 13 to Q2 (enable
Ql to 13 ). The transfers will be right or left
lOS enabled by shift left FF or shift right FF
being set (p. 2-99). If lOs complete, gate 12
to A2 (AI to 12) and 13 to Q2 (Ql to 13). Clear
K546/547 (transfer lOs enable).
V602: Clear .l1... 1 and Ql. Transfer lOs count. If
SCR "f X7 (l's comRlete), input H525 (IO toAI
shifted 1) and H565 (I I to Ql shifted 1), p. 1-31.
If SCR = X7 (l's complete), input H515 (IO to
AI) and H555 (II to Ql). If SCR = 77 (shift
complete), clear K560/561 (busy).
V603: If 1 's complete, gate 10 to Al (enable A2 to 10 )
and II to Ql (enable Q2 to II) shifted 1. Advance l's counter. If l's complete, gate 10 to
Al and II to Ql straight. The enables to 10
and I I are the same whether shifted or not
shifted. If SCR "f 77 (shift complete), input
H600 to repeat shift cycle.
Single -Precision Multiply
The multiply A instruction, function code 50, win
multiply the contents of A register and the contents of
a 24-bit memory location, leaving a 4S-bit product in
AQ registers. (Chapter 3 describes this instruction.)
The multiply operation can be subdivided into three
parts. Refer to figure 244.
1. Initialization.
a. Makes (A) positive if negative and places it in
Q register. This is the multiplier.
b. Makes multiplicand from memory positive if
negative and places it in X register.
c. Records if original signs of multiplicand and
multiplier were unlike.
d. Checks first multiplier bit (MB); the multiplier
bit is the least significant bit of the multiplier.
2. Multiply step.
__
a. If MB = 1, add X and A2. Enable sum to 10 .
b. If MB = 0, enable A2 to 10.
c. Shift 1011 right 1 to AIQl.
d. Check next MB
e. Return to step 2a 2310 times for the 2410 multiply
steps.
The multiply step will form the 4S-bit product in
AQ registers. After the mUltiply step, A and Q registers will be swapped for programing convenience.
The product is formed through a series of additions
and shifts.
3. Complement and/or swap
a. Complement AQ, the product if unlike signed
operands were multiplied. Note: Since the
arithmetic section can mUltiply only positive
numbers,. the product must be positive at this
time. If either or both the multiplier and multiplicand were negative before the multiply step,
the numbers were complemented during ini tialization.
b. Swap A and Q so that the most significant bits
of the product are in Q. This will always take
place.
In the following example of the multiply step 6-bit
registers will simply be used. Finding the product
v·lill require sLx multiply steps.
Example 1
12S x 30S = ?
(A) = 30 = multiplier (M) = 12 = multiplicand
Initialization is complete: A = 00, Q = 30, X = 12
A
1st Step
o0
000 0
Q
0 1 1 0 O[Q] MB = 0
\\\\\
\ \\\\'\
0 000 00 1 10 0
o0
shift AQ right 1
\\\\\\\\\\0{illMB = 0
3rd Step \0 \\\0\\\\\l{ill MB 0
o O~ 000 0000 11shift AQ right 1
2nd Step
o0
0 000
0 0 0 1 1 0 shift AQ right 1
=
4th Step 0 0 0 0 0 0
X= 001010
o0 1 0 1 0
0 0 0 0 1m MB = 1
t
0 0 0 0 1 1 Add A and X
0\\\\\\\\\\\ shift 1right
5th Step 000 1 0 1
X= 001010
o0 1 1 1 1
';\\\\ \
o0 0 1 1 1
6th Step 0 0 0 1 1 1
00 0 0
t1
o[] MB
=
1
0 0 0 0 0 1 Add A and X
\\~~~
1 0 0 0 0 0 shift 1 right
1 0 0 0 0[QJ MB = 0
\\\\~ \ \~~\~
o0
0 0 11
1 1 0 0 0 0 Shift AQ right 1
AQ ;:; 0360 before swap.
The pencil and paper method:
12
x30
00
36
360 The answers match.
Example 2 (Negative times positive)
(M) = 35
A = 60
Initialization is complete: A = 00, Q = 17, X = 35
287
RNI and decode
RNI at P+l
GENERAL FLOW
Initialize
__---I~
Clear A2 and Xl
t------4~
Complement and/or swap
14 to Xl
A. INITIALIZE
12 to A2
DBR to 14
Clear AIQl
Record unlike if
A sign :f M sign.
B. MULTIPLY STEP
Transfer SCR
Record next MB
~------,
Clear A2Q2
Clear AIQl
C. COMPLEMENT AND/OR SWAP
AIQl to A2Q2 I--..,..-I~
Clear AIQl
via 12 and 13
Yes
Clear busy
Complement
Clear A2Q2
Figure288.
AIQl to A2Q2
via 12 and 13 t----I~
A2Q2 to AIQl
Clear AIQl t----I~ via 10 and II
Flow Charts for Multiply A
Note: Using 6 bit registers, bit 05 is the sign bit. Thus
60= - 17. Initialize cycle makes all numbers
positive.
A
Q
1st Step 0 0 0 0 0 0 0 0 1 1 llIJ MB = 1
X= 011101
o 1 1 1 0 1\0 0 1 1 1 1 Add A and X
+
0\ 1 1 1 0
2nd Step 0 0 1 1 1 0
0 0 1 1 1 1\hift 1 right
*
1 0 0 1 llIJ MB = 1
X= 011101
1 0 1 0 1 \ 1 0 0 1 1 1 Add A and X
d\
0 101
1 1 0 0 1 l\Shift 1 right
3rd Step 0 1 0 1 0 1
X= 011101
1 10 0 10
1 1 0 0 1 [] MB = 1
•
1 1 0 0 1 1 Add A and X
0\ 1 0 0 1 \ 1 1 0 0 1\hift 1 right
4th Step 0 1 1 0 0 1
X= 011101
1 10 1 10
\
o1
\
10 1 1
0 1 1 0 0[1 MB = 1
0 1 1 0 0 1 Add A and X
\..
0 0 1 1 0 0 ShIft 1 rIght
5th Step 0 1 1 0 1 1, 0 0 1 1 0 ~MB = 0
o 0 1 1 0 1 ~ 1 0 0 1 1 0 shift 1 right
6th Step 0 0 1 1 0 1,_ 1 0 0 1 l~MB = 0
o 0 0 1 1 0 "1 1 0 0 1 1 shift 1 right
AQ = product = 0663
AQ holds a positive product which must be complemented to equal -0663.
The pencil and paper method:
+35
x -17
313
35
-663
After the complement and swap cycle AQ would hold
7114 with the most significant bits in Q and least significant bits in A ):,egister.
Swapping AQ to leave the least significant bits in A
is justified in that, in most case, the product with sign
can be contained in A register. Thus, in most cases,
the programmer can follow a multiply instruction with
an add or subtract A instruction.
What is the decimal equivalent of the largest signed
number that can be displayed in a 24 -bit register?_
'--_--JT
Figure 289.
X
Data Flow for Multiply Step
The multiplier bit sampled to determine the input to
10 inverter rank is effectively the least significant bit
of Ql, which holds the multiplier.
The first MB is sampled during initialization (bit 0
of II). The remaining MB, bit 1 of Q2 register, will
be sampled at Q510 and Q511. This is necessary because the sampling occurs prior to the shift. Bit 01
will be shifted into bit 00 position after the sample but
before the next addition.
The multiply will be perfo.lJlle_d~--.2A-±9- multiply
steps. Shift count register will count the steps and
will terminate multiply step when SCR = 308 .
Timing for Multiply A Instruction
Refer to figure 244.
Main control's responsibility for single -precision
multiply is:
1. To read the instruction from memory (R N I sequence) and decode.
2. To read the operand from memory (ROP sequence)
and gate the operand to DB register.
3. To start the arithmetic section when the operand
has arrived.
Main control will then initiate an RNI sequence for
the next instruction. Complete timing is given in the
command timing charts.
In the arithmetic section, main control has just performed the RNI sequence. We will pick up the timing
at V008 of ROP sequence.
V008:
Gate EXX2 to DBR (DBR = (M».
Set K104/105 (start arith 2).
The next odd time that arithmetic is not busy and not
wait function the arithmetic timing chain will receive
a start pulse: N687, N691, or N693 (p. 1-29). *
* Logic
Diagrams
289
(N687, N691, N693, and N659 are the start arithmetic
terms.) Refer to the logic diagrams pages 2-93.
N659, N687, N691 & N693: Start Arith.
Input H510 (clear adder feeders A2 and X).
Set K518/519 (A2 to I 1)toprovidea path for the
multiplier during initialization.
The flow path for a positive multiplier is:
Al to 12 to A2 to II to Al
The flow path for a negative multiplier is:
Al to 12 to A2 to II to Ql
Note: An inverter rank inverts its input.
Set K532/533 (unlike signs 1) via J520 if sign of
multiplier is not the same as sign of multiplicand.
Set K516/517 (AI to 12) if multiplier is negative.
Provides for complementing (A).
The arithmetic section has completed initialization.
1. Ql register holds a positive multiplier.
2. Xl register holds a positive multiplicand.
3. A sign flip-flop "remembers" if like or unlike Signed
operands are to be multiplied.
MU LTIPLY STEP
Static enables that will be up during multiply step are:
Al to 12
Ql to 13
A2 and X to adder (These transfer paths exist
at all times and are never disabled).
Q2 to II
V500, V512, V522: Clear A2 and Q2.
Set K510/511 (right shift); multiply uses right
shift only.
Clear K518/519 (A2 to II) used only on initialize.
Input H513 (13 to Q2).
Input H551 (12 to A2).
V510, V530: Clear adder feeders A2 and X.
Set K560/561 (arithmetic busy) to prevent another start pulse to the arithmetic section during multiply operation.
Input H531 (1 4 to Xl).
, - - - - - Input H503 if MB = ° (short cycle) or
Input H551 (1 2 to A2).
V531, V551: Gate 12 to A2 (A positive: static enable - - - - input H501 if MB = 1 (long cycle) to allow adder
propagation time (figure 290).
Al to 12; A negative: static enable Al to 12
(p. 2-139).
Referring to figure 289, you will notice that if
If K516/517 is set, J865, J866, and 1867 = 1 's,
and J880, J881, and J882 = O's. If K516/517 is
MB = 0, A2 is enabled to 1° inverter rank.
clear, the opposite occurs.
All that happens when the MB = 0 is a right
shift of AQ, 1 bit position.
Gate 14 to Xl (M positive: static enable DBR
to 14; M negative: static enable DBR to 14 I
(p. 2-151).
V501, V513, V551: Set K530/531 (static enable ~
to 10).
For the multiply instruction 1904 translates a
Gate 12 to A2 (static enable Al to 12) and 13 to
1 for 50 (M positive). The 1904 output of a 1
Q2 (static enable Ql to 13).
will drop DBR to 14 enable (]905-1908 =O's) and
V502: Wait for adder.
bring up the DBR to 14 enable Q915-J918 = 1 's).
V503: Advance SCR.
Input H514 (clear AI).
Gate K532/533 to K514/515 (unlike signs 1 to
Input H524 (clear Ql).
unlike signs 2).
V513, V531 if MB = 0; gate 12 to A2 and 13 to Q2.
Input H514 (clear AI).
V504: Clear Al and Ql.
Input H524 (clear Ql).
Transfer SCR.
Set K520/521 (static enable A2 to 10) if MB = (j).
V514, V524: Clear Al and Ql.
Input
H525 (10 to Al shifted 1) ~ Occurs if MB=
Input H555 (lIto Ql).
Input
H565 (1 1 to Q 1 shifted 1) j <2> or 1
Clear K516/517 (AI toI2). Drop enable to comV505, V575: Gate 10 to Al RSI. (Static enable: if
plement multiplier.
MB = 0, A2 to 10; if MB = 1, adder to 10.)
V555: Gate II to Ql (static enable A2 to II). Ql now
Gate II to Ql RSI (static enable Q2 to II).
holels the positive multiplier.
Test bit lof Q2 for next: ~vlB,
Set K528/529 if MB = 1.
Sense first MB; if MB = 1, set K528/529.
Input H500 to restart timing chain.
Input H500 to start multiply step.
Input 11512 (clear Q2).
Input H512 (clear Q2).
Input H522 (clear A2).
Input HS22 (clear A2).
2~O
The enables now present are for swap cycle which must
follow complement cycle.
Short Cycle
V6I3:
MB = 1
Figure 290. Short Cycle Timing
If SCR l' 308 (24I~ repeat multiply step. If SCR =
30 8 , set K520/521 (A2 to 1° enable). Multiply step is
complete.
COMPLEMENT AND/OR SWAP
If sign of multiplier is the same as the multiplicand,
set K588/589
to 13 and QT to 12) static enables for
swap cycle. The timing for swap is continued following
the complement cycle timing.
If unlike signed operands were multiplied, set K516/
517 (static enable Al to 12) and K526/527 (static enable
Ql to 13). This provides the enables to be used in
complementing the product.
orr
A2
Q2
Gate 10 to Al (static enable A2 to 10) and I I to
Q 1 (static enable Q2 to II).
This transfer will place the complemented
product in AQ but will not take place if complementing would produce a 48 -bit -0.
Input H620 to start swap cycle.
SWAP CYCLE
V620: Clear A2 and Q2.
Set K586/587 (complement cycle lockout) to
stop timing chain when swap has been completed. This is also V500 time if like signed
operands were multiplied.
V500: Set K586/587 (complement cycle lockout).
Block input H50I.
Input H6II (starts swap cycle).
V6II: Gate 12 to A2 (static enable QT to 12) and 13 to
Q2 (static enable Al to 13).
Set K556/557 (block 10 to AI) and K558/559
(block l I to QI). These two flip -flops are dis cussed at V6II of complement cycle. The flipflops could have been set during complement
cycle (p. 2-101).
V6I2: Clear Al and QI.
Clear K560/561 (arithmetic busy).
After duplicatin~ Fl into F2and clearing wait function FF, the arithmetic section will be available should
the next instruction require it. Remember that arithmetic has been running' independent of main control
Main control has been performing RNI for the next instruction.
0
Al
Figure 291. Data Flow for Complement Cycle
V500:
Clear A2 and Q2.
Input H611 (p. 2-101) to start complement cycle
timing.
Block input to H501 (stops multiply step timing).
V6II: Gate 12 to A2 (static enable Al to 12) and 13 to
Q2 (static enable QI to 13 ).
Set K556/557 (block 10 to AI) if AQ = 0.
Set K558/559 (block II to QI) if AQ = 0.
Setting of these two flip-flops will occur if the product
in AQ is 0. At this time the swap has not taken place
nor has the sign been corrected (complement cycle).
This will prevent a -0 as a product even if unlike signed
operands were multiplied.
QI
Figure 292.
V6I2: Clear Al and QI.
Clearing Al and Ql is done by N500, N502, N504 and
N5I0, N5I2, N5I4, respectively (p. 2-95).
NOTE: H6I2 on their input AND gates.
ClearK5I6/5I7 (drop enable Al to 12 , p.2-139)
andK526/527 (drop enable Ql to 13 , p.2-145).
Set K588/589 (enable Al to 13 and Ql to 12 ).
Al
Data Flow for Swap Cycle
Summary of arithmetic phase times for a multiply
operation:
Initialize = 5 10 times
Multiply step = 96 to 142 10 times depending on MBs
Swap = 4 10 times
291
V613:
Gate 10 to Al (A2 to 10) and II to QI (Q2 to II).
These transfers are blocked if AQ is holding all
O's at V 611 time.
The mUltiply instruction has now been executed and the
product with proper sign is in AQ register.
COMPARISON OF MAIN CONTROL AND ARITHMETIC TIMING
VOO8
VOO9
V084
V087
V014
NOSI
NOSO
VI17
NOSO
VIIS
VI16
NOSI
NOSO
V061
VOOO
VOOI
VOO2
V003
VOO4
VOOS
VOO6
VOO7
V008
(M) to DBR
N691
VS10
VS31
VS14
VSSS
End ROP of multiply instruction
Set request bus
Set main control priority
[SOD
Set storage request
Set lockout
long
cycle
like
signs
Resync reply
short
VSOI cycle
VS02
VSO
VS04
VS05
VSOO
V611
V612
V613
V620
611
V612 clear busy
V613
Initialize, 1 pass
S Ii-' times
}
Multiply step, 24 passes
6 Ii-' times, long cycle
4 Ii-' times, short cycle
Complement cycle, optional
1 pass
4 Ii-' times
Swap cycle, 1 pass
4 !i-' times
Next instruction to F 1 (best case)
Summary of arithmetic phase (0) times for a multiply operation:
Initialize -= 50t
Multiply step = 96 to 1420t depending on MBs
Complement = 40t
Swap = 40t
MULTIPLY TIMING Worksheet
Indicate what complementing is required after multiply step and the number of short cycles.
1. (A) = 10000000
(M) = S7777777
Complement required: _ _
Number of short cycles:
S. (A) = 40000000
(M) = 00040000
2. (A) = 37777777
(M) = 37777777
Complement required: _ _
Number of short cycles: _ __
List the five preceding multiply operations by number below in order of least time to most time required.
3. (A) = 77777777
(M) == 00000001
Complement required: _ _
Number of short cycles:
4. (A) == 77777777
(Ivl) = 40000000
Complement required:
Number of short cycles:
292
---
Complement required:
Number of short cycles-:-
---
Least time
-----
Most time
SINGLE -PRECISION DIVIDE
Divide A instruction, function code 51, will divide
(AQ) registers by a 24 -bit divisor located at address
M in memory. On completion of divide, the quotient
with sign will be in A register and the remainder with
sign will be in Q register.
(See chapter 3 for description of instruction.)
The divide operation can be sub-divided into three
parts. Refer to the flow chart for divide.
1.
Initialization.
a. Makes (AQ) positive if negative and returns it
to AQ as part of the first divide step. This is
the dividend.
b. Makes the divisor negative, if positive, and
places it in the X register. (A divide is a
series of subtractions, thus, divisor must be
negative).
c. Records if original signs of divisor and dividend are unlike.
d. Records sign of dividend. This determines
sign of remainder.
2. Divide Step.
a. Subtracts divisor from dividend.
b. Ifresult is negative, enable A2 to 1°.
If result is positive, enable sum to 1°.
c. Shift 10 II left 1 to AIQ1.
d. Form quotient bit (QB) of D if result was negative. Form QB of 1 if result was positive and
insert QB into least significant end of Q reg.
bit 00. The quotient is assembled in the Q
register.
e. Continue divide step. A total of 24 passes will
be made.
3. Complement and/or swap. (Complement cycle is
optional but used when necessary; results of executing divide instruction follow the rules of mathematies. )
a. Complement quotient if unlike signed operands
were divided.
b. Complement remainder if dividend was negative.
c. Prevent -0 for both quotient and remainder.
d. Swap A and Q to place the quotient in A and the
remainder in Q.
Swapping A and Q registers at the end of a divide
instruction is done for programing convenience. The
multiply A instruction can follow directly. In many
cases the remainder is not important and the quotient
can be incremented or decremented following divide.
The divide operation will be performed with successive subtraction and left shifting. The arithmetic
adder is additive, so to subtract it is necessary to
complement and add. That is the reason for insuring
that the divisor is negative during initialization.
The following is an example of divide step. Six -bit
registers will again be used to simplify the example.
Six divide steps plus one partial step will be needed to
divide a number.
Problem:
After
step:
361 +- 12 =?
AQ = 0361 = dividend
M = 12 = divisor
initialization~
whieh is part of the first divide
x = 110101
Q
A
1 1 o~o 0 0
1st Step
X=
1 1 1 0 0 0
o0
1 1 0 0 0 1 Sum is negative;
shift AQ left 1.
1 0 0 0 1[Q] QB = 0
/1111 '-
0 1 1.t
100.0 10
2nd Step
X=
1 1
1 0 0
o0 1
1 1 1
1 0 0 0 1 0 Sum is negative;
shift AQ left 1.
0 0 0 1 O[QJ QB = 0
/ IIIII
3rd Step 0 0 1 1 1 1
X= 110101
_ _ _+_1
o0 0 1 0 1
0 0 0 1 0 0
I
..
End-around carry
0 0 0 1 0 0 Sum is positive;
I iii
I / I'I /1 shift AQ left 1.
1 0 1 0 0 0 lOOm QB 1
o0
=
4th Step 0 0 1 0 1 0
X= 110101
0 0 1 0 0 1
+
/1///jl rffl~:i*:~::
11111
o0
0 0 0 0
5th Step 000000
X=
0 1 0 0 1 [] QB = 1
010011
1 0101 01o~o 11
Sum is negative;
I IIIII shift AQ left 1.
o 0 0 0 0 0 1 0 0 1 1[QJ QB 0
=
6th Step
X=
100110
1 1 0 1 0 1
o0
+
.
1 0 0 1 1 0 S
urn·IS negatlVe;
shift AQ left 1.
0 0 1 1 0[Q] QB = 0
/ II , ,'-
0 0 0 1
7th Step 0 0 0 0 0 1
0 0 1 1 0 0
X= 110101)
1 1 0 1 0 1 0 0 1 1 0 0 Sum is negative;
shift Q left 1
o 0 0 0 0 1 0 1 1 0 O[Q] QB = 0
*The sum, -0, will be gated back to A register during
the shift as +0
0
293
---.
RNI
RNI and decode
Initialize and divide step
>---:::r-,-----t~
Complement and/or swap
12 to A2
13 to A2
Clear A2Q2
No
Al to r2
Ql to 13
r--...._--I~W ait adder
Transfer SCR
14 to Xl
Set unlike
if - -;- -
DBR to 14
11--...,....----...,
A. INITIALIZE AND
DIVIDE STEP
1°
A2 to
if QB =
°
Advance
SCR
Yes
Adder to 10
if QB = 1
rO to AI,
left shift 1
except lass pass
II to Ql,
left shift 1
(Q2 to II)
Clear A2Q2
~
I
.~
..--~
A2~o/\J
,----------,
Clear A2Q2
AIQl to A2Q2
via 12 r3
Clear AIQl
B. COMPLEMENT
AND/OR SWAP
A2Q2 to AIQl
via IOrl
Figure 293.
Divide Flow Charts
The last divide step is different only in that A is not
shifted. The sensing of sum positive or negative, the
forcing of quotient bit, and the shifting of Q are all
exactly the same. This is necessary in order to leave
the remainder in tact in "A" yet shift the final QB into Q.
U sing the pencil and paper method, check the answer.
30
12 ) 361
36
01
Q = 30 and A = 01 is a quotient of 30 with a remainder
of 1.
Since complement is not needed in this case, swap
cycle would follow divide step. Swap cycle would present the result as the programmer would see it.
Initialization insures a positive dividend and a negative divisor.
Divisor
1.
2.
3.
4.
5.
Static enables for divide step:
Al to 12
QItbI3
Q2 to II
A2 and X to adder
If the sum is positive, enable adder to 10 (the--out--put of the adder is sum) or, if the sum is negative,
enable A2 to 10 •
M neg
M pos
-UBR
DBR
Figure 294. Data Flow for Initialization
QB: Sum pos = 1
Sum neg = 0
Sum neg - - - - - - - {
Q2
Al
Ql
Figure 295. Data Flow for Divide Step
A divide fault may occur when the divide instruction
is executed. The arithmetic section will sense for a
divide fault on the first and second divide step.
Divide fault will occur if the sum is positive on the
first or second divide step. Both of these two passes
must find the sum negative and force a QB = O. (The
divide step does use the left shift but it is not endaround.)
Divide fault occurs when quotientwith sign cannot be
contained in a 24 -bit register.
The following two examples show a divide fault on
the fir st pas s .
295
00 / 1745 or + 0 divided into any number
L
Q
A
001 1 1 1
X=111111
(001 1 1 0
100 101
command timing charts. For this discussion, timing
covered will that of the arithmetic section. The RNI
sequence of a 510 X and the ROP sequence to V008 time
has taken place.
V008:
. ----I.~+1
..
o0
2.
The next odd time that the arithmetic section is not
busy and not wait function, the arithmetic timing chain
will receive a start pulse, N687, N691, N693 and
N659. (p. 1-29-).
A
Q
001 1 1 1
X=111101
(001100
'----.~
100 101
+1
1 1 0 1 positive on first pass
In the 3300 Computer when a divide fault occurs on
the first pass, it indicates that the quotient would be
more than 24 bits in length.
Below is an example of divide fault on the second
pass:
42
3 / 146
1st Pass
X=
A
Q
000001
100110
N687, N691, N693: Start arithmetic. Input H5000 Input H51 0 (clear adder feeders A2 and X). Input
H512 (clear Q2). (Initialization occurs during
the first divide step.) Set K516/517 (enable
Al to 12) and K526/527 (enable Ql to 13) if Al
is negative; this will permit complementing a
negative dividend. Set K532/533 (unlike signs
1) if dividing unlike signed numbers. Clear
K538/539 (divide fault).
If the divide fault FF is set at this time, it indicates
that a fault occurred on a previous divide instruction.
Since the flip -flop is cleared during initialization of
the divide, its being set at the end of the divide indicates that this instruction produced the divide fault.
V500:
~
100110 Sum negative;
shift AQ left 1
o 0 001 1 /
QB = 0
11101
2nd Pass 0 0 0 0 1 1
X= 111100
1 111 11
o0
0000
111~1fo
Clear A2 and Q2. Clear K530/531 (enable sum
to 10 ). If SCR t- 30, clear K520/521 (enable
A2 to 10). Input H513 (13 to Q2). Input H551
(1 2 to A2).
First pass only: Clear X. Set K512 /513
(shift left). Set K560/561 (busy). Input H531
(1 4 to X).
0 0 1 10 0
/
+
0 0 1 1 0 0 Sum sensed pos;
I'~" shiftO'stoA, Q Ll
0 1 1 0 0 1 QB = 1
If K538/539 (divide fault) is set, block input to H501
and clear K560/561 (busy). This stops arithmetic timing and terminates the divide operation.
V501:
When the divide fault is sensed on first or second
pass, that pass is completed. In the 3200 Computer,
a divide fault on the second pass indicates that the quotient would have been 24 bits long excluding sign.
Timing for the Divide A Instruction
Refer to figure 293. Main control r s responsibility
for single -precision divide:
1. Read the instruction from memory (RNI sequence)
2. Read the divisor from memory (ROP sequence) and
gate divisor to DB register.
3. Start arithmetic section.
~lain control will then initiate an RNI sequence for
the next instruction. Complete timing is given in the
296
Set
1 1 1 1 positive on first pass
307
5 / 1745
17
2
o0
Gate EXX2 to DB register (DBR = (M).
K104/105 (start arith 2) •
V502:
V503:
12 to A2 (AI to 12) and 13 to Q2 (Ql to 13 ) 0
First pass only: If A is negative, gate Al to
12 , block Al to 12 , gate Ql to 13 , block Ql to
13 . 14 to Xl: If M is positive,DBR to 14; if M
is negative,DBR to 14. Gate K532/533 to K514/
5150 (unlike signs I-unlike signs 2). At this
time there will be a positive. Dividend in A2
Q2 and a negative divisor in X.
Transfer SC register (p. 2-115).
Input H514 (clear AI). Input H524 (clear Ql).
First pass only: Set K532/533 if dividend is
n~gqtiy~gIlQ,divtqir.g Uk~ sjgr s " Gleety 1(5261
527 (Ql to 13) used if complemented dividend.
Set K550/551 (block last shift A) ifSCR rank
2 ;: 24100; actually, this would be the 25th half
pass, which is the same as the 24 previous
passes except A is not shifted. (Last QB shifted into QOO).
V504:
Clear AIQl.
First pass only: Clear K516/517 (AI to 12 ),
used if complemented dividend.
Input H565 (l I to Ql shifted). If K550/551 is
clear, input H525 (1 0 to Al shifted). If K550/551
is set, input H515 (IO to Al direct); this would
be the last pass.
V505: 10 to Al (LSI, exceptlastpass). If sumispos. .
A
Tn
ItlVe,
a dde1' to TO·
.L ; 11 sum IS negatIve, 1\.L. to l~.
II to Ql (LSI), Q2 to II. If sum is positive,
insert quotient bit of 1; if sum is negative, insert quotient bit of O.
1:
•
•
V612:
Clear Al if K542/543 is clear. Clear QI if
K592/593 is clear. Clear K516/517 (AI to 12)
and K526/527 (Ql to 13 ) as complement enables
no longer needed. Set K588/589 (AI to 13 and
Ql to 12) enables for swap.
V613:
Gate 10 to Al (A2 to 10 ) if K542/543 and K556/
557 are clear. (The N5XX gating terms are on
p. 2-95 and the flip-flops are on p. 2-127.)Gate
I 1 toQl(Q2 to Il)ifK592/593 andK558/559 are
clear. Input H620 to start swap cycle timing.
V500:
Block input H501 if complement cycle not required or
V620:
if complement cycle just completed. Clear
K542/543 (block clear AI) and K592/593 (block
clear Ql) Clear A2 and Q2. Set K586/587
(complement cycle lockout). Input H611.
n
QOOO
QOOI
Sum to 10
(When sum pos)
Figure 296,
A2 to 10
(When sum neg)
0
Left I
(II to Ql)
For the divide, 1023 = QB.
The path for the quotient bit looks complex,
but it allows for other transfers also, such as
AQ end -around left shift.
Input H500 (to continue timing). Input H512
(clear Q2). Input H522 (clear A2).
If SCR rank 2 f:. 24 10 , repeat divide step. If
SCR rank 2 = 2410, continue to complement and/
or swap. If K532/533 (unlike signs 1) is clear,
proceed to swap (V500) as divided positive by
positive.
If K532/533 (unlike signs 2) is set, continue
with complement cycle. The flip-flop's being
set indicates unlike signed operands where divisor and/or dividend were negative.
Set K516/5I7 (AI to 12) enable for the complement. Set K526/527 (Ql to 13 ).
V500:
V611:
Gate 12 to A2 (AI to 12) and 13 to A2 (AI to 13 ).
V6I2:
Clear Al and QI; clear K560/56I (busy), K556/
557 (block 10 to AI), and K558/559 (block II to
QI).
V613:
Gate 10 to AI(A2 to 10 ) and II to Ql (Q2 to II).
Path for Quotient Bit
Clear A2 and Q2. Input H611 (starts complement cycle timing). Block input to H501 (stops
main arithmetic timing).
V6I1, V621: (See p. 2-101). Gate 12 to A2 (AI to 12
enable) and 13 to Q2 (Ql to 13 enable). Actual
complementing of data occurs right here. If
dividend (original (A» is positive, set K542/543
(block clear AI) to leave the remainder positive.
If dividend (original (A» is negative, set K592/
593 (block clear Ql) to leave the quotient positive. If Al = 0, set K556/557 (block rO to AI)
to prevent a remainder of -0. rO contains complemented (AI) at this time). If Ql = 0, set
K558/559 (block II to Ql) to prevent a quotient
of -0. II contains complemented (Ql) at this
time).
General Arithmetic Timing for Divide
N687, N691, N693
V500
V50I
V502
V503
V504
V505
L--_ _ _ _ _ _ _ _
Start
Set busy on first pass.
Transfer SCR RSI to RS2.
Advance SCR RS2 to RSI.
If SCR RS2 f 24, repeat divide
step. 1£ SCR RS2 = 24 (divide
. . . - - - - - - - - - - step complete) and + -;- + or
~C-V-50-0------}-
V611
V6I2
V613
V620
}
V500
V611
V6I2 Clear busy
V6I3
+ -;- - or - -;- + or - -;- Complement cycle (40 times)
Swap cycle (4 0 times)
1. How long would K560/561 (arithmetic busy) be set
if divide fault were sensed on the first divide step?
_ _ _ _ _ On the second divide step? _ _ _ __
20 How long would K560/561 (arithmetic busy) be set
if the divide operation included the complement
cycle?
297
SE LF -EVALUATION QUIZ ON CHAPTER 12
TRUE OR FALSE:
1. The arithmetic section of the 3300 is partially independent of main control since it has its own tim ing chain and its own F register.
13. An interrupt may not be sensed during execution
of an 06 instruction because Rap to Rap cycle progression is used.
2. The 3300Adderis subtractive in nature and yields
an output of sum.
14. A -+0 does not equal -0 for the 07 instruction.
3. If -0 were added to -0 in the 3300Adder, the sum
would be -+0.
4. A selective complement is an exclusive OR function.
5. A logical product is a boolean AND function and
does not require the adder.
6. Optional hardware is necessary to perform a 48bit precision add in the 3300.
7. The adder is not used in the execution of a single precision load instruction.
8. The adder forms part of the transfer path for the
enter A instruction.
9. An 10 to sb transfer is necessary for the load I instruction.
15. A swap cycle will always occur at the end of the
single -precision multiply instruction.
16. The multiplier for the single - precision multiply
instruction is located at M and M + 1 and this quantity will affect the amount of time necessary to execute the instruction.
17. The divide step of a single - precision divide instruction require 318 arithmetic passes.
18. A swap cycle is optional at the end of the singleprecision divide instruction.
19. Adder propagation requires 4 III times.
20. Both the 50 and 51 instructions set K560/561 (arithmetic busy) to insure that main control will not
generate additional start pulses while the instruc tions are being executed.
10. The transfer path Xl to l I to Ql is used for the
load Q instruction.
11. The 52 instruction will advance P during its first
Rap.
12. The compare out-of-limits FF will set for each
arithmetic pass of the 52 instruction.
Score Yourself:
This was a good quiz.
If you missed none or one, congratulations!
If you missed two or three, you're okay.
If you missed four or more--I don't know you!
POWER
PANEL
MULTIPROG.
MODULE
FP/DP
OPTION
STANDARD
ARITHMETIC
BLOCK
CONTROL
MAIN
CONTROL
110
CH.
P
0
W
E
R
P
A
N
E
L
INTERRUPT
I
Figure 297.
Physical Location of the FP/DP Option
CHAPTER 13
FLOATING-POINT /
DOUBLE-PRECISION OPTION
The F.P/DP Option gives the 3300 System hardware
capabilities for executing the instructions listed in
table 20. The FP /DP Option is designated 3310 and
becomes part of the CPU when added to the system.
Physically, the FP /DP option is located in chassis
4 and consists primarily of a 24-bit optional adder
and a 48-bit E register. The optional or left adder is
disabled during single precision operations but during
double precision operation the optional adder operates
on the higher order 24 bits. Figure 297 shows the
physical location of the FP /DP option. Figure 298 is
a block diagram of the arithmetic section w.ith the
FP /DP option present.
ENABLING THE 48 -BIT ADDER
During the 56, 57, and 60 -63 instructions the 48bit adder is enabled by setting K804/805 (optional arithmetic busy). Figure 299 is a simplified logic diagram
showing how optional arithmetic busy affec.ts the adder Reference figure 299 and consider the following
cases:
0
Case 1. Assume optional arithmetic busy set and a
48 -bit operation in which group 8 is a generate and
groups 9 -15 are passes. See the diagram below.
Note that these conditions generate a carry input to
group O. The hardware operation begins with optional
299
Table 20. FLOATING-POINT/DOUBLE -PRECISION INSTRUCTIONS
ADDRESS FIELD
OPERATION FIELD
55 ELQ
QEL
EUA
AEU
EAQ
AQE
56 MUAQ, I
57 DVAQ, I
60 FAD, I
61 FSB, I
62 FMU, I
63 EMD, I
-
- - -
-
-
- -
INTERPRET ATION
Transfer (E L) to Q
Transfer (Q) to E L
Transfer (EU) to A
Transfer (A) to EU
Transfer (E) to AQ
Transfer (AQ) to E
Multiply AQ
Divide AQ
FP addition to AQ
FP subtraction from AQ
FP multiplication of AQ
EP division of AQ
- - -
- - - -
-
- - -
-
-
- -
m,
m,
m,
m,
m,
m,
b
b
b
b
b
b
*
*
I
i
XI
X2
LEn~I
"'-
/'
/'
~/
(
./
('//
E~
E~
I
l __)_-~~--~r-----'------ _)-.--_24_BIT5
~
_ _ _ _ _ _. . . ._ " " " "_ _ _ _ _ _" " , _ , ,
EI
U
E~
""-'I
EI
L
,..~-_-~-~_-;-=-G-IS-_~-E_-R-__ .......... ~'~"'_-;-'Tl-R-E-G-IS-~-~-~-_"_-~"']
_
-_... ......,--_.•._--
~/
!
E--
5
x'
A
--'
FLOATING POINT
EXPONENT ONLY
"
10
(
8.
'i
I
I
10
8
I
,
I4 INVERTERS
LT--r~r,I
I
I~
A'
AI
XI
XI
SHIFT COUNT
-----y---'
EXPONENT
SH I FT
COUNT
E[ BUS
BUS
Ql
ONLY
* OPTIONAL
ARITHMETI C LOGIC
Figure 298. Block Diagram of Arithmetic Section With Floating-Point/Double-Precision Option Present
300
o
GROUP 0
LikE U200
o UNLIKE
UOOO
PASS GROUPS 4 -15
t06A
U3.o4
U30S
U306
U307
---
(F.P./D.P. 8USY)(PASS 12- 15) U~OZ
.
4
L504
5 1.505
CARRY INPUT
FROM GROUP
'-025
{8)
U026
L~08
GENERATE GROUP '"
AND PASS GRO-tJPS 9-15
L024
U508
1..508
{9J
L509
(10)
LSW
ut)
LSII
(l3)
l513
(14)
LSJ..4
..(-is.)
L515
~~:rDIIA
U310
050!
U311
PASS GROUPS 8-1J
_
U912
~~~:reIlB
U3J4
U502
-PASS GROUPS 12-J5
U315
'tJ8-12
Figure 299. Enabling the 48-Bit Adder
For this case L508 = 1 which forces U702 = O. U702
breaks the input to L200 and L200 = 1 which indicates
that group 0 has a carry input.
arithmetic busy being set which drive s U81 0 and U812 to
O. U810 being a 0 enables L508 through L515 to sense
for generate and pass conditions in the optional adder.
15
14
13
12
11
10
9
8
\~-------------------~~----------------------~I
V
Optional adder
Case 2. Assume optional arithmetic busy set and a
48-bitoperationinwhichgroup3 is a generate, groups
4 through 7 are passes and group 8 is a pass. See
diagram below. These conditions would generate a
carry input for a 24-bit adder but not for the 48 -bit
adder.
First consider case 2 for the 24 -bit adder. Optional
arithmetic busy is clear therefore U812 = 1 forcing
U501 and U502 to O. Groups 4 through 7 being passes
7
6
5
4
3
2
1
0 Groups
\~--------------~V~--------------~I
Standard adder
drives U500 to 0 and U600 goes to 1. L403 = 1 since
group 3 is agenerate; therefore L403 and U600 drives
U700toa 0 which breaks the input to L200. L200 goes
to 1 which says carry input to group O. If performing
a 48-bit add, optional arithmetic busy is set, therefore U812 = 0 allowing U501 and U502 respectively to
sense for pass groups 8 -11 and pass groups 12 -15.
Forcase 2 U501 would sense group 8 pass and go to 1
which drives U600 to 0 and group 0 would not sense a
carry input for this case.
301
x
x
x
x
x
x
x
\15
14
13
12
11
10
9
I pa'0af;})a£a:};a2Gen I x
8
/
V
Optional adder
\
7
6
4
5
3
2
V
x
X
1
0
/
Standard adder
DOUBLE-PRECISION MULTIPLY
23
18 17 16 15 14
00
Instruction Description
Multiply (AQ) by the 48 -bit operand in addresses M
and M + 1. The 96-bit product is displayed in AQE.
Refer to figure 300 for operand formats. For every 0
bit in the multiplier the evecution time is decreased
by 125 nsec.
MUAQ multiply AQIL-~56~......I~a.;.....a..1~b---LI_~m~---I1
a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bh)
Multiplicand 48 -bit
47
I
23
I
00
A
\
00 23
00
I
A register
Q register
I
Multiplier 48 -bit
47
00
A
I
23
I
23
00
I
M
00 23
A register
\
00 23
00
M + 1
I
47
Q reg!ster
00
E register
V
96-Bit product
Figure 300. Operand Format for Double-Precision Multiply
SIX-BIT EXAMPLE FOR MULTIPLY
In order to realize the steps that the computer must
take to execute a multiply instruction assume you have
a 6 -bit machine and attempt a double -precision multiply with pencil and paper. The following conditions
exist:
(A) = 40
(Q) = 25 multiplicand
(:M + 1) = 05 ~1.11tip1icr
(M) = 35
With pencil and paper, position the operand thus:
40258 multiplicand
35058 multiplier
The multiplicand is a negative number and must be
complemented before performing a mUltiply. If the
multiplier had been negative it would have been necessary to complement it as well. The computer must
perform the multiply with positive operands. The corn puter would have performed the same steps. The problem has been initialized and appears as:
(- )37528 multiplicand
(+)35058 multiplier
Perform the multiply step.
( - )3752S multiplicand
X (+)35058 multiplier
23622
23622
13676
( - ) 16304022
The product shown is correct in actual value, but
since it is negative it must be complemented to be represented in the computer. The third and final step of
a double -precision multiply becomes complement. The
final result would be:
6 147 3 755
Note that a three -step operation was necessary .
1. Initialize - gives positive form of multiplier and
multiplicand properly positioned for mUltiply.
2. Multiply step - performs actual multiplication and
always yields a positive product.
3. Complement - necessary any time the product is to
be negative.
DETAILED TThlING
Figure 301 is a detailed flow chart of double -preci sion multiply. In order to accomplish the three major
steps of double -precision multiply, several steps are
involved and some operations take place in parallel.
Figure 302 is a graphic representation of parallel tim ing chains involved.
Vl15:
Vl16:
N207:
N206:
Vl09:
V5l8:
V5l9:
V520:
Set K012/0l3.
Test breakpoint stop if BPO selected.
Set K572/573 (wait function).
Set K570/57l (initiate Fl to ?).
If arithmetic not busy, input to H5l8.
Fl to F 2 , clear K570/57l.
Clear K552/553 (sign of A)
Clear K572/573; clear SCR; setK552/553 if(A)
negative.
Resynced storage reply, set K060/061.
Clear KOOO/OOI (request bus)
V061:
VOOO:
VOOl:
V002: Set KlOO/lOl (start arithmetic 1).
V003; Vl09: Input to HIOO.
V004; VlOO: Clear KIlO/Ill (main control priority);
(enable 10 to F).
V005: Set K062/063 (2nd cycle).
V006: Input to H40l, input to H20l.
V007: Clear KOIO/Oll, K012/0l2, Kl16/ll7;
clear DBR, clear F
, input to H4l0;
L15
input to HllO.
V008; VllO: EXX2 to DBR, input to H449.
Second ROP
Set KOOO/OOl, set KI04/l05 (start arithmetic 2).
V009; Vl05; N05l:
Input to H084, input to Hl02;
if K2l0 = 1, set KOIO/Oll;
gate F to S bus, T655 off.
DETAILED TIMING FOR INITIALIZE
At V008 time (M) is gated to DBR, which places the
highest order bits of the multiplier at an entrance p:::>int
to the arithmetic section. Also, at V008 (VllO) time
the new address, M + 1, is gated to Flower 15 so that
at V009 time the proper address for the 2nd ROP is
on the S bus.
Detailed timing starts at V007 time of RNI.
FADR
V007
VOOS:
V009:
VOI0:
VOll:
Set K536/537, set K596/597.
N687, N691, N693, N659: start arithmetic.
V500: Clear Xl and ~.
static enables: + I to
V502:
V503:
F"to
EXX2 to Flo
If arithmetic busy, set KOOS/009.
Test interrupts, clear K002/003.
Input to HOSO.
L
First ROP
V080:
Vl09:
VllO:
N05l:
N050:
Vll7:
N050:
Set K084/085 (ROP); set Kl12/ll3 (no index~
clear K080/08l (RNI).
Input to HllO.
Set KOOO/OOI (request buss); clear Kl12/ll3.
If K2l0 = 1, set KOIO/Oll, gate Fto the s bus,
T655 off.
Input to Hl17.
Set K2l2/2l3 (priority 2); set Kl16/ll7 (storage request); transmit a storage request.
Input to Hl15.
V504:
V505:
6
5
1
I
Clear K596/597;
set K850/851 if (M) ne~ative;
set K850/85l (DBR--.t± enable)if (M) negative.
N687, N691, N693: start arithmetic;
if sign of A f. M, set K532/533;
input to Hl04.
The arithmetic timing shown above forms the address
M + 1 and records whether or not numbers with unlike
signs are being multiplied.
VI06; Vl04; N050: Clear KIlO/Ill, clear Kl04/105;
(VI02)
input to Hl17, block V084.
303
Arithmetic busy
RNI and
decode
ROP at
M +1
ROP
atM
RNI at
P+l
Form
M
+1
Record (M)
negative
XZXl--.Einv
Einv-+E1
(M) ___ E 1
= Multiplier
Xl--'XZ
Record sign
of (A)
Complement
(AIQl)
AIQl-'AZQZ
El-+EZ
EZ...... Einv
Einv--.. E1
AZQZ .....AIQl
Left add~IO
Right add-..I 1
I°-.Al
Right 1
Figure 301, Flow Chart for Double-Precision
:i04
~\ilultiply
Il..... Ql
Right 1
EZ .... El
Right 1
INITIALIZE
MULTIPLY
STEP
I
I COMPLEMENT
I
I
RNI
I
db++l
READ
MULTIPLY STEP
48 PASSES
10
I
ARITH
I
I ARITH
~1-.-_----=~
I
COMPLEMENT
AQE IF
NECESSARY
I
I
Figure 302. Graphic Representation of
Parallel Timing for 56. X
V117:
N050:
V115:
V116:
~b
At the first N051 time above, storage is requested for
(M+l). Notice that at Vl16 time a breakpoint operand
is possible.
Clear Xl and A2 ; clear K536/537.
V501:
14 to Xl: M positive, '0BR to
M negative, DBR to
input to H854.
Clear X2 , input to H855.
Xl to X2 , set K800/801 (wait word 2).
V502:
V503:
V504:
V505:
r4;
r;
V084: Clear K084/085, clear Kl04/l05, '3et KOSO/081
(RNI is to be next); input to H087.
V087: Input to H014.
V014: RNI at P + 1.
Access is timed out for the 2nd ROPandat V008 (M+l),
which is the lower order bits of the multiplier, is gated
to DBR. The arithmetic start which occurs at V009
time will be used to complete the initialization phase.
At V087 time VOl4 is entered to initiate RNI. If the
next instruction requires the use of the arithmetic
section its execution will be held up until the completion of the double precision multiply.
N687; N69l; N693:
V500:
The arithmetic timing shown above places the positive
value of M in X2.
V06l:
VOOO:
VOOI:
V002:
V003:
V004:
V005:
V006:
V007:
COMPLEMENT AQ
""----IF NECESSARY
Set K212/213 (priority 2);
set K116/117 (storage request) transmit a
storage request.
Input to H115.
Set K012/013 (enable data bus).
Test breakpoint stop if BPO selected.
V500:
---_,-....;
Resynced Storage Reply.
Clear KOOO/OOI (request buss).
Clear K060/06l (1st cycle).
Clear K062/063 (2nd cycle).
Input to H401.
Clear K019/0ll, K012/0l3, Kl16/ll7;
clear DBR, input to H4l0.
V008: EXX2 to DBR, set Kl04/l05 (start arithmetic 2~
V009; Vl09: Input to Hl04 and H084; the arithmetic
section receives a start pulse that is coincident with V009.
V50l:
V502:
V503:
V504:
V505:
V611:
V612:
V613:
Input to H500, H5l0 and H512;
start arithmetic coincident with
V009 time of the 2nd ROPcycle;
if a negative setK852/853 (Complement AQE).
Clear Xl and ~Q2; input to H6l1. If K852/
853 is set, input H53l, set K560/56l ar-ithmetic busy.
to Xl:
If K850/85l set, DBR to 14;
if K850/85l clear, DBR to 14.
Clear K850/85l (DBR to 14 enable); setK802/
803 (word 2).
Input H834; input to H6l2 if K852/853 is set.
Set K804/805 (busy), clear E I ; input to H9l5.
Einv to El (X2 X l to Einv.); (M and M+l) --.
X2Xl-.El = multiplier).
2
2
3
3
I to A2 (AI to I ); I to Q2 (Ql to I ).
Clear AI~; input to H613.
10 to Al (A2 to 10); II to Q 1 (Q2 to II); first
pass only: input to H810.
r
The arithmetic timing is used to place the multiplier
in its positive form in EI. Refer to figure 303 for a
simplified data flow diagram. At V 501 time of the
305
The arithmetic timing is used to place the multiplier
in its positive form in EI (figure 303). At V501 time
of first pass of multiply step the positive form of the
multiplicand will be placed in X2 Xl and initialization
is completed (figure 305). At V500 time K560j561
(arith busy) is set, which will exclude main control
from the arithmetic section until execution of this instruction is completed.
The above timing involves the complement and swap
timing chain. This timing would occur only if it were
necessary to complement the multiplicandinAIQI (figure 304).
E
INV
,-----I
r-----
I
--
.....
I
I
I
L- _
(M) P~S
(M) NEG
(M+l)-Figure 303. Data Flow for Initialize
Multiplier to E 1
(M)
DBR
Figure 305.
Multiplicand to X2Xl
~'--'--T-~t31
~__~t
i~----~
Figure 304. AQ Negative (Positive Form of
l\Iultiplicand to AIQl)
Figure 305 shows the enables and transfer paths for
multiply step. Become familiar with this before going
through the detailed timing of multiply step.
RIGHT I
Xl
Figure 306. Enables for Multiply Step
MULTIPLY STEP
Clear E2, input to H871;
clear A2Q2; input to H611 (blocked first pass).
*Clear Xl and X2, input to H811;
clear K800/801 (wait word 2).
*Al to X2, 12 to Xl (Ql to 12 ).
V50l: El to E2;
short
12 to A2 (Ql to 12) blocked first pass;
cycle
13 to Q2 (AI to 13 ) blocked first pass.
lV502
:'\1503: Clear K898/899 (short cycle), advance SCR;
input to H612 and H895.
Clear K802/803 (word 2);
set K810/811 (multiply 2).
V504: Clear AIQIEl: transfer SCR;
input to H525, H565, and H895;
set K898/899 (short cycle) if bit 1 of E2 = 1.
V505: E2 to El RSl, 10 to Al RSl, II to Ql RSl;
if MB = 0, Q2 to 10, A2 to II;
if MB = 1, left adder to 10, right adder to II;
input to H500, H620, and H820;
if SCR =/- 608' repeat multiply step;
if SCR = 608' setK852/853 (complementAQE);
clear K898/899 (short cycle).
:V500:
MULTI PLI CAND
N GTE: Optional adder to 1°
Standard adder to II
X2 and Q2 to optional adder
Xl and A2 to standard adder
Refer to arithmetic chapter for a detailed analysis of
a computer multiply. The main items in multiply step
are:
1. Long and short cycle capabilities. A long cycle
consists of 6 ~ times and is necessarily long to
allow for adder propagation. The short cycle consists of 4 ~ times and is used when the multiplier
bit is a 0. The time for a 56 instruction is dependent on the multiplier (M, M + 1)
0
2. Shift count register. 4810 or 608 passes must be
made during multiply step. It is the responsibility
of the SC register to keep count of the passes. A
count of 608 indicates terminate.
3. A long cycle will always occur on the first pass.
Onpasses 1-47, E201 will be tested for short cycle
on the next pass. MB for the present pass will
always be E2000 This determines the enables into
l0ll; e.g., "Q2A2 or sum.
4. On the first pass A2Q2 is cleared and AIQl is not
gates to Q2A2. This insures that if the first multiplier bit were a 1 that the multiplicand would be
added to all zeros.
COMPLEMENT STEP
*First pass only.
V500: Clear A2Q2E2, clear K806/807 (multiply 1);
clear K810/811 (multiply 2);
input to H611 and H871.
307
V501: El to E2;
12 to A2 (AI to 12);
13 to Q2 (Ql to 13).
V502
V503: If signs unlike, input to H612 and H834.
V504, Clear AIQIEI;
input to H915 and H613 if AQE f O.
V505: Input to H864.
Einv to El (E2 to Einv);
10 to Al (A2 to 10)
lIto Q 1 (Q2 to II).
V684: Clear K560/561 (arith busy).
Clear K804/805 (optional arith busy).
a = addressing mode designator
b = index register designator
m = storage address; M = m + (Bb )
Instruction Description
Divide (AQE) by the 48 -bit operand in addresses M
and M + 1. The quotient is displayed in AQ. The remainder with its sign extended is displayed in E.
If a divide fault occurs, program execution advances
to the next address. The final contents of AQ and E
are meaningless if a divide fault occurs. Refer to figure 307 for operand formats.
SIX-BIT EXAMPLE FOR DIVIDE
In order to visualize the steps that the computer
must take to execute a divide instruction assume you
have a 6-bit machine and attempt a double-precision
divide with pencil and paper. The following conditions
exist:
The clearing of K560/561 at V684 time frees the
arithmetic section for use by main control. The arithmetic timing shown will occur regardless of whether
or not a negative product must be formed. The data
transfers shown below occur only if the complement
is necessary.
(A)
E1 to E2 to Einv to El;
Al to 12 to "A2 to 10 to AI;
Q1 to 13 to Q! to II to Ql.
= 61 (Q) = 47 (E) = 3756
+ 1) = 05
(M) = 35 (M
With pencil and paper, position the operands thus:
divisor 3505) 61473756
DOUBLE -PRECISION DIVIDE
23
DVAQ divide AQ
~
I
57
18 17 16 15 14
a
b
I I
Dividend
Divisor
The dividend is a negative number and must be complemented before performing a division. If the divisor had been negative, it would have been complemen ted for the pencil and paper example as well. The com-
00
I
dividend
m
96-bit dividend
________________________________________
__________________________________________
--JA~
~5
~
\
00
00 23
23
00
A register
00
47
E register
Q register
~
48 -bit divisor
________________
__________________
--JA~
/
~
\
47
00
23
I
00
0023
M
M+1
r--_ _ _ _ _ _ _4_8_--JbX
quotient
I
\
47
00
23
I
00
0023
A regitlter
Q register
48 -bit remainder
~----------------~I\~--------------------~\
{7
I
308
00
E l"egi::;ter
Figure 807.
Operand Format for
Double"-Precision Divide
puter divides by a series of subtractions, thus always
requires the negative form of the divisor. For this
example the computer has to perform the same steps
as above plus complementing the divisor. The problem would appear as:
divisor (+)3505) ( -)16304021 dividend
DETAILED TIMING
Figure 308 is a detailed flow chart of the doubleprecision divide. In order to accomplish the four
major steps of the double -precision divide, several
operations are involved and some take place in parallel. Figure 309 shows parallel timing and the individual timing chains involved.
Perform the divide step.
divisor
3751
+3505) (-)16304021
12717
33650
31343
23052
22131
7211
3505
3504
~----:---:---:-~-
quotient
dividend
remainder
The main items in divide step are:
1. When the computer executes the divide step, the
quotient is in E and the remainder in AQ. The programmer prefers the quotient be in AQ so hardware
performs a step called swap. Swap, which follows
divide step, places the quotient in AQ and the remainder in E. After swap we have:
(AQ)
(E)
2.
= 3751
= 3504
quotient
remainder
The computer always performs the divide step with
positive dividend. At the termination of divide
step the positive value of the operands is available
in AQ and E. The law of signs for division states:
Only when dividing unlike signs is the quotient negative; the remainder always has the same sign as
the dividend. In order to form a negative answer,
the computer must perform a complement step.
After complement step the final result is:
(AQ) = 4026
(E) = 4273
quotient
remainder
For this example note that four-step operation was
necessary.
1. Initialize - yields the positive form of the dividend
and divisor properly positioned for the divide step.
2. Divide step - performs the actual division and always yields a positive qnotient and a positive remainder.
3. Swap - places the positive form of the quotient in
AQ and the positive value of the remainder in E.
4. Complement - forms a negative quotient and/ or
negative remainder.
DETAILED TIlVITNG FOR I},TITLA>.LIZE
Detailed timing starts at V007 time of RNI.
V007:
V008: EXX2 to Fl.
V009: If arith busy, set K008/009 (sense interrupt
during arithmetic busy).
VOlO: Test interrupts, clr K002/003 (RNI lockout).
VOll: Input to H080
V080: Set K084/085 (RaP), set Kl12/ll3 (no index)
clear K080/08l (Rt-."'I).
Vl09: Input to HllO.
VllO: SetKOOO/OOl, (request bus) clear Kl12/ll3
N05l: IfK2l0 ="1", set KOIO/Oll, (main control priority) gate F to the liS" bus, T655 OFF (read
request)
N050: Input to Hl17
Nl17: Set K2l2/2l3 (priority 2)
Set Kl16/ll7, transmit a storage request (T650).
N050: Input to Hl15.
Vl15: Set K012/0l3 (enable data bus).
Vl16: Test breakpoint stop if BPO selected.
N207: Set K572/573 (wait function).
N206: Set K570/57l (initiate Fl to F2).
Vl09: If arith not busy, input to H5l8.
V5l8: Fl to F2, clear K570/57l.
V5l9: Clear K552/553 (sign of A).
V520: Clear K572/573.
Clear SCR
Set K552/553 if (A) negative
V06l: Resynced storage reply, set K060/06l (1st
cycle).
VOOO: Clear KOOO/OOI (request bus).
VOOl:
V002: Set KlOO/lOI.
V003, Vl09: Input to HlOO.
V004, VlOO: Clear KlOO/lOl, set KIlO/Ill.
V005: Set K062/063 (second cycle).
V006: Input to H40l, input to H20l.
V007: Clear KOlO/Oll, K012/0l3, Kl16/ll7, clear
DBR, clear FL15, input to H4l0, input to HllO.
V008, VllO: EXX2 to DBR, input to H27l 2nd Rap
set KOOO/OOl, (request bus) setKl04/l05
V009, Vl05, N05l: Input to H084, input to Hl02 if
K2l0 = "I", set KOIO/Oli. Gate F to "S" bus,
T655 off (read) input Hl04.
309
I
RNI
DIVIDE STEP
4910 PASSES
a.~1
ARITH
ARITH
'------'
FORM M+ I
(M) TO
: SWAP
ARITH
: COMPLEMENT
I
I
I
I
I
I
ARITH
I ARITH
~-----'~......--~--........---I
TO
i
Xl
COMPLEMENT AQE
- - - I F NECESSARY
Figure 309.
Parallel Timing for 57 • X
-----fa
FADR
V500: Clear Xl and A 2 .
Clear K536/537.
V50l: 14 to Xl: (M) negative, DBR to 14
(M) positive, DBR to 14
Input to H5S4.
V502: Clear X2 , input to H355.
V503: Xl to X 2 , set KSOO/SOI (wait word 2).
V504:
V505:
Set K536/537, set K596/597.
N6S7, N69l, N693: Start arith.
V500: Clear Xl and A2 .
V50l: 15 to A2, 16 to Xl
V502: Static enables: +1 to 16 .
V503: FL to 15.
V504: Clear K596/597, if (M) positive set KS50/S5l
V505: N6S7, N69l, N693: Start arithmetic, ifsignof
A = M, set K532/533.
The arithmetic timing shown above forms the address
M + 1 and records whether or not operands with unlike
signs are being divided.
At VOOS time (M) is gated to DBR, which places the
highest order bits of the dividend at an entrance point
to the arithmetic section. Also at VOOS/VllO time the
new address, M + 1, is gated to Flower 15 so that at
V009 time the proper address for the second ROP is
on the S bus. The setting of K060/06l and K062/063
(first and second cycle FF's) allows J063 (logic'diagrams 2-5) to go to "1fT. J063 being "1 fT blocks VOS4
(end ROP) and allows ROP to ROP cycle progression
by preventing the clearing of the ROP FF.
Vl06, Vl04, N050: Clear KIlO/Ill, clear Kl04/l05.
(Vl02)
Input to Hl17, block VOS4.
Vl17: Set K2l2/2l3 (priority 2).
Set Kl16/ll7, transmit a storage request
(T650).
N050: Input to Hl15.
Vl15: Set K012/0l3 (enable data bus).
Vl16: Test breakpoint stop if BPO selected.
At the first N05l time shown above, storage is requested for (M + 1). Notice that at Vl16 time a breakpoint operand is possible.
I
--------I
The arithmetic timing shown above places (M), the
highest order bits of the divisor, in ~.
V06l:
VOOO:
VOOl:
V002:
V003:
V004:
V005:
V006:
V007:
Resynced storage reply.
Clear KOOO/OOI (request bus).
Clear K060/06l (first cycle).
Clear K062/063 (second cycle).
Input to H40l.
Clear KOIO/Oll, K012/0l3, (enable data bus)
Kl16/1l7 (STO request).
Clear DBR, input to H4l0.
VOOS: EXX2 to DBR, set Kl04/l05.
V009: Vl09: Input to Hl04 and HOS4.
The arithmetic section receives a start pulse that is
coincident with V 009. The timing continues on the next
page.
VOS4: Clear KOS4/0S5, clear Kl04/l05, set KOSO/OSl,
input to HOS7.
VOS7: Input to H014.
V014: RNI at P + l.
Access is timed out for the second ROP and at VOOS
time (M + 1), which is the lower order bits of the divisor, is gated to DBR. The arithmetic start which
311
occurs at V009 time will be used to complete the initializationphase. At V087 time V014 is entered to initiate RNI. If the next instruction requires the use of
the arithmetic section its execution will be held up until
the completion of the double precis ion divide.
N659, N687, N691, N693: Start arithmetic coincident
with V009 time of the second ROP. If (A) negative set K852/853.
Input to H500, H510, H512, H820.
V500: Clear A2 Q2 E2 and Xl.
Input to H871, set K560/561 (arithmetic busy)
V501: 14 to Xl: If K850/851 set, DBR to 14.
If K850/851 clear, DBR to 14.
E1 to E 2 .
V502: Clear K850/851 (bus to 14 enable).
Set K802/803 (word 2)
V503: Input to H612 if K852/853 (comp AQE FF) is set.
Input to H834 if K852/853 is set.
V554: Set K804/805 (busy).
V505: Set K808/809 (divide I).
Input to H500, H620, H820.
Clear K852/853 (compl AQE).
(M) POS.
Input H61l if K852/853 (comp AQE FF) is set.
V611: 12 to A2 (AI to 12).
13 to Q2 (Q1 to 13 ).
Clear AI' Q1, E1·
Input to H612 and H915 if K853 is set.
10 to Al (A2 to 10).
II to Q1 (Q2 to II).
Einv to E1 (E2 to einv).
The arithmetic timing shown above completes the
initialization phase by -placing (M + 1) in Xl. Refer
to figure 310 for the dataflow of the divisor into X 1X2.
At V500 time K560/561 (arithmetic busy) is set,which
insures that main control cannot get into the arithmetic
section until the execution of this instruction is complete.
The above timing involves the complement and swap
timing chain. This timing would occur only if it were
necessary to complement the dividend which is in
Al Q1 E 1. Refer to figure 311 for a simplified data flow
diagram.
{M)NEG.
- - - - -Flow for (M)
- - - - - Flow for (M + 1)
Figure 3 I O. Divisor to X2Xl
312
Figure 311. Complement AQE
DIVIDE STEP - Remainder in AQ; Quotient in El
QUOTIENT BIT
~--~~~------------- LEFT
I
DIVISOR
Figure 312 shows the enables and transfer path for
divide step. Become familiar with this before proceeding through the detailed timing of divide step.
V500: Clear A2, Q2, E2; clear KSOO/S01 (wait word
2); input to H611 and HS71.
V501: 12 to A2(QI to 12); 13 to Q2(AI to 13);EltoE2.
V502: If last cycle and :E2 bit 46 or 47 is set, set
K53S/539, (divide fault).
V503: Input to H612 and H834.Clr KS02/S03 (word 2).
V504: Clear AI, Ql, and El; input to H905;
if last cycle input H525 and H565.
Figure 312. Enables for Divide Step
Note: Optional Adder to 1°
Standard Adder to I I
X2 and Q2 to Optional Adder
Xl and A2 to Standard Adder
If SCR = 60S, set KS12/S13 (last cycle).
Advance SC -register.
Transfer SC register.
If last cycle (sum f -0), input to H613;
set KS44/S45 (swap AQE 1).
V505: E2 to El LSI; 1° to A2 LSI except last cycle,
II to Ql LSI except last cycle. If sum positive: QB = 1, 0881 to E400; left adder to 1°,
right adder to II. If sum negative: QB = 0,
OSSl to E400; Q2 to 10, A2 to II. Input to
H500, H620 and HS20; if last cycle, repeat
divide step; if last cycle, input to HSI0 and
proceed to swap.
313
For a step-by-step analysis of a computer divide,
refer to the arithmetic chapter of this text. The main
items for divide step are:
1. Shift count register - Arithmetic passes 4910 or
618 are necessary for divide step. The quotient
is positioned correctly on the sixty-first pass.
The SC register keeps count of the passes. A count
of 618 says terminate.
2. Quotient bit - The divide step consists primarily of
a series of subtractions and left shifts. With each
subtraction the result is sensed; if it is positive the
quotient bit is a 1. Figure 313 shows how the quotient bit is set during divide step. Translations of
the inputs to 0881 and examples of the cases represented are shown. During divide step a result
of -0 must be treated as a positive result.
E2 to El left 1
E400
E401
474645
474645
1 1X
1 1X
o1X
o1X
(2 47 unlike • 246 gen) = L259 -----I.(sum negative)
(2 47 unlike' 246 unlike' 245 gen)
+
474645
101
III
L245 = carry input to group 15
....---c~--L260 = (divide step)
(adder -:j: -0)
(2 45 unlike . unlike' 247 unlike)
474645
001
011
47464n
o 1 0 Carry input
001
Adder -:j: -0
= L175
Divide step
= 0875
247 stage carry lnput = L147
Divide sum negative
247 unlike = U047
474645
OXX
1X X
Figure 313. Quotient Bit Translations
3. Divide fault - Occurs when the upper 48 bits of the
dividend left shifted 1 is greated than or equal to
the divisor. Two 6 bit examples of divide fault are
shown below.
47464n
1 1 0 Carry input
101
Note: Examination of the actual logic prints (p. 4-11)
shows more inputs to 0887 than are shown here.
These other inputs are for functions other than
D. P. divide and as such are of no consequence
during this discussion.
In double -precision divide the quotient is being
formed in E register. During the last cycle E247
or E246 being set will cause the divide fault FF to
be set. (Logic Diagrams 2-103).
100
01)0100 this quotient could not be expressed in a 6-bit register.
40
10)0040 this quotient could not be expressed in a 6-bit register.
311
Divide sum negative
SWAP
V500: Clear A2, Q2, E2, X2, and Xl; clear K812/813
(last cycle).
V501: El to E2.
V502: Set K846/847 (swap AQE 2); input to H811.
- to I2 ); input to H834.
V503: Al to X2; I2 to Xl (Ql
V504: ClearEl; input to H915.
V505: Einv to El (X2Xl to Einv); clear K844/845
(swap AQE 1); input to H500, H620, andH810.
The arithmetic timing shown above accomplishes the
following:
1. The quotient inEl is transferredtoE2. E2 serves
as a holding register for the quotient while the remainder is transferred to E 1.
2. The remainder in AQ at the end of divide step is
transferred to El during this pass. The transfer
is: Al Ql to X2Xl to Einv to El
V500:
V501:
V502:
V503:
V504:
V505:
Clear A2, Q2, X2, and Xl; input to H821.
Set K548/549 (swap AQE 3); E2 upper to X2.
Clear K846/847 (swap AQE 2).
Input to H814 and H844.
Clear Al and QI; input to H515.
10 to Al (left adder to 10); E 2 lower to Q I; set
K852/853 (complement AQE); input to H500,
H620, and H820.
At V500 time the quotient is in E2. This pass will be
used to place the quotient in Al Q1. The data transfers are:
E2 upper to
X2~
Optional adder to 10 to Al
Q's to Q2---"
E2Iower----------~.~
Ql
COMPLEMENT
V500:
Clear A2 Q2 and E2; clear K848/849 (swapAQE
3); input to H611 and H871.
V501: EI to E2; 12 to A2 (AI to 12); 13 to Q2 (QI to 13)
V502
V503: Input to H864.
Complement quotient
Input to H611 if (unlike
signs) (AQ t- 0).
Complement remainder
Input to H834 if Al original was negative and E I t- O.
V504: Clear K804/805 (optional arith
busy).
Clear Al Ql; input to
H613.
Clear EI; input to H915.
V505: Input to H864.
1° to Al (A2 to 10);
II to Ql (Q2 to II).
E inv to EI (E2 to Einv).
The timing shown above is
used only if it is necessary
to express a negative quotient.
The timing shown above is used only
if it is necessary to express a negative remainder.
V864: Clear K560/561 (arith busy)
At V504 time the clearing of optional
arith busy enable the adder to function
as a 24 -bit adder. Clearing arith busy
allows main control to use the arith metic section again.
FLOATING-POINT MULTIPLY
FMU FP multiplication of AQ
23
18
17 16 15 14
62
a
b
I
I
I
I
a = addressing mode designator .
b = index register designator
m = storage address; M = m + (Bb)
00
m
Instruction Description
Multiply the 48-bit floating-point operand in AQ by
the floating -pOint operand located at storage addresses
M and M + 1. The rounded and normalized product is
displayed in AQ.
Bits 12 -48 of E hold the lower 36 bits of the 72 -bit
unnormalized product. The sign of this residue is the
same as that of the product. See operand formats in
figure 314.
315
12 11
23 22
00
00
23
(Q register)
(A register)
Vr-------------------~/
A
~
t
II-bit biased exponent
36-bit coefficient
sign of the coefficient
+
11-bit biased exponent
A
12V ll
23 '22
1\
00
00\
23
(M + 1)
(M)
12 11
47
I
00
E register
\
I
36-bit residue afte/FP multiply
Figure 314.
Operand Format for Floating-Point Multiply
The f0110wingis a24-bit example of how floating-point
multiplication could be performed by pencil and paper
method. You should become familiar with this example
before proceeding through the detailed timing of the 62
instruction. The original octal numbers are in the
upper right-hand corner of the page. The heavy black
lines define the flow path for the problem. The computer would start with the operands packed in floatingpoint format. The steps from this point are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Obtain positive form of operands.
Toggle bit 22 to obtain real exponents.
Form the sum of the II-bit exponents.
Place the sum of the exponents in a holding register.
Multiply the coefficients
Round the product by adding +1.
Normalize the product.
Adjust the exponent.
Merge the exponent and coefficient.
Toggle the bias bit to form biased exponent.
Complement if a negative product is to be formed.
V502: Clear Q3; input to H943.
V503: Al exponent~Q3; clearF LIS ; set K870/87I
(add exponent 1).
V504: Clear K596/597 (FADR2); set KI04/I05 (start
adith 2); set K850/851 if (M) is negative.
V505: I ~FL15
At V501 time the enables come up to form M + 1. At
V505 time M + 1 is gated to FL15 to be available for
the second ROP. At V503, Al exponent is placed in
the holding register Q3. During the transfer the bias
is toggled to place the real exponent in Q3 if Al is positive or the complement of the real exponent in Q3 if
Al is negative.
0
Phase 2: First Arithmetic Pass
N687: Start arithmetic coincident with V009 time of
the first ROP and V505 time of phase 1; set
K532/533 (unlike signs 1) if sign of A 1= sign of
M; input to H500, H510, and H512.
V500: Clear A2, Q2, Xl; input to HS13 and H53I.
In the lower left-hand corner of the page the original
octal numbers are multiplied and the product is packed
into floating-point format. The answer, 5767.3207,
is the same one the computer would obtain.
DETAILED TIMING
Phase I
N687: Start arithmetic coincident witt"'! V003 time of
fhEt first ROP~ set K536/537 (if ADIt 1); set
K596/597 (FADR 2); input to H500 and H510.
V500: Clear A2 and Xl.
V501: I5~A2, (FLlS~I5); I6-..X1, (+1-+16);
input to H942.
316
V501: I4-'X1 (DB reg:!.ster -'14: if (M) negative);
(DB register---.I4 if (M) positive); I3----+Q2
(A1---.I3) bits 0-11 and bit 23; I86X/87X Q2
bits 12-22 (Q3~186X/87X if (Q3) negative);
(Q3----186X/87X if (Q3) positive);
input to H8 54.
V502: Clear X2; input to H821 and H855.
VSU3: Xl~2 bits U-I1 and bit 23;
181X/82)(--""X2 bits 12-22"(Xl....... I8ix/82X);
set K800/801 (wait word 2); set K872/873
(add exponent 2); input to H834.
V504: Clear E1.
V50S: Clear K870/871; input to H500 and H942.
+44.44 8 Original octal numbers
~£L----- -4.111 8
2066.4444
5774.3666
=2006.4444 = I00; 1.1 4444
= 2003.4111 =
0003 • 4111
1
~ to II-bit adder
0006
0003
100111 Hold
.4444 ____
~
.4111
4444
4444
4444
22220
.22735504
+1~
.2274
Greater than half, so round
~
.0100101111002
This number is not properly normalized.
.1001011110002
Left shift 1; insert sign-bit into lowest bit position.
+
~
• 4570
::~~~
+44.44
-4.111
4444
4444
4444
22220
227.35504 = -227.4
I
Adjust exponent by subtracting the shift count from it .
0010.4570
Merge exponent and coefficient
2010.4570
Toggle bias bit.
5757+3207
Since the original signs were unlike, complement.
•
= 5767.3207
Figure 315.
Pencil and Paper Example of Floating Point Multiplication
Phase 2 consists of two arithmetic passes and has three major functions:
1. (tvI)---.X2 - the detailed transfer path is shown.
DB register
(M)~egative
Bits 12-22
j
-----DB register
l
XI---181X/82X
Xl
Xl-------------~-.·X2
(tvI) positive
Bits 0-11 and 23
317
PHASE 3
/~----------------------------------~~~--------------------------------~
R NI
~ ":AD
ROUND
MULTIPLY
COEFFICIENTS
44aPASSES
1
'NORMALIZE I
I
ADJUSTED I
EXPONET ,
I
,
COMPLEMENT
MERGE
(M)
I
ARITH
I
ARITH
I
f-IL------J~I----9"1
ARITH
ARITH
'----r--....
REMOVE BIAS BIT
COMPL EMENT
AQ I F NECESSARY
ARlTH
I
ARITH
~~~~~~~----~~~----~
:W~HIFT
PHASE I
AI EXP -..Q3
I
I
I
~p
(ALL EXPONENTS)
PHASE 2
}
SUM OF EXPONENTS -+Q3
ExTEND SIGN OF COEFFICIENTS
IN AI AND X2 PREFME TO MULTIPLY
THESE OPERATIONS ARE PERFORMED
ON THE FIRST OPERANDS (A) 8 (M)
WHILE WAITING FOR THE SECOND
OPERAND (M+I) FROM STORAGE
Figure 316. Parallel Timing for 62. X
The transfer of Xl ~ 18lX/82X toggles the bias bit
bit so that bits 12 -22 of X2 hold the real exponent at
V503 time.
2. Add Exponents - The sum of the exponents is
formed by forcing the 48 - bit adder to appear as an
II-bit adder. This is accomplished by setting
K872/873 (add exponent 2) at V503 time which
causes groups 0-11 to appear as passes and not
generates. Figure 317 is a simplified logic diagram of how group 12 of the adder is affected by
the setting of add exponent 2. For the time interval defined by add exponent 2, U800 = 1, and U801
:: O. This insures that all inputs to U746, U747,
and U748 are disabled; while all inputs to U749 are
partially enabled. Therefore group 12 only sense fur
carry inputs from groups 12, 13, 14, and 15. Figure 318 shows the data flow for add exponents.
The operands are presented to the adder at V503
time of this arithmetic pass and sum will be sampled at V501 time of the next arithmetic pass.
U800 (ADO
EXP.I
U300
U301
U302
U303
(2)
2 wili be used to extend the sign of the coefficient
f()r both the multiplier arid multipHcand. ThIs sign
extension will allow the computer to perform the
multiplication of the coefficients in the same manner as the multiply step of double -precision multiply. At V505 time of the first arithmetic pass the
~~~~
~ (31:ts~!
(ADO
U308
I
CI5A
EX~)
D31A
(4)
~;::
U309~
L555
U310
U517 _
U644 B-II(5}U544
U311 _ _
U801 .uece.s s:J,;q: bec.ause. the ilr.;tml. 1
division is a 36-bit divisor into a 72-bit dividend.
Therefore the quotient is 37 -bit. At V505 time of
this pass the lower 37 bits of E1 holds the quotient
and the lower 37 bits of AQI hold the remainder
left shifted 1 place.
32i1
3. Pass 38 - the function of the 3810 pass is to ascertain if a round operation is necessary. A subtract
is performed on this pass and, if the result is positive' K884/885 (round up) will be set at V505 time.
The· result of this subtract will not in any case be
gated into AIQI. Instead A2Q2, which hold the
proper remainder left shifted 1 place, will be right
shifted 1 into AIQl. See figure 326 for an example
of why passes 37 and 38 are needed.
4. Shift count register - SC register was cle ared during
copy F 1 to F2 time of RNI and will be counted up
to keep track of the arithmetic passes for divide
step. At V500 time of pass 45 8 (SC register = 448)
K8I2/813 (divide last cycle) will be set.
5. Termination - occurs after 3810 passes. At V500
Tjmp of P::lR.~ .17 divide last cYc:1e is set but since
SC register = 448 at V502 time divide 1 cannot be
cleared; therefore the enables for divide step remain up. On pass 37 SC register advances to 458'
so at V502 time of pass 38 divide 1 is cleared,
dropping the divide step enables
0
El
Sum
positive
}------- Sum
Q2
A2
E2
A2
El
Ql
X2
Xl
~,~11_ _ _
00......;~3_ _ _ _ _ _
0-JOI
Sign extension
of divisor
Figure 325.
Enables for Divide Step
36-bit
divisor
Swap AQ and E: First Pass
El-+E2
V500:
Quotient to E2,
Al--+X2, X2Xl---..Einv-.E1,
Ql-+12-.Xl.
Remainder to E 1
V501:
V502:
V503:
V504:
V505:
Clear A2, Q2, E2, X2, and Xl,
clear K812/813 (divide last cycle);
input to H871.
El to E2.
Set K846/847 (swap AQE 2):
input to H811.
Al to X2;
12 to Xl (Ql to 12); input to H834.
Clear El; input to H915
X2XI to Einv to El;
clear K844/845 (swap AQE 1);
input to H500, H620, and H810.
Swap AQ and E consists of two arithmetic passes
and is used to place the coefficient of the quotient in
AQ and the remainder in E. The timing shown above
is the first pass of swap AQ and E and it accomplishes
the following:
1. Places the quotient in E2.
2. Places the remainder in E 1.
The data flow for this pass is shown above right.
327
110101.000000
1.
2. Subtract
3. Subtract
000010.000000
1000 10
-0110 10 --~
4. Subtract
000010.000000
100 010
-010 010 _ _..J
5. Subtract
000010.000000
10 0010
-00 0010
Let's look at a 6 - bit example to determine why
passes 37 and 38 are necessary for the 63 instruction.
Since the computer must subtract to divide so must
you. The subtraction is with real signed numbers and
each time the difference is positive the appropriate bit
in the quotient register is set. Seven steps were required to arrive at the correct quotient one step more
than the number of bits. The eighth step was used to
see if the answer should be rounded. After the eighth
step the remainder must be shifted right 1 to bring it
back to its proper value.
6. Subtract
7. Subtract
but want to round so
subtract again.
110100
100010
+010010
8. Subtract
This result is positive
so add' 1 to the quotient
in order to round.
Figure 326. Example of Divide Step
\7800
SCR
Divide 1
Divide
last cycle
K808
K812
K809
K813
f 44
V802
60-63
Figure 327. Terminating Divide Step
328
Swap AQ and E: Second Pass
V500: Clear A2, Q2, X2, and Xl;
input to H821.
V501: E2 upper to X2;
set K848/849 (swap AQE 3);
clear K882/883 (shift right 1).
V502: Clear K846/847 (swap AQE 2).
V503: Input to H814 and H844.
V504: Clear Al and Ql;
input to H515.
V505: 10 to Al (left adder to 10);
E2 lower to Q1;
set K822/823 (round);
input to H500, H620, H810, and H820.
Timing shown completes swap AQ and E by placing
the quotient in AIQ1. Figure 328 is a block diagram
of the transfer paths used.
V502
V503: Input to H612.
V504: Clear Al and Q1;
set K898/899 (short cycle);
input to H613 if sum =f -0.
V505: If sum =f -0:
10 to Al (left adder to 10);
II to Q1 (right adder to II);
set K826/827 (normalize) which removes
constant clear from K880j881 and K886j887.
Input to H500, H600, H620, and H820.
Timing for round occurs whether or not an actual
round operation is to take place. The only possible
case for rounding is plus 1. To accomplish plus 1,
AIQl is transferred to Q2A2 and presented to the
adder. X2Xl is forced to 0-" Oland presented to the
adder. The logic for forcing X2Xl is shown in figure
321. If no rounding is required, X2Xl is cleared and
a 48-bit add of the quotient and all zeros takes place,
which preserves the original quotient. The timing for
all floating-point instructions is common for normalize, adjust exponent, merge, and complement. Go to
page 244 to complete the timing for this instruction.
FLOATING-POINT ADD
FAD Floating-point Addition to AQ
I
23
18
60
17
IaI
16 15 14
b
I
00
m
a = addressing mode designator
b = index designator
m = storage address; M = m + (J3b)
o
o
Q2
A2
Figure 328. Quotient to AQ
0--+0
Xl
Upper
E2
Lower
ROUND
V500: Clear A2, Q2, E2, X2, and Xl;
input to H611.
V501: 12 to A2 (Q1 to 12);
13 to Q2
to 13 ).
X2Xl forced to a +1 if round up is set, otherwise X2Xl = O's. Adder propagation begins.
orr
Instruction Description
Add the 48 -bit combined contents of M and M + 1 to
(AQ). The rounded and normalized sum appears in AQ.
The upper order bits of E hold the portion of the operand that was shifted into E during the equalization of
exponents. Refer to figure 329 for operand format.
The pencil and paper example of figure 330 shows how
the computer performed a floating-point addition. The
original octal numbers are in the upper right-hand corner of the page and the flow for the problem is defined
by the heavy black lines. The computer would start
with the operands packed in floating -point format. The
steps are as follows:
1. Toggle the bias bit to obtain the real exponents.
2. Sent the exponents to an II-bit adder and perform
a subtract. The magnitude of the difference indicates how much the smaller operand must be
right shifted to align the octal points. The sign of
329
48 -bit
474.~--------------------------addendor----------------------------~~00
sum
23
00
12 11
22
00
23
Q register
A register
v,...------J/\'-----~V, - - - - - - - - - - - - - ' ,
\
Sign)
11-bit exponent
of
coefficient
')
23
/
~
__-JA____
36 -bit coefficient
~
~
\1
12 11
22
__________________
00
~A~--------------------------
____
23
~\
00
(M)
(M
+ 1)
48-bit
474.~--------------------------augend --------------------------~.~OO
__________________________________
residue
r -__________________________________
~A~
~7
I
~~
00'
E register
I
Figure 329. Operand Format for Round
3.
4.
5.
6.
330
the difference indicates which operand is smaller.
The exponent of the larger operand will be retained
to form the result of the floating-point addition.
Extend the sign of the coefficients.
Shift the coefficient of the smaller number right to
align the octal points. The bits shifted off are retained so that they may be used to determine if a
round is necessary. These bits form the residue.
Perform the addition of coefficients.
Round. The residue is inspected for the round under the following rules:
a. If the operand shifted right was negative and the
highest order bit of the residue is a zero, add
-1 to round. This operation is referred to as
round down.
b. If the operand shifted right was positive and the
highest order bit of the residue is a 1, add +1
to round. This operation is referred to as round
up.
c. In any other case add all O's to round.
d. Round down (-1) is the same as round up except
it deals with negative numbers. Adding a -1 to
a negaiive nurnber and cornpiementing is the
same as complementing first and then adding a
+1.
7. Normalize is not necessary for this example.
8. Adjust exponent is not necessary since normalize
did not take place.
9. Merge the exponent and coefficient.
10. Toggle the bias bit.
In the lower left-hand corner of figure 330 the original octal numbers are added and the sum is packed
in floating-point format. Note that this is the same
answer arrived at by using the computer method.
Parallel timing for the instruction is shown in figure
331.
DETAILED TIMING
Phase 1
N687: Start arithmetic coincident with V003 time of
first ROP;
set K536/537 (FADR 1);
set K596/597 (FADR 2);
input to H500 and H510.
V500: Clear A2 and Xl.
V501: 15 -+A2 WLlS---"l;»);
I6"' X1 (+1 -+1 6);
input to H9420
-44.44 Original
- 7.645 octal numbers
Pack
1777110
~3331
7774. 132
I
to II-bit/
0006/
Hold
3774
0002
177711
7777.3333
oo~~
/00132
This indicates a
right shift of 3 to
equal exponents
}xtend sign
7777.3333
7777.7013(2)
0
Right shift 3
/
Residue
7777.3333
7777.7013
7777 2346
+1
7777.2347
Add coefficients
7777.2347
-1
7777.2346
Round dmvn
111111111II.01~10
777 1
023(
+
5771.2346
- 44.44
- 7.645
-54.305
= -54.31 = 5771.2346
Figure 330.
Note that this number is properly normalized,
therefore normalize and adjust exponent are
not necessary.
Merge
Toggle Bias bit
Note that these answers are equal.
Pencil and Paper Example of Floating Point Addition
V502:
Clear Q3;
input to H943.
V503: Al exponent--'Q3;
clear FLI5;
set K870/871 (add exponent 1).
V504: Clear K596/597 (FADR 2);
set K104/I05 (start arithmetic 2).
V505: IO~FLI5.
At V501 time the enables come up to form M + 1.
At V505 time M + 1 isgatedtoFL15so that it is available for the second ROP. At V503 time Al exponent is
placed in t~e holding register Q3. During the transfer
the bias bit is toggled, which places the real exponent
in Q3 if Al is positive or the complement of the real
exponent in Q3 if Al is negative.
Phase 2: First Arithmetic Pass
N659: Start arithmetic coincident with V009 of the
second ROP and with V505 of phase l;
input to H500, H510, and H512.
V500: Clear A2, Q2, and Xl;
input to H513 and H531.
V501: 14~Xl (I5I3R--.I4);
13~Q2 orr--'I3) bits 0-11 and 23;
186X/87X~ Q2 bits 12-22 (Q3-+186X/87X if
(Q3) negative); (Q3~I86X/87X if (Q3) positive); input to H854.
331
,~
____________________________
I
,
EQUALIZE
I EXPONENTS I
I
ROP
RN~
READ
I
\
(M+I)
PHASE I
AI EXP. ---...Q3
REMOVE BIAS BIT
FORMM+I
ADD
COEFF.
ROUND
I
PHASE 3
~A~
__________________________
I NORMALIZE
I
ADJ. EXP.
I
MERGE
ICOMPLEMENT
I
I
I
XI
SUBTRACT EXPONENTS
WHICH IS LARGER AND
ALSO THE NUMBER OF
SHIFTS REQUIRED TO
EQUALIZE
Figure 331. Parallel Timing for 60. X
PHASE
2
LARGER EXP. ~ Q3
EXTEND SIGN OF COEFFICIENT
IN AI AND X2
DIFFERENCE OF EXPONENTS SCR
VS02:
Clear X2;
input to H821 and H8SS.
VS03: Xl~X2, bits 0-11 and 23;
181X/82X~X2, bits 12-22 (Xl~181X/82Xif
(Xl) positive);
(Xl ......181/82X if (Xl) negative);
set K800/801 (wait word 2);
set K872/873 (add exp 2); enable II-bit adder;
input to H834.
VS04: Clear El.
VSOS: Clear K870/871 (add exponent 1);
input to HSOO and H942.
Phase 2 consists of two arithmetic passes and has six
functions listed as follows:
1. (M)-+X2 - The detailed transfer path is:
bits 12 -22
XI-181X/82X~
DBR--+Xl
Xl
-
.X2
BUsO-ll and 23
The transfer of Xl--.I81X/82X toggles the bias bit
so that bits 12 -22 of X2 hold the real exponent at
VS03 time.
332
~,
2. Difference of exponents to SC register - The difference of the exponents is formed by forcing the
48 -bit adder to appear as an II-bit adder. This
is accomplished by setting K872/873 (add exponent
2) at VS03 time, which causes groups 0-11 to appear as passes and not generates. Figure 332 is a
simplified logic diagram of how group 12 of the adder is affected by the setting of add exponent 2. For
the time interval defined by add exponent 2, U800
= 1 and U801 = O. This insures that all inputs to
U746, 747, and 748 are disabled while all inputs to
U749 are partially enabled. Therefore, group 12
only senses for carry inputs from groups 12, 13,
14, and 15. Figure 333 shows the data flow for subtract exponents. The operands are presented to the
adder at VS03 time of the first arithmetic pass of
phase 2 and m:mr is sampled at VSOI time of the
second arithmetic pass of phase 2. At VS03 time
of the second arithmetic pass the complement of
the required number of shifts is placed in SC register so that the octal points can be aligned before
the addition of coefficients. If the difference between exponents is greater than 778 , 1873 (Logic
Q~~~~~, page 4-25) will block t_he. tran.:~fe!.... of
Q3~SCreglster . Tfiend6re, 7'7 gshifts take place
and the final answer will be the larger operand.
3. Larger Exponent to Q3 - At VS05 time of the sec0nd arithmetic pass of phase 2 one of the following
will occur:
.. a. If the sum of subtract exponents was positive,
Al exponent is the larger exponent. Therefore
Al exponent is gated to Q3 so that it will be
available for adjust exponent. If (AI) is positive' the real exponent is placed in Q3; if (AI)
is negative, the complement of the real exponent is placed in Q3.
b. If the sum of subtract exponents was negative,
M exponent is the larger exponent. The complement of M exponent is in X2 from subtract exponents. Therefore, gating X2 to Q3 places the
M exponent in Q3 so it will be available for adjust exponent. The real exponent is placed in
Q3.
U800 (ADD
EXP.)
U300
U301
U302
U303
U304
U305
U306
U307
5. Larger Number to Xl - If the sum of subtract exponents was positive (M, M + 1) is smaller than
(AQ) and must be right shifted to align the octal
points. Since only AQE have shift capabilities (M,
M + 1) must be placed in AQ as in item 4. In order
to make room for this transfer (AQ) must be placed
in X2Xl. During phase 2 (A) is transferred to Xl
and then Xl is transferred sign extended into X2.
The transfer path for Al to X2 is:
The exchange of (AQ) and (M, M + 1) will be completed during the first arithmetic pass of phase 3.
6. Extend sign - At V505 time of the second arithmetic
pass of phase 2 the operands are positioned with
the upper 24 bits of the larger operand in Xl and
the upper 24 bits of the smaller operand in Q2. The
enables for extend sign are:
Lower 12 bits
Q2 -+
U308
U309
U'310
U511
U311 _ _
U801 (ADO EXP.)
(6)
~~~~
(7)
~~
Lower 12 bits
1°---. Al
Upper 12 bits
Upper 12 bits
i
(II) L411
NOthing_I8lX/ 82
Nothing .... I O i A l
(8) L558
X2
(9) L559
!lO)L560~
(Q2) negative
(Xl) negative
tlZ)l562
U643
L563
(13) U643
'872
I
E!8A
U749
( 14)~~:j
(15)
~:~53
-t--CARRY I.NPUT
D I 08
Nothing (zeros) into the inverter ranks 10 and 18
equals all l's out. If a positive sign extension (O's)
is required, the gates 10 ----.A1 and 18~X2 are
simply not enabled.
0408
\:bDJ~ ~X:P.~ ::~~ ~ADD
EXPONENTS
Figure 332. Enabling the II-Bit Adder
Sum
positive -------t"\
Q3
Sum
0------negative
Q3
4. Smaller number to Al = If the sum of subtract exponentwas positive, (M, M + 1) is smaller than (AQ)
and must be right shifted to align the octal points.
Since only AQE have shift capabilities (M, M + 1)
must be placed in AQ and (AQ) will be placed in
X2Xl. It is important to note that during subtract
exponents the standard adder is functioning as a 24bit adder. The enables for placing (M) in Al are:
Right adder~ 13 -'Q2;
The exchange of (AQ) and (M, M + 1) will be completed during the first arithmetic pass of phase 3.
Figure 333. Data Flow for Subtract Exponents
333
Phase 2: Second Arithmetic Pass
If sum of subtract
exponent positive
A exponent > M exponent
V500: Clear Q3;
input to H943
V501: Left adder~3 (extend bit 10);
set K874/875 (extend sign);
input to H944.
V502: Clear SC register;
clear K872/873 (add exponent 2);
input to H945.
V503: I86X/87X--'SC register;
set K814/815 (equalize exponent);
clear K532/533 (unlike signs 1);
input to H942.
V504: Clear Q3;
input to H943.
V505: Input to H844 and H854.
If sum of subtract
exponent negative
M exponent > A exponent
Set K818/819 (swap Al
and X2); input to H620.
Clear A2 and Q2;
input to H513.
~3~I86X/87X;
Q3-+I86X/87X.
I -+-Q2 (right adder.... I3);
input to H8IO.
Clear X2 and Xl;
input to H511.
I2--11--XI (Al-+I2);
AI-+- Q3.
X2-+Q3.
V844, V854: Clear Al and X2;
input to H555 and H855;
if Xl negative, input to H821.
V515, V855: IO-'Al, bits 0-11 (Q2-'IO);
if Q2 negative, I0--'A1, bits 12-23
(nothing to 10);
X1~X2, bits 0-11 and 23;
if Xl negative, I81X/82X --'X2, bits 12 -23
(nothing to I81X/82X); set K820/821)
(swap QI and Xl); set K800/802 (wait word 2).
Phase 3
N687: Start arithmetic coincident with VOO9 of
second ROP;
input to H500, H510, and H512;
clear K818/819 (swap Al and X2).
V500: Clear A2, Q2, and Xl;
set K560/561 (arithmetic busy);
input to H531. Clear K874/875.
V501: 14~XI (DBR-"14);
set K802/803 (word 2);
set K898/899 (short cycle).
V502: Set K802/S03 (word 2);
set K898/899 (short cycle).
V503:
V504: Set K804/805 (optional arithmetic busy);
transfer 1 's count;
transfer lOs count.
V505: Set K814/815 (equalize exponent);
clear K820/821 (swap QI and Xl);
input to H500, H600, H620, and H820.
The preceding aritilmetlc timing places(ivi + i) ill
Xl at V501 time. At V504 time the shift count register is equalized so that it will count properly during
equalize exponents. Remember that the complement
of the required number of shifts was placed in rank I
334
If A exponent>M exponent
Input to H513.
I3~ Q2 (QI ~ 13);
input to H524.
Clear QI;
input to H555.
II-+Al (XI-+Xl);
input to H810.
Clear Xl;
input to H531.
The preceding enables occur only if Al exponent ~ M
exponent which required that (M, M + 1) be placed in
AQ to allow shifting. During phase 2 (AI) was placed
of SC register during phase 2. The setting of optional
arithmetic busy at V504 time enables the 48 - bit adder.
The setting of K560/561 atV500time insures that main
control cannot get into the arithmetic section until the
execution of this instruction is complete.
Phase 2: Egualize Exponents
V500: Clear A2, Q2, and E2;
clear K800/80l (wait word 2);
V503: Clear K802/803 (word 2).
in X2 and (Nl) was placed in AI.
(Nl + 1) in Ql and (Ql) in X2.
This timing places
V600: If SC register ::f 7X, input to H523, H561, and
H881;
if SC register = 7X, input to HS13; HSSl; and
H871.
V601: Input to H514, H524, and H834;
if SC Register ::f 7X:
I2-'A2, right shift 10 (A1---'I2);
r 3- . Q2, right shift 10 (Ql-.r 3 );
El---.E2, right shift 10;
advance lOs count.
If SC register = 7X:
r 2--'A2 (A1-+ 12);
r3--. Q2 (Q1-" 13);
El~E2.
V602:
V504
V505:
Input to H500, H600, H620, and H820;
if SC register ::f 77, repeat shift cycle;
if SC register = 77, set K816/817
(add/subtract coefficient);
clear K898/899 (short cycle).
The preceding arithmetic timing is a short cycle
(4 ~ times) since K898/899 (short cycle) was set at
V501 time of the previous arithmetic pass.
Clear AI, Q1, and E1; transfer lOTs count;
If SC register ::f X7, input to H525, H565,
and H895;
If SC register = X7, input to H515, H555,
and H885.
V603: If SC register :f X7:
_
r0-'A1, right shift 1 (A1--' 10);
11-.. Q1, right shift 1 (Q2 ..... II);
E2-' E1, right shift 1, advance l's count.
If SC register = X7:
r0-.,A1 (A1---.r O);
r1~Q1 (Q2-.r 1);
E2-+El.
The preceding timing is from the shift timing chain.
At the completion of equalize exponents the coefficient
of the smaller operand will be positioned in AQE sign
extended. That portion of the operand contained in E
is called residue and will be used to determine if a
round operation is necessary. If the difference of exponents is > 36 10' AQ will contain only the sign exten sion.
Phase 3: Add Coefficients
V500: Clear A2, Q2, E2;
clear K814/815 (equalize exponents);
input to H6l1.
V501: I2~A2 (Ql~ 12);
I3~ Q2 (AI-+- 13 );
set K884/885 (round up) if A223 = 0 (A is
positive) and E247 = 1.
V502: Set K890/89l (round down) if A223 = 1 (A is
negative) and E247 = o.
V503: Input to H612.
V504: Clear Al and Q1;
,
input to H6l3.
335
V505:
10~AI (left adder~O).
II-'QI (right adder-.l i );
set K822/823 (round);
input to H500, H620, and H810;
input H510 if round down.
QI
Al
During this arithmetic pass the coefficients are
added. Figure 334 shows the data flow for add coefficients. During this pass the enables for round are
determined by the setting or not setting, round up or
round down. If the residue is > one-half, around is
necessary.
Coefficient of
smaller operand
Figure 334.
Phase 3: Round
V500: Clear A2, Q2, Xl, and X2;
clear K816/817 (add/ subtract coe fficient);
input to H611.
V501: 12 ~A2 (QI-+-12);
13-+ Q2 (AI-..I3);
input to H944.
V502: Clear SC register.
V503: Input to H612.
V504: Clear Al and QI;
set K898/899 (short cycle);
if sum = -0, input to H613.
V505: If sum ., -0:
IO~AI (left adder . . . IO);
II-+-QI (right adder~II);
set K826/827 (normalize);
remove clear from K880/881 and K886/887;
input to H500,· H600, H620, and H820.
The timing for round occurs whether or not an adjJ~Btmcnt O,f
the coc.fUcic.nt
mu~ct
be made .... .Rmu),d can
be +1 or -1 for the 60 instruction. For a +1 operation
the sum of the coefficients is placed in Q2A2, X2X1 is
forced to 0-'01, and a 48-bit add is performed. For
a -1 operation the sum of the coefficients is placed in
Q2A2, X2X1 is forced to 7--..76, and a 48-bit add is
Coefficient of
larger operand
Enables for Add Coefficients
If round down,
input to H531 and H821.
14-..XI (nothing to 14);
1400-.XOOO block by round down;
18IX/82X-+X2 Upper (nothing~18IX/82X);
set X2 lower. (A -1 is thus forced into X2Xl. )
If round up.
A +1 is forced to X2Xl.
In both cases above, adder propagation occurs;
is gated to l°ll.
WID
performed. If neither a +1 nor a -1 is required, X2X1
is t;?leareq prior. to the 48-hit ::lnn ::lnn thp nrigin::ll Rllm
is preserved. The timing for all floating-point instructions is common for normalize, adjust exponent,
merge, and complement. Go to page 244 to complete
the timing for this instruction.
F LOATING-POINT SUBTRACTION
FSB Floating -point
Subtraction
From AQ
,.:;;2~3~--:1:.;;8~1:..;.7~1...;;.6--:1:.;;5;....,..;1;;..;4;....-__0.;..0.;.,
6_1_...&I_a...&I__b_--'-__!11_--_---J1
L - I_ _
a = addressing mode designator
b = index register de signator
c = storage address; M = m + (IP)
48-bit
minuend or
difference
47~
23
22
Instruction Description
Subtract the 48 -bit floating-point operand located at
storage addresses M and M + 1 from the floating -point
operand in AQ. The rounded and normalized difference
is displayed in AQ.
The upper order bits of E hold the portion of the
operand that was shifted into E during the equalization
of exponents. Refer to figure 335 for operand format.
12 11
00
-00
23
00
A register
Q re8:ister
~\
I
v
II-bit exponent
36 -bit coefficient
sign of coefficient
I 11 -bit ~xpone~t
(M)
23
47~
47~
22
12 11
(M + 1)
00
23
00
48 -bit
subtrahend
.. 00
residue
- 00
E register
Figure 335. Operand Format for Floating Point Subtraction
The pencil and paper exam pIe, figure 336 shows how
the computer performs a floating-point subtraction.
The original octal numbers are in the upper right corner of the page and the flow for the problem is defined
by the heavy black lines. The computer would start
with the operands packed in floating -point format. The
steps are as follows:
1. Obtain the complement of the subtrahend.
2. Toggle the bias bit to obtain the real exponents.
3. Send the exponents to an II-bit adder, subtracting the exponent of the subtrahend from the exponent of the minuend. The magnitude of the difference indicates how much the smaller operand must
be right shifted to align the octal points. The sign
of the difference indicates which operand is smaller. The exponent of the larger operand will be
retained to form the result of the floating- point
subtraction.
4. Extend the sign of the coefficients.
5. Shift the smaller coefficient right to align the octal
points. Note that the bits shifted off are retained
so that they may be used to determine if a round
is necessary. These bits form the residue.
6. Perform the subtraction.
7. The residue is inspected for the round under the
following rules:
a. If the operand shifted right was negative and
the highest order bit of the residue is 0, add
-1 to round.
b. If the operand shifted right was positive and
the highest order bit of the residue is 1, add
+1 to round.
c. In any other case add all O's to round.
8. Normalize; a left shift of 1 is required for this
ex~ple.
9. Adjust exponent by subtracting 1 since the shift
was left to normalize.
10. Merge the exponent and coefficient.
11. Toggle the bias bit.
In the lower left-hand corner the original octal numbers are subtracted and the difference is packed in
floating-point format. Note that this is the same answer arrived at by using the computer method.
337
+44.44 Original
+5.325 octal numbers
2006.4444 ; 2006.4444 ;
2003.5325 = 5774.2452
0\44441
7774· 2452
To II-bit
l
E)tend
Sign
~adder
)
0006
3774
0002
+1
0003
Hold 100061
0000.4444
7777.2452
/do
)
Th IS III lcates a
right shift of 3
to equalize
exponents
O
0000 .4444
7777 .7245 (2) Right shift 3
/
0000.4444
7777 .7245
0000 3711
+1
0000.3712
OOOO~3712
'\
Residue
Subtract coeffic ients
by adding
Round down
-1
0000.3711
~
000000000000.011111001001
I
000000000000011:110010010
Note that this number is not
properly normalized
Normalize
Adjust exponent
0006
44.440
Subtract 5.325
37.113
Merge
2005~7622
Toggle bias bit
~
2005.7622
Figure 336.
338
0005.7622
Note that these
answer s are equal
Pencil and Paper Example of Floating Point Subtraction
PHASE 3
/~
____________________________
I
I
I
EQUALIZE
SUBTRACT I
I EXPONENTS I COEFF.
I
ROP
RN~
READ
I
ROUND
--JA~
__________
I NORMALIZE
~
_______________\
ADJ. EXP.
I
MERGE
ICOMPLEMENT
I
I
I
I
\
I
\...----v~---'
b
l
~
:lc=Ji
(M+1l
PHASE I
AI EXP. -..Q3
REMOVE BIAS BIT
FORM M+ I
il
SHIFT
i
I~I
I
I
XI
SUBTRACT EXPONENT TO
DETERMINE WHICH IS
LARGER. ALSO HOW MANY
SHIFTS NECESSARY TO
EQUALIZE.
PHASE
2
LARGER EXP. ~ Q3
EXTEND SIGN OF COEFFICIENT
IN AI AND X2
DIFFERENCE OF EXPONENTS SC R
Figure 337.
Parallel Timing for 61. X
DETAILED T1M]NG
Phase 1
N687: Start arithmetic coincident with V003 time of
first Rap;
set KS36/S37 (FADR 1);
set KS96/S97 (FADR 2);
input to HSOO and HS10.
VSOO: Clear A2 and Xl.
VS01: IS-'A2 (!:.L1S--'1S);
16-'X1 (+1-+16 );
input to H942.
VS02: Clear Q3;
input to H943.
VS03: Al exponent-+Q3;
clear FL1S;
set K870/871 (add exponent 1).
VS04: Clear KS96/597 (FADR 2);
set K104/105 (start arithmetic 2);
set K850/851 (nB~14 enable).
VS05: 10~ F LIS (sum --.rO) .
At V501 time the enables come up to form M + 1.
AtV505 timeM + lis gated to FLl5 so thatitis available for the second Rap. At V503 time Al exponent
is placed in the holding register Q3 During the transfer the bias bit is toggled, which places the real exponent in Q3 if Al is positive or the complement of the
real exponent in Q3 if Al is negative.
0
Phase 2: First Arithmetic Pas s
N687: Start arithmetic coincident with V009 of the
second Rap and with V505 of phase 1;
input to H500, H510, and H512.
V500: Clear A2, Q2, and Xl;
input to HS13 and HS31.
V501: I~X1 (DBR-+14);
r3-'Q2 (A1-+13), bits 0-11 and 23;
186X/87X---"Q2, bits 12-23 (Q3---..186X/87X
if (Q3) is negative);
(Q3-.186X/87X if (Q3) positive);
input to H8 54.
VS02: Clear X2;
input to H821 and H855.
V503: X1-" X2 , bits 0-11 and 23;
181X/82X-..X2, bits 12-22
(X1~I81X/82X if (Xl) positive);
(Xl-'I81X/82X if (Xl) negative);
set K800/801 (wait word 2);
set K872/873 (add exponent 2);
input to H834.
V504: Clear El.
V505: Clear K870/871 (add exponent 1);
input to H500 and H942
0
Phase 2 consists of two arithmetic passes and has
six functions listed as follows:
339
1. (M)--.X2 - The detailed transfer path is shown
below.
time of the second arithmetic pass of phase 2 At
V503 time of the second arithmetic pass the complement of the required number of shifts is placed
in SC register so thatthll octal points canbe aligned
before the subtract step. If the difference between
exponents is greater than 778, 1873 (Logic Diagrams, page 4-25 will block the transfer of Q3
SC register Therefore, 778 shifts take place and
the final answer will be the larger operand.
3. Larger Exponent to Q3 - At V505 time of the second arithmetic pass of phase 2 one of the following
will occur:
a. If the sum of subtract exponents was positive,
Al exponent is the larger exponent. Therefore,
Al exponent is gated to Q3 so that it will be available for adjust exponent. Note that if (AI) is
positive, the real exponent is placed in Q3; if
(Al)is negative, the complement of the real exponent is placed in Q3.
b. If the sum of subtract exponents was negative,
M exponent is the larger exponent. The complement of M exponent is in X2 from subtract exponents. Therefore, gating X2 to Q3 places M
exponent in Q3 so that it will be available for
adjust exponent. Note that the real exponent is
placed in Q3.
4. Smaller number to Al - If the sum of subtract exponents was positive (M, M + 1) is smaller than
(AQ) and must be right shifted to align the octal
points. Since only AQE have shift capabilities (Ml ,
M + 1) must be placed in AQ and (AQ) will be placed
in X2Xl. It is important to note that during sub0
Bits 12-22
DBR---.XI
::
/
181X 82Xj
•
0
Bits 0-11 and 23
The transfer of Xl-.I81X/82X toggles the bias
so that bits 12-22 of X2 hold the real exponent at
V503 time.
2. Difference of Exponent to SC Register - The differ ence of the exponents is formed by forcing the 48bit adder to appear as an II-bit adder. This is
accomplished by setting K872/873 (add exponent 2)
at V503 time which effectively causes groups 0-11
to appear as passes and not generates. Figure 338·
is a simplified logic diagram of how group 12 of the
adder is affected by the setting of add exponent 2.
For the time interval defined by add exponent 2,
U800 = 1 and U801 = O. This insures that all inputs
to U746, U747, and U748 are disabled, while all
inputs to U749 are partially enabled. Therefore,
group 12 only senses for carry inputs from groups
12, 13, 14,. and 15. Figure 339 shows the data flow
for subtract exponents. The operands are presented to the adder at V503 time of the first arithmetic pass of phase 2 and Siii1:1 is sampled at V501
UBOO \ADD
EXP.l
U300
U301
U302
U503
Rank 1
U304
U305
U306
U307
U3ee
U309
U310
U311
Sum
J..------negative
Sum
positive
U5'71---~
ueol ",.00 EXP.)
(6)
~:!~
m~~
(11) L411
\8 )L558
19~
ADO EXP 2
K872
L559
(lO)L560
133
(2)
~;~§
(13)
~~:;
(l4)~~~
(15)
~:~53
-t--t;AftI'Cl
FROM
\'tbJ"
0108
.1.fIIIl"UI
GROUP
D40B
~X:ri.\ ::~~ ~A=0"-0[-XP-ON=EN=T!
Figure 338. Enabling the II-bit Adder
340
J
22
I M exponent
X2
12
_22 .1
12
I I Al exponent
Q2
Figure 339. Enables for Difference of Exponents to SCR
tract exponents the standard adder is functioning as
a 24 -bit adder. The enables for placing (M) in Al
are:
Right adder ..... 13 .....Q2
6. Extend Sign - At V505 time of the secondarithmetic pass of phase 2 the operands are positioned with
the upper 24 bits of the larger operand in Xl and
the upper 24 bits of the smaller operand in Q2. The
enables for extend sign are:
Lower 12 bits
Q2-..I°---'AI
Q2--' I°--..AI
The exchange of (AQ) and (tvI, M + 1) will be completed during the first arith pass of phase 3.
5. Larger Number to Xl - If the sum of subtract exponents was positive, (M, M + 1) is smaller than
(AQ) and must be right shifted to align the octal
points. Since only AQE have shift capabilities (M,
M + 1) must be placed in AQ (as in item 4).
In
order to make room for this transfer (AQ) must
be placed in X2XI. During phase 2 (A) is transferred to Xl and then will be transferred sign extended into X2. The transfer path for Al to Xl is:
Upper 12 bits
Nothing_lOll
(Q2) negative
Lower 12 bits
X1--'X2
Upper 12 bits
Nothing_ 18IX/82XYX2
The exchange of (AQ) and (M, M + 1) will be completed during the first arithmetic pass of phase 3.
(Xl) negative
Phase 2: Second Arithmetic Pass
If sum of subtract exponent
positive, A exponent > M
exponent
V500: Clear Q3;
input to H943.
V501: Left adder ...... Q3 (extend bit 10);
set K874/875 (extend sign);
input to H944.
V502: Clear SC register;
clear K872/873 (add exponent 2);
input to H945.
V503: I86X/87X....... SC register;
set K814/815 (equalize exponent);
clear K532/533 (unlike signs 1);
input to H942.
V504: Clear Q3;
input to H943.
V505: Input to H844 and H854.
If sum of subtract exponent negative, M
exponent> A exponent.
Set K818/819 (swap Al and
X2); input to H620.
Clear A2 and Q2;
input to H513.
Q3~86X/87X;
Q3-+ I86X/87X
I3-+Q2 (right adder 13);
input to H810.
\
Clear X2 and Xl;
Input to H511;
I2 .....X1, (A1 .......I2 );
A1....... Q3.
X2-+Q~
V844, V854: Clear Al and X2;
input to H555 and H855;
if Xl negative, input to H821.
V515, V855: IG--'A1, bits 0-11 (Q2-+ 10);
if Q2 negative, IO~A1, bits 12-23
(nothing to 10); X1--"X2, bits 0-11
and 23; if Xl negative, I81X/82X-..X2,
bits 12-22 (nothing to 181X/82X); set K820/82l
(swap Ql and Xl); set K800/80l (wait word 2).
341
Phase 3: Initialize
N687: Start arithmetic coincident with V009 of sec0nd ROP;
input H500, H510, and H512.
clear K818/819 (swap Al and X2).
V500: Clear A2, Q2, and Xl; clear K874/875;
input to H531;
set K560/561 (arithmetic busy).
V501: I4--..Xl (DBR to 14);
set K802/803 (word 2)
set K898/899 (short cycle);
clear K850/851 (bus--..I4 enabl~).
V502: Set K802/803 (word 2); set K898/899 (short
cycle); clear K850/851 (DBR -.14 enable).
V503:
V504: Set K804/805 (optional arithmetic busy);
transfer 1 's count;
transfer lOs count.
V505: Set K814/815 (equalize exponent);
clear K820/821 (swap Ql and Xl);
input to H500, H600, H620, and H820.
The preceding arithmetic timing places (M + 1) in
Xl at V501 time. At V504 time the shift count register
is equalized so that it will count properly during equalize exponents. Remember that the complement of the
required number of shifts was placed in rank 1 of the
SC register during phase 2. Setting of optional arith metic busy at V504 time enables the 48 - bit adder.
Setting of K560/561 at V500 time excludes main control from the arithmetic section until execution of this
instruction is complete.
Phase 3: Equalize Exponents
V500: Clear A2, Q2, and E2;
Clear K800/801 (wait word 2).
V503:
V504
312
Clear K802/803 (word 2).
If A exponent >M exponent,
Input to H513.
13--.. Q2 (01-+1 3 );
Input to H524.
Clear Ql; input to H555.
Il--.Ql (X1--+ II); input to H810.
Clear Xl;
input to H531.
The enables shown above occur only if A exponent
> M exponent which required that (M, M + 1) be placed
inAQ to allow shifting. During phase 2 (AI) was placed
in X2 and (M) was placed in AI. This timing places
(M + 1) in Ql and (Ql) in X2.
V600: If SC register "f 7X, input to H523, H561, and
H881; if SC register = 7X, input to H513,
H551, and H871.
V601: Input to H514, H524, and H834;
if SC register "f 7X:
I2~ A2, right shift 10 (AI --+-12 ),
13 .... Q2, right shift 10 (Ql ......I3),
El "'E2, right shift 10;
advance 1 Os count.
If SC register = 7X:
I2~A2 (Al-a.-I2),
!3~Q2 (Ql ..... 13 ),
El-tr-E2.
V602: Clear AI, Ql, and El; transfer 10's count.
if SC register "f X7, input to H525, H565,
and H89S.
If SC register::: X7, input to H51S, H5S5,
and H88S.
V505: Input H500, H600, H620, and H820;
if SC register t: 77, repeat shift cycle;
if SC register = 77, setK816/817 (add/subtract
coefficient); clear K898/899 (short cycle).
V603: If SC register t: X7:
IO~A1, right 1 (A2~0),
11-. Q1, right 1 (Q2-+I 1),
E2~E1, right l~ advance l's count.
If SC register = X7:
IO~ Al (A1-+IO),
I1~Q1 (Q2-+-I1),
E2-+E1.
The preceding arithmetic timing is a short cycle
(4 0 times), as K898/899 (short cycle) was set at V501
time of the previous arithmetic pass.
The preceding timing is from the shift timing chain.
At the completion of equalize exponents the coefficient
of the smaller operand will be positioned in AQE sign
extended. That portion of the operand contained in E
is called residue and will be used to determine if a
round operation is necessary. If the difference of
exponents is >36 10, AQ will contain only the sign ex tension.
Phase 3: Subtract Coefficients
V500: Clear A2, Q2, E2;
clear K814/815 (equalize exponents);
input to H611
V501: I2-"A2 (Ql-' 12);
I3-'Q2 (Al"'I3);
set K884/885 (round up) if A223 = 0 (A regis47 ter positive) and E2
= l.
V502: Set K890/891 (round down) if A223 = 1 (A is
negative) and E247 = 0.
V503: Input to H612.
V504: Clear A1Ql;
input to H613.
V505: IO~A1 (left adder'" 10);
II...... Q1 (right adder--.I1);
set K822/823 (round); input to H500, H620,
and H810; input to H510 if round down.
0
During this arithmetic pass the coefficients are subtracted. Remember that, in order to subtract, the
subtrahend must be complemented and addition performed. The complement of the subtrahend was obtained by setting K850/851 (DB~I4 enable) at V504
time of phase 1. This insures that (NI, M + 1) is complemented as it is transferred into the arithmetic section. See figure 340 for data flow during subtract coefficients. During this pass the enables for round are
determined by the setting or not setting of round up or
round down. If the residue is > 1/2, a round is necessary.
Remember: round up forces a +1 to X2X1 and round
down forces a -1 to X2Xl. The adder
propagates in both cases before transferring sum -+10.
Al
A2
Figure 340.
Enables for Subtract Coefficients
Coefficient of
smaller operand
X2
Xl
Coefficient of
larger operand
343
Phase 3: Round
V500: Clear A2, Q2, Xl, and X2;
clear K816/817 (addition/subtraction
coefficient); input to H611.
V501: r2~A2 (Ql-'r2 );
r3 -"Q2 (Al-.r3 );
input to H944.
V502: Clear SC register.
V503: Input to H612.
V504: Clear Al and Ql;
set K898/899 (short cycle);
if sum :f -0, input to H613.
V505: If sum :f -0:
I0--"Al (left adder--'IO);
Il--"Ql (right adder ... r 1);
set K826/827 (normalize);
remove clear from K880/881 and K886/887;
input to H500, H600, H620, and H820.
The timing for round occurs whether or not an adjustment of the coefficient must be made. Round can
be +1 or -1 for the 61 instruction. For a +1 operation
the difference of the coefficients is placed in Q2A2;
X2X1 is forced to 0--'01, and a 48-bit add is performed. For a -1 operation the difference is placed
in Q2A2, X2Xl is forced to 7--'76, and a 48-bit add
Phase 3. Common Timing: Normalize
Set short cycle FF for normalize.
V500: Clear A2 and Q2.
V503: If K886/887 (left lOs shift enabled) is clear and
Ao4-l5 is alII's or all O's,
set K880/88l (left shift lOs);
if K880/881 (left lOs shift enabled)
is clear and All = AI2,
set K888/889 (shift 1 's);
if K886/887 (left lOs shift enabled) is set
and Q20-23 andAOO-05 is all I's or all D's,
clear K880/881 (shift left lOs);
if A 12 t: A13, set K882/883 (shift right 1)
and set K888/889 (shift l's);
if A 10-13 is all l's or all O's,
set K878/879 (normalize complete);
If (AQ) = 0, set K878/879 (normalize complete);
transfer I's count.
Y504' Porcc tnn13fcr 'K88()/~B 1 tn K~Rn/~P.7.
If round down,
input to H531 and H821.
I4---'XI (nothing~4), I400-'XOOO blocked by round
down, 181X/82X-"X2 upper (nothing--.I8IX/82X);
set X2 lower. This equals a -1 in X2X1.
If round up.
Force X2X1 to +1.
is performed. If neither a +1 nor a -1 is required,
X2X1 is cleared prior to the 48-bit add and the original difference is preserved. The timing for all
floating-point instructions is common for normalize,
adjust exponent, merge, and complement. Go to page
244 to complete the timing for this instruction.
V600: If K880/88l (shift left 10) is set,
input to H523 and H561.
If K880/881 (shift left 10) is clear,
input to H513 and H551.
V60l: If lOs enabled:
I2-'A2, left shift 10 (A1~r2),
13~ Q2, left shift 10 (Ql~r3);
advance lOs count.
If lOs enabled:
12 --. A2 (AI ~2),
13~Q2 (Q1~I3).
Vn02:
Cle.::tT ~A.,l andQl;
transfer lOs count;
if K888/889 (shift l's) is set,
input to H525 and H565;
if K888/889 (shift l's) is clear,
input to H5l5 and H555.
V505:
Input to H500, H600, and H620.
If normalize complete:
set K830/831 (adjust exponent);
clear K898/899 (short cycle);
input to H810;
proceed to adjust exponent.
If normalize complete:
repeat shift cycle.
V603: If shift l's and shift right 1:
I°--.Al, left 1 (A2-.IO),
I1-.Ql, left 1 (Q2-+Il);
advance 1 's count.
If shift l' s and shift right 1:
I0-'Al, right 1 (A2--'IO),
I4Ql, right 1 (Q2-+Il);
advance 1 's count.
If shift l's:
14Al (A2-+IO),
r 1-"Ql (Q2-..r 1).
Ao4-15
AnI's
Left shift lOs
enabled
Normalize
arithmetic time 3
Left lOs shift enabled
Ao4-15
All O's
K886
Left shift lOs
enabled
K887
Q20 -----..Ao5 _ _----I~
All O's
Left shift lOs
enabled
Q20-+A05
AliI's
Figure 341. Enabling lOs Shifts
Left shift lOs
enabled
The timing for normalize is common to all floatingpoint instructions and consists of passes through the
arithmetic and shift timing chains. The arithmetic
passes are short cycles (4 0 times) since short cycle
was set at V504 time of round. The main items for
normalize are:
1. Right shift will never be more than 1 place and
could occur for a 60, 61, or 63 instruction. A12
f A13 indicates that a right shift is necessary.
2. Left shift can be any number of shifts less than
36 10 and could occur for any floating-point instruction.
3. lOs shifts will always be left and will always be
completed before any I' s shifts take place. Figure
341 is a simplified logic diagram of setting shift
left lOs. Note that S835 is forced to a Ion the first
pass by K886/887 and that S833 is forced to a 1 on
all following lOs passes.
4. Normalize complete is defined byeither one of two
conditions: AQ = or AI0-13 all alike.
°
345
Phase 3: Adjust Exponent
V500: Clear A2, Q2, Xl, and X2;
clear K826/827 (normalize);
if no shift or left shifts were required during
normalize, input to H821.
V501: I3~Q2 (Al--'I3), bits 0-11 and 23;
I86X/87X-'Q2, bits 12-22;if (Q3) is negative, Q3-----I86X/87X;
if (Q3) is positive, Q3-+I86X/87X.
V502
V503: Input to H942.
V504: Clear Q3;
input to H9430
V505: Sum ~Q3, set bit 11 of Q3;
if exponent sum = -0 (A negative) or
exponent sum ::f -0 (A positive),
input to H500, H620, and H820;
set K834/835 (merge).
The following items are of note for adjust exponent:
1. If no shifts were required during normalize the real
exponent is added to all O's and gated back to Q3 ..
2. If a right shift was required during normalize, adjustment of the exponent requires a +1. This is
accomplished by forcing bits 22 -12 of X2 to 0--- 01
and performing an addition with the real exponent
3. If the shift was left to normalize the shift count
0
If left shift to normalize,
If right shiftto normalize,
Set X620/621. (X2 registe
bits 12-22 set to a +1.)
181X/82X-.X2, bits 1222; SC register-+I81X/
82X, lower 6; nothing--"
181X/82X, upper 6.
(Complement shift
count to adder via
X2 register.)
must be subtracted from the real exponents to adjust the exponent. This is accomplished by gating
the complement of the shift count to X2 at V501 time
and performing an addition with the real exponent.
At V505 time of the last pass of normalize K830/831
(adjust exponent)was set which enables the 48-bit adder to function as an II-bit adder. K830/831 has the
same effect on the adder as K872/873 (add exponent 2).
Phase 3: Merge
V500: Clear A2, Q2 and E2;
clear K830/831 (adjust exponent);
input to H611 and H871.
V501: 12 -.. A2 (Ql--' 12);
I3-+- Q2, bits 0-11 and 23 (AI ..... 13);
I86X/87X-+-Q2, bits 12-22;
if (Q3) positive (Q3~I86X/87X);
if (Q3) negative (Q3-+- 186X/87X).
V502
V503: If AQ t- 0, input to H612.
V504: If AQ ::f 0, clear AIQl; input to H613.
V505: If AQ t- 0, I°-.Al (Q2~ID),
11~QI (A2"'I 1);
set K852/853 (complement AQE or last cycle);
input to H500, H620, and H820.
The data flow for merge is:
Q3~
~
-
-
' \ ... TO
~4h
t:..v
IO'7V
"
/.....-"~"-"'/ '-"
Q3~
The transfer of S"Uiii to Q3 at V505 time of adjust
exponent toggled the bias bit so that the biased exponent is available for merge.
Q2A2~IQl
Bits 12 -22
(Q3) negative
Bits 0-11 and 23
(Q3) positive
Phase 3: Complement
V500: Clear A2, Q2, and E2; clear KS04/S05
(optional arithmetic busy); input to H611, HS71.
V501: r:l~A2 (AI-+r~);
r3-+ Q2 (QI~ r3 );
EI~E2.
V502
V503:
If K532/533 is set
(unlike signs),
V504:
Clear K804/805 (optional arithmetic busy).
V505:
rnputto H864.
V864:
Clear K560/561 (arithmetic busy).
The complement of AQ would occur for floatingpoint multiply or divide when the signs of the coefficient were unlike. A complement of AQ will not
occur for floating-point add or subtract. A complement of E would occur for a floating-point divide when
the dividend was negative. K552/553 (sign of A) which
input to H6I2.
Clear Al and QI;
input to H6I3.
rO~AI (A2--.r O);
rl-'QI (Q2-.II).
If K552/553 (sign of A) is
set and 63 instruction or if
K532/533 (unlike sign 1) is
set and 62 instruction,
input to H834.
Clear EI;
input to H9I5.
Einv~EI (E2-+Einv).
indicates a negative dividend was set during copy
F I--'F2 time of RNI if A23 was set. A complement
of E would occur for a floating-point multiply if the
product were to be negative. The clearing of arithmetic busy at V684 time frees the arithmetic section
so that it may be used by main control.
PROBLEMS
1. May normalize be either a right or left shift for
the 62 instruction? Why or why not?
2. Assume that (AQ) is negative. During phase 1, Al
exponent
Q3 occurs. This places the complement of the real exponent in Q3. How are add exponents accomplished with read exponents in this
case?
3. How is 247 of the adder affected during add exponents?
4. At the completion of the multiply step where is the
product? Can you predict what the lowest 12 bits
of El will be?
5. Why is +1 the only possibility for round of the 62
or 63 instructions?
347
SELF-EVALUATION QUIZ ON CHAPTER 13
TRUE OR FALSE OR FILL IN THE BLANKS:
13.
1. The FP /DP option is located in chassis
~---
2. The FP /DP option is necessary to execute the
_ _ _--', and _ _ _ _ _ _ _ _ __
through _ _ _ _ _ _ arithmetic instructions.
3. Primarily, the FP /DP option consists of a 48 -bit
adder and the 48 -bit E register.
arithmetic passes are required
for divide step of a DVAQ •
14. The highest order bit of E is inspected to determine whether or not a round is necessary during
the FMU.
15. Normalize for the FMU will always be right shift
if any shifts are required.
4. The optional adder is enabled by setting of _ _
16. If the product of an FMU has a negative coefficient
and a positive exponent, complement will not occur.
5. The optional adder may function as an 11 -bit adder.
6. The multiplier for an MUAQ instruction is the
quantity in AQ.
17. Divide fault cannot occur during execution of the
FDV since the hardware can normalize.
18. The function of pass 3810 cf divide step on a FDV
is to allow sensing for round.
7. The first pass of multiply step for the MUAQ instruction must be a long cycle.
19. Round on a FDV will always be -1.
8. The multiply step of the MUAQ instruction requires 608 passes.
20. If
is set, the optional adder will
function as an II-bit adder.
9. Complement is optional in the execution of the
MUAQ instruction.
10. After the first multiply step of the MUAQ instruction, the multiplier hit is sensed at 21 of E2.
11. The amount of time necessary to execute a DVAQ
depends on the number of 0 bits in the divisor.
12. The four steps required for execution of a DV AQ
_ _ _ _ _ _ _ , and
are initialize,
Score Yourself
This quiz was a good one. You may not agree, but
you're entitled to that.
None wrong is way above average.
One wrong is above average.
Two wrong is average.
Three wrong- -you're slipping!
Four or more wrong--you've slipped--into failure!
CHAPTER 14
INTERRUPT
GENERAL DESCRIPTION
The interrupt feature of the 3300 Computer System
allows automatic sensing for specific internal or external conditions whose existence requires special
action on the part of the program. To recognize an
interrupt condition as soon as possible, the hardware
senses for interrupt during RNI and RADR. If an interrupt is recognized, execution of the main program
is terminated, the contents of P are stored at a fixed
location, and program control is transferred to a
fixed location.
TYPES
There are three major groups of interrupts in the
3300 system. These groups listed in order of priority
are:
1. Abnormal interrupts.
2. Normal interrupts.
3. Trapped instruction interrupts.
ABNORMAL INTERRUPTS
There are three interrupt conditions that are classified as abnormal. Listed in order of priority- these
conditions are:
1. Interrupt on storage parity- error or storage not
available.
2. Interrupt on illegal storage reference.
3. Interrupt on power failure.
These interrupts are not masked and the interrupt
system need not be enabled to recognize one of these
interrupts.
349
NORMAL INTERRUPTS
Tn general, to recognize one of these interrupts the
interrupts system must be enabled, the mask bit must
be set, and the interrupt counters must have counted
to the proper count. The exceptions to these conditions are:
1. Associated processor and manual interrupts are
not mask.
2. Executive interrupt is exclusive of all three stated
conditions.
External line interrupts and channel interrupts are
equal in priority, that is, if the channel counter is
active the line counter cannot be started; if the line
counter is active, the channel counter cannot be started. To assign a priority to the normal interrupts,
starting of the interrupt counter must be used as a
time
1.
2.
3.
*4.
5.
6.
7.
8.
reference. The priority becomes:
Executive interrupt.
Arithmetic overflow or divide fault.
Floating point fault or BDP fault.
External line or channel interrupts.
Search/move interrupt.
Real time clock interrupt.
Manual interrupt.
Adjacent processor interrupt.
TRAPPED INSTRUCTION INTERRUPT
The trapped instruction interrupt occurs whenever
an instruction that requires optional hardware is read
into F and the optional hardware is not present. This
interrupt is not masked and the interrupt system need
not be enabled to recognize this interrupt.
ABNORMAL INTERRUPT SEQUENCE
INTERRUPT ONSTORAGE PARITY ERRORORSTORAG E NOT AVAILABLE
This is the highest priority interrupt in the 3300
system and does not require the interrupt to be enabled. Interrupt on storage parity error is switchselectable from the console and recovery from this
fault may not be possible.
If the system is operating non-Executive when this
interrupt is recognized, the hardware interrupt sequence will store the (P) in the lower 15 bits of address 000208. The upper 9 bits of address 000208
are not altered by this operation. An identifying code
is stored in the lower 12 bits of address 000218 and
then RNI at address 00021 8 ,
If the system is operating Executive when this interrupt is recognized, the hardware interrupt sequence
will:
1. Disable the Condition register.
2. Transfer to Monitor State.
3. Store the (P) in the lower 15 bits of address
0000208; the upper 9 bits of address 0000208 are
not altered.
4. Store an identifying code in the lower 12 bits of
address 00021 8 ,
5. RNI at address 000021 8 ,
ILLEGAL STORAGE REFERENCE INTERRUPT
This is the second highest priority interrupt in the
3300 system and does not require the interrupt system
to be enabled. If the system is operating Non-executive, this interrupt does not exist.
If the system is operating Executive. there are four
ccmdi.tic.Il.s v;Mch ..vUl g.c.n.cr.utc n.n nlcgaJ stnragn Reference interrupt. They are:
1. Program State 0 and the STORAGE PROTEC T
switches compare with the lower 15 bits of the address placed on the S bus during a Write. This
condition is sensed in Main Control.
2. Program State and the Page Index referenced has
E = 1 and all other bits ::-: O. This condition is
sensed in the Multiprogramming module and the
interrupt would occur for either a Read or a Write.
3. Program state and the Page Index referenced has
E = 1, any other bit = 1, and a Write is specified.
This condition is sensed in the Multiprogramming
module.
4. Program State and the available page length as
spec ified by PL is exceeded. This condition is
sensed in the Multiprogramming module and would
occur for a Read or Write.
When this interrupt is recognized the hardware interrupt sequence will:
1. Disable the Condition register.
2. Transfer to Monitor State.
3. Store the (P) in the lower 15 bits of addres s
0000148; the upper 9 bits of address 0000148 are
not altered.
4. RNI at address 0000158'
POWER FAIL INTERRUPT
This is the third highest priority interrupt in the
3300 system and does not require the interrupt system
to be enabled. The purpose of this interrupt is to allow the computer to save any pertinent data before
shutdown due to a loss of line voltage. The logic for
detecting a power failure is shown in figure 342.
Source power of 110 vac provides power to the blowers in all the basic electronics cabinets. When this
110v power is brought up, a 24v holding relay (located
*Regardless of channel, a lower-numbered line has
priority over a higher-numbered line; a lower-numbered channel has priority over a higher-numbered
channel.
Figure 342. Power Failure Detection
1ST CYCLE
V009
48-BIT
KOOO
V006
JI31 RNI + RADR
~Tl
:ill
till
VI20
POWERFAIL
110 VAC
A &:111.1
LOCKOUT
III.IT
I""'\UI"t.II'"4I.
KI42
KI28
END OF STO VI86
KI29
V008
K456
K464
KI43
J289 Me
on the power panel) is energizedo This relay holds
the power up after the POWER ON switch is released.
The 24 volts from the relay transformer is applied to
J146 and J147 to normally prevent them from both outputting Is. If the 110 vac source power should drop,
the input voltage to J146 and J147 falls from 24 vac
to 0 vac, allowing both inverters to output Is. The
Abnormal Interrupt FF is then set at V006 time RNI
(provided that the RNI is not the second RNI sequence
for a 71 to 76 instruction) or at V006 of RADR.
Once Abnormal Interrupt has set, Powerfail Lockout will be set to prevent another input to the Abnormal
Interrupt FF. A master clear must then be performed
to again activate the powerfail detection circuit.
If the system is operating non-Executive when this
interrupt is recognized, the hardware interrupt sequence will store the (P) in the lower 15 bits of address 00002S and RNI at address 000038' The upper
9 bits of address 000028 are not altered by this operationo
If the system is operating Executive when this interrupt is recognized, the hardware interrupt sequence
will:
1. Disable the Condition register.
2. Transfer to Monitor state.
30 Store the (P) in the lower 15 bits of add res s
00002S'
4. RNI at address 00003S'
ABNORMAL INTERRUPT SEQUENCE
Timing begins with the Storage Reply during RNI or RADR.
V061:
VOOO:
V001
V002
V003
V004:
V005
V006:
V007:
V008:
V009:
V120:
N120:
N205:
Resynced Storage Reply
Clear KOOO/OOI (Request Bus)
Set K12S/129 if P. E. or illegal storage reference
If Power Failure Set K128/129 (.Abnormal Interrupt)
Clear K010/011 (Main Control Priority), K012/013 (Storage Request Lockout), and Kl16/117 (Storage
Request)
EXX2 to F, if (Power Failure)' (illegal Storage Reference). (ParItY Error), set K142/143 (Powerfail
Lockout).
Input H120
Set K086/087 (STO), K106/107 (Jump), and K124/125 (Special STO Cycle). Clear K080/0S1 (RNI) and
K082/083 (RADR). Input H201; transfer Condition Register to Subcondition Register.
Set Disable IFF K094/095.
Clear IF lower 18; Input H122
351
ABNORMAL INTERRUPT SEQUENCE (Cont)
N122: Clear K05S/059 Program State II
V122: Set KOOO/001 (Request Bus) if illegal Storage Reference; set K45S/459 (illegal Write Clear Enable); force
Flower 15 to the appropriate interrupt address (00002 + 00014 + 00020).
N051: Set K010/011, transmit address .... Flower 15 .... EXXS ..... T6XX ..... S bus; transmit Write signal and
designators of 100112. Note that Storage Protect comparison is disabled.
N050: Input Hl17.
Vl17: Set Kl16/117 (Storage Request), set K212/213.
N050: Input Hl15.
Vl15: Set K012/013 (Storage Request Lockout); transmit 15 on the Data bus.
Vl16: Test Breakpoint stop if BPO is selected.
V061: Resynced Storage Reply.
VOOO: Clear KOOO/001 (Request bus).
V001-V005: Access time.
V006: Set K126/127 (Second STO).
V007: Set FOOO/001; clear K49S/499 (Interrupt Enabled)--this clears the line, Channel and Interrupt cOlUlters
(if EXEC and Parity Error); Clear K496/497 (Interrupt Detected) if K498/499 cleared; input H086.
V086, V1S6: Clear K086/087 (STO), K124/125
For Storage PE interrupt, a second Store Cycle is re(Special STO Cycle), K126/127 (Second
quired to store the identifying interrupt code. For the
STO Cycle), K128/129 (Abnormal Interrequired timing refer to the Normal interrupt timing
rupt) , K464/465 (STO Parity Error); if
(time V007) on page 26~ The code stored at address
illegal Storage Reference Interrupt, clear
00021 varies with the type of sequence in progression
K456/457 (illegal Write); input H087.
and what control section had priority at time of interrupt.
V087: Input H014.
V014, NO 14 : RNI at the interrupt address since Jump is seto
NORMAL INTERRUPT SEQUENCE
The normal interrupts are treated as a group due
to the fact that the hardware interrupt sequence processes all of these interrupts in the same basic manner. For all of these interrupts, the following takes
place during the hardware interrupt sequence:
1. The (P) is stored in the lower 15 bits of address
00004S'
2. An Identification Code (I. D. code) is stored at address 000058'
3. RNI is performed at 00005S.
It is the I. D. code which distinguishes between the
normal interrupts. Table 21 lists the I. D. codes.
Parity Error Interrupts (Abnormal Interrupt) also
use the Second STO Cycle to store an ID code. Table
22 lists the Parity Error Interrupt Codes.
Table 21.
REPRESENTATIVE INT. J.D. CODES
Conditions
Codes
External interrupt
I/O channel interrupt
Realtime clock interrupt
Arithmetic overflow fault
Divide Fault
Exponent overflow fault
BCD fault
Search/move interrupt
*Manual interrupt
*As sociated proce ssor interrupt
*Executive interrupt
001Ch
010Ch
0110
0111
0112
0113
0114
0115
0116
0117
0120
*These Interrupts are not masked.
*See 3300 Command Timing
Table 22.
PARITY ERROR INTERRUPT CODES
Reason for Interrupt
Priority
Operation
Non-existent Memory
Parity Error
Non-existent Memory
Block Control
Block Control
Block Control
73-76
73-76
71, 72, or
typewriter I/O
OOXO
00X2
01XO
Parity Error
Block Control
71, 72, or
typewTiter I/O
01X2
Non-existent Memory
Main Control
RNI or RADR
00X1
Parity Error
Main Control
RNI or RADR
00X3
Non-existent Memory
Parity Error
Main Control
Main Control
ROP or STO
ROP or STO
0005
00X7
Code
X=ch
X=ch
(X=O,
(X= 1,
(X=3,
(X=O,
(X=l,
(X=3,
(X= 0,
(X=2,
(X= 0,
(X=2,
Search),
Move),
TWR)
Search),
Move),
TWR)
RNI) ,
RADR)
RNI),
RADR)
(X= 0 or 1*)
* If X = 1, the Parity Error occurred on the 00. 7 S TO Cycle.
EXECUTIVE INTERRUPT
The Executive interrupt occurs only if the system is
operating Executive and Program State and one of the
following instructions is executed.
00.0
53. (4 ~ 7)(1-.. 3)(XXOO -.. XX37)
71.X
72.X
73.X
74.X
75.X
76.X
77.Xbut not 77.71 or 77.72
The interrupt is removed when the hardware interrupt sequence transfers to Monitor State. Executive
interrupt is the highest priority of the normal interrupts and the interrupt system need not be enabled to
recognize this interrupt. Also it is not masked and
does not reference the interrupt counters. When this
interrupt is recognized, the following events occur:
1. Disable the Condition register.
2. Transfer to Monitor State.
3. Store (P) in the lower 15 bits of address 000004 8 .
4. Store the ID code in the lower 12 bits of address
0000058.
5. RNI at address 000005 8 .
OPTIONAL ARITHMETIC INTERRUPTS
An interrupt may be produced by a floating-point
fault or a BCD fault. The fault is detected by the optional arithmetic hardware (when present) or, in the
absence of the hardware, by the Simulator routine.
FLOATING-POINT FAULT
The Floating-point Fault FF, K420/421, is set to
indicate that a floating-point fault has occurred. It
may be set:
1. By the AND gate of V874 and S883 being made when
floating-point hardware detects the fault, or
2. When instruction 77.71, Set Floating-Point Fault,
is executed. The Simulator routine, used in lieu
of hardware, recognizes any condition that would
cause a fault and executes this instruction to set
the FF. Thus, an interrupt may occur in the same
manner as it would if floating point hardware were
present in the computer.
BCD FAULT
The BCD Fault FF, K418/419, is set to indicate that
a BCD fault has occurred. It may be set:
1. When a BCD fault has been detected by the BCD
hardware, or
2. When instruction 77. 72, Set BCD Fault, is executed. This instruction is also used by the Simulator routine.
INTERRUPT ADJACENT PROCESSOR
Instruction 77.57, Interrupt Adjacent Processor,
allows two processors to interrupt each other.
When the function code of the instruction has been
decoded, T148 outputs an Interrupt Adjacent Processor signal. This signal is received by the adjacent
processor and sets K408/409 in the other processor.
This FF remains set until the interrupt is recognized~
INTERNAL INTERRUPTS
Eight internal conditions may be set to cause an interrupt. These conditions are: Executive Interrupt,
Arithmetic Overflow fault, Divide fault, Exponent
Overflow fault, BCD fault, I/O channel interrupts,
Search/Move interrupt, and Real Time Clock interrupt.
353
EXTERNAL INTERRUPTS
Three external conditions may cause interrupts.
These are: External I/O interrupts (generated by a
piece of I/O equipment), Manual interrupt (set by a
switch on the console or a switch on the console typewriter), and the Associated Processor interrupt.
The mask is selectively set with instruction 7752XXXX,
and selectively cleared by instruction 7753XXXX
(XXXX represents the mask bits). Master Clear does
not affect the mask register. Table 23 gives the mask
bit as signments.
Table 23. INT. MASK REGISTER BIT ASSIGNMENTS
INTERRUPT MASK REGISTER
The programmer can choose to honor or ignore
most normal interrupts by means of the Interrupt
Mask register. The Mask register is a 12-bit, singlerank FF register with inputs from the lower 12 bits
of the F register. The mask bit representing an interrupt condition must be set to a 1 for that interrupt
condition to be recognized by the sensing network.
BIT POSITIONS
DE FINITIONS
00-07
I/O channel 0-7 interrupts
(internal and external)
Clock interrupt
Exponent overflow or BCD fault
Arithmetic overflow or divide fault
Search/move completion interrupt
08
09
10
11
The manual interrupt and the associated processor
interrupt are not masked and thus will always be recognized provided the interrupt system has been enabled.
The interrupt system must be enabled for any normal
interrupt except Executive to be recognized.
Figure 343.
INTERRUPT SELECTION
The programmer has master control over the normal interrupt system. Instruction 7774---- must be
executed to enable the system The translation of th·IS
Interrupt Cycle Flow Chart
External
interrupt
Interrupt from a
peripheral cont roll e r detected ~
on 0 n e of e i g h t
I/O channels
The line counter
scans the lines until
it detects the line
which carries the
interrupt signal.
Internal
interrupt
I/O channel interrupt (end of record
or end of an input
or output block).
r--
Advance "the channel counter u n til
it detects the numher of the interrupting channel.
Arithmetic overflow, divide fault,
exponent
overflow
Internal
fault,
BCD
fault,
interrupts
real time clock interrupt, search / ~
move completion;
I
m,;:uJual mterrupt I
External
or
interrupt from
interrupts
other computer
"
Interrupt counter
advances to determine which interrupt is present.
r----
Interrupt FF is
set to i n d i cat e
to main control
that an interrupt f--Ihas been detected
. .
land ldentlfled .
At the end of
RNI main control recognize s
the interrupt.
---
Store sequence
begins.
PER FORMED BY
instruction by M4l3 sets K454/455 at the end of the
RNI sequence. The output of this FF, in turn, sets
K498/499, the Enable Interrupt FF. Inthe clear state,
this FF disables interrupt recognition by holding the
inputs to the interrupt counters down.
Instruction 7773---- clears Enable Interrupt. This
FF is also cleared by J125 which comes up when Abnormal Interrupt, PE, and Disable (J855) = 1. (The
interrupt section has identified an interrupt before
main control enters an interrupt cycle.) Thus, while
the main control section is processing an interrupt,
all other normal interrupts are disabled. When leaving the interrupt subroutine, the program must execute another 7774---- instruction to again enable the
interrupt system.
The timing on setting Enable Interrupt is such that
the interrupt system is not enabled immediately following the 7774---- instruction. Thus, after executing
a 7774---- instruction, one more instruction is executed before another interrupt can occur. This insure s
that the computer will return to the original program
before the next interrupt. If this were not the case,
and interrupts were to follow each other immediately,
the original return address might be lost. K455 does
not clear until (End RNI)(Indirect) of the next instruction after the 77.74 instruction. This blocks NOlO
(page 2-7) and permits one more instruction before
Interrupt control is fully enabled.
INTERRUPT RECOGNITION
Before an interrupt can be processed, the interrupt
section must recognize the interrupt and determine
its origin.
An order of priority exists between the v;lrious
interrupt conditions. When an active interrupt is received, the priority scanner, composed of three counters (Line, Channel and Interrupt counter), begins
checking the priority list. The sensing networks compare the priority count with the active interrupt. \Vhen
the Interrupt counter starts a resync network is pulsed
and the output of the resync sets K496/497, Interrupt
detected. This signals main control that an interrupt
condition has been detected and identified. Figure 344
is a flow chart of the steps in interrupt recognition.
,- - - - - - - - - - - - - - - - - SOFTWARE
CONSIDERATION
Jump back to
00004 to obtain
the address for
return tot he
main program.
~
I
I
1
1
I
t
I
I
Process the interrupt using a
routine previously stored.
IL ________________
A
J
Contents 0 f P
Address por ( dd
f
a ress 0 next
tion of the ind .
----- struction in F ~ unexecut.e )1~ ~ ~
s t rue t Ion IS
is set to 00004.
store d at 00004 .
Sec 0 nd
Address por. .
store se_ twn of the Inque nee - - - struction in F
.
.
beglllS .
IS set to 00005.
~
Interrupt t ran s lation
(unique representation
for each interrupt condition, obtained from
RN I from
translation of interrupt ---. add res s
counter) is placed on
00005.
data bus, then stored
in the lower 12 bits of
address 00005.
HARDWARE-----------------------------------------------------------------------355
~.:'JO
~~~
Internal
If RNI + RADR
Start interrupt
Sequence
NORMAL INTERRUPT SEQUENCE
Timing begins with NOlO which could be VOIO time of RNI or VOOS time of RADR.
NOlO: If Interrupt has been detected, set K496/497; set K120/l2l (Interrupt Sync). Note that this blocks End
RNI and End RADR pulses.
N053: Input H120.
V120: Set KOS6/0S7 (STO), Kl06/l07 (Jump), K124/l25 (Special STO), and K094/095 (Disable I); clear KOSO/OSI
(RNI) and KOS2/0S3 (RADR); Input H201.
N053, N205: Clear F; Ll1put H122.
V122: Clear K05S/059 (Program State II); Set KOOO/OOI (Request Bus), and F020/021.
N05l: Set KOIO/Oll (Main Control Priority); transmit address 000004, F to EXXS to T6XX to S bus; transmit
Write signal and Write designators of 100112 •
N050: Input to Hl17.
Vl17: Set Kl16/ll7; transmit a Storage Request.
N050: Input to Hl15. NOTE: storage protect comparison is disabled.
VI15: Set K012/0l3, Transmit P on Data Bus (P to T5XX).
Vl16: Test Breakpoint stop if BPO selected.
V06l: Resynced Storage Reply.
VOOO: Clear KOOO/OOL
VOOl-V005: Access Time.
V006: Set K126/l27 (Second STO). Timing from this point on also applies to Parity Error Interrupt Sequence.
V007: Clear KOIO/Oll, K012/0l3, Kl16/ll7; input to H086, input to H122, set FOOO/OOL
V122: Block output from VOS6 and VlS6 (J063); set KOOO/OOL
N05l: Set KOIO/Oll if K2l0 = 1; transmit address 00005, F to EXXS to T6XX to S bus; transmit Write signal
and Write designators of 000112 •
N050: Input to Hl17.
Vl17: Set K2l2/2l3, Kl16/ll7; transmit a Storage Request.
N050: Input to Hl15.
Vl15: Set K012/0I3 (Enable DBR to T5XX); input Hl16, H400.
Vl16, N400: Test Breakpoint Stop if BPO selected; input to H401. NOTE: storage Protect Comparison is
Disabled.
N40l: Clear DBR; input to H4l0.
N4l0: EXX2 to DBR, (ID. to EXX2 to DBR to T5XX to Data bus).
V06l: Resynced Storage Reply.
VOOO: Clear KOOO/OOI.
VOOl- V004: Access Time.
V005: Clear K124/125 (Special STO), J063 = 0; clear K464/465 Storage Parity Error (if PE sequence).
V006: Clear K49S/499 (Enable Interrupt) via J125.
V007: Clear KOIO/Oll, K012/0l3, Kl16/ll7; input to HOS6.
VOS6, VlS6: Clear K126/l27 (Second STO), K120/121 (Interrupt Sync), KOS6/0S7 (STO); set KOSO/OSI (RNI);
input to H08 7•
VOS7: Input to H014.
V014: Jump and RNI at address 00005.
357
TRAPPED INSTRUCTION INTERRUPT
All commands in the instruction repertoire of the
3300 Computer System may be used regardless of the
size of the computer. However, a basic computer
lacking the. optional floating-point 48-bit precision
and/or the BCD package is not capable of directly proce ssing instructions that require this hardware. These
instruction, implemented by software, are called
trapped instructions.
Trapped instructions fall into two groups, those that
are trapped when the floating-point 48-bit precision
option is missing and those that are trapped when the
BCD option is absent. Table 24 lists the instructions
which may be trapped.
Table 24. LIST OF TRAPPED INSTRUCTIONS
CODE MNEMONIC
DESCRIPTION
Floating-point 48-Bit Precision Package Missing
1----
55
56
57
60
61
62
63
r - - - - - r - - - - - - - - - - --IRT, 48-bit precision
Multiply AQ, 48-bit precision
Divide AQ, 48-bit precision
Floating-point add
Floating-point subtract
Floating-point mUltiply
Floating-point divide
MUAQ
DVAQ
FAD
FSB
FMU
FDV
BDP Package Missing
i-
-
64
65
66
67
70
- - - - LDE
STE
ADE
SBE
SFE
EZJ, EQ
EZJ, LT
EOJ
SET
-- -
-----
Load E
Store E
Add to E
Subtract from E
Shift E
E zero jump (E = 0)
E zero jump (E = 0)
E overflow jump
Set D register
-
--
Translator Jl18 (figure 345) determines when an instruction is to be trapped. When the function code of
any optional instruction has been decoded the left AND
gate to Jl18 is broken. The other two AND gates then
test whether the necessary optional arithmetic package is present. If it is present there will be no interrupt and the instruction is handled by the hardware.
If the necessary hardware is not present, Jl18 outputs a 1 which sets trap sync FF at the end of RNI.
A trapped instruction interrupt then proceeds in much
t.hp.
R~mp. m~nnp.r ~
in
R ::l
norm~l
intArrupt.
·The steps
the trapped lnstrl.lC:tiofl interrupt cycle
are:
1. At VOIO time of RNI a test is made for interrupt.
358
2. RNI ends; trap sycn FF is set if Jl18 indicates a
trap cycle necessary.
3. Advance P2 to set the address of the next instruction in P2.
4. Start arith 1, start arith 2, no index, RNI, RADR,
and Rap FFs are cleared. STO, special store
cycle, and jump FFs are set. This sets up initial
conditions for the trap cycle.
5. The lower bits of the F register are cleared.
6. (P2) is transferred to PI.
7. Set request bus FF.
8. F030/031 of Fregister is set. This places address
00010 in F.
9. Main control obtai~s bus priority. A write signal,
write designators of 10011 2 (word address), and
the storage address (00010) are transmitted to
storage.
10. A storage request is sent to the selected module.
11. The complement of the contents of P (address of
the current unexecuted instruction) is placed on
the data bus. This address is then stored in location 00010.
12. A storage reply is received and resynchronized
when the storage module has accepted the word.
The resynchronized reply starts the storage timing chain.
13. Second store cycle FF is set.
14. The bus is released.
15. FOOO/OOI is set. This advances the address in F
to 00011.
16. Request bus is set.
17. Bus priority is once again obtained. A write signal, write designators of 00001 2 (lower 6 bits),
and the storage address (00011) are transmitted
to storage.
18. A storage request is transmitted.
19. Data bus register is cleared.
20. Gate EXX2 to DB register, shifted right three
character positions. (F to 17 to EXX2 to DB register. DB register to the T5XX transmitters of
the data bus.) The storage module accepts the
data and stores the upper 6 bits of F in the lower
6 bits of address 00011. The upper 18 bits of the
word in 00011 are unchanged.
21. A storage reply is received and resynchronized.
The resynchronized reply starts the timing chain.
22. Clear special store cycle FF.
23. The bus is released.
24. Second store cycle, trap sync, and SRO are cleared
while R~I is set.
25. An RNI is now performed with a jump to address
00011. When the trapped instruction interrupt has
hAp.n pror.p.RRp.d, 3 jump is wade back to address
00010 where the address for return to the main
program is found.
F361 56- 63
F366 (=55:-:-)(:-::-1~-3~+~5:---;;-7')
.
M169---o
56 - 63
6X.X
('=55=-0-)(-:-:'1--3:::-+-=5:---=C
7)
70
FPPresent
F361
F365
F366
F368
Trap
J687 STO PE
I
~IlM1681
K120 Int Sync
K142 --PW=-"'Re-:l:-:L"-oc"""'"k-ou-:-t
64-B7 F364
70 F368
J003 MC Priority
K127 2nd STO Cycle
V010
-+--O-~
1iifSYiiC K122
K124 Second Store Cycle
K126 Special Store Cycle
N053 Odd Time
Abnormal Int K138
K136 Breakpoint Lockout
V016
Second store
C cle
STO PE J687
V186
(End of RNI) V380
K440l--_-o-_~
K441
I---o-~ K126
K125
K127
Vl86
Figure 345. Trapped
Inst~ction
V005
K136
Detection
TRAP SEQUENCE
Timing begins at V008 of RNI.
V008:
V009:
YOlO:
VOll:
V080:
N05l:
V120:
EXX2 to Flo
Clear K002/003. Test Interrupt. Set K140/l4l (Trap Sync).
Input to H080.
Advance Storage Sequence Controls to the appropriate cycle. Set K440/441.
Input to H120, Block Start Arith Pulses (J142).
Apply clear pulses to: K080/08l (RNI) , K082/083 (RAD) , K084/085 (ROP), KlOO/lOl (Start Arith),
Kl12/ll3 (Not RNI· Not INDEX). Block # setting of KIlO/Ill (IO to FEn.), KOOO/OOI (Request bus);
set K086/087 (STO), K124/l25 (Special STO), Kl06/l07 (Jump), K094/095; Disable I (if Exec); input to
H20l, H23l.
N05l, N205: Clear F L , input to H122. P2 is advanced, input H220.
V122: Set KOOO/OOI if K2l0 = 1. P2 to PI, clear K058/059 Program State II; set F030/03l F register bit 03
(Address 00010)
N05l: Set KOlO/Oll if K2l0 = 1. Transmit address 00010, F to EXX8 to T6XX to S bus. Transmit Write signal and Write Designators of 100112 ,
N050: Input to Hl17. NOTE: Storage Protect Comparison is Disabled.
Vl17: SetKll6/ll7, K212/213; transmit a Storage Request.
N050: Input to Hl15.
Vl15: Set K012/0l3, transmit P on Data Bus (1) to T5XX)
Vl16: Test Breakpoint Stop if BPO selected.
V06l: Resynced Storage Reply, (Block setting of K060/06l if DP instruction).
VOOO: Clear KOOO/OOL
VOOl-V005: Access Time.
359
TRAP SEQUENCE (Com)
V006:
V007:
V122:
N05l:
Set K126/l27 (Second STO).
Clear KOIO/Oll, K012/0l3, Kl16/ll7, K2l2/2l3; input to H086, input to H122, set FOOO/OOL
Block output of V086 and V186 (J063); set KOOO/OOl, request bus.
Set KOIO/Oll if K2l0 = 1. Transmit address 00011, F to EXX8 to T6XX to S bus. Transmit Write signal and Write Designators of 00001 2 •
N050: Input to Hl17. NOTE: Storage Protect Comparison is Disabled.
Vl17: Set Kl16/ll7, K2l2/2l3; transmit a storage request.
N050: Input Hl15.
Vl15: Set K012/013 (Enable DBR to T5XX); input to H400; set K042/043, first transfer to bus.
N400: Input to H40l.
N40l: Clear DBR, input to H440.
N440: EXX2 to DBR (RS3), F to 17 to EXX2 to DBR to T5XX to Data bus; clear K042/043.
V06l: Resynced storage Reply.
VOOO: Clear KOOO/OOL
VOOl-V004: Access Time.
V005: Clear K124/l25 (Special STOle NOTE: J063 = O.
V006:
V007: Clear KOIO/Oll, K012/0l3, Kl16/ll7, K2l2/2l3; input to H086.
V086, V186: Clear K126/l27 (Second STO),. Clear K140/l4l (Trap Sync), K440/44l; input to H087, clear
K086/087 (STO), set K080/08l (RNI).
V087: Input to H014.
V014: Jump and RNI at Address 000111.
INTERRUPT SENSING
Normal interrupts may be selectively sensed, independently of the interrupt mask register.
The interrupt status and fault sensing networks (Logic Diagrams, pages 2-207, 2-209 and 2-211) identify
the various conditions. The instructions used for sensing are:
(c
1.
2.
3.
= I/o channel designator, XXXX = sense mask)
77. 2cXXXX - Sense status of I/o equipment.
77. 3cXXXX - Sense internal status.
77. 4cXXXX - Sense interrupt.
The various interrupt conditions are identified in
the sensing network (figure 346 shows a portion of this
network), then the condition identified is compared to
its corresponding mask bit. If the mask bit is a 1 for
the active line, one of the J45X* inverters outputs a
O. J455 of the comparison network also outputs a 0 to
indicate comparison found. In this case, no further
action is taken and program execution continues with
an RNI from location P + 1.
Upon execution of sense instruction, if the mask bit
for the active line is not set or if no lines are active,
J455 outputs a 1 to indicate no comparison. This output is
*X
=2
llSP(/
to spt skip 1<'1<',
+4 +6
Proe-r:nn pxpcmtion thpn
PA USE INSTRUCTION
The sensing network is also used for the pause instruction, 77. 60XXXX (XXXX is the mask). The busy
lines defined in table 25 are sensed and compared to
the mask.
Table 25.
BUSY COMPARISON MASK
COMPARISON MASK
BIT POSITIONS
00-07
08
09
10
11
DEFINITION
Channel 0-7 busy
Typewriter busy
Type finish
Type repeat
Search/move contr the controller which will SO(!)ll
reply by placing a word or character in 0 register of
the communications channel. Receipt of this word or
*Contents of address specified by P
369
Register file
busy
Scanners must
recognize and
identify the
re uest
Read register
file location 22
and increment
1--_ _ _ _-I~Write
Zl back t-------I~ Read register
into location 22
file location 32
b 1
Disable reset and
release the scanners
Clear clock request
Figure 350.
character will cause the communications channel to
generate the block control request signal. A write signal causes the communications channel to generate the
block control reque.st signal immediately.
After block control has granted priority to the request, the delay line is started via the G659 (Logic
Diagrams, page 2-177) input to Z332/333. Register
OX, * which contains Ml, is read into Zl. The contents of ZI are then sent to the current address register (82) and to zo through the increment/decrement
network. The network will increment or decrement
Ml by 1, 2, or 4, depending on the type of instruction.
At the same time, Z352/353 (Logic Diagrams, page
2-167) has been set in order to generate the storage
reque st in main control.
Register lX* (M2) is read out and placed in Zl. The
comparison network (Logic Diagrams, page 1-103)
"'Contents of address specified by P
370
Flow Chart for Updating Real Time Clock
will test for Ml = M2. If equality does exist the comparison FF Z350/351 (Logic Diagrams, page 2-167)
will be set. Setting the comparison FF does not terminate the operation until after the word or character
currently being processed is delivered to or from storage.
Transmission of the storage request will suspend the
program while main control waits for bus system priority. The reply from memory originated by the request
from block control will start the timing chain at H150
(Logic Diagrams, page 2-161). As each control delay
is pulsed by the preceding one, certain enabling signals are transmitted. The data bus is connected to 0
register and the communications channel transmits or
receives one word or character. After transmission
of the word or character, the bus is released and the
-----tt-l~
Write register I--_ _--I~
file location 32
No
Yes
~--.t
Record compare;
set clock interrupt
program resumes. The request procedure is repeated
by the communications channel until the block of addresses is exhausted.
I/o
OPERATIONS WITH A
An I/O operation with A begins in the same manner
as those operations with storage. The request from
the communications channel causes registers OX and
IX to be read. A storage request is transmitted in
order to gain access to the bus. A memory cycle is
initiated but, as the lower 17 bits of the first instruction
word are meaningless, the memory performs only a
read. Arithmetic is started and the bus is enabled to
14. After propagating through the adder, the word or
character is placed in the lower bits of A. The upper
bits remain clear. If the operation is an OTA, the
data path is A to I2 to Xl to 17 to EXX2 to DBR to Data
bus.
TYPEWRITER
A type operation begins when the computer senses
a 77.75 (type -in), a 77.76 (type -out) instruction, or
when the operator presses TYPE LOAD or TYPE DUMP
on the console or typewriter. Before this, the current
and terminating address of the block must have been
stored in register 23 and 33 of the register file. This
storage is accomplished through the IRT instruction.
Receipt by block control of a type-in or type-out signal (Logic Diagrams, page 2-169) 'will set a corresponding flip-flop (Z360/361 for type-in, Z362/363 for
type-out).
A block control request signal is then placed in the
scanner network (for type -in, a character must be
typed to initiate the request). After granting priority
the delay line is started and register 23 (M1) is read
out. A storage request is generated and, after mem0ry replies, the bus is connected to 0 register in the
typewriter via transmitters and receivers in block control. A character is then sent to or from storage via
the bus.
During type -in a strobe signal indicates to block control that a character has been typed and is in 0 register
of the typewriter. During type -out a busy signal will
be sent by the typewriter indicating that it is ready to
accept a new character.
When the type load indicators on the typewriter and
on the console go off it indicates type load operation
(NIl = M2) is finished. The operator could continue to
type but the data would be lost.
TIMING
See figure 350.,
}793 = 1 for 200 nsec (when C051 starts its positive
swing and Z380/381 (clock request FF) sets. }793 is
a pulse shaper (C089 card).
G620 = 0; group 3 scanner goes set-set; G638 = 0;
G641 = 1; group scanner goes set/clear; group/program
scanner goes clear-clear.
If Z390/391 has been clear 100 nsec, G657 and G659
will have 100 nsec pulses since G651 = 1 and G656 = O.
SO is forced to a22; Z332/333 (start delay line FF) and
Z348/349 (clock control FF) set.
371
Record buffer cycle with G642 = 1.
(A3) E353: Read current on, clear S2.
(A4) E388: Clear Z332/333 (start delay line FF).
E351: Sense amps -.. ZI, set Z398/399 to disable scanners.
(A7) E356: SO -.. 81, ZI
~
ZO, Zl -.. S2; clear ZOo
(AI0) E359: ZI -.. ZO; clear Z380/381.
(B3) E355: Clear ZI; set Z328(329
set Z390/391; increment all 24 bits by 1.
(rescan 3 FF).
(B4) E367: Advance SO to 32.
(B6) E365: ZO -.. ZI; clear rescan 1 and 2 FFs.
(B8) E360: Write and digit current on; clear rescan 3 FF.
(C2) E367: Clear Z1.
(C5) E370: Read current on.
(C6) E371: Sense amps ...... Z1.
(C9) E376: SO ....... SI.
(D5) E375: If Z1
= ZO «22) = (32», set Z350/351 which sets Z378/379 (clock interrupt FF).
(El) E380: Write and digit currents on.
(E6) E387: Clear Z390/391 and Z350/351.
(E7) E389: Clear Z348/349 (clock control FF).
372
Program priority
\--_ _..... Request program
priority
Transmit channel
enable to C,
drop clear enable
Yes
IRelease block
__- - - - - I..
control
RNI at P + 1
Release block
control
Gate connect or
function code from
F register to
Ore ister
Transmit connect
or function
Wait for external
equipment or
channel response
100 nsec maximu
.-----.t RNI at P + 2
Figure 351. Flow Chart for Connect (77.DC) and Function (77 .1C) Instructions
The flow charts on the following pages show the progression for instructions 71 to 77.1 and the singleprecision interregister transfer instructions (figures
352-357). Complete timing for the instructions is
given in the command timing charts.
The 71 to 76 instructions are covered in two parts,
activate and buffer cycle. During activate the instruction is in F register. Duringbuffer cycle main control
may be executing the instructions of a program or may
be stopped. Use the flow charts as you follow the respective instruction through the Command Timing
Charts and Logic Diagrams.
373
Program priority
I-----t. .
2nd instructiont-_ _---,
ord to DBR
Request program
priority
RNI at P + 2
No
Release
block control
RNI at P+3
Activate
search/move
continuously
r---e-t~ Store (DBR) at
register 2X
Destructive
read phase at
register 2X
I----'---....-t
~--4!--""'" Store (DBR) at I------t~ Release
register 3X
Destructive
read phase at
register 3X
Figure 352. Flow Chart for Activate Search (71) or Move (72) Instructions
374
block control
Register file
EiiSY
I
Scanners must
recognize and
identify the
request
Disable, reset, and l - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
release scanners
Read (register OX),
store in S2,
increment/ decrement
ZlZ0
-
I
Write (Zl) in
register OX
Read register
IX to Zl
No
1
J----~
Bus priority
granted
Transmit channel
enable, and drop I------I~
clear enable
Transmit S2 on S bus;
transmit storage request;
transmit read si nal
Clear 0 register
Yes
DBR to bus,
bus to 0
No
A register to
DBR via X
L--_ _ _ _ _ _ _ _- I...
Transmit
operation complete
RNI at P + 3
Figure 353.
Flow Chart for Output Buffer Cycle
375
Disahle, res~, and~~~~~~~~~~~~~~~~~~~~~~~~~~
release scanners
Register file
busy
Scanners must
recognize and f--~--(
identify the
request
Read (register OX)
~ store in S2,
) - . _......
increment/ decrement
ZIZO
Write (ZI) in
register OX
Read register
IX to ZI
Yes
No
Record
compare
Bus priority
granted
Transmit channel
enable, and drop
clear enable
ransmit write
signals
Yes
tart arithmetic
~--------~~BR~X~A
Clear 0
register
t--~~-----t Channel checks 1--_...,
complete
S2 to S bus)
o register to DBR,
DBR to data bus)
data bus to
memory register Z
Time out
access
Yes
No
~------------~--~~-~~~
Figure 354.
Release
block control
Transmit operation
complete
Flow Chart for Input Buffer Cycle
Disable, reset, and 1----------------------------release scanners
Register
file busy
r-S-=c-a-nn-e-r.....s'--m-u-s-t"""
recognize and
identify the
request
Write (Zl) in
register 20
Read register
30 to ZI
Read register 20
)--.L.....t~increment/decrement ZIZ0~--oCD
Yes
(except 1st pass)
(0----'
1-.-_",
Clear
search/move
busy
transmit
read si nal
No
1--_ _ _ _ _ _-...-tRelease
block control
Set
Time out
access
Gate character
to DBRL6
Clear
search/move
busy
~-------~~ search/move
request
Figure 355. Flow Chart for Character Search Buffer Cycle
377
Register file
busy
Disahle, reset, and
release the scanners
Scanners must
recognize and
identify the
request
r-.......~Read (21)
I-----t~
I---_ _ _ _ _
Clear
search/move
request
1
rncrement ZlZ0
xcept 1st pass
I-----I~
Zl to S2
word address
ecrement
character count
Yes
No
Clear
search/move
busy
Increment ZlZ0
except 1st pass
Write (Zl)
in 31
Memory to DBR
via data bus
Bus priority
granted
Gate character
position into
S2 register
(S2) to S bus
Simulate
bus release
Bus priority
granted
(S2) to S bus,
(DBR) to data bus
)O---I~ transmit write
signal and
designator(s)
Set
1...--------_..... search/move
request
Figure 356. Flow Chart for Move Buffer Cycle
378
Release bus,
release block
control
Arith
busy
Start arithmetic
A or Q to Xl
Xl or 16 to 17
No
Yes
I---+-~DBR
1-
Kequest
block control
i
Initiate RNI
at P + I
to Zl
Clear DBR
Block control
priority granted
'---_ _ _ _ _ _ _ _ _.......-I~Read register file
to Zl and SO
_I
(Zl) in
C0+ Write
register file XX
"'-IDBR to Zl
I
QJ-+ EXX2 to DBR
..-
I
J
•
IYeS(Read
register file?
Write (Zl) in
register file XX
....
No
••
Release
block control
H.
Start arithmetic
~ DBR to A, Q, Bb
Write (Zl) in
~ register file XX
~
Read register file
to Zl and ZO
-..
Write (Zl) in
register file XX
Figure 357. Flow Chart for 1RT With Register File
379
I/O WORD MODIFICATION
Activate I/O and S/M are two-word instructions
which are read from storage and placed into the register file so that Block Control can accomplish the
actual block operation. So that these instructions can
access any portion of 262K of core storage, an 18-bit
word address or 20-bit character address is necessary. The instruction format for the 71 through 76
instructions only allow for a 15-bit word address or a
17-bit character address. The upper 3 address bits
for this instruction group are obtained from the lower
3 bits of the A register. Therefore, the words placed
in the register file on activate will consist of 27 bits
and, in appearance, will differ appreciably from the
Activate instruction.
For 73 through 76 instructions, on activate, (P) are
stored in register IX and (P + 1) are stored in OX.
Figure 358A and 358B illustrate the contents of OX and
IX and the function which the bit positions represent.
Note that bits 24 through 26 of OX and bits 21 through
23 of IX hold a quantity referenced as modified operation code. This quantity is derived from the original
6-bit operation code of the Activate instruction. The
upper bit of the modified operation code is 0 for operations with storage and 1 for operations with A. The
lower two bits of the modified operation code are the
lower two bits of the original 6-bit operation code.
00
Current character address
L.---------l. 1 for interrupt on completion
L . . - - - - - - - -.... O for Assembly
L.----------~1
for backward storage
L . - - - - - - - - - - - - - 4 . 1 for word count control
L-.--------------~Upper
3 bits of address
L.---------------------I.Modified operation code
Figure 358A. Contents of OX Register
001
--~--- ~--~---J'~--------~T~-------------J
t.
Last character address
+1 for forward storage.
Last character address
-1 for backward storage
Copy of bits 17 through 20 of (F)
L.--------P
L.-_ _ _ _ _ _ _ _ _ _----,.
~
.
Modified operation code
Meaningless - not used by buffer cycie
not accessible to programmer
Figure 358B. Contents of IX Register
380
BLOCK CONTROL Worksheet
1. Several sets of I/O instructions are shown below.
Write them as they would appear in the register
file.
(A) = 00000001
73 000105
20 400100
(A) = 00000005
7-3 000105
21 000100
= 77777774
75 400105
21 000100
(A)
(A) = 00000000
75 000105
27 000105
(A) = 00000006
74 000104
36 000100
(A) = 00000003
76 000104
37 000100
2. A move buffer cycle is in progress. Tne address
portion of the word in the register file is:
RF 21 = 32400013
RF 31 = 72000100
What would be the pseudo-character address used
during the read portion of the move buffer cycle in
order to have the character that is read from mem ory positioned in the proper place in DB register
before the store cycle?
30 On a search instruction, a character is read from
storage and compared to a character which is part
of the instruction word in register file location 30.
When this comparison takes place the character
from storage is located at character position
of
register and the character from the instruction word is in the upper six bits of _ _ __
register.
4. If requests came into block control from program
control, search/move, channel 0, channel 2, channel 7, and type, and block control is servicing the
request from channel 0 first, in what order would
the remaining requests be serviced?
1.
2.
3.
4.
5.
(A) = 000000000
74 400104
37 000100
(A) = 00000002
76 000104
30 4{}0100
381
TIMING CHARTS
Timing for Activate I/O, 73 through 76 instructions.
V008:
V009:
V010:
V011:
V080:
Timing begins at V008 of first RNI.
EXX2 to Fl.
Test interrupt.
Input H080.
Set K152/153 (Program Request); when J179 = 0 the Group/Program scanner will hang up set/set, indicating program priority.
Asyncronous: Input H170 when Program Priority and R. F. Busy.
V171: Set K168/169 (Program Register File Priority); input H016; initiate RNI to read second word of the
instruction.
N014: Set KOOO/OOI (Request Bus); input to H23l.
N231/N051: Set K010/011 (Main Control Priority); advance P2; input H220.
N220/N050: P2 to PI; input Hl17.
Vl17: Set Kl16/117 (Storage Request).
N050: Input Hl15.
Vl15: Set K012/013 (Enable Data Bus).
Vl16: Test BPI.
Main Control now waits for Reply from storage.
V061: Resynced Storage Reply; set K060/061 (1st Cycle) which blocks sensing interrupt for this RNI.
VOOO: Clear KOOO/OOI (Request Bus).
V001- V004: Access time.
V005: Set K062/063 (2nd Cycle).
V006: InpUt to H401; Block input to H20l.
V007: Clear K010/011, K012/013, Kl16/117, DBR; input to H410; block input to H200.
V008: EXX2 to DBR, EXX2 to F1 does not occur; set Kl64/165 (Read and Write). Note that at this point in the
timing, F holds (P) and DBR holds (P + 1). Set K176/177 (Gate Channel 0); remove clear inputs from
K15X Channel designator FFs; gate channel designation to K15X channel designator FFs. Note that the
actual channel designated is the inclusive OR of CIR and bits 21, 22, and 23 of DBR. When the contents
of the Channel Designator FFs have been translated (Logic Diagrams, page 2-165) a Channel Enable
signal will be transmitted to the appropriate channel.
V009:
V010:
V011:
V080: Input H151; if selected channel Busy, set KI08/109 (Skip); if selected channel Busy, set K044/045 (Reject
Read and Write).
If Channel Busy
Block Control Timing
V151: Input H014; input H156.
V156: Clear K 15 2 / 15 3 (Program Request); Clear
K 16 4/165 (Activate Read and Write); clear
K176/177 (Enable channel 0); drop the Channel
Enable.
V157:
V158: Clear K168/169 (Program Register File Priority).
Main Control Timing
N014: Set KOOO/011 (Request Bus); input H231.
N051/N231: Advance P2; set K010/011 (Main Control
Priority); input H220.
N050: P2 to PI; input H117; RNI at P + 2 is in progress.
If Channel Busy. For this case, if i/o with A, three timing elements will be running simultaneously. This
timing chart will not show the transfers associated with the Main Control timing but Main Control times will be
listed to the left of the Block Control times.
TIMING CHARTS (Cont)
N161/V151: Input H152, H014; if Word Addressed instruction (Backward + 3307 selected)
Word Addressed instruction (Straight
Transfer + Character Addressed Instruction (12 to 24), set K368/369 (Force
Character Address); set K180/181 (Program Load S).
N014-V152:
N239-V153:
Vl54: Set K170/171
(End of 1st pass)
The relationship of the timing shown below to Block
Control timh"'1g is an approximation.
G680, G682, G683, G686 pulse for 100
nsee, gate channel to SO lower 3. This is
the OR of DBR upper 3 and CIR.
Set Z332/333 (Start Delay Line), Z334/335
(Increment), Z 370/371 (Register File
Write), and Z390/391 (Register File Busy).
Record Activate at G642/G643/G644 by
forcing G643 = 1 (3 state FF) • Clear Z1.
(A3) E353: Read Current On, clear S2'
(A4) E351: DBR to Zl, AL3 to Zl, clear ZO, Block
Sense Amps to Z 1.
E388: Clear Z332/333 (Start Delay Line).
(A7) E356: Zl to ZO, Zl to S2, So to 81.
N217-V155: Input H150.
NOI4-V150:
N051- V151: Input H400.
N050-V152: Set K196/197 (Clear 0); input H401; set
K174/175.
Vl17-V153: SetK172/173 (2nd pass); clear DBR; input H410; set K048/049 (WCC) if (Read)
(Bit 20).
N050- V154: Clear KI98/197; EXX2 to DBR (F to r7 to
(A10) E357:
E359:
(B3) E355:
(B4) E367:
(B6) E365:
(B8) E363:
If Interrupt on Completion, set K192/193.
Block ZI to ZO (Increment/Decrement).
Clear Z1.
Force SO to IX.
ZO to Z1.
Write and Digit Currents On.
(C2) E368: Clear Z1.
EXX2).
V115-V155: Set K194/195 (Bus to 0).
(C5) E370: Read Current On.
(C6). E371: DBR to Z1.
Vl16-V156: Clear K180/181 (Program Load S); K170/
171 (End of 1st Pass), K172/173 (2nd
Pass), K152/153 (Program Request).
(C9) E376: SO to S1.
V061-V157: Clear K194/195 (Bus to 0), K174/175
(Read + Write)~ K048/049 (WCC).
VOOo-V158: Clear K168/169 (Program Priority).
RNI in progress at P + 3.
(D8)
(El)
(E6)
(E7)
E385:
E380:
E387:
E389:
Clear Z334/335 (Increment).
Write and Digit Current On.
Clear Z390/391 (Register File Busy).
Clear Z368/369 (Modify Address), Kl64/
165 (Read + Write)~ K176/177 (Gate Channel 0), and K15X Channel Designator FFs
and Drop Channel Enable.
383
TIMING FOR ACTIVATE SEARCH OR MOVE BUFFER, 71 OR 72 INSTRUCTIONS
Timing begins at VOOS of the first RNI.
VOOS:
V009:
VOlO:
VOll:
VOSO,
EXX2 to Fl'
Test interrupt.
fuput to HOSO.
VlSO, V2S0: Set K152/l53 (Program Request), J179 is driven to a O. Block Control's Priority Scanner
will eventually recognize the request by hanging up with Z300/30l and Z302/303 in their set state. J799
= 1, delay Y95l = 1, Resync via H170/l71.
fuput to H016; set K16S/169 (Program Priority Granted).
Set KOOO/OOI (Bus Request); input to H231.
Set KOlO/Oll (Bus Priority); Advance P 2 ; input to H220.
fuput to Hl17; P 2 to Pl'
Set Kl16/117 (Storage Request).
Input to Hll5.
Set K012/0l3 (Enable Data Bus); input to Hl16.
Test Breakpoint stop if BPI selected.
Resynced Storage Reply; set K060/06l (4S-bit 1st cycle). This blocks Sensing for all interrupts.
Clear KOOO/OOL
V17l:
V014:
N05l:
N050:
Vl17:
N050:
Vl15:
Vl16:
V06l:
VOOO:
VOOl:
V002:
V003:
V004:
V005: Set K062/063 (4S-bit 2nd cycle).
V006: fuput to H40l; Block fuput to H20l.
V007: Clear KOlO/Oll, K012/013, Kl16/1l7, DBR; input to H4l0; Block Input to H200.
cleared.
VOOS: EXX2 to DBR. NOTE: EXX2 to Fl does not occur.
V009:
VOlO:
VOll: fuput to H080.
VOSO, VlS0, V2S0: Input to H151; if S/M is not Busy, set KlOS/109 (Skip).
Timing for S/M Not Busy is continued on next page.
Timing for S/M Busy:
V15l, N15l: Input to H014 •.• Input to H156.
V014: Set KOOO/OOI (Bus Request); input to H231.
N051: Set KOI0/0ll (Bus Priority); advance P 2 ; input to H220.
N050: fuput to Hl17; P 2 to PI; RNI atP+2 (effective).
Fl is not
below.
V156: Clear K152/153 (Program Request). (Priority
Scanner looks for BFR Request).
V157:
V15S: Clear K16S/169 (Program Priority Granted).
Block Control has been released and is free to
honor BFR Requests.
See next page for actual activation of a Search or Move Buffer.
384
NOTE:
The following sequence occurs at the end of the 2nd RNI Cycle providing Search/Move Control is not Busy.
N151: Input to HOI4.
V151: Input to H152.
N161: Set K180/181 (Program Load S), G682/
G683/G686: 100 nsec pulses. Force 21 or 20
to So (JI71/G67X); set Z334/335 (Increment),
Z370/371 (Register File Write), Z 3 9 0/391
(Register File Busy), Z332/333 (Pulse Generator) a...l1d Clear Zl; Record Activate at G642/
G643/G644.
(VOJ.4) V152:
(H239) V153:
(N226) V154: Set K170/171
(End of 1st Pass)
(N229) V155: Input to H150.
(VOI4) V150:
(N051) V151, N153: Input to H400; if Search, clear
Z340/341, if Move, set Z340/341, Z342/343
(S/M Request), Z336/337 (S/M 1st Character),
and Z338/339 (S/M Busy). If (Move) (ml and
m2 designate character 0) (Character count =
XXXXX00 2 ), set Z330/331 (Word Move).
(N050) V152, N400: Input to H401; setK196/197 (Clear
(A3) E353: R~ad Current On; Clear S2.
(A4) E388: Clear Z332/333 (Pulse Generator).
(A4) E351: DBR to ZI; Clear ZO; Block Sense Amps
to ZI.
(A 7) E356: ZI to ZO' ZI to S2' So to SI.
(AIO) E359: Block ZI to Zo (Increment/Decrement).
(B3) E355: Clear ZI.
(B4) E367: Advance So to 3X (30 + 31).
(B6) E365: Zo to ZI.
0).
(VI17)VI53, N401: Set K172/173 (2nd Pass); clear
DBR; input to H410.
(N050) VI54, N410: Clear K196/197 (Clear 0); EXX2
to DBR (F to I7 to EXX2).
(VlI5) V155: Set K194/195 (Bus to 0).
(VI16) V156: Clear K180/181 (Program Load S),
K170/I71 (End of 1st Pass), K172/173 (2nd
Pass), and K152/153 (Program Request).
(V061) V157, V167: Clear K194/195 (Bus to 0).
(VOOO) V158: Clear K168/169 (Program Priority).
(VOOl)
Access and Decode time for RNI at P + 3 (effective).
(B8) E363: Write and Digit Currents On.
(C2) E368: Clear ZI.
(C5) E370: Read Current On.
(C6) E371: DBR to Zl; set Z354/355 ifbit 17 = I (DBR);
Block Sense Amps to Z 1.
(C7)E376: SOtoS I .
(D8) E385: Clear Z334/335 (Increment).
(El) E380: Write and Digit Currents On.
(E6) E387: Clear Z390/391 (Register File Busy).
(E6)
Block Control is free to honor incoming
request of highest priority.
385
SELF-EVALUATION QUIZ ON CHAPTER 15
TRUE OR FALSE OR FILL IN THE BLANKS:
1. Block control contains a word -organized storage
unit which has a
x
x
matrix .
10. The current address of I/O cycles is always a
character address.
2. Each time the register file is accessed, two read/
write cycles take place.
11. For 12 to 24 I/O operations increment/decrement
is by 28 ,
3. Locations 348 through 778 of the register file are
available to the programmer for temporary storage.
12. Block requests and program requests have equal
priority in accessing block control.
4. Location 228 of the register file could be used by
the programmer.
13. During the second RNI of an activate the transfer
of EXX2 to F1 does not occur.
5. Location 178 of the register file could be used for
temporary storage in many systems.
14. The upper 3 bits of address for activate instructions is obtained from the lower 3 bits of the A
register.
6. Both a search and a move may be in progress simultaneously.
7. The channel specified in coding an activate instruction is an absolute channel.
8. All 27 10 bits of a register file are accessible to the
programmer by means of the IRT instructions.
9. During buffer cycle the increment/decrement network is used to update a1l20bits of the current address.
386
15. The upper three bits of location IX of the register
file contain a modified code which specifies what
type of input/output is in progress.
Score Yourself:
You could miss one of these and still be considered
above average.
You could miss two and be considered average.
But if you missed more than two, don 't spread it around
because you Ire below average!
Figure 359. Communications Modules
CHAPTER 16
COMMUNICATIONS MODULES
GENERAL DESCRIPTION
Figure 359 is a front view of two Communications
channels. A maximum of eight channels may be attached to any single CPU. There are two types of I/O
channels available for the 3300 System. The 3306 is
a 12-bit bidirectional channel; a maximum of eight
3306s may be attached to a single CPU. The 3307 is
a 24-bit bidirectional channel; a maximum of four
3307s may be- attached to a single CPU. If present in
a system, 3307s will always be even-numbered channels. Each Communications module may contain two
I/O channels. Figure 360 illustrates the physical
position of the channels.
387
~
1_' I~ ,,~,,~ ,,,:::~;,, ., "
~ ..~OIlIITNHT
CONTROL
I'l108.
":IN
CONTROL
CONTROL
II CH
CH
CH
CH
0 I
2-3
4-5
6-7 P
1-
POWER
/I
N
I1IOOULE
E
L -_ _~_ _~L_ _ _ _ _ _~_ _ _ _-L~L~~~~L
Figure 360. 3300 Computer Physical Layout
Figure 361 is a block diagram of a Communications
module.
Figure 361. 3300
Communications
Module
Block Diagram
"----y-----I
CHANNEL
TO EXT
EQUIP
I
~
CHANNEL 0
TO EXT
EQUIP
3306 COMMUNICATIONS CHANNEL
FUNCTIONAL DESCRIPTION
Communication channels provide a buffer between the
computation section and various peripheral equipment
controllers. They prevent the computation section
from the external equipment. A program must go
through several instructions prior to exchanging data
with a piece of external equipment.
1. It must connect the equipment to the channel.
2. It must set up and direct the equipment with external function codes.
3. It could sense internal and external status conditions.
4. It must initiate a read or write operation.
A 3306 Communication Channel provides a 12-bit,
bidirectional, buffered, input/output path between the
processor and up to eight peripheral equipment controllers. Since there may be up to eight channels, one
processor may communicate with up to 64 controllers.
Each controller in turn may be attached to a number of
units. For example, the 3329 Magnetic Tape Controller
may be physically connected to eight tape transports.
This makes it physically possible for one processor to
communicate with 512 tapes, an unlikely situation, of
course. All data is handled in bytes (groups of 12 bits)
with one parity bit per byte.
OPERATION
An I/O module contains no indicators or controls,
so all operation must be initiated by the program via
the computation section of the computer.
PROGRAMMING
The 15 instructions listed in table 30 are directly
related to the I/O operations of a 3300 Computer. For
a detailed description of these instructions, refer to
the 3300 Computer System Reference Manual.
Table 30. 3300 I/O RELATED INSTRUCTIONS
OPERATION FIELD
77.3
77.3
77.0
77.2
77.2
77.1
73
73
75
75
74
INS
CINS
CON
EXS
COpy
SEL
INPC, INT, B, H
INAC, INT
OUTC, INT, B, H
OTAC, INT
INPW, INT, B, N
74
It-T,-~W:. . I~T
76
OUTW, INT, B, N
OTAW, INT
76
77.51 IOCL
ADDRESS FIELD
x, ch
x, ch
x, ch
x, ch
x, ch
x, ch
ch, r, s
ch
ch, r, s
ch
ch, m, n
~h
ch, m, n
ch
x f 0
x f 0
XfO
XfO
INSTRUCTION
Sense internal status
Copy internal status into lower 12 bits of A
Connect to external equipment
Sense external status
Copy external status into lower 12 bits of A
Select function of external equipment
Input character block to storage
Input character to A
Output character block from storage
Output character from A
Input word block to storage
!~EIJ.~ word to A
Output word block from storage
Output word from A
Selectively clear I/O channel
For specific function codes and status bits refer to the 3000 Series Computer System Peripheral Equipment Codes.
388
THEORY OF OPERATION
This area of the chapter describes the theory of operation of a 3306 Communication Channel. It is broken
down into six main parts:
1. Datarpaths
2. Parity checking
3. Status checking
4. Clearing circuits
5. Interrupts
6. I/O operations
The following paragraph is a rapid run -through of
the sequence of events. Figure 362 is a flow chart of
the sequence of events.
In response to programed instructions, the computation section connects an I/O channel and one of its
external equipments, and sets up the equipment for a
read or write operation with function codes. The chan nel then proceeds with the read or write operation, obtaining access to storage or A register via block control (in central processor) when necessary to fetch or
store information. The entire operation is performed
by block control and the channel, allowing the computation section to ~ontlnue its main program.
Central Processor
Choose to perform
I/O operation
I/O Channel
Block control and
3306 handle this
operation, leaving
central processor
free to continue
main program
Read or
write r=--:-----::-----::--:-----,
Connect a channel
Perform the read/
and a specific unit 1---.----...-,. write operation under
on that channel
channel control
Function
Perform the
function required
by the instruction
Exit
Central Processor
Under program control the central processor can be
1. Interrupted (if programmed) when the operation
is complete; or
2. The central processor can sense the status to
see if the channel is inactive, signifying the
operation is completed.
All data exchanged between a 3300 and its external
equipments is in the form of 12-bit bytes accompanied by one parity bit per byte. Odd parity is used exelusively. Six bit characters use only half of a channel
the lower six bits. All assembly and disassembly of
computer words is done by block control or the controller, not by the 3306.
Figure 363 is a more detailed flow chart of the sequence of operations.
DATA PATHS
In each standard I/O section, there is anevenand an
odd buffer (0) register, one for each 3306 Communication Channel. Each channel has its own set of receivers and transmitters between the 0 register and
external equipment jacks. However, the pair of channels in each I/O section share the set of receivers and
No
Figure 362. Generalized Flow Chart
of Operations
transmitters between the data bus and their respective
o registers.
There is one other data path. The prope r 0 registers
receive information from and transmit information to
the data bus. This is done by the circuits in figure 364.
Note that the communications channel uses common
transmitters back to the data bus just as the 0 registers receive from the data bus via common receivers.
A quick glance at figure 365 will convey what has just
been coveredo
Data which may consist of a connect code, a function
code, or an operand, is gated from the data bus (in the
processor) to 0 register (in the communication channel) by a signal from block control. The data moving
from the communications channel to external equipment (the (0) to external equipment signal) is contrGllled
by each channel. Input data is gated from external
equipment to 0 register by a signal within the channel (figure 366).
389
Program priority
granted
Request
program
priority
RNI and
decode
Transmit channel
enable to 3306,
drop clear enable
l-----..J
Drop connect
or function
Yes
Gate connect or
function code
from F register
to 0 register
Transmit connect
or function
Wait for external
equipment or
channel response
maximum 100 usec
External reject
or no response?
No
t-----I~
RNI at P + 2
Drop cQnnect
or function
Figure 363. Detailed Flow Chart of Sequence of Operation
TO
FflC~'_ :;SL 11
~()t>1-y----
J
I
111
O~
~61T~
f
I'lS 06
7
R507
8
1'lS08
i/JC7' ---t-j:'~
PS71~B
r
"'081-+---\}--i--~
2
1'521
I'lS 02
ti031
3
1'531
I'lS 03
Data bus in
central
processor
9
I'lS 09
10
1'lS10
~1J.l1
l'5u 1
I'lSIJ.l
216 01 -t---r--D-->I
01 1 1-t-D--+--~
21051
5
0551
I'lS 05
jil611
J680 J
II
~ BUS
EVE.N
1'lS11
..1681
J6B2
~BU5
ODD
~ ~ BUS
E.VEN
Figure 364. Data Bus Transmitter Logic
~J683
i1J -~
BUS
ODD
Data bus in
central
processor
STORAGE ADDRESS BUS
3309
STORAGE
MODULE
COMPUTATION
SECTION
CONSOLE
TYPEWRITER
3304 BASIC
PROCESSOR
Figure 365. 3304 Processor with Data Bus
Emphasized
BOTH CONTROLLED
BOTH CONTROLLED
....----. BY I/O CHANNEL..----..... BY PROCESSOR ~-~
EXT.
I/O
PROEQUIP.
CHAN.
CESSOR
Figure 366. I/O Data Flow
THEORY OF OPERATION
The normal operation of a program might be:
1. Connect a specific piece of peripheral "equipm"ent
to the channel.
2. Perform either a read or write operation.
In the next portion we will discuss in detail only the
even channel. Remember that the even and odd channels are identical in operation and each channel contains identical circuits. The circuits common to both
are the receivers and tramsmitters coming from and
going to the data bus in the central processor.
The following section will cover, by individual circuit
analysis, a connect or function operation on the even
channel and a write operation on the even channel.
Connect or Function Operation
When the central processor executes either a 77.0
or 77. 1 instruction the function translators (in the
central processor) will supply a constant control enable to the designated channel. This constant trans1ation of the 77.0 or 77.1 instruction (control enable)
will remain up until another instruction is read to F
register, which will start another RNI.
While the 77.0 or 77.1 instruction is being executed
several separate things must take place. For a quick
glance of what must take place see figure 367. Refer
back to this figure as the operation of a connect is
explained.
Figure 368 shows a function operation. Note the
similarity between connects and functions. Only ~
nect is discussed in detail in this manual. A function
operation is identical to a .;)nnect operation. A connect establishes contact or connection between the
processor and apiece of peripheral equipment. Afunction instruction accomplishes some function, such as
having a magnetic tape handler perform a rewind operation. The function operation may prepare the controller for certain controlling functions such as BCD
or binary mode, write a file mark, etc.
Function operation uses the same circuitry and the
responses to a connect are the same as to a function.
If a solid understanding of the connect operation is
obtained in the next few pages, understanding a function operation will be second nature.
The purpose of the connect operation is to establish
a connection to a piece of external equipment.
There are several signals that are transmitted to
the communications channel from the processor, during the execution of the connect (or function) instruction
Some signals are transmitted back to the processor
from the communications channel also.
A list of these signals with a brief description of the
purpose of each is supplied on the following pages
Read through them carefully to get the big picture.
Remember, the .basic operation to be performed is to
establish a connection between the processor and a
piece of external equipment.
0
Channel Control Enable: This signal comes from the
processor to one of eight channels to enable connect, function, and interrupt clear.
Channel enable: The signal comes from the processor
to one of eight possible channels.
Clear enable: Statically the signal is always here to
enable clearing the channel. It disappears now to
allow test for busy. Either the channel is busy or
not busy and the connection can or cannot be made.
Clear 0: This signal is from the processor and clears
the 0 register.
Bus to 0: This signal enables the information to come
from the processor to the channel.
Connect or function: This signal from the processor
tells which operation is to be done.
o to external equipment:
This signal from the channel relays the 0 to the controller. The connect
or function signal is relayed to the controller at this
time.
Reply: Signal indicating connect or function operation
has been accomplished.
391
I~7:±:17~1~0~13~1~2~1021~0::!::11~1''''41-----lnstruction in F
Connect channel 3 to equipment
via bus system
Function translators
2~
unit 1
,- ___________ 1
,
Channel desi nator
I
I/O device
1
I/O
I
I
I
I
BLOCK
--Connect signal------.t
onnect code and parity bit 1
CONTROL
CHANNEL I-----connect signal---~
# 3
reject or reply----;----''--_ _..J
--Channel enable (unique)
Control enable (unique)
1. With the instruction read and trans1ated' a request is made to block
control.
When priority is established, the
channel is checked for busy.
a. If busy, the next instruction will
be executed at P + 1.
b. If busy, - - - - - - - - - - '
4. The next instruction will be exe cuted at P + 2, and the status lines
will be enabled back to the channel.
1- _ _ _ _ _ _ _ _ _ _
3. The connect code and connect signal is sent to all of
the equipments on the channel.
Each equipment samples the
upper three bits (211, 210,
29 ) of the connect code and
system.---------~
compare them to its equipment select switch.
...4.------Reply - - - - - - - - - a. If comparison, the equipment will con n e c t and
send a reply back to the
channel.
If no response from any of the"'411---b. Ifnocomparisonoraparequipments within 100 usec,
ity error, the equipment
the channel will generate an
will disconnect and no
internal reject.
response is sent back to
the channel.
2. A connect signal is sent to all
channels. Only the channel
w h i c h receives the unique
channel enable will respond.
A 12 - bit connect code along
with a parity bit is transferred
to the I/O channel via the bus
The next instruction will be exe - 4---Reject
cuted at P + 1.
J
Figure 3670 Connect Sequence
Reject: Signal indicating connection is impossible at
this time (unit not ready, for example).
No response: Signal indicating connection is impossible (no unit exists, for example).
While the connect or function instruction is being
executed several signals are transmitted to the I/O
channel by the central processor. One of the first is:
1. Channei enable - The processor is executing an
input / output instruction and is enabling further
communications with this particular channel. Channel enable causes output of J074 = 1.
392
I
Channel reject---- If a multiunit equipment can·
not connect because a unit is
not present, a reject will be
sent back to the channel.
2. Clear enable - This signal drops at this time. Normally a constant clear enable is held at certain
circuits within the channel, but during communications with the processor this signal must drop to
allow valid checking of the channel busy.
Drop clear enable. R084 = 1 (see above).
NorE: When the computer is on, clear enable is
present at all times except when the processor is
checking for channel busy.
171711 13 -10) 01310 1'-- Instruction in F
Function translators
'"
Channel designator
Function signal-----...-.I
BLOCK
CONTROL
1/0
Interrupt on Ready and Not Busy
via Bus System
Function code and parity bit
CHANNEL 1 - - - - - - ~unction signal-----I~ EQUIP.
Channel enable (unique)
# 3
re ject or reply
Channel enable (unique)
#
*
*Previously connected
equipment
3. The function code and function signal are sent to all of
the equipments tied to the
channel, but only the previously connected equipment
will respond.
The function code is decoded.
a. If the function can be accomplished' a reply will
4. The next instruction will be ...4---------Reply - - - - - - - - - - - be sent back to the chanexecuted at P + 2 .
nel.
The next instruction will be ex - 4
Re ject
b. If the function cannot be
ecuted at reject address P+ 1.
Channel reject
accomplished, are j e c t
will be sent back to the
If no res po n s e within 100 ....411---- channel or no response
will be returned.
usec, the channel will generate
an
internal
reject.
Figure 368 . Function Sequence
1. With the instruction read and
translated, a request to block
control is made.
When priority is established
the channel is checked for busy.
a. If busy, the reject instruction at P + 1 will be read.
b. If not busy _ _ _ _ _ _ _.....1
2. A function signal is sent to
all of the channels Only the
one which receives the unique
channel enable will respond.
A 12 - bit function code along
with a parity bit is transferred to the channel via the
bus system. ________-.J
0
I
J[H(Jl/HZO-10,11)
(1)1'80-
6H13A
6f11A
)~_
EVEN CH~N EN~BLEI
6li15B
(I) T072---------;.~>____-____i.a
3. At this point the processor has tried to establish
communications with the channel. One of two things
could have occurred: either the channel is busy
and cannot communicate now, or it is not busy and
can communicate. The channel would be busy if it
were doing a read, write, or master clear.
READ
J[GOl /620-5,6)
(I) T073
CLEAR
E KTERt-IAL
I"IASTE.>l
CLE.AR
~
~I
II
.JCS01/G20-12,13)
{I)
6li15C
)
61-115A
6F16A
RE'lD IC60
TOB4---~)~~
::LEAR E"lABLE
Figure 369. 0 Register Enables
WRITE
>lEPL 1 8
>lEJECT
1-------4)>----
BlJ 51
Figure 370. Channel Busy to Processor
393
If channel not busy 0603 = 0) the central processor
will perform the following transfers to the data bus
transmitters: F to 17 to EXX2 to DBR to T5XX to
transmit the connect or function code to the channel. (The channel is not busy if it is not doing a
read, write, or master clear.) If channel busy,
RNI at P + 1.
Bus to 0 from block control (R072 = 0, J662 and
J663 = 1).
SIGNALS FROM PROCESSOR
BUS
--+
~
READ
4. Clear 0 register: This signal clears the 0 register in preparation for the arrival of information
from the data bus. On a connect or function it is
the unique 12-bit code that will accomplish the operation. Clear 0 register from the block control
(R073 = 0, J664 and J665 = 1).
------) >----.a
CLEAR"
CLEAR ~
--~)~~
IEVEN CHAN. ENABLE
Figure 373. Bus to 0 Register Enable
-----4)~
IEVIEN CHAN. IENABLE
Figure 371. Clear 0 Register Enable
When clear 0 pulse arrives (R073 = 0), and when
the even channel is enabled (R074 = 1, J605 = 0),
then the output of J664/665 is a logical 1, clearing
o register.
6. Connect or function: This signal comes from the
processor to the channel and then is relayed to the
controller to indicate a connect or function code is
on the lines.
Connect or function from the block control (R081
or R082 = 1 and R086 = 1 to cause J602 = 1).
-----4)~
CONNIECT
JOBI
BITS
R08Z
--~)~
R081
fUNCTION
J600
------})~
EVEN CONTROL ENABLE
Figure 374. Channel Preset Status
CLIEAR 0
•
..,
Clear 0
register
At this point the connect or function instruction
has been read by the processor and the connect or
function code has been sent to the channel. The
next action that must take place is the channel relaying the connect code to the external equipment
controller and then the controller reacting. J604
= 1, clearing K620/621, K608/609, and K612/613.
NO
RESPONSE
------) >---.-0
REJECT
rrnsr
CHAN. CLEAR + MC
( UNCONDITIONAL)
£'1IEN CHANNEL
CLEAR + MC
JI15
CHAN. CLEAR + MC+
(NO DATA SIGNAL) Ii
CHAN. TERMINATE
Figure 372. Clear 0 Register Enable
J604~
EKt RIEJECT
fK60el
KIZ4
l
ill.i!.-fS
,R071
5. Bus to 0: The signal comes from the processor and
enables the specific code from the instruction to
enter the 0 register in the channel. The clear 0
register signal will drop out at this time to allow the
entry of. the code to the 0 register.
391
R061
J604
.cr:-- i'!,07,~
~CC+MC+
~ (C+flaBUS-~
K60$
I
L----...I
PARITY
IERROR
J610
Figure 375. Reject and Parity Error
Clear Enables
--J
J604
Fl
--t K~15
.. J
7. 0 to external equipment: This signal comes from
block control to the channel. It enables the information (connect or function code) in the 0 register
to the external equipment.
K622/ 623 going set would cause a 1 on sense line 6 if
a sense instruction were executed, bringing J678 to a 1.
INT. STATUS _
SENSE L IflES
(EVEN CHAN.)
Bit
READ
INTER. STATUS
M218/
------7
M219/
------7~
I
J601
!II _
EXT. EQUI1'.
1C6Z2~~6
INT. STATUS _
tS -
SENSE LlflES
tOOD CHAfI.l
£XT. £QUI P.
J660
Figure 379.
ROl3
REPLY
Figure 376. 0 Register to External
Equipment Enables
During 0 to external equipment, J602 forces J612 to
0, J666 and J667 enable Oto external equipment. Only
one bit of the 0 register is shown.
After 0.2 usec, connect or function is sent to external equipment via T015 to TOI6.
J602
J661
SENSE LINES
To
external
equipment
Figure 377. Connect and Function Signals
Main control hangs up, waiting for one of the following three responses:
Channel Preset Status
T062 will transmit a reply to main control.
Figure 380. Reply on
Connect or Function
~:g~~(---
T---'
~::!
---o------J
REPLY ·Ofl
COtf
the 3306 and block control. The major points to
recognize in this area are:
a. The need for the 3306 to request entrance to
blockcontrol, which assures output of the word,
sends it to the 3306, and checks to see if it is
the last word.
b. The 3306 sends the word on to the controller.
c. The controller relays the word to the peripheral
eqUipment and generates a reply signal.
1) If this is ~ the last word the reply signal
will cause the channel to generate ..another
block control request. (Go back to 2a and
continue until last word.)
2) If this is the last word the reply signal cannot cause the channel to request block control because the channel is disconnected
from the processor.
The following area of circuit analYSis covers from
point B on in figure 39.1.
Block Control Services a Request
(The block control request was from T031 in first
cycle - -remember?)
1. Channel enable: R068=O, R074=0, J605 =0. The
actual circuitry will not be shown here because it
is identical to that shown previously. Refer back
to the first cycle of a write operation or refer to
the complete set of 3306 prints if you do not remember how it works.
/
Main program in
central processor
Set up block
control for
output
Execution
lstcYcle
of a write
operation
Set up output
circuits in
3306
Any instruction--4l---J
Next instruction
@
While the main program continues, the 3306 and block control
of the processor will accomplish the outputting of data to
0.
~
~
PROCESSOR
Block control request
3306 will generate a
block control request,
indicating it is ready
to receive data
r-c
• -1
~
Block control
busy?
,r
Enable channel and
transmit proper word
.,
~~
3306 retransmits
ord to controller
I
I
Disconnect channel;
only last word will
be transmitted
I
Yes
,r
~~
Controller relays word
to peripheral equipment
and generates a reply
~
Last word?
No
--
Data signal
l
Yes
Shut off
write controls
1
;,
'F
Reply
---
-
....
Figure 391. Graphic Representation of a Write Operation
2. Block control resume: R079 = 0, clear K602/603.
K614/615 will clear onthe trailing edge of the bus
to 0 signal. K602/603 going clear removes the
block contr-ol request from T031.
Figure 392.
Clearing the Block Control Request
3. Clear 0: R073 =0, J664 and J665 clear 0 register.
Again, the circuitry is not shown because it is identical to other clear 0 operations. 0 is being cleared
in preparation for output of the word.
4. Bus to 0: Transmitting the word to be output to
o register in the channel. R072 = 0, J662 and J663
enable bus to 0, parity bit to 0120/121; J635 = 1,
set K606/607 (data signal precondition).
The circuitry for a bus to 0 is not shown because it
has been covered previously. A parity bit is transmitted at this time; however, the circuitry for it will
be covered later when all of the parity circuits are
covered.
399
Reply From External Equipment - R013
CHANNEL ENABLE
J074
D.S.
PRECONDITION
DATA SIGNAL
K606
K60
= 1,
J606
=
1. 100 nsec later K610/611 is cleared, dropping the
REPLY
YO 3
data signal to the controller.
K610
K6O!i
J667~~
D~,IO
~~.....
~~~
K611
DATA SIGNAL
0.1 "SEC
K607
K611
Figure 397. Data Signal Transmitter
Figure 393. Data Signal FF Enables
The data signal causes J666 and J667 (enable 0 to
external equipment). 100 nsec later T017 = 1, data
signal.
TOil
--.Data to controller
J661
0--' EXT. EQUIP.
Figure 394. 0 Register to External Equipment Enable
P41A
K6O!J
J667~
K611
-
;:~~
D~,IO
"191~~D"TASIU"L
y~
O.I/LSEC
Read or write ... .J600
Reply
.~~-o-------------,
Channel terminate".,K
J(ROI/S44-12.131
~~R80-
~
~
Informs controller that
the data is on the lines
Figure 395. Data
Signal Transmitter
Now the two paths are sampled: If the channel were
not terminated when reply returned, K602/603 would
set and 100 nsec later K614/615 (lockout) would set;
T031 would send block control request, asking for more
data.
Refer back to figure 391. Remember that bl~ck control sent the word to the 3306 and determined if this
was the last word. The 3306 relayed the word to the
controller whether it was or was not the last word,
but if it was the last word the following would have
occurred.
Figure 398. Block Control Request upon Reply
External equipment drops reply (loss of the data
signal causes this operation). The actual circuitry
that drops the reply is in the controller.
J666 and J667 = 0, dropping 0 to external equipment
enable. At this point return to the area describing
block control services a request and redoes the cycles
until operation complete signal is generated.
If the channel was terminated when reply returned:
Operation Complete - (m1 =m2) or (r =s).
Bit
J087
TERMINATE
PRECONDITION
K611
TERMINATE
K624
K644
K625
K645
K615
Figure 396. Terminate FF Enables
Channel terminate FF is set. Continue on ifor a
'moment to see how channel terminate either allows
or disallows the next block control request.
The channel transmitted the word to the controller
and the controller must now respond with a reply signal. The return of the reply signal to the 3306 will
sample two paths: either the channel has not been ter.minated or it has been terminated. if it has not been
terminated, initiate a block control request; if it has
been terminated,' clear out the write controls.
400
Figure 399. 0 Register to
External Equipment Enable
Refer to the above circuit (see figure 398). It can
be seen that the block control request FF cannot be
set because K644/645wouldhavebeenset by the operation complete signal. All that remains is to clear
out write controls.
Clear K604/605 by J615. J666 and J667 = 0, dropping 0 to external equipment enable.
.1615
Figure 400. 0 Register to External Equipment Enable
1st cycle
of a read
operation
/
Main program in
central processor
~
instruction?
r------E----,
Set up block
control for
input
Any instruction
Next instruction -~----,--.....
@
Set up input
circuits in
3306
While the main program continues, the 3306 and block control
of the processor will accomplish the inputting of data to
@.
®
~306
+
will relay the
read controls to
the controller
3306 will generate a
.....
+control
r( Block
busy?
Yes
J
~Ir
6wee
Reply ... ;
.
Pick up information
from the lines and store
it at proper location
.-
End of record
wee
F igure 40l.
Read 0 pe ration
.....
4,.
'r
Controller will activate
input to peripheral
equipment and receive
word to input and either
Block control request
block control request
indicating the information is on the liJ;les
ready for input
I
~
Drop read controls
and terminate channel
This constitutes a complete write operation, from
the original execution of an output instruction to the
final termination of the channel. Refer back to figure
391 for a quick review of the operation.
It is important to recognize that the output operation
itself was handled independent of the central processor except for initiation and occasional needs for
memory references.
It is also important to recognize that it is the reply
signal from the controller that initiates another block
request, if one is necessary"
Another important item to note is that all of the circuit analysis has been on the even channel. There is
an odd channel, identical to the even channel, with its
own controlling circuits that can be operating at the
same time.
The even channel control logic diagrams may be
found on pages 7-3,5,7,9 and the even channel Oregister and status logic is on pages 7-19,21,23.
Leave read
control up
--
t
~,
No
Last
word?
re
s
~
-~
.~
Read Operation
A readoperation is very similar to a write operation. The biggest differences are in direction of
data flow and how the channel terminates.
Data flows are opposite. On output the flow of information is from the computer to the peripheral
equipment. On input operations, the flow is from the
peripheral equipment to the computer.
Channel termination on a write or output operation
comes from the computer when the starting and terminating addresses are the same. Channel termination may come from an end of record signal from the
external equipment or from the processor when the
addresses are equal.
Previous to any read operation there must be a connect operation. This connect sequence is the same
as the connect operation discussed previously so it
will not be discussed at this time. Remember, connect establishes a connection between controller and
channel.
401
Assume that a connect peration has been performed
and that the connection was made to the odd channel.
Assume that the next instruction is an input (read)
and that the instruction was made to an odd channel.
(The odd channel was selected for this description to
show the common circuitry between the odd and even
channels. )
Remember, the flow of information on input is:
External
equipment~ontroller----channel"'processor
Read through figure 401, keeping in mind:
1. Execution of an input instruction sets up the 3306
channel and block control. The processor goes
about accomplishing the remainder of the program
while the channel and block control handle the input.
2. a. As the words are read by peripheral equipment
and relayed to the controller, the controller
will signal the channel by a reply signal. The
reply signal is in response to the data s ignal by the channel. If the read controls stay
on, the input unit will continue to read information and send it to the controller. Each time
another word is ready to be sent to the channel
the controller will transmit a reply signal if
the channel is requesting data. This operation
continues until block control signifies that the
word that it received was the last one. This
signal causes the channel to terminate.
b. Another signal could be sent from the controller to the channel. This signal is called the end
of record signal and it literally means that there
is either no information to input or the input
information ran out before block control signaled
that the last word had been read in.
Channel Enable: R168=0, R174=0, J645=0. Drop
the clear enable; J 184 = O.
000 CHAN. ENABLE
~J645
Figure 402.
Channel Enable
T084---?~
CLEAR ENABLE
Read: J078 = 1.
Clear 0: Because the _actual clear 0 circuitry has
been shown previously it will not be shown here. Clecu
O'signal now prepares for the arrival of the information from the controller.
SIGNALS FROM PROCESSOR
J675
J'018
.. 610
~
EXT. EQUIF!:
J'
~nT' EQUIP._~
Y912
J641
A graphic representation of read is shown in figure
401. Read through it carefully. Notice the similarity
to the write (output) operation. Note the two ways that
the channel can terminate.
Assuming the connect instruction did receive a reply
and the next ins truction is a read instruction, the following signals will be developed upon the execution of
the input instruction. (Review figure 401 to point B
(first cycle).
1. Channel enable
I
L
I
Clear enable
i
2. Read
3. Clear 0
402
L---
n
~~
Figure 403. 0 Register Enables
__ EXT. EQUIP.
CP ___
EXT. EQUIP.
J641
The combination of read and clear 0 signals will
set K650/651. Note that the 0 to external equipment
signal cannot come up because of J641.
The set output of read FF will not enable external
equipment to 0 until the reply signal Q646) comes back
from the controller.
The channel preset FF will clearwhen read FF sets.
It was set by the connect operation.
Ci-t_""fl...
0·~o:'>r""",)pn' ... ,..
PRESET
i
K672
I
Figure 404. Clear Channel Preset
FF Enable
i
!
~
I
The set output of the read FF will become the read
signal to the controller.
T27A
01,2
K651~f--
READ
To controller
.1669
Figure 405. Read Signal to Controller
While the read signal is going to the controller, a
data signal will also be sent to the controller. When
K656/657 sets for the first time K660/661 and K690/
691 will also set. K690/691 will remain set until the
read is complete. K690/691 ANDed with K696 and J193
will transmit the data signal for a read operation.
BUS TO I/J ~ .1172
REAO
• K651
NOT TERMINATE ...... K694
~~
l. Channel enable
2.
r
L
o to bus
3. Clear 0
____________________~r_l~______
L
4. Operation complete
K656
09,10
Y669
.1193
DATA
SIGNAL
!'RECONDITION
The block control request is accomplished by setting K652/653 and transmitting a block control request via T131.
The reply signal or end of record signal from the
controller will clear the data signal FF .
Eventually block control will honor the request. The
following shows the timing for the reading of the information from the channel to the processor.
DATA SIGNAL
K657
Figure 406. Data Signal Enables
J063
The following is a description of figure 401 starting
at point B.
Eventually the peripheral equipment will have read
the word and relayed it to the controller. The controller will signal the channel via the reply signal indicating the input information is on the lines and ready
to be placed in 0 register.
5 . Bus to 0
-----"-
Block control services the request.
Channel Enable: J168 = 1, J174 = 1, J645 =0. The
actual circuitry will not be shown here. Refer to first
cycle of a read operation or a complete set of 3306
prints (off channel) for a review (p. 7-11,13,15,17).
o to Bus Signal: R079 =0, clears K652/653. K652/
653 going clear will clear K664/665 on the trailing
edge of the bus to 0 signal.
SIGNALS FROM EXTERNAL EQUIPMENT
,.I~~~
~~~
0.1 f'SEC
Read
~~~______________-,
R e p l y - - - - ~K694
Not terminate"""-----
K652
.1095
Figure 409. Block Control
Request Lockout Enable
o to bus:
.1170
.1671
.figure 407. External Equipment to 0 Register
Enables
J683 = 1 (moving the information from the
channel to the processor)o The 0 to bus signal will
remain up until R079 goes to a 1 .
.1645
When the channel receives the reply signal from the
controller it will request block control.
Channel Busy .-.----.-.1093
~ .1640 - 0 - - - - - - - - - - ,
Reply - - - ~ K694
Not terminate~
··"T"
0 --+ BUS (ODD C HAILI
Figure 410. 0 Register to Bus Enable
A clear 0 signal will then arrive. 0 is cleared to
prepare for the next word from external equipment.
8
.1645
Figure 408. Block Control Request upon Reply
Figure 411. Clear 0
Register Enable
R073
0580
0581
403
Refer back to figure 401. Remember that block
control received the word from the channel and determined if this was the last word . If it was the last word
the following would have occurred: Operation complete
(r or Ml = s or m2). If J087 = 1, set K694/695 terminate precondition.
J618~
K684WCC
K674
RI74
K695
K675
Figure 412. Terminate Enable
upon Operation Complete
K665
The set output of K694/695 will transmit a terminate signal to the processor.
IT063!l-----< f - - -
K611S
~
R.63
CHANNEL TERM'NATE
Figure 413. Channel Terminate Signal to CPU
The setting of K694/695 will not allow the block control request FF to set because of the zero on the AND
gate.
J640
~93-o---------------
K694
Figure 414. Blocking Block Control
Requests upon Termination
Read controls are shut off by the clear enable and
no channel terminate. The data signal FF will be prevented from setting by K694. The clear enable is up
all the time after the activate cycle.
The clearing of the read FF drops the read signal
that is constantly being transmitted to the controller.
The channel could be terminated by another method;
this is the end of record if WCC is not selected. The
end of record signal comes when the inputting device
has not found any information to input.
K684
wee
With the drop of the data signal, the EaR signal drops,
letting J091 set K674/675 (terminate FF). The read
FF clears when K674 = 0 and the channel operation is
complete.
WORD COUNT CONTROL
The word count control FF (684/685) allows the
channel to terminate only with the operation complete
signal from block control; not with the EaR signal
from the controller. This allows the programmer to'
read several records from tape or several cards from
the card reader with a single input instruction.
When an EaR signal is received (and WCC) the data
signal and the read signal are dropped momentarily,
but the corresponding FFs are not cleared and the
signals are re-enabled. The controller interprets
the new read and data signals as a new instruction and
initiates another read operation.
This constitutes a complete read operation from the
connect to the channel termination. Refer to figure
402 for a review of the read operation, paying particular attention to the block control request and
channel termination.
The only difference in the termination of the channels is how channel terminate FF gets set.
This is a complete read operation, from connect to
channel termination. Refer to figure 402 for a review
of read operation, paying particular attention to the
block control request and channel termination.
STATUS OPERATION
As was stated earlier, the central processor communicates with the I/O channel previous to actually
using it. One of the first things that could have been
done was to check the status of the channel or some
equipment on the channel. Checking the status of the
channel itself is called internal; checking the status of
equipment attached to the channel is called external.
(See figure 417.)
Figure 416 shows the connections of the status lines
to the processor.
1. Eight external interrupt lines. One from each controller, total of eight per channel.
2. Internal status for the channel (five lines, 0-4, 6,
7).
Figure 415. Terminate Enable upon
End of Record
When end of record ls received (and W-CC) the 'data
signal is up and the channel is waiting for a reply.
EaR .(J618) is ANDed with K684 (WCC) to clear K656/
657. This causes K660/661 to clear 100 nsec later.
404
3. External status for the channel, 12 external status
lines parallel to all eight controllers. (Only the
connected controller will enable its status to be sent
orrthe line'S.)
4. Appropriate sense enable received from processor.
S. Twelve sense lines for sensing internal or external
status from odd or even channel.
Channel internal interru t
®
Processor
Channel internal interr
t
Identical to channels 1 and 0
I
(
M
__------~J\~--------------__\
Figure 416. Status and Sense Lines
EXTERNAL SENSE SEQUENCE
I 7 t7 I 2 I 3 I 0 10
01 I 1......1 - - - _ Instruction in F;
'-----v-_J
~,--/
Function translatorf3_~J
sense equipment on channel 3
for ready and not busy.
Channel designator
Sense code
INTERRUPT
AND SENSING
SECTION
Sense enable (unique)
12 sense lines
I/O
CHANNEL
*3
EQUIPMENT
12 sense lines (static) =It:
~----------------~
*
*Previously connected
equipment
1. After the instruction is read and translated,
a sense enable is sent to the I/O channel via
the interrupt and sensing section.------------..
2. The 12 sense lines from the connected eqUipment
which are statically enabled to the I/O channel are
sent to the interrupt and sensing section.----,
The 12 sense lines are compared to the sense
code.
a. If any bit compares, the instruction at
P + 1 will be executed.
b. If no bits compare, the instruction at
P + 2 will be executed.
Figure 417. Graphic Representation of a Sense Operation
405
STATUS CHECKING
The communication channel status as well as the external equipment status may be checked by the program
in the computation section.
Internal Status
Internal status of the I/O channel may be checked by
the program at any time over seven of the 12 sense
lines which lead from the I/O channel to the computation section. Strobing is done by signals from the
computation section via 1678 Q679). The instruction
for this operation is 773 (ch)XXXX, where ch represents the I/O channel and XXXX is a mask of the conditions being checked. Bits 0-7 in the mask correspond to sense lines 0-4,6,7. Bits 5,8-11 of the mask
represent arithmetic faults within the computation
section. When:XXXX is 0, the internal status information is copied into the lower 12 bits of the A register.
SENSE
LINES
PARITY
ERROR
{
o
EYEN
000
{EYEN
READ
000
{
2
EYEN
WRITE
000
f
f
f
f
YEN
External Status
Status of the external equipment may be checked by
the program at any time over the 12 sense lines which
lead from the I/Ochannel to the computation section.
Signals on these lines have meanings which generally
are unique for each type of external equipment. The
instruction for this operation is 772 (ch) XXXX, where
ch represents the I/O channel and XXXX is a mask
used for looking at individual lines or groups of lines.
When XXXX is 0, the external status information is
copied into the lower 12 bits of A register During the
time that status is being strobed by the computation
section via 1684-5 0686-7), a 1 is sent to the external
equipment over transmitter (T022/T122).
The status circuits are extremely important to the
programmer. It is through these lines that the condition of the external equipment can be determined.
Other checks can be made from the sense lines which
reflect the condition of control within the channel.
These conditions are set by the appropriate signals.
The circuits for each and the sense lines affected are
shown in figure 420.
The parity error FF s can be set by two different
methods.
EXTERNAL
REJECT
YEN
NO RESPONSE
REJECT
40fl
4
ODD
6
YEN
CHANNEL
PRESET
ODD
7
YEN
CHANNEL
INTERRUPT
ODD
INT. STATUS ---+
SENSE LINES
(EVEN CHAN.)
1.
Parity error on connect and function codes works
the same as output or write.
TO
3304
ODD
0
Output or Write. The controller receives a parity
error during the output of the word from the channel. This is the external parity error signal and
comes from the controller.
2. Input or Read. The channel transmitted the (0)
register to the data bus in the processor and the
data bus generates a parity bit. This is transmitted back to the channel and compared to the
parity bit in the 0 register; if they disagree the
parity-error Fl"wilt set.
3
Logic Diagrams,
page 7-23
INT. STATUS----+
SENSE LINES
(ODD CHAN.)
Figure 418. Internal Status
PARITY CHECJ\ING
Parity is checked by one method for connect, function, and write operations and by a second method for
read operations.
EXT. STATUS ~
SENSE LINES
(EVEN CHAN.)
SAMPLE STATUS TIME
SENSE
LINES
11
EVEN
r
ODD
f
12 LINES
TOTAL
FROM
EXTERNAL
EQUIPMENT
Logic Diagrams,
page 7-23
TO 3304
j
EVEN
II
ODD
Figure 419. External Status
EXT. STATUS-+
SENSE LINES
(ODD CHAN.)
SAMPLE STATUS TIME
Sense line 0
Figure 420. Parity Error Status
Connect, Function, and Write
During the connect, function, and write operations
a parity bit is generated in the data bus circuit of the
computation section and is sent to the external equipment via 0120/121 FF in 0 register. A parity bit is
generated in the external equipment and compared with
the parity bit from the computer. If an error exists,
an external parity error signal is sent back to R016in
the 3306. This sets the parity error FF (K612/613)
and provides a 1 on sense line O. K612/613 is cleared
every time that an attempt is made to perform a connect' function, read, or write operation with this channel. (Not all equipments send parity signals on a connect operation. Refer to manuals covering specific synchronizer for details.) It may also be channel cleared
by the program or master cleared by the operator.
407
READ AND WRITE
Even
Odd
READ
~
~
WRITE
fOol
~
(X'[ REJECT
f08l
~I
EXT. REJECT
rmel
bJ
I
I
I
Sense line 1
Sense line 2
Sense line 3
NO RESPONSE
REJECT
Fl
bJ
J
Sense line 4
\
Sense line 5
Read
During a read operation, a parity bit is generated by
the external equipment and sent to the 3306 along with
the 12 bits of data. The parity bit is held in 0120/121
FF of 0 register while the data is forwarded to the
computation section. Parity is generated in the data
bus circuit of the computation section and is sent back
to the 3306. This new parity signal is compared with
the parity signal, being held to 0120/121, which was
generated by the external equipment. If an error exists,
setting of parity error FF (K612/613) is enabled by a
bus to 0 signal from the computation section. This
provides a 1 on sense line O. K612/613 is cleared
every time that an attempt is made to perform a connect,
function, read, or write operation with this channel. It
may also be channel cleared by the program or master
cleared by the operator.
The previous description shows that the condition of
the channels, either odd or even, internal or external,
can be determined through the use of a sense instruction.
INTERRUPTS
Consider for a moment the activate input or output
operation. If the activate instruction carries the appropriate other bits it is possible for the channel to
send an interrupt signal to the processor when the
operation is complete.
The following signals are identical to the ones presented previous to a read or write operation, with the
addition of an interrupt on completion signal.
Channel enable
I
I
Read or write Isignal
Clear enable
Read or write
CHANNEL
PRESET
rrnl
bJ
CHANNEL
INTERRUPT
~
~
CHANNEL
PRESET
1~
~
CHANNEL
INTERRUPT
poj
~
I
I
Ito
odd or evenILloc...hUila...o...ololooe.....J _ _ __
.;;:In::;t;.;e;:r;:r~u;.cp;.;:.t..;o;.:;n:....;;;.co.;;;.m==.Ep;.;l.;;;.e.;;.;te;;..-._--'~times
..;:C;.:.le.::.;a=r::;....;;O~_ _ _ _ _ _---'~times
Sense line 6
OJ 074 and J174 are channel enables.
Odd
Even
IN~UPT~ON
U
CO"PLETION ENABLE
a74
,J
Sense line 7
Figure 421. Internal Status
408
Activate
,
085
1<626
1<621
-
K625
JI74
JOBS
~676
P31
I
~
Figure 422. Channel Interrupt
K675
Other interrupt signals can be developed. The circuitry for each is shown below.
EXTERNAL INTERRUPT
ODD CHANNEL
EVEN CHANNEL
INTER.
LlNE
01,2
PIN
I
03,4
2
O~~~
r
PIN
01,2
I
~~~
I~~~
I/O Channel Interrupts
Each channel contains a channel interrupt FF whose
set output is monitored by interrupt control in the
computation section. This FF is set by the channel
terminate FF provided that the select interrupt on
completion FF has been previously set by the computation section. The select interrupt on completion F F
is set when bit 17 of the second word of an I/O (73-76)
instruction contains a 1. The channel interrupt FF is
cleared by either:
Each line
is from a
different
controller
E3.4
10
E5,6
II
6~~~
7~~~
E3.4
10
E5,6
II
passed directly to interrupt control in the computation
section via one of the receiver cards, R040-7, in the
communication channel. There are eight interrupt
lines per I/O channel, numbered 0-7, each corresponding to the equipment number switch setting on the
peripheral equipment controllers. This interrupt signal remains active until the computation section clears
it with a function code, or until the operator does an
external master clear.
~~~.
~~~
1. A programmed channel interrupt clear
2. An operator's external master clear
Figure 423. Interrupt Signal Circuitry
The select interrupt on completion FF will be cleared
if the channel is not busy and either:
Two types of interrupts are associated with an I/O
operation. These are the external I/O interrupts and
the I/O channel interrupts.
1. An IOCL or CLCA instruction is executed
2. Channel terminate is set (after busy drops)
3. An operator's master clear
External I/O Interrupts
The interrupt circuits in external equipment are enabled by the select function instruction 771(ch)XXXX.
If an enabled interrupt becomes active, a Signal is
CLEARING C IRC UITS
Figure 424 shows the clearing circuits in a 3300
communication channel.
CLEAR CHANNEL ACTIVITY
EXTERNAL
MASTER
CLEAR
EV CHAN CLEAR
K678
CHAN TERM
K624 --t--G.-t
BuS~0
K679
5 usee
CLEAR ENABLE
.1084
R071
CONN+FCN
J610
EVEN CHANNEL
ENABLE
R068
MC
-----::o-~
NOTE: The clear enable is present at all times that
the computer is on except for connect, function, and
activate read or write operations.
Figure 424. Clearing Circuits
There are other circuits within the 3306 that allow
assembly / disassembly, suppression of word mark,
etc. The theory of these circuits is left to the reader.
409
INTERRUPT
LINES
~
o
FROM
EXTERNAL
EQUIPMENT
R040
I
~
INTERRUPT CONTROL
(TO 3304 )
EIGHT LINES PER
CHANNEL TOTAL
I
7
~
~
Figure 425. External I/O Interrupts
CHAN.
ENABLE
CHAN. TERM. (FF)
INTERRUPT
ENABLE
CHANNEL
INTERRUPT
CHAN. INTER.
ON COMPLETION
CH,
K620
AN BUSY]
MC
MC+IOCL
INTE RRUPT CONTROL
(TO 3304 )
SENSE LINE 7
(TO 3304)
INTERRUPT CLEAR
EV CH CONTROL ENABLE
+ CLCA +TERM
(CHAN. CLR.
+ MC)
Figure 426. I/O Channel Interrupts
410
INPUT /OUTPUT CHANNELS Worksheet #1
Write the instruction which will accomplish each of the following operations, then answer the questions regarding each instruction.
Reference: Computer reference manual, instruction descriptions associated with I/O and interrupt, and 3306
theory text.
1. Connect tape handler 3 and controller 5 to channel 7 .
a. What signal would be transmitted to the processor if channel 7 were busy?
b. What signal would be transmitted to the processor if channel 7 were not present in the
system?
c. What would happen if there weren't a synchronizer designated as 5 on channel 7?
d. What would happen if there weren't a tape handler designated as 3 on synchronizer 5 on channel7?
2. Sense for channel 1 busy. What sense line would
carry the signal to the processor?
3. Provided that tape handler 3 on synchronizer 5 were
connected to channel 7, what instruction would sense
for that tape handler at load point? What type of
signal would be developed to indicate this?
4. Sense for illegal write. What sense line carries
the signalindicating anillegal write has occurred?
5. Clear channel 5 and its peripheral equipment.
INPUT/OUTPUT CHANNELS Worksheet #2
Any information you write on magnetic tape and then
read in is wrong. You know the read circuitry itself
is okay because you can correctly read tapes that were
written several days ago.
The fault appears to be in the write operation, somewhere between the processor and the 3306.
List the steps you would perform to localize the
trouble.
CLUES:
a. Remember, read operationworks, but write operation fails. Perhaps a comparison of the flow paths
for each would help eliminate some circuit::i:y that
is common to each.
b. The basic operation of the channel must be good
because you can connect to the proper unit for read
operations.
411
THEORY OF OPERATION FOR 3307 COMMUNICATION CHANNEL
The 3307 is a 24-bit bidirectional I/O channel which
must be an even-numbered chal1nel. The purpose of
the 3307 is two fold:
1. It facilitates convenient interface to a 24-bit I/O
device.
2. It halves the number of storage references required
when operating with ahigh speed 12-bit r!Odevice.
The first purpose of the 3307 is self explanatory
since the 3307 has a24-bitOregister and24 dataIines.
To understand the second purpose of the 3307, remember thatwith the 3306 a buffer cycle, which referenced
storage, was necessary for every data transfer. However, the 3307 has an assembly/disassembly feature
for word addressed I/O enabling assembly of 12 bits
to 24 or disassembly of 24 bits to 12, allowing the 3307
to initiate a buffer cycle for every other transfer
(74 + 76)(N = 0).
0
The 3307 uses odd parity exclusively. There is a
parity bit for the lower 12 bits of the 3307 and a parity
bit for the upper 12 bits.
In an I/O module that contains a 3307 and a 3306,
the clear 0 signal is used as a control signal only and
will not cause the 0 register to clear.
Refer to the 3300 Logic Diagrams, pages 7-27 to
7-39 for the 3307 control circuits and pages 7-49 to
7-55 for the 3307 0 register.
t---+-I..r:ONTROLLER
Figure 427. 3307 Data Flow on Output
(Without Disassembly)
3307 TIMING FOR WRITE NO ASSY /DSSY:
INSTRUCTIONS (75)(H = 0 + 1) OR (76)(N = 1)
Activate I/O Operation
1. Even Channel Enable (J310 = 1).
2. Drop Clear Enable (J308 = 0).
3. Clear 0 register signal (R300 = 0).
4. Write signal (J307 = 1) sets; Write FF K302/303
which sends Write signal to external equipment
(T306 = 1); Block Control Request Enable FF K366/
367; and Block Control Request FF K332/333. Set-
412
ting of K332/333 clears the Block Control Request
Lockout FF K362/363 and sends a Block Control
Request signal (T301 = 1).
5. If (75) (H = 0), suppress assembly / disassembly
(J314 = 1) which sets the Suppress Assembly /Disassembly Synchronizer FF K308/309 and sends a
Suppress Assembly/Disassembly signal (T313 = 1).
6. Wait for Block Control to service request.
Buffer Cycle
1. Even Channel Enable (J310 = 1).
2. Block Control Resume (J352 = 1), causing J456 to
generate a 1 for 100 ns. This clears the Block
Control Request FF K332/333 and the Block Control
Request Enable FF K366/367.
3. If operation complete, R313 = 0 which sets the Terminate Precondition FF K334/335.
4. Clear 0 Register (R300 = 0) which sets Block Control Request Enable FF K366/367 (if operation complete).
5. Bus to 0 Register (J301 = 1). This gates Data bus
to the 0 Register; static 0 to external equipment
transmitters; and sets 0 Loaded FF K340/341.
6. Trailing edge of Bus to 0 signal sets Data Signal
Precondition FF K342/343. After 100 ns this sets:
a. the Data Signal FF K344/345, which sets the
Block Control Request Lockout FF K362/363.
b. the Data Signal II FF K368/369, which sends a
Data signal (T309 = 1).
7. Wait for Reply from external equipment.
8. External Reply (R400 = 0, R450=1, J400 = 1, J451=1,
J452 = 1). This clears the 0 Loaded FF K340/341,
clears the Data Signal Precondition FF K342/343,
and sets the Block Control Request FF K332/333
(ifoperation complete). After 100 ns Y400 = 1 which
clears the Data Signal FF K344/345.
If Operation Complete
Repeat Activate I/O Operation, step 6.
If Operation Complete
1. Reply drops (R400 = 1). Afterl00nsJ450=Owhich
sets Terminate FF K336/337, clears K368/369,
and clears Write FF K302/303.
2. 100 ns after K302/303 clears, the Terminate Precondition FF K334/335 and the Terminate FF K336/
337 clear.
3307
-- ---
1
ODD BYTE
1
BUS UI2
0 U to Ox
TSXJ
0U
U I2
FROM STORAGE
BUS
CONTROLLER
T6X1
Ll2
~
i
0L to 0X
EVEN BYTE
-
-
--
76 (24 to 12)
---
Figure 428. 3307 Data Flow on Output (With Disassembly)
GENERAL FLOW FOR A 3-WORD OUTPUT ON A 76
(24 to 12) DISASSEMBLY (FORWARD)
Step 1: Activate 76 (24 to 12) Forward
a. Send Write signal to controller and request Block
Control.
b. Assembly/Disassembly counter = set, set.
c. Set 12-24 A/D.
Step 2: Serviced by Block Control
a. Bus to 0U/OL. 0u to Ox to T6X1 L12 .
b. Data signal to controller.
c. Assembly/Disassembly counter = clear, set.
Step 3: First Reply from Controller
a. 0L to Ox to T6X1 L12 (Assembly/Disassembly =
clear, clear).
b. Data signal to controller, request Block Control.
c. Assembly/Disassembly counter
set, clear.
Step 4: Second Reply from Controller
a. Assembly/Disassembly counter = set, set.
b. Wait for new word from Block Control.
Step 5: Serviced by Block Control
a. Bus to 0U/OL. 0u to Ox to T6Xl.
b. Data signal to controller.
c. Assembly/Disassembly counter = clear, set.
Step 6: Third Reply from Controller
a. 0L to Ox to T6X1 L12 (Assembly/Disassembly
counter = clear, clear).
b. Data signal to controller, request Block Control.
c. Assembly/Disassembly counter = set, clear.
Step 7: Serviced by Block Control
a. Bus to 0U/OL.
b. Send operation complete.
Step 8: Fourth Reply from Controller
a. 0u to Ox to T6X1 L12. (Assembly /Disas sembly
counter = set, set).
b. Data signal to controller.
c. Assembly/Disassembly counter
clear, set.
Step 9: Fifth Reply from Controller
a. 0L to Ox to T6X1 L12. (Assembly /Disassembly
counter = clear, clear).
b. Data signal to controller. (Don't request Block
Control if operation complete. )
c. Assembly/Disassembly counter = set, clear.
Step 10: Sixth Reply from Controller
a. Assembly/Disassembly counter = set, set.
b. Terminate operation, clear Assembly /Disassembly counter.
3307 TIMING FOR WRITE DISASSEMBLY:
INSTRUCTION (76)(N = 0) FORWARD
Activate I/O Operation
1. Even Channel Enable (J310 = 1).
2. Drop Clear Enable (J308 = 0).
3. a. Clear
signal R300 = 0 which sets Block Control Request Enable FF K366/367. This FF
clears the Block Control Lockout FF K362/363
and sends a Block Control Request (T301 = 1).
b. Write signal (J307 = 1) which sets:
1) Write FF K302/303, Sending Write signal
(T306 = 1).
2) Block Control Request FF K332/333.
c. Assembly/Disassembly signal (J317 = 1) which
sets Assembly/Disassembly FF K304/305 and
AOOO/001 and BOOO/OOL
4. Wait for Block Control to service request.
°
Buffer Cycle
1. Even Channel Enable J310 = 1.
2. Block Control Resume J352 = 1. This forces J456
to output a 100 ns logical 1 whic h clears:
a. Block Control Request FF K332/333.
b. Block Control Request Enable FF K366/367.
3. Clear signal (R300 = 0) and set Block Control Request Enable FF K366/367.
°
413
°
4. Bus to signal (J301 = 1 and R301 = 0). R301 gates
Dus to the
register. J301 sets the
Loaded FF
K340/341. After 150 ns, J462 outputs a 100 ns logical 1 which:
a. Gates 0u to Ox (OX to T static). This sets Suppress Word Mark FF K320/321 and drops Word
Mark (T310 = 0).
b. Sets the Data Signal Precondition FF K342/343.
After 100 ns, this sets the Data Signal FF K344/
345, K368/369, J462 outputs logical 1 for 100
ns which sends the Data signal (T309 = 1), clears
AOOO/001, and sets the Block Control Lockout
FF K362/363.
5. Wait for first Reply from external equipment.
°
°
First Reply
1. R400 = O. After 100 ns Y400 =1 which clears Data
Signal FF K344/345.
2. J451 = 1 for 100 ns. This:
a. Clears the
Loaded FF K340/341.
b. Clears the Data Signal Precondition FF K342/
343.
c. Clears BOOO/OOl.
d. Sets the Block Control Request FF K332/333,
which sends a Block Control Request (T301 = 1)
and clears the Block Control Request Lockout
FF K362/363.
3. J400 = l.
4. J452 = 1 for 150 ns, after which time
a. J454 = 1 for 100 ns. This enables 0L to Ox
(0 to T static), clears the Suppress Word Mark
FF K320/321 and sends Word Mark (T310 = 1).
b. Sets the Data Signal Precondition FF K342/343
(K352). After 100 ns, this sets the Data Signal
FF K344/345 (if Reply has dropped). J465 = 1
for 100 ns, which sets AOOO/OOl.
5. a. Wait for second Reply from I/O equipment.
b. Wait for Block Control to service channel. (In
this example, as sume that the Reply comes up
first. )
°
Second Reply
1. a. R400 = O. After 100 ns Y400 = 1 which clears
the Data Signal FF K344/345.
b. J451 = 1 for 100 ns. This sets BOOO/OOI and
clears the Data Signal Precondition FF K342/
343. (The 0 Loaded FF K340/341 is still clear
(J462 = 0); thus, 0u will not gate to OX' the
Suppress Word Mark FF K340/341 will not set,
the Data Signal Precondition FF K342/343 will
not spt. n~n the Data Signal FF K344/345 will
not set.)
c. J400 = 1.
d. J452 =- 1 for 150 ns.
2. Continue the wait for Block Control to service channel.
414
Buffer Cycle
1. Even Channel Enable J310
= l.
2. Block Control Resume- (J352 = 1) • This causes J456
to output a logical 1 for 100 ns which clears the
Block Control Request FF K332/333 and Block Control Request Enable FF K366/367.
3. Clear
signal (R300 = 0) and set Block Control
Request Enable FF K366/367.
4. Bus to
signal (J301 = 1, R301 = 0). R301 output
gates Bus to
Register. J301 output sets the
Loaded FF K340/341 and after 150 ns, J462 = 1 for
100 ns. The output of J462:
a. Gates 0u to Ox (OXto T static) which sets Suppress Word Mark FF K320/321 and drops Word
Mark (T310 = 0).
b. Sets the Data Signal Precondition FF K342/343.
After 100 ns, this sets the Data Signal FF K344/
345 which causes J465 to output a logical 1 for
100 ns and sends the Data signal (T309 = 1).
This, in turn, clears AOOO/OOI and sets the
Block Control Request Lockout FF K362/363.
5. Wait for third reply.
°
°
°
°
Third Reply
1. a. R400 = o.
b.
c.
d.
2. a.
b.
After 100 ns this causes Y400 = 1
which clears the Data Signal FF K344/345.
J451 = 1 for 100 ns. This:
1) clears the
Loaded FF K340/34l.
2) clears the Data Signal Precondition FF K342/
343.
3) clears BOOO/OOl.
4) sets the Block Control, Request FF K332/333
which sends a Block Control Request (T301 =
1), and clears the Block Control Request
Lockout FF K362/363.
J400 = 1.
J452 = 1 for 150 ns after which time J454 = 1
for 100 ns. This:
1) enables 0L to Ox (static Ox to T). This
clears the Suppress Word Mark FF K320/321
and sends.a Word Mark (T310 = 1).
2) sets the Data Signal Precondition FF K342/
343 (K352). After 100 ns, this sets the Data
Signal FF K344/345 (if Reply has dropped).
J465 = 1 for 100 ns which sets AOOO/OOl.
Wait for the fourth Reply.
Wait for Block Control to service channel. (Assume I/O equipment slow to reply and that Block
Control services request and send another 24bit word to the channel.)
°
BufferC;rcle
1. Even Channel Enable (J310
= 1).
2. Block Control Resume (J352 = 1), causing J456 to
output a logical 1 for 100 ns. This clears the Block
Control Request FF K 3 3 2 /3 3 3 which clea,rs the
Block Control Enable FF K366/367.
3. Operation complete (R313 = 0, J363 = 1, and J313
= 1). J363 sets Terminate Precondition FF K334/
335.
4. Clear Signal (R300 = 0). (Do not set Block Control Request Enable FF K366/367 since operation
complete is up. )
5. Bus to
signal (J301 = 1) and (R301 = 0).
R301
gates the bus to the Register. J301 sets Loaded
FF K340/341. Since Ox is holding 12 bits, J462
will not come up since BOO 0/0 0 1 is still clear.
Thus, no 0u to Ox transfer will take place until
the next (fourth) Reply is received from the channel.
6. Continue wait for the fourth Reply.
°
°
°
°
Fourth Reply
1. a. R400 = o. After 100 ns Y400 = 1 which clears
the Data Signal FF K344/345.
b. J451 = 1 for 100 us. This clears the Data Signal Precondition FF K342/343 and sets BOOO/
001. After 150 us, J462 = 1 for 100 ns since
the
Loaded FF is still set. The output of
J462:
1) gates 0u to Ox (OX to T static). This sets
the Suppress Word Mark FF K320/321 and
drops Word Mark (T310 = 0).
2) sets the Data Signal Precondition FF K342/
343. After 100 ns, the Data Signal FF K344/
345 sets. This, in turn, causes J465 to output a logical 1 for 100 ns and sends a Data
signal (T309 = 1). The output of J465 clears
AOOO/OOI and sets the Block Control Request
Lockout FF K362/363.
c. J400 = 1.
d. J452 = 1 for 150 ns.
2. Reply drops (R400 = 1). After 100 ns Y450 = 1 and
J450 = o. (Cannot set the Terminate FF K336/337
at this time since the Data Signal FF is set).
3. Wait for the fifth Reply.
°
Fifth Reply
1. a. R400 = O. After 100 ns Y400 = 1 which clears
the Data Signal FF K344/345.
b. J451 = 1 for 100 ns. This:
1) clears the
Loaded FF K340/341.
2) clears the Data Signal Precondition FF K342/
343.
3) clears BOOO/OOL
4) cannot set the Block Control Request FF
K332/333 since the Terminate Precondition
FF is set.
c. J400 = 1.
d. J452 = 1 for 150 ns. After 150 ns, J454 = 1 for
100 ns.
2. Reply drops (R400 = 1).
a. Enable 0L to Ox (static Ox to T) which clears
the Suppress Word Mark FF and sends Word
Mark (T310 = 1). The DataSignal Precondition
°
FF K342/343 sets, after 100 ns, this causes:
1) J465 = 1 for 100 us, which sets AOOO/OOL
2) Data signal to be transmitted (T309 = 1).
b. After 100 ns Y450 = 1, which causes J450 = O.
(Cannot set the Terminate FFK336/337 yet since
the Data Signal FF is set.)
3. Wait for the sixth (last) Reply.
Sixth Reply
1. a. R400 = O. After 100 ns Y400 = 1 which clears
the Data Signal FF 1\:344/345.
b. J451 = 1 for 100 ns. This clears the Data Signal Precondition FF K342/343 and sets BOOO/
001. After 150 ns J462 cannot output a logical
1 because the Loaded FF is set; therefore, the
Data Signal Precondition FF will not set.
c. J400 = 1.
d. J452 = 1 for 150 ns.
2. Reply drops (R400 = 1). After 100 ns Y450 = 1 and
J450 = O. This sets the Terminate FF K336/337
since the Data Signal FF is clear. J450 output
causes:
a. J866 = 1, which clears AOOO/001, BOOO/OOI and
K368/369.
b. J863 = 1 until the Terminate FF clears. J863
output clears the Assembly / Disassembly FF
K304/305 and clears the Write FF K302/303.
The Write FF, in turn, drops the Write signal
(T306 = 0). After 100 ns the Terminate FF
K336/337 and the Terminate Precondition FF
K334/335 clear.
°
Joe-G--I
R6X I
~U-.:.::12'--__-CONTROLLER
(Without Assembly)
Figure 429. 3307 Data Flow on Input
3307 TIMING FOR READ NO ASSY/DSSY:
INSTRUCTIONS (73)(H = 0 + 1) OR (74)(N= 1)
Activate I/O Operation
1. Even Channel Enable (J310 = 1).
2. Drop Clear Enable (J308 = 0).
3. Clear signal (R300 = 0) and Read signal (J306 = 1).
a. R300 sets the Block Control Request Enable FF
K366/367.
b. J306 sets:
1) Read FF K300/301 which sends a Read signal
(T305 = 1).
2) K310/311 if word count control.
3)
Unloaded FF K340/341.
4) Data Signal Precondition FF K342/343. This
FF sets the Data Signal FF K344/345 and,
after 100 ns, sets K368/369 which sends a
Data signal (T309 = I).
4. Wait for fir st Reply.
°
°
415
First Reply
1. a. R400 = O.
b. J451 = 1 for 100 ns. This clears the Data Signal
Precondition .F.F K342/343, clears the 0 Unloaded FF K340/341, and sets the Block Control
Request FF K332/333. FF K332/333:
1) clears the Block Control Request=L-o.....
ck..-o-u..,..t FF
K362/363.
2) sends a Block Control Request (T301 = 1).
3) after 100 us Y400 = 1, which clears the Data
Signal FF K344/345.
2. Wait to be serviced by Block Control.
Buffer Cycle
1. Even Channel Enable (J310 = 1).
2. 0 to Bus signal (J352 = 1) and J456 = 1 for 100 ns.
J456 output:
a. clears the Block Control Request FF K332/333.
b. clears the Block Control Enable FF K366/367.
c. gates 0U/OL to the Data bus.
d. gates OU/OL parity bit into 0716/717 and 0836/
837.
Trailing edge of 0 to Bus signal forces J455 = 1 for
100 ns, which sets the 0 Unloaded FF K340/341.
3. Clear 0 signal (R300 = 0). This sets the Block Control Request Enable FF K366/367.
4. Bus to 0 signal (R301 = 0).
a. R301 output controls the Check Parity Error FF
K328/329.
b. Trailing edge of the Bus to 0 signal forces J457
= 1 for 100 us and:
1) sets the Block Control Request Lockout FF
K362/363.
2) sets the Data Signal Precondition FF K342/
343.
3) set the Data Signal FF K344/345 if the Reply
is down for 100 ns.
4) send data signal (T309 = 1) if K344/345 sets.
5. Wait for the second Reply.
Second Reply
1. a. R400 = O.
b. J451 = 1 for 100 ns. This:
1) clears the Data Signal Precondition FF K342/
343.
2) clears the 0 Unloaded FF K340/341.
3) sets the Block Control Request FF K332/333.
This FF clears the Block Control Request
Lockout FF K362/363, sends aBlockControl
Request (T301 = 1), and after 100 ns causes
Y400 = 1 which clears the Data Signal FF
K344/345.
c. J400 = 1.
d. J452 = 1 for 150 ns.
e. J471 = 1 which gates the external receivers to
OU/OL·
2. 'Wait to be serviced by Block Control
416
Buffer Cycle
1. Even Channel Enable (J310 = 1).
2. 0 to Bus signal (J352 = 1 and J456 = 1 for 100 ns).
J456 output:
a. clears the Block Control Request FF K332/333.
b. clears the Block Control Request Enable FF
K366/367.
c. gates 0U/OL to the Data bus.
d. gates OU/OLparitybits into 0716/717 and 0836/
837.
The trailing edge of the 0 to Bus signal forces J455
= 1 for lOOns. This setstheO Unloaded FF K340/
341.
Operation Complete Signal
1. R313 = O.
2. J363 = 1 which sets the Terminate Precondition FF
K334/335.
3. Operation complete.
4. Clear 0 signal (R300 = 0). Cannot set the Block
Control Request Enable FF K366/367.
5. Bus to 0 signal (R301 = 0) which controls the Check
Parity Error FF K328/329. Trailing edge of the
Bus to 0 signal:
a. clears 0716/717 and 0836/837 for 100 us.
b. sets the Block Control Request Lockout FF
K362/363.
c. sets the Data Signal Precondition FF K342/343.
d. cannot set the Data Signal FF K344/345. This
causes the Terminate FF K336/337 to set, forcing:
1) J866 = 1, which clears K368/369 and the Data
Signal Precondition FF K342/343.
2) J863 = 1, which clears the Read FF K300/
301. After 100 ns the Terminate Precondition F F K 3 3 4 /3 3 5 and the Terminate FF
K336/337 clear.
No Operation Complete Signal
1. Operation Complete.
2. Clear 0 signal (R300 = 0). This sets the Block
Control Request Enable FF K366/367.
3. Bus to 0 signal (R301 = 0) which controls the Check
Parity Error FF K328/329. Trailing edge of the
Bus to 0 signal forces J457 = 1 for 100 ns. The
output of J457:
a. clears 0716/717 and 0836/837.
b. sets the Block Control Request Lockout FF
K362/363.
c. sets the Data Signal Precondition FF K342/343.
d. if Reply down for 100 ns, set the Data Signal
FF K344/345which sends aData signal (T309 =
1).
4. Wait for third Reply.
5. If (End of Record) (W:;;';-o-r-';d~C:::-o-u-n~t--::C:::-o-n~tr-o-;-I), continue
at number 1.
6. If (End of Record) (Word Count Control), continue
at number 2.
Number 1
1. End of Record signal (J402 = 1, R402 = 0, and J471
= 1. J402 output:
a. sets the Terminate Precondition FF K334/335.
b. cannot set the Block Control Request FF K332/
333.
c. clears the Data Signal Precondition FF K342/
343.
d. clears the a Unloaded FF K340/341 if ho Word
Count Control.
e. After 100 ns Y413 = 1 which clears the Data
Signal FF K344/345. End of Record signal drops
(R402 = 1). After 100 ns J450 = 0 which sets
the Terminate FF K336/337 if no Word Count
Control.
1) J450 output forces J866 = 1, clearing K368/
369.
2) Terminate FF forces J863 = 1, clearing the
Read FF K300/30l. After 100 ns the Terminate Precondition FF K334/335 and the Ter':"
minate FF K336/337 clear.
J471 output gates the external receivers to OU/OL.
Number 2
1. a. End of Record signal J402 = 1 which:
1) cannot set the Terminate Precondition FF
K334/335.
2) cannot set the Block Control Request FF
K342/343.
3) allows the a Unloaded FFK340/341 to remain
set.
4) after 100 ns Y413 = 1, clearing the Data Signal FF K344/345, and Y412 = 1, setting the
End of Record I FF K338/339.
b. R402 = O.
c. J471 = 1 which gates the external receivers to
OU/OL·
2. End of Record signal drops (R402 = 1). After 100
ns Y403 = 1 and J450 =0. The Terminate FF K336/
337 cannot set. The cleared Terminate FF:
a. forces J866 = 0, preventing K 3 6 8 /3 6 9 from
clearing.
b. forces J863 = 0, preventing the Read FF K300/
301 from clearing.
Y403 output:
a. sets End of Record II FF K346/347 and forces
J865=0, which drops the Read signal (T305=0).
b. after 100 ns clears the End of Record IFF K338/
339 and forces J865 = 1 which brings up the Read
signal (T305 = 1).
c. 100 ns after K338/339 clears, Y338 = 1 which
sets the Data Signal Precondition FF K342/343.
This, in turn, sets the Data Signal FF K344/345
and sends a new Data signal (T309 = 1).
d. 100 ns after the Data signal was sent, Y464 = 1
which clears K346/347.
3. Wait for the next Reply.
1st REPLY
DBR
R01X
Ll2
0x
EXT.
EQUIP.
TO SlORAGE
VIA BUS
2nd REPLY
Figure 430. 3307 Data Flow on Input
(With Assembly)
READ AND 12 TO 24 ASSEMBLY FORWARD
1. Activate 74 (12 to 24) Forward.
Send Read Signal to Peripheral Equipment.
Assembly/Disassembly Counter Clear, Clear.
2. First Data Signal to Peripheral Equipment.
Assembly/Disassembly Counter Set, Clear.
3. First Reply.
R16X to Ox to aU,
Assembly /Disassembly Counter Set, Set.
4. Second Data Signal to Peripheral Equipment.
Assembly /Disassembly Counter Clear, Set.
5. Second Reply.
R16X to Ox to OLD
Assembly/Disassembly Counter Clear, Clear.
Request Block Control.
417
I
~1
CH ENABLE:
CLEAR ENJI,ElL:e:
CLEAR 1\
Bus+1I
READ
I
~Jr-_-......!'}J------1r·J-;--~J~F-f----~JJ
I
~f
If
J1----f~, I
~S~-+_--'""'115_5-+_-_jI~S
II I
1J--.\-----If----f~H__
-----~ljj--~-~Jf5_'--~~J~~
IS
---~~~~--+-----~n~~I-~I~S
H I
WORD COU!!1T CONTROL
~
C:ONTROL K310/K3!!
READ FF KanO/K30!
I
I
_____~,~S---4--~r-~s
B. C. REQ1.::;S~; LOCKOUT K362/K363
SICl.PR~;CONDITION
K368/K369
1H------?~~
I
I~
I
I
II
.J
IS
IS
J~1----f1
I
I
B. C. REQt'::;S1: 1I:332/K333
DATA SIG.K344/K345
{s--f----l5---lSo_S------ff~
I
IJ-----fl
II
ALWAYS CLEAR
DATA
I
~~~~~$~~~~
~f
SUPP. W. NI. FF K3aO/K321
B. C. REQt'I!:S~r ENABLE K366/K3~7
f~
JH------?f----1~~
OPERA TION COMPLETE
caT,J\'I:r
:~J---fJ
----4~sr_-+--___jJ~~_+-_4~f_____1~: I
0+ BUS
WORD
I
L,{~--1-_-I!~$---f~S--.....,.G~fII-----if~1---f5
~
I
I
\~~f--------~S~~~J-f-----~HJ~-----------4--GII--+-~I}---1J
r~~J-----f/f---_---,rJ
1~~1 I
lS
-------jI~f---r----4Jl~~--~I~~
II~~
II I
I
n
1rt___4~~~------~I1~-I-------------:-I
I~rl--------~!~ ~~~f~---------jl~
.J
.J
I
\\--fr-J.---------IIH----,
. ~l-----f}______4~
H
GI-f-+--i'~lr--_ _ _-'r~I_______4~,
L,s
~~I-------//I~-~--~I~~I-----~II~I~Ir-----jJ~f----f1
--.J
!~~~r--J
II
¢ UNLOADlI::::> K340/K341
~
r--1
-----~IJ1--r_~~,
SS
I
~
~
r~
~
fH---,
I
L - - -_____W{/////.
I
~
I
~
Ijl~
If
I
TERMINAT,I:; PRJ!;CONDITION
------~Sl5_J----~----~J!~--~--_;S~rj----------~J1------_;!~~
TERMINAT,:; K336/K337
------~H~--+_----~~~----~$~!~--------~~~------~I.~~~j______~rl I
K338/K339
------~U~----~----i!fl------_;I}______4~j----------'!l~------_;Irt___4~~!----------!Slr'""'I~--~~---I---
K346/K347
DATA SIGN,.\L T30e
REPLY
------~fi5_S----~----~j}j------~I~!~--------~I.~l-I------j,~~~!----------ji~
~'
--~II__I~f-----'r~s__f______4~s
GI-l
___"UH_-+~r~1
IJ-.r~~l
If---{I
r~
If
~
I
E¢R
------~I,5_!----~----iJlI------~I~'~l----------+I\~-I----__4!~~sO_\--------~!I~
WORD MAliK
STATIC 1"
I
#~J-f------iJ~S__lI--_1J·ll-----fj
READ SIGrfA,L
ACTIVATE READ
lIST REPLY
BUFFER
CYCLE
2ND REPLY
I
BUFFER CYCLE
I
I
~r-I
I
~
E0R
TERMINATE IF WCC
CONTINUE IF WCC
75 OR (711) (24
~
CH ENABLE
r
CLEAR ENABLE
~~I--------~
L----\I
I
~rl----------____f I
I
I I
II
L
I
I
\
~
j
I
i
BUS - 0
~L
I
r
I
sr------IL-
WRITE
~
~Irl---------~I
If--
I
(f
CLEAR
~
sr----1L-
B. C. RESUME
S
~fJl----------i i
s
~r,
OPERATION COMPLETE
S
~·rS---------___4 S
I
I
,~~A.-
I-------{I
~f
I
I
II
S
~I
----f
WRITE FF & WRITE SIG.
SUPP. W. M.
B. C. REQUEST ENABLE
GATE BUS-+
-.J
I
-.J
!
~~~
~
s
S
~.~I-----Il___4 I
I/J
I
r--------S~f-S_ _---..JI~
DATA SIG. PRECONDITION
DATA SIG.
~;l-S-------~~
I,
I
~f-I-------~
~
K344/345 & DATA SIG.
K368/369
¢ LOADED K340/341
.1,
TERMINATE PRECONDITION
,
~~i----------~ I
TERMINATE K336/337
WORD MARK
L
ALWAYS CLEAR
K320/321
B. C. REQUEST K332/333
s
-.J
I
I
I
II
!
I
j
II
f
I
Ir-------IL-
r----{I
I
f-J
I
I
I
fl
I
II
~
I
S~
~
j
I
!~
s
U
I
II
~
ALWAYS A "1"
r----ll--,
REPLY
INITIA TE WRITE
1ST BUFFER
CYCLE
2ND BUFFER CYCLE &
~
TERMINA TE
f---fr----l
CM ENABLE
"
j---
¥---i
CLl!;AR ENABLE
CLEAR
~
I----i
"
BUS
-+ II
!---iT---
II -+BUS
~~
I
OPERA110N COMPLETE
r-+--i
I
I
ALWAYS CLEAR IF WCC
ALWAYS SET IF WCC
WORD COUNT CONTROL K310/K311
"
READ K300/301
SUPP. W. M.
I
B. C. REQUEST
"
B. C. REQUE8T~
B. C. REQUEST ENABLE
"
I
I
K320/321
"
-
I
"
I
~
I
I
r--!--i
DATA8IG.
K3>i4/345
I
I
I
~
I
J
I
I
I
1
~
.1
~
I
1
""
""
~
"
I
~
I
1
.1
I
~
"
K368/36S
I
~
1
DATA 8IG. PRECONDITION
I
I
H-4
"
I
I
7
I
GATE ~x -+ lIu
''':
l
I
I--t-i
I
I
~
I
I
I
1t~~s1
AOOO/OOI
$\%\\\\\%\%§§I\\\\%~1»\\\\~\\\\~\t)\~~\\\\\\\\\\~
1
BOOO/OOI
(«\\\\~««\«\~\<1\\\~\<<(1!it
~
I
II UNLOADED
~
I
TERMINATE PRECONDITION
r---Ir---
TERMINATE K336/337
~
-
I
DATA 81G.
READ SIGNAL
SS
«
REPLY
WORD MARK
"
"
T309
1'-
I
I
f----iL
~
l-----\
"
1ST REPLY
~
2ND REPLY
REQUEST B. C. &
REQUEST 3RD BYTE
SERVICED BY BLOCK CONTHOL
I
I
r-~r- l -
CH ENABLE
I
CLEAR ENABLE
r-~
n
CLEAR 0
BUS
Ij- I -
-+ 0
I
{f- +--
n
j
I/J -+ BUS
I
WORD COUNT CONTROL
~r- I-
ASSY/DSSY
~r- I -
WORD COUNT CONTROL/K310/K311
-.,J
1
WAIT
j
FOR
1ST
READ K300/K301
~
SUP. W. M.
r-~
s
S-- I
S
~
s
K320/K321
B. C. REQUEST K322/K323
B. C. REQUEST ~
B. C. REQUEST ENABLE
REPLY
I
~
S
I-- I
s
s
I
I
1--1
GATE (J)I/J I
>DATA BUS
DATA SIG. PRECONDITION
K344/K345
K368/K369
MOO/OOI
BOOO/OOI
T309
REPLY
WORD MARK
READ SIGNAL
!
~~
f-~
~~
~rJ
s
I/J UNLOADED FF
DATA SIG.
r-I
I
r--~
~W
,
---Ir- I-
I
r--l
f-~
I
s
s
s
I
j
I
S
1
s
S
24)
FORWARD
~r- l -
HEAD
DATA SIG.
74 (12
76
~~ Lr~
~f-
('II EX .. Bl.E
~
~S
I
H
S
~
S
IS
~
~
S
IS
S
'r--4
\
Ss
I
~
"
!
I
S--
S
{\
5
«
I
S
L
~S
"
s------1l-
"
~
~T -
WIllTE
I4} -
ASSY/l:.SSY
ENABLE
13. C. J'ESUME (0-BUS)
OPER), nON
LL
SUP. '1\.•
~1.
FF
I
~
I
K320/K321
R. C. l:E(;!UEST
LL
K3~~ -----s~~
~~ -----s~
ASSY,' 'SSY K30 4/K305
~~ -----4~
I
UATA, ;IG
I
~
I
K368/I': 36f!
I
S
I
!
I
"
I
~
~
1
J
I
\
I
!
S
~
(0 - T1 STATIC)
~~
I
I
x
WRIT!' SIG.
~I
~
WORD MARK
J
~
I
I
I
II
I
~
DATA HG.
S
{J
~I
~
I'i
!
\
I
\----fS
~s
~S
~l---II
~,
~s
~s
"
~
(0 - T STATIC)
1
x
,-H-
S
It
~
I
LOJi,DEJ FF K340/K341
\
~~
I
PRE CONDITION K342/K343
t
~
~S
~,;
.r-~~
S~
~
"
FF K344/K345
SI
L
~,
I
I
~\
I
I
I
IS
!
I
,
I
I
S
II
BOOO/FOOl
!~
\
-~~ -------1~
AOOO/" 00 J
I
~
~
I
'"G
K366/K367
B. C. ·(E.l;jUEST ENABLE
S
S
I
~
K362/363
tEQUEST ~
DATA;JG
~
I
co MPLETE
K302 /
WRIT!', YF K303
o
1~-------s!J
I
~~ f-----5f----S
CLEAH. 0
B. C.
.il
I
r~ ~~
I
CUI. '·NABLE
BIT 18
I
I
\
I---ir-------Il--
,
I
~I
~
'r---$\
;
I
~',
s
r - ~~
~S
~
~(;
----.J
TERlIILNATE P RECONDITION FF K334/K335
B. C. SERVICES REQUEST FIRST
TER11i1'NATE K 336/K337
BUFFER CYCLE 0U--0x-EXT.
1ST REPLY
REPL"
(PREPARE TO TERMINATE)
~~
2ND REPLY
REQ. B. C. &
ACTIVA TE WRITE
0 _ 0 x_EXT
(FAST I/O
EQUIP.
B. C. SERVICES REQUEST
~~_EXT
~
3RD REPLY REQ. B. C.
0-0-EXT
I
B. C. SERVICES REQUEST BEFORE
NEXT REPLY (SLOW 1/01
I
~
K302/K303
WRITE F. F.
1
sUP. W. M. FF K 320/K3 21
B. C. REQ. FF K332/K33
I
~
"
~
S
~
B. C. REQ. ~ K3 62/K31l3
~
I
S
I
l,
j
S
I
~
"".,..,
F.NAFlLE lOR 6/K367
ASSY/DSSY K304/K305
I
AOOOI AOOI
I
FloOO/FlOOI
~
I
t"'
I
I
DATA SIG. PRECONDlTION FF K342/K343
I
DATA SIG.
I
FF K344/K345
K36S/K369
°
1
LOADED FF K340/K341
GATE BUS _ ¢
~
GATE 0u_ ¢ x (0x_ T STAcrIC)
GATE ¢l-¢x ( ¢ x - T STATIC)
I
S
~
f
__ L.
I
~
~
I
r
WORD MARK SIGNAL
S
(J
WRITE SIGNAL
DATA SIGNAL
I
TERMINATE PRECONDlTI ON Fl' K334/K335
TERMINATE FF K336/K3 37
S
REPLY
4TH REPLY
0u-0x----- EXT
5TH REPLY 01-¢X-EXT
(PREVENT B. C. REQ.)
6TH REPLY
TERMINATE
Controller
INPC
H = 0
Controller
INPC
H= 1
I\ Zeros
C
I
C
33060
C
I
C
DB R
1
Memory
2
3
1
Controller
INPW
N= 0
3
12
1
2
3
Controller
INPW
N=1
C
C
t
33060
1
DBR
0
2
11
Memory
0
C
3
2
C
C
0
1
2
3
f
Memory
2
1
C
DBR
2
1
c
3306 0
C
3
Figure 137.
424
2
1
0
C
--===}2
~
0
1
I
33060
,
Zeros
o
C
::;
0
1
3306 Forward (73 OR 74) Data Flow
2
3
H=O
OUTC
OUTC
storage
Storage
0
DBR
DBR
1
0
3
2
~~ ~r
~
Zeros
C
C
i
Controller
Zeros
DBR]
2
3
J2
C
C
C
C
C
C
33060
Zeros
Controller
C
N=O
OUTW
Storage
1
0
1
"1------
DBR
DBR
33060
OUTW
Storage
H=l
2
3
~2
C
N=l
0
1
2
3
0
1
2
3
C
C
DBR
C
33060
33060
C
C
Controller
I
Controller
C
C
C
C
Figure 438. 3306 Forward (75 OR 76) Data Flow
425
INPC
INPC
H = 0
H=l
Controller
Controller
6 bits
6 bits
6 bits
6 bits
3307 0
33070
0
2
1
1
0
3
2
First
3
Last
DBR
DBR
0
1
2
0
3
1
2
0
3
INPW
2
3
1
2
3
1
Memory
o
1
INPW
N=O
N=l
Controller
1- -
6 bits
6 bits
I
I
Controller
-
- -
-
-
-
--
24 bit possible
6 bits
6 bits
I- - - - - - - - - -
~
3307 0
0
1
2
3307 0
3
DBR
1
2
3
I
Memory
0
1
3
Figure 439.
426
0
1
2
3
1
2
3
1
Memory
2
3
t
DBR
0
2
1
0
0
3307 Forward (73 OR 74) Data Flow
N=l
OUTW
Storage
Storage
1
0
2
3
t
DBR
1
0
3
t
1
0
ControHer
-
-
1
--
-
-
0
1
2
3
0
1
2
3
0
1
2
3
DBR
2
33070
I
N= 0
OUTW
33070
2
3
I
--
*
1
2
Control ler
I
I
I
24 Bit Possible
C
C
C
C
2
3
---------
OUTC
Storage
H=l
OUTC
Storage
1
0
2
1
DBR
Zeros
33070
Zeros
Zeros
*
Zeros
3
2
C
C
Controller
C
Figure 440.
=0
1
0
DBR
C
*
t
H
Zeros
C
33070
C
Zeros
Zeros
C
Controller
C
Zeros
C
3307 Forward (75 OR 76) Data Flow
427
Table 31. BIDIRECTIONAL SIGNALS
SIGNAL
DEFINITION
Data bits
Lines which carry data are bidirectional and perform as follows:
1. During a read (input) operation, data is transmitted from the external equipment
to the channel.
2. During the write (output) operation, data is transmitted from the channel to the external equipment.
3. The connect code and function code are transmitted from the channel to the external
equipment via the 12 data lines.
Parity bit
A parity bit accompanies each 12 bits transmitted between the channel and external
equipment. Odd parity is used, so the total number of l's transmitted is always an odd
number. Parity bits accompany the connect code, the function code, and each 12 bits
of data.
Table 32. SIGNALS FROM CHANNEL TO EXTERNAL EQUIPMENT
SIGNAL
Connect
DEFINITION
A 1 signal sent to external equipment when 12 -bit connect code is available on
data lines. If the equipment is available, it connects and returns the reply signal. If it is not available, it returns the reject signal. The connect signal and
code drop when the external equipment returns the reply or reject.
A channel may have a maximum of eight external equipments attached to its
set of I/O cables. Eight equipments receive the 12 -bit connect code and the
connect signal but only one equipment (the one which has an equipment number
switch setting matching the upper three bits of the connect code) will respond.
(The other equipments do not return reject signals.)
No response is returned by any of the equipments if the connect code contains
a parity error; however, the transmission parity error indicators on all equipments will light. After 100 usec delay the channel generates its own internal reject.
A connect code does not initiate action; it merely selects an external equipment. The upper three bits of the connect code select one of the eight possible
equipments attached to the channel, and the lower nine bits specify the unit(if any)
attached to that equipment.
A connect code matching its equipment number switch setting will be accepted
by an equipment if it is available, although it may be in the not reply condition.
The connect code will be rejected only if the equipment is already connected to
or reserved by another channel or is otherwise not available. The equipment will,
however, enable its status lines to the channel which attempted to connect, so
that the reason for the re ject may be determined by using the copy status instruction. The status lines remain enabled to that channel until it transmits another
connect code to any of its external equipments.
Once an equipment is connected to a channel, it remains connected until the
channel initiates a disconnect. Any connect code which does not match its equipment number switch setting will disconnect the equipment, including its status
lillei. Th.e -e.quilJmcnt ,must be ,-c flp.2.blc, o,f recognizing the corle
[tr~ di~sl::,onr£rting
less than 1 usec after receiving the connect signal. During selection the equipment must not return a reply or reject sooner than 2 usec after receiving the
connect signal.
428
Table 32 (continued)
SIGNAL
DEFINITION
Function
A 1 signal sent to external equipment when 12 - bit function code is available
on data lines. If the connected equipment is capable of executing the specified
function when it receives the function signal, it initiates the function and returns
the reply signal. If the equipment cannot perform the function, it returns the
reject signal. The function signal and code drop when the external equipment
returns the reply or reject.
The 12 -bit function code and function signal are received by the equipments
attached to the channel, but only the connected equipments will respond. If no
equipment is connected, the function signal and code will be completely ignored.
After a 100 usec delay the channel generates its own internal reject.
The specified function will not be performed if a parity error exists on the
function code; however, a parity error signal is returned by the connected eqUipment. Also, the transmission parity error indicator on the connected equipment
will light.
Once a function code is accepted, all other function codes will be locked out until the first one is acted on. An equipment does not hold or stack up the function
codes; a reply or reject is returned immediately. If the second function code
received is identical to the first, the second function code will be rejected unless the function can immediately be performed a second time.
Channel busy
Static 1 signal sent to external equipment while data channel is active during a
read or write operation. When the processor initiates the read or write operation the channel busy signal becomes 1 immediately and remains up until the
operation is finished and no further operation is specified. It does not drop
when an end of record signal is received unless the end of rec0rd actually terminates the operation.
When the channel busy line goes to 1 the connected equipment immediately
becomes busy (status response bit 1) unless it is already busy or is not ready.
If the equipment is still busy from a previous operation, it finishes that operation before beginning the new operation. The equipment does not become busy
if it is not ready; however, if the equipment becomes ready while the channel
busy signal is up, the equipment will become busy.
Read
Static 1 signal directing the connected equipment to begin reading information
from its storage medium and to continue as long as the read signal is present.
The read operation always starts at the beginning of a record. If the read
signal drops before the complete record is read, data transmission stops but
the external equipment continues its action until the end of record is reached.
If the read signal drops and comes back up within a record, data transmission
stops and does not begin again until the beginning of the next record.
Write
Static 1 signal directing the connected equipment to begin writing information
into its storage medium, and to continue as long as the write signal is present. The write operation always starts at the beginning of a record. Each
time the write signal drops, pxternal equipment automatically ends the record.
Data signal
A 1 signal used during read and write operations. Data signal drops when reply
(or end of record) is received from external equipment.
1. During a read operation the data signal indicates that the channel is ready
to accept data from the external equipment.
2. During a write operation the data signal indicates that the channel has placed
output data on the data lines.
429
Table 32. (continued)
DEFINITION
SIGNAL
Word mark
A 1 Signal sent to external equipment coincident with the data signal to indicate
the last byte of the computer word. The word mark drops when the data signal
drops (on receipt of reply or end of record).
Master clear
A 1 signal from the 3304 which returns channel and external equipment to 0
initial conditions and disconnects external equipment. Initiated by console
EXTERNAL MC or keyboard MC switches.
Com puter running
Static 1 when computer is running.
Suppress assembly /
disassembly
A 1 signal to the controller to force single character data transfers (73 + 75)
Clear external
interrupt
A 1 signal initiated by INCL instruction and transmitted by channel. Not used
by Control Data peripheral equipment.
Sample status time
A 1 signal transmitted by channel while it is gating external status to sense
lines. Not used by Control Data peripheral equipment.
(H
= 0).
Table 33. SIGNALS FROM EXTERNAL EQUIPMENT TO CHANNE L
SIGNAL
DEFINITION
Reply
A 1 signal produced by external equipment in response to a connect, function, or
data signal. Signal drops when connect, function, or data signal drops.
1. If connection can be made when connect signal is received, external equipment
connects and returns a reply.
2. If specified function can be performed when function signal is received, external
equipment initiates function and returns a reply.
3. During a read operation, external equipment sends a reply as soon as it has placed
data on the data lines in response to the data signal. During a write operation,
external equipment sends a reply as soon as it samples the data lines in response
to the data signal. (If end of record is reached during a read operation, the reply
is not returned in response to the data signal. Instead, the external equipment
transmits the end of record signal.)
Reject
A 1 signal produced by external equipment in response to a connect or function signal if the connection cannot be made or the function cannot be performed at the time
that the external equipment receives the respective signal.
End of record
A 1 signal produced (instead of reply) in response to the next data signal following
the end of every record during a read operation. The end of record signal drops
when the data signal drops.
If the read signal drops before end of record, neither the end of record signal nor
the remaining data in the record is transmitted although the external equipment continues its action to end of record. (This applies even though the read signal may
have dropped and come back up again within a record. See definition for read signal.)
Records of data written on magnetic tape are separated by blank spaces called
interrecord gaps. In the case of punched cards, each card is a record.
Parity error
A 1 signal produced if channel does not send an odd number of l's in 12 bits plus
parity bit. (A parity bit accompanies each 12 bits. The external equipment checks
the 12 -bit portion and if there is an error it sends the parity error signal.)
The following events occur when a parity error is detected.
1. Parity error on connect code:
a. No equipment will connect.
b. Any connected equipment will disconnect.
c. No equipment returns a reply or reject.
d. No equipment returns a parity error signal.
e. The transmission parity error indicators on all equipments attached to the
channel will light.
2. Parity error on function code:
a. Nothing happens if no equipment is connected.
b. If an equipment is connected, the following occurs:
1) It returns a parity error signal.
2) Its transmission parity error indicator will light.
3) It does not return a reply or reject.
4) It does not perform the function.
3. Parity error on data during write operation:
.a. Nothing happens if no equipment is connected.
b. If an equipment is connected, the following occurs:
1) It returns a parity error signal.
2) Its transmission parity error indicator will light.
3) It uses the data.
4) It returns a reply.
431
Table 33 (continued)
SIGNAL
Status bits
DEFINITION
The external equipment indicates its operating conditions by placing information on
the 12 status lines. Each equipment has its own particular set of status response
codes, some of which are unique to that equipment. However, several status indications are normally common to all equipments and therefore occupy the same bit
positions in the status response codes for all equipments.
Ready (bit 0 = 1)
An equipment is ready if, when properly connected, a read or write signal can
initiate a read or write operation. Conversely, equipment is not ready if, when
properly connected, a read or write signal cannot initiate a read or write operation.
Once ready, an equipment remains continually ready until operation is no longer
possible; it then becomes not ready. An equipment cannot become not ready while it
is actually transferring information; information transfer must first be halted.
Any equipment which requires manual intervention in its nonnal operation (such
as loading tape, cards, paper, etc.) is provided with switches to put it in either a
manual mode or a computer controlled mode. When in the manual mode the equipment is not ready. An equipment that has become not ready because of the need for
manual intervention automatically goes into manual mode. It becomes ready again
only after it has been attended to and manually switched back into the computer controlled mode.
Busy (bit 1 = 1)
Any equipment is busy when it is in operation. The equipment becomes busy
immediately on initiation of the read or write operation.
Normally, an equipment remains busy until it has finished all activity and is ready
to perform another operation; it then becomes not busy. However, an equipment will
become not busy if a condition arises due to which the equipment can no longer continue the operation. (An example of such a condition is becoming not ready because
of running out of cards, paper, etc. An equipment cannot be busy if it is not ready.)
Error (bit 10 = 1)
This signal indicates information errors produced and detected by the external
equipment. It does not indicate parity errors on information received from the channel; the parity error line is reserved for this. It is not an indication of malfunction
such as paper tearing or printed circuit card failure.
If a read or write operation includes more than one record, the error bit is not
cleared between records, but will indicate an error anywhere in the operation.
The error indication is cleared by beginning a new operation.
Reserved (bit 11 = 1)
This bit is used by multichannel peripheral equipment to indicate that the equipment is reserved by one of the channels to which it is attached. Once a multichannel
equipment has been connected by a channel, it remains reserved by that channel even
though the operation may terminate, the equipment may become not busy, and/or
the channel may connect another equipment. No other channel can communicate with
the equipment until the first channel releases the reservation. This may be done
using a master clear switch, the clear channel instruction, or by issuing the appropriate function code.
432
Table 33 (continued)
SIGNAL
Interrupt lines
DEFINITION
A 1 signal on an interrupt line indicates that an external equipment has reached a
predetermined condition. A channel may communicate with a maximum of eight
equipments and each equipment uses one interrupt line An interrupt signal may be
dropped by reselecting the same selection or by clearing the selection.
Each equipment has a set of conditions on which it will interrupt, if selected.
Some of the interruptable conditions are common to all equipment and are described
below.
0
Interrupt on End of Operation
With this selected, interrupt will occur the next time an operation ends . The operation may be in progress at the time of the selection or it may be initiated later.
Interrupt will not occur from an operation which has ended before the selection is
made.
Interrupt on end of operation can occur both at the end of an I/O read or write
operation and at the end of an operation specified by a function code. If a function
code is accepted to initiate an operation that is already completed, an end of operation interrupt will occur, if selected. An example is a function code to rewind
tape when tape is on load point.
Normally, the end of operation interrupt for a read or write operation will occur
when all data has been transferred, the channel busy signal has dropped, reading or
writing of the current record is completed, and all error checking is completed. In
some cases, this interrupt may occur before the equipment becomes not busy. If
for any reason (such as becoming not ready) the equipment is unable to continue the
activilY, the equipment will end its operation and interrupt will occur.
Interrupt on Abnormal End of Operation
This directs the external equipment to interrupt if an operation ends under circumstances other than normal, such as becoming not ready or detecting an error.
The operation may be in progress at the time of the selection or it may be initiated
later. Interrupt will not occur from an operation which has ended before the selection
is made, even though it may have ended under abnormal circumstances. However,
if the equipment has become not ready before the interrupt is selected, an attempt
to initiate another operation after the selection is made will cause the equipment to
interrupt immediately.
The equipment does not send the interrupt signal while information is being transferred. All activity and information transfer are stopped at the most consistent
point (such as at the end of the current record); then the interrupt occurs. Automatic stopping on an error takes place only when this interrupt is selected.
Interrupt on Ready, or Interrupt on Ready and Not Busy
This interrupt indicates that the external equipment is ready to start a new operation. It is often used to indicate the completion of any manual intervention.
433
SELF -EVALUATION QUIZ ON CHAPTER 16
TRUE OR FALSE OR FILL IN THE BLANKS:
3307s may be used in a sys-
10. The end of record signal may terminate an input
but not an output.
2. A channel clear will cause the channel to appear
busy.
11. The communications modules check parity for
every data transfer on a write operation.
3. The 3306 is a
-bit data channel and the 3307
is a
-bit data channel.
12. The 3307 is a truly independent buffer channel.
1. A maximum of
tern.
4. The communications modules have direct access
to the S bus.
5. The DB register has the capability of generating
two parity bits to facilitate operations on the 24 -bit
data channels.
6. The 3307 has assembly jdisassembly capabilities.
13. During a write operation the write signal pulses
with the data signal.
14. On 24 to 6 write operations work mark accompanies each data transfer.
15. When doing a 12 to 24 operation with the 3307,
block control will be requested for each data transfer.
7. The communications modules ignore word count
control on output operation.
8. The communications modules will generate an internal reject if no response is received from the
external equipment during a read or write.
9. The no response reject will occur 100 usee after a
connect or function if no reply. is received.
·134
Score Yourself:
None wrong is perfect, superior work
One wrong is above average.
Two wrong is average.
Three or more wrong is below average.
APPENDIX A
ANSWERS TO QUESTIONS IN VOLUME II
CHAPTER 4
Page 122, Self-Evaluation Quiz
1. False
11. False
12. False
2. True
13. 3 bit
3. False
If
False
14. True
"7.
15. False
5. False
16. True
6. True
17. True
7. True
18. True
8. True
19. False
9. False
20. False
10. False
CHAPTER 5
Page 146, Self-Evaluation Quiz
1L False
1. True
12. 128
2. False
13. 2 x 24 x.64
3. True
14. False
4~ 5
15. False
5. True
6. False
16. True
17. False
7. True
18. 12
8. True
9. True
19. True
10. False
20. True
CHAPTER 6
Page 171~ Self-Evaluation Quiz
1. False
9. True
2. False
10. True
11. False
3. True
4. False
12. True
13. F354
5. True
6. False
14. False
7. True
15. False
8. True
CHAPTER 7
Page 192, Self-Evaluation Quiz
1. False
9. False
2. True
10. True
3. False
11. False
4. True
12. True
5. False
13. False
6. True
14. False
15. False
7. 1112
8. EXX2, character, word
Page 204,
1. False
2. False
3. True
4. True
5. False
CHAPTER 8
Self-Evaluation Quiz
6. True
7. False
8. True
9. False
10. True
CHAPTER 9
Page 217, Self-Evaluation Quiz
6. True
1. True
2. False
7. True
3. False
8. False
4. False
5. True
9. False
10. False
CHAPTER 10
Page 234, Self-Evaluation Quiz
1. True
9. False
2. False
1{}. True
3. True
11. True
4. True
12. True
5. False
13. True
6. True
14. True
7. True
15. False
8. True
CHAPTER 12
Page 298-, Self-Evaluation Quiz
1. True
10. True
2. False
11. True
3. True
12. True
4. True
13. False
5. False
14. False
6. False
15. True
7. Depends on which
16. False
load instruction is
17. True
executed
18. False
19. True
8. False
20. True
9. True
CHAPTER 13
Page 348, Self-Evaluation Quiz
1. 3310, 4
11. True
2. 58, 57, 60, 63
12. Divide step, SWAP,
3. False
complement
4. K804/805 (optional
13. 618
arithmetic busy)
14. True
15. False
5. True
16. False
6. False
7. True
17. False
18. True
8. True
9. True
19. False
10. True
20. K872/873 (add exp 2)
CHAPTER 14
Page 363, Self-Evaluation Quiz
1. Abnormal Interrupt,
5. True
normal interrupt,
6. True
trapped instruction
7. True
interrupt
8. True
2. True
9. False
3. False
10. True
4. False
A-I
Page 386,
1. 2, 27,
2. True
3. True
4. False
5. True
6. False
7. False
8. False
CHAPTER 15
Self-Evaluation Quiz
64:
9. False
10. True
11. True
12. True
13. True
14. True
15. False
CHAPTER 16
Page
Self-Evaluation (}uiz
1. 4
9. True
10. True
2. True
3. 12, 24
11. False
4. False
12. False
13. False
5. True
6. True
14. True
7. True
15. False
8. False
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