60476010F_FA464_FA465_Cyber18_Tape_Controllers_Mar1983 60476010F FA464 FA465 Cyber18 Tape Controllers Mar1983
60476010F_FA464_FA465_Cyber18_Tape_Controllers_Mar1983 60476010F_FA464_FA465_Cyber18_Tape_Controllers_Mar1983
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60476010
&l c:\ CONTR.OL DATA
\::I r::!I CORPOR{\TION
CDC® MAGNETIC TAPE TRANSPORT
CONTROLLER
FA464, FA465
GENERAL DESCRIPTION
OPERATION
INSTALLATION AND CHECKOUT
THEORY OF OPERATION
DIAGRAMS
MAINTENANCE
PARTS DATA
HARDWARE REFERENCE/MAINTENANCE MANUAL
',-
.
REVISION RECORD
DESCRIPTION
REVISION
-~"' .
Manual released class A. This manual includes data previously contained in publications 89600271 and 89600866
A'
.'
(10/80)
which are obsolete.
Manual revised; includes ECO 05022022, providing a revised cable assembly drawing.
B
(1/81)
.: I , ~
C
Manual revised; includes ECO 05022126, providing clarification of the A-register bits and addition of an FCC non-tested
(9/81)
waminq label.
Manual revised; includes ECO 05022175, providing miscellaneous corrections.
0
(8/82)
E
f·
Manual revised; includes ECO 05022178, that eliminates double word transfers durinQ lonq record transfers.
(8/82)
!
F
!
(3/83)
~:.
....
-
Manual revised; includes ECO 05022253, removing the unnecessary FCC EMI non-compliance warning label.
~
..
·•
1
~
~.
•
&
Ii
;~
I~
t
T
,
I
\'
l
I.
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i
1
~
~
•
~
Publication No.
j
;
60476010
f;lEV1510N LETTER5 1,0,
i@
a, 5, x,
AND Z ARE NOT U5EO
1980, 1981, 1982, 1983
'py Control Data Corporation
~rinted in the United States of America
ii
Address comments concerning this
manual to:
Control Data Corporation
Publications and Graphics Division
4455 Eastgate Mall
5an Diego, California 92121
or use Comment Sheet in the back of
this manual.
( .
MANUAL TO EQUIPMENT LEVEL CORRELATION SHEET
This manual reflects the equipment configurations listed below.
EXPLANATION: Locate the equipment type and series number, as shown on the equipment FCO log, in -·····1
the list below. Immediately to the right of the series number is an FCC number. If that number and all,.~':
of the numbers underneath it match all of the numbers on the equipment FCC log, then this manual" ", .... !
accurately reflects the equipment.
,.... ,,'_.:
••,
•
'j
~
.. ;
~------------------~----------~----------~--------------------------------------..·i
EQUIPMENT TYPE
SERIES
WITH FCOs
COMMENTS
......
-
'.,
...-
I
. ~
....."-'" ... ~
FA464-A
04
FA465-A
02
FA465-8
02
;
.,.,,.,• •__ .
.,1
·-,·· .. ·1;
..... 1.:
60476010 F
iii/iv
i
!
!
'"
LIST OF EFFECTIVE PAGES
New features, as well as changes, deletions, and additions to information in this manual, are indicated by bars in the margins or by a dot
near the page number It the entire pago is affected. A bar by the page number indicates pagination rather than content has changed.
PAGE
Cover
Title Page
ii
iii/iv
v/vi
vii/viii
ix
x
xi
1-1
1-2
2-1 thru 2-3
2-4
2-5 thru 2-10
2-11
2-12 thru 2-15
2-16
3-1
4-1 thru 4-21
4-22
5-1 thru 5-11
5-12 thru 5-39
6-1
6-2
7-1 thru 7-16
A-l
A-2
8-1 thru 8-76
C-l thru C-99
Comment Sheet
Cover
60476010 F
REV
PAGE
REV
PAGE
REV
PAGE
REV
PAGE
REV
-
-
F
F
F
F
A
A
E
A
A
A
D
A
C
A
0
A
A
0
A
E
A
A
E
A
A
A
A
F
--
v/vi
PREFACE
This manual describes the Control Data~
F A464 and
F A465 Magnetic Tape Transport Controller (MTTC) used in
CYBER 18 Processor Systems. The MTTC interfaces the
CYBER 18 computer to the phase encode (PE) or nonreturn
to zero-inverted (NRZI) magnetic tape transport (BWI01,
BW303, BW305, and F A107) via a DZ101 Magnetic Tape
Formatter.
The magnetic tape formatter can interface with any
combination of one to four magnetic tape transports in a
daisy-chain configuration.
The descriptions, diagrams, and drawings contained in this
manual relate specifically to the F A465-A MTTC.
However, they are equally applicable to all F A464 and
F A465 MTTCs unless specifically stated otherwise.
The publications listed below provide more detalled
information relative to equipments, subsystems, and
systems.
Description
Publication No.
Basic Micro-Programmable Processor Hardware Maintenance Manual
39451400
CYBER 18 Computer Systems Central Processor Field Repair Guide
60475001
CYBER 18 Computer Systems with MOS Memory Installation Manual
96768360
CYBER 18 Computer System Overview Manual
60475000
CYBER 18 Processor with MOS Memory (Macro Level) Reference Manual
96768300
Magnetic Tape Transport (NRZI) Subsystem Field Repair Guide
60475041
Magnetic Tape Transport Subsystem, Dual Mode (NRZI/PE) Field
Repair Guide
60475042
60476010 F
vii/viii
CONTENTS
1
GENERAL DESCRIPTION
Physical Description
Functional Description
Reference Oata
Nonoperating Environment
2
,
"-
OPERATION
Controller Jumper Selection
Unit Protect (UPO - UP3)
Autoload Enable (ALD)
Single/Dual Bus (SB)
Bus Priority (BP)
Equipment Code (Q07 - QI0)
Controller Switch Selections
On/Off Line Switch
Maintenance Switches
Continuous Write Zeros
Continuous Write Ones
Continuous Read
Programming
Q Register
A Register
Output From A Operation
Interrupt Request
Bus Connect
Unit Select
Block Length
Director Function
Clear Controller
Load File Address
Self-Test 1
Self-Test 2
Self-Test 3
Self-Test 4
Assemble/Sense Next Ready
Assemble Ready Status
Sense Next Ready
Input to A Operations
Unit Ready Bit
Controller Busy
End-of-Operati on
Interrupt Response
File Mark
End-of-Tape
Corrected Error
Alarm (A03)
On-Bus and Bus Busy
Controller Protected
Alarm Status
Transport Status
Current Bank Status
Current Word Status
Block Length Status
A-Out Status
File Register Status
LRC and CRC Status
60476010 A
1-1
1-1
1-1
1-1
1-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-4
2-4
2-4
2-5
2-5
2-6
2-7
2-9
2-9
2-9
2-9
2-10
2-10
2-10
2-10
2-11
2-11
2-11
2-12
2-12
2-12
2-12
2-12
2-12
2-12
2-12
2-13
2-13
2-15
2-15
2-15
2-15
2-15
2-15
2-16
3
INST ALLA TION AND CHECKOUT
3-1
4
THEORY OF OPERATION
4-1
Format/Controller Interface Signals
Transport Address (TAOD, TAOI)
Initiate Command (GO)
Command Lines
Reverse/Forward (RE V)
Wri te/Read 0NR T)
Write File Mark ~M'"M)
Erase (ERASE)
Threshold (THR)
Spacing Mode (SPM)
Rewind (REW)
Off-Line (OFL)
Last Word (LIM))
Formatter Enable (FEN)
Wri te Data Lines (WO Through W7
and WP)
Low Densi ty (DEN)
Acknowledge (ACK)
Interface Outputs (Formatter to Controller)
Formatter Busy (FBY)
Identification (IDE NT)
Check Character Gate (CCG)
Hard Error (HER)
Corrected Error (CER) •
File Mark (FMK)
Transport Status and Configuration
Wri te Strobe (WSTR)
Read Strobe (RSTR)
Read Data (RO Through R7 and RP)
Command Reject (CRJ)
Data Transfer Error (TFER)
Read Mode Status (ROM)
NRZI Mode (NRZ)
7 Track (7-TR)
Microprogramming Concept
Ini tialization
A/Q Waiting Loop
A/Q Execute
Not-Busy Routines
First Word Address (CWA)
Bank Select
Load File Address
Block Length
Interrupt Request
A-Out Status
Current Word Status
Current Bank Status
File Status
Transport Status
Busy Routines
Director Functions
Space Forward
Search File Mark Forward
Backspace
4-~
4-1
4-1
'l-1
4-1
4-1
4-1
4-1
4-1
4-1
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-4
4-5
4-5
4-5
4-5
4-5
4-5
4-6
4-6
4-6
4-6
4-6
4-6
4-6
4-6
4-6
4-6
4-6
4-7
4-7
4-7
ix
Search File Mark Backward
Fixed Erase
Write File Mark
Read Data
Write Data
Controlled Backspace
Variable Erase
Autoload
Self-Tests
Off-Line Maintenance
Assemble/Sense Next Ready
Microinstruction Description
The Microinstruction Repertoire
Inter-Register Microinstructions
Load Constant Microinstructions
Jump Microinstruction
Jumping to Subroutines
Control Li ne and Set/Reset
Flip-Flop Instructions
4-7
4-7
4-8
4-8
4-10
4-10
4-11
4-11
4-12
4-13
4-13
4-13
4-13
4-13
4-16
4-16
4-19
5
5-1
DIAGRAMS
A/Q Interface
Input/Output Operations
Equipment Identi fleatl on
W Field
READ Signal
WRITE Signal
Sequencer Enable
Power-On Reset
Clock Circuit
Phase Generator
Sequencer
Reject Circuit
Reply Circuit
Microprogram Execute Circuit
Controller Reset
A-Output Register
A-Out Register Buffer
A-Bus Selector
4-19
5-1
5-1
5-1
5-1
5-1
5-1
5-1
5-1
5-1
5-2
5-2
5-2
5-3
5-3
5-3
5-3
5-3
5-3
Program Counter
PROM
B Register
Word Counter Register
File Address Register
Arithmetic Logic Unit
Parity Generator/Checker
Carry Out A B and Parity Latch
B-Bus Selector
Current Word Address Register
DMA Buffer
Buffer 1 Register
Buffer 2 Register
DMA Buffer Control
DMA Transfer Control
Dual Access to the Devices
Destination Decoder
Control Lines
Flip-Flap Network
Jump Condition Network
Uni t Protect Jumpers
Maintenance Switches
Jumper JM
Logic Diagrams
5-4
5-4
5-4
5-4
5-4
5-4
5-5
5-5
5-5
5-5
5-6
5-6
5-6
5-6
5-6
5-7
5-7
5-7
5-8
5-8
5-8
5-8
5-9
5-9
6
6-1
MAINTENANCE
Maintenance Philosophy
Operating Adjustments
Preventive Maintenance
Voltage Margins
A/Q-DMA Slot Pin Assignments
6-1
6-1
6-1
6-1
6-1
7
7-1
PARTS DATA
APPENDIXES
A
B
Operating Procedures
Flow Charts
A-I
B-1
C
Firmware List
C-l
Common Device Controller
Block Diagram
NRZI Write File Mark (7-Track)
Phase Encode Wri te File Mark
NRZI Read Operation
PE Read Operation
NRZI Write Operation
PE Wri te Operation
Microinstruction Groups
Subroutine Jump Instruction Sequence
Phase Pulses
Sequencer Pulses
Timing for Operation Mode of File
4-2
4-8
4-9
4-9
4-10
4-11
4-12
4-14
4-20
5-2
5-3
5-4
FIGURES
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
x
Magnetic Tape Transport
Controller (MTTC)
Typical System Configuration
Switch and Jumper Locations
A-Register Format for Unit Select
A-Register Format for Bank Select
Dynamic Status
A Register Format for Assemble/
Sense Next Ready
Read Status Format
A-Register Format for Status 1
Alarm Status A-Register Bi ts
A-Register Transport Status
4-1
1-2
1-2
2-2
2-6
2-6
2-10
2-10
2-11
2-11
2-13
2-15
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
5-1
5-2
5-3
60476010 A
5-4
r
1
7-2
Magnetic Tape Transport Controller
Logic Diagram
F A465-B Magnetic Tape Transport
Controller Spare Parts List
Magnetic Tape Transport Controller,
Assembly Parts List
7-3
5-12
7-4
7-2
7-5
7-3
F A465-B Magnetic Tape Transport
Controller Cable Assembly
Magnetic Tape Transport Controller
PROM Set
Magnetic Tape Transport Controller
Assembly Parts List
I
7-4
7-11
7-13
TABLES
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
4-1
4-2
Jumper Selection
Off-Line Operations
Q-Register Function Code
Density High/Low Select
Director Function Codes
Transport Stop Time
Formatter/Controller Bus Status
ESO Through ES4 Alarm Status
Transport Mode Code
File Usage
Director Function Command Coding
Source A Codes
60476010 E
2-1
2-3
2-4
4-3
4-4
4-5
2-6
2-7
2-8
2-13
2-14
2-15
2-16
4-7
4-15
4-6
4-7
4-8
4-9
5-1
5-2
5-3
6-1
Source B Codes
Destination Register Codes
ALU Control Code Inter-Register
Microinstructions
Jump Condition Codes
Flip-Flop Codes
Control Une Codes
File Register Usage
Off-Une Operation
Inputs from Formatter
Outputs to Formatter
A/Q-DMA Slot Pin Assignments
4-15
4-15
4-16
4-17
4-20
4-21
4-22
5-8
5-9
5-10
6-1
xi
1
GENERAL DESCRIPTION
The magnetic tape transport controller (MTTC) contains
the logic that: interprets the CYBER 18 central
processing unit (CPU) function codes, assembles and
disassembles the 16-bit words passed between the CPU
and the DZIOl-A magnetic tape formatter and provides
the magnetic tape transport (MTT) status information to
the CPU. The MTTC and the CPU communicate via the
A/Q channel for status, control information, and test, and
via the DMA channel for data transfer.
•
Four on-line self-tests are available for checking:
PHYSICAL DESCRIPTION
•
The MTTC, i,llustrated in figure 1-1, uses the concept of
microprogramming.
It
contains
TTL
(transistorto-transistor) Logic components mounted on one CYBER
18, 11- by 14-inch (279- by 355-millimeter) printed wiring
assembly (PWA) that occupies one A/Q-DMA slot in the
CYBER 18 processor chassis.
FUNCTIONAL DESCRIPTION
The MTTC, via the magnetic tape formatter, can control
up to four tape transports when the tape transports are
connected in a daisy-chain arrangement (refer to figure
1-2). A cable assembly connects the MTTC with the
formatter.
1.
Internal data paths and arithmetic logic unit
(ALU)
2.
Internal flip-flop and jump conditions
3.
Data read via the DMA channel and data
transmitted via the A/Q channel
4.
The A/Q channel data path
Off-line maintenance and test operation
REFERENCE DATA
Transfer Rate:
50 ips
Maximum transfer rate to the computer
is 40 kilowords per second.
25 ips
Maximum transfer rate to the computer
is 20 kilowords per second.
Density:
Low
556 bpi (7 track transport)
800 bpi (9 track transport)
High
800 bpi (7 track transport)
1600 bpi (9 track transport)
lhe MTTC, via the formatter, can handle any type of tape
transport in any sequence of densi ties. It can control
combinations of up to four MTTs having speeds of 25 or 50
inches per second (ips), 7- or 9-track, single or dual mode,
with densities of 556 or 800 bits per inch (bpi) for 7-track
transports, aDo bpi (NRZI) or 1600 bpi (PE) for 9-track
transports.
Power:
+5 V at 9 amps
Temperature:
40 0 F to 120 0 F (40 C to 49 0 C)
The MTTC has the following capabilities:
Humidity:
10 to 90 percent relative humidity with
no condensation.
•
Provides interface control for one to four MTTs
via the magnetic tape formatter
Warm-Up Time: None
•
Decodes the CPU function codes, selects the
MTT, and controls the tape-motion direction
•
Assembles, disassembles, and transfers data
between the CPU and the magnetic tape formatter
Temperature:
-30 0 F to 150 0 F (-22 0 C to 65 0 C)
•
Detects operation and transmission errors
Humidity:
5 to 95 percent relative humidity with no
condensation.
•
Provides the
information
60476010 A
processor
with
MTT
NONOPERATING ENVIRONMENT
status
1-1
F
H
J
K
p
N
R
•
•
s
.5
7
.
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•
...
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•
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fili lilli', iii II iIII iii ,i; iii ii'l i'i i,:iii I'll iii1'ii i\
...
111111111111111111111
2249
Figure 1-1. Magnetic Tape Transport Controller (MTTC)
CYBER18
COMPUTER
M
T
T
FORMATTER
C
2274
Figure 1-2. Typical System Configuration
1-2
60476010 A
OPERATION
This section describes the operating and maintenance
jumpers and switches of the MTTe. The section also
describes the programming instruction formats required
to f~.mction the controller.
2
AUTOLOAD ENABLE (ALD)
This jumper when inserted allows the MTTC to be the
autoload controller. When this jumper is removed, the
MTTe is disabled from performing autoload operations.
This operation is not supported in CYBER 18 systems; this
jumper must be removed.
The magnetic tape transport controller (MTTe) switch
and jumper positions are illustrated in figure 2-1. Table
2-1 indicates the jumper positions that designate
subsystem
address
and
enable/disable operational
functions. For information on the maintenance switches
that provide for selection of maintenance operations and
test conditions, refer to table 2-2.
SINGLE/DUAL BUS (SB)
This jumper when inserted indicates dual CPU access to
the magnetic tape formatter bus. For CYBER 18
operation, this jumper must be removed.
CONTROLLER JUMPER SELECTION
BUS PRIORITY (BP)
UNIT PROTECT (UPO - UP3)
There are four lI1it protect jumpers, one per tape
transport. To protect a transport, the jumper must be
inserted. When a protected tape transport is selected,
only status requests and protected instructions can access
the MTTe.
This jumper determines which controller gains control of
the bus when there are simultaneous bus requests from
both processors. Control goes to the controller that has
the jumper removed. When operating in a dual CPU
system, only one MTTC must have the jumper inserted.
This operation is not supported by CYBER 18 systems; the
jumper must be removed.
The MTTe, after being connected to a protected tape
transport, remains in the protected state until a deselect
instruction is received or an unprotected transport is
selected. Jumpers UPQ, UP 1, UP2, and UP3 select unit
protect function for transports MTTO, MTT1, MTT2, and
MTT3, respectively.
EQUIPMENT CODE (Q07 - Q10)
TABLE 2-1.
These four jumpers are used to represent any hexadecimal
number from 0 to F. They are used to assign an
JUMPER SELECTION
Position
Jumper Name
Function
, Inserted
Q07 - QlO
Determine equipment code
Logic 1
Logic 0
ALOt
Autoload enable
SB t
Single/dual bus access
UPO - UP3
Unit protect
Unit
protected
Unit
unprotected
SOO - S03
Not applicable to MTTC
BPt
Bus priority
JMt
Mode jumper
Removed
t Must always be removed for MTTC operations.
60476010 A
2-1
MODE JUMPER (JM)
TRACK DENSITY (SOD - SD3)
AND UNIT PROTECT (UPO - UP3)
Ll
BUS PRIORITY (BP)
s
SINGLE/DUAL BUS (S8)
EOUIPMENT CODE
(07 - 010)
AUTOLOAD (ALD)
ENABLE
2252
Figure 2-1. Switch and Jumper Locations
2-2
60476010 A
TABLE 2-2. OFF-LINE OPERATIONS
the on-line mode. If the unit is write-protected, no
writing is done. When an EDT marker is detected, the
controller terminates tape motion and exits from the
maintenance routine. All data transfer errors are gated
off.
MS2
~1S1
Off Line Operation Performed
(LS Switch Off)
On
On
Continuous write - O's
Continuous Write Ones
On
Off
Continuous write - l's
Off
N/A
Continuous read
This operation is the same as continuous write zeros
except that the data written on the tape is FFFF 16.
NOTE:
Place LS switch on while changing
MSl or MS2 switch conditions.
Continuous Read
equipment number to the MTTC. Any instruction sent by
the computer must be accompanied by an equipment
number (bits Q07 through QlO) that matches the setting
of the plugs. The W field must be zero.
The controller continuously reads data from the tape.
When the end of a record is reached, the controller will
read the next record. Tape motion continues until the
unit becomes not-ready, an EDT marker is detected, or
the controller is placed in the on-line mode. When an EDT
marker is detected, the controller terminates tape motion
and exits from the maintenance routine. Data transfer
errors and file marks are disregarded in this mode.
CONTROLLER SWITCH SELECTIONS
PROGRAMMING
ON/OFF LINE SWITCH
The MTTC communicates with the central processing unit
via the A/Q and direct memory access channels.
When in the on-line position, this switch enables normal
controller operation. When the switch is in the off-line
position, the controller is disconnected from the
controller CPU bus and is placed in maintenance mode.
The type of off-line operation that is performed is a
function of the maintenance switch positions.
Q REGISTER
The Q register designates the equipment to be referenced
and specifies the operation to be performed when an input
or output instruction is executed. The Q-register format
is shown below:
MAINTENANCE SWITCHES
Table 2-2 srows the available off-line operations selected
by maintenance switches MSI and MS2. Switches MSl,
MS2, and MS3 should be changed only when the on/off-line
(LS) switch is in the on-line position.
Switch MS3 determines the density at which the off-line
operation is performed. MSJ on indicates low density
operation; MS3 off indicates high density operation.
The off-line operation is performed on the first unit that
is ready, starting at unit O. If no unit is ready, the
controller aborts the off-line operation and remains busy
until the controller is placed in the on-line mode. The
unit on which the maintenance is to be performed should
be made ready prior to placing the on/off-line switch in
the off-line position. If the unit becomes not-ready
during the maintenance operation, the operation is
aborted. To restart the operation when the unit does
become ready, the on/off-line switch must be set to the
on-line position and then set again to the off~line
position. Placing the on/off-line switch in the on-line
position terminates the maintenance operation. The
controller remains on bus, but a new unit select command
must be issued.
The W field (bits Q15 through Qll) must always be zero.
The equipment field (bits
MTTC. These bits must
setting of the MTTC. The
by jumper conditions on the
QIO through Q07) selects the
match the equipment code
equipment code is determined
MTTC assembly.
Bits Q05 and Q06 are ignored by the MTTC.
Bits QOO through Q04 specify the function to be
performed by the controller in response to an input or
output instruction.
Refer to table 2-3 for the available functions and their
corresponding codes. Any code not appearing in table 2-3
is illegal.
.
When the CPU executes output instructions with the Q
register according to table 2-3, the controller loads the A
register with the requested controller status.
Continuous Write Zeros
The controller writes a continuous record of 000016 on
the tape until an end-of-tape (EDT) marker is reached,
the unit becomes not-ready, or the controller is placed in
Codes listed in table 2-3 as illegal are rejected by the
MTTC. Status reading and all operation initiation takes
place via the A/Q channel. Data is transferred via the
DMA channel.
,
'---
60476010 A
2-3
TABLE 2-3. Q-REGISTER FUNCTION CODE
Input
Output
Q04
Q03
Q02
QOl
QOO
1
0
0
0
0
Clear controller
Dynamic status
0
0
0
0
1
Director function
A-out status
0
0
0
1
0
First word address
Current word status
0
0
1
1
Bank select
Current bank status
0
0
1
0
0
Load file address
File status
0
0
1
0
1
Sense/assemble next ready
Transport status
0
0
1
1
0
Unit select
III ega 1
0
0
1
1
1
Block length
III egal
0
1
0
0
0
Bus connect
Illegal
0
1
0
0
1
Internal request
Illegal
0
1
0
1
1
Illegal
Illegal
0
1
1
0
0
Self-test 1
Illegal
0
1
1
0
1
Self-test 2
Illegal
0
1
1
1
0
Self-test 3
Illegal
0
1
1
1
1
Self-test 4
Illegal
0
•
The interrupt request command is rejected when the
controller is busy or if a protect fault occurs. The
controller does not become busy upon acceptance of this
command.
A REGISTER
OUTPUT FROM A OPERATION
All operations initiated by an output instruction, with the
exception of clear controller, are rejected if a protect
fault is detected or if the MTTC is busy. Clear controller
is rejected only if a protect fault occurs. Excessive noise
on the A/Q channel may cause valid operations to be
rejected.
The conditions for interrupt selected in the interrupt
request command remain valid for all subsequent
instructions. Master clear, clear controller, and clear
interrupts deselect all interrupts and deacti vate the
interrupt response.
Clear Interrupts
Interrupt Request
The MTTC generates an interrupt for the following
conditions:
•
End of operation (EOP)
•
Alarm
The interrupt request command allows the CPU to select
the conditions under which the interrupt response (signal)
becomes active. This command is also used for clearing
the interrupt response. The A-register format is shown
below:
IM1en bit A07 is set, all EOP and alarm interrupt requests
and status responses are cleared. Interrupt requests may
be cleared and deselected in the same interrupt request
command. The order of execution is to first clear all
interrupt requests and then select them according to bits
A05 and A04. If A07 is not set there is no change in
interrupt select.
Master clear and clear controller clear all interrupt
requests and responses. Bits AOa through A03 and AOa
through A15 are ignored by the controller.
EOP Interrupt Request
1!5
8
7
6
!5
..
3
2
I
0
A_lol~~
I
ALARM INT. R£O.
EOP /NT. REO.
~----CLEAA
2-4
INTERRUPTS
When bit A05 is set an EOP interrupt is enabled. An
interrupt is generated upon completion of an operation
that caused the controller to go busy. An interrupt
becomes active approximately 2 microseconds before end
of operation (EOP) status is set. An EOP interrupt is
generated, if one has been requested, upon completion of
any of the following operations.
60476010 D
•
Director function
Bus Connect/Release
•
Bus connect
•
Unit select
IM1en bit A07 is set the MTTC establishes bus control.
The MTTC is busy until bus control is established. The
mode of the connect is determined by A05.
•
T est modes 1, 2, 3, and 4
•
Assemble/sense next ready
IM1en A07 is cl~ar, the MTTC releases the bus. The
controller does not go busy for bus release. Clear
controller does not affect on-bus status. Master clear
causes a bus release.
Once enabled in the interrupt request command,
interrupts remain enabled for all subsequent instructions
until disabled by clear interrupt, clear controller, or
master clear.
If AOS is clear there is no change in EOP interrupt enable.
Alarm Interrupt Request
When bit A04 is set, an alarm interrupt is generated
whenever an alarm condition is detected. The interrupt is
sent 2 microseconds before the EOP status bit is set
regardless of when the alarm status bit is set. If the
alarm bit is active when an interrupt request command
with A04 equal to 1 is received, an interrupt is generated
immediately.
If A04 is clear there is no change in alarm interrupt
Bus Connect Requests
IM1en the bus connect request is active, bit AOS is clear.
The MTTC first checks bus and usage and goes busy. When
the bus becomes available, the MTTC gains control and
notifies the CPU by setting on-bus status and by
generating EOP status and EOP interrupt (if EOP
interrupt was selected).
A force release signal from the alternate has the same
effect on the MTTC as a master clear, except that EOP
and alarm interrupt requests are not affected by this
signal. They are cleared by master clear.
Unit Select
enable.
Once enabled by the interrupt request command, alarm
interrupt remains enabled until it is disabled by interrupt
clear, clear controller, or master clear.
The unit select command is used to select one of the four
tape transports. This command also selects operating
conditions for the selected transport. Figure 2-2 shows
the A-register format for unit select. Bits 4 and 5 select
the operational unit.
Bus Connect·
The magnetic tape formatter Cal be shared by two
MTTCs on a common bus. When it is necessary for the
MTTC to reference the formatter, exclusive control of
the formatter/controller bus must first be established.
The bus connect command is used for this purpose. The
A-register format for bus connect is shown below:
Unit select commands are rejected if the controller is
off-bus, a protect fault is detected, or the controller is
busy.
Select/Deselect
When bit A07 is set, the transport specified by the code
contained by bits A04 and AOS is selected.
8
,~
6
l
~
4
0
L ""CEO'H"""'"
- - - BUS CONNECT/RELEASE
The bus connect command is rejected if the controller is
busy or a protect fault occurs. Acceptance of the
command causes the MTTC to become busy until bus
control is established.
When A07 is cleared, any transport that was previously
selected is deselected. A04 and ADS have no meaning for
deselect. The controller does not go busy for a unit
deselect.
A master clear deselects all units.
If a change in operating conditions of the selected
transport is desired, a new unit select command must be
issued.
BCD/Binary Select
When the MTTC is off-bus (bus control has not been
established) and not busy, the following commands are
rejected:
\
"'---
•
Director function
•
Unit select
•
Transport status
•
Assemble/sense next ready
60476010 A
When bit A13 is set, binary coded decimal (BCD) format
(7-track transport only) is selected. Data is written onto
the tape with even parity and data read from the tape is
checked for even parity. In BCD format, the all-zero
character is illegal. If an attempt is made to write or
read an all-zero character, a parity error is generated.
When A13 is not set, binary format (7- or 9-track) is
selected. Data is written on the tape with odd parity.
Data read from the tape is checked for odd parity.
2-5
7
'-----OENSrrY HIGHIlOW SELECT
~
6
4
o
3
UNIT SELECT CODE
o 0 UNIT 0
o 1 UNIT 1
SELECT/DESELECT 1
0
UNIT 2
1
1
UNIT 3
2275
Figure 2-2. A-Register Format for Unit Select
For 9-track transports, AI) is ignored. Data is always
read/written in the binary format.
'M1en reading on a dual-mode transport, data is read in the
NRZI mode if no identification (ID) burst is detected, or
in PE mode if an 10 burst is detected regardless of the
state of AIS.
A master clear selects binary format. Clear controller
does not affect the format selection.
Density High/Low Select (AI5)
A PE tape without an 10 burst cannot be read in ·PE mode
on a dual-mode transport.
Bit AIS selects the higher or lower of the two available
densities (refer to table 2-4).
Bank Select
TABLE 2-4.
AlS
Density
9-Track
Dual Mode
(Bpi)
1
Low
a
High
The bank select command specifies one of four 65K banks
in which the address of the first word of a buffer is to be
found. The code of the bank is contained in A07 and A06.
Figure 2-3 shows the A-register format. Bank select and
the first word address together provide an IS-bit address,
allowing the first word of the transferred data buffer to
be located within 265K of memory. The bank select
command is rejected if the controller is busy or a protect
fault has occurred.
DENSITY HIGH/LOW SELECT
7-Track
(NRZI)
800 (NRZI)
1600 (PE)
556
800
Block Length
Density selection can be changed only when the transport
is at beginning of tape (BOT). If the density select is
changed when the transport is in the middle of a tape
reel, operations continue at the previous density selection
until the transport reaches BOT, at which time a switch is
made to the new density selection. A master clear
selects high density. Clear controller does not affect the
density selection.
1!5
The block-length instruction specifies the length of the
buffer to be transferred starting at the first-word
address. Bits 0 through 15 of the A register are used to
specify a maximum block length of 6SK.
Bank boundaries may be crossed during data transfers.
This command is rejected if the controller is busy or a
protect fault occurs.
8
7
~
6
0
A~~
BANK CODE
o
o
1
1
0
1
0
1
BANKO
BANK 1
BANK 2
BANK 3
2276
Figure 2-3. A-Register Format for Bank Select
2-6
60476010 A
Director Function
recovering errors when normal read fails. If it is not set,
it specifies a normal read.
The director function command specifies the operation
and motion that the selected transport is to perform. The
director function A-register format is shown below.
Table 2-5 details the director function codes.
Bit A07 is relevant only for write operations and specifies
whether an odd (1) or an even (0) number of tape words is
to be written.
o
With A07 set, only the upper portion of the last computer
word is written onto the tape. (The lower portion is not
written). This results in a record consisting of an odd
number of tape words.
I~
8
7
6
~
4
3
2
A~~/ ~II
WRITE 000
:=J
THRESHOLD LOW/NORMAL
FUNCTION CODE
(TABLE 2-5)
r~
I
{~
In this manner the record length to be written can be
specified in tape words rather than in computer words.
_ _ _ __
Completion of the motion function, master clear, or clear
controller selects normal read and write even.
Director function commands are rejected if the controller
is busy, off-bus, or a protect fault is detected. A master
clear or clear controller causes all transport motion to
cease.
Functions listed in table 2-5 as illegal should not be used
by the programmer. If an illegal code is received, the
MITC goes busy. Upon determining that the received
code is illegal, EOP status is set followed by not busy
status 1 microsecond after EOP. If an EOP interrupt was
requested, an interrupt is sent to the CPU. Illegal
director function codes act as NOPs.
Bit AOS specifies the read threshold. If A05 is set, it
specifies a lower threshold within the read amplifier for
The controller accepts a new motion function only after
busy status is cleared and EOP status is set.
Table 2-6 provides the transport stop times following read
and write operations for 50 ips and 25 ips tape speeds.
New motion functions in the same direction as a previous
motion received within the stop time interval is
performed without stopping.
Read Data
Two a-bit bytes are read from the tape and assembled
into one 16-bit computer word. Data is written into the
memory starting at the first word address and continues
until the number of words specified in block length has
TABLE 2-5. DIRECTOR FUNCTION CODES
Function
A03
A02
AOI
AOO
0
0
0
0
Read data
0
0
0
1
Space forward
0
0
1
0
Search file mark (forward)
0
0
1
1
Search file mark (backward)
0
1
0
0
Back space
0
1
0
1
Write data
0
1
1
0
Write file mark
0
1
1
1
Rewind
1
0
0
0
Fixed erase
1
0
0
1
Variable erase
1
0
1
0
Controlled backspace
1
0
1
1
Rewind off-line
1
1
0
0
Illegal
1
1
1
0
III egal
60476010 A
2-7
TABLE 2-6. TRANSPORT STOP TIME
computer word are wri tten on the tape. After completion
of the write, an interrecord gap is created on the tape and
tape motion stops. EOP and busy status operation are the
same as for read data.
COII111and
MIT Speed
Write
Wi th A07 = 0, both the upper and lower portions of the last
Read
Write File Mark
25 ips
15 ms
19 ms
50 ips
7.5 ms
12.5 ms
been transferred or the end of record is reached. Upon
acceptance of this command, the controller becomes busy
and remains busy until the next interrecord gap is
detected, after which EOP is set. Busy status is reset 1
microsecond after EOP.
The tape is erased forward approximately 6 inches (152
millimeters) and a file mark is wri tten on the tape. Upon
acceptance of this command, the controller becomes busy.
After writing the file mark, EOP status is set and busy
status is reset.
Rewind
If the first record following BOT is a file mark and not
data, the controUer does not continue to the next record.
The tape is rewound at high speed to load point. The
controller is busy only long enough to validate the
command and to initiate tape motion, after which EOP
status is set and busy status is reset.
Space Forward
Fixed Erase
The tape is moved forward until the next interrecord gap;
if a file mark is detected, file mark status is set. Upon
acceptance of this command, the controller becomes busy
until the next interrecord gap or file mark is detected,
after which EOP status is set and busy status is reset.
A 6-inch (152-millimeter) length of tape is erased, after
which tape motion stops. EOP and busy status operations
are the same as for wri te file mark.
Vari able Erase
Search File Mark (Forward)
The tape is moved forward until the next file mark is
detected. File mark status is set. The operation for EOP
and busy is the same as for space forward.
Variable erase allows a variable length of tape to be
erased. The length is controlled by the block length and is
equal to approximately twice the block length tape words.
After erasing the specified number of words, tape motion
ceases. EOP and busy status operation are the same as for
write file mark.
Search File Mark (Backward)
Controlled Backspace
The tape is moved backward to the previous file mark and
file mark status is set. If no file mark is detected, motion
stops at load point. The operation for EOP and busy is the
same as for space forward.
Backspace
The tape is moved backward until the next interrecord gap;
if a file mark is detected, file mark status is set. Upon
acceptance of this command, the controller becomes busy
until the next interrecord gap or file mark is detected,
after which EOP status is set and busy status is reset.
This feature allows the formatter to posi tion the tape back
to the previous interrecord gap for a record that has just
been written in error. The amount of tape words
backspaced is equal to twice the length specified in block
length. When the last tape word is backspaced, the
formatter goes through its normal termination sequence.
The result is the positioning of the write head 0.13 inch
(3.3 millimeters) ahead of its original position prior to the
erroneous record. This function provides a means of
reversing over dropouts without possible posi tioning errors.
The operation for EOP and busy status is the same as for
space forward:
Write Data
Rewind (Off-Line)
Starting at the first word address, 16-bit data words are
read from the memory, disassembled into two a-bit tape
bytes, and written onto the tape. This process continues
until the number of computer words specified in the block
length have been written on the tape. If a write odd
operation was specified (A07 = 1), writing stops after the
upper byte of the last computer word. The lower byte is
not written, resulting in an odd number of tape words in
the record. This feature allows record-length specification
to be done in tape words rather than in computer words.
2-8
High-speed rewind motion to load point is initiated in the
selected transport, after which the selected transport goes
off-line. The controller is busy only long enough to initiate
the rewind motion, after which the EOP status is set and
busy status is reset. Once the rewind motion is initiated,
the controller is able to accept motion functions to another
transport. This command allows the rewind of one
transport and motion functions in another transport to be
carried out in parallel.
60476010 A
Clear Controller
The clear controller command clears controller statuses,
registers, interrupt requests, and responses. The A register
contents do not affect this command.
the data originally sent in the upper and lower eight bits
of the A register during self-test 1 according to the
following equation:
A Low = ««A up - 1) x 2 + A low) + 1 - A up)·A low)
or A up carry-out is disregarded.
This command is rejected only if a protect fault occurs.
The self-test 1 result is shown below:
Clear controller causes all motion (except rewind motion)
in the selected transport to cease, but the unit select and
on-bus status are not affected.
15
I
AI
1~---:T=RAI6='::ER-:OA::":':T,.,..A-:-.""'F'-6------!I-_-----_--::::RE~SU::-:I1.-::0:::-'~EQ:::':UA~TI~ON~-----!I
load File Address
The load file address command specifies the address of the
MTTC 16 register file, which will be read by a file
registers status request. The load file address A-register
format is shown below:
Self-test 1 also loads the 16 file registers in the following
manner:
FILE (0)
15
.
4
3
2
1
0
A~I.II
I I
FILE ADDRESS { ,
I.
=Transfer data + F16
FILE (1) = Transfer data
FILE (2) = Transfer data + 1
FILE (3) = Transfer data +2
FILE (4) = Transfer data + 3
FILE (5) = Transfer data + 4
The load file address command is rejected if the controller
is busy or a protect fault is detected.
FILE (6) = Transfer data"," 5
FILE (7) = Transfer data + 6
Self-Test 1
FILE (8) = Transfer data + 7
Self-test 1 causes the MTTC to check its internal data
paths and arithmetic logic unit ALU. The lower eight bits
of the A register specify the data that is to be transferred
(transfer data) along the internal data paths of the MTTC.
The upper and lower eight bits of the A register specify the
data that is to be operated on by the ALU. The self-test 1
A-register format is shown below:
FILE (9) = Transfer data + 8
FILE (A) = Transfer data + 9
FILE (8) = Transfer data + A16
FILE (C) = Transfer data + 816
o
15
AI~I---------AL-u-DA-n----------~~-.~~,--------TR-AN-~-R-OO-l------------~~
I
I
_ _ _~.--____
Al,P
---l'----------
FILE (D) = Transfer data + C16
FILE (E) = Transfer data + 016
FILE (F)
= Transfer data + E16
A L!JW
In general, FILE (N) contains the transfer data plus (n-1),
except FILE (0), which contains transfer data plus F 16'
Upon acceptance of this command, the MTTC becomes
busy and remains busy until the internal transfers and ALU
operations are complete. After completion, the EOP
status is set and busy status is reset 1 microsecond later.
If EOP status is not set within 3 microseconds, this is an
indication that the MTTC is defective.
After the busy status is reset, the A-out status should be
read to determine the success of the test. The upper eight
bits of the A register should contain the same data as that
was originally sent in the lower eight bits of the A register
in self-test 1, plus F 16. The lower eight bits should
contain an expected result, which is a function of
60476010 A
After reading A-out status, the contents of the 16 file
registers should also be read and examined for the proper
data.
Self-test 1 must be preceded by a clear controller
command.
Self-Test 2
Self-test 2 checks the MTTC internal flip-flops, jump
conditions, and dynamic status flip-flops. The A register
2-9
is not used for the self-test 2 command. Upon acceptance
of this command, the controller becomes busy until the
test is completed, after which EOP status is set. Busy is
cleared 1 microsecond later. If EOP is not set 3
microseconds after the controller becomes busy, this is an
indication that the controller is defective.
Prior to the execution of self-test 2, a clear controller
command should be issued to ensure that all dynamic
status flip-flops are in their quiescent state. Figure 2-4
illustrates the dynamic status after execution of clear
controller and self-test 2.
When the test is complete (busy status reset), A-out status
should be read immediately after the completion of the
test to determine if the test is successful. A-out status
ACED16 indicates that the test is successful. A-out
status DEAD16 or any other status indicates that the
controller is defective.
If A-out status gives the successful result (ACED16),
dynamic status should be read and compared to bit box B
in figure 2-4.. If these are not identical, the controller is
defective.
14
IS
13
12
II
AINlAINlAIN/AINlAlo
10
9
10 10
8
II
7
6
1010
S
4
IN/AIN/AI
3
2
0 10
0
I
I~
14
13
12
II
10
9
8
7
6
I
I
0
~
Self-test 4 checks the A/Q channel data path of the
MTTC by reading data via the A/Q channel and writing
the same data via the DMA channel. With the Q register
loaded according to table 2-3, execution of an output
instruction causes the MTTC to read the data contained in
the A register and then write it into memory at the
address specified by the first word address and bank
select commands.
Upon acceptance of this command, the controller
becomes busy and remains busy until the transfer into
memory is complete, after which EOP status is set; busy
status is reset 1 microsecond later. The CPU should then
compare the word written into the memory by the MTTC
with the one originally sent via the A/Q. If they are not
identical, the controller is defective.
Self-test 4 must be preceded by a clear controller
command. Self-test 4 is rejected if the MTTC is busy or a
protect fault is detected.
Assemble/Sense Next Ready
..
3
2
I
I
0
0
I I I I I I I I I I I I INIA i II I I INlA I
0
Self-Test 4
I 0 INIAl
A. AFTER CLEAR CONTROLLER
AI N/A N/A N/A
Self-test 3 must be preceded by a clear controller
command. Self-test 3 is rejected if the controller is busy
or a protect fault is detected.
NIA
B. AFTER SELF-TEST 2
2277
The assemble/sense next ready command has two modes
of operation selected by bit 15 of the A register. With
A15 set, the assemble mode is selected. This allows the
CPU to receive information about the ready status of
each of the four units. With A15 clear, the sense mode is
selected. This mode allows the CPU to recei ve
notification when a change in the ready status occurs.
Figure
2-5
shows
the
A-register
format
for
assemble/sense next ready.
Figure 2-4. Dynamic Status
Since after the execution of self-test 2, the dynamic
status does not indicate the true status of the controller,
a clear controller command should be issued before
performing any further operations.
A
Self-test 2 is rejected if the controller is busy or a
protect f aul t is detected.
INITIAL UNIT..
READY STATUS
{
~--~
aUNT
I
~U~N""Tio-:O.-----J
0= UNIT NOT READY
1 = UNIT READY
Self-Test 3
tRELEVANT FOR SENSE NEXT READY ONLY (A 15" 0).
Self-test 3 checks the capability of the MTTC to read
data via the DMA channel and transmit data via the A/Q
channel. Wi th the Q register loaded according to table
2-3, execution of an output instruction causes the MTTC
to read data from the memory at the location specified by
the first word address and bank select commands, and
write the data into the MTTC A-out register.
2278
Upon acceptance of the output instruction command, the
controller becomes busy and remains busy until the
operation is complete. EOP status is reset 1 microsecond
after EOP.
Assemble Ready Status
After completion of the output instruction command,
A-out status should be read. The A-out status should be
compared with the original contents of the .address
specified by the last word address and bank select. If
these two are not identical, the controller is defective.
2-10
Figure 2-5. A Register Format for
Assemble/Sense Next Ready
With the Q register loaded according to table 2-3 and A15
set to 1 (all other bits of the A register are irrelevant),
execution of an output instruction causes the MTTC to go
busy and sample unit ready status of each of the four
MTTC units. The assemble status is then written into the
register file at address E 16. The processor can read
this status by executing a load file address command
specifying file address E 16 and then reading file status.
60476010 A
15
4
3
2
o
,I
,I
I
UNIT 3 READY
O. UNIT NOT READY
1 • UNIT READY
UNIT
2279
!
UNIT 2 READY
UNIT I READY
a READY
Figure 2-6. Read Status Format
Figure 2-6 illustrates the ready status format that is
contained in file address E16 after execution of the
assemble ready status command.
Execution of the sense next ready command causes all
units to be deselected although controller protected
status is not affected. The processor must issue a new
unit select command.
After execution of the command, all units are deselected,
although controller protected status is not affected. The
CPU must issue a new unit select command.
The sense next ready command can be used for detecting
either the completion of a rewind operation or the
mounting of a new tape reel on one of the transports.
When used together with the rewind command, the sense
next ready command detects the completion of the rewind
operation. When used with the rewind off-line command,
the sense next ready command can detect when the
operator mounts a new tape reel on the transport and
manually places the transport on-line.
Sense Next Ready
This command allows rewinding to be performed in
parallel (overlap rewind) with the CPU receiving
notification (EOP interrupt) of the completion of each
rewind by detecting any change in the unit ready status of
the four units (that is, a unit that was previously not
ready becoming ready). With the Q register loaded
according to table 2-3 and with AIS reset to 0, bits 0
through 3 of the A register specify the initial unit ready
status. Each bit corresponds to one of the units (ADO is
unit 0, AOl is unit 1, A02 is unit 2, and AD3 is unit 3).
Upon acceptance of this command, the controller
becomes busy and samples the ready status of each of the
four units. The result of this sampling is then compared
with the unit ready status originaUy received via the A
register. The sample and compare operation continues
until the original unit ready status and the actual
(sampled) unit ready status are not equal, indicating that
one or more of the units that was previously not ready has
become ready, or vice versa.
The assemble/sense next ready command is rejected if the
controller is off-bus, the controller is busy, or a protect
fault is detected.
INPUT TO A OPERATIONS
With the Q register loaded according to table 2-3,
execution of an input instruction causes the controller to
load the A register with the desired controller status. All
status requests except dynamic status requests are
rejected if the controller is busy.
Figure 2-7 shows the A-register format for status 1.
Status 1 requests are always accepted.
EOP status and EOP interrupt, if requested, are generated
when a change in the ready status is detected. Busy
status is then reset 1 microsecond after EOP. After
completion of this command, file address E16 contains
the sampled status in which the change from the original
was detected. The CPU should read this status to
determine which of the units has become ready.
Unit Ready Bit
If ADO is set, the selected transport is ready to receive
commands. ADO not set indicates that the selected
transport is either rewinding or off-line.
ON-BUS
ALARM
FBY (FORMATTER BUSY) t
CORRECTED ERROR
LWD (SET BY FIRMWARE-LAST WORDlt
FPT (FILE PROTECT-NO WRITE RING)t
ERS (SET BY FIRMWARE-ERASE}t
FILE MARK
EOP
END-O F-TAPE
t THESE BITS ARE AVAILABLE AS DEFINED IN THE STATUS 1 WORD AND ARE USED BY THE FIRMWARE TO
DETERMINE THE OUTCOME OF OPERATIONS INTERNALLY. THEY ARE NOT CONSIDERED USEFULL FOR
SOFTWARE PURPOSES AND SHOULD BE MASKED OUT IN NORMAL OPERATIONS.
2280
Figure 2-7. A-Register Format for Status 1
60476010 C
2-11
The following conditions should exist for the unit to be
ready:
•
All interlocks are satisfied
•
Initial load or rewind sequence is completed
•
Transport is on-line
•
Transport is not rewinding or unloading
EOT (end-of-tape) status (A07) is an indication that an
end-of-tape marker was detected by the sensor. This is a
warning that there is only approximately 18 feet (5.5
meters) of tape left on the reel. EOT can occur only
during forward tape motion.
If the unit becomes not ready during any motion function
except rewind, the motion terminates and the alarm
status becomes active.
Controller Busy
When bit AOl is set, the controller
acceptance of the following commands:
•
Unit select
•
Bus connect
•
Director function
•
T est modes 1, 2, 3, and 4
•
Assemble/sense next ready
is
busy
End-of-Tape
upon
All commands to the controller except clear controller
and dynamic status requests are rejected when the busy
status is set.
EaT status becomes active and causes alarm status to
become active approximately 3 microseconds before the
end of the current operation regardless of when the end of
the tape marker was detected. An alarm interrupt is
generated 2 microseconds after alarm status if alarm
interrupt was enabled.
Once an EOT marker is detected, the transport continues
sending EOT status until the EOT marker passes under the
sensor in the reverse direction. Consequently, all director
function operations initiated in the tape region following
the EOT marker terminate with alarm and EaT status.
Corrected Error
Bit All becomes set whenever a single-channel dropout
has been detected during a data transfer and the
formatter performed an error correction. This status
serves only as a warning since the data is correct.
Acceptance of a new motion function, clear controller, or
master clear resets the corrected error status.
Alarm (A03)
End-of-Operation
AD3 becomes active when an uncorrectable error oc'curs
during a data transfer or conditions arise that require
external intervention. Bus relinquish, ready, EOT status
bits, and alarm status should be checked to determine the
cause of alarm (note that the alarm status word may be
checked only after the controller becomes not busy).
When EOP status (AD8) is set, it indicates that the
previous operations have been completed.
Any alarm condition except EOT causes a termination of
the data transfer.
EOP status is reset approximately 1 microsecond after
busy status is set and becomes set 1 microsecond before
busy status is reset.
During write operations the record being written is
terminated immediately after the error condition is
detected, resulting in a shorter record than requested.
The controller becomes not busy and the tape motion
ceases after the appropriate post record delay.
The busy status is cleared by the completion of the
command, which caused the controller to become busy. A
master ciear controller also clears the busy status.
No new motion commands are accepted by the controller
when it is busy. When EOP is set, it indicates that the
controller will finish its current operation within 1
microsecond.
An EOP interrupt, if enabled, is sent to the CPU 1
microsecond before EOP status is set.
Interrupt Response
If bit A02 is set, the MTTC's interrupt signal is active.
A02 is reset by clear interrupts, clear controller, and
master clear.
During read operations. DMA data transfers ceases
immediately after the detection of the error, but the
controller remains busy and tape motion continues until
the next interrecord gap.
If alarm interrupt was enabled, an alarm interrupt is sent
to the CPU approximately 1 microsecond before EOP
status becomes active regardless of when alarm status
became acti vee
The alarm status bit and the alarm status word are reset
upon acceptance of any new command that causes the
controller to become busy. Clear controller master clear
does not clear the alarm status word.
File Mark
File mark status (AD9) is set whenever the read head of
the selected transport detects the code of a file mark
during a read, space, write file mark, or search file mark
operation.
2-12
On-Bus and Bus Busy
On-bus and bus busy status bits (A12 and A15) together
determine
the
status
and
usage
of
the
60476010 A
TABLE 2-7.
FORMATTER/CONTROLLER BUS STATUS
Formatter/Controller Bus Status
Bus Busy
On Bus
0
0
The bus is not being used by either MTTC
0
1
This MTTC has control of the bus and can access the formatter.
1
0
The other MTTC has control of the bus.
1
1
This MTTC has control of the bus, and the alternate controller is
sending a bus request. This condition generates an interrupt if
alternate bus request interrupt is selected.
formatter/controller bus according to table 2-7. These
status conditions are not supported by CYBER 18 systems.
Alarm Status
Unit select,· director function, and transport status
requests are rejected if on-bus status is not set.
Figure 2-8 shows the alarm status A-register bit
assignments. The alarm status word is valid only when
the alarm status bit of dynamic status is active.
On-bus status is cleared when:
The alarm status word is cleared by the acceptance of any
new command that causes the controller to become busy.
Clear controller or master clear does not clear the alarm
status word.
•
A bus release command is accepted
•
A bus is relinquished due to a bus force from the
other CPU
•
Alarm status requests are rejected if the controller is
busy. Alarm status resides in the MTTC register file in
address B16 and A16. To read alarm status, A16
should be loaded by a load file address command, and then
the status of the file registers should be read.
A master clear is generated
Bus busy is reset when the alternate controller releases or
relinquishes the bus.
ESO through ES4
Controller Protected
ESO through ES4 are uncorrectable hard errors that occur
during data transfers. The transfer is terminated when
one of these errors is detected. ESO may occur during
space, search, file mark, or read operations when no
characters are detected within 25 feet of tape movement
after initiation of the motion. Table 2-8 shows the
meaning of ESO through ES4 for both tape formats.
Bit A14, when active, indicates that a protected transport
is selected. The controller rejects all unprotected output
instructions. Unprotected status requests are accepted.
Deselecting the protected
lJlprotected unit clears A14.
unit
or
selecting
MEMORY PROTECT
an
FAlA..T
LOST
BUS
D~A
REUNQUISH
FORM~TER
J
REJECT
FILL
ES4
J
ES3
ES2
!
ES1J
2281
ESO...J
Figure 2-8. Alarm Status A-Register Bits
I
'"
'''----
60476010 A
2-13
TABLE 2-8.
Error
Status
ESO THROUGH ES4 ALARM STATUS
9-Track
Phase Encoding
7-Track or 9-Track
NRZI
ESO
False preamble or postamble
VRC error
ESl
Skew error or buffer overflow
CRC error
ES2
Multichannel dropout
LRC error
ES3
Parity error
Not assigned
ES4
No character read in 25 feet (7.62 meters)
No character read in 25 feet (7.62 meters)
•
E..!!!.
Memory Address Error
Bit A05 is set if an odd number of bytes are read from the
tape during a read operation. The controller fills the
lower portion of the last word transferred into the
memory with random data. Fill status is an indication
that the last byte transferred into the memory originated
from the controller, not the tape.
Bit A10 is set if an attempt is made to reference a
nonexistent memory bank.
Memory Parity Error
Bit All is set if a parity error occurs during a read from
memory.
Formatter Reject
Bit A06, when active, indicates that the formatter
rejected a command from the controller.
The following conditions activate the formatter reject:
•
Reverse commands to a transport at BOT
•
Write commands to a transport unit not having a
write-enable ring inserted
Transmission Parity Error
Bit A12 is set if a parity error is detected during a data
transmission between the formatter and controller.
Transport Status
The transport status describes the physical configuration
and operating conditions of the selected transport. Figure
2-9 shows the A-register transport status bit assignments.
Bus Relinquish
Bit A07 is set if bus control was relinquished by the
controller in response to a bus-force signal from another
controller.
The bus relinquish status bit has precedence over all other
alarm status bits. If A07 is active, all other bits should be
disregarded.
This condition is not supported by CYBER 18 systems.
Transport status requests are rejected if the controller is
off-bus or the controller is busy.
The transport mode code and speed option statuses are
sampled during selection of the unit. If the unit is
off-line when the transport is selected, reading transport
status does not give the correct status for the previously
mentioned status bits even though the unit may have been
placed on-line. Transport status requests should be
preceded by a unit select command to ensure that the
status is correct.
Lost Data
Bit Aoa is set if an attempt is made to transfer data at a
faster rate than the controller can handle.
Bit AOl, when active, indicates that the selected
transport is in the NRZI operating mode. When not active,
the selected transport is in the PE operating mode.
Memory Protect Fault
Bit A09 is set if a transfer initiated by an unprotected
instruction attempts to write data into a protected area
of memory_ The original contents of the memory are not
changed.
2-14
Speed Option
Bit AOZ, when active, indicates the selected transport is
operating at 50 ips. When A02 is inactive, the selected
transport is operating at 25 ips.
60476010 A
SPEED OPTION
NRZI
2282
Figure 2-9. A-Register Transport Status
Transport Mode Code
Current Bank Status
Bits AO) and A04 describe the physical configuration of
the selected transport. Table 2-9 defines the code.
The lower two bits of the A register are filled with the
code of the memory bank that was last referenced. The
upper bits of the A register are filled with zeros.
TABLE 2-9. TRANSPORT MODE CODE
A04
A03
Transport Description
This request is rejected if the controller is busy.
Current Word Status
This status provides the address of the last memory
reference plus 1 (LWA + 1).
0
0
7-track NRZI
0
1
9-track dual mode (PE or NRZI)
1
0
9-track NRZI
Block Length Status
1
1
9-track PE
The block lengfh status indicates how many data words
remain to be transferred when the data transfer is
terminated or when the end of record is reached. Block
length status is resident in the MTTC register file at
addresses a and 9 and is read in the same manner as alarm
status. After a data transfer operation, the block length
status specifies the number of words that remain to be
transferred minus 1 (for example, if 10016 words
remain to be transferred, block length status is FF 16)'
If the entire block length has been transferred, block
length status is FFFF 16'
Rewinding
Bit Aoa is set whenever the selected transport is
performing a rewind operation. AOa is cleared upon
completion of the rewind.
This request is rejected if the controller is busy.
Load Point
A-Out Status
Bit A09, when active, indicates that the sensor of the
selected transport is over a BOT reflective marker.
Wri te Protected
Bit AIO, when active, indicates that the tape reel
mounted on the selected' transport does not have a
wri te-enable ring inserted. Write, erase, or write file
mark commands are rejected by the formatter.
A-out status is used for reading the results of the MTTC
self-tests 1, 2, and 3. After execution of one of these
self-tests, the result resides in the MTTC A-out register.
Since the A-out register is also used for sending other
data on the A-lines, self-test results should be read
directly following the execution of the self-test to ensure
that the result is not lost.
File Register Status
Deselect
Bit A14, when active, indicates that no unit has been
selected.
Off-line
Bit A15, when active, indicates that the transport is
off-line.
60476010 A
File register status requests allow the contents of the
MTTC internal 16 register file to be read. The file
address is specified by the load file address command.
Since the file is 8 bits wide, two consecutive file words
are loaded into the A register. The lower portion of the A
register is loaded with the contents of the file at the
address speci fied by the load file address command. The
upper portion of the A register is loaded with the contents
of the specified file address plus one.
2-15
Table 2-10 specifies the usage of the file registers.
LRC and CRC Status
After an NRZI read operation, file addresses 12 and 13
contain the CRC and LRC characters whenever the entire
record was read. This status is read in the same manner
as alarm status.
TABLE 2-10. FILE USAGE
Usage
File Address
REG. 1 + 0
Return addresst
REG. 3 + 2
N/A
REG. 5 + 4
Interrupt storage t
REG. 7 + 6
Transport status
REG. 9 + 8
Block length
REG. B + A
Alarm status
REG.
o+
C
REG. F + E
CRC character
(NRZI read)
9 track only
LRC character
(NRZI read)
7 and 9 track
N/A
Ready status
tUsed for internal firmware operations only.
2-16
60476010 D
INSTALLATION AND CHECKOUT
3
Refer to the CYBER 18 Computer Systems with MOS
Memory Installation Manual for installation of magnetic
tape transport subsystems.
',--
60476010 A
3-1
THEORY OF OPERATION
The magnetic tape transport controller (MTTC) provides
the interface between the CYBER 18 Computer and the
DZI01-A Magnetic Tape Formatter. The formatter in turn
controls up to four magnetic tape transports.
The CYBER 18 sends functions or status requests to the
MTTC via the A/Q channel. The functions received from
the CYBER 18 are decoded by the MTTC. If the function
requires the operation of the tape transport, the MTTC
issues the appropriate command to the formatter. The
formatter in turn transmits proper control signals to the
transport to perform the operation. The MTTC is a
microprogrammed controller. The hardware is of a general
nature with the firmware providing the interface to the
formatter. -The controller contains on one standard PWA
board: a lK-by-16-bit PROM, an ALU for performing
logical and arithmetic operations, a 16-by-8-bit register
file, auxiliary registers, and other random logic necessary
to read, decode, and execute microinstructions. Figure 4-1
illustrates the common device controller block diagram.
Data transfers between the CYBER 18 and the controller
are made via the DMA channel. Control and status
information is via the A/Q channel.
FORMAT/CONTROLLER
INTERFACE SIGNALS
The following subsection describe the controller/formatter
interface signals. AU formatter and controller pulse
signals are latched by the controller. The output from the
latches are then input to jump condition multiplexers.
Level signals are also input directly to jump condition
multiplexers.
TRANSPORT ADDRESS (TADO, TADI)
These lines determine which one of the four transports has
been selected for operation with the formatter. The codes
correspond to the transport select lines as follows:
TRANSPORT UNIT SELECTION
TADO
TADI
False
False
Unit 0 select
False
True
Uni t 1 select
True
False
Uni t 2 select
True
True
Unit 3 select
4
COMMAND LINES
The l~vels of these lines specify a command to the
formatter. They are transferred to a command register on
the trailing edge of the GO pulse. The levels should be
held ready for 0.5 microseconds immediately before and
after the trailing edge of the GO pulse. The command
lines are as follows:
•
REV
•
ERASE
•
\.\RT
•
THR
•
VWM
•
SPM
REVERSE/FORWARD (REV)
This lEfvel if active specifies reverse tape motion, and if
inactive, specifies forward tape motion.
WRITE/READ (WRT)
This level if active specifies the write mode of operation
and if inactive specifies the read mode of operation.
WRITE FILE MARK (WFM)
If this level is active along with active INRT, it specifies a
file mark to be written on tape.
ERASE (ERASE)
If this level is active in conjunction with WRT being active,
it causes the formatter to execute a pseudo write
command. A length of tape as defined by last word (LWO)
will be erased.
Alternately, if the ERASE, WRT, and V'.f""M command lines
are all active, the formatter writes a fixed erase gap of
approximately 6 inches (152 millimeters) of tape.
THRESHOLD (THR)
If the level of this line is active in conjunction with WRT
being false, it specifies the read recovery mode. The read
recovery mode specifies a lower threshold within the read
amplifiers as defined by the threshold control.
SPACING MODE (SPM)
INITIATE COMMAND (GO)
This is a pulse that initiates the commands specified by the
command lines. The information to the command lines is
transferred to the relevant command registers on the
falling edge of the GO pulse. If the formatter and the
selected transport are ready, the command is accepted and
FBY (formatter busy) is set (active).
60476010 A
This level is active whenever a spacing operation is to be
performed. Read strobe (RSTR) is not transferred over the
read data bus lines to the controller during this mode of
operation. A combination of write, reverse, and spacing
mode causes a backspace until LWO goes active. During
this time, write current is off in the selected tape unit. In
this mode, only the tape runaway error is enabled.
4-1
P
I
N
8
7
6
5
4
3
o
o
c
c
B
B
,.'=--.....
::!
~
L:::J
-
A·~!t
...
A
~
-- ~
-'
• coca_
-:-_:;::-.:; II~~IS~I'_-:'u ~ ~I"·'
.....
e_-
O(Y'C[
IJO
IA
H.::
Ir'··
• .__
~
···t
.....
7
c=Je_CAru ..... T
~.II
6
5
4
Of' LOGIC DlAQIIAM
2282
Cl'\
o
P
-..A
0\
o
o
I-"
:t>
Figure 4-1. Common Device Controller Block Diagram
3
,
06
I
REWIND (REW)
'Mlen this pulse is active it causes the selected transport to
revert to the off-line mode.
During a read operation, the ACK Signal should be used to
indicate the readiness of the controller to receive data
from the formatter. ACK indicates that the controller has
accepted the last byte and is ready for a read strobe for
the next byte.
OFF-LINE (OFL)
This pulse, when active, causes the selected transport to
revert to the off-line mode. It is redesignated as NR (not
ready) at the transport interface. Issuing REW and OFL
commands simultaneously causes the transport to rewind to
beginning of tape (BOT) and go off-line.
INTERFACE OUTPUTS
(FORMATTER TO CONTROLLER)
LAST WORD (LWD)
FORMATTER BUSY (FBY)
'Mlen this level is active during a write or erase command
indicates that the next character to be transferred is the
last character of the tape record. This level should be set
active at the time the last data character is placed on the
interface lines.
This level becomes active on the trailing edge of the GO
pulse if the command issued by the controller is accepted
by the formatter. The level remains true until the
appropriate post-record delay has elapsed, after which the
formatter is available to accept another command. The
off-line and rewind commands cause the formatter to go
busy long enough to validate the command or to complete a
write jog if the write electronics are on.
FORMATTER ENABLE (FEN)
This level
quiescent
formatter
conditions
when false causes the formatter to reset to its
state. This line may be used to clear the
if controller power is lost or other unusual
are encountered.
WRITE DATA LINES (WO THROUGH W7 AND WP)
The eight write data lines, WO through W7, are used to
transmit data from the controller to the formatter. The
formatter normally generates the parity bit (WP). A
jumper option on the board allows the controller bit to be
used as the parity bit, while the formatter checks it for
proper parity. In the case of externally (controller)
generated parity, an error status (TFER) is set if incorrect
parity is sensed. WO corresponds to the least significant
bit, and W7 to the most significant bit of each character.
The first character of a record should be available on these
lines less than 40 character periods after data busy (DBY)
goes active until the trailing edge of the first write strobe
(W5TR) issued by the formatter. The next character should
be placed on the lines within one half of a character period.
5ubsequent characters of a record are transferred in this
manner until LWD is set active by the controller when the
last character is transmitted.
IDENTIFICATION (IDENT)
This level goes true to identify phase encoded tapes. If an
identi fication burst is detected as the BOT marker passes
over the read head, this line is set true for a short period
(approximately 40 through 64 character times). This line is
timeshared with check character gate (CCG).
CHECK CHARACTER GATE (CCG)
This level brackets the CRC and/or LRC check characters
on the read data lines during NRZI transport operations.
The signal line is timeshared with IDENT. The lines can be
used to distinguish data and check information by gating
read strobes with CCG or its complement.
HARD ERROR (HER)
'Mlen this pulse or level is active it indicates that an
uncorrectable read error has been detected by the
formatter. The HER pulse should be used to sample the
error status (E50 through E54) lines.
E50 through E54 indicates the detected error that caused
the hard error (HER) indication. The status lines are
defined as follows:
LOW DENSITY (DEN)
This level when active selects the lower of two
predetermined densi ties in a dual-mode transport during
write operations and for all NRZI 7-track read/write
operations.
•
1600 PE
or
postamble
E50
preamble
False
detected
E51
5kew error or buffer overflow
E52
Multichannel dropout
E53
Parity error during read after write
channel
associated
or without
dropouts
E54
No character read in 25 feet (7.62
meters)
ACKNOWLEDGE (ACK)
This pulse is used to acknowledge the transfer of data
during a read or write operation.
During a write operation, the ACK signal should be used to
acknowledge the data request as signified by the write
strobe signal (WSTR). ACK indicates that the controller
has accepted the last write strobe and is waiting for the
next strobe.
60476010 A
4-3
•
NRZI
Data transferred during erase commands, while the WSTR
is still active, is ignored by the formatter.
ESO
VRC error
ES1
CRC error
READ STROBE (RSTR)
ES2
LRC error
ES3
Not assigned
ES4
No characters read in 25 feet (7.62
meters)
This is a pulse level that identifies each read character on
the read lines (RO through R7 and RP). RSTR pulses are
nominally spaced at character intervals but vary due to
skew and speed fluctuations. The RSTR pulse should be
used to sample the read data lines.
READ DATA (RO THROUGH R7 AND RP)
CORRECTED ERROR (CER)
This line is set active (pulsed) when a single channel
dropout has been detected and the formatter is performing
error correction.
These levels are used to transmit the data from the
formatter to the controller during a read operation. Each
character should be sampled during the RSTR pulse time.
COMMAND REJECT (CRJ)
FILE MARK (FMK)
This line is set active (pulsed) whenever the formatter read
logic has detected a file mark. This may be during any
read forward, read reverse, or read after write file mark
commands.
The command reject signal (pulse) is used
commands that the formatter or transport
perform or respond to at this time.
conditions cause the reject command signal
to signify those
cannot logically
The following
to be active:
•
Commands to a transport unit that is busy
TRANSPORT STATUS AND CONFIGURATION
•
Reverse commands to a transport unit at BOT
These lines indicate the relative status or configuration of
the selected transport; their definitions are identical to the
definitions in the transport to formatter input description.
These Ii nes are as follows:
•
Write command issued to a transport not having a
write-enable ring installed
•
Read forward or space forward commands issued
to a transport having a write \\CON status
condition (reading with write current on)
•
Write and reverse commands issued at the same
time unless spacing mode (SPM) is active
•
•
Transport Status
ROY
Ready
ONL
On-line
RWS
Rewinding
DATA TRANSFER ERROR (TFER)
FPT
File protect
LOP
Load point (BOT)
EDT
End of tape
'M1en active this signal level indicates the controller failed
to acknowledge the data request or transfer during either a
write or read operation. This signal level is also used
during a write operation to indicate the incorrect
data/parity transfer from the controller for data bus
options that include the parity bit.
Configuration
MOPl - Mode option 1
READ MODE STATUS (ROM)
MOP2 - Mode option 2
'M1en active this signal level indicates that the formatter is
performing a read operation (not writing or spacing).
SOP -
Speed option
NRZI MODE (NRZ)
WRITE STROBE (WSTR)
This is a pulse generated for each data character to be
written on tape. The write data lines (\NO through W7 and
WP) are sampled by WSTR and are transferred into the
write register of the formatter.
The first character must be available before the first WSTR
is generated, and subsequent characters must be set up
within one half of a character period after the trailing
edge of each WSTR pulse.
4-4
'M1en active this signal level indicates that the selected
transport is in the NRZI operating mode.
7 TRACK (7-TR)
'M1en active this Signal level indicates that the selected
transport is a 7 -track uni t.
60476010 A
MICROPROGRAMMING CONCEPT
INITIALIZATION
Power on, master clear, or clear controller clears the
program counter (PC). Upon completion of the master
clear or clear controller pulse, microcode execution of the
master clear routine, whose starting address is zero,
commences. Three possible conditions can reset the PC to
zero:
•
Master clear (power ON or from panel)
•
Clear controller
•
Force bus release
The master ciear routine determines the reason for the PC
reset so that appropriate action may be. taken. First, the
force bus line is sampled and, if active, a branch is made to
a bus relinquish routine that sets bus relinquish status and
alarm status. Next, the ROM execute flip-flop (ROM
EXEC F /F), which is used to inform the microcodes that an
A/Q command has been received from the processor, is
sampled. The ROM EXEC F /F being active indicates that
a clear controller command has been received. This causes
a branch to a body of code that resets statuses not cleared
by the clear controller pulse and issues a reply. If neither
ROM EXEC or bus force are active, the reason for the PC
reset is assumed to be master clear. For all three PC reset
conditions, the program flows through the terminate busy
routine. This is an initialization routine that sets the
proper statuses and operating flip-flops. Control then
passes to the waiting loop.
Ala WAITING LOOP
The controller initiates all of its operations, with the
exception of dynamic status requests and clear controller,
from the wai ting loop. This loop continuously samples the
following jump conditions:
•
Ala EXECUTE
The function code Q-bit lines QOO through Q04 together
with the WRITE signal are one input to the A-bus selector.
'M"len the A/Q execute flip-flop is detected as being active
by the waiting loop routine, the Q input to the A bus
selector is complemented, masked, and loaded directly into
the PC. This preload causes a 32-way microprogram
branch. Each of the 32 branch locations contains the
starting address of the routine, which performs the
function whose code is found in QOO through Q04.
Not all of the 32 function codes are valid. The branch
location of illegal codes contains a jump to the reject_
routine. This routine issues a reject and then jumps back
to the wai ting loop.
The following is an example of the preload. The first word
address function (Q=60(2)) is received. Since this function
is initiated by an output instruction, the WRITE signal is
active. The complemented Q input to the A-bus selector is
shown below.
LSB
MSB
7
,
6
5
,
I I I
L
L
"'
H
4
'3
2
0
I I I I I
1004100310021001
1000
L
L
L
H
H
Bits 6 and 7 are always low, bit 5 is high because the
VvRITE signal is active; bit 4 is made high by a
program-mask operation; bits 3, 2, and 0 are low; and bit 1
is high. 'M"len this code (3216) is loaded into the PC, a
branch is made to ROM location 3216, which contains a
branch instruction to the start of the first word address
routine. Bits 8, 9, and 10 of the PC are set to zero by the
hardware for the preload operation.
The routines for executing each one of the A/Q functions
can be divided into two categories: those that cause the
controller to go busy, and those that do not.
A/Q execute flip-flop set - This flip-flop is set
whenever an A/Q command, with Q04 = 0 and the
proper equipment code are received.
NOT-BUSY ROUTINES
•
Autoload line active - This line is activated
whenever the autoload swi tch is pushed. (Not
supported by CYBER 18.)
Routines that do not cause the controller to go busy (such
as first word address) are checked for legality to determine
whether they will be accepted (replied to) or rejected.
Once a reply or reject is issued, a jump back to the waiting
loop is made.
•
On/off-line switch
'M1enever the off-line
maintenance switch is placed in the off-line
position this line goes low (active).
The following conditions cause the reject to be active:
•
Alternate bus request line active - If the
controller is on bus, and alternate interrupt was
requested, an interrupt is generated.
(Not
supported by CYBER 18.)
'M1enever anyone of the above conditions is active, an exit
is made from the waiting loop and the required action is
performed. All actions are terminated by a return to the
waiting loop.
•
Commands to a transport that is busy
•
Reverse commands to a tranport at BOT
•
Write commands to a transport that does not have
a write-enable ring installed.
First Word Address (CWA)
The data recei ved from the CPU is transferred from the A
lines Clower and upper) of the A-bus selector via the ALU
60476010 A
4-5
to the CWA registers (CWAU and CWAL). These registers
provide 16 bits of the address during the DMA transfer
operations. At the completion of a DMA transfer, the
CWAL register is incremented. Overflow from CWAL
increments the CWAU and overflow from the CWAU
increments the CWAL.
Transport Status
The jump conditions of the device status lines are tested.
If the line is active, a 1 is placed in the bit position
corresponding to the device status. An inactive signal
causes a 0 to be placed in the bi t posi tion. Transport
status bi ts are' assembled in this manner until the entire
status word is assembled.
Bank Select
Bits 6 and 7 of the A lines are transferred into the CWA
upper upper (CWAUU) register of the CWA register. This
register selects one of four 65K memory banks.
Load File Address
The lower 8 bits of the A lines are transferred to the B
register. When the file status is requested, the contents of
the B register are moved to the file address register.
Block Length
The data received on the A lines is complemented and
transferred to file address 8 -and 9. File address 8 contains
the lower 8 bits, and address 9 contains the upper. During
data transfers, file address 8 is incremented. If there is a
carry out, this indicates that the lower 8 bits of the block
length have reached zero, in which case the upper 8 bits
(file 9) are incremented. If another carry out results, this
indicates that the entire block length has reached zero and
the data transfer is to be terminated.
Interrupt Request
A-line bi ts 5, 6, and 7 are tested to determine interrupt
conditions. Corresponding flag flip-flops are set so that
the requested interrupts may be activated when conditions
warrant. If the alarm interrupt request (bit A05) is active,
the alarm status bit is tested. If the alarm status bit is
active, the interrupt response is activated.
A-Out Status
This routine simply issues a reply, sending the contents of
the controlled A-out register to the CPU.
Current Word Status
CWAL will be moved to A-out lower and CWAU are moved
to A-out upper, allowing the CPU to read the contents of
the CWA registers.
BUSY ROUTINES
For functions that cause the controller to go busy, a check
is also made for the legality of the command. If all
conditions for acceptance are present, a reply is issued and
the flip-flop is set. This flip-flop informs the A/Q control
logic to reject all commands with Q04=0. The busy
flip-flop remains set for the duration of the operation.
Completion of the operation causes a branch to the
terminate busy routine. This routine sets the initial
conditions that were changed by execution of the previous
command, checks whether an EOP or alarm interrupt is to
be generated, resets the busy flip-flop, and returns control
to the waiting loop.
The following two command routines are necessary for all
tape transport operations:
Bus Connect Routine - The execution of this routine
activates the on bus flip-flop. This flip-flop enables all the
output lines to the formatter.
Unit Select Routine - This routine activates formatter
lines T ADO and TADI. These two lines provide the
formatter with the code of the transport that the CPU
selected. The DEN (low density) and PAR (even parity)
lines may also be activated depending on the parity and
density options selected by the CPU in the unit select
command.
DIRECTOR FUNCTIONS
Once a bus connect and unit select are made, all operations
with the tape transport are initiated via a director function
command. When the Q function code is decoded as code
31l6, a branch is made to the director function routine.
ThiS routine checks that the controller is on-bus, a uni t has
been selected, and that the selected unit is ready. If any
one of these conditions is not true, the command is
rejected. If all the conditions are true a replay is issued,
and the busy flip-flop is set.
The 4-bit director function field, AOO through A03, is
decoded in the same manner as in the Q-function code.
This field is masked and loaded directly into the PC
causing a 16-way microprogram branch.
Current Bank Status
The two bi ts of the CWAUU are decoded and 0, 1, 2, or' 3
are placed in the A-out lower register according to the
results of the decoded bits. The A-out upper is set to zero.
File Status
The contents of the B register are loaded into the file
address register. The contents of the file at address Bare
loaded into the A-out lower register. The B address is then
incremented by one and again loaded into the file address.
The file contents of B+l are moved into the A-out upper
register.
4-6
The MTTC issues commands to the formatter by activating
the five formatter command lines in combinations. The
command coding is given in table 4-1. Upon receipt of a
GO pulse from the controller, the formatter initiates the
execution of the command and becomes busy. The
formatter remains busy for the duration of the operation.
If a command to the formatter is illegal (for example,
write commands to units not having the write-enable ring
inserted), the formatter issues a command reject (CRJ)
pulse.
All director function operations are terminated when the
formatter busy (FBY) signal goes low. This termination is
60476010 A
TABLE 4-1.
DIRECTOR FUNCTION COMMAND COOING
Function
I/O Li ne
GO (Pulse)
Read
REV
Space
REV
Read
FWD
Space
FWD
Write
X
X
X
X
X
X
WRT
REV
X
Write
File
Mark
Erase
Variable
Erase
Fixed
X
X
X
X
X
X
X
X
Controlled
Backspace
X
X
WFM
X
X
X
ERASE
SPM
X
X
X
done through a terminate director function routine which
checks the following conditions:
•
File Mark (FMK) - To determine if a code of a file
mark was encountered during the previous
operation.
•
Hard Error (HER) - Hard error statuses ESO
through ES3 are latched in the HER shift register.
The output of this register goes active whenever a
HER pulse is present. Upon detection of this
latched HER pulse, a jump is made to a rOl,ltine
that shifts and samples the HER shift register to
determine which ES condi tion causes the hard
error. The ES conditions are assembled in the
alarm status word where it is available to the CPU.
•
End-of-Tape
(EOT)
To determine if
end-of-tape marker passed under the sensor.
•
Corrected Error (CER) - This is a warning that a
PE error occurred that was corrected by the
formatter.
•
Command Reject (CRJ) - Alarm statuses are set
to inform the CPU that the previous director
function command was rejected by the formatter.
X
When FBY is low, the MTTC checks the HER (hard error)
line. The only error that may occur during space
operations is tape runaway (no data encountered within 25
feet (7.62 meters) of commencing tape motion).
Search File Mark Forward
an
The terminate director function routine jumps into the
terminate busy routine, which then flows back into the
waiting loop.
This operation is similar to the space forward operation.
The controller issues a space forward command to the
formatter. At the completion of the space, the controller
checks file mark status (FMK). If no file mark has been
detected, the controller issues another space command.
Spacing continues until either a FMK or HER (tape
runaway error), or ROY = LON (unit not ready) is detected.
Backspace
The backspace operation is the same as space forward
except the reverse (REV) command flip-flop is activated
by the controller prior to the GO pulse.
Search File Mark Backward
The controller issues successive backspace commands until
one of the following formatter signals becomes active:
•
FMK (file mark)
•
HER (tape runaway)
•
LOP (load point) - 'M1en performing reverse motion
operations, tape motion always stops at load point.
•
ROY - Low; unit becomes nqt ready.
Space Forward
The controller activates the SPM line, deactivates all other
command lines to the formatter, and issues a GO pulse.
The formatter goes busy and performs the operation.
Fixed Erase
Throughout the operation
following conditions:
the
controller
checks
the
•
ROY (Ready) - To determine that the unit
continues to be ready throughout the operation
•
FBY (Formatter Busy) - An indication that the
formatter completed the operation (FBY goes low)
60476010 A
The controller activates the WRT, WFM, and ERASE
command lines and issues a GO pulse. The formatter goes
busy and erases a 6-inch (152-millimeter) portion of tape.
While the fixed erase operation is in progress, the
controller samples the FBY and HER lines. When FBY is
clear, a jump is made to the terminate director function
routine.
4-7
Write File Mark
If no errors are detected, the data in the B register is
transferred to the buffer 2 upper (BF2U) register. The
second character received is transferred to the buffer 2
lower (BF2L) register. In this way two tape bytes are
assembled into one processor memory word. Once both the
upper and lower bytes are received, the controller initiates
a DMA write cycle. The controller is capable of internally
buffering four tape bytes. If a fifth byte is received and
the DMA cycle is still not complete (BF2 full status is not
set), lost data and alarm status are set.
The controller issues a fixed erase command to the
formatter. lNhen the fixed erase is complete, the ERASE
line is deactivated and another GO pulse is issued
commanding the formatter to write a file mark. This
two-step operation results in a 6-inch (152-millimeter)
erased error followed by a file mark.
Figures 4-2 and 4-3 illustrate the write file mark controller
formatter waveforms for NRZI and PE modes.
The DMA address is provided by the CWAL; CWAU and
CWAUU registers. These three registers form an IS-bit
counter combination and the completion of each DMA
write cycle increments this counter. The block length is
contained in two file address registers at address 8 and 9.
Read Data
Figures 4-4 and 4-5 illustrate the NRZI and PE read
operation waveforms. The controller deactivates all the
command lines and issues a GO pulse. The formatter goes
busy and ini tiates forward motion in the selected
transport. If the read is in PE and the motion started at
BOT, the formatter pulses the IDENT line to inform the
controller that a PE identification burst was detected.
Once the tape is up to speed and the appropriate
pre-record delay has transpired, the formatter issues the
first read strobe (RSTR) to inform the controller that the
first character is on the RO through R7 interface lines.
The completion of each DMA write cycle activates a
decrement block-length subroutine.
This subroutine
decrements the two file registers and checks for block
length equal to O.
The read operation continues until one of the following
conditions is detected:
Read data is multiplexed at the input of the B register with
the ALU bus. During read operation, RO through R7 are
selected as the input to the B register. lNhen the RTSR
pulse is detected, the controller strobes the RO through R7
data into the B register. The controller then pulses the
ACK line to inform the formatter that the character has
been received. The character in the B register is passed
via the ALU through a parity generator. The output of the
generator is compared with the parity bit (RP) received
from the formatter. If these two are not equal, the
transmission parity alarm status is activated and the alarm
bit is set. In addition to parity checking, the controller
samples the hard error (HER) line to detect errors in
transport to the formatter transmission.
REV/FWDt
______
r1~
•
FBY goes low indicating that the end of the record
is reached
•
HER goes high indicating that one of the ESO
through ES4 error conditions is detected
•
ROY goes low indicating that the uni t has become
not ready
•
A transmission parity error is detected
•
A lost data condi tion is detected
•
A block length
=Zero condition is detected.
____________________________________________
U
WRT/READt - -......
WFMt
GOt
FBytt
U
1 Ir--
u
L
1 CHAR CELL
~~~P~R~E~-R~E~C~O~R~D~D~E~LA~Y~~~----------~I~
I
~
I
rC----PO--ST---R-E-C-O-R-D-D-E-LA--Y-
TWDO.WD1.---------------------------,
(WD2. WD3) (WD4)
' - - - - - -...
FMKtt
-------------------------------------,LJ~------------------
TCONTROLLER-TO-FORMATTER WAVEFORMS
ttFORMA TTER-TO-CONTROLLER WAVEFORMS
NOTES:.
1. WAVEFORMS ARE SHOWN LOW TRUE.
2. PRE-RECORD DELAY FOR WRITE FILE MARK AS SPECIFIED IN TABLE 4-1.
3. POST-RECORD DELAY AS SPECIFIED IN TABLE 4-1.
4. WD3 AND WD3 ARE APPLICABLE TO 7-TRACK TAPE TRANSPORTS ONLY.
5. WD41S APPLICABLE TO 9-TRACK TAPE TRANSPORTS ONLY.
2283
Figure 4-2. NRZI Write File Mark (7-Track)
4-8
60476010 A
REV/FWDt~~---------------------------------------------WRT/READt~
WFMt
Got
FBytt
PRE-RECORD DELAY
POST-RECORD DELAY
. WOP, WOO, W D 1 , - - - - - - - - - - WD2, W05, WD7 t
FMKtt
40 DATA CELLS
u
tCONTROLLER-TO-FORMATTER WAVEFORMS
tt FORMATTER-TO-CONTROLLER WAVEFORMS
NOTES:
1. WAVEFORMS ARE SHOWN LOW TRUE.
2. PRE-RECORD DELAY FOR WRITE, FILE MARK AS SPECIFIED IN TABLE 4-1.
3. POST-RECORD DELAY AS SPECIFIED IN TABLE 4-1.
2284
-./
~
t
REV/PWD WRT/READt
Figure 4-3. Phase Encode Write File Mark
~--------------------------------------------------Jr1_______________________________________________
~~------------------------------------u
--,
DByt
r--'-CHAR CELL
=:J~----~-------------__1-~1
~~~~~~~----
RDP, RDO-RD7 (TYPICALI t..;,t_ _-.
RP, RD-7 (TYPICALI tt._ _ _ _ _..
RSTRtt
CCG/IDENTtt,_ _ _ _ _ _ _ _ _ _ _ _ _ __
tCONTROLLER-TO-FORMATTER WAVEFORMS
tt FORMATTER-TO-CONTROLLER WAVEFORMS
NOTES:
1. WAVEFORMS ARE SHOWN LOW TRUE,
2. PRE-RECORD DELAY FOR READY OPERATION AS SPECIFIED IN TABLE 4-1.
3. POST-RECORD DELAY AS SPECIFIED IN TABLE 4-1.
2286
Figure 4-4. NRZI Read Operation
r
,,--
60476010 A
4-9
---.r-J_______________________
WRT/READ ---.r-J.....______________________
REV/fwD
THR
'GO.
FBY
DBY
---.r-J
0
::t
POST RECORD DELAY
RDP, RDO-RD7 (TYPICAL) _ _..
·ftP, RO-R7 (TYPICAL) - - - - -_ __
RSTR
CER
ACK
UUUU1J
t CONTROLLER-TO-FORMATIER WAVEFORMS.
tt FORMATIER-TO-CONTROLLER WAVEFORMS.
)
NOTES:
1. WAVEFORMS ARE SHOWN LOW TRUE.
2. PRE-RECORD DELAY FOR READY OPERATION AS SPECIFIED IN TABLE 4-1.
3. POST-RECORD DELAY AS SPECIFIED IN TABLE 4-1.
2285
Figure 4-5. PE Read Operation
When the formatter reaches the end of a NRZI record, the
check character gate (CCG) line is activated to indicate
that the next two characters are the LRC and CRC check
characters. The controller does not transfer these
characters into the memory, but they are written in the
file at addresses C16 and 016 where they are available
to the CPU as status.
Write Data
Figures 4-6 and 4-7 show the formatter/controller
waveforms for NRZI and PE write operations. The
controller activates the WRT command line and issues a GO
pulse; the formatter either issues a reject to the command,
if the selected unit is not write enabled, or goes busy and
intiates forward tape motion.
DMA data is multiplexed at the input of the buffer 2 lower
(BF2L) and upper (BF2U) registers with the ALU output
bus. During write operations, the DMA data is selected as
the input. When the controller issues a DMA read request,
the DMA control logic of the CPU strobes the DMA data
into the BF2U and BF2L registers and sets BUF2 full status
indicating completion of the DMA cycle.
cycle, this is a lost data error condition. Having received
the DMA data prior to the WSTR, the controller places the
first tape byte into the write character W/C) register and
places the second tape byte into the B register. VfIth the
BF2U and BF2L registers cleared of data, a new DMA
request is sent. In this way tape bytes are double-buffered
in the WC, B, and BF2 registers.
The output of the we register is connected to the write
data interface lines. Data must be placed in the we
register prior to the leading edge of the WSTR pulse and
can be changed only after the trailing edge of WSTR. For
each byte placed into the WC register, a parity bit is
generated. When the trailing edge of WSTR is detected,
data is transferred from the B register into the we register
and the controller waits for the next WSTR. When two tape
bytes have been transferred, the block length is
decremented; and when block length. reaches zero, the last
word data (LIM) signal is activated to inform the
formatter that the last word is being transferred.
All the error conditions listed in read data also cause
premature termination of a write operation.
Controlled Backspace
While the formatter is going through the pre-record delay,
the controller issues a read request to the DMA. If a
leading edge of a WSTR (write strobe) pulse is recieved
from the formatter prior to the completion of the DMA
4-10
The controlled backspace allows the tape to be positioned
0.13 inches (3.3 millimeters) ahead of its original position
for a record that has been written in error. The controller
60476010 A
REV/ANDt
~~--
_____________________________________________
WRT/READt~~-------------------------------------------Got
FBytt
DBytt
WSTR
~~-------------------------------------------+1 I+- 1 CHAR CELL
___~~====~t=~~~~DlRJo--------::;~-E1
----,
~I
~
~
.I____
-I
PRE-RECORD
14-- POST-RECORD
DELAY
D_E_L_A_Y~________________~
I~I
unununu1UnU
tt
I.JUlMJlJ
ACK t
WP, WO-W7 (TYPICAL)t.....___
I...1--JO'011
1
LWDt·
,.-----..,------------
11
LJ
CRCC
DATA
LRCC
TWDP, WDO-WD7 (TYPICAL,
.
GENERATED IN TRANSPORT~
.TFWDt
---,~______________________________
Jr------------------\~-----------------
TAPESPEEDt.t______J 1
t CONTROLLER-TO-FORMATTER WAVEFORMS
tt FORMATTER-TO-CONTROLLER WAVEFORMS
NOTES:
1. WAVEFORMS ARE SHOWN LOW TRUE.
2. PRE-RECORD DELAY AS SPECIFIED IN TABLE 4-1.
3. POST-RECORD DELAY AS SPECIFIED IN TABLE 4-1.
2287
Figure 4-6. NRZI Write Operation
activates WRT, REV, and SPM, and pulses the GO line.
The formatter does a pseudo write in reverse. When the
two WSTR pulses are received, the block length is
decremented although no data is transferred. When the
block length reaches zero, the last word detected (l'MJ)
signal is acti vated, and the operation is terminated.
Variable Erase
The controller activates the WRT and ERASE command
lines and issues a GO pulse. The formatter either rejects
the command if the unit is not write enabled, or goes busy
and executes a pseudo-write onto the tape, erasing. each
character cell. F or each cell erased, a WSTR is issued. For
each two WSTRs received, the controller decrements the
block length. When the block length reaches zero, the
controller activates the LIM) line to terminate the
operation.
t Not supported
Autoload
Whenever the autoload switch is activated, the autoload
jump condition goes low. When this condition is sensed in
the waiting loop, the on-bus and unit-selected jump
conditions are sampled. If either of these lines are active,
the controller remains in the waiting loop and the autoload
operation is not performed. If both of these conditions are
not active, an exit is made from the waiting loop to the
autoload initiation routine.
This routine sets the autoload flip-flop. This flip-flop is
active during the entire autoload operation and ensures
coordination of the various routines utilized during the
autoload operation. The autoload initiation routine causes
a branch to the bus connect routine. At the completion of
bus connect, the autoload flip-flop is sampled and control
returns to the autoload initiation routine. From autoload
initiation, control passes to the assembled sense next ready
routine to determine which is the first unit in the
daisy-chain that is ready. If no units are ready, control
passes back to the waiting loop. Once a unit is found
ready, that unit is designated as the autoload device and a
by CYBER 18
l'"
60476010 A
4-11
WRT/READ~--------------------------------------------------Got
FBytt
u
.-, r-
________________
I ________ __
___
--.,_
..._ _...... J-e---PRE-RECORD
~
DELAY
I
~.
DBytt
~
~~~~
1-CHAR CELL
~ POST-RECORD
DELAY
~-'
I
'WSTRtt
LnUlJ1nJ~-----~-------------t
ACK
WP. WO-W7 t ________..
(TYPICAL)
......_ _ _ _ _~
UlJU1fU~----~--------------
LWD t
TWDP. WDO-WD7 - - - - - - -.....
(TVPI~AL)t
TFWDt
'",-----
1
TAPESPEED----------J
t CONTROLLER-TO-FORMATTER WAVEFORMS
ttFORMATTER-TO-CONTROLLER WAVEFORMS
NOTES:
1. WAVEFORMS ARE SHOWN LOW TRUE.
2. PRE-RECORD DELAY AS SPECIFIED IN TABLE 4-1.
3. POST-RECORD DELAY AS SPECIFIED IN TABLE 4-1.
2288
Figure 4-7. PE Write Operation
branch is made to the rewind routine. This routine
initiates rewind motion and passes control back to the
autoload routine. The autoload routine waits until
completion of the rewind (autoload unit becomes ready
once more). The ONAU and ONAL registers together with
the ONA are set to zero and the block length is set to
FFFF 16, specifying the maximum block length. A
branch is then made to the read data routine. This routine
transfers data from the first record after BOT into the
processor memory starting at address 0, bank O. The
transfer continues in the same manner as for normal read
until the end of record is reached or an alarm condition
occurs. The end of the read routine samples the autoload
flip-flop and passes control back to the autoload routine.
A check is made of alarm status in the autoload routine. If..
alarm is active, a determination is made of the number of
times that the read failed. Four failures pass control back
to the waiting loop. The density select (DEN), read
threshold (THR), and parity mode (PAR) flip-flops are
changed in the following manner:
4-12
~
9-Track
~
DEN
DEN
Attempt 1 Normal High
Attempt 1 High
Binary
Attempt 2 Normal Low
Attempt 2 Low
Binary
Attempt 3 Low
High
Attempt 3 High
BCD
Attempt 4 Low
Low
Attempt 4 Low
BCD
THR
Self-Tests
The controller has four self-tests for checking hardware
via firmware. Self-test 1 checks the internal controller
data paths and ALU operations. The data received from
the CPU is divided into upper and lower portions, called A
60476010 A
upper and A lower, and transferred via the ALU to the B
register and BF2L register. These registers feed the A and
B sides of the ALU, respectively. The logical/arithmetic
operations, specified by the self-test 1 equation, are
performed on these two registers and the result is placed in
the lower portion of the A-out register. The A lower data
is then transferred and incremented through all 16 file
registers and then through all of the controller registers.
A-out upper is the final destination of the data. The CPU
can examine the self-test 1 result (contained in the A-out
register) by reading A-out status.
Self-test Z checks flip-flops and jump conditions. A clear
controller command must be received prior to self-test 2
to ensure that all the flip-flops are in the reset state.
Every jump condition flip-flop that should be reset by a
clear controller pulse is tested to determine that it is in a
reset condition.
Any active flip-flop causes the
hexadecimal number DEAD to be placed in the A-out
register and a return to the waiting loop.
command is an assemble command, control passes back to
the waiting loop via the terminate busy routine. If the
command is a sense command, the assembled ready status
is compared with the status received from the CPU. As
long as these two are identical, the controller remains in a
loop sampling and comparing the status. Once a change
from the original is detected, an exit is made from this
loop and control passes to the waiting loop via the
terminate busy routine.
The portion of this routine that samples the ready status of
all four units starting from unit 0 is used by the autoload
and the off-line maintenance routine to determine which is
the first unit in the daisy chain that is ready.
MICROINSTRUCTION DESCRIPTION
Most of the control logic within the controller is
implemented by microinstructions contained within
read-only memory (ROM). This design approach replaces
the more conventional hard-wired random logic.
After testing for the reset conditions, the flip-flops are set
and then tested for the set condition. The parity generator
and all other jump conditions that can be activated by
microcode are also tested both in their set and reset
states. If all tested conditions are in the proper state, the
program loads ACED16 into the A-out register and
returns to the waiting loop via terminate busy.
To understand the controllers logic, the reader must first
understand how the microcontrol section operates and then
how to follow the logical program flow as shown in the
flow charts.
Self-test 3 initiates a DMA read request. The data read is
placed into the A-out register where it is available to the
CPU as status.
The following description describes the microinstructions
and their implementation. The microprogram flow charts
are provided in appendix A.
Self-test 4 transfers the data in the A-in lower and A-in
upper to the BF2L and BF2U registers, respectively and
then initiates a DMA write cycle. When the cycle is
complete, control passes back to the waiting loop.
THE MICROINSTRUCTION REPERTOIRE
The microinstruction set is divided into four groups:
•
Inter-register instructions
•
Load constant instructions
•
Control line and flip-flop instructions
•
Jump instructions
Off-Line Maintenance
All of the off-line maintenance operations are initiated by
the detection of an active signal caused by the on/off-line
switch being in the off position during the waiting loop. An
exit is made from the waiting loop to a maintenance
initiation routine, which sets the initial conditions of the
controller. Control then passes through the bus connect
routine to connect onto the bus and the assemble/sense
next ready routine, to select the unit on which the
maintenance will be performed.
Maintenance switches 1, 2, and 3 are decoded and the
selected operation is performed. Each of the operations
continuously samples the EOT and on/off-line switch.
Detection of EOT causes a termination of tape motion and
entry into a loop that waits for the on/off-line switch to be
placed in the on-line position so that a return to the
waiting loop can be made.
The 16-bit microinstruction word is denoted ROO through
R15, with ROO being the least significant bit. Figure 4-8 is
a summary of the various microinstruction group formats.
INTER-REGISTER MICROINSTRUCTIONS
Inter-register microinstructions are identified by R14=1
and R15=1. These instructions cause data from a
combination of two sources to be sent through the ALU to
a destination register. Various logic and arithmetic
operations, selected by the ALU control lines, are
performed on the data as it passes through the ALU. The
instruction format is shown below:
Assemble/Sense Next Ready
This command is used either to assemble the ready status
of each of the four units or to sense a change in the ready
status. The controller selects each of the units starting
with unit 0 and then samples its ready status. A 1 for
ready or a 0 for not ready is placed in the bit position
corresponding to that unit. This sampling continues until
the ready status of all four LIlits is assembled. This
assembled status is written into file address E16. If the
60476010 A
i!5
14
13
12
'11
8
o
T
I I
DESTINATION
~
ALU CONTROL
!
SOURCE A I
... -.-----1--.--
.. -.-.
4-13
JUMP
IS
•
Rio
INSTRUCTION
14
9
I I
btooi
0
8
I
I I
JUMP COND SELECT
j.
j
JUMP ADDRESS
LOAD CONSTANT INSTRUCTION
14
IS
RI
1
/.
0
13
1
12
~
j I.
0
MODE
"
·8
0
7
I I
I
j.
DESTINATION
j
CONSTANT
I NTER- REGISTER TRANSFER INSTRUCTION
14
IS
I.
13
12
~SOURCE B~
MODE
8 7 3
II
DESTINATION
L
ALU CONTROL
j.
2
0
IJ
SOURCE A
J
--/
CO\ITROl. LINE AND SET/RESET FlIP·FlCP INSTRU:TION
IS
14
13
12
8
II
7
6
S
o
R
MODE
I.
CONTROL LINE
SELECT
I=SET
O-RESET
I
~
FLIP-FLOP SELECT
2289
Figure 4-8. Microinstruction Groups
4-14
60476010 A
The source A field bits ROO, ROl, and R02 select one of
eight avaUable source A registers.' Table 4-2 provides the
source A codes.
TABLE 4-2.
SOURCE A CODES
TABLE 4-3.
= RlS-R14
Sources
R02
The source B field, bits R13 and R12, select one of four
available source B registers. Table 4-3 provides the source
B codes.
ROI
ROO
Source A
SOURCE B CODES
R13
R12
Source B
a
a
a
1
Current word address lower (CWALS)
Current word address upper (CWAUS)
a
a
a
File
a
a
1
Word counter (WCS)
1
a
Buffer 2 lower (BF2lS)
a
1
a
A-lines low (AINLS)
1
1
Buff er 2 upper (BF2US)
a
1
1
A-lines up (AINUS)
1
a
a
B-register (BREGS)
1
a
1
Q-lines (QS)
1
1
a
ROM (RO-R7)
1
1
1
Program counter (PCS)
(RAM~)
TABLE 4-4.
DESTINATION REGISTER CODES
Rll
RIO
Rag
Roa
a
a
a
a
a
Not used
1
a
a
0
1
Not used
2
a
a
1
a
Not used
3
a
a
1
1
Not used
4
a
1
a
a
File address register (RAMADD)
5
a
1
a
1
Current word address upper upper (CWAUU)
6
a
1
1
a
File (RAMD)
7
a
1
1
1
Program counter (PCD)
a
1
a
a
a
Word counter (WCD)
9
1
a
0··
1
A register upper (AOUTUD)
10
1
a
1
a
Current word address lower (CWAlD)
11
1
a
1
1
Current word address upper (CWAUD)
12
1
1
a
A register lower (AOUTlD)
13
1
1
a
a
1
Buffer 2 lower (BF2LD)
14
1
1
1
a
Buffer 2 upper (BF2UD)
15
1
1
1
1
B register (BREGD)
Destination
60476010 A
The destination field, bits ROB through Rll, selects one of
12 destination registers. Table 4-4 provides the destination
codes. The ALU control field, bits R03 through R07,
activates five of the six ALU control lines. The remaining
ALU control carry-in lines, are acti vated by a control
flip-flop. Table 4-5 provides the ALU operation codes.
Destination
4-15
TABLE 4-5. ALU CONTROL CODE INTER-REGISTER MICROINSTRUCTIONS
ALU Control
Arithmetic
Logic
= 0,
16 = 0, C = 0
S3
S2
SI
SO
0
0
0
0
A
A
A plus 1
0
0
0
1
A+B
A+B
(A+B) plus 1
0
0
1
0
A-B
A+B
0
0
1
1
Logic 0
Minus 1 (2 s camp)
Zero
0
1
0
0
A-B
A plus A- B
A plus A • B plus 1
0
1
0
1
If
(A+B) plus A - B
(A+B) plus (A • B) plus 1
0
1
1
0
A plus B
A minus B minus 1
A minus B
0
1
1
1
A-a
A - 1f minus 1
A-S
1
0
0
0
A+B
A plus A
1
0
0
1
A plus B
A plus B
A plus B plus 1
1
0
1
0
B
(A+B) plus A-B)
(A+B) plus (A - B) plus 1
1
0
1
1
A-B
A - B minus 1
A-B
1
1
0
0
Logic 1
A plus A = 2xA
A plus A plus 1
1
1
0
1
A+B
(A+B) plus A
(A+B) plus A plus 1
1
1
1
0
A+B
(A+B) plus A
(A+B) plus A plus 1
1
1
1
1
A
A minus 1
A
.L
16=1
16
C= 1
(A+B) plus 1
1
B
A plus A
B plus 1
LOAD CONSTANT MICROINSTRUCTIONS
JUMP MICROINSTRUCTION
The load constant microinstruction, identified by R13=0,
R14=0, and R15=1, loads an B-bit character (constant)
originating from the PROM into one of 12 destination
registers. The instruction format is shown below:
Jump-type microinstructions are identified by R15=0. The
jump microinstruction format is shown below:
RI8
RI4 RIS RI2 RII
!
MODE
i
f---- --- - t
I
f.
o
RIO R09 Roa R07
DESTINATION!
~
CONSTANT
14
~o;;' JU"PCO~IlITION SELECT_
9
8
o
I I
.:.. _________
~~ AOOR_ES_S________ ..+
-- -.~
Bits ROB through Rll select the destination register.
Table 4-4 provides the destination register codes.
Bits ROO through R07 designate the address in ROM that
contains the constant to be transferred to the specified
desti nati on.
4-16
18
The jump condition select field consists of bits R09 through
R14. There are 72 available jump conditions divided into 9
groups of B. The jump condition group (JC GRP~9) enable
flip-flop, which is set or reset by the flip-flop/control line
instruction, selects the group. Bits R14 through R09 select
the condition within the group. (For the group of eight,
only R09 through Rll are valid). Table 4-6 shows the jump
condition select codes and the corresponding jump
conditions.
60476010 A
TABLE 4-6.
Jump
Condition
\
JUMP CONDITION CODES
Magnetic Tape Transport
R15
R14
R13
R12
R11
RIO
R09
10
0
0
0
1
1
1
0
Autoload enable
11
0
0
0
1
1
0
0
Write add
12
0
0
0
1
0
1
0
13
0
0
0
1
0
0
0
Check character flag
14
0
0
0
0
1
1
0
Program protect
15
0
0
0
0
1
0
0
ROM execute
16
0
0
0
0
0
1
0
Write strobe line
17
0
0
0
0
0
0
0
Hardwire high (unconditional jump)
20
0
1
0
1
1
1
1
Bus busy
21
0
1
0
1
1
0
1
CRC error
22
0
1
0
1
0
1
1
Load point
23
0
1
0
1
0
0
1
Read strobe latch
24
0
1
0
0
1
1
1
Autoload push-button
25
0
1
0
0
1
0
1
Write strobe latch
26
0
1
0
0
0
1
1
On/off-line switch
27
0
1
0
0
0
0
1
Read strobe line
30
0
0
1
1
1
1
1
DMA write complete
31
0
0
1
1
1
0
1
Half-word
32
0
0
1
1
0
1
1
Current word address bit 2-16
33
0
0
1
1
0
0
1
Buffer 1 full
34
0
0
1
0
1
1
1
Current word address bit 2-17
35
0
0
1
0
1
0
1
36
0
0
1
0
0
1
1
First of data complemented
37
0
0
1
0
0
0
1
Read parity
40
0
0
0
1
1
1
1
ALU A=B
41
0
0
0
1
1
0
1
ALU carry out complemented
42
0
0
0
1
0
1
1
DMA protect fault
43
0
a
0
1
0
a
1
Hard error output
44
a
0
0
a
1
1
1
Buffer 2 full
45
0
0
0
0
1
0
1
DMA parity error
46
0
0
0
a
0
1
1
DMA address error
47
0
a
0
0
0
a
1
60476010 A
4-17
TABLE 4-6. JUMP CONDITION CODES (Contd)
Jump
Condition
4-18
R15
R14
R13
R12
Rll
RIO
R09
Magnetic Tape Transport
50
0
1
1
1
1
1
0
Mode operation 1
51
0
1
1
1
1
0
0
Formatter busy
52
0
1
1
1
0
1
0
Ready
53
0
1
1
1
0
0
0
54
0
1
1
0
1
1
0
File protect
55
0
1
1
0
1
0
0
Parity bit latch
56
0
1
1
0
0
1
0
Transfer error
57
0
1
1
0
0
0
0
File mark
60
0
1
0
1
1
1
0
61
0
1
0
1
1
0
0
Disk error.
62
0
1
0
1
0
1
0
Alarm
63
0
1
0
1
0
0
0
B-register bit 7
64
0
1
0
0
1
1
0
Index 2
65
0
1
0
0
1
0
0
Unit protected
66
0
1
0
0
0
1
0
67
0
1
0
0
'0
0
0
End of tape status
70
0
1
1
1
1
1
1
Identification burst
71
0
1
1
1
1
0
1
Mode operation 2
72
0
1
1
1
0
1
1
Speed option
73
0
1
1
1
0
0
1
7-track
74
0
1
1
0
1
1
1
Read mode
75
0
1
1
0
1
0
1
NRZI
76
0
1
1
0
0
1
1
Rewi nd status
77
0
1
1
0
0
0
1
Conmand reject
80
0
0
1
1
1
1
0
On-bus
81
0
0
1
1
1
0
0
Search file mark
82
0
0
1
1
0
1
0
Selected parity
83
0
0
1
1
0
0
0
84
0
0
1
0
1
1
0
Selected
85
0
0
1
0
1
0
0
B-register bit 5
86
0
0
1
0
0
1
0
Check character flag
87
0
0
1
0
0
0
0
Corrected error status bit
•
On-line
60476010 A
TABLE 4-6.
Jump
Condition
JUMP CONDITION CODES (Contd)
Rl5
Rl4
Rl3
Rl2
Rll
RlO
R09
90 t
0
0
0
1
1
1
0
End of tape
91
0
0
0
1
1
0
0
Corrected error
92
0
0
0
1
0
1
0
Maintenance switch 2
93
0
0
0
1
0
0
0
Maintenance switch 3
94
0
0
0
0
1
1
0
Unit single density
95
0
0
0
0
1
0
0
Maintenance switch 1
96
0
0
0
0
0
1
0
97
0
0
0
0
0
0
0
Magnetic Tape Transport
Auxil i ary
t Jump condition group 9 - ENS flip-flop must be set.
There are twa types of jump instructions:
•
•
Unconditional Jump - This type is identified by the
fact that R14 through R09 equal zero. The
program counter, bits 0 through 8, is loaded with
ROO through ROB. Program counter bit 9 is loaded
with the contents of the ROM bank select
(RMBNKS) flip-flop.
Conditional Jump - If the selected condition is
true, the program counter is loaded with ROO
through ROB and the bank select (RMBNKS)
flip-flop. If the selected condition is false, the
program counter is incremented by one.
JUMPING TO SUBROUTINES
Jumping to subroutines is a two-step process. First the
return address must be saved, and then a jump (conditional
or ,unconditional) must be made to the starting address of
the subroutine. (The RMBNKS flip-flop must be set
according to the bank in which the subroutine is located
prior to the jump.) Figure 4-9 shows the instruction
sequence necessary for jumping to and returning from
subroutines. P incremented by one (P+l) is loaded into the
register file at address 0 via an inter-register instruction.
Address 0 is provided to the file address register
(RAMADD) by the hardware. Execution of this instruction
also causes the upper two bits of the PC to be saved in
flip-flops. Next, a jump is executed to the starting ad,dress
of the subroutine. To return from the subroutine, zero is
loaded into the file address register (RAMADD) via a load
constant instruction. The contents of RAM 0 is
incremented by one and loaded into the PC. This causes a
jump to the return address (P+2). The upper two bits that
were saved in flip-flops are loaded into the upper bit
posi tions by hardware.
ROB through ROO specifies the jump address. The lK ROM
is divided into two banks of 512 words each (locations 0
through 511 are called the lower bank, locations 512
60476010 A
through 1023 are called the upper bank). ROO through ROB
specifies the address within a bank. The ROM bank select
(RMBNKS) flip-flop, which is set or reset by the
flip-flop/control line instruction, selects the bank to which
the jump will be made.
The jump instruction that causes the jump to the starting
address of the subroutine cannot be located in ROM
addresses 255, 256, 511, 512, 767, 768, 1023, or 1024 due to
the structure of the PC.
CONTROL LINE AND SET/RESET
FLIP-FLOP INSTRUCTIONS
These instructions, identified by R13=I, R14=0 and R15=1,
are used for setting or resetting up to 64 control flip-flops
and for providing a pulse on one of 16 available control
lines. Both of these operations can be performed in the
same microinstruction. The instruction format is shown
below:
1&
14
13
12
II
a
1· FF Set
O· FF Reset
The flip-flap select field, ROO through R05, selects one of
56 available flip-flaps. Table 4-7 provides the flip-flap
codes. If bit R12 is clear, the selected flip-flop is reset. If
it is set, the selected flip-flop is set.
The control line select field selects one of 16 available
control lines to be strobed. Table 4-B provides the control
line codes. Table 4-9 provides tabulation of file register
usage.
4-19
..---
ROM
SELECT BANK OF SUBROUTINE
P-
LOAD (P+U TO RAM AT ADDRESS 0
P+I
JUMP TO STARTING ADORESS OF
SUBROUTINE
RETURN ADORESS"(P+2 )
CALLING PFfOGRAM
I- THIS INSTRUCTION MUST NOT BE
LOCATED IN ROM ADDRESSES 2!5!5,
J
2!56, !5If, !512 ,767, 768, 1023,
{ 1024
-
STARTING ADORESS-
SUBROUTINE
BODY
LOAD 0 TO RAM ADORESS
REGISTER (RAMAOO)
RETlJtN SEQUENCE
LOAO[FlLE (0) +
il TO
PC
2290
Figure 4-9. Subroutine Jump Instruction Sequence
TABLE 4-7. FLIP-FLOP CODES
FDD Group
1
0
1
2
3
4
S
6
7
2
0
R03
R02
ROl
ROO
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
6
7
0
0
0
0
0
0
0
0
0
0
2
4
S
1
2
3
4
S
6
7
4-20
R04
0
0
0
0
0
0
0
1
3
3
ROS
1
1
1
1
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1.
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
];
0
Magnetic Tape Transport
Low threshold
Write file mark
Rewind
Check character flag
ROM bank select
Search file mark flag
Spacing mode
Corrected error status
Sel ect buffer 1
Off-line
Last word data
Go
Write
Formatter enable
Acknowledge
Selecter buffer 2
Write/read processor
Buffer 1 enable
Enable double buffer
Write parity
Enable word sync
Compare 1
Read/write mode
Parity mode
60476010 A
TABLE 4-7.
FDD Group
4
R05
R04
R03
R02
ROI
ROO
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
3
4
5
6
0
0
0
0
0
0
0
0
1
1
2
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
1
7
5
1
0
1
2
0
0
0
0
0
0
0
0
3
4
5
6
7
6
0
1
1
1
1
2
1
3
7
FLIP-FLOP CODES (Contd)
4
1
5
6
7
1
1
1
0
0
0
0
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
TABLE 4-8.
Control
line
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Magnetic Tape Transport
Alann
Busy
Select B register
DMA write protect
Hard error load mode
Jump condition group g enabled
Interrupt response
Erase
Reverse
Autoload enable protect system
0
0
1
0
1
Off-line maintenance
Write add
0
Auxiliary
Transport address 1
Density select
Parity select
On-bus
1
0
1
0
1
0
1
Transport address 0
ALU carry in
1
Parity
Index 2
Selected
File mark status
End of operation
End of tape status
0
0
1
0
1
0
1
0
Controller protected
CONTROL LINE CODES
Magnetic Tape Transport Controller
Rll
RIO
R09
R08
0
.0
0
0
0
Not used
1
0
0
0
1
Set reject (REJ)
2
0
0
1
0
Set DMA request (DMAREQ)
3
0
0
1
1
Set reply (RPLY)
4
0
1
0
0
Clear data strobe(CLDSTR)
5
0
1
0
1
Clear DMA request (CREQ)
6
0
1
1
0
Set read strobe latch (SRSTR)
7
0
1
1
1
Reset MTT status latch (CLSTAT)
8
1
0
0
0
Set buffer 1 full (SBFIF)
60476010 A
4-21
TABLE 4-8. CONTROL LINE CODES (Contd)
Control
Line
Magnetic Tape Transport Controller
Rll
RIO
R09
R08
9
1
0
0
1
Set buffer 2 full (SBF2F)
10
1
0
1
0
Clear hard error latch (CLHER)
11
1
0
1
1
Shift hard error 1atch (SFTHER)
12
1
1
0
0
Clear first of data (CFSTDT)
13
1
1
0
1
Clear DMA error (CDMAER)
14
1
1
1
0
Set write strobe latch (SWSTR)
15
1
1
1
Not used
TABLE 4-9. FILE REGISTER USAGE
File
Register
RAM Address Register
Magnetic Tape
Transport Controller
0
0
0
0
0
Return address t
1
0
0
0
1
Assembly/disassemblyt
2
0
0
1
0
N/A
3
0
0
1
1
N/A
4
0
1
0
0
Interrupt storaget
5
0
1
0
1
N/A
6
0
1
1
0
Transport status lower
7
0
1
~
1
Transport status upper
8
1
0
0
0
Block length lower
9
1
0
0
1
Block length upper
10
1
0
1
0
Alarm status lower
11
1
0
1
1
Alarm status upper
12
1
1
0
0
LRC character
13
1
1
0
1
CRC character
14
1
1
1.
0
Ready status
15
1
1
1
1
N/A
tUsed for internal firmware operations only.
4-22
60476010 D
DIAGRAMS
This section contains the detailed circuit description of the
magnetic tape transport controller logic diagrams included
at the end of this section. The logic diagrams specifically
reflect the FA465-A MTTC. However, they are applicable
to all F A464 and F A46S MTTCs.
5
When READ BUF is high, the output of the OR gate at T5-8
, is high. This provides the second enable to the 3-input
posi tive AND gate at U4-2.
WRITE Signal
AlQ INTERFACE
INPUT/OUTPUT OPERATIONS
The necessary conditions for an A/Q input or output
operation are as follows:
The third condition for a write operation is an active (low)
WRITE/ signal from the computer at pin 290. If the write
signal is active, T9-3 is low and the output of this inverter
at T9-4 is high. This output (T9-4) is connected to an OR
gate (T5-10), a 3-input positive AND gate (U4-10), and a
2-input positive NAND gate at R2-9.
For a write operation, the output of the OR gate at TS-8
goes high and gives the second enable to U4-2.
•
The equipment code must match the equipment
number.
•
The W=O field signal (WEO) must be true.
Sequencer Enable
•
The required read or write signal must be active
(low).
If the on/off-line switch (location Ll) is in the on position,
the sequencer at location U3 is able to initiate a sequence
of pulses. The enable is effected by the release of the
clear input at U3-1.
Equipment Identification
"\.
The equipment number is determined by four jumper plugs
individually inserted into (or removed from) socket
terminals marked Q7, Q8, Q9, and QIO at location 58B.
Inserting a jumper plug into the Q7 terminal, for example,
selects a zero for that bit. Removing a jumper plug from
the Q8 terminal selects a one for that bit, and so on. The
four hexadecimal bits of the equipment code are received
from the computer on the ADR08/, ADR09/, ADRIO/, and
ADR11/ lines at pins 281, 282, 283, and 284, respectively.
These four signals are compared with the equipment code
jumper settings.
The equipment code bits from the computer are compared
to the equipment number jumper plug settings by a 4-bit
magnitude comparator at 59. If the compared bits match
and the WEO/ signal is low (that is, A=B in is high), the A=B
out comparator output (59-6) goes high. The high output
obtained at 59-6 is the first condition necessary for the
activation of the A/Q interface sequencer (high level at
U4-1).
WField
The signal WEO/ must be low for read or write operations.
If the W field = 0 condition exists, then WEO/ at pin 292 is
low. This signal is received and inverted to a high level by
a Schmitt-trigger inverter at T9-11/1O; T9-1O is connected
to the A=B in comparator input (59-3).
READ Signal
The third condition for a read operation is an active (low)
read signal from the computer at pin 248 (READ 5STB/). If
read is active, then read at H9-13 is low, and the inverter
output (READ BUF) is high at H9-12. The READ BUF
signal is connected to the reply flip-flop (T4-12), a 2-input
posi ti ve OR gate (TS~9), the A-bus selector (F8-6), and a
3-input positive NAND gate (B3-5).
60476010 A
The hardware uses a digital filter formed by two hex 0
flip-flops at location U6. When U4-12 goes high, the OR
gate output (TS-ll) also goes high. U4-12 is connected to
U6-4; U6-5 goes high after 0 to SO nanoseconds (the clock
of U6 is 20 MHz). U6-S is connected to U6-14; U6-1S goes
high after an additional SO nanoseconds. The result is that
the signal at TS-13 goes high SO to 100 nanoseconds after
the leading edge of U4-12.
Power-On Reset
This circuit generates a reset pulse at power-on. cn is
charged through R30; at this time inputs T7-2 and U6-1
are low.
NOTE
UM1, UM2, UM3, and UM4 are external
connection points.
Diode 01 is used to discharge the capacitor at power-off.
The master reset signal (MR/) from pin 46 is received at
Schmitt-trigger inverter G9-13. Flip-flops U6-3/2 and
U6-13/12 form a digital filter. When G9-12 is high, U6-3
and T6-5 are also high. U6-2 goes high after approximately
SO nanoseconds, raising U6-13 to a high level. U6-12 goes
high after an addi tional 50 nanoseconds. If the MR/ signal
at G9-13 is still active after the 100-nanosecond delay,
T6-6 goes low, driving T7-3 low, which in turn generates a
low level at T7 -6. The GR/ signal from T7 -6 dri ves UI-3
high, generating the master reset pulse (CCMR).
CLOCK CIRCUIT
The controller incorporates a 20-MHz crystal-controlled
oscillator. The oscillator is built from transistors Ql and
Q2; gates T7-9, 10/8, T6-13, 12/11, and T6-9, 10/8; crystal
VI; capacitors; and resistors.
S-l
If an immediate reject condition does not exist, SO causes
the generation of 51 (U3-15).
Phase Generator
The clock input at U6-9 is 20 MHz. Flip-flop U6-6/7 and
NAND gate T6-1, 2/3 form the 20-MHz divider. The
output is a 10-MHz clock that is connected to U5, a hex-O
type flip-flop. The path from U5-5 through U5-6/7 and
T3-13/12 to U5-4 forms the first part of a phase
generator. G2 is a decoder/demultiplexer. Inputs lA
(G2-2) and IB (G2-3) are connected to U5-5 and U5-7.
G2-4, 5, 7, and 6 are phase-generator outputs c'p0/, c'pl/,
c'p2/, and c'p3/ respectively. Figure 5-1 illustrates the phase
pulses.
Pulse 52 is generated when the A/Q command is a clear
controller or a read dynamic status command. For clear
controller or dynamic status commands, ADR05/ is low
(making Q04 equE\l to 1), AND gate input U2-13 is high, and
data input U3-13 (51- Q4) is high.
If 51- Q4 is high, the sequencer generates pulses 52 and
53. The leading edge of pulse 53 generates the reply
pulse. The ending of the A/Q command determines the
reset of all 5 pulses.
Sequencer
REJECT CIRCUIT
Flip-flop U3 is the sequencer used for A/Q commands. The
sequencer is clocked at 10 MHz. When the controller
receives an A/Q command in the on-line state, sequencer
input UJ-l (clear) goes high. The leading edge of the first
lO-MHz clock pulse (U3-9) initiates the sequencer
operation. Figure 5-2 illustrates the sequencer pulses.
When an immediate reject condition exists, the controller
generates the reject signal at 50 (U3-10) and the sequencer
stops. A low level at AND gate U2-10 determines low at
the U3-14 data input.
A/Q commands with Q04 = 0 (ADR05 high) cause a reject
condition if the controller is in the busy state. In this case,
flip-flop BU5Y (Gl-5) is high, U2-5 is high, U2-4 is high,
and AND gate output U2-6 is high. Flip-flop U6-11/10 and
AND gate U2-1, 2/3 form a digital filter for the Q4line.
Another condition for reject is protect violation. If
flip-flop CNTPRT (B1-12) is high, the controller is
protected. An unprotected A/Q write command causes a
protect violation (U4-8 is high). Flip-flop T4-2, 3/5 is the
reject flip-flop. A reject condition (T4-2 high) causes the
generation of the reject pulse at the leading edge of 50.
U6-9
20MHZ
U6-7
IOMHZ
l
IA
G2-2
18
G2-2
",1/
L.__
NOTE: PHASE PULSES
~-
,pOI, ,p1/, ,p2/, AND ,p31 HAVE A PULSE WIDTH OF 100 NSEC EACH.
2261
Figure 5-1. Phase Pulses
5-2
60476010 A
U3-9'
IOMHZ
active low pulses at J2-10 and JZ-IZ outputs. A clear
controller or GR/ pulse clears the program counter and
activates the program from the first PROM address
(000016)·
U3-1
SEQ ENS
U3-!5
SYNC
A-OUTPUT REGISTER
U3-7
DLYD
U3-IO
SO
U3 -1!5
--.J
SI
The multiplexers with latched outputs at F4, E3, E4, and
F3 form the A-output register. F4 and E3 store the eight
least significant bits, and E4 and F3 store the most
significant bits of the controller A-channel outputs. The
ALU output bus is multiplexed with the dynamic status
flip-flops at the input to the A-out register.
U3 -12
S2
When a dynamic status request is received by the
controller, Q04 is high and the read signal is active; 51-Q4
is high; and the multiplexers select the dynamic status bits
(F4-10, E3-10, E4-1O, and F3-10 are high) as the input to
the A-out register.
U3-2
53
2262
Figure 5-2. Sequencer Pulses
If the A/Q command requires microprogram intervention,
the program determines if and when the controller will
send a reject pulse to the CPU. In this case, control line
SET REJECT/sets the reject flip-flop (active low signal at
T4-4). The reject pulse is transmitted to the CPU via
driver 89-13, 12/11 to pin 220.
REPLY CIRCUIT
Flip-flop T4-12, 11/9 is the reply flip-flop. For A/Q
commands with Q04=l, the reply condition (T4-12 high)
causes generation of the reply pulse at the leading edge of
53.
The exclusive OR gate (R4-1, 2/3) generates the SPL5
pulse. This pulse is transmitted through the E2-9, 10/8 and
E2-12, 13/11 NAND gates to clock the outputs of the
dynamic status flip-flops into the A-out register on the
trailing edge of the 5PL5 pulse. AOUTUO/ (K2-14) and
AOUTLD/ (K2-11) are the clocks to select the ALU output
bus data.
A-Out Register Buffer
The A-out register outputs are driven by inverting
three-state buffers at locations E5, F5, and B4. The
buffers are enabled by the active low output of the NAND
gate at 83-6, which places the A-out register contents on
the A-channel during A/Q read commands.
A-Bus Selector
If the A/Q command requires microprogram intervention,
the program decides if and when the controller will
generate a reply pulse. In this case, control line RPL V /
sets the reply flip-flop (active low signal at T4-10).
The 8-bit A-bus selector (F9, 09, F8, 08, OS, and C5)
selects the A input to the ALU during the execution of an
inter-register microinstruction.
The reply pulse is transmitted through driver 89-9, 10/8 to
pin 216. The reply and reject circuits are enabled only at
the time of an A/Q command (T4-13 and T4-1 are both
high).
The selector is composed of an 8-to-48-line mul tiplexer
with three-state outputs, an 8-bit three-state buffer for
the word counter (y./C) register, and the three-state outputs
of the file RAMs. The A-bus selector is controlled by the
A-bus source decoder.
MICROPROGRAM EXECUTE CIRCUIT
The following is a list of the inputs to the A-bus selector:
All A/Q commands with Q04=0 require microprogram
intervention. Flip-flop T2-12, 11/9 is the mIcroprogram
execute flip-flop. The leading edge of 51 sets the flip-flop
when T2-12 is high (Q04=O). The clear controller A/Q
command (Q04=l) sets the RMEXEC flip-flop by an active
low pulse at T2-10. REJ/, RPL V/, or GR/ pulses reset the
RMEXEC flip-flop (T2-13 is low through action of AND
gate U4-3, 4, 5/6). RMEXEC is connected as a jump
condition (Tl-14).
CONTROLLER RESET
The controller is reset by a GR/ pulse (T7-6) or by a clear
controller A/Q command (Q04=1). The clear controller
generates an acti ve low pulse at NAND gate R2-8. This
pulse, like the GR/ pulse, generates a CCMRI active high
pulse at Ul-3 driver output and CCMR2/ and CCMR3/
60476010 A
•
CPU A-channel inputs, lower, 5001/ through 5008/
•
CPU A-channel inputs, upper, 5009/ through 5016/
•
CPU Q-channel inputs AOROI/ through ADR04/,
ADR06/, and READ 8UF signal
•
ROM outputs PRO through PR7
•
Program counter bits PAO through PA7
•
8-register
outputs
8MD7, and BMS8
•
we register outputs
•
RAM outputs
20
through
24 ,
26 ,
5-3
A-Bus Source Decoder
The A-bus source decoder consists of a selector at location
A4 and a decoder/demultiplexer at location BB. When a
jump microinstruction is executed, PR15 is low. This
selects the one inputs of the selector at A4, causing IR
from A4-9 to go low and selecting PRO through PR7 as the
outputs of the multiplexers at locations 05 and C5. The
output of AND gate F2-6· is also dri ven low by the IR
signal. This enables the outputs of multiplexers 05 and C5
by placing a low signal in C5-15 and 05-15. Concurrently,
the IR signal drives the inverter output at B2-12 high,
disabling the outputs of the decoder (BB). Decoder output
BB-11 goes high and disable the outputs of the w:::, register
buffers (C7-1, C7-15, and C6-15 are high). With B2-12
high, buffer outputs C6-9, 5, 3, and 7 are disabled and are
also high. The function select pins of the ALU (FG7-6, 5,
4, and 3 and FG6-6, 5, 4, and 3) are high. ALU mode input
16 (FG7-8 and FG6-8) is driven high by NAND gate output
B3-8. With the function select and mode inputs to the ALU
high, the ALU passes the A-bus data (PRO through PR7) to
ALU outputs FG7-9, 10, 11, and 13 and FG6-9, 10, 11, and
13.
For an inter-register microinstruction, B2-12 is low. The
BB decoder is enabled and PRO, PRl, and PR2 provide the
data for the decoder select inputs (B8-2, 3, and 14). When
the selected source is the RAM, B8-12, A6-8, and A7-8 are
low. When the word counter is the selected source, BB-11
is low, and in turn C7-1, C7-15, and C6-15 are low.
PROGRAM COUNTER
Three synchronous 4-bit counters (07, 06, and B5) provide
a 10-bit address for the 1024-word PROM. This program
counter (PC) receives its lower eight bits from the
ALU-out bus. The two most significant bits are loaded
either from a 2-bit return address register, which is used
for returning from subroutines, or from PR8 and the output
of the ROM bank select flip-flop (RMBNKS). The
multiplexer at A4 selectes the input to the two most
significant bits of the PC.
During a jump to subroutine operation, the lower eight bits
of the PC are saved in address 0 of the register file (RAM)
and the upper two bits of the PC are saved in the 2-bit
return address register at A3.
During subroutine returns, the upper two bits of the PC are
loaded from the two flip-flops at A3 by the A4 selector.
The lower eight bits are loaded from RAM through the
ALU.
Receipt of a low signal on the load PC line (07-9, 06-9,
and B5-9) causes the PC to be loaded on the trailing edge
of 4>0/. The PC outputs are connected to the PROM
address input and to the A-bus selector.
(COl-20, 21 and C03-20, 21 are low); when B5-13 is high,
the upper bank is selected (C02-lB, 19 and C04-18, 19 are
high). The 16-bit, three-state outputs of the upper and
lower PROM banks are wire-ORed together.
PROM bits PRO through PR7 provide an A-source for the
A-bus selector. PROM bits are also connected to various
circuits to generate and control microprogram execution.
8 REGISTER
The B register (locations E6 and E7) is a general-purpose
B-bit register on the A side of the controller. ALU-out bus
data is multiplexed at the input to the B register with
receivers of input pins 29, 2B, 37, 30, 33, 3B, 31, and 34.
These pins are used to receive the RO through R7 read data
from the formatter.
Flip-flop Gl-6 (SELBREG) selects the input to the B
register. The trailing edge of the BREGO/ pulse (from
K2-6) strobes the selected data into the register. The B
register outputs are connected to the A-bus selector.
B-register bits 25 (BMOL) and 27 (BMSB) are
connected to jump conditions at El-14 and F1-l,
respecti ve I y.
WORD COUNTER REGISTER
Two synchronous, 4-bit up-down counters at B6 and B7
constitute the word counter 0NC) register. This circuit is
used as a general-purpose register. The weD/ pulse loads
the w:::, register.
The we register outputs are connected as an A-side source
through three-state buffers at C7 and C6. In addition, the
LWC register outputs are connected via drivers at A8A,
CBB, C9B, CBA, and C9A to pins 7, 1B, 12, 14, 15, 19, 13,
17, and ll. This allows the we to be used as data to the
formatter register. The drivers are enabled and the write
data
through WO) is placed on the lines only when the
on-bus
flip-flop
(ONBUSFF),
which
controls the
ONBUSSTAT signal from J2-2, is set.
wn
FILE ADDRESS REGISTER
Two 16-by-4 clocked RAMs with three-state latched
outputs (at A6 and A7) constitute the file of the controller.
The address of the file is selected by a 4-bit file address
register. The data to be written into the file is received
from the ALU-out bus. The RAM three-state outputs are
connected as a source to the ALU A-input.
An active low RAMO/ pulse from L2-9 acts as a write
pulse at A6-2 and A7-2 during the time that A6-7 and A7-7
are held low. Figure 5-3 illustrates the operation mode of
the file.
PROM
The PROM is organized as an array of 512 words by 8 bits.
Four PROMs are used to construct a micromemory of 1024
words by 16 bits.
The nine address bits of the PROM are provided by the nine
lower program counler bits. The tenth bit of the PC
selects between the lower 512-word bank (COl, C03) and
the upper 512-word bank (C02, C04). When B5-13 is low,
the lower bank is selected
2263
Figure 5-3. Timing for Operation Mode of File
5-4
60476010 A
The transition of the clock pulse (CP) from low to high
causes the contents of the file location selected by address
inputs AO through A3 to be strobed into the RAM output
register. A three-state output enable (EO) controls the
RAM output buffers. When EO (A6-8, A7-8) input is low,
the outputs are determined by the data in the output
register.
The quad-O type flip-flops at A5 are used as the file
address register. This register is loaded from the ALU-out
bus with the address of the file register. The loading is
executed on the trailing edge of a RAMADD/ (LZ-H)
active low pulse.
B-BUS SELECTOR
The dual 4-to-l-line data selectors/multiplexers at J9, J8,
J7, and J6 constitute the B-bus selector. The B sources are
the current word address register (CWAOUT) and buffer 2
register (BUF20UT). PROM bits PR12B and PR13 select
the B-side source during the execution of inter-register
microinstructions.
The B-bus selector outputs are connected to the ALU
B-inputs.
CURRENT WORD ADDRESS REGISTER
ARITHMETIC LOGIC UNIT
The heart of the MTTC consists of an 8-bit ALU (FG7 and
FG6). The ALU is fed on the A side by the A-bus selector,
which selects one of eight source A inputs. On the B side
of the ALU, the B-bus selector selects one of four source B
inputs. The ALU output bus is routed to one of lZ
destination registers and to a parity generator/checker.
The ALU performs 16 binary arithmetic operations that are
selected by four function-select lines (1, Z, 4, and 8). The
function select lines are received from the PROM through
buffers (C6). These buffers are enabled during the
execution of an inter-register instruction. In this case, the
data selector multiplexer (A4) generates an IR signal:
PR15 (A4-1) is high, PR14 (A4-10) is high, and IR (A4-9) is
high. The IR signal is inverted by BZ-13/1Z and provides an
enable for C6-1.
The internal carry (FG7-7) is provided by flip-flop CNALU
(AI-IZ). PR3 is gated by the IR signal (B3-9) and inverted
by B3-8. The output of NAND gate B3-8 supplies the input
for the ALU (FG7-8, FG6-8).
The inverted carry output of the first ALU (FG7-16) is
provided as a carry input to the second ALU (FG6-7).
The synchronous 4-bit up-down counters K9, K8, K7, K6,
and L6 constitute the current word address (CWA) register.
This register is divided into three subregisters: CWAL (K9,
K8), CWAU (K7, K6), and bank (L6). The inputs of each
subregister are connected to the ALU-out bus. The CWAL
and CWAU outputs provide the inputs for the B-side
selector. The Z-bit bank outputs (L6-3 and L6-Z) are
connected as jump conditions to MI-Z and Ml-15,
respectively.
The CWA register is used as an l8-bit address register
during DMA data transfers. This register provides the 16
bits of memory address and two bits of memory bank
address through buffer gates to the DMA address pins. The
16 address bits and the least significant bit of bank address
are enabled by a signal that is the result of a logical AND
between thp. REQ ACC/ (G4-13, J3-lZ) pulse and the state
of the jumper mode (inserted or removed).
When the controller executes a DMA transfer cycle, the
DMAX-RA/ (G4-l) active low pulse generates an ENABLE
ADD/ that enables the three-state buffer inverters L 7, L8,
and L9. Address bits DMA-MABOl/ through DMA-MABI7/
are connected at pins 53 through 62, 253 through 258, and
pin 35.
NOTE
Parity Generator/Checker
Too controller includes a parity generator/checker (R5)
that is provided with eight ALU-out bus bits. The ninth
input (R5-4) is the parity mode flip (PARMD). This
flip-flop is used to select even or odd parity mode.
Tt-e parity bit (R5-5) is sent to the formatter during write
operations or is compared to the parity bit received from
the formatter during read operations.
In the MTTC, the jumper mode state is
always high (the jumper is removed).
The
memory
bank
address
most
significant bit is provided by L6-Z
through buffer gate N9-14/13 to pin 36
(OMA-MAB18). The ENB DMA MR/
acti ve low signal enables this memory
bit during the DMA transfer cycle.
All of the memory address bits are active low signals.
Carry Out A B and Parity Latch
A 4-bit register at G5 is used as a latch for the ALU carry
output (G5-Z/4), for the ALU comparator output A::8
(G5-1/6), and for parity bit/error output (G5-13/8). D,uring
the execution of an inter-register microinstruction, the IR
signal is high. This causes the latch load input (G5-9) to' be
high. Data is strobed into the latch with the leading edge
of clock phase <\l 0/. The latch data remains valid until a
new inter-register instruction is executed.
NOTE
/",.
The A::8 ALU open collector outputs
(FG7-14 and FG6-14) are wire-ORed
together to give comparison for eight
bi ts. A pull-up resistor S3 is used for the
wire OR connection.
The CWA subregisters are loaded from the ALU output
bus. CWAL is loaded when an active low CWALD/ pulse
from KZ-13 is provided to K9-1I and K8-1I. CWAU is
loaded when an active low CWAUO/ pulse from K2-lZ is
provided to K7-1I and K6-1I.
The bank is loaded when an active low BANKD/ pulse from
LZ-lO is provided to L6-1I. The CWA registers are loaded
asynchronously, independent of the register clock.
The clock for the CWA register/counter is the REQ ACC/
pulse with incrementation of the CWA registers taking
place on the trailing edge of the pulse. Each time a DMA
cycle is completed, the counter is clocked and the address
for the next DMA transfer cycle is prepared. At the start
of the DMA transfer operation, the CWA register is loaded
with the first word address from the ALU output bus.
I
60476010 A
5-5
DMA BUFFER
Buffer 1 Register
The buffer 1 register is composed of four 4-bit registers
with multiplexed inputs at M8, N8, P8, and R8. The 16
memory data bits, DFMOI to DFM16, from pins 264 to 279,
are multiplexed at the input of the buffer 1 register with
16-bit parallel data from the shift register at M6, N6, P6,
and R6. Flip-flop group 2 (55-4) selects the input to buffer
1. Data is strobed into the register on the trailing edge of
the CLK BUF 1 pulse. The outputs of buffer 1 are
connected to the inputs of buffer 2.
Buffer 2 Register
The buffer 2 register is composed of four 4-bit registers
with multiplexed inputs at M7, N7, P7, and R7. The
register is divided into two 8-bit subregisters called buffer
2 low (bits 1 through 8) and buffer 2 up (bits 9 through 16).
Bits 9 througb 16 of the buffer 1 register are multiplexed
with the ALU-output bus at the input to buffer 2 low.
Flip-flop 55-12 (SELBF2) selects the input to buffer 2 low
and buffer 2 up. The loading of buffer 2 is controlled by
the DMA buffer control.
The outputs of the buffer 2 register are connected as
sources (buffer 2 low, M7 and N7, and buffer 2 up, P7 and
R7) to the B-bus selector. In addition, the buffer 2 register
is connected through buffer gates to the DMA
data-to-memory
pins
(DMA-DTMOl/
through
DMA-DTM16/). The three-state bus drivers at R9, P9, and
N9 transfer and invert the buffer 2 register data. These
buffer gates are enabled by active low pulse STB-DTM/
from the DMA signal generator. The outputs of the buffer
gates, DMA-DTMOl/ through DMA-DTM16/, are connected
to pins 64 through 79. The DMA buffer control circuit
provides separate clocks for the buffer 2 subregisters. The
clock for buffer 2 up is provided through K5-13, 12/11, and
the clock for buffer 2 low is provided through K5-10, 9/8.
DMA Buffer Control
The buffer 1 full signal is generated by the J-K
negative-edge-triggered flip-flop at location L4. The
flip-flop is clocked by the CLKBUF1/ signal. The
CLKBUF1/ signal is generated whenever a DFM (data from
memory) strobe is received from DMA control. The
program must set the BFIENB (NI-5) flip-flop to allow the
J input (L4-9) of the buffer 1 full flip-flop to be high.
The enable for DMA buffer activity is provided by the
ENBDB flip-flop (Nl-6). When ENBDB and K4-10 are high,
L4-8, L4-3, J4-8, and J4-3 are high, allowing the flip-flops
to be set.
The output of the buffer 1 full flip-flop (L4-1i) is-·
connected to the BF1F jump condition (Ml-1) and to the J
input of the buffer 1 lost data flip-flop (L4-4). If
CLKBUF1/ is provided when the buffer 1 full flip-flop is
set (buffer 1 register is full), flip-flop buffer 1 lost data is
set. The buffer 1 lost data flip-flop output sets M3-4,
which provides the LSTDT jump condition at Ml-4. This
condition informs the microprogram of the completion of a
DMA write cycle.
The J-K negative-edge-triggered flip-flop (J4-9, 12, 6/11)
comprises the buffer 2 full flip-flop. J4-4, 16, 1/14
comprises the buffer 2 lost data flip-flop.
5-6
Automatic control of the double buffer is based on the
clock request generator. When the buffer 1 and buffer 2
registers are empty, L5-1 is high and L5-2 is low. The
result is that L5-3 is low. Two flip-flops, K4-13/12 and
K4-11/10, are cascaded (K4-12 to K4-11). These flip-flops
are clocked by the 10-MHz clock. The clock request
produces a 200-nanosecond low pulse, which resets the
buffer 1 full and sets the buffer 2 full J-K flip-flops.
DMA Transfer Control
DMA data transfer is controlled by a circuit that provides
the DMA memory request signal (DMA-MR/), receives the
DMA request accept signal (DMAX-RA/), and commands
the direction and timing of the data and function transfer
(protect, error).
Write to Memory
The data is received from the formatter by the B register.
The first character is loaded into the buffer 2 up register
and the second character is loaded into the buffer 2 low
register. The buffer 2 register sends the data to memory.
When the controller executes a write to memory cycle, the
microprogram initially resets flip-flops COMPI (NI-I0),
SELBF2 (55-12), and WTRDMP (Nl-4).
The microprogram resets flip-flop ENBDB (Nl-6). When
the controller sets the DMA request, flip-flop ENBDB is
set. Control line DMAREQ/ (52-13) sets request flip-flop
T2-4, 1/5, 6. T2-6 goes low and drivers N9-12/11 and
N9-14/13 are enabled, causing DMA-MR/ to go active (low)
at pin 260 and DMA-MAB18/ to be enabled at pin 36. When
CPU memory control is able to receive or transmit
memory data, signal DMAX-RA/ (low active) is received by
the controller at pin 261. This signal enables the DMA
signal generator at G4. The low level at G4-13 (REQ
ACC/) resets the DMA request flip-flop (T2) through AND
gate J3-1, 2/3. Control line CREQ/ (52-10) is used to reset
the DMA request flip-flop when it is necessary to
terminate a DMA request due to the detection of an error.
The DMA 'v'tR.ITE signal is transmitted at pin 63. This
signal is generated by the microprogram, which controls
flip-flop WTRDMP (Nl-4). The output of this flip-flop is
inverted and buffered by G4-12/11. Flip-flop WTRDMP is
also connected through inverter G3-11/10 to G4-4. The
STB DTM/ pulse (acti ve low) appears at the output of
G4-5. This pulse enables a data transfer to the memory
(R9-1, R9-15, P9-1, P9-15, and N9-1 go low). The STB
DTM signal is provided by inverter T3-4/6 through
selectors P3-11/9 and P4-14/12 to flip-flopJ4-6/11, 10.
When the controller initiates a write to memory cycle, the
ENBDB flip-flop resets flip-flops J4-6/11, 10 and J4-1/14.
For a DMA write cycle, the STB DTM pulse sets flip-flops
J4-4, 1, 16/14. This sets SIR flip-flop M3-2, 3, 1/4. The
microprogram checks jump condition DMAOCP (DMA write
complete) to determine the end of a DMA write cycle.
Read from Memory
Data is received from memory by the buffer 1 register.
This data is transferred from the buffer 2 register through
the ALU to the word counter (We), from which it is sent to
the formatter.
60476010 A
\
~.
When the controller executes a read from memory cycle,
the microprogram resets flip-flop R'M\IOD (N1-11) and
initially sets flip-flops wrRDMP (NI-4), COMPI (NI-I0),
SELBFl (S5-4), and SELBF2 (S5-12).
The microprogram resets flip-flop ENBDB (NI-6). When
the controller sets the DMA request, flip-flop ENBDB is
set.
The DMA-MDS active low pulse is received at pin 262
whenever the controller receives data from the memory.
This pulse indicates the availability of memory data to the
controller. The DMA-MDS pulse is received by a
Schmitt-trigger receiver at G3-13/12 and is transferred
through G4-6/7 (DMAX-RA/ is the enable) to the selector
at P4.
The STBDFM/ pulse is selected at CLKBUFI (P4-9). This
clock strobes the data from memory into the buffer 1
register. The microprogram initially sets the BFIENB
flip-flop. (NI-5). The CLKBUFI pulse sets flip-flop L4-9, 6,
12/ll. L4-10 and L5-3 go low, generating a low-going
pulse at K4-10. This pulse sets flip-flop L4-7/ll. The
microprogram checks this flip-flop at jump condition BF2F
(H3-15) to determine the completion of the read cycle.
DMA Transfer Cycle Errors
The controller receives DMA-MPE/ (parity error),
DMA-PFLT/ (protect fault), and DMA-MAE/ (address
error) at pins 252, 237, and 263, respectively. OR gates at
H6 enable these signals to be latched into three set/reset
flip-flops at H5. Whenever the REQ ACC/ signal is active,
H6-12, 2, 10 is active to allow coupling of the memory
error signals to the latch inputs (H5-11, 12, 6, 15). Control
line CDMAER/ (from M2-10) resets the memory error
latches under microprogram control.
To attempt to prevent lost data during DMA transfer, the
controller generates a PRIORITY/ signal to pin 227. This
signal is acti vated when the microprogram sets flip-flop
PRIOR (BI-4). The priority signal is enabled by the request
flip-flop (whenever M9B is high).
NOTE
At pin 39 the controller provides the
SLOW DMA signal to optimize the
memory performance.
DUAL ACCESS TO THE DEVICES
(This function is not supported in CYBER IB systems.)
The controller incorporates provisions for dual CPU access
to devices. The BUS BUSY/ signal, received at. pin 99, is
active (low) when the second controller has control of the
bus. A jumper double bus (SB) is inserted for dual access.
The BUS BUSY/ signal is received by UB-13/12 arid
transferred (inverted) to jump condition BUSBY (Rl-4).
The normal state of flip-flop RQBUS2 (51-4) is high, thus
the output at Ul-6 is low.
The bus priority (BP) jumper is inserted or removed to
determine which controller will gain bus control when both
controllers are attempting to connect onto the bus
simultaneously. Control goes to the controller that has the
jumper removed.
60476010 A
If the controller has higher priority, the jumper is removed
and driver SBA-2, 1/3 receives an enable (SBA-2 is high).
Flip-flop RQBUSI (AI-I0) announces that the controller
wants to connect onto the bus. If both controllers set their
RQBUSI flip-flop, both controllers generate a BUS NEED/
active low signal at pin 84. The bus busy is received
(active low) at pin 99 of the respective controller. Ul-6
goes low in both of the controllers.
In the controller that has the simultaneous bus determine
jumper inserted, SBA-2 goes low and the BUS NEED/ signal
is deactivated (pin 84 goes high). In this mode, the
controller without the jumper remains on the bus.
For a normal bus connect operation, the controller
transmits the BUS NEED/ signal to the second controller.
The microprogram resets flip-flop RQBUS2; Ul-6 goes
high. The program sets flip-flop RQBUSl; SBA-3 goes low.
When the alternate controller releases the bus, the first
controller may connect onto it.
The controller can gain immediate bus control by forcing
the alternate controller off the bus. Flip-flop FRCBUS
(GI-I0) through inverter J2-3/4 generates the FORCE
BUS/ signal to the alternate at pin 242. The controller can
be forced off the bus by the alternate in the following
manner: at pin 80 the AL T FORCE/ active low signal is
received. This signal is transferred by Schmitt-trigger
inverter G3-9/B and causes the input of NAND gate B9-5 to
go high. At the same time, the alternate controller
provides a BUS BUSY/ active low pulse at pin 99, causing
B9-4 to go high. The output B9-6 generates a master clear
active low pulse through AND gate T7-5, 4/6.
The D and SIR flip-flop (R3-4, 1/5) is used as the force bus
release index. The microprogram sets this flip-flop via
control line SRSTR/ (52-9). This flip-flop informs the
microroutines that the alternate controller has forced the
release of the device bus. This index is reset by control
line CLDSTR/ (S2-11).
DESTINATION DECODER
The decoder/demultiplexers at L2 and K2 make up the
destination decoder. Select inputs L2-1, 2, 3, and K2-1, 2,
3 are connected to PRB, PR9, and PRI0. PRll/ enables
L2, and PRll enables K2 (thus choosing between the two
decoders); DEST DEC ENB/ from AND gate F2-B enables
L2 and K2. The acti ve low pulse to clock the selected
destination is generated when clock phase 4>3/ enables the
L2 and K2 decoder inputs.
The controller uses 12 of 16 destinations. The signal
destination (active low pulse) enables the loading of the
data into the designated register.
CONTROL LINES
The decoder/demultiplexers at 52 and M2 comprise the
control line decoder. Select inputs 52-1, 1, 2 and M2-1, 2,
3 are connected to PR8, PR9, and PRIO. PRll/ enables
52, and PRll enables M2 (thus choosing between the two
decoders); MODE CL/FF / from mode decoder G2-11
enables 52 and M2. The active low pulse of the selected
control line is generated when clock phase 4>3/ enables the
52 and M2 decoder inputs.
The MTTC uses 14 of the 16 control lines. Control line 15
cannot be used due to the structure of the microprogram
instruction.
5-7
FLIP-FLOP NETWORK
The 8-bit addressable latches (A2, 55, Nl, Gl, 51, AI, and
81) are multifunctional devices capable of storing
single-line data in eight addressable latches.
The addressable latch address inputs (pins 1, 2, and 3) are
connected to PRO, PRl, and PR2 through inverters G3-1/2,
G3-3/4, and G3-5/6. PR12 determines the data to be
stored: if set, the selected flip-flop is set, and if clear, it
is reset.
The flip-flop output (H5-4) is inverted by T3-11/IO and
provides the LOAD PC/ pulse for the program counter.
The program counter is loaded with the ALU-out data and
the data selected by the muJ tiplexer at A4, thus executing
a microprogram jump.
The LOAD PC/ signal is acti ve during the time interval
from the leading edge of clock phase c!> 3/ to the leading
edge of the next 92/ clock phase (c!>2/ resets the 5/R
flip-flop at H5).
The controller includes a total of 72 jump conditions.
The decoder/demultiplexer at HI enables the selected
group of eight flip-flops. PR3, PR4, and PR5 select the
group; PRO, PR1, and PR2 select the flip-flop within the
group.
Group selection is enabled when the controller executes a
clear flip-flop (a../FF) instruction. An active low MODE
a../FF / signal enables HI (HI-5 goes low). The HI outputs,
which are connected to enable pins (pin 14) of each of the
flip-flop groups, generate a1 active low pulse on the
selected·output pin during the q,3/ clock phase at HI-4.
UNIT PROTECT JUMPERS
The unit is protected whenever the respective protect
jumper is inserted. The unit protect jumpers (SD4 through
SD7) are located at PI and are connected to the 4-input
multiplexer at P2. Inverted output P2-14 is connected to .
jump condition UNTPRT (Fl-14). Jumper SD7 is associated
with unit and jumper SD4 is associated with unit 3.
°
A removed jumper indicates an unprotected unit.
Groups 1, 2, 3, 4, and 5 are connected to the CCMR2/
signal. A clear controller signal clears the flip-flops in
these groups. Groups 6 and 7 are connected only to the
general reset (GR/) signal, and the clear controller
command does not clear these two groups of flip-flops.
The controller flip-flop network includes a total of 56
flip-flops.
JUMP CONDITION NETWORK
The jump condition network is made up of the 8-to-1 data
selector/multiplexers Tl, Rl, Ml, H3, H7, Fl, U7, El, Jl,
and N2; the 2-input AND-OR invert gate at M5; the OR
gate at K3-1, 2/3; the inverters at H2 and T3-11/10; and
the flip-flop at H5.
There are nine groups of jump conditions. PRIO, PRll, and
PR12 select the jump condition within one of the nine jump
condition groups. 8its PRIO, PRll, and PR12 are inverted
by H2-9/8, H2-11/10, and H2-13/12 and are connected to
input pins 11, 10, and 9 of Tl, Rl, Ml, H3, H7, Fl, U7, and
El (jump condition groups 1 to 8) and Jl (group 9).
Jump condition groups 1 to 8 strobe inputs are constantly
enabled via a connection to ground. Jump condition group
9 is enabled by an acti ve low signal at K3-3 (PR15 ORed
with 4>3/).
PROM bits PR12, PR14, and PR9 select the jump condition
group. The strobe to this selector (N2-7) comes from K3-3
when the controller executes a jump instruction (PR15 is
low). OR gate K3-1, 2/3 provides this strobe signal with
the q,3/ pulse. Flip-flop JGRP9 (Gl-ll) controls the
selection of the jump condition. When the flip-flop is reset,
the controller selects the jump condition within groups 1 to
8. When flip-flop JGRP9 is set, the microprogram selects
the jump conditions in group 9 (J1). Inverter H2-5/6 and
gate M5-13, 1, 9, 10/8 provide this selection. The state of
the sIR flip-flop at H5 depends on the state of the selected
jump condition.
The 5/R flip-flop at H5 is also set by a PCD/ (L2-7) active
low pulse whenever the program counter (PC) is the
destination register for an inter-register instruction.
5-8
MAINTENANCE SWITCHES
The on/off-line (LS) switch is connected to jump condition
ONOFLN. In the on position, the switch permits normal
controller activity. In the off position, the switch
disconnects the controller from the A/Q bus of the
computer and places the controller in maintenance mode.
In this mode, AND gate output U4-12 is low. Sequence
input U6-4 is also low and disables sequencer operation.
Consequently all A/Q commands received generate an
internal reject.
The type of operation performed is determined by the
positions of the maintenance switches (MSI - MS3):
•
MSI is connected to jump condition MSWI (J1-14).
•
MS2 is connected to jump condition MSW2 (Jl-2).
•
MS3 is connected to jump condition MSW3 (Jl-l).
The off-line operation initiated on the first tape that is
ready conforms to table 5-1.
TABLE 5-1. OFF-LINE OPERATION
MS2
MS1
Operati on
Off
Off
Continuous read
Off
On
Continuous read
On
Off
Continuous write - l's
On
On
Continuous write - O's
Switch MS3 determines the density at which the off-line
operation is to be performed:
•
M53 on =
Low density
•
MS3 off =
High density
60476010 A
JUMPER JM
The mode jumper (JM) determines the activity mode of the
exclusi ve OR gates at R4. When the JM jumper is inserted,
T3-2 is high and the gates invert the data transferred by
the receivers (T9). When the JM jumper is removed, the
gates transfer the data without inversion. For the MTTC,
JM is remo ved.
Signal and termination conditions applicable to inputs from
the formatter to the MTTC are listed in table 5-2. All
input signals from the formatter are active low.
Signal and termination conditions applicable to outputs
from the MTTC to the formatter are listed in table 5-3.
The output signals are enabled only when the controller has
TABLE 5-2.
Pin·
Number
Signal
Name
the device bus; that is, the flip-flop ON8U5FF (Al-9) is
set. All output signals to the formatter are active low.
NOTE
Gate 568-6, 7/5 is wire-ORed with gate
56A-6, 7 IS. With jumper JM removed,
56A-2 and 56A-7 are low. The outputs
at pin 81 and 85 are OFL and WR. T ,
respectively.
LOGIC DIAGRAMS
Figure 5-4 is the logic diagrams for the magnetic tape
transport controller.
INPUTS FROM FORMATTER
Receiver
Location
Termination
Type
Jump Condition
Name of Location
16
FPT
220/330
H9-9/8
FPT (H7-15)
20
FMK
220/330
E9-11/l0, HB-4/13
FMK (H7-l2)
21
TFER
220/330
E9-13/12
TFER (H7-13)
22
ROY
220/330
H9-5/6
ROY (H7-2)
23
MOPl
220/330
H9-l/2
MOPl (H7-4)
24
FBY
220/330
H9-3/4
FBY (H7-3)
25
ONL
220/330
E9-9/8
ONL (H7-l)
27
CER
220/330
EB-9/8
CER (J1-3)
2B
R1
220/330
EB-3/4
B-register (E7-5)
29
RO
220/330
EB-5/6
B-register (E7-2)
30
R3
220/330
E9-1/2
B-reg;ster (E7-1)
31
R6
220/330
E9-3/4
B-register (E6-6)
33
R4
220/330
EB-13/12
B-register (E6-2)
34
R7
220/330
EB-ll/l0
B-register (E6-1 )
37
R2
220/330
EB-1/2
B-register (E7-6)
3B
RS
220/330
E9-5/6
B-register (E6-5)
40
ESO
220/330
G9-112
HEROUT (H3-1)
41
ES1
220/330
G9-3/4
HEROUT (H3-1)
43
ES3
220/330
G9-9/B
HEROUT (H3-1)
44
HER
220/330
G9-11/10
HEROUT (H3-1)
45
ES2
220/330
G9-5/6
HEROUT (H3-1)
91
RSTR
470 ohms
T9-13/12, R4-10,9IB,
R3-2,3/5
RSTRLT (R1-1)
92
WSTR
470 ohms
T9-9/B, R4-13,12/11,
R3-12,1l/9
WSTRLT (Rl-14)
60476010
A
5-9
TABLE 5-2.
Pin
Number
Signal
Name
INPUTS FROM FORMATTER (Contd)
Termination
Type
Receiver
Location
Jump Condition
Name of Location
93
LOP
220/330
UB-I/2
LOP (RI-2)
94
lOENT/ECG
470 ohms
U9-l/2
lOENT (U7-4)
95
MOP2
470 ohms
U9-3/4
MOP2 (U7-3)
96
SOP
470 ohms
U9-5/6
SOP (U7-2)
97
ROM
470 ohms
U9-11/iO
ROM (U7-I5)
9B
RW-STAT
220/330
UB-9/B
RWS (U7-13)
295
EOT
220/330
UB-5/6
EOT (Jl-4)
296
RP
220/330
U8-3/4
RP
297
7TRK
470 ohms
U9-9/B
TRK7 (U7-1)
298
NRZI
470 ohms
U9-13/12
NRZI (U7-14)
299
CRJ
220/330
UB-lI/iO
CRJ (U7-I2)
(~11-I2)
TABLE 5-3. OUTPUTS TO FORMATTER
5-10
Driver Location
Pin Number
Signal Name
Origin
3
DEN
Flip-flop DEN
A9B-1,2/3
4
TADO
Flip-flop TADO
A9A-l,2/3
5
THR
Flip-flop THR
ABA-1,2/3
7
SPM
Flip-flop SPM
ABA-6,7/5
8
REW
Flip-flop REW
ABB-6,7/5
9
TADI
Flip-flop TADI
A9A-6,7/5
10
PAR
Flip-flop PARFF
A9B-6,7/5
11
WO
Word count B7-3
CBA-l,2/3
12
W6
Word count B6-6
CBB-l,2/3
13
W2
Word count B7-6
C9A-l,2/3
14
W5
Word count B6-2
C9B-l,2I3
15
W4
Word count B6-3
C9B-6,7/5
17
WI
Word count B7-2
C9A-6,7/5
IB
W7
Word count 86-7
CBB-6,7/5
19
W3
Word count B7-7
CBA-6,7/5
49
ERS
Flip-flop ERS
J5-1,2/3,4/5
50
WFM
Flip-flop WFM
ABB-l,2/3
60476010 A
TA8LE 5-3.
OUTPUTS TO FORMATTER (Contd)
Driver Location
Pin Number
Signal Name
Origin
81
OFL
Flip-flop OFL
568-1,2/3
82
GO
Flip-flop GO
S7A-1,2/3
85
WRT
Flip-flop WRT
S68-6,7/5
86
FEN
Flip-flop FEN
S7A-6,7/5
87
ACK
Flip-flop ACK
S78-6,7/5
88
REV
Flip-flop REV
S8A-6,7/5
250
WP
Flip-flop
M9B-6,7/5
294
LWD
Flip-flop LWD
S78-1,2/3
"-
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60476010 A
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265
266
267
268
269
270
271
272
273
274
275
276
277
278
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65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
53
54
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0102
0102
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0102
0102
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0102
0102
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0102
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0106
0106
0106
0106
0105
0105
0105
0105
0106
0106
0106
0106
0105
0105
0105
0105
0103
0103
0103
0104
0104
0104
0104
0104
0103
DENI
DFHOI
Oftt02
Oftt03
Oftt04
Oftt05
Oftt06
Oftt07
OfH08
Oftt09
OfHIO
Of HI I
OfHli!
OfHI3
OfHI4
Of"15
Of"16
O/1A-OTHOII
0t1A-OTtt021
DHA-OTtt031
DHA-OTtt041
DHA-OTtt051
0ttA-OTtt061
0t1A-OTtt071
Ot1A-OTHOBI
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Ot1A-OTHlll
0HA-OTH121
0HA-OTH131
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0HA-OTH151
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DHA-11A8021
DHA-HAB031
DHA-HA9041
0HA-HAOO51
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•• '.IR'..1 62 01 ••
r- 9,16
~
RX
I..--
I
II
~
0125
'FF GRP-'l'
1 1 0 COIG10
>-- 9,17
SR
OS
J2
4 7 C7/G17
1
TAll I
012:5
Lrx,y
~G9
~RGTR
9~~4
1lE.!i SN
19,10
2 2 - -----.
~
~ RT 0124,0125
FLIP-flIP NETueRK
Figure 5-4. Magnetic Tape Transport Controller Logic Diagram (Sheet 24 of 28)
J
;)(..
I
0123
1.-7
24
I
V1
I
'vi
0\
'X GRP-4'
0\
'X GRP-l'
JUt1P CINDJTIINS NETUIAK
~
.;.,J
0-
~
o
(TJ
Figure 5-4. Magnetic Tape Transport Controller Logic Diagram (Sheet 25 of 28)
/
/
/
~
a
.po
'"
a
~
.. V
10-
a
(T]
S16
1500
S8
1500
R21
1500
01
THAI
01
01
IJi>I
01
REVI
01
Gel
012
FENI
012
I-IFMI
012
REIJI
012
O1l8:J1
0FLI
0118
012
I-IRTI
012
NIJ
+5V
"JUMPERS"
012
S2
2.2K
S2
2.2K
0122
0123
PARI
0123
DENI
\
L
0123
TAD01
0123
TAD I I
I
Yl.J
-=
L0G I C DI AGRAHLCTT F0RHAT C0NTR0LLER
DRIVERS T9 DEVICE .AJI1PERS
Vl
I
VI
-...I
Figure 5-4. Magnetic Tape Transport Controller Logic Diagram (Sheet 26 of 28)
R7
2.2K
-
-',
,
VI
Vol
(Xl
-;-
leGle DIAGRAHLeTT FeRHAT C0NTR0LLER
0'\
RECEIVERS FeR SIGNAlS
FR8H DEVICE
o
+:-
-...J
'"
S
o
fTI
Figure 5-4. Magnetic Tape Transport Controller Logic Diagram (Sheet 27 of 28)
f'
/
"
a..
opo
-..J
a..
o
o
+:5V
I-
fTI
~}80~~}&o
~}&o~~}&o
NRZII ) e9a
~------
t-L "
HI
I"
:5
;~:~;,
S
I
I
I I,
4
I
_______________________________
NR
__ ZJ(VD) 0124
~
0124
0124
2
JDENT/ECG
~.,.
~
FPT/) IS
S7
4
S7
3300
I
2200
[!}
'RECEIVERS'
9
7414
H9
FPT
8
@
0112,0124
~+:5V
-==-
+5V
0113~A'I-~
I
L_
0124
0124
0124
8
-=0104 (ca) ..UtlPER H0DE
'I
I" I''';' '''L'
~------------~--•• ~5V
RECEIVER CIRCUITS
VI
I
VJ
\0
Figure 5-4. Magnetic Tape Transport Controller Logic Diagram (Sheet 28 of 28)
I
SI
&
X/Y
75452
SSA-
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I-lRT I (UR} 0125
(
'--
6
MAINTENANCE
/'
MAINTENANCE PHILOSOPHY
PREVENTIVE MAINTENANCE
The maintenance philosophy for the MTTC is to use
diagnostics to determine if the controller is defective. The
necessity for operator intervention, through the operators
panel, is kept to a minimum.
Preventive maintenance is limited to running diagnostics.
VOLTAGE MARGINS
The defective module should be replaced in the field and
taken to a depot for repair.
The MTTC can operate with a +5 percent voltage variation
from nominal voltages.
-
OPERATING ADJUSTMENTS
A/Q-DMA SLOT PIN ASSIGNMENTS
No operating adjustments are required, except for the
initial setting of the manual control jumpers. (Refer to
section 2.)
TABLE 6-1.
Table 6-1 shows the A/Q-DMA pin assignments.
A/Q-DMA SLOT PIN ASSIGNMENTS
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
1
+5VDC
21
TFER/
41
E501/
61
DMA-~1AB09 /
2
+5VDC
22
ROY/
42
AUTOLOAD/
62
DMA-MABlO/
3
DEN/
23
MOPI/
43
E503/
63
DMA-WRITE
4
TADO/
24
FBY/
44
HER/
64
DMA-DTMOlI
5
THR/
25
ONL/
45
E502/
65
OMA-DTM02/
6
GNO
26
GND
46
MR/
66
DMA-DTM03/
7
SPM/
27
CER/
47
CHAR INPUT/ t
67
DMA-DTM04/
8
REW/
28
Rl/
48
STERM/ t
68
OMA-DTM05/
9
TAD II
29
RO/
49
ERS/
69
DMA-DTM061
10
PARI
30
R31
50
WFM/
70
DMA-DTM07/
11
WO/
31
R6/
51
-12VDC t
71
DMA-DTM08/
12
W6/
32
GND
52
+12VDC t
72
DMA-DTM09/
13
W2/
33
R4/
53
OMA-MABOI/
73
OMA-DTMI0/
14
W5/
34
R7/
54
DMA-MAB02/
74
DMA-DTMll/
15
W4/
35
OMA-MABI7/
55
OMA-MAB03/
75
DMA-DTMI2/
16
FPT/
36
DMA-MABI8/
56
OMA-MAB04/
76
DMA-DTMq/
17
WI/
37
R2/
57
DMA-MAB05/
77
OMA-DTMI4/
18
W7/
38
R5/
58
DMA-MAB06/
78
DMA-DTMI5/
19
W3/
39
5LOW-DMA
59
DMA-MAB07/
79
DMA-OTMI6/
20
FMK/
40
E500/
60
DMA-MAB08/
80
ALT FORCE t
tThese signals are not used by the controller and they mayor may not be pre-wired on the processor
backpl ane.
60476010 A
6-1
TABLE 6-1.
A/Q-OMA SLOT PIN ASSIGNMENTS (Contd)
Signal
Signal
Pin
Signal
Pin
81
OFL/
210
R004/
241
R015/
272
DFM09
82
GO/
211
S005/
242
FORCE BUS
273
DFM10
83
GNO
212
AOR05/
243
S016/
274
OFM11
BUS NEEO/
213
RTERM/t
244
R016/
275
OFM12
85
WRT/
214
R005/
245
AOR04/
276
OFM13
86
FEN/
215
S006/
246
AOR03/
277
OFM14
87
ACK/
216
REPLY/
247
AOR02/
278
OFM15
88
REV/8
217
AOR06/
248
--
279
OFM16
89
N/A tt
218
R006/
249
INTRPT/
280
AOR01/
90
N/Att
219
S007/
250
WP/
281
AOR08/ (Q07)
91
RSTR/
220
REJECT/
251
GNO
282
AOR09/ (Q08)
92
WSTR/
221
R007/
252
DMA-MPE/
283
AORlO/ (Q09)
93
LOP/
222
--
253
DMA-MABll/
284
AOR11/ (QI0)
94
IOENT/ECG
223
S008/
254
OMA-MAB121
285
--
95
MOP2/
224
R008/
255
DMA-MAB131
286
96
SOPI
225
S009/
256
OMA-MAB141
287
---
97
ROM/
226
R009/
257
DMA-MAB15/
288
--
98
RW-STAT/
227
PRIORITY/
258
DMA-MAB161
289
--
290
WRITE/
.
84
Signal
Pin
Pin
-
99
BUS BUSy;t
228
S0101
259
OMA-MClM t
100
--
229
ROlO/
260
DMA-MR/
291
PROGPROTI
101
GNO
230
SOl1l
261
OMAx-RAI
292
WEOI
102
GNO
231
ROll/
262
DMA-MOSI
293
ENPRTSYSI
201
+5VOC
232
GNO
263
DMA-MAE
294
LWO
202
+5VOC
233
S0121
264
DFM01
295
EOT/
203
SOD 11
234
R012/
265
DFM02
296
RP/
204
ROOll
235
S0131
266
OFM03
297
FTRK
205
S002/
236
RD131
267
OFM04
298
NRZI/
206
ROO2/
237
--
268
OFM05
299
CRJ/
207
S0031
238
S014/
269
DFM06
300
--
20B
RD03/
239
R014/
270
DFM07
301
GND
209
S004/
240
S0151
271
OFM08
302
GNO
tThese signals are not used by the controller and they mayor may not be pre-wired on the processor
backp 1ane.
ttThese pins are not used specifically by the MTTC. They are, however, used by the controller logic
circuits. Therefore these pins must be free (not wired).
6-2
60476010 A
PARTS DATA
This section contains the parts lists and
connections for the MTTC and associated cable.
terminal
7
The assembly diagrams in this section reflect the F A464
and both versions of the F A465 MTTCs unless specifically
stated otherwise.
I
' ----
60476010 E
7-1
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\:I r::I CORl'O~nON
ASSEMBLY PARTS UST
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IN
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l'·TE.I'L· I II 1 SIONAL IJUC\"'tNT
Figure 7-1. F A465-B Magnetic Tape Transport Controller Spare Parts List
7-2
60476010E
"
I. IDENTIFY WITH TA6) LA8FL.J tJR SIMIUR ltIE"rI/OD.
NOT£S:UNLESS OTIIERWISG SPECIf:.IED.
/::11:\ CONTRPL DATA
\::t ~ CORJ'ORi\TION
r-------.-Tl.---------------~~--~----~--~--~~2
rQ_6_AQ=~=n=T~:-__~N~.---+~-+.~--------._--••-.-.~._-_-_~~----~~~~~~~~--~-_
__~~~~~~~F
....
=~: ----~
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1 ..
I.e, r:~ r~"lC' o,C:C:Y_1 CTT/""C'... o,TTFI:' C"WT
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nrl1t
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Q~'_lrTT/"rC:~ATT"P
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y",
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== =-:
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.~
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1I ..... t .,
............
c:c","
\, _.
hT<:~r:C;T
"I:'~
rl:' l r"'€ rTr: ... c:
FT"I' '-1,,,,01"<> •
=
' ' 1:'1'\
Figure 7-2. Magnetic Tape Transport Controller, Assembly Parts List
60476010 E
7-3
TABLE
I
£
NOMff.JAL DIMENSION 10L TABLE
DIM (lJJCHES)
TOL (IIJCHES)
O.S TO 5.99
-0 + 0.5
b.O THRU 12.99
-0 +1.0
13.0 THIW 4B.99
-0 +2.0
49.0 THRU
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enO
UP
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,,,.q,
t
TITLE
CRBLE f.lSSYL.eTT/ FORM~TT£I? CONTI?OI..L£R
SHEET
B
1CJTF:,s :
£
&
IDENTIFY
C.118L.E PER CDC oJTD
& flTTRCH
LRI3EL~
(FIN ",7.B.~VO ~ 11) TO SIDE:; OF CONNECTORS RJ SHOIVN ON ISH
4. FILL fiLL UNUSED CRVITIES
£
1.30.008 WITH 1AF6 FRClUTY CJJDE.
INSERT PIN EXTENDER (F/N") INTO CONNECTOR CR'IITY FOR PIN 249 RS SHOWN ON ISH 5.
IN
'II- END CONNECTORS (FIN 21)
5.
WITH CRlIM£D CONTnCT.s(F/N
/4).
TERIAINRTF IILL uND liND UNUSED CONDlJC.TORS liT ~R"END liS SHOWN I1T JH 4 ([ErRIL B). rHESE
TERMINATloNJ CONQI,sT OF FIVE !SOLDER C!ONNECTIONS LOt:IJT£D RPPROX IU SHOWN. [RCIJ .soLD£~
ClWNECTION IS SLEEVED BY FIN I RND IS t!ONNECT£D ~y liN ADDED WIRE (F/N4) TO T!-I£
PIN /)£S/uHIlTED IN THE WIRE UST. FOR EXRMPLE, THE GND -II JOLDE~ CONNEC TION IS WIRED
TO MPI-~.
& GND RND UNUSED WIRES liT -8" END TO· BE. SOLDeReD TO 6ND STRIP liS SHOWN
&. RUBBER STflMP • P" NO'S ON JlDE OF' CONNECTOR RS ,sHOWN ON SH 6.
B. a.% (F'/N 20) fiND I:JTTIICH
ON .sH 45 •
ro CRBLL
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CLOSE TO ~HRINK oSL£EVING WITH CRBLE n£ (F/N/5). TIJEN F'OHM n.sHNlOtJTI-I 1:J1 07HER
END. RND ,J1R£TCH AND tSMOOTII THe
SLE£VIN6 DOWN ITS EN77I?£ L£NGTII TOWI:JRDS
THe lAP I, MPZ OR MP4 E.ND. BEF'ORE TIE. WRRPPIN6 THIiT END , CHEC.K PROPeR DISTRNC£
DR .5PRClN6 RND RDIlJST RS NECE,sJ;IlRY THE IJMOUNT Or .5L£EVlNG {"OLDED INTO THE
FISHMtxJTII •
& UNLESS OTHERWISE. SPECIFIED,
NOTE:
ALL MOM/NAL Of ME I.JSI 0 IJS COMPLY Wln-l TABLE I.
MITC CABLE TERMrNATrON DATA IS APPLICABLE TO CABLE ASSEMBLIES
89600200, 89604657, 96720707, and 96721485.
Figure 7-3. F A465-B Magnetic Tape Transport Controller Cable Assembly (Sheet 1 of 7)
7-4
60476010 E
!
wt.
F~
"
5EE DETAIL
&.
DOCUMENT NO
4
SHeeT
CIU31.£
B
RE',
Sf;J72148S/d9
8
DR~/N WIRE
(WRRP 10 TURNS RROUND
CABLE JACKE.T)
~EF
DETRIL
C
TYP(2PL)
G~~~O:D
DETRll B
(TYPIC'lll WIRIN6 FOR GND -A.-B.-C,-D4,-E)
I
\
Figure 7-3. F A465-B Magnetic Tape Transport Controller Cable Assembly (Sheet 2 of 7)
60476010 E
7-5
DOCUMENT NO
SHEET
f
MPf. MP2 MP4
S
PE V
536721485/139
WIRING END
II
VIEW
PIN.
PIN 78
PIN 201
PIN Z7B
PINtE25
PIN .302
PIN 25
PIN 102
NfP4
"'PI
DOCUMENT NO
SHEET
6
9(0 72 14B 5/89
REv
A
,
1lt2
SIDE 8
GND STRIP
&.
WIRING
VieW or:
P3, P4,f PS
CONNECTOR ASSY
P~,P4,IP5
Figure 7-3. F A465-B Magnetic Tape Transport Controller Cable Assembly (Sheet 3 of 7)
7-6
60476010:E
Figure 7-3. F A465-B Magnetic Tape Transport Controller Cable Assembly (Sheet 4 of 7)
60476010 E
7-7
DOCUMeNT NO
WL
9fJ72/4SS/89
Rev
A
ACCESS
Figure 7-3. F A465-B Magnetic Tape Transport Controller Cable Assembly (Sheet 5 of 7)
7-8
60416010 E
DOCUMENT NO
"
12.
REv
967214t8S/89
WL
A
ACCESS
WL
9~7Z14d5/89
A
ACCESS
1Jt.J.L_______ _
1----L-'~_+_+_+_~~.!IIZ--.4_+_+-=--~:!..604-____1I_U'.J.L..L-_I_=---~~-_+~~-----.--.
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Figure 7-3. F A465-B Magnetic Tape Transport Controller Cable Assembly (Sheet 6 of 7)
I
''-.....
60476010 E
7-9
Figure 7-3. F A465-B Magnetic Tape Transport Controller Cable Assembly (Sheet 7 of 7)
7-10
60476010 E
/
CAUTION:
TI.I PI•••• T••• I (LICT •• IT.TlC
11.lITill .IIICII IIIC ••• , IE
PI •••• I.TIY ••••• 1. I' '.PIOPEI
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IITU.'. II C'C IT. 1.11.1111 CIC 1III
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III
PWA -
81PWT
crr/F"ORMATreR
CONTROL LE'R
".,' z
Rfv
A
NO'ES:
1.
MARK P.IT NO. PER CDC SPEC 88818000.
INSTALL (FIN' ) ROM SET I'EI TABLE Bnow:
INSUIE I.C. PIN 1 IATCIES SOCKET PIN 1
10M SET
PART NO .
LOCATION
.9f17550~
CDI
9f47S50~~
CDZ
CD3
8~7.s50f47
SfiJ75:jO~6
C04
Figure 7-4. Magnetic Tape Transport Controller PROM Set (Sheet 1 of 2)
60476010 E
7-11
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A
I
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.........
1 ,
o-'7C;~n-.~
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or.
Ln~Tr.-lrTT/~"Ok
('r-'I,o"LLFo
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l~
fl>'
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"'T,,,. . IO'''T
~l,.n
'T~~J" '"
~ II""'~" ~
c,; .. "
Figure 7-4. Magnetic Tape Transport Controller PROM Set (Sheet 2 of 2)
7-12
60476010 E
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