Intel® 64 And IA 32 Architectures Optimization Reference Manual

• Chapter 1 Introduction
  • 1.1 Tuning Your Application
  • 1.2 About This Manual
  • 1.3 Related Information
• Chapter 2 Intel® 64 and IA-32 Processor Architectures
  • 2.1 The Skylake Microarchitecture
    • 2.1.1 The Front End
    • 2.1.2 The Out-of-Order Execution Engine
    • 2.1.3 Cache and Memory Subsystem
  • 2.2 The Haswell Microarchitecture
    • 2.2.1 The Front End
    • 2.2.2 The Out-of-Order Engine
    • 2.2.3 Execution Engine
    • 2.2.4 Cache and Memory Subsystem
      • 2.2.4.1 Load and Store Operation Enhancements
    • 2.2.5 The Haswell-E Microarchitecture
    • 2.2.6 The Broadwell Microarchitecture
  • 2.3 Intel® Microarchitecture Code Name Sandy Bridge
    • 2.3.1 Intel® Microarchitecture Code Name Sandy Bridge Pipeline Overview
    • 2.3.2 The Front End
      • 2.3.2.1 Legacy Decode Pipeline
      • 2.3.2.2 Decoded ICache
      • 2.3.2.3 Branch Prediction
      • 2.3.2.4 Micro-op Queue and the Loop Stream Detector (LSD)
    • 2.3.3 The Out-of-Order Engine
      • 2.3.3.1 Renamer
      • 2.3.3.2 Scheduler
    • 2.3.4 The Execution Core
    • 2.3.5 Cache Hierarchy
      • 2.3.5.1 Load and Store Operation Overview
      • 2.3.5.2 L1 DCache
      • 2.3.5.3 Ring Interconnect and Last Level Cache
      • 2.3.5.4 Data Prefetching
    • 2.3.6 System Agent
    • 2.3.7 Intel® Microarchitecture Code Name Ivy Bridge
  • 2.4 Intel® Core™ Microarchitecture and Enhanced Intel® Core™ Microarchitecture
    • 2.4.1 Intel® Core™ Microarchitecture Pipeline Overview
    • 2.4.2 Front End
      • 2.4.2.1 Branch Prediction Unit
      • 2.4.2.2 Instruction Fetch Unit
      • 2.4.2.3 Instruction Queue (IQ)
      • 2.4.2.4 Instruction Decode
      • 2.4.2.5 Stack Pointer Tracker
      • 2.4.2.6 Micro-fusion
    • 2.4.3 Execution Core
      • 2.4.3.1 Issue Ports and Execution Units
    • 2.4.4 Intel® Advanced Memory Access
      • 2.4.4.1 Loads and Stores
      • 2.4.4.2 Data Prefetch to L1 caches
      • 2.4.4.3 Data Prefetch Logic
      • 2.4.4.4 Store Forwarding
      • 2.4.4.5 Memory Disambiguation
    • 2.4.5 Intel® Advanced Smart Cache
      • 2.4.5.1 Loads
      • 2.4.5.2 Stores
  • 2.5 Intel® Microarchitecture Code Name Nehalem
    • 2.5.1 Microarchitecture Pipeline
    • 2.5.2 Front End Overview
    • 2.5.3 Execution Engine
      • 2.5.3.1 Issue Ports and Execution Units
    • 2.5.4 Cache and Memory Subsystem
    • 2.5.5 Load and Store Operation Enhancements
      • 2.5.5.1 Efficient Handling of Alignment Hazards
      • 2.5.5.2 Store Forwarding Enhancement
    • 2.5.6 REP String Enhancement
    • 2.5.7 Enhancements for System Software
    • 2.5.8 Efficiency Enhancements for Power Consumption
    • 2.5.9 Hyper-Threading Technology Support in Intel® Microarchitecture Code Name Nehalem
  • 2.6 Intel® Hyper-Threading Technology
    • 2.6.1 Processor Resources and HT Technology
      • 2.6.1.1 Replicated Resources
      • 2.6.1.2 Partitioned Resources
      • 2.6.1.3 Shared Resources
    • 2.6.2 Microarchitecture Pipeline and HT Technology
    • 2.6.3 Front End Pipeline
    • 2.6.4 Execution Core
    • 2.6.5 Retirement
  • 2.7 Intel® 64 Architecture
  • 2.8 SIMD Technology
  • 2.9 Summary of SIMD Technologies and Application Level Extensions
    • 2.9.1 MMX™ Technology
    • 2.9.2 Streaming SIMD Extensions
    • 2.9.3 Streaming SIMD Extensions 2
    • 2.9.4 Streaming SIMD Extensions 3
    • 2.9.5 Supplemental Streaming SIMD Extensions 3
    • 2.9.6 SSE4.1
    • 2.9.7 SSE4.2
    • 2.9.8 AESNI and PCLMULQDQ
    • 2.9.9 Intel® Advanced Vector Extensions
    • 2.9.10 Half-Precision Floating-Point Conversion (F16C)
    • 2.9.11 RDRAND
    • 2.9.12 Fused-Multiply-ADD (FMA) Extensions
    • 2.9.13 Intel AVX2
    • 2.9.14 General-Purpose Bit-Processing Instructions
    • 2.9.15 Intel® Transactional Synchronization Extensions
    • 2.9.16 RDSEED
    • 2.9.17 ADCX and ADOX Instructions
• Chapter 3 General Optimization Guidelines
  • 3.1 Performance Tools
    • 3.1.1 Intel® C++ and Fortran Compilers
    • 3.1.2 General Compiler Recommendations
    • 3.1.3 VTune™ Performance Analyzer
  • 3.2 Processor Perspectives
    • 3.2.1 CPUID Dispatch Strategy and Compatible Code Strategy
    • 3.2.2 Transparent Cache-Parameter Strategy
    • 3.2.3 Threading Strategy and Hardware Multithreading Support
  • 3.3 Coding Rules, Suggestions and Tuning Hints
  • 3.4 Optimizing the Front End
    • 3.4.1 Branch Prediction Optimization
      • 3.4.1.1 Eliminating Branches
      • 3.4.1.2 Spin-Wait and Idle Loops
      • 3.4.1.3 Static Prediction
      • 3.4.1.4 Inlining, Calls and Returns
      • 3.4.1.5 Code Alignment
      • 3.4.1.6 Branch Type Selection
      • 3.4.1.7 Loop Unrolling
      • 3.4.1.8 Compiler Support for Branch Prediction
    • 3.4.2 Fetch and Decode Optimization
      • 3.4.2.1 Optimizing for Micro-fusion
      • 3.4.2.2 Optimizing for Macro-fusion
      • 3.4.2.3 Length-Changing Prefixes (LCP)
      • 3.4.2.4 Optimizing the Loop Stream Detector (LSD)
      • 3.4.2.5 Exploit LSD Micro-op Emission Bandwidth in Intel® Microarchitecture Code Name Sandy Bridge
      • 3.4.2.6 Optimization for Decoded ICache
      • 3.4.2.7 Other Decoding Guidelines
  • 3.5 Optimizing the Execution Core
    • 3.5.1 Instruction Selection
      • 3.5.1.1 Use of the INC and DEC Instructions
      • 3.5.1.2 Integer Divide
      • 3.5.1.3 Using LEA
      • 3.5.1.4 ADC and SBB in Intel® Microarchitecture Code Name Sandy Bridge
      • 3.5.1.5 Bitwise Rotation
      • 3.5.1.6 Variable Bit Count Rotation and Shift
      • 3.5.1.7 Address Calculations
      • 3.5.1.8 Clearing Registers and Dependency Breaking Idioms
      • 3.5.1.9 Compares
      • 3.5.1.10 Using NOPs
      • 3.5.1.11 Mixing SIMD Data Types
      • 3.5.1.12 Spill Scheduling
      • 3.5.1.13 Zero-Latency MOV Instructions
    • 3.5.2 Avoiding Stalls in Execution Core
      • 3.5.2.1 ROB Read Port Stalls
      • 3.5.2.2 Writeback Bus Conflicts
      • 3.5.2.3 Bypass between Execution Domains
      • 3.5.2.4 Partial Register Stalls
      • 3.5.2.5 Partial XMM Register Stalls
      • 3.5.2.6 Partial Flag Register Stalls
      • 3.5.2.7 Floating-Point/SIMD Operands
    • 3.5.3 Vectorization
    • 3.5.4 Optimization of Partially Vectorizable Code
      • 3.5.4.1 Alternate Packing Techniques
      • 3.5.4.2 Simplifying Result Passing
      • 3.5.4.3 Stack Optimization
      • 3.5.4.4 Tuning Considerations
  • 3.6 Optimizing Memory Accesses
    • 3.6.1 Load and Store Execution Bandwidth
      • 3.6.1.1 Make Use of Load Bandwidth in Intel® Microarchitecture Code Name Sandy Bridge
      • 3.6.1.2 L1D Cache Latency in Intel® Microarchitecture Code Name Sandy Bridge
      • 3.6.1.3 Handling L1D Cache Bank Conflict
    • 3.6.2 Minimize Register Spills
    • 3.6.3 Enhance Speculative Execution and Memory Disambiguation
    • 3.6.4 Alignment
    • 3.6.5 Store Forwarding
      • 3.6.5.1 Store-to-Load-Forwarding Restriction on Size and Alignment
      • 3.6.5.2 Store-forwarding Restriction on Data Availability
    • 3.6.6 Data Layout Optimizations
    • 3.6.7 Stack Alignment
    • 3.6.8 Capacity Limits and Aliasing in Caches
      • 3.6.8.1 Capacity Limits in Set-Associative Caches
      • 3.6.8.2 Aliasing Cases in the Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo and Intel® Core™ 2 Duo Processors
    • 3.6.9 Mixing Code and Data
      • 3.6.9.1 Self-modifying Code
      • 3.6.9.2 Position Independent Code
    • 3.6.10 Write Combining
    • 3.6.11 Locality Enhancement
    • 3.6.12 Minimizing Bus Latency
    • 3.6.13 Non-Temporal Store Bus Traffic
  • 3.7 Prefetching
    • 3.7.1 Hardware Instruction Fetching and Software Prefetching
    • 3.7.2 Hardware Prefetching for First-Level Data Cache
    • 3.7.3 Hardware Prefetching for Second-Level Cache
    • 3.7.4 Cacheability Instructions
    • 3.7.5 REP Prefix and Data Movement
    • 3.7.6 Enhanced REP MOVSB and STOSB operation (ERMSB)
      • 3.7.6.1 Memcpy Considerations
      • 3.7.6.2 Memmove Considerations
      • 3.7.6.3 Memset Considerations
  • 3.8 Floating-point Considerations
    • 3.8.1 Guidelines for Optimizing Floating-point Code
    • 3.8.2 Microarchitecture Specific Considerations
      • 3.8.2.1 Long-Latency FP Instructions
      • 3.8.2.2 Miscellaneous Instructions
    • 3.8.3 Floating-point Modes and Exceptions
      • 3.8.3.1 Floating-point Exceptions
      • 3.8.3.2 Dealing with floating-point exceptions in x87 FPU code
      • 3.8.3.3 Floating-point Exceptions in SSE/SSE2/SSE3 Code
    • 3.8.4 Floating-point Modes
      • 3.8.4.1 Rounding Mode
      • 3.8.4.2 Precision
    • 3.8.5 x87 vs. Scalar SIMD Floating-point Trade-offs
      • 3.8.5.1 Scalar SSE/SSE2
      • 3.8.5.2 Transcendental Functions
  • 3.9 Maximizing PCIe Performance
• Chapter 4 Coding for SIMD Architectures
  • 4.1 Checking for Processor Support of SIMD Technologies
    • 4.1.1 Checking for MMX Technology Support
    • 4.1.2 Checking for Streaming SIMD Extensions Support
    • 4.1.3 Checking for Streaming SIMD Extensions 2 Support
    • 4.1.4 Checking for Streaming SIMD Extensions 3 Support
    • 4.1.5 Checking for Supplemental Streaming SIMD Extensions 3 Support
    • 4.1.6 Checking for SSE4.1 Support
    • 4.1.7 Checking for SSE4.2 Support
    • 4.1.8 DetectiON of PCLMULQDQ and AESNI Instructions
    • 4.1.9 Detection of AVX Instructions
    • 4.1.10 Detection of VEX-Encoded AES and VPCLMULQDQ
    • 4.1.11 Detection of F16C Instructions
    • 4.1.12 Detection of FMA
    • 4.1.13 Detection of AVX2
  • 4.2 Considerations for Code Conversion to SIMD Programming
    • 4.2.1 Identifying Hot Spots
    • 4.2.2 Determine If Code Benefits by Conversion to SIMD Execution
  • 4.3 Coding Techniques
    • 4.3.1 Coding Methodologies
      • 4.3.1.1 Assembly
      • 4.3.1.2 Intrinsics
      • 4.3.1.3 Classes
      • 4.3.1.4 Automatic Vectorization
  • 4.4 Stack and Data Alignment
    • 4.4.1 Alignment and Contiguity of Data Access Patterns
      • 4.4.1.1 Using Padding to Align Data
      • 4.4.1.2 Using Arrays to Make Data Contiguous
    • 4.4.2 Stack Alignment For 128-bit SIMD Technologies
    • 4.4.3 Data Alignment for MMX Technology
    • 4.4.4 Data Alignment for 128-bit data
      • 4.4.4.1 Compiler-Supported Alignment
  • 4.5 Improving Memory Utilization
    • 4.5.1 Data Structure Layout
    • 4.5.2 Strip-Mining
    • 4.5.3 Loop Blocking
  • 4.6 Instruction Selection
    • 4.6.1 SIMD Optimizations and Microarchitectures
  • 4.7 Tuning the Final Application
• Chapter 5 Optimizing for SIMD Integer Applications
  • 5.1 General Rules on SIMD Integer Code
  • 5.2 Using SIMD Integer with x87 Floating-point
    • 5.2.1 Using the EMMS Instruction
    • 5.2.2 Guidelines for Using EMMS Instruction
  • 5.3 Data Alignment
  • 5.4 Data Movement Coding Techniques
    • 5.4.1 Unsigned Unpack
    • 5.4.2 Signed Unpack
    • 5.4.3 Interleaved Pack with Saturation
    • 5.4.4 Interleaved Pack without Saturation
    • 5.4.5 Non-Interleaved Unpack
    • 5.4.6 Extract Data Element
    • 5.4.7 Insert Data Element
    • 5.4.8 Non-Unit Stride Data Movement
    • 5.4.9 Move Byte Mask to Integer
    • 5.4.10 Packed Shuffle Word for 64-bit Registers
    • 5.4.11 Packed Shuffle Word for 128-bit Registers
    • 5.4.12 Shuffle Bytes
    • 5.4.13 Conditional Data Movement
    • 5.4.14 Unpacking/interleaving 64-bit Data in 128-bit Registers
    • 5.4.15 Data Movement
    • 5.4.16 Conversion Instructions
  • 5.5 Generating Constants
  • 5.6 Building Blocks
    • 5.6.1 Absolute Difference of Unsigned Numbers
    • 5.6.2 Absolute Difference of Signed Numbers
    • 5.6.3 Absolute Value
    • 5.6.4 Pixel Format Conversion
    • 5.6.5 Endian Conversion
    • 5.6.6 Clipping to an Arbitrary Range [High, Low]
      • 5.6.6.1 Highly Efficient Clipping
      • 5.6.6.2 Clipping to an Arbitrary Unsigned Range [High, Low]
    • 5.6.7 Packed Max/Min of Byte, Word and Dword
    • 5.6.8 Packed Multiply Integers
    • 5.6.9 Packed Sum of Absolute Differences
    • 5.6.10 MPSADBW and PHMINPOSUW
    • 5.6.11 Packed Average (Byte/Word)
    • 5.6.12 Complex Multiply by a Constant
    • 5.6.13 Packed 64-bit Add/Subtract
    • 5.6.14 128-bit Shifts
    • 5.6.15 PTEST and Conditional Branch
    • 5.6.16 Vectorization of Heterogeneous Computations across Loop Iterations
    • 5.6.17 Vectorization of Control Flows in Nested Loops
  • 5.7 Memory Optimizations
    • 5.7.1 Partial Memory Accesses
      • 5.7.1.1 Supplemental Techniques for Avoiding Cache Line Splits
    • 5.7.2 Increasing Bandwidth of Memory Fills and Video Fills
      • 5.7.2.1 Increasing Memory Bandwidth Using the MOVDQ Instruction
      • 5.7.2.2 Increasing Memory Bandwidth by Loading and Storing to and from the Same DRAM Page
      • 5.7.2.3 Increasing UC and WC Store Bandwidth by Using Aligned Stores
    • 5.7.3 Reverse Memory Copy
  • 5.8 Converting from 64-bit to 128-bit SIMD Integers
    • 5.8.1 SIMD Optimizations and Microarchitectures
      • 5.8.1.1 Packed SSE2 Integer versus MMX Instructions
      • 5.8.1.2 Work-around for False Dependency Issue
  • 5.9 Tuning Partially Vectorizable Code
  • 5.10 Parallel Mode AES Encryption and Decryption
    • 5.10.1 AES Counter Mode of Operation
    • 5.10.2 AES Key Expansion Alternative
    • 5.10.3 Enhancement in Intel Microarchitecture Code Name Haswell
      • 5.10.3.1 AES and Multi-Buffer Cryptographic Throughput
      • 5.10.3.2 PCLMULQDQ Improvement
  • 5.11 Light-Weight Decompression and Database Processing
    • 5.11.1 Reduced Dynamic Range Datasets
    • 5.11.2 Compression and Decompression Using SIMD Instructions
• Chapter 6 Optimizing for SIMD Floating-point Applications
  • 6.1 General Rules for SIMD Floating-point Code
  • 6.2 Planning Considerations
  • 6.3 Using SIMD Floating-point with x87 Floating-point
  • 6.4 Scalar Floating-point Code
  • 6.5 Data Alignment
    • 6.5.1 Data Arrangement
      • 6.5.1.1 Vertical versus Horizontal Computation
      • 6.5.1.2 Data Swizzling
      • 6.5.1.3 Data Deswizzling
      • 6.5.1.4 Horizontal ADD Using SSE
    • 6.5.2 Use of CVTTPS2PI/CVTTSS2SI Instructions
    • 6.5.3 Flush-to-Zero and Denormals-are-Zero Modes
  • 6.6 SIMD Optimizations and Microarchitectures
    • 6.6.1 SIMD Floating-point Programming Using SSE3
      • 6.6.1.1 SSE3 and Complex Arithmetics
      • 6.6.1.2 Packed Floating-Point Performance in Intel Core Duo Processor
    • 6.6.2 Dot Product and Horizontal SIMD Instructions
    • 6.6.3 Vector Normalization
    • 6.6.4 Using Horizontal SIMD Instruction Sets and Data Layout
      • 6.6.4.1 SOA and Vector Matrix Multiplication
• Chapter 7 Optimizing Cache Usage
  • 7.1 General Prefetch Coding Guidelines
  • 7.2 Prefetch and Cacheability Instructions
  • 7.3 Prefetch
    • 7.3.1 Software Data Prefetch
    • 7.3.2 Prefetch Instructions
    • 7.3.3 Prefetch and Load Instructions
  • 7.4 Cacheability Control
    • 7.4.1 The Non-temporal Store Instructions
      • 7.4.1.1 Fencing
      • 7.4.1.2 Streaming Non-temporal Stores
      • 7.4.1.3 Memory Type and Non-temporal Stores
      • 7.4.1.4 Write-Combining
    • 7.4.2 Streaming Store Usage Models
      • 7.4.2.1 Coherent Requests
      • 7.4.2.2 Non-coherent requests
    • 7.4.3 Streaming Store Instruction Descriptions
    • 7.4.4 The Streaming Load Instruction
    • 7.4.5 FENCE Instructions
      • 7.4.5.1 SFENCE Instruction
      • 7.4.5.2 LFENCE Instruction
      • 7.4.5.3 MFENCE Instruction
    • 7.4.6 CLFLUSH Instruction
    • 7.4.7 CLFLUSHOPT Instruction
  • 7.5 Memory Optimization Using Prefetch
    • 7.5.1 Software-Controlled Prefetch
    • 7.5.2 Hardware Prefetch
    • 7.5.3 Example of Effective Latency Reduction with Hardware Prefetch
    • 7.5.4 Example of Latency Hiding with S/W Prefetch Instruction
    • 7.5.5 Software Prefetching Usage Checklist
    • 7.5.6 Software Prefetch Scheduling Distance
    • 7.5.7 Software Prefetch Concatenation
    • 7.5.8 Minimize Number of Software Prefetches
    • 7.5.9 Mix Software Prefetch with Computation Instructions
    • 7.5.10 Software Prefetch and Cache Blocking Techniques
    • 7.5.11 Hardware Prefetching and Cache Blocking Techniques
    • 7.5.12 Single-pass versus Multi-pass Execution
  • 7.6 Memory Optimization using Non-Temporal Stores
    • 7.6.1 Non-temporal Stores and Software Write-Combining
    • 7.6.2 Cache Management
      • 7.6.2.1 Video Encoder
      • 7.6.2.2 Video Decoder
      • 7.6.2.3 Conclusions from Video Encoder and Decoder Implementation
      • 7.6.2.4 Optimizing Memory Copy Routines
      • 7.6.2.5 TLB Priming
      • 7.6.2.6 Using the 8-byte Streaming Stores and Software Prefetch
      • 7.6.2.7 Using 16-byte Streaming Stores and Hardware Prefetch
      • 7.6.2.8 Performance Comparisons of Memory Copy Routines
    • 7.6.3 Deterministic Cache Parameters
      • 7.6.3.1 Cache Sharing Using Deterministic Cache Parameters
      • 7.6.3.2 Cache Sharing in Single-Core or Multicore
      • 7.6.3.3 Determine Prefetch Stride
• Chapter 8 Multicore and Hyper-Threading Technology
  • 8.1 Performance and Usage Models
    • 8.1.1 Multithreading
    • 8.1.2 Multitasking Environment
  • 8.2 Programming Models and Multithreading
    • 8.2.1 Parallel Programming Models
      • 8.2.1.1 Domain Decomposition
    • 8.2.2 Functional Decomposition
    • 8.2.3 Specialized Programming Models
      • 8.2.3.1 Producer-Consumer Threading Models
    • 8.2.4 Tools for Creating Multithreaded Applications
      • 8.2.4.1 Programming with OpenMP Directives
      • 8.2.4.2 Automatic Parallelization of Code
      • 8.2.4.3 Supporting Development Tools
  • 8.3 Optimization Guidelines
    • 8.3.1 Key Practices of Thread Synchronization
    • 8.3.2 Key Practices of System Bus Optimization
    • 8.3.3 Key Practices of Memory Optimization
    • 8.3.4 Key Practices of Execution Resource Optimization
    • 8.3.5 Generality and Performance Impact
  • 8.4 Thread Synchronization
    • 8.4.1 Choice of Synchronization Primitives
    • 8.4.2 Synchronization for Short Periods
    • 8.4.3 Optimization with Spin-Locks
    • 8.4.4 Synchronization for Longer Periods
      • 8.4.4.1 Avoid Coding Pitfalls in Thread Synchronization
    • 8.4.5 Prevent Sharing of Modified Data and False-Sharing
    • 8.4.6 Placement of Shared Synchronization Variable
    • 8.4.7 Pause Latency in Skylake Microarchitecture
  • 8.5 System Bus Optimization
    • 8.5.1 Conserve Bus Bandwidth
    • 8.5.2 Understand the Bus and Cache Interactions
    • 8.5.3 Avoid Excessive Software Prefetches
    • 8.5.4 Improve Effective Latency of Cache Misses
    • 8.5.5 Use Full Write Transactions to Achieve Higher Data Rate
  • 8.6 Memory Optimization
    • 8.6.1 Cache Blocking Technique
    • 8.6.2 Shared-Memory Optimization
      • 8.6.2.1 Minimize Sharing of Data between Physical Processors
      • 8.6.2.2 Batched Producer-Consumer Model
    • 8.6.3 Eliminate 64-KByte Aliased Data Accesses
  • 8.7 Front end Optimization
    • 8.7.1 Avoid Excessive Loop Unrolling
  • 8.8 Affinities and Managing Shared Platform Resources
    • 8.8.1 Topology Enumeration of Shared Resources
    • 8.8.2 Non-Uniform Memory Access
  • 8.9 Optimization of Other Shared Resources
    • 8.9.1 Expanded Opportunity for HT Optimization
• Chapter 9 64-bit Mode Coding Guidelines
  • 9.1 Introduction
  • 9.2 Coding Rules Affecting 64-bit Mode
    • 9.2.1 Use Legacy 32-Bit Instructions When Data Size Is 32 Bits
    • 9.2.2 Use Extra Registers to Reduce Register Pressure
    • 9.2.3 Effective Use of 64-Bit by 64-Bit Multiplies
    • 9.2.4 Replace 128-bit Integer Division with 128-bit Multiplies
    • 9.2.5 Sign Extension to Full 64-Bits
  • 9.3 Alternate Coding Rules for 64-Bit Mode
    • 9.3.1 Use 64-Bit Registers Instead of Two 32-Bit Registers for 64-Bit Arithmetic Result
    • 9.3.2 CVTSI2SS and CVTSI2SD
    • 9.3.3 Using Software Prefetch
• Chapter 10 SSE4.2 and SIMD Programming For Text- Processing/Lexing/Parsing
  • 10.1 SSE4.2 String and Text Instructions
    • 10.1.1 CRC32
  • 10.2 Using SSE4.2 String and Text Instructions
    • 10.2.1 Unaligned Memory Access and Buffer Size Management
    • 10.2.2 Unaligned Memory Access and String Library
  • 10.3 SSE4.2 Application Coding Guideline and Examples
    • 10.3.1 Null Character Identification (Strlen equivalent)
    • 10.3.2 White-Space-Like Character Identification
    • 10.3.3 Substring Searches
    • 10.3.4 String Token Extraction and Case Handling
    • 10.3.5 Unicode Processing and PCMPxSTRy
    • 10.3.6 Replacement String Library Function Using SSE4.2
  • 10.4 SSE4.2 Enabled Numerical and Lexical Computation
  • 10.5 Numerical Data Conversion to ASCII Format
    • 10.5.1 Large Integer Numeric Computation
      • 10.5.1.1 MULX Instruction and Large Integer Numeric Computation
• Chapter 11 Optimizations for Intel® AVX, FMA and AVX2
  • 11.1 Intel® AVX Intrinsics Coding
    • 11.1.1 Intel® AVX Assembly Coding
  • 11.2 Non-Destructive Source (NDS)
  • 11.3 Mixing AVX Code with SSE Code
    • 11.3.1 Mixing Intel® AVX and Intel SSE in Function Calls
  • 11.4 128-Bit Lane Operation and AVX
    • 11.4.1 Programming With the Lane Concept
    • 11.4.2 Strided Load Technique
    • 11.4.3 The Register Overlap Technique
  • 11.5 Data Gather and Scatter
    • 11.5.1 Data Gather
    • 11.5.2 Data Scatter
  • 11.6 Data Alignment for Intel® AVX
    • 11.6.1 Align Data to 32 Bytes
    • 11.6.2 Consider 16-Byte Memory Access when Memory is Unaligned
    • 11.6.3 Prefer Aligned Stores Over Aligned Loads
  • 11.7 L1D Cache LIne Replacements
  • 11.8 4K Aliasing
  • 11.9 Conditional SIMD Packed Loads and Stores
    • 11.9.1 Conditional Loops
  • 11.10 Mixing Integer and Floating-Point Code
  • 11.11 Handling Port 5 Pressure
    • 11.11.1 Replace Shuffles with Blends
    • 11.11.2 Design Algorithm With Fewer Shuffles
    • 11.11.3 Perform Basic Shuffles on Load Ports
  • 11.12 Divide and Square Root Operations
    • 11.12.1 Single-Precision Divide
    • 11.12.2 Single-Precision Reciprocal Square Root
    • 11.12.3 Single-Precision Square Root
  • 11.13 Optimization of Array Sub Sum Example
  • 11.14 Half-Precision Floating-Point Conversions
    • 11.14.1 Packed Single-Precision to Half-Precision Conversion
    • 11.14.2 Packed Half-Precision to Single-Precision Conversion
    • 11.14.3 Locality Consideration for using Half-Precision FP to Conserve Bandwidth
  • 11.15 Fused Multiply-Add (FMA) Instructions Guidelines
    • 11.15.1 Optimizing Throughput with FMA and Floating-Point Add/MUL
    • 11.15.2 Optimizing Throughput with Vector Shifts
  • 11.16 AVX2 Optimization Guidelines
    • 11.16.1 Multi-Buffering and AVX2
    • 11.16.2 Modular Multiplication and AVX2
    • 11.16.3 Data Movement Considerations
      • 11.16.3.1 SIMD Heuristics to implement Memcpy()
      • 11.16.3.2 Memcpy() Implementation Using Enhanced REP MOVSB
      • 11.16.3.3 Memset() Implementation Considerations
      • 11.16.3.4 Hoisting Memcpy/Memset Ahead of Consuming Code
      • 11.16.3.5 256-bit Fetch versus Two 128-bit Fetches
      • 11.16.3.6 Mixing MULX and AVX2 Instructions
    • 11.16.4 Considerations for Gather Instructions
      • 11.16.4.1 Strided Loads
      • 11.16.4.2 Adjacent Loads
    • 11.16.5 AVX2 Conversion Remedy to MMX Instruction Throughput Limitation
• Chapter 12 Intel® TSX Recommendations
  • 12.1 Introduction
    • 12.1.1 Optimization Outline
  • 12.2 Application-Level Tuning and Optimizations
    • 12.2.1 Existing TSX-enabled Locking Libraries
      • 12.2.1.1 Libraries allowing lock elision for unmodified programs
      • 12.2.1.2 Libraries requiring program modifications
    • 12.2.2 Initial Checks
    • 12.2.3 Run and Profile the Application
    • 12.2.4 Minimize Transactional Aborts
      • 12.2.4.1 Transactional Aborts due to Data Conflicts
      • 12.2.4.2 Transactional Aborts due to Limited Transactional Resources
      • 12.2.4.3 Lock Elision Specific Transactional Aborts
      • 12.2.4.4 HLE Specific Transactional Aborts
      • 12.2.4.5 Miscellaneous Transactional Aborts
    • 12.2.5 Using Transactional-Only Code Paths
    • 12.2.6 Dealing with Transactional Regions or Paths that Abort at a High Rate
      • 12.2.6.1 Transitioning to Non-Elided Execution without Aborting
      • 12.2.6.2 Forcing an Early Abort
      • 12.2.6.3 Not Eliding Selected Locks
  • 12.3 Developing an Intel TSX Enabled Synchronization Library
    • 12.3.1 Adding HLE Prefixes
    • 12.3.2 Elision Friendly Critical Section Locks
    • 12.3.3 Using HLE or RTM for Lock Elision
    • 12.3.4 An example wrapper for lock elision using RTM
    • 12.3.5 Guidelines for the RTM fallback handler
    • 12.3.6 Implementing Elision-Friendly Locks using Intel TSX
      • 12.3.6.1 Implementing a Simple Spinlock using HLE
      • 12.3.6.2 Implementing Reader-Writer Locks using Intel TSX
      • 12.3.6.3 Implementing Ticket Locks using Intel TSX
      • 12.3.6.4 Implementing Queue-Based Locks using Intel TSX
    • 12.3.7 Eliding Application-Specific Meta-Locks using Intel TSX
    • 12.3.8 Avoiding Persistent Non-Elided Execution
    • 12.3.9 Reading the Value of an Elided Lock in RTM-based libraries
    • 12.3.10 Intermixing HLE and RTM
  • 12.4 Using the Performance Monitoring Support for Intel TSX
    • 12.4.1 Measuring Transactional Success
    • 12.4.2 Finding locks to elide and verifying all locks are elided.
    • 12.4.3 Sampling Transactional Aborts
    • 12.4.4 Classifying Aborts using a Profiling Tool
    • 12.4.5 XABORT Arguments for RTM fallback handlers
    • 12.4.6 Call Graphs for Transactional Aborts
    • 12.4.7 Last Branch Records and Transactional Aborts
    • 12.4.8 Profiling and Testing Intel TSX Software using the Intel SDE
    • 12.4.9 HLE Specific Performance Monitoring Events
    • 12.4.10 Computing Useful Metrics for Intel TSX
  • 12.5 Performance Guidelines
  • 12.6 Debugging Guidelines
  • 12.7 Common Intrinsics for Intel TSX
    • 12.7.1 RTM C intrinsics
      • 12.7.1.1 Emulated RTM intrinsics on older gcc compatible compilers
    • 12.7.2 HLE intrinsics on gcc and other Linux compatible compilers
      • 12.7.2.1 Generating HLE intrinsics with gcc4.8
      • 12.7.2.2 C++11 atomic support
      • 12.7.2.3 Emulating HLE intrinsics with older gcc-compatible compilers
    • 12.7.3 HLE intrinsics on Windows C/C++ compilers
• Chapter 13 Power Optimization for Mobile Usages
  • 13.1 Overview
  • 13.2 Mobile Usage Scenarios
    • 13.2.1 Intelligent Energy Efficient Software
  • 13.3 ACPI C-States
    • 13.3.1 Processor-Specific C4 and Deep C4 States
    • 13.3.2 Processor-Specific Deep C-States and Intel® Turbo Boost Technology
    • 13.3.3 Processor-Specific Deep C-States for Intel® Microarchitecture Code Name Sandy Bridge
    • 13.3.4 Intel® Turbo Boost Technology 2.0
  • 13.4 Guidelines for Extending Battery Life
    • 13.4.1 Adjust Performance to Meet Quality of Features
    • 13.4.2 Reducing Amount of Work
    • 13.4.3 Platform-Level Optimizations
    • 13.4.4 Handling Sleep State Transitions
    • 13.4.5 Using Enhanced Intel SpeedStep® Technology
    • 13.4.6 Enabling Intel® Enhanced Deeper Sleep
    • 13.4.7 Multicore Considerations
      • 13.4.7.1 Enhanced Intel SpeedStep® Technology
      • 13.4.7.2 Thread Migration Considerations
      • 13.4.7.3 Multicore Considerations for C-States
  • 13.5 Tuning Software for Intelligent Power Consumption
    • 13.5.1 Reduction of Active Cycles
      • 13.5.1.1 Multi-threading to reduce Active Cycles
      • 13.5.1.2 Vectorization
    • 13.5.2 PAUSE and Sleep(0) Loop Optimization
    • 13.5.3 Spin-Wait Loops
    • 13.5.4 Using Event Driven Service Instead of Polling in Code
    • 13.5.5 Reducing Interrupt Rate
    • 13.5.6 Reducing Privileged Time
    • 13.5.7 Setting Context Awareness in the Code
    • 13.5.8 Saving Energy by Optimizing for Performance
  • 13.6 Processor Specific Power Management Optimization for System Software
    • 13.6.1 Power Management Recommendation of Processor-Specific Inactive State Configurations
      • 13.6.1.1 Balancing Power Management and Responsiveness of Inactive To Active State Transitions
• Chapter 14 Intel® Atom™ Microarchitecture and Software Optimization
  • 14.1 Overview
  • 14.2 Intel® Atom™ Microarchitecture
    • 14.2.1 Hyper-Threading Technology Support in Intel® Atom™ Microarchitecture
  • 14.3 Coding Recommendations for Intel® Atom™ Microarchitecture
    • 14.3.1 Optimization for Front End of Intel® Atom™ Microarchitecture
    • 14.3.2 Optimizing the Execution Core
      • 14.3.2.1 Integer Instruction Selection
      • 14.3.2.2 Address Generation
      • 14.3.2.3 Integer Multiply
      • 14.3.2.4 Integer Shift Instructions
      • 14.3.2.5 Partial Register Access
      • 14.3.2.6 FP/SIMD Instruction Selection
    • 14.3.3 Optimizing Memory Access
      • 14.3.3.1 Store Forwarding
      • 14.3.3.2 First-level Data Cache
      • 14.3.3.3 Segment Base
      • 14.3.3.4 String Moves
      • 14.3.3.5 Parameter Passing
      • 14.3.3.6 Function Calls
      • 14.3.3.7 Optimization of Multiply/Add Dependent Chains
      • 14.3.3.8 Position Independent Code
  • 14.4 Instruction Latency
• Chapter 15 Silvermont Microarchitecture and Software Optimization
  • 15.1 Overview
    • 15.1.1 Intel Atom Processor Family Based on the Silvermont Microarchitecture
  • 15.2 Silvermont Microarchitecture
    • 15.2.1 Integer Pipeline
    • 15.2.2 Floating-Point Pipeline
  • 15.3 Coding Recommendations for Silvermont Microarchitecture
    • 15.3.1 Optimizing The Front End
      • 15.3.1.1 Instruction Decoder
      • 15.3.1.2 Front End High IPC Considerations
      • 15.3.1.3 Loop Unrolling and Loop Stream Detector
    • 15.3.2 Optimizing The Execution Core
      • 15.3.2.1 Scheduling
      • 15.3.2.2 Address Generation
      • 15.3.2.3 FP Multiply-Accumulate-Store Execution
      • 15.3.2.4 Integer Multiply Execution
      • 15.3.2.5 Zeroing Idioms
      • 15.3.2.6 Flags usage
      • 15.3.2.7 Instruction Selection
    • 15.3.3 Optimizing Memory Accesses
      • 15.3.3.1 Memory Reissue/Sleep causes
      • 15.3.3.2 Store Forwarding
      • 15.3.3.3 PrefetchW Instruction
      • 15.3.3.4 Cache Line Splits and Alignment
      • 15.3.3.5 Segment Base
      • 15.3.3.6 Copy and String Copy
  • 15.4 Instruction Latency
• Chapter 16 Knights Landing Microarchitecture and Software Optimization
  • 16.1 Knights Landing Microarchitecture
    • 16.1.1 Front End
    • 16.1.2 Out-of-Order Engine
    • 16.1.3 UnTile
  • 16.2 Intel® AVX-512 Coding Recommendations for Knights Landing Microarchitecture
    • 16.2.1 Using Gather and Scatter Instructions
    • 16.2.2 Using Enhanced Reciprocal Instructions
    • 16.2.3 Using AVX-512CD Instructions
    • 16.2.4 Using Intel® Hyper-Threading Technology
    • 16.2.5 Front End Considerations
      • 16.2.5.1 Instruction Decoder
      • 16.2.5.2 Branching Across 4GB Boundary
    • 16.2.6 Integer Execution Considerations
      • 16.2.6.1 Flags usage
      • 16.2.6.2 Integer Division
    • 16.2.7 Optimizing FP and Vector Execution
      • 16.2.7.1 Instruction Selection Considerations
      • 16.2.7.2 Porting Intrinsic From Prior Generation
      • 16.2.7.3 Vectorization Trade-Off Estimation
    • 16.2.8 Memory Optimization
      • 16.2.8.1 Data Alignment
      • 16.2.8.2 Hardware Prefetcher
      • 16.2.8.3 Software Prefetch
      • 16.2.8.4 Memory Execution Cluster
      • 16.2.8.5 Store Forwarding
      • 16.2.8.6 Way, Set Conflicts
      • 16.2.8.7 Streaming Store Versus Regular Store
      • 16.2.8.8 Compiler Switches and Directives
      • 16.2.8.9 Direct Mapped MCDRAM Cache
• Appendix A Application Performance Tools
  • A.1 Compilers
    • A.1.1 Recommended Optimization Settings for Intel® 64 and IA-32 Processors
    • A.1.2 Vectorization and Loop Optimization
      • A.1.2.1 Multithreading with OpenMP*
      • A.1.2.2 Automatic Multithreading
    • A.1.3 Inline Expansion of Library Functions (/Oi, /Oi-)
    • A.1.4 Interprocedural and Profile-Guided Optimizations
      • A.1.4.1 Interprocedural Optimization (IPO)
      • A.1.4.2 Profile-Guided Optimization (PGO)
    • A.1.5 Intel® Cilk Plus
  • A.2 Performance Libraries
    • A.2.1 Intel® Integrated Performance Primitives (Intel® IPP)
    • A.2.2 Intel® Math Kernel Library (Intel® MKL)
    • A.2.3 Intel® Threading Building Blocks (Intel® TBB)
    • A.2.4 Benefits Summary
  • A.3 Performance Profilers
    • A.3.1 Intel® VTune™ Amplifier XE
      • A.3.1.1 Hardware Event-Based Sampling Analysis
      • A.3.1.2 Algorithm Analysis
      • A.3.1.3 Platform Analysis
  • A.4 Thread and Memory Checkers
    • A.4.1 Intel® Inspector
  • A.5 Vectorization Assistant
    • A.5.1 Intel® Advisor
  • A.6 Cluster Tools
    • A.6.1 Intel® Trace Analyzer and Collector
      • A.6.1.1 MPI Performance Snapshot
    • A.6.2 Intel® MPI Library
    • A.6.3 Intel® MPI Benchmarks
  • A.7 Intel® Academic Community
• Appendix B Using Performance Monitoring Events
  • B.1 Top-Down Analysis Method
    • B.1.1 Top-Level
    • B.1.2 Front End Bound
    • B.1.3 Back End Bound
    • B.1.4 Memory Bound
    • B.1.5 Core Bound
    • B.1.6 Bad Speculation
    • B.1.7 Retiring
    • B.1.8 TMAM and Skylake Microarchitecture
      • B.1.8.1 TMAM Examples
  • B.2 Intel® Xeon® processor 5500 Series
  • B.3 Performance Analysis Techniques for Intel® Xeon® Processor 5500 Series
    • B.3.1 Cycle Accounting and Uop Flow Analysis
      • B.3.1.1 Cycle Drill Down and Branch Mispredictions
      • B.3.1.2 Basic Block Drill Down
    • B.3.2 Stall Cycle Decomposition and Core Memory Accesses
      • B.3.2.1 Measuring Costs of Microarchitectural Conditions
    • B.3.3 Core PMU Precise Events
      • B.3.3.1 Precise Memory Access Events
      • B.3.3.2 Load Latency Event
      • B.3.3.3 Precise Execution Events
      • B.3.3.4 Last Branch Record (LBR)
      • B.3.3.5 Measuring Core Memory Access Latency
      • B.3.3.6 Measuring Per-Core Bandwidth
      • B.3.3.7 Miscellaneous L1 and L2 Events for Cache Misses
      • B.3.3.8 TLB Misses
      • B.3.3.9 L1 Data Cache
    • B.3.4 Front End Monitoring Events
      • B.3.4.1 Branch Mispredictions
      • B.3.4.2 Front End Code Generation Metrics
    • B.3.5 Uncore Performance Monitoring Events
      • B.3.5.1 Global Queue Occupancy
      • B.3.5.2 Global Queue Port Events
      • B.3.5.3 Global Queue Snoop Events
      • B.3.5.4 L3 Events
    • B.3.6 Intel QuickPath Interconnect Home Logic (QHL)
    • B.3.7 Measuring Bandwidth From the Uncore
  • B.4 Performance Tuning Techniques for Intel® Microarchitecture Code Name Sandy Bridge
    • B.4.1 Correlating Performance Bottleneck to Source Location
    • B.4.2 Hierarchical Top-Down Performance Characterization Methodology and Locating Performance Bottlenecks
      • B.4.2.1 Back End Bound Characterization
      • B.4.2.2 Core Bound Characterization
      • B.4.2.3 Memory Bound Characterization
    • B.4.3 Back End Stalls
    • B.4.4 Memory Sub-System Stalls
      • B.4.4.1 Accounting for Load Latency
      • B.4.4.2 Cache-line Replacement Analysis
      • B.4.4.3 Lock Contention Analysis
      • B.4.4.4 Other Memory Access Issues
    • B.4.5 Execution Stalls
      • B.4.5.1 Longer Instruction Latencies
      • B.4.5.2 Assists
    • B.4.6 Bad Speculation
      • B.4.6.1 Branch Mispredicts
    • B.4.7 Front End Stalls
      • B.4.7.1 Understanding the Micro-op Delivery Rate
      • B.4.7.2 Understanding the Sources of the Micro-op Queue
      • B.4.7.3 The Decoded ICache
      • B.4.7.4 Issues in the Legacy Decode Pipeline
      • B.4.7.5 Instruction Cache
  • B.5 Using Performance Events of Intel® Core™ Solo and Intel® Core™ Duo processors
    • B.5.1 Understanding the Results in a Performance Counter
    • B.5.2 Ratio Interpretation
    • B.5.3 Notes on Selected Events
  • B.6 Drill-Down Techniques for Performance Analysis
    • B.6.1 Cycle Composition at Issue Port
    • B.6.2 Cycle Composition of OOO Execution
    • B.6.3 Drill-Down on Performance Stalls
  • B.7 Event ratios for Intel Core microarchitecture
    • B.7.1 Clocks Per Instructions Retired Ratio (CPI)
    • B.7.2 Front End Ratios
      • B.7.2.1 Code Locality
      • B.7.2.2 Branching and Front End
      • B.7.2.3 Stack Pointer Tracker
      • B.7.2.4 Macro-fusion
      • B.7.2.5 Length Changing Prefix (LCP) Stalls
      • B.7.2.6 Self Modifying Code Detection
    • B.7.3 Branch Prediction Ratios
      • B.7.3.1 Branch Mispredictions
      • B.7.3.2 Virtual Tables and Indirect Calls
      • B.7.3.3 Mispredicted Returns
    • B.7.4 Execution Ratios
      • B.7.4.1 Resource Stalls
      • B.7.4.2 ROB Read Port Stalls
      • B.7.4.3 Partial Register Stalls
      • B.7.4.4 Partial Flag Stalls
      • B.7.4.5 Bypass Between Execution Domains
      • B.7.4.6 Floating-Point Performance Ratios
    • B.7.5 Memory Sub-System - Access Conflicts Ratios
      • B.7.5.1 Loads Blocked by the L1 Data Cache
      • B.7.5.2 4K Aliasing and Store Forwarding Block Detection
      • B.7.5.3 Load Block by Preceding Stores
      • B.7.5.4 Memory Disambiguation
      • B.7.5.5 Load Operation Address Translation
    • B.7.6 Memory Sub-System - Cache Misses Ratios
      • B.7.6.1 Locating Cache Misses in the Code
      • B.7.6.2 L1 Data Cache Misses
      • B.7.6.3 L2 Cache Misses
    • B.7.7 Memory Sub-system - Prefetching
      • B.7.7.1 L1 Data Prefetching
      • B.7.7.2 L2 Hardware Prefetching
      • B.7.7.3 Software Prefetching
    • B.7.8 Memory Sub-system - TLB Miss Ratios
    • B.7.9 Memory Sub-system - Core Interaction
      • B.7.9.1 Modified Data Sharing
      • B.7.9.2 Fast Synchronization Penalty
      • B.7.9.3 Simultaneous Extensive Stores and Load Misses
    • B.7.10 Memory Sub-system - Bus Characterization
      • B.7.10.1 Bus Utilization
      • B.7.10.2 Modified Cache Lines Eviction
• Appendix C Instruction Latency and Throughput
  • C.1 Overview
  • C.2 Definitions
  • C.3 Latency and Throughput
    • C.3.1 Latency and Throughput with Register Operands
    • C.3.2 Table Footnotes
    • C.3.3 Instructions with Memory Operands
      • C.3.3.1 Software Observable Latency of Memory References