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"CONTROL DATA'
MULTIPLE DISK DRIVE
BM1A6
If
THEORY O'P: 'O·PE'AATION
DIAGRAMS
MAINTENANCE AIDS
WIRE LISTS
CONrRCH DA1A
CUSTOMER ENGINEERING MANUAL
"CONTROL DAT~
MULTIPLE DISK DRIVE
BM1A5
THEORY OF OPERATION
DIAGRAMS
MAINTENANCE AIDS
WIRE LISTS
CONTROL DATA
------
( ,'f·',
) '': ,",
T
u i'j
CUSTOMER ENGINEERING MANUAL
REVISION RECORD
REVISION
01
(9 -27 -69)
A
DESCRIPTION
Preliminary Edition.
Manual released.
112-1-69\
B
(6-15-70)
Engineering Change Order PE21312 incorporating the foUowinll:
ECO PEll081A affecting page 5-21.
FCO PE11100/ECO PEll099 aff~cting pages 5-25, 9-5 thru 9-93.
FCO PE11119A/ECO PE11118A affecting pages 9-5 thru 9-93.
ECO PE11148B affectinjl pages 5-24, 5-25, 9-5 thru 9-93.
FCO PE11204/ECO PEll090 affecting page 4-23.
FCO PE11386/ECO PE11290 affecting pages 5-15, 5-16, 5-20. 5-22
5-23. 5-25.1. 5-25.2. 5-25.3.
PE11386A/ECO PE11290A affecting page 5-15.
PE11417 affecting pages 9-5 thru 9-93.
PE11429/ECO PE21036 affecting pages 5-22. 5-35.
PE11451 affecting pages 9-5 thru 9-93.
PE11451A affecting pages 9-5 thru 9-93.
PE2105&/ECO PE21058 affecting pages 5-21, 5-22, 5-39, 7-30, 7-31, 7-42, .7-42. I, 7-43.
FCO PE21103/ECO PE21103 affecting pages 5-18, 5-19, 5-22, 5-34, 9 -5 thru 9 -93.
ECO PE21122 affecting page 5-27.
FCO PE21143/ECO PE21143 affecting pages 9-5 thru 9-93.
ECO PE5523 affecting pages 5-25.4, 5-25.5.
ECO PE21269 affecting PQJles 9-5 thru 9-93.
Technical Changes affecting page 4-21.
Editorial Changes affecting pages v, vi, vii, viii, 4-30, 5-19.
FCO
ECO
FCO
ECO
ECO
FCO
C
(11-13-70)
Engineering Change Order pE21831 incorporating the following:
ECO PE21143 affecting pages 9-5, 9-20.
ECO PE21253 affecting pages 9-5, 9-21, 9-22, 9-48 thru 9-48. 11.
ECO PE21296 affecting pages vii, 9-48 thru 9-48. 11.
ECO PE21362 affecting pages 9-63, 9-64.
ECO PE21504 affecting pages 5-18, 5-20, 5-22.
ECO PE21514 affecting pages v, 5-24 thru 5-24.2.
ECO PE21537 affecting pages 9 -79 thru 9 -92.
ECO PE21566 affecting pages 5-16, 5-17, 5-18, 5-19, 5 -20, 5 -21.
Publication No.
70602500
ECO PE21572 affectiIlll PQJle 5-39.
ECO PE21594 affecting pages 9-48 thru 9-48. 11.
ECO PE21665 affecting pages 9 -79 thru 9 -92.
ECO PE21667 affectinll pages 9-79 thru 9-92.
Editorial Changes affecting page s 5 -24 thru 5 -26, 9-48.12.
© 1969, 1970, 1971
by Control Data Corporation
Printed in the United States of America
Address comments concerning this
manual to:
Control Data Corporation
Technical Publications Department
4201 North Lexington Avenue
Arden Hills, Minnesota 55112
or use Comment Sheet in the back of
this manual.
REVISION RECORD (CONT'D)
REVISION
D
(2-11-71)
DESCRIPTION
Engineering Change Order PE24038 incorporating the following:
FCO PE21706/ ECO PE21787 affecting page 5 -24.3.
FCO PE21717/ECO PE21717 affecting pages 9-79 thru 9-92.
ECO PE21886 affecting pages 9-63, 9-64.
Technical Changes affecting pages v, 5-24, 5-24.1, 5-24.2, 5-24. 3, 5 -37.
Editorial Changes affecting pages 5 -24.4, 5-24.5.
E
(5-4-71)
Engineering Change Order PE24146 incorporating the following:
Engineering Change Orders
PE21514, PE21933B, PE21997, PE24073, PE24155 affecting pages 5-22, 5-24.1 thru 5-24.10,
9-5, 9-10, 9-24 thru 9-24.23, 9-93 thru 9-121. Editorial Changes affecting pages v, vii, 5 -24. 11/
5 -24. 12, 9 -122.
Publication No.
70602500
PREFACE
All available customer engineering installation,
operation~
and maintenance informa-
tion for the CONTROL DATA® BM1A 5 Multiple Disk Drive is in three manuals.
70602500 A
Publication No. 70602400
General Description, Operation, Installation and Checkout, Maintenance
Publication No. 70602500
Theory of Operation, Diagrams,
Maintenance Aids, Wire List
Publication No. 70601900
Illustrated Parts List
iii
CONTENTS
4.
THEORY OF OPERATION
Functions
4-1
First Seek
4-1
Direct (Forward/Reverse) Seek 4-10
Return to Zero Seek (RT ZS)
4-12
Read/ Write / Erase
4-13
4-14
Assemblies
Power Supply
AC/DC Distribution
4-14
Power -On Sequence
4-16
Power -Off Sequence
4-18
5 -18
Access Control
Head Selection and Fault
Detection
5 -19
Head Gating and Read/ Wri te
5 -21
Chassis Map
Signal Distribution
SiN 574 & Below
SIN 575 thru 1730
SiN 1731 & Above
5-22
5-20
5 -23
5-24
5 -24.1
I
5-24.51
5 -24.5
Logic Chassis
4-20
Power Supply
Mods A05, B05 & Below
Mods A06 & Above
Mods B06 thru B08
Mods B09 & Above
Deck Assembly
4-20
Control Panel
5-24.11
Dri ve Moto r As se mbly
4-21
Spindle Assembly
4-21
Hydraulic Pump
4-23
Schematic Diagrams
Sector Preamp
Cylinder Preamp
5 -26
5 -27
Carriage and Carriage
Mount
4-24
Transducers
4-29
Disk Cleaner Assembly
4-33
Hydraulic Actuator
4-34
Hydraulic Operations
4-36
4-48
Frame
Blower System
Filter Box
Disk Pack
5.
4-14
Difference Counter
4-48
4-48
4-50
DIAGRAMS
Introduction
5 -1
Key to Logic Symbols
5 -13
Input! Output Transmitters and
Receivers
5 -14
Detent Preamp
8AFN Head Select Preamp
8AHN Head Selection
8AJN Upper Difference
Counter
8AKN Address Register
BANN Steering Unit Logic
DAPN Seek Error, On
Cylinder, and XDCR Amps
8AQN / OAQN Solenoid Control
8ARN Receiver
5 -24.2
5 -24.8
5 -28
5 -29
5 -30
5 -31
5 -32
5 -33
5-34
5 -35
5-36
OASN/CASN RTZS and
Fault Detection
5 -37
8A TN Line Transmitter
5-38
BAUN Read Recovery
5-39
8A WN Lower Difference
Counter
5-40
9A YN Write Erase Circuits
5-41
Address Register and Control
Bus Steering
5-15
8AZN Terminator
5-42
Select and Reserve
5 -16
Seek Complete and Index
5 -17
8FAN Analog Gate and
Amplifier
5-43
70602500
E
v
8FBN Select and Reserve
7.
5-44
Low Speed Driver - IDA
7-20
Write Driver - JAB
7-22
AFEN Speed Detector and
Miscellaneous
5-45
Erase Driver - JBB
7 -24
8FFN Tester Card
5-46
Line Transmitter - LAA
7-24
BFGN Fault Status
5-47
Oscillator - MAA
7-27
AF IN Single Sector
5-48
Waveform Generator MBA
7-29
Adjustable Waveform
Generator - MBC
7-30
Quantizing Detector QAA
7-30
Quantizing Detector QBA
7-33
7-33
MAINTENANCE AIDS
General
7-1
SPL Logic
7-1
Physical Description
7-1
Pin Assignment
7-2
Quantizing Detector QCA
Test Points
7-3
Speed Detector - QDA
7-35
Use of Relative Level Indicators
7-3
Or - QEA
7-37
AND Function
7-3
Quantizing Detector QFA
7-39
OR Function
7-4
Information Contained Within
Logic Symbols
Quantizing Detector QFB
7-39
7-4
Discrete Component
Circuits
Quantizing Detector QFF
7-42
7-4
Line Receiver - RAA
7 -42. 1
Intebrid Circuits
7-7
Line Receiver - RBA
7-45
Switch Receiver - RDA
7-45
Switch Receiver - RCA
7-47
Line Receiver - RFA
7-47
Delay - UA-, UBA
7-48
7-9
Delay Circuit - UCA
7-50
Low Level Amplifier - FAB
7-10
Delay Circuit - UCB
7-50
Gated Intermediate Level
Amplifier - GJA
Delay Circuit - UCC
7-50
7-12
Delay Circuit - UCD
7-50
Delay Circuit - UCE
7-50
Delay - UDA
7-52
Delay - UDB
7-52
Wired Functions
7-8
Standard/Non-Standard Logic
Level Indicator
7- 9
Intebrid Circuit Descriptions
7- 9
Discrete Component Circuit
Descriptions
High Level Amplifier - HAA 7 -13
High Level Amplifier - RAB 7-13
vi
High Level Amplifier - HJA
7-13
Lamp Driver - IAA
7 -1 7
Lamp Driver - IBA
7-18
Unidirectional Time
Delay - UEA
7-54
Lamp Driver - ICA
7-18
And - VAA
7-55
70602500 B
~
And - VAB
7-56
And/Or (Single Input) VAC, VJW
7 -56
Power Driver - VJK
7 -59
Power Driver - VJL
7-60
And - VJM
7 -61
Or - VJN
7-62
And - VJP
7 -63
Power Driver - VJR
7-64
Or - VJS
7-65
Or - VJT
7 -65
And - VJU, VJV
7 -66
AndlOr - VJW
7-66
Fli P - Flop - WBB
7 -66
Toggle Flip-Flop - WBC
7-69
Pulse Shaper - XAA
7-70
Pulse Shaper - XAB
7-72
Pulse Shaper - XAC
7-72
Head and Disk Pack Replacement
Criteria
Disk Pack Runout Check
Tester Card
9.
7-75
Head Replacement Criteria
7-75
Disk Pack Replacement
Criteria
7-75
7-76
7-77
WIRE LISTS
Description of Wire Lists
Logic Wire Lists
Non-Logic Lists
Logic Wire List
SIN 2249 & Below
SIN 2250 & Above
Logic Chassis Harness Assy
SiN 574 & Below
SiN 1012 & Below .
SIN 1013 & Above
Deck Assy SIN 132 & Below
'
SiN 133 & Above
2X Final Assy
Control Pane 1
SIN 574 & Below
SIN 575 & Above
Filter Box Assy
Power Supply
Mods A03, B03 & Below
Mods A04, A05, B04, B05
Mods A06 & Above
Mods B06 thru B08
Mods B09 & Above
9-66
9 -79
9-93
9-93
9 -107
Maintenance Panel Assy
9-122
9 -1
9 -1
9-4
9-5
9-24
9 -25
9-36
9-48
9-48.12
9 -53
9-60
9 -62
9-63
9-65
FIGURES
~
Input I Output Signal Gating 2X Cabinet
4-11 Transducer
4-30
4-2
4-12 Detent Detection
4-31
4-2
Select and Reserve Sequence
4-3
4-13 Cylinder Detection
4-31
4-3
Block Diagram - 2X Cabinet
4-9
4-14 Cylinder Position Detection
4-32
4-4
Power Supply - AC I DC
Distribution
4-15
4-15 Indexl Sector Detection
4-33
4-1
4-5
Power Supply - Sequencing
(Upper Deck Only)
4-17
4-6
Deck Assembly
4-22
4-7
Spindle Assembly
4-23
4-8
Carriage I Carriage Mount
4-25
4-9
Head Loading Mechansim
4-27
4-10 Headl Arm Assembly Motion
70602500
t
E
4-29
I
4-16 Hydraulic Actuator - Power
4-35
Off
4-17 Hydraulic Actuator Hydraulic Home
4-38
4-18 Hydraulic Actuator Detent
4-40
4-19 Hydraulic Actuator Forward Fa st
4-41
vii
,.
4-20 Hydraulic Actuator Forward
Intermediat~
4- 43
4-21 Hydraulic Actuator Forward Slow
4- 44
4-22 Hydraulic Actuator Reverse Fast
4- 45
4-23 Hydraulic Actuator Reverse Intermediate
4- 46
4-24 Hydraulic Actuator Reverse Slow
4-25 Blower System
4- 47
4- 49
5-1
Power On/First Seek Sequence
5-2
5-2
Power On/ First Seek Timing
5-3
5-3
Deck or System Power Off
Sequence
5-4
Power Off Timing
5-4
5-5
5-5
5-6
System Power Sequence Lines
5-6
Direct Seek Sequence
5-7
5-8
5-9
Di rect Seek Timing
5-7
5-8
5-9
5-10
5-10
Typical Sector Format
Read/ Write Timing
5-11
7-1
7-2
7-3
Ground Scheme
7-4
Truth Table
7-5
7-6
7-7
Discrete Component Circuit
7-8
Low Level Amplifier - FAB
7-9
Gated Intermediate Level
Amplifier - GJA
7-12
7-10
7-ll
7-12
7-13
High Level Am plifier - HAA
High Level Amplifier - HJA
7-14
7-15
7-16
Lamp Driver - IAA
7-17
viii
Return to Zero Seek Sequence
Return to Zero Seek Timing
SPL Card
AND Function
OR Function
Intebrid Circuit
Wired Functions
High Level Amplifier - HAB
5-11
5-12
7-2
7-14 Lamp Driver - IBA, ICA
7-19
7-15 Low Speed Driver - IDA
7-21
7-16 Write Driver - JAB
7-23
7-17 Erase Driver - JBB
7-25
7-18 Line Transmitter - LAA
7-26
7-19 Oscillator - MAA
7-28
7-20 Waveform Generator - MBA 7-29
7-21 Adjustable Waveform
7-31
Generator - MBC
7-22 Quantizing Detector - QAA,
7-32
QBA
7-23 Quantizing Detector - QCA
7-24 Speed Detector - QDA
7-25 On - QEA
7-34
7-36
7-26 Quantizing Detector - QF A
7-38
7-40
7-27 Quantizing Detector - QFB
7-28 Quantizing Detector - QFF
7-29 Line Receiver - RAA, RBA
7-41
7-43
7-44
7-30 Switch Receiver - RDA,
ReA
7-31 Line Receiver - RFA
7-32 Delay - UA-, UBA
7-33 Delay Circuit - UCA, ueB,
UCC, UCD, UCE
7-46
7-48
7-49
7-51
7-53
7-3
7-4
7-5
7-34 Delay - UDA, UDB
7-35 Unidirectional Time Delay UEA
7-54
7- 6
7-36 And - VAA
7-7
7-8
7-ll
7-37 And - VAB
7-55
7-57
7-38 And/Or (Single Input) 7-58
VAe, VJW
7-39 Power Driver - V JK, VJS
7-40 Power Driver - VJL
7-41 And - VJM
7-42
7-43
7-44
7-45
Or - VJN
7-59
7-60
7-61
7-62
Power Driver - VJR
7-63
7-64
Or - VJT
7-65
And - VJP
70602500 B
7-46 And - VJU, VJV
7-67
7-51 Pulse Shaper - XAC
7-74
7-47 Flip-Flop - WBB
7-68
7-52 Disk Pack Runout Check
7-77
7-48 Toggle Flip- Flop - WBC
7-69
7-53
7-49 Pulse Shaper - XAA
7-71
7-50 Pulse Shaper - XAB
7-73
Logical Presentation of
Tester Card
7-78
TABLES
4-1
Input/Output Lines
70602500 A
4-4
ix
Information for these sections is included in
BMlA5 Multiple Disk Drive
Pub. No. 70602400
SECTION 1
GENERAL DESCRIPTION
SECTION 2
OPERA.TION
SECTION 3
INSTA.LLATION AND CHECKOUT
,/
SECTION 4
THEORY OF OPERA.TION
I
THEORY OF OPERATION
Theory of operation for the MDD is divided into three parts.
The first part considers
the MDD in terms of the functions it performs and the signals exchanged with the controller.
The second part relates the major assemblies of the MDD to the previously
discussed functions.
The last part deals with the disk pack which is physically not a
part of the MDD, but figures functionally in all MDD operations.
FUNCTIONS
Overall capabilities of the MDD are best described by examining the functional blocks
of activity performed by a deck of the MDD.
The functions are as follows:
First Seek
Direct (Forward or Reverse) Seek
Return to Zero Seek (RTZS)
Read/Write / Erase
Each of these functions is further described by flow charts and timing diagrams in
Section 5 of this manual.
The above functions are performed by each deck of the MDD.
Normal operation is
such that a controller will generally be directing the functional activities of more than
one deck.
Figur~
particular deck.
gating.
4-1 shows the method of selecting and gating input/output data to a
Figure 4-2 details the sequence of events that establishes the link and
The signals that are then exchanged are described in Table 4-1 and are shown
relative to a point of origin on Figure 4-3.
FIRST SEEK
This function involves the activities that a deck must perform before it can effectively
respond to a read, a write, or a seek command from the controller.
This function
consists mainly of power supply relay sequencing and status checking by the deck logic.
70602500 A
4-1
As a result, no actual selection of the deck is required and very little MDD / controller
signal exchange occurs.
Successful progression of the function assumes that power
supply circuit breakers for the deck are on, power supply DC / OFF switch for the deck
is set to DC, power supply fuses are operational, related filter box panel UNIT POWER
circuit breaker is on, START indicators for deck are lighted, disk pack is installed on
spindle of deck, and the sector sensor is engaging the disk pack sector disk.
Initiation of the function occurs when the controller makes sequence power available to
the power supply for the deck.
Sequence power causes the power supply relay KDI
(KIDI for lower deck) to energize and the power supply performs a Power-On sequence
(refer to Power Supply under Assemblies in this section for a detailed description).
UPPER DECK
STEERING
LOG IS.
UNIT SEL.
AND LOGIC
J~C.£!>~ ~
CONTROLLER
I
I
I
r---T~
I/O
XMTRS
AND
RCVRS
I
I
I
UPPER DECK
LOGIC NO. COMPARE'
r---
I
--Lr
r-- -
-~
REMAINING
UPPER
DECK
LOGIC
AND SELECT LOGIC
I
----
SIGNAL FLOW OF SELECT
SEQUENCE
I
I
I
L_~
LOWER DECK
LOGIC NO. COMPARE
AND SELECT LOGIC
,
I
I
I
REMAINING
LOWER
DECK
LOG IC
I
LOWER DECK
STEERING
LOGIC
!lcal
Figure 4-1.
4-2
Input / Output Signal Gating - 2X Cabinet
70602500 A
.,.
......
-J
o
O':l
o
I:\:)
CJl
o
o
:J>
t?>
CONTROllER
ISSUES UNIT SELAND LOGIC NO.
CODE FOR DES I RL [)
UN IT OR m:r:K
~Q[S
I
ISSLJEO
LOGIC NO. AGREE
l< TO 1/0
T C>ANS"'1 I TTE RS
5C84
~
I
W
Figure 4-2.
Select and Reserve Sequence
TABLE 4-1.
INPUT /OUTPUT LINES
FUNCTION
SIGNAL
Bidirectional Lines
Information carried by the bidirectional lines
Address and Control
is coupled by five select (tag) signals.
The
influencing tag signal must be known before
information on a bidirectional line can be
interpreted.
The five tag signals are defined
below under Input Lines.
The information
coupled by each tag signal is as follows:
Address/
Control
bus
Bit 0
Read Cylinder Select,
Difference Select, or
Cylinder Select
1
Head
Select
1
Control Select
Write Gate - A "1" input on this line
enables the write drivers.
Bit 1
2
2
Read Gate - A "1" input on this line
enables the digital read data line.
Bit 2
4
4
Seek Forward - A "1" input on this
line initiates forward carriage
movement.
Bit 3
8
8
Bit 4
16
16
Not Used
Erase Gate - A "1" input on this
line initiates reverse carriage
movement.
Bit 5
32
Not
Used
Bit 6
64
Seek Reverse - A "1" input on this
line initiates reverse carriage
rnovement.
Not
Return to Zero - A "1" input on this
Used
line initiates carriage movement to
cylinder 00.
Bit 7
128
Not
Not Used
Used
4-4
70602500 A
TABLE 4-1.
INPUT /OUTPUT LINES (Cont'd)
SIGNAL
FUNCTION
Input Lines
Read Cylinder Select
A "1" input on this line enables the address and
control lines transmitter of the selected deck.
Information transmitted to the control unit
through these lines is the current cylinder
address.
Difference Select
A "1'1 input on this line indicates that the
address and control lines contain the difference
address from the control unit.
This address
is the difference between the control unit's
current cylinder request and the selected deck's
present cylinder location.
Cylinder Select
A "1" input on this line indicates that the addres s
and control lines contain the control unit's
current cylinder request.
Head Select
A "1" input on this line indicates that the
address and control lines contain the head
select information.
Control Select
A 1'1" input on this line indicates that the
address and control lines contain control
information.
::'Unit Select
This signal is preceded by a Logic Number
transmission.
A" 1" input on this line
initiates the select sequence (assuming
the unit is ready) in the unit whose
logic number corresponds to the number
currently on the four Logic Number lines.
If the unit is ready, it returns a Unit Ready
and a Unit Selected signal.
If not ready ~
the unit returns a "0" on the Unit Ready
line.
70602500 A
.
4-5
TABLE 4-1.
INPUT/OUTPUT LINES (Cont'd)
~GNAL
~:~Logic
Number lines (4)
FUNCTION
A transmission on these lines is accompanied
by a Unit Select signal.
The unit with the
logic number corresponding to the digital
number transmitted on these four lines
initiates a select sequence (assuming
the unit is ready and available) when a Unit
Select signal is transmitted.
If the unit is
ready and available, it returns a Unit
Ready and a Unit Selected signal.
If not
ready and/or available, the unit returns a
"0" on the Unit Ready line.
This line enables an unrestricted reset of the
unit select condition.
Release
A "1" input on this line clears the Reserve and
Compare Enable flip-flops in the selected unit.
Write Data
Carries information to be written from the
control unit to the selected deck.
Output Lines
Read Data
Carries digital information read from a disk
to the control unit.
On Cylinder
Indicates that the positioning mechanism of the
selected deck has stopped and the read/write
heads have reached the addressed cylinder.
Seek Error
A "1" output indicates that the selected deck
was unable to complete a seek operation to
the point of an On Cylinder signal to the control
unit.
A Return to Zero command sent to the
unit indicating a seek error clears the Seek
Error condition, returns the heads to cylinder
00, and enables an On Cylinder signal to be
sent to the control unit.
4-6
70602500 A
I
I
TABLE 4-1.
INPUT /OUTPUT LINES (Cont'd)
SIGNAL
Unit Selected
FUNCTION
This signal is a response to the receipt of
a Unit Select and a Logic Number signal
combination.
A "1" output indicates that
the unit is available.
A "0" signal
indicates that the unit is not ready (see
Unit Ready signal).
The control unit
checks that a Unit Selected signal is not
recei ved from more than one unit at a
time.
Index
Provides a track reference mark from the
selected deck to the control unit.
This mark
occurs once for each revolution of the disk pack.
Pack Unsafe
A "1" output indicates that the selected deck has
one or more fault conditions.
Write and erase
currents are inhibited by the presence of any of
the conditions.
The conditions include:
1.
More than one head selected.
2.
Read and write gates up at the same
time.
3.
Read and erase gates up at the same
time.
4.
Erase and no write driver on.
5.
Erase and both write drivers on.
6.
One or both write drivers on and no
erase driver on.
70602500 A
7.
Read, write, or erase gate on and not
On Cylinder.
8.
Low voltage situation that could cause
a loss in control of write and erase
currents.
4-7
TABLE 4-1.
INPUT/OUTPUT LINES (Cont'd)
SIGNAL
FUNCTION
This signal is a response to the receipt of
a Unit Select and a Logic Number signal
combination.
A" 1" output is present if
both of the following conditions are
satisfied:
~:~Seek
Complete or Seek
Error
1.
Disk pack instal1ed, spindle
motor up to speed, and heads
loaded.
2.
Related Logic Chassis Maintenance
panel ON LINE/OFF LINE switch
set to ON LINE.
Indicates that the unit has completed (Seek
Complete) or is unable to complete (Seek
Error) the previously addressed seek.
This
is an interrupt line transmitted with or
without the unit being selected.
The signal
is a 1 J..l sec" 1" pulse which is initiated by
an On Cylinder condition (Seek Complete) or
or if the unit is unable to complete a
seek (Seek Error).
':~This
4-8
signal is not gated by the Unit Selected signal.
706025'00 A
'/0
CABLf
A O~
CAlLES
B
• O. 8
--------,,(r---~
- --+--i)----
..---
CYuNDER PuLSES
LINE 0
LINE 0
LINE .,
LINE 0
14 LlPljES
LINE 3
UNIT SELECT
RELEASE
j
'~:-o-------
NOTE
I
--
B
LOWEF; REFERS TO SPINDLE OR DECK
A I X CABlfIIET DOES NOr uSE A ~Ow(R
DE(:t(
Figure 4-3.
70602500 A
Block Diagram - 2X Cabinet
4-9
Power is applied to the brush and spindle drive motors during the Power-On sequence.
Application of power to the brush motor starts a 60-second (approximately) disk cleaning cycle.
When the disk pack speed reaches 2000 rpm, the power supply relay K05
(KI05 for lower deck) energizes to provide sequence power to the next deck.
Actuator
solenoid power also becomes available, causing the detent pawl to disengage and the
actuator to access forward at 2 ips to the hydraulic home position.
Transfer of the brush switch contacts at the end of the brush cycle sets the Forward
Latch (FF).
This causes the actuator to perform a forward fast access that mechani-
cally loads and latches the read/write heads.
The transferring contacts of the heads
loaded switch sets the RTZS FF which clears the Forward Latch.
The actuator re-
sponds by performing a reverse fast access to the hydraulic home position.
A 300-ms
delay (started when the RTZS FF was set) circuit clears the RTZS FF which in turn
sets the Forward Latch, Intermediate, and Slow FF's.
This causes the actuator to
access forward at 2 ips until the logic senses the leading edge of the first track
(track 00) pulse.
The track pulse sets the Detent FF and releases the detent pawl.
The output of the detent transducer is now observed and 5 ms after the pawl engages
the detent gear, the deck sends an On Cylinder signal to the controller.
(A seek Error
signal would have been sent instead if a 600-ms delay, starting when the heads loaded
switch transferred, had timed out.) The deck is now ready to perform a Read, a
Write, or a seek (Direct or RTZS) operation.
Such an operation must be preceded by
the selecting sequence covered previously (Figures 4-1 and 4-2).
DIRECT (FORWARD/REVERSE) SEEK
The Direct Seek function involves those operations that must be performed to move the
read/write heads from their current track or cylinder location to the one specified by
the controller.
This function must be preceded by the selecting sequence (Figure 4-1
and 4-2) unless the deck is already selected.
Assume that the desired deck just com-
pleted a First Seek and is awaiting further instruction at track 00.
Assume further
that the controller wishes to do a Read or a Write operation at track 88.
When the
controller determines that the deck is selected and ready, it issues a Cylinder Select
signal.
This signal gates the content of the deck Cylinder Address register (00) to the
controller via the bidirectional lines (content of the register always preset to 00 during
4-10
70602500 A
a First Seek or RTZS).
The controller then calculates the difference between the decks
current and desired location and sends a Difference select that gates the seek length
(88 tracks) into the decrement counter of the deck (again via the bidirectional lines).
The controller now uses a Cylinder Select and the bidirectional lines to gate the address
of the desired cylinder (88) into the deck Cylinder Address register.
This is followed
by a Sector Select that enters the sector address into the deck Sector Address register.
Next the controller sends a Head Select signal that gates the number corresponding to
the desired read/ write head into the Head register.
The last address and control
exchange involves the Control Select signal that gates a "1" to the deck on bit 2 (Seek
Forward) of the bidirectional lines.
The Seek Forward pulse causes an Any Seek pulse.
(A Seek Reverse pulse would also
cause the Any Seek, but in addition would have cleared the Forward Latch.) Any Seek
transfers the content of rank I of the decrement counter (88) to rank II and clears the
Detent FF.
The hydraulic actuator responds by applying pressure to the detent pawl.
As soon as the detent pawl clears the detent gear, forward motion begins.
track is crossed, the cylinder transducer generates a track pulse.
As each
The trailing edge
of each of these pulses decreases the content of the decrement counter by one.
Motion
velocity is controlled according to the content of the decrement counter, and since this
content is in excess of 26, the actuator performs a forward fast access.
Fast access
(26 ips) continues until the decrement counter content equals 25 tracks remaining.
At
this time the counter output decoding logic sets the Intermediate FF, and the hydraulic
actuator continues the access in the forward intermediate mode (7 ips).
When the
decrement counter content indicates three tracks to go, the Slow FF sets.
This causes
the actuator to reduce speed to 2 ips and continue the access at a forward slow rate.
When the tracks remaining have been reduced to one, the output of the cylinder transducer detection logic is gated such that the leading edge of the next track pulse sets the
Detent FF.
This causes the hydraulic actuator to release the spring-loaded pawl.
(If
this were a Reverse Seek, the Forward Latch would set as a result of the Detent FF
setting.
Setting the Forward Latch would cause carriage motion to change direction
and allow the detent pawl to engage the gear in the same manner as for a Forward Seek. )
Five
ms after the detent transducer indicates that the detent pawl has engaged the
detent gear, the deck sends an On Cylinder signal to the controller.
(If the period
during which the pawl was disengaged from the detent gear had exceeded 600 ms, a
70602500 A
4-ll
Seek Error signal would have replaced the On Cylinder signal.) The deck is now ready
to perform a Read, a Write, or a Seek (Direct or RTZS) operation.
RETURN TO ZERO SEEK (RTZS)
The RTZS functions allow a controller to return the read/write heads to track 00 when
a Seek Error signal occurs.
This function must be preceded by the selecting sequence
(Figures 4-1 and 4-2) unless the deck is already selected.
The controller responds to
a Seek Error signal from a deck by sending a Control Select tag that gates a "1" on
bit 6 (RT ZS pulse) of the bidirectional lines to the afflicted deck.
The RTZS pulse sets the RTZS FF and causes an Any Seek pulse.
The Any Seek pulse
clears the Detent FF causing the hydraulic actuator to apply hydraulic pressure to the
detent actuator.
The pressure overrides the force of the pawl spring and the carriage
is free to be moved.
The set output of the RTZS FF causes the following events:
Clears decrement counter
Clears Cylinder Address register
Clears Forward Latch
Initiates a 300-ms delay circuit
Establishes a tracks-to-go greater than 26 signal (T>26)
With the Forward Latch cleared and a T> 26 situation, the actuator enters into a fast
reverse access toward the rear stop (cushioned hydraulically).
times out, the RTZS FF clears and the T> 26 signal drops.
When the 300-ms delay
The clear output of the
RTZS FF sets the Forward Latch, Intermediate, and Slow FF's.
The hydraulic
actuator responds to this activity with a slow forward (2 ips) access.
As soon as the
leading edge of the first track pulse occurs, the Detent FF sets and the actuator removes pressure to the spring-loaded detent pawl.
Five ms after the detent transducer
indicates that the detent pawl has engaged the detent gear, the deck sends an On
Cylinder signal to the controller.
(If the period during which the pawl was disengaged
from the detent gear had exceeded 600 ms, a Seek Error signal would have replaced
the On Cylinder signal.) The deck is now ready to perform a Read, a Write, or a Seek
(Direct or RTZS) operation.
4-12
70602500 A
READ/WRITE/ERASE
An On Cylinder signal indicates to the controller that the selected MDD deck has completed a seek operation and is awaiting further instruction.
If, however, the controller
initiated a seek operation in one deck and then in the interim selected another deck, the
first deck would make its status known via the On Sector interrupt signal.
In the latter
case, the controller would be required to precede a Read or a Write operation with the
selecting sequence (Figures 4-1 and 4-2).
The following paragraphs cover the sequence
of events involved in a Read or a Write operation.
A Write operation actually begins before the hydraulic actuator positions the heads to
the desired track: the Head Select tag gates the identifying number of the head to be
used into the Head Address register.
When the seek is completed or a seek error is
discovered, the deck sends a Seek Complete or Seek Error interrupt signal.
IT the
controller has selected another deck in the mean time, this deck will standby until it
is res elected by the controller.
Error and On Cylinder lines.
In any case the controller will examine the Seek
If
If a Seek Error exists, a RTZS pulse will clear it.
an On Cylinder exists, the controller responds with a Control Select tag that gates
the Read Gate signal (bit 1 of the bidirectional lines) to the deck.
Read Gate enables
the read circuit logic to function with the previously selected head.
As each record
of data on the disk pack is reached, the address is read from the Read Data line and
compared by the controller with the address of the desired record.
(Refer to Section
5 of this manual for detailed information relative to the read/write format.) When
the controller is satisfied that the desired record is being read, it drops the Read
Gate and gates in the Write Gate and Erase Gate (bits 0 and 4 of the bidirectional lines)
with the Control Select tag. This disables the read circuit and enables the write
circuit, and nata from the controller is written via the Write Data line onto the
disk pack record.
The Erase Gate signal enables erase current to the erase coil
during the Write operation to ensure a clear writing surface.
A Read operation is performed in much the same manner as the Write operation.
The
difference is that the Write Gate and Erase Gate signals are never enabled (Read Gate
stays on throughout the entire record).
70602500 A
4-13
ASSEMBLIES
POWER SUPPLY
Each MDD cabinet has a self-contained power supply accessible via the rear door and
located behind the swingout logic chassis.
The power supply provides a fixed output
voltage of +40Y volts for use by the solenoids on the deck assemblies.
It also provides
adjustable output voltages of +40 vdc (to read/write logic), :t:20 vdc (to logic), and +6
vdc (to logic).
Each voltage is duplicated within the power supply, so that the voltage
can be distributed separately to the upper deck and the lower deck or to row A and
row B of the logic chassis.
Basic onloff power control and monitoring is provided at the front panel of the assembly.
The front panel is hinged so that access can be gained to adjust or perform maintenance.
The assembly is cooled by fans located on the top surface of the chassis.
AD / DC Distribution (Figure 4-4)
Input power is applied through the closed contacts of the MAIN POWER circuit breaker
(on filter box panel) to the primary of transformer TOL
The presence of the primary
input power at the power supply is indicated by the power supply MAIN BREAKER
indicator.
The input power is applied directly to the cooling fans in the power supply and the logic
chassis.
Input power will also be applied to the blower in the lower part of the cabinet,
but only when the power supply BLOWER circuit breaker is set to ON.
All other dis-
tribution of ac power is delayed until during the power-on sequence (described in a later
paragraph).
4-14
70602500 A
...
........,..
.........
K04
-J
r--
o
OJ
r----1
'I'-~
~---r
.
o
I.\:)
c.n
r---t-
o
o
:P
-~
0A
"B
ec
NEU T
==
~~
+
I---
~
1(0,1~
DC
+ 20Y ---1
DCIOFF<>-
0e }
08
J
TO 8LOWER
r--'
.r--
I
t"--J
SSW03
:
t=r
SSW02
~'I'
I
.A
SSW'04]
). , ~:r "."l
~~~9 ~
""r '~.~
I
,,-..... +---0A
r~
W
~
'i'
MAIN
BREAKER
~
:
TO UPPER DECK BRUSH MOTOR
'C }
TO UPPER DECK
IB
DRIVE MOTOR
.A
"A
TO LOGIC CHASSIS FANS
,A }
0B
TO LOWER DECK
DRIVE MOTOR
KIOI
DC/OFF DC
+20Y---1~C>
L-------------------r-"
L--
~
~ 0C
]SSWI04
KI0)~4~________________________________~____~
HOY
---l I-
flA
TO lOWER DECK BRUSH MOTOR
K05
L __________________-. BUCKING
XfMR AND
FULL WAVE
:~~~~:IER
L-...._ _ _-----jBUCKING
I
-
C - TYPE
FILTER
LC- TYPE
XFMR AND
FULL WAVE
"-""'---1f-K 105
1~
~"----1
f-K02
r="---1 ~
KI02
.r-- -----i
f--
F I L TE R
+40V TO UPPER DECK RIW LOGIC
+40V TO LOWER DECK R Iw LOGIC
+6V
TO ROw A LOGIC
+6V
TO ROw 8 LOGIC
RECTIFIER
L$ f$ Y~"T··I ~
~
l..---
-
+20Y TO OP PNlS AND PACK ON
AND SECTOR SWS
_ _ _ _ _ _ _ _.
~ ,,~.'"
TOI
C""'''".
co-n"
XFMR AND
FU1.L WAVE
FI L TER
~~
RECTIFIER
L-....- BOOST I NG
;~~tw~:~
L----------~--------__,RECTI F IER
LC _ TYPE
,,-.....
FI L TER
,~,:
K02
BEc
+20T TO lOGIC XMTRS/RCVRS
+20V TO ROw A lOGIC
+20V TO ROw 8 LOGIC
-20T TO LOGIC XMTRS/RCVRS
-20V TO ROW A LOGIC
KIC
-20V TO ROW 8 LOG I C
' - - - - - - - - , FULL WAVE
BRIDGE
~_ _ _ _ _.,RECTIFIER
L _________________j
§
C - TYPE
FILTER
1
'"V
I
KC
1<:<
r---
+40Y TO UPPER D£IOK SOLENOIDS
f--
+40Y TO lOWER DECK SOLENOIDS
~
~
I
I-'
c.n
Figure 4-4.
Power Supply - AC / DC Distribution
-
The dc power distribution begins with the application of main input power to the primary
of TO 1.
Voltages developed across the secondary windings are applied to five rectifier /
filter circuits.
Each of these circuits develops a separate dc voltage.
Through the use
of variable transformers, four of the five voltages are adjustable (+40Y solenoid power
is not adjustable).
The +20Y voltage is immediately available when TOl is energized.
This voltage is distributed to the operator panels and the pack on and sector in-place
switches.
The voltage is required to determine the status of these elements during a
power on sequence.
Distribution of the other dc voltages is controlled by circuit
breakers and/ or relay contacts.
Power-On Sequence
Power application to a deck is sequenced up by relays in the power supply (Figure 4-5).
Sequencing is required to prevent damage to read/write heads and/ or disk packs.
A normal on line, power-on sequence begins when switch S501 on the operator panel is
pressed (actuating power supply panel START switch will also start the sequence).
The
.. progression of the sequence assumes that all power supply circuit breakers are on,
that all power supply fuses are operational, that the power supply DC / OFF switch is
set to DC, that a disk pack is installed, that the deck drawer is closed, and that
sequence voltage to relay KOl is available.
NOTE
Although steps 1 through 3 occur prior to actuating
S501, they should be considered a part of the power
on sequence.
1.
When filter box MAIN POWER circuit breaker was set to ON, +20Y voltage
became available (Figure 4-4).
2.
When controller issued sequence voltage, KO 1 energized via pick line
(Figure 4-5).
The +20Y voltage was applied to solid-state switches SSWOl,
SSW02, and SSW03 (Figure 4-4).
This enabled the solid-state switches to
conduct their respective phase of ac power.
The upper deck drive motor and
time meter started.
4-16
70602500 A
y
"""
- .......
~
-J
o
Q')
PICK
o
FROM
CONTROLLER
OR PRECEDING
UNIT
~
CJ1
o
o
!l>
{
=-I~KOI ~
K02
BLOWER
f'j"'\
\.:..J
+20
-20
+ 6
OFF
~~~~~-l
f'j"'\
Ij\
Ij\
0C
\.:..J
+ 20Y
~
1
~
START
I
go
PACK ON
S50 I
0
~
IN STALLED
~
SECTOR
I
-
K05
L"!"T
r------------,
I
T
KOI-
1
1
1
I 0 FF
IN PLACE I
K04
_1~~I.i-9I
INSTAL LED
0
I r---o--- O~--e.--------i t
o
®
IN PLACE I KOt
L _ _ _ _ _ _ _ _ _ _ _ -1
I
SPEED
SPINDLE SPEED
STATUS FROM
LOGIC CHASSI S
(GRD = SPEED)
+20Y TO SSWOI THRU SSW03
(DR IVE MOTOR)
DRIVE MOTOR
NOTES:
.
DECK ASSEMBLY
\
The deck assemblies (Figure 4-6) are responsible for the dynamic operations of an
MDD: driving the disk packs, and loading and positioning the read/write heads.
The
deck assembly consists of a deck plate on which are mounted a drive motor assembly,
a spindle assembly, a hydraulic pump, a carriage and carriage mount, three transducers, a disk cleaner assembly, and a hydraulic actuator.
4-20
70602500 A
The deck assembly mounts in the MDD cabinet on a drawer mechanism.
The drawer
may be extended out the front of the cabinet to load a disk pack, or extended out the
rear of the cabinet for maintenance purpose s.
Drive Motor Assembly
The drive motor drives the spindle assembly and the hydraulic pump. The motor is
an induction type, 3/4-hp unit.
The motor is secured to a mounting plate which bolts
to the underside of the deck plate.
Power is transferred via a flat, smooth-surfaced
belt that threads over the pulleys of the spindle, hydraulic pump, and drive motor.
A spring-loaded idler pulley maintains a constant tension on the belt.
The temperature of the motor is monitored by a thermal protection switch.
To restore
operation after an over-temperature condition, the red, 1/4-inch button on the top end
of the motor must be manually reset (pressed).
Spindle Assembly
The spindle assembly is the physical interface between and MDD deck and a disk pack.
The conical surface of the spindle cone (Figure 4-7) mates directly with the coneshaped opening in the center of the disk pack.
Starting in the spindle cone and running through the center of the spindle assembly is
the vertically free -floating lockshaft.
The upper end of the lockshaft contains internal
threads that engage the external threads of a stud projecting from the disk pack.
When
the disk pack cannister cover handle is rotated clockwise, the spring -loaded lockshaft
is pulled upward and the disk pack is pulled down.
As a result, the conical surfaces
of the disk pack and the spindle cone are engaged by a force of approximately 200
pounds. A clutch mechanism protects the lockshaft from damage that could occur from
over tightening the disk pack. When the disk pack is fully engaged, a released mechanism in the canister handle frees the canister from the disk pack.
A notched lock wheel secures to the bottom surface of the drive pulley.
The notches
of the wheel are engaged by the tip of the spindle lock pawl (Figure 4-6) when the deck
drawer is open. This locks the spindle, making it easier to install or remove a disk
pack. Opening the drawer of an operating deck will cause a loud ratcheting noise
(such action, while not recommended, will not cause damage).
The spindle lock
mechanism can be overridden if deck operation is required with the drawer open
70602500
B
4-21
I
DISK PACK
CANNISTER \
MOTOR
/
. TRACK (CYL) NO.
x\
C=~~~\CATOR\
INDEX (SECTOR)
8
DRIVE
MOTOR
~
/i
/
INDEX
SLOTS
CY"!oTATION
SPINDLE
I
J,
DRIVE
MOTOR
PULLEY
IDLER
PULLEY
PUMP
DRIVE
PULLEY
Figure 4-6.
5cao
Deck Assembly
4-22
70602500 A
(refer to Figure 2-2>.
Closing the drawer will cancel the override.
The spindle drive
pulley is driven by a flat belt linking it to the drive motor pulley.
The Pack-On switch and ground spring are mounted at the lower end of the spindle
assembly.
The ground spring block is mounted
the ground sleeve.
that it is always in contact with
The Pack-On switch contacts transfer in response to the vertical
movement of the lockshaft.
are closed.
SQ
When the shaft is up (disk pack mounted), the contacts
When a pack is not installed, the shaft moves downward to deflect the
switch actuator and transfer the contacts.
/
I
l
DETAIL
\
DETAIL
~~EL
PI"
LOCKSHAFT
(FREE TO MOVE VERTICALLY)
SPINDLE LOCK FRICTION PLATE
~--SPRING
RETAININ(3
.....- /
RING
/
FRICTION
PLATE HUB/
GROUND/
SLEEVE
~
~
WAVE WASHER
' " GkOUND SPRING
BLOCK
PACK ON
SWI TCH
SWITCH
ACTUATOR
Figure 4-7.
5C99A
Spindle Assembly
Hydraulic Pump
The hydraulic pump is a positive-displacement type device capable of delivering 0.67
gpm at a nominal pressure of 200 psi.
70602500 B
4-23
The pump is located on the top of and at the rear of the deck assembly.
The pump is
seated on the pump drive assembly which functions to extend and couple the pump
shaft through the deck to the pump drive pulley.
A flat belt driven by the drive motor
turns the pump.
The input and output hydraulic connections at the pump both originate at the hydraulic
actuator.
The hydraulic fluid pump and all pressure control valves are located in the
hydraulic actuator.
A pressure sensing switch is installed on the pump output line.
The switch transfers
at a nominal output of 10 psi (approximately 50 rpm) and is used in conjunction with
an operator panel indicator (see Section 2).
Carriage and Carriage Mount
The carriage and carriage mount (Figure 4-8) combine to form the vehicle that supports
the read/write heads.
Movement of the carriage, within the carriage mount, is con-
trolled by the hydraulic actuator.
The carriage consists of an upper rail and a lower rail, separated by the receiver and
the coupler plate.
The rails contain bearing surfaces that interface with the various
bearings and rollers of the carriage mount.
Each rail has a rack gear that meshes
with a pinion gear on the detent gear shaft (mounted vertically in carriage mount).
The detent gear and the track position disk are mounted on the lower end of this same
shaft.
The ball tip of the hydraulic actuator drive rod is connected to the carriage by
the drive rod coupler.
When the hydraulic actuator extends or retracts the carriage,
the detent gear shaft (and detent gear and track position disk) rotates.
The cylinder transducer senses the passing of the slots and lands of the rotating
track position disk.
From the center of one slot to the center of an adjacent land is
recognized as a movement of one track.
The transducer output causes the difference
(decrement) counter content to decrease by one each time a track is crossed.
When
the logic determines that the next track to be crossed is the addressed track, it signals the detent solenoid to release the detent pawl.
The spring-loaded pawl is drawn
into the teeth of the detent gear and locks the carriage at the desired track.
The
detent transducer senses the pawl and gear engagement and signals the logic.
4-24
70602500 A
A track indicator (top of detent gear shaft) provides a visual indication of the current
track location of the read/write heads.
A head loading mechanism mounts between the receiver and the coupler plate.
Oper-
ation of this mechanism and the heads loaded switches is covered in the following
paragraph.
Figure 4-8.
Carriage/Carriage Mount
Head Loading
The read/write heads must be loaded to the disk surfaces before exchanging data with
the controller.
The heads must be released from this position (unloaded) and driven
clear of the disk pack when power is removed to the deck or the disk pack velocity
falls below a predetermined rpm.
The carriage components involved in these opera-
tions are identified in Figure 4 - 9.
70602500 A
4-25
Head loading amounts to applying spring pressure to the back of the read/write head
so the aerodynamically shaped head face approaches the related disk surface.
When
the cushion of air that exists on the surface of the spinning disk is encountered, it
resists the further approach by the head.
Spring pressure is designed to just equal
the opposing cushion pressure (function of disk pack rpm) at the required height.
a result, the head flies.
As
However, if the spring pressure exceeds the cushion pressure
(as would happen if the disk pack lost enough speed), the head will stop flying and
contact the disk surface.
This could cause damage to the head as well as the disk
surface.
To prevent damage to the heads and/ or the disk pack during automatic operation,
loading occurs only after the disk pack is up to speed and the heads are over the disk
surfaces.
For the same reason, the heads unload automatically and are retracted if
the disk pack rpm drops out of tolerance.
During manual operations, heads should
never be loaded on a disk pack that is not rotating, nor should heads be loaded without
a disk pack being installed on the spindle.
(The Maintenance section for this equip-
ment provides instructions on how to disable the head loading mechanism.) Head
loading is a part of the First Seek function.
the drive motor starts.
As power to the deck is sequenced up,
This causes disk pack rotation, hydraulic pump operation,
and a brush cycle (approximately 60 seconds).
When the disk pack rpm reaches 2000,
the extend solenoid (and head latch magnet) energizes and the carriage moves from the
retracted position to the hydraulic home position.
Upon completion of the brush cycle
(brushes clear of disk pack), the hydraulic actuator forward solenoid energiz es and the
carriage moves forward toward the spindle and the forward mechanical stop.
loading occurs
~uring
Head
this forward motion.
The cam follower (part of carriage) moves along the head loading cam (part of carriage
mount).
When the follower encounters the up-ramp of the cam, the linkage rod assem-
bly moves upward (Figure 4- 9, part C).
This causes each of the ten torsion rods to
rotate which forces the 20 read/write heads toward the proper disk surface.
The
spring force of the torsion rod is opposed by the air layer on the disk surface and an
equilibrium is attained with the heads flying over the disks.
As the carriage nears the spindle, the head load pawl enters the notch in the linkage
and transfers the heads extended switch.
The head latch magnet holds the pawl in the
latched position until power (to magnet) is removed.
Forward carriage motion contin-
ues until the cam follower contacts the head load cam latch.
4-26
This contact frees the
70602500 A
A
B
MECHANISM
HEADS UNLOADED
SPRING---
o LOAD _____
~
HEA LATCH,
~
CAM
,,/"
./
/"
HEAD
LOADING
CAM
/'
TORSION
ROD
C
HEAD
5C83
Figure 4-9.
70602500 A
.
Mechanism
Rea d LoadIng
4-27
end of the cam and it rotates downward to transfer the heads loaded switches.
This
transfer signals the logic that loading is complete and causes the carriage to be
retracted and positioned to track 00.
The heads remain loaded and latched until power
is removed, the index (sector) transducer is displaced from sector disk of disk pack,
or disk pack rpm drops below tolerance.
Head unloading (Figure 4-9, part D), occurs when solenoid power is removed to the
head latch magnet.
The head load pawl pulls out of the linkage notch, the torsion
rods rotate to relieve the pressure to the back of the read/write heads, and the heads
unload or move away from their respective disk surfaces.
With solenoid power absent,
the reverse biased (hydraulically) actuator moves the carriage toward the retracted
mechanical stop.
As the carriage moves in reverse, the linkage rod assembly press-
ing down on the cam follower pivots the head loading cam s·o that the tip (of cam)
engages the head load cam latch.
This relatching occurs as the carriage moves from
hydraulic home to the retracted stop.
If the linkage malfunctions and fails to unload the heads, the upper roller assembly
(Figure 4-8) contacts the knock off pin (Figure 4-9, part D).
This contact forces the
knnck off pin downward to forcibly rotate the head load pawl clear of the head latch
magnet pole face, the thereby unload the heads.
The knock off pin is contacted by
the roller somewhere between tracks -7 and -12.
Head/Arm Assemblies
Twenty head/arm assemblies are mounted on the carriage of each deck.
A head/arm
assembly consists of a read/write and erase coil package (head assembly) mounted
at the end of a supporting arm structure.
The head assembly (Figure 4-10), which includes a cable and plug, is mounted on a
gimbal ring which in turn is mounted on a floating arm.
This method of mounting
allows the head assembly to move (independent of the arm) tangentially and radially
relative to a data track on the disk surface.
Such motion is required to compensate for
irregularities in the disk surface.
The arm structure consists of a floating arm secured to a heavier fixed arm.
of the fixed arm opposite the head installs in the carriage receiver.
The end
The floating arm
is the mounting point for the head and is necessarily flexible so that it can respond to
4-28
70602500 A
the force applied (on load button) by the torsion rod/spring during head loading.
Each
tip of the Y - shaped torsion spring loads a head, moving one head up and one head down.
The freedom and mobility of the head are necessary elements to being able to function
with interchangeable disk packs.
During head loading the 10 torsion rods rotate in
unison to flex the 20 heads toward the air cushion of the spinning disk surfaces.
The
force applied by the torsion spring causes the heads to fly or float on the air cushion.
Vertical motion by a disk surface (due to warpage or imperfection) is countered by a
move in the opposite direction by the gimballed head and/or the floating arm.
As a
result, flight height remains nearly constant.
TORSION ROD
THIS FORCE
APPLI ED WHEN TORSION
ROD ROTATES DURING
H~ LOADING OPERATIONS
F~nNG~
ARM
/J)/
....
GIMBAL
LOAD5""'''''
BUTTON
Gltl.BAL SPRING
ALLOWS HEAD ASSY
. / MOTION ABOUT
./
THIS AXIS.
,.
...............A
"-
DISK
ROTATION
~,
\
.......
GIMBAL SPRING
ALLOWS HEAD ASSY
MOTION ABOUT
THIS AXIS.
, ....
~
Figure 4-10.
se1l3
Head/ Arm Assembly Motion
Transducers
Three transducers are used on each MDD deck: detent transducer, cylinder transducer, and index (sector) transducer.
70602500 A
A transducer is a potted assembly consisting
4-29
of a primary coil and two secondary coils (Figure 4-11).
The secondary and primary
coils are separated by a notched and movable metal plate.
ducer is excited by a 187-kHz oscillator.
The primary of the trans-
When a notch (air gap) is between the
secondary and primary windings, the output of the transducer secondary is maximum.
The secondary output is minimum when the metal plate is between the windings.
The
secondary outputs drive a preamplifier card.
The related preamplifier card plugs into the transducer.
processed in the logic chassis.
The preamplifier output is
The only adjustment required of this assembly amounts
to repositioning the transducer relative to the slotted metal plate ..
Detent Transducer
The detent transducer senses the location of the slot in the detent flag.
When the
detent pawl engages the gear, the slot is nearer to the bottom secondary coil (Figure
4-12).
This causes the amplifier output to go negative.
filtering removes part of the 187-kHz signal.
The preamplifier card
The detection circuit converts the
negative signal to a "0".
If the detent pawl is disengaged from the gear, the flag slot moves nearer to the upper
coil.
This causes a positive amplifier output which is detected as a "1".
rv
5'>Jb-----'~
F'
\
AIR GAP]
OSCILLATOR
(187 KHZ, 11.8V P-P)
.~I~ '''--METALPLATE
SBDONDA~:~DARY
" - - - SHIELD (COPPER)
5C.4A
Figure 4-11.
4-30
Transducer
70602500 B
TRANSDUCER
PREAMPLIFIER CARD
AMPL
FILTER
LOGIC CHASSIS
DETEC-
TOR
-v
!5ce!S
Figure 4 -12.
Cylinder
DETENT
SIGNAL
Detent Detection
Tran~rl'](~er
The cylinder transducer senses slots in the edge of the rotating track position disk.
The cylinder detection circuit (Figure 4-13) converts the analog output of the transducer to "1' s" and "0' s".
The slotted edge of the track position disk separates the primary of the transducer
from the secondaries.
As the disk rotates, the notches allow varying levels of
coupling between the primary and the secondaries.
Figure 4-14 shows rotational
positions of the track position disk and the resulting cylinder detection.
As the notch
passes over secondary A, maximum coupling of the primary is possible and the output
of secondary A is maximum.
Since secondary B is covered by a land, coupling to the
primary is .minimum as is the output.
TRANSDUCER
PREAMPLIFIER CARD
LOGIC CHASSIS
SEC
A
PRIMA:~
AMPL
FILTER ......-"""4
DETECTOR
CYLINDER
PULSES
!Sce.
Figure 4-13.
70602500 A
Cylinder Detection
4-31
TRACK POSITION
DISK
o
0
~ \[Cjl?
[
X:UC:R
};
SECS
A
A
A
B
B
B
. . . DISK MOTION
LAND
NOTCH
TRANSDUCER
OUTPUT
-In...._____..Jn...._____......fL
DETECTOR OUTPUT _ _ _
5C97
Figure 4-14.
Cylinder Position Detection
As the disk rotates, both secondaries become covered by a land.
Since the outputs
are equal, the transducer output is a null.
Further rotation of the disk uncovers secondary B allowing maximum coupling and
raising output B to the maximum.
Since secondary A is now covered by a land, output
A is a minimum.
Disk rotation continues until both secondaries are centered on a notch, but covered
by a land.
The outputs are again equal, so a null occurs in the output.
Each notch and each land nulls the transducer output.
The detection circuit generates
a pulse for each null in the transducer output.
Index (Sector) Transducer
This transducer senses notches in the edge of the sector disk (large disk at bottom of
each disk pack).
4-32
70602500 A
Each notch on the sector disk causes a differential input to the preamplifier card
amplifier (Figure 4-15).
each notch.
The detector generates a 55-tlsec "1" pulse in response to
These pulses are further processed by the MDD logic to determine if
the disk pack speed is sufficient for continued operation.
All disk packs have two closely spaced notches called index.
the beginning of a revolution of the disk pack.
These notches indicate
Some disk packs have, in addition to
index, other notches equally spaced about the circumference of the sector disk.
These notches are related to data organization on the disk pack.
Disk Cleaner Assembly
The disk cleaner assembly sweeps the disk pack recording surfaces free of any
foreign materials.
The sweep cycle occurs just before the read/write heads are
loaded during the First Seek sequence.
The assembly consists of a motor, lO-comb-mounted brushes, a reset switch, motor
to comb linkage, and a mounting base. The base mounts on the deck assembly and the
brushes are pivot mounted on the base.
motor, the linkage, and the switch.
Pivoting of the brushes is controlled by the
The motor is energized during the power on
sequence and starts a 60-second (approximately) cycle.
As the cycle proceeds, the
brushes sweep toward the spindle until the linkage causes a reversal in direction.
As the brushes return to the original position (clear of disk pack) the reset switch is
encountered and transfers.
This de-energized the Brush Motor relay and disables the
motor.
TRANSDUCER
PRIMARY·~
PREAMPLIFIER CARD
AMPL
LOGIC CHASSIS
DETECTOft
INDEX / SECTOR
PULSES
ac••
Figure 4-15.
70602500 A
t
Index/Sector Detection
4-33
The brushes are mounted using a ball-slot detent mechanism.
If power is dropped
or lost during the brush cycle, the operator can override the detent and rotate the
brushes clear of the disk pack so that the disk pack can be removed from the spindle.
The brush cycle during the next Power-on sequence will be an incomplete cycle as
the brushes automatically reset themselves.
Subsequent cycles will be normal.
Hydraulic Actuator
The hydraulic actuator drives and locks the carriage mounted read/write heads to
anyone of 203 discrete positions or cylinders of data.
Activity of the hydraulic
actuator is regulated by five solenoid-controlled valves that direct the routing of
hydraulic fluid.
The solenoids are controlled from the MDD logic chassis.
Hydraulic
fluid at a pressure of approximately 200 psi is provided by the hydraulic pump.
The hydraulic actuator (Figure 4-16) consists of a piston and sump block in or on
which are mounted a valve block, two hydraulic fluid filters, an extend piston, a
. drive piston, and five solenoid and valve combinations.
Valve Block
The valve block contains all valves and most of the related fluid passages of the unit.
The block mounts directly under the sump chamber of the piston and sump block.
Filters
The two fluid filters are locateq in the sump portion of the piston and sump block.
The primary filter is 'a large-particle screen in the pump suction outlet.
The second-
ary filter removes smaller particles from a bypass flow originating when the slow
solenoid is energized.
A third filter removes smaller particles and is located in the pump output pipe between
the pump and the hydraulic actuator.
Extend Piston
The extend piston is located in the rear cylinder of two concentrically bored cylinders
of the piston and sump block.
This piston is hydraulically positioned to either the
extend or the retracted position by the status of the extend solenoid.
4-34
Whenever power
70602500 A
is applied to the deck, the extend solenoid is energized and the related valve is closed.
Hydraulic pressure on the larger rear face of the piston drives it forward to a positive
stop. This is the extended position, and the piston remains in this position until
power to the deck is dropped. In the extended position the forward face of the extend
piston functions as a hydraulically cushioned stop for the drive piston and also establishes the hydraulic home position for the carriage.
When deck power is removed,
the extend solenoid de-energizes, the spring-loaded valve opens, and the piston moves
to the retracted position.
As a result, the effective operating chamber for the drive
piston is extended to the rear of the carriage and the carriage is retracted to a position where the heads are clear of the disk pack surfaces.
FWD DECELERATION
CHECK VALVE
'------'""Too
~ciL-~::::V1ir'1""l REV DECELERATION
VALVE 3 PSI
V
SUMP
se71
Figure 4-16.
70602500 A
Hydraulic Actuator - Power Off
4-35
Drive Piston
The drive piston operates in the smaller forward cylinder of the piston and sump
block.
This piston connects, via the ball tip, to the movable carriage (mounting
point of the read/write heads>.
The drive piston is constantly biased in the reverse
direction by hydraulic pressure applied via the forward deceleration check valve and
the minimum pressure orifice.
Piston direction and rate of motion are controlled
by three solenoids and valves.
Solenoids and Valves
The hydraulic actuator uses five solenoid and valve combinations.
The function of
the extend solenoid and valve was discussed previously.
The detent solenoid and valve controls the routing of hydraulic pressure to the detent
actuator (not physically a part of the hydraulic actuator).
When hydraulic pressure
is available and the detent solenoid is de-energized, the pressure is applied to the
detent actuator to pivot the detent pawl out of the detent gear.
When the detent
solenoid is energized, the related valve opens to vent pressure to the sump, and the
detent pawl spring pulls the pawl into the gear.
Three solenoids and valves direct the routing of hydraulic fluid to the drive piston.
All solenoid activity is controlled by signals originating in the logic chassis.
The
solenoids are located in the sump chamber of the hydraulic actuator and the control
valves are located in the valve block.
terminal at the rear of the actuator.
valve.
Electrical connections are via a solenoid
Each solenoid operates with at least one related
This valve is open when the solenoid is energized, and closed (spring-loaded)
when the solenoid is de-energized.
The forward/reverse, intermediate, and slow
solenoids each control an additional spring-loaded spool.
When the related solenoid
is de-energized, system pressure from the hydraulic pump overrides the spring
force and repositions the spool toward the spring.
Hydraulic Operations
The following paragraphs describe the configuration of the hydraulic actuator during
the various operational phases.
4- 36
70602500 A
Power Off (Figure 4-16)
No power, electrical or hydraulic, is available to the deck during this phase.
As a
result, all spring-loaded valves or devices are positioned according to spring loading.
The extend and drive pistons are in the retracted position.
This positioning occurs
during removal of power to the extend solenoid during the preceding power shut down.
When the extend solenoid de-energizes, pressure to the rear of the extend solenoid
is vented to the sump.
is decreasing.
Pressure still exists in actuator, even though the pump rpm
The reverse biased drive piston under the influence of this pressure
moves in reverse, pushing the extend piston ahead of it, to the retracted position.
Hydraulic Home (Figure 4-17)
Hydraulic home is the physical location established when the extend piston moves
to the extend position.
The actuator moves to hydraulic home at the beginning of
each First Seek operation.
It is the starting point for the forward motion required
to load and latch the read/write heads.
The sequence of events for this phase is as
follows:
~OO
1.
Hydraulic pump delivers pressure increasing toward
psi.
2.
Increasing pressure and de-energized solenoids cause forward/ reverse
and intermediate spools to move downward and slow spool to move to
right.
3.
De-energized extend solenoid vents pressure to sump.
Extend piston
stays in retracted position (Figure 4-16).
4..
When pump pressure reaches approximately 200 psi, detent actuator
pivots pawl out of detent gear and relief valves begin controlling
pressure.
5.
When disk pack exceeds required speed, power is applied to extend
solenoid.
Vent to sump is blocked, pressure moves extend piston
(and drive piston) to left, and heads move into disk pack to hydraulic
home position.
70602500 A
4-37
SEAL
CONNECTIN~
HOLES
~3
-
-EXTEND PISTON
SUMP
1\i5~~~
DETENT GEAR
~
1
~~~
t
t
SUMP
FWD DECELERATION
VALVE 3 PSI
FWD DECELERATION
CHECK VALVE
~~~~V
R.'-----..r--,)'fo/~ RELIEF
r:~_---.L=~bI...bn.I VALYE
sen
Figure 4-17.
Hydraulic Actuator - Hydraulic Home
Detent (Figure 4-18)
The detent phase occurs at the end of each seek operation.
The operation consists
of removing pressure to the detent actuator so that the detent pawl spring pivots the
pawl to engage the detent gear and lock the carriage to a track.
The sequence of
events for this phase is as follows:
4-38
70602500 A
1.
During a First Seek or a RTZS operation, the detent solenoid energizes
when the leading edge of the first track pulse is sensed as the carriage
moves forward from hydraulic home (after the heads have loaded during
First Seek).
During a forward Direct Seek operation, the detent solenoid
energizes when the leading edge of the first track pulse is sensed after
the decrement counter indicates less than 2 tracks to go to the desired
track.
The forward/reverse solenoid remains energized.
During a reverse Direct Seek operation, the detent solenoid energizes
when the leading edge of the first track pulse is sensed after the decrement counter indicates less than 2 tracks to go to the desired track.
This 'causes the forward/ reverse solenoid to energize.
Changing the
direction of carriage motion at this point allows the detent pawl to
engage the gear in the same manner as for a forward seek.
2.
Energized detent solenoid vents pressure to sump.
Loss of pressure in
detent actuator causes spring to pivot detent pawl into detent gear.
3.
The 50 psi dump valve opens to vent system pressure to sump (via
forward/ reverse solenoid valve).
This causes system pressure to
drop to 50 psi and thereby prevents excessive heating of hydraulic fluid.
4.
Slow solenoid remains energized.
Forward Operations
The length of the seek determines the forward operations to be used.
If the seek is
in excess of 26 tracks when the forward/reverse solenoid is energized, the read/write
heads move toward the center of the disk pack in the forward fast mode (26 ips).
This rate of access continues until the logic determ ines that there are less than 26
tracks to go to reach the desired track.
When this determination is made, the logic
energizes the intermediate solenoid which causes the access to continue in the forward
intermediate mode (7 ips).
When the heads are less than four tracks from the desired
track, the logic energizes the slow solenoid.
This reduces the access rate to 2 ips
(forward slow mode), which continues until the detent pawl engages the detent gear and
stops the heads at the desired track.
If the desired track is less than 26 tracks but
more than 3 tracks from the current location, the intermediate solenoid is energized
immediately.
In this case the seek would consist of a forward intermediate mode,
followed by a forward slow mode, and detent.
70602500 A
4-39
SEAL
CONNECTIN~
HOLES
~~
-EXTEND
TON
\l
SUMP
SUMP
REAR
CVL
CAP
SUMP
FWD DECELERATION
VALVE 3 PSI
FWD DECELERATION
CHECK VALVE
®©@
Figure 4 -18.
l",....----.-.---~O,.2lll RELI EF
'~_--iJ=~~ VALVE
Hydraulic Actuator - Detent
For a seek of three tracks or less, both the slow and intermediate solenoids would
energize immediately.
The seek would consist of a forward slow mode followed by
detent.
Forward motion is stopped by detenting, but there is a back-up method in the form of
a mechanical stop.
4-40
70602500 A
Forward Fast Mode (Figure 4-19): The sequence of events for this mode is as follows:
1.
With extend solenoid energized and detent solenoid de-energized, the
forward/reverse solenoid energizes.
2.
Open forward/reverse valve vents pressure to sump.
Resulting pressure
drop causes upward movement of spring-loaded forward/reverse spool.
NOTE
Pressures at left and right faces of drive piston are
equal. Drive piston moves to left because area of
face is greater
SEAL
CONNECTIN~
HOLES
~3
_ . EXTEND PISTON
SUMP
fE~~.rM
SUMP
EXTEND
PISTON
REAR
CYL
CAP
SLOW
FWD DECELERATION
CHECK VALVE
.:I-l,5L--===''P't''1''..., RE V 0 ECE LE RATION
VALVE 3 PSI
DUMP VALVE
Figure 4-19.
70602500 A
Hydraulic Actuator - Forward Fast
4-41
3.
Hydraulic fluid flows through hole in extend piston causing drive piston
to move left (forward) at 26 ips.
Forward Intermediate Mode (Figure 4-20): The sequence of events for this mode is
as follows:
1.
With extend solenoid energized and detent solenoid de-energized, forward/
reverse and intermediate solenoids energize.
2.
Open forward/reverse and intermediate valves vent pressure to sump.
Resulting pressure drop causes upward movement of spring-loaded
forward/ reverse and intermediate spools.
3.
Hydraulic fluid flows past forward/ reverse spool and around interm ediate
spool.
It then branches into parallel paths through detenting velocity
orifice and slow spool, rejoining at and passing the intermediate spool.
From here it passes through hole in extend piston causing the drive
piston to move left at 7 ips.
Forward Slow Mode (Figure 4-21): The sequence of events for this mode is as
follows:
1.
With extend solenoid energized and detent solenoid de-energized, forward/
reverse, intermediate, and slow solenoids energize.
2.
Open forward/reverse, intermediate, and slow valves vent pressure to
sump.
Resulting pressure drop causes upward movement of spring-
loaded forward/reverse and intermediate spools and slow spool moves
to left.
3.
Hydraulic fluid flows past forward/ reverse spool and around interm ediate
spool.
It then flows through detenting velocity orifice, past intermediate
spool and out forward face of extend piston to rear of drive piston.
4.
Drive piston moves left at 2 ips.
Reverse Operations
As with forward operations, the length of the seek determines the mode(s) required
to complete the seek.
4-42
70602500 A
SEAL
CONNECTIN~
HOLES
~~
-EXTEND PISTON
SUMP
'""tf"'"·~;..~~~-
MIN
-PRESS
ORIFICE
;~"
......
SUMP
1h~;~-U;;;;;;;;;~.,l,..,.IREV DECELERATION
FWD DECELERATION
CHECK VALVE
~
VALVE 3 PSI
"';"'V
5C75
. Figure 4-20.
Hydraulic Actuator - Forward Intermediate
Reverse motion is stopped by switching to forward motion and then detenting or by the
drive piston encountering the hydraulic cushion on the front face of the extend piston.
Reverse Fast Mode (Figure 4-22): The sequence of events for this mode is as follows:
1.
With extend solenoid energized and detent solenoid de-energized,
forward/reverse solenoid de-energizes.
2.
Closed forward/reverse and intermediate valves cause line pressure
to move related spools downward.
70602500 A
4-43
3.
Hydraulic fluid at rear face (right end) of drive piston flows past intermediate spool and returns to sump at lower end of forward/reverse
spool.
4.
Hydraulic fluid flows through minimum pressure orifice to left face of
drive piston and piston moves right at 26 ips.
Reverse Intermediate Mode (Figure 4-23): The sequence of events for this mode is
as follows:
1.
With extend solenoid energized and detent solenoid de-energized,
forward/reverse solenoid de-energizes and intermediate solenoid
energizes.
SUMP
, . • '.;'H.
~
'.;
.:.
..... •
• '.
....
•
{,-4
<"l~
::
~ ' ..
'
.:: ~ -
5C74
Figure 4-21.
4- 44
Hydraulic Actuator - Forward Slow
70602500 A
2.
Closed forward/ reverse valve causes line pressure to move related
spool downward.
3.
Intermediate spool rises.
Hydraulic fluid at rear face of drive piston flows past intermediate spool
and branches into two parallel paths past slow spool and through detenting velocity orifice.
The paths rejoin to pass around the intermediate
spool and vent to sump at forward/reverse spool.
4.
Hydraulic fluid flows through minimum pressure orifice to left face
of drive piston and piston moves right at 7 ips.
SEAL
CONNECTIN~
HOLES
~3
I . ,. . .,", ."'," '.
-EXTEND PISTON
ow.,
SUMP
,="'......""'
•.
EXTEND
~~~~==~~~~~~~~~
REAR
CYL
CAP
DETENT GEAR
~~
SUMP
1~,
._
. :;,
•
MIN
-PRESS
ORIFICE
1 SUMP-!I'IJo'L~
t
SUMP
FWD DECELERATION
VALYE 3 PSI
FWD DECELERATION
CHECK VALVE
~~V
®©@
50 PSI
'\
DUMP VALVE
5C79
Figure 4-22.
70602500 A
Hydraulic Actuator - Reverse Fast
4-45
SUMP
SUMP
t
SUMP
'.\
FWD DECELERATION
VALVE 3 PSI
FWD DECELERATION
CHECK VALVE
~~~V
5C78
Fi~re
4-23.
Hydraulic Actuator - Reverse Intermediate
Reverse Slow Mode (Figure 4-24): The sequence of events for this mode is as
follows:
1.
With extend solenoid energized and detent solenoid de-energized, forward/
reverse solenoid de-energizes and slow and intermediate solenoids
energize.
2.
Closed forw~rd/reverse valve causes line pressure to move related
spool downward.
Open intermediate valve causes related spool to rise.
Open slow valve causes slow spool to move to left.
4-46
70602500 A
3.
Hydraulic fluid at rear face of drive piston flows past intermediate spool,
through detenting velocity orifice, over intermediate spool, and vents to
sump past forward/ reverse spool.
4.
Hydraulic fluid flows through minimum pressure orifice to left face of
drive piston and piston moves right at 2 ips.
SEAL
CONNECTIN~
HOLES
~3
-EXTEND PISTON
SUMP
SUMP
1
SUMP
;.
~G~~~
FWD DECELERATION
VAI..YE 3 PSI
FWD DECELERATION
CHECK VALVE
~qv
RElIEF
~__~~~W~VAI..YE
5C77
Figure 4-24.
70602500 A
Hydraulic Actuator - Reverse Slow
4-47
FRAME
The frame assembly consists generally of the structural members, drawer mechanisms,
and panels of the cabinet.
Two additional subassemblies are, by virtue of their loca-
tion, considered a part of the frame: blower system and filter box.
Blower System
The blower system (Figure 4-25) provides positive pressure at the center of a disk
pack mounted on the spindle of a deck assembly.
The presence of this elevated
pressure at the center of the disk surfaces results in an outward dispersion of air
over each disk surface.
This air flow greatly reduces possible contamination and
damage of the disks and the read/write heads.
The system consists of a motor driven impeller that forces air through an absolute
filter (glass and asbestos) and related ducts upward to the spindles present in the
cabinet.
Much of the ducting is extendable to allow the deck drawers to be extended
out the front and rear of the cabinet.
Power to the blower drive motor is controlled
by the power supply BLOWER circuit breaker.
Filter Box
The filter box controls power to the cabinet in which it is located.
The box is located
in the bottom of the cabinet and is accessible by opening the cabinet rear door.
It
contains a circuit breaker (UNIT POWER) that controls application of main input
power to the cabinet power supply.
The power supply MAIN POWER indicator
monitors the status of the circuit breaker.
Frequency filters for the input power
lines are mounted inside the box.
4-48
70602500 A
l '~~\~l\~EDXTENDABLE
~_ _...L ~ }J /~
UCT
__~;;-w~=-'
AIR BAFFLE
DISTRIBUTION
CHAMBER
'"
ABSOLUTE/
FILTER
.
: BLOWER ...............
DRIVE MOTOR
H
~
~DRIVE
BELT
BLOWER
IMPELLER
5CI09
Figure 4-25.
70602500 A
Blower S ystem
4-49
DISK PACK
The disk pack is the recording medium for the MDD.
The disk pack consists of
eleven 14-inch, magnetic oxide coated disks center-mounted on a hub.
The recording
surface of each disk is coated with a layer (0.0002 inch) of magnetic iron oxide and
related binders and adhesives.
The 203 recording tracks are located in a 2-inch band near the outer edge of the
disk.
Track 202 has a diameter of approximately 9 inches, while the diameter of
track 00 is about 13 inches.
The tracks are spaced 0.010 inch apart.
The top and bottom disk surfaces are covered by protective non-recording disks.
The bottom protective disk is called the sector disk.
that are sensed by the index transducer.
This disk contains notches
The pulse outputs of the transducer are
used to determine disk pack rpm and to detect organizational segments of the disk
pack.
The lower hub of the disk pack contains a replaceable filter.
This filter removes
particles from the air supplied by the blower.. Keeping positive air pressure at
the center of the disks reduces the possibility of dust caused damage.
The disk pack has a two-piece container assembly.
simply by grasping and rotating the center hub.
The bottom cover can be removed
The top cover is designed so that it
can be removed only by installing the disk pack on the deck spindle assembly.
disk pack can
pe
The
removed from the· spindle only by using the top cover (see Section 2).
This design protects the disk pack from physical damage and greatly reduces the
possibility of contamination of the disk pack recording surfaces.
4-50
70602500 A
SECTION 5
DIAGRA.MS
I
·
'
DIAGRAMS
INTRODUCTION
This section contains diagrams that logically describe the MDD in terms of the
functions which the unit performs.
fied circuits
l
Figures 5-1 through 5-10 are flow charts, simpli-
and timing diagrams that describe the First Seek function, the Power
Off sequence, the Direct Seek (forward and reverse) function; the Return to Zero
function, and the Read/Write' operations.
a cabinet.
Figure 5-11 shows the ground scheme for
The logic diagrams for the unit are provided on pages 5-13 through 5-22.
The MDD signal distribution drawing is located on page 5-23, and the unit power
supply schematic is found on pages 5-24 through 5-25.3. Schematic diagrams for the
transducer preamplifier cards and the SPL cards are found at the end of the section.
70602500 B
5-1
VI
I
tv
NO
.........
o
Q"\
o
N
Vt
o
o
OJ
NOTES:
&
&
OECK 0 CENOTES FIRST DE:.
VIA PIl'o£R SEtlIENCE LI"ES.
THIS CDNOIT1(t,1 MA1NTAINtJ
OR SPEED OR RTlS 5 I DNALS.
::JUI~CTED TO CONTllOULR
5C~1.
91 H":"'P. C»'T OR HOS UNLD
Figure 5-1.
Power On/First Seek Sequence
SEQUENCE RELAY
KOI/KIOl
DC POWER RELAY
K02/KI02
SPINDLE DRIV[
MOTOR
f
-----'
___..,.JF:l 60
BRUSH MOTOR
~
' I
'
SEC
(APPR~X) 4'-____________________
I
I',
SPINDLE SPEED
{~(~JK~~10~
BRUSH CYCLE
SWITCH S301
--
..
~-----
"':Lof'D" :r:N A '3
I"L :/louT Q-1S
FOR~~D FF
':f( H{ "B)
,..-p
'e:
HYD ACTUATOR
EXTEND SOLENOID
q. A (-:g. \
It
_ _--_--'1
I
;-p" F .,
~ INTERMtOIATt
ANDttSLOW rr's
A-1 Rr(B) n 11.1)11
FORWARD CARR I AGE t-10T I ON
_ _-
_ _ _2_I_PS_:=RJ= 26
I,
HYDRAUL Ie
HOM[
HEADS ~,'DEO
A8(88)~C.
---LJ
IPS
-=4'--___~~2
DETENT PAW,
tb)
IN
~, S'"
REVERSE CARR I AGE MOT ION
-L
I
I
I
I
I
I
I
I
300 MS
CYLINDER (TRAG,)
PULSES
! PS
I
IF
RTZS FF
":f PI
I
==IL.-____
TRACV 00
----------:~JU1J4~~~n---I-~
________ ________
~
______~____----~__~~______~F26 'PS~L.-
~r-
______
~__
HYDRAIJUC
HOME
DETENT FF
~
At'&)
T"P
".1) ,.
ON CYLINDLR
5MS
~.I
~
Figure 5-2. Power On/First Seek Timing
70602500 A
5-3
~
I
~
DECK POWER OFF
SVS1EM POWER OFT
NO
NOTES:
& ALTMOUGH
P(¥R IS REMOVED TO DECK, DECELERATING _
IF
SPINDLE IS AIl[WATE TO OPERATE HYDRAULIC PUMP (VIA
DRI~ IlELT)AT A LEVEL SUFFICIENT TO RETUJIj CARRIAGE
TO REAR STOP .wJ HOLD l:r lItERE.
-J
o
&
m
o
DECK 0 DENOTES FIRST OECK CONII:CTEO TO CIIITROLLER VIA
POIIIIER SE W£NCE LI NES.
toV
5C59
~
o
o
:J>
Figure 5-3.
Deck or System Power Off Sequence
START SWITCH
DRIVE MOTOR PWR
RELAY K03/Kl03
SP INDLE SPrED
RE LAY Kosi KI05
HEAD LATCH
HYD ACTUATOR
SOLENOIDS
HEADS LOADED
SWITCH
REVERSE CARRIAGE
MOTION
NOTE:
(2)
CARRIAGE ENCOUNTERS REVERSE POSITIVE STOP. RESIDUAL HYDRAULIC PRESSURE
HOLDS CARRIAGE IN THIS POSITION. DETENT PAWL SPRING OVERRIDES FADING
PRESSURE TO PUll PAWL INTO DETENT GEAR.
5C60
Figure 5-4.
70602500 A
Power Off Timing
5-5
P202 J202
"B" CABLES
SEQUENCE
PO\
0.4
I
BID IRECT laNAI LINES OF ADDRESS
AND CONTROL BUS
§
n
I
II
CD
o
ICiJr:u:l
BIT 1 (2 )
I
CD
n
I I
I
I
I
CD
I I
I I
II
I I
II
NOTES:
,.SEC
TAG
I
ADD/CONT
BUS
--W
I
I
I
I
----..:..I-~_:_---L--------------------~
~
------~
I
I
')(I
-*
DECPLAS ING FROM
so
~
TO 0
----!
~----------
60~ 10
DETENT FF
ON CYLINDER
+SMS
I~------------------~~I~
REVERSE CARR I AG~
MOTION
CYLINDER (TRACK)
PULSES
--________--l1~'E~0
~:E ~-"-:-f;1...~I------IVI~111
~----!. JmJU11
I
I
INTERt-£DIATE
FF
SLOW FF
FORWARD FF
DETENT PAWL
IN
6G7
Figure 5-7.
5-8
Direct Seek Timing
70602500 A
....
......
-l
o
en
o
l\!)
CJl
o
o
:P
NO
NO" :
&. UNIT
SlLfCT ACCOMPANIfO BY TRANSMISSION OF :OGJr NlJMJlfR CODE FOR OfSIR(O DECK,
Figure 5-8.
CJl
I
CD
Return to Zero Seek Sequence
-
.......
BIT 6 OF TAG
CONTROL LINES
~~---------------------------I
.. CONTROL SELECT
TAG
~----------------------
RTZS FF
--.JIE-E- - -
300 MS
-----~~L...__________________
I
DETENT FF
~~----------------------~
I
CLR DECREMENT
COUNTER
~
REVERSE CARRIAGE
FORWARD FF
I
~26 IPs----~~~I
____________________________________________
L
I
HYDRAULIC ,....-_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~~______________H-D~
____~
I
TRACK
I 00
CYLINDER (TRACK)
PULSES
--fl-11s
I NTERMED I ATE
FF
~'---------I
SLOW FF
~L___
rI1nJl---.------In~---
I
_ _ _ __ _ _ '
FORWARD CARRIAGE MOTION
I
DETENT PAWL IN
~~--------------------------~
ON CYLINDER
Figure 5-9.
5-10
\
6G9
Retu'rr to Zero Seek Timing
70602500 A
INDEX
@
____~r-l~------------------_______________
I.
ON CYLINDER
~~------------------------
HEAD SELECT (';:;\
TAG
0..;
I
I
I
INTERNAL HEAD
SELECT
____~....:,_'f
r-
I
R
~
16 I'SEt
I
I
____""""--'-_---'F
,
READ GATE
35 j.LSEC
(MAX)
D
~AD
GATE
R
I
I
T
I
I~ ~ ~ ~
_ _ _ _ _ _ _ _ _ _ _ _ _~~,CF~2~,~5~llS~E~C~--------~2~5--j.L5~E~t--~~r---~
_
.
(60 BITS)
L---
G)
SECTOR FORMAT
"I"
"0"
~
IoO
('''15,
-25)
200
.~5
I
"0"
~~O
'
NSEC
~
h 1
10@1810\
:iJ
~
rn 0
I
"1"
~200
1~
100
..120
NSEC
±
NSEC
NSEC
~
'1"
I ?
I
"0'
~~O
NSEC-..j
.: 10;
1.
NSEC
WRITE DATA TIMING
(AT I/O CONNECTOR)
READ DATA TIMING
(AT I/O CONNECTOR)
NOTES:.
G) TOLERANCE
o
o
GAP 1 - 120 BITS - ACCOMODATES PHYS I CAL READ/WR I TE TO ERASE GAP D 1ST ANCE
AND ALLOWS HEAD SWITCH[NG AND READ AMPlIF[ER STABILIZATION TIME.
SYNC PATTERN 1 - 112 BITS - INDICATES BEGINNING OF ADDRESS AREA. CONTROLLER
KIST [N[T[ATE SYNC BYTE (OR BIT) SEARCH M[DWAY THROUGH TH[S PATTERN (REIlJ[RED
TO [NSURE THAT HEAD [5 READ[NG A KNOWN PATTERN EVEN UNDER WORST-CASE CONDIT[ONS
OF HEAD SKEW, RPM, AND [NDEX TOLERANCES DUE TO D [SK PACK [NTERCHANGE),
ADDRESS - 36 B[TS (TYP[CAL) -
TW'ELVE-BIT UPPER ADDRESS, 12-BIT L~R ADDRESS,
AND 12-B [T CHECKWORD.
~
HEAD GAP _ 120-BITS-ACCOMODATES PHYSICAL READ/WR[TE TO ERASE GAP DISTANCE,
5
SYNC PATTERN 2 -
6
DATA FIELD -
112 B[TS (M[N[KlM) -
[IIID[CATES BEG[NN[NG OF DATA FIELD.
LENGTH DEPENDS UPON DATA RECORD FORMAT.
•
POST AMBLE - 1 BIT - A PAD TO ENSURE THAT LAST BIT OF DATA IS NOT DESTROYED
OR DISTORTED.
(!) TOLERANCE
o
GAP 2 - LENGTH DEPENDS UPON FORMAT (SHOULD EIlJAL APPROXIMATELY 2.5:
OF SECTOR BIT CAPACITY). COMPENSATES FOR WORST-CASE CONDITIONS OF SPINDLE
SPEED AND OSCILLATOR TOLERANCES.
HEAD SELECT TAG LINE SHOWN OCCURRING AT LATEST ACCEPTABLE TIME RELATIVE TO
INDEX: NOT TO BE CONSIDERED A TYPICAL RELATIONSH[P.
@ INDEX
PULSE AVAILABLE TO CONTROLLER TO INDICATE BEGINNING OF TRACK OR CYLINDER.
5C69
Figure 5-10.
70602500 A
Typical Sector Format Read/Write Timing
5-11
POWER SUPPLY
LOGIC CHASSIS
DC
GROUND
TB 203
r-_---.,
l- .-
__ ..1
r l r
I
TB02 I
,- ~·--I
I
1- -
L-
-,
~
I
I
I
1
T'eoi
__I
r-
CONN MTG
BKT
1-
--:--,
_...1
TBOI
DRnOTOR
T
UPPER DECK
DRIVE MOTOR
r---
LOWER
DECK
FILTER BOX
5CIOO
GROUND
(GREEN)
Figure 5-11.
5-12
G:round Scheme
70602500 A
..
.,
DISCRETE COMPONENT
GENERAL
EXCEPT FOR SHEET 2, THESE SHEETS SHOW THE LOGIC REOUIRED TO
SUPPORT A SINGLE SPINDLE (DRAWN FOR AN UPPER SPINDLE).
SHEET 2 SHOWS 1/0 LOGIC FOR BOTH SP1NDLES.
DISCRETE COMPONENT CIRCUIT INFORMATION EXAMPLE
INPUT TRANSISTOR
(IF APPLICABLE)
FUNCTION IDENTIFIER
~
J
CIRCUIT TYPE
(SEE BELOW)
ROW A
ILOGIC CHASSU
ROW B
SPECIAL CIRCUIT CHARACTERISTIC:
OSC-OSCILLATOR OUTPUT FREQ
UTD-PERIOD OF DELAY
UPPER
FA8
GJA
HAHJA
ROWS C AHD 0
LOWER
SPINDLE DECK
ROWS C AND 0
VAA}
VAC
(NOT USED)
IIJ200 IIJ201 nJ202
CLR
IN
SPECIAL ANDIOR
FLIP-FLOP
PULSE SHAPER
lCA-
II
GENERAL SYMBOLOGY
~
~
@
TEST POINT
SCREWDRIVER
ADJUSTMENT
-+-
INDICATES ANALOG
I
IL __________ ~~~~~~
SIGNAL
\
G
GROUND
UNUSED
"
0"
INVERTER(TYPE 024, 148,OR Q22)
~5i
IN
FF
SETJI~5~
CLR
OUT
CLR
IN
~~
CLR
OUT
~
.It INPUT ON PIN 41
OF CHANNEL I
CONNECTOR .1200
Itlt0UTPUT ON PIN 41
OF CHANNEL I
CONNECTOR .120 I
OUTPUT OF TERM EXITS
CARD 18 OF ROW A ON PIN 44
SEE LISTED TERM FOR NEXT
PIN CONNECTION
17,8
~I121
~1121
CONT~1'>IUED HERE
FROM .ZONE I
Y'
jTITLE
ODD NUMBERS USED TO DESIGNATE ZONES DURING
FIRST PASS THRU ALPHABET. EVEN NUMBERS USED
ONLY I~ CONNECTIONS EXCEED 24 (IAND 0 NOT USED).
I
OF TERM EXITS CARD
9 OF ROW A ON PIN 6 SIGNAL
~~JE~S CARD 17 OF ROW A ON
_
2 INPUTS{ 4
USED
NO MECHANICAL
EJ-
124123-
6
2INPUTS{
NOT USED
GROUNDED ;,.
~}5
11..
OUTPUTS
USED
"' 3 OUTPUTS
NOT USED
} LEFT OPEN
ALTERNATE
OUTPUT OF TERM HAS TWO
Kill
---,---r-f'
KIII--..LJ
INPUT TO TRANSMITTER COMING
FROM Kill IN ROW A, AND FROM
Kill IN ROW B.
TI
OUTPVT OF RECEIVER GOING TO TWO
WIRED "AND" AT INPUT OF 1121.
}
KEY TO LOGI C SYMBOLS
00
UNUSED
CLR OUTPUTS
LEFT OPEN
ALTERNATE
2
10
~1105
~I105
0
10
UNUSED INPUTS
GROUNDED
~~~1ISN~6.~0~~Nsf5N~~gf~>NS
OUTPUT FROM RECEI VER GOING TO
1105 IN ROW A,AND TO 1105 IN
ROW B
'''-
~
4
3 OF 4
. SET OUT
}PUTS USED
LOGICAL 0 : OV} AT DESIGNATED TEST POINTS
LOGICAL I =+ 3V
BLOCK
3,4'I 7,8
A17-3
/
It. OUTPUT
ERM
1;,6
~.
SHOWN ON
DIAGRAMS
ACTUAL
SFF
.1t~~~~':vrIEc-:f~c~r~: gAG~ttK~'r~~SA!M~LW~NECTOR,
~
e;... _
SHOWN ON
DIAGRAMS
.
~>--
/
- /
-D
6
A09-6
/'
"E" IS CONTINUED ON..
ZONE 5,6
THIS SHEET IN ZONE 7 . /
,
COLLECTOR (TEST POINT)
+6V APPLICATION PIN
LO~WIRE
1,2.5,6
"-. 3 4
•
+
PIN(l5)
CONNECTORS AND JUNCTIONS
WIRED "AND" FORMED BY CONNECTING
OUTPUTS OF TWO OR MORE CIRCUITS
TO THE INPUT OF ANOTHER CIRCU I T
REMOTE ON-SHEET CONNECTIONS
1,2"
• INPUT PIN (7)
7
i5 OUTPUT
EXAMPLES
1J200-41
..........
TI
011
ACTUAL
(TYPE 148 SHOWN)
+TPUT
-®~
G • • .6 . . . . . .
KEY
UNUSED INTEBRID CIRCUIT INPUTS AND OUTPUTS ARE NOT SHOWN ON THE LOGIC DIAGRAMS
IF A GATE HAS ONLY ONE INPUT, THE GATE HAS NO LOGICAL SIGNIFICANCE AND IS NOT SHOWN
1J2~01-41
INDICATES NON-STANDARD
LOGIC LEVEL
16 15 14 13 12 II 10 9
.6 •
-L}-
TPB
IJ
G ......
FUP-FLOP(TYPE 1'24)
SET
IN
LINE RCVR
"-
ZONE
16 1514 1312 II 10 9
INTEBRID SYMBOLS
CJDD
SWITCH RCVR
TERMINATED RCVR
DELAY
"AND"
~~!}
'1~=S
Q22~
•
SPEED DETECTOR
VOLTAGE ''OR''
oU
:~:}
RCA}
RDA
RFA
U--
~
CIRCUIT
TYPE 024, A
OR B SUFFIX
INDICATES
SECTION OF
CIRCUIT
LOCATIONTHIS TERM LOCATED
AT POSITION IA ON
THE CARD PLUGGED
INTO CONNECTOR 12
OF ROW A
OUANTIZING DETECTOR
•
G •••••••
SOLENOID DRIVER
WRITE DRIVER
ERASE DRIVER
LINE XMTR
OSCILLATOR
WAVEFORM GENERATOR
OBA
QCA
QFQDA
148
ORIENTING
IMPRESSION
+ ........ .
LAMP DRIVER
OU}
024
.6
8 7 6 5 4 3 2 I
SECTION
TEST POINT B
ON CARD 12 OF
ROW A
D
+ .......
CIRCUIT
16 15 14 13 12" 10 9
LO LEVEL AMPL
ANALOG GATE
HI LEVEL AMPL
ANALOG LINE DRIVER
IAA}
IU
ICA
IDA
JAB
JBB
LAA
IotAA
MBA
.6 . . . .6
8765432 I
J-OW~
DE~K
SPIHDI..£
DISCRETE COMPONENT CIRCUIT TYPES:
tJrre..;
INTEBRID CIRCUIT PACKAGE IDENTIFICATION
(TOP VIEW)
+ ....
FUNCTION
IDENTIFIER
CABINET - REAR
LOCATIONTHIS TERM LOCATED ON THE
CARD PLUGGED INTO CONNECTOR
70FROWA
:INTEBRID
INTEBRID CIRCUIT INFORMATION EXAMPLE
LOGIC CARD LOCATIONSI RELATIONS
INPUT IS NON-STD
LOGIC LEVEL
- - - . . . , It
....,..-
4
·~~t~L:~R
1J201-1
8
· >--
1025-10
>--
~~---+-~) >--
@
IJ200-21
-
KIOO
IJ:0:~6
1025 -13
>-1025-14
>--
@
1J202-E
KI02
_
I
1026;33
~
1A3(0~
56
17
f.::':../ A26;:~.21 t~~<:' 125/~-34 A30~
lsEIl':COMl§.E'tt ()R SEEK ~02 -H
56_
?'
1025-18
->1025 -20
>-
KI04
~i~RROR
(UPPER)
TPG
@
KI04
1026-36 26
1350--+
T
/::'1
T022
A26-37 26 i~~
t:JI
>1027-10
>-TPC
12
1027-13
· >-
KI06
KIO~
•
1737
~
KI08
@
A27-14
\,4
1024-36
~
u
_
~>-
TPO
~
KI08
1
9
A27-18
)>18
i~:
6)
n
,,' "'. .
56
.
1J202-F
_
':'
1028;441
A3~!5
1028-45
A30~'.
3~
A30~
56
~02-J
REAOOAr'A{UPPER)
':'
1
~02-HH
SEEK
A28-41 31
--+ >-""':":__..,....I- DATA (LOWER)
T~
K@Orek)~"·A~~-
~
1030-10
~02-JJ~
•
1025-24
1025-37
1<511
1J200-31
1025-42
1028-17
TPG
1346
IJ200-22
r;;10
~»~~---+
AU-St
A28-40
1346
TPF
INDEX
1 J 2 1027-28
1J200-25
1J:01-25
CD
tJ200-10
1121
oE-~--~~)>-
IJIOO-JJ
~
1121
READ CYL SELECT
, I IJ201~n
1021-14
SECTPR MARK
()
r
AU;ZI~JO
/I
~~-I'"
TPH
1600
'1
IJ100-14
IJ201~84
1600
AZ7-29
TP£
(")
r
HEAD SELECT
IJ~
(
TPG
A27-36
)>-
.::::=r
1J200-27
1027-37
)>-
1~
lJZOO - 21
1025-22
24
)>-LOGIC NO. Bn 0
A2~-~
1218,1220
I
J
2
I~>
_
_
_
.......A27-41
~)>-
CONT SELECT
1027- 20
· >--
KilO
/fJ200-43
.-
,~
IJ~
-
1J200-52
rPE
23
A2~-~
1220.1221
A29-14
)-
J
1224
®
M501
1J200-47
~>-
1J200-42
~~13
I~Z~-52
CD
-
A27- 42
24 1027-25
1220,1221
I
.
.rJ.~
K1I4~i
.
@I._ 1J200-45
K 114
1:~
TP[
1029-21
23
)~
A!~
..2. I
lEQ
t ','
IJ200-4'
'-.../
IJ201-49
~
AU.-~
1J200-50
1225,1227
1J:01-50
)>-
24
1225,1227
~D-
A29-17
)>--
17
~
B
AU-II
)>-
I,
J
'---: ,'-
IJ200-70
)>-
1227,1228
I~J
3-
UNIT
ADDRI RD CYl SEl'l
CONT D/FF SEL,OR
CYl SEL
8US
IJ200-15
1227,1:228
1029-20
'/
Au-n
IJ~
(
L;OG Ie NO"BetT.'!
AU-16
)>--
oE-~--"""'~)>-
1 J 2 AZ'-28
1029-25
IOAAI
2011029
1J200-46
1
~~/!
/'91'1/
~
TPG
A2'-31
81T 0
)>1<203
-
1029-31
RELEASE
cl..a«
1J200-17
~~-------+) >-
121029-41
IJ200-72
P-aCKUNSAH
IJZOO-JO
T!..O
oE-~---+-~)>-
IJ:01-31
IJ100-31
~l IJ~~~n
1118
1J200-21
A25-41
~~-14 ,
1118
CYL SELECT
I~
AU-II
~»---4~
_ _~
~-
SEEK ERROR
1~01-21 J
1218,1220
KII2
,II
1:J200··21
->--
@
UNIT BUSY.--
KI02
A26-30
1350 --+)
21
~I,t~5
r
1400
A25-29
IJ200-17
12
l.
0
IJ2A25-28
KIOO
T!C
1J201-11
.#
TPF
A2~-
2
..
IJ200- 23
TPB
CD
®
NOT
WRITE
GATE
81T 2
READ
GATE
4
4
81T 4
16
16
BIT 5
32
CD
CD
CD
SEEK
FWD
CD
81T 3
81T 6
64
81T 7
128
ERASE
GATE
SEEK
;~~··IIOj
USED.
PARTIAL INPUT SIGNAL SHOWN. SEE SHEET 7 FOR
COMPLETE GATING INFORMATION.
......
I
81T I
1029-42
NOTE S:
IHEADICONT
SEl
SEL
'ITIONAl OUTPUTS
':II.
SHOWN ON SHEET
A
'7A
3.
AND RECEIVERS
...
5-14
....."..
-
-
~
1,2 • 5,6
........
..
...."
"..,.
....,.
~
AII-U
ROOO
A21-11
---+)
....,.
~~
AIIII8II
AlI'~1
AI::;;-- "400
)
»----
AIICIIIU
A.-I
>--"&00
111100
11101
'14
AlliE
II
A14-11
>--IUJ
"
AII-IO
-+>--1C402
All-Ie
ROO I
---+~
All-IT
Ale-n
Allnl. .
2
~
A08-41
-+>--ICIOI
11101
01
'14
IISD
III I
15
AII·I.
- + > - - "&01
II
AII'II
> - - JUS
10
All'"
A"II"A
- + > - - 1C404
A21-10
R002 - - . ,
AII-22
AI.· ••
AIICII14A
)
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C3052
+
I
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I.
REFER 10 LOGIC DIAGRAM 40091300 SHEET 4. IT FUNCTIONALLY APPLIES TO EITHER ELECTRICAL OR
MECHANICAL PLUGS. A SYSTEM OF MORE THAN ONE DECK MUST USE O"-Y ONE TYPE OF PLUG FOR
SYSTEM COMPATIBILITY. CONTROL PANEL ASSEMBLY USING THE MECHANICAL PLUG IS AVAILABLE
UNDER PART NO. 70957600. ALL UNITS ABOVE SIN 311 ARE MANUFACTURED WITH MECHANICAL PLUGS.
2.
CIRCUITS TO THE LEFT OF P600 ARE
3.
REFERENCE DESIGNATORS WITH PREFIX (A_I ARE PHYSICALLY LOCATED ACCORDING TO THE FOLLOWING:
A3 UPPER DECK "AND RELATED" HALF rI' LOGIC CHASSIS MAINTENANCE PANEL
AS UPPER DECK CONTROL PANEL
CHANGE DESIGNATORS FROM A3 TO A4 AND AS TO A6 FOR LOWER DECK SCHEMATIC.
R315::
:
I '--L--
I
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NO
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- - - - - - - -,
5TB501
I
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I
PRESS SWITCH ON
HY DRAULIC PUMP
I
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THESE
SWITCHES ARE
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SHOWN
BY THE
FOR FUNCTIONAL REFERENCE
MECHAN ICAL
ONLY.
LOGIC PLUG.
A5CSOI
C
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A5CS05
~
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L..-_ _ _ _- I
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SILICON, 92115023,
3,
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3 ~I------------------------------------~
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NOTES
C3
.
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92115023
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4.
FOR
SEE
6
R2
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.,
I
LIST Of' MATERIAL
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CORPORATION
PREAMP DETENT
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24
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READ PREAMPLIFIEII, TYPE AMP-I. EF7400. 11844900
9. COMPONENT ASSY 50.10.210.1.
T'-W
11M
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REV A Rge WAS 3 PARALLEL
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ALL RESISTOR TOLERANCES !
ALL RESISTOR VALUES IN OHMS.
ALL RESISTo.RS RATED 114W.
.111 ASSY
TC3A
38
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ALL DTHER DIDOES, SILICON. 921150.23.
A AIIIY
TczA
4
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140.
SILICON, NPN, 2N3569.
DIDDE. GERMANIUM, 9211.0.0.2.
6. UNLESS OTHERWISE
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1
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50210101.
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ALL INTEGRATED PACKAGES SHOWN IN THE
SCHEMATIC HAVE A DECOUPLING CAPACITOR
CONNECTED TO PIN 8 (+6VDCI AND PIN 16
(GNDI. ALL C8 __ CAPACITORS ARE ASSOCIATED
WITH THE INTEGRATED MCKAGES. THE LAST
TWO ALPHA NUMERIC
CHARACTERS IN THE
REFERENCE DESIGNATION OF THE INTEGRATED
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IT'S ASSOCIATED CAPACITOR ARE THE SAllIE
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c
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21
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ALL DIODES,
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33
3
CRIlJe
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SCHEMATIC DIAGRAM
HEAD SELECTION
t
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7
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I. A LL DIODES SILICON 92115021.
III
4-11
lIT
~
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Z4,
~I
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15
148
(
1
12
2. UNL£SS OTHEIlWlIE SPECIFIED ALL CAPilCITOII
&
15
VALUE. AIlE
t
10'110
ALL INTEGRATED PAa&y-------------------------------------------------------------------------------------------~:
+.v
CR96A
SHOWN IN THE SCHEMATIC
+6i","
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INTEGRATED PACKAGES
HAVE A DECOUPLING CAPACITOR CONNECTED TO
PIN 8(+6VDC) AND PIN 16(GND). ALL C8 __ CAPACITORS
ARE ASSOCIATED WITH INTEGRATED PACKAGES
THE LAST TWO ALPHA NUMERIC CHARACTERS IN THE
REFERENCE DESIGNATION OF THE INTEGRATED PACKAGE .
ANe THE REFERENCE DESIGNATION OF IT'S ASSOCIATED
CAPACITOR ARE THE SAME.
IlV
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12K
ALL
Lt
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A
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'70602500
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VALUlS IN OH .. 5
RESISTORS RATEC
1/4 WATT
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50105506
2.21(
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1.2K
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ALL INTEGRATED PACKAGES SHOWN IN THE
=N'fc~~DH~~E:'ND:~?v~~'rA~~~~T~=(GNDI
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I~"" I
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--------------~~~_+--------------------------------------------~17
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9
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t
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2.
25
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TYPE
C6F,
UNLESS OTHERWISE SPECIFIED
ALL CAPACITOR VALUES ~IO'l'.
Ie
B UNLESS OTHERWISE SPECIFIED
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ALL RESISTOR VALUES IN OHMS
ALL RESISTORS RATED 114W
£. HAVE
ALL INTEGRATED PACKAGES SHOWN IN THE SCHEMATIC
A DECOUPlING CAPACITOR CONNECTED TO PIN B
50
54
26
;"a~wl_
52 (
• ..v
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2.7"
12
(+ 6VDCl AND PIN 16 (GND)'
ALL C8 __ CAPACITORS
ARE ASSOCIATED WITH THE INTEGRATED PACKAGES
THE LAST TWO ALPHA NUMERIC CHARACTERS IN THE
REFERENCE DESIGNATION OF THE INTEGRATED PACKAGE
AND THE REFERENCE DESIGNATION OF IT'S ASSOCIATED
CAPACITOR ARE THE SAME
10 COMPONENT ASSY 50181701
42
22
5.
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ALL DIODES SILICON,92115021
.& :t~E':;i.~R~l~~
:A~:~g~~L~:c?~~P~"cI~~~
CONNECTED TO PIN 8 1+6VDCl ANO PIN 16 IGNDl
ALL C8 __ CAPACITORS ARE ASSOCIATED WITH
THE INTEGRATED PACKAGES. THE LAST TWO
ALPHA NUIIERIC CHARACTERS IN THE
REFERENCE D£SIGNATION OF THE INTEGRATED
PACKAGE AND THE REFEMIICE DE SIGIIA nON
OF IT'S ASSOCIATED CAPACITOR ARE THE
3
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NOTE.
&
&
26
TRANSISTOR. SILICON. NPN. 2N3569. 50210801.
TRANSISTOR. SILICON. PNP. 2N3640.50210400.
3
ALL OTHER TRANSISTORS. SILICON. NPN, 2N3646.
50210300.
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6.
UNLESS OTHERWISE SPECIFIED'
All RESISTOR TOLERANCES t5% .
7.
UNLESS OTHERWISE SPECIFIED
ALL CAPilQTOR VALUES tiD'll..
ALL RESISTOR VALUES IN OHMS.
ALL RESISTORS RATED 114W.
44
20
&
••V
Ie
ALL INTEGRATED PACKAGES SHOWN IN THE
SCHEMATIC HAVE A DECOUPLING CAPACITOR
CONNECTED TO PIN 8 (+6VDC) AND PIN lEi (GND).
ALL C8 __ CAPACITORS ARE ASSOCIATED WITH
THE INTEGRATED PACKAGES. THE LAST TWO
ALPHA NUMERIC CHARACTERS IN THE REFERENCE
DESIGNATION OF THE INTEGRATED PACKAGE
i
::~~:T~;~~~~~~Tg~S~;:T+~~ ~~~~~
CII4A
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COMPONENT ASSY 50182502.
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34
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FAULT STATUS
117G
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50182602
7
70602500 A
6
5
t
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.... , .
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UNLEss
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ALL
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ALL
.~
OTHERWISE
SPECIFIED
RESISTOR TOLERANCES ± 5'110
RESISTOR
VALUES IN OHMS
RESISTORS RATED 1/4 W
CAPACITOR VALUES tlO'!!.
& :~~
~~~~!A~~~C~:~:!~~~O~~OWN IN THE
SCHEMATIC HAVE A DECOUPLIN8 CAPACITOR
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c
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NUMERIC CHARACTERS IN THE REFERENCE
DESIGNATION OF THE INTEGRATED
PACKAGE AND REFERENCE DESIGNATION OF IT'S
ASSOCIATED CAPACITOR ARE THE SAME.
COMPONENT loSSY
50183302
TRANSISTOR, SILICON, NPN. 2N3646 , 50210300.
TRANSISTOR. SILICON. NPN. 2N3569. 50210801.
DIODE. SILICON. ZENER
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,
SECTION 6
MAINTENANCE
Information for this section is included in BMlA.5
Multiple Disk Drive.
I
Pub. No. 70602400
SECTION 7
MAINTENANCE AIDS
I
MAINTENANCE AIDS
GENERAL
Section 7 contains information on logic circuits, the criteria used in determining the
further usability of read/write heads and disk packs, and the tester card used in the
Maintenance section.
SPL LOGIC
The logic used in this device is generally termed SPL (Silicon Peripheral Logic).
consists of two styles of circuits: discrete component and Intebrid.
It
Discrete com-
ponent circuits contain individually identifiable resistors, capacitors, transistors,
etc.
An Intebrid circuit is a chip containing an integrated circuit(s).
PHYSICAL DESCRIPTION
All components of the SPL cards are mounted on one side of a printed circuit board
(Figure 7 -1) which is 6 inches wide and 4-3/4 inches high.
The cards are pluggable and are restricted in vertical and horizontal movement by
card guide spacers when inserted into the panel connectors.
A card puller
(PN 84146900) which grips the upper and lower edges of the card is used for removing
the cards.
No special tools are required to insert a card.
Numerical designators (1 through 99) are etched on the non-component side of the
board to identify each transistor.
A 4-character alphanumeric designator is etched
on the non-component side of the board to identify the card type.
(alphanumeric) also appears on this side.
A matrix code
Non-amplifying components such as Intebrid
chips, resistors, capacitors, diodes, etc., are not marked.
70602500 A
7-1
o
TEST POINTS
2
o
o
o
o ~ '-
t:?\
3
B
-I
I
--t - -t- :
fI\ INTEBRID
\:.-J CIRCU IT
(CHIP)
-c:::::J-
I
DISCRETE
COMPONENTS
o
MATRIX CODE
(ETCHED)
E
COMPONENT SIDE
END
NON-COMPONENT SIDE
NOTE:
01NTEBRID CIRCUIT LOCATED AT 2B
(VIA MATRIX CODE)
Figure 7 -1.
5CII!5
SPL Card
Pin Assignments
The module connector consists of a 37 -pin male blade connector mounted along the
4-3/4 inch board dimension on the component side of the board.
Connector pins are numbe red from the top starting with pin 1 and continuing through
pin 50 on the bottom.
Thirteen pin positions are omitted.
These are 3, 7, 11, 15, 19,
23, 27, 3 1, 35, 3 9, 43, 47, and 49.
Six pins of the 37 -pin connector are reserved as follows:
7-2
Pin 2
Ground
Pin 4
-6v
Pin 6
-20v
Pin 46
+20v
Pin 48
+6v
Pin 50
Ground
70602500 A
Test Points
Test points are located near the edge of the module opposite the connector and in other
strategic places on the component side of the board.
betically starting with A on the top, outer edge.
Test points are assigned alpha-
In most cases, test points A and Z
are available for ground reference.
USE OF RELATIVE LEVEL INDICATORS
The relative level indicator is a small circle located at the origin or termination of a
signal line, and tangent to a logic symbol.
The presence or absence of this indicator
tells the conditions that are necessary to satisfy the function of the logic symbol.
The
presence of the circle indicates a 0 logic level on that line is needed to satisfy the
function.
The absence of the circle represents a logical 1 needed to satisfy the function.
AND FUNCTION
The relative level indicator used with an AND logic function may be interpreted in this
way: Only under the stated input conditions will the stated output condition occur.
Under all other input conditions, the stated output will not occur.
For example,.
Figure 7 -2 indicates that only when A and Bare 0 logic level (indicated by the circle
on their respective inputs) will the output of C be a logical 0 (indicated by the circle
on the output line).
Under all other input conditions, output C will be a logical 1.
_:_____~_.__A
__~t>~---CILl.
Figure 7-2.
70602500 A
AND Function
7-3
OR FUNCTION
The relative level indicator used with an OR logic function may be considered as
follows: If one or the other, or both of the stated inputs are present, then the stated
output will occur.
Only when both of the stated inputs are not present will the stated
output be changed.
For example, Figure 7-3 indicates that if either A is a logical 0
(represented by the circle on its input) or B is a logical 1 (represented by no circle on
its input), or both A is a logical 0 and B is a logical 1, then output C will be a logical O.
Only when A is not a logical 0 and B is not a logical 1, will C not be a logical O.
A
B
• LZ T
Figure 7 -3.
OR Function
A complete truth table for use with relative level indicators is given in Figure 7 - 4.
INFORMATION CONTAINED WITHIN LOGIC SYMBOLS
Discrete Component Circuits
Figure 7 - 5 shows a schematic (as shown on card schematic diagram) and the logical
representation (as shown on logic diagrams) for the same discrete component circuit.
Four lines of information are contained within the logic symbol.
The top line is the
function identifier and designates the broad logic function of that particular symbol.
In this case, PA represents a high level amplifier, the logic function performed by the
circuit.
The third line, also an alphabetic code, designates the circuit type being used
(HAB).
The circuit type is a subdivision of the function identifier (a specific high level
amplifier).
By using the circuit type deSignator, detailed information on that parti-
cular circuit can be derived in the following paragraphs (see Discrete Component
Circuit Descriptions).
7-4
70602500 A
I
~....---....A
A
I
F
G
A
0
0
I
0
0
I
0
•
I
I
0
0
I
A-
I
I
0
I
I
A-
I
F
G
F
0
0
0
I
:=d AF-G
0
I
0
I
I
0
I
0
I
I
0
I
A-
I
F
G
F
0
0
0
I
:=1 F-G
0
I
I
0
I
0
0
I
I
I
0
I
A
I
F
G
0
0
0
I
0
I
0
I
I
0
0
I
I
I
I
0
:
:~
F
Ap-G
:=J. . . I
---'A
I
: =4....-.-.-.A
A
I
: _ _-:_ _A......
F-
: _ _....._ _A......
F
6
• lit
I
F-F
• lit
I I
G
:=1 F:=1
fR
fR
G
I
:=d F-F
'R
:=d
• lit
G
1
:~
:~
• lit
F-F
• lit
G
1
JUI
Figure 7-4.
70602500 A
F
Truth Table
7-5
+20V
R22F
+20V
~------OUT
041
22
PA
A705
39 HAB
A22
R22A
R22D
-20V
41
40
-=
R22B
039
+20V
040
R22G
OUT
R22E
+20V
Figure 7-5.
5 CliO
Discrete Component Circuit
The second line within the symbol is used to differentiate that particular symbol from
similar symbols that appear in the logic diagram.
It is called the logic term and con-
sists of a one-letter prefix and an assigned identification number (in this case, A 705).
The numbers on the input lines to the symbol indicate which transistor is driven by that
input line.
For example, the upper input has a number 22 on its line, showing that it
drives transistor number 22 (ie., Q22 on the card schematic diagram).
The output lines also have numbers associated with them.
which transistor directly feeds the output line.
These numbers indicate
For example, the lower output line has
a number 40 above it, indicating that the output from transistor number 40 (Q40 on the
7-6
70602500 A
card schematic diagram) drives the lower output line.
For other circuits additional
transistor numbers may appear below the logic symbol.
These numbers refer to
internal transistors that are not directly connected to any input or output line, but are
a part of the circuit.
Intebrid Circuits
Figure 7 -6 shows the schematic version (as shown on card schematic diagram) and the
logical representation (as shown on logic diagrams) for the same Intebrid circuit.
The
first and second lines of information inside both blocks are the same, and have the
same meaning as for the discrete component circuit.
Line three identifies the Intebrid circuit type (D24), and on the logic symbol additionally identifies the section (B) of the circuit chip.
(Refer to the Key to Logic Symbols
sheet of the logic diagrams for detailed coverage of Intebrid circuit types being used
and the number of sections in each chip. )
The fourth information line in the block is for location information.
On the schematic
version, lC identifies the matrix block (Figure 7-1) in which the chip is located and B
identifies the section of the chip.
The fourth line of the logic identifies the card
matrix location and it also identifies the logic chassis row (A) and the mating connector
in the row (13).
LOGIC
SCHEMATIC
CHIP
REFERENCE
/DESIGNATOR
ZIC-B
1 0 - -.....
- - -......
CI RCUIT
TYPE
FUNCTION
INPUT PIN~
I
10
OUTPUT PINS
LOCATION (ON CARD)
AND SECTION
IDENTIFIER
LOGIC
TERM
CIRCUIT TYPE
AND SECTION
t.:
OUTPUT PINS
(SHOWN AS CABLING)
L CATION UN LOGIC
CHASSIS AND ON CARD)
lie 112
Figure 7 -6.
70602500 A
Intebrid Circuit
7-7
Pin information for the schematic and logic versions are similar with two exceptions.
The logic version does not show unused chip
all unused pins connected to ground.
origin for each chip output
pin~
pins~
Secondly~
whereas the schematic version shows
the schematic version shows a separate
while the logic version may show a single origin and
identify each pin as the line branches to its destination.
This scheme is termed
cabling and conserves space and preserves appearance.
WIRED FUNCTIONS
The logical representation for wired functions is shown in Figure 7-7.
These functions
are used where circuits have the capability of being combined as an AND function by
having the outputs connected.
This is simply a physical connection and no electrical
or electronic components are involved.
However~
the logical interpretation of the
wired function is consistent with the AND truth table in Figure 7-4.
used to depict logic flow into the gate.
Arrowheads are
The gate output has no arrowhead.
,
A
I
j
J
I
I'
SCIII
Figure 7-7.
7-8
Wired Functions
70602500 A
STANDARD/NON-STANDARD LOGIC LEVEL INDICATOR
The input to a logic function at a voltage other than the standard logic level is represented by a slash across the non-standard level line.
Absence of the slash (or absence
of an A, see below) indicates a standard logic level on that line.
Figure 7 - 5 illus-
trates the use of this symbol.
When the input signal to a logic function is an analog signal, the input line will have
an A across it.
INTEBRID CIRCUIT DESCRIPTIONS
Detailed functional descriptions and schematic diagrams for Intebrid circuits are
provided in CDC Pub. No. 60201000.
DISCRETE COMPONENT CIRCUIT DESCRIPTIONS
Figures 7 -8 through 7 -51 are the schematic diagrams for the discrete component
circuits used in this device.
A verbal description supports each circuit diagram.
The order of presentation is in accordance with the 3-letter alphabetical circuit type
designator.
70602500 A
7-9
Low Level Amplifier - F AB
The FAB circuit (Figure 7-8) is a low level amplifier that amplifies the analog read
signal from the head.
Input B is a gate input.
When input B is +20v, diodes CRNA, CRNB, CRNC, CRND, CRNE and CRNF are
forward biased.
The voltage between CRNC and CRNE and between CRND and CRNF
is clamped at approximately +2. Ov.
With all diodes forward biased, the read signal
can pass to the amplifier.
When input B is ground, diodes CRNG and CRNH clamp the voltage at +0. 6v.
reverse biases the input diodes.
This
No read signal can enter.
The preamplifier is a three stage amplifier using an emitter follower output stage for
low output impedance.
The integrated preamplifier has discrete component ac and dc
feedback.
AC feedback is provided by CNE and RNH in the top half and CNF and RNJ in the lower
half of the circuit.
The signal is brought back to the emitters of the input stage to
increase input impedance.
DC feedback is provided by RNG, RNE and CNC (to ground) in the upper half and RNK,
RNF and CND (to ground) in the lower half of the circuit.
This feedback helps to
stabilize the output.
Capacitors CNG, CNH and CNJ, and CNK filter noise from the +20v and -20v power
supplies, respectively.
The electrolytic capacitors filter low frequency noise.
The
paper capacitors filter high frequency noise.
Open loop gain in the amplifier is approximately 180.
Closed loop gain in the amplifier
is approximately 30.
7-10
70602500 A
+20V
8
OV
A 0 RC
o OR
E
CNG
15",F
+20V
D
~
RN H
6.81K
C NC
IOOOPF
RNE
RNG
10K
C NE
1000PF
10K
ACRNA CRNC
CRNE
C NA
1000PF
X
N
-20V
P
Q
CNI
RNF
101<
.::::c
CNF
1000PF
RNJ
6.81 K
1000 PF
RNK
10 I<
E
CNO
1000PF
RNM
CNJ
O.OI".F
1.2 K
+
CNK
15",F
NOTEI VOLTAGE
AND COMPONENT VALUES
-
-20V
ARE FOR REFERENCE ONLY.
5 C31
Figure 7-8.
70602500 A
Low Level Amplifier - FAB
7-11
Gated Intermediate Level Amplifier - GJA
The GJA circuit (Figure 7-9) is an analog gate that is controlled by input B.
input B is +20v, both transistors are on.
All analog signals pass through the circuit.
Capacitors CNA and CNB ensure that only analog signals are passed.
noise spikes from the gating signal.
When
CNC filters
Dc power for the transistors is supplied by the
circuit in the next stage.
When input B is +0.2v, both transistors are off.
No signals pass through the circuit.
+20V
8
OV
If
::=120MV
A OR C
i
,
E OR 0
I - - -__~--+----\---_I_--.L..-- ~ I
*
I
A
20M V
CNA
1500PF
.:::c
C NC
1000 PF
O---)~~--~--------~
RNA
ON
1.961<
D
E
CNI
C
RNI
OP
1.961<
1500PF
O---)I~--~--------NOTEI
VOLTAGE AND
COMPONENT VALUES
ARE FOR REFERENCE
ONLY.
lell
Figure 7-9.
7-12
Gated Intermediate Level Amplifier - GJA
70602500 A
High Level Amplifier - HAA
The HAA circuit (Figure 7 -1 0) is gated by an analog gate circuit (GJA) and provides
the load and biasing for that circuit.
The preamplifier, ac feedback and dc feedback are identical to the FAB circuit.
Capacitor CND is added to the output of the second stage to decouple high frequency
noise.
High Level Amplifier - HAB
Input to the HAB circuit (Figure 7 -11) is a balanced square wave.
Output is also a
balanced square wave that follows the input.
When input A is positive, B is at Ov.
QQ falls to near ground.
Transistor QN is on and QP is off.
Transistor QQ is off.
With QP off, QR turns on.
Output C rises to approximately +0. 7v.
Output D falls to ground.
When input B is positive, A is at ground.
and QR is off.
The base of
Output C is at ground.
Transistor QN is off, QP is on, QQ is on
Output B rises to +0. 7v.
High Level Amplifier - HJA
The HJA circuit (Figure 7-12) increases the input signal power to transmit over a
coaxial cable.
The input is a differential signal of approximately 3. 6v peak to peak.
The input signal across A and B is divided between resistors RNA and RNB.
sistors QN and QP are forward biased with a gain of 3.
Tran-
The -20v through resistor RNH
and diodes CRNA and CRNB and through resistor RNJ and diodes CRNC and CRND
forward biases QQ and QT, respectively.
Transistors QQ and QT are in a common
collector configuration to provide a current gain.
Transistors QR and QS are emitter followers that draw very little current from QQ
and QT.
They provide low impedance for'discharging CNC and CND, thus reducing
delay time when crossing the zero volt point.
Output voltage is apprOXimately the same as input voltage.
Output current is 20 rna
maximum.
70602500 A
7-13
f
A OR B
~120
TP
A
C
PA
B
HAA
MV
!
f
C OR D
D
~3.6V
~
TP
CNF
15 JLF
~+
CNG
O.OIJLF
-=
CNA
1000PF
PCNK
O.OIJ'F
A
+20V
RNG
1.2 K
TP
RNC
10 K
RNA
10K RND
6.81 K
C NC
3900P F
C
RNM
2 15
+20V
B
CNL
O.OIJL F
D
RNN
215
RNE
6.81 K
RNF
10K
CNE
3900 P F
TP
RNH
1.2 K
NOTE: VOLTAGE
-20V
AND COMPONENT VALUES ARE FOR
REFERENCE
ONLY.
5C30
Figure 7 -1 o.
7-14
High Level Amplifier - HAA
70602500 A
+ 0.6 v
A
OV
+ 0.6
B
V
OV
+ 0.7
C
V
Ov
+ 0.7 V
D
OV
+ 20V
+20V
RNC
S.6 K
CNA
A
3'00P F
o---i
t------4......-----+--0.1
--~'~A'--20V
......- -.....
+20V
RNG
2.2 K
+20V
NOTE: VOLTAGE AND COMPONENT VALUES A RE
FOR
REFERENCE ONLY.
SC!S
Figure 7 -11.
70602500 A
High Level Amplifier - HAB
7-15
A-B
TP
C
A
PA
B
,
,*
3.6V
C-D
HJA
0
3.6V
+
VOLTAG E
TP
~20MA
C OR 0
CURRENT
PEA K
RNK
270
+ 20 V ...--"'vv\,-.....- -__
ON
RNF
2.15K
RNA
2.15K
+20V
RNH
10K
-
R NE
1.5K
-20V
-20V
RNM
RNJ
10K
IK
as
OP
RNP
100
CRNC
CRND
CN 0
O. a III
TP
OT
NOTEI VOLTAGE AND COMPONENT
Figure 7-12.
7-16
VALUES ARE
FOR
D
~
RE FERENCE ONLY.
High Level Amplifier - HJA
70602500 A
Lamp Driver - IAA
The IAA Circuit (Figure 7 -13) sinks a current of 91 ma to drive a lamp.
Capacitor
CNB slows down switching time of QS and provides a ramp output to prolong the life of
the lamp. A" 1" input at either A or B or both lights the lamp.
Bare "0" is the lamp extinguished.
Only when both A and
3V
A OR B
I:~: I
A
B
,
I
~
C
OV
JE-20#oLSEC
I
91 MA
I
C
CURRENT
~
140MS
~
o
M A
+6V
RNA
1.2K
RNB
1.2 K
RNE
lOOK
QR
A
QP
CRNA
C
CNI
O.OIIL F
B
R NF
3.9K
RNC
1.2 K
N()TE: VOLTAGE AND COMPONENT VALUES
Figure 7-13.
70602500 A
ARE
RNH
'680
FOR .REFERENCE ONLY.
selS
Lamp Driver - IAA
7-17
A "1" at either or both inputs turns QN on.
CNA discharges through RND and QN.
The base of QP goes to ground.
Transistor QP is off, so the base of QQ (3. 8v) is
more positive than its emitter.
Transistor QQ is on, causing current to flow through
RNJ.
The voltage drop across RNJ (approximately O. 7v) turns QR on.
QS turns on.
Transistor
Zener diode CRND clamps the voltage across RNL at 2. Ov, which is a
current of 91 rna.
A "0" at both inputs turns QN off.
QP on, QQ, QR and QS are off.
CNA charges through RNE until QP turns on.
With
No current flows in the lamp.
Lamp Driver - lBA
The lBA circuit (Figure 7-14) sinks a constant load current of 200 mao
Capacitor CNA
ramps the output to prolong the life of the lamp connected to output B.
A "1" on input A turns QP on.
The base of QN is at ground.
The base of QR is clamped at +2. 7v by Zener diode CRNC.
Transistor QN is off.
Transistor QR is on.
A
2-volt drop across RNE assures a 200-ma current.
A "0" on input A turns QP off.
base of QR goes to ground.
The collector clamps at +0. 7v when QN turns on.
Transistor QR is off.
The
No current flows.
Lamp Driver - lCA
The lCA circuit (Figure 7-14) functions as a switch supplying current to a lamp at
output B.
When input A receives a "0" (ground) signal, the lamp turns on.
When
input A receives a "1" (+3v) signal, the lamp turns off.
Output B is connected through a lamp to a voltage supply, typically +20v.
receives a "0" signal, transistor QN turns off.
bias transistor QR through resistor RND.
When input A
This allows the +6v supply to forward
Transistor QR turns on, conducting current
from the voltage supply, through the lamp and RNE to ground.
When input A receives a "1" signal, QN turns on.
The lamp lights.
Transistor QN conducts current
away from the base of QR, removing the forward bias.
Transistor QR stops conducting.
The lamp goes out.
7-18
70602500 A
+3V
A
r-
Td1
B
VOLTAGE
~
~
lOY
I BA
2.2V
Td
200MA
B
18A
OV
CURRENT
OMA
+3Y
A
OV
~
.I.CA
+ 20V
B
VOLTAGE
2.2 V
8
IC A
OMA
CURRENT
-tIMA
CNA
B
0.0 IJL F
®
RNA
1.2k
®
RNO
390
+6V
RNC
1.2k
Qft
r
-
-
-
- --
QN
®
CRNC
2.7V
OP
RN8
1.2 k
RNE
10
NOTES
I.
®
I
VOLTAGE AND COMPONENT VALUES
FOR REFERENCE ONLY.
ARE
COMPO NENT AND CONNECTI NG WI RES NOT
USED ON ICA. DOTTED LINE SHOWS Q.N
BASE CONNECTION FOR ICA, ENTIRE
CIRCUIT (LESS DOTTED LINE) FOR X8A.
5C 5
Figure 7-14.
70602500 A
Lamp Driver - IBA, lCA
7-19
The voltage drop across RNE when QR conducts is directly proportional to the load
current.
At a load current of 200 rna, the voltage across RNE is 2 volts.
of QR cannot go more positive than +2. 7v because of Zener diode CRNC.
The base
Therefore,
QR starts losing its forward bias when the load current reaches 200 rna (2 volts across
RNE).
Transistor QR is thereby protected against a short circuit.
Low Speed Driver - IDA
The IDA circuit (Figure 7 -15) acts as a switch.
Outputs Band C are connected through
external resistors and a common load (typically a solenoid) to an external voltage
supply.
A" 1" at input A causes current to flow through the external load.
A "0" at
input A shuts off the current flow.
A "0" at input A turns off transistor QN.
The emitter and base of QP are both at +6v.
Transistor QP is, therefore, not conducting, which keeps QT from conducting.
The
left side of capacitor CNA charges to +6v, while the right side is held at approximately
+0. 7v by resistor RNH and the base-emitter voltage drop across QQ.
Transistor QQ
is held on by the current through RNH, driving the base of QR to ground.
QR is off.
The base of QS is at ground and is off.
Transistor
No current flows through the
external load.
A "1" at input A turns on transistor QN.
on.
The base of QP goes to ground, turning QP
This allows the +6v supply to flow through RNE to the base of QT, turning it on.
Then, 200 rna of current flows through the external load and QT to ground.
When the collector of QN goes to ground, the left side of CNA also goes to ground.
This back biases the base-emitter junction of QQ by approximately 5. 3v (the original
voltage across CNA).
Transistor QQ turns off, allowing the base of QR to go positive.
Transistor QR turns on and drives the base of QS positive.
Transistor QS turns on
and allows an additional 850 rna of current through the external load and QS to ground.
The base of QQ then rises toward +6v through the charging action of resistor RNH on
CNA.
When the base of QQ reaches +0. 7v, QQ turns on and QR turns off.
the current flowing through QS by driving the base of QS to ground.
This stops
The 850 rna of
current through QS lasts approximately 7 ms.
CNB limits the rise and fall time of the 850-ma current pulse.
7-20
70602500 A
M,M
I~:~ b::
A
·0·
A
RNA
RNG
RNH
1.2K
'K
10K
C~
+40V
B~"'7."'(
+40V
IRD
IRD
X
CNC
O.OI"F
QIt
CRI
0.0'".'
RNL
ZIO
NOTE: VOLTAGE AND COMPONENT VALUES ARE
Figure 7-15.
,
70602500 A
FOR REFERENCE
ONLY.
Low Speed Driver - IDA
7-21
Write Driver - JAB
The JAB circuit (Figure 7-16) provides current to the write heads so that data may be
recorded.
Outputs E and F are connected to opposite ends of the write head, which is
center tapped to ground.
When input A is positive, current flows through output E to
its half of the write head.
When input B is positive, current flows through output F to
its half of the write head.
When A is positive and the unit is writing, B is negative.
When A is negative and the unit is writing, B is positive.
Therefore, only one half of
the write head may be activated at anyone instant while the unit is writing.
With a positive charge on input A transistor QN is off.
the emitter of QS is positive.
The negative voltage at B turns transistor QT on.
drives the emitter of QR negative.
about -2v.
-2v.
The base of QR is positive and
This
Transistor QR conducts,driving the base of QQ to
Transistor QQ is an emitter follower, so the emitter of QQ is also near
The -2v on the base of QP turns QP off.
No current flows through output F (-20v
through resistor RNA only reverse biases an external diode).
QS goes slightly negative.
With QT on, the base of
Transistor QS is off, allowing the base of QU to go to +40v.
Transistor QU is an emitter follower, so the emitter of QU also goes to about +40v.
The +40v on the base of QV turns QV on.
Current now flows from a +40v supply con-
nected to output G through transistor QV and its half of the write head to ground.
A
resistor lies between output E and the write head to limit the current flow in the write
head.
When input A goes negative and B goes positive, QN and QS are on and QR and QT
are off.
On the bases of QQ and QU are currents of +40v and -2v, respectively.
emitter of QQ goes to about +40v.
QV is off.
The emitter of QU goes to about -2v.
No current flows through output E.
Transistor QP is on.
The
Transistor
Current flows
from the +40v source connected to output G through QP and its half of the write head
to ground.
Input D supplies a negative voltage when the unit is writing to reverse bias diodes
CRNA and CRNF.
negative.
If the unit is not writing, D is grounded and both inputs A and B go
This turns on QR and QS.
Transistors QP and QV are, therefore, off and
no current flows through the write head.
7-22
70602500 A
OV
A
-3. BV
OV
B
-3.BV
A
E
POW
B
C
F
F
D
B.5 MA
CURRENT
G
OM A
E
8.SMA
CURRENT
OMA
F
G
~
-
C
CNA
O.I,...F
CRNC
CR NO
RHO
33K
-20V
-20V
~--~----~~~
CRN A
CRNF
CRNB
CRNE
A
/"f'CNC
-:!:- 0.0 I,...F
B
- 20V
o
1: NHIBIT
NOTE: VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE ONLY.
IICIIII
Figure 7-16.
70602500 A
Write Driver - JAB
7-23
Erase Driver - JBB
The JBB circuit controls the current driving the erase heads.
When input E
(Figure 7 -17) is a high voltage, output H provides current to erase heads.
When input E goes to a high voltage, capacitor CPA charges, causing a 10-tJsec delay
before transistors QR and QP turn on completely.
supply in a fault detect circuit.
Output G is connected to a +40v
When QR is on, current flows from G through QR to
the erase head connected to output H.
The ramp output protects the information on
neighboring tracks from being destroyed.
When E drops to Ov, CPA discharges through RPA.
off.
After 10 tJsec, QP and QR are
Output H is at Ov.
Line Transmitter - LAA
The LAA circuit (Figure 7-18) provides a positive voltage output at C and a negative
voltage output at D when either A or B or both are a "1" input.
When A and Bare
both "0", the output is determined by the external load circuit connected to C and D.
If both A and Bare "0", QN is off.
The base of QP goes positive and QP conducts.
This causes the emitter of QQ to be more positive than its grounded base.
QQ conducts.
The collector voltages for QP and QQ will be approximately +0. 9v and
+0.2v, respectively.
The difference in collector voltage is due to the positive charge
on the base of QP and the grounded base of QQ.
sate for this voltage difference.
respectively.
Transistor
RNC is smaller than RND to compen-
The emitters of QR and QS will be at +2. 4v and -4. Ov,
The base of QR is held at about +4. 9v by RNF and RNE.
QS is held at about -4. 9v by RNG and RNH.
Both QR and QS are off.
The base of
The voltage at
C and D is, therefore, dependent on any external voltage supply that may be present.
If either or both of the inputs go to "1 ", QN turns on.
base of QP turning QP off.
Current flows away from the
Transistor QQ is, therefore, off.
are then forward biased and conduct about 25. 0 ma of current.
Transistors QR and QS
CRND and CRNE are
forward biased and the output at C goes positive, while the output at D goes negative.
The voltage of either output is determined by the current flow through the external
load, but must be kept under 4. 9v.
7-24
70602500 A
E
I
:I
I
POW
F
JBB
:
39.4V
E
G
OV
37.4V
H
H VOLTAGE
OV
I+- 10"S EC
I
H CURRENT
-+t
F
40 M A
o
M A
10f'SEC
... 40V
RNE
(RPB)
IK
G
E
TP
CNB
J:: (C PA)
-=
H
2200PF
-20V
NOTES
I
VOLTAGE
AND
COMPONENT
Figure 7 -17.
70602500 A
VALUES
ARE
FOR
REFERENCE ONLY.
Erase Driver - JBB
7-25
TP
A
B
~
L:A
+ 2V
A OR B
I E:
OV
C
D
6V
TOTAL POTENTIAL
OF C AND D
IV
+20V
+20V
R NB
3.9K
RNJ
RNL
1.2K
1K
R NE
1.2 K
TP
RND
120
RNK
1.2 K
RNM
IK
- 20V
NOTE:
VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE ONLY.
5C Z 0
Figure 7 -18.
7-26
Line Transmitter - LAA
70602500 A
Oscillator - MAA
The MAA circuit (Figure 7 -19) produces an amplified, oscillating signal at a prescribed frequency.
The circuit description is divided into three parts: the D. C.
conditions throughout the circuit; the oscillator section of the circuit; and the amplifier circuit.
D. C. Conditions
CRNA, RNA, RNB and RND hold the base of QN at approximately +17 volts.
reverse biased by 3 volts and does not conduct.
CRNB is
The emitter of QN is held at about
+16v, producing a collector current in QN of about 16 rna.
The base-emitter voltage drop across QR holds the base of QR near +0. 7v.
current through RNH is then 5. 1 rna.
5. 1 ma must flow through RNJ.
QS must then be about +10v.
be near +10v.
The
With the base current of QR at a low level, the
The voltage at the junction of the emitters of QP and
To maintain this +10v, the collector voltage of QR must
The collector current of QR is, therefore, 5. 55 mao
Oscillator
Transistor QN acts as an emitter follower yielding a high current gain with nearly no
voltage loss.
CNB, CNC, and LNA form a resonant network.
Near the resonant
frequency, the signal voltage at the junction of LNA and CNB can be much greater than
the voltage through RNE in the feed-back portion of the circuit.
loop formed by QN, RNE, CNB and LNA is greater than 1.
oscillates.
The gain around the
The system, therefore,
When the signal at the base of QN exceeds 6v peak to peak, QN approaches
saturation, thereby limiting the amplitude of the oscillation.
Amplifier
Transistor QR is a common emitter amplifier.
to the bases of QP and QS.
a low impedance output.
70602500 A
The output of QR is directly connected
Transistors QP and QS are emitter followers that provide
Capacitor CNF isolates dc voltages from the load.
7-27
OUTPUT
roscl.
A
T?P
AT
A
AA
~
Ov
+20V
RND
RNK
1.8K
470
CRNA
6.2V
+
QP
RNB
470
eN F T P
.---.---+~I~~
RNA
IK
RNJ
1.8 K
-20V
NOTE: VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE
ONLY.
5CII
Figure 7 -19.
7-28
Oscillator - MAA
70602500 A
Waveform Generator - MBA
The MBA circuit (Figure 7-20) is a waveform generator whose output at C is normally
at "0" when both inputs A and B are at a "0".
When either or both of the inputs go to
a "1 ", a "1" pulse is created at output C for a predetermined length of time.
When both inputs are at "0" (ground), tr. QP will be turned on and QN will be turned off.
If the
difference "A minus B" is only slightly negative. QP will conduct more than QN. but
both will be on.
70602500
B
7 -42. 1
j.-IOO---..l.-IOO~
TP
I
NSEC
I
I
NSEC
,..----,
O.7V
A
OV
A-QD
A-++--1 Q FF 1---+-+- B
CUTOFF PO IN T
r-CONTROLLED BY RNL
B
,...-----"""'\- - -,
0.75V
OV
VOl. TAG E 5 UPPLY
RNK
+20V
IK
+20V
I
RNL
5K
+20V
eND
0.01
fLF
RNG
2.2 K
TP
-RNM
470
B
NOTE: VOLTAGE AND COM PONENT VALU ES
ARE FOR REFERENCE ONLY
sel2a
Figure 7-28.
70602500 B
Quantizing Detector - QFF
7-43
TP
A
B
~
R:A
:J
I
C
A
B
OV
D
B
TP
A
HI
~
:1~:A I
LO
OV
3.5V
cao
0
ov
-
r
TP
- -
-------- - I
+20V
I
®
RNN
4.71<
C
..J
- +20V
- --
r
RNP
It(
RNM
820
I
I
t
I
CRNB
___ ..J
L
I
_.J~
NOTES:
I.
VOLTAGE AND
®
PORTION
@
CR NC
COMPONENT
WITHIN
USE DON
VALUES
DOTTED LlNE
RB A
ARE
FOR
IS USED FOR
REFERENCE ONLY.
RAA
ONLY.
0 N L Y.
5 CIO
Figure 7-29.
7-44
CRNC
Line Receiver - RAA
70602500 A
The base of QR, therefore, becomes more negative than the base of QQ.
QR turns on, driving its collector and the bases of QS and QT positive.
Transistor
Transistors
QS and QT turn on, conducting current from the +20v supply through RNN and RNS,
respectively, to ground.
The output at C and D is near Ov or a "0".
If input A is at least +0. 6v more positive than input B (A minus B is greater than or
equal to +0. 6v), QN turns on and QP turns off.
than the base of QR.
The base of QQ is then more negative
Transistor QQ turns on conducting current from the +20v supply,
through RNK and RNL to ground.
current to their bases.
Transistors QS and QT are turned off as there is no
Current is then allowed to flow from the +20v supply, through
the load resistors to outputs C and D.
The value of the output voltage is tempered by
the resistors RNP and RNU to ground, and is held at a "1" level.
The output is a "1".
Line Receiver - RBA
The operation of the RBA circuit (Figure 7-29) is identical to the RAA circuit, except
that output C and its related circuitry are omitted.
Output D remains intact (with the
addition of diode CRNC) and functions the same as output D in the RAA circuit.
For a
detailed discussion of the RBA circuit, refer to the discussion of the RAA circuit.
Switch Receiver - RDA
Switch Receiver RDA (Figure 7-30) produces a "1" (+3v) output at C when the grounded
switch connected to input A is open.
When the switch is closed a "0" (Ov) is felt at
output C.
A switch to ground is connected to input A.
approaches +6v and QN is shut off.
When this switch is open, capacitor CNA
Transistor QP is, therefore, on and conducts
current to the base of QQ through resistor RNF.
base of QR to ground.
Transistor QQ turns on, driving the
Transistor QR is off, which allows current to flow from the +6v
supply through RNK to output C.
The output is a positive voltage, or a "1 ".
When the switch is closed, the voltage across CNA rapidly increases through RNA and
the switch to ground because of the short time constant of RNA and CN A.
bounce on the switch will increase the discharge time.
decreases, QN begins to turn on.
As the voltage across CNA
As QN conducts current to the base of QP, the
forward bias on QP is decreased and QP begins to turn off.
70602500 A
Any contact
As QR turns off, the
7-45
current through RND decreases due to the higher lead resistance (RNE) of QN compared
with QP (RNF).
across RND.
completion.
The current drop through RND causes a decrease in the voltage drop
The bias on QN is, therefore, increased.
Transistor QP is shut off.
causing QQ to shut off.
QR.
The cycle goes rapidly to
With QP off, the base of QQ is near ground,
This allows the +6v supply to flow through RNH to the base of
Transistor QR, therefore, conducts current away from output C and the output is
near ground or "0".
A
A
I
9
I
,
;
LSA
I
SWITCH
INPUT A
~OPE.N
CLOSED
8
I
RCA
LSA
I
3V
8
341£ SEC
C
RDA
~
IE-
66".SEC
4
OV
~
3V
C
OV
+6V
- - - - --,
r
R NH
2.7K
C
B
+
1:: CI"F
NA
QR
RNL
2.7K
~ RNJ
2.7K
QQ
I®
@
L
-
NOTES:
I.
VOLTAGE
AND COMPONENT VALUES
(&)
DOT.TED CONNECTION
~
C I R CU I T
WIT H I N
ARE FOR REfE RENCE
A NO RES ISTOR
B R 0 KEN
LIN E BOX
RN J
ARE
FO R
I SAD DE D FOR
fit
--
-
ON LY.
CA
ON LY.
R0A
0 N L Y.
!5 C I I
Figure 7 -30.
7-46
Switch Receiver - RDA, RCA
70602500 A
..J
When the switch is opened again. CNA charges slowly to +6v due to the long time constant of RNB and CNA.
Any contact bounce on the switch will hold CNA well below the
switching level of QN until the bouncing ceases.
QN begins to turn off.
of QN.
As the voltage across CNA increases.
Transistor QP begins to conduct current away from the emitter
Transistor QP turns on rapidly because of this positive feedback.
The output
then returns to "1".
Switch Receiver - RCA
The operation of the RCA circuit is similar to the RDA circuit. except that transistor
QR is omitted and the output is taken directly from the collector of QQ at B
(Figure 7-30).
The output is. therefore. opposite from the output of the RDA circuit
under the same switch condition.
When the switch is open. the output at B is a "0".
When the switch is closed. the output at B is a "1".
For a detailed discussion of this
circuit refer to the RDA circuit description.
Line Receiver - RFA
The RFA circuit (Figure 7-31) provides a non-standard "0" output at C when input A
is at least O. 6v more negative than input B.
Diode CRNA holds the threshold at 0.6v.
Under all other input conditions the output will be a non-standard "I".
If the differential input (A-B) is greater than O. 6v. transistor QP turns on and QN
turns off.
This drives the base of transistor QR more positive than the base of QQ.
Transistor QR conducts current from the -20v supply. through RNK to ground.
The
output at C is near Ov.
If the differential input (A-B) is less than O. 6v. QN turns on and QP turns off.
base of QQ goes more positive than the base of QR.
The
Transistor QQ conducts and a
negative voltage is felt at output C.
Since a "1" is defined in MDD logic as the most positive voltage. the Ov output in the
first case is interpreted as a non-standard level "1 ".
The negative voltage output in
the second case is. therefore. a non- standard level" 0".
The receiver is self -terminated with 56 ohms to ground on each line.
70602500 A
7-47
>
A-B
0.6\1
0
A
B
:d
2;e
C CURRENT
R
o
, C
MA
MA
;
RFA
c
R NC
220
A
RNA
56
+20\1
RNB
156
RND
220
B
QR
NOTE: VOLTAGE
AND COMPONENT
VALUES
ARE FOR
REFERENCE
ONLY.
IC4.
Figure 7-31.
Line Receiver - RFA
Delay - UA-, UBA
The capacitive delay circuit (Figure 7 -32) delays a "1" input at A for a specified period
of time before providing a "1" output at B.
The delay time for a "0" pulse is negligible.
The delay circuit consists of a capacitor connected to ground.
Assume that a "0" (ground) enters at A.
discharged.
If the capacitor is discharged, it remains
The output is an immediate "0".
If the capacitor is charged when the
signal enters, it discharges almost instantaneously.
The "0" appears at output B with
no noticeable delay.
7-48
"a"
70602500 A
_A_ _
~I ~:
A
:1. ___
B_
B
A
B
0
0
I
I-
Figure 7-32.
CNA
5C 12
Delay -
VA-, VBA
If a "1" (+3. Ov) enters at A, and the capacitor is discharged, the capacitor must first
charge to a minimum "1" voltage (typically +0. 7v) before the "1" appears at output B.
The time necessary to charge the capacitor to this minimum voltage is the delay time
of the circuit.
The charge time is dependent on the value of the capacitor, the value
of an external resistor between the source voltage and the delay circuit, and the
minimum voltage required to produce a "1" response.
Delay times for capacitive delays used in the MDD unit are as follows:
Delay
70602500 A
VAA
VAB
VAC
UAD
VAE
VAF
VAG
VAL
VAM
VAN
UBA
Time
0.3 J-Isec
0.4 J-Isec
O. 2 psec
1 J-Isec
500 psec
2 psec
0.1 psec
'10 J-Isec
8 psec
5 psec
15 J-Isec
7-49
Delay: Circuit - DCA
The DCA circuit (Figure 7 -33) provides a delayed "0" output signal at B a set time
after a "0" is felt at input A.
A" 1" signal is not delayed.
The operation of the DCA circuit is similar to the UDA circuit except the final transistor QU (Figure 7-33) is omitted for the DCA circuit.
This allows a "0" output when
transistor QT (Figure 7-33) conducts, and a "1" output when QT is turned off.
For a
detailed discussion of this circuit, refer to the UDA circuit.
The time delay is still dependent upon the values of RNC and CNA.
The delay for a
DCA circuit will be slightly less than the delay for an identical UDA circuit due to the
extra time taken for transistor QU to turn on in the UDA circuit.
Delay Circuit - UCB
The UCB circuit is identical in operation to the UCA circuit (Figure 7 -33).
The values
of RNC and CNA are changed to produce a different time delay.
Delay Circuit - UCC
The UCC circuit is identical in operation to the UCA circuit (Figure 7-33).
of CNA and several resistors are changed.
The values
In addition, a la-ohm resistor is added in
series with the collector of QN to increase the discharge time of CNA when QN is
turned on.
Delay Circuit - UCD
The UCD circuit is identical in operation to the UCA circuit (Figure 7 -33).
of CNA and several resistors are changed.
The values
In addition, resistors RNA and RNB and
their connections are omitted, CRNA and CRNB are replaced by a lK resistor, and a
47 -ohm resistor is added in series with the collector of QN to increase the discharge
time of CNA.
Delay Circuit - UCE
The UCE circuit is identical in operation to the U.CA circuit (Figure 7-33). The values
of CNA, RNC and RNH are changed. In addition, a 47 -ohm resistor is added in series
with the collector of QN to increase the discharge time of CNA. The feedback to the
base of QR through RNL is omitted. Resistor RNG is replaced by a 3. 6v Zener diode
to limit the voltage on the base of QR to +3. 6v.
7-50
70602500 A
3V
A
P
9
A
OV
~
B
UTD
250",SEC
~
3V
UC_
B
OV
t6V
RNA
RNC
1.2 K
2.7K
RND
2.2 K
RNH
RNM
1.5K
1.2K
B
QN
®
+
aT
CNA
O.I,...F
RNI
RNG
RNN
IK
2.7K
1.2 K
NOTES'
I. VOLTAGE
®
CNA
AND COMPONENT VALUES ARE FOR
IS AN
ELECTROLYTIC CAPACITOR FOR
REFERENCE ONLY.
UCA
AND UCE
CIRCUITS
ONLY.
5ce
Figure 7-33.
70602500 A
Delay Circuit - UCA, UCB, UCC, UCD, UCE
7-51
Delay - UDA
The UDA circuit (Figure 7-34) provides a "1" output at B a set length of time after a
"0" enters at input A.
There is no delay for a "1" input signal.
The output is an
immediate "0".
When a "1" appears at input A, QN conducts current from the +6v supply, through
RNC to ground.
The base of QP, therefore, approaches ground.
The base of QR is
held at approximately +3. 8v by the voltage dividing action of RNG and RNJ.
emitters of QP and QR are, therefore, held at approximately +3 volts.
The base and emitter of QS remain at +6 volts, so QS is off.
QT are both at ground.
Transistor QT is off.
The
QP is off.
The base and emitter of
The collector of QT goes to approxi-
mately +2. 4v due to the voltage dividing network formed by RNM, RNN and the baseemitter voltage drop across QU.
Transistor QU is turned on and the output is held
near ground, or a "0".
When a "0" (ground) appears at input A, QN turns off.
begin charging from the +6v supply through RNC.
This allows capacitor CNA to
When the voltage at the base of QP
reaches approximately +3. 8v, QP starts to conduct, drawing current away from the
base of QS.
Transistor QS starts to turn on, forward biasing the base of QT.
sistor QT starts conducting.
As the collector of QT approaches ground, the voltage
on the base of QR is drawn off through RNH.
This decreases the voltage on the
emitters of QR and QP and drives QP to saturation.
are also driven toward saturation.
ground.
Tran-
With QP saturated, QS and QT
When QT conducts, the base of QN goes toward
Transistor QU is cut off and the output voltage rises to a "1" level.
The time delay is determined by the values of RNC and CNA.
Delay - UDB
The operation of the UDB circuit is identical to that of the UDA except the size of
capacitor CNA (Figure 7-34) differs to cause a delay of 115 ±25 ms.
7-52
70602500 A
A
3V
A
I
9
OV
~300~SEC~
a
UTD
UOA
3V
a
RNC
RNA
1.2K
RHO
2.2K
22K
ov
RNG
RNM
I.SK
1.2 K
B
QN
+
CNA
QT
IS~F
RNa
RNJ
IK
2.7K
NOTE: VOLTAGE
AND COMPONENT
VALUES ARE FOR REFERENCE
ONLY.
5C7
Figure 7-34.
70602500 A
Delay - UDA, UDB
7-53
Undirectional Time Delay - UEA
The UEA circuit (Figure 7-35) provides a O. I-J.lsec delay between the time that a -3. 5v
signal appears at A and the time that transistor QP turns off.
Output at B is either
ground or an open circuit.
When input A is near ground, QN is off.
Transistor QP is on.
When input A goes to -3. 5v, capacitor CNA begins charging.
of QN is sufficiently negative to turn QN on.
The output is ground.
After O. 1 fJsec the base
Transistor QP turns off.
The output is
an open circuit.
OV
A
A
,
I
UTD
I
- 3.5V
-+t
B
I
~O.IIL SEC
...-----4 -
OPE N -
t - I- -
OV
B
U E A_I-- - , . , . . -
-20 V
B
RNA
22K
A
CRNA
T
NOTE: VOLTAGE
CNA
220PF
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE
ONLY.
II C 44
Figure 7-35.
7-54
Undirectional Time Delay - UEA
70602500 A
And - VAA
The VAA circuit (Figure 7-36) consists of a single NPN transistor. When all inputs
connected to A are at a "1" level, the output at B will be a "0". Any "0" appearing at
A will result in a "1" output at B.
When the input to A is a "0", A is held at about +0. 9v.
This input is not sufficient to
forward bias diodes CRNA and CRNB or transistor QN.
output at B is a "1".
Transistor QN is off.
The
When the input to A is a "1", A rises to about +2. 1v. This voltage forward biases
CRNA, CRNB and QN. Transistor QN turns on, conducting current a way from B to
ground. Output B is left at about +0. 9v, or a "0".
Diodes CRNA and CRNB provide noise immunity up to 1. 4v. Resistor RNB connected
to ground turns off QN when the positive voltage is removed from A.
r----'
Vee
I
I
1
I
I I
A
I
1
L _____
-----,1
r----- Vee
I
I
I I
+6V
+0.9v ("0")
~ OV
____ _ .11
I
8
I
+2.lv(N 1")
I
I
IL ____ .JI
DOTTED LINES
AT A OR B
+2.1
V
(",")
+ 0.9 v (·0'·)
=SOv
FOR CIRCUIT WITHOUT LOAD
NOTEI VOLTAGE AND COMPONENT VALUES
ARt
FOR
REFERENCE ONLY.
5 C 21
Figure 7-36.
70602500 A
And - VAA
7-55
And - VAB
The V AB circuit (Figure 7 -3 7) consists of two silicon peripheral logic inverters whose
outputs share a common load resistor, RNE.
(ground), the output at C will be a "1" (+3v).
the output at C will be a "0".
When both inputs A and Bare "0"
If either or both of the inputs are a "1",
This is an AND gate for zeroes, or a NAND function.
When both A and B are at ground, QN and QP are off.
the +20v source through RNE.
logical "1 ".
The output at C is supplied from
The output is a positive voltage, representing a non-
If input A experiences a positive voltage while B is at ground, QP turns
on and conducts current from the +20v supply through RNE to ground.
The "0" on B
has no effect, as all the supply voltage is tapped to ground.
The output at C is ground,
or a "0".
The output is "0".
The situation is similar if A is "0" and B is "1".
both A and B have positive voltage applied to them, QN and QP both conduct.
If
The
output is "0".
Capacitors CNA and CNB provide a one's delay on input B and output C, respectively.
They also maintain a noise barrier to isolate the circuit from stray pulses on the lines.
And / Or (Single Input) - V AC! V JW
The single input AND/OR or silicon peripheral logic (SPL) inverter (Figure 7-38)
provides an inversion from input A to output B: A "1" on A produces a "0" on B, or
a "0" on A produces a "1" on B.
The inverter's output may be connected to the output
of other inverters to form NAND functions or NOR functions.
The SPL inverter is a single NPN silicon transistor connected as a common emitter
amplifier.
When A is a "0" (between Ov and +0. 3v) the transistor is off.
current to flow from the +20v supply, through RNB to output B.
The output is a "1".
When input A is a "1" (between +0. 7v and +3. Ov) the transistor turns on.
conducts current from the +20v source, through RNB to ground.
This allows
The transistor
This leaves output B
near ground, or a "0".
Since the base-emitter threshold for a silicon transistor is approximately +0. 7v, the
circuit ignores up to O. 5v of transient noise.
7-56
70602500 A
20V
A
OV
j
B
3V
OV
20V
A
I
•
I
dv~·1
C
,
OV
, C
7.4 MA
C
OMA
CURRENT
+20V
RNC
6.aK
TP
C
r
OP
CNB
IOOOPF
.::r::
-
ON
-20V
NOTE: VOLTAGE
AND COMPONENT VALUES ARE FOR
REFERENCE ONLY.
5CI4
Figure 7 - 37.
70602500 A
And - V AB
7-57
+4V
A
A
A
,
I
,
I.
9 I
1v:w I
A
OV
B
VAC
+20V
B
ov
B
+20V
B
NOTES:
I.
VOLTAGE AND COMPONENT VALUES
(i) DOT TED LI NE
TO - 20 V AND
ARE
RES 1 S TOR
FOR
RN B
REFERENCE
FOR
ONLY.
VoJ WON L Y.
5C 13
Figure 7-38.
And/Or (Single Input) - VAC, VJW
If the circuit drives just one other transistor, the output may be connected directly to
the base of the driven transistor.
For a fan-out of 2 or more, a base isolation re-
sistor is required for each driven transistor.
This resistor ensures that the base
drive provided to each of the driven transistors will be nearly independent of differences in base-emitter voltages.
For a fan-out of 2 the collector load resistor must
be reduced by one-half its value for driving one transistor to provide for the additional
voltage drop across the isolation resistors.
Switching time for an inverter with a fan-out of 1 is typically 15 nsec.
7-58
70602500 A
Power Driver - V.TK
The VJK circuit (Figure 7-39) is similar to the V-IS circuit with the addition of
capacitor CNB and two outputs.
ramp output.
CNB slows the switching time of QN and p)'ovidcs a
Output B connects to the center tap of the head.
Output C contains a
10K resistor and is connected to a voltage supply in a fault detect circuit.
If two heads
are selected the effective resistance falls to 5K (two 10K resistors in parallel).
increase in current causes a Fault signal.
The
Output lJ contains a diode that isolates each
Write Gate.
3V
OV
I,C,D
- - - - OPEN
OV
tVJK)
-1(::. p,
I
_1._ _
+
+40V
I
OV
tV" S)
•
RNC
2.2 K
B
40V . - -J\IV\r - ...- - - - - - - - - - - - {
@
RNC
10K
C
-0
-AtN'v-
+20V
D
CRNC
--if- --
-0
QN
RNI
22K
NOTES'
-20V
I. VOLTA.E AND CO .... ONENT VALUES
(!)
USED fOR
(!)
USED fOR V ... ONLY.
V.lK ONLY.
Figure 7-30.
70602500 A
ARE
FOR
REfERENCE ONLY.
ICI4
Power Dr'iver' - Y.JK
7-5!J
Power Driver - V,IL
The V,IL circuit (Figure 7-40) is a gate used to bias an analog gate.
If +20v appears at A. QN turns on.
off.
The base of QP goes to ground.
Capacitor CNA charges through RNIJ to +20v.
A +0. 2v signal at A turns QN off.
clamps at +0. 7v.
A
,
I
I
Output at B is a ramp to +20v.
When QP turns on, the collector voltage of QN
CNA discharges rapidly through QP.
:~~ I
,
I
Output B drops to ground.
+ 20V
A
B
Transistor QP is
OV
+
B
20V
OV
+20V
RNA
6.8 K
A
C RNA
CRNB
CRNC
RNB
22K
NOTE
I
VOLTAGE
-20 V
AND COMPONENT
VALUES
ARE FOR REFERENCE
ONLY.
eC11
FigUl'C 7-40.
7-60
Power Drivcr - \"JL
70602500 A
And - VJM
The V JM circuit (Figure 7-41) gates a particular receiver into operation.
at A results in an "open" enable signal to the receiver.
A "0" input
A "I" input at A disable s the
receiver.
A "0" (Ov) input forward biases diode CRNA.
The +20v supply current is drawn through
RNA and CRNA, leaving the base of QN reverse biased.
Transistor QN is off.
Output
is held at -0. 7v by the next stage.
A "I" input turns QN on.
The output goes to ground.
No receiver signal can pass into
the receiver.
+3V
A
9
A
A
VJM
I
,
I
ov
~Td
B
l+-
+O.SV
B
-0.7V
+20V
-20V
NOTE: VOLTAGE AND COMPONENT
VALUES
ARE FOR
REFERENCE ONLY.
5 C2S
Figure 7-41.
70602500 A
And - VJM
7-61
Or - VJN
The V IN circuit (Figure 7 -42) is a NAND circuit that inverts the input signal.
is connected to the output of a receiver and to a gating circuit.
off, the base of QN is grounded.
Input A
If the Write gate is
The circuit is disabled.
When the write gate is on, QN turns on and the receiver inputs a "0".
turns on further and goes into saturation.
Transistor QN
Output voltage at B is approximately -0. 2v.
When the receiver inputs a "1", QN comes out of saturation.
Output at B is approxi-
mately -3. 5v.
Whenever the write gate is on, QN is on to some degree.
Only when the write gate is
off is the base of QN at ground and QN off.
TP
A
}
I:J: pJ
I
OV
A
- O. 7Y
B
o
V
B
- 3.5 V
+20Y
•
~
A
RXA@
~15K
TP
RNB
2.2 K
NOTES:
I.
Ii'
\J
- 20V
VOLTAGE AND COMPONENT
RESISTOR AND POWER
VALUES
FOR
SUPPLY EXTERNAL
RE FERENCE
ONLY.
TO YJN.
Be4!
Figure 7 -42.
7-62
ARE
Or - VJN
70602500 A
And - VJP
The V JP circuit (Figure 7 -43) is normally used as the input circuit to a toggle flipflop.
It ties two receiver outputs to a single-ended output.
Capacitor CNA is used to
reduce the input impedance for faster switching.
When input A is near ground the base of QN is at approximately +0. 9v.
is off.
Transistor QN
Output at B approaches -20v, but is clamped at -3. Bv by a Zener diode in the
following circuit.
When input A is -3. 5v, QN turns on.
Output drops to approximately -0. 2v.
Input to A is short (100 nsec), negative, data pulses.
Output B is also short pulses.
OV
A
- 3. !5 V
,
8
OV
8
-3.8 V
+ 20V
RNC
22K
RNA
IK
A
8
CNA
22PF
RNB
6.8K
- 20V
-20V
NOTE: VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE
ONLY.
Be 41
Figure 7-43.
70602500 A
And - V.JP
7-63
Power Driver - V JR
The V.JH circuit (Figure 7-44) is a +40v switch.
output B.
A "1" on input A produces +40v at
A "0" on input A stops current flow.
A "1" input turns QN on.
Transistor QN conducts current from the +40v supply,
causing a voltage drop across resistor RNB.
This voltage drop turns on QP.
Output
B is at +40v.
A "0" input turns QN off.
are at equal voltage.
Since current no longer flows, the emitter and base of QP
Transistor QP is off.
Output B goes to ground.
+3V
A
A
POW
VJR
,
;
OV
--I Td
B
J.
+40V
B
OV
RNC
2.2 K
A
CRNA
CNA
1:: 1000 PF
RNB
IK
CRNB
RNA
IIC
NOTE:
VOLTAGE AND COMPONENT VALUES
ARE FOR REFERENCE ONLY.
ICla
Figure 7-44.
7-64
Power Dr'iver .. VJR
70602500 A
Or - VJS
The V JS circuit (Figure 7 -39) is a standard inverter with a capacitor delay at the input.
A "1" at input A pulls the output at B to ground.
A "0" produces a +40v output.
Or - VJT
The V JT Circuit (Figure 7 -45) is a gate to the WBB toggle flip-flop.
produces a ground at B, which keeps the flip-flop off.
A" 1" input at A
A "0" input at A produces a
-3.5v output at B, which releases the flip-flop and presets it in a given state.
When a "0" is applied to input A, the base of QN goes to ground.
The base of QP is clamped at +0. 6v by diode CRNC.
Transistor QN is off.
Transistor QP is off.
Output B
is -3. 5v derived from the voltage dividing network of RNF and RNG.
+ 3V
A
OV
~Td ~
I::T F
A
,
I
B
OV
I
- 3.SV
I
-20Y
+20Y
RNI
R NE
22K +20Y
I.IK
I
RNA
6.8 K
RNG
IK
A
.T
CNA
IOOOPF
NOTE: VOLTAGE
AND COM PONENT VALUES
ARE FOR REFERENCE
ONL Y.
Ie ...
Figure 7-45.
70602500 A
Or - VJT
7-65
When A goes to a "1 ", capacitor CNA charges.
positive enough to turn QN on.
Transistor QP turns on.
After a delay, the base of QN is
The base of QP goes negative through resistor RNE.
The output at B drops to ground.
And - V.IU, V JV
The V JU and V JV circuits (Figure 7 -46) are functionally identical.
standard inverter circuit with a capacitive filter input.
They consist of a
The capacitor also presents
a delay.
A "1" on input A reverse biases diode CRNA.
Capacitor CNA charges through RNA
until it is clamped at about 3 diode voltages (approximately 2. 1v).
QN turns on.
Output B falls to ground.
If input A is a "0", CNA discharges through CRNA.
Transistor QN turns off.
Output
B rises to a "1" level due to the clamping by a Zener diode.
And/Or - VJW
Refer to circuit description for circuit type 'lAC.
Flip- Flop - WBB
The WBB circuit (Figure 7-47) is a toggle flip-flop with gate and data inputs.
Input B holds both transistors off by grounding the bases when the circuit is off.
When
a write operation is to be pe t'formed, the base of QP is released while QN is still
grounded by input C.
This sets an initial condition for the flip-flop:
QP is on, QN is
off.
After the nip-flop is pre-set it is toggled through input A by a series of negative data
pulses.
The leading edge of the negative data pulse begins charging capacitor CNB.
Diodc eRN\) becomes forward biased.
QP is on.
Output E is at ground.
of -3. 6v across Zener diode CRNK keeps CRNN reverse biased.
A voltage
CRNK and CRNM
clamp the output of QN at -3. 8v.
7-66
70602500 A
,.---- +4'1
A
V
+4'1
-A-~9 ~ Ul'"___
B
B_
V
o
0'1
+ 20'1
CRYA
B
-20'1
NOTES;
I.
®
@
VOLTAGE
AND
COMPONENT VALUES
RESISTOR
EXTERNAL TO VJV.
D I 0 DEE X T ERN A L
RYA
ARE
FOR
BECOMES
T 0 V J 'It B E COM ESC R N E
REFERENCE ONLY.
RNC
FOR
FOR
VJU.
VJU •
les.
Figure 7-46.
And - V.TU. V.JV
The trailing edge of the data pulse results in a positive pulse to the base of QP.
sistor QP turns off.
Output E goes toward -4v.
Tran-
Both sides of CNA are at ground.
Therefore. CRNC and CRNF are forward biased by the -20v source through HNC.
base of QN goes negative.
The
Transistor QN turns on and Output)) drops to ground.
Diodes CRNM and CRNJ are now reverse biased.
Since the collector of QP is more
negative than the voltage across Zener diode CRNK (-3. 6v). CRNN is forward biased.
This clamps the voltage at output E at approximately -3. 8v.
70602500 A
7-67
OV
B
-3.5V
C
-
-
OPEN
" I"
-
-
"0"
- -
- - -
"I"
" 0"
OV
OV
A
- 3.8V
TP
OV
0
- 3.8V
A
OV
E
- 3.8V
B
C
RNO
8.2 K
-20V
RNE
1.5 K
CRNH
RNF
15K
+ 20V
TP
CRNL
0
CRNC
A
RNA
22K
CRNM
CNA
100PF
I
RNG
2.2 K
CRNI
-20V
CRNN
CNI
IOOPF
CRNF
C
C RNJ
R NH
1.5K
- 20V
CRNP
RNJ
15K
TP
CRND
NOTEI VOLTAGE
AND COMPONENT
VALUES
ARE FOR REFERENCE
ONLY.
le41
F'i gurc 7 - 4 7 •
7-68
Flip- Flop - WEB
70602500 A
The leading edge of the next negative pulse charges CNA and discharges CNB since
both sides of CNB are at about -3. 8v.
The flip-flop will toggle on the ground- going
edge of the pulse in the same manner as described for the first pulse.
Toggle Flip- Flop - WBC
Inputs to A and B of the WBe flip-flop (Figure 7 -48) are either a positive pulse or
ground.
If A has positive pulse, then B is at ground.
positive pulse.
If A is at ground then B has a
If input A receives a positive pulse, output
e
will be at ground and
output D will be a constant positive voltage. A positive pulse at B will toggle the flipflop. e will then be a positive voltage and 1J will be at ground.
+ 4v
Ov
A
TP
+ 4v
A
C
S
Ow
B
+ 4v
WBC
Ow
C
D
B
+4~
D
+20V
Ow
TP
TP
C
QQ
RNB
2.2 K
D
QP
NOTE: VOLTAGE AND COMPONENT VALUES
ARE
FOR REFERENCE
ONLY.
ICII
Figure 7 -48.
70602500 A
Toggle Flip- Flop - WBe
7-69
A positive pulse to input A turns on transistor QN, which drives the base of QR to
ground.
Transistor QR is turned off.
Input B is at ground and QP is off.
QQ is, therefore, positive and QQ turns on.
puts a ground on output C.
The base of
This latches the base of QR at ground and
With QP off and QR latched off, current flows from the +20v
source through RNB to output D.
When a positive pulse is felt at B, QP turns on.
turning QQ off.
positive.
This drives the base of QQ to ground,
Input A is at ground and QN is off.
The base of QR is, therefore,
Transistor QR conducts, latching the base of QQ at ground and driving out-
put)) to ground.
With QN and QQ off, output C is positive.
Pulse Shaper - XAA
The input to A and B (Figure 7 -49) of the XAA circuit is a O. 7v balanced square wave
centered around a positive voltage.
Each time the inputs change polarity a short
negative pulse is formed at output C.
The square wave input is sufficient to alternately turn QN and QQ on and off.
of about 5. 6 ma is alternately switched between QN and QQ.
positive than input B, QN turns off.
The collector of QN rises to about -8.7v.
the base of QR.
of the pulse.
When input A is more
The voltage at the collector of QN is about - 20v.
The voltage at the junction of RNG and RNJ is -1. 6v.
turns on.
A current
When the inputs switch. QN
CNA forms a positive pulse to
The positive pulse turns QR off, QT on and QV off for the duration
The amplitude of the pulse is limited by CRNB.
is about 100 nsec.
Charging time for CNA
When the inputs switch again, QQ turns on and QN turns off.
forms a positive pulse which turns QV off again for the duration of the pulse.
put at C is ground until QV is turned off.
CNB
The out-
During the short time that Q\' is off. a
negative pulse appears at output C.
Diodes eRND and CRNE prevent saturation of QR and QS.
(~S
As the collectors of QR and
approach ground, the negative voltage at the left ends of RNJ and RNK is limited to
the sum of the voltage drops across QR and CRNlJ or QS and CRNE, respectively.
Diode C RN F prevents
7-70
(~V
from saturating.
70602500 A
0.,
A
- 4 .,
TP
A
8
:
SS
XAA
I
,,? C
8
OV
- 4v
C
Ov
-4v
CNA
47PF
TP
CRND
RNP
OR
ON
II<
RNG
8.21<
C
RNB
IK
+20'1
CRNB
RNO
3.3 K
CRNA
-20V
CRNC
OS
RNL
101<
....- -.....- ....._I\.IV'\_. .
e-----4~--fl---_4-._-
RNC
-
20 V
CNB
47PF
II<
-20V
NOTE: VOLTAGE
AND COMPONENT VALUES ARE
FOR REFERENCE
ONLY.
5C II
Figure 7 -49.
70602500 A
Pulse Shaper - XAA
7-71
Pulse Shape r - XAB
The input at A of the XAB circuit (Figure 7 - 50) is a balanced square wave between Ov
and +4v.
The output at B is normally positive, but drops to ground for a short time at
the leading edge of the ground portion of the input wave.
During the positive portion of the input wave, transistors QN and QP are on.
leaves the bases of QQ and QR near ground.
Transistors QQ and QR are off.
This
The
output at B is a positive voltage supplied through resistor RNE.
When the input wave goes to ground, transistors QN and QP turn off.
the base-emitter junction of QR is forward biased.
output at B drops to near ground.
With QP off,
Transistor QR conducts and the
With QN off, capacitor CNA charges toward +20v.
When the charge on CNA reaches a level sufficient to turn on QQ, the base of QR again
drops to ground.
Transistor QR turns off.
The output at B returns to the positive
level.
Pulse Shaper - XAC
The XAC circuit (Figure 7-51) produces a 100-nsec ground pulse at output C when the
inputs at A and B change state.
The output is normally positive.
Input A is connected
to the set side of a flip-flop and input B is connected to the clear side.
When the flip-flop is clear, the base of QR is positive.
Transistor qR conducts 10 rna
of current from the - 20v supply through RND, RNC, QS, QH and RNB.
of QN is at +20v and the collector of QR is near +13v.
The collector
Transistors QT and QU are on
and QV and QW are off.
When the flip-flop sets, QR turns off and QN turns on.
+13v, which drives the base of QT to about -Bv.
QV positive.
The collector of QN goes to
This turns QT off, driving the base of
QV turns on and the output at C goes to ground.
through RNE with a time constant of 135 nsec.
of QT has risen to +0. 7v and QT turns on.
Capacitor CNA charges
After 100 nsec the voltage at the base
This drives the base of QV to ground.
QV
turns off and the output at C returns to a positive level.
When the flip-flop clears again, a 100-nsec ground pulse is formed at C by QH, CNB,
QU and QW.
7-72
70602500 A
+
A
~
A
,•
I I,
SS
XAB
I
40v
Ov
8
+ 20 v
B
OV
+20Y
+20Y
+20Y
RNO
2.2 K
QQ
NOTE:
YOLTAGE AND COMPONENT VALUES
ARE
FOR REFERENCE ONLY.
ecsi
Figure 7 - 50.
70602500 A
Pulse Shape r - XAB
7-73
+4v
A
Ov
+4 v
B
GATE
Ov
+20 v
C
Ov
RNN
2.2K
C
+20V
+20Y
QV
C NA
47 PF
RNE
2.87 K
+20Y
RNH
680
RNM
6.8K
RNK
1.2K
RNI
RNF
2.87K
680
QU
+20V
RNL
-20Y
6.8K
GATE
+20V
NOTEI YOLTAGE AND COMPONENT VALUES ARE
FOR REFERENCE
ONLY.
5 C6
Figure 7 - 51.
7-74
Pulse Shaper - XAC
70602500 A
HEAD AND DISK PACK REPLACEMENT CRITERIA
HEAD REPLACEMENT CRITERIA
Heads of the MOO have been designed so that they should not need replacement if given
proper preventive maintenance and care.
If a head requires replacement refer to the
Preface of this manual for the publication containing the Maintenance section.
to that section for Head / Arm Replacement procedure.
Refer
A head is defective and needs
replacing if any of the following conditions exist:
1.
Consistent oxide buildup on head, indicating repeated head / disk impact.
2.
Appreciable oxide buildup located primarily on the edge of the ferrite insert,
indicating a warped head.
3.
Oxide or wear over 1/2 of the head face surface.
4.
A head which is scratched over 1/2 of the head face surface.
5.
Concentric scratches on disk surface.
6.
Audible ping indicating that the head is hitting the disk surface.
Inspect the head for imbedded particles.
DISK PACK REPLACEMENT CRITERIA
The disk pack is designed to last the lifetime of the equipment.
Replacement of the
disk pack is required only if excessive runout (see Disk Pack Runout Check) is
encountered or physical damage to the pack results in the loss of recording ability.
A disk pack is defective and needs replacement if any of the following conditions exist:
1.
Dalnage to the disk pack resulting in a bent or broken disk.
If a disk is bent
perform Disk Pack Runout Check procedure.
2.
Gouged or scored disk surface causing the loss of stored data.
:L
Imbedded particles in a disk surface that cannot be removed by cleaning and
are causing damage to the heads.
70602500 A
7-75
Disk Pack Runout Check
This procedure determines whether a bent disk pack may remain in use.
If the disk
pack fails to meet the requirements of the procedure, it should be returned to the
manufacturer for reconditioning.
1.
Extend the upper deck drawer forward.
2.
Release four half-turn fasteners securing right-hand shroud side cover.
Set
the side cover aside.
3.
Install the disk pack to be checked on the spindle of the upper deck.
4.
Grasp the pack cleaning brushes, override the shaft detent mechanism. and
rotate the b rushes into the disk pack.
5.
Place the disk pack runout gage (PIN 84357600) base against the underside of
the upper deck shield and set the switch on the base of the gage to ON
(Figure 7 - 52).
6.
Turn the bezel of the dial indicator to indicate zero.
Orient the dial indicator
so that the plastic tip is not only contacting a disk surface but is deflected for
an indication of approximately O. 020 inch.
position.
Tighten dial indicator in this
Turn the bezel to set the dial indicator to zero.
NOTE
A mirror is required to observe dial indicator when
some disk surfaces are checked.
7.
lVlanually and slowly rotate the disk pack one full revolution while carefully
observing the dial indicator.
The sum of the deviations (to either side of zero)
should not exceed O. 012 inch.
8.
If a total deflection of O. 012 inch is encountered in step 7. recheck the indica-
tion.
The total deflection must occur in a disk circumference of 4 inches or
more.
9.
Repeat steps 6 through 8 for the 19 remaining disk surfaces.
10.
Rotate the pack cleaning brushes clear of the disk surfaces.
11.
Remove the disk pack and the disk pack runout gage.
12.
Install the shroud side cover.
7-76
70602500 A
UPPER DECK
DRAWER (RIGHT- .
HAND SHROUD. .
SIDE COVER
R~MOVED)
DETAI L
\
DIAL INDICATOR
(PART OF DISK PACK
RUNOUT GAGE)
~DISK
PACK RUNOUT
GAGE (BASE ATTACHED
MAGNETICALLY TO
UNDERSlDE OF UPPER
DECK SHIELD)
sClle
Figure 7 - 52.
Disk Pack Runout Check
TESTER CARD
The Tester Card (P IN 40072100) is a special tool used extensively in the maintenance
procedures of Section 6.
As an aid in using the card, the schematic diagram (8FFN)
is provided in Section 5 and Figure 7 - 53 is the logical portrayal of the same card.
,..:'.-
70602500 A
7-77
-J
I
1,2 I 5,6
-J
00
003
30
K414
32
K412
K410
3&. K40 B
37
K406
38
K404
K402
,J. .
ON
1,2
~
3,4
1407
LLED FeR UPPER
SPINDLE (LOGIC ROW A). TO USE WITH LOWER SPINDLE, CHANGE
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50
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13.160010
12 1308
41 0 A27
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33
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50
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06 1315
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33
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BI61210
05 B17
36
LOGIC CHASSIS (03)
22 0 1311
44
13162210
05 B14
05 (] Bl1
LOGIC CHASSIS (03 )
BI62310
02 1314
13 0 B15
05
LOGIC CHASSIS (03)
02 1314
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1:3162410
16 0 81~
10
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8162510
02 1314
12 0 t315
18
04 1316
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33 0 821
LOGIC CHASSIS (03 )
LOGIC CHASSIS ( 03)
02 ~21
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;; BK1001l
13
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17
LOGIC CHASSIS (03 )
25 0 821
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BKl0211
17 0 R21
16
02 821
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22
LOGIC CHASSIS (03 )
22 0 821
10
LOGIC CHASSIS ( 03)
BKI0411
03 B21
22 a 821
BK10610
21
LOGIC CHASSIS (03 )
05 B16
12 0 821
14
LOGIC CHASSIS (03 )
BKI0611
02 821
21 0 B21
41
BKI0810
04 B16 \ 37 a B21
LOGIC CHASSIS ( 03 )
LOGIC CHASSIS ( 03 )
BK10811
41 0 821
33
02 B21
42
04 1316
LOGIC CHASSIS (03 )
I:3K11010
29 0 821
30
LOGIC CHASSIS (03 )
BKI1011
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42 0 1321
44
LOGIC CHASSIS (03 )
BK11210
05 816
18 a 821
LOGIC CHASSIS (03 )
BK1121l
44 a B21
29
03 B21
LOGIC CHASSIS (03 )
BKl1410
06 B16
08 a 1321
45
36
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BK11411
03 B21
45 0 1321
40
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HK20310
OR
B1~
22 0 A2~
BK30110
LOGIC CHASSIS ( () 3 )
02 806
38 a BOb
21
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LOGIC CHASSIS (03)
13
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12
02 ~ 1:1
20 n 1314
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2 BK40410
08
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41
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1 BK40610
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o BK40620
03 1:31~
13
30 a B12
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91:3K40710
26
03 1313
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8 BK40810
03 1312
16
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7 BK41010
04 1312
29
17 0 t316
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6 BK41210
28
04 B12
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08
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04 1312
5 BK41410
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18
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12
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05
28
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13
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LOGIC CHASSIS (03 )
LOGIC CHASSIS (03 )
LlJGIC CHASSIS (03 )
LOGIC CHASSIS (03 )
LOGIC CHASSIS (03 )
LOGIC CHASSIS (03 )
LOGIC CHASSIS (03 )
LOGfC CHASSIS (03 )
LOGIC CHASSIS (03 )
LOGIC CHA-SSIS (03 )
LUGIC CHASSIS (03 )
LOGIC CH-AsSIS (03 )
LlIGIC CHASSIS (03 )
LnGTcCHASSIS (03)
LOGIC CHASSIS (03 )
LOGIC CHASSIS (03 )
LOGIC CHASSIS (03 )
LOGIC CHASSIS (03 )
LOGIC CHASSIS (03)
LOGIC CHASSIS (03 )
LOGIC CHASSIS ( 03 )
LUGIC CHASSIS (03 )
LO(; J C CHASSIS (03 )
LOGIC CHASSIS (03 )
LOGIC CHASSIS (U3 )
LDC; rCCI·:r~fssrs-nr3-1
LOGIC CHASSIS ( () 3 )
LT.ffiTC CHASS.lS (03 )
LOGIC CHASSIS (03 )
LOGIC CHASSIS ( 03)
LOGIC CHASSIS (03)
LOGIC CHASSIS ( 03)
LOGIC CHASSIS (03 )
LOGIC CHASSIS ( 03 )
LOGIC CHASSIS (03 )
LOGIC CHASSIS (03)
LOGIC CHASSIS (03)
[OGrc CHASSIS (03)
LOGIC CHASSIS (03)
LOGIC CHASSIS (03 )
LOGIC CHASSIS (03)
LOGIC CHASsIS (03)
LOGIC CHASSIS (03)
LOGIC CHASSIS (03)
LOGIC CHASSIS (03)
[oGlC CHASSIS (03)
LOGIC CHASSIS ( 03 )
LOGIC CHASSIS (03)
LOGIC CHASSIS (03)
lOGIC CHASSIS (03)
LOGIC CHASSIS (03)
LOGIC CHAssIs (03)
LOGIC CHASSIS (03)
LOGIC CHASSIS (O3)
LOGIC CHASSIS (03)
----..,--.-_ _..
..
- - - -.. --------.-- -
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---------------
LW70951400
1"100 SINGLE CHANNEL
~
XI24l10
02 A20
29
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03 A20
37
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04 A20
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04 A20--4l
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11 A12
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30
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32
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(I)
REVISION H
Al9
A19
A19
Al'(
825
H2"!
Al7
0
0
0
0
()
0
0
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21
26
13
30
32
38
13
32
44
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28
38
38
10
10
14
14
20
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. 10
14
14
20
20
10
10
14
14
25
29
40
45
45
25
32
25
09
10
05
17
25
33
30
25
37
LOGIC
LOGIC
LOGIC
U1GIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LUGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LDGIC
LOGIC
LOGIC
LOGIC
LlJG I C
LOGIC
LOGIC
LOGIC
LOGIC
[nGIC
LOGIC
LDGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
38
36
41
20
21
26
13
30
PAGE
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIS ( 03)
CHASSIS (03)
CHASSIS ( () 3 )
CHASSIS (03 )
CHASSIS (03)
CHASSIS (03 )
CHASSIS ( 03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03)
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03 )
C'HASS IS ( () 3 )
CHASSIS (03 )
CHASSIS (03)
CHASSIS (03)
CHASSIS (03)
CHASSIS (03 )
CHASSIS (03 )
CHAssIs (03 )
CHASSIS (03 )
CHA.SSIS (03 )
CHASSIS (03)
CHASSls-T03 )
CHASSIS (03)
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIs (03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03 )
CHASSIS (03)
CHASSIS (03)
CHASSIS (03)
CHASSIS (03 )
CHASSIS (03)
CHASSIS (03 )
CHASSIS (03)
CHASSIS (03)
CHASSIS (03 )
CHASSIS (03)
CHASSIS (03)
CHASSIS (03)
8
5496
5496
5496
~496
549A
54':16
5496
54'::16
5496
5496
5496
5496
5496
5496
5496
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:10 \) ALO
Lt)GIC CHASSIS (03 )
YT01710
10 IiLH
24
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06 B28
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24
32 0 B20
LOGIC CHASSIS ( 03 )
YT01721
03 820
24 n B1H
LOGIC CHASSIS (03)
33
Z203910
08 B25
26 0 A20
36
LOGIC CHASSIS (03)
04 1:325
Z204010
B20
34- 0
36
LOGIC CHASSIS (03)
Z204710
08 B27
26 0 A20
LOGIC CHASSIS ( 03 )
36
Z204810
05 B27
34 0 820
36
LOGIC CHASSIS (03 )
Z206710
03 A22
18 0 A21
01
LOGIC CHASSIS (03 )
Z207010
04 B22
18 0 821
01
LOGIC CHASSIS ( 03 )
44
0100110
05 A18
LOGIC CHASSIS (03)
21 0 A14
02 A18
24 0
LOGIC CHASSIS (03)
0100210
A17
22
20
LOGIC CHASSIS (03 )
0100310
02 A18
18 0 A17
03 A18
0100410
20 0
A17
37
LOGIC CHASSIS (03)
04 A18
05
LOGIC CHASSIS (03 )
0100510
17 0 A14
44
05 B18
LnGIC CHASSIS ( 03 )
0100710
21 0
B14
24 0 817
LOGIC CHASSIS (03)
0100810
02 B18
22
LOGIC CHASSIS (03 )
02 B1R
20
0100910
18 0 817
37
LOGIC CHASSIS ( 03 )
03 B18
20 a 817
0101010
04 B18
05
LOGIC CHASSIS (03 )
17 0 B14
CYI 0101110
08
LOGIC CHASSIS (03 )
02 A25
01 0 A24
~ 0200110
09
LOGIC CHASSIS (03 )
0200210
02 A25
05 0 A24
09 0 A24
LOGIC CHASSIS (03)
0200310
02 A25
13
02-0(Y410
16
LOGIC CHASSIS (03 )
02 ---AZ-5-f2 0 A24
LOGIC CHASSIS (03)
16 0 A24
21
0200510
02 A25
24
LOGIC CHASSIS (03)
17 0 A24
0200610
02 A25
44
LOGIC CHASSIS (03)
0200710
05 A25
26 0 A19
44
LOGIC CHASSIS (03)
09 A25
34 0 B19
0200810
LOGIC CHASSIS (03)
12
0200910
04 A26
21 0 A30
04 A26
24 0 A30
14
LOGIC CHASSIS (03)
0201010
LOGIC CHASSIS (03)
04 A26
13
0201110
28 0 A30
04 A26
16
LOGIC CHASSIS (03)
0201210
29 0 A30
17
LOGIC CHASSIS (03)
04 A26
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33 0 A30
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04 A26
18
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LOGIC CHASSIS (03 )
20
38 a A30
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05 A26
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A30
22
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05 A26
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44 0 A30
0201710
05 A26
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10
0201810
05 A26
45 0 A30
44
LOGIC CHASSIS ( 03 )
0201910
26 a A19
06 A27
44
LOGIC CHASSIS (03)
09 A27 . 34 0 B19
12 0202010
28
LOGIC CHASSIS (03)
04 A27
01 a
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110202110
1oOZ022To----b-4---A27--05 0 A24
29
LOGIC CHASSIS ( 03-)
LOGIC CHASSIS (03)
9 0202310
04 A27
09 a A24
33
LOGIC CHASSIS (03)
34
04 A27
8 0202410
12 0 A24
LOGIC CHASSIS (03)
38
7 0202510
04 A27
16 0 A24
LOGIC CHASSIS (03)
40
04 A27
17 0 A24
6 0202610
LOGIC CHASSIS (03)
05
44 0 A30
5 0202710
05 A2B
YI40010
YI52330
YI52340
YI60020
YK20210
YK20510
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33
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541..J6
5496
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0403-5-10
0403610
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0403710
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0404610
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lit
28
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(I)
--
-
PAGE
REVISION H
LOGIC
LOGIC
LOGIC
LUGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LtlG I C
LOGIC
LUGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LUGIC
U1G IC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
[n(, I C
LUGIC
CUbIC
U1G IC
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHZ\SSI~
CHA.SS IS
CHASSIS
CHASSIS
[ n'GTrCRI\SSTS
(03 )
(03)
(03 )
(03 )
(03)
(03)
(03 )
(03 )
(03 )
(03 )
(03)
(03)
(03 )
(03)
(03 )
(03 )
(03 )
(03)
(03)
(03 )
(O~ )
(03)
(03)
( (3)
(03)
(03)
(03)
(03 )
(03 )
(03)
(03 )
(03 )
(03)
(03)
(03 )
(03)
(03 )
LOGIC CHASSIS
LOGIC CHt\SSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
COG rC--CA A-S'S I--s-r031
LOGIC CHASSIS (03)
[ObIC CHASSIS (03)
LOGIC CHASSIS (03 )
LOGIC CHASSIS ( 03)
LOGIC CHASSIS (03 )
LOGIC CHASSIS ( 03)
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In NO
L.ENGTH
AI4l710
AI41AIO
AI4221t)
A!42220
A!42230
AI42710
AI50910
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AI50930
AI51310
AI51410
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AIS2030
AI52110
AT52210
AIS2220
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At52310
A!52320
AI52330
AI52340
A!6001,)
AI6002t)
AI60210
AI60610
A!6}210
AI62210
AI62310
AI6?410
AI62S10
AKIOOIO
AKIo210
AK10410
AKIo610
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AKliolO
AK11210
AKl1410
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04
03
03
04
02
04
04
04
04
05
04
06
07
02
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11
13
07
11
12
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A12
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A07
A01
A07
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A07
A01
A01
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AOS
A08
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05 A14
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02 Al4
02 A14
04 A16
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04
04 A16
05 A16
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05 A16
06 A16
03. A19
07 A'9
A1('203)0
70602500
ORIGIN
A13
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•
REVISION A
45
41
20
21
22
42
16
18
12
41
21
20
14
21
36
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32
30
29
28
30
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41
44
01
S
DESTINATION TITLE
0
0
0
0
0
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A08
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22
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13
16
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37
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0
0
0
0
0
0
0
0
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29 0
19 0
08 0
28 0
22 0
SIZE/COL.OR
A20
4S
44
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
A29
38
LOGIC r.:HASSIS
17
29
08
01
18
13
17
12
17
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25
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14
09
13
32
25
16
12
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38
13
32
32
33
40
36
44
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10
18
18
11
22
21
41
42
44
ECO
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
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CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
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CHASSIS
CHASSIS
CHASSIS
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CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHASSIS
9-24.3
LW73129700 Cil MOO DC
In. NO
LENGTH
n9
n2
03
n2
02
AT00120
70602500
ORIGIN
A20
A06
A13
Al3
Al3
oS A13
03 All
03 All
03 A12
04 A12
04 A12
04 A12
03 A14
05 Al4
06 AI4
04. A07
04 All
04 A13
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06 A06
('4 A07
04 A07
05 A07
05 A07
05 A07
n2 All
03 All
AIS
0402 AIS
03 AIS
04 AlS
04 AIS
04 Al7
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04 Al7
04 A17
04 A17
07 A24
11 A24
06 A24
10 A24
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AK301It)
AK40010
AK40210
AK40410
AK40610
AI<40620
AK40710
AK40810
AI(41010
AK41210
AI(41410
AI(SI)OIO
AK50020
AK50030
AKS0210
AKSo211
AKS0212
AKc;o310
AKSo31l
AK50610
AKSI)620
AKsn710
AKSn810
AKSo910
AKSll10
AI(Sl120
AK60010
AK60210
AK60410
AK60610
AK60810
AK61010
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AK61410
AK61810.
AK62010
ATOOOIO
ATOO020
ATOOllO
E
REvISInN A
40
38
32
20
12
OS
30
40
25
17
12
01
28
S
DESTINATION TITLE
0
0
0
0
0
0
0
0
0
0
0
0
0
829
38
A06
A14
A14
AIS
A15
A12
A12
Al4
Al6
A14
Al6
Al6
AOS
Aoa
All
A13
All
A06
Al3
All
An8
All
All
All
A12
All
A16
Alb
Al6
Al6
A16
Al4
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Al4
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A16
816
21
13
12
08
41
25 0
14
10
16
34
12
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26
33
36
42
40
32
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08
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10
36
37
17
24
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0
0
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12 0
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13
26
16
29
28
08
18
14
12
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34
42
05
28
14
13
09
13
10
37
50
33
25
22
12
37
21
33
24
10
11
34
34
26
26
SIZE/COLOR
ECO
LOGIC CHASSIS
LOGIC CHASSIS
l.OGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHAC\SIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHA~SIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHA5SIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC r.HA~SIS
LOG I C .CHA~S IS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
L.OGIC CHASSIS
LOGIC CHASSIS
L.OGIC CHASSIS
L.OGIC CHASSIS
9-24.4
Lw73124700 eTI
Ir'I ",0
LEr-J~T
ORIGIN
A24
A24
A24
A24
AToo210
06
09
ATOO3}0
ATOO320
ATOO410
08
01,
06
09
06
09
AT o0510
ATOo520
AT00610
ATOO620
ATOo110
ATJ01,O
AToo810
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ATOO8?O
ATIJOA?l
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AT01220
ATf)l310
AT01320
ATOl410
AT014?O
ATOlb]O
AT016:?O
AT01710
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AT01720
AT017?1
ATO}A10
ATfl}R'G
AT01910
AT01920
AT02010
AT02020
AT 02110
AT02l11
AT02120
AT02210
AT02211
AT02220
AT0231CJ
70602500
07
08
01
10
r)5
04
10
04
01
10
01
09
03
02
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09
07
02
08
02
07
OR
06
02
08
02
06
03
02
09
03
02
05
E
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ATOo2~O
ATOO4~O
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17
lA
c5
26
A24
30
A24
32
36
37
41
42
01
A2~
A24
A24
A24
A26
A26
A2b
A26
A26
A26
A28
12
12
14
14
01
A2~
05
12
14
17
17
A26
DESTINATION TITLE
0
0
0
0
0
0
0
0
0
0
0
Al6
A16
Al6
Al6
05 0
A2b
A28
A2B
A28
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A28
A2e.
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A26
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A26
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A26
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0
0
0
30
16
32
16
36
37
17
18
25
26
30 0
44
32
36
44
37
41
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0
0
0
0
0
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816
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B16
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A20
A21
820
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A28
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819
818
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20
20
09
09
38
38
30
30
16
16
05
05
28
26
28
28
12
12
10
10
02
18
09
09
16
14
16
14
01
01
08
26
O~
32
44
38
37
44
38
42
33
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
A
SIZE./COLOR
ECO
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
C~ASSIS
CHASSIS
CHASSIS
CHASSIS
Ct-iASSIS
CHASSIS
CHASSIS
CHAc)SIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHASSIS
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CHASSIS
r,HASSIS
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CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
9 -24. 5
LW73129700 ell MOD DC
10 NO
L~NGTH
02
AT02320
AT02410
AT02420
AY40410
AVS1510
AY5t511
AV60110
AV60410
AV60411
8110010
8110020
BII0110
8110120
9110210
8110220
8110310
8110320
8110410
8t10420
BrloSIO
8t10520
8I10610
8t10620
8110710
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02
05
03
06
03
04
03
08
04
08
04
08
04
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05
10
05
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06
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8110910
8111810
BT11820
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04
02
09
10
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07
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B 112210
8 I 200,10
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8t20110
8120120
8121510
8121710
8121810
8 I 2211 O.
08
02
03
.04
07
08
08
8122310
70602500
E
ORIGIN
A2e
A26
A26
A13
A08
All
A17
A08
All
821
821
821
821
B21
821
821
821
821
821
42
41
42
10
24
20
10
37
40
13
12
16
08
10
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14
09
33
821
30
40
29
38
36
37
01
34
821
821
821
B21
821
821
B21
816
816
B16
B16
816
817
B17
B17
817
818
818
819
819
819
•
REvISInN A
S
DESTINATION TITLE
0
0
A28
822
A26
A07
All
A18
A14
All
A14
A25
825
a
0
0
0
0
a
0
0
0
0
a
0
0
a
0
a
32 0
44
45
41
21
42
21
25
29
40
22
05
08
12
14
a
0
0
0
0
0
0
0
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50
33
50
08
20
37
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33
10
10
14
14
20
20
10
10
14
14
20
20
10
10
14
14
25
29
40
40
28
45
45
36
45
45
21
25
29
25
25
33
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
l.OGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
L.OGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
l.OGIC
l.OGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
SIZE/COLOR
ECO
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHAt;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
9-24.6
,....,..
ClI MOD DC
Lw7312~700
If') NO
....
ORIGIN
ATOO2~O
06
09
ATOO310
ATOO320
ATOO410
O.g
06
ATOO4~0
09
AT OO5}O
ATOO520
ATa!)610
AT00620
ATOO710
06
A24
A24
A24
A24
A24
A24
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A24
A24
A24
A26
A2b
A26
A26
A26
A26
A28
A2b
A28
A2B
AZB
A28
A2&
A28
A2e.
A19
A26
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A26
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A26
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09
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70602500
06
03
02
09
03
02
05
E
B18
A26
A28
REV I S I nt--! A
S
17 0
lA 0
25 0
26 0
30 0
32 0
36 0
37 0
41 0
42 0
01 0
05 0
12 0
12 0
14 0
14 0
01 0
Alb
20
A16
A16
A16
Al6
B16
A16
B16
A16
20
09
09
38
16
05
05
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36 0
44 0
37 0
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0
0
0
0
0
0
0
0
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0
0
0
0
0
0
0
0
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SIZE./COLOR
DESTINATION TITLE
A28
A28
AlA
B18
A19
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819
818
A18
AlB
Al8
A26
B18
A26
Al8
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18
09
09
16
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14
01
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26
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32
44
38
37
44
38
42
33
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
ECO
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CI-iASSIS
CHASSIS
CHACSSIS
CHASSIS
CHASSIS
r.HASSIS
CHASSIS
CHASSIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
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CHASSIS
CHASSIS
CHASSIS
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r.HA~SIS
CHASSIS
CHASSIS
CHA!'SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
9 -24.5
10 NO
L~NGTH
AT02320
AT02410
AT02420
AY40410
AVS1510
AY5t51l
AV60110
AV60410
AV60411
B1I0010
8110020
BIIOllO
BI10120
8110210
8110220
8tl0310
8110320
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8t10420
BrlOSI0
Btl0520
8110610
8110620
BI10110
02
08
02
05
03
06
03
04
03
08
04
08
04
08
04
09
05
10
05
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10
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10
n6
04
02
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8110910
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8Tl1820
8112010
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8 1122"10
81200,10
8I20020
B120110
8120120
8121510
8121710
8121810
8122110.
8122310
09
10
04
08
07
04
09
08
02
03
.04
07
08
08
ORIGIN
Aze
A26
A26
A13
A08
All
A17
A08
All
821
821
821
821
821
821
821
821
821
821
821
821
821
821
821
821
821
B21
816
B16
B16
B16
B16
911
817
B11
B17
B18
818
819
819
819
•
REVISION A
LW73129100 erI MOD DC
S
42 a
41 a
42 0
10 a
24 0
20 0
10 0
37 0
40 0
13 a
12 0
16 0
08 0
10 0
OS 0
14 0
09 0
33 0
32 0
30 0
40 0
29 a
38 0
36 0
31 0
01 0
34 0
44 0
4S 0
41 0
21 a
42 0
21 0
25 0
29 0
40 0
22 0
05 0
08 0
12 0
14 0
DESTINATION TITLE
A28
822
A26
A07
All
A18
A14
All
Al4
A25
B25
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B25
A25
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A?1
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827
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812
A25
825
812
A29
829
817
620
819
A25
A21
A29
50
33
50
08
20
37
09
40
33
10
10
14
14
20
20
10
10
14
14
20
20
10
10
14
14
25
29
40
40
28
45
45
36
45
45
21
25
29
25
25
33
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
SIZE/COLOR
Eca
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHAt;SIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS'
CHASSIS
CHASSIS
CHASSIS
CHASSIS
9 -24. 7
LW731~9700
In NO
L.ENGTH
8141011
B141210
B141211
B141220
B1412'-1
8t41310
8141510
8141511
8141710
8141810
HI4?2]0
SI422?O
8142230
8142110
8150910
Bt50920
8I50930
BI51310
8151410
B152010
8I52020
8152030
B152110
BtsZ21n
BI52220
8t5223n
BIS2310
8152320
BI5233n
8152340
8I60010
8160020
8160210
8160610
8161210
8162210
8162310
8162410
8162510
9KIOOIO
BKI0210.
70602500
n3
05
('14
05
04
n4
04
n4
04
03
03
04
n2
04
04
n4
04
n5
04
06
01
1"3
04
04
03
03
06
12
11
07
12
• 11
06
05
05
05
02
02
02
04
04
E
REvISInN A
CII MOD DC
S
ORIGIN
812
B11
B12
B11
812
Bll
Bll
B12
B13
813
812
B12
B12
813
80A
B08
813
I:Hl
All
1307
B01
801
B11
907
B07
A07
B08
B08
B08
BOA
R08
B08
815
815
817
814
814
B14
B11t
816
9'16
DESTINATION TITLE
SIZE/COL.OR
813
24
LOGIC CHASSIS
812
813
B12
813
B12
812
813
Bl1
All
813
813
813
811
B12
812
B08
B07
A01
814
817
B08
808
811
B08
B08
B17
A21
827
817
A27
827
B08
B08
Bl1
Bll
815
40
13
41
11
34
38
09
17
29
08
01
18
13
17
12
11
09
25
38
14
09
13
32
25
16
12
40
40
13
33
33
33
40
36
44
05
18
33 0
815
815
821
18
25 0
821
17
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC'
LOGIC
LOGIC
LOGIC
LOGIC
LOCH C
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
L.OGIC
LOGIC
L.OGIC
LOGIC
LOGIC
09 0
08 0
40
05
41
01
12
38
45
41
20
21
22
42
16
18
12
41
21
a
0
0
0
a
0
0
a
0
0
0
0
0
0
a
0
0
20 0
14 0
21
36
24
32
30
29
28
30
32
41
44
01
26
22
0
a
a
a
0
0
0
0
a
0
0
0
0
a
05 0
13 0
16 a
12 0
10
•
ECO
CHASSIS
CHASSIS
CHAC:;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA 55 I S
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
9 -24. 8
-~
---
~
REvlslnN A
LW13129100 CII MOO DC
10 NO
LENGTH
(\4
81<10410 .
81<10010
BK10810
81<11010
8K11210
BKl1410
BI<20210
8K20310
B'<20510
8K30110
8K40010
8K402]0
81<40410
8'<4061Q
8K40620
81<40710
81<40810
8K41010
81<41210
8K41410
BI<50010
BKSnO?O
81<50030
BI<50210
BI<50211
81<50212
B1<5t)310
RK50311
05
04
04
oS
816
816
816
B16
B16
l)6
Bl~
03
819
819
820
02 B06
03 813
02 813
02 813
05 813
03 813
03 813
03 B12
04 B12
04 812
04 812
03 B14
nS 814
06 814
04 607
1)4 B1l
04 B13
n2 . 807
1)6
806
B07
n4
(")4
B07
05 B07
607
n5
05 807
02 B11
03 Bll
04 815
'02 B1S
03 BlS
04 B1S
04 815
03 817
08
06
~K:;(j610
8K5r)6~0
8K50110
81<50810
81<'50910
81<51110
BKS 112.0
61<60010
8K60210
8K60410
8K60610
8K60810
8K61010
70602500
ORIGIN
E
--- ........
S
22 0
12 0
37 0
29 0
18 0
08 0
28 0
22 0
40 0
38 0
32 0
20 0
12 0
05 0
30 0
40 0
25 0
17 0
12 0
01 0
28 0
25 0
14 0
10 0
16 0
34 0
12 0
05 0
26 0
33 0
36 0
42 0
40 0
32 0
37 0
05 0
18 0
08 0
41 0
10 0
36 0
SIZE/Ct)LOR
DESTINATION TITLE
821
B21
821
821
821
821
820
A29
829
B06
814
B14
815
Bl S'
B12
812
B14
816
B14
816
B16
B08
B08
B11
B13
B11
B06
913
Bl1
808
811
Bll
B11
B12
B11
816
B16
816
B16
B16
814
22
21
41
42
44
45
44
40
40
21
13
12
08
41
13
26
16
29
28
08
18
14
12
16
34
42
05
28
14
13
09
13
10
37
SO
33
25
22
12
31
21
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
L.OGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
L.OGIC
L.OGIC
LOGIC
L.OGIC
ECO
CHA5SIS
CHASSIS
CHASSIS
CHA~SIS
CHASSIS
CHASSIS
CHASSIS
CHASSlS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CH4C;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS·
CHASSIS
CHASSIS
CHASSIS
9-24.9
LW73129700 CII MOD DC
10 NO
LENGTH
BI<61210
81<61410
6K618}0
05
04
n4
n4
81(6~010
8TOl)010
8TOQ020
8T001)0
8TOO120
BT00210
8T00220
8T003]0
BT00320
8T004)0
BT00420
8T00510
8T00520
8T00610
8TOO'b20
8T00710
8T00720
BTOOAIO
8TOOA20
8T01210
8T01220
8T01310
8T01320
8:()1410
8T01420
8T01610
8T01620
8T01710
8 T01711
8T01720
(\8
07
08
08
09
06
10
06
08
06
09
06
11
06
09
('6
'08
05
08
01
09
01
(13
02
10
01
10
04
06
8T0172~
03
8T01810
8T01820
8T01910
8TOi920
8T02010
8T02020
BT02110
10
n1
09
02
70602500
06
02
10
E
ORIGIN
817
B17
~17
817
B24
824
824
824
824
824
824
8~4
824
824
824
824
B24
824
826
826
R26
826
828
828
828
828
B28
828
828
828
828
A20
828
820
828
828
826
826
826
826
826
•
REvISlnN A
37
17
24
01
01
OS
12
14
17
18
2S
26
30
32
36
31
41
42
01
OS
12
14
01
OS
12
14
17
18
25
26
30
24
32
24
36
37
17
18
S
DESTINATION TITLE
a
0
a
0
0
a
0
0
0
0
0
0
a
a
0
0
0
0
a
0
0
0
a
0
a
a
0
0
0
0
0
0
0
0
0
a
0
a
B11
814
814
814
Al6
B16
A16
B16
A16
B16
A16
B16
A16.
B16
Al6
816
A16
B16
A16
816
A19
B19
A18
B18
Al8
17
11
10
10
40
40
32
32
13
13
01
01
2S
25
32
32
29
B18
29
828
828
A18
02
11
30
30
24
B18
25 0
26 0
A20
AlB
820
818
A18
818
Al8
826
B18
826
30 a
A19
33
24
10
17
36
36
28
28
33
24
33
34
34
25
26
25
32
32
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
l.OGIC
LOGIC
LOGIC
l.OGIC
LOGIC
SIZE/COLOR
ECa
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA!;SIS
CHASSIS
CHAc)SIS
CHASSIS
CHASSIS
CHAC;SIS
CHASSl~::
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHASSIS
CHASSIS'
CHASSIS
CHASSIS
CHASSI~
9-24.10
-~
---
",.,...--
10 NO
L.ENGTH
('13
8T02111
BT0212u
BT02210
8T02211
8T02220
8T02310
BT0232 1)
8T02410
02
05
BTO~420
n2
BY40410
BYS1510
AYS1511
AY60110
BY60410
BY60411
0100110
0100210
0100310
0100410
0100510
0100710
0100810
0100910
0101010
0101110
02001JO
0?OO210
0200310
0?O0410
0200510
05
03
70602500
06
826
819
826
B28
828
826
A2"
B13
B08
Bll
10
06
03
03
03
05
02
02
03
04
05
('12
02
1')3
04
1'l2
02
02
02
('12
02
0~OO~10
05
09
04
04
04
04
04
04
05
05
E
A19
826
02
02
0200710
0200RI0
0?00910
0201010
0201110
0201210
0201310
0201410
0201510
o20i610
ORIGIN
,,2
B I"
B08
Bll
A18
Ala
Ale
AlB
A18
B18
818
91B
818
B18
A25
A25
A25
A25
A25
A25
A25
A25
A26
A26
A26
A26
A26
A26
A26
A26
-
REvlSlnN A
LW73129700 CiI MOO DC
32
32
36
32
37
41
42
41
42
10
24
20
10
31
40
21
24
18
20
17
21
24
S
DESTINATION TITLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A18
B26
B19
B18
826
A22
828
B22
R26
A07
Bll
818
B14
Bl1
814
A14
A17
A17
A17
A14
B14
817
817
817
814
A24
A24
A24
A24
A24
A24
A19
819
A30
A30
A30
A30
A30
A30
A30
A30
18 0
20
17
01
05
09
12
16
17
26
34
21
24
28
29
33
34
38
40
0
a
0
0
0
0
0
a
0
0
0
0
0
0
0
0
0
0
4S
37
32
45
42
21
50
21
SO
08
20
37
09
40
33
44
22
20
31
05
44
22
20
37
05
08
09
13
16
21
24
44
44
12
14
13
16
17
18
20
22
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
L.OGIC
LOGIC
LOGIC
L.OGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
L.OGIC
LOGIC
L.OGIC
L.OGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
L.OGIC
---
SIZE/COL.OR
ECO
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHA~SIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHAC;SIS
CHA5SIS
CHA5SIS
CHASSIS
CHAt;SIS
CHAC;SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
CHASSI.S
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
9-24.11
REvISlnN A
LW13129700 CII MOO DC
10 NO
LENGTH
0201710·
0?01A10
0201910
0?C)20]0
n202110
0202210
0202310
0202410
0202510
02026]0
0202710
0202810
0202910
0203010
0?03110
0203210
0203310
0203410
0203510
0203blO
0203710
0?03AIO
0?03910
0204010
0204110
02042]0
0204310
0204410
0204~10
0204910
02015010
02051'10
0205210
0205310
0205410
0205510
0205610
0205710
70602500
A27
A21
A27
A27
A21
A27
A21
A27
A28
OS
A28
06
06
04
A29
A29
A29
A29
B25
825
825
825
825
825
825
825
821
827
827
827
827
827
B27
821
826
826
826
826
826
826
826
826
826
n3
O?'0/~510
04
04
04
05
05
05
E
A26
n5
05
n6
09
n4
04
n4
04
04
04
05
02
02
02
02
02
02
n8
04
n4
n4
04
04
04
04
08
. 05
t)4
04
04
0'"'04610
0204110
ORIGIN
A2~
44
45
26
34
01
05
09
12
16
17
44
45
01
05
09
12
01
05
09
12
16
11
26
34
01
05
09
12
16
17
26
34
21
24
28
29
33
S
DESTINATION TITLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A30
A30
A19
819
A24
A24
A?4
A24
A24
A24
A30
A30
A24
A24
A26
A26
B24
824
824
824
924
824
A20
820
824
824
824
B24
624
924
A20
820
830
830
830
830
830
930
930
830
830
a
0
a
0
0
0
a
0
0
0
0
0
0
0
0
0
0
0
0
0
34 0
38 0
40 0
44 0
09
10
44
44
28
29
33
34
38
4C)
05
08
44
45
08
09
08
09
13
16
21
24
36
36
28
29
33
34
38
40
36
36
12
14
13
16
11
18
20
22
09
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
L.OGIC
•
SIZE/COLOR
ECO
CHASSIS
CHASSIS
CHAC:;SIS
CHASSIS
CHASSIS
CHA~SIS
CHASSIS
CHA~SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHAc)SIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA5SIS
CHASSIS
CHASSIS
CHASSIS
CHA!o;SIS
CHASSIS
CHASSI.S
CHASSIS
CHASSIS
CHASSIS
9 -24. 12
-
........
ClI
L'oJ731~9700
In
"'0
LENGTH
<~)
05
~20
oS
~2a
020~01f)
05
06
06
03
03
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IJ200
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REVISlt')N A
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31
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32
30
33
34
37
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38
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43
41
44
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9-24.14
-
LW73129700 CII MOD DC
10 NO
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040iolO
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0401210
0401310
0401410
0401510
0401610
0401710
0401810
0401910
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70602500
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•
REVISION A
ORIGIN
S
DESTINATION TITLE
IJ201
IJ201
IJ201
IJ201
IJ201
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IJ201
IJ201
IJ201
IJ201
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IJ201
IJ201
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11
14
15
18
16
20
17
21
22
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26
24
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31
29
32
30
33
34
37
35
38
40
43
41
44
42
45
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49
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59
63
60
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36
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9 -24. 15
LW73129700 CII MOD DC
10 NO
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ORIGIN
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DESTINATION TITLE
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13
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41
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21
24
28
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REvISION A
LW73129700 ell MOD DC
10 NO
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0602310
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ORIGIN
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DESTINATION TITLE
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IIJ20027
IIJ20028
IIJ20031
IIJ20029
IIJ20032
IIJ20030
IIJ20033
IIJ20034
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9-24.17
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LW73129700 eiI MOD DC
10 NO
LENGTH
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0701710
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70602500
ORIGIN
S
DESTINATION TITLE
IIJ20112
IIJ20110
IIJ20113
IIJ20111
IIJ20114
IIJ20115
IIJ20118
IIJ?0116
IIJ20120
IIJ20117
IIJ20121
IIJ20122
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•
REVISION A
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36
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22
21
22
21
22
16
17
28
29
28
29
33
34
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
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SIZE/COLOR
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9-24. 18
REvISInN A
LW731?9700 ell MOD DC
10 NO
LENGTH
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70602500
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0·7
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ORIGIN
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DESTINATION TITLE
IIJ20160
IIJ20164
IIJ20165
IIJ2017Q
IIJ201b6
IIJ20171
IIJ20167
IIJ20172
IIJ202 B
IIJ202 0
IIJ202BB
IIJ202DO
IIJ202 E
IIJ202 H
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16
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21
24
28
29
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11
33
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14
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38
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33
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10
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45
17
33
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14
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
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LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
L.OGIC
L.OGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
SIZE/COLOR
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHASSIS
CHA~SIS
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CHAClSIS
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CHASSIS.
CHASSIS
CHASSIS
CHASSIS
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9 -24. 19
LW73129700 ell MOD DC
10 NO
LENGTH
11000~2
11000?3
1100030
1100031
1100032
1100033
1100034
1100035
1100040
1100041
1100042
1100043
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70602500
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ORIGIN
803
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04 B03
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07 803
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02 A03
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02 A24
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02 A27
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1000610
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33 0
36 0
37
38
40
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11
29
25
0
0
0
DESTINATION TITLE
B12
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813
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06 R A13
06 R A14
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06 R A16
06 R A17
06 R A12
06 R A19
06 R A20
06 R A21
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06 R A25
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46 R A02
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46
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LOGIC CHASSIS
LOGIC CHAc)SIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHA5SIS
LOGIC CHA5SIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC CHASSIS
LOGIC'CHASSIS
LOGIC CHASSIS
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LOGIC CHASSIS
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LOGIC CHA~SIS'
LOGIC CHASSIS
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SIZE/COLOR
20
20
20
20
20
20
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2"
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9-24.20
LW73~29700
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L£NGTH
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1100122
1100123
1100130
1100131
1100132
1100133
1100134
1100135
1100140
1100141·
1100142
1100143
1100144
1100150
1100151
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1100230
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06
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S
DESTINATION TITLE
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20
20
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1100434
1100435
1100440
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70602500
E
REvISInN A
ORIGIN
S
806
807
B08
809
812
H13
B14
815
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B11
B18
B19
820
821
822
824
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817
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04/06171
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ORIGIN
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801
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REVISION A-
LW13129100 CII MOO DC
S
DESTINATION TITLE
R
R
R
R
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9-24.23
I
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I • 297 . 25
24
0
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4
2978
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298 25
29UA,
299 25
299A
299B
300 25
300A
300B
I
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27
A4J205
12
20
17
27
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15
20
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27
27
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27
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24
302 25
302A
24
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16
20
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27
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4
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21
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34
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14
A4J205
45
20
4
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20
0
A4J205
48
20
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14
4
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20
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14
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FIND GAUGE COLOR LENGTH
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lREF.) lREF,) lAPPAOICJ
NO.
24
303 ' 25
303A
A7
0
303B
305B
306
306A
306B
25
25
307
307A
307B
25
308
308A
308B
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:
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FIND NO.
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DESTINATION
SHEET 20
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1
16,17
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20
27
A3TB202
18
27
4
A7
5
16,17
0
A3TB202
14
27
A7
18
16,17
4
A3TB202
12
27
A7
17
16.17
0
A7
28
16,17
A3TB202
32
27
4
A7
29
16.17
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30
27
0
4
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26
24
27
27
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44
45
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0
4
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1
5
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16,17
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A4TB202
20
18
27
27
0
4
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14
12
27
27
B7
81
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24
24
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305
305A
20
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25
.
24
301
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304
304A
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•
21
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27
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45
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16.17
24
310A
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24 ~7
311
312
12
12
24
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COMMENT SHEET
MANUAL TITLE _ _C::..O~N.;..::T:..::R:..:.O~L~D:..;.A;;;:,.;T::..:A:;..;;:".....=B~M.:;;..;1:;:,:A;.;:;.5;;........;M;;.;.::".;:;U-:;;;L;;;:,.;T;;;:,.;I;;.;;;P;.....;L;;;;.E=-...;D~IS;;.;;;K..;;;..,...;;;D;;.,;;;R~I;;;...V;....E~_ _
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----------------------------------~---------~
FIRST CLASS
PERMIT NO. 8241
MINNEAPOLIS, MINN.
BUSINESS REPLY MAIL
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NO POSTAGE STAMP NECESSARY IF MAILED IN U.S.A.
POSTAGE WILL BE PAID BY
CONTROL DATA CORPORATION
8100 34TH AVENUE SOUTH
MINNEAPOLIS, MINNESOTA 55440
AnN: TECHNICAL PUBLICATIONS DEPT.
PLANT TWO
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