730000_Sol_Systems_Manual_Jan1978 730000 Sol Systems Manual Jan1978
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Sol SYSTEMS MANUAL
Processor Technology
Corporation
7100 Johnson Industrial Drive
Pleasanton, CA 94566
Telephone (415) 829-2600
Copyright (C) 1976, 1977, 1978, Processor Technology Corporation
Fourth Printing, February, 1978
Manual No. 730000
PREFACE
This new edition of the Sol Systems Manual contains many revisions and
additions made to the third printing.
Information which accumulated
in the Updates Section was integrated into the text. Parts lists were
revised to include Processor Technology parts numbers for all parts,
and to include new alternate parts. Several new and revised drawings
were included in Section X, which should make assembly even easier.
The keyboard, previously a kit, is now supplied as a complete tested
subassembly. Sol 10, which consisted of a Sol 20 without the backplane, and with a lighter power supply, has been discontinued. Assembly procedures have improved from the experience of thousands of kitbuilders. An overall parts list for the entire kit has been included
to facilitate receiving inspection.
Much effort has gone towards making this manual complete and accurate.
The process of updating and revision always continues, however, and
we invite your input. If you should find an error, or have suggestions
for improving any of our manuals, please submit your suggestions in
writing to our Technical Publications Department, and they will be
given thorough consideration.
The three-ring binder you are reading from is an "easel" binder. The
cover is hinged from side to side, as well as down the spine, so that
it may form into an "easel" stand. To use this feature, lay the manual
open on a table. Bend the full width of the manual along the creased
hinge, until a resistance to further bending is felt.
Then set the
manual up on the table, with the bottom of the pages down against the
table, and the top inclining away from you. In this position your
hands are free for building, making measurements, or troubleshooting.
A binder set up in this manner is shown below.
IMPORTANT
The first part of this manual you should read is at the very end: the
Updates Section. If updates sheets have been inserted in this section,
make sure to integrate them before you begin building or using your
Sol.
REV A
CONTENTS OUTLINE
Detailed contents precede each section.
I
II
III
IV
V
VI
INTRODUCTION and GENERAL INFORMATION
Sol POWER SUPPLY ASSEMBLY and TEST
Sol-PC ASSEMBLY and TEST
PERSONALITY MODULE ASSEMBLY
KEYBOARD ASSEMBLY
Sol CABINET-CHASSIS ASSEMBLY
VII
OPERATING PROCEDURES
VIII
THEORY OF OPERATION
IX
SOFTWARE
X
DRAWINGS
APPENDICES
UPDATES
PROCESSOR TECHNOLOGY CORPORATION
Sol TERMIN~L COMPUTER™
FIGURE
LIST OF ILLUSTRATIONS
PAGE
TITLE
2-1
Sol-20 fan closure plate assembly .
II-7
2-2
Coaxial cable preparation . . . .
II-9
2-3
Aluminum heat sink installation .
1I-12
2-4
Partially assembled Sol-20 power supply
subchassis assembly . . . . . . . .
II-16
2-5
Sol-20 power supply subchassis assembly . .
II-17
2-6
2-7
Sol-PC power connector and voltage measurements .
II-21
Sol-20 power connector and voltage measurements .
II-21
3-1
Identification of components . .
III-8
3-2
Clock circuit waveforms . . . .
III-18
3-3
Deleted
3-4
Coaxial cable preparation . . . . .
III-21
3-5
Display section timing waveforms . .
III-23
3-6
Bending selected pins on U42, 59 and 75 .
III-25
3-7
U14 through U21 socket jumpers . .
III-26
3-8
Display circuits test pattern . .
III-27
3-8A
Step 28A jumper installation
. . .
III-27
3-9
CPU Functional Test No. 1 display .
III-32
3-10
CPU Functional Test No. 2 display.
III-34
3-11
3-12
Personality module bracket/guide installation .
III-34
Installation of vectored interrupt jumpers
III-46
4-1
Handle bracket installation
IV-6
6-1
VI-4
6-2
Types of screws used in Sol cabinet-chassis
assembly • • . . . . . . . . . . . ". . . .
Brackets used in Sol cabinet-chassis assembly . . . .
6-3
Sol-20 with covers removed . . . . . . • . . . . .
VI-IO
6-4
Sol-20 with covers removed.
VI-IO
6-5
Sol-PC coaxial cable connector assembly .
VI-13
6-6
Backplane board (Sol-BPB) installation
VI-15
6-7
Backplane board (Sol-BPB) installation
VI-16
6-8
Protective foot pad installation. . . . .
VI-19
7-1
Connecting the basic Sol system
VII-6
7-2
Sol control switch settings for terminal mode .
VII-7
REV A
.
VI-4
PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
ILLUSTRATIONS/TABLES
TITLE
FIGURE
PAGE
7-3
Location of positioning adjustments, VRI and VR2. . .
VII-8
7-4
Deleted
Connecting Sol to two cassette recorders
VII-29
Connecting Sol SDI to current loop device
. .
such as TTY
VII-32
7-7
Connecting Sol SDI to
VII-32
7-8
Connecting Sol PDI to
8-1
Clock Generator Timing
7-5
7-6
. . . . . .
. . . . . . · · · · ·
communications modern · · · · ·
parallel device .
· · ·
.
VII-33
8-2
· . VIII-II
Example of uppercase character (I) display . . . . . . VIII-24
8-3
Example of lowercase character (p) display. . . • • . VIII-24
8-4
Video Display timing. . . . • . . . . . . . . • • • . VIII-27
8-5
8-6
6574 Character Generator ROM pattern. .
· VIII-30
6575 Character Generator ROM pattern. .
· VIII-31
TITLE
TABLE
PAGE
1-1
Sol-20 Kit Parts List .
1-5-13
1-2
Sol Systems Parts List. .
1-14,15
2-1
Sol Power Supply Parts List .
3-1
Sol~PC
4-1
PM2708/92l6 Personality Module Parts List
IV-2
6-1
Sol-20 Cabinet-Chassis Parts List • • . • •
VI-2,3
7-1
Sol Operating Controls and Their Functions.
VII-2
7-2
Baud Rate Selection with Switch S3 . .
VII-15
7-3
Word Length Selection with S4-2 & 3 •
VII-15
7-4
Sol Keyboard Assignments.
VII-18-2l
7-5
Control Character Symbols and Definitions .
VII-23
8-1
Port Decoder (U35 & 36) Outputs and
Their Functions
. . .•
• . . . . . . . . VIII-17
REV A
Parts List . • .
11-2-4
111-2-7
I
INTRODUCTION and GENERAL INFORMATION
1.1
1.2
1.3
Introduction.
I-I
1.1.1
1.1.2
I-I
I-I
To the Sol Kit Builder • .
.•.
To Factory Assembled Sol Owners.
General Information . . • .
I-2
1.2.1
1.2.2
1. 2.3
I-2
I-3
I-3
Sol-20 Description .
Service. . . . . •
Replacement Parts.
Receiving Inspection . • •
I-4
1.3.1
1.3.2
I-4
I-4
Sol Kits • • . . • • • • •
Assembled Sol Kits . .
1.4
Section X Drawings . . • .
I-17
1.5
Sol Kit Assembly Order • •
I-17
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
1.1
SECTION I
INTRODUCTION
This manual consists of nine separate sections presented in
the preferred order of usage for the kit builder, a section of assembly drawings and schematics, appendices of useful information, and a
section of updates.
Integrate the update information into this manual before doing
anything else. Then finish reading this section completely, following the suggestions provided and performing the specified inspections.
Sections II, III, IV, V and X primarily supply assembly instructions and aids for the kit builder. The owner of a factory
assembled unit, however, will find some of the test procedures and
chassis-cabinet assembly instructions and drawings useful when servicing Sol. Operating Procedures (Section VII), Theory of Operation
(Section VIII) and Software (Section IX) will be of interest to both
the kit builder and assembled unit owner.
Three special features are incorporated in this manual to make
it easier and more efficient to use. They are 1) an "easel" binder
to facilitate reading while you work with your Sol,
2) an instruction
and component installation check-off format to minimize omitting procedural steps, and 3) foldout drawings printed on one side only. The
third feature eliminates much page juggling since a drawing, when
folded out, is not obscured by the text pages.
1.1.1
To the Sol Kit Builder
For the Sol kit builder, this manual supplies the information
needed to assemble, test and operate the Sol-PC Single Board Computer
and the Sol-20 Terminal Computer Systems. As anxious as you are to
assemble your kit, we suggest that you first take the time to read
this section and scan the rest of the manual before making any inspections or starting assembly.
(The time you take to "get on board
Sol," so to speak, will be time well invested.)
Then proceed with the
receiving inspection and assembly. When assembling your kit, follow
the instructions in the order given.
Should you run into a problem during assembly, calIon us, or
your Sol dealer, for help if necessary.
If your completed kit does
not work properly, recheck your assembly step by step. Most problems
stern from poor soldering, failure to follow the instructions, backward installed components and/or installing the wrong component. OnCE
your are satisfied that your Sol is correctly assembled, feel free to
ask us, or your Sol dealer, for assistance if you still have trouble.
1.1.2
To Factory Assembled Sol Owners
For those who purchased a factory assembled and tested unit,
this manual supplies the information needed to start you on the way
REV A
I-I
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
SECTION I
to using your Sol. It also contains information to help you understand how Sol works and how to service it. As anxious as you are to
use Sol, we suggest that you first take the time to read this section
and scan Sections ·VI!, VIII, IX and Appendices AVI and AVIII.
(The
time you take to "get on board with Sol," so to speak, will be time
well invested.)
Theh proceed with the receiving inspection, and~ using
Section VII as your guide, connect the basic Sol system, place it into
operation and get acquainted with Sol by putting it through some simple operations. When doing this, follow the instructions in the order
given.
Since your unit was factory assembled and tested before shipment, your Sol should operate correctly. If it doesn't, recheck your
interconnect cabling.
If a problem persists, feel free to ask us, or
your Sol dealer, for assistance.
1.2
GENERAL INFORMATION
1.2.1
Sol-20 Description
Except for the power supply and keyboard, the Sol-20 Terminal
Computer electronics is contained on the Sol-PC. The Sol-20 is built
around an 8080 microprocessor. Integral support circuitry permits
full implementation of every 8080 function.
Use of the popular S-lOOI.
bus assures compatibility with a large variety of memory boards and
peripheral devices.
Sol-20 features an 85-key integral keyboard, both parallel
and serial communications interfaces, an audio cassette tape interface, a video display generator, 1024 8-bit words of system RAM
(random access memory), 1024 8-bit words of display RAM, and a plugin personality module with up to 2048 bytes of stored program on ROM
(read only memory) .
Parallel interfacing is eight bits each for input and output
plus control handshaking signals, and the output bus is tri-stated
TTL for bidirectional interfaces. The serial interface includes both
asynchronous RS-232 and 20 rnA current loop provisions with transmission
rates of 75 to 9600 Baud (switch selectable).
The dual rate, 300 or 1200 bps (bits per second), audio cassette interface is program-controlled and self-clocking with a phaselock loop.
It includes automatic level control. Recording is CUTS/
Byte Standard compatible, asynchronously Manchester coded at 1200/
2400 Hz or 600/1200 Hz.
Video display circuitry generates sixteen 64 character lines
from data stored in the integral 1024 8-bit word display RAM. Alpha- . . .
numeric and control characters (the full 128 upper and lower case plu.
control ASCII character set) are displayed black on white or white on
black (switch selectable). Multiple solid video inversion cursors,
REV A
1-2
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
SECTION I
with switch selectable blink, may be programmed. The display output
is standard EIA, 1.0 to 2.5 V peak-to-peak with composite negative
sync, and a nominal 7 MHz bandwidth. It can thus be used to drive
any standard video monitor.
(A monochrome TV, converted for video
input, can also be used. See Appendix VI.)
Included in the Sol are 1024 words of static, low power system RAM capable of full speed operation and a plug-in personality
module that contains the software monitor, or control,program. Three
personality modules are available for Sol:
SOLOS--allows full stand-alone terminal/computer operation.
It permits data storage and retrieval, control of
electronic instruments and independent calculations.
In general, SOLOS is the choice when the Sol system
will be lion its own" operating independently of other
computers. SOLOS is the standard personality module
supplied with the Sol-20.
PM2708--permits customized software with 2708 EPROMS (not
supplied) for special applications.
BOOTLOAD--same as SOLOS except that the SOLOS ITERMinal" command is replaced with a bootstrap loader program for
use with the Helios II disk memory system.
Your Sol Computer power is easily expanded since it is compatible with all S-IOO bus products. Sol-20 has a capacity for five expansion modules. Add-on memory and interface modules are available
from Processor Technology as well as a host of software cassettes.
Processor Technology also has a number of quality peripheral devices
to work with Sol, including a TV monitor and cassette recorder.
1. 2.2
Service
Service of all kinds is the responsibility of the dealer from
whom you purchased your Sol-PC or Sol System. Contact the dealer if
you have problems completing assembly and testing, or your Sol malfunctions and you cannot correct the problem.
1. 2.3
Replacement Parts
Order replacement parts from Processor Technology or your Sol
dealer. When ordering, specify our part number, component descriptiol
(74LSI09 IC (integrated circuit), 2N2222 transistor, and 680 ohm, 1/4
watt, 5% resistor for example). Processor Technology part numbers
for Sol components and assemblies are given in Tables 1-1 and 1-2.
REV A
I-3
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
1.3
RECEIVING INSPECTION
1. 3.1
Sol Kits
SECTION I
Examine the shipping container(s) for signs of possible damage
to the contents during transit.
Then inspect the contents for damage.
(We suggest you save the shipping materials for use in returning the
kit to Processor Technology should it become necessary to do so.)
If
your Sol kit is damaged, immediately contact the carrier, and please
write us at once describing the condition so that we can take appropriate action.
Then check all of the parts and components against Table 1-1
(Table 3-1 if you have a Sol-PC kit).
Table 1-1 is a consolidated
listing of the parts lists in Sections II, III, IV and VI.
It lists
the Processor Technology part number, description, alternate (if any),
and minimum quantity for each part in the complete Sol-20 Terminal
Computer kit. Note that some parts have alternates. An alternate is
equivalent to its primary part and may be used in any location for
which the primary part is specified. Where indicated in Table 1-1,
alternates may be supplied with your kit in lieu of primary parts, and
in some cases you may receive, for a given primary part, a combination
of the primary and/or alternates. For examole,you co~ld receive one
8T97, two 8097 and two 74367 for the five 8T97's specified in Table
1-1; any of these may be used in any place that calls for an 8T97.
(Also use Table 1-1 to find our part number for any replacement part
you order.)
Figure 3-1 in Section III, Figures 6-1 and 6-2 in Section VI
and Drawings X-I through X-IO will help you identify unfamiliar parts.
Should a part be missing, please contact us at once so that we can
take appropriate action.
1. 3.2
Assembled Sol Units
Examine the shipping container(s) for signs of possible damage
to the contents during transit. Then inspect the contents for damage.
(We suggest that you save the shipping materials for use in returning
you Sol unit to Processor Technology should it become necessary to do
so.)
If your Sol unit is damaged, immediately contact the carrier,
and write us at once describing the condition so that we can take appropriate action.
Then check the contents against Table 1-2 to be sure you received everything. Table 1-2 identifies all Sol System assemblies
and parts.and lists their quantity and Processor Technology part number. Should anything be missing, please contact us at once so that
we can take appropriate action.
If you need to order a replacement
part or assembly sometime in the future, use the parts lists in SectiC'-II, III, IV and VI, in conjunction with Tables 1-1 and 1-2, to determine our part number and description.
(Continued on Page 1-16.)
REV A
1-4
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
SECTION I
Table 1-1.
Sol-20 Kit Parts List.
DESCRIPTION
PART NO.
ALTERNATES
MINIMUM
QUANTITY
INTEGRATED CIRCUITS
701001
0026
75369
1
701013
1458
72558
3
701017
1489
75189
1
701053
4N26
701023
4001
14001
1
701027
4013
1413
2
701031
4019
701033
4023
14023
1
701035
4024
14024
1
701037
4027
14027
1
701039
4029
3
701041
4030
1
701045
4046
14046
2
701047
4049
14049
2
701051
4520
14520
1
701011
6011
1602,2017,1013
2
701007
6574
6575
1
701086
74HOO
1
701090
74LSOO
3
701092
74LS02
701094
74LS04
4
701088
74S04
1
701061
7406
2
701098
74LS08
1
701100
74LS10
2
701108
74LS20
3
701118
74LS86
1
701120
74LS109
8
701126
74LS136
1
REV A
1
1
9LS02
1-5
2
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
Table 1-1.
PART NO.
SECTION I
Sol-20 Kit Parts List.
DESCRIPTION
(Continued)
ALTERNATES
MINIMUM
QUANTITY
701128
74LS138
3
701138
74LS157
3
701142
74LS163
701075
74166
701077
74173
701079
74175
701146
74LS175
701150
74LS253
4
701158
74LS367
7
701164
7812
1
701166
7912
1
701184
8T94
1
701186
8T97
8097, 74367
5
701178
8T380
8836
1
701170
8080A
9080, 8080
1
701019
91L02
2102, 21L02
726004
9216* (marked "SOLOS")
1*
701192
93L16
1
* 9216
25LS163
4
1
8TIO
2
1
25LS175
9
16
Personality Module only.
TRANSISTORS
702016
TIP41
1
702002
2N2222
4
702004
2N2907
2
702010
2N4360
1
DIODES and BRIDGE RECTIFIERS
703001
IN270
1
703003
IN4001
6
703005
IN4148
REV A
IN914
1-6
10
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
Table 1-1.
PART NO.
SECTION I
Sol-20 Kit Parts List.
DESCRIPTION
(Continued)
ALTERNATES
MINIMUM
QUANTITY
703011
1N5231
2*
703029
101
1
703027
106-2
703031
970-1
1
703033
980-1
1
*4 if
10632
1
2708 Personality Module is supplied.
RESISTORS
705002
0.1 ohm, wire wound, 5W
1
705005
6.8 ohm, 1/2 W, 5%
2
705009
39 ohm, 2 W, 5%
1
705011
47 ohm, 1/4 W, 5%
3
705013
68 ohm, 1/4 W, 5%
1
705015
75 ohm, 1/4 W, 5%
1
705017
100 ohm, 1/4 W, 5%
2
705019
100 ohm, 1/2 W, 5%
3
705018
130 ohm, 1/2 W, 5%
2*
705023
200 ohm, 1/4 W, 5%
1
705026
270 ohm, 1/4 W, 5%
1
705025
330 ohm, 1/4 W, 5%
15
705027
330 ohm, 1/2 W, 5%
1
705031
470 ohm, 1/4 W, 5%
1
705033
470 ohm, 1/2 W, 5%
2
705035
680 ohm, 1/4 W, 5%
9
705041
1K ohm, 1/4 W, 5%
2
705043
1. 5K ohm, 1/4 W, 5%
705045
1.69K ohm, 1/4 W, 1%
1
705052
3.3K ohm, 1/4 W, 5%
1
705053
4.02K ohm, 1/4 W, 1%
1
* 2708
63
Personality Module Only.
REV A
1-7
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
Table 1-1.
PART NO.
SECTION I
Sol-20 Kit Parts List.
(Continued)
ALTERNATES
DESCRIPTION
MINIMUM
QUANTITY
705055
4.7K ohm, 1/4 W, 5%
1
705057
5.6K ohm, 1/4 W, 5%
6
705061
10K ohm, 1/4 W, 5%
705065
15K ohm, 1/4 W, 5%
2
705071
39K ohm, 1/4 W, 5%
2
705072
47K ohm, 1/4 W, 5%
2
705073
50K ohm, variable
2
705075
56K ohm, 1/4 W, 5%
1
705081
lOOK ohm, 1/4 W, 5%
3
705074
lOOK ohm, variable
1
705083
150K ohm, 1/4 W, 5%
2
705085
1M ohm, 1/4 W, 5%
2
705089
2.2M ohm, 1/4 W, 5%
1
705091
3.3M ohm, 1/4 W, 5%
2
**
38**
39 i f 2708 Personality Module is supplied.
CAPACITORS
707001
10 pf, Disc Ceramic
1
707005
330 pf, Disc Ceramic
1
707009
470 pf, Disc Ceramic
1
707011
680 pf, Disc Ceramic
3
707015
.001 llf, Disc Ceramic
6
707017
.001 llf, Mylar
2
707021
.01 llf, Mylar
2
707023
.047 llf, Disc Ceramic
39
707025
.1 llf, Disc Ceramic
14
707027
.1 llf, Mylar
1
707029
.68 llf, Mono Ceramic
1
707032
1 llf, Tantalum
2*
707036
15 llf, Tantalum
8
*5 if 2708 Personality Module is supplied.
REV A
1-8
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
Table 1-1.
PART NO.
SECTION I
Sol-20 Kit Parts List.
DESCRIPTION
(Continued)
J\.LTERNATES
MINIMUM
QUANTITY
707038
100 ]If, Aluminum
1
707041
2500 ]If, Aluminum
2
707047
18,000 ]If,
1
707049
54,000 ]If, Aluminum
Aluminum
1
SOCKETS, CONNECTORS and HEADERS
713002
DIP, 8-pin
713004
DIP, l4-pin
30
713006
DIP, l6-pin
74
713012
DIP, 24-pin
2*
713014
DIP, 40-pin
3
717002
Header, Male, 20-pin
2
717019
Header, Male, 7-pin
1
717011
Socket, Female, 25-pin
1
717013
Socket, Male, 25-pin
1
717044
Socket, Phone Jack, Miniature
2
717045
Socket, Phone Jack, Subminiature
2
717042
Socket, Coax, 75 ohm
2
717043
Plug, Coax 75 ohm
1
717047
Sleeve, Adapter, Coax
1
719001
Connector, PC, 100-pin
1
719002
Connector, PC, 100-pin
6
719003
Connector, PC, 30-pin
1
724005
Commoning Block, 5 position
2
*3
2
if 2708 Personality Module is supplied.
SWITCHES, RELAYS and HOLDERS
723002
Switch, DIP, 6 Section
2
723003
Switch, DIP, 8 Section
2
723005
Switch, AC Power
1
723010
Relay, DIP, 500 ohm Reed
2
724007
Holder, Fuse
1
REV A
I-9
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
Table 1-1.
PART NO.
SECTION I
Sol-20 Kit Parts List.
DESCRIPTION
(Continued)
ALTERNATES
MINIMUM
QUANTITY
PRINTED CIRCUIT BOARDS
105010
Sol-REG
1
102002
Sol-PC
1
107001
2708/9216 Personality Module
1
103001
Backplane
1
WIRE, CABLE and CABLE ASSEMBLIES
716000
Wire, 24 AWG
7"*
716008
Wire, 24 AWG
l'
716005
Cable, Coaxial, 75 ohm
4'
718002
Cable Assembly, Flat, 20-Wire
1
105012
Cable, Sol PC DC Power, 5-Wire
1
105007
Cable, Sol 20 DC Power, 4-Wire
1
718001
Cord, AC Power, 3-Wire
1
105013
Cable Assembly, C-8
1
105018
Cable Assembly, AC Connector
1
105024
Assembly, Fuse Lead, AC Switch
1
105025
Assembly, Neutral Lead, AC Switch
1
103003
Cable Assembly, Sol Backplane
1
*6"
if 2708 Personality Module is not supplied.
HANDLES, BRACKETS and CARD GUIDES
102004
Bracket, Mounting, Sol PC, 2"
2
101016
Bracket, Backplane, Right-Angle
2
101017
Bracket, Gusset, Left Side
1
101047
Bracket, Gusset, Right Side
1
101005
Bracket, Connecting
1
101006
Bracket, Keyboard Support
2
107009
Handle, Personality Module
1
722007
Card Guide, 2-1/2"
722009
Card Guide, 4"
REV A
2
10
1-10
PROCESSOR TECHNOLOGY CORPORATION
$01 SYSTEMS AND COMPONENTS
Table 1-1.
SECTION I
Sol-20 Kit Parts List.
DESCRIPTION
PART NO.
(Continued)
ALTERNATES
MINIMUM
QUANTITY
CHASSIS, COVERS and LABELS
101003
Chassis, Main
1
105019
Subchassis, Power Supply
1
101004
Subchassis, Expansion
1
101002
Cover, Keyboard
1
101020
Cover, Top
1
101015
Cover, Logo, P1exig1ass
1
105020
Plate, Fan Closure
1
101007
Assembly, Side Panel, Left
1
101008
Assembly, Side Panel, Right
1
101012
Label, Serial Number
1
101014*
Label, Sol Logo*
1*
101032
Label, Connector
1
101019
Label, Fingerwe11, Black
2
*
May be packaged under logo cover.
HARDWARE
720074
Machine Screw, 2-56 x 3/16
2
720075
Lockwasher, Internal Tooth, #2
2
720002
Machine Screw, 4-40 x 1/4
4
720001
Machine Screw, 4-40 x 3/16
4
720003
Machine Screw, 4-40 x 5/16
22
720013
Machine Screw, 4-40 x 7/16
7
720014
Machine Screw, 4-40 x 5/8
9
720049
Spacer, 4-40 x 1/4
2
720038
Lockwasher, Internal Tooth, #4
720025
Lockwasher, Spring, #4
8
720040
Flat Washer, Nylon, #4
2
717051
Lug, #4
2
720010
Hex Nut, 4-40
REV A
36
32
I-II
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
Table 1-1.
PART NO.
SECTION I
Sol-20 Kit Parts List.
DESCRIPTION
(Continued)
ALTERNATES
MINIMUM
QUANTITY
720020
Machine Screw, Metal, 6-32 x 1/2
24
720019
Machine Screw, Nylon, 6-32 x 1/2
2
720022
Machine Screw, 6-32 x 3/4
1
720023
Sheetmetal Screw, #6 x 1/4
32
720026
Self-tapping Screw, #6 x 5/16
5
720041
Lockwasher, Internal Tooth, #6
30
720067
Flat Washer, #6
18
720011
Hex Nut, 6-32
19
720032
Machine Screw, 8-32 x 1/2
3
720051
Lockwasher, Internal Tooth, #8
3
720012
Hex Nut, 8-32
3
720036
Machine Screw, 10-24 x 3/8
8
720079
Machine Screw, 10-24 x 1
2
717053
Lug, #10
2
720042
Screw, Quick Connect, Knurled
2
MISCELLANEOUS
709004
Crystal, 14.31818 MHz
1
105033
Fan Assembly
1
722003
Finger Guard, Fan
1
105028
Transformer, Sol 20
1
105034*
Transformer, 220/240 V*
1*
104000
Keyboard Assembly, 85 Key
1
723018
Fuse, 3.2A, Slo-Bl0
1
105011
Heatsink
1
721004
Heatsink
1
721006
Heatsink
1
721000
Heatsink Compound
1
713018
Augat Pins
720060
Clamp, 1-1/2
15
1
*Sol 20/220 and Sol 20/240 only.
REV A
I-12
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
Table 1-1.
SECTION I
Sol-20 Kit Parts List.
DESCRIPTION
PART NO.
(Continued)
ALTERNATES
MINIMUM
QUANTITY
720061
Clamp, 2-1/2"
1
720046
Washer, Mica, TO-220
2
720062
Washer, Mica
1
722011
Tie, Cable
5
716004
Tubing, PVC
3"
722017
Foot, Rubber, Adhesive
4
716001
Solder, 60/40, 20SWG
727000
Basic 5 Package
1
730000
Manual, Sol Systems
1
REV A
31'
1-13
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
SECTION I
Table 1-2.· Sol Systems Parts List .
. DESCRIPTION
PART NO.
QUANTITY
Sol-20/8
101000-02
Sol-20 Terminal Computer
1
202000-01
8KRA Memory Module
1
723018
Fuse, 3.2A Slo-Bl0
.2
Cap, Fuse Holder
1
718001
Cord, AC Power, 3-Wire
1
727000
Basic 5 Package
1
730000
Manual, Sol Systems
1
730002
Manual, 8KRA
1
Sol-20/16
101000-02
Sol-20 Terminal Computer
1
203000-01
16KRA Memory Module
1
723018
Fuse, 3.2A Slo-Bl0
2
Cap, Fuse Holder
1
718001
Cord, AC Power, 3-Wire
1
727000
Basic 5 Package
1
730000
Manual, Sol Systems
1
730003
Manual, 16KRA
1
Sol System I
400400-01
Sol-20/8 Terminal Computer
1
722016
TV Monitor
1
722019
Cassette Recorder
1
718005 or
101034
Video Cable Assembly
1
718006 or
101041
Audio Cable Assembly
1
718007 or
101042
Motor Control Cable Assembly
1
REV A
1-14
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
Table 1-2.
SECTION I
Sol Systems Parts List.
PART NO.
(Continued)
DESCRIPTION
QUANTITY
Sol System II
400500-01
Sol-20/16 Terminal Computer
1
722016
TV Monitor
1
722019
Cassette Recorder
1
718005 or
101034
Video Cable Assembly
1
718006 or
101041
Audio Cable Assembly
1
718007 or
101042
Motor Control Cable Assembly
1
Sol System III
400500-01
Sol-20/16 Terminal Computer
1
203100
32KRA Memory Module (or two 16KRA
Memory Modules, PIN 203000-01)
1
300000-01
Helios II
1
722016
TV Monitor
1
718005 or
101034
Video Cable Assembly
1
727036
Extended Disk Basic Package
1
730009
Manual, Helios II
1
REV A
1-15
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
SECTION I
Before applyirig power to your factory assembled Sol unit, use
the following procedure to internally inspect the unit, and if required, install the memory module:
CAUTION
DO NOT TOUCH ANY OF THE Sol-PC COMPONENTS,
OR Sol-20 INTERNAL COMPONENTS, UNTIL INSTRUCTED TO DO SO IN THE FOLLOWING PROCEDURE.
REV A
1.
On the Sol-20, remove the two knurled quick connect screws
(located on back of Sol) that hold the top cover in place.
2.
On the Sol-20, refer to Drawing X-10 in Section X and
carefully swing the top cover up, unhook it from the back
edge of the keyboard cover, and set it to one side.
3.
On the Sol-20, carefully swing keyboard cover up, unhook
it from the front edge of the main chassis, and set it to
one side.
4.
On the Sol-20, touch the chassis to discharge any static
electricity.
(On the Sol-PC this may be accomplished by
touching the ground trace along the edge of the board.)
Visually inspect all IC's, the personality module and
cable connectors to see if they are firmly seated. Secure
any" loose cable connectors and push gently down on any
loose IC's until they are fully seated in their socket.
If the personality module is loose, push on its handle
(see Drawing X-7 in Section X) to seat the module firmly
in its socket.
5.
On the Sol-20, install the memory module(s} in the expansion chassis (located in left rear corner of Sol as viewed
from the front).
You may install the module(s} in any of
the five card slots. With the component side up, insert
edge connector side of module in card guides and carefully
slide the module in until the edge connector is fully
seated in the backplane (the vertical circuit board on the
front side of the expansion chassis) connector.
6.
For the Sol-20, reassemble it by hooking the keyboard
cover under the front edge of the main chassis and lowering it over the keyboard, hooking the top cover over the
back edge of the keyboard cover and lowering it down into
place over the rear of the unit, and installing the two
knurled quick connect screws.
7.
Insert a fuse in the fuse cap, push the assembly into the
fuse post (see Figure 7-1 in Section VII), and turn cap
one-quarter turn clockwise.
1-16
PROCESSOR TECHNOLOGY CORPORATION
Sol SYSTEMS AND COMPONENTS
B.
SECTION I
With AC power cord hot plugged into a 110 V ac outlet,
connect power cord to AC connector on Sol rear panel (see
Figure 7-1).
If you have a Sol-PC, it is now ready to use with a keyboard
and TV monitor.
If you have a Sol-20, you are now ready to simultaneously test the Sol functions and get acquainted with its operation.
Information in Section VII ("Sol Operating Procedures") and IX
("Software") will guide you.
Should you have any problem getting Sol to respond as described
in Sections VII and IX, make sure that you faithfully followed all of
the instructions. If that does not remedy the situation, feel free to
seek help from us or your Sol dealer.
1.4
SECTION X DRAWINGS
This overview of the drawings section in this manual (Section
X) is intended to help you better utilize the drawings supplied therein.
The first 10 drawings (X-l through X-lO) are assembly drawings
which the kit builder will use to assemble his kit. They also provide information that will be useful when servicing the Sol-PC or
Sol-20. Drawing X-II is a functional block diagram of the Sol-PC, the
primary "horne" for the Sol electronics. This diagram includes a
table that relates the functional blocks with the applicable schematic(s) and the IC's used. Drawings X-12 and 13 are schematics of the
Sol Regulator and Power Supply, respectively.
The Sol-PC schematic is separated by functional sections into
five separate schematic drawings (X-14 through X-lB). Notes that apply to all five schematics are provided on Drawing X-lB. To assist
you in relating the schematics to the block diagram, each schematic
incorporates grey, identified blocks for each functional block on
Drawing X-II.
Drawing X-19 is the schematic for the 270B/92l6 Personality
Module, and the remaining drawings (X-20 through X-23) pertain to
the Keyboard Assembly.
1.S
Sol KIT ASSEMBLY ORDER
If you are building a Sol-PC, either start assembly with
Section III (Sol-PC) or IV (Personality Module). The assembly of
these two parts is inter-related, so you may begin with either one.
The recommended assembly order for the Sol-20 is to first
build the power supply. You then have the option of starting to
build the Personality Module (Section IV) or the Sol-PC (Section III)
since the assembly of these two parts is inter-related. Having
REV A
1-17
PROCESSOR TECHNOLOGY CORPORATION
SECTION r
Sol SYSTEMS AND COMPONENTS
completed the power supply, Sol-PC and Personality Module, it is time
to assemble the chassis-cabinet (Section VI) which includes building
the expansion backplane board. Once your Sol is finished, you are
ready to put it through some simple operations and functional tests
as described in Section VII.
REV A
1-18
II
Sol POWER SUPPLY ASSEMBLY and TEST
2.1
Introduction • • . . .
II-l
2.2
Parts and Components . .
II-l
2.3
Assembly Tips • • .
II-5
2.3.1
2.3.2
Electrical . •
Mechanical.
II-5
II-5
2.4
Assembly Precautions
II-6
2.5
Required Tools, Equipment and Materials. .
II-6
2.6
Orientation
II-6
2.6.1
2.6.2
II-6
II-6
2.7
Sol-REG PC Board . .
Fan Closure Plate.
Assembly-Test. • .
II-7
2.7.1
2.7.2
2.7.3
II-7
II-IO
Fan Closure Plate Assembly • . . • .
Sol-REG Assembly and Test . . . . • • .
Power Supply Subchassis
Assembly and Test . • . • • .
II-14
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
2.1
SECTION II
INTRODUCTION
The Sol power supply consists of a regulator board plus additional chassis-mounted components. This section covers assembly and
test of the complete power supply.
2.2
PARTS AND COMPONENTS
You will need the parts listed in Table 2-1 to assemble your
Sol power supply. Select and separate the needed parts from those
supplied with your Sol kit before starting assembly.
If you have any
difficulty in identifying any parts by sight, refer to Figure 3-1 in
Section III, Figure 6-1 in Section VI and the "Standard Color Code for
Resistors and Capacitors" chart in Appendix III. The assembly drawings in Section X will also be useful in identifying parts.
To guide you in selecting and identifying parts, Table 2-1
lists each part, its description, quantity ~nd reference designation
on the drawing(s) you will use in assembling the power supply. You
will encounter two types of reference designators in Table 2-1 (and
parts lists in Section III, IV and VI as well): alphanumeric and encircled numeric designators.
Alphanumeric designators
(Cl, R5, U3, D4, etc.) are used to
identify electronic components such as capacitors, resistors, integrated circuits and diodes. Encircled desigHators (CD, ®, ®, etc.
are used to identify the other parts used in the Sol (chassis, cables,
screws, washers, covers, heat sinks, etc.). Two examples of how to
use the information in Table 2-1 follow:
REV B
1.
Alphanumeric Designators. The first integrated circuit
(IC) entry in Table 2-1 indicates its reference designator is U2 and that U2 will be installed using Drawing X-2
in Section X.
In looking at Drawing X-2, we can see that
U2 (a 1458) is an 8-pin dual inline package (DIP) IC that
will be installed in the near center of the Sol-REG board.
2.
Encircled Numeric Designators. The next to last entry in
Table 2-1, a #10 lug, has a reference designator 12 and
indicates that the two lugs will be installed using Drawing X-3 in Section X.
In looking at Drawing X-3, we can
see what these lugs look like and determine that they will
be installed on resistor leads.
11-1
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
SECTION II
Table 2-1.
Sol Power Supply Parts List.
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
Circuit Board
Sol-REG
1
X-2
1
IC
1458 or 72558
1
X-2
U2
IC
7812
1
X-2
Ul
IC
7912
1
X-2
U3
Transistor
TIP41
1
X-2
Ql
Transistor
2N2222
2
X-2
Q2&3
Diode
IN270
1
X-2
D5
Diode
IN4001
2
X-2
D3&4
Diode
IN4148 or IN914
1
X-2
D2
Diode
IN5231
1
X-2
Dl
SCR
106-2 or 10632
1
X-2
SCRI
Bridge Rect.
101
1
X-2
FWB2
Bridge Rect.
970-1
1
X-2
FWBI
Bridge Rect.
980-1
1
X-3
FWB3
Resistor
0.1 ohm, Wire Wound, 5W
1
X-2
Rl
Resistor
39 ohm, 2W, 5%
1
X-3
10
Resistor
68 ohm, 1/4W, 5%
1
X-2
R6
Resistor
100 ohm, 1/4W, 5%
1
X-2
R14
Resistor
330 ohm, 1/4W, 5%
2
X-2
R2&13
Resistor
lK ohm, 1/4W, 5%
2
X-2
R5&8
Resistor
1690 ohm, 1/4W, 1%
1
X-2
Rl1
Resistor
4020 ohm, 1/4W, 1%
1
X-2
R12
Resistor
10K ohm, 1/4W, 5%
4
X-2
R3,4,7&10
Resistor
56K ohm, 1/4W, 5%
1
X-2
R9
Capacitor
.047 ].If, Disc Ceramic
1
X-2
C8
Capacitor
.1 ].If, Disc Ceramic
2
X-2
C2&3
Capacitor
15 ].If, Tantalum, 20V
3
X-2
C1,6&7
Capacitor
2500 ].If, Aluminum, 25V
2
X-2
C4&5
Capacitor
18,000 ].If, Aluminum, 10V
1
X-3
8
Capacitor
54,000 ].If, Aluminum, 15V
1
X-3
9
REV A
11-2
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
Table 2-1.
SECTION II
Sol Power Supply Parts List (Continued)
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
Transformer
Power, Sol T-2
1
X-3
6
Transformer*
Power, Sol 220/240*
1*
X-3
6
Fan Assembly
Rotron 428056 or
Peewee Boxer PWS2l07FL-2-M
1
X-5
5
Connector
AC Power Receptacle
1
X-I
3
Socket
Coax, 75 ohm
2
X-I
55
Holder
Fuse
1
X-I
9
Switch
AC Power, Alternate Action
1
X-I
4
Block
Commoning, 5 position
2
X-I
10
Fuse
3.2A, Slo-Blo
1
Heat Sink
Bar, For SCRl, Ql & FWBI
1
X-2
5
Heat Sink
Rectangular, For Ul & U3
1
X-2
40
Heat Sink
Circular, For Q2
1
X-2
41
Cable
Coaxial, 75 ohm
15"
X-I
2
Cable
C8 Cable Assembly, 2-Wire
1
X-2
4
Cable
Sol-PC Power, 4-Wire
1
X-2
2
Cable
Sol 20 DC Power, 5-Wire
1
X-4
5
Cord
AC Power, 3-Wire
1
X-IO
36
Lead
Fuse Lead to AC Switch, 3"
1
X-I
7
Lead
Neutral Lead, AC Switch, 3-1/4"
1
X-I
8
Guard
Finger
1
X-I
6
Cable Tie
Plastic
4
X-4
13
Clamp
C-8, 1-1/2"
1
X-3
31
Clamp
C-9, 2-1/2"
1
X-3
32
Insulator
Mica Washer
1
X-2
20
Insulator
Mica Washer, TO-220
2
X-2
19
Plate
Fan Closure
1
X-I
1
Subchassis
Power Supply
1
X-3
1
*Supplied
REV A
only with 220 and 240 Vac versions of Sol.
II-3
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
Table 2-1.
SECTION II
Sol Power Supply Parts List (Continued)
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
Screw
Machine, 4-40 x 3/16
2
X-3
20
Screw
Machine, 4-40 x 5/16
6
X-I
X-3
14
18
Screw
Machine, 4-40 x 7/16
1
X-2
44
Screw
Machine, 4-40 x 5/8
1
X-2
45
Spacer
Tapped, 4-40 x 1/4
2
X-3
30
Lockwasher
Internal Tooth, #4
9
X-I
X-2
X-3
18
48
29
Hex Nut
4-40
6
X-I
X-2
16
50
Lug
#4
2
X-1
58
Machine, Metal, 6-32 x 1/2
16
X-I
X-2
X-3
13
Screw
47
16
Screw
Machine, Nylon, 6-32 x 1/2
2
X-2
46
Screw
Machine, Metal, 6-32 x 3/4
1
X-3
19
Screw
Self-tapping, #6 x 5/16
4
X-3
17
Lockwasher
Internal Tooth, #6
22
X-I
X-2
X-3
17
52
28
Hex Nut
6-32
22
X-I
X-2
X-3
15
51
24
Screw
Machine, Metal, 8-32 x 1/2
3
X-3
15
Lockwasher
Internal Tooth, #8
3
X-3
27
Hex Nut
8-32
3
X-3
23
Lug
#10
2
X-3
12
Compound
Heats ink
1
Solder
60/40, 20 SWG
REV A
11-4
PROCESSOR TECHNOLOGY CORPORATION
SECTION II
Sol POWER SUPPLY
2.3
ASSEMBLY TIPS
2.3.1
Electrical
For the most part the assembly tips given in Paragraph 3.2
of Section III (Page III-I) apply to assembling the Sol regulator
board and power supply.
In addition, scan Section II completely before you start to
assemble the power supply.
2.3.2
Mechanical
1. If you do not have the proper screwdrivers (see Paragraph 2.5), we recommend that you buy them rather than using a knife
point, a blade screwdriver on a Phillips screw, and other makeshift
means. Proper screwdrivers minimize the chances of stripping
threads, disfiguring screw heads and marring decorative surfaces.
2. To assure a correct fit and tight assembly, be sure you
use the screws specified in the instructions.
3. Lockwashers are widely used in the power supply assembly
so that screws will not loosen when subjected to stress or vibration.
Wnen a lockwasher is specified, do not omit it and make sure you
install it correctly.
.
4. Some instructions call for prethreading holes. This is
done to make assembly easier by giving you maximum working space for
installing relatively hard-to-drive sheet metal screws.
If you bypass prethreading instructions you will only make subsequent
cabinet-chassis assembly more difficult.
To prethread a hole, insert specified screw in the hole
and position it as straight as possible. While holding the screw in
this position, drive it into the metal with the proper screwdriver.
If started straight the screw will continue to go straight into the
metal so that the head and sheet metal surfaces are in full contact.
5. The diameter of the shank (threaded portion) of a screw
increases in relation to its number. For example, a 6-32 screw is
larger in diameter than a 4-40 screw. Also, a #8 lockwasher is
larger than a #4 lockwasher.
6. Heat sink compound is supplied with this kit in a small
clear plastic package. It is a thick white substance which improves
heat transfer between components and their heat sinks. To use
the compound, pierce a small hole near the edge of the top surface
of the plastic package, using a pin or sharp knife point. Squeezing
the package will cause a small amount of the compound to ooze out
-
Rev B
1I-5
PROCESSOR TECHNOLOGY CORPORATION
SECTION II
Sol POWER SUPPLY
out of the hole, which may then be applied with a toothpick or small
screwdriver blade. Spread a thin film of the compound on the mating
surfaces of both the heat-generating component and the heat sink surface which it will contact. Then assemble as directed.
2.4
ASSEMBLY PRECAUTIONS
The precautions concerning soldering and the installation and
removal of integrated circuits given in Paragraph 3.3 of Section III
(Page 111-9) also apply to assembling the Sol regulator board.
2.5
REQUIRED TOOLS, EQUIPMENT AND MATERIALS
The following tools, equipment and materials are recommended
for assembling the Sol regulator board:
1.
2.
3.
4.
5.
6.
7.
8.
Needle nose pliers
Diagonal cutters
Sharp knife
Screwdriver, thin 1/4" blade
Screwdriver, #2 Phillips
Controlled heat soldering iron, 25 watt
volt-ohm meter
Ruler
2.6
ORIENTATION
2.6.1
Sol-REG PC Board
Location C5 (2500 ufd capacitor) will be located in the lower
right-hand corner of the circuit board when locations SCRl, Ql and
FWBI are positioned along the top of the board.
In this position the
component (front) side of the board is facing up and the horizontal
legends will read from left to right; the other legends will read from
bottom to top. Subsequent position references related to the Sol~REG
board assume this orientation.
2.6.2
Fan Closure Plate
The large circular cutout will be located in the upper right
quadrant of the plate when the heavy gauge doubler plate is facing
up.
In this position the rectangular cutouts are on the left, the
front side of the plate is facing down, the back side is facing up,
and the-small circular cutout is at the bottom:- We suggest you label
the two sides.
REV C
11-6
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
SECTION II
2.7
ASSEMBLY-TEST
2.7.1
Fan Closure·Plate Assembly
Refer to Assembly Drawings on Pages X-l and 4 in Section X.
(Figure 2-1 shows a completed fan closure plate assembly.)
Figure 2-1.
()
Step 1.
Sol-20 fan closure plate assembly.
(Top of plate in foreground.)
Mount cooling fan and guard to fan closure plate.
Insert four 6-32 x 1/2" binder or pan head screws from back
side (side with doubler plate) of fan closure plate.
(Use the
holes positioned in each quadrant of the large circular cutout.)
Slip fan guard over screws on front side of plate (side
without doubler plate side). Position fan with motor support
struts away from front side of closure plate and with its
leads next to the rectangular cutouts in the plate. Place #6
lockwasher on each screw and secure with 6-32 hex nut.
WARNING
FAILURE TO INSTALL FAN GUARD MAY RESULT
IN DAMAGE TO THE Sol AND/OR PERSONAL
INJURY.
()
Step 2.
Install power on-off switch in upper rectangular cutout in fan closure plate.
(Step 2 continued on Page 11-8.)
REV C
II-7
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
SECTION II
Bend four retainer tabs on switch in and position switch with
terminals facing front side of fan closure plate. Push switch
unit from back side of plate through mounting hole and bend
retainer tabs outward if needed to hold switch in place.
()
Step 3. Install commoning blocks (Item 10 on drawing on Page
X-I) on front side of fan closure plate, one on each side of
on-off switch.
position each block with terminal #1 at top and terminal #5
at bottom and attach each block to front side of fan closure
plate with two 6-32 x 1/2 binder or pan head screws. Insert
screws from back side of plate, place block over screws, on
front side of plate, put #6 lockwasher on each screw and secure with 6-32 hex nut.
()
Step 4.
Install fuse holder in mounting hole located between
the two rectangular cutouts in the fan closure plate.
Insert fuse holder from back side of plate, position large
tab at top, next to on-off switch, and secure holder to plate
with the large lockwasher and nut supplied with holder.
()
Step 5.
Install AC Power cord receptacle on fan closure plate.
position receptacle on front side of fan closure plate over
the rectangular cutout below fuse holder. Orient receptacle
with green lead at the bottom and align the receptacle and
closure plate mounting holes.
Insert two 6-32 x 1/2 binder
or pan head screws from back side of plate through each mounting hole, put #6 lockwasher on each screw and secure with
6-32 hex nut. Be sure receptacle is properly seated in cutout before tightening to avoid damage.
()
Step 6.
Install female coaxial connector on fan closure plate.
Insert connector from front side of plate so that the threaded
end projects through to the back side. Then insert four
4-40 x 5/16 binder or pan head screws from back side of plate
through the four connector and plate mounting holes. Place
#4 lockwasher on each screw except the upper one which is
closest to the AC receptacle. Secure with 4-40 hex nuts.
(Leave upper nu~closest to receptacle loose.)
()
Step 7.
Prepare RG59/U coaxial cable.
(See Figure 2-2.)
Cut a 15" piece of coaxial cable from that supplied. Strip
away 1-1/2 inch of the outer insulation at both ends to expose shield. Unbraid shield at one end and loosely twist it
into a single lead. Do the same thing at the other end. Tin
shield lead at each end and solder a #4 lug to each lead.
Then remove one inch of the inner conductor insulation at both
ends and cut inner conductor to 3/8" length.
REV C
II-8
PROCESSOR TECHNOLOGY CORPORATION
SECTION II
Sol POWER SUPPLY
Figure 2-2.
Coaxial cable preparation.
( ) Step 8. Connect coaxial cable to coaxial connector installed in Step 6.
Solder inner conductor on one end to the pin of the connector. Remove hex nut on upper connector mounting screw
closest to AC receptacle, place l.ug (coaxial shield) on
screw and reinstall hex nut.
( ) Step 9.
Connect fan closure plate wiring.
(See Drawing X-4.)
( ) Install the 3" power switch-to-comrnoning block cable. Connect the female spade lug end to the upper terminal of the
on-off switch and the comrnoning block lug end to the #1
terminal of the commoning block closest to the fan.
NOTE: To install comrnoning block lugs, position lug with
its open side facing away from the terminal numbers on the
bloc~Then gently push lug into appropriate terminal receptacle until it is fully seated.
( ) Install the 3-1/4" fuse holder-to-power switch cable.
(This cable has female spade lugs at both ends.)
Connect
one end to the bottom terminal of the on-off switch and
the other to the longer male spade lug on the fuse holder.
( ) Connect the AC receptacle wire closest to the fan to the
other fuse holder lug. NOTE: The green AC receptacle
wire will be connected later.
( ) Connect other AC receptacle wire to terminal #4 on the
comrnoning block furthest away from the fan (TB2).
( ) Connect upper wire of fan cord to terminal #3 of the
comrnoning block closest to fan (TB1).
( ) Connect lower wire of fan cord to terminal #5 of comrnoning block furthest from fan.
( ) Put fan closure assembly aside.
REV C
11-9
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
2.7.2
SECTION II
Sol-REG Assembly and Test
Circuit references, values and outlines are printed on the component side of the board to assist in assembly. Also refer to
Drawing X-2 in Section x.
()
Step 10. Visually check Sol-REG board for solder bridges
(shorts) between traces, broken traces and similar defects.
If visual inspection reveals any defects, return the board to
Processor Technology for replacement. If the board is not defective, proceed to next paragraph.
()
Step 11. Install the following resistors in the indicated locations. Bend leads to fit distance between mounting holes,
insert leads, pull down snug to board, solder and trim.
LOCATION
Rl*
R2
R3
R4
R5
R6
R7
R8
R9
RIO
Rll
R12
*Mount
VALUE (ohms)
330
10
10
1
68
10
1
56
10
1690
4020
.1, 3 watt
, 5 watt
K
K
K
K
K
K
K
COLOR CODE
none
orange-orange-brown
brown-black-orange
"
"
"
brown-black-red
blue-gray-black
brown-black-orange
brown-black-red
green-blue-orange
brown-black-orange
brown-blue-white-brown
yellow-black-red-brown
Rl approximately 0.15" from board surface.
()
Step 12. Install U2 (1458) in its location between C2 and C3.
U2 is positioned with pin 1 in the lower left-hand corner and
soldered into place. See "Loading DIP Devices" in Appendix IV.
()
Step 13. Install diodes Dl (lN5231), D2 (lN4148), D3 and D4
(lN4001). Bend leads to fit distance between mounting holes,
insert leads, pull down snug to board, solder and trim. BE
SURE to position Dl with its cathode (dark band) to the left,
D2 and D3 with their cathode at the bottom, and D4 with its
cathode at the top.
()
Step 14. Install the following capacitors in the indicated locations. Take care to observe the proper value, type and orientation, if applicable, for each installation. Bend leads outward on solder (back) side of board, solder and trim.
(See NOTE on Page II-II.)
REV C
11-10
PROCESSOR TECHNOLOGY CORPORATION
SECTION II
Sol POWER SUPPLY
Disc capacitor leads are usually coated
with wax during the manufacturing process. After inserting leads through
mounting holes, remove capacitor and
clear the holes of' any wax. Reinsert
and install.
LOCATION
(
)
(
)
)
(
(
(
(
)
)
cl
C2
C3
c6
c7
VALUE~9.1
15
.1
.1
15
15
ORIENTATION
TYPE
Tantalum
Disc
Disc
Tantalum
Tantalum
11+11
lead bottom right
None
None
11+11
11+11
lead right
lead left
Ste2 15. Install 2500 ufd capacitors in locations C4 and
C5. Bend leads to fit distance between mounting holes,
insert leads, pull down snug to board, solder and trim. Be
sure to install c4 with its 11+11 lead to the right and C5
with its 11+11 lead to the left.
( ) Ste2 16. Install Q2 and Q3 (2N2222) in their locations.
The emitter lead (closest to tab on can) of Q2 is oriented
toward the left and the base lead toward the bottom. The
emitter lead of Q3 is oriented toward the bottom and the
base lead toward the right.
( ) Step 17. Read assembly tip 6, on page 11-5. Apply heat
sink compound to the inside of the small black "starshaped" cooling fin, and install it, with the cylindrical
grip down, on Q2 by slipping it down onto the can. Be
sure heat sink does not touch any other component on the
board.
( ) Step 18. Install bridge rectifier FWB 2 (101) in its
location at the bottom of the board. Apply heat sink
compound, per Assembly tip 6 on page 11-5. Position FWB2
with its "+" lead at the top and its "-" lead at the bottom,
insert leads, solder and trim.
( ) Step 19. Install large heat sink, Ul and U3 in their locations on the bottom left corner of the circuit board.
( ) Position large black heat sink, (flat side to board) over
the square foil area in the lower left corner of the PC
board. Orient sink so that the two triangular cutouts in
the sink are over the two triangles of mounting holes in
the board.
REV B
( ) Position Ul (7812) on heat sink and observe how leads must
be bent to fit mounting holes. Note that the center lead
must be bent down approximately 0.2 inches.
II-II
PROCESSOR TECHNOLOGY CORPORATION
SECTION II
Sol POWER SUPPLY
further from the body than the other two leads. Bend
leads so that no contact is made with the heat sink
when Ul is flat against the sink and its mounting hole
is aligned with the holes in the sink and PC board.
Apply heat 'sink compound per Assembly Tip 6, on page II-5.
Fasten Ul and sink to board using a 6~32 x ~ metal screw,
lockwasher and nut. Insert screw from back (solder) side
of board and drive nut finger tight.
()
Position U3 (7912) on heat sink, determine how leads
must be bent as you did for Ul, and bend leads. Place a
rectangular mica insulator over the leads of U3 so that
it fully covers the bottom side of the U3 package. Apply
heat sink compound to U3, the heat sink, and both sides
of the mica insulator. Bend the two outside leads of U3
slightly in toward the center lead, insert leads in mounting holes as you did for Ul, and fasten U3 to heat sink
and PC board using a 6-32 x ~ Nylon screw, lockwasher and
nut. Insert screw from back (solder) side of board and
drive nut finger tight.
( ) Position heat sink, Ul and U3 as needed to obtain correct fit and tighten the Ul and U3 mounting screws.
REMEMBER, NO LEADS CAN CONTACT THE SINK. Solder all
leads and trim if required.
( ) Step 20. Install aluminum heat sink, SCRl, Ql and bridge
rectifier FWBI.
( ) Position aluminum heat sink (see Figure 2-3) along top
of PC board so that the three holes in one side of the
sink are aligned with the SCRl, Ql and FWBI mounting
holes in the PC board.
~~m~Lockwasher
Heatsink
Compound and
J~
+- SCRI
Mica
Insulator~~~. .~t=~.w.c~
~solder
(back) Side
x 7/16 Screw
(Left end, cross-section view)
Figure 2-3.
Rev B
Al~inum
heat sink installation.
II-12
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
SECTION II
( ) Position Ql (TlP4l), with component nomenclature up, on
heat sink so hole in Ql package is aligned with the holes
in sink and PC board. Observe how the leads of Ql must
be bent down to fit the pads for Ql and bend them accordingly. Apply heat sink compound to Ql, the heat sink,
and both sides of the rectangular mica insulator. Place
mica insulator between heat sink and Ql, insert leads
(emitter lead to right) and fasten Ql, insulator and heat
sink to board with a 6-32 x 1/2 Nylon screw, lockwasher
and nut.
Insert screw from back (solder) side of board
and drive nut finger tight.
( ) Position FWBI
(970-1) ,
with "+" lead to the right, on
heat sink, determine how leads must be bent as you did
for Ql, and bend leads. Apply heat sink compound.
Insert
leads ("+" lead to right) and fasten FWBI and heat sink
to PC board with a 4~40 x 5/8 screw, lockwasher and nut.
Insert screw from back (solder) side of board and drive
nut finger tight.
( ) Position SCRI (106-2 or 10632)
on heat sink with component nomenclature up and prepare it for installation as
you did Ql and FWBI. Apply heat sink compound to SCRl,
the heat sink, and both sides of the circular mica insulator. Place the mica insulator between the heat sink and
SCRl, insert leads and fasten SCRl, insulator and heat
sink to PC board with a 4-40 x 7/16" screw, lockwasher anc
nut.
Insert screw from back (solder) side of board and
drive nut finger tight.
( ) Check alignment of heat sink, SCRl, Ql and FWB2 and tightE
the three mounting screws. Solder all leads and trim if
required. Wipe off excess heat sink compound, if necessary. NOTE:
The heat sink may have to be repositioned
when you mount the Sol-REG on the power supply subchassis,
This will require that you loosen the mounting screws for
SCRl, Ql and FWB2 and retighten them after repositioning
the heat sink.
(
)
Step 20A.
Install C8 (0.47 ufd disc capacitor), R14 (100 ohm
1/2 watt resistor, color code brown-black-brown), R13 (330
ohm, 1/4 watt resistor, color code orange-orange-brown) and
diode D5 (lN270) as follows (see Drawing X-2 in Section X) :
( ) Connect C8 in parallel with R2 (330 ohm, 5 watt resistor
installed in Step 11). Pass both C8 leads under the two
leads of R2, bend leads of C8 around leads of R2 close to
its body, solder and trim excess lead lengths.
( ) Wrap one lead of R14 around right-hand lead of SCRI and
the other around the right-hand lead of R2. Dress R14
leads as shown on Drawing X-2. BE SURE R14 LEADS DO NOT
SHORT TO OTHER LEADS OF SCRI OR LEAD OF Dl (lN523l).
Solder ONLY the R14-SCRI connection and trim excess lead
length.
REV C
11-13
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
SECTION II
( ) Wrap one lead of R13 around right-hand lead of R2. Physically position R13 parallel to Dl as shown on Drawing X-2.
Solder R13-R14-R2 connection and trim excess lead lengths.
( ) Wrap anode lead of D5 (lN270), the lead opposite the
banded end lead, around anode lead of Dl (lead opposite
banded end lead). Also wrap cathode lead (banded end)
of D5 and loose lead of R13 together. Solder DI-D5 and
D5-R13 connections and trim excess lead lengths.
( ) Check lead dress and inspect for possible shorts and/or
solder bridges.
( ) Refer to Drawing X-2. On the solder (back) side of the
board, the trace that connects R2 to the anode lead of
Dl and the trace that connects the anode lead of Dl to
the right-hand lead (as viewed from front (component)
side of board) of SCRI should have been cut at the factory.
If they were not, cut these two traces as follows:
Using an Xacto knife or razor blade, make two cuts in·
each trace approximately 1/8" apart, cutting across each
trace down to the epoxy base. Insert blade tip beneath
one of the cut sections and gently work it away from the
board. Do the same with the other cut section. Be sure
both "breaks" are free of solder.
( )
Step 21. See Detail A on Drawing X-4 in Section x. Connect
two wire cable assembly (C8 to Regulator Board cable) to regulator. Tin ends without lugs and solder green-white (+ )
lead to pad X2 and white (-) lead to pad X3.
()
Step 22. Test Sol-REG for short circuits. Check for continuity between FWBI
(970-1)
mounting screw and the following points:
(The resistance should be greater than 20 ohms
in all cases.)
X2
T2
Tl
Ql, Emitter
Ql,
Ql,
Dl,
Rl,
Base
Collector
right-hand lead
left-hand lead
D3,
D4,
*D3,
*D4,
top lead
top lead
bottom lead
bottom lead
*Resistance
will be initially low due to C4 and C5, but it
should increase to greater than 20 ohms after a few seconds.
()
2.7.3
Step 23.
Set Sol-REG to one side.
Power Supply Subchassis Assembly and Test
Refer to Drawings X-3 and X-4 in Section X.
()
REV C
Step 24. Mount transformer T2 on power supply subchassis
(L-shaped chassis) .
11-14
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
SECTION II
Position transformer as shown in drawing on Page X-3 and attac
it to the subchassis with three 8-32 x 1/2 binder or pan head
screws, #8 lockwashers and 8-32 hex nuts.
Insert screws from
bottom and outer side of chassis as shown. Place lockwasher
on each screw and secure loosely with hex nuts. Slide transformer as close as possible to the edge of the chassis and
tighten nuts.
NOTE
Only one of the holes in the side wall is
used. Use the one that lines up with the
transformer mounting tab.
()
Step 25.
()
Prepare transformer leads.
Twist two black leads (black and black-red leads and
black-white and black-yellow leads on Sol 20/220 transformer, black and black-yellow leads and black-white and
black-red leads on Sol 20/240 transformer) together except for the last two inches at the commoning block lug
end.
Twist the two green wires together for their full length.
Twist the two yellow wires together for their full length
Twist the two blue wires together for their full length.
()
Step 26. First check that wire color coding in Sol-PC power
cable conforms with that shown in Figure 2-6 on Page 11-21.
Then connect Sol-PC power cable (4-wire cable which connects
to J10 on Sol-PC) to Sol-REG. Tin ends of cable and solder
green lead to pad X9, white lead to pad Xl, red lead to pad
X7 and white-yellow lead to pad X8.
()
Step 27. See Detail C on Drawing X-4. Connect Sol-20 DC
power cable (5-wire) to Sol-REG. Tin ends of cable and soldel
white lead to pad X10 (to right of T3), red-white lead to pad
X5 (between C5 and FWB2) and yellow-white lead to pad x6 (left
of C5) .
()
Step 28.
()
()
REV C
Connect transformer leads to Sol-REG.
See Detail A on Drawing X-4. Solder green leads to pads
Tl and T2, white-yellow lead to pad T3 and yellow leads
to pads T4 and T5 on Sol-REG circuit board.
Step 29. Prethread the three Sol-REG heat sink mounting hole~
in the power supply subchassis shown in drawing on page X-3
with #6 x 5/16 sheet metal screws. Remove screws.
11-15
PROCESSOR TECHNOLOGY CORPORATION
SECTION II
Sol POWER SUPPLY
()
Step 30. Place #4 lockwashers on two 4-40 x 3/16 binder or
pan head screws.
Insert these screws from the bottom side of
the power supply subchassis through the two mounting holes located near the middle of the bottom of the power supply subchassis, one on each side. Drive each screw tightly into a
4-40 x 1/4 tapped spacer.
()
Step 31. Position Sol-REG PC board with top edge over the previously installed spacers. Place #4 lockwashers on two
4-40 x 5/16 binder or pan head screws and drive screws through
Sol-REG board into spacers.
()
Step 32. Attach heat sink on Sol-REG to power supply subchassis as shown in drawing on Page X-3. At this point use only
the two side screws which you used in Step 29 to prethread the
hole~ (The middle screw will be installed later.)
Place a
#6 lockwasher on each screw before driving it through the sink
into the subchassis. Figure 2-4 shows a partially assembled
Sol-20 power supply subchassis.
Figure 2-4.
()
Partially assembled Sol-20 power supply subchassis
assembly.
(Rear of subchassis at left.)
Step 33. Install bridge rectifier FWB3 on power supply subchassis.
(Step 33 continued on Page 11-17.)
REV C
11-16
PROCESSOR TECHNOLOGY CORPORATION
SECTION II
Sol POWER SUPPLY
Position FWB3
(980-1)
on power supply subchassis as shown in
drawing on Page X-3. BE SURE NEGATLVE (-) TEfu~INAL OF
FWB3 is next to transformer. Insert a 6-32 x 3/4 binder or
pan head screw from bottom of subchassis, place #6 lockwasher
on screw and secure with 6-32 hex nut.
Step 34. Connect blue transformer wires to
nals of FWB3.
~arked
termi-
( ) Step 35. Install large (2~") mounting ring for C9 (54,000
ufd capacitor) on side wall of power supply subchassis as
shown in drawing on page X-3.
position ring over the three mounting holes in the side wall
of su~chassis so the clamping screw faces the bottom of subchassis and so it will be accessible from the Sol-REG end of
the subchassis. Insert three 6-32 x ~ binder or pan head
screws from outer side of side wall through the mounting
holes. Place #6 lockwasher on each screw and secure with
6-32 hex nut. Figure 2-5 shows an assembled Sol-20 power
supply subchassis.
Figure 2-5.
Sol-20 power supply subchassis assembly.
(Rear of subchassis at left.)
( ) Step 36. Install small (l~") mounting ring for C8 (18,000
ufd capacitor) as shown in drawing on Page X-3.
(Step 36 continued on Page II-18.)
Rev C
11-17
PROCESSOR TECHNOLOGY CORPORATION
SECTION II
Sol POWER SUPPLY
Position ring over the two mounting holes located between FWB3
and the Sol-REG So that the clamping screw is positioned between the transformer and FWB3. Insert two 6-32 x 1/2 binder
or pan head screws from bottom side of chassis through the
mounting holes. Place #6 lockwasher on each screw and secure
with 6-32 hex nut.
(Refer to Figure 2-4.)
()
Step 37. Route Sol-PC power cable between cs mounting ring
and the transformer, mount cs in its mounting ring, and tighten
clamping screw.
(See Figure 2-4.)
()
Step 3S. See Detail A on Drawing X-4. Connect white wire of
CS cable to negative (-) terminal of CS and green-white wire
to positive (+) terminal of CS.
(This cable was soldered to
the Sol-REG when you assembled it.)
Remove terminal screws
and lockwashers, place cable lugs on screws and drive screws
tightly into appropriate terminals.
()
Step 39. Mount C9 in its mounting ring with its n+n terminal
slightly toward CS and tighten clamping screw.
(See Figure
2-5. )
()
Step 40.
Prepare R13 (39 ohm 2 watt) for installation on C9.
Solder a #10 lug to each lead of R13. Bend leads of R13 to
fit the terminals of C9.
(R13 should fit on C9 as shown in
Figure 2-5.)
()
Step 41. First check that wire color coding in Sol-20 DC
power cable conforms with that shown in Figure 2-7 on Page
II-2l. See Figure 2-5. Connect Sol-20 DC power cable (5-wire)
and R13 to C9. Route cable between CS and transformer.
See Drawing X-3. Remove terminal screws from C9. Place lockwasher,terminal screw, blue lead of Sol-20 DC cable and one
R13 lead on one terminal screw and drive it into the positive
(+) terminal on C9. Attach lockwasher, white cable lead and
other R13 lead to negative (-) terminal on C9 in the same manner. Tighten both capacitor terminals tightly.
CAUTION
LOOSE CONNECTIONS ON C9 CAN LEAD TO ARCING AND SUBSEQUENT POWER SUPPLY DAMAGE.
()
REV C
Step 42. See Detail C on Drawing X-4. Connect blue pigtail
of Sol-20 DC cable to positive (+) terminal of FWB3.
(This
pigtail has a spade lug at its free end and is connected to
the lug you just attached to the positive terminal of C9.)
Connect white pigtail of Sol-20 DC cable to negative (-) terminal of FWB3.
(This pigtail has a spade lug at its free end
and is connected to the lug you just attached to the negative
terminal of C9.)
II-IS
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
SECTION II
()
Step 43. Connect green lead from AC receptacle (mounted on fan
closure plate) to power supply subchassis assembly.
(Use the
#6 x 5/16" sheet metal screw with which you prethreaded the
middle Sol-REG heat sink mounting hole in Step 29.)
Place
lug on screw and drive screw into the middle Sol-REG heat sink
mounting hole.
()
Step 44. Route transformer T2 primary leads along side wall
of power supply subchassis out toward the Sol-REG heat sink.
(See Figure 2-4.)
If you ordered your Sol for 110 V ac operation, T2 will have two black primary leads. If you ordered
your Sol for 220 or 240 V ac operation, T2 will have one black,
one black-red, one black-yellow and one black-white lead. Connect the primary leads of T2 as follows:
()
()
110 V ac Operation. Refer to Detail Bl on Drawing X-4 in
Section X. Connect one black lead of T2 to pin 2 of commoning block TBI (nearest to fan).
Connect other black
lead to pin 3 of other commoning block (TB2).
()
220 V ac Operation. Refer to Detail B2 on Drawing X-4
in Section X. Connect black-yellow lead of T2 to pin 2
and black-white lead to pin 4 of commoning block TBI
(nearest to fan).
Connect black-red lead to pin 1 and
black lead to pin 5 of other commoning block (TB2).
()
240 V ac Operation. Refer to Detail B3 on Drawing X-4
in Section x. Connect black-red lead to pin 2 and blackwhite lead to pin 4 of commoning block TBI (nearest to
fan).
Connect black-yellow lead to pin 1 and black lead
to pin 5 of other commoning block (TB2).
Step 45.
Install cable tie wraps.
()
Install one wrap around the wires that connect to Sol-REG
pads Tl,2,3,X2 and X3 as shown in the Detail A
Wiring
portion of the drawing on Page X-4.
()
Install another wrap around the leads from C9 as shown in
Detail C of drawing on Page X-4.
Two other wraps are supplied with your kit. Use them as
appropriate to make your power supply cabling neater.
()
Step 46. Using a #6 x 5/16 sheet metal screw, attach fan
closure plate to power supply subchassis as shown in Drawing
X-3.
()
Step 47. Push on-off switch in and out to determine the OFF
position (switch mechanically out). With switch in OFF position, connect AC power cord to AC receptacle.
REV C
II-19
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
()
Step 48.
SECTION II
Test power supply for proper operation.
Make sure on-off switch is in OFF position.
Install fuse in fuse holder.
REMOVE FUSE WITH POWER ON.
CAUTION:
NEVER INSTALL OR
( )
Check connector on Sol-PC power cable (4-wire) to insure
it is wired as shown in Figure 2-6.
( )
Check connector on Sol-20 power cable (5-wire) to insure
it is wired as shown in Figure 2-7.
)
Plug power cord into 110 V ac outlet.
Turn on-off switch ON.
Fan should start.
Measure the voltages at the Sol-PC connector at the points
indicated in Figure 2-6. The voltages must be as given
in Figure 2-6. NOTE: Do not take voltage measurements
at any other points in the power supply, even though they
may be more accessible.
It is important that the indicator voltages be available at the connector.
()
Measure the voltages at the Sol-20 connector at the poin
indicated in Figure 2-7. The voltages must be within the
ranges given in Figure 2-7.
(See preceding NOTE.)
()
If the power supply fails any of the preceding tests,
locate and correct the cause before proceeding.
If the power supply is operating correctly, turn on-off switch
OFF, disconnect power cord, set power supply to one side and
go on to Section III.
REV C
1I-20
PROCESSOR TECHNOLOGY CORPORATION
Sol POWER SUPPLY
SECTION II
1----1-----
Red
1-----
White/Yellow
1----_.-
(
1------
Green
(
White (Ground)
Figure 2-6.
f- - - - -
Red/White
-----'
Blue
------
White (Gnd 1)
-----
White (Gnd 2)
1-----
REV B
~
,
I
+5 V de
(+ .25 V)
-12 V de
(±. .6 V)
+12 V de
(+ .6 V)
Sol-PC power connector and voltage measurements.
Yellow/White
Figure 2-7.
(
I(
E
I
:
~
-18 to -23 V de
+18 to +23 V de
?
I
I
+7.5 to 11 V de
j
Sol-20 power connector and voltage measurements.
II-21
III
Sol-PC ASSEMBLY and TEST
3.1
Parts and Components.
III-l
3.2
Assembly Tips . • • . • .
III-l
3.3
Assembly Precautions • .
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
....
Handling MOS Integrated Circuits . . . . . .
Soldering . . • . . • . • • . .
Power Connection (JlO) . • . . . • • . . • .
Installing and Removing Integrated Circuits.
Installing and Removing Personality Module .
Use of Clip Leads.
••..•.
. •.
1II-9
1II-9
1II-9
1II-9
1II-9
1II-9
III-IO
3.4
Required Tools, Equipment and Materials .
III-IO
3.5
Orientation (Sol-PCB)
III-IO
3.6
Sol-PC Assembly-Test Procedure • •
III-IO
3.6.1
3.6.2
3.6.3
III-II
III-12
III-12
3.7
. •
Circuit Board Check. • • • • • .
Personality Module Assembly . • . . . . .
Sol-PCB AS,sembly and Test.
.•...•.
Options • .
3.7.1
3.7.2
REV A
".
. •
625 Line Video, 50 Hz. . • • • • . . • • • •
Vectored Interrupt
.•..•.
.••
1II-43
1II-43
1II-44
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
3.1
SECTION III
PARTS AND COMPONENTS
You will need the parts listed in Table 3-1 to assemble your
Sol-PC. Select and separate the needed parts from those supplied with
your Sol kit before starting assembly. If you have any difficulty in
identifying any parts by sight, refer to Figure 3-1 and the "Standard
Color Code for Resistors and Capacitors" chart in Appendix III. Table
3-1 lists each part, its description, quantity and reference designation on the drawing(s) you will use in assembling the Sol-PC. The
assembly drawings in Section X will also prove useful in identifying
parts.
3.2
ASSEMBLY TIPS
1. Scan Sections III and IV in their entirety before you
start to assemble your Sol-PC kit.
2. In assembling your Sol-PC, you will be following an integrated assembly-test procedure. Such a procedure is designed to progressively insure that individual circuits and sections in the Sol-PC
are operating correctly.
IT IS IMPORTANT THAT YOU FOLLOW THE STEP-BYSTEP INSTRUCTIONS IN THE ORDER GIVEN.
3. Assembly steps and component installations are preceded by
a set of parentheses. Check off each installation and step as you
complete them. This will minimize the chances of omitting a step or
component.
4. When installing components, make use of the assembly aids
that are incorporated on the circuit boards and the assembly drawings.
(These aids are designed to assist you in correctly installing the
components.)
a.
The circuit reference (R3, CIO and U20, for example) for
each component is silk screened on the PC boards near the
location of its installation.
b.
Both the circuit reference and value or nomenclature
(1.5K and 74HOO, for example) for each component are included on the assembly drawings near the location of its
installation.
5. To simplify reading resistor values after installation,
install resistors so that the color codes or imprints read from left
to right .and top to bottom as appropriate (boards oriented as defined
in Paragraph 3.5 on Page 111-10).
6. Unless specified otherwise, install components, especially
disc capacitors, as close as possible to the boards.
7. Should you encounter any problem during assembly, calIon
us for help if needed.
REV A
111-1
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Table 3-1.
SECTION III
Sol-PC Parts List.
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
Circuit Board
Sol-PC
1
IC
0026 or 75369
1
X-5
UI04
IC
4N26
1
X-5
U39
IC
1458 at' 72558
2
X-5
U56&108
IC
1489 or 75189
1
X-5
U38
IC
4001 or 14001
1
X-5
UI02
IC
4013 or 1413
2
X-5
UI00&113
Ie
4019
1
X-5
Ull1
Ie
4023 or 14023
1
x-5
U98
IC
4024 or 14024
1
X-5
U86
IC
4027 or 14027
1
x-5
UI0l
IC
4029
3
X-5
Ul,11&84
IC
4030
1
X-5
U99
IC
4046 or 14046
2
X-5
U85&110
IC
4049 or 14049
2
x-5
U88&109
IC
4520 or 14520
1
x-5
U112
IC
6011, 1602, 2017 or 1013
2
X-5
U51&69
IC
6574 or 6575
1
x-5
U25
IC
74HOO
1
X-5
U91
IC
74LSOO
3
x-5
U44,48&55
IC
74LS02 or 9LS02
2
X-5
U53&60
IC
74LS04
4
X-5
U24,45,
49&54
IC
74S04
1
X-5
U92
IC
7406
2
X-5
U57&87
IC
74LSI0
2
X-5
U47&61
IC
74LS20
3
X-5
U23,59&83
IC
74LS86
1
X-5
U74
IC
74LSI09
8
X-5
U43,52,63,
64,70,72,
73&75
REV A
1II-2
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Table 3-1.
SECTION III
Sol-PC Parts Lists.
(Continued)
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
IC
74LS136
1
X-5
U22
IC
74LS138
3
X-5
U34,35&36
IC
74LS157
3
x-5
U12,30&32
IC
74LS163 or 25LS163
4
X-5
U28,31,
33&40
IC
74166
1
X-5
U41
IC
74173 or 8TI0
2
X-5
U95&96
IC
74175
1
x-5
U97
IC
74LS175 or 25LS175
9
X-5
U2,13,26,27,
42,-76,90,
93&106
IC
74LS253
4
X-5
IC
74LS367
7
x-5
U29,37,50,
71,89,94
&107
IC
8T94
1
X-5
U58
IC
8T97, 8097 or 74367
5
X-5
U67,68,77,
80&81
IC
8T380 or 8836
1
X-5
U46
IC
8080A, 9080 or 8080
1
X-5
UI05
IC
91L02, 2102 or 21L02
16
x-5
IC
93L16
1
X-5
U62
Transistor
2N2222
2
X-5
Q4&5
Transistor
2N2907
2
X-5
Ql&2
Transistor
2N4360
1
X-5
Q3
Diode
IN4001
4
X-5
D2,12,
13&14
Diode
IN4148 or IN914
9
X-5
Dl &
D3 thru 10
Diode
IN5231
1
X-5
Dll
Crystal
14.31818 MHz
1
X-5
XTAL
REV A
111-3
U65,66,
78&79
U3 thru 10
& 14 thru 21
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Table 3-1.
SECTION III
Sol-PC Parts Lists.
(Continued)
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
Relay
DIP, 500 ohm Reed
2
X-5
Kl&2
Resistor
6.8 ohm, 1/2 W, 5%
2
X-5
R155&156
Resistor
47 ohm, 1/4 W, 5%
3
x-5
R137,138
&160
Resistor
75 ohm, 1/4 W, 5%
1
X-5
R81
Resistor
100 ohm, 1/4 W, 5%
1
x-5
R149
Resistor
100 ohm, 1/2 W, 5%
3
X-5
RBI,
132&133
Resistor
200 ohm, 1/4 W, 5%
1
X-5
R82
Resistor
270 ohm, 1/4 W, 5%
1
X-5
R21
Resistor
330 ohm, 1/4 W, 5%
13
X-5
R45,58,
64 thru 71,
87,133&134
Resistor
330 ohm, 1/2 W, 5%
1
X-5
R80
Resistor
470 ohm, 1/4 W, 5%
1
X-5
R150
Resistor
470 ohm, 1/2 W, 5%
2
X-5
R22&23
Resistor
680 ohm, 1/4 W, 5%
9
x-5
R72 thru
79&88
Resistor
1. 5K ohm, 1/4 W, 5%
63
X-5
Rl thru 17,
19,20,24,
30 thru 38,
40 thru 44,
49 thru 57,
59 thru 61,
83,85,86,
89,90,93,
96,97,99,
101,105,106,
115,116,124
&125
Resistor
3.3K ohm, 1/4 W, 5%
1
x-5
R128
Resistor
4.7K ohm, 1/4 W, 5%
1
X-5
R27
Resistor
5.6K ohm, 1/4 W, 5%
6
X-5
R39,46,62,
63,92&151
REV A
111-4
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Table 3-1.
SECTION III
Sol-PC Parts Lists.
(Continued)
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
Resistor
10K ohm, 1/4 W, 5%
31
X-5
Resistor
15K ohm, 1/4 W, 5%
2
X-5
R29&95
Resistor
39K ohm, 1/4 W, 5%
2
X-5
R123&126
Resistor
47K ohm, 1/4 W, 5%
2
X-5
R144&154
Resistor
50K ohm, Variable
2
X-5
VRl&2
Resistor
lOOK ohm, 1/4 W, 5%
3
X-5
R120,
148&153
Resistor
lOOK ohm, Variable
1
X-5
VR3
Resistor
150K ohm, 1/4 W, 5%
2
X-5
R141&152
Resistor
1M ohm, 1/4 W, 5%
2
X-5
R139&143
Resistor
2.2M ohm, 1/4 W, 5%
1
x-5
R147
Resistor
3.3M ohm, 1/4 W, 5%
2
X-5
R84&102
Capacitor
10 pf, Disc Ceramic
1
X-5
C64
Capacitor
330 pf, Disc Ceramic
1
x-5
C30
Capacitor
470pf, Disc Ceramic
1
X-5
C74
Capacitor
680 pf, Disc Ceramic
3
X-5
C34,43
&44
Capacitor
.001 ].1f, Disc Ceramic
6
x-5
C47,49,
54,55,
61&71
Capacitor
.001 ].1f, Mylar
2
X-5
C52&72
Capacitor
.01 ].1£, Mylar
2
X-5
C50&53
REV A
111-5
R18,25,26,
28,47,48,94,
98,100,104,
107 thru 114,
117 thru 119,
121,122,127,
129,135,136,
140,142,
145&146
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Table 3-1.
SECTION III
Sol-PC Parts Lists.
(Continued)
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
Capacitor
.047 11f, Disc Ceramic
37
X-5
Cl thru 14,
16 thru 28,
33,38,41,
42,45,46,
48,56,
65&73
Capacitor
.1 11f, Disc Ceramic
12
X-5
C29,32,36,
37,39,51,57,
63,66,68,
69&70
Capacitor
.1 11f, Mylar
1
X-5
C35
Capacitor
.68 11f, Mono Ceramic
1
X-5
C62
Capacitor
1 11f, Tantalum
1
X-5
C67
Capacitor
15 11f, Tantalum
5
X-5
Capacitor
100 11f, Aluminum
1
X-5
C31
Socket
DIP, 8-pin
2
X-5
U56&108
Socket
DIP, 14-pin
29
X-5
U22 thru 24,
38,44 thru 49,
53 thru 55,
57 thru 61,
74,83,86,87,
91,92,98
thru 100,102,
&113
Socket
DIP, 16-pin
74
X-5
Ul thru 21,
26 thru 37,
40 thru 43,
50,52
62 thru 68,
70 thru 73,
75 thru 81,
84,85,
88 thru 90,
93 thru 97,
101,106,
107 &
109 thru 112
REV A
111-6
C15,40
58,59&60
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Table 3-1.
SECTION III
Sol-PC Parts Lists.
(Continued)
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
Socket
DIP, 24-pin
1
X-5
Socket
DIP, 40-pin
3
X-5
U51,69&105
Socket
Female, 25-pin
1
X-5
J1
Socket
Male, 25-pin
1
X-5
J2
Socket
Phone Jack, Miniature
2
X-5
J6&7
Socket
Phone Jack, Subminiature
2
X-5
J8&9
Header
Male, 20-pin
2
X-5
J3&4
Header
Male, 7-pin
1
x-5
J10
Connector
PC, 100-pin
1
x-5
J11
Connector
PC, 30-pin
1
X-5
J5
Switch
DIP, 6 Section
2
X-5
Sl&4
Switch
DIP, 8 Section
2
X-5
S2&3
Cable
Coax, 75 ohm
33"
X-6
2
Cable Tie
Plastic
1
X-6
129
Tubing
PVC
3"
Bracket
Mounting, Sol-PC, 2"
2
X-6
4
Card Guide
2-1/2"
2
X-6
128
Pins
Augat
Screw
Machine, 4-40 x 1/4
4
X-6
122
Screw
Machine, 4-40 x 7/16
6
X-6
124
Screw
Machine, 4-40 x 5/8
2
X-6
125
Washer
Nylon, #4
2
X-6
127
Lockwasher
Internal Tooth, #4
10
X-6
126
Hex Nut
4-40
10
X-6
123
Wire
24 AWG
Solder
60/40, 20 SWG
Power Supply
Sol-20
1
Assembly
Keyboard
1
Assembly*
2708/9216 Personality Modu1e*
1*
*Not
15
1'6"
needed until Step 50 of Sol-PC assembly.
REV A
U25
111-7
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
Monolythic (left)
and Ceramic Disc
Capacitors
c
"
f
C
Transistor
TO-18 Package (Metal Can)
Transistor
TO-92 Package (Plastic)
Mylar Tubular
Capacitor
Dipped Tantalum
Electrolytic Capacitor
/l.s PowerRegulator
IC or
Transistor (TO-220)
~-,---~ ~ ~l
Electrolytic
Capacitor
(vertical mount)
Metal Film 1%
Precision Resist=o;r~~~~~~~
lIIore.: PIN 1. t'Orw 9e:
,...
c
Carbon Film Resistor
5% (gold), l~~ (silver)
Figure 3-1.
euT-ou~
Dual Inline Package (DIP) IC
(8,14,16,24 or 40 pins)
Identification of components.
111-8
I~DICA't"'D
CJ)""I.I~R. Do'1"
e ""
PROCESSOR TECHNOLOGY CORPORATION
SECTION III
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
3.3
ASSEMBLY PRECAUTIONS
3.3.1
Handling MOS Integrated Circuits
Many of the IC's used in the Sol-PC are MOS devices. They can
be damaged by static electricity discharge. Always handle MOS IC's
so tha·t no discharqe will flow throuqh the IC. Also, avoid unnecessary handling and wear cotton--rather than synthetic--clothing when
you do handle these IC's.
3.3.2
Soldering
1.
**IMPORTANT**
Use a fine tip, low-wattage iron, 25 watts maximum.
2. DO NOT use excessive amounts of solder.
and as quickly as possible.
3. Use only 60-40 rosin-core solder.
solder or externally applied fluxes.
DO solder neatly
NEVER use acid-core
4. To prevent solder bridges, position iron tip so that it
does not touch adjacent pins and/or traces simultaneously.
5. DO NOT press tip of iron on pad or trace. To do so can
cause the pad or trace to "lift" off the board and permanently damage
the board.
6. The Sol-PC uses circuit boards with plated-through holes.
Solder flow through to the component (front) side of the board can
produce solder bridges. Check for such bridges after you install
each component.
7. The Sol-PC circuit boards have integral solder masks (a
lacquer coating) that shield selected areas on the boards. This mask
minimizes the chances of creating solder bridges during assembly. DO,
however, check all solder joints for possible bridges.
8 •. Additional pointers on soldering are provided in Appendix
IV of this manual.
3.3.3
Power Connection (JIO)
NEVER connect the DC power cable to the Sol-PC when power
supply is energized. To do so can damage the Sol-PC.
3.3.4
Installing and Removing Integrated Circuits
NEVER install or remove integrated circuits when power is
applied to the Sol-PC. To do so can damage the IC.
3.3.5
Installing and Removing Personality Module
NEVER install or remove the plug-in personality module when
power is applied to the Sol-PC. To do so can damage the module.
Rev A
111- 9
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
3.3.6
SECTION III
Use of Clip Leads
TAKE CARE when using a clip lead to establish a ground conn.ection when testing the Sol-PCB circuit board. Make sure that the clip
makes contact only with the ground bus on the perimeter of the board.
3.4
REQUIRED TOOLS, EQUIPMENT AND MATERIALS
The following tools, equipment and materials are recommeded
for assembling and testing the Sol-PC:
3.5
1.
Needle nose pliers
2.
Diagonal cutters
3.
Screwdriver
4.
Sharp knife
5.
Controlled heat soldering iron, 25 watt
6.
Volt-ohm meter
7.
Video monitor or monochrome TV converted for video input
8.
IC test clip (optional)
9.
Oscilloscope with calibrated time base
ORIENTATION (Sol-PCB)
Location J5 (personality plug-in module connector) will be located in the upper right-hand area of the circuit board when location
JlO (power connector) is positioned at the bottom of the board. In
this position the component (front) side of the board is facing up
and all IC legends (Ul through UlO, U22 through U24, etc.) will read
from left to right. Subsequent position references related to the
Sol-PCB assume this orientation.
3.6
Sol-PC ASSEMBLY-TEST PROCEDURE
The Sol-PC is assembled and tested in sections and/or circuits.
You will first test the Sol-PCB circuit board for shorts (solder
bridges) between the power buses and ground.
After assembling
REV A
111-10
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
the personality module (see Section IV), the clock and display control
circuits are assembled. The bus, CPU, decoder and memory circuits are
then assembled, followed by the parallel and serial input/output (I/O)
and audio cassette I/O sections.
CAUTION
THE Sol-PC USES MANY MOS INTEGRATED
CIRCUITS. THEY CAN BE DAMAGED BY
STATIC ELECTRICITY DISCHARGE. HANDLE
THESE IC's SO THAT NO DISCHARGE FLOWS
THROUGH THE IC.
AVOID UNNECESSARY
HANDLING AND WEAR COTTON, RATHER THAN
SYNTHETIC, CLOTHING WHEN YOU DO HANDLE
MOS IC's.
(STATIC CHARGE PROBLEMS ARE
MUCH WORSE IN LOW HUMIDITY CONDITIONS.)
3.6.1
Circuit Board Check
Visually check Sol-PCB board for sold~r bridges (shorts)
between traces, broken traces and similar defects.
Check board to insure that the +5-volt-bus, +12 volt-bus
and -12-volt bus are not shorted to each other or to
ground. Using an ohmmeter, on "OHMS X lK" or "OHMS X 10K"
scale, make the following measurements (refer to Sol-PC
Assembly Drawing X-3) .
( ) +S-vo1t Bus Test. Measure between positive and negative mounting pads for CS8.
There should be no
continuity. (Meter reads close to "infinity" ohms.)
( ) +12-volt Bus Test. Measure between positive and negative mounting pads for CS9.
There should be no
continuity.
( ) -12-vo1t Bus Test. Measure between positive and negative mounting pads for C60.
There should be no
continuity.
( ) 5/12/(-12) Volt Bus Test. Measure between positive
mounting pads for CS8 and. CS9, between positive pad
for CS8 and negative pad for C60, and between positive pad for CS9 and negative pad for C60. You should
measure no continuity in any of these measurements.
If visual inspection reveals any defects, or you measure
continuity in any of the preceding tests, return the
board to Processor Technology for replacement.
If the
board is not defective, proceed to next paragraph.
Rev A
111-11
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
3.6.2
SECTION III
Personality Module Assembly
Since the personality module is required for testing the S01PC in the later stages of its assembly, we suggest that you assemble
the personality module first.
In so doing, your Sol-PC assembly will
proceed uninterrupted. Assembly instructions for the personality
module are provided in Section IV of this manual.
If you wish to wait to assemble the personality module until
it is needed, go on to Paragraph 3.6.3.
3.6.3
Sol-PCB Assembly and Test
Refer to Sol-PC assembly drawings X-5 and X-6.
( ) Step 1. Install DIP sockets. Install each socket in the indicated location with its end rrotch oriented as shown Qg the
circuit board ang assembly drawing. Take care not to create
solder bridges between the pins and/or traces.
(Refer to
footnotes at end of this step before installing UIOS.)
INSTALLATION TIP
Insert socket pins into mounting pads of
appropriate location. On solder (back)
side of board, bend pins at opposite corners of socket (e.g., pins 1 and 9 on a
16-pin socket) outward until they are at
a 45° angle to the board surface. This
secures the socket until it is soldered.
Repeat this procedure with each socket
until all are secured to the board. Then
solder the unbent pins on all sockets.
Now straighten the bent pins to their
original position and solder.
LOCATION
(
(
(
(
(
(
(
(
(
(
(
(
(
(
)
)
)
)
)
)
)
)
)
)
)
)
)
)
Ul through 21
U22 through 24
U2S
U26 through 37
U38
U39
U40 through 43
U44 through 49
USO
uSl
US2
US3 through 55
uS6
uS7 through 61
TYPE SOCKE±:
16 pin
14 pin
24 pin
16 pin
14 pin
None
16 pin
14 pin
16 pin
·40 pin
16 pin
14 pin
8 pin
14 pin
(Continued on Page 111-13. )
REV C
TII-12
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL CO~PUTERTM
SECTION III
TYPE SOCKET
LOCATIO~
(
(
(
) U62 through 68
) U69*
) U70 through 73
(
(
(
(
(
(
)
(
(
)
)
)
)
)
)
(
)
)
(
(
(
)
)
(
(
(
(
(
(
(
)
)
)
)
)
)
)
)
16 pin
40 pin
16 pin
U74
14 pin
16 pin
U75 through 81
None#
U82#
14 pin
U83
U84,85
16 pin
U86,87
14 pin
U88 through 90
16 pin
U91,92
14 pin
16 pin
U93 through 97
14 pin
U98 through 100
16 pin
UIOI
14 pin
Ul02
None #
UI03#
None
UI04
UI05**
40 pin
UI06,l07
16 pin
UI08
8 pin
Ul09 through 112
16 pin
Ul13
14 pin
*Especially make sure you solder pin 40.
.
#Spare locations, not used.
**Note that UI05 notch is positioned at the top.
( ) Step 2. Install the following capacitors in the indicated
locations. Take care to observe the proper value, type and
orientation, if applicable, for each installation. Bend
leads outward on solder (back) side of board, solder and
trim.
NOTE
Disc capacitor leads are usually coated
with wax during the manufacturin~ process. After inserting leads through
mounting holes, remove capacitor and
clear the holes of any wax. Reinsert
and install.
LOCATION
(
(
(
(
(
(
(
(
REV A
)
)
)
)
)
)
)
)
Cl
C2
C3
C4
C5
C6
C7
C8
VALUE (ufd)
TYPE
.047
.047
.047
.047
.047
.047
.047
.047
Disc
111-13
ORIENTATION
None
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
LOCATION
( )
(
)
( )
(
(
(
)
)
)
(
CIO
Cll
C13
C14
C15
C16
VALUE (ufd)
.047
.047
.047
.047
15
.047
SECTION III
ORIENTATION
Disc
None
"
"
"
"
"
II
Tantalum
Disc
"+" lead bottom
None
Step 3. Check for +5-volt bus to ground shorts. Using an
ohmmeter, measure between positive and negative mounting
pads for C58. There should be no continuity. If there is,
find and correct the problem before proceeding to Step 4.
( ) Step 4. Install the following capacitors in the indicated
locations. Take care to observe the proper value, type and
orientation, if applicable, for each installation.
Bend
leads outward on solder (back) side of board, solder and
trim.
(refer to NOTE in Step 2.)
LOCATION
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
(
C19
C20
C21
C24
C25
C26
C33
C38
C40
C41
C42
C45
C56
C58
c59
C60
C65
VALUE (ufd)
.047
.047
.047
.047
.047
.047
.047
.047
15
.047
.047
.047
.047
15
15
15
.047
rYPE
ORIENTATION
Disc
None
"
"
"
"
"
"
"
II
II
Tantalum
Disc
"
"
II
II
II
11+11 lead bottom
None
II
II
II
II
II
II
Tantalum
Tantalum
Tantalum
Disc
"+11 lead top
11+11 lead top
11+11 lead top
None
Step 5. Check for +5-volt bus to ground shorts. Using an
ohmmeter, measure between the positive and negative leads of
C58. You should measure at least 100 ohms. Less than 100
ohms indicates a short. If required, find and correct the
problem before proceeding to Step 6. NOTE: In this and
subsequent resistance measurements, any value greater than
the minimum may normally occur, even much higher, unless
otherwise indicated.
( ) Step 6. Install the following capacitors in the indicated
locations. Take care to observe the proper value and type
for each installation. Bend leads outward on solder (back)
side of board, solder and trim.
(Refer to NOTE in Step 2.)
(Step 6 continued on Page 111-15.)
Rev A
111-14
PROCESSOR TECHNOLOGY CORPORATION
SECTION III
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
LOCATION
VALUE (ufd)
C9
Cl2
Cl7
Cl8
C22
C23
C27
C28
C46
(
(
(
(
(
(
(
(
(
.047
.047
.047
.047
.047
.047
.047
.047
.047
TYPE
ORIENTATION
Disc
None
II
II
II
II
II
II
II
II
Step 7. Check for +S-volt bus to ground shorts. Using an
ohmmeter, measure between the positive and negative leads of
CS8. You should measure some resistance. Zero resistance
indicates a short. If required, find and correct the problem
before proceeding to Step 8.
( )
st~.
Install diodes D8 (lN4148 or lN914), Dll (lNS231)
and D12 (lN4001) in their locations (in the area below U90
through U92). Position D8 with its dark band (cathode) to
the right, Dll with its band at the bottom, and D12 with
its band at the top.
( ) step 9. Install the following resistors in the indicated
locations. Bend leads to fit distance between mounting
holes, insert leads, pull down snug to board, solder and
trim.
LOCATION
(
)
)
( )
( )
( )
( )
( )
( )
( )
( )
(
RI04
RIOS
RI06
R130
R131
R132
R133
R134
R13S
R137
&
&
136
138
VALUE (ohms)
COLOR CODE
10 K
1.SK
1.SK
100, !z watt
100, !z watt
100, !z watt
330
330
10 K
47
brown-black-orange
brown-green-red
II
II
II
brown-black-brown
II
II
II
II
II
II
orange-orange-brown
II
II
II
brown-black-orange
yellow-violet-black
Step 10. Install the following capacitors in the indicated
locations. Take care to observe the proper value and type
for each installation. Bend leads outward on solder (back)
side of board, solder and trim.
(Refer to NOTE in Step 2.)
REV A
111--15
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
LOCATION
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
SECTION III
VALUE
C39
C43
C44
C6l
C62
C63
C64
TYPE
.1
ufd
pfd
pfd
.001 ufd
.68 ufd
.1
ufd
10
pfd
Disc
Monolythic or Disc
Monolythic or Disc
Disc
Monolythic
Disc
Disc
680
680
) Ste:Q 11.
Install 14.318 MHz crystal in its location just
above C6l. Insert leads and pull down until the case is
1/16 11 above .the front surface of the board. Solder quickly
and trim.
( ) Step 12. Install male Molex connector in location
JIO. Position connector so the locking clip is next to
the crystal (XTAL), insert shorter pins in mounting
holes and solder.
( ) Ste:Q 13. In the jumper area labeled CLK on the assembly
drawing (between U90 and U9l), install Augat pins in mounting holes A,B,C,D and E.
(Refer to IIInstalling Augat Pins ll
in Appendix IV.) Using #24 bare wire, install a jumper between the A and B pins and another jumper between the D and
E pins. DO NOT SOLDER JUMPERS TO AUGAT PINS.
( ) Step 14. Install the following IC's in the indicated locations. Pay careful attention to the proper orientation. DO
NOT SUBSTITUTE FOR ANY OF THESE IC's.
Dots on the assembly drawing and PC board
indicate the location of pin 1 of each IC.
IC NO.
(
(
(
(
(
)
)
)
)
)
U77
U90
U9l*
U92*
Ul04**
TYPE
8T97 , 8097 or 74367
74LS175 or 25LS175
74HOO*
74S04*
0026 or 72558*
*Take care not to interchange these.
**Solder this Ie in its location.
See IILoading DIP Devices" in
Appendix IV.
()
Step 15. Connect power to power connector JlO.
interconnection requirements are as follows:
(Step 15 continued on Page 111-17.)
REV A
111-16
Power and
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
CAUTION 1
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A. CLEAN NONCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
CAUTION 2
NEVER CONNECT POWER CABLE TO JIO WITH
POWER SUPPLY ENERGIZED.
CAUTION 3
MAKE SURE POWER CABLE CONNECTOR MATES
EXACTLY WITH JIO.
IF CONNECTOR AND
JIO ARE OFFSET (e.g., PIN 2 CONNECTED
TO PIN 1, 3 TO 2, ETC.), THE IC'S
WILL "BLOW".
JIO PIN NO.
o
1°1
0
0
0
0
°1
2 345 6 7
(JI0, Top View)
1
2 and 6
3 and 5
4
7
POWER
Ground
+5 V dc +5%, 2 A max
-12 V dc +5%, 300 rnA max
+12 V dc +5%, 100 rnA max
Ground
NOTE
Though not labeled on the connector, JlO
pins are designated 1 through 7, reading
from left to right.
()
Step 16. Check clock circuits.
( ) Using an oscilloscope, check for the waveforms given in
Figure 3-2 on Page 111-18 at the indicated observation
points and in the. order given. The waveforms shown in
Figure 3-2 approximate actual waveforms.
If any waveforms
are incorrect, determine and correct the cause before
proceeding with assembly.
( ) Turn off power supply and disconnect power connector.
REV A l l t - 1 7
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
CHECK POINT
SIGNAL
(
)
U77,
Pin 7
Oscillator
Output
(
)
U9l,
Pin 6
Clock
Divider
Output
(
)
U9l,
Pin 11
SECTION III
Clock
Divider
Output
WAVEFORM
(This is not
14.3 MHz square wave.
a perfect square wave. It in fact
more resembles a poor sine wave.)
4V
U91, PIN 6
140"0
Ul04,
Pin 7
CPU
Clock
4V
U91, PIN II
I
210ns
Ul04,
Pin 5
CPU
Clock
~2
Figure 3-2.
REV A
280ns
GND
U104,PIN7
fin
( )
I
350ns
GND
12V
( )
I
140"0
GND
I
350ns
12VI
U104,PIN5
210ns
GND
Clock circuit waveforms.
111-18
280ns
I
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
( ) Step 17. Install the following resistors in the indicated
locations. Bend leads to fit distance between mounting holes,
insert leads, pull down snug to board, solder and trim.
LOCATION
VALUE (ohms)
COLOR CODE
( ) Rl
1.5K
brown-green-red
( ) R2
1.5K
"
( ) R3
1.5K
( ) R4
1.5K
( ) R5
1.5K
( ) R6
1.5K
( ) R7
1.5K
( ) R8
1.5K
( ) R9
1.5K
( ) RIO
1.5K
( ) Rll
1.5K
( ) R16
1.5K
( ) R17
1.5K
( ) R19
1.5K
"
( ) R30
1.5K
"
( ) R80
330, ~ watt
orange-orange-brown
( ) R81
75
violet-green-black
200
( ) R82
red-black-brown
( ) R83
1.5K
brown-green-red
( ) R84
3.3M
orange-orange-green
( ) R85
1.5K
brown-green-red
( ) R86
1.5K
"
"
"
( ) R87
330
orange-orange-brown
( ) R88
680
blue-gray-brown
( ) R89
1.5K
brown-green-red
( ) R90
1.5K
"
"
"
( ) R96
1.5K
"
"
"
( ) R97
1.5K
"
"
"
( ) R98
10 K
brown-black-orange
1.5K
( ) R99
brown-green-red
( ) RIOO
10 K
brown-black-orange
1.5K
( ) RIOI
brown-green-red
( ) RI02
3.3M
orange-orange-green
( ) RI03.
1.5K
brown-green-red
( ) R120
100 K
brown-black-yellow
10 K
( ) R121
brown-black-orange
( ) R122
10 K
"
"
"
39 K
( ) R123
orange-white-orange
( ) R124
1.5K
brown-green-red
( ) R125
1.5K
"
"
"
( ) R126
39 K
orange-white-orange
10 K
( ) R127
brown-black-orang~
( ) R128
3~3K
orange~orange-red
( ) R129
10 K
brown-black-orange
Potentiometer
50 K
( ) VRI & VR2
REV B
111-19
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
. ( ) Step 18. Install the following capacitors in the indicated
locations. Take care to observe the proper value and type
for each installation. Bend leads outward on solder (back)
side of board, solder and trim.
(Refer to NOTE in Step 2.)
CAUTION
REFER TO FOOTNOTE AT END OF THIS STEP BEFORE
INSTALLING C3l.
LOCATION
(
(
(
(
(
(
(
(
(
(
(
)
)
)
)
)
)
)
)
)
)
)
.()
VALUE
TYPE
100
Aluminum Electrolytic
C3l*
ufd
C32
.1
ufd
Disc
C34
680
pfd
Monolythic or Disc
C35
Mylar Tubular
.1
ufd
C36
.1
ufd
Disc
C37
.1
ufd
Disc
C52
.001 ufd
Mylar Tubular
C53
.01 ufd
Mylar Tubular
C54
.001 ufd
Disc
C55
.001 ufd
Disc
C57
.1
ufd
Disc
*Install C31 with n+n lead at the top •
Step 19. Install Q2 (2N2907) in its location below and to
the right of U88. The emitter'lead (closest'to tab on can)
is oriented toward the left of the board and the,bi3-se is
oriented toward the bottom. Push straight down on transistor
until it is stopped by the leads. Solder and trim.
( ) Step 20. Install diodes D9 and DIO (lN4l48 or lN9l4) in
their locations below U88. Position D9 with its dark band
(cathode) to the left and DIO with its band to the right.
( ) Step 21. Install remaining length of coaxial cable (33"),
composite video, output.
(See Figure 3-4 for details on how
to prepare cable.)
( ) Strip away about 1-1/4 11 of the outer insulation to expose
shield. Unbraid shield, gather and twist into a single
lead. Then strip away the inner conductor insulation,
leaving about 1/4" at the shield end.
CAUTION
WHEN PREPARING AND INSTALLING SHIELD, BE
SURE BITS OF BRAID DO NOT FALL ONTO BOARD.
SUCH DEBRIS CAN CREATE HARD-TO-FIND SHORT
CIRCUITS.
( ) Insert inner conductor in mounting hole PI (left side of
board), solder and trim.
REV A
111-20
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
Insulation
Inner
Figure 3-4.
Coaxial cable preparation.
( ) Refer to Detail E on Drawing X-6. Insert twisted shield
in mounting hole P2, solder and trim. Using the two large
holes to the right of VRI and VR2, tie cable to board with
tie wrap (see CAUTION below) •
CAUTION
AFTER INSTALLATION, FINE BITS OF THE BRAID
FROM THE SHIELD MAY WORK LOOSE AND FALL
ONTO THE BOARD AND CREATE HARD-TO-FIND
SHORT CIRCUITS. TO PREVENT THIS, COAT ALL
EXPOSED BRAID WITH AN ADHESIVE AFTER SOLDERING AND TIEING. USE AN ADHESIVE SUCH
AS SILICONE, CONTACT CEMENT OR FINGERNAIL
POLISH. DO NOT USE WATER BASE ADHESIVES.
( ) Step 22. Install 6-position DIP switch in location Sl on
left end of board. Position Switch No. 1 at the bottom.
( ) Step 23. Install 20-pin header in location J4 (video expansion connector) between U28 and U29.
position header so
pin I is in the lower right corner.
(An arrow on the connector points to pin 1.)
( ) Step 24. Install the following IC's in the indicated locations. Pay careful attention to the proper orientation.
Dots on the assembly drawing and PC
board indicate the location of pin I
of each IC.
IC NO.
(
(
(
(
(
(
(
,
)
)
)
)
)
)
)
U28
U3l
U33
U40
U43
U47
U49
TYPE
74LSl63
74LS163
74LS163
74LS163
74LSI09
74LSIO
74LS04
or
or
or
or
25LSl63
25LS163
25LS163
25LS163
"-
(Step 24 continued on Page 111-22 . )
REV A
111- 21
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC S.INGLE BOARD TERMINAL COMPUTER™
IC NO.
)
)
)
)
)
)
)
)
U59
U60
U62
U74
U75
U87
U88*
U102*
*MOS device.
SECTION III
TYPE
74LS20
74LS02 or 9LS02
93L16
74LS86
74LS109
7406
4049 or 14049*
4001 or 14001*
Refer to CAUTION on Page III-11.
Step 25. Apply power to Sol-PC and check display section
timing chain operation.
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A CLEAN NONCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
( ) Using an oscilloscope, check for the waveforms given in
Figure 3-5 at the indicated observation points and in the
order given. The waveforms shown in Figure 3-5 approximate actual waveforms. If any waveforms are incorrect,
determine and correct the cause before proceeding with
assembly.
( ) Turn off power supply and disconnect power connector.
( ) Step 26.
Check synchronization circuits.
Set all Sl switches to OFF.
Connect Sol-PC video output cable to video monitor.
SEE CAUTION ON PAGE 1II-24 BEFORE CONNECTING MONITOR.
(Step 26 continued on Page 1II-24.)
REV A
III-22
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
CHECK POINT
SECTION III
WAVEFORM
) U28, PIN 12
4VI
280ns
420ns
GND
(
(
) U47, PIN 8
)U59,PIN8
'1:
600ns
) U43,PIN 9
13.3ms l
(
) U8a, PIN 10
--i\:=4)1S
) uaa, PIN 4
Figure 3-5.
64ps
.1
839}Js
.1
600ns
(
(
REV B
-I:
nO.
7mS
1
13.3ms
I
60,..s
·1
15.5ms
.1
Display section timing waveforms.
111-23
PROCESSOR TECHNOLOGY CORPORATION
. Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
CAUTION
DO NOT CONNECT THE Sol-PC "VIDEO OUTPUT
TO A MONITOR OR TV RECEIVER THAT IS NOT
EQUIPPED WITH AN ISOLATION TRANSFORMER.
(SEE PAGE AVI-7 IN APPENDIX VI.)
( ) Set VR2 (VERT) and VRI (HORIZ) on the Sol-PC to their midrange settings. Turn monitor on and apply power to the
Sol-PC. "
( ) The display raster will be pulled in. Using the monitor
·Vertical Hold, you should be able to· obtain a slow roll
(black horizontal bar moves slowly down the screen) and
a stationary raster. Using the monitor Horizontal Hold,
you should be able to adjust for an out of sync raster
(numerous black lines cutting across the raster) and a
stable raster. If yo~ c~nnot obtain these conditions,
locate and correct the cause before proceeding.
For a stable presentation, a few monitors (especially modified TV sets) may
require a higher sync amplitude than
that supplied by the Sol-PC. In such
cases, increase sync amplitude by reducing the value of R80. DO NOT
DECREASE R80 BELOW 225 OHMS.
( ) If the synchronization circuits are operating correctly,
turn monitor and power supply off, disconnect the power
cable and go on to Step 27.
( ) Step 27. Install the following IC's in the indicated locations. Pay careful attention to the proper orientat"ion.
Dots on the assembly drawing and PC
board indicate the location of pin I
of each IC.
(stet;) 27 continued on Page" 1II-25.;}
III- 24
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
TYPE
IC NO.
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
) SteQ 28.
(
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
Ul*
U2
Ull*
U12
U13
U25*
U26
U27
U29
U30
U32
U41
U42
U44
U61
U89
4029*
74LS175
4029*
74LS157
74LS175
6574 or
74LS175
74LS175
74LS367
74LS157
74LS157
74166
74LS175
74LSOO
74LSIO
74LS367
*MOS device.
Refer to CAUTION on Page III-II.
or 25LS175
or 25LS175
6575*
or 25LS175
or 25LS175
or 25LS175
Check display circuits.
) Set Sl switches as follows:
No. 1 through 5:
No. 6:
(
SECTION III
OFF
ON
) Remove U42 and bend pin 6 out 45° to its normal position.
(See Figure 3-6. )
socket.
Re-install U42 with pin 6 out of the
Bend desired pin
out 45° to
vertical.
Figure 3-6.
Bending selected pins on U42, 59 and 75
(U59 shown).
( ) Remove u59 and bend pin 4 in same manner as U42.
install U59 with pin 4 out of the socke~.
(Step 28 continued on Page 111-26.)
III-25
Re-
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
Remove U75 and bend pin 5 in same manner as U42.
U75 with pin 5 out of the socket.
Re-install
Using #24 wire, NOT CLIPPED COMPONENT LEADS, install the
following TEMPORARY jumpers in the sockets for U14 through
U2l. Double check jumpers after installing for correctness.
(See Figure 3-7.)
IC SOCKET
(
JUMPER
) U14
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
( ) U15
(
)
U16
( ) U17
(
(
(
(
U14
) U18
) U19
) U20
) U2l
U15
Figure 3-7.
U16
U17
U18
12
12
12
12
12
12
12
12
U19
to
to
to
to
to
to
to
to
6
5
4
8
2
7
1
16
U20
U21
U14 through U2l socket jumpers.
( ) Turn monitor on and apply power to Sol-PC.
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A CLEAN NONCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
( ) Momentarily ground pin 1 of U2 and pin 5 of U75. The display shown in Figure 3-8 should appear on the monitor
screen. Adjust VRl and VR2 to center display if needed.
If the display circuits do not pass this test, determine
and correct the cause before proceeding with assembly.
If the display circuits are operating correctly:
Turn monitor and power supply off and disconnect the
power cable.
Remove jumpers from U14 through U2l sockets.
Bend pin 6 on U42, pin 4 on U59 and pin 5 on U75 back
to their normal position and re-install these three
. IC's in their appropriate sockets.
REV A
1II-26
PROCESSOR TECHNOLOGY CORPORATION
SECTION III
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
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Figure 3-8. Display circuits test pattern
with 6575 character generator as U25. 6574
is the same except graphic control characters are displayed.
( ) Step 28A.
Install a permanent jumper (#24 insulated wire)
on solder (back) side of board between pin 13 of UI07 and
the feedthrough hole next to pin 21 of UI05.
Solder jumper
in place, check for solder bridges and trim wire ends if
needed.
The installed jumper is shown in Figure 3-8A.
Install this jumper
UI07--Solder side of board shown
Figure 3-8A. Step 28A jumper installation.
REV B
1II-27
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
( ) Step 29.
Install 91L02, 2102 or 2lL02 IC's in locations U14
through U21.
Dots on the assembly drawing and PC board legendindicate - the locc..tion of pin 1 of each I.C.·
..'
CAUTION
IC's U14 THROUGH U2l ARE MOS bEVICES. REFER TO CAUTION ON PAGE III-II BEFORE YOU
INSTALL THESE IC's.
(
Install the following resi~tors in the indicated
locations. Bend leads to fit distance between mounting
holes, insert leads, pull down snug to board, solder and
trim.
) 3;t:eQ 30.
LOCATION
(
(
(
(
(
(
)
)
)
)
)
)
)
(
(
(
(
)
)
)
(
)
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
REV A
R12
R18
R20
R3l
R32
R33
R34
R3S
R36
R4l
RSO
RSI
RS2
RS3
RS4
RSS
RS6
RS?
RS8
RIO?
Rl08
Rl09
RllO
RIll
Rl12
Rl13
Rl14
RllS
VALUE (ohms)
COLOR CODE
1.SK
10 K
1.SK
1.SK
1.SK
1.SK
1.SK
1.SK
1.SK
1.SK
I.SK
1.SK
1.SK
1.SK
1.SK
1.SK
1.SK
1.SK
330
10 K
10 K
10 K
10 K
10 K
10 K
10 K
10 K
1.SK
brown-green-red
brown-black-orange
brown-green-red
111-28
"
"
"
orange-orange-brown
brown-black-orange
"
"
"
"
"
"
"
"
"
"
"
"
"
"
brown-green-red
PROCESSOR TECHNOLOGY CORPORATION
SECTION III
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
( ) Step 31. Install diode D7 (lN4l48 or lN9l4) in its location
between U46 and U47. Position D7 with its dark band (cathode)
at the bottom.
( ) Step 32. Install 20-pin header in location J3 (keyboard interconnect) between U64 and U65. Position header so pin 1 is in
the upper left corner.
(An arrow on the connector points to
pin 1.)
( ) Step 33. In the jumper area labeled PHTM on the assembly
drawing (below U64), install Augat pins in mounting holes F
and G.
(Refer to "Installing Augat Pins" in Appendix IV.)
Using #24 bare wire, install a jumper between pins F and G.
DO NOT SOLDER JUMPER TO AUGAT PINS.
( ) Step 34. In the jumper area labeled RST on the assembly
drawing (between U76 and U77), install Augat pins in mounting
holes Nand P.
(Refer to "Installing Augat Pins" in Appendix
IV.) Using #24 bare wire, install a jumper between pins N
and P. DO NOT SOLDER JUMPER TO AUGAT PINS.
( ) Step 35.
Install the following IC's in the indicated locations.
Pay careful attention to the proper orientation.
NOTE
Dots on the assembly drawing and PC board
indicate the location of pin 1 of each IC.
IC NO.
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
REV B
)
)
)
)
)
)
)
)
)
)
)
)
)
)
U45
U46
U48
U50
U54
U63
U64
U67
U68
U76
U93
U94
Ul06
Ul07
TYPE
74LS04
8T380 or 8836
74LSOO
74LS367
74LS04
74LSl09
74LSl09
8T97, 8097 or 74367
8T97, 8097 or 74367
74LS175 or 25LS175
74LS175 or 25LS175
74LS367
74LS175 or 25LS175
74LS367
) Step 36.
Apply power to Sol-PC and make the following voltage
measurements:
1II-29
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A CLEAN NONCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
VOLTAGE *
MEASUREMENT POINT
Pin 11 of UI05 Socket
Pin 20 of Ul05 Socket
Pin 28 of Ul05 Socket
-5 V dc + .25 V
- .25
+5 V dc +V
+12 V dc +" .6 V
Pin
Pin
+5 V dc + .25 V
-12 V dc + .6 V
1 of U5l
2 of U5l
Socket
Socket
*All voltages referenced to ground.
) If any voltages are incorrect, locate and correct the
cause before going on to Step 37.
If voltages are correct, turn power supply off, disconnect power cable and go on to Step 37.
( ) Step 37. Install the following IC's in the indicated locations. Pay careful attention to the proper orientation.
Dots on the assembly drawing and PC board
indicate the location of pin I of each ICo
TYPE
IC NO.
U5l*
Ul05* #
*MOS device.
6011, 1602, 2017 or 1013*
8080,8080 or 9080*#
Refer to CAUTION on Page III-II.
#Note that pin 1 of this IC is in the upper
left corner.
( ) Step 38.
Perform Functional Test No. I of CPU circuits.
( ) Set Sl switches as follows:
No. I through 5:
No.6:
OFF
ON
( ) Turn monitor on and apply power to Sol-PC.
REV B
111-30
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A CLEAN NONCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
( ) Momentarily ground pin 1 of U2. You should see a full display (64 characters x 16 lines) on the monitor as shown
in Figure 3-9.
( ) Momentarily ground pin 2 of U75. The display should blank
while pin 2 of U75 is grounded. When you remove the
ground, the display shown in Figure 3-9 should appear.
The pattern shown in Figure 3-9 (delete
characters) results from all bits of the
DIO Bus being high. If you do not see
the delete characters, one or more bits
of the DIO bus are low. Consult the
MCM6575 .or MCM6574 pattern, as appropriate, in Section VIII of this manual
to determine which bits are low.
( ) If the test fails, determine and correct the cause before
proceeding with assembly.
( ) If the Sol-PC passes this test, turn monitor and power
supply off, disconnect power cable and proceed to Step 39.
( ) step 39. Install the following IC's in the indicated locations. Pay careful attention to the proper orientation.
NOTE
Dots on the assembly drawing and PC board
indicate the location of pin 1 of each IC.
IC NO.
( )
( )
REV A
TYPE
U80
U81
8T97 , 8097 or 74367
8T97, 8097 or 74367
.111-31
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Figure 3-9.
( ) Step 40.
SECTION III
CPU Functional Test No.1 display,
6574 or 6575 character generator (U25).
Perform Functional Test No. 2 of CPU circuits.
Check that Sl switches are set as specified in Step 38.
Turn monitor on and apply power to Sol-PC.
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A CLEAN NONCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
( ) Momentarily ground pin 1 of U2 and pin 2 of U75. The display shown in Figure 3-10 on Page 1II-34 should appear
on the monitor.
If the test fails, determine and correct the cause before
proceeding with assembly.
( ) If the Sol-PC passes this test, turn monitor and power
supply off, disconnect power cable and proceed to Step 41.
( ) Step 41.
Install the following IC's in the indicated locations. Pay careful attention to the proper orientation.
REV B
1II-32
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
NOTE
Dots on the assembly drawing and PC board
indicate the location of pin I of each IC.
IC NO.
TYPE
74LS253
74LS253
74LS253
74LS253
74LSI09
U65
U66
U78
U79
U70
( ) Step 42. Turn monitor on,apply power to Sol-PC and perform
the test described in Step 40, except ground pin 5 of U75 instead of pin 2. You should get the same results. - - - - CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A CLEAN NONCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
( ) If the test fails, determine and correct the cause before
proceeding with assembly.
( ) If the Sol-PC passes this test, turn monitor and power
supply off, disconnect power cable and proceed to Step 43.
( ) Step 43. Install the following resistors in the indicated
locations. Bend leads to fit distance between mounting holes,
insert leads, pull down snug to board, solder and trim.
LOCATION
Rl3
Rl4
Rl5
R60
VALUE (ohms)
1.5K
1.5K
1.5K
1.5K
COLOR CODE
brown-green-red
II
II
II
"
II
II
"
II
"
( ) Step 44. See Detail A on Drawing X-6. Using two 4-40 x 5/8
binder head screws, two #4 insulating washers, two lockwashers
and hex nuts, install 30-pin right-angle edge connector in
location J5.
Insert screws from back (solder) side of board
and place an insulating washer on each screw on front (component) side of board. Position connector with socket side
facing right, place over screws and seat pins in mounting
holes. MAKE SURE ALL PINS ARE THROUGH HOLES. Then place lockwasher on each screw, start nuts and tighten. DO NOT OVERTIGHTEN. Solder pins to board.
REV B
111-33
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
( ) Step 45. See Detail D on Drawing X-6. Using 4-40 x 1/4
binder head screws, lockwashers and hex nuts, install two
brackets for personality module in area to right
of J5. Position brackets over the mounting holes as shown in
Figure 3-11. Insert screws from front (component) side of
board, place lockwasher on each screw on back (solder) side
of board, start nuts and tighten.
g~~~9~St.9~9~9~9~9~9~9~9~9~9~9~9~9~9~9t9t9~9~9~9u9~9~9~9~9,mt9~
9~9~9~'3~9~9~9~9~9~9~9~9'69~%9~9~9~9~9t9~9~9~9~9'69~9~9~9t9t9~9~9~
9~9t9~9~9~'3~9~9~9~9~9~9~%9~9t9t9t9t9~9~9~9~9~9t9~9~9~9~9~9~9~9~
9~9~9~9~9~9~9~9~9~9~9t9~9~9~9~9t%9~9~9~9u9~%9~9~9~9~9~:3~9t9~9'6
9~9t'3t9~9~9~9~9~9~9t9u9t9t9t9t9t9t9~9t9~9~%%9~9~9t9~9~9~9t9~%
9~9~,,~9~9t9~9~9~9~9~9t9u%9~9~9~9~9~9~9~9~9~9~%9~9¥'9~9u9lb'3t9t9o
9~9t9¥'9t9~9~9~9~9~9¥'9~9t9t9~9t9~9~9~%9~9~%9~9~9~9~9t.9~9~%9u9u
9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9t9~9t9u
9~9~9~9~9~9~9~9~9~9~9t9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9u9%9~
9~9~9~9~9~9~9~9~9~9t9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9t9~9t9~
9~9~9t9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~9~~9t~9~9~~9~9t9~9~
9'69~9~9~9~9~9~9~9'69~9~9t9~9~9~9~9~%9~9~9~9~9~9'69'69~9~9~9t9~9~9~
9~9~9'69~9'69'69'69'69'69'69'69~9'69~9~9'69t9t9~9~9~9t9t9t9~9t9~9~9~9t~9~
9'69~9t9~9~9'69t9t9'69'69~9t9~9~9~9'69'69'69~9~9~9t9t9t9t9~9t9t9~9'6~9t
9t9~9~9'69~9'69t9t~9t9'69'69'69t9t9t9t9t9t9t9t9'69t9t9'6%9~9'69~9~9~9t
9~9~9~9~9~9~9~9~9u9u9~9n9n9n9~9~9~9~9~9~9~9~9~9~9~~~9~9~~9~9~~
Figure 3-10.
CPU Functional Test No. 2 display,
6575 character generator (U25).
6574 displays: 9090 9D etc.
~
Bracket
screw~
,-----,
sol-PCB~
~ Lockwasher Solder
Side
Figure 3-11.
REV A
~Hex Nut~
Top Edge ..........
of Board,......
Personality module bracket/guide
installation (Viewed from right
end of Sol-PCB).
111-34
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
( ) Step 46. Refer to Detail D on Drawing X-6. Attach plastic
card guide to each of the brackets installed in Step 45.
(See Figure 3-11.)
Insert posts on guides into bracket holes
and push in until they snap into place. Be sure open end of
guide is ~way from connector J5.
( ) Step 47. Install the following IC's in the indicated locations. Pay careful attention to the proper orientation.
Dots on the assembly drawing and PC board
indicate the location of pin 1 of each IC.
IC NO.
( ) U3*
( ) U4*
( ) U5*
( ) U6*
( ) U7*
( ) U8*
( ) U9*
( ) UlO*
( ) U22
( ) U23
( ) U24
( ) U34
( ) U35
( ) U36
( ) U53
( ) U7l
( ) u83
*MOS device.
( ) Step 48.
TYPE
9lL02 , 2102 or 2lL02
9lL02 , 2102 or 2lL02
9lL02, 2102 or 21L02
9lL02 , 2102 or 21L02
9lL02 , 2102 or 21L02
9lL02 , 2102 or 2lL02
9lL02 , 2102 or 21L02
9lL02 , 2102 or 2lL02
74LS136
74LS20
74LS04
74LS138
74LS138
74LS138
74LS02 or 9LS02
74LS367
74LS20
Refer to CAUTION on Page III-II.
Test memory and decoder circuits.
) Set Sl switches as specified in Step 38.
) Turn monitor on and apply power to Sol-PC.
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A CLEAN NONCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
REV B
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
( ) Ground pin 1 of U2. You should see the same display as
shown in Figure 3-10 on Page 111-34. In this case, however, there should be a vertical "flickering" movement
with an apparent flicker rate of approximately three
times per second.
Turn Switch No. 1 of Sl to ON.
The flicker should stop.
If the test fails, determine and correct the cause before
proceeding with assembly.
( ) If the Sol-PC passes this test, turn monitor and power
supply off, disconnect power cable, set Switch No.1 of
Sl to OFF and go on to Step 49.
(
)
Step 49. Assemble personality module if you have not yet done
(See Section IV.)
If you have started assembly, go to
so.
Step 9 in Section IV and complete it.
(
)
Step 50.
Install the following resistors in the indicated
locations. Bend leads to fit distance between mounting holes,
insert leads, pull down snug to board, solder and trim.
LOCATION
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
R21
R22
R23
R24
R25
R26
R27
R28
R37
R38
R39
R40
R42
R43
R44
R45
R46
R47
R48
R49
R59
R61
R62
R63
VALUE (ohms)
270
470, ~ watt
470, ~ watt
1.5K
10 K
10 K
4.7K
10 K
1.5K
1.5K
5.6K
1.5K
1.5K
1.5K
1.5K
330
5.6K
10 K
10 K
1.5K
1.5K
1.5K
5.6K
5.6K
(Step 50 continued on Page 111-37.)
REV A
111-36
COLOR CODE
red-violet-brown
"
"
,.
"
"
"
brown-green-red
brown-black-orange
"
"
"
"
"
"
"
"..
."
.."
yellow-violet-red
brown-black-orange
brown-green-red
green-blue-red
brown-green-red
.
..
orange-orange-brown
green-blue-red
brown-black-orange
.
"
"
"
"
"..
"..
"
"
brown-green-red
green-blue-red
"
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
LOCATION
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R92
R93
R94
R95
Rl16
SECTION III
VALUE ( ohmS)
COLOR CODE
330
330
330
330
330
330
330
330
680
680
680
680
680
680
680
680
5.6K
1.5K
10 K
15 K
1.5K
orange-orange-brown
blue-gray-brown
green-blue-red
brown-green-red
brown-black-orange
brown-green-orange
brown-green-red
( ) Step 50A. Install R29, a 15K ohm, 1/4 watt resistor (color
code brown-green-orange). Make right angle bend in one lead
approximately 1/8" from resistor body. Insert bent lead in
right-hand mounting hole (next to left mounting hole for 03) ,
solder and trim. Slip 0.9" length of insulation tubing over
left-hand lead of R29. Cut lead 0.1" longer than tubing.
Route lead as shown on Sol-PC assembly drawing X-5 in Section
X, hook it around left-hand lead of R23 (470 ohm, 1/2 watt
resistor), solder and trim.
( ) Step 51. Install the following capacitors in the indicated
locations. Take care to observe the proper value and type
for each installation. Bend leads outward on solder (back)
side of board, solder and trim.
(Refer to NOTE in Step 2.)
LOCATION
C29
C30
VALUE
330
.1 ufd
pfd
TYPE
Disc
Disc
Step 52. Install diodes DI (lN4148 or lN914), D2 (lN4001)
and D3 through D6 (lN4148 or IN914) in their locations in
the area of U39. Position all diodes with their dark band
(cathode) to the right.
( ) Step 53. Install the following DIP switches in the indicated locations. Take care to observe proper orientation.
REV A
1II-37
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
TYPE
LOCATION
) S2
) S3
) S4
ORIENTATION
Switch No. 1 at top
Switch No. 1 at top
Switch No. 1 at top
8-position
8-position
6-position
Step 54. Install Ql (2N2907) in its location between U55 and
U56. The emitter lead (closest to tab on can) is oriented
toward the bottom and the base lead toward the right. Push
straight down on transistor until it is stopped by the leads.
Solder and trim.
( )
Step 55. See Detail B on Drawing X-6. Using two 4-40 x 7/16
binder head screws, hex nuts and lockwashers, install 25-pin
female connector in location Jl (serial I/O interface). Position connector with socket side facing right and insert pins
into their holes in the circuit board. Insert screws from back
(solder) side of board, place lockwasher on each screw, start
nuts and tighten. Then solder connector pins to board.
See Detail B on Drawing X-6. Using two 4~40 x 7/16
binder head screws, hex nuts and lockwashers, install 25-pin
male connector in location J2 (parallel I/O interface). Install J2 in the same manner as you did Jl.
Install Augat pins in mounting holes K, Land M.
( ) Step 57.
(Refer to "Installing Augat Pins" in Appendix IV.)
These
holes are located between U85 and U86. No jumper will be
installed.
( ) Step 58. Install the following IC's in the indicated locations.
Pay careful attention to the proper orientation.
( ) Step 56.
NOTE
Dots on the assembly drawing and PC board
indicate the location of pin 1 of each IC.
TYPE
IC NO.
--
74LS367
U37
1489 or 75189*
U38*
4N26#
U39#
74LSl09
U52
74LSOO
U55
1458 or 72558
U56
7406
U57
8T94
U58
. 74LSl09
U72
74LSl09
U73
4029*
US4*
4046 or 14046*
US5*
4024 or 14024*
US6*
74173 or STIO
U95
74173
or 8TlO
U96
74175
U97
CAUTION
on Page III-II.
Refer
to
*MOS device.
#Solder this IC in its location. See "Loading DIP Devices"
in Appendix IV.
111-38
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
REV B
PROCESSOR TECHNOLOGY CORPORATION
Sol~?C SINGLE BOARD TERMINAL COMPUTER™
SECTION III
( ) Step 5SA.
Install R160 (47 ohm resistor, color code yellowviolet-black) as follows:
( ) Wrap one R160 lead around pin 1 of U39 (4N26) and the
other around the cathode lead (banded end) of D3 (lN414S),
dressing the leads as shown on Drawing x-5 in Section x.
( ) Solder both R160 leads in place and trim excess lead
lengths.
( ) Inspect for possible shorts or solder bridges, especially
between pins 1 and 2 of U39.
( ) On the back (solder) side of the board, the trace that
connects pin 1 of U39 to the cathode lead of D3 must be
cut. Using an Xacto knife or a razor blade, make two cuts
approximately l/S" apart, cutting across the trace down
to the epoxy base.
Insert blade tip beneath the cut section and gently work it away from the board. Be sure the
"break" is free of solder.
( ) Step 59.
Check input/output (I/O) circuits.
NOTE
The parallel I/O interface should be
tested with the device you will be
using. Refer to "I/O Interfacing"
in Section VII.
To check the serial I/O circuits, proceed as follows:
() Set
Set
Set
Set
Sl
S2
S3
S4
as in previous test,
switches all OFF,
switches all OFF, except S3-1 ON,
switches all OFF
Set all S4 switches to OFF.
Connect Sol keyboard assembly to Sol-PC. Using the supplied 20-conductor ribbon cable, connect Jl on keyboard
to J3 on Sol-PC as shown in Drawing X-IO in Section X.
( ) Connect Sol-PC video output cable to monitor, turn monitor on and apply power to Sol-PC.
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
AND KEYBOARD WHEN THEY ARE NOT INSTALLED
IN THE CHASSIS, THEY MUST REST ON A CLEAN
NONCONDUCTING SURFACE~E SURE NEITHER
ASSEMBLY IS PLACED ON TOP OF PIECES OF
WIRE AND/OR SOLDER.
REV B
111-39
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Set Sol-PC to local by depressing LOCAL key on keyboard to
turn keyboard indicator light on.
Data entered from the keyboard should appear on the monitor.
If the Sol-PC fails this test, locate and correct the
cause before proceeding.
If the Sol-PC passes this test, turn monitor and power
supply off, disconnect power cable, video output cable,
keyboard and go on to Step 60.
( ) Step 60. Install the following resistors in the indicated locations. Bend leads to fit distance between mounting holes,
insert leads, pull down snug to board, solder and trim.
LOCATION
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
( )
( )
( )
REV B
Rl17
Rl18
Rl19
R139
R140
R141
R142
R143
R144
R145
R146
R147
R148
R149
R150
R151
R152
R153
R154
R155
R156
VR3
VALUE {ohms}
10 K
10 K
10 K
1.0M
10 K
150 K
10 K
1 M
47 K
10 K
10 K
2.2M
100 K
100
470
5.6K
150 K
100 K
47 K
6.8, ~ watt
6.8, ~ watt
100 K
111-40
COLOR CODE
brown-black-orange
"
"
"
"
"
"
brown-black-green
brown-black-orange
brown-green-yellow
brown-black-orange
brown-black-green
yel10w-violet-orange
brown-black-orange
"
"
"
red-red-green
brown-black-yellow
brown-black-brown
yellow-violet-brown
green-blue-red
brown-green-yellow
brown-black-yellow
yellow-violet-orange
blue-grey-gold
blue-grey-gold
Poten"tiometer
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTIO:::-J III
( ) Step 61. Install the following capacitors in the indicated
locations. Take care to observe the proper value and type
for each installation. Bend leads outward on solder (back)
side of board, solder and trim.
(Refer to NOTE in Step 2.)
CAUTION
REFER TO FOOTNOTE AT END OF THIS STEP
BEFORE INSTALLING C67.
LOCATION
( )
( )
(
)
( )
( )
( )
(
)
(
(
(
(
(
(
(
)
)
)
)
)
)
)
VALUE (ufd)
C47
.001
Disc
II
C48
.047
II
C49
.001
CSO
.01
Mylar Tubular
CSI
.1
Disc
II
C66
.1
C67*
1
Tantalum
C68
.1
Disc
II
C69
.1
C70
.1
"
II
C71
.001
C72
.001
Mylar Tubular
C73
.047
Disc
C74
470
pfd
"
*Install C67 with "+" lead at top right.
( ) Step 62. Install miniature phone jacks in locations J6 and
J7 located to the right of UIOI. Position J6 and J7 with
jack facing right, insert pins in mounting holes and solder.
( ) Step 63. Install subminiature phone jacks in locations J8
and J9 in lower right corner of board. Install J8 and J9
as you did J6 and J7.
( ) Step 64. Install Q3 (2N4360) in its location to the left of
C67. Install Q3 with its flat IIside ll at the bottom. Push
straight down on transistor until it is stopped by the
leads, solder and trim.
CAUTION
THE 2N4360 IS STATIC SENSITIVE.
CAUTION ON PAGE III-II.
REFER TO
( ) Step 65. Install Q4 and QS (2N2222) in their locations
above and to the left of UI08. For both transistors, the
emitter lead (closest to tab on can) is oriented toward the
left and the base lead toward the right. Push straight down
on transistor until it is stopped by the leads, solder and
trim.
III- 41
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
( ) Step 66. Install diodes D13 and D14 (lN4001) in their locations in the lower right corner of the board. Position both
diodes with their dark band (cathode) at the bottom.
( ) Step 67. Install DIP reed relays in locations Kl and K2 to
the right of Ul13. Be sure to install Kl and K2 with their
end notch at the bottom )pin 1 in lower right corner).
These relays are soldered to the board.
(Refer to "Loading
DIP Devices" in Appendix IV.)
( ) Step 68. Install the following IC's in the indicated locations. Pay careful attention to the proper orientation.
NOTE
Dots on the assembly drawing and PC board
indicate the location of pin 1 of each IC.
IC NO.
(
)
)
( )
( )
( )
( )
( )
( )
( )
( )
( )
(
U69*
U98*
U99*
UIOO*
UIOl*
UI08
UI09*
UIIO*
Ulll*
Ul12*
ul13*
*MOS device.
(
TYPE
6011,1602,2017 or 1013*
4023 or 14023*
4030*
4013 or 1413*
4027 or 14027*
1458 or 72558
4049 or 14049*
4046 or 14046*
4019*
4520 or 14520*
4013 or 1413*
Refer to CAUTION on Page III-II.
) step 69.
Install Augat pins in mounting holes H, I and J
(located to left of C70).
(Refer to "Installing Augat Pins"
in Appendix IV.) Using #24 bare wire, install a jumper between pins I and J. DO NOT SOLDER .TUMPER TO AUGAT PINS.
( ) Step 70.
Adjust VR3.
Ground ACI audio input (J7) on Sol-PC.
Apply power to Sol-PC.
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A CLEAN N0NCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
REV A
1II-42
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
( ) Using an oscilloscope with a calibrated time base (a frequency counter is preferred) and a high-impedance probe,
monitor the VCO (voltage controlled oscillator) frequency
on pin 4 of UIIO.
Adjust VR3 for a frequency of 14.0 KHz (71.4 usec period).
Disconnect power and remove ACI audio input (J7) ground.
( ) Step 71. If your recorder has only a microphone input, remove
the I-to-J jumper you installed in Step 69 and install a
jumper (#24 bare wire is recommended) between the I and H pins.
DO NOT SOLDER JUMPER TO AUGAT PINS.
NOTE
Microphone inputs are not recommended.
Otherwise, leave the I-to-J jumper in and go on to Step 72.
( ) Step 72. See Detail C on Drawing X-6.
Install lOa-pin edge
connector, Jll. Using two 4-40 x 7/16 binder head screws,
install lOa-pin edge connector in location Jll (center of PC
board). Seat the pins in the mounting holes. Then thread
screws from front (component) side of board into the threaded
inserts that are pre-installed in the Jll mounting holes.
Tighten screws and solder pins to board.
3.7
OPTIONS
3.7.1
625 Line Video, 50 Hz
The European televisions standard defines a raster of 625
lines at a field rate of 50 Hz. The horizontal rate of the U.S.
standard, 15,750 Hz., is maintained. Only the number of scan lines
on the screen is increased.
The Video Display Generator section may be modified for the
50 Hz. standard by following the additional steps below. The effect
of the modification is to increase the modulus of the counter U62 to
eight during-vDISP. This results in four extra character lines (52
scan lines) between the bottom and top of the display area, for
a total of 312 scan lines per field and 624 scan lines per frame.
The field rate should be close enough to 50 Hz. to reduce
any swim effects to less than 0.1 Hz. Some difficulty may be
encountered in obtaining centering of the display within the frame.
This is because the stand-off time to VSYNC from the bottom of the
display is unchanged from the 60 Hz. standard. If objectionable,
increase the value of resistor RIOO which is in series with the VPOS
control.
REV B
1II-43
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
To convert for 50 Hz., perform these additional steps:
( ) Locate U62 on the component side legend. Find pin 5
of this Ie on the component (front) side of the board.
Cut the "V"-shaped trace connecting pin 5 to the nearby pad designated "AF", using a sharp exacto blade or
scribe, so that there is no continuity between these
pads.
( ) Bend a small piece of bare wire, such as a resistor
clipping, into a loop to form a jumper between pad
"AF" , and the adjacent pad "AG". Insert the jumper,
pull close to the board, solder, and trim the leads.
If this modification is made, change the schematic, X-18, to
show that pin 5 of U62 now connects to pin 4 (ground), instead
of pin 6 as shown.
3.7.2
Vectored Interrupt
Though the 8080A microprocessor used in the Sol Computer has
the vectored interrupt capability, Processor Technology software for
the Sol and S-lOO modules built by Processor Technology do not use
it. A jumper arrangement in the Sol, however, is provided to implement vectored interrupt when the interrupt signal is made available
on the S-lOO bus by a circuit board that is plugged into it.
If you wish to use vectored interrupt, you must supply an interrupt controller card.
To modify the Sol-PC for vectored interrupt, two jumpers (AB-to-AD
and AC-to-AE) must be installed to enable the SINTA signal (interrupt acknowledge, S-lOO bus pin 96) to reach the memory decoder circuit. These jumpers may be added at any time, either during assembly
or after the Sol-PC is completely assembled.
NOTE
Vectored interrupt jumpers may be left
in place, even if no S-lOO board generates interrupts. S-lOO bus pin 96
(SINTA) may float with no interference.
To install the two vectored interrupt jumpers, proceed as follows (see Figure 3-12):
( ) Cut two eight-inch lengths of #24 solid, insulated wire
(not supplied).
REV A
111-44
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
Strip 0.1" of insulation from both ends of each wire.
From component (front) side of Sol-PC, insert one end of
one wire into pad AC (to left of pin 9 of U58) and solder.
Insert one end of other wire into pad AB (to left of pin 8
of U58) and solder. Check for solder bridges.
Dress wires as shown in Figure 3-12.
From component (front) side of Sol-PC, insert loose end
of wire from pad AB into pad AD (to left of pin 11 of
U35) and loose end of wire from pad AC into pad AE (to
right of pin 96 of S-IOO bus, Jll). Solder and check
for solder bridges.
( ) Fix long runs of wire to board with silicon compound or
tape.
REV A
111-45
PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
SECTION III
•
..
•
Sol
TERMINAL COMPUTER
©
1976 BY PROCf550R
IECHNOLOGY CORP.
J1
"
.<)
REV A
111-46
TM
~
IV
PERSONALITY MODULE ASSEMBLY
4.1
Parts and Components . .
• IV-l
4.2
Assembly Tips • • • . .
· . IV-l
4.3
Assembly Precautions • • .
4.4
Required Tools, Equipment and Materials.
4.5
Orientation . .
· IV-l
4.6
Assembly-Test •
· IV-3
4.6.1
4.6.2
Circuit Board Check. .
Assembly-Test Procedure. •
• IV-l
• • • • • IV-l
· . IV-3
• • IV-3
PROCESSOR TECHNOLOGY CORPORATION
9216 AND 2708 PERSONALITY MODULES
4.1
SECTION IV
PARTS AND COMPONENTS
The standard Sol uses a Personality Module based on the 9216
masked ROM containing the SOLOS monitor program. The kit version is
Part No. 107000-04, and the assembled version is Part No. 107000-02.
If you are intending to use a monitor program other than SOLOS, you
will have a Personality Module based on the 2708 EPROM (not supplied)
which may be programmed to contain a custom monitor. The kit version
of the 2708 module is Part No. 107000-03, and the assembled and testec
module is 107000-01. All four of these modules use the same circuit
board, designated ASSY 107001 in white on the component side of the
board.
You will need the parts listed in Table 4-1 to assemble your
personality module. Select and separate the needed parts from those
supplied with your Sol kit before starting assembly.
(Note that several parts are not necessary for the 9216 module.)
If you have any
difficulty identifying any parts by sight, refer to Figure 3-1 in
Section III and the "Standard Color Code for Resistors and Capacitors'
chart in Appendix III. Table 4-1 lists each part, its description,
quantity and reference designation on the drawing(s) you will use in
assembling the perspnality module. The assembly drawings in Section}
will also prove useful in identifying parts.
4.2
ASSEMBLY TIPS
For the most part the assembly tips given in Paragraph 3.2 of
Section III (Page III-I) apply to assembling the personality module.
4.3
ASSEMBLY PRECAUTIONS
For the most part the assembly precautions given in Paragraph
3.3 in Section III (Page 111-9) apply.
4.4
REQUIRED TOOLS, EQUIPMENT AND MATERIALS
The following tools, equipment and materials are recommended
for assembling the personality module.
l. Needle nose pliers
2. Diagonal cutters
3. Screwdriver
4. Soldering iron, 25 watt
5. Video monitor
4.5
ORIENTATION
Capacitor location C2 will be located in the upper left-hand
corner of the board when the edge connector is positioned at the
REV B
IV-l
PROCESSOR TECHNOLOGY CORPORATION
9216 AND 2708 PERSONALITY MODULES
Table 4-1.
SECTION IV
2708/9216 Personality Module Parts List.
QUANTITY
PART
DESCRIPTION
9216 PM
REFERENCE
2708 PM
Drawing
No.
Designator
Circuit Board
Personality Module 2708/9216
1
1
X-7
1
IC
74LS08
1
1
x-7
U3
IC
9216 ROM
1
0
X-7
Ul
Diode
lN523l
0
2
X-7
Zl&2
Resistor
130 ohm, 1/2 W, 5%
0
2
X-7
Rl&2
Resistor
10K ohm, 1/4 W, 5%
3
X-7
R3,5&6
Resistor
10K ohm, 1/4 W, 5%
4
X-7
R3,4,5&6
Capacitor
.047 '\1f, Disc Ceramic
1
X-7
C5
Capacitor
1 '\1£, Tantalum, 35V
4
X-7
Cl,2,3&4
Capacitor
1 '\1f, Tantalum, 35V
1
X-7
C2
Socket
DIP, l4-pin
1
1
X-7
U3
Socket
DIP, 24-pin
2
X-7
Socket
DIP, 24-pin
1
Handle
Personality Module Handle
Bracket
1
1
X-7
2
Screw
Machine, 2-56 x 3/16
2
2
X-7
13
Lockwasher
Internal Tooth, #2
2
2
X-7
14
Assembly
Keyboard
1
1
X-IO
3
Cable
Flat, 20-wire
1
1
X-IO
23
Wire
Bus, 24 AWG
0
1"
X-7
15
Solder
60/40, 20 SWG
Subassembly
Sol Power Supply
1
1
Subassembly
Sol-PC (assembled through
Step 48)
1
1
REV B
1
IV-2
X-7
Ul&2
•
Ul
PROCESSOR TECHNOLOGY CORPORATION
9216 AND 2708 PERSONALITY MODULES
SECTION IV
left end of the board. In this position the component (front) side
of the board is facing up. Subsequent position references related
to the personality module circuit board assume this orientation.
4.6
ASSEI~LY-TEST
4.6.1
Circuit Board Check
( ) Visually check circuit board for broken traces, shorts
(solder bridges) between traces and similar defects.
( ) Check circuit board to insure that the +5-volt bus, +12
volt bus and -12-volt bus are not shorted to each other
or to ground. Using an ohmmenter, make the following measurements (refer to personality ,module assembly drawing
in Section X) :
( ) +5 volt Bus Test. On Ul, measure between pin 12,
(ground) and pin 24 (+5 volts). There should be
no continuity.
( ) -5 volt Bus Test. On Ul and U2, measure between
pin 12 (ground) and pin 21 (-5 volts). There
should be no continuity.
( ) +12 volt Bus Test. Also on Ul, measure between
pin 12 (ground) and the bottom edge connector pin
on the component side of the board marked Al.
( ) Inter-bus Test. On Ul, measure between pins 12 and
21, then between edge connector pin Al and pins 21,
then 12. There should be no continuity in any of
these measurements.
If visual inspection reveals any defect, or you measure
continuity in any of the preceding tests, return the
board to Processor Technology for replacement. If the
board is not defective, proceed to next paragraph.
4.6.2
Assembly-Test Procedure
Refer to personality module assembly drawing X-7 in Section X.
CAUTION
THE MEMORY IC'S USED ON THE PERSONALITY
MODULE ARE MOS DEVICES. THEY CAN BE
(CAUTION continued on Page IV-3)
Rev
D
IV-3
PROCESSOR TECHNOLOGY CORPORATION
9216 AND. 2708 PERSONALITY MODULES
SECTION IV
DAMAGED BY STATIC ELECTRICITY DISCHARGE.
HANDLE THESE IC's SO THAT NO DISCHARGE
FLOWS THROUGH THE IC. AVOID UNNECESSARY
HANDLING AND WEAR COTTON, RATHER THAN
SYNTHETIC, CLOTHING WHEN HANDLIl-'J~ 1-10S
IC's.
(STATIC DISCHARGE PROBLEMS ARE MUCH
WORSE IN LOW HUMIDITY CONDIT·IONS.)
( ) Step 1. Install DIP sockets. Install each socket in the
indicated location with its end notch oriented as shown on
the circuit board and assembry-drawing. Take care not tocreate solder bridges between the pins and/or traces.
INSTALLATION TIP
Insert socket pins into mounting pads of
appropriate location. On back (solder)
side of board, bend pins at opposite corners of socket (e.g. pins 1 and 9 on a
l6-pin socket) outward until they are at
a 45° angle to the board surface. This
secures the socket until it is soldered.
Repeat this procedure with each socket
until all are secured to the board. Then
solder the pins on all sockets.
LOCATION
( )
( )
( )
TYPE SOCKET
Ul
U2*
U3
*Used on 2708·
24 pin
24 pin*
14 pin
version only.
( ) Step 2. Install the following resistors in the indicated
locations. Install these resistors parallel with the board.
Bend leads by using needle nose pliers to grip the resistor
lead right next to the resistor body, and bend the portion
of the lead on the other side of the pliers with· your finger.
The bend must be the right distance from the resistor body
for the resistor to fit easily into its two holes. Insert
the leads into the two holes, and from the opposite side of
the board pull the leads to bring the resistor body down to
touch the board. Bend the leads outward on the solder (back)
side of the board so the resistors do not slip out of position.
Rev D
IV- 4
PROCESSOR TECHNOLOGY CORPORATION
9216 AND 2708 PERSONALITY MODULE
VALUE
LOCATION
( )
( )
( )
( )
( )
( )
SECTION IV
130 ohms
130 ohms
10K
10K
10K
10K
Rl*
R2*
R3
R4*
R5
R6
9216
*not used on
COLOR CODE
brown-orange-brown
brown-orange-brown
brown-black-orange
brown-black-orange
brown-black-orange
brown-black-orange
version
( ) Step 3. Install IN5231 Zener Diodes in locations Zl,
and Z2 if you have the 2708
version. Form the leads
as in Step 2. Insert the .diodes so that the white
band on the diode is in the position indicated by the
legend. Bend the leads outward to retain the diodes,
then solder and trim the leads.
( ) Step 4. Install the following capacitors in the indicated locations. Take care to observe the proper value,
type and orientation for each installation. On the dipped
tantalum capacitors, the n+n lead is the one which is
closest to the n+n marking on the body of the capacitor.
Insert this lead in the hole marked n+n on the PC board
legend. After inserting C5, remove it from the board
before soldering to clear wax from the leads and holes.
After inserting all capacitors, pull them close to the
board and bend the leads outward to secure them. Solder
and trim all leads.
LOCATION
)
)
)
)
)
VALUE (ufd)
Cl*
C2
\C3*
C4*
C5
1
1
1
1
.047
*not used on
92.16
TYPE
Dipped Tantalum
Dipped Tantalum
Dipped Tantalum
Dipped Tantalum
Disc Ceramic
version
( ) Step 5. Check for +5, +12, and -12 volt bus-to~ground
shorts.
Using an ohmmeter on OHMS times lK or OHMS
times 10K scale, make the following measurements. A
typical reading is 1 Megohm. A reading less than 10K
indicates a short.
Measure between edge connector pins A2 and A15.
Measure between edge connector pins A14 and A15.
Measure between edge connector pins Al and A15.
If any measurement indicates a short, find and correct
the problem before proceeding.
Rev
E
( ) Step 6.
Using two 2-56 x 3/]6 n binder head screws, install
IV- 5
PROCESSOR TECHNOLOGY CORPORATlON
9216 AND 2708 PERSONALITY MODULE
SECTION IV
handle bracket. Position bracket on back
(trace) side of board at the right end as shown in Figure 4-1.
Align bracket holes with mounting holes in board, insert
screws with lockwashers from back (solder) side of board and
drive into bracket. No nuts are needed since the bracket
holes are tapped.
Figure 4-1.
Handle bracket installation.
()
Step 7.
If you have a 9216 version with the 9216 ROM
(windowless), omit this step.
If you have the 2708 version,
find the area above the Ul socket where the legend reads
"-5V 21 CO 19 +12V." This legend designates five PC pads
in a row directly underneath. On the back (solder) side of
the board, there is a small trace which connects the "CO"
and "21" pad. Cut this trace with a sharp knife or scribe
point so there is no longer continuity between these pads.
Form the clipping from a resistor lead, or other small bare
wire into a loop and insert this jumper between the "-5V"
pad and the "21" pad. Solder and trim the leads. Next find
the two pads between C2 and R6, with legend "-16" under the
right pad of the pair. On the back (solder) side of the
board, cut the trace which connects these pads.
()
Step 8. Stop assembly at this point if you are building a
Sol kit and proceed with Sol-PC assembly and test up through
Step 48.
(See Section III.)
Then go on to Step 9 of this
. procedure.
()
Step 9. Plug personality module into J5 on Sol-PC, apply
power to Sol-PC and make the following voltage measurements
on the personality module, with respect to chassis ground:
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
WHEN IT IS NOT INSTALLED IN THE CHASSIS,
IT MUST REST ON A CLEAN NONCONDUCTING
SURFACE. DO NOT PLACE IT ON TOP OF
PIECES OF WIRE AND/OR SOLDER.
REV E
IV-6
PROCESSOR TECHNOLOG1 CORPORATION
9216 AND 2708 PERSONALITY MODULES
SECTION IV
MEASUREMENT POINT
Pin
Pin
Pin
Pin
Pin
* For
()
24 of Ul, U2
14 of U3
21*of Ul, U2
12 of Ul, U2
7 of U3
+5 V dc ± 5%
+5 V dc ± 5%
-5 V dc ± 5%
Ground
Ground
2708 version only.
()
Measure between edge connector pin B14 and pin B15. You
should measure more than 1M ohms. A reading less than 10
ohms indicates a short.
()
If any voltages are incorrect, locate and correct
the cause before proceeding to Step 10.
()
If the voltages are correct, turn power off, disconnect
power cable, unplug personality module and go on to
Step 10.
Step 10. Install IC's in the sockets numbered Ul through U3
as indicated in the table below. Make sure the dot or notch
indicating pin 1 on the IC package is in the correct position
as indicated on the PC board component legend and the assembly
drawing X-7. Socket U2 is left empty on 9216 versions (9216
ROM with no window).
2708 EPROMs (not supplied) may be inserted in sockets Ul and U2.
IC NO.
TYPE
2708
version
Ul*
U2*
U3
2708
2708
74LS.08
9216
version
Ul*
U2
U3
9216
Empty
74LS.08
*MOS devices.
()
VOLTAGE
See CAUTION on pages IV- 3, 4.
Step 11. Plug personality module into J5 on Sol-PC and connect Sol-PC video output cable to video monitor.
(Refer to
CAUTION on Page 111-24 in Section III.)
( ) Connect Sol keyboard assembly to Sol-PC. Using the supplied 20-conductor ribbon cable, connect Jl on keyboard
to J3 on Sol-PC as shown in Drawing X-IO in Section X.
REV E
IV-7
PROCESSOR TECHNOLOGY CORPORATION
SECTION IV
9216 AND 2708 PERSONALITY MODULES
(
)
Set Sl switches on Sol-PC as follows:
No. 1 through 4:
(
No. 5:
ON
No. 6:
OFF
OFF
) Turn monitor on and apply power to Sol-PC.
CAUTION
WHENEVER POWER IS APPLIED TO THE Sol-PC
AND KEYBOARD WHEN THEY ARE NOT INSTALLED
IN THE CHASSIS, THEY MUST REST ON A CLEAN
NONCONDUCTING SURFACE.
BE SURE NEITHER
ASSEMBLY IS PLACED ON TOP OF PIECES OF
WIRE AND/OR SOLDER.
( ) With a SOLOS module, you should see the cursor, preceded by a prompt character, like this:
J
( ) If you do not see a cursor, locate and correct the
problem before proceeding.
( ) If a blinking cursor is present, the ENter and DUmp
commands should operate as described in Section IX of
this manual.
( ) If the ENter and DUmp commands do not operate correctly,
locate and correct the problem before proceeding.
( ) If the personality module is operating correctly, turn
the monitor and power off, disconnect power cable, video
output cable and keyboard, and if you are building a Sol
kit go on to Step 50 in Section III.
(The personality
module can be left plugged in.)
REV D
IV-8
v
.REV.. ,)\.'
KEYBOARD ASSEMBLY
5.1
Keyboard Assembly.
V-I
5.2
Keyboard Installation . .
V-I
PROCESSOR TECHNOLOGY CORPORATION
SECTION V
Sol KEYBOARD
5.1
KEYBOARD ASSEMBLY
The Sol keyboard is now supplied pre-assembled and tested
(Part No. 104000). Consequently, no assembly is required. An assembl~
drawing and a schematic (Drawings X-23 and 22 respectively in Section X) are provided, however, to facilitate maintenance and repair
should they become necessary.
5.2
KEYBOARD INSTALLATION
Installation instructions for the Sol keyboard are provided in
Steps 37 through 42 in Section VI.
The keyboard cannot be installed,
however, before you complete Steps 1 through 36 in Section VI.
(Note
that use of the keyboard is made in Step 59 of the Sol-PC assembly
procedure (Section III) and Step 11 of the personality module assembly
procedure (Section IV).
The keyboard need not be installed in the
cabinet chassis for this purpose.)
Having completed your Sol power supply, Sol-PC and personality
module, you are now ready to assemble the Sol cabinet-chassis. Complete cabinet-chassis assembly instructions are given in Section VI.
V-I
VI
Sol CABINET-CHASSIS ASSEMBLY
6.1
Introduction. • • . .
• • • VI-l
6.2
Parts and Components.
· • • VI-l
6.3
Assembly Tips . .
6.3.1
6.3.2
6.3.3
· VI-l
General. . .
Electrical .
Mechanical
· • • VI-l
· • • VI-l
· • . VI-S
6.4
Required Tools, Equipment and Materials • •
6.5
Orientation . •
6.5.1
6.5.2
6.6
· VI-6
VI-6
Sol Backplane Board, Sol-BPB
Sol Cabinet-Chassis . . • .
Assembly-Test • • . • • • .
. . ,.
. • . . • VI-6
· • • VI-6
...
6.6.1
Backplane Board (Sol-BPB) Assembly.
6.6.2
Sol Assembly . • • . . . • . . • . • .
• VI-6
. . • • VI-6
• VI-9
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
6.1
INTRODUCTION
This section covers assembly of the Sol-20 chassis and cabinet.
The instructions contained herein assume that you have already assembled the power supply and Sol-PC Single Board Terminal ComputerTM ...
including the personality module.
6.2
PARTS AND COMPONENTS
You will need the parts listed in Table 6-1 to assemble your
Sol cabinet-chassis. At this point in assembly, Table 6-1 should reflect the remaining parts in your Sol kit.
(Note that you may have
been supplied extra pieces of some hardware items, so do not panic
should-you have a few pieces of hardware ,left over after you have completed assembling your Sol-20.)
If you have any difficulty in identifying individual pieces of hardware, refer to Figure 6-1 and 6-2.
Table 6-1 lists each part, its description, quantity and reference
designation on the drawing(s) you will use in assembling the cabinetchassis. The assembly drawings in Section X will also prove useful
in identifying parts.
6.3
ASSEMBLY TIPS
-6.3.1
General
1. Scan Section VI in its entirety before you start to
assemble your Sol cabinet-chassis.
2. IT IS IMPORTANT that you follow the step-by-step instructions in the order given when assembling the Sol cabinetchassis if your assembly is to be done correctly and with minimum
effort.
3. ' Assembly steps and component installations are pre'-'
ceded by a set of parentheses. Check off each installation and
step as you complete them. This will minimize the chances of
omitting a step or component.
4. Should you encounter any problem during assembly, call
on us for help if needed.
6.3.2
Electrical
1. Use a low-wattage soldering iron, 25 watts maximum, for
all soldering.
2.
Solder neatly and as quickly as possible.
3. Use only 60-40 rosin-core solder.
solder or externally applied fluxes.
REV C
VI-l
NEVER use acid-core
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
Table 6-1.
Sol-20 Cabinet-Chassis Parts List.
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
Circuit Board
Sol Backplane
1
X-8
4
Cable Assembly
Sol Backplane, 3", 5-wire
I
X-IO
1
Connector
PC, 100-pin
1
X-8
5
Connector
PC, 100-pin
5
X-8
6
Plug
Coax, 75 ohm
1
Fig. 6-5
Sect. VI
Sleeve
Coax Adapter
1
Fig. 6-5
Sect. VI
Chassis
Main
1
X-8
11
Subchassis
Expansion
1
X-9
12
Bracket
Connecting, Power Supply Subchassis
1
X-9
13
Bracket
Keyboard Support
2
X-9
14
Bracket
Backplane, Right Angle
2
X-8
16
Bracket
Backplane, Left Gusset
1
X-8
17
Bracket
Backplane, Right Gusset
I
X-8
18
Card Guide
Plastic, 4"
10
X-8
34
Assembly
Left Side Panel
1
X-9
5
Assembly
Right Side Panel
1
X-9
6
Cover
Keyboard
1
X-IO
10
Cover
Top
1
X-IO
22
Cover
Logo, Plexiglass
1
X-IO
20
Label*
Sol Logo*
1*
X-IO
21
Label
Fingerwell, Black
2
X-9
28
Label
Connector Identification
1
X-8
29
Label
Serial Number
1
X-8
26
Foot
Rubber, Adhesive
4
Fig. 6-8
Sect. VI
Screw
Machine, 4-40 x 3/16
2
X-8
44
Screw
Machine, 4-40 x 5/16
16
X-8&9
39
Screw
Machine, 4-40 x 5/8
X-8
38
6
*May be packaged under logo cover.
REV C
VI-2
PROCESSOR TECHNOLOGY CORPORATION
Sol CABINET-CHASSIS
Table 6-1.
SECTION VI
Sol-20 Cabinet-Chassis Parts List.
(Continued)
REFERENCE
PART
DESCRIPTION
QUANTITY
Drawing
No.
Designator
16
X-8&9
48
X-8
56
X-8&9
51
L0ckwasher
Internal Tooth, #4
Lockwasher
Spring, #4
Hex Nut
4-40
Screw
Machine, metal, 6-32 x 1/2
8
X-9&lO
40
Screw
Self-tapping, 6-32 x 5/16
1
X-9
43
Screw
Sheetmetal, #6 x 1/4
X-8&9
45
Lockwasher
Internal Tooth, #6
X-8&l0
49
Washer
Flat, #6
X-8&9
56
Screw
Machine, 10-24 x 3/8
8
X-9
42
Screw
Machine, 10-24 x 1
2
X-9
41
Screw
Quick Connect, Knurled
2
X-IO
33
Cable
Flat, 20-wire
1
X-IO
23
Assembly
Keyboard
1
X-IO
3
Cable
AC Power, 3-wire
1
X-IO
36
Subassembly
Sol Power Supply
1
X-9
1
Subassembly
Sol-PC
1
X-IO
2
Subassembly
2708/9216 Personality Module
1
X-IO
8
REV C
8
16
32
8
18
VI-3
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
(A)
(B)
(C)
(D)
"- Washer
(A) Flat Head Wood Screw
(B) Sheet Metal Screw
Figure 6-1.
(C) Binder or Pan Head Screw
(D) Thumb Screw
Types of screws used in Sol cabinet-chassis assembly •
. . . . . . ---1
......
I
(J
()
0
(B)
(A)
(C)
(D)
(A) Keyboard Bracket
(B) Backplane Bracket, Right Angle
(C) Gusset Bracket, Left
(D) Gusset Bracket, Right
(E) Power Supply Subchassis Bracket
(E)
Figure 6-2.
Rev A
Brackets used in Sol cabinet-chassis assembly.
VI-4
PROCESSOR TECHNOLOGY CORPORATION
Sol CABINET-CHASSIS
6.3.2
SECTION VI
Electrical (continued)
4. DO NOT press the tip of the soldering iron on pads or
traces when installing components and/or attaching leads to a PC board.
To do so can cause the pad or trace to "lift" off the board and permanently damage it.
5. The Backplane PC board (Sol-BPB) has plated-through holes.
Solder flow through to the component side of the board can produce
solder bridges (shorts). Check for such bridges after you install
each component or wire.
6. The Backplane PC board (Sol-BPB) has an integral solder
mask (a lacquer coating) that shields selected areas on the board.
This mask minimizes the chances of creating solder bridges during
assembly.
6.3.3
Mechanical
1.
If you do aot have the proper screwdrivers (see Paragraph 6.4), we recorrunend that you buy them rather than using a knife
point, a blade screwdriver on a Phillips screw, and other makeshift
means. Proper screwdrivers minimize the chances of stripping
threads, disfiguring screw heads and marring decorative surfaces.
2. To assure a correct fit and tight assembly, be sure you
use the screws specified in the instructions.
3. Lockwashers are widely used in the Sol cabinet-chassis
assembly so that screws will not loosen when subjected to stress or
vibration. When a lockwasher is specified, do not omit it and make
sure you install it correctly.
4. Some instructions call for prethreading holes. This is
done to :nake assembly easier by giving you maxi:num working space for
installing relatively hard-to-drive sheet metal screws.
If you bypass prethreading instructions yo~ will only make your cabinetchassis assembly more difficult.
To prethread a hole, insert specified screw in the hole
and position it as straight as possible. While holding the screw in
this position, drive it into the metal with the proper screwdriver.
If started straight the screw will continue to go straight into the
metal so that the head and sheet metal surfaces are in full con"tac"t.
5. The diameter of the shank (threaded portion) of a screw
increases in relation to its number. For example, a 6-32 screw is
larger in diameter than a 4-40 screw. Also, a #8 lockwasher is
larger than a #4 lockwasher.
REV B
VI-5
PROCESSOR TECHNOLOGY CORPORATION
Sol CABINET-CHASSIS
6.4
SECTION VI
REQUIRED TOOLS, EQUIPMENT AND MATERIALS
The following tools, equipment and materials are recommended
for assembling the Sol cabinet-chassis.
(Unless indicated otherwise,
none of the following items are supplied with your kit.)
1.
Needle nose pliers
2.
Diagonal cutters
3.
Screwdriver, thin 1/4" blade
4.
Screwdriver, #2 Phillips
5.
Controlled heat soldering iron, 25 watt
6.
Ohmeter
7.
Masking tape
8.
Transparent tape
9.
Rubber mallet or small hammer
6.5
ORIENTATION
6.5.1
Sol Backplane Board, Sol-BPB
When the side without the solder mask (no green lacquer) is
facing you, the PC board identification (Sol-BPB) and revision level
will be located in the upper left-hand corner of the board when the
edge connector (gold contacts) is positioned at the bottom of the
board.
In this position, the component (front) side of the board
(no solder mask) is facing up.
Subsequent position references related to the Sol-BPB assume this orientation.
6.5.2
Sol Cabinet-Chassis
Unless specified otherwise, all position references (e.g.,
left, right, front, back, bottom and top) in the cabinet-chassis
assembly instructions assume the Sol cabinet is viewed from the
front (keyboard) when it is sitting in its normal position (keyboard up) •
6.6
ASSEMBLY-TEST
6.6.1
Backplane Board (Sol-BPB) Assembly
, Refer to Detail B on Drawing X-8 in Section X.
REV C
VI-6
PROCESSOR TECHNOLOGY CORPORATION
Sol CABINET-CHASSIS
SECTION VI
( ) Step 1. Visually inspect Sol-BPB PC board for obvious flaws
such as solder bridges (shorts) between traces, broken traces
and similar defects.
If visual inspection reveals any defects, return the board to
Processor Technology for replacement.
If the board passes
inspection, go on to Step 2.
( ) Step 2.
Install lOa-pin edge connector (Item 5 on Drawing
X-B) on top edge of PC board.
(This edge has silver (not
gold) contacts.)
NOTE
This connector is supplied as a troubleshooting aid.
It is not critical to
normal operation of the Sol-20.
position connector on PC board so that its #1 trace is aligned
with the #1 trace on the board, and push connector fully onto
board. Bend the connector pins slightly so that both rows of
pins are in light contact with the traces on the board. DO
NOT CLOSE CONNECTOR PINS SO MUCH THAT YOU WILL DAMAGE THE
TRACES WHEN PLACING THE CONNECTOR OVER THE EDGE OF THE BOARD.
While holding the connector and board together, place board
solder side down on a book, or other flat surface that is high
than your work surface, so the connector extends ~ully over
the edge. That is, the connector should not rest on the book.
Reposition connector if needed to align the pins and traces.
On the component (front) side of board, solder a pair of
traces. On the component (front) side of board, solder a pair
of pins at each end of the connector to their respective
traces on the board. Then solder the remaining 46 pins on the
component side to traces . .
The connector must be perpendicular to the edge of the board.
If it is not, bend the pins you just soldered to obtain the
required alignment. Then solder the other 50 pins to the
traces.
( ) Step 3.
Install the other five lOa-pin edge connectors. Position connector on front side of board (the side without the
green solder mask) and insert pins. On solder (back) side of
board (the side with the green solder mask), solder pins at
opposite corners-or-the connector to hold it in place while
making sure the entire connector is seated firmly.
Then
solder the remaining 9B pins.
( ) Step 4. First check that wire color code in Sol backplane
cable assembly (3" 5-wire cable) conforms with that given below and in Figure 2-7 on Page 11-21 in Section II. Then connect cable to circuit board to upper-most pads in top right
corner:
Insert wires from solder (back) side of board (green
REV C
VI-7
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
solder mask side) and solder on component (front) side of
board.
If a wire is too large for the mounting hole, snip off
as many individual strands as needed to obtain a fit. Connect
cable leads as follows:
CABLE LEAD
PAD
White
Ground (fifth hole from right)
White
Ground (fourth hole from right)
Blue
+8 V dc (third hole from right)
Red-White
+16 V dc (second hole from right)
Yellow-White
-16 V dc (first hole from right)
NOTE
Pad orientations given above are as viewed
from component (front) side of circuit
b'O'ard, the side without the green solder
mask.
( ) Step 5. Fill feedthrough holes on right-hand side of board
with solder. Fill only those that are exposed (not covered
with green lacquer)-on-the solder mask (back) side. Fill
these holes from the solder mask side so that no solder
protrudes above the back of the board.
( ) Step 6. Check +8-volt, +16-volt and -16-volt buses to insure they are not shorted to each other or to ground. Using
an ohmmeter, make the following measurements on one of the
edge connectors:
( )
+8-volt Bus Test. Measure between pins 1 or 51 and 50 or
100. There should be no continuity (meter reads close to
"infinity" ohms) .
( )
+16-volt Bus Test. Measure between pins 2 and 50 or 100.
There should be no continuity.
( ) -16-volt Bus Test.
Measure between pins 52 and 50 or 100.
There should be no continuity.
( ) 8/16/(-16) Volt Bus Test. Measure between pins 1 or 51
and 2, between pins 1 or 51 and 52, and between pins 2
and 52. There should be no continuity in any of the three
measurements.
REV C
VI-8
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
If you measure continuity (indication of a short) ~n any of
the preceding tests, check your work for solder brldges.
If you measure no continuity in any of the tests, you have
completed the backplane board assembly. Set it to one side
for later installation in the cabinet-chassis.
NOTE
Since the Sol right and left side panels
are now supplied as pre-assembled units,
Steps 7 through 12 have been eliminated.
6.6.2
Sol Assembly
Refer to Drawings X-8 through X-IO in Section X.
and 6-4 show complete Sol assemblies without covers.
Figure 6-3
( ) Step 13. Mount keyboard support bracket (heavy gauge right
angle brackets) to each side of the main chassis as shown in
Drawing X-9.
These are mounted with the narrower
side of the bracket at the top.
Attach each bracket to main chassis with two 6-32 x ~ binder
or pan head screws and #6 lockwashers. Place lockwasher on
screw, insert screw from outer surface of main chassis side
wall and drive into the threaded bracket mounting holes.
( ) Step 14. Attach power supply subchassis bracket (short
leg "T" shaped bracket) to top front of power supply subchassis as shown in Drawing X-9.
(Note that leg of
"T" is closer to side wall of subchassis. This leg is for
mounting a "power on" indicator light--not supplied.)
Insert #6 x ~ sheet metal screw from right side of side wall
and drive into bracket.
.
( ) Step 15. To gain access to the rear area of the power supply subchassis side wall, remove the #6 x 5/16 sheet metal
screw that attaches the fan closure plate to the subchassis.
You should not have to disconnect the transformer (black
wires) or AC receptacle ground (green wire) leads since they
have sufficient slack to permit moving the closure plate out
of the way.
(Set screw to one side for use in re-installing
the fan closure plate.)
REV C
VI-9
PROCESSOR TECHNOLOGY CORPORATION
Sol CABINET-CHASSIS
SECTION VI
Figure 6-3.
Sol-20 with covers removed. Front (or keyboard) is in
foreground, power supply is in right rear corner, expansion chassis (with 8KRA Memory installed) is to left
of power supply. The vertical board just behind white
connector on left is the backplane board.
Figure 6-4.
Sol-20 with covers removed.
Rear side of assembly is
in foreground and Sol-PC is just visible at lower right
rear of assembly. 8KRA Memory is installed in expansion
chassis above Sol-PC.
Rev A
VI-IO
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
( ) Step 16. Install power supply subchassis in main chassis as
shown in Drawing X-9.
Place subchassis over the right rear corner of main chassis
and lower it almost vertically into position. Attach subchassis to main chassis using seven #6 x 1/4 and one #6 x 5/16
sheet metal screws and five #6 flat washers. Five #6 x 1/4
screws, fitted with #6 flat washers, are driven through the
bottom of the main chassis into the subchassis. The #6 x 5/16
screw is driven through the rear hole in the right side of the
main chassis into the subchassis. The remaining #6 x 1/4
screws are driven through the main chassis into the subchassis.
( ) Step 17. Place right side walnut-masonite assembly in proper
position against right side of main chassis and outline the
finger well on the chassis. Remove backing from one black
finger well label and affix it to the right side of main
chassis. Position label to cover the finger well outline you
made. Be sure label extends beyond all edges of the outline.
( ) Step 18. Using five 10-24 x 3/8 binder or pan head screws,
attach right side assembly to main chassis and power supply
subchassis as shown in Drawing X-9.
Insert screws from inside
surface of chassis and drive into the plastic inserts. Note
that the two front screws are driven through the main chassis,
the two lower rear screws are driven through both the power
supply subchassis and main chassis, and the upper rear screw
is driven through the power supply subchassis.
( ) Step 19.
Assemble expansion chassis ("U" shaped chassis).
( ) Prethread 12 mounting holes (six on each side) on expansion chassis side walls for backplane brackets with
#6 x 1/4 sheet metal screws. Three of these holes on each
side are located near the front edge of the main chassis.
The remaining three holes on each side are about 1-1/2 to
2 inches behind the front three. Leave screws installed.
( ) Install female coaxial connector on the tab that extends
out from the lower right front of the expansion chassis.
Insert connector through tab so threaded end faces left
as shown in Drawing X-9.
Insert three 4-40 x 5/16 binder
or pan head screws from left side of tab through the two
front and lower rear mounting holes. Place #4 lockwasher
on each and secure with 4-40 hex nuts.
Insert another
4-40 x 5/16 binder or pan head screw through upper rear
mounting hole and install 4-40 hex nut.
(Leave this nut
loose. )
( ) See Details C and L on Drawing X-8.
Install 10 plastic
card guides (five on each side) on inside surface of both
side walls of the expansion chassis.
REV C
VI-II
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
These are installed over the ventillation cutout with the
gripper fingers pointing towards the backplane board. To
install, simply insert posts on guide into appropriate
mounting holes and push in until they snap into place.
( ) Step 20.
Install expansion chassis on main chassis as shown
in Drawing X-9.
Position expansion chassis with coaxial connector at the front
(near FWB3 on power supply subchassis) over left rear area
of main chassis and lower into place. Attach expansion chassis
to main chassis using nine #6 x 1/4 sheet metal screws and
five #6 flat washers. Five screws, fitted with #6 flat washers,
are driven through the bottom of the main chassis into the
expansion chassis, three are driven through the left side of
the main chassis into the expansion chassis, and one is driven
through the lower left corner of the back side of the main
chassis into the expansion chassis.
( ) Step 21. Attach left end of power supply subchassis bracket
to expansion chassis as shown in Drawing X-9. Drive one
6 x 1/4 sheet metal screw through expansion chassis into
bracket.
( ) Step 22. Route coaxial cable from connector on fan closure
plate along left side of power supply subchassis to connector
on expansion chassis.
( ) Step 23. Using the #6 x 1/4 sheet metal screw you removed in
Step 15, re-attach fan closure plate to power supply subchassis.
(Make sure side lip on plate is on right side of expansion
chassis side wall.
( ) See Drawing X-9. Attach fan closure plate to expansion chassis
with two #6 x 1/4 sheet metal screws. Drive screws through
expansion chassis into fan closure plate.
NOTE
If lip on fan closure plate and expansion
chassis are not in contact, insert one or
two 1/2" flat washers as needed between the
two surfaces. Place washers so screws pass
through them.
( ) Step 25. Connect free end of coaxial cable from connector
on fan closure plate to connector on expansion chassis.
Solder inner conductor to pin of connector. Remove hex nut
on upper rear connector mounting screw, place lug (coaxial
shield) and #4 lockwasher on screw, in that order, and secure
with nut.
REV C
VI-12
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
( ) Step 26.
Install male coaxial connector on free end of coaxial cable that is connected to Sol-PC (the composite video
output cable). Install connector as follows (refer to
Figure 6-5):
!:i"
3/4"
Q
t
Coupling
Ring
Adapter
Figure 6-5.
Braid
Plug Subassembly
Sol-PC coaxial cable connector assembly.
( ) Slide coupling ring and adapter on cable in that order
and cut end of cable even.
Remove one inch of outer insulation.
Fan braid slightly and fold back over outer insulation
as shown.
( ) Slide adapter fully up under braid and press braid down
over adapter body.
( ) Trim braid so that it does not interfer with adapter
threads.
( ) Remove 3/4" of inner conductor insulation and tin exposed conductor.
( ) Slide cable fully into plug subassembly and screw subassembly on adapter.
( ) Solder braid to plug subassembly shell through solder
holes.
(Use enough heat to create a good bond between
braid and shell.)
( ) Solder center conductor to plug contact by filling contact with solder. Cut off excess conductor.
( ) Slide coupling ring over plug subassembly and screw it
onto plug.
Rev A
VI-13
PROCESSOR TECHNOLOGY CORPORATION
Sol CABINET-CHASSIS
( ) Step 27.
SECTION VI
Install Sol-PC in expansion chassis.
Position Sol-PC on bottom of expansion chassis with Jl, J2
and J6 through J9 at the rear. Align threaded standoffs on
bottom of Sol-PC with the oblong holes in the bottom of the
main chassis.
Attach Sol-PC board to chassis with two 4-40 x 3/16 and six
4-40 x 5/16 binder or pan head screws, eight #6 flat washers
and eight #4 spring lockwashers as shown in Detail F on
Drawing X-8 in Section X.
(Note that the two shorter screws
attach to the same standoffs to which SIOO connector, Jll, is
attached.)
Place lockwasher and flat washer on screw in that
order and drive screw loosely into standoff from bottom of
main chassis. Leave all eight screws loose.
( ) Step 28. Connect Sol-PC composite video output cable to expansion chassis coaxial connector.
( ) Step 29. Affix black finger well label to left side of main
chassis in same manner as you did the right side.
(See Step
17.) MAKE SURE LABEL DOES NOT OBSTRUCT COOLING CUTOUT.
( ) Step 30. Using three 10-24 x 3/8 and two 10-24 x 1 binder or
pan head screws, attach left side assembly to main chassis as
shown in Drawing X-9.
Insert screws from inside surface of
chassis and drive into plastic inserts. Note that the two
front screws (10-24 x 3/8) are driven through the main chassis,
the uppermost screw (10-24 x 3/8) is driven through the expansion chassis, and the two lower rear screws (10-24 x 1) are
driven through both the expansion chassis and main chassis.
( ) Step 31. Install left and right backplane right angle brackets
(light gauge brackets) on expansion chassis side walls. Refer
to Figure 6-6 on Page VI-IS.)
These two brackets are installed just to the front of the card guides and should be
positioned as shown in Figure 6-6. Attach each bracket to
the chassis with three #6 x 1/4 sheet metal screws. USE THE
SCREWS YOU USED IN STEP 19 TO PRETHREAD THE HOLES.
( ) Step 32. See Detail B on Drawing X-8.
Install backplane circuit board (Sol-BPB). The photograph in Figure 6-7 on Page
VI-16 shows the backplane board installed.
( ) Position Sol-BPB with 100-pin male edge connector down
and the five female edge connectors facing the card
guides. The board should rest against the front face
of the right angle brackets as shown in Figure 6-6.
Adjust position of Sol-PC as needed so that you can plug
the Sol-BPB edge connector into Jll on the Sol-PC.
( ) Align holes on left and right ends of Sol-BPB with those
in right angle brackets.
REV B
(Step 32 continued on Page VI-16.)
VI-14
PROCESSOR TECHNOLOGY CORPORATION
Sol CABINET-CHASSIS
SECTION VI
Right Angle Bracket
/SOl-BPB
()
+
I"
Left
Gusset
Bracket
()
+.
"""""
~
Expansion Chassis
(Front)
Right /
Gusset
Bracket
*#6 x
~
sheet metal screw
+4-40 x 5/8 binder or pan head screw,
#4 lockwasher and 4-40 hex nut
Figure 6-6.
Rev A
Backplane board (Sol-BPB) installation.
VI-15
PROCESSOR TECHNOLOGY CORPORATION
Sol CABINET-CHASSIS
Figure 6-7.
SECTION VI
Backplane board (Sol-BPB) installation.
Rear of Sol is at bottom and Sol-BPB is
to right of power supply subchassis in
line with C8 and transformer.
(Step 32 continued)
( ) See Detail E on Drawing X-S. Attach Sol-BPB to brackets with
three 4-40 x 5/16 binder or pan head screws, #4 lockwashers
and 4-40 hex nuts on each side.
Insert screws from the back
side of bracket through Sol-BPB, place lockwasher on eac-h--screw and secure each with nut.
( ) Step 33.
Install left and right gusset brackets as shown in
Figure 6~6 on Page VI-IS.
( ) Fit narrower gusset bracket on left side so that its
flanges are flat against the expansion chassis side
wall and the backplane board.
(You may have to bend the
flange slightly to obtain a proper fit.)
( ) Attach bracket to expansion chassis side wall with the
three #6 x ~ sheet metal screws you used in Step 19 to
pre thread the holes.
**See WARNING on Page VI-17.**
(Step 33 continued on Page VI-17.)
REV B
VI-16
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
(Step 33 continued.)
WARNING
IT IS QUITE EASY TO SCRATCH OR CUT YOUR
HAND ON THE SOLDER SIDE OF THE BACKPLANE
BOARD WHEN DRIVING THESE SCREWS. PLACE
A SUITABLE PROTECTIVE BARRIER, SUCH AS
CARDBOARD, AGAINST SOLDER SIDE OF BACKPLANE BOARD DURING INSTALLATION TO PREVENT SUCH INJURY.
( ) See Detail E on Drawing X-S. Attach bracket to backplane
board with three 4-40 x 5/S binder or pan head screws, #4
lockwashers and 4-40 hex nuts.
Insert screws from front
side of bracket through Sol-BPB, place lockwasher on each
screw and secure each with nut.
( ) Install wider gusset bracket on right side in the same
manner as you did the left bracket. THE PRECEDING WARNING ALSO APPLIES TO INSTALLING THIS BRACKET.
( ) Step 34. Connect Sol-20 DC power cable from power supply
subchassis to the Sol-BPB power cable you installed in
Step 4.
( ) Step 35. Check that Sol-PC is in optimum position and tighten
the eight screws holding the Sol-PC to the expansion-main
chassis assembly.
(See Step 27.)
( ) Step 36. Connect Sol-PC power cable (4-wire) to JIO on Sol-PC.
CAUTION: Make sure cable connector mates exactly with JIO.
( ) Step 37. See Drawing X-IO. Position keyboard (Sok-KBD) near
its mounting brackets and connect 20-conductor ribbon cable
supplied with Sol
keyboard
between Jl on keyboard and J3
on Sol-PC. With the cable connected properly, the cable will
run away from the keys from Jl on the keyboard, and towards
the keys from J3 on Sol-PC.
( ) Step 3S. See Drawing X-IO. Attach keyboard to keyboard
brackets with two 6-32 x 1/2 binder or pan head screws and
#6 lockwashers on each side. Place washer on each screw and
drive screws loosely into threaded holes in brackets.
REV C
VI-17
PROCESSOR TECHNOLOGY CORPORATION
Sol CABINET-CHASSIS
SECTION VI
( ) Step 39. See Drawing X-IO. Remove protective cover from one
side of Plexiglass strip and attach "Sol Terminal Computer"
trim plate to Plexiglass with small pieces of transparent
tape. Place trim plate with printed side against Plexiglass.
( ) Step 40. See Drawing X-IO. Remove protective cover from
other side of Plexiglass and slide it into the channel above
the keyboard cutout.
NOTE
A hole is provided in the sheet metal behind the trim plate. This may be used for
a "power on" indicator light if desired.
( ) Step 41. Refer to Drawing X-IO. Install keyboard cover. Hook
front of cover under front edge of main chassis and lower it
over the keyboard.
(A slight adjustment of the keyboard position may be needed to obtain a proper fit.)
Position keyboard within cutout in cover if needed and tighten
keyboard mounting screws.
( ) Step 42.
Install top cover.
( ) Be sure power cord is not plugged into 110 V ac outlet
and disconnect cord from fan closure plate receptacle.
( ) Remove fuse holder cap and fuse.
CAUTION
NEVER REMOVE OR INSTALL FUSE WITH POWER ON •
. ( ) See Drawing X-IO. Hook top cover over back edge of key-'
board cover and lower it down into place over the rear of
the main chassis. Install the two thumb screws (one at
the lower left corner and the other to the right of the
fan closure plate coaxial connector) to attach cover to
rear of main chassis.
( ) Step 43. Re-install fuse and plug power cord into receptacle.
BE SURE POWER CORD IS NOT PLUGGED INTO 110 V ac OUTLET.
See CAUTION on Page VI-19.
REV B
VI-18
PROCESSOR TECHNOLOGY CORPORATION
SECTION VI
Sol CABINET-CHASSIS
(Step 43 continued.)
CAUTION
NEVER REMOVE OR INSTALL FUSE WITH POWER ON.
( ) Step 44. Remove backing from connector identification label
and affix it to rear of top cover. Position label just above
Sol-PC connector opening in cover so that "J9" is aligned
with left-most (as viewed from rear of Sol) subminiature
phone jack and "Jl" is aligned with right-most 25-pin female
connector.
( ) Step 45. See Detail A on Drawing X-B. Remove backing from serial
number label and affix it to rear of top cover. Position label t
right (as viewed from rear of Sol) of fan opening in cover.
( ) Step 46. Affix self-stick protective pads to bottom of Sol as
shown in Figure 6-8.
You have now completed assembly of your Sol Terminal Computer™.
It is ready for use as a stand-alone computer or CRT terminal. Congratulations on a job well done. Proceed now to Section VII to test
and learn to operate your Sol.
Bottom
of
Sol
® Protective
Pads
Front
Figure 6-8.
REV B
Protective foot pad installation.
VI-19
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII, Sol OPERATING PROCEDURES
PARAGRAPH
CONTENTS
TITLE
7.1
INTRODUCTION
VII-l
7.2
THE OPERATING CONTROLS
VII-l
7.3
BASIC OPERATING MODES •
7.3.1 COlnmand Mode • •
7.3.2 Terminal Mode . • • • •
VII-l
VII-I
VII-4
7.4
GETTING ACQUAINTED WITH Sol . •
7.4.1 Monitor and Cassette Recorder Connections
7~4.2
Terminal Mode Operation
7.4.3 Command Mode Operation • . • • • • • • •
VII-4
VII-S
VII-10
OPERATING CONTROLS IN DEPTH • .
VII-12
7.S
0
• • • • • • •
• •
7.S.l
7.S.2
7.S.3
0
•
ON-OFF Switch • . • • . • . • • • •
Restart (RST) Switch, Sl-l • •
Control Character Blanking (BLANK)
Switch 81-3 . . . . . . . . . . . . . . . .
7.S.4 Video Display (POLARITY) switch, Sl-4 • • •
7.S.S Cursor Selection (BLINK, SOLID)
Switches, Sl-S & 6 •
7.S.6 Sense (SSW¢ - 7) Switches; S2 ..... lthrough S2-8
7.S.7 Baud Rate switches, S3-l·thrqugh S3-8 • • .
7.S.8 Parity (PS, PI) Switches, S4-L& S •.••
7.S.9 Data Word Length (WLS-l & 2)
Switches, S4-2& 3 . o • . ~ . . . . . . . .
7.S.l0 stop Bit Selection (SBS) Switch, S4-4 • . •
7.S.ll Full/Half Duplex (F/H) Switch, S4-6 • • • •
• • •
7.S.l2 Keyboard • • .• • • • • • •
0
• • • • • •
I
0
7.6
THE KEYBOARD, GENERAL DESCRIPTION ;; •
7.6.1
7.6 .. 2
7.7
• • • • • • • •
0
0
•
0
0
••
•
Operating Features • . .....
Keyboard Indicators
• • • • • • •
0
0
• • •
0·.
•
VII-4
VII-13
VII-13
VII-13
VII-13
VII-13
VII-13
VII-14
VII-14
VII-14
VII-14
VII-1S
VII-16
VII-16
VII .... 16
VII-16
INDIVIDUAL KEY DESCRIPTIONS •
• • •
VII-17
7.7.1 .Alphanumeric-Punctuation"";Symbol Keys • • • • VII-17
7.7.2 Space Bar • • • . •
• • • • • •
VII-21
7.7.3 Arithmetic Pad Keys • • • • • • • •
• • VII-2l
7.7.4 ESCAPE Key
VII-22
7.7.5 BREAKK~y.
VII-22
7.7.6 TAB Key •
• • •••• • • •
VII-22
7.7 .7 Control(CTRL):K~Y.. ••• o~o. o~.
VII.-22
7.7..8 SHIF'J:Key and.SHIFTLqCK.:Key/In¢iic:~tor • . • VII-22
:7 ..tr.g· .' UPPER·C~SE Key/IndicatOr.··~.. .' /~..
•• ·"Y:l:I-22 .
7.T~lO LOCAL· Key/Indicator . .~;;::~ .... ;;;.;;. .• ,;. .. ~ .•.; ... ~.': ..··"II-24
.0
•
.0
0
•
•
•
•
0
•
•
•
•
•
•
•
0
0
•
•
••
~f~k~1;,~!tq~~ ., .,. "'i\':*·;~~~~;,1;;;;~·i;~~~1~~~f41,~,t(Kii~~~~/,!,i·;.~:~~;i~L~l\.i .
11
7,.7.12
7 .7.13 ' K e y ..
7.7.14 REPEAT, Key'. • ,. • •
7.7.15 MODE SELECT Key '. •
7.7.16, CI..EAR Key • • . . ' .
7.7.17 Cursor Control (HOME
7.8
7.9
VII-24'
• ~"',VII-24
• • • • • • VII-24
• • • .'. • •• ••
VII-24
• • ., • • • • • • • • • VII-24
• ,. • ,. • • . . , . . . • • VII-24
CURSOR and Arrows) Keys VII-25
.' . . . . . . . . . . . . .
BASIC OPERATIONS
7.8.1 switching From Terminal To Command Mode • •
7.8.2 Switching From Command To Terminal Mode
7.8.3 Entering Commands In The Command Mode • • •
7.8.4 Keyboard Restart • • •
• • • • • • • • •
VII-25
Sc>l,...PERIPHERA;L INTERFACING
• •• • • • • • • •
VII~26
Audio Cassette Recorders • • • • • • • • • •
Recorder Selection • • •
• . . . • •
Operating Tips. • •. •
Interconnect Reguirements.
Write Operations
"Read Operations . .
VII-26
~
7.9~1
0
0
7~g~2
7.9.3
7.10
•
..
•
••
0
•
'0
0
•
0
•
•
•
•
0
••
0
•
•
••
•
•
•
•
0
•
•
•
•
• •
•
•
•
Serial Data Interface (SDI). •
Parallel Data ltiterface (PDI).
CHANGING THE FUSE . . • •
•
0
0
•
•
0
VII-25
VII-25
VII-25
VII-26
VII-2,6
V1I j 27
VII~27'
vi'i';';2S,
VII~28
VII-3d
VII';:'3i:
•
VII....;J3
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
7.1
INTRODUCTION
Information in this section will help YO¥Mto become familiar
with the operation of your Sol Terminal Computer r. Following brief
explanations of the operating controls and the two basic operating
modes, you will put your Sol through some simple operations. This
should sufficiently acquaint you with the keyboard and control
switches so that you will feel at ease with your Sol. In addition,
you will have performed functional tests of all Sol sections except
the parallel data interface.
Detailed descriptions of the control switches are also provided to allow you to gain greater proficiency in their use. For
the same reason, individual keyboard key descriptions are also given.
They are intended to be used along with the BASIC/5 and SOLOS Users'
Manuals.
The balance of this section supplies instructions for 1)
connecting typical peripheral devices to the serial and parallel data
interfaces (Jl and J2), 2) using audio cassette recorders, and 3)
changing the fuse.
702
THE OPERATING CONTROLS
Sol operating controls are identified and their functions
briefly defined in Table 7-1 on Page VII-2. Unless noted otherwise,
the location of each control is shown on the Sol-PC assembly drawing
in Section X, Page X-So
7.3
BASIC OPERATING MODES
7.3.1
Command Mode
In this mode Sol operates as a stand alone computer under
control of the program (software) contained in the personality module
and additional software that is stored in the Sol, stored either in a
read only memory (ROM) that is plugged into the computer or the Sol
random access memory (RAM). For a description of the SOLOS monitor
program, refer to SOLOS/CUTER User's Manual respectively.
with the SOLOS Personality Module installed, the computer is
in the command mode when power is applied to the Sol. Command mode
is a sort of "home base" from which excursions may be made into other
programs. An analysis of three levels of programs will make the concept of command mode more understandable.
At the lowest level of software are the instructions which
the 8080 CPU (central processing- unit), the brains of the computer,
REV A
VII-l
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
Table 7-1.
SECTION VII
Sol Operating Controls and Their Functions.
r----------------------r-----------------------------------------------------CONTROL
FUNCTION
ON-OFF Switch
(See Figure 7-1)
Connects and disconnects primary power to Sol.
RST (Restart)
Switch, Sl-l
Permits manual restart of Sol without turning
power off.
(Useful for test purposes.)
BLANK Switch,
Sl-3
Determines if control characters are displayed
or not.
POLARITY Switch,
Sl-4
Selects normal (white characters on black
background) or reverse video display.
BLINK-SOLID
Switches, Sl-5 & 6
Selects blinking, nonblinking or no cursor.
SSW¢ - 7
S2-l through 8
Permits direct data entry to processor.
BAUD RATE Switches,
S3-l through 8
Sets operating speed of serial data interface
(SDI).
PS & PI Switches
S4-l & 5
Selects no parity, even parity or odd parity
for SDI.
WLS-l & 2 Switches,
S4-2 & 3
Selects number of data bits in transmitted
word for SDI.
SBS Switch,
S4-4
Determines number of stop bits in transmitted
word for SDI.
FIR Switch,
S4-6
Keyboard
(See Drawing X-20)
Selects half or full duplex operation for SDI.
Data entry, mode selection, command input and
cursor control.
can understand and run. All programs must ultimately be reduced to
this basic level to be operated on by the computer. In the case of
the 8080 microprocessor, the program is in an "object code" or "machine language", since the "machine" or 8080 CPU understands it. The
SOLOS program contained in the personality module is stored in this
machine language form, and the computer can therefore run directly
from this program. Since the SOLOS program is contained in permanent
ROM which is plugged directly into the computer, the SOLOS program is
always available, and is automatically selected whenever the power
switch of the Sol is turned on. There is also provision for returning at all times to the command mode of SOLOS. From the command mode
other programs may be brought in for various operations or stored on
cassette tape. The contents of the computer's memory may be displayed or changed. The command mode also performs "housekeeping"
functions such as setting the rate at which data is read from tape,
or the rate at which characters are displayed on the video'monitor.
REV A
VII-2
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
The command mode allows the introduction of the second level
of software. This level includes higher-level language programs such
as BASIC/5 or FOCAL in which complex application programs may be more
easily written. These are called higher level languages because they
permit the user to write programs in a form much closer to human languages such as English. However, programs written in these languages
must be translated into the more basic machine language before they
can be run. Besides higher level languages, this second level of
software includes programs such as the TREK 80 and GAMEPAC video
games and the ALS-8 program (a software package used for developing
programs), all of which are offered by Processor Technology Corporation. Through the facilities of the command mode, these second level
programs are transferred (loaded) into memory from cassette tape or
other storage media, and then "executed" (used). These programs may
also exist in ROM or EPROM (erasable programmable ROM) memory which
is plugged into the computer to make them instantly available like
the SOLOS program. All first and second level programs are stored
in the computer as binary object code.
Let us illustrate the concept of the second level of programs
with an example, BASIC/5. Using the "XEQ" command available in the
SOLOS cOlnmand mode, we load the BASIC/5 program into the computer's
memory from cassette tape. With this command BASIC/5 is ready
for use as soon as the tape has stopped moving.
The control of the
computer is now taken over by the BASIC/5 program now in memory, and
SOLOS is no longer in command. All the features of BASIC/5 language
are now available to us, with a new set of commands and rules.
Since
the CPU of the computer only understands the machine language of the
first level of software, the BASIC/5 program must translate the commands and data we enter to this lower level. BASIC/5 does this as we
go. While we are using BASIC/5, we still have access to some of the
commands and features of SOLOS, although they may have a modified
form while we are in BASIC/5. We will load and use BASIC/5 later in
this section.
The third level of software consists of programs written
using the higher order languages of the second level programs. A
program written in BASIC/5 is on this third level. This program only
makes sense to the computer while the computer has BASIC/5 in memory
and control has been transferred to the BASIC/5 program. Third level
programs written in any high level language are often called "applications programs" since they are usually written in order to fit a
specific application need.
The ALS-8 Program Development System is another second level
program. A program to be developed within ALS-8 would then be a
third-level application program. The ALS-8 also includes an Assembler which takes a program written on the third level in "assemblyll
language, and translates it to object code which the computer can
run. The object code version then resides in memory and can be run
in another operation. For a further discussion of types of software
see the article "Your Personal Genie ll in-Appendix VIII of this manual
VII-3
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
7.3.2
SECTION VII
Terminal Mode
Sol operates as a CRT terminal in this mode, capable of sending keyboard data to an output port and displaying data received at
the serial input port on an external video monitor via the Sol video
display circuitry. When Sol is "hard-wired" to another computer or
connected to a modem, the terminal mode is used for data entry, data
retrieval, inquiry/response and monitoring and control applications.
SOLOS Personality Modules permit operation as a CRT terminal.
SOLOS 1) enters the terminal mode when given the "TERM" (terminal)
command and 2) sends keyboard data to any output port available with
the "SET 0" (set out) command.
7.4
GETTING ACQUAINTED WITH Sol
One of the best ways to get acquainted with your Sol is to
use it. After connecting a cassette recorder and video monitor to
your Sol, you will operate the system in the terminal mode to become
familiar with the keyboard and the functions of the video display
switches. You will then switch to the command mode and perform some
of the basic computer operations.
7.4.1
Monitor and Cassette Recorder Connections
The basic Sol system consists of the Sol, a video monitor for
display (e.g., the Processor Technology PT-872 TV-Video Monitor by
Panasonic) and a cassette recorder for external storage (e.g., the
Panasonic Model RQ-4l3S or Realistic CTR-2l).
NOTE
Refer to Paragraph 7.9.1 on Page VII-26
before connecting your cassette recorder
into the basic Sol system.
To connect these three system components, you will need the
following cables:
Audio In & Out Cables--two cables of shielded wire fitted
with miniature phone plugs at both ends.
Motor 1 Cable--one cable pair, such as speaker wire, fitted
with subminiature phone plugs at both ends.
(An identical
cable for Motor 2 is needed if you use two recorders.)
Video Cable--one RG59/U coaxial cable fitted with a PL259
UHF male connector on one end and a monitor-compatible
connector on the other.
Connect the basic Sol system as follows
on Page VII-6) :
REV A
VII-4
(refer to Figure 7-1
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
) Step 1.
Remove top and keyboard covers from Sol.
Step 2. Plug one end of Audio In Cable into Audio IN jack
(J7) on Sol rear panel, and plug other end into MONITOR or
EARPHONE jack on recorder.
( ) Step 3. Plug one end of Audio Out Cable into Audio OUT jack
(J6) on Sol rear panel, and plug other end into AUXILIARY
jack on recorder.
NOTE
The use of the MICROPHONE input is no
longer recommended.
( ) Step 4. Plug one end of Motor 1 Cable into Motor 1 jack (J8)
on Sol rear panel, and plug other end into REMOTE jack on
recorder.
( ) Step 5. Connect PL259 UHF connector on Video Cable to video
output connector on Sol rear panel, and connect other end to
video monitor input connector.
( ) Step 6. Make sure monitor, recorder and Sol power switches
are in their OFF position. Then connect AC power cord to AC
receptacle on Sol rear panel and connect Sol, monitor and
recorder to appropriate power source.
7.4.2
Terminal Mode Operation
The following procedure assumes your Sol is equipped with a
SOLOS personality module.
( ) Step 7. Set Sol control switches as follows (see Figure 7-2
on Page VII-7):
RST Switch (Sl-l):
Sl-2 (spare):
OFF
OFF
BLANK Switch (Sl-3):
OFF (display control characters)
POLARITY Switch (Sl-4):
OFF (reverse video display)
BLINK Switch (Sl-5):
OFF (solid cursor)
SOLID Switch (Sl-6):
ON (solid cursor)
(Step 7 continued on Page VII-7.)
REV A
VII-5
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
.... Left
Sol REAR PANEL
~
D
o /
ON-OFF SWITCH
~FUSE
AC RECEPTACLE
VIDEO
fQl
r OUTPUT
~
~L-__~~~~~~~(~~
J2
Parallel
. Inter
(A)
PL259 UHF
CONNECTOR ~ ~~~
/'
(A) Subminiature Phone Plug
(B) Miniature Phone Plug
(C) Monitor-compatible
Connector
RG59/U
Coax
Cable
)
Motor
Cable
(B)
(A)
o
0
0
REMOTE MONITOR AUX IN
Require
Seperate
Power
Source
~o
Monitor
Video Input
Video Monitor
Figure 7-1.
Cassette Recorder
Connecting the basic Sol system ..
VII-6
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
1 2 345 6
SECTION VIr
1 2 345 6 7 8
1 2 345 6 7 8
REAR
OF Sol
on
6 543 2 1
Figure 7-2.
FRONT OF Sol
Sol control switch settings for terminal mode.
(Step 7 continued.)
SSW Switches (S2-1 - 8):
OFF
BAUD RATE switches (S3-1 - 8):
SDI Switches (S4-1 - 6):
S3-4 ON, all others OFF
(300 Baud)
OFF (selects full duplex operation,
8 data bits, 2 stop bits and no
parity)
VII-7
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
Step 8.
Turn Sol and monitor on.
Step 9. If the monitor display raster is out of sync (black
horizontal bar moves slowly down screen, numerous black lines
cut across raster, or both), adjust monitor vertical and
horizontal hold controls for a stable raster.
( ) Step 10. You should see a prompt character followed by the
cursor ( )1) in the upper left corner of the screen. If you
don't, adjust VRI and VR2 (see Figure 7-3) to move the prompt
character and cursor onto the screen.
Use VRI (horizontal position) and VR2
(vertical position) to center the display
page (16 lines, 64 characters/line) on the
screen.
SOl-PC~
o
~
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
Table 7-4.
Sol Keyboard Assignments.
(Continued)
HEXADECIMAL CODE/CHARACTER GENERATION
KEY #
STANDARD KEYS
UNSHIFTED
Symbol
Hex. Displayed*
Code
6574 6575
SHIFTED
. Symbol.
Displayed*
Hex.
Code
6574
6575
(Continued)
P
OF
10
B
SI
DL
\
\
00
None
None
4Line
Feed
None
CR
Line
Feed·
None
OD
~eturr
Return
Line
Feed
None
Line
Feed
None
None
None
None
None
SH
0
6F
0
0
4F
0
0
P
70
I\
P
P
50
P
40
@
@
60
RETURN
LINE FEED
OD
OA
4Line
Feed
None
CR
Line
Feed
None
@
CTRL
SHIFT LOCK
CONTROL
Symbol
Hex. .Displayed*
Code
6574 6575
None
OD
OA
None
.
None None
OA
None
0
None
A
None
61
a
a
41
A
A
None
01
S
73
s
s
53
S
S
13
6)
D3
D
64
d
d
44
D
D
04
~
ET
F
66
f
f
46
F
F
06
\/'
~
G
67
g
g
47
G
G
07
5t
BL
H
68
h
h
48
H
H
08
J
6A
j
j
4A
J
J
OA
Line
Feed
K
6B
k
k
4B
K
K
OB
L
6C
1
L
L
OC
3B
I
.
4C
I+
I*
.
1
t
BS
Line
Feed
VT
I
2B
+
+
OB
3A
:
:
2A
*
*
OA
1-
7F
None
5F
None
None
None
None
None
None
None
None
None
None
None
None
None
SHIFT
None
None
None
Z
7A
z
X
78
x
z
x
C
63
c
c
~
:
DEL
REPEAT
CTRL
UPPER CASE
I
~.
IF
C9
FF
VT
Line
Feed!
U'
S
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
5A
None
None
None
Z
Z
None
lA
58
X
X
18
X
None
SB
CN
43
C
C
03
-'
Delete Delet.e
*See notes at end of this table, Page VII-2l.
VII-19
~
~
Llne
Feed
~
Ex
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
Table 7-4.
SECTION VII
Sol Keyboard Assignments.
(Continued)
HEXADECIMAL CODE/CHARACTER GENERATION
UNSHIFTED
Symbol..
Hex. Displayed*
Code 6574 6575
KEY #
STANDARD KEYS
SHIFTED
Symbol
Displayed*
Hex.
Code 6574 6575
CONTROL
Symbol
Hex. Displayed*
Code 6574 6575
(Continued)
n
Sy
V
76
v
v
56
V
V
16
B
62
b
b
42
B
B
02
l.
Sx
N
6E
n
n
4E
N
N
OE
@
So
M
60
m
m
40
M
M
OD
2C
,
,
.
3E
<
>
<
>
OC
2E
.
3C
.
<
>
/
?
2F
/
/
3F
?
None
None
None
None
None
None
None
20
None
,
SHIFT
LOCAL
Space Bar
iReturn Ret u,rrr
FF
OE
t
@
?
OF
0
SI
None
None
None
None
None
None
None
None
None
None
None
None
20
None
None
20
None
None
-
2D
-
2D
-
-
*
2A
*
*
2A
*
*
/
/
2F
/
/
So
ARITHMETIC PAD KEYS
-
2D
*
2A
··
2F
/
/
2F
7
37
7
7
37
7
7
37
7
7
8
9
38
8
8
38
8
8
38
39
9
9
39
9
9
39
8
9
8
9
4
34
4
4
34
4
4
34
4
4
5
35
5
5
35
5
5
35
5
6
36
6
6
36
6
6
36
6
5
6
1
31
1
1
31
1
1
31
1
1
2
32
2
2
32
2
2
32
2
2
3
33
33
3
3
30
¢
¢
2E
.
2E
.
¢
·
.
30
3
¢
3
30
3
¢
33
¢
3
¢
2B
+
+
2B
+
+
+
*
VII-20
.
2E
.
+
2B
+
.
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
Table 7-4.
Sol Keyboard Assignments.
(Continued)
HEXADECIMAL CODE/CHARACTER GENERATION
Sy~ol
Hex.
Code
CONTROL
SHIFTED
UNSHIFTED
KEY#
Displayed*
6574
6575
Hex.
Code
Symbol
Q.tsplayed*
6574
6575
Hex.
Code
Symbol
r;>isplayed*
6574
6575
SPECIAL KEYS
LOAD
8C
None
FF
8C
None
FF
8C
None
FF
MODE SELECT
80
None
None
80
None
None
None
None
97
None
None
97
None
None
80
97
None
None
81
None
None
81
None
None
81
None
None
93
None
None
93
None
None
93
None
None
+
None
None
9A
None
None
9A
None
None
HOME CURSOR
9A
8E
None
None
8E
None
None
8E
None
None
CLEAR
8B
None
None
8B
None
None
8B
None
None
t
.~
#Vertical line between characters indicates dual character key.
"None"
*Character generated is displayable and transmittable.
means no code is generated or no symbol is displayed. Return is _
defined in Section 7.7.11, and line feed in Section 7.7.12, on
page VII-24.
7.7.2
Space Bar
pressing the Space Bar, shifted or unshifted, generates the
ASCII space code (2¢) and moves the cursor one space to the right.
7.7.3
Arithmetic Pad Keys
Except for the division symbol key (:), these keys enter the
applicable character into the Sol. The division symbol key enters a
forward slash (/) character. SHIFT does not affect these keys.
The arithmetic pad is useful for entering large amounts of
numerical data. Each key in the pad duplicates its corresponding
numeric, period (decimal point), dash (minus), plus (addition),
asterisk (multiplication) and forward slash (division) key in the
"typewriter ll group of keys. That is, pressing one of the pad keys
does the same thing as pressing its corresponding key in the IItypewriter ll group.
VII-21
PROCESSOR TECHNOLOGY CORPORATION
SECTION·VII
Sol OPERATING PROCEDURES
7.7.4
ESCAPE Key
Pressing ESCAPE, shifted or unshifted, generates the ASCII
escape character (lB). The character is displayed.
7.7.5
BREAK Key
Pressing BREAK, shifted or unshifted, forces the SDI output
line to a space level for as long as the key is depressed. No character is displayed.
(Some communications systems use this feature.)
7.7.6
TAB Key
Pressing TAB, shifted or unshifted, generates the ASCII hor,izontaltab character (¢9). The character is displayed.
7.7.7
Control (CTRL) Key
CTRL, shif,ted or unshifted, is used with alphanumeric, punctuation and symbol keys to initiate functions or generate the characters
defined in Table 7-4. Table 7-5 defines the ASCII control characters.
The characters in Table 7-5 are not always displayed on the video monitor.
A control sequence (e.g., CTRL plus J, which produces ASCII
line feed) requires that CTRL be pressed first and held down while
the other key or keys are pressed in sequence.
7.7.8
SHIFT Key and SHIFT LOCK Key/Indicator
The SHIFT key generates no code and is thus not displayed.
It
is interpreted as a direct internal operation, and when pressed specifically shifts the keyboard from lower case to upper case and from
the lower to upper character on dual character keys as on a typewriter.
The keyboard remains in upper case as long as SHIFT is held down.
Pressing SHIFT LOCK to turn the indicator light on electronically locks the SHIFT key in the upper case position. Again, no code
is generated and no character is displayed. Pressing SHIFT returns
the keyboard to lower case and causes the SHIFT LOCK indicator light
to go out.
7.7.9
UPPER CASE Key/Indicator
Pressing this key, shifted or unshifted, to turn the indicator light on activates the upper case keyboard function so that all
alphabetic characters entered from the keyboard, regardless of SHIFT
key status, are transmitted as upper case characters.
(Dual character keys, however, do respond to the SHIFT key.)
With the indicator light on, the Sol keyboard essentially simulates a teletype (TTY)
keyboard.
.
Pressing UPPER CASE to turn the indicator light off returns
the keyboard to normal SHIFT key operation.
VII-22
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
Table 7-5.
HEXADECIMAL
CODE
SECTION VII
Control Character Symools and Dt2finitions.
SYMBOL GENERATED BY
6574 Generator
6575 Generator
06
~
AI<
07
08
18
5t
BL
DEFINITION
Acknowledge
Bell
+y
BS
X
CN
Backspace
Cancel
OD
11
+(9
CR
Dl
Carriage Return
Device Control 1
12
CD
D2
13
14
6)
E!)
D3
D4
Device Control 2
Device Control 3
Device Control 4
~
f2I
B
-I
DL
EB
Delete
Data Link Escape
End of Transmission Block
e
EC
Escape
05
jgI
EM
EQ
End of Medium
Enquiry
04
~
.-J
ET
End of Transmission
EX
End of Text
FF
FS
Form Feed
File Separator
GS
Group Separator
7F
10
17
IB
19
03
OC
,
~
ID
eJ
EiJ
09
OA
--
lC
15
00
IE
lA
01
OF
-.
LF
'--\-
D
U3
,
r
@
02
16
®
1..
Il.
IF
'[9
OB
t
OE
HT
NK
NU
RS
SB
SH
SI
SO
SX
SY
US
VT
VII-23
. Horizontal Tab
Line Feed
Negative Acknowledge
Null
Record Separator
Substitute
Start of Heading
Shift In
Shift Out
Start of Text
Synchronous Idle
Unit Separator
vertical Tab
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
7.7.10
LOCAL Key/Indicator
The LOCAL key internally connects the SDI output to the SDI
input and disables serial transmission. No character is displayed.
Pressing LOCAL, shifted or unshifted, to turn the indicator light on
sets Sol for local operation. Keyboard entries are not transmitted,
but they are "looped back" to the SDI input for display. That is, Sol
is not on "line". Pressing LOCAL to turn the light off ends local operation. This corresponds to the local/line operation of a TTY.
7.7.11
RETURN Key
Pressing RETURN, shifted or unshiftGd, generates the ASCII
carriage return character (¢D) , which is not displayed, and moves the
cursor to the start of the line on which it resided prior to RETURN
being depressed.
(This is the same action as a TTY carriage return.)
RETURN also erases all data in the line to the right of the cursor.
7.7.12
LINE FEED Key
Pressing LINE FEED, shifted or unshifted, generates the ASCII
line feed character (¢A), which is not displayed, and moves the cursor
vertically downward one line.
(This is the same action as a TTY line
feed.)
Line feed action does not erase any data in the line to the
right of the cursor.
7.7.13
LOAD Key
The LOAD key character is displayed, but the key is nonfunctional with SOLOS. The code generated by this key is ac, and
it may be used by a program to meet a specific need.
7.7.14
REPEAT Key
The REPEAT key generates no character and is consequently not
displayed. Pressing REPEAT, shifted or unshifted, and another key at
the same time causes the other key to repeat at an approximate rate
of 15 times per second as long as both keys are held down. Pressing
REPEAT at the same time as UPPER CASE performs a restart. See Section
7.5.2 on page VII-13.
7.7.15 MODE SELECT Key
Pressing this key, shifted or unshifted, generates the code
8¢ and causes Sol to enter the command mode.
7.7.16
CLEAR Key
Pressing CLEAR, shifted or unshifted, erases the entire screen
and moves the cursor to its "home" position (upper left corner of the
screen) •
REV A
VII-24
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
7.7.17
Cursor Control (HOME CURSOR and Arrows) Keys
Five keys control basic cursor movement. They are HOME CURSOR
and the four keys with arrows. None are affected by SHIFT status, and
none are displayed or transmitted.
Pressing HOME CURSOR moves the cursor to its home position-the first character position in the upper left corner of the screen.
To move the cursor up, down, left or right, press the applicable "arrow" key.
Each time you press a key the cursor moves one
unit in the direction you wish--one space horizontally or one line
vertically. These keys may be used with REPEAT. The cursor will not
move across any margin of the screen with these four keys.
7.8
BASIC OPERATIONS
7.8.1
switching From Terminal To Command Mode
To switch from terminal to command mode, simply press the
MODE SELECT key. Sol enters the command mode, issues a prompt character
and waits for a command input.
(»
7.8.2
switching From Command To Terminal Mode
To switch from command to terminal mode, press UPPER CASE,
type TERM, and press RETURN in that order. Sol enters the terminal
mode and all keyboard data will be sent to the SDI output and all data
received (including "looped back" data) will appear on the screen.
7.8.3
Entering Commands in The Command Mode
The various commands for SOLOS are described in the SOLOS/
CUTERS User's Manual.
You can place more than one command on the screen. For each
command, use the arrowed cursor control keys to position the cursor
at the start of a new line and begin the new command line with a
prompt character (».
A command is executed when you press the RETURN key, and all
characters on the line to the left of the cursor are interpreted as
the command. This means that if more than one command line is on the
screen, you can execute anyone of them as follows:
position the
cursor with the arrowed cursor control keys to the right of the desired command and press RETURN.
Should you make a mistake when entering a command, there are
two ways to correct it:
(Paragraph 7.8.3 continued on Page VII-26.)
REV A
VII-25
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
7.8.4
SECTION VII
1.
If you see the error immediately (the error is to the immediate left 6f the cursor), press the DEL key (unshifted)
to erase the mistake. Then make the correction.
2.
If the error is more than one character position to the
left of the cursor, use the arrowed cursor control keys to
position the cursor over the mistake. Then make the correction.
Keyboard Restart
To perform a keyboard restart, press the UPPER CASE and REPEAT
keys at the same time. This key combination performs the same function
as a power on initialization or setting the RST switch to ON. Use the
keyboard restart to return to SOLOS from 1) a program which does not
recognize the MODE SELECT key or 2) a program that is stuck in an endless loop.
7.9
Sol-PERIPHERAL INTERFACING
7.9.1
Audio Cassette Recorders
Recorder Selection. Not all audio cassette recorders are suitable for data storage use with the Sol. Two models, tested and approved by Processor Technology for such use, are the Panasonic RQ-4l3AS
and Realistic CTR-2l.
(Some users report unsuccessful results with
the Panasonic RQ-309 and the J. C. Penney recorder, Catalog #851-0018.)
Should you wish to use a different recorder than those approved by
Processor Technology, it should have the following features:
1.
Auxiliary Input. Though the Sol can be configured for use
with the microphone input, such configuration is no longer
recommended.
2.
Digital (Tape) Counter.
files on the tape.
3.
Tone Control. The existence of a tone control is one indication of high quality electronics.
The counter is needed to locate
NOTE
Even if a recorder has the preceding features,
there is no guarantee it will work properly
with the Sol. Recorders vary greatly in the
quality of their electronics. When selecting
a "non-approved" recorder, we suggest you test
it before purchase, if possible, with a long
file.
Test it in both the record, or write,
(SAVE) 'and playback, or read, (GET or XEQ)
modes.
If the recorder is unsatisfactory,
you will either 1) get an error message in
the read mode,
2) find differences, upon playback, in what you recorded in the write mode,
or 3) both.
REV A
VII-26
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
SECTION VII
Operating Tips. For best results when using audio cassette
recorders with the Sol, observe these tips:
1.
Use high quality brand-name tape. Cheap tape can wear
down the recorder heads and give erratic results.
2.
Bulk erase tapes before use.
3.
Store cassettes in their protective plastic cases in a
cool place when not in use. Cassettes are easily harmed
by dirt, high temperatures, liquids and physical abuse.
4.
Keep recorder heads cleaned and demagnetized in accordance
with the manufacturer's instructions.
5.
Keep the recorder at least a foot away from the Sol or any
other equipment which can generate magnetic fields.
The
recorder can pick up hum which may cause errors.
6.
Set volume control to about 2/3 full volume and the tone
control at midrange. The Sol has automatic gain control
that compensates for a wide range of levels, and operation
in the middle of this range gives the most reliable results. Experiment to find the optimum setting for the
volume and tone controls.
Interconnect Requirements. Your Sol is capable of controlling
one or two recorders. The interconnect requirements for one recorder
were previously covered in Paragraph 7.4.1 in this section.
Since the Sol has only one audio input and one audio output
jack, however, the interconnect requirements for two recorders are
somewhat different than for one.
You will need two "Y" adapters, one to feed the single Sol
audio output to the AUXILIARY input of two recorders and the other to
feed the MONITOR output of two recorders to the single Sol audio input.
(If you intend to use the Audio In and Out cables described in Paragraph 7.4.1 in this section, miniature phone jack-to-two miniature
phone plug adapters are required.)
Since the recorder outputs are
most likely unbalanced, we also suggest that you incorporate 1000 ohm
resistors in the MONITOR adapter as shown in Figure 7-5 on Page VII-29.
Figure 7-5 also illustrates, in schematic form, how to connect two
recorders to your Sol.
When using two recorders you may read or write to both under
program control as well as read one tape while writing on the other.
If you intend to read one tape while writing on the other,
however, you may have to disconnect the MONITOR plug from the write
unit, with the need for disconnect being determined by the recorder
design. The MONITOR disconnect must be made if the recorder has a
REV A
VII'"'"27
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
SECTION VII
"monitor" output in the record mode.
do, for example.)
(Panasonic RQ-4l3S and RQ-309DS
NOTE 1
Recorders on which the "monitor" jack is labeled
MONITOR usually provide a monitor output in the
record mode.
If the jack is labeled EAR or EARPHONE, the recorder usually does not provide a
monitor output in the record mode.
NOTE 2
To determine if your recorder provides a monitor
output in the record mode, install a blank tape,
plug earphone into "monitor jack and microphone
into MICROPHONE jack, set recorder controls to
record, and speak into microphone while listening with the earphone.
If you hear yourself
through the earphone, your recorder does provide
a monitor output in the· record mode.
Write Operations. Other than placing the recorder(s) in the
record mode, loading the cassette(s) and making sure that the head(s)
is on tape (not leader), no m~nual operations are needed to write on
tape.
NOTE
The MICROPHONE input can be live when recording
through the AUXILIARY input on some recorders.
Deactivate the MICROPHONE input according to the
manufacturer's instructions.
(In some cases this
can be done by plugging a dummy plug into the
MICROPHONE jack.)
In the case of two recorders, however, Unit 1 and 2 must be
specified in the SAVE command in order to select the desired recorder.
A default selects Unit 1. Refer to your SOLOS User's Manual for instructions on how to use tape commands.
When recording more than one file on a tape side, we suggest
you record (SAVE) a special file after the files of interest. This
file, which could be named END, lets you know when you have read the
last file of interest. Also, rewind the tape after recording the last
file on a side, set the tape counter to zero, and issue a CATalog command (see SOLOS/CUTER User's Manual). As each file header is displayed,
make a note of the 1) tape counter reading,
2) exact file name,
3) load address and 4) file length. Then mark the cassette with this
information to make file retrieval much easier.
Read Operations.
In order to read a specific file on tape, you
must start the tape at least two seconds ahead of that file. This delay allows the Sol audio cassette interface circuitry and the recorder
playback electronics to stabilize after power is turned on. Since all
file searches are in the forward direction, the.simplest approach is
to fully rewind the cassette(s) before a read operation unless you know
REV A
VII-28
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
SECTION VII
Sol
CONNECTIONS
RECORDER
CONNECTIONS
CABLING
t--~.AUXILIARY
(J6)
Input
(Unit 1)
(A)
Audio~--~ ~~~~----------------------~~~
AUKILIARY
Input
(Unit 2)
OUT
Shielded Cable
1---"" MONITOR
(A)
(Unit 1)
(J7)
Audio __- - I
IN
I----,n
MONITOR
(Unit 2)
(J8)
(B)
(B) REMOTE
Motor a=flU=:::::========================================~::::u[J:::D (Uni t 1)
1
(J9)
Motor
2
(B)
Speaker Wire
cx::O: :
<.
(B)
:
REMOTE
[J::D (Unit 2)
(A) Miniature Phone Plug
(B) Subminiature Phone Plug
Rl
Figure 7-5.
=
R2
=
1000 ohms,
~
watt
Connecting Sol to two cassette recorders.
that the file of interest is advanced at least two seconds.
(See
Paragraph 7.4.3, Step 21 for instructions on how to rewind the tape.)
For a read operation, proceed as follows:
REV A
1.
2.
Load cassette(s) as just described.
If only one recorder is used, set its volume control at
2/3 full volume. With two recorders, set both volume controls slightly higher than 2/3 full volume.
3.
Set recorder(s) tone control(s) at midrange.
4.
Set PLAY control(s) for playback mode.
5.
Give Sol the GET or "GET, then Execute" command as appropriate.
(Refer to your SOLOS/CUTERS User's Manual for
instructions on how to use tape commands.)
VII-29
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
If you experience a read error, use the following procedure to
isolate the problem:
7.9.2
1.
Check recorder controls for proper settings and make sure
you have followed all appropriate instructions and operating tips in Paragraph 7.9.1.
2.
Check all interconnect cables for intermittent connections
and shorts.
3.
Note exact tape counter reading at the time of the error.
4.
Rewind tape and again read the same part of the tape in
which the error occurred. If there is no read error at
the same point, the error was not recorded on the tape.
If there is, the error was recorded on the tape.
5.
Rewind tape and record a file on the same part of the tape
in which the read error occurred. Then read this file.
If
there is no read error, the original error was generated
during the initial recording process.
If a read error occurs at the same point, the cassette is faulty.
Serial Data Interface (SDI)
The Sol Serial Data Interface (Jl) is capable of driving an
RS-232 device, such as a modem, or a current loop device,. such as the
ASR33 TTY.
S3 (Baud Rate) and S4 (Parity, Word Length, Stop Bits and
Full/Half Duplex) are used to select the various serial interface
options as described in Paragraphs 7.5.7 through 7.5.11 in this section.
REV A
VII-30
PROCESSOR TECHNOLOGY CORPORATION
SECTION VII
Sol OPERATING PROCEDURES
Set S3 switches to select the Baud rate required by the modem
or current loop device.
(Standard 8-level TTY's 'operate at 110 Baud,
S3-2 ON and all other S3 switches OFF.) For standard 8-level TTY's
and most modems, set all S4 switches OFF.
(This selects eight data
bits, two stop bits, no parity bit and full duplex operation for the
SDI.
Figures 7-6 and 7-7 show examples of current loop and modem
interconnections to the Sol SDI connector (Jl). The ASR33 TTY is used
to illustrate a current loop interconnect, and the Bell 103 modem is
used to illustrate a modem interconnect.
When operating in the terminal mode and full duplex, Sol keyboard data is transmitted out on Pin 2 of Jl and date received on Pin
3 of Jl is displayed on the video monitor.
In the command mode, SOLOS
set in and out commands can be used to channel output data and input
data through the SDI.
(Refer to your SOLOS/CUTERS User's Manual for
instructions on how to use the set commands.)
In either mode, the LOCAL key directly controls the SDI. with
the LOCAL indicator light on, received data is ignored and keyboard
data is not transmitted. It is, however, looped back for display on
the video monitor. with the LOCAL light off, received data is displayed and keyboard data is transmitted but not displayed unless it
is echoed back.
7.9.3
Parallel Data Interface (PDI)
The Sol Parallel Data Interface (J2) is used to drive parallel devices such as paper tape readers/punches and line printers.
It provides eight output data lines, eight input data lines, four
handshaking signals and three control signals. The latter allow up
to four devices to share the PDI connector.
(See Appendix VII for
J2 pinouts.)
The port address for parallel input and output data is FD
(hexadecimal), and the control port address for the PDI is FA (hexadecimal). PXDR is available at bit 2 of port FA. When this bit is
set to ¢, the external device is ready to receive a byte of data.
PDR is available at bit 1 of port FA, with ¢ indicating the external
device is ready to send a byte of data. Parallel unit Select (PUS)
is controlled by bit 4 of port FA. The input and output enable lines
are available for tri-stating an external two-way data bus.
Use of the three control signals is optional and is unnecessary when only one device is connected to the PDI connector.
(Paragraph 7.9.3 continued on Page 33.'
REV A
VII-31
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
SECTION VII
(Jl)
ASR33 TTY
BARRIER STRIP
(Right Rear)
Sol SDI
CONNECTOR
7
Signal Ground (SG)
~------~--------~~------------------~
Current Loop Output (CLO)
r-+-----------------~--~----~--~------------_4
6
7
1~~==1-
+
____
PRINT
MECHANISM
~--~----~
~------~
Loop Receiver 1 (LRl)
~~------L-O-O~p~-R-e-c-e-i-v-e-r--2--~(L-R--2~)------------------~~~____~
~
LOOp Current Source (LCS)
CAUTION:
Figure 7-6.
~
PINS 1 AND 2 ON TTY BARRIER STRIP
CARRY 120 V ac LINE VOLTAGE.
Connecting Sol SDI to current loop device such as TTY.
(Jl)
Sol SDI
CONNECTOR
BELL 103
MODEM
~~.____T_r_a_n_s~m
__
i_t_t_e_d__D_a_t~a__(~T_D~)___________________________________~
~
Received Data (RD)
~
(2)
Signal Ground (SG)
(2)
~
Data Set Ready (DSR)*
~
~
Data Terminal Ready (DTR)**
~
*Available at bit 1 of port F8. Terminal mode
software (SOLOS et all does not use this signal
and transmits data whether or not the modem is
ready.
**Sol is wired so that DTR indicates a ready condition whenever power is on.
Figure 7-7.
Rev A
Connecting Sol SDI to communications modem.
VII-32
PROCESSOR TECHNOLOGY CORPORATION
Sol OPERATING PROCEDURES
SECTION VII
In Figure 7-8, the Oliver OP80 Manual Paper Tape Reader is
used to illustrate a typical PDI interconnect.
7.10
CHANGING THE FUSE
Sol is protected with a 3.2 amp Slo-Blo fuse housed on the
rear panel (see Figure 7-1 on Page VII-6). To remove the fuse, turn
Soloff, disconnect power cord, turn fuse post cap one quarter turn
counterclockwise, pull straight out and remove fuse from cap.
To install a fuse, insert fuse in cap, push in and turn onequarter turn clockwise.
(J2)
Sol PDI
CONNECTOR
Rev D*
Rev E*
OLIVER
OP80
TAPE
READER
ID~
~@~-------------------------
IDI
C)--~~-------------------------@
0
ID2
0
@
~0~-------------------------0
~Q3~-------------------------
ID3
Q)--.~~------------------------
ID4
ID5
~0~------------------------@
ID6
~Q)---------------------------
ID7
~ ~~----------------------------@
0
1M
~0~-----------------------
0
DR
Gr-0------------------------~
+5 V dc
-I:U~~L~I+
~~~.--------~
SG
0
0
~0----------------------------0
NOTE:
+5 V dc is not available at J2. The use of an external
+5 V dc power supply with its ground connected to Pin I
of J2 (Sol chassis ground) is recommended.
*Sol-PC Board
Figure 7-8.
REV A
Connecting Sol PDI to parallel device.
VII-33
VIII
THEORY OF OPERATION
8.1
INTRODUCTION • .
VIII-l
8.2
OVERVIEW • .
VIII-l
8.3
BLOCK DIAGRAM ANALYSIS, Sol-PC .
VIII-3
8.3.1
8.3.2
Functional Elements And Their
Relationships • . . . . . •
Typical System Operation. . • . . • • .
VIII-3
VIII-5
Keyboard Data Entry and Display
SDI/UART Transfer and Display • • • . . • •
VIII-5
VIII-6
8.4
POWER SUPPLY CIRCUIT DESCRIPTION • • • ..
VIII-6
8.5
Sol-PC CIRCUIT DESCRIPTIONS • .
VIII-8
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
VIII-8
VIII-14
VIII-18
VIII-22
VIII-33
8.6
CPU and Bus • • . •
Memory and Decoder • .
Input/Output. •
...•• •
Display Section
• • • .
Audio Tape I/O
KEYBOARD . .
VIII-38
8.6.1
8.6.2
VIII-38
VIII-39
Block Diagram Analysis • • • • •
Circuit Description . • • • •
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
8.1
INTRODUCTION
This section concerns itself with the hardware aspects of the
Sol Terminal Co:nputer T.M.. It specifically deals with the operation of
the power supply and the logic associated with the Sol-PC and keyboard. Descriptions of software and the operation of the circuitry
contained in the multitude of integrated circuits (IC's) used in the
Sol fall outside the scope of this section. In some cases, references
to other publications or sections in this manual are provided when it
is felt that additional information will contribute to a better und\~rstanding of how Sol operates.
Should the reader wish to delve
further into the operation of a specific IC, we suggest that he study
the appropriate data sheet for that IC.
The section begins with an oVerview of the Sol design. A
block diagram analysis then provides the reader with an understanding
of the relationship between the functional elements of the Sol-PC.
This analysis sets the stage for detailed descriptions of the circuitry that makes up these elements. The section concludes with a
block diagram analysis and circuit description of the keyboard.
8.2
OVERVIEW
The Sol Terminal computer T .M ., as the name implies, is both a
terminal and computer. It is designed around the S-lOO bus structure
used in other 8080 microprocessor-based computers and incorporates
all of the circuitry needed to perform either function.
In essence,
Sol combines a central processor unit (CPU) with several S-lOO peripheral modules--memory, keyboard input interface (including the keyboard), video display output interface plus audio cassette tape,
parallel, and serial input/output (I/O) interfaces. Sol-20 also includes a five-slot backplane board for adding other memory and I/O
modules that are compatible with the S-lOO bus~
An 8080 microprocessor (the CPU) is the "brain" of the Sol.
It controls the functions performed by the other system components,
obtains (fetches) instructions stored in memory (the program), accepts (inputs) data, manipulates (processes) data according to the
instructions and communicates (outputs) the results to the outside
world through an output port.
(For information on 8080 operation,
refer to the "Intel® 8080 Microcomputer Systems User's Manual. lI )
As shown in the Sol Simplified Block Diagram on Page X-24 in
Section X, data and control signals travel between the CPU and the
rest of the Sol over three buses: 1) a 16-line Address Bus, 2) an
eight-line Bidirectional Data Bus, and 3) a 28-line Control Bus which
is interfaced to the CPU with support logic circuitry.
(Note that
the use of a bidirectional data bus permits eight lines to do the
work of 16, eight input and eight output.) These three buses account
for the bulk of the S-lOO Bus which connects the Sol to expansion
memory and I/O modules.
VIII-l
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SECTION VIII
Sol THEORY OF OPERATION
In the Sol-20, the S-IOO Bus structure takes the form of a
five-slot backplane board. It consists of a printed circuit board
with 100 lines (50 on each side) and five edge connectors on which
like-numbered pins are connected from one connector to another.
Functionally, the Sol version of the S-IOO Bus is comprised of:
1.
Sixteen output address lines from the CPU which are input
to all external memory and I/O circuitry.
(Direct memory
access (DMA) devices must generate addresses on these
lines for DMA transfers.)
2.
Eight data input/output lines that transfer data between
external memory and I/O devices and the CPU or DMA devices.
(These eight lines are paralleled with eight
other bus lines.)
3.
Eight status output lines from the CPU support logic:
Memory and I/O devices use status signals to obtain information concerning the nature of the CPU cycle.
(DMA
devices must generate these signals for DMA transfers.)
4.
Nine processor command and control lines: Six of these
are output signals from the CPU support logic; three of
them are input signals to the CPU support logic from
memory and I/O devices.
(In a DMA transfer, the DMA device assumes control of these lines.)
5.
Five disable lines: Four of these are supplied by a DMA
device to disable the tri-state drivers on the CPU outputs during DMA transfers. The fifth is a derivative of
the DBIN output from the CPU, and it is used to disable
any memory addressed in Page ¢. Use of this disable is
optional with a jumper.
6.
Two input lines to the CPU support logic which are used
for requesting a wait period. One is used by memory and
I/O devices and the other by external devices.
7.
Six power supply lines which supply power to expansion
modules.
8.
Three clock lines.
9.
Four special purpose signal lines.
10.
Thirty-one unused lines.
Definitions for each S-IOO Bus line, as used in the Sol, are
provided on Pages AVII-3 through AVII-6 in Appendix VII.
In addition to the S-IOO Bus structure, Sol also uses an
eight-line keyboard input port, an eight-line parallel input port,
VIII-2
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
an eight-line parallel output port, an eight-line sense switch logic
input port, and a unidirectional eight-line internal data bus.
The use of a unidirectional (input) data bus accommodates
Solis internal low-drive memory and I/O devices that do not meet the
heavy drive requirement of the bidirectional data bus. The low-drive
requirement of the internal bus also allows using the tri-state capabilities of the UARTls (Universal Asynchronous Receiver/rransmitter)
in the serIal and audio cassette I/O circuits without additional
drivers.
All CPU data and address lines are buffered through tri-state
drivers to support a larger array of memory and I/O d'3vices than
would otherwise be possible with the 8080 output drive capability.
Data input to the CPU is selected by a four-input multiplexer from
the Keyboard Port, Parallel Port, Bidirectional Data Bus a~d Internal
Data Bus. The Internal Data Bus is the source of all data input to
the CPU from Solis internal memory, the serial interface and the
cassette interface. The Bidirectional Data Bus is the source of all
data fed to memory and I/O, both internal and external.
It is also
the source of data input to the CPU from eight internal sense switches as well as from external memory and I/O.
8.3
BLOCK DIAGRAM ANALYSIS, Sol-PC
8.3.1
Functional Elements And Their Relationships
As can be seen in the Sol block diagram on Page X-II in Section X, timing signals for Sol are derived from a crystal controlled
oscillator that produces a IIdot clock ll frequency of 14.31818 MHz.
(This frequency, four times that of the NTSC color burst, provides
compatibility with color graphics devices.) The dot clock is applied
directly to the Video Display Generator circuit and divided in the
Clock Generator to provide ¢l, ¢2 and CLOCK. CLOCK synchronizes all
control inputs to the 8080; ¢l and ¢2 are the nonoverlapping, two
phase clocks required by the 8080.
Memory internal to the Sol is divided between 2K of ROM (Read
Only Memory), lK of System RAM (Random Access Read/Write Memory) and
lK of Display RAM. The ROM permanently stores the instructions that
direct the CPUls activities.
(To enhance Solis versatility, this
particular memory is on a plug-in "personality module ll •
Thus, Sol
can be easily optimized for a particular application by plugging in a
personality module that contains a software control program designed
for the task. The CONSOL and SOLOS programs, which are described in
section IX, are examples of such personality modules.) Display RAM
stores data for display on a video monitor, and the System RAM provides temporary storage for programs and data. All memories are addressed on the Address Bus (ADR¢-15) and, except for the Display RAM,
input data to the CPU on the Internal Data Bus (INT¢-7). Data entry
into both RAMls is done on the Bidirectional Data Bus (DIO¢-7).
REV A
VIII-3
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
As can be seen, Sol's internal memory consists of four contiguous 1024-byte pages. There are two pages (C¢ and C4, hexadecimal
or hex) of ROM, with Page C¢ at hex addresses C¢¢¢ through C3FF and
Page C4 at hex addresses C4¢¢ through C7FF. System RAM (Page C8) is
at hex addresses C8¢¢ through CBFF, and Display RAM (Page CC) is at
hex addresses CC¢¢ through CFFF.
The six high order bits of the address are decoded in the
Address Page and I/O Port Decoder to supply the required four memory
page selection signals. The I/O Port Decoder portion of this circuit decodes the eight high order address bits to provide outputs
that control Data Input Multiplexer switching, Data Bus Driver enablement and I/O port selection.
The video display section consists of the Video Display Generator and Display RAM. The RAM is a two-port memory, with the CPU
having the higher priority. Screen refresh circuitry in the Video
Display Generator controls the second port to call up data as needed
for conversion by a character generator ROM into video output signals.
Other circuitry generates horizontal and vertical sync and blanking
signals as well as cursor and video polarity options.
A 1200 Hz signal, extracted from dot clock by a divider in
the Video Display Generator, drives the Baud Rate Generator. This
generator supplies the receive and transmit clocks for the serial
data interface (SDI/UART) and provides all frequencies required for
Baud rates between 75 and 9600. It also supplies clock signals to
the Cassette Data Interface (CDI).
A UART controls data flow through the Serial Data Interface
(SDI/UART) and provides for compatibility between the Sol and a data
communications system, be it RS-232 standard or a 20 rna current loop
device. In the transmit mode, parallel data on the Bidirectional
Data Bus is converted into serial form for transmission. Received
serial data is converted in the receive mode into parallel form for
entry into the CPU on the Internal Data Bus. SDI/UART status is also
reported to the CPU on the Internal Data Bus. The SDI/UART channel
is enabled by the port strobe from the Address Page and I/O Port
Decoder.
Circuitry within the CDI derives timing signals from clocks
supplied by the Baud Rate Generator. The Cassette Data UART functions to 1) convert parallel data on the Bidirectional Data Bus into
serial audio signals for recording on cassette tape, and 2) convert
serial audio signals from a cassette recorder into parallel data for
entry into the CPU from the Internal Data Bus. Note that Cassette
Data UART status is also reported to the CPU on the Internal Data
Bus. Again, a UART performs the necessary parallel-to-serial and
serial-to-parallel conversions. Other CDI circuitry performs the
needed digital-to-audio and audio-to-digital conversions and provides
the signals that allow motor control for two recorders. As with the
SDI/UART, the Cassette Data UART is enabled by a port strobe from the
Address Page and I/O Port Decoder.
VIII-4
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
Output data from the CPU that is channeled through the Parallel Port (pp) is latched from the Bidirectional Data Bus by the parallel strobe from the Address Page and I/O Port Decoder. This data
is made available at P2, the PP connector. Parallel input data
(PID¢-7) on P2, however, is fed directly to the Data Input Multiplexer for entry into the CPU.
As can be seen, keyboard data (IZBD¢-7) from J3 is also fed
directly to the Data Input Multiplexer. The keyboard data ready
flag, though, is input to the CPU on the internal data bus.
The remaining internal source of data input to the CPU is
the Sense Switch Logic, with the data being input on the Bidirectional Data Bus. This is an eight-switch Dual Inline Package (DIP)
array that lets the CPU read an eight-bit word when it issues the
sense switch strobe via the Address Page and I/O Port Decoder. The
sense switch data source is available to interact with the user's
software.
CPU Support Logic accepts six control outputs from the CPU,
status information from the CPU's data bus and control signals from
the Control Bus.
It controls traffic on the data buses by generating signals to 1) select the type of internal or external device
(memory or I/O) that will have bus access and 2) assure that the device properly transfers data with the CPU.
8.3.2
Typical System Operation
Basic Sol system operation is as follows: The CPU fetches
an instruction and in accordance with that instruction issues an
activity command on the Control Bus, outputs a binary code on the
Address Bus to identify the memory location or I/O device that is to
be involved in the activity, sends or receives data on the data bus
with the selected memory location or I/O device, and upon completion
of the activity issues the next activity command.
Let's now look at some typical operating sequences.
Keyboard Data Entry and Display. Assume the "A" and SHIFT
keys on the keyboard are pressed. The keyboard circuitry converts
the key closures into the 7-bit ASCII (American Standard Code for
Information Interchange) code for an "A" (l!1!1!1!1~!n) and sends a keyboard-data-ready status signal to the CPU on the Internal Data Bus.
The monitor program in ROM repetitively "looks" for the status
signal. When it finds this signal the program enters its keyboard
routine and enables the transfer by switching the Data Input Multiplexer to the keyboard bus via the Address Page and I/O Port Decoder.
Following program instructions, the CPU addresses the Display
RAM on the Address Bus to determine where the next character is to
appear on the screen.
It then stores the ASCII code for the "All at
the appropriate location in the Display RAM and adds one to the cursor position in readiness for the next character.
(Addressing is
VIII-5
PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
done over the Address Bus~ cursor position and the "A" enter the Display RAM on the Bidirectional Data Bus.) The CPU is now finished
with the transfer, and will issue the next activity command.
When the refresh control circuitry calls up (addresses) the
"A" from the Display RAM, the character generator ROM decodes the
ASCII-coded "A" that is input from the Display RAM and generates the
"A" dot pattern (see Figure 8-5 and 6) in parallel form. The ROM
output is serialized into a video signal and combined with a composite sync signal to provide an Electronic Industries Association
(EIA) composite video signal for display on an external video monitor.
SDI/UART Transfer and Display. A data transfer through the
SDI/UART is similar to a keyboard entry, but data can be transferred
in either direction.
Assume the SDI/UART wants to transfer an "A" from a modem to
the CPU for display on a video monitor. The ASCII code for the "A",
received in serial form from the modem on the serial data input of
the SDI connector (Jl), is fed to the SDI/UART. In the receiver section of the UART the serial data is converted into parallel form and
placed in the UART's output register. The UART also sends a "received
data ready" status signal to the CPU on the Internal Data Bus. When
the program in ROM checks and finds the status signal, the program
enters the SDI routine, and enables the transfer by switching the
Data Input Multiplexer to the Internal Data Bus. The "A" enters the
CPU on the Internal Data Bus and is sent to the Display RAM on the
Bidirectional Data Bus. Operations involved in displaying the "A"
are identical to a keyboard entry.
Now assume the CPU wants to send an "A" to the SDI/UART for
transmission. The CPU, under program control, sends the SDI/UART
status input port strobe via the Address Page and I/O Port Decoder
to the UART.
In turn, the UART responds with its status on the Internal Data Bus. Assuming the UART is ready to transmit, the CPU places
the ASCII code for the "A" on the Bidirectional Data Bus and sends
the SDI/UART data output port strobe which loads the Bidirectional
Data Bus content into the UART's transmitter section. The "A" is
serialized by the UART and sent out the transmitted data pin of Jl.
8.4
POWER SUPPLY CIRCUIT DESCRIPTION
Section
Refer to the Sol-REG and Sol-20 Power Supply Schematics in
x, Pages X-12 and 13.
The Sol power supply consists of the Sol-REG regulator and
the Sol-20 power supply components.
REV A
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Sol THEORY OF OPERATION
SECTION VIII
Fused primary power is applied through S5 to T2. FWB1, a fullwave bridge rectifier, is connected across the S-volt secondary (green
leads). The rectified output is filtered by CS and applied to the
collector of Ql. Ql, a pass transistor, is driven by Q2, with the two
connected as a Darlington pair. The output of Ql is connected to Rl
which serves as an overload current sensor.
An overload current (approximately 4 amps) increases the
voltage drop across RIo The difference is amplified in one-half of
U2 (an operational amplifier) and the output on pin 7 turns Q3 on.
Q3 in turn IIsteals ll current from QI-Q2 and diverts current from the
output on pin 1 of U20 This in effect turns the supply off to reduce
the current and voltage. Note that the circuit is not a constant
current regulator since the current is IIfolded back ll by R6 and R8.
The current is reduced to about 1 amp as the output voltage falls
to zero.
Divider network Rll and R12, which is returned to -12 volts,
senses changes in the output voltage. If the output voltage is 5
volts, the input on pin 2 of U2 is at zero volts. U2 provides a
positive output on pin 1 if pin 3 is more positive than pin 2 and a
negative output for the opposite condition.
When the output voltage falls below 5 volts, pin 2 of U2
goes more negative than pin 3. This means pin 1 of U2 goes positive to supply more current to the base of Ql. The resulting increase in current to the load causes the output voltage to rise
until it stabilizes at 5 volts. Should the output voltage rise above
5 volts, the circuit operates in a reverse manner to lower the
-voltage.
Protection against a serious over-voltage condition (more than
6 volts) is provided by SCRl, Dl, D5, R2, R13, R14 and CS.
Zener
diode, (Dl), with a 5.1 zener voltage, is connected in series with R13
and R2. When the output voltage exceeds about 6 volts, the resulting
voltage drop across R2 triggers SCRI to short the foldback current to
ground. Since the overload current circuit is also working, the current through SCRl is about 1 amp. Once the current is removed, this
circuit restores itself to its normal condition; that is, SCRl turns
off. R13, R14, CS and D5 serve to slightly desensitize the circuit
so that it will not respond to small transient voltage spikes.
Bridge rectifier FWB2, connected across the other T2 secondary, supplies +12 and -12 V dc. The positive output of FWB2 is filtered by C5 and regulated by IC regulator Ul. The negative output
is filtered by C4 and regulated by U3. Shunt diodes D3 and D4 protect Ul and U3 against discharge of C6 and C7 when power is turned
off.
(Note that should the -12 volt supply short to ground, the
+5 volt supply turns off by the action of U2.
REV A
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SECTION VIII
Sol THEORY OF OPERATION
Unregulated -16 and +16 V dc, at 1 amp, from the filtered outputs of FWB2 are made available on terminals X6 and XS. These are
supplied to the backplane board to drive S-IOO Bus modules.
Power transformer (T2) has an additional 8-volt secondary winding and a third bridge rectifier (FWB3) to supply +8 V dc at 8 amps.
The output of FWB3 is filtered by C9 and controlled by bleeder resistor
R13. Again, this voltage is supplied to the backplane board.
The Sol power supply also includes a cooling fan powered by
the AC line voltage.
8.5
Sol-PC CIRCUIT DESCRIPTIONS
8.5.1
CPU and Bus
Refer to the CPU and Bus Schematic in Section X, Page X-14.
A crystal, two inverter sections in U92 and four D flip-flops
(U90) and associated logic make up the Clock Generator.
The two U92 sections function as a free-running oscillator
that runs at the crystal frequency of 14.31818 MHz. R133 and R134
drive these two sections of U92 into their linear regions, and C6l
and 64 provide the required feedback loop through the crystal. U77,
a permanently enabled tri-state non-inverting buffer/amplifier, furnishes a high drive capability.
This fundamental clock frequency is fed directly to the Video
Display Generator and to the clock inputs of U90. U90 is a fourstage register connected as a ring counter that is reset to zero when
power is applied to the Sol. This reset is accomplished with D8,
Rl04 and C39.
The bits contained in the ring counter shift one to the right
with every positive-going clock transition, but the output of the
last stage is inverted or "flipped" before being fed back to the input.
In a simple four-stage "flip-tail" ring counter, the contents would
progress from left to right as follows: 1!1!1!1, ll~~, lll~, 1111, ~lll,
~~ll, ~~~l, ~~~~--on the first through eighth clocks respectively.
The hypothetical counter would go through eight states, dividing the
clock by eight.
The Sol counter, however, is a modified flip-tail ring counter that can be configured to divide by one of three divisors--S, 6
or 7. This is made possible by using a two-input NAND gate (U9l) in
the feedback path and three jumper options (no jumper, D-to-C and
D-to-E) to alter the feedback path. Let's see how it works.
REV A
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Sol THEORY OF OPERATION
Sol is normally configured with the D-to-E jumper installed
·to meet the clock requirements of the 8080A CPU. with this jumper
installed, the outputs of the third and fourth U90 stages are applied
to pins 9 and 10 of U91. Assuming U90 is reset to zero, pin 8 of U91
is high, and on the first clock pulse the counter contents change to
19191¢.
(Refer to 2.045 MHz Clocks portion of Figure 8-1 on Page
VIII-II.) Pin 8 of U91 cannot change until the fourth state (1111),
at which time it goes to zero. On the fifth clock pulse the counter
changes to 91111. Again, pin 8 of U91 cannot change from zero until
one of its inputs changes. As sho"wn in Figure 8-1, the third U90
stage (C) changes on the seventh clock. The counter now stands at
¢91¢l, and on the eighth clock the counter flips. to l¢9191 and the count
cycle repeats. The pattern is thus l¢91¢, .1191¢, 11191 I 1111, ¢lll,
919111, 9191911. U90 consequently goes through seven states. We have a
3.5-stage counter that divides DOT CLOCK by seven to supply a 2.045
MHz output.
With no jumper install~d, pin 10 of U91 is pulled high by
RI05, and U91 operates as a simple inverter for feeding back the
output of the third U90 stage. In effect we have a three-stage counter that operates in a similar manner to that described in the preceding paragraph.
It goes through six states (l¢¢, 1191, Ill, ¢ll,
¢91l, 9191¢) to divide DOT CLOCK by six which produces a 2.386 MHz output. The timing for this option is also shown in Figure 8-1.
Let's now put the D-to-C jumper in. The feedback in this
case is the NAND combination of the outputs from the second (B) and
third (C) U90 stages. This gives us a 2.5-stag.e counter that divides
DOT CLOCK by five. As can be determined from the 2.863 MHz portion
of Figure 8-1, the counter has five states with this option, and the
count pattern is: 19191, 1191, Ill, 9111, 91911.
Outputs from U90 are applied to the logic comprised of the
remaining three sections in u91. This logic and the A-to-B jumper
option permits extracting clock pulses of varying widths and relationships to each other from various points within the counter. We
extract two clock signals: ¢l on pin 6 of u91 and ¢2 on pin 11 of
U91.
(The ability to select the frequency and pulse width for ¢l and
¢2 permits the use of either the 8080A, 8080A-l or 80aOA-2 CPU for
UI05. The "A" version is the slowest speed unit, the "A-2" has
an intermediate speed, and the "A-l" is the fastest.)
Let's now
see how the pulse width of ~l and ~2 are determined.
¢l on pin 6 of·NAND gate U91 is low only when its two inputs
are high, and this happens only when there is a 1 in the second and
fourth stages of U90. This occurs during the time between· the fourth
and sixth fundamental clocks for 2.04 MHz operation~-the fourth and
fifth clocks for 2.38 MHz and 2.86 MHz. Keeping in mind that the
fundamental clock period is 70 nsec, it is readily seen that the low
frequency pulse train on pin ·6 of U91 has a pulse width of 140 nsec
and the two higher frequency pulse trains have a pulse width of 70
nsec.
(Refer to Figure 8-1 on Page VIII-II.)
VIII-9
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
The A-to-B jumper is installed when the 8080A or 8080A-l CPU
is used in the Sol. Note that the output (¢2) on pin 11 of NAND gate
U9l is low only when the output on pin 3 of NOR gate U9l is high.
(This section in U9l is actually a two-input NAND gate which is functionally the same as a two-input NOR gate.) Pin 3 of U9l, with the
A-to-B jumper in, is high when either the second (B) or third (C) U90
stage is at zero. As shown in Figure 8-1, this occurs between the
sixth and tenth DOT CLOCKS, or 280 nsec (4 x 70 nsec) , for 2.04 MHz
operation. For 2.863 MHz, it occurs between the fifth and eighth
DOT CLOCKS for 210 nsec. The section of NAND gate U9l with its output on pin 11 inverts the output on pin 3 of u9l and introduces a
slight delay to insure there is no overlap between ¢l and ¢2.
with the A-to-B jumper out, pin 11 of U9l is low only when
the second stage (B) of U90 is at zero. At 2.386 MHz, this occurs
between the fifth and eighth DOT CLOCKS for 210 nsec. This configuration is used for the 8080A-2 CPU.
In summary, we have two non-overlapping pulse trains which
represent the ¢l and ¢2 clocks required by the 8080 CPU, and the
pulse widths of these two clocks vary with frequency as follows:
FREQUENCY
¢l PULSE WIDTH
¢2 PULSE WIDTH
CPU
2.045 MHz
2.386 MHz
2.863 MHz
140 nsec
70 nsec
70 nsec
280 nsec
210 nsec
210 nsec
8080A
8080A-2
8080A-l
¢l and ¢2 are applied to S-lOOBus pins 25 and 24 respectively
through inverters (U92) and bus drivers (U77). They are also capacitively coupled to pins 2 and 4 respectively of driver Ul04, the phase
clock conditioner.
An additional clock, called CLOCK, is taken from pin 8 of
NAND gate U9l.
It occurs 70 nsec after ¢2. It is used on the Sol-PC
and is also made available on S-lOO Bus pin 49 as a general 2.04,
2.38 or 2.86 MHz clock signal.
Three J-K flip-flops (U63 and 64) are used to synchronize the
READY, RESET and HOLD inputs to the CPU. All three are connected as
D-type flip-flops so that their outputs follow their inputs on the
low-to-high transition of the clock. The READY flip-flop input on
pins 2 and 3 of one section in U63 is either PRDY or XRDY from the
S-lOO Bus~ these are normally pulled high by R34 and R12 respectively.
S-lOO Bus signal PRESET, which is normally pulled high by R55, inputs
the RESET flip-flop, the other section of U63. The HOLD flip-flop
(U64) input is P HOLD, normally pulled high by R56, from the S·-lOO
Bus. Pull up resistors R5l, R50 and R53 insure that the high states
of these three flip-flops are adequate for the CPU.
VIII-lO
PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
2
DOT CLOCK_~
14.3 MHz
I
U9 O, PjlN
3
4
~
:
I
I
5
6
7
8
9
10
II
~~: _ _ _--'~I~~±:=2=BO!::=ns===t4~9DI" :2",,1
U90, PINI5;0
01 =0-8
14
I
I
"'---+'---.....
I
L
------:--~
i----...;
------+----1
140ns
15
'--....;.-~---!r
I
I
l~iC --------1
13
,I
~70nsrI
12
~---Tj-..;;;.35.;.;0;.,;.n;..;.s--~--J
O2 =R - - - - - - - ;
j210ns
L...----TI--.;..--.....
: 2BOns
I
~OELAYEO =D-C - - - - - - - - - - ;1..._.....;2~IO~n.;.;.I_ __'1
2BOns
2.045 MHz CLOCKS
2
3
4
5
6
7
8
9
10
II
12
13
14
15
DOT CLOCK
14.3 MHz
-~
i---':'---:---j
T' Pi :;: ____
I
_-;bID'1 •:
...:....----I;-r-
U90, PIN 15iO -----'--~~I
01
=0
0
8
,
10 nl
- "":----:-,
!
I
I
I
-------~-....;..I--......
I
I
'---i--~---II
I
I
,
~!---'---3-5~o-ns~-~--Jr--l...--~----~--_7-
O2 =II
:21OnIl
I
;-1-
:-
:A21::0-,nS----;L...---..L______.....
.....
I
I
0 2 0ELAYEO
=C
210n8
L
210ns
2.386 MHz CLOCKS
2
3
4
5
6
7
8
9
10
II
12
13
14
15
I
I
i
~
L
,
I
U90, PIN 15; 0
01 =0-8
02 e-;c
=
I
------~--!l
I
___________~-....f7Or;1
------j
I
,
280nl
I
,
140n8
210n8
140n8
210n8
I
'"
0 2 0ELAYEO=8 o C - - - - - - ;
I
---'_r-L
r--l!-_ _
~__~I
2.683 MHz CLOCKS
Figure 8 -I. CLOCK GENERATOR TIMING
I
I
r,
r-
I - - - _......
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
Diode D7, CIS and R18 make up the poe (power on clear)circuit. When power is applied, CIS starts to charge slowly until it
reaches the threshold on pin 6 of U46, a Schmitt trigger.
(By this
time the logic and 5 volt supply have stabilized.) When the threshold is reached, pin 2 of U46 suddenly goes low. The resulting output
on pin 8 of inverter U92 is initially low and then rapidly goes high.
This signal is passed through a section of U77, a permanently enabled
noninverting tri-state driver, as POC to S-lOO Bus pin 99.
It is
also inverted in a section of U45 to become POCo
The output on pin 8 of U92 is also connected to pin 15 of
U63. Thus, pin 9 (RESET) of u63 is high to start the CPU in the
reset condition when the Sol is initially turned on.
When POC goes high, the RESET flip-flop section of U63 is
free to clock. Assuming PRESET is not active, it will change state
on the first CLOCK transition. The resulting high on pins 10 and 5
of U63 cause pin 7 (READY) of U63 to go low to place the CPU in the
not ready or wait state. This state is subsequently removed on the
CLOCK transition following the transition which removed the low from
pin 5 of U63. This helps prevent the CPU from starting in a crash
condition.
The HOLD flip-flop (U64), however, is not affected by the POC
circuit, and was clocked to a low on pin 7 well before the RESET and
READY signals became active.
Operation of the POC circuit can also be initiated, without
turning the power off, by a keyboard restart signal on pin 13 of J3
or by closing Sl-l if the N-P jumper is in.
In either case, CIS is
discharged through R58 and then allowed to recharge after KBD RESTART
is removed or Sl-l is opened.
POC als9 resets all stages of D flip-flop U76 (the phantom
start-up circuit) to zero. On initial start-up, the CPU performs
four fetch machine cycles (refer to Intel® ,8080 Microcomputer Systems User's Manual) in accordance with program instructions. For
each fetch, the CPU outputs a DBIN on pin 17. U76, connected as a
four-stage shift register, is clocked by the inverted DBIN signal on
pin 3 of NOR gate U46. Thus, PHANTOM, on S-lOO Bus pin 67, is active
low (assuming the F-to-G jumper is in) for the first four fetches or
machine cycles. After the fourth DBIN, PHANTOM goes high. PHANTOM
is used to 1) disable any memory addressed in Page ¢ that has Processor Technology's exclusive "Phantom Disable" feature and 2) cause the
Sol program memory (ROM), which normally responds to Page C¢ (hex) to
respond to Page ¢¢ (hex). The second function is discussed in Paragraph 8.5.2.
REV A
VIII-12
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
The inverted DBIN on pin 3 of U46 is also applied to pin 12
of NOR gate U46 and inverted to appear as PDBIN on S-lOO Bus pin 78.
This section of U46 also allows DIGl (bus pin 57) to override DBIN.
(DIGl is used when an external DMA device replaces the CPU in terms
of writing into and reading from memory.) The other CPU control signals (SYNC, INTE, HLD~t WR and WAIT) are also fed to the S-lOO Bus
pins as indicated. These, as well as DBIN o:c DIG1, are placed on the
bus through tri-state drivers which are enabled by C/C DSB on S-lOO
Bus pin 19. Note that this signal is normally pulled high by R20.
The data lines of the CPU (D¢-7) are bidirectional and are
used for several functions. One of these is to output status at the
start of, each cycle which is marked by the SYNC output of the CPU.
Status on D¢-7 is latched in U93 and U106 (each of which contains
four D flip-flops) when pin 8 of inverter U45 goes high. Status information, as identified on the schematic, is then buffered through
tri-state drivers u94 and U107 to the S-lOO Bus. The status latch
strobe on pin 8 of U45 is extracted in the middle of the SYNC pulse
by gating PSYNC and~ in NAND gate U44. STAT DSB on S-lOO Bus pin
18 is used to disable the U94 and ul07 buffers when a DMA device or
another processor assumes control of the S-lOO Bus.
A second function of D¢-7 is to output data from the CPU to
the Bidirectional Data Bus. Data out of the CPU is placed on this
bus through tri-state drivers (U80 and U8l). Note that these drivers
are normally enabled unless this bus is in the input mode or an external device has control of the bus. In the latter case, DO DSB on
S-lOO Bus pin 23 would be pulled low to make pin 8 of NOR gate U48
high.
In the input mode pin 8 of U48 is high because OUT DSB is low.
This signal is generated by decoding PAGE CC, MEM SEL, PORT IN FC,
PORT IN FD, INT SEL to produce MPX ADR A and MPX ADR B on pins 3 and
11 respectively of two NOR gates in U48. MPX ADR A and MPX ADR Bare
decoded with DBIN on pin 5 of NAND gate U47.
The D¢-7 bus lines are also used to input data to the CPU.
Data input to the CPU is multiplexed from four data buses with four
4-to-l line multiplexers (U65, 66, 70 and 79). These four buses are
the: 1) Keyboard Data Bus, IZDB¢.-7, 2) Parallel Input Data Bus,
PID¢-7, 3) Internal Data Bus, INT¢-7, and 4) Bidirectional Data Bus,
DIO¢-7.
These data multiplexers are tri-state devices, with their
outputs pulled up by RI07 through Rl14 to a level that satisfies the
input requirements of the CPU. Their outputs are active only when
both their El and E2 (pins 1 and 15) are low. As can be seen, this
occurs only when DBIN on pin 3 of NOR gate U46 is 10Wi that is, when
the DBIN output of the CPU is active to indicate its data bus is in
the input mode.
VIII-13
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
Input selection to the multiplexers is done with the A and B
inputs to U6S, 66, 78 and 79. These two inputs are driven by MPX
ADR A on pin 3 of NOR gate U48 and MPX ADR B on pin 11 of NOR gate
U48. There are four possible states for the combination of MPX ADR A
and B, and their relation to input selection is as follows:
1.
If both are active (high), the multiplexers select the
Bidirectional Data Bus.
2.
When the keyboard is called up by the CPU, only
PORT IN FC is active (low) to make MPX ADR A low.
selects the Keyboard Data Bus.
This
3.
When the parallel port is called up by the CPU, only
PORT IN FD is active (low) to make MPX ADR B low. This
selects the Parallel Input Data Bus.
4.
When the CPU selects any I/O port that uses the Internal
Data Bus, only INT SEL (pin 2 of u47 and U61) is active.
Thus, both MPX ADR A and B are low to select the Internal
Data Bus.
Two other conditions, defined by PAGE CC on pin 2 and MEM SEL
on pin 1 of NAND gate U4~are possible. When any of the four memory
pages in the Sol are accessed, MEM SEL goes high and an inversion in
U44 (PAGE CC is normally high) appears as a low MPX ADR A and B to
select the Internal Data Bus. Should Page CC (the Display RAM) be
addressed, PAGE CC also goes active (low) to override MEM SEL. MPX
ADR A and B are consequently high to select the Bidirectional Data
Bus. These two conditions are required since the ROM and System RAM
use the Internal Data Bus and the Display RAM uses the Bidirectional
Data Bus.
The address outputs of the CPU (A¢-lS) are placed on the Address Bus via tri-state drivers (U67, 68 and 81). These drivers are
normally enabled since pin 3 of inverter u49 is pulled high by R36.
ADn DSB on S-IOO Bus pin 22 is used to disable the address drivers
when a DMA device or another CPU takes over the bus.
A S.l volt. zener diode, Dll, and a divider network composed
of R130, 131 and 132 derive -S V dc from the -12 V dc supply for use
by the CPU. Diode D12 and the same divider supply -12 V dc to pin 3
of UI04, the phase clock conditioner.
8.S.2
X-IS.
REV A
Memory and Decoder
Refer to the Memory and Decoder Schematic in Section X, Page
VIII-14
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
The System RAM consists of eight lK by 1 bit static memory
chips, U3 through UIO, and it is assigned addresses C8¢¢-CBFF (hex).
When the CPU wants to write data into memory, it addresses the System
RAM on ADR¢-15. ADR¢-4 select the row inside the RAM chips, ADR5-9
select the column, and ADRl¢-15 select the page (in this case Page
C8, hex). Page selection enables the eight RAM chips on pin 13.
For a read operation, MWRITE on S-IOO Bus pin 68 is low, and the resulting high on pin 3 (WE) of the RAM chips keeps them in the read
mode. Thus, data on the Bidirectional Data Bus is read into the
RAM's on their DI (pin 11) inputs. MWRITE is high, however, during
the time the CPU wants to write data into memory.
In this case, pin
3 of the RAM's is low to enable them to accept data from the Bidirectional Data Bus.
The ROM is also addressed on ADR¢-15 as is the System RAM.
Since there can be two pages, however, two enable lines (one for Page
C¢, hex, and the other for C4, hex) are provided. The C¢ and C4
enables are connected to pins A6 and AS respectively of J5, the Personality Module connector. Unlike the RAM, the ROM can only read
data into the CPU, so the previously discussed MWRITE signal is not
needed. Data out of the ROM is output on the Internal Data Bus on
pins A3, A4 and B5-1¢ of J5.
ADRl¢-15 are input to the Address Page and Port Decoder (U34,
35, 36 and their associated logic). U34 (Address Page), U35 (Output
Port) and U36 (Input Port) are 3-to-8 line decoders which have three
enable inputs (Gl, G2A and G2B). Gl must be high and both G2A and B
must be low in order to obtain an active output.
Let's look at the Address Page Decoder, U34, first.
It must
be able to decode four pages: C¢ and C4 (ROM), C8 (System RAM) and
CC (Display RAM).
(Note that these are the hexadecimal digits of the
six high order address bits, ADRl¢·-15).
The high order four bits (ADR12-15) must be ll¢¢ (C, hex) in
all cases by virtue of the U22 exclusive OR logic. If they are not,
the Gl enable on U34 is low to disable that decoder. Bits ADRl¢ and
11 (The A and B inputs to U34) are the high order bits of the second
hexadecimal digit which must be ¢¢ (¢, hex), ¢l (4, hex), l¢ (8, hex)
or 11 (12, hex) if U34 is to have an active output. For C¢, pin 11
of U34 is active (low)~ for C4, pin l¢ is active: for C8 pin 9 is active~ and for CC pin 7 is active.
These outputs are applied to the
appropriate memories and also provide the MEM SEL signal on pin 6 of
one section in U23.
(This section is actually a 4-input NAND gate
which is functionally the same as a 4-input NOR gate.)
Note that the U22 logic input with ADR14 and 15 is also connected to PHANTOM. When this signal is active (low), the output on
pins 3 and 11 will be low to disable U34 when ADR12-15 represent a
C. If Page ¢ is addressed, however, pins 3 and 11 of U22 are high,
and this, coupled with lows on ADRl¢-13, are decoded by U34 as an
active output on pin 11. The ROM will consequently respond to addresses in Page ¢ and C¢ (hex) as long as PHANTOM is active.
VIII-IS
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
The other two enables on U34 (G2A and G2B) are connected to
SINP and SOUT. These two status signals indicate an input or output
operation during the CPU cycle. U34 is therefore disabled during
these operations.
SINP and SOUT are also fed to pins 5 and 6 of NOR gate u53
which detects an input or output operation. Its output is inverted
by u54 and applied to pin 9 of another U53 NOR gate. The other input
(pin 8) to U53 is MEM SEL. So during a memory reference, input operation or output operation, pin 10 of U53 is active to enable the PRDY
driver, U7l. The low on pin 10 of U53 is also clocked by ¢2 as a
high to pin 7 of U70, a J-K flip-flop that is connected as a D flipflop. Note that the PSYNC • ~ signal on pin 5 of U70 forces U70 to
set during the middle of PSYNC (refer to CPU and Bus discussion). U70
cannot clock until pin 5 is released, and this occurs simultaneously
with thelow-to-high transition of ¢2. PRDY is thus low immediately
after pin 10 of u53 goes low and remains in that state from the middle of PSYNC to the first positive-going ¢2 after PSYNC. This is the
time the CPU tests the status of the ready lines (PRDY and XRDY).
If
either is low, the CPU enters a WAIT state. U53, 70 and 71 thus
guarantees that the CPU enters one WAIT state during cycles in which
an input, output or memory reference is made.
U35 and 36, the Output and Input Port Decoders respectively,
decode the higher order eight address bits (ADR8-15).
All Sol ports have a hexadecimal F (1111) in their high order
four bits (ADR12-l5 are l's). The second hexadecimal digit is also
never less than eight. This means that ADRll is always
I for a
port address. These five address bits are thus NAND gated in U23 to
provide one of the enables on U35 and 36. Note that the ADR14-15
combination is derived from the output on pins 3 and 11 of the U22
exclusive OR logic. This is permissible since no I/O operations are
performed during the first four start-up cycles of the CPU.
The A, B, and C inputs to U35 and 36 (ADR8, 9 and 10 respectively) specify the second hexadecimal digit in the port address and
are decoded to supply the indicated outputs. These outputs and their
functions are defined in Table 8-1. U36 is enabled to decode when
PDBIN and SINP are active: that is, during an input operation. U35
is enabled when SOUT and PWR are active: that is, during an output
operation.
INT SEL on pin 8 of inverter U83 is the remaining signal generated by the Input Port Decoder circuit. This signal is active when
either input port F8, F9, FA or FB is decoded by U36.
Both the address page and input/output decoders can be disabled by SINTA (S-lOO Bus pin 96) when the AE-to-AC and AB-to-AD
jumpers are installed. SINTA is active (high) when the CPU is responding to an interrupt. Should an external device issue addresses
during this time, any memory response would interfere with the
VIII-16
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
Table 8-1.
Port Decoder (U35 & U36) Outputs and Their Functions.
PORT DECODER OUTPUT
PORT OUT FE
.----PORT OUT FD
FUNCTION
Loads starting row address and first display
line position information from Bidirectional
Data Bus into Video Display scroll circuit.
Clocks data from Bidirectional Data Bus to
output data pins of PP connector.
PORT OUT FB
Loads data from Bidirectional Data Bus into
Cassette Data UART.
PORT OUT FA
Clocks PP and CDI control bits from Bidirectional Data Bus.
PORT OUT F9
Loads data from Bidirectional Data Bus into
SDI UART.
PORT OUT F8
Clocks RTS (request to send) from bit 4 of
Bidirectional Data Bus to pin 4 of SDI connector.
PORT IN FF
Permits CPU to read data byte entered from
Sense Switches.
PORT IN FE
Places Video Display scroll timer and screen
position status on bits ¢ and I of Bidirectional Data Bus.
PORT IN FD
Switches Data Input Multiplexer to input data
pins of PP connector and resets PP at end of
a transfer to ready it for another.
PORT IN FC
Switches Data Input Multiplexer to Keyboard
Data Bus.
PORT IN FB
Strobes received data in CDI UART to Internal
Data Bus.
PORT IN FA
Places PP, keyboard and CDI UART status on
Internal Data Bus.
PORT IN F9
Strobes received data in SDI UART to Internal
Data Bus.
-----PORT IN F8
Places SDI UART status on Internal Data Bus.
VIII-17
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
interrupt op~ration. To prevent this, SINTA is inverted in u58 to 1)
disable U34 on pin 6 and 2) force pin 8 of NAND gate U23 high to disable U35 and U36 on pin 5.
(This feature is provided to enable future versions of Sol to operate with a vectored interrupt system.)
8.5.3
Input/Output
Refer to the Input/Output Schematic In section X, Page X-16.
This section in the Sol has five functional circuits: 1)
Parallel I/O Logic, 2) Sense Switch Logic, 3) Keyboard Flag Logic,
4) SDI/UART ~nd 5) Baud Rate Generator.
The PP uses U95 and 96 (4-bit D-type registers) and their related logic. Data output to the PP connector (J2) is latched from
DIO¢-7 by U95 and U96. Data is strobed into these registers on the
leading edge of an inverted active PORT OUT FD signal on pin 4 of inverter U54. This strobe is also applied to pin 2 of U73 which functions as a J-K flip-flop that is clocked by~. When the ~ goes
from low to high 200 to 300 nsec after PORT OUT FD, pin 7 of U73 goes
low to become POL on pin 17 of J2.
(This delay allows U95 and 96 to
stabilize.) U73 is reset in the middle of the following PSYNC which
means POL is active for the balance of the cycle.
The outputs of U95 and 96 are tri-state outputs that are enabled by a low on pin 2. In the absence of POE at pin 15 of J2, pin 2
of U95 and 96 are low by virtue of the output on pin 8 of inverter U550
Note that the input to U55 is normally pulled up through R63. The POE
provision permits tri-stating an external bidirectional data bus.
As discussed in Paragraph 8.5.1, parallel input data on J2 is
fed directly to the Data Input Multiplexer (see Page X-IS). The
strobe that indicates the presence of input data, PD.R on pin 4 of J2,
is applied to pins 2 and 3 of one section in U72, a J-K flip-flop
which is connected as a D flip-flop~ When PDR goes active (low), pin
7 of U72 will go high on the next low-to-high transition of ¢2 to
toggle the following U72 stage. At this point pins 9 and 10 of the
second section in U72 go high and low respectively. Pin 9 supplies
PIAK on pin 5 of J2. When high, PIAK signals the external device
that Sol has yet to complete acceptance of the data. The state of
pin 10 of U72 is transmitted to INTI of the Internal Data Bus through
a U7l tri-state noninverting buffer. U7l is enabled only for the
duration of PORT IN FA (auxiliary status). During the time U7l is
enabled, the CPU reads the Internal Data Bus. A high INTI indicates
the parallel input data is not ready~ a low indicates the data is
ready.
.
The second u72 flip-flop is preset by ~ORT IN FD or POC&
is active to read data in from the PP: POC occurs only
when Sol is restarted or power is turned on. Thus the PP is reset
and ready for another transfer at the end of a transfer or when POC
is active.
~P~O~R~T~·-IN~~F~D~
REV A
VIII-18
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
PXDR on pin 16 of J2 is supplied by the external device. It
indicates the device is ready to receive data. PXDR is buffered to
INT2 and will effect the transfer of data to the Internal Data Bus
during the status input to the cpu. PXDR is analogous to the previously discussed PIAK signal.
Sense switches S2--1 through 8 are driven by PORT IN FF when
it is low. Thus, the DIO lines connected to closed switches are
driven low, and those connected to open switches are pulled high.
U97 (a 4-bit D-type register) and one section of U52 (a J-K
flip-flop connected as a D flip-flop) latch five bits of data on
DI03-7 when PORT OUT FA goes active. These bits, which supply the
indicated outputs, control conditions in both the PP and CDI. with
respect to the PP, PIE enables parallel input, and PUS selects the
parallel device for the transfer. The data in these two latches remains until either a new word is read out or POC goes active.
Also during PORT OUT FA, the keyboard flag is reported.
KEYBOARD DATA READY on pin 3 of J3 is a low going pulse 1 to 10 usec
in duration.
It is applied to pin 13 of J-K flip-flop U70. Some
time after pin 13 of U70 goes low, but before 500 nseCj u70 is set
by ¢2 and pin 10 goes low. 'J'his low is buffered through U71 to INT¢
to indicate the keyboard is ready to send data. Reset of U70 occurs
with a POC or by PORT IN FC. The latter occurs when data is accepted
from the keyboard.
The other half of flip-flop U52, with its output on pin 6,
latches one bit of status, DI04, when PORT OUT F8 is active. Its
output is applied to pin 5 of one operational a~mplifier section in
U56 to become the SRTS (request to send) signal on pin 4 of Jl, the
SDI connector.
The SDI/UART centers around a UART, U51. The UART transmission conditions (parity, word length and stop bits) are determined by
the settings of S4-1 through 5.
(Refer to Paragraphs 7.5.8 through
7.5.10 in Section VII for descriptions of the switch settings and
their effect on transmission.
Data destined to leave Sol through the SDI/UART enters the
UART on its TIl-6 inputs from the Bidirectional Data Bus when TBRL
(pin 23) is low~ that is, when PORT OUT F9 goes active. Circuitry
within the UART serializes the input data, which is in parallel form,
and outputs it on pin 25 at a rate determined by the clock on pin 40.
The binary states at pin 25 are low for a zero and high for a one.
Assuming Sol is not in local operation ("off line") ·the output on
pin 25 of the UART is applied to pins 2 and 11 of Jl via two gates in
U55 and the other half of U56.
I
VIII-19
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
Data that enters Sol through the SDI/UART on pins 3, 12 or 13
of Jl is input to the SDI UART on pin 20 by way of U38, an inverting
level converter that converts data levels of up to +25 volts to TTL
levels.
(Note that current loop data on pin 12 or 13 of Jl is first
rectified before it is applied to U38.) The UART converts this serial
data into parallel form and outputs it on ROI through R08 (pins 12
through 5 respectively) to the Internal Data Bus when ROD (pin 4) is
low; that is, when PORT IN F9 goes active.
The receive-transmit clock for the SDI UART is supplied by
the Baud Rate Generator (U84, U85, U86 and their associated circuitry). U85 is a phase locked loop, U86 is a 7-stage binary counter
and U84 is connected as a divide-by-ll counter. The 1200 Hz reference signal applied to pin 14 of U85 is supplied from the Video Display Generator. A phase comparator in U85 compares this signal to
the output of a voltage controlled oscillator (VCO) in U85. By feeding an output from U86 (in this case the 1200 Hz output on pin 3)
back to the compare input (pin 3) of U85, the circuit acts as a frequency multiplier. The output (pin 4) of U85 remains locked, therefore, to a multiple of its input on pin 14. In this case we have a
128X multiplier to generate 153.6 KHz which is counted down in U86.
Since U86 is a 7-stage binary counter, the first stage output (pin
12) is 76.8 KHz (one-halt' of 153.6 KHz, the clock for U86), the second stage output (pin 11) is 38.4 KHz (one-fourth of 153.6 KHz),
the third stage output (pin 9) is 19.2 KHz (one-eighth of 153.6 KHz),
and so on to the seventh stage output (pin 3) which is 1.2 KHz (1/128
of 153.6 KHz).
Wi.th the exception of outputs on pins 12 and 9, the outputs
of U86 are connected to S3, the Baud Rate Switch. The 19.2 KHz output on pin 9 is divided by 11 in U84 to supply 1745 Hz to S3-2. The
38.4 KHz on pin 12 can be connected to S3-8 instead of the 153.6 Hz
clock by cutting the L-M connection and installing a jumper between K
and M.
Let's now translate the frequencies input to S3 into Baud
rates. The Baud rate of a UART is 1/16 of its clock rate. Thus, a
1200 Hz clock equates to a 75 Baud transmission rate, a 1745 Hz clock
equates to a 109.1 (110) Baud rate, etc. It is now readily seen that
the Baud rate available with S3-8 is 9600 assuming the L-M connection
is made (153.6 KHz 7 16 = 9600).
(The L-M connection is default
wired on the Sol-PC; that is, there is a trace between Land M on the
circuit board.)
If the L-M trace is cut and a jumper is installed
between K and M, the Baud rate with S3-8 is 4800 (76.8 KHz : 16 =
4800) •
We can thus select anyone of eight clock frequencies for the
SDI UART with S3, with the highest being determined by the K, Land M
jumper arrangement.
The selected clock is applied to both the receive and transmit clock inputs (pins 17 and 40 respectively) of the
UART. This means, of course, that the UART always receives and transmits at the same Baud Rate.
VIII-20
PROCESSOR
TECHl~OLOGY
CORPORATION
SEcrION VIII
Sol 'rHEORY OF OPERATION
Returning to the SDI UART, we seQ that its transmitter output
on pin 25 is applied to pin 5 of U55, a tW'.)-input NAND gate that is
functionally a ROR gate. It is normally enabled on pin 4 by pull-up
resistor R44. A low on pin 5 represents a binary 50; a high represents a binary 1. The inverted output on pin 6
U55 is again
inverted (assuming Sol is not operating in Local) by the following
U55 NAND gate. One-half of operational amplifier u56, operating open
loop, converts TTL levels to RS-232 levels (5 to 15 volts). Pin 3 of
U56 is held at +2.5 V dc by the R47 and R48 divider network. When
pin 2 is more negative than pin 3, the ou·tput on pin 1 of U56, which
is fed to pin 2 of Jl, is at approximately +10 volts. For the opposite condition, pin 2 of Jl is about -10 volts. Thus, U56 also
inverts, and a high or low on pin 2 of Jl represent a binary 1 and 50
respectively.
0=
Two conditions can override transmitted data:
a keyboard
break (BRK) or local (KBD LOC) command. For a break com~and, BRK on
pin 4 of J3 and pin 4 of NOR gate u55, is low to hold pin 6 of u55
high for the duratio::l of the BRK signal. This appears as a "space",
or high level, on pin 2 of Jl.
(A space, or break, condition requires that the space level exist for a period longer than the normal
length of a character.) In the case of a KBD LOC command from the
keyboard, pins 1 and 13 of the other two U55 sections are low. Thus,
data cannot be transmitted to pin 3 of NAND gate U55, and pin 11 of
NOR gate u55 is held high to enable tri-state driver U37 at pin 15.
Data on pin 6 of u55 is consequently looped back by way of U37 and
R21 to pin 12 of U38. Data on pin 12 of U38 overrides any data arriving at pin 13 of U38. In local operation, therefore, data from
pin 25 of the UART does not appear at pin 2 of Jl, but it is looped
back to the receiver input (pin 20) of the UART via U37, R21 and U38.
Notice that data on pin 25 of the UART will also be looped
back if S4-6 is closed (half duplex operation). But in this case,
data from the UART is also fed to pin 2 of Jl.
Serial data from the UART that appears at pin 1 of u56 also
drives transistor Ql by way of R45 and R46 to supply the serial current loop output (SCLO) on pin 11 of Jl. Ql supplies 20 rna. (max.)
current for a binary 1 and no current for a binary 50.
Pin 23 of Jl (connected through R23 to +12 V dc) is the
serial loop current source (SLCS). It can supply up to 20 rna of
current to ground and is used when the external current loop device
has no current source.
Data received from a current loop device enters Solon pins
12 and 13 of Jl in the form of no current for a 50 and 20 rna of current for a 1. This input is rectified by bridge rectifier D3-D6 and
applied to a light emitting diode (LED) in optical isolator U39. As
its name implies, U39 electrically isolates the current loop circuit
from the rest of the Sol.
(This isolation permits a high offset
voltage on pins 12 and 13 of Jl.) For a 1, the LED is energized, and
V1II-21
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
the light is optically coupled to the base of a photo transistor in
U39 to cause the transistor to conduct. Conduction translates to a
low, or mark, level at the input (pin 13) of U38. Since both the
current loop and RS-232 received data (SLR1/SLR2 and SRD respectively)
share the input to U38, both should not be used simultaneously.
There are five external control signals in the RS-232 section
of the SDI/UART: two are sent to the external device (SRTS and SDTR),
and three are received from the device (SCTS, SCD and SDSR).
SRTS on pin 4 of Jl was discussed earlier. SDTR (serial data
terminal ready) is simply tied to +12 V dc through R24. This indicates to the external device that Sol is connected to it.
SCTS (serial clear to send), SCD (serial carrier detect) and
SDSR (serial data set ready) indicate status of the external device.
They enter Solon pins 5, 8 and 6 of Jl respectively, and all three
are active high. Following level conversion and inversion in line receivers U38, data on these lines is gated through noninverting tristate buffers U37 to the Internal Data Bus when PORT IN F8 is active.
PORT IN F8 also enables five bits of UART status to be reported over the Internal Data Bus. These are PE, FE, OE, DR and TBRE
on pins 13, 14, 15, 19 and 22 respectively of the UART. They are defined as follows:
8.5.4
PE:
Parity Error--received parity does not compare to
that programmed.
(Bit INT2)
FE:
Framing Error--valid stop bit not received when
expected.
(Bit INT3)
OE:
Overrun Error--CPU did not accept data before it
was replaced with additional data.
(Bit INT4)
DR:
Data Ready--data received by UART is available
when requested.
(Bit INT6)
TBRE:
Transmitter Buffer Register Empty--UART is ready
to accept another word from the Bidirectional
Data Bus.
(Bit INT7)
Display Section
An understanding of how characters 'are formed on the video
monitor will help you follow operation of tpe display section.
The monitor screen can be thought of as a large matrix of
small light elements, or dots, that can be turned on and off. In
this context the overall video presentation consists of light and
dark dots.
VIII-22
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
In the Sol, the display format is 64 characters maximum per
character row, with a maximum of 16 rows per frame (page).
Thus,
up to 1024 characters can be displayed per page.
A 9 x 13 (columns by lines) dot area, or character position,
is alloted on the monitor screen for each displayed character (see
Figures 8-2 and 8-3 on Page VIII-24). Consequently, each character
row consisting of sixty-four 9 x 13 dot areas requires 13 horizontal
scan lines. To provide spacing between both characters and rows,
only 1:> dot lines and seven dot columns within the 9 x 13 matrix are
used for character display. Only nine of the available 12 dot lines,
however, are used for any given character.
Let's take a closer look at how the 9 x 13 dot matrix is used.
The first seven dot columns are available for all character displays;
the last two are used to provide a space between characters.
The
first dot line in a character row is always blank to provide a space
between character rows. As shown in Figure 8-2, the second through
tenth dot lines are available for all upper case (capital) and control characters, all symbol and punctuation marks (except the comma
and semicolon), and all lower case characters (except the g, j, p,
q and y). As shown in Figure 8-3, dot lines five through 13 are
available to display characters that normally extend below the base
line--lower case g, j, P, q and y plus the comma and semicolon.
Now that we have a feeling for how characters are formed on
the video monitor screen, we will move on to the circuit description.
Refer to Display Section Schematic in Section X, Page X-17.
The 14.31818 MHz DOT CLOCK, which defines the period of one
dot (69.8 nsec) in a character display matrix, controls all timing
in the Video Display Generator. DOT CLOCK is applied to pin 2 of
U28, a four-bit binary counter that is preset to count from seven
through 15 to divide DOT CLOCK by nine. Two 1.591 MHz outputs are
supplied by U28: LOAD CLOCK on pin 11 and CHARACTER CLOCK on pin 12.
Pin 11 is a low-active pulse of one DOT CLOCK duration. Pin 12 is
high for five and low for four DOT 'CLOCK periods. Both the LOAD and
CHARACTER CLOCK low-to-high transitions occur synchronously on the
same DOT CLOCK.
CHARACTER CLOCK, which defines the period of one character
position (628 nsec) , is inverted in U49 to become CHARACTER CLOCK.
It performs most of the clocking functions in the Video Display Generator and is made available on pin 4 of J4 for use by external
graphic display devices.
I
\.
CHARACTER CLOCK is in turn divided in U31 and U33, both of
which are presettable four-bit binary counters. Both start at count
3 when pin 8 of NAND gate U47 is low, and together they count 102
CHARACTER CLOCKS to define horizontal timing at 64 usec (102 x 628
nsec = 64 usec).
REV A
VIII-23
PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
CHARACTER
ADDRESS *
1001001
1001001
LINE
ADDRESS
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
SECTION VIII
SCAN
LINE
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
COLUMN NO.
123456789
000000000
0 • • • • • 000
000.00000
000.00000
000.00000
000,00000
000.00000
000.00000
000.00000
0 • • • • • 000
000000000
000000000
000000000
• =
*7-bit ASCII code for I
Figure 8-2.
VIDEO INFORMATION BITS
000000000 (blank)
011111000
000100000
000100000
000100000
000100000
000100000
000100000
000100000
011111000
000000000 (blank)
000000000 (blank)
000000000 (blank)
illuminated dot
Example of uppercase character (I) display.
\
CHARACTER
ADDRESS*
1110000
1110000
LINE
ADDRESS
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
SCAN
LINE
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
COLUMN NO.
123456789
000000000
0'0 00 00 00 a
000000000
000000000
. 0 • • • 0000
• • 000.000
,0000.000
,0000.000
.,000.000
. 0 • • • 0000
,00000000
.00000000
.00000000
000000000
000000000
000000000
000000000
101110000
110001000
100001000
100001000
110001000
101110000
(blank)
(blank)
(blank)
(blank)
ioobooooo
100000000
100000000
• = illuminated dot
*7-bit ASCII code for p
Figure 8-3.
VIDEO INFORMATION BITS
Example of lowercase character (p) display.
VIII-24
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
As indicated in Figure 8-4 on Page VIII-27, Subgroup Counter
U3l and Group Counter U33 are preset to a count of 3 at the. start of
each horizontal scan line. U3l counts from 3 through lS (13 character positions) and enables U33 for one count. U3l then counts ¢
through lS and enables U33 for the second count. The sequence continues through four more groups of 16 character positions, and at
this point U33 is at its sixth count (a binary 9). Thus, pins 11 and
14 are high at pins 10 and 11 of U47. U3l continues to count from ¢,
and on the ninth count (a binary 8) pin 9 of U47 goes high. The resulting low on output pin 8 of U47 loads three into U3l and U33, and
the cycle repeats. The U3l-U33 cycle, from preset, is then 13, 16,
16, 16, 16, 16 and 9 character position counts for a total of 102.
The QD output on pin 11 of U33 is SCAN ADV, and the QC output
on pin 12 is HDISP. SCAN ADV is used to generate horizontal synchronization signals, and HDISP defines the start of the display portion
of the horizontal scan line.
Four o·,~~tputs from U3l and the two low order outputs of U33
(pins 13 and 14) are input to the Character Address Multiplexer, U30
and U32, which supplies the low order six address bits to the Display
RAM (U14 through U2l). The second address source for the Display RAM
is the Address Bus, bits ADR¢-S. Address source selection is controlled by the output on pin 7 of D flip-flop U7S. Pin 7 of U7S goes
high when PAGE CC (the Display. RAM) is active and PSYNC • ~ goes
high (which it does in the middle of PSYNC). Pin 7 of U7S remains
high for the rest of the memory access cycle.
The preset signal (pin 8 of U47) to U31 and U33 is applied to
the Scan Counter (U40) via inverter U87. U40 counts the horizontal
scan lines that make up a row of characters and supplies the line
number to U2S, the Character Generator ROM.
(This ROM is discussed
later.) U40 is preset to a count of IS for the first scan line in
the character row.
It then counts from ¢ through 11. On count II,
SCAN ENABLE on pin 8 of U47 is inverted in u87 to disable the Scan
Counter. A decoder, comprised of NAND gates US9 and U60, decodes the
13th count (count 11) in U40 and SCAN ENABLE to supply a load pulse
to pin 9 of U40. This resets U40 to a count of lS, and the cycle repeats.
(Presetting the Scan Counter to a count of IS permits the
Character Generator ROM to provide a blank spacer line between character rows since line IS in the ROM is always blank.)
I
"-
The output on pin 8 of NAND gate US9, after inversion in U87,
becomes the OVERFLOW LINE signal. This signal occurs after each
character row and appears at pins 7 and 10 of Text Counter U62 to
enable it to count. Thus, the Text Counter counts character rows.
It resets itself with its c~rry output (pin IS) through another inverter in U87, with the reset count being determined by the state on
pin 10 (VDISP) of J-K flip-flop U43. If VDISP is low, the Text
Counter resets to a count of ¢i if VDISP is high, it resets to a
count of 12.
VIII-2S
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
Assume VDISP is active (low), which it is during the vertical
display portion of the displayable area on the screen.
(Refer to
Figure 8-4.) U62 is then preset to a count of ¢ and will count from
¢ through 15 (16 character rows). The resulting carry output on
count 15 of the Text Counter causes the U43 VDISP flip-flop to toggle.
It also appears as a low on the load. input of the Text Counter. The
Text Counter is also enabled to reset by virtue of the OVERFLOW LINE
going low after the reset of the Scan Counter. Since VDISP is now
high, the Text Counter is reset to a count of 12 and will count 12
through 15 (four character rows). The carry output from the Text
Counter then causes the U43 VDISP flip-flop to toggle, and the Text
Counter is reset to a count of ¢. We can now see that the Text Counter counts 16 character rows when the display is active (VDISP is low)
and four character rows when the display is blanked (VDISP is high).
The total of 20 character rows represents a full display of 260 scan
lines for 60 Hz operation (13 scan lines/row x 20 rows = 260 scan
lines per page).
Horizontal and vertical synchronization signals are generated
by two one-shot multivibrators consisting of three two-input NOR gates
in UI02. Horizontal sync is triggered by SCAN ADVANCE and vertical
sync by VDISP. Both circuits generate fixed-length sync pulses with
adjustable starting times. C52 determines the length of the horizontal sync pulse and C53 the length of the vertical sync pulse.
The
starting times, with respect to triggering, are variable with variable resistors VRI (HORIZ) and VR2 (VERT) to provide continuous
adjustment of the display position on the screen. An exclusive OR
gate in U74 combines the two sync pulses into a composite sync (COMP
SYNC) signal. Note that the use of the exclusive OR inverts the horizontal sync pulses when the vertical sync pulse appears.
Since
vertical sync information is extracted in a monitor by an integrating,
or averaging, process, this technique maintains horizontal synchronization during the vertical sync period.
Two types of blanking are available: control character blanking and video blanking. The first blanks control characters and
causes cursor information to be displayed in their place. Video blanking forces portions of the video display to a white or black level,
depending on whether normal or reverse video is selected with Sl-4.
Control character blanking, switch selectable with Sl-3, is
accomplished with one NAND gate in U60 and one NAND gate in U6l.
When a control character is present in the Data Latch (U26 and U27),
pins 3 and 15 of U26 are high. Assuming the blanking option is selected (81-3 closed), the output of U60 (LOAD CLOCK) is gated with
the control character bits by U61 to clear the video p,3.rallel-toserial converter, U41.
U4l then loads all zeros instead of the
character.
Video blanking is initiated by the PRE BLANK or COMP BLANK
(pin 14 of Blank Latch U42) inputs to U59, a three-input NOR gate.
The third input, the video output on pin 6 of exclusive OR gate U74,
is blanked when any of the two blanking inputs is active.
VIII-26
HORIZONTAL
f
GROUP
COUNTER (U33)COUNT"0011(3)
SUBGROUP
COUNTER(U31 )COUNT" 0011(3)
CHARACTER
CLOCKS (PIN 8, U47)
t
0101(5)
0110(6)
0111(7)
1000(8)
1001(9)
OOOO(fij)
OOOO(fij)
OOOO(fij)
OOOO(fij)
OOOO«(IJ) 1000(8)
0100(4)
°i(fij)
RETRACE
t
t
t
t
1001(9)
f" f"
~ ~ ~ ~ ~ ~ ~ ~i ij~~ ~ ~~~ ~~ I~ ~ ~ ~ ~ ~ ~ ~ ~~~~~~~ ~ ~ ~ ~ ~~~ ~~ 1111111~i~~ 1111111 ~ t~ 1111111 ~i ij~ 1111111 ~ ~ j~~ 11 ~ ~ ~ ~ ~ ~ i~~ ~ ~ ~ ~ ~ ~ ~ ~ ::~! ~ ~ ~ ~ ~ ~ ~ ~ ~ i~ ~ ~ ~ ~ ~ ~ ~ W~ ~ ~ ~~1 ~ ~ W
:~H~~~n~:: :~H~~~!tl!:~:::::::c~~~r:lif:t:: :::::~HA~~r:lif:t: :::::~~A~A:ei:~~:
: :p,.·0··:';;:;':I·Q·· Mid:
:: .P..Gs.I:tI·O··N·· ·S·:: d:::: .P..r...~1·0··N·· ·S·:::
::c:f.f~~A~!tl!:~ ::~HAIt~f:ER
:l: :::p..·0···S··J:;,;:nN··";:: :!::: :P... ;:,:S··1· :r;y:wS··: :1:: P'G.SrT. ·I;m.;.;: :: :";0··5··I·I:··I~iS·
11~1nmm~~~lm11!111~11HH~~~~n111~(~Hmmll~~~~H11 ~H~H~~~lllm~~m~ ~!11Hm~~~m0~~~ 1! HHmUrmm ~~mnnHrrm~
lml1111111]llml ullmll1111ll~
mllffillill!llffil1
nnnn~ ~ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~
lHHHHH
:::::::::::::::::::::
H
H
VDISP
(PIN 10,U43)
ACTIVE
H
I
N
-....J
VERTICAL
RETRACE
AR EA'
.
1
ON SGREEN
.:::::::::::::::::::::
.................... :::I::::::::::::f
··················'1
. lHHHHHH HHlH}{
. ::::::::::::::::::::: :::::::::::::::::::
MAXI MUM
................ .....
.....................
1
:::::::::::::::::::::
.....................
HHHlHH
:::::::::::::::::::::
'DISPLAYA~LE
:;:::::::::::::::::::
<:
1
~ ~ ~ ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~! n~ ~ ~ ~ ~ ~~ ~ ~ ~ ~~:
jjjjjjjjjHHjjH :::::::::::::::::::
jjjjjjjjjjjljjjjjt
.....................
···1··········· ··E·.
.:::::::::::::::::::::
....................................
1
,
:::::::::::::::::::::
.....................
ljjjHHHHl
.....................
.....................
:::::::::::::::::::::
.....................
.....................
.....................
.....................
.....................
I
(16
,
~INES
1
OF 64 CHARACT ~ RS)
I
:::::::::::::::::::::
:::I:::::::::::::~.
......................................
llllllllllljjlljlllll
lljjlljjllllj~ljili"
.......................................
..................................... .
::::::::::::::::E:::::::'::::::::::::~:
jjj .....
jH H
...
.... H
....
..................................... .
11111111111~ 1111
~1~1~11~1~11111 ~:~~~~~~~·~~~~~~~1~~~~:~
T
HSYNC(PIN 10, US8)
JELL H l HlHWHLlHl
::::::::::: :::: :
U
T~~ ....
~~~~ ....
... .....
m~TIT; fIT~ ITTI
Hl .....
lH H
...
.... H
....
Hl Hl H HH
~!
~i
:::::::I·::::::::::::~::
u
rm
HPOS(PIN 4,UI02)
~n~~~~~~uY~nn~.
.y~~~~~~~
.....................................
:
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~i
......................
......................
::
~Il..
..il
jl
..1l
jl
II
II..
~:
~:
: ~rrr;~~m;
..ji
H lHHiHHlHl.
.lHHH
.......................................
DlHHH H HHl@lHIlj
H lHHiHEEHJj.
.DEEHl
.......................................
If:HlHll H HlHHjjjjHI
lClHt
tl HHlHHlHHl
:.:::::::::::: :::: :::::::::;::::::::::: :::
~i
..ji
~~
~~
1~
;
li
~i
:;
~m;~mt~m~;rrr:~r:
VSYNC(PIN 4,U88)
SCAN ENABLE
{ (PIN 8, U47)
ACTIVE
HDISP
(PIN 12, U33) ACTIVE
n
~
I
::: ::::: :::: ::::
VPOS
(PIN 15,U88)
ACTIVE
::::::::::::::::::::: ::::::::::::::::::i
VDISP(PIN 10, U43)
SCAN COUNTER(U40)
and TEXT COUNTER
(U62) All Change On
This Clock Edge.
DISPLAYABLE PORTION OF SCREEN
H~H
BLANKED PORTION OF SCREEN
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
The PRE BLANK input provides "window shade" blanking which is
analogous to pulling a window shade down from the top of the display.
PRE BLANK is generated in one half of J-K flip-flop U43. U43 is reset by the TC output of First Screen position Counter, Ull, and set
by VDISP. The output on pin 7 of Ull is generated by the scrolling
circuitry (to be discussed later) and defines the character row for
which the "window shade" ends.
It may begin with any character row
from zero through 14.
The remaining video blanking function concerns the output on
pin 14 of D flip-flop U42. This signal, COMP BLANK, is a composite
of HDISP and VDISP.
Since there is a two character time delay between Display RAM
addressing and the corresponding video output on pin 6 of exclusive
OR gate U74, the horizontal and vertical blanking signals must be delayed an equal amount. U42, connected as a two-stage shift register,
functions to shift the blanking into synchronization with the video.
Since U42 is clocked by LOAD CLOCK (which has a period equal to one
character time), COMP BLANK is delayed two character times from the
input on pin 4 of U42. COMP BLANK is active low during nondisplayable portions of the video scan to override any video input data on
pins 1 and 2 of NOR gate U59. The display is thus blanked.
The Display RAM consists of eight lK x 1 bit RAM (random access memory) chips, U14 through U28. All chips are held permanently
enabled by connecting their CE (pin 13) inputs to ground. Memory addressing is provided through two-to-one multiplexers (U30, U32 and
U12) which select one of two display address sources: 1) an external
address on Address Bus bits ADR¢-9 and 2) an internal address supplied by the Subgroup Counter (U31), Group Counter (U33) and the
Beginning Address Counter (Ul). The function of the address bits
associated with each address source is as follows:
1.
External address bits ADR¢-5 specify the character
position (one of 64) in the character row.
2.
External address bits ADR6-9 specify the character
row position (one of 16) on the display screen.
3.
Internal address bits, a total of six outputs from
U31 and U33, specify the character position (one
of 64) in the character row.
4.
Internal address bits, the four outputs from Ul,
specify the character row position (one of 16) on
the display screen.
VIII-28
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
Normally the internal display address is multiplexed to the
Display RAM. When the CPU or a DMA device requests access (PAGE CC
active), the multiplexers switch to the external address lines,
ADR¢-9.
Seven-bit ASCII-coded data is written into RAM chips U14
through U20 from bits DIO¢-6 of the Bidirectional Data Bus, and the
cursor bit (DI07) is written into RAM chip U21. This writing occurs
when the write enable (WE) input to the RAM chips is low. This occurs when the Display RAM is addressed (PAGE CC active low) and
MWRITE on S-lOO Bus pin 68 is high. The enable is supplied on output pin 8 of NAND gate U44. Data is read out of the Display RAM
when pin 8 of U44 is high. Data out of the Display RAM is placed on
the Bidirectional Data Bus via tri-state drivers U29 and u89 when
PAGE CC and PDBIN (S-lOO Bus pin 78) are active. U29 and u89 are
enabled by a low output on pin 11 of another U44 NAND gate.
Data out of the Display RAM is also strobed into Data
Latches U26 and U27 by LOAD CLOCK. Seven outputs from these latches
are used to address the Character Generator ROM, U25. Note that the
output from RAM chip U19 is inverted in exclusive OR gate U74 before
being applied to the C input (pin 13) of U26" and the complement
(pin 14) of the QC output of U26 is used in addressing U25. This is
done so that the Data latches will output the space code (¢l¢¢¢¢¢)
to the Character Generator ROM when the latches are reset. These
latches are reset each time PAGE CC is active by way of U75, a J-K
flip-flop connected as a D flip-flop, and D flip-flop U42 (Q output
pin 6). By outputting the space code on reset, the Data Latches
insure a blank character position on the screen.
The Character Generator ROM, U25, has seven character address inputs (Ai through A7), four scan line inputs (RSl through
RS4) and seven data outputs (Bl through B7). It is programmed to
generate seven bits (dots) of character information for the selected
scan line of the character row. U25 also automatically blanks scan
lines that are not a part of the character and shifts the g, j, p,
q, y, comma and semicolon to the fifth through 13th scan lines in
the dot matrix (refer to Figures 8-2 and 8-3 on Page VIII,..24). Complete patterns for the 6574 and 6575 Character Generator ROM's are
provided in Figures 8-5 and 8-6 respectively. Note that the address
bits A¢ through A6 in Figures 8-4 and 8-5 correspond to the Al
through A7 inputs to U25 on the schematic, scan lines R¢ through R8
are specified by the RSl through RS4 inputs to U25 on the schematic,
and the data output bits D¢ through D6 correspond to the Bl through
B7 outputs from U25 on the schematic.
Let's see how the Character Generator ROM produces a charac,...
ter using an uppercase "C" and "TII as an example. In this example,,'
these two characters are ,to be displayed in the first and second
character positions respectively on the third character row of the
display screen. Remember that the character position and row parameters are contained in the Display RAM since the' 7-bit ASCII-coded
VIII-29
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
..............
• DOODDD
.000000
aDOODDD
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• • • • 000
• • • • 000
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.000000
, . = Shifted character. The character is shifted three rows to R3 at the top of the font and Rl1 at the bottom,
Figure 8-5.
6574 Character Generator ROM pattern.
"c" and "T" were stored in the RAM in the proper character positions
in the third character row.
After the first two character rows have been displayed, the
Scan Counter (U40) is reset to a binary count of 15 (llll) and the
Character and Line Address Multiplexers (U30, U32 and U12) call up
the "c" in the Display RAM. The Scan Counter output specifies line
15 in the Character Generator ROM on RSI through RS4. As previously
mentioned, this line in the ROM is blank. Thus, the first scan line
of the third character row is blank.
The 7-bit ASCII code for the "c" (l¢¢¢¢ll) is input from the
Display RAM to address the Character Generator ROM by way of the Data
Latches (U26 and U27). This address is applied to ROM inputs A7
through Al (A6 through A¢ in Figures 8-5 and 8-6). The Scan Counter
changes to a count of zero which specifies scan line R¢ in the Charac-,
ter Generator ROM. As shown in Figures 8-5 and 8-6, the ROM in turn
outputs a 7-bit word, ¢¢llll¢, on D6 through D~ respectively (B7
through Bl on the schematic).
VIII-30
,,'
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
~
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0 ••••••
.00aCOD
aOO.DlJO
0 ••••• 0
noollooa
OOO.COIi
•••••• 0
(Joo.con
000.000
"ii!m I~!~Ir
OOa~OO[l
oODOoOO
aaaDDOO
ooaoooo
o[]aOODO
ooaoooo
ooaODllo
DOOllaoO
aOCODoa
oaceoao
UDOCJcao
cODOBOC
o~acaoo
00
00
00
00
DO
DO
DO
00
00
00
00
00
IIII!
aD
DO
DOD
DOD
DOD
DOD
DO
00
0111111
00
0000000
DO
DO
DO
DOD
, . ". Shifted character. The character is shifted three rows to R3 at the top of the font and R 11 at the bottom.
Figure 8-6.
6575 Character Generator ROM pattern.
For the second character position the Character and Line Address Multiplexers call up the "T" in the Display RAM. The resulting
ASCII code for a "T" (1.01.01.0.0) ultimately appears on the address inputs to the Character Generator ROM. Since the Scan Counter is still
at a count of zero, the ROM outputs 1111111. This process continues
for the balance of the displayable portion of the video scan line.
At the end of the horizontal scan line, the Scan Counter
changes to a binary count of .0.0.01 which specifies scan line Rl in the
Character Generator ROM. The "c" and "T" are again called up from
the Display RAM for the first and second character position respectively. The ROM consequently outputs .01.0.0.0.01 and then .0.0.01.0.0.0. This
sequence continues through scan line R8 when the Scan Counter is at a
count of 8 (1.0.0.0) to produce the "c" and "T".
As discussed earlier, the Scan Counter cycles through 13
counts or scan lines. For the "c" and "T" in our example, the Scan
Counter has counted ten lines (15, .0, I, 2, 3, 4, 5, 6, 7 and 8).
The remaining three scan lines are not used in forming the "c" or
"T", so on counts 9, 10 and 11 of the Scan Counter the Character
VIII-31
,
PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
Generator ROM automatically outputs all zeros for these two character
positions. After the last scan line in the third character row, the
Scan Counter is reset to a count of 15 to start the fourth character
row.
The Character Generator ROM output is converted from parallel
to serial form in an 8-bit shift register (U41) that is clocked by the
rising edges of DOT CLOCK. Shift and load control is provided by LOAD
CLOCK. Parallel input bit PH (pin 14) and serial input (pin 1) are
connected to ground to generate the two horizont"al spacer dots between
characters. Following the first seven data bits, the eighth DOT CLOCK
shifts a zero from the grounded serial input into QH to supply the
first spacer dot. The ninth DOT CLOCK, which arrives when LOAD CLOCK
is low, loads the next parallel dot pattern. QH, however, remains low
during the next DOT CLOCK period since PH is at ground, thus supplying
the second spacer dot. LOAD CLOCK then goes high and the sequence repeats.
A blink oscillator (two inverter sections in U88), a latch (one
section in U42) and their associated components comprise the cursor
circuit. The blink oscillator runs continuously at a rate set by R84
and C36.
Its output has a nominal 0.5 sec period. If the blink option
is selected with Sl-5, the blink signal is applied to one input of a
gate in U60. The other input to this gate is provided by the blink
latch, one section in U41.
If the cursor bit QA out of Data Latch U26
is high, D flip-flop U42 sets for the time the ROM is active on the
character and remains set during the period when video data is shifted
out of U41. The output of U42 is gated high through NAND gate U60
when BLINK (pin 6 of U88) is low. BLINK is held low when the blink
option is not selected. The output of U60 is in turn gated with the
video output of U4l in U74, an exclusive OR gate. U74 thus inverts
the video if the output of U60 is high, and no inversion takes place if
the output of U60 is low.
The video signal including the cursor, is gated to pin 9 of
another U74 exclusive OR gate in the absence of any blanking signals
at the other two inputs to NOR gate U59.
If Sl-4 is open, U74 inverts
the video signal to produce a reverse (black on white) display. Raw
video on pin 8 of u74 is supplied to pin 15 of J4. Video out on pin 6
of inverter U87 is combined with COMP SYNC on pin 8 of another U87 inverter in a resistive mixer, R80-R82, to meet EIA composite video signal standards, and coupled to PI for use by a video monitor. This
mixer has a 6l-ohm output impedance.
Both Beginning Address Counter Ul and First Screen Position
Counter Ull are enabled to advance their counts when pin 9 of J-K flipflop U75 is low, which it is for about 600 nsec following OVERFLOW LINE;
that is, after the Scan Counter (U40) is loaded. This, of course,
~ccurs at the end of every scan line in the character row.
The scroll circuit consists of Ul, Ull, Scroll Control Latch
U2 and Screen Position Control Latch U13 and their associated circuitry.
Jl and Ull are up and down counters respectively that are pre~EV
A
VIII-32
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
set to the outputs of latches U2 and 13. U2 latches the starting row
address from DIO~-3 and U13 latches the data on DI04-7, with
PORT OUT FE being the strobe. D~ta on DI04-7 specifies where the
first line will be displayed. Thus, the number loaded into Ul is
the address of the first displayable scan line, and the number loaded
into Ull defines the character row (~ through 15).
Ull is preset by VDISP from pin 9 of J-K flip-flop U43. This
means Ull is forced to its preset condition from the end of the displayed text to the top of the next character row. During this time,
pin 6 of another U43 J-K flip-flop is set high to preset Ul. If Ull
is preset to ~, its TC output on pin 7 is low and pin 6 of U43 is reset to a low. This allows Ul to count with each horizontal scan line.
If Ull is preset to any number other than ~, pin 6 of U43 cannot be reset low until Ull reaches zero. Assume Ull is preset to
two. It must count down two character rows before Ul starts counting. During this time, pin 7 of U43 (PRE BLANK) is low, and as previously discussed, the display is blanked.
We can now see that the PRE BLANK time, often called IIwindow
shade II , is variable with the number loaded into Ull. Therefore,
scrolling is performed by changing the numbers in U2 and U13 without
the need to reposition the text within the Display RAM.
The remaining circuit in the Display section consists of
transistor Q2, one section of U87, 89 and 102. U88 and UI02 are connected as a one-shot 250 msec timer that is triggered when
PORT OUT FE goes active (pin 1 of inverter U87 goes high). Thus,
when data is loaded into U2 and U13, this timer starts. Tri-state
driver U89, which is enabled by PORT IN FE, transmits the state of
this timer to DIO~ on the Bidirectional Data Bus. The CPU can consequently test the timer status by looking for a high on DIO~. This
timing allows a 250 msec scroll rate without the need for complex
timing routines in the CPu. Q2, RI02 and C37 serve to speed up timer
reset.
8.5.5
Audio Tape I/O
Refer to Audio Tape I/O Schematic in Section X, Page X-lB.
Timing for the Audio Tape I/O is derived from the 1200, 2400,
4800, 19,200 and 38,400 Hz signals received from the Baud Rate Generator in the Input/Output section of Sol. The first two are used by
the write data synchronizer (UIOO) and the digital-to-audio converter
(UIOl).
The remaining
a quad multiplexer or
used to select clocks
to the select inputs,
select inputs must be
REV A
three signals are fed to two sections of Ulll,
select gate. All four sections of Ulll are
for low speed or high speed operation according
pins 9 (A) and 14 (B). The states of these two
complementary to each other in order to select
VIII-33
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
the high or low speed clocks. Specifically, A must be high and Blow
to select high speed clocks; the converse condition selects low speed
clocks. The select inputs are supplied by TAPE HI SPEED and
TAPE HI SPEED.
The output of the second section on pin 11 of ulll is BYTE
WRITE CLOCK, 4800 Hz on low speed and 19.2 KHz o~ high speed. The
third section outputs a 19.2 KQz (high speed) or 38.4 KHz (low speed)
timing signal to input pin 10 of binary up counter (Ul12).
RECOVER CLOCK is produced by a phase locked loop (UIIO), another Ul12 binary up counter and the first and fourth sections of Ulll.
The signal input (pin 14) to UIIO is supplied from output pin 1 of D
flip-flop Ul13. It is a constant frequency, regardless of whether
one. or two transitions are detected in the read data during the
count out time (12 counts) of the Ul12 counter with outputs on pins
13 and 14. A phase comparator in ullO compares the signal input to
the output of a voltage controlled oscillator (VCO) in UIIO (pin 4).
By feeding the VCO output through a counter (the other half of Ul12)
before feeding the counter output back to the compare input (pin 3)
of UIIO, the circuit acts as a frequency m~ltiplier. The output of
this circuit remains locked, therefore, to a multiple of the signal
input on pin 14 of UIIO.
The output of UIIO is nominally 19.2 KHz. The actual output
is determined by the signal input which in turn is a function of tape
speed.
In other words, the phase lock loop circuit tracks input frequency variations. And it will track such variations within its
locking range which is determined by the setting of variable resistor
VR3 (connected to pin 12 of UIIO).
For high speed, the divide-by-four output of Ul12 (pin 4) is
selected as RECOVER CLOCK. For low speed, the VCO output of UIIO is
selected for RECOVER CLOCK. This clock serves as read clock for the
CDI UART, U69.
CDI control involves PORT IN FA, PORT IN FB, PORT OUT FB,
TAPE CONTROL 1 and 2, poe (power on clear), TAPE HIGH SPEED and
TAPE HI SPEED. The last two were previously explained in the discussion of Ulll. PORT IN FA strobes the CDI UART status (DR, TBRE,
OE and FE~-refer to Page VIII-22 for definitions) to the Internal
Data Bus, INT3-7. PORT-rN FB strobes received data on pins 5-12 of
U69 to the Internal Data Bus, INT¢-7. PORT OUT FB loads data from
the Bidirectional Data Bus (DIO¢-7) into U69. poe simply resets
U69 whenever power is applied to the Sol.
TAPE CONTROL 1 a~d 2 are used to turn one or two recorder
motors on and off.
An active low TAPE CON'rROL 1 energizes K1 to
close its contacts and turn recorder #1 oni a high de-energizes Kl to
turn the recorder off. TAPE CONTROL 2 does the same thing with K2 to
control another recorder. Diodes D13 and 14, which shunt Kl and K2
VIII-34
PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
respectively, prevent damage to the logic circuitry in the Input/
Output section due to inductive kickback. R155 and,156 are current
limiters that keep the relay contacts from "welding" together.
When the CDI is in the write mode, data is input to the UART
(U69) under control of PORT OUT FB. Upon completion of this strobe,
the transmit sequence is initiated within the UART, with the transmission rate being governed by BYTE WRITE CLOCK.
The transmission sequence begins with a start bit, a low
(data zero) on the UART's TO output. It is followed by eight data
bits and two stop bits (high on the UART's TO output), with the number of bits being fixed by the connections to pins 34 through 39 of
U69.
The data from U69 is applied to the D input of D flip-flop
UIOO which is clocked at 1200 Hz. Consequently, the output on pin 1
of UIOO follows the input data on pin 5 after the rising edge of the
1200 Hz clock. This output is connected to the reset (pin 4) of
UIOl, so when the data out of the UART is high, the first section in
UIOI is forced to a reset condition. In this condition the J and K
inputs to the second stage of UIOI are held high which allows the
flip-flop to change state on the rising edge of the clock.
The clock for UIOI (OUTPUT CLOCK) is 2400 Hz in the high
speed mode or 4800 Hz in the low speed mode. This clock is derived
from 2400 Hz in conjunction with the lo~ speed select signal in NAND
gate U98 and exclusive-OR gate U99.
In the high speed mode, pins 12 and 13 of U98 are held low,
thus holding pin 10 of U98 high. As a result the 2400 Hz signal is
inverted in U99 to become the clock for UIOI.
Pins 12 and 13 of U98 are held high, however, in the low
speed mode to enable U98. In this case Rl17 and C47 provide a delay
in the U98 gate. When the 2400 Hz signal on pin 2 of U99 changes
state, so does pin 3 of U99. Also, C47 charges through Rl17 for
several usec, at which point pin 10 of U98 is brought to the opposite
polarity. The output from U99 then goes high. A series of positive
pulses, with a pulse width approximately equal to the Rl17, C47 time
constant (10 usec) and occuring at every transition of the 2400 Hz
signal, appears on pin 3 of U99. This circuit thus operates as a
frequency doubler in the low speed mode to provide a 4800Hz clock
for UIOI.
The 2400 Hz signal from '.vhich the UIOI clocks are derived also produces the 1200 Hz clock signal for UIOO. As a result the 1200
Hz signal changes state following a propagation delay after the 2400
Hz signal falls.
VIII-35
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
As previously stated, the second stage of UIOI is allowed to
change state on the positive going transitions of the OUTPUT CLOCK as
long as the data out of the synchronizer is a 111". The end result is
an output on pin 14 of UIOI that is one-half the clock frequency
(1200 Hz and 2400 Hz in the high and low speed modes respectively).
Assume the data stream out of the UART goes low (II ¢II ) • On
the next rising edge of the 1200 Hz signal, UIOO will reset with Q
low and Q high. A low reset on pin 4 of U10l enables the first UIOl
stage to toggle on the next rising edge of the OUTPUT CLOCK which occurs 1/2400 second after the synchronizer output falls. Remember
that OUTPUT CLOCK moves from a low to a high shortly before the 1200
Hz signal did. The reset on pin 4 of U10l is thus removed slightly
after the OUTPUT CLOCK occurred. with the J and K inputs to the
first UIOl stage high, its output will change state on each succeeding low to high transition of OUTPUT CLOCK. The second U10l stage in
turn can only toggle on the positive going transition of OUTPUT CLOCK
when its J and K inputs are high. Since the inputs are high at onehalf the clock rate, by virtue of the first U10l stage, the second
UIOI stage toggles at one-fourth the OUTPUT CLOCK rate.
The two sections of UIOl, therefore, operate as a frequency
divider, dividing the OUTPUT CLOCK by two when the write data is a
11111 and by four when the data is a II ¢II.. Thus, in the low speed mode,
four cycles of the 1200 Hz represent a "¢II and eight cycles of 2400
Hz represent a 11111. In the high speed mode, one cycle of 1200 Hz represents a 11111 and one-half cycle of 600 represents a II¢II.
The output on pin 14 of UIOI is applied to one section in
UI09 which provides sufficient current drive for the divider network.
This divider and a jumper arrangement allqw selecting one of three
outputs to be fed to the audio output jack J6. The I-to-J jumper selects a 500 mv signal for the auxiliary input to an audio recorder~
the I-to-H jumper selects a 50 mv signal for the microphone input to
an audio recorder.
When the CDI is in the read mode, data from the recorders
enters on J7. This input is fed to the negative input (pin 6) of
operational amplifier UI08.
The first section of U108 is a high gain amplifier, with its
gain (approximately 100) being determined by R142 and R143. The output from this amplifier is coupled to input pi.n 2 of the following
U108 stage and the base of a Darlington pair (Q4 and Q5) which provides high current gain.
Current into the base of transistor Q5 causes C67 to discharge.
(C67 charges through R39 to 5 V dc.) The voltage on C67 in
turn controls the gate of field effect transistor (FET) Q3. Q3 functions as a variable resistor which can be changed by its gate voltage.
Since Q3 is connected between ground and the input network to the
VIII-36
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
first UI08 stage, it serves as a variable shunt. A low gate voltage
on Q3 decreases the shunt resistance and the input to UI08. In a
like manner, a high voltage on C67 results in an increased input to
UI08. Q3, Q4 and Q5 with their associated circuitry, therefore,
serve as an automatic gain control (AGC) circuit which limits the input to the second UI08 stage to approximately a positive 2 volt peak
signal.
The second stage of UI08 is a comparator with hysteresis that
performs the needed audio to digital conversion. Feedback resistor
R147, in conjunction with R145, establishes the level on the positive
input (pin 3) of UI08. This level, be it positive or negative, is
the threshold voltage, ±50 mv, which the negative input (pin 2) must
exceed in order for the output of UI08 to switch levels, positive to
negative and the converse. Since the feedback loop is regenerative,
UI08 switches at its maximum rate, and UI08 switches on each transition of the audio signal input. It is in this manner that UI08 performs the audio to digital conversion.
The digital output of UI08 is inverted in one section of inverter UI09 and applied to pin 9 of exclusive OR gate U99 which is
connected as a buffer without inversion. If the output of UI09 is
low, the output on pin 10 of U99 is also low and the output on pin 4
of another U99 exclusive OR gate is high. The voltage across C49
under this condition is minimal. When the output of UI09 goes high,
C49 starts to charge through Rl18 until pin 9 of U99 crosses the
threshold of that gate. At this point pin 10 of U99 goes high, and
since the two inputs to the second exclusive~OR gate are both high,
pin 4 of U99 goes low. C49 now discharges because pins 9 and 10 of
U99 are at the same level SO that the circuit can repeat the operation on the next high to low transition at pin 4 of UI09. Rl18, C49
and U99 consequently serve as a transition detector that produces a
pulse less than one microsecond long for each transition of the output on pin 4 of UI09, regardless of the' polarity of the tran,sition.
Transition pulses from U99 clock both D flip-flops in Ul13.
A transition pulse clocks the top Ul13 at pin 3 which sets Q (pin 1)
high and Q (pin 2) low to enable·up binary counter Ul12 on pin 15.
Pin 1 is applied to the D input (pin 9) of the lower Ul13 and the
circuit remains in this state until one of two things occurs: 1)
a second transition pulse arrives before Ul12 reaches count 12 or
2) Ul12 reaches count 12.
If a second transition pulse arrives before count 12, the
bottom Ul13 stage is set and presents a "1" to the D input (pin 9)
of flip-flop UIOO. This is clocked by the Q output on pin 2 of Ul13
as a low to pin 12 of UIOO.
If a transit'ion pulse does not arrive before count 12, the
bottom Ul13 stage outputs a n¢" to input pin 9 of UI00. On count
12, the C and Doutputs of Ul12 go high to reset Ul13 by way of U98
at pin 4. As a result the UIOO clock goes high, as does pin 12 of
VIII-37
PROCESSOR TECI-mOLOGY CORPORATION
SECTION VIII
Sol TlffiORY OF OPERATION
UI00. The output on pin 12 of UIOO is inverted by Ul09 and applied
to the receive input (pin 20) of the UART.
The Q output on pin 1 of Ul13, which occurs at the actual bit
rate of the incoming data, is also used by the receive clock circuitry to reconstruct the receive clock from the data signal.
Received data undergoes serial-to-parallel conversion in the
UART and is placed on the ROl-8 data outputs of the UART when ROD
(pin 4 of the UART) is Imv (PORT IN FB active) and onto INT¢-7.
Four status outputs from the UART can also be enabled when
SFD (pin 16) is low. These four bits are FE (framing grror), OE
(overrun~rror), DR (data ready) and TBRE (transmitter buffer register empty).
8.6
KE'YBOARD
8.6.1
Block Diagram Analysis
A simplified block diagram of the keyboard is provided on
Page X-2l in Section X.
The Clock Oscillator produces the basic timing signals for
the keyboard, and they are distributed as indicated.
At the heart of the keyboard is a Key Svlitch Capacitive
Matrix \"hich can be vie\·ved as a 16 x 16 X-Y matrix, with X being the
column and Y the row. Conceptually, a key depression increases the capacitance between the X and Y coordinates that uniquely define that
key.
The Column Scanner supplies a pulse train to the X lines in
the matrix, with only one line being pulsed at any given point in
time. When a key is depressed to increase the capacitance between the
Column Scanner output and a Row Scanner input, the X-Y coordinates
for that key are detected to provide an input to the Sense Circuit.
The Sense Circuit in turn generates an input to the Sequence
Detector \vhen a key closure occurs. This detector basically detects
key closures and count cycles of the Row Scanner to discriminate
against false key signals and insure that valid closures are serviced
in order.
In the absence of key closures, the Sequence Detector feeds
PKD to the Sense Circuit to increase its threshold. This action
serves to increase the circuit's noise immunity. On valid key closures, the PKD input is such as to decrease the Sense Circuit's
threshold. When valid key closures exist, the Sequence Detector
strobes data into the Output Latch. The low order four bits to this
latch are supplied by the Row Scanner~ the high order four bits are
REV A
VIII-38
PROCESSOR TECHNOLOGY CORPORATION
SECTION VIII
Sol THEORY OF OPERATION
supplied by the Encoding ROM, with the data being determined by inputs from the Column Scanner and Function Latch Decoder. This
strobe (Data Out) also enables the Strobe Generator to outputs~T~R~O~B~E~,
a 6 usec pulse that signals the Sol CPU that the Keyboard is ready to
send data.
Eight bits of keyboard data (ILAG
0191
ORA
A
JNZ
ESCS
IF NON ZERO GO PROCESS THE "REST OF" THF. SEOUF:NCE
0192
0193 •
0194 •
A,B
SAVE IN B... STRIP PARITY BEFORE SCREEN!
0195 CHPCK MOV
ANI
CLR PARITY TO LOCATE IN TBL
0196
7FH
HOV
B,A
KEEP IT WIOUT PARITY IN R TOO
0197
JZ
GOBK
DO A QUICK EXIT IF A NULL
0198
LXI
H, TBL POINT TO SPECIAL CHARACTER TARLE
0199
CALL
0200
TSRCH GO PROCESS
0201 •
0202 GOBACK CALL
VDADD "GET SCREEN ADDRESS
0203
MOV
A,M
"GET PRESENT CURSOR CHARACTER
0204
ORI
80H
MOV
M,A
CURSOR IS BACK ON
0205
0206
LHLD
SPEED-l GET DELAY SPEED
INR
L
MAKE "SURE IT IS NON-ZERO
0207
XRA
A
DELAY WILL END WHEN H=O
0208
0209 TIMER DCX
H
TIMER DELAYS HE~E
CMP
0210
H
DONE WITH DELAY YET
••
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C079
C07C
C07D
C07E
C07F
C2 77 co
Cl
01
El
C9
COBO 23
COBl 23
COB2
COB3
C084
C087
COBB
C089
c08C
C08D
C090
C091
7E
B7
CA
B8
23
C2
E5
CD
E3
C3
94 co
80 CO
36 Cl
27 C2
C094 78
C095 FE 7F
C097 C8
C098
C098 CD lC Cl
C09B 70
C09C
C09F
COAl
COA4
COA7
COA9
3A
FE
DA
3A
FE
C2
08
3F
Cl
09
OF
Cl
C8
COAC
COAD
COBO
COBl
COB4
AF
32 OB C8
4F
CD 23 Cl
AF
CO
CB
CO
PROGRAM DEVELOPMENT SYSTEM
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
0211
JNZ
TIMER KEEP DELAYING
POP
0212 GOBK
B
0213
POP
D
RESTORE REGISTERS
0214
POP
H
0215
RET
EXIT FROM VDMOT
0216 •
0217 NEXT
INX
H
H
0218
INX
0219 •
0220 •
0221·
THIS ROUTINE SEARCHES THROUGH A SINGLE CHARACTER
0222 • TABLE FOR A MATCH TO THE CHARACTER IN "B". IF FOUND
0223 • A DISPATCH IS MADE TO THE ADDRESS FOLLOWING THE MATCHED
0224 • CHARACTER. IF NOT FOUND THE CHARACTER IS DISPLAYED ON
0225 • THE MONITOP..
0226 •
0227 TSRCH MOV
A,M
GET CHR FROM TABLE
0228
ORA
A
0229
JZ
CHAR
ZERO IS THE LAST
0230
CMP
B
TEST THE CHR
0231
INX
POINT FORWARD
H
0232
JNZ
NEXT
FOUND ONE ... SAVE ADDRESS
0233
PUSH
H
0234
CALL
CREM
REMOVE CURSOR
0235
XTHL
GET DISPATCH ADDRESS TO HL
0236
JMP
DISPT DISPATCH NOW
0237 •
PUT CHARACTER TO SCREEN
0238 •
0239 •
0240 CHAR
MOV
A,B
GET CHARACTER
0241
CPI
7FH
IS IT A DEL?
0242
RZ
GO BACK IF SO
0243 •
0244 •
0245 •
0246 OCHAR EQU
$
ACTUALLY PUT CHAR TO SCREEN NOW
0247
CALL
VDADD GET SCREEN ADDRESS
0248
MOV
M,B
PUT CHR ON SCREEN
0249 •
0250
LDA
NCHAR GET CHARACTER POSITION
CPI
0251
END OF LINE?
63
JC
0252
OK
LOA
LINE
0253
0254
CPI
END OF SCREEN?
15
JNZ
0255
OK
0256 •
0257·
END OF SCREEN •.. ROLL UP ONE LINE
0258 •
0259 SCROLL XRA
A
0260
STA
NCHAR BACK TO FIRST CHAR POSITION
0261 SROL
!!OV
C,A
0262
CALL
VDAD
CALCULATE LINE TO BE BLANKED
0263
XRA
A
••
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
COB5
COBB
COBB
COBC
COBE
CD
3A
3C
E6
C3
COCl
coc4
COC5
COC7
COCA
3A 08
3C
E6 3F
32 08
CO
COCB
3A 09
3C
E6 OF
32 09
C9
COCB
COCE
COCF
CODl
COD4
FA CO
OA C8
OF
EE CO
C8
C8
C8
C8
COD5 21 OO·CC
CODB 36 AO
CODA 23
CODB
CODB 36 20
CODD 23
CODE 7C
CODF FE DO
COEl DA DB CO
COE4 37
COES
COE7
COEA
COED
3E 00
32 09 C8
32 oB C8
DO
COEE 03 FE
COFO 32 OA C8
COF3 C9
COF4
COn
COFA
COFC
COFD
COFF
Cl00
Cl0l
CD
3A
FE
DO
36
23
3C
C3
lC Cl
08 c8
40
20
FA CO
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P. O. BOX 5260
SAN MATEO, CA 94402
..
PAGE
3
0264
CALL
CLINl CLEAR IT
0265
LOA
BOT
0266
INR
A
0267
ANI
OFH
0268
JMP
ERAS3
0269 •
0270·
INCREMENT LINE COUNTER IF NECESSARY
0271 •
0272 OK
LOA
NCHAR GET CHR POSITION
0273
INR
A
0274
ANI
MOD 64 AND WRAP
3FH
0275
STA
NCHAR
0276
RNZ
DIDN'T HIT END OF LINE, OK
0277 PDOWN EQU
CURSOR DOWN ONE LINE HERE
$
0278
LOA
LINE
GET THE LINE COUNT
INR
0279
A
0280 CURSC ANI
OFH
MOD 15 INCREMENT
0281 CUR
STA
LINE
STORE THE NEW
0282
RET
0283 •
ERASE SCREEN
0284 •
0285 •
0286 PERSE LXI
H,VDMEM POINT TO SCREEN
0287
MVI
M,80H+'
THIS IS THE CURSOR
0288 •
0289
INX
H
BUMP 1ST
0290 ERASl EQU
$
LOOPS HERE TO ERASE SCREEN
0291
MVI
M,
BLANK IT OUT
0292
INX
H
NEXT
MOV
0293
A,H
SEE IF END OF SCREEN YET
0294
CPI
ODOH
?
0295
JC
ERASl NO--KEEP BLANKING
0296
STC
CARRY WILL SAY COMPLETE ERASE
0297 •
0298 PHOME MVI
A,O
RESET CURSOR--CARRY=ERASE, ELSE HOME
0299
STA
LINE
ZERO LINE
0300
STA
NCHAR LEFT SIDE OF SCREEN
0301
RNC
IF NO CARRY, WE ARE DONE WITH HOME
0302 •
DSTAT RESET SCROLL PARAMETERS
0303 ERAS3 OUT
0304
STA
BOT
BEGINNING OF TEXT OFFSET
0305
RET
0306 •
0307 •
VDADD GET CURRENT SCREEN ADDRESS
0308 CLINE CALL
0309
LOA
NCHAR CURRENT CURSOR POSITION
64
0310 CLINl CPI
NO MORE THAN 63
0311
RNC
ALL DONE
M,
'
0312
MVI
ALL SPACED OUT
INX
H
0313
0314
INR
A
JMP
CLINl LOOP TO END OF LINE
0315
0316 •
••
SOLOS(TM)
77-03-27
COPYRIGHT (C) T977
CT04 3A 09 C8
CT07 3D
CT08 C3 CF co
CTOB 3A 08 C8
CTOE 3D
CTOF
CTOF E6 3F
CTTT 32 08 C8
CTT4 C9
CTT5 3A 08 C8
cn8 3C
CTT9 C3 OF CT
CTTC
CTTF
CT20
CT23
CT24
CT27
CT28
CT29
C12A
C12B
CT2D
C12F
C130
C131
C133
3A 08 C8
~F
3A
6F
3A
85
OF
OF
6F
E6
C6
67
7D
E6
8T
C 134 6F
C135 C9
09 C8
OA C8
03
CC
co
C136 CD lC Cl
CT39 7E
C13A E6 7F
PROGRAM DEVELOPMENT SYSTEM
..
..
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94~02
0317 •
0318 • ROUTINE TO MOVE THE CURSOR UP ONE LtNE
0319 •
LINE
GET LINE COUNT
0320 PUP
LDA
DCR
A
0321
JMP
CURSC MERGE TO HANDLE CURSOR
0322
0323 •
0324. MOVE CURSOR LEFT ONE POSITION
0325 •
NCHAR
0326 PLEFT LDA
DCR
A
0327
EQU
CURSOR ON SAME LINE
$
0328 PCUR
LET CURSOR WRAP
ANI
0329
3FH
NCHAR UPDATED CURSOR
STA
0330
RET
0331
0332 •
CURSOR RIGHT ONE POSITION
0333 •
0334 •
NCHAR
LDA
0335 PRIT
INR
A
0336
JMP
PCUR
0337
0338 •
0339.
ROUTINE TO CALCULATE SCREEN ADDRESS
0340 •
ENTRY AT:
RETURNS:
0341
0342
VDADD
CURRENT
SCREEN ADDRESS
0343 •
ADDRESS OF CURRENT LINE, CHAR 'C'
VDAD2
0344 •
LINE
'A',
CHARACTER POSITION 'C'
VDAD
0345 •
0346 •
NCHAR GET CHARACTER POSITION
0347 VDADD LDA
'C' KEEPS IT
MOV
C,A
0348
0349 VDAD2 LDA
LINE
LINE POSITION
MOV
L,A
INTO 'L'
0350 VDAD
LDA
BOT
GET TEXT OFFSET
0351
ADD IT TO THE LINE POSITION
ADD
L
0352
TIMES TWO
RRC
0353
RRC
MAKES FOUR
0354
MOV
L,A
L HAS IT
0355
MOD THREE FOR LATER
ANI
0356
3
ADI
RETURN A'BSOLUTE SCREEN ADDRESS
0443 •
MOV
0444 ARE'!",
B,H
C,L'
0445
MOV
PRESENT SCREEN ADDRESS TO" BC i'OR RETURN
0446 •
0447 ARETI POP
H
RETURN ADDRESS
0448
POP
o
OLD B
0449
PUSH
B
0450
PUSH
H
0451
'XRA
A
0452 ARET2 STA
ESCf'L
0453
RET
0454 •
0455 •
RETURN PRESENT SCREEN PARAMETERS IN BC
0456 •
0457 •
H,NCHAR
0458 CURET LXI
0459
MOV
B,M
CHARACTER POSITION
H
"
0460
INX
0461
C, M'
'LINE' POSITION
MOV
0462
JMP
ARETI
0463 •
0464 •
START UP SYSTEM
0465 •
0466 •
CLEAR
SCREEN
AND THE FIRST 256 BYTES OF GLOBAL RAM
0467 •
0468 • THEN ENTER THE COMMAND MODE.
0469 •
0470 STRTA XRA
0471
MOV
C,A
0472
LXI
H,SYSRAM CLEAR THE FIRST PAGE
0473 •
0474 CLERA 'MOV
M,A
0475
INX
H
,
C1A6 21 08 C8
C1A9 46
C1AA23
C lAB 4E
CIAC C3 9D Cl
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
C1B6 OC
C1B7 C2 B4 Cl
CIBA
C1BD
CICO
C1Cl
C1C3
C1C6
31 FF
CD 05
AF
03 FA
3207
32 06
C1C9
CICC
C1CF
ClOO
C,lDl
C1D4
C1D7
CIDA
CIDB
CIDE
C1El
31
3A
F5
AF
32
CD
CD
Fl
32
CD
C3
C1E4
C1E7
CIEA
CIEC
ClEF
CIFO
C1F2
ClF5
C1F7
C1F8
CIFA
C1FD
CD
CA
E6
CA
47
FE
CA
FE
C8
FE
C2
06
CB
CO
C8
C8
FF CB
07 C8
07 C8
Fl C2
E4 Cl
07 C8
05 C2
C9 Cl
,
IF CO
E4 Cl
7F
CO Cl
00
F4 CO
OA
7F
FF Cl
5F
CIFF CD 19 CO
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY 'CORP.
P.O. BOX 5260
SAN MATEO., CA 94402
••
PAGE
5
0476
INR
C
JNZ
CLERA
0477
0478 •
LXI
SP,SYSTP SET UP THE STACK FOR CALL
0479
0480 .
CALL
PERSE
0481 COMNI XRA
A
0482
OUT
STAPT BE SURE TAPES ARE OFF
STA
OPORT
0483
0484
STA
IPORT
0485 •
0486 •
0487 •
COMMAND HODE
0488 •
0489 •
0490 •
THIS ROUTINE GETS AND PROCESSES COMMANDS
0491 •
0492 •
0493 COMND LXI
SP;SYSTP SET STACK POINTER
0494
LDA
OPORT GET PORT
PUSH
PSW
0495
0496
XRA
A
STA
OPORT FORCE SCREEN OPERATIONS
0497
0498
CALL
P,ROMPT PUT PROMPT ON SCREEN
CALL
0499
GCLIN GET COMMAND LINE
POP
0500
PSW
0501
STA
OPORT RESTORE DEFAULT PORT
CALL
0502
COPRC PROCESS THE LINE
JMP
COMND OVER AND OVER
0503
0504 •
0505 •
0506 •
0507 • ·THIS ROUTINE READS A COMMAND LINE FROM THE SYSTEM
0508 • KEYBOARD
0509 •
0510' CIR
TERMINATES THE SEOUENCE ERASING ALL CHARS TO THE
0511 •
RIGHT OF THE CURSOR
0512' LIF
TERMINATES THE SEQUENCE
0513' MODE RESTARTS THE COMMAND LINE.
0514 •
SINP
0515 OCLIN CALL
READ INPU,T DEVICE
0516
JZ
GCLIN
ANI
CLEAR PARITY BIT
0517
7FH
0518
JZ
COMNI THIS WAS A MODE (OR EVEN CTL-@l
MOV
B,A
0519
CPI
CR
CARRIAGE RETURN
0520
0521
JZ
CLINE YES--DONE WITH LINE
CPI
LINE FEED
0522
LF
RZ
YES--DONE WITH LINE, LEAVE AS IS
0523
CPI
0524
7FH
DELETE CHR?
JNZ
CONT
0525
HVI
0526
B,BACKS REPLACE IT
0527 •
CALL
SOUT
0528 CONT
••
PROGRAM DEVELOPMENT SYSTEM
SOLOS(TM)
77-03-27
COPYRtGHT.(C) 1977
C202 C3 E4 C1
C205
C208
C20A
C20D
C20E
C211
C212
C215
C218
CD
OE
CD
EB
21
ES
CD
CA
EB
36 C1
01
20 C1
00 CO
2E C3
80 c4
C219 11 4AC2
C21C CD 31 C2
C21F CC 2E C2
C222
C222 CA 81 C4
C225 13
C226 EB
C227
7E
23
66
6F
C22B
C22B E3
C22C 1D
C22D C9
C227
C228
C229
C22A
C22E 11 3C C8
C231
C232
C233
C234
C235
C236
C237
1A
87
C8
E5
BE
13
C2 43 C2
..
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
0529
0530
0531
0532
0533
0534
0535
0536
0537
0538
0539
0540
0541
0542
0543
0544
0545
0546
0547
0548
0549
0550
0551
0552
0553
0554
0555
0556
0557
0558
0559
0560
0561
0562
0563
0564
0565
0566
0567
0568
0569
0570
0571
0572
0573
0574
0575
0576
0577
0578
0579
0580
0581
JMP
•
•
•
•
COPRC
•
DIS PO
GCLIN
FIND AND PROCESS COMMAND
CREM
C,1
VDAD2
REMOVE THE CURSOR
SET FOR CHARACTER POSITION
GET SCREEN ADDRESS
CALL
MVI
CALL
XCHG
LXI
PUSH
CALL
JZ
XCHG
H,START MAKE SURE HL PT TO SOLOS START
H
SAVE IT FOR LATER DISPT
SCHR
SCAN PAST BLANKS
ERR1
NO COMMAND?
HL HAS FIRST CHR
LXI
CALL
CZ
EQU
JZ
INX
XCHG
D,COMTAB POINT TO COMMAND TABLE
FDCOM SEE IF IN PRIMARY COMMAND TABL~
FDCOU IF NOT, TRY CUSTOM TABLE NEXT
$
HERE TO SEE IF ERROR OR DISP
ERR2
NOT VALID, ERROR
o
BUMP TO PTR OF RTN
HL PT TO RTN ADDR
•
•
• THIS IS THE DISPATCH ROUTINE.
• HL PT TO RTN ADDRESS, HL WILL BE RESTORED FM STACK
• SO THAT HL ARE RESTORED BEFORE DISPATCH.
•
OFF TO A ROUTINE
DISPT EQU
$
MOV
A,M
LO ADDR
INX
H
MOV
H,M
HI ADDR
HL NOW COMPLETE
L,A
MOV
HERE TO GO OFF TO HL
DISP1 EQU
$
XCHG HL W/HL ON STACk
XTHL
MOV
A,L
ALSO COPY HERE FOR SETS
RET
AND GO OFF TO THE RTN
•
•
THIS ROUTINE SEARCHES THROUGH A TABLE, POINTED TO
•
• BY 'DE', FOR A DOUBLE CHARACTER MATCH OF THE 'HL'
• MEMORY CONTENT. IF NO MATCH IS FOUND THE SCAN ENDS
• WITH HL POINTING TO ORIGINAL VALUE AND ZERO FLAG SET.
•
D,CUTAB HERE TO SCAN CUSTOM TBL ONLY
FDCOU LXI
•
FDCOM LOU
D
TEST FOR TABLE END
A
ORA
RZ
NOT FOUND .• COMMAND ERROR
SAVE START OF SCAN ADDRESS
PUSH
H
TEST FIRST CHR
CMP
M
INX
D
NCOM
JNZ
••
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C23A
C23B
C23C
C23D
23
1A
BE
C2 43 C2
C240 E1
C241 B7
C242 C9
C243
C244
C245
C246
C247
13
13
13
E1
C3 31 C2
C24A
C24C
C24E
C250
C252
c254
C256
C258
C25A
C25C
C25E
C260
c262
C264
C266
C268
C26A
C26C
C26E
C270
C272
54
67
44
BF
45
23
45
5E
47
A7
53
E6
58
A6
43
2B
53
7A
43
BD
00
45
C3
55
C3
4E
C4
58
C4
45
C4
41
C4
45
C4
41
C5
45
C5
55
C5
C273 OB
C274 D5 CO
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
••
PAGE
0582 •
0583
INX
H
0584
LDAX
D
CMP
0585
NOW SECOND CHARACTER
M
0586
JNZ
NCOM
GOODNESS
0587 •
POP
0588
H
RESTORE ORIGINAL SCAN ADDR
ORA
0589
A
SET NON-ZERO FLAG SAYING FOUND
RET
0590
WITH NON-ZERO SET
0591 •
0592 •
0593 NCOM
INX
D
GO TO NEXT ENTRY
INX
0594
D
INX
0595
D
POP
0596
GET BACK ORIGINAL ADDRESS
H
JMP
FDCOM CONTINUE SEARCH
0597
0598 •
0599 •
COMMAND TABLE
0600 •
0601 •
0602. THIS TABLE DESCRIBES THE VALID COMMANDS FOR SOLOS
0603 •
'TE'
0604 COMTAB ASC
TERMINAL MODE
0605
DW
TERM
'DU'
0606
ASC
DUMP
0607
DW
DUMP
'EN'
0608
ASC
ENTR
0609
OW
ENTER
'EX'
0610
ASC
EXEC
0611
DW
EXEC
'GE'
0612
ASC
GET A FILE
0613
DW
TLOAD
'SA'
0614
ASC
SAVE A FILE
0615
OW
TSAVE
'XE'
0616
Ase
XEQ (EXECUTE) A FILE
0617
DW
TXEQ
'CA'
0618
ASC
CATALOG OF FILES
0619
DW
TLIST
'SE'
0620
ASC
SET COMMAND
0621
DW
SET
'CU'
0622
ASC
CUSTOM COMMAND
0623
DW
CUSET
0624
DB
END OF TABLE MARK
o
0625 •
0626 •
DISPLAY DRIVER COMMAND TABLE
0627 •
0628 •
THIS
TABLE
DEFINES THE CHARACTERS FOR SPECIAL
0629 •
0630 • PROCESSING. IF THE CHARACTER IS NOT IN THE TABLE IT
0631 • GOES TO THE SCREEN.
0632 •
0633 TBL
DB
CLEAR-80H SCREEN
0634
DW
PERSE
I
••
Cl
CO
Cl
Cl
CO
Cl
Cl
Cl
Cl
C292 54 CO
C294 ~A CO
C296 E6 C2
C298 D2 C2
C29A
C29C
C29E
C2AO
C2A2
C2A4
C2A6
C2A8
C2AA
C2AC
C2AE
C2BO
C2B2
C2B4
C2B6
C2B8
C2BA
C2BC
2E
42
DD
CB
54
8E
53
99
49
9D
4F
A1
4E
B5
43
A5
43
A9
CO
CO
C2
C2
~1
C5
3D
C5
3D
C5
3D
C5
3D
C5
49
C5
4F
C5
DB
DW
DB
DW
DB
DW
DB
DW
DB
DW
DB
DW
DB
DW
DB
DW
DB
DW
DB
0635
0636
0637
0638
0639
06~0
0641
0642
06~3
06~~
06~5
06~6
0647
0648
0649
0650
0651
0652
0653
0654
0655
0656
0657
0658
0659
0660
0661
0662
0663
0664
0665
0666
0667
0668
0669
0670
0671
0672
0673
067~
0675
0676
0677
0678
0679
0680
0681
0682
0683
0684
0685
0686
0687
•
•
•
•
OTAB
•
•
•
•
ITAB
•
•
•
•
SETAB
UP-80H CURSOR
PUP
DOWN-80H
PDOWN
LEFT-80H
PLEFT
RIGHT-80H
PRIT
HOME-80H
PHOME
CR
CARRIAGE RETURN,
PCR
LF
LINE FEED
PLF
BACKS BACK SPACE
PBACK
ESC
ESCAPE KEY
PESC
0
END OF TABLE
OUTPUT DEVICE TABLE
DW
DW
DW
DW
VDMOT
SDROT
PROUT
ERROT
••
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 9~~02
SOLOS(TMl
77-03-27
COPYRIGHT (Cl 1977
C276 17
C277 04
C279 lA
C27A CB
C27C 01
C27D OB
C27F 13
C280 15
C282 OE
C283 E5
C285 OD
C286 ~7
C288 OA
C289 ~D
C28B.5F
c28c 3E
C28E lB
C28F 59
C291 00
PROGRAM DEVELOPMENT SYSTEM
C2BE 58 ~5
C2CO Bl C5
C2C2 54 59
C2C~ AD C5
C2C6 ~3 52
C2C8 B9 C5
C2CA 00
C2CB E5
C2CC 2A 00 C8
C2CF C3 D6 C2
C2D2
C2D3
C2D6
C2D7
C2D8
C2DB
C2DC
E5
2A 02 C8
7D
CA CO Cl
E3
C9
C2DD
C2DF
C2EO
C2E2
C2E3
C2E5
DB FA
2F
E6 02
C8
DB FD
C9
C2E6
C2E8
C2EA
C2ED
C2EE
C2FO
DB
E6
C2
78
D3
C9
B~
VDM DRIVER
SERIAL OUTPUT
PARALLEL OUTPUT
ERROR OR USER DRIVER HANDLER
KSTAT KEYBOARD INPUT
SSTAT SERIAL INPUT
PASTAT PARALLEL INPUT
ERRIT ERROR OR USER DRIVER HANDLER
SECONDARY COMMAND TABLE FOR SET COMMAND
ASC
DW
ASC
DW
ASC
DW
ASC
DW
ASC
DW
ASC
DW
ASC
DW
'TA'
TASPD
'S= '
DISPD
'1= •
SETIN
'0= '
SETOT
'N= '
SETNU
'CI'
SETCI
'CO'
SETCO
SET TAPE SPEED
SET DISPLAY SPEED
SET INPUT PORT
SET OUTPUT PORT
FA
04
E6 C2
FD
NULLS
SET CUSTOM DRIVER ADDRESS
SET CUSTOM OUTPUT DRIVER ADDRESS
C2Fl CD F9 C2
C2F4 06 3E
..
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 9~~02
SOLOS(TMl
77-03-27
COPYRIGHT (Cl 1977
INPUT DEVICE TABLE
DW
DW
DW
DW
PROGRAM DEVELOPMENT SYSTEM
0688
0689
0690
0691
0692
0693
ASC
DW
ASC
DW
ASC
DW
DB
069~
0695
0696
0697
0698
0699
0700
0701
0702
0703
0704
0705
0706
0707
0708
0709
0710
9999
0711
0712
0713
0714
0715
0716
0717
0718
0719
0720
0721
0722
0723
0724
077.5
0726
0727
0728
0729
0730
0731
0732
0733
073~
0735
0736
0737
0738
0739
'XE'
SETXQ
'TY'
SETTY
'CR'
SETCR
0
PAGE
7
SET HEADER XEQ ADDRESS
SET HEADER TYPE
SET CRC TO ALLOW IGNORING OF CRC ERRORS
END OF TABLE MARK
•
SOLOS PORT ERROR HANDLER
•
SAVE HL ONCE AGAIN
ERRIT PUSH
H
LHLD
UIPRT GET USER INPUT PORT ADDRESS
JMP
ERROl AND GO PROCESS
•
ERROT PUSH
H
LHLD
UOPRT GET USER OUTPUT PORT ADDRESS
TEST HL FOR ZERO
ERROl MOV
A,L
, ORA
H
JZ
COMNl IF ZERO RETURN TO COMMAND MODE
ADDRESS TO STACK ..• OLD HL TO HL
XTHL
GO TO THE DRIVER
RET
• -'2 OF 3 ......
SOLOS2/1
COPY
•
THIS ROUTINE IS THE PARALLEL DEVICE HANDLER
•
• NO PROVISION IS MADE FOR CONTROLLING THE PORT
• CONTROL BIT.
•
•
PARALLEL INPUT DRIVER
•
•
PASTAT IN
STAPT
INVERT STATUS FLAGS
CMA
TEST BIT
ANI
PDR
WITH FLAG SET
RZ
IN
PDATA GET DATA
RET
•
PARALLEL OUTPUT HANDLER
•
•
STAPT GET STATUS
PROUT IN
TEST IF DEVICE IS READY
ANI
PXDR
PROUT LOOP UNTIL SO
JNZ
MOV
A,B
OUT
PDATA
RET
•
•
OUTPUT A CRLF FOLLOWED BY A PROMPT
•
•
CRLF
PROMPT CALL
B, ')' THE PROMPT
MVI
••
SOLOS(TM)
11-03-21
COPYRIGHT (C) 1911
C2F6 C3 19 co
C2F9
C2FB
C2FE
C300
06
CD
06
CD
OA
19 CO
OD
19 co
C303
C306
C301
C308
C309
C30A
C30D
3A 10 C8
4F
OD
F8
AF
CD lF C4
C3 01 C3
C310
C313
C315
C316
C319
C31A
CD lB C3
3E 01
C8
CD 40 C3
1D
C9
C31B
C31D
C31E
C320
C323
C324
C326
C329
C32A
C32D
OE
lA
FE
CA
13
FE
CA
OD
C2
C9
C32E
C330
C331
C333
C334
c335
C336
OE OA
lA
FE 20
CO
13
OD
C8
OC
20
2E C3
3D
2E c3
lD C3
PROGRAM DEVELOPMENT SYSTEM
..
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
PUT IT ON THE SCREEN
JMP
SOUT
0140
0141 •
0142 •
B,LF
LINE FEED
0143 CRLF
MVI
CALL
SOUT
0144
B,CR
CARRIAGE RETURN
MVI
0145
CALL
SOUT
0146
0141 • NOW OUTPUT THE NULLS
NUCNT GET DESIRED COUNT
0148
LDA
C,A
STORE IN C
MOV
0149
0150 NULOT DCR
C
RETURN W~EN PAST ZERO
RM
0151
GET A NULL
XRA
A
0152
CALL
OUTH
0153
JMP
NULOT
0154
0155 •
0156 •
SCAN OFF OPTIONAL PARAMETER. IF PRESENT RETURN WITH
0151 •
0158 • VALUE IN HL AND COPY OF "L" IN ~'A". IF NOT PRESENT
0159 • RETURN WITH A "1" IN "A" AND HL UNTOUCHED.
0160 •
0161 PSCAN CALL
SBLK
DEFAULT VALUE
0162
MVI
A,l
IF NONE
0163
RZ
.
0164
CALL
SHEX
CONVERT VALUE
GET LOWER HALF
0165
MOV
A,L
0166
RET
0161 •
0168 •
0169. SCAN OVER UP TO 12 CHARACTERS LOOKING ~OR A RLAN~
0110 •
MAXIMUM COMMAND STRING
MVI
C,12
0111 SBLK
0112 SBLKl LDAX
D
CPI
BLANK
0113
GOT A BLANK NOW SCAN PAST IT
JZ
SCHR
0114
INX
D
0115
ALSO ALLOW AN EQUAL TO STOP US
CPI
0116
JZ
SCHR
IF SO, PTR AT CHAR FOLLOWING
0117
NO MORE THAN TWELVE
DCR
C
0118
JNZ
SBLKl
0119
GO BACK WITH ZERO FLAG SET
RET
0180
0181 •
0182 •.
SCAN PAST UP TO 10 BLANK POSITIONS LOOKING FOR
0183 •
0184 • A NON BLANK CHARACTER.
0185 •
SCAN TO FIRST NON BLANK CHR WITHIN 10
MVI
C,10
0186 SCHR
GET NEXT CHARACTER
0181 SCHRl LDAX
D
0188
CPI
SPACE
WE'RE PAST THEM
RNZ
0189
NEXT SCAN ADDRESS
INX
D
0190
DCR
C
0191
RZ
COMMAND ERROR
0192
..
SOLOS(TM)
11-03-21
COPYRIGHT (C) 1911
C331 C3 30 C3
C33A CD lB C3
C33D CA 80 .C4
C340
C343
C344
C346
C341
C349
C34A
C34C
21
lA
FE
C8
FE
C8
FE
C8
00 00
C34D
C34E
C34F
C350
C351
C354
C351
C358
C359
C35A
29
29
29
29
CD 5D C3
D2 80 C4
85
6F
13
C3 43 C3
C35D
C35F
C361
C362
C364
C366
D6
FE
D8
D6
FE
C9
20
2F
3A
30
OA
01
10
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
••
PAGE
8
0193
JMf'
SCHRl KEEP LOOPING
0194 •
0195 •
THIS ROUTINE SCANS OVER CHARACTERS, PAST BLANKS AND
0796 •
0797 • CONVERTS THE FOLLOWING VALUE TO HEX. ERRORS RETURN TO
THE
ERROR HANDLER.
0798 •
0799 •
0800 SCONV CALL
SBLK
FIND IF VALUE IS PRESENT
0801
JZ
ERRl
ABORT TO ERROR IF NONE
0802 •
0803 •
0804· THIS ROUTINE CONVERTS ASCII DIGITS INTO BINARY FOLLOWING
0805 • A STANDARD HEX CONVERSION. THE SCAN STOPS WHEN AN ASCII
0806 • SPACE IS ENCOUNTERED. PARAMETER ERRORS REPLACE THE ERROR
0807 • CHARACTER ON THE SCREEN WITH A QUESTION MARK.
0808 •
0809 SHEX
LXI
H,O
CLEAR H & L
0810 SHEl
LDAX
D
GET CHARACTER
0811
CPI
20H
IS IT A SPACE?
RZ
0812
IF SO
'/'
CPI
SLASH IS ALSO LEGAL
0813
0814
RZ
CPI
0815
EVEN THE COLON IS ALLOWED
0816
RZ
0817 •
0818 HCONV DAD
H
MAKE ROOM FOR THE NEW ONE
0819
DAD
H
0820
DAD
H
0821
DAD
H
0822
CALL
HCOVl DO THE CONVERSION
0823
JNC
ERRl
NOT VALID HEXIDECIMAL VALUE
0824
ADD
L
0825
MOV
MOVE IT IN
L,A
0826
INX
D
BUMP THE POINTER
0827
JMP
SHEl
0828 •
0829 HCOVl SUI
48
REMOVE ASCII BIAS
CPI
0830
10
0831
RC
IF LESS THAN 9
IT'S A LETTER
SUI
0832
7
CPI
10H
0833
RET
WITH TEST IN HAND
0834
0835 •
0836 •
TERM COMMAND
0837 •
0838 •
THIS ROUTINE GETS CHARACTERS FROM THE SYSTEM KEYBOARD
0839 •
0840 • AND OUTPUTS THEM TO THE SELECTED OUTPUT PORT. IT IS
0841 • INTENDED TO CONFIGURE THE Sol AS A STANDARD VIDEO
0842 • TERMINAL. COMMAND KEYS ARE NOT OUTPUT TO THE OUTPUT
0843 • PORT BUT ARE INTERPRETED AS DIRECT Sol COMMANDS.
0844 • THE MODE COMMAND, RECEIVED BY THE KEYBOARD, PUTS THE
0845 • Sol IN THE COMMAND MODE.
/
(
PROGRAM DEVELOPMENT SYSTEM
II
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO,. CA 94402
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C367
C36A
C36D
C370
C373
C376
C379
C37A
C37C
C37F
C382
C38'5
C388
C38B
C38E
C391
C393
C396
C397
C399
C39C
C39E
C3A 1
C3A3
C3A6
C3A9
C3AA
C3AD
C3AE
C3BO
C3B3
C3B5
C3B8
CD
32
CD
32
CD
CA
47
FE
CA
DA
CD
C3
10
06
10
07
C3
C8
C3
C8
2E CO
6B C3
80
CO
88
54
8B
CD 19
CD IF
CA 73
E6 7F
CA 73
47
FE lB
02 B9
FE 00
CA B9
FE OA
CA B9
3A OC
B7
C2 B9
C5
06 lB
CD 54
06 07
CD 54
.Cl
C3B9
C3B9 CD 54
C3BC C3 73.
Cl
C3
CO
C3
CO
CO
C3
C3
C3
C3
C3
CB
C3
CO
CO
CO
C3
II
0846
0847
0848
0849
0850
0851
0852
0853
0854
0855
0856
0857
0858
0859
0860
0861
0862
0863
0864
0865
0866
0867
0868
0869
0870
0871
0872
0873
OB74
0875
0876
0877
0878
0879
0880
0881
0882
0883
0884
0885
0886
0887
0888
0889
0890
0891
0892
0893
0894
0895
0896
0897
0898
I
I
CALL
STA
CALL
STA
PSCAN
IPORT
PSCAN
OPORT
FIND IF INPUT PARAMETER IS PRESENT
SINP WILL USE THIS DRIVER (DEFAULT IS 1)
NOW FOR THE OUTPUT DRIVER
KSTAT
IS THERE ONE WAITING?
II' NOT
SAVE IT IN B
IS IT MODE
YES--RESET AND QUIT TERM
NON-.CURSOR KEY ---SEND TO TERM PORT
PROCESS IT
I
TERMI
CALL
JZ
MOV
CPI
JZ
JC
CALL
JMP
TIN
B,A
MODE
COMNI
TOUT
VDMOT
TIN
I
TOUT
TIN
TERM2
CALL
CALL
JZ
ANI
JZ
MOV
CPI
JNC
CPI
JZ
CPI
JZ
LOA
ORA
JNZ
PUSH
MVI
CALL
MVI
CALL
POP
EQU
CALL
JMP
SOUT
SINP
TERMI
7FH
TERMI
B,A
lBH
TERM2
CR
TERM2
LF
TERM2
ESCFL
A
TERM2
B
B,ESC
VDMOT
B,7
VDMOT
B
$
VDMOT
TERMI
OUTPUT IT TO THE SERIAL PORT
GET INPUT STATUS
LOOP II' NOT
NO HIGH BITS FROM HERE
A NULL IS IGNORED
IT"S OUTPUT FROM "B"
IS IT A CONTROL CHAR TO BE IGNORED
NO--TO VDM AS IS THEN
CR OR LF ARE SPECIAL CASES THOUGH
AND MUST BE PASSED STD MODE TO VDM DRIVER
A CTL CHAR---ARE WE W/IN AN ESC SEQUENCE?
IF YES, THEN OUTPUT CTL CHAR DIRECTLY TO VDM
WE SURE ARE, LET VDM DRIVER HANDLE IT
SAVE THE CHAR
CTL CHAR TO VDM VIA ESC SEQUENCE
SAY TO PUT OUT NEXT CHAR AS IS
ALMOST READY
RESTORE CHAR
ALL .READY TO OUTPUT THE CHAR
PUT IT ON THE SCREEN
LOOP OVER AND OVER
DUMP COMMAND
THIS ROUTINE DUMPS CHARACTERS FROM MEMORY TO THE
CURRENT OUTPUT DEVICE. ALL VALUES ARE DISPLAYED AS
ASCII HEX.
THE COMMAND FORM IS AS FOLLOWS:
DUmp
addrl
addr2
C3BF
C3C2
C3C3
C3C6
C3C7
CD 3A C3
E5
CD 10 C3
Dl
EB
C3C8
C3CB
C3CE
C3Dl
CD
CD
CD
OE
C3D3
C3D4
C3D5
C3D8
C3D9
C3DA
C3DB
C3DC
C3DF
C3EO
C3El
C3E2
C3E5
7E
C5
CD
70
93
7C
9A
02
Cl
23
OD
C2
C3
1'9 C2
E8 C3
06 C4
10
ED C3
C9 Cl
03 C3
C8 C3
C3E8 7C
C3E9 CD OB C4
C3EC 70
C3ED
C3FO
C3F3
C3F6
C3F8
C3FB
C3FD
C400
C403
C406
C408
C40B
C40C
C40D
C40E
CD
CD
CA
E6
CA
FE
C2
CD
CA
06
C3
4F
OF
OF
OF
OB
IF
06
7F
C9
20
06
IF
00
20
19
C4
CO
c4
Cl
C4
CO
C4
CO
II
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
I
TERM
PROGRAM DEVELOPMENT SYSTEM
II
0899
0900
0901
0902
0903
0904
0905
0906
0907
0908
0909
0910
0911
0912
0913
0914
0915
0916
0917
0918
0919
0920
0921
0922
0923
0924
0925
0926
0927
0928
0929
0930
0931
0932
0933
0934
0935
0936
0937
0938
0939
0940
0941
0942
0943
0944
0945
0946
0947
0948
0949
0950
0951
I
I
I
I
PAGE
9
THE VALUES FROM AODRI TO ADDR2 ARE THEN OUTPUT TO THE
OUTPUT DEVICE. IF ONLY ADDRI IS SPECIFIED THEN THE
VALUE AT THAT ADDRESS IS OUTPUT.
I
DUMP
•
DLOOP
CALL
PUSH
CALL
POP
XCHG
SCONV
PSCAN
SCAN TO FIRST ADDRESS AND CONVERT IT
SAVE THE VALUE
SEE IF SECOND WAS GIVEN
GET BACK START
HL HAS START, DE HAS END
CALL
CALL
CALL
MVI
CRLI'
ADOUT
BOUT
C,16
OUTPUT ADDRESS
ANOTHER SPACE TO KEEP IT PRETTY
VALUES PER LINE
H
o
I
DLPI
I
MOV
PUSH
CALL
MOV
SUB
MOV
SBB
JNC
POP
INX
OCR
JNZ
JMP
A,M
B
HBOUT
A,L
GET THE CHR
SAVE VALUE COUNT
SEND IT OUT WITH A RLANK
COMPARE DE & HL
E
A,H
o
COMND
B
ALL OONE
VALUES PER LINE
H
C
DLPI
OLOOP
BUMP THE LINE COUNT
NOT ZERO IF MORE FOR THIS LINE
00 A LFCR BEFORE THE NEXT
OUTPUT HL AS HEX 16 BIT VALUE
I
ADOUT
MOV
CALL
MOV
A,H
HEOUT
A,L
H FIRST
CALL
CALL
JZ
ANI
JZ
CPI
JNZ
CALL
JZ
MVI
JMP
HEOUT
SINp· . SEE IF A CHAR WAITING
BOUT
NO
7FH
CLR PARITY 1ST TKO
COM NO EITHER MODE OR CTL-@
IS IT A SPACE
BOUT
NO--IGN THE CHAR
SINP
IF SPACE, WAIT UNTIL ANY OTHER KEY HIT
WTLPI THIS ALLOWS LOOKING AT THE DISPLAY
SOUT
PUT IT OUT
MOV
RRC
RRC
RRC
C,A
GET THE CHARACTER
THEN "L" FOLLOWED BY A SPACE
I
HBOUT
WTLPI
BOUT
B, "
I
HEOUT
MOVE THE HIGH FOUR DOWN
..
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
CIiOF OF
CillO CD lli Cli
CII13 79
Cli14
C416
Cl118
Clll'
C41D
ClllF
C420
E6
C6
FE
Di
C6
117
C3
OF
30
3A
tr C4
07
19 CO
C423
Cli26
CII27
CII28
CD 3A C3
E5
AF
32 07 C8
Cli2B
C42E
Cli30
Cli33
C436
Cli38
Cli3B
CD
06
CD
CD
OE
CD
EB
F9
3A
FF
36
01
20
C2
Cl
Cl
Cl
CII3C OE 03
Cli3E CD 30 C3
Clilil CA 2B Cli
Cli44
C41i6
C449
CliljC
CII4E
C451
Cli52
Cli53
Cli54
Cli55
Cli56
FE
CA
CD
FE
CA
7D
El
77
23
E5
C3
2F
CO Cl
40 C3
3A
59 C4
3C C4
0952
0953
0951i
0955
0956
0957
0958
0959
0960
0961
0962
0963
0964
0965
0966
0967
0968
0969
0970
0971
0972
0973
0974
0975
0976
0977
0978
0979
0980
0981
0982
0983
0984
0985
0986
0987
0988
0989
0990
0991
0992
0993
0994
0995
0996
0997
0998
0999
1000
1001
1002
1003
1004
•
HEOUl
OUTH
..
••
RRC
CALL
MOV
HEOUl
A,C
PUT THEM OUT
THIS TIME THE LOW FOUR
ANI
ADI
CPI
JC
ADI
MOV
JMP
OFH
48
58
OUTH
7
B,A
SOUT
FOUR ON THE FLOOR
WE WOR~ WITH ASCII HERE
0-9?
YUPI
MA~ IT' A LETTER
OUTPUT IT FROM REGISTER 'B'
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
Cli59 E3
Cli5A 13
Cli5B C3 3C Cli
ENTR COMMAND
THIS ROUTINE GETS VALUES FROM THE ~EYBOARD AND ENTERS
THEM INTO MEMORY. THE INPUT VALUES ARE SCANNED FOLLOWING
A STANDARD 'GCLIN' INPUT SO ON SCREEN EDITING MAY TAKE
PLACE PRIOR TO THE LINE TERMINATOR. A BAC~ SLASH ','
ENDS THE ROUTINE AND RETURNS CONTROL TO THE COMMAND MODE.
A COLON ',' SETS THE PREVIOUS VALUE AS A NEW ADDRESS FOR
ENTER.
ENTER
•
ENLOP
•
•
ENLOl
•
•
CALL
PUSH
XRA
STA
SCONV
H
A
OPORT
CALL
MVI
CALL
CALL
MVI
CALL
XCHG
CRLF
B, '.'
.
CONT
CREM
C,l
VDAD2
MVI
CALL
JZ
C,3
SCHRl
ENLOP
CPI
JZ
CALL
CPI
JZ
MOV
POP
MOV
INX
PUSH
JMP
','
COMNl
SHE X
~
:'
ENL03
A,L
H
M,A
H
H
ENLOl
Cli5E
C461
C462
Cli65
CD 3A C3
E5
21 00 CO
C9
SCAN OVER CHARS AND. GET ADDRESS
SAVE ADDRESS
ENTER VALUES TO SCREEN BUFFER
GET LINE OF INPUT
REMOVE THE CURSOR
START SCAN
GET ADDRESS
..•• TO DE
NO MORE THAN THREE SPACES BETWEEN VALUES
SCAN TO NEXT VALUE
LAST ENTRY FOUND START NEW LINE
COMMAND TERMINATOR?
IF SO ••• RETURN TO STANDARD INPUT
CONVERT VALUE
ADDRESS TERMINATOR?
GO PROCESS IF SO
GET LOW PART AS CONVERTED
GET MEMORY ADDRESS
PUT IN THE VALUE
BACK GOES THE ADDRESS
CONTINUE THE SCAN
Cli66 21 lC C8
C469 CD lB C3
C46C 06 06
C46E
C46F
C471
C474
Cli76
C479
Cli7A
Cli7B
C47C
C47D
lA
FE
CA
FE
CA
77
13
23
05
C2
20
86 C4
2F
86 Cli
6E C4
C480 EB
C481 36 3F
C483 C3 CO Cl
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
••
PAGE
10
1005 ENL03 XTHL
PUT NEW ADDRESS ON STAC~
INX
D
1006
MOVE SCAN PAST TERMINATOR
JMP
1007
ENLOl
1008
1009
EXECUTE COMMAND
1010
1011
1012
THIS ROUTINE GETS THE FOLLOWING PARAMETER AND DOES A
1013
PROGRAM JUMP TO THE LOCATION GIVEN BY IT. IF PROPER
1014
STAC~ OPERATIONS ARE USED WITHIN THE EXTERNAL PROGRAM
1015
IT CAN DO A STANDARD 'RET'URN TO THE SOLOS COMMAND MODE,
1016
THE STARTING ADDRESS OF SOLOS IS PASSED TO THE PROGRAM
1017
IN REGISTER PAIR HL SO IT CAN ADJUST INTERNAL 'PARAMETERS
1018
FOR SOLOS OPERATION.
1019
1020
1021 EXEC
CALL
SCONV SCAN PAST BLAN~S AND GET PARAMETER
1022 EXECl PUSH
H
PUT GO ADDRESS ON STAC~
1023
LXI
H,START TELL THE PROGRAM WHERE WE CAME FROM
1024
RET
AND DISPATCH TO IT
1025 •
1026 •
1027 •
THIS ROUTINE GETS A NAME OF UP TO 5 CHARACTERS
1028 • FROM THE INPUT STRING. IF THE TERMINATOR IS A
SLASH
(') THEN THE CHARACTER FOLLOWING IS TA~EN
1029 •
1030 • AS THE CASSETTE UNIT SPECIFICATION.
1031 •
1032 •
1033 NAMES LXI
H,THEAD POINT TO INTERNAL HEADER
1034 NAME
CALL
SBLK
SCAN OVER TO FIRST CHRS
1035.
MVI
B,6
UP TO SIX ARE ACCEPTED
1036 •
D
1037 NAMEl LDU
GET CHARACTER
1038
CPI
NO UNIT DELIMITER
JZ
NFIL
1039
1040
CPI
UNIT DELIMITER
1041
JZ
NFIL
1042
MOV
M,A
1043
INX
D
BUMP THE SCAN POINTER
1044
H
INX
B
1045
DCR
1046
JNZ
NAMEl FALL THROUGH TO ERRl IF TOO MANY CHRS IN NAME
1047 •
1048 •
SOLOS ERROR HANDLER
1049 •
1050 •
1051 ERRl
XCHG
GET SCAN ADDRESS TO HL
M '?'
1052 ERR2
MVI
PUT QUESTION MARK ON SCREEN
1053
JMP
COMNl AND RETURN TO COMMAND MODE
1054 •
1055 •
1056. HERE WE HAVE SCANNED OFF THE NAME. ZERO FILL FOR
1057· NAMES LESS THAN FIVE CHARACTERS.
','
('
..
PROGRAM DEVELOPMENT SYSTEM
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C486
C488
C489
C48A
36 00
23
05
C2 86 C4
C48D
C48F
C491
C494
C495
C498
FE 2F
3E 01
C2 9A C4
C49A
C49C
C49E
C4A 1
C4A2
C4A5
1.3
CD 2E C3
D6 30
C49A
E6 01
3E 80
C2 A2 C4
IF
32 54 C8
C9
C4A6
C4A7
C4A8
C4A9
C4AC
C4AF
C4B2
3E
AF
F5
21
CD
21
CD
C4B5
C4B6
C4B9
C4BA
C4BB
C4BE
C4C 1
C4C2
C4C5
C4C6
C4C9
EB
21
7E
B7
C2
21
E5
CD
El
CD
DA
C4CC
C4CF
C4DO
C4Dl
C4D2
C4D5
C4D6
CD 50 C5
Fl
B7
C8
3A 22 C8
B7
FA 14 C5
2C
69
00
10
C8
C4
00
C3
2C C8
Cl C4
lC C8
48 C5
CB c6
14 C5
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
•
NFIL
•
•
DEFLT
STUNT
MVI
INX
DCR
JNZ
CPI
MVI
JNZ
INX
CALL
SUI
EQU
ANI
MVI
JNZ
RAR
STA
RET
M,O
PUT IN AT LEAST ONE ZERO
H
B
NFIL
LOOP UNTIL B IS ZERO
. I'
IS THERE A UNIT SPECIFICATION?
PRETEND NOT
A,l
DEFLT
D
SCHR
'0'
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C4D9
C4DC
C4DD
C4EO
C4E3
3A
B7
C2
2A
C3
21 C8
C4E6
C4E9
C4EC
C4ED
C4FO
C4Fl
C4F2
C4F5
CD
CD
E5
CD
E3
E5
CD
22
C4F8
C4F9
C4FA
C4FB
C4FC
C4FD
C4FE
C4FF
C500
C501
C502
C505
El
Dl
E5
7B
95
6F
7A
9C
67
23
22 23 C8
E5
14 C5
27 C8
61 C4
MOVE PAST THE TERMINATOR
GO GET UNIT SPEC
REMOVE ASCII BIAS
MOVE OVER TO INTERNAL REPRESENTATION
1
JUST BIT ZERO
A,TAPEI ASSUME TAPE ONE
STUNT IF NON-ZERO, ITS ONE
$
FNUMF
••
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
SET IT IN
•
•
•
THIS ROUTINE PROCESSES THE XEO AND GET COMMANDS
•
•
•
TXEQ
DB
3EH
THIS BEGINS "MVI A,OAFH"
TLOAD XRA
A
A=O MEANS TLOAD, ELSE TXEO
PUSH
PSW
SAVE FLAG FOR LATER
H,DHEAD PLACE DUMMY HEADER HERE
LXI
NAME
SET IN NAME AND UNIT
CALL
H,O
PRETEND NO SECOND VALUE
LXI
PSCAN GO GET THE ADDRESS (IF PRESENT)
CALL
•
PUT ADDRESS IN DE
TLOA2 XCHG
H,DHEAD PT TO DUMMY HEADER WI NAME TO LOAD
LXI
A,M
SEE IF A NAME WAS ENTERED
MOV
ORA
A
IS THERE A NAME?
TLOA3 YES--SEARCH FOR IT
JNZ
H,THEAD NO NAME, LOAD 1ST FILE
LXI
H
SAVE PTR TO NAME TO LOAD
TLOA3 PUSH
CALL
ALOAD GET UNIT AND SPEED
POP
H
RESTORE PTR TO HDR TO LOAD
CALL
RTAPE READ IN THE TAPE
JC
TAERR TAPE ERROR?
•
CALL
NAOUT PUT OUT THE HEADER PARAMETER~
POP
PSW
RESTORE FLAG FROM ORIGINAL ENTRY
ORA
A
AUTO XEO NOT WANTED
RZ
LDA
HTYPE CHECK TYPE
ORA
A
SET FLAGS
JM
TAERR TYPE IS NON XEO
66 C4
3A C3
3A C3
10 C3
25 C8
C506 CD 48 C5
C509 21 lC C8
C50C CD AF C7
C50F Dl
C510 El
C511 C3 90 C7
C514
C517
C519
C51C
C51F
C522
CD
16
21
CD
CD
C3
F9
06
25
6A
50
CO
C2
C5
C5
C5
Cl
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
••
PAGE
11
1111
LDA
THEAD+5 GET CHARACTER PAST NAME
1112
ORA
A
JNZ
TAERR THE BYTE MUST BE ZERO FOR AUTO XEQ
1113
1114
LHLD
XEQAD GET THE TAPE ADDRESS
JMP
EXEC! AND GO TO IT
1115
1116 •
1117
1118
GET -=
1119 •
THIS ROUTINE IS USED TO SAVE PROGRAMS AND DATA ON
1120 •
THE CASSETTE UNIT.
1121 •
1122 •
1123 •
1124 TSAVE CALL
NAMES GET NAME AND UNIT
1125
CALL
SCONV GET START ADDRESS
1126
PUSH
USE THE STACK AS A REGISTER
H
CALL
SCONV GET END ADDRESS
1127
XTHL
1128
PUT END ON STACK, GET BACK START
PUSH
1129
H
SAVE START ON TOP OF STACK
1130
CALL
PSCAN SEE IF OPTIONAL HEADER ADDRESS WAS GIVEN
1131
SHLD
LOADR PUT HEADER' ADDRESS IN PLACE
11'32 •
POP
H
1133
"FROM" ADDRESS TO HL
POP
1134
D
GET BACK "END" ADDRESS
PUSH
SAVE FROM AGAIN FOR LATER
1135
H
1136
MOV
A,E
NOW CALCULATE SIZE
1137
SUB
L
SIZE=END-START+l
1138
MOV
L,A
MOV
1139
A,D
1140
SBB
H
1141
MOV
H,A
1142
INX
H
SHLD
BLOCK STORE THE SIZE
1143
1144
PUSH
H
SAVE IT FOR THE READ ALSO
1145 •
1146
CALL
ALOAD GET UNIT AND SPEED
1147
LXI
H,THEAD POINT TO HEADER
1148
CALL
WHEAD AND WRITE IT OUT
NOW WRITE OUT THE DATA
1149 •
1150
POP
o
GET SIZE TO DE
1151
POP
H
GET BACK "FROM" ADDRESS
1152
JMP
WRLO! WRITE OUT THE DATA AND RETURN
1153 •
1154 •
1155'
OUTPUT ERROR AND HEADER
1156 •
1157 TAERR CALL
CRLF
1158
MVI
D,6
LXI
1159
H,ERRM POINT TO ERROR MESSAGE
1160
CALL
NLOOP OUTPUT ERROR
1161
CALL
NAOUT THEN THE HEADER
1162
JMP
COMN! AND BE SURE THE TAPE UNITS ARE OFF
1163 •
••
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P.O. BOX S260
SAN MATEO, CA 94402
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C525 _5 52 52
52 20
C52B CD 66 C~
C52E CD F9 C2
C531 CD _8 CS
C53_ 06 01
C536 CD EF C7
C539 CD 23 C7
C53C' DA co C1
C53F C2 39 C5
C5~2 CD 50 C5
C5~5 C3 39 CS
C~_8
~5_B
:5~E
C5~F
CS50
C552
C555
C558
c55B
C5SE
C561
C564
C567
C56A
C56B
C56C
C56F
C571
CS74
21 S~ C8
3A OD c8
B6
C9
16
21
CD
CD
2A
CD
2A
CD
C3
08
lB
6A
06
25
E8
23
E8
F9
~F
7E
B7
C2 71 C5
3E 20
CD IF C4
23
!ERROR
116~
ERRM
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
117S
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
119S
1196
1197
•
•
THIS ROUTINE READS HEADERS FROM THE TAPE AND OUTPUTS
•
THEM TO THE OUTPUT DEVICE. IT CONTINUES UNTIL THE
•
MODE KEY IS DEPRESSED.
•
•
NAMES SET UP UNIT IF GIVEN
TLIST CALL
CALL
CRLF
•
•
ALOAD
LLIST CALL
MVI
B,I
TURN ON THE TAPE
CALL
TON
•
RHEAD
LISTI CALL
COMNI TURN orF THE TAPE UNIT
JC
LISTI
JNZ
CALL
NAOUT OUTPUT THE HEADER
LISTI LOOP UNTIL MODE IS DEPRESSED
JMP
•
•
•
THIS ROUTINE GETS THE CASSETTE UNIT NUMBER AND
SPEED TO REGISTER "A" FOR THE TAPE CALLS
•
•
H,FNUMF POINT TO THE UNIT SPECIFICATION
ALOAD LXI
TSPD
GET THE TAPE SPEED
LDA
M
PUT THEM TOGETHER
ORA
AND GO BACK
RET
•
•
THIS ROUTINE OUTPUTS THE NAME AND PARAMETERS OF
•
THEAD TO THE OUTPUT DEVICE.
•
•
119B •
C8
C5
C4
C8
C3
C8
C3
C2
1199
1200
1201
1202
1203
1204
1205
1206
1207
120B
1209
1210
1211
1212
1213
1214
1215
NAOUT
•
•
NLOOP
CHRLI
ASC
..
••
MVI
LXI
CALL
CALL
LHLD
CALL
LHLD
CALL
JMP
D,8
H,THEAD-l POINT TO THE HEADER
NLOOP OUTPUT THE HEADER
BOUT
ANOTHER BLANK
LOADR NOW THE LOAD ADDRESS
ADOUT PUT IT OUT
BLOCK AND THE BLOCK SIZE
ADOUT
CRLF
DO THE CRLF AND RETURN
MOV
ORA
JNZ
MVI
CALL
INX
A,M
A
CHRLI
A, '
OUTH
H
GET CHARACTER
CS7A
C57D
C580
CS81
CS84
CS85
C588
C58B
C57A
CD lB
CA BO
OS
CD 3A
E3
11 A2
CD 31
C3 22
CS8E
CS8F
C592
CS94
C597
B7
CA 94 CS
3E 20
32 OD c8
C9
C3
C4
C3
C2
C2
C2
C598 78
C599 32 DB' C8
C59C C9
CS9D
C59D 32 06 C8
CSAO C9
IF IT ISN'T A ZERO
OUTPUT CHAR NOW
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
C5A5 22 00 c8
C5AB C9
DCR
JNZ
RET
PAGE
12
D
NLOOP
•
•
•
•
"SET" COMMAND
•
•
THIS ROUTINE GETS THE ASSOCIATED PARAMETER AND
•
DISPATCHES TO THE PROPER ROUTINE FOR SETTING
•
GLOBAL VALUES,
•
•
EQU
SET
THIS IS THE SET COMMAND
$
CALL
SBLK
LOOK FOR SET NAME
JZ
ERRI
MUST HAVE AT LEAST SOMETHING I I
PUSH
D
SAVE SCAN 'ADDRESS
CALL
SCONV CONVERT FOLLOWING VALUE
123~
XTHL
GET SCAN ADDRESS BACK •• SAVE VALUE ON STACK
1235
LXI
D,SETAB SECONDARY COMMAND TABLE
1236
CALL
FDCOM SEE IF IN TABLE
JMP
DISPO AND EITHER ERR OR OFF TO IT
1237
1238 •
1239 •
1240· THIS ROUTINE SETS THE TAPE SPEED
1241 •
1242 TASPD ORA
A
IS IT ZERO?
12~3
JZ
SETSP YES--THAT'S A VALID SPEED
1244
MVI
A,32
SET TO SLOW IF NON-ZERO
1245 SETSP STA
TSPD
SPEED IS STORED HERE
1246
RET
1247 •
1248 •
12119 STSPD MOV
A,B
ESCAPE COMES HERE TO SET SPEED
1250 DISPD STA
SPEED SET DISPLAY SPEED
1251
RET
1252 •
1253· SET INPUT DRIVER
1254 •
1255 SETIN EQU
$
1256
STA
IPORT
1257
RET
125B •
C5Al
C5Al 32 07 c8
C5A4 C9
..
SOFTWARE TECHNOLOGY CORP.
P,O. BOX 5260
SAN MATEO, CA 94~02
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C575 15
C576 C2 6A C5
C579 C9
PROGRAM DEVELOPMENT SYSTEM
1259· SET OUTPUT
1260 •
1261 SETOT EQU
1262
STA
1263
RET
1264 •
SET
USERS
1265 •
1266 •
1267 SETCI SHLD
1268
RET
DRIVER
$
OPORT
CUSTOM INPUT DRIVER ADDRESS
UIPRT
I"
••
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C5A9 22 02 C8
C5AC C9
C5AD 32 22 C6
C5BO C9
C5Bl 22 27 C8
C5B4 C9
C5B5 32 10 C8
C5B8 C9
C5B9
C5B9 32 11 C8
C5BC C9
C5BD
C5CO
C5C3
C5C6
C5C7
C5CA
C5CD
C5DO
C5Dl
C5D3
C5D4
C5D.5,
C5D6
C5D7
C5D8
C5D9
C5DA
C5DB
C5DC
C5DD
C5DE
C5DF
CD
21
CD
E5
21
CD
CA
lB
36
7E
12,
13
23
7E
12
13
El
EB
73
23
72
C9
66 C4
C9 Cl
10 C3
lC C8
2E C2
03 C5
00
PROGRAM DEVELOPMENT SYSTEM
..
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
1269 •
1270' SET USERS CUSTOM OUTPUT DRIVER ADDRESS
1271 •
1272 SETCO SHLD
UOPRT
127.3
RET
1274 •
1275' SET TYPE BYTE INTO HEADER
1276 •
1277 SETTY STA
HTYPE
1278
RET
1279 •
1280'
SET EXECUTE ADDRESS INTO HEADER
1281 •
1282 SETXO SHLD
XEQAD
1283
RET
1284 •
1285 •
1286 SETNU STA
,NUCNT SET THE NULL COUNT
1287
RET'
THAT"S DONE
1288 •
1289 •
1290 SETCR EOU
SET TO IGNORE CRC ERRORS
$
1291
STA
IGNCR FF=IGNORE ERRORS, ELSE=NORMAL
1292
RET
1293 •
1294 •
1295 •
CUSTOM COMMAND NAME AND ADDRESS INTO CUSTOM cnMMAND
1296 •
1297 •
1298 CUSET CALL
NAMES CUSTOM COMMAND ENTRY/REMOVAL
H,COMND DEFAULT ADDR IF NONE GIVEN
1299
LXI
1300
CALL
PSCAN GET RTN ADDR
1301
PUSH
H
SAVE RTN ADDR
1302
LXI
H,THEAD PT AT NAME TO SEARCH
1303
CALL
FDCOU SEARCH IT IN CUSTOM TABLE
1304
JZ
CUSE2 NOT IN TABLE--ENTER IT
D
IN TABLE, REMOVE IT
1305
DCX
1306
MVI
M,O
CHANGE NEW NAME TO BE ZERO
1307 CUSE2 MOV
A,M
GET 1ST CHAR OF NAME
1308'
STAX
D
ENTER IT INTO TABLE
1309
INX
o
AND THE 2ND NAME
1310
INX
H
1311
MOV
A,M
1312
STAX
0
NAME NOW ENTERED
D
GET SET TO ENTER ADDRESS
1313
INX
1314
POP
H
RESTORE RTN ADDR
1315
XCHG
1316
MOV
M,E
SET ADDR IN NOW
AND HI BYTE OF ADDR
1317
INX
H.
M,D
1318
MOV
NAME IS NOW ENTERED OR CLEARED
1319
RET
1320 •
1,321 • -'-
••
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C5EO E5
C5El CD 33 c6
C5E4 C2 FA C5
C5E7 36 01
C5E9 23
C5EA 77
C5EB'23
C5EC 77
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
..
PAGE
13
9999
COpy
SOLos3/1
3 nF 3 ••••••
1322 •
1323 •
1324 •
1325 •
1326'
THE FOLLOWING ROUTINES PROVIDE "BYTE BY BYTE" ACCESS
1327' TO THE CASSETTE TAPES ON EITHER A READ OR WRITE BASIS.
1328 •
1329' THE TAPE IS READ ONE BLOCK AT A TIME AND INDIVIDUAL
1330' TRANSFERS OF DATA HANDLED BYHANAGING A BUFFER AREA.
1331 •
1332' THE BUFFER AREA IS CONTROLLED BY A FILE CONTROL BLOCK
1333
(FCB) WHOSE STRUCTURE IS:
1334
1335 •
1336 •
7 BYTES FOR EACH OF THE TWO FILES STRUCTURED AS
1337'
FOLLOWS:
1338 •
00 IF CLOSED
BYTE - ACCESS CONTROL
1339 •
FF IF READING
1340 •
FE IF WRITING
1341 •
READ
COUNTER
1 BYTE 1342 •
BUFFER
POSITION
POINTER
1
BYTE
1343 •
2 BYTE - CONTROL HEADER ADDRESS
1344 •
2 BYTE - BUFFER LOCATION ADDRESS
1345 •
1346 •
1347 •
1348 •
1349 •
THIS ROUTINE "OPENS" THE CASSETTE UNIT FOR ACCESS
1350 •
1351'
ON ENTRY: A - HAS THE TAPE UNIT NUMBER (lOR 2)
HL - HAS USER SUPPLIED HEADER FOR TAPE FILE
1352 •
1353 •
1354 •
1355'
NORMAL RETURN:
ALL REGISTERS ARE ALTERED
1356 •
BLOCK IS READY FOR ACCESS
1357 •
1358'
ERROR RETURN:
CARRY BIT IS SET
1359 •
1360'
ERRORS: BLOCK ALREADY OPEN
1361 •
1362 •
H
SAVE HEADER ADDRESS
1363 BOPEN PUSH
CALL
LFCB
GET ADDRESS OF FILE CONTROL
1364
JNZ
TERE2 FILE WAS ALREADY OPEN
1365
1366
MVI
M,I
NOW IT IS
INX
H
POINT TO READ COUNT
1367
HOV
M,A
ZERO
1368
INX
POINT TO BUFFER CURSOR
H
1369
MOV
M,A
PUT IN THE ZERO COUNT
1370
1371
1372' ALLOCATE THE BUFFER
1373 •
••
PROGRAM DEVELOPMENT SYSTEM
SOLOS(TM)
77-03-27
COPYRIGHT·(C) 1977
C5ED 11 63 C8
C5FO 3A 5~ C8
C5F3 82
C5F~ 57
C5F5 Cl
C5F6 87
C5F7 C3 B6 C6
C5FA
C5FB
C5FC
C5FD
C5FE
C5FF
C600
C601
C602
El
Dl
AF
37
C9
3D
37
Dl
C9
..
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 9~~02
137~
1375
1376
1377
1378
1379
.1380
1381
1382
1383
138~
1385
1386
1387
1388
1389
1390
1391
1392
1393
•
UBUF
LXI
LDA
ADD
MOV
D,FBUFI POINT TO BUFFER AREA
FNUMF GET WHICH ONE WE ARE GOING TO USE
D
D,A
256 BIT ADD
POP
ORA
JMP
B
A
HEADER ADDRESS
CLEAR CARRY AND RETURN AFTER STORINe;
STORE THE VALUES
PSTOR
•
GENERAL
ERROR
RETURN POINTS FOR STACK CONTROL
•
•
TERE2 POP
H
D
TEREI POP
TEREO XRA
A
CLEAR ALL FLAGS
STC
SET ERROR
RET
•
•
EOFER
139~
1395
1396
1397
1398
1399
DCR
STC
POP
RET
A
D
SET MINUS FLAGS
AND CARRY
CLEAR THE STACK
THE FLAGS TELL ALL
C60D
C60E
C60F
C610
c613
P.~RAMS
23
7E
7E
CD 8F C6
C5
c61~ 21 07 00
c617 09
C618 87
C619 CA 2B C6
C61C
C61D
C61E
C61F
c621
C622
C623
E5
77
23
36 00
23
73
23
C62~
72
C625
C626
C627
C62A
60
69
CD 7C C7
El
l~Ol
1~02
1~o3
l~O~
1~o5
1~06
1~o7
l~o8
1~09
ON ENTRY:
A - HAS WHICH UNIT (lOR 2)
ERROR RETURNS:
C62B
C62C
c62D
c62E
C62F
C630
1~12
1~13
1~1~
1~15
1~16
1417
1~18
PC LOS
•
1~19 •
1~20
C60C 23
·1~21
1~22
1~23
1~2~
1~25
1~26
1~30
1431
1432
1433
1~34
1~35
1436 •
1437 •
1~38 •
1439
14~0
1441
1442
1443
1444
1~45
1446
1447
1448
1449
1450
1~51 •
•
•
•
•
•
•
CALL
RZ
ORA
INR
MVI
RZ
LFCB
A
A
77
1~55
FILE WASN"T OPEN
M,O
GET CONTROL BLOCK ADDRESS
WASN"T OPEN, CARRY IS SET FROM LFCe
CLEAR CARRY
SET CONDITION FLAGS
CLOSE THE CONTROL BYTE
WE WERE READING •.• NOTHING MORE TO DO
THE FILE OPERATIONS WERE "WRITES"
PUT THE CURRENT BLOCK ON THE TAPE
(EVEN IF ONLY ONE BYTE!!)
THEN WRITE AN END OF FILE TO THE TAPE
INX
H
1~53 •
1~5~
1~10
1~11
CD 33 C6
c8
87
3C
36 00
c8
1427
1428
1429
AF
23
77
El
C3 7C C7
1456
1~57
1458
1459
1460
1461
1462
1463
1464
1~65
1466
1467
1~68
C633
C636
C637
c639
C63C
C63F
21 55 c8
IF
E6 01
32 5~ C8
CA ~2 C6
21 5C c8
C6~2
c6~3
c6~~
7E
87
37
C6~2
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SA.N MATEO, CA 94402
SOLOS(TM)
77-03-27
COPYRIGHT (Cl 1977
1~52·
THIS ROUTINE CLOSES THE FILE BUFFER TO ALLOW ACCESS
FOR A DIFFERENT CASSETTE OR PROGRAM. IF THE FILE
OPERATIONS WERE "WRITE" THEN THE LAST RLOCK IS WRITTED
OUT AND AN "END OF FILE" WRITTEN TO THE TAPE. IF
THE OPERATIONS WERE "READS" THEN THE FILE IS JUST
MADE READY FOR NEW USE.
l~OO
C603
C606
C607
C608
c609
C60B
PROGRAM DEVELOPMENT SYSTEM
1469
1~70
1~71
1~72
1473
1474
1~75
1476
1~77
1478
1479
EOFW
PAGE
14
INX
MOV
H
CALL
PUSH
LXI
DAD
ORA
JZ
PLOAD BC GET HEADER ADDRESS, DE BUPFER ·ADDRESS
B
HEADER TO STACK
H,BLKOF OFFSET TO BLOCK SIZE
B
A
TEST COUNT
EOFW
NO BYTES ••• JUST WRITE EOF
A,M
GET CURSOR POSITION
WRITE LAST BLOCK
PUSH
MOV
INX
MVI
INX
MOV
INX
MOV
MOV
MOV
CALL
POP
H
M,A
H
M,O
H
M,E
SAVE BLOCK SIZE POINTER FOR EOF
PUT IN COUNT
ZERO THE HIGHER BYTE
BUFFER ADDRESS
H
M,D
H,B
L,C
WFBLK
H
PUT HEADER ADDRESS IN HL
GO WRITE IT OUT
BLOCK SIZE POINTER
NOW WRITE END OF FILE TO CASSETTE
XRA
MOV
INX
MOV
POP
JMP
A
M,A
PUT IN ZEROS FOR SIZE:
EOF MARK IS ZERO
BYT~
H
M,A
H
WFBLK
HEADER ADDRESS
WRITE IT OUT AND RETURN
•
•
•
•
•
THIS ROUTINE LOCATES THE FILE CONTROL BLOCK POINTED TO
BY REGISTER "A". ON RETURN HL POINT TO THE CONTROL BYT
•
AND REGISTER "A" HAS THE CONTROL WORD WITH THE FLAGS
•
•
SET FOR IMMEDIATE CONDITION DECISIONS.
•
•
LFCB
LXI
H,FCBAS POINT TO THE BASE OF IT
RAR
•
MOVE THE 1 & 2 TO 0 & 1 LIKE COMPUTERS LIKE
ANI
1
SMALL NUMBERS ARE THE RULE
STA
FNUMF CURRENT ACCESS FILE NUMBER
JZ
LFCBl UNIT ONE (VALUE OF ZERO)
LXI
H,FCBA2 UNIT TWO--PT TO ITS FCB
LFCBl EQU
$
HL PT TO PROPER FCB
MOV
A,M
PICK UP FLAGS FM FCB
ORA
A
SET FLAGS BASED ON CONTROL WORD
STC
SET CARRY IN CASE OF IMMEDIATE ERROR RETURN
/.,
/
••
SOLOS(TM)
11-03-21
COPYRIGHT (C) 1911
C645 C9
C646
C649
C64A
C64B
c64E
C650
C651
C652
C653
C654
C651
C658
C659
C65C
C65D
C65E
C65F
c662
C665
C668
C669
C66A
C66B
c66E
c66F
C610
C612
C613
C614
CD
C8
3C
FA
36
23
1E
E5
23
CD
El
B1
C2
D5
E5
23
CD
CD
DA
El
1B
B2
CA
13
23
36
2B
1B
Dl
33 C6
FC C5
FF
BF C6
15 C6
A6 C6
C8 C6
FA C5
FF C5
00
PROGRAM DEVELOPMENT SYSTEM
••
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
1480
RET
1481 •
1482 •
1483
1484
READ TAPE BYTE ROUTINE
1485
1486
ENTRY:
A - HAS FILE NUMBER
1481
1488
EXIT: NORMAL - A- HAS BYTE
ERROR
1489
CARRY SET
- IF FILE NOT OPEN OR
1490
PREVIOUS OPERATIONS WERE WRITE
1491
CARRY & MINUS - END OF FILE ENCOUNTERED
1492
1493
1494
1495
1496
LFCB
LOCATE THE FILE CONTROL BLOCK
1491 RTBYT CALL
RZ
FILE NOT OPEN
1498
TEST IF FF
1499
INR
A
JM
1500
TEREO ERROR WAS WRITING
SET IT AS READ (IN CASE IT WAS JUST OPENF.D)
MVI
1501
M,-1
H
1502
INX
GET READ COUNT
MOV
A,M
1503
PUSH
SAVE COUNT ADDRESS
1504
H
INX
H
1505
CALL
PLOAD GET THE OTHER PARAMETERS
1506
POP
H
1501
ORA
1508
A
JNZ
GTBYT IF NOT EMPTY GO GET BYTE
1509
1510 •
_
1511' CURSOR POSITION WAS ZERO ... READ A NEW BLOCK INTO
1512' THE BUFFER.
1513 •
1514 RDNBLK PUSH
BUFFER POINTER
D
PUSH
TABLE ADDRESS
H
1515
1516
INX
H
CALL
PHEAD PREPARE THE HEADER FOR READ
1511
1518
RFBLK READ IN THE BLOCK
CALL
JC
TERE2 ERROR POP OFF STACK BEFORE RETURN
1519
1520
POP
H
1521
MOV
LOW BYTE OF COUNT (WILL BE ZERO IF 256)
A,E
SEE IF BOTH ARE ZERO
1522
ORA
D
JZ
EOFER BYTE COUNT WAS ZERO •... END OF FILE
1523
MOV
NEW COUNT ( ZERO IS 256 AT THIS POINT)
1524
M,E
INX
BUFFER LOCATION POINTER
H
1525
1526
MVI
M,O
DCX
H
1521
MOV
COUNT TO A
A,E
1528
POP
GET BACK BUFFER ADDRESS
D
1529
1530 •
1531 •
1532 •
PROGRAM DEVELOPMENT SYSTEM
SOLOS(TM)
11-03-21
COPYRIGHT (C) 1911
C615
C616
C611
C618
C619
3D
11
23
1E
34
C61A
C61B
C61C
C61F
C680
C681
C682
83
5F
D2 80 C6
14
1A
B1
C9
C683
C686
C681
c688
c689
C68B
C68C
C68D
c68E
C68F
C690
C693
C694
C695
C696
c691
C69A
C69B
C69C
C69D
C69E
CD 33 C6
C8
3C
c8
36 FE
23
23
78
F5
E5
CD BF c6
El
7E
83
5F
D2 9B c6
14
FI
12
B1
34
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
1533
1534
1535
1536
1531
1538
1539
1540
1541
1542
1543
1544
1545
1546
1541
1548
1549
1550
1551
1552
1553
1554
1555
1556
1551
1558
1559
1560
1561
1562
1563
1564
1565
1566
1561
1568
1569
1570
1571
1512
1513
1574
1515
1516
1517
1518
1579
1580
1581
1582
1583
1584
1585
PAGE
15
THIS ROUTINE GETS ONE BYTE FROM THE BUFFER
•
• AND RETURNS IT IN REGISTER "A". IF THE END
OF
THE BUFFER IS REACHED IT MOVES THE POINTER
•
• TO THE BEGINNING OF THE BUFFER FOR THE NEXT
LOAD.
•
•
GTBYT DCR
A
BUMP THE COUNT
MOV
M,A
RESTORE IT
INX
H
MOV
A,M
GET BUFFER POSITION
INR
M
BUMP IT
•
ADD
E
MOV
E,A
DE NOW POINT TO CORRECT BUFFER POSITION
JNC
RTI
INR
D
RTI
LDAX
D
GET CHARACTER FROM BUFFER
ORA
A
CLEAR CARRY
RET
ALL DONE
THIS ROUTINE IS USED TO WRITE A BYTE TO THE FILE
ON ENTRY:
A -
BTBYT
•
WTl
CALL
RZ
INR
RZ
MVI
INX
INX
MOV
PUSH
PUSH
LFCB
HAS FILE NUMBJ;;R
HAS DATA BYTE
GET CONTROL BLOCK
FILE WASN °T OPEN
A
FILE WAS READ
M,OFEH SET IT TO WRITE
H
H
A,B
GET CHARACTER
PSW
H
SAVE CONTROL ADDRESS.2
NOW DO THE WRITE
CALL
POP
MOV
ADD
MOV
JNC
INR
POP
STAX
ORA
INR
PLOAD
BC GETS HEADER ADDR, DE BUFFER ADDRESS
H
A,M
COUNT BYTE
E
E,A
WTl
D
PSW
D
A
M
CHARACTER
PUT CHR IN BUFFER
CLEAR FLAGS
INCREMENT THE COUNT
..
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C69F CO
C6AO CD A6 C6
C6A3 C3 7C C7
C6A6
C6A9
C6AA
C6AD
C6AE
C6Bl
CD
C5
21
09
01
CD
C6B~ El
C6B5 C9
C6B6
C6B7
C6B8
C6B9
C6BA
C6BB
C6BC
C6BD
C6BE
BF C6
06 00
00 01
B6 C6
23
71
23
70
23
73
23
72
C9
C6BF 23
C6CO ~E
C6Cl 23
C6C2 ~6
C6C3 23
C6C~ 5E
C6C5 23
C6C6 56
C6C7 C9
C6C8 CD DE C7
PROGRAM DEVELOPMENT SYSTEM
..
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 9~~02
RNZ
RETURN IF COUNT DIDN'T ROLL OVER
1586
1587 •
1588.
THE BUFFER IS FULL. WRITE IT TO TAPE AND RESET
1589. CONTROL BLOCK.
1590 •
PHEAD PREPARE THE HEADER
CALL
1591
WFBLK WRITE IT OUT AND RETURN
JMP
1592
1593 •
159~ •
1595 •
1596 •
1597. THIS ROUTINE PUTS THE BLOCK SIZE (256) A~D BUFFER
1598. ADDRESS IN THE FILE HEADER.
1599 •
PLOAD GET HEADER AND BUFFER ADDRESSES
1600 PHEAD CALL
1601
PUSH
B
HEADER ADDRESS
1602
LXI
H,BLKOF-l PSTOR DOES AN INCREMENT
1603
DAD
B
HL POINT TO BLOCKSIZE ENTRY
1604
LXI
B,256
1605
CALL
PSTOR
1606
POP
HL RETURN WITH HEADER ADDRESS
H
1607
RET
1608 •
1609 •
H
1610 PSTOR INX
MOV
1611
M,C
1612
INX
H
MOV
M,B
1613
INX
H
1614
MOV
M,E
1615
INX
1616
H
MOV
M,D
1.617
1618
RET
1619 •
1620 •
1621 PLOAD INX
H
1622
MOV
C,M
1623
INX
H
1624
MOV
B,M
1625
INX
H
MOV
E,M
1626
INX
H
1627
MOV
D,M
1628
RET
1629
1630 •
1631 •
1632 •
1633 •
1634 •
1635.
THIS ROUTINE SETS THE CORRECT UNIT FOR SYSTEM READS
1636 RFBLK CALL
GTUNT SET UP A.UNIT WITH SPEED
1637 •
1638 •
SOLOS(TM)
77-03-27 ..
COPYRIGHT (C) 1977
1639
1640
1641
1642
1643
1644
1645
1646
C6CB
C6CC
C6CE
C6Dl
D5
06 03
CD EF C7
DB FB
C6D3 E5
C6D~ CD 23 C7
C6D7 El
C6D8 DA 06 C7
C6DB C2 03 c6
C6DE
C6DF
C6E2
C6E5
C6E6
E5
11 lC C8
CD D2 C7
El
C2 03 C6
C6E9
C6EA
C6EB
C6EC
C6EF
Dl
7A
B3
2A 23 C8
EB
C6FO C2 F6 C6
C6F3 2A 25 C8
C6F6 D5
C6F7
C6F7 CD 15 C7
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP,
P,O, BOX 5260
SAN MATEO, CA 94~02
••
PAGE
16
TAPE READ ROUTINES
ON ENTRY:
A
HL
DE
HAS UNIT AND SPEED
POINT TO HEADER BLOCK
HAVE OPTIONAL PUT ADDRESS
16~7
ON EXIT:
CARRY IS SET IF ERROR OCCUR ED
1648
.TAPE UNITS ARE OFF
1649
1650
1651 RTAPE PUSH
0
SAVE OPTIONAL ADDRESS
MVI
1652
SHORT DELAY
B,3
TON
CALL
1653
IN
TDATA CLEAR THE UART FLAGS
1654
1655 •
1656 PTAPI PUSH
READER ADDRESS
H
CALL
RHEAD GO READ HEADER
1657
1658
POP
H
1659
JC
TERR
IF AN ERROR OR ESC WAS RECEIVED
1660
JNZ
PTAPI IF VALID HEADER NOT FOUND
1661 •
1662· FOUND A VALID HEADER NOW DO COMPARE
1663 •
1664
PUSH
H
GET BACK AND RESAVE ADDRESS
LXI
D,THEAD
1665
CALL
DHCMP COMPARE DE-HL HEADERS
1666
POP
H
1667
PTAPI
1668
JNZ
1669 •
1670 •
1671
POP
D
OPTIONAL "PUT" ADDRESS
MOV
A,D
1672
ORA
E
SEE IF DE IS ZERO
1673
167~
LHLD
BLOCK GET BLOCK SIZE
XCHG
••• TO DE
1675
1676. DE HAS HBLOCK •.•• HL HAS USER OPTION
1677
JNZ
RTAP
IF DE WAS ZERO GET TAPE LOAD ADDRESS
1678
LHLD
LOADR GET TAPE LOAD ADDRESS
1679 •
1680 •
THIS ROUTINE READS "DE" BYTES FROM·THE TAPE
1681 •
TO ADDRESS HL. THE BYTES· MUST BE FROM ONE
1682 •
CONTIGUOUS PHYSICAL BLOCK ON THE TAPE.
1683 •
168~ •
HL HAS "PUT" ADDRESS
1685 •
DE HAS SIZE OF TAPE BLOCK
1686 •
1687 •
1688 RTAP
PUSH
0
SAVE SIZE FOR RETURN TO CALLING PROGRAM
1689 •
1690 RTAP2 EQU
$
HERE TO LOOP RDING RL~S
1691
CALL
DCRCT DROP COUNT, R.LEN THIS BLK
••
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C6FA CA 10 C7
C6FD CD 44 C7
C700 DA 06 C7
c703 CA F7 C6
C706 AF
C707 37
C70B C3 11 C7
C70B
C70D
C710
C711
C713
C714
C715
C716
C717
C71B
C71B
C71C
C71D
C71E
C71F
06 01
CD Fl C7
AF
D3 FA
Dl
C9
C715
AF
47
B2
C2 20 C7
B3
CB
43
5A
C9
Cno
cno 15
C721 B7
C722 C9
C723
C725
CnB
C729
C72B
06
CD
DB
DB
B7
CnC C2
C72F 05
C730 C2
OA
5D C7
FB
23 C7
25 C7
C733 CD 6F C7
C736 DB
C737 FE 01
PROGRAM DEVELOPMENT
SYSTE~
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
1692
JZ
RTOFF ZERO=ALL DONE
1693 •
CALL
RHEDI READ THAT MANY BYTES
1694
JC
1695
TERR
IF ERROR OR ESC
JZ
1696
RTAP2 RD OK--READ SOME MORE
1697 •
169B· ERROR RETURN
1699 •
1700 TERR
XRA
A
1701
STC
SET ERROR FLAGS
1702
JMP
RTOFI
1703 •
1704 •
1705 TOFF
MVI
B,I
1706
CALL
DELAY
1707 RTOFF XRA
A
170B RTOF 1 OUT
TAPPT
POP
1709
o
RETURN BYTE COUNT
RET
1710
1711 •
1712 •
1713 DCRCT EQU
$
COMMON RTN TO COUNT DOWN RL~ LENGTHS
1714
XRA
A
CLR FOR LATER TESTS
1715
MOV
B,A
SET THIS BLK LEN=256
1716
ORA
D
IS AMNT LEFT < 256
JNZ
1717
DCRC2 NO--REDUCE AMNT BY 256
1718
ORA
E
IS ENTIRE COUNT ZERO
RZ
1719
ALL DONF--ZERO=THIS CONDITION
1720
MOV
B,E
SET THIS BLK LEN TO AMNT REMAINI~r.
1721
HOV
E,D
MAKE ENTIRE COUNT ZERO NOW
1722
RET
ALL DONE (NON-ZERO FLAG)
1723 DCRC2 EQU
$
REDUCE COUNT BY 256
1724
DCR
D
DROP BY 256
1725
ORA
A
FORCE NON-ZERO FLAG
1726
RET
NON-ZERO=NOT DONE YET (BL~ LEN=256)
1727 •
1728 •
1729·
READ THE HEADER
1730 •
1731 RHEAD MVI
B,10
FIND 10 NULLS
1732 RHEA 1 CALL
STAT
RC
1733
IF ESCAPE
1734
IN
TDATA IGNORE ERROR CONDITIONS
ORA
1735
A
ZERO?
1736
JNZ
RHEAD
DCR
B
1737
1738
JNZ
RHEA 1 LOOP UNTIL 10 IN A ROW
1739
1740
WAIT FOR THE START CHARACTER
1741 •
1742 SOHL
CALL
TAPIN
1743
RC
ERROR OR ESCAPE
1744
CPI
AT LEAST 10 NULLS IMMEDIATELY FOLLOWED RY AN 01
••
PROGRAM DEVELOPMENT SYSTEM
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C739 DA 33 C7
C73C C2 23 C7
C73F 21 lC CB
C742 06 10
C744
C744 OE 00
C746
C746 CD 6F C7
C749 DB
C74A 77
C74B 23
C74C CD AB C7
C74F '05
C750 C2 46 C7
C753
C756
C757
C75B
C75B
C75C
CD 6F C7
A9
CB
3A 11 CB
3C
C9
C75D
C75F
C761
C762
C765
C768
C76A
C76D
C76E
DB
E6
CO
CD
CA
E6
C2
37
C9
FA
40
IF CO
5D C7
7F
5D C7
C76F CD 5D C7
C772 D8
C773 DB FA
C775 E6 18
C777 DB FB
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
17B7
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
JC
JNZ
•
•
•
RHED2
PAnE
17
STILL A NULL, KEEP WAITING
NON-ZERO, START SEQUENCE OVER AGAIN
NOW GET THE HEADER
LXI
MVI
•
RHEDI
SOHL
RHEAD
EQU
MVI
EQU
CALL
RC
MOV
INX
CALL
DCR
JNZ
H,THEAD POINT TO BUFFER
B,HLEN LENGTH TO READ
C,O
$
TAPIN
M,A
H
DOCRC
B
RHED2
RD A BLOCK INTO HL FOR B BYTES
INIT THE CRC
LOOP HERE
GET A BYTE
STORE IT
INCREMENT ADDRESS
GO COMPUTE THE CRC
WHOLE HEADER YET?
DO ALL THE BYTES
THIS ROUTINE GETS THE NEXT BYTE AND COMPARES IT
• TO THE VALUE IN REGISTER C. THE FLAGS ARE SET ON
• RETURN.
•
CALL
TAPIN GET CRC BYTE
XRA
C
CLR -CARRY AND SET ZERO IF MATCH, ELSE NON-ZERO
RZ
CRC WAS FINE
LDA
IGNCR GET POSSIBLE OVERRIDE CRC ERROR FLAG
INR
A
FF=IGNORE CRC ERRORS, ELSE PROCESS CRC ERROR
RET
•
THIS ROUTINE GETS THE NEXT AVAILABLE BYTE FROM THE
•
• TAPE. WHILE WAITING FOR THE BYTE THE KEYBOARD IS TESTED
• FOR AN ESC COMMAND. IF RECEIVED THE TAPE LOAD IS
• TERMINATED AND A RETURN TO THE COMMAND MODE IS MADE.
•
STAT
IN
TAPPT TAPE STATUS PORT
ANI
TDR
RNZ
CALL
SINP
CHECK INPUT
JZ
NOTHING THERE YET
STAT
AlII
CLR PARITY 1ST
7FH
JNZ
STAT
NOT A MODE (OR EVEN CTL-@)
STC
SET ERROR FLAG
RET
AND RETURN
•
•
•
TAPIN CALL
WAIT UNTIL A CHARACTER IS AVAILABLE
STAT
RC
•
TAPPT TAPE STATUS
TREDY IN
TFE+TOE DATA ERROR?
ANI
IN
TDATA GET THE DATA
••
SOLOS(TMl
77-03-27
COPYRIGHT (Cl 1977
C779 C8
C77A 37
C77B C9
C77C CD DE C7
C77F
C780
C783
C78#
C787
C788
C789
C78A
C78B
C78C
C78D
C78E
C78F
C77F
E5
CD AF C7
E1
11 07 00
19
5E
23
56
23
7E
23
66
6F"
C790
C790 E5
C791
C791 CD 15
C794 CA DB
C797 CD C3
C79A C3 91
C79D
C79E
C7AO
C7A2
C7A.5
C7A6
F5
DB
E6
CA
F1
D3
C7
C7
C7
C7
FA
80
9E C7
FB
C7A8
C7A8 91
PROGRAM DEVELOPMENT SYSTEM
••
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
1798
RZ
IF NO ERRORS
1799
STC
SET ERROR FLAG
1800
RET
1801 •
1802 •
1803· THIS ROUTINE GETS THE CORRECT UNIT FOR SYSTEM WRITES
1804 WFBLK CALL
GTUNT SET UP A WITH UNIT AND SPEED
1805 •
1806 •
1807
WRITE TAPE BLOCK ROUTINE
1808
1809 •
1810·
ON ENTRY:
A HAS UNIT AND SPEED
1811 •
HL
HAS POINTER TO HEADER
1812 •
1813 •
1814 WTAPE EQU
$
HERE TO WRITE TAPE
1815
PUSH
H
SAVE HEADER ADDRESS
1816
CALL
WHEAD TURN ON, THEN WRITE HDR.
1817
POP
H"
1818
LXI
D,BLKOF OFFSET TO BLOCK SIZE IN HEADER
1819
DAD
D
HL POINT TO BLOCK SIZE
MOV
E,M
1820
1821
INX
H
1822
MOV
D,M
DE HAVE SIZE
1823
INX
H
1824
MOV
A,M
1825
INX
H
MOV
H,M
1826
1827
MOV
L,A
HL HAVE STARTING ADDRESS
1828 •
1829 •
THIS ROUTINE WRITES ONE PHYSICAL BLOCK ON THE
1830· TAPE "DE" BYTES LONG FROM ADDRESS "HL".
1831 •
1832 •
1833 WRL01 EQU
$
HERE FOR THE EXTRA PUSH
1834
PUSH
H
A DUMMY PUSH FOR LATER EXIT
1835 WTAP2 EQU
$
LOOP HERE UNTIL ENTIRE AMOUNT READ
1836
CALL
DCRCT DROP COUNT IN DE AND SET UP B WILEN THIS BLK
1837
JZ
TOFF
RETURNS ZERO IF ALL DONE
1838
CALL
WTBL
WRITE BLOCK FOR BYTES IN B (256)
1839
JMP
WTAP2 LOOP UNTIL ALL DONE
1840 •
1841 •
1842 WRTAP PUSH
PSW
1843 WRWAT IN
TAPPT TAPE STATUS
1844
ANI
TTBE
IS TAPE READY FOR A CHAR YET
1845
JZ
WRWAT NO--WAIT
1846
POP
PSW
YES--RESTORE CHAR TO OUTPUT
1847
OUT
TDATA SEND CHAR TO TAPE
1848 •
1849 DOCRC EQU
$
A COMMON CRC COMPUTATION ROUTINP.
1850
SUB
C
SOLOS(TMl
77-03-27
COPYRIGHT (Cl 1977
C7A9
C7AA
C7AB
C7AC
C7AD
C7AE
4F
A9
2F
91
4F
C9
C7AF
C7B2
C7B4
C7B5
C7B8
C7B9
C7AF
CD ED C7
16 32
AF
CD 9D C7
15
C2 B4 C7
C7BC 3E 01
C7BE CD 9D C7
C7C1 06 10
C7C3
C7C5
C7C6
C7C9
C7CA
C7CB
C7CE
C7CF
OE
7E
CD
05
23
C2
79
c3
00
C7D2
C7D4
C7D5
C7D6
C7D7
C7D8
C7D9
C7DA
C7DB
06 05
1A
BE
CO
05
C8
23
13
C3 D4 C7
C7DE
C7E1
C7E2
C7E5
C7E8
C7DE
3A 54 C8
B7
3A OD C8
C2 EA C7
C6 40
9D C7
C5 C7
9D C7
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P. O. BOX 5260
SAN MATEO, CA 94402
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
18"85
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
MOV
XRA
CMA
SUB
MOV
RET
••
PAGE
18
C,A"
C
C
C,A
ONE BYTE NOW WRITTEN
•
•
THIS ROUTINE WRITES THE HEADER POINTED TO BY
•
•
HL TO THE TAPE.
•
WHEAD EQU
$
HERE TO 1ST TURN ON THE TAPE
CALL
WTON
TURN IT ON, THEN WRITE HEADER
MVI
D,50
WRITE 50 ZEROS
A"
NULOP XRA
CALL
WRTAP
"DCR
D
JNZ
NULOP
•
MVI
A,1
CALL
WRTAP
MVI
B,HLEN LENGTR TO WRITE OUT
•
WTBL
MVI
C,O
RESET eRC BYTE
WLOOP MOV
A,M
GET CHARACTER
CALL
WRTAP WRITE IT TO THE TAPE
DCR
B
INX
R
JNZ
WLOOP
MOV
GET CRC
A,C
JMP
WRTAP PUT IT ON TRE TAPE AND RETURN
•
•
•
THIS ROUTINE COMPARES THE HEADER IN TREAD TO
THE USER SUPPLIED HEADER IN ADDRESS HL.
•
•
ON RETURN IF ZERO IS SET THE TWO NAMES COMPARED
•
DHCMP MVI
B,5
DHLOP LDAX
D
CMP
M
RNZ
DCR
B
RZ
IF ALL FIVE COMPARED
INX
H
INX
D
JMP
DHLOP
•
GTUNT EQU
$
SET A=SPEED + UNIT
LDA
FNUMF GET UNIT
ORA
A
SEE WHICH UNIT
LDA
TSPD
BUT 1ST GET SPEED
JNZ
GTUN2 MAKE IT UNIT TWO
ADI
TAPE2 THIS ONCE=UNIT 2, TWICE=UNIT 1
••
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
C7EA C6 40
C7EC C9
C7ED 06 04
C7EF
C7EF D3 FA
C7F1
C7F4
C7F5
C7F6
C7F7
C7FA
C7FB
C7FE
11 00 00
1B
7A
B3
C2 F4 C7
05
C2 F1 C7
C9
CCOO
009A
0097
00B1
0093
OOBB
OOBE
OOBo
005F
OOOA
OOOD
0020
0020
0018
001B
PROGRAM DEVELOPMENT SYSTEM
1904
1905
1906
1907
190B
1909
1910
1911
1912
1913
1914
1915
1916
1917
191B
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
193B
1939
1940
1941
1942
1943
1944
1945
1946
1947
194B
1949
1950
1951
1952
1953
1954
1955
1956
GTUN2
•
WTON
TON
•
DELAY
DLOP1
ADI
RET
MVI
EOU
OUT
LXI
DCX
MOV
ORA
JNZ
DCR
JNZ
RET
TAPE2
UNIT AND SPEED NOW SET IN A
ALL DONE
B,4
SET LOOP DELAY (BIT LONGER ON A WRITE)
ijERE TO TURN A TAPE ON THEN DELAY
GET TAPE MOVING, THEN DELAY
$
TAPPT
..
..
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1977
OOFA
OOFB
00F9
OOFD
OOFC
OOFE
OOFA
OOFB
OOFF
D,O
D
A,D
E
DLOP1
B
DELAY
•
•
••••• -- END OF PROGRAM-•
•
•
•
S Y S T E M
EQUATES
•
•
•
VDM PARAMETERS
•
•
VDMEM EOU
OCCOOH VDM SCREEN MEMORY
•
•
KEYBOARD SPECIAL KEY ASSIGNMENTS
•
•
THESE
DEFINITIONS
ARE DESIGNED TO ALLOW
•
• COMPATABILITY WITH CUTER(TM). THESE ARE THE
SAME
KEYS
WITH
BIT
7 (X'BO') STRIPPED OFF.
•
•
DOWN
EOU
9AH
CTL-Z
UP
EQU
CTL-W
97H
LEFT
EQU
B1H
CTL-A
RIGHT EOU
93H
CTL-S
CLEAR EOU
BBH
CTL-K
HOME
EQU
BEH
CTL-N
MODE
EOU
BOH
CTL-@
BACKS EOU
5FH
BACKSPACE
LF
EQU
10
CR
EQU
~3
BLANK EQU
SPACE EQU
BLANK
CX
EOU
"X"-40H
ESC
EQU
1BH
•
PORT ASSIGNMENTS
•
•
0001
0002
0004
oooB
0010
0020
0040
OOBO
0001
0002
0004
OOOB
0010
0040
0080
0001
OOBO
0040
C800
C800
CBFF
C800
C802
C804
C806
PROGRAM DEVELOPMENT SYSTEM
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
..
PAGE
19
OFAH
STATUS PORT GENERAL
1957 STAPT EQU
1958 SERST EOU
OF8H
SERIAL STATUS PORT
SERIAL DATA
1959 SDATA EOU
OF9H
1960 PDATA EQU
OFDH
PARALLEL DATA
1961 KDATA EOU
OFCH
KEYBOARD DATA
1962 DSTAT EQU
OFEH
VPM CONTROL PORT
1963 TAPPT EQU
OFAH
TAPE STATUS PORT
1964 TDATA EQU
OFBH
TAPE DATA PORT
1965 SENSE EQU
OFFH
SENSE SWITCHES
1966 •
1967 •
1968 •
BIT ASSIGNMENT MASKS
1969 •
1970 •
1971 SCD
EQU
1
SERIAL CARRIER DETECT
SERIAL DATA SET READY
1972 SDSR
EQU
2
EQU
4
1973 SPE
SERIAL PARITY ERROR
EQU
1974 SFE
8
SERIAL FRAMING ERROR
1975 SOE
SERIAL OVERRUN ERROR
EQU
16
1976 SCTS
EQU
SERIAL CLEAR TO SEND
32
EQU
64
SERIAL DATA READY
1977 SDR
SERIAL TRANSMITTER BUFFER EMPTY
1978 STBE
EOU
12B
1979 •
1980 KDR
1
KEYBOARD DATA READY
EOU
PARALLEL DATA READY
1981 PDR
EOU
2
PARALLEL DEVICE READY
4
1982 PXDR
EOU
1983 TFE
EOU
B
TAPE FRAMING ERROR
1984 TOE
EOU
16
TAPE OVERFLOW ERROR
1985 TDR
64
EOU
TAPE DATA READY
1986 TTBE
EOU
128
TAPE TRANSMITTER BUFFER EMPTY
1987 •
19BB SOK
SCROLL OK FLAG
EOU
1989 •
1990 TAPE1 EOU
BOH
1=TURN TAPE ONE ON
40H
1991 TAPE2 EOU
1=TURN TAPE TWO ON
1992 •
1993 •
1994 •
1995 •
GLOBAL
ARE A
SYSTEM
1996 •
1997 •
RAM STARTS JUST AFTER ROM
1998
ORG
START+oBoOH
1999 •
$
START OF SYSTEM RAM
2000 SYSRAM EQU
2001 SYSTP EQU
SYSRAM+3FFH STACK WORKS FM TOP DOWN
2002 •
2003 •
2004.
PARAMETERS STORED IN RAM
2005 •
2006 UIPRT DS
2
USER DEFINED INPUT RTN IF NON ZERO
2007 UOPRT DS
USER DEFINED OUTPUT RTN IF NON ZERO
2
2008 DFLTS DS
DEFAULT PSUEDO 1/0 PORTS (ALWAYS ZERO IN SOLOS)
2
2009 IPORT DS
1
CRNT INPUT PSUEDO PORT
••
PROGRAM DEVELOPMENT SYSTEM
SOLOS(TM)
77-03-27
COPYRIGHT (C) 1911
2010
2011
2012
2013
2014
2015
2016
2011
201B
2019
2020
2021
2022
C807
C808
CB09
cBOA
CBOB
C80C
C80D
CBOE
CB10
C811
C812
••
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
.SAN MATEO, CA 94402
OPORT
NCHAR
LINE
BOT
SPEED
ESCFL
TSPD
INPTR
NUCNT
IGNCR
•
SOLOS(TM)
11-03-21
COPYRIGHT (C) 1911
DS
DS
DS
DS
DS
DS
DS
DS
DS
DS
1
1
1
1
1
1
1
2
1
1
CRNT OUTPUT PSUEDO PORT
CURRENT CHARACTER POSITION
CURRENT LINE POSITION
BEGINNING OF TEXT DISPLACEMENT
SPEED CONTROL BYTE
ESCAPE FLAG CONTROL BYTE
CURRENT TAPE SPEED
FOR COMPATABILITY WI CUTER
NUMBER OF NULLS AFTER CRLF
FF=IGNORE CRC ERRORS, ELSE NORMAL
DS
10
ROOM FOR FUTURE EXPANSION
•
2023
• • • • I •S
2024 •• • • T• HIS
~
•
• THE
• • • • H• E• A• D• E• R• • LAY
• • • 0 • U• T• • •
2025 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
C81C
C821
CB22
CB23
C825
C827
CB29
c82C
0010
0001
C83C
C854
C855
C85C
C863
CA63
ADOUT
ARET
Bl.ANK
BOT
CHRLI
Cl.INE
CONT
CRLF
CUSE2
CAB4
C3E8
Cl·9B
0020
C80A
C511
COF4
C1FF
C2F9
C5D3
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2031
2038
2039
2040
2041
2042
2043
2044
2045
2046
2041
2048
2049
2050
2051
2052
AINP
ARETl
BLKOF
BOUT
CLEAR
COMNl
COPRC
CUR
CUSET,
•
THEAD
HTYPE
Bl.OCK
LOADR
XEQAD
HSPR
•
HLEN
BLKOF
DHEAD
•
•
CUTAB
•
•
FNUMF
FCBAS
FCBA2
FBUFl
NAME
THIS BYTE MUST BE ZERO
TYPE
BLOCK SIZE
LOAD ADDRESS
AUTO EXECUTE ADDRESS
SPARES
DS
DS
DS
DS
DS
DS
DS
5
1
1
2
2
2
3
EQU
EQU
OS
$-THEAD l.ENGTH OF HEADER
Bl.OCK-THEAO OFFSET TO BLOCK SIZE
A DUMMY HOR FOR COMPARES WHIl.E RDoING
HLEN
DS
6·4
ROOM FOR UP TO 6 CUSTOM USER COMMANDS
FOR CURRENT FIl.E OPERATIONS
DS
1
1ST FILE CONTROl. BLOCK
DS
1
2ND FILE CONTROl. BLOCK
DS
1
DS
2·256 SYSTEM FILE BUFFER BASE
THIS IS AN AREA USED BY CUTER
81
DS
START OF USER AREA
USARE EQU
$
REMEMBER THAT THE STACK WORKS ITS WAY DOWN FROM
•
THE END OF THIS lK RAM AREA.
•
•
• _.-
C022
C19D
0007
C406
008B
C1CO
C205
CODl
C5BD
ALOAD
ARF.T2
Bl.OCK
CHAR
CLERA
COMND
CR
CURET
CUTAB
C548
C1A2
C823
C094
C1B4·
C1C9
OOOD
C1Ao
C83C
AOUT
BACKS
. BOPEN
CHPCK
CLINl
COHTA
CREM
CURse
ex
C01C
005F
C'iEO
C05E
COFA
C24A
C136
COCF
0018
DCRC2
C120
DFLTS
C804
DISPO
C222
DLOOP
C3C8
DOWN
009A
ENL03
C459
EOFW
C62B
C481
ERR2
ERROT
C2D2
ESCSP
C168
FCBA2
CB5C
FDCOU
C22E
GOBAC
C06B
GTUNT
C7DE
HEOUl
C414
HSPR
C829
INPTR
CSOE
KDATA
OOFC
LF
OOOA
LISTl
C539
NAME
C469
NCHAR
CBoB
NLOOP
C56A
OCHAR
C09B
C41F
OUTH
PC LOS
C603
PDOWN
COCB
PHEAD
C6A6
PLOAO
C6BF
PSCAN
C310
PXDR
0004
C004
RETRN
RHEDl
C144
RTAP
C6F6
RTOFl
C111
SCD
0001
SCROL
COAC
SDROT
C04A
SERST
00F8
SETCO
C5A9
SETOT
C5A 1
SETXQ
C5Bl
. C340
SHEX
SOK
0001
SPEED
C80B
START
COOO
STSPD
C598
TAERR
C514
TAPPT
OOFA
0040
TDR
TERM
C361
TFE
0008
C52B
TLIST
DCRCT
DHCMP
DISPl
DLOPl
DSTAT
ENLOP
ERASl
ERRIT
ESC
EXEC
FCBAS
FNUMF
GOBK
HBOUT
HEOUT
HTYPE
IOPRC
KDR
l.FCB
l.LIST
NAMEl
NCOM
NUCNT
OK
OUTPR
PCR
PDR
PHOME
PRIT
PSTOR
ROBLK
RFBLK
RHED2
RTAP2
RTOFF
SCHR
SCTS
SDSR
SET
SETCR
SETSP
SETY
SINP
SOUT
SROL
STAT
STUNT
TAPEl
TASPD
TEREO
TERMl
THEAD
Tl.OA2
PROGRAM DEVELOPMENT·SYSTEM
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
C115
C1D2
C22B
C1F4
OOFE
C42B
CODB
C2CB
001B
C45E
C855
C854
C07C
C3ED
C40B
C822
CO?6
0001
C633
C531
C46E
C243
c810
COCl
C03B
C141
0002
COE5
Cl15
C6B6
Con
C6C8
C146
C6n
C710
C32E
0020
0002
C51A
C5B9
C594
C18C
C01F
C019
coBo
C15D
C4A2
0080
C58E
C5FC
C373
C81C
C4B5
DEFLT
C49A
DHEAD
C82C
DISPD
C599
DLPl
C3D3
DUMP
C3BF
ENTER
C423
COEE
ERAS3
ERRM
C525
ESCFL
C80C
EXECl
c461
FCl.OS
COOA
FOPEN
C001·
GTBYT
C615
HCONV
C34D
HLEN
0010
IGNCR
C811
IPORT. C806
KSTAT
C02E
C642
l.FCBl
l.OADR
C825
NAMES
C466
NEXT
coBO
NULOP
C1B4
OPORT
C801
PASTA
C2DD
. Cl0F
PCUR
PERSE
COD5
PLEFT
Cl0B
PROMP
C2Fl
PTAPl
c603
RDBYT
COOD
RHEAl
C125
RIGHT
0093
RTAPE
C6CB
SBLK
C31B
SCHRl
C330
SDATA
00F9
SECON
C190
SETAB
C2A2
SETIN
C59D
SETTY
C5AD
SFE
0008
SOE
0010
SPACE
0020
C042
SSTAT
S·TBE
0080
SYSRA
C800
TAPE2
0040
TBl.
C273
TEREl
C5FB
TERM2
C3B9
TIMER
C011
TLOA3
C4Cl
DELAY
C1Fl
DHLOP
C1D4
DISPT
C221
DOCRC
C1AB
ENLOl
C43C
EOFER
C5FF
ERRl
C480
ERROl
C2D6
C15F
ESCS
FBUFl
c863
FDCOM
C231
GCLIN
C1E4
GTUN2
C1EA
HCOVl
C35D
HOME
008E
INIT
COOl
ITAB·
C29A
LEFT
0081
LINE
c809
MODE
0080
NAOUT
C550
C4B6
NFlL
NULOT
C301
OTAB
C292
PBACK
C13E
POATA
OOFD
PESC
C159
C140
Pl.F
PROUT
C2E6
PUP
Cl04
RDNBL
C65C
RHEAD
C723
RTl
C680
RTBYT
C646
SBLKl
C31D
SCOIIV
C33A
SOR
0040
SENSE
OOFF
SETCI
C5A5
SETNU
C5B5
SETX.
cl88
SHE·l
C343
SOHl.
C733
SPE
0004
STAPT . OOFA
STRTA
C1AF
SYSTP
CBFF
TAPIN
C16F
TDATA
OOFB
TERE2
C5FA
TERR
C706
TIN
C38R
Tl.OAD
e4A1
PAGE
20
PROGRAM DEVELOPMENT SYSTEM
II
SOLOS(TMl
77-0J-27
COPYRIGHT (Cl 1977
TOE
TREDY
TTBE
UOPRT
VDAD2
WFBLK
WRBYT
WTl
WTBYT
0010
C773
0080
CB02
C120
C77C
COlO
C69B
C6B3
TOFI'
TSAVE
TXEQ
UP
VDADD
WHEAD
WRLOl
WTAP2
WTLPl
••
SOFTWARE TECHNOLOGY CORP.
P.O. BOX 5260
SAN MATEO, CA 94402
C70B
C4E6
C4A6
0091
CllC
C7AF
C790
C191
C400
TON
TSPD
UBUF
USARE
VDMEM
WLOOP
WRTAP
WTAPE
WTON
C7EI'
CBOD
C5F5
CAB4
CCOO
C7C5
C79D
C77F
C1ED
TOUT
TSRCH
UIPRT
VDAD
VDMOT
WRBLr(
WRWAT
WTBL
XEQAD
P~G~
C38B
COB2
C800
C123
C054
C016
C79E
C7C3
CBn
21
X
DRAWINGS
X-I
X-2
X-3
X-4
X-S
X-6
X-7
X-8
X-9
X-IO
X-II
X-12
X-13
X-14
X-IS
X-16
'X:... 17
X-18
X-19
X-20
X-21
X-22
X-23
REV A
Assembly, Fan Closure
Assembly, PCB, Sol Regulator
Assembly, Power Supply, Sol (Sheet 1 of 2)
Assembly, Power Supply, Sol (Sheet 2 of 2)
Assembly, PCB, Sol-PC (Sheet 2 of 2)
Assembly, PCB, Sol-PC (Sheet 1 of 2)
Assembly, PCB, Personality Module (2708/9216)
Assembly, Top, Sol (Sheet 3 of 3)
Assembly, Top, Sol (Sheet 2 of 3)
Assembly, Top, Sol (Sheet 1 of 3)
Sol-PC Block Diagram
Sol Regulator Schematic
Sol Power Supply Schematic
Sol CPU and Bus Schematic
Sol Memory and Decoder Schematic
Sol Input/Output Schematic
Sol Display Control Schematic
Sol Audio Tape I/O Schematic
Personality Module (2708/9216) Schematic
Sol Keyboard Photo
Sol Keyboard Block Diagram
Sol Keyboard Schematic
Assembly, Sol Keyboard
X-1
7
o
'''I' DISC;';.";';TlO=N---
....,
'
I
OJ
I
2
3
1
RE..VI$ION$
o
o
o
D
e.Ct.l \o'l4'l , 10244
Copyright 1976
D
o
X-2
By
NOTSS:
&
cur
11-le..S.e. T~AC:::E.$
';'IDE.. OF THE:: pc:::e.
c
ANC"
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M<:>lJN1
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E·E
B
wH'I'
B
D·D
REF. DES.
PART OR
DWB, NO.
PART DESCRIPTION
ProcessorTechnology
Ul-LESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN INCHES:
TOLERANCES ARE:
~Ir'"
DRAWN:
DATE:
CHECKED:
A
Cme
FRACTIONS
DECIMALS
ANGLES
± -
.xx ± - ± .xxx± -
RELEASED:
DATE:..
DATI:
I{.. "'."'"~vf,
~_~I·.
~---------..J::;':;""'......i.':""::;L.=..":""':'-L..-~:""-';"::"~---1
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PC B) .sc?I
R~GUL-A-rO~
SIZE
I-N-EX-T-A-SS-V.-f----,US":":ED-QN--1
4
3
2
C
DRAWING NO.
10.5008
1
REV.
D
A
8
7
6
1
2
3
4
5
~
REVISIONS
DESCRIPTION
TR
ECII 1024 Sl 101'19 ID244 LREbgAWIJ)
X-3
D
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B
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DIMENSIONS ARE IN INCHES:
TOLERANCES ARE:
A
FRACTIONS DECIMALS
± -
PART DESCRIPTION
PART OR DWG. NO.
Utl..ESS OTHERWISE SPECIFIED
ProcessorTechnology ...-, 1-110
OATE:
11-
........,
ANGLES
DATI:
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A
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o
.-
NOTES:
1. LEOS 1,2, & 3
ARE MV5752
2. Q1, Q2 & Q9 ARE 2N4274, Q3 -
Q8 ARE 2N3640
Sol- KEYBOARD
ASSEMBLY
APPENDICES
AI
Deleted
All
8080 Operating Codes
AlII
Standard Color Code
AIV
Loading DIP Devices, Soldering Tips,
and Installing Augat Pins
AV
IC Pin Configurations
AVI
TV Interface
AVII
Pin-outs for Connectors
S-lOO Bus Definitions, Switch Functions,
and Bit Assignments
AVIII
IIYour Personal Genie,"
(An Article on Types of Software)
.'6'
0
.~.'
JUMP
JMP
JNZ
JZ
,JNC
JC
JPO
JPE
JP
JM
PCHl
C3
C2
CA
D2
DA
E2
EA
F2
FA
E9
Adr
MOVE
IMMEDIATE
MVI
MVI
MVI
MVI
MVI
MVI
MVI
MVI
06
OE
16
lE
26
2E
36
3E
04
OC
14
1C
'.:>4
2C
34
3C
INR
INR
INR
INR
INR
INR
INR
INR
03
13
23
33
INX
INX
INX
INX
~
•
~
CD
C4
CC
04
DC
E4
EC
F4
FC
CALL
CNZ
CZ
CNC
CC
CPO
CPE
CP
CM
Adr
Ace
IMMEDIATE*
B.
C.
O.
E.
H.
L.
M.
A.
INCREMENT**
08
RETURN
CALL
C6
CE
06
08 DE
E6
EE
F6
FE
AOI
ACI
SUI
SBI
ANI
XRI
ORI
CPI
08
DECREMENT**
C9
CO
G8
DO
08
EO
E8
FO
F8
RET
RNZ
RZ
RNC
RC
RPO
RPE
RP
RM
IMMEDIAT~
01
11
21
31
LXI
LXI
LXI
LXI
ACCUMULATOR*
C7
CF
07
OF
E7
EF
F7
FF
07
OF
17
IF
58
59
5A
5B
5C
50
5E
5F
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
E,B
E,G
E,D
E,E
E,H
E,L
E,M
E,A
80
81
82
83
84
85
86
87
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
B
C
0
E
H
L
M
A
AB
AC
AD
AE
AF
XRA B
XRA C
XRA 0
XRA E
XRA H
XRA L
XRA M
XRA A
60
61
62
63
64
65
66
67
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
H,B
H,C
H,D
H,E
H,H
H,L
H,M
H,A
88
89
8A
8B
8C
80
8E
BF
ADC
AOC
AOC
ADC
AOC
ADC
AOC
ADC
B
C
0
E
H
L
M
A
BO
Bl
B2
B3
B4
B5
B6
B7
ORA
ORA
ORA
ORA
ORA
ORA
ORA
ORA
B
G
0
E
H
L
M
A
B8
B9
BA
BB
BC
BD
BE
BF
CMP
CMP
CMP
CMP
CMP
CMP
CMP
CMP
B
C
0
E
H
L
M
A
RST 0
RST 1
RST 2
RST 3
RST 4
RST 5
RST 6
RST 7
H,
sp,
DOUBLE ADD!
09 DAD B
19 DAD 0
29 DAD H
39 DAD SP
E5
F5
PUSH
PUSH
PUSH
PUSH
B
0
H
PSW
C1
01
El
Fl
POP B
POP 0
POP H
POP PSW'
E3
F9
XTHL
SPHL
SPECIALS
B
L
M
A
OA
lA
2A
3A
LOA X
lOAX
LHLD
LOA
B
D
Adr
Adr
B
0
H
SP
OB
lB
2B
3B
OCX
OCX
OCX
OCX
B
0
H
SP
02
12
22
32
STAX
STAX
SHLO
STA
B
0
Adr
Adr
C
LOAD/STORE
constant, or logicaliarithmetic expression that evaluates
to an B bit data quantity.
all Flags (C.l.S,P) affected
RLC
RRC
RAL
RAR
CONTROL
NOP
HLT
01
EI
STACK OPS
B} C5
0, 016 05
25
20
35
3D
H
10
MOVE (contI
LOAD
0
E
H
L
M
A
05
OD
15
ROTATE+
00
76
F3
FB
OCR
OCR
OCR
OCR
OCR
OCR
OCR
OCR
B
C
0
E
RESTART
EB
27
2F
37
3F
XCHG
OAA'
CMA
STCt
CMC+
INPUT/OUTPUT
03 OUT DB
DB IN
08
016
t
MOVE
40
41
42.
43
44
45
46
47
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
B.B
B,C
B,D
B,E
B,H
B,L
B,M
B,A
6B
69
6A
6B
6C
60'
6E
6F
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
L,B
L,C
L,D
L,E
L,H
L,L
L,M
L,A
90
91
92
93
94
95
96
97
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
B
C
0
E
H
L
M
A
48
49
4A
4B
4C
40
4E
4F
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
C,B
C,C
C,D
C.E
C,H
C,L
C,M
70
71
72
73
74
75
MOV
MOV
MOV
MOV
MOV
MOV
M,B
M,C
M,O
M,E'
M,H
M,L
GA
77
MOV MA
98
99
9A
9B
9C
90
9E
9F
SBB
SBB
SBB
SBS
SBB
SBB
SBB
SBB
B
C
0
E
H
L
M
A
50
51
52
53
54
55
56
57
MOV
MOV
MOV
MGV
MOV
MOV
MOV
MOV
O,B
O,C
0,0
D,E
O,H
O,L
O,M
O,A
78 MOV A,B
79 MOV A,C
7A MOV A,O
7B MOV A,E
7C MOV A,H
70 MOV A,L
7E MOV A,M
7F MOV A,A
AO
Al
A2
A3
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
B
C
0
E
H
L
M
A
constant, or 10gicaVarithmetic expression that evaluates
to a 16 bit data quantity.
= only CARRY affected
=
APPENDIX II
\
--------------
A4
A5
A6
A7
CONSTANT
DEFINITION
A8
A9
AA
OBDH
lAH f Hex
105D}
.
105 Decimal
720} Octal
720
11011B} .
00110B Binary
'TEST' }
'A' 'B' ASCII
OPERATORS
+,-
PSEUDO
INSTRUCTION
STANDARD
SETS
ORG Adr
END
EOU 016
A SET
B SET
C SET
0
SET
E SET
H SET
L SET
M SET
SP SET
PSWSET
DS
DB
OW
016
DB [ 1
016 [ 1
~
I
0
2
3
4
5
6
6
6
Adr = 16 bit address
•• = all Flags except CARRY affected;
(exception: INX & OCX affect no Flags)
© Processor Technology Corp.
\
00
01
02
03
04
05
06
07
08
09
OA
DB
OC
00
OE
OF
10
11
12
13
·14
lS
16
17
18
19
1A
lB
lC
NOP
LXI
STAX
INX
INR
OCR
MVI
RLC
10
lE
1F
20
21
22
23
24
25
26
27
08
=
B,016
B
B
B
B
B.08
DAD
LDAX
OCX
INR
OCR
MVI
RRC
B
B
B
C
C
C.08
LXI
STAX
INX
INR
OCR
MVI
RAL
0.016
0
0
0
0
0.08
DAD
LOAX
OCX
INR
OCR
MVI
RAR
0
0
0
E
LXI
SHLO
INX
INR
OCR
MVI
OAA
H.016
Adr
H
H
H
H.08
E
E.08
28
29
2A
2B
2C
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
DAD
LHLO
OCX
INR
OCR
MVI
CMA
H
Adr
H
L
L
L,08
LXI
STA
INX
INR
OCR
MVI
STC
SP,016
Adr
SP
M
M
M,08
DAD
LOA
OCX
INR
OCR
Mill
CMC
MOV
MOV
MaV
MOV
MaV
MOV
MOV
MOV
MOV
MOV
MaV
MOV
MOV
MOV
MOV
MOV
SP
Adr
SP
A
A
A. 08
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
50
5E
Si60
B,B
B,C
B,O
B.E
B,H
B,L
8.M
S,A
C,B
C,C
C,O
C.E
C,H
C,L
C,M
C,A
61
62
63
64
65
66
67
68
69
SA
68
6C
60
6E
6F
70
71
72
73
74
75
76
77
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
HLT
MOV
O,B
O,C
0,0
O,E
O,H
O,L
O,M
O,A
E,B
E.C
E,O
E,E
E,H
E.L
E,M
E,A
H.B
H.C
H.O
H.E
H.H
H,L
H.M
H.A
L,B
L,C
L,O
L,E
L,H
L.L
L,M
L,A
M,B
M,C
M.O
M,E
M.H
M,L
M,A
constant, or logical/arithmetic expression that evaluates
to an 8 bit data quantity.
78 MOV A,B
79 MOV A,C
7A MOV A,O
7B MOV A,E
7C MOV A,H
70 MOV A,L
7E MOV A,M
7F MOV A,A
80 ADD B
81 ADD C
82 ADD 0
83 ADD E
84 ADD H
85 ADD L
86 ADD M
87 ADD A
88 AOC B
89 AOC C
8A AOC 0
SB AOC E
8C AOC H
80 AOC L
8E AOC M
8F AOC A
90 SUB B
91 SUB C
92 SUB 0
93 SUB E
94 SUB H
95 SUB L
96 SUB M
97 SUS A
98 SBB B
99 SBB C
9A SBS 0
9B SSB E
9C SBB H
90 SBB L
9E SSB M
9F SSB A
016
=
AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
SF
CO
C1
C2
C3
C4
C5
C6
C7
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
XRA
XRA
XRA
XRA
XRA
XRA
XRA
XRA
ORA
ORA
ORA
ORA
ORA
ORA
ORA
ORA
CMP
CMP
CMP
CMP
CMP
CMP
CMP
CMP
RNZ
POP
JNZ
JMP
CNZ
PUSH
AOI
RST
B
C
0
E
H
L
M
A
B
C
0
E
H
L
M
A
B
C
0
E
H
L
M
A
B
C
0
E
H
L
M
A
B
Adr
Adr
Adr
B
08
0
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
04
05
06
07
08
09
OA
DB
DC
DO
DE
OF
EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
RZ
RET
JZ
CZ
CALL
ACI
RST
RNC
POP
JNC
OUT
CNC
PUSH
SUI
RST
RC
Adr
Adr
08
1
0
Adr
08
Adr
0
08
2
XRI
RST
CPI
RST
08
7
08
HEX-ASCII TABLE
3
Non-Printing
H
Adr
Adr
H
08
4
Adr
Adr
08
5
constant, or logical/arithmetic expression that evaluates
to a 16 bit data quantity.
APPENDIX II
RP
POP PSW
JP
Adr
01
CP
Adr
PUSH PSW
ORI
08
RST 6
RM
SPHL
JM
Adr
EI
Adr
CM
Adr
08
Adr
JC
IN
CC
SBI
RST
RPO
POP
JPO
XTHL
CPO
PUSH
ANI
RST
RPE
PCHL
JPE
XCHG
CPE
FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF
00
07
09
OA
OB
OC
00
11'
12
13
14
lS
70
7F
Adr
NULL
BELL
TAB
LF
VT
FORM
CR
X-ON
TAPE
X-OFF
ESC
ALT MODE
RUB OUT
=
16 bit address
HEX-ASCII
Printing
0
30
1
31
32
2
3
33
4
34
35
5
6
36
7
37
38
8
39
9
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
A
B
C
0
E
F
G
H
I
J
K
L
M
N
0
P
Q
R
S
T
U
V
W
X
Y
Z
TABLE
Characters
@
40
space
20
21
!
22
23
#
24
$
~/o
25
26
&
27
28
29
2A
2B
+
2C
20
2E
2F
3A
3B
3C
<
3D
3E
>
?
3F
5B
5G
50
5E
(,~)
5F
H
PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
APPENDIX III
STANDARD COLOR CODE FOR RESISTORS AND CAPACITORS
COLOR
Black
Brown
Red
Orange
Yellow
Green
Blue
Violet
Gray
White
Gold
Silver
No Color
SIGNIFICANT
FIGURE
DECIMAL
MULTIPLIER
0
1
2
3
4
5
6
7
8
.g
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
0.1
0.01
-
-
---
*App1ies to capacitors only.
AllI-1
TOLERANCE
(%»
VOLTAGE
RATING*
--
5
10
20
100
200
300
400
500
600
700
800
gOO
1000
2000
500
PROCESSOR TECHNOLOGY. CORPORATION
APPENDIX IV
Sol TERMINAL COMPUTER™
LOADING DIP (DUAL IN-LINE PACKAGE) DEVICES
Most DIP devices have their leads spread so that they can not be
dropped straight into the board. They must be "walked in" using the
following procedure:.
(1) Orient the device properly. Pin 1 isindlcated by a small embossed dot on the top surface of the device at one corner.
Pins are numbered counterclockwise from pin 1.
(2) Insert the pins on one side of the device into their holes on
the printed circuit card. Do not press the pins all the way
in, but stop when they are just starting to emerge from the
opposite side of the card.
(3) Exert a sideways pressure on the pins at the other side of
the device by pressing against them where they are still wide
below the bend. Bring this row of pins into alighrnent with
its holes in the printed circuit card and insert them an equal
distance, until they begin to emerge.
(4) Press the device straight down until it seats on the points
where the pins widen.
(5) Turn the card over and select two pins at opposite corners of
the device. Using a fingernail or a pair of long-nose pliers,
push these pins outwards until they are bent at a 45° angle
to the surface of the card. This will secure the device
until it is soldered.
SOLDERING TIPS
(1) Use a low-wattage iron--25 watts is good. Larger irons run
the risk of burning the printed-circuit board. Don't try to
use a soldering gun, they are too hot.
(2) Use a small pointed tip and keep it clean. Keep a damp piece
of sponge by the iron and wipe the tip on it after each use.
(3) Use 60-40 rosin-core solder ONLY.
der or externally applied fluxes.
solder you can get.
NOTE:
DO NOT use acid-core solUse the smallest diameter
DO NOT press the top of the iron on the pad or
trace. This will cause the trace to "liftll off
of the board which will result in permanent damage.
(4) In soldering, wipe the tip, apply a light coating of new
solder to it, and apply the tip to both parts of the joint,
that is, both the component lead and the printed-circuit pad.
Apply the solder against the lead and pad being heated, but
not directly to the tip of the iron. Thus, when the solder
AIV-l
PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
APPENDIX IV
melts the rest of the joint will be hot enough for the solder
to "take", (i.e., form a capillary film) .
(5) Apply solder for a second or two, then remove the solder and
keep the iron tip on the joint. The rosin will bubble out.
Allow about three or four bubbles, but don't keep the tip
applied for more than ten seconds.
(6) Solder should follow the contours of the original joint. A
blob or lump may well be a solder bridge, where enough solder
has been built upon one conductor to overflow and "take" on
the adjacent conductor. Due to capillary action, these solder bridges look very neat, but they are a constant source of
trouble when boards of a high trace density are bing soldered.
Inspect each integrated circuit and component after
soldering for bridges.
(7) To remove solder bridges, it is best to use a vacuum "solder
puller" if one is available.
If not, the bridge can be reheated with the iron and the excess solder "pulled" with the
tip along the printed circuit traces until the lump of solder
becomes thin enough to break the bridge. Braid-type solder
remover, which causes the solder to "wick up" away from the
joint when applied to melted solder, may also be used.
INSTALLING AUGAT PINS
Augat pins are normally supplied on carriers (e.g., 8-pin and 16-piri
carriers).
In many cases the PC board layout permits Augat pins to
be installed while still attached to the carrier or a portion of the
carrier.
In other cases the pins must be installed singly.
To install two or more pins that are still attached to the carrier,
proceed as follows:
NOTE
It is perfectly alright to appropriately
cut a carrier to accommodate the installation. For·example, an 8-pin carrier
can be cut in half (4 pins each) across
the short dimension to fit a 4-pin, 4corner layout.
It may also be cut in
half along the long dimension to fit a
4-pin, inline layout.
(1) Insert pins in the mounting holes from the front (component)
side of board.
(The carrier will hold the pins p~rpendicu
lar to the board~)
(2) Solder all pins from back (solder) side of board so the solder
"wicks up" to the front side.
AIV-2
PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
APPENDIX IV
(3) Check for solder bridges.
(4) Remove carrier.
To install single pins, proceed as follows:
(1) Hold board between two objects so that it stands on edge.
(2) Insert pins in the mounting holes from front (component) side
of board.
(3) Solder pins from back (solder) side of board so the solder
"wicks up" to the front side.
(This will hold the pins firmly in place.)
(4) Insert a component lead into one pin and reheat the solder.
Using the component lead, adjust pin until it is perpendicular to board. Allow solder to cool while holding the pin as
steady as possible. Remove component lead. Repeat this
procedure with other pins.
NOTE
If cooled solder is mottled or crystallized, a "cold joint" is indicated, and
the solder should be reheated.
(5) Check each installation for cold joints and solder bridges.
AIV-3
PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
APPENDIX V
O
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PROCESSOR TECHNOLOGY CORPORATION
APPENDIX V
Sol TERMINAL COMPUTER™
21L02 or 91L02
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PROCESSOR TECHNOLOGY CORPORATION
APPENDIX V
Sol TERMINAL COMPUTER™
4027
4024
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1-04B
PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
APPENDIX V
6011
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PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
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APPENDIX V
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PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
APPENDIX V
7474
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PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
APPENDIX V
74155
74138
DATA OUTPUll
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PROCESSOR TECHNOLOGY CORPORATION
APPENDIX V
Sol TERMINAL COMPUTER™
74173
74166
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AV-8
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PROCESSOR TECHNOLOGY CORPORATION
Sol TERMINAL COMPUTER™
APPENDIX V
8080
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IN 11
lMIA
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REPRINTED FROM OCTOBER 1975 BYTE WITH PERMISSION
Interface
Television
Anyone with a bunch of memory circuits, control logic and
a wire wrap gun can whip up a digital video generator with
TTL output levels. The problem as I see it is to get that digital
video signal into a form that the TV set can digest. The care
and feeding of digital inputs to the TV set is the subject of
Don Lancaster's contribution to BYTE 2 - an excerpt from
his forthcoming book, TV Typewriter Cookbook, to be
published by Howard W. Sams, Indianapolis, Indiana.
... CARL
We can get between a TV
typewriter and a television
style display system either by
an rf modulator or a direct
video method.
I n the rf modulator
method, we build a
miniature, low power, direct
wired TV transmitter that
clips onto the antenna
terminals of the TV set. This
has the big advantage of
letting you use any old TV
set and ending up with an
essentially free display that
can be used just about
anywhere.
No set
modifications are needed, and
you have the additional
advantage of automatic safety
isolation and freedom from
hot chassis shock problems.
There are two major
restrictions to the rf
modulator method. The first
of these is that transmitters
of this type must meet
by
Don Lancaster
Box 1112
Parker AZ 85344
Fig. 1. Standard video interface levels. (Source impedance
WHITE
DOT-
LEVEL
certain exactly spelled out
FCC regulations and that
s y stem type approval is
required. The second
limitation is one of
bandwidth. The best you can
possibly hope for is 3.5 MHz
for black and white and only
3 MHz for color, and many
economy sets will provide far
less. Thus, long character Ii ne
lengths, sharp characters, and
premium (lots of dots)
character generators simply
aren't compatible with
clip-on rf entry.
I n the direct video
method, we enter the TV set
immediately following its
video detector but before
sync is picked off. A few
premium TV sets. and all
monitors already have a video
input directly available, but
'these are still expensive and
rare. Thus, you usually have
to modify your TV set, either
= 72 or 100 Ohms.)
- - - - - 2VOLTS
(OPTIONAL
GRAY)
fl. OV
BLACK LEVEL
- - - - - - - - SYNC LEVEL---------
0.5 VOLTS
AVI-1
adding a video input and a
selector switch or else
dedicating the set to exclusive
TV typewriter use. Direct
video eliminates the
bandwidth restrictions
provided by the tuner, i-f
strip, and video detector
filter. Response can be
further extended by removing
or shorting the 4.5 MHz
sou nd trap and by other
modifications to provide us
with longer line lengths and
premiu m characters. No FCC
approval is needed, and
several sets or monitors are
easily driven at once without
complicated distribution
problems.
There are two limitations
to the direct video technique.
One is that the set has to be
modified to provide direct
video entry. A second, and
far more severe, restriction, is
that many television sets are
"hot chassis" or ac-dc sets
with one side of their chassis
connected to the power line.
These sets introduce a severe
shock hazard and cannot be
used as TV typewriter video
entry displays unless some
isolation technique is used
with them. If the TV set has a
power transformer, there is
usually no hot chassis
proble m. Transistor television
sets and Ie sets using no
vacuum tubes tend to have
power transformers, as do
older premiu m tube type sets.
All others (around half the
sets around today) do not.
Direct Video Methods
With either interface
approach, we usually start by
getting the dot matrix data,
blanking, cursor, and sync
signals together into one
composite video signal whose
form is useful to monitors
and TV sets. A good set of
standards is shown in Fig. 1.
The signal is dc coupled and
always positive going. Sync
tips are grounded and blacker
than black. The normal open
circuit black level is positive
by one-half a volt, and the
white level is two volts
positive. I n most TV camera
systems, intermediate levels
bet ween the half volt black
level and the two volt white
level will be some shade of
gray, proportionately brighter
with increasing positive
voltage. With most TV
typewriter systems, only the
three states of zero volts
(sync), half a volt (black),
and two volts (white dot)
would be used. One possible
exception would be an
additional one volt dot level
for a dim but still visible
portion of a message or a
single word.
The usual video source
impedance is either 72 or 100
Ohms. Regardless of how far
we travel with a composite
video output, some sort of
shielding is absolutely
essential.
For short runs from board
to board or inside equipment,
tightly twisted conductors
should be OK, as should
properly guarded PC runs.
Fully shielded cables should
be used for interconnections
between the TVT and the
monitor or TV set, along with
other long runs. As long as
the total cable capacitance is
less than 500 pF or so (this is
around 18 feet of RG178-U
miniature coax), the receiving
end of the cable need not be
terminated in a 72 or 100
Ohm resistor. When
terminated cable systems are
in use for long line runs or
mUltiple outputs, they should
be arranged to deliver the
signal levels of Fig. 1 at their
output under termination.
Generally, terminated cable
systems should be avoided as
they need extra in the way of
drivers and supply power.
The exact width of the
horizontal and vertical sync'
pulses isn't usually too
important, so long as the
shape and risetime of these
pulses are independent of
position control settings and
power supply variations. One
exception to this is when
you're using a color receiver
and a color display. Here, the
horizontal sync pulse should
be held closely to 5.1
microseconds, so the
receiver's color burst
sampling does in fact
intercept a valid color burst.
More on this later.
Intentional Smear
Fig. 2 shows us a typical
composite video driver using
a 4066 quad analog switch. It
gives us al 00 Ohm output
impedance and the proper
signal levels. Capacitor Cl is
used to purposely reduce the
video rise and fall times. It is
called a smearing capacitor.
Why would we want to
further reduce the bandwidth
and response of a TV system
that's already hurting to
begin with? In the case of a
quality video monitor, we
wouldn't. But if we're using
an ordinary run-of-the-mill
TV set, particularly one using
rf entry, this capacitor can
Fig. 2. Analog switch combiner generates composite video.
1[+5
-5
H SYNC
.JL+5
-5
CURSOR
l..f+5
-5
V SYNC
VIDEO DOTS
+5KWHITE)
-5
IK
CI
SMEARING
CAPACITOR
(SEE TEXT)
4066 (CMOS)
ANALOG SWITCH
680
~.--------~ VIDEO OUT
100
SYNC·OV
8LACK.0.4V
WHITE·I.5V
very much improve the
display legibility and
contrast. Why?
Because we are interested
in getting the most legible
character of the highest
contrast we can. This is not
necessarily the one having the
sharpest dot rise and fall
times. Many things interact to
determine the upper video
response of a TV display.
These include the tuner
settings and the i-f response
and alignment, the video
detector response, video
peaking, the sound trap
setting, rf cable reflections,
and a host of other responses.
Many of these stages are
underdamped and will ring if
fed too sharp a risetime
input, giving us a ghosted,
AVI-2
shabby, or washed out
character. By reducing the
video bandwidth going into
the system, we can move the
dot matrix energy lower in
frequency, resulting in
cleaner characters of higher
contrast.
For most TV displays,
intentional smearing will help
the contrast, legibility, and
overall appearance. The
ultimate limit to this occurs
when the dots overlap and
become illegible. The
Fig. 3. Block diagram of typical Band W television.
ANTENNA
SPEAKER
optimum amount of
intentional smear is usually
the value of capacitance that
is needed to just close the
inside of a "W" presented to
the display.
I
\---
Adding a Video Input
Video inputs are easy to
add to the average television
set, provided you follow
some reasonable cautions.
First and foremost, you must
have an accurate and
complete schematic of the set
to be modified, preferably a
Sams Photofact or something
similar. The first thing to
check is the power supply on
the set. If it has a power
transformer and has the
chassis properly safety
isolated from the power line,
it's a good choice for a TVT
monitor. This is particularly
true of recent small screen,
solid state portable TV sets.
On the other hand, if you
have a hot chassis type with
one side of the power line
connected to the chassis, you
should avoid its use if at all
possible. If you must use this
type of set, be absolutely
certain to use one of the
safety techniques outlined
later in Fig. 8.
A block diagram of a
typical TV set appears in Fig.
3. UHF or VHF signals
picked up by the tuner are
downconverted in frequency
to a video i-f frequency of 44
MHz and then filtered and
amplified. The output of the
video i-f is transformer
coupled to a video detector,
most often a small signal
germanium diode. The video
detector output is filtered to
AVI-3
remove the carrier and then
routed to a video amplifier
made up of one or more
tubes or transistors.
At some point in the video
amplification, the black and
white signal is split three
ways. First, a reduced
bandwidth output routes
sync pulses to the sync
separator stage to lock the
set's horizontal and vertical
scanning to the video. A
second bandpass output
sharply filtered to 4.5 MHz
extracts the FM sound
sub carrier and routes this to a
sound i-f amplifier for further
processing. The third output
is video, which is strongly
amplified and then
capacitively coupled to the
cathode of the picture tube.
The gain of the video
amplifier sets the contrast of
the display, while the bias
setting on the cathode of the
picture tube (with respect to
its grounded control grid) sets
the display brightness.
Somewhere in the video
amplifier, further rejection of
the 4.5 MHz sound subcarrier
is usually picked up to
minimize
picture
interference. This is called a
sound trap. Sound traps can
be a series resonant circuit to
ground, a parallel resonant
circuit in the video signal
path, or simply part of the
transformer that is picking
off the sound for more
processing.
the video detector output
is usually around 2 volts peak,
to peak and usually subtracts
from a white level bias
setting. The stronger the
signal, the more negative the
swing, and the blacker the
picture. Sync tips are blacker
than black, helping to blank
the display during retrace
times.
and thus higher gain to high
frequency video signals.
Note particularly the
biasing of the video driver. A
bias network provides us with
a stable source of 3 volts. In
the absence of input video,
this 3 volts sets the white
level of the display, as well as
establishing proper bias for
both stages. As an increasing
signal appears at the last
video output transformer, it
is negatively rectified by the
video detector, thus lowering
the 3 volts proportionately.
The stronger the signal, the
blacker the picture. Sync will
be the strongest of all, giving
us a blacker than black bias
level of only one volt.
The base of our video
driver has the right sensitivity
we need for video entry,
Fi.g. 4 shows us the typical
video circuitry of a transistor
black and white television.
Our basic circuit consists of a
diode detector, a unity gain
emitter follower, and a
variable gain video output
stage that is capacitively
coupled to the picture tube.
The cathode bias sets the
brightness, while the video
gai n sets the contrast.
Amplified signals for sync
and sound are removed from
the collector of the video
driver by way of a 4.5 MHz
resonant transformer for the
sound and a low pass filter
for the sync. A parallel
resonant trap set to 4.5 MHz
eliminates sound interference.
Peaking coils on each stage
extend the bandwidth by
providing hig~er impedances
accepting a maximum of a 2
volt peak to peak signal. It
also has the right polarity, for
a positive going bias level
means a whiter picture. But,
an unmodified set is already
biased to the white level, and
if we want to enter our own
video, this bias must be
shifted to the black level.
We have a choice in any
TV of direct or ac coupling of
our input video. Direct
coupling is almost always
better as it eliminates any
Fig. 4. Typical video circuitry of transistor B and W TV set.
+12V
BRIGHTNESS
~
IK
+80o---~~-----,
.001
.. SYNC
.-----4~-
+150V
4.5MHz
SOUND
PICKOFF
3V(WHITE)
I V(SYNC)
LAST VIDEO
I-F XFMR
rSOUND
lOOK
6800
5V~
VIDEO
DETECTOR
VIDEO
DRIVER
5
(2.4V)
+12V
250ILH
(PEAKING)
1.5K
470
I
470
4.5MHz
SOUND
TRAP
(3V) " BIAS
SOURCE
~"2KV
47
.1~
CONTRAST
AVI-4
PICTURE TUBE
Fig. 5. Direct coupled video uses 1.2 volt offset of Darlington
transistor as bias.
+12
+12
shading effects or any change
of background level as
add i t ion al characters are
added to the screen. Fig. 5
shows how we can direct
couple our video into a
transistor black and white set.
We provide a video input,
usually a BNC or a phono
jack, and route this to a PNP
Darlington transistor or
transistor pair, borrowing
around 5 mils from the set's
+12 volt supply. This output
is routed to the existing video
driver stage through a SPDT
switch that either picks the
video input or the existing
video detector and bias
network.
The two base-emitter
diode drops in our Darlington
transistor add up to a 1.2 volt
positive going offset; so, in
the absence of a video input
or at the base of a sync tip,
the video driver is biased to a
blacker than black sync level
of 1.2 volts. With a white
video input of 2 volts, the
video driver gets biased to its
usual 3.2 volts of white level.
Thus, our input transistor
provides just the amount of
offset we need to match the
white and black bias levels of
our video driver. Note that
the old bias network is on the
other side of the switch and
does nothing in the video
position.
Two other ways to offset
our video input are to use
two ordinary transistors
connected in the Darlington
configuration, or to use one
transistor and a series diode
L
EXISTING
DETECTOR 8c
BIAS
NEW
CIRCUITRY
2.2K
ALTERNATE
USING TWO
REGULAR
TRANSISTORS
1.2V (SYNC) RF
3.2V(WHITE)
2.2K
VIDEO
DARLINGTON
TRANSISTOR
PAIR
MPSA65
VIDEO
INPUT
IN914
ALTERNATE
USING TRANSISTOR AND DIODE
to pick up the same amount
of offset, as shown in Fig. 5.
If more or less offset is
needed, diodes or transistors
can be stacked up further to
pick up the right amount of
offset.
The important thing is
that the video driver ends up
with the same level for white
bias and for black bias in
either position of the switch.
Ac or capacitively coupled
video inputs should be
avoided. Fig. 6 shows a
typical circuit. The TV's
ex i s ti ng bias network is
lowered in voltage by adding
a new parallel resistor to
ground to give us a voltage
that is 0.6 volts more positive
than the blacker than black
sync tip voltage. For instance,
with a 3 volt white level, and
Fig. 6. Ac coupled video needs shift of bias to black level plus a
clamping diode.
EXISTI'IG
DETECTOR
RFL ..P---.---t-l
*'
EXISTING
VIDEO
DRiVER
VIDEO
IN914
CLAMP
*
1.5K
(1.6V) 470
+ 12 O--w...---+--4I>---4p'-'VVIt----,
*470
0
""""--V-ID-oE~
.......
*New components.
AVI-5
2 volt peak to peak video, the
sync tip voltage would be 1
volt; the optimum bias is then
1.6 volts. Input video is
capacitively coupled by a
fairly large electrolytic
capacitor in parallel with a
good high frequency
capacitor. This provides for a
minimum of screen shading
and still couples high
frequency signals properly. A
clamping diode constantly
clamps the sync tips to their
bias value, with the 0.6 volt
drop of this diode being
taken out by the extra 0.6
volts provided for in the bias
network. This clamping diode
automatically holds the sync
tips to their proper value,
regardless of the number of
white dots in the picture.
Additional bypassing of the
bias network by a large
electrolytic may be needed
for proper operation of the
clamping diode, as shown in
Fig. 6. Note that our bias
network is used in both
switch positions - its level is
shifted as needed for the
direct video input.
Tube type sets present
about the same interface
problems as the solid state
versions do. Fig. 7 shows a
typical direct coupled tube
interface. In the unmodified
Fig. 7. Direct coupled video added to tube type Band Wtelevision.
+140
PEAKING
...----SYNC
4.7K
IODxa
VIDEO
DETECTOR
VIDEO-AMP
~----'VI/II---o+
CRT
L..--nl.:.;..·I - _.. CATHODE
CONTRAST
VIDEO
INPUT
*
IK
NEW CATHODE SELF-BIAS
SHIFTS TO SYNC LEIIEL IN
VIDEO POSITION
"'New components.
circuit, the white level is zero
volts and the sync tip black
level is minus two volts. If we
can find a negative supply
(scarce in tube type circuits),
we could offset our video in
the negative direction by two
volts to meet these bias levels.
Instead of this, it is usually
possible to self bias the video
amplifier to a cathode voltage
of +2 volts. This is done by
breaking the cathode to
ground connection and
adding a small resistor (50 to
100 Ohms) between cathode
and ground to get a cathode
voltage of +2 volts. Once this
value is found, a heavy
electrolytic bypass of 100
microfarads or more is placed
in parallel with the resistor.
Switching then grounds the
cathode in the normal rf
mode and makes it +2 volts in
the video entry mode.
In the direct video mode, a
sync tip grounded input
presents zero volts to the
grid, which is self biased
minus two volts with respect
to the cathode. A white level
presents +2 volts to the grid,
which equals zero volts grid
to cathode.
Should there already be a
self bias network on the
cathode, it is increased in
value as needed to get the
black rather than white level
bias in the direct video mode.
Hot Chassis Problems
There is usually no shock
hazard when we use c1ip-on rf
entry or wh~n \;Ve use a direct
video jackon a transformerpowered TV. A very severe
. shock hazard can exist if we
use di~ect video entry with a
TV set having one side of the
AVI-6
power line connected to the
chassis. Depending on which
way the line cord is plugged
in, there is a 50-50 chance of
the hot side of the power line
being connected directly to
the chassis.
Hot chassis sets,
particularly older, power
hungry tube versions, should
be avoided entirely for direct
video entry. If one absolutely
must be used, some of the
suggestions of Fig. 8 may ease
the hazard. These include
using an isolation
transformer, husky
bac k-to-back filament
tra nsfor me rs, three wire
power systems, optical
coupling of the video input,
and total package isolation.
Far and away the best route
is simply never to attempt
direct video entry onto a hot
chassis TV.
Making the Conversion
Fig. 9 sums up how we
modify a TV for direct video
entry. Always have a
complete schematic on hand,
and use a transformer style
TV set if at all possible. Late
models, small screen, medium
to high quality solid state sets
are often the best· display
choice. Avoid using junk sets,
particularly very old ones.
Direct coupling of video is far
preferable to ac capacitor
coupling. Either method has
to maintain the black and
white bias levels on the first
video amplifier stage. A shift
of the first stage quiescent
bias from normally white to
normally black is also a must.
Use short, shielded leads
between the video input jack
and the rest of the circuit. If
a changeover switch is used,
keep it as close to the rest of
the video circuitry as you
possibly can.
Extending Video and Display
Bandwidth
By using the direct video
input route, we eliminate any
bandwidth and response
restrictions of an rf
Fig. 8. Getting Around a Hot Chassis Problem.
Hot chassis problems can be avoided entirely by
using only transformer-powered TV circuits or
by using clip-on rf entry. If a hot chassis set
must be used, here are some possible ways
around the problem:
1. Add an isolation transformer.
modulator, the tuner, video
i -f strip, and the video·
detector filter. Direct video
entry should bring us to a 3
MHz bandwidth for a color
set and perhaps 3.5 MHz for a
black and white model, unless
we are using an extremely
bad set. The resultant 6 to 7
million dot per second rate is
adequate for short character
lines of 32, 40, and possibly
48 characters per line. But
the characters will smear and
be illegible if we try to use
longer line lengths and
premium {lots of dots)
character generators on an
ordinary TV. Is there
anything we can do to the set
to extend the video
bandwidth and display
response for these longer line
lengths?
In the case of a color TV,
the answer is probably no.
The video response of a color
set is limited by an essential
delay line and an essential
3.58 MHz trap. Even if we
were willing to totally
separate the chrominance and
luminance channels, we'd still
be faced with an absolute
limit set by the number of
holes per horizontal line in
the shadow mask of the tube.
This explains why video color
displays are so expensive and
so rare. Later on, we'll look
at What's involved in adding
color to the shorter line
lengths.
With a black and white
TV, there is often quite a bit
A 110 volt to 110 volt isolation transformer whose wattage exceeds that of the
set may be used. These are usually expensive, but a workable substitute can be made
by placing two large surplus filament transformers back to back. For instance, a pair
of 24 volt, 4 Amp transformers can handle
arou nd 100 Watts of set.
2. Use a three wire system with a solid ground.
Three prong plug wlrrng, properly
polarized, will force the hot chassis connection to the cold side of the power line. This
protection is useful only when three wire
plugs are used in properly wired outlets. A
severe shock hazard is reintroduced if a
user elects to use an adaptor or plugs the
system into an unknown or improperly
wired outlet. The three wire system shou Id
NOT be used if anyone but yourself is ever
to use the system.
3. Optically couple the input video.
Light emitting diode-photocell pairs are
low in cost and can be used to optically
couple direct video, completely isolating
the video input from the hot chassis. Most
of these optoelectronic couplers do not
have enough bandwidth for direct video
use; the Litronix IL-l00 is one exception.
Probably the simplest route is to use two
separate opto-isolators, one for video and
one for sync, and then recombine the
signals inside the TV on the hot side of the
circuit.
4. Use a totally packaged and sealed system.
AVI-7
If you are only interested in displaying
messages and have no other input/output
devices, you can run the entire circuit hot
chassis, provided everything is sealed inside
one case and has no chassis-to-peopleaccess. Interface to teletypes, cassettes,
etc., cannot be done without additional
isolation, and servicing the circuit presents
the same shock hazards that servicing a hot
chassis TV does.
we can do to present long
lines of characters, depending
on what set you start. out
with and how much you are
willing to modify the set.
The best test signal you
can use for bandwidth
extension is the dot matrix
data you actually want to
display, for the frequency
response, time delay, ringing,
and overshoot all get into the
act. What we want to end up
with is a combination that
gives us reasonably legible
characters.
A good oscilloscope (15
MHz or better bandwidth) is
very useful during bandwidth
extension to show where the
signal loses its response in the
circuit. At any time during
the modification process,
there is usually one response
bottleneck. This, of course, is
what should be attacked first.
Obviously the better a TV
you start with, the easier will
be the task. Tube type gutless
wonders, particularly older
ones, wi II be much more
difficult to work with than
with a modern, small screen,
quality solid state portable.
Several of the things we
can do are watching the
control settings, getting rid of
the sound trap, minimizing
circuit strays, optimizing spot
size, controlling peaking, and
shifting to higher current
operation. Let's take a look
at these in turn.
Control Settings
Always run a data display
at the lowest possible
contrast and using only as
much brightness as you really
need. In many circuits, low
contrast means a lower video
amplifier gain, and thus less
of a gain-bandwidth
restriction.
Eliminate the Sound Trap
The sound trap adds a
notch at 4.5 MHz to the
video response. If it is
eliminated or switched out of
the circuit, a wider video
bandwidth automatically
Fig. 9. How to Add a Direct Video Input to a TV Set.
1.
Get an accurate and complete schematic of
the set - either from the manufacturer's
service data or a Photofact set. Do not try
adding an input without this schematic!
2.
Check the power supply to see if a power
transformer is used. If it is, there will be no
shock hazard, and the set is probably a
good choice for direct video use. If the set
has one side of the power line connected to
the chassis, a severe shock hazard ex ists,
and one of the techniques of Fig. 8 should
be used. Avoid the use of hot chassis sets.
3.
Find the input to the first video amplifier
stage. Find out what the white level and
sync level bias voltages are. The marked or
quiescent voltage is usually the white level;
sync is usually 2 volts less. A transistor TV
will typically have a +3 volt white level and
a +1 volt sync level. A tube type TV will
typically have a zero volt white level and a
-2 volt sync level.
4.
Add a changeover switch using minimum
possible lead lengths. Add an input connector, either a phono jack or the premiu m
BNC type connector. Use shielded lead for
interconnections exceeding three inches in
length.
5.
Select a circuit that couples the video and
biases the first video amplifier stage so that
the white and sync levels are preserved. For
transistor sets, the direct coupled circuits
of Fig. 5 may be used. For tube sets, the
circuit of Fig. 7 is recommended. Avoid the
use of ac coupled video inputs as they may
introduce shading problems and changes of
background as the screen is filled.
6.
Check the operation. If problems with
contrast or sync tearing crop up, recheck
and adjust the white and sync input levels
to match what the set uses during normal rf
operation. Note that the first video stage
must be biased to the white level during rf
operation and to the sync level for direct
video use. The white level is normally two
volts more positive than the sync level.
AVI-8
Fig. 10. Removing the sound trap can extend video bandwidth.
(a) Response
(b) Parallel resonant trap short or bypass.
h
L
h
~F=~~UENCY
WITH SOUND
L-i:
VIDEO
OUTPUT
0UT
FREQUENCY
CONTRAST
(d) Combined trap and
pickoff - open or
remove (series resonant);
short or bypass (parallel
(c) Series resonant trap open or remove.
SOUND I-F
resonant).
4.5MHz
TRAP
SOUND?~
I-F
.
results. Fig. 10 shows us the
response changes and the
several positions for this trap.
G en erally, series resonant
traps are opened and parallel
resonant traps are shorted or
bypassed through suitable
switching or outright
elimination. The trap has to
go back into the circuit if the
set is ever again used for
ordinary program reception.
Sometimes simply backing
the slug on the trap all the
way out will improve things
enough to be useful.
'--
.
Minimizing Strays
One of the limits of the
video bandwidth is the stray
capacitance both inside the
video output stage and in the
external circuitry. If the
contrast control is directly in
the signal path and if it has
long leads going to it, it may
be hurting the response. If
you are using the TV set
exclusively for data display,
can you rearrange the control
location and simplify and
shorten the video output to
picture
tube
interco nn ecti ons?
4.5
MHz
Additional Peaking
Most TV sets have two
peaking networks. The first
of these is at the video
detector output and
compensates for the vestigial
sideband transmission signal
that makes sync and other
low frequency signals double
the amplitude of the higher
frequency ones. The second
of these goes to the collector
or plate of the video output
stage and raises the circuit
impedance and thus the
effective gain for very high
Fig. 11. Adjusting the peaking coil can extend video response.
(a) Circuit.
+
PEAKING
COIL
COLLECTOR
LOAD
~--------~---------'CRT
VIDEO
OUTPUT
TOO MUCH
L TOO LARGE
(b) Response.
~____~~--~r-0PTIMUM
AMPLITUDE
TOO LITTLE
L TOO SMALL
FREQUENCY
AVI-9
frequencies. Sometimes you
can alter this second network
to favor dot presentations.
Fig. 11 shows a typical
peaking network and the
effects of too little or too
much peaking. Note that the
stray capacitance also enters
into the peaking, along with
the video amplifier output
capacitance and the picture
tub e' s input capacitance.
Generally, too little peaking
will give you low contrast
dots, while too much will give
you sharp dots, but will run
dots together and shift the
more continuous portions of
the characters objectionably.
Peaking is changed by increasing or decreasing the
series inductor from its design
value.
Running Hot
Sometimes increasing the
operating current of the video
output stage can increase the
system bandwidth - IF this
stage is in fact the limiting
response, IF the power
supply can handle the extra
current, IF the stage isn't
already parked at its
gain-bandwidth peak, and IF
the extra heat can be gotten
rid of without burning
anything up. Usually, you can
try adding a resistor three
times the plate or collector
load resistor in parallel, and
see if it increases bandwidth
by 1/3. Generally, the higher
the current, the wider the
bandwidth, but watch
carefu II y any dissipation
,limits. Be sure to provide
ex tra ve ntilation and
additional heatsinking, and
check the power supply for
unhappiness as well. For
major changes in operating
current, the emitter resistors
and other biasing components
should
also
be
proportionately reduced in
value.
Spot Size
Even with excellent video
bandwidth, if you have an
out-of-focus, blooming, or
changing spot size, it can
completely mask character
sharpness. Spot size ends up
the ultimate limit to
resolution, regardless of video
bandwidth.
Once again, brightness and
contrast settings will have a
profound effect, with too
much of either blooming the
spot. Most sets have a focus
jumper in which ground or a
positive voltage is selected.
You can try intermediate
values of voltage for
maximum sharpness. Extra
power supply filtering can
sometimes minimize hum and
noise modulation of the spot.
Anything that externally
raises display contrast will let
you run with a smaller beam
current and a sharper spot.
Using circularly polarized
filters, graticule masks, or
simple colored filters can
Fig. 12. Contrast Enhancing
Filter Materials.
Circularly polarized filters:
Polaroid Corp.
Cambridge MA 02139
Anti·reflection filters:
Panelgraphic Corp.
10 Henderson Dr.
West Caldwell NJ 07006
Light control film:
3M Visual Products Div.
3M Center
St. Paul MN 55101
Acrylic plexiglas filter sheets:
Rohm and Haas
Philadelphia PA 19105
Fig. 14. Television Picture
Carrier Frequencies.
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Fig. 13. Standard rf interface levels. Impedance
frequency per Fig. 14.
(
..•••.• 55.25 MHz
•..•.•• 61.25 MHz
.•..•.• 67.25 MHz
•.••.•• 77.25 MHz
.•••.•• 83.25 MHz
3 OOn. Carrier
SYNC TIPS=
100 % AMPLITUDE
4mV RMS TYPICAL
BLACK =
. / 75 % AMPLITUDE
3 mV RMS TYPICAL
o
WHITE= 10% OR
LESS AMPLITUDE
.3mV RMS TYPICAL
minimiZe display washout
from ambient lighting. Fig.
12 lists several sources of
material for contrast
improvement. Much of this is
rather expensive, with pricing
from $10 to $25 per square
foot being typical. Simply
adding a hood and
positioning the display away
from room lighting will also
help and is obviously much
cheaper.
Direct Rf Entry
If we want the convenience of a "free"
display, the freedom from
hot chassis problems, and
"use it anywhere" ability,
direct rf entry is the obvious
choice. Its two big limitations
are the need for FCC type
approval, and a limited video
'bandwidth that in turn limits
the number of characters per
line and the number of dots
per character.
An rf interface standard is
shown in Fig. 13. It consists
of an amplitude modulated
carrier of one of the standard
television channel video
frequencies of Fig. 14.
Channel 2 is most often used
with a 55.250 MHz carrier
frequency, except in areas
where a local commercial
Channel 2 broadcast is
intolerably strong. Circuit
cost, filtering problems, and
stability problems tend to
inc rease wi th increasing
channel number.
The sync tips are the
strongest part of the signal,
representing 100%
modulation, often something
around 4 millivolts rms across
a 300 Ohm Ii ne. The black
level is 75% of the sync level,
or about 3 millivolts for 4
millivolt sync tips. White level
is less than 10% of maximum.
Note that the signal is
weakest when white and
strongest when sync. This is
the exact opposite of the
video interface of Fig. 1.
Rf modulators suitable for
c lip - 0 n r f entry TV
typewriter use are called Class
1 TV Devices by the FCC. A
Class 1 TV device is supposed
to meet the rules and
regulations summarized in
Fig. 15.
Fig. 16 shows us a block
diagram of the essential parts
of a TV modulator. We start
AVI-IO
Fig. 1 S. FCC Regulations on Class
1 TV Devices. More complete
information appears in subpart H
of Part 15 and su bpart F of Part 2
of the Federal Communications
Commission Rules and Regulations. It is available at many large
technical libraries.
A Class 1 TV device generates
a video modulated rf carrier of a
standard television channel
frequency. It is directly
connected to the antenna
terminals of the TV set.
The maximum rms rf voltage
must be less than 6 millivolts
using a 300 Ohm output line.
The maximum rf voltage on
any frequency more than 3 MHz
away from the operating channel
must be more than 30 dB below
the peak in-channel output
voltage.
An antenna disconnect switch
of at least 60 dB attenuation must
be provided.
No user adjustments are
permitted that would exceed any
of the above specifications,
Residual rf radiation from
case, leads and cabinet must be
less than 15 microvolts per meter.
A Class 1 TV device must not
interfere with TV reception.
Type approval of the circuit is
required. A filing fee of $50 and
an acceptance fee of $250 is
involved.
Fig. 16. Block diagram of rf modulator.
FROM
ANTENNA
o
o--~-------------.I
VIDEO
INPUT
,
\
'---
with a stable oscillator tuned
to one of the Fig. 14
frequencies. A crystal
oscillator is a good choice,
and low cost modules are
widely available. The output
of this oscillator is then
amplitude modulated. This
can be done by changing the
bias current through a silicon
small signal diode. One
milliampere of bias current
makes the diode show an ac
and rf impedance of 26
Ohms. Half a mil will look
like 52 Ohms, and so on. The
diode acts as a variable
resistance attenuator in the rf
circuit, whose bias is set and
changed by the video circuit.
Since diode modulators
are non-linear, we can't
simply apply a standard video
signal to them and get a
standard rf signal out. A
differential amplifier circuit
called a video slicer may be
used to compensate for this
non-linearity. The video slicer
provides three distinct
currents to the diode
modulator. One of these is
almost zero for the white
level, while the other two
provide the black and sync
levels. A contrast control that
sets the slicing level lets you
adjust the sync tip height
with respect to the black
level. The video slicer also
minimizes rf getting back into
the video. An attenuator to
re d u ce the size of the
modulated signal usually
follows the diode modulator.
An upper side band filter
removes most of the lower
sideband from the AM
modulated output, giving us a
vestigial sideband signal that
stays inside the channel band
limits. This same filter
eliminates second harmonic
effects and other spurious
noise. The filter's output is
usually routed to an antenna
disconnect switch and the
TV's antenna terminals. A
special switch is needed to
provide enough isolation.
Some of the actual
circuitry involved is shown in
Fig. 17. The video slicer
consists of a pair of high gain,
small signal NPN transistors,
while the oscillator is a
·commercially available
module.
Rf entry systems always
must be direct coupled to the
antenna terminals of the set
and should never provide any
more rf than is needed for a
minimum snow-free picture.
They should be permanently
tuned to a single TV channel.
Under no circumstances
should an antenna or cable
service hookup remain
connected to the set during
TVT use, nor should
radiation rather than a direct
rf cable connection ever be
used.
black and white video dot
ra te is low enough in
frequency to be attractively
displayed on an ordinary
color TV. Color may be used
to emphasize portions of a
message, to attract attention,
as part of an electronic game,
or as obvious added value to a
graphics display. Color
techniques work best on TV
typewriter systems having a
horizontal frequency very
near 15,735 Hertz.
All we basically have to do
is generate a subcarrier sine
wave to add to the video
output. The phase of this
subcarrier (or its time delay)
is shifted with respect to
what the phase was
i mmedi ate I y after each
horizontal sync pulse to
generate the various colors.
Fig. 18 shows us the
differences between normal
color and black and white
operation. Black and white
baseband video is some 4
MHz wide and has a narrow
4.5 MHz sound subcarrier.
The video is amplitUde
modulated, while the sound is
narrow band frequency
Fig. 17. Channel two oscillator, modulator, video slicer and attenuator.
R sets output level.
OX OSCILLATOR MODULE a
EX CRYSTAL (INTERNATIONAL
CRYSTAL) OR EQUIV
7T -1/4 in. DIA (NO SLUG J
2N3643
+5V~~~---'--------~~
;t;.OI
MPS6520
2N5129
2N4400
ETC
+5V
VIDEO
INPUT
470
Color Techniques
We can add a full color
capability to a TV typewriter
system fairly easily and
cheaply - provided its usual
AVI-ll
. . . '1.: Fo~~T
DIRECT COUPLE OUTPUT
IN914 or
4.7K
-5V
Fig. 18. Differences between color and black and white spectra.
(a) mack and white - baseband video.
I
SOUND
VIDEO
(I
i
4.5MHz
DC
i
SOUND
VIDEO
54 55.25
59.75 60 MHz
(b) mack and white - Channel two rf.
(c) Color - baseband video.
!
I
LUMINANCE
modulated. This translates up
to a 6 MHz rf channel with a
vestigial lower sideband as
shown in Fig. 18(b).
To generate color, we add
a new pilot or subcarrier at a
magic frequency of 3.579545
MHz - see Fig. 18(c). What
was the video is now called
the luminance,· and is the
same as the brightness in a
black and white system. The
new subcarrier and its
modulation is called the
chrominance signal and
determines what color gets
displayed and how saturated
the color is to be.
Since the black and white
information is a sampled data
system that is scanned at the
vertical and horizontal rates,
there are lots of discrete holes
in the video spectrum that
aren't used. The color
subcarrier is designed to stuff
itself into these holes (exactly
in a NSTC color system, and
pretty much in a TVT
display). Both chrominance
and luminance signals use the
CHROMINANCE
~O""~
o
LUMINANCE
CHROMINANCE
II Zti,·"
3.58 4.5 MHz
54 55.25 58.82
60 MHz
(d) Color - Channel two rf.
same spectral space, with the
one being where the other
one isn't, overlapping comb
style.
The phase or relative delay
of the chrominance signal
with respect to a reference
determines the instantaneous
color, while the amplitude of
this signal with respect to the
luminance sets the saturation
of the color. Low amplitudes
generate white or pastel
shades, while high amplitudes
of the chrominance signal
produce saturated and deep
colors.
At least eight cycles of a
reference or burst color phase
are transmitted immediately
following each horizontal
sync pulse as a timing
reference, as shown in Fig.
19. The burst is around 25%
of maximum amplitude, or
about the peak to peak height
of a sync pulse.
The TV set has been
trained at the factory to sort
all this out. After video
detection, the set splits out
the ch rominance channel
with a bandpass amplifier and
then synchronously
demodulates it with respect
to an internal 3.58 MHz
reference. The phase of this
demodulation sets the color
and the amplitude sets the
saturation by setting the
ratios of electron beam
currents on the picture tube's
red, blue and green guns.
Meanwhile, the luminance
channel gets amplified as
brightness style video. It is
delayed with a delay line to
make up for the time delay
involved in the narrower band
color processing channel. It is
then filtered with two traps the 4.5 MHz sound trap, and
a new trap to get rid of any
remaining 3.58 MHz color
sub carrier that's left. The
luminance output' sets the
overall b rightness by
modulating the cathodes of
all th ree color guns
simultaneously.
Just after each horizontal
sync pulse, the set looks for
the reference burst and uses
this reference in a phase
Fig. 19 Adding a color reference burst to the back porch of the
horizontal sync pulses.
8 CYCLES (MIN)
OF 3.57945 MHz
COLOR REFERENCE
PHASE
-::u
BLACK
.......1
(BLACK
AVI-12
1-5.I,.SEC
a WHITE)
BLACK
SYNC 1
--1
I
-5.I,.SEC
(COLOR)
Fig. 20. Colors Are Generated by Delaying or Phase Shifting the
Burst Frequency.
Color
Approximate
Phase
Approximate
Delay
00
150
750
1350
1950
2550
3150
0
12 nanoseconds
58 nanoseconds
105 nanoseconds
151 nanoseconds
198 nanoseconds
244 nanoseconds
Burst
Yellow
Red
Magenta
Blue
Cyan
Green
detector circuit to keep its
own 3.58 MHz reference
locked to the version being
transm itted.
Fig. 20 shows us the phase
angles related to each color
with respect to the burst
phase. It also shows us the
equivalent amount of delay
we need for a given phase
angle. Since we usually want
only a few discrete colors, it's
far easier to digitally generate
colors simply by delaying the
reference through gates or
buffers, rather than using
complex and expensive
analog phase shift methods.
S tr ic tl y s peaking, we
should control both the
chrominance phase and
amplitude to be able to do
both pastel and strongly
saturated colors. But simply
keeping the subcarrier
amplitude at the value we
used for the burst - around
25% of video amplitude - is
far simpler and will usually
get us useful results.
A circuit to add color to a
TV typewriter is shown in
Fig. 21. A 3.579545 MHz
crystal oscillator drives a
string of CMOS buffers that
make up a digital delay line.
The output delays caused by
the propagation delay times
in each buffer can be used as
is, or can be trimmed to
specific colors by varying the
supply voltage.
The reference phase and
the delayed color outputs go
to a one-of-eight data
selector. The data selector
picks either the reference or a
selected color in response to a
code presented digitally to
the three select lines. The
logic that is driving this
selector must return to the
wanted. The output
chrominance signal is RC
filtered to make it somewhat
sinusoidal. It's then cut down
in amplitUde to around
one-quarter the maximum
video white level and is
capacitively coupled to the
100 Ohm video output of
Fig. 2 or otherwise summed
into the video or rf
modulator circuitry. For
truly dramatic color effects,
the amplitude and delay of
the chrominance signal can be
changed in a more complex
version of the same circuit.
More information useful in
solving television interface
appears in the Television
Engineering Handbook, by
Donald Fink, and in various
issues of the IEEE
reference phase position
(000) immediately before,
during and for a' minimum of
a few microseconds after each
horizontal sync pulse. This
gives the set a chance to lock
and hold onto the reference
color burst.
The chrominance output
from the data selector should
be disabled for the duration
of the sync pulses and any
time a white screen display is
Tran'sactions on Consumer
Electronics.
Fig. 21; Color subcarrier generator. Hex buffer used as delay line. Use
supply voltage variation on 4050 to trim colors.
22K
4049
(CMOS)
OSC.
GREEN
22MEG
REF
PHASE
H SYNC
INPUT
o o - - - - - - - - -.. . Idis
abc
COLOR
SELECT
INPUTS
4512 (CMOS)
ONE-OF' EIGHT
SELECTOR
Inh
OUT
330n
680pF
MUST RETURN TO 000
(REFERENCE PHASE)
DURING 8 AFTER H
SYNC PULSE
.----I~
I
SET TO
/'25% OF PEAK
WHITE LEVEL
M1W\A
.01
1
VIDEO COMBINER
(loon LOAD)
AVI-13
Pinouts: Parallel Data Interface (PDI) as
Sept. 30, 1976
used on Processor Tech. Sol System
MASTER UNIT-Male connector
J2 Pin # Signal
Signal
J2 pin# Signal
Signal name
nmemonic
name
nmemonic
1
CG
Chassis Ground
i4
US
Unit Select
2
SG
Signal Ground
15
OE
Output Enable
3
IE
Input Enable
16
XDR
eXternal Device Ready
4
DR
Data Ready
17
S
IAK
Input Acknowledge
18
OD7
Output Data,bit 7
6
ID7
Input Data, bit 7 19
OD6
Output Data, bit 6
7
ID6
Input Data, bit 6 20
ODS
Output Data, bit S
8
IDS
Input Data, bit S 21
OD4
Output Data, bit 4
9
ID4
Input Data, bit 4 22
OD3
Output Data, bit 3
10
ID3
Input Data, bit 3 23
OD2
Output Data, bit 2
11
ID2
Input Data, bit 2 24
ODI
Output Data, bit 1
12
IDI
Input Data, bit 1 25
ODO
Output Data, bit 0
13
IDO
Input Data, bit 0
Output Load
Pinouts: Serial Data Interface tSDI) as
used on Processor Tech. Sol System
Female connector-DB2SS
Jl pin# Signal
Signal
Jl pin# Signal
Signal name
nmemonic
nmetnonic
name
1
Carrier Detect
CG
Chassis Gro1.md
CD
8
2
TD
Transmit Data
11
CLO
Current Loop Output
3
RD
Receive Data
12
LRI
Loop Receiver 1
4
RTS
Request To Send
13
LR2
Loop Receiver 2
5
CTS
Clear To Send
20
DTR
Data Terminal Ready
6
DSR
Data Set Ready
23
LCS
Loop Current Source
7
SG
Signal Ground
Note 1:
Note 2:
Note 3:
REV A
Many pins not specified here are used in EIA RS-232C specification.
USE THEM WITH CAUTION.
Terminals output on pins 2,4 & 20 and input on pins 3,5 & 6 for EIA
type hookups. Modems and computer mainframes output on pins 3,5 & 6
and input on pins 2,4 & 20.
Current loop hookups are the same for terminals, modems,mainframes.
AVII-l
J3 Keyboard Connector (between U64 and U65)
pin no.
1
2
3
4
5
6
7
8
9
10
Signal name
ground
+5v
Kbd Data Ready
Break
Kbd Data (D
Kbd Data 1
Kbd Data 2
Kbd Data 3
+5v
ground
pin no.
11
12
13
14
15
16
17
18
19
20
Sol-PC, Rev. 2,E
10/18/76
Signal name
ground
+5v
Restart
Local
KBd Data 4
KBd Data 5
KBD Data 6
KBD Data 7
+5v
ground
J4 Display Expansion Connector (between U28, 29)
no.
Signal name
ground
N.C.
Char. addr. 4
Character clock
Char. addr. (D
Char. addr. 1
Char. addr. 2
Char. addr. 3
N.C.
ground
2
3
4
5
6
7
8
9
10
1
no.
12
13
14
15
16
17
18
19
20
Signal name
ground
N.C.
Dot Clock, l4.3l8MHz
Composite sync. out
TTL Serial Data Out
Composite blanking out
Scan advance out
Char. addr. 5
N.C.
ground
J5 Personality Module Edge Connector
p~n
B15
B14
B13
B12
Bll
BIO
B9
B8
B7
B6
BS
B4
B3
B2
BI
no.
B
0
T
T
0
1-1
R
0
/J
P
I
-N-
pin no.
A15
A14
T
A13
0
A12
p
All
AlO
R
A9
A8
0
A7
vJ
A6
AS
P
A4
I
A3
N
A2
S
Al
Signal name
Ground
+5VDC
Addr. 9
Addr. 8
Addr. 7
INT Bus (D
INT Bus I
INT Bus 2
INT Bus 3
INT Bus 4
INT Bus 5
Program 0
Program I
Program 2
Program 3
Signal name
Ground
+5VDC
Addr. (D
Addr. 4
Addr. 3
Addr. 2
Addr. 1
Addr. 5
Addr. 6
C4
C(D
INT Bus 6
INT Bus 7
-12VDC
+12VDC
J6
S
Audio Out for CUTS Cassette Interface:
J7
Audio In forCUTS Cassette Interface:
J8
Tape Motor Control 1 :
panel
(See output port FA, bit 7) Sub-mini jack at rear
J9
Tape Motor Control 2:
panel
(See output port FA, bit 6) Sub-mini jack at rear
Mini-phone jack at rear panel
Mini-phone jack at rear panel
Rev A
AVII-2
J10
DC Power Connector, Sol-PC
0
0
Ground
+5VDC
-12 VDC
+12 VDC
-12 VDC
+5 VDC
Ground
0
0
'0
0
0
S-100 Bus Definitions
PIN
NUMBER
FUNCTION
Unregulated voltage on bus, supplied
to PC boards and regulated to 5V)
supplied by Sol-20 supply
Positive unregulated voltage supplied by
+16 Volts
Sol-20 power supply
EXTER..1AL READY External ready input to CPU ready
circuitry
Vectored Interrupt
Line 110
Vectored Interrupt
Line IFl
Vectored Interrupt
Line 112
Ve.ctored Interrupt
Line 113
Vectored Interrupt
Line 1/4
Vectored Interrupt
Line 115
Vectored Interrupt
Line 116
Vectored Interrupt
Line 117
EXTERNAL READY 112
not used by Sol-PC
1
SYMBOL
+8V
2
+16V
3
XiRDY
4
VIO
5
VI1
6
VI2
7
VI3
8
VI4
9
VI5
10
VI6
11
VI7
12
13
to
17
XRDY2
TO BE DEFINED
18
STAT DSB
STATUS DISABLE
19
C/C DSB
COMMAND/CONTROL
DISABLE
20
21
22
UNPROT
SS
ADD DSB
UNPROTECT
SINGLE STEP
ADDRESS DISABLE
23
DO DSB
DATA OUT DISABLE
24·
25
26
02
01
PHLDA
PHASE 2 CLOCK
PHASE 1 CLOCK
HOLD ACKNOWLEDGE
REV A
NAME
+8"Vo1ts
AVII-3
-Allows the buffers for the 8
status lines to be tri-stated
-Allows the buffers for the 6
output command/control lines
to be tri-stated
- not used by Sol-PC electronics
- not used by Sol-PC
-Allows the buffers for the 16
address lines to be tri-stated
-Allows the buffers for the 8
data output lines to be tri-stated
Processor command/control output
signal that appears in response to
the HOLD signal; indicates that the
data and address bus will go to the
high impedance state and processor
will enter HOLD state after
completion of the current machine
cycle.
S-100 Bus Definitions-continued
PIN
NUMBER
27
SYMBOL
PWAIT
28
PINTE
INTERRUPT
ENABLE
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A5
A4
A3
A15
A12
A9
DIOI
DI00
AIO
DI04
DI05
DI06
DI02
DI03
DI07
SMI
Address Line
Addre s s Line
Address Line
Address Line
Address Line 1112
Address Line 119
Data In/Out line
Data In/Out line
Address Line 1/10
Data In/Out Line
Data In/Out Line
Data In/Out Line
Data In/Out Line
Data In/Out Line
Data In/Out Line
MACHINE CYCLE 1
45
SOUT
46
SINP
47
SMEMR
48
SHLTA
49
50
51
CLOCK
GND
+8V
52
-16V
REV A
NAME
WAIT
FUNCTION
-Processor command/control output signal that indicates the processor is
in the wait state in response to a
low READY signal or a HALT instruction.
-Processor command/control output signal;
indicates interrupts are enabled, as
determined by the contents of the CPU
internal interrupt flip-flop. When the
flip-flop is set (Enable Interrupt
instruction), interrupts are accepted by
the CPU; when it is reset (Disable
Interrupt instruction), interrupts are
inhibited.
115
1/4
113
#15 (MSB)
#1
#0
same as pin 94
same as pin 95
#4
same as pin 91
#5
same as pin 92
#6
same as pin 93
#2
same as pin 88
#3
same as p~n 89
same as pLn 90
#7
-Status output signal that indicates
that the processor is in the fetch
cycle for the first byte of an
instruction
-Status output signal that indicates
OUTPUT
the address bus contains the address
of an output device and the data bus
will cobtain the ouput data when PWR.
is active
-Status output signal that indicates
INPUT
the address bus contains the address
of an input device and the input data
should be placed on the data bus when
PDBIN is active
-Status output signal that indicates
MEMORY READ
the data bus will be used to read
memory data
HALT ACKNOWLEDGE - Status output signal that acknowledges
a HALT instruction
- Inverted output of the 02 CLOCK
CLOCK
GROUND
Unregulated input to 5 volt
+8 Volts
regulators supplied by Sol-20
power supply
Negative unregulated voltage Rupp1ied
-16 Volts
by Sol-20 power supply
AVII-4
S-lOO Bus
PIN
NUMBER
53
54
55
SYMBOL
SSWI
EXT CLR
RTC
STSTB
Def~nitions-continued
NAME
57
i5ffi
SENSE SWITCH INPUT
EXTERNAL CLEAR
REAL TIME CLOCK
STATUS STROBE
DATA INPUT GATE #1
58
59
FRDY
FRONT PANEL READY
56
to
TO BE DEFINED
64
65
MREQ
MEMORY REQUEST
66
REF
REFRESH
67
PHANTOM
PHANTOM DISABLE
68
MWRITE
MEMORY WRITE
69
70
71
72
Ps
PROT
RUN
PRDY
PROJECT STATUS
PROTECT
RUN
PROCESSOR READY
73
PiNT
INTERRUPT REQUEST
74
PHOLD
75
PRESET
RESET
76
PSYNC
SYNC
77
PWR
WRITE
78
PDBIN
DATA BUS Iij
AVII-S
FUNCTION
not used by Sol
not used by Sol-PC electronics
not used by Sol-PC electronics
not used by Sol
When low forces PDBINS low and
forces CPU input multiplexers to
the DIO bus. During CPU DBIN cycle,
disables CPU DIO bus drivers
-When low disables MWRITE,driver
- Z 80 signal not used by Sol-PC
electronics
- Z 80 signal not used by Sol-PC
electronics
-Output from CPU section used to
disable RAM or ROM during power on
initialization program execution
-Indicates that the data present on
the Data Out Bus is to be written
into the memory location currently
on the address bus
-not used by Sol-PC electronics
-not used by Sol-PC electronics
- not used by Sol-PC electronics
- Memory and I/O input to the CPU
Board wait circuitry
- The processor recognizes an
interrupt request on this line at
the end of the current instruction
or while halted. If the processor
is in the HOLD state or the
Interrupt Enable flip:flop is reset,
it will not honor the request.
-Processor cOlmnand/ control input
signal that requests the processor
enter the HOLD state; allows an
external device to gain control of
address and data buses as soon as
the processor has completed its
use of these buses for the current
machine cycle
-Processor command/control input;
while activated, the content of the
program counter is cleared and the
instruction register is set to 0
-Processor command/control output;
provides a signal to indicate the
beginning of each machine cycle .
-Processor command/control output;
used for memory write or I/O output control. Data on the da~a bus
is stable while the PWR is active
-Processor command/control output;
indicates to external circuits that
the data bus is in the input mode
S-IOO Bus Definitions-continued
PIN
NUMBER
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
SYMBOL
AO
Al
A2
A6
A7
A8
A13
A14
All
DI02
DI03
DI07
DI04
DI05
DI06
DIOI
DI00
SINTA
97
SWO
98
SSTACK
99
100
P6C
GND
NAME
FUNCTION
(LSB)
Address Line 410
Address Line if!
Address Line i,b2
Addres s Line ifo6
Addre s s Line in
Address Line #8
Address Line ifo13
Address Line ifo14
Address Line if!l
Data In/Out Line 412
same as pin 41
Data In/Out Line 413
same as pin 42
Data In/Out Line 417
same as pin 43
Data In/Out Line #4
same as pin 38
Data In/Out Line #5
same as pin 39
Data In/Out Line #6
same as pin 40
Data In/Out Line #1
same as p~n 35
Data In/Out Line #0
same as p1n 36
INTERRUPT ACKNOWLEDGE -Status output signal; acknowledges
signal for INTERRUPT request
WRITE OUT
-Status output signal; indicates
that the operation in the current
machine cycle will be a WRITE
memory or output function
STACK
-Status output signal indicates
that the address bus holds the
pushdown stack address from the
Stack Pointer
POWER-ON CLEAR
GROUND
SWITCH FUNCTION DEFINITION
Switch No.
Sl-l
Sl-2
Sl-3
Sl-4
Sl-5
S1-6
Mnemonic
RST
not used
BLANK
Polarity
BLINK
SOLID
Display Ctrl---Schematic Drawing 414
Function
ON
OFF
Restart to Zero
RUN ( Dwg. 1f1)
Blank Ctrl Characters Display Ctrl Char.
Blinking cursor
Solid cursor
*Solid or NO cursor
*Blinking or NO cursor
*NO cursor if Sl-5 and Sl-6 are off at same time.
Both switches should not be on at the same time.
Drawing 413 -- Sense Switch
Switch No.
Mnemonic
S2-l
SSW0
S2-2thruS2-7
S2-8
SSW7
Function
ON
LSB, data bit
etc.
MSB data bit 7
AVII-6
ON
OFF
0-LO
LO
LO
I-HI
HI
HI
SERIAL I/O BAUD RATE SWITCH -- Schematic Drawing #3
Function
Mnemonic
ON
OFF
Switch No.
75
S3-1
75 BAUD
* Do not turn more than
110 BAUD
one switch on at a time
11
S3-2
150 BAUD
15
S3-3
300 BAUD
30
S3-4
600 BAUD
60
S3-5
12
1200 BAUD
S3-6
24/48
2400 or 4800(normally 2400 if not jumpered K to M)
S3-7
9600 BAUD
96
S3-8
Schematic Drawing #3
SERIAL I/O CONTROL
OFF
Switch No.
Mnemonic
ON
Parity even (if S4-5 on)
PS
S4-l
Parity·odd
WLS 1
Data word length 8bits 7bits 6bits 5bitS)·
S4-2
( Off
WLS 2
S4-3
On
Off
On
Off
Off On
On
2 stOD bits (1.5 if 5bits/word)
S4-4
SBS
1 stop bit
PI
No parity
S4-5
Parity
Half duplex
Full duplex
S4-6
F/R
MEMORY ALLOCATION:
Hexidecimal Address
c000 - C7FF
C800 - CBFF
CC00 - CFFF
ON CARD
Function
Personality Module ROM or PROM (2048 words)
System RAM (1024 words)
Display RAM Memory (1024 characters)
ON CARD INPUT PORT ALLOCATION
Hexidecimal Port
Address
Fa
F9
FA
FB
FC
FD
FE
FF
OUTPUT PORTS
Hex Port Address
F8
F9
FA
FB
FC
FD
FE
FF
Function
Status, Serial Comm. channel
Serial Communicatio~ Channel Data
Aux. Status, Cassette tape interface, parallel
I/O, keyboard input
Audio Cassette (CUTS) Data
Keyboard Data (from J3)
Parallel Port Data (from J2)
Display Status
Sense Switch (S2-l thru S2-8)
.Function
Control, Serial Comm. Channel
Data, Serial Comm. Channel
Control, Parallel I/O, CUTS Cassette I/O
Data, CUTS audio cassette Interface
Alarm (optional)
Data, Parallel output Data channel
Scroll control,
Display Section
not used in Sol-PC
REV B
AVII-7
STATUS PORT INPUT BIT ASSIGNMENTS
PORT F8 (STATUS, SERIAL COMM. CHANNEL)
FUNCTION
SIGNAL NAME
¢
SCD
Serial Carrier Detect (EIA)
1
SDSR
Serial Data Set Ready (EIA)
2
SPE
Serial Parity Error
3
SFE
Serial Framing Error
4
SOE
Serial Overrun Error
5
SCTS
Serial Clear to Send (EIA)
6
SDR
UART Serial Data Ready
7
STBE
UART Serial Transmit Buffer Empty
PORT FA (AUX. STATUS, CASSETTE TAPE INTERFACE, PARALLEL I/O,
BIT
SIGNAL NAME
FUNCTION
¢
KDR
PDR
PXDR
TFE
TOE
not used
TDR
TTBE
1
2
3
4
5
6
7
ACTIVE DIRECTION
1 carrier
link ok
1 error
1 error
1 error
¢ clear
1 ready
11 empty
KEYBOARD INPUT)
ACTIVE DIRECTION
¢
Keyboard Data Ready
Parallel Data Ready
Parallel eXternal Device Ready
Tape Framing Error
Tape Overrun Error
¢
Tape Data Ready
Tape Transmitter Buffer Empty
1 ready
1 empty
PORT FE (DISPLAY STATUS)
BIT
SIGNAL NAME
¢
SOK
Scroll OK~
scroll
FUNCTION
~
sec timeout after
CONTROL PORT OUTPUT BIT ASSIGNMENTS
PORT F8 (CONTROL, SERIAL COMM. CHANNEL)
SIGNAL NAME
FUNCTION
ready
¢ ready
¢ ready
1 error
1 error
ACTIVE DIRECTION
¢ time complete
ACTIVE DIRECTION
1 request
4
SRTS
Serial Request to Send
PORT FA (CONTROL, PARALLEL I/O, CUTS CASSETTE I/O)
BIT
SIGNAL NAME
FUNCTION
3
PIE
Parallel Input Enable
4
PUS
Parallel unit Select
5
TBR
Tape Baud Rate (300/1200)
6
TT2
Tape Transport 2
7
TTl
Tape Transport 1
PORT FE (SCROLL CONTROL, DISPLAY SECTION)
BIT
FUNCTION
SIGNAL NAME
ACTIVE DIRECTION
1 pin 3 J2 low
o pin 14 J2 low
o 1200 Baud
o run tape
o run tape
¢ -
ACTIVE DIRECTION
3
BDLA
Beginning Display Line Absolute
address
4-bit data nybble
4 - 7
FDSP
First Displayed Line Screen
Position
4-bit data nybble
Jl
J2
J3
J4
J5
CONNECTOR DESIGNATION
Serial data
J6
Parallel Data
J7
Keyboard
J8
J9
Display Expansion
ROM Personality Module
JIO
Jll
AVII-8
Cassette Tape Audio Out
Cassette Tape Audio In
Tape Motor 1
Tape Motor 2
PC Power
S-IOO Bus Expansion
Personal Computing Magazine, May/June 1977
Copyright @ 1977, Benwi11 Publishing Corp.
Reprinted with permission.
u
by Tom Munnecke .
It helps you with your income tax, then it takes you in
the Starship Enterprise on an outer space crusade against
the Klingons. It teaches you Boolean logic, then it becomes
an opponent at checkers. It draws vivid pictures on your
television set, then telephones a distant computer to calculate the value of your personal stock portfolio.
What is this personal genie? How can it take on so many
personalities? It is the personal computer, and its personali·
ties are the unique products of its programmer. The computer is capable of nothing more, nothing less than the pro·
grammer instructing it. For all the precision and rigidity
associated with a computer, the programmer's work is still a
uniquely personal reflection of himself.
The fundamental connection between the programmer
and the computer is the computer language. The increasing
number and sophistication of computer languages bring the
power of the personal computer to the non-professional.
Computers are simple to deal with once certain fundamentals are understood. After that, learning becomes a trial and
error experience. A person learning to walk does not need
to understand each muscle, joint, and bone; he simply tries
to walk and corrects his mistakes. So it is with computer
programming. The novice programmer does not need to
know the intricacies of the computer. He needs only: to
know the fundamentals of the language, to know what his
errors are and how to correct them, and to have time enough
to try out his ideas.
The personal computer is a tool - the most powerful
tool ever put in the hands of the private individual. Its potential is limited only by its owner's capacity to apply it.
This article provides a head start on learning any computer language, discussing the merits and drawbacks of many
of the computer languages available to the personal computing enthusiast.
What is a Computer Language?
Computers operate in sequences of primitive decisions
made in millionths of seconds. People think in terms bf
vague concepts derived over days and months. The computer language is the means of linking these vague human concepts to the primitive computer decision.
AVllI-1
k
\,....
If you are going to
/program your own
computer, you need to
.
learn at least one lan';',
guage. This is not as diffi:
cult as it sounds, for com~
uter languages always have a
)
..
very respectable teacher - the
.:"
computer itself. After you learn
// one language, the second and third
. are learned easily. It is not unusual for a
professional programmer to use four or five
languages regularly.
Computers have a reputation for being rigid
and inflexible in their ways. This may be so, but
consider the poor language processor which has to
try to interpret
FORK=STOP
when the programmer mean t
FOR K=S TO P
Most of the rigidity of the computer is there for a purpose. If you learn how they interpret things, some apparent
inflexibility will fade away.
In order for the computer and the programmer to communicate, they must have some common physical medium
for communicating. Usually, this is a keyboard/printer or
video display. The programmer enters his programs in whatever language he is using, .in his version of the language,
known as the source language. He then asks a language processor to prepare it for the computer to process it.
There are two types oflanguage processors - translators
and interpreters. The translator accepts the source language
and translates it to an object language, which is then loaded
into the computer to be executed. Translators are further
broken down into assemblers and compilers. The assembler
is a means of manipulating machine-level operations for a
specific.computer, while the compiler translates higher-level,
or more human-oriented languages. Interpreters execute the
source language directly without the intermediate process
of translating to an object language.
Languages are classified into two vaguely defined classifications: high-level and low-leveL A low-level language is
one in which each of the source code instructions corresponds to a machine-level operation. Source code in a highlevel language may generate many machine-level instructions.
Assemblers, Compilers, and Interpreters
Each of the types oflanguage processors has its merits
and drawbacks - assemblers give the programmer great
power but require very detailed instructions; compilers support higher-level languages, but sacrifice machine efficiency;
and interpreters are easy to use, but are not as efficient as
compilers.
Assemblers
The assembler is the simplest form of computer language,
It accepts source code and translates it one-for-one into machine-level instructions or object code. Thus, the programmer has detailed control (and responsibility) of each instruction. For example, the programmer might write a line in
assembler such as:
NEXT JSR INCHAR; Jump to subroutine to get a
character.
'NEXT' is a label for the line. 'JSR' is a mnemonic for the
Motorola 6800 instruction 'Jump to subroutine'. 'INCHAR' represents the address of the subroutine to be used.
';Jump .. .' is a comment inserted by the programmer to explain the instruction for documentation.
The assembler (for th~ 6800) will assemble this instruction into the hexidecimal '8DXXXX' where '8D' is the operation code for branch to subroutine, and 'XXXX' is the
address of subroutine INCHAR. See Fig. 1.
Since the assembler may not know where the INCHAR
subroutine is to be located when the program is executed,
it must be resolved at a later time by the loader program.
Compilers
The compiler acts much like the assembler, but works
with higher level languages. The compiler understands more
AVIII-2
r-----------,. - - - - - - - - - - - - ' I
Programmer's Instruction
TOT=SUM+NUM
Source Code
'JSR INCHAR'
Action Taken
Source Statement
Action Taken
high level
source code
is compiled into
is assembled into
'SOXXXX'
LOA
ADD
STA
LOA
AOC
STA
Object Code
A SUM+l
A NUM+l
A TOT+l
A SUM
ANUM
A TOT
object code, which
is either loaded
or assembled
which must be
loaded into
Main Memory
'SOEIAC'
Fig. 1 Operation of an Assembler
Fig. 3 Operation of a Compiler
complex expressions, and does much more work than the
assembler. Figure 2 illustrates a single high level language expression which would require 6 lines to write in assembler.
TOT=SUM+NUM
LOA
ADD
STA
LOA
AOC
STA
A
A
A
A
A
A
SUM+l
NUM+l
TOT+l
SUM
NUM
TOT
Add the right
most bytes and
store the result.
Add the left
most bytes and
store the result.
Comparison of the Methods:
Each of the methods is used in the commercial computing world, indicating that there is sound economic need for
each. The methods may intermingle, as in compilers that
accept assemblerlanguage code, incremental compilers,
which are a cross between interpreting and compiling, and
compilers which produce interpretive object code. Fig. 5
illustrates many common considerations of the various
language processors.
Disadvantages of Assemblers
Fig. 2 Comparison of high·level expression and its low·
level language equivalent.
:This is a simple example, but a more complex example,
such as:
TOT=( SUM + NUM/1.238 * COS (ARC/360» ** 2/7.32
could give the.assembler language programmer a tremendous
amount of difficulty.
Typically, a compiler produces assembly language code,
which is then passed through the assembler.
Interpreters
The interpreteds a departure from the techniques of the
assembler or compiler. While the translators create a program
which must be loaded and executed later, the interpreter executes source instructions directly. The source remains in its
original form.
Many languages may be either compiled or interpreted,
although some features of a language may make compilation
difficult, if not impossible. The interpreted language can
change its interpretation as it receives new data, while the
compilt:: ·:loes not know what data the program will receive
until after it has finished its work.
Because the programmer must detail each operation of
the computer, his workload is much greater than with higher
level languages. His chances for making an error are much
greater than in high-level languages. The programmer can
easily become enmeshed in the maze of details he must remember. Modifying an intricate assembler language program
may be very difficult, if not impossible. Assemblers are not
usually interactive, requiring the entire program to be reassembled when an error is made.
Advantages of Compilers
The compiler is capable of supporting much higher level
languages than assembler or macro assembler. The pro·
grammer can work faster, make fewer errors, and learn the
language faster than he can assembler. The compiler's object
code may be executed much faster than an interpreter could
execute the program (between 5 and 10 times faster). Programs written in the higher level language may be recompiled
on a new type of computer, without modifying the program.
/'
Disadvantages of Compilers
Compilers are usually large, complex programs which
require some time to compile a program, in addition to a
significant amount of off-line storage. Compilers are not
AVIII-3
usually interactive, because they require an entire program
to be recompiled when a single change must be made.
Due to the internal workings of the compiler, data types
must be fixed during compilation. This process, known as
binding, reduces the program's ability to adapt to new data
as the program is executed. An interpreter, however, does
not bind its variables until execution.
Disadvantages of the Interpreter
Interpreters tend to be slower than compilers, between 5
and 10 times slower, as a rule of thumb. This slowness is due
to the interpreter's need to analyze each statement every
time it sees it, whereas the compiler need analyze it only
once. The interpreter program must remain in memory for
even a small program.
Advantages of the Interpreter
A Bit of History
Since the interpreter executes its source code directly,
the programmer may interact more directly with the computer. Usually, the inte,rpreter provides a direct mode, where
the programmer may execute statements directly as he enters
them, and an indirect mode, where his commands are stored
in a program for later execution. The programmer can usually stop the program, examine variables, and resume execution. Some interpreters (such as APL and MUMPS) provide
an EXECUTE command, which allows the program to execute a character string as if it were program text. Conversely,
some interpreters (MUMPS) allow a program to treat its own
text as data. Interpreters are useful for systems where the
language processor needs to be 'built in' to the computer,
as in intelligent terminals.
Source Code
is interpreted
and executed
immediately
Fig. 4 Operation of an Interpreter
Binding Time
Off Ii ne Storage
CPU Efficiency
Programmer
Efficiency
Program Size
Error Detection
Language
Interactive
Debugging
Language Processing Efficiency
Compile
much
medium
Execution
little/none
low
Assembly
much
high
medium
large
high
medium
low
small
machine
source
machine
no
yes
no
low
medium
high
Fig 5 Comparison of the features of the various types of language processors.
o Binding time - the point when the program's data types are fixed.
o Offline Storage - the amount of storage such as floppy .disks,
cassettes, etc, required for the language processor to work. _ CPU
Efficiency - of the program being processed. • Programmer Efficiency - of the programmer writing the program to be processed.
• Program Size - of the object code, or source code, in the case of
the interpreter .• Error Detection Language - the language in which
run time errors are detected.
The first computers were large, expensive devices requiring a roomful of air conditioning just to keep them cool.
Programming them was very difficult, and they ran quite
slow:
" ... the machine will then continue in operation hour after hour, completely checking its own
results until either the problem is solved, or a
breakdown occurs" (A Manual of Operation for
the Automated Sequence Controlled Calculator,
Harvard University, 1946).
At that time, a computer cost millions of dollars, and a
programmer cost a few hundred dollars per month. Today, a
computer costs hundreds of dollars, and the programmer
costs thousands of dollars per month. To put it in another
way, in 1946 a computer cost the equivalent of 250 programmers, today the programmer costs the equivalent of 100
computers.
Everyone agrees that computers should be used 'efficiently'. The problem is that people think of making the
CPU efficient, not the person using it. The microcomputer
has undermined the conventional wisdom of computer efficiency. The person who spends several month's rent on a
personal computer wants to see it do something for him
immediately, regardless of whether it uses the CPU 'efficiently'. Chances are he uses the computer only a few
hours a day. On the other hand, the professional programmer who works as one of a score of programmers using
a large computer must con tend with CPU efficiency in order
to keep from overloading the computer.
The microcomputer user needs to worry about CPU efficiency only when he reaches some limit - not enough memory response not fast enough, etc. Since no one else is waiting to use his computer, he does not have to worry about
inefficiencies which do not force him beyond his limits.
The large computer programmer, however, must constantly worry about sharing the computer with all the other
users. Even if a program works fast enough for him, and
uses little enough memory, it still must be made 'efficient'
forthe other users of the system.
As a result of this historical concern for CPU efficiency,
people are fixated on "making the computer run efficiently". Language design has been heavily weighted in favor
of making the computer efficient, not the programmer.
The personal computing software scene was a completely
unforeseen turn of events. None of the language designers
ever thOUght that the programmer would be working alone
on his own computer. As a result, the design tradeoffs were
heavily slanted in favor of the commerical user.
Which language is Best?
"I speak Spanish to God, Italian to women, French
to men, and German to my horse".
Charles V of France_
What is the best language? BASIC? Assembler? PL/M,
AVIII-4
BLOCK
LINE NUMBER
COMMANDS
ARGUMENTS
Fig. 6 BASIC Program Elements
LABEL
OPERATION CODE
OPERANDS
Fig. 7 Assembler Program Elements
STATEMENTS
EXPRESSIONS
Fig. 8 PLIM Program Elements
PROGRAM
WORKSPACE
PROGRAM
ROUTINE
GROUP
FUNCTION
LINE
LINE
LABEL
COMMAND
ARGUMENTS
Fig. 9 MUMPS Program Elements
OPERATORS
LITERALS
FUNCTION REFERENCES
Fig. 10 APL Program Elements
MUMPS, APL, PASCAL, FORTRAN, SNOBOL, COBOL,
USP, COMIT, MAD, or any of the hundreds of others? And
after the best language is chosen, which dialect is best? Consider the dialects of BASIC: Tiny BASIC, Extended BASIC,
BASIC Plus, Business BASIC, ANS BASIC ...
Perhaps a good analogy could be drawn between computer languages and spoken languages. Which spoken language
is best? English? French? Chinese? Italian? It all depends on
what you want to do with it. If you are in Paris, French
would be a good contender for the 'best' language. Suppose
you are in Kansas, and believed Charles' statement above
that Italian is best for speaking to women. Romantic pretentions aside, you would probably have better luck with English.
The "best" computer language is not selected on the basis of its syntax or grammar. It is a very pragmatic decision
based on what is available, what the programmer knows,
whether it can perform the task at hand, and what programs are available to him from other sources.
The selection of a computer language is an important
decision to the personal programmer for many reasons beyond the above pragmatic ones. The language a programmer
uses profoundly affects the way he sees a problem. As
Whorf said, "We dissect nature along lines laid down by our
native language". The APL programmer thinks in terms of
vectors, the MUMPS programmer thinks in terms of data
bases, and the Assembly language programmer thinks in
terms of individual bytes of memory.
Therefore, in reviewing each of the languages, the reader
must apply them to his own needs. The following list is a
sample of some of the languages available (or may be soon)
to the micro-computer user.
BASIC - (Beginner's All purpose Symbolic Instruction
Code). This is the most common high-level language used
on personal computers. It is a very simple, easy to learn
language. There is a large library of programs available,
LINE NUMBER
COMMAND
ARGUMENTS
Fig. 11 FOCAL Program Elements
since BASIC is used in many universities and schools. Because it is a simple language, it is somewhat limited and
difficult to use for some complex problems. BASIC is
usually interpreted on microcomputers, although some
compilers exist. Programs written in BASIC for one computer can often be run on another with only slight
changes.
Assembler - Assembler language is commonly used on personal computers. Since many personal computers have
neither the memory or Input/Output capability to run an
assembler, the programmer often manually assembles his
program and enters it through the switches on the panel.
Assembler language is unique to each computer, so program exchange is limited to one particular computer type.
Assembler language is the common denominator of all
programs - eventually, all programs are just a sequence of
assembler-level instructions. Therefore, anyone wishing
to really know how his computer works must learn at
least a little Assembler. Often, a program is written in a
high-level language which calls an Assembler language subroutine for difficult or critical portions of logic. This can
be a very economical mix for programs which exceed the
limits of a high-level language.
PL/M - (A program name copyrighted by Intel Corp.) is
a compiled language derived from IBM's PL/I. Versions
exist for the 8080,6800, and Signetics 2650. Some high
speed, mass storage (floppy disk, for example) is required. It is an alternative to assembler, producing slightly
less efficient programs in much less programming time.
A basic user would find PL/M difficult to use for simple
problems, but easier to use for more complex problems.
There is no extensive library of programs in PL/M as with
BASIC.
AVIII-5
MUMPS - (Massachusetts General Hospital Utility MultiProgramming System) is an interpretive language oriented
towards interactive data management applications.
MUMPS has many characteristics of BASIC, FOCAL, and
IBM's PL/l. It differs from all these in that it has built-in
data base capabilities for handling data on mass storage
devices. Although not widely available on microcomputers now, the National Bureau of Standards published
a standard version (NBS Handbook 118) which details
how one would write an interpreter for MUMPS.
FOCAL have similar syntaxes, but different semantics.
With this background, you should be able to modify a
simple program to make it do increasingly complex tasks.
Each time you modify the program, use some new aspect of
the language, being careful to add one aspect at a time. Then,
try the new version to see if it does what you expect.
Each step of the way, you will be informed of your mistakes by your friendly adversary, the computer.
The Importance of Making Errors
"Nine times out of ten, in the arts as well as life. there IS
actually no truth to be discovered; there is only error to
be exposed."
H.L. Mencken
MUMPS has extensive data handling capabilities, suited
for applications such as personal accounting, word processing, and general information systems. Since the development of MUMPS was federally supported, much
MUMPS software is in the public domain.
APL - (A Programming Language) is a computer language
derived from Iverson's elegant mathematical notation.
It is a very powerful mathematical tool, having primitive functions for matrix inversion, inner products, sorting, and many other areas. Although initially developed
for large scale computers, it is now available for portable
commercial computers. APL is usually interpreted, and
therefore well suited for interactive personal computing.
FOCAL - (Formulating On-Line Calculations in Algebraic
Language) is a language brought out as an early on-line
language for calculations. Its syntax is similar to MUMPS,
although its functions are closer to.BASIC. FOCAL is
available on the 8080 and has a modest programming
library.
Making an error in a computer program is a fundamental
source of learning. You tried something and the computer
told you it didn't work. The programmer who proudly announces "my last program worked the first time without any
bugs" is a programmer who probably did not learn anything
new writing it.
Integer
(16 Bit)
X
Character
String
X
X
Floating
Point
X
X
Learning a Computer Language
Your first task in learning a new language is to build up a
basic understanding of the language. This can be gained from
the reference manual for the language distributed with the
software. Magazines such as Personal Computing carry many
articles on the more popular languages. There is a variety of
books available in libraries and computer stores, and more
advertised in professional data processing magazines.
When studying a language, it is helpful to divide the project into three areas:
SYNT AX - How you say something
SEMANTICS - What you mean
PRAGMATICS - How you make the language do what
you want
Syntax. The syntax of the language is usually the quickest
part to learn. How does the language distinguish between
a number and a variable? Do you need a number before
each line? What characters are allowed by the language?
Semantics. The semantic aspects of the language are
more difficult to learn, but you do not have to under-.
stand everything to use the language. What are arithmetic functions in the language? How do you retrieve data
from the terminal? How do you format output?
Pragmatics. This is the most difficult portion to learn, yet
it is the skill most easily carried over to other languages.
How do you make the language solve your problem?
How do you create, change, and delete programs? Can
you stop the program while it is executing, examine the
state of things, then resume execution?
X
Byte
Logical
X
Labels
X
x
x
X
X
X
X
X
X
x
x
X
Fig. 12 Cross Index of Data Element Types
Assign·
ment
LET
Read
from
Console
INPUT READ
Write to
Console
PRINT WRITE 0 +-
These three classifications are very useful for comparing
languages. For example, BASIC, FOCAL and FORTRAN
have sirriilar semantics but different syntaxes. MUMPS and
AVIII-6
SET
+-
SET
+-0
ASK
INPUT
TYPE
OUTPUT OUTPUT
INPUT
Fig. 13 Cross Index of Data Movement
Unconditional
Branch
GOTO GOTO
Conditional
Branching IF
IF
Involation
GO
SUB
DO
Return
from
Involation
RETURN QUIT
Looping
FORI
NEXT FOR
~
GO
GOTO GOTO
~
IF
IF
NAME DO
~O
CALL
IF
CALL
QUIT END
RETURN
FOR
DO
DO
Fig. 14 Cross Index of Control of Flow
And
Or
Not
Greater
Than
Less
Than
Equal
Not
Equal
Less
Than
Or Eq.
Greater
Than or
ual
The lesson is clear: When in doubt, try it. Let the computer
tell you whether it will accept the statement. Many manuals
are not reliable enough to trust anyway.
The above advice flies directly in the face of conventional
computer programming wisdom. In the past, there was considerable stigma attached to anyone found 'letting the computer do his debugging'. The theory was, that the computer
is a valuable resource, and that a programmer should not
waste computer time. Instead, he should carefully deskcheck his program before each submission. In the microcomputer world, this philosophy is radically altered. It makes no
sense for the programmer to check his work on paper when
his computer is waiting for him to enter it.
&
>
>
>
<
<
<
*
<>
<=
<
=>
Semantic errors
These errors are also common in the early stages of learning a new language, but continue to plague the programmer
throughout the use of the language. These errors are statements which are syntactically correct, but do not perform
the function desired by the programmer. Some typical
semantic errors are:
a) Mode errors - the programmer tries to add a number
to a character string, but the language does not handle
the conversion.
b) Binding errors - the programmer names the wrong
variable, label or subroutine.
c) Juxtaposition or sequencing errors. An end of a loop is
placed too far down in the program, or a variable is
used before it is initialized.
Most of the same advice for syntax errors applies to grammatical errors. Sometimes, grammatical errors can slip
through and only be detected by erratic program behavior.
*
>
Fig. 15 Logical and Arithmetic Comparison Function
*handled by I F statement structure.
Addition
Subtraction
Divide
Multiply
Exponentiation
Square root
Cosine
Tangent
SINE
eX Exponential
Natural log
Absolute Val
Greatest Integer
Random Number
Signum
Modulo
Fig.
+
+
+
+
+
*
*
+
t
SQR
COS
TAN
SIN
EXP
LOG
ABS
INT
RND
SGN
X
*
*.5
20
30
10
*
®
I
p
$R
#
?
X
FExP
FSQT
FCOS
FSIN
EXP
FLOG
FABS
FITR
FRAN
FSGN
Pragmatic errors
The pragmatic error is a statement which is syntactically
and semantically correct, but does not do what the programmer wants it to. These cannot be caught by the language
processor. Typical pragmatic errors are:
a) wrong function or command - the programmer uses a
sine function instead of cosine.
b) an improper formula - the programmer thought that
Interest was Principal divided gy Rate instead of Principal times Rate.
Pragmatic errors tend to be the last errors in a program to
be detected, if only because the programmer will not see them
until he cleans up the syntax and semantic errors and the
program executes.
Pragmatic errors can be very difficult to detect, particularly in programs which are time dependent or involve much
I
16 Cross Index of Arithmetic
Functions
The absence of an error when writing a program indicates
only that a situation new to the programmer did not come
up - not that the programmer has learned the language.
There are generally four types of errors: syntax, semantic, pragmatic, and covert.
Syntax errors
The syntax error is the most common error which faces
the beginning programmer. A syntax error is a statement
that violates the language's basic rule for expression. Typically, they are caused by:
a) typing errors - a finger Slips to the wrong key, a zero
instead of the letter 0, etc.
b) misunderstanding the syntax. The new programmer
may not understand that he has to put a comma between variables in a print statement, or put apostrophes around literals.
c) confusing the syntax. The programmer might confuse
a colon and the comma, or, he might carryover some
syntax from another language he knows.
One thing in common with all these errors is that the computer can detect them. In most interpreters, the programmer
may directly enter and execute any questionable statements.
Concatenation
Convert String
to Number
$ASCII
Convert Number
to String
Length
AVIII-7
$CHAR
LEN$
Fig. 17 Cross Index String Functions
logic. Pragmatic errors are generally discovered with what
the computing world euphemistically calls "testing".
"I'll test this program to make sure it won't blow up," is an
often heard phrase. Unfortunately after he completes his
testing, he all too often says "my program blew up".
Testing can confirm the existence of an error, not that
one doesn't exist. Just because 99 combinations of input
data were tried does not guarantee that the hundreth combination will not fail.
Covert errors
When a program is tested and declared correct by the programmer, any remaining errors are by definition covert.
These are insidious problems that appear only when events
combine to form some previously untried condition. Some
covert errors are:
a) An angle in a trigonometric equation goes to zero,
causing a zero divide error in a later division.
b) Improper data is entered, which the program does not
reject as invalid. Recently, a program sent out a letter
to the Emmet County Jail, "Dear Emmet C. Jail, you
are among a select group of persons ... " As the saying goes - garbage in, garbage out.
c) The programmer leaves room for only 3 digits of a
number, but the number grows past 999.
Covert errors always have and always will exist in computer software. However, a great deal of attention in computer science circles has been given to writing programs
which may be "proved" correct. These efforts, named
"structured programming", "software engineering", and
"composite design" will be covered in a future article. The
fundamental principles common to these are:
a) Break the big problem into clusters of independent
little problems.
b) link the clusters together in a hierarchical manner
such that each cluster is independently testable.
c) limit the number of paths the program may take.
This is accomplished by limiting the use of the GOTO
statement.
The programmer should learn to improve his skills by analyzing the errors he makes. When he meets that benevolent
dictator of linguistic purity - the error message - he should
treat it asa means of learning a little more about the language.
AVIII-8
\
UPDATES
Sol TERMINAL COMPUTER™
Electronics is a very fast moving field.
Development of new products, and improvements in the old
products proceeds at an unprecedented rate. The continuing development of the Sol Terminal Computer is no
exception. Better parts become available and are included, experience yields circuit improvements, and
new circuitry is developed. This process generates
changes much more frequently than this manual is reprinted. As a result, we include the improvements as
blue update sheets, added to this section as they become available. Be sure to integrate this information
into the body of the manual before beginning, by makrli:?~,.......~ndicated changes in the text, adding or replacing
. J?'J,g'es, or making notes referring you to the update page.
If you have a question as to the currency of a
particular page of text, look in the lower left-hand
corner of the page. The initial version of the page
will have this corner blank. When the contents of the
page have changed, the new version will have "REV A"
in this corner; a third version will have "REV B," and
so forth. When a whole new page and page number are
added, the corner is blank.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2018:08:26 15:46:44-08:00 Modify Date : 2018:08:26 16:03:28-07:00 Metadata Date : 2018:08:26 16:03:28-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:d8d5e7a1-fc96-7249-afe2-ba8256a9e159 Instance ID : uuid:c678e48a-068e-ff47-a4ff-ee20b4b90fea Page Layout : SinglePage Page Mode : UseNone Page Count : 303EXIF Metadata provided by EXIF.tools