Cyber_840A 870A_ _170_State_HRM.60463560C.1987 Cyber 840A 870A 170 State HRM.60463560C.1987
Cyber_840A-870A_-_170_State_HRM.60463560C.1987 Cyber_840A-870A_-_170_State_HRM.60463560C.1987
User Manual: Pdf Cyber_840A-870A_-_170_State_HRM.60463560C.1987
Open the PDF directly: View PDF 
.
Page Count: 260
| Download | |
| Open PDF In Browser | View PDF |
System Description This c h a p t e r i n t r o d u c e s t h e computer systems, i d e n t i f i e s t h e i r p h y s i c a l and f u n c t i o n a l c h a r a c t e r i s t i c s , and provides d e s c r i p t i o n s of major system components. Introduction The computer systems a r e l a r g e - s c a l e , h i g h s p e e d systems f o r both b u s i n e s s and s c i e n t i f i c a p p l i c a t i o n s . The systems i n c l u d e t h e f o l l o w i n g components. C e n t r a l p r o c e s s o r (CP). C e n t r a l memory (CM). I n p u t / o u t p u t u n i t (IOU). Physical Characteristics The mainframe c o n f i g u r a t i o n f o r t h e computer system ( f i g u r e 1-1) i n c l u d e s an i n t e r c o n n e c t e d t h r e e - s e c t i o n c a b i n e t f o r t h e CP, CM, and IOU. System o p e r a t i o n a l s o r e q u i r e s t h e system console. A second CP, which i s contained i n an a d d i t i o n a l one-bay s e c t i o n i s s t a n d a r d on a n 870A and o p t i o n a l on a n 860A. I n a d d i t i o n t o t h e s t a n d a r d I O U u n i t , an o p t i o n a l DMA ( d i r e c t memory a c c e s s ) I O U i s a v a i l a b l e with a l l models. Each c a b i n e t s e c t i o n c o n t a i n s a l o g i c c h a s s i s w i t h plug-in c i r c u i t boards. The CP c a b i n e t s e c t i o n comprises t h r e e a t t a c h e d s u b s e c t i o n s , each w i t h s e p a r a t e power and c o o l i n g f a c i l i t i e s . Each c a b i n e t s e c t i o n a l s o c o n t a i n s an a c / d c c o n t r o l s e c t i o n w i t h v o l t a g e margin t e s t i n g f a c i l i t i e s and d c power s u p p l i e s . A stand-alone water-cooling u n i t ( s ) provides c o o l i n g f o r t h e CP s u b s e c t i o n s , CM, and IOU. For s p e c i f i c c o o l i n g c o n f i g u r a t i o n s , r e f e r t o t h e mainframe s i t e p r e p a r a t i o n manual l i s t e d i n t h e preface. For a d d i t i o n a l c o o l i n g o r power i n f o r m a t i o n , r e f e r t o t h e c o o l i n g system and power system manuals l i s t e d i n t h e preface. I I Functional Characteristics -I---- ---d 1 I IOU CM INTERBAY I WATER COOLING A SYSTEM CONSOLE CPO r I I L---A , + IOU a NOTES: CP1 OPTIONAL WlTH 860A. STANDARD WlTH 810A. A SECOND WATER COOLING UNlT IS REQUIRED FOR CPI. OPTIONAL DMA (DIRECT MEMORY ACCESS) IOU. F i g u r e 1-1. Physical Characteristics Functional Characteristics To a c h i e v e h i g h computation s p e e d s , t h e computer system u s e s emitter-coupled High speed i s a l s o t h e l o g i c (ECL) and l a r g e - s c a l e i n t e g r a t i o n ( L S I ) l o g i c . o b j e c t i v e of t h e CP d e s i g n , which is based on t h e assumption t h a t both d a t a and i n s t r u c t i o n s a r e , i n most cases, a c c e s s e d from s u c c e s s i v e memory l o c a t i o n s . Accordingly, t h e CP p r e f e t c h e s b o t h i n s t r u c t i o n s and d a t a t h a t a r e expected t o be used n e x t w h i l e t h e c u r r e n t i n s t r u c t i o n i s being processed. The semiconductor c e n t r a l memory i s d i v i d e d i n t o e i g h t independent banks. These banks may a l l be s i m u l t a n e o u s l y i n t h e p r o c e s s of completing r e a d l w r i t e r e q u e s t s t h a t a r e queued and d i s t r i b u t e d a t ECL speeds. System i n p u t / o u t p u t speeds a r e determined by t h e c a p a b i l i t i e s of e x i s t i n g e x t e r n a l d e v i c e s . CP Characteristics Characteristics Central Processor The CP has the following characteristics. 60-bit internal word. Eight 60-bit operand (x) registers. Eight 18-bit address (A) registers. Eight 18-bit index (B) registers. Two registers that isolate each user's central memory space ( U C , FLC). TWO registers that isolate each user's extended memory space (RAE, FLE) Register exchange instructions (exchange jumps) for interrupting programs. Floating-point arithmetic (10-bit exponent plus sign bit, 48-bit Some FP instructions use 96-bit (doublecoefficient plus sign bit). precision) coefficients. Integer arithmetic (60/18-bit operands). Character string compare/move facilities (6-bit characters). Packed instructions (15/30/60-bit instructions in 60-bit words). Synchronous internal logic. 64-9 clock period. 2048-word cache buffer memory; option available for 4096-word cache. Instruction and branch instruction look-ahead. Microcode control. Parity checking of all major data and address paths. Maintenance channel to IOU. C M Characteristics Central Memory The CM has the following characteristics. 72-bit data word (60 data bits; 8 single-error correction, double-error detection bits; and 4 unused bits). 2097K words (16 Mbytes) of dynamic random access memory; options available to 167 76K words (128 Mbytes). Organization of eight independent banks. Two memory ports (located in the central processor cabinet). Bounds register to limit write access. 6411s clock period. Maximum data transfer rate of one word every 32 ns. 4643s read access time. 384-8 readhite cycle time. 768-8 partial write cycle time. Read and write data queuing capability. Single-error correction, double-error detection (SECDED) on stored data. Parity checking of all major data, address and control paths. Unified extended memory (UEM), which serves as extended memory within CM. IOU Characteristics InputIOutput Unit The LOU h a s t h e f o l l o w i n g c h a r a c t e r i s t i c s . Twenty p e r i p h e r a l p r o c e s s o r s ( P P s ) . Each PP h a s 4K o r 8K of independent memory (PPM) comprised of 16-bit words w i t h t h e upper 4 b i t s e q u a l t o 0 . P o r t t o c e n t r a l memory. Bounds r e g i s t e r t o l i m i t w r i t e s t o c e n t r a l memory. Twent y-f o u r 12-bit CYBER 170 c h a n n e l s t o e x t e r n a l d e v i c e s . Real-time c l o c k ( c h a n n e l 1 4 8 ) . D i s p l a y c o n t r o l l e r (CYBER 170 c h a n n e l 108). Two-port m u l t i p l e x e r ( c h a n n e l 1 5 8 ) . Maintenance c h a n n e l ( c h a n n e l 178). P a r i t y checking on a l l major d a t a and a d d r e s s p a t h s . O p e r a t i n g speed o f 250 ns and a minor c y c l e of 50 ns. O p t i o n a l c o n c u r r e n t i n p u t / o u t p u t (CIO) PPs and d i r e c t memory a c c e s s (DMA) 1/0 channel adapters. Major System Component Descriptions Major System Component Descriptions The major system components include: r Central processor (CP) 0 Central memory (CM) 0 ~nput/outputunit (IOU) r System console The remainder of the chapter provides brief descriptions of the major system components. The descriptions refer to the computer system block diagram (figure 1-2). Central Processor (CP) The central processor (CP) hardware (figure 1-2) consists of the following. 0 Instruction section. Registers. 0 Execution section. Cache memory. 0 Addressing section. 0 Central memory control. The CP is isolated from the IOU and, therefore, is able to carry on computation or character manipulation unencumbered by I/O requirements. Instruction Section The instruction section directs the arithmetic and manipulative functions for instruction execution. The instruction section prefetches instruction words from memory and disassembles them into instructions.. Major System Component Descriptions Registers Operating registers reduce storage accesses for operands used during the execution of an instruction. These registers are: Eight 60-bit X registers (XO through X7), which hold operands used for computation. Eight 18-bit A registers (A0 through A71, which use A0 primarily for indexing and Al through A7 for CM operand addressing. Eight 18-bit B registers (BO through B7), which are primarily indexing registers to control program execution. The BO register always contains all 0's. Eight support registers support the operating registers during program execution. These registers are: 18-bit program address (PI register. 21-bit reference address for CM (RAC) register. This is a program's lower bound. 21-bit field length for CM (FLC) register. This is a program's upper bound. 6-bit exit mode (EM) register. 6-bit flag register. 21-bit reference address for UEM (RAE) register. 24-bit field length for UEM (FLE) register. 18-bit monitor address (MA) register. The registers store data and control information, present operands to the execution section, and store results. The operating and support registers reside in the operand issue section. Major System Component Descriptions Execution Section The execution section combines the operands'to achieve the result. Cache Memory The cache memory consists of two sets of fast bipolar memory that are capable of storing 2048 60-bit words. Cache memory can be expanded to four sets of bipolar memory with a capacity of 4096 words. The memory addressing sections determine whether a requested word is in the cache memory. If the word is not, they read four consecutive words from central memory into the cache memory. Addressing Section The addressing section checks memory addresses against the CP registers RAC, FLC, RAE, and FLE to ensure isolation of user memory space. Central Memory Control . Central memory control (CMC) is integrated within the CP. CMC controls the flow of data between CM and requesting system components. Major System Component Descript~ons Central Memory (CM) The CM (figure 1-2) consists of the following items. Eight memory banks. Memory ports. Distributor. The CM is a dynamic random access memory organized into eight independent banks. A portion of CM can be reserved for use as extended memory. This portion, which is called unified extended memory (UEM), is referenced by the RAE and FLE registers. The UEM operates in either 24-bit format standard addressing mode or 30-bit format expanded addressing mode. One memory port has a queuing buffer. processor cabinet. The ports are located in the central The distributor resolves port conflicts and multiplexes data from ports to the storage unit. It includes the error correction code (ECC) generator, SECDED, and partial-write logic. The distributor is located in the central processor cabinet . Major System Component Descriptions I I I INSTRUCTIONS 1 I CENTRAL MEMORY ,I I I I INSTRUCTION SECTION CACHE MEMORY -- 1 REGISTERS . OPERANDS I -i -4 4 b EXECUTlON SECTION I ADDRESSING SECTION F 4 I I MAINTENANCE ACCESS CONTROL CENTRAL PROCESSOR ----------J MAINTENANCE CHANNEL MAINTENANCE CHANNEL MAINTENANCE CHANNEL r------------------ -1 I I SYSTEM 4 ! I I CONSOLE CONTROLLER Cr CYBER 170 I/OCHANNELS v v * . v , I PERIPHERAL PROCESSORS I L INPUTIOUTPUT U N I T + + RS 232.C INTERFACE Figure 1-2. System Block Diagram I I I Major System Component Descriptions InputIOutput Unit (IOU) The i n p u t / o u t p u t u n i t (IOU) c o n s i s t s o f : Twenty l o g i c a l l y i n d e p e n d e n t , non-concurrent i n p u t / o u t p u t (NIO) p e r i p h e r a l p r o c e s s o r s ( P P s ) , Options a r e a v a i l a b l e t o i n c r e a s e t h e t o t a l t o 25 o r 30 PPs . a F i v e o r t e n o p t i o n a l l o g i c a l 1y i n d e p e n d e n t , c o n c u r r e n t i n p u t / o u t p u t (CIO) PPs and direct-memory access (DMA) c h a n n e l a d a p t e r s . 0 I n t e r n a l i n t e r f a c e t o 24 1 / 0 c h a n n e l s . t h e t o t a l t o 34 c h a n n e l s . Options a r e a v a i l a b l e t o i n c r e a s e External i n t e r f a c e s t o 1 / 0 channels: - a 11 o r 23 CYBER 170 c h a n n e l i n t e r f a c e s . D i s p l a y c o n t r o l l e r i n t e r f a c e (CYBER 170 channel 108). - Two-port m u l t i p l e x e r i n t e r f a c e ( c h a n n e l 158). - Maintenance channel i n t e r f a c e ( c h a n n e l 178). Real-time c l o c k i n t e r f a c e ( c h a n n e l 148). I n t e r f a c e t o c e n t r a l memory. Bounds r e g i s t e r t o l i m i t w r i t e s t o CM. The PPs a r e o r g a n i z e d i n groups of f i v e , which a r e c a l l e d b a r r e l s . The PPs i n a b a r r e l time-share common hardware. Each PP h a s i t s own 4 K o r 8K i n d e p e n d e n t memory and communicates w i t h a l l 1 / 0 c h a n n e l s and w i t h c e n t r a l memory. System Console The system c o n s o l e , which i s r e q u i r e d f o r system o p e r a t i o n , p r o v i d e s a v i s u a l , alphanumeric r e a d o u t f o r t h e computer. The r e c e i p t of symbol and p o s i t i o n i n f o r m a t i o n from t h e computer e n a b l e s d i s p l a y i n g program i n f o r m a t i o n on a cathode-ray t u b e (CRT). The s t a t i o n a l s o c o n t a i n s an alphanumeric keyboard t h a t e n a b l e s a n o p e r a t o r t o send d a t a t o t h e computer. The keyboard and CRT combination p e r m i t s t h e computer o p e r a t o r t o monitor and c o n t r o l system o p e r a t i o n . Except f o r programming i n f o r m a t i o n i n c h a p t e r 5 , r e f e r t o t h e CDC 7 2 1 hardware r e f e r e n c e manual l i s t e d i n t h e p r e f a c e f o r f u r t h e r system c o n s o l e information. I I 2 Functional Descriptions Functional Descriptions T h i s c h a p t e r p r o v i d e s f u n c t i o n a l d e s c r i p t i o n s of t h e c e n t r a l p r o c e s s o r (CP), c e n t r a l memory (CM), and i n p u t l o u t p u t u n i t ( I O U ) as shown i n t h e b l o c k diagrams i n c h a p t e r 1. F u n c t i o n a l d e s c r i p t i o n s f o r t h e system d i s p l a y s t a t i o n a r e i n t h e CDC 721 hardware r e f e r e n c e manual; d e s c r i p t i o n s of t h e water-cooling system a r e i n t h e c o o l i n g system manual; b o t h manuals a r e l i s t e d i n t h e p r e f a c e . Central Processor The CP c o n s i s t s of t h e i n s t r u c t i o n s e c t i o n , r e g i s t e r s , t h e e x e c u t i o n s e c t i o n , cache memory, t h e a d d r e s s i n g s e c t i o n , and c e n t r a l memory c o n t r o l . Instruction Section The i n s t r u c t i o n s e c t i o n c o n s i s t s a f l o g i c f o r i n s t r u c t i o n c o n t r o l . lnstruction Lookahead The i n s t r u c t i o n lookahead hardware ( ILH) pref e t c h e s a maximum of 12 i n s t r u c t i o n s t o make t h e n e x t i n s t r u c t i o n immediately a v a i l a b l e when t h e execution of t h e p r e v i o u s i n s t r u c t i o n i s completed. T h i s i s accomplished by r e a d i n g i n s t r u c t i o n s from cache/CM i n t o a series o f b u f f e r r a n k s . The ILH responds t o both n e g a t i v e and p o s i t i v e r e s o l u t i o n of a c o n d i t i o n a l branch by purging t h e b u f f e r r a n k s and r e i n i t i a l i z i n g t h e i n s t r u c t i o n f e t c h unit. When ILH d e t e c t s a c o n d i t i o n a l branch, i t assumes t h a t t h e branch c o n d i t i o n w i l l be met. ILH computes t h e branch t a r g e t a d d r e s s and r e a d s i n s t r u c t i o n s from cache/CM s t a r t i n g a t t h e t a r g e t a d d r e s s . I f t h e branch i s t a k e n , t h e b u f f e r ranks c o n t a i n t h e n e x t e x e c u t a b l e i n s t r u c t i o n words. I f t h e branch i s not t a k e n , t h e hardware purges t h e b u f f e r ranks and resumes p r e f e t c h i n g a t t h e i n s t r u c t i o n word f o l l o w i n g t h e u n s a t i s f i e d branch i n s t r u c t i o n . Maintenance Access Control The maintenance a c c e s s c o n t r o l performs i n i t i a l i z a t i o n and maintenance o p e r a t i o n s i n t h e CP. Instruction Section l nstruction Control Sequences The instruction control section performs instruction translation and control sequences. Each control sequence obtains the necessary instruction operands from the operating registers and provides the control signals for execution. Instructions read from CM are 60-bit instruction words that are in four 15-bit groups, two 30-bit groups, or a combination of 15-bit and 30-bit groups. The 15-bit groups are termed parcels with the first parcel (parcel 0 ) being the highest-order 15 bits of a 60-bit CM word. Second, third, and fourth parcels (parcels 1, 2, and 3) follow in order. The 30-bit groups contain two 15-bit parcels. The instruction control sequences control the execution of one or more instructions of a common type. These sequences and associated instructions are briefly described in this chapter. For further information, refer to CP Instruction Descriptions in chapter 4. 8001ean Sequence The Boolean sequence controls instructions that require bit-by-bit data manipulation. This includes both the logical and transmissive operations. The instructions requiring logical operations are: * Xj + Xj - 11 Logical product (Xj) and (Xk) to Xi BXi Xj Xk 12 Logical sum of (Xj) and (Xk) to Xi BXi Xk 13 Logical difference of (Xj) and (Xk) to Xi BXi 15 Logical product of (Xj) with complement of (Xk) to Xi BXI -Xk * Xj 16 Logical sum of (Xj) with complement of (Xk) to Xi BXi -Xk + Xj 17 Logical difference of (Xj) with complement of (Xk) to Xi The instructions requiring transmissive operations are: 10 Transmit (Xj) to Xi BXI Xj 14 Transmit complement of (Xk) to Xi BXi - Xk Xk Instruction Section Shift Sequence The s h i f t sequence c o n t r o l s i n s t r u c t i o n s t h a t r e q u i r e s h i f t i n g t h e 60-bit f i e l d of d a t a w i t h i n t h e operand word. The s h i f t i n s t r u c t i o n s a r e : 20 Left s h i f t (Xi) by jk LXI jk 21 Right s h i f t ( x i ) by jk AXi jk 22 Left s h i f t (Xk) nominally (Bj) places t o X i LXi Bj, Xk 23 ) to X i Right s h i f t (Xk) nominalLy ( ~ j places AXI Bj, Xk 43 Form mask of jk b i t s t o X i M X i jk The s h i f t sequence a l s o c o n t r o l s t h e pack and unpack i n s t r u c t i o n s . I n t h e packed f l o a t i n g format, t h e c o e f f i c i e n t i s contained i n . t h e lower 48 b i t s . The s i g n and biased exponents a r e contained i n t h e upper 1 2 b i t s . The unpack i n s t r u c t i o n o b t a i n s the packed word from the Xk r e g i s t e r , d e l i v e r s the c o e f f i c i e n t t o t h e X i r e g i s t e r , and d e l i v e r s the exponent t o t h e Bj r e g i s t e r . The unpack and pack i n s t r u c t i o n s a r e : 26 Unpack (Xk) t o X i and Bj U X i Bj, Xk 27 Pack (Xk) and (Bj) t o X i PXi Bj, Xk The s h i f t sequence a l s o c o n t r o l s t h e normalize operations. The c o e f f i c i e n t p o r t i o n of t h e operand i s r e p o s i t i o n e d , and the exponent i s a d j u s t e d so that t h e most s i g n i f i c a n t b i t of t h e c o e f f i c i e n t i s i n t h e highest-order b i t p o s i t i o n of t h e c o e f f i c i e n t , and t h e exponent i s decreased by t h e number of b i t p o s i t i o n s s h i f t e d . The normalize i n s t r u c t i o n s are: 24 Normalize (Xk) t o X i and B j N X i Bj, Xk 25 Round normalize (Xk) t o X i and Bj Z X i Bj, Xk Instruction Section Floa ring-Add Sequence The floating-add sequence c o n t r o l s t h e o p e r a t i o n s necessary t o form t h e 48-bit f l o a t i n g sum with a 12-bit exponent of t h e f l o a t i n g - p o i n t sum o r d i f f e r e n c e of two f l o a t i n g - p o i n t operands. The fl o a ting-add i n s t r u c t i o n s a r e : 30 F l o a t i n g sum of (Xj) and ( ~ k )t o X i FXi X j + Xk 31 F l o a t i n g d i f f e r e n c e of ( X j ) and (Xk) t o X i F'Xi X j - Xk 32 F l o a t i n g double-precision sum of (Xj) and (Xk) t o X i DXI X j + Xk 33 F l o a t i n g double-precision (Xk) t o X i DXi X j - Xk 34 Round f l o a t i n g sum of (Xj) and (Xk) t o X i RXi X j + Xk 35 Round f l o a t i n g d i f f e r e n c e of (Xj) and (Xk) t o X i RXi X j - Xk d i f f e r e n c e of (Xj) and Floating-Multiply and Floating-Divide Sequence The f l o a t i n g - m u l t i p l y and f l o a t i n g - d i v i d e sequence c o n t r o l s the o p e r a t i o n of f l o a t i n g - m u l t i p l y , f l o a t i n g - d i v i d e , and population-count i n s t r u c t i o n s . The m u l t i p l y i n s t r u c t i o n s a r e : 40 F l o a t i n g product of (Xj) and (Xk) t o X i FXi Xj 41 Round f l o a t i n g product of ( ~ j and ) ( ~ k )t o X i R X i Xj 42 F l o a t i n g double-precision (Xk) t o X i DXi X j product of (X j ) and * * * The d i v i d e i n s t r u c t i o n s a r e : 44 F l o a t i n g d i v i d e (Xj) by (Xk) t o X i FXi X j / X k 45 Round f l o a t i n g d i v i d e (Xj) by (Xk) t o X i H i Xj/Xk The population-count i n s t r u c t i o n counts t h e number of 1 b i t s i n a 60-bit operand. The i n s t r u c t i o n is: 47 Population count of (Xk) t o X i C X i Xk Xk Xk Xk Instruction Section Increment Sequence The increment sequence c o n t r o l s t h e o n e ' s complement a d d i t i o n and s u b t r a c t i o n of 18-bit f i x e d - p o i n t operands f o r increment i n s t r u c t i o n s 50 through 77. The sequence a l s o c o n t r o l s t h e 6 0 - b i t o n e ' s complement sum and d i f f e r e n c e v a l u e s f o r long-add i n s t r u c t i o n s 36 and 37. The increment i n s t r u c t i o n s a r e : SAi Aj + K S e t Ai t o ( B j ) +K +K SAi B j + 52 S e t Ai t o (Xj) +K SAi X j + K 53 S e t A i t o (Xj) + (Bk) SAi X j + 54 S e t Ai t o ( A j ) + (Bk) 55 S e t Ai t o (Aj) - (Bk) 56 S e t Ai t o ( B j ) + (Bk) SAi Bj + Bk 57 S e t Ai t o ( B j ) - SAL Bj - 60 Set B i t o (Aj) SBi A j +K 61 Set B i t o (Bj) +K +K SBi B j + 62 Set B i t o (Xj) + K SBi X j + K 63 Set B i t o (Xj) + (Bk) SBi X j + Bk 64 S e t Bi t o ( A j ) + (Bk) SBi A j + Bk 65 S e t B i t o (Aj) - (Bk) SBi A j - Bk 66 Set B i t o (Bj) + (Bk) SBi B j + Bk 67 S e t B i t o (Bj) - (Bk) SBi Bj - Bk 70 Set X i t o (Aj) + K SXi Aj + K 71 Set X i t o ( ~ j + ) K SXi Bj + K 72 Set X i t o (Xj) + K SXi X j + K 73 Set X i t o ( X j ) + 74 Set X i t o (Aj) + (Bk) SXi A j + Bk 75 Set X i t o ( ~ j ) (Bk) SXi A j - 76 Set X i t o ( ~ j + ) ( ~ k ) 77 SetXito(Bj)-(Bk) 50 S e t Ai t o ( A j ) 51 (Bk) (Bk) K Bk Bk K SXi Xj + Bk Bk Instruction Section The long-add instructions are: 36 I n t e g e r sum of (Xj) and (Xk) t o X i 37 I n t e g e r d i f f e r e n c e of ( X j ) and (Xk) t o X i CompareIMove Sequence The compare/move sequence c o n t r o l s d a t a manipulation on a c h a r a c t e r b a s i s . The compare/move i n s t r u c t i o n s ( a l s o r e f e r r e d t o a s CMU i n s t r u c t i o n s ) a r e 60-bit i n s t r u c t i o n s t h a t use s i x support r e g i s t e r s f o r source and r e s u l t f i e l d CM a d d r e s s e s and c h a r a c t e r p o s i t i o n o f f s e t s . The support r e g i s t e r s load from t h e 60-bit i n s t r u c t i o n word. The compare/move i n s t r u c t i o n s a r e : + IM Bj 464 Move i n d i r e c t (Bj) 465 Move d i r e c t DM 466 Compare c o l l a t e d CC 467 Compare u n c o l l a t e d CU K + K The support r e g i s t e r s a r e : a An 18-bit l U r e g i s t e r t h a t s p e c i f i e s which r e l a t i v e CM a d d r e s s word c o n t a i n s t h e f i r s t c h a r a c t e r of t h e source d a t a f i e l d . An 18-bit K 2 r e g i s t e r t h a t s p e c i f i e s which r e l a t i v e CM a d d r e s s word c o n t a i n s t h e f i r s t c h a r a c t e r of t h e r e s u l t f i e l d . A &-bit C 1 r e g i s t e r t h a t s p e c i f i e s t h e c h a r a c t e r p o s i t i o n o r o f f s e t of t h e f i r s t CM word of t h e source f i e l d . A 4-bit C2 r e g i s t e r t h a t s p e c i f i e s t h e c h a r a c t e r p o s i t i o n o r o f f s e t of t h e f i r s t CM word of t h e r e s u l t f i e l d . Two 16-bit L r e g i s t e r s (LA and LC) t h a t s p e c i f y t h e number of c h a r a c t e r s i n t h e d a t a f i e l d . The LA r e g i s t e r i s a s s o c i a t e d with K1, and t h e LC r e g i s t e r i s a s s o c i a t e d with K2. I n s t r u c t i o n 464 u s e s 14 r e g i s t e r b i t s . I n s t r u c t i o n s 465, 4 6 6 , and 467 use only t h e lower 8 r e g i s t e r b i t s . NOTE CMU i n s t r u c t i o n s a r e provided f o r c o m p a t i b i l i t y with previous systems. For b e t t e r performance , recompile jobs t o avoid use of CMU i n s t r u c t i o n s . instruction Section CYBER 170 Exchange Sequence The CYBER 170 exchange sequence i s t h e method used t o swap jobs i n and o u t o f e x e c u t i o n . When a CYBER 170 exchange jump i n s t r u c t i o n o c c u r s , t h e CYBER 1 7 0 exchange sequence w r i t e s t h e c o n t e n t s of t h e c u r r e n t j o b ' s CP r e g i s t e r s ( d e s c r i b e d l a t e r in t h i s c h a p t e r ) i n t o an a r e a of c e n t r a l memory c a l l e d a CYBER 170 exchange package. A CYBER 170 exchange package i s a s s o c i a t e d w i t h each job. It c o n t a i n s s u f f i c i e n t i n f o r m a t i o n t o r e s t a r t a job i f t h e job i s To i n t e r r u p t e d d u r i n g e x e c u t i o n and swapped o u t by a CYBm 170 exchange jump. complete t h e sequence, CP r e g i s t e r s f o r a n o t h e r job a r e r e a d from i t s CYBER 170 exchange package, and t h a t job b e g i n s o r resumes e x e c u t i o n . For f u r t h e r i n f o r m a t i o n , r e f e r t o CYBER 170 Exchange Jump i n c h a p t e r 5 . Block Copy Sequence The block copy sequence c o n t r o l s t h e t r a n s f e r of d a t a between CM and UEM. The a d d i t i o n of K t o t h e c o n t e n t s of Bj determines t h e number o f words t o be t r a n s f e r r e d . The s t a r t i n g a d d r e s s f o r CM i s formed by adding e i t h e r t h e A 0 r e g i s t e r o r c e r t a i n b i t s of t h e XO r e g i s t e r t o t h e RAC r e f e r e n c e a d d r e s s . The s t a r t i n g a d d r e s s f o r UEM i s formed by adding c e r t a i n b i t s of t h e XO r e g i s t e r t o t h e RAE r e f e r e n c e a d d r e s s . The block copy i n s t r u c t i o n s a r e : OU Block copy B j +K 012 + Block copy Bj words from UEM t o CM BE B j + K K words from CM t o UEM WE B j + K Direct Read1 Write Sequence I n s t r u c t i o n s 014 and 015 perform single-word, d i r e c t r e a d and w r i t e o p e r a t i o n s f o r UEM, and i n s t r u c t i o n s 660 and 670 perform single-word, d i r e c t r e a d and w r i t e o p e r a t i o n s f o r c e n t r a l memory. + RAE) 014 Read one word from UEM a t (Xk 015 Write one word from X j t o U M a t (Xk 660 Read c e n t r a l memory a t (Xk) t o X j CRXj Xk 670 Write X j i n t o c e n t r a l memory a t ( X k ) CWXj Xk i n t o Xj R X j Xk + RAE) WXj Xk lnstruction Section Normal Jump Sequence The normal jump sequence c o n t r o l s t h e e x e c u t i o n of branch i n s t r u c t i o n s 02 through 07. The 02 i n s t r u c t i o n performs an u n c o n d i t i o n a l jump t o t h e B i r e g i s t e r a d d r e s s p l u s K. The branch a d d r e s s i s K when i e q u a l s 0. The 02 instruction is: The c o n d i t i o n a l jump i n s t r u c t i o n s 03 through 07 branch t o a d d r e s s K if t h e jump c o n d i t i o n i s m e t . These i n s t r u c t i o n s a r e : 030 Branch t o K i f ( X j ) = 0 ZR Xj, K 031 Branch t o K i f (Xj) f 0 NZ X j , K 032 Branch t o K i f ( X j ) i s p o s i t i v e PL X j , K 033 Branch t o K i f ( X j ) i s n e g a t i v e NG Xj, K 034 Branch t o K i f ( X j ) i s i n range IR X j , K 035 Branch t o K i f ( X j ) i s o u t of range OR Xj, K 036 Branch t o K i f ( X j ) i s d e f i n i t e DF Xj, K 037 Branch t o K i f ( X j ) i s i n d e f i n i t e I D Xj, K 04 Branch t o K i f ( B i ) = ( B j ) EQ B i , B j , K 05 Branch t o K i f ( B i ) # ( B j ) NE B i , B j , K 06 Branch t o K i f ( B i ) > (Bj) GE B i , Bj, K 07 Branch t o K i f ( B i ) < LT B i , Bj, K (Bj) Return Jump Sequence The r e t u r n jump sequence c o n t r o l s t h e e x e c u t i o n of t h r e e i n s t r u c t i o n s . 00 E r r o r e x i t t o MA o r program s t o p PS 010 Return jump t o K RJ K 013 C e n t r a l exchange jump t o ( B j ) exchange jump t o MA + K o r monitor XJBji-K Registers Registers The CP c o n t a i n s t h e o p e r a t i n g and s u p p o r t r e g i s t e r s d e s c r i b e d i n t h e f o l l o w i n g paragraphs. 1-2). These r e g i s t e r s a r e l o c a t e d i n t h e operand i s s u e s e c t i o n ( f i g u r e The c o n t e n t s of t h e s e r e g i s t e r s c a n be w r i t t e n i n t o memory and reloaded from memory a s a CYBER 3.70 exchange package by a s i n g l e CP i n s t r u c t i o n (CYBER 170 exchange jump). Figure 2-1 shows t h e CYBER 170 exchange package. The time a CYBER 170 exchange package r e s i d e s i n CP hardware i s c a l l e d an execution i n t e r v a l . During t h i s i n t e r v a l , CP i n s t r u c t i o n s c a n change t h e c o n t e n t s of X, A, B, and P r e g i s t e r s . The c o n t e n t s of o t h e r support r e g i s t e r s change only a s a r e s u l t of a CYBER 170 exchange jump. For f u r t h e r i n f o r m a t i o n , r e f e r t o CYBER 170 Exchange Jump i n c h a p t e r 5. N+3 EM N+4 ///A RAC A1 81 F LC A2 82 A3 83 A4 84 FLAGS RAE CM LOCATIONS NO HARDWARE REGISTERS EXIST Figure 2-1. CYBER 170 Exchange Package Registers Operating Registers The operating registers consist of operand (XI, address (A), and index ( B ) registers. These registers minimize memory references for arithmetic operands and results. X Registers The CP contains eight 60-bit X registers (XO through X7). The XO register is used in the compare instructions to indicate if two fields of characters are equal. Also, the XO register provides the relative UEM starting address in a block copy operation. Registers X 1 through X7 are primarily data-handling registers for computation. Registers X 1 through X5 are used to input data from CM, and registers X6 and X7 are used to transmit data to CM. Operands and results transfer between CM and the X registers as a result of placing CM addresses into corresponding A registers. Registers A Registers The CP contains eight 18-bit A registers (A0 through A 7 ) . The A0 register serves as an intermediate register for the user's discretion. The A0 register is used in the compare collate instruction for the collate table address. Also, the A0 register provides the relative CM starting address in a block copy operation. Registers Al through A7 are essentially CM operand address registers associated one-for-one with the X registers. Placing a quantity into an address register ( A l through A51 causes a CM read reference to that address and transmits the CM word to the corresponding X register (XIthrough X5). Similarly, placing a quantity into the A6 or A7 register causes the word in the corresponding X6 or X7 register to be written into that relative address of CM. 8 Registers The CP contains eight 18-bit B registers (BO through B 7 ) . These registers are primarily indexing registers to control program execution. Program loop counts may also be incremented or decremented in these registers. Program addresses may be modified on the way to an A register by adding or subtracting B register quantities. The B registers also hold shift counts for the nominal B j shifts, the resultant exponent for the unpack, the operand exponent for the pack, and the resultant shift count from a normalize. The BO register always contains 4, which can be used as an operand. This register cannot hold results from instructions. Support Registers Eight support registers assist the operating registers during programs execution. The contents of the support registers are stored in CM, and their new contents are loaded from CM during a CYBER 170 exchange sequence. With the exception of the P register, the contents of the support registers cannot be altered during the execution interval of a CYBER 170 exchange package. When the execution interval completes, the data in the support registers is sent back to CM through a CYBER 170 exchange jump. P Register The 18-bit program address (PI register loads from CM during the first word of a CYBER 170 exchange sequence and contains the current program execution address. The register serves as a program address counter and holds the relative CM address for each program step. Registers RA C Register The 21-bit CM reference address (RAC) register loads from CM during the second word of a CYBER 170 exchange sequence. An absolute CM address forms by adding RAC to a relative address determined by the instruction. The content of the P register is added to RAC to form the program address in CM. A P-equal-to-zero condition specifies relative address 0 and, therefore, (RAC). This CM location is reserved for recording error exit conditions and should not be used to store data or instructions. FLC Register The 21-bit CM field length (FLC) register Loads from CM during the third word of a CYBER 170 exchange sequence. The FLC register defines the size of the field of the program in execution. Relative CM addresses are compared with FLC to check that the program is not going out of its allocated memory range. EM Register The 6-bit exit mode (EM) register loads from CM during the fourth word of a CYBER 170 exchange sequence. The EM register holds six exit mode selection bits that control individual. error conditions for a program. Selected EM register bits cause the CP to error exit when the corresponding conditions occur. Any or all of the 6 bits can be set at one time. Clear EM register bits allow the CP to continue without error processing when most of the corresponding conditions occur. Refer to the error exit tables under Error Response in chapter 5 for specific cases. The exit mode selection bits appear in the exchange package as bits 48 through 50 and bits 57 through 59. The mode selection bits and their corresponding conditions are: Bit Significance 48 Address out of range 49 Infinite operand 50 Indefinite operand 57 Hardware error 58 Hardware error 59 Hardware error Registers Flag Register The 6-bit flag register loads from CM during the fourth word of a CYBER 170 exchange sequence. The flag register holds 6 bits that function as control flags. Bits Condition 51 Hardware error bit. 52 Instruction stack (lookahead) purge flag. If set, extended purging of instruction lookahead registers is enabled. For further information, refer to Instruction Lookahead Purge Control in chapter 5. 53 CMU interrupted flag. has been interrupted. operation is saved. 54 Block copy flag. If set, block copy instructions (011, 012) use bits 30 through 50 of XO rather than A0 to determine the CM address. For further information, refer to the descriptions of the block copy instructions in chapter 4. 55 Expanded addressing select flag. If set, UEM is operating in expanded addressing mode; if clear, UEM is operating in 24-bit standard addressing mode. For further information, refer to Addressing Modes under Memory Programming in chapter 5. - - -- - - -- - If set, one of instructions 464 through 467 The information necessary to resume UEM enable flag. If set, UEM is available. This flag must be set to allow 011, 012, 014, and 015 instructions to access UEM. Registers RAE Register The 21-bit UEM reference address (RAE) register loads from CM during the fifth word of a CYBER 170 exchange sequence. The lower 6 bits of this register are always 0. An absolute UEM address forms by adding RAE to the relative address, which is determined by the instruction. FLE Register The 24-bit UEM field length (FLE) register loads from CM during the sixth word of a CYBER 170 exchange sequence. The lower 6 bits of this register are always 0. The FLE register defines the size of the field in UEM for the program in execution. Relative UEM addresses are compared with FLE. MA Register The 18-bit monitor address (MA) register loads from CM during the seventh word of a CYBER 170 exchange sequence. The MA register contains the absolute starting address of an exchange package that is used when executing a central exchange jump (013) instruction with the CYBER 170 monitor flag clear or when honoring a monitor exchange jump to MA (262x1 instruction with the CYBER 170 monitor flag clear. For further information, refer to CYBER 170 Exchange Jump in chapter 5. Execution Section Execution Section The execution section combines the operands into results, providing additional sequencing control where necessary. Cache Memory Cache memory is a high-speed buffer memory that is transparent to the user. It reduces effective CM access time by eliminating unnecessary CM references. When the CP first reads CM, a block of 4 words from CM (containing the requested word) is read rapidly into cache memory. These words may be instructions or data. On subsequent reading of any of these words, CM does not have to be accessed when these words are in cache memory. Often this is the case because the same data is read more than once or because a loop o f instructions is repeatedly executed. Cache memory is 2048 words or, optionally, 4096 words. Addressing Section An addreas adder calculates memory addresses for data and unconditional jump instructions. Memory management hardware verifies that memory addresses are to access permitted memory areas. If this is the case, this hardware accesses cache memory and, if necessary, central memory. Central Memory Control Central memory control (CMC) provides an interface to CM for the CP and IOU. It is physically located in the CP cabinet. CMC includes: 0 Ports and distributor. SECDED logic. Partial-write Logic. 0 Memory control logic. Maintenance registers. Central Memory Central Memory The CM performs t h e following f u n c t i o n s . The e i g h t memory banks s t o r e from 2097K t o 16 7763 of 64-bit words ( t h e l e f t m o s t 4 b i t s a r e undefined) and an 8-bit SECDED code. The two p o r t s make CM a c c e s s i b l e t o t h e CP and every PP. A bounds r e g i s t e r limits a c c e s s t o CM from e i t h e r o r both p o r t s . The SECDED g e n e r a t o r s g e n e r a t e t h e SECDED code b i t s s t o r e d with each word. SECDED checks c i r c u i t s , c o r r e c t s s i n g l e - b i t e r r o r s , and d e t e c t s double-bit errors. The maintenance channel i n t e r f a c e g i v e s a PI? i n t h e I O U a c c e s s t o t h e CM maintenance r e g i s t e r s f o r system i n i t i a l i z a t i o n , c o r r e c t i v e a c t i o n , e r r o r r e p o r t i n g and d i a g n o s t i c s , and s e t t i n g t h e p o r t bounds r e g i s t e r . Address Format Figure 2-2 i l l u s t r a t e s t h e a d d r e s s format f o r t h e computer system. 23 22 21 20 r I L 32 12 11 I COLUMN ADDRESS I I R o w ADDRESS SELECT I 1 , CHlP ADDRESS CHlP SELECT QUADRANT SELECT Figure 2-2. BANK SELECT Address Format 0 I I Central Memory The following l i s t d e f i n e s t h e a d d r e s s f i e l d s f o r f i g u r e 2-2. Quadrant s e l e c t s p e c i f i e s one of f o u r quadrants ( a r r a y packs) w i t h i n a bank. Chip s e l e c t , i f s e t , enables t h e row a d d r e s s s e l e c t t o t h e upper h a l f ( 7 2 0 ) of t h e 144 c h i p s on memory boards i n a l l e i g h t memory banks. I f c l e a r , c h i p enable enables t h e lower h a l f of t h e 144 chips on memory boards i n all e i g h t banks. Chip a d d r e s s , which comprises column a d d r e s s s e l e c t and row a d d r e s s s e l e c t , s p e c i f i e s t h e a d d r e s s of 1 word on a c h i p f o r t h e s e l e c t e d bank and quadrant. Row address s e l e c t s p e c i f i e s t h e row-select a chip. p o r t i o n of t h e c h i p a d d r e s s on Column a d d r e s s s e l e c t s p e c i f i e s t h e column-select a d d r e s s on a chip. p o r t i o n of t h e c h i p Bank s e l e c t s p e c i f i e s one of e i g h t banks. CM Access and Cycle Times The following paragraphs l i s t CM a c c e s s and c y c l e times t h a t o p e r a t e on an i n t e r n a l clock period of 64 n s (major c y c l e ) . The CM a c c e s s time f o r a read o p e r a t i o n i s 320 ns ( f i v e major c y c l e s ) . One bank c y c l e f o r a read o r w r i t e o p e r a t i o n i s 384 ns ( s i x major c y c l e s ) . Cycle time f o r a p a r t i a l w r i t e (read/modify/write) i s 768 n s (12 major c y c l e s ) . Central Memory CM Ports and Priorities A priority network resolves access conflicts on a rotating basis, preventing long-term lockout of any port. In case of simultaneous requests, the CP has priority. The CM also has a refresh mechanism that may consume a maximum of 4 percent of memory time. Refresh requests have priority over port requests. Refer to table 2-1 for maximum request lockout time. Table 2-1. Maximum Request Lockout Time in Bank Cycles Port Read or Write Requests Refresh Port 0 Port 1 1 4 5 Note: One bank cycle equals six clock periods, which equals 384 ns. Central Memory SECDED Logic The SECDED l o g i c c o r r e c t s s i n g l e - b i t e r r o r s during a CM r e a d , permitting unimpeded computer operation. The SECDED l o g i c prepares f o r t h e e r r o r c o r r e c t i o n by generating e r r o r c o r r e c t i o n code (ECC) b i t s f o r each d a t a word and by s t o r i n g these ECC b i t s i n CM with t h e d a t a word durlng t h e CM w r i t e . Table 2-2 l i s t s t h e hexadecimal codes f o r d l t h e combinations of syndrome b i t s with t h e number of t h e d a t a b i t assigned t o each code o r a note c a t e g o r i z i n g t h e code. During a CM r e a d , CM then performs t h e following SECDED sequence. 1. Read 1 CM word and generate new ECC b i t s f o r d a t a p o r t i o n of CM word. 2. Compare new ECC b i t s with CM word ECC b i t s . 3. I f old and new ECC b i t s match, no e r r o r e x i s t s . requesting unit. 4. If b i t s do not match, generate syndrome b i t s from t h e r e s u l t of the ECC compare. 5. Decode syndrome b i t s t o determine i f a s i n g l e - o r m u l t i p l e - b i t f a i l u r e occurred. 6. I f a single-bit the d a t a word. 7. If a multiple-bit o r o t h e r uncorrectable e r r o r occurred, send the uncorrectable e r r o r response code t o t h e CP o r the IOU. A PP i n the IOU may then analyze the syndrome b i t s using t h e maintenance channel. Send d a t a t o the f a i l u r e occurred, c o r r e c t by i n v e r t i n g t h e f a i l i n g b i t i n Send the c o r r e c t e d word t o t h e r e q u e s t i n g u n i t . Central Memory Table 2-2. Code Bit SECDED Syndrome Codes/Corrected Bits Code Bit 20 66 @ Code Bit 40 65 code @ Bit 60 @ Code Bit 80 66 Code 0 @ 41 @ 61 @ 81 @ Al 22 @ 42 62 43 83 @ @ A2 @ @ @ 82 23 @ @ 4 @ A4 85 @ A5 @ 86 A6 0 87 88 24 0 25 @ 4 4 0 6 45 @ 4 0 @ 65 8 0 A0 21 63 Bit 0 @ 0 0 0 0 A3 26 @ 46 @ 66 27 67 @ 67 68 68 @ 69 48 @ 6B @ @ @ 89 4A @ @ @ 2B @ @ @ @ @ 8B @ @ @ @ @ @ 2C 0 4C @ 6C @ 8C @ AC 2D @ 4D 10 @ 6D @ 80 @ AD 13 @ 48 @ 4F @ @ 5 28 29 2A 2E 4 2F 19 30 6A 22 14 8A A7 8E @ 8F @ AF 70 0 90 @ BO @ 91 @ B1 @ 92 @ B2 0 93 @ 83 @ 94 @ B4 9 95 @ B5 96 @ B6 30 2/30 50 31 @ 51 @ @ 32 @ 52 @ 72 33 @ 53 @ 73 30 54 @ 74 35 @ @ 55 @ 75 58 36 @ 56 @ 76 62 56 71 60 57 @ 99 @ B9 49 3A @ @ 5A @ 7A 61 @ 9A @ BA 53 58 18 @ 78 @ 9B 17 @ BB 0 BC 0 BD 3E 4 3F 5D 0 5E @ 10 @ 9 2 7E @ 9E l @ 5F 0 @ 7F 63 @ 9F @ 51 BE BF EC Corrected single-bit 9 El7 @ 55 @ @ 40 Dl D2 44 07 EF Double error or multiple error (even number of code b i t s s e t ) . Multiple error reported as a s i n g l e error. @ @ F1 a F? @ F3 @ F4 @ F5 @ @ F7 31 @ D9 4 1 0 F9 @ DA 4 5 @ FA @ 0 DB @ DC @ @ DE @ DF 43 DD 47 0 0 0 0 FD 15 a FE 7 @ @ FF FB 23 @ Double error or w l t i p l t error or forced double error due t o a p a r t i a l write parity error on one of the 2 b y t e s indicated. @ No error detected. @ @ FC error. @ 3u FO @ Syndrome code b i t f a i l e d ( s i n g l e code b i t s e t ) . @ J5@ ED Notes: @ @ @ 79 9D 3 7 0 SB F8 @ 9C 3 3 Q 0 0 59 @ E9 D8 @ 0 E8 0 0 39 59 0 0 E7 F6 87 7D @ @ B8 7C @ 38 46 @ 0 34 E6 D6 0 5c €5 @ 98 @ DO 0 54 @ 0- CF @ @ 42 78 12 0 36 05 77 3D @ E3 54 @ @ 3C 11 3 C9 €2 50 @ 20 CD CE C8 0 0 Dl 58 38 @ @ 0 0 27 3 2 0 El 0 57 25 CC C7 EO 03 @ 97 0 C5 C6 Bit @ 52 0 26 C3 c4 @ 0 @ 38 28 C2 Code 0 0 0 0 0 0 0 48 @ @ 37 0 0 0 0 19 AB @ @ CB 0 @ 6 011 Cl @ AA 6F co CA @ 0 0 21 Bit 0 0 0 0 0 0 A9 A8 AE 6E 29 Code @ Central Memory CM Layout C e n t r a l memory c o n t a i n s an a r e a t h a t i s r e s e r v e d f o r s p e c i a l software c a l l e d V i r t u a l S t a t e software. Along with t h e hardware and microcode, t h i s s o f t w a r e handles t h e o p e r a t i o n s of V i r t u a l S t a t e a s d e s c r i b e d i n c h a p t e r 5. V i r t u a l S t a t e software i s l o c a t e d a t t h e h i g h e r end of memory. The remaining memory i s a v a i l a b l e t o t h e CYBER 170 S t a t e and may be a l l o c a t e d a s c e n t r a l memory ( a c c e s s i b l e v i a RAC and FLC) o r a s u n i f i e d extended memory ( a c c e s s i b l e v i a RAE, FLE, and t h e 011, 012, 014, and 015 i n s t r u c t i o n s ) . Refer t o f i g u r e 2-3. f Available CM size (optional) Actual CM size Software I Figure 2-3. CM Layout CM Bounds Register The CM bounds r e g i s t e r l i m i t s t h e w r i t e a c c e s s t o CM from s p e c i f i e d p o r t s . The p o r t s a r e l i m i t e d t o t h e a r e a between an upper and lower bound a s s p e c i f i e d i n t h e CM bounds r e g i s t e r . B i t s i n byte 0 s p e c i f y t h e p o r t ( s ) from which t h e w r i t e a c c e s s i s l i m i t e d . The CM bounds r e g i s t e r i s s e t through t h e maintenance For f u r t h e r i n f o r m a t i o n , r e f e r t o Maintenance Channel Programming i n channel c h a p t e r 5. . Central Memory Reconfiguration C e n t r a l memory r e c o n f i g u r a t i o n i s a manually performed f u n c t i o n t h a t p e r m i t s t h e computer o p e r a t o r t o r e s t r u c t u r e t h e CM a d d r e s s e s SG t h a t a f a i l i n g p a r t of CM can be q u i c k l y locked o u t t o provide a continuous block of u s a b l e CM. To accomplish CM r e c o n f i g u r a t i o n , s e t t h e s w i t c h e s on t h e memory u n i t t o manlpulate t h e upper address b i t s . When each c o n f i g u r a t i o n switch i s s e t , i t i n v e r t s a CM a d d r e s s b i t . T h i s i n v e r s i o n e f f e c t i v e l y moves blocks of bad memory t o t h e h i g h e s t memory block and moves blocks of good memory down, thereby, providing a s e q u e n t i a l l y a d d r e s s a b l e block of e r r o r - f r e e memory. I n c a s e of CM m a l f u n c t i o n s , t h e remaining good memory can be r e c o n f i g u r e d so i t i s a c c e s s i b l e by contiguous a d d r e s s e s from z e r o t o t h e maximum remaining a d d r e s s e s . For f u r t h e r i n f o r m a t i o n , r e f e r t o c h a p t e r 3. InputlOutput Unit InputlOutput Unit The input/output unit (IOU) performs the functions required to locate, select, and initialize the external devices connected to the system. The IOU controls the transfer of data between a selected device and CM. The IOU also performs system maintenance functions. The IOU contains the following functional areas. Peripheral processor (PP). I/O channels. Real-time clock. Two-port multiplexer. Maintenance channel. CM access. Peripheral Processor The basic IOU contains 20 PPs and 24 I/O channels. Each PP is a logically independent computer with its own memory. Each 5-PP group is organized into a multiplexing system that allows the PPs to share common hardware for arithmetic, logical, and I/O operations without losing independence. This multiplexing system comprises five ranks of registers, which is termed a barrel. Each rank contains information related to the instruction being executed by one PP. Each PP can communicate with the CP by issuing a CYBER 170 exchange request to a specific CYBER 170 exchange package associated with the issuing PP. In addition, a PP can also communicate with the CP via CM read and write operations. PPs can communicate with each other over the 110 channels and through CM. Each PP executes programs alone or with other PPs to control data transfers between external devices and CM. These programs are comprised of instructions from the IOU instruction set and respond to requests issued through CM by the operating system. The programs translate generalized operating system requests into c-ontrol functions for accessing the external devices and may also perform device scheduling and optimization. The programs use PP memory as a buffer for the data transfer between external devices and CM to isolate IOU data transfer from variations in CM transfer rate. An IOU upgrade is available which is an optional, concurrent input/output (CIO) subsystem consisting of five or ten P P s . Optional intelligent standard interface (ISI), intelligent peripheral interface (IPI), and CYBER 170 DMA (direct memory access) I/O channel adapters can be installed in the CIO. InputlOutput Unit Deadstart A d e a d s t a r t sequence allows t h e I O U t o i n i t i a l i z e i t s e l f . This d e a d s t a r t sequence i s i n i t i a t e d by t h e DEAD START switch on t h e system console (CC634 system console uses Control G Control R t o i n i t i a t e t h e d e a d s t a r t sequence). The d i s p l a y i n c l u d e s c o n t r o l s f o r a s s i g n i n g any PPM t o PPO. For f u r t h e r information, r e f e r t o chapter 3. Barrel and Slot The b a r r e l c o n s i s t s of t h e R, A, P, Q , and K r e g i s t e r s , each of which h a s f i v e Information i n t h e s e r e g i s t e r s ranks ( 0 through 4 ) . Refer t o f i g u r e 2-4. moves from one rank t o t h e next a t a uniform 20-MHz r a t e , providing a multiplexed system of f i v e PPs, each o p e r a t i n g a t a 4-MHz r a t e . The r e g i s t e r s a r e s t a t i o n a r y while t h e PPs r o t a t e . For example, rank 4 r e g i s t e r s c o n t a i n PPO, PPL, PP2, PP3, and PP4 i n s u c c e s s i o n , each of which consumes 50 n s of t h e t o t a l c y c l e time of 250 ns. Each time d a t a e n t e r s t h e s l o t , a p o r t i o n of t h e i n s t r u c t i o n f o r t h a t d a t a i s executed. The s l o t performs t a s k s such a s a r i t h m e t i c and l o g i c o p e r a t i o n s and program address manipulation. Complete execution of an i n s t r u c t i o n may r e q u i r e t h e R, A, P, Q , and K r e g i s t e r q u a n t i t i e s t o go more than one t r i p around t h e b a r r e l and through t h e s l o t . The PPM may be referenced once each time t h e PP passes around t h e b a r r e l and through t h e s l o t . During i t s s l o t time, t h e PP may a l s o communicate w i t h CM o r with any of t h e 1 / 0 channels. PP Registers The PP r e g i s t e r s , which a r e discussed i n t h e following paragraphs, a r e : 0 R register. A register. 0 P register. 0 Q register. 0 K register. InputlOutput Unit PP MEMORIES 4 1 INSTRUCTION hBARREL ID+ol TO OTHER FROM OTHER CENTRAL CENTRAL MEMORY 1641 --3 MEMORY (641 64-BIT WORD (161 PERIPHERAL EOUIPMENT @ I N SLOT 0 IS THE ADDRESS OF THE FIRST PP WORD Figure 2-4. Barrel and S l o t InputlOutput Unit R Register The 22-bit R r e g i s t e r , i n conjunction with t h e A r e g i s t e r , forms an a b s o l u t e CM a d d r e s s f o r CM r e a d / w r i t e i n s t r u c t i o n s . When b i t 17 of t h e A r e g i s t e r i s s e t , t h e a b s o l u t e CM a d d r e s s i s formed by appending s i x 0 ' s t o t h e lower end of t h e c o n t e n t s of t h e R r e g i s t e r and adding t o t h e r e s u l t b i t s 0 through 16 of t h e c o n t e n t s of t h e A r e g i s t e r ( r e f e r t o f i g u r e 2-5). Figure 2-5. Formation of Absolute CM Address A Register The 18-bit A r e g i s t e r h o l d s one operand f o r a r i t h m e t i c , l o g i c , o r s e l e c t e d 110 o p e r a t i o n s . The c o n t e n t of A may be a n a r i t h m e t i c o r l o g i c a l operand, CM address o r p a r t of a CM a d d r e s s (depending on b i t 1 7 ) , I/o f u n c t i o n , I/O d a t a word, o r a word count f o r block I / O i n s t r u c t i o n s . Various i n s t r u c t i o n s o p e r a t e on 6, 1 2 , 1 6 , o r 1 8 b i t s of t h e A r e g i s t e r . When t h e A r e g i s t e r i s used a s t h e CM a d d r e s s , p a r i t y i s generated f o r t r a n s m i s s i o n with t h e address t o memory c o n t r o l . At d e a d s t a r t , t h e A r e g i s t e r i s s e t t o 10000 ( o c t a l ) . When b i t 17 of t h e A r e g i s t e r i s c l e a r , t h e A r e g i s t e r i s used a s t h e CM a d d r e s s ; however, when b i t 1 7 i s s e t , t h e R r e g i s t e r i s added t o t h e A r e g i s t e r ( a s d e s c r i b e d i n t h e R r e g i s t e r d e s c r i p t i o n ) t o o b t a i n t h e a b s o l u t e CM a d d r e s s f o r CM r e a d l w r i t e i n s t r u c t i o n s . P Register The 16-bit P r e g i s t e r i s t h e program a d d r e s s r e g i s t e r , except during t h e execution of i n s t r u c t i o n s 61, 63, 7 1 , and 73. For t h e s e i n s t r u c t i o n s , t h e P r e g i s t e r c o n t a i n s t h e PPM a d d r e s s of t h e d a t a t r a n s f e r . A t d e a d s t a r t , t h e P r e g i s t e r i s s e t t o 0. InputlOutput Unit Q Register - The 16-bit Q r e g i s t e r holds d a t a f o r s e v e r a l functions such a s t h e address of t h e operand during d i r e c t addressing and i n d i r e c t addressing, t h e p e r i p h e r a l address of d a t a used during 1-word c e n t r a l read o r w r i t e i n s t r u c t i o n s , t h e upper 6 b i t s during constant mode i n s t r u c t i o n s , the channel number on a l l I/O and channel i n s t r u c t i o n s , t h e s h i f t count, and the r e l a t i v e jump d e s i g n a t o r . A t d e a d s t a r t , each rank of t h e Q r e g i s t e r i s s e t t o a corresponding PP number Rank 0 i s s e t t o PPO, rank 2 is s e t t o PP2, and so on. K Register The 7-bit K r e g i s t e r i s v i s i b l e t o t h e programmer through t h e maintenance channel only. This r e g i s t e r holds t h e o p e r a t i o n code f i e l d of an i n s t r u c t i o n f o r d i s p l a y on the IOU d e a d s t a r t console and f o r d e a d s t a r t console i n t e r r o g a t i o n . When a PP i s h a l t e d ( i d l e d ) , t h i s r e g i s t e r c o n t a i n s a l l 1 ' s . PP Numbering PPs a r e numbered a s follows: Barrel PPs 1 05 t o 11 ( o c t a l ) 2 20 t o 24 ( o c t a l ) 3 25 t o 31 ( o c t a l ) The The d e a d s t a r t sequence i s used t o determine PP numbering w i t h i n a b a r r e l . sequence a s s i g n s b a r r e l numbers according t o t h e IOU b a r r e l r e c o n f i g u r a t i o n parameter. During t h e f i r s t minor cycle a f t e r d e a d s t a r t , t h e sequence l o a d s a 0 i n t o the Q r e g i s t e r i n b a r r e l 0. This d e f i n e s a l l the d a t a i n t h a t rank of t h e b a r r e l a s belonging t o PPO, and s i n c e Q i s t h e channel s e l e c t o r , i t a s s i g n s PPO t o channel 0. During t h e next minor c y c l e , Q loads with a 1. This d e f i n e s PP1 and a s s i g n s i t t o channel 1. This process occurs i n p a r a l l e l i n a l l b a r r e l s u n t i l the I O U a s s i g n s each rank of each b a r r e l with a PP number and a channel number. Reassignment can be done only during a d e a d s t a r t . InputlOutput Unit PP Memory Each PP has an independent 4K or 8K word memory. Each word contains 16 data bits, with the upper 4 bits set to 0, and 6 SECDED bits. PPO executes the deadstart program from the microprocessor RAM during the deadstart operation. PP memory 0, therefore, must be operational. A PP memory reconfiguration feature allows the user to restore IOU operation if the IOU detects a fault in the PP memory normally assigned to PPO. To reconfigure, the operator assigns a good PP memory to PPO and the operating system removes the failing PP memory. Computer operation can continue without the failing PP memory, and repairs can be made during scheduled maintenance. The system must be deadstarted to reconfigure PPMs. I/O Channels The I/O channels are composed of: 0 An internal interface that allows common hardware and software to control the external devices, and 0 An external interface that allows the IOU to communicate with the external devices using 12-bit data channels. The internal interface can transfer 16-bit data words between two PPs or between a PP and an external device at a maximum rate of 1 word every 250 ns. This rate can be sustained for the maximum practical channel transfer (4096 words). During transfers between PPs, if the PPs are in the slot at the same time, the transfer rate is 500 ns. Any PP can access any of the CYBER 170 bidirectional 110 channels. All PPs communicate with external devices through the independent 1/0 channels. Each channel may be connected to one or more pieces of external equipment, but only one piece of equipment can use a channel at one time. All channels can be active simultaneously. Available channels are: Twenty-four CYBER 170 compatible I/O channels available with a maximum data transfer rate of 3 ~bytes/second. An optional, DMA-enhanced, intelligent standard interface (ISI) channel adapter, intelligent peripheral interface (IPI) channel adapter or CYBER 170 channel adapter that can be installed in any one of ten channel locations in the CIO cabinet. The adapters transfer data between the IS1 or CYBER 170 channel and PP memory using standard I/O instructions. They also support DMA transfer in which data goes directly between CM and an external device without going through the PP. There are two types of CYBER 170 DMA transfers, fast and normal. Fast transfers are used with the Extended Semiconductor Memory-11 (ESM-II), and normal transfers are used with other CYBER 170 external devices. 1 InputlOutput Unit The d i s p l a y s t a t i o n c o n t r o l l e r (DSC) i s a t t a c h e d t o CYBER 170 c h a n n e l lo8. The DSC i s t h e I O U i n t e r f a c e between t h e PPs and t h e s y s t e m c o n s o l e , s e r v i c i n z b o t h t h e keyboard and t h e cathode-ray t u b e (CRT). It t r a n s m i t s f u n c t i o n words and d i g i t a l symbol s i z e / p o s i t i o n d a t a t o t h e s y s t e m c o n s o l e , and r e c e i v e s It a l s o r e c e i v e s d i g i t a l symbol d i g i t a l c h a r a c t e r codes from t h e keyboard. codes from t h e PPs and c o n v e r t s t h e s e t o a n a l o g s i g n a l s t o t h e CRT. Real-Time Clock The r e a l - t i m e c l o c k i s a 1 2 - b i t , f r e e - r u n n i n g c o u n t e r , i n c r e m e n t i n g a t a 1-MHz r a t e . T h i s c h a n n e l may It i s permanently a t t a c h e d t o c h a n n e l 148. be r e a d a t any t i m e b e c a u s e i t s a c t i v e and f u l l f l a g s a r e a l w a y s s e t . Two-Port Multiplexer The two-port m u l t i p l e x e r p r o v i d e s communication c a p a b i l i t y between a PP and two attached terminals. One p o r t i s r e s e r v e d f o r m a i n t e n a n c e p u r p o s e s , and t h e The two-port m u l t i p l e x e r i s p e r m a n e n t l y o t h e r port is reserved f o r f u t u r e use. a t t a c h e d t o c h a n n e l 158. Maintenance Channel The m a i n t e n a n c e c h a n n e l i s used f o r i n i t i a l i z a t i o n of t h e CP and CM m a i n t e n a n c e r e g i s t e r s and m o n i t o r i n g o f e r r o r s t a t u s . The maintenance c h a n n e l c o n s i s t s o f t h e maintenance c h a n n e l i n t e r f a c e on c h a n n e l 178, a m a i n t e n a n c e a c c e s s c o n t r o l i n e a c h s y s t e m e l e m e n t , and a set of interconnecting cables. Central Memory Access Any PP c a n a c c e s s CM. During a w r i t e from t h e I O U t o CM, t h e I O U a s s e m b l e s f i v e s u c c e s s i v e 12-bit PP words i n t o a 6 4 - b i t CM word w i t h t h e l e f t m o s t 4 b i t s u n d e f i n e d , During a CM r e a d , t h e IOU d i s a s s e m b l e s t h e r i g h t m o s t 60 b i t s of t h e 6 4 - b i t CM word i n t o f i v e PP words. To f i n d t h e CM a d d r e s s , a PP r e a d s t h e A register. I f b i t 17 o f t h e A r e g i s t e r i s c l e a r , t h e PP u s e s t h e c o n t e n t s o f If b i t 17 o f t h e A r e g i s t e r i s s e t , t h e PP t h e A r e g i s t e r f o r t h e CM a d d r e s s . adds t h e r e l o c a t i o n a d d r e s s from t h e R r e g i s t e r t o t h e A r e g i s t e r t o form t h e CM a d d r e s s . A maximum o f 20 PPs i n v a r i o u s s t a g e s o f a s s e m b l y / d i s a s s e m b l y c a n s i m u l t a n e o u s l y r e a d CM words, and f i v e PPs c a n w r i t e CM words. 3 Operating Instructions Operating Instructions This chapter describes mainframe controls and indicators and the operating procedures that are hardware-dependent. Software-dependent procedures are in system software reference manuals listed in the preface. Controls and Indicators This chapter describes IOU deadstart controls and indicators and CM configuration switches that the system operator uses. Other controls that maintenance personnel use are described in the hardware operator's guide and the power distribution and warning system, the cooling system, and the CDC 721 manuals, which are listed in the preface. Deadstart Displays/Controls Pressing the deadstart puohbutton on the CC545 system console or pressing the CTRL G and CTRt R keys on the CC634B system console initiates deadstart and an initial deadstart display appears on the system control screen. The display is created by an independent microcomputer in the mainframe and does not rely on any program being operational in the PPs. The initial deadstart display is used to select a 16-word deadatart program for PPO and to initiate the deadstart sequence for PPO. The display is also used to reconfigure PPMs and barrels, and to display error status and maintenance information. Figure 3-1 shows the format of the deadstart options display, and figure 3-2 shows the deadstart display. Table 3-1 describes the two operator-selectable options and table 3-2 describes the operator entries and functions for the deadstart display. Other deadstart displays are available for maintenance use. Refer to the CYBER Instruction Package (CIP) listed in the preface for additional information. DEADSTART OPTIONS S M SYSTEM LOAD OPTIONS MAINTENANCE OPTIONS (CR) SYSTEM LOAD OPTIONS PROGRAM X SELECTED Figure 3-1. Deadstart Options Display Deadstart DisplayslControls DEADSTART - REV. XX YYYYYY=CHANGE DS PRG XX+YWYW=CHANGE DS PRG I N C $"SHORT DS L'LONG DS H=HELP 01 PPM CONF ' 00 N I O BRL CONF = 0 DLY LOOP = 0 LDS ADDR ' 6000 CLK FREQ = NORMAL N I O MEM SIZE ' 4 K PROGRAM 1 Figure 3-2. I n i t i a l Deadstart Display Deadstart DisplayslControls Table 3-1. Deadstart Options Display Option Description S S e l e c t s a s h o r t d e a d s t a r t sequence using t h e d e a d s t a r t program i d e n t i f i e d a t t h e bottom of t h e d i s p l a y . Upon completion of the d e a d s t a r t sequence a d i s p l a y f o r l o a d i n g system software a p p e a r s . M Causes t h e d e a d s t a r t d i s p l a y t o appear on t h e s c r e e n . Table 3-2. Deadstart Display Operator E n t r i e s and Functions Operator Entry YYYYYY Function Enters a s i n g l e word i n t h e d e a d s t a r t program a t xx t o a new value yyyyyy ( o c t a l ) . XX+YYYYYY Changes words i n t h e d e a d s t a r t program i n sequence s t a r t i n g a t xx. S S e l e c t s a s h o r t d e a d s t a r t sequence. L S e l e c t s a long d e a d s t a r t sequence. Brings up a d i s p l a y t h a t l i s t s and e x p l a i n s a l l a v a i l a b l e commands. Refer t o t h e Hardware Operator's Guide f o r d e t a i l e d information about t h e s e commands. Central Memory Controls Central Memory Controls The CM contains six two-position configuration switches (figure 3-3). These switches are located along the address interface pak switch in the A section of the memory cabinet. The switches are used to eliminate CM sections with malfunctions. Each switch, SWO through SW5, inverts the corresponding CM address bit (37 through 42). The inversion effectively moves blocks of bad memory to the highest memory block and moves blocks of good memory down, thereby providing a sequentially addressable block of error-free memory. Refer to table 3-3. In case of CM malfunctions, the remaining good memory can be reconfigured so it is accessible by contiguous addresses from zero to the maximum remaining address. This is accomplished by setting configuration switches (figure 3 - 3 ) as listed in table 3-3. Refer to the hardware operator's guide listed in the preface for further information. t INV "TM ADRS 6 ii 6 6 6 ADRS ADRS ADRS ADRS ADRS 42 --- -- - -- Figure 3-3. CM Configuration Switches Central Memory Controls Table 3-3. Central Memory Reconfiguration Reconfigured CM Original CM Reconfiguration Settings Size Words (MB) 8390 K ( 6 4 MB) AddressRange 0-37 777 777 Error-Free Size 4195 K ( 3 2 MB) SWO ADRS 37 ADRS 38 SW2 ADRS 39 D U D SWl SW3 ADRS 40 D SW4 ADRS 41 D SW5 ADRS 42 D Notes: 1. CM remaining can be further reconfigured to obtain larger contiguous blocks of error-free memory by setting additional configuration switches. See examples shown in figure 3-4. 2. U equgls up; D equals down. Normal setting of all switches is down. Central Memory Controls .. -- . SET SWO UP TO MOVE BLOCK OF MEMORY CONTAINING ERROR TO UPPER HALF OF MEMORY. 64 MBYTES 1/64 MBYTES// //(CONTAINS/ / /. I. /. ERROR) / I / I I SWO=UP 1/64 MBYTES// / / (CONTAINS1 / ///ERROR)/// 64 MBYTES I 64 MBYTES OF ERROR-FREE MEMORY I 128 MBYTES ERROR I N LOWER 64MBYTE BLOCK OF 128-MBYTE MEMORY. SET SW1 UP TO MOVE 32-MBYTES BLOCK CONTAINING ERROR TO NEXT HIGHER 32 MBYTES. THEN SET SWO UP TO MOVE BLOCK CONTAINING ERROR TO HIGHEST BLOCK OF MEMORY. 32 MBYTES SWl=UP 32 MBYTES SWO=UP 32 MBYTES 96-MBYTES OF ERROR-FREE MEMORY 32 MBYTES 132 MBYTES/ 32 MBYTES //l/lll///ll 128 MBYTES ERROR I N LOWEST 32-MBYTE BLOCK OF 128-MBYTE MEMORY. SET SW2 UP TO MOVE 16 MBYTE BLOCK CONTAINING ERROR TO NEXT HIGHER BLOCK. THEN SET SW1 UP TO MOVE 32 MBYTE BLOCK CONTAINING ERROR TO HIGHEST BLOCK OF MEMORY. 16 MBYTES 16 MBYTES 16 MBYTES 16 MBYTES 16 MBYTES 16 MBYTES 128 MBYTES ERROR I N LOWEST 16-MBYTE BLOCK OF UPPER HALF OF 128-MBYTE MEMORY Figure 3-4. Reconfiguration Examples 112-MBYTES OF ERROR-FREE MEMORY Power-On and Power-Off Procedures Power-On and Power-Off Procedures In Case of an emergency, use t h e system EMERGENCY OFF switch. The power-on and power-off procedures are described i n t h e hardware o p e r a t o r ' s guide l i s t e d i n t h e preface. CAUTION Improper a p p l i c a t i o n o r removal of power may damage system c i r c u i t s a n d l o r a i r - c o n d i t i o n i n g system. Power must be turned on/off by designated personnel. only, except f o r t h e system EMERGENCY OFF switch. Use o d y f o r extreme emergency and not f o r normal shutdown. Operating Procedures Refer t o t h e hardware o p e r a t o r ' s guide. The system i s i n i t i a l i z e d by s e t t i n g i t s d e a d s t a r t d i s p l a y c o n t r o l parameters and then by running e i t h e r a long or s h o r t d e a d s t a r t sequence (defined l a t e r i n t h i s c h a p t e r ) . A f t e r i n i t i a l i z a t i o n , t h e keyboard is used t o i n s t r u c t the system f u r t h e r under program control. Control Checks Before a c t i v a t i n g a long o r s h o r t d e a d s t a r t sequence, check t h e d e a d s t a r t d i s p l a y parameters a g a i n s t t h e i r intended use. The normal s e t t i n g s of t h e s e parameters a r e : Parameter Value PPM CONF 00 NIO BRL CONF 0 LDS ADDR 6000 Error messages None Operating Procedures Deadstart Sequences In response to a keyboard command (L or S) to the deadstart display, the IOU performs a deadstart sequence. Depending on the command (L or S), either the long or the short deadstart sequence is performed. The short deadstart sequence is used when hardware integrity verification is not required. The long deadstart sequence performs all the tasks performed by the short deadstart sequence and some additional tasks. The main additional task is the running of a diagnostic program, from a read-only memory (ROM) in the IOU on logical PPO. The diagnostic program takes approximately 15 seconds to run. Both deadstart sequences begin with a master clear, which sets up all P P s except logical PPO, for a 4096-word block input starting at PP location 0. The input into each PP is from the c h a ~ e lwith the same number as the logical number of the PP concerned. The master clear also resets all external devices and sets maintenance channel connect code bit 52. The individual registers are set as follows: Register Initialization Description K 0071008 Instruction display. Causes block input to start from location 0. A 10,O O O ~ Count of 4096 words, Q 0, 1, 2... I/O channel numbers (PPO: 0, PP1: 1, and so on). All registers in both barrels are set to these values, except the registers of PPO . If the long deadstart sequence is being performed, hardware clears location 7777 in all PP memories and sets the P register of PPO to the value indicated by tae parameter U S ADDR = xXXX (normally 6000s). PPO starts performing a test program from a read-only memory in IOU. Hardware errors cause the LDS program to hang before completion. In the absence of errors, execution When this happens, proceeds until the test program reaches location 7776 the unique part of the long deadstart sequence ends wgth a master cleat. . Next, both deadstart sequences clear PPO location 0, write the deadstart program on the display into PPO memory locations 1 to 208, and clear PPO location 21 PPO then starts executing the program entered from the deadstart dgsplay, which is normally a bootstrap program to input more data from an assigned external device. . The short deadstart sequence does not disturb PP memory other than PPO locations 0 to Zlg. Both deadstart sequences leave all PPs, except PPO, waiting for a block input or for action through the maintenance channel. After the block input is completed, each PP starts executing the program entered from whatever address was entered into location 0 of that PP. IOU Reconfiguration IOU Reconfiguration The logical PP numbers and hardware are assigned to physical PPs circularly from the settings of IOU deadstart display PPM CONF and BRL CONF parameters, specifying which physical barrel and PPM is PPO. Maximum values for these parameters depend on the number of PPs installed (table 3 - 4 ) . Illegal values entered in BB X and RP XX commands are rejected by the deadstart display and cause error messages to appear on the acreen (refer to the hardware operator's guide). ~econfi~uration i s discussed in detail in the hardware operator's guide. Tables 3-5 and 3-6 show allowable values for the PPM CONF and BRL CONF parameters and reconfiguration examples. Table 3 - 4 . Barrel Numbering Table Logical PPs in Physical Barrel With BARREL RECONFIGURATION Switch Values Barrels Installed Four Barrels (20 PPs) Physical Barrel 0 1 2 3 IOU Reconfiguration Table 3-5. No. of PP6 Notes: 1. RP 2. 3. KB Logical PP FiB-2 Logical PP RE-1 Logical PP RB-0 Phyaical PPMs in Each Barrel BARO BARl BARZ BAR3 BAR0 BARl BAR2 BAR3 BAR0 BARl BAR2 BAR3 BAR0 BARl BAR2 BAR3 04 04 11 24 31 31 04 11 24 24 31 04 11 11 24 31 04 Logical PP 0-3 - PP Configuration. NIO Barrel Configuration o d y . BAR 0-3 are the physical barrels. = Table 3-6. No. of PPs PP and Barrel Reconfiguration Example, RPIO Physical PPMs in Each Barrel - PP and Barrel Reconfiguration Example, RPa2 BAR0 Logical PP Logical PP RB4) RB-1 BARl ... W = PP Configuration. 2. 3. BAR BAR2 BAR3 AD = IOU Barrel Configuration only. 0-3 are t h e physical barrels. BAR0 BARJ. BAR2 Logical PP RB-2 BAR3 BAR0 B.4IJ.l BAR2 Logical PP RB-3 BAR3 BAR0 BAR1 BAR2 BAR3 4 Instruction Descriptions Instruction Descriptions This c h a p t e r c o n t a i n s t h e CYBm 170 S t a t e CP i n s t r u c t i o n d e s c r i p t i o n s and PP instruction descriptions. CP Instruction-Formats NOTE CYBER 170 CP i n s t r u c t i o n s use t h e r i g h t m o s t 60 b i t s i n t h e 64-bit word. The l e f t m o s t 4 b i t s a r e undefined. For t h e s e i n s t r u c t i o n s , t h e m o s t - s i g n i f i c a n t b i t i s b i t 59 and t h e l e a s t s i g n i f i c a n t b i t i s b i t 0. Program i n s t r u c t i o n words a r e divided i n t o 15-bit f i e l d s c a l l e d p a r c e l s . The f i r s t p a r c e l ( p a r c e l 0) i s t h e highest-order 1 5 b i t s of t h e 60-bit word. The second, t h i r d , and f o u r t h p a r c e l s ( p a r c e l s 1, 2 , and 3) f o l l o w i n order. Figure 4-1 shows p o s s i b l e p a r c e l arrangements f o r i n s t r u c t i o n s w i t h i n a program i n s t r u c t i o n word. An i n s t r u c t i o n may occupy one, two, o r f o u r p a r c e l s . This arrangement depends on t h e i n s t r u c t i o n format. When an i n s t r u c t i o n occupies two p a r c e l s , i t must occupy two p a r c e l s w i t h i n t h e same program word. A program word may be f i l l e d with a one-parcel pass i n s t r u c t i o n o r an i n s t r u c t i o n a c t i n g a s a two-parcel pass i n s t r u c t i o n . These i n s t r u c t i o n s a r e used t o f i l l a program word when necessary t o p l a c e a p a r t i c u l a r i n s t r u c t i o n i n t h e f i r s t p a r c e l of a program word o r t o avoid s t a r t i n g a two-parcel i n s t r u c t i o n i n t h e f o u r t h p a r c e l of a program word. Pass i n s t r u c t i o n s may a l s o be used f o r branch e n t r y p o i n t s because a branch i n s t r u c t i o n d e s t i n a t i o n address must begin w i t h a new word. One-parcel pass i n s t r u c t i o n s a r e 460xx through 463xx. I n s t r u c t i o n s 60xxx through 62xxx may be used as two-parcel pass i n s t r u c t i o n s by s e t t i n g t h e i i n s t r u c t i o n d e s i g n a t o r t o 0. Refer t o t a b l e 4-1 f o r CP i n s t r u c t i o n d e s i g n a t o r s . CP i n s t r u c t i o n s 011 and 012 have s p e c i a l p r o p e r t i e s . They a r e 60-bit double i n s t r u c t i o n s t h a t musr s t a r t a t p a r c e l 0. The programmer has t h e 0pri0n of providing a branch i n s t r u c t i o n a t p a r c e l s 2 and 3 i n t h e same i n s t r u c t i o n word ( t o an error-handling software r o u t i n e ) o r f i l l i n g t h i s space w i t h pass i n s t r u c t i o n s . Refer t o i n s t r u c t i o n s 011 and 012. I n s t r u c t i o n s 013 and 464 through 467 a r e 60-bit i n s t r u c t i o n s which must s t a r t a t p a r c e l 0. They ignore any information i n p a r c e l s 2 and 3; however, t h e s e p a r c e l s a r e normally s e t t o a l l 0 ' s . CP Instruction Formats INSTRUCTION COMBINATIONS 59 29 44 - 15 15 PARCEL 0 59 29 30 2nd OPERAND REGISTER (1 of 8) 1st OPERAND REGISTER (1 of 8) LRESULT REGISTER (1 of 8) OPERATION CODE List OPERAND REGISTER (1 of 8) RESULT REGISTER (1 of 81 OPERATION CODE Figure 4-1. CP Instruction Parcel Arrangement Instruction Description Nomenclature lnstruction Description Nomenclature The instruction descriptions in this chapter use the following instruction designators. Designator Description 6-bit/9-bit field specifying instruction operation code. 3-bit code specifying one of eight registers. 6-bit code specifying amount of shift or mask. 18-bit operand or addresss. Unused designator. One of eight 18-bit address registers. One of eight 18-bit index registers; BO is fixed and equal to 0. One of eight 60-bit operand registers. Content o f the word at a central memory address. Offset (character address) of the first character in the first word of the source field. Character address of the first character in the first word o f the result field. Klt 18-bit address indicating the central memory location of the first (leftmost) character o f the source field. 18-bit address indicating the central memory location of the first (leftmost) character of the result field. Lower 4 bits of the field length (character count) for a move or compare instruction; used with LU to specify field length. Upper 9 bits of the field length; (character count) for indirect move instruction or the upper 3 bits for direct instructions; used with LL to specify field length. t~pplicableto compare/move instructions only. CP Operating Modes CP Operating Modes The CP executes instructions in CYBER 170 job mode, CYBW 170 monitor mode, and executive state. Changes between CYBER 170 job mode and CYBER 170 monitor mode are caused by CYBW 170 exchange jumps (CP instruction 013 and PP instructions 2600, 2610, and 2620). A hardware flag called the C Y B W 170 monitor flag (MF) indicates whether the CP is in CYBER 170 job mode (flag is clear) or in CYBER 170 monitor mode (flag is set). The executive state is invisible to the applications programmer. It s e t s up the CYBER 170 environment during initialization, executes certain instructions, and handles hardware-detected error conditions. Hardware-caused exchanges are called error exits. Most of these can be enabled or disabled by setting or clearing bits in the CYBER 170 exchange package. For further information on CP operating modes, refer to CYBER 170 Exchange Jump, Executive State, and Error Response in chapter 5 . CP lnteger Arithmetic Instructions CP Instruction Descriptions The CP general instructions are divided into 16 subgroups as follows: 0 Integer Arithmetic 0 Branch Block Copy 0 Shift a Logical 0 Floating Point 0 Jump Exchange/Jump rn ~ompare/~ove rn Set 0 Normalize Pass Illegal Instruction a Mask rn Pop Count Read Free Running Counter CP lnteger Arithmetic lnstructions The integer arithmetic instructions (table 4-1) perform integer arithmetic on signed two's complement words or half words in Xk or XkR. The sign bit is bit 0 for full-word integers or bit 32 for half-word integers. Table 4-1. CP Integer Arithmetic Instructions - . . Opcode Format Instruction Mnemonic 27 26 36 37 ijk ijk Uk 1jk Pack (~k)and (Bj) to Xi Unpack (Xk) to Xi and Bj Integer sum of (Xj) and (Xlc) to Xi Integer difference of (Xj) and (Xk) to Xi PXi Bj Xk UXi Bj Xk IXi Xj+Xk IXi Xj-Xk CP Integer Arithmetic Instructions lnteger Pack/Unpack 27ijk Pack (Xk) and (Bj) t o X i PXi B j , Xk This i n s t r u c t i o n r e a d s t h e c o n t e n t s of Xk and B j , packs them i n t o a s i n g l e word i n f l o a t i n g - p o i n t format, and d e l i v e r s t h i s r e s u l t t o X i . The c o e f f i c i e n t f o r t h e value i n X i i s obtained from t h e c o n t e n t of Xk, which is t r e a t e d as a signed i n t e g e r . The exponent f o r t h e v a l u e i n X i i s obtained from t h e c o n t e n t of B j , which i s t r e a t e d a s a signed i n t e g e r . The lowest-order 48 b i t s i n X i a r e copied d i r e c t l y from t h e lowest-order 48 b i t s i n Xk. The s i g n b i t i n X i is copied d i r e c t l y from t h e s i g n b i t i n Xk. The exponent f i e l d i n X i i s derived from t h e v a l u e i n Bj by e x t r a c t i n g t h e lowest-order 11 b i t s i n Bj and modifying t h i s q u a n t i t y f o r exponent b i a s and c o e f f i c i e n t sign. Four sample s e t s of operands and packed r e s u l t s a r e l i s t e d i n o c t a l n o t a t i o n t o i l l u s t r a t e t h e o p e r a t i o n performed. These examples c o n t a i n t h e f o u r combinat i o n s of c o e f f i c i e n t s i g n and exponent sign. ( X i ) = 2034 4500 3333 2000 0077 (Xi) = 5743 3277 4444 5777 7700 (Bj) = 77 7743 (Xi) = 6034 3277 4444 5777 7700 This i n s t r u c t i o n c o n v e r t s a number i n fixed-point format t o f l o a t i n g - p o i n t format. For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n c h a p t e r 5 . CP Integer Arithmetic Instructions Unpack ( X k ) t o X i and Bj U X i Bj, Xk This i n s t r u c t i o n r e a d s one operand from Xk, unpacks t h i s word from f l o a t i n g point format, and d e l i v e r s t h e c o e f f i c i e n t and exponents t o X i and B j , r e s p e c t i v e l y . The 60-bit word d e l i v e r e d t o X i c o n s i s t s of t h e lowest 48 b i t s u n a l t e r e d from t h e o r i g i n a l operand p l u s t h e upper 1 2 b i t s , each equal t o t h e o r i g i n a l s i g n b i t . This is a signed i n t e g e r equal t o t h e value of t h e c o e f f i c i e n t i n t h e o r i g i n a l operand. The 18-bit q u a n t i t y d e l i v e r e d t o B j i s a signed i n t e g e r equal t o t h e value of the exponent i n the o r i g i n a l operand. The 11-bit exponent f i e l d i n t h e operand i s a l t e r e d t o remove t h e b i a s and then sign-extended t o f i l l out t h e 18-bit q u a n t i t y . The s i g n of t h e c o e f f i c i e n t i s removed i n t h i s process. Four sample s e t s of operands and unpacked r e s u l t s a r e l i s t e d i n o c t a l n o t a t i o n t o i l l u s t r a t e the o p e r a t i o n performed. These examples c o n t a i n the four combinations of c o e f f i c i e n t s i g n and exponent sign. ( x i ) = 0000 4500 3333 2000 0077 (Xi) = 7777 3277 4444 5777 7700 This i n s t r u c t i o n converts a number from floating-point format t o fixed-point format. For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n chapter 5. CP Integer Arithmetic Instructions 36ijk I n t e g e r sum of (Xj) and (Xk) t o X i 98 14 I 36 0 65 32 i j k This i n s t r u c t i o n reads operands from two X r e g i s t e r s , o p e r a t e s on them t o form a 60-bit i n t e g e r sum, and d e l i v e r s t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t i o n a r e i n X j and Xk. These operands a r e signed Overflow i s not i n t e g e r s . The r e s u l t i n g i n t e g e r sum i s d e l i v e r e d t o X i . detected. This i n s t r u c t i o n adds i n t e g e r s too l a r g e f o r handling by 50 through 77 i n s t r u c t i o n s . The i n s t r u c t i o n a l s o merges and compares d a t a f i e l d s during d a t a processing. For f u r t h e r information, r e f e r t o I n t e g e r Arithmetic under CP Programming i n chapter 5. 37ijk I n t e g e r d i f f e r e n c e of ( ~ j )and (Xk) t o X i This i n s t r u c t i o n r e a d s operands from two X r e g i s t e r s , o p e r a t e s on them t o form a 60-bit i n t e g e r d i f f e r e n c e , and d e l i v e r s t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t i o n a r e i n X j and Xk. These operands a r e signed i n t e g e r s . The r e s u l t of s u b t r a c t i n g t h e q u a n t i t y i n Xk from t h e q u a n t i t y i n X j i s delivered t o X i . Overflow i s not detected. This i n s t r u c t i o n s u b t r a c t s i n t e g e r s too l a r g e f o r handling by 50 through 77 i n s t r u c t i o n s . The i n s t r u c t i o n a l s o compares d a t a f i e l d s during d a t a processing. For f u r t h e r information, r e f e r t o I n t e g e r Arithmetic under CP Programming i n chapter 5. CP Branch Instructions CP Branch lnstructions The branch i n s t r u c t i o n s ( t a b l e 4-2) c o n s i s t of both c o n d i t i o n a l and u n c o n d i t i o n a l branch i n s t r u c t i o n s . Each c o n d i t i o n a l branch i n s t r u c t i o n compares t h e c o n t e n t s of two g e n e r a l r e g i s t e r s t o determine whether a normal o r a branch e x i t i s taken. Table 4-2. CP Branch I n s t r u c t i o n s Opcode Format Instruction 030 03 1 032 033 034 jK jK jK jK jK jK jK jK jK Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch Branch 035 036 037 04 i 051 06i 07i jK jK jK Mnemonic t o K i f (Xj) = 0 t o K i f (Xj) # 0 t o K i f (Xj) i s p o s i t i v e t o K i f (Xj) i s negative to to to to to to to to K K K K K K K if if if if if if if K if ( Xj) i s i n range (Xj) (Xj) (Xj) (Bi) (Bi) (Bi) (Bi) i s o u t of range is definite is indefinite = (Bj) (Bj) > (Bj) (Bj) ZR NZ PL NG IR OR DF ID EQ NE GE LT CP Branch Instructions Branch 030 j K ZR Xj, K Branch t o K i f (Xj ) = 0 This two-parcel i n s t r u c t i o n u s e s t h e lower-order 18 b i t s a s operand K. Execution of t h i s i n s t r u c t i o n causes t h e program sequence t o terminate with a jump t o addreas K i n CM o r t o continue with t h e c u r r e n t program sequence, depending on t h e content of Xj. The branch t o address K occurs only on t h e following conditions. The c u r r e n t program sequence continues f o r a l l o t h e r cases. Jump t o K i f : (Xj) = 0000 0000 0000 0000 0000 ( p o s i t i v e z e r o ) ( ~ j = ) 7777 7777 7777 7777 7777 ( n e g a t i v e zero) This i n s t r u c t i o n branches on a zero r e s u l t from e i t h e r a fixed-point o r a floating-point operation. 031j K Branch t o K i f (Xj) " 0 NZ X j , K This two-parcel i n s t r u c t i o n uses t h e lower-order 18 b i t s a s operand K. Execution of t h i s i n s t r u c t i o n causes t h e program sequence t o terminate with a jump t o address K i n CM o r t o continue with t h e c u r r e n t program sequence, depending on the content of X j . The program sequence continues only on t h e following conditions. The branch t o address K occurs f o r a l l o t h e r c a s e s . Continue i f : (Xj) = 0000 0000 0000 0000 0000 ( p o s i t i v e zero) (Xj) = 7777 7777 7777 7777 7777 (negative zero) This i n s t r u c t i o n branches on a nonzero r e s u l t from e i t h e r a fixed-point o r a floating-point operation. CP Branch instructions Branch t o K i f (Xj) i s P o s i t i v e PL X j , K This two-parcel i n s t r u c t i o n uses t h e lower-order 18 b i t s a s operand K. Execution of t h i s i n s t r u c t i o n causes t h e program sequence t o terminate with a jump t o address K i n CM o r t o continue with t h e c u r r e n t program sequence, The branch d e c i s i o n f o r t h i s i n s t r u c t i o n i s depending on t h e content of X j . based on t h e value of t h e sign b i t i n X j . Jump t o K i f : B i t 59 of X j = 0 ( p o s i t i v e ) 1 (negative) Continue i f : B i t 59 of X j This i n s t r u c t i o n branches on a p o s i t i v e r e s u l t from e i t h e r a fixed-point f l o a t i n g - p o i n t operation. 033 j K Branch t o K i f (Xj) i s Negative or a NG X j , K This two-parcel i n s t r u c t i o n uses the lower-order 18 b i t s as operand K. Execution of t h i s i n s t r u c t i o n causes t h e program sequence t o terminate with a jump t o address K i n CM o r t o continue with t h e c u r r e n t program sequence, depending on t h e content of X j . The branch d e c i s i o n f o r t h i s i n s t r u c t i o n i s based on t h e value of t h e s i g n b i t i n X j . Jump t o K i f : B i t 59 of X j = 1 ( n e g a t i v e ) Continue i f : B i t 59 of X j = 0 ( p o s i t i v e ) This i n s t r u c t i o n branches on a negative r e s u l t from e i t h e r a fixed-point o r a floating-point operation. CP Branch Instructions 034jK Branch to K if (Xj) is in range IR Xj, K This two-parcel instruction uses the lower-order 18 bits as operand K. Execution of this instruction causes the program sequence to terminate with a jump to address K in CM or to continue with the current program sequence, depending on the content of Xj. The program sequence continues only on the following conditions. The branch to address K occurs for all other cases. Continue if: (Xj) = 3777 xxxx xmrx xxxx xxxx (positive overflow) (Xj) = 4000 xxxx xxxx xxxx xxxx (negative overflow) This instruction branches on a floating-point quantity within the floatingpoint range. The value of the coefficient is ignored in making this branch test. Ari underflow quantity is considered in range for purposes of this test. 035jK Branch to K if (Xj) is out of range OR Xj, K This two-parcel instruction uses the lower-order 18 bits as operand K. Execution of this instruction causes the program sequence to terminate with a jump to address K in CM or to continue with the current program sequence, depending on the content of Xj. The branch to address K occurs only on the following conditions. The current program sequence continues for all other cases. Jump to K if: ( ~ j )= 3777 xxxx xxxx xxxx xxxx (positive overflow) (Xj) a 4000 xxxx xxxx xxxx xxxx (negative overflow) Branch to K if (Xj) is definite DF Xj, K This two-parcel instruction uses the lower-order 18 bits as operand K. Execution of this instruction causes the program sequence to terminate with a jump to address K in CM or to continue with the current program sequence, depending on the content of Xj. The program sequence continues only on the following conditions. The branch to address K occurs for all other cases. Continue if: (Xj) = 1777 xxxx xxxx xxxx xxxx (positive indefinite) (Xj) = 6000 XMM xxxx xxxx xxxx (negative indefinite) This instruction branches on a floating-point quantity that may be out of range but is still defined. The value of the coefficient is ignored in making this branch test. An overflow quantity or an underflow quantity is considered defined for purposes of this test. CP Branch Instructions Branch to K if (Xj) is indefinite ID X j , K This two-parcel instruction uses the lower-order 18 bits as operand K. Execution of this instruction causes the program sequence to terminate with a jump to address K in CM or to continue with the current program sequence, depending on the content of the Xj register. The branch to address K occurs only on the following conditions. The current program sequence continues for all other cases. Jump to K if: (Xj) = 1777 xxxx xxxx xxxx xxxx (positive indefinite) (Xj) = 6000 murx xxxx xxxx xxxx (negative indefinite) This instruction branches on a floating-point quantity that is not defined. The value of the coefficient is ignored in making this branch rest. An overflow quantity or an underflow quantity is considered defined for purposes of this test. O4i jK Branch to K if (Bi) (Bj) EQ Bi, Bj, K This two-parcel instruction uses the lower-order 18 bits as operand K. Execution of this instruction causes the program sequence to terminate with a jump to address K in CM or to continue with the current program sequence, depending on a comparison of the contents of the Bi and Bj registers. The branch to address K occurs only if the two quantities are identical on a bit-by-bit comparison basis. The current program sequence continues for all other cases. This instruction branches on an index equality test. A quantity consisting of all 0's and a quantity consisting of all 1's are not equal for this test. CP Branch instructions 0 5 i jK Branch t o K i f ( B i ) # ( B j ) NE B i , Bj, K This two-parcel i n s t r u c t i o n u s e s t h e lower-order 18 b i t s a s operand K. Execution of c h i s i n s t r u c t i o n c a u s e s t h e program sequence t o t e r m i n a t e w i t h a jump t o a d d r e s s K i n CM o r t o c o n t i n u e w i t h t h e c u r r e n t program sequence, The depending on a comparison of t h e c o n t e n t s of t h e B i and B j r e g i s t e r s . Program sequence c o n t i n u e s only i f t h e two q u a n t i t i e s a r e i d e n t i c a l on a b i t - b y - b i t comparison b a s i s . The branch t o a d d r e s s K o c c u r s f o r a l l o t h e r cases. This i n s t r u c t i o n branches on an i n d e x i n e q u a l i t y t e s t . A quantity consisting of a l l 0's and a q u a n t i t y c o n s i s t i n g of a l l 1's a r e n o t e q u a l f o r t h i s t e s t . 0 6 i jK Branch t o K i f ( B i ) 2 (Bj) GE B i , Bj, K This two-parcel i n s t r u c t i o n u s e s t h e lower-order 18 b i t s a s operand K. Execution of t h i s i n s t r u c t i o n c a u s e s t h e program sequence t o t e r m i n a t e w i t h a jump t o a d d r e s s K i n CM o r t o c o n t i n u e with t h e c u r r e n t program sequence, Both q u a n t i t i e s a r e depending on a comparison of t h e c o n t e n t s of B i and Bj. t r e a t e d a s signed i n t e g e r s . The branch t o a d d r e s s K o c c u r s i f t h e c o n t e n t of B i i s g r e a t e r than o r e q u a l t o t h e c o n t e n t of B j . The c u r r e n t program sequence c o n t i n u e s i f the c o n t e n t of B i i s l e s s than B j . This i n s t r u c t i o n branches on an index t h r e s h o l d t e s t . c o n s i d e r e d g r e a t e r than a -0 q u a n t i t y . 07i jK Branch t o K i f ( B i ) < A +O q u a n t i t y i s LT B i , B j , K (Bj) This two-parcel i n s t r u c t i o n u s e s t h e lower-order 18 b i t s a s operand K. Execution of t h i s i n s t r u c t i o n c a u s e s t h e program sequence t o t e r m i n a t e w i t h a jump t o a d d r e s s K i n CM o r t o c o n t i n u e with t h e c u r r e n t program sequence, depending on a comparison of t h e c o n t e n t s of B i and Bj. Both q u a n t i t i e s a r e t r e a t e d a s signed i n t e g e r s . The branch t o a d d r e s s K o c c u r s i f the c o n t e n t of B i i s l e s s than t h e c o n t e n t of B j . The c u r r e n t program sequence c o n t i n u e s i f the c o n t e n t of B i i s g r e a t e r than o r e q u a l t o t h e c o n t e n t of Bj. This i n s t r u c t i o n branches on an index t h r e s h o l d t e s t . c o n s i d e r e d g r e a t e r t h a n a -0 q u a n t i t y . A +O q u a n t i t y i s CP Block Copy Instructions CP Block Copy lnstructions The block copy instructions (table 4 - 3 ) transfer 60-bit words between fields in CM and UEM. Table 4 - 3 . CP Block Copy Instructions Opcode Format Instruction 011 012 jK jK Block copy (Bj Block copy (Bj Mnemonic + K) words + K) words from U E M to CM from CM to UEM RE Bj+K WE Bj+K CP Block Copy Instructions Block Copy OlljK Block copy (Bj + K) words from UEM to CM 59 51 47 30 29 K 0 INST. FOR HALF EXIT This instruction copies a block of Bj plus K consecutive words from unified extended memory (UEM) to CM. The source UEM address is XO plus RAE where the bits used depend on the setting of the expanded addressing select flag in the CYBER 170 exchange package, If the flag is clear (UEM is in standard addressing mode), the UEM address is calculated using bits 0 through 22 of XO; bits 24 through 59 are ignored. If the flag i s set (UEM is in expanded addressing mode), the UEM address is calculated using bits 0 through 28 of XO; bits 30 through 59 are ignored. The destination CM address is either A0 plus RAC, or XO plus RAC, depending on the setting of the block copy flag in the CYBER 170 exchange package. When the block copy flag is clear, the CM address is A0 plus RAC. When the block copy flag is set, the CM address is calculated using bits 30 through 50 of XO. Bits 51 through 59 must be set to 0; results are undefined if these bits are not 0. The operation leaves Bj, XO, and A0 unchanged. Bj and K are both signed 18-bit one's complement numbers, making it possible to transfer a maximum of 131 071 60-bit words. If Bj plus K is 0, the instruction acts as a 60-bit pass instruction. If bit 21 or 22 of the result of XO plus RAE is a 1, 0's are transferred, and the next instruction is taken from parcel 2 of the same instruction word. If this is not the case, the next instruction is taken from parcel 0 of the next instruction word. If execution of the OlljK instruction is interrupted, it is restarted from the beginning. This instruction is illegal if it does not start in parcel 0 or the UEM enable flag in the CYBER 170 exchange package is clear. In standard addressing mode, 24 bits of XO are checked against 23 bits of FLE with bit 23 of FLE equal to 0. In expanded addressing mode, 30 bits of XO are checked against 29 bits of FLE with bit 29 equal to 0, If the XO bits are greater than or equal to FLE, an address-out-of-range condition is detected. If Bj plus K is negative, an address range error exit takes place. If the source field and the destination field overlap in physical memory, the final contents of the destination field are undefined. For further information, refer to Block Copy Instructions in chapter 5. CP Block Copy instructions 012jK Block copy ( B j 59 47 51 012 + K) i words from CM t o U W 30 29 K 0 INSP. FOR HALF EXIT This i n s t r u c t i o n copies a block of Bj plus K consecutive words from CM t o UEM. The source CM address i s e i t h e r A0 p l u s RAC o r XO p l u s RAC, depending on the s e t t i n g of t h e block copy f l a g i n the CYBER 170 exchange package. When t h e block copy f l a g i s c l e a r , t h e CM address i s A0 plus RAC. When the block copy f l a g i s s e t , t h e CM address is c a l c u l a t e d using b i t s 30 through 50 of XO. Bits 5 1 through 59 must be s e t t o 0; r e s u l t s a r e undefined i f these b i t s a r e not 0. The d e s t i n a t i o n UPI address i s XO plus RAE where t h e b i t s used depend on t h e s e t t i n g of t h e expanded addressing s e l e c t f l a g i n t h e CYBER 170 exchange package. I f t h e f l a g i s c l e a r (UPI i s i n standard addressing mode), the UEM address i s c a l c u l a t e d using b i t s 0 through 22 of XO; b i t s 24 through 59 a r e ignor'ed. I f t h e f l a g i s s e t (UPI i s i n expanded addressing mode), the UEM address i s c a l c u l a t e d using b i t s 0 through 28 of XO; b i t s 30 through 59 a r e ignored. The operation l e a v e s Bj, XO, and A0 unchanged. B j and K a r e both signed 18-bit one's complement numbers, making i t p o s s i b l e t o t r a n s f e r a maximum of 131 071 60-bit words. If B j plus K i s 0, t h e i n s t r u c t i o n a c t s a s a 60-bit pass instruction. If b i t 21 o r 22 of t h e r e s u l t of XO plus RAE i s a 1, 0 ' s a r e t r a n s f e r r e d and the next i n s t r u c t i o n i s t a k e n from p a r c e l 2 of the same i n s t r u c t i o n word. I f t h i s is not t h e c a s e , t h e next i n s t r u c t i o n i s taken from p a r c e l 0 of the next i n s t r u c t i o n word. I f execution of t h e 012jK i n s t r u c t i o n i s i n t e r r u p t e d , i t i s r e s t a r t e d from t h e beginning. This i n s t r u c t i o n i s i l l e g a l i f i t does not s t a r t i n p a r c e l 0 o r t h e UEM enable f l a g in t h e CYBER 170 exchange package i s c l e a r . I n standard addressing mode, 24 b i t s of XO a r e checked a g a i n s t 23 b i t s of FLE with b i t 23 of FLE equal t o 0. I n expanded addressing mode, 30 b i t s of XO a r e checked a g a i n s t 29 b i t s of FLE with b i t 29 equal t o 0. I f the XO b i t s a r e g r e a t e r than o r equal t o FLE, an address-out-of-range c o n d i t i o n i s d e t e c t e d . I f B j plus K i s negative, an address range e r r o r e x i t t a k e s place. I f t h e source f i e l d and the d e s t i n a t i o n f i e l d overlap i n p h y s i c a l memory, the f i n a l contents of t h e d e s t i n a t i o n f i e l d a r e undefined. For f u r t h e r information, r e f e r t o Block Copy I n s t r u c t i o n s i n chapter 5. CP Shift Instructions CP Shift lnstructions The s h i f t i n s t r u c t i o n s ( t a b l e 4-41 s h i f t t h e X i 60-bit word through t h e number of b i t p o s i t i o n s determined from a computed s h i f t count. Table 4-4. CP S h i f t I n s t r u c t i o n s Opcode Format Instruction Mnemonic 20 22 ijk i jk ij k ijk L e f t s h i f t ( x i ) by jk L e f t s h i f t (Xk) nominally (Bj) p l a c e s t o X i Right s h i f t ( X i ) by jk Right s h i f t (Xk) nominally ( B j ) p l a c e s t o X i LXi LXi AX1 AXi 21 23 jk Bj Xk jk Bj Xk Left Shift 20ijk L e f t s h i f t (Xi) by jk LXi jk This i n s t r u c t i o n r e a d s one operand from X i , s h i f t s t h e 60-bit word l e f t c i r c u l a r l y by jk b i t p o s i t i o n s , and w r i t e s t h e r e s u l t i n g 60-bit word back i n t o t h e same X i r e g i s t e r . The j and k d e s i g n a t o r s a r e t r e a t e d a s a s i n g l e 6-bit p o s i t i v e i n t e g e r operand i n t h i s i n s t r u c t i o n . A left-circular s h i f t i m p l i e s t h a t t h e b i t p a t t e r n i n t h e 60-bit word i s d i s p l a c e d towards t h e h i g h e s t - o r d e r b i t p o s i t i o n s . The b i t s s h i f t e d o f f t h e upper end of t h e 60-bit word a r e i n s e r t e d i n t h e lowest-order b i t p o s i t i o n s i n t h e same sequence. The r e s u l t i n g 60-bit word h a s t h e same q u a n t i t y of b i t s w i t h v a l u e s of 1 and 0 a s i n the o r i g i n a l operand. A sample computation i s l i s t e d i n o c t a l n o t a t i o n t o i l l u s t r a t e t h e o p e r a t i o n performed. I n i t i a l I X i ) = 2323 6600 0000 0000 0111 jk = I2 ( o c t a l ) F i n a l (Xi) = 7540 0000 0000 0022 2464 This i n s t r u c t i o n , t o g e t h e r w i t h i n s t r u c t i o n 21, may be used whenever a d a t a word i s t o be s h i f t e d by a predetermined amount. I f t h e amount of s h i f t i s d e r i v e d i n t h e e x e c u t i o n of t h e program, use i n s t r u c t i o n 22 o r 23. CP Shift Instructions Left shift ( X k ) nominally (Bj) places to Xi rXi Bj, Xk This instruction reads a 60-bit operand from Xk, shifts the data either left or right as specified by Bj, and writes the resulting 60-bit word into Xi. If the value in Bj is positive, the data is left-shifted circularly the number of bit positions designated by the value in Bj. If the value in Bj is negative, the data is right-shifted with sign extension the number of bit positions designated by the value in Bj. Bj bit 17 determines the sign of Bj. A left-circular shift implies that the bit pattern in the 60-bit word is displaced towards the highest-order bit positions. The bits shifted off the upper end are inserted in the lowest-order bit positions in the same sequence. The resulting 60-bit word has the same quantity of bits with values of 1 and 0 as in the original operand. A right shift with sign extension implies that the bit pattern in the 60-bit word is displaced towards the lowest-order positions. The bits shifted off the lower end are discarded. The highest-order bit positions are filled with copies of the original sign bit. Two sample computations are listed in octal notation to illustrate the operation performed. An example of a positive shift count resulting in a leftcircular shift is as follows: An example of the right shift with sign extension is as follows: If Bj bits 6 through 10 are different from Bj bit 17 aid Bj bit 17 is set, the shift count is greater than 63 (decimal) places right, and a result of +O is returned to Xi. Bj bits 11 through 16 are not tested by this instruction. This instruction is used when the amount of shift is derived in the computation. The instruction is also used for correcting the coefficient of a floating-point number when the exponent has been unpacked into a B register. CP Shift Instructions Right Shift 2lijk This sign into 6-bit Right s h i f t (Xi) by jk i n s t r u c t i o n r e a d s one operand from X i , s h i f t s the 60-bit word r i g h t with extension by jk b i t p o s i t i o n s , and w r i t e s t h e r e s u l t i n g 60-bit word back t h e same X i r e g i s t e r . The j and k d e s i g n a t o r s a r e t r e a t e d as a s i n g l e p o s i t i v e i n t e g e r operand i n t h i s i n s t r u c t i o n . A r i g h t s h i f t with s i g n extension implies t h a t t h e b i t p a t t e r n i n the 60-bit word i s displaced toward t h e lowest-order b i t p o s i t i o n s . The b i t s s h i f t e d o f f the lower end of t h e word a r e discarded. The highest-order b i t p o s i t i o n s a r e f i l l e d wtth copies of t h e o r i g i n a l s i g n b i t . Two sample computations a r e l i s t e d i n o c t a l n o t a t i o n t o i l l u s t r a t e the operation performed. An example of a p o s i t i v e operand i s a s follows: I n i t i a l (Xi) Final (Xi) 2004 7655 0002 3400 0004 0000 0000 2004 7655 0002 An example of a negative operand i s a s follows: I n i t i a l (Xi) = 6000 4420 2222 0000 5643 jk = 10 ( o c t a l ) F i n a l (Xi) = 7774 0 0 U 0404 4440 0013 This i n s t r u c t i o n , t o g e t h e r with i n s t r u c t i o n 20, may be used whenever a d a t a word i s t o be s h i f t e d by a predetermined amount. I f the amount of s h i f t i s derived i n t h e execution of t h e program, use i n s t r u c t i o n 22 o r 23. CP Shift Instructions Right s h i f t (Xk) nominally ( ~ j ) places t o Xi AX1 B j , Xk This i n s t r u c t i o n r e a d s a 60-bit operand from Xk, shifts t h e d a t a e i t h e r l e f t or r i g h t a s s p e c i f i e d by t h e content of B j , and w r i t e s t h e r e s u l t i n g 60-bit word I f t h e value i n Bj i s p o s i t i v e , t h e d a t a i s r i g h t - s h i f t e d with s i g n into Xi. e x t e n s i o n t h e number of b i t p o s i t i o n s designated by t h e v a l u e in B j . I f t h e value i n B j i s negative, t h e d a t a is l e f t - s h i f t e d c i r c u l a r l y t h e number of b i t p o s i t i o n s designated by t h e value i n Bj. Bj b i t 17 determines t h e s i g n of B j . A l e f t - c i r c u l a r s h i f t implies t h a t t h e b i t p a t t e r n i n t h e 60-bit word i s d i s p l a c e d towards t h e highest-order b i t p o s i t i o n s . The b i t s s h i f t e d o f f t h e upper end a r e i n s e r t e d i n t h e lowest-order b i t p o s i t i o n s i n t h e same sequence. The r e s u l t i n g 60-bit word has t h e same q u a n t i t y of b i t s with values of 1 and 0 a s i n t h e o r i g i n a l operand. A r i g h t s h i f t with s i g n extension i m p l i e s t h a t t h e b i t p a t t e r n i n t h e 60-bit words i s displaced towards t h e lowest-order b i t p o s i t i o n s . The b i t s s h i f t e d off t h e lower end of t h e word are discarded. The highest-order b i t p o s i t i o n s a r e f i l l e d with c o p i e s of t h e o r i g i n a l s i g n b i t . Two sample computations a r e l i s t e d i n o c t a l n o t a t i o n t o i l l u s t r a t e t h e o p e r a t i o n performed. The following example c o n t a i n s a p o s i t i v e s h i f t count r e s u l t i n g i n a r i g h t s h i f t with s i g n extension. The following example c o n t a i n s a negative s h i f t count r e s u l t i n g i n a l e f t circular shift. (Xk) = 2323 6600 0000 0000 0111 ( B j ) = 77 7765 (Xi) = 7540 0000 0000 0022 2464 B j b i t s 6 through 10 a r e d i f f e r e n t from B j b i t 1 7 , and B j b i t 17 i s c l e a r , t h e s h i f t count i s g r e a t e r than 63 (decimal) p l a c e s r i g h t , and a r e s u l t of +0 is returned t o X i . This i n s t r u c t i o n does not t e s t B j b i t s 11 through 16. This i n s t r u c t i o n i s used when t h e amount of s h i f t i s derived i n the computation. The i n s t r u c t i o n i s a l s o used f o r c o r r e c t i n g the c o e f f i c i e n t of a f l o a t i n g - p o i n t number when t h e exponent has been unpacked i n t o a B r e g i s t e r . CP Logical lnstructions CP Logical lnstructions The logical instructions (table 4-5) perform logical (Boolean) operations in the X registers. Table 4-5. CP Logical Instructions Opcode Format Instruction Mnemonic 12 16 ijk ijk BXi Xj+Xk 13 17 ijk ijk 11 15 ijk Cik Logical sum of (Xj) and (Xk) to Xi Logical sum of (Xj) with complement of (Xk) to Xi and (Xk) to Xi Logical difference of (~j) Logical difference of (Xj) with complement of (Xk) to Xi Logical product of (Xj) and (Xk) to Xi Logical product of (~j)with complement of (Xk) to Xi BXi -Xk+X j BXi Xj-Xk BXi -Xk-Xj B X I X j*Xk BXi -Xj*X j CP Logical Instructions Logical Sum 12ijk Logical sum of (Xj) and ( X k ) to Xi This instruction reads operands from two X registers, operates on them to form a result, and delivers this result to a third X register. The operands for this instruction are in Xj and Xk. The result delivered to Xi is the bit-by-bit logical sum of the two operands. Each of the 60 bits in Xj is compared with the corresponding bit in Xk to form a single bit in Xi. A sample computation is listed in octal notation to illustrate the operation performed and includes the four possible bit combinations that may occur. (Xj) = 0000 7777 0123 4567 1010 0123 7777 7777 4567 1110 (Xi) This instruction merges portions of a 60-bit word into a composite word during data processing. 16ijk Logical sum of (Xj) with complement of (Xk) to Xi 14 I 98 16 65 32 i j BXi -Xk + Xj 0 k This instruction reads operands from two X registers, operates on them to form a result, and delivers this result to a third X register. The operands for this instruction are in Xj and Xk. The result delivered to Xi is the bit-by-bit logical sum of the value in Xj and the complement of the value in Xk. Each of the 60 bits in Xj is compared with the corresponding bit in Xk to form a single bit in Xi. A sample computation is listed in octal notation to illustrate the operation performed and includes the four possible bit combinations that may occur. (Xi) = 7654 7777 0123 7777 7677 This instruction merges portions of a 60-bit word into a composite word during data processing. CP Logical Instructions Logical Difference 13ijk Logical difference of (Xj) and (Xk) to Xi This instruction reads operands from two X registers, operates on them to form a result, and delivers this result to a third X register. The operands for this instruction are in Xj and Xk. The result delivered to Xi is the bit-by-bit logical difference of the two operands. Each of the 60 bits in Xj is compared with the corresponding bit in Xk to form a single bit in Xi. A sample computation is listed in octal notation to illustrate the operation performed and includes the four possible bit combinations that may occur. (Xi) = 0000 3210 7654 7777 0110 This instruction compares bit patterns or complements bit patterns during data processing. 17ijk Logical difference of ( X j ) with complement of (Xk) to Xi BXi -Xk - Xj This instruction reads operands from two X registers, operates on them to form a result, and delivers this result to a thlrd X register. The operands for this instruction are in Xj and Xk. The result delivered to Xi is the bit-bybit logical difference of the value in Xj and the complement of the value in Xk. Each of the 60 bits in Xj is compared with the corresponding bit in Xk to form a single bit in Xi. A sample computation is listed in octal notation to illustrate the operation performed and includes the four possible combinations that may occur. This instruction compares bit patterns or complements bit patterns during data processing. CP Logical lnstruct~ons Logical Product llijk Logical product of (Xj) and (Xk) to Xi BXi Xj * Xk This instruction reads operands from two X registers, operates on them to form a result, and delivers this result to a third X register. The operands for this instruction are in Xj and Xk. The result delivered to Xi is the bit-bybit logical product of the two operands. Each of the 60 bits in Xj is compared with the corresponding bit in Xk to form a single bit in Xi. A sample computation is listed in octal notation to illustrate the operation performed and includes the four possible bit combinations that may occur. This instruction extracts portions of a 60-bit word during data processing. lSijk Logical product of (Xj) with complement of (Xk) to Xi BXI -Xk * Xj This instruction reads operands from two X registers, operates on them to form a result, and delivers this result to a third X register. The operands for this instruction are in Xj and Xk. The result delivered to Xi is the bit-bybit logical product of the value in Xj and the complement of the value in Xk. Each of the 60 bits in Xj is compared with the corresponding bit in Xk to form a single bit in Xi. A sample computation is listed in octal notation to illustrate the operation performed and includes the four possible bit . combinations that may occur. (Xi) = 7654 3000 0120 0067 OOZO This instruction extracts-portions of a 60-bit word during data processing. CP Floating-Point Arithmetic lnstructions CP Floating-point Arithmetic Instructions The f l o a t i n g - p o i n t i n s t r u c t i o n s ( t a b l e 4-6) f l o a t i n g - p o i n t numbers. Table 4-6. Opcode perform a r i t h m e t i c o p e r a t i o n s on CP Floating-point I n s t r u c t i o n s Format 34 31 ijk ijk 33 ijk 35 ijk 40 41 ijk ijk 44 45 ijk ijk Instruction Floating sum of (Xj) and (Xk) t o X i Floating double-precision sum of (Xj ) and (Xk) t o X i Round f l o a t i n g sum of (Xj) and (Xk) t o X i F l o a t i n g d i f f e r e n c e of ( ~ j and ) (Xk) to X i Floating double-precision d i f f e r e n c e of (Xj) and (Xk) t o X i Round f l o a t i n g d i f f e r e n c e of (Xj) and ( X k ) t o X i F l o a t i n g product of (Xj) and (Xk) t o X i Round f l o a t i n g product of (Xj) and (Xk) t o Xi. Floating double-precision product of (Xj) and (Xk) t o X i Floating d i v i d e (Xj) by (Xk) t o X i Round f l o a t i n g d i v i d e (Xj) by ( X k ) t o X i Mnemonic D X i Xj+Xk R X i Xj+Xk FXi X j-Xk D X i Xj-Xk RXI Xj-Xk FXI Xj*Xk D X i Xj*Xk FXI X j / X k Rxi X j / % CP Floating-Point Arithmetic Instructions Floating Sum 30i jk Floating sum of (Xj) and ( X k ) t o X i This i n s t r u c t i o n r e a d s operands from two X r e g i s t e r s , o p e r a t e s on them t o form a floating-point sum, and d e l i v e r s t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t l o n a r e i n Xj and Xk. These operands a r e i n f l o a t i n g - p o i n t format and a r e not n e c e s s a r i l y normalized. The sum of t h e q u a n t i t i e s i n Xj and Xk i s delivered t o X i i n floating-point format and i s not n e c e s s a r i l y normalized. The two operands a r e uppacked from floating-point format, and the exponents are compared. The c o e f f i c i e n t with t h e smaller exponent i s r i g h t - s h i f t e d by t h e d i f f e r e n c e of t h e two exponents such t h a t borh c o e f f i c i e n t s a r e the same s i g n i f i c a n c e . The two c o e f f i c i e n t s a r e then added t o form a 96-bit r e s u l t . The upper h a l f of t h e r e s u l t i s then s e l e c t e d a s a c o e f f i c i e n t and packed along If coefficient with the l a r g e r exponent t o form t h e r e s u l t s e n t t o X i . overflow occurs, t h e sum i s r i g h t - s h i f t e d one place, and t h e exponent i s increased by one. I f t h e two operands have u n l i k e s i g n s , t h e r e s u l t c o e f f i c i e n t may have l e a d i n g zeros. No normalize o p e r a t i o n i s b u i l t i n t o t h i s i n s t r u c t i o n t o c o r r e c t t h i s s i t u a t i o n . A s e p a r a t e normalize i n s t r u c t i o n must be programmed i f t h e r e s u l t is t o be kept i n a normalized form. When t h e difference between the exponents i s g r e a t e r than 128 (decimal), t h e s h i f t e d s i g n b i t i s extended t o t h e e n t i r e s h i f t e d operand. I n f i n i t e x o r 4000xxx...x) o r i n d e f i n i t e (1777xxx x o r 6000xxx x) (3777xxx operands cause corresponding e x i t c o n d i t i o n s t o s e t i n t h e CP f o r e x i t mode action. ... ... ... For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n chapter 5. CP Floating-PointArithmetic Instructions 32ijk Floating double-precision sum of (Xj) and (Xk) to Xi DXi X j + Xk This instruction reads operands from two X registers, operates on them to form a double-precision, floating-point sum, and delivers the lower half of this result to a third X register. The operands for this instruction are in Xj and Xk. These operands are in floating-point format and are not necessarily normalized. The sum of the quantities in Xj and Xk is delivered to Xi in floating-point format and is not necessarily normalized, The two operands are unpacked from floating-point format, and the exponents are compared. The coefficient with the smaller exponent is right-shifted by the difference of the.two exponents such that both coefficients are the same significance. The two coefficients are then added to form a 96-bit result. The lower half of the result is then selected and packed along with the larger exponent minus 48 (decimal) to form the result sent to Xi. If coefficient overflow occurs, the result is right-shifted by one place, and the exponent is increased by 1. Infinite (37771urx...x or 4000xm...x) or indefinite (1777xxx...x or 6000xxx...x) operands cause corresponding exit conditions to set in the CP for exit mode action. For further information, refer to Floating-Poht Arithmetic under CP Programming in chapter 5. 34ijk Round floating sum of (Xj) and (Xk) to Xi This instruction reads operands from two X registers, operates on them to form a rounded floating-point sum, and delivers this result to a third X register. The operands for this instruction are in Xj and Xk. These operands are in floating-point format and are not necessarily normalized. The result is delivered to Xi in floating-point format and is not necessarily normalized. The round floating-point sum is a single-precision floating-point sum with a round bit (or bits) inserted before the add operation takes place. A round bit is always inserted in the coefficient with the larger exponent. If the two exponents are equal, the round bit is inserted in the coefficient for Xk. The round bit is equal to the complement of the sign bit and is inserted immediately to the right of the lowest-order bit in the coefficient. This has the effect of increasing the magnitude of the coefficient by one-half of the l e a s t significant bit. A second round bit is inserted in a corresponding manner to the other coefficient if both operands are normalized or have unlike signs. The second round bit is inserted before the coefficient is shifted by the difference of the exponents. Infinite (3777xxx...x or 4000xxx x) or indefinite (1777xxx. ..x or 6000xxx x) operands cause corresponding exit conditions to set in the CP for exit mode action. ... ... For further information, refer to Floating-Point Arithmetic under CP Programming in chapter 5. CP Floating-Point Arithmetic Instructions Floating Difference 3lijk F l o a t i n g d i f f e r e n c e of (Xj) and (Xk) t o X i This i n s t r u c t i o n r e a d s operands from two X r e g i s t e r s , o p e r a t e s on them t o form a f l o a t i n g - p o i n t d i f f e r e n c e , and d e l i v e r s t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t i o n a r e i n X j and Xk. These operands a r e i n floating-point format and a r e not n e c e s s a r i l y normalized. The r e s u l t of s u b t r a c t i n g t h e q u a n t i t y i n Xk from t h e q u a n t i t y i n X j i s delivered t o X i i n floating-point format and i s not n e c e s s a r i l y normalized. The two operands a r e unpacked from f l o a t i n g - p o i n t format, and t h e exponents are compared. The c o e f f i c i e n t with t h e smaller exponent i s r i g h t - s h i f t e d by t h e d i f f e r e n c e of t h e two exponents such t h a t both c o e f f i c i e n t s a r e t h e same s i g n i f i c a n c e . The Xk c o e f f i c i e n t i s then s u b t r a c t e d from t h e X j c o e f f i c i e n t t o form a 96-bit r e s u l t . The upper h a l f of t h e r e s u l t i s t h e n s e l e c t e d and packed along with t h e l a r g e r exponent t o form t h e r e s u l t s e n t t o X i . If c o e f f i c i e n t overflow occurs, t h e r e s u l t i s r i g h t - s h i f ted one p l a c e , and t h e exponent i s increased by one. I f t h e two operands have l i k e s i g n s , t h e r e s u l t c o e f f i c i e n t may have l e a d i n g zeros. No normalize o p e r a t i o n i s b u i l t i n t o t h i s i n s t r u c t i o n t o c o r r e c t t h i s s i t u a t i o n . A s e p a r a t e normalize i n s t r u c t i o n must be programmed i f t h e r e s u l t i s t o be kept i n a normalized form. I n f i n i t e (3777xxx...x o r 4000xxx...x) or i n d e f i n i t e (1777xxx...x o r 6000xxx...x) operands cause corresponding e x i t conditions t o s e t i n t h e CP f o r e x i t mode a c t i o n . For f u r t h e r information, r e f e r t o Floating-point i n chapter 5. Arithmetic under CP Programming CP Floating-Point Arithmetic Instructions 33ijk Floating double-precision difference of (Xj) and (Xk) to Xi 14 I 98 33 65 3 2 i j DXi Xj - Xk 0 k This instruction reads operands from two X registers, operates on them to form a double-precision, floating-point difference, and delivers the lower half of this result to a third X register. The operands for this instruction are in Xj and X k . These operands are in floating-point format and are not necessarily normalized. The result of subtracting the quantity in Xk from the quantity in Xj is delivered to Xi in floating-point format and is not necessarily normalized. The two operands are unpacked from floating-point format, and the exponents are compared. The coefficient with the smaller exponent is right-shifted by the difference of the two exponents such that both coefficients are the same significance. The Xk coefficient is then subtracted from the Xj coefficient to form a 96-bit result. The lower half of the result is then selected and packed along with the larger exponent minus 48 (decimal) to form the result sent to Xi. If coefficient overflow occurs, the result is right-shifted one place, and the exponent is increased by one. ... ... Infinite (3777xxx x or 4000xxx...x) or indefinite (1777x9~ x or 6OOOxxx... x) operands cause corresponding exit conditions to set in the CP for exit mode action. For further information, refer to Floating-point Arithmetic under CP Programming in chapter 5. CP Floating-point Arithmetic Instructions Round f l o a t i n g d i f f e r e n c e of (xj) and (Xi) t o X i R X i Xj - Xk This i n s t r u c t i o n r e a d s operands from two X r e g i s t e r s , o p e r a t e s on them t o form a rounded floating-point d i f f e r e n c e , and d e l i v e r s t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t i o n a r e i n X j and Xk. These operands a r e i n floating-point format and a r e not n e c e s s a r i l y normalized. The r e s u l t of s u b t r a c t i n g t h e q u a n t i t y i n Xk from t h e q u a n t i t y i n Xj i s d e l i v e r e d t o X i i n floating-point format and is not n e c e s s a r i l y normalized. The round floating-point d i f f e r e n c e i s a s i n g l e - p r e c i s i o n , f l o a t i n g - p o i n t difference with a round b i t ( o r b i t s ) i n s e r t e d before t h e s u b t r a c t o p e r a t i o n t a k e s place. A round b i t i s always i n s e r t e d i n t h e c o e f f i c i e n t with t h e l a r g e r exponent. I f the two exponents are e q u a l , t h e round b i t i s added t o t h e c o e f f i c i e n t f o r Xk. The round b i t i s equal t o the complement of the s i g n b i t and i s i n s e r t e d immediately t o t h e r i g h t of the lowest-order b i t i n t h e c o e f f i c i e n t . This has t h e e f f e c t of i n c r e a s i n g the magnitude of t h e c o e f f i c i e n t by one-half of t h e l e a s t - s i g n i f i c a n t b i t . A second round b i t i s i n s e r t e d i n a corresponding manner t o t h e o t h e r c o e f f i c i e n t i f both operands a r e normalized o r have l i k e s i g n s . The second round b i t i s i n s e r t e d before t h e c o e f f i c i e n t i s s h i f t e d by t h e d i f f e r e n c e o f . t h e exponents. I n f i n l t e x) o r i n d e f i n i t e (1777xxx...x o r 6000xxx x) (3777xxx...x o r 4000xxx operands cause corresponding e x i t conditions t o s e t i n t h e CP f o r e x i t mode action. ... ... For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n chapter 5. CP Floating-Point Arithmetic Instructions Floating Product 40i j k Floating product of (Xj) and (Xk) t o X i FXi X j * Xk This i n s t r u c t i o n reads operands from two X r e g i s t e r s , o p e r a t e s on them t o form product, and d e l i v e r s t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t i o n a r e i n X j and Xk. These operands a r e i n floating-point format and a r e not n e c e s s a r i l y normalized. The r e s u l t i s delivered t o X i i n floating-point format. I f both operands a r e normalized, t h e r e s u l t i s a l s o normalized. I f both operands a r e not normalized, the r e s u l t i s not normalized, a floating-point The two operands a r e unpacked from floating-point format. The exponents a r e added with a c o r r e c t i o n f a c t o r t o determine the exponent f o r t h e r e s u l t . The c o e f f i c i e n t s a r e m u l t i p l i e d a s signed i n t e g e r s t o form a 96-bit i n t e g e r product. The upper h a l f of t h i s product is e x t r a c t e d t o form t h e c o e f f i c i e n t f o r t h e r e s u l t . I f t h e o r i g i n a l operands a r e normalized and t h e product has only 95 s i g n i f i c a n t b i t s , a 1-bit l e f t s h i f t i s done t o normalize t h e r e s u l t c o e f f i c i e n t . The r e s u l t i n g exponent is reduced by one count i n t h i s case. I f both operands a r e not normalized, the r e s u l t i n g double-precision product h a s l e s s than 96 s i g n i f i c a n t b i t s . No t e s t i s made f o r t h e p o s i t i o n of t h e mosts i g n i f i c a n t b i t . The upper 48 b i t s are read from t h e double-precision product r e g i s t e r . Leading zeros occur i n t h i s r e s u l t c o e f f i c i e n t . This i n s t r u c t i o n i s used i n floating-point c a l c u l a t i o n s where rounding of operands i s not d e s i r e d , such a s i n multiple-precision a r i t h m e t i c and i n x or ~OOOXXX...~) c a l c u l a t i o n s involving e r r o r a n a l y s i s . I n f i n i t e (3777xxx o r i n d e f i n i t e (1777xxx x o r 6000xxx...x) operands cause corresponding e x i t conditions t o s e t i n t h e CP f o r e x i t mode a c t i o n . ... ... For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n chapter 5. CP Floating-Point Arithmetic Instructions Round f l o a t i n g product of (Xj) and (Xk) t o X i This i n s t r u c t i o n r e a d s operands from two X r e g i s t e r s , o p e r a t e s on them t o form a rounded f l o a t i n g - p o i n t product, and d e l i v e r s t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t i o n a r e i n Xj and Xk. These operands a r e i n f l o a t i n g - p o i n t format and a r e not n e c e s s a r i l y normalized. The r e s u l t i s d e l i v e r e d t o Xi in f l o a t i n g - p o i n t format. I f both operands a r e normalized, t h e r e s u l t i s a l s o normalized. I f both operands a r e not normalized, t h e r e s u l t i s n o t normalized. The two operands a r e unpacked from f l o a t i n g - p o i n t format. The exponents a r e added w i t h ' a c o r r e c t i o n f a c t o r t o determine t h e exponent f o r t h e r e s u l t . The c o e f f i c i e n t s a r e m u l t i p l i e d as signed i n t e g e r s t o form a 96-bit i n t e g e r product. A rounding b i t is added t o b i t p o s i t i o n 46 of t h i s product. The upper half of t h i s product i s e x t r a c t e d t o form t h e c o e f f i c i e n t f o r t h e r e s u l t . If t h e o r i g i n a l operands a r e normalized and t h e product has o n l y 95 s i g n i f i c a n t b i t s , a l - b i t l e f t s h i f t is done t o normalize t h e r e s u l t c o e f f i c i e n t . The r e s u l t i n g exponent i s reduced by one count i n t h i s case. If both operands a r e not normalized, t h e r e s u l t i n g double-precision product has l e s s t h a n 96 s i g n i f i c a n t b i t s . No t e s t i s made f o r t h e p o s i t i o n of t h e mosts i g n i f i c a n t b i t . The upper 48 b i t s a r e r e a d from t h e double-precision product r e g i s t e r . Leading z e r o s occur i n t h i s r e s u l t c o e f f i c i e n t . This i n s t r u c t i o n i s used i n s i n g l e - p r e c i s i o n , f l o a t i n g - p o i n t c a l c u l a t i o n s . For m u l t i p l e - p r e c i s i o n c a l c u l a t i o n s , t h e 40 and 42 i n s t r u c t i o n s must be used. I n f i n i t e (37779xx.. .x o r 4000rmx.. .x) o r i n d e f i n i t e (1777xxx.. . x or 6000xxx x ) operands cause corresponding e x i t c o n d i t i o n s t o s e t i n t h e CP f o r e x i t mode a c t i o n . ... For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n c h a p t e r 5. CP Floating-Point Arithmetic Instructions 42ijk Floating double-precision product (Xk) t o X i of ( ~ j and ) This i n s t r u c t i o n reads operands from two X r e g i s t e r s , o p e r a t e s on them t o form a double-precision, floating-point product, and d e l i v e r s t h e lower h a l f of t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t i o n a r e i n X j and Xk. These operands a r e i n f l o a t i n g - p o i n t format and a r e not n e c e s s a r i l y normalized. The lower h a l f of the double-precision product i s d e l i v e r e d t o X i i n floating-point format and i s not n e c e s s a r i l y normalized. The operands a r e not rounded i n t h i s operation. The two operands a r e unpacked from floating-point format. The exponents a r e added t o determine t h e exponent f o r t h e r e s u l t . The r e s u l t exponent i s e x a c t l y 48 l e s s than t h e exponent f o r a 40 i n s t r u c t i o n . The c o e f f i c i e n t s a r e m u l t i p l i e d a s signed i n t e g e r s t o form a 96-bit i n t e g e r product. The lower h a l f of t h i s product i s e x t r a c t e d t o form the c o e f f i c i e n t f o r t h e r e s u l t . I f t h e o r i g i n a l operands a r e normalized and t h e double-precision product has only 95 s i g n i f i c a n t b i t s , a l - b i t l e f t s h i f t i s done t o normalize t h e r e s u l t c o e f f i c i e n t . The r e s u l t i n g exponent i s reduced by one count i n t h i s case. I f both operands a r e not normalized, t h e r e s u l t i n g double-precision product has l e s s than 96 s i g r d f i c a n t b i t s . No t e s t is made f o r t h e p o s i t i o n of t h e mosts i g n i f i c a n t b i t . The lower 48 b i t s a r e always read from t h e 96-bit product register. This i n s t r u c t i o n i s used i n multiple-precision, f l o a t i n g - p o i n t c a l c u l a t i o n s . This i n s t r u c t i o n a l s o provides f o r i n t e g e r m u l t i p l i c a t i o n c a p a b i l i t i e s where both operands have an exponent value of plus o r minus zero, and n e i t h e r c o e f f i c i e n t has been normalized. The i n t e g e r r e s u l t s e n t t o X i i s 48 b i t s w i t h 60-bit s i g n extension. I f t h e r e s u l t exceeds 48 b i t s , t h e hardware does not d e t e c t an overflow. An overflow check can be made by executing a 40 i n s t r u c t i o n using t h e same two operands. I f t h e r e s u l t i s nonzero, overflow i s then i n d i c a t e d . An i n t e g e r multiply o p e r a t i o n i s not intended f o r use with x and 4000xxx x) o r indefinite normalized operands. I n f i n i t e (3777xxx (1777xxx...x o r 6OOOxxx... x ) operands cause corresponding e x i t c o n d i t i o n s t o s e t i n t h e CP f o r e x i t mode a c t i o n . ... ... For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n chapter 5. CP Floating-Point Arithmetic Instructions Floating Divide 44ijk Floating divide (Xj) by ( X k ) t o X i This i n s t r u c t i o n r e a d s operands from two X r e g i s t e r s , o p e r a t e s on them t o form a floating-point q u o t i e n t , and d e l i v e r s t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t i o n a r e i n X j and Xk. These operands a r e i n f l o a t i n g - p o i n t format. The r e s u l t of d i v i d i n g t h e content of X j by the c o n t e n t of Xk i s delivered t o X i . If both operands a r e normalized, the quotient i s a l s o normalized. The remainder from the d i v i s i o n process i s discarded. The two operands a r e unpacked from floating-point format. The exponents a r e subtracted with a c o r r e c t i o n f a c t o r t o determine t h e exponent f o r t h e r e s u l t . The c o e f f i c i e n t from X j i s positioned i n a dividend r e g i s t e r . The c o e f f i c i e n t from Xk i s t r i a l - s u b t r a c t e d repeatedly from the dividend. The quotient b i t s a r e assembled i n a q u o t i e n t r e g i s t e r . When 48 b i t s of t h e q u o t i e n t a r e assembled, they a r e packed with the r e s u l t exponent i n t o f l o a t i n g - p o i n t format and delivered t o X i . If the exponent s u b t r a c t i o n causes an underflow o r overflow, a n underflow o r overflow r e s u l t i s r e t u r n e d even with t h e occurrence of a d i v i d e f a u l t . I f the dividend i s not normalized, t h e q u o t i e n t cannot be normalized. However, the q u o t i e n t i s c o r r e c t even though t h e r e may be l e a d i n g z e r o s i n the c o e f f i c i e n t . I f t h e d i v i s o r i s not normalized, t h e q u o t i e n t may be i n c o r r e c t . I f the c o e f f i c i e n t f o r t h e content of X j i s l a r g e r than t h e c o e f f i c i e n t f o r the content of Xk by a f a c t o r of two o r more, a d i v i d e f a u l t causes an i n d e f i n i t e r e s u l t t o be returned t o X i . This i n s t r u c t i o n is used i n floating-point c a l c u l a t i o n s where rounding of operands i s not d e s i r e d . I n multiple-precision d i v i s i o n , t h i s i n s t r u c t i o n m u s t be followed by a m u l t i p l i c a t i o n of t h e q u o t i e n t by t h e d i v i s o r and s u b t r a c t e d from the dividend t o r e c o n s t r u c t the remainder. If i n f i n i t e (3777mrx...x o r 4000xgx...x) o r i n d e f i n i t e (1777xxx...x o r 6000xxx...x) operands a r e used, corresponding e x i t c o n d i t i o n s a r e s e t i n t h e CP f o r e x i t mode a c t i o n . For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n chapter 5. CP Floating-point Arithmetic Instructions 45ijk Bound f l o a t i n g d i v i d e (Xj) by ( ~ k )t o X i This i n s t r u c t i o n reads operands from two X r e g i s t e r s , o p e r a t e s on them t o form a rounded f l o a t i n g - p o i n t q u o t i e n t , and d e l i v e r s t h i s r e s u l t t o a t h i r d X r e g i s t e r . The operands f o r t h i s i n s t r u c t i o n a r e i n Xj and Xk. These operands a r e i n floating-point format. The r e s u l t of d i v i d i n g t h e content of Xj by t h e content of Xk i s delivered t o X i . I f both operands a t e normalized, t h e q u o t l e n t i s a l s o normalized. The remainder from t h e d i v i s i o n process i s discarded . The two operands a r e unpacked from floating-point format i n t h i s operation. The exponents a r e subtracted with a c o r r e c t i o n f a c t o r t o determine the exponent f o r t h e r e s u l t . The c o e f f i c i e n t from Xj i s positioned i n a dividend r e g i s t e r . The X j q u a n t i t y is modified by i n s e r t i n g a 2525 25 round p a t t e r n below the lowest-order b i t of t h e dividend c o e f f i c i e n t . The c o e f f i c i e n t from Xk i s t r i a l - s u b t r a c t e d repeatedly from the dividend. The q u o t i e n t b i t s a r e assembled i n a q u o t i e n t r e g i s t e r . When 48 b i t s of t h e q u o t i e n t a r e assembled, they a r e packed with t h e r e s u l t exponent i n t o floating-point format and d e l i v e r e d t o X i . ... If the dividend i s not normalized, the q u o t i e n t cannot be normalized. However, t h e q u o t i e n t i s c o r r e c t even though t h e r e may be l e a d i n g z e r o s i n the c o e f f i c i e n t . I f t h e d i v i s o r i s not normalized, the q u o t i e n t may be i n c o r r e c t . I f t h e c o e f f i c i e n t f o r the content of Xj i s l a r g e r than t h e c o e f f i c i e n t f o r t h e content of Xk by a f a c t o r of two or more, a divide f a u l t occurs. A d i v i d e f a u l t causes an i n d e f i n i t e r e s u l t t o be returned t o X i . This i n s t r u c t i o n i s used i n single-precision, f l o a t i n g - p o i n t c a l c u l a t i o n s where rounding of operands i s d e s i r e d t o reduce t r u n c a t i o n e r r o r s . ... ... x ) o r i n d e f i n i t e (1777xxx x or I f i n f i n i t e (3777mrx...x o r 4000xxx 6000xxx...x) operands are used, corresponding e x i t c o n d i t i o n s a r e s e t i n the CP f o r e x i t mode a c t i o n . For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n chapter 5. CP Jump Instructions CP Jump Instructions The jump i n s t r u c t i o n s ( t a b l e 4-7) a l l o w d e p a r t u r e from s e q u e n t i a l i n s t r u c t i o n execution. CP Jump I n s t r u c t i o n s Table 4-7. Opcode Format Instruction 010 02 XK ixK Return jump t o K Jump t o ( B i ) + K Mnemonic Jump RJ K Return jump t o K This This two-parcel i n s t r u c t i o n uses t h e lower-order 1 8 b i t s a s operand K. i n s t r u c t i o n w r i t e s a s p e c i a l word i n t o CM a t r e l a t i v e a d d r e s s K. The c u r r e n t program sequence then t e r m i n a t e s by a jump t o a d d r e s s K p l u s 1. The word s t o r e d i n memory c o n t a i n s a jump i n s t r u c t i o n which causes an u n c o n d i t i o n a l jump t o t h e a d d r e s s of t h i s r e t u r n jump i n s t r u c t i o n p l u s 1. This i n s t r u c t i o n c a l l s a s u b r o u t i n e and i n s e r t s execution of t h e s u b r o u t i n e between execution of t h i s i n s t r u c t i o n word and t h e following i n s t r u c t i o n word. I n s t r u c t i o n s appearing a f t e r t h e r e t u r n jump i n s t r u c t i o n i n t h e i n s t r u c t i o n word a r e not executed. The c a l l e d s u b r o u t i n e e x i t must be a t a d d r e s s K. The c a l l e d s u b r o u t i n e e n t r a n c e a d d r e s s must be K p l u s 1. This i n s t r u c t i o n s t o r e s a 60-bit word a t a d d r e s s K i n memory. The upper h a l f of t h i s word c o n t a i n s an u n c o n d i t i o n a l jump (0400) i n s t r u c t i o n with an a d d r e s s t h a t i s e q u a l t o t h e c u r r e n t program a d d r e s s p l u s 1. The lower h a l f of t h e s t o r e d word i s a l l 0 ' s . The o c t a l d i g i t s i n t h e s t o r e d word t h e n appear a s i l l u s t r a t e d with t h e x f i e l d i n d i c a t i n g t h e l o c a t i o n of t h e c u r r e n t program address p l u s 1. K K + 1 0 4 0 0 ~ xxxxx 00000 00000 Subroutine e x i t yyyyy yyyyy yyyyy Subroutine e n t r a n c e yyyyy CP Jump Instructions 02 ixK Jump t o (Bi) 4- K J P B i + K This two-parcel i n s t r u c t i o n uses the lower-order 18 b i t s a s operand K. The i n s t r u c t i o n causes t h e c u r r e n t program sequence t o t e r m i n a t e with a jump t o address B i plus K i n CM. This i n s t r u c t i o n allows computed branch point d e s t i n a t i o n s . This i s the only i n s t r u c t i o n i n which a computed parameter can s p e c i f y a program branch d e s t i n a t i o n address. A11 o t h e r jump i n s t r u c t i o n s have preassigned d e s t i n a t i o n addresses. The q u a n t i t i e s i n B i and operand K a r e added i n an 18-bit o n e ' s complement mode. The r e s u l t i s t r e a t e d as an 18-bit p o s i t i v e i n t e g e r t h a t s p e c i f i e s t h e beginning address i n CM f o r t h e new program sequence. The remaining i n s t r u c t i o n s , i f any, i n t h e i n s t r u c t i o n word do not execute. CP Exchange Jump lnstructions CP Exchange Jump Instructions The exchange jump instructions (table 4-8) exchange the current process registers (formatted as an exchange package) with another set stored in CM, and do the following: When executed with CP in Virtual State monitor mode, the processor switches from monitor to job mode. When executed in Virtual State job mode, the processor switches from mob to monitor mode and the system call bit sets in the monitor condition register (MCR 10). In either case, the P register stored in the outgoing exchange package points to the next instruction that would have executed if the exchange had not occurred. This instruction can cause the following exception conditions. Environment specification error. System call. Refer to chapter 5 for programming information. Table 4 - 8 . CP Exchange Jump Instructions Opcode Format Instruction Mnemonic 013 jK Central exchange jump to (Bj) +K (CYBER 170 monitor flag set) XJ Bj+K Monitor exchange jump to MA (CYBER 170 monitor flag clear) XJ 013 xx CP Exchange Jump Instructions Exchange Jump 013jK Central exchange jump t o (Bj) +K when CYBER 170 MF s e t X J Bj 013xx Monitor exchange jump t o MA when CYBER 170 MF c l e a r XJ +K This i n s t r u c t i o n must s t a r t a t p a r c e l 0. Also, a CYBER 170 exchange package must be ready a t address B j p l u s K o r a t address MA. This i n s t r u c t i o n s t o r e s P p l u s 1 i n t o t h e outgoing CYBER 170 exchange package i n hardware and then exchanges t h i s CYBER 170 exchange package with t h e CYBER 170 exchange package s t o r e d i n memory. I f t h e CYBER 170 MF i s s e t a t the beginning of t h e i n s t r u c t i o n , t h e incoming CYBER 170 exchange package s t a r t s a t a b s o l u t e address B j plus K. I f t h e CYBER 170 MF i s c l e a r a t t h e beginning, then the j and K f i e l d s of the i n s t r u c t i o n a r e ignored, and the incoming CYBER 170 exchange package s t a r t s a t a b s o l u t e address MA, which i s obtained from t h e outgoing CYBW 170 exchange package. I n e i t h e r c a s e , t h e CYBER 170 MF i s toggled, and t h e outgoing CYBER 170 exchange package i s s t o r e d beginning a t t h e same CM address from where the incoming CYBER 170 exchange package i s obtained. Also, t h e jump i s always t o r e l a t i v e address P, p a r c e l 0 , from t h e new CYBER 170 exchange package. Refer t o CYBER 170 Exchange Jump i n c h a p t e r 5 . CP CornparelMove lnstructions CP CompareIMove lnstructions The compare/move instructions (table 4-9) move characters from one CM location to another and compare fields of characters either directly or through a collate table. The transmit instructions move words from one CM register to another . Table 4-9. Opcode 10 14 464 465 466 467 CP Compare/Move Instructions Format Instruction Mnemonic i jx ixk Transmit (Xj) to Xi Transmit complement of (Xk) to Xi Move indirect Move direct Compare collated Compare uncollated BXi X j BXi -Xk IM DM CC CU jK Transmit lOijx Transmit (Xj) to Xi BXi Xj This instruction transfers a 60-bit word from Xj into Xi. This instruction moves data from one X register to another X register. No logical function i s performed on the data. 14ixk Transmit complement of (Xk) to Xi BXi -Xk This instruction reads a 60-bit word from Xk, complements the word, and writes the result into Xi. This instruction changes the sign of a fixed-point or floating-point quantity. The instruction also inverts an entire 60-bit field during data processing. CP ComparelMove Instructions Corn pare/Move The compare/move i n s t r u c t i o n s ( a l s o r e f e r r e d t o a s CMU i n s t r u c t i o n s ) a r e provided f o r c o m p a t i b i l i t y with previous systems. For b e t t e r performance, recompile jobs t o avoid use of instructions. ( X U i n s t r u c t i o n s must appear i n p a r c e l 0 o r they a r e t r e a t e d as i l l e g a l instructions. Data f i e l d s c o n s i s t i n g of 6-bit c h a r a c t e r s may start o r end with any c h a r a c t e r p o s i t i o n ( o f f s e t ) of the t e n + b i t p o s i t i o n s i n each word. The c h a r a c t e r p o s i t i o n s a r e designated a s follows : For move i n s t r u c t i o n s , a K1 designator s p e c i f i e s which CM word contains the f i r s t c h a r a c t e r of the source d a t a f i e l d , and a C 1 d e s i g n a t o r s p e c i f i e s t h e c h a r a c t e r p o s i t i o n ( o f f s e t ) of t h e f i r s t c h a r a c t e r . The K2 d e s i g n a t o r s p e c i f i e s t h e CM l o c a t i o n i n which t h e f i r s t c h a r a c t e r of t h e r e s u l t d a t a f i e l d i s placed, and t h e C2 designator s p e c i f i e s t h e f i r s t c h a r a c t e r p o s i t i o n . For compare i n s t r u c t i o n s , both d a t a f i e l d addresses s p e c i f y source f i e l d s . Example : If t h e i n s t r u c t i o n i s Kl=1000 and C1'3, t h e f i r s t c h a r a c t e r of t h e source f i e l d i s i n p o s i t i o n 3 of l o c a t i o n 1000. Therefore, t h e f i r s t c h a r a c t e r of t h e source f i e l d i s 71. An address i s out of range i f C 1 o r C2 i s g r e a t e r than 9 , K l p l u s N 1 i s g r e a t e r than the program f i e l d l e n g t h f o r CM (FLc), o r K2 p l u s N2 i s g r e a t e r than FLC. N 1 equals t h e number of CM r e f e r e n c e s made t o the source d a t a f i e l d s t a r t i n g a t K1, and N2 equals the number of CM r e f e r e n c e s made t o t h e r e s u l t d a t a f i e l d s t a r t i n g a t K2. When an address-out-of-range c o n d i t i o n occurs, t h e CMU i n s t r u c t i o n i s not executed. U i s t h e lower 4 b i t s , and LU i s t h e upper 9 b i t s of t h e f i e l d l e n g t h designator i n numbers of c h a r a c t e r s . The maximum l e n g t h of t h e d a t a f i e l d s f o r t h e move d i r e c t and t h e compare i n s t r u c t i o n s i s 127 (177 c h a r a c t e r s . The maximum data f i e l d l e n g t h f o r t h e move i n d i r e c t inatruct!?on i s 8191 (17777*) c h a r a c t e r s . I f L (LU and LZ, combined) i s 0, the i n s t r u c t i o n becomes a pass. For overlapping move i n s t r u c t i o n s , the address of t h e source f i e l d ( s p e c i f i e d by K1) must be g r e a t e r than the address of t h e r e s u l t f i e l d ( s p e c i f i e d by K 2 ) t o provide proper f i e l d overlap. I f K1 i s l e s s than K2, p a r t of the source f i e l d i s changed during execution. The amount of change is determined by t h e number of CM c o n f l i c t s encountered. Overlapping f i e l d s should not contain more than 377 ( o c t a l ) c h a r a c t e r s because an exchange jump i n t e r r u p t s any compare/ move operation having a decremented f i e l d l e n g t h g r e a t e r than 377 ( o c t a l ) . CP ComparelMove Instructions 464 j K Move i n d i r e c t 59 51504847 30 29 Any i n s t r u c t i o n s located i n t h e lower two p a r c e l s of t h e i n s t r u c t i o n word do not execute. Bj plus K s p e c i f i e s a r e l a t i v e address i n CM f o r t h e following d e s c r i p t o r word. The d e s c r i p t o r word s p e c i f i e s the movement of t h e source f i e l d t o t h e r e s u l t f i e l d . The movement i s from l e f t t o r i g h t through the f i e l d . R e g i s t e r XO clears a t the end of t h e execution. 465 Move d i r e c t DM This i n s t r u c t i o n moves t h e source f i e l d t o the r e s u l t f i e l d as s p e c i f i e d by t h e 60-bit i n s t r u c t i o n word. The f i e l d l e n g t h i s l i m i t e d t o a 7-bit count. Compare collated CC This instruction compares the field designated by K1,Cl with the field designated by K2,C2 as specified by the 60-bit instruction word. The compare is from left to right through the fields until two unequal characters are found. These two characters are then collated and referenced in the collate table beginning at address A0 (table 4-10). If the table values found for the two unequal characters are equal, the compare continues until another pair of characters is unequal or until the field length is exhausted. If the table values found for the two unequal characters are unequal, XO is set prior to instruction termination as follows: If field K1 is greater than field K2, set XO to 0000 0000 0000 0000 Oxxx. If field K1 is equal to field K2, set XO to 0000 0000 0000 0000 0000. If field K1 is less than field K 2 , set XO to 7777 7777 7777 7777 7yyy where is the complement of wx. yyy The value of the three octal numbers xxx that are stored in XO is determined by the equation L minus N equals xxx (L is the length of the field, and N is the number of-pairsof characters that were collated equal prior to instruction In other words, xxx is the number of pairs of characters not yet termination). compared plus 1. The A0 register contains the starting word address of an 8-word, 64-character collate table (table 4-10). This table must have been previously stored in consecutive CM locations. The collated value of a character is found by examining the collate table. The upper 3 bits of the character to be collated are added to A0 to obtain the relative address of the word containing the collated value. The lower 3 bits of the character to be collated specify the character address of the collated value. Example: Suppose the character under examination is an octal 63. The 6 is added to the A0 to form the word address. The 3 is used to pick the correct character from that word. The value of 63 is 63 in the collate table. CP ComparelMove Instructions Table 4-10. Collate Table Address Collating character Locations 467 Compare uncollated CU This instruction is similar to the 466 instruction except that the collate table is not used. The XO register is set when the first pair of unequal characters is encountered or when the field length is exhausted. CP Set Instructions CP Set lnstructions Table 4-11 lists the CP set instructions. Opcodes 50 through 57 obtain operands from CM for computation and deliver the results back into CM. The remaining opcodes operate on B or X registers only. Table 4-11. CP Set Instructions Opcode Format Instruction Mnemonic Set Ai to (Aj) + K Set Ai to (Bj) + K Set Ai to (~j)+ K Set Ai to (Xj) + (Bk) Set Ai to (Aj) + (Bk) (Bk) Set A i to (Aj) Set Ai to (Bj) + (Bk) Set A i to (Bj) (Bk) Set Bi to (Aj) + K Set Bi to (Bj) + K Set Bi to (Xj) + K Set Bi to (Xj) 4- (Bk) Set Bi to (Aj) + (Bk) Set Bi to (Aj) - (Bk) Set Bi to (Bj) + (Bk) Set Bi to (Bj) (~k) Set Xi to (Aj) + K Set Xi to (Bj) + K Set Xi to (Xj) + K Set Xi to (~j)+ (Bk) Set Xi to (Aj) + (Bk) Set Xi to (Aj) - (Bk) Set Xi to (Bj) + (~k) Set Xi to (Bj) - (Bk) Read CM at ( X k ) to Xj Write Xj into CM at (Xk) SAi Aj+K - - - SAi Bj+K SAi Xj+K SAi Xj+Bk SAi Aj+Bk SAI Aj-Bk SAi Bj+Bk S A i Bj-Bk SBi Aj+K SBi Bj+K SBi Xj+K SBi Xj+Bk SBi Aj+Bk SBi Aj-Bk SBi Bj+Bk SBi Bj-Bk SXi Aj+K SXi Bj+K SXi Xj+K sxi Xj+Bk SXi Aj+Bk SXi Aj-Bk SXi Bj+Bk SXi Bj-Bk CRXj XK C W j Xk CP Set instructions Set Ai S e t Ai t o ( A j ) + K S M Aj +K This two-parcel i n s t r u c t i o n uses t h e lower-order 18 b i t s a s operand K. i n s t r u c t i o n r e a d s an operand from A j , forms t h e sum of t h e operand p l u s d e l i v e r s t h e r e s u l t t o Ai. I f t h e i d e s i g n a t o r i s nonzero, a r e f e r e n c e t o CM, using t h e r e s u l t a s t h e r e l a t i v e address. The type of r e f e r e n c e f u n c t i o n of t h e i d e s i g n a t o r value. i = O No CM r e f e r e n c e i = 1,2,3,4,5 Read from CM t o X i i = 6,7 Write i n t o CM from X i This K, and i s made is. a This i n s t r u c t i o n o b t a i n s operands from CM f o r computation and d e l i v e r s t h e r e s u l t back i n t o CM. 5 l i jK Set Ai t o (Bj) +K SAi Bj +K This two-parcel i n s t r u c t i o n uses the lower-order 1 8 bits a s operand K. i n s t r u c t i o n r e a d s an operand from B j , forms t h e sum of t h e operand p l u s d e l i v e r s t h e r e s u l t t o A i . I f t h e i d e s i g n a t o r i s nonzero, a r e f e r e n c e t o CM, using t h e r e s u l t as t h e r e l a t i v e address. The t y p e of r e f e r e n c e f u n c t i o n of t h e i d e s i g n a t o r value. i = 0 No CM r e f e r e n c e i = 1,2,3,4,5 Read from CM t o X i i = 6,7 Write i n t o CM from X i This K, and i s made is a T h i s i n s t r u c t i o n o b t a i n s operands from CM f o r computation and d e l i v e r s the r e s u l t back i n t o CM. CP Set lnstructions 5 2 i jK Set Ai t o (Xj) + K SAi X j + K This two-parcel i n s t r u c t i o n uses t h e lower-order 18 b i t s as operand K. i n s t r u c t i o n r e a d s an operand from X j , forms t h e sum-of t h e operand p l u s d e l i v e r s t h e r e s u l t t o Ai. I f t h e i d e s i g n a t o r i s nonzero, a r e f e r e n c e t o CM, using t h e r e s u l t a s t h e r e l a t i v e address. The t y p e of r e f e r e n c e f u n c t i o n of t h e i d e s i g n a t o r value. i = 0 No CM r e f e r e n c e i = 1,2,3,4,5 Read from CM t o X i i = 6,7 Write i n t o CM from X i This K, and i s made is a This i n s t r u c t i o n o b t a i n s operands from CM f o r computation and d e l i v e r s t h e r e s u l t back i n t o CM. 5 3 ijk S e t A i t o (Xj) + (Bk) This i n s t r u c t i o n r e a d s operands from X j and Bk, forms t h e sum of t h e operands, and d e l i v e r s t h e r e s u l t t o A i . I f t h e i d e s i g n a t o r i s nonzero, a r e f e r e n c e i s made t o CM, u s i n g t h e r e s u l t a s t h e r e l a t i v e a d d r e s s . The type of r e f e r e n c e i s a f u n c t i o n of t h e i d e s i g n a t o r v a l u e . i = O No CM r e f e r e n c e i = 1,2,3,4,5 Read from CM t o X i i = 6,7 Write i n t o CM from X i This i n s t r u c t i o n o b t a i n s operands from CM f o r computation and d e l i v e r s t h e r e s u l t back i n t o CM. CP Set instructions This i n s t r u c t i o n reads operands from A j and Bk, forms t h e sum of the operands, and d e l i v e r s t h e r e s u l t t o Ai. I f t h e i designator i s nonzero, a r e f e r e n c e i s made t o CM, using t h e r e s u l t a s t h e r e l a t i v e address. The type of r e f e r e n c e i s a f u n c t i o n of t h e i designator value. i = O No CM r e f e r e n c e i = 1,2,3,4,5 Read from CM t o X i i = 6,7 Write i n t o CM from X i This i n s t r u c t i o n o b t a i n s operands from CM f o r computation and d e l i v e r s t h e r e s u l t back i n t o CM. 5 5 i jk S e t lu t o ( A j ) - (Bk) SAi A j - Bk This i n s t r u c t i o n reads operands from A j and Bk, s u b t r a c t s the Bk operand from the A j operand, and d e l i v e r s t h e r e s u l t t o Ai. I f t h e i d e s i g n a t o r i s nonzero, i s made t o CM, using t h e r e s u l t a s t h e r e l a t i v e address. The type of reference i s a f u n c t i o n of t h e i d e s i g n a t o r value. a reference i = O No CM r e f e r e n c e i = 1,2,3,4,5 Read from M t o X i i = 6,7 Write i n t o CM from X i This i n s t r u c t i o n o b t a i n s operands from CM f o r computation and d e l i v e r s t h e r e s u l t s back i n t o CM. CP Set instructions 56ijk Set Ai t o (Bj) + (Bk) SAi B j + Bk This i n s t r u c t i o n r e a d s operands from Bj and Bk, forms t h e sum of t h e operands, and d e l i v e r s t h e r e s u l t t o Ai. I f t h e i d e s i g n a t o r i s nonzero, a r e f e r e n c e i s made t o CM, using t h e r e s u l t a s t h e r e l a t i v e address. The type of r e f e r e n c e i s a function of t h e i d e s i g n a t o r value. i s O No CM r e f e r e n c e i = 1,2,3,4,5 Read from CM t o X i i = 6,7 Write i n t o CM from X i This i n s t r u c t i o n o b t a i n s operands from CM f o r computation and d e l i v e r s the r e s u l t s back i n t o CM. Set Ai t o (Bj) 5 7 ij k - (Bk) SAI B j - Bk This i n s t r u c t i o n r e a d s operands from B j and Bk, s u b t r a c t s t h e Bk operand from the Bj operand, and d e l i v e r s t h e r e s u l t t o A i . I f t h e i d e s i g n a t o r i s nonzero, a reference i s made t o CM, using t h e r e s u l t as t h e r e l a t i v e a d d r e s s . The type of reference i s a f u n c t i o n of t h e i designator value. i = 0 No CM r e f e r e n c e 1 = 1,2,3,4,5 Read from CM t o X i i = 6,7 Write i n t o CM from X i This i n s t r u c t i o n o b t a i n s operands from CM f o r computation and d e l i v e r s t h e r e s u l t back i n t o CM. CP Set lnstructions Set Bi Set Bi to ( A j ) +K This two-parcel instruction uses the lower-order 18 instruction reads an operand from Aj, forms the sum delivers the result to Bi. The sum is formed in an mode. This instruction is for address modification 61ijK Set Bi to (Bj) + K SBi A j + K bits as operand K. This of the operand plus K and 18-bit one's complement in the increment registers. SBi Bj +K This two-parcel instruction uses the lower-order 18 bits as operand K. This instruction reads an operand from Bj, forms the sum of the operand plus K, and delivers the result to Bi. The sum is formed in an 18-bit one's complement mode. 62ijK Set Bi to (Xj) +K SBi Xj + K This two-parcel instruction uses the lower-order 18 bits as operand K. This instruction reads an operand from Xj, forms the sum of rhe operand plus K, and delivers the result to Bi. The sum is formed in an 18-bit one's complement mode. CP Set instructions 6 3 i jk Set B i t o (Xj) + (Bk) This i n s t r u c t i o n reads operands from X j and Bk, adds the operands, and d e l i v e r s the r e s u l t t o B i . The sum i s formed i n an 18-bit one's complement mode. 6 4 i jk Set B i t o (Aj) + (Bk) SBi Aj + Bk This i n s t r u c t i o n reads operands from A j and Bk, adds t h e operands, and d e l i v e r s t h e r e s u l t t o B i . The sum i s formed i n an 18-bit one's complement mode. 6 5 i jk Set B i t o (Aj) - (Bk) This i n s t r u c t i o n reads operands from A j and Bk, s u b t r a c t s t h e Bk operand from t h e Aj operand, and d e l i v e r s t h e r e s u l t t o B i . The d i f f e r e n c e i s formed in an 18-bit one's complement mode. If t h e i designator i s 0, t h i s becomes a pass instruction. CP Set Instructions Set B i t o ( ~ j )+ (Bk) S B i Bj + Bk This i n s t r u c t i o n reads operands from Bj and Bk, adds t h e operands, and d e l i v e r s o n e ' s complement mode. If t h e r e s u l t t o B i . The sum is formed i n a n 18+t t h e i d e s i g n a t o r i s 0 , t h i s becomes a read c e n t r a l memory i n s t r u c t i o n . 67ijk Set Bi t o (Bj) - (Bk) SBi Bj - Bk This i n s t r u c t i o n reads operands from Bj and Bk, s u b t r a c t s the Bk operand from t h e Bj operand, and d e l i v e r s t h e r e s u l t t o B i . The d i f f e r e n c e i s formed i n an 18-bit one's complement mode. If t h e i designator i s 0 , t h i s becomes a w r i t e c e n t r a l memory i n s t r u c t i o n . CP Set Instructions Set Xi 70i j K Set X i t o (Aj) + K SXI A j + K This two-parcel i n s t r u c t i o n uses t h e lower-order 18 b i t s as operand K. This i n s t r u c t i o n r e a d s a n operand from Aj, forms t h e sum of t h e operand p l u s K, and d e l i v e r s the r e s u l t t o X i . The sum i s formed. i n an 18-bit one's complement mode. The 18-bit r e s u l t i s sign-extended by copying t h e highest-order b i t of the r e s u l t i n t o t h e upper 42 b i t p o s i t i o n s i n X i . 7 1 ij K Set X i t o (Bj) +K SXi Bj + K This two-parcel i n s t r u c t i o n u s e s t h e lower-order 18 b i t s a s operand K. This i n s t r u c t i o n reads an operand from Bj, forms t h e sum of t h e operand p l u s K, and d e l i v e r s t h e r e s u l t t o X i . The sum i s formed i n an 18-bit one's complement mode. The 18-bit r e s u l t i s sign-extended by copying t h e highest-order b i t of t h e r e s u l t i n t o t h e upper 42 b i t p o s i t i o n s i n X i . 72i jK S e t X i t o (Xj) + K SXi X j +K This two-parcel i n s t r u c t i o n u s e s t h e lower-order 18 b i t s a s operand K. T h i s i n s t r u c t i o n reads a n operand from Xj, forms t h e sum of t h e operand p l u s K, and The sum i s formed i n an 18-bit o n e ' s complement delivers the r e s u l t to X i . mode. The 18-bit r e s u l t i s sign-extended by copying t h e highest-order b i t of the r e s u l t i n t o t h e upper 42 b i t p o s i t i o n s i n X i . CP Set Instructions SXi Xj 14 65 32 98 i j + Bk 0 k This i n s t r u c t i o n r e a d s operands from X j and Bk, adds t h e operands, and d e l i v e r s the result to Xi. The sum i s formed i n an 18-bit one's complement mode. The 18-bit r e s u l t i s sign-extended by copying t h e highest-order b i t of t h e r e s u l t i n t o t h e upper 42 b i t p o s i t i o n s i n X i . 7 4 i jk Set X i t o (Aj) + (Bk) SXi Aj + Bk This i n s t r u c t i o n r e a d s operands from Aj and Bk, adds t h e operands, and d e l i v e r s t h e r e s u l t t o X i . The sum i s formed i n an 18-bit one's complement mode. T h e 18-bit r e s u l t i s sign-extended by copying t h e highest-order b i t of t h e r e s u l t i n t o t h e upper 42 b i t p o s i t i o n s i n X i . 751jk Set X i t o ( A j ) - (Bk) SXi Aj - Bk This i n s t r u c t i o h reads operands from Aj and Bk, s u b t r a c t s t h e Bk operand from The d i f f e r e n c e i s formed i n a n t h e Aj operand, and d e l i v e r s t h e r e s u l t t o X i . 18-bit one's complement mode. The 18-bit r e s u l t i s sign-extended by copying t h e highest-order b i t of t h e r e s u l t i n t o t h e upper 42 b i t p o s i t i o n s i n X i . CP Set lnstructions 76i jk Set X i t o ( B j ) + (Bk) SXi Bj + Bk This i n s t r u c t i o n r e a d s operands from B j and Bk, adds the operands, and d e l i v e r s t h e r e s u l t t o X i . The sum i s formed i n an 18-bit o n e ' s complement mode. The 18-bit r e s u l t i s sign-extended by copying t h e highest-order b i t of t h e r e s u l t i n t o t h e upper 42 b i t p o s i t i o n s i n X i . 77ijk Set X i t o (Bj) - (Bk) SXi B j - Bk This i n s t r u c t i o n r e a d s operands from B j and Bk, s u b t r a c t s t h e Bk operand from The d i f f e r e n c e i s formed i n an t h e B j operand, and d e l i v e r s t h e r e s u l t t o X i . 18-bit o n e ' s complement mode. The 18-bit r e s u l t i s sign-extended by copying t h e highest-order b i t of t h e r e s u l t i n t o t h e upper 42 b i t p o s i t i o n s i n X i . CP Normalize Instructions Read central memory at (Xk) to Xj CR X j , Xk This instruction loads into Xj the word at location (Xk), where Xk is a right-justified 21-bit relative word address. Bits 21 through 59 of Xk are ignored. If the 21 bits of Xk are greater than or equal to FLC, an address-out-of-range condition is detected. 670jk Write Xj into central memory at (Xk) cw xj, Xk [is instruction stores Xj in location (Xk), where Xk is a 21-*bitrelative wort address. Bits 21 through-59of Xk are ignored. If the 21 bits of Xk are greater than or equal to FLC, an address-out-of-range condition is detected. CP Normalize lnstructions The normalize instructions (table 4-12) perform normalizing operations in floating-point format and deliver the normalized result to Xi. Table 4-12. CP Normalize Instructions -. . Opcode Format Instruction Mnemonic 24 25 ijk ijk Normalize (Xk) to Xi and Bj Round normalize (Xk) to Xi and Bj NXi Bj Xk ZXi Bj Xk C P Normalize lnstructions Normalize 24ijk Normalize (Xk) t o X i and Bj NXi B j , X k This i n s t r u c t i o n reads one operand from X k , performs a normalizing o p e r a t i o n on t h i s word i n floating-point format, and d e l i v e r s t h e normalized r e s u l t t o X i . I n a d d i t i o n , a p o s i t i v e i n t e g e r s h i f t count i s s e n t t o Bj. This s h i f t count i s the number of b i t p o s i t i o n s of s h i f t required t o normalize t h e o r i g i n a l operand coefficient . The normalizing operation c o n s i s t s of r e p o s i t i o n i n g t h e c o e f f i c i e n t p o r t i o n of the operand and then a d j u s t i n g t h e exponent p o r t i o n of t h e operand t o l e a v e t h e value of t h e r e s u l t unaltered. The c o e f f i c i e n t i s s h i f t e d towards t h e higher-order b i t p o s i t i o n s of t h e word. The c o e f f i c i e n t i s s h i f t e d the minimum number of b i t p o s i t i o n s required t o make b i t 47 d i f f e r e n t from s i g n b i t 59. This places t h e most-significant b i t of t h e c o e f f i c i e n t i n t h e highest-order p o s i t i o n . The exponent i s then decreased by the number of b i t p o s i t i o n s shifted. Two sample computations a r e l i s t e d i n o c t a l n o t a t i o n t o i l l u s t r a t e the o p e r a t i o n performed. The following example involves a p o s i t i v e f l o a t i n g - p o i n t number. The following example involves a negative floating-point number. Normalizing a number with e i t h e r a +O o r a -0 c o e f f i c i e n t s e t s a s h i f t count i n Bj t o 48 (decimal) and e n t e r s X i with +O. If Xk contains a n i n f i n i t e q u a n t i t y x ) o r an i n d e f i n i t e q u a n t i t y (1777xxx x or (3777xxx...x o r 40OOxgx x ) , no s h i f t t a k e s place. The content of Xk i s copied t o X i , and B j 6000xxx i s s e t t o 0. Corresponding i n f i n i t e and i n d e f i n i t e e x i t conditions a r e a l s o s e t i n t h e CP f o r e x i t mode a c t i o n . I f the exponent i s less than negative 1777 with a zero c o e f f i c i e n t , t h e c o n t e n t s of X i and Bj a r e s e t t o 0. For f u r t h e r information, r e f e r t o Floating-point Arithmetic under CP Programming i n chapter 5. ... ... ... CP Normalize Instructions Round Normalize Round normalize (Xk) t o X i and B j ZXi Bj, This i n s t r u c t i o n reads one operand from Xk, performs a rounding and then a normalizing o p e r a t i o n i n floating-point format, and d e l i v e r s t h e round normalized r e s u l t t o X i . I n a d d i t i o n , a p o s i t i v e i n t e g e r s h i f t count i s s e n t t o B j . This s h i f t count i s t h e number of b i t p o s i t i o n s of s h i f t required t o normalize t h e o r i g i n a l operand c o e f f i c i e n t . The rounding o p e r a t i o n c o n s i s t s of adding a b i t t o t h e c o e f f i c i e n t p o r t i o n of t h e operand i n a b i t p o s i t i o n immediately below the l e a s t - s i g n i f i c a n t b i t p o s i t i o n . This round b i t h a s a value equal t o t h e complement of the operand s i g n b i t . The r e s u l t i n c r e a s e s t h e magnitude of t h e c o e f f i c i e n t by one-half t h e value of t h e l e a s t - s i g n i f i c a n t b i t . The normalizing operation c o n s i s t s of r e p o s i t i o n i n g t h e c o e f f i c i e n t and a d j u s t i n g t h e exponent t o l e a v e t h e v a l u e of t h e r e s u l t i n g f l o a t i n g - p o i n t q u a n t i t y unaltered. The c o e f f i c i e n t i s s h i f t e d towards t h e higher-order b i t p o s i t i o n s . The round b i t i s s h i f t e d along with t h e c o e f f i c i e n t . The displacement i s the minimum number of b i t p o s i t i o n s r e q u i r e d t o make b i t 47 d i f f e r e n t from s i g n b i t 59. This places t h e most-significant b i t of the c o e f f i c i e n t i n t h e highest-order b i t p o s i t i o n . The exponent i s decreased by t h e number of b i t p o s i t i o n s s h i f t e d . Two sample computations a r e l i s t e d i n o c t a l n o t a t i o n t o i l l u s t r a t e the normalizing o p e r a t i o n performed. An example t h a t involves a p o s i t i v e floating-point number i s a s follows. The following example involves a negative number. ( x i ) = 5751 3012 7777 7755 1537 ... ... If Xk contains e i t h e r an i n f i n i t e q u a n t i t y (3777mrx x o r 4000xxx x ) o r an i n d e f i n i t e q u a n t i t y (1777xxx x o r 6OOOxn..x .) , no s h i f t t a k e s place. The content of Xk i s copied t o X i , and B j i s s e t t o 0. Corresponding i n f i n i t e and i n d e f i n i t e e x i t conditions a r e a l s o s e t i n t h e CP f o r e x i t mode a c t i o n . ... Refer t o Floating-Point Arithmetic under CP Programming i n chapter 5. CP Pass Instructions CP Pass lnstructions The pass instructions (table 4-13) perform no operation and are used for filling words to get the next instruction properly positioned. CP Pass InatructLons Table 4-13. Opcode Format Instruction 460 461 462 463 xx Pass Pass Pass Pass xx xx xx Mnemonic Pass 46Oxx rhru 463xx Pass These lnstructions fill program instruction words where necessary to match jump destinations with word boundaries. The j and k designators are Ignored, and a nonzero value has no effect in this instruction. CP Illegal Instructions CP Illegal lnstructions The illegal instructions (table 4-14) cause an exchange to CYBER 170 monitor mode, when in CYBER 170 job mode, and cause a jump to executive state when in CYBER 170 monitor mode. Table 4-14. Opcode CP Illegal Instructions Format Instruction Mnemonic jK Error exit to MA or interrupt to executive mode Illegal instruction (Trap 180) Read one word from UFM to Xj Write one word from Xj to UEM RT OOxxx 017 014 015 jK jK w xk WXj Xk Error Exit Error exit to MA when CYBER 17 MF clear Interrupt to executive mode when CYBER 170 MF set 00- This instruction causes an illegal instruction error exit. CYBER 170 MF is the hardware monitor flag. Refer to Illegal Instructions in chapter 5 . Illegal l nstruction 017jk - Illegal Instruction Refer to Illegal Instructions in chapter 5. CP Illegal instructions l llegal Read/Write 014 j k Read one word from (Xk + RAE) to X j This i n s t r u c t i o n i s i l l e g a l i f t h e UEM enable f l a g i n t h e CYBER 170 exchange package i s c l e a r . This i n s t r u c t i o n reads t h e 60-bit word from UKM l o c a t i o n Xk plus RAE i n t o X j . Xk i s l e s s than FLE. The number of b i t s checked f o r an address-out-of-range c o n d i t i o n v a r i e s , depending on the addressing mode of UEM. I n standard addressing mode, 24 b i t s of Xk a r e checked a g a i n s t 23 b i t s of FLE with b i t 23 of FLE equal t o 0. In expanded addressing mode, 30 b i t s of Xk a r e checked a g a i n s t 29 b i t s of FLE with b i t 29 of FLE equal t o 0. If Xk i s g r e a t e r than o r equal t o FLE, an addressout-of-range condition i s d e t e c t e d , 015 jk Write one word from Xj t o (Xk + RAE) This i n s t r u c t i o n is i l l e g a l i f t h e UEM enable f l a g i n the CYBER 170 exchange package i s c l e a r . This i n s t r u c t i o n w r i t e s the 60-bit word from X j i n t o the UEM l o c a t i o n Xk plus RAE. Xk i s l e s s than FLE. The number o f b i t s checked f o r an address-out-of-range condition v a r i e s , depending on the addressing mode of UEM. I n standard addressing mode, 24 b i t s of Xk a r e checked a g a i n s t 23 b i t s of FLE with b i t 23 of FLE equal t o 0. I n expanded addressing mode, 30 b i t s of Xk a r e checked a g a i n s t 29 b i t s of FLE with b i t 29 of FLE equal t o 0. If Xk i s g r e a t e r than o r equal t o FLE, an address-out-of-range condition i s detected. CP Mask Instruction CP Mask lnstruction Form Mask Form mask of jk b i t s t o X i This i n s t r u c t i o n g e n e r a t e s a masking word u s i n g t h e j and k d e s i g n a t o r s a s The j and k parameters. No operands a r e read from o p e r a t i n g r e g i s t e r s . d e s i g n a t o r s a r e t r e a t e d a s a s i n g l e , 6-bit o c t a l q u a n t i t y t o d e s i g n a t e t h e width of t h e masking f i e l d . A f i e l d of l ' s , beginning a t t h e highest-order end The completed of t h e word, i s extended downward on a background of 0 ' s . masking word c o n s i s t s of 1 b i t s i n t h e highest-order jk b i t p o s i t i o n s and 0 b i t s i n t h e remainder of t h e word. This masking word i s t h e n d e l i v e r e d t o X i . The following a r e sample parameters. This i n s t r u c t i o n g e n e r a t e s v a r i a b l e width masks f o r l o g i c a l o p e r a t i o n s . T h i s i n s t r u c t i o n , t o g e t h e r with a s h i f t i n s t r u c t i o n , g e n e r a l l y c r e a t e s an a r b i t r a r y f i e l d mask f a s t e r t h a n reading a pregenerated mask from CM. CP Pop Count Instruction CP Pop Count lnstruction Population Count 47ixk Population count of (Xk) t o X i C X i Xk This i n s t r u c t i o n r e a d s one operand from Xk, counts t h e number of one b i t s i n t h e operand, and s t o r e s t h e count i n X i . The count d e l i v e r e d t o X i is a p o s i t i v e i n t e g e r . If t h e operand i s a l l l ' s , a count of 60 (decimal) i s delivered t o X i . I f operand i s a l l z e r o s , a 0 ' s word i s d e l i v e r e d t o X i . CP Read Free Running Counter lnstruction Read Free-Running Counter 016 jk Read f r e e . running counter T h i s I n s t r u c t i o n t r a n s f e r s t h e c u r r e n t c o n t e n t s of t h e 48-bit f r e e running counter t o t h e X j r e g i s t e r . The l e f t m o s t 1 2 b i t s of X j a r e s e t t o 0. The k f i e l d i s ignored. This i n s t r u c t i o n i s a s i n g l e p a r c e l i n s t r u c t i o n t h a t can be l o c a t e d i n any parcel. PP Instruction Descriptions PP lnstruction Descriptions The peripheral processor (PP) instruction s e t comprises the following eight subgroups . Load/Store. Arithmetic. Logical. Replace. Branch. Central Memory Access. Input/Output. Other. PP Instruction Descriptions PP lnstruction Formats Figure 4-2 shows PP instruction formats. PP instructions are 16 or 32 bits long. In instruction descriptions, the operation code is given either by two or three octal digits. The third digit, when used, indicates the state of the s-bit (0 or 1) in 110 instructions (refer to table 4-15). The upper 4 bits of the PP instructions must be 0 to ensure that the Instructions operate as defined in this chapter. Table 4-15. PP Nomenclature Term Description Specifies instruction operation code. Specifies I/O instruction subcode. Specifies channel number. Refers to the A register (arithmetic register) or the content of the A register. Refers to the content of the word at the CM address specified by the A register. Refers to the P register or to the content of the P register (program address register). Refers to the R register or to the content of the R register (relocation register). Refers to the content of the word at the PP memory address specified by the d field (direct mode). Refers to the content of the word at the PP memory address specified by the content of the word at the PP memory address specified by the d field (indirect mode). Refers to the PP memory address specified by the m field indexed by the content of the word at the PP memory addressed specified by the d field. (rn + (dl) Refers to the content of rhe word at the PP memory address specified by the m field indexed by the content of the word at the PP memory address specified by the d field (memory mode). PP Instruction Descriptions 31 2827 22 20 1615 ZEROS OPCODE s Figure 4-2. 0 1211 1 m PP I n s t r u c t i o n Formats PP Data Format Figure 4-3 shows PP data format and how 12-bit data i s packed i n t o 64-bit CM words or unpacked from 64-bit CM words. ZEROS 64 - BIT DATA WORD I N CENTRAL MEMORY LOCATION 15 1211 0 d ZEROS a d+ 1 ZEROS b d+2 ZEROS c d+3 d+4 ZEROS d e ZEROS 64 - BIT DATA WORD I N PP MEMORY Figure 4-3. PP Data Format PP LoadlStore lnstructions PP delocation Register Format Figure 4-4 shows PP relocation (R) register format. This register is loadedfrom/stored-into PP memory by instructions 24 and 25 (load/store R register). 27 I 65 18 17 I a b 0 ZEROS RELOCATION REGISTER I N PP HARDWARE LOCATION 15 12 d d+ I ZEROS RELOCATION REGISTER IN PP MEMORY Figure 4-4. PP Relocation (R) Register Format PP LoadBtore Instructions Load and store instructions (table 4-16) transfer 6-, lo-, 12-, and 18-bit quantities between the PP A register and the PP memory. Table 4-16. Opcode PP Load/Store Instructions Format Instruction Mnemonic Load d Load complement d Load dm Load R Load (dl Load ( ( d l Load (m+(d)) Store R Store (d) Store ((dl) Store (m+(d)) LDN LCH LDC LRD LDD d d m,d d d LDI d LDM SRD STD ST1 STM m,d d d d m,d PP LoadlStore Instructions Load Load d This instruction clears the A register and loads d. are 0. Load complement d LDN d The upper 12 bits of A LCN d This instruction clears the A-registerand loads the complement of d. upper 12 bits of A are 1. 2Odm Load dm The LDC dm This instruction clears the A register and loads an 18-bit quantity consisting of d as the upper 6 bits and m as the lower 12 bits. The content of the location (P plus 1) which follows the present program address (I?) is read to provide m. Load R register LRD d Figure 4-4 shows B register format. If d is not equal to 0, this instruction loads the upper 10 bits of the R register (bits 18-27) from the rightmost 10 bits of PP memory location d. The 12 bits contained in PP memory location d plus 1 are loaded into the next 12 bits of the R register (bits 6 through 17). If d equals 0, the instruction is a pass. LDD d Load (dl This instruction clears the A register and loads the content at location d. The upper 6 bits of A are 0. 40d Load ((dl) LDI d This instruction clears the A register and loads a 12-bit quantity that is obtained by indirect addressing. The upper 6 bits of A are 0. Location d is read from PPM, and the word read is used as the operand address. 5Odm Load (m + (d)) LDM m,d This instruction clears the A register and loads a 12-bit quantity. The upper 6 bits of A are 0's. The 12-bit operand is obtained by indexed direct addressing. In indexed direct addressing, the quantity m, which i s read from PPM.location P plus 1, serves as the base operand address to which the content of d is added. If d equals 0, the operand address is m, but if d is not equal to 0, m plus the location d may be used as an content in d is the operand address. Therefore, index quantity to modify operand addresses. PP LoadlStore Instructions Store Store R register SRD d Figure 4-4 shows R register format. If d is not equal to 0, this instruction stores the upper 10 bits of the R register (bits 18 through 27) into the righrmost 10 bits of PP memory location d. The 12 bits contained In PP memory location d plus 1 are stored into the next 12 bits of the R register (bits 6 through 17). If d equals 0, the instruction is a pass. 34d Store (d) STD d This instruction stores the lower 12 bits of the A register at location d. 44d Store ( ( d l ) ST1 d This instruction stores the lower 12 bits of the A register at the Location specified by the content of location d . 54dm Store (m + (d)) STM m,d This instruction stores the lower 12 bits of the A register in the location determined by indexed direct addressing. In indexed direct addressing, the quantity m, which is read from PPM location P plus 1, serves as the base operand address to which the content of d 1s added. If d equals 0, the operand address is m, but if d is not equal to 0, m plus the content in d is the operand address. Therefore, location d may be used as an index quantity to modify operand addresses. PP Arithmetic lnstructions PP ~rithmeticInstructions The PP arithmetic instructions (table '4-17) perform integer arithmetic using the PP A register contents as one operand, with the other operand specified by the instruction. The result replaces the original contents of A. The PP considers the operands as one's complement integers and performs the arithmetic in one's complement. Table 4-17. Opcode PP Arithmetic Instructions Format Instruction Mnemonic Add d Add dm Add (d) Add ((dl) Add (m+(d)) Subtract d Subtract ( d l Subtract ((d)) Subtract (m+(d)) ADN d ADC m,d ADD d AD1 d ADM m,d SBN d SBD d SBI d SBM m,d Arithmetic Add 16d Add d ADN d This instruction adds d (treated as a 6-bit positive quantity) to the content of the A register. 21dm Add dm ADC dm This instruction adds to the A register the 18-bit quantity consisting of d as the upper 6 bits and m as the lower 12 bits. The content of the location ( P plus 1) which follows the present program address (P) is read to provide m. PP Arithmetic Instructions ADD Add (dl d This instruction adds the content at location d (treated as a 12-bit positive quantity) to the A register. This instruction adds to the content of the A register a 12-bit operand (treated as a positive quantity) obtained by indirect addressing. Location d is read from PPM, and the word read is used as the operand address. 51dm Add (m + (dl) ADM m,d This instruction adds the 12-bit operand (treated as a positive quantity) read by indexed direct addressing to the A register. In indexed direct addressing, the quantity m, which is read from PPM location P plus 1, serves as the base operand address to which the content of d is added. If d equals 0, the operand address is m, but if d is not equal to 0, m plus the content in d is the operand address. Therefore, location d may be used as an index quantity to modify operand addresses. PP Arithmetic Instructions Arithmetic Subtract 17d Subtract d SBN d This instruction subtracts d (treated as a 6-bit positive quantity) from the content of the A register. 32d SBD d Subtract (d) This instruction subtracts the content at location d (treated as a 12-bit positive quantity) from the A register. 42d SBX d Subtract ( (dl ) This instruction subtracts from the A register a 12-bit operand (treated as a positive quantity) obtained by indirect addressing. Location d is read from PPM, and the word read is used as the operand address. 52dm Subtract (m + (d)) SBM m,d This instruction subtracts the 12-bit operand (treated as a positive quantity) read by indexed direct addressing from the A register. In indexed direct addressing, the quantity m, which is read from PPM location P plus 1, serves as the base operand address to which the content of d is added. If d equals 0, the operand address is m, but if d is not equal to 0, m plus the content in d is the operand address. Therefore, location d may be used as an index quantity to modify operand addresses. PP Logical lnstructions PP Logical Instructions The logical instructions (table 4-18) perform operations with one operand as the PP A register contents, and the other as specified by the instruction. The result replaces the origiml contents of A. Table 4-18. PP Logical Instructions Opcode Format Instruction Mnemonic 10 13 11 d d d dm d d Shift d Selective clear d Logical difference Logical difference Logical difference Logical difference Logical difference Logical product d Logical product dm SHN d SCN d LMNd LMC m,d LMDd LMI d LMM m,d LPN d LPC m,d 23 33 43 53 12 22 dm d dm d dm (d) ( (d) ) (m+(d)) Shift 10d Shift d This instruction If d is positive (40 through 771, Thus, d equal to a right-shift of SHN d shifts the content of the A register right or left d places. (00 through 3 7 ) , the shift is left circular. If d is negative the shift is right circular (end-off with no sign extension). 06 requires a left-shift of s i x places; d equal to 71 requires six places. Selective Clear 13d Selective clear d SCN d This instruction clears any of the lower 6 bits of the A register where corresponding bits of d are 1. The upper 12 bits of A are not altered. PP Logical instructions Logical Difference lld Logical difference d LMN d This instruction forms the bit-by-bit logical difference of d and the lower 6 bits of A in the register in A. This is equivalent to complementing individual bits of A that correspond to bits of d that are 1. The upper 12 bits of A are not altered. 23dm Logical difference dm LMC dm This instruction forms the bit-by-bit logical difference of the content of the A register and the 18-bit quantity dm in A. This is equivalent to complementing individual bits of A which correspond to bits of dm that are 1. The upper 6 bits of the quantity consist of d, and the lower 12 bits are the content of the location (P plus 11, which follows the present program address (P). 33d Logical difference ( d ) This instruction forms in the A register the bit-by-bit logical difference of the lower 12 bits of the A register and the content at location d. This is equivalent to complementing individual bits of A that correspond to bits in location d that are 1's. The upper 6 bits are not altered. PP Logical Instructions Logical difference ((dl) This instruction forms in the A register the bit-by-bit logical difference of the lower 12 bits of the A register and the 12-bit operand read by indirect addressing. Location d is read from PPM, and the word read is used as the operand address. The upper 6 bits of A are not altered. 53dm -- Logical difference (m (PI + (d)) LMM m,d (P+l) This instruction forms the bit-by-bit logical difference of the lower 12 bits of the A register and a 12-bit operand obtained by indexed direct addressing in the A register. The upper-6 bits of A are not altered. In indexed direct addressing, the quantity m, which i s read from PPM location P plus 1, serves as the base operand address to which the content of d is added. If d equals 0, the operand address is m, but if d is not equal to 0, m plus the content in d is the operand address. Therefore, location d may be used as an index quantity to modify operand addresses. PP Logical Instructions Logical Product 12d Logical product d LPN d This instruction forms the bit-by-bit logical product of d and the lower 6 bits of the A register and leaves this quantity in the lower 6 bits of A. The upper 12 bits of A are 0. 22dm Logical product dm LPC dm This instruction forms the bit-by-bit logical product of the content of the A register and the 18-bit quantity dm in A. The upper 6 bits of this quantity consist of d, and the lower 12 bits are the content of the location (P plus I), which follows the present program address (PI. PP Replace Instructions PP Replace Instructions The replace instructions (table 4-19) perform integer arithmetic with one operand as the contents of A and the other as specified by the instruction. The result replaces the original contents of A and the contents of the other operands location. The result stored in location d is either the rightmost 12 bits (for the normal instructions) or the rightmost 16 bits (for the long instructions) of the A register. Therefore, since A contains .18 bits, the value remaining in A cannot equal the value stored in PP memory location d. The PP considers the operands as one's complement integers and performs one's complement arithmetic. Table 4-19. PP Replace Instructions - -- Opcode Format Instruction Mnemonic Replace add (d) Replace add 1 (dl Replace add ((dl Replace add 1 ((dl ) Replace add (m+(d)) Replace add 1 (m+(d)) Replace subtract 1 (m+(d)) Replace subtract 1 ( d l Replace subtract 1 ((d)) RAD d AOD d W d A01 d RAM m,d AOM m,d SOM m,d SOD d SO1 d PP Replace Instructions Replace Add 35d Replace add ( d ) RAD d This i n s t r u c t i o n adds t h e q u a n t i t y a t l o c a t i o n d t o t h e content of t h e A r e g i s t e r and s t o r e s t h e lower 1 2 b i t s of t h e r e s u l t a t l o c a t i o n d. The r e s u l t remains i n A a t the end of the o p e r a t i o n , and the o r i g i n a l content of A i s destroyed. 36d Replace add 1 ( d l AOD d This i n s t r u c t i o n r e p l a c e s t h e q u a n t i t y a t l o c a t i o n d with i t s o r i g i n a l value p l u s 1. The r e s u l t remalns i n t h e A r e g i s t e r a t t h e end of the o p e r a t i o n , and t h e o r i g i n a l content of A i s destroyed. 45d Replace add ( ( d l ) RAI d This i n s t r u c t i o n adds t h e operand, which i s obtained from the l o c a t i o n s p e c i f i e d by t h e content a t l o c a t i o n d , t o the content of t h e A r e g i s t e r . The lower 1 2 b i t s of t h e sum r e p l a c e the o r i g i n a l operand. The r e s u l t remains i n A a t the end of t h e operation. PP Replace lnstructrons Replace add 1 ((dl ) This instruction replaces the operand, which is obtained from the location specified by the content at location d, by its original value plus 1. The result remains in the A register at the end of the operation, and the original content of A is destroyed. Replace add (m + (dl) RAM m,d This instruction adds the operand, which is obtained from the location determined by indexed direct addressing, to the A register. The lower 12 bits of the sum replace the original operand in PPM. The result remains in A at the end of the operation, and the original content of A is destroyed. In indexed direct addressing, the quantity m, which is read from PPM location P plus 1, serves as the base operand address to which the content of d is added. If d equals 0, the operand address is m, but if d is not equal to 0, m plus the content in d is the operand address. Therefore, location d may be used as an index quantity to modify operand addresses. 56dm Replace add 1 (m + (dl) AOM m,d This instruction replaces the operand, which is obtained from the location determined by indexed direct addressing, by its original value plus 1. The result remains in the A register at the end o f the operation, and the original content of A is destroyed. In indexed direct addressing, the quantity m, which is read from PPM location P plus 1, serves as the base operand address to which the content of d is added. If d equals 0, the operand address is m y but if d is not equal to 0, m plus the content in d is the operand address. Therefore, location d may be used as an index quantity to modify operand addresses. PP Replace lnstructions Replace Subtract 37d Replace subtract 1 (d) SOD d This instruction replaces the quantity at location d with its original value minus 1. The result remains in the A register at the end of the operation, and the original content of A is destroyed. 47d Replace subtract 1 ((d)) This instruction replaces the operand, which is obtained from the location specified by the content at location d, by its original value minus 1. The result remains in the A register at the end of the operation, and the original content of A is destroyed. 57dm Replace subtract 1 (m + (d)) SOM m,d This instruction replaces the operand, which is obtained from the location determined by indexed direct addressing, by its original value minus 1. The result remains in the A register at the end of the operation, and the original content of A is destroyed. In indexed direct addressing, the quantity m, which is read from PPM location P plus 1, serves as the base operand address to which the content o f d is added. If d equals 0, the operand address is m, but if d is not equal to 0, m plus the content in d is the operand address. Therefore, location d may be used as an index quantity to modify operand addresses. PP Branch Instructions PP Branch lnstructions The branch instructions (table 4-20) allow departure from sequential instruction execution. PP Branch Instructions Table 4-20. Opcode Format Instruction Mnemonic 01 02 03 04 dm Long jump to m + (dl Return jump to m + (d) Unconditional jump d Zero jump d Nonzero jump d Plus jump d Minus jump d Jump to m if channel c Jump to m if channel c Jump to m if charnel c Jump to m if channel c Jump to m i f chamel c Jump to m if channel c L J M m,d 05 06 07 640 650 660 661 670 671 dm d d d d d cm cm cm cm em cm RJM UJN ZJN NJN PJN MJN active AJM inactive full error flag set empty error flag clear. IJM FJM SFM EJM CFM m,d d d d d d m,c m,c m,c m,40B+c m , ~ m,40B+c Long Jump Oldm Long jump to m + (d) LJM m,d This instruction jumps to the address given by m plus the content of location d. If d equals 0, m is not modified. PP Branch instructions Return Jump 02dm Return jump to m + (d) RJM m,d This instruction jumps to the address given by m plus the content of location d. If d equals zero, m is not modified. The current program address (P) plus 2 is stored at the jump address. The next instruction starts at the jump address plus 1. The subprogram exits with a long jump or normal sequencing to the jump address minus 1, which in turn contains a long jump, 0100. This returns the original program address plus 2 to the P register. Unconditional Jump 03d Unconditional jump d UJN d This instruction provides an unconditional jump to any address up to 31 (decimal) locations forward or backward from the current program address. The value of d is added to the current program address. If d is positive (01 through 37), 0001 through 0037 is added, and the jump is forward. If d is negative (40 through 76), 7740 through 7776 is added, and the jump is backward. When d equals 00 or 77, the PP hangs. A deadstart is required to restart the PP. PP Branch Instructions Zero/Nonzero Jump 04d Zero jump d This i n s t r u c t i o n provides a c o n d i t i o n a l jump t o any address up t o 31 (decimal) l o c a t i o n s forward o r backward from t h e c u r r e n t program address. If the c o n t e n t of t h e A r e g i s t e r i s 0 , t h e jump i s taken. I f t h e content of A i s nonzero, t h e next i n s t r u c t i o n executes from P plus 1. A -0 (777777) i s t r e a t e d a s nonzero. For i n t e r p r e t a t i o n of d , r e f e r t o the 03 i n s t r u c t i o n , O5d Nonzero jump d NJN d This i n s t r u c t i o n provides a c o n d i t i o n a l jump t o any a d d r e s s up t o 3 1 (decimal) l o c a t i o n s forward o r backward from t h e c u r r e n t program address. I f t h e content of t h e A r e g i s t e r i s nonzero, t h e jump i s taken. I f t h e content of A i s 0 , t h e next i n s t r u c t i o n executes from P p l u s 1. A -0 (777777) i s t r e a t e d a s nonzero. If d i s p o s i t i v e (01 through 371, 0001 through 0037 i s added, and the jump i s forward. I f d i s negative (40 through 761, 7740 through 7776 i s added, and t h e jump i s backward. When d equals 00 o r 77, t h e PP hangs. A d e a d s t a r t i s required t o r e s t a r t t h e PP. PP Branch Instructions Plus/Minus Jump 06d Plus jump d This instruction provides a conditional jump to any address up to 31 (decimal) locations forward or backward from the current program address. If the sign of the A register is positive, the jump is taken. If the sign of A is negative, the next instruction executes from P plus 1. A +O is treated as a positive quantity. A -0 i s treated as a negative quantity. If d is positive (01 through 37), 0001 through 0037 is added, and the jump is forward. If d is negative (40 through 761, 7740 through 7776 i s added, and the jump is backward. When d equals 00 or 77, the PP hangs. A deadstart is required to restart the PP. 07d Minus jump d This instruction provides a conditional jump to any address up to 31 (decimal) locations forward or backward from the current program address. If the content of the A register is negative, the jump is taken. If the content of A is positive, the next instruction executes from P plus 1. A +O is treated as a positive quantity. A -0 is treated as a negative quantity. If d is positive (01 through 37), 0001 through 0037 is added, and the jump is forward. If d is negative (40 through 761, 7740 through 7776 is added, and the jump is backward. When d equals 00 or 77, the PP hangs. A deadstart is required to restart the PP. PP Branch instructions Jump To m Jump to m if channel c active AJM m,c If channel c is active, this instruction causes a jump to m; otherwise, it is a pass. 650cm Jump to m if channel c inactive IJM m,c This instruction provides a conditional jump to a new address specified by m. The jump is taken if the channel specified by c is inactive. The next instruction is at P plus 2 if the channel is active. 660- Jump to m if channel c full FJM m,c This instruction provides a conditional jump to a new address specified by m. The jump is taken if the channel designated by c is full. The next instruction is at P plus 2 if the channel is empty. An input channel is full when the input equipment places a word in the channel and no PP has accepted that word. The channel is empty when a word has been accepted. An output c h a ~ e lis full when a PP places a word on the channel. The channel is empty when the output equipment accepts the word. P P Branch instructions 661cm Jump t o m i f channel c e r r o r f l a g s e t I f t h e channel c causes a jump t o When m i s s e t t o when t h e program 6 7 Ocm SFM m,c e r r o r f l a g i s s e t , t h i s i n s t r u c t i o n c l e a r s t h e e r r o r flag. and m. I f t h i s e r r o r f l a g i s c l e a r , t h e i n s t r u c t i o n is a p a s s . P p l u s 2 , t h e channel e r r o r f l a g i s u n c o n d i t i o n a l l y c l e a r e d r e a c h e s P p l u s 2. Jump t o rn i f channel c empty EJM m,c This i n s t r u c t i o n provides a c o n d i t i o n a l jump t o a new a d d r e s s s p e c i f i e d by m. The jump i s taken i f t h e channel s p e c i f i e d by c i s empty. The n e x t i n s t r u c t i o n i s a t P p l u s 2 i f t h e channel i s f u l l . An i n p u t channel i s f u l l when t h e i n p u t equipment p l a c e s a word i n t h e channel and no PP has a c c e p t e d t h a t word. The An o u t p u t channel i s f u l l when channel i s empty when a word has been accepted. a PP p l a c e s a word on t h e channel. The channel i s empty when t h e o u t p u t equipment a c c e p t s t h e word. 67 1cm Jump t o m i f channel c e r r o r f l a g c l e a r CFM m,c If If t h e channel c e r r o r f l a g i s c l e a r , t h i s i n s t r u c t i o n c a u s e s a jump t o m. t h i s e r r o r f l a g i s s e t , t h e i n s t r u c t i o n c l e a r s t h e e r r o r f l a g and proceeds with t h e n e x t i n s t r u c t i o n . When m i s s e t t o P p l u s 2 , t h e channel e r r o r f l a g i s u n c o n d i t i o n a l l y c l e a r e d when t h e program r e a c h e s P p l u s 2 . PP Central Memory Access Instructions PP Central Memory Access Instructions The PP central memory access instructions (table 4-21) provide the capability to read and mite CM words to and from PP memory. The PPs have read access to all CM storage locations, while the OS bounds register controls write and exchange accesses. The IOU performs CM addressing with real memory word addresses. To address all locations in the larger CM sizes available, the IOU uses address relocation to modify the CM address in the A register of the PP. If bit 46 in A is 1 during a PP central memory read or write instruction, the IOU adds the R register contents to A register bits 47 through 63 to produce the CM address. If bit 46 of A Is 0, the IOU does not perform address relocation but uses the A address. The R register contains an absolute 64-word starting boundary within CM. When relocation is desired, an absolute CM address is formed by concatenating six 0's to the rightmost end of the R contents and adding bits 47 through 63 of A. PP Central Memory Access Instructions Table 4-21. Opcode Format Instruction Mnemonic 60 61 62 63 d dm d dm Central read from (A) to d Central read ( d ) words from (A) to m Central write to (A) from d Central write (d) words to (A) from m CRD d CRM m,d CUD d CWM m,d Central Read Central read from (A) to d CRD d This instruction disassembles one 60-bit word from central memory into five 12-bit words and stores these in five consecutive PP memory locations, beginning with the leftmost 12 bits of the 60-bit word. The parameters of the transfer are as follows: If bit 17 of A is 0, A bits 0 through 16 contain the absolute address of the 60-bit word transferred. If bit 17 of A is 1, hardware adds relocation register R to zero-extended A bits 0 through 16 to obtain the absolute address of the 60-bit word transferred. For further information, refer to R Register under ~nput/~utput Unit in chapter 2, and PP Relocation Register Format at the beginning of this section on PP Instruction Descriptions. Field d gives the PP location that receives the first 12-bit word transferred. PP memory addressing is cyclic, and location 0000 follows location 7777. PP Central Memory Access Instructions 61dm Central read (dl words from (A) to m CRM d,m PP location 0000 is used by hardware. This instruction disassembles 60-bit words from central memory into 12-bit words, and places these in consecutive PP memory locations, beginning with the leftmost 12 bits of the first 60-bit word. The parameters of the transfer are as follows: If bit 17 of A is 0, A bits 0 through 16 contain the absolute address of the first 60-bit word transferred. If bit 17 of A is 1, hardware adds relocation register R to zero-extended A bits 0 through 16 to obtain the absolute address of the first 60-bit word transferred. For further information, refer to R Register under Input/Output Unit in chapter 2, and PP Relocation Register Format under PP Instruction Descriptions. PP location d must contain the number of 60-bit words transferred. Field m gives the PP location into which the first 12-bit word is placed. This instruction stores P plus 1 into PP location 0000 before beginning the transfer. After the transfer is completed, the next instruction is taken from 1 plus whatever address is stored in location 0000. If the transfer overwrites location 0000, execution resumes at the location specified by (0000) plus 1 and results are undefined. (PP memory addressing is cyclic, and location 0000 follows location 7777.) The A register is incremented by 1 after each 60-bit word is read from central memory. If the incrementing changes A bit 17, the central memory addressing is switched between direct address and relocation address modes. Refer to Central Memory Addressing by PPs in chapter 5. After the transfer is completed, the A register contains either the address of the last word transferred plus 1 (direct addressing) or the same address Less the contents of the relacation address register (relocation addressing), except as follows: If the last word transferred is from a relative address 3777768 and relocation is in effect, then the A register is cleared, and the value returned in A may not point to the last word transferred plus 1. PP Central Memory Access Instructions Central Write 62d Central write to (A) from d CWD d This instruction assembles five 12-bit words from consecutive PP memory locations into one 60-bit word and stores the 60-bit word in central memory. The first 12-bit word is stored in the leftmost 12 bits of the 60-bit word. (PP memory addressing is cyclic, and location 0000 follows location 7777.) The parameters of the transfer are a a follows: If bit 17 of A is 0, A bits 0 through 16 contain the absolute address of the 60-bit word stored. If bit 17 of A is 1, hardware adds relocation register R to zero-extended A bits 0 through 16 to obtain the absolute address of the 60-bit word stored. For further information, refer to R Register under Input/Output Unit in chapter 2, and PP Relocation Register Format under PP Instruction Descriptions. Field d gives the PP location of the first 12-bit word transferred. The transfer is subject to the CM bounds test. PP Central Memory Access Instructions Central write ( d l words to (A) from m CWM m,d Hardware uses PP location 0000. This instruction assembles 12-bit words from consecutive PP memory locations into 60-bit words and stores these in central memory. The first 12-bit word is stored in the leftmost 12 bits of the 60-bit word. (PP memory addressing is cyclic, and location 0000 follows location 7777.) The parameters of the transfer are as follows: If bit 17 of A is 0, A bits 0 through 16 contain the absolute address of the first 60-bit word transferred. If bit 17 of A is 1, hardware adds relocation register R to zero-extended A bits 0 through 16 to obtain the absolute address of the first 60-bit word transferred. For further information, refer to R Register under ~nput/~utput Unit in chapter 2 and in PP Relocation Register Format at the beginning of this section on PP Instruction Descriptions. PP location d must contain the number of 60-bit words transferred. Field m gives the PP location from where the first 12-bit word is obtained. The transfer is subject to the CM bounds test. This instruction stores P plus 1 into PP location 0000 before beginning the transfer. Gfter the transfer is completed, the next instruction is taken from 1 plus whatever address is stored in location 0000. +TheA register is incremented by 1 after each 60-bit word is written into central memory. If the incrementing changes A bit 17, the central memory addressing is switched between direct address and relocation address modes. Refer to Central Memory Addressing by PPs in chapter 5. After the transfer is completed, the A register contains either the address of the last word transferred plus 1 (direct addressing) or the same address less the contents of the relocation address register (relocation addressing), except as follows: If the last word transferred is from a relative address 3777768 and relocation is in effect, then the A register is cleared, and the value returned in A may not point to the last word transferred plus 1. PP lnput/Output Instructions PP Input/Output Instructions The PP input/output instructions (table 4 - 2 2 ) direct activity on the I/o channels. They select an external device and transfer data to or from that device. The instructions also determine whether a channel or external device is available and ready to transfer data. The preparatory steps ensure that the channels carry out an orderly data transfer. Each external device has a set of external function codes that the PP uses to establish operation modes, and to start and stop data transfer. The devices can also detect.certaid errors that are indicated to the controlling PP. Table 4 - 2 2 . Opcode PP Input/Output Instructions Format Instruction - Mnemonic - Test and set channel c flag Clear channel c flag Input to A from channel d Input A words to m from channel d Output from A on channel d Output (A) words from m on channel d Activate channel d Deactivate c h a ~ e ld Function A on channel d Function m on channel d SCF CCF IAN IAM OAN OAM ACN DCN FAN FNC m,&OB+c c d m,d d m,d d d d m,d PP InputlOutput Instructions 641cm Test and set channel c flag SCF m,c If the C h a ~ e lc flag is set, this instruction causes a jump to m. If the chamel c flag is clear, it sets this flag and continues with the next instruction. When m is set to P plus 2, the channel flag is unconditionalLy set when the program reaches P plus 2. If two or more PPs simultaneously issue this instruction for the same channel, the conflict is resolved as follows: If one of the competing channels i s channel 17 (maintenance channel), the PP in the lowest physical level sees the true condition of the flag; the other conflicting PPs see the flag set (and hence take a jump). If the competing chamel is any other channel, software must resolve the conflict. Any five consecutively numbered PPs (in the same barrel) issue instructions at different times. 651cm Clear channel c flag CCF m,c This instruction clears the channel c flag. The m field is required but is not used. PP InputlOutput Instructions Input to A from channel d IAN d This instruction transfers a word from input channel d to the lower 12 bits of the A register. The upper 6 bits of A are cleared to 0. NOTE If bit 5 of d is clear and the channel is inactive, this instruction hangs the PP, waiting for the channel to go active and full, if executed. If bit 5 of d is set and the channel is inactive or is deactivated before a full is received, the instruction exits. The word is not accepted, and the A register clears. Input A words to m from channel d IAM m,d This instruction transfers a block of 12-bit words from input channel d to PPM. The first word goes to the PPM address specified by m. The A register holds the block length. A reduces by 1 as each word is read. The input operation completes when A equals 0 or the data channel becomes inactive. If the operation terminates by the channel becoming inactive, the next storage location in PPM is set to 0. However, the word count is not affected by this empty word. Therefore, A holds the block length minus the number of real data words read. During this instruction, address 0000 temporarily holds P while m is held in the P register. P advances by 1 to hold the address for the next word as each word is stored. NOTE If this instruction executes when the data channel is inactive, no input operation is accomplished, and the program continues at P plus 2. However, the location specified by rn is set to 0. Output from A on channel d This instruction transfers a word from the A register (lower 12 bits) to output channel d. NOTE If bit 5 of d is clear and the channel i s inactive, this instruction hangs the PP, waiting for the channel to go active and full, if executed. If bit 5 of d is set and the channel is inactive, the program continues at P plus 1. The word is not transferred. 73dm Output A words from m on channel d OAM m,d This instruction transfers a block of words from PPM to channel d. The first word is read from the address specified by m. The A register holds the number of words to be sent. A reduces by 1 as each word is read. The output operation completes when A equals 0 or the channel becomes inactive. During this instruction, address 0000 temporarily holds P while m is held in the P register. P advances by 1 to give the address of the next word as each word is read from the PPM. NOTE If this instruction executes when the data channel is inactive, no output operation is accomplished, and the program continues at P plus 2. 74d Activate channel d This i n s t r u c t i o n a c t i v a t e s the channel s p e c i f i e d by d and sends the a c t i v e s i g n a l on the channel t o equipment connected t o the channel. Activating a channel, which must precede a 70 through 73 i n s t r u c t i o n , prepares 1 / 0 equipment f o r the exchange of data. NOTE I f t h i s i n s t r u c t i o n executes when the d a t a channel i s already a c t i v e and i f b i t 5 of d i s s e t , the program continues a t P plus 1. Otherwise, a c t i v a t i n g an already a c t i v e channel causes t h e PP t o wait u n t i l the channel goes inactive. The PP hangs i f t h e channel does not go i n a c t i v e . Deactivate channel d DCN This i n s t r u c t i o n d e a c t i v a t e s the channel s p e c i f i e d by d. d a t a t r a n s f e r stops. d As a r e s u l t , the 1 / 0 NOTES I f t h i s i n s t r u c t i o n executes when the d a t a channel i s already i n a c t i v e and b i t 5 of d i s s e t , the pr.ogram continues a t P p l u s 1. The channel remains i n a c t i v e , and no i n a c t i v e s i g n a l i s s e n t t o t h e 110 equipment. Deactiv a t i n g an already i n a c t i v e channel causes t h e PP t o hang u n t i l the channel becomes a c t i v e . If an output i n s t r u c t i o n i s followed by a disconnect i n s t r u c t i o n without f i r s t establ i s h i n g t h a t t h e i n p u t device (check f o r channel empty) has accepted t h e information, t h e Zast word transmitted may be l o s t . Do not d e a c t i v a t e a channel before p u t t i n g a u s e f u l program i n the a s s o c i a t e d PP. PPs other than 0 a r e hung on an i n p u t i n s t r u c t i o n (71) a f t e r d e a d s t a r t . Deactivating a channel a f t e r d e a d s t a r t causes an e x i t t o t h e address s p e c i f i e d by the content of l o c a t i o n 0000 p l u s 1 and execution of t h a t program. I f the chann e l i s deactivated without a v a l i d program i n t h a t PP, t h e PP executes whatever program was Left i n PPM. Therefore, t h e PP could run wild. Function 76d Function A on chamel d FAN d This instruction sends the external function code in the lower 12 bits of the A register on channel d. NOTE If this instruction executes with bit 5 of d clear and the channel active, PP execution stops until a deadstart or another PP causes the channel to become inactive. If bit 5 of d is set and the channel is active, the program continues at P plus 1. Neither the function signal nor the function word transmits. The channel remains active, and execution continues. Function m on channel d FNC m,d This instruction sends the external function code specified by m on channel d. NOTE If this instruction executes with bit 5 of d clear and the channel active, PP execution stops until a deadstart or another PP causes the channel to become inactive. If bit 5 of d is set and the channel is active, the program continues at P plus 2. Neither the function signal nor the function word transmits. The channel remains active, and execution continues. Other IOU Instructions Other IOU lnstructions Table 4-23 lists the other IOU instructions. Table 4-23. Opcode 00 27 260 261 262 Other IOU Instructions Format Instruction xx Pass Pass Exchange Jump Monitor exchange jump Monitor exchange jump to M d x x x Mnemonic ExN MXN MAN Pass OOxx Pass PSN This instruction specifies that no operation i s to be performed. instruction provides a means of padding out a program. 27d Pass The KPT d This instruction is not an operation. However, it generates a pulse to a testpoint (keypoint) for optional monitoring by external equipment. Other IOU Instructions Exchange Jump 2600 Exchange jump EXN This instruction causes an unconditional exchange jump in the CP, leaving the CP CYBER 170 monitor flag unaltered. The new CYBER 170 exchange package begins at central memory location R plus A when the leftmost bit in A is set. When this bit is clear, A specifies the address. The PP waits until the exchange is completed before proceeding with the next instruction. 2610 Monitor exchange jump MXN If the CP is in the CYBER 170 monitor mode, this instruction is a pass. If the CP is in the CYBER 170 job mode, it causes a CYBER 170 exchange jump in the CP, switching the CP to the CYBER 170 monitor mode (MF equals 1). The new CYBER 170 exchange package begins at central memory location R plus A when the leftmost bit in A is set. When this bit is clear, A specifies the address. The PP waits until the exchange is completed before proceeding with the next instruction. 2620 Monitor exchange jump to MA MAN If the CP is in CYBER 170 monitor mode, this instruction is a pass. If the CP is in CYBER 170 job mode, It causes a CYBER 170 exchange jump in the CP, switching the CP to CYBER 170 monitor mode (MF equals 1). The new CYBER 170 exchange package begins at the absolute address given in the MA field of the outgoing CYBER 170 exchange package. The PP waits until the exchange is completed before proceeding with the next instruction. Instruction Execution Timing Instruction Execution Timing Table 4-24 lists approximate execution times for the PP instructions. These times are listed with the assumption that no conflicts occur. The numbers in the timing notes column refer to the notes at the end of the table. Execution times are given in 250-11s major cycles. NOTE These execution times are approximations only and are subject to change without notice. Accurate timlngs can come only from benchmark tests. Control Data Corporation is not responsible for assumptions made based on the times listed here. Instruction Execution Timing Table 4-24. PP Instruction Timing Execution Time in 250-ns Cycles Timing Notes Instruction Code Description OOxx Pass Oldm Long jump to m 02dm Return jump to rn 03d Unconditional jump d 1 04d Zero jump d 1 - 05d Nonzero jump d 1 - 06d Plus jump d 1 - 07d Minus jump d 1 - 10d Shift d 1 - lld Logical difference d 1 - 12d Logical product d 1 - 13d Selective clear d 1 14d Load d 1 - 2 - 3 - 4 - 1 + 3 (d) f 4 (d) - Load complement d Add d Subtract d Load dm Add dm Logical product dm 23dm Logical difference dm 24d Load R register from (d) and (d) 25d Store R register at (dl and ( d l + 1 +1 (Continued) Instruction Execution Timing Table 4-24. PP Instruction Timing (Continued) - Instruction Code Execution Time in 2.50-ns Cycles Description Exchange jump Timing Notes , Monitor exchange jump Monitor exchange jump to MA Pass Load (dl. Add (d) Subtract (dl Logical difference (d) Store (dl Replace add (d) Replace add one (dl Replace subtract one ( d ) Load ((dl) Add ((dl) Subtract ((d)) Logical difference ((d)) Store ((dl) Replace add ( (dl ) Replace add one ((d)) Timing Notes: 1. No assembly-disassembly unit (ADU) conflicts and no outstanding CYBER 170 exchange jump request in the ADU. (Continued) Instruction Execution Timrng Table 4-24. PP Instruction Timing (Continued) Instruction Code Execution Time in 250-ns Cycles Description Timing Notes Replace subtract one ((dl) Load (m Add (m + (dl + (dl) Subtract (m + (d)) Logical difference(m Store (m + + (d)) (d)) + d)) one (m + Replace add (m Replace add (dl) Replace subtract one (m + (d)) Central read from (A) to d Central read (d) words from (A) to m Central write to (A) from d Central write (d) words to (A) from m Jump to m if channel c active Test and set channel c flag Jump to m if channel c inactive Clear channel c flag Jump to m if channel c full Timing Notes: 2. No ADU conflicts. No central memory conflicts. Add a possible trip due to resynchronization (CM read instructions only). 3, Seven major cycles for instruction set-up and instruction exit. for every CM word. 4. Six major cycles for instruction set-up and instruction exit. for every CM word. Five major cycles Five major cycles (Continued) 4-105 Instruction Execution Timing Table 4-24. PP Instruction Timing (Continued) Instruction Code Description Execution Time in 250-ns Cycles Timing Notes Jump to m if channel c error flag set Jump to m if channel c empty Jump to m if channel c error flag clear Input to A from channel d Input A words to m from channel d Output from A on c h a ~ e ld Output (A) words from m on channel d Activate channel d Deactivate channel d Function A on channel d Function m on channel d Timing Notes: 5. Five major cycles for instruction set-up and exit. One major cycle per word (nonconflict case) or two major cycles per word (conflict case). Nonconflict case occurs when two PPs communicating to each other are not in the slot at the same time. Conflict case occurs when two PPs communicating with each other are in the slot at the same time. Programming Information Programming Information This chapter contains special programming information about the CP, CM, PPs, system console, real-time clock, two-port multiplexer, and maintenance channel. CP Programming CYBER 170 Exchange Jump The CP operates in either CYBER 170 job mode, which is interruptable, or CYBER 170 monitor mode, which is not interruptable. A hardware flag called the CYBER 170 monitor flag (MF) indicates the mode in which the CP is executing a job. The CP uses a CYBER 170 exchange jump operation to switch from CYBER 170 job mode to CYBER 170 monitor mode and back again. The execution of a CYBER 170 exchange jump permits the CP to send pertinent information from the operating and control registers to CM and permits CM to send new information to the same registers. The information that flows from and into the operating and control registers during a CYBER 170 exchange jump is called a CYBER 170 exchange package (figure 5-1). The CP 013 instruction and the PP 2600, 2610, and 2620 instructions initiate a CYBER 170 exchange jump operation. A CYBER 170 exchange jump instruction starts or interrupts the CP and provides CM with the first address of a 16-word exchange package. For the 013 instruction with MF set (CP in monitor mode), the starting address of the CYBER 170 exchange package is Bj plus K. With MF clear (CP in job mode), the address is the monitor address (MA). For the 2600 instruction, the CYBER 170 exchange package address is A plus R when bit 17 of the A register is set. When this bit is clear, the address is A. For the 2610 instruction with MF set, the instruction is a pass. With MI? clear, the CYBER 170 exchange package address is A plus R when bit 17 of the A register is set. When this bit is clear, the address is A. For the 2620 instruction with MF set, the instruction is a pass. With MF clear, the CYBER 170 exchange package address is MA of the outgoing CYBER 170 exchange package. CP Programming N+ 3 EM N+4 ///A FLAGS RAC A1 B1 F LC A2 82 A3 83 A4 84 EM RAE FLE CM LOCATIONS VTA NO HARDWARE REGISTERS EXIST Figure 5-1. CYBW 170 Exchange Package CP Programming The CYBER 170 exchange package contains the following r e g i s t e r s which provide information f o r program execution. 18-bit program address ( P I r e g i s t e r , 21-bit reference address f o r CM (RAC) r e g i s t e r . 21-bit f i e l d l e n g t h f o r CM (E'LC) r e g i s t e r . 6-bit e x i t mode (EM) r e g i s t e r . 6-bit f l a g r e g i s t e r . 21- o r 24-bit r e f e r e n c e address f o r U W (RAE); 2 1 b i t s with Lower 6 b i t s assumed t o be 0 i n standard addressing mode; 24 b i t s r i g h t - s h i f t e d with 6 b i t s assumed t o be 0 ' s i n expanded addressing mode. 21- o r 24-bit f i e l d l e n g t h f o r UEM (FLE); 21 b i t s i n standard addressing mode and 24 b i t s i n expanded addressing mode; lower 6 b i t s a r e assumed t o be 0. 18-bit monitor address (MA) r e g i s t e r . I n i t i a l c o n t e n t s o f e i g h t 60-bit X r e g i s t e r s . I n i t i a l contents of e i g h t 18-bit A r e g i s t e r s . I n i t i a l c o n t e n t s of 18-bit B r e g i s t e r s B 1 through B7; BO contains a c o n s t a n t 0. The time t h a t a p a r t i c u l a r CYBER 170 exchange package r e s i d e s i n the CP hardware r e g i s t e r s i s t h e execution i n t e r v a l . The execution i n t e r v a l begins with a CYBER 170 exchange jump t h a t swaps t h e CYBER 170 exchange package information i n CM with the information contained i n t h e CP r e g i s t e r s . The execution i n t e r v a l ends with the next ClBW 170 exchange jump. CP Programming Executive State The executive s t a t e uses a combination of hardware, software, and microcode to handle t h e following items. System i n i t i a l i z a t i o n . Compare/move i n s t r u c t i o n s . Software e r r o r s and unimplemented i n s t r u c t i o n s t h a t occur i n CYBER 170 monitor mode. a Processor-detected hardware e r r o r s . a Hardware i n t e g r i t y v e r i f i c a t i o n ( d i a g n o s t i c s ) . I n g e n e r a l , executive s t a t e d e t e r m i n e s , t h e cause of an i n t e r r u p t and decides whether t o r e t u r n t h e CP t o the i n t e r r u p t e d mode, t o h a l t t h e CP, o r t o simulate a CYBER 170 exchange and r e t u r n c o n t r o l t o CYBER 170 monitor mode. Refer t o E r r o r Response i n t h i s chapter. Floating-point Arithmetic Format Floating-point a r i t h m e t i c expresses a number i n t h e form kBn. k = Coefficient B = Base number n Exponent o r power t o which t h e base number i s r a i s e d B i s assumed t o be 2 f o r binary-coded q u a n t i t i e s . I n t h e 60-bit, f l o a t i n g point format ( f i g u r e 5-21, the binary point i s considered t o be t o the r i g h t of t h e c o e f f i c i e n t . The lower 48 b i t s express the i n t e g e r c o e f f i c i e n t , which i s t h e equivalent of 15 decimal d i g i t s . The s i g n of t h e c o e f f i c i e n t i s separated from t h e r e s t of the c o e f f i c i e n t and appears i n t h e highest-order b i t of the packed word. Negative numbers a r e represented i n one's complement n o t a t i o n . The exponent i s biased by complementing the exponent s i g n b i t . CP Programming rI COEFFICIENT SIGN BINARY POINT ,,,AS INTEGER COEFFICIENT EXPONENT A I Figure 5-2. Floating-Point Format Table 5-1 summarizes the configurations of bits 58 and 59 and the implications regarding signs of the possible combinations. Bits 58 and 59 Configurations Table 5-1. Bit 59 Bit 58 Coefficient Sign Exponent Sign 0 1 Positive Positive 0 0 Positive Negative 1 0 Negative Positive 1 1 Negative Negative Packing Packing refers to the conversion of numbers in the form kBn to floating-point format. A shortcut method of packing exponents can be derived by considering the representation of -0 and +O exponents. Assuming a positive coefficient, 0 exponents are packed as follows: +O exponent: 2000x,...,x -0 exponent: 1777x,...,x Since positive exponents are expressed in true form, begin with a bias of 2000 (4)aid add the magnitude of the exponent. The range of positive exponents is 0000 through 1777. In packed form, the range is 2000 through 3777. When the coefficient is negative, the packed positive exponent is complemented to become 5777 through 4000. CP Programming Negative 1777 (-0) negative range i s exponents a r e expressed i n complement form by beginning with a b i a s of and then s u b t r a c t i n g the magnitude of the exponent. he range of exponents i s negative 0000 through negative 1777. I n packed form, the 1777 through 0000. When the c o e f f i c i e n t i s negative, t h e packed negative exponent i s complemented t o become 6000 through 7777. Examples of packed and unpacked floating-point numbers a r e shown i n o c t a l b a m p l e s ' l and 2 a r e d i f f e r e n t n o t a t i o n t o i l l u s t r a t e t h e packing process. forms of t h e i n t e g e r p o s i t i v e 1. Fxample 3 i s p o s i t i v e 100 (decimal), and example 4 i s negative 100 (decimal). Examples 5 and 6 a r e l a r g e and small p o s i t i v e numbers. The unpacked values a r e shown as they might appear i n t h e X and B r e g i s t e r s p r i o r t o a pack operation. The packed -0 exponent i s not used f o r normal operation. i n d i c a t e t h e s p e c i a l e r r o r c o n d i t i o n of i n d e f i n i t e . Unpacked c o e f f i c i e n t Unpacked exponent Packed format Unpacked c o e f f i c i e n t Unpacked exponent Packed format Unpacked c o e f f i c i e n t Unpacked exponent Packed format Unpacked c o e f f i c i e n t Unpacked exponent Packed format Unpacked c o e f f i c i e n t Unpacked exponent Packed format Unpacked c o e f f i c i e n t Unpacked exponent Packed format I n s t e a d , 1777 i s used CP Programming Overflow Overflow of t h e floating-point range i s i n d i c a t e d by an exponent value of p o s i t i v e 1777 (3777 o r 4000 i n packed form). This i s t h e l a r g e s t exponent value t h a t can be represented i n t h e f l o a t i n g - p o i n t format. This exponent v a l u e may r e s u l t from the calculation i n which t h i s exponent value, t o g e t h e r with t h e computed c o e f f i c i e n t v a l u e , i s a c o r r e c t r e p r e s e n t a t i o n of t h e r e s u l t . This s i t u a t i o n i s c a l l e d a p a r t i a l overflow. However, f u r t h e r computation using t h i s r e s u l t generates an overflow. A complete overflow occurs whenever a r e s u l t r e q u i r e s a n exponent l a r g e r t h a n p o s i t i v e 1777. I n t h i s case, a complete overflow value r e s u l t s . This r e s u l t has a p o s i t i v e 1777 exponent and a zero c o e f f i c i e n t . The s i g n of the c o e f f i c i e n t i s t h e same a s t h a t which generates i f t h e resu1.t had not overflowed t h e floating-point range. Underflow Underflow of t h e floating-point range i s i n d i c a t e d by an exponent value of negative 1777 (0000 o r 7777 i n packed form). This i s t h e s m a l l e s t exponent v a l u e t h a t can be represented i n t h e f l o a t i n g - p o i n t format. This exponent v a l u e may r e s u l t from t h e c a l c u l a t i o n i n which t h i s exponent v a l u e , t o g e t h e r with t h e computed c o e f f i c i e n t v a l u e , i s a c o r r e c t r e p r e s e n t a t i o n of t h e r e s u l t . This s i t u a t i o n is c a l l e d a p a r t i a l underflow. Further computation using t h i s r e s u l t may be detected a s an underflow. A complete underflow occurs whenever a r e s u l t r e q u i r e s an exponent smaller than negative 1777. I n t h i s c a s e , a complete underflow value r e s u l t s . This r e s u l t has a negative 1777 exponent and a zero c o e f f i c i e n t . The complete underflow i n d i c a t o r i s a word of a l l O ' s , and i t i s t h e same a s a zero word i n i n t e g e r format. Indefinite An i n d e f i n i t e r e s u l t i n d i c a t o r g e n e r a t e s whenever t h e c a l c u l a t i o n i s unresolvable. An example i s d i v i s i o n when the d i v i s o r i s 0 and the dividend is a l s o 0. Another example i s m u l t i p l i c a t i o n of an overflow number times an underflow number. The i n d e f i n i t e r e s u l t i n d i c a t o r i s a value t h a t cannot occur i n normal f l o a t i n g - p o i n t c a l c u l a t i o n s . This i n d i c a t o r corresponds t o a -0 exponent and a 0 c o e f f i c i e n t (177770, ,0 i n packed form). ... Any i n d e f i n i t e i n d i c a t o r used a s an operand generates an i n d e f i n i t e r e s u l t no matter what the other operand v a l u e is. Although i n d e f i n i t e i n d i c a t o r s always generate with a p o s i t i v e s i g n , they may occur a s operands with a n e g a t i v e s i g n . CP Programming Nonstandard Operands In summary, the special operand forms in octal are: Positive overflow (+ ) 3777x,...,x Negative overflow (- ) 4OOOx, ...,x Positive indefinite (+IND) 1777x,...,x Negative indefinite (-IND) 6OOOx, Positive underflow (+0) OOOOx,...,x Negative underflow (-0) 7777x,. ...,x ..,x Tables 5-2 through 5-5 indicate the resulting forms when various combinations of underflow, overflow, and indefinite forms are used in floating-point operations. The designations W and N are defined as follows: W Any word except + co and N Any word except + o, , + IND, and + Table 5-2. + IND 0 Xj Plus Xk (30, 32, 34 Instructions) IND IND IND CP Programming Table 5-3. Xj - Table 5-4. Xj Minus Xk (31, 33, 35 ~nstructions) 03 - rn -00 IND IND IND IND IND Xj Multiplied by Xk (40, 41, 42 Instructions) 0 0 O 0 Integer IND - co IND -ca +co IND IND IND IND IND IND IND +-" I / / Xj + 03 -03 IND IND + a - IND IND IND IND IND IND IND ?If both operands used in the integer multiply are normalized, an underflow results. CP Programming Table 5-5. Xj Divided by Xk (44, 45 Instructions) +O -o, 0 0 +cr, - a 0 0 IND -so +cr, 0 0 IND IND IND 0 0 IND IND IND I-= + a - -+INDIIND - +or IND - IND IND IND IND IND IND Normalized Numbers A normalized floating-point number has as large a coefficient and as small an exponent as possible. A floating-point number in packed format is normalized if the coefficient sign bit is different from bit 47. This condition indicates that the'coefficient has been left-shifted until bit 47 contains the mostsignificant bit in the coefficient; therefore, the floating-point number has no leading sign bits in the coefficient. The normalized instructions perform the coefficient shift. The floating-multiply and floating-divide instructions deliver normalized results when provided with normalized operands. The floating-add instructions may deliver unnormalized results even when both operands are normalized. Therefore, it is necessary to perform the normalize operation after each sequence of floating-add or floating-subtract operations if the result is to be kept in a normalized form. Rounding Floating-point instructions round the results in single-precision computation. These instructions execute in the same amount of time as the unrounded versions. The operands-are modified to accomplish the rounding function. The amount of bias introduced by the rounding operation varies and is affected by the coefficient value in the operands. The descriptions of the round instructions define the effects of rounding in detail. Double-Precision Results The floating-point arithmetic instructions generate double-precision results. Use of unrounded instructions allows separate recovery of upper- and lower-half results with proper exponents. Rounded instructions allow only upper-half results to be obtained. Two instructions, one single-precision and one double-precision, are required to retrieve an entire double-precision result. 60463560 A CP Programming To add or subtract two floating-point numbers, the coefficient with the smaller exponent enters the upper half of an accumulator and is right-shifted by the difference of the exponents. The other coefficient is then added into the upper half of the accumulator. The result is a double-length register (figure 5-3). BINARY POINT 1 ( UPPER HALF RESULT MOST SIGNIFICANT BlTS LOWER HALF RESULT LEAST SIGNIFICANT BlTS Figure 5-3. Floating-Add Result Format If single precision is selected, the upper 48 bits of the 96-bit result and the larger exponent are returned as the result. Selecting double precision causes only the lower 48 bits of the 96-bit result and the larger exponent minus 60 (octal) to be returned as the result. The subtraction of 60 (octal) is necessary because the binary point is effectively moved from the right of bit 48 to the right of bit 0. A 96-bit product generates from two 48-bit coefficients. The result of a multiply is a double-length register (figure 5-4). I BINARY POINT 1 LOWER HALF RESULT UPPER HALF RESULT MOST SIGNIFICANT BlTS LEAST SIGNIFICANT BITS Figure 5-4. Multiply Result Format If single precision is selected, the upper 48 bits of the product and the sum of the exponents plus 60 (octal) are returned as the result. The addition of 60 (octal) is necessary because the binary point effectively moves from the right of bit 0 to the right of bit 48 when the upper half of the 96-bit result is selected. If double precision is selected, the result is the lower 48 bits of the product and the sum of the exponents. CP Programming Fixed-Point Arithmetic Fixed-point a d d i t i o n and s u b t r a c t i o n of 60-bit numbers a r e handled by the long-add i n s t r u c t i o n s ( 3 6 and 37). Negative numbers a r e represented i n o n e ' s complement n o t a t i o n , and overflows a r e ignored. The s i g n b i t i s i n t h e high-order b i t p o s i t i o n ( b i t 59), and t h e binary p o i n t i s t o t h e r i g h t of t h e low-order b i t p o s i t i o n ( b i t 0 ) . The increment i n s t r u c t i o n s (50 through 77) handle fixed-point a d d i t i o n and s u b t r a c t i o n of 18-bit numbers. Negative numbers a r e represented i n one's complement n o t a t i o n , and overflows a r e ignored. The sign b i t is i n t h e high-order b i t p o s i t i o n ( b i t 1 7 ) , and t h e binary point i s t o t h e r i g h t of the low-order p o s i t i o n ( b i t 0 ) . I n t e g e r m u l t i p l i c a t i o n i s handled as a subset operation of t h e floating-multiply (42) i n s t r u c t i o n . The i n t e g e r m u l t i p l y r e q u i r e s ' t h a t both 47-bit i n t e g e r operands have zero exponents and a r e not normalized. The r e s u l t i s 48 b i t s with s i g n extension. Normalized operands cause underflow r e s u l t s to be reported. I f t h e r e s u l t s exceed 48 b i t s , overflow i s not d e t e c t e d . An i n t e g e r d i v i d e t a k e s s e v e r a l s t e p s . For example, an i n t e g e r q u o t i e n t X 1 equal t o ~ 2 / i~s 3produced by the following s t e p s . Instructions Remarks Pack X2 from X2 and BO Pack X2 Pack X3 from X3 and BO Pack X3 Normalize X3 i n XO and BO Normalize X3 ( d i v i s o r ) Normalize X2 i n X2 and BO Normalize X2 (dividend) F l o a t i n g q u o t i e n t of X2 and XO t o X i Divide Unpack X 1 t o X 1 and B7 Unpack q u o t i e n t S h i f t X 1 nominally l e f t B7 places Shift t o integer position The d i v i d e r e q u i r e s t h a t both i n t e g e r (247 maximum) operands must be i n floating-point format, and t h e dividend c o e f f i c i e n t must be l e s s than two times t h e d i v i s o r c o e f f i c i e n t . The normalize X3 i n s t r u c t i o n ensures t h i s condition. The normalize X3 i n s t r u c t i o n l e f t - s h i f t s the d i v i s o r n p l a c e s (n)O), providing a d i v i s o r exponent of negative n. The q u o t i e n t exponent i s then 0 minus (-n) minus 48 e q u a l s n minus 48<0. After unpacking and l e f t - s h i f t i n g nominally, t h e negative ( o r zero) value i n B7 r i g h t - s h i f t s the q u o t i e n t 48 minus n p l a c e s , producing an i n t e g e r quotient i n X 1 . A remainder may be obtained by an i n t e g e r multiply of X 1 and X 3 and s u b t r a c t i n g the r e s u l t from X2. CP Programming Integer Arithmetic I n t e g e r d i v i d e packs the i n t e g e r s i n t o floating-point i n s t r u c t i o n with a zero-exponent value. format, using t h e pack I n i n t e g e r m u l t i p l i c a t i o n , a 48-bit product can be formed by using t h e double-precision multiply i n s t r u c t i o n . Both operands must have an exponent The r e s u l t i s value of +0, and t h e c o e f f i c i e n t s cannot both be normalized. sign-extended t o 60 b i t s and s e n t t o an X r e g i s t e r . I n i n t e g e r d i v i s i o n , the d i v i s o r must be normalized, but t h e dividend does n o t have t o be normalized. The r e s u l t i n g q u o t i e n t must be unpacked and the c o e f f i c i e n t must be s h i f t e d by t h e amount of the unpacked exponent using the l e f t - s h i f t (22) i n s t r u c t i o n t o o b t a i n t h e i n t e g e r q u o t i e n t . Compare/Move Arithmetic The compare/move a r i t h m e t i c provides multiple-character manipulation. The c h a r a c t e r s a r e 6 b i t s long. Characters can be moved from one CM l o c a t i o n t o a n o t h e r , and f i e l d s of c h a r a c t e r s can be compared e i t h e r d i r e c t l y o r through a collate table. The moae d i r e c t i n s t r u c t i o n moves- a f i e l d of up t o 127 c h a r a c t e r s from one l o c a t i o n t o another l o c a t i o n as s p e c i f i e d i n t h e i n s t r u c t i o n . The move i n d i r e c t i n s t r u c t i o n performs t h e same kind of move, b u t a CM r e f e r e n c e i s used t o o b t a i n t h e parameters. The move i n d i r e c t i n s t r u c t i o n moves a f i e l d of up t o 8181 c h a r a c t e r s . The compare c o l l a t e d i n s t r u c t i o n compares two f i e l d s of up t o 127 c h a r a c t e r s . When two c h a r a c t e r s a r e unequal, t h e c h a r a c t e r s a r e referenced i n a c o l l a t e t a b l e , and t h e values a r e compared. I f those values a r e unequal, t h e f i e l d with t h e l a r g e r c h a r a c t e r i s i n d i c a t e d . The compare uncollated i n s t r u c t i o n compares two f i e l d s of up t o 127 c h a r a c t e r s and i n d i c a t e s the l a r g e r o f t h e f i r s t c h a r a c t e r p a i r t h a t i s found t o be unequal. CMU i n s t r u c t i o n s a r e provided f o r c o m p a t i b i l i t y with previous systems. b e t t e r performance, recompile jobs t o avoid use of CMU i n s t r u c t i o n s . For lnstruction Lookahead Purge Control Instruction Lookahead Purge Control Prefetching of i n s t r u c t i o n s a t a branch t a r g e t address by i n s t r u c t i o n lookahead hardware can l e a d t o program f a i l u r e s i f a program modifies i t s own code dynamically. Under normal c o n d i t i o n s , t h e lookahead r e g i s t e r s a r e purged by execution of a r e t u r n jump i n s t r u c t i o n (OlO), UEM read i n s t r u c t i o n (0111, exchange jump i n s t r u c t i o n (0131, o r unconditional branch i n s t r u c t i o n ( 0 2 ) . Selecting extended purge c o n t r o l extends these conditions. When extended purge c o n t r o l i s i n e f f e c t , lookahead r e g i s t e r s a r e a l s o purged by execution of any c o n d i t i o n a l jump i n s t r u c t i o n (03 through 07) o r any CM s t o r e i n s t r u c t i o n (50 through 57 when i equals 6 o r 7 ) . To enable extended purge c o n t r o l , t h e system s e t s b i t 52 of the f l a g r e g i s t e r i n the CYBER 170 exchange package. When self-modifying code is present, it may be h e l p f u l t o s e t extended purge c o n t r o l ; however, the a d d i t i o n a l purging causes a degradation i n execution and does not cover all cases of code modification. Purge Control I f normal purge conditions a r e i n e f f e c t , a s t o r e i n s t r u c t i o n t h a t modifies a s e q u e n t i a l i n s t r u c t i o n must modify a t l e a s t P p l u s 6 words ahead t o ensure execution of t h e modified code. I n a d d i t i o n , a s t o r e i n s t r u c t i o n followed by a branch t o a modified i n s t r u c t i o n executes t h e modified code only i f t h e r e a r e a t l e a s t 12 executed i n s t r u c t i o n s between t h e s t o r e and t h e modified code. I f the extended purge o p t i o n i s next s e q u e n t i a l i n s t r u c t i o n and i n s t r u c t i o n . Likewtse, a s t o r e i n s t r u c t i o n always executes t h e s e l e c t e d , a s t o r e i n s t r u c t i o n can modify t h e be assured of executing t h e modified i n s t r u c t i o n followed by a branch t o a m o d i f i e d , modified code. Error Response When the CP d e t e c t s o r i s informed of an e r r o r , it records the e r r o r . Depending on the type of e r r o r and t h e e x i t mode s e l e c t i o n b i t s s e t i n t h e EM r e g i s t e r , the program i n execution may be i n t e r r u p t e d . I f t h e e r r o r i s an i l l e g a l i n s t r u c t i o n o r an address-range e r r o r on an RNI o r branch, the program i n t e r r u p t i o n i s unconditional. For o t h e r types of e r r o r s , t h e e x i t mode s e l e c t i o n b i t s determine whether o r not t h e program i s i n t e r r u p t e d . I f t h e e x i t mode s e l e c t i o n b i t i s s e t and the corresponding c o n d i t i o n i s d e t e c t e d , the program i s i n t e r r u p t e d . The e x i t mode s e l e c t i o n b i t s a r e contained i n word N plus 3 of t h e exchange package. Figure 5-5 shows the format of t h e e x i t condition r e g i s t e r a t (RAC). Table 5-6 d e s c r i b e s t h e p o s s i b l e c o n t e n t s of the r e g i s t e r . Tables 5-7 and 5-8 l i s t CP e r r o r responses. The CP has the following e r r o r conditions: e r r o r s , and c o n d i t i o n a l software e r r o r s . i l l e g a l i n s t r u c t i o n s , hardware Instruction Lookahead Purge Control 59 CONTENT OF P REGISTER WHEN ERROR IS DETECTED -- EXIT CONDITION 54 53 48 47 P Figure 5-5. Table 5-6. Field 30 29 I 0 ERROR STATUS Format of Exit Condition Registe-r at (RAC) Contents of Exit Condition Register at (RAC) Description --- - -- -- ec 6-bit exit condition code: Code Condition 0°8 018 028 048 208 678 Illegal instruction. Address-range error (bit 48). Floating-point infinite (bit 49). Floating-point indefinite (bit 50). Processor-detected malfunction. Hardware malfunction. P When an error exit occurs, the content of the P register may not correspond to the address of the instruction that caused the error exit. The P register may have been incremented prior to the execution of the instruction. ERROR STATUS Nonzero information in bits 0 through 29 is error status for customer engineering and maintenance. Instruction Lookahead Purge Control Table 5-7. Error E x i t s i n CYBER 170 Monitor Mode (MF=l) Error Response Error Condition Exit Mode Selected - I l l e g a l i n s t r u c t i o n or 00 instruction. Exit c o n d i t i o n b i t 48 s e t by an incremental read w i t h an a d d r e s s out of range (AOR). Exit c o n d i t i o n h i t 48 s e t by m incrementcll m i t e with an 2 d d r e s s out of range (AOR). E x i t corirlition b i t 48 s z t by ~n R V I o r branch a d d r e s s o u t ~f rsnge. Exit Mode Not S e l e c t e d --- 1. The i n s t r u c t i o n i s not executed. 1. N / A ( e x i t mode i s always selected). 2. S t o r e P and e x i t c o n d i t i o n b i t s (00) a t l o c a t i o n RAC. P equals address of i l l e g a l i n s t r u c t i o n . 3. Interrupt t o executive State. 4. CP s t o p s i n executive s t a t e . 1.. The X r e g i s t e r is unchanged. 1. I n h i b i t r e a d , X unchanged 2. The A r e g i s t e r c o n t a i n s t h e AOR address. 2. Continue execution. 3. S t o r e P and e x i t c o n d i t i o n b i t s (01) a t l o c a t i o n RAC. P e q u a l s a d d r e s s of increment i n s t r u c t i o n o r a d d r e s s of i n s t r u c t i o n following t h e increment. 4. Interrupt to executive s t a t e . 5. CP s t o p s i n e x e c u t i v e s t a t e . 1. Block m i t e o p e r a t i o n ; c o n t e n t of CM i s unchanged. 1. I n h i b i t w r i t e , CM unchanged. 2. Continue execution. 2. The A r e g i s t e r c o n t a i n s t h e AOR address. 3. S t o r e P and e x i t c o n d i t i o n b i t s (01) a t l o c a t i o n RAG. P e q u a l s a d d r e s s of i n s t r u c t i o n o r a d d r e s s of i n s t r u c t i o n following t h e increment. 4. Interrupt t o executive s t a t e . 5. CP s t o p s i n executive s t a t e . 1. I n h i b i t execution. 2. S t o r e P and e x i t condZtion b i t s (01) a t l o c a t i o n RAC. P e q u a l s a d d r e s s of i n s t r u c t i o n r e q u i r e d by RNI o r address o f branch destination instruction. 3. Interrupt t o executive s t a t e . 4. CP s t o p s i n executive s t a t e . 1. N / A ( e x i t mode i s always s e l e c t e d r e g a r d l e s s of s t a t u s of EM r e g i s t e r b i t 4 8 ) . (Continued) Instruction Lookahead Purge Control Table 5-7. Error E x i t s i n CYBER 170 Monitor Mode (MP1) (Continued) Error Response Error Condition Exit Mode Selected Exit condition b i t 48 s e t on CMU i n s t r u c t i o n . 1. Detected by executive s t a t e during the execution of compare/move i n s t r u c t i o n . 1. Detected by executive s t a t e during t h e execution of compare/move instruction. 1. C 1 o r C2 g r e a t e r than 9. 2. 2. 2. K1 or K2 address out of range. Condition 1 omits r e a d i n g l v r i t i n g ; M i s unchanged. Condition 2 causes t h e i n s t r u c t i o n t o go unexecuted. Condition 1 omits r e a d i n g / w r i t i n g ; CM i s unchanged. Condition 2 causes the i n s t r u c t i o n t o go unexecuted. 3. Store P and e x i t b i t s (01) a t RAC. 3. Continue with next i n s t r u c t i o n . 4. CP s t o p s i n executive s t a t e . 1. Execute i n s t r u c t i o n a s a pass. 1. Execute i n s t r u c t i o n a s a pass. 2. Store P and e x i t b i t s (01) a t RAC. 2. Exit t o next 60-bit word and continue execution. 3. I n t e r r u p t t o executive s t a t e . 4. CP s t o p s i n executive s t a t e . 1. Execute i n e t r u c t i o n as a pass. 1. Execute i n s t r u c t i o n a s a pass. 2. Store P and e x i t condition b i t s (01) a t RAC. P e q u a l s address of following i n s t r u c t i o n . 2. Exit t o next parcel and continue execution. 3. I n t e r r u p t t o executive s t a t e . 4. CP s t o p s i n executive s t a t e . 1. Store P and e x i t condition b i t s (02 f o r i n f i n i t e o r 04 f o r i n d e f i n i t e ) . P equals address of a r i t h m e t i c i n s t r u c t i o n o r address of instruct i o n follouing. 1. Continue execution. 2. I n t e r r u p t t o executive s t a t e . 3. CP s t o p s i n executive s t a t e . 1. I n t e r r u p t t o executive s t a t e . 1. I n t e r r u p t t o executive s t a t e . 2. Executive s t a t e s t o r e s P and e x i t condition b i t s (20) a t RAC. 2. Executive s t a t e s t o r e s P and e x i t condition b i t s (20) a t RAC. 3. CP s t o p s i n executive s t a t e . 3. CP s t o p s i n executive s t a t e . Exit condition b i t 48 s e t by a UEH address range check f o r i n s t r u c t i o n s 011 and 012. Exit condition b i t 48 s e t by a UEM address range check f o r i n s t r u c t i o n s 014 and 015. Exit condition b i t 49 s e t by i n f i n i t e condition, or b i t 50 set by i n d e f i n i t e condition. Any hardware p a r i t y e r r o r or double SECDED e r r o r . Exit Mode Not Selected . Instruction Lookahead Purge Control Table 5-8. Error Exits in CYBER 170 Job Mode (MF=O) Error Response Error Condition Exit Mode Selected Exit Mode Not Selected Illegal instruction or 00 instruction. 1. The instruction is not executed. 1. N/A (exit mode is always selected). 2. Store P and exit condition bits (00) at location RAC. P equals address of illegal instruction. 3. Exit condition bit 48 set by an incremental. read with an address out of range (AOR). Exit condition bit 48 set by an incremental write with an address out of range (AOR). Exchange jump to MA and set CYBER 170 MF. 1. The X register is unchanged. 1. Inhibit read, X unchanged. 2. The A register contains the AOR address. 2. 3. Store P and exit condition bits (01) at location RAC. P equals address of increment instruction or address of instruction following the increment. 4. Exchange jump to MA and set CYBER 170 MF. 1. Block write operation; content of CM is unchanged. 2. The A register contains the AOR address. Continue execution. 1. Inhibit write, CM unchanged. 2. Continue execution. 1. N/A (exit mode is always selected regardless of status of EM register bit 4 8 ) . 3. Store P and exit condition bits (01) at location RAC. P equals address of instruction or address of instruction following the increment. Exit condition bit 48 set by an RNI or branch address out of range. 4. Exchange jump to MA and set CYBER 170 MF.. 1. Inhibit execution. 2. Store P and exit condition bits (01) at location RAC. P equals address of instruction required by RNI or address of branch destination instruction. 3. Exchange jump to CYBER 170 MF. and set (Continued) Instruction Lookahead Purge Control Table 5-8. Error E x i t s in CYBER 170 Job Mode (MF'O) (Continued) Error Response . . . . . Error Condition Exit Mode Selected E x i t Mode Not Selected Exit c o n d i t i o n b i t 48 s e t on CMU i n s t r u c t i o n . 1. Detected by executive s t a t e during the execution of compare/move instruction. 1. Detected by executive s t a t e d u r i n g t h e execution of compare/move i n s t r u c t i o n . 2. Condition 1 omits r e a d i n g / w r i t i n g ; CN i s unchanged. Conditon 2 causes t h e i n s t r u c t i o n t o go unexecuted. 2. Condition 1 omits reading/ w r i t i n g ; CM i s unchanged. Condition 2 causes t h e i n s t r u c t i o n t o go unexecuted. 3. S t o r e P and e x i t b i t s (01) a t RAC. 3. Continue with next i n s t r u c t i o n 4. Exchange jump t o MA and s e t CYBER 170 HF. 1. Execute i n s t r u c t i o n a s a pass. S t o r e P and e x i t b i t s (01) a t RAC. continue execution. Exchange jump t o MA and s e t CYBER 170 MF. 2. Exit t o next 60-bit word and 1. Execute i n s t r u c t i o n a s a pass. 1. Execute i n s t r u c t i o n a s a pass. 2. Stop CP. 2. hit t o next parcel and continue execution. 1. Continue execution. 1. C1 o r C2 g r e a t e r t h a n 9 . 2. K1 o r K2 address out of range. I Exit c o n d i t i o n b i t 48 s e t by a UEM a d d r e s s range check for i n s t r u c t i o n s 011 and 012. 1. Execute i n s t r u c t i o n a s a pass. 2. 3. Exit c o n d i t i o n b i t 48 see by a UEM a d d r e s s range check f o r i n s t r u c t i o n s 014 and 015. S t o r e P and e x i t c o n d i t i o n b i t s (01) a t l o c a t i o n RAC. Exchange jump t o MA and s e t CYBER 170 MF. Exit c o n d i t i o n b i t 49 s e t by i n f i n i t e condition, or b i t 50 s e t by i n d e f i n i t e condition. Any hardware p a r i t y e r r o r o r double SECDED e r r o r . 1. S t o r e P and e x i t c o n d i t i o n b i t s (02 f o r i n f i n i t e o r 04 f o r i n d e f i n i t e ) . P equals address of arithmetic instruction or address of i n s t r u c t i o n following. 2. Exchange jump t o MA and s e t CYBER 170 MF. 1. I n t e r r u p t t o executive s t a t e . 1. I n t e r r u p t t o executive s t a t e . . 2. Executive s t a t e s t o r e s P and e x i t c o n d i t i o n b i t s (20) a t RAC. 2. Executive s t a t e s t o r e s P and e x i t c o n d i t i o n b i t s (20) a t RAC 3. Exchange jump t o MA and s e t CYBER 170 MF. . 3, Exchange jump t o MA and set CYBER 170 MF. Instruction Lookahead Purge Control Illegal Instructions An instruction is illegal when it has an illegal operating code, an illegal operating parameter, or when it is positioned so that it begins in one instruction word and extends into the next instruction word. In the CYBER 170 job mode, illegal instructions cause an exchange to the CYBER 170 monitor mode. In the CYBER 170 monitor mode, illegal instructions cause a jump to executive state. The CP stops. CP illegal instructions are: 011, 012, 013, 464, 465, 466, 467 if they do not begin at parcel 0. 011, 012, 014, 015 if the UEM enable flag in the flag register of the CYBER 170 exchange package is clear. Any 30-bit instruction that begins at parcel 3. Instruction Lookahead Purge Control Hardware Errors CP/CM hardware e r r o r s a r e : d a t a p a r i t y e r r o r s , a d d r e s s p a r i t y errors, and double-bit e r r o r s . If t h e CP i s i n CYBER 170 job mode, a hardware e r r o r c a u s e s a jump t o e x e c u t i v e s t a t e , which r e t u r n s t o CYBER 170 monitor mode. If t h e CP i s i n CYBER 170 monitor mode, a hardware e r r o r causes a jump t o e x e c u t i v e s t a t e . The CP h a l t s . The i n s t r u c t i o n being executed when such a f a u l t i s d e t e c t e d i s n o t n e c e s s a r i l y connected with t h e f a u l t . Conditional Software Errors C o n d i t i o n a l software e r r o r s a r e caused by address-range e r r o r s and f l o a t i n g p o i n t i n f i n i t e l i n d e f i n i t e operands o r r e s u l t s . A c o n d i t i o n a l software e r r o r causes a c t i o n , depending on b i t s s e t i n t h e EM f i e l d i n t h e c u r r e n t CYBER 170 exchange package. If t h e b i t reserved f o r use with t h e s p e c i f i c type of e r r o r i s c l e a r , t h e e r r o r i s ignored i n both CYBER 170 job and CYBER 170 monitor modes. If t h e b i t i s s e t and t h e e r r o r occurs i n t h e CYBER 170 job mode, i t causes an exchange t o t h e CYBER 170 monitor mode. I f t h e b i t i s s e t and t h e e r r o r occurs i n t h e CYBER 170 monitor mode, i t c a u s e s an i n t e r r u p t t o e x e c u t i v e s t a t e . Memory Programming Memory Programming A l l r e f e r e n c e s t o CM by t h e CP f o r i n s t r u c t i o n s o r r e a d / w r i t e d a t a a r e made r e l a t i v e t o RAC. The RAC d e f i n e s t h e lower l i m i t of the a d d r e s s e s of a program The upper l i m i t of t h e program a d d r e s s e s i s d e f i n e d by FLC added t o RAC. i n CM. A l l r e f e r e n c e s t o UEM by t h e CP f o r i n s t r u c t i o n s o r r e a d / w r i t e d a t a a r e made r e l a t i v e t o RAE. The RAE d e f i n e s t h e lower l i m i t of t h e a d d r e s s e s of a program/data i n UEM. The upper l i m i t of t h e a d d r e s s e s i s d e f i n e d by FLE added t o RAE. The f i e l d l e n g t h i s a number of 60-bit words e s t a b l i s h e d by t h e o p e r a t i n g system p r i o r t o program e x e c u t i o n . A l l r e f e r e n c e s t o CM o r UEM f o r a programldata must be w i t h i n t h e f i e l d e s t a b l i s h e d f o r t h a t program. h r i n g a CYBER 170 exchange jump, RAC and FLC a r e loaded i n t o r e s p e c t i v e r e g i s t e r s t o d e f i n e t h e CM l i m i t s of t h e program t h a t i s i n i t i a t e d by t h e CYBER 170 exchange jump. RAE and FLE a r e loaded t o d e f i n e t h e UEM l i m i t s of a program. Figure 5-6 shows t h e a b s o l u t e and r e l a t i v e memory a d d r e s s e s , RAC, FLC, RAE, and FLE r e g i s t e r r e l a t i o n s h i p s . For a program t o o p e r a t e w i t h i n t h e e s t a b l i s h e d l i m i t s , t h e f o l l o w i n g c o n d i t i o n s must e x i s t . For a b s o l u t e memory a d d r e s s e s : RAC -< (RAC + P) < (RAC + FLC) For r e l a t i v e memory a d d r e s s e s : 0 -< P < FLC Memory Programming CENTRAL JlEMORY YBER 17a MNITOR BSOLUT iDDRES5 JOB A --- 1 RAC+O I PROGRAM'S CENTRAL MEMORY ccy JOB B IAC+F LC ZzZ JOB C RAE+O m I I JOB'S PORTION OF UEM IAEtFLE EXECUTIVE STATE I I PROGRAM'S UEM I I I I I Memory Programming Addressing Modes UEM can be used i n e i t h e r of two a d d r e s s i n g modes: standard or Standard a d d r e s s i n g mode provides a d d r e s s i n g up t o 2 1 b i t s i n a Expanded a d d r e s s i n g mode provides a d d r e s s i n g up t o 24 b i t s i n a Addressing mode i s determined by t h e expanded a d d r e s s i n g s e l e c t word 3 , i n t h e CYBER 170 exchange package. expanded. 24-bit f o r m a t . 30-bit format. f l a g , b i t 55 of Direct Read/Write lnstructions (014,015,660,670) These i n s t r u c t i o n s t r a n s f e r one 60-bit word between t h e s e l e c t e d X r e g i s t e r and a memory l o c a t i o n , u s i n g a 21-bit r e l a t i v e a d d r e s s . I n s t r u c t i o n s 660 and 670 use t h e memory a d d r e s s Xk ( 2 1 b i t s ) p l u s RAC ( 2 1 b i t s ) t o a d d r e s s CM. I n s t r u c t i o n s 014 and 015 u s e t h e memory a d d r e s s Xk ( 2 1 b i t s ) p l u s RAE ( 2 1 b i t s ) t o a d d r e s s UEM. Block Copy lnstructions (011,012) These i n s t r u c t i o n s t r a n s f e r up t o 1 3 1 071 60-bit words between f i e l d s i n CM and The UEM a d d r e s s i s XO p l u s RAE ( b i t s 0 through 22 i n s t a n d a r d a d d r e s s i n g mode; b i t s 0 through 28 i n expanded a d d r e s s i n g mode). The CM a d d r e s s i s A0 p l u s RAC ( i f t h e block copy f l a g i s c l e a r i n t h e CYBER 170 exchange package) o r XO ( b i t s 30 through 50) p l u s RAC ( i f t h e block copy f l a g i s s e t ) . UEM. The t r a n s f e r s occur i n blocks of up t o 64 words, d u r i n g which o t h e r CP a c t i v i t i e s a r e suspended. These i n s t r u c t i o n s a r e 30-bit i n s t r u c t i o n s t h a t must s t a r t a t p a r c e l 0. I f t h e UEM a d d r e s s h a s b i t 21 o r b i t 22 s e t i n s t a n d a r d a d d r e s s i n g mode ( b i t 28 i f i n expanded a d d r e s s i n g mode), 0 ' s a r e t r a n s f e r r e d t o CM and t h e n e x t i n s t r u c t i o n i s t a k e n from p a r c e l 2 of t h e same i n s t r u c t i o n word. If t h i s i s n o t t h e c a s e on a block r e a d , t h e n e x t i n s t r u c t i o n i s t a k e n from p a r c e l 0 of t h e next i n s t r u c t i o n word. A t r a n s f e r of a l l 0 ' s can be made t o c e n t r a l memory u s i n g t h e 011 i n s t r u c t i o n and s e t t i n g b i t 2 1 o r 22 ( o r b i t 28) of t h e a d d r e s s (XO + RAE) when FLE i s s u f f i c i e n t l y l a r g e . PP Programming PP Programming One 64-bit word o r a block of The PPs have a c c e s s t o a l l CM s t o r a g e l o c a t i o n s . 64-bit words can be t r a n s f e r r e d from a p e r i p h e r a l processor memory (PPM) t o CM (Five 12-bit PP words e q u a l one 64-bit CM word, with t h e o r from CM t o PPM. l e f t m o s t 4 b i t s undefined.) Data from e x t e r n a l d e v i c e s i s read i n t o a PPM, and with a d d i t i o n a l i n s t r u c t i o n s , i s t r a n s f e r r e d t o CM. Conversely, d a t a i s t r a n s f e r r e d from CM t o a PPM and is then t r a n s f e r r e d by a d d i t i o n a l i n s t r u c t i o n s t o e x t e r n a l devices. Addresses s e n t t o CM from PPs a r e a b s o l u t e o r r e l o c a t i o n addresses. Central Memory Addressing by PPs PPs a d d r e s s c e n t r a l memory using e i t h e r a b s o l u t e o r r e l o c a t i o n a d d r e s s i n g . Every PP can read a l l c e n t r a l memory l o c a t i o n s without r e s t r i c t i o n . Every PP has w r i t e a c c e s s t o c e n t r a l memory. The bounds r e g i s t e r i n c e n t r a l memory nay a l s o be s e t t o l i m i t w r i t e a c c e s s from t h e I O U . I n s t r u c t i o n s 24/25 l o a d / s t o r e t h e r e l o c a t i o n (R) r e g i s t e r . I f b i t 17 of t h e A r e g i s t e r i s 0, b i t s 0 through 1 6 of A s p e c i f y an a b s o l u t e c e n t r a l memory a d d r e s s 0 through 377 777 I f b i t 17 of A i s 1, b i t s 0 through 16 of A a r e added t o t h e 28-bit R r e g a s t e r t o s p e c i f y an a b s o l u t e c e n t r a l memory a d d r e s s 0 through 0 007 777 7778. I f b i t 17 of A changes d u r i n g a t r a n s f e r , t h e a d d r e s s i n g mode a l s o changes accordingly. The l e f t m o s t 7 b i t s of R r e p r e s e n t unused e x t r a addressing c a p a c i t y . The rightmost 6 b i t s of R a r e appended 0 ' s . I n s t r u c t i o n 24 l o a d s R from two consecutive PP memory l o c a t i o n s . I n s t r u c t i o n 25 s t o r e s R i n t o two PP memory l o c a t i o n s . Figure 4-4 shows how R i s s t o r e d i n PP memory. . PP Memory Addressing by PPs PP i n s t r u c t i o n s use 6-bit o r 18-bit d i r e c t operands o r a c c e s s PP memory through d i r e c t , i n d i r e c t , o r indexed a d d r e s s i n g . Direct 6-Bit Operand PP i n s t r u c t i o n s i n t h i s category a r e no-address i n s t r u c t i o n s . They have t h e format OPCODEd. The d f i e l d i s used a s a 6-bit d i r e c t operand, zero-extended t o 18 b i t s i n c a l c u l a t i o n s . Direct 18-Bit Operand PP i n s t r u c t i o n s i n t h i s category a r e c o n s t a n t a d d r e s s i n s t r u c t i o n s . They have t h e format OPCODEdm. The combined d and m f i e l d s a r e used a s an 18-bit operand. PP Programming Direct 6-Bit Address PP i n s t r u c t i o n s i n t h i s category a r e d i r e c t - a d d r e s s i n s t r u c t i o n s . They have t h e format OPCODEd. The d f i e l d i s used as a 6-bit d i r e c t a d d r e s s , a c c e s s i n g PP memory l o c a t i o n s 0 t o 778. Direct 12-Bit Address PP i n s t r u c t i o n s i n t h i s category a r e indexed d i r e c t - a d d r e s s i n s t r u c t i o n s with zero index. They have t h e format OPCODEdm where d e q u a l s 0. The m f i e l d is used a s a 12-bit d i r e c t address t h a t a c c e s s e s PP memory l o c a t i o n s 0 through 77778. Indexed 12-Bit Address PP i n s t r u c t i o n s I n t h i s category a r e indexed d i r e c t - a d d r e s s i n s t r u c t i o n s . They have t h e format OPCODEdm where d e q u a l s 0. The m f i e l d i s used a s a 12-bit d i r e c t a d d r e s s (base a d d r e s s ) . The d f i e l d s p e c i f i e s a PP memory l o c a t i o n from 1 t o 77 , the c o n t e n t s of which i s a 12-bit one's complement number index. The indgxed d i r e c t a d d r e s s is formed by adding t h e index t o t h e base a d d r e s s a s signed one's complement numbers. Overflow i s ignored. When m p l u s ( d ) e q u a l s 7777, t h e r e s u l t i s s e t t o 0000, except as follows: adding 7777 p l u s 7777 e q u a l s 7777. I n g e n e r a l , adding 0000 o r 7777 l e a v e s t h e o t h e r number unchanged, except when t h e o t h e r number i s a l s o 0000 o r 7777. Indirect 6-Bit Address PP i n s t r u c t i o n s i n t h i s category a r e i n d i r e c t - a d d r e s s i n s t r u c t i o n s . They have t h e format OPCODEd. The 6-bit d f i e l d i s used t o read a 12-bit number from PP l o c a t i o n s 0 through 77 This number i s used a s a 12-bit a d d r e s s t o a c c e s s PP memory l o c a t i o n s 0 fhrough 77778. . PP Programming Central Memory Read/Write lnstructions PP instructions can read and write to central memory either single words or blocks of words. PP Central Memory Read lnstructions (60, 61) - Instruction 60 transfers one CM word into five 12-bit PP memory words. Instruction 61 transfers a block of 1 through 811 CM words into 5 through 4095 12-bit PP words. It is possible to transfer up to 4096 CM words overwriting PP memory cyclically; location 0, however, has special properties. The Central Read description in chapter 4 has more information on instruction 61. PP Central Memory Write lnstructions (62, 63) Instruction 62 transfers five 12-bit PP memory words into 1 CM word. Instruction 63 transfers 5 through 4095 PP memory words into 1 through 811 CM words. It is possible to transfer up to 20 480 PP memory words, repeating information from PP memory cyclically. PP Programming Input/Output Channel Communications Data t r a n s f e r s t o and from e x t e r n a l d e v i c e s a r e c o n t r o l l e d by PP i n s t r u c t i o n s 64 through 77. The assignment of PPs, t r a n s f e r p r i o r i t i e s , and r e s o l u t i o n of c o n f l i c t s a r e software r e s p o n s i b i l i t i e s . Channel p a r i t y and r e s e r v a t i o n must be provided f o r , using t h e channel marker f l a g a n d l o r software i n t e r l o c k s i n c e n t r a l memory. A f t e r any c o n f l i c t s have been r e s o l v e d , proceed a s fbllows: Action Typical I n s t r u c t i o n 1. Clear t h e e r r o r f l a g . Jump i f t h e e r r o r f l a g i s s e t , and c l e a r t h e f l a g (661). 2. Verify i n a c t i v e s t a t u s . Jump i f a c t i v e (640). 3. Verify read s t a t u s : Prepare f o r reading t h e summary s t a t u s . Function m (771. Verify t h a t t h e device responded. Jump i f a c t i v e ( 6 4 0 ) . A c t i v a t e t h e channel. Activate (74). Read t h e summary s t a t u s . Input t o A ( 7 0 ) . Verify t h e e r r o r f l a g i s c l e a r . Jump i f t h e e r r o r f l a g i s s e t (661). Analyze t h e summary s t a t u s . Logical product ( 1 2 ) . (04). 4. Enter t h e number of words t o A. Load d ( 1 4 ) . 5. Prepare f o r i n p u t l o u t p u t : Verify i n a c t i v e s t a t u s . Jump i f a c t i v e (640). Prepare f o r r e a d / w r i t e . Function m ( 7 7 ) . Verify t h a t t h e device responded. Jump i f a c t i v e (640). Zero jump PP Programming Act i o n 6. 7. Typical I n s t r u c t i o n Read/write d a t a : A c t i v a t e t h e channel. Activate (74). R e a d h r i t e data. ~ n p u t / o u t p u tA words ( 7 1 / 7 3 ) . I f w r i t e , loop u n t i l empty. Jump i f f u l l (660). Disconnect t h e channel. Deactivate ( 7 5 ) . Verify i n a c t i v e s t a t u s . Jump i f a c t i v e (640). Verify t r a n s f e r i n t e g r i t y : Verify A words were t r a n s f e r r e d ( r e f e r t o note). Nonzero jump (05). Verify t h e e r r o r f l a g i s c l e a r . Jump i f e r r o r f l a g s e t ( 6 6 1 ) . Verify i n a c t i v e s t a t u s . Jump i f a c t i v e (640). Prepare f o r reading device s t a t u s . Function m ( 7 7 ) . V e r i f y t h a t t h e device responded. Jump i f a c t i v e ( 6 4 0 ) . A c t i v a t e t h e channel. A c t i v a t e (74). Read t h e device s t a t u s . Input t o A ( 7 0 ) . Verify t h e e r r o r f l a g i s c l e a r . Jump i f e r r o r f l a g s e t (661). Analyze device s t a t u s . Logical product (12). jump (051. Disconnect t h e channel. Deactivate ( 7 5 ) . NOTES I f A e q u a l s t h e o r i g i n a l v a l u e , no words were transferred. I f A i s n o t e q u a l t o 0 , t h e device o r a n o t h e r PP ended t h e t r a n s f e r . Nonzero PP Programming Inter-PP Communications Any PP can communicate with any other PP using any channel (except the real-time clock) by omitting the conditioning of the external devices of that channel for a data transfer. Both single-word and block transfers can be used. Either the sending or the receiving PP can activate the channel used, after which the sending PP outputs data into the.channel register of the channel concerned and the receiving PP inputs data from the same register. The transfer rate is 1 word every 250 us, except when the transfer is between PPs in different barrels but in the same time slot. In such a case, the transfer rate is 1 word every 500 ns. PPs that use the same time slots are as follows: Slot PP Number 1 2 0, 1, 2, 3, 3 4 5 5, 20, 25 6, 21, 26 7, 22, 27 10, 23, 30 4, ll, 24, 31 Software resolves priority and reservation problems arising in inter-PP communications by interlocks stored in CM or by other means. PP Program Timing Considerations Some external equipment may require timing considerations in issuing function, activate, and input instructions. Refer to the applicable external equipment reference manual. Such timing considerations may, for example, be required to ensure that the equipment attains a proper speed before data is sent (required by some magnetic tape equipment). Also, equipment that terminates a data transfer by resetting the active flag to inactive often requires timing considerations in issuing the next function instruction. Channel Operation Channel Control Flags Channel operation is affected by the channel active/inactive and full/empty flags and, depending on the status of these two flags, the channel is said to be active, inactive, full, or empty. Each channel also has a marker flag for software use and an error flag for indicating transmission parity errors. PP Programming Channel Active/lnactive Flag A channel i s normally a c t i v a t e d by a f u n c t i o n ( 7 6 o r 7 7 ) i n s t r u c t i o n o r by a n a c t i v a t e channel ( 7 4 ) i n s t r u c t i o n . An e x t e r n a l device can a l s o a c t i v a t e the channel. . A f u n c t i o n i n s t r u c t i o n conditions t h e external. device f o r a coming d a t a o r s t a t u s information t r a n s f e r . The i n s t r u c t i o n p l a c e s a 12-bit function word plus p a r i t y i n the channel r e g i s t e r and s e t s t h e a c t i v e and f u l l f l a g s . The f u n c t i o n word and a f u n c t i o n s i g n a l a r e s e n t t o t h e e x t e r n a l device. No a c t i v e o r f u l l s i g n a l s a r e s e n t during a f u n c t i o n i n s t r u c t i o n . The e x t e r n a l device a c c e p t s t h e f u n c t i o n word and sends an i n a c t i v e s i g n a l , which c l e a r s t h e channel a c t i v e and f u l l f l a g s , c l e a r i n g the channel r e g i s t e r . An a c t i v a t e channel i n s t r u c t i o n prepares a channel f o r d a t a t r a n s f e r and sends an a c t i v e s i g n a l t o the e x t e r n a l device. Subsequent i n p u t o r output i n s t r u c t i o n s t r a n s f e r data. A disconnect channel (75) i n s t r u c t i o n a f t e r a d a t a t r a n s f e r r e t u r n s t h e channel t o an i n a c t i v e s t a t e , and an i n a c t i v e s i g n a l i s s e n t t o the e x t e r n a l device. Register FulVEmpty Flag A r e g i s t e r i s f u l l when it contains a f u n c t i o n o r d a t a word f o r an e x t e r n a l device o r c o n t a i n s a ward received from t h e e x t e r n a l device. The r e g i s t e r i s empty when t h e f l a g c l e a r s . The f l a g i s turned on o r o f f a s t h e r e g i s t e r changes s t a t e . A channel can only be f u l l when i t i s a c t i v e . , On d a t a o u t p u t , t h e processor places a word i n t h e channel r e g i s t e r ( t h e channel should be a c t i v e and empty) and s e t s a f u l l f l a g . The d a t a word plus p a r i t y and a £ 3 1 s i g n a l a r e s e n t t o t h e e x t e r n a l device. The e x t e r n a l device a c c e p t s the word and sends an empty s i g n a l t o t h e channel, which c l e a r s t h e f u l l f l a g , c l e a r i n g the channel r e g i s t e r . The a c t i v e and empty s t a t u s of the channel s i g n a l s the PP t o send t h e next word t o t h e r e g i s t e r . On d a t a i n p u t , the e x t e r n a l device sends a word and a f u l l s i g n a l t o the d a t a channel. The word i s placed i n t h e channel r e g i s t e r , and the f u l l f l a g s e t s . The PP s t o r e s the word and c l e a r s t h e f u l l f l a g , c l e a r i n g t h e d a t a r e g i s t e r . An empty s i g n a l i s s e n t t o t h e e x t e r n a l device, s i g n a l i n g i t t o send t h e next d a t a word. PP Programming Channel (Marker) Flag lnstructions (641, 651) . Software uses t h i s f l a g software a s a marker. This f l a g does not a f f e c t hardware operation. When PPs i n t h e same time s l o t use t h i s f l a g , p r i o r i t y c o n f l i c t s e x i s t . For channel (maintenance channel) marker f l a g , hardware r e s o l v e s p r i o r i t y problems. For o t h e r channels, software must r e s o l v e such c o n f l i c t s . Any f i v e consecutively numbered PPs a r e not i n t h e same time s l o t . Error Flag lnstructions (661, 671) This f l a g i n d i c a t e s an i n p u t d a t a p a r i t y e r r o r on t h e s p e c i f i c channel being t e s t e d . The f l a g a l s o i n d i c a t e s an output d a t a p a r i t y e r r o r on channels t h a t have t h e c a p a b i l i t y of sending an e r r o r s i g n a l t o t h e I O U i n c a s e o f such an e r r o r . The s t a t u s r e g i s t e r of t h e device concerned must be read t o v e r i f y output d a t a i n t e g r i t y . Channel Transfer Timing Figure 5-7 shows channel t r a n s f e r timing. A l l s i g n a l p u l s e s a r e 25 +5 n s i n width and occur 25 2 5 n s following t h e 10-MHz clock. To maintain t h e f a s t e s t p o s s i b l e c y c l e time (500 u s ) , a f u n c t i o n / f u l l / e m p t y pulse from t h e PP must be answered w i t h a n i n a c t i v e / e m p t y / f u l l p u l s e , r e s p e c t i v e l y , w i t h i n 310 235 ns. I f t h e maximum speed i s n o t r e q u i r e d , t h i s response time may be increased by m u l t i p l e s of 100 ns. The PP master clock frequency can be v a r i e d by 2 2 percent. devices used must t o l e r a t e t h i s ' frequency v a r i a t i o n . The p e r i p h e r a l PP Programming 10 MHz CLOCK TRANSMITTED ON CHANNEL ,- -d MASTER CLEAR TRANSMITTED ON CHANNEL p I 7 -25t5nsa u u 25 ns y25+5ns0 U I I I u 1 I I u SENT BY EXTERNAL DEVICE RECEIVED AT PP 1 r , I s I I I I I I I 135 ns 4 w- -4 135 ns CABLE DELAY ICABLE DELAY (APPROX.) I (APPROX.) I EXTERNAL DEVICE I RESPONSE TIME 1 vr I 7 7 - TRANSMllTED FUNCTION ON CHANNEL INACTIVE EMPTY FULL 8 -- I I ' NOTES: @ ALL TRANSMISSION PULSE WIDTHS (INCLUDING DATA. FULL, EMPTY, ETC.) ARE 25: 5 ns 2 O O TO AVOID LOST DATA, ALL INPUTS FROM THE CHANNEL TO THE PP MUST ARRIVE WITHIN THE IO ns. INPUTS MAY BE EARLIER OR LATER BY IOO ns MULTIPLES 3 TOTAL TURNAROUND TIME BETWEEN FUNCTION AND INACTIVE IS MEASURED AT PP. T H 6 T l M E VARIES DUE TO EXTERNAL DEVICE RESPONSE TIME BUT MUST BE WITHIN 310 35 nr TO MAINTAIN THE 5 W ns CYCLE TIME. + . F l g u r e 5-7. Channel Transfer Timing u Idr PP Programming Input/Output Transfers The following paragraphs d i s c u s s input/output t r a n s f e r s with t h e PP. Data Input Sequence The e x t e r n a l device sends d a t a ( f i g u r e 5-8) t o the PP v i a t h e c o n t r o l l e r a s follows : The PP p l a c e s a function word i n t h e channel r e g i s t e r and s e t s t h e f u l l f l a g and t h e channel a c t i v e f l a g . A t t h e same time, t h e PP sends t h e f i r s t of a group of words and f u n c t i o n s i g n a l s t o a l l c o n t r o l l e r s . The f u n c t i o n s i g n a l s cause a l l c o n t r o l l e r s t o sample the words and i d e n t i f y t h e words a s f u n c t i o n codes r a t h e r than d a t a words. Connect codes s e l e c t c o n t r o l l e r s and modes of operation and c l e a r nonselected c o n t r o l l e r s . Only s e l e c t e d c o n t r o l l e r s a r e connected. The c o n t r o l l e r sends an i n a c t i v e s i g n a l t o the PP, i n d i c a t i n g acceptance of t h e f u n c t i o n code. The s i g n a l drops t h e channel a c t i v e f l a g , which i n t u r n , drops t h e f u l l f l a g and c l e a r s t h e channel r e g i s t e r . The PP s e t s t h e channel a c t i v e f l a g and sends a n a c t i v e s i g n a l t o the c o n t r o l l e r , which s i g n a l s the i n p u t equipment t o s t a r t sending d a t a . The i n p u t equipment reads a 12-bit d a t a word p l u s 1 p a r i t y b i t and then sends the word with p a r i t y t o t h e channel r e g i s t e r with a f u l l s i g n a l , which s e t s t h e channel f u l l f l a g (10 t o 1 5 nanoseconds a f t e r the data arrives). The PP s t o r e s the word, drops t h e f u l l f l a g , and r e t u r n s an empty s i g n a l , i n d i c a t i n g acceptance of t h e word. The i n p u t equipment c l e a r s i t s d a t a r e g i s t e r and prepares t o send t h e next word. Steps 4 and 5 repeat f o r each word t r a n s f e r r e d . A t t h e end of the t r a n s f e r , t h e c o n t r o l l e r c l e a r s i t s a c t i v e condition and sends an i n a c t i v e s i g n a l t o t h e PP t o i n d i c a t e t h e end of t h e d a t a . The s i g n a l c l e a r s the channel a c t i v e f l a g t o disconnect t h e c o n t r o l l e r and the PP from t h e channel. As an a l t e r n a t i v e , t h e PP may choose t o d i s c o ~ e c tfrom t h e channel before t h e i n p u t equipment has s e n t a l l i t s d a t a . The PP does t h i s by dropping t h e a c t i v e f l a g and sending an i n a c t i v e s i g n a l t o t h e c o n t r o l l e r , which immediately c l e a r s i t s a c t i v e c o n d i t i o n and sends no more d a t a , although the input equipment may continue t o the end of i t s record o r cycle ( f o r example, a magnetic tape u n i t would continue t o end-of-record and s t o p i n the record gap). PP Programming S B L I ORIGIN Pf' FUNCTION , I , I I ' I I I I I j I , I ,, I I I I / I I I I 6 I I 8 I PP INSTRUCTIONS 76 AND 77 PP INSTRUCTION 74 ACTIVE PP I ' :;DATA: ; I DATA; ; I I I I I I 12-BIT WORD ED + 1 BIT PARITY I FULL ED EMPTY PP INACTIVE ED INACTIVE (ALTERNATE) PP REPEATS FOR EACH WORD t PP INSTRUCTIONS 70 AND 71 DISCONNECT (END OF DATA) PP INSTRUCTION 75 NOTES: O 1 TlME I S A FUNCTION OF EXTERNAL DEVICE (ED). PP RECOGNIZES INACTIVE 1 MAJOR CYCLE (OR A MULTIPLE OF MAJOR CYCLES) AFTER FUNCTION. THE PP MUST PREVIOUSLY RECEIVE INACTIVE. O TlME IS A FUNCTION OF PERIPHERAL PROCESSOR IPP). MINIMUM TlME IS 1 MINOR CYCLE. ACTUAL TIME IS A FUNCTION OF THE W PROGRAM. @ TlME IS A FUNCTION OF ED. 2 ' 4 TlME IS A FUNCTION OF PP. MINIMUM TlME IS 1 MINOR CYCLE. MAXIMUM TlME IS UP TO I MINOR CYCLES TO ALLOW OPERATION WITHIN 1 MAJOR CYCLE. O TlME IS A FUNCTION OF PP. MINIMUM TlME IS 2 MAJOR CYCLES. MAXIMUM TlME IS AN INTEGRAL MULTIPLE OF MAJOR CYCLES. @ TlME IS A FUNCTION OF ED. 5 7. MAJOR CYCLE TIME IS 250 NS. 8. O O 9 10 @ @ @ MINOR CYCLE IS W NS. TlME IS A FUNCTION OF ED. FULL SHOULD PROCEED THE DATA BY A MINIMUM OF 5 NS I15 NS MAXIMUM) TO REMOVE THE CLEAR ON THE INPUT DATA RECEIVERS. PP MAY DISCONNECT AFTER EMPTY SIGNAL OF ANY ED WORD. STATUS REQUEST DISCONNECTS I N THIS MANNER. CHANNEL MUST BE PREVIOUSLY INACTIVE. CHANNEL REMAINS ACTIVE UNTl L ED SENDS INACTIVE. CHANNEL MUST BE PREVIOUSLY INACTIVE. Figure 5-8. Data Input Sequence Timing PP Programming Data Output Sequence The PP send . a t a ( f i g u r e 5-91 t o the e x t e r n a l device as follows. The PP p l a c e s a f u n c t i o n word i n t h e channel r e g i s t e r and s e t s the f u l l f l a g and t h e channel a c t i v e f l a g . The function s i g n a l causes a l l c o n t r o l l e r s t o sample t h e word and i d e n t i f y t h e word as a f u n c t i o n code r a t h e r t h a n a d a t a word. Connect codes s e l e c t c o n t r o l l e r s and modes of operation and c l e a r nonselected c o n t r o l l e r s . Only s e l e c t e d c o n t r o l l e r s a r e connected. The c o n t r o l l e r s e n d s , a n i n a c t i v e s i g n a l t o t h e PP, i n d i c a t i n g acceptance of the f u n c t i o n code. The s i g n a l drops t h e channel a c t i v e f l a g , which i n t u r n , drops the f u l l f l a g and c l e a r s the channel r e g i s t e r . The PP s e t s the channel a c t i v e f l a g and sends a n a c t i v e s i g n a l t o t h e c o n t r o l l e r , which s i g n a l s the output equipment t h a t d a t a flow i s s t a r t i n g . The PP p l a c e s a 12-bit d a t a word p l u s 1 p a r i t y b i t i n t h e channel r e g i s t e r and s e t s t h e f u l l f l a g . Coincidently, t h e PP sends a word w i t h p a r i t y and a f u l l s i g n a l t o the c o n t r o l l e r . The c o n t r o l l e r a c c e p t s t h e word and sends an empty s i g n a l t o t h e PP where t h e s i g n a l c l e a r s t h e channel r e g i s t e r and drops t h e f u l l f l a g . Steps 4 and 5 r e p e a t f o r each PP word. A f t e r t h e l a s t word is t r a n s f e r r e d and acknowledged by t h e c o n t r o l l e r empty s i g n a l , t h e PP drops t h e channel a c t i v e f l a g and t u r n s off t h e c o n t r o l l e r with an i n a c t i v e s i g n a l . PP Programming 1 ACTIVE I I I INSTRUCTIONS 76 A N D 7 7 PP INSTRUCTION 74 SIGNAL - ORIGIN ( FUNCTION PP I n PP ( INACTIVE ED ACTIVE PP I 13-BIT WORD I ~ C T I I I I I I I I I I I I I I I I O COM N I i l l I I k; I I PP I PP ( EMPTY t w I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I @ * I I I I J I I I I I I I l I I I I I I I I :I ( REPEATS FOR EACH ED PP INSTRUCTION 75 INACTIVE PP NOTES: a TlME IS A FUNCTION OF EXTERNAL DEVICE (ED]. PP RECOGNIZES INACTIVE 1 MAJOR CYCLE (OR A MULTIPLE OF MAJOR CYCLES) AFTER FUNCTION. THE PP MUST PREVIOUSLY RECEIVE INACTIVE. @ TlME IS A FUNCTION OF PERIPHERAL PROCESSOR (PP). M I N I M U M TlME IS 1 MINOR CYCLE ACTUAL TlME IS A FUNCTION OF THE PP PROGRAM. @ TlME IS A FUNCTION OF ED @ TlME IS A FUNCTION OF PP. MINIMUM TlME IS 1 MINOR CYCLE. MAXIMUM TlME IS UP TO 4 MINOR CYCLES TO ALLOW OPERATION WITHIN 1 MAJOR CYCLE. @ TlME IS A FUNCTION OF PP. MINIMUM TlME IS 2 MAJOR CYCLES. M A X I M U M TlME IS A N INTEGRAL MULTIPLE OF MAJOR CYCLES. @ TlME IS A FUNCTION OF ED 7. MAJOR CYCLE TlME IS 250 NS. 8. MINOR CYCLE IS 50 NS. @ CHANNEL MUST BE PREVIOUSLY INACTIVE. @ @ CHANNEL REMAINS ACTIVE UNTIL ED SENDS INACTIVE. CHANNEL MUST BE PREVIOUSLY INACTIVE. Figure 5-9. Data Output Sequence Timing System Console Programming System Console Programming Keyboard A PP transmits function code 70208 to request data from the keyboard of the system console. The PP then activates the input channel and inputs one character from the keyboard. This character enters as the lower 6 bits of the word; the upper bits are cleared. There is no status report by the keyboard. Table 5-9 lists the keyboard character codes. Data Display Data is displayed within an 8- by 11-inch area of a cathode-ray tube (CRT). The display can be in character mode (alphanumeric) and/or dot mode (graphic). Two presentation areas (left and right) are displayed. Each is made up of 262 144 dot locations arranged in a 512- by 512-dot format. Each dot position is determined by the intersection of X and Y coordinates. The lower left corner dot i s octal address X16000 and YR7000, and the upper right corner dot is octal address X16777 and Y=7777. An optional CC 634B system console is available. Refer to the hardware reference manual listed in the preface for additional information regarding this terminal. Character Mode In character mode, three sizes are provided. Large characters are arranged in a 32- by 32-dot format with 16 characters per line. Medium characters are arranged id a 16- by 16-dot format with 32 characters per line. Small characters are arranged in an 8- by 8-dot format with 64 characters per line. Table 5-10 lists the display character codes. System Console Programming Table 5-9. Character Keyboard Character Codes Code Character No data 0 A 1 B 2 C D 3 4 E 5 F 6 G 7 H 8 I 9 J K f L M - * / N ( 0 1 P Left blank key Q R s Right blank key 9 T U Carriage return v Backspace W Space X Y Z Code System Console Programming Table 5-10. Character Display Character Codes Code Character 1 2 3 4 5 6 7 8 9 + * / ( 1 Space P Space > Code System Console Programming Dot Mode I n dot mode, d i s p l a y d o t s a r e p o s i t i o n e d by t h e X and Y c o o r d i n a t e s . The X c o o r d i n a t e s p o s i t i o n t h e d o t s h o r i z o n t a l l y . The Y c o o r d i n a t e s p o s i t i o n t h e d o t s v e r t i c a l l y and unblank t h e CRT f o r each d o t . A s e r i e s of X and Y c o o r d i n a t e s form h o r i z o n t a l l i n e s . A s i n g l e X c o o r d i n a t e and a s e r i e s of Y c o o r d i n a t e s form v e r t i c a l l i n e s . Codes A s i n g l e f u n c t i o n word i s t r a n s m i t t e d t o s e l e c t t h e p r e s e n t a t i o n , mode, and c h a r a c t e r s i z e ( c h a r a c t e r mode only). Figure 5-10 i l l u s t r a t e s t h e f u n c t i o n word format. The word following t h e f u n c t i o n word s p e c i f i e s t h e s t a r t i n g c o o r d i n a t e s f o r t h e d i s p l a y ( f o r e i t h e r mode). Figure 5-11 i l l u s t r a t e s t h e c o o r d i n a t e d a t a word. I n c h a r a c t e r mode, t h e words t h a t follow a r e d i s p l a y c h a r a c t e r codes. Figure 5-12 i l l u s t r a t e s t h e c h a r a c t e r d a t a word. 0 = CHARACTER MODE 1 = D O T MODE 2 = KEYBOARD INPUT 0 = LEFT PRESENTAT 1 = RIGHT PRESENTA NOT USED 7 = EQUIPMENT SELECT / I,= 0 = SMALL CHARACTERS MEDIUM CYARACTERS 2 = LARGE CHARACTERS 7 -7 11 , 9 8 7 Figure 5-10. 6 5 32 0 Display S t a t i o n Output Function Code System Console Programming 6=X 7=Y COORDINATE ADDRESS A NOTE: INDOT MODE, EACH Y COORDINATE TRANSMITTED FORCES A DOT DISPLAY. Figure 5-11. FIRST CHARACTER Figure 5-12. Coordinate Data Word SECOND CHARACTER Character Data Word When t h e d i s p l a y o p e r a t i o n has s t a r t e d , t h e c o n t r o l l e r r e g u l a t e s c h a r a c t e r spacing on t h e l i n e . A new c o o r d i n a t e d a t a word must be s e n t t o start each l i n e . I f new c o o r d i n a t e s a r e n o t s p e c i f i e d , d a t a i s w r i t t e n on t h e l i n e s p e c i f i e d by t h e a c t i v e c o o r d i n a t e word, and information a l r e a d y on t h a t l i n e i s o v e r w r i t t e n . Character s i z e s can be mixed by sending a new f u n c t i o n word and coordinate word f o r each s i z e change. Spacing on a l i n e can be v a r i e d by sending a c o o r d i n a t e word f o r t h e c h a r a c t e r that: i s t o be spaced d i f f e r e n t l y . System Console Programming Programming Example The following programming example ( f i g u r e 5-13) r e q u e s t s an i n p u t of one l i n e of d a t a from t h e system console and d i s p l a y s t h i s d a t a on t h e CRT a s I t i s being typed. Programming Timing Considerations When performing an output o p e r a t i o n , t h e computer must waft a t t h e end of t h e output f o r a channel-empty c o n d i t i o n t o prevent a l o s s of c o o r d i n a t e s o r d a t a . A full jump a t t h e end of t h e output e n s u r e s t h a t t h e channel i s empty and the d i s p l a y c o n t r o l l e r a c c e p t s t h e l a s t word of t h e o u t p u t b e f o r e d i s c o n n e c t i n g from t h e channel. System Console Programmrng 0 START INPUT ONE D A T A WORD I ASSEMBLE DATA I N CHARACTER MODE FORMAT ASSEMBLED DATA PLUS I N I T I A L COORDINATES Figure 5-13. Receive and D i s p l a y Program Flowchart Real-Time Clock Programming Real-Time Clock Programming Channel 14 i s reserved f o r t h e real-time clock. This channel, which i s a l w a y s 8 a c t i v e and f u l l , and may be r e a d a t any time. The real-time clock i s a 1 2 - b i t , free-running counter incrementing a t a 1-MHertz r a t e from 0 through 409510. Two-Port Multiplexer Programming NOTE For two-port m u l t i p l e x e r programming, b i t numbering w i t h i n words i s 0 through 63 from l e f t to right. Channel 158 i s reserved f o r communications with one o r two e x t e r n a l d e v i c e s through t h e two-port m u l t i p l e x e r . One p o r t i s r e s e r v e d f o r maintenance purposes, and t h e o t h e r i s r e s e r v e d f o r f u t u r e use. The two-port m u l t i p l e x e r can communicate with all e x t e r n a l d e v i c e s t h a t use EIA s t a n d a r d RS232C s e r i a l i n t e r f a c e . The m u l t i p l e x e r can accommodate d a t a with odd/even p a r i t y , 5 to 8 b i t s per c h a r a c t e r and 1 o r 2 s t o p b i t s . I s s u i n g a p p r o p r i a t e f u n c t i o n codes s e t s t h e format. The r a t e i s switch s e l e c t a b l e f o r each c h a m e l f o r o p e r a t i o n between Il.0 and 9600 baud. These switches a r e l o c a t e d i n t e r n a l l y on t h e two-port m u l t i p l e x e r . Two-Port Multiplexer Programming Two-Port Multiplexer Operation . The Cwo-port m u l t i p l e x e r uses t h e rightmost 12 b i t s on channel 1 5 A 12-bit ( o c t a l ) f u n c t i o n word from t h e PP i s t r a n s l a t e d t o s p e c i f y t h e foalowing operating conditions. A Code Function 7XXX Terminal s e l e c t . 6XXX Terminal d e s e l e c t . ooxx Read s t a t u s summary. Olxx Read t e r m i n a l d a t a . 02xx Write o u t p u t b u f f e r . 03XX S e t o p e r a t i o n mode t o t e r m i n a l . 04XX S e t / c l e a r t e r m i n a l c o n t r o l s i g n a l , d a t a t e r m i n a l ready (DTR). 05XX S e t / c l e a r terminal c o n t r o l s i g n a l , r e q u e s t t o send (RTS). 06XX Not used. 07XX Master c l e a r s e l e c t e d p o r t . Terminal Select (7XXX) The PP sends t h i s s e l e c t code t o s p e c i f y t h e t e r m i n a l t o which t h e f u n c t i o n codes and d a t a t r a n s m i s s i o n s apply. Code 7000 s e l e c t s p o r t 0 ( f o r f u t u r e use), and code 7001 s e l e c t s p o r t 1 (maintenance c o n s o l e ) . Terminal Deselect (GXXX) The PP sends t h i s code, which d e s e l e c t s t h e two-port m u l t i p l e x e r from channel 158 SO the 16-bit channel i s a v a i l a b l e f o r inter-PP communications. Two-Port Multiplexer Programming Read Status Summary (OOXX) T h i s code permits t h e PP t o i n p u t s t a t u s from t h e s e l e c t e d t e r m i n a l . One-word i n p u t must f o l l o w t o r e a d t h e s t a t u s r e s p o n s e . The r e s p o n s e i s 1 2 b i t s , w h i c h a r e d e f i n e d a s follows. Bit Status 52-58 Not used. 59 Output b u f f e r n o t f u l l . 60 I n p u t ready. 61 Data c a r r i e r d e t e c t o r c a r r i e r on. 62 Data set ready. 63 Ring i n d i c a t i o n . PP Read Terminal Data (01XX) T h i s code p e r m i t s t h e PP t o i n p u t t h e terminal d a t a from t h e s e l e c t e d t e r m i n a l . Channel 158 must be a c t i v a t e d , and a 1-word i n p u t must f o l l o w t o r e a d i n t h e t e r m i n a l d a t a . The d a t a word i s 1 2 b i t s , which a r e d e f i n e d a s f o l l o w s . Bit Status 52 Data set ready. 53 Data s e t ready and d a t a c a r r i e r d e t e c t o r . 54 Over r u n . 55 Framing or p a r i t y e r r o r . 56-63 8-bit d a t a . Data Set Ready (Bit 52) When t h e d a t a s e t ready signal i s a c t i v e , t h i s b i t s e t s . Two-Port Multiplexer Programming Data set Ready (DSR) and Data Carrier Detector (DCD) (Bit 53) When both d a t a s e t ready and d a t a c a r r i e r d e t e c t o r s i g n a l s a r e a c t i v e , t h i s b i t sets. Over Run (Bit 54) When t h e p r e v i o u s l y received c h a r a c t e r i s not read by t h e PP b e f o r e t h e p r e s e n t c h a r a c t e r i s t r a n s f e r r e d t o t h e d a t a holding r e g i s t e r , t h e overrun b i t s e t s . Framing or Parity Error (Bit 55) When t h e received c h a r a c t e r does not have a v a l i d s t o p b i t (framing e r r o r ) o r when t h i s b i t s e t s , t h e r e c e i v e d c h a r a c t e r p a r i t y does n o t a g r e e with t h e select parity (parity error). Data Character (Bits 56 Through 63) The lower 8 b i t s of t h e i n p u t word form t h e d a t a c h a r a c t e r . The m u l t i p l e x e r forms t h i s c h a r a c t e r d i r e c t l y from t h e Universal Asynchronous Receiver and T r a n s m i t t e r (UART). PP Write Output Buffer (02XX) This code prepares t h e m u l t i p l e x e r f o r an output o p e r a t i o n t o t h e 64-character output b u f f e r memory. Before an output o p e r a t i o n can proceed, channel must be a c t i v a t e d . The output o p e r a t i o n i s terminated when t h e m u l t i p l e x e r r e c e i v e s an i n a c t i v e s i g n a l from the PP o r when no more l o c a t i o n s a r e a v a i l a b l e i n t h e output b u f f e r . I n t h e l a t t e r c a s e , an i n a c t i v e ( i n s t e a d of empty) s i g n a l i s s e n t back t o t h e channel, which i n t u r n , t e r m i n a t e s t h e o u t p u t o p e r a t i o n s . Two-Port Multiplexer Programming Set Operation Mode to the Terminal (03XX) T h i s code p e r m i t s t h e PP t o set t h e t e r m i n a l o p e r a t i o n mode r e g i s t e r . A 1 2 - b i t f u n c t i o n code word from t h e PP s p e c i f i e s t h e o p e r a t i o n of t h e t e r m i n a l . Thisword i s decoded i n t h e f u n c t i o n r e g i s t e r . Segments of t h e word d e f i n e t h e mode a s follows: Bit Status Not used. No p a r i t y . When t h i s b i t i s s e t , i t e l i m i n a t e s t h e p a r i t y b i t from t h e t r a n s m i t t e d and r e c e i v e d c h a r a c t e r s . The s t o p b i t ( s ) immediately follow the l a s t data b i t . Number of s t o p b i t s . T h i s b i t s e l e c t s t h e number of s t o p b i t s , 1 o r 2 , t o be appended immediately a f t e r t h e p a r i t y b i t . When t h i s b i t i s c l e a r , i t i n s e r t s 1 s t o p b i t and when s e t , i t i n s e r t s 2 s t o p b i t s . Number of b i t s p e r c h a r a c t e r . These 2 b i t s a r e i n t e r n a l l y decoded t o s e l e c t 5 , 6 , 7 , o r 8 d a t a b i t s per character. B i t 61 B i t 62 B i t s Per C h a r a c t e r 0 0 0 - 1 1 1 0 5 6 7 8 1 Odd/even p a r i t y s e l e c t . T h i s b i t s e l e c t s t h e t y p e of p a r i t y t h a t w i l l be appended It a l s o determines t h e p a r i t y immediately a f t e r t h e d a t a b i t s . t h a t w i l l be checked on read d a t a . Set/Clear Data Terminal Ready (04XX) This code p e r m i t s t h e PP t o s e t o r c l e a r t h e t e r m i n a l c o n t r o l s i g n a l , d a t a t e r m i n a l ready (DTR). When b i t 63 i s s e t , DTR i s a c t i v e , and when b i t 6 3 i s c l e a r , DTR i s i n a c t i v e . Two-Port Multiplexer Programming SetKlear Request to Send (05XX) This code permits t h e PP t o s e t o r c l e a r the terminal c o n t r o l s i g n a l , r e q u e s t t o send (RTS). When b i t 63 i s s e t , RTS i s a c t i v e , and when b i t 63 i s ciear, RTS i s i n a c t i v e . Master Clear (07XX) This code permits t h e PP t o master c l e a r t h e s e l e c t e d p o r t including i t s output b u f f e r memory and UART. The terminal operation mode r e g i s t e r and terminal c o n t r o l s i g n a l s a r e not cleared. Programming Considerations Channel 158 communicates with the terminals connected t o t h e e x t e r n a l i n t e r f a c e , one a t a - t i m e . To e s t a b l i s h communications between a PP and t h e t e r m i n a l , t h e PP i s s u e s a function f o r s e l e c t . The f u n c t i o n word f o r s e l e c t i s formed by the l e a s t - s i g n i f i c a n t 12 b i t s , which a r e s e n t t o channel Is8, and s p e c i f i e s the following information. A s e l e c t code t o s e l e c t t h e multiplexer (7XXX). a The terminal with which t h e PP would l i k e t o e s t a b l i s h communication (7XXX). When t h e connect i s e s t a b l i s h e d , t h e two-port multiplexer r o u t e s a l l d a t a t o the terminal designated by t h e s e l e c t code. The multiplexer responds with t h e i n a c t i v e s i g n a l t o acknowledge t h e r e c e i p t of the f u n c t i o n code of 7XXX f o r s e l e c t ; 6XXX f o r d e s e l e c t , and OXXX f o r operation. Otherwise, t h e m u l t i p l e x e r ignores t h e function. Two-Port Multiplexer Programming Output Data The multiplexer a c c e p t s a maximum d a t a block length of 64 c h a r a c t e r s per terminal. During t h e block d a t a t r a n s f e r , the m u l t i p l e x e r t e r m i n a t e s t h e output o p e r a t i o n e i t h e r when it r e c e i v e s an i n a c t i v e s i g n a l from t h e channel or when t h e output b u f f e r i s f u l l . When t h e output b u f f e r i s f u l l , t h e multip l e x e r sends back an i n a c t i v e s i g n a l i n s t e a d of an empty s i g n a l t o t h e channel on t h e l a s t output word. The s i g n a l i n d i c a t e s t h e output b u f f e r a c c e p t s t h e l a s t output word and i t cannot r e c e i v e anymore d a t a from t h e PP. The multip l e x e r does not allow output t o a f u l l b u f f e r . The m u l t i p l e x e r sends back a n i n a c t i v e s i g n a l t o d e a c t i v a t e channel 15 a f t e r t h e m u l t i p l e x e r decodes t h e previous f u n c t i o n code, which i s OZXX (PB w r i t e output b u f f e r ) , and r e c e i v e s a n a c t i v a t e s i g n a l from t h e PP. Input Data The multiplexer does not s t o r e t h e i n p u t d a t a from t h e t e r m i n a l . A l o s t d a t a c o n d i t i o n e x i s t s i f t h e PP does not i n p u t t h e previous d a t a before t h e new d a t a a r r i v e s from t h e terminal. The multiplexer allows i n p u t from an empty i n p u t buffer . Request to Send and Data Terminal Ready The hardware b r i n g s up r e q u e s t t o send and d a t a t e r m i n a l ready a u t o m a t i c a l l y under t h e following c o n d i t i o n s r e g a r d l e s s of the software RTS and DTR b i t s . Data i n t h e UART output r e g i s t e r . 0 Data i n t h e FIFO output r e g i s t e r . When no d a t a i s i n t h e FIFO o r UART, t h e software b i t determines RTS and DTR. Maintenance Channel Programming Maintenance Channel Programming NOTE Maintenance registers are numbered 0 through 63 from left to right. Maintenance Channel A PP in the IOU can perform any or all of the following operations through the maintenance channel (MCH) to each system element, such as the CP, IOU, and CM. Initializing registers, controls, and memories. Monitoring and recording error information. 0 Verifying error-detection and correction hardware. The maintenance channel consists of the maintenance channel interface on channel 17 , a maintenance channel interface in each system element, and a set of intgrconnecting cables. The IOU maintenance channel interface contains a selector that connects to one of up to seven system elements. The IOU is element 0, and its maintenance access control is internally connected to the selector. All other system elements are assigned arbitrary element numbers. A single cable connects each maintenance access control to the selector. This arrangement results in a radial connection that allows any system element to be shut down or removed without affecting communication with the other elements. Maintenance Channel Programming MCH Function Words The MCH f u n c t i o n word c o n s i s t s of t h e connect, opcode, and type f i e l d s , which a r e used a s described I n t h e next t h r e e paragraphs and t a b l e s 5-11 and 5-12. The connect f i e l d s p e c i f i e s t h e u n i t t o which t h e MCH i s connected (CP, CM, or IOU), c o n t r o l l i n g s e l e c t i o n w i t h i n t h e I O U only. The u n i t remains c o m e c t e d u n t i l another connect code s e l e c b s a d i f f e r e n t u n i t . Connect codes 10 t o 178 l e a v e t h e MCB unconnected; i n t h i s s t a t e , t h e i n t e r f a c e can be u s e s f o r PP t o PP communications. The OPCODE f i e l d c o n t r o l s t h e u n i t s e l e c t e d by t h e connect code, p r e p a r i n g the u n i t f o r a coming read/write/echo o p e r a t i o n o r causing t h e u n i t t o h a l t , s t a r t , clear, or deadstart. The use of t h e TYPE f i e l d depends on t h e connected u n i t . When t h e CP i s t h e connected u n i t , type codes 1 through 7 s p e c i f y t h e d a t a t y p e i n t h e o p e r a t i o n t o be performed. Also, f o r t h e CP, type code 0 s p e c i f i e s t h a t t h e i n t e r n a l address of t h e CP r e g i s t e r t o be connected is s p e c i f i e d i n a c o n t r o l word, which i s s e n t as 2 d a t a words immediately following t h e f u n c t i o n word. When IOU i s t h e connected u n i t , type codes 0 through 7 s p e c i f y t h e s t a r t i n g byte number f o r r e a d l n r i t e operations. The exceptions a r e r e a d i n g t h e o p t i o n s i n s t a l l e d and element i d e n t i f i e r r e g i s t e r s . CM u s e s A16 t o a c c e s s t h e maintenance- r e g i s t e r s . Maintenance Channel Programming Table 5-11. B i t Assignments f o r MCH Function Word t o CP and CM MCH Function Word t o CP and CM Field - TYPE ( b i t s 0-3) Code 016 - -- .... - - = CP and CP r e g i s t e r s . = = = = Halt processor. S t a r t processor. Prepare f o r read. Prepare f o r write. Master c l e a r . Clear e r r o r s . Code 116 = C o n t r o l s t o r e memory. OPCODE (bits 4-71 Code 416 516 = P r e p a r e f o r read. Prepare f o r write. OPCODE ( b i t s 4-71 Code 016 116 416 516 616 716 TYPE ( b i t s 0-3) TYPE ( b i t s 0-3) Code 3-716 OPCODE ( b i t s 4-71 Code 416 516 TYPE ( b i t s 0-3) a ' = I n t e r n a l memories. = = P r e p a r e f o r read. Prepare t o write. CM and C M registers. Code A16 OPCODE ( b i t s 4-71 Code 416 5i6 616 716 Table 5-12. = = = = P r e p a r e f o r read. P r e p a r e f o r write. Master c l e a r . Clear e r r o r s . B i t Assignments f o r MCH Function Word t o I O U MCH Function Word t o I O U Field CONNECT ( b i t s 8-11) Code 016 OPCODE ( b i t s 4-7) Code 416 516 616 716 C16 TYPE ( b i t s 0-3) Connect I O U maintenance r e g i s t e r s . a = a ' a Codes 0-716 = P r e p a r e f o r r e a d ( c o n t r o l word r e q u i r e d ) . P r e p a r e f o r w r i t e ( c o n t r o l word required). Master c l e a r . Clear f a u l t s t a t u s r e g i s t e r s . Read I O U s t a t u s summary ( r e a d s 1 b y t e , c o n t r o l word n o t r e q u i r e d ) . I O U r e g i s t e r s a r e read c i r c u l a r l y (byte 0 f o l l o w s b y t e 7 ) from t h e b y t e s p e c i f i e d by t h e TYPE f i e l d . Maintenance Channel Programming MCH Control Words Some function words must be followed by two 8-bit control words, which specify the internal address of the register to be accessed. This is accomplished by transmitting two PP words where the rightmost 8 bits in each word are used. Control words are required.for the following. Function words to CP with opcodes 415. Function words to CM and IOU with opcodes 4/5. Function words to CP, CM, and IOU with opcode 8 (echo). Refer to tables 5-13 through 5-15 for CP, CM, and IOU internal address assignments. MCH Programming for HaWStart (Opcode 0/1) These operations consist of the output of a function word. A halt opcode halts the processor without damaging the process being executed,.including the integrity of the interunit communication of the halted processor such as CDC CYBER 170 exchange 'request commuaication, central memory communications, and the process state. If the process is subsequently restarted without performing any other MCH operations or after performing read/write with certain precautions, the process continues without damage. MCH Clear LED (Opcode 3) This operation clears all LEDs associated with pak errors and is intended, but not required, for use at system initialization. For maintenance reasons, this operation can also clear LEDs without initializing and master-clearing. Maintenance Channel Programming MCH Programming for Read/Write (Opcode 4/5) Refer to Programming for PP Data 1nput/output in this chapter for a more complete procedure. In general terms, proceed as follows: 1. Issue the function with opcode 4/5. 2. Output the first control word. 3. Verify the error flag is clear. 4. Output the second control word. 5. Verify the error flag is clear. 6. Input/output the required number of data words. 7. Verify the error flag is clear. Reading a nonexistent register returns all 0's. Writing to a read-only register or to a nonexistent register does not alter any register. Most registers are readlwrite as 64-bit (8-byte) registers, requiring the input/ output of 8 MCH data words. Most registers that are physically smaller than 8 bytes are right-justified with zero-fill. Fixceptions are as follows: a Reading a status summary register repeats the status information in each byte. a The IOU may disconnect the MCH without affecting subsequent MCH operations in the following cases: - After reading 1 to 8 bytes from any maintenance register. - After writing 1 byte to a corrected error log register. - After writing 1 byte to an uncorrected error log register. The following MCH operations on CP registers can be performed with the CP running or halted. a Read CP status summary register. Read CP fault status register. Read CP corrected error log registers. a Read CP options installed registers. Read CP element identifier register. Readlwrite CP dependent environmental control register. a ~ead/writetest mode control registers. a Clear errors. To readlwrite other CP-registers, the CP must be running since these registers are accessed by microcode. Refer to the Maintenance Register Codes Booklet listed in the preface for register bit assignments. 60463560 A Maintenance Channel Programming MCH Programming for Master Clear/Clear Errors (Opcode 6/7) These operations c o n s i s t of t h e output of a s i n g l e f u n c t i o n word. The master c l e a r immediately and a r b i t r a r i l y c l e a r s the connected u n i t without regard to p o s s i b l e information l o s s . Clear e r r o r s c l e a r s the e r r o r i n d i c a t o r s i n t h e connected u n i t . To avoid l o s s of e r r o r information while the e r r o r s a r e c l e a r e d , t h e u n i t concerned should be h a l t e d . MCH Echo (Opcode 8) This operation checks the d a t a path between the MCH and t h e I O U MAC. Following IOU ignores t h e o p e r a t i o n MCH i s a c t i v a t e d and 2 bytes a r e s e n t t o I O U MAC. t h e f i r s t byte and l a t c h e s t h e second byte i n t h e Address Holding R e g i s t e r i n any d a t a p a t t e r n . MCH i s d e a c t i v a t e d after the second byte i s accepted i n I O U MAC, and t h e channel i s a c t i v a t e d followed by an input sequence. I O U MAC sends d a t a ( c o n t e n t s of Address Holding R e g i s t e r ) upon r e c e i v i n g t h e Active s i g n a l and subsequent Empty s i g n a l s . There i s no r e s t r i c t i o n on t h e number of data words read. MCH Programming for Read IOU Status summary (Opcode C, IOU Only) This o p e r a t i o n i s an a l t e r n a t i v e , f a s t e r means of reading t h e I O U s t a t u s summary r e g i s t e r . 1. I s s u e function with opcode C. 2. Input s t a t u s summary byte. Maintenance Channel Programming Table 5-13. CP Internal Address Assignments Internal Address (1) Hex Octal Type (2) (3) Description 00 000 R A Status summary register. 10 020 R A Element identifier register. 30 060 R A Dependent environment control register. 42 082 R M Monitor condition register. 80-89 200-2U R A Processor fault status registers 1 through 9. Notes: (1) The internal address is the second byte of two 8-bit control words, which must be supplied after a function word output with OPCODE ' 4/5. The first byte is discarded. (2) R (3) A = always accessible, M = read, W = write. Table 5-14. a microcode accessible. CM Internal Address Assignments Internal Address (1) Hex Octal Type (2) Description 00 000 R Status summary register. 10 020 R Element identifier register. 12 022 R Options installed register. A0 240 R/W Corrected error log register. A4 244 R/W Uncorrected error log 1 register. A8 250 R/W Uncorrected error log 2 register. Notes: (1) The internal address i s the second byte of two 8-bit control words, which must be issued after a function word output with OPCODE = 4/5. The first byte is discarded. (2) R = read, W a mite. Maintenance Channel Programming Table 5-15. IOU Internal Address Assignments Internal Address (1) Hex Octal Type (2) Description 00 000 R Status summary register. 10 020 R Element identifier register. 12 022 R Options installed register. 18 030 R/W Fault status mask register. 40 100 R Status register. 80 200 R/W Fault status 1 register. 81 201 R/W Fault status 2 register. A0 240 R/W Test mode. Notes: (1) The internal address is the second byte o f two 8-bit control words, which must be issued after a function word output with OPCODE a 4/5. The first byte is discarded. (2) R read, W write. Appendix Glossary A ADU Assembly-disassembl y u n i t A0K Address o u t of r a n g e C CEL Corrected e r r o r l o g CIF CMU i n t e r r u p t e d f l a g CIO Concurrent i n p u t / o u t p u t CM C e n t r a l memory CMU Compare/move u n i t Central processor Cathode-ray t u b e Common T e s t and I n i t i a l i z a t i o n D DMA Direct-memory a c c e s s DS C Display s t a t i o n DTR Data t e r m i n a l r e a d y E ECC E r r o r c o r r e c t i o n code ECL Emitter-coupled l o g i c EDS Extended d e a d s t a r t ELA Electronic Industries Association EM, EMS E x i t mode s e l e c t i o n EC E x i t c o n d i t i o n code field a t (RAC) Glossary F FIFO First in, first out F LC Field length, central memory FLE Field length, extended memory H HIVS Hardware Inittalization and Verification Software Instruction lookahead hardware Input/output Input/output unit Intelligent peripheral interface Intelligent standard interface M MA Monitor address MCH Maintenance channel >IF Monitor flag MO S Metal oxide semiconductor MUX Multiplexer, selector N NIO Nonconcurrent input/output Operating system Glossary P PE Parity error PP Peripheral processor PPM Peripheral processor memory R RAC Reference address, central memory RAE Reference address, extended memory RAM Random access (read-write) memory RN I Read next instruction ROM Read-only memory RT S Request to send S SECDED Single-error correction double-error detection U U ART Universal Asynchronous Receiver and Transmitter UEM Unified extended memory Index Index A register 2-11,25 Access and cycle times 2-17 Activate instruction 4-97 Add instruction 4-72,73 Addition and subtraction 5-12 Address out of range error 2-12 Address registers, see A registers Addressing section in CP 1-8 Addressing mode Expanded 5-24 Standard 5-24 Addressing section 2-15 B register 2-11 Bank select 2-17 Barrel and PP reconfiguration example (RPaO) 3-12 Barrel and PP reconfiguration example (RP-2) 3-13 Barrel and slot 2-23 Barrel numbering table 3-9 Bit numbering 5 Block copy flag 2-13 Block copy from UEM to CM instruction 4-16,17 Block copy instruction 2-7 Block copy instructions 2-13; 5-24 Block copy sequence 2-7 Boolean sequence 2-2 Bounds register 2-16,21 Branch instruction 2-8 Branch to K instruction 4-10,11,12,13,14 Cache memory 2-1 5 Cache Memory 1-8 Cathode ray tube, see CRT CC634 system console 2-23 Central exchange jump instruction 2-8; 4-40 Central memory control, see CMC 1-8 Central memory, see CM Central processor, see CP 1-3 Central read from instruction 4-89 Central read words from instruction 4-90 Central write to instruction 4-91 Central write words to instruction 4-92 Channel active/inactive flag 5-3 1 Channel control flag 5-30 Channel, 110, see IOU Channel, maintenance, see maintenance channel Channel marker flag instructions 5-32 Channel operation Channel active/inactive flag 5-31 Channel control flag 5-30 Channel marker flag instructions 5-32 Channel transfer timing 5-32 Error flag instructions 5-32 Register full/empty flag 5-31 Channel transfer timing 5-32 Character data word 5-41 Character mode 5-38 Characteristics CM 1-4 CP 1-3 Functional 1-2 IOU 1-5 Physical 1-1 Chassis configuration Dual CP 1-2 Single CP 1-2 Chip address 2-17 Chip select 2-17 1-11; 2-22,27 CIO Clear channel flag instruction 4-94 CM 4-17 Access and cycle times 2-17 . Address format 2-16 Address formation 2-1 3 Addressing mode 5-24 Bank select 2-17 Block copy instructions 5-24 Bounds register 2-21 Characteristics 1-4 Chip address 2-17 Chip select 2-17 Column address select 2-17 Configuration switches 3-3 Direct readlwrite instructions 5-24 Extended, see UEM Functional descriptions 2-16 Internal address assignments 5-58 Layout 2-21 Major system component descriptions 1-9 Index Ports and priorities 2-18 Programming 5-22 Quadrant select 2-17 Queuing buffer 1-9 Reconfiguration 2-21; 3-5 Reference address register, see RAC register Row address select 2-17 SECDED 2-19 UEM 1-9 CM access 2-28 CM configuration switches 3-3 CM controls 3-3 CM internal address assignments 5-58 CM map 5-24 CM read/write instructions PP CM read instructions 5-27 PP CM write instructions 5-27 CM reconfiguration 3-5 CMC 2-15 CMU instructions, see compare/move instruction seqeunce CMU interrupted flag 2-13 Codes 5-41 Column address select 2-17 Compare collated Compare/move arithmetic 5-13 Compare collated instruction 2-6; 4-44 ~ompare/movearithmetic Compare collated 5-13 Compare uncollated 5-13 Move direct 5-13 Move indirect 5-13 Compare/move instruction sequence 2-6 Compare uncollated ~ompare/movearithmetic 5-13 Compare uncollated instruction 2-6 Conditional Software errors 5-21 Configuration, mainframe 1-1 Configuration switches CM 3-3 Configuration switches, CM 3-1 Continue if instruction 4-10,11,12 Control checks 3-7 Controls and indicators 3-1 CP Addressing section 1-8; 2-15 Cache memory 2-15 Characteristics 1-3 CMC 1-8; 2-15 Execution section 2-15 Functional descriptions 2-1 Instruction descriptions 4-1,5 Instruction designators 4-3 Instruction formats 4-1 Instruction section 1-6; 2-1 Internal address assignments 5-58 Major system component descriptions 1-6 Operating modes 4-4 Operating Registers 1-7 Programming 5-1 Registers 2-9 Support Registers 1-7 CP Programming Compare/move arithmetic 5-13 CYBER 170 exchange jump 5-1 Error response 5-14 Executive state 5-4 Fixed-point arithmetic 5-12 Floating-point arithmetic 5-4 Instruction lookahead purge control 5-13 Integer arithmetic 5-13 CRT 2-27 CYBER 170 exchange jump 2-14; 5-1,3 CYBER 170 exchange package 2-22; 4-62; 5-1,3,14 CYBER 170 exchange package address 5-2 CYBER 170 exchange request 2-22 CYBER 170 job mode 5-1,15,21 CYBER 170 monitor flag 5-1 CYBER 170 monitor flag clear 2-14 CYBER 170 monitor mode 5-1,15,21 C1 register 2-6 C2 register 2-6 Data character (bits 56 - 63) 5-48 Data display Character mode 5-38 Codes 5-41 Dot mode 5-38 Data input sequence 5-34 Data output sequence 5-36 Data set ready (bit 52) 5-47 Data set ready (DSR) and data carrier detector (DCD) (bit 53) 5-48 DCD, see Data set ready (DSR) and data carrier detector Deactivate instruction 4-98 Deadstart 2-23 Display operator entries and functions 3-4 Displays and controls 3-1 Initial display 3-2 Options display 3-4 Sequences 3-8 Switches 3-1 Description, major system component 1-6 Direct read/write instruction sequence 2-7 Index 1 Direct read /write i n s t r u c t i o n s CM 5-24 Direct read/write instructions UEM 5-24 D i r e c t 12-bit a d d r e s s 5-26 D i r e c t 1 8 - b i t operand 5-25 D i r e c t 6 - b i t a d d r e s s 5-26 D i r e c t 6 - b i t operand 5-25 D i s p l a y c h a r a c t e r codes 5-38 Display s t a t i o n c o n t r o l l e r (DSC) 2-27 DMA 1-11; 2-22,27 Dot mode 5-41 Double-precision r e s u l t s 5-1 1 DSC 2-27 DSC, s e e D i s p l a y s t a t i o n c o n t r o l l e r DSR, s e e Data set ready DTR, s e e S e t / C l e a r d a t a t e r m i n a l ready ECL 1-2 EM r e g i s t e r 2-12; 5-3 EMC 5-14,15,16,17,18 E m i t t e r coupled l o g i c , s e e ECL EMS b i t s , see E x i t mode s e l e c t i o n b i t s E r r o r e x i t i n s t r u c t i o n 2-8 E r r o r e x i t t o MA i n s t r u c t i o n 4-61 E r r o r f l a g i n s t r u c t i o n s 5-32 E r r o r r e s p o n s e 5-14 C o n d i t i o n a l s o f t w a r e e r r o r s 5-21 Hardware e r r o r s 5-21 I l l e g a l i n s t r u c t i o n s 5-14 Software e r r o r s 5-21 Exchange jump i n s t r u c t i o n 4-10 1 Exchange jump, see CYBER 170 exchange jump Exchange package, s e e CYBER 170 exchange package r e q u e s t Exchange sequence, s e e CYBER. 170 exchange sequence r e q u e s t E x e c u t i o n s e c t i o n 1-8; 2-15 E x e c u t i o n timing 4-102 E x e c u t i v e s t a t e 5-4 E x i t mode r e g i s t e r , s e e EM r e g i s t e r E x i t mode s e l e c t i o n b i t s 5-14 Expanded a d d r e s s i n g mode 5-24 Expanded a d d r e s s i n g s e l e c t f l a g 2-13 Extended purge c o n t r o l , s e e i n s t r u c t i o n lookahead purge c o n t r o l F i e l d l e n g t h f o r UEM r e g i s t e r , see FLE register F i n a l i n s t r u c t i o n 4-18,20 Fixed-point a r i t h m e t i c A d d i t i o n and s u b t r a c t i o n 5-12 I n t e g e r d i v i d e 5-12 I n t e g e r m u l t i p l i c a t i o n 5-12 F l a g r e g i s t e r s 2-13 FLC r e g i s t e r 2-12,21; 5-3 FLE r e g i s t e r 2-14,21 Floating-add i n s t r u c t i o n sequence 2-4 F l o a t i n g d i f f e r e n c e i n s t r u c t i o n 2-4 ; 4-29 F l o a t i n g d i v i d e i n s t r u c t i o n 2-4; 4-35 F l o a t i n g d i v i d e i n s t r u c t i o n sequence 2-4 Floating double-precision d i f f e r e n c e i n s t r u c t i o n 2-4; 4-30 F l o a t i n g d o u b l e - p r e c i s i o n product i n s t r u c t i o n 2-4 ; 4-3 4 F l o a t i n g d o u b l e - p r e c i s i o n sum i n s t r u c t i o n 2-4; 4-28 F l o a t i n g - m u l t i p l y i n s t r u c t i o n sequence 2-4 Floating-point a r i t h m e t i c Double-precision r e s u l t s 5-1 1 Format 5-4 I n d e f i n i t e 5-7 Nonstandard o p e r a n d s 5-8 Normalized numbers 5-10 Overflow '5-7 Packing 5-5 Rounding 5- 10 Underflow 5-7 F l o a t i n g product i n s t r u c t i o n 2-4; 4-32 F l o a t i n g sum i n s t r u c t i o n 2-4; 4-27 Form mask i n s t r u c t i o n 2-3; 4-63 Format 5-4 Framing o r p a r i t y e r r o r ( b i t 55) 5-48 F u n c t i o n i n s t r u c t i o n 4-99 F u n c t i o n a l C h a r a c t e r i s t i c s 1-2 Functional descriptions CM 2-16 CP 2-1 IOU 2-22 G Glossary A-1 H F i e l d l e n g t h f o r CM r e g i s t e r , s e e FLC register Hardware e r r o r s 5-21 110 channel communications 5-28 110 transfers Data input sequence 5-34 Data output sequence 5-36 ILH, see Instruction lookahead Illegal instruction 5-20 Increment sequence instruction 2-5 Indefinite 5-7 Indefinite operand error 2-12 Index registers, see B register Indirect 6-bit address 5-26 Infinite operand error 2-12 Initial instruction 4-18,20 Initialization 2-1 Input data 5-51 Input instruction 4-95 ~nput/outputchannel, see I/O channel communications Input/output unit, see IOU Instruction Increment sequence 2-5 Instruction control sequences Block copy sequence 2-7 Boolean sequence 2-2 Compare/move sequence 2-6 CYBER 170 exchange sequence 2-7 Direct readlwrite sequence 2-7 Floating-add sequence 2-4 Floating divide sequence 2-4 Foating-multiply sequence 2-4 Increment sequence 2-5 Normal jump sequence 2-8 Population count 2-4 Return jump sequence 2-8 Shift sequence 2-3 Instruction descriptions CP 4-1,5 Instruction designators, CP 4-3 Instruction execution timing 4-102 Instruction formats CP 4-1 Instruction lookahead 2-1 Purge control 5-14 Instruction lookahead purge control 2-13; 5-14 Instruction lookahead purge flag 2-13 Instruction prefetch, see Instruction lookahead Instruction section 2-1 CP 1-6 Instruction control sequences 2-2 Instruction lookahead 2-1 Maintenance access control 2-1 Instruction word designators, CP 4-3 Instruction word format, CP 4-1 Instructions Activate 4-97 Add 4-72,73 Block copy 2-7 Block copy from CM to UEM 4-17 Block copy from UEM to CM 4-16 Branch 2-8 Branch to K 4-10,11,12,13,14 Central exchange jump 2-8; 4-40 Central read from 4-89 Central read words from 4-90 Central write to 4-91 Central write words to 4-92 Clear c h a ~ e lflag 4-94 Compare collated 2-6; 4-44 Compare uncollated 2-6 Continue if 4-10,11,12 Deactivate 4-98 Error exit 2-8 Error exit to MA 4-61 Exchange jump 4-101 Final 4-18,20 Floating difference 2-4; 4-29 Floating divide 2-4; 4-35 Floating double-precision difference 2-4; 4-30 Floating double-precision product 2-4; 4-34 Floating double-precision sum 2-4; 4-28 Floating product 2-4; 4-32 Floating sum 2-4; 4-27 Form mask 2-3; 4-63 Function 4-99 Illegal 5-20 Initial 4-18,20 Input 4-95 Integer difference 4-8 Integer sum 4-8 Jump 2-8; 4-87,88 Jump to B 4-38 Jump to K 4-10,11,12,13 Left shift 2-3; 4-18,19 Left shift nominally 2-3 Load 4-69,70 Load complement 4-69 Load R register 4-69 Logical difference 2-2; 4-23,76,77 Logical difference of X with complement of X 4-24 Logical product 2-2; 4-24,25,78 Logical sum 2-2; 4-22 Logical sum of X with complement of X 4-23 Long-add 2-6 Long jump 4-83 Index Lookahead 2-1 Minus jump 4-86 Monitor exchange jump 4-40,101 Monitor exchange jump to MA 4-101 Move direct 2-6; 4-43 Move indirect 2-6; 4-43 Nonzero jump 4-85 Normalize 2-3; 4-58 Normalize operations 2-3 Instructions Output 4-96 Pack 2-3; 4-6 Pass 4-60,100 Plus jump 4-86 Population count 2-4; 4-64 Read CM 2-7; 4-57 Read free running counter 4-64 Read one word 4-62 Read one word from UEM 2-7 Replace add 4-80,81 Replace add one 4-80,81 Replace subtract one 4-82 Return jump 2-8; 4-37,84 Right shift 2-3; 4-20,21 Right shift nominally 2-3 Round floating difference 2-4; 4-31 Round floating divide 2-4; 4-36 Round floating product 2-4; 4-33 Round floating sum 2-4; 4-28 Round normalize 2-3; 4-59 Selective clear 4-75 Set A 4-47,48,49,50 Set Ai 2-5 Set B 4-51,52,53 Set Bi 2-5 Set X 4-54,55,56 Set Xi 2-5 Shift 4-75 Store 4-71 Store R register 4-71 Subtract 4-74 Test and set flag 4-94 Transmissive operation 2-2 Transmit 2-2 Transmit complement 2-2 Transmit complement of 4-41 Transmit X 4-41 Unconditional jump 4-84 Unpack 2-3; 4-7 Write CM 4-57 Write into CM 2-7 Write one word 4-62 Write one word to UPI 2-7 Zero jump 4-85 Instructions, CP (see also inside front cover) Block copy from CM 4-17; 5-24 Block copy from Urn 4-16; 5-24 Branch 4-10 ,11,12,13 ,I4 Central exchange jump 4-40 Compare collated 4-44; 5-13 Compare uncollated 4-45; 5-13 Direct read/wrlte of CM 5-25 Direct read/write of UEM 5-25 Error exit 4-61 Final 4-18,20 Fixed point addition 5-10 Floating difference 4-29 Floating divide 4-35 Floating double-precision difference 4-30 Floating double-precision product 4-34 Floating double-precision sum 4-28 Floating point 5-10 Floating product 4-32 Floating sum 4-27 Form mask 4-63 Increment 5-12 Initial 4-18,20 Integer difference 4-8 Integer divide 5-12,13 Integer multiplication 5-12,13 Integer sum 4-8 Jump 4-38 Left shift 4-18,19 Logical difference 4-24 Logical product 4-25 Logical sum 4-23 Move direct 4-43; 5-13 Move indirect 4-43; 5-13 Normalize 4-58; 5-12,13 Pack 4-6 Packing 5-12 Pass 4-60 Population count 4-64 Read free running counter 4-64 Read one word 4-62 Read word from CM 4-57; 5-27 Return jump 4-37 Right shift 4-20,21 Round floating difference 4-31 Round floating divide 4-36 Round floating product 4-43 Round floating sum 4-28 Round normalize 4-59 Rounding 5-10 Set Ai 4-47,48,49 ,SO Set Bi 4-51,52,53 Set Xi 4-54,55,56 Transmit complement 4-41 Transmit word 4-41 Unpack 4-7 Unpacking 5-12 Index Write one word 4-62 W r i t e word t o CM 5-27 W r i t e X i n t o CM 4-57 A c t i v a t e c h a n n e l 4-97 Add 4-72,73 C e n t r a l r e a d 4-89 ,go C e n t r a l w r i t e 4-91,92 Channel f l a g 5-30 C l e a r channel f l a g 4-94 CM r e a d 5-27 D e a c t i v a t e c h a n n e l 4-98 E r r o r f l a g 5-30 I n s t r u c t i o n s , PP ( s e e a l s o i n s i d e f r o n t c o v e r ) Exchange jump 4-101 Function on c h a n n e l 4-99 I n p u t from c h a n n e l 4-95 Jump i f channel a c t i v e 4-87 Jump i f c h a n n e l empty 4-88 Jump i f c h a n n e l e r r o r f l a g c l e a r 4-88 Jump i f c h a n n e l e r r o r f l a g s e t 4-88 Jump i f c h a n n e l f l a g 4-94 Jump i f c h a n n e l f u l l 4-87 Jump i f c h a n n e l i n a c t i v e 4-87 Load 4-69,70 Load complement 4-69 L o a d / s t o r e R r e g i s t e r 5-27 L o g i c a l d i f f e r e n c e 4-75,76,7 7 L o g i c a l product 4-78 Long jump 4-83 Minus jump 4-86 Monitor exchange jump 4-101 Monitor exchange jump t o MA 4-101 Nonzero jump 4-85 Output from c h a n n e l 4-96 Pass 4-100 P l u s jump 4-86 Replace add 4-80,81 Replace add one 4-80,81 Replace s u b t r a c t one 4-82 Return jump 4-84 S e l e c t i v e c l e a r 4-75 S t o r e 4-71 S t o r e R r e g i s t e r 5-27 S u b t r a c t 4-74 U n c o n d i t i o n a l jump 4-84 Zero jump 4-85 Integer arithmetic I n t e g e r d i v i d e 5-13 I n t e g e r m u l t i p l i c a t i o n 5-13 I n t e g e r d i f f e r e n c e i n s t r u c t i o n 4-8 I n t e g e r d i v i d e 5-12,13 I n t e g e r m u l t i p l i c a t i o n 5-12,13 I n t e g e r sum i n s t r u c t i o n 4-8 I n t e r PP communications 5-28 I n t r o d u c t i o n 1-1 IOU C h a r a c t e r i s t i c s 1-5 CM a c c e s s 2-28 F u n c t i o n a l d e s c r i p t i o n s 2-22 1 / 0 c h a n n e l s 2-27 I n t e r n a l a d d r e s s a s s i g n m e n t s 5-59 Maintenance c h a n n e l 2-28 Major system component d e s c r i p t i o n s P e r i p h e r a l p r o c e s s o r (PP) 2-22 P e r i p h e r a l p r o c e s s o r s , see PPs Real-time ' c l o c k 2-27 R e c o n f i g u r a t i o n 3-9 Two-port m u l t i p l e x e r 2-28 IS1 1-11 2-22,27 Job mode, s e e CYBER 1 7 0 j o b mode Jump i n s t r u c t i o n 2-8; 4-87,88 Jump t o B i n s t r u c t i o n 4-38 Jump t o K i n s t r u c t i o n 4-10,11,12,13 K R e g l s t e r 2-26 Keyboard 5-38 Keyboard c h a r a c t e r c o d e s K1 r e g i s t e r 2-6 K2 r e g i s t e r 2-6 5-38 L r e g i s t e r 2-6 Large s c a l e i n t e g r a t i o n , s e e LSI 1-2 L e f t s h i f t i n s t r u c t i o n 2-3; 4-18,19 L e f t s h i f t nominally i n s t r u c t i o n 2-3 Load complement i n s t r u c t i o n 4-69 Load i n s t r u c t i o n 4-69,70 Load R r e g i s t e r i n s t r u c t i o n 4-69 L o g i c a l d i f f e r e n c e i n s t r u c t i o n 2-2; 4-23,76,77 L o g i c a l d i f f e r e n c e of X w i t h complement of X i n s t r u c t i o n 4-24 Logical product i n s t r u c t i o n 2-2; 4-24,25,78 L o g i c a l sum i n s t r u c t i o n 2-2; 4-22 L o g i c a l sum of X w i t h complement o f X i n s t r u c t i o n 4-23 Long-add i n s t r u c t i o n 2-6 Long jump i n s t r u c t i o n 4-83 Lookahead purge c o n t r o l 5-13 LSI 1-1 I Index MA r e g i s t e r 2-14 MAC, s e e Maintenance a c c e s s c o n t r o l Yainframe c o n f i g u r a t i o n 1-1 Maintenance a c c e s s c o n t r o l 2-1 Maintenance channel 2-28; 5-52 Maintenance channel g e n e r a t o r 2-16 Maintenance channel programming 2-21 Maintenance c h a n n e l 5-52 MCH c o n t r o l words 5-55 MCH f u n c t i o n words 5-53 Major system component d e s c r i p t i o n s CM 1-9 CP 1-6 I O U 1-11 System c o n s o l e 1-1 1 Master c l e a r (07XX) 5-50 MCH c l e a r LED (Opcode 3) 5-55 MCH c o n t r o l words 5-55 MCH c l e a r LED (Opcode 3) 5-55 MCH e c h o (Opcode 8) 5-57 MCH programming f o r h a l t l s t a r t (Opcode 01 1) 5-55 MCH programming f o r m a s t e r c l e a r l c l e a r e r r o r s (Opcode 617) 5-57 MCH programming f o r r e a d I O U s t a t u s summary (Opcode C, IOU o n l y ) 5-5 7 MCH programming f o r r e a d l w r i t e (Opcode 4/ 5) 5-56 MCH echo (Opcode 8) 5-57 MCH f u n c t i o n words 5-53 MCH programming f o r h a l t l s t a r t (Opcode 01 1) 5-55 MCH p r o g r a m i n g f o r master c l e a r l c l e a r e r r o r s (Opcode 61 7) 5-57 MCH p r o g r a m i n g f o r r e a d I O U s t a t u s summary ( Opcode C , I O U o n l y ) 5-57 MCH progrsmming f o r r e a d h i t e (Opcode $15) 5-56 MCH , s e e M,\intenance channel Memory, s e e CM MF, s e e CYBER 170 monitor f l a g Minus jump i n s t r u c t i o n 4-86 Monitor a d d r e s s r e g i s t e r , s e e MA r e g i s t e r Monitor exchange jump i n s t r u c t i o n 4-40,10 1 Monitor exchange jump t o MA i n s t r u c t i o n 4-101 Monitor f l a g , s e e CYBER 170 monitor f l a g Monitor mode, s e e CYBER 170 monitor mode Move d i r e c t Compare/move a r i t h m e t i c 5-1 3 Move d i r e c t i n s t r u c t i o n 2-6; 4-43 Move i n d i r e c t Compare/move a r i t h m e t i c 5-13 Move i n d i r e c t i n s t r u c t i o n 2-6; 4-43 1-11; 2-22.27 Nonstandard o p e r a n d s 5-8 Nonzero jump i n s t r u c t i o n 4-85 Normal jump i n s t r u c t i o n sequence Normalize i n s t r u c t i o n 2-3 ; 4-58 Normalized numbers 5-10 NIO 2-8 0 Operand r e g i s t e r s , s e e X register Operating i n s t r u c t i o n s 3-1 Operating modes CP 4-4 Operating p r o c e d u r e s 3-7 Operating R e g i s t e r s A 2-11 B 2-11 X 2-9 Output d a t a 5-51 Output i n s t r u c t i o n 4-96 Over r u n ( b i t 54) 5-48 Overflow 5-7 P r e g i s t e r 2-11,13,25; 5-3 Pack i n s t r u c t i o n 2-3; 4-6 Packing 5-5 P a s s i n s t r u c t i o n 4-60,100 P e r i p h e r a l p r o c e s s o r (PP) 2-22 P e r i p h e r a l p r o c e s s o r s , s e e PPs P h y s i c a l c h a r a c t e r i s t i c s 1-1 P l u s jump i n s t r u c t i o n 4-86 P o p u l a t i o n c o u n t i n s t r u c t i o n 2-4; 4-64 P o r t bounds r e g i s t e r , s e e CM, Bounds r e g i s t e r P o r t s and p r i o r i t i e s 2-18 Power-on and power-off p r o c e d u r e s 3-7 PP 2-22 PP and b a r r e l r e c o n f i g u r a t i o n examp (RP=O) 3-12 PP and b a r r e l r e c o n f i g u r a t i o n examp ( W 2 ) 3-13 PP CM read i n s t r u c t i o n s 5-27 PP CM w r i t e i n s t r u c t i o n s 5-27 PP d a t a format 4-67 PP i n s t r u c t i o n d e s c r i p t i o n s 4-68 PP i n s t r u c t i o n f o r m a t s 4-66 PP i n s t r u c t i o n s PP d a t a format 4-67 PP i n s t r u c t i o n d e s c r i p t i o n s 4-68 PP i n s t r u c t i o n f o r m a t s 4-66 Index PP relocation register format 4-68 PP memory 2-27 PP memory addressing by PPs Direct 12-bit address 5-26 Direct 18-bit operand 5-25 Direct 6-bit address 5-26 Direct 6-bit operand 5-25 Indirect 6-bit address 5-26 PP numbering 2-26 PP programming 5-25 Channel operation 5-30 CM addressing by PPs 5-25 CM read/write instructions 5-27 1/0 channel communications 5-28 I/O transfers 5-34 Inter PP communications 5-28 PP memory addressing by PPs 5-25 PP programming timing considerations 5-30 PP programming timing considerations 5-30 PP read terminal data (OlXX) Data character (bits 56 63) 5-48 Data set ready (bit 52) 5-47 Data set ready (DSR) and data carrier detector (DCD) (bit 53) 5-48 Framing or parity error (bit 55) 5-48 Over run (bit 54) 5-48 PP registers A 2-25 K 2-26 P 2-25 Q 2-26 R 2-25 PP relocation register format 4-68 PP write output buffer (02XX) 5-48 Prefetch of instructions, see Instruction lookahead Program address register, see P registers Programming CP 5-1 Real-time clock 5-45 Two-port multiplexer 5-45 Programming considerations 5-50 Input data 5-51 Output data 5-51 Programming example 5-41 Programming information 5-1 Programming timing considerations 5-43 Publication index 6 - Q Register 2-26 Quadrant select 2-17 R Register 2-25 RAC register 2-12,21; 5-3 M E register 2-14,21; 5-3 Read CM instruction 2-7; 4-57 Read free running counter instruction 4-64 Read one word from UEM instruction 2-7 Read one word instruction 4-62 Bead status summary (OOXX) 5-47 Real-time clock 2-27 Real-time clock programming 5-45 Reconfiguration examples 2-21; 3-6 Reconfiguration switches 3-3 Reference address for CM register, see RAC register Reference address for UEM register, see RAE register Register full/empty flag 5-31 Registers A 2-11,25 B 2-11 CP 2-9 CP Operating 1-7 CP Support 1-7 C1 2-6 C2 2-6 EM 2-12; 5-3 Exit mode, see Registers, EM Field length, see Registers, FLC and FLE Flag 2-13 FLC 2-12,21; 5-3 FLE 2-14,21 K 2-26 K1 2-6 K2 2-6 L 2-6 MA 2-14 Moai tor address register, see Register, MA Operating 2-9 P 2-11,25; 5-3 Program address, see Register, P Q 2-26 R 2-25 RAC 2-12,21; 5-3 RAE 2-l4,2l; 5-3 Reference address, see Registers, . U C and RAE Support 2-6,11 X 2-9 Relocation register, see Register, R Replace add instruction 4-80,81 Replace add one instruction 4-80,81 Replace subtract one instruction 4-82 Index Request to send and data terminal ready 5-51 Return jump instruction 2-8; 4-37,84 Return jump instruction sequence 2-8 Right shift instruction 2-3; 4-20,21 Right shift nominalJy instruction 2-3 Round floating difference instruction 2-4; 4-31 Round floating divide instruction 2-4; 4-36 Round floating product instruction 2-4; 4-33 Round floating sum instruction 2-4; 4-28 Round normalize instruction 2-3; 4-59 Rounding 5-10 Row address select 2-17 RTS, see Request to send SECDED 2-19 SECDED generator 2-16 Selective clear instruction 4-75 Set A instruction 4-47,48,49,50 Set Ai instruction 2-5 Set B instruction 4-51,52,53 Set Bi instruction 2-5 Setlclear data terminal ready (04~~) 5-49 Set/clear request to send (05XX) 5-50 Set operation mode to terminal (03XX) 5-49 Set X instruction 4-54,55,56 Set Xi instruction 2-5 Shift instruction 4-75 Shift sequence 2-3 Single error correction/double error detection, see SECDED Slot, see Barrel and slot Software errors 5-21 Standard addressing mode 5-24 Store instruction 4-71 Store R register instruction 4-71 Subtract instruction 4-74 Support registers 2-6 C1 register 2-6 C2 register 2-6 EM 2-12 nc 2-12 FLE 2-14 K1 register 2-6 K2 register 2-6 L register 2-6 MA 2-14 P 2-11 RAC 2-12 RAE 2-14 Switches Deadstart 3-1 CM reconfiguration 3-3 System console 1-11 Keyboard 5-38 Major system component descriptions 1-11 System console programming 5-38 Data display 5-38 Programming example 5-43 Programming tirmlng considerations 5-43 System publication index 6 Terminal deselect (6xxx) 5-46 Terminal select (7mnr) 5-46 Test and set flag instruction 4-94 Timing considerations instruction, see Execution timing Transmit complement instruction 2-2 Transmit complement of instruction 4-41 Transmit instruction 2-2 Transmit X instruction 4-41 Two-port multiplexer 2-28 Two-port multiplexer operation Master clear (07XX) 5-50 PP read terminal data (OlXX) 5-47 PP write output buffer (02XX) 5-48 Read status summary (OOXX) 5-47 Set/clear data terminal ready (04XX) 5-49 Set/clear request to send (05XX) 5-50 Set operation mode to terminal (03XX) 5-49 Terminal deselect (6XXX) 5-46 Terminal select (7XXX) 5-46 Two-port multiplexer programming Programming considerations 5-50 Request to send and data terminal ready 5-51 UEM 2-7,14; 4-16,17 Description 1-4 Field length register, see FLE register Reference address register, see RAE register UEM address 4-17 UEM enable flag 4-16 Unconditional jump instruction 4-84 Underflow 5-7 Unified extended memory, see UEM description Unpack instruction 2-3; 4-7 Index Word Bit numbering 5 Write CM instruction 4-57 Write into CM instruction 2-7 Write one word instruction 4-62 Write one word to UEM instruction z 2-7 Zero jump instruction 4-85 MANUAL TITLE: PUBLICATION NO.: CYBER 840A, 850A, 860A, 870A Computer Systems CYBER 170 State Hardware Reference Manual 604 63 560 REVISION: C NAME: COMPANY: STREET ADDRESS: CITY: STATE: ZIP CODE: This form is not intended to b e used as a n order blank. Control Data Corporation welcomes your evaluation of this manual. Please indicate any errors, suggested additions or deletions, or general comments below (please include page number references). 0 Please Reply No Reply Necessary NO POSTAGE STAMP NECESSARY IF MAILED IN U.S.A. FOLD ON DOTTED LINES A N D TAPE FOLD FOLD NO POSTAGE I BUSINESS REPLY MAIL 1 I FIRST CLASS PERMIT NO 8241 MINNEAPOLIS MN POSTAGE WILL BE PAID BY ADDRESSEE 3CONTROL DATA Technology and Publications Division ARH219 4201 North Lexington Avenue Saint Paul, MN 55126-6198 I NECESSARY IF MAILED IN THE UNITED STATES -
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.5 Linearized : No Page Count : 260 Page Mode : UseOutlines XMP Toolkit : XMP toolkit 2.9.1-14, framework 1.6 About : uuid:4d728e84-f2f9-421e-8f8e-6125866d8751 Producer : Adobe Acrobat 6.02 Paper Capture Plug-in Modify Date : 2004:11:27 14:35:10-06:00 Create Date : 2004:11:26 14:28:21-06:00 Metadata Date : 2004:11:27 14:35:10-06:00 Creator Tool : Adobe Acrobat 6.02 Document ID : uuid:7de2f398-e4dd-422a-a997-57eb68e6574a Format : application/pdf Creator : Adobe Acrobat 6.02EXIF Metadata provided by EXIF.tools