DEC 11 H40SA A D_PDP 11_40_System_manual D PDP 40 System Manual

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PDP-11/40 system manual

DEC-II-H40SA-A-D

PDp...11/40 system manual

digital equipment corporation maynard. massachusetts
It

TABLE OF

COtTTE~·.rrrS

Paqe

CHAPTER 1

INTRODUCTION

1"1

Scope

1 ... 1

1 .. 2

System Components

1 ... 3

1 ,,3

Functional Descrintion

1 .. 1 IJ

1 .. 3 .. 1

Unibus

1 ... 11

1.3 .. 2

KD11-A Processor

1 ... 1 4

1 ,,3 .. 3

KY11 ... n Pro,]rammer's Console

1 -1 7

1 .3.4

r,fF 11

1 ... 18

1 .. 3 .. 5

Optional

1 .. 3 .. 6

DEC"Jr iter 8: 7 8 ten

1 .. 3 .. 7

DL11 A.synchronous Line

.. L Core f1er:lory
~\ll.el'lory

Systers

1-2n
1-2~

Inter~a.ce

1 .. 3 .. 8

1 .. 2A
1-")r:

Docu~cntatinn

1 .. 4

Applicahle

1 .5

Engineerin~

CHAPTER 2

INSTALLATION

2 .. 1

Sco!Je

2-1

2 .. 2

Site Preparation

2-3

2.2.1

Physical Dimensions

2-L1

2.2 .. 2

Fire and Safety Precautions

2-7

2 .. 2.3

l:Dvironnental Pequirenoents

2-9

Drawings

1 ... 28
1 .. 38

iii

TABLE

COIJTE~TTS

(Cont)

-- .. 1 0

2 .. 2 .. 3 .. 1

.-,

2 .. 2 .. 3 .. 2

Air Conditionir0

2.2 .. 3 .. 3

Accus tical

Dar~pin (.1

2 .. 2,,3.4

2- 1 1
2 ... 1 2

7- 1 3
Special ':ountinC} Condi tioDS

2- 1 4

2 .. 2 .. 3 .. 6

Static Electricitv

......'

2 .. 2 .. 4

ElectricRl

.. 1

~co'uire11e:nts

2- 1 (,

Installation Proceaures

2- 1 7

2 .. 3 .. 1

1 ... 1 8

Inspection

2-2 1

2 .. 3 .. 3

Cabinet Installation

2 .. 2 3

2 .. 3 .. 4

AC Power Connections

2- ..:.'")r-:)

2 .. 3 .. 5

Intercabinet Connections

,? - 27

2 .. 3 .. 5 .. 1

unibus Connections

Renate

2- '<9

PO";'ler

Connections

Grcund Stru.ppinS

Ir:::3' talla. tion

Initial

2 ... 3 r)

2-3 1

2,,3 .. 7
.. Jilt> U

to.)

2 .. 3 .. G

...:;,

'")()
~

Po~er

'iJ~,r if iea. tiC'~:

Turn-On

2 ... 1 3
2-/1.,1

., .. ~ G
Custo~-~r""~

Z\ccertance

2- 50

TABLE OF CO:NTENTS (Cant)

Paqe

CHAPTER 3

SYSTEH OPERATION

3.1

Scope

3,,2

KY11-D Programmer's

3 .. 3

DEC'\·vr iter

3-18

3.4

Teletype

3-21

3 .. 5

Basic Operation

3 .. 27

3.5 .. 1

Power On

3-2n

3 .. 5.2

Basic Console Control

3 ... 30

3.5 .. 3

~·lanual

3 ... 34

3.5.4

Automatic Loading

3-41

3.5.5

Running Programs

3-48

3.6

Basic Programmin0

3 .. 50

CHAPTER 4

PPOCESSOR INSTRUCTIO-:·JS l\_!TD ()P'!'IONS

4. 1

Scope

4-1

4.2

Ins·truction Set

4-7

4 .. 2 .. 1

A.ddress 1'1odcs

4-4

4.2.2

Basic Instruction Set

ti-7

4 .. 2.3

Extended Instruction Set

4 .. 21

4 .. 3

Processor

4 .. 3.1

KE11-E Extended Instruction Set
(EIS)

3 .. 1
Consol~

3-2

4 .. 24

0~tions

Option

4-2G

'T'ABLF

cOnTET,T'T.'S

(Cont)

Page

4 .. 3.2

KE11-F Floating Instruction Set

(FIS) Option
4 .. 3 .. 3

KJ11-A Stack Limit Register Option

4 .. 14

4 .. 3 .. 4

KT11 ... D !·1crnory r·1anage:r.1ent ODtion

4 ... 37

4 .. 3 .. 5

1('>111 .. L Line Frequency Clocl.- O!')tion

4 ... 41

4 .. 3 .. 6

K~111

4 ... 43

4 .. 3,,7

Small Peripheral

4 .. 4

f ..~eE1ory Q;:>tion s
?·1~·1f

=A ~'l(}intenance l\.~odule Option

1 1 .. L Core

~··1F 1 1

... L Core

·. .1E 1 1 ... L Core
!, ..yj.~ 1 1 . . s

Controll~r

Slot

~1e!:1()ry
[.'~r;:~rl0r

l\~0:D.ory

Core nCflory

CHl\PTEP 5

T.1I'JIBt'S F!.'TD SYSTEIJT OPTIONS

5 .. 1

~)copc

S-l

Onihus
5,,3

Unibus Ontions

5 .. 3 .. 1

PC11 TIi7h-Spf'ed Paner"'Tapp RnCloer/Punch

5 .. 3 .. 2

LP11

5 .. 3 .. 3

CP 11 Card Reacier

5.3 .. 4

TC11/TU5G

5 .. 3 .. 5

Tt"'1/'Tt: 1 () DECD2 gtape S~tS tef'

5 .. 8

T
.
__ ,Inc:
Printer

5 .. 11

DECtape Syst(''l

'Ii

5-1 3
5 ... 1 S

TABLE OF CG:NTENTS

(Cant)

Pa'}c

Me~orv

5 .. 3 .. 6

RC11/RS64 DECdisk

5 .. 3 .. 7

RF11/RS11 Disk

5 .. 3 .. 8

RK11-C DECpack Disk

5 .. 3 .. 9

VT01 Storage Display

5 .. 3.10

VR01 Oscilloscope

5 .. 3 .. 11

VR14 Point Plot Display

5 .. 24

5 .. 3 .. 12

VT05 Alphanuneric Display

5-2S

5 .. 3 .. 13

Rr:'C01 DEClink Terminal

5 .. 26

5.3 .. 14

Conu~unications

5-27

5.3.15

P·~FC11

5 .. 3.16

AD01-D Analog-to-Diqital Conversion Subsystem

5 ... 31

5.3.17

AP. . 11 -D Digi tal- to-Analog Conversion SuhsvsteT'1

5-33

CIIl\PTER 6

RQDIPr"1ENT .1\,10UNTING AND

6 .. 1

Scope

6-1

6.2

System Mounting Box

h-?

6.2.1

Processor Module Allocations

f-4

6.2.2

MeT:l.ory i-1odule l\.llocations

6-5

6.2.3

Programner's Console

6.3

Cabi net and Sys ten

6 .. 3 .. 1

System Cabinet

6-8

6.3.2

System Configuration

6-9

5-1

Syste~

5 ... 18

Cartri~0e

System

5 .. 20

5-22

D~splay

Options

Lo\,,-Level A.nalng Input Subsystef1

5-29

Por~]BP

Mountin~

1',~oun ti nrr

vii

5-23

6-(-

6-7

TABLE OF CONTENTS

(Cant)

Paae

6 .. 4

Power Control System

6 .. 13

6 .. 4.1

860 Power Control Unit

6 ... 14

860 Physical Description

Description

6 .. 4.1 .. 2

8En Functional

6" 4 .. 1 .. 3

8GG Circuit Desc rintion

6 .. 4 .. 2

8 (~1

6 .. 5

P8P11/40 Basic :?OHer Sunnly

() .. 5 .. 1

H7 L12 Bulk PO,'JPr Sunnl:!

6 .. 5 .. 1 .. 1

+1 S"V and +8V of the H742 5uY)n1v

6" 5 .. 1 .. 2

Cloc}: nutnut of tILe II7.12 Sunnlv

f.5.1 .. 3

p.e

(:.5 .. 2

Ii7 4 4

6,,5 .. 2.1

II744 Re'Jula tor Cireui t

(, .. 5 .. 2 .. 2

+5\7 ()v0'rcurrent Scnsinq Circuit.

6 ... 17
6 ... 1 9

Power Control Uni t

6 ... 21

6-27

LO and DC LO Circui ts

+5']

Rc r plla tor

+5'1 Overvol tage Cro\·vbar

the 11744

f-33

Circui t of: the II7/14

6-34

0 1=

II745 .. 15V Ret]ula tor

h-35

6 .. 5,,3 .. 1

.. 1 5\1 Rctjula tor C).rcui t of the II74 5

6 .. 3 h

2 .. 5 .. 3 .. 2

-15V Overcurrent Sensing Circuit

6 .. 5 .. 3.,3

... 15\7 Overvolta.ge

of the H74S

6 .. 5 .. 4

QC Power Distribution

6 .. 5 .. 5

'l0.intenance of Fovror

viii

S~lS

tel'

the H745

6-42

TABLE OF CONTENTS

(Cant)

Page

CEAPTEP. 7

GENE RAL

7 .. 1

Scope

7-1

7 .. 2

Overall Maintenance Techniques

7 ... 2

7 .. 2 .. 1

Kno\vledge of Proper, Hard\'lare Operation

7-3

7.2.2

Detection and Isolation of Error Condition

7 ... 5

7.2",3

Means of

7,,2 .. 4

Di0ital Field Service

7.3

Maintenance Equipment Required

7-9

7 .. 4

Preventiv~

7 ... 13

7 .. 4 .. 1

Physical Checks

7 ... 14

7 .. 4.2

Electrical Checks and AdjustPlents

7 ... 1f)

7 .. 4 .. 2.1

Voltage Regulator Checks

7=17

7.4.2.2

860 Power Control

7 .. 1C)

7.3 .. 2 .. 3

AC Power Connector Recertacles

7-20

7 .. 4 .. 3

ASR33 Teletype

7 ... 21

7 .. 4 .. 3 .. 1

Preventive rv1aintenance Checks

7-21

7 .. 4 .. 3 .. 2

Lubrication

7-22

7.4.4

LA30 DEC\\7r iter

7-24

7.4.4.1

Preventive

7.4 .. 4.2

Cleaning Procedures

7 ... 26

7 .. 4 .. 5

PCOS High-Speed Paper-Tape Reader/Punch (option)

7 .. 28

7.4.5.1

Mechanical Checks

7-29

~1.AINTENl\NCE

Repairin~

the Error Condition

Haintenance

rc~aintenance

Schedule

7-7

7-24

TABLE OF CONTENTS

(Cont)

Page

7 .. 4 .. 5 .. 2

Electrical Checks

7 ... 30

7.5

Usc of !'Todule Extenders

7 ... 31

7 .. 6

PDP ... 11 /40 PO\'ler Sys tem I-1a i n tenance

7 ... 32

7 .. 6 .. 1

Cireui t Tr"acing

7-33

7.6.2

Voltage REgulator Tests

7.6.3

Voltage Regulator Test

(Off"'Line Pepair)
(~fter

REpair)

7 ... 34
7 ... 39

ILLUSTPJ..TIO'NS

2 ... 1

PDP~11/40

2 ... 3

DeCo Cable Harness

2 .. 4 5l\

3 .. 1

PDP-11/40 Programmer's Console

3 ... 4

3 .. 2

DECwriter Controls

3 ... 19

3.,,3

Teletype Controls

3-22

3 ... 4

Flowchart of Procedure for Running PrograMs

3 ... 37

4 ... 1

Douhle and Single Operand

4 ... 6

Connector

2 .. 16l'~

~ddress

Modes

Instruction Formats
PDP-11/40 Svstem Cabinet

6 ... 3]\.

E.. 2

PDP -11 /40 r-':ountinC] Bo~-:

6 ... 3R

6 ... 3

~odule

Basic
6 .. 4

Allocation - KD11-A Processor,

(*) and Options

>1oe]ule fl,lloca tion nasic

(SJ111 -FC)

(*)

6 .. 4F..

r,'tF11 -L

and Optional

ne"~ory,

1'.'F·/f11"'L~

ILLUSTPATIONS

(Cont)

Page

6.,.5

Typical Hultiple Cabinet Systen Cinfic;ura.tion

h-10A

6- 6

Power Control Interconnection

() -1 6A.

6 ... 8

PDP-11/40 Power System Block

6 ... 9

PDP-11/40 Power Supply

6 ... 1 0

Simplified

Dia~ram

6 ... 22A

Diagra~

6 .. 22B

'of Precision Voltage

Regulator E1

6 .. 30A

6 ... 11

DC POv7er Distribution

6 ... 41A

7 ... 1

Voltage Requlator Test Bench Source and

7 ... 2

Typical Vol tage Regulator OutDUt .,.oJavefo:rms

Loa~s

7-3 SA
7 .. 4()P,

CHAPTER 1

1.1

INTRODUCTION

SCOPE

This manual, the PDP11/40 System Manual, provides a general
introduction to the PDPll/40 system and includes sections on
installation, operation, the instruction set, options, mountinq
and power, and maintenance. This overview is supnleFented with
references to other manuals in the PDP11/40

seri~s

for detailed

explanations.

The PDP11/40 manuals provide the user with the theorv of operation
necessary to understand, operate, and maintain the PDP11/40
These manuals reference associated engineerinq

drawin~s,

Syste~.

hoth

are listed in Table 1-2. Please note that the associated drawinns
are separate volumes and documented by their Drawin0 Directory
number (not the manual number). Both volumes are necessary.

The level of discussion in each manual assumes that the reader
is familiar with basic digital computer theory_ The naintenance
philosophy presents information about normal systen onr:rat.inn
and enables the user to recogni ze trou})] e svnntons ana to oerforIll
necessary corrective action. Eoch in(!ividual manual cnntairs theorv
of opera tien, diaqraf..ls, mainte-nance trchnirnu:.;s.

Loc~ic

drar,}iprrs for

the snecif ic component cov8red are contaiJled in sr:nar0. te volures.

1 -1

This chapter describes the basic systen components (paraqraph 1.2)
and provides a functional description of the overall PDP-11/40 system
and each of its major components

(p~ragraph

the chapter covers applicable docuMents

1.3). The

(par~graph

re~ainder

1 .4),

en~ineerjn0

drawings (paragraph 1.5), and termirologv (paragraph 1.6).

1-2

1.2

SYSTEM COMPONENTS

The PDP-11/40 System consists of six hasic connonents: processor,
programmer's console, core memory,

DE~writcr

control, power supply, and mounting

b0~.

with assnciaterl

Possihle

v~ri2tirn

this basic system are listed in Table 1-1.

options and peripherals added to the

~asic

PDP-11/40 System

are covered in separate manuals delivered "tvi th the svstern..
Manuals are included only for those options sppcifically ordered
with an individual system.

(

1- 3

Table 1-1
possible PDP-11/40 Variations

~"1a

j or CnmpC"'D P-11 t

*KD11-A Processor

PossihJe

Vari~ti0ns

tIo 'Jar ia ti ons in has ic processor. !lo~·..''''''·'Trr~; a D-:r
t,

the fol1owinq internal procpssrT

0D~inns

he incluc1t?c1:
l':E11-E E:xtf-:rdec Instruc+:.ion Set

(I'I~~)

KE11-F Ploatinn Instruction Set

(PTS)

K,T11 -l\
T~:"q

St2.CJ~

Lir1i t

Re0istr::r

1-1\ !J1ainten,"::)nce !,-1onule

KT11-0 Menory

M~nane~cnt

l-\\\!11-L Line Frequency

I'·~one

ConsoJe

1-4

(consnJ.0.)

Inter-runt Clock

c~n

Table 1 -1

(Cont)

Possible PDP-11/40 variations

Hajor Component

Core .Memory

possible Variations

8K core

MM11-L

me~ory,

900 ns cycle time,

350 ns internal access time

MM11-L memory plus backplane,

*MF11-L

space exists for two additional
[-1M11 -Ls

MM11-L memory plus backplane,

ME11-L

mountina box, and power supply
(complete memory system)

!v1M 11

-S

Ml'111 -L

memory, interleaved, plus

backplane (may be used for
expansion of memory ahove 24K)

1-5

Table 1-1

(Cant)

Possible PDP-11/40 Variations

Hajor Component

Possible Variati0ns

Core Memory (Cant)
f\1ep10rv

SHS

te::'s

COyn,D2

t ih 1 e '\.Vi th the

PDP-11/20 mav also he used in the
PDP-11/4n.

Th~se

Me~ories

are:

111 -E

4K h'1 1 F. hit

-F

4K bv 1 (-) hit

;'~!..

1\-~!,-111

4K bv 1 6 bit,

fl U-1!1 1 - FP

"Ii th Darity
~'1M 1 1 -

1K hv 1 E bit
2K hv 1 6 bit

T'.1Y':111 - J

These
or

~e~ories

powere~

cannot he mounted within

within thr basic

PDP11/40 nountin0 h(1x.

1-6

Table 1-1

(Cont)

Possible PDP-11/40 Variations

Major Component

DEC\vri ter

Possihle Variations

**LA30

Standard 97-character kevhoard.
Optional 128-character kevhoard
available.

(LA30-S is a serial

DECwriter and is controlled by
a DL11 control; LA30-P is a
parallel DECwriter and is
controlled by an LC11 control.)

Teletype Unit

**33 ASR

Each unit is available in

33 KSR

120V or 240V models.

35 ASR
35 KSR

Input Terminal

DL11-A

Teletype,

Control

DL11-B

EIA terminal control

DL11-C

Teletype, display, or LA30-S control

DL11-D

ETA

DL11-E

Dataset control

1-7

dis~lav,

ter~inal

or LA3n-s control

control

Table 1-1

(Cont)

Possible PDP-11/40 variations

Major Component

Possihle

VariAtion~

KL11-B

Sinilar to KL11-A. Differ

KL11-C

nriparily in baud rates as

KL11-E

descrihed in KL11 manual.

KL11-F

LC11

Power Sys tern.

LP30-P DECwriter control

*H742 Power Supply
1 20V or 24

ov,

(may he junnered for either

5 n/ 6 n Hz)

*H744 +5\1 rec::ulator,

25A (two nor:rlallv

supplied 'i'7i th basic syste:rli addi tional
uni t may be included to hannle svsterrt
options)

*H745 -15\1 regulator,

1-8

10A (two)

Table 1 -1

(Cont)

Possible PDP-11/40 variations

possible Variations

Major Component

*860 Power Control - mounted in top of
cabinet. Two versions available:

860A - requires 120V input
860B - requires 240V input

Mounting Box

*BA11-FC Mounting Box

An asterisk indicates that this is the normal configuration
shipped with the basic machine, unless otherwise specified
by the customero

Either the LA30 DECwriter or the Teletype unit may be used as
the basic PDP-11/40 System input/output device.

1-9

103

Fll1CTIONAL DESCRIPTION

The PDP-11/40 is a 16-bit, general-purpose, parallel-logic,
microprogrammed computer using 1- and 2-address instructions
and 2s complement arithmeticu The system contains a variable
instruction length process6r, which directly addresses all of
core memory. All communication among system components
(including processor, core memory, and peripherals)

is performed

on a single high-speed bus, the Unibusc Because of the bus concept,
all peripherals are compatible, and device-to-device transfers
can be accomplished at the rate of 2,500,000 words-per-secondo All
peripherals are in the basic system address space; therefore,
all instructions are I/O instructions. All system components
and peripherals are linked by the Unibus and power connectors.

Subsequent paragraphs present a brief functional description
of basic PDP-11/40 System componentso A functional description
of all processor options is presented in Chapter 4 of this manuale

1-10

1 .. 3" 1

'Unibus

The Unibus is a single high-speed bus that provides communication
between system components. The Unibus, with bidirectional data,
address, and control lines, allows data transfers between all
units on the bus with control of the bus an important factor in
these transfers. The fixed repertoire of bus operations is flexible
enough fdr speed and design economy, yet provides a fixed specification
for interfaces" The asynchronous nature of these operations also
eases design and operation" The repertoire of bus operations is:

DATI, DATIP, DATO, DATOB - data operations
INTR, PTR (BR, NPR)

- control operations

Full 16-bit words or 8-bit bytes of information can be transferred
on the bus between the master and slave. The DATI, DATIP operations
transfer data into the

mast~r;

the DATO, DATOB operations transfer

data out of the master. When a device is capable of becoming bus
master and requests use of the bus, it is generally for one of
tv.TO

purposes:

to make a direct memory access

(DMA) transfer of

data directly to, or from, another device without processor
intervention; or to interrupt (INTR) program execution and
force the processor to branch to a specif ic address
interrupt service routine is located

~.,here

Bus control is obtained under a non-processor request (NPR)
for the direct memory access (DMA) or under a bus request (BR)

1 -11

for an interrupt (INTR)

A device can perform a

acquiring bus control by a BR:
lower priority

Dr~,

after

bus control acquisition is at a

Requests for the bus can be Made at any tiMe on the bus request
(BR) and non-processor request (NPR)

lines. Transfer of bus control

from one device to another is made by the processor priority
arbitration logic which grants control of the bus to the device
having the highest priority. The NPP's are serviced before and
directly after Unibus data cycles, in addition to specific times
during WAIT or TRAP sequences. The BR 9 s are serviced at the end
of the instruction if the requesting priority exceeds that of the
processore

The processor has a special role in bus control operations as
it performs the priority arbitration to select the next bus
master

The processor assumes bus control when no other dev ice

has control.

The Unibus originates in the processor with the Internal Unibus
and Terminator module (M981)

that carries the Unibus from the

processor to the next system unito All 56 Unibus signals and
17 grounds are carried in this one module

In addition, a 120-conductor

Flexprint cable may be used to connect system units in different
mounting boxes or to connect a peripheral device removed from
the mounting boxo

1-12

A complete description of the Unibus, including specifications,
is presented in the PDP-11 Peripherals and Interfacing
Handbook.

1-13

KD11-A Processor

The KD11-A Processor decodes instructions, modifies data, makes
decisions, and controls allocation of the Unibus among external
devices. The processor contains eight hardware programming
registers which are used 'as arithmetic accumulators, index
register, autoincrement and autodecrement registers, and stack
pointer registersc Two registers are specifically used for
the processor:s program counter (PC) and stack pointer (SP)

Because of the flexibility of hardware registers, address modes,
instruction set, and direct memory access, PDP=11/40 programs are
written in directly relocatable codes

The processor also includes

a full complement of instructions that manipulate byte operands,
including provisions for byte swapping. Either words or bytes may
be displayed on the programmer's console.

Any of the eight internal registers can be used to build last-in,
first~out

stacks. One register serves as a processor (or machine)

stack pointer for automatic

stacking~

This stack handling

capability permits save and restore of the program counter and
status word in conjunction with subroutine calls and interrupts.
This feature allows true reentrant codes and automatic nesting of
subroutines. Addition of the KJ11 Stack Limit Register Option
permits alteration of the stack overflow limit and provides both
warning (yellow) and fatal (red) stack error indications.

1-14

The Unibus is used by the processor and all peripheral devices;
therefore, there must be a priority structure to determine which
device becomes bus master. A device generally requests use of
the bus to make a nonprocessor trnnsfer of data directly to or
from memory, or to interrupt

progra~

execution and force the

processor to branch to an interrupt service routine. A
nonprocessor request (NPR) is granted by the processor at the
end of bus cycles and allows device-to-device data transfer$
without processor intervention. A bus request (BR) is granted
by the processor at the end of an instruction and allo\vs the
device to interrupt the current processor task. The entire
instruction set is then availahle for manipulating device registers.

The processor recognizes four levels of hardware bus requests;
each major level contains sublevels. Hany devices can be
attached on each major level with the device that is electrically
closest to the

processo~

given priority over other devices on the

same priority level. The priority level of the processor itself is
programmable within the hardware levels; therefore, a running
program can select the priority level of permissible interrupts.

Additional speed and power are added to the interrupt structure
through the use of the PDP=11/40 fully vectored interrunt schene.
With vectored interrupts, the device identifies itself, and a
unique interrupt service routine is automatically selected hy
the processoro This eliminates device polling, and permits

(

nesting of device service routines. The device interrupt

1 -1 5

priority and service routine priority are independent to allow
dynamic adjustment of system behavior in response to real-time
conditions ..

The address mapping of the system is dependent on the three
most significant bits of the 16 bits in the KD11-A processor
address for the basic processor. If these bits are all 1s, the
two most significant bits of the Unibus address are forced to
1 S; othervli se, the two mos t siqni f icant hi ts of the 18 - hi t
Unibus address are forced to Os. The KT11-D
Option coverts these

16~bit

Me~ory

Management

addresses into full 18-bit

physical Unibus addresses.

A detailed description of the processor is presented in the
KD11 Processor r·Ianual, DEC-11 -HKDAA ... A-D

1 -1 6

1 03" 3

KY11-D Programmer's Console

The KY11-D Programmer's Console provides the programmer

,.,i th

direct system interface. The console allows the user to start,
stop, load, modify, step, or continue a

progra~.

Console

displays indicate data and address as well as which device
is controlling the bus; thus, operations can be monitored.

The programmer's console interacts with the processor, with
microprogram control for the processor operation located in
the processor. The console contains only indicators (light
emitting diodes), switches, and the contact bounce filtering
circuits for the control switches. Console operation does require
certain Unibus operations through the processor:
and DATI for

EXM~o

DATO for DEP

For single-step operation, the processor

responds to a console bus request (CBR)

The CBR priority

supersedes all other BR priorities. Note that use of the KM11
Maintenance Console option provides further display of machine
states and allows single microstate stepping.

The programmer's console is mounted as the front panel of the
Bll.11 -FC mounting:, box and is connected to the processor by means

of two cables ..

Console operation, including descriptions of all controls and
indicators, is presented in Chapter 3 of this manual. Detailed
descriptions of console logic circuits are covered in the KD11
Processor i--1anual, DEC-11-HKDAA-A"'D ..

1 -17

1.3.4

MF11-L Core Memory

The MF11-L Core Memory used in the PDP-11/40 System is a random
access, coincident current, magnetic core, read/write

me~?ry

with a cycle time of 900 ns and an internal access tire of
350 nsu The memory consists of ferrite cores wired in a planar
3-D, 3-wire configuration that uses a shared sense/inhihit line.
The basic memory unit consists of the backplane and three
modules capable of storing 8192 (8K)

16-bit words. Provision

for additional memory is made by this 9-s1ot, 2-system unit
equivalent backplane. Two MM11-Ls, each consisting of three
modules providing 8192 (8K) words, can be added.

The core memory uses the Unibus for data transfers to and from
the processor and other devices; however, core memory is never
bus master. Because the memory is always a slave device, a
DATO or DATOB indicates information transferred out of the
master into the memoryo Because of the Unibus structure, the
memory can be directly addressed by the processor or any
other master device; every locatior. in core can function as
a true arithmetic accumulator.

The memory does not enter the priority structure because it is
never bus master. The master device, however, can reauest use of
the memory through either a bus request (HP) or a non-nrocessor
request

(~PR).

Because the memory is completely independent of

the processor, any master device can

perfor~

with memory without processor intervention.

1-18

direct data transfers

A detailed description of the memory is presented in the ME11-L
Core Memory manual, DEC-11-HMELA-A-D. Note that the ME11-L is
basically an MF11-L with the addition of a mounting box and power
supply ..

Note that the instruction timing specified for the PDP-11/40 System
applies only for the MF11-L and HM11-S memories. These memories
employ a special HSYN signal between the processor and the
memory housed in the same mounting box.

(
1-19

1 ,,3 .. 5

Optional Hemory Systems

There are two types of optional memory systems that may be
used with the PDP-11/40 System:
MM11 -L, and core memor ies used

core memories
\A]i

si~ilar

to the

th other members of the .

PDP-11 family ..

There are four memory systems similar to the MM11-Lo The prime
difference is packaging. These four memories are:

MM11-L

8K by 16 bit, 900 ns cycle time,
modules and stack only.

MF11-L

MM11-L memory plus backplane
accomodating three MM11-L memories
in a double system unit ..

!'1E 11 - L

Complete memory system consisting of
~U111-L

memory, backplane, mounting box,

and power supply.

MH11 -8

Ml'v111 -L memory singularly in a single
system uni t ..

There are five core rnemor ies designed for use v7i th the PDP 11/20
co

System that may be used, if desired, with the PDP-11/40 SysteP1
provided they are powered by H720 type power supplies . These
memories are:

1-20

MM11-E

4K by 16 bit, 1.2 us access time

MM11-F

4K by 16 bit, 950 ns access time

MM11-FP

an MM11-F with parity option included

MM11-H

1K by 16 bit, 950 ns access time

MM11-J

2K by 16 bit, 950 ns access time

Both the MM11-E and MM11-F memories may be expanded up to 28K
in 4K increments. Each 8K segment may be interleaved.

1-21

DECwriter System

The LC11 DECwriter System is a high-speed teletypewriter system
designed to interface with the PDP-11 family of processors to
provide both input (keyboard) and output (printer) functions
for the system. It can be used as the console input/output deviceo
The system can receive characters from the keybaord or can print
at speeds up to 30 characters per second in standard ASCII formats
The LC11 System consists of two distinct components:

an LA30

DECwriter and a DEC PDP-11 interface unit, which is referred to
as the LC11 Controller.

The LA30 DECwriter is a dot matrix impact printer and keyboard
for use as a full-scale hard copy I/O terminal

teletypewriter~

The keyboard is either 97 or 128 characters. The print set is
64 ASCII characters, 80 characters per line, 10 characters
per inch"

The LC11 Controller is the interface bet\\Yeen the DECwri ter and
the PDP-11 Unibus .. It controls data transfers bet\AJ'een the
DEC\.vriter and other devices in the system .. It also monitors
print status, indicates when the keyboard buffer is full,
and enables the interrupt logic ..

The LC11 controller consists of a single quad module that can be
mounted in the processor small peripheral controller slot. The
LA30 DECwriter is covered in detail in the LA30 DECwriter manual,

1-22

DEC=OOMLA30-DA and the LC11 is covered in the LC11 DECwriter
System manual, DEC-11-HLCB-D.

Note that the LC11 Controller is only used with theLA30-P
parallel \'\lord DECwriter. If an LA30-S serial \'\lord DECwriter
is used, it is controlled by the DL11 interface.

(
1 .. 23

1 .3" 7

DL11 Asynchronous Line Interface

The DL11 Asynchronous Line Interface provides an interface between
a communications device, such as a Telet"pe,
and the PDP-11/40
..~

Unibus. Serial information read or written by the device is
assembled or disasse@bled by the control for parallel transfer
to, or from, the Unibus

The control also formats the data from

the Unibus so that it is in the format required by the device.
The interface provides the flags that initiate these data
transfers and cause a priority interrupt to indicate the availability
of the deviceo The DL11 is used when a Teletype is used as a
system input/output deviceo It is also used with other types of
communications devices such as datasetse

The interface transfers da-ta via processor DATI and DATOB bus
cycles. Although a DATO can be used, normal operation consists
of a DATOB transfer because the device and the interface handle
byte, rather than '\vord I data

The interface can acquire bus control

by a bus request (BR) and is normally set at the BP4 priority
level. Because the interface operates by a means of an interrupt,
no non-processor request (NPR) can be made.

There are five available DL11 interface options (DL11-A through
DL11-E) in order to provide the flexibility needed to handle a
variety of terminals. For example, the user can select an option
for interfacing a Teletype or display keyboard, for handling
EIA data, or for handling dataset devices. In addition, depending

1-24

on the option used, the user has a choice of line speeds,
character size, stop=code length, and parity.

The DL11 interface consists of a single quad module. This
module contains address selection logic for decoding the
incoming bus address, an interrupt control for generating the
interrupt, and receiver/transmitter logic that performs the
conversion and formatting functions. The interface can
be mounted in a standard processor small peripheral controller
slot.

A detailed description of the DL11 interface is presented in
the DL11 Asynchronous Line manual, DEC-11-HDLAA-A-D.

1-25

Power System

The PDP-'1/40 Power System provides power for the basic system
and for expansion units (e.g., extra memory or device interfaces)
mounted within the basic BA11-FC mounting box$ Expansion within
the box is limited by space and availah Ie power

The basic power system consists of a base H742 power supply,
two H745 -15V regulators; and two H744 +5V regulatorsc There
is additional space in the H742 base power system for an
additional power regulator unit (either H744 or H745) depending
on the requirments of the particular system

All regulated outputs are protected with current limiting
circuitsQ In addition, a crowbar overvoltage circuit protects
the +5V output and the -15V output. An unregulated, partially
filtered +5V output is supplied for the indicators on the
programmer "s console

In addition to voltage, other outputs are provided by the power
system:

a line frequency signal, a DC LO logic signal,' and an

AC LO logic signalo The line frequency signal, which is a sine
wave clipped at both ground and +5V, is used by the line frequency
interrupt clock option (KW11-L) within the processoro The DC LO
signal indicates that the dc voltage outputs are not at the proper
value; the AC LO signal indicates insufficient ac voltagee

1 .. 26

The basic power system is controlled by a cabinet-mounted 860
power control unit. This power control unit provides thermal and
overload protection for the base power supply. Overloads in the
switched ac line are handled by a circuit breaker and a thermal
switch removes input power in the event of excessive heat or
fireo The power control, which is controlled by the OFF/PWR/PANEL
LOCK 'switch on the console, applies pwwer to the base H742 power
supply and to the cabinet ac power connectors.

(

1-27

1.4

APPLICABLE DOCUMENTATION

PDP-11 documents related to the PDP-11/40 System are listed in
Table 1-2 in two main categories:

general handbooks and PDP-11/40

System manuals .. System manuals cover the

hard~vare

manuals

specifically related to the PDP-11/40 and have associated
engineering drawings. General documentation covers overall
PDP~11

system descriptions, instruction set, addressing modes,

basic logic mdoules, unibus description, interfacing information .
Also covered is general software documentation covering basic
programs necessary for developing, loading, running, and
diagnostic applicationso A current list of other available
programs may be obtained from the DEC program library.

Both the PDP-11/40 series of manuals and the general handbooks
must be used together for a complete understandinry of PDP-11/40
systems .. The prime subject of this series is the processor
and related internal options unique to the PDP-11/40

system~

Other handbooks discuss the Unibus used to connect the processor
to peripherals, the peripherals

the~selves,

and programming

inforMation . A detailed hardware description of each peripheral
is provided in its associated hardware maintenance manual supplied
with the peripheral.

1-28

Table 1-2
Applicable Documents

Associated
Title

PDP-11/40 Processor

Drawing Set

Description

N/A

A general PDP-11/40

Handbook

System handbook covering

DEC,1972

system architecture,
addressing modes, the
instruction set, programming techniques,
memory management,
internal processor
options, console
operation, and system
specifications

PDP-l1 Peripherals

N/A

A general peripheral

and Interfacing

interface handbook.

Handbook

The first part is

DEC, 1972

devoted to a discussion
of the various peripherals
used ,.,i th PDP ... 11
Systems

The second

part provides detailed
theory, flow, and logic
(continued next page)

1-29

Table 1 - 2 (Cant)
Applicable Documents

Ass.ociated
Title

Drawing Set

Description

descriptions of
the Unibus and
external device logic;
methods of interface
construction; and
e~amples

of typical

interfaces

Logic Handb oak

N/A

Presents functions

DEC, 1972

and specifications
of the M-series logic
modules and accessories
used in PDP-11 interfacing (includes other
types of logic produced
by DEC but not used
with the PDP .. 11.

1-30

Table 1-2 (Cant)

Applicable Documents

Associated
Title

Paper-Tape Software

NjJl

Detailed discussion

Programmincr

of thp PDP-11 soft-

Handhook

~/.T?re

DEC-11-G(;PB-D

load! dump, en.:i.t,

s . . rs ter ;1 usod to

assP~h]e,

an~

dehun

pnp"11 nrnrrrarns;
in!)l1t/ontrut :rro-

rrrarnmi nr; ;1.nc1 the
floatin0 noint and
mClth nacY..Cl0C?

PDP-11/40 Systen

PDP - 1 1 I 4 0 S Y S

tAT'1 S

A r:.reneral iT'trn-

Manual

duction to the

DEC"11-H405~Z\

basic pnp-11/40
syst~1'I

including

sections on in-

stallation, operation,

and the instruction
set. Also nrovides
det~iled

inforMation,

includinn maintenance,

of the s:lsten power

sunplv.

1-31

Table 1-2 (Cant)
Applicable Documents

i'\ssoci(l te0

'ritle

KD11 Processor

Drcp·d

Set

PDP - 1 1 / 4 n

s v s t (~rn s

Doscrintinn

BIncT: diarrrarl dis-

Hanual

cussinn,

DEC -11 -j-IFD1Li\"A - D

discllssion!

flow

di~0ran

thp.or~T

on0T~tinn,

an~

Mai,ntenRnC0 for th0
Kf!11 .. r·

~rocpssor,

KY 11 - J)

~ro("'rarlJY1er'

consol~r

1 i)" i t

K~11

('>

rr i

st~ck

s t er

0 l' t

i. () n ,

KTV11-L line fre!!uPl1cv
,cloc~

nntion, anrl

IGq 1 maintennncp

console ontion.

ME11-L Core Menory

PDP-11/40 SystPTn

~e~eral

rlpscrintion,

f.'lanual

detnilA~

DEC-11-IIr'TELA-l\-D

anrl MaintenAnce of

descrintinn,

thp. t.PT11 - L core rlPT'qory.

th e

rie~"'10rv

s:'s ter'~;

?''r7n 1 -1. the basic

(contiJlllC:'<1 next pafJe)
1-32

Table 1 .. 2 (Cont)
Applicable Documents

Associated
Title

Drawing Set

Description

core memory_ The
MF11-L uses the
backplane and
core memory of the
ME11-L without the
box and power supply.

DL11 Asynchronous

PDP-11/40 System

Installation, con-

Line Interface

figuration, programming,

Manual'

and theory of opera-

DEC-11-HDLAA-A-D

tion of the DL11
interface. Covers DL11-A
through DL 11-E"
The DL11-A or C is
normally used as a
control for the
Teletype of LA30-S
DECwriter but the
DL11 can be used for
a variety of communications devices.

1 .. 33

Table 1-2 (Cant)
Applicable Documents

Ass@ciated
Title

Drawing Set

Description

KE11 Instruction

KE11 .. E Extended

Algorithms, data

Set Options

Instruction Set

programming, theory

Manual

(EIS) Option and

of operation, and

DEC-11-HKEFANA=D

KE11-F Floating

maintenance for the

Instruction Set

KE11-E Extended

(FIS) Option

Instruction Set (EIS)
option and the
KE11 .. F Floating
Instruction Set (FIS)
otpion"

KT11-D Memory

KT11 -D Memory

Operation, programming,

Hanagement

Management

and detailed theory

Option Manual

of operation for the

DEC-11-HKTDA-A-D

KT11-D Memory
Management optiono

1-34

Table 1-2 (Cont)
Applicable Documents

Associated
Title

LA30· DECwriter Manual

Drawing Set

Description

DEC-OO-LA30-DA

Presents a detailed
discussion of the
DECwriter including
installation, operation, principles of
operation, maintenance,
troubleshootin~,

and

engineerin0 drawings

LC11 DECwriter

DEC-11-HLCB-D

System Hanual

Provides general and
detailed descriptions,
programming, and
operation for the
LC11 DECwriter
interface. The
LC11 is userl when an
LA30-P (parallel)
DECwriter is used as
a system input/output
device ..

1-35

Table 1-2 (Cont)
Applicable Documents

Associated
Title

KL11 Teletype

Drawing Set

Description

DEC-11-HR4C"'D

Provides general and

Control Hanual

detailed descriptions,
programming, adjustments, and maintenance for the KL11
Teletype Control that
may he used instead of
the DL11 Control ..

Automatic Send-

Bulletin 273B,

Describes operation

Receive Sets,

two volumes,

and maintenance of

Manual

Teletype Corp ..

the Model 33 ASP
Teletype unit that
can be used as an
input/output device
with the PDP=11/40
System .. Comparable
~anuals

available for

other Teletype models ..

1-36

Table 1 - 2 (Cont)
Applicable Documents

Associated
Title

Drawing Set

Description

Model 33 Page

Bulletin 1184B,

Contains an illustrated

Printer Set,

Teletype Corp.

parts breakdown to serve

Parts

as a guide for disassembly, reassembly,
and parts ordering for
the Model 33 ASR
Teletype Unit"
Comparable manuals
available for other
Teletype models.

1 .. 37

105

ENGINEERING DRAWINGS

A complete set of engineering drawings and module circuit schematics
is provided with each

PDP-11~40

System. These prints sets were

noted in Table 1-2 of paragraph 1-4 either under a Drawing Directory
reference or as a second volume to the Maintenance Manual. The
engineering drawings are necessary and interrelate with the
manual discussion .. The DDI (Dra\ving Directory Index) provides a
list of prints included in the set and includes drawing number,
ti tIe; and revision numbers .. An X in the column labled

CUSTO~I(ER

PRINT SET indicates each drawing that is provided for the customer.
The 1972 DEC Logic Handbook contains general logic symbols used
on DEC drawings .. A more detailed discussion of drawing set
conventions is contained in the KD11 Processor Manual,
DEC-11"'HKDAA-A-D with this convention directly applicable to the
processor and processor options of the PDP=11/40 ..

An overall corporate convention is useful in identifying prints
and is noted below:

D-CS-H7233=O-1

Series

Original drawing size

Manufacturing variation
Module type, equipment

Dra-t"1ing type

type,or a 7-digit
DEC part number.

1-38

cs:

Circuit schematic

BS:

Block schematic

BD:

Block diagram

FD:

Flow diagram

DD:

Drawing directory

MU:

Module utilization

AD: 'Assembly drawing
UA:

Unit Assembly

WL:

\"Yire list

PL:

Parts list

AL:

Accessory list

In addition to the basic drawing number, a second type of number
is used wi th logic dra't'l7ings .. It consists of a 3 -digi t number
located in the title block. For example:

KT .. 3

KT11-D Option drawing set

Sheet 3 of this specific drawing set

The processor drawing set uses a number designation for each
module. Thus, K2-4 indicates sheet 4 of the K2 drawing set.
K2 indicates the U WORD dra\ving set .. Processor drawing set
designations are listed in the KD11-A Processor Manual along
with a description of the flow chart and logic diagram

(

conventions.

1-39

CHAPTER 2

2 .. 1

INSTALLATION

SCOPE

This chapter provides installation information and recommendations
to ensure proper installation, and subsequent operation of the
PDP-11/40 System ..

Only installation of the basic PDP-11/40 System and processor
options is included in this chapter .. A section on installation
of peripherals is not provided because of the modular and Unibus
concepts of the system .. To install a peripheral, for example, it
is usually only necessary to insert the interface module(s) into
the basic system mounting box and connect appropriate cabling
between the interface and the peripheral. Installation and maintenance
of the peripheral itself is normally covered in associated manuals.

It is recommended that sufficient time be given to site planning
and preparation with particular attention given to the

user~s

specific system configuration especially if a large number of
peripherals are part of the system ..

There are two DEC documents that aid in proper site planninCJ:
the PDP-11 Configuration Worksheet and the PDP-11 Site Preparation

(

Worksheet.

2 ... 1

The configuration worksheet permits the user to layout the
system prior to ordering so that he is aware of drawer layout,
cabinet layout, and Unibus interconnection .. This ensures that
the proper number of drawers and cabinets are used and that
Unibus length is sufficient for the system ..

The Si te PREPARATION \·vorksheet permi ts the user to determine
the power requirements, environmental preparations, and physical
arrangement of his system .. The worksheet provides data on
operating environment, power requirements, service and access
requirements, and physical specifications for the basic system
and available peripherals ..

A final layout plan should be approved jointly by the user and
DEC prior to delivery of equipment. It is recommended that any
modifications to the installation site be effected prior to
shipment and installation of the system ..

DEC Sales Engineers and Field Service Engineers are available for
consultation and planning and it is receommended that a qualified
DEC representative either install the system, or be present during
the installation process0

2 ... 2

2.2

SITE PREPARATION

Adequate site planning and preparation can greatly simplify the
installation process, resulting in more efficient and reliable

PDP ... 11/40 installation. DEC Sales Engineers and Field Service
Engineers are available for consultation and planning with
customer representatives regarding objectives, course of action,
and progress of the

installation~

The information in this

paragraph is provided primarily to permit review of the site planning.

(

2-3

Physical Dimensions

The overall dimensions and total weight of the particular
PDP ... 11/40 System as \\7ell as dimensions, weights, and cable
lengths of any optional cabinets and free-standing peripherals
should be known prior to "shipment of the equipment.

The route the equipment is to travel from the customer receiving
area to the installation site should be studied and measurements
of doors, passageways, etc. should be taken to facilitate
delivery of equipment. All measurements and floor plans should
be submitted to the DEC Sales Engineer and DEC Field Service to
ensure that the equipment is packed to suit the installation site
facilities. Any restrictions (such as bends or obstructions in
ahllways, etc.) should be reported to DEC.

If an elevator is to be used for transferring the PDP a 11/40
and its related equipment to the "installation site, DEC
should be notified of the size and gross weight liMitations
so that the equipment can be shipped accordingly.

Installation site space requirements are determined by the
specific system configuration to be installed and, when
applicable, provision for future expansione To determine
the exact area required for a specific configuration, a
machine-room floor plan layout can be helpfule When applicable,
space should be provided in the machine room for storage of

2 ... 4

tape reels, printer forms, card files, etc. The integration
of the work area with storage area can be considered in relation to
the work flow requirements between areas.

In large installations where test equipment is maintained, DEC
recommends that the test equipment storage area be within or
adjacent to the machine room.

Operational requirements determine the specific location of
the various options 'and free-standing peripherals of the system.
Dimensions, weights and cable lengths of free-standing peripheral
equipment must be known prior to installation; ,preferably
during site preparation and planning. The system peripherals
'must not be located

at distances from the basic system where

conne,cting cables exceed maximum limi ts. The following points
should be considered when planning the PDP m 11/40 layout:

Ease of visual observation of input/output
devices by operating personnels

Adequate work area for installing tapes,
access to console, etc.

Space availability for contemplated future
expansion.

(

2 ... 5

d..

Proximity of the cabinets to peripherals ..

e..

Proximity of cabinets and peripherals to any
humidi ty controrling or air condi tioning
equipment ..

The final layout should be reviewed by the DEC Sales Engineer,
DEC Field Service, and in-house engineering personnel to ensure
that cable limitations have not been exceeded and that proper
clearances have been maintained ..

2 ... 6

Fire and Safety Precautions

2.2.2

The following fire and safety precautions are presenteo as an
aid in providing an installation that affords adequate operational
safe9uards for personnel and system components.

If an overhead sprinkler system is used, a
'Gdry pipe"

system is recommended. This type

of system, upon detection of a fire, removes
source power to the room and then opens a
master valve to fill the room's overhead
sprinklers ..

If the fire detection system is the type that
shuts off the power to the installation, a
battery-operated emergency light source should
be provided ..

c..

If an automatic carbon-dioxide fire protection
system is used, an alarm should sound prior to
release of the CO

to warn personnel within the
2

installation.

If power connections are made beneath the floor
of a raised-floor installation, waterproof

(

electrical receptacles and connections should
be used ..

2-7

An adequate earth ground connection should be provided
for the protection of operating personnelG

2-8

2.2.3

Environmental Requirements

An ideal computer room type environment has an air distribution
systeQ which provides cool, well-filtered, humidified aire The
room air pressure should be kept higher than that of adjacent
areas to prevent dust infiltration.

(

2-9

2 .. 2 .. 3 .. 1

Humidity and Temperature - The PDP m 1'/40 electronics

are designed to operate in a temperature range of from 50 F
o
e
0
(10 C) to 122 F (50 C) at a relative humidity of 20 to 95%
without condensation .. However" typical system confiqurations
that use I/O devices such as
etc s
o

~agnetic

tape units, card readers,
o

(15 C)

require an operational tenperature ran1e of from 60 F
0

to 80 F

(27 C) with 40 to 60% relative humiditYe

Nominal opera ting condi tions for a typical systeF1 conf i(]uration
{')

(;)

are a temperature of 70 F (20 C)

and a relative hUMidity of 45%.

2., 2", 3., 2

Air Con'di tioning - When used, computer room air ... condi tioning

equipment should conform to the requirements of the "Standard for
the Installation of Air Conditioning nad Ventilating Systems
(non-residential)", N.F.,PoA Nunber gOA; as well as the requirements
of the "Standard for Electronic Computer Systens", NoP.P.Ao
Number 75.,

(
2 ... 11

2.2.3.3

Acoustical Damping - Some peri:?heral devices (such

as line printers and magnetic tape transports) are quite noisy.
In installations that use a group of high noise level devices,
an acoustically damped ceiling reduces the noise. Operator
comfort and efficiency is a major concern here ..

2..,12

Lighting - If cathode-ray tube (CRT) peripheral devices
are part of the system, the illumination surrounding these
peripherals should be reduced to enable the operator to
conveniently observe the display ..

(

2 ... 13

Special Mounting Conditions - If the PDP-11/40 is
to be subjected to rolling,

pitchin~,

or vibration of the

mounting surface (e.g., aboard a ship), the cahinets should he
securely anchored to the installation floor by mounting bolts.
Since such installations require modifications to the system
cabinets, DEC must be notified upon placement of the order so
that necessary modifications can be made.

2.2.3 .. 6

Static Electricity -

Static electricity can be an

annoyance to personnel and can, in extreme cases, affect the
operational characteristics of the PDP-11/40 System and related
peripherals. If carpeting is installed on the installation room
floor, it should be of a type designed to minimize the effects
of static electricity. Flooring consisting of metal panels, or
flooring ,vi th metal edges, should be adequately grounded ..

2 ... 15

2.2e4

Electrical Requirements

The PDP m 11/40 can be operated from a nominal 115V, 50/60 Hz
or 230V, 50/60 Hz ac power source. The primary ac operational
voltages should be maintained within the defined tolerances.

Line voltage tolerance should be maintained within

10% of

the nominal value and the 50/60 Hz line frequency should not
vary more than 3 Hz.

Primary power to the system should be provided on a line separate
from lighting, airaconditioning, etc o1 so that computer
operation is not affected by voltage surges or fluctuations o

The PDP-11/40 cabinet grounding point should be connected to
the building power transformer ground or to the building ground
point. Direct any questions regarding power requirements and
installation wiring to the DEC Sales Engineer or Field Service
Engineer.

Primary power outlets at the installation site must be
compatible with the PDP-11/40 primary power input connectors.
The PDP-11/40 basic system requires only one receptacle.
Figure 2=1 shows the ac plug.

2=1(,

115V, OR 230V,60Hz,SINGLE-PHASE,30A
(PIN VIEW OF MALE PLUG)
~~-T_FRAME GROUND

(GREEN)
NOTE:
Hubbell 2610
Nema L5-30P (plug)
L5 - 30 R (receptacle)

NEUTRAL
OR
RET""""u"""'R"""'N---'t-~
(WHITE)

PHASE
(BLACK)

11-1134

(
Figure 2-1

PDP-l1/40 Connector
2-16A

2.3

INSTALLATION PROCEDURES

The procedures presented in the following paragraphs are
provided to assist in unpacking, inspection, and installation
of the PDP-11/40 System and associated processor options.

CAUTION
Do not attempt to install the system
until DEC has been notified and a DEC
Field Service Representative is present.

2.3.1

Unpacking

Before unpacking the equipment, check the shipment against the
packing list provided. Check that the correct number of packages
has been delivered and that each package contains all the items
listed on the accompanying packing slip. Also, check that all
items on the accessories list in the Customer Acceptance Procedures
have been included in the shipment. Unpack the cabinets as
described in the following procedure •

.2-18

Step

Procedure

Remove outer shipping container.

:NOTE

The container may be either heavy
corrugated cardboard or plywood.
In either case remove all metal
straps first and then
fasteners and cleats

re~ove
securin~

any
the

container to the skid. If applicable,
remove wood franing and supports
from around the cahinet perineter ..

Renove the polyethylene cover fron the cabinets ..

Remove the tape or

pla~tic

shipping pins, as applicable,

from the cabinet(s) rear access door(s).

Unbolt cabinet(s) from the shipping skid. Access to
the bolts, located on the lower supporting siderails,
is facilitated by opening the access door(s} ..

Re~ove

the bolts ..

the leveling feet so that they are above the
level of the roll-around casters.

2 ... 19

Use wood blocks and planks to form a raMp from the
skid to the floor and carefully roll the cabinet onto
the floor.

Roll the system to the

If applicable, repeat Steps 1 through 7 for the expansion

pro~er

location for installation e

cabinets.

When the cabinets are oriented properly follow the
procedure of Paragraphs

2~3e2

cabinet(s)0

2=20

and 2 0 3.3 to install the

INSPECTION

After removing the equipment packing material, inspect the
equipment, and report any damage to the local DEC slaes office.
Inspect as follows:

Step

Procedure

Inspect external surfaces of the cabinets and related
equipments for surface, bezel, switch, and light damage, etc.

Remove the shipping bolts from the rear door, then open
the rear door of the cahinet, and internally inspect
the cabinet for console, processor, and interconnecting
cable danage; loose mounting rails, loose or hroken
Modules, hlower or fan damage, any loose nuts, bolts,
screws, etc.

Insoect the wiring side of the
broken wires, loose external

Inspect the power

sup~ly

lo~jc

CO~Donents

for proper

and power connectionso

2-21

panels for bent pins,
and foreign material.

s~atinq

of fuses

Step

Procedure

Inspect all peripheral equipment for internal and
external damageo This includes inspection of
magnetic tape and DECtape transport heads, motors,
paper=tape sprockets, etc.

CAUTIG:N

Do not operate any peripheral device
vlhich employs motors

sprockets,

etc~f

tape heads 11

if they appear to

be damaged in shipment.

2 ... 22

2 .. 3 .. 3

Cabinet Installation

The PDP-11/40 cabinets are provided with roll-around casters
and adjustable leveling feet. It is not necessary to bolt
the cabinet to the mounting floor unless conditions indicate
otherwise (e .. g .. , shipboard installation). Cabinet installation
procedures are as follows:

NOTE
In multiple cabinet installation,
receiving restrictions may necessitate
shipping cabinets individually or in
pairs .. In such cases the cabinets are
connected at the installation site ..

Step

Procedure

With the cabinets positioned in the rOOM, install
H952-GA filler strips between cabinet groups
(filler strips are shipped attached to the end
of a cabinet group) .. Remove 4 bolts each froJil
the front and rear filler strips .. Butt the
cabinet groups together while holdinry the
filler strips in place and rebolt through
both cablnets and the filler strips

(see

Drawing C"'UA-H952"'G"'O) .. Do not tighten the
bolts securely at this time.

Lower the leveling feet so that the cahinet(s)
are not resting on the roll-around casters but
are supported on the leveling feet.

Use a spirit level to level all cabinets and ensure
that all leveling feet are firm against the floor.

Tighten the bolts that secure the cabinet groups
together and then recheck the cabinet leveling.
Acrain ensure that all leveling feet are planted
firmly on the floor

Remove the shippinq bracket that secures the
extendable BA11-FC Mounting Box in the cabinet.

2 .. 3 .. 4

Ac Power Connections

A 3-wire cable is used to connect the site source power to the
power control in the top of the H960-C cabinet (see

Fi~ure

2-1

for connector type). The cable is connected at the factory for
either 230V, 50 Hz or 115V, 60 Hz operation. Most cabinets in
a PDP-11/40 system include a power control and a singleac
power cab Ie; power is distributed within the cabinet froM the
power control.

POvJer cables are intended to be connected to a si te power
systen that provides ac power on a single-phase, 2-wire plus
~round

system. One of the two wires should maintain a constant

(neutral) voltage, while the supply voltage is developed on
the other

(phase) wire.

The cabinets should be grounded to an earth

groun~,

with

ground straps connecting all the cabinets to each other.
In addition, the frame ground wire in each power cahle
connects the cabinet ground systen to the site power

syste~

sround co

The power controls in all the cabinets are connected togethpr
to :)rovide a central control of power turn .. on 2.nn ·turn .. off
These connections require that the phase of the voltage
supplied to each power control he the sane as the phRse of
the volta0c supplied to all other power controls in thp
sane syster.1e

2 ... 25

Before connecting any power cables to the site source power,
check all customer wiring. Ensure that power receptacles of the
appropriate types have been provided for each cabinet, and that
the receptacles are positioned close enough to the cabinet
positions to allow connecting the cables without stretching
or crossing the cables. ,In particular, check that the phase
and neutral wires have been connected to the same pins in
each receptacle, so that all cabinet power controls receive
the same voltage phase.

Intercabinet connections

When a mUlti-cabinet system is assembled, three types of electrical
connections must be made between cabinets (see Paragraph 2.3.3
for mechanical connections). These connections are:

Unibus connections - a BC11-A cable

~ust

connect

the last system unit in a cabinet to the first
system unit in the next cabinet.

Remote power connections - all cabinet power controls
are connected to a 3-wire control bus that provides
for system turn-on and turn-off, and

c.'

Ground strapping - the frame ground of the system
is distributed through the cabinets by direct
electrical connections between the cabinet frames.

2=27

Unibus Connections

To connect the Unibus bet'Aleen the

H960-C cabinet and an H960""D Expansion Cabinet, insert the
BC11=A cable in the rear system unit slot of the BA11-FC
mounting box of the H960-C Cabinets The cable then runs through
a cable clamp in the upper left corner at the rear of the BA11-FC
mounting box, and is passed under the power supply mounting rails
into the next cabinets In the

H960~D

cabinet, the cable passes.

through a similar cable clamp, and is inserted in the apnropriate
slot of the first system unit of the mounting boxe The BA11=FC
is noted above as an example, other mounting boxes might be
the last box ..

2 ... 28

2.3 5.2
0

Remote Power Connections - Each cabinet in the system

has one 860 power control. All the power controls are connected
by a 3 . . wire bus that carries a remote turn-on signal, an
emergency turn-off signal, and a control ground; there are
three Mate=N-Lok connectors on each power control for the
3 -\Alire bus .. A cable is supplied 'vi th each cabinet to connect
the power control of that cabinet to the next cabinet. Because
each 860 power control must be capable of connecting to the
860 power controls in the preceding and following cabinets,
two Mate-N-Lok connectors are reserved for the intercabinet
cables. A third connector is provided for connection to the
on/off switch, the thermal switch, or other emergency shut-off
devices within the cabinet.

(

2 .. 305 .. 3

Ground Strapping - Electrical safety is providea by

connecting all the cabinet frames to the ground level of the
site power system. This is done by connecting a wire in Rdch
power cable between the frame and the power system ground; this
is not a load carrying wire, and is intended only as an energency
ground path .. The green wire in each power cable is the frame
ground, whi Ie the "tv-hi te 'Vlire is the neutral, or return ",yire,
that carries the load current ..

To improve the level of safety provided by the frame ground
connections, all cabinet frames are connected by hraided copper
straps of 4 Al\TG solid wire with crimp . . on lugs" which are fastened
to copper studs that are welded to the frames

(this also prevents

the generation of ground loops between cabinc;ts that are connecten
by

si~nal=carrying

cables) .. The studs are welaed to the bottom

side rails of the cabinet frame, facing inward: the stud on the
left side of the cabinet is slightly forward of center while the
stud on the right side is slightly to the rear.

The ground strap supplied with each cabinet is fastenect to
one stud, passed over the side rail of that cabinet and the
side rail of the adjacent cabinet, and fastened to the stud
in that cabinet .. The copper studs arc
supplied on the studs.

threa~ed,

and nuts are

2.3.6

Remote Peripheral Interconnection

Installation instructions for 'remote peripherals, such as line
printers, card readers, and

magneti~

tape units, are covered in

the appropriate peripheral maintenance manual@ Normally, the
peripheral itself is a free-standing unit and the peripheral
controller is mounted in one of the system drawers. The controller
and peripheral must be interconnected and the peripheral must
also be connected to an ac power source.

In a basic PDP-11/40 System, there is a

s~all

peripheral

controller mounting slot that houses the controller for the
syst~m

input/output device

(LA30 DECwriter or Teletype Unit) •

This device is characteristic of remote peripherals installation.

When installing the system, i t is necessary to interconnect
the system and the input/output device (Teletype or DECwriter)
as described in the following steps:

Step

Procedure

Place the freestanding DECwriter or Teletype in the
desired position next to the system cabinet.

2-31

Step

Procedure

Run the control cable from the DECwriter or Teletype
unit through the back of the system cabinet and through
the cable clamp at the rear of the mounting box. Note
that, because of the size of the control cable connector,
the cable clamp must first be removed before the
connector is brought into the box. Once this is done g
the clamp can be replaced.

Connect the control cable connector to the receptacle
on the controller (DL11, KL11, or LC11) mounted in
the small peripheral controller slot of the processorG

Verify that the controller module is plugged securely
into the small controller slote

Connect the power cable from the DECwriter or Teletype
unit into one of the cabinet power receptacles.

2-32

Installation Verification

Prior to turning power on, proper installation of all processor
internal options and memory should be verified. Although memory
and processor options are installed in the

syste~

at the factory,

installation should be verified at the site.

Installation verification procedures for the available processor
options are given in Table 2-1. Verification procedures for core
memory, as well as procedures for installing additional meMory,
are given in Table 2 ... 2. A diagram of the mcnary syste::-t unit is
shown in Figure 2-2.

2 .. 33

Table 2 ... 1
Option Installation Verification

Option

KE11-E Extended Instruction

Procedure

Set (EIS) Option

Verify that KE11-E module M7238
is installed in slot 2 (sections
A-F) of processor backnlane
assembly.

Ensure that

ju~per

N1 on print

K3-8 of KD11-A processor module
M7233

(located in slot 5, sections
re~oved.

A-F) has heen

Ensure that

th~

three over-the-h3ck

cables have been connected to
the 40-pin Berg connectors on
the M7238 KE11-E module and the
M7232 processor module

(slot 3,

section A-D). These cahles provide
the

re~uired

logic interconnection

beb;.veen the processor and the
KF11"E option.

2-34

Table 2 ... 1
Option Installation Verification

Procedure

Option

KE11-F Floating Instruction

Verify that the KE11-E option has
been installed. The KE11-E is a

Set (FIS) option

prerequisite for the KE11-F.

Verify that KE11-F module M7239
is installed in slot 1 (section AmD)
of processor backplane assembly.

3..

Ensure that the three jumpers on
the KE11-E

~7238

module have been

removed .. These must be removed to
allow the KE11-F option to
execute

2-35

floatin~-point

instructions.

Jumper

Module

KE-2

M7238

KE-5

M7238

KE .. 9

M7238

Table 2 ... 1

(Cent)

Option Installation Verification

Option

KT11-D Memory Management

Procedure

Verify that KT11=D module M7236

Option (requires the

is installed in slot 8 (section A-F)

KJ11=A installation

of processor system unite

procedure also)

Verify that processor JUMper
changes have been made as indicated

below (these changes are
detailed in the installation
section of the KT11-D ootion
manual) :

Verify that the following jurnners
ha ve been rer'oved:

tJuE1per

tv10

~'1odule

M7231

\'19

'\'16
vJ5

2 ... 36

K1-8

[.17231

Table 2 .. 1 (Cont)
Option Installation Verification

Option

Procedure

Jumper

Module

K1 .. 7

H7231

K1"'9

M7231

W1
lv2

Verify that the following JUMper
has been moved:

K4 .. 4

1-17234

Verify that the following have
been added:

C106
C107

2 ... 37

K4-4

H7234

Table 2 ... 1 (Cant)
Option Installation Verification

Option

KJ11-A Stack Limit Register

Procedure

Verify that KJ11-A module M7237
is installed in slot E03 of the
processor backplane.

Verify that the following
processor jumpers have been
changed:

Jumper

hT1

Module

K1 ... 8

H7231

K4-4

M7234

M7235

Jumpers are moved according
to instructions on prints.
*Note that if the KT1'-D option
is present Jumper W2 of M7231
is reMoved completely.

2..,38

Table 2 ... 1

(Cont)

Option Installation Verification

Option

KW11-L Line Frequency Clock

Procedure

Verify that

ro~11-L

module M787 is

installed in slot F03 of the processor
backplane. Verify that the backpanel
wire between pin F03R2 and F03V2
for BG6 H has been removed.

KM11=A Maintenance Console

This option consists of a doublelength module (N130/N131)

that is

plugged into slot F01 when used to
monitor KD11-A operation, and slot
E01 when used to monitor KT11-D,

KE11 m E, or KE11-F operation.

Note that this option is not installed
in the system during normal use.

2",,39

Table 2-2
Memory Verification or Installation

Memory

MF11-L Core Memory
(basic to PDP11/40)

Procedure

1. Verify proper address selection on jumpers
on CONTROL & DATA LOOPS(G110) modulea

2a Verify that modules are installed properly:

Hodule

Slot

MEHOHY STACK(H214)
fv1Et,10RY

1,Sections C thru F

DHIVE FE) U:; 23 1 )

2,Sections A thru F

CONTROL & DATA LOOPS(G110) 3,Sections A thru F

3. Verify Unibus interconnection to the KD11-A
processor

(M980) and interconnection or

termination to rest of system

4 .. Verify that system
(D-IA-7009103-0-0)

~nit

(rv~920

or 1\1930) ..

power cable

is connected from the

system unit to MATE ... N. . LOK receptacles of
the power distribution panel located on the
BA11-FC mounting box. Connector P1 goes
to 3; connector P2 goes to '4.

2 ... 40

\1
Table 2 .. 2 (Cant)
Hemory Verification or Installation

Memory

Procedure

5. Verify the interconnection of K4-4 MSYNA L
signal from the KD11-A processor system unit
(pin A0781) to MF11 ... L meP10ry system unit
(pin C01U1). Use twisted pair wire with
grounding at nearest ground pin.

HM11-L Core
Memories

1. Select proper address selection on jumpers
on CONTROL

DATA, LOOPS

(G110)

module ..

(additional
memories added

2 .. Insert modules in either set of locations:

to i'1F11 ... L
memories)

Module

MEMORY DRI\.7ERS (r.231)

Slot

4,Sections A thru F

CONTROL & DATA LOOPS(G110) 5,Sections A thru F
MEMORY STACK(H214)

Module

t1EHORY DElVERS (G231 )

6,Sections C thru F

Slot

7 , Sections A thru F

CONTROL & DATA LOOPS{G110) 8,Sections A thru F
MEMORY STACK(H214)

2 ... 41

9,Sections C thru F

Table 2 ... 2 (Cont)
Memory Verification or Installation

Memory

Procedure

3. Verify the interconnection by wire wran of
pins C03U1 to C04U1 and C06U1

MF11=L Core

to C07U1.

1 .. Insert the MF11 ... L system unit into the

Memory

BA11 m FC mounting box using thumb screws

(expansion units

provided ..

added to basic
PDP11/40)

20 Rearrange Unibus connections and termination
using the M920 and M930, resnectively.
If memory is last unit in the mounting box
use BC11-A cable for interconnection to a
next box ..

3. Verify proper address selections on jumners
on CONTPOL &

DATA LOOPS(G110) modules.

40 Insert modules accordin0 to locations noted
for !-1F11-L Core rITenorv
Core Memories

2 .. 42

(basic) ano !'iM11"'L

(additional).

Table 2 ... 2 (Cont)
Memory Verification of Installation

Memory

Procedure

SOlI

A system unit power cable (D-IA-7009174-0"'0)
is used to connect the backpanel of the
additional MF11-L to the power distribution
panel's MATE-N-LOK receptacles. See
paragraph 6.5.4 for power loading restrictions.

6. connect the K4-4 MSYNA L signal from the
previous MF11 ... L system unit (pin C09U1)

this additional MF11-L system unit (C01U1).
Twisted pair wire with grounding at nearest
pins should be used.

2-43

Initial Power

Turn~On

Before turning power on, check the PDP-11/40 system as
described in the following steps:

Step

Procedure

Ensure that all installation verification procedures
(paragraph 2 307) have been performed c
0

Before

plu~ging

in the system ac power cahles, disconnect

the following Mate=N"'Lok plugs in the basic H742 power
supply wiring harness (see Figure 2-3):
Note that plugs P8 through P15 renain

P1 through P7

connected~

Turn off the circuit breaker on the 860 power
regulator

(If more than one cabinet exists, turn off

all 860 regulators.)

Plug in the ac power cable, turn on the circuit breaker,
and cheek the de voltages generated,hy the regulators.
These voltages can be checked at pins of plugs P1
through P6. See drawing D-IC-11/40=O-2 for specific pin
numbers

Check fan ac power on plug P70

Procedure

Step

, j
i

Turn off the circuit breaker and re-connect all
connectors (P1 through P7) •

Turn on the circuit breaker and verify correct
operation of the console OFF/POWER/PANEL switch.

Check the operation of all fans in the top of the
mounting box.

2-45

POWER DISTRIBUTION BOARD
MOUNTING BRACKET

11-1385

Figure 2-3

D.C. CABLE HARNESS
2 ... 45A

204

INITIAL OPERATION AND PROGRAMMING

Once the system has been installed and power applied, preliminary
operating and programming procedures should be followed prior
to using the system. Console operation o as well as the basic
operating procedures noted in Chapter 3, should be performed
firsto If the user is already familiar with console operation,
then the basic operating procedures given in paragraph 3 6
0

may be performed immediately. These procedures are necessary
to, but independent from, the customer acceptance procedure noted
in paragraph 2050

After initial operation, both procedures use a common set of
system, peripheral, and individual instruction diagnostics.
These programs, listed in Table 2=3, define initial acceptance
and operations They also provide for a continuing check on proper
operation as well as permit analysis of system failures.

2-46

Table 2 ... 3
PDP-11/40 Diagnostic Programs

Number

Tests

PROCESSOR (INSTRUCTION SET) TESTS

MAINDEC-11-DOAA

Unconditional branch

~tAINDEC .. 11

Conditional branch

"" OOBA

MAINDEC-11"'DOCA

Single operand instructions

MAINDEC ... 11"'DODA

Single & double operand instructions

MAINDEC .. 11-00EA

Rotate/Shift instructions

MAINDEC ... 11"'DOFA

Compare with equal results

MAINOEC ... 11"'OOGA

Compare with not equal

MAINDEC ... 11-DOHA

Move instructions

MAINDEC ... 11 ... DOIA

Bit manipulation instructions (RIT,BIC;BIS)

MAINDEC-11 ... DOJA

Add instruction

MAINDEC ... 11 ... DOKA

Subtract instruction

MAINDEC ... 11 .. DOLA

Jump instruction

HAINDEC . . 11 ... DOMA

RTS, RTI, JSR instructions

MAINDEC-11-DCKBA-A

Sign extend instruction

MAINDEC-11=DCKBB

Subtract one and branch instruction

MAINDEC=11-DCKBC

Exclusive OR instruction

MAINDEC-11-DCKBD

Mark instruction

MAINDEC-11-DCKBE'

Trap and interrupt return

!·1AINDEC- 11 ... DBKDM

Trap instructions & error traps

~·1AINDEC""11"'DOQB

T15 combined instruction test

2 ... 47

r~sults

Table 2-3

(Cant)

PDP-11/40 Diagnostic Programs

Number

Tests

MEMORY TESTS

MAINDEC-11-DZMMA

Address test up

MAINDEC-11-DZMMB

Address test down

MAINDEC-11-DZMMK

Up/Down address test for ACT-11

MAINDEC-11-DZMMD

Basic memory patterns test

MAINDEC=11-DZMME

Moving 1s and Os

MAINDEC ... 11 ... 0ZMNF

18 susceptibility test

MAINDEC~11=OZMMG

Worst-case noise test

MAINDECs11=DZ~lliI

Random data test

MAINDEC ... 11""nZQHBA

Memory exerciser

MAINDEC=11-DZQMBA

Extended memory exerciser

KE11-E

(ElS) OPTION

MAINDEC=11-DCKBL

Divide instruction

MAINDEC-11=DCKBK

Multiply instruction

MAINDEC-11=DCKBJ

Arithmetic shift combined instruction

MAINDEC ... 11 .. 0CKBI

Arithmetic shift instruction

MAINDEC-11-DCQKA

MUL/DIV Exerciser

2 ... 48

Table 2 ... )
PDP-~1/40

(Cont)

Diagnostic Programs

Number

Tests

KE11-F (FIS) OPTION

MAINDEC-11-DBKEA

Basic instruction tests

MAINDEC-11-DBKEB

Exerciser

MAINDEC-11-0BKEO

GTP overlay

KT11-D MEMORY MANAGEMENT

MAINDEC ... 11 ""DBKTA.

Basic logic test

MAINDEC=11-DBKTB

Access keys test

MAINDEC-11-DBKTC

HFPI/MTPI tests

MAINDEC-11=DBKTD

States test

MAINDEC-11-DBKTG

Memory management exerciser

MAINDEC-11-DBKTF

Abort test

KJ11-A STACK LI-MIT REGISTER

MAINDEC-11-DCKBF

Stack limit test

~~11-L

MAINDEC 11=DZKWA
a

LINE FREQUENCY CLOCK

, Line frequency clock test

2 ... 49

205

CUSTOMER ACCEPTANCE

Verify correct system operation by performing the Customer
Acceptance Procedures. The Customer Acceptance Procedures
document is shipped with the PDP=11/40 System and lists all
the tools, programs, and tests required to certify syste~
operation.

2-50

3.1

SYSTEM OPERATION

SCOPE

This chapter provides the information necessary to operate
and program the PDP-l1/40 System and associated input/output
terminal (Model 33 ASH Teletype or LA30 DECwriter). The
description is divided into five major parts: programmer's
console, DECwriter, Teletype, basic system operation, and
basic system programmdng.
The description of controls and indicators for the
consoles is in tabular form and provides the user with the
type and function of each operating switch and indicator.
Operating controls

fo~

peripheral devices that are not part

of the basic machine are contained in the appropriate
peripheral manual.
Basic step-by-step procedures for both manual and program
operation are given in paragraph
is covered in paragraph

3.5.

Basic system programming

3.6.

3-1

302

KYll-D PROGRAMMER'S CONSOLE

The KYll-D Programmerfis Console (Figure 3-1) provides the
PDP-ll/~O

interface

System with a necessary and useful programmer&s
0

Manual operation of the system is controlled by

switches mounted on this console which is the front panel
of the basic mounting boxo Visual displays indicate processor
operation and the contents of the address and data registerse
All register displays and switches, whether marked on the
console panel or not, are numbered from right to lefts The
n umb ers correspond t

_e powers
th

2 15 e e e o22
·
o,
f two, 1.eo,

2 1 , 2 0 e Therefore, the most significant bit (MSB) is at the
left of each specific register or display, the least
significant bit (LSB) is at the righto Whenever an indicator
is on, it denotes the presence of a binary 1 in the particular
bit positions The alternate color coding on the console
identifies the different functions or segments of the binary
number in octal formate

3-2

In addition to the alternate color coding, the DATA register
contains an index mark that divides the low-order byte
(bits 0-7) from the high-order byte (bits 8-15)

The high-

order byte is divided into octal format by two more index
marks. No marks are required for the low-order byte because
octal coding for this byte is identical to the alternate
color coding.
Figure 3-1 shows the location of all PDP-ll/40 console
controls and indicators. Each indicator and associated
function is listed in Table 3-1. Each control and related
function is listed in Table 3-2.

3-3

ADDRESS
~---I

RUN

DATA

POWER

USER

c::J
PROC

OFtJ~&117:

BUS

CONSOLE

16: 151~3: '21": '0: 9 B~iE 4 3[2; 10

VIRTUAL

c::J

IDEPI
11-1569

Figure 3-1

PDP-11/40 Programmer's Console

W
I

+:--

..;'~

~.c

Table 3 ... 1
PDP ... ll/40 Console Indicators
Indicator
DATA

16-bit display
MSB at lef't
Color-coded in
3-bit segments
for octal f'ormat
Byte division
noted with
additional
indexing for
octal format in
upper byte

u)
I

Function
Displays the output of a
processor data multiplexer
which gates information from
a variety of sources within
the processor. Normal
programming use results in
the following displays:
HALT instruction has R(OO)
RESET instruction has R(OO)
'WAIT instruction has R(IR)
SINGLE STEP and HALT switch
has processor status (PS)

Remarks
When console switches are used,
information shown on the DATA
display is as follows:
LOAD ADRS - the transferred
switch register information
DEP - the switch register data
just deposited.. Note that
data and address are
correlated. The address is
where this data was stored.

EXAM - the information from the
address examined. Note address
The display of the data
and data correlation.
multiplexer is especially
important when used in the
HALT - displays the current
single clock mode. During this
mode, the KMll maintenance
processor status (PS) word.
console is used to step through
a program a single microinstruction at a time. In this
When a programmed HALT instruction
is issued, bus control is
'
instance, the information in
the DATA display is the result. transferred to the console and
of a single microword snd shown processor register, RG~:is displayed
on the processor flow diagrams
on the DATA display_ This allows
(refer to KDll-A Processor
progrwm identification of halts.
Manual) ..
During direct memory access (DMA)
operations, the processor is not
involved in data transfer functions.
Therefore, the data displayed in
the DATA display is not that of
the last bus operation.

Table 3~1
(continued)
Indicator

ADDRESS

18-bit display
MSB at left
Color-coded in
3-bit segments
for octal
format

Function
Displays the address in the
bus address register (BAR)
of the process ore This varies
with an instruction execution
but for a HALT, WAIT, or single
step operation, the program
counter is displayed between
operations The updated (or
incremented) value of the
program counter is always
displayed.
0

If the KTII-D option is not,
included in the system, the
two most significant bits
(A17,A16) are ordered according to the lower 16 bits; they
are set only when bits A15,AI4,
and A13 are all set. Addresses
between 160000 and 177777,
therefore, are translated to
addresses between 760000 and
777777, respectively.
If the KTII-D memory option
is installed, the ADDRESS
display usually displays a
virtual address with the KTII-D
providing an offset physical bus
address (not displayed). During
console operations, however, the
console provides and displays
a full 18-bit physical address.

!....0
I

Remarks
When console switches are used,
information shown on the ADDRESS
display is as follows:
LOAD ADRS - the transferred
switch register information.
DEP or EXAM - indicates the
bus address just deposited
into or examined.
During a programmed HALT or WAIT
instruction, the ADDRESS displays
the incremented address of the
instructiono The BAR is the
instruction location plus 20
In single instruction mode, the
next PC is placed into the BAR
and displayed in ADDRESS between
instructions.
During direct memory access
(DMA) operations, the processor
is not involved in the data
transfer functions, and the
address displayed in the
ADDRESS display is not that of
the last bus operation.
Within instructions, the display
indicates various processor bus
addresses. These values are
apparent only in a maintenance
mode, using the KMll and single
clocking.

Table 3-1
( continued)
Indicator
RUN

w
'-'

~
~ingle

light

Function
When the RUN indicator is on,
the processor clock is
running and is operating on
an instruction,or looping in
console operation.
When the RUN indicator is'
off, the microprogramming is
not processing an instruction.
The processor may be in control
of the bus and awaiting a
response for a data transfer;
or the processor may have
relinquished bus control for
an NPR or BR request.

Remarks
During normal machine
operation, the RUN light
flickers on and off
(indicated by a faint glow).
A programmed RESET command
turns off the RUN light. This
also occurs between single
clocks when the KMll ma.inte.nance
console is Used.
For programmed HALT and WAIT
instructions, th~ clock
continues to run with the
processor looping in the
microprogram. This is a.lso
true for console operation
of the HALT switch o

Table 3-1
(continued)
Indicator
PROC

Single light

Function
When lit, indicates that the
processor is controlling the
Unibus as the master device.

Remarks
When the PROC light is on and
the RUN light is off, the
processor is waiting for data
from the bus These conditions
indicate that the processor
is in control of the bus
(PROC on) but that the processor
clock is o~~ (RUN o~~)o
e

BUS

Single light

When lit, indicates that some
device has control of the
Unibus If the PROC indicator
is Ii t, that device is theprocessor.
0

CONSOLE

Single light

This display is useful for
determining where bus control
is and that it is presento

Wh~lJ_lit,

indicates that the
processor is in the console
portion of the microflowo
Control switch activation
is sensed and acted uponQ

LV
I

Table 3-1
( continued)
Indicator

F1IDction

USER

Single light

When lit, indicates that the
processor is in the user mode
and certain KTII-D restrictions
on instruction operation and
processor status (PS) word
loading exist. Rerer to the
KTIl-D option discussion in
chapter 4 and the KTIl-D
manual.

VIRTUAL

Single light

When lit, indicates that a
Does not function unless the
virtual address is displayed
KTll-D memory management
in the ADDRESS display. This
option has been installed in
virtual address is usually
the system .
modiried by the KTIl-D option
to provide a dirrerent physical
address ror the Unibus. Ir the
KTII-D option is installed, this
display is usually active during
program operation. During console
operation, the console ADDRESS
display and switch register both
provide a full 18~bit physical
address. The VIRTUAL light is off
in this instance.
When VIRTUAL light is orr, it
indicates that the bus address
indicated by the ADDRESS display
is the physical address.

W
I

Remarks
Does not runction unless the
KTll-D memory management
option has been installed in
the system.

Table 3-2
PDP-II/40 Console Controls

Switch

OFF/POWER/
PANEL LOCK

.3 .... position, key
operated switch

. Function
Provides power control to
console and lock-out of
console controls as follows:
OFF position - removes all
power from the prqcessoro

System not being used

PO\~ER post tion "'" applies
primary power to the
processoro All console
controls are fully
operational when switch is
in this positiono

Normal operationo

PANEL LOCK position - disables

Processor operating;
console cDotlr'GL:ldisabled.

all console (panel) controls
except the switch register key
switches This prevents
inadvertant switch operation
from disturbing a r~nning
programo
0

The data entered in the switch

register is still available to
the processor whenever the
program explicitly addresses
the switch register (address
777570)

Go)

t--'

Remarks

Table 3-2
(continued)

Switch
Regis ter

Function

Switch

18 key-type switches
Bit position o~ each
switch is labled;
MSB is at le~t.
Color-coded in 3-bit
segments ~or octal

Provides a means of speci~ying
an address of' data word into the
processor.
If the word contains data, it is
loaded into the address specified
by the ADDRESS REGISTER by lifting
the DEP key.

~ormato

Up" position - logical
one {or on)o Down
position - logical
zero (or off) ..

If the word in the switch register
represents an address, it can be
loaded into the ADDRESS REGISTER
by depressing the LOAD ADRS key.
If the KTII-D memory management
option "is used, bits 17 and 16
are directly used as the physical
bus address during console
operation~

If the KTII-D is not installed, the
processor bus address bits 17 and 16
are set if switch register bits 15,
14, and 13 are all seto Bits 17 and
16 of the switch register have no
ef~ect.

The contents of the switch register
may be used by the processor any time
the program explicityly addresses the
register at address 7775700 This
address can only be used by the
processor.

l;J

r-'
r-'

Remarks

Table 3-2
(continued)
Switch

LOAD ADRS

Momentary key-type
switch
Depress to
activate

Function
The LOAD ADRS switch
transfers the contents of
the switch register to the
bus address register (BAR)
through a temporary location
R(TEMPC) within the
processor~ This bus address,.
displayed in ADDRESS,
provides an address for the
console functions of EXAM,
DEP, and START.

Remarks
The address is loaded into a
temporary location which is
not modified during program
execution To restart a
program, it is only necessary
to depress the START switch •.
6

NOTE
Double examine or deposit
functions increments the
value of the loaded sddr,ess
both in the BAR and in
R(TEMPC)
0)

Attempts to examine or deposit
an odd bus address (bit 00
enabled) cause bit 00 to be
disregarded. For example, an
attempt to examine address 1001
results in address 1000 being
displayed. Byte data for
location 1001 is located in
DATA bit 15 through bit 08e

LV
I

rtr
~'J--

,~!-

/~"\,.

Table 3 ... 2
(continued)
Switch
EXAM

Momentary key-type
switch
Depress to
activate

Functfon

Remarks

The EXAM switch uses the
contents of R(~EMPC) as a
bus address; the contents of
this bus address is displayed
in DATA, the bus address is
displayed in ADDRESS.

If an odd address·is
examined, bit 00 is ignored
For example, if "address
1001 is examined, the
address 1000 is displayed
in ADDRESS .

A LOAD ADRS operation usually
pre-establishes the initial
R(TEMPC) address; sequential
examines automatically update
R( TEMPe) •

An EXAM operation that

If the EXAM switch is depressed
twice in succession, the contents
of the next sequential bus
address is displayed in DATA.
This action is repeated each
time EXAM is depressed provided
no other switch is used between
these steps.
Whenever the LOAD ADRS or DEP
switch is depressed, i tdest:roys
the incrementing sequence. The
next time EXAM is used, it
displays the current 'address
rather than the next sequential
address.

W
I

I-'

--------------------------------------------~~-------------------------------------------------

references a non-existent
address causes a time out
(with no TRAP) and the
switch register address
(777570) is displayed in
DATA
0

Table 3-2
(continued)
Switch

CONT

~
Momentary key-type
switch
Depress to
activate

Function

Remarks

Causes the processor to
continue operation from the
point at which it had
stopped ..

If program stops, depressing
CONT provides a restart
without power clear.

If the ENABLE/HALT switch is
in the ENABLE mode, CONT
.
returns bus control from the
console to the processor and
continues program operation.
If the ENABLE/HALT switch is
set to HALT, depressing the
CONT key causes the processor
to perform a single instructiona
Control is returned to the
console after each instruction,
permitting a program to be
stepped through an instruction
at a time
0

W
I

t-l

+-'
);',..

Table 3-2
(continued)
Switch
ENABLE/HALT

2-position, keytype switch

Function

Remarks

Allows either the .program or
the console to control
processor operation.
Continuous program control
requires' the ENABLE mode.

ENABLE position - permits the
system to run in a normal
manner. No console control
requests are made. All switches
except ENABLE/HALT and the
switch register are disabled.
HALT position - halts the
processor after the next
instruction or outstanding
TRAP sequences, and before

Unibus'BR requests? and
passes control to
console.

~he

The HALT mode is used with
the CONT switch to step the
machine through programs
one instruction at a time.

W
I

I-'
V1

When the START switch is
activated in the HALT mode,
a system clea~ is ~ffected
without program start. This
mode of operation is useful
for clearing conditions in the
system that might prevent
proper operation. When the
START switch is activated in
the ENABLE mode, it provides
a system clear with a program
start.

The HALT mode is used to
interrupt program control,
perform single intruction
operation, or clear the
system ..

Table 3-2
(c ontinued)
Switch
START

Function

Momentary key-type
switch

Depressing the START switch
provides a system clear
(initialize). When the
Depress to
ENABLE/HALT switch is set to
activate initialize, HALT, the processor does not
release to have
starto
START function
When ENABLE/HALT is set to
occur.
ENABLE, releasing START
begins processor operationo The
starting address is that o~ the
last console operation determined
by R(TEMPC)0 Usually, this
temporary location is loaded ~rom
the switch register by a LOAD ADRS
operatione
If the program stops at any time,
it can be restarted at its original
location by the START
switch; the value of R(TEMPC)
remains unchanged
0

Use of the START switch in the HALT
mode provides for a system clear.
This mode o~ operation is use~ul
~or clearing conditions that
might prevent proper operation.

v.)
(j\

Remarks

Table 3-2
(continued)
Switch
DEP

Momentary key-type
switch
Lift to activate

Function
The DEP switch uses the contents
of R(TEMPC) as a bus addresse
The contents of the switch
register are transferred to
this location. After use, the
data appears on the DATA display
and the address is on the ~DRESS
display.
A LOAD ADRS operation usually preestablishes the initial address;
sequentialDEP operations
automatically update R(TEMPC).
If the·DEP switch is raised twice
in succession, the contents of
the switch register is deposited
in the next sequential bus address
location. This action is repeated
each time DEP is raised provided
no other switch is used between
these steps. Whenever the LOAD
ADRS or EXAM switch is depressed,
it destroys the incrementing
process. The next time DEP is
used, it deposits the current
address rather than the next
sequential addresse

W
I

1'--'1

.....,

Remarks
If an attempt is made to
deposit an odd address,
bit 00 is ignored and a
word deposit occurs.
A deposit operation that
references a non-existent
address causes a time out
(with no TRAP). No error
message is visible from
the console for a deposit
to a non-existent address.
An immediate verification
by an examine operation,
however, would result in
the display of the switch
register address in the
DATA display.

3 .. 3

DECWRITER

The LA30 DECwriter unit is one of the input/output devices
that can be used with the PDP-II/40 Systemo Data can be
entered into the processor via the keyboard or data from
the processor can be printed out by the DECwritero
Controls and indicators for the LA30 DECwriter are shown
in Figure 3-2 and listed in Table 3-30 Further detailed
operating information is contained in the LA30 DECwriter
manual (DEC-OO-LA30-DA) and in the LCll DECwriter System
manual (DEC-ll-HLCB-D) ..

3-18

rr::il
~

(

\
I

\
,--

CB2

/:....-

,---

C'81

[@]

11-0671

Figure 3-2

DECwriter Controls

3-19

Table 3-3
LA30 Controls and Indicators

Control or
Indicator

Type

Remarks

Function

READY
indicator

sinqle light
(white)
-

When lit, indicates that power has
been applied to the system and the
DECwriter is ready for use in either
an input (keyboard) or output
(printer) mode 0

LOC LF
sv1i tch

pushbutton switch
with indicator

When depressed, advances paper as
lonq as switch is held down. Keyboard and printer operation disabled
during line feed0 This is an off-line
operations

CB2

circuit breaker
2-position toggle
switch

When set to on (up)position, applies
power to printer stepping motor
electronics ..

CBl

circuit breaker
double-pole Q.
single throw

When set to on (up) position, applies
primary power to the DECwritero

Keyboard

Typewriter-like
layout

Uses a typewriter-like keyboard to
print characters on paper or to input
information into the computer
0

97 or 128
characters

LV
I

o
~:-.

The keyboard does not type directly
into the printer; it simply sends the
appropriate ASCII code to the controller
for transmission to the Unibuso Therefore,
an echo keyboard program must be used for
typing directly on the papers

3.4

TELETYPE

The model 33 ASH Teletype unit is one of the input/output
devices that can be used with the PDP-II/40 System. Data
can be entered into the processor via the keyboard or
through a paper-tape reader. The Teletype can also be
operated off-line to punch paper

tapes~

Controls for the

Model 33 ASH Teletype are shown in Figure 3-3 and listed
in Table

3-4 .

Further detailed op'erating information is

contained in the Teletype Corporation manuals listed in
Table 1-2 of this manual.

3-21

Figure 3-3

Teletype Controls

3-22

Table 3-4
Teletype Controls
Type

Control

Function

PUNCH
REL. pushbutton

Momentary switch,
depress to activate

Disengages the paper tape
from the punch to allow
loading or removal of tape.

BeSP. pushbutton

Momentary switch,
depress to activate

Backspaces the paper tape
by one space each time the
pushbutton is depressed to
allow manual correction or
rubout of character just
punched.

ON pushbutton

2-position switch,
connected to OFF
pushbutton

When depressed, turns on
the paper tape punch and
releases OFF switch.

OFF pushbutton

2-position switch,
connected to ON
pushbutton

When depressed, turns off
the paper tape punch and
releases ON switch.

l..V
I

N
l..V

----------------...--------_......

_--------------------------------------------'~--~--

Remarks

Table 3=4

(continued)
Control

Type

Function

Remarks

READER
START/STOP/
FREE s\o' itch

3-position switch

Controls operation of the tape
reader ..
START position - enqaqes tape
reader which beqins" operation
under program centrele
STOP position - engages reader
mechanism but does not energize
ito In effect, tape is locked in
the reader but reading operation
does not begin until the switch
is moved to START.
FREE position - disengages
reader to permit loading and
unloading of tape
0

UJ
I

.po

Used on-line

'~""

Table 3-4
(continued)

Control
LINE/OFF/
LOCAL switch

3 .... position
rotary switch

Function
Serves two functions: applies
primary power to Teletype and
connects computer to Teletype.
LINE position - energizes
Teletype and connects i t to
the computer as an input/output
device. Signals from either the
Teletype reader or.keyboard can
be used as an input while the
computer output can be used to
control the keyboard or punch.
OFF position - deenerqizes the
Teletype by removing primary
power
0

LOCAL position - disconnects
the Teietype from the computer.
The Teletype can be used for
punching or reading tapes but
all control is localized at the
keyboard.

LV
I
N

Remarks

Table 3-4
(continued)
Control

Type

Keyboard

45 printing
characters
6 non-printing
characters
Typewriter-like
layout

Function

Remarks

Uses a typewriter-like keyboard
to print characters on paper,
punch tape, or input information
into the computerD
Off-Line Operation (LOCAL) - When
tape reader and punch are off,
prints characters on papero
t~en

punch is on, simultaneously
prints characters on paper and
punches equivalent code into paper
tape.

When reader is on, reades code from
punched paper tape and prints
equivalent characters on papero
On-Line Operation (LINE) - When
tape reader and punch are off,
nrints characters on paner and
sends e~uivalent siqnals to the
comnuter.
When tape reader is on, reads code
from punched paper tape and sends
equivalent signals to computer No
characters are printed.
0

When receiving signals from comnuter,
prints equivalent characters on paper
and punches tape if punch is onQ
Cover
Guard

Latch, push to
release

Used to hold paper tape in position
when using tape reader.

N
(j\

~;-;

3.5

BASIC OPERATION

Many methods exist for storing, modifying, and retrieving
information from the PDP-ll/40 System. These methods depend
on the form of the information, time limitations, and the
peripheral equipment connected to the processor .. The
following procedures are basic to the use of the PDP-II/40
System. Although they may be used less frequently as the
programming and use of the system become more sophisticated,
they are valuable in preparing the initial programs and in
learning the function of system input and output transfers.
For an understanding of the various 'operational controls
.and indicators, refer to paragraphs 3.2 through 3.4. Basic
programming techniques are given in paragraph 3.6.
Operating procedures are separated into the following
categories:

3.5.1

Power on

paragraph

Basic console
control

paragraph 3.5.2

Manual program
loading

paragraph 3.5.3

Automatic program
loading

paragraph

3.5.4

Running programs

paragraph

3.5.5

3-27

3.S.1

Power On

When the console OFF/POWER/PANEL switch is turned from
OFF to POWER, the system is initialized (or zeroed). A
time delay allows sufficient time for voltages to logic
units (especially memory elements) to stabilize~
The power-up initialization logic directly sets the
microprogram control to a sequence of controlled events
determined by the setting of the ENABLE/HALT switch.
If the console ENABLE/HALT switch is set to ENABLE when
power is turned on, the processor executes a power-up
microprogram sequence with the power-up vector address
determined by jumpers on the Status module

(M728S) of

the KDll-A processoro A new processor status (PS) word
and program counter (PC) are unstacked from the vector
address, ,and vector address plus two, respectivelye
Program operation begins with an entrance to the FETCH
portion of the microflow with the new PC used to obtain
the first instruction. Note that the processor Status
module jumpers are initally set at octal location 249
This location can be changed to accommodate system
requirements.

3-28

If the console ENABLE/HALT switch is set to H~T when
power is turned on, the 'processor microflow is directly
set to the console microloope The machine awaits the
activation of a console control switch •.
I

The third position of the OFF/POWER/PANEL switch is PANEL
which provides for program operation with the console
control switches disabledm However, the console switch
register may still be accessed m

3-29

Basic Console Control
Two major areas of control exist: control influenced by
the ENABLE/HALT switch, which selects either program or
console

cont~ol;

and control by the switches and

sequences used for loading data manually into the processor.

ENABLE/HALT Switch
When the processor has control (ENABLE/HALT in ENABLE),
either the START or CaNT switch causes the

progr~

rune The START switch initializes the system with a clear
signal and begins operation at a specific address determined
by the last

console operation (usually LOAD ADRS). The

CONT switch merely releases console control, and the
program continues.
When the ENABLE/HALT switch is set to HALT, the console
obtains control. The LOAD ADRS, EXAM, and DEP switches
can be used. The CONT switch can now cause the processor
to step through the program a single instruction at a time.

3-30

Loading Data Manually
Whenever data is manually loaded into a computer, it is

desirable

to have the address increment automatically

upon each deposito Thus, the user can set a starting
address and continue to store data in sequential memory
locations providing only new data for each location. The
programmer's console logic also permits the user to
immediately examine the data just deposited without
re-addressing, to re-deposit if necessary, and to continue
with automatic incrementation. These sequences are
associated with the functioning of the DEP and EXAM switches.
The address in the

ADDR~SS

increment the first time EXAM or DEP is used after a HALT
or LOAD ADRS. It does not increment if DEP is used
immediately after EXAM or if EXAM is used immediately after
DEP. It does increment if a DEP is used immediately after
a DEP, or if an EXAM is used immediately after an EXAM.
This increment is a word increment as the console is word
oriented. Thus, the user can look at a location, change it,
deposit the changed data, and then re-examine them without
having to load an address each time.

3-31

Incrementation is on even boundaries for all addresses except
the address specifically designated for the processor internal
registers, which are incremented bv onea
For example, to alter several successive locations, the
following steps are performed:
Procedure
I

LOAD ADRS (starting location)

E~~

DEP (no increment - loads startinq location)

EXM~

EXAH (increment - looks at next location)

DEP (no increment - loads second location)

EXAl1 (no increment - checks previous deposit)

EXAl1 (increment - looks at third location)

(no increment - looks at starting location)

(no increment - checks previous deposit)

etc ..

2-32

If the user desires to take advantage of automatic address
incrementation for examining or loading data, the following
steps can be used to load data into sequential locations:
Step

Procedure

LOAD ADRS (starting location)

DEP (no increment - loads starting location)

DEP (increment - loads second location)

DEP (increment - loads third location)

DEP (increment - loads fourth location)

etc.

The same procedure can be used for examining data in
sequential memory locations.

3-33

Manual Loading
A primary manual use of the programmer's console is-tostore the bootstrap loader in the core memory .. (Programs
and data can be stored or modified by manual use of the
programmer's console.) The bootstrap loader (DEC-ll-L1PA-LA)
is a minimal instruction program that can automatically
load programs into core memory from a paper tape punched
in a special bootstrap format. One of these programs,
after being stored, can in turn load any binary format
tape into the computer

(An explanation of the number

designations used for DEC programs is given in Table 3-5.)

3-34

Table 3-5
Program Identification Codes

COMPUTER

IDEmlFICATION

~ iDISTRJBUTION
\
--.,.
DEC-U-lIPA-LA

PRODUCT

Format:

Notes:
Product Code

•• H.

2 3456 78

MAINDEC = maintenance library products
DEC = programming library products

= PDP-II Computer Systems

Computer Series

Major Category

L= Loader

Minor Category
(sequential numbers)

1 frrst in a series of programs
2 = second in series, etc.

Option Category
(hardware required
to use software)

P = paper tape system
H = high-speed reader and/or punch
K = Teletype keyboard only
M= magtape

Revision Category
(sequential letters)

A = basic program
B = fIrst revision
C = second revision, etc.

Distribution Method

L = listing
P = paper tape

Distribution Mode

A= ASCII
B = binary (absolute)
0= other (bootstrap binary)

Example:

DEC-I 1-L2PB-PO

References:

DEC Oassifying and Documenting Standard. DEC-OO-BZZB-D.

indicates a PDP-II programming library product, second in a series of loaders, requiring a
paper tape system to use, the first revision to the
program, supplied as a paper tape in bootstrap
binary forma 1.

A list of all identification codes is in the PDP-11 Com.'ention ftlanual.

3-35

The sequence of loading the computer is shown in Figure

3-4

with programs noted as follows:
a

Bootstrap loader
(DEC-ll-LIPA-LA)

manually loaded by console
switches; provides for
automatic loading of programs
punched in a special format.

Absolute loader

punched in special format;
loaded by bootstrap loader;
provides for automatic loadir.g
of programs punched in binary
format ..

Selected program

punched in binary format;
loaded automatically by
absolute loadero

3-36

USE ABSOLUTE
LOADER TO
LOAD PROGRAM

USE
MAl NTENANCE
LOADER TO
LOAD PROGRAM

USE BOOTSTRAP
TO LOAD
ABSOLUTE OR
MAINTENANCE

'--------I

LOAD BOOT
LOADER
PROGRAM
11-1023

Figure 3-4

Flowchart of Procedure for Loading
and Running Programs

3-37

In order to eliminate the necessity of more than one bootstrap
loader, the bootstrap loader instructions contain two
variables (x and y) to provide compatibility with various
memory configurations and reading deviceso These variables
are listed in Table 3-60 A complete explanation 'of the
bootstrap loader program is given in Chapter

of the

Paper Tape Software Programming Handbook (DEC-II-GGPB-D);
further information may be found in the program listing,
DEC-Il-LIPA-LA ..
The following procedure is used for manually loading the
BOOT loader program (DEC-II-LIPA-LA):
Procedure
1

Set ENABLE/HALT switch to HALT to give bus control
to the console when powering upo

Turn OFF/POWER/PANEL switch to POWER position .. This
energizes the programmer's console ..

Enter starting address of bootstrap loader (Table 3-6)
into switch register. Make certain that the correct
xx value is used (037744 for 8K memory, 077744 for
16K memory, 117744 for 24K memory, etc.).

Depress LOAD ADRS switch~ The'address set in the
switch register is shown on the ADDRESS displayo

Enter starting address contents (016701) into
switch register .

Lift DEP switch .. The contents just entered in the
switch register is displayed in the DATA display.

Enter contents of next address into switch register ..
NOTE
It is not necessary to load addresses after the
starting address has been loaded because the
address is automatically incremented by two each
time DEP is used sequentially.
:.-38

Procedure
8

Lift DEP switch ..

Repeat steps 7. and 8 above for each location
of the: bootstrap loader.. When loading the
contents of address xx7766, make certain that
the correct x value is used. When loading the
contents of the last address, make certain
that the correct y value is used.

The bootstrap loader program is now loaded
in memory locations xx7744 through xx7766
and can be used to automatically load other
programs into memory.

Correct program entry can be verified by
examining the addresses between xx7744 and
xx7766. This is accomplished by setting the
starting address into the switch register and
depressing the EXAM switch. The contents of
the starting addresses are shown in the DATA
display. Each time the EXAM is again depressed,
the address is automatically incremented by
two and the corresponding contents displayed.

This last step (verification) may be sufficient
if the boot~trap loader program has already
been loaded into the system. The program is
stored in the last portion of available
memory so that it tends to survive program
operation and is available for reloading
programs.
If the program is not intact, load
according to the above procedure, beginning
with step 1 ..

3-3,9

Table

3-6

Bootstran Loader
(DEC-II-LIPA-LA)

Bootstrap loader should be toggled into highest core memory bank.
Address

Instruction

xx7744

016701

xx7746

000026

xx7750

012702

xx7752

000352

xx7754

005211

xx7756

105711

xx7760

100376

xx7762

116162

xx7764

000002

xx7766

xx7400

xx7770

005267

xx7772

' 177756

xx7774

000765

xx7776

yyyyyy

xx represents highest available memory bank. First location of the loader is one of the following, depending
on memory size; xx in all subsequent locations is the same as the first.
Address

Memory Bank

Memory Size

037744

077744

1.6K

137744

24K

157744

28K

Contents of address xx7776 (yyyyyy) should contain device status register address of paper-tape reader to
be used when loading the bootstrap formatted tape. Addresses are:
Teletype Paper-Jape Reader

177560

High-Speed Paper-Tape Reader

177550

3.5.4

Automatic Loading

Information can be stored or modified in the computer
- automatically only if a program capable of performing these
functions has previously been. stored in the core memory.

For

example, having -the bootstrap loader stored in the computer
enables the user to operate any program that has been punched
in the special tape format required by the bootstrap loader.
Typical programs of this type include the absolute loader,
the absolute dump, and the teleprinter dump.

The bootstrap loader is limited because of the specisl tape
format; another loader is used to load any binary format
tape into the computer.

This is the absolute loader (DEC-

ll-L2PB-PO), which is loaded into the computer by the bootstrap loader.

Once the absolute loader is in memory, any

binary tape program (such as PAL III assembler, symbolic
editor, input/output service routines, diagnostics, mathematical routines, etc.) may be automatically loaded.

The following paragraphs give procedures for loading the
absolute loader, and for using the absolute loader to store
other programs.
loader program

A complete description of the absolute
~s

give

Chapter 5 of the Paper Tape Soft-

ware Programminq Handbook (DEC-ll-GGPB-D)i refer also the the
program listing, DEC-II-L2PB-LA.

Loading Absolute Loader
The follow;ng procedure is used for automatically loading the
ABSolute Loader Program (DEC-II-L2PB-PO):
Procedure
1

Set ENABLE/HALT

switch to HALT.

Make certain that the bootstrap loader has been
stored in core memory (refer to Paragraph 3.6.3 0
step 11).

Enter starting address of bootstrap loader into
switch register.. The starting address is xx7744
(037744 for 8K memory, 077744 for 16K memory,
137744 for 24K memory, etc.).

Depress LOAD ADRS switch.
The address set in the
switch register is displayed in ADDRESS REGISTER
indicators ..

Set Teletype LINE/OFF/LOCAL switch to LINE.
connects the Teletype to the computer

This

NOTE

If some other reading device (such as
the high speed paper tape reader) is
used, make sure that the y value in
bootstrap loader address xx7776
corresponds to the device as described
in Table'S"" ..
6

Place the absolute loader tape in the Teletype
readero Make certain that the special leader
(a sequence of 351 punches) is under the reader
stationo Blank leader does not work ..

Set ENABLE/HALT to ENABLE ..

Depress START switch.. The tape is now read into
the computer which halts when the entire program
is loaded ..

Upon completion of loading this tape, the DATA display lights may be in any configuration .. The main

:-42

reason for this is that no checksum
exists in the bootstrap loader.

c~pability

Any PDP-II program punched.in binary format may be loaded
automatically by using the absolute loader"

The absolute

loader can be set up to select either an absolute or relocat.able
code.

If a relocatable code is selected, the user may

specify that the relocatable code

star~

at a specific address

or that the code start loading at the point the previous
load stopped.

The absolute loader also provides a checksum

test to ensure accurate loading.. Al though the computernormally stops when the binary tape is loaded, instructions
on the tape itself may cause the computer to begin execution
of the program immediately after loading is finished..

This

action is beyond the control of the user because_it is a part
of the program on certain

binary tapes.

The following procedure is used for automatic loading of
binary tapes into the computer by using the absolute loader:
Procedure
1 .

Make certain that the absolute loader program is
stored in core memory (rerer to paragraph 3.504.1)"

Set ENABLE/HALT switch to HALTo

Enter starting address of absolute loader into
switch register. The starting address is~7500

(217500 for.8K memory, 077500 for 16K memory,
117500 .for 24K memory, etc .. ).

3-43

Procedure
4

Depress LOAD ADRS switch.. The starting address of
the absolute loader is now displayed in ADDRESS
REGISTER indicatorso

Select the type of load desired by setting switch
register as specified in Table 3-7.

Table

3-}

Binary Tape Load Selection
(using ABSolute Loader)

Switch Register Settings
Bits 15-01
Bit 00

Type of Load
Normal (absolute)
Relocatable (continue
where left off) .
Relocatable (load at
specified adqress)

Not applicable

Offset from
tape origin

Make certain that input/output device (Teletype unit
of LA30 DECwriter) is on .... line.,

NOTE
The reading device may be changed at any
time by the user without reloading the
absolute loader.
If a reader is to he
changed, simply replace the contents of
address xx7776 with the appropriate device
status address (y value in Table 3~6).
7

Load desired binary tape into reader by placing
leader under the reader station' ..

3-l~4

Procedure
8

Set ENABLE/HALT switch to ENABLE.

Depress START switch. This begins the binary tape
load ..

If the binary tape contains a transfer address
instruction, the computer begins execution of
the program as soon as loading is complete.

The computer stops when either loading is complete
or there is a checksum error.
a. Loading complete - the low-order (right hand)
byte displayed in the DATA indicators is zero.
Additional binary tapes maybe loaded by repeating steps 5 through 7 above and depressing
the CONT swi tch.
b. Checksum error- the low~order byte displayed
in the DATA indicators is not zero, thereby
indicating a checksum error has ~ccurred i~he
previous block of data. In this case, reposition
the tape in front of the error-producing block
and depress the CONT switch.

3-4~

3.50403

Loading Maintenance Loader

The maintenance Loader program, MainDEC-II-D9EA, provides
an alternate method of loading diagnostic programs that
can be used if the Absolute Loader fails to function
because of a hardware failuree This loader should only be
used to load diagnostic programs if the Absolute Loader
malfunctions ..
Use the following procedure to automatically load the
maintenance loader:
Step

Procedure

Set ENABLE/HALT switch to HALT and depress
START to clear the system ..

Make certain that the bootstrap loader has
been stored in memory, starting at address 0377440
NOTE
The maintenance loader operates in the
lowest 8K of memorYG If some other memory
area must be used, several program locations
must be changed as listed in Table 3-8
after the maintenance program is loaded ..

Set svli tch register to 037744

Set Teletype LINE/OFF/LOCAL switch to LINE.

Place the maintenance loader tape in paper-tape reader.

Set ENABLE/HALT switch to ENABLE and depress START
The tape is read into memory and the processor halts
when the entire program has been loaded

and depress LOAD ADRS ..

NOTE
If the maintenance loader was not loaded
into the lO~~lest 8K of memory u make location
changes at this time (see Table 3-8).

3-46

Table 3-8
Maintenance Loader Location Changes For Different Memories

Change Contents of:

xx7502
xx75l0
xx7542
xx7566
xx7624
xx7674

Where xx equals:

xx7470
xx7474
xx7475
xx7475
xx7776

xx7474

03 for 8K memory
07 for 16K memory
13 for 24K memory

3-47

3 .. 5 .. 5 Running Programs
When running any program, the program must first be loaded
into the core memory either manually or by using one of the
automatic loading programs (bootstrap loader or absolute
loader).

Once the program is in storage g it can be run

at any time by loading the starting address of the program
(refer to appropriate program documentation) into the switch

The user also must make certain

that the ENABLE/HALT switch is in ENABLE and that the
appropriate external devices are on-line (connected to the
computer) .

The program can be manually stopped at any time by setting
the ENABLE/HALT switch to HALT... It can be restarted from
that point by returning the ENABLE/HALT switch to ENABLE
and depressing the CONT switchG

It can be started anew by

reloading the starting address and depressing the START switch.

A program can be altered during operation, or new data
introduced, through the switch register.

This console

The information transferred

may be treated as data or used to alter program flow.

Because of the

sp~ed

of the computer, console indicators are

3-48

of limited value while the computer is running. Major use
of the indicator panel is made during manual operation,
single instruction operation,. or during the maintenance
mode. During manual operation, the console indicators
reflect the console-operations of

LO~D

ADRS, EXAM, and DEP.

During maintenance operations, the console indicators display various data functions of the processor as the
maintenance module is used to step through the program
a microword at a time. Use of the maintenance module is
described in the KDll Processor Manual, DEC-ll-HKDAA-A-D.

3-49

306

BASIC PROGRAMMING

In order to produce programs that fully utilize the power
and flexibility of the PDP-II/40, it is necessary for the
user to first become familiar with various programming
techniques that are part of the basic design philosophy
of the PDP-II/40 System. These techniques (such as use of
stacks, subroutine linkage, interrupt nesting, reentrant
and recursive programming, etc.) are covered in the
PDP-II/40 Processor Handbook which also provides a
detailed discussion or the instruction set.
In addition to the general programming information given
in the PDP-ll/40 Processor Handbook, the user should
familiarize himself with console operation (described in
paragraph 302) and with the basic and extended PDP-ll/4o
instruction sets (Ohapter 4)s

3-50

In the event the user is already familiar with programming
the PDP-II/20 System, the PDP-II/40 canoquickly be learned
by

comparing the prime programming differences between the

two systems .. These differences are listed in Table 3-9.
Basically, the PDP-II/40 has added capabilities a.nd speed ..
These capabilities are increased even more if the KTll-D
Memory Management Option and the KEll Extended (EIS) and
Floating (FIS) Instruction Set Options are included in the
system ..
Note that the basic PDP-II/40 System (without options) has
four more instructions than the PDP-II/20 .. These instructions
are: eXclusive OR (XOR) , Subtract One and Branch (SOB),
ReTurn from inTerrupt (RTT), and Sign eXTend (SXT).

3-51

Table 3-9
PDP-II Programming Comparison
PDP-II/20

PDP-ll/40

JMP/JSR (R)+ uses (REG)+2 as address

JMP/JSR (R)+ uses (REG) before
auto-increment as address. All
auto-increments are now post
auto-incrementsc

All REG 6 (sp) autodecrement
references can cause overflow.
Address modes 4 and 5, JSR and
traps are tested.

Address modes 1?2,4, and 6, JSR
and traps are tested except that
nonaltering (DATls) references to
stack data are always allowed.

No red zone on stack overflow.

Red zone trap occurs if stack is

16 words below boundary. This trap
saves PC+2 and PS on new stack at
locations 2 and O.

SWAB instruction does not
affect V.

SWAB instruction clears V

Program HALT displays PC of
HALT instruction in ADDRESS
display.

Program HALT displays PC+2 of
HALT instruction in ADDRESS
display.

Byte operations to the odd
byte of the PS cause odd
address traps.

Byte operations to the odd byte
of the PS do not traps Not all
bits may exists

No RTT instruction.

If RTT sets the T bit, the T bit
trap occurs after the instruction
following RTT.

If RTI sets T bit, T bit trap
acknowledged after instruction
following RTI.

If RTI sets T bit, T bit trap
acknowledged immediately
following RTI.

Explicit reference to PS can
load T bit. Console can load
T bit, initialize can clear ito

Only implicit references (RTI,
RTT, traps, and interrupts) can
load T bit. Console cannot load
T bit but initialize can clear it.

3-52

Table 3-9
(continued)

PDP-II/20

PDP-11140

Odd address or non-existent
references using the SP cause
a HALT. This is a case of double
bus error with a second error
occurring in the trap service
of the first error.

Odd address or non-existent
references using the SP cause
a fatal trap. On bus error in
trap service, a new stack is
created at locations 0 and 2.

Stack limit boundary fixed at
octal 400 with violations
serviced by an OVFL trap.

Optional variable stack limit
boundary (KJIl-A Option). Use
of red and yellow zones on
either basic (octal 400) or
optionally variable boundary.

First instruction in an
interrupt service routine
is guaranteed to be executed.

The first instruction in an
interrupt routine is not executed
if another interrupt occurs at a
higher priority level than was
assumed by the first interrupt.

Power up vector at
power returns.

when

A trap instruction to vector
location 14 exists for the
IR code 3. No name is give~
this instruction.

Power up vector is initially at
can alter jumpers to other
addresses.

24;

The formerly unnamed instruction
for IR code 3 is now called BPT.

3-53

Table 3-9
(continued)

PDP-II/20

PDP-II/4o
NOTE

The rollowing is the sequence of service
for internal processor traps, external
interrupts, and HALT and WAITe
BUS ERROR TRAP - odd address,
data time out.

BUS ERROR TRAP - odd address, fatal
stack overflow (red); if KTll-D option
is used, memory management violations
to 250 .

HALT instruction for console
operation"

Same" (Refer to KTll-D, if installed,
for other changes.)

TRAP instructions - illegal or
reserved instructions, TRT,
lOT, EMT, TRAP ..

TRAP instructions - Illegal or
reserved instructions, BPT, lOT,
EMT, TRAP.

TRACE TRAP - T bit of
processor status

Same

OVFL trap - stack overflow

OVFL - warning (yellow) stack overflow

PWR FAIL trap - power down

Same

CONSOLE BUS REQUEST - console
operation after HALT switch

Same

UNIBUS BUS REQUEST - peri pheral
request, compared with processor
priority, usually an interrupt
occurs"

Same

WAIT LOOP - loop on a WAIT

Same

instruction in the IR until
an interrupt allows exite A
CONSOLE BUS REQUEST returns
to this loop after being
honored"

3-5 /..,

4.1

PROCESSOR INSTRUCTIONS AND OPTIONS

SCOPE

The purpose of this chapter is to present a brief introduction
of the PDP-II instruction set and the processor options
available for the PDP-II/40 System=
Paragraph

4.2

discusses the basic PDP-II instruction set

and also covers the expanded

instruction~

available if certain processor options

that are

(KEll-E, KEll-F, and

KTil-D) are installed in the basic system.
Paragraph

4.3

describes each of the options that can be

mounted in the basic KDII-A processor and references
appropriate documents containing detailed information on
the specific option. These options are: KEll-E, KEll-F,
KJII-A~

KTII-D, KWII-L, and KMII-A with an additional

Small Peripheral Controller. Specifications are contained
in Tables 4-12 through 4-16.
Information on memory units is presented in paragraph

4.4.

These units include the MMII-L, MFII-L, MEII-L, and MMll-S
memories.

(
4-1

4.2

INSTRUCTION SET

This section summarizes the PDP-II/40 address modes and
instruction set. Its purpose is to define the KDll-A and
provide tabular, quick-rererence information. A complete
description of PDP-ll/4o address modes and instructions,
with additional details and examples, is provided in the
PDP-ll/40 Processor Handbooko

The Instruction Set Processor (ISP) notation is used to
define the processor operations for each address mode arid
instructiono Table 4-1 defines the modified ISP symbology
used in this chapter. A more detailed description of ISP
notation is provided in Appendix A of the PDP-II/40 Processor
Handbook. Similar notation is ued in the block diagram and
flow diagram description of instruction implementation e
The following paragraphs cover address modes (paragraph 402$1)~
the basic instruction set (paragraph
instruction set (paragraph 402

402

2), and the extended

3). The conventions used in

the KDIl-A Processor are:

( )

is used for

< > or

[

or ( ) around an expression indicates logical A~

indicates logical OR
indicates logical negation

plus
minus

indicates addition
indicates subtraction

4-2

Table 4-1
ISP Symbology
Symbol

Defmition

Dermes the limits of an expression, such as word length 05:0>.

[ ]

DerIDes the limits of a memory declaration; Mw [SP] specifies the address of the
stack pointer in memory.
The expression to the left of this symbol is replaced by the expression to the right
of this symbol,
Z +- I indicates the Z bit is set,
. PC +- PC + 2 indicates the program counter register (PC) is incremented by 2.

cat
equiv

It
OR

Indicates concatenation; registers to the left and right of this expression are considered to be MG t"E'3\.ster
Designates that expressions to the left and right are equivalent.
Logical AND
Logical inclusive-OR
Negate

XOR

Logical exclusive-OR
Indicates that a reference to the expression with which this symbol is used may
cause side effects, e.g., registers may be changed as a result of the operation.
Used as a delimiter

;next

A sequential delimiter, the operation to the left must occur before the operation to
the right.
~tes

an address mode; address mode 1 is indicated by m

=:=

General register 7 (program counter)

Auto-increment; by 2 for word instructions, and by I for byte instructions.
r

Indicates a result; used many times with limit symbols as an intermediate register
(r(15:0».
_._.-

Addition; expression to the left is added to expression to the right.
Subtraction; expression to the right is subtracted from expression to the left.

Multiply; expression to the left is multiplied by expression to the right.

Divide; expression to the Jeft is divided by the expression to the right.

sign-extend

The sign bit of a byte. bit 7, is extended through bits 8 to IS.

Memory word declaration; the address in brackets points to the memory location.

nw'

Indicates next word, as pointed to by the PC with side effects ('). The word is at
the next sequential PC address, or the word pointed to by the next word (deferred
addressing).

R [drJ

Indicates that a register (R) address as a memory declaration is that of a device
register.

Destination

Byte destination

Source

Byte source

4-3

Address Modes
The instruction set of the PDP-ll/40 System

flexibly

interacts with the general-purpose registers through the
address modes o Table

4-2

lists all of the address modes,

including the program counter (PC) register address modeso
These address modes, along with the general-purpose register
deSignation, determine the instructions' operands
(source and/or destination) and for.m part of the l6-bit
instruction format (Figure

4-1)0

4-4

Table 4-a,
Address Modes

Symbolic',

ISP

GenenJ

~rpose

Description

RegisterJAddressing

if (m=O) then Rr ;

The register (R, Rr) is the operand.

@Ror(R)

if (m=}) then M [Rr] ;

Defer to operand through register
(R, Rr) as address.

auto-increment

(R)+

if (m=2) and (rg=f:7) then
(M [RrJ; next
Rr +- Rr + ail;

Defer to operand through register
(R, Rr) as address, then increment .

auto-incremen t
deferred

@(R)+

if em=3) and (rg:f7) then
(M [Mw [Rr] ]; next
Rr+- Rr+ 2;

Defer to operand through (R), Mw
[Rr] as address, then increment
register (R, Rr).

auto-decrement

-(R)

auto-decrement
deferred

@-(R)

if (m=5) then (Rr +- Rr - ai;
next M [Mw [Rr]]);

Defer to oper~nd through (R), Mw
Rr after decrement of register (R, Rr).

indexed

±X(R)

if (m=6) and (rg=f:7) then
M[nw'+Rr];

Index via register = (R, Rr) by the
amount specified in next PC word (X).

indexed
deferred

@±X(R)or
@(R)

if (m=7) and (rg=f:7) then
M [Mw[nw' + RrJ];

Defer to operand through index of
register CR, Rr) specified in next PC
word (X) as address.

...

if (m=4) then (Rr +- Rr - ail; Decrement register (R, Rr), then defer
. nt:xt M [R:r];
to operand through register (R, Rr) as
-".
address.

PC Register Addressing

immediate

iJ (m=2) and (rg=7) then
nw'

Defer to operand through PC value
(next word); next word is immediate
operand.

absolute

@#A

if (m=3) and (rg=i) then
Menw']

Defer"via next word (PC address) as
address to operand; absolute addressing.

relative

if (m=6) and (rg=7) then
M[nw' + PC] ;

Relative to PC; uses next word as deferred address of operand.

relative
deferred

if (m=7) and (rg=7) then
M [Mw[nw' + PC]];

Defer relative to PC; uses next word as
address of deferred address of the operand.

NOTE: The following symbols are used in this table:
R
= Register
X, n, A = next program counter (PC) word (constant)

4-5

SINGLE OPERAND

***

"
DESTINATION
ADDRESS FIELD

OP CODE
*=SPECIFIES DIRECT OR INDIRECT

ADDRESS~

**= SPECIFIES HOW REGISTER WILL BE USED,
*** = SPEC IFI ES ONE OF EIG HT GENERAL PUR POSE REGISTERS~

DOUBLE OPERAND

lOP CODE

[
15

lUi

M01DE

lHHI

l@ I

MODE

1@I

***
Rn

I
0

SOURCE
ADDRESS FIELD

DESTINATION
ADDRESS FIELD

*=DIRECT/DEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS.

** = SPECI FI ES
***' = SPECIFI ES

HOW SELECTED REG ISTE RS ARE TO BE USED.
A GENERAL REG ISTER ..
11-1068

Figure 4-1

Double and Single Operand
Addressing

4-6

Basic Instruction Set
The KDll-A basic instruction set is divided into six groups
o:f instruct,ions .. The :format o:f each group is shown in
Figure

4-20
ao

The six groups o:f instructions are:

Double Operand - Operations which imply two operands
(such as add, subtract, move, and compare) are handled
by instructions that specify two addresses. The first
operand is called the source operand; the second is
called the destination operand. Bit assignments in
the source and destination address fields may speci:fy
di:fferent address modes and different registers ..
Double-operand instructions are listed in Table

Single 0ferand - Operations which require only one
operand such as clear, increment, test) are handled
by instructions that specify only a destination
address (operand). The operation code, address mode,
and destination address are specified by the instruction ..
Single-operand instructions are listed in Table

c..

4-3 .

4-4 .

Register Source or Destination - Instructions in this
group make use of the general processor registers as
simple accumulators and the resulted is stored in the
selected register. In:formation can be used as either
a source or destination operand .. For example, the
exclusive OR o:f the selected register and the destination
operand can be stored in the destination address ..
Register source or destination instructions are
listed in Table 4-5 .

4-7

Program Control (Branch) - These instructions permit
control of the program by branching to new locations
in the program dependent on conditions tested by the
program The instructions cause the program to branch
to a location specified by the sum of an offset value
(multiplied by 2) and the current contents of the PC
provided the branch is either unconditionah or is
conditional and the conditions are met after testing
the PS word.
Q

Program control instructions are listed in Table
e.

4-6.

Miscellaneous - These instructions include HALT, WAIT,
and RESET as well as interrupt and trap handling
instructions such as RTI, RTT, EMT, and TRAP.
Miscellansous instructions are listed in Table 4-70

Condition Code Operators - These instructions are used
to set or clear individual condition codes in the
processor status (PS) word. Selected combinations of
these bits may be set or cleared together ..
Condition code operators are listed in Table

4-8.

4-8

DOUBLE OPERAND
Src

OP CODE

dst

REG

SINGLE OPERAND
dst

OP CODE

I
6

MISCELLANEOUS

10 I

REG

BRANCH (PROGRAM CONTROL)
OP CODE

OFFSET

15
CONDITION CODE OPERATORS

TIN

II II
z

11-1069

Figure 4-2

Instruction Formats

(
4-9

Table 4-3
Double Operand Instructions
Mnemonic

ISP Notation

Instruction
andOp Code
MOV

Move
(Src to O5t)
OtSSDD

MOVB

Move Byte
(Src to O5t)
IlSSDD

CMP
Compare
(Src to Ost)
02SSDD

r +- S'; next
N+-rOS>
if (r (I 5:0> = 0) then (Z +- 1 else Z +- 0),
D'+- r

Move source to intermediate register, r.
Set N if negative.
Set lifO.
Clear V.
Transmit result to destination.

r +- Sb'; next
N +- r (7);

Set N if negative.

if (r (7:0> =0) then (Z +- 1 else Z +- 0);
V+-O;
Db' +- r

Set Z ifO.
Clear V.
Transmit result to destination.

r06:0);
if (r (15:0> = 0) then (Z +- 1 else Z +- 0);
if (S (15) =-- D (15» & (S OS) XOR r (15» then
(V +- 1 else V +- 0);
C +- r(16)

Move source to intermediate register, r.

(MPB
Compare Byte
12SSDD

r (8:0) +- Sb' - Db'; next
N ;
if (r = 0) then (Z +- 1 else Z +- 0);
V+-O;·
D+-r

BISB
Bit Set, Byte
lSSSOD

r +- Db' OR Sb'; ;ext
N +-·r(7);
if (r (7:0) == 0) then (Z +- I else Z +- 0);

Inclusive OR of source operand and destination operand.
Set N if negative.

iro.

Set Z
ClearV.
Put result in destination.

Same as BIS, except byte.

V+-O;
Db+-r

ADD
Add

06SSDD

r 06:0> +- S' + D'; next
N +- r (IS>;
if (r (J 5:0) = 0) then (1. +- 1 else Z +- 0);
if (S (IS) equiv D (15» &. (S (IS) XOR r (15»
then (V +- 1 else V +- 0);
C +-r (16);

D+-dlS:0>

SUB

r 06:0> +- D' - S'; next

Subtract
16SSDD

N +- r (15);
if (r (] 5:0> = 0) then (Z +- 1 else Z +- 0);
if (D (IS> XOR S = 1778 ) then (V +- 1 else l/ 4- 0);
Db 4-1'

Set V if result is 1778 (dst byte was 0008 ),

(continued on next page)

4 . . 12

Table

4. .4

(continued)
~~I~

NEG

r +:--.0'; next

Neptedst
OOS4DD

N +- r (IS);

NEGB
NepteByte
lOS4DD

D+-r

Nepte D by 2's complement.
Set N if negative result.
Set Z ifO.
Set V if destination operand was 1000008 •
Clear C if result is 0, otherwise set C.
Put result in destination.

f+--I)b';next

Same as NEG, except byte.

if (r ::: 0) then (C +- 0 else C +- 1);

N +- r (7);
if (I' (7:0) = 0) then (Z +- 1 else Z +- 0);
if (r (7:0) = 2008 ) then (V +- 1 else V+- 0);
if (r (7:0) = 0) then (C +- 0 else C +- 1);
Db+-r

AOC
AddCany .
OOSSDD

r +- D' -+ C; next
N +- r (15);

if (r (15 :0) = 0) then (Z +- 1 else Z +- 0);
if (dIS :0)::: 1000008) &. (C = 1) then (V +- 1
e~se V +- 0); next
if (r <15:0> = 0) &. (C = 1) then (~+- 1 else
C +-0);

Add the C bit to the destination.
Set N if negati,-e.
Set Z ifO.
Set V if destination was 0777778 and C was i.

Set C if destination was 1777778 and C was 1.

D+-r

AOCB
AddCany
Byte
10550.0

r +- Db' -+ C; next
N +- r (7);
if (r (7:0) = 0) then (Z +- 1 else Z·+- 0);
if (r (7:0) = 200s ) &. (C = 1) then (V +- 1 else

Same as AOC, except byte.

V+-O);next

if (r (7:0) =0) & (C =1) then (C +-1 else C +- 0);
Db+-I'

SBC

r +- D' -C; next

Subtract C bit from contents of destination

Subtract

N +- dIS>;

Carry

if (r 05:0) =O} then (Z +- 1 else Z +- 0);
if(r 05:0) = 1000008 ) then (V +-1 else V +-0);
if (dIS :0) =0) & (C =1) then (C +- 0 else
C +-1);

Set N if negative.
Set Z ifO.

OOS6DD

Set V ifresult is 1000008 .
Clear C if result is 0 and C = 1. .

D+-r.

Put result in destinli lion.

SBCB

r +- Db' -C; next

Same as SSC, except byte.

Subtract
Carry Byte

N +- r (7);
if (r (7:0) = 0) then (Z +- 1 else Z +- 0);
if (r <7:0> = 2008 ) then 01 +- 1 else V+- 0);
I
if (r <1:0) ::: 0) &. (C = 1) then (C +- 0 else C +- 1);

1056.0.0

Db+-r

(continued on next page)

Table 4-4
(continued)

TST

r +- 0' -0; next

Sets Nand Z condition codes according to contents of

Test

005700

destination address.

N +- r (IS>;
if (r 05:0> = 0) then (Z +- J else Z +- 0);
V+-O;
C+-O

Test Byte

r +- Db' -0; next
N +- r (7);

105700

if (r (7:0> = 0) then (Z +- 1 else Z +- 0);

TSTB

Same as TST. except byte.

V+-O;
C+-O

ROR

r <16:0) +- D' (0) cat C cat 0' 05:1>; next

Rotate IDght
00600D

N +- I' (1S>;
if (I' (15:0> = 0) then (Z +- 1 else Z +- 0);
C cat D (J 5:0) .... I' 06:0>; next
if (N XOR C) then (V +- 1 else V+- 0)

17-bit intermediate result is C and contents of destination
rotated right one place.
Set N if high order bit is set.
Set Z if result is O.

Put 17-bit result into C bit and destination.
Load V with exclusive-OR of Nand C (after I'otaticm is
complete).

RORB
Rotate Right
Byte

1000DD

r {8:0) .... Db' (0) cat C cat Db' {7: 1>; next
N +- r (7);
if (r <7:0> = 0) then (Z .... I else Z .... 0);
C cat Db +- Jr (8:0); next

Same as ROR. except byte.

if (N XOR C) then (V +- 1 else V+- 0)

ROL

r 06:0} +- D' 05:0) cat C; next

Rotate Left

0061DD

N .... ( (15);

if (r (15:0) = 0) then (Z .... 1 else Z +- 0);
C cat D +- r 06:0); next
if (N XOR C) then (V .... 1 else V+- 0)

17-bit result is C and contents of destination rotated left one
bit.
Set N if result is negative.
Set Z if result is O.
Put resWt·into C and D. Bit 15 into C bit and previous C bit
into bit o.
Load V with exclusive-OR of N and C after rotation is
complete.

ROLB
Rotate Left
Byte
1061DD

ASR
Arithmetic
Shift Right
0062D0

r (8:0) +- Db' \7:0) cat C; next
N .... r (7);
if (r <7:0) =0) then (Z +- 1 else Z +- 0);
C cat Db +- r {8:0}; next
if (N XOR C) then (V +- 1 else V+- 0)

Same as ROL. except byte.

r +- 0'/2; next
C +- D(o);

Contents of destination shifted right one place (+ 2).
Least-significant bit loaded into C.
Set N if result negative.
Set Z ifresult O.
Load V with exclusive-OR of Nand C after shift is complete.
Put result into destination.

N +- r (IS>;
if (r 05:0) = 0 then (Z +- 1 else Z +-·0); next
if (N XOR C) then (V +- 1 else V+- 0);
:r

(continued on next page)

4-14

Table 4-4
(continued)
~

Opmmd Instmctions
Description

r -+- Db'/2; next
C -+-Db (0);
N -+-r (7);
if (r (7:0) = 0) then (l-+- 1 else Z -+- 0); next
if (N XOR C) then (V -+- 1 else V+- 0);
Db+-r

Same as ASR except byte.

r +- D' (IS) cat D' <13:0) cat 0; next

c -+- D (14); next
N -+- r (IS);
if (ll' (I 5:0) =0) then (Z +- 1 else Z -+- 0); next
if (N XOR C) then (V +- 1 else V+- 0);
D+-r

Shifts contents of destination left one place, but sign bit
remains in most significant place.
Bit 14 loaded into C.
Set N if result negative.
Set Z if result O.
Load V with exclusive-OR of Nand C after shift completed.
Put result in destination.

ASLB

r -+- Db' (7) cat Db' (5:0) cat 0; next

Same as ASL, except byte.

Arithmetic

C +- Db (6); next
N +- r (7);

ASRB
Arithmetic
Shift Right

Byte
1062DD

ASL
Arithmetic
Shift Left

0063DD

Shift Left
Byte
1063DD

MARK

if (I (7:0) =0) then (Z +- 1 else Z +- 0); next
if (N XOR C) then (V +- 1 else V+- 0);
Pb+-r

SP +- SP + (2 X df (5:0»; next

Mark
006400

PC+- R[5] ; next
R[5] -+- Mw [SP1 ;
SP+-SP+2

SXT
Sign Extend
destination
0067DD

if (N :z 1) then (r <15:0) +--1 else r 05:0) -+- 0);
next
if (dI5:0> = 0) then (Z +- 1 else Z +- 0);
D'+-r

..,
i

Adjusts stack pointer

b} the number of words indicated in the
low 6 bits of the instruction (2 X nn locations).
Puts old PC (RS) into PC.
Contents of old R5 poppt.'i into RS.·

If the N bit is set, then -I is pIKed in the destiMtm ~
Otherwise, 0 is placed in the destination operand.
Set Z if result is O.

(

4-15

Table

4-5

Description

XOR
Exclusive-OR
074RDD

SOB
Subtract
One and

r +- R[sr] XOR D'; next

The exclusive-OR of the register and the destination operand

if (r = 0) then (Z +- 1 else Z +- 0);
N +- dIS);
V+-O;
R[sr] +- r

Set l if result is O.

is stored in the destination address.

r +- R[sr] -I; next
R [sf] +- r;
if (r :f 0) then (pC +- PC - 2 X df (5 :0})

Set N if result is negative.
Clear V; no overflow possible.

Decrement register by I. If result is not equal to 0, branch.
Subtract 2 X 6-bit offset from PC to get new PC:"

Branch

077R offset

4 ... 16

Table

4-6

Propmn Control Instructions

PC +- PC + sign-extend (instr (7:0> ~ 2)

Always branch.
PC cl1anged as follows:
Eight least-significant bits of instruction are multiplied times 2
and added to PC with sign extended.

if (Z = 0) then (PC...+- PC + sign-extend
(instr (7:0> X 2»

Branch if Z is O.

&anch
Unconditional
000410c

BNE
Branch
Not Equal
OOlOloc

BEQ
Branch on
Equal
OO141oc

if (Z 1) then (PC +- PC + sign-extend
(instr (7:0> X 2»

Branch if Z is 1.

BGE
Branch if

if (N equiv V) then (PC +- PC + sign-extend
(instr <7:0> X 2»

Branch ifN is equivalent to V.

if (N XOR V) then (PC +- PC + sign-extend
(instr (7:0> X 2»

Branch if exclusive-OR of N and V equal 1.

if(-Z & (N equiv V) then (PC <- PC + sign,
extend (inst! (7:0) X 2»

Branch if Z not 0 and N equals V.

. Greater than
or Equal (zero)
002010e

BLT
Branch on
Less Than
002410c
BGT
Branch on
'Greater Than
003010c

BLE
if (Z OR (N XOR V» then (PC +- PC + signBranch on
extend (instr (7:0) X 2»
Less Than
or Equal (zero)
0034loc
BPL
Branch on
Plus
1000 loe
BMI
BrancJt on
Minus
l00410e

(

BHI
BranchoD
Higher
lOlOloc

if (N

=0) then (PC +- PC + sign-extend

Branch if Z equals 1 or if exclusive-OR of N and V equals 1.

Branch if N is O.

(instr (7:0) X 2»

if (N = 1) then (PC +- PC + sign-extend

Branch if N is 1.

(instr <7:O}.X 2»

if -(C OR Z) then (PC +- PC + sign-extend

Branch if C and Z are 0,

(instr <7:0> X 2»

(continued on next page)

4-17

Table 4-6
(continueo)
Prognm COli1lttollmtrudiorus
Mnemonic
ISP Notation

Instruction
andOpCode

BLOS

if (C OR Z) then (PC ~ PC + sign-extend
(instr<7:0) X 2»

Branch if C or Z is 1.

if 01 = 0) then (PC ~ PC + sign-extend
(instr (7:0) X 2»

Branch if V is O.

BVS

if (V = 1) then (PC ~ PC + sign-extend

Branch if V is 1.

Branch on
Overflow Set
102410c

(instr (7:0> X 2»

BHIS
Branch on
Higher or
Same
l03010c

if (C =0) then (pC <- PC + sign-extend
{instr (7:0> X 2»

Branch if C is O.

BID

if (C = 1) then (PC ~ PC + sign-extemi

Branch if C is L

Branch on

(instr rJ:O> X 2»

Branch on
Lower or
Same
1014loc

BVC
Branch on
Overflow
Cleu

lowel!"

l034loc
JSR
Jump to

SP ~ SP -2; next
Mw [SP] +- R[sr] ;

Push contents of R onto stack.

Subroutine
004RDD

R[sr] +- PC
PC +- D address

Store current PC in R.
Load subl!'Outine address into PC.

RTS

PC +- R[dr];

Load contents of R into PC.

Return from
Subroutine
00020R

R[dr] +- Mw [SP];
SP +-SP+ 2

Pop stack pointer into It.

4-18

Table

4-7

Miscellaneous Instructions
Mnemonic
Instruction
and Op Code
HALT

.Description

(sP Notation

Ofr +- true

Processor halts with console in control. No activities or

Halt

instructions can be executed until a console actions restarts

000000

the processor.

WAIT

Wait +- true

Processor relinquishes bus and waits for an external interrupt.

Wait

000001
lOT

SP +- SP -2; next

I/O Trap

Mw [SPj

000004

SP+-SP-2;next

Push PS onto Stack.

PS;
Push PC onto stack.

Mw (SP] +- PC;
PC +- Mw [20];

Get new PC from location 20.

PS +- Mw [22]

Get new PS from location 22.

RESET

Init+-J;

Send INIT on Unibus for 20 ms.

Reset

Delay (20 milliseconds); next

External Bus

Init +- 0

000005
SPL

PS <7:5)

df (2:0)

Load three least significant bits, N, into PS.

Set Priority
Level
ooo23N
RTI

PC +- Mw [SP};

Return from

SP +- SP + 2; next

Interrupt

PS +- Mw [SP};

Pop PS off stack.

000002

SP +- SP + 2

(RTI permits trace trap.)

RTf

PC +- Mw [SP] ;

Pop PC off stack.

Return from
Interrupt

SP +- SP + 2; next
PS +- Mw [SP] ;

Pop PS off stack.

000006

SP +- SP + 2

(RTT inhibits trace trap.)

EMT

SP +- SP -2; next

Push PS onto stack.

Pop PC off stack.

Emulator Trap Mw [SP} +- PS;
104 Code

SP +- SP - 2; next

Push PC onto stack.

(104oo0 104377)

Mw [SP] +- PC;
PC +- Mw [30];

Get new PC and PS from locations 30 and 32.

PS+- Mw [32J
.TRAP

SP +- SP - 2; next

Trap

Mw [SP] +- PS

104 Code

SP +- SP - 2; next

(104400 -

Mw [SP] +- PC;

104777)

PC +- Mw [341;
PS+-Mw[36]

Push PS onto stack.
Push PC onto stack.
Get new PC and PS from locations 34 and 36.

·4-19

Table

4-R

Condition Code Operators
Mnemonic
Instruction
and 01' Code

CLC

IS? Notation

Description

if (instr (4) =0 & instr (0)

= 1) then C+-O

if (instr (4) =0 & instr 0)

= I) then V

OearC

When bit 4 of the instruction is 0 bits 3. 2, 1, and 0 clear
corresponding bits in PS.

000241

ClV

= 37) then

Set all

(C +- 1;
V+-l;

Condition
Codes

Z +-1;

000277

N+-l)

4-20

4.2.3

Extended Instruction Set

Additional instructions are available if qertain processor
options are added to the basic system. These instructions
are:
a.

KEll-E Extended Instruction Set (EIS)
These
instructions have the same format as double-operand
instructions and provide an increased arithmetic
capability to the basic instruction set. These
instructions are: multiply (MUL), divide (DIV),
arithmetic shift (ASH), and arithmetic shift
combined (ASHe).
The EIS instructions are listed in Table

4-9.

KEll-F Floating Instruction Set (FIS)
These
instructions permit.arithrnetic operations in
floating-point notation. The instructions are:
FADD, FSUB, FMUL, and FDIV (floating point addi~ion,
subtraction, multiplication, and division).
Descriptions of each of these instructions are
given in the PDP-ll/40 Processor Handbook.

c ..

KTll-D Memory Management - The ~WPI instruction is
provided to allow inter-address space communication
when the PDP-ll/L~O is using the memory management
option. The MTPI instruction determines the address
of the destination operand in the current address
space.
Note that in the table, the move from previous
instruction (MFPI) and the move to previous
instruction (MTPI) are listed as ¥YPI/D and MTPI/D ..
This is because in the PDP-ll/~_O, lVIFPI and f1FPD
are execu~ed in an identical manner as are MTPI
and MTPD.
The KTII-D instructions are listed in Table 4-10.

4. . 21

Table

4-9

Extended Instruction Set (ElS)

----------r-------------------------------,----------------------------------------Mnemonic

iSi» Notation

mstruction
and Op Code

MUL

Desaiption

r (31:0) +- D' X R[sr]; next

Multiply contents of source register and destination to fonn

if (r (31:0> = 0) then (Z +- 1 else Z +- 0);

Set Z if product is O.

N +-r OD;
if (r (31 :0) < -2 15 ) OR (r (31:0) ~ 2 15 ) then

Set N if product is negative.

Multiply
070RSS

32-bit product.

Set C if product is more than 16-bit result.

(C +- 1 else C +- 0);
No overflow possible; clear V.

V+-O;

R[sr} 05:0)

r <31: 16); next

Store the high-order result in R.

R[sr OR 1] 05:0) +- r <15:0>;

Store the low-order result in succeeding register if R is even
number. Otherwise, store in R.

DIY

rl <31:0} +- R[sr] cat R[sr OR 1] /D'; next

The 32-bit dividend, R, R OR 1, is divided by source operand

r2 <15:0) +- R[sr] cat R[sr OR 1] -(rt X 0);

Determine the remainder.

next N +- rl (15);
if (r 1 <31:0) =0) then (Z +- 1 else Z +- 0);
if (0 =0) then (C +- 1 else C +- 0);
if(rl (IS) =0) & (d (31: 16) f 0)

Set N if quotient is negative.

D. R must be even number.

Divide
071RSS

Set Z if quotient is O.
Set C if divide by 0 attempted.
Set V if divisor is 0, or if the result is too large to be stored
as a 16-bit number.

if(r! (5)= l)&(rl (31:16)=1-1)

OR
if (D = 0) then (V +- 1 else V +- 0);
R[sr] +- d (l5:~)
R[sr OR 1] +- r2

Store quotient in R.

ASH

r (79:0) +- sign-extend (R[sr] 05:0> X 2 t

Contents of R are shifted NN places right or left, where NN

Arithmetic

(D' (5:0) + 32) mod 64); next

Store remainder in R OR 1.

equals the six low-order bits of DD.
NN =--32 to +31.

ShIn
072RDD

R[sr] 05:0) +- r (47:32>; next
if (R[sr] = 0) then (Z +- 1 else Z +- 0);
if «R[sr] (IS) = 0) & (r (79:48)* 0) OR
(R[sr] f 0) then

Load C with low order if right shift.

C +- r (64);
if (D (5:0) = 0) then C+-O

Otherwise, clear C.

4-22

Table 4-10

Memory Management Instruction Set

Mnemonic

Instruction
and Op Code
MFPVD
Move From

ISP Notation

r +- D'; next
SP+-SP-2;

Description

Get destination operand from previous I space.
Push stack.
Set N if negative.
Set Z if O.

N +- r OS>;

Instruction
Space
0065DD

if (r <15:0> = 0) then (Z +- 1 else Z +- 0);
V+-O;

ClearY.

Mw [SP] +- r

Put operand into current address space.

r ..... Mw [SP];

SP +- SP + 2; next
N+-r(5);

Get data from current stack.
Pop stack.
Set N if negative.

Instruction
Space

if (r <15 :0) =0) then (Z +- 1 else Z +- 0);
V+-O;

Clear V.

0066DD

D'+-r

Move to previous I space destination.

"MTPI/f)Move To

Set Z ifO.

/'
\.

4-23

4.3

PROCESSOR OPTIONS

The basic KDII-A processor of the PDP-ll/4.0 System contains
space for installing six processor options. In addition,
there is a small peripheral controller slot that is usually
used for a programmer's console device (such as the DECwriter
or Teletype interface) but that also can be used for a

I).

variety of options dependent on the user's individual
requirements .. The specific slot, or slots, allocated for
each option is listed in Table Lt-lT and shown in Figure 6The processor options that are available are:
a ..

KEII-E- Extended Instruction Set (EIS)

KEIl-F Floating Instruction Set (FIS)

KJll-A Stack Limit Register

KTlI-D Memory Management

e ..

KWlI-L Line Frequency Interrupt Clock

f..

KMII-A Maintenance Cons ole

Small peripheral controller slot (variable option)

The above options can be used in any combination as they
function independently with two exceptions .. The KEll-F(FIS)
option phsically requires the KEll-E(EIS)optio~and software
for the KTII-D option requires the KJII-A option. Eacb
option is discussed separately in subsequent paragraphs which
include a general description, specifications, and a
reference to more detailed documents.

4-24

Table 4-11
Location of Processor Options

Option

Section(s)

Slot

KEIl-E Extended Instruction Set (EIS)

A-F

KEll-F Floating Instruction Set (FIS)

A-D

A-F

For maintenance of the basic
processor

For maintenance of the KTII-D
and lor EIS and FIS options

C-F

KJIl-A Stack Limit Register
KTll-D Memory Management
KWll-L Line Frequency Clock
KMII-A Maintenance Console

Small Peripheral Controller Slot

4-25

KEll-E Extended Instruction Set (EIS) Option
The KEll-E Extended Instruction Set Option is a processor
option that expands the basic PDP-II/40 instruction set to
include: multiply (MUL), divide (DIV), arithmetic shift (ASH),
and arithmetic shift combined (ASHe). The option permits
multiplication and division of signed 16-bit numbers and
ari thmetic shifting of signed 16-bi t or 32-,bi t numbers.
Condition codes are set on the result of each instruction.
The KEIl-E(EIS)option is a single hex (six section) module
(M7238) that plugs directly into slot A02-F02 of the processor
system unit. The option functions as an extension of the
basic KDIl-A data paths, microbranch control, and control ROM.
The basic processor timing is not degraded when this option
is used. The NPR latency is not affected when the instructions
are being executed. Interrupts are serviced at the end of
each instruction in the standard manner.
There are no addressable registers in the KEII-E option.
All operands are fetched from either core memory or from
the general processor registers and the result of each
operation is stored in the general registers.

4-26

The MOL instruction uses the ·contents of the effective address
specified by the destination register and the source register
as 2's complement integers which are multipliede The result is
stored in the source register and, if even, the low-order
result in the succeeding register. If the source register
address is odd, qply the low-order product is stored. The MUL
instruction multiplies full l6-bit numbers for a 32-bit product.
The DIV instruction permits a 32-bit dividend to be divided
by a l6-bit divisor to provide a l6-bit quotient and a
l6-bit remainder. The sign of tbB remainder is always the
same as the sign of the dividend unless the remainder is zero ..
Overflow is indicated

more than 16 bits are required to

express the quotient. In this case, the instruction is aborted,
the overflow condition code is set, the expansion processor
status (EPS) word is loaded into the processor PS register, and
the program branches to a service routine. If the source
register is zero, indicating divide by 0, an overflow is
indicated ..

4-27

When the ASH instruction is used, the contents of the selected
register is shifted right or left the number of places
specified by a count. This shift count is a 6-bit, 2's
complement number which is the least significant 6 bits of
the destination operand~ If the count is positive, the number

is shifted left; if it is negative, the number is shifted
right. This allows for shifts from 31 positions left to 32
positions right (+31 to -.32)0 A count of zero causes no
change in the number.

When the ASHe instruction is used, the contents of a register
(address R) and ·the contents of another register (address of the
first register ORed with one, R+l) are treated as a single 32-bit
word. Register R+l represents bits 0-15, register R represents
bits 16-31. This 32-bit word is shifted right or left the
number of places specified by a count. This shift count is the
same as that described for the. ASH instruction and permits shifts
from +31 to .... 32. If the selected register- (R) is an odd number,
then Rand R+l are the same. In this case, a shift becomes a
rotate and the l6-bit word is rotated the number of counts
specified by the shift count {up to 16 shifts}.

Specifications for the KEll-E option are listed in Table 4-12
at the end of

this paragraph.

A detailed description of this

option is given in the KEll Instruction Set Options Manual,
DEC-ll-HKEFA-A-D.

4-28

Table 4-12
KEII-E

~IS)Specirications

Instructions

Mul tiply (MillJ)
Di vide (DrV)
Arithmetic Shift (ASH)
Arithmetic Shift Combined (ASHC)

Operations

Multiplication and division or
signed 16-bit numbers.
Arith.-rnetic shifting of signed
16-bit or 32-hit numbers

Registers

None in option. Operands fetched rrom
core or general processor registers.

Timing (approximate)

MUL

DIV

= 10.5

ASH

ASHC

= 3.8

Size

9 ..5 us
us

3.4 us plus address calculation
time plus 300 ns times absolute
value of shift count
us plus address calculation
time plus 300 ns times absolute
value of shift count

Single hex module (M7238)

(

4-29

KEII-F Floating Instruction Set (FIS) Option
The KEIl-F Floating Instruction Set Option is a processor
option that enables the KDll-A processor to perform
arithmetic operations using floating-point arithmetic. The
prime advantage of this option is increased speed without
the necessity of writing complex floating-point software
routines. The KEll-F performs single-precision operations.
The KEll-F option cannot be used unless the KEll-E(EIS)
option has been installed in the system.
The KEll-F(FIS)option is a single quad module (M7239) that
~lugs directly into slot AOl-DOl of the processor system unit.

If a BR request is issued before the instruction is within
approximately 8 us of completion, the floatin~-point
instruction is aborted" In this event, the program counter (PC)
points to the

a~orted

floating-point instruction, making the

instruction the next instruction to be performed by the programe
The NPR latency is not affected when floating-point instructions
are being executed o Interrupts are serviced at the end of each
instruction in the standard manner.

4... 30

The FIS option provides four special instructions: floatingpoint addition (FADD), floating-point subtraction (FSUB),
floating-point multiplicaticn (FMUL), and floating-point
division (FDIV).
Floating-point representation of a binary number consists of
three parts: an exponent, a mantissa, and the sign of the
mantissa .. The mantissa is a fraction in magnitude format with
the binary point positioned between the sign bit and the most
significant bit. If the mantissa is normalized, all leading
Os are eliminated from the binary representation; the most
significant bit is thus a 1. Leading Os are removed by
shifting the mantissa left; however, each left shift of the
mantissa must be followed by a decrement of the exponent value
to maintain the true value of' the number. The exponent value
represents the power of 2 by which the mantissa is multiplied
to obtain the value to be used.
For FADD or FSUB operations, the exponents must be aligned
(or equal). If they are not, the mantissa with the smaller
exponent is shifted right until they are. Each right shift
is accompanied by incrementation of the exponent value. Once
the exponents are aligned (equal), the mantissa is added or
subtracted. The exponent value indicates the D1.unber of places
the binary point is to be moved in order to obtain the actual
representation of the number.

4-31

For FMUL instructions, the mantissas are multiplied and the
exponents are added. For FDIV instructions, the mantissas
are divided and the exponents are subtracted.
The KEII-F Floating-Point option stores the exponent in
excess 2008 notation .. Therefore, values from -128 to +127
are represented by the binary equivalent of 0 to

255

(octal 0-377) .. Mantissas are represented in sign magnitude form .
The binary radix point is to the left . The result of the
floating-point operations is always rounded away from zero,
increasing the absolute value of the number .
If the exponent is equal to 0, the number is assumed to be 0
regardless of the sign bit or fraction valuee The hardware
generates a clean 0 in this instance.
Specifications for the KEIl-F option are listed in Table 4-13
at the end of this paragraph", A deta iled descrip tion of thi s
option is given in the KEll Instruction Set Options Manual,
DEC-ll-HKEFA-A.-De

4-32

Table 4-13
KEIl-F(FIS)Specifications

Prerequisite

KEII-E Extended Instruction Set Option

Instructions

Multiply (MUL)
Divide (DIV)
Arithmetic Shift (ASH)
Arithmetic Shift Combined (ASHC)
Floating-point Addition (FADD)
Floating-point Subtraction (FSUB)
Floating-point Mulitply (FMUL)
Floating-point Divide (FDIV)

Operations

Multiplication and division of
signed l6-bit numbers.
Aritbmetic shifting of signed l6-bit
or 32-bit numbers.
Single-precision floating-point addition,
subtraction, multiplication, and division
of 16-bit numbers.

Registers

None in option. Operands fetched from
core or general processor registers
(stack ordered)

Size

Single quad module (M7239)

4-33

KJll-A Stack Limit Register Option
The KDll-A processor is capable of performing hardware stack
operations

Because the number of locations occupied by a

stack is unpredictable, some form of protection must be
provided to prevent the stack from expanding into locations
containing other informationG In the basic illachine, this
protection is provided by a fixed boundary. The KJll-A Stack
Limit Register Option provides a programmable boundary.
The KJll-A consists of a single addressable register,
accessible to both the console and thB processor, that
is used to change the stack limit and to provide warning
(yellow zone violation) and error (red zone violation)
indications to the processor(\) The stach liwit register is an
8-bit register (high byte) that can be addressed either as
a high-order byte

(777775)

or as a full wo~d

(777774)0

During operation, the register is loaded with an address
signifying the lower limit of the stack (stack violations
occur at or below this limit)

During subsequent stack

pointer related bus operations (DATO, DATOB, and DATIP), if
the address of the bus operation is less than the contents
of the stack limit register, an error condition exists.

4-34

If the difference is less than or equal to

16 words, a yellow

zone violation occurs. The operations that caused the yellow
zone violation are completed and then a bus error trap occurs.
This error trap, which itself uses the stack, executes without
causing an additional violation.
If the space between the bus address and the stack limit
register is greater than

16 words, then a red zone violation

occurs and the operation causing the error is abortedo The
stack is repositioned and a bus error trap occurs; that is,
the old PS and PC are pushed into locations 2 and 0 and the
new PC and PS are taken from locations 4 and

6. A red zone

violation is a fatal stack error. Other fatal stack errors
are odd stack or non-existent stack. Note that these two
stack error conditions exist in the basic KDll- A processor;
however, in this case the stack limit is fixed at memory
location 4OOS-

The option utilizes this 400Sboundary also o

The KJII-A Stack Limit Register Option is a single-height
module that plugs into slot E03 of the processor.
Specifications for the KJII-A option are listed in Table 4-14
at the end of this

paragraph. A detailed description of ~nis

option is presented in the KDll-A Processor Manual, DEC-ll-HKDAA-A-D.

(

4-35

Table

4-14

KJII-A Specifications

8-bit stack limit register (bits 15-08)
addressable by console or processor, but
not by any bus device

777774
777775

Stack Limit

programmable; if register is alIOs,
then:
000
337 = red zone
340
377 = yellow zone

Yellow Zone
Violation

occurs if the stack operation's address
is less than the stack limit address by
16 words or lesse The operation is
completed and then a TRAP is executede

Red Zone
Violation

occurs if the stack operation's address
is less than the stack limit address by
more than 16 words The operation is
aborted (fatal stack error), a stack
vector exists at address 4, and a bus
error TRAP occurSe The old PS and PC
are pushed into locations 2 and 0; the
new PC and PS are taken from locations
4 and 60

(word addressing)
(byte addressing)

PDP-ll/40
Stack Limit

The PDP-ll/40 System has a fixed stack
limit at 377. Therefore, it is equivalent
to the initialized state of the KJII-Ao

Size

one single-height module

4-36

KTll-D Memory Management Option
The KTll-D Memory Management Option is a PDP-ll/40 processor
option that provides the capability to expand the 32K-word
addressing of the KDll-A processor to l28K words and to
enhance the use of multi-user, multi-program systems. A
time-sharing environment is created by providing two
operating modes: kernel and user. These modes can operate
with or without relocation and protectione Mode selection
is made by using an expanded KDll-A processor status word.
The KTll-D option basically performs four functions:
a.

Expands the basic 32-K word address capability
to l28K words.

Provides address space with memory relocation
and protection for multi-user timesharing
systems ..

c..

Implements the separate address spaces for the
kernel and user modes of operation.

Provides memory management information for use
of memory in multi-user, multi-program systems.

4-37

The standard l6-bit word length of the KDIl-A processor limits
the memory address capability to 32K words. In addition, the
upper 4K of address space is always reserved for internal
register and external device

addresses~

The KTll-D converts

the l6-bit virtual address generated by the processor to an
18-bit physical bus address, thereby increasing the usable
memory address capability from 28K to 124K words.
Because the KTII-D option relocates all addresses automatically,
the KDII-A processor may be considered to be operating in a
virtual address space. This means that no matter where a
program is loaded into physical memory, it does not have to
be re-linked; it always appears to be at the same virtual
location in memoryo
In a multi-programmed, timeshared system, user programs must
be prevented from modifying or destroying the operating system"
The KTll-D option implements the kernel/user modes of operation
upon which the timeshared system is basedo The option uses two
sets of eight 32-bit Active Page Registers (APR)~ An APR is
actually a pair of 16-bit registers: a Page Address Register
(PAR), and a Page Descriptor Register (PDR). These registers
are always used as a pair and contain all the information
needed to describe and locate the currently active memory pages.
One PARjPDR set is provided for each mode of operation (kernel
and user). Logic within the KTII-D analyzes every memory

4-38

reference to enable the correct PAR/PDR set. Thus, a user
mode program, for example, cannot operate in the space
assigned to kernel programs.
In a mplti-program, multi-user environment, memory space
must be used in the most efficient method possible in order
to accomodate as many users as possible with minimum delay.
The KTll-D option maintains bits that indicate whether the
associated page has ever been written into. The software
memory management system can interrogate each PDR to determine
how that page had been used. This information enables the
software system to evaluate the overall use of available
memory space. For example, if an active memory page has
never been altered, the memory management system might, if
necessary, overlay that page with a new program requested by
a user. If a current active page has been written into, the
memory management operating system needs to be informed so
that the modified program can be rewritten into secondary
storage before the page is overlaid.
Specifications for the KTll-D Memory Management Option are
listed in Table

4-15

at the end of this paragraph. A detailed

description of this option is given in the KTll-D Memory
Management Option Manual, DEC-II-HKTDA-A-D.

4-39

Table 4-15
KTll-D Specifications

Memory Expansion

Expands PDP-ll/40 memory address
capability up to 124K words
0

Interface

Address line outputs compatible
with PDP-II Unibus

Timing

Timing derived from KDII-A processor

Delay

Adds 150 ns to every memory reference
when installed.

Operating Modes

Kernel and user

Available Pages

Provides 8 4K-word pages for each mode

Page Length

A page can vary in length from one
32-word block up to 128 32-word blocks
Maximum page length is 4096 words

Program Capacity

Eight 4096-word pages accomodate
32K-word programs
Q

Size

Single hex-size module (M7236)

4-40

KWII-L Line Frequency Clock
The I\wll-L Line Frequency Clock is a PDP-ll/40 Drocessor
option that provides a method of referencing real intervals.
This oution generates a repetitive interrupt request to the
processor. The rate of interrupt is derived from the ac line
frequency, either

Hz or

60 Hz. The accuracy of the clock

period, therefore, is dependent on the accuracy of this
freouency $ource.
The KWll-L Line Frequency Clock can be operated in either
an interrupt or non-interrupt mode. When in the interrupt
mode, the clock option interrupts the processor each

ti~e

it receives a pulse from the line frequency source. In the
non-interrupt mode, the c10ck option functions as a program
switch that the processor can examine or ignore. Mode
selection is made by the program.
Specifications for the KWII-L Line Frequency Clock Option are
listed in Table 4-16 at the end of this paragraph. A detailed
description of this option is given in the KWll ... L Line Time
Clock Hanual, DEC-II-HKlrIB-D.

4. . 41

Tahle 4-Ho
KT'Jll-L Specifications

2-bit status reaister
bit 06 - interrunt enable
bit 07 - interrupt monitor

777546

Vector
Address

100

~1ode

hit O~ set - interrupt mode
bit 06 clear - non-interrupt mode

Control

~1oni tor

Function

bit 07 can be used to serve as a partial
check on the origin of the interrupt vector

Interrupt Rate

same as line frequency;

Priority Level

BR6

Size

Single-heiaht module (M787) that mounts
in KDll-A processor slot ~3

50 or 60 Hz

4. . 42

4.3.6

KMII-A Maintenace Console Option

The KEII-A Maintenance Console (Also referred to as the
maintenance module) is a 2-module set containing 28
indicator lights and four switches used to monitor and
control functions during maintenance tests.
The functions monitored by the option depend on which
processor slot the module is installed in. Different
overlays are provided to indicate the fUnction being
tested. The module is installed in processor slot FOI
when testing the KDII-A processor and is installed in
salt EOI when testing the KTII-D or KEII-E,F options.
Use of the maintenance module, including a description of
the overlays, is given in the KDll-A Processor Manual,
DEC-II-HKDAA-A-D and in the appropriate option manuals. Also,

a detailed description of the option is presented in
the KDII-A Processor Manual.

4-43

Small Peripheral Controller Slot
Processor slot 09, sections C-F, permit installation of any
small peripheral controller options This slot is normally
used to install the controller for the PDP-Il/40 System
input/output console device, but may be used for any small
peripheral controller, if desired.
The standard controllers for system I/O devices are:
a.

DLII Asynchronous Line Interface - the standard
controller used for either the LA30-S DECwriter
or for the ASR 33 Teletype unit.

LCII DECwriter Control - a controller used when the
LA30-P DECwriter is used as the system I/O device.

KLII Teletype Control - an earlier version of the
Teletype Control which is used only with the
ASR 33 Teletype unit.

A brief description of the Lell and DL1I are given in
paragraphs 103.6 and 1.3.7, respectively, of this manual.
Detailed descriptions of all three controllers are included
in the related maintenance manual listed in Table 1-2.

4-44

4.4

MEMORY OPTIONS

Memories with different ranges of speeds and various physical
and electrical characteristics can be freely mixed and
interchanged in a single PDP-ll/40 System. The basic system
mounting box can house up to

56K of memory in addition to the

processor and processor optionso Additional memory units may
be added by using separate boxes B.nd power supplies. Each
box may be expanded up to 24K in 8K increments.
The following paragraphs describe four of the core memory
types that can be used with the PDP-ll/40 System. It should
be noted that core memories compatible with the PDP-ll/20
may also be used with the PDP-ll/40 provided they are mounted
in a different box and powered by an H720 power supply.

4-45

MMII-L Core Memory
The MMII-L core memory is a read/write, random access, coincident
current, magnetic core type memory with a cycle time of 900 ns
and an access time of 400 ns. The memory is organized in a 3D,
3-wire planar configuration. It provides 8192 (8K) 16-bit words
that are both word and byte addressable.
The memory is organized into 16-bit words, each word containing
two 8-bit byteso The bytes are identified as the low-order byte
(bits 00-07) and the high-order byte (bits 8-15)0 Each byte is
addressable and has its own address location. Low bytes are
always even numbered and high bytes are odd numbered. Full words
are addressed at even-numbered locations onlyc When a full word
is addressed, the high byte is automatically included. For example,
the 8K memory has 8,192 words or 16,384 bytes; therefore, 16,384
locations are assigned. Address 000000 is the first low byte,
address 000001 is the first high byte, 000002 is the second low
byte, 000003 is the second high byte, etc.
The MMII-L consists of three modules: a GIIO hex-type module
containing the memory control logic; a G231 hex-type module
containing the memory driver logic; and an H214 quad-type module
containing the memory core

stack~

4-46

The memory control logic acknowledges the request of the master
device, determines which of the four basic operations (DATI,
DATIP, DATO, or DATOB) is to be performed, and sets up appropriate
timing and control circuits to perform the desired read or write
operationo It also contains the inhibit drivers and sense
amplifiers as well as device selector logic to determine if the
memory bank has been addressed from the Unibus. The control logic
includes a 16-bit

flip-flo~

of a word after it is read out from destructive memory. This
same word can then be written back into memory (restored) when
in the DATI mode. The register is also used during DATO and
DATOB cycles to accomodate loading of incoming data from the
Unibus lines' into the core memory.
The memory driver logic includes: address selection logic that
decodes the incoming address to determine the core specifically
addressed; the switches and drivers that direct current flow
through the magnetic cores to ensure the proper polarity for
the desired function; and the X and Y current generators that
provide the necessary current to change the state of the
magnetic cores.

4-47

The ferrite core memory stack consists of

16 memory mats

arranged in a planar configurationo Each mat contains 8192
ferrite cores arranged in a 128 by

matrix. Each mat

represents a single bit position of a wordo Each ferrite
core can assume a stable magnetic state corresponding to
either a binary 1 or binary 0

Even if power is removed

from the core, the core retains its state until changed by
appropriate control signalso
Information for installation of the MMII-L in the BAII-FC
box of the PDP-Il/40 is noted in Table 2-2.

4-48

MFIl-L Core Memory
The MFll-L core memory is basically a standard MMll-L, 8K
core memory with the addition of a backplane. The backplane
provides the .interconnections between the core memory
modules. The MFIl-L is the normal memory supplied with the
PDP-ll/40 SystemG
Information for installation of the MFII-L in the BAll-Fe
box of the PDP-ll/40 is noted in Table 2-2.

4-49

MEll-L Core Memory
The MEIl-L is a complete memory system consisting of an
MMll-L core memory and associated backplane (MFll-L) housed
in its own mounting box which contains an integral power
supp1y@ This power supply and mounting box can accomodate
up to three MMII-L core memoriese In effect, the MEII-L can
be expanded up to

24K in 8K increments

The system mounting box is

inches high, 19 inches wide, and

20 inches deep and is designed for mounting in a standard
19-inch

cabinet~

Rack-mountable slides are included but the

box can be used as a stand-alone unit, if desired. In addition
to holding the core memory, backplane, and power supply, the
box contains all cables necessary for providing power and
for interfacing the units of the MEII-Lc It also provides for
connection to the Unibuso The rear of the box contains cable
clamps, a line cord for input power, a cooling fan for the
memory modules and power supply, and a power control circuit
breaker.

4-50

The system power supply converts single-phase l15V or 230V ac
line voltage to the two regulated dc voltages required by the
memory system: +5V for the logic and -15V for the core memory.
Both outputs are overvoltage and overcurrent protected. The
power supply also provides line power to the mounting box
cooling fan and the BUS AC

La and BUS DC La signals which are

sent to the Unibus in the event of a power failure.
The power supply consists of a power control, a power chassis
assembly, and a de regulator along with associated ac and dc
cables. The power control contains a thermal circuit breaker
which protects against input overload and is reset by depressing
a button on the rear of the mounting box. A thermostat in the
regulator opens one side of the primary circuit and deenergizes
the power supply if the temperature rises above 100

C. It is

automatically reset when the temperature reaches 63 0 Co

(
\.

4-51

MMll-S Core Memory
The MMll-S core memory is an MMII-L memory with backplane
and is capable of being interleaved in 16K segments o This
permits the m~ory to be expanded above the
the

MFll~Lo

24K

limit of

The prime physical difference between the MMll-S

and the MFII-L is that the MMll-S is a single system unit
while the MFll=L is a double system unit.
If the MMll-S is interleaved, it permits faster memory
operation o When interleaved, two adjacent contiguously
addressed 8K memory banks are used and successive memory
cycles are performed within alternate 8K memory blocks.

4-52

5.1

UNIBUS AND SYSTEM, OPTIONS

SCOPE

The purpose of this chapter is to provide a general
description of the Unibus that is used to interconnect
all major components of the PDP-II/40 System. In addition,
it provides brief descriptions of some of the Unibus
options (peripherals) that can be· used with the PDP-II/40.
Because of the'Unibus concept, these peripherals can be
used, without modification, with any member of the PDP-II
family of computers.
Detailed information on the Unibus and peripheral interfacing
is provided in the PDP-II Peripherals and Interfacing Handbook.

(
\

5-1

5.2

U1fIBUS

The Unibus is a single, common path that connects the processor,
memory, and all

peripherals~

Address, data, and control

information is transmitted along the

lines of the

bus~

The

form of communication is the same for every device on the
Unibus~

The same signal format is used by the processor to

communicate with memory and peripheral deviceso Peripheral

',J>

devices also use this format when coamunicating with the
processor, memory, or other peripheral devices.
All instructions applied to data in memory can be applied
equally well to data in peripheral device registers and
peripheral device registers may be manipulated as flexibly
as memory by the processor. This is an especially powerful
feature, considering the special capability of PDP-ll/40
instructions to process data in any memory location as
though it were an accumulator.
Most Unibus lines are bidirectional; therefore, the input
lines can also be driven as output linese This means that
a peripheral device register can be either read or cha.nged
by the processor or other peripheral devices, and the same
data lines can be used for transfer operations. Thus, the
same register can be used for both input and output functions.

5-2

Communication between two devices on the bus is in a masterslave relationship.

During any bus operation, one device

has control of the bus. This device, the bus master, controls
the bus when

communicat~ng

called the slave.

with another device on the bus,

A typical example of this relationship

is the processor, as master, fetching an instruction from
memory (which is always a slave).

Another example is the

disk, as master, transferring data to memory, as slave.
Master-slave relationships are dynamic.

The processor, for

example, passes bus control to a disk.

The disk, as master,

then communicates with a slave memory bank.

The Unibus is used by the processor and all I/O devices;
thus, a priority structure determines which device obtains
control of the bus.

Consequently, every device on the

Unibus capable of becoming bus master has an assigned priority.
When two devices, which are capable of becoming bus master,
have identical priority values and simultaneously request
use of the bus, the device that is electrically closest
to the

processor receives control.

Communication on the Unibus is interlocked between devices.
Each control signal issued by the master device must be
acknowledged by a response from the slave to complete the
transfer.

Therefore, communication is independent of the

5-3

physical bus length and the response time of the master and
slave devices. The maximum transfer rate on the Unibus with
optimum device design, is one 16-bit word every 400 ns, or
2e5 million 16-bit words per second.
Registers in peripheral devices are assigned addresses
similar to memory; thus all PDP-II/40 instructions that
address memory locations can become I/O

instructions~

Data

registers in devices can take advantage of all the arithmetic
and logic power of the processor. The PDP-II/40 controls devices
differently than most computer systemso Control functions are
assigned a register address, and then the individual bits
within that register can cause control operations to occure
For example, the command to make the paper-tape reader read
a frame of tape is provided by setting a bit (the reader
enable bit) in the control register of the device. Instructions
such as MOV and BIS may be used for this purpose

Status

conditions are also handled by the assignment of bits within
this register, and the status is checked with TST, BIT, and CMP
instructions

In addition, there is no limit to the number of

registers that a device may have, providing an unlimited
flexibility in the design and control of peripheral equipment.
The same bit locations in peripheral registers are assigned
to the same or similar operationo For example, regardless of
the device, bit 15 usually represents an ERROR flag.

5-4

A device (other than the processor) that is capable of becoming
bus master generally requests use of the bus for one of two
purposes:
a.

To make a non-processor transfer of data directly to or
from memory by means of a non-processor request (NPR).

To interrupt program execution and force the processor
to branch to a specific address where an interrupt
service routine is located by means of a bus request (BR).

The request and granting of bus mastership is performed in parallel
with data transfers on a completely independent set of bus lines.
Thus, while one device is using the bus, the next request is
being checked for priority and the next user is being assigned.
Because of this time parallelism, successive data transfers by
different master devices can occur at the full Unibus speed.
When a device capable of becoming bus master requests use of the
bus, the handling of that request depends on the location of
that device in the priority structure .. The following factors
must be considered to determine the priority of the request:
a.

The processor's priority is set under program control
to one of eight levels using bits 7,6, and 5 in the
processor's status register. These three bits set a
priority level that inhibits granting of bus requests
(BRs) on the same or lower levels.

Requests from external devices can be made on any
one of five request lines. Non-processor request (NPR)
has the highest priority, and its request is granted
by the processor between bus cycles of an instruction
execution. Bus request 7 (BR7) is the next highest
•
• +;:J
......
I
-1 owes t
prlorlvY
anu
uUS reques~ 4 \ Dfl4) 1S ~he
.L

"r'\T"'\1

• •

5-5

The four lower level priority requests (BR7 to BR4) are
granted by the processor between instructions When the
processor priority is set to a specific level, all bus
requests on that level and below are ignored. For
example, if the processor priority is 6, requests on
BR6 or any other lower level are not granted.
0

When more than one device is connected to the same
bus request line§ the device electrically nearer the
processor has a higher priority than the device further
away Any number of devices can be connected to a
specific BR or NPR line.
0

When a device other than the processor gains control of the bus,
it uses the bus to perform either a data or interrupt transfer.
Direct memory or device access data transfers can be accomplished
between any two peripherals without processor supervisiono These
are called NPR level data transfers.

Normal~y,

NPR transfers are

made between the memory and a mass storage device, such as a disk e
During NPR transfers, it is not necessary for the processor to
transfer the information between the memory and the mass storage
device. The bus structure allows device-to-device transfers,
thereby allowing customer-designed peripheral controllers to
directly access other devices (such as disks) on the bus. This
direct access capability permits operations such as a disk
directly refreshing a CRT display. An NPR device is allowed
extremely fast access to the bus and can transfer data at high
rates once it gains control. The processor state is not affected

5-6

by this type of transfer; thererore, the processor can relinquish

bus control while an instruction is in progress. This release of
the bus normally

occurs~at

the beginning or end of bus cycles;

however, the bus is never released between cycles of a readmodify-write sequence.
Devices that gain bus control with one of the bus request lines
(BR7, BR6, BR5, BR4) can take full advantage of the power and
flexibility of the processor by requesting an interrupt. The
entire instruction set is then available for manipulating data
and status registers. When a device servicing program is to be
run, the task being performed by the processor is interrupted,
and the device service routine is initiated. After the device
request has been satisfied, the processor returns to its
former taske Note that interrupt reque.sts can be made only if
bus control has been gained through a BR priority level. An
NPR level request can never be used for an interrupt request.

(
5-7

5 .. 3

UNIBUS OPTIONS

A large number of Unibus options are available for use with
the PDP-ll/40 System. A brief description of some of these
options is included in the following paragraphso For more
detailed information, refer to the associated hard,,,are
maintenance manual.

5-8

PCII High-Speed Paper-Tape Reader/Punch
The High-Speed Reader and Punch is capable of reading 8-hole
unoiled perforated paper tape at 300 characters per second,

and punching tape at 50 characters per second. The system
consists of a High-Speed Pa?er-Tape Reader/Punch and the
PCll Control. A unit containing a reader only (PRll) is
also available.
In reading tape, a set of phototransistors translate the
presence or absence of holes in the tape to logic levels
representing Is and Os to the presence or absence of holes
in the tape. Any information read or ,punched is paralleltransferred through the control. vfuen an address is placed
on the Unibus, the control decodes the address and determines

if the reader or punch has been selected. If one of the four
device register addresses have been selected, the control
determines whether an input or an output operation should be
performed. An input operation from the reader is initiated when
the processor transmits a command to the paper-tape reader status
register. An output operation is initiated when the processor
transfers a byte to the naDer-tape punch buffer reqister.
The control enables the PDP-II System to control the reading or
punchinq of paDer tane in a flexible manner. The reader can be
under direct program control or can operate without direct
sunervision through the use of interrunts to TIaintain continuous
operation.

5-9

5 .. 3,,2

LPII High-Speed Line

The LPII High-Speed Line

~rinter

is available in several

models, ranging from an 80-column,

~4-character

model

(LPll-FA) to an 132-colurrln, qf,-character model (LPll-II:8)"
Lither column-Nidth printer can be ordered vlith 64- or
96-character print sets" The printer is an impact type using
a revolving character drum and one hammer per column. Forms
up to six parts may be used for multiple copiesG Fanfold
paper from 4 inches to 14 7/8 inches wide may be used with
adjustment for pin-feed tractors. The print rate is dependent
upon the data and the number of columns to be printedo
Characters are printed 20 at a time (24 on the 132-column model)
and if 20 (or 24) or less are used, the .rate can be as high as
1100 lines per minute ..
An 8-bit value, representing a character to be printed, .is
transferred in parallel from the Unibus to the line printerG
The line printer then loads the character serially into the
printer memory via the line printer buffer (LPB) .. Hhen the
memory becomes full

(20 characters) the characters are

automatically printedo This continues until the full 80 columns
have been printed ·or a special character is recognized" The
l32-column model prints 24 characters at a time.

5-10

5.3.3

eRII Card Reader

Model CRll Card Reader reads EIA standard SO-column punched
data cards at 300 cards per

minute~

model CMII reads 40-

column mark-sense cards, which can have punched holes, at
200 cards per minute.

The punched card reader uses a vacuum picker which works
in conjunction with riffle air so that card wear is insignificant, card jam virtually impossible and the reader
extremely tolerant of damaged cards.

The riffling action

separates the cards in the input hopper to prevent sticking.
The picker uses a strong vacuum to grasp the bottom card and
deliver it to the read station on demand.

The picker and

associated throat block prevent the unit from multiple
picking to the extent that taped or stapled cards are not
allowed to enter the card track.
stops with pick check alarm.

In such cases the reader

The operator can separate the

cards and enter them into the input hopper for normal
reading.

The card track is very short, so that only one

card is in motion at a time.

The combination of damaged

card tolerance, gentle card handling, and short card track
provide virtually jam-proof operation.

Cards are read by column, beginning with Column 1.

A select

5-11

instruction starts the card moving past the read station.
Once a card is in motion, all 80 columns are read.

Column

information is read in one of two program-selected modes:
card image or compressed codee

In the card image mode 12

information bits in one column are loaded into the data
buffer and are available to the program at CRBl address.
In the compressed code mode, the card image is encoded into
8-bit bytes and is available to the program at CRB2 address.
A punched hole is interpreted as binary 1, and the absence
of a hole as binary

5-12

TCll/':!:U56 DEC tape

S~lsten

The TCII/TU56 is a dual-unit, bidirectional magnetic - tape
transport system for auxiliary data storage.

Low cost, low

maintenance and high reliability are assured by:
a. simply designed transport mechanisms which haveyno
no capstans and no pinch rollers.
b. hydrodynamically.lubricated tape guidiQg (the tape
floats on air over the tape guides while in motion)
c. redundant recording
d. Manchester recording techniques (virtually eliminate
drop-outs)

Each transport has a read/write head for information
recording and playback on five channels of tape.

The system

stores information at fixed positions on magnetic tape as in
magnetic disk or drum storage devices, rather than at unknown or variable positions as in conventional magnetic
tape systems.

This feature allows replacement of blocks of

data on tape in a random fashion without disturbing other
previously recorded information.

In particular, during the

writing of information on tape, the system reads format (mark)
and timing information from the tape and uses this information
to determine the exact position at
ation to be written.

which to record the inform-

Similarly, in reading, the same mark

and timing information is used to locate data to be played
back from the tape.

5-13
J

The DECtape system consists of the TU56 dual transport, the
TCll Control (which will buffer and control information for
up to four dual transports) and DEctape(3/4 inch magnetic
tape on 3.9inch reels~e

The system utilizes a IO-track read/write heade

On a tape

the first five tracks include a timing track, a mark track,
and three data tracks.

The other five tracks are identical

counterparts and are used for redundant recording to increase
system reliability.

The redundant recording of each character

bit on non-adjacent tracks materially reduces bit dropout
and minimizes the effect of skew.
phase recording,

The

use of Manchester

rather than amplitude sensi'ng techniques,

virtually eliminates dropouts.

5-14

':'l\Kll/~Ul,)

5 .. 3.5

n:P.Cr..l.aqtaT'e Svstem

The TMII/TUlO is a high-performance, low-cost magnetic
tape system ideally suited for writing, reading, and storing
large volumes of data

a~d

programs in a serial manner.

Because the system reads and writes in industry-compatible
format,

information can be transferred between a PDP-II and

other computers.

For example, a PDP-II might be used to

collect data and record it for later processing on a large
computer.

The 10 1}2 inch tape reels contain up to 2400

feet of tape upon which over 96 million bits of data can
be stored on high density 9-track tape or over 72 million
bits can be stored on high density 7-track tape.

The TMll/TUll employs read after write error checking to check
that proper data is writlEn on the tape.

dropout

Should a tape

be detected, appropriate action can be taken to

assume no loss of data.

Tape motion is controlled by vacuum columns and a servocontrolled single capstan.

Long tape life is possible

because the only contact with the oxide surface is at the
magnetic head and at a rolling contact on one low-friction,
low-inertia bearing.

(
5-15

RCll/RS64 DECdisk Memory
The RCll/RS64 is a fast,
storage system.

low-cost, random access, bulk

One RCll/RS64 combination provides 65,536, 16-

bit words of storage..

Up to four RS64 disks can be

controlled by one RCll Controller for a totalof 262,144
words of storage.

Disk functions include: look ahead,

read, write, and write check, as well as a "look ahead

The RS64 disk stores data in a 32 x l6-bit word block format.
Cyclic Redundancy Check (CRC) error detection is performed
automatically by the controller on a block basis, the blocks
being randomly addressableo
clock recovery system is
reliability.

~sed

A self-synchronizing, phaselock
to ensure exceptional data

This technique facilitates data recovery in

of restart after a power failure or during periods
of high shock or vibration ..
~

Fast track switching time permits spiral read and write.
may be read or written as
words.

32~word

Data

blocks from one to 65,536

When the last address on a track or surface has been

used, the RCll Controller will automatically advance to the
next track orto the first track of a new disk surface.

5-16

Each RS64 disk unit has a set of switches for write protecting
the disk.

The write Lock ENABLE/DISABLE switch determines

whether protection is desired or not.

If this switch is

in ENABLE position, writing data on tracks selected by five
switches is not allowed.

The setting of five switches

below the ENABLE/DISABLE switch forms a binary number that
corresponds to the number of a track; when write protection
is in effect, all tracks numbered from zero to the selected
number (path inclusive) are write protected.

Any attempt

to write in a write protected area will result in an error
indication by the controller.

5-17

RFll/RSll Disk SYstem
The RFll Controller and RSII Disk combine as a fast,
rand9m-access bulk-storage package for the PDP-lIe

low-cost
One

RSII and the RFll provide 262,144 17-bit words (16 data
bits and 1 parity bit) of storageo

Up to eight

RSII disks can be controlled by one RFll for a total of
2,047,152 words of storage.

The Wll/RSll is unique· in fixed head disks because each
word is addressableo

Data transfers may be as small as one

word or as large as 65,536 words..

Individual words or

groups of words may be read or rewritten without any limits
of fixed blocks or sectors, providing optimum use of both
disk storage and ma:n memory in the PDP-II systemo

The RSII contains a nickel-cobalt-plated disk driven by a
hysterisis synchronous motorc

Data is recorded on a single

disk surface by 128 fixed read/write heads.

Fast track- swi tching time permi ts spiral read or wri te..

may be written in blocks from 1 to 65,536 words.

Data

The RFll control

automatically continues on the next track, or on the next
disk surface, when the last address on a track or surface
has been usede

5-18

The disk st0res data words in a 22-bit format which includes
guard bits and a sync bit to operate the self-clocking logic
of the RSll Disk logic.
the data
data.

strobin~

The sync bit adjusts the timing of

to ensure proper recovery of each word of

The RSll has a,redundant set of timing tracks,

recorded exactly in phase with the primary timing tracks.

5-19

RKII-C DECpack Disk Cartridge Svstem
The DECpack cartridge disk drive and control is a complete mass
storage system, offering an economical solution for large
volume, radom-access data storage..

The system includes a

modular mass storage device utilizing removable disk cartridges and a complete easy-to-program control o

The DECpack is available in two models: The RK02 drive with
over 600,000 words per drive; and the RK03 drive with over
1 .. 2 million words of storage per drive ..

The DECpack is ideal where a large volume of programs and
data are developed and maintained for one or more usersQ
When used with PDP-II software such as the Disk Operating
System or RSTS-ll System, DECpack offers the flexibility of
permitting each member of a group of users to maintain his
own private program and data files.

It is expandable up to

4.8 million words (RK02) or 9,,6 million words (RK03 or RK05) per
controller ..

The removable disk cartridge offers the flexibility of
virtually unlimited off-line capacity with rapid transfers
of files between on-line and off-line without copying operations.

It utilizes a cartridge similar to the IBM 2315,

but with 12 sectors"

5-20

Average total access time on each drive is 90 milliseconds.
On expanded systems, operations are overlapped for efficiency;
one drive may read or write while one or more additional
drives are "seeking new

~ead

positions for the next ransfer.

All data transers utilize the non,-Processor Request facili ty
during transfers.

Each disk is permanently mounted inside a protective case
that automatically opens when inserted in the disk drive.
While on-line, dust contamination is prevented by a highlyefficient continuous "absolute" air filtration system.

The DECpack provides accurate data storage and transfers
by means of a write check function, correct cylinder verification by hardware, hardware checksum, and hardware
maintenance features.

There are no mechanical detents, thus

a major source of wear and critical adjustment is eliminated ..

(

5-21

VTOI Storage Displav
The VT01A is a Tektronix Model 611 direct-view storage tube
with a resolution of 400 stored line pairs vertically and
300 stored line pairs horizontally.

Dot writing time is

20ps , with a full screen erase time of 500 ms.

The VTOl

can display 30,000 discrete resolvable points.

The VTOIA is interfaced to the Unibus and controlled via the
AA1I-A and AA1I-D conversion subsystem.

5-22

5.3010

VROI Oscilloscope Displav

The VROlA, a modified Tektronix

ty~e

Rm504

oscilloscope,

provides accurate measureMents in DC-to-4S0 KHz applications.
It is a low-frequency, hiqh-sensitivitv nisplav and can be
used for accurate curve nlottinq in the X-Y mode of
operation.
The VROI is interfaced to the Unibus and controlled by
means of the AAll-B and AAll-D Digital-to-Analoq Conversion
Subsystem.

(
5-23

5.3.11

VR14 Point Plot Display

The VR14 is a completelY self-contained CRT display '{vi th a
6.75 by 9-inch viewino area in a compact 19-inch package.
The VRl4 reauires only analog X and Y position information
with an intensity pulse to generate sharp, bright point
plot displays. Except for the CRT itself, the unit uses all
solid-state circuits 'vith high-speed magnetic deflection to
enhance brightness and resolution .. The intensity pulse may
be time mul tiplexed or gated bv a separate innut to allo'i;1
the screen to be timeshared between two inputs .. The display
unit is available in rack-mountable or stand-alone models ..
The VR14 is interfaced to the Unibus and controlled through
the AAIl-C and AAIl-D Digital-to-Analog Conversion subsystem.
A two-color display (VR20) is also available .. It is used
with the AAll-E and

~AlI-D

Diqital-to-Analog Conversion

subsvstems ..

5-24

5.3 . 12

\TTO ~ ?\lphanumeric Display

The VT05 is a flexible, hgh performance alphanumeric display
terminal with a cathode ray tube display and communications
equipment capable of transmitting data over standard phbne
lines and data sets at half or full duplex at rates up to
300 Baud.

It is contolled by the DLll, the same controller used with
Teletype terminals, or it may be used over a Bell 103A
or equivalent modem.

5-25

RTf') 1

nI~Clink

Terminal

DEC-link is a low-cost, self contained data entry device
which is remotely locatable.
serial line compatibility.

It features Teletype and EIA
DEC-link offers 16 unique

keyboard characters which a monitoring computer may use for
either

nu~eric

data or control functions.

It can display

up to 12 digits of decimal data (plus decimal point) as
well as status indicators.

Data is entered via an integral l6-character keyboard;
numeric data is displayed

locally.

non-numeric information

indicators are used to indicate
such as

repeat transmission",

The status

computer ready!!

etc. Four

programmable status indicators are standard on DEC-link.

The DLll. Control may be used with the RTOl for direct connection
or it may be used over a Bell l03A or equivalent modem.

5-26

5.3.14

Communications Options

DIGITAL has extended the PDP-II's adaptability to various
communications applications with a variety of interfaces.
These devices enable the PDP-II to be connected both locally
and remotely to serial asynchronous and serial synchronous
lines.

The interfaces allow both full and half duplex

operations with connections to communications terminals via
the standard EIA RS232-C and CCITT interface. The devices
are summarized bebw:

('
\

DEVICE

INTERFACES PDP-ll WITH:

DCll

Serial Asynchronous Line

Connects PDP-II to
various asynchronous
terminals, or to
another computer via
a common carrier
communications facility.
Has program controlled
Baud rates, character
lengths, and stop codes.

DPII

Serial Synchronous Line

Connects PDP-II to local
or remote computers and
terminals via high speed
serial line.

DNII

Autocalling Unit

To dial remote computer
or terminal ..

DMII

Up to 16-serial
Asynchronous Lines

Terminal-oriented systems
for timesharing, message
switching, store and
forward, data collection:
remote concentrators.

Serial 8-bit
Asynchronous Line

Connects PDP-II to local
teletype connections
and local 8-bit current
mode devices.

DLII

TYPICAL USES

5-27

DLII

Serial 8-bit
Asynchronous Line

Connects PDP-II to local or
remote 8-bit ErA-compatible
asynchronous terminals such
as CRTs, plotters, card
readers, and line printers.

5-28

5.3.15

APCll Low-Level Analog Input Subsystem

The AFCll is a flexible, high performance, differential analog
input subsystem for IDACS-II industrial data acquisition control
systems.

The AFCll system multiplexes up to 1024 differential input
analog signals, selects gain, and performs a I3-bit analogto-digital conversion at a 200 channel per second rate under
program control. Three signal conditioning modules and eight
program-selectable gains allow the system to intermix and
accept a wide range of signals: low level (lOmv f.s.),
level

(lOO~Ov

f.s.),

high

and current inputs (1 to Sarna f .. s .. ).

Designed for accurate and reliable operation in demanding
industrial environments, the AFCll achieves high isolation
and common mode noise rejection through relay switched
capacitor mUltiplexing.

The subsystem also simplifies input

wiring, requiring only simple twisted pairs which connect
to screw terminals.

Modularly constructed in eight-channel standard hardware
units, the AFell is easy to configure to user applications,
and simple to expand.

The analog input subsystem is particularly suited for data

5-29

acquisition in the high noise environments encountered in
process monitoring and control, production testing and laboratory
applications.

In such environments common and normal mode

noise, cabling and grounding problems can greatly affect the
operation of such transducers as thermocouples, strain gages,
analytical bridges, and .industrial milli~mp, current transmitters.
These problems can also affect the accuracy and performance
of the measuring system.

In typical applications, use of ungrounded sensors could cause
common mode voltages of up to 150 volts peak-to-peak (at power
line frequency) to appear on the jnput signal leads to the
measuring

system~

For example, if termocouples become

ungrounded during operation, large cornman mode voltages can
appear in coincidience with the signal. The design features
of the AFell allow either" floating or grounded signal sources
thus insuring reliable, trouble - free operationo

Due to

the flying capacitor design, the system tolerates common
mode voltages in excess of 200 voltso

FET solid-state

multiplexers, in contrast, can be seriously damaged with common
mode voltages over 25 volts.

5-30

5.3 .. 16

ADOl-D Analoq-to-Digital Conversion Subsystem

The ADOI-D is a flexible, low-cost multichannel analog
data acquisition option which interfaces directly to PDP-II
computers.

When it is under computer or external clock

control, the ADOl-D rpovides la-bit digitizatinn of unipolar
high-level analog signals having a nominal full-scale range
of a to _1.25, +2.5, +5.0 or +10.0 volts.

An optional sign-

bit addition allows II-bit bipolar operation.

Programmable

input range selectinn extends the ADOl-D's dynamic range at
moderate sampling rates the the equivalent of 13 bits for
unipolar signals or 14 bits for bipolar signals.

An optional sample-and-hold amplifier reduces the conversion

aperture to 100 nanoseconds.

Available as a factory or fEld-installed PDP-II option, the
standard ADOI-D consists of an expandable solid-state
input multiplexer, programmable input

range selector,

AID

converter, control, and bus interface in a single 5 1/4 inch
rackmountable assembly plus a separate logic power supply.
The multiplexer can be expanded by adding 4-channel modules
up to 32 channels.

An expansion multiplexer may be added to

provide a manimum configuration of 64 channels.

5-31

The subsystem is well suited to a variety of tasks-testing u
monitoring, logging, and analytical instrument data reduction _
in both laboratoy and manufacturing environments

It is also

a first choice with OEMls and system contractors as an
economic and efficient system component for sophisticated data
acquisition systems

5-32

5.3.17

AA11-D Digita1-to-Analog Conversion Subsystem

The AAll-D is a low cost, high performance multichannel
digital to analog conversion subsystem for PDP-II computers.

Interfacing directly tQ the PDP-II Unibus, the AAIl-D controls
up to four single buffered, 12 bit bipolar digital to analog
converters. Each BA614 converter, which includes Dutput
amplifier and reference voltage source, is contained on a
plug-in module and provides 10 rna current output at +10
volts.

Full scale output voltage is timpot adjustable from

+lv to +lOv in two ranges.

storage scope, display scope, and light pen control options
are available for the AAll-D. These options provide Z axis
blanking for intensity control and require two D/~ converters
to control X and y trace coordinates

Available as a factory or field installed option, the AAll-D
fully implemented with four digital to analog converters and
a scope control option, is contained in a single System Unit.
A rack mountable power supply is separate.

(
5-33

6 .. 1

EQUIPMENT MOUNTING AND POWER

SCOPE

The purpose of this chapter is to provide detailed information on the
PDP ... 11/40 mounting and Dower system ..

The BA11-FC mounting box is basic to the PDP-11/40 mounting system and
is discussed in paragraph 6 .. 2.

System unit allocations as well as

processor and basic memory slot allocations are noted for the basic
box..

This mounting information is presented in context with the

system mounting space within the same cabinet and in adjacent cabinets
(paragraph 6.3).

System power is provided by a cabinet ac power control unit (paragraph
6.4) and a basic power supply..

This power supply (paragraph 6.5)

consists of an H742 bulk power supply and its individual H744
and H745 (-15V) regulators..

(+5V)

These three items are covered separately

in paragraphs 6.5.1 through 6.5.3.

Basic dc power distribution is covered in paragraph 6.5.4 and troubleshooting of the power system is described in paragraph 6.5.5.

6-1

6.2

SYSTEM MOUNTING BOX

The major components of the PDP=11/40 System, with the exception of
the power system and console I/O device, are mounted in a single
BA11-FC mounting box. Space for additional memory and/or peripheral
interfaces is also provided within this· mounting box.

The BA11=FC mounting box is mounted in a standard DEC H960 m C cabinet
as shown in Figure 6 1.
n

The box is mounted on Chassis slides so

that it can be pulled out for maintenance and/or installation of logic
modules; the power supply, however, remains within the cabinet.

Cooling

fans are mounted on top of the box to provide proper cooling of the
logic elements within the box.

The KY11-D Programmer's Console is

located on the front of this box.

The mounting box is capable of holding nine system units or
equivalents.

Each system unit casting contains four slots for

mounting logic modules.

An alternate double system unit contains nine

slots as it has no center casting@

This double system unit is used

for the KD11=A processor and MF11=L memory.

Allocation of logic within the box is shown in Figure 6-2. A double
system unit (with nine slots) is used for the processor and processor
options. Another double system unit is used for the MF11-L core memory
which includes three modules to provide a basic 8K memory_ This leaves
space for five additional system units (or equivalents) for additional
memory and/or peripheral interfaces. Note that core memory should always

6-2

be placed asclose to the processor as possible. The basic mounting
box provides mounting space, power, and cooling for these additional
(expansion) units.

Module allocations for the processor, memory, and programmer's console
are covered in

paragraph~

6.2.1 through 6.2.3, respectively.

Whenever an expansion item is added to the basic box, certain factors
must be considered such as the number of system units required by
the device, power cable connections, Unibus connections, and jumpers.
Power cable connections are covered in paragraph 605, Unibus interconnections are discussed in paragraph 6.3.2. When certain devices
(such as the KT11=D, KJ11-A, etc.) are installed in the box, it is
often necessary to cut jumpers both on the new device and on an
existing device (such as the processor). Pertinent junper information
is included in the manual covering the device. However, information
on the KT11-D, KE11-E, KE11-F, and KJ11-A processor options is also
included in Chapter 2 of this manual.

(
6-3

_ _ _ _ _ _ _ 860 POWE"R CONTROL 1
860A: 11:" Vae
8608: 230 Vae

(HIDDEN)
AC POWER
RECEPTACLES

CABLE SUPPORT STRAP
AND CABLE HARNESS

H742
POWER SUPPLY
WITH REGULATORS ----+-ii+---+i+-~..-----.....:::..:~il>'1l'l
BOX

.:.r::--".?:""""~~ UPPER LOGIC FANS

CONSOLE

11-1386

Figure 6 ... 1

PDP-11/40 System Cabinet
6 ... 3A

MF11-L 8K
CORE MEMORY
DOUBLE SYSTEM
UNIT, 9 SLOTS
I

A
B

C
SECTIONS

E
F

I
I

I
I
I
I
I

I
I
I
I
I
I
I

KY11-D

~ PROGRAMMER'S

CONSOLE

SPACE FOR
ADDITIONAL MEMORY
OR PERIPHERAL
INTERFACES

KD11-A PROCESSOR
DOUBLE SYSTEM
UN ITS, 9 SLOTS

5 SINGLE SYSTEM
UN ITS OR EQUIVALENT

LEFT SIDE VIEW
(MODULE VIEW)
11-1570

:(
\

Figure 6 ... 2

PDP-l1/40 Mounting Box (BA11=FC)
6 ... 3B

Processor Module Allocations

Figure 6-3 shows the module allocation for the KD11-A double system
unit for the basic KD11-A processor and processor options. The modules
noted with an asterisk are the standard basic modules and must always
be presente Other modules are optional with the specific option
designation noted on the figureo The KT110D Memory Management option
KM11~A

requires the M7237 module in addition to the M7236 moduleo The

Maintenance Console option may be plugged into either slot F1 or E1
depending on whether the user is monitoring the basic KD11-A processor
or one of three processor options (KT11=D, MeMory Management, KE11=E,
Extended Instruction Set, or 1\E11-F, Floatin0 Instruction Set)

6-4

:::u
o
=E

I
I

"T1

I
I

,
,

___ I

- -'-

(')

I
I

- -

(J)

-i

SMALL PERIPHERAL CONTROLLER
(USUALLY DL11)

UNIBUS (M981)

KT11-D MEMORY MANAGEMENT OPTION (M7236)

RS64 OR
DMI1-AA

CARTRIDGE
DISKS

RS!1

RFll
CONTROL

RS11

RK05

RS1!

RSII

RK05

H960-D

AD01-D

RS!!

TMll
CONTROL TU56-H

PROCESSOR
CAB I NET

RK!1
CONTROL IVT01-A OR
VR01-A OR
BAI1-ES
BAilOR
PCl1

PDP-11/40
PROCESSOR

FREE - STAN DING
110 UNITS
CR11 OR
CDll
CARD
READER

LPII
LINE
PRINTER
94 OR 96
CHAR

LA30
DECWRITER

11-1572

Figure 6-5 Typical MUltiple Cabinet System Configuration

Table 6'"
Timing Characteristics of PDP-11 NPR Devices

NPR

Worst Case

Time Between Data

Priority

Device

Latency (usee)

Available (usee)

RK11/RK03

8.5

1 1 .. 1

RP11

*14.8

RC11

RF11

RK11/RK02

22 .. 2

TM11

32 (at 800 bpi)

TC11

200

DM11

100

11 9 (at 1200 baud)

CD11

800

DR11 ... B

Dependent on
customer use

*The RP11 transfers two words eaeh 14.8 microseconds

6-11

Table 6 ... 2
Priority of Devices Affected by BR Latency

Priority

BR7

BR6

BR5

BR4

*AD01

KW11"'L

DP11 @ 9600 baud or higher

KL11

DT11 ... B

TC11

DC11

CR11

DP11 @ 4800 baud

CM11

DC11 @ 1200 baud

KW11..,P

DP11

2400 baud

tUDC11

DC11

600 baud

DP11

2000 baud

DC11

300 baud

DM11

**DR11-A

DR11 ... B

*For AD01 sampling at hi9h rates

1800 baud

**Priority positions depend on customer applicationa

** AFe11

Can be assigned to a lower level for

slow input applications a

t UDC immediate

+UDC11

BR6: UDC deferred

6-12

BR4.

6.4

POWER CONTROL SYSTEM

Both the basic and expanded versions of the PDP-11/40 include a
power control system that controls ac power to system components,
permits operation of the entire system from a single master switch,
and shuts down the entire system in the event of fire in any cabinet.
This power control system is functionally the same for all PDP-11
computers and consists of the following:

cabinet-mounted power control unit

a master power switch (OFF/POWER/PANEL switch on

progra~mer's

console of the PDP-11/40)

cabinet-mounted thermal switch

A specific PDP-11/40 system may use either an 860 or 861 power control
system. The 860 power control unit is described in paragraph 6.4.1
and the 861 power control unit is referenced in paragraph 6.4.2.

(
6-13

6 .. 4 .. 1

860 Power Control Unit

The 860 power control unit is operated from the console panel switch
and is capable of switching up to 30A of 115 Vac (860A) or up to
15A of 230 Vac (860B) .. The power control unit distributes ac
voltage to two output strips located within the cabinet .. One strip
provides

~witched

(or controlled) ac powerJ that is, any component

plugged into this strip is under control of the master switch e The
second strip provides unswitched ac for operating devices that require
continual application of power, such as magnetic disk drives .. These
strips permit all system devices to be connected within the cabinet,
thereby necessitating only one power cord from the cabinet .. In the
basic PDP11/40 cabinet the right strip (as you face the cabinet from
the f'ront)

is the swi tched or controlled ac power strip.,

In multiple cabinet configurations, operation of the entire system can
be controlled by the consoleOFF!POWER/PANEL switch provided there is
at least one power control unite However, any systems containing more
than one processor require a master switch that is separate from the
processor console switch ..

The cabinet-mounted thermostat removes power from the switched ac
power strip in the event of fire in any

cabinet~

A power control bus cable is used to interconne'ct all devices in the
system G Devices may be added to the system by connecting them to the
bus in parallel at any convenient pointe No terminators are required on

6-14

the bus and 6GT"

connections may be used without any restrictions. The

power control bus cable is a 3-wire cable joining two 3=wire male
Mate-N-Lok connectors. Detailed instructions for interconnecting devices
are given in paragraph 6.4.1.1.

(
6-15

860 Physical Description

The 860 power control unit consists of an input circuit breaker, line
filter, pilot light, relay, output filter, control board, and thermal
detector e These components are housed in an enclosure which is mounted
in the top of the system cabinet next to the cabinet air intake fano
The bottom of the enclosure contains three 3 m pin Mate-N-Lok connectors,
a REMOTE/OFF/LOCAL switch, and the detection element of the thermal switchQ

The three connectors are wired in parallel to accept connection from the
standard 3-wire control systeme These connectors permit interconnection
of power control units from one system cabinet to another Q The
REMOTE/OFF/LOCAL switch permits all system power to be controlled by
one power control unite When set to LOCAL, it allows the specific power
control unit to be removed from the overall power system so that it can
be run independentlYe In a system containing more than one power
control, interconnecting cables would be installed between the connectors
of adjacent power control units in a daisy chain manner to provide
system power control (Figure 6 s 6)o In this instance, the switch
would be set to REMOTE to allow routing of power control fromone
cabinet to another o

6-16

860
POWER CONTROL
(PROCESSOR CAB IN E,T)

1 2 3) (1

123)(123
1

860
POWER CONTROL
(ADDITIONAL CABINET)

I I

70090 5~ ........
CAB LE

~
1 2

860
POWER CONTROL
(ADDITIONAL CABINET)

-I

1 2 3) (1

23»

I I

I
7008288
CABLE

PDP-11140
CONSOLE
(KY11-D)
11-1573

Figure 6-6

Power Control Interconnection
6-16A

860 Functional Description

The 860 power control unit has two main functions:

to route ac power

from its line cord to an unswitched ac power strip and to switch
the incoming ac on another power strip when the console switch is
closed to turn on the systemo The PDP-11/40 system may use either an
860A or 860B power control unit. The differences between these two
models are listed in Table 6-3.

The power control operates on a 3-wire parallel control. The three
lines are:

Line 1

power on

Line 2

emergency off

Line 3

ground

If neither Line 1 or Line 2 is connected to Line 3, the system is in
a power off state.

When lines 1 and 3 are connected through the console switch, operation
of the switch causes activation of the power relay within the 860
power control and provides input power to the switched or controlled
ac power stripe Connecting Lines 2 and 3 causes an override of any
other state of the power control and removes the switched ac power
by opening the 860 power control internal relay.

Line 2 is utilized by the thermal detector to provide protection in
case of fire or excessive heat.

6-17

Table 6 ... 3
Model Differences'

Item

Model

860A

860B

Input line voltage

115 Vac

230 Vac

Circuit breaker CB1

30A

15A

Transformer T1 primary

115 Vac

230 Vac

Input power line cord

115 Vac

230 Vac

30A

15A

25 feet

PIN 1203485

PIN 1204687

I;,..

6-18

6.4 .. 1.3

860 Circuit Description

The basic 860 power control circuit is shown in Figure 6-7. A pilot
light on the line side of the circuit breaker lights when the ac line
cord is plugged into the wall and power is applied to the unit. The
voltage from the secondary of transformer T1 is half-wave rectified
to provide +24V which is used to provide B+ to control transistors Q1
and Q2, and to energize relay K1. The transformer secondary is fused.
f

In the event the system is connected properly and ac power is applied
to the power control but no output is present on the switched ac strip,
this fuse should be checked. Note that power is available on the
unswitched ac power strip in this case because it is tapped off the
line and does not pass through relay K1.

When the power control is used as a switched power control, the
REMOTE/OFF/LOCAL swi tch S 1 is set to REf·tYOTE .. l'Jhen the console
OFF /PO'~'ffiR/PANEL swi tch is set to P01"ffiR,

it completes a ground

circuit that causes Q1 to cut off .. When Q1 cuts off, Q2 conducts
and causes relay K1 to energize, which closes the switched ac output
circuit .. Other connectors are provided to allow remote power control
switches to perform the same function as the console switch (close
the circuit between pins 1 and 3)

remote power switch would be

used, for example, in systems containing more than one processor.

Thermal switch S2 provides protection against fire or excessive heat ..
It is normally open but closes if the cabinet ambient temperature

(

exceeds 130o F (540
C • )
When.1t closes, Q2 cuts

6-19

.
relay K1 deenerg1zes,

and the switch connects Line 2 (emergency off)

to ground, thereby

switching off the ac output& Pin 2 on connectors J1, J2p and J3 permits
additional thermal switches (in the cabinet and extension mounting
box) to be connected in parallel with thermal switch 82 to perform
the same function. The switch opens to restore power once the temperature
o

falls below 85 FQ

When the power control is used as an unswitched power control,
REMOTE/OFF/LOCAL switch 81 is always set to LOCALe Thus, Q1 is
always cut off, Q2 always conducts, and K1 remains energized. Relay
K1 is deenergized, thereby removing power from the switched ac power
strip, only if there is an input power failure or if an overternperature
condition occurs.

6-20

6.4.2

861 Power Control Unit

A specific PDP-l1/40 system may use an 861 power control unit rather
than an 860. The 861 power control is a later version and is available
in three different models:

861A - 115 Vac, 50/60 Hz, 2-phase

861B - 230 Vac, 50/60 Hz, single phase

861C - 115 Vac, 50/60 Hz, single phase

A detailed description of the 861 power control unit is given in the
Type 861-A, 861-B, 861-C Power Controller Maintenance Manual.

(
6-21

6.5

PDP11/40 Basic Power Supply

The basic PDP11/40 power system consists of the power control unit,
the ac power distribution strips, power distribution for the cabinet and
basic box fans, and a modular power supply for regulated de voltages.

A block diagram of the basic power system is shown in Figure 6.8. The
power control unit (860 or 861) and the ac power strips have already
been discussed. The distribution for cabinet fan power is the unswitch
ac power strip with the basic box fans receiving power through the
H742 bulk power supply. The PDP11/40 Modular Power Supply (Figure 609)
consists of this H742 bulk power supply, two H744 +5V regulators and
two H745 =15V regulators. These elements of the modular power supply
are discussed in detail in paragraphs 6.5.1 through 6.5.3, respectively.

Please note that these details are for theory of operation and offaline
repair. Maintenance should consist of replacement per paragraph 6.5.5.

DC power distribution and cabling are covered in paragraph 6.5.4 with
information on expansion provided. Power supply maintenance is
covered in paragraph 6.5.5.

6-22

,~,

OPTIONAL H744

115/230 VAC

0"\
I

tv
tv

115/23

860
POWER CONTROL

20""30VAC
1

SWITCHED
AC
POWER
STRIP

H745

-15V

BULK
SUPPLY
POWER CONTROL

REMOTE
CONTROL
THERMAL
CUT OFF--------~
SENSORS

CPU DC DISTRIBUTION
BACKPLANE

BULK SUPPLY
AND REGULATOR
FANS

UNSWITCHED
AC
POWER
STRIP

POWER
DISTRIBUTION
, CABLE HARNESS

SYSTEM UNIT POWER
DISTRIBUTION BOARD
115/2:30

LOGIC FANS

CABINET FAN
11-1387

Figure 6-8

PDP-II/40 Power System Block Diagram

115/230 VAC
11-1384

Figure 6-9

PDP-11/40 Power Supply

6.5.1

H742 Bu1.k Power Supply

The H742 power supply is functionally divided into two major parts:

Bulk Power Supply (drawing D-CS-H742-0-1) - used to provide
~he

various ac input voltages required by the fans, regulators,

and power control board.

Power Control Board (drawing C""CS-S409730"'O ... 1) ..... used to
provide +15 and +8 voltages, line clock, and AC LO and
DC LO sighals for system use.

The PDP-11/40 power system operates with 115 Vac or 230 Vac primary
source power inputs. Although different 860 (or 861) power control
units are provided for each input voltage, the same H742 power
supply can be used with both versions. Jumpers are connected to
terminal strip TB1, 'tvhich is the primary of power supply transformer
T1, so that it can operate with the selected input voltage.

If 115 Vac operation is required, jumpers are placed between pins
1 and 2, and between pins 3 and 4 of TB1. If 230 Vac operation is
required, a jumper is connected between pins 2 and 3.

Line power is applied through TB1 to the primary of transformer
T1. The transformer secondaries provide 20-30 Vac input power for
the regulators and power control board as well as 15-24 Vac power
for the power control board. Power to cooling fans is tapped directly
from TB1 and does not corne from the transformer.

6-23

The power control board portion of the power supply (drawing
C-CS-5409730-0-') provides +15 and +8 Vdc outputs, a clock
ou'tput used to drive the KW11-L Line Frequency Clock option, and
the AC LO and DC LO control signals used for power fail sequences.
These outputs are discussed in paragraphs 60501.' through 6.5.'.3

6-24

6.5.1.1

+15V and +8V of the H742 Supply

The power control board of the H742 supply contains a +15V/+8V
dc supply and is described on print C-CS-5409730-0-1. This dc
supply receives 15-24 Vac from the secondary of transformer T1.
This ac input is full-wave rectified by diode bridge D1. The resultant
dc is applied to Darlington power amplifier Q1, through fuse F1.
The bias on Q1 is controlled to provide +15 Vdc at output pins 2
and 3 with respect to output pins 4, 5, and 6 (ground). If the Q1
collector voltage starts to increase, the bias at the base of Q2
increases, and Q2 conducts slightly more current to maintain a
constant output voltage. Zener diode D7 provides approximately
+8 Vdc at output pin 1. When DC LO is grounded at output pin 9,

Q2 conducts hard to cut off Q1 completely; thus removing both the
+15V and +8V outputs.

6-25

6.5.1 .. 2

Clock OUtput of the H742 Supply

The CLOCK output is derived off one leg of full-wave rectifier
bridge D1 by voltage divider RIO and Rl1, and Zener diode D2. The

CLOCK output is a 0 to SV square wave at the line frequency of the
input power source (47 to -63 Hz)

The CLOCK output is used to drive

the K\tV11 .... L Line Frequency Clock option, which mounts in slot F3 of the
processor backplane or the

ID~11ap

option, which can be mounted in

the Small Peripheral Controller slot. Operation of the KW11mL
option is described in the KD11-A Processor Manual; operation of
the

K~v11

.... P is described in its manual

6 .. 26

I\>

6.5.1.3

AC LO and DC LO Circuits

The AC LO and DC LO control signals are used to warn the processor
that a power failure is imminent so that the processor has time to
perform a power-fail sequence. If there is an ac power failure
(line power or bulk supply failure), AC LO is asserted on the bus
followed by DC LO. Sufficient time exists between these signals to
allow storage of volatile data and the conditioning of peripherals.

The 20-30 Vac input from the secondary of transformer T1 is applied to
the AC LO and DC LO sensing circuits on the power control board. The
ac input is rectified and filtered by diodes D8 through D11, and
capacitor C3. A common reference voltage is derived by resistor
R18

and zener diode D12. Both sensing circuits operate in a similar

manner. Each contains a differential amplifier, a transistor switch,
and associated circuits. The major difference is that the base of
Q6 in the AC LO circuit differential amplifier is at a slightly
lower value than that of Q9 in the DC LO differential amplifier.
The operation of both sensing circuits depends upon the voltage across
capacitor C3.

When AC LO is being sensed, the 20-30 Vac input is rectified and
stored in capacitor C3 which charges and discharges at a known
rate whenever the ac power is switched on or off. Thus, the voltage
that is applied to the emitters of differential amplifier Q6/Q7
through R17 is a rising or falling waveforn of known value. For
example, when

~ower

fails, or is shut down, the dc voltage decays

6-27

at a known rate as determined by the RC time constant. If the voltage
decreases to approximately 20V, the base of Q6 becomes negative with
respect to the base of Q7. The increased forward bias on Q6 causes
it to conduct more and the resultant decrease in Q7 causes it to cut
offo This removal of voltage across R16 causes Q5 and Q4 to conduct,
grounding the AC La line at pin 8. The AC La signal is applied
through the cable harness and processor backplane to the processor
power fail initialize logic so that the power fail sequence can be
started.

The DC LO sensing circuit operates in a similar manner to the AC La
sensing circuits The prime difference between these two circuits is
the voltage level at which they '6trip."

For example, if the ac input

starts to decrease, as a result of a power failure or shutdown, the
AC LO lines are grounded before the DC LO lines. As power is restored,
the ground is removed from the DC LO lines before it is removed from
the AC LO lines. The DC La signal is also applied to the power fail
initialize logic.

A description of how the AC LO and DC LO control signals are used
in the KD11 ... A processor is provided in the KD11=A Processor Manual.

6-28

6.5.2

H744 +5V Regulator

Two H744 +5V regulators are used in the basic PDP-11/40 Power System.
The H744 circuit schematic is shown in drawing D=CS-H744-0-1. The
following paragraphs describe the regulator circuit, overcurrent
sensing circuit, and overvoltage crowbar circuite

(
6-29

H744 Regulator Circuit

The 20=30 Vac input is a full wave which is rectified by bridge D1 to
provide a dc voltage (24 to 40V, depending on line voltage) across
filter capacitor C1 and bleeder resistor R10 Operation centers on
precision voltage regulator E1 which is configured as a positive
switching regulator. A simplified schematic of E1 is shown in Figure 6-10.
Regulator E1 is a monolithic integrated circuit that is used as a
precision voltage regulator. It consists of a temperature=compensated
reference amplifier, error amplifier, series=pass power transistor,
and the output circuit required to drive the external transistors.
In addition to E1, the regulator circuit includes pass transistor
Q2, pre-drivers Q3 and Q4, and level shifter Q5. Zener diode D2 is
used with Q5 and R2 to provide +15V for E1. Q5 is usen as a

"level

shifter"; most of the input voltage is absorbed across the collectoraemitter
of Q5. This is necessary since the raw input voltage is well above
that required for E1 operation. This +15V input is supplied while still
retaining the ability to switch pass transistor Q2 on or off by drawing
current down through the emitter of Q5e

The output circuit is standard for most switching regulators and
consists of "free-wheeiing"

diode D5, choke coil L1, and output

capacitors C8 and C9$ These components make up the regulator output
filtero Free wheeling diode D5 is used to clamp the emitter of Q2 to
ground when Q2 shuts off, thus providing a discharge path for L1.

In operation, Q2 is turned on and off generating a square wave of

6-30

FREQUENCY
COMPENSATION

I NV ERT I NG n - - - - - - - - - - - - I - - - ,
INPUT
VREF

------ave

n---~---~-~

SERIES PASS
TRANSISTOR

' * ' - - - - - - 0 V 0 UT

L------avz
NON INVERTING
INPUT

_ _ _ _ _ _ _ _ _~~~

VCURRENT CURRENT
LIMIT
SENSE
11 -1391

Figure 6-10

Simplified Diagram of Precision Voltage Regulator E1
6-30A

voltage which is applied,across D5 at the input of the LC filter
(11, C8 and C9). This type circuit is basically only an averaging
device, and the square ,,,,ave of vol tage appears as an average vol tage
at the output terminal. By varying the period of conduction of Q2, the
output (average) voltage may be varied or controlled, thus supplying
regulation.

Th~

output voltage is sensed and fed back to E1 where

it is compared with a fixed reference voltage. E1 turns pass transistor
Q2 on and off according to whether the output voltage level decreases
or increases. Defined upper and lower limits for the output are
approximately t5.05V and +4.95V.

During one full cycle of operation the

re~ulator

operates as follows:

Q2 is turned on and a high voltage (approximately +30V) is applied
across L1. If the output is already at a +5V level, then a constant
+25V would be present across L1. This constant dc voltage causes a
linear ramp of current to bukld up through L1. At the same time,
output capacitors C8 and C9 absorb this changing current and voltage,
causing the output level C+5V at this point) to increase. When the
output, which is monitored by E1 reaches approxinately +5.05V, E1
shuts off turning Q2 off, and the emitter of Q2 is clamped to ground.
L1 discharges into capacitors C8, C9, and the load. Pre-drivers Q3
and Q4 are used to increase the effective gain of Q2 to ensure that
Q2 can be turned on and off in a relatively short period of time.

Conversely, once Q2 is turned off and the output voltage begins to
decrease, a predetermined value of approximately +4=95V will be
reached causing El to turn on \vhich in turn causes Q2 to conduct,

6-31

beginning another cycle of operatione

Thus, a ripple voltage is superimposed on the output and is detected
as predetermined maximum (+5e05V) and minimum (+4Q95V) values by E1.
When +5.05V is reached, E1 turns Q2 off and when +4 e 95V is reached,
E1 turns Q2 ono This type of circuit action is also referred to as
a

6~ripple

regulatoro~'

6-32

6.5.2.2

+5V Overcurrent Sensing Circuit of the H744

The overcurrent sensing circuit consists of:

Q1, R3 through R6, R25,

R26, Q7, and C4. Transistor Q1 is normally not conducting; however,
if the output exceeds 30A, the forward voltage across R4 is sufficient
to turn Q1 on, causing C4 to begin charging. When C4 reaches a value
equal to the voltage on the anode gate of Q7, 07 turns on and E1 is
biased off, turning the pass transistor off. Thus, the output voltage
is decreased as required to ensure that the output current is maintained
below 35A (approximately) and the regulator is G'short circuit 9

protected.

The regbulator continues to oscillate in this new mode until the overload
condition is removed.

(
6-33

6.5.2.3

+5V Overvoltage Crowbar Circuit of the H744

The'overvoltage crowbar circuit consists of the following components:
Zener diode D1, silicon-controlled rectifier (SCR) D7, DB, R22, R23,
C7, and Q6 ..

Under normal conditions, the trigger input to the SCR (D7)

is at

ground because the voltage across Zener diode D3 is too small to cause
it to conduct. As the +5V line approaches 6V, Zener diode D3 conducts
and the voltage drop across resistor R23 draws gate current and triggers
the

SCRe

The

SCR

shorts the +5V line to ground through resistor R21,

which is a current-limiting resistor. The SCR remains on until the
capacitors discharge.

6-34

6.5.3

H745 -15V Regulator

Two H745 -15V regulators are included in the PDP-11/40 Po\Ver System.
Operation of the H745 is basically the same as that of the +5V
regulator. The H745 schematic is shown in drawing C-CS-H74S-0-1. Input
power (20 to 30 Vac) is taken from the secondary of transformer T1
and applied to the full-wave bridge rectifier (d1). The output of
Dl is a variable 24 to 40 Vdc and is applied across capacitor Cl and

resistor R1. The following paragraphs discuss the regulator circuit,
overcurrent sensing circuit, and the overvoltage crowbar circuit.

6-35

6,,5 .. 3 .. 1

-15V Regulator Circuit of the H745

Regulator operation is almost identical to that of the +5V regulator;
however, the +15V input that is required for operation of E1 is
derived externally and is applied across capacitor C2 to E1 and the
inverting and non-inverting inputs to E1 are reversed. In addition,
the polarities of the various components are reversed. For example,
Q5, which is used as a level shifter, is an NPN transistor on the +5V
regulator but a PNP is required on the -15V regulator to allow the
regulator to operate below ground (at -15V)"

Under normal operating conditions, regulator operation centers around
linear regulator E1 and pass transistor Q2, which is controlled by
E1. Predetermined output voltage limits are

~14Q85V

(minimum) and

-15 .. 15"\1 (maximum). When. the output reaches -15.15V, E1 shuts off,
turning Q2 off, and L1 discharges into CB and Cg. When the output
reaches -14085V, E1 conducts, causing Q2 to turn on, increasing the
output voltage.

6-36

6.5.3.2

-15V Overcurrent Sensing Circuit of the H745

The -15V regulator overcurrent sensing circuit is basically made up of
the same components as the +5V regulator except Q1 is an NPN transistor
in the -15V regulator. Transistor Q1 is normally not conducting;
however, once the output exceeds 15A, Q1 turns on and C3 charges. When
C3 reaches the same value as the anode gate of Q7, E1 is biased off,
which turns Q2 off, thereby stopping current flow and turning the
-15V regulator off. Thus, the regulator is short-circuit protected.

6-37

.. 15V Overvoltage Crowbar Circuit of the H745

When SCR D5 is fired, the -15V output is pulled up to ground and latched
at ground until input power, or the +15V input is removed. A negative
slope on the +15V line can be used to trip the crowbar for power-down
sequencing, if desired.

6-38

6.5.4

DC Power Distribution

Distribution of dc power from the basic PDP11/40 power supply is
shown on the cabling diagram (Sheet 3) of the BASIC ASS'Y (11/40)
print (D-VA-11/40-0-0). Distribution is. effected by cabling from
the various H744 and H745 regulator to a power distribution panel
with further cabling to the individual system units. The cable
(E-IA-70008754-00) from the regulators to the power distribution
panel is defined in the prints:

POWER HARNESS (11/40), D-IC-IV40-0-2

and HARNESS, POWER (WIRE LIST), K-t:"L-7008784-0-1. The cables from
the power distribution panel to the system units are diverse, and
relate to the power interconnection technique on the system units.
Detailed information is provided for the connections to the KD11-A
backpanel and for the MF11-L backpanel, both basic to the PDP11/40.
The cable types are noted on Sheet 3 of the BASIC ASS'Y (11/40),
print D-VA-11/40-0-0 with details on connection on Sheet 4 and in
the respective cable drawings. Connection to DD11 tyne system
units requiring the G772 module connection is provided by the
D-IA-7009177-0-0 cable.

The distribution of dc power from the regulators to the power
distribution panel results in certain regulators driving certain
connectors. Limitations, therefore, exist on the amount of power on
a connector and the number of connectors availahle. Figure 6-11
is a representation of the distribution panel wi th usage (KD11-A, MF11-L)
and source (H744's and H745's per slot assignment in the H742 bulk
power supply).

6-39

Power is supplied to three groups of connectors on J1, J2 and J3,
J4 and J5, J6, respectively. Each of these input connectors have
output connectors: J1, J2 ahve 1, 2 and 3; J3, J4 have 4, 5 and 6;
and J5, J6 have 7, 8 and

Connectors J1, J2 receive power from the

+5v regulator of SLOT A

and the -15V regulator of SLOT E. All of this power is committed
to the KD11-A processor and the MF11-6 memory. Note that this
happens with only two of the three distribution connectors being
used, 1 and 3. The cable from 3 is a joint cable, this portion from
3 suuplying the MF11-6 with -15V powero

Connectors J3, J4 receive power from the ~5V regulator of SLOT Band
the --15V regulator of SLOT D. Note that only two distribution
connectors, 5 and 6, are available for expansion use; connector 4 is
already used to provide +5V power (A) to the basic MF11-6. The
+5V power left for connectors 5 and 6 is reduced by that amount;
the -15V power must be shared with any further expansion logic from
connector 7, 8 or 9.

Connectors J5, J6 receive power from the optional +5V regulator of
SLOT C and the already mentioned -15V regulator of SLOT D. Three
distribution connectors 7, 8 and 9 are available but care must be
used to avoid overloading the -15V regulator also used for the J3, J4
connectors. Note thttt expansion beyond two additional single system
units require the option

+5V regulator of SLOT C due to distrihution

connection limitationu The first two

6-40

svste~

units use up connectors

5 and 6, additional units require connector (and therefore power) from
the J5, J6 connector group. The optional +5 regulator of SLOT C
is provided with logics origianally ordered with the PDP11/40i it
must be separately ordered for add on situations.

6-41

-15V@10A,SlOT 0
A

SU PP l Y
(REGULATOR)

POWER
DISTRIBUTION
PANEL

r:l2

+5 V @ 25A, SLOT A
-15V@ IOA,SlOT E

+5V@25A,
SLOT B

+5V@l25A ,SLOT C
(OPTIONAL)

r---"----..

r;l3

L:J LJ

K011-A
+5V @ 25A
-15V@ 1A

-15V@9A

+5V

MFl1-l

+15V@.3A
11-1574

6 ... 41A

6.5.5

Maintenance of Power System

For the most part, maintenance of the power system at the field level
consists of replacing defective modules, such as the regulators. The
details on regulator operation presented in paragraphs

6~5.1

through

6.5.3 are for theory of operation and off-line repair of failed
units (see paragraph 7.5). With Maintenance consisting of module
replacement, the major maintenance effort consists,of failure isolation.
Table 6-4 lists a procedure that can be followed as a guideline to
assist in locating defective components.

CAUTION

Because there are two f5V and two -15V
regulators in the PDP-11/40 System, a
common troubleshooting technique would
be to swap an operatinry regulator with
a faulty regulator. If this is done,
first check regulator input voltages to
prevent damage to the second regulator
in the event the fault lies in the power
supply.

6-42

Table fi-4
Power System Troubleshooting Guide

Step

Test

Procedure

syste~

Results

Verify that proper ac voltage

115V

- measure

input to power supply is

between pin 1 or 2 and

present.

pin 3 or 4 of TR1 on

Incorrect - indicntes

H742 power supply.

fnilure may be in 860

Correct - proceed to Step 2.

power control or input
line. Proceed to Step 5.
0\

23nv system - measure

I
.J::'
W

between pin 2 and 3 of TB1.

Verify that H742 bulk

20-30 volts should be

power supply is providing

present on the following

the proper ac outputs.

pins:

Correct - proceed to step 3.

Incorrect - indicate
failure of H742 transformer.
If all voltages are correct

~T 1

- pins 1 ,2

except one, problem could

IT2 - pins 1 ,2

be either transformer

pins 8,9

secondary or a wiring

pins 11 ,12

malfunction.

Table 6-4 (Cont)
Power System Troubleshooting Guide

Step

Test

Procedure

Results

J3 ... pins 1,2
pins 3,4
pins 5,6
pins 7,8

15-24 volts should be
cr-

present between pins

I
.t-~

3 and 4 of J1.

Verify that the proper

+5V Regulator - check for

input voltage is present

20-30 Vac at pins 6 and 7

at the regula tor

of J1 ..

Correct

proceed to step 40

Incorrect - indicates
failure is probably in

... 15V Regulator - check for

the wiring between the

20-30 Vac at pins 6 and 8

H742 and the regulator.

of J1. Check for +15V at

If the +15V for the -15V

pins 4,5 of

J'.

regulator is not present,
the trouble may be in the
H742 power control board.
'W'.
\.~

Table 6-4 (Cont)
Power System Troubleshooing Guide

Step

Test

Procedure

Results

Verify that the proper

+5V Regulator - measure

Correct - check remaining

output voltage is being

between pin 2,5 <+5) and

regulators: If all

produced by the regula-

3,4 (GND) of J1

regulators are within

tor.

must be between +5.05V

tolerance, the power

and +409 5V •

system is not malfunctioning

Output

and the problem exists
elsewhere.

0'\

I
.p.
In

-15V Regulator - measure

Incorrect - If the +5V .

between pin 1 (-15V) and

regulator is not functioning

pin 2,3 (GND) of J1.

replace. If the -15V

Output must be between

regulator is not functioning

-15.15V and -14.85V.

check fuse F1 in the
regulator. If this does not
correct the problem, replace
the regulator.

Table 6-4

(Cant)

Power System Troubleshooting Guide

Step

Test

If previous tests indicate

Proced.ure

Results

Verify that proper ac

If not, check input

that prqper input voltage

voltage is supplied to

line cord and line

is not heing supplied to bulk

input terminals of 860

power receptacles

supply, perform the tests

(or 861) power control.

listed in this step.
b.
0'\

Verify that circuit

If none of these tests

breaker CB1 is ON.

correct the problem,

I
~
Q'\

proceed to step 6.
c.

Verify that REMOTE/
OFF/LOCAL switch 51
is set to either LOCAL
or REMOTE ..

Verify that thermal
switch 82 is closed.

.:,

Table 6 .. 4 (Cont)
Power System Troubleshooting Guide

Step

0'\

I
.&::--

.......

. Test

Procedure

Results

Verify that the power

If the board is

control board is

control board is prOm

producing the proper

functioning properly.

ducing the proper

outputs, the problem

outputs. Refer to

could he a malfunction

drawings

of power control

C-CS-860 O-1 and
a

relay K1 ..

C-CS-S409770-0-1.
If the board is not
producing correct
outputs, replace the
board.

7.1

GENERAL MAINTENANCE

SCOPE

This chapter provides general
System and includes:

~aintenance

infor~~tion

for the PDP-11/40

preventive maintenance of mechanical asseMblies,

system power checks, and power supply maintenance.

Maintenance information related to the processor and memory
components of the basic PDP-11/40 System is presented in the
associated maintenance manuals

~·1aintenance

of Unibus peripherals

requires not only the associated maintenance manual, but also an
, understanding of Unibus operation.

In addition to the maintenance information contained in the
processor, memory, and peripherals manuals of the PDP-'1/40,
significant maintenance information is available in the diaqnostic
programs documentation. The diaqnostic programs are a

~ajortool

detecting and isolating machine faults and Preventive maintenance
should include their regular use.

(
7-1

for

7.2

OVERALL MAINTENANCE TECHNIQUES

Maintenance of the PDP-11/40 System requires:

knowledge of proper hardware operation,
ability to detect and isolate an error condition, and
means to repair the error condition

This is true for all but the preventive maintenance procedures for
mechanical assemblies and for the relatively simple power check-out
procedures. This section outlines techniques for performing
maintenance on the PDP-11/40c Note, however, that the essential
starting point is to have knowledgeab Ie and able service

7-2

personnel~

7.2.1

Knowledge of Proper Hardware Operation

Training courses and machine documentation provide information on
hardware operation and is available at the programming, systems,
and individual device levels.

The training courses available for the PDP-ll/40 System include:

PDP-11j40 Hardware Familiarization (10 days)
PDP-l1/40 Options Maintenance (5 days)
Interfacing the PDP-l1

(5 days)

Other courses are available on Paper Tape Software, Disk Operating
System Software, and Resource

Ti~esharing

System Software. Information

on these and other PDP-l1 courses is available from either the
Digital Account Representative or from the Digital Education Centers.

Documentation pertinent to the PDP-l1/40 System includes documents
produced specifically for the PDP-l1/40, and common PDP-l1 documents
on programming and Unibus interfacing. All of the relevent documents
are listed in Table 1-2 of this manual.

A special effort has been expended in production of documents
relating to the PDP-l1/40 processor (KD11-A)

and processor options

(KE11-E, KE11-F, and KT11-D). Innovations include:

print set

formats, tables and notes on the prints, and wire list print
notations. These are provided to facilitate initial learning but,

7-3

more importantly, to provide instant reminders of specific details
during maintenanceo Information describing the print sets appears
in the processor and options maintenance manuals.

7-4

7.2.2

Detection and Isolation of Error Condition

Malfunctioning hardware is normally indicated by either software failure
or by peripheral malfunctions. This can occur with customer's svstem
software or vvi th the periodic operation of various MainDEC diagnostic
programs. If the failure occurs with system software, verification
by MainDEC programs is suggested.

Isolation of the specific failure is the most difficult aspect of
maintenance repair and the reason for trained service personnel.
Operation of MainDEC diagnostic programs can isolate the failure to
a specific device or operation but knowledge of program operation
and documentation is necessary. The modular nature of the Unibus, with
its separate peripherals, may also help isolate failures, but
knowledge of Unibus specifications and peripheral operation is
essential. Often, however, error detection is reduced to knowledge
of proper machine operation with detection of discrepancies. Detailed
manuals on device operation with clear, annotated prints, provide
information on operation. Detection of discrepancies requires
experience and expertise.

The level of fault isolation is important. In the power supply,
regulator units such as the H744 or H745 are replaced if their

7-5

output voltages are in error; the circuit board of the H742 unit
is replaced if the AC LO or DC LO control signals are in error.
Repair procedures for the replaced units are given in paragraph

7&5020 Replacement of KD11-A processor modules is suggested for
situations requiring minimum down timeo Experienceo service
personnel, however, may find integrated circuit (IC) replacement a
practical alternative to the cost or transportation of modules.

7-6

7.2.3

Means of Repairing the Error Condition

The method of repairing an error condition is directly related to
the level of fault isolation mentioned in the previous paragraph.
If~

for example, fault isolation and repair is to be at the Ie

level, then the parts identified in the machine documentation must
be available. Suitable repair and rework techniques must be
followed to avoid equipment damage. If module or sub

asse~bly

level

of fault isolation and repair is to be used, these units must
be available. Spare part kits are available for the PDP-11/40 (SP11-KP
for processor and SP11-PD for the power supply) and the various
Unibus devices. Repair is normally at this level when down tiMe is
critical or when a large number of machines is involved.

Verification of repair at any level is made by running the apnropriate
MainDEC diagnostic programs.

7-7

Digital Field Service

The present state-of=the-art in complex computer systems requires
qualified service

personnel~

Installation and 90-day warranty

service are provided by such personnel from Digital Field Servicee
These people are trained both in basic PDP-11/40 components (processor,
console, and memory) and in the peripherals that may be placed on
the Unibus. Material support exists both at the

level (directly

equivalent parts) and at the module and subassembly levelG

Digital Field Service support may be continued beyond the warranty
period with a Digital Service
programs are available

Agreernent~

Total equipment maintenance

Details of this service may be obtained

from the Digital Account Representative at the local Field ,Service
Officeo

7-8

7.3

HAINTENANCE EQUIPMENT REQUIRED

Maintenance procedures for the PDP-11/40 require the standard equipment
(or equivalent) listed in Table 7-1. Especially important in analyzing
operation of the processor, or processor options, is the KM11 option
consisting of W130 and W131 modules and associated overlays. Use of
the KM11 maintenance displays and switches is' covered in the processor
and processor options maintenance manuals. The module extender board
(W900) is also an important diagnostic tool and is discussed in
paragraph 7.4 ..

(
7-9

Table 7-1
Maintenance Equipment Required

Model, Type,

Equipment
or Tool

Manufacturer

or Part No.

Oscilloscope

Tektronix

*453

29-13510

Volt/Ohmmeter (VOM) Triplett

Unwrapping Tool

DEC Part No.

Gardner-Denver 505 244-475

29 .. 18387

(CatQ H812A)

Hand

~~rap

Tool

Gardner-Denver A-20557-29

29-18301

(Cat .. H811A)

29-13460

Diagonal Cutters

utica

47-4

Diagonal Cutters

utica

46 6 - 4 (mod if i ed ) 29 '" 1 9 5 51

Miniature Needle

utica

23-4-1/2

29-13462

Millers

1015

29-13467

Standard

29-13467

Nose Pliers

Nire Strippers

Solder Extractor

. Solder Pullit

7-10

Table 7 .. 1 (Cant)
Maintenance Equipment Required

Model, Type,

Equipment
or Tool

i'-1anufacturer

or Part No.

DEC Part No ..

Soldering Iron

Paragon

615

29-13452
(IC type head)

(30 watts)

Soldering Iron Tip

Paragon

605

29-19333

16-pin IC Clip

AP Inc.

AP923700

29-10246

24-pin IC Clip

AP Inc ..

AP923714

29-19556

KM11 Option

DEC

KM11 .. A

**W'130,W131

r.1aintenance Modules

Maintenance Card

DEC

559081-0-12

DEC

5509081-0-13

DEC

W900

Overlay (KD11-A)

Maintenance Card
OVerlay (KE11-E,F,
KT11-D)

Module Extender
Board

7-11

Table 7 -1

(Cant)

Maintenance Equipment Required

Model, Type,

Equipment
or Tool

Manufacturer

or Part No.

Regulator Extender

DEC

70-08850-0-1

DEC Part No.

Cable

Tektronix Type 453 Oscilloscope is adequate for most test
procedures; Type 454

(or equivalent) mny be required for

some measurements ..

N133 is a dual version of 1'1130 .. It provides the drivers for
two 1\1131 maintenance cards

The 130 may still be used;

however, two units would be required for

si~ultaneous

monitoring of the basic processor and options

Two W131s

are required for simultaneous monitoring in any caseo

7-12

704

PREVENTIVE MAINTENANCE

Preventive maintenance consists of specific tasks to be performed
periodically; its major purpose is to prevent future failures caused
by minor damage or progressive deterioration due to aging. A

preventive maintenance log book should be established and necessary
entries made according to a regular schedule. This data, compiled
over an extended period of time, can be very useful in anticipating
possible component failures resulting in module replacement on a
projected module or component reliability basis.

Preventive maintenance tasks consist of mechanical and electrical
checkse All maintenance schedules should be established according
to conditions at the particular installation site that are dependent
on

enviro~~ental

conditions, usage, etc. Mechanical checks should be

performed as often as required to allow the fans and air filters to
function efficiently. All other preventive maintenance tasks should
be performed on a regular schedule determined by reliability
requirements. A recommended ·schedule is every 1000 operation hours
or every three months, whichever comes first.

(
7-13

7.4,,1

Physical Checks

The following procedure contains' the necessary steps required for
mechanical checks and physical care of the PDP .. 11/40:

Procedure

Step

Clean the exterior and interior of the cabinet with a
vacuum cleaner or clean cloth moistened with non=
flammable, non-corrosive solvent"

Check all fans to ensure that they are not obstructed
in any

way~

Vacuum clean the air vents of the upper and

lower logic fan housings, and upper and lower regulator
fan housings. Remove and wash the filters in the cabinet
fan, located in the top of the cabinet.

Inspect all wiring and cables for cuts, breaks, fraying,
deterioration, kinks, strain, and mechanical security

Repair or replace any defective wiring or cable covering.

Inspect the following for mechanical security:

LED or

lamp assemblies, jacks, connectors, switches, power supply
regulators, fansu capacitors, etc .. Tighten or replace as
required ..

7 .. 14

Inspect all module mounting panels to ensure that each
module is securely seated in its connector and the
locking-releasing mechanism is functioning properly.

Inspect power supply capacitors for leaks, bulges, or
discoloration and replace as required.

Inspect module guides for wear, damage, and secure fasteningo

(
7-15

Electrical Checks and Adjustments

The following checks should be made when the system is first
installed and whenever a new component is installed in the
system (such as an additional regulator, processor option
module, interface module, etce)

7.4 .. 2.'

Voltage Regulator Checks - Perform the power system

checks listed in Table 7-2. Use a VOM to check the output voltages
under normal load conditions .. Use an oscilloscope to measure the
peak-to-peak ripple content on all dc outputs. Each voltage regulator
has an adjustment potentiometer located just below the output
indicator lamp. If the regulator outDut is not within the specified
tolerance, adjust as required to obtain an acceptable output (use
a non-conducting adjustment tool)" If a voltage regulator cannot be
adjusted to meet specifications, remove and replace the regulator.

Table 7-2
DC Output Voltage Checks

Ripple
REgulator

Voltage

Peak-to-Peak

H744 +5V Regulator

+5" O' volts

0.15 volts

+5 .. 0 vol ts

0.15 volts

+5.0 volts

0.15 volts

-15 .. 0 volts

0.45 volts

( slotA)

H744 +5V Regulator
(slot B)

H744 +5V Regulator,
optionsl (slot C)

H745 -15V Regulator
(slot D)

(

7 ... 17

Table 7-2 (Cont)
DC Output Voltage Checks

Ripple
Regulator

Voltage

Peak .. to-Peak
f>

H745 .... 15V Regulator

-15 .. 0 volts

0 .. 45 volts

(slot E)
'I

H742 Power Supply

+8 .. 0

0 .. 24 volts

(6,,8 to 9 .. 2)

7 ... 18

860 Power Control - Opera te the REMOTE IOFF ILOCAL St",i tch 81
on the 860 Power Control to make sure power is turned on in the
LOCAL position and disconnected in the OFF position. Return 81 to
the LOCAL position after performing this test if only a basic
(single box) PDP11/40 is presento See section 6.4 of this manual for
other connections.

(
7 .. 19

7e302c3

Ac Power Connector REceptacles - Test the output voltage

at each plug to be sure 115- or 230-volt ac power is available.

7-20

7.4.3

7.4.30'

ASR33 Teletype

Preventive Maintenance Checks - Check the following ASP33

items during system preventive maintenance:

Check distributor plates for deposits.

Check platen and typewheel for depositse

Check wires around distributor area for secure
mechanical and electrical connections.

Check the print hammer and replace if worn.

Rotate the mainshaft manually and check that movement
is free. If movement is restricted, check clutch
assemblies.

Check typewheel pinion racks, and gears for dirt.

(
7-21

Lubrication - Use a 50-50 mixture of 20 weight, non-detergent
oil and STP oil additive for viscosity improvement to perform the
follbwing lubrication, except where otherwise noted:

Oil all clutch assemblieso

Oil all felts until saturated

Lightly oil all pivot points.

Oil drive motor at both lubrication points provided.

Oil print carriage bearingso

Oil main shaft bearingso

Oil bearing on function shafto

Oil the eye ends of all springse

Oil the typewheel pinion and gear.

Oil repeat mechanism in keyboard assembly.

Clean the dashpot assembly and lubricate it with
graphite dust.

NOTE
Do not put oil in the dashpot.

Grease the teeth on spacing ratchet.

7~404

7.4.4.1

LA30 DECwriter

Preventive Maintenance Schedule - When the LA30 DECwriter

is included in the sytern, it is supplied with a maintenance manual
that contains detailed preventive maintenance procedures. The items
to be cleaned, inspected, and replaced on a regular schedule are
listed in the following chart:

Inspect

Printing Interval Clean

Replace

(Hours)

300-500

1. Ribbon Idlers

1. Ribbon Tension 1. Print

(Para .. -5 .. 2)

Head Assy
(Para 5 .. 4 .. 2)
c

2000

1 " Ribbon Motors

(Para" 5 2)
co

1 " Ribbon Tension

(Para .. 5.4,,6)

2. Carriage Assy
Round Shaft
(Para" 5.2)
3 " Ventilating Fan
Blades, if necessary
(Para .. 5 . 2)

-:~

Printing Interval Clean

Inspect

(Hours)

4. Linkage Pins,
Ratchet and
Pawl Mechanism
(Para., 502)

NOTE
Paragraphs referenced in this chart refer
to applicable paragraphs in Chapter 5 of
the LA30 DEC'i,vri ter Haintenance l'ianual ..

7 .. _

Replace

Cleaning Procedures - Always use a clean, lint-free cloth
to wipe off outside surfaces and a lightly-oiled cloth to remove any
dust or ink from inside the unit.

(The ink is oil-base)

Use

commercial furniture or automotive wax to protect the outside of
the covero Dust the cover and wipe the keyboard clean whenever
paper is replenished

Do not attempt to clean the print head assembly; rather, replace
it after

300~500

hours of

operation~

The replacement procedure is

described in Paragraph 504.2 of the LA30 DECwriter maintenance
Manual

At the time i t is replaced, wipe the ribbon idlers clean

with an oiled clotho

After 2000 hours of operation, remove each ribbon motor, as
described in Paragraph

5~405

oil to the lower bearing

of the LA30

felt~

manual~

Apply a light

At this time, lubricate the carriage

assembly round shaft, DEC part number 14-8656-1/20 Spray a light
coating of Molykote 557 along the entire shaft and sipe lightly
with a dry cloth to leave a thin coating of lubricant on the

shaft~

NOTE
(~{<

Do not attempt to clean of vacuum-clean
the control box asseroblyo It will function
better if left alone.

If necessary, after 2000 hours of operation remove the fan and
wipe the blades clean with an oiled clotho The fan motor does

not require scheduled lubrication.

At the 2000-hour interval of preventive maintenance, check the
paper advance mechanism linkage pin and pivot pins for grease
and freedom of movement. Normally, no maintenance is required.
However, if the terminal is in an extreme ambient temperature
environment, these pins will require lubrication. If so, disassemble
the linkages and apply Molykote B2KR grease to all bearing surfaces.

NOTE
The two dark green nylon rollers must
remain free of oil or grease to allow
the mechanism to function properly.

7-27

peDS High~Speed Paper-Tape Reader/Punch (option)

The PCOS HighaSpeed Paper-Tape Reader/Punch includes a ROYTRON
500 Series Reader/Punch mechanismo Complete lubrication and
preventive maintenance instructions for this mechanism are contained
in the Preventive Maintenance Section of the Roytron Maintenance
Manual, which is supplied with the

peoso

In addition to the preventive

maintenance procedures listed in that manual, perform the following
')

mechanical and electrical checks as part of the system preventive
maintenance proceduree

1-28

7.4 5.1
0

Mechanical Checks - Inspect the PCOS as follows:

Step

Procedure

Visually inspect the general condition of the tape
reader.

Clean the PCDS, inside and out, using a vacuum cleaner
or a clean cloth that has been moistened with a
non-flammable solvent.

Lubricate the chassis slide mechanism with a light
machine oil. Wipe off excess oil.

Inspect all wiring and replace any defective wiring
or defective cables.

Check that the READER FEED switch, READER ON/OFF
LINE switch light condensor, phototransistor assembly,
depressor arm, hold-down bracket, all connectors and
circuit modules, tape feed motor, front cover, and
resistor assembly are mechanically secure.

7-29

1&405e2

Electrical Checks - Perform power supply output

tests listed in the following chart:

Output

Pin Number

Tolerance

Ripple
(peak-to-peak V)

A1A2

f 0 .. 25 volts

0 .. 1 volts

... 15 volts

A1B2

11 ,,0 volts

0 .. 1 volts

... 18 volts

B8V2

:.: 2 .. 0 vo 1 ts

1 .. 0 volts

-36 volts

A8V2

+4 .. 0 vol ts

1 .. 0 volts

vol,ts

Use a VOM to measure output voltage and an oscilloscope to check
ripple voltage. The +5- and -15-volt outputs are adjustable:
the -18= and -36-volt outputs are not adjustable.

1 .. 30

7.5

USE OF MODULE EXTENDERS

The W900 module extender is a double-height, multi-layer etch
board that provides one-to-one connections between module
connectors and corresponding processor backplane connector slots.
Thus, three W900 module extenders can be used to extend a PDP-11/40
hex-size module from the processor backplane to provide access
to res and discrete components for test purposes under active
operating conditions.

CAUTION
Do not attenpt to extend more than one
module at a time while performing tests.
Note that the processor clock may have
to be adjusted to allow operation with
the modules extended.

7-31

7.6

PDP .. 11/40 POWER SYSTEM MAINTENANCE

System maintenance of the PDP11 /40 po,..,er system consists of
replacement of the modular elements. Offline repair is then
necessary for the replaced element, and is presented in this
sectiono Detaiied circuit operation is presented in paragraph 6.5
and is necessary for background to the troubleshooting procedures
of this section ..

7 .. 32

7.6.1

Circuit Tracing

The user should first read the description of the power system
contained in Chapter 6 of this manual. By next referring to the
schematic and interconnecting diagraMs in

.
(

print set, the

user should be able to trace through the ac power control and dc
power distribution circuits

fro~

the primary ac input connectors

to the dc inputs of each logic module.

(

t~e

7-33

Voltage Regulator Tests

(Off~Line

Repair)

Figure 7-1 shows a reconmended bench test source that can be
fabricated from standard parts. It also shows the bench test
loads used to test the voltage regulator outputs under various
load conditions. No additional test equipment or tools are required
other than those listed in Table 7-10

The voltage regulator extender cable allows a voltage regulator
to be removed from its assigned slot on the H742 power supply to
provide access for test purposes. This cable only supplies ac
input power to the voltage regulator. An additional voltage
regulator bench test source and load fixture can be fabricated
from standard DEC parts to perform troubleshooting and performance
tests under the various load conditions

required~

The circuit

schematic and part numbers required to build this optional test
fixture are shown in Figure 7-1.

Whenever a power system fault has been isolated to a voltage
regulator, examine the internal fuse F1. A blown fuse usually
means that the main pass transistor Q2, and/or one of its
drivers (Q3, Q4) is short circuited. This can be checked by
using the following procedure:

7-34

Step

Procedure

Check for damage to base-emitter bleeder resistors
and scorching of the etched board in the area or
Q3 and Q4.

If the pass transistor and drivers are not faulty,
the fault may be caused by continuous base drive to
the first driver (Q4)

Check level shifter Q5 for

a short circuit.

Check the resistance to ground at the input to the
precision voltage regulator integrated circuit E1
(pins 4 and 5) to determine if an external short
circuit is holding the IC in conduction. The approximate
resistance to ground is listed for each voltage
regulator in Table 7-3.

Use a VOM to check for short circuit between fuse
terminals and ground. Possible short circuits involving
mounting TO-3

co~ponents

to the heat sink

~ay

located by connecting the VOM leads between

TO-~

cases and

a regulator mounting screw on the end of the heat sink.

7-35

r-------------,

I
I
TRANSFORMER
16-10856
lOA
VARIAC

115Vac

lOA
CIRCUIT
BREAKER
12-10191-1

Lr1

8-PIN MALE
MATE-N-LOCK
12-09351-8
~300W

25Voc

r--------------,I

9
I

I rl~F4~~II
lKV

~ 0.4.0.

(lor 3)

% LOAD

TERM

50
100
200
SHORT

1
3
3.2
1.2

% LOAD

TERM

30
100
200
SHORT

2
1.2
1.2.3
1.2.4

% LOAD

TERM

50
100
200
SHORT

3
3,2
1.2

>- 6

TO H746 MOS REGULATOR
UNDER TEST

J
I

. If?KI~FJ

'-l

I
I

TO H744 +5V REGULATOR
UNDER TEST

II~

j a-

PIN MALE
MATE-N-LOCK
12-09351-8
4
6.0.
100W

825vac

+10.0.
40W

~3
5.0.

25W

0---

r--------------,I
I

9
I

TO H745 -15V REGULATOR
UNDER TEST
7

4
CLOSE
SWITCH
TO TURN
OFF AND
CROWBAR

25Vac

10
15

a-PIN
MALE
MATE-N-LOCK
12-09351-8
(lor 3)

_3
~ 3..0.0.
u-----
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