XMC4700 XMC4800 Reference Manual Infineon UM V01 02 EN
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- Revision History
- About this Document
- Introduction
- CPU Subsystem
- 2 Central Processing Unit (CPU)
- 2.1 Overview
- 2.2 Programmers Model
- 2.3 Memory Model
- 2.4 Instruction Set
- 2.5 Exception Model
- 2.6 Fault Handling
- 2.7 Power Management
- 2.8 Private Peripherals
- 2.9 PPB Registers
- 3 Bus System
- 4 Service Request Processing
- 5 General Purpose DMA (GPDMA)
- 5.1 Overview
- 5.2 Functional Description
- 5.3 Basic Transfers
- 5.4 Multi Block Transfers
- 5.4.1 Block Chaining Using Linked Lists
- 5.4.2 Auto-Reloading of Channel Registers
- 5.4.3 Contiguous Address Between Blocks
- 5.4.4 Suspension of Transfers Between Blocks
- 5.4.5 Ending Multi-Block Transfers
- 5.4.6 Programing Examples
- 5.4.6.1 Single-block Transfer
- 5.4.6.2 Multi-Block Transfer with Source Address Auto-Reloaded and Contiguous Destination Address
- 5.4.6.3 Multi-Block Transfer with Source and Destination Address Auto-Reloaded
- 5.4.6.4 Multi-Block Transfer with Source Address Auto-Reloaded and Linked List Destination Address
- 5.4.6.5 Multi-Block DMA Transfer with Linked List for Source and Contiguous Destination Address
- 5.4.6.6 Multi-Block Transfer with Linked List for Source and Destination
- 5.5 Service Request Generation
- 5.6 Power, Reset and Clock
- 5.7 Initialization and System Dependencies
- 5.8 Registers
- 6 Flexible CRC Engine (FCE)
- 2 Central Processing Unit (CPU)
- On-Chip Memories
- 7 Memory Organization
- 8 Flash and Program Memory Unit (PMU)
- 8.1 Overview
- 8.2 Boot ROM (BROM)
- 8.3 Prefetch Unit
- 8.4 Program Flash (PFLASH)
- 8.5 Service Request Generation
- 8.6 Power, Reset and Clock
- 8.7 Registers
- System Control
- 9 Window Watchdog Timer (WDT)
- 10 Real Time Clock (RTC)
- 11 System Control Unit (SCU)
- 11.1 Overview
- 11.2 Miscellaneous Control Functions
- 11.3 Power Management
- 11.3.1 Functional Description
- 11.3.2 System States
- 11.3.3 Hibernate Domain Operating Modes
- 11.3.4 Embedded Voltage Regulator (EVR)
- 11.3.5 Power-on Reset
- 11.3.6 Supply Watchdog (SWD)
- 11.3.7 Power Validation
- 11.3.8 Supply Voltage Brown-out Detection
- 11.3.9 Hibernate Domain Power Management
- 11.3.10 Flash Power Control
- 11.4 Hibernate Control
- 11.5 Reset Control
- 11.6 Clock Control
- 11.6.1 Block Diagram
- 11.6.2 Clock Sources
- 11.6.3 Clock System Overview
- 11.6.4 High Precision Oscillator Circuit (OSC_HP)
- 11.6.5 Backup Clock Source
- 11.6.6 Main PLL
- 11.6.7 Internally Generated System Clock Calibration
- 11.6.8 USB PLL
- 11.6.9 Ultra Low Power Oscillator
- 11.6.10 Internal Slow Clock Source
- 11.6.11 Clock Gating Control
- 11.7 Debug Behavior
- 11.8 Power, Reset and Clock
- 11.9 Initialization and System Dependencies
- 11.10 Registers
- 11.11 Interconnections
- Communication Peripherals
- 12 LED and Touch-Sense (LEDTS)
- 13 SD/MMC Interface (SDMMC)
- 13.1 Overview
- 13.2 Functional Description
- 13.3 Card Detection
- 13.4 Data Transfer Modes
- 13.5 Read/ Write Operation
- 13.6 Special Command Types
- 13.7 Error Detection
- 13.8 Service Request Generation
- 13.9 Debug Behavior
- 13.10 Power, Reset and Clocks
- 13.11 Initialisation and System Dependencies
- 13.12 Registers
- 13.13 Interconnects
- 14 External Bus Unit (EBU)
- 14.1 Overview
- 14.2 Interface Signals
- 14.3 Memory Controller Structure
- 14.4 Memory Controller AHBIF Bridge
- 14.5 Clocking Strategy and Local Clock Generation
- 14.6 External Bus Operation
- 14.7 External Bus Arbitration
- 14.8 Start-Up/Boot Process
- 14.9 Standard Access Phases
- 14.10 Asynchronous Read/Write Accesses
- 14.11 Synchronous Read/Write Accesses
- 14.11.1 Signals
- 14.11.2 Support for four Burst FLASH device types
- 14.11.3 Typical Burst Flash Connection
- 14.11.4 Burst Flash Clock
- 14.11.5 Standard Access Phases
- 14.11.6 Burst Length Control
- 14.11.7 Control of ADV & CS Delays During Burst FLASH Access
- 14.11.8 Burst Flash Clock Feedback
- 14.11.9 Asynchronous Address Phase
- 14.11.10 Page Mode Support
- 14.11.11 Critical Word First Read Accesses
- 14.11.12 Example Burst Flash Access Cycle
- 14.11.13 External Cycle Control via the WAIT Input
- 14.11.14 Flash Non-Array Access Support
- 14.11.15 Termination of a Burst Access
- 14.11.16 Burst Flash Device Programming Sequences
- 14.11.17 Cellular RAM
- 14.11.18 Programmable Parameters
- 14.12 SDRAM Interface
- 14.12.1 Features
- 14.12.2 Signal List
- 14.12.3 External Interface
- 14.12.4 External Bus Clock Generation
- 14.12.5 SDRAM Characteristics
- 14.12.6 Supported SDRAM commands
- 14.12.7 SDRAM device size
- 14.12.8 Power Up Sequence
- 14.12.9 Initialization sequence
- 14.12.10 Mobile SDRAM Support
- 14.12.11 Burst Accesses
- 14.12.12 Short Burst Accesses
- 14.12.13 Multibanking Operation
- 14.12.14 Bank Mask
- 14.12.15 Row Mask
- 14.12.16 Banks Precharge
- 14.12.17 Refresh Cycles
- 14.12.18 Self-Refresh Mode
- 14.12.19 SDRAM Addressing Scheme
- 14.12.20 Power Down Mode
- 14.12.21 SDRAM Recovery Phases
- 14.12.22 Programmable Parameters
- 14.13 Debug Behavior
- 14.14 Power, Reset and Clock
- 14.15 System Dependencies
- 14.16 Registers
- 15 Ethernet MAC (ETH)
- 15.1 Overview
- 15.2 Functional Description
- 15.2.1 ETH Core
- 15.2.2 MAC Transaction Layer (MTL)
- 15.2.3 DMA Controller
- 15.2.4 DMA Descriptors
- 15.2.5 MAC Management Counters
- 15.2.6 Power Management Block
- 15.2.7 PHY Interconnect
- 15.2.8 Station Management Interface
- 15.2.9 Media Independent interface
- 15.2.10 Reduced Media Independent Interface
- 15.2.11 IEEE 1588-2002 Overview
- 15.2.11.1 Reference Timing Source
- 15.2.11.2 Transmit Path Functions
- 15.2.11.3 Receive Path Functions
- 15.2.11.4 Time Stamp Error Margin
- 15.2.11.5 Frequency Range of Reference Timing Clock
- 15.2.11.6 Advanced Time Stamp Feature Support
- 15.2.11.7 Peer-to-Peer PTP (Pdelay) Transparent Clock (P2P TC) Message Support
- 15.2.11.8 Clock Types
- 15.2.11.9 PTP Processing and Control
- 15.2.11.10 Reference Timing Source (for Advance Timestamp Feature)
- 15.2.11.11 Transmit Path Functions
- 15.2.11.12 Receive Path Functions
- 15.2.12 System Time Register Module
- 15.2.13 Application BUS Interface
- 15.3 Service Request Generation
- 15.4 Debug
- 15.5 Power Reset and Clock
- 15.6 ETH Registers
- 15.7 Interconnects
- 16 EtherCAT Slave Controller (ECAT)
- 16.1 Overview
- 16.2 EtherCAT Protocol
- 16.3 Ethernet Physical Layer
- 16.4 FMMU
- 16.5 SyncManager
- 16.6 EtherCAT State Machine
- 16.7 EtherCAT Slave Controller Address Space Overview
- 16.8 ESI EEPROM
- 16.9 Sync/Latch Signals
- 16.10 LED Signals (Indicators)
- 16.11 Service Request Generation
- 16.12 Debug Behavior
- 16.13 Power, Reset and Clock
- 16.14 Initialization and System Dependencies
- 16.15 Registers
- 16.15.1 ECAT kernel registers
- 16.15.2 Station Address
- 16.15.3 Write Protection
- 16.15.4 Data Link Layer
- 16.15.5 Application Layer
- 16.15.6 PDI / ESC Configuration
- 16.15.7 Interrupts
- 16.15.8 Error Counters
- 16.15.9 Watchdogs
- 16.15.10 SII EEPROM Interface
- 16.15.11 MII Management Interface
- 16.15.12 FMMU
- 16.15.13 SyncManager
- 16.15.14 DC – Receive Times
- 16.15.15 Time Loop Control Unit
- 16.15.16 SyncManager Event Times
- 16.15.17 ESC specific registers (0x0E00:0x0E01)
- 16.16 Interconnects
- 17 Universal Serial Bus (USB)
- 17.1 Overview
- 17.2 Functional Description
- 17.3 Programming Overview
- 17.4 Host Programming Overview
- 17.4.1 Host Initialization
- 17.4.2 Host Connection
- 17.4.3 Host Disconnection
- 17.4.4 Channel Initialization in Buffer DMA or Slave Mode
- 17.4.5 Halting a Channel
- 17.4.6 Selecting the Queue Depth
- 17.4.7 Handling Special Conditions
- 17.4.8 Host HFIR Functionality
- 17.4.9 Host Programming for Various USB Transactions
- 17.5 Host Programming in Slave mode
- 17.5.1 Writing the Transmit FIFO in Slave Mode
- 17.5.2 Reading the Receive FIFO in Slave Mode
- 17.5.3 Control Transactions in Slave Mode
- 17.5.4 Bulk and Control IN Transactions in Slave Mode
- 17.5.5 Bulk and Control OUT/SETUP Transactions in Slave Mode
- 17.5.6 Interrupt IN Transactions in Slave Mode
- 17.5.7 Interrupt OUT Transactions in Slave Mode
- 17.5.8 Isochronous IN Transactions in Slave Mode
- 17.5.9 Isochronous OUT Transactions in Slave Mode
- 17.6 Host Programming in Buffer DMA Mode
- 17.6.1 Control Transactions in Buffer DMA Mode
- 17.6.2 Bulk and Control IN Transactions in Buffer DMA Mode
- 17.6.3 Bulk and Control OUT/SETUP Transactions in Buffer DMA Mode
- 17.6.4 Interrupt IN Transactions in Buffer DMA Mode
- 17.6.5 Interrupt OUT Transactions in Buffer DMA Mode
- 17.6.6 Isochronous IN Transactions in Buffer DMA Mode
- 17.6.7 Isochronous OUT Transactions in Buffer DMA Mode
- 17.7 Host Programming in Scatter-Gather DMA Mode
- 17.8 Device Programming Overview
- 17.8.1 Device Initialization
- 17.8.2 Device Connection
- 17.8.3 Device Disconnection
- 17.8.4 Endpoint Initialization
- 17.8.5 Programming OUT Endpoint Features
- 17.8.6 Programming IN Endpoint Features
- 17.8.7 Worst-Case Response Time
- 17.8.8 Choosing the Value of GUSBCFG.USBTrdTim
- 17.8.9 Handling Babble Conditions
- 17.8.10 Device Programming Operations in Buffer DMA or Slave Mode
- 17.9 Device Programming in Slave Mode
- 17.9.1 Control Transfers
- 17.9.2 IN Data Transfers
- 17.9.3 OUT Data Transfers
- 17.9.4 Non-Periodic (Bulk and Control) IN Data Transfers
- 17.9.5 Non-Isochronous OUT Data Transfers
- 17.9.6 Isochronous OUT Data Transfers
- 17.9.7 Isochronous OUT Data Transfers Using Periodic Transfer Interrupt
- 17.9.8 Incomplete Isochronous OUT Data Transfers
- 17.9.9 Incomplete Isochronous IN Data Transfers
- 17.9.10 Periodic IN (Interrupt and Isochronous) Data Transfers
- 17.9.11 Periodic IN Data Transfers Using the Periodic Transfer Interrupt
- 17.9.12 Interrupt OUT Data Transfers Using Periodic Transfer Interrupt
- 17.10 Device Programming in Buffer DMA Mode
- 17.10.1 Control Transfers
- 17.10.2 OUT Data Transfers
- 17.10.3 Non-Periodic (Bulk and Control) IN Data Transfers
- 17.10.4 Non-Isochronous OUT Data Transfers
- 17.10.5 Incomplete Isochronous OUT Data Transfers
- 17.10.6 Periodic IN (Interrupt and Isochronous) Data Transfers
- 17.10.7 Periodic IN Data Transfers Using the Periodic Transfer Interrupt
- 17.10.8 Interrupt OUT Data Transfers Using Periodic Transfer Interrupt
- 17.11 Device Programming in Scatter-Gather DMA Mode
- 17.11.1 Programming Overview
- 17.11.2 SPRAM Requirements
- 17.11.3 Descriptor Memory Structures
- 17.11.4 Control Transfer Handling
- 17.11.5 Interrupt Usage for Control Transfers
- 17.11.6 Application Programming Sequence
- 17.11.7 Internal Data Flow
- 17.11.7.1 Three-Stage Control Write
- 17.11.7.2 Three-Stage Control Read
- 17.11.7.3 Two-Stage Control Transfer
- 17.11.7.4 Back to Back SETUP During Control Write
- 17.11.7.5 Back-to-Back SETUPs During Control Read
- 17.11.7.6 Extra Tokens During Control Write Data Phase
- 17.11.7.7 Extra Tokens During Control Read Data Phase
- 17.11.7.8 Premature SETUP During Control Write Data Phase
- 17.11.7.9 Premature SETUP During Control Read Data Phase
- 17.11.7.10 Premature Status During Control Write
- 17.11.7.11 Premature Status During Control Read
- 17.11.7.12 Lost ACK During Last Packet of Control Read
- 17.11.8 Bulk Transfer Handling in Scatter/Gather DMA Mode
- 17.11.9 Interrupt Transfer Handling in Scatter/Gather DMA Mode
- 17.11.10 Isochronous Transfer Handling in Scatter/Gather DMA Mode
- 17.12 OTG Revision 1.3 Programming Model
- 17.13 Clock Gating Programming Model
- 17.13.1 Host Mode Suspend and Resume With Clock Gating
- 17.13.2 Host Mode Suspend and Remote Wakeup With Clock Gating
- 17.13.3 Host Mode Session End and Start With Clock Gating
- 17.13.4 Host Mode Session End and SRP With Clock Gating
- 17.13.5 Device Mode Suspend and Resume With Clock Gating
- 17.13.6 Device Mode Suspend and Remote Wakeup With Clock Gating
- 17.13.7 Device Mode Session End and Start With Clock Gating
- 17.13.8 Device Mode Session End and SRP With Clock Gating
- 17.14 FIFO RAM Allocation
- 17.15 Service Request Generation
- 17.16 Debug Behaviour
- 17.17 Power, Reset and Clock
- 17.18 Initialization and System Dependencies
- 17.19 Registers
- 17.20 Interconnects
- 18 Universal Serial Interface Channel (USIC)
- 18.1 Overview
- 18.2 Operating the USIC
- 18.3 Asynchronous Serial Channel (ASC = UART)
- 18.3.1 Signal Description
- 18.3.2 Frame Format
- 18.3.3 Operating the ASC
- 18.3.3.1 Bit Timing
- 18.3.3.2 Baud Rate Generation
- 18.3.3.3 Noise Detection
- 18.3.3.4 Collision Detection
- 18.3.3.5 Pulse Shaping
- 18.3.3.6 Automatic Shadow Mechanism
- 18.3.3.7 End of Frame Control
- 18.3.3.8 Mode Control Behavior
- 18.3.3.9 Disabling ASC Mode
- 18.3.3.10 Protocol Interrupt Events
- 18.3.3.11 Data Transfer Interrupt Handling
- 18.3.3.12 Baud Rate Generator Interrupt Handling
- 18.3.3.13 Protocol-Related Argument and Error
- 18.3.3.14 Receive Buffer Handling
- 18.3.3.15 Sync-Break Detection
- 18.3.3.16 Transfer Status Indication
- 18.3.4 ASC Protocol Registers
- 18.3.5 Hardware LIN Support
- 18.4 Synchronous Serial Channel (SSC)
- 18.4.1 Signal Description
- 18.4.2 Operating the SSC
- 18.4.2.1 Automatic Shadow Mechanism
- 18.4.2.2 Mode Control Behavior
- 18.4.2.3 Disabling SSC Mode
- 18.4.2.4 Data Frame Control
- 18.4.2.5 Parity Mode
- 18.4.2.6 Transfer Mode
- 18.4.2.7 Data Transfer Interrupt Handling
- 18.4.2.8 Baud Rate Generator Interrupt Handling
- 18.4.2.9 Protocol-Related Argument and Error
- 18.4.2.10 Receive Buffer Handling
- 18.4.2.11 Multi-IO SSC Protocols
- 18.4.3 Operating the SSC in Master Mode
- 18.4.4 Operating the SSC in Slave Mode
- 18.4.5 SSC Protocol Registers
- 18.4.6 SSC Timing Considerations
- 18.5 Inter-IC Bus Protocol (IIC)
- 18.5.1 Introduction
- 18.5.2 Operating the IIC
- 18.5.2.1 Transmission Chain
- 18.5.2.2 Byte Stretching
- 18.5.2.3 Master Arbitration
- 18.5.2.4 Non-Acknowledge and Error Conditions
- 18.5.2.5 Mode Control Behavior
- 18.5.2.6 Data Transfer Interrupt Handling
- 18.5.2.7 IIC Protocol Interrupt Events
- 18.5.2.8 Baud Rate Generator Interrupt Handling
- 18.5.2.9 Receiver Address Acknowledge
- 18.5.2.10 Receiver Handling
- 18.5.2.11 Receiver Status Information
- 18.5.3 Symbol Timing
- 18.5.4 Data Flow Handling
- 18.5.5 IIC Protocol Registers
- 18.6 Inter-IC Sound Bus Protocol (IIS)
- 18.6.1 Introduction
- 18.6.2 Operating the IIS
- 18.6.2.1 Frame Length and Word Length Configuration
- 18.6.2.2 Automatic Shadow Mechanism
- 18.6.2.3 Mode Control Behavior
- 18.6.2.4 Transfer Delay
- 18.6.2.5 Parity Mode
- 18.6.2.6 Transfer Mode
- 18.6.2.7 Data Transfer Interrupt Handling
- 18.6.2.8 Baud Rate Generator Interrupt Handling
- 18.6.2.9 Protocol-Related Argument and Error
- 18.6.2.10 Transmit Data Handling
- 18.6.2.11 Receive Buffer Handling
- 18.6.2.12 Loop-Delay Compensation
- 18.6.3 Operating the IIS in Master Mode
- 18.6.4 Operating the IIS in Slave Mode
- 18.6.5 IIS Protocol Registers
- 18.7 Service Request Generation
- 18.8 Debug Behaviour
- 18.9 Power, Reset and Clock
- 18.10 Initialization and System Dependencies
- 18.11 Registers
- 18.11.1 Address Map
- 18.11.2 Module Identification Registers
- 18.11.3 Channel Control and Configuration Registers
- 18.11.4 Protocol Related Registers
- 18.11.5 Input Stage Register
- 18.11.6 Baud Rate Generator Registers
- 18.11.7 Transfer Control and Status Registers
- 18.11.8 Data Buffer Registers
- 18.11.9 FIFO Buffer and Bypass Registers
- 18.12 Interconnects
- 19 Controller Area Network Controller (MultiCAN+)
- 19.1 CAN Basics
- 19.2 Overview
- 19.3 MultiCAN+ Kernel Functional Description
- 19.4 Use Case Example MultiCAN+
- 19.5 MultiCAN+ Kernel Registers
- 19.6 MultiCAN+ Module Implementation
- Analog Frontend Peripherals
- 20 Versatile Analog-to-Digital Converter (VADC)
- 20.1 Overview
- 20.2 Introduction and Basic Structure
- 20.3 Configuration of General Functions
- 20.4 Module Activation and Power Saving
- 20.5 Conversion Request Generation
- 20.6 Request Source Arbitration
- 20.7 Analog Input Channel Configuration
- 20.8 Conversion Result Handling
- 20.9 Synchronization of Conversions
- 20.10 Safety Features
- 20.11 External Multiplexer Control
- 20.12 Service Request Generation
- 20.13 Registers
- 20.14 Interconnects
- 21 Delta-Sigma Demodulator (DSD)
- 21.1 Overview
- 21.2 Introduction and Basic Structure
- 21.3 Configuration of General Functions
- 21.4 Input Channel Configuration
- 21.5 Main Filter Chain
- 21.6 Auxiliary Filter
- 21.7 Group Delay
- 21.8 Conversion Result Handling
- 21.9 Service Request Generation
- 21.10 Resolver Support
- 21.11 Time-Stamp Support
- 21.12 Registers
- 21.13 Interconnects
- 22 Digital to Analog Converter (DAC)
- 22.1 Overview
- 22.2 Operating Modes
- 22.3 Service Request Generation
- 22.4 Power, Reset and Clock
- 22.5 Initialization
- 22.6 Registers
- 22.7 Interconnects
- 20 Versatile Analog-to-Digital Converter (VADC)
- Industrial Control Peripherals
- 23 Capture/Compare Unit 4 (CCU4)
- 23.1 Overview
- 23.2 Functional Description
- 23.3 Service Request Generation
- 23.4 Debug Behavior
- 23.5 Power, Reset and Clock
- 23.6 Initialization and System Dependencies
- 23.7 Registers
- 23.8 Interconnects
- 24 Capture/Compare Unit 8 (CCU8)
- 24.1 Overview
- 24.2 Functional Description
- 24.2.1 Overview
- 24.2.2 Input Selector
- 24.2.3 Connection Matrix
- 24.2.4 Start/Stop Control
- 24.2.5 Counting Modes
- 24.2.6 Active/Passive Rules
- 24.2.7 Compare Modes
- 24.2.8 External Events Control
- 24.2.9 Multi-Channel Support
- 24.2.10 Timer Concatenation
- 24.2.11 Output Parity Checker
- 24.2.12 PWM Dithering
- 24.2.13 Prescaler
- 24.2.14 CCU8 Usage
- 24.3 Service Request Generation
- 24.4 Debug Behavior
- 24.5 Power, Reset and Clock
- 24.6 Initialization and System Dependencies
- 24.7 Registers
- 24.8 Interconnects
- 25 Position Interface Unit (POSIF)
- 25.1 Overview
- 25.2 Functional Description
- 25.3 Service Request Generation
- 25.4 Debug Behavior
- 25.5 Power, Reset and Clock
- 25.6 Initialization and System Dependencies
- 25.7 Registers
- 25.8 Interconnects
- 23 Capture/Compare Unit 4 (CCU4)
- General Purpose I/O Ports
- Startup Modes
- Debug and Trace System
- Lists of Figures and Tables