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UM10360
LPC176x/5x User manual
Rev. 3.1 — 2 April 2014

User manual

Document information
Info

Content

Keywords

LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763,
LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM
Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller

Abstract

LPC176x/5x user manual

UM10360

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LPC17xx user manual

Revision history
Rev

Date

Description

3.1

20140402

LPC176x/5x user manual
Modifications:

•
•
3

20131220

Added LPC1768UK.
Table 73 “Pin description (LPC175x)” and Table 74 “Pin description (LPC176x)”: Changed
RX_MCLK and TX_MCLK type from INPUT to OUTPUT.

LPC176x/5x user manual
Modifications:

UM10360

User manual

•
•
•

Part ID for part LPC1763 added.

•
•
•

Updated Serial Wire Output description (Table 610).

•

Description of CAN interrupt request updated. One common CAN interrupt is triggered. See
Section 16.8.3.

•
•
•
•

Condition on minimum frequency of CAP input clock added in Section 21.5.1.

•
•
•
•

Description of INXCNT register updated. See Section 26.6.3.6.

•
•
•
•

Boot loader SRAM use explained. See Section 33.5.

•

Figure 118 “RI timer block diagram” updated.

Changed title to “LPC176x/5x User manual”.
Updated numbering for CAN interfaces: CAN1 uses SCC = 0, CAN2 uses SCC = 1. See
Section 16.13 “ID look-up table RAM” and Section 16.15 “Configuration and search algorithm”.
Clarified burst mode information for ADGINTEN (Table 532 and Table 534).
Condition CCLK > 18 MHz for USB operation is not applicable for this USB peripheral and was
removed (see Section 4.7.1, Section 11.13, and Section 13.11).

Description of RIMASK register corrected. See Table 434.
Condition for maximum allowable STCLK frequency added. See Section 23.4.
Delete statement “All PWM related Match registers are configured for toggle on match.” in
Figure 121.
Reset value of the RTC_AUX register corrected. See Table 508.
DAC power-down mode removed in Section 30.2.
Added: The DAC output is disabled in deep-sleep, power-down, or deep power-down modes.
See Table 538.
SYSRESETREQ supported. See Table 660.
Figure 19 “Ethernet packet fields” corrected.
Bit description in the SPI test control register corrected. Bit 0 indicates test mode. All other bits
are reserved. See Section 17.7.5 “SPI Test Control Register (SPTCR - 0x4002 0010)”.

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LPC17xx user manual

Revision history …continued
Rev

Date

Description

20100819

LPC176x/5x user manual revision.
Modifications:

20100104

•
•
•
•

UART0/1/2/3: FIFOLVL register removed.

•
•
•

Clocking and power control: add bit 15 (PCGPIO) to PCONP register (Table 46).

•
•
•

Motor control PWM: update description of match and limit registers.

ADC: reset value of the ADCTRM register changed to 0xF00 (Table 500).
Timer0/1/2/3: Description of DMA operation updated.
USB Device: Corrected error in the USBCmdCode register (0x01 = write, 0x02 = read)
(Table 184).
Part LPC1763 added.
Update register bit description of USBIntStat register in Host and Device mode (Table 155 and
Table 221).
GPIO: update register bit description of the FIOPIN register (Table 73).
Numerous editorial updates throughout the user manual.

LPC176x/5x user manual revision.

Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Chapter 1: LPC176x/5x Introductory information
Rev. 3.1 — 2 April 2014

User manual

1.1 Introduction
The LPC176x/5x is an ARM Cortex-M3 based microcontroller for embedded applications
requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as modernized debug
features and a higher level of support block integration.
High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU
frequency. Other versions operate at up to an 100 MHz CPU frequency. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branches.
The peripheral complement of the LPC176x/5x includes up to 512 kB of flash memory, up
to 64 kB of data memory, Ethernet MAC, a USB interface that can be configured as either
Host, Device, or OTG, 8 channel general purpose DMA controller, 4 UARTs, 2 CAN
channels, 2 SSP controllers, SPI interface, 3 I2C interfaces, 2-input plus 2-output I2S
interface, 8 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder
interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power RTC
with separate battery supply, and up to 70 general purpose I/O pins.

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Chapter 1: LPC176x/5x Introductory information

1.2 Features
Refer to Section 1.4.1 for details of features on specific part numbers.

• ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed
versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory
Protection Unit (MPU) supporting eight regions is included.

• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
• Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data bus
provides high code performance from flash.

• Up to 64 kB on-chip SRAM includes:
– Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance
CPU access.
– Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as
for general purpose instruction and data storage.

• Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, the Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.

• Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and
the USB interface. This interconnect provides communication with no arbitration
delays unless two masters attempt to access the same slave at the same time.

• Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.

• Serial interfaces:
– Ethernet MAC with RMII interface and dedicated DMA controller.
– USB 2.0 full-speed controller that can be configured for either device, Host, or
OTG operation with an on-chip PHY for device and Host functions and a dedicated
DMA controller.
– Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA
support. One UART has modem control I/O and RS-485/EIA-485 support.
– Two-channel CAN controller.
– Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.
– SPI controller with synchronous, serial, full duplex communication and
programmable data length. SPI is included as a legacy peripheral and can be used
instead of SSP0.
– Three enhanced I2C-bus interfaces, one with an open-drain output supporting the
full I2C specification and Fast mode plus with data rates of 1Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.
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Chapter 1: LPC176x/5x Introductory information

– I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I2S interface can be used with the GPDMA. The I2S interface supports
3-wire data transmit and receive or 4-wire combined transmit and receive
connections, as well as master clock output.

• Other peripherals:
– 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with
configurable pull-up/down resistors, open drain mode, and repeater mode. All
GPIOs are located on an AHB bus for fast access, and support Cortex-M3
bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any
pin of ports 0 and 2 can be used to generate an interrupt.
– 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
– 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
– Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
– One motor control PWM with support for three-phase motor control.
– Quadrature encoder interface that can monitor one external quadrature encoder.
– One standard PWM/timer block with external count input.
– Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V Lithium button
cell. The RTC will continue working when the battery voltage drops to as low as
2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.
– Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
– Cortex-M3 system tick timer, including an external clock input option.
– Repetitive interrupt timer provides programmable and repeating timed interrupts.

• Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire
Trace Port options.

• Emulation trace module supports real-time trace.
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.

• Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.
• Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.

• Non-maskable Interrupt (NMI) input.
• Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, or the USB clock.

• The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up
from any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep power-down modes.
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Chapter 1: LPC176x/5x Introductory information

• Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).

•
•
•
•
•

Each peripheral has its own clock divider for further power savings.
Brownout detect with separate threshold for interrupt and forced reset.
On-chip Power-On Reset (POR).
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a
system clock.

• An on-chip PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.

• A second, dedicated PLL may be used for the USB interface in order to allow added
flexibility for the Main PLL settings.

• Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.

• Available as LQFP100 (14 mm 14 mm 1.4 mm), TFBGA1001 (9 mm 9 mm 0.7
mm), WLCSP100 (5.074
mm) packages

5.074

0.6 mm) package, and 80-pin LQFP (12 x 12 x 1.4

1.3 Applications
•
•
•
•
•
•

eMetering
Lighting
Industrial networking
Alarm systems
White goods
Motor control

LPC1768/65 only.

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1.4 Ordering information
Table 1.

Ordering information

Type number

Package
Name

Description

Version

LQFP100

plastic low profile quad flat package; 100 leads; body 14

LPC1768FET100

TFBGA100

plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x
0.7 mm

LPC1768UK

WLCSP100 wafer level chip-scale package; 100 balls; 5.074

LPC1769FBD100
LPC1768FBD100
LPC1767FBD100

1.4 mm

SOT407-1

LPC1766FBD100
LPC1765FBD100
LPC1764FBD100
LPC1763FBD100

5.074

SOT926-1

0.6 mm

LPC1759FBD80
LPC1758FBD80
LPC1756FBD80

LQFP80

plastic low profile quad flat package; 80 leads; body 12

1.4 mm

SOT315-1

LPC1754FBD80
LPC1752FBD80
LPC1751FBD80

1.4.1 Part options summary
Table 2.

Ordering options for LPC176x/5x parts

Type number

Max. CPU
speed

Flash

Total
SRAM

Ethernet

USB

CAN

I2S

DAC

Package

LPC1769FBD100

120 MHz

512 kB

64 kB

yes

Device/Host/OTG

yes

100 pin

LPC1768FBD100

100 MHz

512 kB

64 kB

yes

Device/Host/OTG

yes

100 pin

LPC1768FET100

100 MHz

512 kB

64 kB

yes

Device/Host/OTG

yes

100 pin

LPC1768UK

100 MHz

512 kB

64 kB

yes

Device/Host/OTG

yes

100 pin

LPC1767FBD100

100 MHz

512 kB

64 kB

yes

100 pin

LPC1766FBD100

100 MHz

256 kB

64 kB

yes

Device/Host/OTG

yes

100 pin

LPC1765FBD100

100 MHz

256 kB

64 kB

Device/Host/OTG

yes

100 pin

LPC1764FBD100

100 MHz

128 kB

32 kB

yes

Device

100 pin

LPC1763FBD100

100 MHz

256 kB

64 kB

yes

100 pin

LPC1759FBD80

120 MHz

512 kB

64 kB

Device/Host/OTG

yes

80 pin

LPC1758FBD80

100 MHz

512 kB

64 kB

yes

Device/Host/OTG

yes

80 pin

LPC1756FBD80

100 MHz

256 kB

32 kB

Device/Host/OTG

yes

80 pin

LPC1754FBD80

100 MHz

128 kB

32 kB

Device/Host/OTG

yes

80 pin

LPC1752FBD80

100 MHz

64 kB

16 kB

Device

80 pin

LPC1751FBD80

100 MHz

32 kB

8 kB

Device

80 pin

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Chapter 1: LPC176x/5x Introductory information

ARM Cortex-M3

DMA
controller

Ethernet
10/100
MAC

USB
device,
host,
OTG

Clocks
and
Controls

System
bus

D-code
bus

I-code
bus

Clock Generation,
Power Control,
Brownout Detect,
and other
system functions

Flash
Accelerator

Flash
512 kB

SRAM
64 kB

Multilayer AHB Matrix

High Speed GPIO

RST

Test/Debug Interface

USB
interface

Xtalout

JTAG
interface

Trace Module

Ethernet
PHY
interface

Trace
Port

Xtalin

1.5 Simplified block diagram

ROM
8 kB
AHB to
APB bridge

AHB to
APB bridge

APB slave group 0

APB slave group 1

SSP1

SSP0

UARTs 0 & 1

UARTs 2 & 3

CAN 1 & 2

I2S

I2C 0 & 1

I2C2

SPI0

Repetitive Interrupt
Timer

Capture/Compare
Timers 0 & 1

Capture/Compare
Timers 2 & 3

Watchdog Timer

External Interrupts

PWM1

DAC

12-bit ADC

System Control

Pin Connect Block

Motor Control PWM

GPIO Interrupt Ctl

Quadrature Encoder
32 kHz
oscillator

Real Time Clock
Note: shaded peripheral blocks
support General Purpose DMA

20 bytes of backup
registers
RTC Power Domain

Fig 1.

LPC1768 simplified block diagram

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Chapter 1: LPC176x/5x Introductory information

1.6 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses which are faster and are used similarly to TCM interfaces: one bus
dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of
two core buses allows for simultaneous operations if concurrent operations target different
devices.
The LPC176x/5x uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other
bus masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals on different slaves ports of the matrix to be accessed simultaneously by
different bus masters. Details of the multilayer matrix connections are shown in Figure 2.
APB peripherals are connected to the CPU via two APB busses using separate slave
ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller. The APB bus bridges are configured
to buffer writes so that the CPU or DMA controller can write to APB devices without
always waiting for APB write completion.

1.7 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The Cortex-M3 offers many new features,
including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with Wake-up Interrupt
Controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is
appended to this manual.

1.7.1 Cortex-M3 Configuration Options
The LPC176x/5x uses the r2p0 version of the Cortex-M3 CPU, which includes a number
of configurable options, as noted below.
System options:

• The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the
SYSTICK timer.

• The Wake-up Interrupt Controller (WIC) is included. The WIC allows more powerful
options for waking up the CPU from reduced power modes.

• A Memory Protection Unit (MPU) is included.
• A ROM Table in included. The ROM Table provides addresses of debug components
to external debug systems.

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Chapter 1: LPC176x/5x Introductory information

Debug related options:

• A JTAG debug interface is included.
• Serial Wire Debug is included. Serial Wire Debug allows debug operations using only
2 wires, simple trace functions can be added with a third wire.

• The Embedded Trace Macrocell (ETM) is included. The ETM provides instruction
trace capabilities.

• The Data Watchpoint and Trace (DWT) unit is included. The DWT allows data
address or data value matches to be trace information or trigger other events. The
DWT includes 4 comparators and counters for certain internal events.

• An Instrumentation Trace Macrocell (ITM) is included. Software can write to the ITM in
order to send messages to the trace port.

• The Trace Port Interface Unit (TPIU) is included. The TPIU encodes and provides
trace information to the outside world. This can be on the Serial Wire Viewer pin or the
4-bit parallel trace port.

• A Flash Patch and Breakpoint (FPB) is included. The FPB can generate hardware
breakpoints and remap specific addresses in code space to SRAM as a temporary
method of altering non-volatile code. The FPB include 2 literal comparators and 6
instruction comparators.

1.8 On-chip flash memory system
The LPC176x/5x contains up to 512 kB of on-chip flash memory. A flash memory
accelerator maximizes performance for use with the two fast AHB-Lite buses. This
memory may be used for both code and data storage. Programming of the flash memory
may be accomplished in several ways. It may be programmed In System via the serial
port. The application program may also erase and/or program the flash while the
application is running, allowing a great degree of flexibility for data storage field firmware
upgrades, etc.

1.9 On-chip Static RAM
The LPC176x/5x contains up to 64 kB of on-chip static RAM memory. Up to 32 kB of
SRAM, accessible by the CPU and all three DMA controllers are on a higher-speed bus.
Devices containing more than 32 kB SRAM have two additional 16 kB SRAM blocks, each
situated on separate slave ports on the AHB multilayer matrix.
This architecture allows the possibility for CPU and DMA accesses to be separated in
such a way that there are few or no delays for the bus masters.

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Chapter 1: LPC176x/5x Introductory information

ARM Cortex-M3
D-code
bus

EMULATION
TRACE MODULE

TEST/DEBUG
INTERFACE

I-code
bus

DMA
controller

Ethernet
10/100
MAC

RST

clock generation, CLK
power control, OUT
and other
system functions
Vdd
voltage regulator

clocks
and
controls

USB
device,
host,
OTG

Xtalout

USB
interface

X32Kin

Ethernet PHY
interface

Debug Port

X32Kout

JTAG
interface

Xtalin

1.10 Block diagram

internal
power

System
bus
Flash
Accelerator

Flash
512 kB

SRAM
32 kB

ROM
8 kB

SRAM
16 kB
SRAM
16 kB

AHB to
APB bridge

Multilayer
AHB Matrix

DMAC
regs

USB
regs

HS
GPIO

Ethernet
regs

AHB to
APB bridge
APB slave group 0

APB slave group 1

SSP1

SSP0

UARTs 0 & 1

UARTs 2 & 3

CAN 1 & 2

I2S

I2C 0 & 1

I2C2

SPI0

Capture/compare
timers 2 & 3

Capture/compare
timers 0 & 1

Repetitive interrupt
timer

Watchdog timer

External interrupts

PWM1

DAC

12-bit ADC

System control

Pin connect block

Motor control PWM

GPIO interrupt control
32 kHz
oscillator

Quadrature encoder

Real Time Clock

Note: shaded peripheral blocks
support General Purpose DMA

Vbat ultra-low power
Backup registers
regulator
(20 bytes)
RTC Power Domain

Fig 2.

LPC1768 block diagram, CPU and buses

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Chapter 2: LPC176x/5x Memory map
Rev. 3.1 — 2 April 2014

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2.1 Memory map and peripheral addressing
The ARM Cortex-M3 processor has a single 4 GB address space. The following table
shows how this space is used on the LPC176x/5x.
Table 3.

LPC176x/5x memory usage and details

Address range

General Use

Address range details and description

0x0000 0000 to
0x1FFF FFFF

On-chip non-volatile
memory

0x0000 0000 - 0x0007 FFFF

For devices with 512 kB of flash memory.

0x0000 0000 - 0x0003 FFFF

For devices with 256 kB of flash memory.

0x0000 0000 - 0x0001 FFFF

For devices with 128 kB of flash memory.

On-chip SRAM

0x2000 0000 to
0x3FFF FFFF

0x4000 0000 to
0x5FFF FFFF

0xE000 0000 to
0xE00F FFFF

0x0000 0000 - 0x0000 FFFF

For devices with 64 kB of flash memory.

0x0000 0000 - 0x0000 7FFF

For devices with 32 kB of flash memory.

0x1000 0000 - 0x1000 7FFF

For devices with 32 kB of local SRAM.

0x1000 0000 - 0x1000 3FFF

For devices with 16 kB of local SRAM.

0x1000 0000 - 0x1000 1FFF

For devices with 8 kB of local SRAM.

Boot ROM

0x1FFF 0000 - 0x1FFF 1FFF

8 kB Boot ROM with flash services.

On-chip SRAM
(typically used for
peripheral data)

0x2007 C000 - 0x2007 FFFF

AHB SRAM - bank 0 (16 kB), present on
devices with 32 kB or 64 kB of total SRAM.

0x2008 0000 - 0x2008 3FFF

AHB SRAM - bank 1 (16 kB), present on
devices with 64 kB of total SRAM.

GPIO

0x2009 C000 - 0x2009 FFFF

GPIO.

APB Peripherals

0x4000 0000 - 0x4007 FFFF

APB0 Peripherals, up to 32 peripheral blocks,
16 kB each.

0x4008 0000 - 0x400F FFFF

APB1 Peripherals, up to 32 peripheral blocks,
16 kB each.

AHB peripherals

0x5000 0000 - 0x501F FFFF

DMA Controller, Ethernet interface, and USB
interface.

Cortex-M3 Private
Peripheral Bus

0xE000 0000 - 0xE00F FFFF

Cortex-M3 related functions, includes the
NVIC and System Tick Timer.

2.2 Memory maps
The LPC176x/5x incorporates several distinct memory regions, shown in the following
figures. Figure 3 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping,
which is described later in this section.

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0x400B 4000
0x400B 0000

15
14
13

0x400A 8000

I2S

0x400A 4000

reserved

0x400A 0000

I2C2

UART3

Rev. 3.1 — 2 April 2014

UART2

Timer 3

0x5020 0000
0x5000 0000

reserved

reserved
APB1 peripherals
1 GB

APB0 peripherals

Timer 2

0x4008 C000

DAC

reserved

0x4008 8000

SSP0

AHB SRAM bit band alias addressing

1 - 0 reserved

reserved

reserved
0.5 GB

AHB SRAM (2 blocks of 16 kB)
reserved
8 kB boot ROM
reserved

I-code/D-code
memory space

GPDMA controller

Ethernet controller

32 kB local static RAM

0x4000 0000

0 GB

0x5000 8000
0x5000 4000
0x5000 0000

I2C1
22 - 19 reserved

0x4008 0000
0x4006 0000
0x4005 C000
0x4004 C000

CAN2

0x4004 8000

CAN1

0x4004 4000

CAN common

0x4004 0000

CAN AF registers

0x4003 C000

0x2008 4000

CAN AF RAM

0x4003 8000

0x2007 C000

ADC

0x4003 4000

0x1FFF 2000

SSP1

0x4003 0000

pin connect

0x4002 C000

GPIO interrupts

0x4002 8000

RTC + backup registers

0x4002 4000

SPI

0x4002 0000

I2C0

0x4001 C000

PWM1

0x4001 8000

reserved

0x4001 4000

UART1

0x4001 0000

UART0

0x4000 C000

TIMER1

0x4000 8000

1
0

TIMER0

0x4000 4000

WDT

0x4000 0000

0x200A 0000

0x1FFF 0000
0x1000 8000
0x1000 0000

0x0000 0000

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0x5000 C000

0x2200 0000

0x0008 0000
512 kB on-chip flash

31 - 24 reserved

0x2400 0000

+ 256 words
active interrupt vectors

APB0 peripherals

0x4008 0000

reserved

Fig 3.

reserved

0x4010 0000

0x2009 C000

0x0000 0000

USB controller

0x4200 0000

GPIO

0x0000 0400

0x4400 0000
peripheral bit band alias addressing

0x4009 0000

0x4008 0000

0xE000 0000

reserved
AHB periherals

0x5020 0000

127- 4 reserved

Chapter 2: LPC176x/5x Memory map

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0x4009 4000

private peripheral bus

12 repetitive interrupt timer
reserved

AHB peripherals

0xE010 0000

reserved

0x4009 8000

0xFFFF FFFF
reserved

QEI
motor control PWM

0x400A C000

0x4009 C000

LPC1768 memory space

system control
30 - 16 reserved

0x400C 0000
0x400B C000
0x400B 8000

4 GB

NXP Semiconductors

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APB1 peripherals

0x4010 0000
0x400F C000

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Figure 3 and Table 4 show different views of the peripheral address space. The AHB
peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required
to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.

2.3 APB peripheral addresses
The following table shows the APB0/1 address maps. No APB peripheral uses all of the
16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at
multiple locations within each 16 kB range.
Table 4.

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APB0 peripherals and base addresses

APB0 peripheral

Base address

Peripheral name

0x4000 0000

Watchdog Timer

0x4000 4000

Timer 0

0x4000 8000

Timer 1

0x4000 C000

UART0

0x4001 0000

UART1

0x4001 4000

reserved

0x4001 8000

PWM1

0x4001 C000

I2C0

0x4002 0000

SPI

0x4002 4000

RTC

0x4002 8000

GPIO interrupts

0x4002 C000

Pin Connect Block

0x4003 0000

SSP1

0x4003 4000

ADC

0x4003 8000

CAN Acceptance Filter RAM

0x4003 C000

CAN Acceptance Filter Registers

0x4004 0000

CAN Common Registers

0x4004 4000

CAN Controller 1

0x4004 8000

CAN Controller 2

19 to 22

0x4004 C000 to 0x4005 8000

reserved

0x4005 C000

I2C1

24 to 31

0x4006 0000 to 0x4007 C000

reserved

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Table 5.

APB1 peripherals and base addresses

APB1 peripheral

Base address

Peripheral name

0x4008 0000

reserved

0x4008 4000

reserved

0x4008 8000

SSP0

0x4008 C000

DAC

0x4009 0000

Timer 2

0x4009 4000

Timer 3

0x4009 8000

UART2

0x4009 C000

UART3

0x400A 0000

I2C2

0x400A 4000

reserved

0x400A 8000

I2S

0x400A C000

reserved

0x400B 0000

Repetitive interrupt timer

0x400B 4000

reserved

0x400B 8000

Motor control PWM

0x400B C000

Quadrature Encoder Interface

16 to 30

0x400C 0000 to 0x400F 8000

reserved

0x400F C000

System control

2.4 Memory re-mapping
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the Cortex-M3. Refer to Section 6.4 and Section 34.4.3.5 of the
Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset
feature.

Boot ROM re-mapping
Following a hardware reset, the Boot ROM is temporarily mapped to address 0. This is
normally transparent to the user. However, if execution is halted immediately after reset by
a debugger, it should correct the mapping for the user. See Section 33.6.

2.5 AHB arbitration
The Multilayer AHB Matrix arbitrates between several masters. By default, the Cortex-M3
D-code bus has the highest priority, followed by the I-Code bus. All other masters share a
lower priority.

2.6 Bus fault exceptions
The LPC176x/5x generates Bus Fault exception if an access is attempted for an address
that is in a reserved or unassigned address region. The regions are areas of the memory
map that are not implemented for a specific derivative. These include all spaces marked
“reserved” in Figure 3.
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For these areas, both attempted data access and instruction fetch generate an exception.
In addition, a Bus Fault exception is generated for any instruction fetch that maps to an
AHB or APB peripheral address.
Within the address space of an existing APB peripheral, an exception is not generated in
response to an access to an undefined address. Address decoding within each peripheral
is limited to that needed to distinguish defined registers within the peripheral itself. For
example, an access to address 0x4000 D000 (an undefined address within the UART0
space) may result in an access to the register defined at address 0x4000 C000. Details of
such address aliasing within a peripheral space are not defined in the LPC176x/5x
documentation and are not a supported feature.
If software executes a write directly to the flash memory, the flash accelerator will
generate a Bus Fault exception. Flash programming must be accomplished by using the
specified flash programming interface provided by the Boot Code.
Note that the Cortex-M3 core stores the exception flag along with the associated
instruction in the pipeline and processes the exception only if an attempt is made to
execute the instruction fetched from the disallowed address. This prevents accidental
aborts that could be caused by prefetches that occur when code is executed very near a
memory boundary.

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3.1 Introduction
The system control block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:

•
•
•
•

Reset
Brown-Out Detection
External Interrupt Inputs
Miscellaneous System Controls and Status

Each type of function has its own register(s) if any are required and unneeded bits are
defined as reserved in order to allow future expansion. Unrelated functions never share
the same register addresses

3.2 Pin description
Table 6 shows pins that are associated with System Control block functions.
Table 6.

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Pin summary

Pin name

Pin
direction

Pin description

EINT0

Input

External Interrupt Input 0 - An active low/high level or falling/rising
edge general purpose interrupt input. This pin may be used to wake up
the processor from Sleep, Deep-sleep, or Power-down modes.

EINT1

Input

External Interrupt Input 1 - See the EINT0 description above.

EINT2

Input

External Interrupt Input 2 - See the EINT0 description above.

EINT3

Input

External Interrupt Input 3 - See the EINT0 description above.

RESET

Input

External Reset input - A LOW on this pin resets the chip, causing I/O
ports and peripherals to take on their default states, and the processor to
begin execution at address 0x0000 0000.

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3.3 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 7.

Summary of system control registers

Name

Description

Access

Reset value

Address

External Interrupts

EXTINT

External Interrupt Flag Register

R/W

0x400F C140

EXTMODE

External Interrupt Mode register

R/W

0x400F C148

EXTPOLAR

External Interrupt Polarity Register

R/W

0x400F C14C

Reset Source Identification Register

R/W

see Table 8

0x400F C180

R/W

0x400F C1A0

Reset

RSID

Syscon Miscellaneous Registers

SCS

System Control and Status

3.4 Reset
Reset has 4 sources on the LPC176x/5x: the RESET pin, Watchdog Reset, Power On
Reset (POR), and Brown Out Detect (BOD).
The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once
the operating voltage attains a usable level, starts the wake-up timer (see description in
Section 4.9 “Wake-up timer” in this chapter), causing reset to remain asserted until the
external Reset is de-asserted, the oscillator is running, a fixed number of clocks have
passed, and the flash controller has completed its initialization. The reset logic is shown in
the following block diagram (see Figure 4).

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external
reset

Reset to the
on-chip circuitry

C
Q

watchdog
reset

Reset to
PCON.PD

POR
BOD

WAKE-UP TIMER
START

power-down

COUNT 2 n

EINT0 wake-up
EINT1 wake-up

internal RC
oscillator

S
write “1”
from APB

EINT2 wake-up
EINT3 wake-up
RTC wake-up
BOD wake-up
Ethernet MAC wake-up

reset
APB read of
PDBIT
in PCON

USB need_clk wake-up
CAN wake-up
GPIO0 port wake-up
GPIO2 port wake-up

Fig 4.

FOSC
to other
blocks

Reset block diagram including the wake-up timer

On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset,
External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time
(maximum of 60 s on power-up) and after the IRC provides a stable clock output, the
reset signal is latched and synchronized on the IRC clock. Then the following two
sequences start simultaneously:
1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is
de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times
out. The boot code performs the boot tasks and may jump to the flash. If the flash is
not ready to access, the Flash Accelerator will insert wait cycles until the flash is
ready.
2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is
de-asserted. The flash wake-up timer generates the 100 s flash start-up time. Once
it times out, the flash initialization sequence is started, which takes about 250 cycles.
When it’s done, the Flash Accelerator will be granted access to the flash.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Figure 5 shows an example of the relationship between the RESET, the IRC, and the
processor status when the LPC176x/5x starts up after reset. See Section 4.3.2 “Main
oscillator” for start-up of the main oscillator if selected by the user code.

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IRC
starts

IRC
stable

IRC status

RESET

VDD(REG)(3V3)
valid threshold

GND

60 µs

1 µs; IRC stability count
boot time

supply ramp-up
time

7 µs

181 µs

224 µs

user code

processor status
flash read
starts

Fig 5.

flash read
finishes

boot code
execution
finishes;
user code starts

Example of start-up after reset

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3.4.1 Reset Source Identification Register (RSID - 0x400F C180)
This register contains one bit for each source of Reset. Writing a 1 to any of these bits
clears the corresponding read-side bit to 0. The interactions among the four sources are
described below.
Table 8.

Reset Source Identification register (RSID - address 0x400F C180) bit description

Bit

Symbol Description

Reset
value

POR

Assertion of the POR signal sets this bit, and clears all of the other bits in
this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.

See
text

EXTR

Assertion of the RESET signal sets this bit. This bit is cleared only by
software or POR.

See
text

WDTR

This bit is set when the Watchdog Timer times out and the WDTRESET bit See
in the Watchdog Mode Register is 1. This bit is cleared only by software or text
POR.

BODR

This bit is set when the VDD(REG)(3V3) voltage reaches a level below the
BOD reset trip level (typically 1.85 V under nominal room temperature
conditions).

See
text

If the VDD(REG)(3V3) voltage dips from the normal operating range to below
the BOD reset trip level and recovers, the BODR bit will be set to 1.
If the VDD(REG)(3V3) voltage dips from the normal operating range to below
the BOD reset trip level and continues to decline to the level at which POR
is asserted (nominally 1 V), the BODR bit is cleared.
If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level
above the BOD reset trip level, the BODR will be set to 1.
This bit is cleared only by software or POR.
Note: Only in the case where a reset occurs and the POR = 0, the BODR
bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level
or not.

31:4 -

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Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.

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3.5 Brown-out detection
The LPC176x/5x includes a Brown-Out Detector (BOD) that provides 2-stage monitoring
of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below the BOD interrupt trip
level (typically 2.2 V under nominal room temperature conditions), the BOD asserts an
interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt
Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor
the signal by reading the Raw Interrupt Status Register.
The second stage of low-voltage detection asserts Reset to inactivate the LPC176x/5x
when the voltage on the VDD(REG)(3V3) pins falls below the BOD reset trip level (typically
1.85 V under nominal room temperature conditions). This Reset prevents alteration of the
flash as operation of the various elements of the chip would otherwise become unreliable
due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point
the Power-On Reset circuitry maintains the overall Reset.
Both the BOD reset interrupt level and the BOD reset trip level thresholds include some
hysteresis. In normal operation, this hysteresis allows the BOD reset interrupt level
detection to reliably interrupt, or a regularly-executed event loop to sense the condition.
But when Brown-Out Detection is enabled to bring the LPC176x/5x out of Power-down
mode (which is itself not a guaranteed operation -- see Section 4.8.7 “Power Mode
Control register (PCON - 0x400F C0C0)”), the supply voltage may recover from a
transient before the wake-up timer has completed its delay. In this case, the net result of
the transient BOD is that the part wakes up and continues operation after the instructions
that set Power-down mode, without any interrupt occurring and with the BOD bit in the
RSID being 0. Since all other wake-up conditions have latching flags (see Section 3.6.2
“External Interrupt flag register (EXTINT - 0x400F C140)” and Section 27.6.2), a wake-up
of this type, without any apparent cause, can be assumed to be a Brown-Out that has
gone away.

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3.6 External interrupt inputs
TheLPC176x/5x includes four External Interrupt Inputs as selectable pin functions. The
logic of an individual external interrupt is represented in Figure 6. In addition, external
interrupts have the ability to wake up the CPU from Power-down mode. Refer to
Section 4.8.8 “Wake-up from Reduced Power Modes” for details.

EINTi interrupt enable
EINTi pin

EINTi to wakeup timer

GLITCH
FILTER

Interrupt flag
(one bit of EXTINT)

EXTPOLARi
S
1

S
Q

EXTMODEi

S
Q

PCLK

internal reset
write to EXTINTi
Fig 6.

to interrupt
controller
APB read
of EXTINTi

100621

External interrupt logic

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3.6.1 Register description
The external interrupt function has four registers associated with it. The EXTINT register
contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level
and edge sensitivity parameters.
Table 9.

External Interrupt registers

Name

Description

Access

Reset
Address
value[1]

EXTINT

The External Interrupt Flag Register contains
interrupt flags for EINT0, EINT1, EINT2 and
EINT3. See Table 10.

R/W

0x00

0x400F C140

EXTMODE

The External Interrupt Mode Register controls
whether each pin is edge- or level-sensitive.
See Table 11.

R/W

0x00

0x400F C148

EXTPOLAR

The External Interrupt Polarity Register controls R/W
which level or edge on each pin will cause an
interrupt. See Table 12.

0x00

0x400F C14C

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

3.6.2 External Interrupt flag register (EXTINT - 0x400F C140)
When a pin is selected for its external interrupt function, the level or edge on that pin
(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in
this register. This asserts the corresponding interrupt request to the NVIC, which will
cause an interrupt if interrupts from the pin are enabled.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding
bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
event that was just triggered by activity on the EINT pin will not be recognized in future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt), the
corresponding bit in the EXTINT register must be cleared! For details see
Section 3.6.3 “External Interrupt Mode register (EXTMODE - 0x400F C148)” and
Section 3.6.4 “External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)”.
For example, if a system wakes up from Power-down using low level on external interrupt
0 pin, its post wake-up code must reset EINT0 bit in order to allow future entry into the
Power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke
Power-down mode will fail. The same goes for external interrupt handling.
More details on Power-down mode will be discussed in the following chapters.

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Table 10.

External Interrupt Flag register (EXTINT - address 0x400F C140) bit description

Bit

Symbol Description

Reset
value

EINT0

In level-sensitive mode, this bit is set if the EINT0 function is selected for
its pin, and the pin is in its active state. In edge-sensitive mode, this bit is
set if the EINT0 function is selected for its pin, and the selected edge
occurs on the pin.
This bit is cleared by writing a one to it, except in level sensitive mode
when the pin is in its active state.[1]

EINT1

In level-sensitive mode, this bit is set if the EINT1 function is selected for
its pin, and the pin is in its active state. In edge-sensitive mode, this bit is
set if the EINT1 function is selected for its pin, and the selected edge
occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode
when the pin is in its active state.[1]
2

EINT2

In level-sensitive mode, this bit is set if the EINT2 function is selected for
its pin, and the pin is in its active state. In edge-sensitive mode, this bit is
set if the EINT2 function is selected for its pin, and the selected edge
occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode
when the pin is in its active state.[1]
3

EINT3

In level-sensitive mode, this bit is set if the EINT3 function is selected for
its pin, and the pin is in its active state. In edge-sensitive mode, this bit is
set if the EINT3 function is selected for its pin, and the selected edge
occurs on the pin.

This bit is cleared by writing a one to it, except in level sensitive mode
when the pin is in its active state.[1]
31:4 [1]

Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.

Example: e.g. if the EINTx is selected to be low level sensitive and low level is present on

corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the
pin becomes high.

3.6.3 External Interrupt Mode register (EXTMODE - 0x400F C148)
The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins
that are selected for the EINT function (see Section 8.5) and enabled in the appropriate
NVIC register) can cause interrupts from the External Interrupt function (though of course
pins selected for other functions may cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write
the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the
interrupt. An extraneous interrupt(s) could be set by changing the mode and not
having the EXTINT cleared.

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Table 11.

External Interrupt Mode register (EXTMODE - address 0x400F C148) bit
description

Bit

Symbol

Value Description

Reset
value

EXTMODE0

Level-sensitivity is selected for EINT0.

EINT0 is edge sensitive.

1
2
3

EXTMODE1
EXTMODE2
EXTMODE3

31:4 -

Level-sensitivity is selected for EINT1.

EINT1 is edge sensitive.

Level-sensitivity is selected for EINT2.

EINT2 is edge sensitive.

0
0

Level-sensitivity is selected for EINT3.

EINT3 is edge sensitive.

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

0
NA

3.6.4 External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive. Only pins that are selected for the EINT function Only pins that are
selected for the EINT function (see Section 8.5) and enabled in the appropriate NVIC
register) can cause interrupts from the External Interrupt function (though of course pins
selected for other functions may cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write
the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the
interrupt. An extraneous interrupt(s) could be set by changing the polarity and not
having the EXTINT cleared.
Table 12.
Bit

Symbol

EXTPOLAR0 0

EINT0 is low-active or falling-edge sensitive (depending on
EXTMODE0).

EINT0 is high-active or rising-edge sensitive (depending on
EXTMODE0).

EXTPOLAR1 0

EINT1 is low-active or falling-edge sensitive (depending on
EXTMODE1).

EINT1 is high-active or rising-edge sensitive (depending on
EXTMODE1).

EXTPOLAR2 0

EINT2 is low-active or falling-edge sensitive (depending on
EXTMODE2).

EINT2 is high-active or rising-edge sensitive (depending on
EXTMODE2).

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External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit
description
Value Description

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Table 12.
Bit

Symbol

EXTPOLAR3 0

EINT3 is low-active or falling-edge sensitive (depending on
EXTMODE3).

EINT3 is high-active or rising-edge sensitive (depending on
EXTMODE3).

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

31:4 -

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External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit
description
Value Description

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Reset
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3.7 Other system controls and status flags
Some aspects of controlling LPC176x/5x operation that do not fit into peripheral or other
registers are grouped here.

3.7.1 System Controls and Status register (SCS - 0x400F C1A0)
The SCS register contains several control/status bits related to the main oscillator. Since
chip operation always begins using the Internal RC Oscillator, and the main oscillator may
not be used at all in some applications, it will only be started by software request. This is
accomplished by setting the OSCEN bit in the SCS register, as described in Table 3-13.
The main oscillator provides a status flag (the OSCSTAT bit in the SCS register) so that
software can determine when the oscillator is running and stable. At that point, software
can control switching to the main oscillator as a clock source. Prior to starting the main
oscillator, a frequency range must be selected by configuring the
OSCRANGE bit in the SCS register.
Table 13.
Bit

Symbol

Value Description

3:0

OSCRANGE

User manual

Access Reset
value

Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is
not defined.

Main oscillator range select.

R/W

The frequency range of the main oscillator is 1 MHz
to 20 MHz.

The frequency range of the main oscillator is
15 MHz to 25 MHz.

OSCEN

Main oscillator enable.
0

The main oscillator is disabled.

The main oscillator is enabled, and will start up if
the correct external circuitry is connected to the
XTAL1 and XTAL2 pins.

OSCSTAT

31:7 -

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System Controls and Status register (SCS - address 0x400F C1A0) bit description

Main oscillator status.
0

The main oscillator is not ready to be used as a
clock source.

The main oscillator is ready to be used as a clock
source. The main oscillator must be enabled via the
OSCEN bit.

Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is
not defined.

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4.1 Summary of clocking and power control functions
This section describes the generation of the various clocks needed by the LPC176x/5x
and options of clock source selection, as well as power control and wake-up from reduced
power modes. Functions described in the following subsections include:

•
•
•
•
•
•
•
•

Oscillators
Clock source selection
PLLs
Clock dividers
APB dividers
Power control
Wake-up timer
External clock output

USB PLL settings
(PLL1...)

USB PLL
select
(PLL1CON)

USB PLL
(PLL1)
main PLL
settings
(PLL0...)

osc_clk
rtc_clk
irc_osc

sysclk

usb_clk

USB
Clock
Divider

CPU PLL
select
(PLL0CON)

USB clock divider setting
USBCLKCFG[3:0]

Main PLL
(PLL0)

system clock select
CLKSRCSEL[1:0]

pllclk

CPU
Clock
Divider

cclk

CPU clock divider setting
CCLKCFG[7:0]

watchdog clock select
WDCLKSEL[1:0]

Peripheral
Clock
Divider

pclk1
pclk2
pclk4
pclk8
wd_clk

PCLK_WDT

Fig 7.

Clock generation for the LPC176x/5x

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4.2 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 14.

Summary of system control registers

Name

Description

Access

Reset value Address

R/W

0x400F C10C

Clock source selection
CLKSRCSEL

Clock Source Select Register

Phase Locked Loop (PLL0, Main PLL)

PLL0CON

PLL0 Control Register

R/W

0x400F C080

PLL0CFG

PLL0 Configuration Register

R/W

0x400F C084

PLL0STAT

PLL0 Status Register

0x400F C088

PLL0FEED

PLL0 Feed Register

0x400F C08C

PLL1 Control Register

R/W

0x400F C0A0

PLL1CFG

PLL1 Configuration Register

R/W

0x400F C0A4

PLL1STAT

PLL1 Status Register

0x400F C0A8

PLL1FEED

PLL1 Feed Register

0x400F C0AC

CCLKCFG

CPU Clock Configuration Register

R/W

0x400F C104

USBCLKCFG

USB Clock Configuration Register

R/W

0x400F C108

PCLKSEL0

Peripheral Clock Selection register 0.

R/W

0x400F C1A8

PCLKSEL1

Peripheral Clock Selection register 1.

R/W

0x400F C1AC

PCON

Power Control Register

R/W

0x400F C0C0

PCONP

Power Control for Peripherals Register

R/W

0x03BE

0x400F C0C4

Clock Output Configuration Register

R/W

0x400F C1C8

Phase Locked Loop (PLL1, USB PLL)

PLL1CON

Clock dividers

Power control

Utility
CLKOUTCFG

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4.3 Oscillators
The LPC176x/5x includes three independent oscillators. These are the Main Oscillator,
the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more
than one purpose as required in a particular application. This can be seen in Figure 7.
Following Reset, the LPC176x/5x will operate from the Internal RC Oscillator until
switched by software. This allows systems to operate without any external crystal, and
allows the boot loader code to operate at a known frequency.

4.3.1 Internal RC oscillator
The Internal RC Oscillator (IRC) may be used as the clock source for the watchdog timer,
and/or as the clock that drives PLL0 and subsequently the CPU. The precision of the IRC
does not allow for use of the USB interface, which requires a much more precise time
base in order to comply with the USB specification. Also, the IRC should not be used with
the CAN1/2 block if the CAN baud rate is higher than 100 kbit/s.The nominal IRC
frequency is 4 MHz.
Upon power-up or any chip reset, the LPC176x/5x uses the IRC as the clock source.
Software may later switch to one of the other available clock sources.

4.3.2 Main oscillator
The main oscillator can be used as the clock source for the CPU, with or without using
PLL0. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency
can be boosted to a higher frequency, up to the maximum CPU operating frequency, by
the Main PLL (PLL0). The oscillator output is called OSC_CLK. The clock selected as the
PLL0 input is PLLCLKIN and the ARM processor clock frequency is referred to as CCLK
for purposes of rate equations, etc. elsewhere in this document. The frequencies of
PLLCLKIN and CCLK are the same value unless the PLL0 is active and connected. Refer
to Section 4.5 “PLL0 (Phase Locked Loop 0)” for details.
The on-board oscillator in the LPC176x/5x can operate in one of two modes: slave mode
and oscillation mode.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(CC in Figure 8, drawing a), with an amplitude between 200 mVrms and 1000 mVrms.
This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4
V. The XTAL2 pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 8,
drawings b and c, and in Table 15 and Table 16. Since the feedback resistance is
integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected
externally in case of fundamental mode oscillation (the fundamental frequency is
represented by L, CL and RS). Capacitance CP in Figure 8, drawing c, represents the
parallel package capacitance and should not be larger than 7 pF. Parameters FC, CL, RS
and CP are supplied by the crystal manufacturer.

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LPC17xx

XTAL1

LPC17xx

XTAL2

XTAL1

XTAL2
L

<=>

CC
Clock

Xtal

CX1

Fig 8.

CX2

Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external
crystal model used for CX1/X2 evaluation
Table 15.

Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) low frequency mode (OSCRANGE = 0, see Table 13)

Fundamental oscillation
frequency FOSC

Crystal load
capacitance CL

Maximum crystal
series resistance RS

External load
capacitors CX1, CX2

1 MHz to 5 MHz

10 pF

< 300

18 pF, 18 pF

20 pF

< 300

39 pF, 39 pF

30 pF

< 300

57 pF, 57 pF

10 pF

< 300

18 pF, 18 pF

20 pF

< 200

39 pF, 39 pF

30 pF

< 100

57 pF, 57 pF

10 pF

< 160

18 pF, 18 pF

20 pF

< 60

39 pF, 39 pF

10 pF

< 80

18 pF, 18 pF

5 MHz to 10 MHz

10 MHz to 15 MHz
15 MHz to 20 MHz
Table 16.

Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) high frequency mode (OSCRANGE = 1, see Table 13)

Fundamental oscillation
frequency FOSC

Crystal load
capacitance CL

Maximum crystal
series resistance RS

External load
capacitors CX1, CX2

15 MHz to 20 MHz

10 pF

< 180

18 pF, 18 pF

20 pF

< 100

39 pF, 39 pF

10 pF

< 160

18 pF, 18 pF

20 pF

< 80

39 pF, 39 pF

20 MHz to 25 MHz

Since chip operation always begins using the Internal RC Oscillator, and the main
oscillator may not be used at all in some applications, it will only be started by software
request. This is accomplished by setting the OSCEN bit in the SCS register, as described
in Table 13. The main oscillator provides a status flag (the OSCSTAT bit in the SCS
register) so that software can determine when the oscillator is running and stable. At that
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point, software can control switching to the main oscillator as a clock source. Prior to
starting the main oscillator, a frequency range must be selected by configuring the
OSCRANGE bit in the SCS register.

4.3.3 RTC oscillator
The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can
be used as the clock source for PLL0 and CPU and/or the watchdog timer.
Remark: The RTC oscillator must not be used as a clock source when the PLL0 output is
selected to drive the USB controller. In this case select the main oscillator as clock source
for PLL0 (see also Table 17).

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4.4 Clock source selection multiplexer
Several clock sources may be chosen to drive PLL0 and ultimately the CPU and on-chip
peripheral devices. The clock sources available are the main oscillator, the RTC oscillator,
and the Internal RC oscillator.
The clock source selection can only be changed safely when PLL0 is not connected. For a
detailed description of how to change the clock source in a system using PLL0 see
Section 4.5.13 “PLL0 setup sequence”.
Note the following restrictions regarding the choice of clock sources:

• Only the main oscillator must be used (via PLL0) as the clock source for the USB
subsystem. The IRC or RTC oscillators do not provide the proper tolerances for this
use.

• The IRC oscillator should not be used (via PLL0) as the clock source for the CAN
controllers if the CAN baud rate is higher than 100 kbit/s.

4.4.1 Clock Source Select register (CLKSRCSEL - 0x400F C10C)
The CLKSRCSEL register contains the bits that select the clock source for PLL0.
Table 17.

Clock Source Select register (CLKSRCSEL - address 0x400F C10C) bit
description

Bit

Symbol

1:0

CLKSRC

Value Description

Reset
value

Selects the clock source for PLL0 as follows:

Selects the Internal RC oscillator as the PLL0 clock source
(default).

Selects the main oscillator as the PLL0 clock source.
Remark: Select the main oscillator as PLL0 clock source if the
PLL0 clock output is used for USB or for CAN with baudrates
> 100 kBit/s.

Selects the RTC oscillator as the PLL0 clock source.

Reserved, do not use this setting.

Warning: Improper setting of this value, or an incorrect sequence of
changing this value may result in incorrect operation of the device.
31:2

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Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

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4.5 PLL0 (Phase Locked Loop 0)
PLL0 accepts an input clock frequency in the range of 32 kHz to 50 MHz. The clock
source is selected in the CLKSRCSEL register (see Section 4.4). The input frequency is
multiplied up to a high frequency, then divided down to provide the actual clock used by
the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem
has its own dedicated PLL (see Section 4.6). PLL0 can produce a clock up to the
maximum allowed for the CPU, which is 120 MHz on high speed versions (LPC1769 and
LPC1759), and 100 MHz on other versions.

4.5.1 PLL0 operation
The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value
"N", which may be in the range of 1 to 256. This input division provides a greater number
of possibilities in providing a wide range of output frequencies from the same input
frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the
range of 6 through 512, plus additional values listed in Table 21. The resulting frequency
must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO
output by the value of M, then using a phase-frequency detector to compare the divided
CCO output to the multiplier input. The error value is used to adjust the CCO frequency.
There are additional dividers at the output of PLL0 to bring the frequency down to what is
needed for the CPU, peripherals, and potentially the USB subsystem. PLL0 output
dividers are described in the Clock Dividers section following the PLL0 description. A
block diagram of PLL0 is shown in Figure 9
PLL activation is controlled via the PLL0CON register. PLL0 multiplier and divider values
are controlled by the PLL0CFG register. These two registers are protected in order to
prevent accidental alteration of PLL0 parameters or deactivation of the PLL. Since all chip
operations, including the Watchdog Timer, could be dependent on PLL0 if so configured
(for example when it is providing the chip clock), accidental changes to the PLL0 setup
values could result in unexpected or fatal behavior of the microcontroller. The protection is
accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLL0FEED register.
PLL0 is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL0 must be configured, enabled, and connected to the system by software.
It is important that the setup procedure described in Section 4.5.13 “PLL0 setup
sequence” is followed or PLL0 might not operate at all!

4.5.1.1 PLL0 and startup/boot code interaction
When there is no valid user code (determined by the checksum word) in the user flash or
the ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the
boot code will setup the PLL with the IRC. Therefore it can not be assumed that the PLL is
disabled when the user opens a debug session to debug the application code. The user
startup code must follow the steps described in this chapter to disconnect the PLL.

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4.5.2 PLL0 register description
PLL0 is controlled by the registers shown in Table 18. More detailed descriptions follow.
Warning: Improper setting of PLL0 values may result in incorrect operation of the
device!
Table 18.

PLL0 registers

Name

Description

PLL0CON

PLL0 Control Register. Holding register for
R/W
updating PLL0 control bits. Values written to this
register do not take effect until a valid PLL0 feed
sequence has taken place.

0x400F C080

PLL0CFG

PLL0 Configuration Register. Holding register for R/W
updating PLL0 configuration values. Values
written to this register do not take effect until a
valid PLL0 feed sequence has taken place.

0x400F C084

PLL0STAT

PLL0 Status Register. Read-back register for
RO
PLL0 control and configuration information. If
PLL0CON or PLL0CFG have been written to, but
a PLL0 feed sequence has not yet occurred, they
will not reflect the current PLL0 state. Reading
this register provides the actual values controlling
the PLL0, as well as the PLL0 status.

0x400F C088

PLL0FEED

PLL0 Feed Register. This register enables
loading of the PLL0 control and configuration
information from the PLL0CON and PLL0CFG
registers into the shadow registers that actually
affect PLL0 operation.

0x400F C08C

[1]

Access Reset
Address
value[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

PLLC
PLLE
PLOCK

pd
refclk
pllclkin

N-DIVIDER
NSEL
[7:0]

PHASEFREQUENCY
DETECTOR

FILTER

M-DIVIDER

CCO

pllclk

MSEL
[14:0]

Fig 9.

PLL0 block diagram

4.5.3 PLL0 Control register (PLL0CON - 0x400F C080)
The PLL0CON register contains the bits that enable and connect PLL0. Enabling PLL0
allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting PLL0 causes the processor and most chip functions to run from the PLL0
output clock. Changes to the PLL0CON register do not take effect until a correct PLL0
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feed sequence has been given (see Section 4.5.8 “PLL0 Feed register (PLL0FEED 0x400F C08C)”).
Table 19.

PLL Control register (PLL0CON - address 0x400F C080) bit description

Bit

Symbol

Description

Reset
value

PLLE0

PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate 0
PLL0 and allow it to lock to the requested frequency. See PLL0STAT
register, Table 22.

PLLC0

PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and
locked, then followed by a valid PLL0 feed sequence causes PLL0 to
become the clock source for the CPU, AHB peripherals, and used to
derive the clocks for APB peripherals. The PLL0 output may potentially
be used to clock the USB subsystem if the frequency is 48 MHz. See
PLL0STAT register, Table 22.

31:2

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

PLL0 must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL0 output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that PLL0 is locked before it is connected or automatically
disconnect PLL0 if lock is lost during operation. In the event of loss of lock on PLL0, it is
likely that the oscillator clock has become unstable and disconnecting PLL0 will not
remedy the situation.

4.5.4 PLL0 Configuration register (PLL0CFG - 0x400F C084)
The PLL0CFG register contains PLL0 multiplier and divider values. Changes to the
PLL0CFG register do not take effect until a correct PLL feed sequence has been given
(see Section 4.5.8 “PLL0 Feed register (PLL0FEED - 0x400F C08C)”). Calculations for
the PLL frequency, and multiplier and divider values are found in the Section 4.5.10 “PLL0
frequency calculation”.
Table 20.

PLL0 Configuration register (PLL0CFG - address 0x400F C084) bit description

Bit

Symbol

Description

Reset
value

14:0

MSEL0

PLL0 Multiplier value. Supplies the value "M" in PLL0 frequency
calculations. The value stored here is M - 1. Supported values for M
are 6 through 512 and those listed in Table 21.

Note: Not all values of M are needed, and therefore some are not
supported by hardware. For details on selecting values for MSEL0 see
Section 4.5.10 “PLL0 frequency calculation”.

23:16 NSEL0

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

PLL0 Pre-Divider value. Supplies the value "N" in PLL0 frequency
0
calculations. The value stored here is N - 1. Supported values for N are
1 through 32.
Note: For details on selecting the right value for NSEL0 see
Section 4.5.10 “PLL0 frequency calculation”.

31:24 -

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Table 21.

Multiplier values for PLL0 with a 32 kHz input

Multiplier
(M)

Pre-divide
(N)

FCCO

Multiplier
(M)

Pre-divide
(N)

FCCO

4272

279.9698

12085

396.0013

4395

288.0307

12207

399.9990

4578

300.0238

12817

419.9875

4725

309.6576

12817

279.9916

4807

315.0316

13184

432.0133

5127

336.0031

13184

288.0089

5188

340.0008

13672

448.0041

5400

353.8944

13733

450.0029

5493

359.9892

13733

300.0020

5859

383.9754

13916

455.9995

6042

395.9685

14099

461.9960

6075

398.1312

14420

315.0097

6104

400.0317

14648

479.9857

6409

420.0202

15381

504.0046

6592

432.0133

15381

336.0031

6750

442.3680

15564

340.0008

6836

448.0041

15625

512.0000

6866

449.9702

15869

519.9954

6958

455.9995

16113

527.9908

7050

462.0288

16479

359.9892

7324

479.9857

17578

383.9973

7425

486.6048

18127

395.9904

7690

503.9718

18311

400.0099

7813

512.0328

19226

419.9984

7935

520.0282

19775

431.9915

8057

528.0236

20508

448.0041

8100

530.8416

20599

449.9920

8545

280.0026

20874

455.9995

8789

287.9980

21149

462.0070

9155

299.9910

21973

480.0075

9613

314.9988

23071

503.9937

10254

336.0031

23438

512.0109

10376

340.0008

23804

520.0063

10986

359.9892

24170

528.0017

11719

384.0082

4.5.5 PLL0 Status register (PLL0STAT - 0x400F C088)
The read-only PLL0STAT register provides the actual PLL0 parameters that are in effect
at the time it is read, as well as PLL0 status. PLL0STAT may disagree with values found in
PLL0CON and PLL0CFG because changes to those registers do not take effect until a
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proper PLL0 feed has occurred (see Section 4.5.8 “PLL0 Feed register (PLL0FEED 0x400F C08C)”).
Table 22.

PLL Status register (PLL0STAT - address 0x400F C088) bit description

Bit

Symbol

Description

14:0

MSEL0

Read-back for the PLL0 Multiplier value. This is the value currently 0
used by PLL0, and is one less than the actual multiplier.

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

23:16 NSEL0

Read-back for the PLL0 Pre-Divider value. This is the value
currently used by PLL0, and is one less than the actual divider.

Reset
value

PLLE0_STAT Read-back for the PLL0 Enable bit. This bit reflects the state of the 0
PLEC0 bit in PLL0CON (see Table 19) after a valid PLL0 feed.
When one, PLL0 is currently enabled. When zero, PLL0 is turned
off. This bit is automatically cleared when Power-down mode is
entered.

PLLC0_STAT Read-back for the PLL0 Connect bit. This bit reflects the state of
the PLLC0 bit in PLL0CON (see Table 19) after a valid PLL0 feed.

When PLLC0 and PLLE0 are both one, PLL0 is connected as the
clock source for the CPU. When either PLLC0 or PLLE0 is zero,
PLL0 is bypassed. This bit is automatically cleared when
Power-down mode is entered.
26

PLOCK0

31:27 -

Reflects the PLL0 Lock status. When zero, PLL0 is not locked.
When one, PLL0 is locked onto the requested frequency. See text
for details.

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

4.5.6 PLL0 Interrupt: PLOCK0
The PLOCK0 bit in the PLL0STAT register reflects the lock status of PLL0. When PLL0 is
enabled, or parameters are changed, PLL0 requires some time to establish lock under the
new conditions. PLOCK0 can be monitored to determine when PLL0 may be connected
for use. The value of PLOCK0 may not be stable when the PLL reference frequency
(FREF, the frequency of REFCLK, which is equal to the PLL input frequency divided by the
pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL
may be assumed to be stable after a start-up time has passed. This time is 500 s when
FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less than 400 kHz
PLOCK0 is connected to the interrupt controller. This allows for software to turn on PLL0
and continue with other functions without having to wait for PLL0 to achieve lock. When
the interrupt occurs, PLL0 may be connected, and the interrupt disabled. PLOCK0
appears as interrupt 32 in Table 50. Note that PLOCK0 remains asserted whenever PLL0
is locked, so if the interrupt is used, the interrupt service routine must disable the PLOCK0
interrupt prior to exiting.

4.5.7 PLL0 Modes
The combinations of PLLE0 and PLLC0 are shown in Table 23.

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Table 23.

PLL control bit combinations

PLLC0 PLLE0 PLL Function

PLL0 is turned off and disconnected. PLL0 outputs the unmodified clock input.

PLL0 is active, but not yet connected. PLL0 can be connected after PLOCK0 is
asserted.

Same as 00 combination. This prevents the possibility of PLL0 being connected
without also being enabled.

PLL0 is active and has been connected as the system clock source.

4.5.8 PLL0 Feed register (PLL0FEED - 0x400F C08C)
A correct feed sequence must be written to the PLL0FEED register in order for changes to
the PLL0CON and PLL0CFG registers to take effect. The feed sequence is:
1. Write the value 0xAA to PLL0FEED.
2. Write the value 0x55 to PLL0FEED.
The two writes must be in the correct sequence, and there must be no other register
access in the same address space (0x400F C000 to 0x400F FFFF) between them.
Because of this, it may be necessary to disable interrupts for the duration of the PLL0 feed
operation, if there is a possibility that an interrupt service routine could write to another
register in that space. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLL0CON or PLL0CFG register will
not become effective.
Table 24.

PLL Feed register (PLL0FEED - address 0x400F C08C) bit description

Bit

Symbol

Description

Reset
value

7:0

PLL0FEED The PLL0 feed sequence must be written to this register in order for
PLL0 configuration and control register changes to take effect.

0x00

31:8

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

4.5.9 PLL0 and Power-down mode
Power-down mode automatically turns off and disconnects PLL0. Wake-up from
Power-down mode does not automatically restore PLL0 settings, this must be done in
software. Typically, a routine to activate PLL0, wait for lock, and then connect PLL0 can be
called at the beginning of any interrupt service routine that might be called due to the
wake-up. It is important not to attempt to restart PLL0 by simply feeding it when execution
resumes after a wake-up from Power-down mode. This would enable and connect PLL0
at the same time, before PLL lock is established.

4.5.10 PLL0 frequency calculation
PLL0 equations use the following parameters:

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Table 25.

PLL frequency parameter

Parameter

Description

FIN

the frequency of PLLCLKIN from the Clock Source Selection Multiplexer.

FCCO

the frequency of the PLLCLK (output of the PLL Current Controlled Oscillator)

PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG
NSEL0 field + 1). N is an integer from 1 through 32.

PLL0 Multiplier value from the MSEL0 bits in the PLL0CFG register (PLL0CFG
MSEL0 field + 1). Not all potential values are supported. See below.

FREF

PLL internal reference frequency, FIN divided by N.

The PLL0 output frequency (when PLL0 is both active and connected) is given by:
FCCO = (2

FIN) / N

PLL inputs and settings must meet the following:

• FIN is in the range of 32 kHz to 50 MHz.
• FCCO is in the range of 275 MHz to 550 MHz.
The equation can be solved for other PLL parameters:
M = (FCCO

N) / (2

N = (2

FIN) / FCCO

FIN = (FCCO

FIN)

N) / (2

Allowed values for M:
At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are
allowed. This supports the entire useful range of both the main oscillator and the IRC.
For lower frequencies, specifically when the RTC is used to clock PLL0, a set of 65
additional M values have been selected for supporting baud rate generation, CAN
operation, and obtaining integer MHz frequencies. These values are shown in Table 26.
Table 26.

Additional Multiplier Values for use with a Low Frequency Clock Input

Low Frequency PLL Multipliers

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4272

4395

4578

4725

4807

5127

5188

5400

5493

5859

6042

6075

6104

6409

6592

6750

6836

6866

6958

7050

7324

7425

7690

7813

7935

8057

8100

8545

8789

9155

9613

10254

10376

10986

11719

12085

12207

12817

13184

13672

13733

13916

14099

14420

14648

15381

15564

15625

15869

16113

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Table 26.

Additional Multiplier Values for use with a Low Frequency Clock Input

Low Frequency PLL Multipliers

16479

17578

18127

18311

19226

19775

20508

20599

20874

21149

21973

23071

23438

23804

24170

4.5.11 Procedure for determining PLL0 settings
PLL0 parameter determination can be simplified by using a spreadsheet available from
NXP. To determine PLL0 parameters by hand, the following general procedure may be
used:
1. Determine if the application requires use of the USB interface, and whether it will be
clocked from PLL0. The USB requires a 50% duty cycle clock of 48 MHz within a very
small tolerance, which means that FCCO must be an even integer multiple of 48 MHz
(i.e. an integer multiple of 96 MHz), within a very small tolerance.
2. Choose the desired processor operating frequency (CCLK). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
frequency than that of the processor (see Section 4.7 “Clock dividers” on page 55 and
Section 4.8 “Power control” on page 59). Find a value for FCCO that is close to a
multiple of the desired CCLK frequency, bearing in mind the requirement for USB
support in [1] above, and that lower values of FCCO result in lower power dissipation.
3. Choose a value for the PLL input frequency (FIN). This can be a clock obtained from
the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support,
the main oscillator should be used. Bear in mind that if PLL1 rather than PLL0 is used
to clock the USB subsystem, this affects the choice of the main oscillator frequency.
4. Calculate values for M and N to produce a sufficiently accurate FCCO frequency. The
desired M value -1 will be written to the MSEL0 field in PLL0CFG. The desired N value
-1 will be written to the NSEL0 field in PLL0CFG.
In general, it is better to use a smaller value for N, to reduce the level of multiplication that
must be accomplished by the CCO. Due to the difficulty in finding the best values in some
cases, it is recommended to use a spreadsheet or similar method to show many
possibilities at once, from which an overall best choice may be selected. A spreadsheet is
available from NXP for this purpose.

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4.5.12 Examples of PLL0 settings
The following table gives a summary of examples that illustrate selecting PLL0 values
based on different system requirements.
Table 27.

Summary of PLL0 examples

Example

Description

• The PLL0 clock source is 10 MHz.
• PLL0 is not used as the USB clock source, or the USB interface is not used.
• The desired CPU clock is 100 MHz.

• The PLL0 clock source is 4 MHz.
• PLL0 is used as the USB clock source.
• The desired CPU clock is 60 MHz.

• The PLL0 clock source is the 32.768 kHz RTC clock.
• PLL0 is not used as the USB clock source, or the USB interface is not used.
• The desired CPU clock is 72 MHz.

Example 1
Assumptions:

• The USB interface will not be used in the application, or will be clocked by PLL1.
• The desired CPU rate is 100 MHz.
• An external 10 MHz crystal or clock source will be used as the system clock source.
Calculations:
M = (FCCO

N) / (2

FIN)

A smaller value for the PLL pre-divide (N) as well as a smaller value of the multiplier (M),
both result in better PLL operational stability and lower output jitter. Lower values of FCCO
also save power. So, the process of determining PLL setup parameters involves looking
for the smallest N and M values giving the lowest FCCO value that will support the required
CPU and/or USB clocks. It is usually easier to work backward from the desired output
clock rate and determine a target FCCO rate, then find a way to obtain that FCCO rate from
the available input clock.
Potential precise values of FCCO are integer multiples of the desired CPU clock. In this
example, it is clear that the smallest frequency for FCCO that can produce the desired CPU
clock rate and is within the PLL0 operating range of 275 to 550 MHz is 300 MHz
(3 ´ 100 MHz).
Assuming that the PLL pre-divide is 1 (N = 1), the equation above gives
M = ((300 ´ 106 ´ 1) / (2 10 ´ 106) = 300 / 20 = 15. Since the result is an integer, there is
no need to look any further for a good set of PLL0 configuration values. The value written
to PLL0CFG would be 0x0E (N - 1 = 0; M - 1 = 14 gives 0x0E).
The PLL output must be further divided in order to produce the CPU clock. This is
accomplished using a separate divider that is described later in this chapter, see
Section 4.7.1.

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Example 2
Assumptions:

• The USB interface will be used in the application and will be clocked from PLL0.
• The desired CPU rate is 60 MHz.
• An external 4 MHz crystal or clock source will be used as the system clock source.
This clock source could be the Internal RC oscillator (IRC).
Calculations:
M = (FCCO

N) / (2

FIN)

Because supporting USB requires a precise 48 MHz clock with a 50% duty cycle, that
need must be addressed first. Potential precise values of FCCO are integer multiples of the
2 ´ the 48 MHz USB clock. The 2 ´ insures that the clock has a 50% duty cycle, which
would not be the case for a division of the PLL output by an odd number.
The possibilities for the FCCO rate when the USB is used are 288 MHz, 384 MHz, and 480
MHz. The smallest frequency for FCCO that can produce a valid USB clock rate and is
within the PLL0 operating range is 288 MHz (3 ´ 2 ´ 48 MHz).
Start by assuming N = 1, since this produces the smallest multiplier needed for PLL0. So,
M = ((288 ´ 106) ´ 1) / (2 (4 ´ 106)) = 288 / 8 = 36. The result is an integer, which is
necessary to obtain a precise USB clock. The value written to PLL0CFG would be 0x23
(N - 1 = 0; M - 1 = 35 = 0x23).
The potential CPU clock rate can be determined by dividing FCCO by the desired CPU
frequency: 288 ´ 106 / 60 ´ 106 = 4.8. The nearest integer value for the CPU Clock Divider
is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
If it is important to obtain exactly 60 MHz, an FCCO rate must be found that can be divided
down to both 48 MHz and 60 MHz. As previously noted, the possibilities for the FCCO rate
when the USB is used are 288 MHz, 384 MHz, and 480 MHz. Of these, only is 480 MHz is
also evenly divisible by 60. Divided by 10, this gives the 48 MHz with a 50% duty cycle
needed by the USB subsystem. Divided by 8, it gives 60 MHz for the CPU clock. PLL0
settings for 480 MHz are N = 1 and M = 60.
The PLL output must be further divided in order to produce both the CPU clock and the
USB clock. This is accomplished using separate dividers that are described later in this
chapter. See Section 4.7.1 and Section 4.7.2.

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Example 3
Assumptions:

• The USB interface will not be used in the application, or will be clocked by PLL1.
• The desired CPU rate is 72 MHz
• The 32.768 kHz RTC clock source will be used as the system clock source
Calculations:
M = (FCCO

N) / (2

FIN)

The smallest integer multiple of the desired CPU clock rate that is within the PLL0
operating range is 288 MHz (4 ´ 72 MHz).
Using the equation above and assuming that N = 1, M = ((288 ´ 106) ´ 1) / (2 32,768) =
4,394.53125. This is not an integer, so the CPU frequency will not be exactly 72 MHz with
this setting. Since this example is less obvious, it may be useful to make a table of
possibilities for different values of N (see below).
Table 28.

Potential values for PLL example

M Rounded

FREF in
Hz (FIN /
N)

FCCO in
CCLK in MHz
Error
MHz (FREF x (FCCO / 4)
(CCLK-72) / 72
M)

4394.53125

4395

32768

288.0307

72.0077

0.0107

8789.0625

8789

16384

287.9980

71.9995

-0.0007

13183.59375

13184

10922.67

288.0089

72.0022

0.0031

17578.125

17578

8192

287.9980

71.9995

-0.0007

21972.65625

21973

6553.6

288.0045

72.0011

0.0016

Beyond N = 5, the value of M is out of range or not supported, so the table stops at that
point. In the third column of the table, the calculated M value is rounded to the nearest
integer. If this results in CCLK being above the maximum operating frequency, it is
allowed if it is not more than 1/2 above the maximum frequency.
In general, larger values of FREF result in a more stable PLL when the input clock is a low
frequency. Even the first table entry shows a very small error of just over 1 hundredth of a
percent, or 107 parts per million (ppm). If that is not accurate enough in the application,
the second case gives a much smaller error of 7 ppm. There are no allowed combinations
that give a smaller error than that.
Remember that when a frequency below about 1 MHz is used as the PLL0 clock source,
not all multiplier values are available. As it turns out, all of the rounded M values found in
Table 28 of this example are supported, which may be confirmed in Table 26. If PLL0
calculations suggest use of unsupported multiplier values, those values must be
disregarded and other values examined to find the best fit.
The value written to PLL0CFG for the second table entry would be 0x12254
(N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254).
The PLL output must be further divided in order to produce the CPU clock. This is
accomplished using a separate divider that is described later in this chapter, see
Section 4.7.1.
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4.5.13 PLL0 setup sequence
The following sequence must be followed step by step in order to have PLL0 initialized
and running:
1. Disconnect PLL0 with one feed sequence if PLL0 is already connected.
2. Disable PLL0 with one feed sequence.
3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired.
4. Write to the Clock Source Selection Control register to change the clock source if
needed.
5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG
can only be updated when PLL0 is disabled.
6. Enable PLL0 with one feed sequence.
7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do
this before connecting PLL0.
8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register,
or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is
slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input
frequency divided by the pre-divider value) is less than 100 kHz or greater than
20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time
has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF
seconds when FREF is less than 400 kHz.
9. Connect PLL0 with one feed sequence.
It is very important not to merge any steps above. For example, do not update the
PLL0CFG and enable PLL0 simultaneously with the same feed sequence.

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4.6 PLL1 (Phase Locked Loop 1)
PLL1 receives its clock input from the main oscillator only and can be used to provide a
fixed 48 MHz clock only to the USB subsystem. This is an option in addition to the
possibility of generating the USB clock from PLL0.
PLL1 is disabled and powered off on reset. If PLL1 is left disabled, the USB clock can be
supplied by PLL0 if everything is set up to provide 48 MHz through that route. If PLL1 is
enabled and connected via the PLL1CON register (see Section 4.6.2), it is automatically
selected to drive the USB subsystem (see Figure 7).
PLL1 activation is controlled via the PLL1CON register. PLL1 multiplier and divider values
are controlled by the PLL1CFG register. These two registers are protected in order to
prevent accidental alteration of PLL1 parameters or deactivation of PLL1. The protection
is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLL1FEED register.
PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input
frequency is multiplied up to the range of 48 MHz for the USB clock using a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (for USB,
the multiplier value cannot be higher than 4. The CCO operates in the range of 156 MHz
to 320 MHz, so there is an additional divider in the loop to keep the CCO within its
frequency range while PLL1 is providing the desired output frequency. The output divider
may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum
output divider value is 2, it is insured that the output of PLL1 has a 50% duty cycle. A
block diagram of PLL1 is shown in Figure 10.

4.6.1 PLL1 register description
PLL1 is controlled by the registers shown in Table 29. More detailed descriptions follow.
Writes to any unused bits are ignored. A read of any unused bits will return a logic zero.
Warning: Improper setting of PLL1 values may result in incorrect operation of the
USB subsystem!
Table 29.

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PLL1 registers

Name

Description

PLL1CON

PLL1 Control Register. Holding register for
R/W
updating PLL1 control bits. Values written to this
register do not take effect until a valid PLL1 feed
sequence has taken place.

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0x400F C0A0

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Table 29.

PLL1 registers

Name

Description

Access Reset
Address
value[1]

PLL1CFG

PLL1 Configuration Register. Holding register
for updating PLL1 configuration values. Values
written to this register do not take effect until a
valid PLL1 feed sequence has taken place.

R/W

PLL1STAT

PLL1FEED

[1]

0x400F C0A4

PLL1 Status Register. Read-back register for
RO
PLL1 control and configuration information. If
PLL1CON or PLL1CFG have been written to,
but a PLL1 feed sequence has not yet occurred,
they will not reflect the current PLL1 state.
Reading this register provides the actual values
controlling PLL1, as well as PLL1 status.

0x400F C0A8

PLL1 Feed Register. This register enables
loading of PLL1 control and configuration
information from the PLL1CON and PLL1CFG
registers into the shadow registers that actually
affect PLL1 operation.

0x400F C0AC

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

PLOCK
PLLSTAT[10]
PLL input
clock
Phase
Detector

CurrentControlled
Oscillator

Fcco

Divide by 2P

PLL output
clock

PSEL
PLLSTAT[6:5]
Divide by M

MSEL
PLLSTAT[4:0]

100416

Fig 10. PLL1 block diagram

4.6.2 PLL1 Control register (PLL1CON - 0x400F C0A0)
The PLL1CON register contains the bits that enable and connect PLL1. Enabling PLL1
allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting PLL1 causes the USB subsystem to run from the PLL1 output clock. Changes
to the PLL1CON register do not take effect until a correct PLL feed sequence has been
given (see Section 4.6.6 and Section 4.6.3).

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Table 30.

PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description

Bit

Symbol

Description

Reset
value

PLLE1

PLL1 Enable. When one, and after a valid PLL1 feed, this bit will
activate PLL1 and allow it to lock to the requested frequency. See
PLL1STAT register, Table 32.

PLLC1

PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and
locked, then followed by a valid PLL1 feed sequence causes PLL1 to
become the clock source for the USB subsystem via the USB clock
divider. See PLL1STAT register, Table 32.

31:2

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

PLL1 must be set up, enabled, and lock established before it may be used as a clock
source for the USB subsystem. The hardware does not insure that the PLL is locked
before it is connected nor does it automatically disconnect the PLL if lock is lost during
operation.

4.6.3 PLL1 Configuration register (PLL1CFG - 0x400F C0A4)
The PLL1CFG register contains the PLL1 multiplier and divider values. Changes to the
PLL1CFG register do not take effect until a correct PLL1 feed sequence has been given
(see Section 4.6.6). Calculations for the PLL1 frequency, and multiplier and divider values
are found in Section 4.6.9.
Table 31.

PLL Configuration register (PLL1CFG - address 0x400F C0A4) bit description

Bit

Symbol

Description

Reset
value

4:0

MSEL1

PLL1 Multiplier value. Supplies the value "M" in the PLL1 frequency
calculations.

Note: For details on selecting the right value for MSEL1 see
Section 4.6.8.

6:5

PSEL1

PLL1 Divider value. Supplies the value "P" in the PLL1 frequency
calculations.

Note: For details on selecting the right value for PSEL1 see
Section 4.6.8.

31:7

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

4.6.4 PLL1 Status register (PLL1STAT - 0x400F C0A8)
The read-only PLL1STAT register provides the actual PLL1 parameters that are in effect
at the time it is read, as well as the PLL1 status. PLL1STAT may disagree with values
found in PLL1CON and PLL1CFG because changes to those registers do not take effect
until a proper PLL1 feed has occurred (see Section 4.6.6 “PLL1 Feed register (PLL1FEED
- 0x400F C0AC)”).

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Table 32.

PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description

Bit

Symbol

Description

4:0

MSEL1

Read-back for the PLL1 Multiplier value. This is the value currently 0
used by PLL1.

6:5

PSEL1

Read-back for the PLL1 Divider value. This is the value currently
used by PLL1.

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

PLLE1_STAT Read-back for the PLL1 Enable bit. When one, PLL1 is currently
activated. When zero, PLL1 is turned off. This bit is automatically
cleared when Power-down mode is activated.

PLLC1_STAT Read-back for the PLL1 Connect bit. When PLLC and PLLE are
0
both one, PLL1 is connected as the clock source for the
microcontroller. When either PLLC or PLLE is zero, PLL1 is
bypassed and the oscillator clock is used directly by the
microcontroller. This bit is automatically cleared when Power-down
mode is activated.

PLOCK1

31:11 -

Reset
value

Reflects the PLL1 Lock status. When zero, PLL1 is not locked.
When one, PLL1 is locked onto the requested frequency.

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

4.6.4.1 PLL1 modes
The combinations of PLLE1 and PLLC1 are shown in Table 33.
Table 33.

PLL1 control bit combinations

PLLC1

PLLE1

PLL1 Function

PLL1 is turned off and disconnected.

PLL1 is active, but not yet connected. PLL1 can be connected after PLOCK1
is asserted.

Same as 00 combination. This prevents the possibility of PLL1 being
connected without also being enabled.

PLL1 is active and has been connected. The clock for the USB subsystem is
sourced from PLL1.

4.6.5 PLL1 Interrupt: PLOCK1
The PLOCK1 bit in the PLL1STAT register reflects the lock status of PLL1. When PLL1 is
enabled, or parameters are changed, the PLL requires some time to establish lock under
the new conditions. PLOCK1 can be monitored to determine when the PLL may be
connected for use.
PLOCK1 is connected to the interrupt controller. This allows for software to turn on the
PLL and continue with other functions without having to wait for the PLL to achieve lock.
When the interrupt occurs, the PLL may be connected, and the interrupt disabled.
PLOCK1 appears as interrupt 48 in Table 50. Note that PLOCK1 remains asserted
whenever PLL1 is locked, so if the interrupt is used, the interrupt service routine must
disable the PLOCK1 interrupt prior to exiting.

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4.6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC)
A correct feed sequence must be written to the PLL1FEED register in order for changes to
the PLL1CON and PLL1CFG registers to take effect. The feed sequence is:
1. Write the value 0xAA to PLL1FEED.
2. Write the value 0x55 to PLL1FEED.
The two writes must be in the correct sequence, and there must be no other register
access in the same address space (0x400F C000 to 0x400F FFFF) between them.
Because of this, it may be necessary to disable interrupts for the duration of the PLL feed
operation, if there is a possibility that an interrupt service routine could write to another
register in that space. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLL1CON or PLL1CFG register will
not become effective.
Table 34.

PLL1 Feed register (PLL1FEED - address 0x400F C0AC) bit description

Bit

Symbol

Description

Reset
value

7:0

PLL1FEED

The PLL1 feed sequence must be written to this register in order for
PLL1 configuration and control register changes to take effect.

0x00

31:8

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

4.6.7 PLL1 and Power-down mode
Power-down mode automatically turns off and disconnects activated PLL(s). Wake-up
from Power-down mode does not automatically restore PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wake-up. It is important not to attempt to restart a PLL by simply feeding it when
execution resumes after a wake-up from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
If activity on the USB data lines is not selected to wake the microcontroller from
Power-down mode (see Section 4.8.8 for details of wake up from reduced modes), both
the Main PLL (PLL0) and the USB PLL (PLL1) will be automatically be turned off and
disconnected when Power-down mode is invoked, as described above. However, if the
USB activity interrupt is enabled and USB_NEED_CLK = 1 (see Table 192 for a
description of USB_NEED_CLK), it is not possible to go into Power-down mode and any
attempt to set the PD bit will fail, leaving the PLLs in the current state.

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4.6.8 PLL1 frequency calculation
The PLL1 equations use the following parameters:
Table 35.

Elements determining PLL frequency

Element

Description

FOSC

the frequency from the crystal oscillator

FCCO

the frequency of the PLL1 current controlled oscillator

USBCLK

the PLL1 output frequency (48 MHz for USB)

PLL1 Multiplier value from the MSEL1 bits in the PLL1CFG register

PLL1 Divider value from the PSEL1 bits in the PLL1CFG register

The PLL1 output frequency (when the PLL is both active and connected) is given by:
USBCLK = M

FOSC or USBCLK = FCCO / (2

The CCO frequency can be computed as:
FCCO = USBCLK

P or FCCO = FOSC ´ M

The PLL1 inputs and settings must meet the following criteria:

• FOSC is in the range of 10 MHz to 25 MHz.
• USBCLK is 48 MHz.
• FCCO is in the range of 156 MHz to 320 MHz.
4.6.9 Procedure for determining PLL1 settings
The PLL1 configuration for USB may be determined as follows:
1. The desired PLL1 output frequency is USBCLK = 48 MHz.
2. Choose an oscillator frequency (FOSC). USBCLK must be the whole (non-fractional)
multiple of FOSC meaning that the possible values for FOSC are 12 MHz, 16 MHz, and
24 MHz.
3. Calculate the value of M to configure the MSEL1 bits. M = USBCLK / FOSC. In this
case, the possible values for M = 2, 3, or 4 (FOSC = 24 MHz, 16 MHz, or 12 MHz). The
value written to the MSEL1 bits in PLL1CFG is M - 1 (see Table 37).
4. Find a value for P to configure the PSEL1 bits, such that FCCO is within its defined
frequency limits of 156 MHz to 320 MHz. FCCO is calculated using FCCO = USBCLK
2 P. It follows that P = 2 is the only P value to yield FCCO in the allowed range. The
value written to the PSEL1 bits in PLL1CFG is ‘01’ for P = 2 (see Table 36).

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Table 36. PLL1 Divider values
Values allowed for using PLL1 with USB are highlighted.
PSEL1 Bits (PLL1CFG bits [6:5])

Value of P

Table 37. PLL1 Multiplier values
Values allowed for using PLL1 with USB are highlighted.

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MSEL1 Bits (PLL1CFG bits [4:0])

Value of M

00000

00001

00010

00011

...

11110

11111

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4.7 Clock dividers
The output of the PLL0 must be divided down for use by the CPU and the USB subsystem
(if used with PLL0, see Section 4.6). Separate dividers are provided such that the CPU
frequency can be determined independently from the USB subsystem, which always
requires 48 MHz with a 50% duty cycle for proper operation.

USB PLL settings
(PLL1...)

osc_clk

USB PLL select
(PLL1CON)

USB PLL
(PLL1)
main PLL
settings
(PLL0...)

sysclk

CPU PLL
select
(PLL0CON)

Main PLL
(PLL0)

pllclk

USB
Clock
Divider

usb_clk

USB clock divider setting
USBCLKCFG[3:0]
CPU
Clock
Divider

cclk

CPU clock divider setting
CCLKCFG[7:0]

Fig 11. PLLs and clock dividers

4.7.1 CPU Clock Configuration register (CCLKCFG - 0x400F C104)
The CCLKCFG register controls the division of the PLL0 output before it is used by the
CPU. When PLL0 is bypassed, the division may be by 1. When PLL0 is running, the
output must be divided in order to bring the CPU clock frequency (CCLK) within operating
limits. An 8-bit divider allows a range of options, including slowing CPU operation to a low
rate for temporary power savings without turning off PLL0.

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Table 38.

CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit
description

Bit

Symbol

7:0

CCLKSEL

31:8

Value

Description

Reset
value

Selects the divide value for creating the CPU clock (CCLK)
from the PLL0 output.

0x00

pllclk is divided by 1 to produce the CPU clock. This setting is
not allowed when the PLL0 is connected, because the rate
would always be greater than the maximum allowed CPU
clock.

pllclk is divided by 2 to produce the CPU clock. This setting is
not allowed when the PLL0 is connected, because the rate
would always be greater than the maximum allowed CPU
clock.

pllclk is divided by 3 to produce the CPU clock.

pllclk is divided by 4 to produce the CPU clock.

pllclk is divided by 5 to produce the CPU clock.

255

pllclk is divided by 256 to produce the CPU clock.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1. Having
CCLKSEL = 2 results in CCLK being one third of the PLL0 output, CCLKSEL = 3 results in
CCLK being one quarter of the PLL0 output, etc.

4.7.2 USB Clock Configuration register (USBCLKCFG - 0x400F C108)
This register is used only if the USB PLL (PLL1) is not connected (via the PLLC1 bit in
PLL1CON). If PLL1 is connected, its output is automatically used as the USB clock
source, and PLL1 must be configured to supply the correct 48 MHz clock to the USB
subsystem. If PLL1 is not connected, the USB subsystem will be driven by PLL0 via the
USB clock divider.
The USBCLKCFG register controls the division of the PLL0 output before it is used by the
USB subsystem.The PLL0 output must be divided in order to bring the USB clock
frequency to 48 MHz with a 50% duty cycle. A 4-bit divider allows obtaining the correct
USB clock from any even multiple of 48 MHz (i.e. any multiple of 96 MHz) within the PLL
operating range.
Remark: The Internal RC oscillator should not be used to drive PLL0 when the USB is
using PLL0 as a clock source because a more precise clock is needed for USB
specification compliance (see Table 17).

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Table 39.

USB Clock Configuration register (USBCLKCFG - address 0x400F C108) bit
description

Bit

Symbol

3:0

USBSEL

Value Description

Reset
value

Selects the divide value for creating the USB clock from the
PLL0 output. Only the values shown below can produce even
number multiples of 48 MHz from the PLL0 output.

Warning: Improper setting of this value will result in incorrect
operation of the USB interface.

31:4

PLL0 output is divided by 6. PLL0 output must be 288 MHz.

PLL0 output is divided by 8. PLL0 output must be 384 MHz.

PLL0 output is divided by 10. PLL0 output must be 480 MHz.

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

4.7.3 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 0x400F C1A8 and PCLKSEL1 - 0x400F C1AC)
A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal
that will be supplied to the corresponding peripheral as specified in Table 40, Table 41 and
Table 42.
Remark: The peripheral clock for the RTC block is fixed at CCLK/8.
Table 40.
Bit

Symbol

Description

Reset
value

1:0

PCLK_WDT

Peripheral clock selection for WDT.

3:2

PCLK_TIMER0

Peripheral clock selection for TIMER0.

5:4

PCLK_TIMER1

Peripheral clock selection for TIMER1.

7:6

PCLK_UART0

Peripheral clock selection for UART0.

9:8

PCLK_UART1

Peripheral clock selection for UART1.