UM10360 LPC176x/5x User Manual LPC176x

• Chapter 1: LPC176x/5x Introductory information
  • 1.1 Introduction
  • 1.2 Features
  • 1.3 Applications
  • 1.4 Ordering information
    • 1.4.1 Part options summary
  • 1.5 Simplified block diagram
  • 1.6 Architectural overview
  • 1.7 ARM Cortex-M3 processor
    • 1.7.1 Cortex-M3 Configuration Options
  • System options:
  • Debug related options:
  • 1.8 On-chip flash memory system
  • 1.9 On-chip Static RAM
  • 1.10 Block diagram
• Chapter 2: LPC176x/5x Memory map
  • 2.1 Memory map and peripheral addressing
  • 2.2 Memory maps
  • 2.3 APB peripheral addresses
  • 2.4 Memory re-mapping
  • Boot ROM re-mapping
  • 2.5 AHB arbitration
  • 2.6 Bus fault exceptions
• Chapter 3: LPC176x/5x System control
  • 3.1 Introduction
  • 3.2 Pin description
  • 3.3 Register description
  • 3.4 Reset
    • 3.4.1 Reset Source Identification Register (RSID - 0x400F C180)
  • 3.5 Brown-out detection
  • 3.6 External interrupt inputs
    • 3.6.1 Register description
    • 3.6.2 External Interrupt flag register (EXTINT - 0x400F C140)
    • 3.6.3 External Interrupt Mode register (EXTMODE - 0x400F C148)
    • 3.6.4 External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)
  • 3.7 Other system controls and status flags
    • 3.7.1 System Controls and Status register (SCS - 0x400F C1A0)
• Chapter 4: LPC176x/5x Clocking and power control
  • 4.1 Summary of clocking and power control functions
  • 4.2 Register description
  • 4.3 Oscillators
    • 4.3.1 Internal RC oscillator
    • 4.3.2 Main oscillator
    • 4.3.3 RTC oscillator
  • 4.4 Clock source selection multiplexer
    • 4.4.1 Clock Source Select register (CLKSRCSEL - 0x400F C10C)
  • 4.5 PLL0 (Phase Locked Loop 0)
    • 4.5.1 PLL0 operation
      • 4.5.1.1 PLL0 and startup/boot code interaction
    • 4.5.2 PLL0 register description
    • 4.5.3 PLL0 Control register (PLL0CON - 0x400F C080)
    • 4.5.4 PLL0 Configuration register (PLL0CFG - 0x400F C084)
    • 4.5.5 PLL0 Status register (PLL0STAT - 0x400F C088)
    • 4.5.6 PLL0 Interrupt: PLOCK0
    • 4.5.7 PLL0 Modes
    • 4.5.8 PLL0 Feed register (PLL0FEED - 0x400F C08C)
    • 4.5.9 PLL0 and Power-down mode
    • 4.5.10 PLL0 frequency calculation
    • 4.5.11 Procedure for determining PLL0 settings
    • 4.5.12 Examples of PLL0 settings
  • Example 1
  • Example 2
  • Example 3
    • 4.5.13 PLL0 setup sequence
  • 4.6 PLL1 (Phase Locked Loop 1)
    • 4.6.1 PLL1 register description
    • 4.6.2 PLL1 Control register (PLL1CON - 0x400F C0A0)
    • 4.6.3 PLL1 Configuration register (PLL1CFG - 0x400F C0A4)
    • 4.6.4 PLL1 Status register (PLL1STAT - 0x400F C0A8)
      • 4.6.4.1 PLL1 modes
    • 4.6.5 PLL1 Interrupt: PLOCK1
    • 4.6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC)
    • 4.6.7 PLL1 and Power-down mode
    • 4.6.8 PLL1 frequency calculation
    • 4.6.9 Procedure for determining PLL1 settings
  • 4.7 Clock dividers
    • 4.7.1 CPU Clock Configuration register (CCLKCFG - 0x400F C104)
    • 4.7.2 USB Clock Configuration register (USBCLKCFG - 0x400F C108)
    • 4.7.3 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 - 0x400F C1A8 and PCLKSEL1 - 0x400F C1AC)
  • 4.8 Power control
    • 4.8.1 Sleep mode
    • 4.8.2 Deep Sleep mode
    • 4.8.3 Power-down mode
    • 4.8.4 Deep Power-down mode
    • 4.8.5 Peripheral power control
    • 4.8.6 Register description
    • 4.8.7 Power Mode Control register (PCON - 0x400F C0C0)
      • 4.8.7.1 Encoding of Reduced Power Modes
    • 4.8.8 Wake-up from Reduced Power Modes
    • 4.8.9 Power Control for Peripherals register (PCONP - 0x400F C0C4)
    • 4.8.10 Power control usage notes
    • 4.8.11 Power domains
  • 4.9 Wake-up timer
  • 4.10 External clock output pin
    • 4.10.1 Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8)
• Chapter 5: LPC176x/5x Flash accelerator
  • 5.1 Introduction
  • 5.2 Flash accelerator blocks
    • 5.2.1 Flash memory bank
    • 5.2.2 Flash programming Issues
  • 5.3 Register description
  • 5.4 Flash Accelerator Configuration register (FLASHCFG - 0x400F C000)
  • 5.5 Operation
• Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
  • 6.1 Features
  • 6.2 Description
  • 6.3 Interrupt sources
  • 6.4 Vector table remapping
  • Examples:
  • 6.5 Register description
    • 6.5.1 Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100)
    • 6.5.2 Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104)
    • 6.5.3 Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180)
    • 6.5.4 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184)
    • 6.5.5 Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200)
    • 6.5.6 Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204)
    • 6.5.7 Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280)
    • 6.5.8 Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284)
    • 6.5.9 Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300)
    • 6.5.10 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304)
    • 6.5.11 Interrupt Priority Register 0 (IPR0 - 0xE000 E400)
    • 6.5.12 Interrupt Priority Register 1 (IPR1 - 0xE000 E404)
    • 6.5.13 Interrupt Priority Register 2 (IPR2 - 0xE000 E408)
    • 6.5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C)
    • 6.5.15 Interrupt Priority Register 4 (IPR4 - 0xE000 E410)
    • 6.5.16 Interrupt Priority Register 5 (IPR5 - 0xE000 E414)
    • 6.5.17 Interrupt Priority Register 6 (IPR6 - 0xE000 E418)
    • 6.5.18 Interrupt Priority Register 7 (IPR7 - 0xE000 E41C)
    • 6.5.19 Interrupt Priority Register 8 (IPR8 - 0xE000 E420)
    • 6.5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00)
• Chapter 7: LPC176x/5x Pin configuration
  • 7.1 LPC176x/5x pin configuration
    • 7.1.1 LPC176x/5x pin description
• Chapter 8: LPC176x/5x Pin connect block
  • 8.1 How to read this chapter
  • 8.2 Description
  • 8.3 Pin function select register values
  • Multiple connections
  • 8.4 Pin mode select register values
  • Function of PINMODE in open drain mode
  • 8.5 Register description
  • Pin control module register reset values
    • 8.5.1 Pin Function Select register 0 (PINSEL0 - 0x4002 C000)
    • 8.5.2 Pin Function Select Register 1 (PINSEL1 - 0x4002 C004)
    • 8.5.3 Pin Function Select register 2 (PINSEL2 - 0x4002 C008)
    • 8.5.4 Pin Function Select Register 3 (PINSEL3 - 0x4002 C00C)
    • 8.5.5 Pin Function Select Register 4 (PINSEL4 - 0x4002 C010)
    • 8.5.6 Pin Function Select Register 7 (PINSEL7 - 0x4002 C01C)
    • 8.5.7 Pin Function Select Register 9 (PINSEL9 - 0x4002 C024)
    • 8.5.8 Pin Function Select Register 10 (PINSEL10 - 0x4002 C028)
    • 8.5.9 Pin Mode select register 0 (PINMODE0 - 0x4002 C040)
    • 8.5.10 Pin Mode select register 1 (PINMODE1 - 0x4002 C044)
    • 8.5.11 Pin Mode select register 2 (PINMODE2 - 0x4002 C048)
    • 8.5.12 Pin Mode select register 3 (PINMODE3 - 0x4002 C04C)
    • 8.5.13 Pin Mode select register 4 (PINMODE4 - 0x4002 C050)
    • 8.5.14 Pin Mode select register 7 (PINMODE7 - 0x4002 C05C)
    • 8.5.15 Pin Mode select register 9 (PINMODE9 - 0x4002 C064)
    • 8.5.16 Open Drain Pin Mode select register 0 (PINMODE_OD0 - 0x4002 C068)
    • 8.5.17 Open Drain Pin Mode select register 1 (PINMODE_OD1 - 0x4002 C06C)
    • 8.5.18 Open Drain Pin Mode select register 2 (PINMODE_OD2 - 0x4002 C070)
    • 8.5.19 Open Drain Pin Mode select register 3 (PINMODE_OD3 - 0x4002 C074)
    • 8.5.20 Open Drain Pin Mode select register 4 (PINMODE_OD4 - 0x4002 C078)
    • 8.5.21 I2C Pin Configuration register (I2CPADCFG - 0x4002 C07C)
• Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO)
  • 9.1 Basic configuration
  • 9.2 Features
    • 9.2.1 Digital I/O ports
    • 9.2.2 Interrupt generating digital ports
  • 9.3 Applications
  • 9.4 Pin description
  • 9.5 Register description
    • 9.5.1 GPIO port Direction register FIOxDIR (FIO0DIR to FIO4DIR- 0x2009 C000 to 0x2009 C080)
    • 9.5.2 GPIO port output Set register FIOxSET (FIO0SET to FIO4SET - 0x2009 C018 to 0x2009 C098)
    • 9.5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR- 0x2009 C01C to 0x2009 C09C)
    • 9.5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009 C014 to 0x2009 C094)
    • 9.5.5 Fast GPIO port Mask register FIOxMASK (FIO0MASK to FIO4MASK - 0x2009 C010 to 0x2009 C090)
    • 9.5.6 GPIO interrupt registers
      • 9.5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080)
      • 9.5.6.2 GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090)
      • 9.5.6.3 GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0)
      • 9.5.6.4 GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - 0x4002 8094)
      • 9.5.6.5 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4)
      • 9.5.6.6 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084)
      • 9.5.6.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4)
      • 9.5.6.8 GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088)
      • 9.5.6.9 GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8)
      • 9.5.6.10 GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)
      • 9.5.6.11 GPIO Interrupt Clear register for port 2 (IO2IntClr - 0x4002 80AC)
  • 9.6 GPIO usage notes
    • 9.6.1 Example: An instantaneous output of 0s and 1s on a GPIO port
    • 9.6.2 Writing to FIOSET/FIOCLR vs. FIOPIN
• Chapter 10: LPC176x/5x Ethernet
  • 10.1 Basic configuration
  • 10.2 Introduction
  • 10.3 Features
  • 10.4 Architecture and operation
  • 10.5 DMA engine functions
  • 10.6 Overview of DMA operation
  • 10.7 Ethernet Packet
  • 10.8 Overview
    • 10.8.1 Partitioning
    • 10.8.2 Example PHY Devices
  • 10.9 Pin description
  • 10.10 Registers and software interface
    • 10.10.1 Register map
  • 10.11 Ethernet MAC register definitions
    • 10.11.1 MAC Configuration Register 1 (MAC1 - 0x5000 0000)
    • 10.11.2 MAC Configuration Register 2 (MAC2 - 0x5000 0004)
    • 10.11.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0x5000 0008)
    • 10.11.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0x5000 000C)
    • 10.11.5 Collision Window / Retry Register (CLRT - 0x5000 0010)
    • 10.11.6 Maximum Frame Register (MAXF - 0x5000 0014)
    • 10.11.7 PHY Support Register (SUPP - 0x5000 0018)
    • 10.11.8 Test Register (TEST - 0x5000 001C)
    • 10.11.9 MII Mgmt Configuration Register (MCFG - 0x5000 0020)
    • 10.11.10 MII Mgmt Command Register (MCMD - 0x5000 0024)
    • 10.11.11 MII Mgmt Address Register (MADR - 0x5000 0028)
    • 10.11.12 MII Mgmt Write Data Register (MWTD - 0x5000 002C)
    • 10.11.13 MII Mgmt Read Data Register (MRDD - 0x5000 0030)
    • 10.11.14 MII Mgmt Indicators Register (MIND - 0x5000 0034)
    • 10.11.15 Station Address 0 Register (SA0 - 0x5000 0040)
    • 10.11.16 Station Address 1 Register (SA1 - 0x5000 0044)
    • 10.11.17 Station Address 2 Register (SA2 - 0x5000 0048)
  • 10.12 Control register definitions
    • 10.12.1 Command Register (Command - 0x5000 0100)
    • 10.12.2 Status Register (Status - 0x5000 0104)
    • 10.12.3 Receive Descriptor Base Address Register (RxDescriptor - 0x5000 0108)
    • 10.12.4 Receive Status Base Address Register (RxStatus - 0x5000 010C)
    • 10.12.5 Receive Number of Descriptors Register (RxDescriptor - 0x5000 0110)
    • 10.12.6 Receive Produce Index Register (RxProduceIndex - 0x5000 0114)
    • 10.12.7 Receive Consume Index Register (RxConsumeIndex - 0x5000 0118)
    • 10.12.8 Transmit Descriptor Base Address Register (TxDescriptor - 0x5000 011C)
    • 10.12.9 Transmit Status Base Address Register (TxStatus - 0x5000 0120)
    • 10.12.10 Transmit Number of Descriptors Register (TxDescriptorNumber - 0x5000 0124)
    • 10.12.11 Transmit Produce Index Register (TxProduceIndex - 0x5000 0128)
    • 10.12.12 Transmit Consume Index Register (TxConsumeIndex - 0x5000 012C)
    • 10.12.13 Transmit Status Vector 0 Register (TSV0 - 0x5000 0158)
    • 10.12.14 Transmit Status Vector 1 Register (TSV1 - 0x5000 015C)
    • 10.12.15 Receive Status Vector Register (RSV - 0x5000 0160)
    • 10.12.16 Flow Control Counter Register (FlowControlCounter - 0x5000 0170)
    • 10.12.17 Flow Control Status Register (FlowControlStatus - 0x5000 0174)
  • 10.13 Receive filter register definitions
    • 10.13.1 Receive Filter Control Register (RxFilterCtrl - 0x5000 0200)
    • 10.13.2 Receive Filter WoL Status Register (RxFilterWoLStatus - 0x5000 0204)
    • 10.13.3 Receive Filter WoL Clear Register (RxFilterWoLClear - 0x5000 0208)
    • 10.13.4 Hash Filter Table LSBs Register (HashFilterL - 0x5000 0210)
    • 10.13.5 Hash Filter Table MSBs Register (HashFilterH - 0x5000 0214)
  • 10.14 Module control register definitions
    • 10.14.1 Interrupt Status Register (IntStatus - 0x5000 0FE0)
    • 10.14.2 Interrupt Enable Register (IntEnable - 0x5000 0FE4)
    • 10.14.3 Interrupt Clear Register (IntClear - 0x5000 0FE8)
    • 10.14.4 Interrupt Set Register (IntSet - 0x5000 0FEC)
    • 10.14.5 Power-Down Register (PowerDown - 0x5000 0FF4)
  • 10.15 Descriptor and status formats
    • 10.15.1 Receive descriptors and statuses
    • 10.15.2 Transmit descriptors and statuses
  • 10.16 Ethernet block functional description
    • 10.16.1 Overview
    • 10.16.2 AHB interface
  • 10.17 Interrupts
    • 10.17.1 Direct Memory Access (DMA)
    • 10.17.2 Initialization
    • 10.17.3 Transmit process
    • 10.17.4 Receive process
    • 10.17.5 Transmission retry
    • 10.17.6 Status hash CRC calculations
    • 10.17.7 Duplex modes
    • 10.17.8 IEE 802.3/Clause 31 flow control
    • 10.17.9 Half-Duplex mode backpressure
    • 10.17.10 Receive filtering
    • 10.17.11 Power management
    • 10.17.12 Wake-up on LAN
    • 10.17.13 Enabling and disabling receive and transmit
    • 10.17.14 Transmission padding and CRC
    • 10.17.15 Huge frames and frame length checking
    • 10.17.16 Statistics counters
    • 10.17.17 MAC status vectors
    • 10.17.18 Reset
    • 10.17.19 Ethernet errors
  • 10.18 AHB bandwidth
    • 10.18.1 DMA access
    • 10.18.2 Types of CPU access
    • 10.18.3 Overall bandwidth
  • 10.19 CRC calculation
• Chapter 11: LPC176x/5x USB device controller
  • 11.1 How to read this chapter
  • 11.2 Basic configuration
  • 11.3 Introduction
  • 11.4 Features
  • 11.5 Fixed endpoint configuration
  • 11.6 Functional description
    • 11.6.1 Analog transceiver
    • 11.6.2 Serial Interface Engine (SIE)
    • 11.6.3 Endpoint RAM (EP_RAM)
    • 11.6.4 EP_RAM access control
    • 11.6.5 DMA engine and bus master interface
    • 11.6.6 Register interface
    • 11.6.7 SoftConnect
    • 11.6.8 GoodLink
  • 11.7 Operational overview
  • 11.8 Pin description
  • 11.9 Clocking and power management
    • 11.9.1 Power requirements
    • 11.9.2 Clocks
    • 11.9.3 Power management support
    • 11.9.4 Remote wake-up
  • 11.10 Register description
    • 11.10.1 Clock control registers
      • 11.10.1.1 USB Clock Control register (USBClkCtrl - 0x5000 CFF4)
      • 11.10.1.2 USB Clock Status register (USBClkSt - 0x5000 CFF8)
    • 11.10.2 Device interrupt registers
      • 11.10.2.1 USB Interrupt Status register (USBIntSt - 0x5000 C1C0)
      • 11.10.2.2 USB Device Interrupt Status register (USBDevIntSt - 0x5000 C200)
      • 11.10.2.3 USB Device Interrupt Enable register (USBDevIntEn - 0x5000 C204)
      • 11.10.2.4 USB Device Interrupt Clear register (USBDevIntClr - 0x5000 C208)
      • 11.10.2.5 USB Device Interrupt Set register (USBDevIntSet - 0x5000 C20C)
      • 11.10.2.6 USB Device Interrupt Priority register (USBDevIntPri - 0x5000 C22C)
    • 11.10.3 Endpoint interrupt registers
      • 11.10.3.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0x5000 C230)
      • 11.10.3.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0x5000 C234)
      • 11.10.3.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0x5000 C238)
      • 11.10.3.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0x5000 C23C)
      • 11.10.3.5 USB Endpoint Interrupt Priority register (USBEpIntPri - 0x5000 C240)
    • 11.10.4 Endpoint realization registers
      • 11.10.4.1 EP RAM requirements
      • 11.10.4.2 USB Realize Endpoint register (USBReEp - 0x5000 C244)
      • 11.10.4.3 USB Endpoint Index register (USBEpIn - 0x5000 C248)
      • 11.10.4.4 USB MaxPacketSize register (USBMaxPSize - 0x5000 C24C)
    • 11.10.5 USB transfer registers
      • 11.10.5.1 USB Receive Data register (USBRxData - 0x5000 C218)
      • 11.10.5.2 USB Receive Packet Length register (USBRxPLen - 0x5000 C220)
      • 11.10.5.3 USB Transmit Data register (USBTxData - 0x5000 C21C)
      • 11.10.5.4 USB Transmit Packet Length register (USBTxPLen - 0x5000 C224)
      • 11.10.5.5 USB Control register (USBCtrl - 0x5000 C228)
    • 11.10.6 SIE command code registers
      • 11.10.6.1 USB Command Code register (USBCmdCode - 0x5000 C210)
      • 11.10.6.2 USB Command Data register (USBCmdData - 0x5000 C214)
    • 11.10.7 DMA registers
      • 11.10.7.1 USB DMA Request Status register (USBDMARSt - 0x5000 C250)
      • 11.10.7.2 USB DMA Request Clear register (USBDMARClr - 0x5000 C254)
      • 11.10.7.3 USB DMA Request Set register (USBDMARSet - 0x5000 C258)
      • 11.10.7.4 USB UDCA Head register (USBUDCAH - 0x5000 C280)
      • 11.10.7.5 USB EP DMA Status register (USBEpDMASt - 0x5000 C284)
      • 11.10.7.6 USB EP DMA Enable register (USBEpDMAEn - 0x5000 C288)
      • 11.10.7.7 USB EP DMA Disable register (USBEpDMADis - 0x5000 C28C)
      • 11.10.7.8 USB DMA Interrupt Status register (USBDMAIntSt - 0x5000 C290)
      • 11.10.7.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0x5000 C294)
      • 11.10.7.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0x5000 C2A0)
      • 11.10.7.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0x5000 C2A4)
      • 11.10.7.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0x5000 C2A8)
      • 11.10.7.13 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0x5000 C2AC)
      • 11.10.7.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0x5000 C2B0)
      • 11.10.7.15 USB New DD Request Interrupt Set register (USBNDDRIntSet - 0x5000 C2B4)
      • 11.10.7.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0x5000 C2B8)
      • 11.10.7.17 USB System Error Interrupt Clear register (USBSysErrIntClr - 0x5000 C2BC)
      • 11.10.7.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0x5000 C2C0)
  • 11.11 Interrupt handling
  • Slave mode
  • DMA mode
  • 11.12 Serial interface engine command description
    • 11.12.1 Set Address (Command: 0xD0, Data: write 1 byte)
    • 11.12.2 Configure Device (Command: 0xD8, Data: write 1 byte)
    • 11.12.3 Set Mode (Command: 0xF3, Data: write 1 byte)
    • 11.12.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes)
    • 11.12.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)
    • 11.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte)
    • 11.12.7 Get Device Status (Command: 0xFE, Data: read 1 byte)
    • 11.12.8 Get Error Code (Command: 0xFF, Data: read 1 byte)
    • 11.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte)
    • 11.12.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))
    • 11.12.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte)
    • 11.12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte (optional))
    • 11.12.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))
    • 11.12.14 Validate Buffer (Command: 0xFA, Data: none)
  • 11.13 USB device controller initialization
  • 11.14 Slave mode operation
    • 11.14.1 Interrupt generation
    • 11.14.2 Data transfer for OUT endpoints
    • 11.14.3 Data transfer for IN endpoints
  • 11.15 DMA operation
    • 11.15.1 Transfer terminology
    • 11.15.2 USB device communication area
    • 11.15.3 Triggering the DMA engine
    • 11.15.4 The DMA descriptor
      • 11.15.4.1 Next_DD_pointer
      • 11.15.4.2 DMA_mode
      • 11.15.4.3 Next_DD_valid
      • 11.15.4.4 Isochronous_endpoint
      • 11.15.4.5 Max_packet_size
      • 11.15.4.6 DMA_buffer_length
      • 11.15.4.7 DMA_buffer_start_addr
      • 11.15.4.8 DD_retired
      • 11.15.4.9 DD_status
      • 11.15.4.10 Packet_valid
      • 11.15.4.11 LS_byte_extracted
      • 11.15.4.12 MS_byte_extracted
      • 11.15.4.13 Present_DMA_count
      • 11.15.4.14 Message_length_position
      • 11.15.4.15 Isochronous_packetsize_memory_address
    • 11.15.5 Non-isochronous endpoint operation
      • 11.15.5.1 Setting up DMA transfers
      • 11.15.5.2 Finding DMA Descriptor
      • 11.15.5.3 Transferring the data
      • 11.15.5.4 Optimizing descriptor fetch
      • 11.15.5.5 Ending the packet transfer
      • 11.15.5.6 No_Packet DD
    • 11.15.6 Isochronous endpoint operation
      • 11.15.6.1 Setting up DMA transfers
      • 11.15.6.2 Finding the DMA Descriptor
      • 11.15.6.3 Transferring the Data
  • OUT endpoints
  • IN endpoints
    • 11.15.6.4 DMA descriptor completion
    • 11.15.6.5 Isochronous OUT Endpoint Operation Example
    • 11.15.7 Auto Length Transfer Extraction (ATLE) mode operation
  • OUT transfers in ATLE mode
  • IN transfers in ATLE mode
    • 11.15.7.1 Setting up the DMA transfer
    • 11.15.7.2 Finding the DMA Descriptor
    • 11.15.7.3 Transferring the Data
  • OUT endpoints
  • IN endpoints
    • 11.15.7.4 Ending the packet transfer
  • OUT endpoints
  • IN endpoints
  • 11.16 Double buffered endpoint operation
    • 11.16.1 Bulk endpoints
    • 11.16.2 Isochronous endpoints
• Chapter 12: LPC176x/5x USB Host controller
  • 12.1 How to read this chapter
  • 12.2 Basic configuration
  • 12.3 Introduction
    • 12.3.1 Features
    • 12.3.2 Architecture
  • 12.4 Interfaces
    • 12.4.1 Pin description
      • 12.4.1.1 USB host usage note
    • 12.4.2 Software interface
      • 12.4.2.1 Register map
      • 12.4.2.2 USB Host Register Definitions
• Chapter 13: LPC176x/5x USB OTG
  • 13.1 How to read this chapter
  • 13.2 Basic configuration
  • 13.3 Introduction
  • 13.4 Features
  • 13.5 Architecture
  • 13.6 Modes of operation
  • 13.7 Pin configuration
    • 13.7.1 Connecting the USB port to an external OTG transceiver
    • 13.7.2 Connecting USB as a host
    • 13.7.3 Connecting USB as device
  • 13.8 Register description
    • 13.8.1 USB Interrupt Status Register (USBIntSt - 0x5000 C1C0)
    • 13.8.2 OTG Interrupt Status Register (OTGIntSt - 0x5000 C100)
    • 13.8.3 OTG Interrupt Enable Register (OTGIntEn - 0x5000 C104)
    • 13.8.4 OTG Interrupt Set Register (OTGIntSet - 0x5000 C20C)
    • 13.8.5 OTG Interrupt Clear Register (OTGIntClr - 0x5000 C10C)
    • 13.8.6 OTG Status and Control Register (OTGStCtrl - 0x5000 C110)
    • 13.8.7 OTG Timer Register (OTGTmr - 0x5000 C114)
    • 13.8.8 OTG Clock Control Register (OTGClkCtrl - 0x5000 CFF4)
    • 13.8.9 OTG Clock Status Register (OTGClkSt - 0x5000 CFF8)
    • 13.8.10 I2C Receive Register (I2C_RX - 0x5000 C300)
    • 13.8.11 I2C Transmit Register (I2C_TX - 0x5000 C300)
    • 13.8.12 I2C Status Register (I2C_STS - 0x5000 C304)
    • 13.8.13 I2C Control Register (I2C_CTL - 0x5000 C308)
    • 13.8.14 I2C Clock High Register (I2C_CLKHI - 0x5000 C30C)
    • 13.8.15 I2C Clock Low Register (I2C_CLKLO - 0x5000 C310)
    • 13.8.16 Interrupt handling
  • 13.9 HNP support
    • 13.9.1 B-device: peripheral to host switching
  • Remove D+ pull-up
  • Add D+ pull-up
    • 13.9.2 A-device: host to peripheral HNP switching
  • Set BDIS_ACON_EN in external OTG transceiver
  • Clear BDIS_ACON_EN in external OTG transceiver
  • Discharge VBUS
  • Load and enable OTG timer
  • Stop OTG timer
  • Suspend host on port 1
  • 13.10 Clocking and power management
    • 13.10.1 Device clock request signals
      • 13.10.1.1 Host clock request signals
    • 13.10.2 Power-down mode support
  • 13.11 USB OTG controller initialization
• Chapter 14: LPC176x/5x UART0/2/3
  • 14.1 Basic configuration
  • 14.2 Features
  • 14.3 Pin description
  • 14.4 Register description
    • 14.4.1 UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR - 0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0)
    • 14.4.2 UARTn Transmit Holding Register (U0THR - 0x4000 C000, U2THR - 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0)
    • 14.4.3 UARTn Divisor Latch LSB register (U0DLL - 0x4000 C000, U2DLL - 0x4009 8000, U3DLL - 0x4009 C000 when DLAB = 1) and UARTn Divisor Latch MSB register (U0DLM - 0x4000 C004, U2DLL - 0x4009 8004, U3DLL - 0x4009 C004 when DLAB = 1)
    • 14.4.4 UARTn Interrupt Enable Register (U0IER - 0x4000 C004, U2IER - 0x4009 8004, U3IER - 0x4009 C004 when DLAB = 0)
    • 14.4.5 UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR - 0x4009 8008, U3IIR - 0x4009 C008)
    • 14.4.6 UARTn FIFO Control Register (U0FCR - 0x4000 C008, U2FCR - 0x4009 8008, U3FCR - 0x4009 C008)
      • 14.4.6.1 DMA Operation
  • UART receiver DMA
  • UART transmitter DMA
    • 14.4.7 UARTn Line Control Register (U0LCR - 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR - 0x4009 C00C)
    • 14.4.8 UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)
    • 14.4.9 UARTn Scratch Pad Register (U0SCR - 0x4000 C01C, U2SCR - 0x4009 801C U3SCR - 0x4009 C01C)
    • 14.4.10 UARTn Auto-baud Control Register (U0ACR - 0x4000 C020, U2ACR - 0x4009 8020, U3ACR - 0x4009 C020)
      • 14.4.10.1 Auto-baud
      • 14.4.10.2 Auto-baud modes
    • 14.4.11 UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024)
    • 14.4.12 UARTn Fractional Divider Register (U0FDR - 0x4000 C028, U2FDR - 0x4009 8028, U3FDR - 0x4009 C028)
      • 14.4.12.1 Baud rate calculation
        • 14.4.12.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600
        • 14.4.12.1.2 Example 2: PCLK = 12 MHz, BR = 115200
    • 14.4.13 UARTn Transmit Enable Register (U0TER - 0x4000 C030, U2TER - 0x4009 8030, U3TER - 0x4009 C030)
  • 14.5 Architecture
• Chapter 15: LPC176x/5x UART1
  • 15.1 Basic configuration
  • 15.2 Features
  • 15.3 Pin description
  • 15.4 Register description
    • 15.4.1 UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0)
    • 15.4.2 UART1 Transmitter Holding Register (U1THR - 0x4001 0000 when DLAB = 0)
    • 15.4.3 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0x4001 0000 and U1DLM - 0x4001 0004, when DLAB = 1)
    • 15.4.4 UART1 Interrupt Enable Register (U1IER - 0x4001 0004, when DLAB = 0)
    • 15.4.5 UART1 Interrupt Identification Register (U1IIR - 0x4001 0008)
    • 15.4.6 UART1 FIFO Control Register (U1FCR - 0x4001 0008)
      • 15.4.6.1 DMA Operation
  • UART receiver DMA
  • UART transmitter DMA
    • 15.4.7 UART1 Line Control Register (U1LCR - 0x4001 000C)
    • 15.4.8 UART1 Modem Control Register (U1MCR - 0x4001 0010)
    • 15.4.9 Auto-flow control
      • 15.4.9.1 Auto-RTS
      • 15.4.9.2 Auto-CTS
    • 15.4.10 UART1 Line Status Register (U1LSR - 0x4001 0014)
    • 15.4.11 UART1 Modem Status Register (U1MSR - 0x4001 0018)
    • 15.4.12 UART1 Scratch Pad Register (U1SCR - 0x4001 001C)
    • 15.4.13 UART1 Auto-baud Control Register (U1ACR - 0x4001 0020)
    • 15.4.14 Auto-baud
    • 15.4.15 Auto-baud modes
    • 15.4.16 UART1 Fractional Divider Register (U1FDR - 0x4001 0028)
      • 15.4.16.1 Baud rate calculation
        • 15.4.16.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600
        • 15.4.16.1.2 Example 2: PCLK = 12 MHz, BR = 115200
    • 15.4.17 UART1 Transmit Enable Register (U1TER - 0x4001 0030)
    • 15.4.18 UART1 RS485 Control register (U1RS485CTRL - 0x4001 004C)
    • 15.4.19 UART1 RS-485 Address Match register (U1RS485ADRMATCH - 0x4001 0050)
    • 15.4.20 UART1 RS-485 Delay value register (U1RS485DLY - 0x4001 0054)
    • 15.4.21 RS-485/EIA-485 modes of operation
  • RS-485/EIA-485 Normal Multidrop Mode (NMM)
  • RS-485/EIA-485 Auto Address Detection (AAD) mode
  • RS-485/EIA-485 Auto Direction Control
  • RS485/EIA-485 driver delay time
  • RS485/EIA-485 output inversion
  • 15.5 Architecture
• Chapter 16: LPC176x/5x CAN1/2
  • 16.1 Basic configuration
  • 16.2 CAN controllers
  • 16.3 Features
    • 16.3.1 General CAN features
    • 16.3.2 CAN controller features
    • 16.3.3 Acceptance filter features
  • 16.4 Pin description
  • 16.5 CAN controller architecture
    • 16.5.1 APB Interface Block (AIB)
    • 16.5.2 Interface Management Logic (IML)
    • 16.5.3 Transmit Buffers (TXB)
    • 16.5.4 Receive Buffer (RXB)
    • 16.5.5 Error Management Logic (EML)
    • 16.5.6 Bit Timing Logic (BTL)
    • 16.5.7 Bit Stream Processor (BSP)
    • 16.5.8 CAN controller self-tests
  • 16.6 Memory map of the CAN block
  • 16.7 CAN controller registers
    • 16.7.1 CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD - 0x4004 8000)
    • 16.7.2 CAN Command Register (CAN1CMR - 0x4004 x004, CAN2CMR - 0x4004 8004)
    • 16.7.3 CAN Global Status Register (CAN1GSR - 0x4004 x008, CAN2GSR - 0x4004 8008)
    • 16.7.4 CAN Interrupt and Capture Register (CAN1ICR - 0x4004 400C, CAN2ICR - 0x4004 800C)
    • 16.7.5 CAN Interrupt Enable Register (CAN1IER - 0x4004 4010, CAN2IER - 0x4004 8010)
    • 16.7.6 CAN Bus Timing Register (CAN1BTR - 0x4004 4014, CAN2BTR - 0x4004 8014)
    • 16.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)
    • 16.7.8 CAN Status Register (CAN1SR - 0x4004 401C, CAN2SR - 0x4004 801C)
    • 16.7.9 CAN Receive Frame Status register (CAN1RFS - 0x4004 4020, CAN2RFS - 0x4004 8020)
    • 16.7.10 CAN Receive Identifier register (CAN1RID - 0x4004 4024, CAN2RID - 0x4004 8024)
    • 16.7.11 CAN Receive Data register A (CAN1RDA - 0x4004 4028, CAN2RDA - 0x4004 8028)
    • 16.7.12 CAN Receive Data register B (CAN1RDB - 0x4004 402C, CAN2RDB - 0x4004 802C)
    • 16.7.13 CAN Transmit Frame Information register (CAN1TFI[1/2/3] - 0x4004 40[30/ 40/50], CAN2TFI[1/2/3] - 0x4004 80[30/40/50])
    • 16.7.14 CAN Transmit Identifier register (CAN1TID[1/2/3] - 0x4004 40[34/44/54], CAN2TID[1/2/3] - 0x4004 80[34/44/54])
    • 16.7.15 CAN Transmit Data register A (CAN1TDA[1/2/3] - 0x4004 40[38/48/58], CAN2TDA[1/2/3] - 0x4004 80[38/48/58])
    • 16.7.16 CAN Transmit Data register B (CAN1TDB[1/2/3] - 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0x4004 80[3C/4C/5C])
    • 16.7.17 CAN Sleep Clear register (CANSLEEPCLR - 0x400F C110)
    • 16.7.18 CAN Wake-up Flags register (CANWAKEFLAGS - 0x400F C114)
  • 16.8 CAN controller operation
    • 16.8.1 Error handling
    • 16.8.2 Sleep mode
    • 16.8.3 Interrupts
    • 16.8.4 Transmit priority
  • 16.9 Centralized CAN registers
    • 16.9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000)
    • 16.9.2 Central Receive Status Register (CANRxSR - 0x4004 0004)
    • 16.9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008)
  • 16.10 Global acceptance filter
  • 16.11 Acceptance filter modes
    • 16.11.1 Acceptance filter Off mode
    • 16.11.2 Acceptance filter Bypass mode
    • 16.11.3 Acceptance filter Operating mode
    • 16.11.4 FullCAN mode
  • 16.12 Sections of the ID look-up table RAM
  • 16.13 ID look-up table RAM
  • 16.14 Acceptance filter registers
    • 16.14.1 Acceptance Filter Mode Register (AFMR - 0x4003 C000)
    • 16.14.2 Section configuration registers
    • 16.14.3 Standard Frame Individual Start Address register (SFF_sa - 0x4003 C004)
    • 16.14.4 Standard Frame Group Start Address register (SFF_GRP_sa - 0x4003 C008)
    • 16.14.5 Extended Frame Start Address register (EFF_sa - 0x4003 C00C)
    • 16.14.6 Extended Frame Group Start Address register (EFF_GRP_sa - 0x4003 C010)
    • 16.14.7 End of AF Tables register (ENDofTable - 0x4003 C014)
    • 16.14.8 Status registers
    • 16.14.9 LUT Error Address register (LUTerrAd - 0x4003 C018)
    • 16.14.10 LUT Error register (LUTerr - 0x4003 C01C)
    • 16.14.11 Global FullCANInterrupt Enable register (FCANIE - 0x4003 C020)
    • 16.14.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0x4003 C024 and FCANIC1 - 0x4003 C028)
  • 16.15 Configuration and search algorithm
    • 16.15.1 Acceptance filter search algorithm
  • 16.16 FullCAN mode
    • 16.16.1 FullCAN message layout
    • 16.16.2 FullCAN interrupts
    • 16.16.3 Set and clear mechanism of the FullCAN interrupt
  • 16.17 Examples of acceptance filter tables and ID index values
    • 16.17.1 Example 1: only one section is used
    • 16.17.2 Example 2: all sections are used
    • 16.17.3 Example 3: more than one but not all sections are used
    • 16.17.4 Configuration example 4
    • 16.17.5 Configuration example 5
    • 16.17.6 Configuration example 6
    • 16.17.7 Configuration example 7
    • 16.17.8 Look-up table programming guidelines
• Chapter 17: LPC176x/5x SPI
  • 17.1 Basic configuration
  • 17.2 Features
  • 17.3 SPI overview
  • 17.4 Pin description
  • 17.5 SPI data transfers
  • 17.6 SPI peripheral details
    • 17.6.1 General information
    • 17.6.2 Master operation
    • 17.6.3 Slave operation
    • 17.6.4 Exception conditions
  • 17.7 Register description
    • 17.7.1 SPI Control Register (S0SPCR - 0x4002 0000)
    • 17.7.2 SPI Status Register (S0SPSR - 0x4002 0004)
    • 17.7.3 SPI Data Register (S0SPDR - 0x4002 0008)
    • 17.7.4 SPI Clock Counter Register (S0SPCCR - 0x4002 000C)
    • 17.7.5 SPI Test Control Register (SPTCR - 0x4002 0010)
    • 17.7.6 SPI Test Status Register (SPTSR - 0x4002 0014)
    • 17.7.7 SPI Interrupt Register (S0SPINT - 0x4002 001C)
  • 17.8 Architecture
• Chapter 18: LPC176x/5x SSP0/1
  • 18.1 Basic configuration
  • 18.2 Features
  • 18.3 Description
  • 18.4 Pin descriptions
  • 18.5 Bus description
    • 18.5.1 Texas Instruments synchronous serial frame format
    • 18.5.2 SPI frame format
      • 18.5.2.1 Clock Polarity (CPOL) and Phase (CPHA) control
      • 18.5.2.2 SPI format with CPOL=0,CPHA=0
      • 18.5.2.3 SPI format with CPOL=0,CPHA=1
      • 18.5.2.4 SPI format with CPOL = 1,CPHA = 0
      • 18.5.2.5 SPI format with CPOL = 1,CPHA = 1
    • 18.5.3 National Semiconductor Microwire frame format
      • 18.5.3.1 Setup and hold time requirements on CS with respect to SK in Microwire mode
  • 18.6 Register description
    • 18.6.1 SSPn Control Register 0 (SSP0CR0 - 0x4008 8000, SSP1CR0 - 0x4003 0000)
    • 18.6.2 SSPn Control Register 1 (SSP0CR1 - 0x4008 8004, SSP1CR1 - 0x4003 0004)
    • 18.6.3 SSPn Data Register (SSP0DR - 0x4008 8008, SSP1DR - 0x4003 0008)
    • 18.6.4 SSPn Status Register (SSP0SR - 0x4008 800C, SSP1SR - 0x4003 000C)
    • 18.6.5 SSPn Clock Prescale Register (SSP0CPSR - 0x4008 8010, SSP1CPSR - 0x4003 0010)
    • 18.6.6 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0x4008 8014, SSP1IMSC - 0x4003 0014)
    • 18.6.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0x4008 8018, SSP1RIS - 0x4003 0018)
    • 18.6.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0x4008 801C, SSP1MIS - 0x4003 001C)
    • 18.6.9 SSPn Interrupt Clear Register (SSP0ICR - 0x4008 8020, SSP1ICR - 0x4003 0020)
    • 18.6.10 SSPn DMA Control Register (SSP0DMACR - 0x4008 8024, SSP1DMACR - 0x4003 0024)
• Chapter 19: LPC176x/5x I2C0/1/2
  • 19.1 Basic configuration
  • 19.2 Features
  • 19.3 Applications
  • 19.4 Description
    • 19.4.1 I2C FAST Mode Plus
  • 19.5 Pin description
  • 19.6 I2C operating modes
    • 19.6.1 Master Transmitter mode
    • 19.6.2 Master Receiver mode
    • 19.6.3 Slave Receiver mode
    • 19.6.4 Slave Transmitter mode
  • 19.7 I2C implementation and operation
    • 19.7.1 Input filters and output stages
    • 19.7.2 Address Registers, I2ADR0 to I2ADR3
    • 19.7.3 Address mask registers, I2MASK0 to I2MASK3
    • 19.7.4 Comparator
    • 19.7.5 Shift register, I2DAT
    • 19.7.6 Arbitration and synchronization logic
    • 19.7.7 Serial clock generator
    • 19.7.8 Timing and control
    • 19.7.9 Control register, I2CONSET and I2CONCLR
    • 19.7.10 Status decoder and status register
  • 19.8 Register description
    • 19.8.1 I2C Control Set register (I2CONSET: I2C0, I2C0CONSET - 0x4001 C000; I2C1, I2C1CONSET - 0x4005 C000; I2C2, I2C2CONSET - 0x400A 0000)
    • 19.8.2 I2C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR - 0x4001 C018; I2C1, I2C1CONCLR - 0x4005 C018; I2C2, I2C2CONCLR - 0x400A 0018)
    • 19.8.3 I2C Status register (I2STAT: I2C0, I2C0STAT - 0x4001 C004; I2C1, I2C1STAT - 0x4005 C004; I2C2, I2C2STAT - 0x400A 0004)
    • 19.8.4 I2C Data register (I2DAT: I2C0, I2C0DAT - 0x4001 C008; I2C1, I2C1DAT - 0x4005 C008; I2C2, I2C2DAT - 0x400A 0008)
    • 19.8.5 I2C Monitor mode control register (I2MMCTRL: I2C0, I2C0MMCTRL - 0x4001 C01C; I2C1, I2C1MMCTRL- 0x4005 C01C; I2C2, I2C2MMCTRL- 0x400A 001C)
      • 19.8.5.1 Interrupt in Monitor mode
      • 19.8.5.2 Loss of arbitration in Monitor mode
    • 19.8.6 I2C Data buffer register (I2DATA_BUFFER: I2C0, I2CDATA_BUFFER - 0x4001 C02C; I2C1, I2C1DATA_BUFFER- 0x4005 C02C; I2C2, I2C2DATA_BUFFER- 0x400A 002C)
    • 19.8.7 I2C Slave Address registers (I2ADR0 to 3: I2C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28]; I2C1, I2C1ADR[0, 1, 2, 3] - address 0x4005 C0[0C, 20, 24, 28]; I2C2, I2C2ADR[0, 1, 2, 3] - address 0x400A 00[0C, 20, 24, 28])
    • 19.8.8 I2C Mask registers (I2MASK0 to 3: I2C0, I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C]; I2C1, I2C1MASK[0, 1, 2, 3] - address 0x4005 C0[30, 34, 38, 3C]; I2C2, I2C2MASK[0, 1, 2, 3] - address 0x400A 00[30, 34, 38, 3C])
    • 19.8.9 I2C SCL HIGH duty cycle register (I2SCLH: I2C0, I2C0SCLH - 0x4001 C010; I2C1, I2C1SCLH - 0x4005 C010; I2C2, I2C2SCLH - 0x400A 0010)
    • 19.8.10 I2C SCL Low duty cycle register (I2SCLL: I2C0 - I2C0SCLL: 0x4001 C014; I2C1 - I2C1SCLL: 0x4005 C014; I2C2 - I2C2SCLL: 0x400A 0014)
    • 19.8.11 Selecting the appropriate I2C data rate and duty cycle
  • 19.9 Details of I2C operating modes
    • 19.9.1 Master Transmitter mode
    • 19.9.2 Master Receiver mode
    • 19.9.3 Slave Receiver mode
    • 19.9.4 Slave Transmitter mode
    • 19.9.5 Detailed state tables
    • 19.9.6 Miscellaneous states
      • 19.9.6.1 I2STAT = 0xF8
      • 19.9.6.2 I2STAT = 0x00
    • 19.9.7 Some special cases
      • 19.9.7.1 Simultaneous repeated START conditions from two masters
      • 19.9.7.2 Data transfer after loss of arbitration
      • 19.9.7.3 Forced access to the I2C-bus
      • 19.9.7.4 I2C-bus obstructed by a LOW level on SCL or SDA
      • 19.9.7.5 Bus error
    • 19.9.8 I2C state service routines
      • 19.9.8.1 Initialization
      • 19.9.8.2 I2C interrupt service
      • 19.9.8.3 The state service routines
      • 19.9.8.4 Adapting state services to an application
  • 19.10 Software example
    • 19.10.1 Initialization routine
    • 19.10.2 Start Master Transmit function
    • 19.10.3 Start Master Receive function
    • 19.10.4 I2C interrupt routine
    • 19.10.5 Non mode specific states
      • 19.10.5.1 State: 0x00
      • 19.10.5.2 Master States
      • 19.10.5.3 State: 0x08
      • 19.10.5.4 State: 0x10
    • 19.10.6 Master Transmitter states
      • 19.10.6.1 State: 0x18
      • 19.10.6.2 State: 0x20
      • 19.10.6.3 State: 0x28
      • 19.10.6.4 State: 0x30
      • 19.10.6.5 State: 0x38
    • 19.10.7 Master Receive states
      • 19.10.7.1 State: 0x40
      • 19.10.7.2 State: 0x48
      • 19.10.7.3 State: 0x50
      • 19.10.7.4 State: 0x58
    • 19.10.8 Slave Receiver states
      • 19.10.8.1 State: 0x60
      • 19.10.8.2 State: 0x68
      • 19.10.8.3 State: 0x70
      • 19.10.8.4 State: 0x78
      • 19.10.8.5 State: 0x80
      • 19.10.8.6 State: 0x88
      • 19.10.8.7 State: 0x90
      • 19.10.8.8 State: 0x98
      • 19.10.8.9 State: 0xA0
    • 19.10.9 Slave Transmitter states
      • 19.10.9.1 State: 0xA8
      • 19.10.9.2 State: 0xB0
      • 19.10.9.3 State: 0xB8
      • 19.10.9.4 State: 0xC0
      • 19.10.9.5 State: 0xC8
• Chapter 20: LPC176x/5x I2S
  • 20.1 Basic configuration
  • 20.2 Features
  • 20.3 Description
  • 20.4 Pin descriptions
  • 20.5 Register description
    • 20.5.1 Digital Audio Output register (I2SDAO - 0x400A 8000)
    • 20.5.2 Digital Audio Input register (I2SDAI - 0x400A 8004)
    • 20.5.3 Transmit FIFO register (I2STXFIFO - 0x400A 8008)
    • 20.5.4 Receive FIFO register (I2SRXFIFO - 0x400A 800C)
    • 20.5.5 Status Feedback register (I2SSTATE - 0x400A 8010)
    • 20.5.6 DMA Configuration Register 1 (I2SDMA1 - 0x400A 8014)
    • 20.5.7 DMA Configuration Register 2 (I2SDMA2 - 0x400A 8018)
    • 20.5.8 Interrupt Request Control register (I2SIRQ - 0x400A 801C)
    • 20.5.9 Transmit Clock Rate register (I2STXRATE - 0x400A 8020)
      • 20.5.9.1 Notes on fractional rate generators
    • 20.5.10 Receive Clock Rate register (I2SRXRATE - 0x400A 8024)
    • 20.5.11 Transmit Clock Bit Rate register (I2STXBITRATE - 0x400A 8028)
    • 20.5.12 Receive Clock Bit Rate register (I2SRXBITRATE - 0x400A 802C)
    • 20.5.13 Transmit Mode Control register (I2STXMODE - 0x400A 8030)
    • 20.5.14 Receive Mode Control register (I2SRXMODE - 0x400A 8034)
  • 20.6 I2S transmit and receive interfaces
  • 20.7 I2S operating modes
  • 20.8 FIFO controller
• Chapter 21: LPC176x/5x Timer 0/1/2/3
  • 21.1 Basic configuration
  • 21.2 Features
  • 21.3 Applications
  • 21.4 Description
  • 21.5 Pin description
    • 21.5.1 Multiple CAP and MAT pins
  • 21.6 Register description
    • 21.6.1 Interrupt Register (T[0/1/2/3]IR - 0x4000 4000, 0x4000 8000, 0x4009 0000, 0x4009 4000)
    • 21.6.2 Timer Control Register (T[0/1/2/3]CR - 0x4000 4004, 0x4000 8004, 0x4009 0004, 0x4009 4004)
    • 21.6.3 Count Control Register (T[0/1/2/3]CTCR - 0x4000 4070, 0x4000 8070, 0x4009 0070, 0x4009 4070)
    • 21.6.4 Timer Counter registers (T0TC - T3TC, 0x4000 4008, 0x4000 8008, 0x4009 0008, 0x4009 4008)
    • 21.6.5 Prescale register (T0PR - T3PR, 0x4000 400C, 0x4000 800C, 0x4009 000C, 0x4009 400C)
    • 21.6.6 Prescale Counter register (T0PC - T3PC, 0x4000 4010, 0x4000 8010, 0x4009 0010, 0x4009 4010)
    • 21.6.7 Match Registers (MR0 - MR3)
    • 21.6.8 Match Control Register (T[0/1/2/3]MCR - 0x4000 4014, 0x4000 8014, 0x4009 0014, 0x4009 4014)
    • 21.6.9 Capture Registers (CR0 - CR1)
    • 21.6.10 Capture Control Register (T[0/1/2/3]CCR - 0x4000 4028, 0x4000 8028, 0x4009 0028, 0x4009 4028)
    • 21.6.11 External Match Register (T[0/1/2/3]EMR - 0x4000 403C, 0x4000 803C, 0x4009 003C, 0x4009 403C)
    • 21.6.12 DMA operation
  • 21.7 Example timer operation
  • 21.8 Architecture
• Chapter 22: LPC176x/5x Repetitive Interrupt Timer (RIT)
  • 22.1 Features
  • 22.2 Description
  • 22.3 Register description
    • 22.3.1 RI Compare Value register (RICOMPVAL - 0x400B 0000)
    • 22.3.2 RI Mask register (RIMASK - 0x400B 0004)
    • 22.3.3 RI Control register (RICTRL - 0x400B 0008)
    • 22.3.4 RI Counter register (RICOUNTER - 0x400B 000C)
  • 22.4 RI timer operation
• Chapter 23: LPC176x/5x System Tick Timer
  • 23.1 Basic configuration
  • 23.2 Features
  • 23.3 Description
  • 23.4 Operation
  • 23.5 Register description
    • 23.5.1 System Timer Control and status register (STCTRL - 0xE000 E010)
    • 23.5.2 System Timer Reload value register (STRELOAD - 0xE000 E014)
    • 23.5.3 System Timer Current value register (STCURR - 0xE000 E018)
    • 23.5.4 System Timer Calibration value register (STCALIB - 0xE000 E01C)
  • 23.6 Example timer calculations
  • Example 1)
  • Example 2)
  • Example 3)
  • Example 4)
• Chapter 24: LPC176x/5x Pulse Width Modulator (PWM)
  • 24.1 Basic configuration
  • 24.2 Features
  • 24.3 Description
  • 24.4 Sample waveform with rules for single and double edge control
    • 24.4.1 Rules for Single Edge Controlled PWM Outputs
    • 24.4.2 Rules for Double Edge Controlled PWM Outputs
  • 24.5 Pin description
  • 24.6 Register description
    • 24.6.1 PWM Interrupt Register (PWM1IR - 0x4001 8000)
    • 24.6.2 PWM Timer Control Register (PWM1TCR 0x4001 8004)
    • 24.6.3 PWM Count Control Register (PWM1CTCR - 0x4001 8070)
    • 24.6.4 PWM Match Control Register (PWM1MCR - 0x4001 8014)
    • 24.6.5 PWM Capture Control Register (PWM1CCR - 0x4001 8028)
    • 24.6.6 PWM Control Register (PWM1PCR - 0x4001 804C)
    • 24.6.7 PWM Latch Enable Register (PWM1LER - 0x4001 8050)
• Chapter 25: LPC176x/5x Motor control PWM
  • 25.1 Introduction
  • 25.2 Description
  • 25.3 Pin description
  • 25.4 Block Diagram
  • 25.5 Configuring other modules for MCPWM use
  • 25.6 General Operation
  • 25.7 Register description
    • 25.7.1 MCPWM Control register
      • 25.7.1.1 MCPWM Control read address (MCCON - 0x400B 8000)
      • 25.7.1.2 MCPWM Control set address (MCCON_SET - 0x400B 8004)
      • 25.7.1.3 MCPWM Control clear address (MCCON_CLR - 0x400B 8008)
    • 25.7.2 MCPWM Capture Control register
      • 25.7.2.1 MCPWM Capture Control read address (MCCAPCON - 0x400B 800C)
      • 25.7.2.2 MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010)
      • 25.7.2.3 MCPWM Capture control clear address (MCCAPCON_CLR - 0x400B 8014)
    • 25.7.3 MCPWM Interrupt registers
      • 7.3.1 MCPWM Interrupt Enable read address (MCINTEN - 0x400B 8050)
      • 25.7.3.2 MCPWM Interrupt Enable set address (MCINTEN_SET - 0x400B 8054)
      • 25.7.3.3 MCPWM Interrupt Enable clear address (MCINTEN_CLR - 0x400B 8058)
      • 25.7.3.4 MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068)
      • 25.7.3.5 MCPWM Interrupt Flags set address (MCINTF_SET - 0x400B 806C)
      • 25.7.3.6 MCPWM Interrupt Flags clear address (MCINTF_CLR - 0x400B 8070)
    • 25.7.4 MCPWM Count Control register
      • 25.7.4.1 MCPWM Count Control read address (MCCNTCON - 0x400B 805C)
      • 25.7.4.2 MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060)
      • 25.7.4.3 MCPWM Count Control clear address (MCCNTCON_CLR - 0x400B 8064)
    • 25.7.5 MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018, 0x400B 801C, 0x400B 8020)
    • 25.7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028, 0x400B 802C)
      • 25.7.6.1 Match and Limit write and operating registers
    • 25.7.7 MCPWM Match 0-2 registers (MCMAT0-2 - 0x400B 8030, 0x400B 8034, 0x400B 8038)
      • 25.7.7.1 Match register in Edge-Aligned mode
      • 25.7.7.2 Match register in Center-Aligned mode
      • 25.7.7.3 0 and 100% duty cycle
    • 25.7.8 MCPWM Dead-time register (MCDT - 0x400B 803C)
    • 25.7.9 MCPWM Commutation Pattern register (MCCP - 0x400B 8040)
    • 25.7.10 MCPWM Capture Registers
      • 25.7.10.1 MCPWM Capture read addresses (MCCAP0-2 - 0x400B 8044, 0x400B 8048, 0x400B 804C)
      • 25.7.10.2 MCPWM Capture clear address (MCCAP_CLR - 0x400B 8074)
  • 25.8 PWM operation
    • 25.8.1 Pulse-width modulation
  • Edge-aligned PWM without dead-time
  • Center-aligned PWM without dead-time
  • Dead-time counter
    • 25.8.2 Shadow registers and simultaneous updates
    • 25.8.3 Fast Abort (ABORT)
    • 25.8.4 Capture events
    • 25.8.5 External event counting (Counter mode)
    • 25.8.6 Three-phase DC mode
    • 25.8.7 Three phase AC mode
    • 25.8.8 Interrupts
• Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI)
  • 26.1 Basic configuration
  • 26.2 Features
  • 26.3 Introduction
  • 26.4 Functional description
    • 26.4.1 Input signals
      • 26.4.1.1 Quadrature input signals
      • 26.4.1.2 Digital input filtering
    • 26.4.2 Position capture
    • 26.4.3 Velocity capture
    • 26.4.4 Velocity compare
  • 26.5 Pin description
  • 26.6 Register description
    • 26.6.1 Register summary
    • 26.6.2 Control registers
      • 26.6.2.1 QEI Control register (QEICON - 0x400B C000)
      • 26.6.2.2 QEI Configuration register (QEICONF - 0x400B C008)
      • 26.6.2.3 QEI Status register (QEISTAT - 0x400B C004)
    • 26.6.3 Position, index and timer registers
      • 26.6.3.1 QEI Position register (QEIPOS - 0x400B C00C)
      • 26.6.3.2 QEI Maximum Position register (QEIMAXPOS - 0x400B C010)
      • 26.6.3.3 QEI Position Compare register 0 (CMPOS0 - 0x400B C014)
      • 26.6.3.4 QEI Position Compare register 1 (CMPOS1 - 0x400B C018)
      • 26.6.3.5 QEI Position Compare register 2 (CMPOS2 - 0x400B C01C)
      • 26.6.3.6 QEI Index Count register (INXCNT - 0x400B C020)
      • 26.6.3.7 QEI Index Compare register (INXCMP - 0x400B C024)
      • 26.6.3.8 QEI Timer Reload register (QEILOAD - 0x400B C028)
      • 26.6.3.9 QEI Timer register (QEITIME - 0x400B C02C)
      • 26.6.3.10 QEI Velocity register (QEIVEL - 0x400B C030)
      • 26.6.3.11 QEI Velocity Capture register (QEICAP - 0x400B C034)
      • 26.6.3.12 QEI Velocity Compare register (VELCOMP - 0x400B C038)
      • 26.6.3.13 QEI Digital Filter register (FILTER - 0x400B C03C)
    • 26.6.4 Interrupt registers
      • 26.6.4.1 QEI Interrupt Status register (QEIINTSTAT)
      • 26.6.4.2 QEI Interrupt Set register (QEISET - 0x400B CFEC)
      • 26.6.4.3 QEI Interrupt Clear register (QEICLR - 0x400B CFE8)
      • 26.6.4.4 QEI Interrupt Enable register (QEIIE - 0x400B CFE4)
      • 26.6.4.5 QEI Interrupt Enable Set register (QEIIES - 0x400B CFDC)
      • 26.6.4.6 QEI Interrupt Enable Clear register (QEIIEC - 0x400B CFD8)
• Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers
  • 27.1 Basic configuration
  • 27.2 Features
  • 27.3 Description
  • 27.4 Architecture
  • 27.5 Pin description
  • 27.6 Register description
    • 27.6.1 RTC interrupts
    • 27.6.2 Miscellaneous register group
      • 27.6.2.1 Interrupt Location Register (ILR - 0x4002 4000)
      • 27.6.2.2 Clock Control Register (CCR - 0x4002 4008)
      • 27.6.2.3 Counter Increment Interrupt Register (CIIR - 0x4002 400C)
      • 27.6.2.4 Alarm Mask Register (AMR - 0x4002 4010)
      • 27.6.2.5 RTC Auxiliary control register (RTC_AUX - 0x4002 405C)
      • 27.6.2.6 RTC Auxiliary Enable register (RTC_AUXEN - 0x4002 4058)
    • 27.6.3 Consolidated time registers
      • 27.6.3.1 Consolidated Time Register 0 (CTIME0 - 0x4002 4014)
      • 27.6.3.2 Consolidated Time Register 1 (CTIME1 - 0x4002 4018)
      • 27.6.3.3 Consolidated Time Register 2 (CTIME2 - 0x4002 401C)
    • 27.6.4 Time Counter Group
      • 27.6.4.1 Leap year calculation
      • 27.6.4.2 Calibration register (CALIBRATION - address 0x4002 4040)
    • 27.6.5 Calibration procedure
  • Backward calibration
  • Forward calibration
    • 27.6.6 General purpose registers
      • 27.6.6.1 General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses 0x4002 4044 to 0x4002 4054)
    • 27.6.7 Alarm register group
  • 27.7 RTC usage notes
• Chapter 28: LPC176x/5x Watchdog Timer (WDT)
  • 28.1 Features
  • 28.2 Applications
  • 28.3 Description
  • 28.4 Register description
    • 28.4.1 Watchdog Mode register (WDMOD - 0x4000 0000)
    • 28.4.2 Watchdog Timer Constant register (WDTC - 0x4000 0004)
    • 28.4.3 Watchdog Feed register (WDFEED - 0x4000 0008)
    • 28.4.4 Watchdog Timer Value register (WDTV - 0x4000 000C)
    • 28.4.5 Watchdog Timer Clock Source Selection register (WDCLKSEL - 0x4000 0010)
  • 28.5 Block diagram
• Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC)
  • 29.1 Basic configuration
  • 29.2 Features
  • 29.3 Description
  • 29.4 Pin description
  • 29.5 Register description
    • 29.5.1 A/D Control Register (AD0CR - 0x4003 4000)
    • 29.5.2 A/D Global Data Register (AD0GDR - 0x4003 4004)
    • 29.5.3 A/D Interrupt Enable register (AD0INTEN - 0x4003 400C)
    • 29.5.4 A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to 0x4003 402C)
    • 29.5.5 A/D Status register (ADSTAT - 0x4003 4030)
    • 29.5.6 A/D Trim register (ADTRIM - 0x4003 4034)
  • 29.6 Operation
    • 29.6.1 Hardware-triggered conversion
    • 29.6.2 Interrupts
    • 29.6.3 Accuracy vs. digital receiver
    • 29.6.4 DMA control
• Chapter 30: LPC176x/5x Digital-to-Analog Converter (DAC)
  • 30.1 Basic configuration
  • 30.2 Features
  • 30.3 Pin description
  • 30.4 Register description
    • 30.4.1 D/A Converter Register (DACR - 0x4008 C000)
    • 30.4.2 D/A Converter Control register (DACCTRL - 0x4008 C004)
    • 30.4.3 D/A Converter Counter Value register (DACCNTVAL - 0x4008 C008)
  • 30.5 Operation
    • 30.5.1 DMA counter
    • 30.5.2 Double buffering
• Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
  • 31.1 Basic configuration
  • 31.2 Introduction
  • 31.3 Features
  • 31.4 Functional description
    • 31.4.1 DMA controller functional description
      • 31.4.1.1 AHB slave interface
      • 31.4.1.2 Control logic and register bank
      • 31.4.1.3 DMA request and response interface
      • 31.4.1.4 Channel logic and channel register bank
      • 31.4.1.5 Interrupt request
      • 31.4.1.6 AHB master interface
        • 31.4.1.6.1 Bus and transfer widths
        • 31.4.1.6.2 Endian behavior
        • 31.4.1.6.3 Error conditions
      • 31.4.1.7 Channel hardware
      • 31.4.1.8 DMA request priority
      • 31.4.1.9 Interrupt generation
    • 31.4.2 DMA system connections
      • 31.4.2.1 DMA request signals
      • 31.4.2.2 DMA response signals
      • 31.4.2.3 DMA request connections
  • 31.5 Register description
    • 31.5.1 DMA Interrupt Status register (DMACIntStat - 0x5000 4000)
    • 31.5.2 DMA Interrupt Terminal Count Request Status register (DMACIntTCStat - 0x5000 4004)
    • 31.5.3 DMA Interrupt Terminal Count Request Clear register (DMACIntTCClear - 0x5000 4008)
    • 31.5.4 DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C)
    • 31.5.5 DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010)
    • 31.5.6 DMA Raw Interrupt Terminal Count Status register (DMACRawIntTCStat - 0x5000 4014)
    • 31.5.7 DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018)
    • 31.5.8 DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C)
    • 31.5.9 DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)
    • 31.5.10 DMA Software Single Request register (DMACSoftSReq - 0x5000 4024)
    • 31.5.11 DMA Software Last Burst Request register (DMACSoftLBReq - 0x5000 4028)
    • 31.5.12 DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C)
    • 31.5.13 DMA Configuration register (DMACConfig - 0x5000 4030)
    • 31.5.14 DMA Synchronization register (DMACSync - 0x5000 4034)
    • 31.5.15 DMA Request Select register (DMAReqSel - 0x400F C1C4)
    • 31.5.16 DMA Channel registers
    • 31.5.17 DMA Channel Source Address registers (DMACCxSrcAddr - 0x5000 41x0)
    • 31.5.18 DMA Channel Destination Address registers (DMACCxDestAddr - 0x5000 41x4)
    • 31.5.19 DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8)
    • 31.5.20 DMA channel control registers (DMACCxControl - 0x5000 41xC)
      • 31.5.20.1 Protection and access information
    • 31.5.21 DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0)
      • 31.5.21.1 Lock control
      • 31.5.21.2 Transfer type
  • 31.6 Using the DMA controller
    • 31.6.1 Programming the DMA controller
      • 31.6.1.1 Enabling the DMA controller
      • 31.6.1.2 Disabling the DMA controller
      • 31.6.1.3 Enabling a DMA channel
      • 31.6.1.4 Disabling a DMA channel
  • Disabling a DMA channel and losing data in the FIFO
  • Disabling the DMA channel without losing data in the FIFO
    • 31.6.1.5 Setting up a new DMA transfer
    • 31.6.1.6 Halting a DMA channel
    • 31.6.1.7 Programming a DMA channel
    • 31.6.2 Flow control
      • 31.6.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow
      • 31.6.2.2 Peripheral-to-peripheral DMA flow
      • 31.6.2.3 Memory-to-memory DMA flow
    • 31.6.3 Interrupt requests
      • 31.6.3.1 Hardware interrupt sequence flow
    • 31.6.4 Address generation
      • 31.6.4.1 Word-aligned transfers across a boundary
    • 31.6.5 Scatter/gather
      • 31.6.5.1 Linked list items
        • 31.6.5.1.1 Programming the DMA controller for scatter/gather DMA
        • 31.6.5.1.2 Example of scatter/gather DMA
• Chapter 32: LPC176x/5x Flash memory interface and programming
  • 32.1 Introduction
  • 32.2 Features
  • 32.3 Description
    • 32.3.1 Memory map after any reset
      • 32.3.1.1 Criterion for Valid User Code
    • 32.3.2 Communication protocol
      • 32.3.2.1 ISP command format
      • 32.3.2.2 ISP response format
      • 32.3.2.3 ISP data format
      • 32.3.2.4 ISP flow control
      • 32.3.2.5 ISP command abort
      • 32.3.2.6 Interrupts during IAP
      • 32.3.2.7 RAM used by ISP command handler
      • 32.3.2.8 RAM used by IAP command handler
  • 32.4 Boot process flowchart
  • 32.5 Sector numbers
  • 32.6 Code Read Protection (CRP)
  • 32.7 ISP commands
    • 32.7.1 Unlock <Unlock code>
    • 32.7.2 Set Baud Rate <Baud Rate> <stop bit>
    • 32.7.3 Echo <setting>
    • 32.7.4 Write to RAM <start address> <number of bytes>
    • 32.7.5 Read Memory <address> <no. of bytes>
    • 32.7.6 Prepare sector(s) for write operation <start sector number> <end sector number>
    • 32.7.7 Copy RAM to Flash <flash address> <RAM address> <no of bytes>
    • 32.7.8 Go <address> <mode>
    • 32.7.9 Erase sector(s) <start sector number> <end sector number>
    • 32.7.10 Blank check sector(s) <sector number> <end sector number>
    • 32.7.11 Read Part Identification number
    • 32.7.12 Read Boot Code version number
    • 32.7.13 Read device serial number
    • 32.7.14 Compare <address1> <address2> <no of bytes>
    • 32.7.15 ISP Return Codes
  • 32.8 IAP commands
    • 32.8.1 Prepare sector(s) for write operation
    • 32.8.2 Copy RAM to Flash
    • 32.8.3 Erase Sector(s)
    • 32.8.4 Blank check sector(s)
    • 32.8.5 Read part identification number
    • 32.8.6 Read Boot Code version number
    • 32.8.7 Read device serial number
    • 32.8.8 Compare <address1> <address2> <no of bytes>
    • 32.8.9 Re-invoke ISP
    • 32.8.10 IAP Status Codes
  • 32.9 JTAG flash programming interface
  • 32.10 Flash signature generation
    • 32.10.1 Register description for signature generation
      • 32.10.1.1 Signature generation address and control registers
      • 32.10.1.2 Signature generation result registers
      • 32.10.1.3 Flash Module Status register (FMSTAT - 0x0x4008 4FE0)
      • 32.10.1.4 Flash Module Status Clear register (FMSTATCLR - 0x0x4008 4FE8)
    • 32.10.2 Algorithm and procedure for signature generation
  • Signature generation
  • Content verification
• Chapter 33: LPC176x/5x JTAG, Serial Wire Debug (SWD), and Trace
  • 33.1 Features
  • 33.2 Introduction
  • 33.3 Description
  • 33.4 Pin Description
  • 33.5 Debug Notes
  • 33.6 Debug memory re-mapping
    • 33.6.1 Memory Mapping Control register (MEMMAP - 0x400F C040)
  • 33.7 JTAG TAP Identification
• Chapter 34: Appendix: Cortex-M3 user guide
  • 34.1 ARM Cortex-M3 User Guide: Introduction
    • 34.1.1 About the processor and core peripherals
      • 34.1.1.1 System level interface
      • 34.1.1.2 Integrated configurable debug
      • 34.1.1.3 Cortex-M3 processor features and benefits summary
      • 34.1.1.4 Cortex-M3 core peripherals
  • 34.2 ARM Cortex-M3 User Guide: Instruction Set
    • 34.2.1 Instruction set summary
  • Note
    • 34.2.2 Intrinsic functions
    • 34.2.3 About the instruction descriptions
      • 34.2.3.1 Operands
      • 34.2.3.2 Restrictions when using PC or SP
      • 34.2.3.3 Flexible second operand
        • 34.2.3.3.1 Constant
        • 34.2.3.3.2 Register with optional shift
      • 34.2.3.4 Shift Operations
        • 34.2.3.4.1 ASR
  • Note
    • 34.2.3.4.2 LSR
  • Note
    • 34.2.3.4.3 LSL
  • Note
    • 34.2.3.4.4 ROR
  • Note
    • 34.2.3.4.5 RRX
    • 34.2.3.5 Address alignment
    • 34.2.3.6 PC-relative expressions
  • Note
    • 34.2.3.7 Conditional execution
      • 34.2.3.7.1 The condition flags
      • 34.2.3.7.2 Condition code suffixes
    • 34.2.3.8 Instruction width selection
      • 34.2.3.8.1 Example: Instruction width selection
    • 34.2.4 Memory access instructions
      • 34.2.4.1 ADR
        • 34.2.4.1.1 Syntax
        • 34.2.4.1.2 Operation
        • 34.2.4.1.3 Restrictions
        • 34.2.4.1.4 Condition flags
        • 34.2.4.1.5 Examples
      • 34.2.4.2 LDR and STR, immediate offset
        • 34.2.4.2.1 Syntax
        • 34.2.4.2.2 Operation
        • 34.2.4.2.3 Restrictions
        • 34.2.4.2.4 Condition flags
        • 34.2.4.2.5 Examples
      • 34.2.4.3 LDR and STR, register offset
        • 34.2.4.3.1 Syntax
        • 34.2.4.3.2 Operation
        • 34.2.4.3.3 Restrictions
        • 34.2.4.3.4 Condition flags
        • 34.2.4.3.5 Examples
      • 34.2.4.4 LDR and STR, unprivileged
        • 34.2.4.4.1 Syntax
        • 34.2.4.4.2 Operation
        • 34.2.4.4.3 Restrictions
        • 34.2.4.4.4 Condition flags
        • 34.2.4.4.5 Examples
      • 34.2.4.5 LDR, PC-relative
        • 34.2.4.5.1 Syntax
        • 34.2.4.5.2 Operation
        • 34.2.4.5.3 Restrictions
        • 34.2.4.5.4 Condition flags
        • 34.2.4.5.5 Examples
      • 34.2.4.6 LDM and STM
        • 34.2.4.6.1 Syntax
        • 34.2.4.6.2 Operation
        • 34.2.4.6.3 Restrictions
        • 34.2.4.6.4 Condition flags
        • 34.2.4.6.5 Examples
        • 34.2.4.6.6 Incorrect examples
      • 34.2.4.7 PUSH and POP
        • 34.2.4.7.1 Syntax
        • 34.2.4.7.2 Operation
        • 34.2.4.7.3 Restrictions
        • 34.2.4.7.4 Condition flags
        • 34.2.4.7.5 Examples
      • 34.2.4.8 LDREX and STREX
        • 34.2.4.8.1 Syntax
        • 34.2.4.8.2 Operation
        • 34.2.4.8.3 Restrictions
        • 34.2.4.8.4 Condition flags
        • 34.2.4.8.5 Examples
      • 34.2.4.9 CLREX
        • 34.2.4.9.1 Syntax
        • 34.2.4.9.2 Operation
        • 34.2.4.9.3 Condition flags
        • 34.2.4.9.4 Examples
    • 34.2.5 General data processing instructions
      • 34.2.5.1 ADD, ADC, SUB, SBC, and RSB
        • 34.2.5.1.1 Syntax
        • 34.2.5.1.2 Operation
        • 34.2.5.1.3 Restrictions
  • Note
    • 34.2.5.1.4 Condition flags
    • 34.2.5.1.5 Examples
    • 34.2.5.1.6 Multiword arithmetic examples
    • 34.2.5.2 AND, ORR, EOR, BIC, and ORN
      • 34.2.5.2.1 Syntax
      • 34.2.5.2.2 Operation
      • 34.2.5.2.3 Restrictions
      • 34.2.5.2.4 Condition flags
      • 34.2.5.2.5 Examples
    • 34.2.5.3 ASR, LSL, LSR, ROR, and RRX
      • 34.2.5.3.1 Syntax
      • 34.2.5.3.2 Operation
      • 34.2.5.3.3 Restrictions
      • 34.2.5.3.4 Condition flags
      • 34.2.5.3.5 Examples
    • 34.2.5.4 CLZ
      • 34.2.5.4.1 Syntax
      • 34.2.5.4.2 Operation
      • 34.2.5.4.3 Restrictions
      • 34.2.5.4.4 Condition flags
      • 34.2.5.4.5 Examples
    • 34.2.5.5 CMP and CMN
      • 34.2.5.5.1 Syntax
      • 34.2.5.5.2 Operation
      • 34.2.5.5.3 Restrictions
      • 34.2.5.5.4 Condition flags
      • 34.2.5.5.5 Examples
    • 34.2.5.6 MOV and MVN
      • 34.2.5.6.1 Syntax
      • 34.2.5.6.2 Operation
      • 34.2.5.6.3 Restrictions
      • 34.2.5.6.4 Condition flags
      • 34.2.5.6.5 Example
    • 34.2.5.7 MOVT
      • 34.2.5.7.1 Syntax
      • 34.2.5.7.2 Operation
      • 34.2.5.7.3 Restrictions
      • 34.2.5.7.4 Condition flags
      • 34.2.5.7.5 Examples
    • 34.2.5.8 REV, REV16, REVSH, and RBIT
      • 34.2.5.8.1 Syntax
      • 34.2.5.8.2 Operation
      • 34.2.5.8.3 Restrictions
      • 34.2.5.8.4 Condition flags
      • 34.2.5.8.5 Examples
    • 34.2.5.9 TST and TEQ
      • 34.2.5.9.1 Syntax
      • 34.2.5.9.2 Operation
      • 34.2.5.9.3 Restrictions
      • 34.2.5.9.4 Condition flags
      • 34.2.5.9.5 Examples
    • 34.2.6 Multiply and divide instructions
      • 34.2.6.1 MUL, MLA, and MLS
        • 34.2.6.1.1 Syntax
        • 34.2.6.1.2 Operation
        • 34.2.6.1.3 Restrictions
        • 34.2.6.1.4 Condition flags
        • 34.2.6.1.5 Examples
      • 34.2.6.2 UMULL, UMLAL, SMULL, and SMLAL
        • 34.2.6.2.1 Syntax
        • 34.2.6.2.2 Operation
        • 34.2.6.2.3 Restrictions
        • 34.2.6.2.4 Condition flags
        • 34.2.6.2.5 Examples
      • 34.2.6.3 SDIV and UDIV
        • 34.2.6.3.1 Syntax
        • 34.2.6.3.2 Operation
        • 34.2.6.3.3 Restrictions
        • 34.2.6.3.4 Condition flags
        • 34.2.6.3.5 Examples
    • 34.2.7 Saturating instructions
      • 34.2.7.1 SSAT and USAT
        • 34.2.7.1.1 Syntax
        • 34.2.7.1.2 Operation
        • 34.2.7.1.3 Restrictions
        • 34.2.7.1.4 Condition flags
        • 34.2.7.1.5 Examples
    • 34.2.8 Bitfield instructions
      • 34.2.8.1 BFC and BFI
        • 34.2.8.1.1 Syntax
        • 34.2.8.1.2 Operation
        • 34.2.8.1.3 Restrictions
        • 34.2.8.1.4 Condition flags
        • 34.2.8.1.5 Examples
      • 34.2.8.2 SBFX and UBFX
        • 34.2.8.2.1 Syntax
        • 34.2.8.2.2 Operation
        • 34.2.8.2.3 Restrictions
        • 34.2.8.2.4 Condition flags
        • 34.2.8.2.5 Examples
      • 34.2.8.3 SXT and UXT
        • 34.2.8.3.1 Syntax
        • 34.2.8.3.2 Operation
        • 34.2.8.3.3 Restrictions
        • 34.2.8.3.4 Condition flags
        • 34.2.8.3.5 Examples
    • 34.2.9 Branch and control instructions
      • 34.2.9.1 B, BL, BX, and BLX
        • 34.2.9.1.1 Syntax
        • 34.2.9.1.2 Operation
        • 34.2.9.1.3 Restrictions
        • 34.2.9.1.4 Condition flags
        • 34.2.9.1.5 Examples
      • 34.2.9.2 CBZ and CBNZ
        • 34.2.9.2.1 Syntax
        • 34.2.9.2.2 Operation
        • 34.2.9.2.3 Restrictions
        • 34.2.9.2.4 Condition flags
        • 34.2.9.2.5 Examples
      • 34.2.9.3 IT
        • 34.2.9.3.1 Syntax
        • 34.2.9.3.2 Operation
        • 34.2.9.3.3 Restrictions
        • 34.2.9.3.4 Condition flags
        • 34.2.9.3.5 Example
      • 34.2.9.4 TBB and TBH
        • 34.2.9.4.1 Syntax
        • 34.2.9.4.2 Operation
        • 34.2.9.4.3 Restrictions
        • 34.2.9.4.4 Condition flags
        • 34.2.9.4.5 Examples
    • 34.2.10 Miscellaneous instructions
      • 34.2.10.1 BKPT
        • 34.2.10.1.1 Syntax
        • 34.2.10.1.2 Operation
        • 34.2.10.1.3 Condition flags
        • 34.2.10.1.4 Examples
      • 34.2.10.2 CPS
        • 34.2.10.2.1 Syntax
        • 34.2.10.2.2 Operation
        • 34.2.10.2.3 Restrictions
        • 34.2.10.2.4 Condition flags
        • 34.2.10.2.5 Examples
      • 34.2.10.3 DMB
        • 34.2.10.3.1 Syntax
        • 34.2.10.3.2 Operation
        • 34.2.10.3.3 Condition flags
        • 34.2.10.3.4 Examples
      • 34.2.10.4 DSB
        • 34.2.10.4.1 Syntax
        • 34.2.10.4.2 Operation
        • 34.2.10.4.3 Condition flags
        • 34.2.10.4.4 Examples
      • 34.2.10.5 ISB
        • 34.2.10.5.1 Syntax
        • 34.2.10.5.2 Operation
        • 34.2.10.5.3 Condition flags
        • 34.2.10.5.4 Examples
      • 34.2.10.6 MRS
        • 34.2.10.6.1 Syntax
        • 34.2.10.6.2 Operation
        • 34.2.10.6.3 Restrictions
        • 34.2.10.6.4 Condition flags
        • 34.2.10.6.5 Examples
      • 34.2.10.7 MSR
        • 34.2.10.7.1 Syntax
        • 34.2.10.7.2 Operation
  • Note
    • 34.2.10.7.3 Restrictions
    • 34.2.10.7.4 Condition flags
    • 34.2.10.7.5 Examples
    • 34.2.10.8 NOP
      • 34.2.10.8.1 Syntax
      • 34.2.10.8.2 Operation
      • 34.2.10.8.3 Condition flags
      • 34.2.10.8.4 Examples
    • 34.2.10.9 SEV
      • 34.2.10.9.1 Syntax
      • 34.2.10.9.2 Operation
      • 34.2.10.9.3 Condition flags
      • 34.2.10.9.4 Examples
    • 34.2.10.10 SVC
      • 34.2.10.10.1 Syntax
      • 34.2.10.10.2 Operation
      • 34.2.10.10.3 Condition flags
      • 34.2.10.10.4 Examples
    • 34.2.10.11 WFE
      • 34.2.10.11.1 Syntax
      • 34.2.10.11.2 Operation
      • 34.2.10.11.3 Condition flags
      • 34.2.10.11.4 Examples
    • 34.2.10.12 WFI
      • 34.2.10.12.1 Syntax
      • 34.2.10.12.2 Operation
      • 34.2.10.12.3 Condition flags
      • 34.2.10.12.4 Examples
  • 34.3 ARM Cortex-M3 User Guide: Processor
    • 34.3.1 Programmers model
      • 34.3.1.1 Processor mode and privilege levels for software execution
      • 34.3.1.2 Stacks
      • 34.3.1.3 Core registers
        • 34.3.1.3.1 General-purpose registers
        • 34.3.1.3.2 Stack Pointer
        • 34.3.1.3.3 Link Register
        • 34.3.1.3.4 Program Counter
        • 34.3.1.3.5 Program Status Register
        • 34.3.1.3.6 Exception mask registers
        • 34.3.1.3.7 CONTROL register
      • 34.3.1.4 Exceptions and interrupts
      • 34.3.1.5 Data types
      • 34.3.1.6 The Cortex Microcontroller Software Interface Standard
    • 34.3.2 Memory model
      • 34.3.2.1 Memory regions, types and attributes
      • 34.3.2.2 Memory system ordering of memory accesses
      • 34.3.2.3 Behavior of memory accesses
      • 34.3.2.4 Software ordering of memory accesses
      • 34.3.2.5 Bit-banding
        • 34.3.2.5.1 Directly accessing an alias region
        • 34.3.2.5.2 Directly accessing a bit-band region
      • 34.3.2.6 Memory endianness
        • 34.3.2.6.1 Little-endian format
      • 34.3.2.7 Synchronization primitives
      • 34.3.2.8 Programming hints for the synchronization primitives
    • 34.3.3 Exception model
      • 34.3.3.1 Exception states
      • 34.3.3.2 Exception types
      • 34.3.3.3 Exception handlers
      • 34.3.3.4 Vector table
      • 34.3.3.5 Exception priorities
      • 34.3.3.6 Interrupt priority grouping
      • 34.3.3.7 Exception entry and return
        • 34.3.3.7.1 Exception entry
        • 34.3.3.7.2 Exception return
    • 34.3.4 Fault handling
      • 34.3.4.1 Fault types
      • 34.3.4.2 Fault escalation and hard faults
      • 34.3.4.3 Fault status registers and fault address registers
      • 34.3.4.4 Lockup
    • 34.3.5 Power management
      • 34.3.5.1 Entering sleep mode
        • 34.3.5.1.1 Wait for interrupt
        • 34.3.5.1.2 Wait for event
        • 34.3.5.1.3 Sleep-on-exit
      • 34.3.5.2 Wakeup from sleep mode
        • 34.3.5.2.1 Wakeup from WFI or sleep-on-exit
        • 34.3.5.2.2 Wakeup from WFE
      • 34.3.5.3 The Wake-up Interrupt Controller
      • 34.3.5.4 Power management programming hints
  • 34.4 ARM Cortex-M3 User Guide: Peripherals
    • 34.4.1 About the Cortex-M3 peripherals
    • 34.4.2 Nested Vectored Interrupt Controller
      • 34.4.2.1 The CMSIS mapping of the Cortex-M3 NVIC registers
      • 34.4.2.2 Interrupt Set-enable Registers
      • 34.4.2.3 Interrupt Clear-enable Registers
      • 34.4.2.4 Interrupt Set-pending Registers
      • 34.4.2.5 Interrupt Clear-pending Registers
      • 34.4.2.6 Interrupt Active Bit Registers
      • 34.4.2.7 Interrupt Priority Registers
      • 34.4.2.8 Software Trigger Interrupt Register
      • 34.4.2.9 Level-sensitive and pulse interrupts
        • 34.4.2.9.1 Hardware and software control of interrupts
      • 34.4.2.10 NVIC design hints and tips
        • 34.4.2.10.1 NVIC programming hints
    • 34.4.3 System control block
      • 34.4.3.1 The CMSIS mapping of the Cortex-M3 SCB registers
      • 34.4.3.2 Auxiliary Control Register
        • 34.4.3.2.1 About IT folding
      • 34.4.3.3 CPUID Base Register
      • 34.4.3.4 Interrupt Control and State Register
      • 34.4.3.5 Vector Table Offset Register
      • 34.4.3.6 Application Interrupt and Reset Control Register
        • 34.4.3.6.1 Binary point
      • 34.4.3.7 System Control Register
      • 34.4.3.8 Configuration and Control Register
      • 34.4.3.9 System Handler Priority Registers
        • 34.4.3.9.1 System Handler Priority Register 1
        • 34.4.3.9.2 System Handler Priority Register 2
        • 34.4.3.9.3 System Handler Priority Register 3
      • 34.4.3.10 System Handler Control and State Register
  • Caution
    • 34.4.3.11 Configurable Fault Status Register
      • 34.4.3.11.1 Memory Management Fault Status Register
      • 34.4.3.11.2 Bus Fault Status Register
      • 34.4.3.11.3 Usage Fault Status Register
    • 34.4.3.12 Hard Fault Status Register
    • 34.4.3.13 Memory Management Fault Address Register
    • 34.4.3.14 Bus Fault Address Register
    • 34.4.3.15 System control block design hints and tips
    • 34.4.4 System timer, SysTick
      • 34.4.4.1 SysTick Control and Status Register
      • 34.4.4.2 SysTick Reload Value Register
        • 34.4.4.2.1 Calculating the RELOAD value
      • 34.4.4.3 SysTick Current Value Register
      • 34.4.4.4 SysTick Calibration Value Register
      • 34.4.4.5 SysTick design hints and tips
    • 34.4.5 Memory protection unit
      • 34.4.5.1 MPU Type Register
      • 34.4.5.2 MPU Control Register
      • 34.4.5.3 MPU Region Number Register
      • 34.4.5.4 MPU Region Base Address Register
        • 34.4.5.4.1 The ADDR field
      • 34.4.5.5 MPU Region Attribute and Size Register
        • 34.4.5.5.1 SIZE field values
      • 34.4.5.6 MPU access permission attributes
      • 34.4.5.7 MPU mismatch
      • 34.4.5.8 Updating an MPU region
        • 34.4.5.8.1 Updating an MPU region using separate words
        • 34.4.5.8.2 Updating an MPU region using multi-word writes
        • 34.4.5.8.3 Subregions
      • 34.4.5.9 MPU design hints and tips
        • 34.4.5.9.1 MPU configuration for a microcontroller
  • 34.5 ARM Cortex-M3 User Guide: Glossary
• Chapter 35: Supplementary information
  • 35.1 Abbreviations
  • 35.2 Legal information
    • 35.2.1 Definitions
    • 35.2.2 Disclaimers
    • 35.2.3 Trademarks
  • 35.3 Tables
  • 35.4 Figures
  • 35.5 Contents