CHAP_5 MSP430 Instructions
User Manual: Pdf
Open the PDF directly: View PDF 
.
Page Count: 10
| Download | |
| Open PDF In Browser | View PDF |
MSP430 Family Instruction Set Summary Topics 5 Instruction Set Summary 5-3 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 Symbols and Abbreviations Addressing Modes Instruction Set Summary Clock cycles, Length of Instruction Format I Instructions Format II Instructions Format III Instructions Miscellanous Instructions or Operators 5-4 5-5 5-6 5-8 5-8 5-9 5-9 5-9 Tables Table 5.1 5.2 5.3 5.4 5.5 Title Symbols and Abbreviations used in the Instruction Set Summary Addressing Modes MSP430 Family Instruction Set Summary Format I Instructions Format II Instructions Page 5-4 5-5 5-6 5-8 5-9 Notes Title 5.1 5.2 5.3 5.4 Addressing Modes Emulated Instructions Cycle Time of the DADD Instruction Immediate mode in destination field Page 5-5 5-7 5-8 5-9 5-1 Instruction Set Summary 5-2 MSP430 Family MSP430 Family 5 Instruction Set Summary Instruction Set Summary This chapter summarizes the MSP430 family instruction set. 5-3 Instruction Set Summary 5.1 MSP430 Family Symbols and Abbreviations The following table lists the instruction set symbols and abbreviations used throughout the rest of this chapter. Symbol Definition Symbol Definition src The source operand defined by As and S-reg dst The destination operand defined by Ad and D-reg As The bits representing the addressing mode used for the source Ad The bit representing the addressing mode used for the destination S-reg The used Working Register for the source src D-reg The used Working Register for the destination dst R0 or PC Register 0 or Program Counter R1 or SP Register 1 or Stack Pointer R2 or SR/CG1 Register 2 or Status Register/Constant Generator 1 R3 or CG2 Register 3 or Constant Generator 2 R4 to R15 Working Register, general purpose Rn Working Register with n=4-15, general purpose # Immediate Data @ Register indirect addressing & Absolute address --> Data transfer direction label 16-bit label TOS Top of Stack C Carry Bit N Negative Bit V Overflow Bit Z Zero Bit .B The suffix .B at the instruction memonic will result in a byte operation .W The suffix .W or no suffix at the instruction memonic will result in a word operation MSB Most significant Bit LSB Least significant Bit Table 5.1: Symbols and Abbreviations used in the Instruction Set Summary 5-4 MSP430 Family 5.2 Instruction Set Summary Addressing Modes All seven addressing modes for the source operand and all four addressing modes for the destination operand can address the complete address space. The bit numbers show the contents of the As resp. Ad mode bits. As Ad Addressing Mode Syntax Description 00 0 Register Mode Rn Register contents are operand 01 1 Indexed Mode X(Rn) (Rn + X) points to the operand. X is stored in the next word 01 1 Symbolic Mode ADDR (PC + X) points to the operand. X is stored in the next word. Indexed Mode X(PC) is used 01 1 Absolute Mode &ADDR The word following the instruction contains the absolute address. 10 - Indirect Register Mode @Rn Rn is used as a pointer to the operand 11 - Indirect Autoincrement @Rn+ Rn is used as a pointer to the operand. Rn is incremented afterwards 11 - Immediate Mode #N The word following the instruction contains the immediate constant N. Indirect Autoincrement Mode @PC+ is used Table 5.2: Addressing Modes Note: Addressing Modes The addressing modes using the PC as the working register use the normal effects of the addressing modes. The special addressing modes are caused by the pointing of the PC to the ROM word following the currently executed instruction. 5-5 Instruction Set Summary 5.3 MSP430 Family Instruction Set Summary Status Bits * ADC(.B) ADD(.B) ADDC(.B) AND(.B) BIC(.B) BIS(.B) BIT(.B) * BR CALL * CLR(.B) * CLRC * CLRN * CLRZ CMP(.B) * DADC(.B) DADD(.B) * DEC(.B) * DECD(.B) * DINT * EINT * INC(.B) * INCD(.B) * INV(.B) JC/JHS JEQ/JZ JGE JL JMP JN Legend: 0 x * dst src,dst src,dst src,dst src,dst src,dst src,dst dst dst dst src,dst dst src,dst dst dst dst dst dst Label Label Label Label Label Label dst + C → dst src + dst → dst src + dst + C → dst src .and. dst → dst .not.src .and. dst → dst src .or. dst → dst src .and. dst Branch to ....... PC+2 → stack, dst → PC Clear destination Clear carry bit Clear negative bit Clear zero bit dst - src dst + C → dst (decimal) src + dst + C → dst (decimal) dst - 1 → dst dst - 2 → dst Disable interrupt Enable interrupt Increment destination, dst +1 → dst Double-Increment destination, dst+2→dst Invert destination Jump to Label if Carry-bit is set Jump to Label if Zero-bit is set Jump to Label if (N .XOR. V) = 0 Jump to Label if (N .XOR. V) = 1 Jump to Label unconditionally Jump to Label if Negative-bit is set Status bit always cleared Status bit cleared or set on results Emulated Instructions 1 - Status bit always set Status bit not affected Table 5.3: MPS430 Family Instruction Set Summary 5-6 V x x x 0 0 x x x x x x x x - N x x x x x 0 x x x x x x x x - Z x x x x x 0 x x x x x x x x - C x x x x x 0 x x x x x x x x - MSP430 Family Instruction Set Summary Status Bits JNC/JLO JNE/JNZ MOV(.B) * NOP * POP(.B) PUSH(.B) RETI Label Label src,dst dst src * RET * RLA(.B) * RLC(.B) RRA(.B) RRC(.B) * SBC(.B) * SETC * SETN * SETZ SUB(.B) SUBC(.B) SWPB SXT * TST(.B) XOR(.B) Legend: 0 x * dst dst dst dst dst src,dst src,dst dst dst dst src,dst Jump to Label if Carry-bit is reset Jump to Label if Zero-bit is reset src → dst No operation Item from stack, SP+2 → SP SP - 2 → SP, src → @SP Return from interrupt TOS → SR, SP + 2 → SP TOS → PC, SP + 2 → SZP Return from subroutine TOS → PC, SP + 2 → SP Rotate left arithmetically Rotate left through carry MSB → MSB ....LSB → C C → MSB .........LSB → C Subtract carry from destination Set carry bit Set negative bit Set zero bit dst + .not.src + 1 → dst dst + .not.src + C → dst swap bytes Bit7 → Bit8 ........ Bit15 Test destination src .xor. dst → dst The Status Bit is cleared The Status Bit is affected Emulated Instructions 1 - V x N x Z x C x - - - - x x 0 x x x x 0 x x x x x x x 1 x x x x x x x x x x 1 x x x x x x x x x x 1 x x x x x The Status Bit is set The Status Bit is not affected Table 5.3: MPS430 Family Instruction Set Summary (Concluded) Note: Emulated Instructions All marked instructions ( * ) are emulated instructions. The emulated instructions use core instructions combined with the architecture and implementation of the CPU for higher code efficiency and faster execution. 5-7 Instruction Set Summary 5.4 MSP430 Family Clock cycles, Length of Instruction The operating speed of the CPU is independent from individual instructions. It depends on the instruction format and the addressing modes. The number of clock cycles refer to the internal oscillator frequency. 5.4.1 Format I Instructions Address Mode As Ad 00, Rn 0, Rm 0,PC 00, Rn 1, x(Rm) 1, EDE 1, &EDE 01, x(Rn) 0, Rm 01, EDE 01, &EDE 01, x(Rn) 1, x(Rm) 01, EDE 1, TONI 01, &EDE 1, &TONI 10, @Rn 10, @Rn 11, @Rn+ 11, #N 11, @Rn+ 11, #N 11, @Rn+ 11, #N 0, Rm 1, x(Rm) 1, EDE 1, &EDE 0, Rm 0, PC 0, Rm 0, PC 1, x(Rm) 1, EDE 1, &EDE #of cycles 1 2 4 3 6 3 3 3 2 5 1 2 2 2 1 1 2 2 2 3 2 3 2 3 2 2 5 Table 5.4: Format I Instructions Note: Cycle Time of the DADD Instruction The DADD instruction needs 1 extra cycle. 5-8 Length of instruction 1 1 2 2 2 2 2 Example MOV R5,R8 BR R9 ADD R5,3(R6) XOR R8,EDE MOV R5,&EDE MOV 2(R5),R7 AND EDE,R6 MOV &EDE,R8 ADD 3(R4),6(R9) CMP EDE,TONI MOV 2(R5),&TONI ADD EDE,&TONI AND @R4,R5 XOR @R5,8(R6) MOV @R5,EDE XOR @R5,&EDE ADD @R5+,R6 BR @R9+ MOV #20,R9 BR #2AEh MOV @R9+,2(R4) ADD #33,EDE MOV @R9+,&EDE ADD #33,&EDE MSP430 Family 5.4.2 Instruction Set Summary Format II Instructions Address Mode A(s/d) #of cycles RRC PUSH/ RRA CALL SWPB SXT 1 3/4 4 5 4 5 3 4 00, Rn 01, x(Rn) 01, EDE 10, @Rn 11, @Rn+ see Note 11, #N 3 3 4/5 4/5 Length of instruction [words] Example 1 2 2 1 SWPB R5 CALL 2(R7) PUSH EDE RRC @R9 1 2 SWPB @R10+ CALL #81h Table 5.5: Format II Instructions Note: Immediate mode in destination field Instructions should not use immediate mode in the destination field. This would result in unpredictable program operation. 5.4.3 Format III Instructions Jxx - instructions need all the same #-of-cycles independent of a successfull Jump or not. Clock Cycle: 2 Cycle. Length of Instruction: 1 word. 5.4.4 RETI Miscellanous Instructions or Operators Clock Cycle: 5 Cycle. Length of instruction: 1 word. Interrupt Clock Cycle: 6 Cycle. 5-9 Instruction Set Summary 5-10 MSP430 Family
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.2 Linearized : No Page Count : 10 Create Date : 1998:03:12 07:19:06 Producer : Acrobat Distiller 3.01 for Windows Creator : Windows NT 4.0 Title : Microsoft Word - CHAP_5.DOCEXIF Metadata provided by EXIF.tools