MT7620 Programming Guide E2 20120815

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MT7620
PROGRAMMING
GUIDE

Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

MT7620 Overview
The MT7620 SoC includes a high performance 580 MHz MIPS24KEc CPU core and USB host controller/PHY,
which is designed to enable a multitude of high performance, cost-effective IEEE 802.11n applications with a
MediaTek (Ralink) client card.

Functional Block Diagram
16-Bit
SDR/DDR1/DDR2

EJTAG

To CPU
interrupt
s
INTC

DRAM
Controller

OCP
_IF
OCP Bridge

Arbiter

Timer

PBUS

MIPS 24KEc
64 KB I-Cache
32 KB DCache
(580 MHz)

RBUS (SYS_CLK)

SPI

SPI

NFC

NAND

UART

UART

GPIO

GPIO
/LED

I2C

I2C

I2S

I2S

PCM x4

PCM

PBUS
SDHC

Single-Port
USB 2.0 PHY

PCIe 1.1
PHY

Host/
Device

PCIe x1

WLAN
11n 2x2

Switch
(4FE + 2GE)

GDMA

5-Port EPHY
SD

2.4 GHz

RJ45 x5

RGMII
TMII/MII
x2

Figure 1-1 MT7620 Block Diagram

There are several masters (MIPS 24KEc, USB , PCI Express) in the MT7620 SoC on a high performance, low
latency Rbus, (Ralink Bus). In addition, the MT7620 SoC supports lower speed peripherals such as UART, GPIO,
and SPI via a low speed peripheral bus (Pbus). The SDRAM/DDR1/DDR2 controller is the only bus slave on the
Rbus. It includes an Advanced Memory Scheduler to arbitrate the requests from bus masters, enhancing the
performance of memory access intensive tasks.

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Table of Contents
1. MIPS 24K PROCESSOR
1.1 FEATURES
1.2 BLOCK DIAGRAM
1.3 MEMORY MAP SUMMARY
1.4 CLOCK PLAN
1.5 CPU CLOCK MUX

11
11
12
13
14
15

2. REGISTERS
2.1 NOMENCLATURE
2.2 SYSTEM CONTROL

16
16
17

2.2.1 FEATURES
2.2.2 BLOCK DIAGRAM
2.2.3 LIST OF REGISTERS
2.2.4 REGISTER DESCRIPTIONS (BASE: 0X1000_0000)
2.3 TIMER

17
17
18
19
46

2.3.1 FEATURES
2.3.2 BLOCK DIAGRAM
2.3.3 LIST OF REGISTERS
2.3.4 REGISTER DESCRIPTIONS (BASE: 0X1000_0100)
2.4 INTERRUPT CONTROLLER

46
47
48
49
53

2.4.1 FEATURES
2.4.2 BLOCK DIAGRAM
2.4.3 LIST OF REGISTERS
2.4.4 REGISTER DESCRIPTIONS (BASE: 0X1000_0200)
2.5 SYSTEM TICK COUNTER

53
53
54
55
60

2.5.1 LIST OF REGISTERS
2.5.2 REGISTER DESCRIPTIONS (BASE: 0X1000_0D00)
2.6 UART

60
61
62

2.6.1 FEATURES
2.6.2 BLOCK DIAGRAM
2.6.3 LIST OF REGISTERS
2.6.4 REGISTER DESCRIPTIONS (BASE: 0X1000_0500)
2.7 UART LITE

62
62
63
64
72

2.7.1 FEATURES
2.7.2 BLOCK DIAGRAM
2.7.3 LIST OF REGISTERS
2.7.4 REGISTER DESCRIPTIONS (BASE: 0X1000_0C00)
2.8 PROGRAMMABLE I/O

72
72
73
74
81

2.8.1 FEATURES
2.8.2 BLOCK DIAGRAM
2.8.3 LIST OF REGISTERS
2.8.4 REGISTER DESCRIPTIONS (BASE: 0X1000_0600)
2
2.9 I C CONTROLLER

81
81
82
84
97

2.9.1 FEATURES
2.9.2 BLOCK DIAGRAM
2.9.3 LIST OF REGISTERS

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2.9.4 REGISTER DESCRIPTIONS (BASE: 0X1000_0900)
2.10 NAND FLASH CONTROLLER

99
105

2.10.1 FEATURES
2.10.2 NORMAL MODE FLOW
2.10.3 ECC
2.10.4 LIST OF REGISTERS
2.10.5 REGISTER DESCRIPTIONS (BASE: 0X1000_0800)
2.11 PCM CONTROLLER

105
105
105
108
109
116

2.11.1 FEATURES
2.11.2 BLOCK DIAGRAM
2.11.3 LIST OF REGISTERS
2.11.4 REGISTER DESCRIPTIONS (BASE: 0X1000_2000)
2.11.5 PCM CONFIGURATION
2.12 GENERIC DMA CONTROLLER

116
116
118
119
130
132

2.12.1 FEATURES
2.12.2 BLOCK DIAGRAM
2.12.3 PERIPHERAL CHANNEL CONNECTION
2.12.4 LIST OF REGISTERS
2.12.5 REGISTER DESCRIPTIONS (BASE: 0X1000_2800)
2.13 SPI CONTROLLER

132
132
133
134
135
139

2.13.1 FEATURES
2.13.2 BLOCK DIAGRAM
2.13.3 LIST OF REGISTERS
2.13.4 REGISTER DESCRIPTIONS (BASE: 0X1000_0B00)
2.14 I2S CONTROLLER

139
139
140
141
152

2.14.1 FEATURES
2.14.2 BLOCK DIAGRAM
2
2
2.14.3 I S SIGNAL TIMING FOR I S DATA FORMAT
2.14.4 LIST OF REGISTERS
2.14.5 REGISTER DESCRIPTIONS (BASE: 0X1000_0A00)
2.15 MEMORY CONTROLLER

152
152
153
154
155
159

2.15.1 FEATURES
2.15.2 BLOCK DIAGRAM
2.15.3 SDRAM INITIALIZATION SEQUENCE
2.15.4 SDRAM POWER SAVING CONFIGURATION
2.15.5 DDR INITIALIZATION SEQUENCE
2.15.6 LIST OF REGISTERS
2.15.7 REGISTER DESCRIPTIONS (BASE: 0X1000_0300)
2.16 RBUS MATRIX AND QOS ARBITER

159
159
159
160
161
162
163
178

2.16.1 FEATURES
2.16.2 BLOCK DIAGRAM
2.16.3 LIST OF REGISTERS
2.16.4 REGISTER DESCRIPTIONS (BASE: 0X1000_0400)
2.17 USB HOST CONTROLLER & PHY

178
178
179
180
183

2.17.1 FEATURES
2.17.2 BLOCK DIAGRAM
2.17.3 REGISTER DESCRIPTION (BASE: 0X101C.0000)
2.17.4 EHCI OPERATION REGISTERS (BASE: 0X101C.0000)

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2.17.5 OHCI OPERATION REGISTERS (BASE: 0X101C.1000)
2.18 USB DEVICE CONTROLLER

185
186

2.18.1 FEATURES
2.18.2 BLOCK DIAGRAM
2.18.3 BULK OUT
2.18.4 LEGACY MODE
2.18.5 AGGREGATION MODE
2.18.6 DE-AGGREGATION MODE
2.18.7 BULK-OUT AGGREGATION FORMAT
2.18.8 BULK IN
2.18.9 PDMA DESCRIPTOR FORMAT
2.18.10 REGISTER DESCRIPTIONS (BASE: 0X1012_0000)
2.18.11 USB DEVICE CONTROLLER REGISTERS
2.18.12 UDMA REGISTERS
2.18.13 PDMA REGISTERS
2.19 FRAME ENGINE

186
186
186
187
187
188
189
189
190
192
192
193
194
202

2.19.1 PSE FEATURES
2.19.2 PPE FEATURES
2.19.3 PACKET DMA (PDMA) FEATURES
2.19.4 BLOCK DIAGRAM
2.19.5 PDMA FIFO-LIKE RING CONCEPT
2.19.6 PDMA TX DESCRIPTOR FORMAT
2.19.7 PDMA RX DESCRIPTOR FORMAT
2.19.8 GLOBAL REGISTERS (BASE: 0X1010_0000)
2.19.9 CPU PORT REGISTERS (BASE: 0X1010_0400)
2.19.10 PDMA REGISTERS (BASE: 0X1010_0800)
2.19.11 MIB COUNTER DESCRIPTION (BASE: 0X1010_1000)
2.20 ETHERNET SWITCH

202
202
202
203
204
205
207
209
216
223
235
237

2.20.1 FEATURES
2.20.2 BLOCK DIAGRAM
2.20.3 FRAME CLASSFICATION
2.20.4 SWITCH L2/L3 ADDRESS TABLE
2.20.5 VIRTUAL LAN
2.20.6 ACCESS CONTROL LOGIC
2.20.7 ARL REGISTERS (BASE: 0X1011_0000)
2.20.8 BMU REGISTERS
2.20.9 PORT REGISTERS
2.20.10 MAC REGISTERS
2.20.11 MIB REGISTERS
2.20.12 GSW CONFIGURATION REGISTERS
2.20.13 MDIO CONTROL
2.21 PCI/PCIE CONTROLLER

237
238
238
240
244
247
252
291
308
320
329
338
347
354

2.21.1 BLOCK DIAGRAM
2.21.2 PCIE CONTROLLER ACTING AS A PCIE DEVICE
2.21.3 BLOCK DIAGRAM
2.21.4 PCI/PCIE MASTER ACCESS IN HOST MODE
2.21.5 PCIE CONTROLLER HOST MODE INITIALIZATON EXAMPLE
2.21.6 HOST-PCI BRIDGE REGISTERS (BASE: 0X1014_0000)
2.21.7 PCIE0 RC CONTROL REGISTERS (BASE: 0X1014_2000)

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356
357
358
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2.21.8 MEMORY WINDOWS REGISTERS (BASE: 0X1015_0000)
2.21.9 IO WINDOWS (BASE: 0X1016_0000)
2.22 802.11N 2T2R MAC/BBP
2.22.1 FEATURES
2.22.2 BLOCK DIAGRAM
2.22.3 802.11N 2T2R MAC/BBP REGISTER MAP
2.22.4 SCH/WPDMA REGISTERS (BASE: 0X1018_0000)
2.22.5 PBF REGISTERS (BASE: 0X1018_0000)
2.22.6 RF TEST REGISTERS (BASE: 0X1018_0000)
2.22.7 MAC REGISTERS (BASE: 0X1018_0000)
2.22.8 MAC TIMING CONTROL REGISTERS (BASE: 0X1018_0000)
2.22.9 MAC POWER SAVE CONFIGURATION REGISTERS (BASE: 0X1018_0000)
2.22.10 MAC TX CONFIGURATION REGISTERS (BASE: 0X1018_0000)
2.22.11 MAC RX CONFIGURATION REGISTERS (BASE: 0X1018_0000)
2.22.12 MAC SECURITY CONFIGURATION REGISTERS (BASE: 0X1018_0000)
2.22.13 MAC HCCA/PSMP CONTROL STATUS REGISTERS (BASE: 0X1018_0000)
2.22.14 MAC STATISTIC COUNTERS (BASE: 0X1018_0000)
2.22.15 MAC SEARCH TABLE (BASE: 0X1018_1800)
3. SECURITY ENTRY FORMATS AND KEY TABLES
3.1 SECURITY ENTRY FORMAT TABLES (BASE: 1018.0000, OFFSET: 0X4000)
3.1.1 SECURITY KEY FORMAT (8DW)
3.1.2 IV/EIV/WAPI_PN FORMAT (4DW)
3.1.3 WCID ATTRIBUTE ENTRY FORMAT (1DW)
3.1.4 SHARED KEY MODE ENTRY FORMAT (1DW)
3.2 SECURITY TABLES (OFFSET: 0X4000)
3.3 SECURITY TABLE MAP
3.3.1 PAIRWISE KEY TABLE (OFFSET: 0X4000)
3.3.2 IV/EIV TABLE (OFFSET: 0X6000)
3.3.3 WCID ATTRIBUTE TABLE (OFFSET: 0X6800)
3.3.4 SHARED KEY TABLE (OFFSET: 0X6C00)
3.3.5 SHARED KEY MODE (OFFSET: 0X7000)
3.3.6 SPARE MEMORY SPACE MODE (OFFSET: 0X7010 TO 0X73EC)
3.3.7 SHARED KEY MODE EXTENSION (FOR BSS_IDX=8 TO 15) (OFFSET: 0X73F0)
3.3.8 SHARED KEY TABLE EXTENSION (FOR BSS_IDX=8 TO 15) (OFFSET: 0X7400)
3.3.9 WAPI PN TABLE (EXTENSION OF IV/EIV TABLE) (OFFSET: 0X7800)
4. TX/RX DESCRIPTORS AND WIRELESS INFORMATION
4.1 TX DESCRIPTORS AND FRAME INFORMATION

367
367
368
368
368
369
370
382
392
393
409
416
421
449
457
458
462
471
473
473
473
473
474
475
476
476
477
477
477
477
478
478
479
479
480
481
481

4.1.1 TXD FORMAT
4.1.2 TX WIRELESS INFORMATION
4.2 RX DESCRIPTORS AND WIRELESS INFORMATION

482
484
488

4.2.1 RXD FORMAT
4.2.2 RXINFO FORMAT
4.2.3 RXWI FORMAT
4.3 BRIEF PHY RATE FORMAT AND DEFINITION

489
490
492
494

4.3.1 MODULATION AND CODING SCHEME
5. SD HOST CONTROLLER
5.1 FEATURES

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5.2 SD HOST BLOCK DIAGRAM
5.2.1 BASIC DMA MODE
5.2.2 LINKED-LIST BASED DMA MODE
5.2.3 DMA GENERIC PACKET DESCRIPTOR (GPD) FORMAT
5.2.4 DMA BUFFER DESCRIPTOR (BD) FORMAT
5.2.5 REGISTER DESCRIPTION (BASE: 0X1013_0000)

497
498
498
500
502
503

6. LIST OF REGISTERS

504

7. ABBREVIATIONS

520

8. REVISION HISTORY

523

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Table of Figures
FIGURE 1-1 MT7620 BLOCK DIAGRAM .......................................................................................................................... 2
FIGURE 1-1 MIPS 24KEC PROCESSOR .......................................................................................................................... 12
FIGURE 1-2 MT7620 CLOCK DIAGRAM ........................................................................................................................ 14
FIGURE 1-3 CPU CLOCK MUX ..................................................................................................................................... 15
FIGURE 2-1 SYSTEM CONTROL BLOCK DIAGRAM ............................................................................................................. 17
FIGURE 2-2 TIMER BLOCK DIAGRAM ............................................................................................................................. 47
FIGURE 2-3 INTERRUPT CONTROLLER BLOCK DIAGRAM .................................................................................................... 53
FIGURE 2-4 UART BLOCK DIAGRAM ............................................................................................................................. 62
FIGURE 2-5 UART LITE BLOCK DIAGRAM ...................................................................................................................... 72
FIGURE 2-6 PROGRAMMABLE I/O BLOCK DIAGRAM ........................................................................................................ 81
FIGURE 2-7 I2C CONTROLLER BLOCK DIAGRAM .............................................................................................................. 97
FIGURE 2-8 NORMAL MODE FLOW............................................................................................................................. 105
FIGURE 2-9 24-BIT ECC GENERATED FROM 512-BYTE DATA .......................................................................................... 106
FIGURE 2-10 HARDWARE ECC DETECTION FLOWCHART ................................................................................................. 107
FIGURE 2-11 PCM CONTROLLER BLOCK DIAGRAM ........................................................................................................ 116
FIGURE 2-12 GENERIC DMA CONTROLLER BLOCK DIAGRAM........................................................................................... 132
FIGURE 2-13 SPI CONTROLLER BLOCK DIAGRAM .......................................................................................................... 139
2
FIGURE 2-14 I S TRANSMITTER BLOCK DIAGRAM .......................................................................................................... 152
FIGURE 2-15 I2S TRANSMIT/RECEIVE ......................................................................................................................... 153
FIGURE 2-16 SRAM/SDRAM CONTROLLER BLOCK DIAGRAM ........................................................................................ 159
FIGURE 2-17 QOS ARBITRATION BLOCK DIAGRAM ........................................................................................................ 178
FIGURE 2-18 USB HOST CONTROLLER & PHY BLOCK DIAGRAM ...................................................................................... 183
FIGURE 2-19 USB DEVICE CONTROLLER BLOCK DIAGRAM .............................................................................................. 186
FIGURE 2-20 DE-AGGREGATION FLOW ........................................................................................................................ 188
FIGURE 2-21 BULK-OUT AGGREGATION FORMAT .......................................................................................................... 189
FIGURE 2-22 PDMA TX DESCRIPTOR FORMAT ............................................................................................................. 190
FIGURE 2-23 PDMA RX DESCRIPTOR FORMAT ............................................................................................................. 191
FIGURE 2-24 USB DEVICE REGISTER MAPPING............................................................................................................. 192
FIGURE 2-25 FRAME ENGINE BLOCK DIAGRAM ............................................................................................................. 203
FIGURE 2-26 PDMA FIFO-LIKE RING CONCEPT ........................................................................................................... 204
FIGURE 2-27 PDMA TX DESCRIPTOR FORMAT ............................................................................................................. 205
FIGURE 2-28 PDMA RX DESCRIPTOR FORMAT ............................................................................................................. 207
FIGURE 2-29 ETHERNET SWITCH BLOCK DIAGRAM ........................................................................................................ 238
FIGURE 2-30 PHY ADDRESS DECODING (I)................................................................................................................... 347
FIGURE 2-31 PHY ADDRESS DECODING (II) .................................................................................................................. 348
FIGURE 2-32 PCIE HOST TOPOLOGY ........................................................................................................................... 354
FIGURE 2-33 PCIE AP MODE .................................................................................................................................... 355
FIGURE 2-34 PCIE CONTROLLER BEHAVING AS A PCIE ENDPOINT..................................................................................... 356
FIGURE 2-35 PCIE RC/EP BLOCK DIAGRAM ................................................................................................................ 357
FIGURE 2-36 PCIE MEMORY SPACE PROGRAMMABLE MAPPING...................................................................................... 358
FIGURE 2-37 PCI MEMORY SPACE FIXED MAPPING....................................................................................................... 358
FIGURE 2-38 I/O SPACE PROGRAMMABLE MAPPING ..................................................................................................... 358
FIGURE 2-39 802.11N 2T2R MAC/BBP BLOCK DIAGRAM ........................................................................................... 368
FIGURE 2-40 802.11N 2T2R MAC/BBP REGISTER MAP .............................................................................................. 369
FIGURE 3-1 SECURITY KEY MEMORY LOCATIONS ........................................................................................................... 476
FIGURE 4-1 TXD AND TX FRAME INFORMATION............................................................................................................ 481
FIGURE 4-2 TXD FORMAT ........................................................................................................................................ 482
FIGURE 4-3 RX DESCRIPTOR RING .............................................................................................................................. 488

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FIGURE 4-4 RX DESCRIPTOR FORMAT .......................................................................................................................... 489
FIGURE 4-5 RXINFO FORMAT ................................................................................................................................... 490
FIGURE 4-6 RXWI FRAME FORMAT ............................................................................................................................ 492
FIGURE 5-1 SD HOST BLOCK DIAGRAM ....................................................................................................................... 497
FIGURE 5-2 BASIC DMA........................................................................................................................................... 498
FIGURE 5-3 DESCRIPTOR DMA .................................................................................................................................. 499
FIGURE 5-4 GPD FORMAT ........................................................................................................................................ 500
FIGURE 5-5 BD FORMAT .......................................................................................................................................... 502

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List of Tables
TABLE 2-1 UART LITE INTERRUPT PRIORITIES ................................................................................................................. 75
TABLE 2-2 PDMA RX FIELD DESCRIPTIONS .................................................................................................................. 191
TABLE 2-3 RULE MASK ............................................................................................................................................. 249
TABLE 2-4 RATE CONTROL ........................................................................................................................................ 249
TABLE 2-5 RULE CONTROL ........................................................................................................................................ 249
TABLE 2-6 TRTCM METER TABLE............................................................................................................................... 251
TABLE 2-7 ADDRESS TABLE WRITE DATA REGISTER: MAC ADDRESS ................................................................................. 277
TABLE 2-8 ADDRESS TABLE WRITE DATA REGISTER: DIP ENTRY ....................................................................................... 277
TABLE 2-9 ADDRESS TABLE WRITE DATA REGISTER: SIP ENTRY ....................................................................................... 277
TABLE 2-10 ADDRESS TABLE READ DATA REGISTER: MAC ENTRY .................................................................................... 279
TABLE 2-11 ADDRESS TABLE READ DATA REGISTER: DIP ENTRY....................................................................................... 280
TABLE 2-12 ADDRESS TABLE READ DATA REGISTER: SIP ENTRY ....................................................................................... 280
TABLE 2-13 VLAN AND ACL WRITE DATA-I REGISTER: VLAN ENTRY ............................................................................... 281
TABLE 2-14 VLAN AND ACL WRITE DATA-I REGISTER: ACL RULE TABLE .......................................................................... 282
TABLE 2-15 VLAN AND ACL WRITE DATA-I REGISTER: ACL RULE MASK .......................................................................... 282
TABLE 2-16 VLAN AND ACL WRITE DATA-I REGISTER: ACL RATE CONTROL ..................................................................... 282
TABLE 2-17 VLAN AND ACL WRITE DATA-I REGISTER: ACL RULE CONTROL ..................................................................... 282
TABLE 2-18 VLAN AND ACL WRITE DATA-I REGISTER: TRTCM METER TABLE ................................................................... 283
TABLE 2-19 VLAN AND ACL WRITE DATA-II REGISTER: VLAN ENTRY .............................................................................. 283
TABLE 2-20 VLAN AND ACL WRITE DATA-II REGISTER: ACL RULE TABLE ......................................................................... 283
TABLE 2-21 VLAN AND ACL WRITE DATA-II REGISTER: ACL RULE MASK ......................................................................... 283
TABLE 2-22 VLAN AND ACL WRITE DATA-II REGISTER: ACL RATE CONTROL .................................................................... 283
TABLE 2-23 VLAN AND ACL WRITE DATA-II REGISTER: ACL RULE CONTROL .................................................................... 283
TABLE 2-24 VLAN AND ACL WRITE DATA-II REGISTER: TRTCM METER TABLE .................................................................. 284
TABLE 2-25 DEBUG CONTROL REGISTER: DEBUG ID AND CONTROL .................................................................................. 289
TABLE 2-26 PCI/PCIE SCENERIO AND RELATIVE CONTROL REGISTER SETTINGS ..................................................................... 356
TABLE 2-27: 0X1398 TX_RATE_LUT_EN = 0 AND MULTI_MAC_ADDRESS = 0 ......................................................... 471
TABLE 2-28: 0X1398 TX_RATE_LUT_EN = 1 AND MULTI_MAC_ADDRESS = 0 ......................................................... 471
TABLE 2-29: 0X1398 TX_RATE_LUT_EN = 1 AND MULTI_MAC_ADDRESS = 1 ......................................................... 472
TABLE 3-1 IV/EIV FORMAT ...................................................................................................................................... 473
TABLE 3-2 WAPI_PN FORMAT ................................................................................................................................. 474
TABLE 3-3 WCID ATTRIBUTE ENTRY FORMAT .............................................................................................................. 475
TABLE 3-4 SHARED KEY MODE ENTRY FORMAT (1DW) ................................................................................................. 475
TABLE 3-5 PAIRWISE KEY TABLE (OFFSET: 0X4000) ....................................................................................................... 477
TABLE 3-6 IV/EIV TABLE (OFFSET: 0X6000) ................................................................................................................ 477
TABLE 3-7 WCID ATTRIBUTE TABLE (OFFSET: 0X6800) ................................................................................................. 477
TABLE 3-8 SHARED KEY TABLE (OFFSET: 0X6C00) ......................................................................................................... 478
TABLE 3-9 SHARED KEY MODE (OFFSET: 0X7000) ........................................................................................................ 478
TABLE 3-10 SHARED KEY MODE EXTENSION (FOR BSS_IDX=8 TO15) (OFFSET: 0X73F0) .................................................... 479
TABLE 3-11 SHARED KEY TABLE EXTENSION (FOR BSS_IDX=8 TO15) (OFFSET: 0X7400) .................................................... 480
TABLE 3-12 WAPI PN TABLE (EXTENSION OF IV/EIV TABLE) (OFFSET: 0X73F0) ............................................................... 480
TABLE 4-1 TX DESCRIPTOR FORMAT FIELD DESCRIPTIONS ............................................................................................... 483
TABLE 4-2 TXWI FRAME FORMAT.............................................................................................................................. 484
TABLE 4-3 TXWI FIELD DESCRIPTIONS ........................................................................................................................ 487
TABLE 4-4 RXWI FIELD DESCRIPTIONS ........................................................................................................................ 493
TABLE 4-5 BRIEF PHY RATE FORMAT AND DEFINITION .................................................................................................. 494
TABLE 4-6 MODULATION AND CODING SCHEME ........................................................................................................... 496

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1. MIPS 24K Processor
1.1 Features
 8-stage pipeline
 32-bit address paths
 64-bit data paths to caches and external interfaces
 MIPS32-Compatible Instruction Set
 Multiply-Accumulate and Multiply-Subtract Instructions (MADD, MADDU, MSUB, MSUBU)
 Targeted Multiply Instruction (MUL)
 Zero/One Detect Instructions (CLZ, CLO)
 Wait instructions (WAIT)
 Conditional Move instructions (MOVZ, MOVN)
 Prefetch instructions (PREF)
 MIPS32 Enhanced Architecture (Release 2) Features
 Vectored interrupts and support for an external interrupt controller
 Programmable exception vector base
 Atomic interrupt enable/disable
 GPR shadow registers (one, three or seven additional shadows can be optionally added to minimize
latency for interrupt handlers)
 Bit field manipulation instructions
 MIPS32 Privileged Resource Architecture
 MIPS DSP ASE
 Fractional data types (Q15, Q31)
 Saturating arithmetic
 SIMD instructions operate on 2x16 b or 4x8 b simultaneously
 3 additional pairs of accumulator registers
 Programmable Memory Management Unit
 32 dual-entry JTLB with variable page sizes
 4-entry ITLB
 8-entry DTLB
 Optional simple Fixed Mapping Translation (FMT) mechanism
 MIPS16e™ Code Compression
 16-bit encodings of 32-bit instructions to improve code density
 Special PC-relative instructions for efficient loading of addresses and constants
 SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines
 Improved support for handling 8 and 16-bit datatypes
 Programmable L1 Cache Sizes
 Instruction cache size: 32 KB
 Data cache size: 16 KB
 4-Way Set Associative
 Up to 8 outstanding load misses
 Write-back and write-through support
 32-byte cache line size

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1.2 Block Diagram

ISPRAM DMA
OCP I/F

User-defined
CorExtend
block

Instruction
scratchpad
RAM

CorExtend

CP2

Off/on chip
trace I/F

EJTAG
Trace
TAP

Off-chip
Debug I/F

Fetch Unit
8-entry instruction buffer
512-entry BHT
4-entry RPS

MDU

User-defined
COP2 block

i-cache 0/8/16/32/64 KB
4-way set associative

Execution Unit
(RF/ALU/
Shift)

MMU
16/32/64 JTLB or FMT

BIU
4-entry merging
write buffer,
10 outstanding
reads

OCP
Interface onchip Bus(es)

Non-blocking load/store
unit
8 outstanding misses
DSPRAM
DMA OCP
Interface

System Coprocessor

Power
Managment

D-cache
0/8/16/32/64 KB
4-way set associative

Data scratchpad
RAM

Fixed / Required
Optional

Figure 1-1 MIPS 24KEc Processor

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

1.3 Memory Map Summary
Start
0000.0000
1000.0000
1000.0100
1000.0200
1000.0300
1000.0400
1000.0500
1000.0600
1000.0700
1000.0800
1000.0900
1000.0A00
1000.0B00
1000.0C00
1000.0D00
1000.2000
1000.2800
1000.3000
1000.3800
1000.4000
1010.0000
1011.0000
1011.8000
1012.0000
1012.8000
1013.0000
1013.4000
1014.0000
1018.0000
101C.0000
1020.0000
1024.0000
1028.0000
1C00.0000

-

End

Size

Description

0FFF.FFFF
1000.00FF
1000.01FF
1000.02FF
1000.03FF
1000.04FF
1000.05FF
1000.06FF
1000.07FF
1000.08FF
1000.09FF
1000.0AFF
1000.0BFF
1000.0CFF
1000.0DFF
1000.27FF
1000.2FFF
1000.37FF
1000.3FFF
100F.FFFF
1010.FFFF
1011.7FFF
1011.FFFF
1012.7FFF
1012.FFFF
1013.3FFF
1013.FFFF
1017.FFFF
101B.FFFF
101F.FFFF
1023.FFFF
1027.FFFF
1BFF.FFFF
1C00.7FFF

256 MBytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
2 KBytes
2 KBytes
2 KBytes
2 KBytes

DDR2 256 MB/ DDR1 256 MB/SDRAM 128 MB
SYSCTL
TIMER
INTCTL
MEM_CTRL (SDR/DDR)
Rbus Matrix CTRL
UART
PIO
<>
NAND Controller
I2C
I2S
SPI
UARTLITE
MIPS CNT
PCM (up to 16 channels)
Generic DMA (up to 64 channels)
<>
<>
<>
Frame Engine
Ethernet Swtich
ROM
USB Device Control
<>
SDHC
<>
PCI Express
WLAN BBP/MAC
USB Host
<>
<>
<>
When the system is powered on, a 24 KB internal
boot ROM is mapped.

PGMT7620_V.1.0_040503

64 KBytes
32 KBytes
32 KBytes
32 KBytes
32 KBytes
16 KBytes
48 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
32 KB ROM

Page 13 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

1.4 Clock Plan
CLK_PERI
(Timer/Uart/I2C/I2S)

20/40 MHz

CLK_SDHC

/12
48 MHz
/10

12 MHz
/4

USB PHY (TSMC)
12/48 MHz

20/40 MHz

Xtal in
RF

/3
/4
/5

20/40 MHz

600 MHz
20/40 MHz

CPU PLL
(SSC)

0

0

1

1

DRAM_CLK

PLL_CLK *
(1/M)

CPU_CLK
SYS_CLK
OCP_SYNC

CPU_CLK_AUX0
CPU_CLK_AUX1

480 MHz
BBP PLL
20/40 MHz

PCM_480
PCM_240

/2
PLL_PCIe CG
(w/ SSC)
20/40 Mhz

100 MHz

PCIe DRV

PCIe_CLK (EXT)
PCIe_PHY_CLK

PCIe PHY (PLL)
2.5 GHz

EPHY
20/40 MHz

125 MHz
250 MHz

EPHY_CLK
GSW

Figure 1-2 MT7620 Clock Diagram

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

1.5 CPU Clock Mux
20/40 MHz

Crystal

BBP
PLL

/2

480 MHz

/3
/4

1
CPU
PLL

Fractional
Clock
Generator

1
0

600 MHz

DRAM_CLK

CPU_CLK
SYS_CLK

0

CPU_CLK_AUX0

CPU_SYS_CLKCFG: (offset: 0x003C)

CPLL_CFG0: (offset: 0x0054)
CPLL_CFG1: (offset: 0x0058)

CPU_CLK_AUX1

Figure 1-3 CPU Clock Mux

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2. Registers
2.1 Nomenclature
The following nomenclature is used for register types:
RO
Read Only
WO
Write Only
RW
Read or Write
RC
Read Clear
W1C
Write One Clear
Reserved bit
X
Undefined binary value

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.2 System Control
2.2.1 Features
 Provides read-only chip revision registers
 Provides a window to access boot-strapping signals
 Supports memory remapping configurations
 Supports software reset to each platform building block
 Provides registers to determine GPIO and other peripheral pin muxing schemes
 Provides some power-on-reset only test registers for software programmers
 Combines miscellaneous registers (such as clock skew control, status register, memo registers, etc)
2.2.2 Block Diagram

System Control Block
Memory Remapping

CPU Rbus Wrapper

Boot Strapping Signals
GPIO Pin Muxing Scheme
System Control
Registers

Per Block S/W Reset

Pin Muxing Block
Platform Blocks

Cache Hit/Miss Strobes
Miscellaneous Registers

To/From MIPS

PCIe, PCM, ...

PalmBus Interface

Figure 2-1 System Control Block Diagram

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.2.3 List of Registers
No. Offset
Register Name

Description

Page

1

0x0000

CHIPID0_3

Chip ID ASCII Character 0-3

19

2

0x0004

CHIPID4_7

Chip ID ASCII Character 4-7

19

3

0x000C

REVID

Chip Revision Identification

19

4

0x0010

SYSCFG0

System Configuration Register 0

19

5

0x0014

SYSCFG1

System Configuration Register 1

20

6

0x0018

TESTSTAT

Firmware Test Status Register

22

7

0x001C

TESTSTAT2

Firmware Test Status Register 2

22

8

0x0020

Reserved

-

22

9

0x0024

Reserved

-

23

10

0x0028

Reserved

-

23

11

0x002C

CLKCFG0

Clock Configuration Register 0

23

12

0x0030

CLKCFG1

Clock Configuration Register 1

24

13

0x0034

RSTCTRL

Reset Control

25

14

0x0038

RSTSTAT

Reset Status

26

15

0x003C

CPU_SYS_CLKCFG

CPU and SYS Clock Control

27

16

0x0040

CLK_LUT_CFG

Clock Look Up Table Configuration

29

17

0x0044

CUR_CLK_STS

Current clock status

30

18

0x0048

BPLL_CFG0

BB PLL Configuration 0

31

19

0x004C

BPLL_CFG1

BB PLL Configuration 1

31

20

0x0054

CPLL_CFG0

CPU PLL Configuration 0

33

21

0x0058

CPLL_CFG1

CPU PLL Configuration 1

36

22

0x005C

USB_PHY_CFG

USB PHY control

36

23

0x0060

GPIOMODE

GPIO Purpose Select

36

24

0x0064

PCIPDMA_STAT

Control and Status of PDMA in PCIe Device

39

25

0x0088

PMU0_CFG

Power Management Unit 0 Configuration

39

26

0x008C

PMU1_CFG

Power Management Unit 1 Configuration

40

27

0x0098

PPLL_CFG0

PCIe PLL Configuration 0

41

28

0x009C

PPLL_CFG1

PCIe PLL Configuration 1

43

29

0x00A0

PPLL_DRV

PCIe Driver Configuration

44

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.2.4 Register Descriptions (base: 0x1000_0000)
1. CHIPID0_3: Chip ID ASCII Character 0-3 (offset: 0x0000)
Bits
Type
Name
Description

Initial Value

31:24

RO

CHIP_ID3

ASCII CHIP Name Identification Character 3

0x36

23:16

RO

CHIP_ID2

ASCII CHIP Name Identification Character 2

0x37

15:8

RO

CHIP_ID1

ASCII CHIP Name Identification Character 1

0x54

7:0

RO

CHIP_ID0

ASCII CHIP Name Identification Character 0

0x4D

2. CHIPID4_7: Chip Name ASCII Character 4-7 (offset: 0x0004)
Bits
Type
Name
Description

Initial Value

31:24

RO

CHIP_ID7

ASCII CHIP Name Identification Character 7

0x20

23:16

RO

CHIP_ID6

ASCII CHIP Name Identification Character 6

0x20

15:8

RO

CHIP_ID5

ASCII CHIP Name Identification Character 5

0x30

7:0

RO

CHIP_ID4

ASCII CHIP Name Identification Character 4

0x32

3. REVID: Chip Revision Identification (offset: 0x000C)
Bits
Type
Name
Description

Initial Value

31:17

-

-

Reserved

16

RO

PKG_ID

Package ID
0: DRQFN-148 pin
1: TFBGA-269 ball
NOTE: This value is determined by the package
used.

15:12

-

-

Reserved

0x0

11:8

RO

VER_ID

Chip Version Number

0x2

7:4

-

-

Reserved

0x0

3:0

RO

ECO_ID

Chip ECO Number

0x1

4. SYSCFG0: System Configuration Register 0 (offset: 0x0010)
Bits
Type
Name
Description

0x0
-

Initial Value

31:24

RW

TEST_CODE

Test Code
Default value is from bootstrap and can be
modified by software.

0x0

23

-

-

Reserved

0x0

22:12

RO

BS_SHADOW

BS shadow register for last boot-up value
Displays a backup copy of the last bootup value.

BS

11:9

-

-

Reserved

0x0

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

8

RO

DRAM_FROM_EE

DRAM Configuration from EEPROM
0: DRAM/PLL configuration from EEPROM.
1: DRAM configuration from Auto Detect.
For more information see the Bootstrapping
Pins Description in the datasheet for this chip.

Initial Value
BS

7

RO

DBG_JTAG_MODE

Debug JTAG Mode
0: EPHY_LED
1: JTAG MODE

BS

6

RO

XTAL_FREQ_SEL

Xtal Frequency Select
0: 20 MHz
1: 40 MHz

BS

5:4

RO

DRAM_TYPE

DRAM Type
0: SDRAM (150 MHz) (LVTTL 3.3 V) TSOP
Package
1: DDR1 (200 MHz) TSOP Package
2: DDR2 (200 MHz) FBGA Package

BS

3:0

RO

CHIP_MODE

Chip Mode
A vector to set chip function/test/debug modes
in non-test/debug operation.
For more information see the Bootstrapping
Pins Description in the datasheet for this chip.

BS

5. SYSCFG1: System Configuration Register 0 (offset: 0x0014)
Bits
Type
Name
Description

Initial Value

31:30

-

-

Reserved

-

29:28

RW

DDR_DPIN_RXPWD

SDRAM Data Pin Receiver Circuit Power Down
Control*
(DQ/DQS)
0: Disable (SDR/DDR1/DDR2 default)
1: Enable
2: Enable while data pin is output mode.
3: Enable while data pin is input mode.

BS

27:26

RW

DDR_DPIN_ODT

SDRAM Data Pin On Die Termination Setting*
(DQ/DQS)
[27:26] SDR
SDR
DDR1
DDR2
(3.3 V) (2.5 V/
1.8 V)
0
(Disable) (Disable) (Disable) (Disable)
1
75 Ω
75 Ω
75 Ω
75 Ω
2
150 Ω
150 Ω
150 Ω
150 Ω
3
N/A
N/A
N/A
N/A

BS

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

25:24

RW

DDR_DPIN_DRV

SDRAM Data Pin Driving Setting*
(DQ/DQS/DQM)
[25:24] SDR
SDR
DDR1
(3.3 V) (2.5 V/
1.8 V)
0
N/A
10 mA Class II
1
N/A
8 mA
N/A
2
16 mA 4 mA
(Class I)
3
(8 mA) (2 mA) N/A

Initial Value
BS
DDR2

Full
N/A
(Half)
N/A

23

-

-

Reserved

-

22

RW

DDR_CPIN_RXPWD

SDRAM Command Pin Receiver Circuit Power
Down Control*
(MA/MBA/MCS_N/MWE_N/MRAS_N/
MCAS_N/ MCKE)
0: Disable power down
1: Enable power down (SDR/DDR1/DDR2
default)

BS

21:20

RW

DDR_CPIN_DRV

SDRAM Command Pin Driving Setting
(MA/MBA/MCS_N/MWE_N/MRAS_N/
MCAS_N/ MCKE)
[21:20] SDR
SDR
DDR1
(3.3 V) (2.5 V/
1.8 V)
0
N/A
10 mA Class II
1
N/A
8 mA
N/A
2
16 mA 4 mA
(Class I)
3
(8 mA) (2 mA) N/A

BS

DDR2

Full
N/A
(Half)
N/A

19

RW

DDR_PIN_MODE

SDRAM Pin Receiver Mode Selection*
0: Select pseudo-differential receiver for 2.5 V
SSTL2 and 1.8 V SSTL18. (DDR1/DDR2
default)
1: Select CMOS receiver for 3.3 V LVTTL, 2.5 V
LVCMOS and 1.8 V MDDR. (SDR default)

BS

18:17

-

-

Reserved

0x0

16

RW

PULL_EN

Pad Pull High/Low Enable
0: Disable
1: Enable

0x0

15:14

RW

GE2_MODE

Gigabit Port #2 Mode
Sets the interface mode on Gigabit port 2.
2’b00: RGMII Mode (10/100/1000 Mbps)
2’b01: MII Mode (10/100 Mbps)
2’b10: Reverse MII Mode (10/100 Mbps)
2’b11: RJ-45 Mode

0x3

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

13:12

RW

GE1_MODE

Gigabit Port #1 Mode
Sets the interface mode on Gigabit port 1.
2’b00: RGMII Mode (10/100/1000 Mbps)
2’b01: MII Mode (10/100 Mbps)
2’b10: Reverse MII Mode (10/100 Mbps)
2’b11: Reserved

0x0

11

-

-

Reserved

0x0

10

RW

USB0_HOST_MODE

0: Set USB #0 to device mode
1: Set USB #0 to host mode.

BS

9

-

-

Reserved

0x0

8

RW

PCIE_RC_MODE

0: Set PCIe to EP mode
1: Set PCIe to RC mode

BS

7:4

-

-

Reserved

0x0

3:2

RW

GE2_PIN_DRV

RGMII2 Pin Driving Setting
[1:0] LVTTL (3.3 V)
0
N/A
1
N/A
2
16 mA
3
(8 mA)

LVCMOS (2.5 V)
10 mA
8 mA
4 mA
(2 mA)

RGMII1 Pin Driving Setting
[1:0] LVTTL (3.3 V)
0
N/A
1
N/A
2
16 mA
3
(8 mA)

LVCMOS (2.5 V)
10 mA
8 mA
4 mA
(2 mA)

1:0

RW

GE1_PIN_DRV

Initial Value

0x3

0x3

NOTE:
1. For bits marked with an *, the default value is defined by bootstrap “DRAM_TYPE” and can be modified by
software.
2. Default values are marked with parentheses.
6. TESTSTAT: Firmware Test Status Register (offset: 0x0018)
Bits
Type
Name
Description
31:0
RW
TSETSTAT
Firmware Test Status
NOTE: This register is reset only by a power-on reset.
7. TESTSTAT2: Firmware Test Status Register 2 (offset: 0x001C)
Bits
Type
Name
Description
31:0
RW
TSETSTAT2
Firmware Test Status 2
NOTE: This register is reset only by a power-on reset.
8. Reserved (offset: 0x0020)
Bits
Type
Name

PGMT7620_V.1.0_040503

Description

Initial Value
0x0

Initial Value
0x0

Initial Value

Page 22 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

Initial Value

31:0

RW

BOOTSRAM_BASE

Boot from SRAM base address (Test mode only)
Addr_tuned =
bootsram[31:0] | oc_maddr[15:0]

0x10240000

9. Reserved (offset: 0x0024)
Bits
Type
Name

Description

Initial Value

31:0

Reserved

-

-

10. Reserved (offset: 0x0028)
Bits
Type
Name

Description

31:0

Reserved

-

-

11. CLKCFG0: Clock Configuration Register 0 (offset: 0x002C)
Bits
Type
Name
Description

0x0

Initial Value
0x0

Initial Value

31:30

RW

SDRAM_CLK_SKEW

SDRAM Clock Skew
0: Zero delay
1: Delay 200 ps
2: Delay 400 ps
3: Delay 600 ps

0x1

29:24

RW

OSC_1US_DIV

Oscillator 1 μs Divider
Sets the maximum for the reference clock
counter for either a 20 MHz or 40 MHz external
XTAL input. The count increments each 1 μsec
(indicating 1 MHz), up to the maximum, before
resetting to zero. This counts the frequency of
an external XTAL. This count is used to output a
32 KHz frequency to the REFCLK0 pin.
6’b0: Automatically generates a 1 μs system tick
regardless of whether XTAL frequency is 20
MHz or 40 MHz.
6’d39: Default value for an external 40 MHz
XTAL.
6’d19: Default value for an external 20 MHz
XTAL.
Others: Manual mode for tick generation.

0x0

23

-

-

Reserved

0x0

22:18

RW

INT_CLK_FDIV

Internal Clock Frequency Divider
The frequency divider used to generate the
Fraction-N clock frequency.
Valid values range from 1 to 31.
Fraction-N clock frequency =
(INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ

0x8

17

-

-

Reserved

0x0

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Name

Description

RW

INT_CLK_FFRAC

Internal Clock Fraction-N Frequency
A parameter used in conjunction with
INT_CLK_FDIV to generate the Fraction-N clock
frequency.
Valid values range from 0 to 31.
Fraction-N clock Frequency =
(INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ

0x0

11:9

RW

REFCLK0_RATE

Reference Clock 0 Rate
0: Xtal clock 20/40 MHz
1: 12 MHz
2: 25 MHz
3: 40 MHz
4: 48 MHz
5: Internal Fraction-N_CLK/2
6: Reserved
7: CPLL_DIV8

0x0

8

-

-

Reserved

0x0

7:5

-

-

Reserved

0x0

4

RW

PERI_CLK_SEL

Peripheral Clock Source Select
Sets the peripheral clock to use the 20/40 MHz
frequency input from XTAL.
0: 40 MHz from 480 MHz divided by 12.
1: 20 MHz/40M Hz from XTAL input

0x0

3

RW

EPHY_USE_25M

EPHY Clock Source Select
Set the EPHY clock to use the 25 MHz frequency
input from the PPLL.
0: EPHY use 20/40 MHz from XTAL
1: EPHY use 25 MHz from PPLL

0x0

2

-

-

Reserved

0x0

1:0

-

-

Reserved

0x0

16:12

Type

12. CLKCFG1: Clock Configuration Register 1 (offset: 0x0030)
Bits
Type
Name
Description

Initial Value

Initial Value

31

-

-

Reserved

0x0

30

RW

SDHC_CLK_EN

SDHC clock enable

0x1

29

-

-

Reserved

0x1

28

RW

AUX_STCK_ CLK_EN

Aux system tick clock enable

0x1

27

-

-

Reserved

0x0

26

RW

PCIE0_ CLK_EN

PCIE0 clock enable

0x1

25

RW

UPHY0_ CLK_EN

UPHY0 clock enable

0x1

24

-

-

Reserved

0x1

23

RW

ESW_ CLK_EN

Ethernet switch clock enable

0x1

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

22

-

-

Reserved

0x1

21

RW

FE_ CLK_EN

FE clock enable

0x1

20

-

-

Reserved

0x0

19

RW

UARTL_ CLK_EN

UART Lite clock enable

0x1

18

RW

SPI CLK_EN

SPI clock enable

0x1

17

RW

I2S CLK_EN

I2S clock enable

0x1

16

RW

I2C CLK_EN

I2C clock enable

0x1

15

RW

NAND_CLK_EN

Nand flash control clock enable

0x1

14

RW

GDMA CLK_EN

GDMA clock enable

0x1

13

RW

PIO CLK_EN

GPIO controller clock enable

0x1

12

RW

UART_ CLK_EN

UART clock enable

0x1

11

RW

PCM_ CLK_EN

PCM clock enable

0x1

10

RW

MC_ CLK_EN

Memory controller clock enable

0x1

9

RW

INTC_ CLK_EN

Interrupt controller clock enable

0x1

8

RW

TIMER_CLK_EN

Timer clock enable

0x1

7

RW

GE2_CLK_EN

GE2 controller clock enable.

0x1

6

RW

GE1_CLK_EN

GE1 controller clock enable.

0x1

Reserved

0x0

5:0
NOTE:
0: Clock is gated.
1: Clock is enabled.

13. RSTCTRL: Reset Control Register (offset: 0x0034)
Bits
Type
Name
Description

Initial Value

Initial Value

31

RW

PPE_RST

Resets PPE

0x0

30

RW

SDHC_RST

Resets SD Controller.

0x0

29

-

-

Reserved

0x0

28

RW

MIPS_CNT_RST

Resets MIPS counter block.

0x0

27

-

-

Reserved

0x0

26

RW

PCIE0_RST

Resets PCIE Host Bridge, PCIE0 Controller and
PHY.

0x0

25

RW

UHST0_RST

Resets USB PHY0.
NOTE: USB Host controller will be reset when
both UHST0_RST and UHST1_RST are set.

0x0

24

RW

EPHY_RST

Resets the Ethernet PHY block.

0x0

23

RW

ESW_RST

Resets the Ethernet switch block.

0x0

22

-

-

Reserved

0x0

21

RW

FE_RST

Resets the Frame Engine block.

0x0

20

RW

WLAN_RST-

Resets the WLAN block.

0x0

19

RW

UARTL_RST

Resets the UART Lite block.

0x0

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MT7620 PROGRAMMING GUIDE
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Bits

Type

Name

Description

18

RW

SPI

Resets the SPI block.

17

RW

I2S

Initial Value
0x0

2

0x0

2

Resets the I S block.

16

RW

I2C

Resets the I C block.

0x0

15

RW

NAND

Resets the NAND block.

0x0

14

RW

DMA

Resets the DMA block.

0x0

13

RW

PIO

Resets the PIO block.

0x0

12

RW

UART_RST

Resets the UART block.

0x0

11

RW

PCM_RST

Resets the PCM block.

0x0

10

RW

MC_RST

Resets the Memory Controller block.

0x1

9

RW

INTC_RST

Resets the Interrupt Controller block.

0x0

8

RW

TIMER_RST

Resets the Timer block.

0x0

7:1

-

-

Reserved

0x0

Resets the whole SoC.

0x0

0
W1C
SYS_RST
NOTE:
0: Deassert reset
1: Reset

14. RSTSTAT: Reset Status Register (offset: 0x0038)
Bits
Type
Name
Description

Initial Value

31

RW

WDT2SYSRST_EN

Watchdog Timeout To System Reset Enable
Enables watchdog timeout to trigger a system
reset.
0: Disable
1: Enable

0x1

30

RW

WDT2RSTO_EN

Watchdog Timeout to Reset Output Enable
Enables watchdog timeout to trigger the reset
output pin.
0: Disable
1: Enable

0x1

29:16

RW

WDTRSTPD

Watchdog Reset Output Low Period
Controls the WDT reset output low period. For
example:
If the pin share mode was set correctly and
WDT2RSTO_EN=1,
 When WDTRSTPD= 0, you can see duration
of 1 μs low on the WDT reset output pin.
 When WDTRSTPD= 3, you can see duration
of 4 μs low on the WDT reset output pin.
(unit: 1 μs)

0x3

15:4

-

-

Reserved

0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

3

R/W1C

SWCPURST

Software CPU Reset
Indicates when software has reset the CPU by
writing to the RSTCPU bit in RSTCTL.
0: Has no effect.
1: Clears this bit.
NOTE: This register is reset only by a power-on
reset.

0x0

2

R/W1C

SWSYSRST

Software System Reset
Indicates when software has reset the chip by
writing to the RSTSYS bit in RSTCTL.
0: Has no effect.
1: Clears this bit.
NOTE: This register is reset only by a power on
reset.

0x0

1

R/W1C

WDRST

Watchdog Reset
Indicates when the watchdog timer has reset
the chip.
0: Has no effect.
1: Clears this bit.
NOTE: This register is reset only by power-on
reset.

0x0

0

-

-

Reserved

0x0

15. CPU_SYS_CLKCFG: CPU and SYS Clock Control (offset: 0x003C)
Bits
Type
Name
Description

Initial Value

Initial Value

31:20

-

-

Reserved

0x0

19:16

RW

CPU_OCP_RATIO

CPU OCP Ratio
The ratio between the system bus frequency
and the CPU frequency.
Value
Ratio (SYS : CPU )
4’d0
1 : 1 (Reserved)
4’d1
1 : 1.5 (Reserved)
4’d2
1:2
4’d3
1 : 2.5 (Reserved)
4’d4
1:3
4’d5
1 : 3.5 (Reserved)
4’d6
1:4
4’d7
1:5
4’d8
1 : 10
Others
Reserved
NOTE: If the chip runs in USB OHCI mode, the
OCP frequency cannot be lower than 30 MHz. It
means that
PLL_FREQ*(CPU_FFRAC/CPU_FDIV)/(CPU_OCP_
RATIO+1) >= 30 MHz.

0x4

15:13

-

-

Reserved

0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

12:8

RW

CPU_FDIV

CPU Frequency Divider
The frequency divider is used to generate the
CPU frequency. The value must be larger than
or equal to CPU_FFRAC. Valid values range from
1 to 31.

Initial Value
0xA

7:5

-

-

Reserved

0x0

4:0

RW

CPU_FFRAC

CPU Frequency Fractional
A parameter used in conjunction with the CPU
frequency divider to determine the CPU
frequency. Input a value in the following
equation to determine the CPU frequency.
Valid values range from 0 to 31.
CPU frequency =
(CPU_FFRAC/CPU_FDIV)*PLL_FREQ
NOTE: If the chip runs in USB OHCI mode, the
OCP frequency cannot be lower than 30 MHz. It
means that
PLL_FREQ*(CPU_FFRAC/CPU_FDIV)/(CPU_OCP_
RATIO+1) >= 30 MHz.

0x1

NOTE:
1. Equation used to derive system frequency after chip boot up:
PLL_FREQ = 600
CPU_FREQ = PLL_FREQ * (CPU_FFRAC / CPU_FDIV).
BUS_FREQ = CPU_FREQ/3. (CPU_OCP_RATIO = 1:3)
Limitations:
CPU_FDIV >= CPU_FFRAC.
2.

If the chip runs the USB function, the OCP frequency cannot be lower than 30 MHz. Then PLL_FREQ
follows this limitation.
BUS_FREQ >= 30 MHz.

3.

Example:
PLL_FREQ
CPU_FREQ
BUS_FREQ

= 600 MHz.
= 600 * (1/5) = 300 MHz. (CPU_FFRAC=1; CPU_FDIV=5)
= 300/3 = 100 MHz. (CPU_OCP_RATIO=1:3)

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

16. CLK_LUT_CFG: CPU and SYS Clock Auto Control (offset: 0x0040)
Bits
Type
Name
Description

Initial Value

31

RW

SLP_EN

Sleep Mode Enable
Enables sleep mode when MIPS SI_Sleep is
asserted.
0: Disable
1: Enable
Sleep Mode CPU Frequency =
(1/CPU_FDIV)*PLL_FREQ

0x0

30

RW

STEP_EN

Step Jump Enable
Enables step jump after MIPS exits sleep mode.
The CPU will jump to the normal frequency in
increments defined by STEP_FFRAC.bit[4:0] of
this register.
0: Disable
1: Enable

0x0

29:28

-

-

Reserved

0x0

27:20

RW

STEP_CNT

Step Counter
Sets the period of each step jump. When the
counter counts down to zero, the CPU clock
automatically changes to the next step
frequency.
The count period unit is 1 μs.

0x2

19:16

RW

SLP_OCP_RATIO

Sleep Mode CPU and System Bus Frequency
Ratio
Sets the ratio between the system bus frequency
and the CPU frequency when entering sleep
mode. (SYS:CPU)
Value
Ratio (SYS : CPU )
4’d0
1:1
4’d1
1 : 1.5 (Reserved)
4’d2
1:2
4’d3
1 : 2.5 (Reserved)
4’d4
1:3
4’d5
1 : 3.5 (Reserved)
4’d6
1:4
4’d7
1:5
4’d8
1 : 10
Others Reserved

0x4

15:5

-

-

Reserved

0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

4:0

RW

STEP_FFRAC

Step Frequency Fraction
Sets the fractional size of the increment in CPU
frequency after the CPU exits from sleep mode
and returns to normal operation. This step is
only valid when SLP_STEP_EN is enabled.
FRAC_VALUE =
PREVIOUS_FRAC_VALUE + STEP_FFRAC
CPU Frequency =
(FRAC_VALUE/CPU_FDIV)*PLL_FREQ

17. CUR_CLK_STS: Current Clock Status (offset: 0x0044)
Bits
Type
Name
Description

Initial Value
0x6

Initial Value

31:21

-

-

Reserved

20

RO

SAME_FREQ

Indicates that the SYS and DRAM clocks are on
the same frequency.
0: False
1: True

-

19:16

RO

CUR_OCP_RATIO

Current CPU_OCP_Ratio (SYS : CPU)
Shows the current ratio between the system bus
and CPU frequencies.
Value
Ratio (SYS : CPU )
4’d0
1:1
4’d1
1 : 1.5 (Reserved)
4’d2
1:2
4’d3
1 : 2.5 (Reserved)
4’d4
1:3
4’d5
1 : 3.5 (Reserved)
4’d6
1:4
4’d7
1:5
4’d8
1 : 10
Others Reserved

-

15:13

-

-

Reserved

0x0

12:8

RO

CUR_CPU_FDIV

Current CPU Frequency Divider
The frequency divider is used to generate the
CPU frequency.
For more information, see CPU_SYS_CLKCFG,
offset 0x003C, bit[12:8].

0xA

7:5

-

-

Reserved

0x0

4:0

RO

CUR_CPU_FFRAC

Current CPU Frequency Fraction
A parameter used in conjunction with the CPU
frequency divider to determine the CPU
frequency.
For more information, see CPU_SYS_CLKCFG,
offset 0x003C, bit[4:0].

0x1

PGMT7620_V.1.0_040503

0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

18. BPLL_CFG0: BB PLL Configuration 0 (offset: 0x0048)
Bits
Type
Name
Description

Initial Value

31

RW

BPLL_SW_CFG

BB PLL Software Configuration
Sets BB PLL parameters set by software.
0: Apply default parameters set by hardware.
1: Apply new parameters set by software in
BPLL_CFG0 & BPLL_CFG1.

0x0

30:23

-

-

Reserved

0x0

22:20

RW

BBPL_OPTION

Reserved

0x0

19:17

-

-

Reserved

0x0

16

RW

BBPL_PD

BB PLL Power Down
0: Power On
1: Power Down

0x0

15:14

-

-

Reserved

0x0

13

RO

BBPL_FBDV2

BB PLL Feedback Divisor 2
This value depends on the bootstrap pin.
<0x0>: 40 MHz
<0x1>: 20 MHz

BS

12

RW

BBPL_FOUTDV2

BB PLL Frequency Output Divisor 2
0: Fixed at 960 MHz

0x0

11:8

RW

BBPL_RDV

BB PLL Reference Input Divisor
divisor: M=RDV[3:0])

0x1

7:4

RW

BBPL_FDV

BB PLL Feedback Divisor Control
Sets the real feedback divisor (N) based on the
value of BBPL_FBDV2 (bit13).
 If FBDV2=0, N=FDV[3:0]+16
 If FBDV2=1, N=2*(FDV[3:0]+16)

0x8

3:0

RW

BBPL_ODV

FOUT Frequency Control
Sets the real output divisor (P) based on the
value of BBPL_FOUTDIV2 (bit12).
 If FOUTDV2=0, P=ODV[3:0]
 If FOUTDV2=1, P=ODV[3:0]*2
NOTE: In this chip ODV[3:0]=0000, so FOUT=0.

0x1

19. BPLL_CFG1: BB PLL Configuration 0 (offset: 0x004C)
Bits
Type
Name
Description
31

-

-

Reserved

30

RO

BBPL_OK

Lock-detector state
0: Not locked
1: Locked

PGMT7620_V.1.0_040503

Initial Value
0x0
-

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

29:28

RW

BBPL_ICPP

PLL CPP current control
Sets the proportional charge pump current.
(Default: 01)
00: 25 μA
10: 75 μA
01: 50 μA
11: 100 μA

0x1

PLL CPI current control
Sets the integral charge pump current.
00: 1.25 μA
10: 3.75 μA
01: 2.5 μA
11: 5 μA

0x1

PLL I-path initial voltage
00: Reserved
10: 600 mV
01: 500 mV
11: 700 mV

0x2

PLL bypass mode for testing
0: Normal mode
1: Bypass mode

0x0

Bandgap output test current selection
01: Pass bandgap PMOS current to output
10: Pass bandgap NMOS current to output
11: Reserved

0x0

FTEST frequency control
Sets the FTEST frequency based on the value of
BBPL_FTESTDV2 (bit16).
 If FTESTDV2=0,
divisor=OTDV[3:0], OTDV[3:0]=0001, FTEST=0
 If FTESTDV2=1,
divisor=OTDV[3:0]*2, OTDV[3:0]=0001,
FTEST=0
NOTE: In this chip OTDV[3:0]=0000, so FTEST=0.

0x0

0x1

27:26

25:24

23

22:21

20:17

RW

RW

RW

RW

RW

BBPL_ICPI

BBPL_VCS

BBPL_BP

BBPL_TESTSEL

BBPL_OTDV

16

RW

BBPL_FTESTDV2

FTEST Divisor 2
Used in bit[20:17] to calculate FTEST frequency.

15

RW

BBPL_FOKTH

Lock Detection FOUT Threshold Selection
0: Freq. window < +/- 3.2%
1: Disable (BBPL_OK=1)

14:13

RW

BBPL_TSTT

The time AFC waits until BIAS is ready
00: 5 μs
10: 20 μs
01: 10 μs
11: 40 μs

PGMT7620_V.1.0_040503

Initial Value

0x0

0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

12:11

RW

BBPL_TLCK

BB PLL Time Lock
The delay from when AFC is ready to when PLL
starts locking.
00: 5 μs
10: 20 μs
01: 10 μs
11: 40 μs

0x0

Force PLL open loop
0: Close loop
1: Open loop

0x0

BB PLL Automatic Frequency Calibration
VCO band selection/output code[8:0]
0xxxxxxxxx: Normal
1xxxxxxxxx: Manual set
When read, BBPL_AFC[8:0] is the output code
from BBPL macro

0x0

10

9:0

RW

RW

BBPL_FORCE

BBPL_AFC

20. CPLL_CFG0: CPU PLL Configuration 0 (offset: 0x0054)
Bits
Type
Name
Description

Initial Value

Initial Value

31

RW

CPLL_SW_CFG

CPU PLL Software Configuration
Sets CPU PLL parameters set by software.
0: Apply default parameters set by hardware.
1: Apply new parameters set by software in
CPLL_CFG0[25:0], CPLL_CFG1[9:0] and [26].

0x0

30:25

-

-

Reserved

0x0

24

RW

OPEN_LOOP

Force PLL Open Loop
Forces PLL to operate in open loop mode.
0: Closed loop
1: Open loop

0x0

23:22

RW

AFC_WAIT_TIME

Automatic Frequency Calibration (AFC) Wait
Time
The time AFC waits until BIAS is ready.
00: 5 μs
01: 10 μs
10: 20 μs
11: 40 μs

0x0

21:20

RW

PLL_LOCK_TIME

PLL Lock Time
The delay from when AFC is ready to when PLL
starts locking.
00: 5 μs
01: 10 μs
10: 20 μs
11: 40 μs

0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

19

RW

EC_CUPLLOK

CPU Lock OK
0: Check AFC. After AFC, if Fvco is within ± 3.2% of
the target value, this bit is set to 1.
1: Set this bit to always indicate CPU Lock status
is OK, and disable the AFC check.

0x0

18:16

RW

PLL_MULT_RATIO

PLL Multiplying Ratio
Sets the ratio between the VCO and reference
clock frequencies.
 When LC_CURFCK = 0:
Factor=1
PLL_MULT_RATIO =
FVCO / FREF(40 MHZ)/ Factor
 When LC_CURFCK = 1:
Factor=2
PLL_MULT_RATIO =
FVCO / FREF(20 MHZ)/ Factor
where
FVCO = VCO frequency
FREF = Reference clock frequency
000: 24
001: 25
010: 26
011: 27
100: 28
101: 29
110: 30 (default)
111: 31 (test only)

0x6

15

RW

LC_CURFCK

PLL Input Frequency Source
0: 40 MHz
1: 20 MHz

BS

14

RW

BYPASS_REF_CLK

Bypass Reference Clock
0: Normal
1: Bypass

0x0

13:12

RW

IPATH_INI_VAL

I-path Initial Voltage
00: Reserved
01: 500 mV
10: 600 mV (default)
11: 700 mV

0x2

PGMT7620_V.1.0_040503

Initial Value

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

11:10

RW

PLL_DIV_RATIO

PLL Dividing Ratio
Sets the ratio between the VCO and PLL output
frequency.
PLL_DIV_RATIO = FVCO/FOUT.
where
FVCO = VCO frequency
FOUT = PLL output frequency
00: 2 (default)
01: 3
10: 4
11: 8

0x0

9:8

RW

SSC_UP_BOUND

Spread Spectrum Clock (SSC) Frequency Upper
Boundary
00: 0 (default)
01: 1/4 SSC swing
10: 2/4 SSC swing
11: 3/4 SSC swing

0x0

7

RW

SSC_EN

Spread Spectrum Clock (SSC) Enable
Enables the spread spectrum clock (SSC) to
reduce EMI and improve SNR.
0: Disable (default)
1: Enable

0x0

6:4

RW

SSC_SWING

SSC Swing
000: 1250 ppm
001: 2500 ppm
010: 3750 ppm
011: 5000 ppm
100: 6250 ppm
101: 7500 ppm
110: 8750 ppm
111: 10000 ppm (default)

0x7

3:2

RW

INT_PATH_OPT

Integration Path Option
00: 1.25 μA (default)
01: 2.5 μA
10: 3.75 μA
11: 5 μA

0x0

1:0

RW

PRO_PATH_OPT

Proportional Path Option
00: 25 μA
01: 50 μA (default)
10: 75 μA
11: 100 μA

0x1

PGMT7620_V.1.0_040503

Description

Initial Value

Page 35 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

21. CPLL_CFG1: CPU PLL Configuration 1 (offset: 0x0058)
Bits
Type
Name
Description

Initial Value

31:27

-

-

Reserved

0x0

26

RW

CPLL_PD

CPU PLL Power Down
0: Power on
1: Power down

0x0

25

RW

CPU_CLK_AUX1

CPU Clock Source Select
Selects CPU source clock from aux0 or Xtal_IN
pins.
0: From aux0
1: From Xtal_IN

0x0

24

RW

CPU_CLK_AUX0

CPU Clock Auxiliary 0 Enable
Selects CPU source clock from temporary 480
Mhz clock.
0: Disable
1: Enable

0x0

23

RO

CPLL_LD

CPLL Lock
0: Unlock
1: Lock

22:14

RO

EC_CUAFCOUT

CPU PLL AFC output code

0x0

13:10

RO

EC_CUPHDRFT

SSCG output code
(two’s complement)

0x0

9:0

RW

FR_CUAFCSET

CPU PLL AFC Set
0xxxxxxxxx: Normal
1xxxxxxxxx: Manual set

0x0

22. USB_PHY_CFG: USB PHY Control (offset: 0x005C)
Bits
Type
Name
Description

-

Initial Value

31:2

-

-

Reserved

0x0

1

RW

UTMI_8B60M

USB UTMI 8-bit 60 Mhz Mode Select
Sets the operation mode of the UTMI interface.
0: 16-bit 30 Mhz mode
1: 8-bit 60 Mhz mode

0x0

0

RW

UDEV_WAKEUP

USB Device Wakeup
Enables remote wakeup of the USB device.
0: Disable
1: Enable

0x0

23. GPIOMODE: GPIO Purpose Select (offset: 0x0060)
Bits
Type
Name
Description

PGMT7620_V.1.0_040503

Initial Value

Page 36 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

31:30

RW

SUTIF_SHARE_MODE

Serial UTIF Pin Share Mode
Sets the serial UTIF pin to operate in UARTL or
2
I C mode.
0: Not shared
1: Shared with UARTL -overwrites the
UARTLITE_GPIO_MODE setting.
2
2: Shared with I C - overwrites the
I2C_GPIO_MODE setting.
3: Reserved

0x0

29:23

-

-

Reserved

0x0

22:21

RW

WDT_RST_MODE

Watchdog Timer GPIO Share Mode
Sets the watchdog timer reset pin to operate in
REFCLK_OUT or GPIO mode.
0: WDT_RST_N (normal mode)
1: REFCLK0_OUT
2: GPIO mode
3: Reserved

0x0

20

RW

PA_G_GPIO_MODE

Power Amplifier GPIO Share Mode
Sets the power amplifier pin to operate in GPIO
mode.
0: PA_PE_G0/PA_PE_G1/ANT_TRN/ANT_TRNB
(normal mode)
1: GPIO Mode

0x1

19:18

RW

ND_SD_GPIO_MODE

NAND/SD GPIO Share Mode
Sets the ND pins to operate in SD, BT or GPIO
mode.
0: ND Mode
1: SD Mode (BT Coexist)
2: GPIO Mode
3: Reserved

0x2

17:16

RW

PERST_GPIO_MODE

PCIe Reset GPIO Share Mode
Sets the PERST_N pin to operate in REFCLK0 or
GPIO mode.
2’b00: PERST_N (normal mode)
2’b01: REFCLK0_OUT
2’b10: GPIO mode
2’b11: Reserved

0x2

15

RW

EPHY_LED_GPIO _MODE

LED JTAG GPIO Share Mode
Sets an LED pin to operate in JTAG or GPIO
mode.
0: Normal Mode (JTAG/EPHY_LED depending on
bootstrapping settings)
1: GPIO Mode

0x0

14

-

-

Reserved

0x0

PGMT7620_V.1.0_040503

Initial Value

Page 37 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

13

RW

WLED_GPIO_MODE

WLAN LED GPIO Share Mode
Sets the WLAN LED pin to operate in GPIO
mode.
0: Normal mode
1: GPIO Mode

0x1

12

RW

SPI_REFCLK0_MODE

SPI Reference Clock GPO Share Mode
Sets SPI pins to operate in reference clock and
GPO mode.
0: Normal SPI mode
1: SPI_CS1 pins are shared with the reference
clock and GPO mode.

0x1

11

RW

SPI_GPIO_MODE

SPI GPIO Share Mode
Sets the SPI pins to operate in GPIO mode.
0: Normal Mode
1: GPIO Mode

0x0

10

RW

RGMII2_GPIO_MODE

RGMII2 GPIO Share Mode
Sets the RGMII2 pins to operate in GPIO mode.
0: Normal Mode
1: GPIO Mode

0x1

9

RW

RGMII1_GPIO_MODE

RGMII1 GPIO Share Mode
Sets the RGMII1 pins to operate in GPIO mode.
0: Normal Mode
1: GPIO Mode

0x1

8:7

RW

MDIO_GPIO_MODE

MDIO GPIO Share Mode
Sets the MDIO pin to operate in GPIO mode.
2’b00: Normal Mode
2’b01: REF_CLK Mode
2’b10: GPIO Mode
2’b11: Reserved

0x2

6

-

-

Reserved

0x0

5

RW

UARTL_GPIO_MODE

UART Lite GPIO Share Mode
Sets the UART Lite pins to operate in GPIO
mode.
0: Normal Mode
1: GPIO Mode

0x1

4:2

RW

UARTF_SHARE_MODE

UART Full Interface Share Mode
Sets the UART Full interface to operate in PCM,
I2S, and GPIO mode.
A detailed description of the UARTF Mode Pin
Sharing scheme is shown in the datasheet for
this chip.

0x7

1

-

-

Reserved

0x0

0

RW

I2C_GPIO_MODE

I2C GPIO Share Mode
Sets the I2C pins to operate in GPIO mode.
0: Normal Mode
1: GPIO Mode

0x1

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

NOTE: For more information on pin sharing schemes, see the datasheet for this chip.
24. PCIPDMA_STAT: Control and Status of PDMA in PCIe Device (offset: 0x0064)
Bits
Type
Name
Description

Initial Value

31:4

-

-

Reserved

0x0

3

RW

PCIPDMA_RX_EN

PDMA Rx DMA Enable
In iNIC applications, the external Host can
enable the PDMA of a PCIe Device to start Rx
PDMA (from the point of view of the external
host).
However, the actual PDMA Rx is enabled when
both of following conditions are met.
 MIPS (internal CPU) writes 1 to
PCIPDMA_RX_EN.
 External Host writes 1 to RX_DMA_EN via
BAR1.

0x0

2

RW

PCIPDMA_TX_EN

PDMA Tx DMA Enable
In iNIC applications, the external Host can
enable the PDMA of a PCIe Device to start Tx
PDMA (from the point of view of the external
host).
However, the actual PDMA Tx is enabled when
both of following conditions are met.
 MIPS (internal CPU) writes 1 to
PCIPDMA_TX_EN.
 External Host writes 1 to TX_DMA_EN via
BAR1.

0x0

1

RO

PCIPDMA_RX_BUSY

PCIe PDMA Rx Busy
Indicates PDMA Rx in the PCIe device is busy.
0: PDMA Rx is idle
1: PDMA Rx is busy

0x0

0

RO

PCIPDMA_TX_BUSY

Indicates PDMA Tx in the PCIe device is busy.
0: PDMA Tx is idle
1: PDMA Tx is busy

0x0

25. PMU0_CFG: (offset: 0x0088)
Bits
Type
Name

Description

31:29

-

-

Reserved

0x0

28

RW

PMU_SW_SET

PMU Software Register Set
0: Set hardware to control the PMU software
register.
1: Set software to control the software register
field [24:16]

0x0

24

RW

A_DCDC_EN

SW Analog DC/DC Converter Enable
0: Disable
1: Enable

0x1

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Bits

Type

Name

Description

23:20

-

-

Reserved

0x0

19

RW

A_SSCPERI

Analog Spread Spectrum Clock Generator
(SSCG) Modulation Period Select
0: 16.5 kHz
1: 33 kHz

0x1

18

RW

A_SSCGEN

Analog Spread Spectrum Clock Generator
Enable
0: Disable
1: Enable

0x1

17:16

RW

A_SSC

Analog Spread Spectrum Clock Control
Increases the SSCG modulation frequency from
a base level of 1 MHz.
<0x0>: ± 5%
<0x1>: Reserved
<0x2>: ± 10%
<0x3>: ± 20%

0x2

15:11

-

-

Reserved

0x0

10:8

RW

A_DLY

Analog Delay
Controls the output power MOSFET dead zone.
Sets the turn off/delay period between the
external upper and lower MOSFET. The periods
given below are approximate as the exact value
depends on the production process for each
chip, the input voltage, and the chip
temperature.
<0x1>: Approx. 40 nsec
<0x2>: Approx. 30 nsec
<0x3:> Approx. 20 nsec
<0x4:> Approx. 10 nsec

0x2

7:0

RW

A_VTUNE

Analog Voltage Tune
Sets the output voltage level.
<0x51>: 0.76 V (min)
…
<0xB9>: 1.75 V - 20 mv
<0xBA>: 1.75 V - 10 mv
<0xBB>: 1.75 V (default)
<0xBC>: 1.75 V + 10 mv
<0xBD>: 1.75 V + 20 mv
…
<0xFF> : 2.4 V (max)

0xBB

26. PMU1_CFG: (offset: 0x008C)
Bits
Type
Name

Description

31:30

Reserved

-

-

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Initial Value
-

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MT7620 PROGRAMMING GUIDE
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Bits

Type

Name

Description

29:28

RW

DIG_LDO_GAIN

DIG_LDO gain control
00: High DC gain
00: Reserved
10: Reserved
11: Low DC gain

27:26

-

-

Reserved

25

RW

DIG_SW_SEL

SW Configured Digital LDO output level
0: HW controlled DIG LDO
1: SW controlled DIG LDO field [24:16]

0x0

24

RW

DIG_LDO_EN

DIG LDO Enable
0: Disable
1: Enable

0x1

23:16

RW

DIG_LDO_VALUE

LDO Output Level Selection

0x69

15:14

-

-

Reserved

13:12

RW

DDR_LDO_Gain

DDR LDO gain control
00: High DC gain
00: Reserved
10: Reserved
11: Low DC gain

11:10

-

-

Reserved

9

RW

DDR_SW_SEL

SW Config DDR LDO Output Level
0: HW control DDR LDO (based on bootstrap
value)
1: SW control DDR LDO field [8:0]

0x0

8

RW

DDR_LDO_EN

DDR LDO Enable
0: Disable
1: Enable

0x1

7:0

RW

DDR_LDO_VALUE

LDO Output Level Selection
default:
<10011011> for output=1.8 V (DDR2)
<11010101> for output=2.5 V (DDR1)

BS

27. PPLL_CFG0: PCIe PLL Configuration 0 (offset: 0x0098)
Bits
Type
Name
Description

Initial Value
0x0

-

0x0

-

Initial Value

31

RW

PPLL_SW_SET

Progammable PLL Software Set
0: HW sets default PLL parameters
1: SW applies new parameters with
PPLL_CFG0[23:0] & PPLL_CFG1[9:0] &
PPLL_CFG1[26]

0x0

30:24

-

-

Reserved

0x0

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MT7620 PROGRAMMING GUIDE
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Bits

Type

Name

Description

23:22

RW

AFC_WAIT_TIME

Automatic Frequency Control (AFC) Wait Time
The time AFC waits until BIAS is ready.
00: 5 μs
01: 10 μs
10: 20 μs
11: 40 μs

0x0

21:20

RW

PLL_LOCK_TIME

PLL Lock Time
The time PLL starts to lock after AFC is ready.
00: 5 μs
01: 10 μs
10: 20 μs
11: 40 μs

0x0

19

RW

EC_PEPLLOK

PCIe PLL Lock OK
0: Check AFC. After AFC, if Fvco is within ± 3.2%
of the target value, this bit is set to 1.
1: Set this bit to always indicate CPU Lock status
is OK, and disable the AFC check.

0x0

18:17

-

-

Reserved

0x0

16

RW

OPEN_LOOP

PLL Open Loop
Forces PLL to operate in open loop mode.
0: Close loop
1: Open loop

0x0

15

RW

LC_PERFCK

(Logic side Code) PCIe Reference Clock
Frequency Source
0: 40 MHz
1: 20 MHz

BS

14

RW

BYPASS_REF_CLK

Bypass Reference Clock
0: Normal
1: Bypass

0x0

13:12

RW

IPATH_INI_VAL

I-path Initial Voltage
00: Reserved
01: 500 mV
10: 600 mV (default)
11: 700 mV

0x2

11:10

RW

PLL_OUT_FREQ

Output Clock Frequency
00: 50 MHz (test only)
01: 100 MHz (default)
10: 200 MHz (test only)
11: 600 MHz (test only)

0x1

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MT7620 PROGRAMMING GUIDE
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Bits

Type

Name

Description

9:8

RW

SSC_UP_BOUND

Spread Spectrum Clock (SSC) Frequency Upper
Boundary
00: 0 (default)
01: 1/4 SSC swing
10: 2/4 SSC swing
11: 3/4 SSC swing

0x0

7

RW

SSC_EN

SSC Enable
Enables the spread spectrum clock (SSC) to
reduce EMI and improve SNR.
0: Disable (default)
1: Enable

0x0

6:4

RW

SSC_SWING

SSC Swing
000: 1250 ppm
001: 2500 ppm
010: 3750 ppm
011: 5000 ppm
100: 6250 ppm
101: 7500 ppm
110: 8750 ppm
111: 10000 ppm (default)

0x3

3:2

RW

INT_PATH_OPT

Integration Path Option
00: 1.25 μA (default)
01: 2.5 μA
10: 3.75 μA
11: 5 μA

0x0

1:0

RW

PRO_PATH_OPT

Proportional Path Option
00: 25 μA
01: 50 μA (default)
10: 75 μA
11: 100 μA

0x1

28. PPLL_CFG1: PCIe PLL Configuration 1 (offset: 0x009C)
Bits
Type
Name
Description

Initial Value

Initial Value

31:27

-

-

Reserved

0x0

26

RW

PPLL_PD

PPLL Power Down
0: Power On
1: Power down

0x0

25:24

-

-

Reserved

0x0

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MT7620 PROGRAMMING GUIDE
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Bits

Type

Name

Description

23

RO

PPLL_LD

PPLL Lock
0: Unlock
1: Lock

22:14

RO

EC_PEAFCOUT

PCIe PLL AFC output

0x0

13:10

RO

EC_PEPHDRFT

PCIe PLL Phase Drift
SSCG output code
(two’s complement)

0x0

9:0

RW

FR_PEAFCSET

PCIe PLL AFC Set
0xxxxxxxxx: Normal
1xxxxxxxxx: Manual set

0x0

29. PPLL_DRV: PCIe Driver Configuration (offset: 0x00A0)
Bits
Type
Name
Description

Initial Value
-

Initial Value

31

RW

PDRV_SW_SET

PCIe Driver Software Set
0: HW sets default parameters
1: SW configures values for [19:0] in this
register.

0x0

30:20

-

-

Reserved

0x0

19

RW

LC_CKDRVPD

(Logic side Code) PCIe Clock Driver Power Down
(Low Active)
0: Power Down
1: Power On

0x0

18

RW

LC_CKDRVOHZ

(Logic side Code) Reference PCIe Output Clock
Mode Enable
0: Enable output clock (Host mode only)
1: High Impedence (Device mode)

0x1

17

RW

LC_CKDRVHZ

(Logic side Code) PCIe PHY Clock Enable
0: Enable clock (Host mode only)
1: High Impedence (Device mode)

0x1

16

RW

LC_CKTEST

(Logic side Code) Single-ended clock for output
testing
0: Normal operation
1: Testing only

0x0

15:0

RW

FR_CKDRVHZ

PCIe Clock Driver Set
(default 0000-0101-0000-0100)
See NOTE below.

0x0504

NOTE: [15:0] bit values are as follows.
Bits
Description
15:13

Reserved

12

Input clock selection
Value Description
0
From PEPLL
1
From LC_CKTEST

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MT7620 PROGRAMMING GUIDE
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Bits

Description

11:10

Output voltage level
Value Description
00
0.7 V
10
0.8 V
01
0.75 V
11
0.85 V

9

Reserved

8:4

Output termination adjustment
Value Description Value Description
00000
70
01010
52
00001
66
01011
51
00010
64
01100
50
00011
62
01101
49
00100
61
01110
48
00101
59
01111
47
00110
58
10000
46
00111
56
10001
45
01000
55
10010
44
01001
54
10011
43
10100
42

3:2

Output slew-rate control
Value Description
00
1.71 V/ns
01
1.12 V/ns
10
0.78 V/ns
11
0.6 V/ns

1:0

Reserved

PGMT7620_V.1.0_040503

Value
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Description
41
40
39
38.5
38
37.5
37
36.5
36
35.5
35

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MT7620 PROGRAMMING GUIDE
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2.3 Timer
2.3.1 Features
 Independent clock pre-scale for each timer.
 Independent interrupts for each timer.
 Two general-purpose timers which run at a 40 MHz clock rate. The other two run at a 32 kHz clock rate.
 Periodic mode
 Free-running mode
 Time-out mode
 Second timer may be used as a watchdog timer. Watchdog timer resets system on time-out.
 Timer Modes
 Periodic
In periodic mode, the timer counts down to zero from the load value. An interrupt is generated when the
count is zero. After reaching zero, the load value is reloaded into the timer and the timer counts down
again. A load value of zero disables the timer.
 Timeout
In timeout mode, the timer counts down to zero from the load value. An interrupt is generated when the
count is zero. In this mode, the ENABLE bit is reset when the timer reaches zero, stopping the
counter. After reaching zero, the load value is reloaded into the timer. A load value of zero disables the
timer.
 Free-running
In free-running mode, the timer counts down to zero from FFFFh. An interrupt is generated when the
count is zero. After reaching zero, FFFFh is reloaded into the timer. This mode is identical to the periodic
mode with a load value of 65535. It is worth noting that if firmware writes to the load value register in
this mode, the timer will still load that value even though that value will be ignored thereafter. Also note
that when the timer is first enabled, it will begin counting down from its current value, not necessarily
FFFFh.
 Watchdog
In watchdog mode, the timer counts down to zero from the load value. If the load value is not reloaded or
the timer is not disabled before the count is zero, the chip will be reset. When this occurs, every register
in the chip is reset except the watchdog reset status bit WDRST in the RSTSTAT register in the system
control block; it remains set to alert firmware of the timeout event when it re-executes its bootstrap.

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MT7620 PROGRAMMING GUIDE
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2.3.2 Block Diagram

Timer
Timer 0
Test Control

Load Value

Prescale

Counter

Mode Control

Clock
Reset

Timer 0 Interrupt
Timer 1 Interrupt
Interrupt
Control

Timer 1

Watchdog Timeout
Watchdog
Status

Load Value

Counter

Test Control

Prescale

Mode Control

PalmBus
Interface

PalmBus Signals

Figure 2-2 Timer Block Diagram

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MT7620 PROGRAMMING GUIDE
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2.3.3 List of Registers
No. Offset
Register Name

Description

Page

30

0x0000

TMRSTAT

Timer Status

49

31

0x0010

TMR0LOAD

Timer 0 Load Value

50

32

0x0014

TMR0VAL

Timer 0 Counter Value

50

33

0x0018

TMR0CTL

Timer 0 Control

50

34

0x0020

TMR1LOAD

Timer 1 Load Value

51

35

0x0024

TMR1VAL

Timer 1 Counter Value

51

36

0x0028

TMR1CTL

Timer 1 Control

51

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MT7620 PROGRAMMING GUIDE
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2.3.4 Register Descriptions (base: 0x1000_0100)
30. TMRSTAT: Timer Status Register (offset: 0x0000)
Bits
Type
Name
Description

Initial Value

31:6

-

-

Reserved

0x0

5

WO

TMR1RST

Timer 1 Reset
Read
Reading this bit returns a 0.
Write
0: No effect.
1: Reset Timer 1 to 0xFFFF if in free-running
mode, or to the value specified in the
TMR1LOAD register in all other modes.

0x0

4

WO

TMR0RST

Timer 0 Reset
Read
Reading this bit returns a 0.
Write
0: No effect.
1: Reset Timer 0 to 0xFFFF if in free-running
mode, or to the value specified in the
TMR0LOAD register in all other modes.

0x0

3:2

-

-

Reserved

0x0

1

R/W1C

TMR1INT

Timer 1 Interrupt Status
Indicates that timer 1 has expired and timer 1
interrupt to the processor has asserted. After
the interrupt is sent, the bit is written to 1 and
cleared.
Read
0: Not asserted.
1: Asserted.
Write
0: No effect
1: Clears the interrupt.

0x0

0

R/W1C

TMR0INT

Timer 0 Interrupt Status
Indicates that timer 0 has expired and timer 0
interrupt to the processor has asserted. After
the interrupt is sent, the bit is written to 1 and
cleared.
Read
0: Not asserted.
1: Asserted.
Write
0: No effect
1: Clears the interrupt.

0x0

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31. TMR0LOAD: Timer 0 Load Value (offset: 0x0010)
Bits
Type
Name
Description

Initial Value

31:16

RO

-

Reserved

0x0

15:0

RW

TMRLOAD

Timer Load Value
This register contains the load value for the
timer. In all modes, this value is loaded into the
timer counter when this register is written. In
all modes except free-running mode, this value
is reloaded into the timer counter after the
timer counter reaches 0. It may be updated at
any time; the new value will be written to the
counter immediately.
0: Disables the timer, except in free-running
mode.

0x0

32. TMR0VAL: Timer 0 Counter Value (offset: 0x0014)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RO

TMRVAL

Timer Counter Value
This register contains the current value of the
timer. During functional operation, writes have
no effect.

33. TMR0CTL: Timer 0 Control (offset: 0x0018)
Bits
Type
Name
Description

Initial Value
0x0
0xffff

Initial Value

31:16

-

-

Reserved

0x0

15

RW

TESTEN

Test Enable
Reserved for testing. This bit should be set to 0.

0x0

14:8

-

-

Reserved

0x0

7

RW

ENABLE

Timer Enable
Enables the 40 MHz timer0.
0: Disable the timer. The timer will stop
counting and will retain its current value.
1: Enable the timer. The timer will begin
counting from its current value.

0x0

6

-

-

Reserved

0x0

5:4

RW

MODE

Timer Mode
0: Free-running
1: Periodic
2: Time-out
3: Time-out

0x0

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Bits

Type

Name

Description

3:0

RW

PRESCALE

Timer Clock Pre-scale
These bits are used to scale the timer clock in
order to achieve higher resolution or longer
timer periods. Their definitions are below.
Value Timer Clock Frequency
0
System clock
1
System clock / 4
2
System clock / 8
3
System clock / 16
…
…
14
System clock / 32768
15
System clock / 65536

Initial Value
0x0

NOTE: The pre-scale value should not be
changed unless the timer is disabled.
34. TMR1LOAD: Timer 1 Load Value (offset: 0x0020)
Bits
Type
Name
Description

Initial Value

31:16

-

-

Reserved

0x0

15:0

RW

TMRLOAD

Timer Load Value
This register contains the load value for the
timer. In all modes, this value is loaded into the
timer counter when this register is written. In
all modes except free-running mode, this value
is reloaded into the timer counter after the
timer counter reaches 0. It may be updated at
any time; the new value will be written to the
counter immediately.
0: Disable the timer, except in free-running
mode.

0x0

35. TMR1VAL: Timer 1 Counter Value (offset: 0x0024)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RO

TMRVAL

Timer Counter Value
This register contains the current value of the
timer. During functional operation, writes have
no effect.

36. TMR1CTL: Timer 1 Control (offset: 0x0028)
Bits
Type
Name
Description

Initial Value
0x0
0xffff

Initial Value

31:16

-

-

Reserved

0x0

15

RW

TESTEN

Test Enable
Reserved for testing. This bit should be set to 0.

0x0

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Bits

Type

Name

Description

14:8

-

-

Reserved

Initial Value
0x0

7

RW

ENABLE

Timer Enable
Enables the 40 MHz timer1.
0: Disable the timer. The timer will stop
counting and will retain its current value.
1: Enable the timer. The timer will begin
counting from its current value.

0x0

6

RW

WD_TIMEOUT_SRC

Watchdog Timeout Alarm Source
0: From Timer 1
1: From PMU watch dog timer

0x0

5:4

RW

MODE

Timer Mode
0: Free-running
1: Periodic
2: Time-out
3: Watchdog

0x0

2:0

RW

PRESCALE

Timer Clock Pre-scale
These bits are used to scale the timer clock in
order to achieve higher resolution or longer
timer periods. Their definitions are below.
Value Timer Clock Frequency
0
System clock
1
System clock / 4
2
System clock / 8
3
System clock / 16
…
…
14
System clock / 32768
15
System clock / 65536

0x0

NOTE: The pre-scale value should not be
changed unless the timer is disabled.

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MT7620 PROGRAMMING GUIDE
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2.4 Interrupt Controller
2.4.1 Features
 Supports a central point for interrupt aggregation for platform related blocks
 Separated interrupt enable and disable registers
 Supports global disable function
 2-level Interrupt priority selection
 Each interrupt source can be directed to IRQ#0 or IRQ#1
NOTE: MT7620 supports MIPS 24K’s vector interrupt mechanism.
There are 6 hardware interrupts supported by MIPS 24K. The interrupt allocation is shown below:
MIPS H/W interrupt pins

Connect to

Remark

HW_INT#5

Timer interrupt

Highest priority

HW_INT#4

Reserved

HW_INT#3

FE

HW_INT#2

PCIe

HW_INT#1

Other high priority interrupts (IRQ#1)

HW_INT#0

Other low priority interrupts (IRQ#0)

Lowest priority

2.4.2 Block Diagram
MIPS Timer INT

INT 5
INT 4
INT 3
INT 2

Interrupt Controller
Interrupts
(from platform blocks)

MIPS

IRQ1
(high priority)
Interrupt
Masking

INT 1

Interrupt Priority
Selection

INT 0
IRQ0
(low priority)

PalmBus
(to/from MIPS)
PalmBus Interface

Figure 2-3 Interrupt Controller Block Diagram

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MT7620 PROGRAMMING GUIDE
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2.4.3 List of Registers
No. Offset
Register Name

Description

37

0x0000

IRQ0STAT

Interrupt Type 0 Status after Enable Mask

55

38

0x0004

IRQ1STAT

Interrupt Type 1 Status after Enable Mask

55

39

0x0020

INTTYPE

Interrupt Type

56

40

0x0030

INTRAW

Raw Interrupt Status before Enable Mask

57

41

0x0034

INTENA

Interrupt Enable

58

42

0x0038

INTDIS

Interrupt Disable

58

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.4.4 Register Descriptions (base: 0x1000_0200)
37. IRQ0STAT: Interrupt Type 0 Status after Enable Mask (offset: 0x0000)
Bits
Type
Name
Description

Initial Value

31:20

-

-

Reserved

19

RO

UDEV

USB device interrupt status after mask

0x0

-

18

RO

UHST

USB host interrupt status after mask

0x0

17

RO

ESW

Ethernet Switch interrupt status after mask

0x0

16

-

-

Reserved

0x0

15

RO

R2P

R2P interrupt after mask

0x0

14

RO

SDHC

SDHC interrupt after mask

0x0

13

-

-

Reserved

0x0

12

RO

UARTLITE

UARTLITE interrupt status after mask

0x0

11

RO

SPI

SPI interrupt status after mask

0x0

10

RO

I2S

I2S interrupt status after mask

0x0

9

RO

PC

MIPS performance counter interrupt status
after mask

0x0

8

-

-

Reserved

0x0

7

RO

DMA

DMA interrupt status after mask

0x0

6

RO

PIO

PIO interrupt status after mask

0x0

5

RO

UART

UART interrupt status after mask

0x0

4

RO

PCM

PCM interrupt status after mask

0x0

3

RO

ILL_ACC

Illegal access interrupt status after mask

0x0

2

RO

WDTIMER

Watchdog timer interrupt status after mask

0x0

1

RO

TIMER0

Timer 0 interrupt status after mask

0x0

0
RO
SYSCTL
System control interrupt status after mask
0x0
NOTE: These bits are set if the corresponding interrupt is asserted from the source and with the following two
conditions.
1. The interrupt is not masked (the bit is not set in the INTDIS register)
2. The interrupt type is set to INT0 (in the INTTYPE register).
NOTE: Writing to these bits is ignored and each bit cannot be simultaneously active in both the IRQ0STAT and
IRQ1STAT registers.
38. IRQ1STAT: Interrupt Type 1 Status after Enable Mask (offset: 0x0004)
Bits
Type Name
Description

Initial Value

31:20

-

-

Reserved

19

RO

UDEV

USB device interrupt status after mask

0x0

18

RO

UHST

USB host interrupt status after mask

0x0

17

RO

ESW

Ethernet Switch interrupt status after mask

0x0

16

-

-

Reserved

0x0

15

RO

R2P

R2P interrupt after mask

0x0

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MT7620 PROGRAMMING GUIDE
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Bits

Type

Name

Description

14

RO

SDHC

SDHC interrupt after mask

Initial Value
0x0

13

-

-

Reserved

0x0

12

RO

UARTLITE

UARTLITE interrupt status after mask

0x0

11

RO

SPI

SPI interrupt status after mask

0x0

10

RO

I2S

I2S interrupt status after mask

0x0

9

RO

PC

MIPS performance counter interrupt status
after mask

0x0

8

-

-

Reserved

0x0

7

RO

DMA

DMA interrupt status after mask

0x0

6

RO

PIO

PIO interrupt status after mask

0x0

5

RO

UART

UART interrupt status after mask

0x0

4

RO

PCM

PCM interrupt status after mask

0x0

3

RO

ILL_ACC

Illegal access interrupt status after mask

0x0

2

RO

WDTIMER

Watchdog timer interrupt status after mask

0x0

1

RO

TIMER0

Timer 0 interrupt status after mask

0x0

0
RO
SYSCTL
System control interrupt status after mask
0x0
NOTE: These bits are set if the corresponding interrupt is asserted from the source and with the following two
conditions:
1. The interrupt is not masked (the bit is not set in the INTDIS register)
2. The interrupt type is set to INT1 (in the INTTYPE register).
NOTE: Writing to these bits is ignored and each bit cannot be simultaneously active in both the IRQ0STAT and
IRQ1STAT registers.
39. INTTYPE: Interrupt Type (offset: 0x0020)
Bits
Type
Name

Description

31:20

-

-

Reserved

19

RW

UDEV

USB device interrupt status type

0x0

18

RW

UHST

USB host interrupt status type

0x0

17

RW

ESW

Ethernet Switch interrupt status type

0x0

16

-

-

Reserved

0x0

15

RW

R2P

R2P Interrupt status type

0x0

14

RW

SDHC

SDHC Engine interrupt status type

0x0

13

-

-

Reserved

0x0

12

RW

UARTLITE

UARTLITE interrupt status type

0x0

11

RW

SPI

SPI interrupt status type

0x0

10

RW

I2S

I2S interrupt status type

0x0

9

RW

PC

MIPS performance counter interrupt status
type

0x0

8

-

-

Reserved

0x0

7

RW

DMA

DMA interrupt status type

0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

6

RW

PIO

PIO interrupt status type

Initial Value
0x0

5

RW

UART

UART interrupt status type

0x0

4

RW

PCM

PCM interrupt status type

0x0

3

RW

ILL_ACC

Illegal access interrupt status type

0x0

2

RW

WDTIMER

Watchdog timer interrupt status type

0x0

1

RW

TIMER0

Timer 0 interrupt status type

0x0

0
RW
SYSCTL
System control interrupt status type
0x0
NOTE:
0: IRQ type 0
1: IRQ type 1
The interrupt type may be changed at any time; if the interrupt type is changed while the interrupt is active,
the interrupt is immediately redirected.
40. INTRAW: Raw Interrupt Status before Enable Mask (offset: 0x0030)
Bits
Type
Name
Description

Initial Value

31:20

-

-

Reserved

0x0

19

RO

UDEV

USB device interrupt status before mask

0x0

18

RO

UHST

USB host interrupt status before mask

0x0

17

RO

ESW

Ethernet Switch interrupt status before mask

0x0

16

-

-

Reserved

0x0

15

RO

R2P

R2P interrupt status before mask

0x0

14

RO

SDHC

SDHC interrupt status before mask

0x0

13

-

-

Reserved

0x0

12

RO

UARTLITE

UARTLITE interrupt status before mask

0x0

11

RO

SPI

SPI interrupt status before mask

0x0

10

RO

I2S

I2S interrupt status before mask

0x0

9

RO

PC

MIPS performance counter interrupt status
before mask

0x0

8

-

-

Reserved

0x0

7

RO

DMA

DMA interrupt status before mask

0x0

6

RO

PIO

PIO interrupt status before mask

0x0

5

RO

UART

UART interrupt status before mask

0x0

4

RO

PCM

PCM interrupt status before mask

0x0

3

RO

ILL_ACC

Illegal access interrupt status before mask

0x0

2

RO

WDTIMER

Watchdog timer interrupt status before mask

0x0

1

RO

TIMER0

Timer 0 interrupt status before mask

0x0

0
RO
SYSCTL
System control interrupt status before mask
0x0
NOTE: These bits are set if the corresponding interrupt is asserted from the source. The status bit is set if the
interrupt is active, even if it is masked, and regardless of the interrupt type. This provides a single-access
snapshot of all active interrupts for implementation of a polling system.

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

41. INTENA: Interrupt Enable (offset: 0x0034)
Bits
Type
Name
Description

Initial Value

31

RW

GLOBAL

Global Interrupt Enable
Allows local interrupts in this register to be
individually enabled. Set this bit before
enabling interrupts in this register.

0x0

30:20

-

-

Reserved

0x0

19

-

-

Reserved

0x0

18

RW

UHST

USB host interrupt enable

0x0

17

RW

ESW

Ethernet Switch interrupt enable

0x0

16

-

-

Reserved

0x0

15

RW

R2P

R2P interrupt enable

0x0

14

RW

SDHC

SDHC interrupt enable

-

13

-

-

Reserved

-

12

RW

UARTLITE

UARTLITE interrupt enable

0x0

11

RW

SPI

SPI interrupt enable

0x0

10

RW

I2S

I2S interrupt enable

0x0

9

RW

PC

MIPS performance counter interrupt enable

0x0

8

-

-

Reserved

0x0

7

RW

DMA

DMA interrupt enable

0x0

6

RW

PIO

PIO interrupt enable

0x0

5

RW

UART

UART interrupt enable

0x0

4

RW

PCM

PCM interrupt enable

0x0

3

RW

ILL_ACC

Illegal access interrupt enable

0x0

2

RW

WDTIMER

Watchdog timer interrupt enable

0x0

1

RW

TIMER0

Timer 0 interrupt enable

0x0

System control interrupt enable

0x0

0
RW
SYSCTL
NOTE: Where applicable,
1: Enable

42. INTDIS: Interrupt Disable (offset: 0x0038)
Bits
Type
Name
Description

Initial Value

31

RW

GLOBAL

Global Interrupt Disable
Allows local interrupts in this register to be
individually disabled. Set this bit before
disabling interrupts in this register.

0x0

30:20

-

-

Reserved

0x0

19

-

-

Reserved

0x0

18

RW

UHST

USB host interrupt status disable

0x0

17

RW

ESW

Ethernet Switch interrupt disable

0x0

16

-

-

Reserved

0x0

15

RW

R2P

R2P interrupt disable

0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

14

RW

SDHC

SDHC interrupt disable

0x0

13

-

-

Reserved

0x0

12

RW

UARTLITE

UARTLITE interrupt disable

0x0

11

RW

SPI

SPI interrupt disable

0x0

10

RW

I2S

I2S interrupt disable

0x0

9

RW

PC

MIPS performance counter interrupt disable

0x0

8

RW

NAND

NAND flash controller interrupt disable

0x0

7

RW

DMA

DMA interrupt disable

0x0

6

RW

PIO

PIO interrupt disable

0x0

5

RW

UART

UART interrupt disable

0x0

4

RW

PCM

PCM interrupt disable

0x0

3

RW

ILL_ACC

Illegal access interrupt disable

0x0

2

RW

WDTIMER

Watchdog timer interrupt disable

0x0

1

RW

TIMER0

Timer 0 interrupt disable

0x0

System control interrupt disable

0x0

0
RW
SYSCTL
NOTE: Where applicable,
1: Disable

PGMT7620_V.1.0_040503

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.5 System Tick Counter
2.5.1 List of Registers
No. Offset
Register Name

Description

43

0x0000

STCK_CNT_CFG

MIPS Configuration

61

44

0x0004

CMP_CNT

MIPS Compare

61

45

0x0008

CNT

MIPS Counter

61

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.5.2 Register Descriptions (base: 0x1000_0d00)
43. STCK_CNT_CFG: MIPS Configuration Register (offset: 0x0000)
Bits
Type Name
Description

Initial Value

31:2

-

-

Reserved

1

RW

EXT_STK_EN

External System Tick Enable
Selects the system tick source
0: Use the MIPS internal timer interrupt.
1: Use the external timer interrupt from an
external MIPS counter.

0x0

0

RW

CNT_EN

Count Enable
Enables the free run counter (MIPS counter).
This counter increments every 20 μs.
0: Disable
1: Enable

0x0

44. CMP_CNT: MIPS Compare Register (offset: 0x0004)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RW

CMP_CNT

Compare Count
Sets the cutoff point for the free run counter
(MIPS counter). If the free run counter equals
the compare counter, then the timer circuit
generates an interrupt. The interrupt remains
active until the compare counter is written
again.

45. CNT: MIPS Counter Register (offset: 0x0008)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RW

CNT

MIPS Counter
The MIPS counter (free run counter) increases
by 1 every 20 μs (50 KHz). The counter
continues to count until it reaches the value
loaded into CMP_CNT.

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Initial Value
0x0

Initial Value
0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.6 UART
2.6.1 Features
 16550-compatible register set, except for Divisor Latch register
 5-8 data bits
 1-2 stop bits (1 or 2 stop bits are supported with 5 data bits)
 Even, odd, stick or no parity
 All standard baud rates up to 345 600 b/s
 16-byte receive buffer
 16-byte transmit buffer
 Receive buffer threshold interrupt
 Transmit buffer threshold interrupt
 False start bit detection in asynchronous mode
 Internal diagnostic capabilities
 Break simulation
 Loop-back control for communications link fault isolation
2.6.2 Block Diagram
Reset
from System
Control

16550-Compatible UART
PalmBus
Interface
RXD

TXD

Serializer

Transmit FIFO

Deserializer

Receive FIFO

MODEM
Control

Protocol Control

Baud Rate
Generator

Status

Interrupts

PalmBus Signals
from PalmBus

Clock
from System
Control

Interrupt
to Interrupt
Controller

Figure 2-4 UART Block Diagram

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.6.3 List of Registers
No. Offset
Register Name

Description

46

0x0000

RBR

Receive Buffer Register

64

47

0x0004

TBR

Transmit Buffer Register

64

48

0x0008

IER

Interrupt Enable Register

64

49

0x000C

IIR

Interrupt Identification Register

65

50

0x0010

FCR

FIFO Control Register

66

51

0x0014

LCRLCR

Line Control Register

66

52

0x0018

MCR

Modem Control Register

67

53

0x001C

LSR

Line Status Register

68

54

0x0020

MSR

Modem Status Register

69

55

0x0024

SCRATCH

Scratch

70

56

0x0028

DL

Clock Divider Divisor Latch

70

57

0x002C

DLLO

Clock Divider Divisor Latch Low

71

58

0x0030

DLHI

Clock Divider Divisor Latch High

71

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.6.4 Register Descriptions (base: 0x1000_0500)
46. RBR: Receive Buffer Register (offset: 0x0000)
Bits
Type Name
Description
31:8

-

-

Reserved

7:0

RO

RXD

Receive Buffer Data
Data is transferred to this register from the
receive shift register after a full character is
received. If the contents of this register have
not been read before another character is
received, the OE bit in the LSR register is set,
indicating a received data buffer overrun.

47. TBR: Transmit Buffer Register (offset: 0x0004)
Bits
Type
Name
Description
31:8

-

-

Reserved

7:0

RO

TXD

Transmit Buffer Data
When a character is written to this register, it is
stored in the transmitter holding register. If the
transmitter register is empty, the character is
moved to the transmitter register, starting
transmission.

48. IER: Interrupt Enable Register (offset: 0x0008)
Bits
Type
Name
Description

Initial Value
0x0

Initial Value
0x0

Initial Value

31:4

-

-

Reserved

3

RW

EDSSI

Enable Modem Interrupt
Enables the following modem status interrupts.
 Data Carrier Detect (DCD)
 Ring Indicator (RI)
 Data Set Ready (DSR)
 Clear to Send (CTS)
 Delta Data Carrier Detect (DDCD)
 Trailing Edge Ring Indicator (TERI)
 Delta Data Set Ready (DDSR) to Send (DCTS)

0x0

2

RW

ELSI

Enable Receiver Line Status Interrupt
Enables the following receive line status
interrupts.
 Overrun Error (OE)
 Parity Error (PE)
 Framing Error (FE)
 Break Interrupt (BI)

0x0

1

RW

ETBEI

Enable Transmit Buffer Empty Interrupt
Enables the transmit buffer empty (THRE)
interrupt.

0x0

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

0

RW

ERBFI

Enable Rx Buffer Full Interrupt
Enables the receive buffer full interrupt, as well
as the data ready (DR) and character time-out
interrupts.

Initial Value
0x0

NOTE:
0: Disable
1: Enable
49. IIR: Interrupt Identification Register (offset: 0x000C)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

7:6

RO

FIFOEN

FIFOs Enabled
These bits reflect the FIFO enable bit setting in
the FIFO Control Register.
00: FIFO enable bit is cleared.
11: FIFO enable bit is set.

0x0

-

5:4

-

-

Reserved

0x0

3:1

RO

INTID

Interrupt Identifier
These bits provide a snapshot of the interrupt
type, and may be used as the offset into an
interrupt vector table.
See NOTE below.

0x0

0

RO

INTPEND

Interrupt Pending
0: An interrupt bit is set and is not masked.
1: No interrupts are pending.

0x1

NOTE:
The interrupt encoding is given below.
ID

Priority

Type

7

Undefined

6

Undefined

5

Undefined

4

Undefined

Source

3

1 (highest)

Receiver Line Status

OE, PE, FE, BI

2

2

Receiver Buffer Full

DR

1

3

Transmitter Buffer Empty

THRE

0

4 (lowest)

Modem Status

DCTS, DDSR, RI, DCD

If more than one category of interrupt is asserted, only the highest priority ID is given.
The line and modem status interrupts are cleared by reading the corresponding status register in the UART
block (LSR (0x001C), MSR (0x0020)). The receive buffer full interrupt is cleared when all of the data is read
from the receive buffer. The transmit buffer empty interrupt is cleared when data is written to the TBR register
(0x0004) in the UART block.

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

50. FCR: FIFO Control Register (offset: 0x0010)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

7:6

RW

RXTRIG

Rx Trigger Level
Sets the number of characters contained by the
receive buffer which triggers assertion of the
data ready (DR) interrupt.
0: 1
1: 4
2: 8
3: 14
NOTE: This register is not used if the receive
FIFO is disabled.

0x0

5:4

RW

TXTRIG

Tx Trigger Level
Sets the number of characters contained by the
transmit buffer which triggers the threshold
empty (THRE) interrupt.
0: 1
1: 4
2: 8
3: 12

0x0

3

RW

DMAMODE

Enable DMA transfers
This bit is writeable and readable, but has no
other hardware function.

0x0

2

WO

TXRST

Tx Reset
1: Clears the transmit FIFO and resets the
transmit status. The shift register is not
cleared.

0x0

1

WO

RXRST

Rx Reset
1: Clears the receive FIFO and resets the receive
status. The shift register is not cleared.

0x0

0

RW

FIFOENA

FIFO Enable
Enables Tx and Rx FIFOs. When disabled, the
FIFOs have an effective depth of one character.
0: Disable
1: Enable
NOTE: The FIFO status and data are
automatically cleared when this bit is changed.

0x0

51. LCR: Line Control Register (offset: 0x0014)
Bits
Type
Name
Description

-

Initial Value

31:8

-

-

Reserved

0x0

7

RW

DLAB

Divisor Latch Access Bit
This bit has no functionality, and is retained for
compatibility only

0x0

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MT7620 PROGRAMMING GUIDE
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Bits

Type

Name

Description

6

RW

SETBRK

Set Break Condition
0: Normal functionality.
1: Force TXD pin to 0. Tx otherwise operates
normally.

0x0

5

RW

FORCEPAR

Force Parity Bit
0: Normal functionality.
1: If even parity is selected, the (transmitted
and checked) parity is forced to 0.
If odd parity is selected, the (transmitted and
checked) parity if forced to 1.

0x0

4

RW

EPS

Even Parity Select
0: Odd parity selected (checksum, including
parity is 1).
1: Even parity selected (checksum, including
parity is 0).
NOTE: This bit is ignored if the PEN bit is 0.

0x0

3

RW

PEN

Parity Enable
0: Parity is not transmitted or checked.
1: Parity is generated (transmit), and checked
(receive).

0x0

2

RW

STB

Stop Bit Select
0: 1 Stop Bit is transmitted and received.
1: 1.5 Stop Bits are transmitted and received if
WLS is 0;
2 Stop Bits are transmitted and received if
WLS is 1, 2, or 3.

0x0

1:0

RW

WLS

Word Length Select
Selects the character length.
0: Each character is 5 bits in length
1: Each character is 6 bits in length
2: Each character is 7 bits in length
3: Each character is 8 bits in length

0x0

52. MCR: Modem Control Register (offset: 0x0018)
Bits
Type
Name
Description
31:5

-

-

PGMT7620_V.1.0_040503

Reserved

Initial Value

Initial Value
0x0

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MT7620 PROGRAMMING GUIDE
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Bits

Type

Name

Description

4

RW

LOOP

Loopback Mode Enable
0: Normal Operation.
1: The UART is put into loopback mode, and
used for self-testiing. The TXD pin is driven
high; the TXD signal connections are made
internally.
Signal
Wrapped Back Through:
TXD
RXD
DTRN
DSRN
RTSN
CTSN
OUT1N RIN
OUT2N DCDN

0x0

3

RW

OUT2

OUT2 Pin Value
0: OUT2N pin is driven to a high level.
1: OUT2N pin is driven to a low level.
NOTE: This bit is only functional in loopback
mode.

0x0

2

RW

OUT1

OUT1 Pin Value
0: OUT1N pin is driven to a high level.
1: OUT1N pin is driven to a low level.
NOTE: This bit is only functional in loopback
mode.

0x0

1

RW

RTS

RTSN1 Pin Value
0: RTSN pin is driven to a high level.
1: RTSN pin is driven to a low level.

0x0

0

RW

DTR

DTRN 1 Pin Value
0: DTRN pin is driven to a high level.
1: DTRN pin is driven to a low level.

0x0

53. LSR: Line Status Register (offset: 0x001C)
Bits
Type
Name
Description

Initial Value

Initial Value

31:8

-

-

Reserved

0x0

7

RC

ERINFIFO

Error in FIFO
Indicates that a FIFO contains data which was
received with a parity error, framing error, or
break condition.

0x0

6

RC

TEMT

Transmit Shift Register Empty
Indicates that the transmit shift register is
empty. This bit is reset when data is written to
the transmit buffer register (TBR).

0x1

5

RC

THRE

Transmit Holding Register Empty
Indicates that the transmitter holding register is
empty. This bit is reset when data is written to
the transmit buffer register (TBR).

0x1

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Bits

Type

Name

Description

4

RC

BI

Break Interrupt
Indicates that a break is received, that is, when
the RXD signal is at a low state for more than
one character transmission time (from Start Bit
to Stop Bit). Under this condition, a single 0 is
received.

Initial Value
0x0

3

RC

FE

Framing Error
Indicates that a valid Stop Bit is not detected. If
a framing error occurs, the receive buffer will
attempt to re-synchronize by sampling the Start
Bit twice and then receiving the data.

0x0

2

RC

PE

Parity Error
Indicates that the received parity is different
from the expected value.

0x0

1

RC

OE

Overrun Error
Indicates that when a receive overrun occurs.
This happens if a character is received before
the previous character has been read by
firmware.

0x0

0

RC

DR

Data Ready
Indicates that character is received, and has
been transferred to the receive buffer register.
This bit is reset when all the characters are read
from the receive buffer register.

0x0

NOTE:
0: False
1: True
54. MSR: Modem Status Register (offset: 0x0020)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7

RC

DCD

Data Carrier Detect
Indicates the DCDN (Data Carrier Detect) pin is
at a low value.

0x0

6

RC

RI

Ring Indicator
Indicates the RIN (Ring Indicator) pin is at a low
value.

0x0

5

RC

DSR

Data Set Ready
Indicates the DSRN (Data Set Ready) pin is at a
low value.

0x0

4

RC

CTS

Clear to Send
Indicates the CTSN (Clear to Send) pin is at a
low value.

0x0

3

RC

DDCD

Delta Data Carrier Detect
Indicates when the DCDN (Data Carrier Detect)
pin changes.

0x0

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Bits

Type

Name

Description

2

RC

TERI

Trailing Edge Ring Indicator
Indicates when the RIN (Ring Indicator) pin
changes from a low to a high value.

Initial Value
0x0

1

RC

DDSR

Delta Data Set Ready
Indicates when the DSRN (Data Set Ready) pin
changes.

0x0

0

RC

DCTS

Delta Clear to Send
Indicates when the CTSN (Clear to Send) pin
changes.

0x0

NOTE:
0: False
1: True
55. SCRATCH: Scratch Register (offset: 0x0024)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7:0

RW

SCRATCH

Scratch
This register is defined as a scratch register in
16550 application. It has no hardware function,
and is retained for compatibility only.

0x0

56. DL: Clock Divider Divisor Latch (offset: 0x0028)
Bits
Type
Name
Description

Initial Value

31:16

-

-

Reserved

0x0

15:0

RW

DL

Divisor Latch
This register is used in the clock divider to
generate the baud clock.
The baud rate (transfer rate in bits per second)
is defined as:
baud rate = 40 MHz / (CLKDIV * 16).

0x1

NOTE:
1. In standard 16550 implementation, this register is accessible as two 8-bit halves only. In this implementation,
the DL register is accessible as a single 16-bit entity only.
2. DL[15:0] should be >= 4.
SRC Clock Freq.

40 MHz

Req. Baud Rate (Bd)

DL [15:0]

Err Rate (%)

57000

44

-0.32%

115200

22

-1.36%

230400

11

-1.36%

345600

7

3.34%

460800

5

8.51%

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57. DLLO: Clock Divider Divisor Latch Low (offset: 0x002C)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7:0

RW

DLLO

This register is the equivalent to the lower 8
bits of the DL register. It is provided for16550
compatibility.
NOTE: In standard 16550 implementation, this
register is accessible as two 8-bit halves only.
For convenience, the divisor latch is accessible
as a single 16-bit entity via the DL register.

0x1

58. DLHI: Clock Divider Divisor Latch High (offset: 0x0030)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7:0

RW

DLHI

This register is the equivalent to the upper 8
bits of the DL register. It is provided for 16550
compatibility.
NOTE: In standard 16550 implementation, this
register is accessible as two 8-bit halves only.
For convenience, the divisor latch is accessible
as a single 16-bit entity via the DL register.

0x0

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2.7 UART Lite
2.7.1 Features
 2-pin UART
 16550-compatible register set, except for Divisor Latch register
 5-8 data bits
 1-2 stop bits (1 or 2 stop bits are supported with 5 data bits)
 Even, odd, stick or no parity
 All standard baud rates up to 345600 b/s
 16-byte receive buffer
 16-byte transmit buffer
 Receive buffer threshold interrupt
 Transmit buffer threshold interrupt
 False start bit detection in asynchronous mode
 Internal diagnostic capabilities
 Break simulation
 Loop-back control for communications link fault isolation
2.7.2 Block Diagram
clock
reset

TXD

Baud Rate
Generator

Transmit FIFO

Serializer

CPU Interface

Receive FIFO

Deserializer

from System
Controller

CPU Interface
from PalmBus
Controller

Interrupt
to Interrupt
Controller

Interrupts

Status

RXD

Protocol Control

Figure 2-5 UART Lite Block Diagram

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2.7.3 List of Registers
No. Offset
Register Name

Description

59

0x0000

RBR

Receive Buffer Register

74

60

0x0004

TBR

Transmit Buffer Register

74

61

0x0008

IER

Interrupt Enable Register

74

62

0x000C

IIR

Interrupt Identification Register

75

63

0x0010

FCR

FIFO Control Register

76

64

0x0014

LCR

Line Control Register

76

65

0x0018

MCR

Modem Control Register

77

66

0x001C

LSR

Line Status Register

78

67

0x0028

DL

Clock Divider Divisor Latch

79

68

0x002C

DLLO

Clock Divider Divisor Latch Low

79

69

0x0030

DLHI

Clock Divider Divisor Latch High

80

70

0x0034

IFCTL

Interface Control

80

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2.7.4 Register Descriptions (base: 0x1000_0C00)
59. RBR: Receive Buffer Register (offset: 0x0000)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7:0

RO

RXD

Receive Buffer Data
Data is transferred to this register from the Rx
shift register after a full character is received.
The OE bit in the LSR register is set if the
contents of this register have not been read
before another character is received, indicating
an Rx buffer overrun.

0x0

60. TBR: Transmit Buffer Register (offset: 0x0004)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7:0

RO

TXD

Transmit Buffer Data
When a character is written to this register, it is
stored in the Tx holding register; if the Tx
register is empty, the character is moved to the
Tx register, starting transmission.

0x0

61. IER: Interrupt Enable Register (offset: 0x0008)
Bits
Type
Name
Description

Initial Value

31:3

-

-

Reserved

0x0

2

RW

ELSI

Enable Line Status Interrupts
Enables the following Rx line status interrupts.
 Overrun Error (OE)
 Parity Error (PE)
 Framing Error (FE)
 Break Interrupt (BI)

0x0

1

RW

ETBEI

Enable Tx Buffer Empty Interrupt
Enables the Tx buffer empty interrupt (THRE),
which indicates the Tx buffer is empty.

0x0

0

RW

ERBFI

Enable Rx Buffer Full Interrupt
Enables the Rx buffer full interrupt, as well as
the Data Ready (DR) and Character Time-Out
interrupts.

0x0

NOTE:
0: Disable
1: Enable

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62. IIR: Interrupt Identification Register (offset: 0x000C)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7:6

RO

FIFOENA

FIFOs Enabled
These bits reflect the FIFO enable bit setting in
the FIFO Control Register.
00: FIFO enable bit is cleared.
11: FIFO enable bit is set.

0x0

5:4

-

-

Reserved

0x0

3:1

RO

INTID

Interrupt Identifier
These bits provide a snapshot of the interrupt
type, and may be used as the offset into an
interrupt vector table.
See NOTE below.

0x0

0

RO

INTPEND

Interrupt Pending
0: An interrupt bit is set and is not masked.
1: No interrupts are pending.

0x1

NOTE:
The interrupt encoding is given below.
Table 2-1 UART Lite Interrupt Priorities
ID Priority
Type
7

Undefined

6

Undefined

5

Undefined

4

Undefined

Source

3

1 (highest)

Receiver Line Status

OE, PE, FE, BI

2

2

Receiver Buffer Full

DR

1

3

Transmit Buffer Empty

THRE

0

Undefined

If more than one category of interrupt is asserted, only the highest priority ID is given.
The line and modem status interrupts are cleared by reading the corresponding status register (LSR (0x001C)).
The receiver buffer full interrupt is cleared when all of the data is read from the receive buffer. The transmitter
buffer empty is cleared when data is written to the TBR register (0x0004).

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63. FCR: FIFO Control Register (offset: 0x0010)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7:6

RW

RXTRIG

Rx Trigger Level
Sets the number of characters contained by the
receive buffer which triggers the data ready
(DR) interrupt.
0: 1 character
1: 4 characters
2: 8 characters
3: 14 characters
NOTE: This register is not used if the Rx FIFO is
disabled.

0x0

5:4

RW

TXTRIG

Tx Trigger Level
Sets the number of characters contained by the
transmit buffer which will trigger the threshold
empty (THRE) interrupt.
0: 1 character
1: 4 characters
2: 8 characters
3: 12 characters

0x0

3

RW

DMAMODE

DMA Mode
Enables DMA transfers
This bit is writeable and readable, but has no
other hardware function.

0x0

2

WO

TXRST

Tx Reset
1: Clears the transmit FIFO and resets its status.
The shift register is not cleared.

0x0

1

WO

RXRST

Rx Reset
1: Clears the receive FIFO and resets its status.
The shift register is not cleared.

0x0

0

RW

FIFOENA

FIFO Enable
Enables Tx and Rx FIFOs. When disabled, the
FIFOs have an effective depth of one character.
0: Disable
1: Enable
NOTE: The FIFO status and data are
automatically cleared when this bit is changed.

0x0

64. LCR: Line Control Register (offset: 0x0014)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7

RW

DLAB

Divisor Latch Access Bit
This bit has no functionality, and is retained for
compatibility only.

0x0

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Bits

Type

Name

Description

6

RW

SETBRK

Set Break Condition
0: Normal functionality.
1: Force TXD pin to 0. Tx otherwise operates
normally.

0x0

5

RW

FORCEPAR

Force Parity Bit
0: Normal functionality.
1: If even parity is selected, the (transmitted
and checked) parity is forced to 0.
If odd parity is selected, the (transmitted and
checked) parity if forced to 1.

0x0

4

RW

EPS

Even Parity Select
0: Odd parity selected (checksum, including
parity is 1).
1: Even parity selected (checksum, including
parity is 0).
NOTE: This bit is ignored if the PEN bit is 0.

0x0

3

RW

PEN

Parity Enable
0: Parity is not transmitted or checked.
1: Parity is generated (transmit), and checked
(receive).

0x0

2

RW

STB

Stop Bit Select
0: 1 Stop Bit is transmitted and received.
1: 1.5 Stop Bits are transmitted and received if
WLS is 0; 2 Stop Bits are transmitted and
received if WLS is 1, 2, or 3.

0x0

1:0

RW

WLS

Word Length Select
Selects the character length.
0: Each character is 5 bits in length
1: Each character is 6 bits in length
2: Each character is 7 bits in length
3: Each character is 8 bits in length

0x0

65. MCR: Modem Control Register (offset: 0x0018)
Bits
Type
Name
Description

Initial Value

Initial Value

31:5

-

-

Reserved

0x0

4

RW

LOOP

Loopback Mode Enable
0: Normal Operation.
1: The UART is put into loop-back mode, used
for self-testing: The TXD pin is driven high;
the TXD signal are connected to RXD
internally.

0x0

3:0

RO

-

Reserved

0x0

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66. LSR: Line Status Register (offset: 0x001C)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7

RC

ERINFIFO

Error in FIFO
Indicates that a FIFO contains data which was
received with a parity error, framing error, or
break condition.

0x0

6

RC

TEMT

Transmit Shift Register Empty
Indicates that the transmit shift register is
empty. This bit is reset when data is written to
the transmit buffer register (TBR).

0x1

5

RC

THRE

Transmit Holding Register Empty
Indicates that the transmitter holding register is
empty. This bit resets when data is written to
the Tx buffer register (TBR).

0x1

4

RC

BI

Break Interrupt
Indicates that a break is received, that is, when
the RXD signal is at a low state for more than
one character transmission time (from Start Bit
to Stop Bit). Under this condition, a single 0 is
received.

0x1

3

RC

FE

Framing Error
Indicates that a valid Stop Bit is not detected. If
a framing error occurs, the receive buffer will
attempt to re-synchronize by sampling the Start
Bit twice and then receiving the data.

0x0

2

RC

PE

Parity Error
Indicates that the received parity is different
from the expected value.

0x0

1

RC

OE

Overrun Error
Indicates that when a receive overrun occurs.
This happens if a character is received before
the previous character has been read by
firmware.

0x0

0

RC

DR

Data Ready
Indicates that a character is received, and has
been transferred to the receive buffer register.
The bit is reset when all the characters are read
from the receive buffer register.

0x0

NOTE:
0: False
1: True

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67. DL: Clock Divider Divisor Latch (offset: 0x0028)
Bits
Type
Name
Description

Initial Value

31:16

-

-

Reserved

0x0

15:0

RW

DL

Divisor Latch
This register is used in the clock divider to
generate the baud clock. The baud rate
(transfer rate in bits per second) is defined as:
Baud rate = system clock frequency / (CLKDIV *
16).
See NOTE below.

0x1

NOTE:
1. In standard 16550 implementation, this register is accessible as two 8-bit halves only. In this implementation,
the DL register is accessible as a single 16-bit entity only.
2. DL[15:0] should be >= 4.
SRC Clock Freq.

Req. Baud Rate (Bd)

DL [15:0]

Error Rate (%)

57 000

44

-0.32%

115 200

22

-1.36%

230 400

11

-1.36%

345 600

7

3.34%

460 800

5

8.51%

40 MHz

68. DLLO: Clock Divider Divisor Latch Low (offset: 0x002C)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7:0

RW

DLLO

Divisor Latch Low
This register is the equivalent to the lower 8
bits of the DL register. It is provided for 16550
compatibility.
NOTE: In a standard 16550 implementation,
this register is accessible as two 8-bit halves
only. For convenience, the divisor latch is
accessible as a single 16-bit entity via the DL
register.

0x1

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69. DLHI: Clock Divider Divisor Latch High (offset: 0x0030)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

0x0

7:0

RW

DLHI

Divisor Latch High
This register is the equivalent to the upper 8
bits of the DL register. It is provided for 16550
compatibility.
NOTE: In a standard 16550 implementation,
this register is accessible as two 8-bit halves
only. For convenience, the divisor latch is
accessible as a single 16-bit entity via the DL
register.

0x0

70. IFCTL: Interface Control (offset: 0x0034)
Bits
Type
Name

Description

31:1

-

-

Reserved

0x0

0

RW

IFCTL

Open Collector Mode Control
This register controls if the UART Lite TXD
output functions in open collector mode or is
always driven.
0: The output is always driven with the value of
the transmit data signal.
1: The TXD output functions in open collector
mode, where the TXD output is either driven
low (when the transmit data output is active
low) or tri-stated (when the transmit data
output is active high).

0x0

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MT7620 PROGRAMMING GUIDE
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2.8 Programmable I/O
2.8.1 Features
 Supports 73 programmable I/Os
 Parameterized numbers of independent inputs, outputs, and inputs
 Independent polarity controls for each pin
 Independently masked edge detect interrupt on any input transition
 Programmable I/O pins are shared with MDIO, JTAG, UART-Lite, UART, SPI, PCM, I2C, GE1, and
EPHY_LED.
2.8.2 Block Diagram

PIO Controller

Polarity

Data Out

Q

Q

Reset
from Power
Management

Clock
from Power
Management

PIO Data
to I/O Cells

Edge Detect

Direction
Q

PalmBus Interface

Interrupt
to Interrupt
Controller

PalmBus Signals
to PalmBus
Controller

Figure 2-6 Programmable I/O Block Diagram

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2.8.3 List of Registers
No.
Offset
Register Name

Description

Page

71

0x0000

GPIO23_00_INT

PIO Pin Ports 23 to 00 Interrupt Status

84

72

0x0004

GPIO23_00_EDGE

PIO Pin Ports 23 to 00 Edge Status

84

73

0x0008

GPIO23_00_RMASK

PIO Pin Ports 23 to 00 Rising Edge Interrupt Mask

85

74

0x000C

GPIO23_00_MASK

PIO Pin Ports 23 to 00 Falling Edge Interrupt Mask

85

75

0x0020

GPIO23_00_DATA

PIO Pin Ports 23 to 00 Data

85

76

0x0024

GPIO23_00_DIR

PIO Pin Ports 23 to 00 Data Direction

86

77

0x0028

GPIO23_00_POL

PIO Pin Ports 23 to 00 Data Polarity

86

78

0x002C

GPIO23_00_SET

PIO Pin Ports 23 to 00 Set Data Bit

86

79

0x0030

GPIO23_00_RESET

PIO Pin Ports 23 to 00 Clear Data Bit

86

80

0x0034

GPIO23_00_TOG

PIO Pin Ports 23 to 00 Toggle PIO Data Bit

86

81

0x0038

GPIO39_24_INT

PIO Pin Ports 39 to 24 Pin Interrupt Status

87

82

0x003C

GPIO39_24_EDGE

PIO Pin Ports 39 to 24 Pin Edge Status

87

83

0x0040

GPIO39_24_RMASK

PIO Pin Ports 39 to 24 Rising Edge Interrupt Mask

88

84

0x0044

GPIO39_ 24_FMASK

PIO Pin Ports 39 to 24 Falling Edge Interrupt Mask

88

85

0x0048

GPIO39_24_DATA

PIO Pin Ports 39 to 24 Data

89

86

0x004C

GPIO39_24_DIR

PIO Pin Ports 39 to 24 Data Direction

89

87

0x0050

GPIO39_24_POL

PIO Pin Ports 39 to 24 Data Polarity

89

88

0x0054

GPIO39_24_SET

PIO Pin Ports 39 to 24 Set Data Bit

90

89

0x0058

GPIO39_24_RESET

PIO Pin Ports 39 to 24 Clear Data Bit

90

90

0x005C

GPIO39_24_TOG

PIO Pin Ports 39 to 24 Toggle Data Bit

90

91

0x0060

GPIO71_40_INT

PIO Pin Ports 71 to 40 Interrupt Status

90

92

0x0064

GPIO71_40_EDGE

PIO Pin Ports 71 to 40 Edge Status

91

93

0x0068

GPIO71_40_RMASK

PIO Pin Ports 71 to 40 Rising Edge Interrupt Mask

91

94

0x006C

GPIO71_40_FMASK

PIO Pin Ports 71 to 40 Falling Edge Interrupt Mask

91

95

0x0070

GPIO71_40_DATA

PIO Pin Ports 71 to 40 Data

92

96

0x0074

GPIO71_40_DIR

PIO Pin Ports 71 to 40 Data Direction

92

97

0x0078

GPIO71_40_POL

PIO Pin Ports 71 to 40 Data Polarity

92

98

0x007C

GPIO71_40_SET

PIO Pin Ports 71 to 40 Set Data Bit

93

99

0x0080

GPIO71_40_RESET

PIO Pin Ports 71 to 40 Clear Data Bit

93

100

0x0084

GPIO71_40_TOG

PIO Ports 71 to 40 Toggle Data Bit

93

101

0x0088

GPIO72_INT

PIO Pin Port 72 Interrupt Status

93

102

0x008C

GPIO72_EDGE

PIO Pin Port 72 Edge Status

93

103

0x0090

GPIO72_RMASK

PIO Pin Port 72 Rising Edge Interrupt Mask

94

104

0x0094

GPIO72_FMASK

PIO Pin Port 72 Falling Edge Interrupt Mask

94

105

0x0098

GPIO72_DATA

PIO Pin Port 72 Data

95

106

0x009C

GPIO72_DIR

PIO Pin Port 72 Data Direction

95

107

0x00A0

GPIO72_POL

PIO Pin Port 72 Data Polarity

95

108

0x00A4

GPIO72_SET

PIO Pin Port 72 Set Data Bit

96

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109

0x00A8

GPIO72_RESET

PIO Pin Port 72 Clear Data Bit

96

110

0x00AC

GPIO72_TOG

PIO Pin Port 72 Toggle Data Bit

96

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MT7620 PROGRAMMING GUIDE
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2.8.4 Register Descriptions (base: 0x1000_0600)
71. GPIO23_00_INT: PIO Pin Interrupt Status (offset: 0x0000)
Bits
Type
Name
Description
31:24

-

-

Reserved

23:0

RC

PIOINT

PIO Pin Interrupt
A PIOINT bit is set when its corresponding PIO
pin changes value and the edge for that pin is
enabled via the PIORMASK or PIOFMASK
register. The pin must be set as an input in the
PIODIR register to generate an interrupt.
Read
0: No change detected.
1: Change detected.
Write
All bits are cleared by writing 1 to either this
register or the PIOEDGE register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.

72. GPIO23_00_EDGE: PIO Pin Edge Status (offset: 0x0004)
Bits
Type
Name
Description
31:24

-

-

Reserved

23:0

RC

PIOEDGE

The PIOEDGE bits have different meanings
depending on whether the interrupt for that pin
is enabled via the PIORMASK or PIOFMASK
register.
Read
If the PIO PIN Interrupt for this PIO pin is
asserted, the corresponding PIOEDGE bit
indicates whether a falling or rising edge
triggered the interrupt.
0: Interrupt triggered by falling edge.
1: Interrupt triggered by rising edge.
If the interrupt is masked (disabled), the
PIOEDGE bit is set on either a rising or falling
edge and remains set until cleared by firmware.
Bits corresponding to pins that are not set as
inputs will never be set.
Write
All bits are cleared by writing 1 to either this
register or the PIOINT register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.

PGMT7620_V.1.0_040503

Initial Value
0x0

Initial Value
0x0

Page 84 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

73. GPIO23_00_RMASK: PIO Pin Rising Edge Interrupt Mask (offset: 0x0008)
Bits
Type
Name
Description
31:24

-

-

Reserved

23:0

RW

PIORMASK

PIO Pin Rising Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
0 to a 1, i.e. a rising edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.

74. GPIO23_00_MASK: PIO Pin Falling Edge Interrupt Mask (offset: 0x000C)
Bits
Type
Name
Description
31:24

-

-

Reserved

23:0

RW

PIOFMASK

PIO Pin Falling Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
1 to a 0, i.e. a falling edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.

75. GPIO23_00_DATA: PIO Pin Data (offset: 0x0020)
Bits
Type
Name
Description
31:24

-

-

Reserved

23:0

RW

PIODATA

PIO Pin Data
These bits are used for driving or sensing static
signals on the PIO pins. To drive a value onto a
PIO pin, the corresponding bit in the PIODIR
register must be set. If the corresponding
direction bit is set, the value written to the bit
in the PIODATA register will be driven at the
pin. A read of this register returns the value of
the signals currently on the PIO pins.
NOTE:
1. The value of any bit in this register is inverted
with respect to the pin if the corresponding bit
in the PIOPOL register is set, both in input and
output modes.
2. The values read from the PIO pins are not
synchronized; the user should be sure that the
data will not change when this register is read,
or should be aware that the bits which are not
static at that time may be inaccurate.

PGMT7620_V.1.0_040503

Initial Value
0x0

Initial Value
0x0

Initial Value
PC

Page 85 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

76. GPIO23_00_DIR: PIO Pin Direction (offset: 0x0024)
Bits
Type
Name
Description
31:24

-

-

Reserved

23:0

RW

PIODIR

PIO Pin Direction
Sets the data direction on PIO pins
corresponding to bits in this register.
0: Set data direction to input.
1: Set data direction to output.
The values driven onto the PIO pins are
controlled by the PIOPOL and PIODATA
registers.

77. GPIO23_00_POL: PIO Pin Polarity (offset: 0x0028)
Bits
Type
Name
Description
31:24

-

-

Reserved

23:0

RW

PIOPOL

PIO Pin Polarity
Sets the polarity of data on PIO pins
corresponding to bits in this register.
0: Maintain original polarity
1: Invert existing polarity
NOTE: The polarity controls affect both input
and output modes.

78. GPIO23_00_SET: Set PIO Pin Data Bit (offset: 0x002C)
Bits
Type
Name
Description
31:24

-

-

Reserved

23:0

W

PIOSET

PIO Pin Set
Sets the corresponding bit in the PIODATA
output register.
0: No effect.
1: Set the selected PIODATA bit.

79. GPIO23_00_RESET: Clear PIO Pin Data Bit (offset: 0x0030)
Bits
Type
Name
Description
31:24

-

-

Reserved

23:0

W

PIORESET

PIO Pin Reset
Clears the corresponding bit in the PIODATA
output register.
0: No effect.
1: Clear the selected PIODATA bit.

80. GPIO23_00_TOG: Toggle PIO Pin Data Bit (offset: 0x0034)
Bits
Type
Name
Description
31:24

-

-

PGMT7620_V.1.0_040503

Reserved

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Initial Value
-

0x0

Initial Value
-

Page 86 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

23:0

W

PIOTOG

PIO Pin Toggle
Toggles the corresponding bit in the PIODATA
output register.
0: No effect.
1: Invert the selected PIODATA bit.

81. GPIO39_24_INT: PIO Pin Interrupt (offset: 0x0038)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RC

PIOINT

PIO Interrupt
A PIOINT bit is set when its corresponding PIO
pin changes Value and the edge for that pin is
enabled via the PIORMASK or PIOFMASK
register. The pin must be set as an input in the
PIODIR register to generate an interrupt.
Read
0: No change detected.
1: Change detected.
Write
All bits are cleared by writing 1 to either this
register or the PIOEDGE register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.

82. GPIO39_24_EDGE: PIO Pin Edge Status (offset: 0x003C)
Bits
Type
Name
Description
31:16

-

-

PGMT7620_V.1.0_040503

Reserved

Initial Value
0x0

Initial Value
0x0

Initial Value
-

Page 87 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

15:0

RC

PIOEDGE

The PIOEDGE bits have different meanings
depending on whether the interrupt for that
pin is enabled via the PIORMASK or PIOFMASK
register.
Read
If the PIO Pin Interrupt for this PIO pin is
asserted, the corresponding PIOEDGE bit
indicates whether a falling or rising edge
triggered the interrupt.
0: Interrupt triggered by falling edge.
1: Interrupt triggered by rising edge.
If the interrupt is masked (disabled), the
PIOEDGE bit is set on either a rising or falling
edge and remains set until cleared by firmware.
Bits corresponding to pins that are not set as
inputs will never be set.
Write
All bits are cleared by writing 1 to either this
register or the PIOINT register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.

83. GPIO39_24_RMASK: PIO Pin Rising Edge Interrupt Mask (offset: 0x0040)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RW

PIORMASK

PIO Pin Rising Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
0 to a 1, i.e. a rising edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.

84. GPIO39_ 24_FMASK: PIO Pin Falling Edge Interrupt Mask (offset: 0x0044)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RW

PIOFMASK

PIO Pin Falling Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
1 to a 0, i.e. a falling edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.

PGMT7620_V.1.0_040503

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Page 88 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

85. GPIO39_24_DATA: PIO Pin Data (offset: 0x0048)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RW

PIODATA

PIO Pin Data
These bits are used for driving or sensing static
signals on the PIO pins. To drive a value onto a
PIO pin, the corresponding bit in the PIODIR
register must be set. If the corresponding
direction bit is set, the value written to the bit
in the PIODATA register will be driven at the
pin. A read of this register returns the value of
the signals currently on the PIO pins.
NOTE:
1. The value of any bit in this register is inverted
with respect to the pin if the corresponding bit
in the PIOPOL register is set, both in input and
output modes.
2. The values read from the PIO pins are not
synchronized; the user should be sure that the
data will not be changing when this register is
read, or should be aware that the bits which are
not static at that time may be inaccurate.

86. GPIO39_24_DIR: Program I/O Direction (offset: 0x004C)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RW

PIODIR

PIO Pin Direction
Sets the data direction on PIO pins
corresponding to bits in this register.
0: Set data direction to input.
1: Set data direction to output.
The values driven onto the PIO pins are
controlled by the PIOPOL and PIODATA
registers.

87. GPIO39_24_POL: PIO Pin Polarity (offset: 0x0050)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RW

PIOPOL

PIO Pin Polarity
Sets the polarity of data on PIO pins
corresponding to bits in this register.
0: Maintain original polarity
1: Invert existing polarity
NOTE: The polarity controls affect both input
and output modes.

PGMT7620_V.1.0_040503

Initial Value
PC

Initial Value
0x0

Initial Value
0x0

Page 89 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

88. GPIO39_24_SET: Set PIO Pin Data Bit (offset: 0x0054)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RC

PIOSET

PIO Pin Set
Sets the corresponding bit in the PIODATA
output register.
0: No effect.
1: Set the selected PIODATA bit.

89. GPIO39_24_RESET: Clear PIO Pin Data Bit (offset: 0x0058)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RC

PIORESET

PIO Pin Reset
Clears the corresponding bit in the PIODATA
output register.
0: No effect.
1: Clear the selected PIODATA bit.

90. GPIO39_24_TOG: Toggle PIO Pin Data Bit (offset: 0x005C)
Bits
Type
Name
Description
31:16

-

-

Reserved

15:0

RC

PIOTOG

PIO Pin Toggle
Toggles the corresponding bit in the PIODATA
output register.
0: No effect.
1: Invert the selected PIODATA bit.

91. GPIO71_40_INT: PIO Pin Interrupt Status (offset: 0x0060)
Bits
Type
Name
Description
31:0

RC

PIOINT

PGMT7620_V.1.0_040503

PIO Pin Interrupt
A PIOINT bit is set when its corresponding PIO
pin changes value and the edge for that pin is
enabled via the PIORMASK or PIOFMASK
register. The pin must be set as an input in the
PIODIR register to generate an interrupt.
Read
0: No change detected.
1: Change detected.
Write
All bits are cleared by writing 1 to either this
register or the PIOEDGE register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Page 90 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

92. GPIO71_40_EDGE: PIO Pin Edge Status (offset: 0x0064)
Bits
Type
Name
Description
31:0

RC

PIOEDGE

The PIOEDGE bits have different meanings
depending on whether the interrupt for that
pin is enabled via the PIORMASK or PIOFMASK
register.
Read
If the PIO PIN Interrupt for this PIO pin is
asserted, the corresponding PIOEDGE bit
indicates whether a falling or rising edge
triggered the interrupt.
0: Interrupt triggered by falling edge.
1: Interrupt triggered by rising edge.
If the interrupt is masked (disabled), the
PIOEDGE bit is set on either a rising or falling
edge and remains set until cleared by firmware.
Bits corresponding to pins that are not set as
inputs will never be set.
Write
All bits are cleared by writing 1 to either this
register or the PIOINT register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.

93. GPIO71_40_RMASK: PIO Pin Rising Edge Interrupt Mask (offset: 0x0068)
Bits
Type
Name
Description
31:0

RW

PIORMASK

PIO Pin Rising Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
0 to a 1, i.e. a rising edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.

94. GPIO71_40_FMASK: PIO Pin Falling Edge Interrupt Mask (offset: 0x006C)
Bits
Type
Name
Description
31:0

RW

PIOFMASK

PGMT7620_V.1.0_040503

PIO Pin Falling Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
1 to a 0, i.e. a falling edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Page 91 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

95. GPIO71_40_DATA: PIO Pin Data (offset: 0x0070)
Bits
Type
Name
Description
31:0

RW

PIODATA

PIO Pin Data
These bits are used for driving or sensing static
signals on the PIO pins. To drive a value onto a
PIO pin, the corresponding bit in the PIODIR
register must be set. If the corresponding
direction bit is set, the value written to the bit
in the PIODATA register will be driven at the
pin. A read of this register returns the value of
the signals currently on the PIO pins.
NOTE:
1. The value of any bit in this register is inverted
with respect to the pin if the corresponding bit
in the PIOPOL register is set, both in input and
output modes.
2. The values read from the PIO pins are not
synchronized; the user should be sure that the
data will not be changing when this register is
read, or should be aware that the bits which
are not static at that time may be inaccurate.

96. GPIO71_40_DIR: PIO Pin Direction (offset: 0x0074)
Bits
Type
Name
Description
31:0

RW

PIODIR

PIO Pin Direction
Sets the data direction on PIO pins
corresponding to bits in this register.
0: Set the data direction on this pin to input.
1: Set the data direction on this pin to output.
The values driven onto the PIO pins are
controlled by the PIOPOL and PIODATA
registers.

97. GPIO71_40_POL: PIO Pin Polarity (offset: 0x0078)
Bits
Type
Name
Description
31:0

RW

PIOPOL

PGMT7620_V.1.0_040503

PIO Pin Polarity
Sets the polarity of data on PIO pins
corresponding to bits in this register.
0: Maintain original polarity
1: Invert existing polarity
NOTE: The polarity controls affect both input
and output modes.

Initial Value
PC

Initial Value
0x0

Initial Value
0x0

Page 92 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

98. GPIO71_40_SET: Set PIO Pin Data Bit (offset: 0x007C)
Bits
Type
Name
Description
31:0

RC

PIOSET

PIO Pin Set
Sets the corresponding bit in the PIODATA
output register.
0: No effect.
1: Set the selected PIODATA bit.

99. GPIO71_40_RESET: Clear PIO Pin Data bit (offset: 0x0080)
Bits
Type
Name
Description
31:0

RC

PIORESET

PIO Pin Reset
Clears the corresponding bit in the PIODATA
output register.
0: No effect.
1: Clear the selected PIODATA bit.

100. GPIO71_40_TOG: Toggle PIO Pin Data bit (offset: 0x0084)
Bits
Type
Name
Description
31:0

RC

PIOTOG

PIO Pin Toggle
Toggles the corresponding bit in the PIODATA
output register.
0: No effect.
1: Invert the selected PIODATA bit.

101. GPIO72_INT: PIO Pin Interrupt Status (offset: 0x0088)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

RC

PIOINT

PIO Pin Interrupt
A PIOINT bit is set when its corresponding PIO
pin changes value and the edge for that pin is
enabled via the PIORMASK or PIOFMASK
register. The pin must be set as an input in the
PIODIR register to generate an interrupt.
Read
0: No change detected.
1: Change detected.
Write
All bits are cleared by writing 1 to either this
register or the PIOEDGE register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.

102. GPIO72_EDGE: PIO Pin Edge Status (offset: 0x008C)
Bits
Type
Name
Description
31:1

-

-

PGMT7620_V.1.0_040503

Reserved

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Initial Value
-

Page 93 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

Bits

Type

Name

Description

0

RC

PIOEDGE

The PIOEDGE bits have different meanings
depending on whether the interrupt for that
pin is enabled via the PIORMASK or PIOFMASK
register.
Read
If the PIO PIN Interrupt for this PIO pin is
asserted, the corresponding PIOEDGE bit
indicates whether a falling or rising edge
triggered the interrupt.
0: Interrupt triggered by falling edge.
1: Interrupt triggered by rising edge.
If the interrupt is masked (disabled), the
PIOEDGE bit is set on either a rising or falling
edge and remains set until cleared by firmware.
Bits corresponding to pins that are not set as
inputs will never be set.
Write
All bits are cleared by writing 1 to either this
register or the PIOINT register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.

103. GPIO72_RMASK: PIO Pin Rising Edge Interrupt Mask (offset: 0x0090)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

RW

PIORMASK

PIO Pin Rising Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
0 to a 1, i.e. a rising edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.

104. GPIO72_FMASK: PIO Pin Falling Edge Interrupt Mask (offset: 0x0094)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

RW

PIOFMASK

PIO Pin Falling Edge Interrupt Mask
Masks the PIO interrupt indicating when data
on the corresponding PIO pin transitions from a
1 to a 0, i.e. a falling edge.
0: No mask
1: Mask
NOTE: Edge detection is done after the polarity
is adjusted according to the PIOPOL register.

PGMT7620_V.1.0_040503

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Page 94 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

105. GPIO72_DATA: PIO Pin Data (offset: 0x0098)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

RW

PIODATA

PIO Pin Data
These bits are used for driving or sensing static
signals on the PIO pins. To drive a value onto a
PIO pin, the corresponding bit in the PIODIR
register must be set. If the corresponding
direction bit is set, the value written to the bit
in the PIODATA register will be driven at the
pin. A read of this register returns the value of
the signals currently on the PIO pins.
NOTE:
1. The value of any bit in this register is inverted
with respect to the pin if the corresponding bit
in the PIOPOL register is set, both in input and
output modes.
2. The values read from the PIO pins are not
synchronized; the user should be sure that the
data will not be changing when this register is
read, or should be aware that the bits which are
not static at that time may be inaccurate.

106. GPIO72_DIR: PIO Pin Direction (offset: 0x009C)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

RW

PIODIR

PIO Pin Direction
Sets the data direction on PIO pins
corresponding to bits in this register.
0: Set the data direction on this pin to input.
1: Set the data direction on this pin to output.
The values driven onto the PIO pins are
controlled by the PIOPOL and PIODATA
registers.

107. GPIO72_POL: PIO Pin Polarity (offset: 0x00A0)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

RW

PIOPOL

PIO Pin Polarity
Sets the polarity of data on PIO pins
corresponding to bits in this register.
0: Maintain original polarity
1: Invert existing polarity
NOTE: The polarity controls affect both input
and output modes.

PGMT7620_V.1.0_040503

Initial Value
PC

Initial Value
0x0

Initial Value
0x0

Page 95 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

108. GPIO72_SET: Set PIO Pin Data Bit (offset: 0x00A4)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

W

PIOSET

PIO Pin Set
Sets the corresponding bit in the PIODATA
output register.
0: No effect.
1: Set the selected PIODATA bit.

109. GPIO72_RESET: Clear PIO Pin Data Bit (offset: 0x00A8)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

W

PIORESET

PIO Pin Reset
Clears the corresponding bit in the PIODATA
output register.
0: No effect.
1: Clear the selected PIODATA bit.

110. GPIO72_TOG: Toggle PIO Pin Data Bit (offset: 0x00AC)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

W

PIOTOG

PIO Pin Toggle
Toggles the corresponding bit in the PIODATA
output register.
0: No effect.
1: Invert the selected PIODATA bit.

PGMT7620_V.1.0_040503

Initial Value
0x0

Initial Value
0x0

Initial Value
-

0x0

Page 96 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2

2.9 I C Controller
2.9.1 Features
2
 Programmable I C bus clock rate
2
 Supports the Synchronous Inter-Integrated Circuits (I C) serial protocol
 Bi-directional data transfer
 Programmable address width up to 8 bits
 Sequential byte read or write capability
 Device address and data address can be transmitted for device, page and address selection
 Supports Standard mode and Fast mode
2.9.2 Block Diagram

SCLK
Clock Control
RST_N
CLK

L_SCLK
SCLK_OE_N

I2C
Configuration
Registers

State Machine

PB_I2C_SEL

L_SD

PB_WE

Data Holding
Registers

Serdes

SD_OE_N

PB_RE
PB_ADDR

SDOUT

PalmBus
Interface

PB_WDATA
PB_I2C_RDATA

Arbiter

PB_I2C_WAIT

Figure 2-7 I2C Controller Block Diagram

PGMT7620_V.1.0_040503

Page 97 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.9.3 List of Registers
No.
Offset
Register Name
111
112
113

0x0000
0x0004
0x0008

CONFIG
CLKDIV
DEVADDR

Description

99

2

99

2

100

2

100

2

100

2

101

2

101

2

102

2

102

I C Configuration
I C Clock Divisor
I C Device Address

114

0x000C

ADDR

I C Address

115

0x0010

DATAOUT

I C Data Out

116
117
118
119

0x0014
0x0018
0x001C
0x0020

DATAIN
STATUS
STARTXFR
BYTECNT

PGMT7620_V.1.0_040503

Page

2

I C Data In
I C Status
I C Transfer Start
I C Byte Counter

Page 98 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.9.4 Register Descriptions (base: 0x1000_0900)
2

111. CONFIG: I C Configuration Register (offset: 0x0000)
Bits
Type
Name
Description

Initial Value

31:8

-

-

Reserved

-

7:5

RW

ADDRLEN

Address Length
The value written to this register plus one
indicates the number of address bits to be
transferred from the I2C ADDR register.
0: Transfers a 1-bit address
1: Transfers a 2-bit address, etc.

0x0

4:2

RW

DEVADLEN

Device Address Length
The value written to this register plus one
indicates the number of device address bits to
be transferred from the DEVADDR register. This
field should be programmed to 6 for
compliance with I2C bus protocol.

0x0

1

RW

ADDRDIS

Address Disable
Selects whether the address is included in
transmission.
0: Normal transfers occur with the address
included in the transfer, followed by read or
write data.
1: The controller reads or writes serial data
without transferring the address.

0x0

0

RW

DEVADDIS

Device Address Disable
0: The device address is transmitted before the
data address.
1: The controller does not transfer the device
address.
NOTE:
1. If this bit is set, the ADDRDIS bit is ignored,
and an address is always transmitted.
2
2. Most I C slave devices require a device
address to be transmitted; this bit should
typically be set to 0.

0x0

2

112. CLKDIV: I C Clock Divisor Register (offset: 0x0004)
Bits
Type
Name
Description
31:16

-

-

PGMT7620_V.1.0_040503

Reserved

Initial Value
0x0

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Bits

Type

Name

Description

15:0

RW

CLKDIV

Clock Divisor
The value written to this register is used to
generate the I2C bus SCLK signal by applying
the following equation:
SCLK frequency = 40 MHz / ( 2 x CLKDIV )
NOTE:
1. Only values of 8 and above are valid.
2
2. Due to synchronization between the I C
internal clock and the system clock, the exact
equation is actually
SCLK frequency = PB_CLK frequency / ((2 x
CLKDIV) + 5).
For most systems, CLKDIV is usually
programmed to very larger numbers since the
system clock frequency should be orders of
magnitude faster than the I2C bus clock. These
results in the synchronization errors being
insignificant and the exact equation
approximating the simpler one given above.

Initial Value
0x0

2

113. DEVADDR: I C Device Address Register (offset: 0x0008)
Bits
Type
Name
Description
31:7
6:0

-

-

RW

DEVADDR

Reserved
2

I C Device Address
This value is transmitted as the device address,
if DEVADDIS bit in the CONFIG register is not set
to 1.

Initial Value
0x0
0x0

2

114. ADDR: I C Address Register (offset: 0x000C)
Bits
Type
Name
Description
31:8
7:0

-

-

RW

ADDR

Reserved
2

I C Address
These bits store the 8-bits of address to be sent
to the external I2C slave devices when the
ADDRDIS bit is 0.

Initial Value
0x0
0x0

2

115. DATAOUT: I C Data Out Register (offset: 0x0010)
Bits
Type
Name
Description
31:8
7:0

RW

DATAOU

PGMT7620_V.1.0_040503

Reserved
2

I C Data Out
These bits store the 8-bits of data to be written
to the external I2C slave devices during a write
transfer.

Initial Value
0x0
0x0

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2

116. DATAIN: I C Data In Register (offset: 0x0014)
Bits
Type
Name
Description
31:8

-

-

Reserved

7:0

RO

DATAIN

I C Data In
These bits store the 8-bits of data received from
the external I2C slave devices during a read
transaction. The DATARDY bit in the STATUS
register is set to 1 when data is valid in this
register.

2

Initial Value
0x0
0x0

2

117. STATUS: I C Status Register (offset: 0x0018)
Bits
Type
Name
Description

Initial Value

31:5

-

-

Reserved

0x0

4

RO

STARTERR

Start Overflow Error
0: Indicates firmware is writing to the STARTXFR
register when the BUSY bit is cleared.
1: Indicates an overflow error occurred. The
STARTXFR register is written and a transfer is
in progress. When this occurs, the write to
the STARTXFR register is ignored.

0x0

3

RO

ACKERR

I C Acknowledge Error Detect
0: Indicates firmware is writing to the STARTXFR
register.
1: Indicates the Host controller did not receive
a proper acknowledge from the I2C slave
device after the transmission of a device
address, address, or data out.

2

RO

DATARDY

I C Data Ready for Read
This bit indicates that the receive buffer
contains valid data.
0: Indicates firmware is reading the DATAIN
register.
1: Indicates data is received from an I2C slave
device and is transferred from the interface
shift register to the DATAIN register.

1

RO

SDOEMPTY

I C Serial Data Out Register Empty
This bit indicates that the transmit data buffer
is empty.
0: Indicates the DATAOUT register is being
written to by software.
1: Indicates when transmit data is transferred
from the DATAOUT register to the interface
shift register. Firmware may write to the
DATAOUT register when this bit is 1.

PGMT7620_V.1.0_040503

2

0x0

2

0x0

2

0x1

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Bits

Type

Name

Description

0

RO

BUSY

I C State Machine Busy
0: The I2C interface is idle. Firmware may
initiate an I2C transfer.
1: Indicates the I2C interface is active, and
firmware should not modify any I2C host
controller.

2

Initial Value
0x0

2

118. STARTXFR: I C Transfer Start Register (offset: 0x001C)
Bits
Type
Name
Description

Initial Value

31:2

-

-

Reserved

0x0

1

RW

NODATA

No Data Transfer
Initiate transfers without transferring data.
When this register is written with this bit set, an
address-only transaction is initiated. If
DEVADDIS is 0, the device address, direction,
address and stop condition are transmitted to
the I2C slave device.
If DEVADDIS is 1, the address and stop
condition are transmitted to the I2C slave
device. This bit should be written with a 0 for
normal I2C bus accesses.
NOTE: ADDRDIS is ignored if this bit is set for a
transaction.

0x0

0

RW

RWDIR

Read/Write Direction
When this register is written with this bit set, a
read transaction is initiated; when written with
this bit reset, a write transaction is initiated.
NOTE: This bit is shifted out to the I2C slave
device after the device address; if DEVADDIS is
1, this bit is not shifted out to the device.

0x0

2

119. BYTECNT: I C Byte Counter Register (offset: 0x0020)
Bits
Type
Name
Description

Initial Value

31:6

-

-

Reserved

0x0

5:0

RW

BYTCNT

Byte Count
Used for sequential reads/writes. The value
written to this register plus one indicates the
number of data bytes to be written to or read
from the external I2C slave device. If its value is
non-zero, multiple sequential read or write
cycles will be issued with a single address
(and/or device address).

0x0

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2

2.9.4.1 I C Programming Description
Write Operation: (Single)
S

DEV_ADR

A(S)

SUB_ADR

A(S)

DATA

A(S)

P

S

DEV_ADR

A(S)

SUB_ADR

A(S)

DATA

A(M)

P

NOTE:
The bit-width of DEV_ADR is defined in REG(CONFIG) bit[7:5]
The bit-width of SUB_ADR is defined in REG(CONFIG) bit[4:2]
NOTE: As REG(CONFIG) bit[1]=1'b1, the SUB_ADR field will be absent.
(the waveform will be shown as below.)
S

DEV_ADR

A(S)

DATA

A(S)

P

NOTE: As REG(CONFIG) bit[0]=1'b1, the DEV_ADR field will be absent.
(the waveform will be shown as below.)
S

SUB_ADR

A(S)

DATA

A(S)

P

Sequence Write Operation:
Action-1

S

Action-2

DEV_ADR
RS

A(S)

DEV_ADR

SUB_ADR
A(S)

A(S)
DATA

DATA
A(S)

A(S)
P

Action-1: SET REG(STARTXFR) bit[2]=1'b1, the “STOP” 
 field disappears.
Action-2: SET REG(STARTXFR) bit[2]=1'b0, the “STOP” 
 field appears.

S

START bit

A(S)

ACKNOWLEDGE BY DEVICE

P

STOP bit

A(M)

ACKNOWLEDGE BY HOST

Initialization:
1. Configure the REG(CLKDIV) to decide the clock frequency of I2C.
2. Configure the bit width of DEV_ADDR and SUB_ADDR by configure REG(CONFIG).
Read/Write Operation:
1. Write the DEV_ADDR and SUB_ADDR to REG(DEVADDR) & REG(ADDR).
2. Write the DATAout (REG(DATAOUT)) for write operation.
3. Write the operation cfg by REG(STARTXFR) to kick off the command.
4. Read the BUSY status by REG(STATUS) to monitor if the operation is done.
5. Read back the REG(DATAIN) for read operation.

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Multiple Data Transfer: (write operation.)
E.g. we want to write (n+1) beats data by I2C
S

DEV_ADR

A(S)

SUB_ADR

A(S)

DATA

A(S)

DATA

...

A(S)

P

(N+1) bytes
Burst Write Operation:
1) Write the DEV_ADDR and SUB_ADDR to REG(DEVADDR) & REG(ADDR)
2) Write (N) to REG(BYTECNT).
3) Write the REG(DATAOUT) for write operation.
4) Write the operation cfg by REG(STARTXFR) to kick off the command.
5) Read the SDOEMPTY bit by REG(STATUS) to monitor if the data is sent.
6) Quit when all data is written, otherwise put the new data to the REG(DATAOUT) for write operation.
7) Return to step 4.
Multiple Data Transfer: (read operation.)
E.g. we want to read (n+1) beats data by I2C
S

DEV_ADR

A(S)

SUB_ADR

A(S)

DATA

A(M)

...

DATA

A(M)

P

(N+1) bytes
Burst Read Operation:
1) Write the DEV_ADDR and SUB_ADDR to REG(DEVADDR) & REG(ADDR)
2) Write (N) to REG(BYTECNT).
3) Write the operation cfg by REG(STARTXFR) to kick off the command.
4) Read the DATARDY bit by REG(STATUS) to monitor if the data is obtained.
5) Read REG(DATAIN) and return to step-4 until all bytes are read.

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MT7620 PROGRAMMING GUIDE
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2.10 NAND Flash Controller
2.10.1 Features
 Supports read/erase/page program NAND flash memory.
 Hardware ECC engine. (Hardware generating and software correcting)
 Supports NAND flash memory with 512-byte and 2048-byte page size.
 Indirect access for special commands.
 Configurable write protect register.
 Little / bit ending operation.
2.10.2 Normal Mode Flow
Under this mode, CPU must first configure the command register of the controller register. After configuration
of the command register, the controller sends serial commands and addresses to NAND flash memory. Then a
byte data is read (write) from the data buffer (NAND flash) to NAND flash (data buffer). At the same time, the
CPU or GDMA is responsible for writing (reading) data into (from) the data buffer.
CPU configures GDMA

CPU configures NAND
controller

CPU kicks NAND controller

NAND controller sends
command / address

CPU or GDMA read/writes
data buffer

NAND controller done &
interrupt sent to CPU

Figure 2-8 Normal Mode Flow

2.10.3 ECC
The ECC engine uses Hamming code. The Hamming code generates a 24-bit ECC per 512 bytes in order to
perform a 2-bit detection and a 1-bit correction. In our application, hardware performs ECC error detection,
and software performs 1-bit ECC error correction.
The following table shows how the 24-bit ECC was generated from 512-byte data.

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1 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

P8*

2 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

P8

3 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
4 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

P8*

509 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

P8*

510 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

P8

511 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

P8*

512 byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

P8

P1

P1*
P2

P1

P1*

P2*
P4

P1

P1*

P1

P2

P8

P16
*
P16

P16
*

P32
*

P32

P2048
*

P2048

P16

P1*

P2*
P4*

Figure 2-9 24-bit ECC Generated from 512-Byte Data
P1 = bit7 ^ bit5 ^ bit3 ^ bit1 ^ P1
P2 = bit7 ^ bit6 ^ bit3 ^ bit2 ^ P2
P4 = bit7 ^ bit6 ^ bit5 ^ bit 4 ^ P4
P8 = bit7 ^ bit6 ^ bit5 ^ bit 4 ^ P4 ^ bit3 ^ bit2 ^ bit1 ^ bit0 ^ P8
P1* = bit8 ^ bit6 ^ bit4 ^ bit2 ^ P1*
P2* = bit5 ^ bit4 ^ bit1 ^ bit0 ^ P2*
P4* = bit3 ^ bit2 ^ bit1 ^ bit 0 ^ P4*
P8* = bit7 ^ bit6 ^ bit5 ^ bit 4 ^ P4 ^ bit3 ^ bit2 ^ bit1 ^ bit0 ^ P8*
The following table shows how the 24-bit ECC bits are arranged in three bytes. The first and second ECC bytes
contains row parity bits. The third ECC byte contains six column parity bits, plus two row parity bits.

ECC

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ECC 0

P64

P64*

P32

P32*

P16

P16*

P8

P8*

ECC 1

P1024

P1024*

P512

P512*

P256

P256*

P128

P128*

ECC 2

P4

P4*

P2

P2*

P1

P1*

P2048

P2048*

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The figure below shows the hardware ECC detection flow chart.
New ECC generated during
data read
XOR previous ECC with new
ECC

All results = 0

N

Y
No error

Error detected :
11 bits data = 1 (correctable error)
1 bit data = 1 (ECC error)

Figure 2-10 Hardware ECC Detection Flowchart

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2.10.4 List of Registers
No.
Offset
Register Name

Description

Page

120

0x0010

CTRL0

Control 0

109

121

0x0014

TRANS_CFG

Transfer Configuration

109

122

0x0018

CMD1

Command 1

110

123

0x001C

CMD2

Command 2

110

124

0x0020

CMD3

Command 3

111

125

0x0024

ADDR

Address

111

126

0x0028

DATA

Data

111

127

0x0030

STATUS

ECC Status

111

128

0x0034

INT_ENA

Interrupt Enable

112

129

0x0038

INT_STA

Interrupt Status

112

130

0x003C

CTRL1

Control 1

112

131

0x0040

ECC_PAGE1

Error Correction Code Page 1

113

132

0x0044

ECC_PAGE2

Error Correction Code Page 2

113

133

0x0048

ECC_PAGE3

Error Correction Code Page 3

113

134

0x004C

ECC_PAGE4

Error Correction Code Page 4

113

135

0x0050

ECC_ERR_PAGE1

ECC Error Information Page 1

113

136

0x0054

ECC_ERR_PAGE2

ECC Error Information Page 2

114

137

0x0058

ECC_ERR_PAGE2

ECC Error Information Page 3

114

138

0x005C

ECC_ERR_PAGE3

ECC Error Information Page 4

114

139

0x0060

ADDR2

Address 2

115

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2.10.5 Register Descriptions (base: 0x1000_0800)
120. CTRL0: Control 0 (offset: 0x0010)
Bits
Type
Name

Description

31:24

-

-

Reserved

0x0

23:16

RW

TWAITB

Time Wait Busy Signal
Dummy time period to wait for a busy signal =
clock * (TWAITB + 1)

0x0

15:12

RW

THOLD

Time Hold
Hold time duration = clock * (THOLD+1)

0x0

11:8

RW

TPERIOD

Time Period
Period time duration = clock * (TPERIOD+1)

0x0

7:4

RW

TSETUP

Time Setup
Setup time duration = clock * (TSETUP+1)

0x0

3:2

RW

BURST_SIZE

Burst Size
0: 1 DW
1: 2 DW
2: 4 DW
3: 8 DW

0x0

1

RW

DBUF_CLR

Clear Data Buffer
0: No effect
1: Clear

0x0

0

RW

WP

Write Protect Enable
0: Disable
1: Enable

0x0

121. TRANS_CFG: Transfer Configuration (offset: 0x0014)
Bits
Type
Name
Description

Initial Value

Initial Value

31:30

-

-

Reserved

29:20

RW

BNUM_DATA

Byte Number Of Data
Sets the number of bytes to be transferred.
(unit: bytes)

19

-

-

Reserved

0x0

18:16

RW

BNUM_ADDR

Byte Number Of Addresses
Sets the number of bytes in an address.
(unit: bytes)
NOTE: Maximum number is 4

0x3

15:14

-

-

Reserved

0x0

13:12

RW

BNUM_CMD3

Byte Number Of Commands 3
Sets the number of bytes in a command.
(unit: bytes)

0x0

11:10

RW

BNUM_CMD2

Byte Number Of Commands 2
Sets the number of bytes in a command.
(unit: bytes)

0x0

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0x528

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Bits

Type

Name

Description

9:8

RW

BNUM_CMD1

Byte Number Of Commands 1
Sets the number of bytes in a command.
(unit: bytes)

Initial Value
0x1

7

RW

RESPB_DATA

Respect busy signal after data phase.
0: Disable
1: Enable

0x0

6

RW

RESPB_ADDR

Respect busy signal after address phase.
0: Disable
1: Enable

0x0

5

RW

RESPB_CMD3

Respect busy signal after command 3 phase.
0: Disable
1: Enable

0x0

4

RW

RESPB_CMD2

Respect busy signal after command 2 phase.
0: Disable
1: Enable

0x0

3

RW

ECC_ENA

Error Correction Code (ECC) Enable
0: Disable
1: Enable
NOTE: In read transfers, HW ECC check function
is active. In write transfers, HW ECC generate
function will be active.

0x0

2

RW

DMA_ENA

DMA Enable
Sets the GDMA to read or write data to the data
buffer.
0: CPU (default)
1: GDMA

0x0

1

RW

WR_TRANS

Sets a transfer to read or write.
0: Read
1: Write

0x0

0

W1C

KICK_TRANS

Kicks a NAND flash transfer.
0: No transfer
1: Kick a transfer
NOTE: This bit will auto-clear

0x0

122. CMD1: Command 1 (offset: 0x0018)
Bits
Type
Name

Description

31:24

-

-

Reserved

0x0

23:16

RW

CMD1_BYTE3

3rd byte of command 1

0x0

15:8

RW

CMD1_BYTE2

2nd byte of command 1

0x0

7:0

RW

CMD1_BYTE1

1st byte of command 1

0x0

Initial Value

123. CMD2: Command 2 (offset: 0x001C)

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Bits

Type

Name

Description

31:24

-

-

Reserved

Initial Value
0x0

23:16

RW

CMD2_BYTE3

3rd byte of command 2

0x0

15:8

RW

CMD2_BYTE2

2nd byte of command 2

0x0

7:0

RW

CMD2_BYTE1

1st byte of command 2

0x0

124. CMD3: Command 3 (offset: 0x0020)
Bits
Type
Name

Description

31:24

-

-

Reserved

0x0

23:16

RW

CMD3_BYTE3

3rd byte of command 3

0x0

15:8

RW

CMD3_BYTE2

2nd byte of command 3

0x0

7:0

RW

CMD3_BYTE1

1st byte of command 3

0x0

Initial Value

125. ADDR: Address (offset: 0x0024)
Bits
Type
Name

Description

31:24

RW

ADD_BYTE4

4th byte of NAND memory address

0x0

23:16

RW

ADD_BYTE3

3rd byte of NAND memory address

0x0

15:8

RW

ADD_BYTE2

2nd byte of NAND memory address

0x0

7:0

RW

ADD_BYTE1

1st byte of NAND memory address

0x0

126. DATA: Data (offset: 0x0028)
Bits
Type
Name

Description

31:0

Data for read / write

RW

DATA

Initial Value

Initial Value
0x0

127. STATUS: ECC Status (offset: 0x0030)
Bits
Type
Name

Description

31:17

-

-

Reserved

0x0

16:8

RO

DEC_BYTE

ECC Decode Failed Byte Address
Shows the address of a byte that failed ECC
decoding.

0x0

7

-

-

Reserved

0x0

6:4

RO

DEC_BIT

ECC Decode Failed Byte Address
Shows the address of a bit that failed ECC
decoding.

0x0

3

-

-

Reserved

0x0

2

RO

ND_RB_N

NAND Flash Ready
0: Busy
1: Ready

0x1

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Bits

Type

Name

Description

1

RO

DEC_ERR

Decode Error
Shows the ECC decode check status.
0: No error
1: Correctable error or ECC error

Initial Value
0x0

0

RO

BUSY

NAND flash controller is busy.
0: Idle
1: Busy

0x0

128. INT_ENA: Interrupt Enable (offset: 0x0034)
Bits
Type
Name
Description

Initial Value

31:17

-

-

Reserved

0x0

7:0

RW

INT_ENA

Interrupt Enable Control
0: Disable
1: Enable

0x0

129. INT_STA: Interrupt Status (offset: 0x0038)
Bits
Type
Name
Description

Initial Value

31:17

-

-

Reserved

0x0

7

W1C

RX_BUF_ERR1

Rx Buffer Error 1 Interrupt
Asserts when kicking a new transfer but the Rx
buffer is not empty.

0x0

6

W1C

TX_BUF_ERR1

Tx Buffer Error 1 Interrupt
Asserts when kicking a new transfer but the Tx
buffer is not empty.

0x0

5

W1C

RX_BUF_ERR0

Rx Buffer Error 0 Interrupt
Asserts when transfer is complete but the Rx
buffer is not empty.

0x0

4

W1C

TX_BUF_ERR0

Tx Buffer Error 0 Interrupt
Asserts when transfer is compete but the Tx
buffer is not empty.

0x0

3

W1C

ECC_ERR

ECC Check Error Interrupt
Asserts when an ECC error is detected.

0x0

2

W1C

RX_BUF_RRDY

Rx Buffer Read Ready Interrupt
Asserts when the Rx buffer is ready for reads.

0x0

1

W1C

TX_BUF_WRDY

Tx Buffer Write Ready Interrupt
Asserts when the Tx buffer is ready for writes.

0x0

0

W1C

XFER_DONE

Transfer Done Interrupt
Asserts when transfer is complete.

0x0

130. CTRL1: Control 1 (offset: 0x003C)
Bits
Type
Name

Description

31:20

Reserved

19:16

RW

ECC_BYTE3_LOC

PGMT7620_V.1.0_040503

Initial Value
0x0
rd

The location of 3 ECC byte in spare 16-byte

0x8

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Bits

Type

Name

Description

15:12

RW

ECC_BYTE2_LOC

The location of 2 ECC byte in spare 16-byte

Initial Value
nd

0x7

st

11:8

RW

ECC_BYTE1_LOCT

The location of 1 ECC byte in spare 16-byte

0x6

7:2

-

-

Reserved

0x0

1

RW

DATA_BYTE_SWAP

Data Byte Swap Enable
0: Disable
1: Enable

0x0

0

RW

PAGE_SIZE

Page Size
0: 512 bytes per page
1: 2048 bytes per page

0x0

131. ECC_PAGE1: Error Correction Code Page 1 (offset: 0x0040)
Bits
Type
Name
Description

Initial Value

31:24

-

-

Reserved

0x0

23:0

RO

ECC_PAGE1

HW ECC computing result for page1

0x0

132. ECC_PAGE2: Error Correction Code Page 2 (offset: 0x0044)
Bits
Type
Name
Description

Initial Value

31:24

-

-

Reserved

0x0

23:0

RO

ECC_PAGE2

HW ECC computing result for page 2

0x0

133. ECC_PAGE3: Error Correction Code Page 3 (offset: 0x0048)
Bits
Type
Name
Description

Initial Value

31:24

-

-

Reserved

0x0

23:0

RO

ECC_PAGE3

HW ECC computing result for page 3

0x0

134. ECC_PAGE4: Error Correction Code Page 4 (offset: 0x004C)
Bits
Type
Name
Description

Initial Value

31:24

-

-

Reserved

0x0

23:0

RO

ECC_PAGE4

HW ECC computing result for page 4

0x0

135. ECC_ERR_PAGE1: ECC Error Information Page 1 (offset: 0x0050)
Bits
Type
Name
Description

Initial Value

31:15

-

-

Reserved

0x0

14:6

RO

ECC_ERR_BYTE

HW ECC Failed Byte Address
Shows the address of a byte that failed ECC.

0x0

5

-

-

Reserved

0x0

4:2

RO

ECC_ERR_BIT

HW ECC Failed Bit Address
Shows the address of a bit that failed ECC.

0x0

1

-

-

Reserved

0x0

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Bits

Type

Name

Description

0

RO

ECC_ERR

HW ECC Failed
0: Pass
1: Fail

136. ECC_ERR_PAGE2: ECC Error Information Page 2 (offset: 0x0054)
Bits
Type
Name
Description

Initial Value
0x0

Initial Value

31:15

-

-

Reserved

0x0

14:6

RO

ECC_ERR_BYTE

HW ECC Failed Byte Address
Shows the address of a byte that failed ECC.

0x0

5

-

-

Reserved

0x0

4:2

RO

ECC_ERR_BIT

HW ECC Failed Bit Address
Shows the address of a bit that failed ECC.

0x0

1

-

-

Reserved

0x0

0

RO

ECC_ERR

HW ECC Failed
0: Pass
1: Fail

0x0

137. ECC_ERR_PAGE2: ECC Error Information Page 3 (offset: 0x0058)
Bits
Type
Name
Description

Initial Value

31:15

-

-

Reserved

0x0

14:6

RO

ECC_ERR_BYTE

HW ECC Failed Byte Address
Shows the address of a byte that failed ECC.

0x0

5

-

-

Reserved

0x0

4:2

RO

ECC_ERR_BIT

HW ECC Failed Bit Address
Shows the address of a bit that failed ECC.

0x0

1

-

-

Reserved

0x0

0

RO

ECC_ERR

HW ECC Failed
0: Pass
1: Fail

0x0

138. ECC_ERR_PAGE3: ECC Error Information Page 3 (offset: 0x005C)
Bits
Type
Name
Description

Initial Value

31:15

-

-

Reserved

0x0

14:6

RO

ECC_ERR_BYTE

HW ECC Failed Byte Address
Shows the address of a byte that failed ECC.

0x0

5

-

-

Reserved

0x0

4:2

RO

ECC_ERR_BIT

HW ECC Failed Bit Address
Shows the address of a bit that failed ECC.

0x0

1

-

-

Reserved

0x0

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Bits

Type

Name

Description

0

RO

ECC_ERR

HW ECC Failed
0: Pass
1: Fail

Initial Value
0x0

139. ADDR2: Address 2 (offset: 0x0060)
Bits
Type
Name

Description

31:24

-

-

Reserved

0x0

23:16

RW

ADD_BYTE7

7th byte of NAND memory address

0x0

15:8

RW

ADD_BYTE6

6th byte of NAND memory address

0x0

7:0

RW

ADD_BYTE5

5th byte of NAND memory address

0x0

PGMT7620_V.1.0_040503

Initial Value

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MT7620 PROGRAMMING GUIDE
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2.11 PCM Controller
2.11.1 Features
 PCM module provides PBUS interface for register configuration and data transfer
 Two clock sources are reserved for PCM circuit. (From internal clock generator, INT_PCM_CLK and
EXT_PCM_CLK)
 PCM module can drive a clock out (with fraction-N dividor) to an external codec.
 Up to 4 channels PCM are available. 4 to 128 slots are configurable.
 Each channel supports a-law (8-bit)/u-law (8-bit)/raw-PCM (8-bit and 16-bit) transfer.
 Hardware converter of a-law<->raw-16 and u-law <-> raw-16 are implemented in design.
2
 Support long (8 cycle)/short (1 cycle)/configurable (intervals are configurable, use to emulate I S
interface) FSYNC.
 DATA & FSYNC can be driven and sampled by either rising/falling of clock.
 Last bit of DTX can be configured as tri-stated on falling edge.
 Beginning of each slot is configurable by 10-bit registers on each channel.
 32-byte FIFO are available for each channel
 PCM interface can emulate I2S interface (only 16-bit data-width supported ).
 MSB/LSB order is configurable.
 Supports both a-law/u-law (8-bits) linear PCM(16-bit) and linear PCM(16-bit)  a-law/u-law (8-bit)
2.11.2 Block Diagram
PBUS

PCM Module
PCM Control
Status Register

RFIFO
(32 bytes)

DRAM

PBUS LTF

TFIFO
(32 bytes)

GDMA LTF

RFIFO
(32 bytes)

CH1

TFIFO
(32 bytes)

CH0

a/ulaw

a/ulaw

SYS clock domain
PCM clock domain
PCM IF/I2S
IF

Figure 2-11 PCM Controller Block Diagram

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Two clock domains are partitioned in this design. PCM converter (u-law < = > raw-16-bit and A-law < = > raw
16-bit) are implemented in PCM. The threshold of FIFO is configurable. When the threshold is reached, PCM (a)
triggers the DMA interface to notify external DMA engine to transfer data, and (b) triggers an interrupt to the
host.
The interrupt sources include:
 The threshold is reached.
 FIFO is under-run or over-run.
 A fault is detected at the DMA interface.
The A-law and u-law converter is implemented based on the ITU-G.711 A-law and u-law table. In this design,
both A-law/u-law(8-bit)  linear PCM (16-bit) and linear PCM (16-bit)  A-law/u-law (8-bit) are supported.
The data-flow from codec to PCM-controller (Rx-flow) is shown as below:
 The PCM controller latches the data from DRX at the indicated time slot and then writes it to FIFO. If FIFO
is full, the data is lost.
 When the Rx-FIFO reaches the threshold, two actions may be taken:
 When DMA_ENA=1, DMA_REQ is asserted to request a burst transfer. It rechecks the FIFO threshold
after DMA_END is asserted by GDMA. (GDMA should be configured before channel is enabled.)
 Assert the interrupt source to notify the host. The host can check RFIFO_AVAIL information then get
back the data from FIFO.
The data flow from the PCM controller to codec (Tx-flow) is shown below. After GDMA is configured, software
should configure and enable the PCM channel. The empty FIFO should behave as follows.
 When DMA_ENA=1, DMA_REQ is triggered to request a burst transfer. It then re-checks the FIFO
threshold after DMA_END is asserted by GDMA (a burst is completed).
 The Interrupt source is asserted to notify HOST. HOST writes the data to Tx-FIFO. After that, HOST
rechecks TFIFO_EMPTY information, and then writes more data if available.
NOTE: When DMA_ENA=1, the burst size of GDMA should be less than the threshold value.

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2.11.3 List of Registers
No.
Offset

Register Name

Description

Page

140

0x0000

GLB_CFG

Global Configuration

119

141

0x0004

PCM_CFG

PCM Configuration

120

142

0x0008

INT_STATUS

Interrupt Status

121

143

0x000C

INT_EN

Interrupt Enable

121

144

0x0010, 0x0110

CHA_FF_STATUSn

Channel A FIFO Status n

122

145

0x0014, 0x0114

CHB_FF_STATUSn

Channel B FIFO Status n

123

146

0x0020, 0x0120

CHA_CFGn

Channel A Configuration n

124

147

0x0024, 0x0124

CHnB_CFG

Channel B Configuration n

125

148

0x0030

FSYNC_CFG

PCM FSYNC Configuration

125

149

0x0034, 0x0134

CHA_CFG2

Channel A Configuration

126

150

0x0034, 0x0138

CHB_CFG2

Channel B Configuration

126

151

0x0040

IP_INFO

IP Address Information

127

152

0x0038

RSV_REG16

Reserved

127

153

0x0050

DIVCOMP_CFG

Integer Part of the Dividor

127

154

0x0054

DIVINT_CFG

Integer Part of the Dividor

127

155

0x0060

DIGDELAY_CFG

Digital Delay Configuration

127

156

0x0080

CH0_FIFO

Channel 0 FIFO

129

157

0x0084

CH1_FIFO

Channel 1 FIFO

129

158

0x0088

CH2_FIFO

Channel 2 FIFO

129

159

0x008C

CH3_FIFO

Channel 3 FIFO

129

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2.11.4 Register Descriptions (base: 0x1000_2000)
140. GLB_CFG: (offset: 0x0000)
Bits
Type
Name

Description

Initial Value

31

RW

PCM_EN

PCM Enable
When disabled, all FSM of PCM are cleared to
their default value.
0: Disable
1: Enable

0x0

30

RW

DMA_EN

DMA Enable
0: Disable the DMA interface, transfer data
using software.
1: Enable the DMA interface, transfer data
using DMA.

0x0

29

RW

LBK_EN

Loopback Enable
0: Normal mode
1: Loopback
(Asyn-TXFIFO DTX DRX Asyn-RXFIFO)

0x0

28

RW

EXT_LBK_EN

External Loopback Enable
0: Normal mode
1: External loopback enable
(Ext-Codec DRX DTX Ext-Codec)

0x0

27:23

-

-

Reserved

0x0

22:20

RW

RFF_THRES

RXFIFO Threshold
When the threshold is reached, the host/DMA
is notified to fill FIFO. The threshold should be
>2 and <6.
When data in FIFO is under the threshold, the
following interrupts and GDMA are triggered.
 CH0T_THRES
 CH0R_THRES
 CH1T_THRES
 CH1R_THRES
(unit: word)

0x4

19

-

-

Reserved

0x0

18:16

RW

TFF_THRES

TXFIFO Threshold
When the threshold is reached, the host/DMA
is notified to fill FIFO.
It should be >2 and <6.
When data in FIFO is over the threshold, an
interrupt and DMA are triggered.
(unit: word)

0x4

15:4

-

-

Reserved

3:0

RW

CH_EN

Channels 3 to 0 Tx and Rx Enable
0: Disable
1: Enable

PGMT7620_V.1.0_040503

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141. PCM_CFG: (offset: 0x0004)
Bits
Type
Name

Description

31

-

-

Reserved for future.

0x0

30

RW

CLKOUT_EN

PCM Clock Out Enable
0: A PCM clock is provided from the external
Codec/OSC.
1: A PCM clock is provided from the internal
dividor.
NOTE: Normally, the register should be
asserted to 1. Also, it should be asserted after
configuring the divider and enabling the divider
clock.

0x0

29:28

-

-

Reserved

0x0

27

RW

EXT_FSYNC

FSYNC is provided externally
0: FSYNC is generated by internal circuit.
1: FSYNC is provided externally

0x0

26

RW

LONG_FSYNC

FSYNC Mode
0: Short FSYNC
1: Long FSYNC

0x0

25

RW

FSYNC_POL

FSYNC Polarity
0: FSYNC is low active
1: FSYNC is high active

0x1

24

RW

DTX_TRI

DTX Tri-State
Tristates DTX when the clock signal on the last
bit is has a falling edge.
0: Non- tristate DTX
1: Tristate DTX

0x1

23:3

-

-

Reserved

0x0

2:0

RW

SLOT_MODE

Sets the number of slots in each PCM frame.
0: 4 slots, PCM clock out/in should be 256 KHz.
1: 8 slots, PCM clock out/in should be 512 KHz.
2: 16 slots, PCM clock out/in should be 1.024
MHz.
3: 32 slots, PCM clock out/in should be 2.048
MHz.
4: 64 slots, PCM clock out/in should be 4.096
MHz.
5:128 slots, PCM clock out/in should be 8.192
MHz.
Other: Reserved.
NOTE: When using the external clock, the
frequency clock should be equal to PCM_clock
out. Otherwise, the PCM_CLKin should be 8.192
MHz.

0x0

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MT7620 PROGRAMMING GUIDE
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142. INT_STATUS: (offset: 0x0008)
Bits
Type
Name

Description

31:8

-

-

Reserved

0x0

7

R/W1C

CHT_DMA_
FAULT

Channel Tx DMA Fault Interrupt
Asserts when a fault has been detected in a CHTx DMA signal.

0x0

6

R/W1C

CHT_OVRUN

Channel Tx FIFO Overrun Interrupt
Asserts when the CH-Tx FIFO is overrun.

0x0

5

R/W1C

CHT_UNRUN

Channel Tx FIFO Underrun Interrupt
Asserts when the CH-Tx FIFO is underrun.

0x0

4

R/W1C

CHT_THRES

Channel Tx Threshold Interrupt
Asserts when the CH-Tx FIFO is lower than the
defined threshold.

0x0

3

R/W1C

CHR_DMA_FAULT

Channel Rx DMA Fault Interrupt
Asserts when a fault is detected in a CH-Rx
DMA signal.

0x0

2

R/W1C

CHR_OVRUN

Channel Rx Overrun Interrupt
Asserts when the CH-Rx FIFO is overrun.

0x0

1

R/W1C

CHR_UNRUN

Channel Rx Underrun Interrupt
Asserts when the CH-Rx FIFO is underrun.

0x0

0

R/W1C

CHR_THRES

Channel Rx Threshold Interrupt
Asserts when the CH-Rx FIFO is lower than the
defined threshold.

0x0

NOTE:
Read
0: Interrupt not asserted.
1: Interrupt asserted

Initial Value

Write
1: Clear the interrupt

143. INT_EN: (offset: 0x000C)
Bits
Type
Name

Description

Initial Value

31:8

RO

-

Reserved

0x0

7

RW

INT7_EN

INT_STATUS[7] Enable
Enables the Channel Tx DMA Fault Interrupt.
This interrupt asserts when a fault has been
detected in a CH-Tx DMA signal.

0x0

6

RW

INT6_EN

INT_STATUS[6] Enable
Enables the Channel Tx FIFO Overrun Interrupt.
This interrupt asserts when the CH-Tx FIFO is
overrun.

0x0

5

RW

INT5_EN

INT_STATUS[5] Enable
Enables the Channel Tx FIFO Underrun
Interrupt. This interrupt asserts when the CH-Tx
FIFO is underrun.

0x0

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Bits

Type

Name

Description

Initial Value

4

RW

INT4_EN

INT_STATUS[4] Enable
Enables the Channel Tx Threshold Interrupt.
This interrupt when the CH-Tx FIFO is lower
than the defined threshold.

0x0

3

RW

INT3_EN

INT_STATUS[3] Enable
Enables the Channel Rx DMA Fault Interrupt.
This interrupt when a fault is detected in a CHRx DMA signal.

0x0

2

RW

INT2_EN

INT_STATUS[2] Enable
Enables the Channel Rx Overrun Interrupt. This
interrupt when the CH-Rx FIFO is overrun.

0x0

1

RW

INT1_EN

INT_STATUS[1] Enable
Enables the Channel Rx Underrun Interrupt.
This interrupt when the CH-Rx FIFO is underrun.

0x0

0

RW

INT0_EN

INT_STATUS[0] Enable
Enables the Channel Rx Threshold Interrupt.
This interrupt asserts when the CH-Rx FIFO is
lower than the defined threshold.

0x0

NOTE:
0: Disable
1: Enable
144. CHA_FF_STATUSn: (offset: 0x0010, 0x0110) (n=0, 1)
Bits
Type
Name
Description

Initial Value

31:24

-

-

Reserved

0x0

23

R/
W1C

CHTX_DMA_FAULT

Tx DMA Fault Detected Interrupt
Asserts when a fault is detected in a Channel A
Tx DMA signal.

0x0

22

R/
W1C

CHTX_OVRUN

Tx Overrun Interrupt
Asserts when the Channel A Tx FIFO is overrun.

0x0

21

R/
W1C

CHTX_UNRUN

Tx FIFO Underrun Interrupt
Asserts when the Channel A Tx FIFO is
underrun.

0x0

20

R/
W1C

CHTX_THRES

Tx FIFO Below Threshold Interrupt
Asserts when the Channel A FIFO is lower than
the defined threshold.

0x1

19

R/
W1C

CHRX_DMA_FAULT

Rx DMA Fault Detected Interrupt
Asserts when a fault is detected in a Channel A
Rx DMA signal.

0x0

18

R/
W1C

CHRX_OVRUN

Rx FIFO Overrun Interrupt
Asserts when the Channel A Rx FIFO is overrun.

0x0

17

R/
W1C

CHRX_UNRUN

Rx FIFO Underrun Interrupt
Asserts when the Channel A Rx FIFO is
underrun.

0x0

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Bits

Type

Name

Description

16

R/
W1C

CHRX_THRES

Rx FIFO Below Threshold Interrupt
Asserts when the Channel A FIFO is lower than
the defined threshold.

Initial Value
0x0

15:8

-

-

Reserved

0x0

7:4

RO

CHRFF_AVCNT

Channel A RXFIFO Available Space Count
Counts the available space for reads in channel
A RXFIFO.
(unit: word)

0x0

3:0

RO

CHTFF_EPCNT

Channel A TXFIFO Available Space Count
Counts the available space for writes in channel
A TXFIFO.
(unit: word)

0x8

NOTE:
1. CHA_FF_STATUSn and CHB_FF_STATUSn registers have n=2 channels each, which together make up CHA0,
CHB0, CHA1, and CHB1. To configure a specific channel, select an offset in CHA_FF_STATUSn or
CHB_FF_STATUSn registers, where the first or second offset is indicated by n=0 or 1, respectively.
2. Where applicable,
Read
Write
0: Not asserted
1: Clear this bit.
1: Asserted
145. CHB_FF_STATUSn: (offset: 0x0014, 0x0114) (n=0, 1)
Bits
Type
Name
Description

Initial Value

31:24

-

-

Reserved

0x0

23

R/
W1C

CHTX_DMA_
FAULT

Tx DMA Fault Detected Interrupt
Asserts when a fault is detected in Channel B Tx
DMA signal

0x0

22

W1C

CHTX_OVRUN

Tx Overrun Interrupt
Asserts when the Channel B Tx FIFO is overrun.

0x0

21

W1C

CHTX_UNRUN

Tx FIFO Underrun Interrupt
Asserts when the Channel B Tx FIFO is
underrun.

0x0

20

W1C

CHTX_THRES

Tx FIFO Below Threshold Interrupt
Asserts when the Channel B FIFO is lower than
the defined threshold.

0x1

19

W1C

CHRX_DMA_FAULT

Rx DMA Fault Detected Interrupt
Asserts when a fault is detected in a Channel B
Rx DMA signal.

0x0

18

W1C

CHRX_OVRUN

Rx FIFO Overrun Interrupt
Asserts when the Channel B Rx FIFO is overrun.

0x0

17

W1C

CHRX_UNRUN

Rx FIFO Underrun Interrupt
Asserts when the Channel B Rx FIFO is
underrun.

0x0

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Bits

Type

Name

Description

16

W1C

CHRX_THRES

Rx FIFO Below Threshold Interrupt
Asserts when the Channel B FIFO is lower than
the defined threshold.

Initial Value
0x0

15:8

-

-

Reserved

0x0

7:4

RO

CHRFF_AVCNT

Channel B Rx FIFO Available Space Count
Counts the available space for reads in channel
A Rx FIFO.
(unit: word)

0x0

3:0

RO

CHTFF_EPCNT

Channel B Tx FIFO Available Space Count
Counts the available space for writes in channel
A Tx FIFO.
(unit: word)

0x8

NOTE:
1. CHA_FF_STATUSn and CHB_FF_STATUSn registers have n=2 channels each, which together make up CHA0,
CHB0, CHA1, and CHB1. To configure a specific channel, select an offset in CHA_FF_STATUSn or
CHB_FF_STATUSn registers, where the first or second offset is indicated by n=0 or 1, respectively.
2. Where applicable,
Read
Write
0: Not asserted
1: Clear this bit.
1: Asserted
146. CHA_CFGn: (offset: 0x0020, 0x0120) (n=0, 1)
Bits
Type
Name
Description

Initial Value

31:30

-

-

Reserved

0x0

29:27

RW

CMP_MODE

Compression Mode
Sets the conversion method for the hardware
converter to compress raw data.
000: Disable HW converter, linear raw data (16bit)
010: Disable HW converter, linear raw data (8bit), A-law or u-law (8-bit)
011: Reserved
100: Enable HW converter, raw data(16-bit) 
U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit)
 raw data (16-bit) (PCM bus in raw, 16bit format)
110: Enable HW converter, raw data (16-bit) 
A-law mode (8-bit) (PCM bus in
compressed format)
111: Enable HW converter, A-law mode (8-bit)
 raw data (16-bit) (PCM bus in raw, 16bit format)

0x0

26:10

-

-

Reserved

0x0

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Bits

Type

Name

Description

9:0

RW

TS_START

Timeslot starting location
(unit: clock cycles)

147. CHnB_CFG: (offset: 0x0024, 0x0124) (n=0, 1)
Bits
Type
Name
Description

Initial Value
0x1

Initial Value

31:30

-

-

Reserved

0x0

29:27

RW

CMP_MODE

Compression Mode
Sets the conversion method for the hardware
converter to compress raw data.
000: Disable HW converter, linear raw-data (16bit)
010: Disable HW converter, linear raw-data (8bit), A-law or u-law (8-bit)
011: Reserved
100: Enable HW converter, raw data (16-bit) 
u-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit)
 raw-data(16-bit) (PCM bus in raw, 16bit format)
110: Enable HW converter, raw-data (16-bit) 
A-law mode (8-bit) (PCM bus in
compressed format)
111: Enable HW converter, A-law mode (8-bit)
 raw-data (16-bit) (PCM bus in raw, 16bit format)

0x0

26:10

-

-

Reserved

0x0

9:0

RW

TS_START

Timeslot starting location
(unit: clock cycles)

0x1

148. FSYNC_CFG: (offset: 0x0030)
Bits
Type
Name

Description

Initial Value

31

RW

CFG_FSYNC_EN

Enables configurable FSYNC.
0: Disable
1: Enable

0x0

30

RW

POS_CAP_DT

Positive Edge Capture Data
Sets the PCM controller to capture data on the
negative or positive edge of the PCM clock.
0: Negative edge
1: Positive edge
NOTE: This configuration should be 0 if
DTX_TRI=1.

0x0

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Bits

Type

Name

Description

29

RW

POS_DRV_DT

Positive Edge Drive Data
Sets the PCM controller to drive data on the
negative or positive edge of the PCM clock.
0: Negative edge
1: Positive edge

0x1

28

RW

POS_CAP_FSYNC

Positive Edge Capture FSYNC
Sets the PCM controller to capture FSYNC on
the positive or negative edge of the PCM clock.
0: Negative edge
1: Positive edge

0x0

27

RW

POS_DRV_FSYNC

Positive Edge Driver FSYNC
Sets the PCM controller to drive FSYNC on the
negative or positive edge of the PCM clock.
0: Negative edge of PCM clock
1: Positive edge of PCM clock

0x1

26:22

-

-

Reserved

0x0

21:10

-

-

Reserved

0x0

9:0

RW

FSYNC_INTV

Interval when FSYNC may be configured.
(unit: clock cycles)

0x0

149. CHA_CFG2: (offset: 0x0034, 0x0134) (n=0, 1)
Bits
Type
Name
Description

Initial Value

Initial Value

31:4

-

-

Reserved

0x0

3

RW

CH_RXFF_CLR

Channel A Rx FIFO Clear
0: Normal operation
1: Clear this bit

0x0

2

RW

CH_TXFF_CLR

Channel Tx FIFO Clear
0: Normal operation
1: Clear this bit

0x0

1

-

-

Reserved

0x0

0

RW

CH_LSB

Enable CH Tx in LSB order.

0x0

150. CHB_CFG2: (offset: 0x0034, 0x0138) (n=0, 1)
Bits
Type
Name
Description

Initial Value

31:4

-

-

Reserved

0x0

3

RW

CH_RXFF_CLR

Channel B Rx FIFO Clear
0: Normal operation
1: Clear this bit

0x0

2

RW

CH_TXFF_CLR

Channel B Tx FIFO Clear
0: Normal operation
1: Clear this bit

0x0

1

-

-

Reserved

0x0

0

RW

CH_LSB

Enables CH transmit in LSB order

0x0

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151. IP_INFO: (offset: 0x0040)
Bits
Type
Name

Description

31:16

-

-

Reserved

0x0

15:8

RO

MAX_CH

Maximum channel number.

0x4

7:0

RO

VER

Version of this PCM Controller

0x1

Initial Value

152. RSV_REG16: (offset: 0x0038)
Bits
Type
Name

Description

31:16

-

-

Reserved

0x0

15:0

RW

SPARE_REG

Spare register for future use.

0x0

153. DIVCOMP_CFG: (offset: 0x0050)
Bits
Type
Name

Description

Initial Value

Initial Value

31

RW

CLK_EN

Clock Enable
Enables setting of the PCM interface clock
based on DIVCOMP and DIVINT parameters.

0x0

30:8

-

-

Reserved

0x0

7:0

RW

DIVCOMP

A parameter in an equation which determines
FREQOUT. See DIVINT.

0x0

154. DIVINT_CFG: (offset: 0x0054)
Bits
Type
Name

Description

31:10

-

-

Reserved

0x0

9:0

RW

DIVINT

A parameter in an equation which determines
FREQOUT.
Formula:
FREQOUT = 1/(FREQIN*2*(DIVINT+DIVCOMP
/(2^8)))
FREQIN is always fixed to 40 MHz.

0x0

155. DIGDELAY_CFG: (offset: 0x0060)
Bits
Type
Name

Description

Initial Value

Initial Value

31

RW

TXD_CLR_GLT

TXD Clear Glitch Flag
Clears the glitch detected flag for TXD.
0: No effect.
1: Clear the flag.

0x0

30

RW

CHEN_CLR_GLT

Channel Enable (CHEN) Clear Glitch Flag
Clears the glitch detected flag for CHEN.
0: No effect .
1: Clear the flag.

0x0

29:27

-

-

Reserved

0x0

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Bits

Type

Name

Description

26

RO

TXD_GLT_ST

TXD Glitch Status
Indicates if a glitch is detected in a TXD signal. It
can be cleared by bit[31].
0: Not detected.
1: Detected

0x0

25:23

-

-

Reserved

0x0

22

RO

CHENN_GLT_ST

CHEN Negative Glitch Status
Indicates if a glitch is detected in a CHEN signal.
It can be cleared by bit[30] (negedge sample).
0: Not detected.
1: Detected

0x0

21:19

-

-

Reserved

0x0

18

RO

CHENP_GLT_ST

CHEN Positive Glitch Status
Indicates if a glitch is detected in a CHEN signal.
It can be cleared by bit[30] (posedge sample).
0: Not detected.
1: Detected

0x0

17

-

-

Reserved

0x0

16

RO

CHENPD_GLT_ST

CHEN Positive Delay Glitch Status
Indicates if a glitch is detected in a CHEN signal.
It can be cleared by bit[30] (posedge sample,
delay 1 cycle).
0: Not detected.
1: Detected

0x0

15

RW

TXD_DIGDLY_EN

TXD Digital Delay Enable
Enables digital delay path.
0: Disable
1: Enable

0x0

14:13

-

-

Reserved

0x0

12:8

RW

TXD_DLYVAL

Delay Count Value
The description is the same as the
CHEN_DLYVAL field in this register.

0x2

7

RW

CHEN_DIGDLY_EN

CHEN Digital Delay Enable
Enables the digital delay path.
0: Disable
1: Enable

0x0

6:5

-

-

Reserved

0x0

PGMT7620_V.1.0_040503

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Bits

Type

Name

Description

4:0

RW

CHEN_DLYVAL

Delay Count Value
The delay error =
CLK_PERIOD * (SYNC_DELAY + SYNC_DELTA +
(DLYCNT_CFG) + 1)
For example,
DLYCNT_CFG = 4,
(SYNC_DELAY is always fixed to 4)
Final Delay
= CLK_PERIOD * (2 + (-1/0/+1) + (4) + 1)
= CLK_PERIOD * (6/7/8)= CLK_PERIOD * (6 to 8)
= 25 ns to 33.3 ns
NOTE:
Period is 1/240 MHz = 4.1667 ns in MT7620.

156. CH0_FIFO: (offset: 0x0080)
Bits
Type
Name

Description

31:0

Channel 0 FIFO access point

RW

CH0_FIFO

157. CH1_FIFO: (offset: 0x0084)
Bits
Type
Name

Description

31:0

Channel 1 FIFO access point

RW

CH1_FIFO

158. CH2_FIFO: (offset: 0x0088)
Bits
Type
Name

Description

31:0

Channel 2 FIFO access point

RW

CH2_FIFO

159. CH3_FIFO: (offset: 0x008C)
Bits
Type
Name

Description

31:0

Channel 3 FIFO access point

RW

CH3_FIFO

PGMT7620_V.1.0_040503

Initial Value
0x2

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

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MT7620 PROGRAMMING GUIDE
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2.11.5 PCM Configuration
2.11.5.1 PCM Initialization Flow
1. Set PCM_CFG
2. Set CH0/1_CFG
3. Write PCM data to FIFO CH0/1_FIFO
4. Set GLB_CFG to enable the PCM and channel.
5. Set dividor clock
6. Enable clock
7. Monitor FF_STATUS to receive/transmit the other PCM data.
2.11.5.2 PCM Configuration Examples
Below are some examples of PCM configuration.
Case 1:
CFG_FSYNC Register: CFG_FSYNC_EN = 0 (PS: fsync is always driven at SLOT_CNT=1)
CH0_CFG Register: TS_START=1
CH1_CFG Register: TS_START=9
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b1, DRX_TRI=1’b0, SLOT_MODE=3’b0

Case 2:
CFG_FSYNC Register: CFG_FSYNC_EN = 1, START_LOC=0, interval=16
CH0_CFG Register: TS_START=1
CH1_CFG Register: TS_START=17
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b1, DRX_TRI=1’b0, SLOT_MODE=3’b0, RAW16-bits

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Case 3:
CFG_FSYNC Register: CFG_FSYNC_EN = 1, START_LOC=0x1A, interval=2
CH0_CFG Register: TS_START=1 (disable)
CH1_CFG Register: TS_START=0x1A
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b0 (LOW active), DRX_TRI=1’b0, SLOT_MODE=3’b0,
RAW16-bits

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MT7620 PROGRAMMING GUIDE
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2.12 Generic DMA Controller
2.12.1 Features
 Supports 16 DMA channels
 Supports 32 bit address.
 Maximum 65535 byte transfer
 Programmable DMA burst size (1, 2, 4, 8, 16 double word burst)
 Supports memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
transfers.
 Supports continuous mode.
 Supports division of target transfer count into 1 to 256 segments
 Support for combining different channels into a chain.
 Programmable hardware channel priority.
 Interrupts for each channel.
2.12.2 Block Diagram

Rbus Interface
(Master)

Rbus
Master

Rbus Interface
(Master)

Rbus
Master
DMA Engine

DMA
Interface

Arbiter

Interrupt
Interface

Interrupt
Controller

Ch0
Pbus
Slave

Mux

Pbus Interface
(Slave)

Ch"n"

Figure 2-12 Generic DMA Controller Block Diagram

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2.12.3 Peripheral Channel Connection
Channel number
Peripheral
0

Reserved

1

ND Controller

2

I2S Controller (TXDMA)

3

I2S Controller (RXDMA)

4

PCM Controller (RDMA, channel-0)

5

PCM Controller (RDMA, channel-1)

6

PCM Controller (TDMA, channel-0)

7

PCM Controller (TDMA, channel-1)

8

PCM Controller (RDMA, channel-2)

9

PCM Controller (RDMA, channel-3)

10

PCM Controller (TDMA, channel-2)

11

PCM Controller (TDMA, channel-3)

12

SPI Controller (RXDMA)

13

SPI Controller (TXDMA)

8 to 15

Reserved

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2.12.4 List of Registers
No. Offset

Register Name

Description

Page

160

0x0000, 0x0010, 0x0020,
0x0030, 0x0040, 0x0050,
0x0060, 0x0070, 0x0080,
0x0090, 0x00A0, 0x00B0,
0x00C0, 0x00D0, 0x00E0,
0x00F0

GDMA_SAn

GDMA Channel n Source Address

135

161

0x0004, 0x0014, 0x0024,
0x0034, 0x0044, 0x0054,
0x0064, 0x0074, 0x0084,
0x0094, 0x00A4, 0x00B4,
0x00C4, 0x00D4, 0x00E4,
0x00F4

GDMA_DAn

GDMA Channel n Destination Address

135

162

0x0008, 0x0018, 0x0028,
0x0038, 0x0048, 0x0058,
0x0068, 0x0078, 0x0088,
0x0098, 0x00A8, 0x00B8,
0x00C8, 0x00D8, 0x00E8,
0x00F8

GDMA_CT0n

GDMA Channel n Control 0

135

163

0x000C, 0x001C, 0x002C,
0x003C, 0x004C, 0x005C,
0x006C, 0x007C, 0x008C,
0x009C, 0x00AC, 0x00BC,
0x00CC, 0x00DC, 0x00EC,
0x00FC

GDMA_CT1n

GDMA Channel n Control 1

136

164

0x0200

GDMA_UNMASKINT

GDMA Unmasked Interrupt Status

137

165

0x0204

GDMA_DONEINT

GDMA Interrupt Status

138

166

0x0220

GDMA_GCT

GDMA Global Control

138

167

0x02A0

GDMA_REQSTS

GDMA Request Status

138

168

0x02A4

GDMA_ACKSTS

GDMA Acknowledge Status

138

169

0x02A8

GDMA_FINSTS

GDMA Finish Status

138

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2.12.5 Register Descriptions (base: 0x1000_2800)
160. GDMA_SAn: GDMA Channel n Source Address (offset: 0x0000, 0x0010, 0x0020, 0x0030, 0x0040, 0x0050,
0x0060, 0x0070, 0x0080, 0x0090, 0x00A0, 0x00B0, 0x00C0, 0x00D0, 0x00E0, 0x00F0) (n: 0 to 15)
Bits
Type
Name
Description
Initial Value
31:0

RW

CHANNEL SOURCE
ADDRESS

Channel Source Address
This register contains the source address
information.

0x0

161. GDMA_DAn: GDMA Channel n Destination Address (offset: 0x0004, 0x0014, 0x0024, 0x0034, 0x0044,
0x0054, 0x0064, 0x0074, 0x0084, 0x0094, 0x00A4, 0x00B4, 0x00C4, 0x00D4, 0x00E4, 0x00F4) (n: 0 to 15)
Bits
Type
Name
Description
Initial Value
31:0

RW

CHANNEL DESTINATION
ADDRESS

Channel Destination Address
This register contains the destination address
information.

0x0

162. GDMA_CT0n: GDMA Channel n Control Register 0 (offset: 0x0008, 0x0018, 0x0028, 0x0038, 0x0048,
0x0058, 0x0068, 0x0078, 0x0088, 0x0098, 0x00A8, 0x00B8, 0x00C8, 0x00D8, 0x00E8, 0x00F8) (n: 0 to 15)
Bits
Type
Name
Description
Initial Value
31:16

RW

Target Transfer Count
(Byte)

The number of bytes to be transferred.

0x0

15:8

RO

Current Segment

Indicates the current segment (0 to 255).

0x0

7

RW

Source Address Mode

Sets the source address mode
‘b0: Incremental mode
‘b1: Fix mode

0x0

6

RW

Destination Address
Mode

Sets the destination address mode.
‘b0: Incremental mode
‘b1: Fix mode

0x0

5:3

RW

Burst Size

Sets the number of double words in each burst
transaction.
‘b000: 1 DW
‘b001: 2 DWs
‘b010: 4 DWs
‘b011: 8 DWs
‘b100: 16 DWs
Others: Undefined

0x0

2

RW

Transmit Done Interrupt
Enable

Enables the transmit done interrupt. This
interrupt asserts after transfer of each segment
is done.
‘b1: Enable
‘b0: Disable

0x0

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Bits

Type

Name

Description

1

RW

Channel Enable

Channel Enable
‘b0: Disable
‘b1: Enable
If CONTINUOUS MODE ENABLE=0, this bit is deasserted by hardware after the number of bytes
transferred reaches the Target Transfer Count.

Initial Value
0x0

0

RW

Hardware/Software
Mode Select

Hardware/Software Mode Select
‘b1: Software Mode
‘b0: Hardware Mode
 In software mode, the data transfer starts
when the Channel Enable bit is set.
 In hardware mode, the data transfer starts
when DMA Request is asserted.

0x0

163. GDMA_CT1n: GDMA Channel n Control Register 1 (offset: 0x000C, 0x001C, 0x002C, 0x003C, 0x004C,
0x005C, 0x006C, 0x007C, 0x008C, 0x009C, 0x00AC, 0x00BC, 0x00CC, 0x00DC, 0x00EC, 0x00FC) (n: 0 to 15)
Bits
Type
Name
Description
Initial Value
31:26

-

-

Reserved

0x0
N

25:22

RW

Number of Segment (N)

The number of segments=2 , where N is the
value of this bit. Valid values for this bit range
from N=0 to 8.
N
The segment size=(Target Transfer Count/2 ).
N
If Target Transfer Count is not a multiple of 2 ,
N
the segment size = (Target Transfer Count/2 ) +
1.

0x0

21:16

RW

Source DMA Request

Selects the source DMA request.
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
…
n: DMA_REQn
32: The source of the transfer is memory
Others: Undefined

0x0

15

-

-

Reserved

0x0

14

RW

Continuous Mode Enable

Sets HW to keep the data channel enabled
when the number of bytes transferred reaches
the Target Transfer Count defined in the
GDMA_CT0n register.
0: HW will clear Channel Enable after the target
transfer count is reached.
1: HW will NOT clear Channel Enable after the
target transfer count is reached.

0x0

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Bits

Type

Name

Description

13:8

RW

Destination DMA Request

Selects the destination DMA request.
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
…
n: DMA_REQn
32: The destination of the transfer is memory.
Others: Undefined

0x0

7:3

RW

Next Channel to Unmask

Selects the next unmasked channel. When the
number of bytes transferred reaches the Target
Transfer Count, the hardware clears the
Channel Mask bit of the Next Channel to
Unmask.
0: Channel 0
1: Channel 1
2: Channel 2
...
n: Channel n
If the hardware does not need to clear any
Channel Mask bit, these bits must be set to
their own channel.

0x0

2

RW

Coherent Interrupt
Enable

Enables the coherent interrupt.
1’b1: GDMA issues a dummy READ to
Destination after the last WRITE to
Destination. This can ensure the last WRITE
arrived at the MEM and avoids a race
problem between interrupt and data to the
MEM.
NOTE: Do not set this to 1’b1 if the destination
is not MEM.

0x0

1

RW

Channel Unmask
Failure Interrupt Enable

Enables the channel unmasked interrupt.
‘b0: Disable
‘b1: Enable
When this bit is set, an interrupt is asserted
when the hardware tries to clear the Channel
Mask bit of Next Channel to Unmask but the
Channel Mask bit is already set to 0.

0x0

0

RW

Channel Mask

Channel Mask
‘b0: This channel is not masked
‘b1: This channel is masked
When this channel mask is set, the GDMA
transaction does not start until this bit is clear.

0x0

164. GDMA_UNMASKINT: GDMA Unmasked Interrupt Status Register (offset: 0x0200)
Bits
Type
Name
Description

PGMT7620_V.1.0_040503

Initial Value

Initial Value

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Bits

Type

Name

Description

31:0

W1C

Unmask Fail Interrupt

Indicates the status of unmasked fail interrupt.
This bit is set when the hardware tries to clear
the Channel Mask bit of Next Channel to
Unmask but the Channel Mask bit is 0 already.
Bit[n:0] is for channels n to 0 respectively.

165. GDMA_DONEINT: GDMA Interrupt Status Register (offset: 0x0204)
Bits
Type
Name
Description
31:0

W1C

Transmit Done Interrupt
Status

Indicates the status of the transmit-done
interrupt.
The interrupt asserts after each segment size is
transferred.
Bit[n:0] is for channels n to 0 respectively.

166. GDMA_GCT: GDMA Global Control Register (offset: 0x0220)
Bits
Type
Name
Description

Initial Value
0x0

Initial Value
0x0

Initial Value

31:5

-

-

Reserved

4:3

RO

Total channel number

2’b0: 8 channels
2’b1: 16 channels
2’b2: 32 channels
2’b3: Reserved

0x1

2:1

RO

IP version

GDMA Core Version

0x3

0

RW

Arbitration Selection

Selects the channel arbitration method.
1’b0: Channel 0 has the highest priority.
Channels 1 to n are round-robin.
1’b1: Channels 0 to n are round-robin.

0x0

167. GDMA_REQSTS: GDMA Request Status Register (offset: 0x02A0)
Bits
Type
Name
Description
31:0

RO

GDMA Request Signal
Status

Indicates the status of the GDMA request
signal.
Bit[n:0] are for GDMA_REQ n to 0 respectively.

168. GDMA_ACKSTS: GDMA Acknowledge Status Register (offset: 0x02A4)
Bits
Type
Name
Description
31:0

RO

GDMA Acknowledge
Signal Status

Indicates the status of the GDMA Acknowledge
Signal.
Bit[n:0] are for GDMA_ACK n to 0 respectively.

169. GDMA_FINSTS: GDMA Finish Status Register (offset: 0x02A8)
Bits
Type
Name
Description
31:0

RO

GDMA Finish Signal
Status

PGMT7620_V.1.0_040503

Indicates the status of the GDMA Finish Signal.
Bit[n:0] are for GDMA_FINISH n to 0
respectively.

-

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

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MT7620 PROGRAMMING GUIDE
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2.13 SPI Controller
2.13.1 Features
 Supports up to 2 SPI master operations
 Programmable clock polarity
 Programmable interface clock rate
 Programmable bit ordering
 Firmware-controlled SPI enable
 Programmable payload (address + data) length
 Supports 1/2/4 multi-IO SPI flash memory
 Supports command/user mode operation
 Supports SPI direct access
 Extends the addressable range from 24 bits to 32 bits for memory size larger than 128 Mb.
2.13.2 Block Diagram
clock
reset
from System
Controller

CPU Interface
from PalmBus
Controller

GDMA

TX_FIFO

CPU
Interface

RX_FIFO

Clock
Generator

SPICLK

SO/SIO1
SERDES

WP/SIO2

SPI Control
FSM

Figure 2-13 SPI Controller Block Diagram

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2.13.3 List of Registers
No.
Offset
Register Name

Description

Page

170

0x0000

SPISTAT0171

SPI Interface 0 Status

141

171

0x0004

Reserved

-

141

172

0x0008

Reserved

-

141

173

0x000C

Reserved

-

141

174

0x0010

SPICFG0

SPI Interface 0 Configuration

141

175

0x0014

SPICTL0

SPI Interface 0 Control

142

176

0x0020

SPIDATA0

SPI Interface 0 Data

143

177

0x0024

SPIADDR0

SPI Interface 0 Address

144

178

0x0028

SPIBS0

SPI Interface 0 Block Size

144

179

0x002C

SPIUSER0

SPI Interface 0 User Mode

144

180

0x0030

SPITXFIFO0

SPI Interface 0 TX_FIFO

146

181

0x0034

SPIRXFIFO0

SPI Interface 0 RX_FIFO

146

182

0x0038

SPIFIFOSTAT0

SPI Interface 0 FIFO_STATUS

146

183

0x003C

SPIMD0

SPI Interface 0 Mode

147

184

0x0040

SPISTAT1

SPI Interface 1 Status

147

185

0x0050

SPICFG1

SPI Interface 1 Configuration

147

186

0x0054

SPICTL1

SPI Interface 1 Control

148

187

0x0060

SPIDATA1

SPI Interface 1 Data

149

188

0x0080

SPIDMA

SPI Interface DMA

150

189

0x0084

SPIDMASTAT

SPI Interface DMA_FIFO_STATUS

150

190

0x00F0

SPIARB

SPI Interface Arbiter

150

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2.13.4 Register Descriptions (base: 0x1000_0B00)
170. SPISTAT0: SPI Interface 0 Status (offset: 0x0000)
Bits
Type
Name
Description
31:1

-

-

Reserved

0

RO

BUSY

Indicates SPI transfer in progress
0: The SPI interface is inactive.
1: An SPI transfer is in progress.
NOTE: This bit must be set to 0 before initiating
a transfer. Any attempt to start a data transfer
is ignored if this bit is a 1.

171. Reserved (offset: 0x0004)
Bits
Type
Name

Description

31:0

Reserved

-

-

172. Reserved: (offset: 0x0008)
Bits
Type
Name

Description

31:0

Reserved

-

-

173. Reserved: (offset: 0x000C)
Bits
Type
Name

Description

31:6

Reserved

-

-

174. SPICFG0: SPI Interface 0 Configuration (offset: 0x0010)
Bits
Type
Name
Description

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Initial Value

31:13

-

-

Reserved

12

RW

ADDRMODE

SPI Address Mode
0: 3-Byte address mode
(for SPI flash <= 128 Mb)
1: 4-Byte address mode
(for SPI flash >= 256 Mb)

0x0

11

RW

RXENVDIS

Rx Pre-Envelope Disable
Disables setting a pre-data input before the first
data is received.
0: Enable clock PRE_ENVELOP (slave mode)
1: Disable clock PRE_ENVELOP (SPI flash mode)

0x0

10

RW

RXCAP

Rx Capture Delay Mode
0: Rx data capture is not delayed.
1: Rx data capture is delayed for half an SPICLK
cycle

0x0

PGMT7620_V.1.0_040503

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Bits

Type

Name

Description

9

RW

SPIENMODE

SPI Enable Mode
0: SPI Enable is controlled by SW register
settings (SPICTL0)
1: SPI Enable is controlled by HW (SPI Flash
CMD)

0x0

8

RW

MSBFIRST

Bit Transfer Order
0: LSB bits of data sent/received first.
1: MSB bits of data sent/received first.
NOTE: This bit applies to both the command
and data.

0x1

7

-

-

Reserved

6

RW

SPICLKPOL

SPI Clock Default Polarity
Sets the default state of the SPICLK
0: Logic 0
1: Logic 1
NOTE: This bit is ignored if the SPI interface
block is a slave (SPISLAVE bit is set).

0x0

5

RW

RXCKEDGE

Rx Clock Capture Edge
0: Data is captured on the rising edge of the
SPICLK signal.
1: Data is captured on the falling edge of the
SPICLK signal.

0x0

4

RW

TXCKEDGE

Tx Clock Transmit Edge
0: Data is transmitted on the rising edge of the
SPICLK signal.
1: Data is transmitted on the falling edge of the
SPICLK signal.

0x0

3

RW

HIZSPI

Tri-state all SPI pins
0: SPICLK and SPIENA pin are driven.
1: SPICLK and SPIENA pin are tri-stated.
NOTE: This bit overrides all normal
functionality.

0x0

2:0

RW

SPICLK

SPI Clock Divide Control
0: SPICLK rate is system clock rate / 2
1: SPICLK rate is system clock rate / 4
2: SPICLK rate is system clock rate / 8
3: SPICLK rate is system clock rate / 16
4: SPICLK rate is system clock rate / 32
5: SPICLK rate is system clock rate / 64
6: SPICLK rate is system clock rate / 128
7: SPICLK is disabled.
NOTE: These rates may change in the future.

0x4

175. SPICTL0: SPI Interface 0 Control (offset: 0x0014)
Bits
Type
Name
Description
31:5

-

-

PGMT7620_V.1.0_040503

Reserved

Initial Value

-

Initial Value
-

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Bits

Type

Name

Description

4

RW

START

Start SPI Flash Transaction Mode
0: No effect
1: Starts SPI internal controller to start an SPI
instruction transaction.
NOTE: The BUSY bit in the SPISTAT register is
set when this bit is set and is cleared when the
data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.

0x0

3

RW

HIZSDO

Tri-state Data Out
0: The SPIDO pin remains driven after the cycle
is complete.
1: The SPIDO pin is tri-stated after the cycle is
complete.
NOTE: This bit applies to write transfers only;
for read transfers the SPIDO pin is tri-stated
during the transfer.

0x0

2

WO

STARTWR

Start SPI Write Transfer
0: No effect.
1: The contents of the SPIDATA register are
transferred to the SPI slave device.
NOTE: The BUSY bit in the SPISTAT register is
set when this bit is set and is cleared when the
data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.

0x0

1

WO

STARTRD

Start SPI Read Transfer
0: No effect.
1: Start a read from the SPI slave. The read data
is placed in the SPIDATA register.
NOTE: The BUSY bit in the SPISTAT register is
set when this bit is set and is cleared when the
data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.

0x0

0

RW

SPIENA

SPI Enable
0: The SPIENA pin is negated.
1: The SPIENA pin is asserted.

0x0

176. SPIDATA0: SPI Interface 0 Data (offset: 0x0020)
Bits
Type
Name
Description
31:8

-

-

PGMT7620_V.1.0_040503

Reserved

Initial Value

Initial Value
-

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Bits

Type

Name

Description

7:0

RW

SPIDATA

SPI Data Transfer
This register is used for command/data
transfers on the SPI interface. The use of this
register is given below:
Write
The bits to be transferred are written here,
including both command and data bits. If values
are transmitted MSB (most significant bit) first,
the command is placed in the upper bits and
the data in the lower bits. Bit 0 of the data is
written to SPIDATA [0]; bit 0 of the command
follows the MSB of the data. If data is
transmitted LSB (least significant bit) first, the
command is placed in the lower bits and the
data is placed in the upper bits.
Read
The command bits are written here. Bit 0 of the
command is written to SPIDATA[0]. When the
transfer is complete, the data transferred from
the slave may be read from the lower bits of
this register.
When using SPI Flash transaction, this
SPIDATA[7:0] is used for SPI_INSTR[7:0].

177. SPIADDR0: SPI Interface 0 Address (offset: 0x0024)
Bits
Type
Name
Description
31:0

RW

SPI_ADDR

SPI Flash Address
When 3-Byte SPI address is configured,
SPI_ADDR[31:8] is used.
When 4-Byte SPI address is configured,
SPI_ADDR[31:0] is used.

178. SPIBS0: SPI Interface 0 Block Size (offset: 0x0028)
Bits
Type
Name
Description
31:0

RW

SPI_BLOCKSIZE

SPI Block Size
Defines how many data bytes are transferred
during an SPI instruction execution.

179. SPIUSER0: SPI Interface 0 User Mode (offset: 0x002C)
Bits
Type
Name
Description

Initial Value
0x0

Initial Value
0x0

Initial Value
0x0

Initial Value

31:22

-

-

Reserved

0x0

21

RW

USERMODE

User Manual SPI Mode Enable
0: Disable user mode
1: Enable user mode. Allows SW to set the
phase and type of SPI commands that are
not pre-defined.

0x0

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Bits

Type

Name

Description

20

RW

INSTR_PHASE

Instruction Phase
0: No instruction bytes
1: One byte instruction phase (SPIDATA0)

0x0

19:17

RW

ADDR_PHASE

Address Phase
000: No address byte
001: One byte address phase
(SPIADDR0[31:24])
010: Two byte address phase
(SPIADDR0[31:16])
011: Three byte address phase
(SPIADDR0[31:8])
100: Four byte address phase (SPIADDR0[31:0])
Others: Reserved

0x0

16

RW

MODE_PHASE

Mode Phase Byte Count
0: No mode bytes
1: One mode byte (SPIMD0[31:24])

0x0

15:14

RW

DUMMY_PHASE

Dummy Phase Byte Count
00: No dummy phase
01: One dummy byte
10: Two dummy bytes
11: Three dummy bytes

0x0

13:12

RW

DATA_PHASE

Data Phase Type
00: No data phase
01: Read data phase
10: Write data phase
11: Reserved
Data writes to Tx/Rx FIFO when user mode is
enabled.

0x0

11:9

RW

ADDR_TYPE

Address Transfer Type
001: Single Address Mode
010: Dual Address Mode
100: Quad Address Mode
Others: Reserved

0x0

8:6

RW

MODE_TYPE

Mode Transfer Type
001: Single Address Mode
010: Dual Address Mode
100: Quad Address Mode
Others: Reserved

0x0

5:3

RW

DUMMY_TYPE

Dummy Transfer Type
001: Single Address Mode
010: Dual Address Mode
100: Quad Address Mode
Others: Reserved

0x0

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Bits

Type

Name

Description

2:0

RW

DATA_TYPE

Data Transfer Type
001: Single Address Mode
010: Dual Address Mode
100: Quad Address Mode
Others: Reserved

180. SPITXFIFO0: SPI Interface 0 TX_FIFO (offset: 0x0030)
Bits
Type
Name
Description

Initial Value
0x0

Initial Value

31:8

RW

TX_FIFO

This register is used to write
TX_DMA_FIFO[31:8].

0x0

7:0

RW

TX_FIFO

This register is used to write TX
FIFO[7:0]/TX_DMA_FIFO[7:0].

0x0

181. SPIRXFIFO0: SPI Interface 0 RX_FIFO (offset: 0x0034)
Bits
Type
Name
Description

Initial Value

31:8

RC

RX_FIFO

This register is used to read RX DMA FIFO[31:8].

0x0

7:0

RC

RX_FIFO

This register is used to read RX
FIFO[7:0]/RX_DMA_FIFO[7:0].

0x0

182. SPIFIFOSTAT0: SPI Interface 0 FIFO_STATUS (offset: 0x0038)
Bits
Type
Name
Description

Initial Value

31:20

-

-

Reserved

0x0

19

RO

TX_EMPTY

Tx FIFO Empty

0x1

18

RO

RX_EMPTY

Rx FIFO Empty
Should not read SPIRXFIFO0 data when this flag
is true.

0x1

17

RO

TX_FULL

Tx FIFO Full
Should not write SPITXFIFO0 data when this flag
is true.

0x0

16

RO

RX_FULL

Rx FIFO Full

0x0

15:8

RO

TX_FIFO_CNT

Tx FIFO Count
Transmit FIFO Depth = 16,
When TX_FIFO_CNT=0, TX_EMPTY=1.
When TX_FIFO_CNT=16, TX_FULL=1.

0x0

7:0

RO

RX_FIFO_CNT

Rx FIFO Count
Receive FIFO Depth = 16,
When RX_FIFO_CNT=0, RX_EMPTY=1.
When RX_FIFO_CNT=16, RX_FULL=1.

0x0

NOTE: Where applicable,
0: False
1: True

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183. SPIMD0: SPI Interface 0 Mode (offset: 0x003C)
Bits
Type
Name
Description

Initial Value

31:24

RW

SPI_MODE

SPI Flash Mode
Selects the SPI flash mode. Available modes
depend on the SPI flash vendor. For more
information on available modes, please check
the datasheet provided by the SPI vendor.

0x0

23:0

RW

SPI_DUMMY

SPI Dummy
Contains data used for dummy writes to the SPI
flash.

0x0

184. SPISTAT1: SPI Interface 1 Status (offset: 0x0040)
Bits
Type
Name
Description
31:2

-

-

Reserved

0

RO

BUSY

SPI Transfer In Progress
0: The SPI interface is inactive.
1: An SPI transfer is in progress.
NOTE: This bit must be 0 before initiating a
transfer. Any attempt to start a data transfer
will be ignored if this bit is 1.

185. SPICFG1: SPI Interface 1 Configuration (offset: 0x0050)
Bits
Type
Name
Description

Initial Value
0x0

Initial Value

31:12

-

-

Reserved

11

RW

RXENVDIS

Rx Pre-Envelope Disable
Disables setting a pre-data input before the first
data is received.
0: Enable clock PRE_ENVELOP when
(CLOCK_POL ^ RX_CLKEDGE = 0)
1: Disable clock PRE_ENVELOP (SPI flash mode)

0x0

10

RW

RXCAP

Rx Capture Delay Mode
0: Rx data captured is not delayed.
1: Rx data captured is delayed for half a SPICLK
cycle.

0x0

9

-

-

Reserved

8

RW

MSBFIRST

Bit Transfer Order
0: LSB bits of data sent/received first.
1: MSB bits of data sent/received first.
NOTE: This bit applies to both the command
and data.

7

-

-

Reserved

PGMT7620_V.1.0_040503

-

0x1

-

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Bits

Type

Name

Description

6

RW

SPICLKPOL

SPI Clock Default Polarity
Sets the default state of the SPICLK.
0: Logic 0
1: Logic 1
NOTE: This bit is ignored if the SPI interface
block is a slave (SPISLAVE bit is set).

0x0

5

RW

RXCKEDGE

SPI Clock Default State
0: Data is captured on the rising edge of the
SPICLK signal.
1: Data is captured on the falling edge of the
SPICLK signal.

0x0

4

RW

TXCKEDGE

SPI Clock Default State
0: Data is transmitted on the rising edge of the
SPICLK signal.
1: Data is transmitted on the falling edge of the
SPICLK signal.

0x0

3

RW

HIZSPI

Tri-states all SPI pins
0: SPICLK and SPIENA pin are driven.
1: SPICLK and SPIENA pin are tri-stated.
NOTE: This bit overrides all normal
functionality.

0x0

2:0

RW

SPICLK

SPI Clock Divide Control
Sets the SPI clock divisor.
0: SPICLK rate = system clock rate/ 2
1: SPICLK rate = system clock rate / 4
2: SPICLK rate = system clock rate / 8
3: SPICLK rate = system clock rate / 16
4: SPICLK rate = system clock rate / 32
5: SPICLK rate = system clock rate / 64
6: SPICLK rate = system clock rate / 128
7: SPICLK is disabled
NOTE: These rates may change in the future.

0x4

186. SPICTL1: SPI Interface 1 Control (offset: 0x0054)
Bits
Type
Name
Description
31:4

-

-

Reserved

3

RW

HIZSDO

Tri-state Data Out
0: The SPIDO pin remains driven after the cycle
is complete.
1: The SPIDO pin is tri-stated after the cycle is
complete.
NOTE: This bit applies to write transfers only;
for read transfers the SPIDO pin is tri-stated
during the transfer.

PGMT7620_V.1.0_040503

Initial Value

Initial Value
0x0

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Bits

Type

Name

Description

2

WO

STARTWR

Start SPI Write Transfer
0: No effect.
1: The contents of the SPIDATA register are
transferred to the SPI slave device.
NOTE: The BUSY bit in the SPISTAT register is
set when this bit is set and is cleared when the
data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.

0x0

1

WO

STARTRD

Start Read
0: No effect.
1: Start a read from the SPI slave. The read data
is placed in the SPIDATA register.
NOTE: The BUSY bit in the SPISTAT register is
set when a this bit is set and is cleared when
the data transfer is complete. This bit is only
meaningful if the SPI interface block is
configured as a master.

0x0

0

RW

SPIENA

SPI Enable
0: The SPIENA pin is set low.
1: The SPIENA pin is set high.

0x0

187. SPIDATA1: SPI Interface 1 Data (offset: 0x0060)
Bits
Type
Name
Description
31:8

-

-

Reserved

7:0

RW

SPIDATA

This register is used for command/data
transfers on the SPI interface. The use of this
register is given below:
Write
The bits to be transferred are written here,
including both command and data bits. If
values are transmitted MSB (most
significant bit) first, the command is placed in
the upper bits and the data in the lower bits.
Bit 0 of the data is written to SPIDATA
[0]; bit 0 of the command follows the MSB of
the data. If data is transmitted LSB (least
significant bit) first, the command is placed
in the lower bits and the data is placed in the
upper bits.
Read
The command bits are written here. Bit 0 of the
command is written to SPIDATA[0]. When the
transfer is complete, the data transferred from
the slave may be read from the lower bits of
this register.

PGMT7620_V.1.0_040503

Initial Value

Initial Value
0x0

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188. SPIDMA: SPI Interface DMA (offset: 0x0080)
Bits
Type
Name
Description

Initial Value

31:11

-

-

Reserved

0x0

10:9

RW

TxBurstSize

The number of transfers in a Tx burst
transaction.
‘b00: 1 transfer
‘b01: 2 transfers
‘b10: 4 transfers
Others: Undefined

0x1

8

RW

TXDMA

Tx DMA Enable
0: Disable Tx GDMA
1: Write Tx FIFO from GDMA

0x0

7:3

-

-

Reserved

0x0

2:1

RW

RxBurstSize

The number of transfers in a Rx burst
transaction.
‘b00: 1 transfer
‘b01: 2 transfers
‘b10: 4 transfers
Others: Undefined

0x1

0

RW

RXDMA

Rx DMA Enable
0: Disable Rx GDMA
1: Read Rx FIFO from GDMA

0x0

189. SPIDMASTAT: SPI Interface DMA FIFO Status (offset: 0x0084)
Bits
Type
Name
Description

Initial Value

31:20

-

-

Reserved

0x0

19

RO

TX_DMA_EMPTY

Indicates the Tx DMA FIFO is empty.

0x1

18

RO

RX_DMA_EMPTY

Indicates the Rx DMA FIFO is empty.

0x1

17

RO

TX_DMA_FULL

Indicates the Tx DMA FIFO is full.

0x0

16

RO

RX_DMA_FULL

Indicates the Rx DMA FIFO is full.

0x0

15:8

RO

TX_DMA_CNT

Shows the value of the Tx DMA FIFO counter.

0x0

7:0
RO
RX_DMA_CNT
NOTE: Where applicable,
0: False
1: True

Shows the value of the Rx DMA FIFO counter.

0x0

190. SPIARB: SPI Interface Arbiter (offset: 0x00F0)
Bits
Type
Name
Description
31

RW

ARB_EN

Arbiter Enable
0: Only one SPI interface will work depending
on CSCTL settings.
1: SPI Interface 0 and 1 work concurrently.

30:19

-

-

Reserved

PGMT7620_V.1.0_040503

Initial Value
0x0

-

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Bits

Type

Name

Description

18:16

RW

CSCTL

Chip Select Control
000: SPI control for chip select 0
001: SPI control for chip select 1
010-111: Reserved

15:2

-

-

Reserved

1

RW

SPI1_POR

SPI1 Pin Polarity Read
Indicates that the SPI device on interface 1 is
active depending on whether the chip enable
pin is high or low.
0: Active when the chip enable pin is low.
1: Active when the chip enable pin is high.

0x0

0

RW

SPI0_POR

SPI0 Polarity Read
Indicates that the SPI device on interface 0 is
active depending on whether the chip enable
pin is high or low.
0: Active when the chip enable pin is low.
1: Active when the chip enable pin is high
NOTE: This register must be configured when SPI interface 1 is activated.

0x0

PGMT7620_V.1.0_040503

Initial Value
0x0

-

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2.14 I2S Controller
2.14.1 Features
 I2S transmitter/receiver, which can be configured as master or slave.
 Supports 16-bit data, sampling rates of 8 kHz, 16 kHz, 22.05 kHz, 44.1 kHz, and 48 kHz
 Support stereo audio data transfer.
 32-byte FIFO are available for data transmission.
 Supports GDMA access
 Supports 12 Mhz bit clock from external source (when in slave mode)
2.14.2 Block Diagram
2
The I S transmitter block diagram is shown as below.

CPU

SCLK

Parallelto-serial
converter

FIFO
PBUS

PBUS
Control

SDRAM

RBUS

WS

CSR

Async interface

SD

RBUS

I2S Design

RBUS

RBUS

GDMA

2

Figure 2-14 I S Transmitter Block Diagram

2

The I S interface consists of two separate cores, a transmitter and a receiver. Both can operate in either master
or slave mode. The transmitter is only shown here in master or slave mode.

PGMT7620_V.1.0_040503

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2

2

2.14.3 I S Signal Timing For I S Data Format

Figure 2-15 I2S Transmit/Receive

Serial data is transmitted in 2’s complement with the MSB first. The transmitter always sends the MSB of the
next word one clock period after the WS changes. Serial data sent by the transmitter may be synchronized
with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal. However, the
serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are
some restrictions when transmitting data that is synchronized with the leading edge.
The word select line indicates the channel being transmitted:
 WS = 0; channel 1 (left)
 WS = 1; channel 2 (right)
WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be symmetrical. In
the slave, this signal is latched on the leading edge of the clock signal. The WS line changes one clock period
before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data
that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear
the input for the next Word.

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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.14.4 List of Registers
No.
Offset
Register Name

Description
2

Page

191

0x0000

I2S_CFG

I S Configuration

155

192

0x0004

INT_STATUS

Interrupt Status

156

193

0x0008

INT_EN

Interrupt Enable

156

194

0x000C

FF_STATUS

FIFO Status

157

195

0x0010

TX_FIFO_WREG

Transmit FIFO Write to Register

157

196

0x0014

RX_FIFO_RREG

Receive FIFO Read Register

157

2

197

0x0018

I2S_CFG1

I S Configuration 1

157

198

0x0020

DIVCOMP_CFG

Integer Part of the Dividor Register 1

158

199

0x0024

DIVINT_CFG

Integer Part of the Dividor Register 2

158

PGMT7620_V.1.0_040503

Page 154 of 523

MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip

2.14.5 Register Descriptions (base: 0x1000_0A00)
2

191. I2S_CFG: I S Tx/Rx Configuration Register (offset: 0x0000)
Bits
Type
Name
Description
2

Initial Value

31

RW

I2S_EN

I S Enable
2
2
Enables I S. When disabled, all I S control
registers are cleared to their initial values.
0: Disable
1: Enable

0x0

30

RW

DMA_EN

DMA Enable
Enables DMA access.
0: Disable
1: Enable

0x0

29

-

-

Reserved

0x0

28

RW

BYTE_SWAP

Swaps the order of data bytes in each 16-bit
channel.
0: No data swap
1: Data byte swap

0x0

27:25

-

-

Reserved

0x0

24

RW

TX_EN

Transmitter on/off control
0: Disable
1: Enable

0x0

23:21

-

-

Reserved

0x0

20

RW

RX_EN

Receiver on/off control
0: Disable
1: Enable

0x0

19:17

-

-

Reserved

0x0

16

RW

SLAVE_MODE

Sets master or slave mode.
0: Master: using internal clock
1: Slave: using external clock

0x1

15

-

-

Reserved

0x0

14:12

RW

RX_FF_THRES

Rx FIFO Threshold
When the threshold is reached, the host/DMA
is notified to fill FIFO. 2

---

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Page Count                      : 523
Language                        : zh-TW
Tagged PDF                      : Yes
Title                           : MT7620 Programming Guide
Author                          : huiwen
Creator                         : Microsoft® Office Word 2007
Create Date                     : 2012:08:15 13:24:42+08:00
Modify Date                     : 2012:08:15 13:24:42+08:00
Producer                        : Microsoft® Office Word 2007

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