N00039 73 C 0431_AN_UYK 20_Technical_Manual_Volume_1_Jan1974 0431 AN UYK 20 Technical Manual Volume 1 Jan1974
N00039-73-C-0431_AN_UYK-20_Technical_Manual_Volume_1_Jan1974 N00039-73-C-0431_AN_UYK-20_Technical_Manual_Volume_1_Jan1974
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NAVELEX XXXX-XXX-XXXI
TECHNICAL MANUAL
OPERATION
AND
MAINTENANCE
WITH
PARTS LIST
DATA PROCESSING SET
AN/UYK-20(V)1
Each transmittal of this document outside of the Department of Defense must have
approval of the issuing service.
Published by direction of Commander Naval Electronics Systems Command
RECORD OF CHANGES
CHANGE
NO.
DATE
TITLE OR BRIEF
DESCRI PTI ON
ENTERED BY
NAVELEX XXXX-XXX-XXXl
TECHNICAL MANUAL
OPERATION
AND
MAINTENANCE
WITH
PARTS LIST
Data Processing Set
AN!UYK-20( V) 1
Sperry Univac, A Division of Sperry Rand Corporation
N00039-73-C-0432
Each transmittal of ~his document outside of the Department
of Defense must have approval of the issuing service.
Published by direction of Commander Naval Electronics Systems Command
25 ,January 1974
NAVELEX XXXX-XXX-XXXI
Reproduction for non-military use of the information or iUustration contained in
this publication is not permitted. The policy for military use reproduction is
established for the Army in AR308-5, for the Navy and Marine Corps in OPNAVINST
55l0.lB and for the Air Force in Air Force Regulation 205-1.
LIST OF EFFECTIVE PAGES
Insert latest changed pages; dispose of superseded pages in accordance with applicabie regulations.
On a changed page, the portion of the text affected by the latest change is
indicated by a vertical line, or other change symbol, in the outer margin of the
page. Changes to illustrations are indicated by miniature pOinting hands. Changes
to wiring diagrams are indicated by shaded areas.
~:
Total number of pages in this manual is 417 consisting of the following.
PAGE NO.
"#
Title
A • •
1-0 - 1-16
2-1 - 2-32
3-1 - 3-153
3-154 Blank
4-1 - 4-8 •
5-1 - 5-6 •
6-1 - 6-8 •
7-1 - 7-55
7-56 Blank
8-1 - 8-16
A-I - A-20
B-1 - B-39
B-40 Blank
C-l - C-50
D-1 - D-2 •
E-l - E-2 •
G-l - G-5 •
G-6 Blank '.
"#
A
•
•
•
•
•
..
CHANGE NO.
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Zero in this column indicates an original page.
VALIDATION PERFORMANCE
NAVSHIPS:
Title of Publication:
Technical Manual for nata Processing Set AN/UYK-20(V)l
Contractor:
Sperry Univac
Defense Systems
Univac Park
St. Paul, Minn.
Sub-Contractor (if performing
validation) :
Contract No(s) and Purchase Orders, if applicable
Contract No.
Chapter
Section
Name & Authority of Validating
Officer:
Paragraph
Date
Validation
Completed
Check here i f
not validated
Signature of Validating Officer:
Sheet I of I
VERIFICATION PERFORMANCE
Title of Publication:
NAVSHIPS:
Technical Manual for Data Processing Set AN/UYK-20(V)l
Government Activity:
Date Verification Completed:
Date Correction Completed:
Date Reverification Completed:
Chapter
Section
Para
Date Verif
Completed
Name & Authority of Verifying
Officer:
Date Corrections made
Date
Reverified
Check here if
not verified
Signature of Verifying Officer:
Sheet 1 of 1
TABLE OF
CONTru~TS
Chapter
Page Chapter
1 GENERAL INFORMATION . . . . . .
1-1.
Introduction . . . • . .
1-13. Functional Description .
1-31. Physical Description . .
1-36. Reference Data . . . . .
1-38. Equipment Accessories,
and Publications
1-40. Equipment Required but
not Supplied .
1-1 6 CORRECTIVE MAINTENANCE . . • . •
6-1.
Introduction . . . • . •
1-1
1-2
6-2.
Removal and Replacement
1-5
Procedures
1-10
7 PARTS LIST . . . . . .
1-10
7-1.
Introduction
7-3.
List of Major Units.
1-10
7-5.
Parts List . . . . . . .
7-7.
List of Common Item Descriptions • . . . . •
2-1
List of Attaching Hard2-1
7-9.
2 OPERATION . . • . . . .
2-1.
Introduction •.
2-3.
Control Panel Switches
and Indicators . . . .
2-5.
Maintenance Panel
Switches and Indicators . . . . . . .
Operating Procedures
2-7.
2-26. Microinstructions
2-28. Macroinstructions
3 FUNCTIONAL DESCRIPTION . . . .
3-1.
Introduction . .
3-3.
Primary Block Diagram
Description . . . . .
3-18. Functional Block Diagram
Description • . . . .
3-191. Operational Description.
3-203. Logic Device Descript ions . . . . .
.
4 PREVENTIVE MAINTENANCE
4-1.
Introduction . .
4-3.
Preventive Maintenance
Procedures .
5 TROUBLESHOOTING. .
5-1.
Introduction.
5-8.
Troubleshooting Procedures . . . . .
Page
ware
2-1
7-11.
7-13.
. . . . . . .
List of Manufacturers •.
Parts Location Illustrations
. . . .
2-1
2-1 8 INSTALLATION. • . . . . . .
2-17
8-1.
Introduction • . . .
2-17
8-3.
Installation Instructions
8-10. Installation Checkout . .
3-1
APPENDIX A - MICROINSTRUCTION
3-1
REPERTOIRE . . . . . . . . •.
3-1
APPENDIX B - REPERTOIRE OF MACRO
INSTRUCTIONS . . • . . •
3-6
3-133
APPENDIX C - MICROPROGRAM
LISTING . . . . . . . .
3-153
6-1
6-1
6-1
7-1
7-1
7-1
7-1
7-1
7-1
7-2
7-2
8-1
8-1
8-1
8-7
A-I
B-1
C-l
4-1
4-1
APPENDIX 0 - MAIN MEMORY ADDRESS
ALLOCATION . • . . . . . . . .
0-1
4-2
APPENDIX E - DEVICE DESCRIPTIONS
E-l
5-1
5-1
GLOSSARY OF TERMS AND ABBREVIATIONS . . . . . .
G-l
5-4
9 EQUIPMENT DIAGRAMS . .
9-1.
Introduction . . • .
9-3.
Logie Symbology . . . . •
9-1
9-1
9-1
i
LIST OF iLLUSTRATIONS
Number
1-1.
1-2.
1-3.
1-4.
1-5.
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20,
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
3-28.
3-29.
3-30.
3-31.
3-32.
3-33.
3-34.
3-35.
3-36.
3-37.
ii
Title
Page
.
Data Processing Set, AN/UYK-20(V)1 •
.'
Simplified Block Diagram • •
Data Processing Set, Open •• • • • • • • • . • .
Typical Single-Width Circuit Card • • • •
Typical Triple-Width Circuit Card
•••••
Control Panel • • • .
. • • • •
Maintenance Panel • • . • . . • • •
• • . •
• • • •
Basic Instruction Word Format
• • • •
Instruction Word Format for Format RI Type 1 ,
• •
Address Generation Example for Format RI Type 1 Instructions •
Indirect Address Format
Primary Block Diagram
MPC Functional Block Diagram
Overlapped Bus Operation • •
Microinstruction Format
Condition Register Format . • • • •
Master Clock Block Diagram • • • •
Master Clock Timing
• • . • • • . •
Processor/Emulator Functional Block Diagram
Emulator Control Word (ECW) Format .
Status Register ~l Format •• • .
Status R~gister #2 Format . • • •
• • • • •
Interrupt Addressing • • • • • ••
••• • • • •
Class I and II Interrupt Entrance Address Index
Class III Interrupt Entrance Address Index •
Multiply Timing • • • • • • • • • • • . • •
Memory Interface Functional Block Diagram
Page Addressing Function • •
Indirect Address Format
Main Memory Block Diagram
Memory Bank Block Diagram • • • •
Timing and Control Block Diagram •
Split Cycle Timing • . . . • • •
Full Cycle Timing
. . • • • .
Memory Timing Circuits.
Memory Array Board • • • •
Memory Core Drive Circuits
Internal Timing - Read/Restore • • •
Internal Timing - Read/Modify/Write
.
IOC Functional Block Diagram • . . • • • • • • • .
I/O Control Memory Format • • • • •
Serial Control Word Format . . • • • .
Parallpl Output Communication Interface
Parallel Input Communication Interface •
Parallel Slow (-15V) Interface • •
. . • • • • •
Parallel Fast (-3V) Interface • • • . • • • • • • , • • , • • • •
Parallel ANEW (+3.5V) Interface . • • • • • • • • . • , .
Parallel I/O External Function or Output Data Timing (-15 Volt
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . .. .
1-0
1-3
1-6
1-8
1-9
2-2
2-5
2-21
2-21
2-22
2-23
3-3
3-7
3-9
-3-12
3-17
3-19
3-20
3-23
3-25
3-27
3-29
3-32
3-34
3-34
3-42
3-44
3-46
3-47
3-50
3-55
3-57
3-59
3-61
3-63
3-67
3-69
3-73
3-77
3-79
3-83
3-84A
3-90
3-91
3-92
3-93
3-94
3-96
LIST OF ILLllSTRATIONS (CONT)
Number
Title
Page
3-39.
Parallel I/O External Interrupt or Input Data Timing {-15 Volt
I~terface . • . . . • . . . . . . . . . . . . . . • . . . .
Parallel I/O External Function or Output Data Timing {-3 Volt
3-40.
Parallel I/O External Interrupt or Input Data Timing {-3 Volt
3-41.
Parallel I/O External Function or Output Data Timing (+3.5 Volt
3-42.
Parallel I/O External Interrupt or Input Data Timing (+3.5 Volt
Interface • . • . . . . . . • • • • . . . •
Parallel Dual Channel Jumper Cable Diagram . . . . • •
Parallel I/O Intercomputer Interface
MIL-STD-188 Serial Channel Interface • • • •
MIL-STD-188 Interrupt Word Format . . . . • .
EIA RS-232 Standard Serial Channel Interface
RS-232 Interrupt Word Format
NTDS 32-Bit Serial I/O Channel
NTDS Serial Channel Interface . .
3-Bit Control Frames • • . . •
NTDS Serial I/O Word Format • .
Bi-Polar Pulse Characteristics
Power Supply Overall Function3l Block Diagram •
Switching Regulator Simplified Block Diagram
Switching Regulator Oscillator Waveform . . .
Pulse Width Modulator Voltage Waveform
•.
Switching Regulator Base Drive Current Waveform • • . . . • • .
Converter Oscillator-Driver and Chopper Circuit Simplified Block
3-38.
In terface . . . . . . . . . . . . . . . . . . . . . . . . . .
In terface . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface . . . . . . . . . . . . . . . . . . . . . . . . . .
3-43.
3-44.
3-45.
3-46.
3-47.
3-48.
3-49.
3-50.
3-51.
3-52.
3-53.
3-54.
3-55.
3-56.
3-57.
3-58.
3-59.
Diagram . . . . . . . . . . . . . .
3-60.
3-61.
3-62.
3-63.
3-64.
3-65.
3-66.
4-1.
4-2.
4-3.
6-1.
6-2.
8-1.
8-2.
8-3.
. . . .
Chopper Oscillator Voltage Waveform
•.
Chopper Transistor Voltage Waveform . • . . . .
Input Starting Current Ramp . • • . . . . . . •
Macro Instruction Emulation . • . • • . • . • .
I/O Transfer Between Macro Instruction Execution
t/O Transfer That Interrupts a Macro Instruction
Micro Interrupt Sequence. . . . • ••
.• • • .
DPS Cabinet, Overall View . • . • •
••.•.
DPS Cabinet, Front Panel Open . •.
. •.••
Power Interrupt (Fault) Test Setup
Preparation for Wire Wrapping . • •
Wire Wrap Connections . . . • • • . • • • •
DPS Outline Drawing • . • . • • .
Input/Output Channel Assignments
Installation Summary Sheet • • • •
3-97
3-98
3-99
3-100
3-101
3-106
3-107
3-111
3-112
3-114
3-115
3-115
3-116
3-117
3-118
3-120
3-122
3-125
3-126
3-127
3-128
3-129
3-130
3-130
3-131
3-134
3-139
3-140
3-142
4-3
4-4
4-8
6-7
6-8
8-3
8-8
8-16
iii
LIST OF ILLUSTRATIONS (CONT)
Chapter 9
Dwg. No.
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iv
Fig. No.
000
OOOA
OOOB
OOOC
001
002
003
004
005
006
007
008
009
010
011
012
013
014
015
016
017
018
019
020
021
C22
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
Title
Index
Chassis Map
Power Distribution
Power Distribution
Control Panel and Maintenance Panel Schematic
Conn. Jack/Pin Assignments
CP/IO Mem. Paddle Bd. A
CP/IO Mem. Paddle Bd. B
Maint. Panel Paddle Bd 1 (JOI)
Maint. Panel Paddle Bd I (J02)
Maint. Panel Paddle Bd 2 (J03)
Master Clock
Micro P, Hold, & Display - Bits 00-03
Micro P, Hold, & Display - Bits 04-07
Micro P, Hold, & Display - Bits 08-11
Display Bits 12-15
K Counter, J..L Mem. Sel., Dspl. BFR. 00-03
K Counter, J..L Mem. Sel., Dspl. BFR. 04-07
K Count~r, J..L Mem. Sel., Dspl. BFR. 08-11
J..L Mem. Addrs. 0-377 & Instr. Reg. Bits 0-7
J..L Mem. Addrs. 0-377 & Instr. Reg. Bits 8-16
J..L Mem. Addrs. 1000-1377 & Instr. Reg. Bits 0-7
J..L Mem. Addrs. 1000-1377 & Instr. Reg. Bits 8-16
J..L Mem. Addrs. 400-777
J..L Mem. Addrs. 1400-1777
Mu1t. & Div. Control
Micro Control
Repeat Control & Master Clear
Condition Reg. 0-7
Micro Condo Reg. Bits 8-15
Shift Control
Source Translator
Destination Translator
ALU Bits 0-3
ALU Bits 4-7
ALU Bi ts 8-11
ALU Bits 12-15
ALU File Bits 0~3
ALU File Bits 4-7
ALU File Bits 8-11
ALU File Bits 12-15
Look-Ahead Network
ALU Control
Shift Matrix Control
Shift Matrix Control
Multiply Control
Multiply Control
LIST OF ILLUSTRATIONS (CONT)
Dwg. No.
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Fig. No.
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
093
Ti tle
-
Special Mem. Interface
Special Mem. Interface
Special Mem. Interface
Special Mem. Interface
P Reg. Bits 0-3
P Reg. Bits 4-7
P Reg. Bits 8-11
P Reg. Bits 12-15
Mar & Bkpt Bits 0-7
Mar & Bkpt Bits 8-15
ALU Control II
ALU Control III
RTC Bits 0-7, 16-23
RTC Bits 8-15, 24-31
Status 1 & 2 Bits 0-7
Status 1 & 2 Bits 8-15
PSW Se1. Bits 0-7
PSW Se1. Bits 8-15
Emulate Control I
Emulate Control II
Emu1~te Control III
Emulate Control IV
Instruction Reg. 0-3
Instruction Reg. 4-7
Instruction Reg. 8-11
Instruction Reg. 12-15
ECW ROM
20 MHz Osc.
20 MHz Osc.
Jump & IA
Jump & IA
Mon. Clock Control
Resume & Dual Chan.
Special Mem. Control 1
Special Mem. Control 2
Special Mem. Control 3
NDRO Control & Panel Interface
NDRO Control & Panel Interface
NDRO & CORDIC 0-11
NDRO & CORDIC 12-15
Gen. Reg. 0-3
Gen. Reg. 4-15
~ Mem. Bank Sel. & Misc.
P~ge Control & Counter
Page Reg. Bits 3-5, 15
Page Reg. Bits 0-2
Pwr. Intrpt. & MA CLR
Shift Matrix, Input Reg. R1, R2, 20 -2 7
v
LIST OF ILLUSTRATIONS (CONT)
Dwg. No.
Fig. No.
7101750
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094
095
7101750
096
7101750
097
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098
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710l75Q
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099
100
101
102
103
104
105
106
107
108
109
llO
111
112
113
114
115
200
201
2Q2
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
vi
Title
Shift Matrix, Input Reg. HI, R2, 28 -2 15
Shift Matrix, Data Input, Upper Bits 0,
8,9, 12, 13
Shi ft Ma trix ,Da ta Input, Lower Bits 0,
8, 9, 12, 13
Shift Matrix, Data Input, Upper Bits 2,
10, 11, 14, 15
Shift Matrix, Data Input, Lower Bits 2,
10, 11, 14, 15
Shift Matrix, Ranks 1 & 2
Shift Matrix, Ranks 1 & 2
Two Bit Multiply
Two Bit Multiply
Two Bit Multiply
Two Bit Multiply
Two Bit Multiply
Two Bit Multiply
Micro Memory
Micro Memory
Micro Memory
Micro Memory
Micro Memory
Micro Memory
PRI Control
Int. Adrs.
PRI Control II & Timing
I/O Priori ty I
I/O Priori ty II
X1ator Control
X1ator Control
Xlator Sel.
X1ator & CMA
CMA Drive
Micro Control 15
Micro Control 15
Interrupt Storage
Interrupt Storage
I/O Data Drive & Mon. Clk.
I/O Data Drive & Mon. C1k.
I/O CM Addr Bits 0-3
1, 4, 5,
1, 4, 5,
3, 6, 7,
3, 6, 7,
LIST OF ILLUSTRATIONS (CONT)
Dwg.
No.
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Fig. No.
223
224
225
226
227
228
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250
251
252
253
254
255
256
257.
258
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260
261
262
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276
277
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282
283
284
285
286
287
288
289
290
291
Title
I/O CM Addr Bits 4-7
I/O CM Addr Bits 8-11
I/O CM Addr Bits 12-15
I/O Control Mem. Bits 0-3
I/O Control Mem. Bits 4-7
I/O Control Mem. Bits 8-11
I/O Control Mem. Bi ts 12-15
Mode Select
Grp. 0, Type I, No. 1
Grp. 0, Type I, No. 1
Grp. 0, Type I, No. 1
Grp. 0, Type I, No. 1
Grp. 0, Type II
Grp. 0, Type II
Grp. 0, Type II
Grp. 0, Type II, No. 1
Grp. 0, Type I, No.2
Grp. O. Type I, No. 2
Grp. 0, Type I, No. 2
Grp. 0, Type I, No. 2
Grp. 0, Type III
Grp. 0, Type III
Grp. 0, Type III
Grp. 0, Type II, No.2
Grp. 1, Type I, No. 1
Grp. 1, Type I, No. 1
Grp. I, Type I, No. 1
Grp. 1, Type I, No. 1
Grp. 1, Type II
Grp. 1, Type II
Grp. 1, Type II
Grp. I, Type II, No. 1
Grp. 1, Type I, No.2
Grp. 1, Type I, No. 2
Grp. I, Type I, No. 2
Grp. 1, Type I, No. 2
Grp. 1, Type III
Grp. 1, Type III
Grp. 1, Type III
Grp. 1, Type II, No.2
Grp. 2, Type I, No. 1
Grp. 2, Type I, No. 1
Grp. 2, Type I, No. 1
Grp. 2, Type I, No. 1
Grp. 2, Type II
Grp. 2, Typf' II
Grp. 2, Type II
Grp. 2, Type II, No. 1
Grp. 2, Type I, No.2
vii
LIST OF ILLUSTRATIONS (CONT)
Dwg •. No.
7101750
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7101750
7101750
.. 7101750
7101750
.. 7101750
7101750
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7101750
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7101750
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viii
Fig. No.
- --
292
293
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308
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3.73
374
375
Title
Grp. 2, Type I. No. 2
Grp. 2, Type It No. 2
Grp. 2, Type I, No. 2
Grp. 2, Type III
Grp. 2, Type III
Grp. 2, Type III
Grp. 2, Type II, No. 2
Grp. 3, Type I, No. 1
Grp. 3, Type I, No. 1
Grp. 3, Type I, No. 1
Grp. 3, Type I, No. 1
Grp. 3, Type II
Grp. 3, Type II
Grp. 3, Type II
Grp. 3, Type II, No. 1
Grp. 3, Type I, No. 2
Grp. 3, Type I, No. 2
Grp. 3, Type I. No. 2
Grp. 3, Type I, No. 2
Grp. 3, Type III
Grp. 3, Type III
Grp. 3, Type III
Grp. 3, Type II, No.2
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schematic
-15V Slow Interface Logic Schemati~
-15V Slow Interface LogiC Schematic
-15V Slow Interface Logic Schematic
-3V Fas t Interface .Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
LIST OF ILLUSTRATIONS (CONT)
Dwg. No.
7101750
7101750
7101750
7101750
7101750
7101750
7101750
7101750
7101750
7101750
7101750
7101750
7101750
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7101750
7101750
-71Q1750
7101750
7101750
7101750
7101751
71017;J1
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
Fig. No.
376
377
378
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384
385
386
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394
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406
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411
412
413
414
415
Title
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
-3V Fast Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schemati,;
+3.5V ANEW Interface Logic Schema ti:~
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
+3.5V ANEW Interface Logic Schematic
NTDS Serial Interface Logic Schematic
NTDS Serial Interface Logic Schematic
NTDS Serial Interface Logic Schematic
NTDS Serial Interface Logic Schematic
NTDS Serial Interface Logic Schematic
NTDS Serial Interface Logic Schematic
NTDS Serial Interface Logic Schematic
NTDS Serial Interface Logic Schematic
NTDS Serial Interface Logic Schematic
NTDS Serial Interface Logic Schematic
Memory Chassis Map
Bank 0 Memory Control Board
Bank 0 Memory Control Board
Bank 1 Memory Control Board
Bank 1 Memory Control Board
Bank 0 Memory Data Board 0-3
Bank 0 Memory Data Board 0-3
Bank 1 Memory Data Board 4-7
Bank 1 Memory Data Board 4-7
Bank 0 Memory Array Board 0
Bank 0 Memory Array Board 0
Bank 0 Memory Array Board 1
Bank 0 Memory Array Board 1
Bank 0 Memor.y Array Board 2
Bank 0 Memory Array Board 2
Bank 0 Memory Array Board 3
Bank 0 Memory Array Board 3
ix
LIST OF ILLUSTRATIONS (CONT)
DW9. No.
7101751
7101751
7101751
1101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
7101751
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7101751
: 7101751
7101751
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7101751
7101751
7101751
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7101751
7101840
7101875
7101880
x
Fig. No.
416
417
418
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461
Title
Bank 1 Memory Array Board 4
Bank 1 Memory Array Board 4
Bank 1 Memory Array Board 5
Bank 1 Memory Array Board 5
Bank 1 Memory Array Board 6
Bank 1 Memory Array Board 6
Bank 1 Memory Array Board 7
Bank 1 Memory Array Board 7
Functional Card Index
MCB - Control I
MCB - Control II
MCB - Control III
MCB - Address Reg. Bits 0-7
MCB - Address Reg. Bits 8-14
MCB - Bit Group Xlation
MCB - Bit Diode Xlation
MCB - Word Group, Word Diode Xlation
MCB - Mod. 0, 1 Read Drive
MCB - Mod. 2, 3 Read Drive
MCB - Mod. Write
MDB - Mod. 0 Write Bits, Bits 0-17
MDB - Mod. 1 Write Bits, Bits 0-17
MDB - Mod. 2 Wri te Bi ts, Bi ts 0-17
MDB - Mod. 3 Write Bits, Bits 00-17
Mem. Data Board - Bits 0-4
Mem. Data Board - Bits 5-9
Mem. Data Board - Bits 10-15
MAB Sense Amps. Data Bits 00 - Parity L
MAB Sense Amps. Data Bits 09 _-_ Parity U
MAB Bi tAxis, Bi ts 00 & 01------ MAB Bit Axis, Bits 02 & 03
MAB Bit Axis, Bits 04 & 05
MAB Bit Axis, Bits 06 & 07
MAB Bit Axis, Bits Parity L & 08
MAB Bit Axis, Bits 09 & 10
MAB Bit Axis, Bits 11 & 12
MAB Bit Axis, Bits 13 & 14
MAB Bit Axis, Bits 15 & Parity U
MAB Word Axis, 00-03
MAB Word Axis, 04-07
MAB Word Axis, 10-13
MAB Word Axis, 14-17
MAB Word Axis, 20-23
MAB Word Axis, 24-27
MAB Word Axis, 30-33
MAB Word Axis, 34-37
3~A, 400 Hz Power Supply Schematic
l~, 400 Hz Power Supply Schematic
3~A, 60 Hz Power Supply Schematic
LIST OF ILUJSTRATIONS (CONT)
Dwg. No.
7101885
7101990
7101995
7119455
Fig. No.
Ti tIe
10, 60 Hz Power Supply Schematic
30Y, 60 Hz Power Supply Schematic
30Y, 400 Hz Power Supply Schematic
Power Supply Control Card Schematic
xi
LIST OF TABLES
Number
Title
Reference Data . . . • • • • •
• • • . • • • •
Equipment, Accessories, and Documents Supplied . • • • .
Equipment'and Publications Required But Not Supplied.
2-I.
Control Panel Switches and Indicators
2-2.
Maintenance Panel Switches and Indicators
2-3.
Display Select Codes • . •
2-4.
Initial Switch Positions.
2-5.
Microinstruction Repertoire • • . • • •
2-6.
D-Designator • . • • • • . • •
2-7.
S-Designator . . • . • • • • •
Macroinstruction Repertoire
2-8.
3-I.
Parallel I/O Channel Groups • • • • • •
3-2.
Fixed Addresses in Micro Memory
3-3.
Micro Address Selection . • . • . . • • • •
Microcode for Command Generator ROM Chip U03
3-4.
3-5.
Microcode for Command Generator ROM Chip U06
3-6.
Microcode for Command Generator ROM Chip U04 •
Discrete Bit Inputs to MPC Source Selector.
3-7.
3-8. , ALU Shift Selector Functions • • • •
Condition Code Designator Functions
3-9.
3-10. Interrupt Priority • . • . • . • • •
3-11. Microcode for Shift Control ROM 09 • •
3-12. Microcode for Shift Control ROM 24 .
3-13. Adder Functions High Speed Multiply
3-14. Microcode for Multiply Control ROM 22
3-15. Memory Interface Signals . . . • • •
3-16. Address Bit Decode • . . . . . . . .
3-17. Read/Restore Sequence of Events
. • • •
3-18. Read/Modify/Write Sequence of Events . . . . •
3-19. I/O Control Chip Function Relative to Function Bits
3-20. I/O Buffer Control Word Bit ASSignments
.•
3-21. Registers Rl and R2, and ALU Control for Buffers •
3-22. I/O Cycle Timing on Data Transfer
• • • . • •
3-23. I/O Dual Channel Output Data Transfer
3-24. I/O Dual Channel Input Data Transfer • . • • • .
3-25. Function of Parallel Output Channel Lines
3-26. Function of Parallel Input Channel Lines • • .
3-27. Function of Intercomputer Channel Control Lines
3-28. MIL-STD-188 Serial I/O Characteristics • • •
3-29. MIL-STD-188 Control Lines . • • • • • . • . . •
3-30. RS-232 Standard Serial I/O Characteristics • . .
3-31. NTDS 32-Bit Serial I/O Characteristics • . • • . •
3-32. Power Supply Characteristics • • • • . • • • • • •
3-33. Micro Branch Conditions for Emulate Start Operation • • . • •
3-34. Micro Branch Conditions for Interim Sequences
3-35. Micro Branch Conditions for General Display
4-I.
Preventive Maintenance Index . . • • . . • • • • •
4-2.
Control and Maintenance Panel Indicators • • . • . • •
5-I.
Multiple-Usage Circuit Cards . . • ••
. •••
5-2.
Troubleshooting Index . . • . . • • • •
•• • .
I-I.
1-2.
1-3.
xii
Page
1-11
1-15
1-15
2-3
2-6
2-11
2-12
2-18
2-19
2-20
2-25
3-5
3-11
3-11
3-14
3-15
3-16
3-18
3-25
3-28
3-31
3-35
3-38
3-42
3-43
3-52
3-65
3-70
3-72
3-81
3-85
3-86
3-87
3-88
3-89
3-90
3-91
3-108
3-110
3-112
3-113
3-115
3-123
3-137
3-137
3-153
4-1
4-5
5-2
5-2
LIST OF TABLES (CONT)
Number
5-3.
5-4.
5-5.
5-6.
5-7.
6-1.
7-1.
7-2.
7-3.
7-4.
7-5.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
9-1.
Title
Page
Relay Index . • .
Lamp Index
Protective Device Index
Power Supply Test Data
Thermostat Test Points
. . • •
• • • • •
Special Equipment and Tools Required But Not Supplied . . . . •
List of Major Units . • • • • • • • • • . . • . • • •
Data Processing Set AN/UYK-20(V) and AN/UYK-20X(V), Parts List
List of Common Item Descriptions
. • • •
List of Attaching Hardware
• • . •
List of Manufacturers • • • • • • •
• • • • . • • • • • • • .
Power Connector Pin Assignments • • • • • • •
• • • • .
Parallel Channel I/O Connector Pin Assignments (Even Group)
Parallel Channel I/O Connector Pin Assignments (Odd Group)
Serial Channel I/O Connector Pin Assignments
Dual Channel I/O Jumper Plug Pin Assignments
External Real Time Clock Connector Pin Assignments
• ••••
Logic Voltages . . • • •
Equipment Diagram List • • . • • • • • • • . • • •
5-3
5-3
5-4
5-5
5-5
6-1
7-3
7-5
7-46
7-49
7-54
8-9
8-9
8-10
8-12
8-13
8-13
8-15
9-1
xiii
Figure 1-1.
1-0
Data Processing Set, AN/UYK-20(V)1
CHAPTER 1
GENERAL INFORMATION
1-1.
INTRODUCTION.
1-2. SCOPE. This technical manual describes the Data Processing Set (figure 1-1).
AN/UYK-20(V), hereafter generally called the DPS. The manual documents all variations of the DPS in existence at time of publication, and provides the information
normally necessary to install, operate, and maintain it.
1-3. MANUAL ORGANIZATION. This technical manual is divided into ten chapters.
Chapter 9, Equipment Diagrams, is in a separate B-size volume. Chapter 10 is in a
separate A-size volume and documents the maintenance/diagnostic program. Chapters
1 through 8 are in this volume; a brief description of each chapter follows.
1-4. Chapter 1 - General Information. Chapter 1, General Information, contains a
brief description of the DPS and a basic explanation of the functions or operations
it performs. It also contains a quick reference table of the equipment characteristics, and lists of recommended tools and associated equipment.
1-5. Chapter 2 - Operation. Chapter 2. Operation, describes the operating controls
and indicators, gives instructions for manual operation, and lists the repertoire of
computer macro instructions and micro instructions.
1-6. Chapter 3 - Functional Description. Chapter 3, Functional Description, describes the internal operation of the DPS on the basis of primary block diagrams and
functional block diagrams.
1-7. Chapter 4 - Preventive Maintenance. Chapter 4, Preventive Maintenance, provides scheduled procedures for ensuring that the DPS is in optimum operating condition.
1-8. Chapter 5 - Troubleshooting. Chapter 5, Troubleshooting, suggests ways to
use all data contained in this manual when troubleshooting, and provides procedures
for isolating various faults.
1-9. Chapter 6 - Corrective Maintenance. Chapter 6, Corrective Maintenance, provides information for removal, replacement, reinstallation, and repair of parts and
assemblies.
1-10. Chapter 7 - Parts List. Chapter 7, Parts List, lists and describes the
replaceable electrical and mechanical parts.
1-11. Chapter 8 - Installation. Chapter 8, Installation, contains information concerning equipment installation, including outline drawings to illustrate space
requirements and to aid in interconnecting to other equipment.
1-12. Appendices. Appendices following Chapter 3 contJin detailed descriptions of
the macro and micro instruction repertoires and a glossary of unique terms.
1-1
1-13.
FUNCTIONAL DESCRIPTION.
1-14. The Data Processing Set AN/UYK-20(V) meets the various processing requirements of Naval shipboard, land-based, and submarine combat systems. It is a modular, medium-scale, general purpose digital data processing device using a microprogrammed control structure. The microprogram consists of micro instructions and
control data stored in a read-only memory (ROM). The computer operates from a
stored program of macro instructions read from main memory to perform arithmetic
operations, solve real-time problems, control other equipment, and perform a
variety of other data processing operations. It performs two's complement integer
arithmetic using signed numbers. Its logic construction is parallel. The basic
word length is 16 bits which may be handled as 8-bit bytes (such as ASCII character codes), as 16-bit words, or as double-length 32-bit words. It has memory
addressing capability of up to 65K 16-bit words which may be treated as groups of
pages for relative (virtual) addressing. The memory cycle time is 750 nanoseconds.
The DPS communicates with peripheral equipment through an I/O controller containing
up to 16 channels, which may be parallel or serial channels or a mixture of both.
It has an interrupt structure, dependent on priority assignments, which permits
interruption of the normal program sequence to perform special functions. It allocates a portion of micro-memory for a user-defined microprogram. It has a real
time clock and a monitor clock which operate either from an internal oscillator or
from an external clock input.
1-15. Figure 1-2 is a simplified block diagram of the DPS. The sections shown are
functional divisions, not separate physical entities. The processor/emulator performs the arithmetic and data processing operations as directed by a program of
instructions. The I/O circuits transfer data between the DPS and peripheral equipment. The main memory stores instructions, operands, and other data. The processor, I/O, and memory interface circuits are under the control of a microprogrammed
controller (MPC) operating from its own microprogram stored in a read-only memory.
Data transfers between the major elements occur over two 16-bit bidirectional
busses: a source bus and a destination bus. Control signals between sections do
not use the busses, but are wired directly.
1-16. CONTROL PANELS. The DPS has two control panels: an operator's panel and a
maintenance panel. The panel controls provide for applying and removing power,
starting and stopping operations, operating in different modes, master clearing
(master reset), controlling programmed stops, and for other manual control or manipulation of the DPS. Th~ panel controls permit displaying and manually modifying
register contents through the register display. The registers that can be displayed and modified are the general registers, the P register (program address
register), the memory address register, the U register (macro-instruction register),
status register ~l, status register ~2, the real-time clock registers, the breakpoint register, the I/O control memory, the micro-address register, and the microinstruction register. A detail description of the operating controls is contained
in Chapter 2.
1-17. MICROPROGRAMMED CONTROLLER (MPC). The MPC provides all control functions for
the DPS to execute the program stored in main memory. The MPC has its own microprogram (also called firmware) stored in a read-only memory that the MPC executes
to provide the control functions and data manipulations. All registers and logic
networks in the DPS are addressable by the micro-instructions. For each macroinstruction read from main memory, several micro-instructions are used by the MPC
to provide control, timing, and data transfers necessary to execute the macro-
1-2
SOURCE BUS
•
MICRO
PROGRAM
STORE
(ROM)
--.
~
Ir
l.i""""
MPC
OPERATOR G
MAINTENANCE
PANELS
j
~
.......
,..
.......
-
.
I/O
CONTROL
PROCESSOR/
EMULATOR
-- -
-\
"----
CONTROL
PANEL
BUS
NDRO (ROM)
MEMORY
MEMORY
INTERFACE
DESTINATION BUS
I
W
To Peripheral Devices
Figure 1-2.
Simplified Block Diagram
,
.
MAIN
MEMORY
(ORO)
.
instruction. In effect. the microprogram replaces some of the control logic that
would otherwise be required to execute the macro-instruction.
1-18. The MPC receives an Emulator Control Word (ECW) from the processor for each
macro-instruction read from main memory. The ECW contains control bits and an
address pointer. The address pointer is the starting address of a microprogram
subroutine which the MPC uses to execute that particular micro-instruction. When
a subroutine is completed. the MPC branches to a microprogram subroutine to read
the ntxt instruction from main memory.
1-19.
The MPC also controls the panel display function.
1-20. PROCESSOR/EMULATOR. The processor/emulator contains logic circuits which
augment the MPC. It contains an instruction register to hold the macro-instruction
during execution and other registers and subsections that operate under MPC control
to form an efficient general purpose processor. These include the general registers, status register. real time clock and monitor clock registers. interrupt control. and high-speed shift and multiply circuits.
1-21. An instruction is fetched from main memory and loaded into the instruction
register hy the MPC via the source bus. The instruction is translated and the
processor sends an Emulator Control Word (ECW) to the MPC. Each instruction has
its own ECW which is stored in a small ROM. Thp ECW directs the MPC in execution
of the instruction.
1-22. MEMORY INTERFACE. The memory interface handles the transfer of information
between the processor or the MPC and main memory. and between I/O control and main
memory. An I/O channel memory request has priority over a program request. The
memory interface is asynchronous, using requests and acknowledges. It initiates
the memory for a read or write operation and sends a 16-bit address to memory. The
data word transferred between the memory interface and memory also contains 16 bits.
1-23. The memory interface section contains a 192-word non-destructive readout
(NORO) memory. Access to the NORO is controlled by the condition of the NORO mode
bit in the status #1 register. When the bit is clear, addresses from 00-77 (octal)
and 300 to 477 (octal) are read from the NORO memory instead of the main memory.
1-24. MAIN MEMORY. The main memory provides storage for the macroprogram. It is
available in 8192-word (8K) increments to a maximum of 65,536 words (65K). Word
length is 16 bits and the main memory cycle time is 750 nanoseconds nominal.
1-25. I/O CONTROL. The I/O Control section provides for communication between the
OPS and peripheral equipments, including up to sixteen I/O channels. The system
provides asynchronous parallel I/O channels, expandable in groups of four channels.
and/or serial channels, expandable in groups of two channels, to a possible combined total of 16 channels. The channels within a group must have identical interface characteristics. All channels ore fully duplexed to permit input and output
transmissions to occur simultaneously.
1-26. The parallel I/O channels operate with either a Naval Trctical Data System
(NTOS) Fast (-3v), an NTOS Slow (-15v), or an ANEW (r3.5v) interface. They are
capable of operation in single word (16 bit) mode or dual word (32-bit) mode. Both
single and dual channels are capable of operation in an Intercomputer mode. Dual
channels are also capable of operation in a UYK-7 compatible Externally Specified
Addressing (ESA) mode when so requested on the initial equipment order.
1-4
1-27. The NTDS serial I/O channel is an asynchronous double word length (~1~-Li·
d1'lUI r,ommunication channel formed from two adjoining 16-bit channels. Ear:h 11·-:) i
ch8nnel requires one coaxial cable for input and another for output. Information
is tr1'lnsmitted using bi-polar, phase modulated, serial pulse trains.
1-2B. Synchronous serial channels provide communications at bit rates up to 9hlKl
bits per second (bps). They are capable of accepting an external clock sign81.
1-29. Asynchronous serial I/O channels may have any four of the following modulation rates selectable through the program: 75, 150, 300, 600, 1200, or 2400 baud.
The four rates desired for each two-channel group must be specified at time of
equipment order. The character interval consists of up to ten signal elements with
equal time intervals: they comprise one start element, five to seven data elements,
one character parity element, and one or two stop elements.
1-30. POWER. The power section includes the power supply and power distribution
circuits. This section converts ac input power into the dc power required for the
logic circuitry and the memory. The power supply is regulated against input voltage variations and transients, and it protects against output overload conditions.
It has sufficient capacitor energy storage so that it continues to provide in-tolerance output power for a minimum of 250 usec after an input voltage loss is detected,
to permit storing the contents of the working registers before shutdown occurs.
1-31.
PHYSICAL DESCRIPTION.
1-32. Figures 1-1 and 1-3 picture the DPS. Its nomenclature is AN/UYK-20(V) Data
Processing Set for the 400 Hz configurations or AN/UYK-20X(V) for the 60 Hz configurations. It consists of a single pabinet. A hinged door, called the ControlIndicator Unit, forms the front of the cabinet. Its front side contains an operator's control panel with the most essential controls and indicators. A more complete maintenance control panel is mounted on the back side of the door and is
accessible with the door open. An alarm horn and the air intake grill and
filter are also on this door. Immediately behind the door is the memory chassis,
which is hinged and mounted on slides so it may be extended and completely exposed
for servicing. Behind the memory, and accessible when the memory chassis is extended, are the processor/IOC chassis and the power supply. The rear panel of the
cabinet contains the power connector and grounding stud. The cabinet's left side
as you face the cabinet contains air exhaust grills for the power supply, processor/
IOC chassis, and memory chassis, each of which has its associated blower. Cabinet
dimensions are given in Chapter 8 of this manual.
1-33. The processor/IOC chassis is called the Processor-Verifier Unit. It contains
two sizes of printed circuit cards. The processor circuits are mostly containec on
single-width cards, as illustrated in figure 1-4, and the I/O circuits are mostly
contained on triple-width cards, as illustrated in figure 1-5. The single-width
circuit cards are single-layer boards with printed wiring on both sides; the triplewidth cards are three-layer boards. Single width cards have one 56-pin connector;
triple width cards have two connectors. Guide pins on the connectors are keyed to
keep the cards from being inserted into the wrong jack, and the card shape keeps
them from being inserted into their jacks backwards. The cards have test points
along their top edges and a notch or square blivet identifies the first test point.
The maintenance philosophy expects faulty cards to be replaced, rather than repaired. The rear panel of the processor/IOC chassis contains the I/O connectors.
With the chassis removed from the cabinet this panel can be removed for access to
]-5
......
I
0'
Fi gu re 1- 3.
Data Pr oc es sin g Se t,
Open
the I/O connector wire wrap and the circuit card connector wire wrap. The processor/IOC chassis is variable and may contain ofte or .ore of the interface kits
listed below, depending on the I/O type. Ind i.terface levels required. Each kit
consists of a set of circuit cards.
1)
Interface Kit, Slow, MK-1693/UYK-20(V)
2)
Interface Kit, Fast, Negative,
3)
Interface Kit, Fast, Positive, MK-1695/UYK-20(V)
4)
Interface Kit, Serial Synch, nomenclature not aSligned.
5)
Interface Kit, Serial Asynch, nomenclature not assigned.
6)
Interface Kit, Fast Serial, nomenclature not a.signed.
7)
Interface Kit, Slow Serial Synch, nomenclature not assigned.
8)
Interface Kit, Slow Serial Asynch, nomenclature not assigned.
MK-169~/UYK-20(V)
1-34. The memory is made up of three different ty,es of circuit boards. These
are the Memory Control Board (MCB); the Memory Oata Board (MOB); and the Core
Memory Unit, MU-604/UYK-20(V), generally called the Memory Array Board (MAB).
Each MCB contains control and addressing circuits for up to 32K of memory; each
MDB contains a data register and bit drivers for up to 32K of memory; and each
MAB contains an 8K x 16 bit core matrix, together with associated drivers and
sense amplifiers. The memory chassis, with its full COMplement of two MCB and
two MOB boards is designated the Control, Core Memory Unit. From one to eight
Core Memory Units (MAB) are inserted into the chalsis to produce the required memory capacity, from 8K to 65K words. A memory chassis containing optional MCB and
MOB boards which have additional circuitry for a direct memory access (OMA) feature
may be specified at time of order. According to the maintenance philosophy, faulty
memory cards, like faulty processor/IOC cards, should be replaced, rather than
repaired.
1-35. The power supply is a single chassis, intended for replacement rather than
on-site repair. It supplies all dc power needed by the OPS. The power supply
exists in six configurations, depending on the input power requirements as follows:
n
115 Vac, 30 A , 400 Hz - PP 7032/UYK-20(V)
2)
208 Vac, 30 'Y
3)
115 Vac, 10, 400 Hz - Nomenclature not assigned
4) ·115 Vac, 30 A
400 Hz - Nomenclature not assigned
60 Hz - Nomenclature not assigned
5)
208 Vac, 30 'Y , 60 Hz - Nomenclature not assigned
6)
115 Vac, 10, 60 Hz - Nomenclature not assigned
J-7
TO BE SUPPLI ED.
Figur e 1-4.
1-8
Typic al Single -Widt h Circu it Card
l
TO BE SUPPLIED
Figure 1-5.
Typical Triple-Width Circuit Card
1-36.
REFERENCE DATA.
1-37.
Table 1-1 lists the features of the DPS in quick reference format.
1-38.
EQUIPMENT, ACCESSORIES, AND PUBLICATIONS.
1-39. Table 1-2 lists equipment, accessories, and publications normally supplied
with the DPS. (Check specific ordering document.)
1-40.
EQUIPMENT REQUIRED BUT NOT SUPPLIED.
1-41. Table 1-3 lists equipment not supplied with the DPS, but usually required
for operation or for maintenance.
1-10
Tahle 1-1.
Reference Data
ITEM
Input Power
CHARACTERISTICS
115 Vac + 5%, 3 phase (delta), 115 Vac + 7%, single
-
-
phase, or 208 Vac ! 5%, 3 phase (wye); 60 Hz! 5% or
400 Hz ! 5%; 1000 Watts max.
Internal Power
+ 5 Vdc, +.3V, -.lV, 35 Amp., max. (Logic)
+ 5 Vdc, !.25V, 17.5 Amp., max. (Memory)
- 5.2 Vdc, !.3V, 10 Amp., max.
+ 12 Vdc, !.6V, 1 Amp., max.
+ 15 Vdc, !.3V, 12 Amp., max.
- 5 Vdc, !.4V, 1 Amp., max.
- 16 Vdc, !.8V, 2.4 Amp., max.
100 mv max. combined noise and ripple on all voltages.
Cooling
Ambient air circulated by internal blowers,
cu ftl
minute maximum.
Maximum heat dissipation:
Operating Environment
Operating temperature:
Humidity:
32 0 to 122°F. (0 0 to 50°C)
95% maximum without condensation
Nonoperating temperature:
Size and Weight
3400 BTU/hr (1000 watts)
_40 0 to 167 0 F (_62 0 to 75°C)
Height 20 in. max.; width 19 in. max.; depth 24 in. max.,
not including shock pins.
Weight 200 pounds maximum.
Functional Character-
Micro-programmed control structure
istics
750 nsec basic cycle time
Word length:
16 bits parallel
65,536 word maximum memory size
16 or 32 general registers
Direct and multilevel indirect addressing
Program controlled relative addressing
1-11
Table 1-1.
Reference Data (Cont)
ITEM
CHARACTERISTICS
Functional Character-
Real-time clock register and Interrupt clock register
istics (Cont)
capable of operating from internal oscillator or external
clock source.
Breakpoint register; two status registers.
Multiclass and multilevel interrupt processing.
Running time meter.
192-word bootstrap memory
Power monitoring and auto restart
Up to 16 input/output channels in any combination of
parallel channels in groups of four and serial channels
in groups of two.
Processor-initiated I/O program chain.
Parallel I/O Channel
Processor-initiated program chain; Asynchronous; Full
Basic Features
duplex; Buffer Control Memory; Single or Dual Channel
(16-bit or 32-bit).
Parallel I/O Channel
Available in groups of four to total I/O complement of
Options
16 (the channels within each 4-channel group must have
the same characteristics); NTDS Parallel Slow (-15 volt)
interface; NTDS Parallel Fast (-3 volt) interface; ANEW
Parallel (+ 3.5 volt) interface; Intercomputer or Normal
mode, any channel.
compatible) •
1-12
ESA mode on dual channel (AN/UYK-7
Table ]-1.
Reference Data (Cont)
ITEM
Parallel I/O Rates
CHARACTERISTICS
Transfer Rates (16-bit words/second) depending on
Interface Type:
Number of
Channels
+3.5V, -3V
-15V
1-4
190,000
41,600
5-8
400,000
83,300
9-12
750,000
l24 r 900
1,000,000
166,600
13-16
These rates are the maximum for the specified number of
active input channels or output channels.
The combined
transfer rates (both input and output channels active)
are twice the rates specified but not greater than
1,300,000 words/second, which is the maximum I/O data
handling rate.
The 32-bit word transfer rates are slower
due to the additional 750 nsec needed for each word to
transfer the additional 16 bits to and from memory.
MIL-STD-188
Either asynchronous or synchronous modes.
Serial I/O Interface
Full duplex.
Buffer control memory.
Available in groups of two channels.
Modulation rate up to 9600 Bits/second in synchronous
mode.
Any four of the following bit rates (75, 150, 300, 600 9
1200, or 2400) program selectable per two channel group
in asynchronous mode.
(Rates to be specified on order.)
Program selectable character size of 5, 6, 7, or 8 bits.
Capable of loopback testing (diagnostic aid).
All interface lines of one channel in one connector.
1-13
Taple 1-1.
Reference Data (Cont)
ITEM
CHARACTERISTICS
EIA Standard
Either asynchronous or synchronous modes.
RS-232 Serial
Full duplex.
I/O Interface
Buffer control memory.
Available in groups of two channels.
Modulation rate up to 9600 Bits/second in synchronous
mode.
Any four of the following bit rates (75, 150, 300, 600,
1200, or 2400) program selectable per two channel group
in asynchronous mode.
(Rates to be specified on order.)
Program selectable character size of 5, 6, 7, or 8 bits.
Capable of loopback testing (diagnostic aid).
All interface lines of one channel in one connector.
NTDS Serial
Asynchronous mode.
I/O Interface
Full duplex.
Each group consists of one output channel and one
input channel.
32-bit data word with sync bits, identifier bits, and
control bits (input and output).
Continuous communication between interface and
peripheral equipment.
Output' channel - one coax cable.
Input channel - one coax cable.
1-14
Tahle 1-2.
NOMENCLA1URE
QTY
PER
EQUIP
1
Equi pmen t., Accessories, and Documents Suppl ied
DESIGNATION
NAME
PURPOSE
AN/UYK-20(V) or
Data Processing Set
AN/UYK-20X(V)
Tahle 1-3.
QTY
PER
EQUIP
2
1
Equipment and Puhlications Required But Not Supplied
NOMENCLATURE
NAME
DESIGNATION
Technical Manual, Vol. 1
Not available
Technical Manual, Vol. 2
Not available
Technical Manual, Vol. 3
Not
I/O Device
Variable
8
REQUIRED USE
Technical documentation
vai lable
Provide input and output
capabilities
1
Power Cable, 30 or
7098772-00 or
To connect input power
Power Cable, 10
7098772-01
Variable
Input Cable
7126392
To connect parallel I/O
Variable
Output Cable
7126393
channels, if utilized.
Variable
Serial I/O Connector
7128005-00
To connect MIL-STD-188
or RS-232 channels, if
utilized.
2
I/O End-around Test
7126394-00
For I/O channel testing
7128052
To facilitate removal of
Cables
1
Card Extractor, Memory,
Right Hand
1
Card Extractor, Memory,
circuit cards
7128053
Left Hand
1-15
Table 1-3.
QTY
PER
EQUIP
Equipment and Publications Required But Not Supplied (Cont)
NOMENCLATURE
NAME
REQUIRED USE
DESIGNATION
1
Card Extractor, Logic
7100903-00
1
Diagnostic Program Tape
Not available
Troubleshooting
.
I
1-16
CHAPTER 2
OPERATION
2-1.
INTRODUCTION.
2-2. This chapter presents information concerning the use of the control panel and
the maintenance panel, and also lists the repertoire of macroinstructions and microinstructions. The control panel is located on the exterior of the DPS front access
door (Control-Maintenance Unit). It contains the minimum of switches and indicators
necessary for monitoring and controlling DPS operations. The maintenance panel is
on the inside of the access door anct is accessible only with the door opened. It
permits operating in several modes at several rates, and permits inspecting and/or
changing the contents of various registers.
NOTE
Operation of the DPS with the access door opened permits rf radiation.
2-3.
CONTROL PANEL SWITCHES AND INDICATORS.
2-4. Figure 2-1 shows the control pan01.
and indicators.
2-5.
Table 2-1 describes the panel's switches
MAINTENANCE PANEL SWITCHES AND INDICATORS.
2-6. Figure 2-2 shows the maintenance panel. Table 2-2 describes the panel's
switches and indicators. Tabl~ 2-3 describes the maintenance panel display select
codes.
2-7.
OPERATING PROCEDURES.
2-8.
TURN-ON PROCEDURE.
1. Operate switches on control panel and maintenance panel to initial settings
per table 2-4.
2.
Operate CIRCUIT BREAKER ON/OFF switch to ON position.
3. Operate POWER, BLOWER ON/OFF switch to ON position. Observe that POWER,
BLOWER indicator lights and that blowers operate to discharge air from three
exhaust grills on side of cabinet.
4. Operate POWER, LOGIC ON/OFF switch to ON position. Observe that POWER, LOGIC
indicator lights and that FAULT, POWER and OVER TE~W indicators do not light.
NOTE
Turning on power places the DPS in a master cleared state with Run mode
selected.
2-9. TURN-OFF PROCEDURE. Depress STOP and reverse above procedure, first turning
off POWER, LOGIC, then POWER, BLOWER, and finally CIRCUIT BREAKER.
Figure 2-1.
Control Panel
TABLE 2-1.
CONTROL PANEL SWITCHES AND INDICATORS
IDENTIFICATION
TYPE
CIRCUIT BREAKER
ON/OFF
Two-position
toggle switch
FUNCTION
ON position enables primary power to
the DPS.
OFF position disables primary power to
the DPS.
BLOWER POWER
ON/OFF
Two-posi tion
toggle switch
ON position enables power to the DPS
cooling fans and enables LOGIC POWER
ON/OFF switch function.
OFF position disables power to the DPS
cooling fans and disables LOGIC POWER
ON/OFF switch function.
BLOWER POWER
Indicator (neon
with white lens)
LOGIC POWER
ON/OFF
Two-position
toggle switch
When lit, indicates blower power is
, applied.
ON position enables power to the dc
power supply.
OFF position disables power to the dc
power supply.
LOGIC POWER
Indicator (incandescent with white
lens)
When lit, indicates dc power is
applied.
POWER FAULT
Indicator
When lit, indicates a Power Fault
Interrupt has occurred.
POWER FAULT CLR
Two-position
return-to-neutral
toggle switch
When momentarily operated to the CLR
position, clears the POWER FAULT indicators on both the control panel and
the maintenance panel.
PROGRAM FAULT
Indicator (red LED
with clear lens)
When lit, indicates a Program Fault
Interrupt has occurred, caused by
attempting to execute an illegal
instruction.
PROGRAM FAULT
CLR
Two-position
return-to-neutral
toggle switch
When momentarily operated to the CLR
position, clears the PROGRAM FAULT
indicator on the control panel and
the PROG FAULT indicator on the maintenance panel.
PROG RUN
Indicator (green
LED with green
lens)
When lit, indicates DPS is executing
instructions in Run Mode.
2-3
TABLE 2-1.
IDENTIFICATION
CONTROL PANEL SWITCHES AND INDICATORS (CONT)
TYPE
FUNCTION
OVER TEMP
Indicator (neon
with red lens)
When lit, indicates DPS internal
cabinet air temperature is within
25 0 F of the maximum temperature at
which the DPS can operate without
component damage.
ALARM
Audible
This alarm sounds if the ALARM ENABLE/
DISABLE/TEST switch is in the ENABLE
position and the internal cabinet air
temperature is within 25 0 F of the
maximum temperature at which the DPS
can operate without component damage.
ALARM ENABLE/
DISABLE/TEST
Three-position
toggle switch
ENABLE position enables the audible
alarm function.
DISABLE position disables the audible
alarm function.
TEST position causes the audible alarm
to sound and the OVER TEMP indicator
to light.
BATTLE SHORT
ON/OFF
Two-position
toggle switch
ON position disables DPS overtemperature shutdown function.
OFF position enables DPS overtemperature shutdown function.
BATTLE SHORT
Indicator (neon
with red lens)
When lit, indicates BATTLE SHORT
switch is in the ON position.
BOOTSTRAP 1-2
Two-posi tion
toggle switch
Selects one of two possible bootstrap
programs in the NDRO memory. Operates
in conjunction with the Op Code =
40RR, a = 7 Conditional Jump macroinstruction and may be used, at programmer's discretion, to control
branching in other programs.
LOAD/STOP
Three-position
return-to-neutral
toggle switch
When momentarily operated to the LOAD
position, causes the DPS to execute a
master clear, select Run mode, then
begin executing the bootstrap program
selected by the BOOTSTRAP 1-2 switch.
When momentarily operated to the STOP
position, causes the DPS to stop
executing instructions if the computer is in the Run mode.
2-4
Figure 2-2.
Maintenance Panel
TABLE 2-2.
IDENTIFICATION
AUTO START/START
W~INTENANCE
TYPE
Three-position
toggle switch
PANEL SWITCHES AND INDICATORS
FUNCTION
When set to the AUTO START position,
causes the DPS to begin executing
instructions at NDRO bootstrap memory
address 000000 when power is applied
or is restored after a power failure.
When momentarily operated to the
START position, causes the DPS to
begin executing instructions in the
mode selected.
STOP
Two-position
return-to-neutral
toggle switch
When operated to the STOP position
while the DPS is executing instructions in the Run mode, causes the DPS
to stop executing macroinstructions.
MA CLR
Pushbutton switch
When operated while the DPS is not in
Run condition, the DPS resets to a
master cleared state*.
When operated while the DPS is in the
Run mode, clears the FAULT indicators
on the control and maintenance panels.
BREAK PT
READ/OFF
Two-position
toggle
READ position causes the DPS to stop
executing instructions after reading
data from the memory address specified
by the contents of the breakpoint
register. OFF position disables the
read stop.
BREAK PT
WRITE/OFF
Two-position
toggle
WRITE position causes the DPS to stop
executing instructions after writing
data in the memory address specified
by the contents of the breakpoint
register. OFF position disables the
write stop.
PROG RUN
Indicator-switch
(green LED with
green lens)
Indicator function: When lit, indicates the DPS is executing instructions in the Run mode.
Switch function: Selects run
condition in microstep mode.
* Master Cleared State: P register, status register nl, and status register #2
cleared; real time clock and monitor clock disabled; page registers set equal
to their own address; I/O channels cleared as specified for the 70RR, m = 0
macroinstruction, and Normal Display selected.
2-6
TABLE 2-2.
IDENT IFICATION
POWER FAULT
MAINTENANCE PANEL SWITCHES AND INDICATOI{S (CONT)
FUNCTION
TYPE
Indicator-switch
(red LED with
clear lens)
Indicator function: When lit, indicates a Power Fault Interrupt has
occurred.
Switch function: When operated
clears the POWER FAULT indicators
on both the operator's control panel
and the maintenance panel.
PROG FAULT
Indicator-switch
(red LED with
clear lens)
Indicator function: When Ii t, indicates a Program Fault Interrupt has
occurred caused by attempting to
execute an illegal instruction.
Switch function: When operated,
clears the PROGRAM FAULT indicator
on the operator's control panel and
the PROG FAULT indicator on the
maintenance panel.
PROGRAM STOP
Indicator (red
LED with clear
lens)
When lit, indicates a programmed stop
has been executed. (40RR, A = 11, 12,
or 13.)
PROGRAM STOP
l/OFF
Two-position
toggl e swi tch
In 1 position, causes a program stop
when the DPS executes a jump macroinstruction (40RR with an A-value =
12.
PROG STOP
2/0FF
Two-position
toggle switch
In 2 position, causes a program stop
when the DPS executes a jump macroinstruction (40RR) with an A-value =
13.
Time meter
4 digit, 0000 to
9999
Records accumulated hours that dc
power has been applied.
DIAGNOSTIC
JUMP
Two-position
toggle switch
In the JUMP position, enables branching
on the F = 14, M = 17 Branch microinstruction. Its usage causes the DPS
to jump from the operating microprogram.
When used in connection with NORMAL
DSPL, GENL DSPL, DISPLAY NUMBER =
1111, and MICRO STEP it enables manual
loading of the micro P register. (See
paragraph 2-XX.)
2-7
TABLE 2-2.
IDENTIFICATION
DIAGNOSTIC
DISPLAY
PROCESSOR
DISABLES: RT CLK
DISABLE/INT/EXT
MAINTENANCE PANEL SWITCHES AND INDICATORS (CONT)
TYPE
FUNCTION
Two-position
toggle switch
In the DISPLAY position while the DPS
is in the Microstep mode.
Three-position
toggle switch
a.
With MICRO ADRS set, REGISTER/
DATA displays the address of the
next microinstruction to the executed.
b.
With MICRO INSTR set, REGISTER/
DATA displays the microinstruction
currently being executed.
c.
With NORMAL DSPL set, REGISTER/
DATA displays the data on the
source bus.
DISABLE position inhibits incrementing
of the Realtime Clock Register and
decr~menting of the Monitor Clock
register.
INT position causes the Realtime-Clock
Register and the Monitor Clock register
to use the internal clock source for
timing.
\
EXT position causes the Realtime Clock
Register and the Monitor Clock register
to use the external clock source for
timi ng.
PROCESSOR
DISABLES: ADV P
Two-position
toggle switch
Up position inhibits incrementing of
the P-Register, thus causing the DPS
to repeatedly perform one l6-bit macroinstruction.
PROCESSOR
DISABLES:
INTERCMPTR
TIME OUT
Two-position
toggl e switch
Up position inhibits the occurrence of
a Class III Intercomputer Timeout
Interrupt.
MODE: MICRO
STEP
Indicator-switch
(red LED with
clear lens)
Indicator function: When lit, indicates DPS is in Microstep mode to
execute a single microinstruction.
(To clear, depress DISPLAY SELECT CLR
switch.)
Switch function: When operated, places
DPS in Microstep mode.
2-8
TABLE 2-2.
IDENTIFICATION
MODE:
OP STEP
MAINTENANCE PANEL SWITCHES AND INDICATORS (CONT)
TYPE
Indicator-switch
(red LED with
clear lens)
FUNCTION
Indicator function: When lit, indicates DPS is in Op Step mode or in
Microstep mode to execute a single
macroinstruction.
Switch function: When operated,
clears Run mode and places DPS in Op
Step mode, to execute one macroinstruction per operation of the
START switch.
MODE:
RUN
Indicator-switch
(red LED with
clear lens)
Indicator function: When lit, indicates DPS is in Run mode or in Microstep mode to execute successive
instructions.
Switch function: When operated,
clears Op Step mode and enables the
Run mode.
DISPLAY SELECT
CLR
Pushbutton
switch
When operated, clears DISPLAY NUMBER
o through 3 and clears the Microstep mode.
ALTER MODE
SET/CLEAR
Two-position
toggle switch
In the SET position,
a.
Causes individual bit of register
being displayed to set when corresponding REGISTER/DATA indicator
switch is operated.
b.
Causes all bits of register being
di spl ayed to clear when REGISTER/
DATA SET/CLR switch is operated.
In the CLEAR position,
REGISTER/DATA
SET/CLR
Pushbutton
switch
a.
Causes individual bit register
being displayed to set when
corresponding REGISTER/DATA indicator switch is operated.
b.
Causes all bits of register being
displayed to clear when REGISTER/
DATA SET/CLR switch is operated.
When operated, sets or clears the
register being displayed in REGIS~ER/
DATA indicator switches 0 through 15,
dependent on ALTER MODE SET/CLEAR
position.
2-9
TABLE 2-2.
IDENTIFICATION
REGISTER/DATA
through 15
o
MAINTENANCE PANEL SWITCHES AND INDICATORS (CONT)
TYPE
Indicator-switches
(red LED with clear
lens)
FUNCTION
Indicator function: Display contents
of selected register.
Switch function: Modify contents of
selected register.
DISPLAY
SELEC~
MICRO ADRS
MICRO INSTR
NORMAL DSPL
INSTR REG
GENL DSPL
GENL REG
DISPLAY NUMBER
0-3
2-10
Indicator- switches
(red LED with clear
lens)
Indicator function: When lit as
specified in table 2-3, indicate
REGISTER/DATA is displaying the
corresponding register. Changing
the contents of REGISTER/DATA changes
the contents of the register being
di spl ayed.
Switch function: When operated
as specified in table 2-3, causes
REGISTER DATA to display the corresponding register contents.
Operation of anyone of MICRO
ADRS, MICRO INSTR, or NORMAL DSPL
causes the other two to clear.
Operation of anyone of INSTR
REG, GENL DSPL, or GENL REG causes
the other two to clear.
TABLE 2-3.
[fJ
0:::
0..,
z
0
'"
~
~
0:::
[fJ
1.'
spected should be sho~n in REGISTER/DATA.
7. If it is desired to change the information,
new contents into it.
ihl~
e.il:'ll'
UH~
prol'.pdures outlined in
~."j.
iJ Cc;\
'H.ldress to be in-
HEGIS'fEH/UATA and set the
NOTE
If the address to be inspected next is not the next consecutive address,
clear the P register and set it to the address dpsired before performing
step 8.
8. Press the START switch. The new word (or old if not changed) is now stored
in memory, and the contents of the next adjacent address is displayed in the
REGISTER DISPLAY.
9.
Repeat steps 7 and 8 until all addresses desired are inspected/changed.
2-21. LOAD MICRO P PROCEDURE. When debugging programs, or when manually troubleshooting the DPS, it may be useful to reach a particular micro memory address. The
following procedure loads the address into the micro P register:
1.
Depress STOP switch.
2.
Select NORMAL DSPL and GENL DSPL.
Set DISPLAY NUMBER indicator-switches to
llll.
3.
Select MICRO STEP mode 9 MICRO ADRS, DIAGNOSTIC DISPLAY, and PROG RUN.
4 .. Operate DIAGNOSTIC JUMP toggle switch to up position.
5. Operate START switch repeatedly until selected address appears in REGISTER/
DATA. (It may be necessary to step a number of times to complete the microprogram
subroutine before micro P is loaded.) When selected address appears in micro P,
the next operation of the START switch will perform the microinstruction at that
address.
6. To step through successive microinstructions following the selected address,
proceed per steps 4, 6, and 7 of paragraph 2-23.
NOTE
To start the microprogram running from a particular microinstruction,
perform steps 1, 2, and 4, select RUN mode, and depress START switch.
2-15
2-22.
time:
OP STEP PROCEDURE.
1.
Depress STOP switch.
Proceed as follows to perform one mac,roinstruction at a
2. Load desired main memory address into P register by selecting NORMAL DSPL and
GENL DSPL, setting DISPLAY NUMBER indicator-switches to 0000, and inserting address
into REGISTER/DATA indicator-switches.
3. If necessary, insert required data into general registers and memory addresses
that will be used by the macroinstruction.
4.
Select OP STEP mode.
5. To keep repeating the same macroinstruction, operate PROCESSOR DISABLES ADV P
switch to the up position. (This is usable only for RR and RI format macroinstructions; RK and RX require P to advances to obtain the second half of the instruction.)
6.
Depress START switch for each instruction execution.
2-23. MICRO STEP PROCEDURE. Proceed as follows to step through a macroinstruction,
performing one microinstruction at a time:
Depress STOP switch.
1.
a. If the desired macroinstruction is contained in main memory, set its address
into P register by selecting NORMAL DSPL and GENL DSPL, setting DISPLAY NUMBER indicator-swiches to 0000, and inserting addr,ess into REGISTER/DATA indicatorswitches.
b. If the desired macroinstruction is not in main memory, load it at a convenient address per paragraph 2-19.
c. If desiring to start at a certain microinstruction, load its micro memory
address into micro P register per paragraph 2-21.
2.
Select MICRO STEP.
3.
Select LIAGNOSTIC DISPLAY and:
a. MICRO ADRS to display the address of the next microinstruction to be performed.
4.
b.
MICRO INSTR to,display the microinstruction being executed, or
c.
NORMAL DSPL to display the data on the source bus.
Select DIAGNOSTIC JUMP and depress PROG RUN indicator-switch.
NOTE
If RUN mode is selected, DPS will micro step through successive macroinstructions. If OP STEP mode is selected, DPS will micro step to completion of first macroinstruction, then begin micro stepping through
console mode micro program subroutine.
2-16
5.
Depress START switch for each micro step.
6.
At completion of micro step sequence, clear MICRO STEP by depressing DISPLAY
CLR switch, and extinguish PROG RUN by selecting OP STEP.
SELE~:T
2-24. EMERGENCY OPERATION. A BATTLE SHORT switch on the control panel disables
the ,wertemperature shutdown function, thus permi tting the DPS to continue operating
inan emergency situation.
2-25, EMERGENCY TURN-OFF. For fast turn-off in an emergency, set the CIRCUIT
BREA)(ER ON/OFF swi tch to OFF. The DPS will accomplish an orderly shutdown intern; lly, generating a power fault interrupt and storing essential register. Before
turn:,ng CIRCUIT BREAKER on again set POWER LOGIC and BLOWER swi tches to OFF.
2-26,
MICROINSTRUCTIONS
2-27.
The microinstruction repertoire is shown in table 2-5. The repertoire conof 16 basic microinstructions with many variations. The basic microinstruction
formEt is divided into four 4-bit fields. The F-field, bits 15-12, specifies the
function to be performed such as add, subtract, shift. etc. The D-field, bits 11-8,
defirC)s the register or network to receive the dc:ta on the destination bus. Table
2-6 lLsts the destinations. Destination I (Dl) or Destination 2 (02) is determined
by tile F-field or M-field for each microinstruction. The S-field, bits 7-4 (sometime~' also called the 0 or origin field), defines the register I (S1) or Source 2
(S2) is determined by the F-field or M-fip.ld for each microinstruction. The M-field,
bits )-3, modifies the microinstruction. Some microinstructions use special fields
of K (constant), X (12-bit address), or F2 (extension of F-field). Appendix A
describes each microinstruction in detail.
sist~
2-28.' MACROINSTRUCTIONS.
2-29. INSTRUCTION FORMATS. The DPS performs instructions using five instruction
word formats. Instructions may be single length or double length.
2-30. Format RR. The Format RR instructions are single length and use the format
shown in figure 2-3. They perform operations using the general registers. (RH =
Regis;er and Register.) Unless otherwise specified in an individual instruction,
the a.designator selects the Ra register, and the m-designator selects the Rm
regis ;er.
2-31. Format RI. The Format RI instructions are also single length. They may be
eithe' Type 1 or Type 2. The Format RI Type 1 instructions use the format shown in
figur ~ 2-4. Y is generated using the x and d-designators as specified in figure
2-5. Format RI Type 2 instructions use the format shown in figure 2-3. They perform
opera ,ions using the general registers and a memory reference. (RI = Eegister and
Immed ate Memory.) Unless otherwise specified in an individual instruction, the
a-des: gnator selects the Ra register, and the m-designator selects the Rm register
whose contents shall be used as a memory address Y.
2-32. Format RK. Format RK instructions are double length, consisting of two words
store\ in consecutive memory addresses. The first word uses the format shown,in
figur,· 2-3. The second word is a 16-bi t quanti ty designated y. The Format RK instruc'ions perform operations using general register and memory references. (RK =
Eegisl er, and fonstant (Immediate Operand).) Unless otherwise specified in an individ~al instruction, the a-designator selects the Ra register, and the m and
2-17
TABLE 2-5.
MICROINSTRUCTION REPERTOIRE
INSTRUCTION FORMAT
15 14 13 12
F
=a
F
=1
=2
F =3
F =4
F =5
F =6
F =7
F
7 6 5 4
D
S
3 2 1
M
X (12 Bits)
a
DESCRIPTION
Transfer
Unconditional Branch
D
S
M
Add S2
D
S
M
Shift
D
S
M
Add Sl
D
S
M
Subtract
D
S
M
Logic I
D
S
M
Logic II
= 10
F = 11
F = 12
D
K
Add constant
D
K
Subtract constant
D
K
Transfer constant to Dl
F
= 13
D
K
Transfer constant to D2
F
= 14
F2
K
Branch
= 15
F = 16
F2
F2
= 17
D
F
F
F
2-18
11 10 9 8
S
M
Micro repeat
K
S
Micro control
M
Emulate
TABLE 2-6.
D-DESIGNATOR
o
DESTINATION 2 (02)
DESTINATION 1 (D1)
VALUE
o
Unassigned
f-LP register
1
Breakpoint
Condition register
2
P Register
Display register
3
Memory Data register
Cycle counter
4
General register
RTC Upper
5
Status register U1
Una ssigned
6
Status register u2
Unassigned
7
RTC Lower
Unassigned
10
AO/Shift Register Upper/Page
Address Counter
Page Table
11
AI/Shift Register Lower
Unassigned
12
A2
Instruction register/SGR
13
A3
SGR
14
A4
I/O Control Memory Translator
15
A5
I/O Translator
16
A6/Shift Counter
Output Data
17
A7/MAR
I/O Control Memory
2-19
TABLE 2-7.
S-DESIGNATOR
S
2-20
SOURCE 2 (S2)
SOURCE 1 (Sl)
VALUE
o
Unassigned
tLP Hold Register
1
Breakpoint
Condition Register
2
P Register
Display Register
3
Memory Data Register
Normalize/Panel Select
4
Page Table
RTC Upper
5
IA Pointer
STATUS 1 Register
6
Shift Matrix Output
STATUS 2 Register
7
Monitor Clock/Part Prod/Feed
RTC Lower
10
AO
General Register
11
Al
Cordie Table
12
A2
Instruction Register With
AM-Field Sign Extension
13
A3
Instruction Register
14
A4
Class I & II Interrupt Codes
15
A5
Class III Interrupt Codesl
I/O Translator
16
A6
Input Data
17
A7
I/O Control Memory
15
_.--
d-clP51(lnalt \I
1
..•
-. -- ----_.. __._-------- --- ---.-.--.-- , . -
Format:
00
~
Formilt HR
Ul ,-. format iii
10' FOlfr,at HK
11
,~
Format RX
~---------------------
-----_..-------
Operiltion Corle
Figure 2-3.
Basic Instruction Word Format
8
15
L~_I--~=---.-----------I
Opf!ration Codl!-
'-------
Figure 2-4.
Instruction Word Format for Format HI Type 1
2-21
JJ
15 1 141 13 1 121111 10 1 91 81 71 61 51 4 3 2 11
!
1
1 I 0
110 1 1 I 0 0
0
0 1 0
0
0
1
I
1
I
I
I
1
Xl
(Sigd Extended) ~ X 0 1 0 0 010 0
1
I
I
:
I
1
I
I
1
I
I
~
I
I
I
I
0 I 0
0
1
0
01
0
1
I
1
!
*
0
0
1
0
1 10
1
110
I
0
0
1 10
1
1 10
1
1 10
I
I
I
I
I
I
1
Contents of p*
1
d-designator from the
instruction word.
Y shall be the sum of (P)
and d as follows:
I
I
I
I1
I
I
I
I
I
I
I
I
J0
I
1 0
(P) + d when x = 0
(Positive)
0
(P) + d when x = 1
(Negative)
I,
I
I
I
I
1
After normal incrementation resulting from instruction fetch.
Figure 2-5.
Address Generation Example for Format RI Type 1 Instruction
y designators are used to form an operand (a l6-bit signed literal or constant) or
a memory address, designed Y. Y is formed as follows:
1)
When m equals zero, Y is equal to y.
2) When m does not equal zero, Y is the sum of the contents of Rm and Y.
om-designator selects the Rm register.
The
2-33. Format RX. The Format RX instructions are double length, consisting of two
words stored in consecutive memory addresses. The first word uses the format as
specified in figure 2-3. The second word is a l6-bit quantity designated y. The
Format RX instructions perform either whole word (16-bit) or byte (8-bit) operations
using the general registers and memory references as specified in the following
subparagraphs. (RX = Begister and memory with or without inde~ing).
2-34. When the Format RX instruction designates whole word operations, the a, m
and y-designators are used as follows, unless otherwise specified in an individual
instruction~
1)
The a-designator selects the Ra register.
2)
The m and y-designators form a memory address designated Y as follows:
a)
2-22
When m equals zero, Y is equal to y and is a direct memory reference.
b) When m is not equal to 0, 10, 12, 14, or 16 or when m equals 10, 12, 14, or
16 and the 2-bit field of status register #2 corresponding to the particular Rm
register is equal to a or 1, Y is the sum of the contents of Rm and y is a direct
memory reference.
c) When m equals 10, 12, 14, or 16 and the 2-bit field of Status Register #2
corresponding to the particular Rm register is equal to 2, Y is the contents of y
and is an address pointer to the first word of a two word indirect memory reference.
Figure 2-6 specifies IW word formats and interpretation for indirect addressing.
d) When m equals 10, 12, 14, or 16 and the 2-bit field of status register #2
corresponding to the particular Rm register is equal to 3, Y is the sum of the
contents of Rm and y and is an address pointer to the first word of a two word
indirect memory reference. Figure 2-6 specifies IW word formats and interpretation
for indirect addressing.
,
"-V
J
Y
J VALUE
ADDRESS DETERMINATI ON
a
Final operand at Y
1
Final operand at Y + Rx
2
Final operand at Y+ Rm
3
Final operand at Y + Rm+l
4
Cascaded IW at Y
5
Cascaded IW at Y + Rx
6
Cascaded IW at Y + Rm
7
Cascaded IW at Y+ Rm+l
10-17
Figure 2-6.
Unassigned
Indirect Address Format
2-23
2-35. When the Format RX instruction designates byte operations, the a, m and
y-designators are used as follows, unless otherwise specified in an individual
instruction:
1)
The a-designator selects the Ra register.
2) When m does not equal zero, the m-designator selects a General Register
designated Rm. The contents of Rm are used to form a memory address designated
Y and a byte position in the memory location as follows:
the
the
the
the
a) The least significant bit (LSB) of the contents of Rm (bit 0) determines
byte position in the selected memory location. When the LSB is 0, the byte is
eight most significant bits (bits 8 through 15) in the memory location. When
LSB is 1, the byte is the eight least significant bits (bits 0 through 7) in
memory location.
b) Y is the sum of y and the contents of Rm right-shifted one position and
zero-filled in the left most position. The original value of Rm remains in Rm.
3) When the m-designator equals zero, Y is equal to y and the byte is the
eight most significant bits in the memory location.
2-36. Format RL. The Format RL instructions are single length and use the format
as specified in figure 2-3. The a-designator selects the Ra register; the mdesignator field contains a 4-bit, unsigned literal; the f-designator is interpreted as a secondary function code.
2-37. DOUBLE LENGTH WORDS. The DPS performs double-length word operations when
specified in an individual instruction. In the double instructions, the contents
of two adjacent registers or memory locations are used as one 32-bit word. The
word at a location designated Ra , Rm, or Y becomes the most significant 16 bits of
the double length word, and the word at a location designated Ra+1, Rm+l, or Y + 1,
respectively, becomes the least significant 16 bits of the double length word. The
memory address or register address of the most significant 16 bits must be an even
number.
2-38. SHIFT INSTRUCTIONS. Shift instructions shift the contents of a register or
registers to the right, left, or left circular. The contents of bits 0 through 5
of the quantity specified in the RK or RR instructions or bits 0 through 3 of an
RL format instruction word determine the number of places shifted. The shift
operations ate as follows:
1) Right shifts move the data toward the least significant bit position. Bits
shifted out of the least significant bit position are lost. After each shift step,
the most significant bit position is filled with either a zero (zero extended to
fill) or a sign bit (sign extended to fill) as specified in the individual instruction.
2) Left shifts move the data toward the most significant bit position. Bits
shifted out of the most significant bit position are lost. At each shift step,
the least significant bit position is filled with a zero. A sign change at the
most significant bit position sets the OVERFLOW designator.
2-24
3) Left shift circular means that the data is shifted left, and the bits shifted
out of the most significant bit position are transferred to the least significant
bit position. A sign change at the most significant bit position sets the OVERFLOW
designator.
2-39. INSTRUCTION REPERTOIRE. Table 2-8 lists the macroinstruction repertoire and
shows the operation code, the format, and the execution time for each instruction.
Detailed descriptions of each instruction are provided in Appendix B.
MISCELLANEOUS OPERATING AIDS. Miscellaneous items of value to operators of
the DPS are listed in the Appendices as follows:
~-40.
1)
Detailed Descriptions of Microinstruction Repertoire - Appendix A.
2)
Detailed Description of Macroinstruction Repertoire - Appendix B.
3)
Internal Micro Program Listing - Appendix C.
TABLE 2-8.
OPERATION
CODE
00
FORMAT
MACROINSTRUCTION REPERTOIRE
INSTRUCTION
EXECUT ION TIME
MICROSECONDS
-
RR
RI
RK
RX
Unassigned (See Note)
Unassigned
Unassigned
Byte Load
2.25
01
RR
RI-2
RK
RX
Load
Load
Load
Load
.75
1.5
1.5
2.25
02
RR
RI-2
RK
RX
Una ry-Ari thmeti c
Load Double
Unassigned
Load Double
1.0
2.25
RR
RI
RK
RX
Unary-Control
Unassigned
Unassigned
Load Multiple
RR
RI
RK
RX
Unary-Shift
Unassigned
Unassigned
Byte Load and Index by 1
3.0---74.0
RR
RI-2
RK
RX
Set Bit
Load and Index by 1
Unassigned
Load and Index by 1
1.5
1.5
03
04
05
-
3.0
.75-7>8.0
-
-
1.5 +'!'N times .75
-
-
2.25
-
2.25
*N = number of registers loaded
NOTE: Unassigned instructions produce an instruction fault.
2-25
TABLE 2-8.
OPERATION
CODE
06
07
10
11
12
13
14
*N
= number
2-26
MACROINSTRUCTION REPERTOIRE (CONT)
INSTRUCTION
FORMAT
EXECUTION TIME
MICRO SECONDS
1.5
2.55
RR
RI-2
RK
RX
Clear Bit
Load Double and Index by 2
Unassigned
Load Double and Index by 2
RR
RI-2
RK
RX
Compare Bit
Load PSW
Unassigned
Load PSW
3.75
RR
Logical Right Single Shift
1.0
RI
RK
Unassigned
Logical Right Single Shift
1.7
RX
Byte Store
2.4
RR
Algebraic Right Single Shift
1.0
RI-2
RK
Store
Algebraic Right Single Shift
1.7
1.7
RX
Store
2.4
RR
Logical Right Double Shift
2.6
RI-2
RK
Store Double
Logical Right Double Shift
2.4
3.2
RX
Store Double
3.2
RR
Algebraic Right Double Shift
2.6
RI
RK
Unassigned
Algebraic Right Double Shift
3.2
RX
Store Multiple
RR
Algebraic Left Single Shift
1.0
RI
RK
Unassigned
Algebraic Left Single Shift
1.7
RX
Byte Store and Index by 1
2.4
of registers loaded
3.3
1.8
3.0
TABLE 2-8.
OPERATION
CODE
MACROINSTRUCTION REPERTOIRE (CONT)
INSTRUCTION
FORMAT
EXEC UT I ON TI ME
MICROSECONDS
RR
Circular Left Single Shift
1.0
RI-2
RK
Store and Index by 1
Circular Left Single Shift
1.7
1.7
RX
Store and Index by 1
2.4
RR
Algebraic Left Double Shift
2.7
RI-2
RK
Store Double and Index by 2
Algebraic Left Double Shift
2.6
3.3
RX
Store Double and Index by 2
3.3
RR
Circular Left Double Shift
2.4
RI-2
RK
Store Zeros
Circular Left Double Shift
1.7
3.0
RX
Store Zeros
2.4
20
RR
RI-2
RK
RX
Subtract
Subtract
Subtract
Subtract
.75
1.5
1.5
2.25
21
RR
RI-2
RK
RX
Subtract Double
Subtract Double
Unassigned
Subtract Double
1.7
2.25
22
RR
RI-2
RK
RX
Add
Add
Add
Add
.75
1.5
1.5
2.25
23
RR
RI-2
RK
RX
Add Double
Add Double
Una s si gned
Add Double
1.5
2.25
RR
RI-2
RK
RX
Compare
Compare
Compare
Compare
.90
1.5
1.7
2.25
15
16
17
24
-
3.0
-
3.0
2-27
TABLE 2-8.
OPERATION
CODE
25
MACROINSTRUCTION REPERTOIRE (CONT)
FORMAT
INSTRUCTION
EXEC UTI ON TIME
MICROSECONDS
Compare Double
Compare Double
Unassigned
Compare Double
3.0
26
RR
RI-2
RK
RX
Multiply
Multiply
Multiply
Multiply
3.8
4.0
4.4
4.6
27
RR
RI-2
RK
RX
Divide
Divide
Divide
Divide
6.8
7.0
7.4
7.5
30
RR
RI-2
RK
RX
AND
AND
AND
AND
.75
1.5
1.5
2.25
31
RR
RI-2
RK
RX
OR
OR
OR
OR
.75
1.5
1.5
2.25
32
RR
RI-2
RK
RX
Exclusive
Exclusive
Exclusive
Exclusive
33
RR
RI-2
RK
RX
Masked
Masked
Masked
Masked
34
RR
RI-2
RK
RX
Compare
Compare
Compare
Compare
35
RR
RI-2
RK
I/O Command
Biased Fetch
Remote Execute
4.0* + I/O Inst
2.25
1.5+ Inst.
RX
Biased Fetch
3.0
OR
OR
OR
OR
Substitute
Substitute
Substitute
Substitute
Masked
Masked
Masked
Masked
1.7
2.25
-
.75
1.5
1.5
2.25
1.4
1.5
2.0
2.25
1.5
1.7
2.1
2.4
*Includes the time to clear bits 14 and 15 of memory address 000140.
2-28
.
RR
RI-2
RK
RX
TABLE 2-8.
OPERATION
CODE
MACROINSTRUCTION REPERTOIRE (CONT)
INSTRUCTION
FORMAT
.
EXECUTION TIME
MICROSECONDS
36
RR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
37
RR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
40
RR
RI-1
RK
RX
Conditional Jump
Local Jump
Conditional Jump
Conditional Jump
1.1
1.2
1.7
2.4
41
RR
RI-l
RK
RX
Index
Local
Index
Index
1.4
2.0
2.1
2.25
42
RR
RI
RK
RX
Jump and Link Register
Unassigned
Jump and Link Register
Jump and Link Register
1.2
2.25
RR
RI-1
RK
RX
Unassigned
Local Jump and Link Memory
Jump and Link Memory
Jump and Link Memory
2.0
2.9
3.2
44
RR
RI-l
RK
RX
Jump Register = 0
Local Jump Llual
Jump Register = 0
Jump Register = 0
1.4
1.2
2.1
2.25
45
RR
RI-l
RK
RX
Jump Register 1- 0
Local Jump Not E4ua1
Jump Register 1- 0
Jump Register 1- 0
1.4
1.2
2.1
2.25
46
RR
RI-l
RK
RX
Jump Register Positive
Local Jump Greater than Or Equal
Jump Register Positive
Jump Register Positive
1.4
1.2
2.1
2.25
47
RR
RI-l
RK
RX
Jump Register Negative
Local Jump Less Than
Jump Register Negative
Jump Register Negative
1.4
1.2
2.1
2.25
43
Jump
Jump Indirect
Jump
Jump
1.2
-
-
2-29
TABLE 2-8.
MACROINSTRUCTION REPERTOIRE (CONT)
"
OPERATION
CODE
INSTRUCTION
FORMAT
Unassigned
Unassigned
Unassigned
Unassigned
51
RR
,RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
52
RR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
53
RR
RI
RX
Unassigned
Unassigned
Unassigned
Unassigned
RR
RI-2
'RK
ftX
Load Address Register
Load Address Register
Unassigned
Load Address Register Multiple
1.8
2.6
ftft
ftl-2
RK
RX
Store Address Register
Store Address Register
Unassigned
Store Address Register Multiple
1.8
2.6
56
RR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
57
RR
ftI
ftX
Unassigned
Unassigned
Unassigned
Unassigned
60
RL-l
RL-2
RL-3
RL-4
Logical Right Single Shift
Algebraic Right Single Shift
Logical Right Double Shift
Algebraic Right Double Shift
1.3
1.3
2.8
2.8
61
RL-l
RL-2
RL-3
RL-4
Algebraic Left Single Shift
Circular Left Single Shift
Algebraic Left Double Shift
Circular Left Double Shift
1.3
1.3
2.8
2.8
RK
54
55
RK
*n == Number of address registers
.
--
RR
RI
RK
RX
50
2-30
EXECUT ION TIME
MICROSECONDS
--
3.0 + .75 x n':'
-
3.0 + 1.1 x
--
'.
n~'
TABLE 2-8.
OPERATION
CODE
62
63
64
65
66
67
70
71
72
MACROINSTRUCTION REPERTOIRE (CONT)
EXECUTION TIME
FORMAT
INSTRUCTION
~IICROSECONDS
RL-l
RL-2
RL-3
RL-4
Subtract
Subtract Double
Add
Add Double
RL-l
RL-2
RL-3
RL-4
Load
Compare
Multiply
Divide
4.2
7.4
1m
HI
RK
RX
Unassigned
UnLlssigned
Unassigned
Byte Subtract
2.25
RR
RI
RK
RX
Unassigned
Unassigned
Una s s ignt'd
Byte Add
2.25
RR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Byte Compare
2.25
RR
RI
RK
RX
Reserved
Unassigned
Unassigned
Byte Compare and Index by 1
2.25
RR
Channel Control (Command)
Ril
RI
RK
RX
Channel Control (Chaining)
Unassigned
Unassigned
Initiate Transfer (Chaining)
RR
RI
RK
RK
RX
RX
RR
RI
RK
RX
RX
Unassigned
Unassigned
Initiate Chain (Command)
Load Control Memory (Chaining)
Load Control Memory (Command)
Load Control Memory (Chaining)
Unassigned
Unassigned
Unassigned
Store Control Memory (Command)
Store Control Memory (Chaining)
.9
1.8
.9
1.8
.9
1.2
30.0 for m = 0-7;
2.0 for m = 10-17
2.25
4.5
2.25
2.25
3.0
3.0
3.0
3.0
2-31
TABLE 2-8.
OPERATION
CODE
73
74
75
76
77
2-32
FORMAT
MACROINSTRUCTION REPERTOIRE (CONT)
INSTRUCTION
EXECUTION TIME
MICROSECONDS
RR
RI
RK
RX
Halt/Interrupt (Chaining)
Unassigned
Unassigned
Set/Clear Flag (Chaining)
RR
RI
RK
RX
Unassigned
Unassigned
Conditional Jump (Chaining)
Unassigned
RR
1.5
RI
RK
RX
Search for Sync; Set Monitor/
Set Suppress (Chaining
Unassigned
Unassigned
Unassigned
RR
RR
RI
RK
RX
RX
Set/Clear Discretes (Command)
Set/Clear Discretes (Chaining)
Unassigned
Unassigned
Store Status (Command)
Store Status (Chaining)
1.5
1.5
RR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
1.5
-
3.0
-
2.25
-
3.0
3.0
-
--
•
CHAPTER 3
FUNCTIONAL DESCRIPTION
3-1.
INTRODUCTION.
3-2. This chapter describes the internal operation of the DPS. The description is
presented in two levels: primary block diagram level and functional block diagram
level.
3-3.
PRIMARY BLOCK DIAGRAM DESCRIPTION.
3-4. The primary block diagram (figure 3-1) divides the DPS into six major functional sections. These are the Microprogrammed Controller (MPC) , the Processor/
Emulator, the Memory Interface, the Main Memory, the I/O Controller, and the Power
Sections. Data transfers between sections are handled by the Source Bus and the
Destination Bus.
3-5. The MPC controls the DPS. The main difference between MPC-controlled computers and standard computers is that most of the hard wired control is replaced by
microprogrammed control. They operate, like other computers, from a program of
instructions stored in the main memory. This program is called the macroprogram to
distinguish it from the microprogram that controls the MPC. The computer instructions are called macroinstructions to distinguish them from the MPC's microinstructions. The MPC in the Data Processing Set, AN/UYK-20(V), is a general purpose
controller. It has its own read only memory (ROM) to hold its microprogram, and
can be programmed to provide control for a wide range of functions. It is essentially a small computer, and performs many of the required computer functions within
its own circuits. The link between the macroprogram and the MPC is provided by an
"emulator" which decodes the macroinstructions and causes entrance into an MPC
microprogram subroutine to perform (emulate) the desired function. Sometimes all
of the circuitry with the exception of the MPC itself is called the emulator, since
it all augments the MPC and assists it in emulating required functions. The capabilities of microprogram controlled computers can often be changed or increased
simply by adding new translations into the emulator and new subroutines into the
microprogram.
3-6. MICROPROGRAMMED CONTROLLER. The MPC executes 16 basic microinstructions with
many variations. (See Appendix A for a detailed description of each microinstruction). Data transfers occur over the two bi-directional data buses. The two-bus
structure allows instruction overlapping to increase the microinstruction execution
rate. Two fields within the microinstruction word define what register or network
is applied to the source bus (S-field) and what register or network is the recipient
of data on the destination bus (D-field). Simply stated, a microinstruction performs a function on the source and transmits the result to the destination. Following is a description of the major MPC elements.
3-7. The micro memory is a read-only memory. It is capable of holding up to 4K
(4096) words of microprogram including 512 addresses ~sually reserved for optional
customer specified routines. Microprogram~ can be changed only by substituting
different pre-programmed cards. The micro memory control section contains thp. addreSSing circuits that control the reading of the micro memory. The micro function
control section receives the current microinstruction from the micro memory, translates it, and issues control signals to all sections of the DPS to carry out
3-1
the instruction. It includes the master clock which provides timing for the entire
DPS. The repeat control section controls the repetitive cycling of microprogram
subroutines, as required by the Repeat microinstructions. The arithmetic section
contains accumulator storage registers and an arithmetic/logic unit (ALU) which
performs arithmetic and logical operations on the operands. The displaY,control
section, under the control of a microprogram subroutine, provides the interface
between the operator and maintenance panels and the displayable registers of the
DPS.
3-8. PROCESSOR/EMULATOR. The processor/emulator is concerned
instructions. It contains many of the registers and functions
with the central processor portion of a computer, but performs
the control of the MPC. The following paragraphs describe the
emulator subsections.
with the macronormally associated
its functions under
major processor/
3-9. The function control section translates the macroinstruction word and sends an
Emulator Control Word (ECW) to the MPC directing it to perform the proper microprogram subroutine for accomplishing each macroinstruction. The general registers
can be used for accumulator storage, as scratch pad registers, as index registers,
etc. They are normally addressed by the A and M fields of the macroinstruction
word. There may be one or two groups of 16 general registers; if there are two
groups, a status register bit determines which group is addressed. The program
status section contains the two status registers, the real time clock and monitor
clock registers, and the interrupt control circuits. The status registers store
program status information, provide for selecting the general register group, enable
reading from NDRO memory, control the disabling of interrupts, and control direct
and indirect addressing; the real time clock and monitor clock permit the DPS to
monitor elapsed time; the interrupt circuits handle program interrupts according to
their aSSigned priorities. The high speed shift and multiply section contains a
shifting matrix and multiply logic which operate without involving the MPC arithmetic unit, and perform their tasks faster than possible in the MPC. The multiply
logic operates with two multiplier digits at a time.
3-10. MEMORY INTERFACE. The memory interface handles the transfer of information
to and from the main memory. It permits reading or writing of full words or either
byte of a word, or reading a word, modifying it, and restoring the modified word.
The memory interface section divides into three subsections: memory address control,
memory data interface, and "NDRO memory.
3-11. The memory address control section provides the address information to the
main memory." The program address normally increments by one after each memory
reference. A breakpoint function allows the program to be stopped when a preselected memory address is referenced. Paging circuits permit the memory to be
addressed as 64 separate and interchangeable lK portions. The memory data interface
section transfers data to and from the main memory. The NDRO memory consists of up
to 192 words of read-only memory generally used for a bootstrap load program.
Access to the NDRO memory is controlled by a bit in status register 1.
3-12. MAIN MEMORY. The main memory, which is used for storage of the macroprogram
is a coincident current magnetic core memory, expandable to 65K (65,536) words in
8K (8192) word increments. Word length is 16 bits. Cycle time is approximately
750 nsec for a read or write cycle, and approximately one ~sec for a read, modify,
restore cycle (called split cycle) •. The memory chassis holds up to twelve boards
of three types: memory control boards (MCB), memory data boards (MOB), and memory
array boards (MAB). MCB's contain control and addreSSing circuits for up to 32K
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of memory. MOB's contain a data register and bit drivers for up to 32K of memory.
In addition, MCB's and MDB's may contain the logic for an optional direct memory
access (DMA) feature, which allows the memory to be used also by external devices
on a priority basis. Two MCB's and two MOB's are installed to permit memory sizes
up to 65K.
Each MAB contains 8K of core storage, along with associated drivers
and sense amplifiers. A chassis contains from one to eight MAB' boards.
3-13. I/O CONTROLLER. The I/O Controller provides communication interface between
the DPS and the peripheral equipment via a possible total of 16 input/output channels. Both control and data circuitry are included in the controller. Input/output
channels are of two types: parallel and serial. Both types are available in either
single or dual channel mode operation. Parallel channels must always exist in complete groups of four adjacent channels~ Serial channels are divided into groups of
two. For dual channel operation with parallel channels, two adjacent groups are
required and the lower group must be even numbered (0 or 2). The channels involved
are nand n+4. Dual channel operation with serial channels uses the pair of channels in a two-channel group. The 16 I/O channels, whether parallel or serial or a
mixture, divide into four groups of four channels for internal addressing purposes
(refer to Table 3-1). The higher numbered channels have the higher priority
(channel 178 highest, channel 0 lowest).
Table 3-1.
GROUP
Parallel I/O Channel Groups
CHANNELS
0
0, 1, 2, 3
1
4, 5, 6, 7
2
10, 11, 12, 13
,3
14, 15, 16, 17
3-14. Parallel channels have three optional interfaces: NTDS Slow (-15V), NTDS
Fast (-3V) , or ANEW (+3.5V). Parallel. channels operate asynchronously, with transfer rates per interface as specified in Table 1-1. Parallel channels will operate
in the intercomputer mode if so specified on order; otherwise they operate in the
normal buffer mode. Serial channels are of three optional types: expanded MIL-STD188' synchronous or asynchronous, RS-232 standard synchronous or asynchronous, or the
NTDS 32-bit asynchronous. Serial channel transfer rates are as specified (synchronous or asynchronous) in Table 1-1. The order of data transfer is from the least
significant bit (0) to the most significant bit (15). Both serial and parallel
channels operate in full duplex mode.
3-15. The I/O Controller receives/transmits data from/to both the DPS source bus
and the peripheral equipment. See figure 3-1, system primary block diagram. The
major circuits of the I/O controller are defined below.
3-16. The Input Data Circuitry receives data from peripherals and determines
whether the peripheral data or data from the I/O Function Control is to be gated to
the source bus. The Req/Ack Control circuitry receives requests (ODR, EFR, IDR, or
EIR)from the peripherals, and acknowledges (ODA, EFA, IDA, EIE) those requests. A
request must be acknowledged before another similar request is allowed in from
3-5
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that channel. The Group/Channel Control Circuitry receives the channei requests
from the Req/Ack Control and establishes channel and function priority. This circuitry also generates a clear request signal and enables an acknowledge signal to
be returned to the peripheral equipment. It generates a group select signal for
the Output Data circuitry. The I/O Function Control circuitry receives information
from the source bus and passes it to the control memory (CM) or decrements the
buffer word counts and increments the address pointers of control memory. The
altered counts and pointers may be sent to either CM or the source bus. Data is
also taken from control memory and sent to the source bus via the Input Data circuitry. The Output Data circuitry obtains data from the DPS via the source bus
and sends the data to the peripheral devices designated by the Group Select signal
from the Group/Channel Control.
3-17. POWER. The power supply converts the ac input power to the various dc
voltages required by the DPS. It is oscillator controlled. It maintains closetolerance regulation of the output voltages and provides filtering to limit line
noise and transients. It checks for under and over-voltage at the input and for
overload at the output. Variations of the power supply permit input power to be
115 Vac or 208 Vac, single phase or three phase, 60 Hz or 400 Hz.
3-18.
FUNCTIONAL BLOCK DIAGRAM DESCRIPTION.
3-19. The following paragraphs provide detailed block diagrams and accompanying
descriptions for each of the major sections of the computer. The diagrams are as
follows: figure 3-2, MPCj figure 3-8, Processor/Emulatorj figure 3-16, Memory
Interface, figure 3-19, Main MemorYj figure 3-29, I/O Controllerj and figure 3-54,
Power Supply and Distribution. The numbers associated with the lower right hand
corner of each symbol on these block diagrams signify the figure numbers of the
logic schematics on which the circuitry may be found. The logic schematics are in
chapter nine (Volume 2) of this manual.
3-20. MICROPROGRAMMED CONTROLLER (MPC). The MPC executes microinstructions to
perform all control operations and data manipulations in the computer. The microinstructions are permanently stored in a read-only memory (ROM). See Appendix A
for a detailed description of the microinstruction repertoire. The two-bus (source
bus and destination bus) structure allows instruction overlapping as shown in figure 3-3. Overlapping increases the microinstruction execution rate to one microinstruction per clock pulse. The S-field within the microinstruction word defines
what register or network is applied to the source bus, and the D-field defines
what register or network is the recipient of data on the destination bus. Figure
3-2 is the 610ck diagram of the MPC. Following is a description of the maj or ele:..' ments:
3-21. Micro Memory. The micro memory contains the unalterable microprogram.
It
is a ROM memory, consisting of four printed circuit cards, each containing 1024 (lK)
l6-bit words. The ROM cards are factory pre-programmedj therefore microprograms
can be cha~ged only by substituting different cards.
3-22. The basic microprogram qonsumes the first 1-1/2Kmicro memory addresses,
physically located on the cards at locations 5B and 4B. The next 1/2K addresses
(30008 to 37778) are reserved for customer-specifiea microprogram routines. Note
that if customer-specified microprograms are added after the computer leaves the
factory, both the micro memory card at location 4B must be replaced, and also the
card at location IOC which must generate ECWs for the new macroinstructions. The
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third card, at location 38, contains addresses 40008 to 57778 and is reserved for
the optional extended mathematics microprogram called Math Pack. An MPC diagnostic
program occupies the fourth card, at location 28, which contains addresses 60008 to
77778·
3-23. The micro memory addresses listed in Table 3-2 are permanently assigned
addresses in the basic microprogram. Those labelled as micro interrupt addresses
are reached through a Normal Start microinstruction (17 00 00 14). This instruction enables a hardwired priority network that checks the micro interrupts and
causes a jump to the proper address if an interrupt is present. If no interrupts
are present, it causes a jump to micro address 2748 and begins the Macro Instruction
Read subroutine.
3-24. The address in the micro P register selects a 16-bit microinstruction word
from the micro memory. The word remains on the micro memory output lines, available to the micro instruction register until the address is changed.
3-25. Micro Memory Control. The Micro Memory Control section consists mainly of
the micro address selector, the micro P register, and the micro P hold register.
3-26. The micro address selector is 12 bits wide. It selects one of four inputs
as shown in table 3-3. The inputs labelled Interrupt Address come from the processor/emulator and from the I/O controller, and transfer the fixed addresses of table
3-2. The microprogram subroutines for emulating macro operation codes 40 through
77 occupy micro memory addresses above 10008 and are selected by bit 15 of the macro
. instruction register which accompanies the nine ECW address bits when selected.
3-27. The l2-bit micro P register holds the address of the next instruction to be
read from the micro memory. A bank selector uses the upper three bits of the
register to select 1/2K (512 word) segments of the memory. The micro P register
normally increments by one each clock pulse to form the next address. Jumping or
branching to a non-consecutive address requires that the new address be loaded into
the register from the source bus via the micro address selector. Since the address
field in branch instructions has only eight bits, the upper four bits of the micro
P register are gated onto the source bus to accompany the branch address.
3-28. The l2-bit micro P hold register stores the beginning address of a series
of microinstructions that are being repeated. The repeat (F = 16) microinstruction
initiates the repeat mode. When the last microinstruction in the series is read
from micro memory, the contents of the micro P hold register are loaded into the
micro P register via the micro address selector to repeat the series again. This
continues until the repeat mode is terminated.
3-29. Micro Function Control. The Micro Function Control section of the MPC
generates timing and control signals for the MPC and for much of the rest of the
DPS. The following paragraphs describe its functional sections.
3-30. The micro instruction register holds the micro instruction that is currently
being executed. Most instructions use a basic instruction format which divides
the register into four 4-bit fields (F, D, S, and M) as shown in figure 3-4. The
F-field specifies the basic function to be performed, such as add, subtract, shift,
transfer, etc. The D-field defines the destination register for the result. The
S-field specifies the source register on which to perform the function; this field
is sometimes called the Origin or O-field. The ~-field modifies the basic function
3-10
Table 3-2.
0000
Master Clear (Auto Start)
0200
I/O Return
0204
Bootstrap Load
0210
Micro
Inter- 1
0310
I/O In Data, Pass
0320
I/O Out Data, Pass> 1
0330
I/O Out Data, Pass
0340
IA Byte Mod
0344
IA Byte Mod
0350
IA Word Mod
0354
IA Word Mod
0360
Norm Byte Mod
0364
Norm Byte Mod
0370
Norm Word Mod
0374
Norm Word Mod
2374
Ill. I/O Instr.
2376
Ill. CP Instr.
27XX
IA Table
1
1
Micro Address Se1ection*
Interrupt Address (Bits 1-7, 10)
ECW Address Pointer (Bits 0-8) plus IRIS
Micro P Hold Register
Source Bus
*See Volume 2, Figures 9-8 to 9-10.
3-11
15
F
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DESTINATION
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Figure 3-4.
, T
REG.S.
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Microinstruction Format
<
in various ways for the different micro instructions. See Appendix A for a description of each micro instruction. The contents of the micro instruction register
direct most of the control functions of the DPS, The contents can be gated to the
source bus and can be displayed on the maintenance panel through the panel selector.
3-31. Three Command Generator ROM's translate micro instruction codes and generate
basic command signals. Two are elements 01 and 02 on the c;:trd at location
lOB and appear on figure 9-38 in Volume 2. These two primarily control the operation of the MPC Arithmetic Section (ALU) and are, therefore, called the ALU control
chips. The Function (F) and Mode (M) fields of the micro instruction word select
the addresses in these ROM's. Tables 3-4 and 3-S show their microcoded contents.
The third ROM is clement 03 on the card at location 7B and appears on
figure 9-21. It decodes the D-field (or F2 - field) on Repeat (F = 16) microinstructions. It, therefore, is called the repeat control chip. Table 3-6 shows its microcoded contents. Additional MPC control Circuits occur throughout the DPS, but
mostly appear on logic figures 21 through 28 (Chapter 9) and are grouped into one
block labelled Control.
3-32. A number of circuits throughout the Micro Control Section are associated
with the D-field of the microinstruction register. The F2 register holds the Dfield on Repeat microinstructions, in which the D-field becomes a secondary function
code. It is decoded by the repeat control command generator ROM described in the
preceding paragraph. The branch control circuits translate the D-field as a secondary function code to determine the branching condition. (See figure 9-2S. Chip U07
is enabled for F2 0-7; U04 is enabled for F2 11-17. Output of disabled chip is held
high. See Appendix A, table A-IO for the branch conditions.) A D-delay register
permits the MPC instruction overlap described in paragraph 3-20 and figure 3-3 by
holding the destination information for one clock period after the microinstruction
register. The contents of the D delay register are compared with the source field
of the current microinstruction. If they are the same, the MPC doesn't stop to
wait until the data has first. been sent to the destination, but simply gates the
destination bus data directly through the X selector to make immediate use of it,
while simultaneously gating it to its destination. Likewise, the D delay register
is compared to the D field of the current microinstruction. If both are deSignating the same address in the accumulator stack, the MPC gates the contents of the
destination bus directly through the accumulator selector. This is necessary,
because most microinstructions use the. D-field for deSignating one of the four
accumulator stack registers (AO - 3) as one of the operand sources, as well as for
designating the destination of the result.
3-33. The 16-bit condition register (CR) defines the status of arithmetic operations as shown in figure 3-S. Status is loaded into the condition register when
specified by a microinstruction with F = 2 through 7 and save status bit set (Mfield bit 3 = 1). Bits 0-7 of the condition register load directly from the destination bus. Bits 8-lS load through the CR selector and may be data from the destination bus or may be arithmetic status bits.
3-34. The 16-bit MPC source selector is the main path for MPC data to be placed on
the source bus. Its output is gated to the bus when one of its inputs is designated by the microinstruction S field. It selects inp~ts as follows:
1)
Selector control bits = 00:
2)
Selector control bits
= 01:
Discrete bits per table 3-7
Panel Selector
3-13
Table 3-4.
Microcode for Command Generator ROM Chip U03
Address
(Octal)
Contents
(Octal)
00
01
02
03
04
05
06
07
10
167
267
377
377
166
166
167
167
166
166
164
164
167
167
167
167
176
176
174
174
177
177
277
277
337
337
357
357
373
371
376
376
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
31
FUNCTION
TRANSFER DESTINATION
TRANSFER DESTINATION
1
2
JUMP
JUMP
ADD SOURCE 2
ADD SOURCE 2
SHIFT
SHIFT
ADD SOURCE 1
ADD SOURCE 1
SUBTRACT
SUBTRACT
LOGIC 1
LOGIC 1
LOGIC 2
LOGIC 2
ADDK
ADD K
SUBTRACT K
SUBTRACT K
TRANSFER K TO
TRANSFER K TO
TRANSFER K TO
TRANSFER K TO
BRANCH
BRANCH
MICRO CONTROL
MICRO CONTROL
REPEAT
REPEAT
EMULATE
EMULATE
BIT SIGNIFICANCE
27
28
25
24
23
22
21
2° I
O~Arith Mod e
O~
1~
O;>Colllplemen t 'Addr OP
F= Repeat (F=16)
F = 01, 10-17
Dl
Dl
D2
D2
O~
O~
Branch (f=14)
0:> Dest 2
0:> Dest 1
Micro Control (F=15)
Table 3-5. . Microcode for Command Generator ROM Chip U06
Address
(Octal)
Contents
(Octal)
00
01
02
03
04
05
06
07
10
177
277
176
276
373
373
373
373
277
277
237
257
174
174
175
175
177
177
137
157
177
177
137
137
167
167
167
167
167
167
167
167
11
12
13
14
15
16
17
20
21
22
23'
24
25
26
27
30
31
32
33
34
35
36
37
c,.)
I
......
c..n
Function
TRANSFER
TRANSFER
TRANSFER
TRANSFER
NORMAL S1 }
NORMAL S2
REVERSE S1
REVERSE S2
JUMP
JUMP
JUMP
JUMP
S2 NORMAL
S2 NORMAL
S2 + 0
S2 -1
SHIFT LEFT
SHIFT LEFT
SHIFT RIGHT
SHIFT RIGHT
ADD S1 NORMAL
ADD S1 NORMAL
ADD S1 +0
ADD S1 -1
SUB NORMAL
SUB\NORMAL
SUB FROM 0
SUB FROM 0
LOGIC 1
LOGIC 1
LOGIC 1
LOGIC 1
LOGIC 2
LOGIC 2
LOGIC 2
LOGIC 2
}
f
=0
f
=1
27
ADD
ADD
ADD
ADD
}
f
2b
24
25
23
21
22
2U
I
0:> ALU SO
=2
O~ALU
p1
O=> BRANCH
f
!
=3
O~Logic
O~Force
f =4
O=> Force ACC
0::> Source
}
}
}
0;>
f
=5
f
=6
f ='7
Source
Sel
ACC to -1
=
0
2
1
(Reference:
Vol. 2, Fig. 9-38)
c..l
I
.....
0-
Table 3-6.
Address
(Octal)
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
Contents
(Octal)
125
234
345
250
374
343
377
377
0
0
121
334
274
363
367
~'
t~5
~37
345
253
377
343
377
377
Microcode for Command Generator ROM Chip U04
Function
MULTIPLY SINGLE
DIVIDE SINGLE
MULTIPLY DOUBLE 2
DIVIDE DOUBLE 2
SQUARE ROOT 2
CORDIC PRESCALE 2
VECTOR 2 AND 3
ROTATE 2 AND 3
(When = 0)
2
7-;ir~5i;4r;3 -;2[;Q-;0-1
p.
1
\ --
.
I
--·-1----- !-"1~~~
----. -.
So
: 1 I i I ; !ALU S 1
MULTIPLY DOUBLE 1
DIVIDE DOUBLE 1
i I I I I I 1 ..• - - - - - - - - - - SQUARE ROOT 1
iii
lSHF SEL_S_O_
CORDIC PRESCALE 2
VECTeR 1
ISHF SELECT Sl
ROTATE 1
MULTIPLY SINGLE LAST
I lHOLD
__
DIVIDE SINGLE LAST
I
MULTIPLY DOUBLE 2 LAST
iTRANSFER
I
DIVIDE DOUBLE 2 LAST
SQUARE ROOT 2 LAST
DIVIDE
PRESCALE 2 LAST
VECTOR 2 AND 3 LAST
MULTIPLY
ROTATE 2 AND 3 LAST
,
I
:
! I
i
I !
i
~_
!
Q
0
121
337
277
363
367
373
BIT SIGNIFICANCE
(Reference:
MULTIPLY DOUBLE 1 LAST
DIVIDE DOUBLE 1 LAST
SQUARE ROOT 1 LAST
PRESCALE 1 LAST
VEC,];OR 1 LAST
ROTATE 1 LAST
Vol. 2, Figo 9-21)
...•\~
Prev.iolls stnLus zero: if all instruetlon
specifics S:j'.'e Stutus, lr;:li\sfer lJi t 13 to
hit. fl before uf.dat.inu lJit 13
Greater thnn:
Status.
the
Carry
Shift
SHVC
~--------
J1rc'Jiou~·
5;)\,C:
----------------.----------
Figure 3-5.
all instruction specifics ~1Jve
the value of hi t. 9 aeconling to
CUlltClIls of hi ts 10 and 11.
if
~elJer(Jtc
carry out of the MSD of the ADDER
---------------
------------------------------~~---------
Condition Register Format
3-17
Table 3-7.
Discrete Bit Inputs to MPC Source Selector
BIT
INPUT
o
Display Number Indicator Switch 0
1
Display Number Indicator Switch 1
2
Display Number Indicator Switch 2
3
Display Number Indicator Switch 3
4
Alter Mode Switch
5
I/O Active Signal
6
General Register Select Indicator Switch
7
Instruction Register Select Indicator Switch
8
Normalize 2° Signal -
9
Normalize 21 Signal
10
Normalize 22 Signal
11
Normalize 23 Signal
12
Normalize 24 Signal
13
Normalize 25 Signal _
14
Not used
15
Not used
Shift Count
3)
Selector control bits
= 10:
Condition Register
4)
Selector control bits
= 11:
Micro P Hold Register (bits 12 to 15
= 0).
3-35. The master clear (also called master reset) circuits generate the master
clear signal from two sources: the MASTER CLEAR switch on the maintenance console,
and the power supply. When in Normal (Run) mode, the only effect of the MASTER
CLEAR switch is to clear the fault indicators. The power supply monitors the +5
Vdc output and generates a master clear Signal if the voltage falls below tolerance.
When powering up, the signal is generated to produce an initial clear until the
+5 Vdc output reaches its normal operating voltage. The master clear signal sets
most of the registers and flip-flops to an initial condition and causes the MPC
to enter the micro program at micro memory address 0000 to begin an Initialize
subroutine, or to enter the diagnostic subroutine if the diagnostic jump switch is
up.
3-18
3-36. Figure 3-6 is a simplified diagram of the master d ",:rJ""', r:tu'j produce a series of 'timing pulses called the phase early (t)e) and } ~h:,,~ ':;.1 ,)'ml (;1n)
pulses, which are used throughout the DPS. Their frequency and If.hu',!cs,i,cm depend on
the selected delay line taps. Figure 3-7 shows the approxim!litft ? ~.i:"'",.r?'i':ltion"hips
of the various elements wi thin the master ClOCK. The Clc,lCk' ~:vc1 11,;~!):dmately
150 nsec. The tle pulse and the f6n pulse each have a diJratio1i1: fif nf!","n:t'rf'Rtely 50
nsee.
1
3-37. Repeat Control. The repeat control section is concf::fl1ed ',r~, ):"1 't"l: Hepe,i t
microinstructions (function code = 16) which require thl!.:
ti i:::;'·(nd.
of
microprogram subroutines. The section consists of a cyc16 G3unte~
~~~r~inst£uction clJunt hold register, an instruction counter, and a COI!'lp:,n."~: Uti:
:; ',;, ';;:fle repeat
microinstructions, the D-field acts as a secondary functi(J:1 ~~(lide
:)
iF;::
F 2 codes 0-7, the S & M fields combined are called the K-neld !nh~ :~,p,~""i.iy the cycle
count, which the MPC loads into the cycle counter. The in~truct.1i);r ~I",fi!,:nt i!; nenerated by hardware. For F2 codes above 7, the cycle counter must be! :~i)~fed hy E
previous instruction, and bi ts 0-3 of the K-field (the M-field) fpe,;;i
the c(.'unt
for the microinstruction count hold register. The count sp~Jcifie:f31 m~.~:S; be one less
than the number of microinstructions to he repeated. '!be repeat mic!LOITlstruction
always sets the microinstruction counter to zero. As each micrD~n~~r0ction In a
seiries is executed, the counter advances by one. When the COI..Ul.tr:Y' ljnd the microinstruction count hold register are equal, the cycle counter is ineremented w the
microinstruction counter is reset to zero, and the address stored !~ the micro P
hold register is loaded into micro P to repeat the series. The series repeats until
terminated by the cycle counter.
\
.I
.t),1l'M e-i NO"" 4:1Reference Volume 2, figure 9-1.
Figure 3-6.
PCAtleS '!
Master Clock Block Diagram
3-19
)
c.. ~ 0 C k. (6i a.f.. 3l.)
tPE. ~'TOP
( Q
cjJ '" ~TO f (Q
02)
1
lPN
S1Jt(r
(q 03)
1
4>e.
rUTrQO'f)
I'
s)
J
QYCI-£.
(QO
r
57)
I
L~~~ (e;.rt~
+5)
1,
,>,),fO;
foe;;
I
14l...
I
[
I
L~ ~ N (,~../~
FI'uP-t..<)
J
j
( r; ~ +.t 4- 7 )
"tLL.
I
I
0')
I
Figure 3-7.
15~ Nt;.-
I
I
I
"'1
I
Master Clock Timing
3-38. l2-bit cycle counter is loaded through the micro P address selector. It
initially receives the complement of the cycle count, and advances by one each
cycle until it fills and generates a terminal count signal. It can also be used
for other functions, with the micro control (F = 15) microinstruction providing
control to advance the counter. The microinstruction counter and microinstruction
count hold register each contain four bits. The count hold register receives its
input from the repeat selector, which transmits the M-field when F2 is greater
than 7, or generates an instruction count when F2 is 0 to 7. The instruction count
comparator compares the count of the counter and the count hold register.
3-39. Arithmetic. The arithmetic section performs most of the arithmetic and logic
functions of the DPS. Arithmetic control is scattered throughout the logic schematics, but mostly appears on figures 9-37 and 9-38. The following paragraphs describe the major elements of the arithmetic section and their functions!
3-40. The arithmetic section contains two scratch pad memory stacks. One is
called the ALU file and contains registers AO through A7. The other is called the
accumulator stack and contains four registers which are duplicates of AO through
A3' When the specified destination of an operand is one of registers AO through
A3. it is stored in both the ALU file and the accumulator stack. Data can be
written into and read from different addresses of the stacks simultaneously. Both
are loaded from the destination bus. Data from the ALU file is placed on the
source bus. Data read from the accumulator stack is gated into 'the accumulator
3-20
register via the accumulator selector. The D-field in most microinstructions,
besides designating the destination for the result, also designates one of the
registers AO through A3 as the accumulator source.
3-41. The accumulator register and X register provide the inputs to the ALU. They,
in turn, receive their inputs from the accumulator selector and the X selector.
The usual source for the accumulator selector is the accumulator stack (AO - A3).
The usual source for the X selector is the source register. Both selectors sometimes use the data from the destination bus, the X selector when S = D and the
accumulator when destination
accumulator, as described in paragraph 3-32.
=
3-42. The heart of the arithmetic section is the arithmetic/logic unit (called the
ALU chips and accompanying carry look-ahead chips are described in paragraphs 3and 33-43. The ALU output passes through the shift selector, which is capable of shifting the result as shown in table 3-8. A shift source selector determines the input
to bit 15 on right shifts and to bit 0 on left shifts. The shift selector handles
the shifting required for most of the complex arithmetic functions, such as divide,
square root, etc. High speed multiply circuits in the processor/emulator perform
the multiply function and a high speed shift matrix performs the shift function.
The ALU output through the shift selector goes to the destination bus. Note that
this is the only input to the destination bus and, therefore, is always on the bus
and is the only data on the bus.
3-44. Display Control. The MPC contains a microprogram subroutine that controls
the control panel display function through the display control circuits. The display subroutine begins at micro memory address 2148. It is entered automatically
whenever the computer is not in the Run mode, and thus permits manual manipulation
of registers whenever the DPS is not performing instructions. Chapter 2 lists the
displayable registers and gives the procedures for displaying and changing them.
The display indicator switches on the maintenance panel constantly display the contents of the l6-bit display register through the display bus. The register to be
displayed is selected by means of the MICRO ADRS, MICRO INSTR, NORM DSPL, GENL DSPL,
INSTR REG, GENL REG, and DSPL NUMBER indicator swi tches (In t.he maintenance panel.
These indicator switches appear on figure 9-24 and 9-55 of the logic schematics in
Volume 2. The microprogram loads the contents of the selected register into the
display register through the panel selector. When the contents of the display
register indicator switches on the panel are manually changed, the microprogram
reads the change from the display bus through the panel selector onto the source
bus· and changes the· contents of the actual register. The gating of the panel
selector is shown below. The micro address selector and the micro P register have
only 12 bits. When the micro P register is gated, the upper four bits are gated as
zero's. When the micro address selector is gated, bits 12 to 15 are added from the
source bus. This permits this path to be used for transferring source bus data to
the display register.
= 00:
1)
Selector control bits
2)
Selector control bits = 01:
3)
Selector control bits
4)
Selector control bits
= 10:
= 11:
Display bus
Micro address
sel~ctor
Microinstruction register
Micro P
regis~er
3-21
3-45. PROCESSOR/EMULATOR. The processor/emulator operates with the program of
macroinstructions. For each instruction, it generates an emulator control word
(ECW) which causes the MPC to enter the proper microprogram subroutine and to issue
the proper control signals for performing the macroinstruction. The processor/
emulator contains general registers, a program status section, and high speed shift
and multiply circuits, all of which augment the general purpose MPC and combine with
it to efficiently perform the tasks required of the Data Processing Set. Figure
3-8 is a detailed block diagram of the processor/emulator. The following paragraphs describe its major sections and subsections.
3-46. Function Control. The function control section translates the macroinstructions and generates control signals that function together with the MPC and its
microprogram to control the DPS. It consists of the instruction register (IR), the
ECW stack, the emulate control circuits, and the IR selector.
3-47. The l6-bit instruction register holds the macroinstruction that is currently
being executed. It receives the instruction from main memory via the memory interface section and the source bus. (See Chapter 2 and Appendix B for descriptions of
the macroinstructions and the instruction word formats.) A comparator circuit monitors the A and M fields and, when equal, generates a signal used for the F = 14,
F2 12 Branch microinstruction.
=
3-48. The emulator control word stack is a ROM containing 256 l6-bit words. The
upper eight bits of the macroinstruction word (six-bit operation code and two-bit
format code) address it. At each address, it contains an emulator control word
(ECW) peculiar to that instruction. The last portion of the microprogram listing
in Appendix C is a listing of the ECW stack contents. Figure 3-9 shows the ECW
format. The lower nine bits of each ECW wocd are called the address pointer and
are sent to the MPC as the starting address of a microprogram subroutine. Bits 1
through 4 of the address pointer can be modified by the macroinstruction m-field
(IRO-3) through four gates appearing on figure 9-66. The unary macroinstructions
use the m-field as a secondary operation cod~. Modifying the address pointer
permits starting at different microprogram addresses for each code. ECW bits 9
through 12 are called the Unary, Overlap, Interim and Modify pointers, respectively.
The Unary pointer, when both it and the Modify bit are zero, signifies a Unary
.macroinstruction, and one of its functions is to enable the ECW address pointer to
be modified by the m-field. When the Modify pointer is one, the primary purpose
of the Unary pointer is to enable or inhibit the next instruction write function.
The Overlap pointer, when equal to one, permits overlap of macroinstructions. It
enables the next macroinstruction to be read from main memory early, without waiting for completion of the microprogram subroutine, and enables the setting of a
next instruction resident (NIR) control bit, which signifies that the next macroinstruction is already available. The Interim pointer is coded into the ECW word
for RK and RX format macroinstructions. These are double length instructions and
require an interim memory reference to obtain the second half of the instruction
word. The Modify painter, when zero, combines with the Unary pointer to enable
the address pointer to be modified by the m-field. When equal to one, it signifies
the RI and RX format macroinstructions, which require an additional memory reference
to fetch or store an operand. The upper three bits of the ECW word are the Memory
Mode pointers and are interpreted as shown in figure 3-9. Note that bit 13 is the
Read/Write bit, signifying read mode when zero and write mode when equal to one.
On I/O sequences, memory mode pointer bits are generated according to IOC conditions
and the ECW memory mode pointers are disabled.
3-22
OES TIN A-T 10 N
To
HI(R()
ADO(~S'S
r - - - -- -- I
I
l
I
I
5fL
f-
-1 r - -- - - - - - - I
.DP~EsS
iff,. ~3
i
EHUL.A-Tf
CONTR~
;~
r
,
t
I
I.
I
I
GENf"((AL RE4
I
•
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i
I
(S6R SEL )
•I
EM 1.4 '-ATE
G
I
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.ss
_ _ _ -lI
~NT.'T
Co~~~~~
It
H'NITo~
C I-"k..
lJr,2lt
I
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esc
"
I
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72,70
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•
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f--
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I
ofF lAIM
INSTf
L ___ _
~~
"-'9
J
I
:~,
------.,
S1
$t.n
~
5"&• .59
5"' 57
TI
/
1 'If
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\~,
(11\ SEL )
ION
4)'."
.
)
.03, 'D~
,I
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99. 100
RT 0,.,8/ '1)
S tfl= HitTR. , x I ({AN I(
~
99,100
I
~
F"u NeT
($IIF
I
~
,It
_(SEL
:~
I
SHF H~TR.IXJ I(ANK I
,II
NORM
PARTIAL
(..ONTI(OL
P((ODcltT
.02.'DS
+lJ'DJ, •
I
•I
I
(SEL, UPpEfl)
I
II/
,II
~
L __
I
,11
(SEL lD..,ec)
I
I
~'l.1F') CRz)
J,
,II
1
n
II
~--.---.----.--~--------.
I
ST
I
Hu,-,'pI..Y
AND
039.
93.94
I
I
#-ItcH Sf'fEED SHIFT
Rz
I
ft n:
RT c..
U
,Ps-..A11t.S STA'f'IU &.OW'
,,-
11\', •
ROM)
70
I
S ...
I
(.ON1'"«OLw. aD S'.,.~ct
,
84 M Rf cl/JiE fJS
1.·1'\
L _ ~ __ . "'"
~ _ _ _ _
R.
--...,, r - - - - - - - - - ---,
c: EftE((AL
SC;R
•
•
•
'2-' 5 7D
i
, if
11\
til c.~o
(e,...,
r---------- \11 ---- -----------,,
H p<:
J"
I
e us
I
I
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:
I
SUF HIrr«.'"
39,40
I
I
:
,1/8.13 0-3
c..ONT"ltOL-
HPY
, I
CONT~OL
4' ,42
I
CONTRoL..
(i
I
- - - - - - - - - - - - --:......&
L __ _
"-"
~It
Sou(ce
BUS'
Figure 3-8.
Proces.sor/Emulator Functional Block Diagram
3-23/(3-24 blank)
Table 3-8.
ALU Shift Selector Functions
FUNCTION
SELECTOR OONTROL BITS
No Shift
Byte Shift (8 Places Circular)
Shift Right One Place
Shift Left One Place
00
01
10
11
MODIFY
INTERIH
OVERLAP
UNARY
15 \14 \13
J I I
10
9
8
M
I
0
U
Emulation Pointer Address
-
6
5
I 3 I 2[ 1 l 0 I
11
0000
0001
0010
'0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
7
f 4
12
RR Unary; modify ECW pointer by mj no overlap
RR; no overlap
RR Unary; modify ECW pointer by m; overlap
RR; overlap
RK Unary; modify ECW pointer by m; no overlap
RK; no overlap
RK Unary; modify Eel? pointer by m; overlap
RK; overlap
RI; Inhibit next instruction "Trite
RI; Enable next instruction write
RI; Branch direct from Branch 1
RI; Branch direct from Branch 1
RX; Inhibit next instruction write
RX; Enable next instruc.tion "Trite
RX; Inhibit indexing; inhibit next instruction write
RX; Inhibit indexing; enable next instruction write
Memory Mode
000
001
010
011
100
101
110
111
Read word
Write word
Read odd word
Write odd word
Read split cycle
Write zeros
Read byte
-Write byte
-
Figure 3-9.
...
Emulator Control Word (ECW) Format
3-25
3-49. The emulate control circuits provide the hardwired control logic that functions together with the MPC and its microprogram to control the operation of the
DPS. Emulate control circuits are scattered throUghout the logic schematics but
are mainly found on figures 9-62 through 9-65. For help in understanding these
cO,ntrol circuits, refer to the functional operation description starting at paragraph 3- • Micro address generator circuits located on figure 9-63 generate the
addresses of fixed microprogram subroutines (see table 3-2). These addresses are
generally called interrupt addresses and interim addresses. They are placed on a
common bus with similar addresses from the IOC (figure 9-201) and are sent to the
micro address selector in the MPC.
3-50. The IR selector, when its output gates are enabled, places one of four inputs
onto the source bus as follows:
IR (Instruction Reg)
Selector control bits
= 00:
= 01:
3)
Selector control bits
= 10:
CORDIC table from NDRO
4)
Selector control bits
= 11:
General Register
1)
Selector control bits
2)
IR lower byte, sign extended
3-51. General Registers. The general register section contains the general registers, the SGR, and the SGR selector. A general register stack consists of sixteen
l6-bit registers. For the optional second set of general registers, a type 5520 card
is used at location 12C instead of the type 5510. The second set is enabled when
bi t 14 of status registe,r :ttl is set. When a register is enabled and is addressed by
the SGR register, it becomes active; that is~ its contents appear on the stack output lines, and it is capable of being loaded. The general registers receive data
directly from the destination bus; their output is placed on the source bus via
the IR selector.
3-52. The 4-bit SGR register holds the general register address. It can be incremented by one each clock pulse. The 4-bit SGR selector selects one of four inputs
to load into the SGR register as follows:
3)
Se1ect'or control bits
= 00:
= 01:
= 10:
IR M-fie1d with lower bit clear
4)
Selector control bits = 11:
Lower four bits from source bus
1)
Selector control bits
2)
Selector control bits
IR A-field
IR A-field with lower bit clear
3-53. Program Status Section. The program status section contains two status
registers, the real time clock and monitor clock, the PSW selector, and,the inter!
rupt control circuits.
3-54. Status register :ttl and status register :tt2 are l6-bit registers for storing
program status information. Exc'ept for several bits, their setting and clearing
is a program responsibility. They can be set and cleared using the unary control
macroinstruction (Op Code 03). They receive their input from the destination bus.
Figure 3-10 shows the significance of the bits in status register :ttl. Bits 1-3,
when set, permit the honoring of interrupts of their aSSigned class; when cleared,
they prevent the honoring of interrupts of their class. Bit 4 is used with the DMA
3-26
15
14
13
12
11
10
91 8
7
I6Is
4
3
12 I
1
o
I
,/
0 = DMA locked out
1 -- DMA enabled
Interrupt lockout designators:
bi t 1 -- Class III
bit 2 -- Class II
bi t 3 -- Class I
A bit cleared means the interrupts in that class are locked
out.
Not used
Not used·
Condition code designator; the condition of these
bits specifies the result of arithmetic and compare
instructions as shown in table 3-9.
Overflow designator; this bit sets when an arithmetic
or shift operation produces a result which requires
more bits than provided in the register.
Carry designator; this bit sets when an arithmetic
operation generates a carry out of the most
significant bit in the register.
NDRO Mode: The condition of this bit shall select
access to NDRD memory.
Bit 12
Bit 12
= 0,
= 1,
selects NDRO for addresses 00-77 and 300-477
selects main memory for addresses 00-77 and 300-477
Not used
o = General
1
= General
Register set 0 (standard set)
Register set 1 (optional set)
Not used
Figure 3-10.
Status Register
~1
Format
3-27
(direct memory access) option; when cleared it disables the DMA port to prevent the
external device from gaining access to the main memory. Bits 5-7 are unassigned.
Bits 8 and 9 (condition code designators), bit 10 (overflow designator), and bit 11
(carry designator) are capable of being set and cleared automatically as a result
of arithmetic operations. See Table 3-9 for the significance of the condition code
designators. Bit 12, when cleared, permits referencing the NDRO memory. Bit 14
selects the general register stack to be used. Bits 13 and 15 are unassigned.
Figure 3-11 shows the significance assigned to the bits of status register 11:2.
Bits 0-3 are unassigned. Bits 4-7 are assigned to the memory resume error, and
show which lK (1024 word) stack of main memory failed to respond. Bits 8-15 control the use of four general registers for direct or indirect addressing.
3-55. The real-time clock (RTC) register is a 32-bit register divided into two
l6-bit registers designated RTC Upper and RTC Lower. It operates in conjunction
with an internal oscillator or an external clock ~ignal. The register can be
loaded and its incrementing can be enabled and disabled under program control by
means of the unary control macroinstruction (Op Code 03). It receives its input
from the destination bus. When enabled, the register increments by one at each
pulse from the oscillator, and generates the RTC overflow interrupt if the contents of RTC Lower change from all ones to all zeros (i.e., reach its maximum
count). The internal RTC oscillator frequency is 1000 Hz. The external clock
frequency can be from 0 to 50 KHz; its interface voltage must be Ov to -3v.
Table 3-9.
Condition Code Designator Functions
FUNCTION
CONDITION CODE
,
Arithmetic Operation
Compare Operation
0
Zero
Equal
8
1
Not zero
Not equal
9
0
Positive
R ~
a
R
or Y
9
1
Negative
R <
a
R
or Y
Bit
Value
8
m
m
COMBINED VALUE
Bit 9
-
Bit 8
0
0
Zero
R
0
1
Not zero and positive
RA> Rm or Y
1
0
Not used
Not useo
1
1
Not zero and negative
R < R or Y
a
m
3-28
a
= Rm or
y
Isl/~
I~
/31
II
1 /D
't
Ie
7
I, I ~- I ~ I 3 I z I II () I
C.L4~ S I
I
meL!lQ~~ ~~(,),..,f; ~~~
l>
M M.
tr\
I
0
r LLE(;A '- ~L()
c.LASS.J[
D
IN ~TRvc:T fO IJ
CHAI~
C.
-.
c... c..
e
O. X
I
0
0
Comft'A- N :Q
-
0
0
-0 .0
INblR6c.-T Col\rneoL
"I. ~b\Rk.c." cp,vTftoL. BITS foR..
Fo~
,
~=IO
f~
Blrs
I
,!f\.)tl\~'T C/)t-->T~L 81r~
D
.0
R.".:. 12...
«..tv\ :::. J~
rNT~I2P~-ETA'rIQ_"'"
M
6co 00
I -
~ WriJJfl",,( S i~c. ~ ,
01 I -
IYlWwl~r
100 -
'$T~ ~
o , 0 - IV\'MDft. It( SiM=k-,
, 0
I -
m£/l1lj!'t ~~ _~ __
hI~otr ~1ttd:
(fIWtt(JQ.'r
/10 - /t1611a?(S"(Nt. 7
1/1 - ~l~V S~ ~
5"
ST"Ai,t (,
C. :t:.AJT"€.I2_pgE. rA-TIt>N
~
c:,.. "",c-
-
CHANfJGL N()tr,B!.1<...
0 - Ili
-
X ~f'JT6~jacTA-1i()AJ
X .:0: J:NPvr
I...
=- I:
OuTP.!)'
-
1-" j.JDI~T
-
ctlA~tJ€t-
c.HANtJ~'-
.-
-
.
-
CDNTJtoL Brr l=IJT€.?fRe174,/(),J
4PD~E.S SING,..
Df) -
No{eJfl.t4 '-
0, -
NOR..M.ltl- ADDt.E.SSJ{u~
10 "
-
'tNt>\~T AbDeEs~JNG- (wot.b ~T- V)
l=NDI e.c.c.r Ah)~S/tJG. w/1"1I ~1>~flJ~_
Figure 3-11.
-
~D~1) itT
Y-+
~h\)
Status Register #2 Format
3-29
3-56. The monitor clock register (also called interrupt clock register) is mainly
used for monitoring the response time of peripheral devices for the IOC. It may
be loaded and enabled by the Unary macroinstruction (Op Code 03). It is loaded
from the IOC output data register, and decrements at the same frequency (internal
or external) as selected for the RIC register. When operated on the internal
clock (1000 Hz) the value of the least significant bit (LSB) is one msec, and a
full l6-bit value is 65.536 seconds. When the contents of the register reaches
zero, the Monitor Clock interrupt is generated.
3-57. The program status word (PSW) selector selects an output to gate onto the
source bus as follows:
1)
Selector control bits
2)
Selector control bits
3)
Selector control bits
4)
Selector control bits
= 00:
= 01:
= 10:
= 11:
RTC upper
Status register #1
Status register #2
RIC lower
3-58. The interrupt control circuits initiate the processing of an interrupt and
cause the micro address generator (para 3-49) to send the MPC the starting address
of a microprogram subroutine for handling the interrupt (see table 3-2). Interrupts are divided into three classes with decreasing priority as follows: Class I,
class II, and class III. Interrupts within a class are also assigned priority
as shown in Table 3-10. The code assigned to the honored interrupt is placed onto
the source bus through the I/O selector, figures 9-222 through 9-225. When an
interrupt is honored, its class and all classes of a lower priority are locked out
until released by the processor macroprogram. A higher priority class will interrupt a lower priority class unless it has been locked out by the program. An
interrupt class (except power fault interrupt and CP instruction fault interrupt)
can be enabled or locked out by the associated interrupt lockout designator in status
register #1 (figure 3-10). The programmer, therefore, has complete control over the
processing of interrupts. The power up master clear (initial master clear) clears
the lockout bits in the status register, thus disabling most interrupts until the
program is ready to handle them. The program, when ready, must execute a Load
Status Reg #1 macroinstruction (Op Code 03, n = 5) to enable them. Processing of
an interrupt consists of storing pertinent data to allow resuming normal macroprogram
operation from point of interruption and then transferring control to a macroprogram
subroutine to process the interrupt. Eight main memory references are required
before trans'ferring control to the interrupt subroutine. AddreSSing for the eight
memory references is shown in figure 3-12. These eight addresses are not loaded
into the P register but directly into the memory address register (MAR). When the
eight memory references ia're completed, the contents of the P register, which now
contains the address of the first instruction of the interrupt subroutine, are
loaded into .MAR to start executing the interrupt subroutine. Following is a step-bystep description of the interrupt process.
1. Terminate the current program sequence and lockout all interrupts during
steps 2 through 5.
2. Store the contents of the P register, status registers #1 and #2, and the
lower RTC register at assigned main memory addresses (figure 3-12).
3-30
Table 3-10.
CLASS
PRIORITY
WITHIN
CLASS
Interrupt Priority
INTERRUPT
UITERRUPT
CODE
(BINARY)
CLASS I
1
POWER FAULT - Generated by an out of tolerance
voltage condition. (No lockout)
000
Hardware
Errors
2*
MEMORY RESUME - Generated when the main memory
fails to acknowledge a request within 12 usee.
001
CLASS I!
1*
CP INSTRUCTION FAULT - Generated when the
processor attempts to execute an instruction
with an unused operation code, an operation
code 00, or an operation code 7X. (No lockout)
000
2*
IOC INSTRUCTION FAULT - Generated when the
IOC attempts to execute an instruction with
an unused operation code or any operation
code other than 7X.
001
3
Unassigned
010
4*
EXECUTIVE RETURN - Generated when the computer
executes the OJ RR, m = a instruction.
011
5
RTC OVERFLOW - Generated when the contents of
the RTC lower register (bits 0-15) increments
from all ones to ail zeros.
100
6
MONITOR CLOCK - Generated when the contents
of the monitor clock register equals zero.
101
1
INTERCOMPUTER (IC) TIME OUT - Generated in
the transmitting computer when the receiving
computer fails to accept a data word from the
transmitting computer and return a resume
signal within the allotted time.
11
2
EXTERNAL INTERRUPT - Generated when the computer has stored an external interrupt word
or, if serial interface (except NTDS), generated for a discrete interrupt.
00
3
OUTPUT CHAIN (Output Monitor Interrupt) Generated when the IOC executes the 73 RR,
a = 1 (Chain Interrupt) instruction from an
output chain.
10
4
INPUT CHAIN (Input Monitor Interrupt) - Generated when the IOC executes the 73 RR, a = 1
(Chain Interrupt) instruction from an input
chain.
01
Program
Interrupts
CLASS II!
I/O
Interrupts
*
If the class lockout is set when this condition is generated, the DPS will
stop at completion of the macroinstruction currently being executed.
3-.'31
15
~
,.
9
8
f
7
I6
5
I4t3
21 1
10 1
000 = STOr.AGE FOR P
001 = STORAGE FOR STATUS III
010 = STORAGE FOR STATUS #2
011 = STORAGE FOR RTC LOWER
100 = LOAD P
101
110
= LOAD
= LOAD
STATUS III
STATUS #2
111 = STORAGE FOR RTC UPPFR
001
010
011
= CLASS
= CLASS
= CLASS
III INTERRUPT
II H1TERRUPT
I INTERRUPT
001
ALL ZEROS
--
Figure 3-12.
3-32
Interrupt Addressing
- .
,l,
,.
3. Load the P register with the interrupt entrance address. For class I and II
interrupts, the entrance address is the sum of the contents of the Load P address
from main memory and the index shown in figure 3-13. For class III interrupts, the
index shown in figure 3-14 is added to the contents of the Load P address to form the
entrance address,
4. Load status registers Ul and u2 with the contents of the assigned memory
addresses.
5.
Store the contents of the upper RTC register at its assigned memory address.
6.
Enable honoring of any interrupts not locked out.
7.
Execute the instruction at the interrupt entrance address.
3-59. High Speed Shift and Multiply Section. This section is dedicated to performing the shift and multiply functions for the DPS, including the functions of
the Unary Shift macroinstruction (Op Code 04, RR). It performs these functions
faster than possible in the arithmetic circuits of the MPC. A description of its
main subsections follows.
3-60. Rl and R2 are also called shift register upper and shift register lower,
respectively. They are the input registers for the high speed shift and multiply
section. They receive their data directly from the destination bus. They have
the capability of shifting their contents left or right one place when needed for
arithmetic operations. The upper and lower selectors determine the nature of the
input into their portion of the shift matrix, as required for circular, sign-fill,
or zero-fill shifts. A ROM chip in the shift matrix control circuits (09, figure
9-39) is addressed according to the shift count and type of operation, and issues
the signals to control each selector. Table 3-11 shows the contents of this chip.
Both selectors operate as follows;
1)
Selector control bits = 00:
2)
Selector control bits
3)
Selector control bits
4)
Selector control bits
= 01:
= 10:
= 11:
Insert zeros into matrix
Insert sign into matrix
Insert R2 into matrix
Insert R1 into matrix
3-61. The shift matrix has two ranks. Rank 1 shifts the data to the right 0, 4,
8, or 12 places; rank 2 shifts right 0, 1, 2, or 3 places. The two ranks together
can shift any number of places from 0 to 15. They accomplish left shifts by shifting the complementary number of places right. A ROM chip in the shift matrix
control circuits (24, figure 9-40) is addressed according to the type of shift
and the shift count, and issues the. signals to control each rank. Table 3-12 shows
the contents of this chip. The output of the shift matrix is placed onto the source
bus through gates appearing on figures 9-33 through 9-36. When performing the
optional CORDIC functions, the count in the shift counter of the shift control circuits forms an address for referencing the CORDIe table in NDRO memory.
3-62. The fast shift and multiply section performs multiplication two bits dt a
time under the control of a multiply subroutine in the microprogram. Basically,
the operations involved in the multiply are as follows:
1)
Multiplier~
R2 reg; clear partial product reg.
15 •
~
4
3
I 2 I1
o
I
0
VALUE OF THE INTERRUPT CODE AS
SPECIFIED IN TABLE 3-10
ALL ZEROS
Figure 3-13.
Class I and II Interrupt Entrance Address Index
15 E
~
-
7
6 E:
..
~
3
2
I1
o
t
0
VALUE OF THE HITERRUPT CODE AS
SPECIFIED IN TABLE 3-10
I/O CHANNEL NUMBER
ALL ZEROS
Figure 3-14.
3-34
Class III Interrupt Entrance Address Index
Table 3-11.
PROGRAM
ADDRESS
(OCTAL)
CHIP
ADDRESS
(DECIMAL)
000
001
002
003
004
005
006
007
010
011
012
013
014
015
016
017
020
021
022
023
024
025
026
027
030
031
032
033
034
035
036
037
040
041
042
043
044
045
046
047
050
051
052
053
054
055
056
057
a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46.
47
Microcode for Shift Control ROM 09
CHIP
DATA
1110
1111
1011
1010
1110
1111
1011
1010
1011
1010
1110
1111
1011
1010
1110
1111
0000
0000
0000
0000
0000
0000
1000
1010
0000
0000
0000
0000
1000
1010
1110
1111
l1ll
1111
1111
1111
1111
1111
1111
:_111
0000
0000
0000
0000
0000
0000
1100
1111
PROGRAM
ADDRESS
(OCTAL)
060
061
062
063
064
065
066
067
070
071
072
073
074
075
076
on
100
101
102
103
104
~05
106
107
110
111
112
113
114
115
116
117
120
121
122
123
124
125
126
127
130
131
132
133
134
135
136
137
CHIP
ADDRESS
(DECIMAL)
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
n
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Q3
94
95
CHIP
DATA
1010
1010
1010
1n10
0110
0101
0101
0101
1111
1111
1111
1111
1111
1111
0111
0101
0000
0000
0000
0000
0011
0011
1110
1110
0000
0000
0000
0000
0000
0000
0011
0011
0101
0101
0101
0101
0111
0111
1110
1110
0101
0101
0101
0101
0101
0101
011.1
0111
3-35
Table 3-11.
!PROGRAM
iADDRESS
(OCTAL)
140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161
162
163
164
165
166
167
170
171
172
173
174
175
176
177
200
201
202
203
204
205
206
207
210
211
212
213
214
215
216
217
3-36
CHIP
ADDRESS
(DECIMAL)
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Microcode for Shift Control ROM 09 (Cont)
CHIP
DATA
PROGRAM
ADDRESS
(OCTAL)
CHIP
ADDRESS
(DECIMAL)
CHIP
DATA
1011
1011
1110
1110
1011
1011
1110
1110
1110
1110
1011
1011
1110
1110
1011
1011
1111
1111
lll1
1111
1111
1111
1111
1111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0011
OOll
1110
lll0
1000
0000
0000
0000
0000
0000
0011
0011
ll10
220
221
222
223
224
225
226
227
230
231
232
233
234
235
236
237
240
241
242
243
244
245
246
247
250
251
252
253
254
255
256
257
260
261
262
263
264
265
266
267
270
271
272
273
274
275
276
277
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
0101
0101
0101
0111
0111
1110
1110
1000
0101
0101
0101
0101
0101
0111
0111
1110
0111
0111
0111
0111
0111
0111
0111
0111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Table 3-11.
Microcode for Shift Control ROM 09 (Cant)
PROGRAM
ADDRESS
(OCTAL)
CHIP
ADDRESS
(DECIMAL)
CHIP
DATA
300
301
302
303
304
305
306
307
310
3ll
312
313
314
315
316
317
320
321
322
323
324
325
326
327
330
331
332
333
334
335
336
337
340
341
342
343
344
345
346
347
350
351
352
353
354
355
356
357
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
2ll
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
0111
0111
Olll
Olll
01ll
01ll
01ll
0111
0101
0101
0101
0101
0101
0101
0110
OllO
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1110
1110
0000
0000
0000
0000
1000
0010
01ll
0111
0000
0000
1000
1110
1110
0011
..-
PROGRAM
ADDRESS
(OCTAL)
CHIP
ADDRESS
(DECIMAL)
CHIP
DATA
360
361
362
363
364
365
366
367
370
371
372
373
374
375
376
377
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
3-37
Table 3-12.
PROGRAM
ADDRESS
(OCTAL)
CHIP
ADDRESS
(DECIMAL)
400
401
402
403
404
405
406
407
410
411
412
413
414
415
416
417
420
421
422
423
424
425
426
427
430
431
432
433
434
435
436
437
440
441
442
443
444
445
446
4,47
450
451
452
453
454
455
456
457
0
1
2
3
4
5
6
7
8
9
10
11
12
3-38
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Microcode for Shift Control ROM 24
CHIP
DATA
PR(x;RAM
ADDRESS
(OCTAL)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
0000
460
461
462
463
464
465
466
467
470
471
472
473
474
475
476
477
500
501
502
503
504
505
506
507
510
511
512
513
514
515
516
517
520
521
522
523
524
525
526
527
530
531
532
533
534
535
536
537
CHIP
ADDRESS
(DECIMAL)
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
CHIP
DATA
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
oorm
0000
0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Table 3-12.
PROGRAM
ADDRESS
(OCTAL)
Microcode for Shift Control ROM 24 (ContI
.._,
CdLP
CHIP
PROGRAM
ADDRESS
ADDRESS
ADDRESS
CHIP
(OCTAL)
(DECIMAL)
DATA
(DEC. Il-lALl
.-.~"-~--
540
541
542
543
544
545
546
547
550
551
552
553
554
555
556
557
560
561
562
563
564
565
566
567
570
571
572
573
574
575
576
577
600
601
602
603
604
605
606
607
610
611
612
613
614
615
616
617
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
1111
0011
0100
0110
1011
0011
1011
1001
1010
1110
0000
0000
0000
0000
0000
0000
0000
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
620
621
622
623
624
625
626
627
630
631
632
633
634
635
636
637
640
641
642
643
644
645
646
647
650
651
652
653
654
655
656
657
660
661
662
663
664
665
666
667
670
671
672
673
674
675
676
677
.
------
--
I-
,,--.,
...,.~"~ ...
ChIP
"i,'" --,
-
1!i " I ' l ( j " ' 1
~
1 ' c : \ ( \ , r)
~_J·i'·.)
~
'i:.~_""
I
146
.
G~]l
I
l!f 7
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
OlOO
u1'Ol
J1._:"0
0111
1000
1001
1010
1:J11
1100
1101
lll0
1111
0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
3-39
~
Table 3-12.
Microcode for Shift Control ROM 24 (Cont)
PROGRAM
ADDRESS
(OCTAL)
CHIP
ADDRESS
(DECIMAL)
CHIP
DATA
700
701
702
703
704
705
706
707
710
711
712
713
714
715
716
717
720
721
722
723
724
725
726
727
730
731
732
733
734
735
736
737
740
741
742
743
744
745
746
747
750
751
752
753
754
755
756
757
192
193
194
195
196
197
198
199 '
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
0100
1000
1100
0000
0100
1000
1100
0000
0100
1000
1100
0000
0100
1000
1100
0000
1100
1000
0100
0000
1100
1000
0100
0000
1100
1000
0100
0000
1100
1000
0100
0000
1011
0111
0011
1111
1011
0111
0011
1111
1011
0111
0011
1111
1011
0111
0011
1111
3-40
PROGRAM
ADDRESS
(OCTAL)
C}llP
ADDRESS
(DECIMAL)
760
761
762
763
764
765
766
767
770
771
772
773
774
775
776
777
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
CHIP
DATA
0100
1000
1100
0000
0100
1000
llOO
0000
0100
1000
1100
0000
0100
1000
1100
0000
2)
R2 (multiplier)
3)
Set cycle counter
4)
Initiate Repeat.
feed reg.; multiplicand
~
=6
~
R2 reg.
(to repeat 7 cycles).
5) Cycle 7 times (see figure 3-15). Each cycle looks at ~he :nw~r ~lts ~ll ~he
feed register (multiplier) and controls the adder and the insertj0t 0; t:IC
regis tel' (multiplicand) into the adder as indicated in table 3-.1: 1,. ij}~ ,:;;;:;\1 :~ycle.
th8 adder output is shifted right two places into the partial pr()dJ:;i(r·.'J:i.~;1>,:!j ::md
the two rightmost (least significant) bits are shifted into th~ m03t si0nlficant
bit pOSitions of the feed register. The feed register also 3hifts tl,1l0 pl"Jees right
so the following cycle can look at the next bits of the multiplier. When the seven
cycles are completed. the least significant half of the produ«.:tl" in the; feed
register. and the most significant half is in the partial produe t re~p.;; U~r.
6)
Store least significant half of product.
7)
Store most significant half of product.
8)
Set condition code.
3-63. 26, 27, and 30 of the multiply control circuits (figure 9-42) provide the
signals to control the inputs and functions of the multiply adder. The high speed
mul tiply uses the So = 1 and 51 = 1 selections. The 5150 = 00 selection is used
for normalize (scale) and other arithmetic functions, if performed in this section.
A ROM chip (22, figure 9-42), addressed according to the type of shift and the
instruction count, issues other control signals. Table 3-14 shows the addressing
and the contents of this chip.
3-64. For the Scale Factor macroinstruction (04 RR, m = 3), normalize circuits
determine the pOSition of the first significant bit in a word, develop a shift
count, and cause the word to be shifted accordingly. The word is placed into the
R2 register and sensed at the output of the multiply adder. The normalize detectors sense zeros; therefore, if the word is positive it is complemented by the
multiply adder. The most significant 16 bits of double length words are checked
first, then the least significant 16 bits. Circuits appearing on figure 9-41
generate the shift count. Double length words require two passes. A flip-flop
stores whether or not a significant bit was detected in the first pass, and a 4-bit
register holds the shift count, if any, generated on the first pass. Bit 4 of the
generated shift count is low (active) only if normalization occurs on the second
pass (second half of the double length word). Bit 5 goes low (active) only if no
significant bit is detected in either pass, and produces a count of 1000000 2 , The
shift count is placed onto the source bus through the MPC source selector. The
count generated is one count high, so it is decremented by the microprogram. It
is then placed into the shift counter and the word is shifted left that many places
by the shift matrix to produce the normalized word.
3-65. MEMORY INTERFACE. Figure 3-16 is
section. The memory interface transfers
divides into four main sections: memory
memory control, and NDRO. The following
their subsections.
a block diagram of the memory interface
data to and f~om the main memory. It
address control, memory data interface,
paragraphs describe these sections ~nd
3-41
150 ns
I
I
~
Clock
H=.> Set RPT Active (MPY Control Sel SO, Fig. 9-42)
7 Cycles
Figure 3-15.
Table 3-13.
H:;> RPT Active Delayed (MPY
Control Sel 51, Fig. 9-42)
Multiply Timing
Adder Functions, High Speed Multiply
Feed Reg
3210
-
Set RPT
Active (SO)
= 1
(Initiate
Repeat)
RPT Active
Delayed (51)
= 1
(7 repeated
cycles)
{XX 00
XX 0 1
XX1 0
X XII
Add Zeros
Add Hultiplicand
Subtract 2X Multiplicand
Subtract Multiplicand
""-00 o X
o0 1 X
o lOX
o1 1 X
1 0 0 X
1 0 1 X
1 lOX
1 1 1 X
Add·Zeros
Add Multiplicand
Add Multiplicand
Add 2X Multiplicand
Subtract 2X Multiplicand
Subtract Multiplicand
Subtract Multiplicand
Subtract Zeros
(See U7, Ull, and UlS, figure 9-42)
3-42
Table 3-14.
PROGRAH ADDRESS
CHIP ADDRESS
o 000 0
00001
o 0 010
o0 0 1 1
00100
00101
00110
00111
o 1 000
o 1 001
o 1 010
o 1 011
01100
01101
01110
o1
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1 1 1
1 0 000
10001
1 001 0
10011
10100
1 010 1
10110
1 0 1 1 1
11000
1 1 001
1 101 0
1 101 1
1 1 1 0 0
1 1 101
1 1 1 1 0
20
21
22
23
24
25
26
27
28
29
30
1 1 111
IALU
Microcode for Multiply Control ROM 22
31
MICROCODE
o 1 1 1 1 111
01111 1 1 1
111 1 1 111
1 0 1 1 1 111
10111 000
111 1 1 0 0 0
o 000 0 0 0 0
0000000 0
10111 1 1 1
1 1 1 1 1 111
101 1 1 1 1 1
1 1 1 1 1 111
1 1 I I I 000
10111 000
000 0 0 000
000 0 a 0 a a
1 1 III 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 000
1 1 1 1 1 000
aa0 0 aaa0
a0 0 0 0 0 0 0
aa
o0
0 0 0
0 0 0
1 1 1 1 0
1 1 1 1 0
110 0 1
10101
o0 0 0 0
oaa0 a
o0 0 0 0
000 0 0
a
I0 ~
o~
Sign
20 Instr Count
1
o
21 Instr Count
~
I0
Repeat 21
RPT Active Delayed ~
RPT 20 )
O~
Sw Shf Matrix Input
~"'Step
Bus 2 0
~ Source Bus 21
o ~ CampI.
~
Incr Shf Counter
Toggle Shf Matrix Sign
o ~ Source
Repeat 2 0
CReadcut Enable
0 0
0 0 0
III
1 1 1
1 1 1
III
0 0 0
000
0 0 0
000
Adder Op.
Test Hyperbolic Mode
3-43
/
i
E~rE«NAL
O.vteE'
DESTINATIoN BUS
"
I--
HAtH
OMA
HEHoRY
(ORO)
~oPr.)
..,1._"""
;
ADDJ.&IS
r - - - - - r- - - - - - - - -
~
MEMORY
j
ADO~E~S
D~~
~~
- - - - - -- -
- - --,
I
i.
,
I
I
(HA- S~t. )
CONTRoL.
~--------~--~
I
4S- SI
I
I
I
I
I
I
I
r ---- - - - ----'
,
(FA S.L.)
I
!
r - - - - - - --,
II
I
( P SEt.. )
I
I
(NOAa 5.1-)
:
t
J,
:
88
;:s-s-,
\.S).
~
48-5"1 :
I
It
G
r-----------
11t
I
G
I
~O,
L ___
_ _ _~S,47
____
,
I
J
89 I
~J
SOIA
t- _______
"ce 8 us
Figure 3-16.
-1
f1El1o~Y
C.ON 'tt.o l-
73 74 7,-gl
It
Memory Interface Functional Block Diagram
~
B3
~OM
I
t
I
82,83
:
I
3-66. Memory Address Control. The memory ad(1:::-!~SS control ci rcui ts provide the
address information to the main memory or the NlJiW memory.
3-67. The program address register (P register) holds the address of the next
macroinstruction. To read the next instruction. its contents are loaded into the
memory address register (MAR) through the memory address selector. It then advances by one to be ready for reading the subsequent instruction. Double length
instructions require two memory references, with the P register ~dvancing after
each reference. Addresses of operands, addresses for Execute Hemote instructions
(Op Code 35 RK), and addresses for IOC memory references are not placed into the
P register; they are placed directly into the MAR from the destination bus through
the memory address selector. On jump instructions, the new address is loaded into
the P register from the destination bus.
3-68. The breakpoint register permits stepping the DPS when a pre~selected memory
address is referenced. This function is especially useful when troubleshooting.
The breakpoint register can be loaded manually from the control panel. It works
in conjunction with the Read and Write Breakpoint switches on the panel. If the
appropriate Read or Write Breakpoint switch is set, the DPS will stop if it references the address contained in the breakpoint register. Comparator circuits
appearing on figures 9-52 and 9-53 check for equality between the contents of MAR
and the breakpoint register. Gates appearing on f:gure 9-81 generate a stop signal
if equality occurs at a write request while the breakpoint WRITE switch is activated
or at a read request while the breakpOInt READ switch is activated.
3-69. The address from the memory address register (MAR) is transmitted to main
memory through the page addressing circuits. This provides a capability often
called relative addressing or virtual memory. It allows a block of program to be
placed into any "page" of the main memory, and still be correctly addressed. All
memory addresses are subject to page addressing; many of these addresses may already
have been indexed or indirectly formed. Page addressing is illustrated in figure
3-17. For page addressing, the lower ten bits of MAR are transmitted directly to
the memory. They represent a page of 1024 (lK) addresses. The upper six bits
select one of 64 page address registers. The contents of that register become the
upper six bits of the memory address and effectively select one of 64 lK pages.
The page address registers must be correctly loaded by program means, using the
operation code 54 macroinstructions. The uppermost bit of the page address registers is set by the control logic or by bit 15 when loading. It is used as a flag
bit. ~hen loading or storing the page address registers, the register number
(address) is placed into the page counter. For multiple loads and stores, the
counter advances to successive addresses. On master clears, an initialize subroutinl
residing in address 178 - 238 of micro memory loads each page address register with
its own address, i.e. (00) = 0, (01) = 1, --- (778). Therefore, in the initial
condition, all memory references are to the true memory addresses.
3-70. Memory Data Interface. The memory data interface section transfers data to
and from the main memory. It comprises the memory data register (MDR) , the MDR
selector, and the byte selector.
3-71. The MDR holds the data being transmitted to or from the memory. It receives
its input through the MDR selector as follows: 5150
00, Source Bus; 5150
01,
Destination Bus; 5150 = 11, Memory Data In. The data on the Memory Data In Jines
can be either from the main memory or the NDRO memory. Data transferring in from
memory is gated to the source bus through the byte selector. Data transferring out
is gated to the main memory through the byte selector. The byte selector normally
=
=
3-45
DESTINATION BUS
~
PAGE
COUNTER
MEMORY ADDRESS REGISTER (MAR)
10 BITS
6 BITS -r
coNTROL
!
,
AD~~SS~
,
I
SELECTOR
PAGE ADDRESS
REGISTERS
(64 X 7)
I
, ~
,
~
TO SOURCE
BUS
Figure 3-17.
~---------~~~--------~/
ADDRESS BITS
TO MEMORY
Page Addressing Function
transfers the data bit for bit, but when the Reverse Byte signal is present, it
interchanges the upper and lower eight bits. MDR bits 12 through 14 are also sent
to gates appearing on figure 9-206 which enable the microprogram to look at the
J-value of indirect addresses.
3-72. Indirect addressing of operands is possible on RX format macroinstructions
'with m-field values of 10, 12, 14, or 16. The programmer controls indirect addressing by specifying these m-values and by controlling the contents of the indirect
address control bits in status register u2 (see figure 3-11). Indirect address
words are double length and have the format shown in figure 3-18. The J-value of
the first word determines the formation of the operand address. J-values of 4
through 7 specify a cascaded indirect word; that is they cause formation of the
address of another double length indirect word. Cascading may be repeated any
number of times before the final operand address is formed.
3-73. NORO. The OPS has 192 words of semiconductor ROM called the NORO (nondestructive read-out) memory. It is divided in~o two blocks. One block contains
64 words and is aSSigned addresses 00-778 ; the other block contains 128 words and
is assigned addresses 300 - 4778. Generally, the entire 192 words are used for a
bootstrap load program. The programs vary according to the channel and type of
peripheral device used for program loading. ROM memories are programmed at the
time of manufacture and cannot be changed except by substituting a different ROM
card. Access to the NORO memory is exclusive to the processor, and is performed
when the NORO mode bit (bit 12) in status register 1 is clear. The BOOTSTRAP 1-2
switch on the operator's panel permits choosing either of two bootstrap programs
3~6
J,
,
154
x,
"
~12111
Unassigned
15 ..
J Value
~o
lAW 1
.0
lAW 2
Address determination
0
Final operand at address specified by (lAW 2)
1
Final operand at address specified by (lAW 2) + (Rx)
2
Final operand at address specified by (lAW 2) + (Rm)
3
Final operand at address specified by (lAW 2) + (Rm+ 1)
4
Cascaded lW at address specified by (lAW 2)
5
Cascaded lW at address specified by (lAW 2) + (Rx)
6
Cascaded lW at address specified by (lAW 2) + (Rm)
7
Cascaded lW at address specified by (lAW 2) + (Rm+ 1)
10-17
Unassigned
Figure 3-18.
Indirect Address Format
3-47
combined in the NORO. In the BOOTSTRAP 2 position, the switch enables the execution
of a conditional jump instruction (operation code 40) with an a-designator of 7.
The switch may also be used, at the programmer's discretion, to control branching
in other programs.
3-74. The NORD memory is addressed through the NORD selector. The address is
normally from the MAR. However, for the optional COROIC operations, additional
ROM locations are provided in the NORO, and they are addressed from the shift
counter. Bit 2 from the macroinstruction register m-field, inserted as bit 5 of
the shift count, determines whether the NORD memory reference is for a trigonometric
or a hyperbolic function. The NORD memory output is gated onto the memory data in
bus for gating through the MDA selector into the memory data register. For COROIC
operations, the NORO output is gated onto the source bus via the IR selector.
3-75. Memory Control. These circuits control the memory interface. They generate
the control signals for the memory and receive control signals from the memory.
Refer to the main memory description (para. 3-78) for a discussion of these signals
and their effect on memory operation. The memory control circuits are directed by
memory mode bits from the S-field on Micro Control (F=15) microinstructions (see
Appendix A), or from bits 15-13 of the emulator control word (see figure 3-9).
These bits are gated into a storage register and translated by circuitry shown on
figure 9-78. Mode bit configurations of 000 or 010 generate a whole word read
operation; the full cycle Signal is active, and the write upper (zone 2) and write
lower (zone 1) Signals are inactive, causing a read operation for both bytes. Mode
bit configurations of 001 and 011 generate a whole word write operation, with the
write upper and write lower Signals active, to cause a write operation in both
bytes. The write zeros operation (101) is identical except that the MDR to memory
bus signal is disabled, so the bus remains zero to write zeros into memory. 010
and 011 generate the memory address 20 Signal, forcing an odd address. A read byte
operation (110) is similar to a whole word read, except that bit 15 of the condition
register is sampled by circuitry appeaoing on figure 9-76 to generate the byte
point odd signal on figure 9-78. Rm 2 of Byte Load macroinstructions is the byte
identifier and is shifted off into condition register bit 15. If the upper byte
is required (CR215 clear), the reverse byte Signal is generated, causing the upper
byte from MOR to be gated into the lower position through the byte selectors. On
write byte operations (Ill), CR215 causes generation of either the write upper or
write lower signals. Mode bit configuration 100 generates the read split cycle
(read, modify, and restore) operation. The full cycle Signal is disabled and a
split cycle flip-flop sets to enable generation of the write initiate signal (figure 9-79).
3-76. The write initiate signal is generated only for the restore portion of the
split cycle operation. The read initiate signal (figure 9-79) initiates all other
memory operations. The load MAR and initiate Signal (figure 9-77, element 12) is
present on emulate starts and branches, and on Micro Control (F=15) microinstructions
with 0=4 or 14. It produces the signal called "words" (figure 9-78) to cause the
setting of the memory request flip-flop (07905) and generation of the read initiate
signal (figure 9-79). When the data available signal comes from the memory, it
clears the memory request flip-flop. This sets a data available control flip-flop
to disable the clear signal until the memory drops the nata available signal.
3-77. Time delay flip-flops 08 and 09 on figure 9-79 control the memory resume
fault. The read initiate enable Signal sets flip-flop 09. Normally, it is cleared
again when the memory request flip-flop clears. If the data available signal
doesn't arrive before the time delay expires, flip-flop 08 sets. After another
3-48
time delay, its output appears as an artificial resume signal to clear the memory
request flip-flop and set the resume error flip-flop (figure 9-76). The total
delay for the two time delay flip-flops is factory preset at approximately 12 nsec.
3-78. MAIN MEMORY (MM). The MM stores instructions and data for the macroprogram
and, if the optional direct memory access (DMA) logic is installed, can be directly
accessed by external devices. The memory is a random-access core storage device
using three-wire, 2-1/2D organization. It is capable of operating in two modes:
full cycle (read/restore or clear/write) and split cycle (read/modify/write), The
memory performs a full cycle in 750 nanoseconds and a split cycle within 1000 nanoseconds. Access time is 425 nanoseconds maximum, measured from the leading edge of
the initiate signal, to the time data from a specified address is stable on the data
output lines. The basic storage unit in the memory is the Memory Array Board (MAB).
It is an 8K word X 16 bi t core array. The memory c:1assis can accommodate up to eight
of these 8K arrays, giving a storage capacity of 65K words X 16 bits.
3-79. Memory Organization. The memory core arrays:' and all related circuitry are
contained on three types of circuit boards: memory control board (MCB) , memory
data board (MDB) , and memory array board (MAB). The memory is arranged into two
memory banks, each containing a control board, a data board, and from one to four
array boards. See figure 3-19. As supplied, the memory chassis contains the control boards and data boards for both banks, and is designated the Control, Memory
Unit. Array boards. designated Core Memory Unit, are inserted to produce the
desired memory size. The functions of the individual boards are detailed below.
3-80. The memory control board (MCB) contains most of the interface circuitry and
control logic for the memory bank. Included on the MCB are:
1) The timing and control logic, which receives the control signals from the
processor and generates the internal timing;
2) The address register, which stores the incoming address information and
drives the address decoding logic;
3) Address decoding logic, which selects the address and enables the read and
write drivers;
4) Module read and write drivers, which provide internal control Signals to
access d memory address;
5)
3-81.
An optional configuration of the MCB also contains a portion of the DMA logic.
The memory data board (MDB) contains the following circuits:
1) The data register, which receives and holds data read out of the memory or
data to be written into the memory;
2) The data out gates, which gate the contents of the data register to the data
output buss;
3) The module write bit gates, which gate the contents of the data register to
the bit switches on the array board;
4) An optional configuration of the MDB contains, in addition to the above, the
balance of the DMA logic.
3-4Q
""oc.n
I
I
pATA
IN
.... ME- MOl(
Y
WI( I rE
DATA
.,-
17~.rA
,
.....
BOARD
JDATA
/fr{£#/oRY
(MDB)
001
H €. IA " .<:' f(
AR!t.A rlfJl/
$IGIV"L.1
""
MEMollY
,
I
-
-
I
.-SAME
I
-
-
-
AS
-
-
-
-
t7~V
ARRAY
'"
j\
(otr-rl(oL
f,A.t
M
[JOAK
BANK
-
0
-
-
BANK 0
I
I
1_
I·
I
-
-
-
--
Figure 3-19.
-
-
-
-
Al\E~OA..Y
Main Memory Block Diagram
-
I
-
BAIV/( L
-- -
I
3-82. The memory array board (MAB) contains the core arrays and switching and
diode circuits, as follows:
1) The core array. This is the basic storage area for the MAB and consists
of an 8K X 16 bit core array arranged on one double-sided board. The 8K array
further subdivides into 16 mats, one for each bit;
2)
The sense amplifiers;
3) A word switch-diode matrix, containing two sets of 16 X 16 diode pairs (one
set for each half of the core array).
4) A bit switch-diode matrix containing 16 sets of 4 X 4 diode pairs (one set
for each bit mat).
3-83. Operating Modes. The memory is capable of operating in two modes: Full
cycle (read/restore or clear/write) and split cycle (read/modify/write). During
a full cycle read, data is fetched, or read out from a selected address in memory,
and then the same data is restored to the same address location. During a full
cycle write, existing data is cleared from a selected address in memory, and new
data is written into that address. During a split cycle, data is read out from
a given location and replaced wholly or in part with modified data.
3-84. Interface Control Signals. Table 3-15 lists the memory interface signals.
The control signals received by -and transmitted from -the memory interface regulate the operation of the memory and inform the controlling equipment (processor
or DMA device) of the memory status. The interface signals are described in detail
below.
3-85. The +memory select signal functions as an address signal by selecting one
of the two banks of memory. Only one of the two memory select signal lines can be
high (active) at one time. The signal, in conjunction with the memory initiate,
activates the control circuits of the selected memory bank. The signal is received
by the memory at the start of both a full and split cycle operation and at the
write initiate time of a split cycle operation. The signal must remain active at
the memory interface for a minimum of 100 ns.
3-86. The +read initiate signal initiates all memory operations except the write
portion of a split cycle operation. The Signal activates the memory bank control
circuits and must remain active for a minimum of 75 ns.
3-87. The +full cycle Signal is received at the start of a full cycle operation.
The Signal activates circuits which enable the memory timing chain to cycle through
twice without interruption, once for the clear or read portion of the memory cycle,
and once for the write or restore portion. The activated circuits also help to
initialize the control circuits at the end of the operation. The -full cycle signal
is received at the start of a split cycle operation and specifies a read/modify/
write. The Signal activates circuits which a) enable the memory timing chain,
b) enable the memory available signal at the end of the read cycle, c) enable reinitiation of the timing chain at the start of the write cycle of the operation,
and d) enable initialization of the control r.ircuits at the end of the operation.
The Signal must remain in the desired state for a minimum of 100 ns after the leading edge of the initiate Signal goes high.
3-51
Table 3-15.
Memory Interface Signals
Inputs to Memory:
Address In
(15 lines)
Data In
(16 lines)
+Full Cycle
(1 line)
+Read Initiate
(1 line)
+Write Initiate
(1 line)
-Power Fault
(1 line)
-Zone Write Upper
(1 line)
-Zone Write Lower
(1 line)
+Memory Select
(2 lines)
Outputs from Memory:
Data Out
(16 lines)
-Data Available
(1
line)
+Memory Available
(1
line)
3-88. The -power fault signal is a reset signal generated by the DPS power supply
during initial power up, or when the power supply shuts down due to input power
failure. The signal causes the memory to clear its control circuits and address
register.
3-89. The +write initiate signal is received at the start of the write portion of
a split cycle operation and is an order to write data into the memory. The signal
activates the memory bank control circuits and must remain active for a minimum of
75 ns.
3-90. The zone write upper and zone write lower signals control the operation of
the memory on their bytes of the memory word. When a zone signal is low, the memory
data register accepts input data for that byte and writes it into the selected
memory address. When a zone signal is high, the memory data register reads data
from that byte of the selected address and restores it back again. When both zone
signals are low or both high, the memory performs a whole word write or whole word
read, respectively. The zone write signals must hold their state for a minimum of
100 ns after the initiate signal becomes active.
3-91. The -data available signal informs the processor or DMA device that data
has been read from the memory and is available for sampling on the memory output
data lines. The signal is present on a memory output line between 300 and 400 ns
after start of the read operation of both full and split cycles.
3-52
3-92. The +memory available signal is present on a memory output line except when
the memory is processing a memory request. The signal informs the requesting device
that the memory can be accessed. The signal is needed by the processor before it
can initiate an operation and again before it can initiate the write portion of a
split cycle operation.
3-93. Timing and Control Functional Description. The organization of one memory
bank is shown in the bank block diagram. figure 3-20. The dotted lines on this
diagram show the partitioning of the bank in terms of printed circuit boards. while
the bloeks inidicate the basic functional units. Each memory bank contains one
control board. one data board, and from one to four array boards. The diagram
shows only one of the array boards but does show the signals running to/from the
other three array boards. Reference may also be made to figure 3-25. a detailed
schematic diagram of one core stack and associated switch and diode circuits. The
timing and control block of the bank diagr~m is further detailed in figure 3-21.
The timing and control section receives control signals from the memory control
interface and initiates internal timing and control signals required to execute a
memory operation. The following paragraphs describe the functions of each block
in the timing and control block diagram.
3-94.
set at
timing
a full
during
of the
signal
The busy control circuits consist essentially of two flip-flops which are
the start of a memory operation and whose outputs enable all of the other
and control section functions. The circuits remain active during all of
cycle operation. During a split cycle operation, the circuits are active
the read portion, then become inactive. and are again activated at the start
write cycle. When busy control is inactive. it enables the memory available
to the requesting device (processor or DMA device).
3-95. The clock-oscillator circuit is activated by a signal from the busy control
circuits at the start of a memory cycle ana continues to operate until busy control
goes inactive. Outputs of the circuit are nominal 30-nanosecond pulses used primarily to clock the timing chain. Figures 3-22 and 3-23 show the clock-oscillator
and timing chain pulses. Figure 3-24 shows the clock-oscillator and timing chain
circuits. Two clock signals are produced by the clock-oscillator, CLOCK 1 and
CLOCK 2. CLOCK 1 is used to produce Tl, T3, T5, T7, and T9 of the timing chain.
while CLOCK 2 produces T2, T4, T6, and 18.
3-96. The timing chain consists of nine series connected. -edge-triggered flipflops which are connected as a shift register. Outputs of the timing chain are
timing pulses and pulse complements designated Tl through T9, each having a duration
of about 190 nanoseconds. The pulses control the sequencing of the memory operations. The timing chain cycles through twice for each kind of memory operation.
For a full cycle operation, the timing chain runs continuously until completion of
the two timing cycles. For a split cycle, the timing chain cycles once to time the
read part of the operation and then becomes inactive until the start of the write
portion, at which time the timing cycle is restarted. Pulse T9 is shortened at the
end of both timing cycles during a split cycle operation, and T7, T8, and T9 are
shortened at the end of the full cycle operation •. This occurs when busy control
becomes inactive.
3-97. The general reset control initializes the memory control circuits during a
power up and prevents accidental loss of memory data in the event of a power loss.
Inputs to the control are +5 and +15 volt power, a power fault (-PF) signal from the
processor, and a signal from busy control. Outputs are a master clear and enable
3-53
signals. During an initial power up or following loss of power, the reset control
master clears (initializes) the memory timing and control circuits. When power
reaches an operational level, the circuit outputs enable the bit selector, module
write drivers, and module read enable drivers. The reset control also permits the
memory to execute an orderly shut down sequence when a power failure occurs. Under
such a condition, the control maintains its enable outputs until the operation is
completed (full cycle) or until the timing chain cycle is completed (split cycle).
Thus, in the case of a full cycle or the write part of d split cycle, the memory
has time to write data into memory before complete power failure occurs.
3-98. The cycle control section consists of a single fllp-flop which is always in
the clear state at the start of a memory operation. The Hip-flop is set at the
start of an operation by the active +full cycle input control Signal to specify a
read/restore or clear/write operation. If the signal is In~ctive (-full cycle) at
the start of an operation, then the flip-flop remains cl~ar~ specifying a read/
modify/write operation. Outputs of the flip-flop enable the timing chain, enable
the memory available signal following the read portion of 8 split cycle, and enable
final initialization (clearing) of the busy control circuits.
3-99. The read control section is comprised of two read flip-flops, whose outputs
combine with other timing and control signals to provide sequencing of the read
operation. The Read Initial flip-flop is always in the set state at the start of
a memory read cycle, having been set either by n master clear, or by the TS pulse in
the previous memory operation. The flip-flop is cleared by the NOT TS pulse at the
end of the read cycle. The Read Final flip-flop is always in the clear state at
the start of a memory read cycle. It is set at T3 time of the first timing cycle
and is cleared at T3 time of the second timing cycle.
3-100. The write control section is comprised primarily of the Zone Write Upper
and Zone Write Lower (ZWu and ZWL) flip-flops. They are set only at the start of
a memory operation if the corresponding ZWu or ZWL control Signal is received. The
ZWU flip-flop clears bits 8-lS of the data register and gates bits 8-lS from the
input bus into the data register. ZWL flip-flop effects the same actions for bits
0-7 of the data word. If a flip-flop is not set, the corresponding byte in the data
register will retain the data received from the memory matrix during the read cycle,
so the same byte data will be restored to its original matrix address.
3-101. Memory Address Register. The address register functions as an open latch
for address bits 0-14 received from the memory input bus. Outputs of the register
are continuously applied to the address decoder circuits.
3-102. Address Decoder. The address decoder receives the memory address from the
address register and continuously translates the bits to select the address to be
accessed. Fifteen address bits are required to select an address in one memory
bank. The bits are decoded as shown in table 3-16. The address decoder contains
three sub-functions which issue decode Signals to select the memory address. They
are the module selector, the word selector, and the bit selector.
3-103. The module selector decodes address bits 13 and 14 to select one of the
four array boards (8K of memory). As stated in paragraph 3-8S, one memory bank
(32K) is selected by the memory select input signal. The module selector is enabled
if the array board is present in the memory chassis. Outputs of the circuit go to
the module read and write drivers and to the module write bit gates.
3-54
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3-63/(3-64 blank)
Table 3-16.
Address Bit Decode
ADDRESS
BIT
SELECT
14, 13
Select one of four array boards in the memory bank.
12
Select one of two core stack sections on the selected array
board.
11 - 8
Select one of 16 word drive lines in each of 16 word groups.
7 - 4
Select one of 16 word groups (bits 12 - 4 in combination
select one word drive line in a core stack).
3, 2
Select one of 4 bit drive lines in each of 4 bit groups.
1, 0
Select one of 4 bit groups (bits 3 - 0 in combination
select one bit drive line in a core stack).
3-104. The word selector translates bits 4 through 12 to select one word drive
line in a core matrix. Bit 12 selects one of the two core array sections (upper or
lower) on an array board, thus selecting 4K of memory. Bits 8 through 11 select one
of 16 word drive lines in each of 16 word groups, thus narrowing the possible addresses to 256. Bits 4 through 7 are decoded to select one word group out of a
possible 16 groups, thereby narrowing the possible addresses to 16. Outputs of the
word selector are word diode and word group signals which are continuously applied
to the word switch gates on the array board.
3-105. The bit selector decodes bits 2 and 3 of the address register to select one
bit drive line in each of four bit groups, thus decreasing the possible memory
selection to four addresses. Bits 0 and 1 are decoded to select one bit group from
among four groups. At this point the address bits have selected one address in the
memory bank. Outputs of the bit selector are bit group and bit diode signals which
are continuously applied to the bit switch gates on the array board, except for a
period of about 70 nanoseconds at the end of a memory operation.
3-106. Module Read Drivers. The module read drivers consist of four sets of drive
gates, one set for each array board. A gate is enabled between the 25 and 365 nanosecond times of a read cycle when the array board has been selected for access by
the module selector. Outputs of the gates are module read bit source and read bit
sink signals which gate the bit selector decode (bits 0 - 3) to the bit switches,
thereby causing read current to flow in the selected bit drive line of each mat in
the core array.
3-107. Module Read Enable Orivers. The module read enable drivers consist of four
sets of drive gates, one set for each array board. A gate is enabled at T3 time of
a read cycle and remains enabled until 365 nanoseconds after zero time of the read
cycle. Outputs of the gates are module read enable signals which gate the word
selector decode (bits 4 ~ 12) to the word switches, thereby causing read current to
flow in the selected word drive line of the selected core array.
3~5
3-108. Module Write Drivers. The module write drivers consist of four sets of
drive gates, one set for each array board. The gates are enabled at T2 time of a
write cycle if the module has been selected by the module selector, and remain
enabled until the end of T4 time of the write cycle. Outputs of the gates are
module WRITE signals which gate the address decode to the word write switches
during a write operation, thereby causing write current to flow in the selected
word drive line.
3-l0Y. Data Register. The memory data register, physically located on the data
board, acts as an open latch to hold data received from memory addresses via the
sense amplifiers or data received on the memory input lines from the processor or
DMA device. The register is cleared at the beginning of the read cycle, and again
at the start of the write portion of a split cycle, depending on the setting of the
zone write control signals (paragraph 3-90). During a read cycle, data from the
sense amplifiers is loaded into the register by the strobe signals, which are active
from approximately 295 to 415 time of the read cycle. During a write cycle, data
received on the input bus lines is gated into the register by the data to DR signal,
which occurs between times 45 and 160 of the write cycle. Data loaded into the
register from the input bus may be a complete l6-bit word or an 8-bit byte, as
determined by the setting of the zone write flip-flops. Data register outputs go
to the data out gates and to the module write bit gates.
3-110. The data out gates enable the data register outputs to the memory output
data lines. The data is gated out by the data to bus signals, which occur during
T9 time of a read cycle. The module write bit gates consist of four sets of gates,
one for each array board in the memory bank. Each set of gates contains 16 gates,
one for each bit in the data word. Inputs to the gates are from the data register,
and they are gated by the EN WRITE signal which occurs during times T2 and T4 of the
write cycle. Outputs of the gates are write bit (0 - 15) signals. The signals are
applied to the bit write switch gates, thereby gating in the bit selector decode and
causing write current to flow in the selected bit drive line.
3-111. Word/Bit Switches and Diodes. The word and bit switches consist of gating
circuits and transistors which "switch" on to cause current to flow in matrix drive
lines. Inputs to the switches are address decode signals and internal read or write
control signals. A set of the switches is located at each end of the word and bit
drive lines, and current flows when the switches at both ends of a line are switched
on. See figure 3-25 for switch detail. Two sets of diodes are located at one end
of both the word- and bit-matrix drive lines. The sets of diodes are of opposite
polarity, one set permitting current to flow in one direction for a read operation,
the other set permitting current to flow in the opposite direction for a write
operation. The diodes connect on one end to the transistors in the switches; on the
other end they connect to the matrix drive lines.
3-112. Memory Stack. Each memory array board holds an 8K array stack, electrically
divided into two sections designated as upper and lower. Each stack contains 16
core-mats. A mat holds one bit, for example bit 1, of each of the 8192 (512 X 16)
addresses in the stack. A mat is constructed with 512 cores along one axis (word
axis) and 16 cores on the other (bit axis). A word drive line runs through all of
the 16 cores in one group column of one stack, and a bit drive line runs through all
of the 512 cores in one bit row of the stack. A cure is read, or written into, when
word current and bit current flow through the core at the same time. These "coincident" currents flow in one direction for a read operation and in the opposite direction for a write operation. When a "1" is written into a core, the state of the core
is changed from one magnetized state (designated the "0" state) to the opposite"
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Write BCW2
Highest u Int:
Returns control to CP u Code
-
at point of I/O Break In.
Saves an address for return to operation if only one data transfer is required.
No address is saved on multiple data transfers.
3-89
PeRIPHc~AL
£QtJ 1~;1IE IV r
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EXTeRNAL F'UNCTIOAJ R£G(lJCST LING
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Figure 3-32.
Table 3-25.
NAME OF LINE
1£
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r- t e ;; /. r: ,'.: a I tY. 'it *' ~ /,
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Parallel Output Communication Interface
Function of Parallel Output Channel Lines
DIRECTION OF
SIGNAL
FUNCTION
External
Function
Request
Line (Control)
Peripheral
Equipment to
lOC
Set condition indicates readiness of the
peripheral equipment to accept an External
Function Code Word on that channel.
External
Function
Acknowledge
Line (Control)
lOC to
Peripheral
Equipment
Set condition indicates the IOC has placed
an External Function Code Word on the Output Data Lines of that channel.
Output Data
Reques t Li ne
(Control)
Peripheral
Equipment
to lOC
Set condition indicates readiness of
the peripheral equipment to accept a
word of data on that channel.
Output
Acknowledge
Line (Control)
lOC to
Peripheral
Equipment
Set condition indicates the IOC has
placed a word of data on the Output
Data Lines of that channel.
Output Data
Lines
06-Bi t Data)
lOC to
Peripheral
Equipment
Carry 16-bit output data word.
3-90
P£~/PHE~AL
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roc
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LINE
EXTeRAI~1. XNTGIIP.VPi i£QV£ST LINE
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c.HAIt/NeL
:I.NPt)7 A C.KAlDWL6 DGE LINe
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CHANNE./.
Figure 3-33.
Table 3-26.
Parallel Input Communication Interface
Function of Parallel Input Channel Lines
NAME OF LINE
DIRECTION OF
SIGNAL
External Interrupt Enable
Line (Control)
IOC to
Peripheral
Equipment
Set condition indicates readiness of the
IOC to accept an External Interrupt Code
Word on that channel.
Input Data
Request Line
(Control)
Peripheral
Equipment
to IOC
Set condition indicates that the peripheral equipment has placed a word of data
available to the IOC on the Input Data
Lines of that channel.
External Interrupt Request
Li ne (Con tro l)
Peripheral
Equipment
to IOC
Set condition indicates the peripheral
equipment has placed an Interrupt Code
word available to the IOC on the Input
Data Lines of that channel •
. Input Acknowledge Line
(Control)
IOC to
Peripheral
Equipment
Set condition indicates that the IOC has
sampled the Input Data Lines of that
channel.
Input Data
Lines
(l6-Bi t Data)
Peripheral
Equipment
to IOC
Carry l6-bit input data word.
FUNCTION
3-91
OUff:.,I";
"I.NPVr
Df,~rf-'
/YAft.1 fJeR.
I'
I'
,
1. --,
I
i .:7"..-' PN LlfJ~ " ....
7=-A- (". s £ ,.",: :. 'i b ~ i ~.' s ted
Figure 3-34.
l
Parallel Slow (-15V) Interface
6) Circuit output does not switch as a result of any input transient-pulse signal with an integrated amplitude-duration of less than 15 volt-microseconds (a delay
of 1.5 ~ 0.5 microseconds with a IS-volt step input).
3-130. The -15V output driver has the following characteristics when driving a line
with 6000 or 12,000 picofarads capacitance:
1)
Binary one steady state output voltage is -1.5 volts to +1.5 volts.
2)
Binary zero steady state output voltage is -10.0 volts to -17.5 volts.
3) Voltage variations between all binary zero output signals on one channel does
not exceed 1.0 volt.
4) Voltage variations between all binary one output signals on one channel does
not exceed 1.0 volt.
5) The circuit is capabl& of supplying 4.0 milliamperes per line for a steady
state binary one output, or of sinking 1.0 milliamperes per line for a steady state
binary zero output.
6) Circuit output switches in not more than 6.0 microseconds (measured between 10
and 90 percent amplitude points), and at a rate of not more than 5.0 volts per
microsecond.
7) If power to the control line driver circuit is removed, the driver presents not
less than 100,000 ohms impedance to the line with the restriction that the line volttage is within the range of -10.0 to -17.5 volts.
3-92
3-131. The -3 volt (NTOS Fast) interface uses 0 volts and -3 volts to represent
binary one and binary zero respectively. The switching threshold is-l.5 ± 0.4 volts.
Figure 3-35 illustrates the output driver-input amplifier interface •
.5ltiNAL L IN£
Figure 3-35.
3-132.
Parallel Fast (-3V) Interface
The -3V input amplifier has the following characteristics:
1)
Circui t output swi tches from binary zero to binary one whenever the input
signal changes in the positive direction through the range of -1.9 volts to -1.1
vol ts •
2) Circui t output swi tches from binary one to binary zero whenever the input
signal changes in the negative direction through the range of -1.1 to -1.9 volts.
3) Circuit output is a binary zero whenever the steady state input signal is
more negative than -1.9 volts, and a binary one if the steady state input is more
positive than -1.1 volts.
4)
If circuit input is open-circuited, the output is a binary zero.
5) The circuit does not draw more than 1.5 milliamperes for a steady state binary
one nor more than 0.5 milliamperes for a steady state binary zero.
6) The circuit output will not switch as a result of any input transient-pulse
signal that has an amplitude of less than 7.5 volts if its duration and amplitude
are common to both sides of the line (common mode).
7) Circuit input presents a terminal impedance to the line equivalent to a resistance of 150 to 180 ohms in series with a capacitance of 0.0068 to 0.0100 microfarads.
3-93
3-133. The -3V output driver has the following characteristics when driving a line
with impedance of 100 to 180 ohms:
1)
Binary one steady state output voltage is 0.0 volts to -0.5 volts.
2) Binary zero steady state output voltage is -3.0 volts to -4.5 volts. (The
voltage may be more negative if the driven input circuit presents a more negative
signal, with the restriction that the driven input circuit negative voltage does
not exceed -7.0 volts.)
3) The circuit is capable of supplying 1.5 milliamperes for a steady state binar)
one output, or of sinking 0.5 milliampere for a steady state binary zero output.
4) Circuit output switches in not more than 0.4 microseconds (measured between
0.5 and -3.0 volts).
5) If power to the control line driver circuit is removed, the driver presents
not less than 100,000 ohms impedance to the line wi th the res triction that the li ne
voltage is within the range of -3.0 to -7.0 volts.
3-134. The +3.5 volt (ANEW) interface uses 0 volts and +3.5 volts to represent
binary one and binary zero respectively. The switching threshold is between +0.8
and +2.2 volts. Figure 3-36 illustrates the output driver-input amplifier interface.
SJ~ /VAL
L.JN&
Figure 3-36.
3-135.
Parallel ANEW (+3.5V) Interface
The +3.5V input amplifier has the following characteristics:
1) Output of the circuit switches from binary zero to binary one whenever the
input signal changes in the negative direction through the range of +2.2 volts to
+0.8 vol ts.
2) Output of the circuit switches from binary one to binary zero whenever the
input signal changes in the positive direction through the range of +0.8 volts to
+2.2 volts.
3) Circuit output is a binary zero whenever the steady state input signal is
more positive than +2.2 volts, and a binary one if the steady state input is more
negative than +0.8 volts.
4)
If the circuit input is open circuited, the output is a binary zero.
5) The circuit does not draw or provide more than 2.5 milliamperes when a +3
volt or 0 volt signal, respectively, is applied to the signal input terminal.
6) The circuit output does not switch as a result of any input transient-pulse
signal that has an amplitude between +6.0 and -6.0 volts if its duration and amplitude .are common to both sides of the line (common mode).
7) Input circuit presents a terminal impedance to the line equivalent to a resistance of 110 to 160 ohms in series with a capacitance of 0.0068 to 0.01 microfarad.
8) Signal input and return input terminal input res!stances are matched to within
±.8 percent.
3-136. The +3.5 volt output driver has the following characteristics when driving a
line with impedance of 100 to 180 ohms:
1) Binary one steady state output voltage is 0.0 to +0.45 volt.
sinks a current of 40 milliamperes at the +0.45 volt level.
The output driver
2) Binary zero steady state output voltage is +2.7 volts minimum when supplying
27 milliamperes, or +4.5 volts maximum when open circuited.
3) Output voltage fall times (90% to 10%) and rise times (10% to 90%) are less
than 100 nanoseconds.
4) If power to the control line driver is removed, the driver presents not less
than 100,000 ohms impedance to the line with the restriction that the line voltage
is within the range of +3.0 to +7.0 volts.
3-137. Parallel I/O Timing. Figures 3-37 through 3-42 illustrate the minimum
durations of signals, and timing between signals, in the communication sequence for
each of the three types of parallel interfaces. Figures 3-37 and 3-38 are for the
Slow (-15V) interface. Figures 3-39 and 3-40 are for the Fast (-3V) interface.
Figures 3-41 and 3-42 are for the ANEW (+3.5V) interface. I/O operation timing is
provided by the OPS Master Clock and is developed into timing signals Tl, T2, 1'3,
and T4 in the IOC timing circuitry (logiC diagram, figure 9-202).
3-138. When the Input Data Request (lOR) Line is set, the peripheral equipment
must clear the lOR Line at least 20 microseconds before it changes the data on the
input data lines and sets the External Interrupt Request (EIR) line. This prevents
the DPS from interpreting the External Interrupt Code Word (EICW) on the input data
lines as an input data word.
3-139. When the External Interrupt Reques t (EIR) line is set, the peripheral equipment must clear the EIR line at least 20 microseconds before it changes the external
interrupt data on the input data lines and sets the Input Data Request (lOR) line.
This prevents the OPS from interpreting the input data word on the input data lines
as an External Interrupt Code Word (EICW).
3-140. Parallel I/O Operations. The following paragraphs describe the interaction
of the IOC and the peripheral equipment for the various parallel I/O operations.
Table 3-19 lists the various I/O chip functions.
3-95
0.0 minimum
1 - - - - - - - - - - . -_ _ _ _~....
EFR from
90%---
peripheral
equipment
1.0 usee
minimum
---I~
- - - - - - - - - ---10%
O--------f
0.0
minimum
Peripheral equipment sampling time
1---------.
...
90%OutP1Jt Da ta B1 t
from
ra:
....- - -
16.7 usee
minimum - -.....~
o - - - - - - - - -.....
4.2
u see--~-__I....
minimum
4.3 usee
minimum
1----- --- -- --90%
EFA
from IOC
....-
o ----------------~
Figure 3-37.
3-96
2.8
usee
minimum
--,.....-- .. - - -
Parallel I/O External Function or Output Data Timing
(-15 Volt Interface)
sampling time
~~~--
1------...
90%
0.0 usee minimum
Input Data Bit
from peripheral
equipment
O---___
J
0.0 usee minimum
"0.0 usee minimum
1---------or IuR from
EIR
90%-
peripheral
equipment
o--------------~
0.0 usee minimum .........-
......
1------------·-IDA
from
IOC
0-----------.. . .
1.0 usee maximum
8.0
usee
minimum
1 - - - - - - - - - - -...1
8.0
.....-usee-...
minimum
EIE from
IOC
EIE must be
reset by program
control
0 - - - - - - - - - - - - ..... - ' - - - - - -..
Figure 3-38.
Parallel I/O External Interrupt or Input Data Timing
(-15 Volt Interface)
3-97
...- - 0.0 usee
minimum
-0.5
EPR or ODR
0.8 usee
m n mum
from peripheral
equipment
0 _ _ _ _ _ _....
0.0
- -..... usee
minimum
Peripheral equipment sampling time
1 - - - - - - - - -....
-0.5 v Output Data Bit
from
lit::
3.2 usee
~---+----minimum------~
0---------..
-3 v-
0.4 usee
minimum
----~.-~~
0.5 usee
minimum
1----...,-- - - - - - EFA or ODA
from
roc
.....--=2·.2 use
-3 v-
o------------~
Figure 3-39.
3-98
I
~
minina.un
=l
Ut;e~
0.8
minimum
---~--
Parallel I/O External Function or Output Data Timing
(-3 Volt Interface)
Sampling time
1----..
um
-0.5 v
Input Data Bit
from peripheral
equipment
0-----..
-3
0.0 usee
0.0 usee minimum
minimum--~~
1------EIR . or "fI from Switeh1ng
-9. 5 v
per1pheral
level
equipment
0------.1
0.0 usee
minimum---M~~
1---------IDA from roc
0.8
.....-usee
minimum
-3 v-
o-----------------~
0.4 usee maximum
-----~
2.2
.....-us.e-....
minimum
l-------------~
EIE must be
EIE from
re s.t by progrc
control
IOC
0--- -
- - - - - - ' -_ _ _ _..4
Figure 3-40.
Parallel I/O Interrupt or Input Data Timing
(-3 Volt Interface)
3-99
0----...
+2.7 volts
Ern or
ODR from
I~usee
0.8
peripheral
equipment
min
1i6--
0.0 usee
minimum-..........
0.0 usee
minimum
Peripheral
~--------------~------ equipment
sam ling time
+2.7 volts
o
Output Data
Bi t from IOC
3.2
usee
minimum
1-----..,
0.4 usee
minimum
+0.45 volt
- +0.45 volt
--~~--~
0.5 usee
..- - minimum
o ----____________-.
-- +2.7
volts
EFA or 0tJl
from IOC
1--- - -
-
Figure 3-41.
3-100
-
-
-
~ - , ' - - - - - - -..
Parallel I/O External Function or Output Data Timing
(+3.5 Volt Interface)
sampling time
o
- - - - - -+2.7 volts
Input DaterBi t from
peripheral
equipment
-
-
-
-
-
-
+0.45 volt
1
0.0 usee
0.0 usee
mi nimum
....---IM--
minimum
I.
O•.o.u sec
t4--" ml.nl.mum
o----------------~
-
ElF or
HlI'! from
0.8
.....-
peripheral
equipment
--+2.7 volts
usee
min
- - +0.45 volt
1 -------0.0 usee
minimum - .....
o------------________~
IDA
- - +2.7 volts
from IOC
- +0.45 volt
1-----------0.4 u-;ee
maximum
G-- -
--iII~
-------
-
- +2. 7 vo 1 t s
ElE must be
EIE from IOC
reset by
program control
1 - -_ _ _ _ _ _--'
Figure 3-42.
-
-+O.4~
volt
Parallel I/O External Interrupt or Input Data Timing
(+3.5 Volt Interface)
3-101
3-141. When an External Function buffer has been established for a channel, the
IOC and peripheral unit on that channel transfer an External Function Code Word
(EFCW) in the following manner. See Figures 3-37, 3-39, or 3-41.
1) When the peripheral equipment is ready to accept an External Function Code
Word, the peripheral equipment sets the External Function Request line (this may
have already happened before the External Function buffer was established).
2) In accordance with internal priority, the IOC detects the setting of the
External Function Request line.
3)
The IOC places an EFCW on the output data lines.
4) The IOC sets the External Function Acknowledge line (to indicate that the
External Function Code Word is on the output data lines).
5) The peripheral equipment detects the setting of the External Function Acknowledge line. (The peripheral equipment may clear the External Function Request
line any time after detecting the setting of the External Function Acknowledge line,
but it must clear the External Function Request line before the IOC will recognize
the next External Function Request.)
6) The peripheral equipment samples the External Function Code Word on the output
data lines.
7) The IOC clears the External Function Acknowledge line before it places the
next word on the output data lines.
NOTE
Steps 1 and 2 above are omitted for peripheral equipment which do not have
an External Function Request (EFR) line.
3-142. When the current instruction of the DPS macroprogram is a Forced External
Function, the IOC and peripheral unit on that channel transfer an External Function
Code Word in the following manner. The External Function Request line is not involved and the transfer proceeds whether or not the External Function Request line
is set. See figures 3-37, 3-39, or 3-41.
1)
The IOC places an External Function Code Word on the output data lines.
2) The IOC sets the External Function Acknowledge line (to indicate the EFCW is
on the output data lines).
3) The peripheral unit detects the setting of the External Function Acknowledge
line. (The peripheral unit may clear the External Function Request line any time
after detecting the setting of the External Function Acknowledge line, but it must
clear the Request line before the IOC will recognize the next External Function
Request.)
4)
The peripheral unit samples the EFCW on the output data lines.
5) The IOC clears the External Function Acknowledge line before it places the
next word on the output data lines.
3-102
NOTE
Programming restrictions may be required for peripheral equipment which
cannot accept Forced External Functions at the rate possible. Refer to
individual equipment specifications or technical manuals.
3-143. When an output data buffer has been established for a channel, the IOC and
the peripheral unit on that channel transfer data in the following sequence. See
figure 3-37, 3-39, or 3-41.
1) When the peripheral equipment is ready to accept data, the peripheral equipment sets the Output Data Reques t line (this may already have happened before the
output data buffer was established).
2) In accordance with internal priurities, the IOC detects the setting of the
Output Data Request line.
3)
The IOC places a word of data on the output data lines.
4) The IOC sets the Output Acknowledge line (to indicate that a word of data is
on the output data lines).
5) The peripheral equipment det0cts the setting of the Output Acknowledge line.
(The peripheral equipment may clear the Output Data Request line any time after
detecting the setting of the Output Acknowledge line, but it must clear the Output
Data Request line before the IOC will recognize the next Output Data Request.)
6) The peripheral equipment samples the data word which is on the output data
lines.
7) The IOC clears the Output Acknowledge line before it places the next word on
the output data lines. The actual state (binary one or zero) of the data lines is
detected, therefore the data lines need not be cleared between words.
3-144. The IOC and the peripheral equipment repeat the above sequence for each
successive word of data until they have transferred the entire block of data words
specified by the Output Buffer Control Words. On output operation, the IOC provides a delay between gating data to the output lines and setting the ODA or EFA
lines to insure the data lines are stable for sampling any time the ODA 'or EFA
lines are set. The.ODR and EFR signals, once set by the peripheral unit, remain
set until the IOC sets the corresponding acknowledge line, ODA or EFA respectively.
3-145. The IOC and peripheral unit transfer an External Interrupt Code Word (EICW)
in the following manner. See figures 3-38, 3-40, or 3-42.
1)
The IOC, under program control, sets the External Interrupt Enable line.
2) The peripheral equipment detects the setting of the External Interrupt Enable
line.
3) The peripheral equipment places an External Interrupt Code Word on the input
data lines.
4) The peripheral equipment sets the External Interrupt Request line (to indicate
that the External Interrupt Code Word is on the input data lines).
3-103
5) In accordance with internal priorities, the IDC detects the setting of the
External Interrupt Request line.
6) The IDC samples the External Interrupt Code Word which is on the input data
lines.
7)
The IOC sets the Input Acknowledge line.
8)
Synchronously with step 7, the IOC clears the External Interrupt Enable line.
9) The peripheral equipment detects step 7 or both steps 7 and 8. (The peripheral equipment may clear the External Interrupt Request line any time after detecting the setting of the Input Acknowledge line, but it must clear the External
Interrupt Request line before the IOC will recognize the next External Interrupt
Request.)
10) The IOC clears the Input Acknowledge line before it samples the next word
on the input data lines.
3-146. When an input data buffer has been established for a channel, the IOC and
peripheral unit on that channel transfer data in the following sequence. See
figures 3-38, 3-40, or 3-42.
1)
The peripheral equipment places a word of data on the input data lines.
2) The peripheral equipment sets the Input Data Request line (to indicate that
a word of data is on the input data lines).
3) In accordance with internal priorities, the IOC detects the setting of the
Input Data Request line.
4)
The IOC samples the data word which is on the input data lines.
5) The IOC sets the Input Acknowledge line (indicating that it has sampled the
data word on the input data lines).
6) The peripheral equipment detects the setting of the Input Acknowledge line.
(The peripheral equipment may clear the Input Data Request line any time after
detecting the setting of the Input Acknowledge line, but it must clear the Request
line before the IOC will recognize the next Input Data Request.)
7) The IOC clears the Input Acknowledge 1 ine before it reads the next word on the
input data lines. The actual state (binary one or zero) of the data lines is detected, therefore the data lines need not be cleared between words.
3-147. The IOC and peripheral equipment repeat the above sequence for each successive word of data until they have transferred the entire block of data words
specified by the Input Buffer Control Words. Once the IDR or EIR has been set, the
peripheral equipment must not change the state of the input data lines before the
IOC has acknowledged the request. The only exception to this is that the lOR or
EIR may be cleared before the IDA is received if the possible loss of data is of
secondary importance.
3-104
,'
3-148. The dual channel mode selector card is required to select dual channel
mode. Dual channel operations occur during input data, output data, or external
function transfers, when the transfer mode (TM) designators of a buffer control
word specify double length (32-bit) I/O transfers. The two parallel channels
used simultaneously (n, n + 4) are corresponding channels in consecutive 4-channel
groups, which must have the same interface voltage level. Channel n must be in an
even numbered group (group 0 or 2). Channel n controls the transfer, and channel
n + 4 control is disabled. Channel n + 4 uses memory data located at address Y and
channel n uses address Y + 1, where Y is the address specified in the buffer address
pointer of the buffer control word. Y must be an even., number and must contain the
16 most significant bits of the double length word, with Y + 1 containing the 16
least significant bits. During dual channel operation, an external interrupt word
from the peripheral being referenced will be stored at the memory location corresponding to the lower channel (n) only. Tables 3-23 and 3-24 list the dual channel input and output sequences. See figure 3-43 for dual channel jumper cable block
diagram. A jumper is plugged into both the input and output connectors on channel
connectors of channels nand n + 4. Dual channels are capable of operation in Normal
mode, Intercomputer mode (when so specified on initial order), or Externally Specified Addressing (ESA) mode (when so specified on initial order).
3-149. ESA mode provides an AN/UYK-7 compatible interface. On ESA mode an input
and output channel pair may operate to send or receive data on a word-by-word basis.
The peripheral device then specifies an address for each output and input word requested. On ESA mode output, the peripheral device places the address on the lower
16 bits of the input channel and signals via the Output Data Request line of the
output channel. The lOC places the 32-bits of data (from the requested memory address) on the output channel and sends an Output Data Acknowledge. On ESA mode
input, the peripheral device places the data on the high-order 16 data lines and the
address on the low-order 16 data lines and signals via the Input Request line of the
input channel. The IOC then stores the 32 data lines (data and address) at the requested memory address and sends an Input Acknowledge. Transfers are deactivated by
the IOC executing a 70 RR instruction with an m-designator of 0 or 10, or by normal
buffer termination. For channels to operate in the ESA mode, the mode selector card
must be wired to select the ESA mode.
Only dual channels operate in ESA.
3-150. When the DPS and another computer are connected as illustrated in figure
3-44, they are capable of transferring data in the intercomputer mode. Table 3-27
defines the function of each of the intercomputer channel control lines. The transmit:ing computer holds the data or EF code on the output data lines until the receiving computer sets the Resume line or the transmitting computer program intervenes to
resolve no-resume condition.
3-151. Whenever an External Function buffer has been established in the transmitting computer for a channel, the transmitting computer and the receiving computer
transfer a command word as follows:
*1) When the receiving computer is ready to accept an External Function Command
Word, the receiving computer, under program control, sets the External Interrupt
Enable line.
*
These steps are omitted for computers which do not have an EIE line.
3-105
fER I
PH ERA L
DEy/leE
I
I
1 r-~I
t
t
'I'
J
1
Il
I
;1\
I
/(rS,r
H.-lilT
cIlAN. AI
INpuT"
CIMAI, II
ovr'uT
DPS
Figure 3-43.
3-106
Parallel Dual Channel Jumper Cable Diagram
ONE ,r/o CABLE
,.
Transmit ting
External
Computer
Function
,
Request Line,
.....
-,
I
I
-----r-'Receivlng
Interrupt
Computer
Enable Line
I
--
I
I,
External
Function Ack- I
Interrupt
Ex'ternal
nowledge Line
Inter-
f
*External
I
I
Request Line
I
computer
,....
Normal
Input Data
Ready Line
Request Line
"
Output
[nput
lIo
Channel
Input Data
Acknowledge
...
I
Line
Resume Line
~
Input
Output
)lata
L~!le~
Data Lines
..L
-'-)1..-
*Not alt computers have an External Interrupt Enable (EIE) line; rl:'f.er to the
individual computer specification or technical manual.
Figure 3-44.
Parallel I/O Intercomputer Interface
*2) In accordance wi th internal p'riori ty, the transmi tting computer detects the
setting of the External Interrupt Enable line (which it recognizes as its External
Function Request line).
3) The transmitting computer places an External Function Command Word on the
output data lines.
4) The transmitting computer sets the External Function Acknowledge line (to
indicate that the External Function Command Word is on the output data lines).
5) In accordance wi th internal priori ties t the receiving computer detects the
setting of the External Function Acknowledge line of the transmitting computer
(which it recognizes as its External Interrupt Request line).
6)
*
The receiving computer samples its input data lines.
'these steps are omi tted for computers which do not have an EIE line.
3-107
Table 3-27.
NAME OF LINE
Function of Intercomputer Channel Control Lines
DIRECTION OF
SIGNAL
FUNCTION
*External
Interrupt
Enable Line
Receiving
Computer to
Transmi tting
Computer
Set condition indicates readiness of the
receiving computer to accept an EF command
word on that channel.
Ready Line
Transmi tting
Computer to
Receiving
Computer
Set condition indicates that the transmitting computer has placed a word of
data on the Output Data Lines of that
channel.
External
Function
Acknowledge
Line
Transmit ting
Computer to
Receiving
Computer
Set condition indicates the transmitting
computer has placed an EF Command Word
on the Output Data Lines of that channel.
Res ume Line
Receiving
Computer to
Transmi tting
Computer
Set condition indicates that the receiving computer has sampled the Input Data
Lines of that channel.
*Not all computers have the EIE Line; refer to the individual computer specification or technical manual.
7)
The rec.ei ving computer sets its Input Acknowledge line.
*8)
Synchronously with step 7, the receiving computer clears the External Interrupt Enable Line.
9) The transmi tting computer detects the setting of the Input Acknowledge line
of the receiving computer (which it recognizes as its Resume line).
10) The transmitting computer clears its External Function Acknowledge line before
it places -the next word, on its output data lines, and the receiving computer clears
its Input Acknowledge line before it reads the next word on its input data lines.
3-152. Whenever the currept instruction of the transmitting computer program is a
forced External Function, that computer transfers a Command Word to the other computer as follows:
1) The transmitting computer places an External Function Command Word on its
output data lines.
2) The transmi tting computer sets its External Function Acknowledge line (to
indicate that a Command Word is on the data lines).
* These steps are omitted for computers which do not have an EIE line.
3-108
3) In accordance with internal priorities, the receIVIng computer detects the
setting of the External Function Acknowledge line of the transmitting computer
(which it recognizes as its External Interrupt Request line).
4)
The receiving computer samples its input data lines.
5)
The receiving computer sets its Input Acknowledge line.
6) The transmitting computer detects the setting of the Input Acknowledge line
of the receiving computer (which it recognizes as its Resume line).
7) The transmitting computer clears its External Function Acknowledge line before
it places the next word on its output data lines, and the receiving computer clears
its Input Acknowledge line before it samples the next word on its input data lines.
3-153. Whenever an Output Data buffer has been established in the transmitting
computer and an Input Data buffer has been established in the receiving computer
for the same channel, the transmitting computer and the receiving computer transfer
data as follows:
1)
The transmitting computer places a word of data on its output data lines.
2) The transmitting computer sets its Ready line (to indicate that a word of
data is on its output data lines).
3) In accordance with internal priorities, the receIvIng computer detects the
setting of the Ready line of the transmitting computer (which it recognizes as its
Input Data Request line).
4)
The receiving computer samples the input data lines.
5)
The receiving computer sets its Input Acknowledge line.
6) The transmitting computer detects the setting of the Input Acknowledge line
of the receiving computer (which it recognizes as its Resume line).
7) The transmitting computer clears the Ready line before it places the next
word of data on its output data lines, and the receiving computer clears its Input
Acknowledge line before it samples the next word of data on its input data lines.
The computers repeat this sequence until they have transferred the block of words
specified by the buffer control words.
3-154. MIL-STD-188 Serial I/O. The expanded MIL-STD-188 serial I/O channel interface in either synchronous or asynchronous mode is available as a plug-in option.
NOTE
I/O options are plug-in options, but adapter plugs and a rewired jumper
mode card may be required to change from one I/O option to another. When
an option requires a coaxial cable a l20-pin adapter plug wIth a coaxial
connector is required.
Refer to Chapter 8 for interface jack, pin, and cable assignments. MIL-STD-188
serial I/O channels are available in groups of two channels with the characteristics
3-109
listed in table 3-28. Each channel is capable of internal loopback testing under
program control. Figure 3-45 ill us trates the expanded MIL-STD-188 interface. ,The
MIL-STD-188 interface has seven discrete control lines with +6 volts ON and -6 volts
OFF, and five discrete control lines with +6 volts ON and 0 volts OFF. All 12 of
the discrete control may be used concurrently. The control lines are lettered
ra ther than named as each application may use the discrete functions differently.
Table 3-29 lists the control lines and their function, if designated. Lines TX
Clock and RX Clock are used in synchronous mode only to gate the respective data
lines. All interface lines for one channel are contained in one interface connector.
3-155. The MIL-STD-188 serial I/O interrupt word format is specified in figure
3-46. Either of the three discrete signals shown cause a Class III external interrupt (see table 3-10).
3-156. EIA RS-232 Standard Serial I/O. The RS-232 serial I/O channel interface in
either synchronous or asynchronous mode is available as a plug-in option. Refer to
Chapter 8 for interface jack, pin, and cable assignments. RS-232 serial I/O channels
are available in groups of two channels with the characteristics listed in table 3-30.
Each channel is capable of internal loopback testing under program control. Figure
3-47 illustrates the EIA RS-232 standard interface. The RS-232 interface uses
eight discrete control lines plus two data and two clock (synchronous mode only)
lines. All interface lines for each channel are contained in one interface connector, and all RS-232 data and control lines are EIA standard.
3-157. The RS-232 serial I/O interrupt word format is specified in figure 3-48.
The Ring On or Carrier Off events set the Class III external interrupt (see table
3-10). The DPS stores the interrupt word at the main memory address assigned to
its channel.
Table 3-28.
MIL-STD-188 Serial I/O Characteristics
CHANNEL
TYPE
MODULATION
RATE
CHARACTER
SIZE
Synchronous
Up to 9600
Bits/Second
5, 6, 7, or 8 level
(Selectable under
program control)
Parity bit is program
selectable, and if used
is included in the
character interval.
Asynchronous
75, 150, 300,
600, 1200, or
2400 Bits/ .
second (Any
four* of above
six rates
available (per
two channel
group) as an
ordering
option) •
5, 6, 7, or 8 level
(Selectable under
program control)
Includes a Start bit,
and under program
control one or two
Stop bi ts and a
Parity bit.
* Each
3-110
CHARACTER
INTERVAL
of the four rates are program control selectable for each channel.
'" -
-" -
""
,-
"
"
Al
.....
~
. f"""")
B2
.iii
-.•
C5
L.oiII
Dl
~
E6
,L...
.
"""
Gl
,~
-6V
OFF
I
-p
Fl
o
~_-
+6V
ON
,
)
~
<"
External
Device
•
TX CLOCK*
~
TX DATA
~
~
-
""
-
-- .---.
.
..
--
.....
...
.....:
RX CLOCK*
RX DATA
--.-
-
AN/UYK-20(V)
DPS
-.
'
..
'"
HI
!~
I~
...
12
..
K3, 7
.
:
L4, 7
i
+6V
ON
-,
Jl
~
~
I ......
Signal ground
).
OV
OFF
"~
,
*
Synchronous
mode only
1.
2.
3.
4.
5.
6.
7.
Under Program Control
Generates Class III Interrupts when switched to "ON"
Inhibits Input Transfers when "OFF"
Inhibits Output Transfers when "OFF"
Generates Class III Interrupt when switched to "OFF"
Available as Status to IOC Program
Line will go "ON" when disconnected
Figure 3-45.
MIL-STD-188 Serial Channel Interface
Table 3-29.
MIL-STD-188 Control Lines
CONTROL
LINE
FUNCTION
Al
Under Program Control
Dl
Under Program Control
Fl
Under Program Control
Gl
Under Program Control
HI
Under 'Program Control
Jl
Under Program Control
B2
Generates Class III Interrupt
when switched to ON
12
Generates Class III Interrupt
when switched to ON
K3
Inhibits Input Transfers when OFF
L4
Inhibits Output Transfers when OFF
C5
Generates Class III Interrupt
when switched to OFF
E6
Available as status to IOC Program
K7
Line goes ON when Disconnected
L7
Line goes ON when Disconnected
154
10
-II
9
8
!
711/1:
.. 01
Unassigned
1
1
1
=
= B2
Discrete turned on
= C5 Discrete turned off
12 Discrete turned on
Unassigned
Figure 3-46.
3-112
MIL-STD-188 Interrupt Word Format
Table 3-30.
RS-232 Standard Serial I/O Characteristics
CHANNEL
TYPE
MODULATION
RATE
CHARACTER
SIZE
CHARACTER
INTERVAL
Synchronous
Up to 9600
Bits/second
5, 6, 7, 8 Level
(Selectable under
program control)
Parity bit is program
selectable, and if used
is included in the
character interval.
Asynchronous
75, 150, 300,
600, 1200':',
or 2400':- Bi ts /
second (Any
four*~' of
above six
ra tes available (per two
channel group)
as an ordering
option).
5, 6, 7, or 8 Level
(Selectable under
program control)
Includes a Start bit,
and under program
control one or two
Stop bits and a
Parity bit.
* 1200 and 2400 Bits/second options available at a future date.
** Each of the four rates are program control selectable for each channel.
3-158. NTDS 32-Bit Serial I/O. The NTDS serial I/O channel is available as a
plug-in option on the DPS, when so specified on order. NTDS serial I/O channels
operate in asynchronous mode and are 32 bits in length (a dual AN/UYK-20(V) word
length). Each serial NTDS group consists of an output channel and an input channel.
The,output channel uses one cable connected at the even-numbered output channel location, and the input channel uses one cable connected at the even-numbered input
channel location. The odd-numbered I/O channel connector locations are not used.
Each cable, output and input, consists of a coaxial signal line and a return line
as shown in figure 3-49. Both the output and input channels transfer 32-bits of
da ta along wi th sync bi ts, identifier bi ts, and control bi ts. Table 3-31 lis ts
the ciaracteristics of the NTDS 32-bit channel.
3-159. The NTDS serial interface receives control frames, input data words, and
external interrupt control words. It transmi ts control frames, output data words,
and external fun~tion words. See figure 3-50. There are four types of control
frames. Each control frame consists of a sync bit followed by two control bits.
For each type of control frame, the two control bits specify the control function
(nature of the request or enable, or the not ready status of the equipment). Figure
3-51 defines the four types of control frames.
.
3-160. The EF and EI control words and the data words have the format shown in
figure 3-52. The first bit is the sync bit, the second is the word identifier, and
the remaining bits are the information bits of the word.
3-161. The IOC continually interrogates the peripheral equipment on each NTDS
serial output channel by sending Output Enable Control Frames (OECF) to the peripheral
3-113
c.u
I
.....
.....
.t:..
I....
Loop Test (AI)**
...
.~
Data Terminal Ready (DI)*i<
~
New Sync (EI)**
r...-
r-.
.
Carrier Interrupt (C5)H
...
Ring Interrupt (B2)**
,
II
-...
Receive Clock*
External
. Device
Receive Data
r
...
Transmit Clock*
~
r-.
.~
r
Transmit Data
Request to Send
(GI)*~~
~
Data Set Ready (K3,
6) *"<
.
Clear to Send (E6)*'':
Signal Ground
*
*:',
"...
....
~
,3ynchronous mode only
equivalent
~nL-STD-l88
Figure 3-47.
EIA RS-232 Standard Serial Channel Interface
A11/lJYK- 20 (V)
DPS
15
•
J 10
,)
74
R
.0/
UnasRiined
]
I
.
1
=
=
Carrier off
Ring on
,I Unassigned
Figure 3-48.
RS-232 Jnterrupt Word Format
IDe
PERIPHERAL
EOUIPMENT
INPUT
CHANNEL
SIGNAL AND RETURN
l..1li.
rw
-------
--------
OUTPUT
CHANNEL
SIGNAL AND RETURN
Figure 3-49.
Table 3-31.
III
~
NTDS 32-Bit Serial I/O Channel
NTDS 32-Bit Serial I/O Characteristics
CHANNEL
TYPE
MODULATION
RATE
Asynchronous
75, 150, 300,
or 600 Bits/
second (Accuracy of 1%)
DATA CHARACTER
SIZE
5 or 7 data elements
CHARACTER
INTERVAL
Consists of ten signal
elements with equal time
intervals; one start,
seven or five data, one
Character parity, and
one or two stop elemellts
(programing option).
3-115
we
pprlphernl
EOll i _pmEm\:
Olle COclxiai
Cnhle
+
..... _ .J
,
'External Interrupt Worn
••
I
Input
~
I
,Input lJata Word
•
•
.Input Request Control
CIlannel
..
Frf\1nl~
I
,
.
'Input Enable Control Frame
~---
"
I
- - -- -
External Function Word
I
I
I
Output Data Word
Output
Channel
I...
Output Request Control Frame
~
I
I
I
I
.
II'
.
II'
I
I
I
Output Enable Control Frame
I
I
I
..
r
One Coaxial
Cable
Figure 3-50.
3-1H:
NTDS Serial Channel Interface
I
I
:1
I
2
1
I
Synchronization Bit
I
0
I
0
=
Not Used
0
,
I
1
Input Duta Request (InR)
I
0
=
=
=
1
1
a.
I
1
External Interrupt Request (EIR)
IDR and EIR
Input Request Control Frame (IRCF), Peripheral-to-DPS
3
1
I
j
1
2
I
I
I
0
0
I
1
1
1
h.
Synchronization Bit
0
I
I
I
I
,~-,~
0
1
=
=
=
=
Not Ready
Input Data Enable (IDE)
External Interrupt Enable (EIE)
IDE and EIE
Input Enable Control Frame (IECF), DPS-to-Peripheral
3
I
I
2
I
1
I
0
I
I
Synchronization Bit
I
0
=
Not Ready
"
0
1
1
c.
I
I
I
I
I
1
=
Output Data Request (ODR)
0
=
External Function Request (EFR)
1
=
ODR and EFR
Output Request Control Frame (ORCF) , Peripheral-to-DPS
3
I
_1
11
2
_
_-,-.;
...
............
Synchronization Bit
d.
0
I
0
0
I
1
,I
1
I
Not Used
1
=
=
0
=
External Function Enable (EFE)
1
=
ODE and EFE
Output Data Enable (ODE) ,
I
Output Enable Control Frame (OECF) , DPS-to-Peripheral
Figure 3-51.
3-Bit Control Frames
3-117
~----------- N Hi t
3l,th .L
.,
Ii
,.
J
...
\
31
~6
I5 I
4
I
3
5th
t.th
3rd
2
1
0
2nd
l!';tl
SYllchronization
Bit
!vo rd Ielent if ier Bit:
'~
32 bits
•
r
Input
0
1
= Input Dntll Ford
= Ext£~rnal Interrupt
\vord
Output
34th bit
=
0
= Output Data tlord
1
=
External Fl1nction
Word
last bit in data word and last bit to be transmitted.
Figure 3-52.
NTDS Serial 1/0 Word Format
equipment •. The peripheral equipment responds with an Output Request Control Frame
(ORCF), with both output data and external function bits set. If the IOC has an
active output buffer corresponding to its OECF, it sends, in accordance with internal
priorities, a 32-bit output or external function word to the peripheral equipment.
If the IOC does not have an active output buffer corresponding to its OECF, another
OECF from the roc and another ORCF sequence from the peripheral equipment occurs.
All output control frames and output data are transferred on the output channel
cable. Each 32-bit output data word transferred is accompanied by an OECF and an
ORCF.
3-162. The peripheral equipment continually interrogates the IOC on each NTDS
serial input channel by sending Input Request Control Frames (IRCF) , with both input
data request and external 'interrupt bits set, to the IOC. The IOC responds with an
Input Enable Control Frame (IECF). If the peripheral equipment is ready with its
data, a 32-bit input or interrupt word is sent to the IOC. If the peripheral equipment does not have data corresponding with the IECF from the roc, another IRCF from
the peripheral equipment and another lECF sequence from the roc occurs. All input
control frames and input data are transferred on the input channel cable. Each 32bit input data word transferred is accompanied by an IRCF and an IECF.
3-163. Serial I/O Timing. I/O operation timing is provided by the DPS Master Cloc¥
and developed into timing signals Tl-T4 in the IOC timing circuitry, or timing is
provided from an external source. To assure reliable data transfers, the following
3-118
•
signal timing restrictions (plus cable propagation time of 1.5 nanoseconds/foot) are
required of the equipment. Unles.s otherwise specified the timing requirements are
measured from the leading edge of the synchronization pulse of one event to the
leading edge of the synchronization pulse of the succeeding event. Each of the
following timing requirements refers to the timing on each individual cable.
1) Consecutive Control Frames: Time between consecutive control frames transmitted by the same equipment must not be less than 18.5 microseconds plus cable
propagation time.
2) OECF to ORCF: Time between computer transmitting an OECF and receIvIng the
ORCF from the peripheral equipment must not be greater than 17 microseconds plus
cable propagation time.
3) Enable-To-Request Time Exceeded: If this time exceeds 17 microseconds plus
cable propagation time, the processor must again send the OECF if data transfer is
s ti 11 required.
4) ORCF to Data: There is no time limit between the time the processor receives
the ORCF and the time it transmits the requested output data word.
5) Output to Sync: Time between the trailing edge of the last bit of an output
word and the next sync bit must be not less than 200 nanose~onds.
6) IRCF to IECF: Time between receiving an IRCF and transmitting an IECF must
not be greater than 15.0 microseconds.
7) IECF to Input: Peripheral equipment must transmit an input word within 15.0
microseconds of receiving an IECF. The time between transmission of an IECF and
receiving an input word must not be greater than 17.0 microseconds plus cable
propagation time.
8) Input to Sync: Time between the trailing edge of the last bit of an input
word to the next IRCF bit must not be less than 200 nanoseconds.
9) Transmitter Receiver Pair: Except when the transmitter is transmitting, the
receiver is capable of receiving signals at all times.
3-164.
The output timing characteristics for the NTDS serial I/O are listed below.
1) If the peripheral equipment does not respond to the OECF by sending an ORCF,
the DPS sends an OECF every 30 microseconds nominal.
2) If the periph~ral equipment responds to each OECF with a not ready ORCF, both
the OECF and the ORCF occur within 3 microseconds nominal.
3) If the DPS is to send an external function with force, it begins to transfer
the data word within 30 ~sec nominal after the OECF even if the peripheral equipment did not respond with the ORCF.
4) If normal data transfers occur, the DPS transfers each 32-bit word, along
with the required OECF and ORCF, every 7 ~sec nominal for an effective data transfer
rate of 150,000 words/second (32-bit words).
3-119
3-165. Figure 3-53 provides the bi-polar pulse timing and characteristics at the
transmitter end for the NTDS serial interface. Information is transmitted via bipolar, phase modulated, serial pulse trains. The first pulse (sync pulse) of the
serial pulse train is a phase zero degree pulse (binary one) and is a high polarity
followed by a low polarity. A binary zero pulse is a phase 180 degree pulse (low
followed by high). During the time when control frames or data and control words
are not being transmitted, no signal is present •
.:\---
T= lOO±5 ns
~..- 2.
+2.5ns2 ...
+2.75V-,
[
-
-:..- *t3. 25 ±O. 5V
:....--
-0 V
t
m~x
Figure 3-53.
3-120
-------*-3.25±0.5V
20.9 ns
max
Bi-polar Pulse Characteristics
3-166. POWER SUppLy. The power supply converts the ac input power into the
filtered and regulated dc voltages required by the DPS logic and memory circuits.
It provides protection against input overvoltage and output overcurrent conditions,
and provides master clear and power interrupt status signals to the processor when
input or output voltages are out of tolerance. The power supply occupies its own
chassis at the bottom rear of the cabinet. Figure 3-54 provides a functional block
diagram, and table 3-32 lists the characteristics of the power supply. There are
six power supply schematic diagrams, representing six optional input power configurations. These diagrams are in Chapter 9 (Volume II) of this manual; the
diagram number for each input option appears in table 3-32. The schematic diagram
for the control card used in all power supplies is 7119455. The major functional
elements of the power supply are an EMI filter (on 400 Hz options only), an input
power transformer (on three phase options only), a rectifier circuit, a switching
regulator, a dc-dc converter, power status circuits, and overvoltage/overcurrent
protective circuits.
3-167. EMI Filter. An inductor-capacitor filter network is included in each ac
power input line on 400 Hz input power options to minimize introduction of external
power line noise into the supply and to attenuate transmission of internally generated switching noise. A typical filter network appears on schematic diagram number
7101840, and comprises chokes A3 L1-L9, and capacitors A3 CI-C6.
3-168. Input Power Transformers and Rectifiers. Input transformers and rectifiers
both vary according to the input power options as follows.
3-169. Power supply options having a three-phase input power configuration employ
an input power transformer with either a delta or wye prImary connection. The
transformer secondary outputs are rectified by a three-phase full-wave bridge to
provide the nominal +150 Vdc required by the switching regulator. An inductorcapacitor averaging filter follows the rectifier to smooth the dc input to the
switching regulator. Referring to schematic diagram number 7101840 as an example,
the ac input from EMI filter A3 is applied to the delta-connected primary of Tl.
The Tl secondary outputs are rectified by the full-wave bridge comprised of A7CR14CR15-CR16, and the resulting dc smoothed by series inductor AlLI, and shunt capacitor AICI.
3-170. Power supply options having a single-phase input power configuration rectify the input power directly following the EMI filter without use of an input transforme~.
Referring to the schematic diagram, number 7101875 as an example, the ac
input power is applied to rectifier A7CR14 via A8Rl which limits the starting
current inrush to protect the power switch. Approximately 50 milliseconds after
power application, relay A8Kl closes to effectively remove A8Rl from the circuit.
The rectified output from A7CR14 is filtered by shunt capacitor AICI and the resulting de furnished to .the switching regulator.
3-171. Internal Power. A +15V bootstrap power supply is included in all power
supply configurations to furnish initial operating power to the control circuits
during start-up. After start-up, operating power is derived from the dc to dc
converter outputs. +5V power is provided for the integrated circuits in the power
supply control circuitry.
3-172. The bootstrap power supply consists of a transformer, rectifier, and regulator. Referring to schematic diagram number 7101840, one leg of the three-phase
power input is applied to transformer A4Tl. The transformer secondary output is
rectified by full-wave bridge A6CRl located on the control card, schematic
3-121
_.
PRIME
POWER
INPUT
,....
EMI
FILTERS '
INPUT
TRANSF ORMERRECTIFI ER"
H
SERIES PASS
SWITCHI NG
REGULA TOR
"~r'
,...
DC·TO-DC
CONVER TER
(CHOPPER)
---_._OUTPU T
RECTIFI ERS
AND
FILTE RS
-~
-5.2 VDC
+5 VDC
+12 VDC
-16 VDC
•• _ _ _ _ _ ~w· _ _
'I'
'I'
'I'
V
~
FOLD BACK
CURREN T
LIMITING
~
~
SWITCHI NG
REGULA TOR
CONTRO L
CIRCUIT S
15VOLT
REGULA TOR
+20 VDC
W
OPERATIN~
VOLTAG E
BOOTST RAP
POWER
SUPPLY
.J.
+5VDC
REGULA TDR
+15 VOLTS
TO MEMORY
~
1
OPE:AT ING
VOLTAG E
~
OVERVO LTAGE
OVERCU RRENT
DETECTO RS
+15 VDC STARTIN G
VOLTAG E
~+5VDCTO
~
CONVER TER
OSCILLA TOR
DRIVER
POWER
INTERRU PT
GENERA TOR
______ ___ EXTERN AL
SENSE LINE
i - - - - ~ MASTER
CLEAR
SIGNAL
POWER
-------~~INTERRUPT
SIGNAL
• EMI FILTER USED ONLY ON 400 HZ OPTIONS
•• TRANSF ORMER INPUT USED DNL YON
POWER OPTIONS
3.
Figure 3-54.
!
~
MASTER
CLEAR
GENERA T OR
L.....:;
INTEGRA TED
CIRCUIT S
~
Power Supply Overa ll Functi onal Block Diagram
Table 3-32.
Power Supply Characteristics
ITEM
CHARACTERISTIC/PARAMETER
Input Power
- Option 1
115 Vac +5%, 1ine-to-1ine, 400 Hz 3~ delta
input (schematic diagram No. 7101840)
- Option 2
115 Vac +7%. 400 Hz,
diagram No. 7101875)
- Option 3
115 Vac +5%, line-to-line, 60 Hz, 3~ del ta
input (schematic diagram No. 7101880)
- Option 4
115 Vac ±7%, 60 Hz, 1~ input (schematic
diagram No. 7101885)
- Option 5
115 Vac +5%. 1ine-to-neutra1, 60 Hz, 3~
wye input (schematic diagram No. 7101990)
- Option 6
115 Vac +5%, 1ine-to-neutra1, 400 Hz, 3~
wye input (schematic diagram No. 7101995)
1~
input (schematic
Total Power Requirement
850 Watts nominal
Power Supply Power
Dissipation
250 Watts nominal
Output Power
Tolerance
Maximum Load
-5.2 Vdc
±5%
10.0 Amperes
-5.0 Vdc
±5%
1.0 Amperes
+5 Vdc Memory
±5%
18.5 Amperes
+5 Vdc Processor
±5%
4.2.0 Amperes
+12 Vdc
±5%
1.0 Amperes
+15 Vdc
±2%
12.0 Amperes
-16 Vdc
±2%
2.4 Amperes
3-123
diagram number 7119455. The rectified voltage is regulated to +15 Vdc by seriespass transistor A7Q2. Zener diode A6CR6 provides the nominal 15 volt reference
for the base of A7Q2. After the supply is in operation, the bootstrap voltage is
overridden by the nominal 20 volt operating voltage derived from dc-de converter
output winding A5T2-A29-A3l. The output is rectified by diodes A6CR7 and A6CR8,
and filtered by series resistor A6R6 and shunt capacitor A6C12. In addition to
being used for control circuit operation, this voltage is sensed by the feedback
voltage regulator to detect output voltage errors.
3-173. The internal +5 Vdc power furnished to the integrated circuits is derived
from the +20 Vdc bus by integrated regulator circuit A7Ul. The +20 Vdc input is
applied to A7Ul-Pin 1. The +50 Vdc output appears at A7Ul Pin 2, and is filtered
by capacitor A6Cll.
3-174. Switching Regulator Control Circuits. The switching regulator control
circuits develop and control the drive supplied to the switching regulator. These
circuits consist of an oscillator pulse width modulator, toggle flip-flop, feed
forward and feedback voltage sensors, and a driver circuit. They appear in the
control card schematic diagram, number 7119455, and are shown in the simplified
block diagram, figure 3-55.
3-175. The oscillator is composed of cross-coupled one-shot circuits A6UlA and
A6UlB. It produces a 22 KHz single-phase square wave output. The oscillator
waveform is shown in figure 3-56. The oscillator output appearing at A6UlB-Pin 9
is applied to toggle flip-flop A6U8-Pin 12 and from A6UlB-Pin 16 to pulse width
modulator A6U7-Pin 16. J-K toggle flip-flop A6U8 converts the single phase oscillator signal to a two-phase signal for the pulse width modulator control circuit
and the switching regulator driver. The toggle flip-flop outputs appearing at
A6U8-Pins 6 and 8 are applied to pulse width modulator A6U9-Pins 4 and 9.
3-176. Voltage comparator A6U6 provides feedback voltage regulation which corrects
for dc-de converter output voltage errors. The comparator senses voltage errors
on the +20 Vdc operating bus and responds by providing a correction voltage to
A6UlA-B to increase or decrease the oscillator frequency. A6U6 samples the +120
Vdc bus via the voltage divider comprised of A6R23-R39-R3l, and output voltage
control potentiometer A6R38. The voltage sample is compared with an internally
developed reference voltage, with the resultant error voltage supplied to the
oscillator as a frequency control bias vOltage. This voltage appears at A6U6Pin 10 and i~ applied to the oscillator via A6CR19 and A6R2.
3-177. A pulse width modulator circuit provides feed-forward regulation that
corrects for input voltage errors. It consists of pulse width modulator control
one-shot A6U7 and pulse-width modulator gate A6U9. A voltage sample from the
+150 Vdc switching regulato,r input is dropped to a lower level by resistors A6Rl
and R5 and zener diode A6CR9, and is applied as a control bias to one-shot A6U7Pin 14. Variations in the sampled voltage cause corresponding variations in the
width of the output pulse produced by A6U7. This variable width pulse is applied
to pulse width modulator gate A6U9-Pins 5 and 10. where it is "anded" with the'
constant pulse width oscillator signal to produce the pulse-width modulated output.
Figure 3-57 shows the pulse width modulator waveform. The A6U9 output can also
be inhibited by an overcurrent or overvoltage shut-down signal as explained in
paragraphs 3-185 and 3-186.
3-178. The pulse width modulator applies an alternating base drive to switching
regulator driver transistors A6Q3 and Q5 via current limiting resistors A6R25
3-124
FEEDBACK VOLTAGE SAMPLE
FROM 20' VOLT
OPERATING
BUS
UNREGULATED
+150 VDC
OVERCURRENT/
OVERVOLTAGE
SHUTDOWN SIGNAL
REFERENCE
ADJUST
BASE Cl)8RENT
WAVEFORMc
5l--l, /
FREQUENCY CONTROL VOLTAGE
OSCILLATOR
(A6U1A, U1B)~-----;!
)'
FREQUeNCY ~22KHZ
3 VOLT SINGLE
PHASE OUTPUT
vee
\
Jl
PULSE
WIDTH
MODULATOR
GATE
(A6U9)
u
7'
+~5CI
WIDTH SIGNAL
n
J-K
TOGGLE
FLIP-FLOP
(A6UB)
r-L
VARIABLE PULSE-
TWO-PHASE
OUTPUT
FEED FORWORD ERROR
VOLTAGE
_---IV
FEED-FORWARD VOLTAGE
SAMPLE FROM SWITCHING
REGULATOR OUTPUT
"
Ca...UTAT
DIODE
PULSE WIDTH
CONTROL
PULSEWIDTH
CONTROL
ONE-SHOT
(A6U7)
+20 VDC SWITCHING
REGULATOR DRIVER
FOLDBACK CURRENT
LIMITING SIGNAL
Figure 3-55.
Switching Regulator Simplified Block Diagram
REGULATED +9OVOC
TO CHOPPER
~3V
"
If'~----SEE
NOTE:
NOTE ---~>I
NOMINAL OSCILLATOR FREQUENCY IS 22 KHz MEASURED AT CIRCUIT
A6UlB-PIN 10.
Figure 3-56.
Switching Regulator Oscillator Waveform
and R34. Q6Q3 and Q5 are coupled to the base of switching regulator transistor
A7Ql (schematic diagram 710840) via transformer A6T2. Figure 3-58 shows the waveform of this base drive current.
3-179. Series-pass transistor A7Ql functions as a switching mode voltage regulator.
The signal driving it is both pulse width modulated and varied in frequency to control its duty cycle. The +150 Vdc output from the prime power rectifier is applied
to the collector and a regulated dc output of approximately +90 volts is derived
from the emitter. An inductor-capacitor averaging filter consisting of choke Ll
and capacitors AlC2 and AlC3 follows the transistor to filter the dc output.
Commutating diode A7CR5, connected across the transistor emitter, bypasses negative
voltage excursions occuring during transistor off times as a result of the action
of choke LI.
3-180. DC to DC Converter. A dc to dc converter produces the power supply output
voltages from the regulated +90 Vdc. The converter consists of an oscillatordriver (chopper) circuit, a transformer, and output rectifiers and filters.
3-181. The converter drive signal is developed by an 11 KHz oscillator comprised
of cross-coupled one-shots A6U2A and A2B, shown in schematic diagram 7119455, and
in the simplified block diagram, figure 3-59. The oscillator output has a waveform
as shown in figure 3-60. It is applied to J-K flip-flop A6U3-Pin 12, which toggles
to convert the single-phase oscillator output to a two-phase output appearing at
pins 6 and 8. The output from the J-K flip-flop drives shut-down control Gate A6U4,
which inhibits the converter drive signal during an overcurrent or overvo1tage
3-126
NORMAL DUTY CYCLE IS~ 60%
AN INCREASE IN SUPPLY LOAD
CAUSES WIDlli OF "ON" TIME
PULSE TO DECREASE.
~ENOT~
I
~1
,--
~2
::!.3
fI
VOLTS
l
NOTES:
I- _
1-I
1
SEE NOTE 3
I
I<
SEE NOTE 2
~
~
1)
PULSES ARE MEASURED AT PULSE WIDlli CONTROL GATES, PINS 6 AND 8 OF
INTEGRATED CIRCUIT A6U9.
2)
OPERATING FREQUENCY UNDER NORMAL LOAD IS APPROXIMATELY 22 KHz.
3)
WAVEFORMS FOR BOlli PHASES SHOULD BE NEARLY SYMMETRICAL IN BOlli
AMPLITUDE AND WIDTH.
Figure 3-57.
Pulse Width Modulator Voltage Waveform
3-12'
A--
T
,- 0.6
AMPERE
NOTE:
THE WAVEFORM IS MEASURED ATTIIE BASE OF A7QI WITH A CURRENT PROBE.
DUTY CYCLE UNDER NORMAL LOAD IS APPROXIMATELY 60%.
Figure 3-58.
THE
Switching Regulator Base Drive Current Waveform
condition, as explained in paragraphs 3-185 and 3-186. The A6U4 output, pins 6
and 8, is applied to the bases of chopper driver transistors A6QI and Q2 via
resistors A6R7 and R13. The chopper driver transistors provide the alternating
drive signals to chopper transistors A7Q5 and Q6 via transformer A6Tl. Figure
3-61 shows the chopper transistor collector voltage waveform.
3-182. The nominal +90 Vdc output from the switching regulator is changed to an
alternating 70ltage via the chopper circuit. This enables voltage conversion via
a transformer and provides isolation from the ac power source. Referring to
schematic diagram number 7101840, the dc input is switched via transistor pair
A7Q5-A7Q6 which are coupled in push-pull parallel to the primaries of transformers
A5Tl and A5T2. The alternating drive signals applied to the bases of the transistors
are constant in both frequ~ncy and pulse width and provide 100% duty cycle operation. An emitter reSistor, A4Rl, is used with the transistor pair to balance the
transistor currents and provide a means of detecting overcurrents by sensing the
voltage drop across the resistor. The output voltages are determined by the
transformer primary-to-secondary turns ratios. Each output voltage from the chopper
transformer secondaries is full-wave rectified and the resulting dc filtered by an
inductor-capacitor averaging filter. As a typical example, the +5 Vdc memory
output, schematic diagram 7101840, is produced from secondary windings A588-C5-8l4
and rectified by A7CR8 and CR9, then is filtered by series inductor A2L2 and shunt
capacitors A2C5 through C8. After filtering, the dc voltage outputs are supplied
to the DPS logic and memory circuits.
3-128
~~VOL~
Z3VOLTS
OSCILLATOR
(A6U2)
&-_ _ _.--;=111
Sl
n
1lL
SHUT·
J·K
TOGGLE
FLIP·FLOP
(A6U3)
/
"X 3 VOLTS
A6T1
DOWN
CONTROL
GIITE
(A6U4)
li
FREQUENCY ~ 22KHZ
~3 VOLT SINGLE
PHASE OUTPUT
OVERVOLTAGE/OVER·
CURRENT SHUTDOWN
CONTROL SIGNAL
+20VDC
+90 VDC
TO
RECTIFIERS
FILTERS
-----I
A5T2
r
l
Figure 3-59.
Converter Oscillator-Driver and Chopper Circuit Simplified Block Diagram
SEE NOTE
NOTE:
WAVEFORM MEASURES AT A6U2B, PIN 9.
Figure 3-60.
I<
+40V ~
FREQUENCY IS ~ 11 KHz.
Chopper Oscillator Voltage Waveform
SEE NOTE
-----?/
~-------t
+20V ---------" - - - - - -
I- - - -
-
-
+2V ~ '---------'
NOTE:
WAVEFORM MEASURED AT COLLECTORS OF TRANSISTORS A7Q3 AND A7Q5.
FREQUENCY IS 11 KHz.
Figure 3-61.
3-130
Chopper Transistor Voltage Waveform
NOMINAL
3-183. Overcurrent/Overvoltage Sensors. The overcurrent/overvoltage sensors
consist of a foldback current limiting circuit, an overcurrent shut-down circuit
and an overvoltage shut-down circuit. These circuits appear in the control card
schematic diagram number 7119455.
3-184. The fo1dback current limiting circuit limits the maximum inrush current
through the switching regulator during start-up. Figure 3-62 shows the typical
starting current ramp and resulting overshoot when power is initially applied and
the foldback circuit is operating. The voltage developed across chopper transistor emitter resistor A4Rl (schematic diagram 7101840) is applied to pins 4 and 6
of comparator A6U10 on the control card (schematic diagram 7119455). A6U10 is connected to operate as a trigger, and when the applied voltage reaches a critical
value, approximating a 50% overload, the output appearing at pin 9 switches from
a low to a high level. This signal is applied to inverter A6UII. The output of
A6Ull at pin 8 is then low, and is applied to pulse width modulator A6U7-Pin 13
as an inhibit signal. Thus, the pulse width modulator is alternately inhibited
and released during the starting phase to limit the duty cycle of the switching
regulator until the chopper current requirement stabilizes.
MAXIMUM
-STARTING
--------
6 VOLT
OVERSHOOT
NOMINAL
OPERATING
CURRENT
CURRENT
MINIMUM
CURRENT
~~-:::::.-
'--
-
--_._. _. -
1<'
NOTE:
-- -
-- ---- -
-
-I
0.5 SEC
CURRENT MEASURED WITH CURRENT PROBE AT COLLECTOR OF SWITCHING REGULATOR
TRANSISTOR A7Q1.
Figure 3-62.
Input Starting Current Ramp
3-131
3-185. An overcurrent circuit operates to shut down the power supply by inhibiting
chopper and switching regulator drive signals if the supply load exceeds approximately 200% of maximum rates value. The overcurrent condition is detected by a
sense line monitoring the net average of chopper transistor collector voltages
at the junction of resistors A6R15 and A6R79. If the chopper circuit is overloaded,
these voltages will become unbalanced, due to one or the other chopper transistor
dropping out of saturated operation. When the overload is sufficient to cause
this voltage to rise approximately 8 volts, the voltage rise on the sense line will
set flip-flop A6Q7-Q8 via zener diode A6CR33 and the base of A6Q7. The flip-flop
output then appears as a low at pins 2 and 12 of pulse width modulator control
gate A6U9 and pins 5 and 10 of chopper circuit shutdown control gate A6U4. With
these gates inhibited, drive signals are effectively removed from the switching
regulator and chopper circuit, thus stopping power supply operation. The flip-flop
will remain set until input power is temporarily removed, permitting it to reset.
3-186. An overvoltage senSing circuit utilizing zener diode A6CR25 monitors the
+90 Vdc switching regulator output and causes flip-flop A6Q7-Q8 to set if this
voltage rises to a value between 105 and 115 volts, due to a long-term input power
transient. The effect of setting the flip-flop is identical to that described
for an overcurrent condition, paragraph 3-185.
3-187. Power Interrupt Generator. A power interrupt generator samples the +150
Vdc input voltage bus and generates a power interrupt signal if the voltage falls
to approximately +97 Vdc. This signal warns the processor of an incipient power
failure. The circuit, shown in schematic diagraM 7119455, is comprised of voltage
comparator A6U12, solid-state relay A6Fl, and a driver transistor contained in
circuit A6Q9? A voltage sample from the +150 Vdc bus is applied to pin 5 of A6U12
via the wiper arm of adjustment potentiometer A6R55. The circuit output drives
solid-state relay A6Kl. The relay output drives the output transistor contained
in A6Q9, pins 8, 9, 10. The output signal is normally high (+5 volts) and switches
low (+0.25 volts) when active.
3-188. Master Clear Generator. The master clear generator, shown in schematic
diagram 7119455, senses the +5 Vdc supply output and generates a master clear signal
if this output falls to +4.7 Vdc or less. A voltage sample from the +5 Vdc bus is
applied to voltage sensor circuit A6U13-Pin 5 via the wiper arm of adjustment potentiometer A6R59. When the voltage drops below the set tolerance the circuit
output, pin 3, drives a dc-coupled transistor pair, circuit A6Q9-Pins 1, 2, 3, and
5, 6, 7, which provides the master clear output signal. The signal is normally
high and switches low in the active state.
3-189. 15 Vdc Regulator. The +15 Vdc Memory voltage is regulated within ± 2% by
a linear series-pass regulator. The regulator consists of sensor-comparator circuit A6U5, schematic diagram 7119455, and series-pass control transistors A7Q3 and
Q4, schematic diagram 7101840. Circuit A6U5 compares a sample of the +15 volt
output with an internal reference voltage and provides an analog control signal
at pin 10 which drives the bases of A7Q3 and Q4. The control signal varies in
response to output voltage errors. The regulated output appears at the emitters
of A7Q3 and Q4. An external sense line connected to A6U5-Pin 4 via A6R30 and adjustment potentiometer A6R29 permits the regulator to compensate for temperature
within the core memory via a thermistor located in the core memory stack.
3-190. POWER DISTRIBUTION. The power distribution schematic diagram, figures
OOOA and B in Chapter 9,shows ac and de power routing within the DPS and provides
terminal, switch t indicator and relay connection data.
3-132
3-191.
OPERATIONAL DESCRIPTION.
3-192. The following paragraphs are an operational description of the DPS. The
description covers the jOint operation of the hardware and firmware (microprogram).
The DPS has a master clock that provides two pulses: a phase early (~e) and a
phase normal (~n) pulse. These two timing pulses and the program of micro instructions are used to execute macroinstructions and to process I/O transfers and interrupts. The micro program consists of many short subroutines that provide control
to execute each macroinstruction or control function. Thus, the micro program
replaces hardware generated timing sequences and discrete control signals. The
following paragraphs describe the basic sequences,
3-193. MACROINSTRUCTION EMULATION. The macroinstruction emulation sequence is the
basic sequence that determines the operation to be performed next. Figure 3-63 is
a flowchart of the macroinstruction emulation sequence. This sequence starts with
an Emulate Start microinstruction. (Most micro program subroutines end with this
instruction, thus returning to this sequence.) At this time, I/O requests and
micro interrupt requests are honored in priority order, If a request is present,
a hardware generated address is loaded into the micro P register to branch to an I/O
transfer or micro interrupt subroutine (see table 3-33). (The I/O transfer sequence
is described in paragraph 3-194 and micro interrupt sequence is described in paragraph 3-197.) When a request is not present, the next step is to check the Next
Instruction Resident (NIR) bit. NIR indicates that a memory request for the next
macroinstruction had been made previously. If NIR is not set, a memory request
is initiated to fetch the next instruction. Hardware generated address 2748 is
loaded into the micro P register to branch to the instruction read subroutine. The
first microinstruction of the subroutine transfers the contents of the memory data
register (MDR) to the instruction regis ter (IR), however, if the "Data Available"
signal has not been received from memory, the master clock is stopped until the
signal is received. (The master clock is disabled when there is a memory reference
and the S-field bits 0 and 1 equal 112.) In this case, the source was MDR (S=OOll).
After the signal is received, the instruction is gated into IR. The next microinstruction in the subroutine is an Emulate Branch 1. I/O requests present at this
time will be honored. With no I/O request present, the emulator control word (ECW)
bits 9 through 12 are interrogated. If ECW I (bit 11) equals 1, a hardware generated address is loaded into the micro P register to branch to an Interim sequence
(see table 3-34). The Interim sequence is used for instructions with RK or RX
formats. The end result of the Interim sequence is to place the operand in A6.
The Inte~im sequence ends with an Emulate Branch 2 microinstruction. I/O requests
present at this time will be honored. When no I/O request is present, ECW is checked
for overlap (ECW bit 10 = 1 and bit 12 = 0) and unary (ECW bit 9 = a and bit 12 = 0),
If overlap, a memory request is initiated to fetch the next instruction. If unary
instruction, the ECW pOinter is modified by the m-field. The ECW pointer (bits 0-0)
and IR bit 15 are gate~ to the micro P register to branch to the macroinstruction
subroutine. IR bit 15 increases the pointer addreSSing capability to 17773; thus,
subroutines for instructions 40 through 77 are at micro program addresses above
10008'. If the macroinstruction :is illegal, the PRClG FAULT indicator is set and the
Class II interrupt is processed. If Class II interrupts are locked out, the computer is placed in the console mode (Prog Run flip-flop cleared). For legal instructions, the macroinstruction subroutine is executed. Long subroutines allow I/O
transfers at specified intervals. The subroutine ends with an Emulate Start microinstruction which starts another emulation sequence.
3-133
EMULATE
ST",eT
__..___ ..__..-1
.....
~----------.-----------.
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'..,
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3-"
YES
Figure 3-63.
3-134
Macro Instruction Emulation
~"""I>(
IoIfMtW TD
:r".s'f""''t'""
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ScQ .... NC..
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R e Cit'1A
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Figure 3-64.
I/O Transfer Between Macro Instruction Execution
3-139
-~ :t/:-J
: Sl(flw(H TO
i
;r",p\4T
i (. to. I(IUI
Plt.sS
::l
1\ 1)f'. ~ "!> 10)
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.----.-.-.I.-
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D,,1"JI\ "',
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Figure 3-65.
3-140
I/O Transfer That Interrupts A Macro Instruction
./0
mA~FE...
\&~~NG"
\'E'1W&& IJ l\ot~clU\
~"'ST· S'1'E'<.vn.r.))
see- 1<.6. 3-H
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Figure 3-65.
'"
I/O Transfer That Interrupts A Micro Instruction (Cont)
3-141
,
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7
;'
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--- - - - -.-.- - - ·---------·---··---l
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Figure 3-66.
Micro Interrupt Sequence (Cont)
3-143
.,,~-
----~-
J
Figu re 3-66.
3-144
Micro Interrup t Sequence (Cont)
~
,., \ r I 1'\1" E
Mli-M()fl."f
c..tte-i\O~
, -_ _ _- - A J . -_ _""'"
r{ 0
'1'ltuIS~
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NelS
t'.t ..1'H.tLuPfS)
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se.':,.l-'';
c.o~nHN.S
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(A').t, ..... "7
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Figure 3-66.
Micro Interrupt Sequence (Cont)
3-145
CH~IN
Ab ... ·
pel NTf;(t ~ Mr\ft ;
!
i
._....._....... .1
I
EM lll..,..,.S-
I
.s"'}I\~1
:r::-t-JI""~&
tA& M oa..y
L._--.--_
"TD ell.,,,,
SIZ"''''(~
rl.u.1'. ~E~~ ~ E~.
CM ICl.O A nCl.S ~ I ~
\...--
(~5Ab)
I
J
I
(.L-ASS
t.L..GI\j(
rw'T.
A
t-J b
xr
'fE'S
C~AIN
REQ\.l&''i.T'
I
I
~oo ~
Ao
L.
Figure 3-66.
3-146
Micro Interrupt Sequence (Cont)
'(e-5
:tI 0 l' It" a.t\f'E tl.
S e~"'6-t\l(,6'
\
L~e.r1"&'C.""""'"S) t--~
~e ..
"'",1>-£(
~"'\"TI~"e
MeMO{lJj
RSGl",es. r
~t.I''tIl\T6'
.r--....I
MfrM"iC.-,(
Ii!.~&~ T'
s.eT
Figure 3-66.
".., I>
N,/fe
Micro Interrupt Sequence (Cont)
3-147
Figure 3-66.
3-148
Micro Interrupt Sequence (Cont)
8 ~~NC Ii
To
c.o IIISOI.. M1>1) If
SE-4»UE~E
(."""~~ "bItS 1.14)
(Co NSOL Ii /VI 00 e
5 WITGli4f.s' -i" A 0
l t> \ ~ ~I..'- '1'
?--o
NIA~U~
:SWl'tc.tl&s)-+ A I
(A&..Te-1C ,MO\)S
afr) -",.5
-I
l6-R)~A4-
~
'--_ _ _ _ _ _ JI
Figure 3-66.
Micro Interrupt Sequence (Cont)
3-149
T
I (SH~~r~; ----;
No (c.L.It)
NO
""'Obi f:1 e 1)
~A4
is s e
liO c. c.LJl)
NO
~
r-·-··----- ,. ",
Mobl FI e D
~
1''
.1)
tJ 01'&
!
_ _ _ _~
[M
-::;,-;-r
DII1''''
I
1.)
I
II 4-
i-'
_-J
I
(SSE- tvoTf'
tJOT&' :
I.
a/T'
SEl.BcTlII'''''' SS-T
C.oft.~H-PClA/b' N6- ;0
SIN
~.
Ifc.t1ES
f!.E.rrr~tz( Jftrli
f>r{tss,SD ON
p~"EL.
grt.S seUcTlvC,y ''''' cARE,.
c.ot~SPC~I)fN"
T" fU.&4.(Mtj Dftr"
SvHTCHSI" p~e.ssE I) "tJ flor1" 11. •
Figure 3-66.
3-150
Micro Interrupt Sequence (Cont)
YES
(""') -...
SEt.E(.T~
Re-~Isre.e
.------....- .._-
I
Figure 3-66.
Micro Interrupt Sequence (Cont)
3-151
x. NSSR.T
MEMott~
I!>riS'.IN S1'1I1'US 2.
_ _ _ --r-_ _ _
.J
!-------r--;
I
,--- ..+------"I
f
r---'
• ~ Nie.-.~\1. ... \'i
•
t..o~6- ~ '" 0
:
!
(r'\
0')':;:" S 11fTttS !
;(. ~G&-'\T8/2.
I
~-,,-'
1'----.
ll\o)~
A2.
"''''
/"
/ / eL.MS 3 '"
~wr'UVfT'
, (s'n\iUS f R&&)
,,/'
......
- - + A7
.,'
"'-"
_-___J~:._!
.
; 1"\6-t'I 91"H -.,
~o
~5"'5n'i ( ~\,\R.13-fs)i
1'1«''' C ow"TJI\INeO I PI I
aF ~ Alf c..:ll
''''5 .. -,
IZO-..A1
A IV 'b M
C.L~SS
"It
I
I"CI-EII! ~ . _ - - \
t ...-'11itT-'-IA-"s,--;l.-f;~
r---
~
~-.-.-
C~(
4--"
I
A"
I
c. .....,~ ~ M ••a.:lt
j
~)jTe-tl.fZ.VPTS
!
~---~------.
-
till'
I
r-··--C-a..-e;:--fI\-(l.----.!
I
teulo}
(;0 1'0
1'30--+ A7
&rTS
"Nl
c L-tnft'2-
CL.~SS
I: It N~ .Jr
.z; N Tcnrf "PT.$
'1"0 ('01'''''•.
~""'6\
__"v Pf"
U61"""'~f'
Figure 3-66.
3-152
Micro Interrupt Sequence (Cont)
Table 3-35.
Micro Branch Conditions For General Display
DSPL NUMBER
SWITCHES
3210
ADDRESS LOADED IN
MICRO PREG (OCTAL)
REGISTER OR
ROUTINE SELECTED
0000
2000
P Reg
0001
2004
Status #1 Reg
0010
2010
Status #2 Reg
0011
2014
RTCL
0100
2020
RTCU
0101
2024
Breakpoint Reg
0110
2030
I/O Control Memory
0111
2034
Page Address Reg
1000
2040
Main Memory (P Reg
contains address)
1001
2044
Output Data
1010
2050
Monitor Clock
1111
2036
Load j.LP Reg
3-199. The Load Interrupt (activated by the LOAD switch) starts the computer
executing the bootstrap load program stored in NDRO memory.
3-200. The I/O Chain Interrupt executes a macroinstruction in the I/O chain and
updates the chain address pointer.
3-201. The Not Run Interrupt places the DPS in the console mode. This allows
the, operator to moni tor or change the contents of registers from the panel.
3-202. The Class I, II, and III Interrupts are macro interrupts (see paragraph
3-58). The micro program subroutine stores the contents of the P, Status Register
#1, Status Register'#2, RTCL, and RTCU registers in the assigned main memory
locations (see Appendix D) and 'loads the P, Status Number 1, and Status Number' 2
registers. The P register contains the starting address of the interrupt subroutine stored in main memory.
3-203.
LOGIC DEVICE DESCRIPTIONS
3-204. Appendix E describes the logic devices used ~n the logic and memory circuit
cards in the DPS. In most cases, the logic devices are contained in dual-in-line
packages (DIP's). The descriptions of these devices are a valuable aid in understanding the logic schematic diagrams of Chapter 9 (Volume II) on which these logic
devices appear in symbolic form.
3-153/(3-154 blank)
CHAFTER 4
PREVENTIVE
4-1.
MAINT&~ANCE
INTRODUCTION.
4-2. Preventive maintenance (PM) encompasses the procedures to be followed by DPS
operators or maintenance personnel to keep the equipment in optimum operating condition and to prevent a decline of productive use. Table 4-1 provides an index to
the DPS PM procedures, which consist mainly of cleaning, of switch and indicator
checks, and of performing a diagnostic/confidence test program. The PM procedures
should be performed by a Data Systems Technician Second Class or equivalent. The
procedures should be performed at regularly scheduled intervals; the frequency of
the intervals may vary dependent on the operating schedules necessary to meet productive requirements. Where the DPS operates continuously, operation should be
discontinued at least once a week for PM. Where DPS operation is on a daily on/off
basis, the diagnostic program or other test program should be run daily as a confidence check; the other PM procedures should be performed as scheduled. The
diagnostic test program is documented in Volume 3 (Chapter 10)* of this technical
manual. If the diagnostic test program is not aVailable, the Factory Acceptance
Test or similar confidence test program may be used. The scheduled maintenance
instructions in this manual are cancelled when the Planned Maintenance System (PMS)
is implemented for this equipment aboard your ship or station.
*Not available at time of this publication.
Table 4-1.
Preventive Maintenance Index
PERIODICITY
MAINTENANCE ACTION
REFERENCE
MR*
Clean Air Filter
Paragraph 4-4
SR*
Clean Cabinet
Paragraph 4-5
M
Test Indicators
Paragraph 4-6
DR**
Run Confidence Test
Paragraph 4-7
D = Daily
W= Weekly
M = Monthly
Q = Quarterly (3 mo.)
S = Semiannually (6 mo.)
A = Annually (12 mo.)
R = As specified
*More or less often depending on environmental conditions.
**May be less often, if required by system operating schedules.
4-1
4-3.
PREVENTIVE MAINTENANCE PROCEDURES.
4-4. AIR FILTER CLEANING. The front panel air filter is the only item that
requires regular attention. It should be cleaned monthly or when necessary by
vacuum cleaning or washing in a soap or detergent solution. To remove and clean
the air filter, use the following procedure. See figure 4-1.
1.
Ensure power is turned off.
2. Remove eight front panel retaining screws (Figure 4-1), using a 5/32 inch
All en wrench.
3.
Swing front panel open.
4.
Remove two filter retaining screws (Figure 4-2), using screwdriver.
5.
Vacuum the filter.
If filter is to be washed:
a.
Clean filter thoroughly in hot, soapy water.
b.
Rinse, wipe with clean cloth, and vacuum dry.
6.
Replace filter and filter retaining screws.
7.
Swing the front panel closed.
8.
Replace the eight front panel retaining screws.
4-5. CABINET CLEANING. Semiannually, or as required, the cabinet should be
cleaned and visually inspected. See Figure 4-2. Electrical checks and adjustments,
if required, can also be made at this time.
CAUTION
Use of forced air for cleaning is not recommended, since it may force
dirt particles into critical areas, Use care not to damage or disturb
wiring or components.
1.
2.
4-4.
Ensure power is turned off and power cable disconnected.
Open the front panel of the DPS as listed in steps 2 through 3 of paragraph
3. Using a soft bristle brush and a vacuum cleaner, clean the inside of the
front panel door and the exposed side of the memory drawer.
4. With Phillips screwdriver, disengage four quick-release memory chassis
fasteners. Pullout the memory chassis assembly and swing it open to the left.
Vacuum the memory chassis.
5.
Remove the power supply, following the removal procedure listed in Chapter 6.
6. Vacuum the cabinet space used by the power supply, the power supply itself,
and the front of the individual circuit card modules, being careful not to damage
components.
4-2
EXHAUST
VENTS
TOP
PANEL
FRONT
PANEL
R (2)
FASTENE
IN T A K E
ER
A IR F IL T
VENTS
FRONT
PANEL
R (2)
FASTENE
FRONT
PANEL
DOOR
Figure 4 - 1 .
FRONT
PANEL
R (2)
FASTENE
View
t, Overall
DPS C a b in e
4 -3
MEMOR Y
EXHAUS T
BLOWER
MEMOR Y CHASSIS
FASTEN ERS
(2; 1 HIDDEN )
POWER
SUPPLY
FRONT
PANEL
FASTEN ER
HOLES (2)
MEMOR Y
CHASSIS
FASTEN ER
HOLES (2)
MAINTE NANCE
PANEL
MAINTE NANCE
PANEL
FASTEN ER
FILTER
RETAIN ING
SCREWS
(2 HIDDEN )
MEMOR Y
DRAWE R
Figur e 4-2.
FRONT
PANEL
FASTEN ER
HOLES (2)
REMOV AL
HANDLE
DPS Cabin et" Front Panel Open
INTAKE
AIR
FILTER
7.
Vacuum off the exhaust vent filters.
8. Visually inspect electrical components for discoloration and evidence of
overheating.
9. Check terminal connections for security and insulation for cracks or
deterioration.
10. Make necessary corrections for any defects discovered in the foregoing
inspections.
11.
Replace the power supply per procedure in Chapter 6.
12.
If power supply voltages are to be cfiecked, follow procedure in Chapter 5.
13.
Replace and fasten the memory drawer.
14.
Close and fasten front panel.
15.
Replace power cable and apply power.
4-6. CONTROL AND MAINTENANCE PANEL INDICATORS. Table 4-2 provides a list of
the DPS indicators and a method of testing them. See Figures 2-1 and 2-2.
Table 4-2.
PANEL
IDENTIFICATION
Control and Maintenance Panel Indicators
FUNCTION
TEST
Control
BLOWER POWER
Indicator
When lit, indicates
blower power is applied
and enabled.
Ensure power cable is connected and CIRCUIT BREAKER
is ON. Place BLOWER POWER
switch in ON position.
Control
LOGIC POWER
Indicator
When lit, indicates
logic power is applied
and enabled.
Ensure power cable is connected, CIRCUIT BREAKER is
ON, and BLOWER POWER is ON.
Place LOGIC POWER switch in
ON position.
Control
POWER FAULT
Indicator
When lit, indicates a
Power Fault Interrupt
has occurred. Cleared
by POWER FAULT CLR
switch in CLR position.
See figure 4-3 for test setup. Reduce input voltage
until FAULT indicator lights.
Return voltage to correct
level and clear fault.
Control
PROGRAM FAULT
Indicator
When lit, indicates
the DPS has attempted
to execute an illegal
instruction. Cleared
by PROGRAM FAULT CLR
switch in CLR position.
Refer to Chapter 2, Operation,
and manually set in and
execute an illegal instruction. Then clear the indicator.
4-5
Table 4-2.
PANEL
Control and Maintenance Panel Indicators (Cont)
IDENTIFICATION
FUNCTION
TEST
CONTROL
PROG RUN
Indicator
When lit, indicates DPS Refer to Chapter 2 and start
is exeeuting instrucDPS executing instructions in
tions in RUN mode.
RUN mode.
Control
OVER TEMP
Indicator
When lit, indicates DPS Place the ALARM ENABLE/DISABLE
internal cabinet air
TEST switch in the TEST potemperature is within
sition. OVER TEMP indicator
25 0 F of the maximum
lights and ALARM sounds.
temperature at which
the DPS can operate
without component
damage.
Control
ALARM (Audible)
Indicator
When sounding (ALARM
ENABLE/DISABLE/TEST
switch in ENABLE
position), indicates
DPS internal cabinet
air temperature is
within 25 0 F of the
maximum temperature
at which the DPS can
operate without component damage.
Place the ALARM ENABLE/DISABLE
TEST switch in the TEST position. ALARM sounds and OVER
TEMP indicator lights.
Control
BATTLE SHORT
Indicator
When lit indicates
BATTLE SHORT switch is
in the ON position
(which disables DPS
overtemperature shutdown function).
Place BATTLE SHORT ON/OFF
switch in ON position.
Maint.
PROG RUN
Indicator-switch
When lit, indicates
the DPS is executing
instructions in the
RUN mode.
Refer to Chapter 2 and start
DPS executing instructions
in the RUN mode.
Maint.
POWER FAULT
Indicator-switch
When lit, indicates a
Power Fault Interrupt
'has occurred. Pressing the indicator-switch
clears the POWER FAULT
indicator,
See figure 4-3 for test setup.
Reduce input voltage until
indicator lights. Return
voltage to correct level and
clear fault.
Maint.
PROG FAULT
Indicator-switch
When lit, indicates the
DPS has attempted to
execute an illegal instruction. Pressing
the indicator-switch
clears the PROG FAULT
indicator.
Refer to Chapter 2, Operating
Instructions and manually set
up and execute an illegal
instruction.
4-6
Table 4-2.
PANEL
Control and Maintenance Panel Indicators (Cant)
IDEN TI FICA TI ON
FUNCTION
TEST
Maint.
PROGRAM STOP
Indicator
When lit, indicates a
program stop condition
has been satisfied.
Refer to Chapter 2, Operation,
to set up a program stop.
Maint.
Time Meter
Indicates time in
hours that DPS logic
power has been applied
and enabled.
Apply logic power and observe
that meter advances.
Maint.
MICRO STEP MODE
Indicator-switch
When lit indicates IJ?5
is in Micro Step mode.
Pressing indicator
switch places DPS in
Micro Step mode.
Activate MICRO STEP switch.
To clear Micro Step mode
activate DISPLAY SELECT CLR
switch.
Maint.
OP STEP MODE
Indicator-switch
When lit, indicates DPS
is in Op Step mode or
in Micro Step mode to
execute a single instruction.
Activate OP STEP switch to
clear RUN mode and place DPS
in Op Step mode.
Maint.
RUN MODE
Indicator-switch
When lit, indicates DPS
is in Run mode or in
Micro Step mode to
execute successive instructions.
Activate RUN MODE switch to
clear Op Step mode and enable
Run mode.
REGISTER/DATA
When lit, displays contents of selected
register.
Set ALTER MODE SET/CLEAR
switch in SET pOSition and
press REGISTER/DATA SET/CLR
switch. To clear, set ALTER
MODE SET/CLEAR switch in CLEAR
pOSition and press REGISTER/
DATA SET/CLR switch.
When lit, as specified
in Table 2-3, indicate
REGISTER/DATA is displaying the corresponding register.
When lit, as specified
in Table 2-3, indicate
REGISTER/DATA is displaying the corresponding register.
When operated as specified in Table ?-3 these
switches cause REGISTER/
DATA to display the
corresponding register
contents.
Refer to Table 2-3. Operation
of anyone of MICRO ADRS,
MICRO INSTR, or NORMAL DSPL
causes the other two to clear.
Maint.
0-15
Indicatorswitches
Maint.
DISPLAY SELECT
MICRO ADRS
MICRO INSTR
NORMAL DSPL
INSTR REG
GENL DSPL
GENL REG
DISPLAY NUMBER
0-3 Indicatorswitches
Refer to Table 2-3. Operation
of anyone of INSTR REG, GENL
DSPL, or GFNL REG causes the
other twu to clear.
Press DISPLAY NUMBER indicator
switches 0-3. Observe that
they light. Press DISPLAY
SELECT CLR switch. Ohserve
that indicators extinguish.
4-7
115 VAC
1I0 liz
.
.,
'!I.
6
VARIAC
0
0
AC HIGIJ
AC COMMON
-TBI -
:0 2
~3
,
--
-,
,
POWEll
I
I
SUPPLY
,
__ J
*Ensure the correct voltage and frequency are used for the equipment under test.
Figure 4-3.
Power Interrupt (Fault) Test Setup
4-7. CONFIDENCE TEST. The diagnostic test program, documented in Volume 3 (Chapter
10), should be run daily, or as often as practical under the processing schedules,
as a performance test, to give confidence that the DPS is performing correctly.
This is the only performance test required for the DPS. It attempts to exercise
and test every DPS circuit and the micro control program, and to diagnose any
failure it detects. If the diagnostic test program is not available,* the Factory
Acceptance Test or similar program should be used; this will detect malfunctions,
but not diagnose them. The recommended procedure is to load and run the program at
the end of a computing day, and to run it again immediately after turning on the DPS
at the beginning of the next computing day.
*Not available at time of this publication.
4-8
CHAPTER 5
TROUBLESHOOTING
5-1.
INTRODUCTION.
5-2. Troubleshooting information and procedures for the DPS are based primarily on
the assumption that most malfunctions will be detailed and isolated through use of
the diagnostic test program* documented in Volume 3 (Chapter 10) of this technical
manual.
5-3. DIAGNOSTIC TEST PROGRAM. The diagnostic test is to be run regularly as part
of the normal preventive maintenance procedures; it should also be run as the primary troubleshooting tool whenever a malfunction is suspected or has been detected
by some other means. The DPS has three built-in fault detectors; overtemperature,
power out of tolerance, and program fault. Most faults, however, are first detected
by the diagnostic or other test program, and the procedures that are included in the
program documentation lead to isolation of the faulty circuit card or component.
5-4. MANUAL TROUBLESHOOTING. In some cases, where the nature of the fault is such
that it prevents the loading of the diagnostic test program or prevents the DPS
from successfully diagnosing itself, troubleshooting must be done manually. In
many cases, manual diagnosis can be performed by replacing circuit cards in the
suspected area with spare cards until the symptom disappears, or shifting multiple
usage cards from one location to another to see if the symptom shifts. Table 5-1
is a list of the multiple usage cards.
5-5. Sometimes it may be necessary to troubleshoot manually by stepping through
instructions in Op Step or Micro Step mode, observing the contents of displayed
registers or observing the status of individual signals on an oscilloscope, and
logically troubleshooting with the aid of the logic schematic diagrams in Volume 2
(Chapter 9) and the microprogram listing in Appendix C. The outer edge of all
logic circuit cards contains test points, where the major signals in that card
are available for checking. These test points are accessible with the maintena~ce
panel door and the memory chassis swung open.
5-6. TROUBLESHOOTING AIDS. Additional troubleshooting aids provided in this
chapter are the Troubleshooting Index, the Lamp and Relay Indexes, and the Protective
Device Index, Tables 5-2 through 5-5, respectively.
CAUTION
Turn power off before removing or replacing circuit cards.
5-7. MAINTENANCE TURN-ON. No special turn-on procedures are required for maintenance purposes. Follow the procedures given with the diagnostic test program in
Chapter 10 (Volume 3) or the operating procedures in Chapter 2.
* Not available at time of this publication.
5-1
Table 5-1.
Multiple-Usage Circuit Cards·
CARD NO.
TITLE
LOCATIONS
7092175
7092185
7125306
7125311
7125380
7125500
7126125
7126155
ALU
MICRO REG
I/O CONT MEM
P, BKPT, MAR
STATUS REG
SHFT MTRX
TWO BIT MULTIPLY
MEM IN1RFC
Bl1-14
A3-5
A20-23
C5-6
C13-l4
A9-1O
A7-8
C3-4
';'The IOC has addi tional multiply usage cards if it has several groups of channels
with identical interfaces.
Table 5-2.
5-2
Troubleshooting Index
Functional Area
Troubleshooting
Paragraph
Troubleshooting
Diagram
Functional
Description
Paragraph
Blowers
5-13
Figure 9-0008
N/A
Heat Sensors
5-14
Figure 9-000B
N/A
IOC
5-3 through 5-5
and 5-16
Figure 9-200
through 9-407.
Chapter 10
3-119 through
3-165
Logic (MPC and
Processor)
5-3 through 5-5
Figure 9-001
th rough 9-115.
Chapter 10
3-20 through
3-77, and
3-191
Memory
5-15
Chapter 9,
diagram 7101751399 through -461
3-78 th rough
3-118
Panels
5-12
Figure 9-000C
2-3 th rough
2-6
Power
5-~
Chapter 9,
Figure 9-000A
and B
7101840
7101875
7101880
7101885
7101990
1701995
7119455
3-166 through
3-190
through 5-11
Table 5-3.
Reference
Description
A2Kl
Functional Name
Power Supply Energizing Relay
Table 5-4.
Functional Name
AlDSl
AlDS2
AlDS3
AlDS4
AlDS5
AlDS6
AlDS7
Ba t tl e Short On
Temperature Warning
Program Run
Program Faul t
Power Fault
Logic Power
Blower On
A2DSl
A2DS2
A2DS3
A2DS4
A2DS5
A2DS6
A2DS7
A2DS8
A2DS9
A2DSlO
A2DS11
A2DS12
A2DS13
A2DS14
A2DS15
A2DS16
Prog Stop
Display Bit 00
Display Bit 01
Display Bit 02
Display Bit 03
Display Bit 04
Display Bit 05
Display Bit 06
Display Bit 07
Di splay Bi t 08
Display Bit 09
Display Bit 10
Display Bit 11
Display Bit 12
Display Bit 13
Display Bit 14
Display Bit 15
Program Fault
Power Fault
Program Run
Display Select 00
Display Select 01
Display Select 02
Display Select 03
General Register
General Display
Instruction Register
Normal Display
Micro Instruction
Micro Address
Run Mode
Op Step Mode
Micro Step Mode
A2DS18
A2DS19
A2DS20
A2DS22
A2DS23
A2DS24
A2DS25
A2DS26
A2DS27
A2DS28
A2DS29
A2DS30
A2DS31
A2DS35
A2DS36
A2DS37
)
Engineering
Voltage
Figure
Number
115 Vac or
240 Vac
9-000A
Lamp Index (See Paragraph 5-
Reference
Description
A2DSl7
•
Relay Index (See Paragraph 5-
)
Engineering
Voltage
Figure
Number
Neon
Neon
LED
LED
LED
Incand.
Neon
115 Vac
115 Vac
+5 Vdc
+5 Vdc
+5 Vdc
+5 Vdc
115 Vac
9-000A
9-000A
9-00OC
9-00OC
9-00OC
9-000C
9-000A
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-000C
9-00OC
9-000C
9-000C
Type
I/S.
I/S.
l/S.
I/S.
I/S.
l/S.
I/S.
l/S.
l/S.
I/S.
l/S.
l/S.
l/S.
l/S.
l/S.
l/S.
l/S.
l/S.
l/S.
l/S.
1/5.
l/S.
l/S.
1/5.
l/S.
l/S.
l/S.
l/S.
I/S.
l/S.
l/S.
l/S.
Vdc
Vdc
Vdc
Vdc
Vdc '
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
5-3
Table 5-5.
Reference
Description
AICBl
5-8.
Protective Device Index (See Paragraph 5-
Front Panel
Marking
Rating
Volts
AAffi
Circuit Breaker
)
Circuit Protected
AC Blowers, Alarm
Buzzer, Running
Time Meter, and
Power Supply
Figure
Number
9-000A
TROUBLESHOOTING PROCEDURES.
5-9. POWER. When troubleshooting the power circuits, check all primary power lines,
switches and other circuit elements to determine whether the source of trouble is in
the power distribution system or in the power supply itself.
5-10. Power Supply. If the power supply is suspected, use the voltage and test
point data given in table 5-6 to check for proper operation. In the event the power
supply is found defective, it must be exchanged with a replacement unit and returned
to the factory, since it is not a field repairable item.
5-11. Power Distribution. If ac power is not being delivered correctly to the
power supply, or if the power supply is operating correctly but dc power does not
reach its destination, use figures 9-00OA and B to check the ac and dc power
distribution.
5-12. PANELS. Panel functions are normally tested and diagnosed as part of the
regular running of the diagnostic test program*. If an individual switch or indicator is suspected; check its operation while measuring the voltage across its
terminals with a multimeter of oscilloscope. The maintenance panel is hinged at
the bottom and held by five screws. Opening it provides access to its wiring and
the control panel wiring. Control and maintenance panel wiring appears on figure
9-000C.
5-13. BLOWERS. If an individual blower stops operating, it may not always cause an
overtemperature fault, since air will be drawn through its chassis in a reverse
direction by the two operating blowers. To test blower operation, place hand at
each of the three air exhaust grilles on the left side of the cabinet to verify that
air is being exhausted. Or place a sheet of paper in front of each exhaust grille;
it will be repelled by the air flow from operaing blower and will be drawn against
the grille by air flowing backward through a non-operating blower.
5-14. HEAT SENSORS. Each chassis contains two thermostats: Sl which in each case,
is normally open and provides the overtemperature warning; and S2 which, in each
case, is normally closed, and provides the overtemperature cut-off. Figure 9-000B
shows the thermostats may be checked with a multimeter at terminal boards on each
chassis. Refer to table 5-7.
* Not available at time of this publication.
5-4
Table 5-6.
Power Supply Test Data
ITEM
TES T DATA
AC Input Power
Refer to power distribution schematic diagrams, figures
9-000A and B for applicable terminals for checking ac input
power at A2TBl behind the maintenance panel or PSITBI on the
power supply.
WARNING
Dangerous voltages are encountered in this check.
Vol tages should be 115 Vac ± "1'7<; for single phase power and
115 Vac + 5% for 3 phase power. Del ta inputs are measured
line to line and wye inputs line to neutral.
VOLTAGE/TOLERANCE
Logic Output
Voltages
TEST POINT
+5 Vdc -+ 5% Memory
+5 Vdc -+ 5% Processor
-5 Vdc -+ 5%
PSI-TB4-4
-5.2 Vdc ± 5%
PS I-TI33-3
+12 Vdc -+ 5%
+15 Vdc -+ 2%
PSI-TB3-3
-16 Vdc -+ SOlo
PSI-TB3-5
Table 5-7.
PSI-TB4-6
PSI-E9
PSI-TB4-2
Thermostat Test Point
WARNING
These terminals carry 115 Vac if power is turned on.
CHASSIS
A2 Memory
A3 CP/IO
PSI Power Supply
OVERTEMP ALARM
S 1 (NO)
OVERTEMP CUT-OFF
S2 (NC)
TBl-3,4
TBl-6,7
TB2-1,2
TB1-1,2
TBl-3,5
TB2-3,5
5-15. MEMORY. The memory has no test points to facilitate manual testing, because
it is thoroughly tested and diagnosed by the diagnostic test program, chapter 10,
and the diagnostic procedures accompanying the program. If the memory is suspected
and the diagnostic test program does not determine the trouble, it may be tested by
replacing circuit cards with spares, or by swapping the position of identical cards,
until the symptom disappears or shifts its position.
5-5
5-16. INPUT/OUTPUT. Diagnostic testing of the I/O circuits requires a special test
I/O mode card which is supplied with each DPS. This card must be inserted into the
DPS in place of the normal operational I/O mode card when running the diagnostic
tests. Refer to Volume 3 (chapter 10) of this manual for instructions on the use of
the special card. If manually troubleshooting the I/O circuits by replacing cards
in the suspected area with spare cards or interchanging the positions of identical
(multiple usage) cards, be careful to interchange only cards of the same type.
Cards which may be interchanged depend on the I/O options installed. In order to
be interchangeable, cards must be for the same type of interface and of the same
interface voltage level.
5-6
CHAPTER 6
CORRECTIVE MAINTENANCE
6-1.
INTRODUCTION.
6-2. This chapter covers corrective maintenance of the DPS. Corrective maintenance
consists of replacement of faulty printed circuit cards, fuses, indicators, or other
components. All LRI's (lowest replaceable items) for the DPS, except memory and
power supply modules, are designed to be throwaway items. No adjustments are required.
6-3.
REMOVAL AND REPLACEMENT PROCEDURES.
6-4. The following paragraphs describe the chassis and assembly removal procedures.
Included are connector pin and indicator-switch replacement procedures. Table 6-1
provides a list of tools required but not supplied.
Table 6-1.
QTY
PER
EQUIP
Special Equipment and Tools Required But Not Supplied
NOMENCLATURE
NAME
DESIGNATION
REQUIRED
USE
EQUIPMENT
CHARACTERISTICS
1
Oscilloscope
Tektronix Model
545A, AN/USM-28l,
AN/USM-140, or
equivalent
Troubleshooting and
maintenance
1
Preamplifier, Dual
Trace
Tektronix lA2
or equivalent
Required with
Oscilloscope
Dual Trace
1
AC Current Probe
with Passive
Terminator
Tektronix P602l
(015-0140-00 ) or
equivalent
Required with
Oscilloscope for
memory read/
write current
testing
Current Probe
1·
Voltage Probe Xl
Tektronix P6028
(010-0074-00) or
equivalent
Required with
Oscilloscope
Voltage Probe
2
Voltage Probe XlO
Tektronix P6006
(010-0127-00) or
equivalent
Required with
Oscilloscope
Voltage Probe
XlO
1
Mul timeter
Tripplett Model
630, AN/PSM-4(V)
or equivalent
Troubleshooting
and maintenance
6-1
Table 6-1.
QTY
PER
EQUIP
Special Equipment and Tools Required But Not Supplied (Cont)
NOMENCLATURE
NAME
DESIGNATION
REQUIRED
USE
EQUIPMENT
CHARACTERISTICS
Hand Operated
1
Pin Inserter and
Extractor Handle
Univac No. 8839225
Remove and insert
wire wrap pins and
bushings for card
jacks and rear
connector panel
1
Adapter
Univac No. 8839224
Required with
handle
1
Tip, Inserti on
Univac No. 8839226
Insert pins
.1
Tip, Extraction
Univac No. ETX
861690
Remove pins
1
Wire Stripper
Ideal 45-171
Wire repair
1
Stripper Blade
Ideal L52ll
16-26 gauge
1
Stripper Blade
Ideal L5436
26-30 gauge
1
Low-Voltage
Soldering Iron
Hand Operated
Miscellaneous
Hand Tools
6-2
Logic and Connector
wiring
Battery Operated
1
Wire Wrap Gun
Gardner-Denver
14R2
1
Power Pack for
Wire Wrap Gun
Gardner-Denver
503885
1
Wire-Wrap Bit
Gardner-Denver
26263
Logic Wiring
24 gauge
(on large pin)
1
Wire-Wrap Bit
Gardner-Denver
501381
Logic Wiring
30 gauge
(on large pin)
1
Wire-Wrap Bit
Gardner-Denver
504221
Logic Wiring
30 gauge
(on small pin)
1
Wire-Wrap Sleeve
Gardner-Denver
18840
Logic Wiring
24 gauge
(on large pin)
1
Wire-Wrap Sleeve
Gardner-Denver
17611-2
Logic Wiring
30 gauge
(on large pin)
1
Wire-Wrap Sleeve
Gardner-Denver
500350.
LogiC Wiring
30 gauge
(on small pin)
Rechargeable
Table 6-1.
QTY
PER
EQUIP
Special Equipment and Tools Required But Not Supplied (Cont)
NOMENCLATURE
NAME
DESIGNATION
REQUIRED
USE
EQUIPMENT
CHARACTERISTICS
1
Unwrap Tool
Gardner-Denver
500130
Logic Wiring
20-26 gauge
1
Unwrap Tool
Gardner-Denver
505244
Logic Wiring
30 gauge
6-5. POWER SUPPLY REMOVAL PROCEDURE.
replace the DPS power supply.
1.
Listed below is the procedure to remove and
Turn off power and disconnect the power cable from connector J35.
2. Open front panel by loosening the eight retaining screws and swinging
panel open.
3. Remove Phillips screw securing left hand bracket of telescoping door stop
from front bottom edge of cabinet. This allows the front panel to open wider.
CAUTION
--Ensure no stress is placed on the cables (J01-J04) to the maintenance
panel. In case of stress, these cables must be unplugged and/or cable
clamp removed.
4. With Phillips screwdriver, disengage four quick-release memory chassis
fasteners. Pullout the memory chassis assembly and swing it open to the left.
5. Remove ribbon cable cover (four Phillips screws) located on the lower right
bottom of cabinet.
6. Remove memory fastening block located at lower right front corner of cabinet.
It is held with four Phillips screws accessible from outside of cabinet.
7. Unplug and tag the six CP/IO chassis paddle boards (ribbon cable cards) from
CP/IO chassis rows A and C, slots 1, 2, and 3. Remove ribbon cable from behind
cable holder located left front of power supply.
8.
Remove four bottom bolts (7/16" wrench) securing power supply to the cabinet.
9. Remove and tag all wires on TBI through TB5, located on front of power
supply. TBI and TB2 have removable covers.
10. Remove and tag wires from terminals E9 and ElO, located on front of power
supply.
11. Ensure cabinet is firmly fastened down .or held in place. Grasp power supply
handle, located on bottom center of supply, pull unit forward, and remove from
cabinet.
6-3
12. To gain access to the interior of the power supply, remove the 18 screws
securing the top panel to the supply frame.
6-6. Cp/IO CHASSIS REMOVAL PROCEDURE.
and replace the DPS Cp/IO chassis.
1.
Listed below is the procedure to remove
Turn off power and disconnect the power cable from connector J35.
2. Remove and tag all cables from the connector panel located on the rear of
the Cp/IO chassis (connectors extend through rear panel of cabinet).
3.
Open front panel per paragraph 6-5 f steps 2 and 3.
4. With Phillips screwdriver, disengage four quick-release memory chassis
fasteners. Pullout the memory chassis assembly and swing it to the left.
5. Unplug and tag the six CP/IO chassis paddle boards (ribbon cable cards)
from Cp/IO chassis rows A and C, slots 1, 2, and 3.
6. Remove all cards of CP/IO chassis center row B, using card extractor.
cards aside stacked in sequence.
Set
7. Using a spintite, remove the four nuts holding the cover for TBl, located
in row B.
8.
Using a 5/16" wrench, remove the cable clamp holding the ac power wires to
TBI.
9.
10.
Remove and tag all wires on TBI.
Remove eight Phillips head screws securing Cp/IO chassis to cabinet.
CAUTION
When removing Cp/IO chassis, do not let it fall into the lower part of
the cabinet.
11.
Pull forward on CP/IO chassis and remove it from the cabinet.
12.
Replace the Cp/IO chassis by reversing the above procedure.
6-7. POW~R SUPPLY BLOWER REMOVAL PROCEDURE.
use the following procedure.
To remove the power supply blower,
1.
Perform the power supply removal procedure, paragraph 6-5.
2.
Remove the 12 Phillips screws around the power supply blower vent (located
rear portion of left side of cabinet). Pull assembly loose from cabinet.
~ower
on
3.
Remove and tag the three power wires on the blower assembly.
4. Remove the four Phillips screws holding the blower assembly to the vent grill,
and remove blower.
5.
6-4
Replace the power supply blower unit by reversing steps 1 through 4 above.
6-8. CP/IO CHASSIS BLOWER REMOVAL PROCEDURE.
use the following procedure.
To remove the CP/IO chassis blower,
1.
Perform the CP/IO chassis removal procedure, paragraph 6-6.
2.
Remove the 17 screws holding the CP/IO chassis blower cover.
3.
Remove and tag the power wires to the blower.
4.
Remove the four screws holding the blower assembly to the CP/IO chassis.
5.
To replace the blower, reverse steps 1 through 4 above.
6-9. MEMORY CHASSIS BLOWER REMOVAL PROCEDURE.
use the following procedure.
1.
To
L~move
the memory chassis blower,
Open cabinet and extend memory chassis per paragraph 6-5, steps 1-4.
2. Remove and tag three power wires located at lower left corner of blower
assembly.
3.
Remove four Phillips screws located at blower 3ssembly corners.
4.
Pull blower assembly straight out.
5.
Replace blower assembly by reversing steps 1 through 4 above.
6-10. MEMORY BOARD ACCESS.
the following procedure.
1.
To gain access to the DPS memory chassis boards, use
Open cabinet and extend memory chassis per paragraph 6-5, steps 1-4.
2. Remove the eight screws securing the chassis end panel (perforated panel
facing forward)j remove the panel, providing access to the boards.
3. Engage right-hand and left-hand card extractors (table 1-2) into holes at
top and bottom edges of selected memory. board; press to loosen and remove board.
4.
To replace the unit, reverse steps 1 through 3 above.
6-5
6-11. INDICATOR-SWITCH REPLACEMENT. To replace faulty switches or indicatorswitches in the maintenance panel or control panel, use the following procedure.
1.
Shut off power and disconnect the power cable from connector J35.
2. Open front panel by loosening the eight retaining screws, and swinging
open.
3.
Loosen the five screws securing the maintenance panel to the door.
4. Pull the top of the maintenance panel forward to swing it down on its hinge,
exposing the rear of both the maintenance panel and the control panel.
5. Remove and tag wires from faulty component, referring to either the wire
wrap procedure or the solder procedure depending on how the wires are secured.
6. Loosen and remove the knurled ring (located on front of panel) securing the
component to the panel.
7.
Replace the faulty component with a new component of the same part number.
8.
Reverse above procedure to close and secure panel assembly.
6-12. CP/IO CONNECTOR PIN REPLACEMENT. To replace pins in the CP/IO circuit card
connectors or in the I/O connectors located on the back of the CP/IO chassis, use
the following procedure.
1.
Perform CP/IO chassis removal procedure, paragraph 6-6.
2.
Remove CP/IO blower assembly panel per paragraph 6-8.
3. Remove screws securing CP/IO back connector panel; open panel to provide
access to wire wrap side of connectors.
4. Remove the wire from the connector pin by following step 1 of wire wrap
procedure, paragraph 6-15.
6. Using inserter/extractor handle (Univac No. 8839225, table 6-1), adapter
(Univac No. 8839224), and extraction tip (Univac No. ETX 861690); remove the
faulty pin.
7. Using inserter/extractor handle (Univac No. 8839225), adapter (Univac No.
8839224), and insertion tip (Univac No. 8839226); insert a new connector pin.
8.
Follow wire wrap procedure, steps 2 through 6, to connect wire to new pin.
9.
Close connector panel.
10.
Replace unit by reversing procedures in steps 1 through 3 above.
6-13. WIRE WRAPPING. Wire connections to connector terminals of the DPS are made
by wrapping several turns of wire around the post. Each terminal post has a
rectangular cross section. The wrapped connections. form helical coils on the posts,
with points of contact at each of the four corners. Two connections may be made
at each post, the second connection being wrapped around the upper portion (level)
6-6
of the post. If a lower level wire must be removed, remove the upper level first
to gain access.
6-14. Two commercial tools are used to replace defective wires: a manually operated wire-wrap tool for removal of the old wires, and a battery-operated wire-wrap
gun, with a detachable rechargeable battery which forms the handle, for installation
of the new wires. The wire-wrap gun is used in conjunction with various size bits
and sleeves to position the wire over the terminal post and accomplish the wrap.
The size of the wire to be wrapped determines the bit and sleeve size that must be
used. Refer to table 6-1 for the various size bits and sleeves.
6-15.
To replace defective wires, perform the following steps:
1. Remove old wire by placing barrel of wire-unwrap tool over terminal post
and twisting tool in a direction opposite to that of the wire wrap.
2. Remove approximately one inch of insulation from replacement wire, being
careful not to nick bare area of wire.
3. Use wire-wrap sleeve and bit corresponding to size of wire.
bit in wire-wrap gun.
Place sleeve and
4. Insert bare portion of replacement wire into longitudinal groove of bit.
Edge of wire insulation must touch end of bit (figure 6-1).
S1.EEVE
. TERMINA1. POST
I+----WIRE
BARE WIRE
(APPROXIMATE1.Y
I INCH)
A. INSERTION OF WIRE INTO 1.0NGlTUDINAl. GROOVE.
4.
<
",
B. POSITIONING OF GUN, WIRE, AND TERlItNAI_ POST.
•
Figure 6-1.
Preparation for Wire Wrapping
6-7
5. Bend wite so insulated portion is at right angle to longitudinal groove of
bit (figure 6-1).
6. Position wire-wrap gun over terminal post, with terminal post inserted in
bit, and press trigger. Wire-wrap gun supplies necessary power to make wrap.
Complete at least four complete turns around post with wire. Wire must be evenly
applied, without overlapping of turns or gaps between turns (figure 6-2).
NOTE
Do not wire-wrap with a gun that does not have fully charged batteries.
Recharging the battery is accomplished by twisting the handle 90 0
counterclockwise and inserting it into a conventional 115 Vac, 60 Hz,
single-phase electrical outlet for 12 hours.
6-16. SOLDER CONNECTIONS. Normal soldering techniques employed for electronic
component replacement and repair should be applied when removing or forming solder
connections.
UNACCfP'TARL£
WRAPPING
ACCEPTABLE.
WRAPPING
'J'
.~
VARIABLE
IfiSUFF Ie IEIH
EXCESSIVE
BACKFOr.C(
BACKFORCE
BliCKfORCE
Figure 6-2.
6-8
Wire Wrap Connections
CHAPTER 7
PARTS LIST
7-1.
INTRODUCTION.
7-2. The Parts List identifies units, assemblies, and detail parts for the Data
Processing Sets AN!UYK-20(V) and AN!UYK-20X(V). The parts list contains fifteen
(15) optional units and eleven (11) kits. A given Data Processing Set does not
contain all major units, therefore to aid the user in locating parts table 7-2
is subdivided into separate parts lists with identical parts repeated for each
uni t.
7-3.
LIST OF MAJOR UNITS.
7-4. Table 7-1 is a tabular listing of the major units comprising this equipment.
The first column lists the unit numbers in numerical order. Table 7-1 also provides the name of unit, designation and location of first page of its parts listing in table 7-2.
7-5.
PARTS LIST.
7-6. Table 7-2 lists the uni ts and tht,ir repairable parts. This list is divided
and arranged by major units in numerical sequence. Parts attached to the unit are
listed first in alpha-numerical order, followed by unit assemblies with parts also
listed in alpha-ntimerical order. Column I contains the reference designations of
all parts listed in sequential order. Replaceable components not reference designated are listed after their next higher assembly or at the end of each unit. The
notes column is not used for this equipment. Column 3 consists of the noun name
or item name and electrical or physical characteristics to identify the parts
within the equipment. Following this description, part manufacturer's Federal
supply code number, manufacturer's part number, contractor's Federal supply code
number, contractor's drawing number or military type designation, as applicable,
are included. Identical parts that are used more than five times in a given unit
are li sted wi th "Same as
" and referenced to the i tern number in table 7-3 Li st
of Common Item Descriptions. The attaching hardware, with quantity required, is
identified by an assigned letter code and listed immediately following the item
which they secure. The figure and item number (column 4) identifies the illustration which pictorially locates the part by listing the figure number with item
numher enclosed in parenthesis.
7- 7.
LIST OF COMMON I TEM DESCRIPTIONS.
7-8. Table 7-3 is a'list of like parts that are used over five applications. The
parts are grouped and arranged in alphabetical order with item numbers assigned
consecutively. The description is the same as shown in table 7-2.
7-9.
LIST OF ATTACHING HARDWARE.
7-10. Table 7-4 contains a list of all the attaching hardware referenced in table
7-2. These items are grouped and arranged in alphabetical order with letter codes
assigned consecutively.
7-1
,7-11.
LIST OF MANUFACTURERS.
7-12. Table 7-5 is a list of manufacturers containing the names, addresses, and
code symbol of all manufacturers supplying items for the equipment as referenced
in the parts listo
7-13.
PARTS LOCATION ILLUSTRATIONS.
7-140 Suitable parts location illustrations located in other chapters of the
manual are referenced and not repeated. Illustrations provided only for locating
parts are placed at the end of this chapter o
7-2
Table 7-1.
UNIT
NO.
List of Major Units
NAME OF UNIT
DESIGNATION
1
Cabinet, Electrical Equipment
CY-
juYK-20(V)
:2
Cabinet, Electrical Equipment
CY-
jtm-20X(V)
3
Control-Maintenance Unit
C-
/UlK-20(V)
4
Control-Maintenance Unit
c-
/UYK-20X(V)
5
Power Supply.
PP-7032/UYK-20(V)
6
Power Supply.
pp-
/UYK-20(V)
7
Power Supply.
pp-
/UYK-20(V)
8
Power Supply.
pp-
/UYK-20I(V)
9
Power Supply.
pp-
juYK-20X(V)
10
Power Supply.
pp-
juYK-20X(V)
11
Processor-Verifier Unit
cp-
(P)/UIK-20(V)
12
Processor-Verifier Unit
CP-
(P)/UYK-20X(7)
13
Core Memory Unit
MU-604/UYK-20(V)
14
Control, Core Memory
C-
(P)/UYK-20(V)
15
Control, Core Memory.
C-
(P)/UYK-20X(V)
16
Interface Kit, Fa st Serial
MK-
/UYK-20(V)
17
Interface Kit, Serial Sync
MK-
/UYK-20(V)
18
Interface Kit, Se rial Async
MK-
(V)/UYK-20(V)
19
Interface Kit, Serial
Communications, Sync
MK-
/U!K-20(V)
20
Interface Kit, Serial
Communications, Async
MK-
(V)/UYK-20(V)
21
Interface Kit, Slov
MK-1693/U!K-20(V)
22
Interface Kit, Fast, Negative
MK-1694/U!K-20(V)
23
Interface Kit, Fast, Positive
MK-1695/UYK-20(V)
PAGE
NO.
7-3
Table 7-1.
List of Major Units (Cont)
T~Tr
yr-" •
......T:,l"r:''
~.....
nESIrm~·Tr~~
I1r:-
(V)/UYK-20(V'
Haintenance Kit
MK-
/UYK-20(V)
Accessory I:it
MK-
/UYK-20(V)
24
~Ucro
25
26
7-4
"!-' UNTT
Hemory Program Kit
PAGE
!r0.
TAlfLE 7-2.
Reference
Designation
DATA PROCESSING SET
PARTS LIST
Notes
Cabinet, Electrical Equipment
1
.~,N/F'i')
CABlNE'T
C;y~
it .1)
ELEC':mFiJ~
/UYK,,20(V) :
Provides illou:n"·;t
Processinp: 8,~!
shipboard ~wd
lBl
.,"
, part no.
7101970-00.
FAN,
J\.xn.L ~
C'iol;" ..•
.~;:i'.ln(_m':'t CaSf:3,
in. aq, 1. S .,'... <
81 ODS m1[~ ST ~
4. 688
no.
1
(Attachin,tr
IAl
IA2
lA3
lA4
lA4FLl
thru
lA4FL4
lA4Jl
lA5
lA6
IA6CI
lA6E;l .
lA6E2
lA6TBl
lA7
lA7R1
thru
lA7R3
BB(Ji-), DCU,,\ ,"
CtlNTROL-MJtlltrZ:NA}i
CORE }!Ei. FiRY m~~T.:
PROCESSCR-VERIYIE;, )
FILTER ASSEHBLY'
7101950 ...00.
(Attaching
FILTER, RADIO E'RE~!F;;;:r;;.{
circuit 1'1'1 fil tEn" ,
part nO e JNl7-456L,!i
CONNECTOR,
RECEPTA~LE:
.4 filters
T
mfr 56289,
7904,734-00 ..
Male 7-
contact; MIL type ,
(Attaching Parts)
not used
ELECTRONIC COMPONENJ'S '".",.,1'"',·,·,,.
Contains 1
capacitor, 1 tt~:rm:b'lr::J
1'l11d .2 terminal s;
mf1' 90536, part no.
(AttachL.'1g Pa:rts
:'
CAPACITOR, FIXED,
DIEL.EC'fRIC: L C'UF,
±10%, 400VDCW; mfr
.~ pa!'t no.
260P10594S2, 90536,
"/903001-11"
TERl.fINAL, STUD: Insulated, stand off', threaded
/2 turret; mfr 71279"
no.. 570-·3650-02-05,
90536, dwg 910185-.\')2.
(Attaching Parts)
;;, ~
TERMINAL BCiARD: nF.Lt1.,:,it'5J:
terminals; mf'r
75382, part no. 600AYJJ
dwg 904862-04.
(Attaching Parts) Ii
AG ( 2), AJ' ( 2), BC ( 2) ,
RI(6)
RESISTOR AS5EHBLY, FIl'ED: Contains 3
resistors; mfr 90536, pa:rt no. 7128008-00.
(Attaching Parts) l~I( ,13r(2)
RESISTOR, FIXED, C()MPOSITIOI~: lOOK ohm, .±5%,
1/2W; MIL type RCR20GI04.;'11.
~----------~--~-----------------------,--------------~~------~
7-3
TABLE 1-2. DATA PROCESSING SET AN/UYK-20(V) AND AN/UYK-20X(V), PARTS LIST (CuNT.)
Reference
Designation
1 (Cont.)
Name and Description
Notes
Figure
Number
(Item)
C0NTACT, ELECTRICAL C,·'NNECTnR: Female,
removable, for rack and panel connectors,
0.764 in. long, 16Al1G, 13 mnp rating; mfr
81312, part no. 100510168994, 90536, dwg
4910566-01 (8).
.
cr'IITACT, ELECTRICAL C~'NIrECT('R: Female,
removable, for rack and panel connectors,
0.764 in. long, 24AHG, 13 amp rating; mfr
81312, part no. 100510248994, 90536, dwg
4910566-05 (6).
C~·'NTACT, ELECTRICAL C:',N1TECT')R:
Female,
removable, for rack and panel connectors,
0.764 in. long, 26 to 30A:TG, 13 amp rating;
mfr 81312, part no. 1005102639Q4, 90536, dwg
4910566-08 (4).
Cabinet, Electrical Equipment CY-
/UYK-20X(V)
(Unit 2)
~----------~~--~------------------------------------------r-------~
CABINET ELECTRICAL EQUIPMENT CY/UYI:-20X(V):
2
2B1
Provides mounting for units of Data
Processing Set i\N/UYK-20X(V), designed for
shipboard and ground use; mfr 90536, part no.
7101970-01.
FAU, AXIAL: Cw rotation, aluminum case, 4.688
in. sq., 1.5 in. thick; mfr 82877, part no.
682YS TYPE ST, 90536, dyg 7901420-03.
C',tbchin~ arts) G(4), 1(4), X(2), AH(2),
RB(4), RC(4), RH(4), BI(6)
cnr·lTW'L-H1UNTENENCE UNIT: See unit no. 4.
C"RE HE?YRY UNIT: See unit no. 13.
PR"'CESS"R-VERIFIER UI1IT: See unit no. 12.
FILTER ASSSHBLY, ELECTRIC'lL: Contains 4 filters
and 1 connector; mfr 90536, part no.
7101950-01.
(Attaching Parts) AL(8), BJ(8)
FILTER, RA.DIO FREQUENCY INTERFERENCE: T circuit
rfi.fi1ter, 125vac, 12amp; mfr 56289, part no.
JNI7-456~\, 90536, dwg 7904734-00.
CO NNE CTr':R, RECEPTACLE, ELECTRICAL: Hale, 7contact; HIL type H83102R20-15PZ·.
(Attaching Parts) G(4), AA(4), AU(4), BB(4)
not used.
iELECTRrrrrC Cf"HPC:NENTS A8SEloIDLY: Contains 1
capacitor, I terminal board~ and 2 terminals;
mfr 90536, part no. 7126335-01.
(Attaching Parts) AH(2), BI(2)
p.
2A1
2:\2
2/\.3
2A4
2J\4FL1
thrn
2A1.FL4
2A4Jl
2A5
2A6
7-6
TABLE 7-2.
DATA PRf"lCESSING SET ANjUYK-20(V) AND AN/UYK-20X(V), PARTS LIST (CONT.)
Reference
Designation
216c1
216E1
2A6E2
216m
2A7
217Rl
thru
2A7R3
Figure
Notes
Name and Description
Numbe~
(Item)
CAPACITOR, FIXED, PLASTIC DIELECTRIC: 1.39UF,
±10%, 400VDCW; mfr 56289, part no. 260P3949481
90536, dwg 7903001-33.
TERMINAL, STUD: Insulated, stand off, threaded
/2 turret; mfr 71'Z79, part no. 570..:.3650-02-05,
90536, dwg 910185-02.
.
(AttaChing Parts) V(2)
TERMINAL BOARD: Barrier typ~, 3 terminals; mfr
75382, part no. bOOAY3, 90536, dwg 904862-04.
(Attaching Parts).I(4), AG(2), AJ(2), BC(2),
BI(6)
RESISTOR ASSEMBLY, FIXED: Contains 3 resistors;
mfr 90536, part no. 7128008-00.
(Attaching Parts) AH(2), BI(2)
RESISTOR, FIXED, COMPOSITION: lOOK ohm, ±5%,
l/2W; MIL type RCR20G104JM.
CONTACT, ELECTlUCAL CONNECTOR: Female,
removable, for rack and panel connectors,
0.764 in. long, 16AWG, 13 amp rating; mfr .:
81312, part no. 100510163994, 90536, dwg
4910566-01 (8).
CrNTAc:r, ELECTRICAL CONNECTOR: Female,
removable, for rack and panel connectors,
0.764 in. long, 24AWG, 13 amp rating; mfr
81312, part no. 100510248994, 90536, dwg
4910566-05 (6).
.
CONTACT, ELECTRICAL CONNECTOR: . Female,
removable, for rack 'and panel connectors,
0.764 in. long, 26 to 30AWG, 13 amp rating;
mfr 81312, part no. 100510265994, 90536, dwg
4910566-08 (4).
Control-Maintenance Unit C-
3
3181
/UYK-20(V)
(Unit 3)
CONTROL-MAINT&NANCE UNIT C/UYK-20(V):
Evaluates performance and provides control and
visual moriitoring of internal functions of. the
Data Processing Set AN/UYK-20(V), operating
power ·115 VAC, 400HZ, 3-phase delta or 208
VAO, 400HZ, 3-phase wye or 115 VAC, 400HZ,
single phase; mfr 90536, part no. 7101985-00.
HORN, ELECTRICAL: With solid state oscillator,
1.7 in. dia, 30-120 volt; mf~ 37942, part no.
3C110Z W/ALMTGRING l 90536, dw~ 7904742-00.
(Attac~ing Parts) .AC(2), BH(2)
7-7
TABLE 7-2.
DATA PReCESSING SET AN/UYK-20(V} AND l.N/UYK-20X(V}, PARTS LIST (CONT.)
Reference
Designation
.3Al
.3AlCB1
.3AlDS1
.3AlDS2
.3A1DS.3
.3A1DS4
.3AlDS5
.3A1DS6
.3A1DS7
.3AlS1
.3AlS2
.3A1S)
.3AlS4
JA1S5
.3AlS6
.3AlS7
7-8
Figure
Notes
Name and Description
CC'NTROL PANEL ASSEMBLY: Contains 1 circUit
breaker, 7 indicators, and B switches; mfr
905.36, part no. 7101985-00.
(Attaching Parts) R(12), lUI(12), BI(12)
CIRCUIT BREAKER, MAGNETIC: .3 poles, '20 amp,
240V, 400HZ;' MIL type M.39019/5-80.
(Attaching Part) N(l)
LIGHT, INDICAT:-:'R: Neon, w/resistor, red sealed
lens, RFI shielding; mfr 07137, part no •
SIL8062A25, 905.36 l dw~ 79047.35-20.
(Attaching Part) BF(2)
,
LIGHT, INDICAT('R: Light emitting diode,
w/resistor, sealed green lens; mfr 07137,
part no. SSILB066133C, 90536, dwg 7904467-14.
(Attaching Parts) L(l), BF(l) .
LIGHT INDICAT-R: Light emitting diode,
w/resistor, sealed clear lens; mfr 071.37,
part no. SSIL8059A22, 90536, dwg 7904279-12.'
(Attaching Parts) L(2), BF(2)
LIGHT, nmICATrJR: Incandescent, w/75 ohm
resistor, non-replaceable lamp, 5 V, 0.06 amp,
sealed white lens; mfr 07137, part no.
SILB065A32, 90536, dw~ 7904806-00.
(Attaching Parts) L(l), BF(l)
LIGHT, INDICATCR: Neon, w/resistor, sealed
white lens, RFI shielding; mfr 07137, part no.
SIL8062A32, 90536 t dwg 7904735-23 •.
(Attaching Part) BF (1)
SWITCH, TOGGLE: Minature, dpdt, sealed; MIL
type MS24656-231.
(Attaching Part) L(l)
,m.fITCH, TOGGLE: Minature, dpdt, sealed; MIL
type MS24656-311.
(Attaching Part) L(l)
SWITCH, TrGGLE: Minature, single pole, panel
sealed; MIL ,type MS24655-231.
(Attaching Part) L(lO)
SWITCH, TOGGLE: Minature, single pole, panel
sealed; MIL type MS24655-27l.
(Attaching Part) L(l)
SWITCH, TrGGLE: Minature, single pole, panel
sealed; MIL type MS24655-281 •
(Attaching Part) L(2)
SllITCH, TeGGLE: l-1inature, single pole, panel
sealed; lUL type 11S24655-221(Attaching Part) L(l)
Number
(Item)
TABLE 7-2.
DATA PROCESSING SET AN,!trYK-20(V) AND AN/UYK-20X(V), PARTS LIST (CONT.)
Referenoe
Designation
JAlS8
JA2DSl
JA2JOl
JA2J02
JA2JOJ
JA2J04
3A2Kl
Notes
Figure
Name and Deacription
Numbe~
(Item)
SWITCH, TOGGLE: Subninature, sealed, J pole;
mfr JIJ56, part no. T04-323, 90536, dvg
7904733-01.
, (Attaching Parts) L(l), BF(l)
PANEL ASSEMBLY, MAINTENANCE: Contains 1
indicator, 4 connectors, 1 relay, 1 meter, 47
av1tches, and 1 terminal board; mfr 90536,
part no. 7101850-00.
(Attaching Parts) R(6), AH.(6), BI(12)
LIGHT, INDICATOR: Light emitting diode,
v/resistor, clear lens; mfr 07137, part no.
SSI18722C22, 90536~ dvg 7904279-00.
(Attaching PartS) K(l), BK(l)
CONNECTOR BLOCK: Contains 120 terminal
assemblies; mfr 90536, pirt no. 7101817-00.
(Attaching Part) m(4J
INSULATOR, ELECTRICAL CONNECTeR: Male,
rectangular, 20 contact locations; mfr 81312,
part no. MRAC20PJ6-436, 90536, dwg
4911532-00.
RELAY, ARMATURE: 3 SPST, 115 VAC, 400HZ; MIL
type MS27418-lA.
JA2Ml
3A2S1
JA2S2
JA2SJ
3A2S4
JA2S5
JA2S6
JA2S7
JA2SS
JA2S9
3A2S10
.3A2S11
,·3A2S12
3A2S13 .
METER, TIME TOTALIZING: 115V, 400HZ,' 9999
hour elapsed time, square case; MIL type
MS17322-10.
(Attaching Parts) P(2), AS(2), BC(2)
SWITCH, PUSH: SPST normally open double break,
0.1 amp, white. button; mfr 07137, part no.
SBS8732B26, 90536, dw~ 7904277-00.
(Attaching Parts) K(3), BK(J)
SWITCH, PUSH: SPST normally open double break,
light emitting diode indicator, w/resistor,
0.1 amp, clear lens; mfr 07137, part no.
SSBL8721C22, 90536 dug 7904278-00.
(Attaching Parts~ K(24), BK(24)
SWITCH, PUSH: SPST normally open double break,
light emitting diode indicator, w/resistor,
0.1 amp, clear lens; mfr 07137, part no.
SSBL8774C22, 90536t dwg 7904278-03.
(Attaching Parts) 1-1(7), BK(7) .
Saine as JA2S2 (itam no. 22),
.
,
Same as 3A2S5 (itam no. 23)
7-·9
TABLE 7-2.
DATA PROCESSING SET AN/UYK-20(V) AND AN/UYK-20X(V), PARTS LIST (CONT.)
Figure
Reference
Number
Notes.
Nama and Description
Designation
(Item)
Same as ~A2S2 (item no. 22)
3A2Sl4
3A2Sl5
3A2Sl6
Same as 3A2S5 (item no. 23)
3A25l7
Same as 3A2S2 (item no. 22)
3.\2518
3A2Sl9
3A2S20
3A2S2l
3A2S22
thru
3A2S3l
3A2S32
3A2S33
3A2S34
3A2S35
3A2S36
3A2S37
3A2S38
3A2S39
3A2S40
3A2S41
3A2S42
3A2S43
3A2S44
3A2S45
3A2S46
3A2S47
3A2TBI
7-10
SWITCH, PUSH; SPST normally open double break,
light emitting diode indicator, 0.1 amp,
green lens; mfr 07137, part· no.
SSBLS025A33C, 90536, dwg 7904466-07.
(Attaching Parts) K(l), BK(l)
Same as 3A2Sl ( item no. 21)
Same as 3A252 (item no. 22)
Same as 3A1S3
(item no. 25)
Same as 3A2S2
(item no. 22)
Same as 3AlS3
(item no. 25)
SWITCH, TOGGLE: Minature, single pole, panel
sealed; MIL type MS24655-21l.
. (Attaching Parts) K(l)
Same as 3A1S3 (item no. 25)
Sl>TITCH, TnGGLE: DPDT, mina t ure, panel sealed;
MIL type }IS2l352-351.
(Attaching Parts) I~(l)
. SHITCH, T::GGLE: l-1inature, single pole, panel
sealed; MIL type HS2l350-321.
(Attaching Parts) K(l)
Same as 3A2Sl (item no. 21)
Same as 3AlS3 (item no. 25)
TERMIUAL BOARD: Barrier type, 14 terminals;
mfr 71785, part no. 354-11-14-001, 90536,
dwg 900125-16.
(Attaching Parts) AI(2), BI(2)
C~)NTACT, ELECTRICAL CCNNECTCR:
Male,
removable, for rack and panel connectors,
0.764 in. long, l6A1/G, 13 amp rating; mfr
81312, part no. 1001016P159, 90536, dwg
4910565-01 (8).
TABLE '1-2.
DATA PROCESSING SET AN/U!K-20(V) AND AN/UYK-20X(V), PARTS LIST (CONT.)
Reference
Designation
3 (Cont.)
Figure
Notes
Name and Description
4181
4AJ..
4A1CB1
4tUDSl
4A1DS2
(Item)
CONTACT, ELECTRICAL CONNECTOR: Male,
•
removable, for rack and panel connectors,
0.764 in. long, 24AWG, 13 amp rating; mfr
81312, part no. 100l024P159, 90536, dwg
4910565-05 (6).
.
CnlITACT, ELECTRICAL Cnm-lECT(l!1: Male,
removable, for rack and p~nel connectors,
0.764 in. long, 26 to 3U AwG, 13 amp rating;
mfr 81312, part no. lODl026P159, 90536, dwg
4910565-08 -(4).
FILTER, AIR CONDITInNING: AllDIlinlDIl, oiled type,
15.5 in. long, 9 in. Y1.de, 0.5 in thick, type
R82A; mfr 00736, part no. 124786-219, 90536,
dwg 910486-20 (1).
FILTER: EMI large; mfr 90:~J6, part no.
7101913-00 (1).
Control Maintenance Unit C4
NUI!I.be~
/UYK-20X(V)
(Unit 4)
CONTROL-MAINTENANCE UNIT C/UYK-20X( V) :
Evaluates performance and provides control
and visual monitoring of internal functions
of the Data Processing Set AN/UYK-20X(V),
operating power 115 VAC, 60HZ, 3-phase delta.
or 208 VAC, 60HZ, 3-phase wye or 115 VAC,
60HZ, single phase; mfr 90536, part no.
7101985-01.
HORN, ELECTRICAL: With solid state oscillator,
1.7 in. dia, 30-130 volt; mfr 37942, part no.
SCII0Z W/ALMTGRING.t 90536, dw~ 7904742-00.
(Attaching Parts) AC(2), BH(2)
cnNTRnL PANEL ASSEMBLY: Contains 1 circuit
breaker, 7 indicators, and 8 switches; mfr
90536, part nq. 7~01985-Ol.
(Attaching Parts) R(12), AH(12), BI(12)
CIRCUIT BREAKER, ru.GNETIC: 3 poles, 20 amp,
24 "V, 60HZ; HIL tyPe 1139019/5-78.
(AttRching Part) N(l)
.
LIGHT, INDICATOR: Neon, w/resistor, red
sealed lens, RFI shielding; mfr 07137, part
no. SIL8062A25, 90536, dwg 7904735-20.
.
(Attaching Part) BF(2)
7-11
Reference
Designation
MuDS3
Ij.·~l D:;/~
Ik~lDS5
4:.1DSI)
4:'181
4AlS3
4A1S4
4AlS5
4A1S6
. 4A1~7
4A1S8
7-12
Figure
Notes
Name and Description
LIGHT, nmICAT"R: Light emitting diode,
w/resistor, sealed Green lens; mfr 07137,
part no. SSIl80h6~33G, C)0536~ our; 790M+67-l/~.
(·,.ttnchinp, :'I"lrts) !,(l), ':r(l)
LI~;r,:"
II:DIC\T '1: Lir;ht onittinp, diode,
w/resistor, sealed clear lens; mfr 07137,
part no. SSILS059A22, 90536, dwg 7904279-12.
(.:'l.ttaching Parts) L(2), 13F(2)
LIGHT, I!f.)IGA'I" -'.: Tncf:.ndescent, "'7/75 ohr"1
rcsi~tor, nor.-r":-l"!cenblf> 1 "~'r, 5'1, 0.06 ~p,
scnled whitn lens; nfr 07137, !,nrt no.
8IL8065A32, 90536, dwe; 7904806-00.
(Attaching Parts) L\l), BF(l)
LIGHT, DIDICAT,"R: Neon, w/resistor, sealed
white lens, RFI shielding; mfr 07137, part
no. SILS062A32, 90536, dwg 7904735-23.
(.Attaching Parts) 13F(l)
Sl,JITCH, T(~~LF.: !1inUtur0., dpdt, sealed; ~~T~.
type 1.fS2/+656-231.
C~ttllching Pllrt) L(l)
SHITC:I, T,'\GGLS: Hin iB:Iure, dpdt, sealed; HIL
type HS24656-311.
(Attaching Part) L{l)
S1UTCH, Tr'GGLE: Hin i8.tlre , single pole, panel
sealed; MIL type MS24655-231.
(Attaching Part) L(lO)
Si-1ITCH, T:iGGLE: Min:ia1ure, single pole, panel
sealed; MIL tyPe MS24655-27l.
(Attaching Part) L{l)
S\UWH, TOGGLE: Miniature, single pole, panel
sealed; MIL type HS24655-2fll.
(Attaching Part) L(2)
SWITCH, TOGGLE: Hiniature, single pole, panel
sealed; MIL type 11S24655-221.
(Attaching Part) L(l)
Sl.;"ITCII, TOGGLE: Subminiature, sealed, 3 pole;
mfr.31356, part no. T04-323, 90536, dwg
7904733-01.
.
(Attaching Parts) L(l), BF(l)
PANEL ASSENBLY, HAINTENANCE: Contairis 1
indicator, 4 connectors, 1 relay, 1 meter, 47
switches, and 1 terminal board; mfr 90536,
part no. 7101850-01.
(Attaching Parts) R(6), AH(6), BI(l~)
Number
(Item)
T~ 7'7~!_~~TAPROCE;S6IN<;r SET AN!UYK-20(Y).AND ~/U~-20X(V), PARTS LIST (CONT.)
Referenoe
Designatiqn
4A2DSI
4A2JOI
4A2J02
4A2J03
4A2J04
4A2Kl
4A2Ml
4A2Sl
4A2S2
4A2S3
4A2S4
4A2S5
4A2S6
4A2S7·
4A288
4A2~9
4A2Sl0
4A2S11
4A2Sl2
4A2Sl3
4A2Sl4
4A2Sl5
4A2Sl6
4A2Sl7
4A2Sle
4A2Sl9
Figure
Notes
Name and Desoription
Number
(Item)
LIGHT, INDICAT0R: Light emitting diode,'
w/resistor, clear lens; mfr q7l37, part no.
SS.IL8722C22, 90536~ dwg 7904Z79JJO.
(Attaching Parts) K(l), BK(l)
CCNNECTOR BLOCl,(: Contains 120 termiilal
assemblies; mfr 90536, art no. 710l8l7JJO.
(Attaching Part) AR(4J
nmULATOR,. ELECTIUCAL CONNECTOR: Male,
rectangular, 20 contact locations; mfr 81312,
part no. MRAC20PJ6-436, 90536, dwg
49ll532JJO.
RELAY, ARMlI.TURE: j SPST, 115 VAC, 400HZ; MIL
type MS27418-lA.
METER, TIME TOTALIZING: l15V, 60HZ, 9999 hour
elapsed time, square case, mfr 82227, part no
K19603B6, 90536, dwg 7903922JJI.
(Attaching Parts) P(2), AS(2), BC(2)
SWITCH, PUSH: SPST normally open double
break, 0.1 amp, white button; mfr 07137, part
no. SBS8732B26, 90536, dwg 7904277JJO.
(Attaching Parts) K(3}, BK(3}
SWITCH, PUSH: SPST normally open double
break, light emitting diode indicator, .
w/resistor, 0.1 amp, clear lens; mfr 07137,
part no. SSBL8721C22, 90536, dwg 7904278JJO •.
. (Attaching Parts) K(24), BK(24}
SWITCH, PUSH: SPST normally open double break,
light emitting diode indicator,
w/resistor, 0.1 amp, clear lens; mtr 07137,
part no. SSBL8774C22, 90536, dwg
7904Z78JJ3.
(Attaching Parts) M(7), BK(7)
Same as 4A2S2 (item no. 22)
p.
Same as 4A2S5
(item no. 23)
Same as 4A2S2
(item no. 22)
Same as 4A2S5
,Same as 4A2S2
(itam no. 23)
(i tem no... 22)
7-13
TABLE.7-2 .. DATA PROCESSING SET. AN/UYK-20(V) AND AtljUIK-20X(V) , PARTS LIST (C('NT.)
Reference
Designation
4A2S20
4A2S2l
4.A2S22
thru
4.A2S3l
4A2S32
4.A2S33
4.A2S34
4A2S35
4A2S36
4A2S37
4A2S38
4A2S39
4A2S40
4A2S41
4A2S42
4A2S43
4A2S44
4L2S45
4A2S46
41.2S47
'4ATB1
7-14
Figure
Notes
Ngme and Description
SvlITCH, PUSH: SPST normally open double"
break, light emitting diode indicator, 0.1
amp, green lens; mfr 07137, part no.
SSBLB025A33C, 90536, dw~ 7904466-07.
(Attaching Parts) K(l}, BK(l)
.
Same as 4A2Sl (item no. 21)
Same as 4.A2S2 (item no~ 22)
Same as 4A1S3
(item no. 25)
Same as 4A2S2
(item no. 22)
Same as 4A1S3
(item ~o. 25)
S1UTCH, T'GGLE: Hiniature, single pole, panel
sealed; HIL type HS24655-2ll.
(Attachinr; Parts) r(1)
Same as 4A1S3 (item no. 25)
SWITCH, TOGGLE: DPDT, miniature, panel
sealed; MIL type HS2l352-351.
.
(Attaching Parts) Y.(l)
SWITCH, TCGGLE: Hiniature, single pole, panel·
seiled; HIt ty;"le HSn350-321.
(~tt~chin~ PArts) Y(l)
Same as 4.\2Sl·· (i tem no. 21)
Same as 4AlS3 (item no. 25)
TERMINAL Br'ARD: Barrier type, 14 terminals;
mfr 71785, part no". 354-11-14-001, 90536,
dwg 900125-16 •
.
.
. (Attaching Parts) AI(2), BI(2)
cnNTACT, ELECTRICAL.CONNECTOR: Male, removable,
for rack and panel connectors, 0.764 in.
long, l6A'~, 13 amp rating; mfr 81312, part
no. 10010l6P159, 90536, dwg 4910565-01 (8).
C0NTACT, ELECTRICAL CONNECT0R: Male, removable,
for rack a.nd panel connectors, 0.764 in. long,
24AWG, 13 amp rating; mfr 81312, part no.
1001024P159, 90536, dwg 4910565-05 (6).
Contact, electrical connector: Male, removable,
for rack and panel connectors, 0.764 in. long,
26 to 30 AWG, 13 amp rating; mfr 81312 part
no. 1001026P159, 90536, dwg 4910565-08 t4}.
Nmber
(Item)
TABLE 7-2.
DATA PROCESSING SET AN,!uYK-20(V) AND AN/UYK-20X(V), PARTS LIST (CONT.)
Figure
Reference
Numbe~
Notes
Name
and
Description
Designation
(Item)
Power Supply PP-70321uYK-20(V)
5
511
5P1
5P2
5Tl
5TB1
5TB2
5Al
5AlC1
5AlC2
5AlC3
5A1L1
5A2
5A2TB1
5A2TB2
5A2TB3
5A2TB4
(Unit 5)
POWER SUPPLY PP-7032/UYK-20(V): Provides power
to each of the units within the data proc~ss
or cabinet, operating power 115V, 400HZ,
3-phase delta; mfr 90536, part no.
7101840-00.
CHOKE ASSEMBLY, ELECTRICAL: Mrr 90536, part
no. 7101974-00.
(Attaching Parts) AN(2), AX(2), BE(2)
CONNECTOR, PLUG,' ELECTRICAL: Male; mfr 90536,
part no. 7101883-00.
(Attaching Parts) AC(4), AU(4)
TRANSFORMER ASSEMBLY: Mrr 90536, part no.
7126376-00.
(Attaching Parts) AN(6), AX(6), BE(6)
not used
TERMINAL BOARD: Barrier type, 5 terminal s; mfr
75382, part no. 354-28-05-001, 9053~dwg
904862-09.
(Attaching Parts) 1(2), A1(2), AV(2), BC(2),
B1(2)
.
ELECTRONIC COHPONENTS ASSEMBLY: 3-phase, 400HZ,
contains. 3 capacitors and 1 choke; mfr 90536,
part 11.0.' 7101982-00.
.
(Attaching Parts) ~(4), AX(4), BE(4)
_
CAPACITOR, FmD, ELECTROLYTIC: Al can, 680UF,
±15%, 250V; MIL tyPe CE'71C681M.
(Attaching Parts) AN(2), BE(2)
CAPACITOR, FIXED ELECTROLYTIC: 120UF, -15%,
+30%, 150V; mfr 56289, part no.
112Dl27G3150n, 90536, dwg 7901635-13.
PLATE ASSEMBLY, EHOKE: Mrr 90536, part no.
7101987-00.
(Attaching Parts) AJ(4), AV(4)
OUTPUT FTI.TER ASSEMBLt: Contains 2 capacitor
boards, 1 inductor choke assy, and 3
terminal boards; I1fr 90536, part no.
7101978-00.
(Attaching Parts) AN(6), AX(6), BE(6)
not used
TERMINAL BOARD:
Barrier type, 7 terminals; mfr
75382, part no. 600AY7, 90536, dwg 904862-11.
(Attaching Parts) AE(8), BC\8), BH(8)
7-15
TABLE 7-2.
DATA PROCESSING SET AN/UYK-20(V) AND Jr,N/UYK-20X(V), PARTS LIST (crNT.)
Roforence
Designation
5A2TB5
5A3
5A4
5A4C1··
5A4C2
5A4R1
5A4Tl
5A5
5A6
7-16
Figure
Notes
Name and Description
TERMINAL BOARD: Barrier tyPe, 4 terminal,s; mfr
75382, part no. 600AY4, 90536, dwg 904862-05.
(Attaching Parts) AE(4), BC(4), BH(4)
CAPACITOR BOARD ASSEMBLY: 13 capacitors and 2
resistors mtd on board, epoxyed; mfr 90536,
part no. 7101951-00.
.
(Attaching Parts) G(4), U(4), AU(4), BB(4)
CAPACITOR BOARD ASSEMBLY: 19 capacitors and 2
resistors mtd on board, epoxyed; mfr 90536,
part no. 7101952-00.
.
(Attaching Parts) G-(4), U(4), AU(4), BB(4)
INDUCTOR CHOKE ASSEMBLY: 8 chokes mtd on plate,
epoxyed; mfr 90536 t part no. 7101932-00.
(Attaching Parts) 1(4), BI(4)
FILTER ASSEMBLY, INPUT: 6 capacitors and 9
chokes mtd in chassis, epoxyed; mfr 90536,
part no. 7101979-00.
(Attaching Parts) AN(4), AX(4), BE(4)
ELECTRONIC COMPONENTS ASSEMBLY: Contains 2
capacitors, 3 resistors, and 1 transformer
mtd on bracket; mfr 90536, part no.
7101980-00.
(Attaching Parts) AN(), AX(3), BE()
CAPACITOR, FIXED, PAPER DIELECTRIC: 1. OJF, ±10~
400VDCW; MIL type CV09AlKE105KM.
CAPACITOR, FIXED, GLASS DIELECTRIC: 5100PF,
~O%, 300VDCW; mfr 07115, part no.
CY20C512K, 90536, dwg 4912284-16.
RESISTOR, FIXED, WIREWC!UND: 0.1 ohm, ±1%, 20W;
MIL type RE70GRlOO.
(Attaching Parts) G(2), T(2), AU(2), BB(2)
RESISTOR, FIXED, FILM: 20000 ohm. ±2%, 2W; MIL
type M22684-04-0159.
RESISTOR, FIXED WlREWOUND: 1 ohm, ±1%, 5W; MIL
type RE60G1ROO.
.
(Attaching Parts) P(2), S(2), BG(2)
TRANSFORMER, POWER, 'STEPDOWN: Control, single
phase, 50-400HZ; mfr 16153, part no. MC4518,
90536, dwg 7904726-00.
(Attaching Parts) 1(2), Y(2), AV(2), BC(2)
TRANSFORMER COIL ASSEMBLY: 2 transformers mtd
in bracket, epoxyed; mfr 90536, part no.
7101981-00.
(Attaching Parts) AN(4), AX(4), BE(4)
CIRCUIT CARD ASSEMBLY, CqNTROL: Plug-in type,
contains components epoxyed on printed wiring
board; mfr 90536, part no. 7119455-00.
Ntmber
(Item)
DATA PROCESSING SET AN/UYK-20(V) AND AN/UYK-20X(V), PARTS LIST (C~.T.)
Figure
Reference
Notes
Number
Name aDd Description
Designation
(Item)
TABLE 7-2.
5A7
5A7Cl
5A7C2
5A7C3
5A7CRl
thru
5A7CR4
5A7CR5
5A7CR6
HEAT EXCHANGER ASSEMBLY: Contains 3 capacitors,
16 diodes, 6 transistors, 4 resistors, and 1
integrated circuit; mfr 90536, part no.
7101877-00.
(Attaching Parts) W(2), AN(5), ~(5), BE(5)
CAPACITOR, MICA DIELECTRIC: 75G'PF, ±2%,
5OOVDCW; MIL type CM06FD751G03.
CAPACITOR, FmD, CERAMIC )):;:ELECTRIC: 47000PF,
:t10%, 50VDCWJ MIL type CK05B~73K.
SEMICONDUCTOR DEVICE, DIODE: Silicon, medium
power, 30 Amp, 50VDC, mfr 03877, part no.
SR1595, 90536, dwg 7901637-05.
(Attaching Parts) D(8)
SEMICONDUCTOR DEVICE, DIODE: Power, 12 AMP,
400VAC; MIL type 1N3893.
(Attaching Parts) B(l), J(l), AX(l), BM(l)
Same as 5A7CRl (item'no. 20)
thru
5A7CR9
5A7CRlO
5A7CRll
5A7CRl2
5A7CRl3
5A7CRl4
5A7CRl5
5A7CRl6
5A7Ql
5A7Q2
5A7Q3
5A7Q4
RECTIFIER, SEMICONDUCTOR DEVICE: Doubler and
CT assemblies, 100VDC, 10 AMP; mfr 12969,
part no. 655-082-1 90536, dwg 7903528-00.
(Attaching Parts~ I(l), AI(l), AV(l), BC(l)
RECTIFIER, SEMICONDUCTOR DEVICE: Doubler and
CT assemblies, 100VDC, 10 AMP; mfr 12969,
part no. 655-083-1 90536, dWg 7903528-06. _
(Attaching Parts~ I(3), AI(3), AV(,,), BC(3)
RECTIFIER, SEMICONDUCTOR DEVICE: Unitized,
3-phase, full wave, 3 AMP, 400V piv per leg;
mfr 12929, part no. 691-4, 90536, dwg
7904496-03.
(Attaching Parts) Z(6), BI(6)
TRANSISTOR: NPN, silicon, power, high voltage,
325VDC, looW; mfr 21845, part no. SDT8821 ,
•
90536, dwg 7901448-00.
(Attaching Parts) C(3),E(3), AY(3), BN(3)
TRANSISTOR: NPN, silicon, power, Darlington;
mfr 04713, part no.'MJlOOO, 90536, dwg
7904415-00.
(Attachin~ Parts) A(l), I(2), AI(2), AV(2),
BC(2), BL(2)
TRANSISTOR: MPN,' ,silicon, power, Darlington,
80VDC; mfr 04713, part no. M.TI..031.. , 90536,
dv~ 7904256-01.
{Attachin~ PartA) A(2) I(4},AI(4), AV(4),
BC(4)"BL{4)
.
"
7-17
TABLE 7-2.
DATA PROCESSING SET AN,/UYK-20(V) AND AN,/UYK-20X(V'), PARTS LIST (ceNT.)
Reference
Designation
'Figure
Notes
5A7Q5
5A7Q6
5A7lU
thru
5A7R4
5A7U1
Power Supply PP6
6L1
6P1
6P2
6T1
6TE1
'6TB2
bA1C2
6A1C)
7-18
Name and Description
Same as 5A7~
(item no. 31)
RESIST("\R, FIXED, WIREHC'UND:
MIL type RW69VRlO.
0.10 ohm ±10%, .3W;
HTTEGRATED CIRCUIT, VOLTAGE REGULATr::R: Mfr
182.34, part no. RC5109K, 905.36, dwg
7904270-01.
(Attachin~ Parts) A(l), 1(2), AI(2), AV(2),
BC(2), BL(2)
CONTACT, ELECTRICAL: Male, crimp type, 22AWG,
blue color code, 0.56 in. long; mfr 16512,
part no. 540176, 905.36, dwg 790.3660-01 (42).
/UYK-20(V)
(Unit 6)
POWER SUPPLY PP/UYK-20(V): Provides power
to each of the units within the data processor cabinet, operating power 208V, 400HZ,
.3-phase ~; mfr 90536, part no. 7101995-00.
CHC'KE ASSEMBLY, ELECTRICAL: Mfr 905.36, part
no. 7101974-00.
(Attaching Parts) !Jr(2), 1:.X(2), BE(2)
CCNNECT0R, PLUG, ELECTRIC~'c!.: l~ale; r.lfr 905.36,
n~rt no. 710188.3-00 •
. (.lttA.chinp, Parts) t,C(4), AU( 4)
TR\NSFnp~R ASSEMBLY:
Mfr 905.36, part no.
7126.376-00.
(Attaching Parts) l.n(6) ,,\1(6), BE(6)
not used
TERNINAL B'.'i.RD: E!'lrrier type, 5 tenninn1s; mfr
753~2, P'lrt no • .35"4-2?-05-O01, 90536, dwe
901~r62-09 •
C'.ttllchi"~ Pflrts) I(2), AI(2), '.V(2), ~C(2),
BI(2)
. .
ELECTRCHIC C'll!p~'HErrTS J1SSEl·IDLY: 3-phase, 400HZ,
contains 3 capacitors and 1 choke; mfr 905.36,
part no. 7101982-00.
(Attaching Parts) :'::(4), .'.1:(4)', B:S(4)
C.'.PACI':''''P., FIXSD, F:I.ECTP.(l.YTIC: iJ. can, 68 r UF,
±15%, 250"; HIL tyt)e CE71C681H.
(Attaching Parts) AN(2), BE(2)
CAPACITC:R, FIXED, ELECTRCLYTIC: 12i'UF, -15%,
±30%, 150V; mfr 56289, part no.
112Dl27C3150Yl, 90536, dwp 79016.35-1.3.
NUI!lber
(Item)
TABLE 7-2.
DATA
Reference
Designation
6A1Ll
6A2
6A2TB1
6A2TB2
6A2TB3
6A2TB4
6A2TB5
6A3
6A4
6A4C1
6A4C2
PROCESSING SET AN;UIK-20(V) AND AN/UYK-20X(V), PARTS LIST (CONT.)
Notes
Figure
Name and Description
NUlDbe~
(Item)
PLATE ASSEMBLY, CHOKE: Mfto 90536, part no.
7101987-00.
(Attaching Parts) AJ(4), AV(4)
CUTPUT FILTER ASSEMBLY: Contains 2 capacitor
boards, 1 inductor choke assy, and- 3
terminal boards; mfr 90536, part no.
7101978-00.
(Attaching Parts) AN(6), .U(6), BE(6)
not used
TERMINAL BOARD:. Barrier type, 7 terminals; mfr
75382, part no. 600AY7, 90536, dwg
904862-11.
(Attaching Parts) AE(8), BC(8), BH(8)
TERMINAL BOARD: Barrier type, 4 terminals; mfr
75382, part no. 600AY4, 90536, dwg
904862-05.
(Attaching Parts) P.E(4), BC(4), BH(4)
CAPACITOR BOARD~SSEMBLY: 13 capa9it6rs~and 2
resistors mtd on board, epoxyed; mfr 90536,
part no. 7101951-00.
(Attaching Parts) G(4), U(4), AU(4), BB(4)
CAPACITOR BOARD ASSEMBLY: 19 capacitors and 2
resistors mtd on board, epo~Jed; mfr 90536,
part no. 7101952-00.
(Attaching Parts) G(Jj.), U(4), AU(4), BB(4)
INDUCTOR CUnI:E ASSEMBLY: 8 chokes mtd on plate,
epoxyed; mfr 90536~ part no. 7101932-00.
(Attaching Parts) 1(4), BI(4)
FILTER ASSEMBLY, INPUT: 6 capacitors and 9
chokes mtd in chassis, epoxyed; mfr 90536,
part no. 7101979~1.
(Attaching Parts) AN(4), AX(4), BE(4)
ELECTRONIC COMPONENTS ASSEMBLY: Contains 2.
capacitors, 3 resistors, and 1 transformer
mtd on bracket; mfr 90536, part no.
7101980-00.
(Attaching Parts)·AN(3), AX(3), BE(3)
CAPACITOR, l"IXED, PAPER DIELECTRIC.: 1.0UF,
±lO%, 400VDCW; MIL type CV09JUKEl05KM.
CAPACITOR, FIXED, GLASS DIELECTRIC: 5100PF,
±10%, 300VDCH; mfr 14674, part no.
CY20C512K, 90536, dwg 4912284-16.
RESISTOR, FIXED, WIRE1.J'(1UND: 0.1 ohm, ±1%, 20\-1;
MIL type RE70GRlOO.
(Attaching Parts) G(2), T(2)"AU(2), BB(2)
7-19
TABLE 7-2.
DATA PRrCESSINGSET AN/UYK-20{V) AND AN/UYK-20X(V), PARTS LIST (CnNT.)
Reference
Designation
6A4R2
6A4R3
6:.!.. Tl
6A5
6A6
6A7
6:c7C1
6A7C2
6A7C3
6A7CRl
thru
6A7CB4
6A7CR5
6A7CR6
thru
Figure
Notes
Name and Description
RESISTOR, FmD, FILM: 20000 ohm, ±2%, 2W;
MIL type M22684-04-0159.
RESISTOR, Fn'"ED, HlREW'UND: 1 ohm, ±1%, 5H;
HIL type' RE60G1ROO.
(:.ttllchinp: Parts) P(2), S(2), !3G(2)
"'?_·.~;SF·mIER, prT:TER, STEPn'·1m:
Control, single
phase, 50-400HZ; mfr 16513, pa.rt no.
HC4518, 90536, dwg 790L~726-00.
(Attaching Parts) 1(2), ~(2), AV(2), BC(21
TRANSFr'RMER cnIL ASSEMBLY: 2 transfonners mtd
in bracket, epo~ed; mfr 90536, part no.
'7101981-00.
(Attaching Parts) A!l(4), AX(4), BE(4)
CIRCUIT CARD ASSEt-IDLY, CrrfrRoL: Plug-in type,
contains components epo~ed on printed wiring
board; mfr 90536, pa.rt no. 7119455-00.
HEAT EXCHANGER ASSEHBLY: Contains 3 capacitors,
16 diodes, 6 transistors, 4 resistors, and 1
.integrFited circuit; Nfr 90536, pnrt nne
710lP,77-00.
C'"ttachi.'1g PFirts) :1(2), .1;.11(5), AX(5), BE(5)
C;i.P: ..CITR, HICA DmL3CT~IC: 75 "PF, ±2%, 500VDCl~
HIL type CH06FD751G03.
CAPACITf'R, FIXED, CERAllIC DIELECTRIC: 47000PF,
±10%, 50VDCW; MIL type CK05BX473K.
SEMICONDUCTOR DEVICE, DIODE: Silicon, medium
power, 30 amp, 50VDCj mfr 03877, part no.
SRl595, 90536, dwg 7901637-05.
(Attaching Parts) D(8)
SEMICOmUCTCR DEVICE, DIODE: Power, 12 AMP,
400 VAC; MIL type 1N3893.
(Attaching Parts) B(l),J(l), AX(l), EM{l)
Same tl S 6.',7CHI (itam. no. 20 )
6.i~7CR9
6 JI.'7CRlO
·6A'7CR11
6A'7CRl2
6A'7CR13
7-20
R~CTIFIER,
SEllIC:"'lmUCT~R DEVICE:
Doubler and
CT assemblies, 100VDC, 10 Al1P; mfr 12969,
pFirt no. 655-0P?-1 '90536, dwg 7903528-00.
(Attaching Parts~ 1(1), AI{l), AV(l), BC{l)
RECTIFIER, SEMIcr:NDUCTnR DEVICE: Doubler and
CT assemblies, 100VDC, 10 AMP; mfr 12969,
part no. 655-083-1 90536, dwg 7903528-06.
(Attaching Parts~ 1(3), AI(3), AV(3), BC(3)
Number
(Item)
TABLE 7-2.
DATA PROCESSING SET AN/UYK-20(V)' AND AN/UYK-20X(V), PARTS LIST (CONT.)
Reference
Designation
Figure
Notes
6A7cRi4
6A7CRl.5
6A7CRl.6
6A7Ql
6A7Q.2
6A7Q3
6A7Q4
6A7Q5
6A7Q6
6A7Rl
thru
6A7R4
6A7U1
Power Supply 1'1'7
7L1
71'1
71'2
Name and Description
RECTIFIER, SEMICONDUCTOR D~VICE:' Unitized,
3-phase, full wave, 3 AMP, 400V piv per leg;
mir 12929, part no. 691-4, 90536, dwg
7904496-03.
.
(Attaching Parts) Z(6), BI(6)
.
TRANSISTOR: NPN,' silicon, power, high voltage,
325VDC, 100W; mfr 21845, part no. SDT8821,
90536, dwg 7901448-00.
.
(Attaching Parts) C(3), B(3), ."oY(3), mr(3)
TRANSIST'IR: NPN, silicon, power, Darlington;
mfr 04713, part no. HJ1000, 90536, dwg
7904415-00.
.
(Attachin~ Parts) A(l), 1(2), AI(2), AV(2),
BC(~), BL(2) " ..
TRANSISTOR: NPN, silicon, pouer, Darlington,
80VDC; mfr 04713, part no. HJ4034, 90536, dwg
7904256-01.
(Attachin~ Parts) A(2), I(4), AI(4), A.V(4)
BC(4), BL(4)
.
Same as 6A7Ql (item no. 31)
p..ES;rSTC'R, FIXED, t-IIREWnmD:
3~·r; HIL type RH69VRlO.
0.10 ohm,.±10%,
INTEGRATED CIRCUIT, VOLTAGE REG:UU.TOR: Mfr
18234, part no. RC5109K, 90536, dwg
7904270-01.
,
(Attaching Parts) A(l), I(2), A!(2), AV(2)
BC(2), BL(2)
C0NTACT, ELECTRICAL: Male, crimp type 22A~·iG,
blue color code, 0.56 in. lone; rofr 16512,
part no. 540176, 99536, dwg 7903660-01 (42).
/UYK-20(V) (Unit 7)
peWER SUPPLY 1'1'-"
/UYK-20(V) : Provides power
to each of the units within the data processor
cabinet, operating power 115V, 400HZ, single
phase; mfr 90536, part no. 7101875-00.
CHOKE ASSEMBLY, ELECTRICAL: Mrr 90536, part no.
7101974-00.
(Attaching Parts) AN(2), AX(2), BE(2)
CONNECTOR, PLUG, ELECTRICAL: ~fule; rofr 90536,
part no. 7101883-00.
(Attaching Parts) AC(4), AU(4)
Number
(Item)
TABLE 7-2.
DATA PReCESSING 'SET AN/UIK-20(V) AND AN/UIK-20X(V), PARTS LIST (CONT.)
Reference
Designation
7TB1
7TB2
7A1
7A2
7A2TB1
7A2TB2
7A2TB3
7A2TB4
7A~TB5
7A3
7A3Cl
7-22
Figure
Notes
Name and Description
not used
TERHINAL Bi·~"..RD: BArrier type, 5 terminals; mfr
75382, part no. 354-28-05-001, 90536, dwg
904862-09.
,
(Attaching Parts) G(2), AF(2), AU(2), BB(2)
CAPACITcR ASSEMBLY: Single phase, 400HZ,
contains 3 capacitors; mfr 90536, part no.
7128002-00.
(Attaching Parts) LU(4) , XX(4), m::(Jj.)
CAPACIT"'R, FIXF:D, EU:CTTr'LYTIC: lU can, 680UF,
+15%, 250V; HIL type CE71C68U1.
TAttaching Parts) AN(2), BE(2)
CAPACITnR,FIXED ELECTRCLYTIC: 120UF, -15%,
+30%, 150V; mfr 56289, part no.
112D127C3150Yl, 90536, dwg 7901635-13.
CUTPUT FILTE:l ASSElffiLY: Contains 2 cllp9.citor
boards, 1. inductor choke assy, and 3 terminll1
bo~rds; mfr 90536, ~~rt no. 7101978-00.
(f.ttachine Parts) ~'Jl'(6), AX(6), m:(6)
not used
TERHIWiL BCARD: Barrier type, 7 terminals;
mfr 75382, part no. 600AY7, 90536, dwg
904862-11.
(Attaching Parts) BC(S), AE(8), BH(8)
TERMINAL BIlARD: Barrier type,' '4 terminals; mfr
75382, part no. 600AY4, 90536, ,dwg 904862-05.
(Attaching Parts) BC(4), AE(4), BH(4)
CAPACITOR BOARD ASSEMBLY: 13 Capacitors and 2
resistors mtd on board, epoxyed; mfr 90536,
part no.'7101951-00. .
(Attaching Parts) G(4), U(4), AU(4), BB(4)
C~ACITOR BOARD'ASSEMBL~i 19 capacitors and
2 resistors mtd on board, epo:xyed; mfr
90536, part no. 7101952-00.
(Attaching Part~) G(4), U(4), AU(4), BB(4)
INDUCTOR CHOKE ASSEMBLY: 8 chokes mtd on plate,
epoxyed; mfr 90536t 'part no 7101932-00.
(Attaching Parts) 1'(4), BI (4)
FILTER ASSEMBLY, INPUT: 400HZ single phase, 1
capacitor, 1 terminal board, and 2 chokes mtd
in chassis; mfr 90536, part no. 7128001-00.
(Attaching Parts) AN(4), AX(4), BE(4)
CAPACIT()R FIXED, PLASTIC DIELECTRIC: 2. 5UF ,
±10%, 400VDCH; mfr 56289, part no.
260P25594S~90536, dwg 7903001-13.
Number
(Item)
TABLE 7-2.
DATA PROCESSING SET AN/trnc-20 (V) AND AN/UYK-20X( V) , PARTS LIST (CONT.)
Reference
Designation
7A311
7A3L2
7A3TBl
7A4
7A4C1
7A4C2
7A4Rl
7A4R2
7A4R3
7A4T1
7A5
Figure
Notes
Numoor
Name and Description
(Item)
CHOKE: Mrr 90536, part no. 7101977-15.
Same as 7TB2 (item no. 26)
(Attaching Part~AD(2), AU(2), BB(2)
ELECTRONIC COMPONENTS ASSEMBLY: Contains 2
capacitors, 3 resistors, and 1 transformer
mtd on bracket; mfr 90536, part no.
7101980-00.
(Attaching Parts) AM(3), AW(3), BD(3)
CAPACITOR, FIXED, PAPER DIELECTRIC: 1.0UF,
±10%, 400VDCW; MIL type CV09A1KE105KM.
CAPACITOR, FIXED, GLASS DIELECTRIC: 5100PF,
±10%, 300VDCW; mfr 14674, part no. CY20C512K,
90536, dwg 4912284-16.
RESISTOR, FIXED, WIREWOUND: 0.1 ohm, ±1%, 20W;
MIL type RE70GIUOO.
(Attaching Pal~s)'G(2), T(2), AU(2), BB(2)
RESISTOR, FIXED, FILM: 20000 ohm, ±2%, 2W;
MIL type M22684-04-0159.
RESISTOR, FmD WIREi-1OUND: 1 ohm, ±1%, 5W; MIL
type RE60G1ROO.
(Attaching Parts) P(2), S(2), BG(2)
TR~SFORMER, POv~R STEPDGWN:
Control single
phase, 50-400HZ; mfr 16513, part no. MC4518,
90536, dwg 7904726-00.
(Attaching Parts) I(2), Y(2), AV(2), BC(2)
TRANSFCID1ER C:IL ASSEHBLY: 2 transformers mtd
in bracket, epoA~ed; nfr 90536, p~rt no.
7101921-00.
( . ' tt fl CI1l!l.g
,.
"y (! ) ':l"p ( / )
...':') ~r t)
S
"','T
.. (L )
~."cr~D .".S.s::::IIT3LY, CO'TTT).OL:
l'lu{"7-in t:rpc,
cO'ltains cOI'lponents epo:::;:rod on printed
uirine board; mfr 90536, part no. 7119455-00.
I{El~T F.JCCIL. . NGER ASSEMBLY:
ContR ins 3 capacitors,
14 diodes, 6 transistors, 4 resisters, and 1
integrated circuit; mfr 90536, part no.
7101877-01.
(Atte.ching Parts) W(2), AN(5), AX(5), BE(5)
CAPACIT0R, MICA DIELECTRIC: 750PF, ±2%,
500VDC1;1; HIL type CH06FD751G03.
CAPACIT~IR, FIXED, CERAHIC, DIELECTRIC:
47000PF,
±10%, 50VDCH; MIL type cr:05BX473K.
SENICClNDUCT(~R DEVICE, DIODE:
Silicon, medium
power, 30 ~{P, 50VDC; mfr 03877, part no.
SR1595, 90536, dw~ 7901637-05.
(Attaching Part) D(8)
d
.;.,
,. ' . .
,
,
,
""J
!.
CI:r:.CT.:'IT
71>.7
7A7C1
7A7C2
7A7C3
7A7CIU
thru
7A7CR4
7-23
TABLE 7-2.
D:S:.
Reference
Designation
7A7CP/;
thru
7A7CR9
7A7CRlO
7A7CPJ.l
7/,7CRl2
7A7CR.13
7A7CfJ.4
7A7Ql
7A7Q2
7A7Q3
7A7QL~
·7~\7o.5
7A7o.6
7A7FJ.
thru
7A7R4
7A7Ul
7A8
7A8Kl
7-24
PR1CE~;SING
Notes
:-;1':T AN/UYK-20(V) AND ANjuYY.-20X(V), PARTS LIST (cmn.)
Name and Description
SElITCi'NDUCT:'n DE'lICE, DIDE: Power, 12 !\MP,
400 VAC; MIL type 1113893.
C\ttaching Parts) B(l), J(l), A.,"C(1) BN(l)
1.me as 7A7CRl (item no. 20)
RECTIFIER, SEHIC",UDUCTrR DEVICE: Doubler and
CT assemblies, 100VDC, 10 AHP; mfr 12969,
part no. 655-082-1, 90536, dw~ 7903528-00.
(Attaching Parts 1(1), AI(l) AV(l), BC(l)
RECTIFIER, SEHICi;NDUCTCR DEVICE: Doubler and
CT assemblies 100VDC, 10 A}W; mfr 12969,
part no. 655-083-01, 90536, dw~ 7903528-06.
(Attaching Parts) 1(3), AI(3), AV(3), BC(3)
RECTIFIER, SEHIC(\NDUCT~)R DEVICE: Single phase,
full wave bridge, 25 AMP, 400V; mfr 12929,
part no. 655-081-4 90536,dw~ 7903529-03.
(Attaching Parts~ J(l), AP(l), AX(l), BE(l)
TRANSISTOR: nPN silicon, power, high voltage,
. 325VPC, 100W~~mfr'2l845, part no. SDT8821,
90536, dwg 7901448-00.
(Attaching Parts) C(3), E(3), AY(3) BN(3)
rRANSISTr'R: nPN silicon, power, Darlington; mfr
04713, part no. MJlOOO, 90536 dwg 7904415-00.
(Attachin~ Parts) A(l), I(2), AI(2), AV(2),
BC(2), BL(2)
Transistor; nPN, silicon, power, Darlington,
80VDC; mfr 04713, part no. MJ4034 , 90536, dwg
7904256-01.
(Attaching Parts)A(2), I(4),AI(4),AV(4),
13C(4), BL(4)
Same as 7A7Q1
(ite~ no. 31)
RESIST('R, FIXED, 1.1IREHr:mm:
HIL type Rl-169VIUO.
0.10 omr. ±10%, )'W;
IN'IEGRATED CIRCUIT, VOLTAGE REGULATOR: Mfr
18234, part no. RC5109K, 90536, dwg
7904270-01.
(Attachin~ Parts) A(l), 1(2), A!(2), AV(2),
13C(2), BL(2)
RELAY ASS~ffiLY: Contains 1 relay and 1 resistor mtd on bracket; mfr 90536, part no.
7126391-00.
(Attaching Parts) ~1(4), AW(4), BD(4)
RELAY ARMATURE: 3 spst contacts, 115VAC, 400HZ;
MIL type MS27418-1A.
(Attaching Parts) AV(4)
Figure
NUI!loor
(Item)
TABLE 7-2.
DATA PROCESSING SET AN/UYK-20 (V) AND AN/UYK-20X( V), PARTS LIST (CONT.)
Figure
Reference
Designation
7!SRl
Powr Supply
S
SLl
SP1
8P2
8Tl
STB1
STB2
SAl
8Ale1
SAlC2
SAlC3
8AlLl
8A2
SA2TB1
8A2TB2
N~e
Notes
and Description
RESISTOR, FIXED, WIREWOUND:. Sufge limiting,
)' ohm/.±l%, 5W; mtr 11502, part no. PW5446 ,
90536, dwg 7904765..()0.
CONTACT, ELECTRICAL: Male, crimp type" 22AW"
blue color code, 0.56 in. long; mtr. 16512,
part no. 540176, 90536, dwg .7903660"()1 (42).
Jp-
/UYK-20X(V)
(Unit 8)
POWER SUPPLY PP/U!K";'20X(V): Provides power
to each of the units ~thin the data
processor cabinet, operating power 115V, 60HZ,
3-phase delta; mtr 90536, part no.
71018S0"()0..
CHOKE ASSEMBLY, ELECTRICAL: Mfr 90536, part no.
7101974..()0.
(Attaching Parts) AN(2), AX(2), BE(2)
CONNECTOR, PLUg.ELECTRICAL_: Male, mfr 90536,
part no. 7101SS3..()0.
(Attaching Parts) AC(4), AU(4)
TRANSFORMER ASSEMBLY: Mfr 90536, part no.
712S010"()0.
(Attaching Parts) AN(6), AX(6), BE(6)
TERMINAL BOARD: "Barrier type, 5 'terminalsj 1Ilfr
75382, part no. 354-2S..()5-001; 90536, dwg
_
904862-09.
(Attaching Parts) H(2), AF(4)', AU(6), BB(2)
ELECTRONIC COMPONENTS ASSEMBLY: 3-phase, 400HZ,
contains 3 capacitors and 1 choke; mtr
90536, part no. 71019S2"()0.
(Attaching Parts) AN(4), AX(4), BE(4)
CAPACITOR, FIXED, ELECTROLYTIC: A1 can,6S0UF,
±15%, 250V; MIL tyPe CE71C681M.
(Attaching Parts) AN(2), BE(2)
.
CAPACITOR, FIXED, ELECTROLYTIC: 120UF, .15%,
+30%, 150V; mfr 56289, part no. 112Dl27C3150Yl,
90536, dwg 7901635-13.
PLATE ASSEMBLY, CHOKE: Mfr 90536, part no.
71019S7-00.
(Attaching Parts) AJ(4), ~V(4)
OUTPUT FILTER ASSEMBLY: Contains 2 capacitor
boards, 1 inductor choke assy, and 3 .
terminal boards; mfr 90536, part no.
7101978-00.
(Attaching Parts) !N(6), AX(6), BE(6)
Poot used
'
Numbe~
(Item)
TABLE 7-2.
DATA PRiJCESSING SET kN/UYK-20(V) AND ,AN/UYK-20X(V), PARTS LIST (CONT.)
Reference
Dosignation
SA2TB3
SA2TB4
BA2TB5
SA3
SA4
SA4C1
SA4C2
SA4Rl
SA4T1
SA5
SA6
7-26
Notes
Figure
Name and Description
TERMINAL BrARD: Barrier type, 7 terminals; mfr
753S2, part no. 600AY7, 90536, dwg 904S62-11.
(Attaching Parts)BC(S), AE(S), BH(S)
TERUINAL B0ARD: Barrier type, 4 terminals; mfr
753S2, part no. 600AY4t 90536t dwg.904S62-05.
(Attaching Parts) BC(4J, J\E(4J, BH(4)
CAPAC1TnR. B'AP..D ASSEMBLY: 13 Capacitors and 2
resistors rotd on board, epoxyed; mfr 90536,
part no. 7101951-00.
,
(Attaching Parts) G{4), U(4), AU{4), BB(4)
CAPAC1Tr:R B~ARD ASSEHBLY: 19 capacitors and 2
resistors rotd on board, epoxyed; mfr 90536,
part no. 7101952-00.
(Attaching Parts) G(4), U(4), AU(4), BB(4)
INDUCTiR CHnKE ASSEMBLY: S chokes mtd on plate,
epoxyed; mfr 90536, part no. 7101932-00.
(Attaching Parts) I(4), BU(4)
not used
ELECTR()NIC cnMP(NENTS .A.SSm-ffiLY: Contains 2
capacitors, 3 resistors, and 1 transformer
mtd on bracket; mfr 90536, part no.
7101980-00.
(Attaching Parts) M~(3), AW(3), BD(3)
CAPAC1TC'R, FIXED, PAPER DIELECTRIC: ., .nm ± 10~
400VDCW; MIL type CV09A1KE105l{M.
CAPACITOR, FmD, GLASS DIELECTRIC: 51 JOPF,
±10,. 300VDCW; mfr 14674t part no. CY20C512K,
90536, dwg 49122S4-16.
RESISTrR, FIXED, WlRE,,,cUND: 0.1 ohm, ± 1%, 20W;
MIL type RE70GRlOO.
(Attaching Parts) G(2), T(2), AU(2), BB(2)
RESISTOR, FIXED, FIIJ:f: :"0(')00 t"lhm} ±2%, 2"-1; MIL
type M226S4-04-0159.
RESIST "R, FIXED, "'IREW~)UND: 1 ohm, ±1%, 5\"; !'IlL
type RF..60G1ROO.
(Attaching Parts) P(2), S(2), BG{2)
TRAi'TSF('Rl-mR, pr:~'l!m, STEPDr~m: Control single
~hase, 50-400HZ; mfr 16513, part no. HC451S,
90536, dwg 7904726-00.
(Attaching Parts) 1(2). Y(2), AV(2), BC(2)
TRA11SFr"RMER Cr.IL ASSEHBLY: 2 transformers mtd ir.
bracket, epoxyed; mfr 90536, part no.
7101981-00.
(Attaching Parts) AlT(4), AX(4), BE (4')
CIRCUIT Cl'LRD ASSEMBLY, C!lNTRrL,; plug-in type,
contains components epoxyed on printed
wiring board; mfr 90536, part no. 7119455-00.
NUl!'loor
(Item)
TABLE 7-2.
DATA PROCESSING SET AN,/UlK -20(V) AND AN/UIK-20X(V), PARTS LIST (CONT.)
Referenoe
Designation
SA7C1
SA7C2
SA7C.3
SA7CRl
thru
SA7CR4
SA7CR5
SA7CRl1
SA7CRl2
SA7CRJ,.3
SA7CRl4
8A7CRl5
8A7CRl6
SA7Q2
SA7Q.3
SA7Q4
SA7Q5
SA7Q6
Name and Desoription
Number
(Item)
HEAT EXCHANGER ASSEMBLY: Contalns.3 capacitors,
16 diodes, 6 transistors, 4 resistors, and 1
integrated circuit; mfr 905.36, part no.
7101S77-OO.
.
(Attaching Parts) W(2), AN(5), ~(5), BE(5)
CAPACITOR, MICA DIELICTRIC: 750PF, ±2%,
500VDCW; MIL type CM06FD751GO.3.
CAPACITOR, F,IXED, CERAMIC DIELECTRIC: 47000PF,
±10%, 50VDCW; MIL type CK05B~7.3K.
SEMICONDUCTOR DEVICE, DIODE: Silicon, medium
power, .30 AMP, 50VDC; mfr 0.3877, part no.
SRl595, 905.36, dwg 79016.37-05.
(Attaching Parts) D(S)
SEMICONDUCTOR DEVICE, DIODE: Power, 12 AMP,
400VAC; MIL type 1N.389.3.
(Attaching Parts) B(l), J(l), AX(l), EM(l)
Same as 8A..7CRl (itam no. 20)
SA7
SA7CR6
thru
SA7CR9
SA7CRlO
Figure
Notes
I
RECTIFIER, SEMICONDUCTOR DEVICE: f:oub1er and CT
assemblies, 100V»C, 10 AMP; mfr 12969, part no
655-OS2-1, 905.36, dwg 790.3528-00.
.
(Attaching Parts) 1(1),' AI(l), AV(l), BC(l)
RECTIFIER,. SEMICONDUCTOR DEVICE: Doubler and
CT assemblies, 100VDC, 10 AMP; mfr 12969, part
no. 655-OS.3-1, 905.36, dwg 790.3528-06.
(Attaching Parts) 1(.3), AI(.3), AV(.3), BC(.3)
RECTIFIER, SEMIcnNDUCTrR DEVICE: Unitized·
.3-phase, full wave, .3 :JP, L.OOV piv per lee;
nfr l2~29, p~rt no. 691-4, ~0536, GW~
790/J.96-03.
(:.ttpchinz Parts) Z(t)), rI(6)
T::.·..:r3IsT'·!\.: !I?lJ, silicon, pm..rer, hirrh voltap:e,
3~5VDC, 100:1; mfr 21845, pr:trt no. SDT8S2l,
90536, dwg 7901448-00.
(Attaching Parts) C(3), E(3), AY(3), BN(.3)
TRANSISTC:R: NPN, silicon, power, Darlington;
mfr 04713, part no. MJlOOO, 90536, dwg
7004415-00.
(Attachin~ Parts) A(l), 1(2), AI(2), AV(2),
BC(2), BL(2)
TRANS ISTr'R: NBN, silicon, power, Darlington,
SOVDC; mfr 04713, part no. MJ40.34, 90536, dwg
7904256-01.
(Attachin~ Parts) A(2), 1(4), AI(4), AV(4),
BC(4), BL(4)
Same as SA7Ql
(item. no • .31)
.
7-27
TABLE 7-2.
DATA PROCESSING sET AN/UYK-20(V) AND' AN/UYK-20X(V), PARTS LIST (C~NT.)
Reference
Designation
Figure
Notes
8A7Rl
thru
8A7R4
8A7Ul
Pbwer Supply'PP()
/
9Ll
9P1
9P2
9T1
9TB1
9TB2
9Al
9!,lC1
9!.J.C2 '
9A1C3
9AlL1
7-28
Name and Description
RESISTOR, FInn, HIRE1/rUND:
3W; MIL type RW69VRlO.
0.10 ohm, ±10%,
INTEGRATED CIRCUIT, V(lLTAGE REGULATr'R: Hfr·
18234, part no. RC5109E, 90536, d'\org 790A270-O
(Attachin~ Parts) :"(1), 1(2), AI(2), 1JT(2) ,
DC(2), DL(2)
.
C' !1TLCT BLECTRICf.L: Ua.lG, crimp type, 22ANG,
blue color code, 0.56 in. 1011£\; mf'r 16512,
~art no. 540176, 90536, dwe 7903660-01 (42).
/UYE-20X(V)
(Unit 9)
P ~:::;'J. SU::?PLY pp/UYI:-20X(V) : Provides
power to each of the units within tho data
processor cabinet, opcr"l.tin~ pOl1Or 20[;7,
60HZ, .3-phase wye; rafr 90536, part no.
7101990-00.
CIlKS ASS~·mLY, EL3CTRICAL: 11fr 90536, part no
7101974-00.
, (Attaching Parts) AN(2), AX(2), BE.(2)
cr'NNECTC'R, PLUG ELECTRICAL: Male, mf'r 90536,
part no. 7101883-00.
(Attaching Parts) AC(4), AU(4)
TRANSFORMER ASSEMBLY: Mfr 90536, part no.
7128010-00.
(Attaching Parts) AN(6), A[(6), BB(6)
TERMINAL BriARD: Barrier type, 5 tenninals;
mf'r 75382, part no. 354-28-05-001, 90536, d",~
90/~862-O9 •
(Attaching Parts) II(2), J:~(4), AU(6), BB(2)
ELECTW'IHC C:"'Hpt'lreNTS ASSENBLY: 3-phase, 1~OOII1'l
contains 3 capacitors and 1 choke; mfr
90536 part no. 7101982~0.
(Attaching Parts) JJr(L~), t:..'X:(4), BE(lJ
CAPACIT'R, FIXED, SLECT::1rLYTIC: ~'J. can, 68 UF,
±15%,,250V; HIL tyPe CmC681H.
(Attaching Parts) lJi(2), BE(2)
CAPACIT-'R, FIX'8D, :<;LBCTnrr"YTIC: 120UF, -15%,
+30%, 150V; mf'r 56289, part no.
112D127C3150Yl, 90536, dwg 7901635-1~
PLATE ASSEI·ffiLY, CH"KE: Hfr 90536, part no.
7101987-00.
(Attaching Parts) AJ(4), AV(4)
Numbe~
(Item)
Reference
Designation
9A2
Figure
Notes
FILTER ASSEMBLY: Contains 2 capacitor
boards,. 1. inductor choke ass:;", and 3
terminal boards; mfr 90536, Dart no.
(AttachL~g Parte)
9~l'B5
(Item)
~UTPUT
710197S-00.
9A2TB1
9A2TB2
9A2TB3
9A2TB4
Ntmlbe~
Name and Description
not used
AN(6),
~~(6), ~E(6)
Barrier t~rpe, 7 terminals; mfr
753~2, part no. 600AY7, 9053?, dwg 904862-11.
(Attaching Parts) AE(8), BCCS), BH(e)
TERUIN1..L BIlARD: Barrier t:rpe, 4 t~nT.:~na1s, mfr
753 Et2, part no. 600AY4, 90536, dug 9()M~62-05.
(!~ttc,ching Parts) I.E (4) , BC(!J, I3II(4)
CAPACITOR BOARD ASSEMBLY: 13 C":/'lcttorc anc:. 2
resistors [ltd on board, epoxyed; nfr
C)0536, part no. 71019:;1-00.
(:..ttachine rarts) G(Jj-), U(4), AU(4), LJVJ
T:2r'J·II!TM.
B~.AIlD:
CAPACITfn J3nf~!t,.., l~SS~mL:~:
~-""l
r nsistor"
v
.
v.... on. . hc"'r~
~~~3~
r~
.. \ ..../ "", J.JU v ~ o. "1~'~~~
to..J
y
I ...... , .....
oI.,..\.
j
, .. ,
\.I.....L..',;, .. -
1(" .;,~.~p:-tcit0rr r . ~r,~
,.,
0"0--",,(1."
""~
J.,J
-\."...;,.~ J
.:...J..
...
c'"
.!. •
....
(Attaching Parts) G(4), U(4), AU(4), BB(4)
9A4Cl
INDUC'i.\.R Cli . :L:': ..'ISSEHBL7: ~ cllol~es !:ltd on plate"
epoxyed; mfr 90536~ pnrt no. 7101932-00.
(l:l.tt1.ching Parts) I(4), 13I(4)
!'lot used
l:;r.::CTlL lIIC C'}1P(",NENTS ASS:lIDLY: Conta.i!:s 2
c.:lpacitors, 3 resistors, CL"1c1 1 t:>.':.'..'1sf'croer
:.:td on hracket; nfr 90536, part no.
7101980-00.
(Atta.chi~l:: Pa.rt::;) AI·l(3), X:(3), DD(3)
CAPACIT .. R, FIXED, P..1.PZH DI3WC'.L,'IU::;: 1.\/UF,
'lon'
lfTL ~lJ~-pe ''''''1''\('1
'1.,j.,J.:.
·'~Oe:.·
"
~
ilJ, I.,.JOO-1T'C"
",/J.) ~.;"'~
',j.,.u.
• .. 1.6..,,£,'.i..
C~p....CIT:::;n, FJ:::rm, GUSS D:r:.;:::....:;C:..'l.IC:
5100PF,
±10;;, .'300VDCilj ufr l467!" p3.~.'t no;, CY2JC5121.
9C53 6, dHG /;.9122S4-16.
P.::,sIS7CR, FIXED, lIIru::: ::;..-::); C.1 O:!Ll, j;:l;::, 2CU;
~iIL t:'Pe P..E7001:l00.
(:~ttr'.c~~:tn~.; :c~rts) G(;:», ::.(:::;, l~U(2), BB(2)
RESI5'l'-n, FIXED, I:'ILH: 20000 onm, +2%, 2W; MIL
type M226CI,.-04.-0159.
- .
IG:~:::G7:.:-:, fI:rr::.>, liIRE.·;, Uin-J:
1 olm, ±l~~. 5::; un,
tY'~e RE60G1noo.
(Attachinc Fl:rts) P(2), :::(2), DG(?)
~~~-~~.:;~: .=~::;:~, r'·.i~R, STEPD . j:.1~·:
Contrnl, ~incl~
,')"""0 'if)_~rv'\IT'7.
1'
~1
1'~rt "'0
~ ...... ., , .,.'
' ';' ' ' ' u.., 1"'-t'~·
.~. . _
. ).. .. ~-',
~ . ._
'.'. 1,'CLr.,r\
_::.>_."
90536, d\.J'C: 790L:,726.JJo.
(la.tt~chine PartsY .I(2), ~(2), .. ;l(~), DC(~)
lJJi. ..
9A4R3
j,
7.. 29
TABLE 7-2.
DATA PROCESSING SET AN/U!K-20(V) AND AN/UYK-20X(V), PARTS LIST (CONT.)
Reference
Designation
9,',5
9A7
9A7C1
9A7C2
9A7C3
9A7CRl
thru
9A7Cft4
9A7CR5
9A7CR6
thru
9A7CR9
9A7CRlO
'<),'..7C:D.l
9A7Cr..l2
9A7CP..l3
9A7CP..l4
9A7C?15
9A7Cm6
9A7Q1·
9A7Q2
7-30
Figure
Notes
Name and Description
C II, .'·.S~~~~L~!: 2 trnnsfomcrs ntd
in bracket, sjlcY,':red; nfr 00536, part no.
7101981-00.
(J.ttaching Parts) .:';11(4), AX(4), BE(4)
CIRCUIT CARD ASSEr,IDLY, CCNTRr-:L: Plug-in type,
contains components epoxyed on printed wiring
board; mfr 90536, part no. 7119455-00.
HEAT EXCHANGER ASSEMBLY: Contains 3 capacitors,
16 diodes, 6 transistors, 4 resistors, and 1
integrated circuit; mfr 90536, part no.
7101877-00.
(Attaching Parts) W(2}, AN(5}, AX(5}, BE(5}
CAPACITOR, MICA DIELECTRIC: 750PF, ±2%, 500
VDCW; MIL type CM06FD751G03.
'CAPACITOR, FnED, CERAMIC DIELECTRIC: 47000PF,
±10%, 50VDCW; MIL type CK05BX473K.
SEMICONDUCTOR DEVICE, DIODE: Silicon, medium
power, 30 AMP, 50VDC; m.fr 03877, part no •.
SRl595, 90536, dwg 7901637-05.
(AttaChing Parts) D(8)
SEMICONDUCTOR DEVICE, DIODE: Power, 12 AMP,
400VAC; MIL type 1N3893.
(Attaching Parts) B(l), J(l), AX(l), EM(l)
Same as 9A7CRl (itam no. 20)
T::'~~~I~3;t"'r·:rJC1
RECTIFIER,. SEMICCNDUCTOR DEVICE: . Doubler and
CT assemblies, 100VDC, 10AHI'; mfr 12969,
part no. 655-082-1 90536, d'\.Tg 790352r-OO.
(Attachinl'" P~rts~ 1(1), .'~I(l), AV(l), BC(l)
R~CTIF:r::::R, Se:HIcrlIDUCTR DEVICE:
Doubler and
CT assemblies, 100VDC, 10 l'J.fi'; mfr 12969, part
no. 655-083-1, 90536, dwg 7903528-06.
(Attachine Parts) I(3), AI(3), ,W(3), DC{3)
RECTIFnR, SEHICnmUCTr'R DEVICE: Unitized,
3-phase, full "rave, 3 :.HP, 400V piv per leg;
lnfr 12929, part no. .691-4, 90536, dwg
7904496-03.
(Attaching Parts) Z(6}, BI(6} .
TRAUSISTOR: }lPN, silicon, power, high voltage,
325VDC, 100W; mfr 21845, part no. SDT8821,
90536, dwg 7901448-00.
.
(Attaching Parts) C(3), E(3}, AY(3), BN(3}
TRANSISTOR: NPN,si1icon1 power, Dar1ingtonJ
mfr 04713, part no. MJl000, 90536, dwg
7904415-00.
(Attachin~ Parts) A(l), I(2}, 'AI(2), AV(2),
BC(2}, BL(2)
Numbs%'
(Item)
TABLE 7-2. DATA PROCESSING SET AN/UIK-20(V) AND AN/UIK-20X(V), PARTS LIST (CONT.)
Reference
Designation
Figure
Notes
9A7Q5
9A7Q6
9A7I1
RESISTOR, FIXED, WIREWOUND:
311; MIL type RW'69VRJ.O.
thru·
9A7R4
9A701
10
lOCI
lOLl
lOP:
10P~
10TEl
10TB2
10Al
Name and Description
(Item)
TRANSISTOR: NPN, silicon, power -Darlingten,
80VDC; mfr 04713. part no. MJ4034, 90536, dvg
7904256-01.
(Attaching Parte) A(2), I(4), AI(4), AV(4),
BC(4), BL(4)
.
Same as" 9A7Q1 (item no. 31)
9A7Q3.
9A7Q4
Power ,Supply
Numbel1
0.10 ohm, ±10%,
.
INTEGRATED CIRCUIT, VOLTAGE REGULATOR: Mf'r
18234, part no. RC5109K, 90536, dvg
7904270-01.
(Attachin~ Parts) A(l), 1(2), AI(2), AV(2),
BC(2), BL(2)
CONTACT, ELECTRICAL: MaL e, I!rimp type,22AWG,
blue color code, 0.56 in. long; mfr 16512,
part no. 540176, 90536, dwg 7903660-01 (42t
tp-
/UY?:-20X(V)
(Unit 10)
FeHER SUPPLY PPjuYK-20X(V): Provides power
to each of the units within the data processor
cabinet, operating power 115V, 60HZ, single
phase; mfr 90536, part no. 7101885-00.
CAPACITOR, FmD, PAPER DIELECTRIC: 15UF, ±10%,
370VACH; mfr 56289, part no. 2QOP2176, 90536,
d'''f; 7901282-08.
(Attaching Parts) AlI(4), 1~X(4), BE(4)
CHI~I:E ASSID1BLY, ELECTRICAL:
Hfr 90536, part no.
7101974-00.
(Attaching Parts) AN(2), AX(2), BE(2)
CONNECTOR, PLUG, ELECTRICAL: Hale; mfr 90536,
part no. 7101883-00.
(Attaching Parts) AC(4), AU(4)
not used
TERMINAL BOARD: Barrier type, 5 tenninals; mfr
75382, part no. 354-28-05-001, 90536, dwg
904862-09.
(Attaching Parts) G(2), AF(2),'AU(2), BB(2)
CAPACITOR ASSEMBLY: Single phase, 60HZ,
contains 3 capacitors; mfr 90536, part no.
7126398-00.
(Attaching Parts) AN(4), AX(4), BE(4)
.
Reference
Designation
10llC1
10A1C2
10A1C3
10A2
10!\2TB1
10A2TB2
10A2TB3
10A2TB4
10A2TB5
1011.3
10A3TB1
101.4
10A4C1
1011.4C2
7-32
Notes
Figure
Name and Description
CAPACITCiR, FIXED, ELECTRr:LYTIC: Al can,
2200UF, ±18%, 250Vi MIL type CE71C222M.
(Attaching Parts) AQ(2), AZ(2)
CAPACITOR, FIXED ELECTRrLYTIC: . 12 f 'UF, -15%,
+30%, 150V; mfr 56289, part no.
112D127 C3150Yl, 90536, dwg 7901635-13.
r;UTPUT FILTER ASSEMBLY: Contains 2 capacitor
boards, 1 inductor choke assy, and 3
terminal boards; mfr 90536, part no.
7101978-00.
(Attaching Parts) AN(6), AX(6), BE(6)
not used
TERHTIfAL B!'ARD: Barrier type, 7 terminals; mfr
75382, part no. 600AY7, 90536, dwg 904862-11.
(Attaching Parts) AE(8), BC(8), BH(S)
TERMINAL BOARD: Barrier type, 4 terminals;
mfr 75382, part no. 600AY4, 90536, dwg
904862-05.
(Attaching Parts) AE(4), BC(4), BH(4)
CAPACITi'R B('ARD ASSEHBLY: 13 capacitors and 2
resistors mtd on board, epoxyed; mfr 90536,
part no. 7101951-00.
(Attaching Parts) G(4), U(4), AU(4), BB(4)
CAPACITOR BeARD ASSEMBLY: 19 capacitors and 2
resistors mtd on board, epoxyed; mfr 90536,
part no. 7101952-00.
(Attaching Parts) G(4), U(4), AU(4), BB(4)
INDUCTOR CHCKE ASSEHBLY: 8 chokes mtd on plate,
epoxyed; mfr 90536t part no. 7101932-00.
(Attaching Parts) 1(4), BI(4)
FILTER ASSEMBLY, INPUT: 60HZ single phase, 1
terminal board, and 3 chokes mtd in chassis,
epoxyed; mfr 90536 t part no. 7126397-00.
(Attaching Parts) AN(4)~ AX(4), BE(4)
Same as 10TB2 (item no. 26)
(Attaching Parts) AD(2), AU(2), BB(2)
ELECTRONIC CCMPnNENTS ASSEMBLY: Contains 2
capacitors, 3 resistors, and 1 transformer
mtd on bracket; mfr 90536, part no. 7101980-00
(Attaching Parts) AN(3), AW(3), BD(3)
CAPACITCR, FIXED, PAPER DIELECTRIC: l.r;UF, 90%
400VDCW; MIL type CV09AlKE105KM.
CAPACIToR, FIXED, GLASS DIELECTRIC: 5100PF,
±10%, 300VDCW; mfr 14674, part no. CY20C512K,
90536, dwg 4912284-16.
Number
(Item)
,
TABLE 7-2.
DATA PROCESSING SET AN/UlK-20(V) AND AN/UYK-20X(V), PARTS LIST (CONT.)
Reference
Designation
10A.4R1
10A4R2
10A4R3
10A4Tl
10AS
10A6
10A7
10A7C1
10A7C2
10A7C3
10A7CRl
thru
10A7CR4
10A':'CRS
10A7CR6
thru
10A7CR9
10A7CRlO
10A7CRll
10A7CRl2
10A7CRl3
Figure
Notes
Name and Description
RESISTOR, FIXED, WIREWGUND: 0.1 ohm ±1%, 20W;
MIL type RE70GRlOO.
(Attaching Parts) G(2), T(2), AU(2), BB(2)
RESISTOR, FIXED, FILM: 20000 ohm, ±2%, 2W;
MIL type M22684-04-o159.
RESISTOR, FIXED WIREWCUND: 1 ohm, ±1%, 5W; MIL
type RE60G1ROO.
(Attaching Parts) P(2) S(2) BG(2)
TRANSFORMER, POWER, STEPD~JN: . b'ontro1, single
phase, 50-400HZ; mfr 16513, part no. MC4S18,
90536, dwg 7904726-00.
.
(Attaching Parts) 1(2), Y(2), AV(2), BC(2)
TRANSFORMER COIL ASSEMBLY: 2 transformers mtd
in bracket, epoxyed; mfr 90536, part no.
7101981-00.
(AttaChing Parts) AN(4), AX(4), BE(4)
CIRCUIT CARD ASSEMBLY, CONTROL: Plug-in type,
contains components epoxyed on printed wiring
board; mfr 90536, part no. 711945S-00.
HEAT EXCHANGER ASSEMBLY: Contains 3 capacitors,
14 diodes, 6 trans~stors, 4 resistors, and 1
integrated circuit; mfr 90536, part no.
7101877-01.
(Attaching Parts) W(5), AN(S), AX(S), BE(5)
CAPACITOR, MICA DIELECTRIC: 750PF, ±2%,
500VDCW; MIL type CM06FD751G03.
CAPACITOR, FIXED, CERAMIC DIELECTRIC: a7000PF,
±10%, 50VDCW; MIL type CK05BX473K.
SEMICONDUCTOR DEVICE, .DIODE: Silicon, medium
power, 30 AMP, 50VDC; mfr 03877, part no.
SRl595, 90536, dwg 7901637-05.
(Attaching Parts) D(8)
.
SEMICONDUCTOR DEVICE, DIODE: Power 12 AMP,
400VAC; MIL type 1N3893.
(Attaching Parts) B(l), J(l), AX(l), BM(l)
Same as 10A7CRl (item no. 20)
RECTIFIER, SEMICONDUCTOR DEVICE: Doubler and CT
assemblies, 100VDC, 10. AMP; mfr 12969, part no
655-082-1, 90536, dwg 7903528-00.
(Attaching Parts) 1(1), AI(l), AV(l), BC(l)
RECTIFIER, SEMICONDUCTOR DEVICE: Doubler and CT
assemblies, 100VDC, 10 AMP; mfr 12969, part no.
655-083-1, 90536, dwg 7903528-06.
(Attaching Parts) I(3), AI(3), AV(3), BC(3)
NU1!loor
(Item)
TABLE7-2.
DATA PROCE.SSING SET AN/UYK-20(V) AND AN!UYK-20X(V), PARTS LIST (CONT.)
Reference
Designation
10A7Ctu4
10A7Ql
10A7Q2
lOA7Q3
10A7Q4
10A7Q5
10A7Q6
10A7RJ.
thru
10A'rn4
10A7U1
Fieure
Notes
NUI!1oor
Name and Description
(Iten)
RECTIFIER, SEMICt:NDUCTnR DEVICE: Single phase,
full wave bridge, 25AMP, 400V; mfr 12929,
part no. 655-08l-4t 90536, dwg 7903529-03.
(Attaching Parts) J(l), AP(l), AX(l), BE(l)
TRANSISTOR: NPN, silicon, power, high voltage,
325VDC, 100W; mfr 21845, part no. SDT882l,
90536, dwg 7901448-00.
(Attaching Parts) C(3), E(3), AY(3), BN(3)
TRANSISTOR: NPN, silicon, powe~, Darlington;
mfr 04713, part no. MJIOOO, 90536, dwg
7904415-00.
(Attachin~ Parts) A(l), I(2), AI(2), AV(2),
BC(2), BL(2)
TRANSISTOR: NPN, silicon, power, Darlington,
80VDC; mfr 04713, part no. }U4034, 90536, dwg
7904256-01.
(Attachin~ Parts) A(2), 1(4), AI(4), AV(4),
BC(4), BL(4)
Same as 10A7Q1 (item no. 31)
RESIST(m, FIXED, HIRE1·/':mm:
MIL type RH69VPJ.0.
INTEGRA.TED CEtCUIT, V· LT/,GE
0.10 ohm ±10%,
:rr;;.;GUL~·. T'
n:
3~1;
~;fr
18234, Il'lrt no. P,C5109::, 00536, dwe
7904270-01.
(Attaching Parts) le(l), I(2), !.I(2), .3(?),
10:.2:
13C(2), 13L(2)
rrSL.i.? ..L\SS'Sl:DLY:
Cont~ins
1 relnJ'" ~!1d 1
resistor ntd on brn.cl:et; mfr 90536, part no.
7126391-00.
(Attn.chinr, Parts) 'c~f(l"), ': .'(1,.), :-:J(;;)
~~L~~~:-' ~~=:::~_?G:-::'~:
:!:YJ
3
~~~t c0nt~cta, 115il~~C, /_oor:~~;
t~rJ.JC ~:~27/i-l~-J
'.e
C'.ttn.chin,,; P"'.rt) ..7U.)
=lSGI3'l' ::., FI:CD, ~.'I2::~·.: mID: Surge 1initinG,
ohm, ±1~~, 5H; ofr 11502, part no. P;;5446,
3
90536, dug 7CJ047(,5-00.
C ;:'l':.CT, =L=CTT~IC.'.L: l1"'.le, criT.1I1 type 22:\'.'C,
blue color codo, 0.56 in. Ion;:; Y1fr 16512,
:!"r;rt no. 5/t 0176, <)0536, d~!::; 7903(l6o-01 (/+2).
7-34
TABLE 7-2.
DATA PIlciCESSn:G·SET IJ1/UYK-20(V) AND AN/url-20X(V), PARTS LIST (cnn.)
Reference
Designation
Notes
Processor-Ve ifier Unit CP11
11B1
11C1
11J1
triru
I1J33
11J34
11TB1
Figure
Number
Name and Description
(r)/Un:-20(V)
(Item)
(Unit 11)
PR'lCESSi-n-VERIFIER UNIT CP(p)/UYI:-20(V):
Performs the arithoetic a~d data procossing
operation as directeCi., aperatinG power 115VAC
400HZ, 3-phase delta or 20(W:.C, /~ODHZ,
3-phase wye or 115VAC, L•.oOHZ, single phase;
mfr 90536, part no. 712e031-00.
FAN mcI1l.L: ClI rotation, nlurninum case, /Jo.6SC
in. Si, 1.5 in. thick; w~r 22877, part no.
B10DS TYPE ST, 90536, dWG 7901420-01.
(Attaching Parts) R(4), Y(4), BI(4)
CAPACITC:R, FIXED, PLASTIC DIEL:CTRIC: 1.39 UF,
±10%, 400VDCH; mfr 56289, part no.
260P39494S2, 90536, dwg 7903001-33.
not used
C('NNECTCR RECEPTACLE, ELECT:lICAL: Hale 5contact; HIL type HS120E14-5P.
(Attaching Parts) AC(I.. ), B3(/-j.), DH(4)
T~rurruAL BARD:
Barrier type, 8 terminals; mfr
75382, part no. £10-8, 90536, d,,,g 4912642-07.
(Attaching Parts) G(LJ, Q(lt), LD(4), BB(J.),
3II(12)' ,
CI1CUIT CARD M;SSHBLY: Al1.ITItISTIC L -GIC IDHT;
mfr 90536, part no. 7092175-01 (11-).
CIRCUIT CARD ASSEMBLY: ARITIDETIC V'GIC C;mTR"L
IDJIT; mfr 90536, part no. 70<)02181-01 (1).
CIRCUIT CARD ASSEMBLY: ALU CrNTR'·L II; m.fr
90536, part no. 7125415-01 (1).
CIRCUIT CARD ASSEMBLY: HICR': REGISTER; mfr
90536, part no. 7092185-01 (3).
CIRCUIT CARD .\SS:bHBLY: lITeR.' C:J'~:~';-:L' mfr
90536, part no. 7092192-01 (1).
'
CIRCUIT CARD .\S~~lmLY: n:-:":'Tc:r C'T'l'R'Lj nfr
90536, part no. 7092195-01 (1).
CI:'.CUIT C.'.TID ASSEHBLY: p.2~r~:.T C' IT':'R'L; rnfr
90536, part no. 7092200-01 (1).
CIJCUIT C.·l.RD ~·l.SSElmLY: s :r.CE ,·i.!ID pEGTI:LTI IT
m-",
,-(' . . .,f .... 00536 ,j/;:"l
.... rt ..n () • '7f'1()')')n6-01 (1)
1... """'~.... .:..>,
or.crIT C:,:!lD .c'.SS;:·illL1: :·r:~:I:1.'7 C":;':'l1L; r.lfr
90536, part no. 7125665,-01 (1).
CIl1C~rIT C:illD ASSEHBLY:
S:-'~~CL'.L :rl: -nY IlJTE;u'~~C~
nfr 90536, part no. 7126155-01 (2).
.L.4.
....
/
I
,) /
..:
1·_ "'_
_
•
Reference
Designation
11 (Cont.)
Figure
Notes
NUl!lber
Nrune and Description
CI:lC~I'~'
c. . =·'.:)
. :'~~::~::~jL·~: . :""-~;l·.:~~-~~::
(Item)
~_JD~~~:S
~::~:}I~~~:-:;; ::l:Lr r;o53(), p--::-t no. 7125310-01
CIr:C:'TIT
C.T~D .',SS:::;~mLY:
CIIlC:"~I1
~.n.::!) ~;.:~:~:: :~3T;~i":
(2)
SHIFT H;'_TI:.IX IUPUT
;'C~GISTZIlS; mfr 90536, ~Qrt no. 7126130-01 (1)
S"TT-:"",: ~ .?~.I:{ C{'\!JTRr~L;
TIfr 9053(;, "[;rt y ..... J ;:-'()135-r>~ (1).
,.,.,.n,.,-T"':M r' """'l"l .
..-·T .. ,"'.
~T. r" •
J._, ,"'. . -'- c(')536
/.,
, ")~rt
..
no. 70C)203J.-01 (1).
CI~.C"HT C:.?D ~·.. S;::~~:3L~[:
EDr..·, .rilEL I!JTERF.AC~~
mfr 90536, part no.' 7126145-01 (1).
CIRCUIT CA?J) ASSElffiLY: Hr,n CL1-: C'N'T, RESm.m
DUAL ClUU1; mfr 90536, part no. 7126160-01 (1)
CI:!tCUIT GAR;) "iST.IIDLY: I l C'UT HEIr &. I::1BXIHG
L '~IC; r1:~C' t;('.53(), :~"r+. J:'!. ":'~~~)':;(1-0} (/.). /
"""'!""-- ......... _....., '; ......... -.,
,-,.-....... ~-~ ...... :
--" .... ~-~~: .•.. '~' --. :r::'i:-" r.rS3~:·,
----~·:.. t .,---. 7~ ~./<~.~~r:_("J_ (J.).
·:I~~~."I~ C: . ~l .·_:.·.:0~-~I=~:rj~.~:
~ :~':-- IJ 15; T:.fr
90536, part no. 712!)190-01 (1).
'''''_.:¥
.:_.~
.. ' ..
_._~
CI=-:~::=r~ C_<.?~)
';'1+''j'"
"'\f ... ···- ..
J;.,.J.J~J_..
.•••'"
.J ....
. ~::~~~.::~:I.:~
•
:~C~}·.J~"~~:,
~() ~J=~~;
0n!:3/
,.." ,.!.).'
...,~ ",.",,,,,_".'
\
.-) 0, ~Yl.r t nc •..
..... C1
... J.
rIT'"- ~;~;'~1 C~· .. :. . .~,; _;::(:,,:~-; ... :~:
~.
:~~._r~~:.·~ ~~:~r~.R ~.l'G
j.
r::-:'~
·r
71')t:;3r'n-01 (?)
;
CI~~CLI~ 8jl~l :_SS~::JLY:
II'rSTnUCTI: '1T P~GISTER
0-7,mfr 90536, part no. 7125240-01 (1).
CIRCUIT CARD .\.SSZlIBLY: EHULATE CONTR'L I; mfr
90536, part no. 7125236-01 (1).
CIRCUIT CARD ASSEr1BLY: EHULATE CONTROL II; mfr
90536, part no. 7125385-01 (1).
CIRCUIT CARD ASSm-ffiLY: PAGE REGISTERS; mfr
90536, part no. 7125405-01 (1).
CIRCUIT CARD ASSEr·IDLY: I/O PRli'RITY; mfr 90536,
part no. 7126175-01 (1).
CIRCUIT CAP..D ASSEHBLY: I/O I'fl.IQ:UTY C: HTr..L
.·~!TD TI! ~IlrG;
. t:~~'" r:("' ~ 3'~, . ~~ ~7.. :lC.
""-'r
.. ' ...... . .
.'."'.
..J • ..l.l ~
~f'"
• l_L _ (")r,r:31'
';," ") ,.),
"rt
t .."
'10
..
_1 .. . /
( .... J
,_
•
71~6lf'()-Ol (1).
CIlCT::7 l~ lI) ~ .. ss~~: 2L·": J::r::~ :.~D I.;~; I:lfr <)05,36,
}l''!rt no. 712()}()5-O1 (1).
CI:?CUI:' C;·~::.n ::..88::;8LY: !fTJLTII'LY C'-·UTIl L; mfr
90536, part no. 7126140-01 (1).
CIRCUIT CARD ASSEJ-IBLY: SHIFT lL\TRIX; mfr 90536,
part no. 7125500-01 (2).
CIRCUIT C.ARD ASSENDLY: TI'!O BIT r.rur.TIPLYj mfr
90536, part no. 7126125-01 (2).
CIRCUIT CARD ASSErIDLY: U MEM BANK SELECT AND
}ITSC; mfr 90536, part no. 7126205-01 (1).
CIRCUIT CARD ASSEHBLY: lID DATA DRIVE &
W'NITrR CU!CK~ mfr 90536, part no.
7126150-01 (1).
...
7-36
TABLE 7-2.
DATA PROCESSING SET AH/UlK-20(V) AND AN/UYK-20X(V), PARTS LIST (CONT.)
Figure
Reference
Numbe~
Notes
Name and Description
Designation
(Item)
11 (Cont.)
CIRCUIT CARD ASSEMBLY: INTERRUPT STORAGE; mtr
90536, part no. 7126185-01 (1).
CIRCUIT CARD ASSEMBLY: TRANSLAT0R CONTROL AND
TDfING; mtr 90536, part no. 7126195-01 (1).
Processor-Verifier Unit CP12
12B1
12C1
12Jl.
(P)jU!K-20X(V)
(Unit 12)
PROCESSOR-VERIFIER UNIT: CP(P)/UIK-20X(V~
Perrorm. the arithmeti.c and data processing
operations as directed, operating power 115
VAC,.60HZ, 3-phase delta or 208VAC, 60HZ,
.
3-phase wye or 115VAC, 60HZ, single phase;
mtr 90536, part no. 7128031-01.
FAN, AXIAL: Cw rotation, aluminum case., 4.688
in. sq, 1.5 in. thick; mtr 82877, part no.
682IS TYPEST, 90536, dwg 79()1420-O3.
(Attaching Parts) R(4), Y(4), BI(4)
CAPACITOR FIXED, PLASTIC DIELECTRIC: 1.0UF,
±10%, ,4DOVDCW; mfr 56289, part no.
260Pl0594S2, 90536, dwg 7903001-11.
not used
thru
12J33
. 12J'4
12TBl
CONNECTOR, RECEPTACLE, ELECTRICAL: Male, 5contact;" MIL type MS120E14-5P.
(Attaching Parts) AC(4), BB(4), BH(4)
TERMINAL BOARD: Barrier type, 8 termima1s; mfr
75382, part no. 410-8, 90536, dwg
4912642-07.
(Attaching Parts) G(4), Q(4), AB(4), BB(4),
BH(12)
CIRCUIT CARD ASSEMBLY: ARITIn-1ETIC L(";GIC mrrTj
mfr 90536, pnrt no. 7092175-01 (~).
CI::1CUI':' c."..rrn ,\00:101.Y:
'.::'L':I!r,~~IC L'G1C
r, ~""""1'
'1 tTPTM.
.., t no •
~
1, mf r 9053(J ,p,--r
)
L
••
) . j ....
709021t1-01 (1).
.
.·~.r.,T.~ C~"rTT~ I; II; :.1fr
90536, "'1nrt·no. 7125L.l5-o1 (1).
CI:~C:JIT G:I.PJ) J~SS~lJ3LY:
LIC::::/ ?":::GISTER; nfr
90536, part no. 7092185-01 (3).
.
CIRCUIT CARD ASSEHBLY: l-ITCnr C:~UTnc'L; mfr
90536, part no. 7092192-01 (1).
CIRCUIT CARD ASS:!!l·U3LY: n.n.:urCII C(IJ7R'L; mfr
90536, part no. 7092195-01 (1).
C1H.CUIT CAnD .~SS;];mLY: ~"'":r:= ..T C ?rrr.'R'L; mfr
90536, part no. 7092200-01 (1).
CI~~TJI':' C~-l.rm .::..33:?~mLY:
7-37
.- -:--,,- (
,..'
I · ...
Reference
D()::;iQ1lltion
12 (Cont.)
..
1
-
••
,,',
I,
r
1
T
p-"~r',
~
...• I
Fif~;.rc
notes
Name and Doscription
;::~'.~!-~I~ (j _'~J
.(~:: . -~:~'~~::
,,~, ~~~\r:-.~
"'10.
~.~] ~~'::.H~.~I~:'~r::'! .~
'::'? ~;(:; ;;.fr t") 1J 53(), ~~rt
7(Y)2?06-G1 (1).
C~~~C1!IT Cl~.. :m .~~SS~~! mL ~{: ~·C;11 RY C ::=,p. rIJ; mfr
90536, ~nrt no. 7125665-01 (1).
CIRCUIT C1"\...1i.D ASSmmLY: SPECI~\L HEl!:'RY Il1TERFACE; mfr 90536, part no. 7126155-01 (2).
CIRCUIT CARD ASSElffiLY: P-BKPT-HEH ADDRESS
REGIST~RS;
mfr 90536, part no. 7125310-01 (2)
CIRCUIT CARD .~.SSEl"ffiLY: SHIFT .HATRIX INPUT
REGISTERS; mfr 90536, part no. 7126130-01 (1)
CIRCUIT CARD ASSEHBLY: SHIFT HATRIX C"~1TRf"L;
mfr 90536, part no. 7126135-01 (1).
CL''''CK; mfr 90536, part
no. 7092031-01 (1)~.
CIRCUIT CARD ASSEHBLY:
CIRCUIT CARD ASSEMBLY:
NDR', PANEL INTERFACE;
mfr 90536, part no. 7126145-01 (1).
CIRCUIT CARD
DUAL CJLtl~;
CIRCUIT CARD
L-GIC; mfr
CIRCUIT CAnD
ASSEMBLY:
H 'N CLK C'~NT, RESID.fE,
mfr 90536, part no. 7126160-01 (1).
ASSEHBLY:
II" Ci'?'1T MEH &. INDEXING
90536, part no. 7125306-01 (4).
ASSEHBLY: THANSLAT"R; mfr 90536,
part no. 7126170-01 (1).
CIRCUIT CARD ASSElffiLY: U CNTR'L 15; mfr
90536, part no. 7126190-01 (1).
CIRCUIT CARD ASSE},IDLY: -SCILLATR, 20 HHZ; mfr
90536, part no. 7126200-01 (1).
CIRCUIT CARD ASSEMBLY: P + STATUS RGTR RTC +
PSH SEL; mfr 90536, part no. 7125380-01 (2).
CIRCUIT CARD ASSEHBLY: INSTRUCTI'N REGISTER
0-7;mfr 90536, part no. 7125240-01 (1).
CTRCUIT CARD ASSEHBLY:
EHULATE Cr;NTRCL I; mfr
90536, part no. 7125236-01 (1).
CIRCUIT CARD ASSEl.ffiLY:
EHULATE C~'NTRCL II;
mfr 90536, part no. 7125385-01 (1).
CIRCUIT CARD ASSEMBLY:
PAGE REGISTERS: mfr
90536, part no. 7125405-01 (1).
CIRCUIT CARD ASSEt.ffiLY:
I/O PRI('HITY; mfr 90536,
part no. 7126175-01 (1).
CIRCUIT CARD ASSEMI3LY: 1/ PHI'RITY C' :lITROL AND
TTI1ING; mfr 90536, part no. 7126180-01 (1).
CIRCUIT C.:'\..1i.D ASSEl'ffiLY: .nn1P AND IA; mfr 90536,
part no. 7126165-01 (1).
CIRCUIT CARD ~~.SSE!'ffiLY:
HULTIPLY C NT:i"L; mfr
90536, part no. 7126140-01 (1).
7-38
r..., --,., ,
\.;
l'\.rr:-J~f"":.:r
(Itf.!::J.)
DATA rr..c.CESSI:;G SET AN/Un:-20(V) ;~m 1~lrj'Jj.'Y-20X(V), PARTS LIST (CeNT.)
Figure
Reference
Number
Notes
Name and Description
Designation
(Item)
TABLE 7-2.
12
(Cont.)
CIRCUIT CARD ASSEt·IDLY: SHIFT HATRIX; mfr
90536, part no. 7125500-01 (2).
CIRCUIT CARD ASSEMBLY: T\·lO BIT 14ULTIPLY; mfr
90536, part no. 7126125-01 (2).
CIRCUIT CARD ASSEHBLY: U ISH D1JIK SELECT /11m
r.IIS~ mfr 90536, part no" 7126205-01 (1).
CIRCUl.T CARD ASSEMBLY: 1/[1 DATA DRIVE &
MONITOR CLOCKi mfr 90536, part no.
7126150-01 (1).
CIRCUIT CARD ASSEMBLY: INTERRUPT STORAGE; mfr
90536, part no. 7126185-01 (1).
.
CIRCUIT CARD ASSEMBLY: TRANSLATOR CONTROL AND
TDUNG; mfr 90536, part no. 7126195-01 (1).
Core l·IemoI"l! Unit Hu-601/TJYI:-20(V)
13
(Unit 13)
GfRZ lfp.HrRY lTNTT ~IU-60L./T;~:!:_?O(V):
Zlectronic
circui t p1ue-in modulo contf'ini'1p, ~~'Y
:r., onetic cero memorY, used i:-- (~(,!,G m.enorr
control C(r)/UY:~-20(7) ~'1r1 8(I')/
H~1T'
')0" ('I) ,connne t or .,_t .(;,
' . :r.L.!'.
co
Cl053(J, part
"':'h-";"1.
no. 7126382-00.
¥.
Control, Core l'Iemor'J C14
14131
14C1
14T131
14TB2
(P)/UYK-20(V)
(UnH 1/)
C:'UTRCL, C:Rl~ HEHlRY C(p)/U:C-20(V):
Proyides control for core memory unit
::iJ-()oLiu11:-20(V), o?orl:!tine po"~r 1l5VAG,
4nOlIZ, 3-phr:se del tfl 01' 20CV•• C, 400HZ, 3ph:1se "r:m or 115V.t..C, 400HZ, s'ine1e phase; mfr
90536, part ~O. 7128029-00.
FAN AXIAL: m'l rota.tion, aluminum case,4.688 in.
sq, 1.5 in. thick; mfr 82877, part no.
810DS TYPE ST, 90536, dvg 7901420-01.
(Attaching Parts) AI(4J, BI(4)
CAPACIT~R. FIXED, PLASTIC DIELECTRIC:
1.39UF,
:'~O%, L~OOVDcr;; mfr 56239, D€rt no.
2601>391+9'.S2, 905.36, dw~ 79·J30 nl-33.
T:~ru·:IlL',L Kl~RD:
Barrier type, 12 terminals;
mfr 75382, part no. 600AY12, 90536,'dwg
904862-15.
(Atta.ching Parts) AI(4), BI(4)
TERMINAL BOARD: Barrier type, 3 terminals; MIL
type 37TB-3.
. (Attaching Parts) AK(4), BI(4)
7-39
TABLE 7-2.
DATA PReCESSING SET AN/UYK-20(V) AND
Reference
Designation
14 (Cont.)
Notes
15B1
15C1
15TB1
15TB2
CIRCUIT CARD ASSEMBLY: MEMORY DATA BOARD,
plug-in type; mfr 90536, part no.
7101824-00 (2).
CIRCUIT CARD ASSEMBLY. CONTROL DATA BOARD,
plug-in type; mfr 90536, part no.
7101826-00 (2).
7-40
(P)/UYK-20X{V)
(Unit 15)
CONTROL, cnRE MEMORY C(P)/UYK-20X(V):
Provides control for core memory unit
MU-604/UYK-20(V), operating power 115VAC,
60HZ, 3-phase delta or 208VAC,60HZ, 3-phase
wye or 115VAC, 60HZ, single phase; mfr 90536,
part no. 7128029-01.
FAN AXIAL: CW rotation,aluminum case, 4.688
in. sq, 1.5 in. thick; mfr 82877, part no.
682YS TYPE ST,9D536, dw~ 7901420-03.
(Attaching Parts) AI(4), BI(4)
CAPACITOR, FIXED, PLASTIC DIELECTRIC: 1.0UF,
±10%, 400VDCW; mfr 56289, part no.
260P10594S2, 90536, dwg 7903001-11.
.
TERMINAL BeARD: Barrier type, 12 terminals;
mfr 75382, part no. 600AYl2, 90536, dwg
904862-15.
(Attaching Parts) AI(I~), BI(4)
TERl1I!lAL Dr AnD: Barrier t:;'Te, 3 terr:.inI11s; :IIL
type 37TB-3.
Ctbchin!! Pnrts) ;.r (I.), BI(;J
CInCUIT CllP.D(..SSSl-IDLY: EEl! RY D_".T'. H~A?.D;
plug-in type; mfr 90536, part no.
7101824-00 (2).
CIRCUIT C.ARD ASSEMBLY: CCNTRC'L DATA B"'ARD,
plug-in type; mfr 90536, part no.
7101826-00 (2).
Interface Yit, Fast $el"ia1
16
PARTS LIST (CONT.)
Figure
Name and Description
Control, Core Memory C15
AN/UYK-20X(V~
MI~-
juYK-20(V)
(Unit 16)
HTTERFACE 1(IT, FAST SERIAL }n~juYE-20(V):
Contains 2 circuit p1uf,-in cards required for
1 group of 2 input and 2 output channels, used
in processor-verifier unit CP(P)/UYK-20
(V) and CP(P)/UYK-20X(V); mfr 90536, part
no. 7101802-00.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; mfr
90536, part no. 7119425-01 (1).
Number
(Item)
TABLE 7-2.
DATA PROCESSING SET AN/UYK-20(V) AND AN/UYK-20X(V), PARTS LIST (GONT.)
Reference
Designation
16 (Cont.)
Fif..rure
Notes
Name and Description
MK-
/UYK-20(V)
(Unit 17)
INTERFACE KIT, SERIAL SYNC MK/UYK-20(V):
Contains 2 circuit plug-in cards required for
1 group of 2 input and 2 0Utput channels, used
in processor-verifier unit Cp(P)/UYK-20
(V) and CP(P)/UYK-20X(V); mfr 90536, part
no. 7101803-00.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; mfr
90536, part no. 7119435-01 (1).
CIRCUIT CARD ASSEMBLY: 2 CHANNEL RECEIVER; mfr
90536, part no. 7119440-01 (1).
Interface Kit, Seriai Async
18
(Ito:1)
CIRCUIT CARD ASSEMBLY: 2 CHANNEL RECEIVER; mfr
90536, part no. 7119430-01 (1)
Interface Kit, Serial Sync
17
Number
MK-
(V)jU!K-20(V)
,
(Unit 18)
INTERFACE KIT, SERIAL ASYNC MK(V)/UYK-20(V}
Contains 1 receiver and,16 optional driver
circuit plug-in cards required for 1 group of
2 input and 2 output channels, used in
processor-verifier unit CP(P)/UYK-20(V)
and CP-. (P)/U1K-20X(V); mfr 90536, part
no. 7128069-00.
CIRCUIT CARD ASSEMBLY: :2 CHANNEL RECEIVER; mfr
90536, part no. 7133225-01 (1).
.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; mfr
90536, part no. 7123230-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; m.fr
90536, part no. 7133235-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; mfr
90536, part no. 7133240-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; mfr
90536, part no. 7133245-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; mfr
90536, part no. 7133250-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; mfr
90536, part no. 7133255-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; mfr
90536, part no. 7133260-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL DRIVER; mfr
9053~, part no. 7133265;..01.
"
7-41
TABLE 7-2.
1
DATA PROCESSING SET AN/UYK-20(V) AND AN/UYK-20X(V), PARTS LIST (C"'NT.)
neference
Dcsicnntion
18 (Cont.)
F~[':fl~O
Notes
CIRCUIT CARD ASSEHBLY: 2 CHANNEL
90536, part no. 7133270-01.
CIRCUIT CARD ASSEMBLY: 2 Clli~L
90536, part no. 7133275-01.
CIRCUIT CARD ASSEHBLY: 2 ClliiNNEL
90536, part no. 7133280-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL
90536, part no. 7133285-01.
CIRCUIT CARD ASSEHBLY: 2 CHANNEL
90536, part no. 7133290-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL
90536, part no. 7133295-01.
CIRCUIT CARD ASSEHBLY: 2 CHANNEL
90536, part no. 7133300-01.
CIRCUIT CARD ASSEMBLY: 2 CHANNEL
90536, part no. 7133305-01.
Interface Kit, Serial Communications, Sync Mt:19
7-42
}~-
1
..... v· .....
(''''0''')
DRIVER; mfr
I
DRIVER; mfr
mfr
DR~VER;
DRIVER; mfr
I
I
DRIVER; mfr
DRIVER; mfr'
DRIVER; mfr
DRIVER; mfr
/UYK-20(V)
(Unit 19)
INTERFACE KIT, SERIAL cr,:·tMUNICATIr'NS, SYNC
111R ITEM DESCRIPTIONS
Item baber
,1.3
14
(Cu.N'l' .. )
Description
RECTIFIER, SEMICGNDUCTOR DEVICEI
Unitized, 3-phas8, r~il..l \;i'll'Wlt' .3 AMP ,
400V piv per leg:; ltl.fr 1;(~69, part no.
691-4, 90536, dvg 7901.,i..96·IJJ.
RESISTOR, FIXED;b COMPOSITION: lOOK ohm,
1/2'.:.'~ MIL type RCR20G104JM.
±5%,
15
RESISTOR, FIXED, FIU{~, ;~nf~'JG ohln J ±2%,
2W; MIL type M22684-04-.{J159.
16
RESISTOR, FUED, WIRE"w01JND: 0.1 ohm,
±l%, 20\01; MIL t~"Pe RE'70C:~EIOO~
17
RESISTOR, FIXED t~'TPEW'Cr\'J.
r~~:::"'r'':~J:
ruDbcr,
,,"',.., r:
•·.·f
.w.', . f - ••.•
r. "'39
liCfi
rin.~,
i.n ID,
~~,,'.:J~:':::, :1~~!:;:
7L.~:', GRES, No. 0, O.06J
in ID, 0.099 in OD, n.016 in thic!m'3so;
:;....J()~OCO •
7-52
nT 'l1" 7-'
T•:...u..u:..;..
4e
LIS""1 "F
.'
Letter Code
(("NT
oJ\'"
• )
Name and Description
,
BlI
l......
i"Tm·CT_TI~TG·
uC,"CT\'J
......
J..i.
.ru ..... :.J..)., ........""'7
l...C.I
::,ASHER, pL.:i.nh FLAT, crc~s , i~o. I~, 0.115
j.n ID, 0.209 in OD, 0.03? in thic1~nGso;
lJAS620C4.
BI
BJ
..
Brr
WASHER, FLAIBa nat, ORES, Ho. 8, 0.169
in ID, 0.304 in OD, 0.032 in thickness;
UAS620Ce.
111.3HER, PL..",IN: FLAT, CRES, 1/4 size, 0.255
in ID, 0.468 in OD, 0.063 in thickness;
NAS620C416.
BL
WASHER, SHOULDEnED:
FIBR-r.:, INSULATTIIG,
flanged, No.6, 0.13C in ID, 0.187 in ID shldr
dia, 0.312 in OD; I:lfr ?3330, part nr..
2153.
Blf
~l.ASHSn.,
SIL.:ULDERED:
FIi:mr:,
n~SULATIlm,
flanged, lb. 10, 0.190 in ID, 0.308 in ID
shldr dia, 0.380 in OD; rnfr 83330, part no.
2156.
BN
PL/:.STIC, 5/16 size,
teflon, 0.325 in ID, 0.415 in ID shldr dia,
0.500 in UD; mfr 86684, part no. 495334-6.
1.J.ASHER, SHOULDEBED:
7-!13
TABLE 7-5.
Vendor
Code
LIST OF MANUFACTURERS
Name
Address
00736
Filter Products, Div of Uorth
Amnrican Rockwell Corp, Air-Haze
';lant·
25000 ;"1iles Rood
Cleveland, OR 44128
03577
Transistron Electronic Corp
168-186 Albion Street
r,;avefie Id, I·m, 01 ~80
Hotorola Inc
Semiconductor Products Division
5005 East NcDo\,roll Road
Phoenix, AZ 85008
07137
TEC Inc
6700 l.Jashineton Ave South
Eden Prairie, r1JlT 55343
08289
Bli~n
11502
TRVJ E.lectronic Components,
Delbert Co., Inc., The
IRC ?ixed Resistors, Boone Div
167e East >!ission Blvd
P. O. Box 20m
Pomona, CA 91766
Greenv;ay Hoad
Boone, NC 286m
12969
. Uni trade Corp
580 Pleasant Street
tY'a terto\m, >1A. . 02172
13103
Thcrmalloy Co
F. O. Box 34829
2021 Hest Valley View Lane
Dallas, TX 75234
13137
j'·fica Fabricating Co
55 Central Ave
Rochelle Park, l!J
07662
Corning Glass ~.Toi-ks
Houghton Park
Corning, NY 11..830
16512
Fabri-Tek Inc,
National Conpector Division
9210 Science Center Drive
New Hope, >IN 55428
16513
Nag-Con Inc
85 2nd Ave Soutpeast
New Brighton, NN 55112
18234
Lindgren Erik A. and Associates,
Inc
4515 North P.avenswood
21845
Solitron Devices, Inc
Transistor Division
1177 Blue Heron Blvd
Riviera Beach, FL 33404
31356
J-B-T Instruments, Inc
42l~
.
Chicago, IL
60640
C,baoel Street
P. O. Box 1818
New Haven, CT
7-54
06508
TABLE 7-5. . LIST OF MANUFACTURERS (COlIT.)
Vendor
. Code
Address
37942
Mallory, P. R. and 00., Inc
3029 East v.Tashington Street
Indianapolis, IN· 46206
56289
Sprague Electric Co
North Adams, MA
71279
Cambridge Thermionic Corp
445 Cone ord Ave
Cambridge, MA 02138
71785
TRW Electronic Components,
Cinch Division
1501 Morse Ave
Elk Grove Village, II. 600(J7
72962
Elastic Stop. NUt, Division of
AmeraceESNA Corp
2330 Vauxhall Road
Union, NJ (J7003
75382
Kulka
81312
Winchester Electronics,Division
of Litton Industries Inc
M"iin Street and. Hillside Ave
Oakville, CT 06779
82227
North American Philips Controls
.Corp
P. O. Box 768
Fip Baod
Cheshire, CT 06410
82877.
Rotron, Inc
7-9 Hasbrouck Lane
Woodstock, NY ,12498
833.30
Smith, Herman H., Inc
86684
RCA Corp. , Elect:t'onic Components
90536
Sperry Univac, Defense Systems
Electric .Corp
01247
633-643 South Fulton Ave
~'!ountVernon, NY
10550
·812 Snediker Ave
Brooklyn, NY 11207
415 South 5th Street
Harrison, NJ 07029
Univac Park
P. O. Box 3525
St. Paul, MN 55165
7-55/{7-56 blank)
,. i..
CHAPTER 8
INSTALLATION
8-1.
INTRODUCTION.
8-2. This chapter describes the installation of the Data Processing Set (DPS) for
either rack mounting or table top operation. Included are dimensional drawings,
cabling information, and test procedures to facilitate the installing of the DPS.
8-3.
INSTALLATION INSTRUCTIONS.
8-4.
TOOLS AND MATERIALS.
8-5.
UNPACKING AND REPACKING.
No special tools are required for installation.
Perform the following steps for unpacking.
1.
Remove thinwall nails at the bottom of the crate that go into the skid.
2.
Remove steel bands.
3.
Lift up crate from unit.
4.
Remove upper cushioning insert if it remained on top of unit.
5.
Lift unit up from lower cushioning insert and skid.
6.
Inspect outside of unit for physical damage.
All damage should be reported.
7. If possible, retain the shipping crate and cushioning inserts for reshipment
at a later date.
8-6.
For repacking, perform the following steps.
1.
Repacking in original shipping crate if kept.
a.
Place cushion insert on skid.
b.
Place unit on cushion insert.
c.
Place cushion insert on top of unit.
d.
Place crate over top of unit and down resting on cushion.
e.
Nail sides of crate to skid using four thinwall nails per side.
f.
Place metal strap around crate.
g.
Place label on crate.
A-I
2.
Repacking in made up crate.
a. Place unit in a corrugated cardboard inner container, with corrugated
cardboard spacers or one-inch polyurethane foam at front and rear to protect
switches, indicators, and connectors.
b. Place inner container into a cleated panel outer container with space
between filled with at least four inches of two-pound density polyurethane foam
or equivalent.
8-7. PREPARATION OF FOUNDATION. The rack should be prepared to provide sufficient space to receive the DPS, and be drilled to receive the eight mounting
bolts and two shock pins. Refer to figure 8-1 for the space requirements and
position and size of the mounting holes. The rack must be able to support the
200 pound weight of the DPS. For table top installation, make sure the proper
space is available and the table is capable of supporting the DPS's 200 pounds.
8-8. INPUT REQUIREMENTS. Refer to paragraph 1-35 and table 1-1 for input power
requirements for the various options.
8-9.
INSTALLATION PROCEDURES.
1.
Rack Mounting
a. Use an allen wrench to loosen the eight screws that hold the maintenance
panel door closed.
b.
Open the maintenance panel door.
c. Remove and mark the three ribbon cable connectors from JOI, J02, and J03
(upper left on maintenance panel).
d.
door.
Remove the power cable from the cable clamps on the maintenance panel
e. Use a slotted screwdriver to unscrew the power cable connector clamp
connected to J04 (upper left on the maintenance panel.
f. Use a phillips screwdriver and remove the left holding bracket of the
telescoping door stop
g. Use phillips screwdriver and remove the four screws that hold the two
maintenance panel door hinges in place. Remove door.
h.
Lift the DPS into place in the rack.
i.
Using eight bolts, bolt the DPS in place.
j. Remount the maintenance panel door using the four phillip head screws to
hold the two hinges in place.
8-2
k.
Remount the left holding bracket of the telescoping door stop.
1.
Connect the power cable to J04.
IiArcH
""~L./)
).
\
C.
c:.
c.
......- - - - ' 9 . 0 0
(4.Z5
It
.45 5/.0T
(I) /.00 0111
:l
::l
~
CllJIWGE PLATE.
J 18.6IJ ItE'-
I
REfI--";:~
FRONT VIEW
....- - I •. OO~--....
....
.
.
•
....
Figure 8-la. DPS Outline Drawing
B-3
•
L
....... "t .
. ·~~t
".: ..';~;ii'~' ..
...........--+--23.'3 M..lC'----~
·
~~~~--~~
.-
•
AIR eX,.,AtLSr, . . ,
NlEMOIi'Y
rI=---,.
A .....
'1
•
•
I
•
• +
It. 91 ItE"
I
••
•
14l1f E'I. HAUST1
S.U.PPLY
POVtIIi'~
SIbS
VII:W
INPUT POWER
CONNeCTOR
•
•
•
•
+
PINS
+
8.00
GI<'Ou.ND
•
.....- - - 1 5 . 0 0 - - - - - . . I
...
REAR VIEW
Figure a-lb.
8-4
DPS Outline Drawing
STU.D
_ _ ~L.t~u", _
C'LEI'IR"'",CIio S::o~·
r:-(
0
c. At.~.S
t----,-/7. SO
..
2.0.0 MIN-----+e--"'I
eXHA"Sr C'EARANC£
+
Figure 8-le.
+
IS.SO
R
DPS Outline Drawing (To Serial 4)
8-~
....- - - 1 1••0
.
MAW---'"
.
+
•
& .•0
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Figure 8-ld.
8-6
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C,~~A~CE
DPS Outline Drawing (From Serial 4
m.
PlAce the cable back in the cable clamps.
n.
Replace the three ribbon cable connectors to JUI, J02, and J03.
o.
Unlatch the telescoping door stop and close the maintenance panel door.
p.
Fasten the eIght bolts to secure the door.
2.
Table Mounting
a.
Place DPS on table as close to final position as possible.
b. Use an allen wrench and unscrew the eight screws holding the maintenance
panel door closed.
c.
Open the maintenance panel door.
d.
Loosen the four screws holding the memory chassis closed.
e.
Slide out the memory chassis.
f.
Remove the CP/IOC chassis as indicated in Chapter 6.
g.
Remove the power supply chassis as indicated in Chapter 6.
h.
Remove the power supply blower as indicated in Chapter 6.
i.
Move DPS to align mounting holes.
j.
table.
Use the front two and back two mounting holes and mount the DPS to the
k.
Replace the power supply blower as indicated in Chapter 6.
1.
Replace the power supply chassis as indicated in Chapter 6.
m.
Replace the CP/IOC chassis as indicated in Chapter 6.
n.
Swing in memory chassis and push in slide.
o.
Lock memory chassis in place with the four screws.
p.
Close the maintenance panel door and secure with the eight screws.
8-10.
INSTALLATION CHECKOUT.
8-11.
INSPECTION.
1. Before connecting the power cable, use a meter to verify that the proper
voltages are available. Table 8-1 shows the voltage en each pin.
2. Connect the input/output cables per system definition to the various jacks
as indicated in figure 8-2. Tables 8-2 through 8-5 show I/O cable pin assignmen t s.
8-7
1:,,"
I
".-- .....
j
.4
.
.
'.
1
i
)
--'
~ol
:. tJ
,,--.
i
4
i
'1
o
j
I
L)
:ro-z-
~
4.
.
:fo3
% /oj
:~
r-"
I
IS
L)
:rIO
1:1..1'1"
:!13
---[~
::1. rl
:! I r
01A"
.- . .
~
:!. to....
/"--
t.'
en-
r-'
l:J
C"\J-
, r - -..
-.
.... 1<
r z..1
IN
IN
GJ
o
.r 31>
Figure 8-2.
8-8
'l'34
Input/Output Channel Assignments
.
~~
I'll
':1"14
12J
;
TABLE 8-1.
PIN n:
POWER CONNECTOR PIN ASSIGNMENTS
10
30y
306
A
115 Vac
115 Vac Line to Neut.
115 Vac Line to Line
B
Neutral
115 Vac Line to Neut.
115 Vac Line to Line
C
Not Used
115 Vac Line to Neut.
115 Vac Line to Line
D
Not Used
Neutral
Not Used
E
Safety Ground
Safety Ground
Safety Ground
F
Not Used
Not Used
Not Used
G
Not Used
Not Used
Not Used
TABLE 8-2.
PARALLEL CHANNEL I/O CONNECTOR PIN ASSIGNMENTS (EVEN GROUP':')
FUNCTION
INPUT
OUTPUT
Input Data Request
Input Acknowledge
External Interrupt Request
External Interrupt Enable
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Output Acknowledge
Output Data Request
External Function Acknowledge
External Function Request
Bit 00
Bit 01
Bit 02
Bit 03
Bit 04
Bit 05
Bit 06
Bit 07
Bit 08
Data
Data
Data
Data
Bit
Bit
Bit
Bit
Bit
Bit
Bit
09
10
11
12
13
14
15
CONNECTOR PIN
SIGNAL
RETURN
B-5
B-6
B-7
B-8
D-l
D-2
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-lO
D-ll
D-12
G-1
G-2
G-3
G-4
A-5
A-6
A-7
A-8
C-l
C-2
C-3
C-4
C-5
C-6
C-7
C-8
C-9
C-lO
C-ll
C-12
H-1
H-2
H-3
II- 1
-Even Groups - Group 0, Channels 0-3; Group 2, Channels 10-13 (Octal)
8-9
TABLE
B~2.
PARALLEL CHANNEL I/O CONNECTOR PIN ASSIGNMENTS (EVEN GROUP*) (CONT)
CONNECTOR PIN
SIGNAL
RETURN
FUNCTION
I
INPUT
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
OUTPUT
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
16
G-5
G-6
G-7
G-B
G-9
G-lO
G-ll
G-12
J-1
J-2
J-3
J-4
J-5
J-6
J-7
J-B
17
IB
19
20
21
22
23
24
25
26
27
2B
29
30
31
H-5
H-6
H-7
H-B
H-9
H-lO
H-ll
H-12
K-1
K-2
K-3
K-4
K-5
K-6
K-7
K-B
*Even Groups - Group 0, Channels 0-3; Group 2, Channels 10-13 (Octal)
TABLE B-3.
PARALLEL CHANNEL I/O CONNECTOR PIN ASSIGNMENTS (ODD GROUP*)
FUNCTION
INPUT
OUTPUT
Input Data Request
Input Acknowledge
External Interrupt Request
External Interrupt Enable
Data
Data
Data
Data
Data
Data
Output Acknowledge
Output Data Request
External Function Acknowledge
External Function Request
Bit 00
Bit 01
Bit 02
Bit 03
Bit 04
Bit 05
CONNECTOR PIN
RETURN
SIGNAL
B-5
B-6
B-7
B-B
D-l
D-2
D-3
D-4
D-5
D-6
*Odd Groups - Group Iv Channels 4-7; Group 3, Channels 14-17 (Octal)
B-I0
A-5
A-6
A-7
A-B
C-1
C-2
C-3
C-4
C-5
C-n
TABLE 8-3.
PARALLEL CHANNEL I/O CONNECTOR PIN ASSIGNMENTS (ODD GROUP*) (CONT)
FUNCTION
INPUT
OUTPUT
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Data Bit 06
Data Bit 07
Data Bit 08
Data Bit 09
Data Bit 10
Data Bit 11
Data Bit 12
Data Bit 13
Data Bit 14
Data Bit 15
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Channel Data
Bit 00
Bit 01
Bit 02
Bit 03
Bit 04
Bit 05
Bit 06
Bit 07
Bit 08
Bit 09
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
CONNECTOR PIN
SIGNAL
RETURN
D-7
D-8
D-9
D-lO
D-11
D-12
G-l
G-2
G-3
G-4
F-l
F-2
F-3
F-4
F-5
F-6
F-7
F-8
F-9
F-lO
F-11
F-12
B-9
C-7
C-8
C-9
C-lO
C-11
C-12
H-l
H-2
H-3
H-4
E-l
E-2
E-3
E-4
E-5
E-6
E-7
E-8
E-9
E-lO
E-11
E-12
A-9
B-lO
B-11
B-12
A-1O
A-11
A-12
*Odd. Groups - Group 1, Channels 4-7; Group 3, Channels 14-17 (Octal)
8-11
TABLE 8-4.
SERIAL CHANNEL I/O CONNECTOR PIN ASSIGNMENTS
FUI\CTION
MIL-STD-188
A
B.
C
D
E
F
G
RS-232
CONNECTOR PIN
ODD GROUP>:'~"
EVEN GROUP*
Loop Test
Ring Indicator
Received Line Signal Detector
Data Terminal Ready
Clear To Send
New Sync.
Request To Send
H
I
J
K
Data Set Ready
L
Transmit Clock Transmitter Signal Element Timing
Transmit Data
Transmitted Data
Receive Clock
Receiver Signal Element Timing
Receive Data
Receive Data
Signal Ground
Signal Ground
*Even Group - Channels 0,1; 4,5; 10,11; and 14,15 (Octal)
**Odd Group - Channels 2,3; 6,7; 12,13; and 16,17 (Octal)
8-12
D-8
D-4
C-4
C-8
D-5
D-7
C-7
D-6
D-3
C-6
C-3
D-2
G-4
D-12
C-12
H-4
G-l
G-3
H-3
G-2
D-ll
H-2
C-ll
D-lO
B-5
A-5
A-7
B-7
A-6, A-8
TABLE 8-5.
DUAL CHANNEL I/O JUMPER PLUG PIN ASSIGNMENTS
ORIGIN
FUNCTION
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
00
01
02
03
04
05
06
07
08
09
Bit
Bit
Bit
Bit
Bi t
Bit
10
11
12
13
14
15
TABLE 8-6.
SIGNAL
RETURN
0-1
D-2
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-lO
D-ll
D-12
G-1
G-2
G-3
G-4
C-l
C-2
C-3
C-4
C-5
C-6
C-7
C-8
C-9
C-lO
C-ll
C-12
H-1
H-2
H-3
H-4
L~
E-l
E-2
E-3
E-4
E-5
E-6
E-7
E-8
E-9
E-lO
E-ll
E-12
A-9
A-lO
A-ll
A-12
F-l
F-2
F-3
F-4
F-5
F-6
F-7
F-8
F-9
F-lO
F-11
F-12.
B-9
B-lO
B-ll
B-12
EXTERNAL REAL TIME CLOCK CONNECTOR PIN ASSIGNMENTS
FUNCTION
H~
DESTINATION
RETURN
SIGNAL
Spare
Spare
External Real Time Clock
External Real Time Clock
Spare
Spare
. 3. Connect the ground strap to the ground stud.
shown in figure 8-1.
CONNECTOR PIN
A
B
C
D
E
F
The location of the stud is
4. Connect the external real time clock cable to jack 34, if required. The
position of this jack is shown in figure 8-2. Table 8-6 shows connector pin assignments.
8-13
8-12.
INITIAL TEST.
1. Set the switches on the control panel and maintenance panel to the positions
indicated in table 2-4.
2. Set the CIRCUIT BREAKER switch on the operator's control panel to the ON
position.
3. Set the POWER BLOWER switch to the ON position. Make sure that the blower
is discharging air from the exhaust grills on the side of the cabinet. The power
blower indicator should be lit.
4. Set the POWER LOGIC switch to the ON position. The indicator should be lit.
The FAULT POWER and OVER TEMP indicators should not be lit. If either one or both
are lit refer to section five (troubleshooting).
5. Use a meter and check the logic voltages. Refer to table 8-7 for description
of the logic voltages. The voltages on TB4 should be made in reference with
processor signal ground (EIO). All voltages have 5% tolerences. TB3 and 4 are
located at the bottom middle on the front of the power supply.
8-13. INSTALLATION VERIFICATION TEST. Run the diagnostic tests listed in chapter
10 to verify the operation of the DPS. These tests procedd logically through the
equipment using operational circuits to test the untried areas and provide corrective instructions if the results are not as specified.
8-14. INSTALLATION SUMMARY SHEET. Use the installation summary sheet shown in
figure 8-3 to record the verification of each test.
8-14
TABLE 8-7.
LUG NO.
LOGIC VOLTAGES
DESCRIPTION
T83
1
2
3
4
5
6
7
-5.2 volts
-5.2 volts return
+12 volts
+12 vol ts return
-16 volts
-16 volts return
Spare
TB4
1
2
3
4
5
6
7
Spare
+15 volts
+15 volts sense
-5 volts
Memory Signal Ground
+5 volts memory
Spare
E9
+5 volts processor
ElO
Processor Signal Ground
8-15
INSTALLATION SUMMARY SHEET
OPERATION
Power cable voltage
I/O cables connected to proper jacks
DMA cable connected to jack 33
External real time clock connected to jack 34
Blower operating correctly
Power came up properly
Logic voltages correct
Diagnostic Test
Figure 8-3.
8-16
Installation Summary Sheet
VERIFICATION
CHECK
OK
NOT OK
APPENDIX A
MICROINSTRUCTION- REPERTOIRE
Instructions defined in this appendix are
used is a 16-bit instruction divided into
specifies the function code. The D-field
register. The S-field {Table A-I lis the
used as a microinstruction modifier.
the DPS microinstructions. The format
four equal 4-bit fields. The F-field
(Table A-2) defines the destination
source field for data. The M-field is
Symbols used in microinstructions
Symbol
Description
Scratch pad registers
D
Destination field
F
Function code
K
Constant
M
Microinstruction modifier field
P
Program address register
Ra.
The register designated by a
Hm.
The register designated by m
S
Source field
tL P
Micro P register
tLP Hold
Micro P hold register
( )
The contents of the location specified within the
parenthesis
Transfer to
A-I
Table A-I.
' i
S
VALUE
A-2
S-Designator
.
SOURCE 1 (Sl)
SOURCE 2 (S2)
o
Unassigned
~P
1
Breakpoint
Condition Register
2
P Register
Display Register
3
Memory Data Register
Normalize/Panel Select
4
Page Registers
RTC Upper
5
Indirect Address Pointer
STATUS 1 Register
6
Shift Matrix Output
STATUS 2 Register
7
Monitor Clock/Feed/Partial
Product (Determined by
F = 15, FII = 16)
RTC Lower
10
AO
General Register
11
Al
Cordic Table
12
A2
Instruction Register AM Sign
Extended
13
A3
Instruction Register
14
A4
Class I & II Interrupt Code
15
AS
Class III Interrupt COde/I/O
Translator
16
A6
Input Data
1'7
A7
I/O Control Memory
Hold Register
Table A-2.
D-Designator
o
DESTINATION 2 (02)
DESTINATION 1 (01)
VALUE
o
Unassigned
~P
1
Breakpoint
Condition Register
2
P Register
Display Register
3
Memory Data Register
Cycle Counter
4
General Register
RTC Upper
5
Status Register ul
Unassigned
6
Status Register U2
Unassigned
7
RTC Lower
Unassigned
10
AD/Shift Register Rl/Page
Address Counter
Page Registers
11
AI/Shift Register R2
Unassigned
12
A2
Instruction Register/SGR
13
A3
SGR
14
A4
CM Translator
15
A5
I/O Translator
16
A6/Shift Counter
Output Data
17
A7/Memory Address Register
I/O Control Memory (CM)
Register
A-3
F = 00 TRANSFER
0000
o
5
M
Transfer the contents of the source register as specified by 5 (Table A-I) and
modified by M to the destination register as specified by 0 (Table A-2) and
modified by M. M designator usage as shown below in Table A-3.
Table A-3.
M-Oesignator for Microinstruction F=OO
M
FUNCTION
3 2 1 0
o XX X
Do not update the Condition register
1 X X X
Update the Condition register
X0 XX
Transfer direct
X1 XX
Transfer data rotated left circularly 8 bit positions
X X 0 0
Transfer (51) to 01
XX0 1
Transfer (52) to 01
XX1 0
Transfer (51) to 02
XX1 1
Transfer (52) to 02
I
A-4
F = 01 JUMP
x
0001
Transfer (~P) to
address X.
~P
HOLD, Load
~P
with X, then execute the microinstruction at
F = 02 ADD
0010
01
52
Add the contents of the source register as specified by 52 (Table A-I) to the
value specified by M (Table A-4) and transfer the sum to 01 (Table A-2).
Table A-4.
M-Designator for Microinstruction F=02
M
321 0
FUNCTION
o X XX
Do not update the Condition register
1 XXX
Update the Condition register
X0 0 0
(52) + (An »:'
~
X 0 0 1
(52) + (A n )*
~
01, Carry hold
x0
(52) + (An »;,
~
01, Carry end around
1 0
01, Force carry
X0 1 1
(52) +
X 1 0 0
(52) + P05 ZERO
~
01, Force carry
X1 0 1
(52) + NEG ONE
~
01, Carry hold
XII 0
(52) + P05 ZERO
~
01, Carry end around
XII 1
(52) + NEG ONE
~
01, No carry
(Ait»:<~
01, No carry
-:'The least significant 2 bits of 01 srrecify one of the registers AO-A3 as
operand source.
A-5
F
= 03
SHIFT
0011
Dl
Sl
M
Shift Sl (Table A-I) one bit position as specified by M (Table A-5) and transfer
the result to 01 (Table A-2).
Table A-5.
M-Designator for Microinstruction F=03
M
3 2 1 0
A-6
FUNCTION
oXXX
Do not update the Condition register
1 XXX
Update the Condition register
X0 XX
Shift left 1 bit position
X1 XX
Shift right 1 bit position
XX0 0
Zero fill (right or left shift)
X X 0 1
Sign fill (right shift) or circular (left shift)
XX1 0
Insert the bit shifted off in previous shift operation
X XII
Insert special (reserved for serial I/O data operations)
F = 04 ADD
0100
01
51
M
Add the contents of the source register 51 (Table A-I) to the value specified
by M (Table A-6) and transfer the sum to 01 (Table A-2).
Table A-6.
M-Oesignator for Microinstruction F=04
M
3 2 1 0
FUNCTION
0 XXX
Do not update the Condition register
1 XXX
Update the Condition register
X 000
(51) + (A n)*
~
01, Force carry
X 001
(51) + (A n)*
~
01, Carry hold
X 010
(51) + (A n)*
~
01, Carry end around
X 011
(51) + (A n )*
~
01, No carry
X 100
(51) + P05 ZERO
X 101
(51) + NEG ONE
X1 1 0
(51) + P05 ZERO
X III
(51) + NEG ONE
~
~
~
~
01, Force carry
01, Carry hold
01, Carry end around
01, No carry
*The least significant 2 bits of 01 specify one of the registers AO-A3 as the
operand source.
A-7
F = 05 SUBTRACT
0101
01
Sl
M
Subtract the contents of the source register Sl (Table A-I) from the value
specified by M (Table A-7) and transfer the difference to 01 (Table A-2).
Table A-7.
M-Oesignator for Microinstruction F=05
M
3 2 1 0
FUNCTION
o XXX
00 not update the Condition register
1 XXX
Update the Condition register
X0 0 0
(A n)* - (S1) -+ 01, Force carry
X 0 0 1
(A n )'!<
X 0 1 0
(A n )* - (S1)-+
X0 1 1
(An) . . - (S1) -+ 01, No carry
X 1 0 0
POS ZERO - (S1) -+ 01, Force carry
X 1 0 1
POS ZERO - (Sl) -+ 01, Carry hold
XII 0
POS ZERO - (Sl) -+ 01, Carry end around
XII 1
POS ZERO - (Sl) -+ 01, No carry
-
(S1) -+ 01, Ca rry hold
01, Carry end around
*The least significant 2 bits of 01 specify one of the registers AO-A3 as
the operand source.
A-8
F = 06 LOGIC I
~
__0_1_1_0__
~
___D_l__
~
___5_l__
~
___M
____
~1
Perform the logic function specified by M (Table A-8) and transfer the result
to Dl (Table A-2).
Table A-8.
M-Designator for Microinstruction F=06
M
FUNCTION
3 2 1 0
o X.x X
Do not update the condition register
1 XXX
Update the condition register
X0 0 0
Logical Exclusive OR of (An)* and (51)
(An)*
(£)
(51)
X 0 0 1
Logical complement of the logical AND
of (An)* and (51)
(An)*
•
(51)
X 0 1 0
Logical AND of (A n)* and the log.ical
complement of (51)
(AX)* ..
(51)
x0
Logical complement of (51)
(A n )* +
(51)
1 1
X 1 0 0
Logical OR of (A n )* and (51)
X1 0 1
All ones
1
X1 1 0
X1 1 1
(An )*
Logical OR of (A n )* and the logical
complement of (51)
(A n )*
+
(51)
*The least significant 2 bits of Dl specify one of the registers AO-A3 as
the operand source.
A-9
F = 07 LOGIC II
0111
01
51
M
Perform the Logic function specified by M (Table A-9) and transfer the result
to 01 (Table A-2).
Table A-9.
M-Designator for Microinstruction F=07
M
3 2 1 0
FUNCTION
0 XXX
Do not update the Condition register
1 XXX
Update the Condition register
X 000
Logical AND of the logical complement
of (A n )* and (51)
(A n )*
X 001
Logical complement of (A n )*
(An)>:'
Xo I 0
All zeros
Xo I I
Logical complement of the logical OR
of (A n )* and (51)
(An)"" +
X 100
(51)
(51)
XI 0 1
Logical OR of the logical complement
of (A n )* and (51)
(A n )* +
(51)
X1 1 0
Logical AND of
(A n )*
.
(51)
X1 1 1
Logical,complement of the logical
Exclusive OR of (A n )* and (51)
(A n )* +
(51)
(51)
0
(An)~l<
and (51)
*The least significant 2 bits of 01 specify one of the registers AO-A3 as
the operand source.
A-10
.
(51)
F = 10 ADD CONSTANT
Dl
1000
K
Add the 8 bit constant K (zeros extended to 16 bits) to the accumulator (A n )*
and transfer the sum to Dl (Table A-2).
*The least significant 2 bits of D1 specify one of the registers AO-A3 as
the operand source.
F
= 11
SUBTRACT CONSTANT
1001
Dl
K
Subtract the 8 bit constant K (zeros extended to 16 bits) from the accumulator
(A n )* and transfer the difference to Dl (Table A-2).
*The least significant 2 bits of Dl specify one of the registers AO-A3 as the
operand source.
F = 12 TRANSFER CONSTANT
1010
Dl
K
Transfer the 8 bit constant K (zeros extended to 16 bits) to D1 (Table A-2).
F
= 13
1011
TRANSFER CONSTANT
I
D2
K
Transfer the 8 bit constant K (zeros extended to 16 bits) to D2 (Table A-2).
A-ll
F == 14
BRANCH
FII
1100
K
If the branch condition specified by FII (Table A-10) is satisfied, transfer (~P)
to ~P HOLD and load bits 0-7 of ~P with K leaving bits 8-11 of ~P unchanged. Then
execute the microinstruction at the address in ~P. If the branch condition specified by FII is not satisfied, the MPC will perform the next instruction as
programmed.
Table A-10.
FII Designator for Microinstruction F=14
FII
11 10 9 8
BRANCH CONDITION
o 0 0 0
Last arithmetic operation result had negative sign (COND
register bit 14 set).
000
1
Last operation had a result of zero (COND register bit 13 set).
001
0
Greater than (COND register [2 11
001
1
Overflow, add or subtract (COND register [2 11 • 214] + 212 == 1)
(!)
212] ~ 210 == 1).
o 1 0 0
Carry (COND register bit 10 set)
o 1 0 1
Inside limits (COND register 29 . [(2 11
o 1 1 0
Double precision zero (COND register 28 + 213 == 1)
o
Shift save == 0 (COND register bit 15 set)
1 1 1
(!)
212) ~ 210 ] == 1)
1 000
Last operation was not zero (COND register bit 13 == 1)
100 1
Cycle count == 0
i
0
A # M (increment instruction register AM)
101
1
Fast shift busy
1
0
Floating point interrupt enable (status register ~1
1
0
1
0
=0)
1 101
Floating point round (status register ~1
1 1 1 0
Class II I/O interrupt disable (status register ~1
1 1 1 1
Micro jump switch
A-12
26
27 == 0)
22 == 0)
F = 15
[
MICRO CONTROL
1101
FII
S
M
This microinstruction performs micro control functions as described in Table A-II.
F = 108 controls shifting operations as follows: for single precision operations,
it causes the shifting of one 16 bit register AO. For double precision operations,
it causes the shifting of two l6-bit register: AO, the most significant 16 bits;
and AI, the least significant 16 bits. The value of the 7 bit combined Sand M
fields is interpreted per Table A-12. The shift count uses A6. One microinstruction delay is required before the microprogram can access the shifted quantity at
the shift matrix output. When using 5=7, the Feed, Partial Product, or Monitor
Clock Register must be selected as specified in 7nble A-13.
Table A-II.
FII
11 10 9 8
0 000
0
0
0
0
000
000
o 00
011
0' 100
0 100
0
101
FII, Sand M-Designators for Microinstruction F=15
FUNCTION
INCREMENT
CLR 110 RETURN
NOT USED
NOT USED
Select Page
Enable
INCREMENT
S
765 4
not used
FUNCTION
M
321 ()
not used
FUNCTION
000 1 Decrement cycle countel
by 1
100 0 Increment SGR
not used
not used
not used
not used
000 1 Decrement cycle countel
by 1
100 0 Increment SGR
o0 0 X
001 X
o lOX
o1 1 X
100 X
101 X
1 lOX
1 1 1 X
CONDITION CODE X X X 0
CONTROL
XXX1
MEMORY
XX0 X
XX 1 X
X0 XX
X1 XX
OXXX
1 XXX
Read
not used
,Write
Read odd
Write odd
Read Split
Write O's
Read Byte
Write Byte
Clr 8 and 9 o X X X No Shift Overflow
Set 8' and 9
Check
on Condition 1 X X X Shift Overflow Check
Clr 10 and 11
Set 10 and 11
on Condition
Compare
masked
Compare
Double Precision
Single Precision
A-13
Table A-11.
FIl
11 1098
FIl, Sand M-Designators for Microinstruction F=15 (Cont)
FUNCTION
S
765 4
FUNCTION
OOXX
XX
lOX X
1 I XX
SGR
A -+ SGR
K -+ SGR
M+ I -+ SGR
M
321 0
FUNCTION
0 1 1 0 NOT USED
0 1 1 1 SGR CONTROL
I 000 SHIFT CONTROL
oI
A + I
not used
See Tables Al2 & Al3
I 001 NOT USED
I o I 0 NOT USED
1
o1
1 NOT USED
I I 0 0 MEMORY
000 X
o0 I X
o lOX
oI I X
I 00 X
I 0 I X
I lOX
Read
Write
Read odd
Write odd
Read Spli t
Write 0' s
Read Byte
not used
I
XXXI
Set Chain Condi tion
Channel Control
Initiate Transfer
XXX1
I 0 1 I/O CONTROL
XX1 X
XI XX
XX I X
X1 XX
I XXX
1 1 1 0 CP CONTROL
I XXX
o0 0 0
X0 0 1
XXXI
Search for Sync
X0 I 0
X0 I I
1
A-14
III
NOT USED
XXI X
Load Discrete
XI 0 0
XI XX
Clear RUN
XI 0 I
XI I 0
I XXX
Reset I/O, Light
,PROG FAULT
XI I I
Enable Out Data
Sel/Clr Status
Clr Interrupt
Clr Chain/Inter
rupt Req.
Halt/Interrupt
Enable power
interrupt
No Operation
Disable RTC interrupt
Enable RTC interrupt
Disable monitor
clock
Enable monitor
clock
Enable RTC Count
Disable RTC
Count
Clear class I +
II interrupts
,.-
Table A-12.
COMBINED SAND
M DESIGNATORS
(7 BITS)
Shift Control Commands (F=15, FII=IO)
FUNCTION
SHIFT COUNT
INTERPRETATION
0000000
Double precision-Circular left shift Al
Shift count=A6 (4 bits)
0000001
Double precision-Circular left shift AO
Shift count=A6 (4 bits)
0000010
Double precision-Arithmetic left
shift Al
Shift count=A6 (4 bits)
0000011
Double precision-arithmetic left
shift AO
Shift count=A6 (4 bits)
0000100
Single precision-Circular left shift AO
Shift count=A6 (4 bits)
0000101
Single precision-Arithmetic left
shift AO
Shift count=A6 (4 bits)
0000110
Extract left shifted bits of Al
Shift count-A6 (4 bits)
0000111
Extract left shifted bits of AO
double or Single precision
Shift count=A6 (4 bits)
0001000
Double precision-Logical right shift Al
Shift count=A6 (4 bits)
0001001
Double precision or single precisionLogical right shift AO
Shift count=A6 (4 bits)
0001010
Double precision-Arithmetic right
shift Al
Shift count=A6 (4 bits)
0001011.
Double precision or single precisionArithmetic right shift AO
Shift count=A6 (4 bits)
0010000
Double precision-Logical right shift Al
Shift count=A6 (4 bits)
- 1 count
0010001
Double preCision or Single precisionLogical right shift AO
Shift count=A6 (4 bits)
- 1 count
0010010
Double precision-Arithmetic right
shift Al
Shift count=A6 (4 bits)
- 1 count
0010011
Double precision or Single precisionArithmetic right shift AO
Shift count=A6 (4 bits)
- 1 count
0011000
~O
to shift matrix output
Shift count=O
0011001
Al to shift matrix output
Shift count=O
O100XXX
See OOOOXXX
Shift count=A6 (6 bits)
A-15
Table A-12.
Shift Control Commands (F=15, FII=lO)
COMBINED S AI'iD
M DESIGNATORS
(7 BITS)
SHIFT COUNT
INTERPRETATION
FUNCTION
0110XXX
See OOlOXXX
Shift count=A6 (6 bits)
- I count
0111000
Cordic scale initialize
A6=17 for trigonometric
function
A6=13 for hyperbolic
function
1010100
Cordic algorithm
A6-17 for trigonometric
function
A6=16 for hyperbolic
function
1011100
Floating point-normalize Al to 223
A6=negative, shift right
A6=positive, shift left
A6=O, no shift
1001101
Floating point-normalize AO to 223
A6=negative, shift right
A6=positive, shift left
A6=O, no shift
1101011
Hexidecimal floating point posi tioning of AO
x 4
Hexidecimal floating point positioning with round of Al
x 4
1110011
Hexidecimal floating paint positioning with round of AO
Shift count=A6 (4 bits)
- I count
1111100
Hexidecimal floating point-normalize
Al to 223,
A6=nega ti ve, shift right
1110010
Shift count=A6 (4 bits)
Shift count=A6 (4 bits
A6=posi tive, shift left
A6=O, no shift
1111101
Hexidec~mal
AO to 2 3
floating point-normalize
A6=negative, shift right
A6=positive, shift left
A6=O, no shift
A-16
I
Table A-13.
Feed/Partial Product/Monitor Clock Selection for Sl =7
COMBINED S AND
M DESIGNATORS
F =15, FII =10
F
REGISTER SELECTION
XXXXX 0 0 X
Feed Register
XXX XX 0 1 X
Partial Product Register
X X X X X lOX
Monitor Clock Register
= 16
MICRO REPEAT
1110
F11
K
This instruction establishes a repeat mode wherein the next instruction or series
of instructions will be repeated as specified in the following paragraphs to accomplish the function specified. K determines the cycle count. The instruction
repeat count is preset to accomplish the function specified. K determines the
cycle count. The instruction repeat count is preset. The MPC transfer (~P) to
~P HOLD before the repeat sequence.
The contents of ~P HOLD are then transferred
back to ~P for each repeat cycle.
Multiply single (F = 16, FII = 0000). This instruction multiplies the single
length multiplicand in Sl by the multiplier in R2 and stores the most significant
half (MSH) of the product in 01 and the least significant half (LSH) of the product in Rl. This instruction is executed when the instruction following it is as
follows:
Add
F
o
S
M
04
01
Sl·
00
The register specified by 01 must be A2 or A3 and must be cleared before executing
this routine. The value of K must be one less than the number of bits of the
mlil tiplier •
Divide single (F = 16, FII = 0001). This .instruction requires both the divisor
and dividend to be· positive. It divides the double length dividend (the MSH
in register 01, the LSH in HI) by the divisor in 51. The quotient is stored in
R2 and the remainder in 01. This instruction is executed when the instructions
following it are as follows:
F
o
S
M
Sub
05
01
Sl
00
Branch Neg
14
00
X
X
Add
04
01
51
03
A-17
The register specified by 01 must be A2 or A3. The quotient is 2's complement
fractional; it will be an integer if the dividend is shifted left 1 bit before
execution of the divide routine. The value of K must be one less than the number
of bits of the divisor.
=
=
Multiply double (F
16, FII
0010). This instruction multiplies the double
length multiplicand (the MSH in A8 or A6 and the LSH in A5 or A7) by the double
length multiplier (the MSH in Rl and the LSH in R2). The 32 bits in the MSH of
the product are in Rl and R2 with Rl containing the upper 16 bits. The 32 bits
in the LSH of the product are in A2 and A3 with A2 containing the upper 16 bits.
This instruction is executed when the instructions following it are as follows:
F
o
S
M
Add
04
13
Sl
10
Add
04
12
S2
01
Add Constant
10
13
o
00
The A2 and A3 registers must be cleared before executing these instructions.
value of K must be one less than the number of bits of the multiplie~.
The
Divide double (F = 16, FII = 0011). This instruction requires both the divisor
and the dividend to be positive. It divides the 64 bit dividend (the upper 16
bits of the MSH in A3 and the lower 16 bits of the MSH in A2, and the upper 16
bits of the LSH in Rl and the lower 16 bits of the LSH in R2) by the double length
divisor (the MSH in A5 or A7 and the LSH in A4 or A6). The quotient is stored in
Rl and R2 and the remainder stored in A2 or A3. This instruction is executed when
the instructions following it are as follows:
F
o
S
M
Sub
05
13
Sl
10
Sub
05
12
S2
11
Branch Neg
14
00
x
x
Add
04
13
Sl
13
Add
04
12
S2
01
The quotient is2's complement fractional; it will be n integer if the dividend is
shifted left 1 bit before executing this instruction. The branch routine is for
end correction if required. The value of K must be one less than the number of
bits of the divisor.
Repeat rotate (F
tions K+l times.
"
= 16,
Add
A-18
=
FII
0100). This instruction repeats the next 3 instrucIt is executed when the instructions following it are as follows:
F
o
S
M
02
12
11
XOll
F
D
S
M
Add
04
11
06
X011
X110
Add
04
10
06
0011
0110
Repeat vector (F = 16, FII = 0101. This instruction repeats the next 3 instructions
K+I times. It is executed when the instructions following it are as follows:
F
D
S
M
Add
02
12
11
03
Add
04
11
06
13
Add
04
10
06
03
Repeat scale (F = 16, FII = 0110). This instruction repeats the next 2 instructions K+l times. It is executed when the instructions following it are as follows:
either:
or:
F
D
S
M
Sub
05
10
06
00
Sub
05
11
06
00
Add
04
10
06
03
Add
04
11
06
03
Square root repeat (F = 16, FII = 0111). This instruction repeats the next 2
instructions K+l times. It is executed when the instructions following it are
as follows:
F
D
S
M
Add
04
12
06
13
Add
04
12
00
03
Repeat normal (F = 16, FII = 1000). This instruction executes the K+l instructions
following it n+l times. K+l shall be equal to the value in bits 3-0 of K, plus
one. n+l shall be equal to the contents of the cycle count register plus one
(which must be loaded by a previous instruction).
Repeat normal, suppress last cycle (F =b16, FII = 1001). This instruction executes
the K+l instructions following it n times. K+I shall be specified by the value in
bits 3-0 of K, plus one. n shall be equal'to the contents of the cycle count
register (which must be loaded by a previous instruction).
A-19
F = 17
EMULATE
1111
so
Dl
M
This instruction is freeform and is interpreted as shown in Table A-14.
TABLE A-14.
Sand M-Designators for F=17
S
M
765 4
FUNCTION
FUNCTION
321 0
o XXX
Load SGR
000 0
I/O Breakpoint
1 X X X
Inhibit Load SGR
000 1
Not Assigned
001 0
Not Assigned
001 1
Operand Reference (Destination
o1
0 0
Not Assigned
o1
0 1
Normal Branch 1. If bit 11 of
ECW set, P ~ MAR. If bit 11 of
ECW clear, GR ~ MAR.
o1
1 0
Not Assigned
Normal branch 2. If bit 12 of ECW
is clear, P ~ MAR and force read.
If bit 12 of ECW is set, P~ MAR,
and initiate the operation selected
by bits 15-13 of the ECW.
100 0
Restart overlap.
advance P
1 0 0 1
Branch 1 special. Des t ~ MAR,
Inhibit I/O, and force read.
o1
0
Not Assigned
101 1
Not Assigned
1 1 0 0
Normal Start.
P
~
MAR, no
Branch, P
~
MAR,
P+l~P.
A-20
MAR
011 1
1
..
~
1 1 0 1
Branch 1 special. Des t ~ MAR,
Inhibit I/O, and force read .
1 1 1 0
Normal start jump. Branch,
Dest ~ MAR, P + 1 ~ P.
1 1 1 1
Not Assigned
APPENDIX B
REPERTOIRE OF MACRO INSTRUCTIONS
Instructions defined in this list include the basic instruction set and those required for optional features in the computer. Users of computer configurations
that do not include certain optional instructions must place those respective
instructions in the "Not assigned" category and assemble programs accordingly.
The instructions are described in the following format:
(Operation Code)
(ULTRA symbol) (instruction format) (instruction name)
(Detailed descriptive text that includes special designator interpretations when
applicable)
When the a- or m-designator is used as a sub-function code, the information is
presented in table form.
Symbols Used In Instructions
Symbol
Description
a
The a-designator from instruction words.
d
The deviation value in a local jump instruction.
R
The register designated by a.
m
The m-designator from instruction words.
R
The register designated by m.
y
The operand or memory address generated in the execution of an
instruction.
Y
The contents of the second word of an RK or RX instruction.
P.
The Program Address register.
j.LP
The Micro Program Address Register
( )
The contents of the location specified within the parenthesis.
a
m
Operation Code 00
RR Format - DIAGNOSTIC RETURN
If the DIAGNOSTIC JUMP switch is in the up position, transfer the contents
of General Register 178 to j.LP.
RI Format - Not assigned
B-1
RK Format - Not assigned
BL
RX Format - BYTE LOAD
Load the selected byte from address Y in bits 7 through 0 of Ra , clearing
bits 15 through 8, and setting the Condition Code.
=
Address Y Y + (Rm) right shifted one place; bit 0 of Rm is the byte
identifier.
Operation Code 01
LR
RR Format - LOAD
Load (Rm) in Ra , and set the Condition Code (table XIII).
LI
RI Format Type 2 - LOAD
Load the contents of memory address Y in Ra , and set the Condition Code
(table XIII).
LK
RK Format - LOAD
Load the Operand Y in Ra , and set the Condition Code (table XIII).
L
RX Format - LOAD
Load the contents of memory address Y in Ra , and set the Condition Code
(table XIII).
Operation Code 02
RR Format - UNARY ARITHMETIC
Perform the operation specified for the m-value in Table I and then set
the Condition Code according to the quantity resulting in Ra (table XIII).
LDI
RI Format, Type 2 - LOAD DOUBLE
Load the contents of addresses Y and Y+l in Ra and Ra+l respectively, and
set the Condition Code (table XIII).
RK Format - Not assigned
LD
RX Format - LOAD DOUBLE
This instruction shall load the contents of memory address Y and Y + 1 in
Ra and Ra+l respectively, and set the Condition Code (table XIII).
Operation Code 03
RR Format - UNARY-CONTROL
Perform the operation specified in Table II for the m-value.
,
ffi
B-2
RI Format - Not assigned
RK Format - Not assigned
See Table I
See Table II
TABLE 1.
ULTRA
Symbol
PR
UNARY-ARIlliMETIC INSTRUCTION m-VALUES
m
Value
o
Description
Operatiun
MAKE POSITIVE
If (Ra) are negative, perform the two's complement of (Ra) and store the result in R .
When the maximum negative number* is comp~e
mented, set the overflow designator (table
XIII ).
If (Ra) are positive, do not change (R a ).
NR
1
MAKE
l~EGATIVE
If (Ra) are positive and not zero, perform
the two's complement of (Ra) and store the
resul t in Ra'
If (Ra) are negative or zero, do not change
(Ra) .
RR
2
ROUND Ra
If (R ) are positive, add bit 15 of Ra+l
to (R:) and ~tore the result in Ra'
Jf (Ra) are negative, subtract the complement of bit 15 of Ra+l from (Ra) and store
the result in Ra
Not assigned
3
TCR
4
TWO'S COMPLEMENT,
SINGLE
Perform the two's complement of (Ra) and
store the result in Ra.
TCDR
5
TWO'S COMPLEMENT,
DOUBLE
Perform the two's complement of double length
(R a , Ra+l) and store the result in Ra , Ratl .
When the maximum negative number* is comp emented, set the overflow designator (table
XIII).
OCR
6
ONE'S COMPLEMErH,
SINGLE
Perform the one's complement of (Ra) and
store the result in Ra'
Not assigned
7
TROR
10
INCREASE Ra BY 1
Increase (Ra) by 1 and store the result in Ra'
DROR
11
DECREASE Ra BY 1
Decrease (Ra) by 1 and store the result in Ra'
TRTR
12
INCREASE Ra BY 2
Increase (Ra) by 2 and store the result in Ra'
DRTR
13
DECREASE Ra BY 2
Decrease (Ra) by 2 and store the result in Ra'
14-17
Not assigned
,;, ( 1 ,000 , 000 , 000, 000, 000 )
B-3
TABLE II.
ULTRA
m
Symbol
Value
UNARY-CONTROL INSTRUCTION m-VALUES
Description
Operation
ER
1
STORE STATUS
REGISTER #1
Store the contents of Status Register #1
in Ra'
SSOR
2
STORE STATUS
REGISTER #2
Store the contents of Status Register #2
in Ra'
SCR
3
STORE RTC LOWER
Store the contents of the Real Time Clock
Lower Register in Ra'
LPR
4
LOAD P
Load (Ha) in P.
LSOR
5
LOAD STATUS
REGISTER #1
Load (Ra) in Status Register #1.
LSTR
6
LOAD STATUS
REGISTER #2
Load (Ra) in Status Register #2.
LCR
7
LOAD RTC LOWER
Load (Ra) in the Real Time Clock Lower
Register.
ECR
10
ENABLE RTC
Enable the Real Time Clock Register to
increase by one for each cycle of the clock
sources. Generate a RTC Interrupt when
the contents of the Real Time Clock Lower
Register changes from all ones to all zeros
DCR
11
DISABLE RTC
Disable the Real Time Clock Register from
advancing. The RTC Oscillator continues
to operate.
12
LOAD AND ENABLE
CLOCK MONITOR
Load (Ra) in Monitor Clock Register and
enable register to decrement by one for
each cycle of the clock source. Generate
the Monitor Clock interrupt when the contents of the Monitor Clock Register equals
zero.
13
DISABLE MONITOR
CLOCK
Disable Monitor Clock and Monitor Clock
Interrupt.
14
LOAD RTC DOUBLE
Load (R a • Ra + 1) in the Real Time Clock
Register and enable the register to increase by one for each cycle of the clock
source. RTC Interrupt enable/disable
condition is not affected.
15
STORE RTCDOUBLE
Store the contents of the Real Time Clock
into Ra and Ra + 1.
B-4
I
TABLE II.
ULTRA
Symbol
m
Value
UNARY-CONTROL INSTRUCTIONS m-VALUES (CONT)
Operation
Description
---
16
ENABLE RTC INTERRUPT
Enable generation of RTC interrupt when
the contents of the Real Time Clock Lower
Register changes from all ones to all
zeros.
---
17
DISABLE RTC INTERRUPT
Disable generation of the RTC Interrupt.
LM
RX Format - LOAD MULTIPLE
Load the contents of sequential memory addresses beginning at Y, in
sequential registers beginning at Ra and ending at Rm. If a is greater
than m, load registers in the order Ra , Ra+l' ... , R17, RO ... Rm. Address
Y is equal to y.
Operation Code 04
RR Format - UNARY-SHIFT (Optional Feature)
Perform the operation specified in Table III for the m-value.
RI Format - Not assigned
RK Format - Not assigned
BLX
RX Format - BYTE LOAD AND INDEX BY 1
Load the selected byte from memory address Y in bits 7 through 0 of Ra
clearing bits 8 through 15 and setting the Condition Code (table XIII);
and then increase (Rm) by 1.
Address Y = Y + (Rm) right shifted one place; bit 0 of Rm is the byte
identifier.
Operation Code 05
SB
RR Format - SET BIT
Set the bit in Ra specified by the m-value.
LXI
RI Format,Type 2 - LOAD AND INDEX BY 1
Load the contents of memory address Y in R • set the Condition Code
(table XIII), and then increase (Rm) by l.a
RK Format - Not assigned
LX
RX Format - LOAD AND INDEX BY 1
Load the contents of memory address Y in Ra. set the Condition Code
(table XIII), and then increase (Rm) by 1.
~ See Table III
B-5
TABLE III..
TTT'T'D1I
u ..... ~1.l11.
Symbol
UNARY-SHIFT INSTRUCTION m-VALUE
i11
o
RVR
1
Description
Operation
Value
Not assigned
REVERSE REGISTER
Change (Ra) to the reverse order
according to the 4-bit example:
Initial
Final
CNT
2
COUNT ONES
Count the number of one bits in (R a ),
and store the count in Ra+l.
SFR
3
SCALE FACTOR
Shift the double length (Ra , Ra+l)
to the left with zeros extended to
fill, until bits 15 and 14 of Ra
are not equal and store the shift
count in Ra+2.
4-17
Not assigned
Operation Code 06
ZBR
RR Format - ZERO BIT (Clear Bit)
Clear the bit in Ra specified by the m-value.
LDXI
RI Format, Type 2 - LOAD DOUBLE AND INDEX BY 2
Load the contents of memory address Y and Y + 1 in Ra and Ra+l
respectively, set the Condition Code (table XIII), and then increase
(Rm) by 2.
RK Format - Not assigned
LDX
RX Format - LOAD DOUBLE AND INDEX BY 2
Load the contents of memory address Y and Y + 1 in Ra and Ra+l
respectively, set the Condition Code (table XIII), and then increase
(Rm) by 2.
Operation Code 07
CBR
B-6
RR Format - COMPARE BIT (Test Bit)
Test the bit in Ra specified by the m-value and set the Condition Code
(Table XIII) if the bit is set.
LPI
RI Format, Type 2 - LOAD PSW (Program Status Word)
Load the contents of memory addresses Y, Y + 1, and Y + 2 in Program
Address Register, Status Register ~l, and Status Register ~2,
respectively. Y = (R m).
RK Format - Not assigned
LP
RX Format - LOAD PSW (Program Status Word)
Load the contents of memory addresses Y, Y + 1, and Y + 2 in the Program
Address Register, Status Register ~l, and Status Register ~2,
respectively. Y = (Rm) + y.
Operation Code 10
LRSR
RR Format - LOGICAL RIGHT SINGLE SHIFT
Shift (Ra) to the right n-places with zeros extended to fill.
value in bits 5-0 of Rm.
n is the
RI Format - Not assigned
LRS
BS
RK Format - LOGICAL HIGHT SINGLE SHIFT
Shift (Ha) to the right n places with zeros extended to fill.
value in bits 5-0 of operand Y.
n is the
RX Format - BYTE STORE
Store bits 7-0 of (Ra) in the selected byte of memory address Y.
Y = Y + (Rm) right shifted one place; bit 0 of (Rm) is byte identifier.
Operation Code 11
AHSR
RR Format - ALGEBRAIC RIGHT SINGLE SHIFT
Shift (Ra) to the right n places with sign extended to fill.
value in bits 5-0 of Rm.
SI
RI Format, Type 2 - STOllE
Store (Ha) at memory address Y.
ARS
Format HK - ALGEBHAIC RIGHT SINGLE SHIFT
Shift (Ra) to the right n places with sign extended to fill.
value in bits 5-0 of operand Y.
n is the
n is the
RX Format - STORE
Store (Ra) at memory address Y.
S
Operation Code 12
LHDR
RH Format - LOGICAL HIGHT DOUBLE SHIFT
Shift the double length (H a , Ra+l) to the right n-places with zeros
extended to fill. n is the value in bits 5-0 of Rm.
SDI
RI Format, Type 2 - STORE DOUBLE
Store (Ra) and (Ra+l) at memory addresses Y and Y + 1 respectively.
,
B-7
LRD
RK Format - LOGICAL RIGHT DOUBLE SHIFT
Shift the double length (Ra , Ra+l) to the right n places with zeros
extended to fill. n is the value in bits 5-0 of operand Y.
SD
RX Format - STORE DOUBLE
Store (Ra) and (Ra+l) at memory addresses Y and Y + 1 respectively.
Operation Code 13
ARDR
RR Format - ALGEBRAIC RIGHT DOUBLE SHIFT
Shift the double length (R a , Ra+l) to the right n places with the sign
extended to fill. n is the value in bits 5-0 of Rm.
RI Format - Not assigned
ARD
RK Format - ALGEBRAIC RIGHT DOUBLE SHIFT
Shift the double length (Ra , Ra+l) to the right n places with the Ra sign
extended to fill. n is the value in bits 0-5 of operand Y.
SM
RX Format - STORE MULTIPLE
Store in sequential memory addresses beginning at Y, the contents of
sequential registers beginning at Ra and ending at Rm. If a is greater
than m store registers in the order Ra , Ra+l' •.• ' R17, Ro' ••. ' Rm.
Y equals y.
Operation Code 14
ALSR
RR Format - ALGEBRAIC LEFT SINGLE SHIFT
Shift (Ra) to the left n places with zeros extended to fill.
value in bits 5-0 of Rm.
n is the
RI Format - Not assigned
ALS
BSX
RK Format - ALGEBRAIC LEFT SINGLE SHIFT
Shift (Ra) to the left n places with zeros extended to fill.
value in bits 5-0 of operand Y.
n is the
RX Format - BYTE STORE AND INDEX BY 1
Store bits 7-0 of Ra in the selected byte at memory address Y; and then
increase (Rm) by 1. Y = Y + (Rm) right shifted one place; bit 0 of (Rm)
is byte identifier.
Operation Code 15
CLSR
SXI
B-8
RR Format - CIRCULAR LEFT SINGLE SHIFT
Shift (Ra) circularly to the left n places.
of Rm.
n is the value in bits 5-0
RI Format, Type 2 - STORE AND INDEX BY 1.
Store (Ra) at memory address Y; and then increase (Rm) by 1.
Y = (Rm).
CLS
RK Format - CIRCULAR LEFT SINGLE SHIFT
Shift (Ra) circularly to the left n places.
of operand Y.
SX
n is the value of bits 5-0
RX Format - STORE AND INDEX BY 1
Store (Ra) at memory address Yj and then increase (Rm) by 1.
Operation Code 16
ALDR
RR Format - ALGEBRAIC LEFT DOUBLE SHIFT
Shift the double length (R a , Ra+l) to the left n places with zeros
extended to fill. n is the value in bits 5-0 of Rm.
SDXI
RI Format, Type 2 - STORE DOUBLE AND INDEX BY 2
Store (Ra) and (Ra+l) at memory addresses Y and Y + 1, respectively;
then increase (Rm) by 2.
ALD
RK Format - ALGEBRAIC LEFT DOUBLE SHIFT
Shift the double length (R a , Ra+l) to the left n places with zeros
extended to fill. n is the value in bits 5-0 of operand Y.
SOX
RX Format - STORE DOUBLE AND r:mEX BY 2
Store (Ra) and (Ra+l) at memory addresses Y and Y + 1, respectively;
and then increase (Rm) by 2.
Operation Code 17
CLDR
RR Format - CIRCULAR LEFT DOUBLE SHIFT
Shift the double length (R a , Ra+l) circularly to the left n places.
n is the value in bits 5-0 of Rm.
SZI
RI Format, Type 2 - STORE ZEROS
Clear memory address Y. Y = (Rm)
CLD
RK Format - CIRCULAR LEFT DOUBLE SHIFT
Shift the double length (Ra , Ra+l) circularly to the left n places.
n is the value in bits 5-0 of Y.
SZ
RX Format - STORE ZEROS
Clear memory address Y.
Operation Code 20
SUR
,
SUI
RR Format - SUBTRACT
Subtract (Rm) from (Ra) and store the result in Ra; then set the
Condition Code (table XIII).
RI Format, Type 2 - SUBTRACT
Subtract the contents of memory address Y from (Ra) and store the result
in Ra; then set the Condition Code (table XIII). Y = (R m).
SUK
RK Format - SUBTRACT
Subtract operand Y from (R ) and store the result in Ra; then set the
Condition Code (table XIII'.
SU
RX Format - SUBTRACT
Subtract the contents of memory address Y from (Ra) and store the result
in Ra; then set the Condition Code (table XIII).
Operation Code 21
SUDR
RR Format - SUBTRACT DOUBLE
Subtract the double length (Rm, Rm+1) from the double length (Ra , Ra+l)
and store the result in Ra and Ra+1; then set the Condition Code (table
XIII) •
SUDI
RI Format, Type 2 - SUBTRACT DOUBLE
Subtract the double length contents of memory addresses Y, Y + 1 from the
double length (Ra , Ra+l) and store the result in Ra and Ra+1; then set
the Condition Code (table XIII).
RK Format - Not assigned
SUD
RX Format - SUBTRACT DOUBLE
Subtract the double length contents of memory addresses Y, Y + 1 from the
double length (R a , Ra+l) and store the result in Ra and Ra +1; then set
the Condition Coae (taole XIII).
Operation Code 22
AR
RR Format - ADD
Add (Rm) to (Ra) and store the result in Ra; then set the Condition Code
(table XIII). .
AI
RI Format, Type 2 - ADD
Add the contents of memory address Y to (Ra) and store the result in Ra;
then set the Condition Code (table XIII).
AK
RK Format - ADD
Add operand Y to (Ra) and sto5re th result in Ra; and then set the
Condition Code (table XIII).
A
RX Format - ADD
Add the contents of memory address Y to (Ra) and store the result in Ra;
and then set the Condition Code (table XIII).
Operation Code 23
ADR
B-10
'RR Format - ADD DOUBLE
Add the double length (Rm, Rm+1) to the double length (Ra , Ra+l) and store
the result in Ra and Ra+1; then set the Condition Code (table XIII).
ADI
RI Format, Type 2 - ADD DOUBLE
Add the double length contents of memory addresses Y, Y + 1 to the
double length (R a , Ra+l) and store the result in Ra and Ra+l; then set
the Condition Code (tanle XIII).
RK Format - Not assigned
AD
RX Format - ADD DOUBLE
Add the double len~th contents of memory address Y, Y + 1 to the double
length (R a , Ra+l) and store the result in Ra and Ra+l; then set the
Condition Code (table XIII).
Operation Code 24
CR
RR Format - COMPARE
Arithmetically compare (Ra) to (Hm), and set the Condition Code (table
XIII) .
CI
RI Format, Type 2 - COMPARE
Arithmetically compare (Ra) to the contents of memory address Y, and set
the Condition Code (Table XIII).
CK
RK Format - COMPARE
Arithmetically compare (Ra) to operand Y, and set the Condition Code
(table XIII).
C
RX Format - COMPARE
Arithmetically compare (Ra) to the contents of memory address Y, and set
the Condition Code (table XIII).
Operation Code 25
CDR
RR Format - COMPARE DOUBLE
Arithmetically compare the double length (R a , Ra+l) to the double length
(Rm, Rm+l) and set the Condition Code (table XIII).
CDI
RI Format, Type 2 - COMPARE DOUBLE
Arithmetically compare the double length (R a , Ra+l) to the double length
contents of memory addresses Y, Y + 1 and set the Condition Code (table
XIII) ,
RK Format - Not assigned
CD.
RX Format - COMPARE DOUBLE
Arithmetically compare the double length (R a , Ra+l) to the double length
contents of memory address Y, Y + 1 and set the Condition Code (table
XIII ).
Operation Code 26
MR
RR Format - MULTIPLY
Multiply (Rm) by (Ratl) and store the double length result in Ra , Ra+];
and then set the CondItion Code (table XIII).
B-ll
MI
RI Format, Type 2·- MULTIPLY
Multiply the contents of memory address Y by (Ra+l) and store the double
length result in Ra , Ra+l; and then set the Condition Code (table XIII).
MK
RK Format - MULTIPLY
Multiply operand Y by (Ra+l) and store the double length result in
Ra , Ra+l; and then set the Condition Code (table XIII),
M
RK Format - MULTIPLY
Multiply the contents of memory address Y by (Ra+l) and store the double
length result in Ra , Ra+l ; then set the Condition Code (table XIII).
Operation Code 27
DR
RR Format - DIVIDE
Divide the double length (Ra, Ra+l) by (Rm), store he quotient in Ra+l
and the remainder in Ra; then set the Condition Code (table XIII).
DI
RI Format, Type 2 - DIVIDE
Divide the double length (Ra , Ra+l) by the contents of memory address Y;
store the quotient in Ra+l and the remainder in Ra; then set the Condition
Code (table XIII).
DK
RK Format - DIVIDE
Divide the double length (Ra , Ra+l) by operand Y, store the quotient in
Ra+l and. the remainder in Ra; then set the Condition Code (table XIII).
D
RX Format - DIVIDE
Divide the double length (Ra , Ra+l) by the contents of memory address Y,
store the quotient in Ra+l and the remainder in Ra; then set the Condition
Code (table XIII).
Note:
For all divides, the remainder has the same sign as the dividend
and is interpreted as fOllows:
Remainder
Sign
+
Divisor
Sign
+
Remainder
Less than the divisor.
Less than the absolute value of
the two's complement of the
divisor.
+
+
Less than the divisor.
The absolute value of the remainder is less than the
absolute value of the divisor.
8-12
Operation Code 30
ANDR
RR Format - AND
Perform the logical AND of (Ha) and (Rm), and store the result in Ra
(clear bits in Ra corresponding to zeros in Rm). Set Condition Code
(table XIII).
ANUI
RI Format, Type 2 - AND
Form the logical AND of (Ra) and the contents of memory address Y, and
store the result in R~ (clear bits in Ra corresponding to zeros in the
contents of address Y). Set Condition Code (table XIII).
ANDK
RK Format - AND
Form the logical AND of (Ra) and operand Y, and store the result in Ra
(clear bits in Ra corresponding to zeros in operand Y). Set Condition
Code (table XIII).
AND
RX Format - AND
Form the logical AND of (Ra) and the contents of memory address Y, and
store the result in Ra (clear bits in Ra corresponding to zeros in the
contents of address Y). Set Condition Code (table XIII).
Operation Code 31
ORR
RR Format - OR
Form the logical OR of (Ra) and (R m), and store the result in Ra.
Condition Code (table XIII).
Set
ORI
RI Format, Type 2 - OH
Form the logical OR of (Ra) and the contents of memory address Y, and
store the result in Ra' Set Condition Code (table XIII).
aRK
RK Format - OR
Form the logical OR of (Ra) and operand Y, and store the result in Ra .
Set Condition Code (table XIII).
OR
nx Format - OR
Form the logical OR of (Ra) and the contents of memory address Y, and
store the result in Ra' Set Condition Code (table XIII).
Operation Code 32
XORR
RR Format - EXCLUSIVE OR
Form the exclusive OR of (Ra) and (Rm), and store the result in Ra'
Set Condition Code (table XIII).
XORI
,
RI Format, Type 2 - EXCLUSIVE OR
Form the exclusive OR of (Ra) and the contents of memory address Y, and
store the result in Ra' Set Condition Code (table XIII).
XORK
RK Format - EXCLUSIVE OR
Form the exclusive OR of (R ) and operand Y, and store the result in Ra.
Set Condition Code (table X'II).
8-13
XOR
RX Format - EXCLUSIVE OR
Form the exclusive OR of (Ra) and the contents of memory address Y, and
store the result in Ra. Set Condition Code (table XIII).
Operation Code 33
MSR
RR Format - MASKED SUBSTITUTE
For each bit set in (Ra+l), transfer the corresponding bit of (Rm) to the
corresponding bit in Ra and leave the remaining bits in Ra unchanged.
Set Condition Code (table XIII).
MSI
RI Format, Type 2 - MASKED SUBSTITUTE
For each bit set in (Ra+l), transfer the corresponding bit of the contents of memory address Y to the corresponding bit in Ra and leave the
remaining bits in Ra unchanged. Set Condition Code (table XIII).
MSK
RK Forma t - MASKED SUBSTITUTE
For each bit set in (Ra+l), transfer the corresponding bit of operand Y
to the corresponding bit in Rq and leave the remaining bits in Ra unchanged. Set Condition Code ttable XIII).
MS
RX Forma t - MASKED SUBSTITUTE
For each bit set in (Ra+l), transfer the corresponding bit of the contents of memory address Y to the corresponding bit in Ra and leave
the remaining bits in Ra unchanged. Set Condition Code (table XIII).
Operation Code 34
CMR
RR Format - COMPARE MASKED
Compare (bit by bit) the result of the logical AND of (Ra) and (Ratl) to
the result of the logical AND of (Rro) and (Ra+l) and set the Condl lon
Code (table XIII).
.
CMI
RI Format, Type 2 - COMPARE MASKED
Compare (bit by bit) the logical AND of (Ra) and (Ra+l) to the logical
AND of contents of memory address Y and (Ra+l) and set the Condition
Code (table XIII).
CMK
RK Format - COMPARE MASKED
Compare (bit by bit) the logical AND of (Ra) and (Ra+l) to the logical
AND of operand Y and (Ra+l) and set the Condition Code (table XIII).
CM
RX Format - COMPARE MASKED
Compare (bit by bit) the logical AND of (Ra) and (Ra+l) to the logical
AND of contents of memory address Y and (Ra+l) and set the Condition
Code (table XIII).
Operation Code 35
IOCR
B-14
RR Format - I/O COMMAND
Execute the. I/O command instruction from main memory address 000140 and
clear bits 14 and 15 at address 000140.
BFI
RI Forma t, Type 2 - BIASED FETCH
Transfer the sign (bit 15) of the contents of memory address Y to the
Condition Code and then set the two most significant bits at that memory
location, leaving the remaining bits unchanged.
REX
RK Format - EXECUTE REMOTE
Execute the instruction stored at memory address Y; do not change (P)
when reading this instruction. Then continue with the next sequential
instruction.
BF
RX Format - BIASED FETCH
Transfer the sign (bit 15) of the contents of memory address Y to
Condition Code bits 8 and 9 and then set the two most significant bits
at that memory location, leaving the remaining bits unchanged.
Operation Code 36 - Not assigned
Operation Code 37 - Not assigned
Operation Code 40
RR Forma t - CONDITIO!'IAL JUMP
Test for the condition specified in table IV for the a-value and perform
one of the following:
w
(1)
If the specified condition is met, load (Rm) in P (jump to the instruction located at the address specified in Rm). If a specified
Stop, or a Stop Key condition is met, disable RTC and stop the computer. On restart, load (Rm) in P (jump to the instruction at the
address specified by (R m».
(2)
If the specified jump condition is not met, execute the next instruction. If the specified stop condition is not met, execute the jump
without stopping.
RI Format, Type 1 - LOCAL Jm1P
Load Y in P (jump to the instruction located at memory address Y).
Y = (P)i ±d.
RK Format - CONDITIONAL JUMP
Test for the condition specified in Table IV for the a-value and perform
one of the following:
CD
(1)
If the specified condition is met, load Y in P (jump to the instruction located at the address specified by operand Y). If a specified
Stop, or a Stop Key condition is met, disable RTC and stop the computer. On restart, load Y in P (jump to the instruction located at
the address specified by operand Y).
(2)
If the specified jump condition is not met, execute the next instruction. If the specified stop condition is not met, execute the jump
without stopping.
See Table IV
B-15
TABLE IV.
CONDITIONS FOR a-VALUE IN JUMP INSTRUCTIONS
ULTRA Symbol
for Format
Jump Condition
aValue
Condition code for
Arithmetic Operation
Indicates
Condition code for
Compare Operation
Indicates
RR
RK
RX
JER
JE
JE
o
Zero
JNER
JNE
JGE
1
Not Zero (bit 8 = 1)
Not Equal (bit 8 =1)
JGER
JGE
JGE
2
Positive (bit 9 = 0)
Greater Than or
(bi t 9 = 0)
Equal
JLSR
JLS
JLS
3
Negative (bit 9 = 1)
Less Than (bit 9 = 1)
JOR
JO
JO
4
Overflow designator is set
JCR
JC
JC
5
Carry designator is set
JPTR
JPT
JPT
6
Power is out of tolerance
JBR
JB
JB
7
Bootstrap 2 is selected
JR
J
J
10
Unconditional Jump
JSR
JS
JS
11
Stop; jump on restart
JKSR
JKS
JKS
12
Stop if program stop key 1 is selected, jump
on restart
JKSR
JKS
JKS
13
Stop if program stop key 2 is selected, jump
on restart
--- 14-17
(bit 8 = 0)
Equal
(bit 8
= 0)
Not assigned
RX Format - CONDITIONAL JUMP
Test for the condition specified in Table IV for the a-value and perform
one of the fQllowing.
(1)
~
o
B-16
(2)
If the speoified condition is met, load (Y) in P (jump to the instruction located at the address specified by the contents of memory
address Y). If a specified Stop, or a Stop Key condition is met,
disable RTC and stop the computer. On restart, load (Y) in P (jump
to the instruction located at the address specified by the contents
of memory address Y).
If the specified jump condition is not met, Execute the next instruction. If the specified stop condi tion is not met, execute the jump
without stopping.
See Table IV
Operation Code 41
XJR
RR Format - INDEX JUMP
Test (Ra) and perform one of the following:
(1)
If (Ha) does not equal zero, decrease (Ra) by 1 and load (Rm) in P
(jump to the instruction located at the address stored in Rm).
(2)
If (Ra) equals zero, execute the next instruction.
LJ
RI Format, Type 1 - LOCAL JUMP INDIRECT
Unconditionally jump to the address specified by the contents of memory
address Y. Y = (P)±D.
XJK
RK Format - INDEX JUMP
Test (Ra) and perform one of the following:
XJ
(1)
If (Ra) does not equal zero, decrease (Ra) by 1 and load operand Y
in P (jump to the instruction located at address Y).
(2)
If (Raj equals zero, execute the next instruction.
RX Format - INDEX JUMP
Test (Ra) and perform one of the following:
(1)
If (Ra) does not equal zero, decrease (Ra) by 1 and load (Y) in P
(jump to the instruction located at the address specified by the
contents of memory address Y).
(2)
If (Ra) equals zero, execute the next instruction.
Operation Code 42
JLRR
RR Format - JUMP AND LINK REGISTERS
Store (P)+l in Ra , and load (Rm) in P (jump to the instruction located
at the address stored in Rm).
RI Format - Not assigned
JLR
RK Format - JUMP AND LIi~K HEGISTER
Store (P)+2 in Ra , and load operand Y in P (jump to the instruction
located at the address Y).
JLK
RX Format - JUMP AND LINK REGISTER
Store (P)+2 in Ra , and load (Y) in P (jump to the instruction located
at the address specified by the contents of address Y).
Operation Code 43
RR Format - Not assigned
LJLM
RI Format, Type 1 - LOCAL JUMP AND LINK MEMORY
Store (P)+l at memory address Y, and load Y+l in P (jump to the
instruction located at memory address Y+l. Y (P)±d.
=
B-17
JLM
RK Format - JUMP AND LINK MEMORY
Store (P)+2 at memory address Y, and load Y+1 in P (jump to the instruction located at memory address Y+1).
JLM
RX Format - JUMP AND LINK MEMORY
Store (P)+2 at the address specified by the contents of address Y, and
load (Y+1) in P (jump to the instruction located at the address specified
by the contents of address Y+1).
Operation Code 44
=
JZR
RR Format - JUMP REGISTER 0
Test (Ra) and perform one of the following:
LJE
(1)
If (Ra) equals zero, load (Rm) in P (jump to the instruction located
at the address stored in Rm).
(2)
If (Ra) does not equal zero, execute the next instruction.
RI Format, Type 1 - LOCAL JUMP EQUAL
Test the Condition Code in the Status Register and perform one of the
following:
(1)
If bit 8 of the Condition Code is zero, load Y in P (jump to the
instruction located at memory address Y). Y = (P)±d.
(2)
If bit 8 of the Condition Code is not zero, execute the next instruction.
=
JZ
RK Format - JUMP REGISTER 0
Test (Ra) and perform one of the following:
(1)
If (Ra) equals zero~ load operand Y in P (jump to the instruction
located at the address specified by operand Y).
(2)
If (Ra) does not equal zero, execute the next instruction.
RX Format - JUMP REGISTER = 0
Test (Ra) and perform one of the following:
JZ
(1)
If (Ra) equals zero, load (Y) in P (jump to the instruction located
at address specified by the contents of mem~ry address Y).
(2)
If (Ra) does not equal zero, execute the next instruction.
Operation Code 45
JNZR
"I>
8-18
RR Format - JUMP REGISTER ~ 0
Test (Ra) and perform one of the following:
(1)
If (Ra) does not equal zero, load (Rm) in P (jump to the instructi\ln
located at the address stored in Rm).
(2)
If (Ra) equals zero, execute the next instruction.
LJNE
JNZ
JNZ
RI Format, Type 1 - LOCAL JUMP NOT EQUAL
Test the Condition Code and perform one of the following:
(1)
If bit 8 of the Condition Code is one, load Y in P (jump to the
instruction located at memory address Y). Y = (P)±d.
(2)
If bit 8 of the Condition Code is not one, execute the next
instruction.
RK Format - JUMP REGISTER # 0
Test (Ra) and perform one of the following:
(1)
If (Ra) does not equal zero, load Y in P Uump to the instruction
located at the address specified by operand Y).
(2)
If (Ra) equals zero, execute the next instruction.
RX Format - JUMP REGISTER # 0
Test (Ra) and perform one of the following:
(1)
If (Ra) does not equal zero, load (Y) in P (jump to the instruction
located at the address specified by the contents of memory address
YL
(2)
If (Ra) equals zero, execute the next instruction.
Operation Code 46
JPR
LJGE
JP
RR Format - JUMP REGISTER POSITIVE
Test (Ra) and perform one of the following:
0)
If (R ) is equal to or greater than zero, load (Rm) in P U ump to
(2)
If (Ra) is less than zero, execute the next instruction.
the i~struction located at the address stored in Rm).
RI Format, Type 1 - LOCAL JUMP GREATER THAN OR EQUAL
Test the Condition Code and perform one of the following:
(1)
If bit 9 of the Condition Code is a zero, load Y in P (jump to the
instruction located at memory address Y). Y (P)±d.
(2)
If bit 9 of the Condition Code is not zero, execute the next
instruction.
=
RK Format - JUMP REGISTER POSITIVE
Test (Ra) and perform one of the following:
(1)
If (Ra) is equal to or greater than zero, load Y in P (jump to the
instruction located at the address specified by operand Y).
(2)
If (Ra) is less than zero, execute the next instruction.
R-19
.JP
RX Format - JUMP REGISTER POSITIVE
Test (Ra) and perform one of the following:
(1)
If (Ra) is equal to or greater than zero, load (Y) in P (jump to
the instruction located at address specified by the contents of
memory address Y).
(2)
If (Ra) is less than zero, execute the next instruction.
Operation Code 47
JNR
LJLS
JN
JN
RR Format - JUMP REGISTER NEGATIVE
Test (Ra) and perform one of the following:
(1)
If (Ra) is less than zero, load (Rm) in P (jump to the instruction
located at the address stored in Rm).
(2)
If (Ra) is equal to or greater than zero, execute the next instruction.
RI Format, Type 1 - LOCAL JUMP LESS THAN
Test the Condition Code and perform one of the following:
(1)
If bit 9 of the Condition Code is one, load Y in P (jump to the
instruction located at memory address Y). Y = (P)~.
(2)
If bit 9 of the Condition Code is not one, execute the next
instruction.
RK Format - JUMP REGISTER NEGATIVE
Test (Ra) and perform one of the following:
(1)
If (Ra) is less than zero, load Y in P Uump to the instruction
located at the address specified by operand Y).
(2)
If (Ra) is equal to or greater than zero, execute the next
instruction.
RX Format - JUMP REGISTER NEGATIVE
Test (Ra) and perform one of the following:
(1)
. (2)
If (Ra) is less than zero, load (Y) in P (jump to the instruction
located at address specified by the contents of memory address Y) .
If (Ra) is equal to or greater than zero, execute the next
instruction.
Operation Code 50 - Not assigned
Operation Code 51 - Not aSSigned
Operation Code 52 - Not assigned
B-20
Operation Code 53 - Not assigned
Operation Code 54
RR Format - LOAD ADDRESS REGISTER
Load the page address register specified by (Ra) with bits 15 and 5-0
of (R m). Only bits 0 through 5 of Ra are interpreted.
RI Format - LOAD ADDRESS REGISTER
Load the page address register specified by (Ra) with bits 15 and 5-0
of the contents of the memory address specified by (Rm). Only bits 0
through 5 of Ra are interpreted.
RK Format - Not assigned
RX Format - LOAD ADDRESS REGISTER MULTIPLE
Load bits 15 and 5-0 of the contents of sequential memory addresses beginning at Y, into sequential page address registers beginning at the
address word defined by (Ra) and continuing until the number of executions
equals the count defined by (R a ). Bits 0 through 5 of Ra designate the
word and bits 8 through 13 of Ra designate the count. A count of zero
causes all page registers to be loaded.
Operation Code 55
RR Format - STORE ADDRESS REGISTER
Store the page address register specified by (Ra) in Rm.
through 5 of Ra are interpreted.
Only bits 0
RI Format - STORE ADDRESS REGISTER
Store the page address register specified by (Ra) in the memory address
specified by (R m). Only bits 0 through 5 of Ra are interpreted.
RK Format - Not assigned
RX Format - STORE ADDRESS REGISTER MULTIPLE
Store sequential page address registers beginning at the address word
defined by (Ra) into sequential memory addresses beginning at Y and
continuing until the number of executions equals the count defined by
(R a ). Bits 0 through 5 of Ra designate the word and bits 8 through 13
designate .the count. A count of zero causes all page registers to be
stored.
Operation Code 56 - Not assigned
Operaticn Code 57 - Not assigned
B-2l
Operation Code 60 '
RL (00) Format - LOGICAL RIGHT SINGLE SHIFT
Shift (Ra) right n places with zero extended to fill.
in bits 0-3 of the instruction m-designator.
"n" is the value
RL (01) Format - ALGEBRAIC RIGHT SINGLE SHIFT
Shift (Ra) right n places with sign extended to fill.
in bits 0-3 of the instruction m-designator.
"n" is the value
RL (10) Format - LOGICAL RIGHT DOUBLE SHIFT
Shift the double length (Ra, Ra+l) right n places with zeros extended
to fill. "n" is the value in bits 0-3 of the instruction m-designator.
RL (11) Format - ALGEBRAIC RIGHT DOUBLE SHIFT
Shift the double length (Ra , Ra+l) right n places with sign extended to
fill. "n" is the value in bits 0-3 of the instruction m-designator.
Operation Code 61
RL (00) Format - ALGEBRAIC LEFT SINGLE SHIFT
Shift (Ra) left n places with zeros extended to fill.
value in bits 0-3 of the instruction m-designator.
"n" is the
RL (01) Format - CIRCULAR LEFT SINGLE SHIFT
Shift (Ra) left circular n places. "n" is the value in bits 0-3 of the
instruction m-designator.
RL (10) Format - ALGEBRAIC LEFT DOUBLE SHIFT
Shift the double length (Ra , Ra+l) left n places with zeros extended to
fill. "n" is the value in bits 0-3 of the instruction m-designator.
RL (11) Format - CIRCULAR LEFT DOUBLE SHIFT
Shift the double length (R a , Ra+l) left circular n places.
value in bits 0-3 of the instruction m-designator.
"n" is the
Operation Code 62
RL (00) Format - SUBTRACT
Subtract the 4-bit literal contained in the m-designator of the instruction from (Ra ), store the result in Ra , and set the Condition Code
(table XII!).
RL (01) Format - SUBTRACT DOUBLE
Subtract the 4-bit literal contained in the m-designator of the
instruction from the double length (R a , Ra+l)' store the result in
Ra , Ra+l' and set the Condition Code (table XIII).
"
RL (10) Format -ADD
Add the 4-bit literal contained in the m-designator of the instruction
to (R a ), store the result in R , and then set the Condition Code (table
XIII).
a
B-22
RL (11) Format - ADD DOUBLE
Add the 4-bit literal contained in the m-designator of the instruction
to the double length (R a • Ra+l)' store the result in Ha. Ra+l' and
then set the Condition Code (table XIII).
Operation Code 63
RL (00) Format - LOAD
Load the 4-bit literal contained in the m-designator of the instruction
into Ra and set the Condition Code.
RL (01) Format - COMPAHE
Arithmetically compare the 4-bit literal contained in the m-designator
of the instruction with (Ra) and set the Condition Code.
RL (10) Format - MULTIPLY
Multiply the 4-bit literal contained in the m-designator of the instruction by (Ra+l) and store the double length result in Ra. Ha+I; then set
the Condition Code (table XIII).
RL (11) Format - DIVIDE
Divide the double length (H • RD~l) by the 4-bit literal contained in
the m-designator of the ins~ruction. store the quotient in Ra+l and
the remainder in Ha; then set the Condition Code (table XIII).
Operation Code 64
RR Format - Not assigned
RI Format - Not assigned
RK Format - Not assigned
RX Format - BYTE SUBTRACT
Subtract the selected byte of memory address Y from (Ha ). store the
result in Ra. and set the Condition Code (table XIII).
Operation Code 65
RR Format - Not assigned
RI Format - Not assigned
RK Format - Not assigned
RX Format - BYTE ADD
Add the selected byte from memory address Y to (R a ). store the result
in Ra' and set the Condition Code (tnble XIII).
B-23
Operation Code 66·
RR Format - Not assigned
RI Format - Not assigned
RK Format - Not assigned
RX Format - BYTE COMPARE
Arithmetically compare (Ra) to the selected byte of memory address Y,
and set the Condition Code (table XIII).
Operation Code 67
RR Format - Reserved for user-designated macroinstructions.
RI Format - Not assigned
RK Format - Not assigned
RX Format - BYTE COMPARE AND INDEX BY 1
Arithmetically compare (Ra) to the selected byte of memory address Y,
set the Condition Code (table XIII), and increment (Rm) by 1.
Operati.on Code 70
® mACR,
RR Format - CHANNEL CONTROL (COMMAND OR CHAINING)
Perform the operation specified by the m-designator as specified in
table V on all I/O channels or the channel specified by the a-designator
as specified in table V. For chaining, the a-designator is not used.
RX Format - INITIATE TRANSFER (CHAINING)
Load the control memory Buffer Control Word (BCW) and Buffer Address
Pointer (BAP) locations with the contents of memory addresses Y and
Y+I respectively, and enable input or output transfers on the channel
c~rresponding to the chain executing the instruction.
Address Y must
be even. Chaining on the channel (input or output) is disabled until
.transfer termination. Transfer termination results when the buffer word
count decrements to zero. Chaining is re-enabled after transfer termination. The a-designator is interpreted as specified in table VI,
and is applicable for both parallel and serial transfers.
Operation Code 71
ICK or
OCK
RK Format - INITIATE CHAIN (COMMAND)
Initiate chaining for the channel specified by the a-designator. The
~m-designator specifies the chain:
m 2, input chain; m 6, output
chain. Load the corresponding Chain Pointer with the operand Y for
use as the starting address for the selected chain.
-----
See Table V
See Table VI
B-24
=
=
TABLE V.
ULTRA
Symbol
ACR
CCR
CHANNEL CONTROL INSTRUCTION m-DESIGNATOR
m
Value
Instruction
o
*Master clear all channels (deactivate all data buffers and
disable all external interrupt data and Class III interrupts).
1
Not assigned
2
Not assigned
3
Not assigned
4
*Set External Interrupt Enable (EIE) lines on all channels.
Accept external interrupt data on all channels. Store the
data at assigned memory addresses and clear EIE on affected
channel.
5
*Clear EIE on all channels. (Do not accept external interrupt
data from any channel.)
6
*Enable external interrupt monitors on all channels. Generate
the Class III, Priority 2 interrupt if any external interrupt
was accepted with monitors disabled. Enable generation of
Class III priority 2, 3, and 4 interrupts.
7
*Disable generating the Class III, Priority 2, 3, and 4
interrupts for all channels.
10
Master clear the channel specified by the a-designator.
11
Not assigned
12
Not assigned
13
Not assigned
14
Set EIE line for channel specified by the a-designator.
(Accept external interrupt data on the channel.) Store the
data at the assigned memory address and clear the EIE.
15
Clear EIE line for channel specified by the a-designator.
(Do not accept external interrupt data on the channel.)
16
Enable external interrupt monitor on the channel specified by
the a-designator. Generate the Class III, Priority 2 interrupt
if any external interrupt was accepted on the channel with
monitor disabled. Enable generation of Class III priority 2,
3, and 4 interrupts on the channel.
17
Disable generating the Class III, Priority 2, 3, and 4 interrupts for the channel specified by the a-designator .
•:' The a-designator must be zero.
B-25
TABLE VI.
INITIATE TRANSFER INSTRUCTION a-DESIGNATOR
a.
ULTRA
Symbol
Parallel or NTDS Serial
Transfer Mode
a-Value
0
Input data
1
Output data
2
External function
3
External function with force
10
Not assigned
4-17
b.
a-Value
xX
X 0
MIL-STD-l88 Serial
Function
Serial input without monitor
XXX1
Serial input with monitor
XX0 X
Generate-check odd parity
XX1 X
Generate-check even parity
X 0 XX
Disable parity
X 1 XX
Enable parity
o XXX
Serial input without suppress
1 XXX
Serial input with suppress
CD LCMK
RK Format - LOAD CONTROL MEMORY (CHAINING)
Load the control memory location specified by the m-designator as
specified in table VII with Y. The a-designator is not used.
LCM
RX Format - LOAD CONTROL MEMORY (COMMAND)
Load the control memory location specified by the m-designator as
specified in table VII with the contents of the memory address
specified by Y. The a-designator specifies the channel.
LCM
RX Format - LOAD CONTROL MEMORY (CHAINING)
, Load the control memory location specified by the m-designator as
specified in table VII with the contents of address Y. The
a-designator is not used.
(2)
B-26
See Table VII
TABLE VII.
LOAD, STORE, CONTROL MEMORY VARIABLES
a.
m-designator
m-Value
Location
o
1
TM, 0, B and Buffer Word Count (IN)
Buffer Address Pointer (IN)
2
Chain Address Pointer (IN)
3
Not assigned
4
TM, 0, B and Buffer Word Count (OUT)
5
Buffer Address Pointer (OUT)
6
Chain Address Pointer (OUT)
7
Not assigned
10
Monitor Register (MIL-STD-188 and RS-232 Serial)
11
Suppress Register (MIL-STD-188 and RS-232 Serial)
12
Serial Mode Information (MIL-STD-188 and RS-232
Serial)
13-17
Unassigned
b.
Serial Mode In.
Bit Locations
7
6
I5
4
0
3
2
1
I0 I
00
Character Size - 5 Bits
01
Character Size - 6 Bits
10
Character Size - 7 Bits
11
Character Size - 8 Bits
0
Odd Parity
1
Even Parity
0
Parity Disable
1
Parity Enable
One Stop Bit }
Asynchronous
Two Stop Bits
1
Asynchronous Clock Speed Select (00 Lowest - 11 Highest)
Not used
B-27
Operation Code 72
RCM
RX Format - STORE CONTROL MEMORY (COMMAND)
Store the contents of the control memory location specified by the
m-designator as specified in table VII at memory address Y. The
a-designator specifies the channel.
SCM
RX Format - STORE CONTROL MEMORY (CHAINING)
Store the contents of the control memory location specified by the
m-designator as specified in table VII at memory address Y. The
a-designator is not used.
Operation Code 73
RR Format - HALT/INTERRUPT (CHAINING)
Perform one of the following as specified by the a-designator; the
m-designator is not used:
HCR
(1)
If a = 0, halt the chaining action.
IPR
(2)
If a
= 1,
generate the Chain interrupt.
RX Format - SET/CLEAR FLAG (CHAINING)
Set or clear the most significant two bits (flag) of the memory
location specified by Y as specified by the a-designator; the mdesignator is not used.
SF
(1)
If a
= 1,
set flag.
ZF
(2)
If a
= 0,
clear flag.
Operation Code 74
HK Format - CONDITIONAL JUMP (CHAINING)
Jump to the address specified by the operand y if the condition
specified by table VIII is met. If none of the conditions are met,
execute the next instruction. After execution of this instruction
the Monitor Flag or Suppress Flag is cleared.
TABLE VIII.
a-Designator
,
B-28
CONDITIONAL JUMP INSTRUCTION a-DESIGNATOR
Jump Operation
0
Unconditional Jump
1
Jump if Suppress Flag Not Set
2
Jump if Monitor Flag Set
Operation Code 75
RR Format - SEARCH FOil SYNC SET SUPPRESS, SET MONITOR (CHAINING)
(1)
When bit 0 is set in the m-designator and the synchronous serial
interface is in use, at each bit time the input channel compares
the value of the last n bits of input data to the contents of
the suppress register (n is equal to the character length of
the channel). When a match occurs, the next character of n bits
is compared to the suppress register. If the next character
compare results in a match, the suppress designator is set and
the next instruction of the chain is enabled. If the next character compare does not result in a match, the suppress designator
is not set and the next instruction 0f the chain is enabled.
(2)
When bit 1 is set in the m-designator, input data matching the
character loaded into the suppress register shall not be transferred to memory. Occurrence of suppression shall cause the
suppress flag to be set.
(3)
When bit 2 is set in the m-designator and the interface is either
the synchronous or asynchronous MIL-STD-lSS or RS-232 serial
interface, the last n bits of input data are compared to the
monitor register. When a match occurs, the monitor flag is set
and that character is input as data. The buffer is then terminated and the chain is enabled.
When the m-designator equals zero, disable the search for sync
function on the channel.
(4)
Operation Code 76
RR Format - SET-CLEAR DISCRETES (COMMAND)
Set or clear the discretes associated with the MIL-STD-lSS or RS-232
serial interface as specified by the m-designator. The a-designator
specifies the channel. Discrete set-clear functions in the MIL-STD-lSS
interface are specified in table IX. Discrete set-clear functions in
the RS-232 interface are specified in table X.
RR Format - SET-CLEAR DISCRETES (CHAINING)
Set or clear the discretes associated with the MIL-STD-lSS or RS-232
serial interface as specified by the m-designator. The a-designator is
not used. Discrete set-clear functions are specified in table IX and
table X.
RX Format - STORE STATUS (COMMAND)
Store the data on the input data bus at the memory location specified
by operand Y. The data is interpreted as specified in table XI for the
MIL-STD-lSS serial interface and as shown in table XII for the RS-232
serial interface. The a-designator specifies the channel.
RX Format - STORE STATUS (CHAINING)
Shall store the data on the input data bus at the memory location specified by operand Y. The data is interpreted as shown in table XI for the
MIL-STD ISS serial interface and as specified in table XII for the RS232 serial interface. The a-designator is not used.
Operation Code 77 - Unassigned
B-2Q
TABLE IX.
m-Designator
Discrete
Function
Line Designator
1111
Set
Outbound Control Line 1
Al
1110
Clear
Outbound Control Line 1
Al
1101
Set
Outbound Control Line 2
Dl
1100
Clear
Outbound Control Line 2
Dl
1011
Set
Outbound Control Line 3
F1
1010
Clear
Outbound Control Line 3
F1
1001
Set
Outbound Control Line 4
Gl
1000
Clear
Outbound Control Line 4
Gl
0111
Set
Outbound Control Line 5
HI
0110
Clear
Outbound Control Line 5
HI
0101
Set
Outbound Control Line 6
J1
0100
Clear
Outbound Control Line 6
Jl
0011
Set
Not used
0010
Clear
Not used
0001
Clear
Internal Loop Test
0000
Set
Internal Loop Test
TABLE X.
m-Designator
"
B-30
MIL-STD-188 DISCRETE SET-CLEAR FUNCTIONS
RS-232 DISCRETE SET-CLEAR FUNCTION
Function
Discrete
1111
Set
Loop Test
1110
Clear
Loop Test
1101
Set
Data Terminal Ready
1100
Clear
Data Terminal Ready
1011
Set
New Sync
1010
Clear
New Sync
TABLE X.
RS-232 DISCRETE SET-CLEAH FUNCTION (CONT)
m-Designator
Function
Discrete
1001
Set
llequest to Send
1000
0111
0110
0101
0100
0011
0010
0001
0000
Clear
Set
Clear
Request to Send
Enable lUng Interrupt
Enable Ring Interrupt
Spare
Spare
Spare
Spare
Internal Loop Test
Internal Loop Test
Clear
Set
TABLE XI. STOlm STATUS BIT INTERPRETATION,
MIL-STD-188 SERIAL INTERFACE
Bit
Description
Function
0
Break
1
Overrun
2
Parity Error
3
E6 Active
The serial I/O did not detect a stop bit.
Used in asynchronous mode only.
The serial I/O did not transfer a data
word to memory before another I/O word
was received.
The serial I/O detected a parity error
on an input data word.
Control Line E6 was set active by an
external device.
TABLE XII. STORE STATUS BIT INTERPRETATION,
RS-232 SERIAL INTERFACE
Bit
Function
Description
The serial I/O did not detect a stop bit.
Used in asynchronous mode only.
0
Break
1
Overrun
,
The serial I/O did not transfer to memory
before another I/O word was received.
2
Parity error
The serial I/O detected a parity error on
an input data word.
3
Clear to
Send
Clear to Send was set active by an external
device.
'I:.
B-3l
TABLE XIII.
Instruction
CONDITION DESIGNATORS
Carry
Designator
Overflow
Designator
Condition
Code
(9)
(8)
Register
00 RR Diagnostic Return
RI Unassigned
RK Unassigned
RX Byte Load
NC
NC
NC
0
NC
NC
NC
NC
0
0
NC
NC
NC
X
01 RR Load
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
NC
NC
NC
X
X
NC
X
X
X
X
X
X
X
X
0
0
X
X
(R )
a
NC
NC
X
X
X
X
X
X
X
X
X
X
X
X
NC
(R )
a
(R )
a
(R )
a
(R )
a
RI Load
RK Load
RX Load
02 RR Unary-Arithmetic
m= 0 Make Positive
m= 1 Make Negative
m = 2 Round Ra
m = 3 Unassigned
m= 4 Twos Complement
Single
m = 5 Twos Complement
Double
m = 6 Ones Complement
Single
m= 7 Unassigned
m = 10 Increment (R )
a
m= 11 Decrement (R )
a
m = 12 Increment (R )
a
m = 13 Decrement (R )
a
m = 14 - 17
by 1
by 1
by 2
by 2
NC
NC:
no change in the designator
0:
end resul t is O.
X:
corttingent upon the designator function
for that instruction
NA:
not applicable
B-32
X
NC
NC
NC
X
X
X
NC
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R a , Ra +l )
TABLE XIII.
Instruction
IU-2 Load
RK Unassigned
RX Load Double
CONDITION DESIGNATORS (CONT)
Condition
Code
(8)
(9)
Carry
Designator
Overflow
Designator
0
NC
X
NC
X
X
NC
(R a • Ra +l )
0
0
NC
X
X
(R a • Ra +l )
X
NC
X
NC
r~c
I~C
NC
NC
Register
03 RR Unary-Control
m = 0-3
m = 4 - 17
0
0
NC
I~C
RI Unassigned
RK unassigned
RX Load Multiple
NC
NC
NC
r~c
NC
I~C
NC
NC
m = 0 Unassigned
m = 1 Reverse
Register
Nt:
0
I~C
I~C
NC
0
X
X
m = 2 Count Ones
m = 3 Scale Factor
NC
NC
NC
I~C
NC
NC
NC
r~c
m = 4 - 17
NC
NC
NC
NC
RI Unassigned
NC
NC
NC
RK Unassigned
NC
NC
NC
NC
RX Byte Load & Index by 1
0
0
0
X
0
0
X
X
RI Load & Index by 1
0
0
X
RK Unassigned
RX Load and In1ex by 1
NC
NC
NC
X
NC
0
0
X
X
0
0
X
0
0
X
X
X
NC
l~C
NC
NC
0
0
X
X
0
NC
0
NC
X
NC
X
NC
NC
I~C
NC
NC
NC
NC
(R )
a
04 RR Unary-Shift
05 RR Set Bit
06 RR Clear Bit
RI Load Double & Index by 2
RK Unassigned
RX Load Double & Index by 2
07 RR Compare Bit
RI Load PSW
RK Unassigned
RX Load PSW
NC
NC
(Ra)
NC
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R a • Ra+l )
(R a • Ra+ 1)
(R )
a
B-33
TABLE XIII.
Instruction
10 RR Logical Right Single
Shift
RI Unassigned
RK Logical Right Single
Shift
RX Byte Store
11 RR Algebraic Right Single
Shift
RI Store
RK Algebraic Right Single
Shift
RX Store
12 RR Logical Right Double
Shift
RI Store Double
RK Logical Right Double
Shift
RX Store Double
13 RR Algebraic Right Double
Shift
RI Unassigned
RK Algebraic Right Double
Shift
RX Store Multiple
14 RR
RI
RK
RX
Algebraic Left Single Shift
Unassigned
Algebraic Left Single Shift
Byte Store & Index by 1
15 RR Circular Left Single Shift
RI Store & Index by 1
RK Ci~cular Left Single Shift
RX Store & Index by 1
B-34
CONDITION DESIGNATORS (CONT)
Condition
Code
(9)
(8)
Carry
Designator
Overflow
Designator
0
0
X
X
NC
NC
0
0
NC
X
NC
X
NC
NC
NC
NC
0
0
X
X
(R )
a
NC
NC
0
0
NC
X
NC
X
(R )
a
NC
NC
NC
NC
0
0
X
X
NC
NC
0
0
NC
X
NC
X
NC
NC
NC
NC
0
0
X
X
NC
NC
NC
0
0
NC
X
NC
NC
NC
NC
0
X
NC
X
X
NC
(Ra)
0
X
NC
X
(R )
a
NC
NC
NC
X
NC
0
NC
0
NC
X
NC
X
NC
(R )
a
0
0
NC
X
NC
(Ra)
NC
X
NC
NC
X
Register
(R )
a
(R )
a
(R a ,Ra+1)
(Ra ,Ra+1)
(R a ,Ra+1)
(R a , Ra +l )
TABLE XIII.
Instruction
CONDITION DESIGNATORS (CONT)
Carry
Designator
Overflow
Designator
Condition
Code
(9)
(8)
l{eg i s ter
16 RR Algebraic Left Double Shift
RI Store Double & Index by 2
0
X
X
X
NC
NC
NC
j~C
ilK Algebraic Left Double Shift
RX Store Double & Index by 2
0
X
X
X
NC
NC
NC
j~C
0
0
X
NC
NC
X
NC
0
NC
0
NC
X
NC
X
NC
20 RR Subtract
X
X
X
X
RI Subtract
X
X
X
X
RK Subtract
X
X
X
X
RX Subtract
X
X
X
X
1m Subtract Double
X
X
X
X
RI Subtract Double
X
X
X
X
RK Unassigned
NC
NC
I~C
NC
RX Subtract Double
X
X
X
X
22 RR Add
X
X
X
X
RI Add
X
X
X
X
RK Add
X
X
X
X
RX Add
X
X
X
X
23 RR Add Double
X
X
X
X
RI Add Double
X
X
X
X
RK Unassigned
NC
NC
NC
NC
RX Add Double
X
X
X
X
24 RR Compare
X
X
X
X
(R a , Ra+1)
Result
RI Compare
X
X
X
X
I~esult
RK Compare
X
X
X
X
Result
Compare
X
X
X
X
Result
25 RR Compare Double
X
X
X
X
Result
RI Compare Double
X
X
X
X
Result
17 RR Circular Left Double Shift
RI Store Zeros
ilK Circular Left Double Shift
RX Store Zeros
21
R~
(Il ,
l{a+l)
a
(Il , I l
a
(Il
a
a+ 1)
Ra+ 1)
f
NC
(R a , Ill)
a+
(R )
a
(R )
a
(R )
a
(ll )
a
(R , R 1)
a
a+
(R , Ra +l )
a
(R a , Ra+ 1)
(R )
a
(R )
a
(Il )
a
(R )
a
(R , R 1)
a
a+
(R , R 1)
a
a+
B-3:1
TABLE XIII.
Instruction
RK Unassigned
RX Compare Double
CONDITION DESIGNATORS (CONT)
Carry
Designator
Overflow
Designator
Condition
Code
(9)
(8)
NC
X
NC
X
NC
X
NC
0
X
X
X
X
X
X
X
X
Register
Result
(R ,
a
(R ,
a
(R ,
a
(R ,
a
26 RR
RI
RK
RX
Multiply
Multiply
Multiply
Multiply
0
0
0
0
0
0
0
27 RR
RI
RK
RX
Divide
Divide
Divide
Divide
0
0
0
0
X
X
X
X
X
X
X
X
X
X
30 RR
HI
RK
RX
31 RR
RI
RK
RX
AND
AND
AND
AND
OR
OR
OR
OR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32 RR
RI
RK
RX
Exclusive
Exclusive
Exclusive
Exclusive
X
X
X
X
X
X
X
X
33 RR
RI
RK
RX
Masked
Masked
Masked
Masked
X
X
X
X
X
X
X
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(R )
a
(Ra)
(Ra)
34 RR
RI
RK
RX
Compare
Compere
Compare
Compare
X
X
X
Result
Result
Result
X
Result
B-36
OR
OR
OR
0
0
0
0
0
OR
0
0
Substitute
Substitute
Substitute
Substitute
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
0
0
X
Masked
Masked
Masked
Masked
0
,
X
X
X
Ra+ 1)
Ra +l )
Ra +l )
Ra +l )
(Ra+l )
(R a+l )
(R a+l )
(R a+l )
TABLE XIII.
Instruction
CONDITION DESIGNATORS (CONT)
Condition
Code
(8 )
(9)
Carry
Designator
Overflow
Designator
NC
0
NC
0
NC
X
HC
X
NC
NC
NC
l~C
35 RR
RI
RK
RX
I/O Command
Biased Fetch
Execute Remote
Biased Fetch
NC
0
NC
0
36 HR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
NC
NC
NC
NC
NC
HC
l~C
NC
NC
NC
l~C
37 Unassigned
NC
j~C
I~C
NC
40 - 47
l~C
NC
l~C
NC
NC
l~C
J~C
l~C
X
NC
X
Unassigned
Unassigned
Unassigned
Unassigned
NC
NC
NC
J~C
I~C
l~C
I~C
NC
NC
~C
J~C
l~C
I~C
51 RR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
NC
NC
NC
NC
NC
NC
NC
NC
[~C
NC
NC
NC
NC
NC
NC
NC
52 RR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
NC
NC
NC
NC
J~C
I~C
NC
NC
NC
J~C
53 RR
RI
RK
RK
Unassigned
unassigned
Unassigned
Unassigned
NC
NC
NC
NC
NC
NC
NC
NC
54 RR
RI
RK
RX
Load Address Register
Load Addrf'ss Register
Unassigned
Load Address Register
Multiple
NC
NC
NC
NC
NC
NC
NC
NC
l~C
l~C
NC
55 RR
RI
RK
RX
,
Store Address Register
Store Address Register
Unassigned
Store Address Register
NC
NC
NC
NC
NC
NC
NC
j~C
[~C
56 RR
RI
RK
RX
Unassigned
Unassigned
Unassigned
Unassigned
NC
NC
NC
NC
[~C
NC
NC
NC
[~C
NC
l~C
(y)
(y)
l~C
50 RR
RI
RK
RX
NC
NC
Register
NC
NC
NC
J~C
NC
NC
NC
NC
l~C
[~C
I~C
I~C
J~C
I~C
NC
NC
I~C
NC
I~C
l~C
NC
NC
l~C
NC
NC
NC
J~C
l~C
I~C
8-37
TABLE XIII.
CONDITION DESIGNATORS (CONT)
Condition
Code
(9)
(8)
Carry
Designator
Overflow
Designator
57 RR Unassigned
RI Unassigned
RK Unassignpd
RX Unassigned
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
60 RL-l
Logical Right
Single-Shift
0
0
X
X
(R )
a
RL-l
Algebraic Right
Single-Shift
0
0
X
X
(R )
a
RL-3
Logical Right
Double-Shift
0
0
X
X
(R a " Ra+l )
0
0
X
X
(R a
Algebraic Left
Single-Shift
0
X
X
X
(R )
a
Circular Left
Single-Shift
0
0
X
X
(R )
a
RL-3 Algebraic Left
Double-Shift
0
X
X
X
(Ra
I
Ra+l )
RL-4
Circular Left
Double-Shift
0
0
X
X
(Ra
I
Ra+1)
Subtract
X
X
X
X
RL-2
Subtrrct Double
X
X
X
X
RL-3
Add
X
X
X
X
RL-4
Add Double
X
X
X
X
Load
0
0
0
X
RL-2
Compare
X
X
X
X
RL-3
MultiIJly
0
0
X
X
(R
RL-4
DivJde
0
X
X
X
(Ra+l )
Instruction
RL-4 Algebraic Right
Double-Shift
61 RL-l
RL-2
62 RL-l
63 RL-l
B-38
Register
I
Ra+l )
(R )
a
(R a
I
Ra+l )
(R )
a
(Ra
Ra+1 )
(R )
a
(R )
a
I
a ,Ra+1 )
TABLE XIII.
Carry
Designator
Overflow
Designator
Unassigned
Unassigned
Unassigned
Byte Subtract
NC
NC
NC
X
NC
NC
NC
X
Unassigned
Unassigned
Unassigned
Byte Add
NC
NC
NC
X
Unassigned
unassigned
Unassigned
Byte Compare and Index
by 1
NC
NC
NC
X
Instruction
64 RR
RI
RK
RX
65 RR
RI
HK
RX
66 RR
RI
RK
RX
67 RH
RI
RX
RX
70 - 77
CONDITION DESIGNATOHS (CONT)
I{eserved
Unassigned
Unassigned
Byte Compare and Index
by 1
As required
NC
NC
X
NA
Condition
Code
(9)
(8 )
NC
NC
NC
NC
l~C
l~C
X
X
NC
NC
l~C
l~C
J~C
l~C
l~C
X
X
NC
NC
X
l~C
NC
NC
NC
X
NC
NC
X
As required As required
NC
NC
Register
(R )
a
(I{ )
a
NC
I~C
NC
X
Result
l~C
I~C
[~C
X
X
NC
X
NA
NA
NA
Result
.
B-39/(B-40 blank)
APPENDIX C
MICROPROGRAM LISTING
The microprogram, contained in the ROM, provides internal control for the DPS and
provides the microinstruction sequences for execution of each macroinstruction.
Most subroutines are preceded by a title or macroinstruction function code. See the
operational description near the end of Chapter 3 for an introduction to microprogram operation.
('-1
I
I
.
n ------- n
~
'"'I
___
:>
:)
-,,-
'I.
---5.
6.
______ 7.
-- ---- - ----000000- ------ ~----SO -- -----EQU
0
000000
00
EQU
0
-----------000001BRKPT-~~--£QU
1
8.
000002
PREG
EQU
2
_ 9.
3
- - - - - - CUl0003 ----- _____ --1l0R ____ ~EQU
10.
OOCOO'l
PTSLS
EQU
'I
--H.
----COC(UO
P-litLD----EQU - -010
12.
000006
5M
EQU
6
----------~000007-Pf'ROD - --- EQU
7
---~!:-000007
MONCLK
EQU
7
- - - IS.
- - -----0000(;0
UP-- -----EQU
0
16.
000001
CREG
EQU
1
--170---- - - o ClCH10 2OR£G--~-- EQU 2
18.
000003
eM
EQU
3
---190000003--SHIF'-TS---~ EQU~-3
20.
000003
NORM
EQU
3
---210- ---- ------- ---~00001l'l RH-\J--~~-EQU
'I
22.
0000C5
5TATI
EQU
5
--_2-J-o ---- ~~---------_Goeo~1>----STAT2---EQU
it
2'1.
000007
RTCL
EQU
7
--_27--.28.
n
o
o
o
()
---~OOOO_l_'I
00001'1
30.
------.13....
1 &---32.
---».
--~~~g~~~----------~~:~~L-- --~~~
________
----~0,OOOC5--
_ ___42.--"9.------
()
PAGE
-------~-~--------
J ---~:: - ----~~-~
o
_OATE 10157J
TPfS,MUYK20/BA5ICAPE_ _
___ ~ _____ _
GPA ASSEMBLEO BY V-ION 15 OCT 73 AT
20:07:15
_ ______ ____ _ _ _ _ _ _ _
e-tJLTRA
_AP_E
PR8S
CYCLE 01
_1.
2.
3.
o :>
MINI-UYK-20 lAPEl
__ "fGPA.c..PA8.5
o
o
---~---------~--------~----------------
000015
-
------~"h1_
000012
-~--~---~oaOI2
3'1.
000017
--350-------lJ-O~OOCJ_l_6_
36.
000016
--_31-0-------400000IH~-'I-38.
000016
---19-. - ------~-----
CtOCHH-'
000003
'10.
- - - ' I I-.-~- ---------GOOClGl_3
'12.
000010
- -g:~
HI-TC-O~QU--- (; 1'1
XLTRM
EQU
01~
IDP
£QU ______ 5
XLTR
EQU
015
IRS
EQU--~ll
IRD
EQU
G12
..... 1t _ _ ~£Qu __ -1112
10CMR
EQU
017
IDIC
~QU---016
ODR
EQU
016
RCiiiC-----EQU
~
5HIFTO
EQU
016
HAR
£QU- -G17
CK
EQU
3
5GR
-~EQU ---- 013
PAC
EQU
010
NON-EXISTANT
NON-Ex ISTANT
aREAKPOINT REGiSTER
01151
01151
P REGiSTER
MEMORy DATA REGISTER
01151
PAGE TAilLE
51
pAGE TABLE
D2
ShIFT MATRIx OUTPUT
51
pA.HIAL PRODUCT
51
MONITOR CLOCK
51
MICRO P
02/52
cONOITION REGISTER
02/52
D2/S2 ol~PLAY RE,"ISTER
CONSOLE MODE
52
52
shifT COUNTER
52
NORMALIZE
52 RTC UppER
01/52
sTAT I
sTA T 2
01152
01152 RTC LOAER·
GENERAL REGISTER STACK
52
COkOIC TABLE
52
INTERRUPT-CoDES
52
TRANSLATOR-M.
02
-5 ,
INOIRECT PoINTER-I/O _XLAIOR
I/O TRANSL.ATOR
02lS2
INSTRUcTION REGIstER
52
INSTRuCTION REGISTER
02
1.R. A AND M FIELDS - SIGN EXTED
52
1/0 CONTROL MEMORY REGISTER
02/S2
INPuT DATA
52
OIJTPUT OATA
02
GENERAL REGISTER STACK
01
SHIFT COUNTER
01
MEMORy AoORESS REGISTER
01
cYCLE COUNT
02
5 GENERAL REGISTER
02
PAGE ADDRESS COUNTER
01
• 51
• 0I
•
o
•
•
o
,
o
o
•
o
----'13-. - - - - - - -
'1'1.
--------'15.
'16.'
--- -----------------
00
000000
-,__________ --~-
1'1 17 00'1
BMJS 000'1
T
1.7 .CM, 1
'18.
000002 01 0017
J
HCSUBQ
-- '1-9.. - _____ ~ ------CUlQOO 3--1!>-16 DO--O 3-JotC- - - 0 16.0.3
so.
00000'1 01 7771
J
07771
---5lo-----~---------000005--12 -IO-OOC
TeL AO.O
52.
000C06 01 6000
J
06~UO
53,___
-_0000Q7~--oit 11 1 0 0 3 - - - - - - - - - - - - - - 1 . 1
Al,AO.3
5'1.
000010 01 7765
J
0 7 765
-5S.---CUlOQ11---0Q-11-QO~OI
T --AI.UP.l
--~'---------DetHHl_l---tUl-__l1_0~&1
o JP TO OIAG PROG If DIAG JP S~lTCH IS uP
• CONSOLE MODE TO A7
o JUMP TO MASTER CLEAR SlQ
• DISABLE MONITOR CLUCK
o JUMP TO ADOREsS 7771
• TRANSfER ZEROS TO AD
• JUMP TO ADDRESS 6000
o lAOj c u77777,
1'5 CaMP Of AO TO AI'
o LOAD MICRU HOLD REG ~ITH 0011
• MICRO P HOLD TO Al
.
------
..
_-----------_._------DATE 101573
56.
oaoci2 01 7713
01773
J
57.
000013
13 13 017
SGR,Ol7
Te2
58.
- - - - ---_.- ---59.
SETADR 1117
60.
--------------_... _.- . __ ._-_._61.
• HASTER CLEAR SUBROUTINE
-62. - .. -- .---.-----•
--- _____ .___ . ___ ..
63.
000017
12 10 000
MeSUBO
Tel
PAC.O
6 .. ·---------000020--13 -tl3-077TC2- CIC ,1l77
65.
000021
16 10 001
RN
I
66.
---GOOC22 00 10 Hi 02-------~-~----f_--PTbLD.PAC.2
67.
000023
10 10 Ovl
AC
AO.I
.8.____
--00002" --J-5-14---tlCi--06MC----- Oh.0.6
69.
000025
12 II 020
TCI
AI.020
.
o
o
o
o
o
~
__
----~~:
--- ---~:~~~~- . : !~~- ~~~----
-
HCSUB
-----1720------ - ---000030---13--03---0-11-73.
000031
J6 .10 002
- - - 1 ... ---·--------000032--Q2--Ift-15-03
75.
000033
IS IS 02 00
---:~:-~.
lC2--CIC. IS
2
AS2--A5 •. XLTR,l
MC
015.2,0
-- . --g:gg~;-d~~-1~~~;02-
~C2
o
_--.
_._-_ .. .~------~---
--._-
SETADR 0"0
--------.----
83.
o
85.
-~6.
-_..
AD. IRS. I
---8'''--~--- --------------------..--,.~e.n't--RR--UNARY-SH
o
CLR PAGE ADDRESS COUNTER
REPEAT CT
REPEAT NEXT 2 INST
PA~E ADDRESS VALUE TO PAGE TA8LE
INC PAGE TABLE VALUE
CLR 1/0 DATA/OISAaLE RTe
• REPEAT NEXT 3 INST
• A1 + TRANSLATOR TO AS
• CHANNEL CONTROL
;~~:;AS.2
J--LA8
81.
--~82.
•
•
•
•
•
•
ig - !~~~~O
o ___ !~:----------o0000-3-7--G-O-I-C-I-3-0-1--------.------To
• JUMP TO DIAG HETURN ROUTINE
• SETUP SG" FOR DIAG RETURN ROUTINE
RN
----78. ----- ----OOOG3t.--0IuUZ3-
1fT
•
--- -
87.
0000 .. 0 01 0265
:::un----------G~GC .. l___GC~~
EMfl
H11- UNASSI(lNED
J
EMIIL
• HI6 N~~~-SS-IGN~Dn- ---
--. ----~-
----9.0.--.----GOOOU----Ol-02b6-:o5---.----------;.
J
o
o
o
---
--
MINI-UYK-20 lAPEl
OATE 101573
______.___________________________ •. _116
Ill,
UNASSI(,NEO
I 1'1.
000062
01 026S
oJ
EHIIL.
I IS,
_ ______ NOOP
._.000063 DO_CO 00.00_
116,
• H5
UNASSIGNEO
_117,
_ _ _ _ _ _ _ _ OJ
_EHllL.
___ 0(;006'1 01 _0265
118,
00,1(165
NOOP
00 00 00 00
_ _ _ _ _ _ _ _ .__-*-H/f __ UNASS I CaNEO
119.
120.
000066 01 0265
oJ
EHIIL.
121.
000067 - 000000-00.·
NOOP _. •
122.
• H3
SCAL.E FACTOR
__ .123.
- OuOC70 01 1126 --- - - - -oJ--LI'7
12/f.
HC
7,0,0
000071
IS 07 DC 00
• A'I TO SGR
_ _ _ _ _ _ _ _ _ _ _ _ _ _ ___+_. K2_-COUN TONES
12S,126.
oJ
LJQ
000072 (;1 210"
-.-127.
OCOC7l -l3 Ol 011--- _ _ _ _ .________ 1.C2 CK ,IS
128.
• HI
REVERSE REGISTER
_ _ .-129.
_ _ _ _ _ _ _ _ _ -...1 __ .1.1 ..
_ 00007/f -01-2261--130,
Ca007S
IJ OJ 017
TC2
eK,15
--131.
____ ---------------------<.o---1KO--SQUARE ROO T
132.
000076 01 026S
oJ
EHIIL.
.____
.
_._13l ,--------------OQ.ilO 77_00_G.0-1lQ-'l0-NOJJP_____.
13'"
~J5_'-. _________________~---------------">S!.TAO-R-_.O'I 00 __
136.
_ _..1.1.,.,37.
138.
UNARY-ARITHMETIC
• F'C-02 RR
o ___
.....
.J
o
~t
~
o
o
.__._t _ _ _
~_~
________________._ .__ " __
• START
• AD - I TO RGR
ISSI
()
.•
o
0-
• START
I IO.RGR ISS)
AD.'
• START
• 1'5 COMp OF AD TO HGR 1551
J
"
..1
_.
MINI-UYK-ZO (APEI
a
0
170.
171.
I7Z.
17l.
___ 17'"
17S.
176.
177.
178.
179.
J
0
180~
181.
~) __. _18Z.
18l.
18" •
US.
C>
___ 186.
187.
-.-~
C>
a
D
_ _ 188 •._
189.
____ 190.
191.
____ UZ_._
I9l.
_ _ 19"~_
195.
o --- ::~:
_ _ 198! __ ._
19'.
_200.
ZOI.
___ ZOZ.
ZOl.
__ -ZO",
ZOs.
~Jl6.
Z07.
_ _ 208L
Z09.
___ 210.
a _.
a
o
o
Z1I.
a __ 2.12.
Zll·
_ _ 21"_-, __
215.
_ _ 216' _
ZI7.
)
o __
ZI"
_ _ 220'
a '2ZI.
22Z.
21~.
22l.
ct
22 ...
n
2Z5.
(" ___2.2 6 .• _
I
i~
DATE 10lS1l
I
________ . _______ ,-.1'15
000 I Z..
COOIZS
000 116
COOIZ7
OOOllO
_000131
00013Z
000113
-
00013'1
_toO IlS
000116
000 I J7
.COMPLEMENT,UOUBLE
LEI
I'IC
_7.ll.0
T~OS COMPLEMENT,SINGLE
__. __ LG3 • M.. _E
_I LOoOo I ..
O.Il,OI ..
SU
RGf(D.AO,OI'l
OS 0" 10 1'1
_ _ _ _ _ _ _ _ '-113 UNASSIGNED
01 OZ6S
.,j
EMIIL
00 __ 00 .110 _00 _____________________ NOOP ..
• 1'12 ROUND RA
01 _I"ZS_
oJ
LID
IS -07 00 DO
I'IC
7.u.0
---.-- - - - . - - - - - - - - - - -_ _ _ --0- l't 1
I'IAKE NEGATIVE
.,j
01 OilS
LG'I
._8N
LGS
-- ---- .._- _.. ---I" _00 315 _
HO MAKE POSITIVE
•
LGS
01 _OlIS_ ---------oJ
LGl
IN
I" DC 126
0 I I III
15_0700_00_
T~OS
.,j
-
• ..lUMP
• A+I To SGR
• START
• a - AO TO RGR (SSI
• RA+I TO SGR
• GO COMPLIMENT
• DONE IF RA IS NEG
• DONE IF RA IS POS
.. e ____ .
• FC-03 RR - UNARY-CONTROL
._---.......... -_.- -- - --
• 1'117 DISABLE RTC LO~ER OVERFLO~ INTERRuPT
__ E
0,0,01'1
• START
Me
016,0.1
• DISABLE RTc INTERRUPT
.- _______ ._. __·_______ ~_.MU ENABLE .Hc LO~ER OVERFLO' INTERRUPt
0001'12 17 '00 00 1'1
LJl
E
0,0.01'1
START
0001'11. 15 __ .16 _oo_OZ _________________ l'tC0I6.0,2
• ENABLE RTC INTERRUPT
• HIS STORE RTC UPPER AND LO~lR
_ _______
.1 __ __ LC 1
,
... ____11001'1'1.__ 0L.1U1_______
T
RGHD,RTCU,I
• RTC UPPER TO RA
0001'15 000'1 0'1 01
---o __ .MI'I __ LOAD RTC UppER AND LO~ER
- ------- - - - - - - - .,j
LCZ
0001'16 01 1122
_____ T_____ RTCu,AO.2
_00tl'17 ~oa_0"_lQ_02_
• RA TO Rye UPPER
• I'Ill DISABLE INTERRUPT CLOCK
___ 000 ISO .17 _1111.Jl0_1'L ______________ E _____ 0,0.01'1
• START
• DISABLE INTERRUPT cLOCK
000151
IS 16 0003
MC
016.0,3
____ .__________________________L_K12 _LOAD ANIJ ENABLE INTEHRUPT CLOCK
000152 01 1115
.I
LC'I
___ 000I.S3 __0D_1ULIO_01L
_ _ _ L__ DO ,AO.O
• HII DISABLE RTC
.1 _
_EMU
-GO 0 15'1- 0 Ln.l'UL - --- - - - - - _ _ _ _ _....
MC
016,0.6
OOolSS IS 16 00 06
• DISABLE RTC COUNT
---------~.~KI0 ENABLE kTc
000156 01 OI'lZ
.,j
LJ3
__ ..110015 7_1S_16_QIL.Jl:o.S_ _ _ _ _ _ _ _ _ _ _ftC ____ 016.0,5
• ENABLE RTC COUNT
• M7 LOAD RTc (LO~ERI
000160 __ ILI10 DO_I'I __________ --- ____ E
0.0,01'1
• .START
• RA TO RTC LO~ER
000161 00 07 10 00
T
RTcL,AD,O
_____ L_!t'_ LOAP sTATus REGISTER Z
000162 17 DO 00 1'1
E
0,0,01'1
• START
000163 _._00 _06 10 -00 _ _ ______________ T_
_STATZ, AO ,0
• RA TO STATUS REG 2
."5 LOAD STATus REGISTER
_ _ _ _ _ _oJ_
LJ'I
COOl6'1 01 0262_ - - --- • RA TO STATUS REG I
000165 00 as 10 00
T
STATI.AO,O
______________________ L-K'I. ___ LOAD P
00016' 01 1267
J
LAIJ
....._____ 000161_1111_02_ 10 --DC L-__ I'REG. AD, 0
• RA_TO P-REGlSTER
-- 0001110
OeOl'l1
17_00 -DO _1'1 ------_____ EMAZ
IS 16 00 01
PAGE
HINI-UY~-20
)
J
__ 22 7.
228.
229.
230.
231.
232.
233.
23'io
235.
236.
237!
238.
___239. __
2'10.
IAPE)
,
---2'15.
o
2'16.
--2'17.
2'18.
J
J
J
'"'
O
STORE RTC ILO~EH'
0.0.01'1
• START
_T
RGRD.RTCL.I
• RTC LO~ER TO RA
o M2
STORE STATUS REGISTlK 2
_E
O.O.Olq
• START
T
RGRD.STAT2.1
• STATUS REG 2 TO RA
--------- • HI _STORE STATUS REGISTlk
E
0.0.01'1
• START
____________________1 ___ RGKD .STAT I. I
• STATUS REG I TO HA
o HO
ExECUTivE RETURN
________________ J _
LF"9
T
AO.STAnd
• GET STAll
17_0000 Iq
00 0'1 06 01
01 _2266
00100501
E
sETADR 0200
------------ - - - - - - - - - - -
-------,,---lNtERRueT TABLE
------- -- - - - - - - - - - - - - - - - - - - - - e _ _ R E TURN
HC
0.0.0
000200
15 00 oc 00
- ---00020 1--00 00--15- 02 - - - - - - - - - - - - l - - U P . A 5 . 2
000202
00 16 16 00
T
A6.A6.0
-- -000203 - 000000 ---0 --
• CLEAR RETURN
• INTERKUPT CODE TO MICRO-P
• A6 TO A6
250.
---251.--
----------------------SETADR-020q
•
252.
-----2.53.
25'1.
---- -- - - - - - - - - - - - - - - - -
--255.
. 256.
-----2.57 • -__ _
258.
0-------_ _ _ _ _ _ _ _ _ _ _
• BOOTSTRAP LOAD
S~ITCH
272.
--273.
27'1.
• CLEAR CLASS I1II
INTS
.
• SETUP BOOT:TRAP LOAD ADDRESS
--
• CLR INT ANa CHAIN REQ
• TO CONTINUATION Of SEQ
• MASK fOR SET/CLR FLAG INST (73RXI
•
- - - - - - - - - - - - - - - - - - - - - - - - - - . - - f I V N I BAR I
00021'1
00 10 03 01
----2-15. -- --------- oao 2 ,5--- -12--H--G-l--1---000216
01 2153
27 6 •
---- ---~00217---07-J 1-10- 06-- - --- 217.
278.
RUNBAR
T
Tel
AD,CM,I
J
LFI
Al,AO,6
------------~2
A I. Ii 17
• CO~SOLE MODE TO AO 1551
• 17 TO AI
• GO TO Co~TI~UATIO~ Of CO~SOLE MaCE
----SETADR 022C
-- ---279..
o _
fUNCTION
00020'1
15 16 00 C7
HC
016.0.7
£.I1AlA
---00C20S -(JJ--03.2-'I---- - - - - - _ _ _.v.J
TCI
PR~G.2
000206
12 02 002
_ _ _ _ _ _ _ _ _ _ _...D ________ _
- - --..........(We 20 z--------nil0 O[ltL-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~SETAOR_ 0210
-----2. 6 1. _
262.
-----2.63.---• CHAIN INST READ
26'1.
-----2.65. ------- - - -000210
15 15 00 0'1
HC
015.0.q
2660
--- ---tl0021l--01--1-4-J-1 - - - - - - - 4------LHO
---267.
268.
000212
12 10 300
TCI
AO~0300
--26'iJ.-- ------~OC213__--00nOoo-----------------10--------------270.
S-ETAOR e21"
-----2 7 1-.
J
o
000172
OeOl73
___OOC 176
000177
J ~:~:--J
17 00 00 1'1
00 0'1 07 -01
00017'1
17 00 00 1'1
_Oe017S _00_0'105_01
---2'19.---
:)
000170
000171
____ 2'13.
2'1'1.
J
PAGE
o-H3
-
:>
DATE 101573
2aO.
28la
282.
283. _
C00220
_~00221
- - - - - - - - - . CLASS I OR II
T
AD,INTCOD,OII
00 10 I q 1 I
00-10 lC-Oq----- - - - - - - _ _ t... __ AO.AO,q
• INT CODE
• RoTATE
~D
TO AO (55)
5
c
- - - - --28'1.
285.
286.
287.
28B.
289.
290.
291.
292.
293.
29'1.
295.
296.
297.
29B.
299.
300.
30 10
302.
303.
---30'1·
305.
306.
307.
-30B.
309.
310.
J I I •
- - J I 2 . --313.
---~I'I·
J
,
o
-J
I
3 IS.
----.l16.
317.
- - -316.
319.
_ _ -320.
321·
___ 3Z2.
323.
___ J2'h
325.
___ 326.
327.
_ _ _321!.'_
329.
_330.
331.
332.
333.
33'1._
335.
336.
337.
338.
J39.
__
3'10.
000222
000223
00022'1
000225
OCi0226
000227
12
1'1
07
10
01
12
12 006
237
12 Ie 06
12 010
1565
- -------lH217 120
oe
--------~------
DATE
------
.
TCI
8N
L2
A2,6
Ltil
AZ,AO,6
Ae
A2,Ol0
oJ
-c I SB
Tel
A7.0120
PAGE
•
•
•
•
•
•
MASK fOR INT CODE
JP If CLASS I
CODE alTS TO A2
ADO CLASS I BIT 10
TO COMMON INTERRUPT SE~
CLASS II MAIN MEMORY LOCATION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CLR INT AND CHAIN REQ
MASK
INT CODE ~D TO A2 ~/ROTATE
SAVE liD INT ~ODE PORTION ONLY
CLR INT
TO COMMON INT SEQ
CLASS .ILI MAIN MEMORY LOCATION
MASK
MEMORy BITS TO AO
STATZ To A6
CLR MEMORY BITS
INSERT MEMORY BITS
CHEC~ fOR CLASS I PO'ER fAULT CODE
JP If NOT PnR INT
LOAD STATZ
TO COMMON INTERRUPT SE~
-~---
SEHOR 0230
• eL"SS III
000230
15 IS Co O ' l - - - - - - - - - - - - J i e
CiI5,O,'1
000231
12 10 377
Tel
AO,0377
000232
CO 1215 0 5 - - - - - - - - - - - - 1 "Z,XLTR,5
000233
07-12 10 06
L2
A2,AO,6
-00023'115 IS CO 02
- - - - - - ----KC--- 015,0,2
000235
01 1566
J
(lse
000236 -12 17 110--leI-A7.0110
000237
12 13 160
LHI
Tel
,,3,0160
- - 0002'10 07 10 13 06
- - - - - - - - - - - - - 1 . 2 - AO ,A3 ,6
0002'11
00 16 06 01
T
,,6,STAT2,1
---0002'12
07-17-16 00
--L2 --A7,A6,O
0002'13
0'1 10 17 03
ASI
AO,A7,3
-0002'1'1
00 -12-12 10
-------------1-----A2,A2,OI0
0002'15
1'1 10 251
8NZ
LHIA
-0002'16
0006 -It 00- - - - - - - - - - - - - 1 - - - STAT2.AC.0
C002'17
01 156'1
J
CISA
1l002:'0 0000 CO- 0 0 - - - - - - - - - - HOOP
A7.STATlt!
oe02S1
00 17 0:' 01
LHIA
T
- - 0002:'2 --1-2 -13-010- - - - - - - - - - - - - - - -Ttl- /13.010
A7.A7.cI6
OC0253
07 17 17 16
L2
- 001l2S'I--1 'I- 01-335 -- ----------8Z-- FALTle
OOCiZ:'S
OCi 00 00 00
NOOP
---- 0002:.6--01-1:.6'1----------.J--- CISA
0002:'7
00 00 00 00
NOOP
• FC-27 RR.RK --
101~7J
MASK
• CtiECK fOR cLASS I LOCKOUT
• GO SToP AND ENTER CONSULE SEQ
• TO COMMON iNT SEQ
DIVIDE
---------------
000260
01 2217
EMKI
J
EMKIA
000261_00_.1L tll--ltl- __
L ____ A2. AO, II I 0
000262
01 032'1
LJ'I
J
EMAIA
000263 _l:._16_nC--_OO _______________ ltC
016.0,0
00026'1
00 00 Ie 02
LM2
T
UP.AO.2
Oil0265_12_l2_0CO
_~l1L_ TCI
A2.0
000266
00 12 13 03
EMIILA
T
IRo.IRS,3
000267
00 _03 __QL_0_~_
TMOf(. MOR, 0
000270
1'1 16 335
BCL
FALTIC
000271
15 _16 10 _00 __________________ .MCO 16,0 I 0,0
000272
01 1566
J
Clse
00C273 _12_I'L120_
_ _ _T_CI_ A7.0120
-------------------
• RA TO A2 1551
•
•
•
•
•
•
•
•
•
INITIALIZE liD INTS
TO NE ... M lCRO-P
CP ILLEGAL INST INT COUE
~AIT FOR POSSIBLE MEMORY REf,CLR NI RESIO
COMPLETE POSSIBLE SPLIT CYCLE
GO STOP AND ENTER CONSOLE SEQ
SET PROG~AM fAULT
TO COMMON INT SE~
CLASS II MAIN MEMOHY LOCATION
____ . SEHDR 027'1 •
-- _ _ _ _ _ --I--_INSTRUCTION READ
T
lRo.MDR,2
00C27'1
OC 12 03 02
- ------- --- . --- - - E .
0 I 6 ,0 , 5
000275
17 16 00 os-AO,RGRS.OII
T
C00276
DO 10 Ie II
------------0
C00217 --CIlOCCO---
• MOR TO IR
• BRANCH I
• RGR To AU ISS)
!
J
'-
("l
PAGE
I
CD
J
3'11.
3'1Z.
3'13.
3'1'1.
3'1S.
3'16.
3'17.
3'18.
3,,9.
3S0.
______ SETAOR 0300
---_*
"
OOa30iJ
000301
00030Z
OGC303
00030"
00
00
00
17
03
00
00
00
DD 00
3Slo
J
~
35Z.
___ 3S3.
35'1.
-- --3SS. -
J
:>
'"'
• INPUT DATA TO MOR
• START.KElP SGR
- DIVIDE
-DO -12 10 10------~MIC.Z------- TAZ.AOtOIO
EMKIA
000106 01 2217
J
- 000307 - 00 16 03 00------- - - - - - - - - - T - -106 tMOR ,0
• RA TO 102 (5SI
356.
- - - - - - - - - - - - - - - , - - - - - --SETADR 0310
358.
--3S9.
360.
_ _ --ltd.
• 110 INPUT PASS
_______ _
162.
000310 00 03 16 01
T
___ 363 ' _ _ 0 0 0 3 1 1 0 Z _ 1 5 -00 _07 ___ . _____________ AS2 __
36".
OOOllZ 00 00 03 O a T
_---.l.6S.! ________ Q00313--l7_DOJC--_1'I
E
366.
oca31'1
00 00 00 00
NOOP
---369.
J
~--
--- -00030S
:> __ ~:!: _~~~~!:
)
16 01
--- --. _. --- - T
HDR II DR t1
NOOP
00 00
LIla
03 00
- - ---- ------------1
DO.MDR.O
10 I"
E
0.010.01"
DD (;0 --- -.------------------!iOOP
· - - - - - - - - - - - - - -....-F'c.Z 7 R I .Rl(
-3S7.
J
--liD INPUT PloSS GT
370.
-·--37-1.
37Z.
---l73.-
~~ _~~_g~ .~~--- --------LGS----- _~OOP
----COO-l1-7 - OO-OIl--IG--l-li---------
1
HDR.IOR.I
AS ,UP. 7
DO.MORtO
0,010.01'1
• INPUT DATA TO MOR
• HICRO-P-l TO AS
0.0.01'1
RGRO.AO.OIQ
• START
• TRANSFER RA -Tv RA SET CONDIT I or. CODE
• START.KEEP SGR
- - - - - - - - - - - - - - - - - ' S E T A D R 03Z0
•
37'"
1/0 OUTPUT PASS GT
---3-7S •.
376.
J
------317.
"
J
------31-9 • -.
378.
380.
_---------11ll-o_
J
)
.:)
...,.
.J
)
38Z.
------383. -- -
38'1.
- - . l a s ..
386.
---l87.
388 •
---38-9 .. 390.
---391.·
39Z.
-- ---393.
19'"
39S.
396.
)
197.
000320 00 00 DC 00
NOOP
CC032100 -00 - 0 ' " - 0 0 - - - - - - - ----NOOP
ODR.MORtZ
00012Z 00 16 C3 OZ
T
---000323 -17-00 IG---' "
-E - 0,010.01'1
00032'1 DO 00 00 00
EMAIA
NOOP
IhO.O 1'1
O(;032S
11 OC DC -'''£1 ____
.....,
'-'
:)
:)
I_INDIRECT BYTE MODIFY
00 12 16 00
A2.A6.0
T
_IS _a7 1'1 -00 - - - -_ _ _ _ _ _-lK.C ____ l.O I '1.0
01 2760
.J
LAl6
0'116 '13 -al --ASI A6 ,MDR.3
I INDIRECT BYTE NO HOD
- - -'1-10.
00n3'1'1--'1C-I2- 16 00
1'----A2.A6.0
'III.
0003'15 1507 1'1 00
HC
7.01'1.0
----'112.
0003'16 - 012160 -.1-- ---LA 16
'113.
T
A6,MDR.0
C003'17 00 16 03 00
---'11'1·
----------~INDIRECT lORD HODIFY
'115.
OOOlSO 00 12 16 00
T
A2.A6,0
---'116.
000151 -15 071'1-(10------ - - - - HC--- 7-.0 I '1,0
'117 •
000lS2 0 I 2760
.J
LAI6
___ 'lIS'
aOC3Sl ----0'1--16 OJ O-lASI A6.HDR.3
'119.
• INDIRECT .ORD NO HOD
_ _'120.
-- - -- COOlS'! _ ._00 -121LOO---1-_A2,A6,0
'121.
aaOlSS
IS 07 1'100
He
7,01'1,0
'122"- ___ _
. - -_ _ _ _ _ _ _ _ .J__ _LA 16
____ ce03S6 _0'- 2760_ - __
'12l.
00illS7 00 16 03 00
T
A6,MDR,O
- _ _ _ _-------'IO-!lIN ORMAL_ BY TE MOD I fl'
-~!~~-:---000360 03 12 16 1'1
5
A2,A6,OI'l
~2bL ___ _
- -OC Q 361 __0.L16-O-J --&jO-..l3~_ _ _ _ _ _ _ _ _ ___"A'-'lS...1 - ~ 6 .1\ aR .3
'127.
000362
17 00 00 .07
E
0.0,7
'Us. - - OC036l---C0 -I-Cnli:~-U
TAO ,RGRS.O II
'129.
I NORMAL BYTE NO HOD
____U£lL
--IH10 36 '1----D--2--U-C 0 I 2
_ _ _ _ _ _ _ _ _~L2 ___ A2 ,"SO .01 2
'Ill.
oea36S DC 16 Ol 00
T
A6,HDR.0
--'Il2.
-- 000166 1-1----'14----00--07
LAI---E ---- 0,,0.7
'133.
000367 00 10 10 II
T
A-.~RS,OI1
---'13'1. . - - - - - - - - - - - - - - - . . ~ORIIALIORD HOD IFY
'1lS.
OCOl70 00 12 16 00
T
A2,A6,O
_ _!t3-4L_______ -----000371- 0 9 16 U
03
A-SI ___ --A6,MDR.l
'137.
000372 17 00 CC 07
E
0,0.7
- - ItJS'-- 000l7l-0C--l-O-I~-OlT -----AO,RGR5.1
'1l9.
I NORHAL lORD NO HOD
--'I't0. -- - 000l7'1--00 C(l.-OQ-(l.O
liiOOP
A6,HDR,O
'I'll.
DOOl7S 00 16 Ol 00
T
0,0,7
----'1112.
--- 000l76--17--.0(l OQ-uO+7-------IL~AA_42---.---!:AO,RGR5t1
'I'll.
000377 00 10 10 CI
T
_ _ _ _ _ --0_ - __ - - - _ _'1'1'1.
I
Fc-02 RI,RX - LOAD DOUBLE
'1'15.
- -_ _ _ _ _--"1 _
_ . __
'1'16. ----RGI __
:>
o
o
o
n
o ____
o
J
r
-------------~---
C"l
I
-D _ _ '1-5-.9.
}
• A6 TO A2
• H+I To 5GR
• JUMP
• A2 + MDR TO A6
• 46 TO A2
• H+I To 5GR
• .JUMP
• I'IDR TO 46
• A6 TO A2
• 1'1+1 To 5GR
I
.JUMP
• A2 + HDR TO A6
A6 TO A2
To 5GR
• JUMP
• MOR To A6
I
• 11+1
• A6 R51 TO A2 (551
.• _A2 + MOR TO A6
• SRANCh 2
• RGR To AO (551
• _ZERO TO A2
IS51
• HaR To A6
• SRANCH 2
• RGR To AO (551
• A6 TO 42
• A2 • MOR TO
• BRANCH 2
• RGR -TO Au
A6
•
• MDR To AI>
• BRANCH 2
• RGR To AC.
• HDR To RGR (551
, 46 TO A6
• OP-REF. A TO 5GR
PAGE
8
----------_MINI-UVK-ZO (APEI
o
::)
-.
..J
:)
'""
'-'
=>
'ISS.
'156.
'157.
'ISS.
'159.
'160.
'161.
'162.
'163.
'16'1. T
_ '165.
'166.
----
000'10'1
000'105
-- -_._----
-------_._---_._----
DATE 101573
00 -0'1 _03 10
17 0(; 00 1'1
.RGRD.MDR.OIO
0.0.01'1
• MDR TO RGR (55)
• START
------------~------------.~-----
• FC-03 RX - LOAD MULTIFLE
RX -STORE MULTIPLE
----------------------------.~_FC.13
e'l &6 16 0'1
OvO'lC7
17 00 00 03
000'110 -00-1010-01
OOC'Ill
1'1 12 OG6
000'112 DO 0'1 03 -00
000'113
17 00 00 1'1
O~O'l06
_ _ %7.
-----1.-1.3 ---.--.-1.51
A6.A6,'1
0,0,3
E
_________________ T_____ AO .RGRS ,I
EMA5
SAM
LA3
L
___ RGRD .MOR ,0
E
0,0,01'1
---- -- --- - ------------------------------0 _________ _
'I6S.
___'169 •
'170.
---'171.
'172.
- - '113.
'11'1.
AI. - I TO AI.
, OP-REF, A TO SGR
RGR .To Au
, BRANCH A NE M
• MOR TO RGi<
• START
• FC-06 RI,RX - LOAD DOUBLE AND INDEX By 2
000'11'1 00 13 13 03
EMI.l.
T
5GR,IR5,3
OCD'IIS 02 0" 10 0'1
1.52 RGRO,RGRS,'1
IS 07 0(; (;0
MC
7,0,0
COC'l16
000'111--00 G'I-03-1D
f----RG~D,MOR.DIO
000'120 DC 16 16 00
T
A6,A6,O
- - DC OH l--- 11-- 00 ~(j --o-3---------------E--- . 0 .0 • 3
~'S.'176.
--"".
'I7S.
• M TO SGR
• RGR - I TO RGR
• A+I TO SGR
• MDR TO RGR (55)
• A6 TO 1.6
• OP"REF
--- ---- --------------------------------_+o-.fC.&O'l-RX -.. SYTE LOAD AND INOEI'. By
• FC-OS Rl,RX - LOAD.AND INO~X =Y I
.- .__. _ - - - -----------------------------------....------_ .._--_._--'17-90'ISO.
SGRtlR5,3
COO'l22 00 13 13 03
EMA7
T
RGRO,RGR5,'I
-OCO'l23 --02- 0'1 10 C'I
--------~S2
'"' ----"81.7,'1,0
I1C
-'
'IS2.
IS 07 0'1 00
OOO'lZ'I
T
--RGRD,MDR.OIO
----"83.-- --.
---COO '12 f>----OO 014---03 -I~
'IS'I.
0,0,01'1
E
17 00 00
000'126
:) --'1850---'186.
• FC-3'1 RI,RX - COMPARE MASKED
"I
• 11 TO SGR
• RGR +1 TO RGR
• A TO 5GR
• MOR_TO RGR .l551
• START
____--'It'-"S
.. ZL-______ . _________________________________________________________
'ISS.
000'127
IS 07 CC 00
___ tIHlUD __ 00 _lLJ-O __ CL.___
'190.
000'131
07 10 II 06
____--''11'91..1.0_ ---------~OO 'l3L_il'L_U_--0.3._G6ceO'l33 051011.10
'I9Zo
~S9.
o __~:~: _
u
-
----~~~~;~--~~~~~~I-------------~!c-- -~:~i~~~
----------------------- ... - - - - - - -
----~9S.
:>
o
o
, FC-07 RI,RX - LOAD
'196.
-----'19 7 •
'19S.
--~~~:--
000'136
_L ____
00 02 OJ CO
:J
EMA9
~~~~~ -~~-~~ir~~;-----
50S.
___509.
SIOo
__.......5.11·
•
•
•
•
• A-ITO SGR
RGR To AI
AO.AI To AO
AI.MOR TO AI
AD - AI TO AD ISS)
• START
•
U CorH CC
•
•
•
•
o
•
•
•
o
y To pREG
y.l ADDRESS TO BUSS
OP-REF.A TO SGR
y.1 .To STATUS I
Y_2 AOURESS TO BUSS
OP-REF.A TO SGR
ENABL£ P~R I~TERRUPT5
y+2 To STATUS 2
START
PS~
T
PREG,I1DR,O
~51
~~~~~,'I
- - - - - - 5 0 1 0 - .. -oeO'l'l1 00 eSOl 00 - -------------- -.-f. ---STAll ,MOR ,0
502.
000'1'12 0'1 16 16 0'1
1.51
A6,A6.'1
--503.-0G-0~J.--1-7--00__CG__03------------------£--- 0.0,3
50'1.
COC'I'I'I
IS 16 00 10
He 016,0,010
-50S.
--000'1'15--00 06 03 00---------. T-- _STAT2,t-1DR,O
506.
oeO'l'!6
17 OC DC 1'1
E
0.0,01'1
----so 7.
~
EI1AS
I1C
7,0,0
_ _ _ _ _ _ _---'-T __ AhRGRS, 1
L2
1.0,1.1,6
________________.....JL...,2 ___ AI • MDR, 6
SU
AO,AI,OIO
• FC-12 Rl,RX - STORE OOUBLE
-*- --
COO'l'l7
____ 000'150
00 16 16 00
lL~0--03 ~.l.
EMAIO
--~---
T
E
-
• A6 TO A6
• QP-REF. A TO 5GR
PAGE
9
o
')
--,
I
,
:J
J
~
0
~
0
~
0
0
0
0
0
0
,,<"'>
....•
DATE 101573
512.
513.
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521.
522.
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12
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DATE 101573
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17 CO 00 I~
LOIIIA
E
- - - - . - - ----- --TCO c~ 12 CO
I~ CO 252
LOV2
BN
-- 05 I 0 I 0 I 'l -·----------------su
OS 12 12 OS
SU
. -. ------- - - - - . - ---- - -.. -4
CI 227503 10 10 10
5
_ _ _ _ _ _ _ _ BN _
1~-OO-312
LOV~
A2,A2,2
LOV7X
LOVIA
LOv3
A6,A6,~
LOV6
RGRI.l.SM.OI'l
0,0,01'1
RGRD.A2.0
LO~2B
AO.AO,OI'!
A2,A2,5
LOV3
AO,AO,olO
LOV 8
RGRD,SMIOI'l
0022'45
.1725. T
0022'l6
5U
1726.
0022'l7
05 O~ 06 1'4
O.O,OI~
----1727.
002250-·-17 OC-OOI~-----\.LOV2L----~E -SU
RGRD,A2.'4
1728.
002251
05 o~ 12 o~
---L~O.\t\/·.2 8 --- - - _s U
A2,A2.5
--17 29.
002252 - OS - 12 12-05A6,A6 ...
SU
1730.
002253
05 16 16 Q'4
_
1.731.
_ 00225~- 01 2275___
.....J_
LO~3
AD,AO,OIO
1732.
002255
03 10 Ie 10
S
---1.733. T
- CC2256
,~- 00-311-----------·---__ BN . - LOv7X
LOV2A
173'l.
002257
01 2250
J
--.1735.
.. ----002260
00 00-0000-- -- ----- - - - -~OOP
1736.
CC2261
16 10 001
LI~
RN
1
--l-737.
- ---002262 - 03 -IO-Ili--t-tt-5 - - · AO .AO.O 10
1738.
C02263
03 II 11 t6
5
AI.AI.6
--1739.
- (l0226~
11- 00- O-tr-l ~-.
t·---O.o.o Iii
,7'40.
002265
00 0'4 II 10
T
RGRD.AI.OIO
---~ HI. -.
--0022106 - -(lQ--ft'+-02--i;1j-- -------IL~Fo.J9~-----'T----- RGRO ,PREG. 0
171i2. T
002267
1'4 16 273
BCL
LFIO
- - I H 3 . - - C 0 2 2 7 C - - -t2t2-G06---let
A2.6
17'4'4.
002271
CI 1565
J
el5S
----1-71i5.
-0022}2 --12-11-12G---·--Tel
A7.0120
17~6.
002273
01 Q211i
LFlo
J
RUN8AR
--l11i7.
--(Hj221~ --H.-li>-(PI-OO-·
MC - OU.Ii.O
171iS.
002275
03 12 12 02
LOV3
5
A2,A2,2
--J.7-~9. ------002276-- 02- 15-00-11-4--1.-I).1I .... - - - - . -A S2 - A5.up.~
1750.
002277 -'6 01016
OS
ol~
---US I.
C~2.J00--tl~I2-l6-HlSU--A2 .A6.0 10
17S2~
002301
0'4 12 16 03
ASI
A2,A6,3
_-.17530T_
-002302--I'LC;0 -100.----BI'L. _l.OV5
175~.
002303
00 0'4 06 IC
T
RG~O.SM,OIO
__. 1 - 1 5 5 . _ . 00230'L- 00 00 I~ 02----______ .. ___ T__UP,A5.2
1756.
002305
OS 12 16 00
SU
A2.A6.0
---1.257 ___ .---------002306.--~n.OO--1S-02__
~V5- - -1
-UP,A5,2
175B.
002307
00 OC 00 Oc
NOOP
_ _ 1159. _ -___.~il2110 _ 01-2231..-----LOU-- - ___ J --- _LOv lA
1760.
002311
15 OS 02 10
LOV7X
MC
5,2.010
---17610
--tJ02312-- 01-2250- ---------LI).V~----···~·
·LOV2A
1762.
C02313
15 OS C2 10
MC
S,Z,OIC
P61.
--002311i
13 -12 011
----- -------LAO'--- --Te2
IRD.CI7
17o.~.
002315
12 10 017
TCI
AO,OI7
1765.---0023110---03--10 10-110----------1.A7------- 5
AO .AO ,e
• TO Olv/SU~ SE~
• 5klFT A2 L IRAI
• ~XECUTE REMOTE IF
• GO STORE REM
PAGE
OIlERFLO~
• TO Olv/SUB SEQ
• COMP A6 IYI
• .Jp IF OVF
• COMP QUOT 1551
• START
• RA RESULT (REMAINOERI
• JP IF Y AND ~A NEG
• COMP AO (551 IRAol1
• COMP AZ (RAI
• TO CIII/SUe SEQ
• SHifT AO L (551 (RAoll IQUOTIENTI
• JP IF OVf
• COMP QOUT (551
• START
• COMP REMAINDER
• CCMP AZ IRAI
• COMP AI> " I
• ,TO 0 I Vi SUB SEQ
• SHIFT AO L 1551 RA+III~UOTIENTI
• EXECUT~ REMOTE IF OIlERfLOA
•
•
•
•
•
•
REPEAT NEXT 2 INST 16 TIMES
SHIFT LEFT (5SI
SHIFT RIGHT.I~SERT BIT SAVED
START
RETURN REVERSED DATA
• P TO i(~
• JP IF CLASS II LOCKED OUT
• INT CODE
• CLASS
•
•
•
•
CLEAR RUN
SHifT AZ LIRA)
"11 CRO-P TO AS --.
REPEAl Dill
• A2
•
•
•
•
•
II MAIN MEMORY LLlCATION
AI> TO AZ
IF NEG
QuOT TO RGR 1551
RETURN
A2 - A6 TO A2
RETURN
0
.JP
• SET OvF
• SET OvF
• LEfT SHifT
IRAol1
31
1766.
1767.
1768.
17 ... 9.
1770.
1771.
1772.
1773.
177'1.
1775.
1776.
177 7.
1778.
1779.
1780.
178 I •
1782.
1783.
178'1·
17a5.
----1786.
17a7.
17aa.
17a9.
1790.
1791.
1792.
1793.
--179'1.
1795.
1796.
1797.
1798.
1799.
1800.
1801.
--1602.
1803.
180't.
1805.
1806.
1807.
1808.
1809.
1810.
1811·
1812.
1813.
lSI'! ,
1815.
1816 •
lS17.
1818.
1111 9.
I
lE'20.
("'l
1821.
I
w
w_- 1822,
I
0'
32
DATE 101573
HINI-UYK-20 (APEI
002317
002320
oe2321
002322
CIl2lZl
00232'1
(102325
(102326
002327
002330
002331
002332
002333
00233'1
002335
002336
002337
0023'10
CO
15
17
CO
03
OC!
13
16
02
IS
00
17
00
IS
IS
00
17
15
1'1
15
00
oe
10
III
03
10
IS
IS
Ie;
00
,,0
10
07
0'1
00
05
to _e2
02 00
00 1 'I
00 CO
Ie -00
10 C!2
011
002
-15- 03
02 CO
IS li2
00 III
00 00
CO2
Oil 00
07 10
OC 1'1
01 00
_.
_T
HC
_E
NOOP
__ 5
- - ___ .LAB
T
__________ TC2
RN
____ AS2
HC
T
E
._-----NOOP
HCS
LA9A
HC
T
~--.--------
_~
_ _ _ _ _ _ _ _ _ 0-
- ..- - -- - - - - - - -
---[
HC
XLTRH,A:l.2
01!>12,0
O.O,Olll
AO lAO 10
XLTRHIAC , 2
CK 115
2
AS , XLTRI3
015,2.0
XLTR,AS,2
ti.U,OI'l
2
7.'1,0
RGkDIPPROD,OIO
0.0.01'1
5 tl .0
CHANNEL CONTri(JL
, START
, LEFT 5HlfT
, REPEAT NE~T 3 IN5T
• AI + THA~5LATOR TO A5
• CHANNEL CONTHOL
• START
• SELECT MOST
A TO SGR
START
SETAOR C237'l
•
-----.--ILLEGAL 11-0 INST
C0237'1
002375
-J
01 0266
12 12 002
TCI
-_.-
------
----
-
01 0266
-1 l- 12 -coo
-----
002'100
OC2'10I
002'102
OC2'103
002'10'1
002'105
002'1(;6
002'107
&02'110
oa2'111
-002'112
002'113
C02'111l
002'115
002'116
002'117
002'120
002'121
002'122
002'123
OC2'12'1
002'125
002'126
J
---
-
~~.-~
--------_._--
Tel
EH II LA
A2.0
•
__________________
SETAOR
,
- _____-lK3 - - HC
15 co OO.OC
T
00 1'1 0'1 00
- - - - - - - ---J
01 2'132
NOOP
co 00 00 00
_________ T
00 -10 13 -01J
01 032'1
1-00 10 1'1 G2 --- - - - -- --- -----T
TAJ
CO 0'1 06 10
.--. -----U't.
-HC
15 07 0'1 00
T
00 0'1 06 10
---------- - - ..
E
-17 00 CG---Ilf
HC
IS 05 01 00
T
EMAIlIA
00 II 10 -0 I
IICS
IS 10 0'12
HCS
15 10 0'13T
00 0'1 C6 10
. T
CO ''1 _06 IC
HC
15 05 01 00
HCS
IS 10 0'16
MCS
IS 10 01f7
T
co II 06 00
T
00 I I 06 00
IIC
----_._----- .
15 07-0'1-00
----------
-
• 110 IL.L.EGAL INST INT CODE
ILLEGAL CP INST
•
002376
OC2377
EHIILA
A2.2
----
_021l00
OIU,O
A'I,PT8LS,O
LNSUB
_f'AC,IRStI
EHAIA
PT~L.D.A'I.2
RGRO,5M.OIO
7,'1,0
RGkO,SMIOIO
0,0.01'1
5" 10
AI,RGRSti
01f2
O'lJ
RGHD,SI'I101O
A'I,SMIOIO
5 ti,C
a If II
(,'17
AI,SM.C
AI, SM, Ii
_7. '1,0
·
·
·
··•
·,
··
•
·
···
·
CP IL.L.EGAL. INST INT CODE
U CaNT PAGe: SEL.ECT
IR VAL.UE TO PAC
RETURN L5
A TO :ouR
RE TUR~, 1'15
5TART
DOU8LE. PRECiSION STATu:>
LS PO"TluN
SklFT LEfT DP LS A"ITk U.-B IT)
sHin LEFT OF MS HelTH III-Bill
RETURN L.5
DOUBL.E PriECISION STATuS
ExTRACT 81TS SHIFHD L.lf'T LS
ExTRAcT tllTS SHIFH.D L.lFT MS
A
To SGR
(1l-tllT )
(1l-BIl)
_ HINI-UYK-20 IAPE)
1823,
182'1.
182S,
1826.
1827.
1828.
1829.
1830.
- --183 I.
1I!32.
- __ 1833.
183'1·
___ 183S.
1836.
1837.
1838. T
1839.
18'10.
-18'1 I •
18'12.
--18'13. T
IS'I'I.
~ -l8'1S.
18'16. T
---18'11-. IS'I8.
---111'19.
18S0.
~-18SI. T
18S2.
~--l8S3. - T18S'I.
--l85S.
1856.
_1857. T
1858.
1859.
186O.
--1861.
1862.
--1863.
186'1.
--lS65.
IS66.
1867.
1868.
1869.
1870.
--187&-.1872.
__ 18~l. T
187'1.
____ U1S.
1876. U
_ U77.
187S.
1879.
DATE 10lS73
002'127
002'130
OU2'131
_T
00 -0'1 1'1 -00
01 0626
12 12 0'10
RGRD,A'I.O
J
TAl
TCI
A2.0'l0
PAGE
33
• RETURN 1'15
• MASK
-- ._THIS _SUBROUTI~E PERFORMS T~ST~ TO DETERMINE IF AN OPERATOR ENTRy CAUSED A
• CHANGE IN THE DISPLAY REGISTER - 1'I0DIFIE5 ADDM REG (A'll AND DISPLAY IF NEC
-*__INPUT A'I" ADI)RESSED REGISTER AS" ALTER MODE STATvS
• OUTPUT A'I AND DISPLAY MEG LOADED nlTH MODIFIED VALVES IF CMANGE ENTERED
________e._- ___ . __
--- - - - - - - - -
002'132 112
002'133 00
002'13'1 C6
002"3S 66
0(;2'136 00
002'137 CO
1'1
002'1'10
002'1'11
00
13
002'1'12
002'1'1J 00
002'1'1'1 00
002'1'15 --1'1
16 00 0'1
LNsua
A52 A6,UP.'1
• SAVE RETURN+I IN A6
13 02 01
A3 ,DREG 01
• SAVE ,URMENT CONTENTS OF DISPLAY REG
--------------- _T
12 12 05
A2.A2,5
LI
• SET A2 TO ALL ONES
Cl- 12 C2 - 01-- ~57C; ______
-t"--irI'I~'""~ri!_-----.._*A~.f:~~·Sf'~~~SS_hII.ET
eiitE:6 .... 2.£
NOOP
00 OC CO
-- ---------- ---L
AO,DREG,OII
• REG CLEAR S~ITCH ACTION READ DISP SAVE STAT
'0 02 1 1_
01 062
82
LN5UB2
• CLEAR S~ ACTIVATED SO
------_._- ---- ---15 15--10
-1 - - -A5.AS,OI0
• TEST THE ALTER MODE
• REG CLEAk S~ uNCHANGED SO STROBE DISPLAY
02 000
Te2 DREG,O
00 oIi-- OO---------------------NOOP
10 02 II
T
AO,DREG,OII
• REG fOR PDSSldLE BIT ALTERATION RD DiS SS
• ~o MO~IF SO EXIT AITM ADOR REG A'I
Ol-CS2---- ----------------8Z----LNSUBI
• LOADED ~ITH ADDHESSED kEG lA'll VALUE
a02'1'16 £iD IS IS 1 0 - - - - - - - - - - - - - - 1 - -----A5,A5.010
• TEST THE ALTEH MODE STATUS
00Z'I'I7
1'1 10 052
BNZ LNSUBI
• IS SET (NORMAL) SO EXIT ~ITH THE BIT/~ITS
0(;Z"50 C61'1--IJ (l~
-Ll--A'I,A3.'I
• SET O~ DISPLAY STROBE riET OR'D INTO A'I
CCZ~51
06 1'1 13 00
LI
A'I.AJ,C
• ALTER MODE CLR SO CLEA~ 81T IN A'I
-D02'1S2 .Qw £2 1'1 Iii -0\
:).,"00 LNSuBI-- J
gPi.r..,A'I.2
e-i~·t--A4&-A""""~~1 TH I4Q .. '~~Q~A.l.. UE.,
002'153
12 Ie 377
Tel
AO.0377
• DELAY CT
(]iiZ'I5~- . I'll 7-(l6f}---------------l-NSUBA---5 MJ5 LNSUBB
• ..IP IF MICHO-JP SA SELECTED
CC2~55
0'1 10 10 17
A51
AD.AO,OI?
• DEC CT
- 002'1S6
1't-IO-05~--BNZ--LNSUSA
• DELA Y -LOOP
002'157 00 00 co DC
NOOP
-- Ni2 '160-.vv-CO--li>.-if2---~
--l.NSU8B-~~T-- ----UP. A6 ,2
• R~TUR~
002'161
00 00 oe 00
NOOP
• ALTER MODE BIT IS SET SO EXIT ~ITH
OOZ'I62
1'1 IO-DS2~--- ---------'..NSU82 -ilNZ
LNSUBI
• AODR REG SET TO ALL ZEROS
002'163
12 I~ Oco
Tel
A'I.~
• ALlER MOUE CLEAR SO ExiT ~ITH
(l02'16'1Q 1- 2~S.2--·-------4----LNSUB I
• ADDR REG SET TO ALL D~ES
QJ2'165 CO 1'1 12 00
T
A'I.A2,C
• SAVE MICkO-P + I I~ A~
. -- - 002'166 ~ 02-1 ~-OG-u~-------~\l8
-~A52. -A'I,uP ,'I
• SkifT L ZERO fiLL (SS)
002'167 03 II II 10
5
AI.AI.010
• SkifT L ~lTH INSERT FROM pREVIOUS 1551
002'170 OJ-IO lO-12-----~-----------~- - AO,"O,OI2
• SHIFT L ~ITH INSERT fROM pREVIOUS (551
002'171 {)3 13 13 12
5
A3,A3,012
• SkifT L ~lTH INSERT FROM PREVIOUS
- 002'172-- ilJ- 12-I-Z--02---S----A2 .A2. 2
• ALLO~ I/u
0(;2'17J
17 00 Ie co
E
0.010;0
• V CONT SNlfT INIT
ttl 2 'I 7 'I --IS Hi- 0 1--CHi
----~(---O I u. 1 .0
• REPEAT DOUBLE OIVIDE
002'175
16 {)J 037
00
037
• A3 - A7 TO AJ (551
- C02'176 05-IJ-I? lO-----------------~---sU
--A3,A7,cIO
• A2 - A6 TO A2 (SSI
002'177 05 12 16 II
SU
A2.A6,CII
--~C025QO --17-01J------l-e.-OO
1:----0,1110,0
• ALLOI'o I/O
002501
00 00 00 CO
NOOP
DOVSA
002502 -1't 00-106-------------------BN
00250J 00 00 00 00
NOOP
lIP,A'I.2
(J02S0't 00 OQ-H- 02-----------~0\/8AA
T
• RETUR~
A'I.SRU5.0
00250S CO l't CO 00
T
AJ,A7,cl3
• A3 + A7 TO A3 lSSI
002506 0'113 17- 13_------ --~--DD\/8A
···ASI
DOVSAA
002507 01 250'1
J
• A2 + A6 TO A2
CUl25 1-0 0't12--16--01-__ ASl A2,A611
--
-
~---
HINI-UYK-20 lAPEl
1880.
1881.
1882.
1883.
-1&8'1.
1885.
---1886.
1887.
---l888.
1889.
--1890.
1891.
---1892.
1893.
---189'!.
1895.
-----1896.
1897.
1898.
1899.
- - - - - - - ---
T
-
T
U
U
1901.
--1902.
1903.
.--1-90'!'
1905.
---
~906.
,.
I
A3.AO,0
DDVO
00 13 10 00
T
IS 07 0'1 00
He
7. '1.0
T
A2,RGR5,Oli
~02513
00 12 10 II
DDVOA
0,0,010
00251'1
IS 00 00 10
He
--_ .. ---0,,,,010
002515
IS 00 00 10
--He
T
002516 00 10 10 C I
AO.RGR5,1
IS DC 00 10 - - -- -- ------------- He
D02517
0.0.010
8N
002520
1'1 00 150
DDV'I
- -------------- T
,U ,RGR5 tI
-002521
oil I I 10 01
002522 00 16 16 10
T
A6.A6,OID
------------------- 8N
DOY7
002523 1'1-\)0 171
A7,A7,OI'l
SU
0"252'1 OS 17 17 I'!
----------------------.1
DD~8
002525 - 0 I -2'166
A7,A7, ..
SU
002526 OS 17 17 O'!
AI,SRL5,O
002527 Oil 11- 00 00
----------ODV \---- ---1
AO.SRUS,O
002530 00 10 00 00
T
-- -----DDV2------T -_.- RGRD,AI,OIO
002531 co 0'1 It 10
7,'1,0
Me
15 07 0'1 00
002532
- -------------------1 ----RGHD,A2,O
0(;2533 - DO 0'1 12 00
0,0,010
HC
15 00 00 10
OD253'1
- - - - - - - - - - --T-- -RGRD,A3,C
002535 Oil 0'1 13 00
Me
0,0,010
002536
15 0(; 00 10
- ----" ----_._----- -l-RGI'iD,AO,OIQ
- 0(l2537 00 O'! -10 10
A'!.A'I,CIC
DDV2B
0025'10 00 I'! 1'1 10
T
- ---IH~V 2-A -- --- T
AC,5TATI,5
--0025'11 - 00 -H)-OS US
TC 1 AI ,'!
0025'12
12 1 I 00'1
\01
-O(l25'1~
-AD ,A I."
06 I (I -II 0'1
DDY3X
I'! 00 1'!7
8N
002S'!'!
-- - t! C 2 5 '! 5-- p-- -0 c -1-e-I-'1E -----ChO 1'0 ,e I '!
NOOP
0025'16 00 co 00 00
-- - ------IH>-¥ 3-X ----1 ---STATItAO,'1
- O~25-'!7 00 IlS 10 O'!
DDV'!
AI, A1,0 I 'I
5U
002550 05 II II 1'1
su- --AO,Ao,(;15
002 SS 1----05-- HI---I-o-I5A3,A3,Cl5
SU
O02S52 aS 13 13 IS
su - A2,A2,50025-53 OS 12 1-2-05------A6,A6,Ol0
T
00255'! 00 16 16 10
.lHL_ DDY5
002555
1'1.- oc- 16'1._ - - - - - A7,A7,OI'1
SU
002556 aS 17 17 1 ..
J. __ _DDV8
___ 002557 OL2'IU ____
A7,A7,'I
SU
002560 aS 17 17 0'1
_...su _ _Al.5RL5,CI'I
_C,u2561 __ 05_11.00_ l'f
OOVb
J
002562 01 2566
___ AO .5RUS ,5
...sU
_Cl025t..3 - OS ----Ul--1l!l.-C s
DOV8
J
DDV5
00256'! 01 2'!66
____ 002565 C5__ lA.--16 ..Q..5. __
Ab.Ab,5
SU
A3,A3,OI't
ODV6
5U
002566 aS 13 13 I'!
_ _ J ____ DOV!
002567 01 _2521 ___ ----A2,A2,5
SU
002570 aS 12 12 OS
DDV8
- 002571 01--2.!16.6-----------------D-C-V7 -----J
A6,A6,5
5U
002572 OS 16 16 05
- ..
Al,5Rl5,Ol't
SU
002573 AS II 00 1'1
DDv2
J
00257'1 01 2531
-AO,5RUS,5
-SU
002575 OS 10 00 oS
002511
002512
0'
~900.
1907.
-----t -9 0 8 •
1909.
--1-910'
1911 •
----1-912.
19 13.
--1-91'!.
1915.
_ _191.6.
1917 •
_ _1_918L
1919.
__ 1_920.
1921.
_ _ 1'i22.
1923.
_J92'1·
1925.
__ 1926.
1927.
-----------l-9.2 8.
1929.
--1930.
1931.
--1932.
19::;3.
--193'"
1935.
I
~ --1936.
DATE 101573
----------
T
--
-
T
U
U_
U
U
-
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A To SuR
RA TO A2 ( 551 1'15 Of DIVIDEND
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INC SGR TO RA+2
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INC 5GR TO RA+3
JP If DIVIDEND 15 NEG
RA+3 TO AI
RM TO RM (55 I
JP If DIVISOR IS NEG
CaMP DiviSOR (RM+ II ISS I
TO Dlv/SUB SEIoi
caMP olvl50R bACK (\\ AS NOT I'iEGI
LS Of QUOTIENT TO IU+3 (S5 )
A TO 5GR
f'lS Of REMAINDER TO RA
INC 5GR Te RA+I
L5 OF ~EMAlI'iDER TO RA+I
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MS of QUoTIENT To RA+2 1551
A'I TO A'I (551
STATUS I TO AD to/ROTATE
K
OR AD + AI TO AO
JP IF Ovt:RfLO/\ TO IlE SU,EXEcUTE REMOTE
STAR)
MODIFIED STATI TO STATuS I
COMP ulVIOEI'iD
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JP IF DIVISOR IS NI:.G
COMP OlvlSOR IRM+l1 1551
TO Dlv/SUIl 5 He
CaMP ulVISOR BACK (~A5 NOT I'iEGI
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• CaMp MS Of QUOTIENT
TO Diy/sua SE(,I
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·
•
·•
·
·
PAGE
COMP ulVIDEND
TO Dlv/5UB SEIol
caMP 1'15 Of DlylSOR
COMP loS UF QUOTIENT
COMP
MS
Of I;;UCTI[NT
DATE
1937.
193f.
1939.
19"C.
I 9 .. 1 •
19"2.
19"3.
19" ...
---
------~-
002700
Ou2701
002702
002703
.'
19~:'.
17
00
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-" - ---
--------------
I A \\/0 BYTE (FINAL OPEHAt.D AT Y)
_E
0.0.011
NOOP
,J
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T
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00 00 1 I
00 00 00
0376
16 03 00
··
----~-------.
• J-I
FOR
IA \\/0 BYTE
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002705
002706
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- -----------"
00 1210 00
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J
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----------------------------+--..I .. 2-FOR
BRANCH
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·· ·
·
IA \\10 BYTE
Y + RXI
BRANCH I, ( (RX ITO ACI
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LA2
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AQ
195C.
- I 951.
·
(FINAL OPERAND AT
------------- ---------------------<>--------
19"6.
1<;.,7.
19 .. ".
101573
(FINAL OPERAr-.D AT
Y + RMI
1952.
___ 1 Ii 53.
0027101700-00-11
---------- ------- -E-- -0.0.011
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_______________ ..J ___ LA2
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---19,,7.
1958.
• ,J.,3 FOR
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AT Y + (RM+I)1
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A2
•
(FINAL OPERAND AT Y)
TO All
PAGE
35
MINI-UYK-20 (APEI
.
199'1.
1995.
1996.
1997.
1998.
1999.
2000.
2001.
2002.
2G03.
--- 200'1.
2005.
-----2006.
2007.
- -2008.
2009.
--2010.
2011.
--- -2012.
20 t3.
--- 20 I 'I.
2015.
--2016.
2017·
2018.
2019.
2020.
2021.
---2022.
2023.
202'1.
2025.
--2026.
2027.
---2e2B.
2029.
--2030.
2031.
--2032.
2033.
--203'1.
2035.
---2036.
2037.
-----2038.
2039.
_ _20'10.
20'11.
-------2 0 'I 2 • T
20'13.
_ _20'1'1.
20'15. T
__ 20'16.
20'17.
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('")
I
20'19.
w
---2050.
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)
DATE 101573
-
0027'10
0027'11
0027'12
0027'13
17
07
01
00
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12 00 12
0366
16 03 00
PAGE
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5H 1fT R1, AO To A2 (55 )
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REPEAT NLXT 2 It-;ST 7 TIM E. 5
...-----------_.----------
003000
003001
003002
003003
003CO'l
003005
003006
003007
003010
003011-
12 16 002
1'1 01l-037
0 3 10 10 10
12
Ilcoe
1'1 00
03 10
IS 10
16 07
0'1 12
0'1 --12
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SQ
--
----~--
.--
5ET AOR C3000
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--
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Tel
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S
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5
10 00
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06 13
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--
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A6.2
_TALC
AO,Ao,ole
AI l [j
TAIO
AO,AO,C
2
6
A2,5M.oI3
A2.S0.3
- - - - - - - - - - - - - - . - - - - - - - - - - - - _ . -------
KINI-UYK-ZO
2051.
2052.
20SJ_
205'1.
2055.
2056.
2057.
2058.
2059.
2060.
20610
206Z.
2063.
2C6'1.
--- -2065.
Z066.
- - 2067.
Z068.
--2069.
2070.
--2071.
Z072.
~07l.
207'1.
--2C7S.
2(;76.
---2077.
2078.
---2079.
20S0.
--20SI.
20S2.
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20S'I.
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20S6.
--20s1.
2088.
---2089.
2090.
--2091.
2092.
T
T
T
T
lAPEl
DATE 101573
003012
17 _00 10 - 0 0 _ _ _ _ _
______ E
_0,010.C
003013
IS 07 00 00
HC
7.0.0
003CI'I 00 10 10 -01
- - - - - - - - - - - _____ T
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0'1 12 OLOa- _________TAS _ _ _ AS!
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17 00- 00 111- - - - - - - - - - - - - - - - E ---0.0.01'1
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5
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003061
12 16 eGO
TCI
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16 -06 003-------------~RHS 1
----2C97.
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003063
0'1 10 06 03
ASI
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---2099.- -------~--(!03C6'1--G_'I-1l -01>-03
T
UP,A'I.2
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------003066 -12-11>-011Tel
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A'I.UP.'I
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-~--QQlC71 _O'L-lO -06 -03 ___
-AS1 __ AO.SM.3
IS 10 070
, SHIFT RIGHT ZERO FILL
• START
_ START
• sET ovF
ENTRY FOR /'1=3
TO SCALE SUB
ENTin FOR M= I
IX).(KA+l) TO Al
INC SGR To RA+Z
TO TRIG ROTATl Sua
'101.(RA+21 TO A2 ISS)
~ TO f/.A+2
A TO SGR
, y TO RA
• INC s"RTO RA+I
• 5TI'RT/HOLo SGti
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•
•
•
•
•
•
•
Tft 1 G--SC ALE sUe
CO 305'1 --02 -I 'I O(j--(j-'t------~-----l-T-SE-L- ----AS2
003055
• REPEAT NEXT 2 INST S TIMES
EXEC
-OC3C'Il- CI--1CS'iuTP~--~- -UseL
0030'12
00 II IC 01
TP3
T
AI.RGRS.I
- OCi1C'I1-IS-OG-OO-UI
--KC-- -o.e.olo
C030'l'l
01 3111
J
TPTR
-- 0030 'IS-- 00-121 0 -11-- - - - - - - - - - - - - T - - - - - A Z . RGR S. 0 I I
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T
RGRo.A2.0
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CC3GSO OC 0'1 Ie cc
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003052
17 00 10 1'1
0.010.01'1
nO-JCSJ--no- -c 'i- -l-l---VC
l~ ---RGRO. A I .0
- - - - - - - - - - - - - - . , u
, ALLCiI 1/0
• 10+1 To S('R
• SA~E RETURN + I
• CORDIe SCALE INITIALIZE
• stdrT R liiHT
• SHIFT f/.IGHT
• ALLO{j 1/0 HOLD SGR
• REPEAT SeALE.NEXT 2 INST 'I TIMES
• RETURN
• SA~E RETURN + I
• REPEAT SeALE.NEXT 2 INST 2 TIMES
PAGE
37
2108.
2109~
2110.
2111.
- - 2112.
2113.
211" •
211 ~.
2116.
2117.
003072
00lC73
C0307'1
003iH5
003C76
003077
003100
COlIOI
-~2130.
21310
-~2132.
2133.
-~-213'1.
213~.
-~2136.
~--
2137.
21 38.
2139.
-~21'10·
21'1 I.
-~-21"2.
21'13.
-~21'.'1.
0'1
17
12
16
05
OS
..0
00
lSI
E.
11 06 -03
10 00
1106
OOZ
06 00
06 00
1'1 C2
DC 00 uO
00
16
06
10
II
00
----~-----~
_~ZI50·
21510
__ 2152.
2153.
~ __ 215'i •
215~.
---2156.
2157.
___ 2158.
2159.
2160.
216 I.
2162.
nI
2163.
w ---216'1.
'"
J
-----~-SU
•
2
• REPEAT
ALLO~
I/O HOLU SGR
SCALE,NE~T
2 INST 3 TIMES
AO,SM,O
AI,SM,O
UP,A'I,2
TRIG VECTOR EXEC
003102 01 l05'1
&&lI0l -CO 11--10 10
IS 00 OC lil
00310'1
00310S 01 l1l1
001106 00 12 10 01
001107 01- lO'H
001110 00 0'1 12 00
-
~
Tp!>
J
__ ~_T_f'6 _______ 1
MC
------------~ ~---
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T
-
-.oJ
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TTSCL
AI,RGRS,OIO
C,O,OIO
-- TPTV
A2,RGRStI
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RGRD,A2,0
,
•
•
,
,
•
,
TO SCALE SUB
ENTRY FOR M-2
IA),IRA+I) TO AI
ENTky FOR M-O
INC S~R TO RA+2
TO TRIG vECTOR SUB
1~),I~A+2)
TO A2
TO RE:.ToRE SEQ
\\ To RA+2
• TRIG ROTATE COMPUTATION SUo
--------_.
OCl111
001112
0111113
oe311'1
00311~
02
12
IS
16
02
C03116 ~'I
OC3117 0'1
-- 00312017
001121
12
CO 3 1 22
15
003123
16
- 00312'1(j2
003125 0'1
CC3126 0'1
0(j31Z7 00
0031lO-00
------~--~-~-----
---
TPTR
A52
1'1 00 0'1
---------------~- TC I
16 017HeS
10 030
-----------~----- -RP 1 R
0'1 000
A52
12 11 Il
-------~------~- AS 1
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lSI
10 06 06
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10 0 13 -- -- - - RPTR
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------------ A51
10 C6 03T
CO 1'1 02
OC DC OO-----~- -------~-- NOOP
21'1~.
21'19.
TC 1
RPT5
5U
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NOOP
_ _ _.L.__TRl-GVECTOR
---21'16.
21'17.
_~21'18.
-----------
AI,SM,3
0,010,0
A6,b
---- -------------.--_._------
~-2118.
2119.
2120.
21210
--2122.
2123.
212'"
2125.
2126.
2127.
-~2128 •
2129.
PAGE
DATE 101573
_ MINI-UYK-20 lAPEl
-003131
0l)l132
COl133
00313'1
003115
003136
003117
OOll'lO
0031'11
0031'12
Ot31'1l
0031'1'1
0031'15
eOll'16
0031'17
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02
12
_IS
16
02
o~.
0'1
J7
12
IS
16
02
C'I
0'1
co
00
I'L 110.(1'1
16
10
0'1
12
I1
10
00
16
10
0'1
12
II
10
00
00
017
030
oeo
----------
Ii- 03
06 16
06 06
10 00
ace
013
015
11 03
06 13
06 03
1'1 02
00 00
AS2
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A6,Ol7
03"
o
A2,CORTBL,OI3
AI ,SH, 6
AO.SM,6
0.010,0
A6,0
013
13
A2,CORTBL,OI3
A1,SM,3
AO.SM,3
UP,A'I,2
• SAVE RETURN
+
I
, R1, couNr=O
• REPEATE ~OTATE,~EXT 3 INST I TIME
• ALLO" I/O HOLD SGR
• SHIFT RIGHT SP ARITH
• REPEAT ROTATE,NEXT 3
I~-BITI
1~5T
i~
TIMES
, RETUf(t;
COMPUTAT IUN SUd
A'I,UP,'I
A6,017
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0
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AC.SM,6
0.010,0
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A6,0
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·
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··
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TI~E
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REPEAT RuTATE,t;EXT 3 I r,::. T l~ TIM E5
RETuRr-.
38
I
r __ _
HINI-UYK-20 (APEI
DATE 101!>71
.!:o.
o
2165.
2166.
___ 2167.
2168.
2169.
2170.
-ZI71.
2172.
2173.
217'1.
2175.
_________ , _HYPER .ROTATE \1/0 SCALE EXEC
003151
Oe31S2
CC31S3
OC31S'I
01l31S5
003156
.'
----2.1.91.
2192.
--2193.
219'1.
--2-1-95.
2196.
--2197 •.
2198.
---,-·-2-1-99.
2200.
--2201.
2202.
--2·203.
220'1·
----2205.
22010.
---2207.
2208.
_-2209.
2210.
____ 22110
2212.
--221.3·
221'+·
--2215.
2216.
2217.
221S.
.2219.
2220.
--2221.-
11 10_0 I
CO 00 10
32C612 10 II
30'17
C'I 12 00
--- -
-----
Ot3157
003160
C03161
{l03162
0113163
C0316'1
003165
CC3166
003167
- ___TP1
_T
HC
-
--
-----~--
-
---
T
---..I
----~-~-
---.-
AI .RGRS ,I
0.0.010
_TPHR
A2.RGRS,OII
TP3A
RGRD,A2,O
-J
;
T
----.-
• HYPER VECTOR
~/o
_ _ _e _ _ _ _ _ _ _ _
00317C 00 II 10 II
- 003nl--15 OO-OC---l()
003172 C1 3233
ar.31730C 121e-01
00317'1 01 3050
- -_. C0317S ·--1 S-01----n-lf.-ucr-----
ENTHY FOR II=!>
• IXI.IRA+II TO Al
• INC S6R TO RA+2
• TO HypER ROTATE SUB
• 1~1.IRA+2) TO A2 ISS)
TO REsTORE SE,"
• 1'1 TO kA+2
-~
• HYPER ROTATE ~,/SCALE EXEC
----------- - - - ..
Tpa
OC II 10 0 I
T
AI.RGRStl
-- /'IC
C .0 ,0 I 0
IS GG--OO-IO
J
TPHR
01 3206
-------------- T- --- A2.RGRS,OII
00-12 lOll
00 0'1 12 OC
T
RGRO.A2.0
01 3067-- - - - - - - - - - - - ---~---THSCL
12 16 00-'1
Ttl
Ab.,+
-- -J- -- -TP'I
--01 3050----IS 07 0'+ 00
HC
7.'t.0
----------
21710.
---2177.
21711.
2179.
218C.
----2181.
2182.
--2183.
218'1.
--2185.
2186.
--2187 •.
2188.
--2189. __
2190.
00
IS
IH
00
01
00
PAGE
Tp9
T
.ftt
J
AI.RGRS,OII
- 0 • (j .0 I 0
VECTOR
•
•
•
•
•
•
Ixl.IRA+I) TO AI
INC S6R TO RA+2
TO HYPER kOTATE Su~
1~),IRA+2) TO A2
~ TO RA+l
TO SCALE SUB
• TO RESTORE SE(,j
• A TO SGR
ENTRY FOR 11"'1
SCALE
TPHV
- - - - . - - - - - -_ _ _ T____ A2.RGRStl
JTP'I
-----------11'1C----- 1·. '1.0
------------~. -~y~ER
ENTRY FOR M-7
•
•
•
•
•
..
IX),IRA+II TO AI
tNC S6R TO RA~2
TO HypER VECTuR SUB
IAI.(RA+21 TO A2
TO RESTORE SE\o
A TO SGR
•
•
•
,
•
(XI.IRAtil TO AI
INC S6R TO RA+2
TO HYPER VECTuR SUb
(I'II,IRA+ZI TO A2
TO SCAL.E sua
~/SCAL(
- C031 76-00 -- H- Hl-l-l---l-P-l-(}.----- T--·----A I • RSR 5,01 I
C03177
IS CO 00 10
HC
0.0.010
003200 01 ·-3233-- - - - - - - - - - - - - - - - J - ---- TPHV
0113201
00 12 IC 01
T
A2.RGRS.I
-OG3202 GI- 3067 - - - - - - - - - ------------..1 ---TIiSCL.
003203
12 16 00'1
TCI
A6.'I
-- --1l0320'l--GI- 3050-- - - . - - - - - - . - - - - J
TP'I
003205
IS 07 0'1 CO
HC
7,'t,0
• TO RESTORE SEIo
• A TO SGR
• HYPER ROTATE SUB
---
-,
------
C032e6 02
C03207 - -12
IS
003210
16
C03211
0[i3212 02
---C03213 - 0'1
00321'1 0'1
&03215---17
003216
12
(;03217
16
003220 02
--003221
Cit
003222 0'+
-003223
.7
~---.----
AS2 A'I,UP.'I
TPHR
1'1 OC 0'1
16 00 I - . _ - - - - - - - - - - - - - - _to _ A6.1
MCS 013
10 013
_. _RPTR 3
0'1 003 --AS2 A2.CORTBL.,013
12 11 13
AI.SM.3
11-06-03 -.--- - - - - - ---------- --ASI
ASI
AO.SM.3
10 06 03
O.OIO,C
E
00 10 00 - ---- --- ... - - A6,'I
TCI
16 00'1
RPTR 9
0" 011
AS2 A2,CORTBL.,CI3
12 II 13
- AS 1 Al,SM.3
I I Ol> e3
ASI
AO.SM.3
10 06 03
-E -- o.olo.e
00 10 00
--------~
"-"
-----
.--.--.--~--------------
• SAVE RETURN + I
• SHIFT RIGHT SP ARITH ('I-BIT)
• REPEAT ROTATE,N~XT 3 1~5T ~ TIMES
• AL.L.O~ I/O HOLD SGR
• REPEAT ROTATE,NEXT 3 INST 10 TIMES
• AL.L.OA 1/0 HOL.D SGR
39
MIN I- UY/C-20 lAPEl
2222.
2223.
222'1.
2225.
2226.
2227.
2228.
2229.
2230.
2231 •
- .-2232.
2233.
--223'1·
2235.
~-~ 2236.
2237.
2238.
2239.
22'10.
22'11.
--22'12.
22 .. 3.
--22 .....
22,+5.
---22'16.
22 .. 7.
--22'18.
22'19.
--.4.250.
2251.
2252.
2253·
--225".
2255.
2256,
2257.
--2258.
2259.
---2260.
2261.
--2262.
2263.
---226'1.
2265.
_._2266.
2267.
_ ... 2268.
2269.
__ 2270. T
2271.
__ 2272.
2273,
227'1. T
_
2275.
__.__ 2276.
n
2277.
I
oJ>,.
--.2278.
>-'
~.-
I
0'
00322'1
003225
003226
003227
C03230
003231
003232
DATE 101573
12
16
02
0'1
0'1
00
15
16
0'1
12
1I
IC
00
10
015
002
1113
06 03
06 03
1 'I 02
070
Tel
RPTR
As2
ASI
ASI
T
lies
. _______ HyPER -ROTATE
------- - - - - - -
C03233
00323"
003235
003236
003237
0032'10
0032'11
0032'12
0032,+3
C032'1"
0032 .. 5
0032'16
0032'17
003250
(l032SI
003252
oe32S3
00325"
Ou32SS
003256
0032S7
02
12
15
16
02
0'1
0'1
17
12
16
02
0"
0'1
17
12
16
02
0"
-0'+
00
15
A6 , 13
2
A2,CORTBL,Ol3
Al,SMo)
AO,SM,3
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07(;
1 .. 00 0 ..
AS2
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I b 001
Tel
Mes
10 013
RPTV
os 003
12 II C3
AS2
ASI
11 06 1 3
- - - - - - _ . -AS 1
10 06 03
00 10 ijO
E
16 00'1
TC I
RPTv
05 011
AS2
12 I I 03
ASI
I I 06 13
-ASI
10 06 03
E
00 10 00
~Tel
16 015
RPTV
os 002
12 11 03
-As2
ASI
11 06 I 3
-H! 06-IH----- ---------·--A S 1
T
00 1 'I 02
- --~ ·I<\es
10 070--------
--- -
------------
-----------
-
-------
~UB
AI! • UP, 'I
A6,1
013
3
A2.CORTBL.3
Al.SM,OI3
AO.5M.3
0.010.0
A6.'1
9
A2.CORTBL.3
Al,SM.013
AO.SM.3
0.010.0
A6.13
2
A2.CORTBLd
AI.SM,OI3
AO.SMsJ
UP. A.. ,2
070
-SETAOR 03'100
CQ3"OC
003"C;1
OC3'102
003'103
003 .. C;'1
Oe3'105
003"06
00 1~ 03 CC
OC; \6 16 00
17 CO 00 03
12 12 177
cO -12 12 0'1
06 I 1 03 CO
00 --l3~ 10 01-----------
003"07
003'1IC
003"11
003'112
003'113
003'11'1
003"15
003"16
003'117
(j03'120
003"21
003'122
003"23
0C/3"2'1
07
C;7
CiS
17
12
I"
00
00
00
1"
00
Oil
OS
17
IS
12
16
00
12
.CO
17
13
10
01
II
16
12
CO
-L&I
~--
"'''.MDR.C
A6. A6.0
E
C.U.3
Tel A2.0177
A2.A2,'1
-T
Al,MOR,a
LI
A3,RGRStl
T
HS PART
• 2ND OP
1ST Op
M5 PA~T
,,5.A2.6
L2
__ L. 2
A2,A3,o
A6,A5,ulO
SU
T
-- --------
-LB2
- --"- - - - - - - - -
12 06
13 06
15 10
00 _00
Oij7
1'15
13 00
100e
II UO
153
1'1 00
16 0'1
16 10
CO 00
T
E
Tel
BN
T
T
T
BZ
T
__ LB:!
---------------
--
.
T
SU
E
o til. iJ
A2 .7
La II
,,7.A3,O
"3."0,0
AO ,A I .0
LB I 2
.q • A'I. Ci
A" ,A 6 ,'I
A2,A6.CIG
0,0,0
·
··
·
··
·
·
·
•
··
··
··
··
P A---ll-ASI- A2 0SMoOII
OU3'1"2
17 00 00 00
E
0.000
003 .... 3 -00 IS 12 00------------------ ----1-- A5.A2,0
C03"'I'I
1'1 06 325
BDZ
LB29
- 0C;3'1'15 -12 12-010-- - - - - -- TO - A2.01(;
OC3"'I6
05 16 16 00
SU
A6.A6.0
~POSITION RESIDUE
C03'1'17
15 10 1'10
HCS
01'10
OCl'+5C
15-1C--1-'I-Ifle5 01'11
CC3'151
C;O I" 06 00
LBS
T
A'I.SM.O
lliU'I52
DO--II-l-5-CCi
T-----AI ... 5.0
003'153
CO 16 06 00
T
A6 0SM.O
0C;3'15'1- 17-f)o-~O-OC-------llBl>------E ---- O.CI.o
003'155
00 10 II CO
T
AO.AI.O
003'156 CO-H-13-0ti - - - - - - - - - b - 3 7 - - - - - --f --- AI.A300
003'157
15 10 175
Mes 0175
- OC3'160-00--12--03--{J1
1----- A2,NORMtI
• POSITION COUNT
-- - 003'161
03-121-2-0'1----------~5-- ... 2 .A2."
S
A2,A2.'1
QCi3"62 03 12 12 0"
_____________
COUNT
Tel }o5.2
12 15 002
C03'163
003'16'1- Oil- IS 15--0'!.---------------- ---1-- ___ A5 I A5 ...
MC
0,0.010
IS CO 00 10
003"65
I 't·CO -co 0 - - - - - - - - __________ BN
-tOlQ66
• STORE RESIDUE
--003'167- 05-12-15 0 0 - - - _________ ~U -- A2 I AS,0
003'170
17 CO 00 00
LBB
E
0,0.0
003'171
1213- 371---------------- ----Tel
A3.0377
003'172
06 12 13 12
LI
A2,A3,012
- - 01i3'1,3 -01--13-17-(,0--L2---- ... 3 ,A7.0
003"7Q
1'1 CI 267
BZ
LB~3
003'17 S - 05--13 - 12-00 -- ------ -------------5U - A3, A2, C
003'176
06 17 17 10
LI
A7,A7,010
OOl'i77
17 OCOO at
- - - - - - - . --E
0,1),0
001500
00 17 16 00
. T
A7.A6,C
---003S01- --1'1- 00--3-36-----8N
UNOV
003502
00 16 12 0'1
T
A6.A2.'I
- 003503
IQ-15 277
----8FPR LB2'1
00350'1 06 13 06 C'I
LI
A3,SM.'I
- 003505
15 10--1 H- ----------------- liCS 0 I 7'1
003506
00 OC 16 1'1
T
00.A6.01'l
ee3507 -17-00 cc-oo_______________ E
OIU.O
eOlSIO
12 12 010
Tel
A2.UIO
__ --003511
l't- 00- 303--- .
-- -BN
LB2S
•
•
•
•
•
•
MASK
JPISHIFT CT GT 28
CHECK FOK SIGN DIFFERENCE
SIGN/CHA~ 2NO OP
~P.FLOATING POINT ~/ROUNO INO RESIDUE)
SIGN/CHAK 1ST OP
• HEX ALIGN LEAST
• COMPLIMEhT THl SMA~LER
• HEX ALIGN MOST
• ALLOil I/O
• JP,ANSliER ZERO
• ADJUST cT FOR RESIDUE
• HEX LEFT LE~ST
• HEA LEFT MOST
• ACCESS NORM COUNT
• ALLOI'f 1/0
• HEX NORMALIZE MOST
~.AOJUST
T
T
T
T
• RoTAh.
• INC SGR TO RA+3
• ~PIRESIDUE UNDERFLO~
• ALLOit 110
•
•
•
•
•
•
TEST FOR ZERO COUNT
CHACTERISTIC
JP.NO HEhORMALIZING
CORREcT C.H~R
TEST FOR OVER/UNDERFLOn
ALLOt. 1/0
• Ol/F/UF ERROR
• ROTATE
• ~P.FLDATING POINT
~ITH
• TEST FOR R'I SHIFT I
• ALLOI'f 110
• ~P.R'i SHIFT
RCUhO
'11
MINI-UYK-20
I
2336.
2337. 0'
233e.
2339.
23 .. 0.
23"1.
23 .. 2.
23 .. 3.
23 .....
23 .. 5.
23 .. 6.
23'17.
------23 .. e.
23 .. 9.
-2350.
23510
2352.
2353.
235'"
2355.
- - 2356.
2357.
--235e.
2359.
--2360.
2361.
--2362.
2363.
--236'1. T
2365.
2366.
2367.
2368.
2369.
---2370.
2371.
--2372.
2373.
--- 231'"
2375.
__ 2376.
2377.
---2378. T
2379.
--2380.
2381.
~ ___ 2382. T
2383.
_ _ 238'1.1
2385.
--2386.
2387.
23e8. T
238~.
)l
t;
-'
--- -.1390.
2391.
--2l92.
(APEI
DATE
003512
003513
os 16 16 oc
aD 12 06 00
00351"
DOlSI5
OOl0170L
00 II 1'1 00
DQ)516
(0)517
G0352C
003521
IS
IS
06
06
DC)522
CC)523
(0)52"
00 0" 13 10
IS D7--DO 00
CO O~ 12 00
10
10
12
13
I SO
151
06 0'1
06 0 ..
•
SU
A6.A6.e
T
1.2.51'1.0
• RESIDUE TO SHIfTER
T
1.0.1.7.0
T
A I. A'I.O
• SHifT RESIDUE INTO sur.
~ _______ MCS
015(;
•
HC5
0151
•
---------- 1.1
1.2. SM. 'I
LI
A3.SM ...
----------~-- _ REPACK AND STORE SUM
T
RGRD.A3.010
- - - - - - -- HC
7.0.0
•
T
RGRD.A2,
----.------------- -
003525
0(;)526
003527
CO)530
DO)5JI
(0)532
003513
- 00353'1
COl535
003536
0(]3537
C035"0
00l5 .. 1
- 00l5'12
0035 .. 3
-COl5'1'1
0035 .. 5
0035'16
DCl5 .. 7
0(]3550
003551
003552
003553
00355 ..
003555
003556
C03557
(lC3560
(]03561
003562
001563
0(;356'1
003565
- 003566
003567
C03570
003571
003572
o03S73
_________
•
ADJUST
couNT
FOR
FI~AL.
12 12 006
Tel
1.2,6
051616 00------------------- ___ SU
1.6.1.6.0
' . CORRECT CHAR-2"
001212 0"-----~---------TA2.A2 ...
OS 17 12 00
SU
A7.A2.0
17 00-10 00 - - - - - - - - - - - - - --E
o.OID.a
12 12 377
Tel
1.2.0377
-----------------~--.----- _ ACCESS fiNAL RESIDUE
IS 10 1 .. 2
MCS
01 .. 2
-15-10 1'13--- ----------.----------MCS (j I '13
CO II 06 10
Le9
T
AI.SM.eID
0716 0 6 1 6 - - - - - - - - - - 1.2
A6.SM.016
07 12 17 OS
1.2
1.2.1.7.5
-~------------------ -aoz
1.821
- 1'1 06 331C6 13 17 10
LI
A3.A7.010
06 12 - 16 0"
~----------------__t.1
1.2 .A6.'t
17 00 10 I..
I.BIO
E
o.OIO.cl'l
--DO-O'l--i-l- 00--- ----~-----------l - - RGRO.AI.O
OS 16 16 0"
LBII
SU
1.6.1.6, ..
00 1711 0 0 - - - - - - - - - - - --- -T
1.7.1.1.0
DO II 10 CO
T
AI.AO,C
DO 10-1-3- (i0 . _____________________ 1AO.A3.0
01 3~22
J
LB3
CO -13--1'1 00 ---- - - - - - - - - - - - - - - T
A3 tA".O
12 12 377
LBI2
TCI
A2.0377
07 00 17 17 - ----------~-------l2
DOtA7tCl7
07 10 12 Q6
1.2
AO,A2,6
I" 00-17'1
- - - - - - - - - - - - aN
LBI5
07 12 17 06
L2
A2.A7.6
OS 13-11-10-----SU
A3.AI.ole
os 12 10 II
SU
A2.AO,OII
1 ~ Ou 1 7 7 - - - - - - BN
LB 16
00 00 00 00
NOOP
I ~ 06- 325
.. ------Lal3
BOZ
L829
12 1'1 cco
LBI..
TCI
1.",0
17 CC 00 0 0 - - - £
0.0.0
12 16 000
Tel
A6 t O
1'1 IS 206
eFPR LBI7
00 11 12 00
T
Al t A2.C
0' 3'156
J
LB7
00 10 II 00
T
AOtAltO
.. PERfORM ADO
101573
ADJUST COUNT fOR RESIOUE
LS RL~ORMALIZlD SUM
HEX RIGHT ZERO fiLl. LEAST
HEX RIGHT ZERO fILL MOST
A-I
To SGR
RESIDUE
• RoTATE
•
ALLO~
I/O.KEEP SGR
• MASK CHAR
JP,RE510UE
0
• TEST FOR CHAR U~OERFLO'
• INSERT CHAR
• STARTtKEt:P SGR
=
• 2' 5 CaMp A6
• 2~D OPIMSI
• 1ST oplLSI
ST OplM!o1
•
1
• 2ND OplLSI
• TEST SIG~S DIFfEREhT
• SIGN/CHAK 2ND OP
• SIGN/CHAR
• JPtGO
1ST OP
COMPlIME~T
• eLK RESIDUE
• ALLO'" I /e;
• CLR RE 5 1DUE
• JP.fLOATI~G
PCI~T
SUM
A~D
~/RO~~C
TOGGLE
SIG~
DATE
239).
239'1.
2395.
239~.
2397.
2398.
2399.
2'10(;.
Z'IOI.
2'102.
2'103.
2'10'1·
-----2'105.
2'106. T
--2'107.
2'108.
----2'109.
2'110.
---2'111.
2'112.
-.--- -2'11 J.
2'11'1·
--Z'IIS,
2'116.
----2 .. I 7.
2"18.
-----2'119. T
2'120.
--2"21.2"22.
--2"23. 2'12'1.
-2-'125.--2'126.
---2"'27.
2'1Z8.
--2"29.--T
2'13C;·
--2'13l'
Z'I32.
__ 2'133.
2'13'1. E
-----2-"35.
2'136.
--Z'I37.
2'138.
___ 2"39.
2"'10.
--2 .... 1. T
2 .... 2.
- - Z .... 3.
Z'I'I'I.
- 2'1 .. 5.
2 .... 6.
2 .... 7.
2"'18.
- - Z'1'19.
0'1 13 11 _13
__ LeiS
ASI
A3.AI.013
01 356'1
J
LBI3
0'1 12 Ie II
ASI
A2,AO,QII
AS 15 13 1'1
LBI6
SU
A5,A3,01'1
OS IZ 12 ~s
SU
A2,A2.5
12 13 zoo
Tel
A3,OZOC
00 13 13 0 ' 1 - - - - - - - - - - - - - 1
A3,A3, ..
06 17 17 00
LI
A7,A7,0
01 3565------.l---- L81'1
00 13 IS 00
T
A3,A5,0
12 12377 - - --,-----\.817--1el
A2.:;377
07 IZ II 10
LZ
A2.AI.0IO
(i0 -I C-I-l- 00 - T---- - AO • A I • a
BZ
L87
1'1 01 056
12-12 -CO'l -- --- - - - - - - - - - - Te I - AZ.'1
• RIGHT '1 ROu/'jO
C03613
0" -13 -&2 13---------- --------1<51-- A3.A2.013
OC361'1
12 10 000
Tel
AO.O
,)(,361 5 --(l" -ID --II- 01
A51 -AO. A I tI
003616
12 12 376
Tel
A2.0376
C03617 - -OO-II-U---OQ--1----" l.A3.0
C03620
01 3'170
J
LB~
003621--00---12 -U-O'l---- - - - - - - - - - - - - - 1 - - - A 2 .A2 ...
• eHAR DIFF GT 28
------------------~. "ASK OFF SIG/'j/(HAR
L2
AO.A2.6
01:3622
07 10 IZ 06
LeiS
L819
CC3623 --I't--OO--227---- ---------88~N~
L2
AZ.A7.6
oe362"
07 I~ 17 06
- - - - ------------------------~. eOHPLlI'IENT SMALL.ER
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________ -___ -. ROU/',O sMAL.L.ER
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CC3611
(lC3612
101573
• 2'5 eeMp
•
TOGGL.E SIG/'j BIT
•
TEST FOR RENORMAL.IZE RIGhT 'I
••
RIGHT SHifT 'I COUNT
• TO RENORMALIZE
• ROTATE ShIfT (T
IF SIGNS
DIFFE~E~T
• POSITION REsleUE
• TO RENOR~AL.IZE
• POSITION REsluUE
•
TO RE/'jOR/1AL.IZE
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•
hEX ROUNU ,.OST
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PAGE
'13
DATE 101573
MINI-UYK-20 (APEI
_TC 1 A'I,o
2'150.
• CLk kE.SI(,UE
12 1'1 000
003656
2 '151.·' T
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2'152.
A6,O
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2'153.
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-- --.-------------~- A51
2'158.
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OP eODE ON NEXT LINE IS ILLEGAL
L
RGRD'A3,OI~
---- 2'159.
----- -----I..B23
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• JP.FLOATING POINT ~/ROUND
BF"PR LB Hi
2'160. T
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- - - - - - - - - - ---,JLB:l6
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12 16 002
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7.0,0
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2'172.
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____ ~ __ ~ _____________ ~_~ _____ O-_STORE SUM
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C0370S
IS 07 00 CO
---- -------------ttc - -7.0.0
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2'477.
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2'178.
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---L2
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2'179.
• MASK ANO INSERT I~TO ~ESIDUE
2'180.
~~2'181.
OCi3711-07-12--1'1 00 --------------------L2- -A2.A'I,O
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AI.A2,'1
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_____ ---------------------- .. -ADJUST CHAR RESIDUE.
~-2'183.
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12 16 003
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2'192.
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15 10 ISS
- ___________MeS 0155
RIGHT (IR FOR R£.SIDUE P05ITIO~dNG
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• RESTORE ZEROS FOR A r. 5 .. ER
2'19'1.
ZERO
_T
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2'196.
15 07 co 00
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2'197.
003727
T
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2'198.
• ZERO
003730 00 C'I 00 10
______ L821
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MC
0.(;.010
2'199.
15 _00 Co 10
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T
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251J0.
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• ZEI 17.
,
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- - - - ----- - - - - - - - - - - - - - - - - - ' 1 - - - - 2519.
EIHOM.
PRoe
-2520.
fORM 3.1.1.1.1.9
•
---------LESROMf2!:.21.
ESROMf
EIROMII.II.ESHOMII,21,EsRoMII,31,ESRoMII."I.:
2!:.22. -.. ESROMli.51.c 7 77-IESRoMI2.111
2!:.23.
END
- -- _. __ .. , ._------_._-----252'1.
2525.
SETAOR 010000
---------2526.
2527.
• HEM HOOE-3. M- 1. I-I • 0-1. u-I • Ee'" PoINTER-9
-"
---_.._- -- --".
---252S.
2529.
• • • • • • • • • • • • • • • • • • • • • • • •
•
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IL.LEGAL. INST
o.C.C,Ool t.M III 0
ILL.EGAL. INST
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2531.
010001
0 0 0 0 I 123
".0.0.001 t.M Ilia
EIROM
IL.LEGAL. INST
----2532.
0.0.0.001 t.,., I I 10
- 010002--0 0- 0 0-1- -1-23----ESROM
2533.
010003 0 0 0 0 I 123
0.0.0.001 EM 1110 • ILLEGAL H,ST
[IROM
--253'1·
otl.Otl,O t.MOS
clooe'l -O-l- 0--1--e--07'1
EIROM
ILLEGAL I~ST
253!:..
".C,O.u,1 i:. M1110
OICOO!:. 0 C 0 0 I 123
ESROl'! -- ---- (j • C ,C .0 , I lM 1110
-------2 5 3 6 •
- -- --tH (j(jQ6 - t: C~- Q-l-1-2-J........----.
• IL.LEGAL INST
EIROM
2537.
0.C.O.1.1 EHe3
Cl0007 0 0 C I I 101
EIROM
ILL.EGAL INST
0.[j.0.001 t.MI tIO
--2S38. ------01;:0 I C--o.-0--0--0--1--12..1----ILLEGAL INST
2!)39.
EIROM
0.0.0.0.1 t.~; I I 10
0 0 0 0 I 123
010011
__ ESROl'!
----2.5'lC! •
0.0.0.(;01 i:./'IIIIO
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• Il.LEGAL INST
ESROM
25'110
o.e.Otl.1 E.Mo'!
OIOCll 0 0 a I I 10
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O.O.C.Oo1 t.ld 110
--25'12.
til 0 til 'l- - 0.- fl- 0-- Q. ---1-1-23
• ILLEGAL Ih5T
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25'13.
C,I.Oo1.(; E./'IFJ
010015 0 I 0 I a 1'17
__2.5'1'1. ___
-01001 L -DC - 0 _D--l __ l-2..J..____________ESROM
_o.O.O.eo1 ::~ II 1 0 • ILLEGAL II'lST
[SROM
U.O,O.[jo1 C:rd 110
25'15.
cIOCI7 0 0 a 0 I 123
• ILLEGAL I~ST
____ E.SRQM
0.1.0d.;.; EMJl
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CICC20 0--1- 0 I -C--60l---ESROM
2!:.'I7.
".0.0. e • 1 EMil 1 0 • ILLEGAL INST
[j10021
0 0 a 0 I 123
__ 2S'I8.
o.e.o,ool EM III 0 • Il.LEGAL INST
- - - - 0 10022- 0--0 _0._ 0-l-1-21.- - - - - - - - - - - - - --- -E I RO M
ESROM
O.e.Ool.1 E.HJ'!
2!:.'I9.
010[j23 0 0 0 I I 1'12
c,I.Otl,t; t:MH:'
--25!)O·
--(i1002'1 -c -I 0-1 O--S'lJ--------------EIROM
ILLEC,AL I~ST
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c.e.o.ool C:rd 110
25!:.1.
010025 a 0 0 0 I 123
______________ ESROM
ILLEGAL INST
C.C.O.Ool toldllO
---2552.
OIOOH 0 a Q D 1123--ESROl'!
ILLEGAL I~ST
2553.
0.0.0.001 t.M III 0
010021 0 t 0 0 I 123
O.I.O,I.e i:.MH'i
---25!:''I- - - - -- ---- ---010030 - C 1-0-1-- C-SSJ-------- -------EIRO/'\
EIROM
O,l.Otl.L E.M",3
2!:.55.
0le031
D I (j I 0 610
ILLEGAL INST
u.O.O,(;,1 tId 110
_-2S56.
- GICC32 C o Q 0-1- -12l ---------------------- EIROM
EIROl'!
ILL.EGAL INST
2551.
".o.O,eo1 i:.,., Ilia
0lCOl3 0 (j a 0 I 123
__ ESROM
--------_._-- _..
_-2S58.
c.tl.Co1.0 t:Mt6!1.
2569.
2570.
2571.
2572.
2S73.
257'1.
2575.
2576.
2577.
2578.
2S79.
2580.
2581.
2582.
2583.
2S8'1.
2585.
2586.
2587.
2588.
2589.
2590.
2591.
2592.
2593.
259'j.
2595.
2596.
2597.
2598.
2599.
2600.
2601.
2602.
2603.
260'1.
2605.
2606.
2607.
2608.
2609.
2610.
2611.
2612.
2613.
261'j·
2615.
2616.
2617 •
2618.
2619.
.'
0100'11
0100~2
010O~3
OIOG'I'I
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0100'16
0100'17
Q10j)5iJ
010e51
010052
010053
CI005'j
010055
CI0056
010G57
CIOC60
010061
010062
(JI0063
01006'j
010065
CI0066
010067
0lC070
010G71
010G72
010(;73
01007'1
CI0075
010076
Oloa77
010100
010101
010102
010103
01010'1
010105
010106
010107
010110
010 III
010112
01 [j 113
OICll'j
010115
010116
C I~ 117
010120
010121
010122
010123
CIOI2'1
010125
010126
010127
010130
010131
DATE. 10 1573
0 0 0 II
0 0 0 0
COOOOO
6 I I a
0 0 0 0
0 0 0 0
0 0 0 0
6 I I 0
0 0 0 0
0 0 0 0
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0 C 0 I
0 0 a I
2 0 0
0 C 0
2 0 0
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0 C 0 0
[j 0 0 0
0 0 0 0
0 a 0 0
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0 0 0 (j
0 0 0 0
0 0 Ii 0
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O.C C 0
0 0 0 0
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0 0 [j 0
0 0 0 0
0 0 0 0
I I I 0
0 0 0 0
I I 0 0
0 0 c 0
a I I 0
0 0 0 0
0 I a 0
0 0 0 0
0 0 0 0
a 0 0 0
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0 0 0 0
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ESROM
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0.0.0.0.1 <-~, I I u
(j.CtO.Ool EM I I U
0
0 612
I '162
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l,a·Ooo I ,
223
227
235
2'11
2'j6
252
260
26'1
270
27'1
302
310
31'1
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77'1
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777
677
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•
·
··
·
ILLE(,AL It.ST
IL.LEGAL INST
···
··
·
··
···
··
·
·
·
···
···
··
··
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RK
RI
RR
Ut.AS~IGl'~ L 1 us.t0.0.00101 EMES
0.0.00101 t.MEb
2.0.00101 EMCI~
0.0,001.1 lM C I3
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-
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2620.
21>21.
.2622.
2623.
262'"
2625.
2626.
2627.
2628.
262 9 •
2630.
2631.
.2632.
2633.
--.263".
2635.
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2637.
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2639.
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26'11.
__ 26'12.
26'13.
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26'15.
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26'17.
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--2650.
2651.
010132
010133
01013'1
010135
0'
2653·
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2655.
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2675.
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0 0 0 0
,
PATE 101573
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0101'10 0 I I 0 I 522
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1l11l1'+2 0-0 C C -t. 127--··0101'13 0 C 0 0 I '166
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0101'15 0 0 I 0 I '176
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0 0 0 0 I '176
- .- .------.-.-- EsROM
010150 0 1 I· 0-1--502010151
0 0 I lJ I 506
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.. _____._ -E s ROM
010152 0 0 o 01127
IlIOl53 0 0 0 0 I 506
EIROM
01015'1 0 I 1-0-1- ·s 12-------------EIROH
EIROM
010155 0 0 I 0 I 516
ESROH
010156 -·c Cl - 0-.. Q--t--t..21
EIROM
010157 0 0 0 0 I 516
.__ EIROH
ole 160 0 I -l-·O--l-'ICU
ESROM
I I I 0 0 '113
010161
010162-··.(1.-0- 0 -tJ.-l-'ll-o-~------~~-£SROM
EIROM
0lCI63 0 0 0 C I '162
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o I ~ 165 C 0 I 0 I '+23
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010167 0 0 0 0 I '123
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ESROH
010171
0 0 I 0 I '133
EIROM
- 010172 C -G-0--0--1-·'t05 ~---.
ESROH
010173 C a 0 0 I '+33
01017'1 0 1 l-- 0-+-672-· -~-- ..... --.---.-- - - ESROH
ESROM
010175 0 0 I 0 I 671
C l£i 176 --0- 0- (J 0-l--'+l1----------·--~-E SROH
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OICI71 !l 0 0 0 I 671
- --- 01020C -00 0-0.-1 -512--- -__________ £SROH
EIROM
010201
0 0 0 0 I 512
OlC2Q2 o-a C; (I -.1- 5 I 2 . . ...~------ __ ~ ___ .ESROH
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010203 a 0 0 0 I 512
-01020'1 - 00, a-~+ 512 ..- - _~_. ______ ._ESROM
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010205 0 0 0 a I 512
EIROM
010206 C 0 0-0 I 512 - --_._----------EIROH
010207 0 0 Ii 0 I 512
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-- _. --01(J210 'I I -1- 0 C 06S ESROM
010211
0 I I 0 0 173
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010213 0 C 0 a 1 057
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010217 0 tl 0 I I 202
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(!1!)220 a
0 0 2101
EIROM
010221
0 C I I I 216
.. --EIROM
OI(l222 Ij-+- e· (}·O 21e
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2657.
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2659.
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2661.
2662.
2663.
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2665.
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·•
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ILLEGAL
ILLEGAL
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PAGE
I'C-SO
FC-,,7
FC-'11>
FC-"s
FC-'1'1
FC z 'l3
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·
IL.LEGAL II
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FC-37
FC-36
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2677,
2678.
2679.
2680.
2681.
2682.
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2692.
2693.
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2712.
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271'1.
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2716.
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2720.
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2722.
____ 2723.
272'+0
. _2725.
2726.
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2728.
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2732.
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OATE 101573
1 1 216
EIROM
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0 0 221
EIROM
1 I 220
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EIROM
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010231
0 0 I - I 1 223
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010232 0 1 0 0 0 22 ..
- - - - - - - - - -- ESROII
010233 - 0 0 0 1 - 1- 223
ElFiOM
01023'1 0 I I 0 C 227
--- - --- ------ ----- - ESROM
010235 0 C I 1 I 226
EIROM
Cl0236 0 I 0 0 0 227
---- --------EsROM
013237 0 (j 0--1 I 226
EIROM
1 0 0 '172
0102'10 0
-------ESROII
0102'11 (; 0
0 I S 17-ESROM
0102'12 C I 0 C 0 '172
------- - - - - ----E S ROM
0102'13 0 0 0 0-1 517 - -ElFiOM
0102'1" a I I 0 0 122
---- ------- ----- E s ROM
0102'15 0 0
0 I 121EIROM
0102'16 0 I 0 0 0 122
C102'17 0 0--0 -0 I - 121 --- - ---- --------------E I ROil
EIROM
010250 2 I 1 0 0 236
- - ---------EIROM
tl0251
0 C 0 0 1- 512
EIRO,.,
010252 2 J 0 0 0 236
---~------- E IR 0 M
010253 -2 0 0 1 -I 252
EIROM
01025'1 0 I I 0 0 2'12
______________ ESROM
010255 0 0 1 1 I 2 '11--ESROM
010256 0 I 0 0 0 2 .. 2
010257 0- O-O--I-l--Z'U------EIROM
EIROM
010260 2 1 1 0 0 260
0lC261
C 0 0- 0--1- !il2 - - - - - - -- --- _. - - - - .f I ROM
EIROM
0lc262 2 1 Cl 0 0 26e
----01.1263 2---0- O--1--1--2~7--------- _____ ESROM
EIROM
01026'1 a I 1 0 0 300
010265 a 01 1- 1-21-7---------------- - UROM
EsROH
010266 0 I 0 0 0 300
-------- E S ROM
010267- 0 0-~--1 1- 277
EIROM
010270 2 J I 0 0 275
IH027! -0- 0--0- 0- 1 512--- --- -----------E S ROM
EIROM
010272 2
0 0 0 275
---------- EIROM
010273 2 0 0-1 1 313----EIROM
01e27" 0 I I 0 0 303
------ _.EIROM
010275 0 0- 1--1 -I 302- -----EIROM
010276 a I 0 a 0 303
------ - - . - - - - ElFiOM
010277 --0 a 0 1--1-302
EIROM
010300 5 I I 0 0 325
EIROH
I 12,.
010301 a 0 1
EIROM
010302 5 1 0 a a 325
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EIROM
01;)30'1 3 I I 0 I 323
ElROM
010305 0 0 1- t I 131
EsROM
010306 3 I 0 a I 323
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010307 0 a a
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EIROM
010310
I I 1 0 I 316
EIROM
C 1 0311
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EIROM
010312
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EIRCM
010313 0- 0- 0
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01022'1
010225
('10226
010227
010230
0 0
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0 0
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0
1
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----
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1,1,0.0,1
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PAGE
EMAJ2
FC-32
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EMAJI
EMAJO
iMAJI
EMA2e
t:MA29
EMAl8
EMAZ"
EMAl6
EMAl7
EMAll>
EMA27
EMKl
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EMA'!3
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£1'111 L
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t.MA'I1
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t:MAI3
t:MAJ7
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'f8
RR
RX
Fill
Fil
FiFi
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Rx
FC-30
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FC-27
·
ILLEGAL.
fC-26
FC-25
Rx
INST
FC"'z'I
·
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ILL.EGAL. IJliST
FC-22
FC=21
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Rx
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Rx
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RX
RIC:
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Fe-15
fix
RII
RI
RR
~
I
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'0
MINI-UYK-2.o (APEI
273'10
273!;·
2736.
2737.
273a.
2739.
27'10.
27'11.
__ 27'12.
27'13.
27'1'1.
27'1!;.
27'16.
27'17.
27'18.
27'19.
2750.
2751.
-2752.
• 2753.
275'1.
2755.
2751.,
2757.
2758.
2759.
2760·
27610
-- -2762.
2763.
276'1.
2765.
- ---2766.
2767.
-2168.
2769.
2770.
2771.
2772.
2773.
277'1.
2775.
----- 2776.
2777.
2776.
2779,
2780-.
2781.
-- -2782.
278l.
278'1.
2785.
2786.
DATE
01031'1
7 I I a
ESROM
316
010315 0 0 I
ESROM
156
CI0316 0 a 0 0
512
ESROM
0lC317 a 0 0
156
EsROM
0111320
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I 1 I I
366
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010321
136
C 0 I 4
- -- ----._-- ESROM
CI0322 0 0 0 C
512
EsROM
010323 0 0 0
136
-----____. _£ S Ra H
01032'1 3 1 1 0 l- 330
ESROH
010325 0 0 I I I 1'13
____________________ ESROM
010326 3 1 0 a _I 330 010327 0 0 0
EsROH
I I'll
---------- - - _ESROH
01C330
I I -1 a
-32S
ESROH
010331
16'10
0 0 I f
- -------~---- ESROM
010332
1 I 0 0325
EsROH
010333 (! C C
I 16't
--~-- - -- ESROH
01C33'1 7 I 1 0+ 325ESROM.
010335 0 0 I
1 161
010136 -1)- (} c 0-1 512--------~-~E SROH
ESROM
010337 a 0 0 I I 167
-i:SROM
-(HOl'lC 0 I- I 0 0- 3'11- -----~EsROil
0103'11
a 0 0 0 I 512
01u3'12 -0 I 0 0- 0--3'11 ---- - - - - - - - - - - - . £ SROH
ESROM
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• I C76
[SROM
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[SROM
0103'46 2 I a c (} -363
(SROM
0103'17 0 0 0
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-ESROM
010350--0-1- 1-0-0-355----ESROM
010351
0 0 0 0 I 512
_____ - _ _ ~_£ S ROM
010352 O-I-C 00 --35SESROM
010353 0 C 0
I 110
--ESROM
----- III C35'1- -4.-1--1--~ - 0 -,lS5-ESROM
CIOl55 0 0 0 0 I 512
CI:>356- 0 Q 0 0 1_ -512 ---- --------- -- - --E S ROM
ESROM
010357 0 0 t 0 0 737
----~--~ES ROM
010l6(;.- 0-- 1--1 -1- 1- 366ESROM
C C Ii 0 I 512
010361
___________ ESROM
01G362 - C c-- 0 C-I-SI2EsROM
010363 0 0 0 0 0 637
2 1 1- 0 0 377-~- -----------------ESROM
01036'1
ESROM
010365 0 C 0 C I 512
010366 2 I - 0--0- Ii ·377------------------£IROM
ESROM
0lCl67 0 [1 0 I C 677
01(l370 0 1-1-0-" 373- ----------------E SFi OM
ESROM
010371
0 0 I I I 067
-- EsROM
010372 0 -I 0 0 0 373ESROM
010l7l 0 0 [1 1 I 067
-EsROM
-010l7'1 6 I 1-0-(1-373-- -EsROM
010l7S 0 0 0 C 1 512
ESROM
01Q376 0 0 c 0 1 512 - -ESROM
0lOl77 0 0 0 0 I 512
------END
SRLS
SRUS
-- - - - - - - - -- - FPOV
------- ----FPML
.'
•
•
•
•
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•
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C;t1t1.u.c
EM A'll
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t:MA9
EME)
EMAt.
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EMA6
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EM AII
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0.0.0.0.1
0,1.0.0,0
0.0.0.C..1
2.&.1.0,0
0.0.0.0.1
2,1.0,0.0
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t
----~
70101.0.1
0.0,1.0.1
0.1l.0.0.1
0.0.0.0,1
1.1,1""
O.CoI,O,l
o.o.O,iJ.1
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a.Otl,c.tI
0.0.0,001
o.c.o.o ..
•
101!>73
PAGE
FC-I'I
•
ILLEGAL INST
FC>IJ
•
ILLEGAL INST
FC c l2
FC-l1
FC-IO
·
·
·
·
·•
·•
·
ILLEGAL INST
FC-07
ILLEGAL INST
-FC-06
ILLEGAL INST
FC-05
ILLEGAL I',ST
FC-O'l
f.C-Ol
FC"02
ILLEC.AL INST
EC-OI
···
FC-OO
ILLEGAL 1,"5T
IL.LEC.AL I,"ST
ILLEGAL I"ST
RX
RK
RI
RR
RX
RK
RI
RR
RX
RK
RI
RR
Rx
RK
RI
RR
Rx
RK
RI
RR
RX
RK
RI
FiR
RX
FiK
RI
RR
RX
RK
_R I
RR
RII
RK
RI
RR
ILLEG .... 11'I5T
ILL.EGAL I"ST
ILLEGAL I,"ST
ILLEGAL l,"sT
'19
/'o(x
FiK
R1
RFi
RX
RK
RI
RR
RX
FiK
RI
RR
RX
RK
RI
RR
APPENDIX 0
MAIN MEMORY ADDRESS ALLOCATION
FUNCTION
ADDRESS
000000
000107
)
000110
CP Class III interrupt address for Store P
000111
CP Class III interrupt address for Store Status
000112
CP Class III interrupt address for Store Status :tt2
CP Cl<;lsS III interrupt address for Store RTC Lower
000113
:ttl
CP Class III interrupt address for Load P
CP Class III interrupt address for Load Status :ttl
CP Class III interrupt address for Load Status #2
CP Class III interrupt address for Store RTC Upper
000114
000115
000116
000117
CP Class II interrupt address for Store P
CP Class II interrupt address for Store Status #1
CP Class II interrupt address for Store Status #2
000120
000121
000122
000124
CP Class II interrupt address for Store RTC Lower
CP Class II interrupt address for Load P
000125
CP Class II interrupt address for Load Status
:ttl
000126
CP Class II interrupt address for Load Status
:tt2
000127
CP Class II interrupt address for Store RTC Upper
000130
CP Class I interrupt address for Store P
000131
000132
CP Class I interrupt address for Store Status :ttl
CP Class I interrupt address for Store Status #2
000133
CP Class I interrupt address for Store RTC Lower
000134
CP Class T interrupt address for Load P
000135
000136
CP Class I interrupt address for Load Status +1:1
CP Class I interrupt address for Load Status +1:2
000137
CP Class I interrupt address for Store RTC Upper
000140
10 Command Cell Location 1
000141
10 Command Cell Location 2
000123
'.
Unassigned
000142
000177
000200
}
Unassigned
Channel 0 EI Interrupt Storage
0-1
ADDRESS
FUNCTION
000202
Channel 1 EI Interrupt Storage
Channel 2 EI Interrupt Storage
000203
Channel 3 EI Interrupt Storage
000204
Channel 4 EI Interrupt Storage
Channel 5 EI Interrupt Storage
Channel 6 EI Interrupt Storage
000201
000205
000206
000211
Channel 7 EI Interrupt Storage
Channel 10 EI Interrupt Storage
Channel 11 EI Interrupt Storage
000212
000213
Channel 12 EI Interrupt Storage
Channel 13 EI Interrupt Storage
000214
Channel 14 EI Interrupt Storage
000215
Channel 15 EI Interrupt Storage
000216
Channel 16 EI Interrupt Storage
000217
Channel 17 EI Interrupt Storage
000207
000210
000220
177777
'.
D-2
)
Unassigned
APPENDIX E
DEVICE DESCRIPTIONS
This appendix contains descriptions of the logic devices used on the DPS
logic and memory circuit cards. These descriptions are a valuable aid in
understanding the logic schematic diagrams in Chapter 9 (Volume II) on
which these logic devices appear in symbolic form.
E-l
11
B+
ENA
ENB
RESA
A-
DLR
RESB
8
A+
B-
S3
VEE
ZB
ZA
A
B
13
2
GROUND PIN - 14
VOLTAGE PIN - 07
PIN NAMES
A+, A-, B+, B-
Inputs
EN A,ENB
Enables
VEE, S3
-10 Volts Supply
RES A, RES B
Terminating Resistors
ZA,ZB
Outputs
DESCRIPTION
This mtegrated circuit contains two line receivers which are designed to discriminate a
worst case logic swing of 2 volts from a ±10 volts common mode noise signal or ground
shift. Each output is enabled by a high enable (ENA or ENB). The logic configuration
is shown below.
LOGIC CONFIGURATION
Figure E-l.
E-2
Dual Line Receiver (7903776)
-
..,.
Il)
~
3
-~
2
DB
CLR
REXT
1
CEXT
DA
13
DUAL
ONE-SHOT
14
MV2
A
15
Q
,..
Q
Q
0
"
N
DA
DUAL
REXT ONE-SHOT
CEXT
U
to
DB
CLR
MV2
B
Q
.~
01
GROUND PIN - 08
VOLTAGE PIN - 16
PIN NAMES
DA
Trigger Input (Active High)
CEXT,REXT
External Timing .
DB
Trigger Input (Active Low)
Q
Output
CLR
Master Reset (Active Low)
Q
Complementary Output
DESCRIPTION
The one-shot multivibrator provides an output pulse whose duration and accuracy
depends on external timing components connected to CEXT and REXT. The
multivibrator has two trigger inputs, one active high (DA), and one active low (DB).
This allows leading edge or trailing edge triggering. When input conditions for triggering
are met, a new cycle starts and the external capacitor is rapidly discharged and then
allowed to charge. An input cycle time shorter than the output cycle time will retrigger
the multivibrator and result in a continuous true output. A LOW level at the CLR
input terminates the output pulse_
TRIGGERING TRUTH TABLE
DA
DB
CLR
Operation
L-+H
L
X
H
H-+L
X
H
H
L
Trigger
Trigger
Reset
H = High voltage level
L = Low voltage level
X = Irrelevant
H -+ L = High to low voltage level transition
L -+ H = Low to high voltage level transition
Figure E-2.
Dual One-Shot Multivibrator (7903777)
E-3
A1
1
....
M
N
M
~
DDC
A
1 OF 4
DECODER
EN
Z2
l
Z3
•
,....
to
A1
AD
Z1
15
...
•
"""
DDC
B
Z3
Z2
Z1
U
C
U
Ol
It)
AD
10F4
DECODER
EN
ZO
I;J
"""
0
- ~
~
ZO
C,
N
GROUND PIN - 08
VOLTAGE PIN - 16
PIN NAMES
EN
Enable Inputs (Active Low)
AI,AO
Inputs
Z3, Z2, ZI, ZO
Outputs (Active Low)
DESCRIPTION
This decoder consists of two independent one-of-four decoders, each with an active
low enable. The two bit input code is translated into one-of-four mutually exclusive
active low outputs. The active low enable must be present to permit any output to be
low.
TRUTH TABLE
INPUTS
OUTPUTS
EN
Al
AO
Z3
Z2
Zl
ZO
H
L
L
L
L
X
X
L
L
H
H
L
H
L
H
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
,If
= High voltage
level
L = Low voltage level
X = Irrelevant
Figure E-3.
E-4
Dual One-of-Four Decoder (7903779)
10
11
13
14
6
5
3
2
10
11
13
D1
DO
C1
CO
B1
BO
Al
AD
D1
DO
I
C1
---0 S
15
-
QUAD
MUX
-
Q2X
E
S
14
6
5
3
CO
B1
BO
A1
QUAD
MUX
2
AD
02X
15 ---
'---\
J
r---I
I
-
r-L
NC
2
C
A
Y(LOW)
DESCRIPTION
3
D
4
E
5
F
I
6
GND
I
7
= A . B + C . D + E· F + G . H
This integrated circuit contains four two-input AND gates feeding an inverting OR
gate. When any pair of inputs to the AND gates (A and B, or C and D, or E and F, or G
and H) are high, the output of the OR gate (Y) is low.
Figure E-I0.
Four-Wide, Two-Input AND-OR Inverter (7903786)
£-11
14
20
13
2B
10
2C
12
I
11
2A
9
I
VCC
NC
L
)}
NC
1A
2Y
8
2
1B
I
3
GNO
4
lC
5
10
6
lY
l
7
Y (LOW) = A· B . C· 0
DESCRIPTION
This integrated circuit contains two four-input positive NAND gates. The NAND gate
produces a low output (Y) when all four inputs (A, B, C, and D) are high.
Figure E-ll. Buffer, Dual Four-Input Positive NAND (7903787)
E-12
MAKE NO
EXTERNAL CONNECTION
1B
14
13
.----.
X
12
1D
10
X
11
1C
1Y
9
8
I
VCC
---
""'""'-
-
J
~~l
:=LJo
-
I
:f>--
~
GND
I
1A
Y (LOW) = A . B
DESCRIPTION
2
3
4
5
6
2A
2B
2C
2D
2Y
7
+ C· D
This integrated circuit contains two two-input inverting OR gates. The inputs to each
inverting OR gate are two two-input AND gates. The inverting OR gate output (Y) is
low when both inputs (A and B or C and D) to either AND gate are high. The output is
also low when all four inputs to the AND gates are high.
Figure E-12. Dual Two-Wide, Two-Input AND-OR Inverter (7903788)
E-13
A
2
3
4
5
B
C
o
E
6
F
7
I
-
GND
L
--....-
VCC
I
14
NC
I
13
NC
12
11
H
G
I
10
NC
I
9
8
Y
Y(LOW)=A·B·C·D·E·F·G·H
DESCRIPTION
This integrated circuit contains a positive eight ·input NAND gate. The output (Y) is
low only when all eight inputs (A, B, C, D, E, F, G, and H) are high.
'.
Figure E-13. Single Eight-Input Positive NAND (7903789)
E-14
14
2D
2C
13
12
I
2B
10
11
2A
2Y
9
8
I
VCC
NC
L
C
))GND
NC
2
1A
1B
I
3
4
1C
5
6
1D
1Y
I
7
Y (LOW) = A . B . C . D
DESCRIPTION
This integrated circuit contains two four-input positive NAND gates. The output of the
NAND gate (Y) is low when all four inputs (A, B, C, and D) are high.
Figure E-14. Dual Four-Input NAND (7903790)
E-15
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
8
vee
GND
2
1A
1Y
3
2A
4
5
6
2Y
3A
3Y
7
Y (LOW) = A
DESCRIPTION
This integrated circuit contains six one-input inverting gates. The output (Y) is low
when the input (A) is high. The output is high when the input is low.
Figure E-15. Inverter Gate, Hex, One-Input (7903791)
E-16
3B
9
3A
8
3Y
10
4A
11
4B
4Y
12
13
14
vee
GND
7
6
5
4
3
2
2B
2A
2Y
1B
lA
1Y
Y (lOW) = A + B
DESCRIPTION
This integrated circuit contains four two-input positive NOR gates. The output (Y) is
low when either or both inputs (A and B) are high.
TRUTH TABLE
A
B
Y
L
L
H
H
L
H
L
H
H
L
L
L
L
H
= Low voltage level
= High voltage level
Figure E-16. Quadruple Two-Input Positive NOR (7903792)
E-17
3A
3B
3Y
4A
8
9
10
11
4B
12
4Y
13
14
GND
7
6
5
4
3
2
2B
2A
2Y
1B
1A
1Y
Y (LOW) = A· B
DESCRIPTION
This integrated circuit contains four two-input positive NAND gates. The output (Y) is
low when both inputs (A and B) are high.
Figure E-17. Quadruple Two-Input NAND Gate with Open Collector Output (7903793)
E-18
14
4B
4A
4Y
3B
3A
3Y
13
12
11
10
9
8
vee
GND
2
1B
1A
Y (LOW)
DESCRIPTION
~
3
lY
4
5
2A
28
6
2Y
7
A· B
This integrated circuit contains four two-input positive NAND gates. The output (V) is
low when both inputs (A and B) are high.
Figure E-18. Quadruple Two-Input Positive NAND (7903794)
E19
4B
13
14
4Y
4A
12
11
3B
10
3A
3Y
9
8
vee
GND
2
1B
1A
Y (LOW}
DESCRIPTION
~
3
1Y
4
5
6
2A
2B
2Y
7
A· B
This integrated circuit contains four two-input positive NAND gates. The outout (Y) is
low when both inputs (A and B) are high.
Figure E-19. Quadruple Two-Input Positive NAND Buffer (7903795)
E-20
18
6
5
4
3
7
8
20
83
SELO
22
1
B1
B2
19
BO
21
23
A2
A3
2
A1
AO
16
CR
SEL1
17
4·BIT
ALU
SEL2
CG
ALU
15
SEL3
CP
CIN
A=B ,..
MODE
Z3
G
H
13
Z1
Z2
11
14
ZO
E
F
10
PIN NAMES
9
GROUND PIN - 12
VOLTAGE PIN - 24
A3, A2, AI, AO
Word A Inputs
B3, B2, Bl, BO
Word B Inputs
SEL 0 - SEL 3
Function Selection Inputs
CRIN
Carry Input
MODE
Mode Control Input (Active Low)
Z3,Z2,ZI,ZO
Function Outputs
CR
Ripple Carry Output
CRG
Carry Generate Output (Active Low)
CRP
Carry Propagate Output (Active Low)
A=B
Word A Equals Word B
DESCRIPTION
1 his integrated circuit is a 4-bit high-speed arithmetic logic unit capable of performing
16 different arithmetic operations and 16 different logical operations depending on the
condition of the function selection inputs and the mode control inputs. The table
shows the possible operations for the adder using active low inputs.
Larger (greater than 4-bit) adders can be built by cascading the less significant CR
outputs to the more significant CR IN inputs. By using the CR G and CR P outputs in
conjunction with the Carry Lookahead Device propagation time of the ripple carry is
reduced.
A = B output goes high when outputs ZO-Z3 are high.
Figure E-20. Four-Bit Arithmetic Logic Unit (Adder) (7903799)
E-21
MODE SELECTION FOR ACTIVE LOW INPUT DATA
SELECTION
MODE=H
S
E
L
3
S
E
L
2
S
E
L
I
S
E
L
0
LOGIC MODE
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
F=A
F=AB
F=A+B
F=I
F=A+B
F=B
F=AEIlB
F=A+B
F=AB
F=AEIlB
F=B
F=A+B
F=O F=AB
F=AB
MODE=L ARITHMETIC MODE
CR IN = L
CR IN = H
(No Carry)
(With Carry)
F=A MINUS I
F=AB MINUS 1
F=AB MINUS I
F=MINUS I (2'~ comp)
F=A PLUS (A+Bl
F=AB PLUS (A+B)
F=A MINUS
B MINUS I
F=A+B
F=A PLUS (A+B)
F=A PLUS B
F=AB PLUS (A+B)
F=A+B
F=A PLUS A
F=AB PLUS A
F=AB PLUS A
F=A
F=A
F=AB
F=AB
F=ZERO
F=A PLUS (A+BL PLUS 1
F=AB PLUS (A+B) PLUS I
F=A MINUS
B
F=(A+B) PLUS 1
F=A PLUS (A+B) PLUS I
F=A- PLUS B PLUS 1
F=AB PLUS (A+B) PLUS 1
F=(A+B) PLUS 1
F=A PLUS A PLUS 1
F=AB PLUS A PLUS 1
F=AB PLUS A PLUS I
F=A PLUS 1
-
F=A
L = Low voltage level
H = High voltage level
Figure E-20. Four-Bit Arithmetic Logic Unit (Adder) (7903799) (Cont)
E-22
13
14
5
6
CG4
CP4
CIN
15
CG3
CP3
1
2
3
4
CG2
CP2
CG1
CP1
C30
CLA
CP
C20
E
9
10
CG
CARRY
LOOKAHEAD
C10
;)
11
7
I-
C
12
GROUND PIN - 08
VOLTAGE PIN - 16
PIN NAMES
CRIN
Carry Input
CGO- CG3
Carry Generate Inputs (Active Low)
CPO - CP3
Carry Propagate Inputs (Active Low)
CO, Cl, C2
Carry Outputs
CRG
Carry Generate Output (Active Low)
CRP
Carry Propagate Output (Active Low)
DESCRIPTION
This integrated circuit is a high-speed lookahead carry generator. It is used with the
4-bit arithmetic logic unit to provide high-speed lookahead over word length of more
than four bits. The lookahead carry generator accepts up to four pairs of Carry
Propagate and Carry Generate signals and a Carry Input signal and provides anticipated
carries (CO, Cl, C2) across four groups of binary adders. The Carry Propagate and
Carry Generate outputs are used for further levels of lookahead.
Figure E-21. Carry Lookahead Unit (7903800)
E-23
TRUTH TABLE
INPUTS
CR
IN
C
G
0
C
P
0
X
L
X
H
H
H
L
X
H
X
X
L
X
X
L
X
X
H
X
H
H
X
L
X
X
H
X
X
X
L
H
H
H
L
X
X
H
X
X
X
L
L
X
X
X
L
X
X
X
H
X
X
H
H
X
X
L
X
X
X
H
X
X
X
X
L
X
H
H
H
X
L
X
X
X
H
X
X
X
X
L
L
H
H
H
H
L
X
X
X
H
X
X
X
X
L
L
L
X
X
H
H
X
X
L
X
X
X
H
X
X
X
X
L
X
H
H
H
X
L
X
X
X
H
X
X
X
X
L
L
X
X
X
H
X
X
X
L
H
X
X
X
L
C
G
1
C
P
1
OUTPUTS
C
G
2
C
P
2
C
G
3
C
P
3
C
0
C
1
C
2
C
R
G
H
L
H
H
X
H
X
X
L
L
L
L
H
H
H
X
X
H
X
L
L
L
L
L
H
H
H
H
H
H
H
H
L
X
X
X
H
X
X
X
X
L
L
L
H
H
H
H
L
L
L
L
X
X
X
H
L
L = Low voltage level
H = High voltage level
X = Irrelevant
Figure E-21. Carry Lookahead Unit (7903800) (Cont)
E-24
C
R
P
H
H
H
H
L
~
~
~1.
1
9
....
-
~
S3
Ln
"
~
(Xl
I
D3
EN
D2
S2
STOR
(4)
'B
- - - 0
C)
A=B
-
'B
A Greater than B Output
A B output from one device into an A input on another device and
the A < B output into the corresponding B input permits easy expansion.
TRUTH TABLE
EN
Word A
Word B
H
L
L
L
X
Word A >
Word A <
Word A =
X
Word B
Word B
Word B
A>B
L
H
L
L
A8
OUT
A>8
IN
--
A<8
OUT
GND
A___
5 __~:,____7__J
~__
2 ____~~,____
4 __
DATA
INPUTS
DESCRIPTION
I
8
OUTPUTS
CASCADING INPUTS
This unit performs magnitude comparison of straight binary and straight binary coded
decimal (BCD) codes. Three fully decoded decisions about two 4-bit words (A, B) are
made and are externally available at three outputs.
TRUTH TABLE
COMPARING INPUTS
CASCADING INPUTS
OUTPUTS
A3,B3
A2,B2
AI,BI
AO,BO
A>B
AB
AB3
A3B2
A2BI
AIBO
AO
ADDRESSABLE
ON-I
>0
LATCH
L
QN-I
>0
H
~-l
QN-I
..
..
:>
QN-I
L
QN-I
H
X = Irrelevant
L = Low Voltage Level
H = High Voltage Level
QN-l = Previous Output State
Figure E-36. Eight-Bit Addressable Latch (7904227) (Cont)
13
12
DI
...
WE
l'
2
AO
1
A1
15
A2
14
A3
i
A4
9
A5
10
4
5
RA2
A6
11
3
256
BIT
RAM
A7
....
....
CS1
~
CS2
... CS3
DO
6' A
GROUND PIN - 08
VOLTAGE PIN - 16
PIN NAMES
DI
Data Input
WE
Write Enable
AO - A7
Address Input
CSl - CS3
Memory Enable
DO
Data Output
DESCRIPTION
This device is a Read/Write memory with 256 addressable bits. The chip (memory) is
enabled when all memory enable inputs are low. The read and write operations are
controlled by the write enable when the chip is enabled. When the WR EN is law, the
DI is written into the bit location addressed by inputs AO through A 7. When the WR
EN is high, the bit location addressed by AO through A 7 is read out and placed on the
output (DO) as the complement of the data written into memory.
Figure E-37.
256-Bit Random Access Memory (7904274)
E-43
B5
B6
24
2
B4
B7
23
3
B3
B8
22
STROBE
21
4
5
B2
20
6
B1
19
7
-=-64
18
8
C
17
9
-=-16
16
10
VSS
11
X
12
Y
SR
15
14
STOP
13
DESCRIPTION
ASYNCHRONOUS OPERATION
The terminal transmitter maintains an output condition of continuous Mark bits (logic "1" or high
level) in between the transmission of characters.
The reset signal forces the transmitter into this
mode of operation for a minimum of one character
time. This state (continuous "marks" being applied
to the output line) may be termed the "idling
condition."
Data is presented to the buffer storage register by
means of the data inputs from the system of which
the terminal transmitter is a part. This data is in
the form of a character with a bit length between 5
and 8 bits. The character bit length (excluding control bits such as Start and Stop bits) is defined by
the Word Length Selector input. Parity is included
in the total number of bits making up the word
length if it is being utilized in transmission. The
input data (when stable) is strobed into the buffer
register by means of the Load Strobe. The Buffer
Empty output line indicates that new data is in the
buffer and that the system can apply a low level to
the System Ready line. This low level signal enabIes the transfer timing logic, which clears all
functional blocks except the buffer storage register, and then automatically causes a transfer of the
buffer data into the shift register.
The new character (just transferred into the shift
register) is automatically preceded by a Start bit (a
space or logic "0") and serially transmitted to the
modem as an NRZ waveform at the programmed
bit rate. The internal timing counter keeps track of
the character position in the shift register, provides
timing control to the sequence control logic for
insertion of parity (if internal parity is selected)
into the last bit position of the character, and adds
the Stop bit or bits. The number of Stop bits being
added is determined by the 2nd Stop Bit Selector
line which specifies one or two Stop bits. The
transmission of the character and control bits
(Start and Stop bits) is now complete, and the
sequence control logic either returns the transmitter to the "idling condition" and places Marks
on the output line or begins a new cycle. The new
cycle automatically begins if a new character has
been strobed into the buffer storage register (Buffer Empty output is low) and a low level is applied
to the System Ready line.
The bit rate of the transmitted data is determined
by the input frequency of the clock at the oscillator input and by the divide ratio of the counter
in the internal clock generator. Three counter
ratios are available: 71, .;.-16 and 764. These provide compatibility with the oscillator required for
the terminal receiver. The chip reset is achieved
Figure E-38. P-Channel MOS Terminal Transmitter (7904275)
E-44
when both the -;-16 Enable and the -;.-64 Enable are
high. The reset function will clear the internal
counters and shift register to prevent extraneous
data from being placed upon the output line.
SYNCHRONOUS OPERATION
Data is presented to the buffer storage register by
means of the data inputs from the system of which
the terminal transmitter is a part. This data is in
the form of a character with a bit length between 5
and 8 bits. The character bit length (including
parity if applicable) is defined by the Word Length
Selector input. The input data is strobed into the
buffer register by means of the Load Strobe and
the Buffer Empty output line then indicates that
new data is in the buffer. When the last bit of the
previous character is placed on the output line, the
transfer timing logic clears all functional blocks
except the buffer storage register and then automatically causes a transfer of the buffer data into
the shift register. The new character Uust transferred into the shift register) is serially transmitteli
to the modem as an NRZ waveform at the programmed bit rate. The internal timing counter
keeps track of the character position in the shift
register and provides timing control to the
sequence control logic for insertion of parity (if
internal parity is selected) into the last bit position
of the character. The last bit of the character is
now present at the output and sequence control
logic will initiate a new cycle automatically. The
new cycle results in the transmission of the next
character if a new character has been strobed into
the buffer storage register (Buffer Empty output is
low) or a character length of all Marks if no new
character has been stored. Thus, character sync is
maintained even though an interruption appears in
the data stream.
The bit rate of the transmitted data is determined
by the input frequency of the clock at the oscillator input and by the divide ratio of the counter
in the internal clock generator. Three counter
ratios are available: -;-1, 716 and -;-64. These provide compatibility with the oscillator required for
the terminal receiver. The chip reset is achieved
wheh both the -;.-16 Enable and the -;.-64 Enable are
high. The reset function will clear the internal
counters and shift register to prevent extraneous
data from being placed upon the output line.
INPUTS
Data Inputs - Characters of differing bit lengths
(from 5 to 8 bits including parity bit, if desired)
may be entered in parallel in right justified bit positions by means of the eight Data Inputs. The data
is strobed into a set of buffer latches where it is
stored until transmitted. Unused Data Inputs must
be maintained in the high state. (There is no inversion of the data within the Circuit; therefore a high
input will he transmitted as a high output.)
Load Strobe - A high level on the Load Strobe
traItsfers the input character on the Data Inputs
into the Storage Buffer latches and resets the
Buffer Empty latch.
Internal Parity - A high level applied to the Internal Parity input causes the transmitter Parity Generator to replace the trailing bit of a character of
any selected word length with an internally generated parity bit. A low level causes the trailing bit to
be transmitted as loaded from the inputs.
Even Parity - When a high level is applied to both
the Internal Parity and the Even Parity inputs, the
Parity Generator places the proper bit value in the
trailing bit position of a character to insure that
the total number of high levels is even. Odd parity
is formed by using a low level on the Even Parity
input.
2nd Stop Bit Select - A high level on the Stop Bit
Select input causes two STOP bits to be transmitted in the asynchronous mode. A low level will
cause one STOP bit to be transmitted. This function is disabled in the synchronous mode.
tion of START and STOP bits, and causes MARK
bits to appear on the output terminal between the
transmission of characters. A low level on this line
shortens the word length by the two or three control bits (START, STOP) and allows for automatic
recycling to either transmit the next character or a
character length of MARK bits.
System Ready - This input allows control of the
device by the external system. A low le'lel releases
Figure E-38. P-Channel MOS Terminal Transmitter (7904275) (Cant)
E-45
Asynchronous Mode - A high level on the Asynchronous Mode input enables the device for operation in the asynchronous mode, causes the generathe transmitter for the next transmission cycle.
This signal is normally applied after the Buffer
Register has been loaded (Buffer Empty output is
low). The low level should be maintained until the
next cycle is initiated (the Buffer Empty output
goes high), then made high until the next Data
Strobe.
External Clock - This is the oscillator input that
controls the transmission rate of the Terminal
Transmitter.
Word Length Selector - Two inputs (X, Y) define
the character bit length. The following truth table
defines the character length for each input combination. (Unused Data Inputs must be maintained in
the high state. This may be accomplished by
leaving the unused inputs open.)
X
Y
I
I
I
0
I
0
0
0
WORD LENGTH
8
7
6
5
bits
bits
bits
bits
';'-16 and .;-64 Counter Enables - These two Enable
inputs provide compatibility with the oscillator frequency being utilized for the Terminal Receiver,
according to the following table:
+16
+64
0
1
0
1
0
0
I
I
OSCILLA TOR FREQUENCY AT
THE EXTERNAL CLOCK INPUT
= Bit Rate
= 16 x Bit
= 64 x Bit
Rate
Rate
Master Reset
OUTPUTS
Data Output - This output transmits data in serial
fashion with START and STOP bits (if applicable).
The START bit is a SPACE (low level), the data is
transmitted in positive logic, and the STOP bit or
bits are MARK (high level).
Buffer Empty - A high level on the Buffer Empty
output indicates that the data previously stored in
the Buffer Storage latches has been transferred into
the Shift Register and the latches are available for
new data. The Load Strobe input automatically
resets this output during the load cycle.
Figure E-38. P-Channel MOS Terminal Transmitter (7904275) (Cont)
E-46
WORD
LENGTH
SELECTOR
X
2nd STOP BIT
SELECT
Y
C) 12
11 (
,
13 ()
-;-64
ENABLE
LOAD
STROBE
C) 16
014
,
,
PARITY
GENERATOR
STOP BIT
GENERATOR '.
•
....
SEQUENCE
CONTROL
-
....7
-
EXTERNAL 8
CLOCK
0--.
ASYNCHRONOUS
MODE
17 )
9
ENABLE
EVEN
PARITY
,
INTERNAL TIMING
(BIT COUNTER)
-;-16
INTERNAL
PARITY
~
INTERNAL
CLOCK
GENERATOR
I
I
I
I
I
-
J
19
-" DATA
OUT
SHIFT REGISTER
I
I
I
I
21
....
-
VGG = PIN 4
VSS = PIN 10
VDD- PIN 18
I
I
I
I
START BIT
LOGIC
I
I
I
I
I
I
TRANSFER
TIMING
I
I
A
22() 23
C
B8
B7
•
~
24
C)
B6
1
C)
B5
2
C)
B4
3 (
B3
SYSTEM
READY
20 BUFFER
-'"
EMPTY
BUFFER STORAGE
•
15
~
•
5C)
60
B2
B1
8 DATA INPUTS
Figure E-38. P-Channel MOS Terminal Transmitter (7904275) (Cont)
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
DESCRIPTION
ASYNCHRONOUS OPERATION
The function of the terminal receiver is to respond
to input data and synchronize with that data. The
normal state of the data line during the time when
no character is being transmitted is the Mark state.
The initial change in state of this line occurs upon
receipt of the Start bit. This "Mark-to-Space"
transition (of the Start bit) causes the internal
clock genera tor to be initialized for synchronization of the internal clock with the data. The data
line is continuously monitored until the internal
clock signal is generated at the midpoint of the
Start bit period. This assures the presence of a valid
Start bit. The synchronizing logic is then disabled
until the complete character (following the Start
bit) is received. If the data line returns to the Mark
state (as in the case of noise) during the monitoring
period, the bit is ignored and the terminal receiver
resumes looking for a valid St..rt bit.
After the Start bit has been detected and the
synchronization accomplished, data is shifted
through the shift register and the Start bit appears
in the Start bit flip-flop (the last stage of the shift
register). The complete character is now stored in
the shift register and the receiver automatically
generates a itansfer command to load the character
in the buffer storage register. At the same time, the
state of the Stop bit flip-flop is monitored to verify
the presence of a Stop bit. Its absence results in an
elTor output called Break being stored in the
receiver status register.
As the character shifts through the shift register,
parity for the character is accumulated. The resulting parity bit condition is compared with correct
parity (odd or even) and, in the case of error,
Parity Error is stored in receiver status register.
When the character is transferred to the buffer
storage register, a Buffer Full signal is stored in the
receiver status register. If the transfer occurs during
a full buffer condition, the old character is lost and
an error signal called Overrun is stored in the
receiver status register. The receiver status information is retained throughout the character time until
a new character is received and the new status is
stored.
The access of data in the buffer storage register by
means of the Data Strobe resets the buffer status
output, indicating that the last character stored in
the buffer storage register has been taken by the
system.
The internal clock generator divides the bit time
for each data bit into 16 or 24 segments, depending upon the externallY' selected ratio. A single
cycle of the oscillator input signal is gated out of
Figure E-39. P-Channel MOS Terminal Receiver (7904276)
E-48
the clock generator at the center of a bit. This
pulse is the internal clock signal which samples the
data and provides the internal timing for the entire
terminal receiver. The clock generator and
synchronization circuitry can be bypassed by a low
level on both the -;-16 Enable and the -;-64 Enable.
In this case, the oscillator input signal becomes the
internal clock.
times are averaged; therefore, signal noise pulses or
other data aberrations do not cause the receiver to
completely lose bit synchronization. This feature is
particularly important in synchronous transmission
because of the problem of maintaining character
synchronization and the necessity of re-establishing
character synchronization whenever bit synchronization is lost.
A master reset is provided by means of these same
two clock enable lines. When both the ';'-16 Enable
and the -;-64 Enable are at a high level, the chip is
held in a master reset condition.
Character synchronization is performed external to
the terminal receiver by means of a sequence of
comparisons between the received data and a
synchronization code (e.g., "Syn") or set of
synchronization codes. The terminal receiver is
designed to facilitate this external character
synchronization in the following manner. When the
"Syn" Detected input is low and the receiver is
operating in the synchronous mode, the buffer
storage register is "transparent" so that data can be
monitored as it ripples through the shift register.
After the first sync code has been detected, the
"Syn" Detected signal is applied, which returns the
buffer storage register to its normal mode of operation and initializes the character counter. The
second character in the sync detection sequence is
then transferred automatically to the buffer
storage register when complete. This character is
then accessed for verification as a sync code. Theprocess is repeated until it has been determined
that character synchronization has been achieved.
(If the required sync code is not present in the
buffer storage register during the synchronization
comparison, the "Syn" Detected signal is removed
and the process starts over.) Once the synchronization sequence is complete, the external sync comparison logic is disabled and the incoming data
message is processed as data.
SYNCHRONOUS OPERATION
Synchronous data transmission has several characteristics which require special consideration in the
sy nchroniza tion of incoming data with the
receiving system. Synchronous data appears as a
continuous bit stream with no interval between
characters and no control bits (Start and Stop
bits). Therefore, synchronization must be accomplished by means of the regular characteristics of
the data itself. Two degrees of synchronization are
required in order to receive a valid message. These
are bit synchronization (which synchronizes the
internal clock of the receiving system to the data
bits) and character synchronization (which establishes a character reference by means of sync codes
and utilizes the fixed bit length of the characters to
maintain character synchronization).
The technique of bit synchronization provided in
the terminal receiver for the synchronous mode of
operation utilizes each "Mark-to-Space" transition
of the data. The data transition causes an incremental correction of the internal clock timing of
1/32 or 1/128 of the bit time (depending upon the
counter ratio selected, .;-16 or ~64). The process
of incrementing the clock with respect to the data
continues with each Mark-to-Space transition of
the data until the clock signal occurs at the midpoint of the data bit. The synchronization logic
continuously attempts to correct the phase error
between the midpoint of the data bit and the internal clock. This results in the internal clock maintainiJig lock within 0.8% of the reference (764
clock model). The advantage of this technique is
that the data transition (Mark-to-Space transition)
As the character shifts through the shift register
(bypassing the Stop bit flip-flop), parity for the
character is accumulated. The resulting parity bit
condition is compared with correct parity (odd or
even) and, in the case of error, Parity Error is
stored in the receiver status register.
When the character is transferred to the buffer
storage register, a Buffer Full signal is stored in the
receiver status register. If the transfer occurs during
a full buffer condition, the old character is lost and
an error signal called Overrun is stored in the
Figure E-39. P-Channel MOS Terminal Receiver (7904276) (Cont)
E-49
receiver status register. The receiver status information is retained throughout the character time until
a new character is received and a new status word
is stored.
The access of data in the buffer storage register by
means of the Data Strobe resets the buffer status
output, indicating that the last character stored in
the buffer storage register has been taken by the
system.
The internal clock generator divides the bit time
for each data bit into 16 or 64 segments depending
upon the externally selected ratio. A single cycle of
the oscillator input signal is gated out of the clock
generator at the center of a bit. This pulse is the
internal clock signal which samples the data and
provides the internal timing for the entire terminal
receiver. The clock generator and synchronization
circuitry can be bypassed by a low level on both
the -;'-16 Enable and the .;.-64 Enable. In this case,
the oscillator input signal becomes the internal
clock.
A master reset is provided by means of these same
two clock enable lines. When both the ';'-16 Enable
and the -;-64 Enable are at a high level, the chip is
held in a master reset condition.
INPUTS
All inputs are in tern ally compensated (20 k n to
VSS for improved compatibility with TTL. The
internal compensation biases unused inputs to VSS
(high state).
Data Input - The serial data from the modem or
other sources is entered into the Terminal Receiver
by means of this terminal. The data is not inverted
within the receiver and appears at the output in the
same sense as it enters.
Data Strobe - The Buffer Storage latches are sampled whenever a high level is applied to the Data
Strobe input. The Data Strobe may be maintained
in the high state.
Status Enable - The latches of the Receiver Status
Register are sampled whenever a high level is
applied to the Status Enable line. The Status
Enable may be maintained in the high state.
Even/Odd Parity - A high level on the Even/Odd
Parity input causes a check for an even number of
high-level data bits, including the parity bit. A low
level checks for odd parity in a similar manner.
There is no provision to inhibit the Parity Check
logic for "no parity" data transmission.
Word Length Selector - Two input lines (X, Y) are
provided to define the character bit length. A character always appears at the output in a right justified bit position for the selected word lengths. The
following table shows the character length for each
input combination.
X
Y
WORD LENGTH (INCLUDING
PARITY, IF APPLICABLE)
1
0
1
0
1
1
0
0
8 bits
7 bits
6 bits
5 bits
-;.-16 and -;.-64 Counter Enables - These two inputs
provide a means of producing the internal clock
from an oscillator that is either 16 or 64 times the
bit rate. Provision is also made to bring the already
synchronized clock from a source such as a modem
into the Terminal Receiver to act as the internal
clock. Available options are shown in the following
table.
716
764
0
I
0
1
0
0
1
1
OSCILLATOR FREQUENCY AT
THE EXTERNAL CLOCK INPUT
= Bit Rate
= 16 x Bit Rate
= 64 x Bit Rate
Master Reset
External Clock Input - This is th~ oscillator input
that controls the transmission rate of the Terminal
Receiver.
Figure E-39. P-Channel MOS Terminal Receiver (7904276) (Cont)
E-50
Asynchronous/Synchronous Mode - A high level
on the Asynchronous/Synchronous Mode input
enables the device for operation in the asynchronous mode using control bits (STA RT and STOP).
The START bit is used to indicate the presence of
a character and for synchronization of the internal
clock with the character. The presence of a STOP
bit verifies character synchronization.
A low level on this input enables the device for
synchronous operation and disables all asynchronous logic. In the -;-16 or ~64 modes, a transition
monitor samples each "Mark-to-Space" transition
of the data, compares the -;-16/-;-.64 clock counter
state with the preferred coincidence state, and
incrementally adjusts one-half clock step toward
correct bit synchronization. In the -;-1 mode, bit
synchronization must be accomplished externally.
Character synchronization is handled externally by
detecting a series of sync characters (e.g., "SYN").
"Syn" Detected (Synchronous Mode only) - A
low level on this line holds the Buffer Storagl.Cl
Register latches open so that data ripples across the
outputs to permit external detection of sync codes
on the receiver outputs. The transition to a high
level indicates to the receiver that external logic
has determined character sync. A high level on this
input enables the system to operate in the synchronous mode by cycling in synchronization with each
character.
OUTPUTS
All used outputs require external pulldown
resistors. For TTL interfacing with a fan-out of one
(1), RL = 6.8 kS1 ±S% (see Figure I).
Data Outputs - Data is transferred to the eight
parallel open-drain outputs from the Buffer
Storage Register latches. The outputs are enabled
by an input signal to the Data Strobe input and
provide bussing capability. For character lengths of
5 to 8 bits, data appears in a right justified position.
Serial Output - The data being shifted into the
shift register is simultaneously available at the
Serial Output. This provides a means for externally
accumulating longitudinal parity.
Receiver Status Outputs - Status information is
provided by means of four open-drain outputs.
These outputs are enabled by the Status Enable
input for bussing capability. The functions of these
Status outputs are:
1. Buffer Full - This output shows that a
character is in the Buffer Storage latches and has
not been sampled at the eight data outputs by
using the Data Strobe input. The Data Strobe signal automatically resets the Buffer Full output. If
the Data Strobe input is maintained in the high
state, the Buffer Full output appears as a pulse.
2. Overrun - This output provides an indication that two or more characters have been transferred into the Buffer Storage Register latches in
succession without an intervening sampling of the
buffer contents by use of the Data Strobe. This
means that at least one character has been lost. Use
of the Data Strobe removes this indicator after the
transfer of the next character into the Buffer
Storage Register.
3. Parity Error - Incorrect parity for a particular character causes an error signal (high level)
to be generated and made available at the Parity
Error output for the period that the character is
present in the Buffer Storage Register.
4. Break (Asynchronous Mode only) - The
absence of a STOP bit following the character
causes a Break signal to be stored in the Receiver
Status Register for the character time.
Clock Output - The internal clock that has been
synchronized with the data is available for external
use by means of this output.
Figure E-39. P-Channel MOS Terminal Receiver (7904276) (Cant)
E-SI
EXTERN AL
CLOCK
COUNT
ENABLE S
-;-64
716
WORD
LENGTH
SELECT OR
SYNCHR ONOUS
CLOCK
SYNCHR ONIZER
EVEN/O DD
PARITY
8
INTERN AL
CLOCK
GENERA TOR
ASYNCH RONOU S
CLOCK
SYNCHR ONIZER
4
PARITY
CHECK
LOGIC
SYNC WORD
COUNTE R
18
CLOCK OUTPUT
SERIAL OUTPUT
DATA
3
7
SHIFT REGIST ER
INPUT 20
DATA
STROBE
TRANSF ER
TIMING
BUFFER STORAG E REGIST ER
6
2
ASYNCH RONOU S/
SYNCHR ONOUS MODE
"SYN" DETECT ED
VGG
VSS
VDD
~
~
~
PIN 5
PIN 12
PIN 21
...--------------
~
24
RECEIV ER STATUS
REGIST ER
---------------~
STATUS ENABLE
"'"
8 DATA OUTPUT S
23
BUFFER
FULL
PARITY
ERROR
OVERRUN
Figure E-39. P-Channel MOS Termin al Receiver (79042 76) (Cont)
BREAK
14
46
13
4A
12
4Y
11
36
10
3A
9
3Y
8
vee
GND
1A
2
3
4
5
6
16
1Y
2A
26
2Y
7
Y (LOW) = A' 6
Figure E-40. Quadruple Two-Input NAND Gate (7904292)
E-53
14
6A
6Y
5A
5Y
4A
4Y
13
12
11
10
9
8
vee
GND
1A
2
3
1Y
2A
4
2Y
5
6
3A
3Y
7
Y=A
DESCRIPTION
This integrated circuit contains six inverter circuits. A positive input (A) results in a
negative output (Y). A negative input results in a positive output.
'.,
Figure E-41. Hex Inverter (7904293)
E-54
14
20
13
2C
12
11
2B
2A
2Y
10
9
8
I
I
VCC
NC
L
}
GNO
NC
2
1A
1B
I
3
4
1C
5
10
6
I
7
1Y
Y (LOW) = A . B . C . D
Figure E-42. Dual Four-Input NAND Gate (7904296)
E-55
CLEAR
o
CLOCK
PRESET
Q
Q
13
12
11
10
9
8
14
I
VCC
!
-
PR
~
b
CK
CLR
•
1
D
r0-
Q
Q
-
2
Q
CK
0
-
L
Q
CLR
r
-
PR
I
L...-
GNO
CLEAR
DESCRIPTION
2
3
4
5
o
CLOCK
PRESET
Q
6
Q
This integrated circuit contains two D type flip-flops with direct clear and preset inputs
and both Q and Q outputs. Information at the D input is transferred to the outputs on
the positive edge of the clock pulse. The function table shows the outputs for each
input. The preset and clear inputs are independent of the clock. A Iowan the preset
input sets Q to a high. A Iowan the clear input sets Q to a low. A low on both inputs
sets Q and Q to a high. This is an unstable condition.
TRUTH TABLE
PRESET
L
H
L
H
H
H
L
H
X
t
Qo
*
INPUTS
CLEAR
CLOCK
H
L
L
H
H
H
X
X
X
t
t
L
D
OUTPUTS
Q
Q
X
X
X
H
L
X
H
L
H*
H
L
Qo
L
H
H*
L
H
Qo
= Low voltage level (steady state)
= High voltage level (steady state)
= Irrelevant
= Transition from low to high level
= The level of Q before the indicated input conditions were established
= This configuration is not stable; that is, it will not persist when preset
and clear inputs return to their inactive (high) level.
Figure E-43. Flip-Flop, Dual D (7904298)
E-56
I
7
7
G
F
6
5
E
4
o
3
C
2
A
1
I
GND
n
Y (LOW) = A . B + C . 0 + E . F . G + H . I + X + X
DESCRIPTION
This integrated circuit contains an inverting OR gate which has three two-input AND
gates and one three-input AND gate for inputs. The output (V) of the OR gate is low
when at least one of the AND gate outputs is high. The AND gate output will be high
when all the inputs to the AND gate (A and B, or C and D, or E, F, and G, or H and I)
ar~ high. T~ output of the OR gate will also be low when the X input to the gate is
high or the X input is low.
Figure E-44.
Single 2-2-2-3 Input AND-OR Inverter (7904418)
E-S7
8
28
2A
18
1A
2Y
1Y
7
6
5
4
3
2
veCl
VEE
veC2
9
10
11
12
13
14
15
4Y
3A
38
4A
48
3Y
4Y
Y (LOW)
DESCRIPTION
~
16
A +8
This integrated circuit contains four two-input inverting OR gates. The output (Y) will
be low when either or both inputs (A and B) are high. Pin 9 is an inverted signal of pin
15.
Figure E-45. Quadruple Two-Input NOR (7904474)
E-58
8
2A
7
B
6
1A
1Y
5
4
2Y
3
1Y
2Y
2
I
VEE
I
Ii-
\"'-"C
\d
"'"--1
vee
I
9
GND
10
4A
11
3A
12
13
4Y
3Y
14
15
3Y
4Y
I
16
Y =A· B
DESCRIPTION
This integrated circuit contains four TTL TO ECL translators. The output (Y) will be
high when both inputs (A and B) to the AND gate are high. At the same time the
output (Y) will be low.
TRUTH TABLE
INPUT
A B
OUTPUT
Y
Y
L
L
H
H
L
L
L
H
L
H
L
H
H
H
H
L
L = Low voltage
H = High voltage
Figure E-46. Translator-Quad, TTL to ECL (7904477)
E-S9
2B
8
7
2A
6
2Y
5
1Y
1B
1A
4
3
2
VBS
VEE
vee
9
GND
10
11
12
13
14
15
3A
38
3Y
4Y
4A
48
16
Y=A+B
DESCRIPTION
This integrated circuit contains four ECL to TTL translators. Either input A or B will
be connected to the translator. If A is connected, the output (Y) is high when the
input (A) is low. If B is connected, the output (Y) is high when the input (B) is high.
The VBB bins voltage input at pin I is intended for use of the circuit as a Schmitt
trigger; it is not used in the DPS.
Figure E-47. Translator-Quad, ECL to TTL (7904478)
E-60
VCCE
C1
81
6
5
8
D1
7
9
10
11
12
A2
82
C2
A3
DESCRIPTION
Y2
VCC1
2
1
A1
4
Y1
3
13
83
14
15
16
C3
Y3
VCC2
This integrated circuit contains three inverting OR gates. Two of the OR gates have
three inputs and the other one has four inputs. A high signal on any or all of the inputs
(A, B, C, D) to a gate produces a low output (Y) from that gate.
Figure E-48. Triple 4-3-3 Input NOR Gate (7904706)
E-61
8
7
6
5
4
VEE
B2
A2
B1
A1
3 .
Y2
Y1
veC1
VBB
A3
10
B3
11
A4
12
B4
Y3
Y4
13
14
15
veC2
16
9
DESCRIPTION
This integrated circuit contains four line receivers. The line receiver produces an output
(Y) when it senses a differential voltage on the inputs (A and B). The VBB bias voltage
input at pin I is intended for use of the circuit as a Schmitt trigger; it is not used in the
DPS.
Figure E-49. Quadruple Line Receiver (7904707)
E-62
2
8
7
6
I
2
3
4
5
I
II
VEE
VCC1
I
C
K1
-
R1
J1
51
-
-
01
01
I
I
I
K2
C
J2
R2
52
-
02
02
VCC2
I
9
DESCRIPTION
I
12
11
10
-
13
15
14
I
16
This integrated circuit is a dual master-slave dc coupled J-K flip-flop. Asynchronou<;
set (S) and reset (R) are provided. The set and reset inputs override the clock.
A common clock is provided with separate J-K inputs. When the clock is static, the J-K
inputs do not affect the output.
The output sta tes of the flip-flop change on the positive transition of the clock.
TRUTH TABLE (R-S)
'.
TRUTH TABLE (J-K)
-
-
R
S
QnH
J
K
Qn+l
L
L
H
H
L
H
L
H
Qn
H
L
N'D'
L
L
H
H
L
H
L
H
Qn
L
H
Qn
=
L
H =
N'D' =
Qn =
Qn =
Low voltage
High voltage
Not defined
Output
Inverted output
-
Output states change on
posi!!ve !!ansition of clock
for J. K input condition
present.
Figure E-50. Dual J-K Master Slave Flip-Flop (7904708)
E-63
15
14
1
lG
"-v-' \
E,\lABLE
-
2B
2\
I
13
2
3
1A
1B
V
I
2YO
2Y1
12
11
4
5
lYO
lYl
-
~
~
A
J
-
-
~
2A
16
DATA OUTPUTS
,..__________
____________
SELECTA_____
INPUTS
~
ENABLE
r--..::-"
2G
2Y2
2Y3
10
9
6
7
,
8
lY2
1Y3
_ _ _ _ _....JI
\~-----------""V,..-
SELECT INPUT
DATA OUTPUTS
TRUTH TABLE
INPUTS
ENABLE
SELECT
'.
OUTPUTS
G
B
A
YO
YI
Y2
Y3
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H = High Level
L = Low Level
X = Irrelevant
Figure E-51. Dual 2 to 4 Line Decoder (7904773)
E-64
2C
14
13
12
11
28
2A
2Y
10
9
8
VCC
GND
2D
2
3
4
5
6
1A
1B
1C
10
1Y
Y (LOW) = A· B + C . D
DESCRIPTION
7
NC = NO CONNECTION
This integrated circuit contains two two-input inverting OR gates. The input to the
inverting OR gates are two two-input AND gates. The inverting OR gate output (Y) is
low when both inputs (A and B, or C and D) to either AND gate are high.
Figure E-52. Dual AND-OR Inverter Gate (7904774)
E65/(E-66 blank)
GLOSSARY OF TERMS AND ABBREVIATIONS
DEFINITION
TERM
ADRS
Address
ADV
Advance
ALU
Arithmetic/Logic Unit: An adder that is also capable
of performing logic functions.
Asynchronous
Not Synchronous
BAP
Buffer Address Pointer
Baud
The number of code elements per second.
BCW
Buffer Control Word
bps
Bits per second
Breakpoint
A point for breaking off program operation. The DPS
stops upon J~:aching any address placed into the breakpoint register.
byte
A group of bits handled as a unit; DPS words may be
handled as two 8-bit bytes.
C
Centigrade
CAP
Chain Address Pointer
Chip
An integrated circuit semiconductor device. Usually
refers to the complete package, although theoretically
referring to the semiconductor device within the package.
CLh:
Clock
CLR
Clear
CM
Control Memory
CORDIC
Coordinate Rotation Digital Computer; a technique for
handling trigonometric and hyperbolic computations.
CP/IO
Central Processor and Input-Output sections of the DPS.
'.DIP
DMA
Dual-in-line package; a rectangular semiconductor
package with leads arranged in two parallel rows.
Direct Memory Access
Glossary 1
GLOSSARY OF TERMS AND ABBREVIATIONS (CONT)
TERM
l)EFINITION
DPS
l)ata Processing Set
l)SPL
lJisplay
ECW
Emulator Control Word
EFA
External Function Acknowledge
EFR
External Function Request
EIA
Electronics Industries Association
EIE
External Interrupt Enable
EIR
External Interrupt Request
Emulator
The portion of a microprogram controlled processor that
adapts it to perform specific functions.
EN
Enable
ESA
Externally Specified Address
ExOR
Exclusive OR
F
Fahrenheit
F-field
Format code field of macroinstruction word or function
code field of microinstruction word~
Firmware
Unchangeable internal program; distinguished from
hardware or changeable software.
Full l)uplex
Data transmission in both directions simultaneously.
GENL
General
Half Duplex
Data transmission in only one direction at a time;
also called simplex.
Hz
Hertz:
lAW
Indirect Address Word
IC
Integrated Circuit
Glossary 2
cycles per second
GLOSSARY OF TERMS AND ABBREVIATIONS (CONT)
DEFINITION
TERM
IC Channel
Intercomputer Channel
IDA
Input Data Acknowledge
IDR
Input Data Request
IECF
Input Enable Control Frame
Indirect Addressing
A scheme in which a referenced address contains a
coded word causing the referencing of another address,
INST or INSTR
Instruction
I/O
Input/Output
IOC
Input/Output Controller
!RCF
Input Request Control Frame
LED
Light Emitting Diode
LRI
Lowest Replaceable Item
LSB
Least Significant Bit
MA CLR
Master Clear
Macro Instruction
Instruction used by processor/emulator.
Macroprogram
Program of macro instructions stored in main memory.
Micro Instruction
Instruction used by MPC.
Microprogram
Program of micro instructions stored in micro memory.
MPC
Microprogrammed Controller
ms
Millisecond:
MSB
Most Significant Bit
NDRO
Nondestructive Readout Memory
1
1000 second
No Operation
Normalize
To scale the mantissa of a floating point quantity
the first significant bit adjoins the sign bit and
adjust the exponent accordingl~
S0
Glossary 3
GLOSSARY OF TERMS AND ABBREVIATIONS (CONT)
TERM
DEFINITION
1
1,000,000,000
ns
Nanosecond:
NTDS
Naval Tactical Data System
OUA
Output Data Acknowledge
ODR
Output Data Request
OECF
Output Enable Control Frame
ORCF
Output Request Control Frame
Paging
A system of virtual memory or relative memory addressing in which the memory is divided into groups of
addresses called pages which may be interchanged under
program con tro!.
P Register
Program Address Register
PROM
Programmable Read Only Memory
PT
Point
Real Time
A term applied to processing operations that can be
interrupted or controlled by events outside the system,
and that can react with sufficient speed to analyze or
control the external events.
Reg
Register
ROM
Read Only Memory
RTC
Real Time Clock
Scale
See Normali ze
Simplex
Transmission in one direction only; also called half
duplex.
Software
Data Processing Programs
Sync
See Synchronous
Synchronous
Operating at a clocked rate.
Glossary 4
second
GLOSSARY OF TERMS AND ABBREVIATIONS (CONT)
DEFINITION
TERM
TM
Transfer Mode
TP
Tes t Point
f.!.I
Micro Instruction
Micro Memory
Micro Program
Microsecond:
Virtual Memory
(also called
relative addressing)
~~l~~ second
1,000,000
A memory addressing system in which programs or data
may be placed in different addresses, but appear to the
program as though they were located in the true (virtual)
addresses. Usually accomplished by modifying the address wi~h a changeable base address. See paging.
Glossary 5!(Glossary 6 blank)
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