STM32F411xC/E Advanced Arm® Based 32 Bit MCUs STM32F411 MANUAL
STM32F411_MANUAL
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- 1 Documentation conventions
- 2 Memory and bus architecture
- 3 Embedded Flash memory interface
- 3.1 Introduction
- 3.2 Main features
- 3.3 Embedded Flash memory in STM32F411xC/E
- 3.4 Read interface
- 3.5 Erase and program operations
- 3.6 Option bytes
- 3.7 One-time programmable bytes
- 3.8 Flash interface registers
- 4 CRC calculation unit
- 5 Power controller (PWR)
- 5.1 Power supplies
- 5.2 Power supply supervisor
- 5.3 Low-power modes
- 5.4 Power control registers
- 5.5 PWR register map
- 6 Reset and clock control (RCC) for STM32F411xC/E
- 6.1 Reset
- 6.2 Clocks
- 6.3 RCC registers
- 6.3.1 RCC clock control register (RCC_CR)
- 6.3.2 RCC PLL configuration register (RCC_PLLCFGR)
- 6.3.3 RCC clock configuration register (RCC_CFGR)
- 6.3.4 RCC clock interrupt register (RCC_CIR)
- 6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
- 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
- 6.3.7 RCC APB1 peripheral reset register for (RCC_APB1RSTR)
- 6.3.8 RCC APB2 peripheral reset register (RCC_APB2RSTR)
- 6.3.9 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
- 6.3.10 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
- 6.3.11 RCC APB1 peripheral clock enable register (RCC_APB1ENR)
- 6.3.12 RCC APB2 peripheral clock enable register (RCC_APB2ENR)
- 6.3.13 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)
- 6.3.14 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR)
- 6.3.15 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)
- 6.3.16 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)
- 6.3.17 RCC Backup domain control register (RCC_BDCR)
- 6.3.18 RCC clock control & status register (RCC_CSR)
- 6.3.19 RCC spread spectrum clock generation register (RCC_SSCGR)
- 6.3.20 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
- 6.3.21 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
- 6.3.22 RCC register map
- 7 System configuration controller (SYSCFG)
- 7.1 I/O compensation cell
- 7.2 SYSCFG registers
- 7.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)
- 7.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)
- 7.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 7.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 7.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 7.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 7.2.7 Compensation cell control register (SYSCFG_CMPCR)
- 7.2.8 SYSCFG register map
- 8 General-purpose I/Os (GPIO)
- 8.1 GPIO introduction
- 8.2 GPIO main features
- 8.3 GPIO functional description
- Figure 16. Basic structure of a five-volt tolerant I/O port bit
- Table 23. Port bit configuration table (continued)
- 8.3.1 General-purpose I/O (GPIO)
- 8.3.2 I/O pin multiplexer and mapping
- 8.3.3 I/O port control registers
- 8.3.4 I/O port data registers
- 8.3.5 I/O data bitwise handling
- 8.3.6 GPIO locking mechanism
- 8.3.7 I/O alternate function input/output
- 8.3.8 External interrupt/wakeup lines
- 8.3.9 Input configuration
- 8.3.10 Output configuration
- 8.3.11 Alternate function configuration
- 8.3.12 Analog configuration
- 8.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
- 8.3.14 Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
- 8.3.15 Selection of RTC functions
- 8.4 GPIO registers
- 8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..E and H)
- 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..E and H)
- 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..E and H)
- 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..E and H)
- 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..E and H)
- 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..E and H)
- 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..E and H)
- 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..E and H)
- 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..E and H)
- 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..E and H)
- 8.4.11 GPIO register map
- 9 DMA controller (DMA)
- 9.1 DMA introduction
- 9.2 DMA main features
- 9.3 DMA functional description
- 9.3.1 General description
- 9.3.2 DMA transactions
- 9.3.3 Channel selection
- 9.3.4 Arbiter
- 9.3.5 DMA streams
- 9.3.6 Source, destination and transfer modes
- 9.3.7 Pointer incrementation
- 9.3.8 Circular mode
- 9.3.9 Double buffer mode
- 9.3.10 Programmable data width, packing/unpacking, endianess
- 9.3.11 Single and burst transfers
- 9.3.12 FIFO
- 9.3.13 DMA transfer completion
- 9.3.14 DMA transfer suspension
- 9.3.15 Flow controller
- 9.3.16 Summary of the possible DMA configurations
- 9.3.17 Stream configuration procedure
- 9.3.18 Error management
- 9.4 DMA interrupts
- 9.5 DMA registers
- 9.5.1 DMA low interrupt status register (DMA_LISR)
- 9.5.2 DMA high interrupt status register (DMA_HISR)
- 9.5.3 DMA low interrupt flag clear register (DMA_LIFCR)
- 9.5.4 DMA high interrupt flag clear register (DMA_HIFCR)
- 9.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7)
- 9.5.6 DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)
- 9.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)
- 9.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)
- 9.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)
- 9.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)
- 9.5.11 DMA register map
- 10 Interrupts and events
- 10.1 Nested vectored interrupt controller (NVIC)
- 10.2 External interrupt/event controller (EXTI)
- 10.3 EXTI registers
- 11 Analog-to-digital converter (ADC)
- 11.1 ADC introduction
- 11.2 ADC main features
- 11.3 ADC functional description
- 11.4 Data alignment
- 11.5 Channel-wise programmable sampling time
- 11.6 Conversion on external trigger and trigger polarity
- 11.7 Fast conversion mode
- 11.8 Data management
- 11.9 Temperature sensor
- 11.10 Battery charge monitoring
- 11.11 ADC interrupts
- 11.12 ADC registers
- 11.12.1 ADC status register (ADC_SR)
- 11.12.2 ADC control register 1 (ADC_CR1)
- 11.12.3 ADC control register 2 (ADC_CR2)
- 11.12.4 ADC sample time register 1 (ADC_SMPR1)
- 11.12.5 ADC sample time register 2 (ADC_SMPR2)
- 11.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
- 11.12.7 ADC watchdog higher threshold register (ADC_HTR)
- 11.12.8 ADC watchdog lower threshold register (ADC_LTR)
- 11.12.9 ADC regular sequence register 1 (ADC_SQR1)
- 11.12.10 ADC regular sequence register 2 (ADC_SQR2)
- 11.12.11 ADC regular sequence register 3 (ADC_SQR3)
- 11.12.12 ADC injected sequence register (ADC_JSQR)
- 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
- 11.12.14 ADC regular data register (ADC_DR)
- 11.12.15 ADC common control register (ADC_CCR)
- 11.12.16 ADC register map
- 12 Advanced-control timer (TIM1)
- 12.1 TIM1 introduction
- 12.2 TIM1 main features
- 12.3 TIM1 functional description
- 12.3.1 Time-base unit
- 12.3.2 Counter modes
- 12.3.3 Repetition counter
- 12.3.4 Clock selection
- 12.3.5 Capture/compare channels
- 12.3.6 Input capture mode
- 12.3.7 PWM input mode
- 12.3.8 Forced output mode
- 12.3.9 Output compare mode
- 12.3.10 PWM mode
- 12.3.11 Complementary outputs and dead-time insertion
- 12.3.12 Using the break function
- 12.3.13 Clearing the OCxREF signal on an external event
- 12.3.14 6-step PWM generation
- 12.3.15 One-pulse mode
- 12.3.16 Encoder interface mode
- 12.3.17 Timer input XOR function
- 12.3.18 Interfacing with Hall sensors
- 12.3.19 TIMx and external trigger synchronization
- 12.3.20 Timer synchronization
- 12.3.21 Debug mode
- 12.4 TIM1 registers
- 12.4.1 TIM1 control register 1 (TIMx_CR1)
- 12.4.2 TIM1 control register 2 (TIMx_CR2)
- 12.4.3 TIM1 slave mode control register (TIMx_SMCR)
- 12.4.4 TIM1 DMA/interrupt enable register (TIMx_DIER)
- 12.4.5 TIM1 status register (TIMx_SR)
- 12.4.6 TIM1 event generation register (TIMx_EGR)
- 12.4.7 TIM1 capture/compare mode register 1 (TIMx_CCMR1)
- 12.4.8 TIM1 capture/compare mode register 2 (TIMx_CCMR2)
- 12.4.9 TIM1 capture/compare enable register (TIMx_CCER)
- 12.4.10 TIM1 counter (TIMx_CNT)
- 12.4.11 TIM1 prescaler (TIMx_PSC)
- 12.4.12 TIM1 auto-reload register (TIMx_ARR)
- 12.4.13 TIM1 repetition counter register (TIMx_RCR)
- 12.4.14 TIM1 capture/compare register 1 (TIMx_CCR1)
- 12.4.15 TIM1 capture/compare register 2 (TIMx_CCR2)
- 12.4.16 TIM1 capture/compare register 3 (TIMx_CCR3)
- 12.4.17 TIM1 capture/compare register 4 (TIMx_CCR4)
- 12.4.18 TIM1 break and dead-time register (TIMx_BDTR)
- 12.4.19 TIM1 DMA control register (TIMx_DCR)
- 12.4.20 TIM1 DMA address for full transfer (TIMx_DMAR)
- 12.4.21 TIM1 register map
- 13 General-purpose timers (TIM2 to TIM5)
- 13.1 TIM2 to TIM5 introduction
- 13.2 TIM2 to TIM5 main features
- 13.3 TIM2 to TIM5 functional description
- 13.3.1 Time-base unit
- 13.3.2 Counter modes
- Figure 90. Counter timing diagram, internal clock divided by 1
- Figure 91. Counter timing diagram, internal clock divided by 2
- Figure 92. Counter timing diagram, internal clock divided by 4
- Figure 93. Counter timing diagram, internal clock divided by N
- Figure 94. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 95. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 96. Counter timing diagram, internal clock divided by 1
- Figure 97. Counter timing diagram, internal clock divided by 2
- Figure 98. Counter timing diagram, internal clock divided by 4
- Figure 99. Counter timing diagram, internal clock divided by N
- Figure 100. Counter timing diagram, Update event
- Figure 101. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
- Figure 102. Counter timing diagram, internal clock divided by 2
- Figure 103. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 104. Counter timing diagram, internal clock divided by N
- Figure 105. Counter timing diagram, Update event with ARPE=1 (counter underflow)
- Figure 106. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 13.3.3 Clock selection
- 13.3.4 Capture/compare channels
- 13.3.5 Input capture mode
- 13.3.6 PWM input mode
- 13.3.7 Forced output mode
- 13.3.8 Output compare mode
- 13.3.9 PWM mode
- 13.3.10 One-pulse mode
- 13.3.11 Clearing the OCxREF signal on an external event
- 13.3.12 Encoder interface mode
- 13.3.13 Timer input XOR function
- 13.3.14 Timers and external trigger synchronization
- 13.3.15 Timer synchronization
- Figure 127. Master/Slave timer example
- Figure 128. Gating timer 2 with OC1REF of timer 1
- Figure 129. Gating timer 2 with Enable of timer 1
- Figure 130. Triggering timer 2 with update of timer 1
- Figure 131. Triggering timer 2 with Enable of timer 1
- Figure 132. Triggering timer 1 and 2 with timer 1 TI1 input
- 13.3.16 Debug mode
- 13.4 TIM2 to TIM5 registers
- 13.4.1 TIMx control register 1 (TIMx_CR1)
- 13.4.2 TIMx control register 2 (TIMx_CR2)
- 13.4.3 TIMx slave mode control register (TIMx_SMCR)
- 13.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 13.4.5 TIMx status register (TIMx_SR)
- 13.4.6 TIMx event generation register (TIMx_EGR)
- 13.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 13.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 13.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 13.4.10 TIMx counter (TIMx_CNT)
- 13.4.11 TIMx prescaler (TIMx_PSC)
- 13.4.12 TIMx auto-reload register (TIMx_ARR)
- 13.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 13.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 13.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 13.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 13.4.17 TIMx DMA control register (TIMx_DCR)
- 13.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 13.4.19 TIM2 option register (TIM2_OR)
- 13.4.20 TIM5 option register (TIM5_OR)
- 13.4.21 TIMx register map
- 14 General-purpose timers (TIM9 to TIM11)
- 14.1 TIM9/10/11 introduction
- 14.2 TIM9/10/11 main features
- 14.3 TIM9 to TIM11 functional description
- 14.3.1 Time-base unit
- 14.3.2 Counter modes
- Figure 137. Counter timing diagram, internal clock divided by 1
- Figure 138. Counter timing diagram, internal clock divided by 2
- Figure 139. Counter timing diagram, internal clock divided by 4
- Figure 140. Counter timing diagram, internal clock divided by N
- Figure 141. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 142. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 14.3.3 Clock selection
- 14.3.4 Capture/compare channels
- 14.3.5 Input capture mode
- 14.3.6 PWM input mode (only for TIM9)
- 14.3.7 Forced output mode
- 14.3.8 Output compare mode
- 14.3.9 PWM mode
- 14.3.10 One-pulse mode
- 14.3.11 TIM9 external trigger synchronization
- 14.3.12 Timer synchronization (TIM9)
- 14.3.13 Debug mode
- 14.4 TIM9 registers
- 14.4.1 TIM9 control register 1 (TIMx_CR1)
- 14.4.2 TIM9 slave mode control register (TIMx_SMCR)
- 14.4.3 TIM9 Interrupt enable register (TIMx_DIER)
- 14.4.4 TIM9 status register (TIMx_SR)
- 14.4.5 TIM9 event generation register (TIMx_EGR)
- 14.4.6 TIM9 capture/compare mode register 1 (TIMx_CCMR1)
- 14.4.7 TIM9 capture/compare enable register (TIMx_CCER)
- 14.4.8 TIM9 counter (TIMx_CNT)
- 14.4.9 TIM9 prescaler (TIMx_PSC)
- 14.4.10 TIM9 auto-reload register (TIMx_ARR)
- 14.4.11 TIM9 capture/compare register 1 (TIMx_CCR1)
- 14.4.12 TIM9 capture/compare register 2 (TIMx_CCR2)
- 14.4.13 TIM9 register map
- 14.5 TIM10/11 registers
- 14.5.1 TIM10/11 control register 1 (TIMx_CR1)
- 14.5.2 TIM10/11 Interrupt enable register (TIMx_DIER)
- 14.5.3 TIM status register (TIMx_SR)
- 14.5.4 TIM event generation register (TIMx_EGR)
- 14.5.5 TIM10/11 capture/compare mode register 1 (TIMx_CCMR1)
- 14.5.6 TIM10/11 capture/compare enable register (TIMx_CCER)
- 14.5.7 TIM10/11 counter (TIMx_CNT)
- 14.5.8 TIM10/11 prescaler (TIMx_PSC)
- 14.5.9 TIM10/11 auto-reload register (TIMx_ARR)
- 14.5.10 TIM10/11 capture/compare register 1 (TIMx_CCR1)
- 14.5.11 TIM11 option register 1 (TIM11_OR)
- 14.5.12 TIM10/11 register map
- 15 Independent watchdog (IWDG)
- 16 Window watchdog (WWDG)
- 17 Real-time clock (RTC)
- 17.1 Introduction
- 17.2 RTC main features
- 17.3 RTC functional description
- 17.3.1 Clock and prescalers
- 17.3.2 Real-time clock and calendar
- 17.3.3 Programmable alarms
- 17.3.4 Periodic auto-wakeup
- 17.3.5 RTC initialization and configuration
- 17.3.6 Reading the calendar
- 17.3.7 Resetting the RTC
- 17.3.8 RTC synchronization
- 17.3.9 RTC reference clock detection
- 17.3.10 RTC coarse digital calibration
- 17.3.11 RTC smooth digital calibration
- 17.3.12 Timestamp function
- 17.3.13 Tamper detection
- 17.3.14 Calibration clock output
- 17.3.15 Alarm output
- 17.4 RTC and low-power modes
- 17.5 RTC interrupts
- 17.6 RTC registers
- 17.6.1 RTC time register (RTC_TR)
- 17.6.2 RTC date register (RTC_DR)
- 17.6.3 RTC control register (RTC_CR)
- 17.6.4 RTC initialization and status register (RTC_ISR)
- 17.6.5 RTC prescaler register (RTC_PRER)
- 17.6.6 RTC wakeup timer register (RTC_WUTR)
- 17.6.7 RTC calibration register (RTC_CALIBR)
- 17.6.8 RTC alarm A register (RTC_ALRMAR)
- 17.6.9 RTC alarm B register (RTC_ALRMBR)
- 17.6.10 RTC write protection register (RTC_WPR)
- 17.6.11 RTC sub second register (RTC_SSR)
- 17.6.12 RTC shift control register (RTC_SHIFTR)
- 17.6.13 RTC time stamp time register (RTC_TSTR)
- 17.6.14 RTC time stamp date register (RTC_TSDR)
- 17.6.15 RTC timestamp sub second register (RTC_TSSSR)
- 17.6.16 RTC calibration register (RTC_CALR)
- 17.6.17 RTC tamper and alternate function configuration register (RTC_TAFCR)
- 17.6.18 RTC alarm A sub second register (RTC_ALRMASSR)
- 17.6.19 RTC alarm B sub second register (RTC_ALRMBSSR)
- 17.6.20 RTC backup registers (RTC_BKPxR)
- 17.6.21 RTC register map
- 18 Inter-integrated circuit (I2C) interface
- 18.1 I2C introduction
- 18.2 I2C main features
- 18.3 I2C functional description
- 18.4 I2C interrupts
- 18.5 I2C debug mode
- 18.6 I2C registers
- 18.6.1 I2C Control register 1 (I2C_CR1)
- 18.6.2 I2C Control register 2 (I2C_CR2)
- 18.6.3 I2C Own address register 1 (I2C_OAR1)
- 18.6.4 I2C Own address register 2 (I2C_OAR2)
- 18.6.5 I2C Data register (I2C_DR)
- 18.6.6 I2C Status register 1 (I2C_SR1)
- 18.6.7 I2C Status register 2 (I2C_SR2)
- 18.6.8 I2C Clock control register (I2C_CCR)
- 18.6.9 I2C TRISE register (I2C_TRISE)
- 18.6.10 I2C FLTR register (I2C_FLTR)
- 18.6.11 I2C register map
- 19 Universal synchronous asynchronous receiver transmitter (USART)
- 19.1 USART introduction
- 19.2 USART main features
- 19.3 USART functional description
- Figure 167. USART block diagram
- 19.3.1 USART character description
- 19.3.2 Transmitter
- 19.3.3 Receiver
- 19.3.4 Fractional baud rate generation
- Table 73. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz, oversampling by 16
- Table 74. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK =12 MHz, oversampling by 8
- Table 75. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz, oversampling by 16 (continued)
- Table 76. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz, oversampling by 8
- Table 77. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 16
- Table 78. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 8 (continued)
- Table 79. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 16 (continued)
- Table 80. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 8 (continued)
- Table 81. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz, oversampling by 16 (continued)
- Table 82. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz, oversampling by 8 (continued)
- 19.3.5 USART receiver tolerance to clock deviation
- 19.3.6 Multiprocessor communication
- 19.3.7 Parity control
- 19.3.8 LIN (local interconnection network) mode
- 19.3.9 USART synchronous mode
- 19.3.10 Single-wire half-duplex communication
- 19.3.11 Smartcard
- 19.3.12 IrDA SIR ENDEC block
- 19.3.13 Continuous communication using DMA
- 19.3.14 Hardware flow control
- 19.4 USART interrupts
- 19.5 USART mode configuration
- 19.6 USART registers
- 20 Serial peripheral interface (SPI)
- 20.1 SPI introduction
- 20.2 SPI and I2S main features
- 20.3 SPI functional description
- 20.3.1 General description
- 20.3.2 Configuring the SPI in slave mode
- 20.3.3 Configuring the SPI in master mode
- 20.3.4 Configuring the SPI for half-duplex communication
- 20.3.5 Data transmission and reception procedures
- Figure 199. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers
- Figure 200. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers
- Figure 201. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers
- Figure 202. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers
- Figure 203. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers
- Figure 204. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers
- 20.3.6 CRC calculation
- 20.3.7 Status flags
- 20.3.8 Disabling the SPI
- 20.3.9 SPI communication using DMA (direct memory addressing)
- 20.3.10 Error flags
- 20.3.11 SPI interrupts
- 20.4 I2S functional description
- 20.4.1 I2S general description
- 20.4.2 I2S full duplex
- 20.4.3 Supported audio protocols
- Figure 210. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0)
- Figure 211. I2S Philips standard waveforms (24-bit frame with CPOL = 0)
- Figure 212. Transmitting 0x8EAA33
- Figure 213. Receiving 0x8EAA33
- Figure 214. I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0)
- Figure 215. Example
- Figure 216. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0
- Figure 217. MSB justified 24-bit frame length with CPOL = 0
- Figure 218. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0
- Figure 219. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0
- Figure 220. LSB justified 24-bit frame length with CPOL = 0
- Figure 221. Operations required to transmit 0x3478AE
- Figure 222. Operations required to receive 0x3478AE
- Figure 223. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0
- Figure 224. Example of LSB justified 16-bit extended to 32-bit packet frame
- Figure 225. PCM standard waveforms (16-bit)
- Figure 226. PCM standard waveforms (16-bit extended to 32-bit packet frame)
- 20.4.4 Clock generator
- 20.4.5 I2S master mode
- 20.4.6 I2S slave mode
- 20.4.7 Status flags
- 20.4.8 Error flags
- 20.4.9 I2S interrupts
- 20.4.10 DMA features
- 20.5 SPI and I2S registers
- 20.5.1 SPI control register 1 (SPI_CR1)(not used in I2S mode)
- 20.5.2 SPI control register 2 (SPI_CR2)
- 20.5.3 SPI status register (SPI_SR)
- 20.5.4 SPI data register (SPI_DR)
- 20.5.5 SPI CRC polynomial register (SPI_CRCPR)(not used in I2S mode)
- 20.5.6 SPI RX CRC register (SPI_RXCRCR)(not used in I2S mode)
- 20.5.7 SPI TX CRC register (SPI_TXCRCR)(not used in I2S mode)
- 20.5.8 SPI_I2S configuration register (SPI_I2SCFGR)
- 20.5.9 SPI_I2S prescaler register (SPI_I2SPR)
- 20.5.10 SPI register map
- 21 Secure digital input/output interface (SDIO)
- 21.1 SDIO main features
- 21.2 SDIO bus topology
- 21.3 SDIO functional description
- Figure 234. SDIO block diagram
- Table 93. SDIO I/O definitions
- 21.3.1 SDIO adapter
- Figure 235. SDIO adapter
- Figure 236. Control unit
- Figure 237. SDIO adapter command path
- Figure 238. Command path state machine (CPSM)
- Figure 239. SDIO command transfer
- Table 94. Command format
- Table 95. Short response format
- Table 96. Long response format
- Table 97. Command path status flags
- Figure 240. Data path
- Figure 241. Data path state machine (DPSM)
- Table 98. Data token format
- Table 99. Transmit FIFO status flags
- Table 100. Receive FIFO status flags
- 21.3.2 SDIO APB2 interface
- 21.4 Card functional description
- 21.4.1 Card identification mode
- 21.4.2 Card reset
- 21.4.3 Operating voltage range validation
- 21.4.4 Card identification process
- 21.4.5 Block write
- 21.4.6 Block read
- 21.4.7 Stream access, stream write and stream read (MultiMediaCard only)
- 21.4.8 Erase: group erase and sector erase
- 21.4.9 Wide bus selection or deselection
- 21.4.10 Protection management
- 21.4.11 Card status register
- 21.4.12 SD status register
- 21.4.13 SD I/O mode
- 21.4.14 Commands and responses
- 21.5 Response formats
- 21.6 SDIO I/O card-specific operations
- 21.7 CE-ATA specific operations
- 21.8 HW flow control
- 21.9 SDIO registers
- 21.9.1 SDIO power control register (SDIO_POWER)
- 21.9.2 SDI clock control register (SDIO_CLKCR)
- 21.9.3 SDIO argument register (SDIO_ARG)
- 21.9.4 SDIO command register (SDIO_CMD)
- 21.9.5 SDIO command response register (SDIO_RESPCMD)
- 21.9.6 SDIO response 1..4 register (SDIO_RESPx)
- 21.9.7 SDIO data timer register (SDIO_DTIMER)
- 21.9.8 SDIO data length register (SDIO_DLEN)
- 21.9.9 SDIO data control register (SDIO_DCTRL)
- 21.9.10 SDIO data counter register (SDIO_DCOUNT)
- 21.9.11 SDIO status register (SDIO_STA)
- 21.9.12 SDIO interrupt clear register (SDIO_ICR)
- 21.9.13 SDIO mask register (SDIO_MASK)
- 21.9.14 SDIO FIFO counter register (SDIO_FIFOCNT)
- 21.9.15 SDIO data FIFO register (SDIO_FIFO)
- 21.9.16 SDIO register map
- 22 USB on-the-go full-speed (OTG_FS)
- 22.1 OTG_FS introduction
- 22.2 OTG_FS main features
- 22.3 OTG_FS functional description
- 22.4 OTG dual role device (DRD)
- 22.5 USB peripheral
- 22.6 USB host
- 22.7 SOF trigger
- 22.8 Power options
- 22.9 Dynamic update of the OTG_FS_HFIR register
- 22.10 USB data FIFOs
- 22.11 Peripheral FIFO architecture
- 22.12 Host FIFO architecture
- 22.13 FIFO RAM allocation
- 22.14 USB system performance
- 22.15 OTG_FS interrupts
- 22.16 OTG_FS control and status registers
- 22.16.1 CSR memory map
- 22.16.2 OTG_FS global registers
- OTG_FS control and status register (OTG_FS_GOTGCTL)
- OTG_FS interrupt register (OTG_FS_GOTGINT)
- OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
- OTG_FS USB configuration register (OTG_FS_GUSBCFG)
- OTG_FS reset register (OTG_FS_GRSTCTL)
- OTG_FS core interrupt register (OTG_FS_GINTSTS)
- OTG_FS interrupt mask register (OTG_FS_GINTMSK)
- OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP)
- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
- OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0)
- OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_HNPTXSTS)
- OTG_FS general core configuration register (OTG_FS_GCCFG)
- OTG_FS core ID register (OTG_FS_CID)
- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
- OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number)
- 22.16.3 Host-mode registers
- OTG_FS Host configuration register (OTG_FS_HCFG)
- OTG_FS Host frame interval register (OTG_FS_HFIR)
- OTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM)
- OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
- OTG_FS Host all channels interrupt register (OTG_FS_HAINT)
- OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)
- OTG_FS Host port control and status register (OTG_FS_HPRT)
- OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number)
- OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where x = Channel_number)
- OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) (x = 0..7, where x = Channel_number)
- OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, where x = Channel_number)
- 22.16.4 Device-mode registers
- OTG_FS device configuration register (OTG_FS_DCFG)
- OTG_FS device control register (OTG_FS_DCTL)
- OTG_FS device status register (OTG_FS_DSTS)
- OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
- OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
- OTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS)
- OTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE)
- OTG_FS device IN endpoint FIFO empty interrupt mask register: (OTG_FS_DIEPEMPMSK)
- OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
- OTG device endpoint-x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number)
- OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0)
- OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, where x = Endpoint_number)
- OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, where x = Endpoint_number)
- OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, where x = Endpoint_number)
- OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0)
- OTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0)
- OTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) (x = 1..3, where x = Endpoint_number)
- OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number)
- OTG_FS device OUT endpoint-x transfer size register (OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number)
- 22.16.5 OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)
- 22.16.6 OTG_FS register map
- 22.17 OTG_FS programming model
- 23 Debug support (DBG)
- 23.1 Overview
- 23.2 Reference Arm® documentation
- 23.3 SWJ debug port (serial wire and JTAG)
- 23.4 Pinout and debug port pins
- 23.5 STM32F411xC/E JTAG TAP connection
- 23.6 ID codes and locking mechanism
- 23.7 JTAG debug port
- 23.8 SW debug port
- 23.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 23.10 Core debug
- 23.11 Capability of the debugger host to connect under system reset
- 23.12 FPB (Flash patch breakpoint)
- 23.13 DWT (data watchpoint trigger)
- 23.14 ITM (instrumentation trace macrocell)
- 23.15 ETM (Embedded trace macrocell)
- 23.16 MCU debug component (DBGMCU)
- 23.17 TPIU (trace port interface unit)
- 23.17.1 Introduction
- 23.17.2 TRACE pin assignment
- 23.17.3 TPUI formatter
- 23.17.4 TPUI frame synchronization packets
- 23.17.5 Transmission of the synchronization frame packet
- 23.17.6 Synchronous mode
- 23.17.7 Asynchronous mode
- 23.17.8 TRACECLKIN connection inside the STM32F411xC/E
- 23.17.9 TPIU registers
- 23.17.10 Example of configuration
- 23.18 DBG register map
- 24 Device electronic signature
- Revision history