STM8 CPU Programming Manual
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PM0044
Programming manual
STM8 CPU programming manual
Introduction
The STM8 family of HCMOS microcontrollers is designed and built around an enhanced
industry standard 8-bit core and a library of peripheral blocks, which include ROM, Flash,
RAM, EEPROM, I/O, Serial Interfaces (SPI, USART, I2C,...), 16-bit Timers, A/D converters,
comparators, power supervisors etc. These blocks may be assembled in various
combinations in order to provide cost-effective solutions for application-specific products.
The STM8 family forms a part of the STMicroelectronics 8-bit MCU product line, which finds
its place in a wide variety of applications such as automotive systems, remote controls,
video monitors, car radio and numerous other consumer, industrial, telecom, and multimedia
products.
September 2011
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www.st.com
Contents
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Contents
1
STM8 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
STM8 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2
Enhanced STM8 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
STM8 core description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
5
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM8 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
Memory interface architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pipelined execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
6
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Description of pipelined execution stages . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.1
Fetch stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.2
Decoding and addressing stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.3
Execution stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2
Data memory conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3
Pipelined execution examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4.1
Optimized pipeline example – execution from Flash Program memory . 24
5.4.2
Optimize pipeline example – execution from RAM . . . . . . . . . . . . . . . . 26
5.4.3
Pipeline with Call/Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.4
Pipeline stalled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.5
Pipeline with 1 wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM8 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1
Inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2
Immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3
Direct addressing mode (Short, Long, Extended) . . . . . . . . . . . . . . . . . . 34
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6.4
7
6.3.1
Short Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.2
Long Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.3
Extended Direct addressing mode (only for CALLF and JPF) . . . . . . . . 38
Indexed addressing mode (No Offset, Short, SP, Long, Extended) . . . . . 39
6.4.1
No Offset Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.2
Short Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.3
SP Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.4.4
Long Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4.5
Extended Indexed (only LDF instruction) . . . . . . . . . . . . . . . . . . . . . . . . 44
6.5
Indirect (Short Pointer Long, Long Pointer Long) . . . . . . . . . . . . . . . . . . . 45
6.6
Short Pointer Indirect Long addressing mode . . . . . . . . . . . . . . . . . . . . . 46
6.7
Long Pointer Indirect Long addressing mode . . . . . . . . . . . . . . . . . . . . . . 47
6.8
Indirect Indexed (Short Pointer Long, Long Pointer Long,
Long Pointer Extended) addressing mode . . . . . . . . . . . . . . . . . . . . . . . . 48
6.9
Short Pointer Indirect Long Indexed addressing mode . . . . . . . . . . . . . . 49
6.10
Long Pointer Indirect Long Indexed addressing mode . . . . . . . . . . . . . . . 51
6.11
Long Pointer Indirect Extended Indexed addressing mode . . . . . . . . . . . 53
6.12
Relative Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.13
Bit Direct (Long) addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.14
Bit Direct (Long) Relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . 59
STM8 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2
Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.1
Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.2
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.3
Code condition bit value notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.4
Memory and addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.5
Operation code notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.3
Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.4
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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BCCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
BCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
BCPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
BREAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
BRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
BSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
BTJF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
BTJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
CALLF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CALLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
CCF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
CLR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
CLRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
CPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
CPLW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
DECW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DIVW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
EXG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
EXGW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
HALT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
INCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
INT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
IRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
JP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
JPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
JRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
JRxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
LDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
NEGW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
POPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
PUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
PUSHW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
RCF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
RET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
RETF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
RIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
RLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
RLCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
RLWA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
RRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
RRCW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RRWA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
RVF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SCF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SLL/SLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SLLW/SLAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SRAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SRLW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SWAPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
TNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
TNZW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
TRAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
WFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Interruptability levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data/address decoding examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Example with exact number of cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Example with conventional number of cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Optimized pipeline example - execution from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Optimize pipeline example – execution from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Example of pipeline with Call/Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Example of stalled pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pipeline with 1 wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM8 core addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STM8 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Inherent addressing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Immediate addressing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Overview of Direct addressing mode instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Available Long and Short Direct addressing mode instructions . . . . . . . . . . . . . . . . . . . . . 34
Available Extended Direct addressing mode instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Available Long Direct addressing mode instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Overview Indexed addressing mode instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
No Offset, Long, Short and SP Indexed instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
No Offset, Long, Short Indexed Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Extended Indexed Instructions only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Overview of Indirect addressing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Available Long Pointer Long and Short Pointer Long Indirect Instructions. . . . . . . . . . . . . 45
Available Long Pointer Long Indirect Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Overview of Indirect indexed instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Available Long Pointer Long and Short Pointer Long Indirect
Indexed instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Available Long Pointer Long Indirect Indexed instructions . . . . . . . . . . . . . . . . . . . . . . . . . 48
Long Pointer Extended Indirect Indexed instructions instruction . . . . . . . . . . . . . . . . . . . . 48
Overview of Relative Direct addressing mode instructions. . . . . . . . . . . . . . . . . . . . . . . . . 55
Available Relative Direct instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Overview of Bit Direct addressing mode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Available Bit Direct instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Overview of Bit Direct (Long) Relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Available Bit Direct Relative instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
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List of figures
PM0044
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
8/162
Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Context save/restore for interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Interface Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pipelined execution principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pipelined execution stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Immediate addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Short Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Long Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Far Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
No Offset Indexed addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Short Indexed - 8-bit offset - addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SP Indexed - 8-bit offset - addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Long Indexed - 16-bit offset - addressing mode example. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Far Indexed - 16-bit offset - addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Short Pointer Indirect Long addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Long Pointer Indirect Long addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Short Pointer Indirect Long Indexed addressing mode example . . . . . . . . . . . . . . . . . . . . 50
Long Pointer Indirect Long Indexed addressing mode example. . . . . . . . . . . . . . . . . . . . . 52
Long Pointer Indirect Extended Indexed addressing mode example . . . . . . . . . . . . . . . . . 54
Relative Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Bit Long Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Bit Long Direct Relative addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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1
STM8 architecture
STM8 architecture
The 8-bit STM8 Core is designed for high code efficiency. It contains 6 internal registers, 20
addressing modes and 80 instructions. The 6 internal registers include two 16-bit Index
registers, an 8-bit Accumulator, a 24-bit Program Counter, a 16-bit Stack Pointer and an 8bit Condition Code register. The two Index registers X and Y enable Indexed Addressing
modes with or without offset, along with read-modify-write type data manipulation. These
registers simplify branching routines and data/arrays modifications.
The 24-bit Program Counter is able to address up to 16-Mbyte of RAM, ROM or Flash
memory. The 16-bit Stack Pointer provides access to a 64K-level Stack. The Core also
includes a Condition Code register providing 7 Condition flags that indicate the result of the
last instruction executed.
The 20 Addressing modes, including Indirect Relative and Indexed addressing, allow
sophisticated branching routines or CASE-type functions. The Indexed Indirect Addressing
mode, for instance, permits look-up tables to be located anywhere in the address space,
thus enabling very flexible programming and compact C-based code. The stack pointer
relative addressing mode permits optimized C compiler stack model for local variables and
parameter passing.
The Instruction Set is 8-bit oriented with a 2-byte average instruction size. This Instruction
Set offers, in addition to standard data movement and logic/arithmetic functions, 8-bit by 8bit multiplication, 16-bit by 8-bit and 16-bit by 16-bit division, bit manipulation, data transfer
between Stack and Accumulator (Push / Pop) with direct stack access, as well as data
transfer using the X and Y registers or direct memory-to-memory transfers.
The number of Interrupt vectors can vary up to 32, and the interrupt priority level may be
managed by software providing hardware controlled nested capability. Some peripherals
include Direct Memory Access (DMA) between serial interfaces and memory. Support for
slow memories allows easy external code execution through serial or parallel interface
(ROMLESS products for instance).
The STM8 has a high energy-efficient architecture, based on a Harvard architecture and
pipelined execution. A 32-bit wide program memory bus allows most of the instructions to be
fetched in 1 CPU cycle. Moreover, as the average instruction length is 2 bytes, this allows for
a reduction in the power consumption by only accessing the program memory half of the
time, on average. The pipelined execution allowed the execution time to be minimized,
ensuring high system performance, when needed, together with the possibility to reduce the
overall energy consumption, by using different power saving operating modes. Power-saving
can be managed under program control by placing the device in SLOW, WAIT, SLOW-WAIT,
ACTIVE-HALT or HALT mode (see product datasheet for more details).
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STM8 architecture
PM0044
Additional blocks
The additional blocks take the form of integrated hardware peripherals arranged around the
central processor core. The following (non-exhaustive) list details the features of some of the
currently available blocks:
1.1
Boot ROM
Memory area containing the bootloader code
Flash
Flash-based devices
RAM
Sizes up to several Kbytes
Data EEPROM
Sizes up to several Kbytes. Erase/programming operations do not require
additional external power sources.
Timers
Different versions based on 8/16-bit free running or autoreload timer/counter are
available. They can be coupled with either input captures, output compares or
PWM facilities. PWM functions can have software programmable duty cycle
between 0% to 100% in up to 256/65536 steps. The outputs can be filtered to
provide D/A conversion.
A/D converter
The Analog to Digital Converter uses a sample and hold technique. It has 12-bit
resolution.
I2C
Multi/master, single master, single slave modes, DMA or 1byte transfer, standard
and fast I2C modes, 7 and 10-bit addressing.
SPI
The Serial peripheral Interface is a fully synchronous 3/4 wire interface ideal for
Master and Slave applications such as driving devices with input shift register
(LCD driver, external memory,...).
USART
The USART is a fast synchronous/asynchronous interface which features both
duplex transmission, NRZ format, programmable baud rates and standard error
detection. The USART can also emulate RS232 protocol.
Watchdog
It has the ability to induce a full reset of the MCU if its counter counts down to
zero prior to being reset by the software. This feature is especially useful in noisy
applications.
I/O ports
They are programmable by software to act in several input or output
configurations on an individual line basis, including high current and interrupt
generation. The basic block has eight bit lines.
STM8 development support
The STM8 family of MCUs is supported by a comprehensive range of development tools.
This family presently comprises hardware tools (emulators, programmers), a software
package (assembler-linker, debugger, archiver) and a C-compiler development tool.
STM8 and ST7 CPUs are supported by a single toolchain allowing easy reuse and
portability of the applications between product lines.
10/162
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1.2
STM8 architecture
Enhanced STM8 features
●
16-Mbyte linear program memory space with 3 FAR instructions (CALLF, RETF, JPF)
●
16-Mbyte linear data memory space with 1 FAR instruction (LDF)
●
Up to 32 24-bit interrupt vectors with optimized context save management
●
16-bit Stack Pointer (SP=SH:S) with stack manipulation instructions and addressing
modes
●
New register and memory access instructions (EXG, MOV)
●
New arithmetic instructions: DIV 16/8 and DIVW 16/16
●
New bit handling instructions (CCF, BCPL, BCCM)
●
2 x 16-bit index registers (X=XH:XL, Y=YH:YL). 8-bit data transfers address the low
byte. The high-byte is not affected, with a reset value of 0. This allows the use of X/Y as
8-bit values.
●
Fast interrupt handling through alternate register files (up to 4 contexts) with standard
stack compatible mode (for real time OS kernels)
●
16-bit/8-bit stack operations (X, Y, A, CC stacking)
●
16-bit pointer direct update with 16-bit relative offset (ADDW/SUBW for X/Y/SP)
●
8-bit & 16-bit arithmetic and signed arithmetic support
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Glossary
2
12/162
PM0044
Glossary
mnem
mnemonic
src
source
dst
destination
cy
duration of the instruction in CPU clock cycles (internal clock)
lgth
length of the instruction in byte(s)
op-code
instruction byte(s) implementation (1..4 bytes), operation code.
mem
memory location
imm
immediate value
off
offset
ptr
pointer
pos
position
byte
a byte
word
16-bit value
short
represent a short 8-bit addressing mode
long
represent a long 16-bit addressing mode
EA
Effective Address: The final computed data byte address
Page Zero
all data located at [00..FF] addressing space (single byte address)
(XX)
content of a memory location XX
XX
a byte value
ExtB
Extended byte
MS
Most Significant byte of a 16-bit value (MSB)
LS
Least Significant byte of a 16-bit value (LSB)
A
Accumulator register
X
16-bit X Index register
Y
16-bit Y Index register
reg
A, XL or YL register (1-byte LS part of X/Y), XH or YH (1-byte MS part of X/Y)
ndx
index register, either X or Y
PC
24-bit Program Counter register
SP
16-bit Stack Pointer
S
Stack Pointer LSB
CC
Condition Code register
Doc ID 13590 Rev 3
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STM8 core description
3
STM8 core description
3.1
Introduction
The CPU has a full 8-bit architecture, with 16-bit operations on index registers (for address
computation). Six internal registers allow efficient 8-bit data manipulation. The CPU is able
to execute 80 basic instructions. It features 20 addressing modes and can address 6 internal
registers and 16 Mbytes of memory/peripheral registers.
3.2
CPU registers
The 6 CPU registers are shown in the programming model in Figure 1. Following an
interrupt, the register context is saved. The context is saved by pushing registers onto the
stack in the order shown in Figure 2. They are popped from the stack in the reverse order.
Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations as well as data manipulations.
Index registers (X and Y)
These 16-bit registers are used to create effective addresses or as temporary storage area
for data manipulations. In most of the cases, the cross assembler generates a PRECODE
instruction (PRE) to indicate that the following instruction refers to the Y register. Both X and
Y are automatically saved on interrupt routine branch.
Program Counter (PC)
The program counter is a 24-bit register used to store the address of the next instruction to
be executed by the CPU. It is automatically refreshed after each processed instruction. As a
result, the STM8 core can access up to 16-Mbytes of memory.
Figure 1.
Programming model
7
0
A ACCUMULATOR
15
8 7
0
XH
15
X INDEX
XL
8 7
0
YH
Y INDEX
YL
15
0
SP STACK POINTER
16 15
23
PCE
8 7
0
PCH
PCL
7
V
0
- I1 H I0 N Z C
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CC CODE CONDITION
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STM8 core description
PM0044
Stack Pointer (SP)
The stack pointer is a 16-bit register. It contains the address of the next free location of the
stack. Depending on the product, the most significant bits can be forced to a preset value.
The stack is used to save the CPU context on subroutines calls or interrupts. The user can
also directly use it through the POP and PUSH instructions.
After an MCU reset the Stack Pointer is set to its upper limit value. It is then decremented
after data has been pushed onto the stack and incremented after data is popped from the
stack. When the lower limit is exceeded, the stack pointer wraps around to the stack upper
limit. The previously stored information is then overwritten, and therefore lost.
A subroutine call occupies two or three locations.
When an interrupt occurs, the CPU registers (CC, X, Y, A, PC) are pushed onto the stack.
This operation takes 9 CPU cycles and uses 9 bytes in RAM.
Note:
The WFI/HALT instructions save the context in advance. If an interrupt occurs while the CPU
is in one of these modes, the latency is reduced.
Figure 2.
Context save/restore for interrupts
).4%22504 '%.%2!4)/. EXECUTE PIPELINE
#OMPLETE INSTRUCTION IN EXECUTE STAGE CYCLE LATENCY
053( 0#,
053( 0#(
053( 0#%
053( 9
053( 8
053( !
053( ##
#05 #9#,%3
*5-0 4/ ).4%22504 2/54).% ')6%. "9 4(% ).4%22504 6%#4/2
2%452.
5.34!#+
0/0
)2%4 ).3425#4)/.
0#,
0#,
0#(
0#,
0#%
0#,
9,
0#,
9(
0#,
8,
0#,
8(
0#,
!
0#,
##
0#,
).4%22504
).4%22504 2/54).%
%8%#54)/.
34!#+
053(
0/0 ##
0/0 !
0/0 8
0/0 9
0/0 0#%
0/0 0#(
0/0 0#,
#05 #9#,%3
*5-0 4/ 4(% !$$2%33 ')6%. "9 02/'2!- #/5.4%2 2ELOAD 0IPELINE
-36
14/162
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STM8 core description
Global configuration register (CFG_GCR)
The global configuration register is a memory mapped register. It controls the configuration
of the processor. It contains the AL control bit:
AL: Activation level
If the AL bit is 0 (main), the IRET will cause the context to be retrieved from stack and the
main program will continue after the WFI instruction.
If the AL bit is 1 (interrupt only active), the IRET will cause the CPU to go back to WFI/HALT
mode without restoring the context.
This bit is used to control the low power modes of the MCU. In a very low power application,
the MCU spends most of the time in WFI/HALT mode and is woken up (through interrupts)
at specific moments in order to execute a specific task. Some of these recurring tasks are
short enough to be treated directly in an ISR, rather than going back to the main program. In
this case, by programming the AL bit to 1 before going to low power (by executing WFI/HALT
instruction), the run time/ISR execution is reduced due to the fact that the register context is
not saved/restored each time.
Condition Code register (CC)
The Condition Code register is a 8-bit register which indicates the result of the instruction
just executed as well as the state of the processor. These bits can be individually tested by a
program and specified action taken as a result of their state. The following paragraphs
describe each bit.
●
V: Overflow
When set, V indicates that an overflow occurred during the last signed arithmetic
operation, on the MSB operation result bit. See INC, INCW, DEC, DECW, NEG, NEGW,
ADD, ADC, SUB, SUBW, SBC, CP, CPW instructions.
●
I1: Interrupt mask level 1
The I1 flag works in conjunction with the I0 flag to define the current interruptability level
as shown in the following table. These flags can be set and cleared by software through
the RIM, SIM, HALT, WFI, IRET, TRAP and POP instructions and are automatically set
by hardware when entering an interrupt service routine.
Table 1.
Interruptability levels
Interruptability
Priority
Interruptable Main
Interruptable Level 1
Lowest
I1
I0
1
0
0
1
0
0
1
1
↕
Interruptable Level 2
Highest
Non Interruptable
●
H: Half carry bit
The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an
ADD or ADC instruction. The H bit is useful in BCD arithmetic subroutines.
For ADDW, SUBW it is set when a carry occurs from bit 7 to 8, allowing to implement
byte arithmetic on 16-bit index registers.
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STM8 core description
●
PM0044
I0: Interrupt mask level 0
See Flag I1
●
N: Negative
When set to 1, this bit indicates that the result of the last arithmetic, logical or data
manipulation is negative (i.e. the most significant bit is a logic 1).
●
Z: Zero
When set to 1, this bit indicates that the result of the last arithmetic, logical or data
manipulation is zero.
●
C: Carry
When set, C indicates that a carry or borrow out of the ALU occurred during the last
arithmetic operation on the MSB operation result bit (bit 7 for 8-bit result/destination or
bit 15 for 16-bit result). This bit is also affected during bit test, branch, shift, rotate and
load instructions. See ADD, ADC, SUB, SBC instructions.
In bit test operations, C is the copy of the tested bit. See BTJF, BTJT instructions.
In shift and rotates operations, the carry is updated. See RRC, RLC, SRL, SLL, SRA
instructions.
This bit can be set, reset or complemented by software using SCF, RCF, CCF
instructions.
Example: Addition
$B5 + $94 = "C" + $49 = $149
C
0
7
1
C
7
+
0
1
=
C
1
7
0
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
0
0
0
1
The results of each instruction on the Condition Code register are shown by tables in
Section 7: STM8 instruction set. The following table is an example:
V
I1
V
0
H
I0
N
Z
C
0
N
Z
1
where
Nothing =
Flag not affected
Flag name = Flag affected
16/162
0=
Flag cleared
1=
Flag set
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STM8 memory interface
4
STM8 memory interface
4.1
Program space
The program space is 16-Mbyte and linear. To distinguish the 1, 2 and 3 byte wide
addressing modes, naming has been defined as shown in Figure 3:
●
"Page" [0xXXXX00 to 0xXXXXFF]: 256-byte wide memory space with the same two
most significant address bytes (XXXX defines the page number).
●
"Section" [0xXX0000 to 0xXXFFFF]: 64-Kbyte wide memory space with the same most
significant address byte (XX defines the section number).
The reset and interrupt vector table are placed at address 0x8000 for the STM8 family.
(Note: the base address may be different for later implementations.) The table has 32 4-byte
entries: RESET, Trap, NMI and up to 29 normal user interrupts. Each entry consists of the
reserved op-code 0x82, followed by a 24-bit value: PCE, PCH, PCL address of the
respective Interrupt Service Routine. The main program and ISRs can be mapped
anywhere in the 16 Mbyte memory space.
CALL/CALLR and RET must be used only in the same section. The effective address for the
CALL/RET is used as an offset to the current PCE register value. For the JP, the effective
address 16 or 17-bit (for indexed addressing) long, is added to the current PCE value. In
order to reach any address in the program space, the JPF jump and CALLF call instructions
are provided with a three byte extended addressing mode while the RETF pops also three
bytes from the stack.
As the memory space is linear, sections can be crossed by two CPU actions: next
instruction byte fetch (PC+1), relative jumps and, in some cases, by JP (for indexed
addressing mode).
Note:
For safe memory usage, a function which crosses sections MUST:
- be called by a CALLF
- include only far instructions for code operation (CALLF & JPF)
All label pointers are located in section 0 (JP [ptr.w] example: ptr.w is located in section 0
and the jump address in current section)
Any illegal op-code read from the program space triggers a MCU reset.
4.2
Data space
The data space is 16-Mbyte and linear. As the stack must be located in section 0 and as
data access outside section 0/1 can be managed only with LDF instructions, frequently used
data should be located in section 0 to get the optimum code efficiency.
All data pointers are located in section 0 only.
Indexed addressing (with 16-bit index registers and long offset) allows data access over
section 0 and 1.
All the peripherals are memory mapped in the data space.
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STM8 memory interface
Figure 3.
PM0044
Address spaces
PROGRAM SPACE
DATA SPACE
0xFFFFFF
0x82
INT28E
INT28H
SECTION 256
INT28L 0x00807C
0xFF0000
0x82
0x82
0x82
0x82
0x82
INT1E
INT1H
INT1L
INT0E
INT0H
INT0L
0x01FFFF
NMIE
NMIH
NMIL
TRAPE TRAPH TRAPL
RESETE RESETH RESETL 0x008000 0x010000
0x00FFFF
3-BYTE ADDRESSING MODE
ACCESSIBLE DATA
SECTION 1
0x008000
VECTORS
0x0000FF
PAGE 0
0x000000
18/162
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SECTION 0
0x00807F
2-BYTE ADDRESSING MODE
BIT HANDLING CAPABILITY
POWERFUL DATA MANAGEMENT
STACK AREA
POINTERS
1-BYTE ADDRESSING MODE
BIT HANDLING CAPABILITY
FAST DATA ACCESS WITH
SHORT GENERATED CODE
PM0044
Memory interface architecture
The STM8 uses a Harvard architecture, with separate program and data memory buses.
However, the logical address space is unified, all memories sharing the same 16-Mbytes
space, non-overlapped. The memory interfaces are shown in Figure 4. It consists of two
buses: address, data, read/write control signal (R/W) and memory acknowledge signal
(STALL).
The STALL acknowledge signal makes the CPU compatible with slow serial or parallel
memory interfaces. When the memory interface is slow the CPU waits the memory
acknowledge before executing the instruction. So in such a case, the instruction CPU cycle
time is prolonged compare to the value given in this manual.
The program memory bus is 32-bit wide, allowing the fetch of most of the instructions in one
cycle.
As the address space is unified, the architecture allows data to be stored also in the Flash
memory and program to be fetched also from RAM (data bus). In this later case the
performance is impacted, besides the fact that data and fetch operation share the same bus,
the instructions will be fetched one byte at a time, thus taking longer (1 cycle /byte).
Memory Interface Architecture
Memory Interface (Flash)
STALL
D31..0
@BUS
Figure 4.
DATABUS
(FETCH)
4.3
STM8 memory interface
0x00
A23..0
24
Data@E Data@E0:H:L
CPU
@DATABUS
"LDF" INSTRUCTION
N
PROGRAM COUNTER
PCE PCH PCL
7
@DATABUS
RAM FETCH INSTRUCTION
24
24
N
D7..0
Y
@BUS
DATABUS
STALL
24
17
Y
A15..0
R/W
Memory Interface (RAM)
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Pipelined execution
5
PM0044
Pipelined execution
The STM8 family uses a 3-stage pipeline to increase the speed of the flow of instructions
sent to the processor. Pipelined execution allows several operations to be performed
simultaneously, rather than serially:
●
Fetch
●
Decode and address
●
Execute
The Program Counter (PC) points always to the instruction in decode stage as shown in
Figure 5.
Figure 5.
0# N
Pipelined execution principle
&%4#(
0#
$%#/$%
0# N
%8%#54%
)NSTRUCTIONSS FETCHED FROM MEMORY
)NSTRUCTIONS DECODING AND DATA READ FROM MEMORY IF NEEDED
2EGISTERS DATA READ FROM REGISTER BANK
3HIFT AND !,5 OPERATION
7RITE BACK REGISTERS DATA TO 2EGISTER BANK
7RITE BACK DATA TO MEMORY
-36
5.1
Description of pipelined execution stages
Figure 6 and Section 5.1.1, Section 5.1.2, and Section 5.1.3 provide a detailed description
of each stage of the pipeline execution.
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Pipelined execution
Pipelined execution stages
&ETCH
7RITE "ACK
-RD
BIT
$ECODE-EM 2EAD
2EGISTER
BIT
%XECUTION
$ECODE
BIT
!LIGN
)MM
)4#
0REFETCH BUFFER
0ERIPHERALS
2!-
!,5
!DDRESS
COMPUTATION
-%-/29
#/.42/,
&LASH
INSTRUCTION
MEMORY
7" ADD
0#
/P CODE
Figure 6.
%XECUTE7RITE BACK
-36
5.1.1
Fetch stage
The first pipeline stage includes a 64-bit fetch buffer and a 32-bit prefetch buffer, totalling 3
words named F1, F2 and F3. This buffer structure allows any instruction code (up to 5 bytes)
to be available for decoding immediately after F1 (and F2 when needed) is/are loaded.
The instruction access from Flash Program memory is 32-bit wide and it is performed from
an aligned address i.e. 0xXXX0, 0xXXX4, 0xXXX8, or 0xXXXC.
Unlike the decode and execute stages that are performed at every cycle, the fetch stage
accesses the program memory only when needed, and stops memory access when the
buffer is full. This allows reducing the core power consumption,
Reading program from RAM is similar to reading program from ROM. However, since the
RAM data bus is 8-bit wide, 4 consecutive read operations have to be performed to load one
FX word, thus resulting in RAM execution being slower than Flash execution.
5.1.2
Decoding and addressing stage
The decoding stage includes an instruction alignment unit. The alignment unit uses the 64bit input from the fetch unit and feeds an instruction (from 1 to 5 bytes depending on the
instruction) to the decoding unit.
The instruction code consists of 2 parts (see examples in Table 2):
●
The op-code itself (1 or 2 bytes)
●
and a data/address part (0 to 3 bytes).
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Pipelined execution
PM0044
The op-code is decoded in this stage. When present, the instruction address is used for
address computation, whilst the immediate operand is forwarded to the execution stage.
Table 2.
Data/address decoding examples
Instruction
Syntax
Op-code
Data/address
LD A, XH
0x95
-
Register load
LD A,($12,SP)
0x7B
0x12
Register store
LD ($12,SP),A
0x6B
0x12
LDF A,($123456,Y)
0x90 AF
0x12 34 56
Register to register
move
Data load / store with
extended address
Long/unaligned instructions
For long instructions (i.e. 5-bytes instructions), the fetch may need 2 program memory
accesses to be completed. In this case, the decoding stage (after decoding the op-code
part), is stalled waiting for the fetch stage to complete the 2nd fetch.
In case of shorter instructions, this may also happen when they cross a 32-bit boundary.
Indirect addressing
For indirect addressing, the CPU is stalled in this stage to read the pointer from the data
memory (i.e. RAM). The number of cycles during which the CPU is stalled depends on the
pointer size (short, long or extended addressing mode).
5.1.3
Execution stage
In the execution stage, the operation is executed and the result is stored in the accumulator,
index register or RAM.
5.2
Data memory conflicts
3 types of operations perform accesses to the data memory:
●
Effective address computation in case of indirect addressing
●
Data read: source operand
●
Data write: destination for store or read-modify-write operations
In case of simultaneous accesses to the same memory area both in execution stage (write)
and decoding stage (read), the decode stage is stalled till the execution stage releases the
resource.
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5.3
Pipelined execution
Pipelined execution examples
A few pipelined execution examples are reported below. The numbers of cycles for the
decoding and execution stages correspond to the minimum number of cycles needed by the
instruction itself. In some cases, depending on the instruction sequence, the cycle taken
could be more than that number.
5.4
Conventions
Although the decode and/or execute stage of some instructions may take a different number
of cycles, a simplified convention providing a good match with reality, has been used in this
section:
●
The decode stage of each instruction takes one cycle only
●
The execution stage takes a number of cycles equal to
C y = DecCy + ExeCy – 1
Where
Cy is the number of execution cycles. In case of decode and execute cycles, It
corresponds to the minimum number of cycles needed by the instruction itself, and
does not take into account the impact of the instruction sequence.
DecCy is the exact number of decode cycles.
ExeCy is the exact number of execute cycles.
The decode stage of the next instruction starts during the last execution cycle. In
instructions performing pipeline flush, the convention is that, in case the branch is taken, the
next fetch are performed during the last instruction execution cycle.
The exact number of cycles (see Table 3) and the number of cycles obtained using this
convention (see Table 4) are identical.
Table 3.
Address
0xC000
0xC003
0xC006
0xC009
Example with exact number of cycles
Instruction
LDW X, [$50.w]
ADDW X, #20
LD A, [$30].w
….
Decode Execute
lgth
cycles
cycles
4
2
3
1
2
1
Time (cycle)
1
3
3
3
2
3
4
5
6
D
D
D
D
E
D
D
D
F1
F2
7
8
9
D
D
E
E
D
D
D
D
10 11 12 13 14
D
D
E
F3
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Pipelined execution
Table 4.
Address
PM0044
Example with conventional number of cycles
Instruction
0xC000 LDW X, [$50.w]
Decode Execute
lgth
cycles
cycles
4
3
Time (cycle)
1
3
2
3
4
5
6
7
8
9
D
E
E
E
E
D
D
D
D
E
E
E
D
D
D
D
10 11 12 13 14
F1
0xC003
ADDW X, #20
3
3
3
F2
0xC006
LD A, [$30].w
3
3
3
E
E
E
F3
0xC009
….
Table 5.
5.4.1
Legend
Symbol/Color
Definition
F
Fetch
D
Decode stalled
D
Decode
E
Execute
Optimized pipeline example – execution from Flash Program memory
In the example shown in Table 6, the code is stored in the Flash Program memory (32-bit
bus). As a result, 3 cycles are needed to fill the 96-bit prefetch buffer. At each cycle, one
word is loaded and stored in F1, F2 and F3. The next fetch operation can start only when all
the instructions contained in one of the Fx word are decoded. In fact, at cycle 9, the last
instruction contained in F3 (SWAP A) is decoded, and a fetch operation can start to fill F3
word.
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Table 6.
Add.
Pipelined execution
Optimized pipeline example - execution from Flash
Instruction
Cycle
Decod.
cycles
Exec.
cycles
lgth
1
0xC000
NEG A
1
1
1
0xC001
XOR A, $10
1
1
2
0xC003
LD A, #20
1
1
2
0xC005
SUB A,$1000
1
1
3
0xC008
INC A
1
1
1
0xC009
LD XL, A
1
1
1
0xC00A
SRL A
1
1
1
0xC00B
SWAP A
1
1
1
0xC00C
SLA $15
1
1
2
0xC00E
CP A,#$FE
1
1
2
0xC010 MOV $100, #11
1
1
4
0xC014 MOV $101, #22
1
1
4
Table 7.
2
3
D
E
F1
D
4
5
6
7
8
9
10 11 12 13 14
E
D
F2
E
D
E
D
E
D
F3
E
D
E
D
E
D
F1
E
D
F2
E
D
F3
E
D
E
Legend
Symbol/Color
Definition
F
Fetch
D
Decode
E
Execute
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Pipelined execution
5.4.2
PM0044
Optimize pipeline example – execution from RAM
In the example shown in Table 8, the RAM is accessed through an 8-bit bus. As a result, 12
cycles are required to fill the 96-bit pre-fetch buffer. Every 4 cycles, one word is loaded and
stored in Fx. The decoding of the first word instruction can start only when the Fx word is
filled. This occurs for example till the 4th cycle, and the first instruction (NEG A) can be
decoded only at the 5th cycle.
In case of read/write access to the RAM, the fetch is stalled. This occurs during the 6th cycle
since RAM address 10 is read during the decode stage of XOR A, $10.
Decode cycles
Execute cycles
lgth
Optimize pipeline example – execution from RAM
Instruction
0xC000
NEG A
1
1
1
0xC001
XOR A,
$10
1
1
2
1
1
2
LD XL, A
1
1
1
0xC00A
SRL A
1
1
1
0xC00B
SWAP A
1
1
1
0xC00C
SLA $15
1
1
2
0xC00E
CP
A,#$FE
1
1
2
Table 9.
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F1_3
F2_1
FS
D
D
D
D
E
E
D
E
D
FS
D
D
D
E
D
E
D
D
Legend
Symbol/Color
Definition
F
Fetch
FS
Fetch stalled
D
Decode
D
Decode stalled
E
Execute
Doc ID 13590 Rev 3
E
E
D
F1_4
0xC009
D
F1_3
1
E
F1_2
1
D
10 11 12 13 14 15 16 17 18 19 20 21
F1_1
1
D
9
F3_4
INC A
D
8
F3_3
0xC008
D
7
F3_2
3
6
F3_1
1
5
F2_4
1
4
F2_3
SUB
A,$1000
3
F2_2
0xC005
2
F1_4
0xC003 LD A, #20
1
F1_2
Add.
Cycle
F1_1
Table 8.
E
D
E
PM0044
5.4.3
Pipelined execution
Pipeline with Call/Jump
In the example shown in Table 10, a branch is taken after the JP/CALL instruction, and the
fetched instruction(s) are lost (flush). New instructions must be fetched. 3 fetch sequences
are required to refill the pre-fetch buffer. The fetch start depends on the instruction being
executed.
For a JP instruction, the fetch can start during the first cycle of the "dummy" execution.
For the CALL instruction, it starts after the last cycle of the CALL execution.
0xC000
Instruction
Decode Execute
lgth
cycles
cycles
INC A
1
1
JP label
1
1
3
0xC004
LDW X,[$5432.w]
X
X
4
0xD010
label: NEG A
1
1
1
0xD011
CALL label2
1
2
3
0xD014
LDW X,[$5432.w]
X
X
4
0xD018
LDW X,[$7895.w]
X
X
4
0xE030
label2: INCW X
1
1
1
5.4.4
1
1
0xC001
Table 11.
Cycle
2
3
D
E
F1
D
F2
4
5
6
D
E
7
8
E
E
9
10
11
F1
D
E
E
F1
D
F2
F3 FS
Flush
Add.
Example of pipeline with Call/Jump
Flush
Table 10.
Legend
Symbol/Color
Definition
F
Fetch
FS
Fetch stalled
D
Decode
E
Execute
Pipeline stalled
The decode stage can be stalled when the execution lasts more than one cycle.
The flush is due to the branch. Fetching the branch address is performed during the second
execution cycle of the BTJF instruction.
The Decode operation can also be stalled when the memory target is modified during the
previous instruction. In the example given in Table 12, the INCW Y instruction writes the X
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Pipelined execution
PM0044
register during the first execution cycle. As a result, in this cycle, the next instruction
(LD A,(X)) cannot be decoded since it reads the X register.
Address
0xC000
Example of stalled pipeline
Decode Execute
lgth
cycles
cycles
Instruction
SUB SP, #20
1
1
LD A, #20
1
1
2
0xC004
BTJT 0x10, #5, to
1
2
5
0xC009
INC A
1
1
1
0xC00A
BTJF 0x20, #3, to
1
2
5
0xC00F
NOP
X
X
1
0xC010
LDW X,[$5432.w]
X
X
4
0xC014
LDW X,[$1234.w]
X
X
4
0xD020
to: INCW Y
1
1
2
LD A,(X)
Table 13.
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1
1
1
2
0xC002
0xD023
Time (cycles)
2
3
D
E
F1
D
F2
4
7
8
E
E
D
D
9
10
11
E
E
E
D
F3
E
D
F1
F2
F3
F1
2
Legend
Symbol/Color
Definition
F
Fetch
D
Decode stalled
D
Decode
E
Execute
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12 13 14
Flush
Table 12.
D
E
D
D
E
PM0044
5.4.5
Pipelined execution
Pipeline with 1 wait state
In the example given in Table 14, performing the fetch takes 2 cycles, and there is no
overlap between the 2 fetch cycles.
If the instruction is decoded/executed during the last 2 fetch cycles, then the wait state is
transparent compared to the no-wait state execution.
Table 14.
Address
0xC000
Pipeline with 1 wait state
Instruction
NEG A
Decode Execute
lgth
cycles
cycles
1
1
1
0xC001
DEC ($10, X)
1
1
3
0xC004
LDW X, #20
1
1
3
0xC007
LD (X), A
1
1
1
0xC008
INC A
1
1
1
0xC009
NEG ($5A, Y)
Table 15.
1
1
Time (cycle)
1
2
MS
3
4
D
E
F1
1
5
D
6
7
E
E
D
D
8
9
10
E
MS
D
F2
MS
E
D
F3
E
D
E
Legend
Symbol/Color
Definition
F
Fetch
D
Decode stalled
D
Decode
MS
Memory stalled
E
Execute
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STM8 addressing modes
6
PM0044
STM8 addressing modes
The STM8 core features 18 different addressing modes which can be classified in 8 main
groups:
Table 16.
STM8 core addressing modes
Addressing mode groups
Example
Inherent
NOP
Immediate
LD A,#$55
Direct
LD A,$55
Indexed
LD A,($55,X)
SP Indexed
LD A,($55,SP)
Indirect
LD A,([$55],X)
Relative
JRNE loop
Bit operation
BSET byte,#5
The STM8 Instruction set is designed to minimize the number of required bytes per
instruction. To do so, most of the addressing modes can be split in three sub-modes called
extended, long and short:
The extended addressing mode ("e") can reach any byte in the 16-Mbyte addressing
space, but the instruction size is bigger than the short and long addressing mode.
Moreover, the number of instructions with this addressing mode (far) is limited (CALLF,
RETF, JPF and LDF)
●
The long addressing mode ("w") is the most powerful for program management, when
the program is executed in the same section (same PCE value). The long addressing
mode is optimized for data management in the first 64-Kbyte addressing space (from
0x000000 to 0x00FFFF) with a complete set of instructions, but the instruction size is
bigger than the short addressing mode.
●
The short addressing mode ("b") is less powerful because it can only access the page
zero (from 0x000000 to 0x0000FF), but the instruction size is more compact.
STM8 addressing mode overview
Mode
Syntax
Inherent
NOP
Immediate
LD A,#$55
Destination
address
Short
Direct
LD A,$10
000000..0000FF
Long
Direct
LD A,$1000
000000..00FFFF
Extended
Direct
LDF A,$100000
000000..FFFFFF
No Offset
Direct
Indexed
LD A,(X)
000000..00FFFF
Short
Direct
Indexed
LD A,($10,X)
000000..0100FE
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Pointer
address
Pointer
size
Table 17.
●
PM0044
STM8 addressing mode overview (continued)
Mode
Syntax
Destination
address
Pointer
address
Pointer
size
Table 17.
STM8 addressing modes
Short
Direct
SP
Indexed
LD A,($10,SP)
00..(FF+Stacktop)
Long
Direct
Indexed
LD A,($1000,X)
000000..01FFFE
Extended
Direct
Indexed
LDF A,($100000,X)
000000..FFFFFF
Short
Indirect
Pointer Long
LD A,[$10.w]
000000..00FFFF
000000..0000FF
2
Long Pointer
indirect
Long
LD A,[$1000.w]
000000..00FFFF
000000..00FFFF
2
Long Pointer
indirect
Extended
LDF A,[$1000.e]
000000..FFFFFF
000000..00FFFF
3
Short
Indirect Indexed
Pointer Long
LD A,([$10.w],X)
000000..01FFFE
000000..0000FF
2
Indexed
Long Pointer
Indirect
Long
(X only)
LD A,([$1000.w],X)
000000..01FFFE
000000..00FFFF
2
Long Pointer
Indirect Indexed
Extended
LDF A,([$1000.e],X)
000000..FFFFFF
000000..00FFFF
3
Relative
Direct
JRNE loop
Bit
Long
Direct
BSET $1000,#7
Bit
Long
Direct
Relative
PC+127/-128
BTJT $1000,#7,skip
000000..00FFFF
000000..00FFFF PC+127/-128
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STM8 addressing modes
6.1
PM0044
Inherent addressing mode
All related instructions are 1 or 2 byte. The op-code fully specifies all required information for
the CPU to process the operation.
Table 18.
Inherent addressing instructions
Instructions
Functions
NOP
No operation
TRAP
S/W Interrupt
WFI, WFE
Wait For Interrupt / Event (Low Power Mode)
HALT
Halt Oscillator (Lowest Power Mode)
RET
Sub-routine Return
RETF
Far Sub-routine Return
IRET
Interrupt Sub-routine Return
SIM
Set Interrupt Mask
RIM
Reset Interrupt Mask
SCF
Set Carry Flag
RCF
Reset Carry Flag
RVF
Reset Overflow Flag
CCF
Complement Carry Flag
LD, LDW
Load
CLR, CLRW
Clear
PUSH, POP, PUSHW, POPW
Push/Pop to/from the stack
INC, DEC, INCW, DECW
Increment/Decrement
TNZ, TNZW
Test Negative or Zero
CPL, NEG, CPLW, NEGW
1’s or 2’s Complement
MUL
Byte Multiplication
DIV, DIVW
EXG, EXGW
SLA, SLL, SRL, SRA, RLC,
RRC, SLAW, SLLW, SRLW,
SRAW, RLCW, RRCW
SWAP, SWAPW
Division
Exchange
Shift and Rotate Operations
Swap Nibbles/Bytes
Example:
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1000 98
RCF
; Reset carry flag
1001 9D
NOP
; No operation
1002 9F
LD A,X; Transfer X register content into accumulator
1004 88
PUSH A; Push accumulator content onto the stack
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6.2
STM8 addressing modes
Immediate addressing mode
The data byte required for the operation, follows the op-code.
Table 19.
Immediate addressing instructions
Instructions
Functions
LD, MOV, LDW
Load and move operation
CP, CPW
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC, ADDW, SUBW
PUSH
Arithmetic Operations
Stack Operations
These are two byte instructions, one for the op-code and the other one for the immediate
data byte.
Example:
05BA
05BC
05BE
AEFF
A355
A6F8
LD
CP
LD
X,#$FF
X,#$55
A,#$F8
Action:
Load X = $FF
Compare (X, $55)
A = $F8
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STM8 addressing modes
Figure 7.
PM0044
Immediate addressing mode example
Before Completion
A
Steps to Determine
Effective Address
Previous Value
PC
LD A, #0F8h
A6
05BE
F8
05BF
PC = 05BE
05BE
PC = PC + 1 = 05BF
EA = PC = 05BF
05C0
New PC = PC + 1
= 05C0
After Completion
Instruction Complete
A
A = (EA) = F8
F8
A6
05BE
F8
05BF
New PC
05C0
05C0
New PC = 05C0
VR02059A
6.3
Direct addressing mode (Short, Long, Extended)
Table 20.
Overview of Direct addressing mode instructions
Addressing mode
Syntax
EA formula
Ptr Adr
Ptr Size
Dest adr
Short
Direct
shortmem
(shortmem)
op + 1
Byte
00..FF
Long
Direct
longmem
(longmem)
op + 1..2
Word
0000..FFFF
Extended
Direct
extmem
(extmem)
op + 1..3
Ext word
000000..FFFFFF
The data byte required for the operation is found by its memory address, which follows the
op-code.
Direct addressing mode is made of three sub-modes:
Table 21.
Available Long and Short Direct addressing mode instructions
Instructions
Functions
LD, LDW
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC, ADDW, SUBW
BCP
34/162
Arithmetic Addition/Subtraction operations
Bit Compare
Doc ID 13590 Rev 3
PM0044
STM8 addressing modes
Table 21.
Available Long and Short Direct addressing mode instructions
Instructions
Functions
MOV
Move
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1’s or 2’s Complement
SLA, SLL, SRL, SRA, RLC, RRC
SWAP
CALL, JP
Table 22.
Swap Nibbles
Call or Jump subroutine
Available Extended Direct addressing mode instructions
Instructions
Function
CALLF, JPF
Call or Jump FAR subroutine
LDF
Table 23.
Shift and Rotate Operations
Far load
Available Long Direct addressing mode instructions
Instructions
EXG
PUSH, POP
Function
Exchange
Stack operation
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STM8 addressing modes
6.3.1
PM0044
Short Direct addressing mode
The address is a byte, thus require only one byte after the op-code, but only allow 00..FF
addressing space.
Example:
004B
052D
20
B64B
coeff
dc.b
LD
$20
A,coeff
Action:
A = (coeff) = ($4B) = $20
Figure 8.
Short Direct addressing mode example
Before Completion
Steps to Determine
Effective Address
A
Coeff .byte 20h
20
Previous Value
004B
PC = 052D
PC
LD A,Coeff
PC = PC + 1 = 052E
B6
052D
4B
052E
= (4B + 0000)
052F
= 004B
052D
EA
EA = (PC)
004B
After Completion
A
Coeff .byte 20h
LD A,Coeff
20
004B
B6
052D
4B
052E
052F
20
Instruction Complete
A = (EA) = 20
New PC
New PC = PC + 1 = 052F
052F
VR02059L
36/162
Doc ID 13590 Rev 3
PM0044
6.3.2
STM8 addressing modes
Long Direct addressing mode
The address is a word, thus allowing 0000 to FFFF addressing space, but requires 2 bytes
after the op-code.
Example:
0409
06E5
C606E5
40
coeff
LD
dc.b
A,coeff
$ 40
Action:
A = (coeff) = ($06E5) = $40
Figure 9.
Long Direct addressing mode example
Before Completion
A
Previous Value
Steps to Determine
Effective Address
PC
LD A,Coeff
C6
0409
06
040A
E5
040B
0409
06E5
PC = 0409
PC = PC + 1 = 040A
EA = (PC) : (PC+1) = 06E5
040C
Coeff .byte 040h
40
06E5
EA
06E5
After Completion
Instruction Complete
LD A,Coeff
C6
0409
06
040A
E5
040B
New PC
040C
040C
A = (EA) = 40
New PC = PC + 2 = 040C
A
Coeff .byte 040h
40
06E5
40
VR02059B
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STM8 addressing modes
6.3.3
PM0044
Extended Direct addressing mode (only for CALLF and JPF)
The address is an extended word, thus allowing 000000 to FFFFFF addressing space, but
requires 3 bytes after the op-code.
Example:
000409
0106E5
8D0106E5
4C
CALLF sw_routine
INC
A
sw_routine
Action:
PC = $0106E5
Figure 10. Far Direct addressing mode example
Before Completion
A
Previous Value
Steps to Determine
Effective Address
PC
CALLF
sw_routine
8D
0409
01
040A
06
040B
E5
040C
0409
0106E5
EA
INC A
4C
PC = 0409
PC=PC+1
EA=(PC):(PC+1):(PC+2)
=0106E5
New PC = EA
0106E5
0106E5
After Completion
Instruction Complete
CALLF
sw_routine
8D
0409
01
040A
06
040B
E5
New PC = 0106E5
040C
New PC
INC A
4C
0106E5
0106E5
VR02059U
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Doc ID 13590 Rev 3
PM0044
6.4
STM8 addressing modes
Indexed addressing mode (No Offset, Short, SP, Long,
Extended)
Table 24.
Overview Indexed addressing mode instructions
Addressing mode
Syntax
EA formula
Ptr Adr
Ptr Size
Dest adr
(ndx)
---
---
00..FFFF
No offset
Direct Indexed
(ndx)
Short
Direct Indexed
(shortoff,ndx) (ptr + ndx)
op + 1
Byte
00..100FE
Stack
Pointer
Direct Indexed
(shortoff,SP)
(ptr + SP)
op + 1
Byte
00..(FF+stacktop)
Long
Direct Indexed
(longoff,ndx)
(ptr.w + ndx) op + 1..2 Word
Extended
Direct Indexed
(extoff,ndx)
(ptr.e + ndx) op + 1..3 Ext Word 000000..FFFFFF
000000..01FFFE
The data byte required for operation is found by its memory address, which is defined by the
unsigned addition of an index register (X or Y or SP) with an offset which follows the opcode.
The indexed addressing mode is made of five sub-modes:
Table 25.
No Offset, Long, Short and SP Indexed instructions
Instructions
Functions
LD, LDW
Load
CLR
Clear
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC, ADDW, SUBW
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1’s or 2’s Complement
SLA, SLL, SRL, SRA, RLC, RRC
SWAP
Table 26.
Arithmetic Addition/Subtraction operations
Shift and Rotate Operations
Swap Nibbles
No Offset, Long, Short Indexed Instructions
Instructions
CALL, JP
Table 27.
Functions
Call or Jump subroutine
Extended Indexed Instructions only
Instructions
LDF
Functions
Far Load
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STM8 addressing modes
6.4.1
PM0044
No Offset Indexed addressing mode
There is no offset, (no extra byte after the op-code), but only allows 00..FF addressing
space.
Example:
00B8
05F2
05F4
11223344 table
AEB8
F6
dc.w $1122, $3344
LD
X,#table
LD
A,(X)
Action:
X = table
A = (X) = (table) = ($B8) = $11
Figure 11. No Offset Indexed addressing mode example
Before completion
A
Previous Value
Table .word 1122
11
00B8
22
00B9
33
00BA
44
00BB
X
B8
Steps to determine
Effective Address
PC = 05F4
EA = X + 0000 = 00B8
PC
LD A,(X)
F6
05F4
05F4
EA
00B8
After completion
A
Table .word 1122
11
00B8
Instruction Complete
11
A = (EA) = 11
22
X
33
New PC = PC +1 = 05F5
B8
44
LD A,(X)
F6
05F4
New PC
05F5
05F5
VR02059C
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Doc ID 13590 Rev 3
PM0044
6.4.2
STM8 addressing modes
Short Indexed addressing mode
The offset is a byte, thus requires only one byte after the op-code, but only allows 00..1FE
addressing space.
Example:
0089 11223344
0759 AE03
075B E689
$11223344
X,#3
A,(table,X)
table dc.l
LD
LD
Action:
X = 3
A = (table, X) = ($89, X) = ($89, 3) = ($8C) = $44
Figure 12. Short Indexed - 8-bit offset - addressing mode example
Before completion
A
Table .long 11223344
Steps to determine
Previous Value
11
0089
22
008A
X
33
008B
03
44
008C
Effective Address
PC = 075B
PC = PC + 1 = 075C
EA = (PC) + X = 89 + 03 = 008C
PC
LD A, (table,X)
E6
075B
89
075C
075B
075D
03
89
Adder
EA
008C
After Completion
Table .long 11223344
Instruction Complete
11
0089
22
008A
A
33
008B
44
44
008C
X
A = (EA) = 44
New PC = PC + 1 = 075D
03
LD A, (table,X)
E6
075B
89
075C
New PC
075D
075D
VR02059D
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STM8 addressing modes
6.4.3
PM0044
SP Indexed addressing mode
The offset is a byte, thus require only one byte after the op-code, but only allow 00..(FF +
stack top) addressing space.
Example:
0086 4B11
0087 4B22
0088 4B33
0089 7B03
PUSH #$11
PUSH #$22
PUSH #$33
LD A,($03,SP)
Action:
A = ($03, SP) = ($03, $1FFC) = ($1FFF) = $11
Figure 13. SP Indexed - 8-bit offset - addressing mode example
Before completion
PC
LD A, ($03,SP)
7B
0089
03
008A
Steps to determine
0089
effective address
A
008B
PC = 0089
Previous Value
PC = PC + 1 = 008A
EA = (PC) + SP=03+1FFC= 1FFF
SP
1FFC
33
1FFD
22
1FFE
11
1FFF
1FFC
1FFC
03
Adder
EA
1FFF
After completion
LD A, ($03,SP)
7B
0089
03
008A
008B
New PC
008B
Instruction Complete
A = (EA) = 11
New PC = PC+1 = 008B
SP
1FFC
1FFC
33
1FFD
22
1FFE
A
11
1FFF
11
VR02059D
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PM0044
6.4.4
STM8 addressing modes
Long Indexed addressing mode
The offset is a word, thus allowing up to 128 KB addressing space, but requires 2 bytes after
the op-code.
Example:
0690 AE02
0692 D6077E
077E BF
table
86
DBCF
Action:
X = 2
A = (table, X) =
LD X,#2
LD A,(table,X)
dc.b $BF
dc.b $86
dc.w $DBCF
($077E, X) = ($077E, 2) = ($0780) = $DB
Figure 14. Long Indexed - 16-bit offset - addressing mode example
Before completion
PC
LD A, (table, X)
D6
0692
07
0693
7E
0694
Steps to Determine
Effective Address
0692
PC = 0692
X
PC = PC + 1 = 0693
02
table . byte BF
BF
077E
86
077F
DB
0780
CF
0781
EA = (PC):(PC+1) + X
= 077E + 02 = 0780
A
Previous Value
077E
02
Adder
EA
0780
After Completion
X
LD A, (table, X)
table . byte BF
D6
0692
07
0693
7E
0694
New PC
0695
0695
02
A = (EA) = DB
New PC = PC + 2 = 0695
BF
077E
86
077F
A
DB
0780
DB
CF
0781
Doc ID 13590 Rev 3
Instruction Complete
VR02059E
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STM8 addressing modes
6.4.5
PM0044
Extended Indexed (only LDF instruction)
The offset is an extended word, thus allowing 16Mbyte addressing space (from 000000 to
FFFFFF), but requires 3 bytes after the op-code.
Example:
0690
AE02
0692
AF010780
010780 BF
table
86
DDFE
LD
X,#2
LDF A,(table,X)
dc.b
$BF
dc.b
$86
dc.w $DDFE
Action:
X = 2, A = (table, X) = ($010780,X) = ($010780+2)) = ($010782) = $DD
Figure 15. Far Indexed - 16-bit offset - addressing mode example
Before Completion
PC
LDF A, (table, X)
Steps to determine
Effective Address
AF
0692
01
0693
07
0694
X
PC = PC + 1 = 0693
80
0695
02
EA= (PC):(PC+1):(PC+2)+X
0692
PC = 0692
= 010780+02 = 010782
A
Previous Value
table . byte BF
BF
010780
86
010781
DD
010782
FE
010783
010780
02
Adder
EA
010782
After Completion
LD A, (table, X)
Instruction Complete
X
AF
0692
01
0693
A = (EA) = DD
07
0694
New PC = PC+3 = 0696
02
80
0695
New PC
0696
0696
table . byte BF
BF
010780
86
010781
A
DD
010782
DD
FE
010783
VR02059R
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Doc ID 13590 Rev 3
PM0044
6.5
STM8 addressing modes
Indirect (Short Pointer Long, Long Pointer Long)
Table 28.
Overview of Indirect addressing instructions
Addressing mode
Syntax
EA formula
Ptr
Size
Ptr Adr
Dest adr
Short Pointer Long Indirect
((shortptr.w)) ((shortptr.w))
00..FF
Word
0000..FFFF
Long Pointer Long Indirect
((longptr.w))
0000..FFFF Word
0000..FFFF
((longptr.w))
The data byte required for the operation is found by its memory address, located in memory
(pointer).
The pointer address follows the op-code. The indirect addressing mode is made of three
sub-modes:
Table 29.
Available Long Pointer Long and Short Pointer Long Indirect Instructions
Instructions
Functions
LD, LDW
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
CALL, JP
Table 30.
Arithmetic Addition/Subtraction operations
Call or Jump subroutine
Available Long Pointer Long Indirect Instructions
Instructions
Functions
CLR
Clear
TNZ
Test Negative or Zero
CPL, NEG
1’s or 2’s Complement
SLA, SLL, SRL, SRA, RLC, RRC
SWAP
INC, DEC
Shift and Rotate Operations
Swap Nibbles
Increment/Decrement
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STM8 addressing modes
6.6
PM0044
Short Pointer Indirect Long addressing mode
The pointer address is a byte, the pointer size is a word, thus allowing up to 128 KB
addressing space, and requires 1 byte after the op-code.
Example:
0040
42E5
0409
92C640
42E5
11
ptr
var
dc.w
var
LD
A,[shortptr.w]
dc.b
$11
Action:
A = [shortptr.w] = ((shortptr.w)) = (($40.w)) = ($42E5) =
$11
Figure 16. Short Pointer Indirect Long addressing mode example
Before Completion
Steps to determine
Effective Address
ptr .word var
42
0040
E5
0041
A
Previous Value
PC
LD A, [shortptr.w]
92
0409
C6
040A
40
040B
0409
PC = 0409
PC = PC + 2 = 40B
EA = ((PC)) :((PC)+1)
= 42E5
040C
var.byte 0x011
11
42E5
EA
42E5
After Completion
Instruction Complete
ptr .word var
42
0040
E5
0041
A = (EA) = 0x11
New PC = PC +1 = 040C
LD A, [shortptr.w]
92
0409
C6
040A
40
040B
New PC
040C
040C
42E5
0x11
A
var .byte 0x011
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11
Doc ID 13590 Rev 3
PM0044
6.7
STM8 addressing modes
Long Pointer Indirect Long addressing mode
The pointer address is a word, the pointer size is a word, thus allowing 64 KB addressing
space, and requires 2 bytes after the op-code.
Example:
1040
1409
42E5
42E5
72C61040
11
ptr
var
dc.w
LD
dc.b
var
A,[longptr.w]
$11
Action:
A = [longptr.w] = ((longptr.w)) = (($1040.w)) = ($42E5) = $11
Figure 17. Long Pointer Indirect Long addressing mode example
Before Completion
Steps to determine
Effective Address
ptr .word var
42
1040
E5
1041
A
Previous Value
PC
LD A, [longptr.w]
72
1409
C6
140A
10
140B
40
140C
1409
PC = 1409
PC = PC + 2 = 140B
EA =((PC):(PC+1)):
((PC):(PC+1)+1)
= 42E5
140D
EA
var.byte 0x011
11
42E5
42E5
After Completion
Instruction complete
ptr .word var
42
1040
E5
1041
A = (EA) = 0x11
New PC = PC + 2 = 140D
LD A, [longptr.w]
72
1409
C6
140A
10
140B
40
140C
New PC
140D
040D
A
var .byte 0x11
11
42E5
Doc ID 13590 Rev 3
0x11
VR02059G
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STM8 addressing modes
PM0044
6.8
Indirect Indexed (Short Pointer Long, Long Pointer Long,
Long Pointer Extended) addressing mode
Table 31.
Overview of Indirect indexed instructions
Addressing mode
Syntax
EA formula
Ptr Adr
Ptr Size
Dest adr
Short Pointer
Indirect
Long
Indexed ([shortptr.w],ndx) ((shortptr.w) + ndx) 00..FF
Word
000000.01FFFE
Long Pointer
Long
Indirect
Indexed ([longptr.w],ndx)
([longptr.w] +ndx)
00..FFFF
Word
000000.01FFFE
Long Pointer
Extended
Indirect
Indexed ([longptr.e],ndx)
([longptr.e] +ndx)
00..FFFF
Extword
000000.FFFFFE
This is a combination of indirect and indexed addressing mode. The data byte required for
the operation is found by its memory address, which is defined by the unsigned addition of
an index register value (X or Y) with a pointer value located in memory. The pointer address
follows the op-code.
The indirect indexed addressing mode is made of four sub-modes:
Table 32.
Available Long Pointer Long and Short Pointer Long Indirect
Indexed instructions
Instructions
Functions
LD, LDW
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
CALL, JP
Table 33.
Arithmetic Addition/Subtraction operations
Call or Jump subroutine
Available Long Pointer Long Indirect Indexed instructions
Instructions
Functions
CLR
Clear
TNZ
Test Negative or Zero
CPL, NEG
1’s or 2’s Complement
SLA,SLL, SRL, SRA, RLC, RRC
SWAP
INC, DEC
Table 34.
Shift and Rotate Operations
Swap Nibbles
Increment/Decrement
Long Pointer Extended Indirect Indexed instructions instruction
Instructions
LDF
48/162
Functions
Far load
Doc ID 13590 Rev 3
PM0044
6.9
STM8 addressing modes
Short Pointer Indirect Long Indexed addressing mode
The pointer address is a byte, the pointer size is a word, thus allowing up to 128 KB
addressing space, and requires 1 byte after the op-code.
Example:
0089
0800
ptr
dc.w
table
0800
10203040 table dc.b
$10,$20,$30,$40
0690
AE03
LD
X,#3
0692
92D689
LD
A,([shortptr.w],X)
X = 3
A = ([shortptr.w],X) = ((shortptr.w), X)
= (($89.w), 3)
= ($0800,3) = ($0803) = $40
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STM8 addressing modes
PM0044
Figure 18. Short Pointer Indirect Long Indexed addressing mode example
Before completion
ptr .word table
08
0089
00
008A
Steps to determine
Effective Address
PC
LD A,([shortptr.w],X)
table .byte 0x10,0x20,0x30,
0x40
92
0692
D6
0693
89
0694
0692
PC = 0692
PC = PC + 2 = 0694
X
EA = ((PC)) : ((PC)+1) + X
03
EA = 0803
800
A
20
801
Previous value
30
802
40
803
10
800
03
Adder
EA
0803
After completion
ptr .word table
08
0089
00
008A
Instruction Complete
X
LD A,([shortptr.w],X)
table .byte 0x10,0x20,0x30
0x40
50/162
03
92
0692
D6
0693
89
0694
New PC
0695
0695
10
0800
20
0801
30
0802
A
40
0803
40
Doc ID 13590 Rev 3
A = (EA) = 40
New PC = PC + 1 = 0695
PM0044
6.10
STM8 addressing modes
Long Pointer Indirect Long Indexed addressing mode
The pointer address is a word, the pointer size is a word, thus allowing up to 128 KB
addressing space, and requires 2 bytes after the op-code.
Example:
1089
1800
ptr
dc.w table
1800
10203040 table dc.b $10,$20,$30,$40
1690
AE03
LD
X,#3
1692
72D61089
LD
A,([longptr.w],X)
X = 3
A = ([longptr.w],X) = ((longptr.w), X) =
(($1089.w), 3)
= ($1800,3) = ($1803) = $40
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STM8 addressing modes
PM0044
Figure 19. Long Pointer Indirect Long Indexed addressing mode example
Before completion
ptr .word table
18
1089
00
108A
Steps to determine
Effective Address
PC
LD A,([longptr.w],X)
72
1692
D6
1693
10
1692
PC = PC + 2 = 1694
X
1694
1695
03
10
1800
Previous value
20
1801
30
1802
89
PC = 1692
EA = (((PC) : (PC+1)) :
((PC) : (PC+1) +1)) + X
A
EA = 1803
table .byte 0x10,0x20,0x30,
0x40
40
1800
03
Adder
1803
EA
1803
After completion
ptr .word table
18
1089
00
108A
Instruction Complete
X
LD A,([longptr.w],X)
table .byte 0x10,0x20,0x30,
0x40
52/162
03
92
1692
D6
1693
10
1694
89
1695
New PC
1696
1696
10
1800
20
1801
30
1802
A
40
1803
40
Doc ID 13590 Rev 3
A = (EA) = 40
New PC = PC + 2 = 1696
PM0044
6.11
STM8 addressing modes
Long Pointer Indirect Extended Indexed addressing mode
The pointer address is a word, the pointer size is an extended word, thus allowing 16-Mbyte
addressing space, and requires 2 bytes after the op-code.
Example:
1089
180000
ptr
dc.b
page(table), high(table), low(table)
180000 10203040 table dc.b
$10,$20,$30,$40
1690
AE03
LD
X,#3
1692
72A71089
LDF
A,([longptr.e],X)
X = 3
A = ([longptr.e],X) = ((longptr.e), X) =
(($1089.e), 3)
= ($180000,3) = ($180003) = $40
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STM8 addressing modes
PM0044
Figure 20. Long Pointer Indirect Extended Indexed addressing mode example
Before completion
ptr .word table
18
1089
00
108A
00
108B
Steps to Determine
Effective Address
PC
LDF A,([longptr.w],X)
72
1692
A7
1693
10
89
1692
PC = 1692
PC = PC + 2 = 1694
X
1694
1695
EA = (((PC) : (PC+1)) :
((PC) : (PC+1) +1) :
((PC) : (PC+1) +2)) + X
03
A
EA = 180003
table .byte 0x10,0x20,0x30,
0x40
10
180000
20
180001
30
180002
40
180003
Previous value
180000
Adder
EA
03
180003
After completion
ptr .word table
18
1089
00
108A
00
108B
Instruction Complete
A = (EA) = 40
X
LDF A,([longptr.w],X)
table .byte 0x10,0x20,0x30,
0x40
54/162
New PC = PC + 2 = 1696
03
72
1692
A7
1693
10
1694
89
1695
New PC
1696
1696
10
180000
20
180001
30
180002
A
40
180003
40
Doc ID 13590 Rev 3
VR02059I
PM0044
6.12
STM8 addressing modes
Relative Direct addressing mode
Table 35.
Overview of Relative Direct addressing mode instructions
Addressing mode
Direct
Relative
Syntax
off
EA formula
PC = PC + off
Ptr Adr
op + 1
Ptr Size
---
Dest adr
PC +127/-128
This addressing mode is used to modify the PC register value, by adding an 8-bit signed
offset to it. The offset added to the PC register value is relative to the start of the next
instruction.
Table 36.
Available Relative Direct instructions
Instructions
Functions
JRxx
Conditional Jump
JRA
Jump Relative Always
CALLR
Call Relative
The offset follows the op-code.
Example:
04A7
04A9
04AA
2717
9D
9D
jreq
nop
nop
04C0
20FE
skip jra*
skip
; Infinite loop
Action:
if (Z == 1)then PC = PC + $17 = $04A9 + $17 = $04C0
elsePC = PC= $04A9
Doc ID 13590 Rev 3
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STM8 addressing modes
PM0044
Figure 21. Relative Direct addressing mode example
Before completion
CC
Steps to Determine
Z
JREQ SKIP
27
04A7
17
04A8
04A9
Effective Address
PC
04A7
PC = 04A7
02
PC = PC + 1 = 04A8
TEMP = (PC) = 17
04A7
PC = PC +1 = 04A9
Adder
Stop here if there
is no Branch; i.e., Z = 0
EA = PC + TEMP
04A9
= 04A9 + 17
EA
= 04C0
New PC = EA if Branch is taken
After completion
(Branch taken)
CC
Instruction Complete
Z=1
PC
JREQ SKIP
04A7
27
17
New PC = EA = 04C0
04A9
04A8
04A9
04A9
17
Adder
SKIP :
04C0
04C0
New PC
04C0
EA
After completion
(No branch taken)
CC
Z=0
JREQ SKIP
27
17
04A9
56/162
New PC = EA = 04A9
04A7
04A8
Instruction Complete
New PC
04A9
Doc ID 13590 Rev 3
PM0044
6.13
STM8 addressing modes
Bit Direct (Long) addressing mode
Table 37.
Overview of Bit Direct addressing mode instruction
Addressing mode
Bit
Long Direct
Syntax
EA formula
Ptr Adr
Ptr Size
Dest adr
longmem, #pos
(longmem)
op + 1..2
Word
0000..FFFF
The data byte required for the operation is found by its memory address, which follows the
op-code. The bit used for the operation is selected by the bit selector which is encoded in
the instruction op-code.
Table 38.
Available Bit Direct instructions
Instructions
Functions
BRES
Bit Reset
BSET
Bit Set
BCPL
Bit Complement
BCCM
Copy Carry Bit to Memory
The address is a word, thus allowing 0000 to FFFF addressing space, but requires 2 bytes
after the op-code. The bit selector #n (n=0 to 7) selects the nth bit from the byte pointed to by
the address.
Example:
0408
721006E5
06E5
40
coeff
BCPL
coeff, #0
dc.b
$ 40
Action:
(coeff) = ($06E5) XOR 2**0 = $40 XOR $01 = $41
Doc ID 13590 Rev 3
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STM8 addressing modes
PM0044
Figure 22. Bit Long Direct addressing mode example
Before c ompletion
PC
BCPL Coeff,#0
90
0408
10
0409
06
040A
E5
040B
Steps to d etermine
e ffective a ddress
0408
PC = 0408
06E5
PC = PC + 2 = 040A
EA = (PC ) :(PC+1) = 06E5
040C
Coeff .byte 040h
06E5
40
EA
06E5
EA = (PC ): (PC+1) = 06E5
After c ompletion
BCPL Coeff,#0
Coeff .byte 040h
58/162
90
0408
10
0409
06
040A
E5
040B
New PC
040C
040C
06E5
40 XOR 01
41
Doc ID 13590 Rev 3
Instruction c omplete
(EA) = (EA) | 2**0 = 40 | 01 = 41
New PC = PC + 2 = 040C
PM0044
6.14
STM8 addressing modes
Bit Direct (Long) Relative addressing mode
Table 39.
Overview of Bit Direct (Long) Relative addressing mode
Addressing mode
Bit
Long
Direct
Syntax
Relative
EA formula
Ptr Adr
Ptr Size
Dest adr
(longmem)
op + 1..2
Word
0000..FFFF
PC = PC + off
op + 3
Byte
PC +127/128
longmem, #pos, off
This addressing mode is a combination between the Bit Direct addressing mode (for data
addressing) and Relative Direct mode (for PC computation).
The data byte required for the operation is found by its memory address, which follows the
op-code. The bit used for the test operation is selected by the bit selector which is encoded
in the instruction op-code. Following the logical test operation, the PC register value can be
modified, by adding an 8-bit signed offset to it.
Table 40.
Available Bit Direct Relative instructions
Instructions
Functions
BTJT, BTJF
Bit Test and Jump
The data address is a word, thus allowing 0000 to FFFF addressing space (requires 2 bytes
after the op-code). The bit selector #n (n=0 to 7) selects the nth bit from the byte pointed to
by the address. The offset follows the op-code and data address.
Example:
104B 00
DRA
dc.b
bit0 equ
04A7 7201104BFB wait_1
04AC
....
$00
; Port A data
register (input
value)
$0 ; data bit 0
BTJF DRA, bit0, wait_1
cont_0
Action:
Test = select_bit(0, ($4B)) = select_bit(0, DRA)
if (Test /= 1)
then PC = PC + $FB
= $0004AC - $05 =
$0004A7
else
= $0004AC
PC = PC
Doc ID 13590 Rev 3
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STM8 addressing modes
PM0044
Figure 23. Bit Long Direct Relative addressing mode example
DRA .byte
DRA
b0
Steps to Determine
DRA.b0 =? 0
104B
Effective Address
PC
104C
04A7
PC = 04A7
05
PC = PC + 2 = 04A9
EA = (PC):(PC+1) = 104B
04A7
BTJF DRA, #0, wait_1
72
04A7
PC = PC + 2 = 04AB
TEMP = (PC) = FC
01
04A8
10
04A9
04AC
4B
04AA
EA
FB
Test = (EA).b0
Adder
wait_1
PC = PC +1 = 04AC
Stop here if there
is no Branch; i.e., Test = TRUE (1)
04AB
EA = PC + TEMP
= 04AA + FD
After completion
= 04A7
(Branch taken)
New PC = EA if Branch is taken
(EA)
Instruction Complete
b0 = 0
wait_1
BTJF DRA, #0, wait_1
04A7
72
01
04A8
10
04A9
4B
04AA
FB
04AB
04A7
PC
New PC
04AC
New PC = EA = 04A7
04AC
FB
Adder
04A7
EA
After completion
(No branch taken)
(EA)
b0 = 1
wait_1
BTJF DRA, #0, wait_1
72
04A7
01
04A8
10
04A9
4B
04AA
FB
04AB
04AC
60/162
Instruction Complete
New PC = EA = 04AC
New PC
04AC
Doc ID 13590 Rev 3
PM0044
STM8 instruction set
7
STM8 instruction set
7.1
Introduction
This chapter describes all the STM8 instructions. There are 96 and they are described in
alphabetical order. However, they can be classified in 13 main groups as follows:
Table 41.
Instruction groups
Load and
Transfer
LD
LDF
CLR
MOV
Stack
operation
PUSH
POP
PUSH
W
POPW
Increment/
Decrement
INC
DEC
INCW
DECW
Compare and
Tests
CP
TNZ
BCP
CPW
TNZW
Logical
operations
AND
OR
XOR
CPL
CPLW
Bit Operation
BSET
BRES
BCPL
BCCM
Conditional Bit
Test and
Branch
BTJT
BTJF
Arithmetic
operations
NEG
ADC
ADD
SUB
SBC
MUL
DIV
DIVW
NEGW ADDW SUBW
SLL
SRL
SRA
RLC
RRC
SWAP
SLLW
SRLW
SRAW RLCW RRCW
SWAP
RLWA
RRWA
Unconditional
Jump or Call
JRA
JRT
JRF
JP
JPF
CALL
CALLR CALLF
Conditional
Branch/
Execution
JRxx
WFE
Interrupt
management
TRAP
WFI
HALT
IRET
Condition
Code Flag
modification
SIM
RIM
SCF
RCF
CCF
RVF
Shift and
Rotates
Breakpoint/
software break
EXG
LDW
CLRW EXGW
RET
RETF
NOP
BREAK
The instructions are described with one to five bytes.
PC-1
End of previous instruction
PC
Op-code
PC+1..4 Additional word (0 to 4) according to the number of bytes required to compute the
effective address(es)
Doc ID 13590 Rev 3
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STM8 instruction set
PM0044
Using a pre-code (two-byte op-codes)
In order to extend the number of available op-codes for an 8-bit CPU (256 op-codes), four
different pre-code bytes are defined. These pre-codes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC-1
End of previous instruction
PC
Pre-code
PC+1
Op-code
PC+2
Additional word (0 to 3) according to the number of bytes required to compute the
effective address
These pre-bytes are:
0x90 = PDY
Replaces an X based instruction using immediate, direct, indexed or
inherent addressing mode by a Y one.
It also provides read/modify/write instructions using Y indexed
addressing mode with long offset and two bit handling instructions
(BCPL and BCCM)
0x92 = PIX
Replaces an instruction using direct, direct bit, or direct relative
addressing mode to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to
an instruction using indirect X indexed addressing mode.
0x91 = PIY
Replace an instruction using indirect X indexed addressing mode by
a Y one.
0x72 = PWSP
Provide long addressing mode for bit handling and read/modify/write
instructions.
It also provides indirect addressing mode with two byte pointer for
read/modify/write and register/memory instructions.
Finally it provides stack pointer indexed addressing mode on
register/memory instructions.
62/162
Doc ID 13590 Rev 3
PM0044
STM8 instruction set
7.2
Nomenclature
7.2.1
Operators
←
↔
7.2.2
7.2.3
CPU registers
A
X
XL
XH
Y
YL
YH
accumulator
X index register (2 bytes)
least significant byte of the X index register (1 byte)
most significant byte of the X index register (1 byte)
Y index register (2 bytes)
least significant byte of the Y index register (1 byte)
most significant byte of the Y index register (1 byte)
PC
PCL
PCH
PCE
program counter register (3 bytes)
low significant byte of the program counter register (1 byte)
high significant byte of the program counter register (1 byte)
extended significant byte of the program counter register (1 byte)
SP
stack pointer register (2 bytes)
CC
CC.V
CC.I0
CC.H
CC.I1
CC.N
CC.Z
CC.C
Condition code register (1 byte)
overflow flag of the code condition register (1 bit)
interrupt mask bit 0 of the code condition register (1 bit)
half carry flag of the code condition register (1 bit)
interrupt mask bit 1 of the code condition register (1 bit)
negative flag of the code condition register (1 bit)
zero flag of the code condition register (1 bit)
carry flag of the code condition register (1 bit)
Code condition bit value notation
1
0
X
7.2.4
is loaded with ...
has its value exchanged with ...
bit not affected by the instruction
bit forced to 1 by the instruction
bit forced to 0 by the instruction
bit modified by the instruction
Memory and addressing
M(...)
R
R(...)
Rn
XX.B
content of a memory location
8-bit operation result value
8-bit operation result value stored into the register or memory shown inside parentheses
bit n of the operation result value (0≤n≤7)
bit B of the XX register or memory location
imm.b
imm.w
shortmem
longmem
extmem
byte immediate value
16-bit immediate value
memory location with short addressing mode (1 byte)
memory location with long addressing mode (2 bytes)
memory location with extended addressing mode (3 bytes)
shortoff
longoff
extoff
short offset (1 byte)
long offset (2 bytes)
extended offset (3 bytes)
[shortptr.w] short pointer (1 byte) on long memory location (2 bytes). Assembler notation = [$12.w].
[longptr.w] long pointer (2 bytes) on long memory location (2 bytes). Assembler notation = [$1234.w]
[longptr.e] long pointer (2 bytes) on extended memory location (3 bytes). Assembler notation = [$1234.e]
Doc ID 13590 Rev 3
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STM8 instruction set
Operation code notation
extended order byte of 24-bit extended address
high order byte of 16-bit long address or middle order byte of 24-bit extended address
short address or low order byte of 16-bit long address or 24-bit extended address
immediate data byte or low order byte of 16-bit immediate data
high order byte of 16-bit immediate data
relative offset byte in a range of [-128..+127]
7.3
Instruction set summary
Table 42.
Instruction set summary
64/162
Set if there is a carry from bit 3 to 4 Set if there is a carry from bit 3 to 4
cleared otherwise
cleared otherwise
ADC A,($12,SP)
A ← A + M(SP+shortoff) +
CC.C
19 bb
1
ADD A,($12,SP)
A ← A + M(SP+shortoff)
1B bb
1
ADD SP,#$12
SP ← SP + imm.b
5B ii
2
X ←-X + M(SP+shortoff)
72 FB bb
2
A ← A AND
M(SP+shortoff)
14 bb
1
-
-
-
-
-
-
-
ADDW X,($12,SP)
-
-
-
AND A,($12,SP)
-
Example
opcode(s)
Set if R7 is set
cleared otherwise
Set if R=$00
cleared otherwise
Set if there is a carry from R7
cleared otherwise
Logical AND
C
-
-
Operation
Set if R7 is set
cleared otherwise
Set if R=$00
cleared otherwise
Set if there is a carry from R7
cleared otherwise
AND
Z
Set if R15 is set
cleared otherwise
Set if R=$0000
cleared otherwise
Set if there is a carry from R15
cleared otherwise
Add word
without carry
N
Set if R7 is set
cleared otherwise
Set if R=$00
cleared otherwise
ADDW
I0
Set if there is a carry from bit 7 to 8
cleared otherwise
Add without
carry
H
Set if the carry from R6 is
different from the carry bit C
ADD
I1
Set if the carry from R6 is
different from the carry bit C
Add with carry
V
Set if the carry from R14 is
different from the carry bit C
ADC
Syntax example
-
Mnemo
Effect on CC register
Description
-
-
-
-
Doc ID 13590 Rev 3
Pipe
ee
ww
bb
ii
iw
rr
Cycles(1)
7.2.5
PM0044
PM0044
STM8 instruction set
Instruction set summary (continued)
BCCM
Copy carry
in memory bit
BCP
Logical bit
compare
BCPL
Complement bit
in memory
-
-
-
-
-
-
-
BCPL $1234,#1
BREAK
Software
breakpoint
-
-
-
-
-
-
-
SW-BREAK
BRES
Bit reset
-
-
-
-
-
-
-
BRES $1234,#1
M(longmem).bit ← 0
72 1n ww bb
n= 1 + 2*bit
1
BSET
Bit set
-
-
-
-
-
-
-
BSET $1234,#1
M(longmem).bit ← 1
72 1n ww bb
n= 2*bit
1
BTJF
Bit test and
relative
jump if
condition is
false
-
-
-
-
-
-
tested
bit
BTJF $1234,#1,label
if M(longmem).bit=0
then PC ← PC + 4 + rr
else PC ← PC + 4
72 0n ww bb
n= 1 + 2*bit
2/3
BTJT
Bit test and
relative
jump if
condition is true
-
-
-
-
-
-
tested
bit
BTJT $1234,#1,label
if M(longmem).bit=1
then PC ← PC + 4 + rr
else PC ← PC + 4
72 0n ww bb
n= 2*bit
2/3
CALL
Call to
Subroutine with
address in
same section
CALL [$1234.w]
PC ← PC + 4
M(SP--) ← PCL
M(SP--) ← PCH
PCH ← M(longmem)
PCL← M(longmem + 1)
72 CD ww bb
6
Flush
CALLF
Call to
subroutine
with extended
address
-
-
-
-
-
-
-
CALLF $123456
PC ← PC+4
M(SP--) ← PCL
M(SP--) ← PCH
M(SP--) ← PCE
PC ← extmem
8D ee ww bb
5
Flush
CALLR
Call Subroutine
relative
-
-
-
-
-
-
-
CALLR label
PC ← PC + 4
M(SP--) ← PCL
M(SP--) ← PCH
PC ← PC + rr
AD bb
4
Flush
CCF
Complement
carry flag
-
-
-
-
-
-
C
CCF
CC.C ← CC.C
8C
1
CLR
Clears the
destination byte
-
-
-
-
0
1
-
CLR ([$1234.w],X)
M( M(longmem).w + X ) ←
0x00
72 6F ww bb
4
CLRW
Clears the
destination
index register
-
-
-
-
0
1
-
CLRW X
X ← 0x0000
5F
1
CP
Compare
-
-
-
CP A,($12,SP)
test { A - M(SP+shortoff) }
11 bb
1
Syntax example
Operation
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
BCCM $1234,#1
M(longmem).bit ← CC.C
-
-
-
-
BCP A,($12,SP)
test {A AND
M(SP+shortoff) }
N and Z are updated
accordingly
M(longmem).bit ←
M(longmem).bit
-
-
-
-
-
-
Set if R7 is set
cleared otherwise
Set if R=$00
cleared otherwise
Set if A 0
Description
Read the destination byte, test the corresponding bit (bit position), and
jump to 'rel' label if the bit is true (1), else continue the program to the next
instruction. The tested bit is saved in the C flag. The destination is a
memory byte. The bit position is a constant. The jump label represents a
signed offset to be added to the current PC/instruction address (relative
jump). This instruction is used for boolean variable manipulation, hardware
register flag tests, or I/O polling.
Instruction overview
Affected condition flags
mnem
BTJT
dst
bit position
Mem
C⇒
jump label
#pos
rel
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
C
Tested bit is saved in the C flag.
Detailed description
dst
pos = 0..7
Asm
cy
lgth
longmem
n= 2*pos
BTJT
$1000,#1,loop
2/3
5
Op-code(s)
72
0n
MS LS
ST7
XX
See also: BTJF
Doc ID 13590 Rev 3
87/162
STM8 instruction set
PM0044
CALL
CALL
CALL Subroutine
(Absolute)
Operation
PC = PC+lgth
(SP--) = PCL
(SP--) = PCH
PC = dst
Description
The current PC register value is pushed onto the stack, then PC is loaded
with the destination address in same section of memory. The CALL
destination and the instruction following the CALL should be in the same
section as PCE is not stacked. The corresponding RET instruction should
be executed in the same section. This instruction should be used versus
CALLR when developing a program.
Instruction overview
Affected condition flags
mnem
dst
CALL
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
dst
cy
lgth
CALL $1000
4
3
(X)
CALL(X)
4
1
FD
(shortoff,X)
CALL($10,X)
4
2
ED
XX
(longoff,X)
CALL($1000,X)
4
3
DD
MS
(Y)
CALL(Y)
4
2
90
FD
(shortoff,Y)
CALL($10,Y)
4
3
90
ED
XX
(longoff,Y)
CALL($1000,Y)
4
4
90
DD
MS
[shortptr.w]
CALL[$10.w]
6
3
92
CD
XX
[longptr.w]
CALL[$1000.w]
6
4
72
CD
MS
([shortptr.w],X) CALL([$10.w],X)
6
3
92
DD
XX
([longptr.w],X)
6
4
72
DD
MS
6
3
91
DD
XX
longmem
Asm
CALL([$1000.w],X)
([shortptr.w],Y) CALL([$10.w],Y)
See also:RET, CALLR, CALLF
88/162
Doc ID 13590 Rev 3
Op-code(s)
CD
MS
ST7
LS
✗
✗
✗
LS
✗
✗
✗
LS
✗
✗
LS
✗
LS
✗
PM0044
STM8 instruction set
CALLF
CALLF
CALL Far Subroutine
Syntax
CALLF dst
e.g. CALLF label
Operation
PC = PC+lgth
(SP--) = PCL
(SP--) = PCH
(SP--) = PCE
PC = dst
Description
The current PC register value is pushed onto the stack, then PC is loaded
with the destination address.This instruction is used with extended memory
addresses. For safe memory usage, a function which crosses sections
must be called by CALLF.
Instruction overview
Affected condition flags
mnem
dst
CALLF
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
dst
Asm
cy
lgth
extmem
CALLF $35AA00
5
4
[longptr.e]
CALLF [$2FFC.e]
8
4
See also:
Op-code(s)
92
8D
ExtB
MS
8D
MS
LS
ST7
LS
RETF, CALL, JPF
Doc ID 13590 Rev 3
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STM8 instruction set
PM0044
CALLR
CALLR
CALL Subroutine Relative
Syntax
CALLR dst
e.g. CALLR chk_pol
Operation
PC = PC+lgth
(SP--) = PCL
(SP--) = PCH
PC = PC + dst
Description
The current PC register value is pushed onto the stack, then PC is loaded
with the relative destination address. This instruction is used, once a
program is debugged, to shrink the overall program size. The CALLR
destination and the corresponding RET instruction address must be in the
same section, as PCE is not stacked.
Instruction overview
Affected condition flags
mnem
dst
CALLR
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
dst
Asm
cy
lgth
shortmem
CALLR $10
4
2
See also: CALL, RET
90/162
Doc ID 13590 Rev 3
Op-code(s)
AD
XX
ST7
✗
PM0044
STM8 instruction set
CCF
CCF
Complement Carry Flag
Syntax
CCF
Operation
CC.C <- CC.C
Description
Complements the Carry flag of the Condition Code (CC) register.
Instruction overview
Affected condition flags
mnem
CCF
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
C
C =C ,
Complements the carry flag of the CC register.
Detailed description
Addressing
mode
Inherent
Asm
CCF
cy
lgth
1
1
Op-code(s)
ST7
8C
See also: RCF, SCF
Doc ID 13590 Rev 3
91/162
STM8 instruction set
PM0044
CLR
CLR
Clear
Syntax
CLR dst
e.g. CLR A
Operation
dst <= 00
Description
The destination byte is forced to 00 value. The destination is either a
memory byte location or the accumulator. This instruction is compact, and
does not affect any register when used with RAM variables.
Instruction overview
Affected condition flags
mnem
dst
CLR
Mem
CLR
A
V
I1
H
I0
N
Z
C
-
-
-
-
0
1
-
0
1
N: 0
Cleared
Z: 1
Set
Detailed description
dst
cy
lgth
CLR A
1
1
shortmem
CLR $10
1
2
longmem
CLR $1000
1
4
CLR (X)
1
1
A
(X)
Asm
✗
72
3F
XX
5F
MS
✗
CLR ($10,X)
1
2
6F
XX
CLR ($1000,X)
1
4
72
4F
MS
CLR (Y)
1
2
90
7F
✗
LS
✗
(shortoff,Y)
CLR ($10,Y)
1
3
90
6F
XX
(longoff,Y)
CLR ($1000,Y)
1
4
90
4F
MS
(shortoff,SP)
CLR ($10,SP)
1
2
0F
XX
[shortptr.w]
CLR [$10]
4
3
92
3F
XX
[longptr.w]
CLR [$1000].w
4
4
72
3F
MS
([shortptr.w],X) CLR ([$10],X)
4
3
92
6F
XX
CLR
([longptr.w].X]
([$1000.w],X)
4
4
72
6F
MS
([shortptr.w],Y) CLR ([$10],Y)
4
3
91
6F
XX
Doc ID 13590 Rev 3
✗
LS
7F
(longoff,X)
See also: LD
ST7
4F
(shortoff.X)
(Y)
92/162
Op-code(s)
✗
LS
✗
LS
✗
LS
✗
PM0044
STM8 instruction set
CLRW
CLRW
Clear word
Syntax
CLRW dst
e.g. CLRW X
Operation
dst <= 00
Description
The destination is forced to 0000 value. The destination is an index
register.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
CLRW
X
-
-
-
-
0
1
-
CLRW
Y
-
-
-
-
0
1
-
N: 0
Cleared
Z: 1
Set
Detailed description
dst
Asm
cy
lgth
X
CLRW X
1
1
Y
CLRW Y
1
2
Op-code(s)
ST7
5F
90
5F
See also: LD
Doc ID 13590 Rev 3
93/162
STM8 instruction set
PM0044
CP
CP
Compare
Syntax
CP dst,src
e.g. CP A,(tbl,X)
Operation
{N, Z, C} = Test (dst - src)
Description
The source byte is subtracted from the destination byte and the result
is lost. However, N, Z, C flags of Condition Code (CC) register are updated
according to the result.The destination is a register, and the source is a
memory or data byte. This instruction generally is used just before a
conditional jump instruction.
Instruction overview
Affected condition flags
mnem
dst
CP
src
Reg
Mem
V
I1
H
I0
N
Z
C
V
-
-
-
N
Z
C
(A7.M7 + A7.R7 + A7.M7.R7) ⊕ (A6.M6 + A6.R6 + A6.M6.R6)
Set if the signed subtraction of the destination (dst) value from the
source (src) value generates a signed overflow (signed result cannot be
represented on 8 bits).
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
(A7.M7 + A7.R7 + A7.M7.R7)
Set if the unsigned value of the contents of source (src) is larger than the
unsigned value of the destination (dst), cleared otherwise.
V⇒
N⇒
Z⇒
C⇒
Detailed description
dst
src
Asm
cy
Op-code(s)
ST7
A
#byte
CP A,#$10
1
2
A1
XX
✗
A
shortmem
CP A,$10
1
2
B1
XX
✗
A
longmem
CP A,$1000
1
3
C1
MS LS
✗
A
(X)
CP A,(X)
1
1
F1
A
(shortoff,X)
CP A,($10,X)
1
2
E1
XX
✗
A
(longoff,X)
CP A,($1000,X)
1
3
D1
MS LS
✗
A
(Y)
CP A,(Y)
1
2
90
F1
A
(shortoff,Y)
CP A,($10,Y)
1
3
90
E1
XX
✗
A
(longoff,Y)
CP A,($1000,Y)
1
4
90
D1
MS LS
✗
A
(shortoff,SP)
CP A,($10,SP)
1
2
11
XX
✗
✗
A
[shortptr.w]
CP A,[$10.w]
4
3
92
C1
XX
A
[longptr.w]
CP A,[$1000.w]
4
4
72
C1
MS LS
A
([shortptr.w],X)
CP A,([$10.w],X)
4
3
92
D1
XX
A
([longptr.w],X)
CP A,([$1000.w],X)
4
4
72
D1
MS LS
A
([shortptr.w],Y)
CP A,([$10.w],Y)
4
3
91
D1
XX
See also: CPW, TNZ, BCP
94/162
lgth
Doc ID 13590 Rev 3
✗
✗
✗
PM0044
STM8 instruction set
CPW
CPW
Compare word
Syntax
CPW dst,src
e.g. CPW Y,(tbl,X)
Operation
{N, Z, C} = Test (dst - src)
Description
The source byte is subtracted from the destination byte and the result is
lost. However, N, Z, C flags of Condition Code (CC) register are updated
according to the result. The destination is an index register, and the source
is a memory or data word. This instruction generally is used just before a
conditional jump instruction.
Instruction overview
Affected condition flags
mnem
dst
CPW
Reg
src
Mem
V
I1
H
I0
N
Z
C
V
-
-
-
N
Z
C
V⇒
(X15.M15 + X15.R15 + X15.M15.R15) ⊕ (X14.M14 + X14.R14 + X14.M14.R14)
Set if the signed subtraction of the destination (dst) value from the source (src)
value generates a signed overflow (signed result cannot be represented on 16
bits).
N⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
(X15.M15 + X15.R15 + X15.M15.R15)
Set if the unsigned value of the contents of source (src) is larger than the
unsigned value of the destination (dst), cleared otherwise.
Detailed description
dst
src
Asm
CPW X,#$10
cy
lgth
Op-code(s)
ST7
2
3
A3 MS LS
✗
X
#word
X
shortmem
CPW X,$10
2
2
B3 XX
✗
X
longmem
CPW X,$1000
2
3
C3 MS LS
✗
X
(Y)
CPW X,(Y)
2
2
F3
✗
90
X
(shortoff,Y)
CPW X,($10,Y)
2
3
90
E3 XX
✗
X
(longoff,Y)
CPW X,($1000,Y)
2
4
90
D3 MS LS
✗
X
(shortoff,SP)
CPW X,($10,SP)
2
2
X
[shortptr.w]
CPW X,[$10.w]
5
3
92
C3 XX
X
[longptr.w]
CPW X,[$1000.w]
5
4
72
C3 MS LS
X
([shortptr.w],Y)
CPW X,([$10.w],Y)
5
3
91
D3 XX
Doc ID 13590 Rev 3
13
XX
✗
✗
95/162
STM8 instruction set
PM0044
CPW detailed description (Continued)
dst
Note:
src
Asm
lgth
Op-code(s)
ST7
Y
#word
CPW Y,#$10
2
4
90
A3 MS LS
✗
Y
shortmem
CPW Y,$10
2
3
90
B3
XX
✗
Y
longmem
CPW Y,$1000
2
4
90
C3 MS LS
✗
Y
(X)
CPW Y,(X)
2
1
F3
✗
Y
(shortoff,X)
CPW Y,($10,X)
2
2
E3
Y
(longoff,X)
CPW Y,($1000,X)
2
3
Y
[shortptr.w]
CPW Y,[$10.w]
5
3
91
Y
([shortptr.w],X) CPW Y,([$10.w],X)
5
3
Y
([longptr.w],X)
5
4
CPW Y,([$1000.w],X)
XX
✗
D3 MS LS
✗
C3 XX
✗
92
D3 XX
✗
72
D3 MS LS
CPW Y, (shortoff, SP) is not implemented, but can be emulated through a macro using
EXGW X,Y & CPW X, (shortoff, SP)
See also: CP, TNZW, BCP
96/162
cy
Doc ID 13590 Rev 3
PM0044
STM8 instruction set
CPL
CPL
Logical 1’s Complement
Syntax
CPL dst
e.g. CPL (X)
Operation
dst <= dst XOR FF, or FF - dst
Description
The destination byte is read, then each bit is toggled (inverted) and the
result is written to the destination byte. The destination is either a memory
byte or a register. This instruction is compact, and does not affect any
registers when used with RAM variables.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
CPL
Mem
-
-
-
-
N
Z
1
CPL
Reg
-
-
-
-
N
Z
1
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z ⇒R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
1
Set.
Detailed description
dst
Asm
cy
lgth
Op-code(s)
✗
A
CPL A
1
1
43
shortmem
CPL$10
1
2
33
XX
longmem
CPL$1000
1
4
53
MS
72
ST7
✗
LS
✗
(X)
CPL(X)
1
1
73
(shortoff.X)
CPL($10,X)
1
2
63
XX
(longoff,X)
CPL($1000,X)
1
4
72
43
MS
(Y)
CPL(Y)
1
2
90
73
(shortoff,Y)
CPL($10,Y)
1
3
90
63
XX
90
43
MS
03
XX
✗
33
XX
✗
(longoff,Y)
CPL($1000,Y)
1
4
(shortoff,SP)
CPL($10,SP)
1
2
[shortptr.w]
CPL[$10]
4
3
92
✗
LS
✗
[longptr.w]
CPL[$1000].w
4
4
72
33
MS
([shortptr.w],X)
CPL([$10],X)
4
3
92
63
XX
([longptr.w].X]
CPL([$1000.w],X)
4
4
72
63
MS
([shortptr.w],Y)
CPL([$10],Y)
4
3
91
63
XX
✗
LS
LS
✗
LS
✗
See also: NEG, XOR, AND, OR
Doc ID 13590 Rev 3
97/162
STM8 instruction set
PM0044
CPLW
CPLW
Logical 1’s Complement Word
Syntax
CPLW dst
e.g. CPLW X
Operation
dst <= dst XOR FFFF, or FFFF - dst
Description
The destination index register is read, then each bit is toggled (inverted)
and the result is written back to the destination index register.
Instruction overview
Affected condition flags
mnem
dst
CPLW
Reg
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
1
N⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
1
Set
Detailed description
dst
Asm
cy
lgth
X
CPLW X
2
1
Y
CPWL Y
2
2
See also: CPL, NEGW, XOR, AND, OR
98/162
Doc ID 13590 Rev 3
Op-code(s)
90
ST7
53
✗
53
✗
PM0044
STM8 instruction set
DEC
DEC
Decrement
Syntax
DEC dst
Operation
dst <= dst - 1
Description
The destination byte is read, then decremented by one, and the result is
written to the destination byte. The destination is either a memory byte or a
register. This instruction is compact, and does not affect any registers when
used with RAM variables.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
DEC
Mem
V
-
-
-
N
Z
-
DEC
Reg
V
-
-
-
N
Z
-
(A7.M7 + M7.R7 + R7.A7) ⊕ (A6.M6 + M6.R6 + R6.A6)
Set if the signed operation generates an overflow, cleared otherwise.
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
V⇒
N⇒
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
dst
A
Asm
cy
lgth
Op-code(s)
✗
DEC A
1
1
4A
shortmem
DEC $10
1
2
3A
XX
longmem
DEC $1000
1
4
5A
MS
(X)
72
1
1
7A
DEC($10,X)
1
2
6A
XX
(longoff,X)
DEC($1000,X)
1
4
72
4A
MS
DEC(Y)
1
2
90
7A
DEC($10,Y)
1
3
90
6A
XX
(longoff,Y)
DEC($1000,Y)
1
4
90
4A
MS
(shortoff,SP)
DEC($10,SP)
1
2
0A
XX
[shortptr.w]
DEC[$10]
4
3
92
3A
XX
[longptr.w]
DEC[$1000].w
(shortoff,Y)
4
4
72
3A
MS
4
3
92
6A
XX
([longptr.w].X]
4
4
72
6A
MS
4
3
91
6A
XX
DEC([$1000.w],X)
LS
✗
LS
✗
([shortptr.w],X) DEC([$10],X)
([shortptr.w],Y) DEC([$10],Y)
✗
✗
DEC(X)
(shortoff.X)
(Y)
ST7
✗
LS
✗
LS
✗
LS
✗
See also: DECW, INC
Doc ID 13590 Rev 3
99/162
STM8 instruction set
PM0044
DECW
DECW
Decrement word
Syntax
DECW dst
Operation
dst <= dst - 1
Description
The value of the destination index register is decremented by one.
Instruction overview
Affected condition flags
mnem
dst
DECW
Reg
V
I1
H
I0
N
Z
C
V
-
-
-
N
Z
-
V⇒
(A15.M15 + M15.R15 + R15.A15) ⊕ (A14.M14 + M14.R14 + R14.A14)
Set if the signed operation generates an overflow, cleared otherwise.
N⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
dst
Asm
cy
lgth
X
DECW X
1
1
Y
DECW Y
1
2
See also: INCW, DEC
100/162
Doc ID 13590 Rev 3
Op-code(s)
5A
90
5A
ST7
PM0044
STM8 instruction set
DIV
DIV
Divide (unsigned)
Syntax
DIV dst,A
e.g. DIV X,A
Operation
dst <= dst / A (Quotient)
Description
Divides a 16-bit unsigned value, dividend, contained in an index register (X
or Y) by an 8-bit value, divisor, contained in A. The quotient is placed in the
same index register and the remainder is placed in A.
A <= dst%A (Remainder)
The register values are unchanged in the case of a division by zero.
Note:
Note: This instruction is interruptible, generating a latency of 1 cycle only.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
DIV
X
A
0
-
0
-
0
Z
C
DIV
Y
A
0
-
0
-
0
Z
C
V⇒
0
Reset.
H⇒
0
Reset.
N⇒
0
Reset.
Z⇒
Q15.Q14.Q13.Q12.Q11.Q10.Q9.Q8.Q7.Q6.Q5.Q4.Q3.Q2.Q1.Q0
Set if the quotient is zero (0x0000), cleared otherwise.
C⇒
A7.A6.A5.A4.A3.A2.A1.A0
Set if division by 0, cleared otherwise.
Detailed description
dst
src
Asm
cy
lgth
X
A
Y
A
DIV X,A
2 to 17
1
DIV Y,A
2 to 17
2
Op-code(s)
ST7
62
90
62
See also: DIVW, ADD, ADC, SUB, SBC, MUL
Doc ID 13590 Rev 3
101/162
STM8 instruction set
PM0044
DIVW
DIVW
Divide word (unsigned)
Operation
X <= X / Y (Quotient)
Y <= X%Y (Remainder)
Description
Divides a 16-bit unsigned value, dividend, contained in X register by a
16-bit value, divisor, contained in Y. The quotient is placed in the X register
and the remainder is placed in Y register.
The quotient and remainder values are indeterminate in the case of a
division by zero.
Note:
This instruction is interruptible, generating a latency of 1 cycle only.
Instruction overview
Affected condition flags
mnem
dst
DIV
src
X
V⇒
Y
V
I1
H
I0
N
Z
C
0
-
0
-
0
Z
C
0
Reset
H⇒
0
Reset
N⇒
0
Reset
Z⇒
Q15.Q14.Q13.Q12.Q11.Q10.Q9.Q8.Q7.Q6.Q5.Q4.Q3.Q2.Q1.Q0
Set if the quotient is zero (0x0000), cleared otherwise.
C⇒
Y15.Y14.Y13.Y12.Y11.Y10.Y9.Y8.Y7.Y6.Y5.Y4.Y3.Y2.Y1.Y0
Set if division by 0, cleared otherwise.
Detailed description
dst
src
Asm
cy
lgth
X
Y
DIV X,Y
2 to 17
1
See also: ADD, ADC, SUB, SBC, MUL, DIV
102/162
Doc ID 13590 Rev 3
Op-code(s)
65
ST7
PM0044
STM8 instruction set
EXG
EXG
Exchange register
contents
Syntax
EXG dst, src
Operation
dst <=> src
e.g. EXG A, XL
src <= dst
dst<= src
Description
Exchanges the contents of registers specified in the instruction as shown
below.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
EXG
A
XL
-
-
-
-
-
-
-
EXG
A
YL
-
-
-
-
-
-
-
EXG
A
Mem
-
-
-
-
-
-
-
Detailed description
dst
src
Asm
cy
lgth
Op-code(s)
A
XL
EXG A,XL
1
1
41
A
YL
EXG A,YL
1
1
61
A
longmem
EXG A,$1000
3
3
31
MS
ST7
LS
See also: EXGW, LD
Doc ID 13590 Rev 3
103/162
STM8 instruction set
PM0044
EXGW
EXGW
Exchange Index register
contents
Syntax
EXG dst, src
Operation
dst <=> src
e.g. EXGW X, Y
src <= dst
dst<= src
Description
Exchanges the contents of registers specified in the instruction as shown
below.
Instruction overview
Affected condition flags
mnem
dst
EXGW
src
X
Y
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
dst
src
Asm
cy
lgth
X
Y
EXGW X,Y
1
1
See also: EXG, LDW
104/162
Doc ID 13590 Rev 3
Op-code(s)
51
ST7
PM0044
STM8 instruction set
HALT
HALT
HALT Oscillator
(CPU + Peripherals)
Syntax
HALT
Operation
I1 = 1, I0 = 0, The oscillator is stopped till an interrupt occurs.
Description
The interrupt mask is reset, allowing interrupts to be fetched. Then the
oscillator is stopped thus stopping the CPU and all internal peripherals,
reducing the microcontroller to its lowest possible power consumption. The
microcontroller resumes program execution after an external interrupt or
reset, by restarting the oscillator, and then, fetching the corresponding
external interrupt, which is an I/O interrupt, a specific peripheral interrupt,
or the reset vector.
Instruction overview
Affected condition flags
mnem
HALT
V
I1
H
I0
N
Z
C
-
1
-
0
-
-
-
I1: 1
Set.
I0: 0
Cleared.
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
HALT
10
1
Op-code(s)
8E
ST7
✗
See also: WFI
Doc ID 13590 Rev 3
105/162
STM8 instruction set
PM0044
INC
INC
Increment
Syntax
INC dst
e.g. INC counter
Operation
dst <= dst + 1
Description
The destination byte is read, then incremented by one, and the result is
written to the destination byte. The destination is either a memory byte or a
register. This instruction is compact, and does not affect any registers when
used with RAM variables.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
INC
Mem
V
-
-
-
N
Z
-
INC
A
V
-
-
-
N
Z
-
V⇒
(A7.M7 + M7.R7 + R7.A7) ⊕ (A6.M6 + M6.R6 + R6.A6)
Set if the signed operation generates an overflow, cleared otherwise.
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
dst
Asm
cy
lgth
A
INC A
1
1
shortmem
INC $10
1
2
longmem
INC $1000
1
4
(X)
INC (X)
1
1
(shortoff.X)
INC ($10,X)
1
2
6C
XX
(longoff,X)
INC ($1000,X)
1
4
72
4C
MS
(Y)
INC (Y)
1
2
90
7C
(shortoff,Y)
INC ($10,Y)
1
3
90
6C
XX
(longoff,Y)
INC ($1000,Y)
1
4
90
4C
MS
(shortoff,SP)
INC ($10,SP)
1
2
0C
XX
[shortptr.w]
INC [$10]
4
3
92
3C
XX
[longptr.w]
INC [$1000].w
4
4
72
3C
MS
✗
72
3C
XX
5C
MS
✗
LS
✗
7C
✗
LS
✗
INC ([$10],X)
4
3
92
6C
XX
([longptr.w].X]
INC ([$1000.w],X)
4
4
72
6C
MS
([shortptr.w],Y)
INC ([$10],Y)
4
3
91
6C
XX
Doc ID 13590 Rev 3
ST7
4C
([shortptr.w],X)
See also: INCW, DEC
106/162
Op-code(s)
✗
LS
✗
LS
✗
LS
✗
PM0044
STM8 instruction set
INCW
INCW
Increment word
Syntax
INCW dst
e.g. INCW X
Operation
dst <= dst + 1
Description
The destination index register value is incremented by one.
Instruction overview
Affected condition flags
mnem
dst
INCW
Reg
V
I1
H
I0
N
Z
C
V
-
-
-
N
Z
-
V⇒
(A15.M15 + M15.R15 + R15.A15) ⊕ (A14.M14 + M14.R14 + R14.A14)
Set if the signed operation generates an overflow, cleared otherwise.
N⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
dst
Asm
cy
lgth
X
INCW X
1
1
Y
INCW Y
1
2
Op-code(s)
ST7
5C
90
5C
See also: INC, DECW
Doc ID 13590 Rev 3
107/162
STM8 instruction set
PM0044
INT
INT
Interrupt
Syntax
INT dst
Operation
PC <= dst
Description
This instruction is used only in the interrupt vector table.
Instruction overview
Affected condition flags
mnem
dst
INT
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
dst
Asm
cy
lgth
extmem
INT $2FFFFC
2
4
See also: JP, JPF, CALLF
108/162
Doc ID 13590 Rev 3
Op-code(s)
82
ExtB
ST7
MS
LS
PM0044
STM8 instruction set
IRET
IRET
Interrupt Return
Syntax
IRET
Operation
CC = (++SP)
A = (++SP)
XH = (++SP)
XL = (++SP)
YH = (++SP)
YL = (++SP)
PCE = (++SP)
PCH = (++SP)
PCL = (++SP)
Description
Placed at the end of an interrupt routine, returns to the original program
context before the interrupt occurred. All registers, which have been
saved/pushed onto the stack are restored/popped. The I bit will be reset if
the corresponding bit stored on the stack is zero.
Instruction overview
Affected condition flags
mnem
IRET
V
I1
H
I0
N
Z
C
V
I1
H
I0
N
Z
C
Condition flags set or reset according to the first byte pulled from the stack.
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
IRET
11
1
Op-code(s)
80
ST7
✗
See also: Interrupts, TRAP
Doc ID 13590 Rev 3
109/162
STM8 instruction set
PM0044
JP
JP
Jump (absolute)
Syntax
JP dst
e.g. JP test
Operation
PC <= dst
Description
The unconditional jump, simply replaces the content of PC by destination
address in same section of memory. Control then passes to the statement
addressed by the program counter. This instruction should be used instead
of JRA during S/W development.
Instruction overview
Affected condition flags
mnem
dst
JP
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
dst
longmem
Asm
JP $1000
cy
lgth
1
3
CC
MS
JP(X)
1
1
FC
(shortoff,X)
JP($10,X)
1
2
EC
XX
(longoff,X)
JP($1000,X)
1
3
DC
MS
JP(Y)
1
2
90
FC
(shortoff,Y)
JP($10,Y)
2
3
90
EC
XX
(longoff,Y)
JP($1000,Y)
2
4
90
DC
MS
[shortptr.w]
JP[$10.w]
5
3
92
CC
XX
[longptr.w]
JP[$1000.w]
5
4
72
CC
MS
([shortptr.w],X) JP([$10.w],X)
5
3
92
DC
XX
([longptr.w],X)
5
4
72
DC
MS
5
3
91
DC
XX
See also: JRT
Doc ID 13590 Rev 3
✗
✗
LS
✗
✗
(Y)
JP([$1000.w],X)
LS
ST7
✗
(X)
([shortptr.w],Y) JP([$10.w],Y)
110/162
Op-code(s)
✗
LS
✗
✗
LS
✗
LS
✗
PM0044
STM8 instruction set
JPF
JPF
Jump far
Syntax
JPF dst
e.g.:JPF test
Operation
PC <= dst
Description
The unconditional jump simply replaces the content of the PC by a
destination with an extended address. Control then passes to the
statement addressed by the program counter. For safe memory usage, this
instruction must be used, when the operation crosses a memory section.
Instruction overview
Affected condition flags
mnem
dst
JPF
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
dst
Asm
cy
lgth
extmem
JPF $2FFFFC
2
4
[longptr.e]
JPF [$2FFC.e]
6
4
Op-code(s)
92
ST7
AC
ExtB
MS
AC
MS
LS
LS
See also: JP, CALLF
Doc ID 13590 Rev 3
111/162
STM8 instruction set
PM0044
JRA
JRA
Jump Relative Always
Syntax
JRA dst
e.g. JRA loop
Operation
PC = PC+lgth
PC <= PC + dst, if Condition is True
Description
Unconditional relative jump. PC is updated by the signed addition of PC
and dst. Control then passes to the statement addressed by the program
counter. Else, the program continues normally.
Instruction overview
Affected condition flags
mnem
dst
JRA
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
dst
Asm
cy
lgth
shortoff
JRA $2B
2
2
See also: JP
112/162
Doc ID 13590 Rev 3
Op-code(s)
20
XX
ST7
✗
PM0044
STM8 instruction set
JRxx
JRxx
Conditional Jump
Relative Instruction
Syntax
JRxx dst
e.g. JRxx loop
Operation
PC = PC+lgth
PC <= PC + dst, if Condition is True
Description
Conditional relative jump. PC is updated by the signed addition of PC and
dst, if the condition is true. Control, then passes to the statement
addressed by the program counter. Else, the program continues normally.
Instruction overview
Affected condition flags
mnem
dst
JRxx
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Instruction List
mnem
meaning
JRC
Carry
JREQ
Equal
JRF
sym
Condition
Op-code (OC)
C=1
25
Z=1
27
False
False
21
JRH
Half-Carry
H=1
JRIH
Interrupt Line is High
JRIL
Interrupt Line is Low
JRM
Interrupt Mask
JRMI
Minus
JRNC
Not Carry
JRNE
Not Equal
JRNH
Not Half-Carry
H=0
90
28
JRNM
Not Interrupt Mask
I=0
90
2C
JRNV
Not Overflow
JRPL
Plus
=
I=1
<0
90
29
90
2F
90
2E
90
2D
N=1
<> 0
>= 0
2B
C=0
24
Z=0
26
V=0
28
N=0
2A
JRSGE
Signed Greater or Equal
>=
(N XOR V) = 0
2E
JRSGT
Signed Greater Than
>
(Z OR (N XOR V)) = 0
2C
JRSLE
Signed Lower or Equal
<=
(Z OR (N XOR V)) = 1
2D
JRSLT
Signed Lower Than
<
(N XOR V) = 1
2F
JRT
True
True
20
JRUGE
Unsigned Greater or Equal
C=0
24
JRUGT
Unsigned Greater Than
>
C = 0 and Z = 0
22
JRULE
Unsigned Lower or Equal
<=
C = 1 or Z = 1
23
JRC
Carry
C=1
25
JRULT
Unsigned Lower Than
C=1
25
JRV
Overflow
V=1
29
Detailed description
dst
Asm
cy
lgth
shortoff
shortoff
JRxx $15
JRxx $15
1/2
1/2
2
3
Doc ID 13590 Rev 3
Op-code(s)
90
Op-code
Op-code
XX
XX
ST7
✗
✗
113/162
STM8 instruction set
PM0044
LD
LD
Load
Syntax
LD dst,src
e.g. LD A,#$15
Operation
dst <= src
Description
Load the destination byte with the source byte. The dst and src can be a
register, a byte (low/high) of an index register or a memory/data byte. When
half of an index register is loaded, the other half remains unchanged.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
LD
Reg
Mem
-
-
-
-
N
Z
-
LD
Mem
Reg
-
-
-
-
N
Z
-
LD
Reg
Reg
-
-
-
-
-
-
-
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
dst
114/162
src
Asm
cy
lgth
Op-code(s)
ST7
A
#byte
LD A,#$55
1
2
A6
XX
✗
A
shortmem
LD A,$50
1
2
B6
XX
✗
A
longmem
LD A,$5000
1
3
C6
MS
A
(X)
LD A,(X)
1
1
F6
✗
✗
A
(shortoff,X)
LD A,($50,X)
1
2
E6
XX
A
(longoff,X)
LD A,($5000,X)
1
3
D6
MS
A
(Y)
LD A,(Y)
1
2
90
A
(shortoff,Y)
LD A,($50,Y)
1
3
90
E6
XX
A
(longoff,Y)
LD A,($5000,Y)
1
4
90
D6
MS
A
(shortoff,SP)
LD A,($50,SP)
1
2
7B
XX
A
[shortptr.w]
LD A,[$50.w]
4
3
92
C6
XX
A
[longptr.w]
LD A,[$5000.w]
4
4
72
C6
MS
✗
LS
✗
✗
F6
A
([shortptr.w],X)
LD A,([$50.w],X)
4
3
92
D6
XX
A
([longptr.w],X)
LD A,([$5000.w],X)
4
4
72
D6
MS
A
([shortptr.w],Y)
LD A,([$50.w],Y)
4
3
91
D6
XX
Doc ID 13590 Rev 3
LS
✗
LS
✗
✗
LS
✗
LS
✗
PM0044
STM8 instruction set
LD detailed description (Continued)
dst
src
Asm
cy
lgth
Op-code(s)
shortmem
A
LD $50,A
1
2
B7
XX
longmem
A
LD $5000,A
1
3
C7
MS
(X)
A
LD (X),A
1
1
F7
(shortoff,X)
A
LD ($50,X),A
1
2
E7
XX
(longoff,X)
A
LD ($5000,X),A
1
3
D7
MS
ST7
✗
LS
✗
✗
✗
LS
✗
✗
(Y)
A
LD (Y),A
1
2
90
F7
(shortoff,Y)
A
LD ($50,Y),A
1
3
90
E7
XX
(longoff,Y)
A
LD ($5000,Y),A
1
4
90
D7
MS
✗
LS
✗
(shortoff,SP)
A
LD ($50,SP),A
1
2
6B
XX
[shortptr.w]
A
LD [$50.w],A
4
3
92
C7
XX
[longptr.w]
A
LD [$5000.w],A
4
4
72
C7
MS
([shortptr.w],
X)
A
LD ([$50.w],X),A
4
3
92
D7
XX
([longptr.w],X)
A
LD
([$5000.w],X),A
4
4
72
D7
MS
([shortptr.w],
Y)
A
LD ([$50.w],Y),A
4
3
91
D7
XX
dst
src
Asm
cy
lgth
XL
A
LD XL,A
1
1
97
✗
A
XL
LD A,XL
1
1
9F
✗
YL
A
LD YL,A
1
2
90
97
✗
A
YL
LD A,YL
1
2
90
9F
✗
XH
A
LD XH,A
1
1
95
A
XH
LD A,XH
1
1
9E
YH
A
LD YH,A
1
2
90
95
A
YH
LD A,YH
1
2
90
9E
✗
LS
✗
LS
Op-code(s)
✗
ST7
See also: LDW, LDF, CLR
Doc ID 13590 Rev 3
115/162
STM8 instruction set
PM0044
LDF
LDF
Load Far
Syntax
LDF dst,src
e.g. LDF A,($555555,X)
Operation
dst <= src
Description
Load the destination byte with the source byte. The dst and src can be a
memory location or accumulator register.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
LDF
A
Mem
-
-
-
-
N
Z
-
LDF
Mem
A
-
-
-
-
N
Z
-
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
dst
src
Asm
cy
Op-code(s)
ST7
A
extmem
LDF A, $500000
1
4
BC
ExtB
MS
LS
A
(extoff,X)
LDF A,($500000,X)
1
4
AF
ExtB
MS
LS
A
(extoff,Y)
LDF A,($500000,Y)
1
5
90
AF
ExtB
MS
LS
A
([longptr.e],X) LDF A,([$5000.e],X)
5
4
92
AF
MS
LS
A
([longptr.e],Y) LDF A,([$5000.e],Y)
5
4
91
AF
MS
LS
A
[longptr.e]
5
4
92
BC
MS
LS
dst
LDF A,[$5000.e]
src
Asm
cy
lgth
Op-code(s)
ST7
extmem
A
LDF $500000,A
1
4
BD ExtB
MS
LS
(extoff,X)
A
LDF ($500000,X),A
1
4
A7
ExtB
MS
LS
(extoff,Y)
A
LDF ($500000,Y),A
1
5
90
A7
ExtB
MS
LS
([longptr.e],X)
A
LDF ([$5000.e],X),A
4
4
92
A7
MS
LS
([longptr.e],Y)
A
LDF ([$5000.e],Y),A
4
4
91
A7
MS
LS
[longptr.e]
A
LDF [$5000.e],A
4
4
92
BD
MS
LS
See also: LD, CALLF
116/162
lgth
Doc ID 13590 Rev 3
PM0044
STM8 instruction set
LDW
LDW
Load word
Syntax
LDW dst,src
Operation
dst <= src
e.g. LDW X,#$1500
Description
Load the destination word (16-bit value) with the source word. The dst and
src can be a 16-bit register (X, Y or SP) or a memory/data 16-bit value.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
LD
Reg
Mem
-
-
-
-
N
Z
-
LD
Mem
Reg
-
-
-
-
N
Z
-
LD
Reg
Reg
-
-
-
-
-
-
-
LD
SP
Reg
-
-
-
-
-
-
-
LD
Reg
SP
-
-
-
-
-
-
-
N⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
dst
src
Asm
cy
lgth
Op-code(s)
X
#word
LDW X,#$55AA
2
3
AE
MS
X
shortmem
LDW X,$50
2
2
BE
XX
MS
X
longmem
LDW X,$5000
2
3
CE
X
(X)
LDW X,(X)
2
1
FE
X
(shortoff,X)
LDW X,($50,X)
2
2
EE
XX
X
(longoff,X)
LDW X,($5000,X)
2
3
DE
MS
X
(shortoff,SP)
LDW X,($50,SP)
2
2
1E
XX
X
[shortptr.w]
LDW X,[$50.w]
5
3
92
CE
XX
X
[longptr.w]
LDW X,[$5000.w]
5
4
72
CE
MS
X
([shortptr.w],X) LDW X,([$50.w],X)
5
3
92
DE
XX
X
([longptr.w],X)
5
4
72
DE
MS
dst
src
LDW
X,([$5000.w],X)
Asm
cy
lgth
LS
✗
✗
LS
✗
✗
✗
LS
X
LDW $50,X
2
2
BF
XX
longmem
X
LDW $5000,X
2
3
CF
MS
(X)
Y
LDW (X),Y
2
1
FF
(shortoff,X)
Y
LDW ($50,X),Y
2
2
EF
XX
(longoff,X)
Y
LDW ($5000,X),Y
2
3
DF
MS
✗
✗
LS
✗
LS
Op-code(s)
shortmem
Doc ID 13590 Rev 3
ST7
ST7
✗
LS
✗
LS
117/162
STM8 instruction set
PM0044
LDW detailed description (Continued)
dst
src
cy
lgth
X
LDW ($50,SP),X
2
2
[shortptr.w]
X
LDW [$50.w],X
5
3
92
CF
XX
[longptr.w]
X
LDW [$5000.w],X
5
4
72
CF
MS LS
([shortptr.w],X)
Y
LDW ([$50.w],X),Y
5
3
92
DF
XX
([longptr.w],X)
Y
LDW ([$5000.w],X),Y
5
4
72
DF
MS LS
Asm
cy
lgth
src
ST7
1F
Op-code(s)
✗
✗
ST7
Y
#word
LDW Y,#$55AA
2
4
90
AE
MS LS
✗
Y
shortmem
LDW Y,$50
2
3
90
BE
XX
✗
Y
longmem
LDW Y,$5000
2
4
90
CE
MS LS
✗
Y
(Y)
LDW Y,(Y)
2
2
90
FE
Y
(shortoff,Y)
LDW Y,($50,Y)
2
3
90
EE
XX
✗
Y
(longoff,Y)
LDW Y,($5000,Y)
2
4
90
DE
MS LS
✗
Y
(shortoff,SP)
LDW Y,($50,SP)
2
2
16
XX
Y
[shortptr.w]
LDW Y,[$50.w]
5
3
91
CE
XX
✗
Y
([shortptr.w],Y)
LDW Y,([$50.w],Y)
5
3
91
DE
XX
✗
cy
lgth
dst
src
Asm
✗
Op-code(s)
ST7
shortmem
Y
LDW $50,Y
2
3
90
BF
XX
✗
longmem
Y
LDW $5000,Y
2
4
90
CF
MS LS
✗
(Y)
X
LDW (Y),X
2
2
90
FF
(shortoff,Y)
X
LDW ($50,Y),X
2
3
90
EF
XX
✗
(longoff,Y)
X
LDW ($5000,Y),X
2
4
90
DF
MS LS
✗
(shortoff,SP)
Y
LDW ($50,SP),Y
2
2
17
XX
[shortptr.w]
Y
LDW [$50.w],Y
5
3
91
CF
XX
✗
([shortptr.w],Y)
X
LDW ([$50.w],Y),X
5
3
91
DF
XX
✗
dst
src
cy
lgth
Y
X
LDW Y,X
1
2
X
Y
LDW X,Y
1
1
✗
Op-code(s)
90
ST7
93
✗
93
✗
X
SP
LDW X,SP
1
1
96
✗
SP
X
LDW SP,X
1
1
94
✗
Y
SP
LDW Y,SP
1
2
90
96
✗
SP
Y
LDW SP,Y
1
2
90
94
✗
LDW Y,[longptr.w] and LDW [longptr.w],Y are not implemented. They can be emulated using
EXGW X,Y.
See also: LD, CLRW
118/162
Op-code(s)
(shortoff,SP)
dst
Note:
Asm
Doc ID 13590 Rev 3
PM0044
STM8 instruction set
MOV
MOV
Move
Syntax
MOV dst,src
e.g. MOV $80,#$AA
Operation
dst<= src
Description
Moves a byte of data from a source address to a destination address. Data
is examined as it is moved. The accumulator is not affected.
There are 3 addressing modes for the MOV instruction:
●
An immediate byte to a direct memory location
●
A direct memory location to another direct memory location (from $00
to $FF)
●
A direct memory location to another direct memory location (from
$0000 to $FFFF)
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
MOV
Mem
Imm
-
-
-
-
-
-
-
MOV
Mem
Mem
-
-
-
-
-
-
-
Detailed description
dst
src
Asm
cy
lgth
longmem
#byte
MOV $8000, #$AA
1
4
35
XX
MS
shortmem shortmem
MOV $80,$10
1
3
45
XX2
XX1
longmem
MOV
$8000,$1000
1
5
55
MS2
LS2
longmem
Op-code(s)
ST7
LS
MS1
LS1
See also: LD, EXG
Doc ID 13590 Rev 3
119/162
STM8 instruction set
PM0044
MUL
MUL
Multiply (unsigned)
Syntax
MUL dst,src
e.g. MUL X,A
Operation
dst:src <= dst x src
Description
Multiplies the 8-bit value in index register, low byte, (XL or YL) by the 8-bit
value in the accumulator to obtain a 16-bit unsigned result in the index
register. After the operation, index register contains the 16-bit result. The
accumulator remains unchanged. The initial value of the high byte of the
index register (XH or YH) is ignored.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
MUL
X
XL,A
-
-
0
-
-
-
0
MUL
Y
YL,A
-
-
0
-
-
-
0
C: 0
Cleared.
Detailed description
dst
src
Asm
cy
lgth
X
A
MUL X,A
4
1
Y
A
MUL Y,A
4
2
See also: ADD, ADC, SUB, SBC
120/162
Doc ID 13590 Rev 3
Op-code(s)
42
90
42
ST7
PM0044
STM8 instruction set
NEG
NEG
Negate (Logical 2’s complement)
Syntax
NEG dst
e.g. NEG (X)
Operation
dst <= (dst XOR FF) + 1, or 00 - dst
Description
The destination byte is read, then each bit is toggled (inverted), and the
result is incremented before it is written at the destination byte. The
destination is either a memory byte or a register. The Carry is cleared if the
result is zero. This instruction is used to negate signed values. This
instruction is compact, and does not affect any register when used with
RAM variables.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
NEG
Mem
V
-
-
-
N
Z
C
NEG
A
V
-
-
-
N
Z
C
V⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if there is an arithmetic overflow on the 8-bit representation of the
result. The V bit will set when the content of "dst" was $80 (-128) prior to
the NEG operation, cleared otherwise.
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
R7+R6+R5+R4+R3+R2+R1+R0
Set if a borrow in the implied subtraction from zero, cleared otherwise. The
C bit will be set in all cases except when the contents of "dst" was $00 prior
to the NEG operation.
Detailed description
dst
Asm
cy
lgth
Op-code(s)
✗
A
NEG A
1
1
40
shortmem
NEG $F5
1
2
30
XX
longmem
NEG $F5C2
1
4
50
MS
(X)
NEG(X)
1
1
70
(shortoff,X)
NEG($F5,X)
1
2
60
XX
(longoff,X)
NEG($F5C2,X)
1
4
72
40
MS
(Y)
NEG(Y)
1
2
90
70
(shortoff,Y)
NEG($F5,Y)
1
3
90
60
XX
(longoff,Y)
NEG($F5C2,Y)
1
4
90
40
MS
(shortoff,SP)
NEG($F5,SP)
1
2
00
XX
[shortptr.w]
NEG($F5)
4
3
30
XX
Doc ID 13590 Rev 3
72
92
ST7
✗
LS
✗
✗
LS
✗
✗
LS
✗
121/162
STM8 instruction set
PM0044
NEG detailed description (continued)
dst
Asm
cy
lgth
[longptr.w]
NEG($F5C2.w)
4
4
72
30
MS
([shortptr.w],X)
NEG([$F5],X)
4
3
92
60
XX
([longptr.w],X)
NEG([$F5C2.w],X)
4
4
72
60
MS
([shortptr.w],Y)
NEG([$F5],Y)
4
3
91
60
XX
See also: NEGW, CPL, AND, OR, XOR
122/162
Op-code(s)
Doc ID 13590 Rev 3
ST7
LS
✗
LS
✗
PM0044
STM8 instruction set
NEGW
NEGW
Negate word (Logical 2’s Complement)
Syntax
NEGW dst
e.g. NEGW X
Operation
dst <= (dst XOR FFFF) + 1, or 0000 - dst
Description
The destination word is read, then each bit is toggled (inverted), and the
result is incremented before it is written at the destination word. The
destination is an index register.
Instruction overview.
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
NEGW
X
V
-
-
-
N
Z
C
NEGW
Y
V
-
-
-
N
Z
C
V⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if there is an arithmetic overflow on the 16-bit representation. The V bit
will set when the content of "dst" was $8000 prior to the NEGW operation,
cleared otherwise.
N⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
R15+R14+R13+R12+R11+R10+R9+R8+R7+R6+R5+R4+R3+R2+R1+R0
Set if a borrow in the implied subtraction from zero, cleared otherwise. The
C bit will be set in all cases except when the contents of "dst" was $0000
prior to the NEGW operation.
Detailed description
dst
Asm
cy
lgth
X
NEGW X
2
1
Y
NEGW Y
2
2
Op-code(s)
ST7
50
90
50
See also: NEG, CPLW, AND, OR, XOR
Doc ID 13590 Rev 3
123/162
STM8 instruction set
PM0044
NOP
NOP
No operation
Syntax
NOP
Operation
Description
This is a single byte instruction that does nothing. This instruction can be
used either to disable an instruction, or to build a waiting delay.No register
or memory contents are affected by this instruction
Instruction overview
Affected condition flags
mnem
NOP
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
NOP
1
1
See also: JRF
124/162
Doc ID 13590 Rev 3
Op-code(s)
9D
ST7
✗
PM0044
STM8 instruction set
OR
OR
Logical OR
Syntax
OR A,src
e.g. OR A,#%00110101
Operation
A <= A OR src
Description
The source byte, is logically ORed with the contents of the accumulator
and the result is stored in the accumulator. The source is a memory or data
byte.
Truth table
OR
0
1
0
0
1
1
1
1
Instruction overview
Affected condition flags
mnem
dst
OR
src
A
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
-
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
dst
src
Asm
cy
lgth
Op-code(s)
ST7
A
#byte
OR A,#$55
1
2
AA
XX
✗
A
shortmem
OR A,$10
1
2
BA
XX
✗
MS
A
longmem
OR A,$1000
1
3
CA
A
(X)
OR A,(X)
1
1
FA
A
(shortoff,X)
OR A,($10,X)
1
2
EA
XX
A
(longoff,X)
OR A,($1000,X)
1
3
DA
MS
A
(Y)
OR A,(Y)
1
2
90
LS
✗
✗
✗
LS
✗
✗
FA
A
(shortoff,Y)
OR A,($10,Y)
1
3
90
EA
XX
A
(longoff,Y)
OR A,($1000,Y)
1
4
90
DA
MS
A
(shortoff,SP)
OR A,($10,SP)
1
2
1A
XX
A
[shortptr.w]
OR A,[$10.w]
4
3
92
CA
XX
A
[longptr.w]
OR A,[$1000.w]
4
4
72
CA
MS
A
([shortptr.w],X)
OR A,([$10.w],X)
4
3
92
DA
XX
A
([longptr.w],X)
OR A,([$1000.w],X)
4
4
72
DA
MS
A
([shortptr.w],Y)
OR A,([$1000],Y)
4
3
91
DA
XX
✗
LS
✗
✗
LS
✗
LS
✗
See also: AND, XOR, CPL, NEG
Doc ID 13590 Rev 3
125/162
STM8 instruction set
PM0044
POP
POP
Pop from stack
Syntax
POP dst
e.g. POP CC
Operation
dst <= (++SP)
Description
Restore from the stack a data byte which will be placed in dst location. The
stack pointer is incremented by one. This instruction is used to restore a
register/memory value.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
POP
A
-
-
-
-
-
-
-
POP
CC
V
I1
H
I0
N
Z
C
POP
Mem
-
-
-
-
-
-
-
Detailed description
dst
Asm
cy
lgth
A
POP A
1
1
84
✗
CC
POP CC
1
1
86
✗
longmem
POP $1000
1
3
32
See also: PUSH, POPW
126/162
Doc ID 13590 Rev 3
Op-code(s)
MS
ST7
LS
PM0044
STM8 instruction set
POPW
POPW
Pop word from stack
Syntax
POPW dst
e.g. POPW X
Operation
dstH <= (++SP)
dstL <= (++SP)
Description
Restore from the stack a data value which will be placed in dst location
(index register). The stack pointer is incremented by two. This instruction is
used to restore an index register value.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
POPW
X
-
-
-
-
-
-
-
POPW
Y
-
-
-
-
-
-
-
Detailed description
dst
Asm
cy
lgth
X
POPW X
2
1
Y
POPW Y
2
2
Op-code(s)
90
ST7
85
✗
85
✗
See also: PUSHW, POP
Doc ID 13590 Rev 3
127/162
STM8 instruction set
PM0044
PUSH
PUSH
Push into the Stack
Syntax
PUSH src
e.g.:PUSH A
Operation
(SP--) <= dst
Description
Save into the stack the dst byte location. The stack pointer is decremented
by one. Used to save a register value and a memory byte on to the stack.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
PUSH
A
-
-
-
-
-
-
-
PUSH
CC
-
-
-
-
-
-
-
PUSH
Imm
-
-
-
-
-
-
-
PUSH
Mem
-
-
-
-
-
-
-
Detailed description
dst
Asm
cy
lgth
A
PUSH A
1
1
✗
CC
PUSH CC
1
1
8A
PUSH #$10
1
2
4B
XX
longmem
PUSH $1000
1
3
3B
MS
Doc ID 13590 Rev 3
ST7
✗
88
#byte
See also: POP, PUSHW
128/162
Op-code(s)
LS
PM0044
STM8 instruction set
PUSHW
PUSHW
Push word onto the Stack
Syntax
PUSHW src
e.g. PUSHW X
Operation
(SP--) <= dstL
(SP--) <= dstH
Description
Save the dst index register onto the stack. The stack pointer is
decremented by two. Used to save an index register value onto the stack.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
PUSHW
X
-
-
-
-
-
-
-
PUSHW
Y
-
-
-
-
-
-
-
Detailed description
dst
Asm
cy
lgth
X
PUSHW X
2
1
Y
PUSHW Y
2
2
Op-code(s)
90
ST7
89
✗
89
✗
See also: POPW, PUSH
Doc ID 13590 Rev 3
129/162
STM8 instruction set
PM0044
RCF
RCF
Reset Carry Flag
Syntax
RCF
Operation
C=0
Description
Clear the carry flag of the Condition Code (CC) register. May be used as a
boolean user controlled flags.
Instruction overview
Affected condition flags
mnem
RCF
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
0
C: 0
Cleared.
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
RCF
1
1
See also: SCF, RVF
130/162
Doc ID 13590 Rev 3
Op-code(s)
98
ST7
✗
PM0044
STM8 instruction set
RET
RET
Return from subroutine
Syntax
RET
Operation
MSB (PC) = (++SP)
LSB (PC) = (++SP)
Description
Restore the PC from the stack. The stack pointer is incremented twice. This
instruction, is the last instruction of a subroutine in same section.
Instruction overview
Affected condition flags
mnem
RET
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
RET
4
1
Op-code(s)
81
ST7
✗
See also: CALL, CALLR
Note:
Please note that the RET should be in the same section as the corresponding CALL.
Doc ID 13590 Rev 3
131/162
STM8 instruction set
PM0044
RETF
RETF
Far Return from
subroutine
Syntax
RETF
Operation
PCE = (++SP)
PCH = (++SP)
PCL = (++SP)
Description
Restore the PC from the stack then restore the Condition Code (CC)
register. The stack pointer is incremented three times. This instruction is
the last one of a subroutine in extended memory.
Instruction overview
Affected condition flags
mnem
RETF
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
RETF
5
1
See also: CALLF
132/162
Doc ID 13590 Rev 3
Op-code(s)
87
ST7
PM0044
STM8 instruction set
RIM
RIM
Reset Interrupt
Mask/Enable Interrupt
Syntax
RIM
Operation
I1 = 1, I0 = 0
Description
Clear the Interrupt mask of the Condition Code (CC) register, which enable
interrupts. This instruction is generally put in the main program, after the
reset routine, once all desired interrupts have been properly configured.
This instruction is not needed before WFI and HALT instructions.
Instruction overview
Affected condition flags
mnem
RIM
V
I1
H
I0
N
Z
C
-
1
-
0
-
-
-
I1: 1
Set.
I0: 0
Cleared.
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
RIM
1
1
Op-code(s)
9A
ST7
✗
See also: SIM
Doc ID 13590 Rev 3
133/162
STM8 instruction set
PM0044
RLC
Syntax
RLC
Rotate Left Logical
through Carry
RLC dst
e.g. RLC (X)
Operation
Description
The destination is either a memory byte or a register. This instruction is
compact, and does not affect any register when used with RAM
variables.This instruction shifts all bits of the register or memory, one place
to the left, through the Carry bit. Bit 0 of the result is a copy of the CC.C
value before the operation.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
RLC
Reg
-
-
-
-
N
Z
bit7
RLC
Mem
-
-
-
-
N
Z
bit7
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
b7
Set if, before the shift, the MSB of register or memory was set, cleared
otherwise.
C
b7
b0
Detailed description
dst
Asm
cy
lgth
RLC A
1
1
49
shortmem
RLC $10
1
2
longmem
RLC $1000
1
4
A
(X)
72
ST7
39
XX
✗
✗
59
MS
RLC (X)
1
1
79
(shortoff,X)
RLC ($10,X)
1
2
69
XX
(longoff,X)
RLC ($1000,X)
1
4
72
49
MS
RLC (Y)
1
2
90
79
(shortoff,Y)
RLC ($10,Y)
1
3
90
69
XX
(longoff,Y)
RLC ($1000,Y)
1
4
90
49
MS
(shortoff,SP)
RLC ($10,SP)
1
2
09
XX
[shortptr.w]
RLC [$10]
4
3
92
39
XX
[longptr.w]
RLC [$1000].w
4
4
72
39
MS
([shortptr.w],X)
RLC ([$10],X)
4
3
92
69
XX
([longptr.w],X)
RLC ([$1000.w],X)
4
4
72
69
MS
([shortptr.w],Y)
RLC ([$10],Y)
4
3
91
69
XX
(Y)
See also: RLCW, RRC, SLL, SRL, SRA, ADC, SWAP, SLA
134/162
Op-code(s)
Doc ID 13590 Rev 3
LS
✗
✗
LS
✗
✗
LS
✗
✗
LS
✗
LS
✗
PM0044
STM8 instruction set
RLCW
RLCW
Rotate Word Left Logical
through Carry
Syntax
RLCW dst
e.g. RLCW X
Operation
Description
The destination is an index register. This instruction shifts all bits of the
register one place to the left through Carry bit. Bit 0 of the result is a copy
of CC.C value before the operation.
Instruction overview
Affected condition flags
mnem
dst
RLCW
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
bit15
Reg
N⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
b15
Set if, before the shift, the MSB of register or memory was set, cleared
otherwise.
C
b15
b0
Detailed description
dst
Asm
cy
lgth
X
RLCW X
2
1
Y
RLCW Y
2
2
Op-code(s)
90
ST7
59
✗
59
✗
See also: RLC, RRCW, SLLW, SRLW, SRAW, SWAPW, SLAW
Doc ID 13590 Rev 3
135/162
STM8 instruction set
PM0044
RLWA
RLWA
Rotate Word Left through A
Syntax
RLWA dst
e.g. RLWA Y,A
Operation
A <= dstH <= dstL <= A
Description
The destination index register and Accumulator are rotated left by 1-byte.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
RLWA
X
A
-
-
-
-
N
Z
-
RLWA
Y
A
-
-
-
-
N
Z
-
N⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
dst
src
Asm
cy
lgth
X
A
RLWA X
1
1
Y
A
RLWA Y
1
2
See also: RRWA, SWAPW
136/162
Doc ID 13590 Rev 3
Op-code(s)
02
90
02
ST7
PM0044
STM8 instruction set
RRC
Syntax
RRC
Rotate Right Logical through Carry
RRC dst
e.g. RRC (X)
Operation
Description
The destination is either a memory byte location or a register. This
instruction is compact, and does not affect any register when used with
RAM variables.This instruction shifts all bits of the register or memory, one
place to the right. Bit 7 of the result is a copy of the CC.C bit value before
the operation.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
RRC
Reg
-
-
-
-
N
Z
bit0
RRC
Mem
-
-
-
-
N
Z
bit0
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
b0
Set if, before the shift, the LSB of register or memory was set, cleared
otherwise.
C
b7
b0
Detailed description
dst
Asm
cy
lgth
RRC A
1
1
46
shortmem
RRC $10
1
2
longmem
RRC $1000
1
4
RRC (X)
1
1
76
(shortoff,X)
RRC ($10,X)
1
2
66
XX
(longoff,X)
RRC ($1000,X)
1
4
72
46
MS
A
(X)
(Y)
72
Op-code(s)
ST7
36
XX
✗
56
MS
✗
LS
✗
✗
LS
✗
RRC (Y)
1
2
90
76
(shortoff,Y)
RRC ($10,Y)
1
3
90
66
XX
(longoff,Y)
RRC ($1000,Y)
1
4
90
46
MS
(shortoff,SP)
RRC ($10,SP)
1
2
06
XX
[shortptr.w]
RRC [$10]
4
3
92
36
XX
[longptr.w]
RRC [$1000].w
4
4
72
36
MS
([shortptr.w],X)
RRC ([$10],X)
4
3
92
66
XX
([longptr.w],X)
RRC ([$1000.w],X)
4
4
72
66
MS
([shortptr.w],Y)
RRC ([$10],Y)
4
3
91
66
XX
✗
LS
✗
✗
LS
✗
LS
✗
See also: RLC, SRL, SLL, SRA, SWAP, ADC, SLA
Doc ID 13590 Rev 3
137/162
STM8 instruction set
PM0044
RRCW
RRCW
Rotate Word Right Logical through Carry
Syntax
RRCW dst
e.g. RRCWX
Operation
Description
The destination is an index register. This instruction shifts all bits of the
register or memory, one place to the right, through the Carry bit. Bit 15 of
the result is a copy of the CC.C bit value before the operation.
Instruction overview
Affected condition flags
mnem
dst
RRCW
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
bit0
Reg
N⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
b0
Set if, before the shift, the MSB of register or memory was set, cleared
otherwise.
C
b15
b0
Detailed description
dst
Asm
cy
lgth
X
RRCW X
2
1
Y
RRCW Y
2
2
Op-code(s)
90
56
✗
56
✗
See also: RRC, RLCW, SRLW, SLLW, SRAW, SWAPW, SLAW
138/162
Doc ID 13590 Rev 3
ST7
PM0044
STM8 instruction set
RRWA
RRWA
Rotate Right Word through A
Syntax
RRWA dst
e.g. RRWA Y,A
Operation
A => dstH => dstL => A
Description
The destination index register and Accumulator are rotated right by 1-byte.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
RLWA
X
A
-
-
-
-
N
Z
-
RLWA
Y
A
-
-
-
-
N
Z
-
N⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
dst
src
Asm
cy
lgth
X
A
RRWA X
1
1
Y
A
RRWA Y
1
2
Op-code(s)
ST7
01
90
01
See also: RLWA, SWAPW
Doc ID 13590 Rev 3
139/162
STM8 instruction set
PM0044
RVF
RVF
Reset overflow flag
Syntax
RVF
Operation
V=0
Description
Clear the overflow flag of the Condition Code (CC) register. May be used
as a boolean user controlled flags.
Instruction overview
Affected condition flags
mnem
RCF
V
I1
H
I0
N
Z
C
0
-
-
-
-
-
-
V: 0
Cleared.
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
RVF
1
1
See also: RCF, SCF
140/162
Doc ID 13590 Rev 3
Op-code(s)
9C
ST7
✗
PM0044
STM8 instruction set
SBC
SBC
Subtraction with
Carry/Borrow
Syntax
SBC A,src
e.g. SBC A,#$15
Operation
A <= A- src - C
Description
The source byte, along with the carry flag, is subtracted from the contents
of the accumulator and the result is stored in the accumulator. The source
is a memory or data byte.
Instruction overview
Affected condition flags
mnem
dst
SBC
src
A
Mem
V
I1
H
I0
N
Z
C
V
-
-
-
N
Z
C
V⇒
(A7.M7 + A7.R7 + A7.M7.R7) ⊕ (A6.M6 + A6.R6 + A6.M6.R6)
Set if the signed subtraction generates an overflow, cleared otherwise.
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
A7.M7 + A7.R7 + A7.M7.R7
Set if a borrow request occurred from bit 7 of the result, cleared otherwise.
Detailed description
dst
src
Asm
cy
lgth
Op-code(s)
ST7
A
#byte
SBC A,#$55
1
2
A2
XX
✗
A
shortmem
SBC A,$10
1
2
B2
XX
✗
A
longmem
SBC A,$1000
1
3
C2
MS
A
(X)
SBC A,(X)
1
1
F2
A
(shortoff,X)
SBC A,($10,X)
1
2
E2
XX
A
(longoff,X)
SBC A,($1000,X)
1
3
D2
MS
A
(Y)
SBC A,(Y)
1
2
90
F2
A
(shortoff,Y)
SBC A,($10,Y)
1
3
90
E2
XX
90
D2
MS
12
XX
LS
✗
✗
✗
LS
✗
✗
A
(longoff,Y)
SBC A,($1000,Y)
1
4
A
(shortoff,SP)
SBC A,($10,SP)
1
2
A
[shortptr.w]
SBC A,[$10.w]
4
3
92
C2
XX
A
[longptr.w]
SBC A,[$1000.w]
4
4
72
C2
MS
A
([shortptr.w],X)
SBC
A,([$10.w],X)
4
3
92
D2
XX
A
([longptr.w],X)
SBC
A,([$1000.w],X)
4
4
72
D2
MS
A
([shortptr.w],Y)
SBC
A,([$10.w],Y)
4
3
91
D2
XX
✗
LS
✗
✗
LS
✗
LS
✗
See also: ADD,ADC,SUB, MUL
Doc ID 13590 Rev 3
141/162
STM8 instruction set
PM0044
SCF
SCF
Set Carry Flag
Syntax
SCF
Operation
C=1
Description
Set the carry flag of the Condition Code (CC) register. It may be used as
user controlled flag.
Instruction overview
mnem
SCF
Instruction overview
Affected condition flags
mnem
SCF
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
1
C: 1
Set.
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
SCF
1
1
See also: RCF, RVF
142/162
Doc ID 13590 Rev 3
Op-code(s)
99
ST7
✗
PM0044
STM8 instruction set
SIM
SIM
Set Interrupt
Mask/Disable Interrupt
Syntax
sim
Operation
I1 = 1, I0 = 1
Description
Set the Interrupt mask of the Condition Code (CC) register, which disables
interrupts. This instruction is useless at the beginning of reset routine. It
need not be used at the beginning of interrupt routines as the interrupt level
is set automatically in CC.I[1:0].
Instruction overview
Affected condition flags
mnem
SIM
V
I1
H
I0
N
Z
C
-
1
-
1
-
-
-
I1 and I0: 1
Set.
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
SIM
1
1
Op-code(s)
9B
ST7
✗
See also: RIM
Doc ID 13590 Rev 3
143/162
STM8 instruction set
PM0044
SLL/SLA
Syntax
SLL/SLA
Shift Left Logical/Shift
Left Arithmetic
SLL dst
e.g. SLL (X)
SLA dst
e.g. SLA (X)
Operation
Description
The destination is either a memory byte or a register.It double the affected
value. This instruction is compact, and does not affect any register when
used with RAM variables.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
SLL/SLA
Mem
-
-
-
-
N
Z
bit7
SLL/SLA
Reg
-
-
-
-
N
Z
bit7
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
b7
Set if, before the shift, bit 7 of register or memory was set, cleared
otherwise.
C
b7
b0
0
Detailed description
Asm(1)
cy
lgth
SLL A
1
1
shortmem
SLL $15
1
2
longmem
SLL $1505
1
4
SLL (X)
1
1
dst
A
(X)
72
ST7
✗
48
38
XX
58
MS
✗
LS
✗
78
(shortoff,X)
SLL ($15,X)
1
2
68
XX
(longoff,X)
SLL ($1505,X)
1
4
72
48
MS
SLL (Y)
1
2
90
78
(Y)
144/162
Op-code(s)
✗
LS
✗
(shortoff,Y)
SLL ($15,Y)
1
3
90
68
XX
(longoff,Y)
SLL ($1505,Y)
1
4
90
48
MS
(shortoff,SP)
✗
LS
SLL ($15,SP)
1
2
08
XX
✗
[shortptr.w]
SLL [$15]
4
3
92
38
XX
✗
[longptr.w]
SLL [$1505].w
4
4
72
38
MS
([shortptr.w],X)
SLL ([$15],X)
4
3
92
68
XX
Doc ID 13590 Rev 3
LS
✗
PM0044
STM8 instruction set
([longptr.w],X)
SLL ([$1505.w],X)
4
4
72
68
MS
([shortptr.w],Y)
SLL ([$15],Y)
4
3
91
68
XX
LS
✗
1. For the shift left arithmetic instruction, replace SLL by SLA.
See also: SLA, SRA, SRL, RRC, RLC, SWAP
Doc ID 13590 Rev 3
145/162
STM8 instruction set
PM0044
SLLW/SLAW
Syntax
SLLW/SLAW
Shift Left Logical
Word/Shift Left Arithmetic
Word
SLLW dst
e.g. SLLW X
SLAW dst
e.g. SLAW X
Operation
Description
The destination is an index register.It double the affected value.
Instruction overview
Affected condition flags
mnem
dst
SLLW/SLAW
Reg
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
bit15
N⇒
R15
Set if bit 15of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
b15
Set if, before the shift, bit 15 of register or memory was set, cleared
otherwise.
C
b15
b0
0
Detailed description
Asm(1)
cy
lgth
X
SLLW X
2
1
Y
SLLW Y
2
2
dst
Op-code(s)
58
90
58
1. For the shift left arithmetic word instruction, replace SLLW by SLAW.
See also: SLL, SRAW, SRLW, RRCW, RLCW, SWAPW, SLAW
146/162
Doc ID 13590 Rev 3
ST7
PM0044
STM8 instruction set
SRA
SRA
Shift Right Arithmetic
Syntax
SRA dst
e.g. SRA (X)
Operation
Description
The destination is either a memory byte or a register. It performs an signed
division by 2: The sign bit 7 is not modified.This instruction is compact, and
does not affect any register when used with RAM variables.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
SRA
Reg
-
-
-
-
N
Z
bit0
SRA
Mem
-
-
-
-
N
Z
bit0
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
b0
Set if, before the shift, the LSB of register or memory was set, cleared
otherwise.
b7
b7
b0
C
Detailed description
dst
Asm
cy
lgth
SRA A
1
1
shortmem
SRA $15
1
2
longmem
SRA $1505
1
4
SRA (X)
1
1
A
(X)
Op-code(s)
✗
47
72
37
XX
57
MS
✗
LS
✗
77
(shortoff,X)
SRA ($15,X)
1
2
67
XX
(longoff,X)
SRA ($1505,X)
1
4
72
47
MS
SRA (Y)
1
2
90
77
(Y)
ST7
✗
LS
✗
(shortoff,Y)
SRA ($15,Y)
1
3
90
67
XX
(longoff,Y)
SRA ($1505,Y)
1
4
90
47
MS
(shortoff,SP)
✗
LS
SRA ($15,SP)
1
2
07
XX
✗
[shortptr.w]
SRA [$15]
4
3
92
37
XX
✗
[longptr.w]
SRA [$1505].w
4
4
72
37
MS
([shortptr.w],X)
SRA ([$15],X)
4
3
92
67
XX
([longptr.w],X)
SRA ([$1505.w],X)
4
4
72
67
MS
([shortptr.w],Y)
SRA ([$15],Y)
4
3
91
67
XX
LS
✗
LS
✗
See also: SRAW, SRL, SLL, RRC, RLC, SWAP
Doc ID 13590 Rev 3
147/162
STM8 instruction set
PM0044
SRAW
SRAW
Shift Right Arithmetic
Word
Syntax
SRAW dst
e.g. SRAW X
Operation
Description
The destination is an index register. It performs a signed division by 2. The
sign bit (15) is not modified.
Instruction overview
Affected condition flags
mnem
dst
SRAW
Reg
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
bit0
N⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
C⇒
b0
Set if, before the shift, the LSB of register or memory was set, cleared
otherwise.
b15
b15
b0
C
Detailed description
dst
Asm
cy
lgth
X
SRAW X
2
1
Y
SRAW Y
2
2
Op-code(s)
57
90
See also: SRA, SRLW, SLLW, RRCW, RLCW, SWAPW
148/162
Doc ID 13590 Rev 3
57
ST7
PM0044
STM8 instruction set
SRL
SRL
Shift Right Logical
Syntax
SRL dst
e.g. SRL (X)
Operation
Description
The destination is either a memory byte or a register.It perform an
unsigned division by 2.This instruction is compact, and does not affect any
register when used with RAM variables.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
SRL
Reg
-
-
-
-
N
Z
bit0
SRL
Mem
-
-
-
-
N
Z
bit0
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
C
b0
Set if, before the shift, the LSB of register or memory was set, cleared
otherwise.
0
b7
b0
C
Detailed description
dst
A
Asm
cy
lgth
SRL A
1
1
shortmem
SRL $15
1
2
longmem
SRL $1505
1
4
SRL (X)
1
1
(X)
Op-code(s)
✗
44
72
34
XX
54
MS
✗
LS
✗
74
(shortoff,X)
SRLL ($15,X)
1
2
64
XX
(longoff,X)
SRL ($1505,X)
1
4
72
44
MS
SRL (Y)
1
2
90
74
(Y)
ST7
✗
LS
✗
(shortoff,Y)
SRL ($15,Y)
1
3
90
64
XX
(longoff,Y)
SRL ($1505,Y)
1
4
90
44
MS
(shortoff,SP)
✗
LS
SRL ($15,SP)
1
2
04
XX
✗
[shortptr.w]
SRL [$15]
4
3
92
34
XX
✗
[longptr.w]
SRL [$1505].w
4
4
72
34
MS
([shortptr.w],X)
SRL ([$15],X)
4
3
92
64
XX
([longptr.w],X)
SRL ([$1505.w],X)
4
4
72
64
MS
([shortptr.w],Y)
SRL ([$15],Y)
4
3
91
64
XX
LS
✗
LS
✗
See also: RLC, RRC, SRA, SWAP, SLL, SRLW
Doc ID 13590 Rev 3
149/162
STM8 instruction set
PM0044
SRLW
SRLW
Shift Right Logical Word
Syntax
SRLW dst
e.g. SRLW X
Operation
Description
The destination is an index register. It performs an unsigned division by 2.
Instruction overview
Affected condition flags
mnem
dst
SRLW
Reg
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
bit0
N⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
b0
Set if, before the shift, the LSB of the register was set, cleared
otherwise.
0
b15
b0
C
Detailed description
dst
Asm
cy
lgth
X
SRLW X
2
1
Y
SRLW Y
2
2
Op-code(s)
54
90
54
See also: SRL, RLCW, RRCW, SRLW, SRAW, SWAPW, SLLW
150/162
Doc ID 13590 Rev 3
ST7
PM0044
STM8 instruction set
SUB
SUB
Subtraction
Syntax
SUB A,src
e.g. SUB A,#%11001010
Operation
A <= A- src
Description
The source byte is subtracted from the contents of the accumulator/SP and
the result is stored in the accumulator/SP. The source is a memory or data
byte.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
SUB
A
Mem
V
-
-
-
N
Z
C
SUB
SP
Imm
-
-
-
-
-
-
-
V⇒
(A7.M7 + A7.R7 + A7.M7.R7) ⊕ (A6.M6 + A6.R6 + A6.M6.R6)
Set if the signed operation generates an overflow, cleared otherwise.
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
A7.M7 + A7.R7 + A7.M7.R7
Set if a borrow request occurred from bit 7, cleared otherwise.
Detailed description
dst
src
Asm
cy
lgth
Op-code(s)
ST7
A
#byte
SUB A,#$55
1
2
A0
XX
✗
A
shortmem
SUB A,$10
1
2
B0
XX
✗
A
longmem
SUB A,$1000
1
3
C0
MS
A
(X)
SUB A,(X)
1
1
F0
A
(shortoff,X)
SUB A,($10,X)
1
2
E0
XX
A
(longoff,X)
SUB A,($1000,X)
1
3
D0
MS
A
(Y)
SUB A,(Y)
1
2
90
F0
A
(shortoff,Y)
SUB A,($10,Y)
1
3
90
E0
XX
90
D0
MS
10
XX
C0
XX
✗
LS
✗
✗
(longoff,Y)
SUB A,($1000,Y)
1
4
A
(shortoff,SP)
SUB A,($10,SP)
1
2
A
[shortptr.w]
SUB A,[$10.w]
4
3
A
[longptr.w]
SUB A,[$1000.w]
4
4
72
C0
MS
A
([shortptr.w],X)
SUB A,([$10.w],X)
4
3
92
D0
XX
A
([longptr.w],X)
SUB
A,([$1000.w],X)
4
4
72
D0
MS
A
([shortptr.w],Y)
SUB A,([$10.w],Y)
4
3
91
D0
XX
#byte
SUB SP,#$9
1
2
52
XX
SP
✗
✗
A
92
LS
✗
LS
✗
✗
LS
✗
LS
✗
See also: SUBW, ADD, ADC, SBC, MUL
Doc ID 13590 Rev 3
151/162
STM8 instruction set
PM0044
SUBW
SUBW
Word Subtraction
Syntax
SUBW dst,src
e.g. SUBW X, #$5500
Operation
dst <= dst - src
Description
The source 16-bit word is subtracted from the contents of the destination
index register and the result is stored in the same index register. The
source is a memory or 16-bit data.
Instruction overview
Affected condition flags
mnem
dst
src
V
I1
H
I0
N
Z
C
SUBW
X
Mem
V
-
H
-
N
Z
C
SUBW
Y
Mem
V
-
H
-
N
Z
C
V⇒
(X15.M15 + X15.R15 + X15.M15.R15) ⊕ (X14.M14 + X14.R14 +
X14.M14.R14)
Set if the signed operation generates an overflow, cleared otherwise.
H⇒
X7.M7 + X7.R7 + X7.M7.R7
Set if a carry occurred from bit 7, cleared otherwise.
N⇒
R15
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒
X15.M15 + X15.R15 + X15.M15.R15
Set if a borrow request occurred from bit 15, cleared otherwise.
Detailed description
dst
X
src
#word
Asm
cy
lgth
2
3
SUBW X,#$5500
1D
MS
LS
LS
X
longmem
SUBW X,$1000
2
4
72
B0
MS
X
(shortoff, SP)
SUBW X,($10,SP)
2
3
72
F0
XX
Y
#word
SUBW Y,#$5500
2
4
72
A2
MS
LS
LS
Y
longmem
SUBW Y,$1000
2
4
72
B2
MS
Y
(shortoff, SP)
SUBW Y,($10,SP)
2
3
72
F2
XX
See also: SUB, ADDW, ADC, SBC, MUL
152/162
Op-code(s)
Doc ID 13590 Rev 3
ST7
PM0044
STM8 instruction set
SWAP
Syntax
SWAP
Swap nibbles
SWAP dst
e.g. SWAP counter
Operation
Description
The destination byte upper and low nibbles are swapped over. The
destination is either a memory byte or a register. This instruction is
compact, and does not affect any register when used with RAM variables.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
SWAP
Reg
-
-
-
-
N
Z
-
SWAP
Mem
-
-
-
-
N
Z
-
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
dst
A
Asm
cy
lgth
Op-code(s)
✗
SWAP A
1
1
4E
shortmem
SWAP $15
1
2
3E
XX
longmem
SWAP $1505
1
4
5E
MS
(X)
72
ST7
✗
LS
✗
SWAP (X)
1
1
7E
(shortoff,X)
SWAPL ($15,X)
1
2
6E
XX
(longoff,X)
SWAP ($1505,X)
1
4
72
4E
MS
SWAP (Y)
1
2
90
7E
(shortoff,Y)
SWAP ($15,Y)
1
3
90
6E
XX
(longoff,Y)
SWAP ($1505,Y)
1
4
90
4E
MS
(shortoff,SP)
SWAP ($15,SP)
1
2
0E
XX
✗
[shortptr.w]
SWAP [$15]
4
3
3E
XX
✗
[longptr.w]
SWAP [$1505].w
4
4
72
3E
MS
([shortptr.w],X)
SWAP ([$15],X)
4
3
92
6E
XX
([longptr.w],X)
SWAP ([$1505.w],X)
4
4
72
6E
MS
([shortptr.w],Y)
SWAP ([$15],Y)
4
3
91
6E
XX
(Y)
92
✗
LS
✗
✗
LS
LS
✗
LS
✗
See also: SWAPW, RRC, RLC, SLL, SRL, SRA
Doc ID 13590 Rev 3
153/162
STM8 instruction set
PM0044
SWAPW
Syntax
SWAPW
Swap bytes
SWAPW dst
e.g. SWAPW Y
Operation
Description
The destination index register upper and low bytes are swapped over.
Instruction overview
Affected condition flags
mnem
dst
SWAP
Reg
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
-
N⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
dst
Asm
cy
lgth
X
SWAPW X
1
1
Y
SWAPW Y
1
2
See also: SWAP, RRC, RLC, SLL, SRL, SRA
154/162
Doc ID 13590 Rev 3
Op-code(s)
90
ST7
5E
✗
5E
✗
PM0044
STM8 instruction set
TNZ
TNZ
Test for Negative or Zero
Syntax
TNZ dst
e.g. TNZ A
Operation
{N, Z} = Test(dst)
Description
The destination byte is tested and both N and Z flags of the Condition Code
(CC) register are updated accordingly. This instruction is compact, and
does not affect any register when used with RAM variables.
Instruction overview
Affected condition flags
mnem
dst
V
I1
H
I0
N
Z
C
TNZ
Reg
-
-
-
-
N
Z
-
TNZ
Mem
-
-
-
-
N
Z
-
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
dst
A
Asm
cy
lgth
Op-code(s)
✗
TNZ A
1
1
4D
shortmem
TNZ $15
1
2
3D
XX
longmem
TNZ $1505
1
4
5D
MS
(X)
72
✗
LS
✗
TNZ (X)
1
1
7D
(shortoff,X)
TNZL ($15,X)
1
2
6D
XX
(longoff,X)
TNZ ($1505,X)
1
4
72
4D
MS
TNZ (Y)
1
2
90
7D
(shortoff,Y)
TNZ ($15,Y)
1
3
90
6D
XX
(longoff,Y)
TNZ ($1505,Y)
1
4
90
(shortoff,SP)
TNZ ($15,SP)
1
2
[shortptr.w]
TNZ [$15]
4
3
[longptr.w]
TNZ [$1505].w
4
4
([shortptr.w],X)
TNZ ([$15],X)
4
3
([longptr.w],X)
TNZ ([$1505.w],X)
4
4
([shortptr.w],Y)
TNZ ([$15],Y)
4
3
(Y)
ST7
✗
LS
✗
✗
4D
MS
0D
XX
✗
3D
XX
✗
72
3D
MS
92
6D
XX
72
6D
MS
91
6D
XX
92
LS
LS
✗
LS
✗
See also: TNZW, CP, BCP
Doc ID 13590 Rev 3
155/162
STM8 instruction set
PM0044
TNZW
TNZW
Word Test for Negative or
Zero
Syntax
TNZW dst
e.g. TNZW X
Operation
{N, Z} = Test(dst)
Description
The destination 16-bit word, index register, is tested and both N and Z flags
of the Condition Code (CC) register are updated accordingly.
Instruction overview
Affected condition flags
mnem
dst
TNZW
Reg
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
-
N⇒
R15
Set if bit 15 of the result is set (negative value), cleared otherwise.
Z⇒
R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x0000), cleared otherwise.
Detailed description
dst
Asm
cy
lgth
X
TNZW X
2
1
Y
TNZW Y
2
2
See also: TNZ, CPW
156/162
Doc ID 13590 Rev 3
Op-code(s)
5D
90
5D
ST7
PM0044
STM8 instruction set
TRAP
TRAP
Software interrupt
Syntax
TRAP
Operation
PC = PC + 1
(SP--) = LSB (PC)
(SP--) = MSB (PC)
(SP--) = Ext(PC)
(SP--) = YL
(SP--) = YH
(SP--) = XL
(SP--) = XH
(SP--) = A
(SP--) = CC
PC = TRAP Interrupt Vector Contents
Description
When processed, this instruction forces the trap interrupt to occur and to be
processed. It cannot be masked by the I0 or I1 flags.
Instruction overview
Affected condition flags
mnem
TRAP
V
I1
H
I0
N
Z
C
-
1
-
1
-
-
-
I1 and I0: 1
Set.
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
TRAP
9
1
Op-code(s)
83
ST7
✗
See also: IRET
Doc ID 13590 Rev 3
157/162
STM8 instruction set
PM0044
WFE
WFE
Wait for Event
(CPU stopped,
low power mode)
Syntax
WFE
Operation
The CPU Clock is stopped till an external event occurs. Internal peripherals
are still running. It is used for synchronization with other computing
resources (e.g coprocessor).
Description
The state of the CPU is frozen, waiting for synchronization with an external
event. The CPU clock also is stopped, reducing the power consumption of
the microcontroller. Interrupt requests during this period are served
normally, depending on the CC.I[1:0] value.
Instruction overview
Affected condition flags
mnem
WFE
V
I1
H
I0
N
Z
C
-
-
-
-
-
-
-
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
WFE
1
2
See also: HALT
158/162
Doc ID 13590 Rev 3
Op-code(s)
72
8F
ST7
PM0044
STM8 instruction set
WFI
WFI
Wait for Interrupt
(CPU stopped,
low power mode)
Syntax
WFI
Operation
CC.I1= 1, CC.I0 = 0. The CPU Clock is stopped till an interrupt occurs.
Internal peripherals are still running.
Description
The interrupt flag is cleared, allowing interrupts to be fetched. Then the
CPU clock is stopped, reducing the power consumption of
the microcontroller. The micro will continue the program upon an internal or
external interrupt.
Instruction overview
Affected condition flags
mnem
WFI
V
I1
H
I0
N
Z
C
-
1
-
0
-
-
-
I1: 1
Set.
I0: 0
Cleared.
Detailed description
Addressing
mode
Asm
cy
lgth
Inherent
WFI
10
1
Op-code(s)
8F
ST7
✗
See also: HALT
Doc ID 13590 Rev 3
159/162
STM8 instruction set
PM0044
XOR
XOR
Logical Exclusive OR
Syntax
XOR A,src
e.g. XOR A,#%00110101
Operation
A <= A XOR src
Description
The source byte, is logically XORed with the contents of the accumulator
and the result is stored in the accumulator. The source is a memory or data
byte.
Truth table
XOR
0
1
0
0
1
1
1
0
Instruction overview
Affected condition flags
mnem
dst
XOR
src
A
Mem
V
I1
H
I0
N
Z
C
-
-
-
-
N
Z
-
N⇒
R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒
R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
Detailed description
dst
src
Asm
cy
lgth
ST7
A
#byte
XOR A,#$55
1
2
A8
XX
✗
A
shortmem
XOR A,$10
1
2
B8
XX
✗
A
longmem
XOR A,$1000
1
3
C8
MS
A
(X)
XOR A,(X)
1
1
F8
A
(shortoff,X)
XOR A,($10,X)
1
2
E8
XX
A
(longoff,X)
XOR A,($1000,X)
1
3
D8
MS
A
(Y)
XOR A,(Y)
1
2
90
✗
✗
LS
✗
✗
F8
(shortoff,Y)
XOR A,($10,Y)
1
3
90
E8
XX
A
(longoff,Y)
XOR A,($1000,Y)
1
4
90
D8
MS
A
(shortoff,SP)
XOR A,($10,SP)
1
2
18
XX
A
[shortptr.w]
XOR A,[$10.w]
4
3
92
C8
XX
A
[longptr.w]
XOR A,[$1000.w]
4
4
72
C8
MS
A
([shortptr.w],X)
XOR
A,([$10.w],X)
4
3
92
D8
XX
A
([longptr.w],X)
XOR
A,([$1000.w],X)
4
4
72
D8
MS
A
([shortptr.w],Y)
XOR
A,([$1000],Y)
4
3
91
D8
XX
Doc ID 13590 Rev 3
LS
✗
A
See also: AND, OR, CPL, NEG
160/162
Op-code(s)
✗
LS
✗
✗
LS
✗
LS
✗
PM0044
8
Revision history
Revision history
Table 43.
Document revision history
Date
Revision
14-Jan-2008
1
Initial release.
05-Jun-2008
2
Modified Figure 2: Context save/restore for interrupts on page 14
20-Sep-2011
3
Changes
Changed notation for hexadecimal numbers from XXh to 0xXX.
Removed CPU register context saving from Section 3.2: CPU
registers.
Added LDF in Table 22: Available Extended Direct addressing mode
instructions.
Updated Figure 2: Context save/restore for interrupts.
Added BREAK instruction in Table 41: Instruction groups.
Added Section 5: Pipelined execution.
Table 42: Instruction set summary: updated ADDW, BCCM, BRES,
BSET, BTJF, BTJT, CALLR, DEC, DECW, DIV, EXGW, JRA, JRC,
JREQ, JRH, JRIH, JRIL, JRM, JRMI, JRNC, JRNE, JRNH, JRNM,
JRNV, JRPL, JRSGE, JRSGT, JRSLE, JRSLT, JRUGE, JRULT, LDF,
LDW, MOV, NEG, PUSH, RRCW, SBC, SLA, SLAW, SLL, SLLW,
SRA, SRAW, SRL, SRLW, SUB. Added BREAK and INT instructions.
Section 7: STM8 instruction set: updated ADD, ADDW, BCCM, BCP,
BCPL, BRES, BSET, BTJF, BTJT, CLR, CP, CPW, DEC, DECW,
HALT, INCW, INT, JP, JRxx, MOV, RLWA, RRCW, RRWA, SBC,
SRLW, SUB, and SWAPW. Added BREAK instruction. Merged JRA
with JRL instructions, SLA with SLL, and SLAW with SLLW.
Doc ID 13590 Rev 3
161/162
PM0044
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Doc ID 13590 Rev 3
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No Page Layout : SinglePage Page Mode : UseNone Page Count : 162 Creator : C2 v2.1.0.1 build 007 - c2_rendition_config : Techlit_Active Producer : Acrobat Distiller 8.1.0 (Windows) Title : STM8 CPU programming manual Keywords : Technical Literature, 13590, Product Development, Specification, Programming manual, STM8AF Series, STM8AL Series, STM8AF Automotive Series, STM8L Series, STM8 L series, STM8S Series, STM8AF5166, STM8AF5168, STM8AF5169, STM8AF5176, STM8AF5179, STM8AF5188, STM8AF5189, STM8AF518A, STM8AF5198, STM8AF5199, STM8AF51A8, STM8AF51A9, STM8AF51AA, STM8AF51AB, STM8AF5268, STM8AF5269, STM8AF5288, STM8AF5289, STM8AF528A, STM8AF52A8, STM8AF52A9, STM8AF52AA, STM8AF6123, STM8AF6143, STM8AF6146, STM8AF6166, STM8AF6178, STM8AF6179, STM8AF6189, STM8AF618A, STM8AF6199, STM8AF619A, STM8AF61A8, STM8AF61A9, STM8AF61AB, STM8AF61B9, STM8AF61BA, STM8AF61BB, STM8AF61BC, STM8AF6226, STM8AF6246, STM8AF6248, STM8AF6266, STM8AF6268, STM8AF6269, STM8AF6286, STM8AF6288, STM8AF6289, STM8AF628A, STM8AF62A8, STM8AF62A9, STM8AF62AA, STM8AH5169, STM8AL303, STM8AL3146, STM8AL3148, STM8AL314x, STM8AL316, STM8AL3166, STM8AL3168, STM8AL3L46, STM8AL3L48, STM8AL3L6, STM8AL3L66, STM8AL3L68, STM8L1013DIE, STM8L101F1, STM8L101F2, STM8L101F3, STM8L101G2, STM8L101G3, STM8L101K3, STM8L151C3, STM8L151C4, STM8L151C6, STM8L151C8, STM8L151F2, STM8L151F3, STM8L151G2, STM8L151G3, STM8L151G4, STM8L151G6, STM8L151K2, STM8L151K3, STM8L151K4, STM8L151K6, STM8L151M8, STM8L151R6, STM8L151R8, STM8L1526DIE, STM8L152C4, STM8L152C6, STM8L152C8, STM8L152K4, STM8L152K6, STM8L152M8, STM8L152R6, STM8L152R8, STM8L162M8, STM8L162R8, STM8S003F3, STM8S003K3, STM8S005C6, STM8S005K6, STM8S007C8, STM8S103F2, STM8S103F3, STM8S103K3, STM8S105C4, STM8S105C6, STM8S105K4, STM8S105K6, STM8S105S4, STM8S105S6, STM8S207C6, STM8S207C8, STM8S207CB, STM8S207K6, STM8S207K8, STM8S207M8, STM8S207MB, STM8S207R6, STM8S207R8, STM8S207RB, STM8S207S6, STM8S207S8, STM8S207SB, STM8S208C6, STM8S208C8, STM8S208CB, STM8S208MB, STM8S208R8, STM8S208RB, STM8S208S6, STM8S903F3, STM8S903K3, STM8SPLNB1, STM8TS10FU6, STM8L051F3, STM8L052C6, STM8L052R8, STM8L151, STM8L1513DIE, STM8L151APL, STM8L151C2, STM8L1528DIE, STM8LP10126, STM8LP151T6, STM8S103, STM8S208R6, STM8S208S8, STM8S208SB, STM8AF628ADIE, STM8AF62A6, STM8AL3026, STM8AL3033, STM8AL3036, STM8AL3126, STM8AL3136, STM8AL3138, STM8AL316DIE, STM8AF6286TDIE, STM8AF6168, STM8AF519A, STM8AF6188, STM8AH5188, STM8AH6168, STM8S208M8, STM8L150M8 Modify Date : 2011:09:20 14:46:38+02:00 Subject : - Create Date : 2011:09:20 14:29:39Z Author : STMICROELECTRONICSEXIF Metadata provided by EXIF.tools