Scanned Semiconductor_Handbook_V1_1987 Semiconductor Handbook V1 1987
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1987
Semiconductor
Databook
Volume 1
U.SA
ISRAEL
SCOTLAND
Confidential and Proprietary
• Foreword
We at Semiconductor Operations (SCO) are committed to provide excellence in integrated circuit technologies, products, and services to support our customers, the Digital Systems Groups.
Our primary objective is to optimize Digital's competitive market position by developing leadership system performance at the lowest possible cost and within the appropriate
time constraints.
The execution of programs designed to achieve this 9
Introduction to the V-11 Chipset.; '.' .... ,'. -.4 •• :•••• ' ' ' ••• j • •: " . ;.( • • • • • • • '• • • • • • • • • • 1"207
DC327 V-ll ProcessorROM/RAM Logic ................ <;t; . ; . ; •• n . . , • • " . ' •••.•• 1-209
PC328 V-lll?tocessor Instruction/ExecutiQ1)-lpgic. . . . • .• .
. " J•.." •• '.'." •.•••• t:, 1"217
DC329 V-lll?tocessor Memory Management Logic ... ... i....'"
, ••••••• : .•• \1." 1·227
OC330 V-ll Processor Floating-point Accelerator Logic ........................... 1-241
DCJ1116-bit Microprocessor ............................................... 1-249
FPJll Floating-point Accelerator ............................................ 1-323
DCTlll6-bit Microprocessor .............................................. 1-349
Section 2 • Vadeo Processors and ControUers
78680 Video Processor (VIPER) ............................................ 2-1
78690 Video Control (ADDER) ............................................. 2-31
DC503 Progranunable Sprite Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-75
Section .3 • Communications Devices
78808 Eight-channel Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
OC319 DL11 Compatible Asynchronous Receiver/'lhnsmitter . . . . . . . . . . . . . . . . . . . . .. 3-27
Section ... • Bus Support Devices
VAXBI 78732 General Purpose Bus Interconnect Interface ........................ 4-1
VAXBI 78743 BCI Adapter Interface ..........•.............................. 4·135
VAXBI 78733 BCI Bus to MicroVAX II Bus Interface ............................. 4-159
VAXBI 78701 Clock Driver ................................................. 4·191
VAXBI 78072 Clock Receiver ............................................... 4·203
DC003 Dual-interrupt Logic ............................................... 4·213
DC004 Register Select (Protocol) Logic ....................................... 4-223
DC005 4-Bit Transceiver. , ............. , .... , ....................... , ..... 4-233
DC006 Word Count/Bus Address Logic ....... , ............................... 4-243
DCOIO Direct Memory Access Logic ...... , .... , ............................ ,4-255
Dcon UNmus Request and Control Logic ................. , ........... , ...... 4-269
De02t Octal Bus Transceiver ................... , .. , ......... ,., ...... , .... 4-283
Section j • Mass-storage Devices
DC018 Serializer/Deserializer Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
DC024 Encoder/Decoder Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-19
DC309 Reed Solomon Generator for ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-49
SeCtion 6 • General Purpose Devices
DC022 16-Word by 4-bit Register File . . . . . . . . . . . ... . . . . .. . . . . . . . ..• . . . . . . . . . . . 6.1
DC102 Eight-channel Equals Checker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .. . .. 6-23
DC30l Dual Baud Rate Generator ..................... ,. . . . . . . . . . . . . . . . .. . .. 6-31
Appendixes
Appendix A • MicroVAX 78032 CPU and MicroVAX 78132 FPU Instruction Set .......... A·1
Appendix B· DCTn and DCJll Microprocessors Instruction Set ...................... B-t
Appendix C • dc Specification Test Circuits ...........•..................... .... Col
Appendix D • Input/Output Voltage Waveform Parameters ....•. , ...... ; ............ D-1
Appendix E • Mechanical Specifications . . . . . .. . . . . . . ... ; ,; ..................... E-I
x
Confidential and Proprietary
· Section 1-Microprocessor and Support Devices
The micropr()cessors~d support devices provide a low-cost ~s to implement the power and
versatility of the PDP"ll and VAX. comp~ters into system designs.
MicroVAX32.bitMic:roproeesSol' '.
...
..
. ...' . .....
.
..,
'.
.
MicroVAX 78032 Central Processing Un it- The MicroVAX. cpU is a.~~-bit N8h-perfo~f;Ice
microprocessor that. contains the architecture. and functions. of .a. VAX minkompl.lter. The
MicroVAX·78032 implements a subset of the VAX. insttuctionset'andfull VAX.;lf memory
management. It is fabricated in ZMOS (double-metatNMtJSfandisc~ht:lrinedin'~{single68-piii
package.
MicroVAX 78132 Floating-point Unit-The MicroVAX FPU is a high-performance cooperative
processor used to accelerate the floating-point instructions of the MicroVAX. 78032 CPu. It
supports floating-point add, subtract, multiply, divide, and convert and other VAX.-ll floatingpoint operations. The FPU is fabricated in ZMOS and is contained in a 68-pin package.
MicroVAX 78516 Vectored Interrupt Controller- The VIC is a programmable interrupt controller that
is fully compatible with the MicroVAX 78032 CPU. The 78516 VIC services up to 16 interrupt
sources, resolves interrupt priorities, drives the IRQ line!> of the CPU, and provides a programmable
16-bit interrupt to the CPU. It is fabricated in high-speed CMOS and is contained in a 68-pin
package.
MicroVAX 78532 Direct Memory Access Controller-The 78532 DMA is a high-performance dualported four channel virtual memory DMA controller that enables high-speed data transfers
between I/O subsytems and peripheral devices and the MicroVAX 78032 CPU bus. It contains dual
ports and four channels that are independently programmable. The 132-pindevice is fabricated in
CMOS.
MicroVAX 78584 Dynamic RAM Controller-The MicroVAX. DYRe provides an interface between
the MicroVAX CPU and up to 4 Mbytes of dynamic random access memory (DRAM). The 78584
DYRC operates at two speeds to support 256K by I-bit DRAMs that operate at different speeds. It
is contained in an 84-pin package and is fabricated in CMOS.
Advanced Development VAX Incircuit Emulator- The ADVICE is contained on a single module and
provides a full-speed incircuit emulator of the MicroVAX 78032 CPU and MicroVAX 78132 FPU. It
is used for the development of hardware and software products using the MicroVAX CPU and FPU.
V.1132·bit VAX Processor
The V-ll processor chip set consists of four custom VLSI chips that were developed for use with the
Scorpio CPU module which is a single module VAX system.
DC327 ROM/RAM Logic-The ROM/RAM chip is a 44-pin cerquad device that provides the
microcode control store function for the
processor.
DC328 Instruction/Execution Logic-The lIE chip is a I32-pin PGA device that functions as the
main data path and contains the microsequencer, minitranslation buffer, and instruction buffer.
v-n
DC329 Memory Management Logic-The M chip is a I32-pin PGA device that provides most of the
memory management logic and includes a tag store for cache memory, four UARTS, and a 512-entry
backup translation buffer.
DC330 Floating-point Accelerator Logic-The F chip is a 132-pin PGA device used to decrease the
execution time of F , D , and G floating-point instructions and some integer multiply and divide
instructions.
Cottfidenfull and Proprietary
PDp·ll 16·bit Processors
DCJllMicroprocessor"":':'The DCJllmicroprocess6r isa60-pin CMOSmP de\"ice that implements
the full PDP·ll instruction set and has Eipe:tformance comparable tothe:PDPl l1/44 mihiprocessor.
FPJll Floating-point Accelerator-The FPJll FPA is a 40-pin DIPthatimplc::rnents in llatdware #
the floating-point instructions of the DC]l1 thereby significantly improving the performance of
fl6!iting-point instructions.
.
DCTn Microprocessor-The DCTll microprocessor is a 40-pin DIP device that contains the
essential elc!:ments of the PDP·ll architecture.
xii
Confidential and Proprietary
• High performance
- 32-bit internal and external data path
- Pipelined ru:clUtecture
- Insirtlctidn prefetch
• Subset of the VAX instruction set
- 245 instructions
• 4 gigabyte virtual address space
: SiXte~ 3~·kif$~~ra1PUll?Os~,register$
• 1 gigabyte physical address space
- 512 Mbyte physical memory space
- 512 Mbyte I/O space
• 22 interrupt levels
- 15 software
• VAX memory management
- Full memory protection
- Four privilege modes
- Process and system space mapped
• .Veetoredspftware and hardware interrupts
- 21 address~~ode~
~9 oata'types·'
•.
-7 hardware
~lndustr,yl»mpatible external interface
• Single 5 V~.,~er.supply
. Description
The MicroVAX 73082 is a high-performal}ce single-chip mic;ropt9F~sor that provides the
architecture and functions oft;he VAX minicomputer in a single'68-p.~ package. Fabricated in
ZMOS (double-metal MOS),·the MicroVAX 780:32 implements a.£Uli· 32"hit architecture that can
directly access 4 Gbytes ?fvif1;Ual m~mory and 1 Gbyte of physie# meptory. Figure 1 is a block
diagram of the MicroVAX78O'32 microprocessor,
GENERAL REGISTERS
A.O
INTERNIAL ReGt$T£~&
CON'fAOI. EHJS$ES
1
\
i
'.6IT ALU
AND
BARREL SHiFTER
L
i.
. - - - -.... .,
i?
il-o
eLKO
elKI
RESET
=3
MICAoseOUENctR
AND
CONTROL STOAe
CLOCKS
I
Figure 1 • MicroVAX 780J2 Microprocessor Block Diagram
Confidclltial ~P1pprietary
1-1
."
, ' ,
'
'
'.'~)?:/
,
'
!':'
"
'.
.' '.:: .)'
J',<, ,.,:::""", . ':,'
tYli:¢:'Q~a1[ 'fSf'}4(uses$&ingletvdt~~s~ppl~~;~~uire~/no~pec~suppott.1o~c,and
is
easily
with industry standard peripheral chlps. It is ideal for use as a single-board
computer, personal computer and workstation, and as a low-end system .
. Pin and Signal Descriptions
.
This section provides a brief description of the input and output signals and p0o/er and g.ro\lnd
connections of the MicroVAX 7803268-pin package. The pin assignments are id~ntified in Figure
2 !lnd the signals are summarized iri Table 1.
'iiiiiiiiiiiiiiic
~@§~~~5~~~S~~~~g
VOD
61
43
Vss
DAL06
DAL05
DAL04
DAlO3
DAL02
DAlO1
DALOO
62
63
64
65
42
41
40
39
38
37
36
DAL22 .
DAL23
DAL24
DAL25
DAL26
DAL27
DAL28
DAL29
DAl30
DAL31
66
67
68
VSS
VOD
1
2
iRi::i3
3
iIlQ2
TEST
4
im:ff
5
6
ifl()5
7
PWRIT
Vas
8
1---------1
I
I
I
I
I
I
MiCroVAX 78032
I
I
PROCESSOR CHIP
I
I
TOP
VIEW
I
I
I
I
IL _________ -1I
I
I
Voo
Vss
~
00
i5'i3r
CLKO
Figure 2· MicroVAX 78032 Pin Assignments
1-2
Confidential and Proprietary
MkroVAX 18032
Preliminary
Table 1 • MicroVAX 78032 Pin and Signal Summary
~t1Outpu;t*
Definition/Funetion
33-42 DAL<:31:00,. ..····input!output
45-59
Data!Address lines-Time multiplexed, ··bidi:reetional data and address bus.
62-68
30
AS
output
.
29
os·
12-15 BM<3:0>
Address
strobe-SY$tem address strobe,
. ...
. ......
H.··
... ..•
i ...'
output
input/output
21
WR
output
28
DBE
output
. Byte tfut~kli;..-:rdEintifi~t:he bytes of th~ DALbus that
containfvatid data.
' .,
'i'
.
transceivers.
ROY
input
20
ERR
input
16
:RESEr
11
BAtT
19
Ready-Providc;s.s~t\is~f~~~~rduring ~
memory or interrupt bus ~. '..
24-26 CS<2:0>
input/output
3,4,
6,7
input/output
IRQ<3:0>
8
,
'"
Interrupt request-Interrupt lines for device interrupts.
input
input
Interval timer- Indkate~
condition.
18
input
DMA request.,.,..~~ststhebus f()rDMA transfeiS.
22
output
DMA grant-Grants bus fot,DM,Atransfers.
23
output
External processor strobe..;.;..Coordinates exrernru
10
INTTIM
an;;:Kter1'lai inte~ timer
processor transactions.
2,32, VDn
44,61
input
Supply voltage-5 Vdcsupply.
1,31, Vss
43,60
input
Ground-Ground refe.rence.
17
CLK!
input
Clock in-Clock input for chip timing.
27
cum
input
Clock out-Clock output at half the frequency of
CKU.
9
VBB
output
Back-bias-For manufacturing use.
5
TEST
input
Test-For manufacturing use.
*All signals are TTL levels except for ~in 23(;ePS) ",Welds CMOS.
Confidential and Proprietary
1-3
nata ancl.A.ddressBus< " ' . , " ,
"f,:';".·,' ..: .hi";,
Uataand adchessbus (DAL< 31:00»-:-~heda~a a9dadclress~l.1sisatime"multiplexedbidirec
tional bus that transft!rs. address, dat~,and'dth~rirlforml!tioif'a{lririgf)uscycles. Fdf';a'detaife~
desc.tiption ofOAL< .31:00 :>bus, refer to tlwMicraVAX 78032;32~BitGentral~ctssint)}nitJjJser'$
Guide. (Document No. EK-78032-UGJ
Bus Control" "
" "
"
"',"
",
Address, strobe, (AS)-This signal indicates that valid address information is available on the
DAL < 29:02> bus and 'valid status information is 00 the BM < 3:0 >,CS <2:0 > , andWR: lines;
~le~dipgeai?;e of
si~nalc~n be used to lat<:.hthe address.
tJ:is
External processor strobe (EPS)- Thlssignal.\sused by the CPU to coordinate external processor
transactions,.!t is usedwiththdollowing transactiolls:
• ,Transaction'between an extetp.al processorc6ntrolled by the CPU , such as 'the MittoVAX 78132
Floating~Point
Unit.
'
",
.,
.. TransactiQos betweenlogit that implements a register or registers thatare defined as a part of the
Mie:tOVAXlrltertial prbtessot 'register set.
"
'
.,
Data strobe (.QS)--:Thissignal indicates that the OAt" bus is free to re,ceive data'during a GPUread
cydeor that valid datllison the DAL bus during a CPU write cycle. ,. "
Byte maskS (BM < 3:0 > )--These signals ate used to indicate which. bytes of the DAibus contain
va):idqataas lis:te<,i in Table 2. F()r a read cycle, they indicate which by~es. p£ theDAL bus must have
data driven onto them. For a wri~cycle, theY il1dicate which bytes of the DAL bus contain valid
data; Bits BM< H5 > art< valid when the AS ~ignal is asserted.
~ble 2 • MicroVAX 78~32~yte Mask Data Selection
Byte Mask , Valid Data Byte
BMJ
DAL< 31:24 >
BM2
DAL<23:16>
BMI
"PAL<15:Q8>
'.m;ro.,l)AL< 07 :00 >
1-4
Confidential and Propriet~
Preliminary
Writetfi~-1hi$ signal specifies the directionofdatatrmsfer 'on theDA.1L bus £or,thecurret1t bus
cycle;:,Whena~ted,:ithe CPU is performing a. write operatlon.When·notdeassertkcl,the CPtJ
is performing a read operation. The WR signal is valid when the AS or EPS signal is asserte )- These lines areused with ~itbertfie'ASofthe EPS andWRsignals to
define the type of operation in progress for
current bUs CYC~]Jn.e~4;nes cS < 2:0 >~re vaIi9
when the AS or the BPSsignalis asserted.
.
the
During a read,.write,orinterrupt-acknowledge
select the bus cycles indicated in Table 3.
Write Control Status
cycl~(AS asserted},.i'b~WRand CS « :2:0>
Bas: Cycle
WR
CS<2:0>
H
LLL
reserved
H
LHH
interrupt acknowledge
H
HLL
read (instruction)
H
HLH
H
HHL
H
HHH
read (data, no modify intent)
L
llL
reserved
L
llH
reserved
L
reserved
L
U1L
... LIDI
L
HLL
reserved
L
HLH
write unlock
L
HHL
reserved
L
HHH
write (data)
reserved
CoMidential and Proprietary
.'
lines
Preli~ . . · ·
Atthebegiriningohm:,cxternalpracessor .read, Write:,;. orrespo~ qrcle.(m as~ted),the
es< l:Q:> signals select the bfu;cyc1esincli(:atedin
Table 4.
CS2sigllal is.high,.andthe:wR and
~ble 4·
l\.iic:roVAX 78032 Ext:emaJRtgis_lJus Cyde
Write' ContrOl Status Bull Cycle
CS<1:0>
fi
LL
rest!rved
H
LH
read data
H
HL
reseI'Ved
H
HH
response enaple
writec'?mnland (FPU)
L
write data
L
HL
L
HH
. write command (non-,FPU)
reserved
During a response enable Cycle the ts <2 > signal maybe pulled loW bVthe external logic. Refer to
the External Processor Cycle section for a description of a response enable cycle ..
Interrupt ContrOl
Interrupt request (~IR~Q:O:--::<:-:;j"":o~>-)·-These lines are used by the extetnallogic to generate interrupt
requests to the CPU. The lines are sampled by the CPU every microcyde. Table 5 lists the ipterrupt
level assignments.
Table 5 • MicroVAX 78032 Interrupt Request Assignments
IRQ Line· Interrupt Level
IRQ 3
IPL 17
IPL 16
IPL 15
1PL 14
1-6
CcmfidentiaI and Proprietary
Preliminary..•..
MicroVAX71l92
Powerfail (PWRFL)-This line allows the external logic to notify the CPU ofa powerfaii
condition. It is s~mpled by the CPU every microcycle. The PWRFL signal generates aninterrupt at
1PL IE (hexad~imal). This interrupt is internally acknowledged by the CPU and does qat use an
interrupt ac,kn= 1Qand DAL<05:00> == 111111) and then
enters the restart process. The restart proce$s sets tQe CPU to a known state and then passes control
to user code beginning at physical address 20040000 (hexadecim~). Fgr a description of the restart
process, refer to the MicroVAX 78032 User's Guide.
DMAControl
DMA request (DMR)..;.;.This signal is usedby the external logic 1;0 take control of the DAL bus and
its related control signals.
..
DMA grant (DMG)-This signalindicates that the CPU has gran:~dthe use of the DAL bus and its
related control signals.
Clock Signals
Clock in (CLKJ)-A TTI.. input that provides the basic clock timing to the clock generator on the
MicroVAX 78032.
Clock out (CLKO)-A timing signal output at half the frequenCyo,fb(!si~dock (eLKI) to be used
for system timing.
Miscellaneous Signals
Test (TEST)-Reserv(f,d. This pififl/ust be connected to ground..
Power Supply Connections.
Power (VDO)-5 Vdc supply..
Ground (Vss)-Ground reference.
Back-bias generator (VDS)-Reserved. This pin must notbe.coWlected ..
Confidential and Proprietary
1·7
-
• Ai'chite«:tu1'e Summary.
The MlCtuVAX78032 "~hitecture show~ inPigure 3Is. group~into two ,main areas. One' area is
use(fhy the' application programmer and contains general registers, pointer re~isters, and the
processor status word. The remaining area is used by the system programme!: and contains process
control registers, memory management registers, interrupt registers, and theprocessorstiitus
lOogwOrd.
APPLICATIONS
PROGRAMMING
GENERAL REGISTERS
RO
RT
R2
A3
KSP
R4
ESP
AS
SSP
Ae
USP
A1
RS,
RU
RIO
PROCESSOR STATUS WORD
RIT
PSW
SYST~M.
PROGRAMMING
PROCESS CONTROL REGISTERS
INTERRUPT REGISTERS
seeB
SlRR
PCBB
515R
MEMORY MANAGEMENT REGISTERS
L..-_ _ _:.::ISP:..-_ _.-.J
POBR
1,
'i> 32 .
General Register Addressing
The general register address modes use one or more general registers, depending on the instruction
and data type, or information required to locate the operand(s) to be lised by the specifi~d
instruction.
Register mode-:-.The operand is contained in one of the general registers (Rn).
Register deferred mode-Register Rn contains the address of the operand.
Autoinaement mode........ Register Rn contains the address of the operiU1d. After the operand address
is determined, the size of the operand in bytes is detertninedby its data type and is added to the
contents of register Rn and the result is placed in register Rn.
AutoinC1'ement deferred mode-Register Rn contains a longword address that points to the
operand address. After the operand address has been determined, the number four is added to the
contents of Rn and the result is so tred in Rn.
Autodeaement mode-The size of the operand ,in· bytes is determined by its data type and is
subtracted from the contents of Rn and the result is stored in Rn. The updated, content of register
Rn is the address of the operand.
Literal mode-Literal mode addressing provides an efficient means of specifyingioteger constants
in the range of from 0 to 63 (decimal). In addition to short integer literals, this mode can be used to
specify floating-point literals. The value is contained in the operand specifier.
Displacement mode-The displacement contairied in' the operatid specifier, after being signextended to.32 bits if it is a byte or word, is added t() the contents otregister Rn,and the result is
the operand address.
.
Displacement deferred mode-The displacement contained in the operand specifier, after being
sign-extended to 32 bits if it is a byte or word, is added to the contents of register Rn, and the result
is the operand address.
Confidential and Proprietary
Index mode-The Qperandspecifier consistS of two bytes or more, a primary operand specifier and
a base Operand specifier. The primary operand specifier,contained in bits 0 fhro~ 7, iucludes the
,index regi£tet(Rx)and a modespecmer of4. The address of the primary opemndisdetermined by
multiplying the contents of index ~ter Rx by the sWeof the primary operand in bytes which is
determined byc>pC!ran4 type~ Thisyalue is then added 1)) the ~dress spet;ified by the b$C operand
specifier (bits 15 through 8), and the n;s9;lt'is the pp~ryqpeliand addtess.
Program Counter Addressing
Register 15 is used as the program counter (PC). It can also be usedin.·th~a~i03;rqodes,l'he
processor increments the program counter as the opcode, operand specifie~ ~tld immediat~ data or
addresses of the instruction afeeValuated/fheatl1i)Unt thaHhe'iPG isincrementedis detexritinedby
the opcode, number of openioospecifiersartaother values.1'bePCcanbe usedwithalloftneVAX
addressing modes,6ti:ept regiSter; index, ~siterdefetred; orautodecrement.
Immediate mode-This mode is an autoincrement.mode.andthf! PC is~.as the general register.
The contents of the loeationfoDowing the~ddresSingmdde CQMUu.iminddiaie data.
This mod~i~··~· ~ufoili~reinerit d~ferre~.@dellsing the 'J?C.•aSthe general
registe.c The contents of the location following the addJ!essing' mode ,. are takeh. as the operand
address. This is interpreted as an absolute address that is an address that n;~~t~Jll;in.tl-.Ie
memory locatic)flwhel;'e . ~~seml?led.ipstruc.tioJl4~~.ted,
AbsolUte
mocle-
Relative mode--Thismdcleisa displaeementmocle and the PC is" uSed aslhecgeooraltegister. The
displacement that follows the operand specifier is added to the PC Illld the sum is/the address of the
operand.
Relative deferred mode-This mode is similar to the relative mode except that the displacement,
which follows the addressing mode, is added to the PC and the sum is the longword address of the
operand.
Branch Addressing
During branc.hdisplai;ementaddn;ssing,clie byte 91' word displace1l1eht is sign-extended to 32 bits
and added to the updated content of the PC. The/updated content of the PC is the address of the
'
first byte beyond the operand specifier.'
• Instruction S~t
A summary of the VAX instructions implemented by the MicroVAX 78032, the floating-point
instructions supported by the SOating.point unit, and the emulated instrQctionsthat are assisted
by the microcode are listed in Appendix A..
Operand Type
The operand type specifies the use of the operand that is associated with an instruction. The
apcode includes the data type of each eperand and the method of acce:;s as follows:
1. Read-The specified operand is ready-only.
2. Write-The specified operand is write-only.
3. Modify-The specified operand is read, may be modified, and is written.
4. Address-Address ddculation occurs Until tHe address of the . operand is obtained. In this
mode, the data type indicates the operand size to be used in address calculation. The specified
operand is not accessed directly; however, the instruction may use the address to access that
operand.
1-17
Preliminary
5. Variable bitfiekd baseaddress"'-If only .registerR(n] is spedfied;the fie41is iil genim.uregister
R(o] or in R[n't'l}'R[n] (i.e., R[n+ 1] concatenated with R[n]); If R{nlisnot specified, an
address calculation occurs until the actual address of the operand is obtained; This address
specifies the base to which the field position (offset) isawlied.
6. Brandl---No operand is accessed. The operand specifier is the branch displacernent and the
data type indicates the size of the branch displacement.
.
. Memory Management
The mem9ry management. unit provides. a. flexible and efficient virtual memory programming
environment. Memory management and the operating system provide paging with user control
and swapping. It also provides four hierarchical modes-:-kernel1 executive, superyiso,r, and user,
with ~ad/write.access control for each mode.
The VMS Virtual MeU1QrySystem provides a large address SPace and allows programs to tun with
smail memory configurations. Programs are executed ina process environment. Each process can
.
operate with an address space of 4-billion bytes.
VIrtual Address Space .
Memory management divides the virtual address space into two spaces of.equal size-the system
space and the process space. The process space is divided into PO and PI regions. Figure IOshows
'the virtual address space assignments.
00000000
LENGTH OF PO REGION IN PAGES·
I.POLRI
PO
REGION
3FFFFFFF
40000000
PI
REGION
1
1
PO R;EGION GROWTH DIRECTION
PI REGION GROWTH DIRECTION
LENGTH OF PI REGION IN PAGES
12 u ll-PI LRI
1FFf cF FFF
80000000
LENGTH OF SYSTEMR~GION IN PAGeS
ISLRI
SYSTEM
REGION
1
BFFFFFFF
C()ooqooo
SYSTEM REGION GROWTH 01 RECTION
RESERVED
REGION
FFFFFFFF
Figure 10- MicroVAX 78032 VirtuslAddress Space Assignments
1-18
Confidential and Proprietary
_
.. ,
Preliminary
Vartualac.fdtess format-A 32-bit virtUal address is generated £Or eachinstrurtion and operand in
memory. As the process is executed, the processor translates each viruw address into a physical
~s; 1'hefprmat qf ,~~irtual address is shown in Figure 11 aJ'ld describ~d inThbIe 9.
Page pl.'Ot.eetion-Independent of its location in virtual address space, a page of5U bytes may be
protected according to its use. A Pl'9gWD ~y,g~teany ~ss;.hQWeV~. Plep~Jl1 may be
prevented from modifying or acce$sillgpor~ons of tl1eshan:9syS,te;n space. AptogJ;ammay. also be
prevented from accessing or iOOdifYing portions o! proCess space.'
'. ' , ,
VIrtUal address $p8ee l~t"":~sstOthePti,P1, and Sys~enil"e,ii6ns'is Cohtrolledhy the {PDLR,
PUR, and SiR)lengthregisters;Within:theJitnits set byttBe leilgthregiSte&;'tlie"acceSS; is
controlled by a page table that specifies the validity, access requirements, and location of each page
inthe region.
Figure 11. IiMi~VAX 780')2 Virttl4l~,Format
Bit
Desc:riptioos
31:09
VPN (Virtual Page Numbed-This field specifies the virtual page to be referenced.
Virtual,address ~e cont~8;3~~.608pages of~UbYtes each-
Bits <31:30> ofthe.VPNseleet the region (1£ virtual ad~ss space being
re£erencedasfollows:
"
'
Value of
Region
Bits <31:30> Referen<;ed
(j
PO ,"
1
Pl
2
Sys~ni
.3
.. Reset\?ed
08:00
Byte number-This field speclfiesthe number o£'~k byte within the page.
&cess Control
The access control fun<;tiori detelitnines whether a read or wri~,~ory ref~ will be all~
to a memory page. Every page in memory isassignedaprotectWnicoc:k to preVent illegal access to
memory information.
Confidential. and ProprietarY
1-19
,MOde,..,...'i['netourhimucliicaltilW.dcs,'tlsed .• h¥theMitroVAX."1 803210'the'1QtCier of,most :.toJeast
privileged are
a Kern~Iili..b~ed byth2ketbel;of:the operatingsgstertJ. for~age'triariagert1~I1t!" schedUUrig;arid
'. l/O:dr~vers. '.
, l:'EJKeOtitiVeL used formanyofthe operating sy~tern service ~alls;
2' sUPei:visbf:'::":used £6r services;s~~:~scommand interpremibn:
~'"
~-
Us,t;r-;:\lsep for user level code', u'tiHties, co~piIers?Aebugg~rs,
~!c:,'" '.
i: -.,-:,' .', _"
" -', >, ,-
' ,
"
.' ,;
':"; -
,
'
•
- •
,,' '
-', - , '
,."
-' " ;
t: ,.',;
<
The curre~t p~Ces$~:l1: tm;'e;e is~tored in the current mO
R
12
1100
URSW
RW
RW
RW
R
UREW
RW
RW
R
R
'UltRW'
RW
UR
R
R
R
R,
1101
13
14'
15
U'
···.ff10} ,
: -;("
1111
Legend:
- = no access
* = unpredictable
R = readonIy
RW= read/write
W = write
"
R
, 1::-
K = Kernel
E = Executive
S = Supervisor
U
RW
= User
Confidential andJProprietilry
-
MicroVAX780l2
. Memory Management Control
Three registers are used to control memory management .. One register is used to enable ~nd disable
memory management and the other two are used to control the address translation buffer.
Memo!y Management,Enable
The map enable register (MAPEN) determines whether· the 11lemory manag~mentfunctions is
disabled or enabled. The fqrrnat of the map enable: regillteris, $hc:wn in Figure 12 :mddescribed in
Table 1 1 . '
' . . .
I::: :::::: ::: ::~ ;.;:: :: :.::: ::::11I
31
.' .
'.'
.. ' 0100
:MAPEN
MME
Table 11 • Mic:roVAX 78032 Map Enable ~sterDesaiption
Bit
Descriptions
31:01 MBZ (Must be zero).
00
MME (Memory management enable)-used to enable and disable memory management as
follows:
1 =MME' enabled
0= MME disabled
Translation Buffer
The translation bUffer stores frequently used flletnOry page references. The translation buffer
stores eight entries that contain page table entries (P'FE) £or sulleessful:virtUal address translations.
It is cont.roned pythe,~tionbl¢fc;r iilvali~te s~ of the virtual address become the phy~ical address, and access
is allowed in all modes. When MME = 1, the memory mapping is enabled and tbe virtual address is
mapped to a physical address by the memory management. The address translation process when
memory management is enabled is as follows.
Page table entry-All virtual addresses are translated to physical addresses by a page table entry
(PTE) shown in Figure 14 and described in Table 12.
Protection check before valid checlt-The page table entry contains a valid bit that controls the
validity of the modify bit and page frame number field. The protection field is always valid and is
checked first.
OWN
Figure 14 • MicroVAX 78032 Page-table Entry Format
Table 12 • MicroVAX 78032 Page Table Entry Descriptions
Bit
Descriptions
31
V (Valid bit)-Governs the validity of the M modify bit and the page frame number (PFN)
field. V = 1 for valid; V =0 for not valid.
30:27 PROT. (ProteCtion field)-Describes the protection for the page. This field is always valid
and is used by the hardware even when V = O.
26
M (Modify)- This bit is set (= 1) if the page has already been recorded as modified. M = 0
if the page has not been recorded as modified. Used only if V = 1.
25
o(Zero)-reserved.
;24:23 OWN (Owner)-reserved.
22:21
0 (Zero)-reserved.
20:00 PFN (Page frame number)-The upper 21 bits of the physical address of the base of the
page. Used if V = 1.
1-22
Confidential and Proprietary
...
Preliminary
MicroVAX180.32
System Space Address ltansIation
A virtual address with bits 31atld 30 equal to 2 is an address in the system virtual address space
that is mapped by· the system page table (SPT). The·SPT is located in physical memory and its
location and lengthane defined by the system base register (SBR) and the system length register
(SLR), Figure l5.The SBR contains the phys~cal~.s of thesystempagetl!.ble.TheSLRCQ~s
the size of the SPT in longwords that is the·l1\Ul;lh« of page table entries. The page table entry
pointed to by the S~R 1l1jlps to the firstpag¢ o£SYStemvirnW~ spa(;e.that is virtual~byte
ad~ss 80000000 (hexadecimal);.
Figure 16 shows the translation of a system virtual adSVA <08:00 >
Figure 15 • Mi&roVAX 78032 System Mapping Register Formats
313029 .
SVk
ISYSTEM VIRTUAL,
ADDRESS)
00
0908
2
BYTE
E,~TRACT ANP
CHECt< LENGTH
0:2 0100
2322
31
o
o
ADD
SBR,
FeTCH
3130
2120
PFN
PTE,
CHECK ACCESS
THIS ACCESS,q.tECK
tN CU'flP:ENT' MODE
0908
00
PHYSICAL ADR OF DATA,
Figure 16 • MicroVAX 78032 System Virtual.to.Physical Address Translation
Confideritial"and Proprietary
1·23
MicroVAX78032
Preliminary
Process Space Address Translation
.,
A virtual acldress witllbit J 1 s.,t to 0 is an adpress in the process vil'tl,lal address space. The process
space is divided into two equal sized, sepaqltely mapped regions. If virtual address bit 30 is set to 0,
the address is in regionpO. If virtual address bit 30 is settol, the address ism region PL
PO region addreSs transIation~ The pO region ofptocess address space is specified by the PO page
table (POPT). The'POPT is located in system virtual address and its location and length are defined
by the PO base register (POBR) and the PO length register (POLR), Figure 17. The POBR contains the
system virtual address of the PO page table. The POLR contains the size of the POPT in longworos,
that is, the number of page table entries. The page table entry pointed to by the PO base register
maps the first page of the fO region of the virtual
address space, that is,
.
., virtual byte address O. .
Figure 18 shows the translation of a PO virtual address into a physical address.
The algorithm used to generate a physical address from a PO region virtual address is
PVAYTE ... POBR + 4 *PVA < 29:09 >
PTE_PA= (SBR + 4*PViLPTE < 29:09 > ) < 20:00 >'PVAYTE < 08:00 >
PROe_PA = (PTE_PA)< 20:00 > 'PVA < 08:00 >
020100
SystEM VIRTUAL LONGWOAI> AODRESS OF POI'T
MBZ
:POBR
Figure 17 • MicroVAX 78032 PO Region Mapping Register Formats
313029
0908
00
PVA:
(PROCESS VIRTUAL
ADDRESSI
0
BYTE
EXTRACT AND
CHECK LENGTH
31
020100
2322
0
ACD
31
POOR:
0100
I:::::::: :+:+~+HDH+~:::: ::::: If I
I :::::::: :s:S:+f+:AHO~P~E: : : : : : : : : : Ii I
VIStOS
31
0100
FETCH BY SYSTEM SPACE
TRANSLA lION ALGORITHM,
INCLUOING LENGTH AND
-KERNel MODE ACCESS CHECKS
3130
2120
PTE:
00
PFN
TH IS ACCESS CHECK
IN CURRENT MODE
CHECK ACCESS
29
09 OIl
PHVSICALADR OF DATA:
Figure 18 • MicroVAX 78032 PO Virtual-to-physical Address Translation
1·24
Confidential and Proprietary
00
MicroVAX78032
PI region address translation-The PI region of the address space is specified by tbe PI page table
(PIPT). '!be PIPT is located in the system virtual address space and its location and length are
defilledrby the PI base register (PlBR) and the PI length register (PILR) , shown in Figure 19.
Because the PI space eXpands toward smallet addresses, and a consistent hardware interpretation
of the base and length registers isaesirable,tl1eP1BR and PI LR contain the portion ofthe P1i:!!pace
that is nbt accessible. Note tharP1LR containsthefitimber of nonexistent PTEs. PIBR connUns the
system virtual address of what would be the PTE for the first page of PI, which is the virtUal byte
address 40000000 (hexadecimal). The address in the PIBR may not be a valid system virtual
address; however, all the addresses of PTEs must be valid system vit:tval ~~.1?i&qre 20s1;wws
the PI virtual address to physical address translation.
The.alg<)rithm used to gen~rate ~ physi~aladctre~s£rolllapr~onyirtualaddress i~
PVAJTE =PIBR + 4*PVA <29:09 >
PTEJA= (SBR +4*PVA-l'TE <29:09.~)< 20:00 > 'PYAJTE < 08:00 >
. . PROCYA = (PTEYA) ~20:oo> ''pyA -< 08:00 > .
.
I::: ~: ::: I:: ;:+~~?+H+~~f+:::: I
31
,
2221
",.,,' '-
.',
00
-"
, ., 1 ',,, "" "''',, ",,,,' - ,
,P1LR
Figure 19 • MicroVAX 780)2 PI ~~Mapping Register Formats
0909
PVA,
(PROCESS VIRTUAL
ADDRESS)
00
IIYTE
EXTRACT AND
C-HECK -LENGTH
23 22
31
o
ADO
moo
~
P1BR,
I:::::::: :+:vH+H+1+~::: :::.::: If!
I: :: ::::::H~++~+~+H :::,:: ::: :1 fl
YIEL.OS
~
moo
FETCH BY SYSTEM SPACE
TRAN$LAiIQN ALGORITHM,
INCLUDING LENGTH AND
~Ea"E~JIIOOli
3130
ACCESS CHECK'>
00
2120
PTE,
PFN
nus ACCE;SS c;t-tECK
CHECK ACCESS
IN CURRENT MODE
29
0908
00
PHYSICAL ADR OF DATA,
Figure 20· MicroVAX 78032 PI Virtual-to-physicalAddress Translation
ConfidentisU Ilnd Proprietary
1-25
" ary,
Prelimin
MicroVAX 78032
Memory Management Faults
The two types of fawts ~sociated with memory mapping and.protection are translation not valid
and access control violation. An access con;trpl violation fault exists when the protection field of
the PTE indicates that. the intended page reference in the specified access mode is illegal. A
tran$1ation not-valid fault exists when a read .or write reference is attempted through an invalid
PTE. If ~ access control violation and a translation not-valid faults occur, the access control takes
precedence .
• Exceptions and Interrupts
During system operation, events that are not related to the current process can require service.
These events cause the processor to interrupt the process being executed and transfer control to a
program that will service the event.
An exception is the notification of an event that is relevant to the currently executing process and
normally invokes a program in the context of the executing process.
An interrupt is the notification of an event that is relevant to other processes or to the system and is
serviced in a system wide context. The system wide context is defined as executing on the interrupt
stack. The priority associated with the interrupt is the interrupt priority level. (IPL).
Interrupt Priority Levels
The VAX architecture includes 31 priority interrupt levels. Fifteen levels (1 through F hexadecimal)
are software related and 16 levels (10 through IF hexadecimal) are hardware related. Table 13 lists
the interrupt priority level assignments for the MicroVAX 78032.
Table U • MicroVAX 78032 Interrupt Priority Level Assignments
IPL Level
Interrupt Condition
(hexadeclmal)
IF
unused
IE
PWRFL asserted
18-1D
unused
17
iRQJ
16
INTTIM asserted
16
IRQ2
asserted
15
nmI
asserted
14
IRQO
asserted
10-13
unused
01-0F
software interrupt request
1-26
asserted
Confidential and Proprietary
...
MicroVAX 78032
Interrupt Requests
Interrupt requests are serviced during the execution of long interactive instructions such as string
instructions and at the completion of an instruction.
Urgent interrupts-....Interrupt levellE (hexadecimal) indicates a powerfail condition and requires
immediate service in the MicroVAX 78032.
Device internlpts-Interrupts 14 through 17 (hexadecimal) are assigned to the peripheral devices
operating with the MicroVAX 78032.
Software interrupts-Interrupts 1 throughF are used by the MitroVAX 78032 system to generate
.
software controlled interrupts.
.
Interrupt Registers
The interrupt system is controlled by the int~ptpri¢rity level register (IPL) , the software
interrupt request register (SIRR), and the soft~interruPt'~ary register (SISR).
~'~
-
, "
- ,,'
Software interrupt summary Ngister-Thesof~inUU'rupt summary register (SISR), shown in
Figure 21, is a privileged register that recordSl:lI:t~.So(~ interrupts. A 1 is set in the bit
position corresponding to levels on whichsoit\1nll'¢ in~pts:~ pending.
31
:SISR
MOZ
Figure 21 • MicroVAX 78032 Software InJ:emtptSummary Register Format
Software interrupt request register-The software interrupt request register (SIRR),. shown in
Figure 22, is a write-only, 4-bit privileged register used for rrialdng a software lliierrupt request.
The software requests an interrupt by writing the appropriate interrupt leveltothe SIRR. Once a
software interrupt request is made, the corresponding bit in the SISR is set. The processor will clear
the bit in the SISR when the interrupt has beenacknowl~.
31
0400
flO
I:::::::::::::H+? ::::::::::H+Hs,RR
Figure22 • MicroVAX 78032 Jntemtpt Request Regis~ Format
Interrupt priority level register-Writing to the IPL register, shown in Figure 23, loads the
processor priority field in the processor status longwood (PSL).
31
05 04
flO
I:::::::::: :+iRf~ +~Ho: ::::::I:::: I
:IPL
'--v---"
PSL<20:18>
Figure 23 • MicroVAX 78032 Interrupt Priority Level Register Format
Confidential and Proprietary
1-27
mDBlllD
MicroVAX 78032
. Exceptions
An exception is an event that is the direct result of executing a specific instruction. Exceptions also
include errors automatically detected by the proCessor, such as improperly formed instructions.
The MicroVAX 78032 recognizes the six classes of exceptions summarized in Table 14.
1Bble 14 • Mic.roVAX 78032 Classe.s of Exceptions
Exception Class
Condition
arithmetic traps/faults
integer overflow trap
integer divide by zero trap
subscript range trap
floating overflow fault
floating diVide by zero fault
floating underflow fault
memory management exceptions access control violation fault
translation not valid fault
operand reference exceptions
reserved addressing mode fault
reserved operand fault or abort
instruction execution exceptions
reserved/privileged instruction fault
emulared instruction fault
extended function fault
breakpoint fault
tracing exceptio~
trace trap
.system failure exceptions
memory read error abort
memory write error abort
kernel stack not valid abort
interrupt stack not valid abort
machine check abort
System Control Block
The system control block (SeB) is a page in physical memory that contains the vectors for servicing
interrupts and exceptions. Table 15 shows the type and location of the vectors. The SCB is pointed
to by the system control block base register (SCBB), Figure 24.
313029
Maz
PHYSICAL LONGWOAD ADDRESS OF sea
:SCBB
Figure 24 • MicroVAX 78032 System Control Block Base Register Format
1-28
Confidential and Proprietary
Preliminary
Table 15- MiaoVAX 78032 System Control Block Vectors
Vector
Address
Type
~tor
Name
(hexadecimal)
00
unused
abort
04
machine check
abort
08
kernel stack not valid
interrupt
OC
powerfail
fault
10
reserved/privileged
instruction
fault
14
extended instruction
faUlt/abort
18
reserved operand
fault
IC
reserved addressing mode
fault
20
access control violation
faUlt
24
translation not valid
fault
28
trace pending(TP)
f~t
2C
breakpoint instruction
30
unused
34
arithmetic
38-3C
unused
trap
40
CHMK
CHME
trap
. trap
4C
CHMS
CHMU
50-80
unused
interrupt
84
software level I
in~rrupt
88
software level 2
interrupt
8C
soft\yare level 3
int;errupt
9O-BC
sOftware levels 4-15
1nterrupt
CO
interval timer
C4
unused
fault
C8
emulation start
fault
44
48
trap/fault
trap
Confidential and Proprietary
1-29
...
MicroVAX.1S().32
Table 15· MicroVAX 780.32 System Control Block Vectors (Cont.)
Vector
Address
Vector
Name
Type
(hexadecimal)
CC
emulation continue
DO-FC
unused
interrupt
lOO-1FC
adapter vectors *
interrupt
200-3FC
device vectors *
*Used by the MicroVAX 78032 to directly vector interrupts from the external bus. The vector is
determined from bits < 9:2 > of the value supplied by external hardware. If bit < 0 > of the offset
is 1, then the new IPL is forced to 17 hexadecimal. Only device vectors in the range of 100 to 3FC
hexadecimal should be used, except by devices emulating console storage and terminal devices .
• Process Structures
A process is .the basic entity scheduled by the system software. The context of the current process is
contained in the process control block (PCB) shown in Figure 25. The PCB is located in physical
memory and is pointed to by the process control block base register (PCBB) shown in Figure 26.
00
31
KSP
:PCB
ESP
+4
SSP
+B
US!'
+12
RD
+16
Rl
+20
R2
+24
R3
+28
R4
+32
RS
+39
RS
+40
R7
+44
RS
+48
R9
+52
RIO
+66
+60
Rll
AP {R121
+68
FP{RI3)
+72
PC
Mez
PSL
+76
POBR
+80
I tSr I MBZ I
POLR
+84
P1LR
+92
P1BR
PMEI
MBZ
I
+8B
NOTE: THE PME FIELD IS UNUSED.
Figure 25 • MicroVAX 78032 Process Control Block Assignments
1·30
Confidential and Proprietary
-
MicroVAX 78032
Figure 26 • MicroVAX78032 Process Control Block Base Register Format
• Processor RegiSters
The MicroVAX 78032 processor contains many registers~t;~ac<:;essible to the user. These
registers are listed in Table 16 and.~ groupsdc;~ribed by the following categories.
1 = Registers implemented by the MicroVAX 78032 as specified l;)ytheMicroVAx Architecture.
2=Registers implementedooly by the MicroVAX 78032,
3 =Registers passed to the external logic' via the. external processor .register .protocol. If not
implemented externally, they at'e read as ~ and result in no operationdurlng a write cycle.
4 =Register access is not allowed (reserved operarid fault).
Table.
16 • Mie1'OVAX,78632 Intemai Proeessor~
.....
.
';, . . ' , . :
.~
A-lnemo.uc 11ype.
..
Number Register Name
Category*
2
Supervisor Stack Pointer
3
User Stack Pointer
KSP
ESP
SSP
USP
4
Interrupt Stack Pointer
ISP
5
reserved
4
6
reserved
4
7
reserved
4
8
PO Base Register
9
POkngth Register
10
PI Base Register
11
PI Length Register
12
System Base Register
13
System Length Register
14
reserved
4
15
reserved
4
16
Process Control Block Base
0
Kernel Stack Pointer
1
Executive Stack Pointer
POBR
POLR
PIBR
PILR
SBR
SLR
PCBB
RW PROe
~ t£ ;"
RW PROe
RW PRDe
RW PRDe
RW epu
InitiaJile.
',",
RW
RW
RW
RW
RW
RW
RW
1
1
,
PRDe
PRot
PROC
PROC
CPU
CPU
PROC
1
1
1
1
1
1
1
1
1
1
*Refer to Processor Register description.
Confidential and Pr,oprietary
1-31
~DlllmD·
MicroVAX78()32
Table 16 .. MieroVAX 78032 Internal Processor Registers (Cont.)
Number Register Name
Mnemonic: Type Scope Initialize Category'"
17
Syst\!m Control.6lock Base
18
Interrupt Priority Level
SCBB
IPL
RW
RW
CPU
CPU
yes
1
19
ASTLevel
Software Interrupt Request
RW
W
PROC yes
CPU
1
20
ASTLVL
SIRR
21
Software Interrupt Summary
23
CMI Error Register
CPU
CPU
CPU
1
Interprocessor Interrupt
RW
RW
R
yes
22
SISR
IPIR
CMIERR
24
Interval Clock Control
Next Interval Count
26
Interval Count
CPU
CPU
CPU
27
Time Of Year
28
Console Storage Receiver Status
RW
W
R
RW
RW
yes
25
ICCS
NICR
29
Console Storage Receiver Data
30
31
Console Storage Transmitter Status
Console Storage Transmitter Data
32
Console Receiver Status
33
Console Receiver Data
34
Console 'Ihmsmitter Status
35
Console Transmitter Data
36
Translation Buffer Disable
37
Cache Disable
38
ICR
TODR
CSRS
CSRD
CSTS
CSTD
R
RW
W
RXCS
RXDB
RW
R
TXCS
TXDB
TBDR
RW
W
RW
Machine Check Error Summary
CADR
MCESR
RW
RW
39
Cache Error
CAER
40
Accelerator Control/Status
RW
RW
CPU
CPU
CPU
CPU
1
1
4
4
2
3
3
3
3
3
3
CPU
3
CPU
CPU
CPU
3
3
3
CPU
CPU
CPU
3
CPU
3
CPU
CPU
CPU
CPU
CPU
CPU
CPU
3
3
3
4
45
ACCS
Console Saved Interrupt Stack Pointer SAVISP
SAVPC
Console Saved PC
SAVPSL
Console Saved PSL
WCSA
WCSAddress
WCSD
WCSData
46
reserved
4
47
reserved
4
41
42
43
44
R
R
R
RW
RW
2
2
2
4
4
*Refer to Processor Register description.
1-32
-~
..~"" ..... ~--~~-~.
Confidential and Proprietary
~-;;.."."....<---~~~,,"'-~ --.>-.---,,......~-"-~
~~~--=~
-
MicroVAX78032
Tablel6- MicroVAX 78032 Internal Processor Registers (Cont.)
Number Register Name
Mnemonic Type Scope Initialize Category*
48
SBI Fault/Status
SBIFS
RW
CPU
3
49
SBI Silo
SBIS
R
CPU
3
50
SBI Silo Comparator
SBISC
RW
CPU
3
51
SBI Maintenance
SBIMT
RW
CPU
3
52
SBl Error Register
SBIER
RW
CPU
3
53
SBI Timeout Address
SBlTA
R
CPU
3
54
SBI Quadword Clear
SBIQC
W
CPU
3
55
56
10 Bus Reset
IORESET. W
CPU
3
Memory Marutge¢ent Enable
MA~EN:
RW
CPU
57
Trans. Bu£. Invaliqate All
TBlA
'SQ
CPU
1
58
Trans. Buf. Invalidate Single
TBIS
W
CPU
1
59
Translation Buffer Data
TBDATA
RW
CPU
3
60
Microprogram Break
M;6RI<
RW·· CPU
3
61
Performance Monitor Enable .
PM:£(·
RW·· PROC ...-
3
62
System Identification .
SID
R
CPU
1
6,3
Translation Buffer Check
?¥I
cPIJ
1
64:127
reserved
"-"..........'
';<'~ ;, " :'
yes
1
4
*Refer to ProcessOr Register description.
- Interfacing Requirements
The MicroVAX 78032 connects to memory, to external circuits, and to the powef&Ql.lrcethrougb
the connection pins on the package. The .following p~phs~inethe power,reset, and bus
connections and describe .the timing considerations for hLlSQpe~tion.
Power Connections
The MicroVAX 78032 requires a single 5 Vdc power supply. Eight pins are provided for power
connections; four VDD pins and four Vss pins. The VOD pins connect to 5 V and the Vss pins connect
to ground. The power decoupling and grounding is important. Decoupling the power supply is
implemented by connecting a capacitor between each VDD pin and its associated Vss pin as shown in
Figure 27. The recommended capacitor type is 10 I!f tantalum, + 1, -10%. The ground pins (Vss)
should be connected to the common ground for the power supply at the chip.
The MicroVAX 78032 internally generates the required negative voltage that is externally available
on the VBB pin. This voltage does not require filtering and the VBB pin must not be connected either
to ground or to 5 V.
Confidential and· Proprietary
1-33
Preliminary
MicroVAX78032
MicroVAX 78032
+5 Vo----'-'---l2
VCCI
16
ALL CAPACITORS
10".F TANTALUM. +1 -10%
Figure 27· MicroVAX 78032 Power and R.esetConnections
Reset and Powerup Requirements
The MicroVAX 78032 is reset by the following conditions.
1. When power is first applied, the RESET level must be held low for a minimum of 3.0 ms after
Voo has reached 4.75 V. To ensure that the internal voltages are stable before an operation
begins.
2. The RESET level must be held low for a minimum of 3.0 ~s if the RESET level is asserted after
VOD has been at 4.75 V for more than 3.0 ms.
When RESET level is asserted, the MicroVAX 78032 stops executing instrucdonsand enters the
restart process. The restart process sets the CPU to a known state and then passes control to user
code beginning at physical address 20040000 (hexadecimal). For a description of the restart
process, refer to the MicroVAX 78032 Central Processing Unit User's Guide.
Bus Connections
Figure 28 shows a typical interface configuration of the MicroVAX 78032 and includes control
signals and bus connections. The directions of the input and output signal are indicated by the
arrows on the lines.
1·34
Confidential and Proprietary
Preliminary
II'ITERIIUPT
CONTROL
OMA
CONnOL
{§
{=:
m
Hl.i."I'
.PWRFL
iNffiM
MicroVAX 78032
ERR
ROY
RDv
iiM<'3:O>
~
IIM<3:0>
iii
AS
55
AS
•
i5MR
i5MG
A
DAl<31 :00>
MlomVAX78032
CENTI\AL PRDCESSII"G
UNIT
i58e
vm
ADDRESS
LATCH
"
DATA
TRANSCEIVERS _
f f
-
I
~
I'"
y
,. > t.B0<3 .00
...
i5iiE
WR
MicroVAX 78132
FLOATIJ:oja
POINT
iPS
CLKI
l(
t.M<31:00>
.-~
w..,
-,I
Rffii
L
I
J
UN,.!'
CS<2:0>
CLKO
""""c
rn;
CS<2:O>
CLKO
Figtlre 28 • MicroVAX 78032 Typical IntCrfoce Configt:lrati,on
. BusCydes
A bus cycle will be initiated by one of the following conditions:
A microcycle is the bask timing unit for abus~cle. Amic.rqcyde-is shown ih Figure 29 and is
defined as four cycles of CLKO'{TI through T4}~
"
• Acknowledging an interrupt by reading the device interrupt vector.
• Transferring information from or to an external processor.
- - - - -.....- - - - -..'C.OCVCL.-----!
CLKO
Figure 29· MicroVAX 78032 Microcycle
1-35
. .Dill
Preliminary,
MicroVAX18032
CPU Read Cycle
The CPU uses a CPU read cycle to input information from memory or an 1;0 device. A CPU read
cycle timing sequence is shown in Figure 30. A CPU read cycle requires a minimum of 2.0
microcycles and may be extended for slower memory or devices.
MfCROCYCLE
MICROCYCLE
CLKO
OAI.,<:U:OQ>
______~~>---<~__.-oo-.e-~--~)r-------.----------~----~<
~~
:
I
~ ~I
I
,,~------~~------------~
"~-r----------~~
I
/'(
I
I
"'~~------~------~~~--I
CS<2:0>
Figure 30 • MicroVAX 78032 CPU Read Cycle Timing Sequence
1-36
)-
DATA
I
I,--_ _ _~
Confidential and Proprietary
MicroVAX18032
The first microcycle of a CPU read operation is used to transfer the address and control information
and the data is latched into the CPU during the last microcyde.
The sequence of events for a CPU read operation follows:
1. The physical (longword) address is driven onto DAL < 29:02 > and the memory operand length
onto DAL<31:30> by the CPU.
2. The WR signal is unasserted and CS <2:0> are asserted as required to indicate the type of bus
cycle being performed.
3. The BM < 3:0 >llnes are asserted as requited.
4. The AS signaJ is asserted to indicate that the address is valid and can be latched for
de multiplexing and to qualify CS < 2:0> and BM < 3:0> information.
5. The i'5S signal is asserted to indicate that the bus is
to receive the requested information.
The DBE signal is also asserted at this time and can be used to control the DAL bus transceivers.
6. If the requested data is valid, itcan be placedonthe bus duringT30ft~~~t~e, the
external logic asserts the'RD? signal; and the miciocyclethat fOllOWs is the last for thisbus cycle.
If theRDY signal is not asserted by the end of the cUrrent micfuCycle, thebuscyde will be
extended by one microcycle.
If a bus error occurs, external 'logic responds by asserting' the 'E'Usignal.. If '~'is asserted
during a data read, the CPU ignores the data onDAL< 31:00 >,' extends the bus cycle by one
microcycle, and initiates a nw:hlne ch~~k. IftheERR,signalis~tetld~~aninstruction
read witheS <2:t1> •..; 100, ,the, CPU ", stpps...prefetd1ing:"and"whentheitist:ruCtion buffer is
empty; the CPU will attempt to £~tch the nextinstructiotl,.~, ~~h a data rea,d cyqe\ The ~
signal takes preceden~ overtheR:iJ'2' signal;Theas~ttitlno£eithe:r RD"Vor tileERR signals
.'
.
.
results in the completion of the current bus cycle.
free
7. The requested data is latched into the CPU and the DS signal is deasserted.
8. The AS and DBE signals aredeassertedto end the, bus cycle.
CPU Write Cycle
The CPU uses a CPU write cycle to transferWormationto~emol:Y or,to an 1/0 device. A CPU
write cycle, shown in FiguJe 31, requires a minimum of 2 microcycles and may he extended for
slower memory or devices. '
" '
"., -
1·37
-----
___
'-----~----_=
..0'
MicroVAX78032
CLI(O
DAl~1:og:..
I
I
'a
--/"1I
/
I
I
I
--.-/:
~~~I~
w.~
CS<2:0>
ADDRESS
>eX- - - - - . . . - - - - - - ,x==:
DATA
I
"
'--------,------------/:
I
I
~'-----~/
/:
"'"
"'---:---------......
I
~
----~------------~---------------t=J(
--ex
t=
I
I
I
I
_h~~G_
I
I
I
I
Figure 31 • MicroVAX 78032 CPU Write Cycle Timing Sequence .
The first microcycle of a CPU write operation is used to transfer the address and control
information and the valid data is written during the second microcycle.
The sequence of events for a CPU write operation follows:
1. The physical (longword) address is driven onto DAL < 29:02> and the memory operand length
.
is onto DAL<31:30> by the CPU.
2. The WR signal is asserted and CS <2:0> lines are asserted as required.
3. The BM < 3 :0 > lines are asserted as required.
4. The AS signal is asserted to indicate that the address is valid and can be latched for
demultiplexing and to qualify the CS<2:0> and BM<3:0> information.
5. The DBE signal is asserted and can be used to control the DAL bus transceivers.
6. The CPU drives data onto the DAL bus and asserts the DS signal to indicate that the data is valid.
7. If the data can be read during the next microcycle, the external logic asserts the RDY signal and
the following microcycle is the last for this bus cycle. If the RDY signal is not asserted by the end
of the current microcycle, the bus cycle will be extended by one microcyde.
If a bus error occurs, external logic responds by asserting the ERR signal and the CPU initiates a
machine check. The ERR signal takes precedence over the RDY signal.
The assertion of either the RDY or ERR signals results in the completion of the current bus cycle.
1-38
Confidential and Proprietary
-
MicroVAX18032
8. The DS sign,al is deasserted to indicate that the data will be removed from the OAL bus by the
CPU.
9.· The AS and DBE signals are deasserted to end the bus cycle.
Interrupt Acknowledge Cycle
An interrupt acknowledge cycle is used to acknowledge an interrupt request from an I/O device,
and to read a vector. The structure of this cycle is the same as a CPU read cycle shown in Figure 30.
The first microcycle of an interrupt acknowledge cycle is used totransfe;1.' the interrupt priority level
(IPL) that is being acknowledged and the interrupt vector from the interrupting: device is latched
into the CPU during the last microcycle.
The sequence of events for an interrupt acknowledge cycle is as follows:
1. The CPU places the IPL of the interrupt being acknowledged on DAL<04:00>.
OAL<29:05> lines are zero and the DAL<31:.30> lines are =10.
2. Lines CS < 2:0 > are asserted to indicate an interrupt acknowledge cycle .
.3 . Lines BM < .3 :0 > are all asserted and the WR signal is unasserted.
4. The AS signal is asserted to indicate that the IPL level on the OAL < 04:00 > lines is valid.
5. The OS is aSserted to indicate that the bus can receive incoming data. The DBE signal is also
asserted at this time and can be used to control the DAL bus transceivers.
6. If no error occurs, the· external logic responds by placing the interrupt vector on the
OAL < 09:02 > lines the normal Q-bus processing flag on OAL < 00 >, and by asserting the
ROY signal. The OAL < 15:10,01 > lines mustbe a high or low level in aceqrOancew,iththesetup
times specified in the timing diagrams.
7. If an error occurs, the external logic asserts the ~RR signal and the CPU cancels the cycle and
ignores the data on the OAL bus.
.
8. The interrupt vector is latched into the CPU and the i5S signal isde~~erted.
9. The AS and DBE signals are deasserted to end the l;>uscycle. .
DMACycle
A DMA cycle shown in Figure 32, is used by the CPU to relinquishcontrolofthe DAL bus and
related control signals upon requesdro~ a DMAdevice or anot.h~CPU.
The sequence of events for a DMA ,cycle is
1. The DMA device requests use of the bus by asserting thepMR signaL
2. The CPU samples the OMR line for a DMA request during each microcycle unless the current bus
cycle is a read lock cycle.
3. The CPU causes theDAL< 31:00 > , AS, i5S,013E,WR,B¥~3:0>" andCS<2:0> lines to
become a high-impedance and asserts the 'f.5MG line to grant the DMA device use of the DAL
~s.
.
.
4. When the requesting device is finished using the bus, it deasserts the i5MR signal, and the CPU
takes control of the bus.
Confidential and Proprietary
1-39
mllllllB
I"
~
DMii
i5I.1G
CML<31:OU·
D-l:_:...
d_. '.
.......;;.l.Uu.u.uu:,].•
I
MicroVAX t80'32
t,
~,~-------\(/
,,-----"')~
- - - \ 'I
~:.
~\~------------~
>
----i
~--------~--------------~~
----i
~------------~------------~~
----i
---\
----i
\----------------~c==
AS
os
We
aM,
C5<1~,
Figure 32· MicroVAX 780}2 DMA Cycle Timing Sequence
• External Processor Cycles
The CPU uses external processor cycles to communicate with external processors and external
processor registers.
External Pmc:essor Read Cycle
The external processor read cycle shown in Figure 33 is used to transfer information from an
external processor or external processor register to the CPU. An external processor read cycle
requires one microcycle.
The sequence of events for an external processor read cycle is:
1. The CS < 1:0> lines are ~serted as required and the CS21ine is sustained at a high level.
2. The WR signal is not asserted for a read cycle.
3. The EPS signal is asserted to indicate that an external processor bus cycle is in process and to
qualify the CS < 2:0 > lines.
4. The external processor places the requested information on the DAL.
5. The requested information is latched into the CPU and the EPS line is deasserted.
6. The external processor removes its information from the DALbus to end the bus cycle.
External Pmc:essor Response Cycle
The external processor response cycle shown in Figure 33 is used to transfer information and a
completion or confirmation signal from an external processor or external processor register to the
CPU. An external processor response cycle requites one microcycle.
.1-40
Confidential and Proprietary
Preli11Ull8tY.
.
T4
\'
Tl
.
~
ClKO
I
I
I·
DAl<31:00>
I '
I
I
I
CS
CS2
----IX
'l
lX~--"--~----,x,---:--_
I
I
Ir-----~--------~--------~
---~
r'-----
\~.~~~~I
--
Figure 33 • MicroVAX 78032 External Processor Read/Re~me Cycle Timing Sequence
The sequence of events for an external processor response cycle is:
1. The CS < 1:0> lines are asserted as required and the CS.t~i~:sus~athigh level.
2. TheWR signal is not asserted fo:r a read cycle.
. .
3. The EPS signal is asserted to indicate that an external pmcessor bus cycle is in process and to
qualify the CS<2:0> lines.
.
4. The external processor places the requested information on the DALbus and optionally drives
the CS2 line low.
5. The requestedinfotmation is latched intOthe'CPUnnd theE.PS signal is deasserted.
6. The external processor removes its information from the DAL bus and deasserts CS2, if asserted,
to end the bus cycle.
Confidential and Proprietary
Preliminary
MicroVAX 78032
External Processor Write Cycle
The external processor write cycle shown in Figure 34 is used to transfer information from the CPU
to an external processor or external processor register. An external processor write cycle requires
one microcycle.
The sequence of events for an external processor write cycle is:
1. The CS < 1:0> lines are asserted as required and the CS2line is sustained at high level.
2. The WR signal is asserted .
.3. The EPS signal is asserted to indicate that an external processor bus cycle is in process and to
qualify the CS < 2:0 > lines.
4. The CPU drives the information onto the DAL bus.
5. The BPS signal is deasserted and the external processor reads the infromation to the bus cycle.
MICROCYCLE
CLKO
I
I
DAL<31:00>
EPS
--<
)
(
I
I
~I
~
I
WR
DATA:
~
I
CS<2:0>
(c:X
/
>-
I
I
~
I
b
I
Figure 34 • MicroVAX 78032 External Processor Write Cycle Timing Sequence
• Memory Access ProlDcol
The 28-bit address provided by the MicroVAX 78032 on DAL < 29:02> is a longword address that
uniquely identifies one of up to 268,435,456 32-bit memory locations. The chip provides four-byte
masks, BM < 3:0>, to select byte accesses within the 32-bit memory locations. No restrictions
exist on data alignment. The data may start at any memory address except for the aligned operands
of ADAWI instruction and the interlocked queue instructions.
The memory consists of four parallel 8-bit banks, each of which receive the longword address on
the DAL<29:02> lines in parallel. Each bank reads or writes one byte of the data bus
(DAL<31:00», when its byte mask signal is asserted as shown in Figure 35.
1-42
Confidential and Proprietary
Preliminary
MicroVAXi8032
CPU read or write operations are grouped into one of the following categories-byte access, word
access within a longword, word access across longwords, aligned longword acceSs, and unaligned
longword access. Quadword accesses are treated as two successive longword accesses, with no
optimization. Byte accesses, word accesses within a longword, and aligned longward accesses
require one bus cycle. Unaligned longword acCesses and word accesses that cross a longword
boundary require two bus cycles.
8M<1>
..
. 8M
,~~
BBITS
BBITS
BBITS
OAL<31::M>
I>AL<23;16>
I>At<1.5;(11:>
semi
OAL<29:02>-
I>At<07:00>
Figure 35 • MicroVAX 78032 Memory Organization
. External Processor Protocols
External processor protocols allow the MicroVAX 78032 to communicate efficiently with one or
more external processors. Two external processor protocols exist-one for communicating with the
optional floating-point unit and the second for communicating with processor register logic.
Floating-Point Unit Protocols
The optional floating-point unit (FPU) is coa.trolled by the CPU. When the CPU receives afloatingpoint instruction, it passes the opcode and operands to the FPU for processing. The CPU waits for
the FPU to complete the operation and then requests status information and the processing results.
The FPU protocol is as follows:
1. Command transfer-The CPU performs an external processor write cycle to ttansmit a
command to the FPU. During this cycle, the CS contains 00 indicating a FPU command
and the opcode of the floating-point instruction is placed on the DAL < 08:00 > lines.
2. Operand transfer-The VAX opcode determines the number and data type of operands to be
transferred from the CPU to the FPU. The CPU performs one or more external processor write
cycles to transfer the operands. During these cycles, the CS < 1:0> lines are equal to 01 (data
ttansfer), and the DAL< 31:00 > lines contain the data to be transferred.
Confidential and Proprietary
1-43
Preliminary
MicroVAX'78032
3. Operand processing-While the FPU.is processing the operands, the CPU checks to determine
.where the operation is completed by executing extemalprocessor response enable cycles.
4. Status transfer-When ·the. FPU has finished processing the operands, it ·responds to the next
external processor response enable cycle by placing status information on the DAL<05:00>
lines and by driving the CS2 bus low. The CPU responds to the CS2 low signal by reading the
status information on the DAL < 05 :00> lines.
5. Result transfer-After reading the status code, the CPU may initiate one or more external
processor read cycles to transfer the result operand(s). During these cycles, the CS < 1:0> lines
are equal to 01 (data transfer), and the DAL<31:00> lines contain the data to be transferred.
The VAX opcode determines the number and data type of the operand(s) to be transferred from
the FPU to the CPU.
Register Protocols
The external processor register protocol permits the external logic to implement processor register
functions that are a part of the MicroVAX architecture but are not implemented in the hardware of
the MicroVAX 78032. Refer to Table 16 for the processor registers implemented by the MicroVAX
78032. The following CPU protocols are used with a move from processor register (MFPR) or move
to processor register (MTPR) instruction to access a register not contained in the CPU.
Read from processor register-The read from processor sequence is shown in Figure 36. This
sequence is performed when an MFPR instruction is used to read data from processor registers 25
through 39,48 through 55, or 59 through 61. The protocol is as follows:
,
1. The CPU initiates an external processor write cycle to specify the register number. During this
cycle, the CS < 1:0> lines equal 10 to indicate to a non-FPU command, the DAL < 31 > lines
equal 1 (read register), and the DAL<05:00> lines contain the register number specified by the
MFPR instruction.
2. The CPU waits one cycle and then executes an external processor response cycle to read
the register data. If the CS2 line is driven low by the external logic, the data on the
DAL<31:00> lines is the result of the MFPR instruction. If the CS2line is high, the CPU
returns zero as the result.
i_i"
I
I
I
,
I
I
wo~
-,., =:=x,.-------..~(««~<<(c=
=::==>'
~%««<{I««(«<{~««»)J~J))J$_
\ -----1--1=
1
I " ,
cs<'>
IiXHPoNAI. i"fIOC~SSQR
COMIoU./oiD (:'f(:U
NON·~f'lI
I
Nt).O~ "
E)ITIlA"",,U l"kOCES$OP
R£.,t,DIk(SP(l~ cvcv
Figure 36· MicroVAX 78032 Read from Processor Register Timing Sequence
1-44
Confidential and Proprietary
I
-
Preliminary
....
MicroVAX780J2
Write to processor regj.ster.....The write to processor register sequence is shown in Figure 37. This
sequence is performed when an MTPR instruction is used to write data to· processor registers 25
through 39, 48 through 55, or 59 through 61. The protocol is as follows:
1. The CPU initiates an external processor write cycle to specify the register number. During this
cycle, the CS < 1:0> lines equal 10 indicating a non-FPU command, the DAL31lines equal
o (write register), and the DAL lines contain the register number specified by the
MTPR instruction.
2. The CPU executes an external processor write cycle to write the register data. During this.-cycle,
the CS < 1:0 > lines equal 01 (write data), and the DAL< 31:00> lines contain the data specified
in the MTPR instruction.
3. The next cycle is not an external processor cycle.
MfCROCVCLE
MICROCYCLE
T1
T2
T4
T3
Tt
CLKO
I
llAL
~~~I~
I
I
W.a
_/H:
~,-_ _ _...........
I
WAiTEOATA
~
:.
:
~~______K=
I
CS<2>
I
I
. t
I
CS<1:0>
>--,,"-____. . ./..-lj>---
~I>_--------~<:E;,!!::~NUMBER)>---------~(
I
~--------r-------~K=
I
I
EXTERNAL PROCESSOR NON·FPU
COMMAND CYCLE
E,XTEfiNAL PROCESSOR WR!TE CYCL£
Figure 37 • MicroVAX 78032 Write to Processor Register Timing Sequence
de Elect:ric,.t Characteristics
The de electricalcharaeteristicsofthe MicroVAX78032 for the operating voltage and temperatw:e
ranges specified are listed in Table 17.
Confidentwa.ndProptieWy
1-45
. .Dill
Preliminary
MicroVAX 78032
Tablel7 • MicroVAX 78032 dc Input and Output Parameters
Parameter
Symbol
Requirements
min
max
Units
High-level input voltage
~H
2.0
V
Low-level input voltage
~L
High-level output voltage
VOll
Low-level output voltage
VoL
High-level output
voltage (EPS only)
VORl!
Low-level output
voltage (EPS only)
VOLIl
Input leakage
current (CS2)1
IlLS
Input leakage current
IlL
Output leakage current
IOL
Active supply current
0.8
Test Condition
V
V
loR = -400~
IoL = 2.0 rnA
V
loR =
0.2
V
IoL = 1.0 rnA
3.2
rnA
~N
-10
10
~
0.4
-10
10
~
Inn
700
rnA
Input capacitance
CIN
8.0
pF
Output capacitance
COUT
8.0
pF
V
2.4
0.4
2.6
-100~
= 0.4 V
< ~ < Vnn
0.4 < ~N < Vnn
loUT = 0, 1;. = OC
Note:
lWhen CS2 is sustained high by the CPU the maximum sustainer current (IlL) is 3.2 rnA.
ac Electrical Characteristics
The input and output signal timing parameters for the MicroVAX 78032 is shown in Figures 38
through 43.
The following notes apply to Figures 38 through 42 and their associated timing tables.
1. Formulas for the timing parameters are stated in terms of the CLK! period. CLKl
period = top =P.
2. All times are in nanoseconds except where noted.
3. The ac characteristics are measured with a purely capacitive load of 100 pF. Times are valid for
loads of up to 100 pF on all pins.
4. ac hlgh levels are measured at 2.0 volts and aclow levels at 0.8 volts except for the BPS and TEST
signals.
5. An ac hlgh level for the EPS and TEST signals are measured at2.2 volts and an ac low level at 0.6
volts.
6. S = the number of microcycles slipped during a bus cycle.
7. The sampling window is used to sample the following asynchronous signals: RDY, ERR, and
DMR. The RDY and ERR signals are qualified when AS is asserted. The DMR signal is qualified
by the AS signal being deasserted. The effect of these signals on the current bus cycle is as
follows:
1-46
Confidential and Proprietary
Preliminary
MicroVAX 7ICB2
• The bus cycle will conclude at the end of the current microcycle if the RlSY signal is asserted. and
the E'[R signal is not asserted throughout the sampling window while the AS sigr$lisasserted.
• If the ERR signal is asserted throughout the sampling window while the AS signal is asserted, the
current microcycle becomes an extension cycle and the bus cycle ends after the .next microgcle.
• If the RDY or ERR signals go through a transi~>duringtheS4.U1lplingwindowwhile.theAS
signal is asserted, the result is indeterminate,
• The DMR signal is sampled at every microcycleboundary.
• If the DMR signal is asserted throughout the sampling window and the AS signal is not asserted,
and the CPU has not locked the bus, the next mierocycle will be the beginning of a DMA cycle.
the .
• The first microcycle ~ter the end of the/current bl:'s cycle 'YPl pegin a I?MA. cyclei!
~
signal is asserted throughout the sampling wfuilow, theA:'Ssigril:ll is a~serted, and the CPUhas not
'.. . .. '
. ...
. .
locked the bus.
• A DMA cycle concludes at the end of the current microcycle if the DMR signal, is deasserted
throughout the sampling window.
8. There are no internal pull-up circuits on theIRQ<3:0>, N$FL, INTTIM, and HAlT lines .
. Specifications
The mechanical, electrical, and environmental·characteristiClS and specifications for the MicroVAX
78032 ate described in the following paragraphs. The test conditions for the dectrical values are as
follows unless specified otherwise.
• Operating temperature (T".): 70 0 e
• Ground reference (Vss): 0 V
• Supply voltage (Vnn): 4.75 V
Meclumical Coniiguration
The physical dimensions of~he MicroVAX 78032 68-pin cerquad package are contained in
AppendixE.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratingS may ¢3use. ~rmanent damage to the deviCe.
Exposure to thtl absolute maximum ratings for extended' periods may adversely affect the
reliability of the device.
• Supply voltage (Vnn): -0.5 V to 7.0 V
• Input or output voltage applied: -0.5 V to 7.0 V
• Active temperature (T.J: ooe to 70°C
• Storage temperature (1;): -55°e to 125°C
• Power dissipation: 3.5 watts (maximum)
Confidentialand.Proprietary
1-47
.".'i.
MicroV.Mf7S0j2
Preliminary
~otnrnended Operating COnditions
• Supply voltage (Vou): 4.75Vto·5.25V
• Active supply cu~nt: (100): 700 rnA (maximum)
• Relative humidity: 10% to 95% (noncondensing)
• Minimum airflow over chip: 250 linear feet/minute
Cloclc Input Tuning
Figure 38 shows the timirigspecifications for the eLKI input clock signal andTable 18 lists the
timing parameters indicated on the diagram.
.
Figure 38 • MicroVAX 78032 eLKl Timing Wave/orm
Table 18 • MicroVAX 78032 eLKI Timing Parameters
Timing Symbol
Signal Definition
tCIF
Clock in fall time
telH
Clock in high
8
telL
Clock in low
8
ten>
taR
Clockperiod
25
Requirements (ns)
min
max
Clock in rise time
Confidential and Proprietary
4.5
50
4.5
Preliminary
CPU Read and Write Cycle Timing
Figure 39 .shows the timing sequence for the CPU read cycle and Figure 40 shows the timing
sequence£or the CPU write cyele. The parameters for the CPU read arid write cycles
listed in
are
Table 19.
Figure 39 • MicroVAX 78032 CPU Read Cycle Timing Sequence
ConfidelltW a119 Propri~
--
Preliminary
MicroVAX 78032
Figure 40· MicroVAX 78032 CPU Write Cycle Timing Sequence
Confidential and Proprietary
-
MicroVAX lID)!
1iahle·19 ~ MieroVAX 78012 CPU aridWri1e CydePatameten
Tuning Sipal Defiaition
Symbol
Add.ress set up time to AS assertion
RequiremeDts (as).
max
min
2P-28
tASA
Address hold time after AS assertion
t ASHc
AS rising through 2.0 V to CLKO rising throughO;SV
P.;.)2J.
t ASLC
AS falling through 0.8 V to
1>-20
CLKO rising through 0.8 V
AS· assertion to DBE and i5S (read) assertion
3P-15
AS asSertion toreaddatavalid1
tASnsoAS
llP-.30+8PS
assertion to D'S assertion (write)
.5P+20
tASOZ
AS and DBE deassertion to data three-state
t ASHW
AS deassertion Width
.3P .
tASUI'
AS asserti~ width
121:':"1.5 +8),S
tASWB
tAS'IL'E
tAS'IL'lI
.3P+20
2P-20
(61'.,-45) +8PS
AS assertion to beginning of
RiJY, ERR, andi5MR sampling windoW
AS assertion to end of ID5Y,
6P+I0+8Ps·
ERR, and DMR sampling windoW
WR, BM < 3:0 >, CS <2:0> hold
time £;c,om AS deasser~
·P-l0
I:c:.uH
CLKO rising through 2.0 Vto AS rising thro~ O.S\1
P+15
tc.uL
CLKO rising through 2.0 V to AS falling through 2.0 V P-9
P+16
teo)
CLKO rising through 2.0 V to read data valid
P-5
tCDO
Write data hold time from CLKO rising through 2.0 V P-15
ter
CLKO fall time
trn
CLKO high
(2P-25) x.5
teL
CLKOlow
(2P-25) x.5
to.
CLKO period
50
tea
CLKO rise time
12.5
teWB
T4 CLKO rising through 2.0 V to beginning of
RDY, ERR, and DMR sampling window2
.3P-45
!:ewE
T4 CLKO rising through 0.8 V to end of
RDY, ERR. and DMR sampling window}
12.5
100
.3P+ 15
1·51
Table 19- MictoVAX i80:J2 'CPUaru:tWrite GydeParameters(Cont.)
Timing Signal Definition
Requirements (ns)
Symbol
min
tDBLW
DBE assertion width
9P-20+8PS
tooc
Write data set-up time to CLKO rising through O.S V
.3P-42
tOODS
Write data set-up time to OS assertion
.3P-30
t 05AS
DS deassertion to AS and DBE de assertion
P-15
tUSD
Read data hold time after l5S deassertion
0
tusm
DS assertion to read data valid'
tusoo
Write data hold time from DS deassertion
t050Z
i5S deassertion to read data high impedence
t DSHW
6P
t 05LWI
DS deassertion width
OS assertion width (read)
tDSL'lVO
DSassertion width (write)
6P-20+ SPS
tWEDI
Sampling window end to read data valid
t wllAS
WR, CS < 2:0 > .set up time before
max
SP-35+8PS
3P-20
3P:20
8P-20+SPS
5P-25
3P-.35
AS assertion
Notes:
, Read data is valid early enough if t ASDI or t 05m or tcmis satisfied.
1 Requirements for the beginning of the sampling window are satisfied if either t ASWD or tCWD is
satisfied.
) Requirements for the end of the sampling window are satisfied if either t ASWE or tcW! is satisfied.
1-52
Confidential and Proprietary
...
MicroVAX: 7$Ol2
Ditect Memory~ss CydeT"1Dline:
Figure 41 shows the timing ~u~nce for direct memory acces&(DMA) transfers and Table 20 lists
the timing parametetsfor the symbols referenced on the diagram. .
OAl
----\
----\
'ASG
AS
'G••
os
DiE
iiii<3:i>.
QK2~
----\
Figure 41 • DMA Timing Seq~e
1-53
MicroVAX 78032
Requirements (os)
min
max
Timing Signal Definition
Symbol
t ASG
AS and DBE deassertion to DMG assertion
4P-25
troH
CLKO rising through 2.0 V to
DMG rising through 0.8 V
P-7
P+16
teGL
CLKQ rising through 2.0 V to
DMG falling through 2.Ov
P-7
P+18
t OMKG
DMR to DMG latency
10P~25
60P + 20 + 16PS
tOMIlGU
DMR to DMG latency with
bus unlocked
10P-25
28P+20+8PS
DMR hold with respect to
0
tmwl
i5M:"G assertion
teOALZ
DMG deassertion to external
device three-state of DALS.
4P-20
teOMlt
DMG assertion to'i5MR deassertion
such that no more DMA cycles are
requested
6P-45 +
«N-2) X 8P)1
teRe
DMG rising through 2.0 V to
CLKO rising through 0.8 V
P-25
tmc
DMG falling through 0.8 V to
CLKO rising through 0.8 V
P-23
teL'&'
DMG minimum assertion width
10P-25+
«N-2) X 8P)!
tesz
DMG assertion to three-state
of AS, DS, DBE, WR. CS<2:0>
andBM <3:0>
-10
DMG deassertion to external
device of three-state of AS, DS,
DBE, WR,CS<2:0> <3:0>andBM <3:0>
0
3P-202
Notes:
• The number of microcyles that occur during a DMA grant. A DMA grant is issued for a minimum
of two microcycles.
2 At the conclusion of a DMA grant the external logic must deassert the AS, DS, and DBE signals
before the external bus drivers become a high impedance.
External Processor Cycle Timing
Figure 42 shows the timing sequence for the external processor read and response timing and for
the external processor write command timing. Table 21 lists the timing parameters for the symbols
referenced on the diagrams.
1-54
Confidential and Proprietary
-
MicroVAX.78032
ClKO·
DAL<31:00>
CS
CLKO
DAL<31:00>
Cs<2:(l>
External Processor WrlteICommand Timing
Figure 42 • MicroVAX 78032 External Processor Cycle Timing Sequence
Confidential andfroprietary
MicroV.t\X'8032
. Table 21 • MicroVAX 78032 External Processor Cycl~ Timing Parameters
TlR1in8 Signal De£iniiioQ
Requirements
Min.
Max.
Symbol
t eEP
CLKO falling through 0.8 V toEPS falling through 2.2 V
P-5
t OOEPH
Write data valid set up time to EPS deassertion
2P-35
t EPCSL
EPS assertion to eXternal processor assertion of CS < 2 >
0
3P-40
t EPCSZ
EPS deassertion to CS < 2 > three-stated by external processor
0
2P-20
tEPD[
EPS assertion to read data valid
t EPF
EPS fall time from 2.2 V to 0.6 V
0
t EPHOO
Write data hold time from EPS deassertion
2P-25
t EPLe
EPS falling through 0.6 V to CLKO falling through 2.0 V
P-25
tEPLWI
EPS assertion width (read)
4P-20
4P+20
tEPL\lIO
EPS assertion width (write)
5P-20
5P+20
tEPWIl
WR and CS < 1:0> hold time from EPS deassertion
P-20
tEPZ
EPS deassertion to read data three-state
t\ll1lEP
WR and CS < 1:0 >' set up time before"':Ei5!; assertion.
P+19
4P-40
10
3P-20
2P-35
Reset Tuning
Figure 43 shows the timing sequence for the reset function of the processor and Table. 22 lists the
timing parameters for the symbols referenced on the diagram.
eLlm
Figure 43 • MicroVAX 78032R.eset Timing Sequence
1-56
Confidential and Proprietary
...
MicroVAX 78032
18ble 22 • MiaoVAX 78032 Reset Tuning Parameters
Tuning Signal Definition
Requirements (08)
min
max
Symbol
tus
RESET deassertion to first CLKO pulse if RESET
is deasserted synchronously
3P+10
t RESC
Number of CLKO periods from RESET deassertion
until first DAL activity
32 periods
tUSGH
RESET assertion to DMG, EPS deassertionl
150
t RESH
RESET assertion to AS, DS', 15BE, WR deassertionl
1.0 IlS
t RESW
R'ESET assertion width after VDO := 4.75 V
3.0ms
RESET assertion width if VDO has already been at 4.75 V
for 3 ms when ImSEf is asserted
3.0 IlS
tUSWII
tRI!SZ
RESET assertion to DAL< 31:00 > ,JUOlt<3:0>,
CS<2:0> highimpedence'
3P+85
100
Notes:
1 When the RESET level is asserted, theDMG and EPS signals become high and remain high.
l When RESET is asserted, AS, DS', I5BE and f t outputs become a high impedance state and the
levels become high by low current internal pull-ups.
~ When the mft level is asserted the BM<3:0> lines and CS<2:0> lines become highimpedance .
• Meehanical Specifications
The dimensions of the MicroVAX 78032 68-pin cerquad surface and socket mount packages are
shown Appendix E.
Confidential and Proprietary
1-57
--------_._----------
• High performance
-Accelerates by 50 times the execution of MicroVAX floating-point instructions
-Accelerates by two times the execution of MicroVAX integer multiply and divide
• Subset (70 instructi.ons) of the VAX floating-point instruction set'
• Operates with standard VAX integer data tYPes· "
-byte, wOrd, IOngWord, and quadwortt
• Operates with standard VAX floating-point data types
-single-precision (FJ!oating)
-double-precision (D.Jioati?g)
-extended range double-precision (G_flollting)
• Arithmetic error checkill&andreporting
• High-speed ZMOS technology
• Single 5 Vdc power supply
• Description
The MicroVAX 78132 Floating-Point Unit (FPU), contained in a ~-pin cerquadpackage, is a highperformance cooperative processor that extends the data paths of the MicroVAX 18032 central
processing unit (CPU). Its primary functiot1·is to exeCUte MicroVAXfloating-point instructions to
eliminate the emulation of floating-pomtirtstrUCfionsin software. Figurel is a general block
diagram of the MicroVAX 78132 F P U . · '
..
FRACTION
DATA M1H
FRACTiON
CONTImL
'61
13
MAIN SEQUENCER
12IJO X 35J
CS2
CS1
cso iNA EPS
Figure 1 • MicroVAX 78132 General Block Diagram
Conf~deQti1ll~nd Proprietary
f;.mrr:r _.ltllJClIUIII! _ _
1!m~l~Z:"'"
1-59
- -......- - - - - . - -_ _ _........
IiSll. . . .IU
.................
" ......_ _ _ _ _ _ _ _ _ _ _ _ _ __
·.~ ..
the Mi~VAXFPU handles the FJIoating (single-ptecision), D_floating (double-precision), ~d
G.J1oating (extended range double-precision) VAX floating-point data types. It supports several
VAX floating-point operations, including floating-point add, subtract, multiply, divide, .and
convert.
The MicroVAX FPU also accelerates the execution of integer multiply and divide operations. The
FPU supports sign~d integer ~ultiply and unsign~d integer divide operations .
• Pin and Signal Descriptions
This section provides a brief description of the input and 0\ltput signals and power and ground
connections of the MicroVAX 78132 68-pin package. The pin assignments are identified in Figure 2
and the signals are summarized in Table 1.
DALOO
EPs
'CS2
DALOI
60 59 58
61
DAL02
62
DAL03
63
DAL04
64
DALOS
65
DAL06
66
DAL07
81
vce
68
VSS
NC
vec
vee
NC
51 56 55 54 53 62 51 50 49 48 47 46 45 44
r------------,
I
I
I
I
I
I
MicroVAX 78132
L
FLOATING-POINT UNIT
OAL31
42
DAl30
41
DAU9
40
DAU8
39
DAL27
311
DAUB
37
OAL25
36
OAU4
vec
vss
I
35
2
I
34
VSS
DALOB
3
33
vss.
OAL09
4
I
I
32
OAL23
DAllO
5
I
31
DAL22
DALlI
6
'L ___________ ..JI
30
CAUl
29
DAUO
VSS
(FPUI
I
DALl2
DALl3
8
28
DALIS
DAL14 .
9
27
DALl8
10 11 12
DAllS
vec
13 14 15 16 17 18 19 20 21 22 23 24 26 26
ClKI
RESET
VSS
NC
NC
VSS
Figure 2 • MicroVAX 78132 Pin Assignments
1-60
43
Confidential and Proprietary
DAL17
Preliminary ,
MieroVAX 7852
,1We 1- MkroVAX 78132 ~ and Signal S~,
43-36,
32-25,
10-3,
'DAL<31:00>
input/output Data/address lines-1tansfersdata, status, and
control information between the FPlhmd'CPU.
67-61
57-56
input
CS<1:0>
eoritrolstat~;< 1:0> ~IndkateSthetypeo{
, in£6rnlation~ingtransferred to ot'fromihe PPU
(commarid$,': dats:; orrespofiseenable). Valid
when EPS is asserted.
CS2
58
55
output
Con~lVl ,s~t'9s
2__A~~ 9ut~.anexternal
piocessor~ppnse, .,~1lable b~s' cYcle" wh~n'
FNJ hascq~~~~e ~O~~9~ ()pe,ration.
input
Write.:.....Irlpii'tfrom theMicroVAKCPUfuafindf.
cates' ~ta,aj')w;dU:ection. '~n,ass.etted.,jndl~
cates_flmjJtQmm~·cputo the FPU. Valid
the
,.wheiimil,~~Q.
tps
54
input
txternaIv~t stroqeAsserted'by the
MicroVAX CPIJ to qualify aU' tommurucation
i
between the FPU and CPU.
16
RESET
input
Reset ___Asserted by external logic to resynclm:>~~~ FPVi with ,the CPU.
14
CLK!
input
CIockiD,pUt,~J:4tisi!;r;igek timing input. to, the
FPU. Has the ~amei£l:equency as the MicroV~
CPU clock~CLKI)input.
45
VIII
output
BaCk-biasvoltage.
".,
'I"
Vee
input
VOltaSe-Powet! supply de voltage
1,2,17,18,
Vss
23,24,33,34,
52,53
input
GroundLCommon ground ref.f!rence
11-13,46-48,
35,68
15,19-22,
44,49-51,59
No connection-All unused pins should be left
NC
~oating
and not pull~
up;- or,',,'_grpWl~.
.-' - -';,' -:""\ ,r:"
- '"
'>;,,:
j ' ','
nata and Address Bus
Data, and address bus (OAL < 31:00 > )- The data and address bus is a time-multip~9 bidirectional bUll that transiel'sacidress, data, statUll, and control~nforlllation between the, FPlt~Jhe
GU. The MicroVAX CPU is always the bus master and communicates with the FPU'according to
the protocol outlined in the "CPUjFPU General Protocol" discussion.
Con£idet1tial-and'~
''''$'1.1'1'''"._ _....._
1-61
_n_n__
llli_iIII-..
............._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ._. _ _ _ .•. _._,_'"_ ... __ ;
. ._ _ _.
_ . ..
_!'"""-1.i!
__
._
........." "
__
PHI.l.,..
..
_ ..&1Il
. .................
-
MicroVAX78132
BUll Control
m
E:x:ternal processor strobe (EPs')~1'he
si~al is used toWtiate'all CPU/FPUbus cycles that are
external processor bus cydes.ftindicatesto the FPU thanheinformation on the CS < 1:0> and
WR lines is valid. Refer to the "Bus Cycles Description" discussion for more information on CPUr
FPU bus cycles.
For reset operations, the FPU uses the first assertion of the EPS cycle following the assertion of the
RESET signal to synchronize itself with the CPU.
Write (WR)-The WR signal is an input from tqe MicroVAX CPU that specifies the direction of
data flow between the CPU and FPU on the DAL<31:00> lines. When WR is asserted, data is
being transferred from the CPU to the FPU.
System Control
Reset (RESiIT)-External logic asserts the RESET signal to synchronize the FPU and the
MicroVAX CPU. The assertion of RESET causes the CPU to perform a number of EPS cycles. The
first external processor (EPS) cycle synchronizes the FPU and CPU. The remaining EPS cycles are
used to verify the presence of the FPU in the system.
Control Status (CS < 2:0> )-The CS lines p1'OVide status information about the current bus cycle.
The CS< 1:0> lines are inputs to the FPU that specify the type of information being transferred.
CS < 1:0> are valid inputs only when the EPS signal is asserted. The WR signal further qualifies
the type of bus cycle, as summarized in Table 2. Refer to the "Bus Cycle Descriptions" section for
more information on the types of bus cycles.
1.able 2 • M.icroVAX78132 Bus Cycle Types
CSline
1
0
Write(WR)
Bus Cycle Type
0
0
0
External processor command write
0
0
1
External processor data read
0
1
0
External processor data write
1
0
0
Non-FPU command write
1
1
1
External processor response enable
CS2 is an open-drain output that is asserted when the current bus cycle is an external processor
response enable cycle and the FPU·gas completed the current commanded operation.
OoekSignal
Ooc:k In (CLKI)-This signal is the basic timing input provided to both the FPU and CPU from an
external clock Source.
.
Confidential and Proprietary
-
Power Supply Connections
Power (Vbc>"":'Theseinputs are used to supply j Vde power to theFPU.
G~ (V"s)-The~ mputs are used as aground reference for the chip.
Back-Bias Generator (Va.)-This is a ~ek-bias voltage that is either bypassed to ground with a
capacitor (typically 0.01 IJf) or attached to a back-bias supply (typically -2.5 volt± 10% at 10
rnA) .
• Architecture Summary
The MicroVAX 78132 FPU architecture, shown in Figure 3, consists of three separate processors-a
1-bit sign processor, a 13-bit <:x~l;lC:9tJ~mc~r,.~r!~a?7-~lM~(:tipp, ~~essof. The extfublts in
the fraction data path acconunOdateex~precisi()n ins,~io~ Such as EMODx. A nUcrosequencer containing 200 35-bit controlwords~C6n.trtih'ib~fioob£ the three p~ssors;,Data
enters and leaves the FPUJhrou~~~/Qb~£~ .GonttolfRfo~on passes to an~:lfrolll the FPU
through the interface controI·logic.
The following paragraphs descritJe
T
Qr
I
are FPtJarchitectureaccessib~to the user.
CL«Y$
'"
UU""fft
r
~~~~~~~==~~
"
Figure 3 • MicroVAX 78132 Detailed Block Diagram
Confidentlithmd·.Proprietary
1.:.6:3
MicroVAX7tt32
Preliminary
Visible State
The MicroVAX FPU does not contaip user-accessible interpal~gisters.or mode bits. The MictoVAX .'
CPU contains the floating-point general registers al')d con,dition codes. Commands sent from the
CPU to the FPU determine the operational modes (round or truncate) and the data types (for
example, F_£loatingor D.:..£Ioating).
. .
Exception Detection and Reporting
Table 3 lists the exceptions that the MicroVAX FPU detects and reports.
Table 3 • MicroVAX 781.32 Reported Exceptions
Condition
Result Returned to CPU
Reserved operand
Unpredictable~CPU unconditionally faults
Integer overflow
Low order 8, 16, or 32 bits of the true'result
Floating overflow
Unpredictable-CPU unconditionally faults
Floating underflow
Floating zero
Floating divide by zero
Original quotient
Unimplemented instruction. Qnpredictable-"command not valid" exception
The exceptions associated with specific MicroVAXFPUinstructions are described in the following
paragraphs:
Data Types
, '.
. ,
The MicroVAX FPU handles seven data types-byte, word, 16ngword, quadword, F JIoating,
D_floating, and G_floating. Figure 4 illustrates the data tYl'e formats. For a summary of the data
types associated with specific MicroVAX FPU instructions, refer to appropriate instruction
discussions that follow.
1-64
Confidential and Proprietary
Prelimin~
!.lli.
W!!ll!:!.
~
BYTE
8BJTS
51GNEDO(I
UNSIGNED INTEGER
WORD
16 BITS
SIGNED DR
UNSIGNED INTEGER
'3~BtT~
SX!NEOQR
00
07
I
I
I
I
:11
00
15
I
:A,
31
LONGWORD
ONSIGNEClIN'T~GER
j'
64 BITS
SIGNED OR
UNSIGNEO INTeGER
~.
'<;
I';
63
1\1 14 ,"
,51
"
00
-<,',',
' :->1
;-''-lr'
""",;
_".,1
FJLOIITING
I
:A
:;;'1;
31
OUAOWORD
00
~ "
,
t ,
'lI'lfJfk; .'". :,
,fin'
f!XI'Of'/ENTI~crIO'H
FRACTION
I:
32
.',.
:1\
:1\+2
31
64 81T5
FLOATING PoiNT
MBITS
Figure 4 • MicroVAX 78112 Di1f4 Types
1,.65
i
,_,
MicroVAX7&W
• MicroVAX 78132 FPU Instruction Set
The MicroVAX 78132 FPU instruction set consists of floating-point instructions, integer multiplication instructions, and integer division instructions. Refer to Appendix A for a summary listing of
the FPU instruction set.
Floating-Point Instructions
The FPU opcode is a nine-bit code for an FPU instruction derived from the opcode of the original
instruction fetched by the MicroVAX CPU. The opcode for a G.,...floating instruction is the original
instruction preCeded by a 1. The opcode for an instruction that is not of extended range
(GJIoating) is the originalinstruction preceded by a O.
The MOV, MNEG, and TST floating-point instructions are marked with an asterisk to indicate that
they are implemented entirely within the MicroVAX CPU. In a system without an FPU, the CPU
performs a reserved operand fault if an attempt is made to execute these instructions.
The MicroVAX FPU treats a two-operand instruction the same way it treats the corresponding
three-operand instruction. The MicroVAX CPU handles the differences in processing these
instructions.
The POLY instruction is implemented as a continuous, interruptible instruction. The MicroVAX
FPU assists the CPU by performing floating-point addition and multiplication operations. After
each step of the polynomial calculation, an intermediate result is returned to the MicroVAX CPU
and a new coefficient is passed to the FPU. (No new command is issued to process this coefficient
during normal operation.) A new intermediate result is then computed. If the CPU is interrupted, it
can restart the POLY instruction by reissuing the POLY command and sending the most recent
intermediate result, the argument, and the current coefficient.
Integer Multiplication Instructions
The MicroVAX FPU can perform signed integer multiplication. The MicroVAX CPU uses this
capability to accelerate the execution speed ofthe following instructions. Refer to Appendix A for
the format and exceptions of the signed integer instructions executed by the MicroVAX FPU.
Opcode
Instruction
7A
EMUL (Extended multiply)
INDEX (Index calculation)
MULL2 (Multiply long 2-operand
MULL3 (Multiply long 3-operand)
OA
C4
C5
During MicroVAX FPU integer multiplication
• The FPU performs a 32 by 32-bit signed multiplication.
• The FPU in all cases returns a 64-bit result.
• The exception code is zero and the condition codes are unpredictable.
Integer Division Instructions
The MicroVAX FPU can perform unsigned integer division. The MicroVAX CPU uses this
capability to accelerate the execution speed of the following instructions. Refer to Appendix A for
the format and exceptions of the unsigned integer division instructions executed by the MicroVAX
CPU.
1-66
Confidential and Proprietary
-
Opeode
Jnstmction
DIVL2 (Divide long 3-operand)
DIVL3 (Divide long 3-operand)
C7
EDiv(Extended divide)
7B
During MicroVAX FPU integer division',
C6
• A 64.bit dividend is divided by a 32-bitdivisoi
• The operands are unsigned.
• The operands are guaranteed not to cause an integer overflow., {'Fhe MicroVAX CPU checks this
condition before actiwtirtg the FPU.)
• The FPUretllrns a 32-bitresult and a }2,bfrremahlder..
• The exception code is zero and the condition iodes~unp~ble ..:·
• Interfacing Requirements
The MicroVAX 78132 FPUis designed. as a coproceSsor fOttb~ MicioVAX 78032 CPU. Therefore,
all in1:ertacing considetatio~ ~. macie wit1;t~t to. tlua,. ,~rqVM,C~U., The:,1i'PU/<;;:Ptl
inter£ace-inc1qding bU$ cycles, the FPUJCrUJil+'P~l; ~.a~icalfPU/crointerconnection
scheme-is described in thefollowing ~hs;
Bus Cycle Descriptions
The MicroVAX FPUrecognizes five typesot bu~cys;~ :¢it:ttAtilprOc~sorcomtpa:Odwrite,
external processor data read, externalprocessordatawnte, rioo-F$J;coiJ)mandwritejmd' external
processor response enable. The following paragraphs briefly describe these busoycles. RefertQ the
"MicroVAX 78032 32-bitCentral~Qr:.p,~it" ~ti":l:l!o~thei:O~J'Onding MicroVA~CPU
bus cycles. Figures 9 and 10 are detlilledbus~cYcIeJllagroms; . "
. '. .
'
External Processor Command Write-An external processor commandwrite, cycleispertormed
when the CPU has acommatld(typically instruction o~e)Jor ~l:teFPB;~;tead'Md ~xecute.
This type of cyc1elasts fom"clock (CLKOY Periods or onemiCiotjcle.THesequen~ &fevents is .
an
,
'
' t ' "
'.
" "
, ' , .
• The CPU drives cycle-status information ol1llnes CS~:l:P:;;1"(C$~f:;O>:;... pp..£qr"th~ty,pe of
cycle), drives the cQmmandon theDAL<31:00> bus, and assert&J:lie
El5Sand'WR
signals .
",,'t--',
,'.', : - "'i"
.
".
"
'
"
,'"''
,,',"
';-
,
'
,'i
"~"
• The Fl'U reads the opcodeol'ltheDAL.
• The CPU deasserts th~ BPS and 'Wit signaIs,and'the cyde ends: .'
External processordouead-AneJ(temalp~$lIQrd~ta ~~te i§ ~or~ed when the FPU
has data for the CPIJ to process. Thist:ypeofcycIe,lalIts foUl:'.~ peri04s,',I'he seq~eJ>f events. is .
• The CPU drives cycle-status information on lines CS< 1:0> (CS< 1:0> =01 for this type of
cycle) and asserts the BPS signal. The WR signal is not asserted because this is not a write cycle.
• The FPU responds by driving thi,DAL < 31:00> bus wit;hdat~.
• The CPU reads the data.
• The CPU deasserts the BPS signal, and the cycle ends.
1-67
Confidential. and Proprietary
-------------------------_ _-_
..
...
__.....
Preliminary
External processor data write-An external processor data write cycle is performed when the CPU
has data to write to the FPU. This type of cycle lasts f01.ir·clock periQds. The sequence of events is
• The CPU drives cycle-status information on lines CS<1:0> (CS<:1:0> =01 for this type of
cycle) and asserts the EPS and WR signals.
.
• The CPU drives the data on the DAL< 31:00> bus and deasserts th~EPS andWR lines.
• TheFPU responds to the deassertion of the EPS signal by reading the data on the DAL < 31:00 >
bus, and the cycle ends.
N'on-FPU command write-A non-FPU command write cycle is perform,ed when the CPU has an
instruction or command for a processing unit other than the FPU. The sequence of events is
• The CPU drives cycle-statusinfQrmation on lines CS< 1:0> (CS < 1:0> = 10 for this type of
cycle) and asserts the EPS and WR signals.
• The FPU initializes itself, suspends its operation, and disables its outputs so that it cannot
respond to an external processor data read cycle or an external processol" response enable cycle
until an external processor command write cycle for the FPU has been initiated.
External processor iesportse. enable-An external processofresponse enable cycle is performed
when the CPU is ready to accept the result of Some operation from the CPU. The sequence of events is
• The CPU drives cycle-status information on lines CS < 1:0> (CS < 1:0> = 11 for this type of
cycle), asserts the EPS signal, and puts the CS2line in the high-impedance state. 'fP.e WR signal is
not asserted because this is not a write cycle.
.
.
.
• When die FPU completes its current instruction, it drives status information on the DAL bus and
pulls line CS21ow.
• The CPU reads the information and deasserts the 'Ei5'S ~ignal to end the cycle.
CPU/FPU. General Protocol
The communicap,on protocol between the CPU and the FPU is grouped into five categoriescommand transfer, operand transfer, operand processing, status transfer, and result transfer. The
following paragraphs describe each transfer. .
. .
Command transfer-The CPU initiates an interaction with the FPU by performing an external
processor command write cycle. The CPU drives a command (an instruction opcode) on the DAL·
bus, drives a status code on lines CS < 1:0> , and asserts the BPS andWR signals.
Although the DAL<.31:00> bus is driven with a command (in this case an instruction opcode)
during the external processor command write cyde, only DAL< 08:00:> is significant to the FPU.
Figure j shows the FPU command format and able 4 describes the bit functions.
31
..
.
...
..
0908
.
00
I::::: ::::::::: :: ::::: :I: : ?++, ;: I
Figure 5· MicroVAX 78132. Command Format
1-68
Confidential and Proprietary
-
Preliminary . . . . . . .
DALLine
Description
<31:09>
Not used
<08:00>
ContahJs theopcode of the in~trilction that the FPU is tbexecute. or assist in
executing.
Fro
Operand transfer-The instru~ion opcode specUiesthe operat~on(s) to he~rtor~ by the
and the number and data type of operands inVolved. The CPU f~tch:es thfreqUired opera:nd(sf~nd'
transfers them to the FPU by performing one'&t'nl0re external processor d~tawrite cycles. Dudnt,
these cycles, lines CS < 1:0>. = 01 and the nAt <31:00 > DUS ccintaihs. th~tNnsfer:re(t ~ata~
The opcode of the mstruclwft t~ be executed determines the number and dlltitype of the operands
transferred from the CPU to ineFPU . The followmgroles apply to the transfer of operanQs from the
CPU to the FPU:
.
• Integer operand-An in~r operand is ~~f!lTed in one externalpro~sspr data wri~ cycI~.if
the integer is a byte,it apPe~son DAL<67:~6> with leading zeroes 01ll)AL<31:P8>. lIthe
integer is a word, it appe~on DAL < 15 :o(». ~th leading ze):Oeson D.t\t .~.'
."
• Floating-point operands~;An FJloating operand is transferred in one ~ternal pIOi:tessor' dilta
write cycle. A DJldIlting or GJloating o~d is transfefred in' two consecutive exrer.ti¥:ti
processor data write cycles; bits < 31:00> are transferred during thefitst cycle: and bits
.
< 63:32 > during the second.
• Multiple operands-Ihoperations requiringt«ro operands, the secondotierand is transfer~
first. In operations ~UiriDg three or more ()l'¢rilnds, the order of operand ttansfer iSderermiried
by the instructionbblng~ted.
•'..
',t
'f_''".',·','",_
-
"
• POLY instruction-Exe<:utio~ of the POLYinstruetioninvolvesan ind~terminate ,number,!;>£
operands and results. DuriJlg a POLY imtruoti~n, the FPU need. 'Only receive a coe£#cient;;to'
calculate the next im;~ediate result. The FE>pcoptinuesto acceptcoeffi¢i(mts and return result:;,,·
until the CPU sendstheFPU another command..
Table 5 summarizes ~ order in which ope~and results are
The ~ble uses the
fonoWipg
conventions:
recognized by the Fi>U.
' . . -' , < ' ,
:'
-."
'., ,,.
transfe~red for allh1structi.ons
' .\ '
.
'..
• An "x" in a mnemonic·indkates thattheFBl;lprocesses the two-operand and tliree-operand
versions of the insttiiction.inexactly the same way
• The "#" nID!t to SOll11? of the operands and reSults of a POLY instruction indicates that .the
number of these operands and results depends on the size of the coefficient table.
• A result may bewundedIR],truncated [Ttpf~act[EJ.·
The MicroVAX FPU User's Guide
prov~de~.cotnpl~ede$Criptio~~fth~ opera~
instructiom .
."'__
.....,....
"'_"'_"""_'_%lIfiJ''''_'''''~'''_JiA4d'''''~'''='''''''
__
~_'_-'-_-~--.--~
.....____________,____________"_,.___ _
of these
-
Preliminaty
Table J- MicroVAX78132 OpetandTtans£er .
VAX
FPU
Flt'St
Second Thircl
Mnemonic Opcoc:Ie 1iansfer '&ansfer Transfer Operation
ACBD
ACBF
ACBG
06F
04F
14F
limit.d add.d
limit.f add.f
limit.g add.g
add1+add2
add1+add2
add1+add2
CMPD
CMPF
CMPG
071
051
151
src2.d
sre2.f
src2.g
src1-src2
srel,src2
srel-src2
CVTBD
CVTBF
CVTBG
CVTDB
CVTDF
CVTDL
CVTDW
CVTFB
CVTFD
CVTFG
CVTFL
CVTFW
CVTGB
CVTGF
CVTGL
CVTGW
CVTLD
CvrLF
CVTLG
CVTWD
CVTWF
CVTWG
CVTRDL
CVTRFL
CVTRGL
DIVDx
DIVFx
DIVGx
EMODD
EMODF
EMODG
O6C
04C
14C
068
076
O6A
069
048
056
199
04A
049
148
133
14A
149
06E
04E
14E
06D
04D
14D
06B
04B
14B
sre.b
sre.b
sre.b
sre.d
sre.d
sre.d
sre.d
sre.£
sre.f
sre.£
sre.£
sre.£
sre.g
src.g
src.g
sre.g
sre.l
src.l
sre.!
sre.w
sre.w
src.w
sre.d
src.f
sre.g
sre1.d
srel.f
srcl.g
066, 067 divd.d divr.d
046,047 divd.f divr.f
146, 147 divd.g divr.g
074
054
154
muirx.b muir.d
muirx.b muir.f
muirx. w muir.g
Result 1
Result 2
index.d (index + add}:limit (index.d[R])
index.f (index + add):limit (index.f[R])
index.g (index + add):limit (index.g[R])
ADDDx 060,061 add2.d addl.d
ADDFx 040,041 add2.f addLf
ADDGx 140,141 add2.g add1.g
1-70
MicroVAX78152
sum.d[R]
sum.£[R]
sum.g[R]
£It cvrt
fItcvrt
fIt cvrt
intcvrt
fIt chatige
intcvrt
intcvrt
intcvrt
£I.t change
£It change
intcvrt
intcvrt
int cvrt
fltchange
int cvrt
intcvrt
flt cvrt
£Itcvrt
flt cvrt
flt cvrt
flt cvrt
fIt cvrt
midint cvrt
midint cvrt
midint cvrt
d...Jloat[E]
Lfloat[EJ
8-fIoat[E]
byte[T]
Lfloat[R]
longword[T]
word[T]
byte[T]
cLfloat[El
cLfloat[E]
longword[T]
word[T]
byte[T]
Lfloat[R]
10ngword[T]
word[T]
cL£loat[EJ
Lfloat[R]
8-fIoat[E]
cLfloat[E]
Lfloat[E]
8-float [E]
10ngword[R]
longword[R]
longword[R]
divd/divr
divd/divr
divd/divr
quo.d[R]
quo.f[R]
quo.g[R]
muld.d muir*(muir'muirx) int.l
muld.f muir*(muir'muirx) int.1
muld.g muir*(muir'muirx) int.!
Confidential and Proprietary
fract.d[R]
fract.f[R]
fract.g(R]
-
Preliminary
nw
VAX
FPU
Fast
Second
Mnemonic Opcode Transfer'liansfer 'Ihmsfer Operation
MULDx
MULGx
064, 065 muk.d muld.d
044, 045 muir.f muld.f
144,145 muir.g muld.g
POIYD
POLYF
POLYG
075
055
155
SUBDx
SUBFx
062, 063 min.d
042,043 min.f
142, 143 min.g
MULFx
SUBGx
arg.d
arg.£
arg.g
intl.d
intl.f
int1.g
prod·8[1~J
#coeff.d
(iI1'g*intl) +coeif
~~£f.f{atg*int1) + coeff
#int2.dQtJ
Hint2.f[R]
IIcoeff:i:(arg*mtl) -f;co~ff #int2.g{Rl
sub.d
sub.f
sub.g
muir.ri muld.ri --
min-suh
min-sub
diff.dQl.l
i'IliiHuh
diftg[R]
,mWt~mul4;
07A
OOA
DlVLx
EDIV
OC6, OC7 divr.rl
divd.rq--
divd/divr
07B
divd.rq-
divd/divr
size~ri
OC4, OC5 rnuiNl muld.ri --:.
divr.rl
prod.cl[R]
prod.fER]
muir*muld
muir*muld
rnuil:*muId
EMUL
INDEX
MULLx
(muir·ti)
Result 1
tnuir*size
mUir*mUld
lint 3.d[R] ...
#int3.f[R] 1."
#int3,g[R] ...
dif£,£[R]
.•
pmd.wqfE]
m~u~.wq[E] --
prod:\\iq[El
rem.w(E]
rem.w(E]
Note: The integer divide instructions require that th~ldWer 32:tn1:s of the dividend be transferred
first, and then the upper 32-bits.
Operand ptOC:e88ing-After the CPU ttatlSfel'$1)he Itst()perand, iteontinuously performs external
processor response enable cycleS and wrutsfOf a responsefroffithe FPu. For each of these cycles,
the CPU asserts the appropriate status code on lines CS< 1:0> (CS< 1:0> ... 11) and asserts the
EPS signal.
.
... .
..•
FPU operand processing is completdyinyisib~ ~. the ~PU iUld may no~~. alt~d h}I.t;he user.
Status transfer-When the FPTt1 is ready to pass.;a result to theOPU; it respondstri the nextextci:nal
processor response enable cycle by asserting theC82Signal.imCl $imultaneouslydrivingstatUs
information onto the DAL,.bus.TheCPU teSpondstoi~iasset1;i~flof theCS2~by.per£or~
one additional externalprocessQl' response enable~cle>iduring,Which the CPU rei.\dstheFPU status
information again.
The format of the status informMion is shOlNn,in.Figure6 and defined inlable 6. When the flPU
asserts the CS2signal, it places n bits of s~tus ()nto,~I'-~:L<31:00> bus. The CPU examines
bits <05:00>.
'
.
.
Figure 6· MicroVAX 7.81)2 StatusForrnat
1-71
Tabie 6- MicroVAX 781.32 Status Qes¢ption
DALLine
31:06
Not used
05
FN (Functlon negative)-Indicates the status asJollows:
FN = 1 if result LSS is 0
FN =0 if LSSnot 0
04
FZ (Functionzero)-Indicates the status as follows:
FZ= 1 if the result EQL is 0
FZ =0 if restilt EQL is not 0
03
BR (Branch)-Indicates the status as follows:
BR..,1 if ABCx should branch
BR ... 0 if ABCx should not branch
02:00
EXC CODE (Exception code}-Indicates that the following events have occurred:
Code
Description
1
2
3
4
5
6
reserved
floating divide by zero
integer overflow
floating overflow
floating underflow
reserved operand detected
operation completed normally
o
If the EXC CODE is not 7 after a floating-to-integer conversion instruction, the condition codes
associated with the instruction are unpredictable and must be determined by the CPU. Integer
multiply and divide instructions always return unpredictable condition codes (that is, in the FN,
FZ, and BR fields) and set the EXC CODE field to 7.
Result ttansfe:r-The CPU performs one or more external processor data read cycles to read a result
from the FPU. During one of.these cycles, lines CS =01 and the DAL<31:00> bus
contains the read data. After the result transfer, the CPU and FPU are free for the 'next transaction.
The following rules apply to result transfers from the FPU to the CPU:
in
• Integer results-An integer result is transferred one external processor data read cyCle. If the
integer is a byte, it appears on DAL<07:00> with unpredictable data on DAL< 31:08>. If the
integer is a word, it appears on DAL < 15:00> with unpredictable data on DAL < 31:16 >. For
integer multiplication, two 32-bit transfers are necessary to return the entire result.
• Floating-point results-An F.J1oating operand is transferred in orieexternal processor data read
cycle. A D..Jloating or G_floating opemnd is transferred in two co.nsecutive external processor
data read cycles; bits < 31:00 > are transferred during the first cycle; and bits < 63:32 >, during
the second cycle.
'
• Overflow and underflow-In integer overflow cases, the FPU always returns the low-order bits of
the true integer result; in floating underflow cases, the FPU always returns a zero result.
• CMPx instruction results-CMPD, CMPF, and CMPG do not cause a result to be generated by the
FPU, but the CPU will request one. The FPU returns a meaningless result that the CPU ignores.
1·72
Confidential and Proprietary
-
Typical FPU/CPU Interconnec:tion
Figure 7 illustrates atypical FPU/CPU hardware configuration. lathe example, a DALt:ransceiver
and latch is included in the design for the benefit of theextemallogic that con1municates with the
FPU/CPU via the DAL. Also included for completeness are several MicroVAX 78032 CPU control
signals that must be interpreted or generated by external logic. Refer to the "MicroVAX 78032
CPU" section for information on these control signals.
eLKI
vee
~
. - - - - - GND, VIlS
AS
~~~----------r---------.As
iNTfiM
5MR
OMG
BM
os
i>WiiFi:
iiALi'
ERFi
......--v~e
FiDY
....--GND,VS8
REsET
Figure '7. MicroVAX 78132 Typical F~tlIMicfoVAX78032
CPU Interconnection
,
"
'
. Specifications
The mechanical, electrical, and environmentalcliaracteristics and specificatiotlsior the MicroVAX
78132 are described in the following paragraphs. The test conditions for theelectrf<;dvalues are as
followsuruess specified otherWise.
. ....
.
• Ground reference (Vss)
• Supply voltage (Vcc): 4.75 V
Mechankal Configuration
The physical dimensions of the MicroVAX 78132 68-pin CERQUAD package are contained in
AppendixE.
Confidential and Proprietary
1-73
...
Preliminary
MicroVAX'7SU2
Absolute Maximum Ratings
Stresses greater than the absolute maximlll,Q ratings may cause permanent' damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
• Supply voltage (Vee): -':0.5 V to 7.0 V
• Input or output voltage applied: -1.0 V to 10 V
• Storage temperature range: -55°C to 125°C
• Power dissipation: 3 watts (maximum)
Recommended Operating Conditions
• Supply voltage: 4.75 V to 5.25 V
• Active supply current (led: 240 rnA (maximum)
• Temperature range: O°C to 70°C
• Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics
The de electrical specifications of the MlcroVAX 78132 FPU for the operating voltage and
temperature ranges specified are listed in Table 7.
Table 7 • MicroVAX 78132 de Input and Output Parameters
Symbol
Parameter
Requirements
Min.
Max.
Units
Vm
High-level
input voltage
2.0
V
Vn,
Low-lever
input voltage
Vllm
High-level
input EPS signal
VILE
Low-level
input EPS signal
VOH
High-level
output voltage
VOL
Low-level
output voltage
VOLS
Low-level
output voltage CS2
1-74
0.8
Test Conditions
V
V
2.2
0.6
V
= -400 I1A
V
IOH
0.4
V
IoL=2.0rnA .
0.4
V
I oL =5.2 rnA
2.4
Confidential and Proprietary
-
Symbol·
In.
MicroVAXlIm.
Pre~
Pannnetet
Requirements
Min.
Max.
Uqits
Test
CS2
IJITIII//IJ I
-,,----,0
=:rcJ
T4
I\\W
x==
~tEPCSL~
T2
T!
T1
T4
13
teEP tEPLC
CLKO
50
) I
OAl<31:00>
EPS
DATA
)-
I~ ..,.:.~~:,~~
---I"---j~L
F
twREP
WR
(
... d--1
tEPLWO (MAX)
\\\\\\\\\\\
I
In.
tEPWA
V7l7lZ
I
CS<1:0>
Wri1a1Command Write Cycle
.Figure 9 • MicroVAX 781j2 Extemal Processor Data TransacHon, Timing
1-76
Confidential and Proprietary
-
MicroVAX 78132
Table 9· MicroVAX78132 External Processor nata Transaction Tuning Parameters
SymboJ Definition
Requirements (ns)
Min.
Max.
P + 19
teEP
CLKO falling through 0.8 V to EPS falling through 2.2 V
P+1
tOOEPH
Write data valid setup time to EPS deassertion
2P- 35
t EPCSL
EPS assertion to external processor assertion of CS < 2 >
0
3P-40
t EPCSZ
EPS deassertion to CS < 2 > three-stated by external processor
0
2P-20
t EPDI
EPS assertion to read data valid
4P-40
t EPHDO
Write data hold time from EPS deassertion
2P-25
tEPLC
EPS falling through 0.6 V to CLKO rising through 2.0 V
P-25
tEPLWI
EPS assertion width (read)
4P-20
4P
t EPLWO
EPS assertion width (write)
5P- 20
5P + 20
tEPWB.
WR and CS < 1:0> hold time from EPS deassertion
P- 20
tEPZ
EPS deassertion to read data three-state
3P-20
tWREP
WR and CS< 1:0> set up time before EPS assertion
2P- 35
+ 20
1-77
Confidential and Proprietary
,.
• Features
• Fully compatibile"with the MicroVAX 78032 CPU, CVAX 78034 CPU and rtVAX 78R32 CPU
• 16 Peripheral Interrupt Request (PIRQ) lines
• Edge or level triggering for each PIRQ line with individually selected priorities
• 16 Programmable vector addresses
• ,Optional external vector generation
• Fixed or round robin priority modes
• Uses a daisychain interrupt-enable scheme for cascading
• High-sp~d,low-power CMOS technology
• Single 5-Vdc power supply
• Description
The MicroVAX 78516 Vectored Interrupt Controller (VIC)* is a low-cost, programmable interrupt
controller that is fully compatible with the MicroVAX 78032 CPU, CVAX 78034 CPU, and rtVAX
78R32 CPU. The VIC manages as many as 16 interrupt sources, resolves interrupt priorities, drives
the interrupt request (IRQ) lines of the CPU, and provides a programmable 13-bit interrupt vector
to the CPU. Users can choose either the fixed or round robin interrupt priority mode. Using a
daisychain scheme, the VIC is ~scadable. Figure 1 is a general block diagram of the MicroVAX
78516 VIC.
PlRO.15
OAt<15,OO>
A1l
W1i
6ll
CS<2-:(I>
PifIJ14
I'IRn'3
MicroVAX
INTERFACE
REGISTERS
AND
CONTROl
LOGIC
m5'1
PtRQ112
ARnH
' I'IRntO
PlAOQ9
~
PIAtlO8
~
PlROO7
PlR006
.,0005
eLK _
PlIlOO4
PlROO.
CleCK
GENERATION
AAO RESET
LOGIC
PRIORITY
AND
ARSITRATION
LOGIC ..
illm_
PlROO!
PlROO.
PlROOO
)MC
iACK
IAlCECW
IAKEI
IA input/output Data/address lines < 15:0> -Time-multiplexed
lines used to transfer address, data, and interrupt
information between the VIC and the CPU.
lnput/Output Definition/Func:tion
47
~nput
Address strobe-Latches the state of the VIC
into interrtaltigisters.
41
input
Data Strobe.;;;;...When asserted during a CPU read
"or interrupt acknowledge cycle:, it indicates that
DAL< 15:00.> lines are available to receive data.
When asserted during a CPU write cycle, it
"'latches the.
on' the DAL < 15:00' >.lines into
the internru:registers.
d:ata
40
WR
input
Write-Indicates the direction of data transfer
on the DAL< 15:00> lines.
43,45,46
CS<2:0>
input
Control status-Used to decode the bus cycle
type.
50
RDY
outpUt
.. Ready ....... SyndOOnizes data transfers betWeen the
VIC and theCPU.
28.13
PIRQ< 15:00;> inputs
peppheral i~f;f:J:lUPtrequests <: 15:00>-Used
by peripherall1evi.ces to request an internipt.
51·54
IRQ<3:0>,
output
Intetruptteq'Uest <3:0>-Used to flotify the
CPU of any pending interrupts. These lines are
maskable by tbeCPU.
55
lACK
output
Interrupt ackno~ledge~:mdicat;~S that the
rent bus cycle edge is Ql).interrupt acknowledge
cycle.
.
6t
)wEC
output
External veetor__ Indicates that the interrupt
request is being acknowledged and the peripheral
device mus.ts.upply a vector.to the CPU.
42
IA.KEI
input
,
'l{ ,
"
"
,
air·
Interrupt . acknowledge enable in....:...Daisychain
control signal that indicates the V1C Can reSpond
to the curreht interrupt acknOWledge CYcle,
56
IAKEOP
output
Interrupt.aCknowledge e,ru,tble out P-Anacdve
high puIlup output .that connects together with
the with the IA1{EON output to the iAK'EI input
of the next device in tht:: daisychain.
.
Confidential and· Proprietary
1·81
-
Pin
Preliminary
Signal
Input/Output,
MicroVAX7SSt6
.
"PefinitionLF
..... , unction
57
IAKEON
output
Interrupt acknowledge enable out N-An active
low pulldown output that connects together with
the IAKEOP output to the lAKEI input of the
next device in the daisychain or connects to the
ERR input of the CPU.
39
CSEL
input
Chip select-Enables read/write operations to
,the internal registers.
31
RESET
input
Reset-Sets the VIC to a known initial state.
30
CLK
input
Clock-Used to generate the internal time states
of the VIC.
10,11,29,44,60 Voo
input
Voltage-Power supply voltage.
U,32,48,58,59 Vss
input
Ground-Ground reference
MicroVAX Bus Interface Signals
lines (DAL < 1.5 :00 > )-These lines are bidirectional and are· used to transfer
address and data between the VIC and the CPU. During internal VIC register access cycles, when
the CSEL line is asserted, the DAL < 15 :00> lines transfer data to and from the internal registers.
During interrupt acknowledge cycles, if the IAKEI input is asserted and the VIC has a pending
interrupt at the level being acknowledged, the VIC places one of its interrupt vector registers on the
DAL < 15:00> lines or assert the external vector control signal (XVEC). When the XVEC signal is
asserted, the interrupting device must then supply a vector. During interrupt acknowledge cycles,
the DAL < 15 :00> lines are driven only when the IAKEI input is asserted, the IAKEON output is
deasserted, and the XVE bit in the interrupt vector register is cleared. The DAL < 15:00> lines are
otherwise in a high-impedance state.
Data!Address
Address strobe (AS)-When asserted, this signal latches the information on the DAL < 06:00 > ,
CS < 2:0 >, and the WR lines into the VIC. This information is used internally to latch the
PIRQ < 15 :00> line information for the duration of a read or interrupt acknowledge bus cycle that
accesses the VIC.
Data strobe (DS)- This signal is used by the VIC for data timing during internal register access
cycles and interrupt acknowledge cycles. When writing to one of the internal registers, the
assertiono£ this signal strobes the DAL < 15: 00 > line data into the selected register. When reading
an internal register, the assertion of this signal is used to transfer the contents of the selected
register onto the DAL< 15:00> lines. When responding to an interrupt acknowledge cycle, the
assertion of this signal is used to transfer the contents of the appropriate interrupt vector register
ontotheDAL<15:00> lines.
Write (WR)- This signal indicates whether the current bus cycle is a read or a write cycle. This
signal is used with the CS < 2:0 > inputs to decode the type of bus cycle in progress and to access
, internal registers to determine whether the operation is a read or write operation. The WR input is
asserted for write cycles and is deasserted for read or interrupt acknowledge bus cycles.
Control status (CS < 2: 0 > )-These lines and the WR input are decoded to determine the presence
of a read, write, or interrupt acknowledge bus cycle. The bus cycle selections are listed in Table 2.
1-82
Confidential and Proprietary
Preliminary
MieroVAX 78'16
1ltbIe 2 • MicrOVAX 18516 Bus Cycle Decoding*
CSEL
Bus Cycle
H
L
Read
H
L
L
Write
H
H
X
I1lterruptaclqxowledge
.CSLine
2
1
o
H
x
x
H
X
L
H
*H=high leveI,L=low level, X=either high or low level.
Ready (Ri)V)-'This signal is asserted by the VIC when its irttel'tlal registers are accessed during a
read or write cycle or during an interrupNlcknowledge (IACK)Cy'dewhenthe VIC is providing an
interrupt vectol: During IACK cycles, at lelUltone rej\dysllp will t5e generated to aI1ew an interrupt
acknowledge enable signal· (iAKEi, IAKEOp, 'Or IAKEON) to ~tOpagatethrough .the daisYchain.
The total number of ready slips that occur depends on the length of the daisychain. This is an open
drain (pulldown) output capable of sinking 16 mAo
Interrupt Inter:faee Signals
Peripheral interrupt request (PIRQ < 15:00 > )-These input lines are used by peripheral circuits
to request an interrupt .. When one.or ·1llOre of these linesal'e asserted ~nd the interrupts are
enabled, .the VIC will assert the appropriateIlQline(s). Mj!.pping between each PIRQIine and the
IRQ line is programmable by softwarethaughthe IRQ Map registers. The interrupt request .can, be
sensed by a signal level or edge or by the signal polarity. The sensing is programmable by the user.
Unused PIRQ lines must. be connected to a valid logic level.
Interrupt request (IRQ < 3:0> )-One or more of these lines will. be asserted by the.VIC when a
PIRQ line is asserted and the interrupts are enabled. The IRQ Map registers determine which IRQ
line is asserted for a particular PIRQ line. An IRQ line will bedeassert¢d when all pending
interrupts mapped to that IRQ line have been serviced. These)~u'¢open drain (pulldown} outputs
that require external pullup resistors.
Interrupt acknowledge (iAC'K)-This signal is a result of decoding the CS<2:0> and the WR
lines and will be asserted for all interrupt acknowledge cycles. The signal isnotaffect:ed by the
interrupt acknowledge daisYc:hain $ignaIs. It allows the ~ternal)ogic to disable the memory
transceivers during an interrupt acknowledge cycle.
..
External vector enable li$es in the high.imped~, state. The hardware supplying the
vector is required to assert the RDY signal at the correct time.
Daisydtain Interface Signals
Interrupt acknowledge enable in (IAKEI)-This input allows more than one VIC and other
peripheral chips to be connected together in a daisychain. When this input is asserted, the VIC can
respond to the current interrupt acknowledge bus cycle. This signal should be connected to a
ground reference if the VIC is the highest priority device in the daisychain.
Confidential and Proprietary
1·83
-
MicroVAX1s'16
Interrupt ackl'lOwledge enable >QUt lUgh (L\KEOP)- This Qutput and the IAKEON eutput are
cennected to the IAKEI pin of the next lowest device in the interrupt daisychain. The IAKEOP
output is normally an active high pullup. However, when the IAKEI signal is asserted and the VIC
has no. pending interrupts at the level being acknewledged, the IAKEOP eutput is a highimpedance. If the VIC is the lowest-priority device in the daisychain, this line is not cennected to
another device. This is an open drain, pullup output that cannot be pulled low. For daisychain
operation, the pulldown function is performed by the lAKE ON line.
Interrupt ackl'lowledge enable out low/error low (IAKEON)-This is an open drain pulldown
output that is used to either pull down the next IAKEI level in a daisychain application, or pull
down the ERR input to the CPU if this VIC is the last (or enly) device in the daisychain. The
IAKEON line is normally in a high-impedance state. However, when the IAKEI signal is asserted
and the VIC has no. pending interrupts at the level being acknowledged, theIAKEON signal is
asserted. The VIC asserts this signal if PIRQ line is in level mode and the interrupting device
removes its request before the interrupt is acknowledged. The level sensitive inputs are not stored
bithe VIC. Therefore, the PIRQ line that was asserted cannot be used to determine the Vector to
return to the CPU. This output is a high current open drain output.
Miscellaneous Signals
Chip select (CSEL)-This signal, when asserted, enables read/write operations to. the internal
registers.
Reset (RESET)~This signal,' when asserted, sets all the internal registers to a known value except
fer the interrupt vector (IVEe) and IRQ map (IMAP) registers. The contents of the IVEe and lMAP
registers are unknown. The interrupts are disabled and the DAL<15:00> lines become a high
impedance.
Clock (CLK)-This signal is used to gene'rate the internal time states within the VIC. Any escillator
that meets the input requirements of CLK signal may be used.
Power and GroundCOhnections
Power supply voltage (VDD)-Power supply 5 Vdc.
Ground (Vss)-Ground reference .
• Functional De$Crl.ption
The VIC may be connected directly to the CPU bus or to. a buffered I/O bus. It accepts up to 16
priority interrupt requests (PIRQ < 15:00» from peripheral devices and it drives an associated
IRQ line to the CPU. The mapping between the VIC PIRQ lines and CPU IRQ lines is
programmable. The VIC decodes the presence of a CPU interrupt acknowledge (lACK) cycle on the
bus and monitors the interrupt prierity level of the interrupt being acknowledged. It will respond
to. the IACK cycle by transferring the appropriate user programmed vector on lines DAL < 15 :00 > .
The CPU uses the vector as an effset into. the system centrol bleck (SCB) to. lecate the starting
address of the interrupt routine.
A daisychain wiring scheme enables the user to connect more than one VIC tegether so. as to
expand the int~rrUpt handling capability from that of a single VIC. This scheme is compatible with
the daisychain scheme used bY' the other peripheral interfaces.
A peripheral device requests service by asserting one of the PIRQ lines. When the VIC detects the
PIRQ line that has been enabled, it reflects the assertien of the line in the pending summary
register (PSR) bit that corresponds to that PIRQ line. The IRQ output, programmed by the user for
that PIRQ, will also be asserted to indicate to the CPU the interrupt condition at the specified IPL
1-&4
Confidential and Proprietary
Preliminary
level. The CPU will respond with an interrupt acknowledge cycle that contains the priority levd of
the interrupt beingackoowledged; The VIC then decodes the lACK cycle and IPL line information
and ifthe VIC ~eneratedthe interrupt and the lAKEl (daisychain input) signal is asserted, it selects
the vector of the nextPIRQ to be serviced for that IPL level. It then places that vector on the
DAL< 15:00> lines. If the VIC did not request the interrupt, it asserts the IAKEON (daisychain
output) signal to allow the next devices in the daisy chain to be serviced. When the VIC is
responding to an interrupt, it holds the. fAKEON line from be~I1& asserted to prevent devices in the
daisychain that have a lower priority from responding,
Registers
The VIC contains 16 interrupt vector registers andBcinterrupt control registers that allow each
request to be individually configured by software,' The internalVIC registers, shown in Figure 3,
are accessible by the CPU and are used by software to cOIlfigutethe operation of the VIC. Each
register consists of 16-bits and is located on a longword boundary. The base address is determined
by external address decode logic. Direct access to the VIC registers is enabled when the CSEL signal
is asserted and the VIC decodes the address on the DAL < 06:09> lines to select the register to be
accessed.
.
.
NOI'E: Only word access to the lower 16-bits of thelongwordare allowed to transfer data between
the CPU and the VIC. Byte accesses and longword accesses are not allowed. Longword
access may result in the CPU reading the incorrect data or lost data during a write cycle.
ADDRESS
BASE
BASE+4
15
OD
...
POLARITY REGISTER'
, LEVEL/EDGE REGIST£R
BASE+8
PENDtNGSl,JM~ARX REGISTER
BASE+12
INTERRUPT ENASL.E REGISTER
BAS~+16
IRQ. MAP REGisTER .0 .
BASE+20
I IRQ MAP REGISTER 1
BASE +24
IRQ MAP REGISTER 2
BASE+28
BASE +32
BASE+36
IRQ MAP REGISTER 3
•.. 'ROUND ROBlfIH'I.EGISTJ;R
"
.,' ADDRESSES
tBASE+361
:.;,
• '. TQ(BAiSIl~ARe
",NOT INTEflN!'\I..L V
• 'OeCOOE1:>!'V'tHE VIC
•
BASE+64
BASE-+6B
8ASE+124
INTERRUPT VECTOR REGISTER 0
··
INTERRUPT VECTOR R.EG.ISTER 15
Figure 3· MicroVAX 78516 Register Address and Descriptions
Confidential and Proprietary
~ .......
-
....
- ..-.---.-.--...
1·85
------------------,-----.--,~-------------.
-
Preliminary. ,
MicroVAX78516
Polarity register-The polarity (POL) register selects. the polarity of the input used to assert a
PIRQ < 15:00 > line. When a bit is set, the corresponding line is asserted by a low-to-high
transition or by a high leveL When a bitis clear, the corresponding line is asserted by a high-to-Iow
transition or by a low level. The register format is shown in Figure 4.
15
.1
00
:
T
PIRO< 15;OO>lEVEL/EDGE POLARITY
Figure 4· MicroVAX 78516 Polarity Register Format
The POL register is used with the level/edge (LE) register to configure each PIRQ input. A PIRQ
input may be configured to respond to a rising edge, a falling edge, a high level, or a low level signal.
Table 3 shows the bit selections of the POL and LE registers and the resulting state of a PIRQ line.
When the RESET line is asserted, the POL register is cleared.
Table 3 • MicroVAX 78516 PIRQ Input Line Configurations
POL Bit
LE Bit
PIRQ Asserted State
o
0
Falling edge
1
0
Rising edge
o
1
Low level
1
1
Highlevd
LeveJ{Edge register-The level/edge (LE) register is used to select the way in which a PIRQ
< 15 :00> line detects an interrupt request. It allows the user to select either level or edge sensitive
triggering. When a bit is set, the corresponding PIRQ line is level sensitive. When a bit is clear, the
corresponding PIRQ line is edge sensitive. The polarity of the PIRQ line input is selected by the
polarity register (POL). Figure 5 shows the register format.
00
15
T
PlRQ< 1 5;00> LEVEL/EDGE TRIGGER
Figure 5 • MicroVAX 78516 Level/Edge Register Fomtat
1·86
Confidential and Proprietary
MicroVAX 18S16
Level-sensitive inputs allow more than one device to be connected to a single PIRQ line by using a
wired NOR structure. Once the correct polarity level is detected by the VIC, the corresponding
interrupt pending bit is setin the pending summary register (PSR). The interrupt pending bit will
remain set until the PIRQ line is cleared. Therefore, an interrupt acknowledge cycle from the CPU
will not clear the interrupt pending bit in the PSR register until the PIRQ line is deasserted. If a
wired NOR structure is used, a external pullup resistors is required pn the PIRQ line.
Edge sensitive inputs detect either a high-to-Iow (falling edge) or low-to-high (rising edge)
transition. When the correct transition is detected, the corresponding bit in the PSR register will be
set .. The VIC will clear the bit when the interrupt is seryicedllPd will not recognize another
interrupt request onthis line un~ the proper tqmsition occurs. When the IrnSm'line is asserted,
.
the LE register is cleared.
PendingSuounary registef-'The pending summary regis:ter (f$R) pro¢'des a s,ummary of the
internal interrupt pending flags. When a bit is set, an interrupt request is pending for the
corresponding PIRQ line. When a bit is clear, Po interrupt is pending. for t/:1e corre~pol1di.r:%PlRQ
line. The contents of the PSR register are latcp.ed during a read andIACK cycle. The regi.~ter format
is shown in Figure 6.
. .
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
.
PlRQ< 15:00> INTERRUPT PENDING
Figure 6· MicroVAX 78518 Pending Summary Register Format
The VIC manages the setting and clearing the PSR register bits for level and edge sensitive PIRQ
inputs as follows. When the RESET input is asserted, the PSR register is cleared .
• For level sensitive PlRQ inputs, thecdrresponding .PSR bit will be set· when the PIRQ line is
asserted and cleared when line is deasserted .
• For edge sensitive PlRQ inputs, the corresponding PSR bit is set on the asserting edge of thePtRQ
input. The PSR bit for a PIRQ input will be cleared by an 1nterrupt.acknowledge cycle that
acknowledges the interrupt request of the corresponding PIRQline, when .the software clears the
PSR bit by writing a zero into the appropriate bit, or when in£ormatioriis written into the LE
register.
Interrupt Enable register-The interrupt enable (lEN) register is used to enable or disable the
reporting of interrupts to the CPU by each PIRQ line. When a bit is set, it allows an interrupt
request from the associated PIRQ line to generate an interrupt to the CPU. When a bitis clear, the
associated PIRQ line is prevented from generating an interrupt to the CPU, The register format is
shown in Figure 7..
Confidential and Proprietary
1-87
MicroVAX7Sji6
Preliminary
15
14
13
12
:
11
:
10
:
09
08
07
06
05
04
03
02
01
.00
i.
I·
y
PIRO< 15:00>INTERRUPT ENABLE/DISABLE
Figure 7· MicroVAX 78516 Interrupt Enable Register Format
The lEN register enables or disables the generating of an interrupt to the CPU and does not affect
the detection of interrupts by the VIC. When a PIRQ line is asserted, the corresponding bit in the
PSR register is set regardless of the state of the lEN bit for the PJRQ line. ThelEN register provides
the support for i1 software interrupt polling scheme. The register is cleared when the RESET input
is asserted.
IRQ Map registers (0-3)-The interrupt request map registers (IMAPO through lMAP3) are used to
select the IRQ line to be asserted by the VIC when aPIRQ line is asserted. When a bit in one of the
IMAP registers is set, the corresponding PIRQ line is mapped to the associated IRQ line. The
register format is shown in Figure 8. Each register corresponds to one of the IRQ outputs as defined
in Table 4.
15
14
13
12
I:
11
10
: :
09
08
07
06
05
04
:
03
:
02
01
00
yo
PIRO< 15:00> TO MicroVAX IRO LINE
Figure 8· MicroVAX 78516 IRQ Map Registers (0-3) Format
Table 4 • MicroVAX 78516 !MAP Register to IRQ Mapping
Register
Line
lMAP3
IRQ3
IMAP2
IRQ2
lMAPl
IRQ1
IMAPO
IRQO
Example: If bit 3 of the IMAPlregister is set when the PIRQ31ine is asserted and the lEN register
bit is set for tIlls line, line IRQ1 will be asserted.
The lMAP registers are not initialized when the RESET line is asserted and the contents will be
undefined until programmed by software.
1-88
Confidential and Proprietary
-
MicroVAX'l8116
Round Robin~The round robin (ROBIN) register is used to select either fixed or round
robin priority mode otoperation for each IRQ level. More than one bit maybe set in this register at
a time and the register controls only the PIRQ lines for the asscociated VIC . 'The register is cleared
when the WET input is asserted .. The register for.JDat is shown in Figure 9 . Table 5 describes the
function of each bit.
15
:
..
RAl
:I:
04
':
: :
;
00
03
.
~
'H
t
RR17-RRI4
Figure 9 • MicroVAX 78516 Round Robin R:eJjSfer Format
'DIble 5 • MicroVAX 78516 Round Robin Register Description
Bit
Description
15:04
RAZ (Read as zeros)-Not used
03:00
RR17-RR14 (ROUND ROBIN IPL17-IPL14)-....c1'heSe~sele£tthepriority mbdefor.al1
interrupts mapped to lines IRQ<3:0>. RR17 selects IRQ3 etc, When set,rhe mund
robin mode is selected. When cleared,' the fixed mode·isselected,
Interrupt Vector registers. (O-15)-Eacho£ the 16 interrupt vector (WECO through IV'EC15)
registers contains a fully programmable 16;bit vector. There isan IVEe~giSter£or eachPIRQ line.
The register format is shown in Figurte 10 and Table 6 describes die fdrtdion of each bit.
~
15
!
.
~
• 1
::
'
.
:
'
,
: :
PIRQ INTERRUPT
VECTOR
'"
'
•
02
01
00
; ; : !I I I
XVE
I
OFLG
Figure 10 • MicroVAX. 78516 Intlm'UPt. Vector, Rcgistet;s (0-15) Format
1-89
_-----------
_._---_._._. _---_._--------,_..._-_._-_..._------_._..
MicroVAX78j1.~
Table 6· MicroVAX 78S16lt:de1'tUpt V~tOrRegiMs(O.1S)Descripti()n .
Bh
~prion
15:02
VECTOR (PIRQ interrupt vector}-This vector is the offset into the system
control block (SCB) for the location of the interrupt routine.
01
XVE (External vector enable)-When set, the DAL< 15:00> line drivers are
disabled and the XVEC line is asserted during an lACK t)'de, indicating that an
external vector is to be supplied. When clear, the VIC will drive the contents of
the IVEC register onto the DAL< 15:00> lines during an lACK cycle.
00
QFLG (Normal/Q-bus processing flag)-When set, this bit forces the interrupt
priority line of the CPP to priority IPL17 when servicing the interrupt. When
clear, the CPU will service the interrupt normally.
These registers are not initialized when the RESET input is asserted and the contents of the register
is undefined until programmed by software.
Interrupt Level 1iiggering and Edge Triggering
The sensing of an interrupt condition by the VIC may be programmed for each PIRQ input by the
LE register. Each PIRQ line can be set to respond to either a signal level or to a signal transition
(edge). The polarity of the sensed condition is also programmable.
In the edge-triggered mode, either a high-to-Iow or low-to-high transition on the PIRQ line will
cause the VIC to latch the PIRQ line information. Further transitions on this PIRQ line will have no
effect. After the acknowledgment of the latched assertion by the CPU, the VIC resets the latching
mechanism allowing the ti!ler to again assert the interrupt with a proper transition on the PIRQ line.
A latched PIRQ assertion may be cleared by writing to the LE register or by writing a zero to the
corresponding bit of the pending status register.
In the level mode, the interrupting device must deassert the PIRQ input before the interrupt
service routine ends to prevent the VIC from sensing the previous level and posting the same
interrupt twice. During edge- or level-triggering, a bit in the pending summary register corresponding to that PIRQ line indicates the pending interrupt and if the interrupt is enabled, the VIC will
assert the appropriate IRQ line as programmed in the IMAP register.
If the CPU responds to an interrupt caused by a edge-triggered signal, the completion of the lACK
cycle will cause the VIC to clear the corresponding PSR register bit. If level-triggered mode was
selected, the PSR bit would continue to reflect the PIRQ status.
1-90
Confidential and Proprietary
-
MicroVAX1S'16
Fixed and Round Robin Priority
The two priority modes available to the user are fixed and round robin. Each PIRQ line has a fixed
priority with respect to the other PIRQ lines with line PIRQ15 as the highest priority and line
PIRQO as the lowest.
In fixed priority mode, the highest pending PIRQ for the IRQ level being recognized by the CPU
will be serviced first. In round robin mode, the. highest pending PIRQ for the IRQ level being
recognized by the CPU will be serviced and then prevented from requesting another interrupt until
all other pending interrupts for that IRQ level have been serviced. When all pending interrupts
assigned to an IRQ level have been serviced, the VIC will enable all the PIRQ lines assigned to that
IRQ level and the round robin process will start again. The'round robin mode operates only within
the PIRQ lines of a specific VIC,
The VIC accepts as many as 16 interrupts from peripheral devices and drives an interrupt request
(IRQ) line of the CPU, as determined by the user. The VIC decodes the presence of an interrupt
acknowledge cycle on the bus, monitors the interrupt priority line (IPL) being recognized, and
sends a 13-bit vector to the CPU. Each of the 16 (IRQ) lines i~ configured by software as follows:
• triggering mode and polarity
• IRQ mapping to the CPU
• enabling/disabling of interrupt request
• an interrupt vector
External Vector Generation
External devices can generate their own vector under control of a bit in the IVEC register. The
vector generation sequence is as follows:
1. The VIC provides the external vector enable ~ signal to the external logic that generates
the vector.
;
2. The XVEC signal indicates that the interrupt requested is ge1ng acknowledged.
3. The external logic supplies a vector to the ~ and assert~ an RDYto end the bus cycle.
Daisychain Configuration
More than one VIC can be connected in a daisychain-enable configuration as shown in Figure 11.
The three signals used are the ackrtowWQge enal>le in (i'AKEl), interrupt acknowledge enable out
high (IAKEOP), and interrupt acknowledge enable out low/error low (IAKEON). When the lAKEI
signal is asserted, the VIC can respond to the current interrupt acknowledge cycle. If no pending
interrupts exist for the IPL line being acknowledged, the VIC asserts the iAKEON and !AKBOP
lines to allow the next device in the chain torespohd to the interrupt acknowledge cycle.
Interrupt Operation
The VIC receives interrupt requests £roll1qevices and posts interrupts to the CPU by asserting the
appropriate IRQ lines. It also provides a vector address to the CPU during an interrupt acknowledge
cycle if the XVE bit in the interrupt register is not set. If it is set, the VIC notifies the device that a
vectoraddress is required from the device .•
Posting interrupts-When the VIC detects an assertion on aPIRQ input from a device, it sets a bit
in the in Pending Summary register that corresponds to the PIRQ input, If the corresponding
interrupt enable (lEN) bit in Interrupt Enable register is also set, an IRQ line is set to notify ~he
CPU of the.interPlpt request. The IRQ line that is set is selected by one of the four Interrupt Map
registers. Figure 11 shows the sequence for posting an interrupt req\lest.
Confidential and PlPPrietary
1-91
-
Preliminary' ,
SET BIT
INPSR
NO
ASSERT IRO <3:0>
LINE SELECTED
BYIMAPAEG
Figure 11 • MicroVAX· 78516 Interrupt Request Posting Sequence
Interrupt acknowledge response-After the IRQ line is asserted, The CPU responds with an
interrupt acknowledge cycle that transfers the interrupt priority level (IPL) of the interrupt being
acknowledged on the DAL< 04:00> lines. The VIC decodes this information to determine if it
had requested the interrupt. If it had made the request, an(hhe'IAKEI input is asserted, the VIC
blocks the propagation of the IAKEI signal to another VIC, and sel~cf the vector address associated
with the PIRQ line that requested the interrupt. The VIC then transfers the vector to the CPU
1-92
Confidential and Proprietary
MicroVAX 78516
through the DAL < 15:00 > lines. If an interrupt is not pending at the IPL being acknowledged, the
VIC passes control to the next device in the daisychain by asserting the IAKEON signal and by
placing the IAKBOP line in a high-impedance state. The interrupt acknowledge response sequence
is shown in Figure 12.
NO
DECODE
NO
IPL
ASSERT iAiEON
DEASSERT
IAKEOP
SELECT HIGtfm"
PENDI~
'.
INTeMUPT
fORlPl
YES
PLACEIVEC
REG ON .M!".
ASSERTADY
A
Figure 12 • MicroVAX 78516 Interrnpt Acknowledge Response Sequence
Confidential and Proprietary
1-93
-
MicroVAX'18.516
c
A
NO
NO
BlOCKPIRO
JUST SERVICED
FROM REOU EST
ANOTHER
INTERRUPT
CLEAR PSR BIT
RESET EDGE
DETECTMECH
YES
UNBLOCK
ALL PUlOs
MAPPED TO IPL'
Figure 12· MicroVAX 78516 Interrupt Acknowledge Response Sequence (Continued)
1-94
Confidential and Proprietary
MiaoVAX 71St6
.lQ~~ments
The VIC can beusedmth the MkroVAX78031 CPU, CVAX 78034 CPU, or the rtVAX 78R32 CPU.
It can be. connected to either the CPU bus or to a buf£erred I/O bus. A typical example of the VIC
connecteCl toa MicroVAX 78032 CPU is shown in Figure 13. The circuit includes separate address
decode logic to assert the CSEt input that is used tose1ect regist~rs in the VIC.
PERIPHE~
DEVICE;·
DAl<15:00>
MicroVAX
78032 CPU
.PERlPHI;RAl
DEVICE
PERIPHERAL
DEVICE
D!!
CS<2:O>
WI
~
fAO<3:0>'"
ROY
RESET'"
CLKO
ClK'
~
Rffii'
IAJ(tOp
• ANY CLOCK MEETING PC. SPECIFICATIONS
., SYSTEM-WIDE RESET SIGNAL
••• THESE LINES NEED EXTERNAL PULLUPS.
Figure U • MicroVAX 78516 Typical VIC and MicrovAxi8OJ2 CPU Interface Con/igpration
Daisychain Wiring
Figure 14 is an exampleof ~ 1\4icroVAX 78032.CPUan4 th~ o~VIC and wired in a daisychainenable configuration: The init~'iAKEI input to the VIC is'heldasserted by a ground connection to
allow the VIC to respond to to the current interupt acknowledge cycle. If a pending interrupt does
not exist for the IPL being acknowledged, the VIC asserts the mEON and IAKEOP lines to allow
the next device in the chain to respond to t~~jnterrupt ac~ledgecycle.
Confidential and ProPrietary
1-95
-
, ,,'.
,
D I J I~
n
D1<31.f>
(
"f
V
)
"
...
V
IAKEI
PERIPHERAL
D'EVICES
DAL
MICROVAX
78032 CPU
MICROVAX
78516 VIC
IRQ<3:0>
,:,""
PERIPHERAL
DEVICES
PEAfPHERAi'
DEVICES
PIRQ<15:00>
IAKEOP
°IRQ<3:0>
IAKEON
IAKEI
bAL<15:00>
MICROVAX
78516 VIC
o'RQ<3:0>
PIRO <15:00>
IAKEOP
fAKEON
iAKiIT
DAL<15:00>
MICROVAX
78516
• i'RCf<'31i>
PIRO <"5:00>
IAKEOP
IAKEON
~
.,
TO NEXT DEVICE IN DAISY CHAIN
"EXTERNAL PULLUP CIRCUITS 'REQUIRED
Figure 14· MicroVAX785161AK DaisychainWiring Configuration
Bus Cycles
The VIC responds to read cycles, write cycles, and interrupt acknowledge cycles.
Register read cycle-A read cycle is performed by the CPU to read information from a VIC internal
register. The VIC responds to the read cycle when the CSEL input is asserted and when the address
on the DAL < 15:00 > lines corresponds to the address of a VIC internal register. The signal timing
and parameters for register read cycle are shown in the Specification section. The register read cycle
sequence follows.
1. The CPU transfers an address on the DAL < 15 :00> lines, indicates a read cycle on control lines
CS<2:0>, and deasserts the WR input to the VIC.
2. The CPU asserts the AS signal to indicate that the information on the hus is valid.
3. The VIC latches the DAL< 06:00 > ,CS<2:0>, and WR line information.
4. The external address decode logic, Figure 13, decodes the address on the DAL lines and asserts
the CSEL input to the VIC.
1-96
Confidential and Proprietary
'
Prelimin
. ary
5, The VIC transfers the content of the selected register to the bus and asserts the ROY ootP'llt'.
6. TheCPIilatches the data and deasserts the iSS andASoutputs to. indicate the end of the bus
cycle. 'The VIC th~ deasserts the ROY output to the CPU end the read cycle.
.
to
Register write c:ycle-A write cycle is performed by the cPtI' to write information into a viC
internal register. The VIC responds to the write cycle when the CSEL input is asserted by the CPU
and the address on the DAL<06:00> lines corresponds to the address of a VIC internal register.
The signal· timing ancl parameters. £01' register write cycle are in the SP lines, iiXticaies a write cycle on control lines
CS < 2:0 > , and asserts the WR input to the VIC.
2. The CPU asserts the AS signal to indicate that the infol'mation on the bus is valid.
3. The VIC latches the DAL < 06:00 > , CS < 2:0 > , and WR line information.
4. The external address decode logic, Figure 13, decodes the address on the DAL lines and asserts
the CSEL input to the VIC.
5. The VIC asserts the 'Ri5Y signal, latches the data on the DAL < 15 :00> lines into :the selected
register, and deasserts the RDY output when the CPU deasserts the DS input.
6. The CPU deasserts the AS output to indicate the end of the bus cycle which also ends the register
write cycle.
Iote:rrupJ .~ledge cycle-The CPU performsahinterrupt acknowledge cycle in response to an
intem,tpt request (IRQ<3:0» output from the VIC. The VIC responds to the interrupt
acknowledge bu.s cycle when its IAKEI input is asserted and when its pending interrupt is the same
interrupt .~ recognized by the CPU. The signal timing and parameters for the interrupt
acknOWledge cycle are in the Specification section. The sequence of the interrupt acknowledge
cycle sequence follows.
1. The CPU transfers a hexadecimal value of the IPL on the OAL < 15 :00> lines,. indicates an
interrupt ~cknowledge cycle on control lines CS < 2:0 > , and deasserts the WR input to the VIC.
2. The CPU ass¢rts the AS signal to indicate that the information on the bus is valid.
3. The VIC latches the DAL < 06:00 > , CS < 2:0 > , and WR line information.
4. The lAKEI input is asserted. The timing of thl~ event depends on the'locatl.ono£ the VIC in the
daisychaim
5. The VIC transfers the vector address on the DAL < 15 :00 > lines and asserts the'Ri5Y signal. If
the device is required· to supply the vector' address, the VIC IISs'erls the XVEC output to the
device and the device asserts the'Ri5Y signal.
6. The CPU latches the vector address and deasserts the DS and AS outputs to indicate the end of
the bus cycle. The VIC then deasserts the RDY output, if asserted, to end the cycll . .
..
Con£idendaland Proprietary
-
MicroVAX78Sl6
Power Supply Decoupling
Figure 15 shows the power supply connections to the VIC. The Voo pins connect to 5 Vdc and the
Vss pins connect to a common grourid. All the Voo pins shoUIdbe connected together anCl all the Vss
pins should be connected together. Decoupling is provided by connecting 1. Ou f capacitors between
the Voo and Vss pins as shown on the figure.
r-,--;------r---oooutputs.
SApplies only to the RDY and IAKEON outputs.
ac Electrical Characteristics
Figure 16 shows the input signal apd c1oc.k signal waveforms arid the parameters are listed in Table 8.
tRISnE·
._
'FALL
90%
to%
CLOCK INPUT
elK
INPUT SIGNAL
_Figure 16· MicroVAX 78516 Input and Clock Signal Timing
1-100
Confidential and Proprietary
Table S.MkroVAX 78516 Input and Clock SignsI T~ PuametelS
Symbol
De6rution :
Requirements
Min.
Max.
tCPG
Input clock high .
5.1 ns
500 \is
tePL
tew
Input clock low
5.1 ns
500 J.IS
t R1SE
Input signal riSe
15 or
t pJlLL
Input signal fall
15 nsl
,-,
!
,
50 tis'
Input clock period
.
ITo be deterrDined
2Measuredbet~ri
'
", , .,'
10%, and 90% leve1s.'Appll,~sto'lill il1.put§exeeptPIRQ <'15:00::>. Maximum
tlUSJl and tFALL times£or PIRQ < 15 :00 > isSOO~.
.
Figure 17 and 18 show the signal tipling and symbols for a fugiSterread cycle and register write
cycle, respectively, between the MieroVAX CPU and VIC. Figure 19 shows the signal timmg and
symbols for an interrupt acknowledge cycle when the VIC responds 'with a vector and when the
external device supp1.iisthe vectOr"F~
OAl<15:00>
Figure 17· MicroVAX 78516 Register Read Cycle Timing
os,
CSEL
CS<2:0>
OAl<15:00>
ROY
Figure 18· MicroVAX 78516 Register Write Cyck Timing
1-102
Confidential ~nd Proprietary
.....
....
D-l:~._
......... .
~
,~,';
Wft
CS<2:0>
OAt <15:00>
ROY
IAKEI
lACK
VIC SUPPLIES vecTOR
os
CS<2:0>
DAl< 1S:OO>
XVEC
IAKEI
lACK
~--~~~----------------~
EXiEANAL DE:VICE SUPPLlESVeC'rOA
Figure 19· MicroVAX 78516 Interrupt Acknowledge Cycle Timing
1-103
-.
WR
DAl<15:00>
IAKEI
iAKEoN
IAKEOH
P=_t
IOAS_ _
IAGK
~r--------~------~
DAISYCHAIN-NO PRIORITY PASSED TO VIC
WR
IAKEI
IAKEON
IAK£OH
lACK
55
DAISYCHAIN-PRIORITY PASSED TO VIC
Figure 20 • MicroVA.X 78516DaiSY9hain Priority Signal Timing
1-104
Confidentiafand Proprietary
PtflO<.n>
,
PIRQ ASSERTEDIDEASSERTED TO.IRQ·A$SERTED/06A$S£RT·ED
AS
J
r'pRQS } ______'""-----'-_
~~~~~~~~
PIRQSETUp·
RESET
OAl<15:00::-
AS
R6SET TIMING
Figure 21 • MicroVAX'I851(jPIRQand RndSigtialTiming
Confid~ntial and Propri~tary
1-105
-
PrelimiruIry
MicroVAX"18516
Table 9 • MicroVAX 78516 Signal Timing Parameters
Symbol Definition
Requirements
Min.
Max.
t MSH
DAL < 06:00 > hold after AS assertion
0
t AASS
DAL < 06:00 > setup to AS assertion
15
t ASCS
CSEL assertion after AS assertion
t ASDS
DS assertion after AS assertion
0
t ASH
AS high after deassertion
1.5T
teSLH
CSEL hold after AS deassertion
0
tDRD
RDY or XVEC deassertion from DS deassertion
t DSAS
AS deassertion after DS deassertion
0
tDSS
DS setup before RDY assertion
30
1
RESET deassertion to VIC enabled internally
j.lS
1.5T +45
Read data threecstate delay from DS deassertion
t02
tENA
1
30
5T+250
t lAAS
IACK assertion after AS assertion
1.5T+45
t lDAS
IACK deassertion after AS deassertion
1.5T+45
tlDRD
IAKEO/IAKEOP deassertion from AS deassertion
40
tUDnom
IAKEON/IAKEOP delay from IAKEI assertion (IAKE! asserted
7.5T or more after AS
tHO• ax
IAKEO/IAKEOP delay· from AS assertion (IAKEI asserted less
than 7.5T more after AS
t OH
IAKEI hold after AS deassertion
0
PIRQ assertion to IRQ assertion delay
0
tPL\D
2
25
8.5T+25
tPiDD
PIRQ deassertion to IRQ deassertion delay (applicable to level
triggering only)
tPnom
PIRQ minimum assertion width (applicable to edge triggering
only)
90
PIRQ setup (proper level/edge) before AS assertion
50
Read data delay from CSEL assertion
6.5T
Read data or XVEe delay from iAKEi assertion (lAKE I asserts
7.5T or more after AS)
6T
tPRQS
3
tRDD
tRDDI-.in
t RDDI _
t RDYD
1-106
100
Read data or XVEC delay from AS assertion (IAKEI asserted less
than 7.5T after AS)
RDY delay from CSEL assertion
Confidential and Proprietary
100
7.5T+25
13.5T+25
8.5T
9.5T +25
-
MieroVAX 78S16
Requirements
Min.
Max.
t llSTL4
Minimum RESET low time
t lln
RESET assertion to DALs three-state
RDY delay from IAKEi assertion (JAKEl asserted 7.5Tor m~re
tum....
200 I.Is
100
8T
after AS)
tllyDJ.ax
15.5T + 25
RDY delay from AS assertion (IAKEI asserted less than 7.5T after
AS)
t llyoS
DS deassertion from RDY assertion
0
t WC5H
CS < 2:0 >, WR hold after AS assertion
0
twcss
CS < 2:0 > , WR setup to AS assertion
15
tlll'oo
Write data delay from em assertion
tWDH
Write data hold after D'S deassertion
3.5T-5
20
tVDD must be greater than or equal to 4.75 V during th~ period.
2Maximum time is 100 os unless a PIRQ line is asserted durinS a register read or an lACK cycle. In
these cases the IRQs will be asserted 100 os after the end oithe register read or lACK cycle.
'This ensures that the PIRQ signal will be recognized if the bus cycle started by the AS signal is a
read or interrupt acknowledge cycle. Otherwise the VIC will hot recognize the PIRQ signal until
the bus cycle has ended.
4The VIC requires 5T + 250 os after ~ is deasserted to complete its internal reset. The AS .
signal should not be asserted until after this delay.
Mechanical Confipration
The MicroVAX 78516 is available as a 68 pin cerquad surface mount package or socket mount
package. The physical dimensions of each package is contained in Appendix E.
Confidential and Proprietary
1-107
~. VirtllafthemoryDMA(direct memory access) controner, compatible witp VAXano'Mi61:>VAX
architectures
. .
.
• Full 32-bit architectute and implementation
• Peak data transfer rate of 10 Mbytes/sec
• Maximum DMA transfer length of 1 Gigabyte
• Maximum I/O bus~dressspa~eqf16~S:,
. -
" , : '• .
.
".",.
, i .,
, : '"
~
"
,.
!
.
!
• High-speed CMOS technology
• Single 5-Vdc power,supply
n..........J-..:
.•...•
·~'l''''on
The MicroVAX 78532 MicroDMA controller is a high-performance, dual-ported, foW'~e1
virtual memory DMA contronet. Figure 1 is a block diagram of the MicroDMA controller.
Figure 1 • MicroVAX 78.532 MicroDMA B¥Wk Diagram
It provides two buses, one for the MicroVAX interface and one for the I/O devices. It interfa'q:sthe
32.bit MicroVAX bus with high·speed peripheral devices or inwJligent I/O subsystems ontheS-,
16·, or ;2-bit I/O bus. The MicroI?MA is used for the foilowingapplications:
• ForDMA transfers between memory (or devices) on the MicroVAX bus and memory (or devices)
are the I/O bus
• As a window futo
Micr6vAX memo~ for devices onthel/O bus
• As an access port to devk~s OJ:). the I/O bus.£qr thetvU(;WYA}l:.
'
~/
- "
MicttSDMA is ..~ .VirtualiliemoryDM4, .oon~ller with£Ull lJA.fcqlllpatiblememClty
management capabilities. It processes address translation for :t>MA transfers so that this function is
transparent to the user. Page table information is accessed from MicroVAX memoryancl used
directly without alteration. The MicroDMA. also performs data buffering and byte alignment for
transfers between the MicrovAx bus and the I/O bus.
. .
The
• Pin and Signal Definitions
The input and output signals and power and ground connections of the MiCl'oDMA controller 132pin package are shown in Figure 2. The signals are defined in the following paragraphs in two
groups-signals that connect to the MicroVAX bus and signals that connect to the I/O bus. The
power and ground connections are defined with the I/O bus signals.
VODM
VSSJ<4
iREG
rrRi
iTiU
iii1
W
CU{I
VSS!
tOALOO
IDAL02
tOAI,04',
10.11.\.06
tOAl08
IDALIO
IDAt 12
1DAU4
VOOlQ
"'Xl
"'
.,"
iiMi
H9
so
iiM2
1>0
90
iiiMi
'"
'"
79
IDAl~9
lDAUO
iiM6
iiiS
iWii
ffiii
iAS
iDiiiG
iOPiNT
iCiili
'"
17
"
10At.21
100\l22
",.
100U]
".
'"
"
"
"
70
I04L25
,,.
".
129
iEiii
130
,.....0
'"
132
TEST'
5ir
Dii
MktoVAX 78j32 DMA
TOP VIEW
59
iiiiii
11$1'
CSO
VSSXl
,."
"
DAL29
63
"".....
Con£idential and· Proprietary
DAUD
",,[21
DAL2E1
DAUS
OAl24
DAU3
.Am
"",2,
55
DAUO
54
OAlIS
:"l
DALlS
M
VSOX2
.,
Figuw: 2· MicroVAX 78532 Pin Assignments
1-110
64
."
12
0$'
iAKED
.,
59
11
lOA",>
1OA13O
tDAL31
5.
JO
10AL28
OAl..3t
"
iiM2
IDAUD
lOA'"
.7
..
iiiii
10Al.24
.6
.,
iiiO
Vail
5Miii1
.
6'
Wii
AS
IDAl17
:IDAl~8
7.
123
,,.
iDiiii
ifiijV
JOALI6
041.17
-
Preliminary
MkroVAX Bus Inte:rfaee Signals
~'f911qwing ~s CO~ctto the Mict(lVAX bus and inclu4Ef.da~andaddress \ines,btJ.s conuvI
and statli$llneS, inte,rrljlpt control lines, and a dock input line. The bus signals are summarized in
Table L A more decii1ed.deScription of the signal functions is contained in the following
paragraphs.
'
.
~52
."
,
~i'and aeldress"lliieS <31:00>~Thl1e multi• . ~ lines usedtotransfet data and address infor,mation·between:the MicroDMAand devices on the
DAL<.~l:Ol)1ti.·.
49·33
~AXbus.
Input/ou~puti i\dctl:ess strobe-Asserted to indicate a valid
, ii.;;~sontheDAL<31;OO> lines .
10
5
l)atal!ttObe~Ass~te:~~g
a rea4~e to indi~
cattthat the DALl('3t:OO> lines are available 'to
·~t~ data and deassertedto indicate that data has
.'OS'
'~~i~y~, ...J\~~1i •.4w:~. . a wri~ . ~e . to
in~te that datai,$i~ble on th~tfJW~ 31:00i~
,~~$,and deasserted
the data is to be removed.
when
2
~;:
9-6
BM<3:0>
input/output
'.'
; '-AS!~d to~~te~referencein the YObusrange
'Q~itfJa "MicroD¥Aregister de£ineli by t~e
DAt.< ;1:00> lines,:
{'.,. q"/ . . ~,
Byt~mask-Sp'ecifies
the b}"tes of the
nAL<31:00> lines that co$invalid
d1ttl,
":
~_~",--_ _~........_ _........_ _ _- - , - _...........,""'",".,.....
' .................
'
27
input/output·
'vets~iidf,U£fers ~enab~.
',y".""'h,),""'
",:.\;.,:,:
",;,'>,:"/,<;':""i:/t~
RatdyMllStG.~~y~.ta.t.!l$fe,t'$.~n
d¢¥~i~~~:"l removing
data from the bus.
.
' , ' , ",
if,
26
input/output
,,'
}<-,;"
,""'<
"i','
,,,_,"
-
,
,)'
,,-",
"
Error....,-Asse.rtedto indicate· aiittler condition in
the current MicroVAX cycle.
Confidential and Proprietary
1·111
Pre~···
Pin
Sipl
Input/Output
13-15
CS<2:0>
fuput/outpllt
22-25
IRQ < 3:0 >
output
Interrupt request-Interrupt request lines for the
devices on the MicroVAX bus that are maskable.
29
DMR
output
DMA request-Asserted to indicate that a device on
the MitroVAX bus is. requesting control of the
MicroVAX bus.·
.
20
DMGI
input
DMA grant· input-Asserted to cause the
MicroDMA controller to become bus master of the
MicroVAX bus and perform a DMA transfet:
output
DMA grant output-Used only with systems having
more than one MicroDMA controllers. Asserted
when a DMA request· is to be granted to another
contfuller in the daisychain.
input
Intenupt acknoWledge enable in-Asserted to allow
the MicroDMA to respond to a MicroVAX interrupt
acknowledge.
output
Interrupt acknowledge enable out-Asserted when
an interrupt acknowledge is to be processed by
another device in the interrupt daisychain.
input
Oock in-A TTL clock input used for timing.
19
iA'KEi
16
104
CLKI
103
NC
Control staths-Indicatesthe type of cYcl~lking
performed on the MicroVAXbus.
.
No connection.
MkroVAX Bus Interface LiDes
Data andAdtkess (DAL<31:00»-These are time-multiplexed bidirectional lines used to
transfer data and address information between the MicroDMA controller and other MicroVAX bus
devices such as MicroVAX CPU and MicroVAX memory. The strobe signals AS and DS determine
whether data or address information is tmo.s£erred.
Address Suobe (AS)-The fa1l.ing edge of the: AS signal indicates that lines DAL < 31:00 > contain
~va1iCl address. On the falling edge of AS, the MicroDMA controller latches the .address and
inteqJrets it as. a phy:sical address. If the CSL line is als6 asserted, the CPU is performing a
MicroDMA access op~ration. This access could be to a MicroDMA register. or to a location in I/O
bus memory spaee. Refer to the Access Operations section.
1£ the MictODMA controller is bus rilastet; the AS line indicates that lines DAL < 29:02 > ) contain a
valid MicroVAX physidd memory address. ThbDAL<31:30> lines contain a 1 and a 0,
respectiVely.
The falling edge of the AS signal also mdicates that the information is valid on the BM < 3:0> ,
CS<2:0>, and W'R lines.
1-112
Confidential and ProprietarY
Preliminary
Data stroLe (DS):"'-This sigpal~Pestinting~fll'lt#p~~. ~ ~tt\trimSfer portion of a read
or write cycle. '~. a read cycle, the falling·edge aiDS signal indieates~hat"theDAL< 31;00.>:
lines are available'to receive data and the rising edge indicates that the data mabout to be latd.1~.
During a write cycle, the falling edge of the D'S signal indica~that~tais pl'eSefi.t on the
DAL< 31:00> lines andth.e:rising edge indkatesthat the data is about to be J!iemoved..
Byte Masks lines~
valid during the curtent datatransfet Duringawrite'C}1Cle,.litltsiW< 3:iJ> specify which byres ot
the DAL < 31:.00 :>Ut1.~~co~ y~d data.' :pUljllgare,a4st8~,Jines B~,: specify which
bytes oftheDAL.~.3l;OO>,lines must be supp1iedwith ~data by an aternaldevice. Th,
information on lines,BY<.3:0>·· is 'Vaiidoll the fidling '~'. of the·As: signaL The byte mask
assignments are 'shown in Table 2.
..
of
>
,',.',
DAL<31:2-t>
DAL<23:16>
DAL<15:0S>
DAL<07:0tb
Write (Wi)-This signal specifies the direction OJf data tr$S£er on lines DAL<31:00> for the
rurrentbus cycle. When I"ISserted,tlie cW.TefiiSiiS ~tel ~~~.O:(l.the~.<.>:~()O,~ ..~
during the data transfer portion ofthe cycle. When\'im: is nousserted, anaternal deVice supplies
the data during the data transfer portion of the cycle or lines DAL < 31:00> do not contain data.
The WI{ signal may be used by extemallogic to control the ~j~9. of.I>M-~U~,~~. ~
WRillput 4validon me~~eo~Jhe ~si&tW.
.' (r,i';';:!":'·,,· ' . '.
Data:lJ.' ~t~E)~ThU~r~:~\~~m.t~i~~,by~rQal~'to
control the DAL<:ll.;OO> ~ ~~v!!'~,,~_~MAisbus~ter,it~s
the DBE signal to enable the buffers or transceivers anddeastle$tmi! to disable them.
Ready (IDY)-This signal is asserted by external logic to indicate that it will complete the current
bus cycle. When not .asserted•. itextends. the.~bus.cyple iora slower memory. or periphe:ral
device. The RDY or1!im:S'Pal rtmsfi:be~;tQ~_;tht~tbus cYde'.
Bus Ertor (EiOO-TlUs siPu is as~t,-~,~;d logic toi1x:ticate ~t an error ~
withthecurrentbuscycle.suchasbustimeout6rparityetrQJ;·hasoc:curredandtoetJdthe~
bus cycle. The ERR or iIDY signal must be asserted to endthe cun-ent buscycle.lf tlle Micro~
is bus master and detects the assertion of tlW ~ signal, it ends the bus cycle, interrupts~~
MicroVAX CPU (if enabled), and reootdstheerror.TheMicroDMAasserts the·E&R signal Han I/O
bus error (iElm) signal is detected during aniltcess transfer.
.,'
Control Status(CS<2:0> )-TheMi~DMA'uses these lines together with the WR ~;(to
. recognize and respond to the type'of bus cycle c:urrently·inprogress. Table 3 lists the bus cycle
selections.
1·113
...
Write
Preliminary .
MicrovMf1S532
BusC:xcleType .
Wi
CSline
2
1
0
1
0
0
0
reserved
1
0
0
1
reserved
1
0
1
0
reserved
1
0
1
1
interrupt acknowledge
1
1
0
0
read instruction
1
1
0
1
read lock*
1
1
1
0
read data, modify intent
1
1
1
1
read data, no modify intent*
0
0
0
0
reserved
0
0
0
1
reserved
0
0
1
0
reserved
0
0
1
1
reserved
0
1
0
0
reserved
0
1
0
1
write unlock*
0
1
1
0
reserved
0
1
1
1
write*
*Used by MicroDMA as bus master.
MkroVAX Bus Interrupt Conttol
Interrupt Request (IRQ < 3:0 > )-These lines are used by the MicroDMA to interrupt the
MicroVAX CPU; The vectors associated with these interrupts are provided to the MicroDMAby
. MicroVAX system software. The interrupt request assignments are listed Table 4.
in
Table 4 ~ MicroVAX 78532 Interrupt Request .A$signments
IRQ Line
Interrupt Level
1PL 15
IPL 14
1-114
Confidential and Proprietary
MicroVAX BUsDMA~,
DWA .lteqaest r(i)iiI).;....nIs sigria1, is'8SSertedbJ,tbeMkroDMA controller to initiate a DMA
ttansfetovertheMi~VAX'bus~ Ont;he~;£olJ;wing the assertion of the lThIf signal, the
MicroVAX CPU disables the bus and assert$,~:.eSigna1. ~ allows,
~croOMA.to take
c()ntrol ' ',' •.. ' .
.' can be as~ by the
the
MicroDMAonly.i£ ~J)MA enab1ebitof~)~;«mtrQl~$~~heenset... ',. .
'
DMA..
Iaput(i.mGl)-Wberi~,';ijle'~J)M.N>¢t)~J1er takes control of the'·
MiciOVAX bus for II .DMA ~ ~S' J.irlti it'CW~ in'. d"i~yenain.if more than one DMA
device is in 11 system.TheMicitWAx:'tUJ~~·~l(!fed tothe··.~ lineofrhe rugnest priority
DMAdevice:I£:thisMictoDMA~~rn6f~ aDMA 1'tlq!.;leSt pending, it asserts its
~1ine,
CO
to the§fl4itj~~\$t;~tDMAdevke. A MicroDMA controner
cannotpeftoml'tl DMAthlbsfer O!ttlleMi~~~6ntilit$I)MGI line is asserted.
DMAGtaat()qtpUt{)$ikW)-~~is~:~~~\~~~.'thanoneD~'~~aw! .
is asserted when a DMA request is to,be ~toa\~ priority OMA device in the daisydtain.
Grant
wJndt n1leets
. 'Hn bOth the~VAXb1.JS
CPU and MlcroVAJC'FPU.
'
. I/0Bas Inwface·SipIs
The.lJObus inkrfaceJines connect to the,lJO~d~s!lP9. co~st (If data and ~s li.nces .a11d
contnnJines,ThI: bus,si,snals,~.~i*l,~lej. A ~j~d descriptiol:)(~fthe signal
functi011$iscontained~the£~~pht
'. ,
<:omidential andP1'Oprietary
1-115
67·82
85-101
IDALinput/butput . Dttaandaddress lihes< 31:00 >:... lunetnwtiplexed
lines •usedwtranSfer data and '. address . information
betweertthe MicroDMA and,devices-ASSertedto ilidi~l1te
that a device on the I/O b1i$ requires servke. '.•:Line$
ITR<3:0> corresponds to duinpe13Vu'Origh G,
respectively.
"
.,' "
.
input
I/O interrupt request-Interrupt request lines lor I/O
bulPdevices., Lines lIR <3~0> corresponds to diannel
3 through 0, respectively. Typically uSed to terminate a
DMA .transfer.
input/output
1/0 address strobe-Asserted to indicate that the
IDAL < 31:00> lines contain .valid data., .'
input/output
I/O data strobe'""'":"Asserted during. a re:adcy.;:kto mdi~
cafe that th(! IDAL < 31:00 > lines are availab.k to
receive data and deas~to indicate that the d~ul. has
been received. As~ed during a write cycle toindicate
that data is~liton thell)AL<31:00> ll,nesat¥!
deasserted to indicate,thatdat!;l is to be.rem.o:ved ..
input/output
1/0 data buffer enable.:....Assettedto.'enablethe
IDAL< 31:00 > transceivers.
121-118 IBM<3:0>
input/output
I/O byte mask-Specifies the bytes on the
IDAL < 31:00> lines that contain valid data.
'JWR
input/output
'I/Owrite-Specmes the direction of data 'tranSfer on
'. the IDAL< 31:00> lines. Asserted to indicate that the
current bus master will be the source of the data. Can
be used to control the directioliof thetDAL<31:00,:>
lines.
131
inplltjoutput
I/Chcidy.:....Usedto synchronize datatransfers;hetween
devices operating at different transfer ratesonthe'I/O
bus. The current bus master must wait for the assertion
of this line before terminating the cycle and removing
the data.
130
input/output
I/O error-Asserted to indicate an I/O bus error condition. In the window mode, it also may indicate a
MicroVAX bus error.
129
input/output
I/O DMA request-Asserted to indicate that a device
on the I/O bus is requesting mastership of the I/O bus.
The transfer could be I/O DMA, DMA, or I/O access.
106-109 IIR<3:0>
124
123
1-116
,i'iSBE
Confidential and Proprietary
Pm·
Preliminary
.••..~
I"
ipput/output
21
I/O DMA gtllOt-Asserted to ~thaftbeJlO;bus
has been re1eru1ed by the currentJjO J;nq;. ~tp allow
~DMAt~~to~'
.
MiC1'O'\1AXbu$;~Causes:;""du:" 'MJ,croDM;A)to
input
requesttht·~ ;6fffieMiCroVAXoos;'!l'ypicaHy'used
wbet\pe~,~;~traQ_
11
VBG
114
nmc'
127
IOPIN't
'output
I/O'"~~~r;~~:Aiset~'~Wn;;~tiY"'DMA
channd initia
'. ·.i ."·'N:,· ··t~a#,ydp~sof.
--~--~~~~~~~--~~~~~
28
'iil')Q{
inpUt .
..~;~.
Itra,~.;
iJO'~~A$~'to
115
.
,
..
.
.
····,~~ilp~'*~,tp
"'J,u~
~e.,~~ '-"~~
, •.
enab'k' ~:~fiMA 't;o
··.~. •t1ien'lastu~;lheItDbushy;&fault"" .
. iOwt "
1,132
'I'est
input
U8
ICLKO
output
~st..,..~· Wt·t5tirtgm.e;Mi.trQDMA;~ller
during~.,\'J;i,;:,
I/O clock output......Ac1ock pulse output at one-fourth
of the eLK! frequency.
32,101
18,50,
84,116
31,102
Vss
input
17.51
83,117
30
I/O Data and Address
.
I/O DataaodAddren 8d.(IDAL<~l~OO;»- TheselineS!Are tlme-mu1t~"h~ona1
and are used to tran$i'er data and address infEi'matio.n betWeenthe,~DMACbnt:WU~ aQd
. devkesor oontroUerson the ItObus:1'beilines can.~pt'Q~£ot8-i J6·, or-.J2"bit.data
widths', 'I'he; strobes~als m,lt'Ildms··deterll'linewb\rtherthe.bus camesduaor ~
information.
1·117
-
Prelimin.my
I/O Address Strobe (W)-If the 1;v,[i~M4.is~U/l ..tnast~;:JtU8e$~emsign:aliojqdicate that
the IDAL<31:00> lines contain valid address information and that the information on
mM < 3:0 > and iW'Risalso \1alid.The iASline 1S use lines
are\1alid during the current data transfer: During a write cycle, the IBM < 3:0 > lines specify the
bytes that contain valid datafofwriting:During a read cycle, the IBM<3:0> lines specify the
DAL<31:00> lines that must be supplied with valid data by an external device. The information
on the IBM < 3:0 < lines is valid on the falling edge of the iAS signal.
The validity oUhe bytes also depends on the width of the current data transfer. If the current
transfer isl byte wi4e, the information on the IBM < 3:0 > lines is not significant because a byte is
transferred orily' on the IDAL<07:00> lines. H the current transfer is 2 bytes wide, the
IBM<3:0> lines specify whether lines IDAL< 15:08> and/or IDAL<07:00> contain valid
information. If the·rurrent transfer is 4 bytes wide, the valid bytes are specified hy IBM < 3:0> .
Table 6 lists the I/O bus byte mask assignments.
an
Table 6· MicroVAX 78')2 I/O Bus Byte Mask Assignments
I/O Byte Mask Line
Valid Data
IBM}
IDAL< 31:24 >
IDAL<23:16>
IDAL< 15;08>
IDAL<07:00>
I/O Write (iWR)-This signal specifies the direction of data transfer on thelDAL < 31:00> lines
for tMrurreht·bus cycle. When the IWR signal is asserted, the current·bus masterdrivesth~ lines
during the data transfer· portion of the cycle;. When the IWR signal is not asserted, 1ltl external
. device supplies the data during the data transfer portion of the cycle or the lines are idle. This signal
maybe used by external logic to control the directional the IOAL"" 31:00> transceivers. The fWR
information is valid on the falling edge of the iAS signal.
1-118
Confidential and Proprietary
-
I/ODataB• . B~ {I6iE)-..,This signalmaybettBdW!:Ilh~;1WRs~ toamtrolextermd
IDAL<,31!OO>~vers and buffers. When asserted, it enables a~ot buffer and
when l'lOt aSserted,the O\1tputs of the tmnsceiverorxbufferate disabled.
I/O Ready (ilO)Y)-During I/O bus cycle data transfer, the bus master must wBit for the assertion
ofthissignalbeforetenm.,.ting the.cui'rent cycle. andx1at~.(tit"re~da.·.&omdlC'Ous.
1/0 •••·Ert:or '(MII)--Thissp indica~*·~bt1S.:el~COndItiOl!rothe ~tx.b6s
~ter> If theMicroDMAdetedS·the.·assertiOhot··$is·. •jJ(,~~itnMAttanSf~lt ·~the
eUitetlt·· bus"'cyehe, mc.t·interruPt$'tbeMicln'\1AX·.~PU;(if~~)1>If··~l\tiCtbnMA··deteCi$ tfle
Biijlsignald~ IlWindo\v transfer;it~ieriimkRsOthat ~buserrofis i1~ftfit& the:ttO
processor.
lIQ,.·1la1a1.iaosfet Control
~,""'&om·I/O·Periee.(iiii< :ltO»-'lbiJ~is~~atJ..JI€)bus;~
~DMAserviceot by an ~d~1_t"~~5"~~~;' ~1itlb·is
~ed.to.~.cbannel Sim~~~ •.·~.~~~·to~'cbannel~
with "iNO' athigbest·priotityand 1m. at~t;tflJ,~ ~~~to.theaSsertiqnp£a
line by performing a DMA uans£er if the channel is in DMAr$'.Ide ora window transfot,if ithe
channel is in window mode. The MicroDMA does not admow~ these sj~;.~~~
performedau~~tkaIly. ~.~inypl~dirl.t~ ~.~st~~j£.,fI;,~~
device ~ IU\Nu:knpwlq~;$~.
.
Interrupt Request £rom I/O Device (ttf<):O> )-These ~are asserte4.byB~~Qn:the
I/qhtJs tointettUPl,thet&~~.. O~,~el$a~Jo,.e~~~~lfa ~t·~~
wlu,:nthe~o~. .ljtleis~,:the~t~~i~~~Y~~~~
channelis disabled . ~JO!the~pt.~••~.*.1'~",~·~.~a~. ,~
if;rterrupt. conditiOll tbatcausedthclinet9be~~'fr1.,l>e,,~~t~.~~ .c.an,he
enabled again.
I/O BusDMACOnttol
IfODMA' ~t (16II1i),:--:rhls signal iS8$serledbfa~ti~busm~teitotequd$ttt0buS
ownership. When theMicrdDM1\i$ttHeaefmlt;buS;'~~(~Rmtmt'l$~,t~
'i'D'M'I is an inputsigrtalthat istypidUy..~.~l/Op~s$Otor'U_~;ontheI/Obus;
When the MicroDMA is not the de£aultWs l:ll4lSter, it assertstne'~ line to use the bus :for a
local memory transfer or a transfer to a peripheral register.
I/O DMA Grant (1l)im)-This signal is asserted by the CUl'...entbus·' master'inl'¢S1)OOse to the
IDMR signal. It indicates that the bus master has released the l/Obusandthat·1oUS ownetsbip.truly
now be assumed by another device.
I/O ~ Conttol.,
. " ......
............. '.
. '., ....... '. '"
.<
MkloV'AX BUI~it tvm-ThissigriaI~assettedpy~I(Q Pl;fJce5SOl' tocOntrolt:he
Micro\7~blls when'~OrtniJlg aw~~rt'l~~tO~S:&sn£lid:~the
~croVAX cpuaccessesthel/Obusatthe~~;j(nlflinesiiliould be interpreted as a registe1' address; It should be
deasserted at the enq q£ the cycle~
I/o. P!Ocessor Intarupt(lOPINT)..,..Thi& signal is asserted when any ofthe MicroDMA channels
initiates an interrupt to an I/O p1,'O(:esso~ Becausemor; than on~.channel may interrupt atcthe same
time. t:h,e I/O processor.must poll.aU the c~ls.to.determine the.highestpriority interrupt.·l'he
I/O processor software deasserts this ~. by settitlg the £NABLEbit pr clearing the.:poNE bit
of the channel control register of tpe interrupting channel. or .py. redirecting the interrupt.to
the MicroVAX CPU.
MkroVAX Bus Loc:k {I1OCK)-'This signal is asserted by an I/O processor to create locked
MicroVAX bus cycles during a window reference. During window read and write Operations,
asserting this signal ·causes Mic:roVAX memorY read and wrlteoperations to be,~d .witb··a
code of WI on linesCS <2:0 > (read lock or write unlock). The MicroDMA continues to assert ·the
DMR line while the~signal is asserted, but OOesllot assert the read lock cOde while accessing
the page table information required by the willdow access. It dOes not check the sequence of reads
and writes ..
MisceDaneous Signals
itO Bus ~(IM:A,grER)~When asserted, the MicroDMA becomes bus master of the Ifo bus
by default and it responds to the assertion of the IDMR signal by asserting the IDMGlineand by
.
releasing the I/O bus.
CLiP SeIed(Cfi;)-This signal is used by the external logic toallow·the MicroVAX CPU to access
the 1/0 buso! a MiciODMA interr1aIregister. When'asserted, theinf6rmation on the
DAl. < 23:00> lines is interpreted as an I/Obus physical address if lines DAt < 23 :09 > are not all
Zeros or the info.rmationon lines DAl. < 08:00 > are interpreted assn internal register 'address if
the DAl.<23:09> lines are all zeros.
Reset (RESET)-When asserted, this signal sets the MicroDMA to a specified. initial state.
Test (TEST contains an internal pull-down circuit;
.
I/o. Bus' Qock Output (ICLKO)-Aclock output at one-fourth of the CLKHrequency.
Power and Ground Connections
Voltage (Voo)-5Nde. power supply.
Gtmmd· (Vss)-Ground reference .
• MieroDMA Controller Operation
The Micrp.QMA controller is a multipurpose interface that can be used ~ween.the MiqoVjJc
processprar;~a compatib1e32~bit I/O bus forperipherai devices Of controllers. The MicroDMA has
£ou,riodq,endendy programrpable.channels thro~ which DMA, wind()w,and I/Ohus data
trapsferscan be per£orfiled. ·The four chinuels. are~l!signed a Hxed priodtYm~h chlln~ 0 having
the ~l>t priop,tr. Devi~.thatttlUlSfer.4~ta at th~highest! rates or metnorytransfeqshotlldbe
assign~4the l~t priority chapn~s to
theslowerdeviq!s to.aecessthe bu,s. This ~on
briefly describes the characteristics
these transfers and the otheJ; major .functi0l1s
the
MiCl"ODMA.
. ..
,
' ! ..
.
of
1-120
allow
Confidential and Proprietary
of
1}rpe$of DMATtaosfets
The ptimary function of thet.MiGraIDMAistopmfo~bto&.~'HMA,~~~arnwnts
of data: ClltJ bettarufetftd !between,a~ceodnteJligentl.lOSUbsys~mon theJlO bUswli\ldeviee
or memory on MicroVAX bus without CPU intervention. DMA transfers may als<>involve~
~~n,;data~n't1aytd4ataib\!l~.
Window!T~I~devices. on.thel1Q .·bus·.earti~;!';~l\J.dndows>;';in tht!MiE1,liQVAX
memory. Window transfers allow the devices to access buffers aytd to operate from wotkqueuedri
~Ory> Them.ca~ 1IllIiI·~of i\'~C1W:~4¢~e{.l~!t~~~;~~~~jo~l{W~Vl~~~
~yin'!.101veaddres~~shltion~datI'J~g~~tl
.
's>< "
•.
flO DM.t\ .1NMlers.;...TheMrortIDMAoodtrol1fJt;cat1i,;~br~;1ocal 01/0 ·.bus~.tttlnsfers .
it.tdependehtlyof~het aCtivitiesthat'1lI3Yoo;tti~.ihe~AXJ)us• • i(ODMA ~
allows the I/O bus memory to be used as a large buffer for data tate s~ ..Xhel/QbttstMnlory
can be filled by a channel in I/O DMA mode while another channel in DMA mode transfers the data
to MicroVAX memory. I/O DMA transfers do not involve adclress translation or data realigrunent.
Access Operations
The MicroDMA controller allows the MkroVAX CPU to access memory and devices on thel/O bus
similarly to devices directly connected to the MicroVAX bus. These access operations are
performed by the user application and define a region of MicroVAX physical address space as an I/O
bus access range. When a range is referenced, an access to one or more equivalent locations on the
I/O bus is performed. Access operations may occur in parallel with channel operations such as
DMA, window and I/O DMA transfers. During access operations, data packing and unpacking is
performed and address translation or realignment is not performed.
1·121
-
-----
---
-._-------_._----------'----------------:,
Data Realignment'-:Data iii MiQ'OVAX memory orTIO iriemorycan be accessed on arbitrary byte
boundaries. 'The re#ignmentcanoccur as pattof a lDMA or window transfer. During realignment a
data byte, word, or longword on one bus. is .buffered by the MicroDMA and shifted for proper
~nment on the other bus.
Data Buffering-The MicioDMA provides a buffer oftwo longwords per channd to improve DMA
transfer speed and efficie,ncy. 'The data from a device on one bus can be read and buffered until the·
device on the other bus is ready to accept the data, The buffer can also be used to convert bytes and
words from the I/O bus into longword data for the Micio.VAX bus .. This improves the speed of
MicroVAX bus transfers. During realignment, the buffer is used to hold data temporarily that is to
be realigned.
Data Packing and Unpacking-Data packing and unpacking is used for byte and word DMA
transfers and access operations. It asembles or separates data between the MicroVAX and I/O bus.
Data packing is performed to arrange byte or word data into longwords for the MicroVAX bus. Data
unpacking separates longwords into bytes and words for the I/O bus.
Address Translation
'The MicroDMA performs virtual to physical address translation for DMA and window transfers if
mapping is enabled for the channd involved in the transfer. 'The MicroDMA uses page table
information stored in MicroVAX memory and maintained by MicroVAX system software. This
information includes the system page table (a collection of page table entries contiguous in physical
memory), the process page tables (a collection of page table entries contiguous in virtual memory),
and the global page table used to describeshated pages.
Bus Interfacing
The MicroDMA controller prevents different activities between the buses from interfering with
each other. 'The controller appears as a DMA peripheral device on the MicroVAXbus. It requests
and relinquishes the bus through the DMA request andgrandogic. 'The bus interface. uses signals
with the same timing characteristics as those used .for any· other MicroVAX bus device. such as
MicroVAX·memory.
'The controller appears as an I/O processor or CPU on the IjO·bus. The I/O bus supports the
simultaneous use o£S.;l6-,and 32-bit devices and has an interfacing protocol simil~ to :that of the
MicroVAX bus.
The MicroDMA may operate as a master or a slave on either bus. Therefore, the bus controhignal
AS (address strobe), for example, can be used as an input or output. Thble 7 summarizes the
MicroDMAoperations. It specifies operations for which the MicroDMA is bus master and shows
the source and destination buses for each. MicroDMA internal registers can be accessed from either
the MicroVAX bus or I/O bus.
1-122
Confidential and Proprietary
-
Preliminary
MicroVAX 78'32
'fable 7· MiaoVAX 78'32 OpeNtion Summary
Destination
Address
Source
Bus
Bus
Translation
Data
Data
Alignment
Packing
Yes
Yes
Yes
MicroVAX/IO
~s
Yes
No
10
10
No
No
No
MicroVAX/IO
IO/MicroVAX
No
No
:res
Operation
Bus
Master
DMA
Transfer
MicroDMA
MicroVAX/IO
IO/MicroVAX
Window
Transfer
IOP*
IO/MicroVAX
I/ODMA
Transfer
MicroDMA
Access
Operation
MicroVAX
*IOP = Intelligent I/O device or I/O processor.
Registers
The MicroDMA controller contains 63 byte addressable, user-accessible registers. The MicroDMA
controller contains· one set of global registers that defineS the Overall. state of the MicroDMA
controller and four sets of channel registers that define the stat~o£each channel. The registers may
be accessed from either the MicrovAXbus or the I/O.bus.~
The registers occupy a 512-byte region in MicroVAXI/O address space. The base address of this
region is defined by the user and must begin on a 16-MbYte boundary. The user's application
decodes lines DAL<31:QO> and.assetts the cSL line whenan~ddress in the register region is
referenced. When CSL is asserted, the information on the DAL < 08:00 > lines is interpreted as a
register address if the DAL<23:09> lines are all zeros. HDAL<23:09> are not all zeros, the
information on DAL < 23:00 >is interpreted as an I/O bus address and an I/O access cycle will be
performed. (Refer to Access Operations.) The addresses associated with the global registers are
listed in Table 8. Table 9 lists the addresses assigned to the channel registers.
Table 8 • MicroVAX 78532·GJobaJRegisters.Adchess Assignments
ReadfWrite
Address·
(hexadecimal)
Mnemonic
(RfW)
Description
000
DGCTL
RW
Global ControlRegister
004
DSBR
RW
System Base Register
008
DGBR
RW
Global Base Register
Reserved
OOC-03C
*Register addresses must appear on the DAL < 08:00:> or IDAL <::: 08;00:> lines. References to
reserved addresses will cause unpredictable results. Some registers have more than one function
depending on the current operational mode of the MicroDMA controller.
1-12.3
Confidential and Proprietary
~'el!!!fN'[1l!1i1l:!l
~":I:
8""'!!l
4 .. _ _ _
~_.
-
_____________
~_,
_ _,__ """ __ ,__ _
-
Preliminary
MicroVAX 18'32
Table 9· MieroVAX 78532 Channel Regis1;efIiAddress Assignments
Address"
Read/Write
CbO
ChI
Ch2
Ch.3
Mnemonic+
RfW
Register:!:
040
080
OCO
100
DCCTLx
RW
DMA Channel Control
044
084
OC4
104
048
088
OC8
108
DCINTx
RW
DMA Channel Interrupt Vector
04C
08C
OCC
lOC
DCIOBAx
RW
DMA I/O Base Address
04C
08C
OCC
IOC
DCIDSx
RW
DMA I/O Source Address
050
090
ODO
110
DCIBCx
RW
DMA Initial Byte Count
050
090
ODO
110
DCWMx
RW
Window Mask (window)
054
094
OD4
114
DCBOx
RW
Byte Offset (mapping on)
054
094
OD4
114
DCUPAx
RW
MicroVAX Physical Address (no map)
058
098
OD8
118
DCSPTEx
RW
SVAPTE Register (DMA, window)
058
098
OD8
118
DCIDDx
RW
I/O DMA Destination Address
060
OAO
OEO
120
DCCSVx
R
Current System Virtual Address of PTE
064
OA4
OE4
124
DCIOAx
R
Current I/O Bus Address
068
OA8
OE8
128
DCBCx
R
Current Byte Count
06C
OAC
OEC
12C
DCPTEx
R
Current Page Table Entry
070
OBO
OFO
130
DCPAx
R
Current Physical Address
074
OB4
OF4
134
Reserved
078
OB8
OF8
138
Reserved
07C
OBC
OFC
DC
Reserved
Reserved
'"Hexadecimal notation. Register addresses must appear on the DAL < 08:00 > or IDAL < 08:00 ~
lines. References to reserved addresses will cause unpredictable results.
tx = Register designations 0, 1, 2, or 3, depending on channel number.
:j:Some registers have more than one function depepding on the current operational mode of the
MicroDMA controller.
To access a register from the I/O bus, the user's application decodes IDAL <23:00> and. asserts
the lREG signal to indicate a register access. The MicroDMA interprets the IDAL<08:00>
information as a register address. The I/O buswrite access to the registers is controlled by bit 10 in
theDGCTLregister, the value of which is usually determined by MicroVAX system software.
DMA Global Control Register-The DMA global control register (DGCTL) is used to control,
configure, and deternUne the global status for the MicroDMA controller. The format of the register
information is shown in Figure 4 and defined in TableJO.
1-124
Confidential and Proprietary
MicroVAX 71:5:}2
Preliminary
if::
;:::I::::H::::
I .
DEAD
n): ++ ~mrnI'
.
1 1
.
lOWE
DIiON
MWE
RESET
EBLIM
Figure 4 • MicroVAX 78532 DMA Global Control Register Format
Table 10· MicroVAX 78532 Global Control Register Desc:.ril'Uon
Bit
Description
31
DEAD (Dead1ock)-Aread~only bit that is set to indicatetllat a deadlock situation
existed in a previous I/O bus access operation. Geared during a reset operation or
by writing a one to this bit.
Not used (read as zeros).
30:24
23:12
VID (Version identification)-A read-only field that contains.the version number
of the MicroDMA chip. For the initial Version.of this chip. thetiliti:lbet is 00000001.
11
MWE (Maintenance ~iteenwle~:--Settina~sread/wri~ bit enables writing to
any register includingth~read-only regis~rs.Jtis~itlte~ for diagnostic and
manufacturing test usage only. The status/error bits cannot .he set when this bit is
set. Geared during a reset operation.
10
lOWE (I/O bus register write enable)-A read/write bit set to enable an I/O device
to write data to a channel register. When cleared, a write to external ~gisters will be
ignored. CI~ during a reset o~tion.
9:5
BUM (Burst limit)-Specifies the m~imum letigth (in.~ <:ycles)of a DMA blltst
on the MicroVAXbuswhen EBLlM (bit 1) is set •• Clearedd,l:\ring a reset operation.
4:3
WID fWidth)-A read/write fl~rdtFlat specifies the' data width of 1/0 bus access
operations as follows. These bits Me cleareddut1ng areSet;op.eradon.
<
WID Bits
,,'
,,-,',
';.
-
'-"
' - ' , , '
';
Data Wldth
04
03
o
o
1
0
1
0
1 byte
lbyte
2 bytes
1
1
4 bytes
2
DEN (DMA enable)-A read/write bit that must be set to allow the MicroDMA
controller to perform DMA transfers on the MicroVAX bus. Clearing this bit
prevents the MicroDMA f1'?Ill~Ss~~tingcI5iVM.Cleared durmga,reset operation.
1
EBLIM (Enable burst limit)-A read/write bit. When set~BL:rM(bits 9:5) defiJle
the maximum length of a DMA burst. When· clear, the I)MA burst length is
unlimitecl. Cleared during a reset operation.
o
RESET-A read/write bitthatisset toinitiare,areset operation that forces the
MicroDMA to a known itlitial state.Settmg'thisbit has the same effect as asserting
the RESET input.
..
..
ConfJdential and Proprietary
_._-----------
1·125
...
Preliminary,
MicroVAX'78'32
DMA System Ba" Register"';' The DMA system base register (DSBR) is used in address translation
and contains a copy of MicroVAXsystem base register which is the physical address of the base of
the system page table. Refer to MicroVAX 78032 CPU in this databook for more detailed
information on the MicroVAX system base register: The DSBR must be loaded by MicroVAX system
software before any address translation occurs so that MicroVAX memory will not be corrupted.
The format of the register information is shown in Figure 5 and defined in Table 11.
Figure 5· MicroVAX 78532 DMA System Base Register Format
Table 11· MiCl'OVAX 78532 DMA System Base Reaister Description
Bits
Description
31:30
Not used (read as zeros).
29:02
SBR (System base register)-Contains the physicallongword address of the system
page table. The same as bits 29:02 of the MicroVAX system base register.
01:00
Not used (read as zeros).
DMA Global Base Register....,...The DMA global base register (DGBR) contains a copy of the
information in the MicroVAX global base register. It is used by the MicroDMA during virtual-tophysical address translation to locate the global page table that describes the shared pages in system
virtual memory. The register must be Ioadedby MicroVAX system software before any virtual DMA
activity so that MicroVAX memory will not be corrupted. The format of the register information is
shown in Figure 6 and defined in Table 12.
Figure 6· MicroVAX 78532 DMA Global Base Register Format
Table 12 • MiCl'OVAX 78532 DMA Global Base Register Description
Bits
Desc:.ription
31:.30
Not used (read/write).
29:02
GBR (Global paseregister)-Used to locate. the global page table in the system
virtual memory. The~ as bits 29:02 on the MicroVAX global base register
01:00
Not used (read as zeros).
1-126
Confidential and Proprietary
Preliminary
MicroVAX 78'32
DMA Channel Control Registers (0·)- The four channel control (DCenO through DCCTL3)
registers, one for each ch.annel, are used to control, configure, and determine status for the four
channels. Three translation error bits are used for system, process,aoo global tranSlation errors~
Translation errors can occur when a bus error is detected while fetching a page table entry, by an
invalid.page table, and by a global page table entry that lead$ to another global page table entry.
The cause of errors is indicated only by the error bits that define the location in the translation
process in which.the errol; occurred. For~mplef ~~he el;tc?t occutteddQring the global part of
translation, then the global error bit will be·set.,1J.:'h,e£or1l19,tof t~register information is shown in
Figure land defined in Table 13.
..
IPR
CHAtlIITOr, WIDTH
CIR TE~M
ISPTE
Figure 7· MicroVAX 78.532 DMA Channel Cont1tJfRegisteYS (0-3) Format
Table 13 • MicroVAX 78'32 DMA Channel eonurolRepters{O.3)Deacription
,
, <
'j'
"
' .
'
•••••
, '
"\
Bits
Description
31
ERR (Error)-A read-only bit ,seqo iQcation, or by setting the ENABLE
(bit 00).
.
26
IBE (I/O bus error)-A read-only bitsetto indicate that a bus errol' occurred on the
I/O bus during aDMA transfer on this channel. Cleared during a reset operation, by
writing a 1 to this location, or by setting the ENABLE (bit 00).
ConfiQential and Proprietary
1-127
...
Preliminary
Bits
DeScription
25:24
Not used (read as zeros).
23
OONE~Aread-only bit set to indicate that the current channel operation has
terminated. Cleared during a resetoperation when written to a 1 or when ENABLE
(bit 00) is set.
22
IOI (I/O interrupt)-A read/write bit set to indicate that the IIR line for this
channel has been asserted. If the 101 (bit 10) is also set, the current tranSfer will
terminate. Cleared during a reset operation or when ENABLE (bit 00) is set.
21:18
Not used (read as zeros).
17
PHYS (Physical)-A read/write bit set to disable the address translation for this
channel. The contents of the DCSPTE;x: register are ignored and the contents of the
DCUPAx register are used as the first physical byte address of the transfer.
16:15
IPR (Intemlpt priority)-Read/write bits that specify which IRQ line is asserted if a
channel error occurs or when a DMA operation terminates as follows:
IPR
16
o
o
Bits
15
0
1
1
1
0
1
IRQ Line
. iRQ(}
IRQ1
IRQ2
IRQ3
14:13
NXTCH (Next channel)-Read/writebits that indicate the number of the next
channel to be enabled in a chaining operation when CHAIN (bit 12) is set.
12
CHAlN.;....Aread/write bit set to start a transfer on the channel specified by
NXTCH channel number when the current transfer terminates without error.
11
nop (Interrupt I/O processor)-A read/write bit when set and IE (bit 02) is set, it
causes the channel interrupts to be directed to an I/O bus processor when the
IOPINT signal is asserted: When cleared and IE (bit 02) is set, the channel
interrupts are directed to the MicroVAX CPU as determined by the IPR line.
10
101 (Termination on intettupt)-A read/write bit set to terminate DMA transfers
on this channel upon the assertion of the IIRsignal for this channel.
09:08
CTM (Count mode)-Read/wri~e bits that determine whether addresses on the
MicroVAX bus and/or I/O bus will remain the same or be incremented for data
transfers on this channel; MicroVAX bus addresses are incremented by 4. The I/O
bus addresses· are incremented according to the data width of· the I/O device
involved in the transfer.
CTM
09
o
o
1
1
1-128
Bits
• 08
0
1
0
1
MieroVAX Bus
I/O Bus
Address
Address
sanie
same
same
incremented
incremented
same
i n c r e m e n t e d , incremented
Confidential and Proprietary
-
MicroVAX.78512
07:06
WID'l'H...,....Read,lwrite bits that specify; the.data width of the I/O device associated
with the channel as follows:
wmrH Bitt
Data Width
07
06
1 byte
o
o
1
1 byte
o
1
o
2·~s
1
1
4 bytes
05:04
MODE (Mode field)--Readj'W'ritebits that speci£}r the operational mode of the
channel.
MODE Bits
os
04
0
0
0
1
0
1
1
1
03
DIR (Direction)-A read/write bit that specifies the direction of a data transfer in
DMA mode. Set to specify a transfer from the I/O bus to the MicroVAX bus. Cleared
to
02
Operational Mode
specify a transfer fromthe:MkroVAKbu$t()-~I/G bus.
IE (lntettuptcmah!e)...,.....t\ ~~te bitsettoe~bk~e/~pts to devices on
the MicroVAX bus and I/O bus. Must be set before or at the same time ENABLE (bit
00) .is set. cleared '.during a 'reset operation . to iiilinediately disable all channel
interrupts.
01
00
TERM (Tenninate)-A read/write bit, set to force the termination of the current
channel operation, but alloWS" buffered datatobewrltten.Cleared during a reset
operation'Of by setting ENABLE (bit 00).
ENABLE (Enable)--A~writl! bitsetto ~iatdydear bits 31:27 and 23:22
of this register and to co~ the chanM1 tU;Cotding to bits 17:03. Cleared during
a reset operation to i~ately abort the ~nt channd. operation. Any buffeted
data is lost.
DMA ChannelIn~~ Register$(O-J)-Thechannel interrupt veetor/(DCINTO through
DCINT3) registers cOntain the Vector value used by MicroVAX CPU to process interrupts related to
the operation of the channeL The priority.oft;Q,,1f interrupt is: specified:by thl! LPR field of the
register. The format of the register information is shown in Figure 8 .
. Figure 8· MicroVAX 78532 DMA Channel Interrupt Registers (0-3) Format .
Confident;ial andPl;'Oprietary
1-129
Preliminary
Mic:roVAX78532
DMA I/O Base Address Registers (O.3)-The DMA I/O base address (DeIOBAO through
DCIOBA3) registers contain the base address of the device or memory on the I/O bus that will
participate in a DMA transfer on this channel. When the DMA transfer is started, the register is
copied into the DCIOAx register which may be modified during the transfer. The DCIOBAx
register information may be used in subsequent transfers or in chaining operations. The format of
the register information is shown in Figure 9.
Figure 9· MicroVAX 78532 DMA I/O B~e Address Registers (0-3) Format
DMA I/O Source Address Registers (O-3)-The DMA I/O source address (DCIDSO through
DCIDS3) registers contain a 24-bit physical I/O bus address that specifies the source of an I/O DMA
transfer. This address may be associated with a peripheral device or the start of a memory buffer in
I/O bus memory~ The format of the register information is shown in Figure 10.
Figure 10· MicroVAX 78532 DMA 1/0 Source Address Registers (0-3) Format
DMA Initial Byte Count Registers (O.3)-The initial byte count (DCIBCO through DCIBC3)
registers contain the initial byte count for a DMA or I/O DMA transfer. When the transfer is started,
the register information is copied into the DCBCx register where it is decremented as the transfer
proceeds. The maximum DMA transfer length is 1 Gbyte and the maximum 1/0 DMA transfer
length is 16 Mbytes. The format of the register information is shown in Figure 11.
Figure 11- MicroVAX 78532 DMA Initial Byte eountRegisters (0-3)Format
DMA Wintlow Mask Registers (O-3)-The DMA window mask (DCWMO through DCWM3)
registers are used during window mode data. transfers to help determine where in MicroVAX
memory a window mode transfer will occur. Refer to the Window Transfers paragraph for more
information. In window mode, the register information is logically ANDed with the address on the
I/O bus to specify an offset within the window. The format of the register information is shown in
Figure 12.
1-130
Confidential and Proprietary
MicroVAX18532
Preliminary
F::~.J: ::::::::H7: : : : : : : : : : n
S
Figure 12-MicroVAX 78532 DMA Window M.4sk Registers (0·3) Format
DMA Byte Offset Registers (0·3)-The DMA byte offset(DCBOO through DCB03)~gisters are
used with the DMA system virtual PTE (OCSPTEO through DCSPTE:3) registers to 4etermine a
memory location where a mapped DMA·· buffer or MicroVAX· window starts. The register
information is used tofind the physical address of thdirst (baSe) page of the tranSfer. Each register
contains an offset (in bytes) that,
added to the base page address, specifies the physiCal
address of the first byte of the buffer or window. Refer to the Address Translation paragraph for the
use of these registers. The format of the register information is shown in Figure 13.
when
Figure 13· MicroVAX 78532 DMA Byte Offset Registers (0-3) Format
DMA MicroVAX Physical Address· Registers (0.3)-The DMA MicroVAX physic31 address
(DCUPAO through DCUPA3) registers contain the base physical address in MieroVAX memory for
unmapped transfers in DMA and window modes. For unmapped DMA mode transfers, this register
specifies the physical address in MicroVAX memory at which a DMA transfer will begin. For
unmapped window mode transfers, an offset is added to the contents of these registers to
determine the starting address of thetransfer. The offset is obtaif1eJd by ANDing the address on the
I/O bus with the DCWMx register. The fomrat of the· register information is shown in Figure 14.
Figure 14· MicroVAX 785J2DMAPhysicai Address Registers (0-3) Format
DMA System V'trtual Address PTE Registers (O-3)-The system virtual address PTE (DCSPTEO
through DCSPTE)) registers contain the system virtual address of a page table entry. The page table
entry points to the base·add~ssof the page at which a mapped DMA buffer or window begins. An
offset (expressed as a number of bytes) contained in the DCBOx register is added to the base
address to specify the address of the first byte in the butfer or window. The format of the register
information is shown in Figure 15.
Confidential and Proprietary
1-131
.-
MicroVAX785J2
313029
00
~ :::::::::::H7eis : : : : : : : : :: : : : : I
0
Figutr! 15 • MicroVAX 78532 DMA System Virtual Addtr!ss PTE Registers (0-3) Format
DMA I/O Destination Address Registers (O-3)-The DMA I/O destination address (DCIDDO
through DCIDD3) registers contains a 24-bit physical 1/0 bus address that specifies the destination
of an I/O DMA transfet This address may be associated with a peripheral device or the start of a
memory buffer in I/O bus memory. The format of the register information is shown in Figure 16.
Figutr! 16· MicroVAX 785)2 DMA I/O Destination Addtr!ss Registers (0-3) Format
DMA Current System Vtttual Address PTE Registers (0·3)-The current system virtual address
PTE (DCCSVO through DCCSV3) registers contain the system virtual address of the page table
entry currently being accessed. If a translation error occurs (for example, when a page table entry is
invalid), the system virtual address of the erroneous page table entry is in this register. These
registers are read only. The format of the register information is shown in Figure 17.
Figure 17· MicroVAX 78532 DMA Current System Virtual Address PTE Registers (0-3) Format
DMA Current I/O Bus Address Registers (0.3)-1£ an I/O bus error occurs, the DMA current I/O
bus addre~s (DCIOAO through DCIOA3) registers contain the I/O bus address associated with the
error. These registers are read only. The format of the register information is shown in Figure 18.
Figure 18· MicroVAX 78532 DMA Current I/O Bus Addtr!ss Registet! (0-3) Format
1-132
Confidential and Proprietary
-
Preliminary .
MicroVAX 785:12
DMA Current Byte Count Registers (0.3)-The current byte count (DCBCOthrough DcaC3)
registers contain the byte count for the transfer currently in progress. It specifies the number of
bytes remaining In thetrans£et. TheSe registers are read only. The format of the register
information is shoWn in Figure 19.
Figure 1~. MicroVAX 785}iPMA c.urrentByte CoujdR.egtstersro.:3)Formaf
DMA Current Page 18ble Entry Registers (0-3)-The DMA current page>table ~try (QCJ!I'EO
through DCPTE3) registers contain the page table entry currently being accessed. If a translation error occurs due to an invalid page table entry, the erroneous page table entry can be found in
these registers. These registers are read only. The format of the register information is shown in
Figure 20.
.
Figure 20 • MicroVAX 78532 DMA CurrentPage TttbkEntry RegisteiS (0-3)Format
,
"
"
',.'
;-,
','
'\"',
.,
-",',-
,.
'
,
,
DMA CurrentPhysicd Address Registers (O.l}:-I£:aMicrovax; buserroto(;curs, theOMA Cl.ij:'rent
physical address (DCPAO through DCPAJ} registet5:CIU1 usually be decrelllentedby 4 to obtain the
MicroVAX longwonlphysical addresSI.\$S0ciatedWiththeerrot.An~ception is when bits 8:0 = 0
during a mapped transfer (Le. ,a page boundary.iserossedJ.and thelongwondthat caused the efror
is the last longword of the previous page. These registers are read only. The format of the register
information is shownm Figure 21.
Figure 21 • MicroVAX 78532 DMA Curretit Physical AddressRigisters (0-3) Format
Confidential and Proprietary
1-133
,..
Preliminary
MicroVAX 78532
• cLanneJ Operations
The type of operation performed by a channel is specified by MODE bits 05 and 04 of· the
appropriate DMA configuration register (DCCTLO through DCCTL3).·· A channel operation is
performed by the following:
• The configuration data is entered into the DMA global control register.
• The I/O device involved in the transfer must be appropriately configured and enabled. This is
usually accomplished by an access operation that writes data to the I/O device.
• In the MicroDMA, the user registers that define the parameters of the channel operation are
written (initialized) with appropriate data. If mapped transfers are to occw; the DMA global base
register and DMA system base register must also be initialized.
• The data that configures the channel and initiates the channel operation is written into the DMA
channd control registet
DMA Transfers
A DMA transfer requires the user to specify the starting MicroVAX bus address, the starting I/O bus
address of the transfer, and the number of data bytes to be transferred. The configuration
parameters such as the direction and data width of the transfer are then written into the
appropriate DMA channel control register.
For unmapped DMA transfers, the starting MicroVAX bus address of the transfer is completely
specified by the physical byte address of the beginning of the data buffer. This is contained in the
DMA MicroVAX physical address register. For mapped DMA transfers, the system virtual address of
the page table entry that points to the first buffer page and the byte offset from the start of that
page to the first data byte must be entered. These addresses specify the beginning of the buffer in
virtual memory when the DMA· system base register and the DMA global base register are
initialized. The system software computes these quantities from a virtual address and the process
context, and loads them into the appropriate DCSPTEx' register and the DCBOx register to define
the virtual buffer. The starting I/O bus address of a transfer is contained in the DMA I/O base
address register.
The initial byte count is contained in the DMA initial byte count register (DCIBCx). At the
beginning of the transfer, the DCIBCx register information is loaded into the current byte count
register (DCBCx) and the reglster is decremented as the transfer progresses. When DCBCx reaches
zero or becomes negative, the transfer is complete and is terminated.
Configuration information for the DMA transfer is contained in the DCCTLx register. In addition
to specifying the data width and direction of the transfer, it also contains a "count mode" that
specifies which addresses will be incremented !lnd the value pf the increment as data is transferred
from one bus to another. Addresses to or from the MicroVAX bus may be incremented by 0 or 4
because memory is always addressed in longworos on that bus. Addresses to or frof)1 the I/O bus
may be incremented by 0,1,2, or 4 depending on the programmed width of the I/O bus. I/O bus
addresses are not incremented for DMA transfers to or from a peripheral device through its data
register. I/O bus addresses are incremented for I/O bus memory to MicroVAX memory transfers.
Table 14 lists the initial conditions of the registers involved with a DMA transfer. When these
conditions have been established, a DMA transfer is initiated by the assertion of the ITR signal by
the I/O device. A simplified flow diagram of the actions of an I/O device, the MicroDMA controller,
the MicroVAX CPU, and MicroVAX memory during a typical DMA transfer is shown in Figure 22.
1·134
Confidential and Proprietary
-
Preliminary .
MicroVAX 78'32
Table 14 lists the initial conditions of the registers involved with a DMAtransfer:. When these
signal by
conditions have been established, a DMA transfer is initiated by the assertion of the
the I/O device. A simplified flow diagram of the actions of an I/O device, the MicroDMA controller,
the MicroVAX CPU, and MicroVAX memory during a typical DMA transfer is shown in Figure 22.
m
18ble 14· MicroVAX 78532 DMA 'liansfer Initial Conditions
Bit
Content
DGCTL
OC(16)·(DEN =1, WID 03:02 (byte)
DCIOBA2
1001(16) (1/0 base address)
OCIBC2
OA(16)(Iqitial byte count)
DCB02
3316}(Byteof£set)
OCSPTE2
System virt:u8l address of base page table entry
DCCTL02
03
~
DCCTL2
05:04
10 (DMAfmode)
OCCTU
07:06
01 (Byte wide)
OCCTU
09:08
10 (HOLD I/O addre~a.nd INC MicroVAX address)
(Transfer is to MicroVAX)
Data to be transferred is 01,02,03,04,05,06,07/08,09, and OA.
Confidential and Proprietary
1·135
, MieroVAX
~I'lmory
MicroVAX
CPu
110 Bus "
MicroDMA
Controller
Device·
,t
WAITING 'FOB
D~TA
MAY PERFORM
ADDRESS
TRANSLATION
Figure 22· MicroVAX 78532 DMA Transfer Flow Diagram
1-136
Confidential and Proprietary
Preliminary
MloroVAl<
CPU
Micl'OVAX 78"2
110 BUS
Device
MiCNOMA
Controiler
ASSERTS As; Wrf. ETC.
ASSE\lTS Rl'W
LOOPeACK
TOWAIT.,OROATA
Figure 22 • MicrOVAX 78532DMA ffans/er
Flow Diagram
(Continued)
.
'.
,.
:
-
"
~'-
, ";
Confidential· and ,Proprietary
,,'
MicroVAX785)2
Preliminary
An example of a DMA sequence to transfer 10 bytes of data from a bytewideI/O device at I/O bus
address 1001 (hexadecimal) to a buffer in MicroVAX virtual memory at offset 33 (hexadecimal)
from the base page is listed in Table 15. Channel 2 is used for the transfer.
Table 1.5 • MkroVAX 78532 DMATransfer Sequence
Byte MicroVAX
Bus
Count Operarion Address'" BM < 3:0 > Data
10
write
---30
0111
9
8
7
6
write
---34
0000
5
4
3
2
1
0
write
---38
write
---3C
Transfer terminates
0000
1110
I/O
mM < 3:0 >
Bus
Data
1001
xxxO
xxxxxx01
1001
1001
1001
1001
xxxO
xxxO
xxxO
xxxO
xxxxxx02
xxxxxx03
xxxxxx04
xxxxxx05
1001
1001
xxxO
xxxO
xxxO
xxxO
x-xxxxx06
xxxxxx07
xxxxxx08
xxxxxx09
1001
xxxO
xxxxxxOA
Operation Address
read
01xxxxxx read
read
read
read
05040302 read
read
read
read
09080706 read
xxxxxxOA-
1001
1001
*The upper bits of the MicroVAX address depend on the page table information and are not shown.
The lower two bits of the MicroVAX address are indeterminate and not necessarily zero.
Window '&ansfers
To perform a window transfer, a window (Le., a set of I/O bus addresses that correspond to
locations in MicroVAX memory) must first be defined by the user. The user application decodes I/O
bus addresses (IDAL<23:00> such that the ITRx signal is asserted when an address in the
window region is referenced.
When the I/O processor begins a window access, the MicroDMA uses the IBM < 3 :0> information, and the width of the I/O bus (byte, word, or longword) the effective byte count of the transfer
and to perform substitution for the low one or two bits of the incoming address, shown in Figure 23
and Table 16.
For unmapped window transfers, the base of the window region is completdy specified by the
physical byte address of the window in MicroVAX memory. This must be loaded into the
MicroDMA physical address register (DCUPAx), and is added to the window address derived from
the I/O bus device requesting the window access.
1-138
Confidential and Proprietary
-
MicroVAX78S32
IDAL<23:D2>
TQOCBCx
(BVTE COUNTf
00
WINDOW ADDRESS (W.o.)
Figure 23 • MicroVAX 78532 Window Addressing Logic
This window address is derived by ANDing the effective 24-bit I/O address with thewindow'mask
register DCWMx). Using the window mask to mask off the "don't care" bits from the address,
simplifies the external hardware required to decode the
signal. The sum of this window
address and the DCUPAx register forms the MicroVAX physical address of the window transfer. The
actual transfer will require 1I1Ofe than one access ,~. MicmVAX ~ is the.
bytes cross of
longword boundar}r..
. .,' .
rmx
accesS
&r mapped wln<;low,trans£ers, both the SYlj;tem virtual ad~sof th~ p~~tabk entry and byte
offset in the £irs~ window page must be s~ied ~ly,toaDM,4 t;ansfetTh~incomingI/()bus
address and byte tQaSb define a displacetn¢Dt;£rom the base ol,t&~.Ths is masked by the
contents of DMA window mask register and ~.to compute a new system. virtual address PTE and
byte offset.
For both mapped.and unmapped window transfers, the width qhhe channd is defined by DMA
channel contJ.t)l register bits 7 and 6. .
.,
,.
.
COn£identialiend Proprietary
.....v......_....." ...'_'R""ll...
P.f"_ _
C!O...
V'R.......""''"'_'_1iI1Jf_......_ .......,.... .......,__
~_""_'_"''''Il-IlI_
_~
~
1-1.39
_ _ _"'__ _ _ _...
~
,,~_~
-
MicroVAX 785j2
Table 16 • MicroVAX 7~'32 WiQdow Transfer Byte Count and Effective Displacement
Channel Width
IBM<3:0>
Byte Count
Effective I/O
Bus Address < 01:00 >
Byte
xxxx
xxOO
1
IDAL < 01:00 >
2
1
1
IDAL<01> '0*
IDAL<01> '1
IDAL '0
4
.3
00
01
10
11
00
01
Word
xxOl
xx 10
Longword
0000
0001
0011
0111
1000
1001
1011
1100
1101
1110
2
1
.3
2
1
2
1
1
10
00
01
00
"(') indicates concatenation.
If the MicroVAX CPU performs an I/O bus access when' a windoW' access is being performed, a
deadlock may occur as the MicroVAX and I{O processor each wait for the other's bus.
The I/O processor can ensure a unique access·to MicroVAX memory. Before beginning a window
access, the I{O processor must assert VBR and wait for VBG to be asserted. Because the MicroVAX
pus is acquired by the· MicroDMA before the window access, the possibility of deadlock is
eliminated. Aftei the window access (or accesses), VBRshould be deaSserted to allow the
MicroVAX processor to regain control of its bus.
The MicroDMA chip conciinshardware that detects the presenCe of a deadlock if it occurs. It
breaks the deadlock by causing a bus error on the MicroVAX bus by asserting the ERR· signal and
sets a bit in the DMA global control register to inform the MicroVAX CPU of the cause of the error.
Thble 17 lists the initial conditions for an example of a window transfer. The sequence of events
involved in this example is shown in Table 18. One byte is to be transferred from the I/O bus to the
MicroVAX bus. The channel is configured in word mode. The user application decodes I/O bus
addresses in the range xxxlOOOO-xxxl01FF (hexadecimal) as window references. The I/O
processor writes data word 55xx to location 10022 (hexadecimal).
Confidential and: Proprietary
Preliminary ,
MicroVAX1SSl2
Table 17 • Mic:roVAX 78S32 Wmdow 1iansfer Initial Conditions
Bit
Content
04 DEN = 1
.IFF (Mask high bits of I/O bus address)
DCWMx
DCCTLx
05:04
11 (Wirtdilw mode)
DCCTLx
17
1 (Physical addressing)
DCCTLx
07:06
10 (Word width)
7341 (MicroVAX memory base physical address)
DCUPAx
Address
Table 18 •MieroVAX 78.532,Wmdow ~erSequence
Data
Qpeqa~ ·.\.ddress . 1J~<3:0:> ~ta
10022
xxOl
I/O Bus
xxxx55xx Write
7364
1110
Operation
xxxxxx55 Write
The MicroDMA adjusts the value of the lower bits of the I/O bus address, as shown in Table 16. A
byte count of 1 is llent to the DMA 'current byte C6tlnt :reiistet.
•
,
' 1
I/O DMATransfer
An I/ODMA: transfer is an unmapped, unbUffereddita transferbetweert an I/O bus
source and an I/O bus destination. Because buffering arid datil liligrimeht are not performed, the
source and destination addresses must be aligned on "nat_'boundaries.ilf a channd.is
configured to 'perform word transfers; theacidresseslitU$tbe:a multiple of 2. If a channel is
configured to perform loogword transfers,. theaddressesrnust beainultiple of 4. An' I/e· DMA
operation has the following sequence:
1. The appropriate ITR < 3:0 > signal is asserted by an I/O device.
2. An I/O bus read cycle is performed at the address specified by the DMA I/O source address
register (DCIDS).
3.If bit 8 of the DlvIA channel cohtrorrewster (DCC1L)iss~t,theDCIDSregister is in.:remented
by the width of the channel specified by bits 7:6 of the DCCTL register. If cleared, d)e.DCIDS
register is not changed.
4. An I/O bus write cycle is performed at the ~dress speci£iedby the D.MA I/O destin,atio.1,l address
(DCIDD) register. The appropriate ITR< 3:0> line should be de asserted by the end of this
write cycle if the I/O device is not ready for another transfer.
5. If bit 9 of DCCTL register is set, the DMA destination address (DCIDD) register is incremented
by the width of the channel. If cleared, the DCIDD register is not changed.
6. The byte count initially contained in DCIBC register and subsequently contained in DCBC
register is decremented by the width of the channel. If the byte count is zero or a negative value,
the transfer terminates. If it is not, the transfer continues at step 1.
Confidential and Proprietary
1-141
Preliminary
MicroVAX 7Sl32
• &cess OperatiOI,1S
Figure 24 shows the relationship between a user-defined "access region" in MicroVAXphysical
address space and its counterpart in I/O bus address space. The user application decodes MicroVAX
bus addresses such that csr; is asserted whenever a reference to the access region is made. The
access region always starts on a 16-Mbyte boundary and the lower 512 bytes of the region are
reserved for the MicroDMA internal registers.
MicroDMA
I
I
I
I
I
I
MicroVAX BUS
XXFFFFfF
I/O BUS
ACCESS
XXOOO200
XX0001FF
XXOOOOOO
MicroDMA
REGISTER
ACCESS
--
I/O BUS
FFFFFF
I/O BUS
LOCATIONS
I
I
000200
MicroDMA
REGISTERS
I
000000
Figure 24 • MicroVAX 78532 Access Operation
When the CSL signal is asserted and the address on lines DAL<23:09> is equal to zero, a
MicroDMA internal register is accessed by the address on lines DAL<08:00>. When the
DAL<23:09> address is not zero, the I/O bus is accessed.
An access operation may require the transfer of a byte, word, or Iongword as determined by bits 4
and 3 of the DGCTL register and the infortpation onlinesBM<3:0>. The following are. more
detailed examples of the access operation.
Example 1-able 19 lists the sequence required to perform an access operation to write a word in
I/O bus· memory from the MicroVAX CPU. The number 1234 (hexadecimal) is to be written into
location 2002 (hexadecimal) and the I/O bus width is 16 bits. The MicroDMA has an address of
21000000 (hexadecimal) in MicroVAX physical address space.
Table. 19 • MicroVAX 78532 Access Operation Sequence 1
I/O
MicroVAX
Address
BM<3:0>
Data
21002000 0011
1234xxxx Write-
1-142
Operation Address
2002
IBM<3:0> Data
Operation
xxOO
Write
Confidential and Proprietary
1234
MicroVAX7S'12,
Example 2-Table 20 lists the sequence required to perform access operation 2 from the MicroVAX
CPU. The number 332211 (hexadecimal) is read from location 2001 (hexadecimal), The I/O bus
width is 8 bits: ThE! MicroDMA has'an address of'21000000 {hexadecimal)in MicroVAX physical
address space. The initial condition of the DGCTL register is bits 4:3 = 01 (I/O bus byte width).
18ble 20 • MicroVJ,1\X 785.32 Access ()peJation Sequeru:e 2
<
Address
;BM;-;-<~3;-::O:::-:>~
,>
,'"
,"
.',,-
",
_.,,',
_.
t
I/O
MiaoVAX
Data
Operation Addtess
Read-
21002000 0001
2001
.2002
2003
mMData
Operation
x:~.~O
Read
x:xxO
xxx{)
---11
---22
·--33
Read
Read
332211xx
• Address Translation
When bit 17 (PHYS) of a channel control register is clear, mapping is enabled and virtual to physical
address translation will occur for DMA and
. window
.. mode transfers on that channel.
For mapped DMA transfers, the information requirements to completeIyspeclfy a buffer in virtual
memory after the DSBR an.d DGBRregisters h~he~ninitia1ized lire that the DCSPTEx register
must point to the page table entry that references the phY,'sicalpage in which the virtual buffer or
window starts. The DCBOxregistermust contlrlnthe byte, offset from the beginning of that
physical page to where the virtual buffer or window starts:'
Figure 25 shows the address translation for DMAtrans£ers ~atq~ references to process (PO or P1)
or system page tables. Figure 26 shows a DMA transfer th~t uses references to global (Le., shared)
page tables. Further information related to VAX memory mahagement is in Chapter 5 of the
VAX-ll Architecture Reference Manual (EK-VAXAR·RM).
Confidentialand Proprietary
1-143
-
Preliminary .
....
31
MicroVAX1g,;32
09 OS
DCBOXLI______
~--------O----------------~I--~;·~8-YT-E----~1
3130 29
DCSPTEx
00
09 08
VPN OF PTE
10
EXTRACT
31
2322
o
ADD
31
OSBR
00
PHYSICAL BASE ADDRESS OF SYSTEM PAGE TABLE
YIELDS
31
00
PHYSICAL BASE ADDRESS OF SYSTEM PTE
~
PERFORM MEMORY REFERENCE TO FETCH SYSTEM PTE; CHECK VALID.
IF BUS ERROR. OR INVALID. OR GLOBAL,. DCCTLx<3O: 28>" 001.
~~
00
SYSTEM PTE
PFN
00
09 08
29
PHYSICAL AORESS OF
PO, PI, OR SYSTEM PTE L -__________________
~
__
--~--~
PERFORM MEMORY REFERENCE TO FETCH PO. Pl. OR SYSTEM
PTE. CHECK BITS < 31. 26, 22>.
IF BUS ERROR. OR INVALID, OCCTLx<30:2S>= 010.
iF VALID. THEN USE PFN TO FORM PHYSICAL ADDRESS.
IF GLOBAL, TO TOP OF.FIGURE B.
00
PTE
PFN
29
09 08
PHYSICAL ADDRESS OF DATA OR
INSTRUCTION
PTE <31.26.22>
lXX
000
001
01X
PTE TYPE
VAUDPFN
VALID PFN
GLOBAL PTE (SEE FIGURE 261
INVALID. I/O ABORT
Figure 25· MicroVAX 78532 DMA Address Translation for Process and PTE References
1·144
Confidential and Proprietary
00
Preliminary
00
GLOBAL PAGE TABLE INDEX
EXTRACT
24 23
020100
ADO
SYSTEM VIRTUAL BASE ADDRESS OF GLOBAL PAGE TABLE
OGBR
YIELDS
31 30 29
SYSTEM V I RTUAl ADDRESS
OF GLOB ALPTE
I
00
0908
VPN OF PTE
BYTE
I
EXTRACT
31
I
DSB
A
,
23 22
02 0100
f
0
,
,
31
ADD
I
PHYSICAL BASE ADDRESS OF SYSTEM PAGE TABLE
31
oj
00
I
YIELDS
00
~
(
;':
" ;.-'vl
PHYSICAL BASE OF SYSTa4 filE'
,d
'"
;
"
;::'}.'
"',,"
'"
,
"
PERFORM MEMORY REFERENtE'TO FEl'CK S¥STIlMPTt:; CHI!CK';Vll.tlO:
IF BUS ERROR, OR INVALID, OR,GLOBAI...aoerL"'<30,28>~101V
'
21 20
31
00
I
PFN
29
00
09 08
PHYSICAL ADDRESS OF ,
FINAL PTE
PERFORM MEMORY REFERENCE TO FETCH GLOBAL PTE; CHECK VALID,
IF BUS ERROR, OR INVALID, OR GLOBAL, DCCTl,,<30:28>=10L
31
00
21 20
I
I
PFN
09 08
29
00
J
pHYSICAL ADDRESS OF
oATA OR INSTRUCTION
LOW BYTE
= OCBO" IF FIRST TRANSLATION
= 0 OTHERWISE
, Figure 26 • MicroVAX 78532 DMA Address Translation for Global References
Confidential and Proprietary
1-145
MicroVAX 78532
Preliminary
i
For mapped window transfers, the actual transfer might not start in the page referenced by the
DCSPTEx register. The window address, shown in Figure 23) is used to compute new values for the
SVAPTE register and byte offset shown in Figure 27. The operation is transparent to the user.
A byte offset (BO') and system virtual address (PTE) are associated with point B in Figure 28 that
must be calculated before address translation can occur. Figure 28 shows how these parameters are
determined. Once BO' and DCSPTE' are found, they are used to perform address translation in the
same way as for a DMA transfer (see Figures 25 and 26).
SYSTEM VIRTUAL ADDRESS SPACE
.
B
1
DCSPTEx'
HIGHER
ADDRESSES
1
-~
WA
WA'
Ao
DCSPTEx
A ==
B'"
WA'"
WA' =
t
80
of
BASE ADDRESS
WINDOW
ADDRESS WITHIN WINDOW THAT IS REFERENCED
WINDOW ADDRESS RELATIVE TO BASE
WINDOW ADORESS RELATIve TO"FIRST PAGE
DCSPTE,,' AND BO' ARE THE DISPLACEO SVAPTE AND
BYTE OFFSET DERIVED FROM DCSPTEx AND BO.
Figure 27· MicroVAX 78532 Address Translation for Window References
1-146
Confidential and Proprietary
-,
Pre1iminary
31
WINDOW ADDRESS (WA)
Mkl'OVAX 7"'2
2423
I
0
00
I
I
ADD
0908
31
DeBOx
I
2423
YIELDS
BO
r
00
0908
SOl
0
1716
31
I
1
0
31
WINDOW A DDRESS' (WAit
00
I
02 0100
0
o
I
ADD
DCSPTEx
YIELDS
31 30 29
DCSPTEx'
1
Figure 28· MicroV'AX 78532 WinfJow RejerencePdrameters
. MieroDMA Interrutrts
The MicroDMA can interrupt the MicroVAX CPU otan I/O p~sor; ~pending onthe contents of
the interrupting channel's DCCTLx register.
.. . .
'
The termination o{'aDMA tran$fer sets DONE (bit '3) oftheDMA cMnnelcontrol(])CCTL)
regist~ resUlting in an interrupt if IE (bit 02) is ~t. The.i,ntenupt will be' proces~d by the
MicroVAX CPU if nop (bit 11) is cleared or by an I/O processor ifbit 11 is set.
For a MicroVAX CPU interrupt,
• The MicroDMA asserts an IRQ < 3:0> line according to the level encoded by IPR (bits 16 and 15)
of the DCCTLxregister. "
• The MicroVAXCPU responds by initiating an inteuupt~knowledge bus (}Tcle. Th¢ MicroDMA
provides an interrupt vector frOm the the DCINTx register.
• If the systemcoilta:ins more tharttme MicroDMA controller, the MlcroDMA closest to the CPU
with respect to the interrupt daisychain that has posted art iilteriuptat the current level
, participate in the interrupt acknowledge cycle.
will
• If .more cllan one channel on the MicroDMAcp.ntl'()ller ,has posted an, interrupt, at the current
level, the channel with the highest priority will return the interiupt vector
Confidential ~nd Proprietary
to the CPU.
1-147
-
Preliminary
MicroVAX78'32
• The system software dears DONE (bit 2)) qf the DCCTLxregister after the interrupt has been
acknowledged to prevent the same interrupt from heing acknowledged ag~.
For an I/O processor interrupt,
• The MicroDMA asserts the 10PINT signal.
• The I/O processor polls all MicroDMA channels to determine which channel caused the interrupt.
• The I/O processor processes the interrupt according to some I/O processor dependent protocol.
• The I/O processor software dears DONE (bit 23) of the DCCTLxregister after the interrupt has
been acknowledged .
. Termination of DMA Transfers
DMA and I/O DMA transfers are normally terminated when the byte count associated with the
transfer and contained in DCBC register becomes zero or a negative value. A transfer can also be
terminated before the byte count reaches zero when the TERM (bit 01) of the DCCTL register is set
or when the external hardware asserts the appropriate IIR signal and TOI (bit 10) of a DCCTL
register is set. The 101 (bit 22) of the DCCTL register is also set to indicate that termination was
caused by an interrupt. The number of bytes remaining to be transferred can be read from the
DCBCx register.
DMA transfers can also be terminated when the i'E'RR signal Is asserted during an I/O bus cycle,
when the E'RR signal is asserted during a MicroVAX bus cycle, or when an invalid page table entry is
referenced.A global page table entry reference that is either invalid or refers to another global page
table entry will also terminate the transfer. If the transfer is terminated by an error, a corresponding
bit in the DCCTL register is set to specify the error type.
The MicroDMA performs the following for all DMA transfer that are terminated.
• Sets DONE (bit 23) of the DCCTL register.
• Sets 101 (bit 22) of the DCCTL register if an I/O interrupt caused the termination.
• Clears ENABLE (bit 00) of the DCCTL register.
• Asserts the IOPINT signal if IE (bit 02) and nop (bit 11) of the DCCTL register are set.
• Initiates a MicroVAX interrupt at the level specified by IPR (bits 16 and 15) of the DCCTL register
if IE (bit 02) is set and nap (bit 11) is cleared .
• Chaining
The MicroDMA includes logic to automatically switch channels after the data transfer has
terminated. This is defined as chaining and is normally used by I/O subsystems that continuously
transfer data at high data rates. To reduce the time required to service an interrupt and reconfigure
a channel following the termi{lation of.a DMA transfel; chaining is used to switch channels and the
buffers associated with the channels to prevent data loss.
Chaining is enabled by setting CHAIN (bit 12) of the DCCTL register and the next channel in the
chain is specified by NXTCH (bits 14 and 13). If the current DMA transfer terminates without
errol; the channel specified by the NXTCH bits begins operation. Interrupts that were enabled for
the first chanriel will be serviced when the next: channel in the chain is active.
The pins for the ITR < 3:0 > channels involved in a chain should be connected together to preserve
the transfer requests.
1-t48
Confidential and Proprietary
--
Preliminary
The pins for the ITR < 3:0> channels involved in a chain should be ~nnectecl together txj.~
the transfer requests •
. MiaoDMA Reset
When the RESET line isasserted,the RESET (bit 00) of the DGCTLregister is set and the
MicroDMA performs the following reset operation:
• DGCTL regist:er-C!ears'theDEAD(bit31),IOwE (bit 10), wtO'bit<04:()3> an lines.
2. TheWRline is unassertc:dandthe CS<;2:0 >.lines life drivefl.1:Jy the busmastertoi,ndicate the
type of cycle being performed.
3.· The bus master drivesthe~BM~·:<:::-O.j"".:O~>:-. lines.
4. The bus master asserts the AS signal to indicate that the address on the DAr.,. lines is valid a~ can
be latched. When the· MicroDMA is be:\ngaddtessed for n;gi:ster OJi'·. I/O bus §\GCe$s,theCID:
signal must be asserted. The AS signal also qualifies the~~for~iol;l ontbeCS<2:0> ,WR,
and BM < 3:0 > lines.
5. The bus master asserts the DS signal to indicate that the bus is available to receive the required
information. The bus master also asserts the DiE signallit~time whlcP. canbe used to
control DAL line bus transceivers.
•
..
.•
6. If the slave can supply valid data within minimumaccesstimc>.it, asserts,.the R'DYsigna!·at the
first sample window. after the assertion of AS and the master latches the data. If ·gata is, not
available at this time, the master waits eight periods of the Cuq·~ and samples the ROY
signal again. This sequence continues every eight clock peri~ unt:Uthe ROY signal is asserted.
If a bus error occurs, the external logic or the bus slave will respond by asserting the ERR signal.
The bus master must then process thc:error. The current bUl! CYl';lejs completed when the RDY or
ERR signals are asserted. The bus master latches the request:eddata anddea~rts theDS line.
7. The bus master deasserts the
line if it is asserted, and asserts the AS and DBE lines to end
the bus eycle.
m
ConfidentiaLand Proprietary
Preliminary
MicroVAX 78532
MicroVAX Bus Write Cycle
A MicroVAX bus master performs a MicroVAX bus write cycle to transfer information to another
MicroVAX bus device. During the first part of the bus cycle, address and control information is sent
to the bus slave. During the second part, the data to be written is transferred. The sequence of
events follows:
.
1. The bus master drives the physicallongword address of .the location to be read onto the
DAL < 29:02> lines.
2 . The WR signal is asserted and the CS<2:0> lines are driven by the bus master as required.
3. The bus master drives the BM < 3:0 > lines and asserts the AS signal to indicate that the address
on the DAL lines is valid and can be latched. When the MicroDMA is being addressed for
signal must be asserted. The AS signal also qualifies the
register or I/O bus access, the
information on the CS <2:0 >, WR, and BM < 3:0 > lines.
4. The bus master asserts the DBE signal, drives data onto the DAL lines, and asserts the DS line to
indicate that the data is valid.
5. If the slave can accept valid data within the minimum write cycle time, it asserts the RDY signal
at the first sample window after the assertion of the AS signal and latches the data when the DS
line is deasserted. If the data cannot be accepted at this time, the master waits eight periods of
the CLKI signal and samples the RDY signal again. This sequence continues every eight clock
periods until the RDY line is asserted. If a bus error occurs, the external logic or the bus slave
responds by asserting the ERR signal and the bus master must then process the error. The
current bus cycle is completed when the RDY or ERR signal is asserted.
6. The bus master deasserts the DS signal to indicate that it will remove the data from the DAL lines
and deasserts the AS and DBE lines to end the bus cycle.
m
MkroVAX Bus DMA Cycle
This cycle is used to force the bus master to release control of the DAL lines and related control
signals to another MicroVAX bus device. The sequence of events follows:
1. A device requests the use of the MicroVAX bus from the bus master by asserting theDMR signal.
2. If the bus master is not performing a locked read cycle, it responds to the assertion of the DMR
by releasing the DAL<31:00>, AS, DS, DBE, WR, and BM<3:0>, lines.
3. The bus master asserts the DMG signal when it releases control of the bus and grants the use of
the bus to the requesting device.
4. One or more read and/or write cycles occur on the bus between the requesting device .(the new
bus master) and its slave.
5. When the requesting device is finished with the bus, it deasserts the DMR line to return control
of the bus to the original bus master.
6. The bus master deasserts the DMG signal and resumes operation on the bus.
Mic.ro VAX Bus Interrupt Acknowledge Cycle
A MicroVAX bus master performs an interrupt acknowledge cycle to acknowledge an interrupt
request from a slave through the IRQ lines and to read a vector, The timing for this cycle is the same
as the MicroVAX bus read cycle shown in Figure 30. The sequence of events follows:
1. The bus master transfers the priority of the interrupt being acknowledged onto lines
DAL< 04:00 > . The DAL<29:05> lines contain zeros and the DAL<31:30> lines contain
the value of 10.
2.· TheCS < 2:0 > lines are driven by the bus master to indicate an interrupt acknowledge cycle.
3. The bus master asserts all the BM <3:0> bits.· The WR signal isunasserted.
1-150
Confidential and Proprietary
-
MicroVAX 18"2
4. 'The bus master asserts~he AS signal to indicate that the interrupt.priority on the DAL lines is
valid and asserts !;he OS signal to indicate that the bus is available to receive incoming data. The
bus master also asserts the DBE line, which can be used to control DAL line transceivers.
5. If no error occurs, the exter:nallogic or the bus slave transfers the illterrupt vector on the
DAL<09:02> lines, the normal processing/Q-busprocess;.qg flagon the DAL line,and
asserts theRDY signal. Refer to the Micra VAX CPU User's Guide for a description of the normal
processinglQ-bus processing flag. The DAL < 15 :10,Q1 > lines ~ust be set to a valid high or low
level in accordance with the setup times shown in Figure 30.
.
6. If an error occurs, the external logic or the bus slave asserts the ERR signal. Thebus master
cancels the cycle jUld ignores the data on the PAL lines.
7. The bus master latches the interrupt vector" dea~erts the D'S signal, and deasserts the AS and
DBE signals to end the cycle.
.
I/OBusC~
I/O Bus Read Cycle~An I/O busmasterper£ormsan 110 bus re~ cyele when it requires
informacion from another I/O busdevice. During the first part oh read cycle, address and control
informacion is sent to the bus slave. During the secondplU;t of the cycle the data is read. The
sequence of events follows:
1. The bus master drives the physical longword address of the locationto be read: onto the
IDAL<23:00>.lines.
2. The iWR signal is left unasserted. 'The bus masteras~rtsJihe IBM <3:(,» .as required.
4. The bus master as~rtsthe lAS signal to indicate. that theadqress on theclD.t\J. Unesisvalid and
ready ~ be latched. The lAS signal also qualifies the informatipnon!;heIBM <3:0 > and iWR
lines.
..
.
5. 1£ the MicroDMA is not I/O bus master. and is performing ~ wiPdow~ss, then the iTR signal
for the requested window channel should be asserted when the lAS" signal is asserted. If a
MicroDMA register access is to beoorfofmed) theIREG sigmllshould. be asserted at this time.
6. The bus master asserts the IDS signal to indicate that the bus is available. t9receive: the required
in£or~tion. At this time tn.e bus master also asserts IDBE which can be used to control IDAL
line transceivers.
7. If the slave can supply valid data within the minimum acces$tii:rI.~, it assert.S the IRDY signal at
the first sample window after the assertion of the lAS signal and the master latches the data. If it
cannot supply valid data during this time, the master waits four periods of the eLK! signal and
samples the IRDY signal again. This sequence continues every f~ur clock periods until thenmY'
line is asserted. If a bus error occurs, the external logic or th~ pus s1~ve responds by asserting the
IERR signal, and the bus master must then proceSS the error. The current bus cycle is completed
when the 'iRi5Y or IERR signals are asserted.
8. 'The bus master latches the requested data, deasserts the IDS. signal, and deasserts the '!AS arid
IDBE signals to end the bus cycle.
I/O Bus Write Cycle
An I/O bus master performs an I/O bus write cycle to transfer information to another I/O bus
device. During the first part of the cycle, address and control information is sent to the bus slave.
During the second part, the data is written. The sequence of events follows:
1. The bus master drives the physical longword address of the loca.tion to be read onto the
IDAL<23:00> lines.
2. The iWR signal is asserted.
Confidential and Proprietary
1-151
----------"-
~----------------------g---~
Preliminary
MicroVAX 78>32
3. The bus mastet drives IBM<3:0> lines and asserts the lAS signaIto indicate that the address
on the IDAL lines is valid and should be latched; The lAS sign-al also qualifies IBM < 3:0> and
IWR line information.
4. If the MicroDMAis not bus master and is performing a window access, the 'iTRsignal for the
requested window channd should be asserted when the lAS signal is asserted. If:a MicroDMA
register access is to be performed, the IREG signal should be asserted at this time.
5. The bus master asserts the iDBE line which can be used to control the IDAL line transceivers,
transfers data onto the IDAL lines, and asserts the IDS signal to indicate that the data is valid.
6. If the slave can accept valid data within the minimum write cycletime, it asserts the IRDY signal
at the first sample window after the assertion of the lAS line and latches the data when the DS
signal is deasserted. If the slave cannot accept the data during this time, the master waits four
clock periods and samples the IRDY line again. This sequence continues every four periods of
the eLK! signal until the IRDY signal is asserted. If a bus error occurs, the external logic or the
bus slave responds by asserting the !ERR signal and the bus master must then process the error.
The current bus cycle is completed when theIRDYorIERR signal is asserted.
7. The bus master deasserts the ii'5S signal to indicate that it will remove the data from the IDAL
lines and deasserts the lAS and IDBE signals to end the bus cycle.
I/O Bus DMA Cycle
This cycle is used to force the bus master to rdease control of the IDAL lines and control signals to
another I/O bus device. The sequence of events follows:
1. A device requests the use of the I/O bus from the bus master by asserting the IDMR signal.
2. If the bus master is not performing a locked read cycle, it responds to the assertion of IDMR by
releasing the IDAL<31:00>, lAS, IDS, IDBE, IWR, and IBM < 3:0> lines.
3. The bus master asserts the IDMG line to release control of the bus and to grant the useo£ the bus
to the requesting device.
4. One or more read or write cycles occur on the bus between the requesting device (the new bus
master) and its slave.
5. When the requesting device has finished with the bus, it deasserts the 'fi5MR signal to return
control of the bus to the original bus master.
6. The bus master deasserts the IDMG signal and resumes operation on the bus .
• Specifications
The mechanical, electrical, and environmental characteristics and specifications for the
MicroDMA are described in the following paragraphs. The test conditions for the dectrical values
are as follows unless specified otherwise .
• Temperature: 70°C
• VOD=4.75V, Vss=OV
Meclumica1 Configwation
The physical dimensions of the 133-pin package are contained in Appendix E.
1-152
Confidential and Proprietary
Preliminary
Absolute Maximum Ratings
Sttesse8'gttater thal'1 the absolute maximum ratings may cause permanent damage to the devlce,~
Exposure to the absolute' maximum ratings for extended" periods may adversely affect the
reliability of the device. The functional operation of the device at these or other conditions greater
than indicated is not defined.
• Power supply voltage (Voo): -0.5 V to 5.5 V
• Input or output vOltage applied: V ss -0.3 V toVDO 0.3 V
• Storage temperature (Ts): -55°(; to 125°C
• Relative humidity: 10% to 95% (noncondensing)
Reeommended Operating Conditions
• Power supply voltage (V00): 5 V ± 5%
• Supply current (Icc) : 500 rnA (maximum)
de ~ Cl.traCter;sdcs
The dc electrical characteriStics of the MicroVAX 78532 for 'the' operating voltage !:Indtemperature
ranges specified are listed in 'Dahle 21.
.
"' ,
v
'2;0
Hjgh-level
itlput voltage
Low-level
0.8
V
input voltage
High.level
output voltage
.Low-lerel
output voltage
Low·level
output open-drain
I;,H ... 4()OiLA
CL = lOOpF
v
~=2,OmA
C~;=100pF
v.
IoL=U5mA,
CL =100 pF
voltage*
illY, ERR DMR,
lRA<3:0»
Confidential and Proprietary
1-153
---------------------------------~--~---"
maDI8
Preliminary
MicroVAX 78'32
Requiemet1tl1
Mm.
Max.
Symbol
Parameter
Test Condition
Iu
Input leakage
current
OMR signal is sampled at every I/O bus microcycle.
Clock Input Timing
Figure 29 shows the timing specifications for the clock input (CLKI) signal and Table 22 lists the
timing parameters indicated in the diagram.
Figure 29. Mim>VAX 78.5J2CLKI Timing Wave/orm
Clock input fall time
4.5
Clock input high
8.0
Clock input low
8.0
Clock period
25
Clock input rise time
50
4.5
Coo,fidentia1,and Proprietary
------------
-.----.."------~-----.-----------------------
. -.......-.- ...
-.
Preliminary .
MicroVAX;1s532.
MicroVAX Bus Read arid Write Cycles
Figure 30 shOWs the MieroVAXbus ,mastet read CYcletitning!U1dFigureJl showsthe MicroVAXb\ls
,master write cycletitning, TaI:>le 23 defines the read and write cycle tilllingparameters.
IClKO
DAL<31:0> _ _ _ _oJ'
C5<2:0>
¢~§~)-..,;------1~~!§~~tt--------
-----,....--i-t--...;,...;------+----..:or'-----
BM<3:0>
Figure 30· MicroVAX 78532 MicroVAX Bus Master Ret:tdCycle Timing
Confidential and Proprietary
DAl<31:0>
CS<2:0>
-----.../lJ...!~!!!:~,.....----.....;..;....-----"""f,----
- ......................,
Figure 3l.~ MjcroVAX 78512 MtcmVAX Bus'MtJ$tl!rW'rite Cycle)'iming
Symbol
SignaI'Definition'
tAAS
DAL < 31:0 > address setup time td. WS'IiSsertibrt'
tASA
DAL < 31:0 > address hold time after AS assertion
2P-15
t,uDIl
AS assertion to DBE and DS (read) assertion
3P-15
t,uDl
AS assertion to read data valid*
t,uDSO
AS assertion to I5S assertion (write)
t,um:
-
llP-30+8PS
5P-15
AS and DBE deassertion to busslave DAL<31:0>
three-state
tASH'&'
AS deassertion width
t ASLw
AS assertion width
3P+20
5P+20
2P-20
4P-25
12P-15+8PS
Confidential and 'Proprietary
1·157
MicroVAX'15l2
Symbol ·De£ioition
Requirements (ns)
Min.
•
tARB
•
Max.
J
~ assertion to beginning of ltiSY and 'ERR sample
window
6P - 45 + 8PS
t AsWIl
AS assertion to end of RDY and ERR sample window . 6P + 10 + 8PS
tASWII
WRfBM < 3:0 > les < 1> hold time from AS
P - 20
deassertion
t.w.s
BM < 3:0 > setup time before AS assertion
2P - 25
tDBLW
DBE assertion width
9P-20+SPS
tDOllS
DAL < 31:0 > write data setup time to D'S assertion
3P-30
D'S4eassertion to AS and Dill'! deassertion
P-15
DAL < 31:0 > read data hold time after DS
deassertion
o
tosm
~assertiontoDAL<31:0> read data valid
SP-35+SPS
t DSOO
DAL<31:0> writedataholdtimefrom'i:5S
deassertion
3P-20
DS deassertion to bus slave DAL< 31:0 > three-state
3P-20
tosoz
on¥ bUs cycles
tOSHW
DS deassertion width (read)
SP - 50
tOSLWI
~ assertion width (read)
8P - 20 + SPS
t DSLWO
DS assertion width (write)
6P - 20 + 8PS
tWI!DI
RDY internal sample window end to DAL<31:0>
read data vatid
tWIIAS
WR and es < 1> setup time before AS assertion
*Read data is valid if tASDI or tIlSDI conditions are satisfied.
1-158
Confidential and Proprietary
5P-:25
3P - 35
Preliminary
MicroVA.X78")3
Figure 32 shows the MicroVAX bus slave read cycle timing and Figure 33 shows the MicroVAX bus
slave write cycle timing. Thble 24 lists the timing parameters.
IClKO
DAL<31:0>
===:::)(~~~~--:------4t=~§:~~Pr-----
tS<2:0> -
.....---I-----+"Ii"'-----
.....-~.,....--++----
Figure 32· MicrovAX 78532 MicroVAX Bus Slave Read Cycle Timing
Confidential arid Proprietary
...
Preliminary
IClK0
DAl<31:0>
CS<2:0>
---------'.~~~~,--------~~--------~~-------
______-J,.__-++-______________
~
____
~.'----------
Figure 33· MicroVAX 78532 MicroVAX Bus Slave Write Cycle Timing
.'l8hle 24 • MicroVAX 785.32 Bus Slave Read and Write Cyde Timin,g Parameters
Symbol Signal Definition
Requirements (ns)
Max.
Min..
tAIIE
AS assertion to RDY/ERR assertion for MicroDMA
bus-slave cycles
"
*
t ASDSR
Required AS assertion to DS assertion delay (read
cycles)
3P-20
3P+25
AS assertion to OS assertion delay (write 5P-20
5P+25
tASDSW
Required
cycles)
tASH
AS deassertion width
tASlII!
AS deassertion to RDY/ERR deassertion
t BMS
BM <
tDDHll
t Dnmv
1-160
2P+25
31:00 > setup time before AS assertion
OAL<31:00> data hold time after OS deassertion
(slave reads)
100
2P-25
0
Required DAL < .31:00 > hold time after OS deasser- 35
tion on MicroOMA bus-slave writes
Confidential and. Proprietary
-
Preliminary
Symbol Sipal DeSnition
tDDSW
Requirements (nil)
Min.
Max.
Required DAL<31:00> setup time before m deas- 20
serrion on MicroDMA bus-slave writes
tosASS
Required 00 deassertio,n to:ASdeassertion delay
tosos
mdeassertion to DAL < 31:00> three-state
tHDA
Required DAL < 31:00 > hold timeafter.E assertion 35
P-20
55
RDY assertion to DAL<31:00> data valid fof -
35
MicroDMA bus-slave reads
Required DAL<31:00>
assertion
t1f1lH
setup
time before AS
15
WR/BM< 31:00>/CS <2:0> hold time after AS
P-25
deasserrion
tftS
WR/CS<2:0> setup time before :AS assertion
time depends on the system configutation.
transfer, etc.)
.
*tAlUl
3P-50
(memory speed, number of cycle slips, type of
Figure 34 shows the MicroVAX bus signal timing for the DMA cycle and able 25 lists the
MicroVAX bus DMA cycle titnin,g parameters ..
ICLKO
.\.,s
5S
15
£T
N
it
II..
u
-
DAL<31 :0>
-
'OCNO
l-
JJ
i---
{(
'OAWE
-I
"
t='OOOT
(
s~
J5
--0
'DVWE
M"
Figure)4. MicroVAX 78532 MicroVAX Bus DMA Cycle Timing
Confidential and Proprietary
1-161
-
MicroVAX 785)2
Preliminary
IClKO
iAKEi~.
-'AAEO ______ '-+-t:=-.
twEl-O
::1-.
__________
\
~
BUlll!lnd OMA A$serted by Another Device
'CLI(O
5iiiGi ----.,.
\Io..4-L-'DWE-O\"----"-_-______
Mk;roDMA Not Using
BuB
ICLKO
0Miii
DMGO
-----J ~ooF---.
MicroOMA Was Not Using Bus
IClKO~~
~~
~~~'----No Interrupt Pending for MicroOMA
Figure 34· MicroVAX 78532 MicroVAX Bus DMA Cycle Timing (Continued)
1-162
Confidential and Proprietary
Preliminary
Reqll~(ns)
Symbol Signal Defiqitioo
Min.
tAllG
tDCND
2H'7"". 25
AS and OBE deassertion to DMGO,a&Sertion
End of DMGI s~ewindo~ to AS ~~n
request pending for MicroDMA)
Max.
(P¥A:;"
Deassert DMR to 'AS/DSIV/t[/CS< 1 > !DBE(--
BM<3:0> three-state
DeaSsert DMR to DAt < 3i:oo;:J'three-state .
lOP+20+4Pl{"
3P+25
P+20
2P+33
End ofDMm sample wirldOw to ~usertion(n()
DMA request ~JorMicroDMA)
Deassert DYGI to 'i5M(jO deassert
tWEro
0
IAKE! sample window end to IA'K&) asserts
:?P+.30
60
2P+30
*K =the number of microcycles (0, 1, 2, .3. 4) that the sequencer is busy.
MicmVAX Bus Genentl Tuning
Figure 35 shows the general signals for the MicroVAX bus timing and Table 26 lists the general
timing signal parameters.
ICLKO
ROY. ERR
---------+---"\1
Figure 35 • MicroVAX 78532 MicroVAX Bus General Signal Timing
Confidential· and Proprietary
1-163
-
MicroVAX78S12
Symbol SignatDe6nition:·'
RequitementS'(ns)
Min.
Max:.
ICLKO to beginning of AS sample window
ICLKO to end of AS sample window
-35
JP+5
ICLKO to beginning of IiDCK sample window
ICLKO to end of IWCK sample window
tlLWE
tsWB
-50
.
5
ICLKO to beginning. of CSL/Vl3R/DMGI/IAKEI sample window
3P-50
,
tSWll
ICLKO to end of CSr:tVBR/DMGi/iAKEi sample 3P+5
window
ICLKO to ER'R/R'DY assertion
1·164
Col'lfidential and Proprietary
3P-5
3P+26 .
MicroVAX1M32
I/O Bus M8itet.~ and 'Write ~ycles
Figures 36 and 37 are tim.ing qiagrams for the I/O bus maste,r read and write cycles, respectively.
Table.271isis thesytnp<'>ls and PQta11leters for the timing sigrwls.
Figure 36 • MicroVAX 78532 I/O Bus Master ~ad Cycle Timing
1·165
Preliminary
MicroVAX18.532"
ICLKO
. . . . . . . . . .; .;.;.;.;:.;. -.................- - i.........-
IDAL<31:0> - - - - -..... 'I'I-~~iOoIIf.,...---
...........;
IBM<3:0>
Figure37 • MicroVAX 78532 I/O Bus Master Write C'Y,c/e Timing
Symbol Signal Definition
Requirements (ns)
Min.
IDAL < 31:00 > address setup time to IAS assertion
m assertion
tL\SA
IDAL< 31:00 > address hold time after
tIASDB
m assertion to IDBE and IDS (read) assertion
2P-28
2P-15
3P-15
iAS assertion to read data valid
t IASD50
IAS assertion to 'iDS assertion (write)
Max.
3P+20
llP-30+4PS
5P-15
IAS and IDBE deassertion to bus slave IDA-
5P+20
2P-20
L<31:00> three-state
4P-25
IAS deassertion width
12P-15+4PS -
lAS assertion width
lAS assertion to beginning of IERRjiRiSY/IDMR
sample window
1-166
Confidential and Proprietary
6P-45+4PS
Preliminary
Symbol SignalDe6nition
t lASWE
Requirements (os)
Min.
Max.
lAS assertion to end of IRDY/IERR/IDMR sample
6P+ lO+4PS -
window
t lASBM
mM < 3:0 > hold time £tom lAS assertion·
3P-20
P-20
tl8MAS
IBM < 3:0 > seruptime. before iAS assertion
tlDBLW
IDBE·assertion width
tlOODS
IDAL < 31:00> write data setup time to iDS assertion) 3P- 30
tlDSD
tlDSDI
tlDSDO
tlDSDZ
IDAL < 31:00 > read data hold time after iDS
deassertion
pc-: 25
0
SP - .3;5 + 4 PS
iDS assertion to IDAL <31:00 > teaddltta valid
IDAL<.31:00> write data hold time £tom iDS
deassertion
3F-20
iDSdeassertion to bus slave IDAL~31:0Q> ~
sta.teonread bus cycles
tlDSHW
IDS dea&sertion width (read)
tIDSLWI
IDS assertion width (read)
tIWEOl
IRDY internal sample window end to IDAL < 31:00 >
read data valid
t IWIIAS
IWR setup time before lAS assertion
.3P-20
8P-20+4PS -
5P - 25
3P - 35
Confidential and Proprietary
_ _ _ _ _ _......_ _ _ _......._
......_,..u_"~...
__
m_ _ _ _ _ _ _ _ _ _ _ _ _ _ •
·1-167
_~_, _ _ _ _ ,___ _
...
I/O Bus Slave Read. and Wq~Cycl.es
. ... ....
. ..... .
Figures.38 aJ;ldJ9 are timlng~ms for the I/O bus slave read and writecycies, respectively.1able
28 lists the as~ated timing pal-ameters.
ICLKO
DAL<31:0>====:)(~~~)------"""~~~~~~-----""
lAS
IDS
Figure 38· MicroVAX 78532 I/O Bus Slave Read Cycle Timing
1·168
Confidential and Proprietary
IDAl<31:0>
IBM<3:0>
------
----
Figure 39· MicroVAX 78532 I/O Bus Slave Write Cycle Timing
Symbol Sipal Definition
RequDements(ns)
Min.
tIASDIIIt
tWiDSW
Required lAS assertion to
cycles)
'IDS .assertiondelay (tead }P""20
Required lAS assertion to ms assertion delay (write
cycles)
.
5P - 20
tWl>mv
tWI>SW
tlDSASS
5P+25
2P+25
lAS deaSsertion to I1IDY~ deassertion
tWI>HIt
3P+25
.
lAS deassertion width
t UIMS
Max.
UiM < 3:0 > setup time before lAS assertion
100
P - 25
IDAL<31:00> data hQld timeafteriQS' de~~rtion 0
(slave reads)
Required IDAL< 31:00 > hold time after II)S deas). 35
sertion on MicroDMA bus-slave writes
Required IDAL< 31:00 > setup time before TI5S deas- 20
serrion on MicroDMA bus-slave writes
Required i'i)S deassertion to lAS deassertion delay
Confidential and Proprietary
P - 20
1-169
...
MicroVAX 785}2
Symbol Signal Definition
Requirements (ns)
Min.
t msDs
IDS deassertion to IDAL < 31:00> three-state
tnmA
Required IDAL < 31:00 > hold time after lAS assertion 35
55
IRDY assertion to IDAL< 31:00> data valid for
MicroDMA bus-slave reads
tlRDR
Max.
P+35
tImA
Required IDAL< 31:00 > setup time before
assertion
t lWm
iWR/IBM<3:0> hold time after lAS deassertion
P-25
tlWRS
IWR setup time before lAS assertion
3P-50
lAS
15
I/O Bus DMA Cycle
Figure 40 is a timing diagram for the I/O bus DMA cycle. Thble 29 lists I/O bus.DMA cycle timing
parameters.
leLKO
. ~ '1AllD
f--
-. Ir-'IAOC
~===========~~~~~~~----------------r:::::=
~
iAS.i6BI
-------'
~ASG
--
\
551----------'------
IMASTER IS ASSERTED
ICLKO~~
iDMll~J
.
~~~~
:==============================~S~5~~Z~~~~~===A=.·r}:-~-~--IMASTER IS OEASSERTED
Figure 40· MicroVAX 78532 I/O Bus DMA Cycle Timing
1-170
Confidential and Proprietary
Symbol SipalDe6nition
Requiremebts(tu)
Min.
Max.
····40
Assert Il'»l(j to iAS,IU5J~/IBM<:3:0>
three-state
twx:
IDAL<: 31:00 > three-state to assert ~
tlAJ)D
tLUG
2P+5
Asserted IDMR (internal) sample windPw., end,to,'~J?,
.*
4P-25
iAS and IDBE deassertion tolf5MG assertion
Asserted iIlMC:i (internal) sample window end to m -
10P+35+4Pl(t
'iiS'&IG assertion
t IDAS
.
.
'.
assertion
Asserted "ImYie' (internal) sample Wittdowend to IBM Ilsrertiori'
.
tJDBM
tUlCND
tJDDDT
Deassert IDMR to iAS/Ii5S~IBM <: 3:0>
three-state
3P+35
Deassert mm to IDAL <31~OO > three-state
P+:30
Deasserted IDMR (internal) sample window end to ,,~
~~~
*Maximumvalue determfueby latency specificanom.
tK == The number ofmicroc.ydes(O, 1.2,3, 414tat~~u~~busy,
JlOBus~Request
,.',',," ','
','
, ". ", ,"
2P+40
"". ..:
Figure 41 shows tbeJlQ'llus ttlmSfer~uest~ ~)~n4 $b&)~lit!lt;~~ng parameters.
ICLKO
----'l
iTR<3:O>--------.
1~~=======_t_ITIIA_5S...._;.;-_~-. ._:..-~. __:...-It=- .:=:j
lAS _ _ _ _ _ _ _
Figure 41 • MicroVAX 785321/0 Bus Tmtts/tr.&quest Timing
Confidential: and Proprietary
1-171
-
Preliminary ""
Symbol Sign_Definition
R.equftments(hs)
Min.
Max.
ITR < 3:0> assertion to m asserti6nror requestmg
channel
25P+30+4PK*
m
assertion to ITR < 3:0 > deassertion to assure
present requested"bus cycle is last of ITRrequested
bus cycles (MicroDMA is bus master)
6P..;.35+4PS
"K= The number of microcycles (0, 1, 2, 3, 4) that the sequencer is busy.
I/O Bus General Signal Timing
.
Figure 42 shows the general timing forthe I/O bus signals. Table 31 lists 1/0 bus general signal
timing parameters which include sample windows times for the asynchronous signals.
ICLKO~:
lAS
ITR<3:0>
IREG
IIR<3:0>
SAMPLE WINDOWS FORASYNCH.RONOUs SIGNALS
ICLK°----JI
\
I
tl_AS_PH_~_"~
~~
______
lAS
IRO¥
•
r- """
\'---_
~
--"'--------.......-'----'-_'____----\!===-+--\_
~~~
T!ffiR
DRIVE TIMES
Figure 42· MicroVAX 78532 liD Bus General Signal Timing
1-172
Confidential and Proprietary
_.
Pte.liminary
'fabIe}l-;MicroVAX 78'32 I/O Bus General Timing Parameters
Symbol SipaJ Definitioo
ReqUire1nents(ns)
Min. .
ICLKOto
m asserted·
P-12
ICLKO to begjnnjng ofWsample window
ICLKO.!oe~.?fiASsamplewindow
Max.
P+25
-35
3P+5
trowB
ICLKO t6~~iitDY~ple w~dO\V ~P+5
end..,"·'
tlR'B
ICLKOtobepmingofITR1tREG ~;
window
.
.. .
.
ICLKO to end of :rni <3:0 >- sample wfudoW
ICLKO to iERR/Iiill'Y assertion
50
P +5
3P+26
• Interfacing Requir¢!Jle1lts
MicroDMA interface designs vary depending on the type of peripherals being interfaced. Figure'4i3
is a simplified example of a typical interface application. The MicroDMA is used as an interface
between the MicroVAX CPU and an 8-bit peripheral chip similar to an Intel* device.
*Intel is a trademark of Intel Corporation.
An address latcb and decoder enables the MicroDMA and other devices on the MicroVAX bus. If
more than one device on the MicroVAX bus can respond to a DMA or an interrupt acknowledge in
cycle, the devices are connected as a daisychain as shown. The peripheral chip has separate read and
write controls. The assertion of the IWR and iI5S lines indicates that a write operation is required.
The assertion of the IDS signal without the IWR being asserted indicates that a read operation is
required. The peripheral interface includes buffers 'for the IDAL data and addresses, and a decoder
for asserting signals such as DACK (a DMA data transfer acknowledgment signal), ~ (a peripheral
chip select signal), and peripheral chip register addressing signals.·The !MASTER signal is asserted
(MicroDMA is the default master of the I/O bus) and the IDMR signal is deasserted so that another
device cannot request control of the I/O bus.
Timing for the interfa(:e is from a common 40-MHz clock. The timing logic used depends on the
type of peripheral chip(s) being interfaced and determines when an I/O bus cycle can be terminated
and when IRDY line should be asserted. All the chips are reset by common reset circuit.
1-173
.-
Preliminary
~
ilM1l
CS<2>
i51ifH:
iiM'<'3':'O'>
I
ICS
I m mwm
rnTIIIII1TOIFROMOTHER
MICROVAX
DEI/ICES
TO OTHER
DEVICES IN
DAISY CHAIN
B!§\ASI
DAl<31 :00>
~
ffip..----'
ORO
INT
s·sn PERIPHERAL CINTEl)
DEVICE INTERfACE
SIGNALS
Figure 4,3 • MicroVAX 78532
1-174
Typical MicroDMA Inter/acing
Confidential and Proprietary
aus
• Featul'es
• Compatible with the MicroVAX 78032 CPU
• Supports battery backup refresh
• 32-bit memory data organization
• Suppo~ pa#ty erJ;Qr reporting with address
capture
• Controls operation of 4 Mbytes of 256K by
I-bit dynamic RAMs
• Generates multip1exed address, RAS and
CAS signals for as many as four banks of
memory
• Two acceSs speeds for use with differentspeed dynamic RAMs
• Bus timeout error detection and reporting
• Generates 100-Hz interval dock
• Doubl~~~ CM()~t~ology
• Minimum parts count memory interface
• Four refresh modes
• Description
The MicroVAX 78584 Dynamic Ram Controller (DYRC) provides a low cost interface between the
MicroVAX 78032 CPU and 4 Mbytes of dynamic RAM (DRAM). The DYRCsupports 256Kl>y I-bit
DRAMs and supplies mcltiplexed address, timing strobes, and refresh/access arbitrationoontfQl.
Two operating speeds allow the designer to use different speed DRAMs. The choice ot speed
determines whether memory errors are reported during the same cycle or iii following cycle. Error
address capture logic is implemented in the PYRC.to aid in the reporting of memory errors. The
DYRC also provides battery backup refresh suppqlt.r~ lOQ-Hz interval timer, and bus timeQut logic
to report nonexistent addresses or no response to the address strobe. Figure 1 is a block diagram of
the MicroVAX 78584 DYRC'
AOWAPOAfSS
Figure 1 • MicroVAX 78584 DYRC Block Diagram
ConfidelltW and Proprietary
1-175
Using the DYRC results ina triininl'*m part count 32·bit DRAM memory interface that requires a
single 5-Vdc supply and is compatible with the MicroVAX 78032 CPU .
. Pin and Signal Description
This· section provides a description of the input and output signals and power and ground
connections used by the MicroVAX78584DYRC. The signal pin assignments are shown in Figure 2
and summarized in Table 1.
VPARITY ~ FlEFSElO
RINPRG
20MHZ
VSS
EAS(j
7&
53
BSl
CAS1
76
52
BSO
CAS2
77
51
NC
CAS3
78
50
NC
SPARE
79
49
NC
DALO
DA1l9
DAl1
DAlfs
ADS
ADO
DAL2
vss
MicroVAX 78584
DYNAMIC RAM
VOD
CONTROLLER
DAL3
45
DAL17
44
DALl6
43
VDD
42
VSS
ADI
3
41
AD7
DAl4
4
40
DAL15
DALS
5
39
DAL14
AD2
6
38
ADS
37
DAL13
DAL6
DAL7
8
36
DAU2
AD3
9
35
ADS
DALS
10
34
DUTENB
DAL9
11
33
i5iiE
DALl 0
INTTIM
8M1
8M3
vss
elKI
Figure 2· MicroVAX 78584 Pin Assignments
1-176
Confidential and Proprietary
CS1
ENBTMR
Preliminary
Pin
Signal,
48,47,45,44, DAL<19:00>
40,39,37,36,
14,13,11,10,
8,7,5,4,2,83
Input/Output
Function{Definition
input/output
Data address lines < 19:00>-During the
address pottion of a memory cycle, the
address on DAL < 19:02> is used to form the
row and column addresses.
The D~$15:00> lines. are used for ~
transfer of information to and from the commandstatusand faultaddt'ess registers.
66
SLOW
milut
Slow-MatJbes the operating speed of the
DYRC with the speed of slower memory chips.
45
SELEC'r
input
Select-,Sel.eds the'chip£or,~memory acce~s
cycle.
'
61
~
input
Register lie:lect-Selectstl(,:CeSs to the two
internal registers.
62
CSR
input
Comma~d,,' status regis.t~ select-Selects
which ohhe two internarregJ.sters is to be
accessed.
57
AS
input
Addres~strdbe-A stro&; ~rom the CPU that
latches, address aoocontrol information into
the DYRC and starts a RAM access cycle if the
SELECT signal is asserted or an internal register ac~es~ if,the as'~ ~~erted.
;
" , 'r '. ,',
~'
"
,'
28-30
(:5.<2:0>
input
Control status-Determines the type of bus
cycle to be performed.
19-16
BM<3:0>
input
Byte m,asks-Selects the,'byte(s) to b~
accessed.
53,52
BS<1:0>
input
Bank se~--Se1ects the 'haa:lk of memory to
be accessed.
46,41,38,35
12,9,6,3,82
AD<8:0>
output
Address <8;O>-Providesthe multiplexed
memory~dress to theAA¥ array.
59,58,56,55
RAS<3:0>
output
Row address strobe-Strobe signa1s used to
latch the row address into the meOlOry bank
selectedbv,,BS < 1:0 >.,
78-75
CAS<3:0>
output
Column address strobe-Strobe signals used
to latch the CQlumn address into the byte(s) of
the memory array selected by BM < 3:0 > .
output
Ready-Synchronizes the data transfers.
input
Outputenable--o;.Enables the DYNe outputs.
24
34
OUTENB
Confidential and Proprietary
JtI1lll''''''''''''''_''''''''
___'_llIif1o_P._'_________
1117_ _ _ _ _ _,
......
__
«&4QW_ik~!l!llIll1""~_ ~
1-177
Pin
-
Signal
Inpttt/Outp1:Jt
Function/Definition.
26
WR
input
Writ;e..,....Indicates the direction of data transfer on the DAL < 19:00 > lines.
33
DBE
input
Data buffer enable-Enables the three-state
DAL < 19:00> lines drivers during an internal register read.
70,69
REFSEL< 1:0 > input
Refresh select-Select one of four refresh
modes.
27
EPS
input
External processor strobe-Provides a refresh
request· synchronization for processors that
use external processor cycles.
68
RRQST
input
Refresh request-Used by external logic to
request a refresh cycle.
67
RINPRG
output
Refresh in progress-Indicates that a refresh
cycle is in progress.
31
ENBTMR
input
Enable timeout timer-Enables the bus
timeout function.
74
PARIN
input
Parity in-Used by external logic to report a
parity error to the DYRC.
25
ERR
output
Error-Indicates a parity error or bus timeout
condition to the CPU.
73
VPARITY
output
Valid parity-For use by diagnostics to verify
the operation of parity logic by forcing it to
write a wrong parity.
32
DV
output
Data valid-Indicates that the data being
written to or read from memory is valid.
23
CLKI
input
Clock input-A clock input that provides
timing for the DYRC and synchronization
with the CPU.
65
20MHZ
input
20 MHz-An optional clock input for generating 100-Hz internal timing and bus timeout
timing.
71
INCLKSEL
input
Internal dock select-Selects the clock source
to be used for generating internal timing and
bus timeout timing.
15
INTTIM
output
Internal timer-A lOO-Hz clock that can be
used to support operating system timing functions.
1·178
Preliminary
MicroVA¥·1SJIJ4
Confidential and Proprietary
Pin
Signal
60
input
Powerfail-Continues memory refresh opera..
tion during a powerfail conditicm when
refresh mode 0 or 1 is selected and memory .
~b~t~ry backup.
20
input
Reset.-.;..;Sets the 'nYRC to a known initial
state.
1,22,43,64
Voo
input
21,42,63,84
Vss
input
Gtound........Grounclrefere:t)(;le.
input
Input and Output Signals
.........
Data address lines (DAL < 19:00 > )-These lines . ~~sed ~. form the multiprexed address for th~
256K dynamic memory chips and to transfer infortl1atio~;t)etwtren the CPU and the two internlll
registers. During a memory read or write t}'cle, litl~s 0At;<19:02 > are latched into the DYRC by
the assertion of the ~input.The multiplexed row
coIumn address i$Jormed from this
information. Lines DAL< 19, 17, 15, 13, 11,09,07,05,03> areusedtocfotmthe·9-bitroilradd:ress
and linesDAL< 18,16,14,12,10,08,06,04,02> are used to form the9-bitcolumn address. The
DAL < 15:00 > lines are used to transfer information between the two internal registers and the
CPU. .Access to the internal registers is controlled by the RS and CSR inpu!~:
.
and
Input Signals
. ,.
Select (SELECT)-This signal, when aSserted by eitetnaladt:fteSs decode logiC,enables amemoty
access cycle when the AS signal is asserted. TheCAS,
nv.
RAS<3:0>, CAS<3:0> , DAL< 15:00>, 'im?,
ill"&PRG,l!RR, IN"fTIM, and VPARITY.lf
the OUTENB input is not asserted, these outputs are .~~nce.
Address strobe (AS)-This signal, when asserted, latch~ t~p~i < 19:02> and BS < 1:0> line
information into the DYRC. The assertion of the AS btPUt~s a memory ~ecess t}'Cle if the
SELECT input is asserted or an internal register access cycle it the RS input is asserted. The AS
inputis also used to internally synchronize the refresh logic. '
External processor strobe (EPS)-This signal and the AS and SELECT signals
internally synchronize the refresh logic.
are
used
to
Control status lines (CS < 2:0 > )-These signals are decoded by the DYRC with the WR input to
monitor the type of bus t}'cle being performed. Table 2 lists the bus t}'cle assignments and indicates
if a memory access is allowed for the cycle selected.
1·179
MicroVAX78584
Preliminary
TaMe"2·MietOVAX~78'84 Bus
WR
CSlJne*
2
BusC,cle Type
1
0
H
L
L
L
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
L
L
H
L
H
L
L
L
L
L
L
L
H
L
H
H
L
L.
H
L
H
H
L
L
L
L
CYcle Assignments
L
H
H
L
H
H
L
H
Memory
Access
reserved
reserved
reserved
interrupt acknowledge
read (instruction)
read lock
read (data, modify intent)
read (data, no modify intent)
No
No
No
No
Yes
Yes
Yes
Yes
reserved
reserved
reserved
reserved
reserved
write unlock
reserved
write (data)
No
No
No
No
No
Yes
No
Yes
*H =high level, L=low level.
Byte masks (BM < 3:0 > )-These signals are used to generate the information on the CAS < 3 :0 >
outputs. During a memory read or write cycle, the byte mask BM < 3:0 > lines that are asserted
result in the corresponding CAS <3:0 > line being asserted.
.
Bank select (BS < 1:0> )-These signals select one of the four banks of memory for access. by
selecting the RAS line to be asserted as described in Table J.
Table .3 • MicroVAX 78;84 Bank Select Decoding
BS Line·
RASLine
1
0
L
L
H
H
L
H
L
H
RAS
RAS
RAS<2>
RAS<3>
*H =high .level, L =low level.
1-180
Confidential and Proprietary
Preliminary
ContrOl iltatustegisttr(CSR)-Thissignai is used with theRSinput t6·select the internidregisterto
be'aCcessed. When the~inputis aSserted, the control status register is selected. When theCSR
input is riot asserted, the fauluddress register is selected.
Write (WR)-This signal is used by the bYRc to detect a read or a wnte bus cycle.
nata buffet enable (DBE)'-:'1bis sigrtal is used With the RSsighai to enable fnethree-state
DAL < 15:00 > drivers when one of the interfialmgisterSis beingrrea )-These lines are ~.toRlect oneoftheiour ref~h lnodeS.
The DYRC selects the re~h . mOOewbett;>~~:~i'ppu;t;.is a&se~. Th~pinsshould·1.>e
connected to the proper voltage level. Thble 4 lists the refresh mode selections.
R,EFSJi:L l.ine
1
0
o
o
1.
1
0
o
1
0
1
2
1
J,
Refresh teqUeSt'(RRQST)~ Thj$'sjgnal is ,.•~~ .b)r. ext~~ic:~Q~tl~t~'memo~refi:esh
cycle. whenretm~ mode .2.i~ ~lecteP,. Ut~J:lYRC js.• ~~~ll8.ili;~~~.~~eQj .1. Br} . .lltld
signal is assert:ed,an extra refresh cycle
be~formed .•
trus.dOesnot have~ affect
on the refresh interVal;bec~~se ffic:int&nalc6~ntersof~ ~9 arefiqt·~ .. " ,.,' .t.·
Slow (SLOW)-This sign~ is~cltomat~ th~p~rat' '" ., ·~hhePY~C'witht&operi.ting
s~dof the DRAMSbelngijSed.~n assertea;the ..............•...• ~'Wi~tlir$·i.ncreakdaridthe
CAS < 3:0 > .and.RiJY signals aretldayecl, alloWing theDYKC' h5b!ius@WIth slower Dlti\1v1s. This
pin shoUld be connected toVDIl()!YU'
.
will
this
f1oWever,
Enable, timeout .·.timet· (EN1fHia)' .' When .aSseft(!4, '·this ~~tiliabl~~ .the bus titneaut. timer.
When enabled and the AS iriput has been asSerted' for 251lS,' t:h;\!!'·~c willas'sert the'mm Otlq,ut
to notify the CPU of an error. The CPU is then required to examine theCSR to determine tnecause
of the error. This pit, shotlld be connei:ted:ft5:VDD or V~li; '.'
Parity in (PARIN)-This signal is assertedbyexternalparitychecking 10gicwh~1'l apanby errorha&
occurred. If this signal isoot',used, it· shoutd'be coonecte(VroVDD'throUgh ari'e:x:temalpullup
resistor.
ClOck input (CLKI);";';This is the input clock that ptovidesthebwic timinS'refcremee forthe·DYRC.
20 MHz (20MHZ)-This clock is used to generate the l00~HziNfflM output and the 25 I.lS bus
timeout timer if selected by the INCLKSEL input.
"
Internal clock select (INCLKSEL)-This signal selects the clock source to be used to generate the
IOO-Hz INTIIM output and 25-1JI!! bus timeout timer:. When the INCLKSEL signal is asserted, the
CLK! divided by two is selected as the dock source. When the INcLKSEL signal is deasserted, the
20MHZ input is selected as the dock source. This pin should be connected to VDO or V5S'
Confid¢ntial and Proprietary
1-181
...
·Preliminary
MicroVAX7eS4
10m
PowerfaiI (PFAiL)-This~na1isasse~~ by external
to notify t~DYR<::.pf a system power
failute and that the DYRC is to continue refreshing memQry foo lIl ab~ckuppower source. This
signal is functional in refresh modes 0 or 1 only. When thF: DYRC is used without a backup power
source, the PFAIL input must l:>e pulled up by an external resistor.
Reset (RESET)-This line is asserted to set the DYRC to a known state.
Voltage (VDD)-Connects to the power supply voltage.
Ground (Vss)-Connects to the ground refet'¢hce.
Test (TEST)-Resetved for manufacturing use. This pin must be connected to V DD .
Output Signals
Address (AD < 8:0 > )-These are the multiplexed memory address outputs. When the selected
RAS < 3:0 > output is asserted, these lines contain the row address for the DRAMs. When the
selected CAS < 3:0> output.or outputs are aSserted, lines AD <.8:0 > contain the column address
for the DRAMs. These outputs cannot drive the DRAMs direcdy. Therefore a memory driver is
required between these lines and the memory array. Each line is capable of driving up to four
memory driver inputs.
Row address strobe
(·=RA,.....,..S-<,....3.....,:0~>,....)-These signals are used to latch the row address into the
selected bank of memory. The RAS<3:0> line or lines to be asserted are selected by the
BS < 1:0> inputs or by the refresh logic. The RAZ < 3:0> outputs cannot direcdy drive the
DRAMs. A memory driver is required between these lines and the memory array. Each line is
capable of driving up to four memory driver inputs.
.
Column address strobe (CAS < 3:0> )-These signals are used to latch the column address into the
selected byte(s) of the memory array. The lines to be asserted are selected by the BM < 3:0> inputs.
'these outputs cannot drive the DRAMs directly. Therefore a memory driver is required between
these lin~s and the memory array. Each line is capable of driving up to foUr memory driver inputs.
Ready (IIDY)- This signal is asserted to notify the controlling processor that the current memory
access bus cycle or internal register data transfer bus cycle can be completed.
.
Data valid (DV)-This· signal is asserted by the DYRC to notify the external error detection and
correction IQgic that the data being read from or written to memory is stable.
Enor (ERR)- This signal is asserted by the DYRC to notify the CPU that the parity checking logic
has reported a parity error to the DYRC by asserting the PARIN signal or that a bus. timeout
condition has occurred. When there is more than one DYRC ina system, only one should report a
bus timeout.
Refresh in progress (RINPRG)-This signal is asserted to notify the eXtemallogic that a refresh
cycle is in progress.
Intervaltitner {trINLi.Ii'TTIM. ~)-A 100-Hz timer for use by the operating system.
Valid parity (VPARITY)-This signal can be used by diagnostics to verify the operation of the
external parity checking logic. This signal is controlled by the write wrong parity (WWP) bit in the
command status register. When VPARITY is asserted, the parity logic should function normally.
When deasserted, the parity should be inverted.
1-182
Confidential and Proprietary
....
• FunCtional Description
This section describes the basic operation and organization of the MicroVAX 78584 DYRC.
Memory OrganizatMln
.
The DYRG supports a .32"bit, byte Qriented,.memory dataorga~tion.. Because of the byte
orientation of the mernYsignal reqUired
for bus c.;ycle termination. The timing informa.tionJor a read or .~ite\Cyde is in the Specifictltiort
section.
A memory read orwriteCyclels initiated by the assertion 6fthe SEL~eTand AS signal~.If a
refresh request is not pending or in progress' the DYRC t,ral'!$,fersthe row ad~sson the memory
address bus and assert t~ RAS < 3:(5 >ouqmt as se1ectedbY~S< 1:0 >1l,neS . .After thesPecif~
row address hold time, the DYRC transfers the colUmn addtess' onto the' memory addreSs bus and
asserts the CAS <3:0> outputs as selected by the BM <310 >·lines.The DYRe asserts ·the lillY
signal to notify the CPU that'the current bus cyde cat:i'be Completed. The assertion oftheRl)Y line
is determined by the type of memoryc.;ycle (slow. or faSt) being performed. The data on the
DAL<31:0> lines i'sthedata·'to'·be written intiil1lr readfrom·tbe accessed DR.AMchips~TbeDV
signal is asserted to notify the external logic, such as parity or EDAC logic, that the data is valid.
The AS signal is deasser,ted and the memory access is comp1trted.. The DYl\<;: l,iIsesthe "early write"
mode of theDHAM fOl:' writing data into memory..
If a memoryteftesh is pending or in progress when the .D'ilRCili selected and the AS signal is:
asserted, the·memory access \Vill beddayed until the refresh cycle is oot:npleted. The MicroVAxbus
cycle is stretched by the delay of the aSSet'tion·tjf the RD'Y signal ft6m the DYRG.
RefresbOperation
The AS, SELECT, EPS, and PFAIL inputs are used by the DYRC to arbitrate a ref.-esh c.;yde. The
DYRe performs the arbitration and control for the refresh cycles that may be started by the
following:
• Detecting thed~ssertion of the AS signal whentheSELECThlgrihl is asserted. The D$Cknows
when the p~t as:;ertion of the AS signal will ocCur. This allbws time for the DYRC to arbitra,te
.
between a refreshc.;ycle and the next memory cycle.'
• Detecting the deassertion of BPS. TheDYl\Cwill perform the:necessary refresh cycles during the
execution of long floating-point instructions .
• Detecting the assertionof the As sisllarwhen the SELECT 017ErS are deas~ for an extended
period of time (62.5 \.IS maximum). Four consecutive rows will be refreshed during the refresh
cycle. This allows refresh c.;ycles to bepertormed while theCPU'is' commuriicating with sloW
peripheral devices.
..
Confidential and Proprietllry
-----------------------_._--_._--------------------------
1·183
I11III0
Preliminary
• At the assertion of the PFAIL signal. This condition inhibits memory accesses other thMrefresh
cycles. When the PFAIL signal is asserted, the aut~matic refresh occurs only when refresh mode 0
or 1 is selected and there is a badmp power sourc:e.· .
.
A refresh cycle consists of transferring the refresh address onto the memory address bus, asserting
the RAS< 3:0 > line information, and incrementing the refresh row address counter by 1 until four
rows have been refreshed. While a refresh cycle is in progress, the DYRC aSSerts the RINPRG signal.
The refresh cycle is completed when the RAS < 3:0 > lines and the RINPRG signal are deasserted.
Any· memory accesses attempted during· a refresh operation· are deferred until the refresh is
completed.
DMA devices that access memory controlled by the DYRC must consider the latency time that may
occur as a result of a refresh cycle. The DMA device can use RINPRG to detect a refresh cycle in
progress.
The four refresh modes that are selected by the REFSEL< 1:0> lines
refresh mode to be used is selected when the R:ESE'i" line is asserted.
are listed in Table 2.
The
.
ModeO-In this mode refresh operation is automatically controlled by the DYRC. The DYRC will
·refresh 256 consecu.tive locations in 4 ms when the clock input is.40 MH.z. During the powerup
sequence, the memory anay is initialized with eight refresh cycles before any access is permitted.
The RINPRG output will be asserted during refresh cycles.
Mode l.,.,-In this mode, refresh operation is automatically controlled by the DYRC. The DYRC will
refresh 512 consecutive locations in 4 ms when the dock input is 40 MHz or 256 consecutive
locations in 4 ms when it is 20 MHz. During powerup, the memory array is initialized with eight
refresh cycles before any access is permitted. The RINPRG output will be asserted during refresh
cycles.
Mode 2-1n this mode, refresh operation is controlled by external logic. The external logic
requests a refresh cycle by asserting the RRQST input. 'The DYRC arbitrates the refresh cycle,
asserts the RINPRG output, performs the four refresh cycles, and increments the·refresh counter.
The RINPRG output can be used to clear the RRQST signal. During the powerup sequence, the
memory array is initialized with eight refresh cycles before any access is permitted. Automatic
refresh is not performed after powerup.
Mode 3-1n this mode the refresh operation is disabled and no refresh will occur during the
powerup sequence.
Internal Registers
The, DYRC contains two 16-bit registers. The control and status register (CSR) is a read/write
register. that is used to transfer control and status information between the processor and the
DYRC. The fault address register (FAR) is a read-only register that is .used to store the addreSS of the
page in memory being accessed at the time a parity error is reported. Access to the CSRand FAR is
controlled by the RS;CSR, andWR inputs. TheRS input selects the DYRC for a register access, the
CSR input selects the register to be accessed, and the WR input determines whether a read or write
transaction is to be performed. The addresses for the CSRand FAR registers must be on a longword
boundary. Because these registers are 16 bits wide, they must be accessed using word instructIons.
Control Status Register-The control status register (~SR) enables parity errol; support, reports
parity a~d bus timeout status, and forces a wrong parity for diagnostic purposes. During the initiai
powerup sequence or at the assertion of the RESET input, this register is cleared. Figure· J shows
the CSR register format and Table 5 describes the function of each bit.
1-184
Confidential and Proprietary
.00
ERRSTAT \. ENB
WWP
,READ AS.Q';s
I.
I
BTO
Figure ;·MiCroVAX 87584 Control StatuS Ritgister Format··,
1abIe' • MicroVAX 81'84 Control Status Register Desc:riP:~.
Bit
15
14
Description
ERRSTAT (Error statUs)~ lrusbitis used to report 9~ity erroratid is set when the ENS
(bit 13) is set and the PA.RiN input is asserted. When set, this bit indicates that a parity
errol" has 1Jet!~ dete<.:ted.1?Ythe external parity logic, This bit is cleared when the CSR is
read or tbe~inputis4s$erteti<
WWP (Write wrong parity)-This bit is set and cleared by software.·Whenset, it causes
the VPARttYoul;put to be qeaSSetted:Wht;rt cleated~ the vPA:l(trY output is llsserted.
Can.beus. .ed. during
.........••....diQ.g. p. •.o• Stics
.... OperatlqnS.·;
.........to
..... ~
.•.~.,.'
.. .' input
()~.,ra. . istiOn.·.'of.
t.h.e exte
.. rnal parity
asserted.
:iT. '. . .
logic by forcing wrong.p~ty. Cle~ wl;1en the
?
13
J.:-
' j )
ENB (e~bl~h-' Tbtshit.is ,l,1Secl.to eAAblethenablethe
parity. error reporqngfiqiction of tlu{ !m:~C;~~ dearecito tliSablethe parity error
reporting
asserte(l. ~cti~n i.n~ the E.~~:rAT fl\lS,.·qe~ when ,the tmm input is
. J "
.•...•. . . .
...,'
_.
• ••
When repbrtiilg ~. pafit)'errorto thil:~' the nYiCdkablesthe'parityerror reporting
function by clearing .t'lili 1;,it.'This is.cfu'~tdkeep'irtw.tiPle parity e11'0rs from· Corrupting
thefaultaddressm.theFAR.Mter handling a parit'y;error software mustreenable parity
error reporting by setting this bit.
12
BTO (BU$tim@ut)-Wh~ ~t.Jrn$ bitindic~te~.tlu!~ Jbe bus has timed 9ut.This bit is
set enabled when the ENBTMR input is asserted. This bit is cleared when the CSR is read
or the RESET input is asserted.
11:00
RAZ (Read as zeros)-Not used.
Confidential and Proprietary
------.-------
1-185
-
Preliminary
MicroVAX78S84
Fault AddressRegiste1'..,...The fault address register(FARUs~~rUyre!Pstertha't is used to store
the address of the page in memory being accessed when a parity error is reported to the DYRC. This
register is cleared wheh the RESET input isassetted. Figure 4 shows the FAR format and Table 6
describes the function of each bit.
15
14
13
I I
12
I
11
10
00
I
I~l
I ...
RESERVED'---------O-A-L<
.......T9:09>
85<1:0>
ERRSTAT
Figure 4 • MicroVAX 78584 Fault Address Register Format
Table 6 • MkroVAX 78584 Fault Address Register. Description
Bit
Description
15
ERRSTAT (Parity error status)-This bit is set when external parity logic detects a parity
error and asserts the PARIN input. When set, register contents cannot be changed.
Cleared by a processor read transaction or when the.RESET input is asserted.
14:13
BS < 1:0> (Bank select)-These bits contain the value of the BS < 1:0> information at
the time the PARIN input was asserted. This value can be used to determine the bank of
memory with the parity error. Cleared when the RESET input is asserted.
l2:11
RESERVED (Reserved)-These bits are cleared at powerup and set after the first memory
operation. They remain set until the RESET input is asse.rted.
10:00
DAL< 19:09> (Data/Address < 19:09> )-These bits contain the address of the page in
memory being accessed at the time the PARIN pin was asserted. Cleared when the RESET
. inpu,t is asserted.
Error Reporting
The DYRC reports memory parity errors, bus timeout, and nonexistent memory address errors to
the CPU. For a memory parity errol; the DYRC provides the error reporting interface between
external parity checking logic and the CPU. TI'le bus timeout logic monitors the MicroVAX bus
activity and reports a timeout error when the addressed device does not respond by asserting the
RDY signal. When an error has been reported to the CPU by the DYRC, the error handling routine
must read the CSR to determine the type of error being reported.
Parity Error Reporting-The DYRC provides the interface between external parity checking logic
and the MicroVAX 78032 CPU for reporting a parity error. Parity error reporting is enabled by
setting the ENB bit in the CSR. When a parity error has been detected by external parity checking
logic, it asserts the PARIN input of the DYRC. This causes the page address to be captured in the
FAR, the ERRSTAT bit in the CSR to be set, the parity error logic to be disabled by the clearing of
the ENB bit in the CSR, and the CPU to be notified of an error by asserting the ERR output. The
1·186
Confidential and Proprietary
-
Preliminary
DYRC will hold the ERR signal asserted until the next data stream access to memory. This ensures
that the CPU will detect the error condition and respond. After responding to the parity error, the
software must reenable the parity error logic by setting the ENB bit in the CSR. Refer to the
MicroVAX 78032 Central Processing Unit User's Guide for information on error handling. The parity
error reporting logic also aids parity and error detection and correction (EDAC) designs by
providing a data valid strobe. The TN strobe can be used by external parity or EDAC logic as an
indicator that the d-ata on the bus is valid.
...
Bus timeout ert'Ol'-The bus timeout logic provides a means to monitor the MictoVAX ~s activity
and to notify the CPU oia nonexistentmen;l.ory error or some other error that causes AS to be
asserted for more than 25 ~s.Proper operation of this logic requires a .to-MHz clock input with the
INCLKSEL input assertedot a 20-MHz inJ?ut with tbeiNanEtinputcleassetted. The bus
timeout logic is enab1edor disabled by conn«rlng the ENB'i'Ml(inp\1t toVilD 01' Vss· When the bus
timeout logic is e~ledand the AS inpm has been asserted for more than 25 \.1$, the DYRC will set
the IITO bit in the CSR and asseit the ERR'signal.
Interval Timer
The interval timer provides a 100-Hz output (IN1'fiM) that can be used to support operating
system timing functions. The clock source for this. output is selected by the INCLKSEL input.
When this input is asserted, the clock squrce (cLio) is divided by two and the output is the clock
source for the timing circuit. When . not asserted, the 2o.;MH~input is the clock source for the
timing circuit. The IN'ITIM output will be 100Hz when the input is 40 MHz or the 20 MHz input
is 20 MHz.
Powerfail Standby
Powerfail standby. is functional.only whenrefte·sh mode 0 Ol' l·is selected. The powerfail logic
provides automatic memory refresh for powerfail conditions when memory and the DYRC have a
backup power source. Powerfail standby operation is enabled by the assertion of the PFAIL input.
This input must be asserted by external logic before the system power supply becomes unstable.
When asserted and refresh mode 0 or 1 is selected, any activity on the MicroVAX bus is ipored,
and the DYRC continues to refresh memoryuntil.the ~ signal. is deasserted or the backup
power supply fails. The PFAIL signal should be deasserted a..ID.ll.xhllUm of 10 ~ before pprmal
operation is resumed.
•. . .
..
Reset/Powerup
The DYRC will resetits internal counters and timing sequencers 'when .theRE'SET input is asset:ted
for a minimum of 800 I.IS and the clock input is operating. When the RESET input is deasserted,
the DYRC will initialize theDAAMs with eight refresh cycles. Menl0ry·a.ccess is delayedun~.i1 the
completion of the eight RAS-only refreshes. The DRAM data will belast when 'itESET is aSserted.
When power is first appliedtotheDYRC, the RESET input must be asserted fot a minimum of 800
IJS after the power supply voltages havestabilize&
• Interfacing Requirements
A typical MicroVAX CPU and DYRC interface configuration is shown in Figure 5. The external
logic required to interface a dynamic memory system is also shown. The actual logic may vary
according the requirements of the system. The typical external components consist of external
address decode logic, data bus transceivers with parity, memory address bus drivers, RAS and CAS
drivers, and a write buffer.
Confidential and Proprietary
1-187
I.-
Preliminary
MicroVA'X 78584
CKLI
Rm'f
<
I
l l
'
l
ERR
20 MHZ
iNciJ
OV
INTTIM
REFSEL
m
mil
DBE
Si:Qi.ii
DYRC
AS
CS<2:0>
.A
WR
I
DUTENB
! !
R'RaST
RINRPG
~ ADDRESS
~<31~
DECODE
LO\'lIC
DBE
SYSTEM
CONTROL SIGNALS
Eiiiii'fiiiiR
SE'LECf
CSA
----
OAl<19:00>
--to
85<1,0>
DBE
Rs
BUFFER
RAS<3:0>
CAS<3:0>
:----"'\
IiP.Aiiii"Y
PARIN
WR
AO<8:0>
rV
AODR
RAS<3:0>
DIN
ENS
OAL<31:00>
BUFFER
~
/
.A
B
A (
TRANSCEIVERS
"
DIR
RAM
BANKS
CAS<3:0>
BDAL<31:00>
WRT
~
OOUT
I
loo
REAO/WRITE DATA
f
Figure 5· MicroVAX 78584 Typical MicroVAX CPU and DYRe Interface Configuration
Dynamic RAM Requit'ements
TheDYRC supports 256K dynamic RAMs that have the following characteristics.
• Multiplexed row and column addresses
• 9-bit memory address bus
• Data in and three-state data out to allow common input/output
.. RAS only refresh
• 256 count or 512 count 4 ms refresh
The dynamic RAMs that meet the timing specifications in Table 7 will allow the MicroVAX 78032
CPU to access memory with no wait states or one cycle slip.
1-188
Confidential and Proprietary
Preliminary
Table 7 • MicroVAX 78584 Dynamic RAM Specifieatiolls
Parameter
Aa:esswith
no cycle slip (os)
Min.
Max.
&cess with
one c:ydulip{n$)
Min.
Max.
Access time from RAS
1.50
200
Access time from CAS
75
100
Row address hold time
20
25
Column address setup time
0
9
Column address hold time
45
5.5
RAS to CAS delay time
30
35
RAS precharge time
100
120
CAS precharge time
30
35
150
200'
RAS pulse width
DMA Interface
. .,
. ....'.
..
...-
.
The DYRC performs DMA read and write cycles s4Jillar to CPUread and write cycles. TheDMA
<
controller must controI:~tJALOC;:19:0 > , CS <2:(», BS 1:0 > , WIt, BM <3:0> ; SELEEl' 'and
AS lines, and check the'. state of the iIDY and DY. sigllals to transfer data to or from memory. It must
also check the state o£the ERR line for error conditions.
When the DMA accesses a memory that is controlled by the DYRC, the DMA·de.vi.ce must consider
the latency timetllllt may occur a result of arclreS'hCycle.TheDMA device (;Q1l use the RINPRG
signal to detect a refresh cycle in progress. The DYRC does not support ref.reshhold off. A DMA
device must process a request without waiting or RAM data rould be lost .
as
• Specifications
The mechanical, electrical, and environmental characteriStics and specifications for the MicroVAX
78584 DYRC are described in the following paragraphs. The test conditions for the dectrical values
are as follows unless specified otherwise.
• Power supply voltage (VDD): .5 V
±5%
• Ground (Vss): 0 V
Mechaniad Configuration
The physical dimensions of the 78584 84-pin cerquad package are contained in Appendix E.
Confidential and. Proprietary
1-189
MicroVAX78;84
Preliminary
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absOlute maximum ratings for extended periods may adversely affect the
reliability of the device.
• Power supply voltage (VDD): 5.0V ±5%
• Input and output voltage applied: -0.5 V VOD plus 0.5 V (5.5 V maximum)
Recommended Operating Conditions
• Power supply voltage (VDD): 5 V ± 5 %
• Temperature (TJ O°C to 70°C
de Electrical Charae:teristics
The de electrical parameters of the MicroVAX 78584 DYRC for the operating voltage and
temperature ranges specified are listed in Thble 8.
Table 8 • MicroVAX 78584 de: Input and Output Parameters
Symbol
Parameter
Test Conditions
Requirements
Min.
Max.
Units
Vrn
High-level
input voltage
2.0
VDD
V
Va
Low-level
input voltage
0
0.8
V
VmE
High-level
input voltage
(EPS only)
2.6
VDD
V
VILE
Low-level
input voltage
(EPS only)
0
0.2
V
Von
High-level
output voltage
Ion =28
2.4
VDD
V
VOL
Low-level
output voltage
IoL= 11 rnA
0
0.4
V
IlL
Input leakage
current
V..,*
0
-10
!-IA
IoL
Output leakage
current
V..,*
0
-10
!-IA
1m
High-level
input current
1-190
rnA
100
Confidential and Proprietary
J.LA
-
Symbol
Preliminary
Parameter
...·Requirements
Min.
Max.
-40
High-level
output current
Active supply current
300
Cm
Input capacitance
5.0
C"",
Output capacitance
5.0
Units
mA
mA
pF
*To be determined.
ac Electrical Characteristics
The ac timing parameters for the MicroVAX 78584 are grouped according to their functions. Figure
6 shows the clock input waveform and symbols and the parameters are defined lmle 9. Figure 7
shows the timing and symbols for the reset operation and the parameters are listed in Table 10. The
memory read signal timing is shown in Figure 8 and ~eWrite signal timing in Figure 9. Table 11
lists the timing requirements for both memory read and write transactions. The refresh signal
timing is shown in Figure 10 andthe timing parameters are listed in Table 12 . The register read and
write timing is shown in Figuresn and 12, respectively, and the parameters are listed in Table 13.
Figure Ushowsthe error reporting timing and Tabte14 lists the timing requirements,
The 'following notes apply to Figures 7 through 13 and to the associated timing parameter tables,
• All times are in nanosecl>ndsexcept ~here nOted,
• The ac high levels are measured at 2.0 V and the low levels at 0.8 V.
• The ac characteristics are measured with a purely capacitive load at the output of 50 pF on
RAS <: 3:0>, CAs <: 3:0> AD <: 8:0>. Rf:)Y, andOV.
j
telR
Figure 6· MicroVAX 78584 Clock Input Timing
Con£id~tial and Proprietary
1-191
1ltble9 • Mi'UoVAX 78;84 ··CIbclt I:titmt Parameters
Symbol
Definition
tru
Clock in fall time
taH
Clock in high
8
ten.
Clock in low
8
tclP
Clock in period
tc.K
Clock in rise time
Requirem.ents (ns)
Min.
Max.
4.5
25
50
4.5
··t,t,.w
-\
UNKNOWN
I
-
IAt.FI_
UNKNOWN
J
UNKNOWN
J
Figure 7· MicroVAX 78584 Reset Input Signal Tirning
Table 10· MicroVAX 78584 Reset Input Timing Param.et.ers
Symbol
Defmition*
Requirem.ents (ns)
Min.
Max.
tIlLW
RESET assertion width after VDD=5.0 V
800 IlS
tKHA
RESET deitssertion to AS assertion
100
tRUl
tRHI
t lKEP
RESET assertion to RAS<3:0>, CAS<3:.0>, RDY, and DV
deassertion
RESET deassertion to start of initial eight refresh cycles
refresh enabled)
50
(if
Time required to perform eight initial refresh cycles (if refresh
enabled)
200
31ls
*Delay from assertion of RESET to deassertion of AS by the MicroVAX 78032 CPU is typically
1.5 j.IS. CLKI input must be applied while RESET is being asserted.
1-192
Confidential and PrOprietary
Preliminary
MkroVAX18'84
DM<31:OO>
85<1:0>
....<3...
""TA
Figure 8· MicroVAX 78j84MemoryRe~C;yc!e Timing
DAl<-;:I:OO>
BS
8M<3'~
----(I
A.II)ORESS' '
~
_ _ _ _ _- '
1:10<'0:0>
COLUMN At)ORfSS
----.,..""--I~
Io-,-----------'r
RAS<3:0>
SGLECTED BANK
. CAS<3:0>
-~~~~
______________________
~mw~
ROY
f'-'.------------'ASlOVl.-----.
:1
-----\l
Figure 9· MicroVAX 78584 Memory Write Cycle Timing
Confidential!lnd Proprietaty
H93
-
Pteli~y
Tahl4;') 11· MicroVAX 78'84 Memory~te Cycle Timing Parameters
Symbol Definition
tARAV
MicroVAX18584
Requirements (ns)
Slow Cycle
Fast Cycle
Min.
Max.
Min.
Max.
20
10
20
DAL< 19:02> valid to tow ad~ss valid
tAsHCASH AS deassertion to CAS < :>:tI > deassertion
50
50
t ASHDVH
AS deassertion to i5V deassertion
50
50
tASHRDH
AS deassertion to RDY deassertion
50
50
t ASLDVL
AS assertion to DV assertion
tASLRDYL* AS assertion to RDY assertion
t ASLRL *
AS assertion to RAS assertion
tASLSH
SELECT hold time after AS assertion
tunAsn
Column address hold time after AS deassertion
tRAn
Row address hold time after RAS < 3:0> assertion
t RLRCL
425
450
225
250
260
300
60
100
20
15
20
15
20
20
55
100
30
75
RAS < J:O > assertion to read CAS assertion
105
150
55
110
tRW
RAS < Bj > pulse width
315
350
240
275
tRLWCL
RAS assertion to write CAS < J:O>
assertion
115
140
115
140
tSA
DAL < 19:2> and BS < 1:0> setup time to AS
assertion
t SLASL
SELECT setup time to AS assertion
t SRCA
Corumn address setup time before read CAS < 3:0 >
assertion
20
30
20
30
t SWCA
Column address setup time before write
CAS<3:0> assertion
RAS < J:O > precharge time
70
80
70
80
23
23
8
8
150
125
*The maximum times for tASLRDYL and tASLRL assume there is no refresh cycle in progress.
1-194
Confidentialand Proprietary
·Table 12 • Mic:roVAX 78S84 Rdiesh TimiogParameters
~ts(n8}
Symbol Definition
Slow Cycle
Min.
Max.
Fast Cycle
Min.
Max.
25
100
Refresh address setup time. to RAS < 3:0 >
assertion
100
Refresh address hold time· after RAS < 3:0 >
assertion
235
265
.135
165
tllEFPllll
RAS<3:0> precharge .
,165
185
165
185
to",
lwk.lo> pulse width
215
235
165
185
tAOS
tAJ>H
Figure 10· MicroVAX 78584 &fresh Signal Timing
Wli /
I.
-
Preliminary
MicroVAX.78.584
DATA,
---{
00'
Figure 12 • MicroVAX 78584 Register Write Signal Timing
Table 13 • MicroVAX 78584 Register Read/Write Timing Parameters
Symbol
Definition
t ASHlIDH
AS deassertion to RDY deassertion
35
t"SLRDL
AS assertion to RDY assertion
25
tDADBEH
Data setup before 'i5BE deassertion
50
tDAH
Required data hold time after DBE assertion
10
t DBED"
tRSASL
1·196
Requirements (ns)
Min.
Max.
DBE assertion to stable I/O data on DAL< 15:00 >
RS setup time before AS assertion
Confidential and Proprietary
25
15
CS<2:O>
MicroVAX 78584
Preliminary
-<. . ____
--'X'--__
OAT_AS_""_"'_M_ _
---J>-
X'-___
S_"_"A_"_ _......
'"_STR_UCT_'O_"
~\~_____~r\
OA_T_AS_"'_EA..
___
r\~-----f
'_PAE_R.l_)~~._{__---l!
,_" ~
PA: _ _ _ _ _ _
Parity Error
OAL<31:00>
BM
--<
AOCRESS
>----<. ._______
\)_"O_"_'N'_O_ _ _ _ _
=-->>----
~~~-------------------1
IIASURL---~
9
~"SH'Rl}-
Time·out Error
Figure 13· MicroVAX 78584 Error Reporting Signal Timing
Symbol
Table 14· MicroVAX 78S84 Error Reporting Timing Parameters
Definition
Requirements (ns)
Min.
Max.
t pAElIRL
PARIN to ERR assertion
50
tpAEllKH
ERR deassertion after data stream cycle
50
tASLI!KL
AS assertion to ERR assertion
t ASHElIH
AS deassertion to ERR deassertion
Confidential and Proprietary
25 IlS
50
1-197
.Fea~
·Low~costMicro"AX d~lopmellt$ystem contairyed a single module
• Full-speed incircuit emulation of MicroVAX 78032 microprocessor chip and MicroVAX 78132
floating-point unit chip
• PROM-resident monitOr with pOwerful eomtnand set
• 64 Kbytes of relocatable memory simulation RAM for target applicatiGn ,
• Two RS.232-compatible serial lines for host and terminal connections, one with modem control
• Internal clock of 10-,20-, or 40-MHz or external clock
• Bus timing controllable by ADVICE and t3.l'8et()rbytr;qet~ne (wait states only)
• Powerup diagnostic tests to verify its own oPeration
• Connectors for dock-in, trigger-in, trigget-~ut, power supply~ and R$-232 ports
• Single 5-volt power supply
. Description
The ApplicationsDevelopment MicroVAX Irlcircuit Elllwator (ADVICE) is a low-cost, incircuit
emulator used for the development of ~ardware ~4s6£tware products based on the MicroVAX
78032 32-bit microprocessor and thelvJiicroVAX 78~2 floating.pointut1it~ ~ostic or application programs for the user's target miiy~ developed on a VAXNMS ¥st'an(t~nloaded to
ADVICE. ADVICE containsalfthe necess!uyhardw~ alldSroprietary
1-199
• Sy81em Overview
The ADVICE enables the hardware emulation of the MicroVAX CPU and FPU at full-speed (40MHz) and provides the user with complete control over MicroVAX CPU operation. This includes
the ability to start and stop the program operation and to single-step through a program. It contains
hardware and software that can be used directly by the target application to simplifythe
development of the target hardware and software.
Figure 2 shows the system interconnections to the ADVICE module. The host computer is used to
write, edit, and optionally debug the user programs that will eventually run on the target system.
These programs are converted to hexadecimal format by the DECPROM software and downloaded
to the ADVICE over a serial line. A local console terminal is used to enter commands and control
the entire development process.
HOST COMPUTER
POW.E!I ON LEO
CLOCK IN SNC
Figure 2· MicroVAX ADVICE System Interconnection
1-200
Confidential and Proprietary
Module Connectors
Table 1 lists the connector types that are included on the ADVICE module and their function. R.efur
to Figure 2 for the location of the connectors on the module and to the ADVICE User's Guide for the
connector applications and signals .
.'BIttle 1 • ADVICE Module: Connectors
Connector
J1
J2
J3
J7
J8
J9
Type. '.
Function
BNe
Clock in
Target circuit
Target circuit
. 4O-pin
40-pin
. BNC.
Triggerip
BNC
Trigger out
Power supply
Host computer port (serial-line)
Console port( serial-line)
4-pin
25-pin
25-pin
J10
J11
,
SwiteheSand Indka10ts
TheADVlCE mOdule Contains eight switches inll.4!l~-in:lj.rte p~~JDIP)tha~ a:(e ~~,selea
various functions. a reset pushbutton switch, arid two tED indicitOrs~ Table2 lists the positions
and selections of the SWitches on the DlP.·Theresftt-pushoatfonis'use'dtoWtiali!e,the moduleiiid
causes a series of diagnostic tests to he perlormed.The power on1i&htindiQl~~ tl1aithe
.
DMR, :o.:«:?< 3:0>,
• The output of an address comparator that indicates whether a MicroVAX bus address is greater
than, less than, or equal to a stored value
• The logical level of a BNC connector input
The ADVICE can be programmed.to igno~ eve.msQr halt pl."Q1Jl:'8m ~tiol:lwhen an event ocCurs.
In either case, a trigger output from ADVICE indicates the occu.r:rence of an eVent.
Memory Simulation
The ADVICE contains 32·Kbytes or 64.Kbytes of memory simulation RAM (MSR) that can be
mapped anywh(:re in the UU"get address space. The eIlabling of ¥S.R ensure$thht tlsersthllf\'alid
memory is available during the application development.
Serial-line Ports
One EIA RS-232 serial-line port is used to connect the host processor to the ADVICE and includes
modem control. The remaining EIA RS-232 serial-line port connects to the console terminal. These
ports are used in nontransparent mode and an internal subroutine is included to access these ports.
SeH-diagn.ostks
Several diagnostic tests are performed in the ADVICE during the powerup sequence or when the
Reset pushbutton on the ADVICE module is pressed. These programs verify the integrity of the
information in PROM and RAM (including MSR) and the operation of serial-line ports, event
detection logic, and MicroVAX CPU and FPU. The user can select a limited diagnostic routine to
preserve RAM contents or a comprehensive diagnostic routine that tests RAM without regard for
its original contents .
. User-suppJied Equipment
The standard and optional equipment and software required for use with the ADVICE is listed· as
follows. The optional listing depends on the type of application to be developed.
• A VAX processor system with an available RS·232 serial-line port
• VAXjVMS operating system, Version 3.4 or higher
• DECPROM software, Version 1.0 or higher
• 5·Volt power suppJy
- Local VT100 compatible terminal
• Appropriate etch layout around target MicroVAX CPU surface mount pads to match ADVICE
connector (Refer to the ADVICE User~ Guide)
• RS232-compatible modem for remote host or terminal (optional)
• External clocks or triggering circuits including cables (optional)
Confidential and Proprietary
______'__
--·-~~~'·~--~~-_""A_A!!l_r.r'!P'W_I'iI
'_._MIII!J_'_ _ _ _ _ _ _ __
"'~_ISM_i
1-205
-
, MicroVAX Incircuit Emttla_
• Specifications
The phY!iical and electrical specifications of the ADVICE are as fonows:
Operating Environment
• Temperature: 15°Cto 32°C at 200 linear feet/minute air flow
• Relative humidity: 20% to 80% (noncondensing)
Module Dimensions
• Height: 26.0 em (10.25 inches)
• Length: 40.6 cm(16.0 inches)
• Width: 2.5 em (1.0 inches)
Power~ents
• Power supply: 5 V ±5 % at 6 A (maximum) 4.5 A (typical)
1·206
Confidential and Proprietary
. Features
• Enitllates the VAX proceSsors·
• CoIlsistsof the DC328 irutruction/ex;ecution lqgic {I/l':chiIA,tlw DC3.29l1l ) that are also time multiplexed. The DAL line addresses are driven
during the first half of each.0'cle, and DAL data is dtiven during the seCond half.
The V-ll chips interface to main memory and 1/0 devices through three gate arrays that form
the port controller. This logic provides three ports, one of which is the CPU port to the V-U chips.
The remaining two ports access main memory and 1/0 devices. Main memory and system I/O are
on the VAXBI bus and are accessed through the VAXBI bus port and the VAXBI 78732 bus
interconnect interface chip (BIIC). The third port is used for localI/O transfers to the control panel,
floppy disk, etc.
Related Documents
Additional information on the V-ll chip set is contained in the following specifications.
• V-ll CPU Functional Specification
• De327 ROM/RAM Chip
• DC328 l/E Chip
• DC329 M
Functional Specification
Functional Specification
Chip Functional Specification
• DC330 F Chip
Hardware Specification
• Scorpio Port Controller Specification
• KA820 CPU Modt& Specification
1-208
Confidential. and Proprietary
• Featutes
• Custom. deSigned VLS1 ROMjRAM chip for the Von processor.
• Contains 16K by 8-bit word ROM, 1K by 8-bit word RAM and 32 by 14-bit word CAM .
. Description
The D027 ROM/RAM, contai~ ina,~47pin'Packag~.is~VI.sI chip designed for the V·U
processor. It~ontains 16K 8-bhwords Qf maskedlll;Ogra~ROM(read-oruy, memory), 1K by Sbit words
R.A1v1' (randOril~cXesslliemoty')and.:32 .i 4-bit' words of CAM (content addt-essable
memory). The PC.32ichip is deSiglle
AND
MSElB
LATCH
'
D<7:0>
WE
Figure 1· Del21 ROM/RAM Block Di4gram
Confidential and Proprietary
.1-209
De327
.. Ym 8nd Signal Descriptions
The input and output signals and power and ground connections for the DC327 44-pin package are
summarized in Table 1. The table also contains the physical pin locations that are shown on Figure
2. The following paragraphs provide more detailed descriptiops of the inputs and outputs of the
Mchip.
Table 1 • DC327 Pin and Signal Summary
Pin
Signal
Input/output
17-14,1O~7
D<7:00>
inputs/outputs' Data-Transfers data from the ROM and transfers
data to and from the RAM and CAM.
3,4,30-33,
36-43
A<13:00>
inputs
Address-The ROM, RAM, and CAM address
inputs.
5
CE
input
Chip enable-Clock signal to latch the A < 13 :00 >
and MSELB inputs.
26
MATCH
outpue
Match-Indicates the result of the CAM match
operatioIl during a read cycle.
29
MSELB
input
M sdect B-Sdects the ROM, RAM,· and CAM
arrays for data access.
19
OE
input
Output enable-Activates the output buffers during a read operation .
. TRISTATE . input
Three state-Used only during manufacturing test.
6
Description/Function .
20
WE
input
Write enable-Selectsa. read or write operation for
the RAM or CAM.
28
VSB
input
Voltage back-bias-Power supply back·bias voltage.
18
VH
input
Voltage high-Connects to VDD through an external
lO-ke 5% resistor.
27
V
input
Voltage low-Connects to Vss.
21
Not used.
35,34,22,
23,13,2
Von
input
Voltage-Power supply voltage.
25,24,11,
12,1,44
Vss
input
Ground-Common ground reference.
'Three-state output
20pen-drain
1·210
Confidential and Proprietary
Dell7
Preliminary
~ ~
OQ
<0
....
~
~
....
U)
g ~
III
q-
w
i i
:;(
~
N
;;;
~
C')
'" '" '" '" '" '" '"
A03
- ...
aI
Cl
0
II)
~
'"28
N
VBS
A02
27
ilL
AOI
26
MATCH
AOO
25
VSS
24
VSS
23
liDO
22
liDO
21
NOT USED
20
WE
19
.OE
.......18
VH
VSS
44
. . - - - PIN '·'DENTIFIER
VSS
~327
TOPVlEW
~
6
....
OQ
§ 8
QI
;.!
88
-- - ,..'" - ...'"
q-
N
~
~ ..
~
g
Cl
,';'.
.....
c·
8. g g
",.
FigUn! 2- DCJ27 PintliSigtiments
Data (D < 7:0> )-Bidlrectional data lines used to transfer data from the ROM, and to and from
the RAM and CAM.
.
,
.Address (A < 13:00 »-The address inptIts to reference the ROM,; RAM, andCA¥.These inputs
are latched during read and write. cycles during.the high-to~loW tnttisitionof the C! input.
Chip Enable (CE)...-A clock signalthatlatchestheA~ 13:00>~MSf:LB hlputs, and initiates
the internal.aca;ss cycle with'll high.tp..lowttansition. Whende~ted.the~ signal <;auses the
data output buffers to become a high iD)pedance.
Match .(MAMJJ-An open-drain output that indicates the reswt9f the CAM match operation
during.a read cycle. The CAMmatch ~tiona.nd the MA1t;H Q~~put are active durirlg RAM read
cycles as well as ROM read cycles. The M1\1'CH' output is disabled only when the ROM/RA.?vJ: chip is
in test mode. The state of the MA1eH' signal is not define<;t duri~ JtAMlCAM write cycles.
M Select B (MSEL6~-An address input that ~crlects. the ROM or.CAMarrays and theRAM array
for data access. This sijplal is latchedduriDg read. or write cycles.
OutputEnahle (OE)-Activ:atesthe output buffets during a read operation.
1-211
Three State (TRISTATE)-l}sed only for manufacturing test purposes and not used during normal
operation. The input connects the power llupJ:!Iy voltage (Voo) through a lO-kn ±5% external
resistor. When enabled, the D < 7:0> outputs are a high imped~.
Write Enable (WE).,...This input selects the read and write operations to the RAM or CAM. When
asserted, the output lines of the buffer become a high impedance independently of the state of OE
input.
Voltage High (VH)-This input connects to the power supply voltage (VDO) through a lO-kn ± 5%
resistor.
Voltage Low (VL)-This input connects the ground reference.
Voltage (VBB)-Power stlpply -3 V (nominal) back-bias input voltage.
Voltage (VDD)-Power supply 5 V (nominal) input voltage.
Ground (V.s).....Common ground references for the chip.
Functional Operation
The patching of incorrect ROM data with RAM data is performed by the.following operation. The
14-bit ROM addresses of the incorrect ROM data are written into the CAM. The correct data is
written into RAM locations that have lO-bit addresses that are identical to the low-order lO-bits of
the incorrect ROM data. BaCh time the ROM is accessed, the incoming ROM address is
automatically compared with the addresses stored in the CAM. If the addresses are the same, the
MA'It:H output is asserted to inform the external logic that the ROM data currently being accessed
is incorrect and that the correct data is in the RAM. The RAM is then accessed in the following
cycle(s) with the same address. tThe ten low-order address bits must be identical to access the
correct data.
The DC327 ROM{RAM chip contains an address/MSELB latch; a ROM,RAM, CAM" a data
multiplexer, and an output buffer shown in Figure 1.
.
' .,
Address/MSELB 'Latch-Thi,siatch ,holds address inputs A < 13 :00 > and the' MSELB 'input.
When the CE input is deasserted, the address and the MSELB inputs pass through the latch to the
intetruillogicof the chip ..A high-to-Iow transition of the CE input loads the state ofthe address and
MSELB H informationint6 the latch, and any trahsitions on those inputs that follow are ignored.
Read-only Memory (ROM)-The 16K by 8-bit word ROM is accessed by the address information
onthe A < 13:00> lines £rot'nthe output of the address latCh. The ROM is accessed during a highto:low transition of the CE input and the 8-bits of the ROM data are transferred to the data
mrl+iplexer.
'
Random Access Memory (RAM)-The lK' by 8-bit word RAM is accessed by the' address
iliformation onthe A< 9:0> lines from the output of the addresslatch. A high-to-Iow transition
of the CE input when the WE input is deasserted will access the RAM and transfer 8-bits of the
RAM data to the data multiplexer. The RAM is written with the data on the D < 7:0> lines when
the latched MSELB signal is asserted, the CE signal makes a high-to-Iow transition, and the WE
input is asserted with the proper timing.
Content Addressable Memory (CAM)-The CAM consists of 32 14-bit registers, 32 14-bit
comparators, logic for detecting an address match, a CAM test address register, and logic for testing
the CAM. When the CAM operates in the normal mode (not test mode), the latched address
information on lines A< 13:00> is cqmpared with the addresses stored in the 32 14-bit CAM
registers. If the latched address is the same as an address stored in the CAM registers, the MATCH
output is asserted. The MATCH output is indeterminate during a RAM or CAM write cycle. In test
mode, the MATCH output is disabled. The MATCH open drain output is internally disabled at the
beginning of each cycle and must be pulled up to its inactive state by an external resistor.
1-212
Confidential and Proprietary
'D__t ! - ! _
rn:umm.ary
CAM Write Operations
The mask progm~le CAM write decoder enables up to eight ROM,IRAM chips to be tonn~
in p~rallel while main~ a unique write access to each CAM register on each of the eight ROM}
RAM chips., AROMIRAM chip can access each of the 32· individual CAM registers. The CAM
registers arewrit~l'l ",hen the WE input is asserted,the rylSELB input is Zero, the CE input is
asserted, and when the write decoder decodes one of the reserved addresses shown in Table 2.
Address A < 13:00 >
Internal Sttucture &cessed
(bexadecimal)*
CAM Register
'0 <07:00>
0<13:08>
1 <07:00>
1
0000
0001
'0002
0003
Data
D<7:0>
'D<:5:0:>
D<''7:(l>
D<5:0>
(continued through)
31 <07:00>
31<:13:08> '.
oo3E
003F
D<7:0>
D<5:0:>.
*Assume mask p~ble bifs A < 8:6 > o£;th~CAM write decoder are zerOs.
Datil Mtd~~
.
The data multiplexer selects the data to be transferred to the output buffer and then to the
I
D<7:0> ,lines. Eight bits of RONfdata, RAM data, or CAM register match state are selected
depending on thesta!;e of the intewal CAMSEL signal and the latch MSELB signal listed in Table,3.
CAMSEL
MSELB
D<7:0> output
o
o
o
ROM
1
RAM
1
X
"X=lorO:
Output Buffer
The output bUffer driVes the output ofthe data multiplexer onto the D<7:0 > lines. When not
tra.nsferringdata; ,the Qutputs of the buffer area high imped~ce. Tabl~ 4,·lists the. state. of the
outputs depending on the input signal conditions.
Confidential and Proprietary
1·213
...
Preliminary
00'27
Table 4 • DC327 Output Buffer States'"
TRISTATE
CE
WE
OR
Output.
1
0
1
0
Drive output
1
0
1
1
high-impedance
0
X
X
X
high-impedance
X
1
X
X
high-impedance
X
X
0
X
high-impedance
.
"X=lorO.
Summary of Read and Write Operations
Thble 5 lists the inputs required for read and write operations for each of the ROM/RAM chip
sections.
Table.5 • DC327 Read and Write Operation Selection'"
CE
TRISTATE
WE
OE
MSELB
A< 13:0>
Operation
0
1
1
0
0
3FFB-OOOO
ROM read
0
1
1
0
1
3FFB-OOOOI
RAM read
0
1
1
0
X
3FFF-3FFC
CAM m~tch state read
0
1
0
X
0
003F-00OQ2
CAM write
0
1
0
X
0
0201-0200
CAM test address reg write
0
1
0
X
1
3FFB-00OOI
RAM write
IThe RAM is accessed by address bits A < 09:00 >. Bits A < 13:10> are not used.
2Mask programmable bits A < 08:06 > of the CAM write decoder are zeros.
*X= 1 orO .
• Specifications
The mechanical, electrical, and environmental specifications for the DC327 are contained in the
following paragraphs. The test conditions for the parameters in these specifications, unless
specified otherwise, are as follows:
• Ambient temperature (TA): O°C to 70 0 e
• Power supply voltage (VDD): 5.0 V ± 5 % (maximum ripple 200 m V peak-to-peak)
• Power supply back-bias voltage NBB): -3.0 V ±15% (maximum ripple200mVpeak-to-peak)
1-214
Confidential and Proprietary
...
Preliminary
DC327
Mechanical Configuration
The mechanical dimensions for mounting the DC327 44.pin leadless package are shown in
AppendixE .
. Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to a device.
Exposure to the absolute maximum rating conditions for ex:tended periods may adversely affect
the reliability of the device.
• Power supply voltages (VDD): -1.5 V to 7.0 V
• Power supply substate voltage (Vss): -6.0 V to 0 V
• Input/output pin voltage: -1.0 V to 10.v
• Storage temperature range: -55°C to 125°C
• Ambient temperature operating range (TJ: OOC to 70°C
Recommended Operating Conditions
• Power supply voltage (V(0): 5.0 V ± 5%
• Power supply back-bias voltage (V88): - 3.0 V
• Ambient temperature (TA): 25°C
at: and dc Electrical Characteristics
Refer to the DCJ27 ROM/RAM Chip Functional Speci/icationfor the de input and output parameters
and ac timing parameters.
Confidential and Proprietary
1-215
• FeatUres
• Main processor element for the V-ll chipset
• Used with the M-chip and F-chip to emulate VAX instruction set and memory management
• Initiates memory references and containsaddres~ translation logic
v','_"
'r.<
. Description
The De32S Ins~n/Execution(I/E) logic'ls contained in a 132"pinPGA package and is the
main processing elem~nto£ theV-ll processor chipset. It pre£etcltesinstnictions, parses opcodes
and specifiers, initiates all memory references, and contains the resister fUe~nd arithmetic logic
unit (ALU) and most of the address translation hardware. Together with the F chip and M chip, it
emulates the VAX instruction set and memory architecture. The function:U block diagram of the
I/E chip is shown in F~re 1.
. .
'.
FBOXN
FBOXZ
110
.
....
'1 BOX
,.
t
~Brnt
AWIW$<30..21.5:0>
....;
-"'.
Dt~)
...
~[.
.'
I'iAt"S'I'IQl.
~;I.
;I.
A
CMISS
"
CAM MATCH
~
M'E'RRiiW>
T
i:7
~
r-
-
MICROSEOVENCER
MEMORY
r-
IlI/TEllFACE
r-
PHYS ADOR
Aii5'iii'
MTBMISS
;
;'
...
- -
I;}IIl
INTEIW.CI'
r;
...
I--
. 'lI£I\IS
'.
II;}I\L<3':OO~
A
.....
I
DIiIUS<31:00>
•
......
10A1..<31:00>
.'
MICRO TEST<3:0>
.~
l~~
,
~/ ~
-
. r-.
'-
IMI8<3aoo>
I
A
CLK
CLK lIAR
CLKSYNC
M18< 39:00
3!
ri
MIS
INTERFACE
MAB<14:OO>
CLOCKS
OCtO
~j!;TATE
CSWE
Figure 1 • DC328 lIE Chip Block Diagram
1-217
.Confidentialand.Proprietary
-. ~
------·-~---------
-'--'-"_II!__
_____ ___'_I O____'.._."'_.
.~_.
'_I~""'''''''''''''''''''_",_~_._!I'IlIi''''''"'
OC328
Pin ~ SigtW Descriptions
The input and output signals and power and ground connections to the DC328 I/E chip are shown
in Figure 2 and summarized in Thble 1. The paragraphs that follow provide a more detailed
description of the signal functions listed in Table 1.
14 13 12·11
10
9
8
7
6
5
4
3
p
0
0
0
0
0
0
0
0
0
0
0
0
0
0
N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
N
P
0
0
0
M
0
0
0
L
o· 0
0
0
0
K
0
0
0
0
J
0
H
M
0
0
0
l
0
0
0
K
0
J
·0
0
0
0
0
0
0
0
0
0
H
0
o· 0
0
0
G
0
0
0
0
0
0
G
F
0
0
0
0
0
0
F
OC328
E
0
0
0
0
0
0
E
0
0
0
0
0
0
0
D
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
8
0
0
0
.0
0
0
0
0
0
0
.0
0
0
0
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0 ..
A
10
9
8
7
6
5
4
3
2
14 13 12 11
mpVIEW
Figure 2· DC328 Pin Assignments
1·218
2
Confidential and Proprietary
PACKAGE··IDENTlFIQATION
'lable 1- DC)28 Pin and S p Summary
Pin
8ipaJ
P4,P3,N3,P2,
M3,N2,M2,Pl,
L3,Nl,L2,Ml,
K3,Ll,K2,Kl,
DAL<31:00> input/output Data/address lines-Transfer. data and
address information to and from the I/E chip.
Input/output Deseripdon/Function
J2,HIJl,Gl,
H2,Fl,E2,El,
E3,Dl,D2,Ct,
C2,Bl-B3
C02
DAt BUSY
input
Data/address lines busy---Indicates that the
port controller has control of the DAL lines.
A7
bAt STALL
input
Data/address linestall--Indicates that the
data source cannot respond to a data request
during the same cycle.
B7
CMISS
input
CaC~mjss--Indica~s that the backup translation buffer miss has occurred.
K13
CAMMA'ItH input
Content .··addressablememory match-Indicates that an improper address has been
detected
by the ROM'JMM
logic.
;
"",
,
J12
CPU FAULT
output
~
,
"
CPU fault-Indicates that a hardware error
has been deteCted.
L14
MERR TRAP
input
Memory error trap-Indicates that the M
chip ha$. detected an error condition.
M14,A9,AlO,BIO, MIB<39:00> input/output Microinstruction bus-Transfers microAU,ClO,A12,Bll,
address;micromstructioO!>, andintetclUpstatus.
A13,B12,AI4,B13,
C13,BI4,D13,Cl4,
E13,DI4,F12,E14,
F13,F14,H14,PS,
N9,P9,M9,Pll,
PIO,P12,N12,M12,
P13,M13,N13,L12,
P14,L13,NI4,K12
J13
output
Control store output enable-Controls the
stateo£ the control store output buffers.
K14
output
Control store write enable-Controls the
writing of information into the RAM or CAM
of the control store memory.
M14
MIBPAR
input/outputMlB paritY-lndicatesthe odd parity of the
infl,)rmationon theMIB < 39:00 > lines.
Confidential and Prop1'iet:ary
~~~
1-219
______
• •_ _ _ _ _ _..._ _ i
~.~.--~-------~----------~-.---.-
~
Pin
Initial instruction decode-Indicates the start
of a macroinstruction to an F chil?o
P7
lID
P6
FBOX N
input
F chip sign N flag-Indicates that the result
of an F chip computation is negative.
P5
FBOX Z
input
F chip sign Z flag-Indicates that the result of
an F chip computation is zero.
A2,B4,A3,B5,
A4,B6,A5
PAL<6:0>
output
Physical address lines-Transfer part of the
DAL line address information to the M chip.
AO
ABORT
output
Abort-,-Indicates that the current microinstruction should be ignored.
A6
Mrs MISS
outPJ.lt
Mini translation buffer miss-Indicates that a
mini translation buffer lookup has failed.
G3
eLK
input
Clock-A MOS dock signal from the M chip.
F3
CLK BAR
input
Complemented MOSclock-A complementary CLK signal.
G 14
. CLK SYNC
input
Clock synchronization-Provides a phase 2
reference marker during a cycle.
N6
TRISTATE
input
Tristate-Causes the output buffers to
become a high impedance.
J14
DCW
input
dc low-Indicates that the dc power is not
within the required specifications.
Al
Vuu
input
Voltage back-bias-Power supply voltage for
the substrate of the chip. (-3.0 Vdc nominally)
B9,C3,C6,C9,
Cll,C12,D3,G2,
H12,H13J3,M5,
M7,Mll,N5,N7,
Nll
Vnn
input
Voltage-Power supply voltage.
B8,C4,C5,C8,
D12,E12,F2,G12,
G13,H3,M4,M6,
MS,MIO,N4,NS,
Vss
input
Ground-Common ground reference.
NlO
Data Address Lines{D,fU.. < 31:00 >.-B.idirectionallines used to transmit address and data to and
from the Vll chipset, .the port controller, and the cache and backup translation buffer (BTB)
RAMS. The I/E chip transfers address information during the first half of the the microcycle. Data
is transmitte<;l and recc:iv<;d by the DAL lines. The data is valid only during phase P7 when the data
is received from the cache or BTB )tAMs ..When the data is received from other sources, it is valid
during phases P7 and P8.
1-220
Confidential and Proprietary
-
DAJ.Busy WALBUS).'>-This
input is asserted when the port c0ntroller has conttol of the
DAL< 31:00>li~.Whenasserted. the DAL< 31:00 > outputs become a high i~ance.1'he
Dicr:.lJp$Y.sigtlal is a$serted.dUJ:ing cache fillcycles . after the port controller bas accepted the
comm.ndsent. to it by the M chip. It is held.by the port con~ller until the .last loQgwordof .the
cache £ill has been received. !he port controller also asser~!the DAL lJusysi,gnal during. I/O
invalidate cycles to hold the DAL lines while the controller transfers the invalid address to the
Mchip.
DAL Stall (DAL STALL)-This input is asserted when a data
SOurce
cannot respond to a data
transferrequestdurtngthe same cycle; !'he'sOuWe that fequ.estedthe data'is stalle!d'until the
responder can resporlquring memory reqtiest write
transactions, memory request read transactions that have cach~ miS$e$. IB-fill trarlsactions that
have cache misses,. load PTE operations, and Mini-TBmiss cycles that result in amiss in the BTB.
This input is used by the I/E chip only to indicate that a backup TB miss has occurred.
Content Addressable Memory Match (CAM MATCH)-Used to detect patched ROM locations
during a ROMaccess ••Thig,:signal is;assertedwhenthe CAM.in~_DC3~1cMtrol StOre .detects an
address with a pstchedmb:toinstructiotL. The execution0f'thefaultymicroinstruction is
suppressed by the AH6RT signal.
CPUPault (CPU FAtIL'f)-ThisJ.ine indicates. that a hatttware emtirhasd(iCllTred andisased for
driving an LEDin the field. Refer to. Microseque:ru:eJl.sect:icm£oriietalled information.
M Error Trap (M ED TRAjt}..~Thit.lib.e isasst'i'ted:by ~M chip to infOrm the lJEchip o£an
errot. The assertion of this signal causes the I/E chip to abort the microtrap operation. It is' asserted
when apa1dtyerror~ bnthe&tareadbperation£rom OllIe of;the'tag~ys 'duringamcmOl'y
request (MEMREQ)"m.fill, or Mini..TBmis&operati.on~k isalsoasseJtted:i'nenitw: POl'tconttoller
asserts a port controlenordue 'to adatlt·'er.rm(dtat:'haS~.duringamemorytead orwrlte
operation.
[
Microinstruetio Bus (MID < 38:00 > )-This is the primary cOhttdlbuS .. Internal status bits and
mit:roaddresseslJ1'l::transferredonthisbUsinpba$esP)'iUldP4during.the~shalfoftheCyde.
TheDC327controistotedtivesthemkroinst:nrotioMorltheMIB-<38:00>1inesirtphasesP7.and
P8 during the laSt half of the ¢ycle.
Control Store Output Enable(~...;;;.ASserted. to causethe.outPut btiliefs'of the control store to
become./thighimpedancedwingiphllSesiP6.thtoughP8.
Control Store ~BnahIe (GSWE).;...Controlsthe \VritiDg()flilie'40~bl:t~rd to the RAM or CAM
in thecontrol.store.
MID Parity (MID PAR)-This line indicates odd parity for the 39·bit control word during phases P7
and P8;It. is.not·used duringphasesPJ and P4 •. When a pari,ty;f1rror isdeteeteci; the.I/E.chip
forces a microttap.
Initial Instruction Decode (llD)-Indicates to the F chip that a new macroinstruction execution is
beginning and thattheopcode on lines MIB < 22:15 > is valid.
F Chip N Bit (FBOX N}-Indicates that the reSult Qf an F chip computation is negative during
phases P7 and P8. When no F chip is present, a pullupresistormust be connected to this input. The
F chip also indicates an error by asserting the N bit during phases P3 and P4.
F Chip Z Bit (FBOX Z)-Indicates that the result of an F chip computation is zero during phases
P7 andPS.
1·221
-
D0.32S
Physical Address Lines (l?At < 6:0> )-These lines provide the M chip with part of the address
earlier than the address is available on the bAL < 38:00 > lines. When the MTB MISS signal is
asserted, the value on these lines is a virtual address. If the MTB MISS signal is not asserted,· the
address on the DAL<38:00> lines is a physical address. The mapping of the virtual and physical
address of the DALlines to thePAL<6:0> lines is shown in Table 2.
Table 2 • DCl2S Physical Address Line VIrtUal and Physical Addre~s Correlation
Virtual Address
DAL Line < 31 >
PAL Line
<30:17>
<0>
<16:11>
<10:00>
<6:1>
Physical Address
DALLine
PAL Line
<28:13>
<12:06>
<6:0>
<05:00>
Abort (ABORT)-This signal indicates that the current microinstruction should be ignored. This
inhibits execution of the current microinstruction and forces the loading of the next microinstruc.
tion.
Mini-TB Miss (MTB MISS)-This output is asserted during memory requests and IB·fill operations
when a Mini-TB lookup fails. It indicates that a Backup TB read cycle should be performed, a PTE
should be passed from the BTB to the IjE chip, and the microinstruction or I .boxrequest should be
initiated again.
Clock (CLK)-This signal is driven by the M chip and is used by the lIE chip, M chip, F chip, and
port controller chips. The eLK input makes a transition from a 0 to 1 at the beginning of every odd
phase. The eLK frequency is one half the frequency of the Tn eLK IN input to the M chip that is
used to generate the eLK and eLK BAR signals. The nominal value for TTL eLK IN input is 40
MHz resuting in a 20.MHz eLK input.
Clock Bar (CLK BAR)-Thls signal is used by the I{E chip, M chip, F chip, and port controller
chips. The eLK BAR signal makes a transition from a 0 to l·at the beginning of every even phase.
The frequency of this signal is one·half the frequency of the TTL eLK IN signal. The nominal value
for TTL eLK IN is 40 MHz, thus producing a 20·MHz eLK BARinput.
Clock Synchronize (CLK SYNC)- This signal is from the M chip and is used to synchronize the
chip set and port controller by supplying the reference marker for phase 2 in the cycle.
dc Low (DeW) -This signal is driven by the module to indicate that the dc power is not within
specifications or is heingrestored.
Three State (TRISTATE)-This signal forces all of the output buffers to theirhigh·impedance
state. This feature is used only during parametric characterization, debugging operations, and for
module .test purposes.
Back·bias Voltage (VBB)-A -3.0 V from an external supply used for substrate bias.
Voltage (VDD).....Power supply 5.0 V (nominal) voltage.
Ground (GND < ).....:Ground reference.
1-222
Confidential and Proprietary
-
..PreIiminary
I/E Chip Iimhtg
'TheIlE chip.mictocycleisdivided intoeigbt:time slots PI throughP8 shown in Figund. Two .
nonoverIapping clocks and a .synchronization strobe' are' requtted to generate thesephase~ The
ei8ht time slots can be qivided into five. ~ional time slots.-fetch, decode. drive the operands
onto theipput buses, A:LUoperation.and wtjte the results .. 1'he liE chip ismpelin~ .such that the
fetch and write cycles, liU"e. overlapped. The overlap of mknJirJs~~cti0IlS Ularu.i U2 is shown.
PI
MICRO Cl'CLE
WRITE
I
P2
DECOOEVI
I
P3
I P41
ORIVEU10PERANDS:
I
P5
P6
Ul ;>.LUOPEAATlON.
I
I
.LQAl>U2
'; '.,
Figure J. DCJ28 MiCmcycle ~g
The liE. chip is interlaced with the systemthro* thetime.mulijplexed microinsttuction. bus
(MIB < 39:00 > ) and the data address lines (DAL < ThOO»,.I:he"aQ$ess isttansfenedduringthe
first half of the cycle (1)3 and P4) and the~ta is t~tnittl!d~r~eived in the 5e(lOnd, h!Uf of the
cycle and Dtti.. Timw.·
g
,
"',
'
,
'
FW1~I>eset~
Flgut'e lshows the f\mctional elements, bus struc~,and ·~lines o,.tht;.I/Echip. Refer ~
DenS liE Chip Funetional Speciijattion fot detai1edope~i9~·o£t~chip. A brie( deS'eription of
the I/EchipJollows:
Inst:l'tKtiOlt·~ and Decoder (I Bdrt)-.-The I box prefetches the instruction stream,
generates microprogram fork addresses, and provides instmctionjdatatotbe E box. The
instructionp~gl'3mmable 199ic array
(IPLA.tis 19Catedin the.J;b9¥:.
Microsequencer-The microsequencer determines the address ofthe next microiasJ;metiontObe
fetched and executed from the external control store ROM/RAM. Its facilities included an eightentry stack, and two adders for fast next-address generation in conditional branches. It also has
special hardware used to enhance the power of microdiagnostics and handles microtrap generation.
Execution Box (E Box)-The E box contains facilities to implement the VAX instruction set. The
E box contains the general purpose registers (GPRs), temporary registerS" (TEMPs), and working
registers. It also includes a shifter, a 32-bit arithmetic logic unit (ALU), a constant generator
(KMUX), and the shift counter (SC) register.
-
Memory Interface-The memory interface converts program generated virtual" addresses' to
physicaiaQdresses and' governs all data requests of mijn memory or thecachedt also:has facilities
.to improve the performance of common memory management exceptions.
DAf.: Interface-TheDAL interrace COnnects the I/Echip to the external data path. It performs
byte rotation, buffering, and determines when the data on the DAL< 31:00 > .lines is valid.
Mm Interface-Th~ MIB interface connects the I/E chip to the external control store through the
MIB. It receives and checks the parity of the microcode wards that are read from the external
control store, controls the sequencing of the ROM/RAM chips, and oversees the use of the MIB for
passing interchip status signals. It is also used for writing the patch RAM section of the DC327
ROM/RAM chips.
.
Interri.a1 Bus Structure
Five of the internal lIE chip buses are 32-bit data buses and the remaining two are used for control.
The f()l1owing is a brief description of the major buses.
.
Internal Memory Information(IMm < 38:00 > )-The IMIB < 38:00 > lines provide the main
control and are used to transfer the microinstruction to all other logic functions in the chip.
Because the lIE chip cannot stall the clocks, it must execute a microinstruction every cycle. The
information on this bus is v:tlid every cycle. The memory interface logic inhibits write operations
that are associated with a stalled microinstrUction. .
.
Microtest <):0::>';";"The miciotest bus is used t6 transfer 'the results oia conditional branch test to
the microsequencer. The microsequeneef uses thls' value and the branch command field to
determine the next microaddress to be driven to the control store.
Internal DatalAddress (IDAL < 31:00 > )-The IDAL bus connects the DAL < 31:00> lines to the
internal register HIe. It is driven by the memory interface during the address portion of the
microcycle and during the data half of the microcycle if the datais being written by the l/Echip. It
is drivenby'the DAL <31;00 >linesll theI/Echip is executing a read transactiori.
D-stteam Bus (DBtJS < 31:00 > -This bus connects the E box registers to the IDAL bus and IS
driven when the lIE chip reads D stream data or external registers. The microinstruction specifies
the E box register to be loaded from this bus.
AW Bus (AWBUS < 31:00 > -This is the main data bus between the I box, E box, and memory
interface and is used as one of the input buses to the ALU. It also transfers the result of the
computation from the ALU. During a normal ALU operation, one of the operands (inputs to the
ALU) is driven onto the AW bus by an E box register. After the ALU operation, the results are
transferred onto this bus and are then written into an E box register. Whetidata is beitig written
from the E box to the DAL lines, the AW bus is used to transfer the data to the memory interface
that then drives, the DAL lines. It is also used to connect registers located in the Ihemory.intertace
and I box to the E box registers.
B Bus (B <31:00> )-This bus is located in the E box and is driven by Eboxregisters to provide
the .remlUo)ng input to the ALU.
1-224
Confidential and Proprietary
-
DC328
• Specifications
The mechanical, electrical, and environmental specifications for the DC328 are contained in the
following paragraphs. The test conditions for these specifications, unless specified otherwise, are
as follows:
• Ambient temperature (TJ: O°C to 70°C
• Supply voltage (VDD): 5.0 V ±5% (maximum ripple ~OO mV peak-to-peak)
• Back-bias voltage (Vn ): -3.0 V ± 15% (maximum ripple 200 mV peak-to-peak)
Mechanical Configuration
ThemechanicaidimensionsformountingtheDC328132-pinPGApackageareshowninAppendixE .
. Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may caus~ permanent damage to a device.
Exposure to the absolute maximum rating conditions for extended periods may adversely affect
the reliability of the device.
• Supply voltage (VD~: -0.5 V to 7.0 V
• Pin voltages: -1.0 V to 10 V
• Power dissipation (TA =O°C): 7.5 W
• Power dissipation (TA = 70°C): 5.0 W
• Ambient temperature operating range (TA): O°C to 70°C
• Storage temperature range: -55°C to U5°C
Recommended Operating Conditions
• Supply voltage (Vcc): 5.0 V ± 5%
• Ambient temperature operating range (TA ): O°C to 70°C
ac and de Electrical Characteristics
Refer to the DC328 I/E Chip Functional Specification for the de input and output parameters and
ac timing parameters.
Confidential and Proprietary
1-225
• Features
• Contains memory management logic
• Provides tag store for cache memory and backup translation buffer
• Provides functions Eor interrupts, communications, and timing
• Description
The DC329V.Uprocessor memory management (¥drip} Jogic,ooritainedin a 132-pin,pin,grid
array (PGA) package, i11cludesmost of thetnemory management hardware and the tag store for the
cache memory and for a 512-entry virtual·tp.physical address backup translation buffer (TB;snJO).
The BTB supplements the mini-TB that is located in the I/E chip. The cache data and the, DTB
address translation entries are stored in exremal static BAM chips. The M chip also contains
miscellaneous CPU functions such as CPU clock drivers, processor registers, the in1:el'Vatand timeof-day timer registers, interrupt hardware, clock-generation circuits, and four serial-line unitS,
Figure 1 is a block diagram of the DC329 M chip.
<, M\II,<31;~8>'0:
A,
...
,
MlII...;a,,:M;>
~
:..
:b ...
A
...
.
r
.
.~
<...
L,.
I
ADDRESS
TIWj$LATIOI'j
mD
..
lOGIC
/'
~,.
,
;,
~.
.,
)0.
:
'Ii
>-
"'I
TIMER
~,
>-
mCLK
CLOCK
GENERATOR
•
~
.(,).
,..:
.
)P,
UARtlli
4,UARTS
.~H~.- fUAltttT
RECEIVER!
TRANSMITTERS . UN!T2 R
UAlfu:T
iJ.AIl1'3!t.
UARt3T
tmmfrj!
ClKBAR
..
W\RTOIl
UARI'Ot
om
elK
i"
,'Ii
PME
BIINTR·4
tlKSYNC
Io~
G ';'1
I
PCNTL<3:0>
~
ClKDIS
ft
.OAL<3"0>
~
···Ae
4
"~!I'··
i!1'IR$
OUTPUT EN
"REGISTER
,
COMMJI~7:0>
LOGIC
RAM
TEM!'QI\I\RY
fUIITAUSl
,
'fliT:.
CONTROl
} CAl<10:0>
CASHECS
TRANSLATION
BUFFER
\.
IiITlIMISS "
)
.QlII!Ir
WREN<3:Q>
PAJ".<1I:0> .A
CA$IIIi tAG
ARRAY
f1UTAGs)
PIUOIIiTY
INTERRUPT
CONTROLLER
IiiIm'Ii
~
5C"£1r
Figure 1 • DC329 Memory Management Logic Block DiagnJm
1-227
_3·····
.... ~.......... .
• Pin and SignaIDescripticms
The input and output signals and power and ground connections for the 132-pin package are
summarized in Table 1. The table also contains the physical pin locations that are shown in Figure
2. The following paragraphs provide a more detailed description of the inputs and outputs of the
Mchip.
Table 1 • DC329 Pin and Signal Summary
Pin
Signal
Input/output'" Description/Function
K13,K14,G13,
DAL<31:00>
input/output
Data/address lines-Transfers data and
address information to and from the V-ll
chipset.
D2
DALBUSY
input
DAL busy-Indicates thatthe D~L < ?1:00 >
lines are controlled by the porfcontroller.
Al
DALSTALL
input/output
J14,G12,H14,
F13,G 14,F12,
F14,E13,E14,
E12,D14,D13, .
C14,C13,BIJ,
BI4,B12,AI4,
Bll,A13,BlO,
A 12,C9,All,B9,
AlO,C8,A9,B8
BI
DAL stall-Indicates that the data ~urce cannot respond to the data request in the Same
.cycie.
input
Abort'-Asserted to ignore the last chieminstruction.
N12,N13,M12,
P14,M13,NI4,
L12,MI4,L13,
L14,K12
MIB<38:28>
input/output
Microinstruction bus-The primary control
bus to transfer commands and status
information.
B4,A4,C5,A5,
B5,A6,C6,A7,
B6,A8,B7
CAL<10:00>
outputs
Cache address lines-Provid.es physical
address to cache and virtual addresS1:oBTB
PTE.
J1
BCIACLO
input
BCI ac low-Initiates an ac power low
interrupt.
H2
L1
L2
L7
BIINTR4
BIINTR5
BIINTR6
BIINTR 7
inputs
BI interrupts (4-7)-B1 bus interrupt}eve,k14
through 17
output
BTB chip select-Asserted to transfer data to
or from the BTB PTE RAMs.
A2
1·228
Confidential and Proprietary
Input/output* Deseription/Funetion
Pin
B3
'mHEcs
output
M9
CLK·
input/output
Cache chip select-Asserted to transfer data
to or from the cache data RAMs.
Clock.;..,...A MOS clOck signal to the I/E chip;F
chip, and port controllers.
MIO
CLKBAR
input/output
Clock bar-A comPlement MOS eLK sigOal
. to theIJEchlp,Ff1U~a~~port controllers.
NlO
CLKSYNC
B2
inputJputput
Clock synchronization-Provides Phase 2 reference for synchronization.
input/output
Cachemiss......Asserted during cache misses,
load PTE operations, and cycles that miss in
the Mta.
J2
CNSLINTR
K3
CRl)IN'I'R
input
Console, interrupt-Asserted to indicate an
·~blein~l?t ...
input
,' ..
C:or~c:redreadda,ta interrupt-Asserted to
reqUJ::$t an intd:rtiptanlPL 16.
M5,N4,M4,N3 .WREN<3:0;> inputs
PlO
BtinCW'
input
."BTB/c~he wr!te enable::-
BClCic!IOw-lt1&catJsthat the power supply
voltage will be. below .the specified minimum
value;
D1
MERR
output
M chip error-Inforros theJJE chip of an
el'l"Ot wtidition.
P9
MTBMISS
input
. Mini,TBmiss::-::-:1ndicateS.whether a cache or
BTB'a()(less is ri:4uired.• when a mini-TB miss
has occurred.
K2
NIINTR
input
NI inteftupt-Indicates that, atiunmaskable
interrupt is posted.
.
A3
OUTPUT EN
output
Otttput~ble-Controls the outpUt enable
of the ~a'che and BTB.
P3-Pl,Nl
PCMD<4:0>
C2
PCNTLERR
output
Port controller command...... PrQVides)c~m
ma.nds-tothe
portcontrolJer.
,
.
input
Port controller error-Indicates an error has
~inthe port controller during a data
,
,
~
ttansfer.
".
. "
..
C1
PCNTLRDY
input
Port controller ready-Indicates that a command can be sent to the port controller.
P7,N6,P6,M6,
PAL<6:0>
input
Physical addiess < 6:0 > - Provides a physical
or virtual address to the M chip.
CollfidentW,andProp:rictal'y
1-229
Pin
Signal
Input/output· ,Deseription/Func:tion,
M2
PMEOUT
output
Performance monj.tor enable-Indicates the
state of the PME bit in the PILR.
N9
TTLCLKIN
input
TTL clock-A TTL 20-MHz clock signal for
UARTs and timers.
P8
CLKDIS
input
Clock disable-Disables the clock outputs.
MI
TRISTATE
input
Three state-Disables all outputs of the M
chip except for the CLK, CLK BAR, and CLK
SYNC.
G3
UARTORCV
input
UARTO receive-Serial-line input from
UARTO.
F2
UARTOXMIT
output
UARTO transmit-Serial-line output to
UARTO.
HI
UARTIRCV
input
UARTI receive-Serial-line input from
UARTl.
Fl
UARTIXMIT
input
UARTl transmit-Serial-line output to
UARTl.
G2
UART2RCV
input
UART2 receive-Sedal-line input from
UART2.
E2
UART2XMIT
input
UART2 transmit-Serial-line output to
UART2.
Gl
UART3RCV,
input
UART3 receive-Serial-line input from
UARTJ.
E2
UART3XMIT
input
UART3 transmit-Serial-line output to
UARTJ.
C3,C4,CI0,C11, VDD
H3,H12J12,M3,
M7,M8,N8
input
Voltage-Power supply voltage.
C7,C12,D3,D12, V's
E3,H13J12J13,
LJ,M11,N7,N11
input
Ground-Common ground reference.
N2
input
Back-bias voltage-Power supply back-bias
voltage..
Preliminary
VBB
.. All pihs have TTL compatible levels except eLK and eLK BAR.
1-230
Confidential and Proprietary
OC3Z9
-
PreIitninary
l4 13 12 11 10
P
N
i
9 ·8
1
:6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
O.
0
.0
0
0
0
0
0
0
0
0
0
O· 0
0
0
0
0
Q
N
M
0
0
0
L
0
0
0
0
0
0
0
0
0
0
0
P
0
0
0
M
0
0
0
L
K
K
0
0
0
0
0
0
J
0
0
0
0
0
0
J
H
0
0'0
0
0
0
H
G
0
0
0
0
0
G
F
0
0
0
0,>
0
0
F
E
0
0
0
0
0
0
E
D
0
0
0
C
0
0
0
0
0
0
B
0
0
0
0
0
0
A
0
0
0
0
0
1
DC329
0
14 13 12 11
10
9
0
0
0
0
0
0
8
7
6
6
43:' 2
10PVIEW
Figure 2· DC329 Pin As#g?t~1S
Dataladdress Lines (DAL < 31:00 > )-These lines are used for transmitting addresses and data to
and from ~V·llchipset, the PQ~t contro~.andthe:cac:bc! RAM1~.~e:Mchip~eivesaddress and
data ipformaiion~ transn;dts dataon, this:bus .The da~.iJi.validQmy .dtJ;rlngphase 7~hen the ~ta
is frOm the,cilChe da~RAMs. When the,lataish'ol:ntheM>duP.kis valid for>M~es P7 3Jld.)?s.
DAL·B~(DAL IUSY).....This inpgt iS1\sserted lines. When asserted, the OALlines are ahighimpedanceand the DAL STALL'and
CMISS are released by the Mchip. It is '$S$err.eddut~ tachefill:¢yc1es after the po:i:t controller.'has
ac~pted thecomm.and s~t.1;9 it byth,e;:M chj,fl.,Itis held>~the;P9ncontrolleruntil t:h,elast
longw:ordof the cache anopenldonhasblren~ivr;d. 'J;'he ~·controner .a1:l0 $sserts this. ~t
during I/O invalidate cycles to ~nable it to drivetheinv~~te~~onto the.OAf. < 31:0 >. tines,_
DAL Stall(DAt .STALL);-This signal.~)~sse~ when a~ta$O~ .cannot ~P9nd JO a data
transfer requestir} thesapre cycle. Th~resQu~ ~tte<1uest¢ldtheda'ta is stalled until the soorce
can resPQnd. The M chip asserts this'signal when the cache'or bac~pm.nslatU?nbuffer is busy
with a previOQs .conunand~d a new COtnn1al1d isteCt!ived "rhi~ requests the M chip~ It~ used
during the first ready cycle ~£an MREQ read transiu:tiont~~lha~a ca~he ,miss, at¥l when there is a
read miss or a cache write and the PQrt controller is not ready. The Mchip alsoassertstheJ5XL
STArI signal when the lIE chip ~t~!Dpts to read the PTEadderlUid the Mchipisc~atin~ the
result. It is also used tostallthe 'I/E chi!? during the first cycle of the two cycle MXPR read
operations and during the second cycle of the tWo cycle MXPR write openltions if the microcode is
attempting to initiate another operation that requires the M chip. The M chip does not assert this
signal when the DAt BUSY input is asserted. The DAL STAll signal must be deasserted by the end
of phase P4 if it is to remain deasserted for the rest of the cycle.
Confidential and Proprietary
1·231
Microinstruction Bus (MIB <: 38:28> )-This is the primary control bus and the M chip receives
U of the MIB<39:00> lines in the system. LinesMIB < 38:32::> are used as input to the M chip
and lines MIB < 31:28> are bidirectional three-state lines. During the first half of the cycle, the M
chip transfers status information on lines MIB < 31: 28 > and during the second half of the cycle it
receives status information· on. lines MIB < 38:32 >. The M chip receives commands on lines
MIB < 38:32 > during the second half of the cycle. The status information received by the M chip
during the P3 and P4 phases is listed in Table 2. Table 3 lists the status transmitted by the M chip
during phases P3 and P4.
'lable 2 • DC329 MIB Line Status Received
MIBLine
Description
38-35
Write mask bits as follows:
Bit 38-Longword bits 31:24 (byte 3)
Bit 37-Longword bits 23:16 (byte 2)
Bit 36-Longword bits 15:8 (byte 1)
Bit 35-Longword hits 31:14 (byte 0)
34
IB Fill
33
Using DAL
32
Request second reference
The write mask (bitd8:3) indicate to the Mchip which longword bytes are to be written into the
cache and main memory or to the 1/0 device. The M chip uses these bits to enable the cache write
enables if the cache hits on a MEM REQ write instruction. Each bit corresponds to the assoCiated
cachewrite enable output. These bits are asserted to 1 and are supplied to the port controller on the
PCMD4:o outputs; These bits must be set whenever the microcycle is not a MREQ write
instruction and low when asserted on the MIB asserted implies that the byte is to be written.
TheIB Fill MIB34 'line is asserted low when the M chip is not completing a p~ious operation and
initiates a read operation to read the requested VAX instructioniocated at the address present on
the DAL lines during the address half of the DAL cycle.
The UsingDAL MIB33 line is asserted high to indicate to the M chip that thecurtent
microinstruction uses the DAL lines. This bit is used in determining when the current microinstruction has been completed.
The Request2nd reference MIB32 is asserted low to indicate to the M chip that the reference is
unaJjgned'~na that two MJffiQoperationsare required to transfer aIIofthe data. This appues to
urialigned read and unalignedwrite transactions. It is asserted fot the first unaligned data reference
and pre~nts.t;he ~-chip £ium updating the microinstruction that ~()Uld cause it t() reexecute the
memory ~uest (MREQ). The upd~ted address is supplied by the lIE chip~ .
1-232
Confidential and Proprietary
Prelimimtty
31 .
llCJ29
Letigth violation
30
29
IID interrupt request
28
FPD intenuptrequest i
'.
The length :violation MIB31 output reports the rompUiS()nofthe :valueS'contairiedina selected
p~~.O! sy*mlengtl;tremte!Yfith,qe·MVA~He.:tft~MYA~in ~cle(~},the.first
microcycle that can branch on the new sta.~
.. .is(n+:4).~
.
,"
,
; '-
,
-
,-
~,
The systemsp~e M$.30 outp~t ~,~qyil\l~ent to th~;vallltt'9£~N'A~l,
The lID interrupt request .MIB29.outputis the intetruptftequest genel'atedrh¥the iirtettupt
controller, It is asserted high . n there is"~'I?Mdi:ni tmiSkable .mrruptinputthllt baSil: wIue
,above .the.currentI}lL,. 'YJJel}.1th~ .isan. H~W~ int~l'!tJJiI!::pen4in&,ort~~,;ISTA1'US
H,t\1I~it is set:WJjtitlglto t~ SI~It> the ~>OF~ I~Wt.T$~f~a~e.in f:he intert;l;lpt
Silltus on,~.~; l1ris·.isin~gpntom~.in~~~,~Pl,lts t:luu;.~cal,lSeintertupts .
•There lsa ~betweettchqWsonea£tlutse re~ters ~;~~~ o;that~on tJ:te lID
input·
The FPD interrupt request MIB28 'output'. is the, interruPt ·.request generated by the interrupt
contronet. It is asserted. high when 'there is apendingmuk~intttNpt1np\tt that has a wlUe
above the currentm!;; il).f whenmunmaSkableinterl'1.lptis:~ed,;The ~istheSame '.IIS for
the llD ilitettupt request status signal.
.
The microinstruction formats that are recognized" dn
MIRdurlngphasesP7 aiid PS
shown
in FigtU:e 3; .
····'r
the
are
MXPR:
MIS
MEM REO:
Figure 3 • DC329 MIB Microinstrnction Format
Cortfidentiahmd Pmprietary
"1.233
-
Preliminary
;'OCJ29
Abort (ABo'RT)-This input i~ ~~rtedwhel'l th(d~$tinstructionon theMIB intheprevious P7
and P8 phase is to be ignored. Becausethe AB"C5RTsignal is generated by the lIE chip, the M chip
may not be executing the same microinstruction as the I/E chip and therefore it applies to the
instruction that the I/E chip is executing. When this occurs, the M chip ignores the abort. If the M
chip asserts the MERR signal, the ABORT signal will be asserted by the lIE chip in a subsequent
cycle, causing a microtrap to occur. This ABORT signal must be deasserted by the end of phase 3 if
it is to remain deasserted for the rest of the cycle.
Micro Error (M ERR)-This signal is asserted by the M chip to inform the I/E chip of an error
condition. It causes the I/E chip to abort and microtrap when there is a parity error on data read
from one of the tag arrays in an MREQ, IB fill, or MTB miss operation and when the port controller
asserts a port control error due to a data error on an MREQ read or write operation.
BCI ac Low (BCI ACLO)-This is an interrupt input to the M-chip. When asserted, an interrupt is
requested at IPL 16. This signal is sampled each cycle and is not latched by the M chip.
PortCobtroDer Error (PCNTL ERR)-This inputinforms the M chip that an error has occurred in
the port controller as a result of a data transfer operation.
Port Controller Ready (PCNTL READY)-This input informs the M chip that the port controller
is ready to accept a command. When deasserted and the current instruction requires the port
controller, the M chip will assert the DAL STALL signal until the port controller becomes ready.
Cache Address Lines (CAL < 10:00 > )-These outputs provide the physical address to the cache
during cache read and write cycles and the virtual address to the BTB during PTE· read and write
cycles. The cache data array is organized into 2K longwords that require 11 address lines. The B'tB
contains 512 PTEs of one longworcl each. The CAL < 10:00> outputs reflect the address sent to the
M chip on the DAL<.31:00> lines during the first cycle of cache read operation and MTB miss
cycles. The source of the CAL < 10:00> information is the MVA for the load PTE operation.
During cache fill operations, the M chip modifies the value of the CAL < 1:00> lines by
incrementing them by modulo four (starting from the value of these bits supplied on the DALlines)
each time one of the four Iongwords are received. The CAL line value is derived from the address
received on the DAL < 31:00 > lines or from the MVA.
Cache Chip Select (CACHE CS)-This signal is asserted when data is to be transferred to or from
the cache data RAMs during read and write operations. The direction of transfer is specified by the
WREN <3:0> lines. The RAMs address is on the CAL < 10:00> lines.
Write Enable (WREN < 3:0 > )-These lines specify the direction of the data to the cache and BTB
data and parity RAMs. When active, the data for the associated byte in the cache or BTB RAM
arrays is written. The chip selerct lines determine which bank of cache or BTB is to be written. The
lines are asserted during the following:
• An MREQ write operation that has a cache hit. The write mask that is received by the M chip
during the MIB line status transfer is used to determine which of the 4 bytes in the longword are
to be written.
• When the cache is written with data on a cache fill. All 4 bytes are written and the write mask
contains all ones.
• During an MREQ read operation of the PTE. ,When the PTE returns from memory, it is loaded
into the PTE store and the write mask contains all ones.
• During an MXPR write operation to the PTE. All 4 bytes are written and the write mask contains
all ones.
1~234
Confidential and Proprietary
BTB Chip Seleet (BTli eS)-This signal is .as$erted when data is to be transferred to Of from the
BTB PTE.UMs dtll:':il'lg read and write opet:a.tions. The ~ion of transfer is speci£ied.by the
WREN < 3:0 lines. The RAM address is on the CAL < 10:00> lines.
Output Enable (OUTPUT EN)-This output is used to enable the cache and BTB data chips.
When asserted, the selected bank of data. RAMs will drive the DAL lines.
Caclte Miss (~~This signal is an 9U~p,Ut%>~~ M ~pw~en the . :'DA""L""'B""',tJ""'S""y
. signal is not
asserted aad is an inPut to the M..chlp wheD:the fiAt IftiSYsign8I iussertetl It is asserted on
MREQ write and read operations that result in .cache misses,m fills transactions thlIt rt:sult in
cache misses, load PTE operations, and MTB miss cyclesth'it: reSult in a miss in the BTB. When
asserted by the M chip and the MTBtniss is not true, this !lign~#@lcates to the PQrtC(lntrol1er !hat
the command that was sent to it is to be executed. The ~l~nal is deasserted by the end of
phase 4 if it is to remaindeasserted for the rest of the cycle. DU1'ing cache read misses and load PTE
operations, the CMISS signal is asserted by the M. chip for each cycle up to and including the first
cycle in which the port controller is ready. The port controller then asserts the CMISS signal until
the completion of the £i11operatiol}.TheMF,hip $0 waits £ort~ePQrt C()at~ to ~~ ~Y
during. write CYcks- The CMISS~put.is~ to.~cate~tthe l>4. chlpisto perior~an. 1/0
~te cycle. Theport~ntroner d~this bydeasSf!rtingthis.,S~at: thesame time. thilt the
DAL StALL andDALBtJSY ~ignals:u-easserted.
,....
.. .
Port Conunand (PCMD <4rtl»--These outputsprQVide thecotrul,lQ,lld to:the PQrt>controller
dur~ phasesP3 and P4 and the write maslc d)Jl~pbaSf!~.1'1al1c.i P8.Theco~and is eJtectlted
only by. the !?Ort controller Hthe ~ is~ted~tet4t¢at.cyde .. The wrl,te .• mask is used by
only by the port controller during write openltions.
.....
'.
.
Clock (CLK)-The eLK signal is pM9S levelinput'1'he~~p~%~,thisputpl,lt back ~o its<;l£ as
an input and it is used on the module by theI/¥cMp,F clUp,,~~ portcoP~lk:r chips, A transition
of this signalfrom ll. 0 to 1occurs at the beginningofev!=ry )-These inputs· provide part of the address that was
previously referenced on the DALlines. Table 4 lists the address bitcorre1ation for a virtualaddress
(MTB MISS asserted) and for a physical address(MTB MISS not asserted).
18ble 4 • DCl2' PAL Line V1rtual and Physical Address Correlation
Virtual Address
DAL Line
PAL Line
31
0
Physical Address
DALLine
PAL Line
< 11:6>
<6:0>
< 16:11 >
< 6:1 >
Mini·TB Miss (MTB MISS)-This input is asserted by the IfE chip when there is a mini-TB miss.
The M chip uses this signal to indicate whether the BTB or the cache is to be accessed during an
MREQ operation. It is aqualifieron the address received on the DAL and PAL.<6:0> linesthat
indicates whether the address is virtual or physical. When asserted, the M chip transfers the virtual
address onto the CAL < 10:0> lines and reexecutes the last microinstruction.
BI Interrupt (BI iNTi < 4:0 > )-These are interrupt inputs to the M chip. When a line is asserted,
an interrupt is requested on IPL 14 through IPL 17. These signals are sampled during each CYge and
are not latched by the M chip.
Console Interrupt (CNS! INTR)-When asserted, an unmaskable interrupt is posted. This signal
is sampled each cycle and it is not latched by the M chip.
CRD Interrupt (CRDI'NfR)-When asserted, an interrupt is requested at IPL 16. This signal is
sampled each cycle and it is not latched by the M chip.
NI Interrupt (NI INTR)-When asserted, an unmaskable interrupt is posted. This input is sampled
each cycle and is not latched by the M chip.
ac Low (BCI ACW)-This input is asserted when the ac voltage is below the specified limit and
initiates an interrupt request on IPL 16. This input is sampled each cycle.
de Low (BCI DCW)-This input signal is asserted by the power supply when its output voltage is
about tobe lower than the specified minimum value. When asserted, all.outputs of the M chip
become a high impedance except for the CLK, CLKBAR, CLK SYNC, and OUTPUT EN outputs.
The CLK and CLK BAR outputs are normal. The CLK SYNC signal and OUTPUT EN signals are
deasserted.When the BCI DCW signal is deasserted and the CLK and CLK .BAR signals are
asserted,the first assertion of the CLK SYNC signal is within four or six TTL CLK IN cycles. After
this signal is deasserted, the M chip will remain in a reset state and the outputs will be a high
impedance for the first three cycles of the CLK SYNC output. When the CLK SYNC signal has
pulsed a minimum of four times, the M chip will respond to microinstructions on the Mm, and the
high-impedance outputs will be enabled.
Voltage (VBB)-ThiS input is used to supply the back-bias voltage to the module.
PerfortnatK:e Monitor Enable Output (PME OUT)-This output has the same value as the PMEbit
mthe Pl length register (PILR). Refer to the Register section for a description of the P1LR If the
state of PME hit changes, the PME OUT signal will be valid during phase P4 of the following two
cycles. If the PME bit does not change, the PME OUT signal will be stable for phase PI
through P8.
1-236
Confidential and Proprietary
TTL Clock Input (TTL eLK IN)-The TTL clock input is nominally 40 MHz and is used to
generate aUdocksignaJs to the V-U chipset. The M chip provides a 20·MHz MOS level dock pulse
to the·other¥l1chips by dividing the input. by two as the reference.
UART Receive and transmit (UARTO R-UART3 Rand UARTO T-UART3 T)-These lines provide
the serial line inputs from the fout UARTS and serial.line outputs to the four UAR'Th. Each input is
asynchronous to the"reterence clock
Voltage (VDD)-Power supply voltage 5 V (nominal)
Ground (Vss)-Signal ground reference .
• Functional Description
The DO 29 contains the functions shown in Figure 1 and is d¢SCribedas follows.
• Address translation logic
• Backup translation buffer tags (BTB)
• Cache tag array
• Clock generator
• Control logic
• Priority interruptfhalt controller
• RAM temporary regis~rs
• Timer logic
• FourUARTS
Address 'lianslation Logic
The address translation logic (ATL) calculates a page-table entry address when the page~tableelltry:
necessary to translate a virtual address.is not in themini.Q~. b~p tl;aIilSlation buffet's. The' A'lL
contains the following registers;
".
.
• PO base register (POBR)
• PO length register (POLR)
• Pl base register (PlBR)
• Pl1ength register (P1LR)
• SO base register (SOBR)
.. SO length registet' (SOLR)
• PTE translated address (PTE ADR)
1-237
...
Preliminary
Backup Translation Buffer
The backup translatitln buffer (BTB) is ad.irect mapped arraywith 128 entries,grouped into system
and process spaces as determined by bit .31 of the virtual address. Each entry'containsa tag that
corresponds to a group of four page-table entries (PTEs) and four valid bits, one for each PTE, The
512 PTEs are not included in the chip and are typically industry-standard RAMs. This array is used
on MREQ or IB FILL operations when the MTB MISS signal is asserted and on the MREQ read PTE
operations. It is also used in some MXPR instructions and contains the following registers.
• Memory address register (MAR)
• Missed virtual address register (MVA)
• Invalidate address register (INVAR)
• Refresh address register (REFR)
• BTB tag, valid bits, and parity bits register (BTB ENTRY)
• BTB invalidate register (lITB INV)
• PTE array register (BTB PTE)
• BTB status register (BTB STAT)
• Error status register (ERR STAT)
Cache Tag Array
This section contains 128 direct mapped cache tags each of which is mapped to a 64-byte block of
contiguous physical data. Each tag has four valid bits to indicate the validity of each octaword (16
bytes) in the allocated block. The registers in this section are
• Cache tag, valid bits, and parity bits (CACHE ENTRY)
• Cache status register (CACHE STAT)
Control Logic
The control logic is distributed throughout the chip. It receives the control inputs and generates
the internal and external control and contains the following registers.
• Indirect MXPR register (INDIR)
• Indirect address value register (INDIR ADDR)
• No-Op diagnostic register (NO DRIVE)
Clock Generator
The clock generator divides the 40-MHz TTL CLK IN input by two and generates the dock sources
(CLK, eLK BAR, and CLK SYNC). It also receives the CLK, CLK BAR, and eLK SYNC inputs so
that it can generate the M chip internal phases.
1·2.38
Confidential and Proprietary
Pte.Iim·
. mary
Priority Interrupt ContmDer
. .
The ir).terruptsectiO,n.of. the .M chip receives the internal arld external interrUpt requests and
reports an active interrupt if there is an interrupt whose priority is higher than that of. th~
processor's current priority. The software HALT request in the ISTATUS register is reported with
the interrupt requests during the MIB status transaction. It also containsh~ware logic to support
REI instruction. The registers contained in this section are
.,.
.'
• Interrupt prioHtylevel (lPL)
• Interrupt status register (ISTATUS)
• Asynchronous system trap level (ASTLVL)
• Processor status longword (PSL)
• Processor statUs longword temporary register (PSI. TEMP)
• Software interrupt status register (SISR)
RAM1emporary Registers
. ..'
.
The RAM temporary registers are MTi::MPO thn:>ijghMTeMPlti
TnnerLogk
The
logic consists of the interval counter (IVC) and time-o~-<:!a~ ~s,t~('IOI)~).'l11~IVC:is
used to provide a source of interrupts at a repeatable ratethatcari&p~edby ~f~8.rein i
IlS steps. The mDR supplies the real-time clock £unction.te£1ecrlrigtheirel4~·timeJ~mitslllSt
initialization. The TODR alsO is used to piov~~pCriOdiC~?f~.~ka:ble,i,q~Pts . ~
timer
1.28 seconds. This logic oontains thcdolloWing registers:'
.'
'.
..
.,. , .
.
• Interval counter.control and status register (ICCS)
• Interval counter·vaIue register (ICR)
• Next interval counter value register (NICR)
• Time-of-day register (TODR)
• Time-of-day prescaler register (TODPRE)
Universal Asynchronous Receivers and Transmitters
Each of the four universal asynchronous receivers and transmitters (UARTO through DART3)
contain a status register and a data registet.
The mechanical, electrical, and environmental specifications for the DC329 are contained in the
fonowing paragraphs. The test conditions for the parameters specifications, unless specified
otherwise, are as follows:
• Ambient temperature (T,J: O°C to 125°C
• Supply voltage (VJlI): 5.0 V ± 5% (maximum ripple 200 mV peak-to-peak)
• Back-bias voltage (VBB): -3.0 V ± 15% (maximum ripple 200 mV peak-to-peak)
Confidential and.Proprie~
1-239
DC329
Mechankal Configuration
The mechanica1dimel1~oQs for moUnting the DC329 132-pin CERQUAD package are shown in
AppendixE.
.
. . ..
.
. Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause per~anentdamage to a gevic~.
Exposure to the absolue maximum rating conditions for extended periods may adversely affect the
reliability of the device.
• Power supply voltage (Voo ): -0.5 V to 7.0 V
• Back-bias voltage (Vau): -7 V to 0 V
• All other pin voltages: -1.0 V to 10 V
= O°C): 5.25 W
Power dissipation (TA = 70°C): 3.5 W
• Power dissipation (TA
•
• Ambient temperature operating range {TAl: oo~ to 70°C
• Storage temperature range: -55°C to 125°C
• Power supply voltage (Vcc):5,O V±5%
• Arribient temperattlreoperating range (TA): O~C to 70°C
8C
and de Eledl'kal Cbara~tics
Refer to the DC329 M Chip F.unctional Specification for the dc input and output parameters and ac
,
.
timing parameters.
1-240
Confidentiru ~nd PrOprietary
. Features
• Contains a fraction processor and exponent and sign processor
• Accelerates a subset of the VAX instructions
• Description
The DC330 V-ll processor fIp~ting.pomt,accelerator, contaiped in a 132~pin grid array {PGA)
package, receives opcodesahd normalizedfloating~pOint dperands from the lIE chip, and exeqJtes
the instructions faSter than lfE chip'microCode. It is optimized to accelerate a subset ohre'VAX.'
instruction set. Figure 1 is a block diagram of the DC330 floating-point accelerator.
.
ClK
CLKBAR
CL.KSYNC
CLOCK
lOGIC
PH12
.
'ffliS'fA"i'E
OCtO
A
<
.
,
.~'.
'-c,
FRf'.CT!ON
...
PROCESSOR
DAt.; 31:00::-
'" DAlBUSY
DALSTALL
ABORT
FBOXN
.
II"
OAL
INTERFACE
FBOXZ
110
...
<""
MTBMISS
MIRTEST
OPEltVALID
OATAOUT
<:= --
~ ~
r-
.
NORM VALUE
'"
'"
SIGN, ALIGf'lMENT
"I"
STATUS
l-
EXPONENT·
1'ROCESSOR'·
r
Ill"
.
I II
1
'.
DECOOED'Qf1CODE
.'
j:
Ir
Itm;RNAL MIQ1QWQ1!o
.,
,
I
II
DECODED
EXTERNAL· MICfIOWOfID·
"
...
'
.,
'.
.i
...
...
10AL <:31:00 >
....
MIRTEST<5:0> )
I:
j
..
CONTROL
STORE
..........
J
I--
'
MIBSYNC
1
MI8<35-:15>
.liB
...
,t'"
INTERFACE
','
..
Figure .1, DCJ30FJoating-poim fJeceJerator Block Diagram
1-241
-_._..
_._--_._------------------
-,
,
D..-1:_:_A
. _'.
.1;" J."ftI,?UU~,
DC33()
• Pin and Signal Descriptions
'The input and output signals and power and ground connections of the DC330 are shown in Figure
2 and are summarized in Table 1. Refer to the paragraphs that follow for a more detailed description
of the signal functions.
Thble 1 • DC330 Pin and Signal Summary
Pin
Signal
Input/output
De~ptionfFunction
DAL<31:00> input/output Data/address lines-Transfer data, status, and
B3,A4,B6,
B8,B9-Bll,
address information to and from the F chip.
C12,C4,C5,
A6,A8,A3,A5,
B7,C8-Cll,
C13,B4,B5,A7,
A9,All,A13,
B13,C14
J2
DALBUSY
input
DAL busy-Indicates that the DAL<31:0> lines
are controlled by the port controller.
Dl
DALSTALL
input
DAL stall-Indicates that the data source cannot
respond to the data request in the same cycle.
N5,P4,M5, MIB<38:15> input
N4,M4,N3,
M3,N2,K2,
]lJ3,Hl,L2,
Microinstruction bus-Transfers microinstnictions, synchronization control, and opcodes.
Ll,K3,Kl,
G3
MTBMISS
input
Mini-TB miss-Indicates that the mini-TB in the
IfE chip has missed.
I/E chip is
G2
lID
input
Input instruction-Indicates that the
starting a new VAX instruction.
Fl .
ABORT
input
Abort-When asserted, the last instruction is
ignored.
El
TRISTATE
input
Tristate-Disables all outputs of the F chip.
Gl
DeW
input
dc low...,...Asserted for 70 illS after the power supply
voltage is within the specified value to initialize
theF chip.
F2
FBOXN
output
F box N code-Indicates a negative value or an
exception to the I/E chip at the completion of a
floating-point calculation.
C3
FBOXZ
output
Fbox Zcode-Indicates a zero value to the lIE chip
at the completion of a floating-point calculation.
Confider)rial-.nd Proprietary
-
Ym
Signal
Input/output Description/Function
M6
OPERVAUD
input
Operand valid-Indicates the successful assembly
of the operand.
P5
DATA OUT
output
Data out-Indicates that the F chip read result is
pending.
E14
PH 12
output
Phase 12-Internal phase 12 output.
H12,H13
CLK
input
Clock-The MOS clock signal from the lIE chip.
G12,G13
CLKBAR
input
Clockbar-A complement MOS eLK signal from
the I/E chip.
J14
CLKSYNC
input
Clock synchroniza,tion--:-A synchronizing clock
signal that indica~ T, of the 200 ms microcycle.
K14,L13,
L14,M13,
L12,M12
MIR 9-4
outputs
Microcodetest-Intet1lal test bits MIR 9 through
MIR4.
C6,D12,D13, VDn
E2,E3,F12F14,GI4,M8,
N8,P8
input
Voltage-Power supply voltage.
C7,D2,D3,
Vss
E12,E13,F3,
H2,H3J12,
J13,K12,K13,
M9,N9,P9
input
Ground-Co.!ll1DOD ground reference.
Preliminary
Confidential and Proprietary
DCJ30
1·243
...
De3l0
14 13 12 11
10
..
9
8
7
6
5
4
3
2
p
00000000000000
P
N
00000000000000
N
M
00000000000000
M
l
0
0
0
000
l
K
0
0
0
000
K
J
0
0.0
000
J
H
0
0
000
H
0
DC330
GOO
0
000
G
F
0
0
0
000
F
E
0
0
0
000
E
D
0
0
0
000
D
COO
0
000
C
B
00000000000000
0
B
A
o
A
000
14 13 12
11
0
0
0
0
000
0
0
0
0
0
0
0
0
o
10
9
8
7
6
5
4
3
2
0....
PACKAGE
IDENTIFICATION
TOP VIEW
Figure 2· DC330 Pin Assignments
Data/address Lines (DAL<31:00> )-These are bidirectional, three-state lines that are used for
receiving operands, transmitting results, and for reading and writing the control/status register of
the F chip. Addresses are received from the DAL lines for detecting unaligned memory references
and to properly assemble the data.
DAL Busy (DAL BUSY)-This synchronization signal is driven by the port controller to indicate
that it is driving the DAL < 31:00 > lines. Any microcoded data that was transferred during the
cycle is ignored and must be sent again. The DAL < 31:00 > lines are a high impedance when this
signal is asserted.
DAL Stall (';::n"'lA,L';"·-:;S.::;tr.l\";"L";"'L·)-This synchronization signal is driven by the V-ll chips to stall the
microinstructions so that operations that require more than one cycle can be completed. It is used
when the I/E chip reads a result of a calculation that is not completed.
Abort (ABORT)-When asserted, it indicates that the microword received during the last T150T200 phase is not valid and should not be executed.
de Low (DCW)-This signal is asserted for 70 ms after the 5-Vdc power is within the specified
limits. It is used for initializing the control sequencers in the F chip.
F Box Negative (F BOX N)-This condition is transferred to the liE chip to indicate a negative
result upon completion of a floating-point calculation. It is also used to indicate exceptions.
F Box Zero (F BOX Z)- This condition is transferred to the ljE chip to indicate a zero result upon
completion of a floating-point calculation.
1-244
Confidential and Proprietary
-
Initial Instruction ~e (DD)-This input indicates that the I/E chip is .sqtttfug ~.~ ..~
instruction and that a newopcode may be transferred to the F chip. If a calculation was in progress,
it must be aborted anet the'new instruction started.
"
., .
.
~str1,IWonBqs(MIB <)~MS > >-Theselint;$ C.9ntail1.~mi.:;roinstruction t1"Q.1ll·~.r150 to
T200and provide $y~Qiz~ti0n ~oPtrol £ro~,. t~e·');'O ttittOO. ,
.
Mini Translation Buffer Miss (MTB MISS)-This input is used for DAL line synchronization. I~
indicates that·theMini~TB in the'IfE'chip has missed data; and that· a Pageta91eentryis lJeing
transferred from the BTB,OQ the DALlines. The .cut:tent miq:piAstru.ctiof1 ~h~Id;b¢ stall~.
Operation Valid (OPER VALID):-This is an input sequencer. test signalthatin )"0'T4e~~~,~es~,!l~tput~c~~.the,.Y~~.~£;the
inter~microinst;uction regisj;¢t )\M:!R<9;4?) .. ~, . lU"e. ~~req'(iillddri~n;by ~n~
devicesand~nal plillup.te$~tors of.lk. ~,t;equ~r; •. ~in~rn~~~ changes'ev~
100 ns at PHIl apL1'flII5.
CIock.(CLK)-Thissignalis,the·MqS'clocl<..input~.the,'M:';chip.andis.us~.JO.·gene;a~.the
internaltitiUng.. The CLK inputbasa~of50 ,nsanti,is,highidttting odo..phases.
Clock Bar(Cl.K IWI)":'"TIiis signal is theoofuplement '6£theMOS CLKsignill'£rOfn the M Chip
arid is used·w generate the intefnilldming. Th¢CLl·.BAR.inputisthe.no~pping inverse of
the CLK signal.
Clock Syncltroruze(ctK SYN~)-1'hissigha.l ih'd1ctafuS time~T~o£tbc! 200fismicrocycle; Ittisesat
time T175 and £allSafT25.
.
,
i
.
Pb8se12(PHI2Y':;"This rstheintema1 PHI2 sigrial'tftitt'is inverted andbttfferedby an 6pen Source.
An extemal1-k pulldownresiiltOi-'isrequired.
.
.
1Httate ('MIS'fAfE)..-.Causes the DAL<31:00 >. FBOX Ni FBOXZ; and DA'LST.fii:U.outputs to
beeomea high itripedance. . .
. ..,
,\
\1Qlmse (Vnn ) -ThePc>weI ~upply yq!~<; t§the 11 pg~~' iOpu~
~~.,'
,'<,
"
t -'";
:,
'
'
~,,"
-'
,
,
:,,:""
.',',"
)'_".',
","'.,
",~
,J;~,'
(." , f . "
~ (VsJ-The powe!;. supply~turn and signal»t'und tO~ ~3, ifQuJild input pil:l!1r
~tina·PQint Jn~Set
. ' . ,'. ....•.. . . . ."
TheFchip isoptiml.zedto.ac~.~ f~~ ~~Iil~oftw..VA¥ .il:l!1t!'Uttion~t.Jie£erto,the
VAX· $Ylltem Re£~rert,ce Manuai.(s"lU4) ·foll··a. Clilmp~4escript;ionq£ thf.! o~tions. It.does not
execute the PDP-ll compatibility mode instruction set.
ADDF2.AODP2"ADD(12, APDF3, ADQDJ, APDG},~\.lBFZiSt1l}P~t,S:PBG?,StJ:SFl, S\.lBDJ,
SUBGJ, MULF2>~Um2, ~ULG2;,MT;1.LF3, ~f!JLP~i;¥UI.G3,,?lNF~~,.QIVD2jD:rvv2, PI~3,
DIVD3; DIVG3,PQLYF.J;'0IXl),PO:rXQ,C¥Pl1,. CMJm,CMPO, CVTLF, OJTLD,CVTLG,
MULI2, MULL3, DIVL2,DIVLJ, EMVL,an,d EDIV'
Itexetures ina nonoptimizedmannerthe folldwing$ubset ofrthe VAX instuction set.
ADDF, .AnnD,·ADDG, SUB'F,SUBD,'SUBG,'MULF,MULD, MUtG, DIVF, DIVO,DIVGPOLYF,
POlYD, POLYG, CMPF, CMPD, CMPG, CVTIF, CVTLD, CVTLG, EDIV' and EMUL. .
. .liD
Preliminary
• Functitmal Operation
The F chip operates in the 200-ns cycle of the synchronous V-ll processOr system. It receives
microinstl1lctions from the V-ll cont~l store that can initiate sequences in the F chip controlled by .
the internal control store. The illternal opeJ.'ations of the F chip cycle are performed at 100 ns.
Figure 1 shows the main logic elements described in the following paragraphs and includes the
following:
• A·DAL and MIB interface
• A control store memory
• Afraction processor
• An exponent and sign processor
• Clock logic
DALInterface--The DAL interface conneCts the F chip to the DAL < 31:00> lines. Together with
theMIB interface, its conttollogic deterfuines when data on the DAL is valid. It provides the
interfaces between the external DAL lines and the internal data paths, and it formats the data
internally in a standard floating-point form. It also detects unaligned data and latches and rotates
the data to the proper format. It detects short literals and unpacks them into the standard floatingpoint formats. The DAL Interface also contains the Fchipcontrol and status register (CSR) that is
used by the I/E chip microcode to determine the exceptional conditions that may occur.
MIB Interface-This interface connects the F chip conttollogic to the microinstl1lction bus (MIB)
and contains the currently executing external microinstruction, the current opcode and some of the
DAL line synchronization bits. h contains logic that decodes the current external microinstruction
and opcode, sending control information to the DAL interface and control store.
Control Store-The control store is a 160-word by 36-bit ROM that provides the internal
microinstruction for the F chip. It also contains the simple microsequencer.
Fraction Processor-The fraction procesSQr contains the 67-bit. data path and control logic. It
accelerates the execution of the VAX floating-point ADD, SUB, MUL, DIV, and POLY instructions
on the Float, Double, and grand data types.!t also accelerates the MULL and DIVLinstructions.
The fraction data path contains a registerfile of two temporary and eight constant registers, a 67bit arithmetic logic unit (ALU), a 67-bit shifter, registers for storing the ALU information; shifter
data and Q data, and a shift register able to shift up to 3 bits at a time. The operands are assembled
in the I/O register that forms the interface between the fraction data path and the DAL interface.
The fraction control logic receives encoded control signals· .from the control store (internal
microinstruction) and MIB Interface (external microinstruction}. It decodes these signals and
drives the data-path control lines.
Exponent and Sign P:rocessot-The exponent processor is a 13-bit data path with control logic. It
allows calculations tobe performed on exponents and signs of operands in parallel with operations
in the fraction processor. The data path consists of a four location dual-ported RAM with zero
detection on each output, an ALD, and latches for holding ALU data. A PLA is included to detect
certain cases ·of exponent differences and a path for normalization data to get from the. fraction
data path to the exponent ALU. Literals can be transferred .to the exponent data path from a
dedicated' ROM.
..
1-246
Confidential and Proprietary
-
DC330
Clock Logic-The clock logic receives the V-ll high-level, 50 ns cycle time dock signals and the
TTL-compatible 200 ns cycle time phase signal. It generates clocks that allow the DAL and MIB
interfaces to synchronize to the 200 ns data transfers, and the internal data paths and control
machines to cycle at 100 ns .
• Specifications
The mechanical, electrical, and environmental specifications for the DC330 are contained in the
DC330 F Chip Hardware Specification. The test conditions for the parameters in these specifications, unless specified otherwise, are as follows:
• Supply voltage (VDD): 5.0 V ±5% (maximum ripple 200 mV peak-ta-peak)
• Back-bias voltage (VBB): -3.0 V ± 15% (maximum ripple 200 mV peak-to-peak)
• Ground (Vss): 0 V
Mechanical Configuration
The mechanical dimensions for mounting the DC330 132-pinPGApackageareshowninAppendixE.
Absolute Maxinuun Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to a device.
Exposure to the absolute maximum rating conditions for extended periods may adversely affect
the reliability of the device.
• Power supply voltage (VDD): -5.0 V to 7.0 V
• Power supply voltage (Vss): -3.0 V to -6.0 V
• Pin voltages: -1.0 V to 10 V
• Power dissipation (TA = lOO°C) 3.5 W
• Power dissipation (TA =O°C) 5.25 W
• Storage temperature range: -55°C to U5°C
Recommended Operating Conditions
• Supply voltage ~t/o\itpUtl .
Data/address lines-Time-multiplexed data and
~$S.b1,lS.
43-44.,
47,60
17-18
BS < 1:0>
output!
Blink'select-These time-multiplexed signals define
theitypeo£ physical address on the data/address bus,
and il;l~~~~te ifeithera each!! memory~~s or a force
miss occurs.
j " -.'.' .,'
•
-
.-
'-, -
~.
-
,
-
-'
19
MAP
output'
Map-This time-mulitiplexed signal indicates if the
, I/O ~pis~nabled (}r ifa DMAgtant ocC\lrs.
2-5
AIO<3:0>
output'
Ap~sinput/output-1'hese signals indicate the type
of· transac~ion . currently being executed" , i.e;; read,
'·'write/or'fACK.
" "
40
ALE
outputl
Address Ultchenable-Lat-ches addresses, AIOcodes,
L·., .". _, '.
i
mape:tlll~l~~ignals~and d.1~BS C()ntro1si~nals.
Bliffet 'ci:mtrol- InQicates, i:h~~cti¢n \6£ data on .the
. OAL bus. The line is active (low) when the DC} 111s not
driVi~gwi:he DAL bus.
41
BUFCTt
outpufl
38
SCTL
output'
39
STRB
o';ttPUt'
29
PRDC
outputl
Predecode strobe-Indicates when the prefetchbu,tfer
is being decoded as the next macroinstructi<>o,.
20
ABORT
input/outpue
Abort-Indicates that an abort condition exists, i.e., a
memory management or address error, bus timeout,
nonexistent memory, or parity error.
28
MISS
input'
Miss-RepOrts the hit or miss status of the current
cache memory entry lookup.
42
DV
input'
Data valid-Set to latch data into the DC}11.
32
CONT
inpue
Continue-Used to terminate all extended cycles.
27
DMR
input'
Direct memory access request-Used to force a current
cycle to be extended.
10-13
IRQ<3:0>
input'
Interrupt Request < 3:0> -Four maskable interrupt
request lines.
9
HALf
inpue
Halt-A low-priority nonmaskable interrupt that
forces the system into console mode.
8
EVENT
input'
Event-A maskable interrupt that forces a trap
through vector location 100.
."'
~
Stretc;~c;?ntrol~Ideritin~s 'the extended,pOriiori of
stretCheclcycles. The edges can be used. to strobe data.
$~r?~""":General purpOse Strobe signal.
,
. ConfidentiallUlcU\!Oprietary
·"PreJiminary
Pin
Signal
6
input'
:Powerf!ill2A high~prioritynonmaskable interrupt that
forces a trap throughvectodocation24:-
7
input'
Floating·point enable-Reserved for a future FPA
coprocessor implementation. A high-priority notlmaskable interupt that. forces a trap through . vector
location 244.
Used 'to report parity errors.
14
PARITY
input'
35
CLK
output2
. Clock-An output for intra-hybrid and diagnostic use
only.
34
CLK2
output1
Clock 2-An output with identical frequency as eLK.
Can be used as system dock.
.
33
INIT
input'
Initialize-:Initializes or resets the system by forcing it
through the powerup procedure.
36
XTALI
input
Crystal input-External crystal input
37
XTALO
output
Crystal output':"'-External crystal output
input
Voltage..,.....Power supply voltage
I"~
16,46 . Vee
~--------------------
15,45
GND
input
Ground~Ground reference.
1
TESTP
input
Disables all outputs.
31
TEST22
input
Disables the dock outputs .. Permits external logic to
drive the DC] 11 clock circuitry through CLK output.
'TTLlevds
'MOS levels
, 1.2;2
Confidential and Proprietary
-
. 'Nlinsinary
Figure 3sbows the input and output signals grouped according to signal fuhcti.oo.:
DCJ11
........_
IRaQ - - - - I
.'- ,
IRQ,~; ........_ _l.r
. INTERRUPTS
..... DAL
:...}1~~"""nAL
t--.............··OAL < 16>
'PWRF ................--I
FPE
1 - - - - OAL
EVENT--'"
HALT ........~........ · •
DATNAOORESS
<: 21 >
t----~IOO
1----A.I03
DATA CONTR9L'J
1
1~ADDRESS
110
t - - - - 8S0
t---- SSt
BANK SELECT
t---- BOf'CT[
t----·AtE
BUS ERROR
DMACONTROL
CACHE CONTROL
t - - -.., 'STIrs
1---- ,SCll
INIT1AL~E
t----M5C
CLOCK INPUT
[
..
1 - - - - MAP
XTALI
XTALO·--.......
.
~,'~.;;;........:~
t - - -.... ClK2
t----ClK
TEST'2 -......,....,.....
,figu,re ;- QC]~lSignal F,u1{f!fpns ,
,~_ - ",,,
--:
"y, ,r '
- -'
',',
,>",C,
~
'-~:'_"~
-,
Data and Address Bus
Data Bct'~'tms(l)AL;;';'!he'dm and addi\::ss "bUS consists'of 22 time;'Multiplexed
datii'mdaddresslirie~.TIiebasit-buSdjmist!sofDAL 'and', is "'used ''for odtP\i£s!'oniy.; Dt:lririg thefiJist halfof.iea&
transaction, the DCJll provides either a physical address, the acknowledged in~ level Or a
general purpose code. The physical address can use all 22 bits of the bus. The acknowledged
interrupt level uses DAL< 03:00:> and the general purpose code uses DAL < 07:00 > . Durine the
second half of the transaction, the DCJll, transmits, or receives data, ori;·the6asicbtis
(DAL< 15:00> );The extended bmllirl~ (DAl~'21t!6»\tIe' driveri' witb~t mtoHn~tioil when
the BtffiCTL"Sigmll,is' assertea. 1'he'databeblg'ttafuimittedor ~ivedd~ on the type of bus
tranS{tctioq being pet£o~ md is 'd~ibed:under bUs opeHitiorlS.
.
, ," ,
1-2j3
-
A ddless Input/OutputLinell
Address input/output (AIO < 3:0 > )-The address input/output signals are latched at the start of
any bus transaction and are coded to indicate the type of transaction being performed. Table 2 lists
the bus transactions selected by the AIO lines.
1able 2 • DCJIIBus 1iansaction SeleCtion
AIOLine
Transaction
l
3
2
1
0
1
1
1
1
Non-I/O operation (NOP)2
1
1
1
0
General purpose read
1
1
0
1
Interrupt acknowledge (read vector)
1
1
0
0
Instruction stream request read
1
0
1
1
Read-m9(lliy-write,no bus lock
1
0
1
0
Read-modify-write,: ous lock
1
0
0
i
Data stream read
1
0
0
0
Instruction stream demand read
0
1
1
X
Reserved
0
1
0
X
General purpose word write
0
0
1
X
Bus byte write
0
0
0
X
Bus word write
lX=logic lorO
A NOP transaction is an internal operation that does not require a bus transfer.
2
A bus transaction uses the DAL bus
to access memory, 1/0 devi~s, or addressableregi.,sters. A
gerwral purpose transaction is used to access interface devices th~t are not directly addressable by
the DAL bus. Int¢rrupt acknowledge (lACK) transactions are in response to the DCJll granting an
interrupt request,
B..bk Select Lines
<:
Bank ~~t(BS 1:0> )-The bank select signals (BS 1 and.BSQ) are time7multiplexed. During the
first half ofa bustra~action, they are used toqefine the type of acldress that is .present on the
DAL < 21:00 > bus. During the second halfaf the ,read and write transa~tions, the~e lines define
the cache memory status. A cache memory bypass condition exists if the Bsf signal is asserted
high, and a force cache miss exists if the BSO signal is asserted high. Table 3 lists the address space
selected by the bank select signals.
Confidential andProprietaty
-
DQU
Table 3 • DCJll Bank Select Line Assignments
BS~
1
0
0
0
0
1
1
0
External jJO
1
1
Internal register
Memory
Table 4 lists the addresses assigned to the system registers and intert:talreg,isters of the DCJl1
microprocessor. Physical addres$~sIessthan 17760000 are inem,()ryaddresses:AddreSsesin the I/O '
page (17760000-17771777) that ~o not. ac~saDCJl1 rewsmr,are external I/O addresses.
Addresses in the I/O page that access intenlal registers; 'exCePt for'CCR, 'lire internal register
addresses. Addresses in the range of 177 77740 to 17777150areclassi£.ied as system registers,
RqJister
Address
Register
Classification
17777 776
17 777 772
17 777 766
17777 752
17 777 740-17 777 750
Processodtattis woiu(PSW)
Programintettupt'request (PIRQ)'" .
CPU error
System register space
Internal'
Internal
Internal
lnterool.
System
17 777 746
17777707-17 777 700
17 777 676-17 777 660
17 777 656-17 777 640
17777636-17777620
Cache control
CPU general registers
User data PARl Reg.O~ 7
UsednstntctionPAR, Reg.C-7
User dataPDR, Reg. 0: 7
System
lriternal
Internal
InterriaI
Internal
17 777 616-17 777 600
17777 576
17777 574
17 777572
17 777516
UserinstI'll~tionPDR,Reg., 0- ~
MM Status Register 2 (W4R2)
MM StatusRe~i~ter 1(M~R1)
MMStattls Register 0 (MMRO)
MM Status
Register 3 (MMR3)' '
..
Int!!rnal
Internal
Internal
.Internal
Internal
17 772 376--;-17 772 360
17772 356-17 772 340
17 772 336-17 772 320
17772316-17 772300
17772276-17772260
Kernel data PAR, Reg. 0-7
Kernel instruction PAR,Reg. 0-7
Kernel data PDR, Reg. 0- 7
Kernelinstruction PDR,Reg. 0-7
Supervisor data.PAR,,. Reg. 0-7
Internal
Internal
Internal
Internal
Internal
17772256-17 772 240
17 772236-17772220
Supervisor instrticiion PAR, Rei 0-7
Supervisor instruction PDR, Reg. 0-7
Internal
Internal
Hit/Miss register
"
'
,
"-"',"
\-,;'
All other addresses in I/O Page 17760000-17777777
0-,17 757 777 physical memory space memory
Confi~t;i.al and Proprietary
External I/O
1-255
·tX:Jll·
Data Control Lines
Buffer control (""'B:;";U""FC""'TL"""'"')- The BUFCTL lirieis asserted when J;he DAL < 15:00), bus is not being
driven by the DCJll when receiving data during read transactions and during the stretched portion
of any nonwrite transaction. The BUFCTL signal is negated when the DCJll is writing an address
ordatatotheDAL<15:00> bus.
Address latch enable (ALE)-The ALE line is asserted anhestart ofa transaction and is used to
latch the address, I/O bank, I/O map and AIO code irifonnation. During the second half of the
transaction, the signal is negated and can be used to latch the cache memory data.
Strobe (STRB)-The STRB is negated at the end of every tfarisaction and asserted by the end of the
second dock period of the next transaction. The STRB signal identifies the end of a transaction and
can be used for external bus control.
Stretch c:ontrol(SCTL)- Th~ SCTLline is asserted for the stret~hed portiQn of a bus transaction.
During ~rite transactions, the leading or trailing edges of theSCTL signal may be used to latch
data. During read transactions, the trailing edge of SCTL max be used to latch bus. The DMR line status is sampled bythe DCJllat the rising edge of TO andthe
request is acknowledged by the DCJll by asserting the MAi3·1ines. The.I5MR signal is not
acknowledged during write transactions. AssertingDMR ensures that the next transaction will be
stretched. All write transactions are stretched.
.
1-256
Confidential and Proprktary
Cache miss (MISS)-The MISS input is received from the system interface to indicate the status of
the current dai:!flememory lookup entry. The DCJll samples the status of the ~ISS line at the rising
edge of T3 during a read transaction. If the MISS signal is asserted to ihdicate the entry was not
located in cache memory, the current read transaction will be stretched.
Initialize (INIT)-The INIT input is driven by the system interface to initialize the DC] 11 by
forcing it to go through a powerup routine.
Interrupt Lines
..... .
Interrupt request (IRQ < 3:0> )-IRQ < 3:0> are fouttnaskable in~rrupt request lines that allow
the system interface to interrupt DCJll operations. ~ four j;tputs represent four interrupt levels
and are synchronized and latched by theDCJli:'
'
.
The interrupt is acknowledged only if the current PSW bits 07 :05 are set to a lower level than
requested by the system intetface.Th,ble ; lists theintet'l'Uptlevel a~ents.
InPut
LeVel
PSWbits
01
06
IRQ 3
7
1
1
IRQ 2
6
1
1
IRQ. 1
5
1
IRQ 0
.4
1
0"
1
0
Powerfail (PWRF)-The i.5WRF input is a nonmaskable interrupt from the system interface. The
DC]l1 traps to vector address 24 for the powerfail routine.
F1oa~"}P9int~on(FfE)-The FPE.input is a nontl\lll$kable: interrupt from. thesyste!tn
interfa,ce that cl;luses the DC] 11 to .trapj;() ~ectot:address 244Jor the servi6e rQutin~.
.
Bus even~ (£VENl~The. EVENT itlput. is ,8. hl.l!> fl1terrupt· ft:Om the system in,terfaeea,nd. the
DC]ll traps to vector address 100 for the ~ervit:e 1'9utine.
Halt (HALT)-The HALT input is the lowest nonmaskable interrupt from the system interface and
it fo(ces the DCJll into the console mode.
,'''..'
-
-
,
.' ',<
'-,
..-',;'.,' ,.';
I
'
.',
"
,"
Confidential and Proprletary
,
L'
,"
'.'.'
1-257
DCJU
Clock Lines
.
..
Crystal input (XTALl and XTALO)-TheXTALl anq XTALO inputs provide connections for an
external crystal as shownil'l Figure 4.
.
68pF
r--....---,.--- XTALI
CRYSTAL
c::::J
1M
1-_-'-_ _""--"'--_ XTALO
68pF
Figure 4 • DC]l1 Typical Crystal Connections
Clock (CLK)-The CLK signal is used for testing purposes and should not be used.
Clock 2 (CLK2)-The CLK2 signal is the same as the CLK and can be used by the system interface
as the system dock. The frequency of this signal is the same as the crystal frequency.
Misc::eIlaneous Lines
Test 1 (TESTl)-The TESTl input is asserted by the system interface and disables all the DCJ11
output signals. The input is pulled up internally.
Test 2 (TEST2)-The TEST2 input is asserted by the system interface to disable the CLK and CLK2
outputs and to allow an external dock to drive the DC] 11. The input is pulled up internally.
Power Supply
11
0
0
10
09
I I I
0
0
os
07
0
0
06
05
I I
0
00
•
fLOW
Figurel0' D(.:Jll Hit/Miss RegiSter Format
• Floating-point Register Set
The floating-point registers are used to store floating-point data and to control and report floatingpoint information.
'
Floating-point Accumulator
Six 64-bit accumulators (ACO through AC5) are used to store and manipulate 32-bit and 64-bit
floating. point data types.
Confidential and Proprietary
-
Floating-point Status Register
The floating-point status (FPS) register provides mode and interrupt control for the floating"point
unit andconditions,resulting from the execution of the previous instrucuon.'t'he FPS register
contains an, error flag and' ~our ,conditioncooes-'-+Cal"ty, I,overflow, zero, and nt!@ative,-that are
equivaientto the CPU condition codes. Thefloating..poi~tprooes50r(FPP) recognizesthe following
Hoating:-point exceptions.
• Detectibnoftheptesence of the undefinedvrffiilib1e intne~rY
• Floating overflow
o
FlOating underflow
o
Failure of floating to integer conversion
• Attempt topivJde py~rp
• Illegal floating opeode
the
For the first four, exceptions, ,the bits in,
FPSfegist~are available tp enable or disable
interrupts.An interrupt caused bjr the la~t tW6 exceptloPs,canlje dis~l),led,onlybysetting a bit that
disables ,the intenilpts of all, seven of the exrep~ons. tbe:er1'C!r'f1ag ahd~onditioilcodes are set by
the FPP as Pllft of t~e output oia. flw~ting"poi~~' instructiol1. The piode and interru~tcontrol bits
may be set byusUlg the LDFS ~tructiQh. ~i~ 11 showstlle format o£ the FPSregister, and the
functions of the registerbits are described in Table 10.
",
'
RESERVED
RESERVED
Figure 11 • Delli FlOiJfi1rg-point SfatUsRegister Format
Bit
DescriPtiotl
15
FER' (Floating error)-This bit is set during afioaiing-p<,intinttroction when a division
by zero occurs, an illegal opcode1sspecifi~;or l'lnyoHheremainin.g errors are detected
when the corresponding error interrupt is enabled.
hitis,set,l)y the Fl9ating-point
Processor (FPP) and deared(.mly anLDFPS instructiJ?n. Th~ bit" status is valid only if the
most'recent floating-point instruction produced a floating-point exception. This action is
independent of the FID bit status.
This
14
FID (Floating interrupt disable)-Whenset,al!flollting-point illterrupts ate disabled:
TheFID bit i~ primarily a maintenance feattl1'e andshooldnormally be clear to assure that
the storage of -Oby an FPP is always accompanied by an interrupt. This bit is assumed to
dearIor all desct1ptionsthat follow that involyingoverflow, underflow, and OCC1lrtence of
-0, and "<,'
iniegerconversi()n
errors.
:;i'i"
, _
f
'
~,'
Confidential and 'Proprietary
Bit
Desc:tiption
13:12
Not used-Reserved.
11
Preliminary
FIUV (Floating interrupt on undefined variahle)-An interrupt occurs when this bit is set
and a -Ois obtained from memory as an operand of an ADD, SUB, MUL, DIV, CMF, MOD,
NEG, ABS, TST, or any WAD instruction. The interrupt occurs before execution except
for a NEG, ABS, and TST instructions whenit occurs after execution. When FIUV is
reset, -0 can be loaded and used in any FPP operation. The interrupt is not activated by
the presence of -0 in any BC operand of an arithmetic instruction and trap on -0 does not
occur in mode O. The FPP will not store a result of -0 without a simultaneous interrupt.
10
FlU (Floating interrupt on underflow)-When set, a floating underflow will cause an
interrupt. The fractional part of the result of the operation causing the interrupt will be
correct. The biased exponent will be too large by 400 (octal) except for the special case of
0, which is correct. If the FTIJ bit is reset and if underflow occurs, no interrupt occurs arid
the result is set to exact O.
09
FIV (Floating interrupt on overflow)-When set, a floating overflow will cause an
interrupt; The fractional part of the result of the operation causing the overflow will be
correct. The biased exponent will be smaller by a value of 400 (octal). No interrupt will
occur if the FlV is reset and overflow occurs. The FPP returns to exact O. Special cases of
an overfloW condition are defined in the detailed descriptions of the MOD and LDEXP
instructions.
08
FIC (Floating interrupt on integer conversion)-When set and the conversion to an
integer instruction fails, an interrupt will occur. The destination is set to 0, and all other
registers are not affected. If this bit is reset, the result of the operation will be the same as
previously described but an interrupt will not occur. The conversion instruction fails if it
generates an integer that is longer than the short or long integer word specified by the FL
bit.
07
FD (Floating double precision mode)-This bit determines the precision that is used for
floating-point calculations. When set, double-precision is assumed; when reset, singleprecision is used.
06
FL (Floating long integer mode)-This bit is used in the conversion between integer and
floating-point format. When set, the integer format assumed is double-precision two's
complement (i:e., 32 bits). When reset, the integer format is assumed to be singleprecision two's complement (i.e., 16 bits).
0.5
FT (Floating chop mode)-When set, the result of any arithmetic operation is chopped
(or truncated). When cleared, the result is rounded.
04
Not used-reserved.
03
FN (Floating negative)-This bit set when the result of the last floating-point operation
wasO.
.
02
FZ (Floating zero)-This pit is set if the result of the last floating-point operation was O.
01
FZ (Floating overflow)-This bitisset if the last floating-pointing operation resulted in
an exponent.
00
FC (Floating ·carry)-This bit is set 1f the last operation resulted ih a carry of the most
significant bit. This can occur only in a floating ordouble-to-integer conversion.
1-266
Confidential and Proprietary
Floating-point EEeption Register
. .'. ..... . . . '.. .' .
One int~ptvec;tod~ ~sigQedto all floating-point ~ePti6n:s. The six ~ssible e11'Ors ~ coded
in the 4-bithting eXceptiofH!ode (FEe) register asf0llOws~
• 2 Floating-opcodeerror
• 4 Floating-divide by ·zero
• 6 Floating~ or doubJe..to-integer conversion error
• 8 Floating-overflow
• 10 Floating~UndeHlow
• 12 Floating-undefined variable
The address of the instruction producing the ~eption is stored in the Floating Exception Address
(FEA) register. The FEe and FEA registers ~ updated when one of the following occurs:
• Divide by zero
• megal opcode
If one of the five exceptions.~s with. the~r~nding ,interrupt :disabled, the FEe and FEA
are not updated. Inhibition of .it)terruPtll"by~he,F.JQatihg tnter1JlP(DisableJFID) bit does not
inhibit updating of the FEe and FEAif an ,~on()cC\lrs.Th~F}~:<:;~n4 FI!:t\ are not updated if
no exception occurs. Therefore, the storestatu!i (S':['ST)it)str~ction wi1:retur0cl.lrrent information
only if the most recent floating-point instruetiori'pr04uc~ an exception. 'No instructions are
provided for storage into the FEe and F£Aieg!Siers.
I
. Memory Management
The DCJll· implements the complete PDP-ll memory management and protection architecture
with its extensions for extended direct addressing. This architecture provides a fully supported
protection model for the design of, reliable mu!tiuser ()r multitasking systems. Address relocation
and protection logic is'm~l;ed~~the,Pi~~~e~~;so~t]J&(ormance penalty is not
incurred by using the memory management urrlt'(MMU).
The MMU provides.three sepiU11te, addressfPaces---kern.el,s~pel'Visor,
a~~~imodes_with
differentprivilegesandindependenisets6f16.hitmappi~gamt'p~lHegiSter$;This structure
protectstheoperatingS)i'sten'i frortl'lesspriViiegeiJ progritrtl$anlitni~zes s;tSteInuveri1ead from
switching. The executiono£ some of the instructions is--diffe¥erit~ndibg on the cUttent program
mode.
."--..
-
....
.
..
1-267
. Supervisor/UserMcxle'
Instruction
Kernel Mode
HALT
Executes as specified
Traps through 4
WAIT, RESET, SPL
Executes as specified
Execute as a NOP instruction
RI'I. RTT,
MPTS
Alter PSR priority level
bits 07:05 freely
Cannot alter PSR priority
leVel bits 07:05
Stack references
Checked for overflow
Not chec1wd f()roVerfl~
INSTRUCTION SPACE
PDR
DATASPAd
PDR
PAR
PAR
..
.'
"'.
....
:i
•
,
.
I
I
I
I
MMRO
MMR2
MMR3
. 'MMRI
T
INDEPENDENT SET FOR EACH MODE:
KERNEL SUPERVISOR. USER
Figure 12 • DC] 11 Memory Management Registers
Table 12 .. OCJl1Page Descriptor Register DeScriptions
Bits*
Description
15
Bypass c~che,..... This bit implements a conditional cache 'bypass mechanism. If the 1'DR
.accessed during a .reloc4l,tion operation has this bit set, the time-multiplexed signalBS 1 is
asserted during the subsequent I/O cycle.
.
.
14:08
PLF (Page length field)-This field specifies the block number that defines the page
boundary. The block number of the virtual address is compared against the page length
field to detect length errors. An error occurs when expanding upward if the block number
is greater than the page length field, and when expanding downward if the block number
is less than the page length field.
07
Not used.
06
W (Page written)-This bit indicates whether the page has been written into since it was
loaded in memory. When this bit is set, it indicates a modified page. This bit is
automatically cleared when the PAR or PDR of that page is written into.
1-268
Confidential and Proprletary
-
.DeJl!
ED (Expansion.clirection)-/fhisbit speci£iesdnwhicltdirection the page ~. If
03
:S:D'*(),tht'lpage expmds.upwll1'd &omhh:k number () to in~ bbclcs.:with .higher.
addresses;. IfED.l,thepage'ekpahds:~fJl)mblooknumbert27
blocks with lowerac:ldnesses.
02:01
w'iticlUd~
.ACF(ACc~sCo~trol·lieldb'irus·t~aconiamsthe.j&essCode£~r'thispmicib.ar.page.
The access code specifies the manner in which a page may be accessed and whether Q'
given' access should result in an arortof thecUirerit OPefation
.. The ~~ ~
.' ,: :>," " '1'. '_','" .,1
Access'Code
Pase'Atcess
Bit02 BaOl
o
0
Nonresident-aoort all accesses
o
1
REAd only--abOrt ~n ~tes
1
0
Notused;;';':"lIbortrulllCCesses .
1
1
Read/wrlte' acceSs.
J,
()()
Not used.
*All bits can be read or written except as indicated.
TheMMU
conta.iDsfour memorymanag~t~~J'~t~tate~ to C()ntrolar,tdl-~corctthe
status of the memory m~asement functions. '!lteregisters and a4dress ~~t:s'.!~:asf6lt~:
• Memory man~ementregister 0 (addre~ 17 777 572)
,
• Memory management register 1 (address 17777574)
• Memory management register 2 ~ad~s 17777576)
• MemoryllllUlagement register 3 (address 17777 516)
Page Address and Page Deserlptor Registers
Each operating'mode is aSsigned 16 page-address registers(PAR)~J6 p~escriptor registers
(PDR) to control the instruction and data space.. These 96registe.t:s ate addresSable to the external
DAL bus. A PAR contains a 16-bit displacement that is added to bits 12:06 df the virtual PC or to
the address received £rom the execution section tClcreate pariofthe:~Io~~,,~hysicat address. A
PDR contains information relative to page datuuch as expansion, length,andaecess controtThe
format of the information in the PDR is shown in Figure 13 and the function of the register bits is
described in Table 12.
15
I I
08
14
f ''--------v-f-----'
BYPASS
CACHE
PAGE LENGTH
FIELD
PAl
WRITTEN
EXPAL~
OIRECTld~ I
ACCESS
CONTROL FIELD
Figure 13 • DCJll Page Descriptor Register Format
Confidential and .Proprietary
...
OC}u
ThebCJI1 can optionally implement instruction and data space (lID Space) nllqcatipn to expand
the direct addressingrangeofa DC]l1 programor to facilitate efficient code sharing ina ~ultiuser
environment. lID space relocation can be separately enabled for each of theprclcessor modes.
When l/Dspace, relpcationis.enabled, the DC] 11 Classifies memory references as instruction stream
or data stream'referel1ces and independendyrelocates them.through the corresponding PAR and
PDR. The me~ory refereD(;e~aredassifiedbyt:he DC] 11 as I space references. All other references
are classified as D space references. If the I/D space relocation is disabled, ,all memory references
are relocated via the instruction space for that mode that includes the following information:
~,
Instf\lction fetches
• Immediate operands (mode 27)
• Absolute addresses (mode 37)
• Index words
• First references in modes 17,47, and 57
The classifications of memory references by addressing ~ocles for the first, second, and third
memory reference are listed in Table 13.
Table 13 • DCJll ID Space Relocation
Address MQde
~ster
0-6
7
o
1
D
2
D
3
DID
lID
4
D
I
5
DID
lID
6
lID
lID
7
'1/D/D
I/DID
1-270
I
Confidential and Proprietary
····DCJ·:n
Memory Management Register 0
The memorY management register 0 (MMRO) provides memory management register control and'
recotdsstatus. The format of the information in the MMRO is shown in Figure 14 and the function
of the i!lformation is described in Table ·14.
.... 1.",
-
ABORT PAGE
' - - - - LENGTH ERROR .
ABORT
'-----.,-.
NOIt-REI~IOENT
PAGE ADPRESS
SPAcellt)"
ENABLE RELOCATION
Figure 14 • DCJll Memory ManagemeniRegister 0 Format
Table 14· DCJll Memory Management Reamer 0 Description
Bits*
Description
15
Abort nonresident-Set by attempting toaccesu p~withan access control-field key
equal to 0 or 2. It is.also set by attempting to use1lletOOry relocation Wifh':an mt:g~
processPr.1llQde· (PSR 15:14"l'~),
14
Abort page length;error-$etby~tteirtpfitlg tOac'<:essa'locationina~ witha block
nwnber(~ ~s:bits12,:O(l)tha~is outsideth:~ @t.llQ~l>y~J.ge lqth
field of the pagedesaipto~ registet!~r~lltpage:
..
13
Abort read-onlyac{;essviolatiM--,Setby.l1ttemptitlg~·Write iQ..l1~d-onlypage. Readonly pages ~access key-sof 1. .'
12: 7
Not used.
06:05
Processor mooe-A read-only bit that indicates the processor mode kernel/supervisor/
user/illegal associated with the page causing the abort (kernel =00, supervisor =01,
user = 11, illegal = 10). If the illegal mode is specified, an.abort.i~generat~,~ bi,t;t,?is
set ..
04
Page spac~A read"onlybit trult indicates thead ) are
latched at the DCJlloutputat the beginning of a transaction and indicate the type of transaction
being performed. The Ala < 3:0 > codes for the type of transaction are identified in Table 2.
The bank select (BSI and BSO) signals are used with bus and general purpose, read or write
transactions. The~e signals provide .coded information to define the type of physical address that is
on the DAL < 21:00> lines. Thebimk select transactions are listed in Table 3.
Physical addresses that are less than 177 60000 (octal) are memory references. Addresses in the I/O
p8.ge (17769000-17777777) that do not access a DCJll register are external 1/0 references.
Ac!.d.ressesinthe I/Opage access internal registers, except for CCR, are internal register references.
System register references are addresses 17777740 through 17777750.
No Operation Transaction
During a no operation (NOP) transaction, the DCJll performs an internal operation and the bus is
used for external data as shown in, F~gure ,17. The assertion of ALE latches the Ala code that
identifies the transaction as non-1/0. The ttansiictionrequires four periods to complete provided
no DMA requests occur.
If DMR is asserted at the start of the cycle, the Nap transaction is stretched. A stretched
transaction is shown in Figure 18. The DMA request stretches the transaction to a minimum of
eight periods. The DMA request is received 011 DMR and is granted by MAP line. The BUFCTL an'd
scn signals are asserted during the stretched portion.' the transaction continues to stretch in twoperiod increments until the DCJl1 receives the CONT signal to end the transaction.
TO
T1
T2
T3
elK
Si'iiii
AIO
- t - - - I - - - - t '....
-t----f"'''"'''-
Figure 17· DC]l1 Nonstretched Non-I/O Cycle Timing Sequence
1-276
Confidential and Proprietary
Bus Read Transaction
A bus read transacti~ns~pwflirt,Ft-gure 19~~,e~ ~h~.J?#~lJs !Sl.~aW~orwatio.nITom memory, I/O,
and other addressable rl!gisiers. These transactiOns may be instruction
read, data stream
read, or the read portions of read-modify-write. The type of read tnmsaction being Performed is
identifie4 by theAlqcode .. The DCJll reads wprds a~dif a l:>yte iu;~quir¢, the complete word is
tead .!lIla the eXce~sbytt: i§ignor¢1.·'\
.'
'..
.
stl-eam
T~ DCJl1f ,alldMAp lilies sn6ti1abeigllored angTh~lius transactiol1;~oo1dnofbestarted.
~. read transaction ~jnitiated .bythe assertion of m.TIussigtl,lll.,,4t.'
'ilncode, the
pliysicaladdress on"l.)}\Lbus,theB~, eiata;·andfhe"'M1Ji'{~~~J': . .' f$ignal. The
DQ1l1atches the dataOfi tnerillillg,.
.. BS<1:0.> set to zeros (memory reference)
• No cache bypass
• No cache fOf~~.
~';U
Bus Write 1iansadion .' . . . . '. . . ". '. . ."
., .... .. ., . '. ... .
During a buswri~~Cti()n, '$bQ\vn in F'igQre 21, the PAL bu~ is Used t6 wri~infpr~tion into
memory, I/O, and other addressable registers. The information can be a byteotlaWord~,,~
bytheAIOcode.·Th.eOCJll reports memory man~ment or.addre~~rrors on;t'lwi~'~
the first part of the cycle. If the ABORT signal.isassetted,the informationon'DAL < 21:00 > .
BS < 1:0> , and MAP lines should be ignored.
The write transaction is initiated by the assertion~£theOOJt.~.Thiuignallat~ the AID~;
the physical addressonDAL <21:00> , BS< 1:0 >. andthe: ~(I/9 MIt' '~) signals: A~
write requires amimimum ofeight periodsandcanbutretdledlP.t . 'diikementsuntil the
ocJll receives the ct>NT signal to end the transaction. Thest~siPal.is~ during the
stretched portion andihewrite<1atills Vtilidon leiiding ~d':~~pg~1i9K~ ~. Si8~,
Sixteen bits of theDALbU8~ used forhrte write with tile ~cdataQAdlelow byte if the
address is evenand the correct data on the high byte iftheaadres$·if6da.'i'fhe data on the
remaining byte is not defined.'
. . . .' .... . "
.,
ClK
DAl
~,t::t]lt:~~~~=
BUFCTl +-~+-~~~~~~~~-4~~--~~~"~~~--~--~~
sen
~ Purpose Writar Transactions.," . . . '. . n ' " '
.
The genetal purpose write tmMactiOn is used.~ad~ ftOO-~DP.ll interface hardware through
t1re~ purp<>SeicodesonI?AL<07 :Qt}~: Either'bytcor~rite$ canbeit'litiated·1{S defil;l.e,4
by the l\IP~,zt&e ~~liotitI)eJ)A.t~us~g?9()~~Th~ .XJP'bit~.re~tthe gen~nd
purpose write' ,code.. ::a,ble 19 lists the write code assignments for the. general purpose tetld·
transaction;
ConfidentiRl atld P,roprietary
1-279
....
Write Code
Function"
014
Asserts bus reset signal
RdeilSes system from consOle ODT mode
040"
100
J
Acknowledges EVENT
214 "
140
Acknowledges powerfall ..
220
Microdiagnostic test 1 passed
224
Microdiagnostic test 2 passed
230
~crodiagnostic test 3 pas~ed
234
Places .s,ystem iritO '~onsole ODT'mode
m
The general pu~se ~rite trans~ction shown in F'ig~re 22 is itli"tiat~d..\,Y the~s~rtion~fthe
line; This' signal latches theAIO code and the genera!, ,purpose ctOdeon i~he DALbus. The
transa.ction reqUires aininimuth of eight periods and is stretched in two-period incrementS until the
DCl iirece1vesthe CON'fsig~llltQendthe ~nin~!lctiqn. The SC'rLsigrlaI i~' asserted during: the
stretched portion and the. write data is valid ,on leading and trailing edges. of this signal.
elK
DAL
ALE
icT!' '
, '~'
DV
Figure 22 • DCJll General Purpose Write Cycle Timing Sequence
1-280
-
General Purpose a.e.d Transaction
Th¥ gen~PurPose' Wtitetialisactio~ is USed to addreSs non·PDP~ll'interface'harti~thtouAll:
the ~;~~espl$Cedonbt1s. 0hly viOrds.re~by the~
~,.·~s.·~!i·i£'i1·.~.• is.reqUired, .the 'excess' byte is·~.·The~··on !be DAr: is
l~~XXX: ~:'XD: bit~;tepMent the ge~;~~code:Tab'M 2O'Ji$tS there8& cede
assigninentHorthe~purP6$ereadttaii~ot( , .,'
.
001
002
,"
Reads FPA data.
\
-
.'Rdads"th~ 'pOv.i~prribde,'haliby,tlPfi;FPA.,oPti9ti;PbK~al:-'a~b\;lOr:~~iis,:.
andcl~~'FPA'sF:PS.'
'0
."
:",
" ' ? ' .. " : " "
'I
.
.
The general pu~ re~ tmnsactioq, s~n in F,Jgure~3, is iffliated by th~assertion of the ALE
line.Th.!s ~g~ ·~tshe~..~e 4Iq¥~~ an~""the 's~n.e~J~Qi.~:~ tCadt! /on~th,~1;)t\L~, l'h~
~~aE~9.n,t'eCl~a' nurumum of elghtpefl0ds
theIDqll tereiyes~flilrCfjN'j"sigfuilt~rertathe'
latchestbedatawhile;SGtL~. .
t
·J~Q:~upcl..!!;lttements until
.;.' ............ ~~t~DV~nale'ncl
: ;:" ;': . , ' .
,
CLIC
DAL
Figure 23 • DCJll General Purpose Read Cycle Timing Sequence
,1·281
-
D MA Request and Grant 1 h m s a c t i o n " . · ,
.. ' . . " .
When theextetnaJ!system req¥~ststhe use of th~ D~I,..Ql,lS or want~. tp,stallthe Dqll, ,if ~er.tsthe
DM,R input. This disables; t~ DCJll frqmthe BAt bus. anq .~ses astJ:!':t<:hed. transaction:. The
DMRinputisacknowledged,aftetthe I/O map i!lf9l:mation is Qothe'¥4l? ()u~put;The R¥R inpq~
is the P;.1Arequestandthe Mf\P output .is theDMA grant. These. signals should be recog,l)ized
during NOP or read transactions. The write transactions stretch beyond four peri,ods l\11d the I)~
bus may contain write data. The DMA transfer stretches the transaction beyond eight periods by
two period increments, until the DC]U receives the CONT signal to end the transaction.
Interrupt Acknowledge
..,
The interrupt acknowledge trimsaction is used to acknowledgeari interruJ;>t requestrecehTed.
through the IRQ<3:0> inputs. The. vector add:ress specified can be an interrial predesignii:el
address cran cbcternal address received on the DAL bus. The deooded interrupt level acknowledged"
is sent on the DAL < 03:00 > lines at the beginning oithe thutsaction.The DAL< 21:16 > lines are
set to one and DAL bits < 15:04> are set to zero.
Thdnterruptac~owledge transactionshown inFigure 24, is il1itiatedby the assertion of the Au:
line that latches the AlO code and the acknowledged interrupt level.' The trans~tion requires eight
periods to read the vector address and can be stretched in two"period increments until the CONT
input is asserted'. 'The DV input is asserted to latch the interrupt vector address while the SCTL
signal is asserted.
·eLK
~ru~rw'r\-~'rufu~~~n
•
.
L
.....
lilA
BJJFCTL
""
....
.... .
~\\\\
III/I
..
..
I
I
~\\\\ SYSTEM ABORT STATUS
\\\~
I'
i\UU.
11111
\M
ALE
~.
~ .,'.'
"
.
SYSTEM INTERFAceil'l1rl
·.ORIVESOAL
INTERRUPT L E V E L l
'c.
I
I
.!
I
~\\\\
"
'" ; i.' (.
I
i ....'
• .CQf\I;rINUE
\\\\1
,
um
I
'
..
II/II
• . 11111
1111.
Figure.24 • Interrupt Acknowledge Cycle Timing Sequence
~\\\\.
Initialization
......;. .
<
i."
.......
..·..i·
thE: DCJllstarts the initialization processwhen\he~ystem interface pro~es 5 volts. {Vccland
assertsINIT for a minimum of 25 dock periods. The IN IT signal can be a.ssetted4>y the sys~
in~f~,bY us~a.~wakeupcircui~, ~~nitWizati9n process can~itDpJe~nted at ~y
timE: the systE:m interface asserts !NiT as showq~lf~ 25'~i
r---
e l K , ,"",- ..
(OFFSETI ~.,
'.'-./'
lNrlTL
sc
.',
~
-.--t=
.
~'._;:_;':'~;-f..~!
.··-·:,-,-:,-,-.".,-,*-~:~::~-----------+-"-+----.
~_
~I.LH+-:""""',"""",,~_~_,,",II
IND-
..,..
•
Figure 25· DC/II InitialiZiltion Timing Sequence
Th~ inltiauzarlon p~s uses the powerupiC>~ijOe,t&~;~ijrie:~~~i~~ ~t
returns the DCJll from the console ODT mode. A 002 G'P'~~bnl$~£OJ;m<:d dUrilig'ahY
routine, and thE: .system interface provides the configuration data through the DAL < 15:00 > . The
system interil!.Ce provides .tbi,s. data byJwd~,~ft:w~,PtJ~.r.~6 ~c:ny~ the fomut t
of the information in the ~~tioni.te;arutW."'e:f21lists the function of the
information.
UNUSED--------------------'
HALTO"'ION(---------------------------------~
POWERUPMODE--------------------------------------~
POK----------------------------------------------------~
Figure 26· DC/ll Powerup Configuration Register Format
Bits~.
15:09
BOOt address..';4Jrovides th~bOOe adcIteS;; asthePG· fortheusets prograrnwheiithe
powerup option #.3 is used. The PSW is .340. . .
08
FPA available-Indicates the system interface is using a floating-point accelerator.
07:(l4
Not used-Res~rved.
03
Haltoption-'-"'Selectsaction to be taken when a halt is executed in kernel mode.
02:01
Powerup mode-Selects the powerup mode for the syst~m mterfag! ..
00'
roK~lndicates when the system ac power supply is OK.
*All bits are read-only
mode
~l'
7 ':fable 22 lists th,!1 fo~ pc>weru~ ortions available to the user and selected by mode
.. .
.
bits Oland 01 oftheconflguration J;egis~r:. . . .
"
,
,-
"";'
I,
Powetup
Bit 02
Bit 01
Mode Description
o
o
0
PC at 24, PS at 26
1
Mlcro ODT,Ps=O
1
o
PC= 173000;PS;.. 340
1
1
User bootstrap, PS = 340
.
Confideritialand Proprietary
-
• Powerup option O~The proc~or reads Physkalm.eUlOry locations24aitif26 and loads the data
into the PC andPSR, respectively. The processor services. pending interrupts or starts program
execution beginning at the memory locat~p?#ttedtobythe PC.
• Powerup option l-The processor uncon. M ate cleared and the PSRlS set to
340. The processor then services pendi981~~ii:g!s~s the program execution beginning at
the memory location pointed to by theIPc~. fr;,: ',,<: , _~,' '" '(
".
,;"1
',;',
\'
(;,
"
Power OK-The power OK (POK) inpuJisl'roV~by th~Jrstem interface to indicate that the ac
supply is operating at the <:O~ voltag~: \'IUben,:~tf.iis'~, the voltage is correct; when bit 0 is
deal; the DCJU' ~~~'~ is off.
" ", "".,"1
Boot Address-The boot address reads the·~~t·bits (15:09) of the starting address from
the system interface. The remaining bits (08:~J.~,~iiS'~s. This ~the bootstrap address
to reside on any 2,048-word boundary. 'Fheboo"~sis5ele(:ted by powerup option 3.
FPA Available-The system interface s~thi~~11~ffl;¥ no.ting-point ac~tor is in the system
and is eleared when a floating-point accdeMtoPi$>~1Acl~.
Halt-The halt option is used by the s~il\:~~J\?ipdicate the interpretation of the halt
instruction in kernel mode. When set, tHis bit ~G~;~t;the processor will trap through vector
address 4. When cleared, it indicates thatt~wmbJ placed into console ODT mode.
'!iL
Initiali:r.ation Sequence
i"":'"
The initia.lization sequences are shownin~:toJlGWingflOw diagrams. The powerup routine is
described in Figure 27, sheets 1 throughf1i'Th!:'~routine is desc.rlbed in Figure 28. The
return from the our routine is described:,mE~.Z';~ 1 and 2. All ffiese routines perform a
variety of GP read and write transactions that are~ed in the Bus Operation section.
!:
'
1-285
GPWRITE
SYStEM IS NOT
IN CONSOLE OOT
MODE .
.GPWRITE
NIP.
GPWRITE
NIO
1'410
'NIO
BUS WRITE
NIO
Figure 27· DC]l1 Powerup Sequence Flow Diagram (sheet 1 of 4)
1-286
ConfiClenruu and Proprietai:y
BUS CYCLE
GP READ
NIQ
~T
8 OF THE CCR, WHICH IS
IMPLEMENTED BY
THE.
R /11$. l"HEFLUSH CACHE
8'I'r;(J.. ,AcCHiSYSTEMSI. CLEAR
THEOTH.~JN;CR BITS.
"tv
BUS WRITE
~~fARTHE MEMORY SYSTEM
...iR~J\.$EGm.E,R, WHICH MAY
',l1A'~'(.~T !!t!:lIMPLEMENTED
BYri'lltt~,*fI.'
",.10
NIO
.'
Figure 27· DCJ11 Powerup Sequence Flow Dis~ (sheet 2 of4)
-
n.....h_!_
:rRlUDlll&ry
8USCVCLE
DCd'1'\):'"
OPERATION
GPWRITE
. T:EST U'.t.sSii.D. CPU ERROR REGISTER
WRITTEN AND READ CORRECTLY.
BUS READ
DETERMINE IF EXTERNAL LOGIC THINKS
LOCATIQ:N (lIS IN NONEXISTEIliT M~ORY
UTSHOUl.[)NOT). IF IT DOES, EXTERNAL
LOGIC "tYPICALLY GENERATES AN ABORT.
BUS READ
,DIfTE;R~INEIF ~XTERNAL LOGIC THINKS
\..O,.CATIQN17777700 IS IN NONEXISTENT
MEMORY (IT SHOULD}. IF IT DOES,
'EXTERNAL LOGIC TYPICALLY GENERATES
.. AN ABO 1fT•.
'fl':s:t :U~ASSED. NXM ABORT NOT
GPWRITE
GENERATED BY REFERENCE TO
LOCAT10N:QBUT WAS GENERATED
BY .•MfERENCE lTO LOCATION
mntOD.
BUS READ
.
READ RECEIVER CONTROL
AND STATUS REGISTER lRCSR)
Figure 27· DC]l1 Powerup Sequence Flow Diagram (sheet 3 of 4)
Confidential. ana Proprietary
-
NOTES
BUS CYCLE
~'
OeTEaMINE IF EXTERNAL LOGIC
!HINt,>TEST"i.,PASSED. NXM ABORT NOT
GENERATED BY R£FERENCE TO RCSR.
GPWRITE
TRAP THROUGH
LOCATION,24
~::::
-'i'*.,,-
Figure 27· DCJll Powert4p'SequenceFlowBjagram (sheet 4)
.''', '
"
"~,~j
~
1·2,89
-
'Di..._H_! __ _
;;o.n:W:U.IlIlIUU-Y
DCJll
BClseVCLE
OPERATION
GPWRITE
2 BUS READS
2 BUS WRITES
EXECUTE
NEXT POWER
DOWN SERVICE
ROUTINE
INSTRUCTION
GP READ
S£TaIT7
OF CPU ERROR
REGISTER AND
TRAP THROUGH
LOC4
SETBIT7
OFCPUERAOR
REGISTER AND
TI'IAPTHROUGH
LOC4 .
ENTER
CONSOLE
ODT
Figure 28· DCJll Powerdown Sequence Flow Diagram
1·290
Confidentiil and Proprietary
-
BUS CYCLE
Gf>W'UTE
OCJ 11
OPERATION
Ng'rES
SvsrEM IS NOT
,IN CONSOLE OOT
M€)t)E
GPWRITE
1410
GPWRITE
.NIO
HIO
BUS WRITE
NIO
Figure 29· DC]l1 Console Start Sequence Flow Diagram·
1-291
-
BUS CYCLE
,QWI1
~ OI'ERATION
NOTES
READ POWER·UP CONFIGURATION
DATA THAT IS DRIVEN ON CAL
BY EXTERNAL LOGIC.
SET BIT 8 OF THE CCR, WHICH
,,"IS TYPICALLY IMPLEMENTED BY
THE USER AS THE FLUSH CACHE
BIT (IN CACHE SYSTEMS). CLEAR
THE OTHER CCR BITS.
BUS WRITE
CLEAR THE MEMORY SYSTEM
ERROR REGISTER, WHICH MAY OR
MAY NOT BE IMPLEMENTED BY
THE USER.
BUS WRITE
BUS WRITE
NIO
BEGIN EXECUTING CODE
Figure 29 • DC]l1 Console Start Sequence Flow Diagram (Continued)
. Instruction Timing
The execution time for an instruction depends on the type of instruction executed, the mode of
addressing used, and the type of memory being referenced. In general, the total execution time is
the sum of the base instruction fetch and execute time plus the operand(s) address calculation/fetch
time.
Tables 23 through 30 and the source and destination tables Sl, Dl through D6, and Fl through F4
are used to determine the execution time of an instruction in microcydes. The execution times
listed in the tables specify the number of microcycles required to fetch and execute the base
instruction. The read/write (R/W) columns specify the number of read and write microcydes
required. If the instruction involves a calculation or fetch operation of one or more operands, a
source or destination table is referenced in the table. The source and destination tables specify the
number of microcycles required to perform the calculation or fetch operation for the source or
destination. It also lists the number of read and write microcycles required. During the remaining
microcyc1es, no operations (NOP) are performed .
1~292
.Confidential andProprietaty
The table vatuesaij;;~.uculated.~l'lJm~ thatlill:'ead froqul,l,<:lll011'~tio~ ~uires aminithum of
of eight clOck periods,anda
four clock ~iods,a:write to memory operation requires
NOP'rrt~ti4¢tionr&t~res fo~ ci
"
,
shows
Determinetne execution time 000
i03400
2
l(}(JOOO
1/0
1/0
4
4
I/O
4
2/Q~
2/0
2/0 ..
2ie
2/0
2/0
4:
2
'1/0<"
1/0
4
4
2
1/0
4
..2/0
2{~F
2/0'
Signed Conditional Branches
BGE
SLT
BGT
BLE
Br if greater.or equal t.o 0
Br#.~~~g_
Brif greater than 0
Br if less .01: equaltdU"
';}i'f','" ':,:",1 -"\""_'i'"
unstgn
. cd ConditionalBranches
r/',
020000
,,{Qq2100··
00:3000'
003400
, ~.
..
~
2/0
·i./O
liP \,,''''::
.2
2
1/0
I/O
2/0
4
.if ,
.~,
"
--
,.
2/0
..
i;!'/
,
BHI
101000
2
1/0
4 ..
2/0'
BIDS
'101400
2
4
2/0'
499
2
2
3
I/O
1/0
1fG
Br if higher .
Br if lowerot same
SHISBr if highelior same
BlO
Brif lower' .
SOB
Sul?tract 1 a,hd bran~ if
not equal to.O
lQ3QQQ
103
07'7RNN
1/0
4
2/Q
4
5
'2/0
'-"
210
Table 26 ~ DCJll JumP and'~Une InstruetiQn Execution Tunes',.
Exeeution
Me--
DestiRat:iOQ
p;['f{;
"
\
,l@).;Je
:. ,J .. ;:;"
/!
MnetnOnk Instrudio11
Opeode'
JMP
Jump
0001 DO
05
}SR
Jump to subroutine
004RDD
D64
RTS
' Return from subroutine
00020R
5
3/0
Stack cleanup
0064NN
10
3/0
w
MARK
,.'
.:.\
'
.I'
14
Mnemonic Inst:i.uCtion
EMT'
TRAP
'Emu1~tor tr!lp
Opcode
'j""
Tmp
Execution
Time (Ilc) R/W
10400020
104377
104400~
20
20
20
4/2
4/0
Breakpoint tmp
lOT··.
Input/output tmp
000003
000004
RTi:
Return from intet~pt
000602
9
RT&' .•·
Return from interrupt
000006
9
r~\
'-,:
4/2
104777
BPI
",1- ..
)
Table:28 • DCJ1t Con~tion Code Operators Instruction Execntibn'TImes
Mnemonic Instruction
Opcode
Execution
Time (Ilc)
Cu:;
ClearC
000241
3
CLV
Clear V.
3
CLZ
ClearZ
OQ024,'?
000244
CLNi
Clear N.
,3
CCC
Clear all CC bits
SEC
SetC
. QOO250
000257
000261
SEV
Set V
000262
3
000264
000270
3
3
1/0
000277
3
1/0
"'.',
RfYJ
WI f
SEZ
SEN
SCC
'Setall CC i'its"
3
3
,I/O
1/0
3
1/0
.Cnnfidentiahmdl?roprietary
\.
-
....~
Execution
Taae(~)
R/W'pi
H:A:I:f ..... Halt
WAIT. ····Wait£Q1'inteJ:Npt
000001'
...
.
NOP,
~
t'
(No operation) . .
0066SS
. "\.,
~-,
.~
'-3
·1fl. . , 'DJ
MTPD ~. 1;0' previousdat'll spacel~S
2/(l
'.+
MFPT
Mo\te&ot11p~sor (RO
operations. One of the ltEAD opexations!s acconnted for in ~ exet;:ute,;£etch timing.
3. Read-only and read-modify-write destination mode 57 re£~s actually perform four READ
operations. One of the READ operations is accounted for in the execute, fetch timing.
4. Subtnlct 11J.C if the link register is the PC.
5. Add 1J.IC·if ~!~~,~~~,~~,;,.:
6. SUbtrap;.~Mcif~$Puri:emode'is fl9t~;,
' ......... " .
"", ., ............ .
7. Add 1 MC if the;q~~nt is even. Add2·~~~i~ overflow ~~~\4Memory
Cycles
Destination
Mode
Destination
Register
1
0-7
9
2
1
2
0-7
10
2
1
3
0-6
10
3
1
3
7
9
3
1
4
,0-7
10
2
1
5
.0-7
11
3
1
6
0-6
10
3
1
6
7
9
:3
1
7
0-7
12
4
1
Read
'Write
Tattle Fl • DCJll Floating Source Modes 1 through 7 Cycle ri,me
Microcode
Mode
Single Precision
1
2
2
3
3
4
5
6
7
Memory
Re8ister
:Memory
Cycles
Read
0-7
0-6
3
3
2
2
.·Write
0
0
0
7
1
1
0-6
4
7
3
0
0
4
3
3
2
3
3
6
4
0
5
5
4
4
0
0
0
0
0
0-7
0-7
0-7
0-7
4
5
0
0
0
Double Precision
1
2
2
3
3
4
5
6
7
0-6
7
0-7
0-7
0-7
7
0-7
0-7
0-6
01>
6
5
6
1
5
5
4
7
5
6
8
5
6
Con£jdential~d Proprietary
0
0
0
0
1:303
...
Microcode
Mode
1:·· •..
PIeIiminary
Table F2· oCJUFloating~tinatiott Modes 1. through 1 eyed, Time-,.'
.Memory
·Memory
. Register
Cycles
Read
Write
Single Precision
1
2
2
3
3
4
5
6
0-7
0-6
7
0-6
7
0-7
7
0-7
0-7
0-7
3
.3
1
0
0
0
4
3
4
5
4
0
6
2
5
5
0
1
1
1
1
2
2
1
2
2
2
2
2
2
Double Precision
1
2
2
3
3
4
5
6
7
1-304
0-7
0-6
7
0-6
7
O~7
0-7
0-7
0-7
(-1)1~
6
5
6
7
6
8
0
0
1
1
4
4
1
4
4
0
4'
1
4
1
2
4
Confidential and Proprietary
4
,",Mju
",":n....u:...:_.....
.
. .- ,
~1~
Table F)d)CJl1 FlOa~ Reaa~modify.write Modes htlUougli1 €yde IlDJe
Mkrooode
Mode
Memory
""Register
Memory
Cycles
'"-Read
~:Write
Single Precision
1
0-7
2
2
3
3
,0-6
4
0-7
0-7
0-7
0-7
5
6
7
-'1
0-6
"J
Double Precision
1
0-7
2
0-6
2
3
3
4
5
6
7
7
0-7
0-6
7
0-7
0-7
0-7
5
5
'. It.;
6
5
6
7
6
8
9
9
_211
10
9
10
11
10
12
2
'2
1
3
3
2
3
3
4
4
4
i
5
.5
2
2
1
2
2
2
2
2
'2
4
,4
1
4
4
(4
.5
5
,4
6
,4
Confidential and Proprietary
4
4
" 1..305
Microcode
Mode
f\>'OC)U'
Preliminary
Tabt~ F4,.DGJUiln.l:eger Sow:ee Modes.l:thtough
Memory
Register
Memory
Cycles
0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7
2
7Cyde Time
Read
Write
1
1
1
2
2
1
2
2
0
0
Integer
1
2
2
3
3
4
5
6
7
2
01 '
3
2
3
4
3
5
0
0
0
3
0
0
0
0
Long Integer
'0-7
0-6
4
4
2
0
2
2
2
7
015
1
3
3
0-6
5
A
5
6
5
7
3
3
0
0
0
0
0
0
0
0
1
4
7
0-7
6
0-7
0-7
7
0-7
5
1·306
2
3
3
4
Confidential and Proprietary
Preliminary
DC}1l.
Table F5 • DCJll Integer Destination Modes 1 through 7 Cycle Time
Microcode
Mode
Memory
Register
Memory
Cycles
0-7
0-6
4
Read
Write
2
2
2
5
4
0
0
0
1
1
Integer
1
2
2
3
3
4
5
6
7
7
4
1
0·6
7
0-7
0-7
0-7
5
0
2
6
5
1
1
2
0-7
7
2
2
0-'7
0-6
7
2
2
2
3
2
3
0
0
1
1
1
1
2
2
2
Long Integer
1
2
2
3
3
0-6
7
4
5
0-7
0-7
6
0-7
7
0-7
0
1
1
0
1
1
4
1
1
3
5
1
2
1
Confidential· and Proprietary
1
1-307
-
PmJiminary
. Instruction Se*.
Refer to Appendix B for a complete list of the DCJll ~Cl,'Oprocessor in.s~ction set .
. Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC319-AA
are described in the following paragraphs. The test conditions used for the electrical values listed
are as follows unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for the
general specifications for integrated circuits.
• Operating temperature (T,~): 70°C
• Power supply voltage (Vcc): 4.75 V
Mechanical Con£isuration
The physical dimensions of the DCJll 60-pin ceramic DIP are contained in Appendix E.
Absolute Maxnnum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device. These ratings are for stress conditions only and do not imply that the
device will function properly at these ratings or ratings above those indicated.
• Power supply voltage (Vcc): 7.0 V
• Input or output voltage applied (Vss): -0.3 V, {Ved: 0.3 V
• Active temperature: -55°C to 125°C
• Storage temperature: -65°C to 150°C
Recommended Operating Conditions
• Temperature range:
ooe to 70°C
• Voltage range: 5 V ±5%
• Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics
Table 31 contains the dc electrical parameters for the input and outputs of the DCJll for the
specified operating voltage and temperature ranges. Refer to Appendix C for test circuit
configurations referenced in the tables and used to perform the tests. Table J2 lists the applicable
dc tests required for the input and outputs of the DCJll.
Co1:1fidential and Proprietary
.
Symbol
."Preliminary
'OOJB
.
18bIe :n·· DCJU dtInput and Output Parameters
Pamneter
Test
Condition
Vm
High·level
MOSinput
Vu.
Low-level
...
Units
')fit
Chadt
V
Cl,C2
30%Vcc V
Cl,C2
V
Cl,C2
V
Cl~G2
pA
C3,C4
rnA
C5
rnA
Cl
Requirements
Min.
Max.
70% Vee
,~'
,;
MOSmput
VIHT
High-level
'ITLinput
VaT
Low-lel('el
2.2
TTL input
II
IlIL
Input-leakage
current
non-Test inputs
oV !:!VI !:!Vee
Input current
Test inputs
VIN=OV
,.,"
-10
10
Vcc =5.25 V
0.1
5.0
Vcc =5.2'V
Vour=Vcc·-.(My
lou
Outputcuttent
lox.
Output current
at }owlevel
VciIir=OAV
2.0
rnA
Cl,C2
10m
Output cuttent
at high TTt.
level
Highlevel .
VOUT=2.4V
-2.0
rnA
C2
VOUT= Vee -to V
-0.2
-(}.p.
rnA -
C6.
0.2
0.8
rnA
C6
at high'leYei
suStainer
current
';i
VOUT =1.0V
current
Vcc == 5.25 V
Ioz
Output leakage
current l
oV !:!VO !:!Vcc
L:csB
Static power
supply current 2
e.,
'~
Vcc =5.25V
Low level
sustainer
Ion
-:-2.0
CB'iC9
Vee =5.25 V
30.0
Vee =5.25 V
Input only
cllpacitanc;eJ
7.0
Con£identialand Ptoprtetaty
•
rnA
C7
-
;'IL..;.l'
,
:r:RIlnunaty
Symbol ·PaWneter
~t
Units
.
Condition
Input/output
capacitance'
15
pF
C.., .
Output
capacitance'
15
pF
C....
DCJll capacitance
plus external
capacitance
100
pF
Test
Circuit
lApplies only in the high-impedance condition.
2With TESTi, TES1'2, and all outputs open circuit. All other inputs equal to Vee.
'Sampled and guaranteed, but not tested. Does not apply to TESTi or fEST'i.
Table 32 • OCJll de Signal Test Summary
Type
Name
Applicable de Test
TIL input
IRQ <3:1>, HALT, PW'RF, EVENT, PARI1Y
DV, MISS, CONT, DMR, INIT and FPE
Vrm:, V'LT,II
TTL output
DAL< 21:16 > , AIO<3:0>, ALE, BUFCTL,
sC':rL, STRB, BS < 1:0 > , MAP, and PRDC
IoL' 101fT. loll
MOSinput
TESTl and TEST2
Vm, TIL, IILL
MOSoutput
CLKandCLK2
Ion, lot, 1m
TTLIjO
AB'Oi'IT*
V'tT' IoL, 10m,
~,IosH
TTLI/O
DAL<15;OO>
VrnT, VItT. IoL,
loHT'Ioz
Power
Vee
Ices8
*A'B'QRT must be driven with lll1 open-collector driver because the DCJll has a. pullup device that
supplies losn.
ae f:lectrical Chapteteristics
The timing references and signal parameters of the DCJll are shown in the following figures and
tables. Figure 3() shows the input and output voltage waveform characteristics. The test conditions
used to perform the ac measurements follow: Figure 33 shows the output load circuits referenced
on the tables and used to perform the output measurements.
Confidential and Proprietary
REFERENCE
OUTPUT
ClK (MaS)
OV (TTL)
MaS, TTL
(INPUT)
VOH
MOS, TTL
~
Vee -.04
VOL =0.4 V
td =
t;,
DEL~ y TlM~
=HOLD TIME
t. = SETUP TIME
Ien= ENABLE TIME
tdii> =DiSAB~~riME
.
Figure 30 • DCJll Input and Output Voltage Waveforms
Confidential and :proprietary
1-311
-
Preliminary
OUTPUT
UNDER _ - - -......- -...--~ TEST POINT
TEST
50PF
MA-9423
Load A-Three-state disable lest circuit
vee
TEST
POINT
RL
RL IS SELECTED TO PROVIDE
IOLOF2MAATO.4VOLTS
OUTPUT
UNDER 0 - - -....-4111-....
TEST
ALL DIODES ARE EITHER
IN916 OR IN3064
-=
CLOAD
= CMAX-J-11 PIN CAPACITANCE
~ 8-TTL Oulpullest circuit
OUTPUT
UNDER
TEST
O'O---I. . . ----O
CLOAD
TEST
POINT
~
CLOAD = CMAX - J-l1. PI N CAPACITANCE
Load C-MOS output test circuil
Figure 31 • DC]l1 Output Loading Circuits
Clock Signal Timing
Figure 32showsthe timing references for the dock pulses referenced in the following measurements. The reference edges are defined as' whole- and half-unit clock cycles. A whole unit is the
time between the rising edges of the clock cycles and a haIf unit dock pulse is defined as the time
betwe~n the riSIng and falling edge of a clock cycle. Figure 33 shows the timing references for the
clock outputs and Table 33 lists the.clock timing parameters.
~~
TO. 5
Tl.S
T2.5
T3.5
T4.5
T-2.5
T-1.5
Figure 32· DC]l1 Clock Cycle Reference Edges
1-312
Confidential and Proprietary
T-0.5
-
n..._1!_!.....
. rl.'CW.lWlary
Figure 33· DCJll Clock Output Timing Wave/orms
Load
Refelence Circuit!
Symbol
Patamder
tINJTW
INIT pulse width,
N/A
'''';:'';
. 225
tSHTU.H
Initialization interVal
tcvCLB
tam
CLK cycle time .
61'
CLK high width
28. '.
t CLn
CLK low width
28
til
eLK rise time
tl'
CLK fall time
......:.:.:
tpeyc
CLK2 cycle time
67
.ns
tPCIJ[J)2
CLK to CLK2high time
tPCLKH
CLK2 high width
28
ns
tl'CLKL
CLK2low width
28.
tl'll
CLK2 rise time '
fis
ns
,-
t pp
CLK2 fall time
............
os
.."....
os
7
os
'7
hs
,
"""l'-
7, .
7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
;
,
'
LoadC
LoadC
LoadC
LoadC
LoadB
LoadB
os
N/A
N/A
nS
NJA
LoadB
'ns
N/A
LoadB
lRefer to Figure 31 for output load circuits used for the timing measurements.
zDependent on output" loading)of
CLK and CLK2.
";'
'
LoadC
\
Confidential and Proprietary
LoadB
-
Preliminary
Signal Timing
.
The following figures show the timing references forthe bus read and write transactions, general
purpose (GP) read and write transactions, and the interrupt acknowledge bus cycles. Figure 34
shows the nonstretched bus read timing sequence and Table 34 lists the timing.parameters. Figure
35 shows the stretched bus read timing sequence and Figure 36 shows the bus write. timing
sequence. Table 35 lists the timing parameters for both the stretched bus read arid bus write
transactions. Figure 37 shows the GP read timing sequence and Figure 38 show the GP write timing
sequence. Thble 36 lists the timing parameters for both the GP read and GP write transactions.
Figure 39 shows the interrupt acknowledge timing sequence and Figure 40 shows the interrupt
timing sequence. The timing parameters for the interrupt sequences are listed in Table 37. Refer to
Table 38 for the tSD and t 5m parameter references in respect to the eLK signal timing shown in
Figure 39.
eLK
T2/T6
T3m
TO
T1
T2
T3
TO
AIO
BS
OAL
DV
Figure 34· DCJ11 Nonstretched Bus Read TimingSequence
1-314
Confidential and Proprietary
-
Preliminary
1ibIe '4.' DCJllNonsttetcbed Bus Read Taming ~
~ts
Symbol
.P.meter
Min.
tAJO»
AIO< 3:0 >deJay.
75
DALvaiid delay
65
DAL valid hold
tm!
Load
Max.
Units
RefeMnee
Cireui~l
>:£-1.5
LoadB
5
Load A
DAL o\iltputdisable
30
20
DMiihold2
tos
.. DAL< 15:00 > seru,;.e
,.
tsm
ns
1'3
30
'ns
T3
10
.nS
1'3
. ns
TO
PRDC valid delay
50
PRDCinactive delay
'(1'
$
tsD
ns
35
MISS hold
tPID
n5
..
:1'2,
t
,Strobe active 4elm'
Strobe uiactive dd.ay '.
35
ns
Table 38
35
ns
Table 38
4 _"'''-"
LoadB
LoadB
LoadB
LoadB
lRefer to Figure }1 for output load circuits used for the timing measurements.
'The serup and hold signaI~ts ensure the recognition of the lle1d: sample point.
ConfidenHaland. Proprietary
1-.315
-
T2fT8
13rr?
TO .
T1 .. " T2
.
AIOO....
.
',.
14'"
14
14
'''''00111
_P""
T5
T4
~~IpIOj
____
-
-
lSi>
,....!m!l
~ ....i-
X
;
7'C..
\1Af'
It-
-ooi
85<1:0>
j
'sOo4oj
'r1
'sID
'1
....
~
II+/'
"
TSO ....
I-- 'so
-oi
X
~
r~/1 r-,. r
'cALO'"
OAL
:::~
" _
....,
~~tOALH
=-
I---
J
ADDRESS
Oil
-!DH
~'cS
K:'
"
__
AB
f.l.:-tABD
'cNTS
'ABW
--
IsID .....
---- ,
~
~ rr--
-- "5,['" I---- 'AIli;- I- ./'' 9i"
__ L
,
'J
'so...
"
---.
----------
DMG
BYP/FORCE
~ ~'s0
"
_.',
IX
I+- 'so
,
.
TO
__
;I
'sID-
'"
" ,
DMRH
-to
X
"',
tHMS HMH
I--'t""'"IX!
'
T7
..... r-1~
__
3C.....
- J.o:.:t
'sO....
"- - ~'sOX
---
__
C;'_,,,_'"'\_
:::>/'
~tp)-.T
, 0
85
14
T4
.~~~f-!)::~~~ r-' "
eLK
'
.::...r'r
__r - "
tsD
V~
'"
'cNTH
,,'
'
r-~
SLOW
READ
L
I ~
JTA
~
X----
.x
~X
FAST
IIEAD
OllTA
*
to~
./
_
~ .......I",
OVW
I
••
'OVOH
tOVF
',,'
,'OVH
,!
>C
·1
--
I----tovs
Figure 35 • DC! 11 Stretched Bus Read Timing Sequence
T21T6
T3I17
TO
11'
T2
T3
14
T4
T4
T4
T4
elK
AID
PR1iC
OAl
m
STAB
BuFC'f'l
,/
sen.
BS
BYP/FOACE
WJ'
TABOd
I+-
DMG
AmmT
CONi'
Figure 36· DCJll Bus Write Timing Sequence
1-316
,CGnfidentialand Proprie.tary
T5
T6
17
TO
tMOO
75
'. AIO<3:0> delay
~...
30
tanu .
20
t-15
t~
LoadB
LoadB
DAL yalid hola
T 1.5.Tl Load B
5
T t5,T4 LoadA
20
tDMII1J.
tDYDl:(
TO
" ns
30
DAL< 15:00:> hold
'.MDV.L
'fr:
t Dm
DV deassertion
tDVS
DV deassertion
tDVW
DV pulse width
tm
i?Ri'5C valid dday
tl'fl)
PRDC inactive delay
0
ll$
.i',M/A
os
·T65
ns
T4
N/A
TO
T2
ns
50
ns
ns
LoadB
LoadB
''lable3S) LoadB
,,,<:.>
lable38.
LoadB
1Refer to Figure31 lor output load citcUitsused torthetiriiliig'm~rneIlts: ....•.......•....
2The setue,andholdsignal~~ ensurew ~piition~f. ~.tl,~.samplt:. pcint.
C9nfi~ial and Proprietary
T21T6
T3fT7
1:1
12
TI
TO
104
T4
TO
T7
~~~.:;.r
tAl 0 . ,...,.. ~~~~,.-,
'AIOD (1)'0 11
. .
.
__
~ ru..
>c;;;.
~ KJ
-trt:1 ....
i--'PIO
.'.
-
eLK
AID
"' ~
iW
'X
.:: =- X
-X
-
'DMRS.
---;;~
....
X
/'"
... 'so
X
OMG
tOMRH
'50-1 100-....
....
--- ~ID'"
----------
L.:" - ' -
c:::;
'SO ~
~
/1
'I+- 'sID
.-40
/'
.r'sD
'"
teNTS:;
/1
'sO..... FO-
,
!;-...
tOALO-
::::5
OAL
ov
~
1--
I
...
---
.... ~.'s0
r--'s0
-01
X
---
IX.
r'SO
1-'
I-
'--1-
'SO
SLOW
~tsiO
/"
~'cNTH
----.......r--/
.....-1~~'
--
X--
1-'s10
__
--X -~X ~IHA
." -:x:---'OIS-1-J:;;,.
~ 'o~ r:-~OVH
J 'o~
tOALH-tlci
GP.COOE
'.--
::::.:::.
I
GPOATA
_tOYS
tOVF
--
Figure 37· DC]l1 GP Read Timing Sequence
T21T6
TJIT]
TO
11
T2
T3
T4
T4
T4.
T4
104
T5
TS
ClK
AID
OAL
=-::;~~:j~~£Ijt>cC:::t:::~t=t===~G~PWRITE DATA
BS
DMG
ltCNTH
Figure 38· DC]l1 GP Write Timing Sequence
1~318
Confidential and Proprietary
T7
TO
OOj'u
Preliminary
18bIe }6 • CJU GP Read and Write Timing Parameters
.' Requirements
Symbol
tABS
A.BOR'f
delay
,;".
. "'1'·
ABPR.T drive
tAllY
AJ30lg wi4~
tAliD
tMoo
Min.
Pumleter
.
.
Max.
0
os
3'0
ns
40+
' AIO<3:0::>
del
" " . ..sr.
Reference.
Units
tCLJtll
ns
7'5 .
ns
T-15
Load
Circuitl
LoaclB
t.orrs
CONTsetup'
30
ns
t:",3;5
tcNm
CONThold
20
os
T;..,3.5-
tOALD
DAL \\'alid delay
ns
'I'-1,T1.5 LoadB
tOALH
bAL valiclhQld
.
5
:ru!.
XL ',T3
tOR
DAL<:~,:OO>
hOld
5
ns
T3
tOlS
DAL,output disable
tDllOlS
DMRsetup'
6'5
ns
35
30
LoadB
'Tq~T4
ns
Load A
TO
,~
j
'.' Tll. .
tDM\tH
ilMRhoid'
~Q,
.ns
tm;
PAL <15 :00 > setup
35
,'os
tOVOH
DAL < 15 :00> hold
,35
ns
tovns
DAL < 15:00> setup
35
ns
MDV-L
MDV.L
tDVP
DV fall time
15
ns
N/A
t Dm
DV deassertion
0
ns
T6.5
t DVS
DV cleassertion
0
ns
T4
tovw
DV pulseWklth '
35
ns
N/A
tHKS
MISSsettip
30
ns
T3
tWIN
MISS hold
10
ns
T3
ns
TO
LoadB
t po
,PRDCVlilld ck:lay
"
,50
:n
tPID
PRDC inactive delay
ns
T2
LoadB
tSD
Strobe active delay
os
Table 38
LoadB
t 5m
Strobe inactive delay
ns
Table 38
LoadB
0
35
lRefer to Figure 31 for output load circuits used for the timing measurements.
:the setup and hold signal requirements ensure the recognition of the next sample point.
Confidentialancl Proprietary
"
.•
""
.........
" 1'>;.4""
..........""'._!lI!J:!'I;_,()I!",",!I.___, .....
"_'1HI.......
1
.....""_
......"""...
...
UIJii..,'"......_
!&Ji_~
......._ _ _
• _ ....
___D_ _ _ _ _ _ _ _
• ____
-
1·319
,~
...
~.----
...•
-
T2fT6" T31T7
TIJ
T1
T4'
T3
T2
T4
T4
T4
,~'""'~~~~~ ~"'--
CLK
AID
i,,:
:::!:::...i- ~4:-.~
X
.......
's0-001
,
"
--
I-~HMH
1-'-
~X
MA1I' IX
iX
~
!,'
tpl~ !t,.'HMS
.'PO..,!
'so
OMG
~ :!!::. r'"""'OMR
'so .. ~ ;:X
'so.....
--- "
D<
.....
I-tso
X
J
I+-
'sID'"
~ ~'s0
'SID
V
'I
i-
r
'sD""",
.....
I-'sD
XI
I.......
f.i,...tABD
,.I
-
_,!CNTS~
~
'sID'"
'sD-40
---"
---==:;;
I
tolS
,,:::.0.
~
INTE.jRUPT
LEVEL
pv
I+-
....... ~
.'2.~~~
DAL
------------..
---------
"
::>
IINI
r:
l/1f-
J'SO
l
--
INTERRUPT .
VECTOR
~:.t:..1
t~
.. x
~
INT~TVECTOR
(FASTI
•
T
__
~"~
D~',~tOVDH
/rD~ ......I.
I.--,
'ovs
,
'O\lF
__
--
'O\lH------
HALT,PWRF,
FPE, EVENT
PARITY
Figure 40· DC]l1 Interrupt Timing Sequence
Confidential arilProprietary
-
~
DQtl
'lible 37· DCJU Interrupt mel Acknowledge Timing Parameters
i"
Symbol
~
t ABO
AlIDRT delay
"
Requirements
Max.
Min.
Units
0
nS
30
ns
tAlOD
'i\iIDR.T .drive
ABORT width
AlO < 3:0 > delay
teNts
CONTsetllIT,
I:cNm
<::5NThold
tOALD
DAL valid delay
tn.uu
tAIlS
tAB'&'
40+
tallH
;,':
T-2.,
11S'·,
7,
.ns
T-1S
30
os
' T-35
20
ns
T-35
as
T-l
LoadB
DAL valid bQld
T1.5,T3
LoadB
t DlS
DAL outPUt disa~5
T1.5T4
Lo~gA.
tOMas
i'5MR setupl
30
tDMJIB
DMRhokP
20
os
TO
tDVDH
DAL<15:00> hold
35
ns
MDV·L
tDVI>S
DAL< 15:00> setup
55
'ns
tDW
Dvfall time
toVH
DV deassertion
tOYS
DV deassertioo
tovw
DV pulse width
t llMS
MISS setup
tHMH
65
LoadB
TO
1
1Y>,
MbV-L
N/A
15
ns
T6.5
ns
T4
as·
N/A
30
os
T3
MISShoI.d
10
ns
T3
tpAllS
PARI1Y setup
20
ns
Figure 39
tpAltH
PARITY hold'
20
os
Figure 39
tm
PRDC valid delay
50
as
TO
LoadB
tPJD
'i?Ri5'C inactive delay
50
os
T2
LoadB
tso
Strobe active delay
0
35
os
Thble38
LoadB
tsm
Strobe inactive delay
0
35
os
Table 38
LoadB
0
O'
·35
Confidential and Proprietary
r""'....!$1l!lIISl
........
....
--,If', ...
!W!i....
~
~ Circuit!
1U"'"".1_
1·321
_.\1miie_".."""""'....,
__...""""'..".,._____w_.O'ii_""'""'________
.".".....W_.¢I._li......
~
'-_~~·
__·___·,__·_
.Requirements
Min.
Max.
Units
Reference Citcuit'
IRQ<3:0>, mr.r,
PWRF, FPE, EVENT
setup:
20
ns
Figure 41
. IRQ<3:0>, HAlT,
PWRF, FPE, EVENT
hold'
20
ns
Figure 41
Parameter
t svcs
Load
lRefer to Figure 31 for output load circuits used for the timing measurements.
2The setup and hold signal requirements ensure the recognition of the next sample point.
Table 38 • DCJll tsn and tsm Parameter References
Signal
tsn Reference Edge
tsm Reference Edge
ALE
TO.5
T3
STRB
T1.5
TO
BUFCTL
Tl.5, first T4
T3, T-l
SCTL
Second T4 or T5
T-2
BS
T-0.5,T1
MAP
T1.5
ABORT
T-0.5
1·322
Confidential and Proprietary
. Features
• Accderates by five to eight times the DCJll floating-point instruction perfotru.ahce.
• Improves by three to five times the system performance in floating-point applications.
• Supports the complete FPll floating-pointins~onset;.
• Supports single- and double-precision :qoating-point, !is ~U Q$ 16.- and 32-bit integers.
• High-speed, double-metal ZMOS ttchnhlogy.
• Single 5-Vdc power supply.
-Description
The FPJll, shown in Figure 1, isavery large ~caleintegratiqf! (VLSI) floating-point coprocessor for
the DCJU microprocessor thatirnplements the FPll floating-point instruction set on a single 40pin chip. The high performance of the FPJU'significantly ifupl'O\(es the performance of computation-intensive applications.
.
.
The FP]l1 interface provides the ai)illtytp overlap instruction ~tion in a DCJll system. This
ability allows the effective execution. time· of floating-point ins~ons to be measured as the time
required to execute the support microCOde" in the OCJl1\ and .any time waiting for a previous
floating-point instruction to complete.
I
I
I
I
I
I
I
I
I
I
I
I
I
.-J
Figure 1 • FP]11 FPA Block Diagram
Confidential and Prop:t:~
1·323
This section provides a description of the input and output signals and power and ground
connections of the FPJll package. The pin assignments are identified in Figure 2 and the"signals
are summarized in Table 1.
.Figure :2 • FPJll Pin Assignments
Table 1 • FPJll Pin and Signal Summary
P'm
Signal
Input/Output
Definition/Fm.ction
2-9
32-39
DAL < 15:00>
input/o';tput
Data lines-Transfer data; control, and status information between the DCll1 and the FPJ11.
13-16
AIO<3:0>
input
Address input/output-Transfers control signals to
indic(:lte the type of DCJll cycle being performed.
17,18
ADDR< 1:0>
input
Address-The two least significant bits of the
DCJlladdress used to determine the FPJl1 function
during GPreaa and CP write cycles.
19
INIT
input
Initialize-Initializes the FPJl1 and clears the floating-point status register.
1-324
COnfidential i and Proprietary
-
Input/Output
~tion/FunctioQ.
20
input
Stretch control-Used to enable the samplingo~the
abort condition and clear the initialization condi·
tion.
21
input
Abort-..:indicates a noncompletion of the ctlt1'ent
Cycl~ to the FPJU;
22
input
Acknowledge-Enables the transfer of the FPJll
output data onto DAL< 15:00 > .
Pin
23
Signal
DV
input
Data
valid--:J\n ~~~fi()u~strobe from the sys-
tem "!:nterla:te 'i,1~e«to .1~tct1
iQPut data dur4ig
stretchedrellds and general purpose write ~:
24
STRB
S~be-Atimipg~ign.al f~!ll·tllc::. DCJll used to
input and to indicate the end of
input
latch
~e.
25
theru:mc
input
PredecQde""":lndicates .that an instruction is being
.
decoded.
input
Address latch enable-A timing signal us~ to latch
the AlO<3;0> and A.DDR<1:0> inputs at lowto-high tnmsition and to read cache data at high-to19W .transition.
output
Floa~"point accelerator opetation-Asserted to
inforinthe syStem intedace.of Write cycles that use
>"~.
26
ALE
27
FPJll data.
28
FPASTL
30
FPARDY
31
FPAFPE
output
10
eLK
input
11
TEST
input
Test"","":Used during manufacturing test only.
1,29
Voo
input
Voltage-P9Wer supply voltage.
12,40
Vss
input
Ground-Gro\lnd"refere:nce:
output
Fia.tipg-point ..al:celenttor '~y-Indi~tes . the
FPJll output data iSl'ellJdyfot;t:mlls£.:r.
.
Floating·point accelerator floating-point exception-Assertedto inform the DCJll of a floatingwint ~Ptiop~tipn.
.
Confidential and Proprietary
-----
-.-----.--.--------~--.~--.----.--'.-"-.-----.--~.----
1-325
-
n.._I!.;;...~.L
_ ••
cR!llllllllilry
Data Lines
.
.
.. .
Data lines (DAL < 15,00 > )-These lines are bidirectional I/O lines used for data com'munication
witlnhe DeJll.
System Control
OOc::k (CLK)-Basic clock input to theFPJll.
Address input/output (A10 < 3:0 »-The AIO < 3:0> lines indicate to the FPJll the type of I/O
cycle as described in Table 2.
18ble 2 • FPJU Addtess inPUt/Output Code Assignments
AIOIiae
3
2
Cydetype
1
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
0
X
1
0
X
X
X
X
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
Non-I/O mictocycle (Non 10)
General purpose read (GP Read)
Not used
Instruction stream read request (I Read request)
Read-modify-Write (RMW)
Data stream read (D Read)
Instruction stream read demand (I Read demand)
Not used
General purpOse word write (GP Write)
Not used
External word write (Write)
X=either lor 0
Addtesslines(ADDR < 1:0> )-The ADDR < 1:0> lines contain the two least significant bits of
the Dqll address. They are used by the FPJll to decode the type ofgeneraI purpose (GP) read and
write cycles as described in Table 3.
18ble 3 • FPJU GP Read and Write Address Code Assignments
ADDRLine
1
0
Cycle Function
GP Read cycle
o
o
0
Read powerupoptions
1
Read data from the FPJll
1
1
0
1
Read powerup options and clear floating-point status register
Read floating-point exception code and clear floating-point exception signal
GP Write Cycle
1
1-326
1
Load data into the FPJll
Confidential and Proprietary
-
Address latch enable (ALE)-The low-to-high transition of this signal is used· to latch the
information from the: AID < 3:0> and ADDR < 1:0> lines. The high-ta-low tritriSition is: used to
the latch cache-hit input data to the FPJll. 'The polarity of this signal is inverted from,the ocJn
output.
Strobe (STRB)-The high-to-Iow transition of this signal indicl,l.t~s the ,~dof Ii DCJ1~cycle.
During FPJU read cycles, the STRB signal indicates that data was loaded by either the ALE or DV
signal. The low-to-high transition is used to sample the'PRl'5'e signal. ~,po~rity ofthissigpalis .
inverted from the nCJu output.
. '
Ptedecode(PBl)C)-This signal indicates to the FPJll that ~iDCJl1 i$''initiating ihstruction
decode. . , '
.
/.
Stl'etm control (SCTt)-this signal enables.the samplingof.tPeAUOftT llne by 0-e FPJ]J. during a
DCJll stretched I/O cycle. The low-to-high transition of scTtis'~so ~ed after the negation of the
!NIT signal to cleltttheil}itf~2;ationcOtiditi6ti~.. ....
. "~', . . .......i '.' . . '
Abott ' lines. The DV
signal is used by the FPJU to latch inJ;lUt data duringGP write or stretched FPJU read cycles.
Aclmowledge (ACK)-This signal is used to enable the operation of the FPIll output drivers. The
low to high transition of ACK indicates that output data ha.sheen.Jatched:rh~, FPA RDY signal is
then deasserted by the FPJU.
.
Initia1ize (INIT)-This signal initia1i~theFPJU andclear$the~Ps re~ster.·Thepolarity of this
signal is inverted from the DCJ11 input.
...
r~
Output~.
......
. ..
FPA ope!ate (FPA OP)-Thissigr)al is asserted by the FPJll to iQf9rmthe system interlace that data
for the nextwrite ,cycle will bepl'OVided by~he FPJll.The:fi5A ($p sigfilllisvalid by the assertion of
the ALE signal for DeJlI bus write cycles; It is also asse~J;ed during GP read cycles that read the
system powerttp optioIl.s,toindicate tPe presence of an FPJU.inthe system.
FPA ~ .(i'iPA S'tC)-This signal is asserted by the FPJll to stall the DCJR It should be OR gated
into the DCJlI DMRinput.The system interface must assert the CONT signal to the DCJll after
the negation of FPA STL to restart the DCJU.~
FPA floating-point exception (pPA FPE)-This signal is asserted by the FPJl1 to indicate that the
last completed floating-point instruction hadcausoo aqexc~.. The system interface must
assert the CaNT signal to the DCJ 11 without performing the bus write cycle. The FPA FPE signal is
cleared by a GP read operation of the floating-point exception code cycle. This cycle is described in
the architecture section.
FPA ready (FPA RDy)-:']thissigtl4ll is asserted by the fPAto~catetbat.9utputda,~isready. The
ACK signal must be asserted trom the systeDl;QlterfaceQurinfj Gp;read,.cydes be~ore thefPJ 11 will
assert the FPA RDY signat.l'be FPARDY signal may be ~ priQrto ACK fOr'wnte cycles. The
low-to-high transition of Ae'KnegatestheFPJ\ RDy~gnal. ItwULnot bereassel.'t~d until after
completion of the current write or GP read cycle.
Confidenti~ and Prop~
1-327
-
Miscellaneous
TeSt (TEST).....This signal is ~erved £or use by the manufacturer; . It is puHedup internally to the
inactive state.
Power (VDD)-The 5-Vdc power supply.
Ground (Vss)--Groundreference .
• ArclUtect't1re SUDlI11aI'Y
;The FPJll architectural configuration, shown in Figure 3, contains six. user-addressable 64-bit
floating-point accumulators (ACO-AC05), a floating-point status (FPS) register and a floating-point
exceptioQ code (FEC). register. The FPll architecture also includes .a floatiQg-point exception
address (FEA) registerthat is implemented in the DCJll.
The FPJll opera~es on single-precision (F) a~d doublc-precisiol1 (D) floatiQg-point, and 16- and 32bit integer data. Single-precision format uses the··32 most sigriificant bits of the.floating-point
acCuniulators and produces·· 8-decinial-digit precision. DoUble-precision format produ.ces 17decinial-digit precision.
.
r------------------~~
.. 64.BIT
.
I
I
ACCUMULATOR.
~
I
3 2·BIT
ACCUMULATOfl
I
I
I
I
I
I
~
.
,.'
FPP
EXCEPTION
CODE
,
REGISTER
ACO
I
AC1
r--
FPP
STATUS
REGISTER
I
AC2
II
AC3
I
AC4
I
AC5
FlOAT,ING POINT
ARITHMETIC
AND
COIolVERSION
UNIT
I
I
I
,
,
"
T~!.O~T.!..R~E'::~ _ _ _ _ _ _ _ _ _ ;.... ~ .
L~o~
I
I
I
I
I/O BUS
I
I
I
I
,I
I
I
I
CENTRAL
PROCESSOR
ARITHMETIC
AND
LOGICAL
UNIT
I
I
I
.J
~
H
'---
MEMORY
CPU
PROC!;&I)OR .. '\
STATUS
CPU
GENERAL
REGISTER
I
PROGRAM POINTER
;(0 LAST
INSTRUCTION
CAUSING EXCEPTION
Figure J·PPJ11 Architectural Configuration
Operational Units
The FPJl1 consists of two main functional units. The execution unit (EB) consists'of the fraction,
exponent, and sign processors; The bus interface unit (BIU} controls all interface functions between
the EU-andDCJll system. Both units contain independent control sequencers that intetacttoallow
possiblepefiormance impl'tivement through parallel operation of the I/O operations in the BIU and
instruction execution in the EU.
The BIU receives all instruction stream data and decodes instructions in parallel with the DC] 11.
Support microcode in the DCJll initiates all I/O cycles required by the FPJll. On completion of the
support microcode, the DC]l1 proceeds to the next instruction. Subsequent integer instructions
can proceed without FPJl1 intervention. For subsequent load class floating-point instructions, the
1-328
Confidential and Proprietary
-
'FfJl1
BID can support the overlap of operand data loading while the EU completesl!Xecuti,on of the
previous instruction; For subSC'1uent store class floating-point instructiOIi, the DQl n prbceeds to
the bus write cycle and then waits for the FPJll to provide write data or to signal an exception by
the FPA FPE input.
Floating-point Data .Forrna~.. '. . '.' . . . . .
.....
A Boating-point number may be defin~as having t.he form ( + or - )(2K) X £, where K is an integer
and £is a fraction. For a nonzeronumbet;K anMare determined by imposing. the condition lh ±
< f 1. The fractional part (f) of the number is then normalized. For the number 0, f is assigned the
value 0 and the value of K is indeterminate.
Thei pP]l1floating"point data fc:lJ:tiUlts are derived from: this represeomtiotifor floating-point
numbers. Two types offloating-pointd~taare J?rovided. Ins§Peprecision, or fl~tingmOde, the
data is 32 bits long. In double precision, or double mode, the data is &fbits long. Sign magnitude
notation is used.
.
Nonzero Floating-point Numbers
The fractional part (f) is assumed to be binary norttl;ilized, SO that i~s ~tsigt:Uficax:¢.bit must be 1.
Uris 1 is thehinerif of 0 and a
nonzero fractional part. An arithmetiC operation fotwhich the ~tingtruee:xponent exceeds 177
(octal) is regarded as producing a floating overflow; if the true exponent is less than -177 (octal),
the operation is regard~ ~spro#~a;fl()~ti~'Ul1({~~\v.A·h~~sed expOJ'1~t of 0 cahOccur from
arithmetic operations as a special caSe of oVerflow (true exponerit =200 octal).
Undefined Variable
The undefined variable is anyhit pattern with a sign bit 00 and a.biased exponent of O. The term
"undefined variable" is used to indicate that these bit patterns are not assigned a corresponding
floating-point arithmetic value. The undefined variable is also referred to as -0. The FPJll
ensures that the undefined variable will not be stored as the result of any floating-point arithmetic
instruction in a program that is run with the overflow and underflow interrupts disabled. This is
achieved by storing an exact 0 on overflow and underflow if the corresponding interrupt is
disabled.
ConfideJltw lind Proprietary
1-329
D.....I:....
•.. :.,;"
•. ......
;.,.
...' £~.u.uauu. ~
Floa'ting.point Data
The single- and double-precisionfloating~pQint data is stored in lMmQt'y a$ shown in Figure 4 •.
F FORMAT, FLOATlNG·POINT SINGLE PRECISION
'00
15
+2
__ __ ____~__~__~__~__AR~AC_~ON~<_15_:00~>
1~ ~ ~
15
14
__
__
MEMORY+o~I S~ ~
__
__
07
____
~__~~~____~__~__~__~
06
00
~ ~ E~X_P ~ ~ ~ ~~ ~ ~'_F_R~A_CT <2_2~:_16> ~ ~ '~'1
__
__
__
__
__
__
__
__
__
__
__
__
Single-precision (F)
D FORMAT, FLOATING POINT DOUBLE PRECISION
15
00
I
,.
15
00
+4~1:__~__~~__~__~__~__~__F_R~A_CT IO~N_<_3_1~:1~6_> ~ ~ ~ ~ ~~~~~
__
__
__
__
__
__
:1
15
+2
00
~1'__~__~~__~__~__~__~__F_R~A_CT IO~N_<_4_7_:3~2_> ~ ~ ~ ~ ~ ~ ~
__
15
MEMORY +0
~I_·_s.....L_~~_J....._~_E~X_P_..J.._.....I.._~
__
07
__
__
__
06
__
__
__
00
~_.l.-_oI-_F_R...JAI...C_T_.<5....L.4_:4_B>-J._~-,.---I
S ~ SIGN OF FRACTION
exp ~JiXPONeNT IN EXCESS 200 NOTATION, RESTRICTED TO 1 TO 377 OCTAL
FOR NONVANISHING NUMBERS.
fRACTION = 23 lilTS IN F FORMAT, 55 BITS IN D FOAMATPLUSONli. HIDDEN
BIT (NORMALIZATION). THE BINARY RADIX POINT IS TO THE LEFT.
Double-precision (D)
Figure 4· FPJll Floating-point Data Formats
1-330
__
Confidential and Proprietary
TheFPJll provides' £c?r CQ~iono£&ati~,po!ntt9~ger,£ormat ~d integer format to
&ating.point format. The
recognizes the 16-bit short integer {I), and the }2.bit long
integer (1) shown in FlgIlle 5. The numbers are in two's CQmplement format.
'
processor
I FORMAT. SHORT·INTEGER SINGLE PRECISION
15
00
14
NUMBER <15;00>
I
,
00
15
L FORMAT, LONG·INTEGER DOUBLE PRECISION
15
MEMORV
..ellS I
14 ",
" "
"" "
I'
S D SIGN OF !'4UMBEII
NUMBIIR ·15, 81,TStN,1 FQRM.~r. 31.,BI,.UN t.,F~f\~"T.
Floatina-point Status,~ ','
","
,", ""
, , , , '","'" ",'
,
The flOatirtg-poiritstatusri!g1ster(FPS}, show!;linFisure 6;Cd~threeinodecbfm.ol bits, five
itrtettUptcontrolwts,' an: etrorbit; 'andidi.tt Cd~C&dbs':'~PPSi'eji&ter'bitsr~deScribed in
Table 4:1his regiSter is cleated dlnirigthJ ~pSequcnceoh~!ftl!l:'ir~PreadcYtfe; ,
~LOATINGl
ERROI'l'
INTERRUPT
DISABLE
',-. -~
<
":~,""',',',';;"',"
'" - ",r , - -',MODES,;,
'l .
FLOATING "
COOblTION cbbES
Figure G,. FPJllFIoating·poinl Status, Regjstb Format,
Bit
Function
15
FER (Floating error)-This bit is set if one of the following conditions occurs. The setting
of this bit is independent of the state of the FID (bit 14), Cleared only by the LDFPS
instruction from the DCJ11.
1. a division'by zero
2. an illegal opcode
.
3. a floating overflow and FIV(bit 09) = 1
4. floating underflow occurs with FIU'=l'
5. an undefined variable is loaded and FIUV (bit 11) = 1
6. a floating-to-integer conversion error and FIC (bit 08) = 1
14
FID (Floating interrupt disable)~\Vhen set, aU floating-point interrupts are.disabled.
This occurs on .anattempt to divide by zero or by the detec:tionof illegal opcode.
13,12
RAZ (Read as zeros)
11:0.8
Interrupts-Initiates interrupt requests as follows:
B~t 11 Fruv (Floating in,tet'l'llpt ~~undefined ;variables)...,.-When set, an interrupt ocCurs if
FID (bit 0.9) is dear and a -0 is obtained from memory as anFIUV operand for an ADD,
SUB, MUL, DIV, CMF, MOD, NEG, ABS, TST, or any WAD 'instruction. The FPJ11
performs an interrupt before the executiorioriaIl instructions. Note: The FPJ 11
instruction set is interrupted affer the ~tion of NEG, ABS, and TST instructions.
Bit 10 FlU (Floating interrupt on underflow)-When set and the FID (bit 14) is dear, a
floating underflow will cause an interrupt. The fractional part of the result of the
operation causing the interrupt will be cdrre(iTfiebi~ed exponent will be too large by a
value of 40.0. (octal), except for the special case of 0. in which it is correct. If cleared and an
underflow occurs, no interrupt occurs and the FPJ11 returns exact O.
.
Bit 0.9 FlV(Fl~ting ill~pt 9n overflow)~Whenset and
~4) is.dc:~, a
floating pverflow will cau,ge an in,terru,pt;'irhe f~qtioq~part of the result of .the qB~tion
causit}g t~overflowwill be c;:orrect.Th~b~edexponent will he~mallel," by a value of 400
(octal).
PID '(bit
Bit 0.8 FIC (Floating intetrupt on integer conversion)-When set and FID is cleared, an
error in .the conversion to in,teger instruction will causrah interrupt. The FPJll . returns
exact zero. When cleared, theeca:ct zeiois return~ona conversion to integer error but
·nlYmterrupt willoceur. A fldating-to-integermodeconVersionerror occurs when a result
is nol: representable in the integer formatspecificd by the Ft (bit 0.6).
07:05
¥.od,es...;..Spec;:ifies the modes as follows:
Bit 07 FD (Floating double precision)-Determines the precision that is used for floatingpoint calculations. When set, the double-precision modeisnsed. When cleared, the
single-precision mode is used.
Bit 06 FL (Floating long integer)-When set, the long integer format is used (32 bits),
When cleared, the integer format is used (16 bits).
Bit 05 FT (Floating chop)-When set, the result of an arithmetic operation is chopped
(truncated). When cleared, the result is rounded.
1-332
Confidential and Proprietary
Bit
Fuficiiotl
Bit q3 FN(Floating ~egative)-Set if the result ohhelast fioating-p6iht Opentt16hWa$
negiitive;' ,
" , '"
,"::/":"
":/",',
BitOt}?z·~~. ~):) fSetgth,~:~~t,~.of~~~:~~rt~~~~t and ADDR < 1:0> lines fully identify the type of bus cycle to the FPJ 11.
The FPJl1 loads all instruction stream data into aprefetch huffer. TheDCJU ~sserts thePRDC ;line
when decoding instructions. PRDC is never asserted unless the prefetch buffer is valid. Floatingpoint instructions (opcode 15:12= 17) begin executign in the FPJll in patanetwith the DeJl!.
For instructions requiring data from memory, the DCJli executes the bus cycles necessary to fetch
the operands. The DCJli then continues to the next instruction after checking for a FPE from a
previous FP instruction. For register mode instruction, the DCJli continues to the next instruction
immediatdyafter,the FPE check.
. ..
The FPJl10utputs data only during store type instructions. OUtput data is supplied by the FPJll
during write cycles and GPread cycles as required. The FPJll may cancel an output cycle by
asserting theFPA FPE signal if the·previous floating-point instruction caused afloatibg-point·
exception.
The'FPJl1 asserts theFPASTL line when executing a floating-point instruction that does not
output data if the execution unit is still busy with a previous instruction. Thi! FPA STL signal is
asserted before the DCJll test for the FPA FPE signal.
The timing and system interface requirements for read, write, GP read, GPwrite, and the FPA stalls
described in fhefblloWing sections. Refer to timing diagl"ams FigUres 11 through 15.
are
An STFjD, STFPS, CFCC, or STEXP to memory instruction should be executed as the first floating.
POint storeinstmction after the powerup sequence to initialize the FPJ 11. This initialization is
performed automatically by all Digital software operating systems except MicroPowerfPascal.
Instruction or Data Reads
The FPJll inputs read data on all instruction read cycles and data read cycles that are fetching FPA
operands. Data is loaded at the high-to-low transition of the ALE signal for cache hits and again at
the high-to-Iow transition of the DV signal for main memory reads. The FPJll uses the high-to-Iow
transition of the STRB input to determine the end of the read cycle. It does not require cache hit/
miss information. The system interface read sequence is not altered by the presence of the FPJli in
the system. If the ABORT signal is asserted during a demand read cycle, the FPJll will abort the
present instruction.
1-338
Confidential and Proprietary
J7P,J"W.~ '.
..
, '. . . . ;
The FPJ~l assel1's~emoP.line. prior to the low~to-high transition of the ALEsigpal for all DeJli
buswritecycles~data£rom.theFPJ11.Thisin£ormsthesysteminter£a(;'e.~t.dle~tedata
is to be supplied by the FPJll. The system interface can assert the ACK ~ ~teIy ~POtl
recogni:/:ing a :FrJll write cycle. Th~~serti()n ofACK enab1es~eFPJll 0IlWUt,dri~.
The FPJ\RDY signalis'~ertedtoindi~t~ that~~~daatis ~~~, tp.~~~ , , ·L~~:OQ>.
The FPA ROY signal will not be asserted prior ~~§;W.1p--~.~~#on()~.
sign~~()ra
FPJll write. The system interface is required to wait for the FPA R1JY signal before continuing the
bus write cycle. There is no required precedence between FPA ROY and A.a< signals f~.bt.1$; ~~
cycles. DutingGPn:ratl~St;~ t:4esY~i9ter£asernpsF ~•. ~ ~,~!gnal bef~1:he
fPJll will~sert the ,FpA ROy 'si8naL,.~ fP,JllOP11'9 t "9ata;~~wi~,toIlY"~' ¢;~
assertion of.the, F:P4lUlY~ or~thitl t()J!,ti~'Qt~ ~s~OJ1 of~~.~~? wlUch~is
longe:c After recognizing the FPA RDY signal, the system interface lat~tPe JilPJ,l:+.
,-,.',
,",
.'''
,'.',.',-':'
',---;~
'-;,-"/:.:~'--':,-'
',L.~-'
_">{i-
.-'--
GP Read Ttansae.tioos
The general purpose (GP) read cycle is used by the DC]l1 to transfer data from a system interface
register or theFPJll"TheAD.QR <1;0> bits ~~es~f91:.~.~JU f9~tinguish~ ty~ ~f
Gp, read cycle b~g~ortned. ,The fo1.tt~ypeso£ GJ? 'read~s~llt~~~zed,\:>Y~h~fPJl1
are ~scrib~ in the £olklwiog paragraphs.,
GP~ad ~~.(~Q~"10)~~a,ngt~.GP~cyele.o£,;~ p(!W;et\li'op#ons~
the, FPJUwill ass~t :therl?PApjP;sigruil•. indiclltirlgt~pre~~Q~ i rAe FPJll.· ipthe system
configuration.
GP read floating-point conditioneode$ot' U;.;bil'cJata:(ADDlt.<:hO>:*t)......~ngthe;GPread
cycle of the floating.point oo.(lditioncodes (fCG)or 16·bit'data,d:lib ·s.ystemjntto,r£are~s both
the DV and ACK signals and waits for theFPJllto a$sertthe FPAlU;)Y'signah:ACK'1l1U$t be asserted
by the system interface before the FPJll will assert FPA RDY. Upon recognizing the FPA RDY
signal, the system interface deasserts DV, strobing the FPJll output data ;in~~:OCllL. SetJ.!Pand
hold requirements wi~h respect to t11e,FPARDYsi~~and Ai:Ksig~l,£orFP]n output data, are
identical~r GP reaaahdbuswnte.'eyc1es. After th~ ~ta is·la.tChed,'th¢systemint~~cC'..inay
d.eassert A<:K, causing FPJ11 outputdrlvers to beCotne' a higlf impe'&irice.' The FPnl\\jHlrth~n
deassert FPA RDY. If FPA FPE is asserted instead of FPA ROY, indicating a floating-point exceptioIl~
the FP] n will transfer a floating-point exception code. The system interface must still complete the
bus cycle but the DCJll will not use the data. A subsequent GP read transaction to the FEe register
will occur to read the register again and clear the exception condition.
GP read powerup options and clear FPS register (ADDR < 1:0> =2)-During the GP read cycle of
powerup options and to clear the FPS register, the FP] 11 will assert the 'PPA01? signal, indicating
the presence of the FPJll in the system configuration. The FP]ll will also dear the FPS register.
The G command in the DDT command language causes this cycle.
Confidential and: Proptic:~
GP J:e8d floating-point exception code (ADDR < 1:0>= 3) __ The Gp rea#.cyeti! =3)-The GP write cyCle withADDR < 1:0> =3 is used by the DC]11 to
write mode o integer source data to the FP]1L Setup· and hold requirements for the data with
respettto DV is identical to thafof a data read cycle.
DCJUStaD
TheFPJll asserts the FPA STL signal when execUting a·floating-point instruction that·dbes·not
ttansferdata if the EUis still busy with a previous instruction. This signal is asserted prior to the
DCJl1restfor It floating-pointexception.Thie FPA STLsignal is also asserted to minimiZe DMA
latency in aOCJl1 system.
The.FPA,STL signal should be OR gatedil:Jto theDC]l1DMArequest (i.5MR) input. Thesysterrt
inter£~e must assert the CONT input to the DC] 11 after the negation of FPA STL to restart program
.
execution in the DC]l1.
There are two cases when the FPJ11 will assert the FPA STL signal. The FP]l1 does not maintain a
copy of the virtual ad~ss of the executing instruction. Therefore, the DC]l1 maintains the
floating-point exception address register. The DCJll microinstrUction sequence determine~ the
extent to whkhfloating-pointlnstructions can be overlapped. The DCJl1 can be allowed to oVerlap
execution of a sUbsequent instruction only up to a point of the floating-point exception check. The
FPJ11 monitors OC]l1 microinstructions and always stalls the DC]l1 while allowing .amaximum
overlap.
During· FP]l1 load class instructions, this overlap allows the DCJllto complete data fetch
operations for a subsequent instruction before it: is stalled by the FPJ11. The effect of load class
overlap in floating-point intensive code is significant when much of the data is located in memory.
The FPJllalso asserts the FPA STL signal to limit the worst caseDMA latency of the DC] 11 'syStem:
The system interface cannot service DMA requests while wairlngfor FPJll data
a\vrite
cycle. The FP]l1 will assert this signal prior to the write cycle allowing the system interface to
serviceDMArequests if FP]11 output data will not be ready within worst case DMA latency time.
This condition can occur only if the execution.unit is executing a previous MOD or DIVD
instruction when the store instruction is decoded by the DCJll .
within
• System Configuration
Atyp,ical DC] 11 system configuration with theFP] 11 and cache memory is shown in Figure 91 In a
single bus system ~nfi~tion, the ADDR< 1:0> li,nes would be connected to DAt < 01:00 >
pins.
1·.340
Confidential and Proprietary
DCJll
SYSTEM 'Bus
<21;00>
. figure 9· FPJll Typical System Configuration
. Spedfications
The mechanical, electrical, andenvirontnental characteristics. and spe<:i£i~addfis£or the FPJll . are
described in the fonm.ring paragraph~. Th~ t~t conditioriS.t~tthe' electriCal va1Qes,~ as follows
unless specified otherwise.
• Temperature range (TJ:O°Cto 70°C
• Grmmd (Vss): 0 V
Mecbanical Con£igut'8tion
The physical the device .•
ExpOsure to the absolute maximum ratings for exten&H periods may adversely affect the
reliability of .thedevice.
.
• power supply voltage (VDD): 5 V ±5%
• Input voltage appliedWia): -1.0 V to 7.0 V
• Power dissipation: 2.~, W
• Operating temperature (TA ): ooe to 70 0 e
J'-
-
'j
H41
-
·'ft_.
"':0......
.1::•••....
·M J'
. :a J.o;;.LUU&IAAI.
Recommended Operating Conditions
• Power supply voltage (VDO): 5 V ± 5 % '
de: Elec:tric:al Characteristics
The de electrical parameters of the FPjll for the operating voltage and temperature ranges
specified are listed in Thble9.
Table 9 • FPJl1 de: Input and Output Paramele1'S
Symbol
Parameter
Vrn
High-level
input voltage
2.0
7.0
V
VIHC
eLK IUgh"level
2.4
7.0
V
-1.0
0.8
V
Test Conditions
Requireinents
Min.
Max.
Units
input voltage
VB..
Low-level
input voltage
VOH
High-level
output voltage
1oH=-1.0mA
VOL
Low-level
output vq1t:a&e
1oL=4.0 rnA
0.40
IlL
Input-low
leakage current
V.. =OV
±10
~H
Input-high
leakage current
V,.=5.0V
± 10
I-tA
Ion
Low three-state
leakage current
V,.=OV
TEST=OV
± 100
I-tA
loza
High three-state
leakage current
r
,
V.. =5.0V
TEST=OV
±100
~
I TsT
TEST short
circuit current
TEST =0 V
1.9
mA
P~~pply
VDu =5.25 V
500
rnA
fe= 1 MHz. All
unmeasured pins
returned to GND
5.0
pF
5.0
pF
100
2.5
0.3
V
current
CCLIt..
eLK capacitance
CIn ..
Input capacitance
C_*
Output capacitance
10
pF
I/O capacitance
15 .
pF
ClO*
1-342
COhfidential'and PrOprietary
ac Electrical,~
The clock iMut waV~£or~~ap.4 timing symbols are shown in Figure 10. Table i6 contains the timing
signal definitions end parameters for the clock input. ThetcuH width is measured at 2.0 volts.
Figure 10· FPJll Cltxk Input Timing,
,'(
_;r'
Figures 11 through 15 show the signal timing an&symbo~,f~,the£ollowjpg~Afloafing.point
accelerator operation are shown in Figure ll. Figure '12.~,the ~~~dtu'ing FPA siaIl
conditions. Figure 13 shows at:!!ad and cache hit tranSli!~iffiii:;'F~ljhWwsa:genl!ral purpose
write and stretched read transaction. Figure 15 shows a write operation with the IllY signal
asserted before the assertion of the stretch control (S'CTE) signal and a write and general purpose
read operation with the system interface waiting for the RDY signal from the FPJll.
The timing symbols and parameter definitions for the figures are listed in Table 10. The following
specifications,apply~
• Theac characteristics.are for a tOOpEcapa.citive lo.ad atthe.QUI:J;IUt§;
Symbol
Definition
.
Requirements (ns)
Min.
Acknowledge res{X>08e
Cache data hold
Max.
60
7
Clock fall time
15
Clock high width
T/2-)
Clock low width
T/2·3
Clock rise time
15
T
Clock cycle
Delay time FPA STL, FPAQ'i5
2T
Assert time FPA FPE, FPA RDY
50
DV£all time
20
Confidential and Proprietary
1·.343
...
. Preliminary
Symbol
Definition
tom
DV data hold time
25
tovpw
DV pulse width
50
tow
DV rise time
tlDPN
Input data strobeto STRBor PRDC
4T/5
tlDS
Input data setup time
40
tm
Input hold time
25
tIS
Input setup time
T/2
tLROLY
Last read delay to FPA STL
toOH
Output data hold time
t60v
.Output data valid from: FPA ROY
Output da~ valid from ACK
toE
ReC:(UitelfientS(rls)
. Ma;.
Mm.'
20
3T/2
o
eLK
DCJlf
FPAOP
I
joo-
STRB
AODF\~SS
REAl;)
MICRO INST
\
1
......_ _ _ _ _ _
RELOCATE ,
\
/
t OLV _ , ' - - - - - - - - - - - - - '
\. . . _---IIr------.\I..--____1
Figure n •WJll PPA Operation Timing
1·344
READ
Confidential and Proprietary
-
eLK
DCJI1
MICRO INST
STRB
LATCH
PAoe
END
STAll
CYCLE
OCJll
FPA Stall by Register Mode Inst1'Uction
elK
OCJII
MICRO INST
/
STRB
. . . '...... X
LASTAEAD
ADDRess RELOCATE
II'RDlY-I
END
STAB
CYCLE
ASSERTED
-- - - -
- -
-
STALL
DCJll
FPA Stall after Overlap of OperandFeteh
Figure 12 • FPJll FPA Stall Condition Timing
elK
AI0<3:0>
ADDR<1:0> _ _/,\..--I~_..J,\'_ _ _ _ _ _--:_ _ _ _
I\'_+-_...J'-______
DAl< 15:00>
~_
------4----------J,
ALE
STRB
LATCH
A10<3:0>
AOOR<1:0>
LATCH OAL
DATA
END
CYCLE
Figure 13 • FPIll Read and Cache Hit Transaction Timing
Confidential and.Proprietary
-------------_._-------
1·345
----------_ .. - _.._---
..
\ . . ptelimmary
ClK
AIO<3:0>
AODA<1:0>
DAl<15:00>
ALE
'OVR
DV
-- - - -- - y-----------------t----t-LATCH
LATCH
AIO<3:0>
AO'OA<1:0>
DATA
Figure 14· FPJll GP Write and Stretched Read Transaction Timing
.Confidential and Proprietary
END
CYCLE
-
FPJll
CCK
AIO<3:0>
ADDR
__A-~~~___________________________________________ _
+-____________________
OA.L<15:OO> _ _ _
~,\..
'""':"..t.,-------
___
OA_TA_ _
tODH
ALE
STAB
,"'---'" +-_____- J
'F'PAOP _ _ _
\
tACK
LATCH
Al0<3:O>
AOOA<1:0>
SAMPLE F"fiAOP
ENiABLE
OUTPUT
1'""','---_ _ __
VALID
DATA
DRIVERS
Writes with FPA ROY Asserted before !CT[
ClK
AIO<3:0>
AODR
x-
X
J..
OAl<15:00>
'OOH-
\
ACE
.",.
y:-
OATA
I
r---
/
\
.
J
10
\.
"1'-y~
tACK
tOD'\I
\
LATCH
A10<3:0>
SAMPtE~
.t
ENABLE
OUTPUT
-
----
t-L
r---
to
~R<1:0>
F
VAllO
DATA
DRIVERS
Writes and GP Read with System Interface Waiting for FPA RDY
Figure 15 • FPJ11 Write and GP Read TranSl:lCtion Timing
Confidential and Proprietary
1-347
.Featum
• Basic PDP-11 instruction set (except for the
MARK instruction)
• Full dynamic memory support:
-:-R~ dynamic addressing
-ID.abd 00 su-obes
• 16- or 8-bit data paths selected at initi~,;
,I;
tion
- Re£reJfh counter
-Aut0~tic ref~h cycles
• Interrupts on four priority levels with 15
internally generated vectors
• Progra~ble ~eregister featuring
-8- ot 1(,-bit ext~ data bus
• Option of having the interrupt device WQ~
vide the vector address
' '.
-Start ~d resw.rt~ss selection
-Statidor dynamknremory support
-Stal1ldfatd or long·microcycles
• DMA arbitration
"""Bus's~hcluonOUsor constant clock output
• Single5~'w
de ~~upply
"",
",'.
• Description
The DCTll microprocessor isaPDP-11 prOcessor containedinlt 40.pin,drial·inline package (DIP).
It is available in two versions; df1e'operate~ ~th a maximurl:tdhck freque'nty of 7.5 MHz (part no.
21-17311-00,01) and one operates;with a ~imum clock f~~ncy oflfJ:z..mz (part no. 21-17311-
#-
02). Full dynamic memory SUl'p/:lrt is p~ded for 4K/16f{ 64K.clji~,memory. This includes
., cycles;~ a refresh counter. The
timing strobes, dynamic ad~;!llultiple:!fin,g. automatic
interrupt is multilevel, using four priority levels •. Vectot
scan besuppJied by the DCTll (15
internal vector addresses are available) or by the interrupting devi,ce. DMA arbitration is included
in the DCTll. The maximum clock freque.t\l.'G1'is 10 MH:t:A~rs~ are TTL-compatible. Figure 1
is a block diagram of the DCT11 microprocessor.
Figure 1 • DCTll Microprocessor Black Diagram
Confidential and Proprietary;
,
-,',
"'-,
,.
j
1-349
The DCTll is a 40-pin microprocessor that functions with the input and output signals described
in the following paragraphs. The signal pin assignments are identified in Figure 2 and summaHzed
in Table 1.
ML1S .
1
Vee
OAl14
OAlla
:2
3
AI7
AI6
OAll2
DAlll
4
AI5 '
AI4
5
OAl1()
6
OAl09
7
AI3
AIZ
All
AIO
BGND
8
OAl08
DAlO7 . .
'to"
PI
0A106
OAL05
11
CAS
12
RiiS
OAL04
13
RlWlB
OAL03
OALOZ
OAlO1
14
RlWHB
15
AEAW
16
SELO
DAlOO
17
SELl
XTlO
XTLI
COUT
I:lI\L07
·BCiJi
PUP
20
·GND
Figure2 ··DCTll Pin Assignments
'l8ble 1 • DCTU Pin and Signal Summary .
Pin
Sign8J
1-7,9-17
DAL<15:00> input/output
8
BGND
Data/address lines-"-:Multiplexed, bidirectiooaldata
and address lines.
B Ground-A ground reference for all DCTll
. input
signals.
18
BCIlt,
output
Bus clear-An initialization signal from the DCTll
to reset th¢ system.
19
pup
input
Powerup-A signaltot:he DCTll that starts the
initialization process.
20
Gl-lD
input
Grouncl-A ground reference for all DCTll signals.
21
COUT
output
CIock'out-The clock output signal.
1-350
Confidential and· Proprietary
Pin
Signal
22
. XTLl
23
XTLO
Input/Output
Definition/Funetion
Crystal input I-External crystal conhecticinto the
internal oscillator "
Cr¥s~jflput.OiJ;:X~al crystal cQ~ection to the
.intern~ osc.illamr
24
SELl
output
Select .1-:-:-EncQd~with .·th~ .SEL.O line to indicate
the,transactipl'l: bclpg pert(;ll'tned.
25
SELO
output
Select 0"'- E'rl(::O&~Withthe5EL1-lin¢ toinrucate
.. the transact1'()lt~ingtp'erfu:i:ined.'·
26
READY
input
27
R/WHB
input
Reao/write·· ~ .•.~.strobe.:-Provickis·read and
write cQntrQho:the,$f$tet;n,.·
28
R/WLB
output
Read/write16w' '~fe stro&;--PtovicIes read and
write control to tnesystetn.
29
RAS
output
Row address strobe-A system ad~~~s~bt7.
30
m
butput
Column address'strobe~Anaddress arid chip Select
31
PI
output
Priority in-The write~ in.teJ:J:ul'i~ ~dDMA request
32-39
Al<7:0>.
A<17:10>
.input/output
A.ddr~s/~nterrup~(I1.:1e~~uttipkxed, .. bidirec-
strobe.~
strobe.
.,.
.' .
..
tional lines that transfer the dynamic memory
address and receive all system inter,l"lJPts.anp, DMA
·requests..
input
40
lttterrUPt
Data Address and
»hs
Data and address bus. (DAL<15:00> )-:Thedataand address.linesaretime-lfitdtiplexed,
bic1ireCtionallities used .to' ttlu1s{er ad~siftfol'mationand;~ata;'During ,reador"write
transaction, the systemaddres'sis tftins£efredfirsllfol1owed by thedlita. The <>peNtiori of the bus
lines depends on the selection o£the 8- or 1-6-bi'll'ffio'de.
.
Address and interrupt lines (AI < 7:0> )-The address and interrupt lines are bidii-ectiorud, timemultiplexed lines used to address dynamic random access memory (RAM) and to r<:,eeive interrupt
and direct memory access requests. At the beginning of the. bus ~le, .t!ie.'. addte$g on 'Jines
AI < 7:0> is the same as the address on the DALbus. The information on the AllineS depends on
the selection of dynamic or'static RAM rrtocle of operation ..
Confidential and Proprietary
1-3'51
• Bus Control
Row and~~mn 8ddteSS sttQbe(~ !'fIdCA~)-Whendynamic RAM supportisselected, the
row address strobe (RAS) and column~ddress strqqe (CAS) signals are used to latch the row and
column address of lines AI < 7:0> into dynamic· memory. If static mode is selected, the RAS
outputis used as a system address strobe. The CAS output can be used by the external logic in
either static or dynamic mode, as a chip select: enable signal.
During read operations, the data on the data and address lines DAL < 15: 00> is read by the DCTll
when the CAS signal is negated. During writeopeJ:ations, the negation of RAS or CAS signals can
be used to latcll data into the system ir¢erface.
Read/wite high byte andlow~byte (R{WHB)and RIWLB)-The read and write high byte and read
and write low byte outputs specify the direction of the information transfer on the DAL < 15:0 >
lines during the input or output portIon of a read or write bus cycle. The function ~nd name of the
~ and writeUnes depend on the selection of 8~ or 16-bit data bus mode.
Select 1 and 0 (SELl andSELO)-These lines ate encoded by the DCTll to indicate the type of
bus tnmsaction that being performed.
Ready (READY)-This line is as~rted by external logic to extend the current bus cycle.
is
System Control
Bus clear (BCLR.)-The bus clear line. is asserted by the proces~r. during the powerup sequence
and during the PDP-ll RESET instru~tion. The DAL< 15:8> and DAL< 1:0> lines receive the
mode register information during the assertion of the BCLR signal and the selected bits are loaded
.
into the DCTll· mode register.
Powerup (PUP)-The powerup signal resets the processor. When this signal is asserted, the DCTll
stops all operation and an initializaticn sequence 'is executed when the signal. is· negated.
Interrupt Control
Priority in (PI)-The priority in signal is used as the system priority enable strobe. When the PI
line is asserted, the AI <;: 7;0 > l~s receive interrupt inputs and the direct memory access request
(DMR). This signal may alse be used as a data strobe for read or write operations.
Clock Signals
Clock out (COUT)- The clock-out line provides a clcck signal that is centrolled by the selection .of
the mede register. This output can be .one-half of the DCTll oscillatcrfrequency .or a pulse asserted
once during e~ch internal microcycle.
Crystal,inputs (XTALO and XTALl)-The crystaI-inputJinesa~ external crystal connections J()
the internal clock generator. A crystal .or an external TTL-level clock generatcr may be used as an
input. When an external .oscillator is used, it coo,nectst.o the XTLl input and the XTLO input
connects~o ground.
~~ SuppJyC9npectioos
... .
Supply volta8~ (Vcci-Connects tc,tbe.5 Vdc pcwer supply.
Ground and B Ground (GND and BGND)~ Thesegrollnd pins coml{.~cttogether,and to the system
ground t.o provide ground references fer all lines .of the DCT 11.
1-352
Confidential and Proprietary
l)CTlt·
. Architecture ·Sumuwj ..
The DCTll microprocessor contains eight 16-bit general purpose regis~, a pr«:essor sta~
registet;.anda mode register. ,These registers, except for thelVooe register; are accessible to the
system prograinmerse!egisters are!iliown In figure' 3.1'he!ie registers operate as
accllmulators,. ind~~gisters,.Il~iru,;remf!nt~Il~, lm~~m~t.~rs,or as .stack
pointers for temporary storage of data.
Registers R6 and R7 are dedicated. R6 open1tes as the ~.po~~:{SP)am:ltstotesJhe location
(address) of the last entry in the hardware stack. Register R7 (\.pera~j.~.thepJ:OCeSsor program
counter (PC) and stores the addre~ oft~ n,eKt ~t:ruct;ionOl; ~ to Qc used;
RO
R1
R2
GE~~RAL.I'lEIlISTER$
e' 1'13
.,'
'.'
,'" .e
,
R4
R5
;
"
STACK POINTER
PROGRAM COUNTER
R6
I
ii'll
Figure) • DCT1l General PUt'/lose Registers
Proc:essor Status Register
The processor statusregisterCC)p.tain~. the Pro,<:es~o~status:word (PSW) consisting of condition
codes, trap bit, and currentli~soJ>p#()T1tY::\.'1'he Pr()CesSOt statu~"kgister f()rmat is shown in
Figure 4. Table 2 lists the functions of the register information,
Figure 4 • DCT11 Processor Status Register FOmt4t
Confidential and ProPrietarY
I-J53
Table 2· DCTll Processor Status Register Descrii'ti'on ..
Bit
"Description'
07-05
Priority level
bits used by the. software to determine
which interrupt
will be serviced,..
,
,
,
,
04
The trace bit used in debugging programs.• During a trap or interrupt operation, the
trace bit can be set or cleared when returning from the interrlJpt by using a Return
from Interrrupt (RTI) or Return from Trap .(RTT) instruction.
.
03-00
ThecoRdition codes Contain information about the result of the last CPU arithmetic or
logical instructions. The bits are as follows:
'''"
, , '
'
""
,,-
~
"'"
'
,
,'"
:
,,'
-
'
-
-
~"",
N"" 1 The result Was negative.
Z= l' The result was O.
V = 1 The operation resulted in an arithmetic overflow.'
C = 11 The operand resulted in a carry from the most significant bit or a 1 was shifted
from the most significant bit or least significant bit.
Mode Register
The 16-bit mode register (MR) is used to program mariy ofthe DCTll features. The mode register
bit format is shown in Figure 5. This register must be loaded by the external hardware during the
powerup sequence. It may be reloaded when a RESET instruction is executed; however, changing
processor modes after the powerup sequence has occurred is not recommended. Table 3 lists the
functions of the register information.
15
14
13
06
os
04
START/RESTART
Figure 5 • DeTIl Mode Register Format
. Table 3 • DCTll Mode Register De~tion
Bit
Description
15-13
12
Start or restart address.
User or tester mode.
.8cbitor.l6-bit data bus ..
4K/l6K or 64K chip memory.
Static or dynamic memory;
Delay or normal read or write strobes.
Nofused.
Standard or long microcycle.
Processor or constant mode clock.
11
10
09
08
07-02
01
00
1·354
Confidential and Proprietary
03
02
Table 4· OCTU Mode Register Starting Address Assigrnnents
start/Restart
Start
Restart
(bits 15:13)
Address
Address
7
172000
6
173000
{nOM
5
000000
010000
020000
040000.
100000·
140000
000004
010004
020004
040004
4
3
2
1
0
172004
1\10004
140004
"I't
• Bus . Operatif)ll
The
following;par~hs. describe. $e .~petatiQJilofi ~:i~iTll'~p~~$O~ 9~~dw:iugi the
of inst~~Q$~ Each. ~:or-l1 jnstl11ilc;tio~.,con$is~~t.~eorPlQre. transacliqns .. A.
execu~n
transae.tionis tbeactiviw on the bus ~~to ~~Qrm:t,~J9qc~,u,g P~H?Os.
..
• Read
• Write
• Refresb
• DMA (Direct memory access)
• IACK (Interrupt acknowledge)
• ASPI (Assert priority in)
• NOP (No operation)
Each transaction consists of one or two microcycles·anciamicrocyclecQPsists of three or four cycles
of the basic oscillator. One internal rnicroinstl'llction is executed fore~ch microcycle. The number
of microcycles required for a read a$Clwritetransaction depe~ds'onthe mode register selections.
The standard microcycle mode Uses. three clock cycleS for most transactions. The lopg microcyc1e
mode uses four microcycles for
transactions. One nUcroinstructkni is executed duripg each
microcyde. During a microinstruction. ad and AI<7:0> lines depending on
the type of operation.
Dynamic Operation;..;.;..The timing sequence for the '16-bit read and write operation with dynamic
memory is shown in Figure 6. The timing sequence for the 8-bit read or write operation with
dynamic memory is shown in Figure 7. When dynamic RAM operation is selected, the address
present on lines DAL<15:00> is time-multiplexed through the AI<7:0> outputs. The row.
address and then the column address is transferred at the beginning of a read or write transaction.
The'IO\V address is valid before the assertion of the RAS signahlrid thecolumnaddtess is valid
before the assertion of them signal.' The multiplexed address is the same aclcltessthl1t is
transferre<:t by the DAL otis before the ro\S sigtii1l ocCurs.I:.ilnes AI < 7:0 > are 9150 used to tm·nsfer
the internal refresh counter as a row address during the REFRESH transaction.
•
CPU ReAD TRANSACTION
1 - - " " 0 ADO.ESS
+
READ
,
INPUT~
COUT
A" H:lO>
PI
A/WU
• .WIlIi .
NOAMAl -
S[LO.S~L'I
-+__-+-___-+-___
____
DATA STRI;),8E
Read Sequence
Figure 6 Ii VCTn 16-bit DynamkRetraandWrite TimingSequence
Confidentialanq Proprietary
-
CP1,J WRITE TRANSACTION
•
r-WflITE
iI
ADDfU;SS~~RITE OurPUT---1
COUT
illiirr
AiWH8
NORMAL _ _ _..oJ
Am
RiWH6
OELAvEO
S£L{),SE LI
L..,...-J
~
AODRfSS STROBiiS'
OATA STROBES.
Write Sequenee
Figure 6· DCTll Dynamic ReaJana Write TimingSequence (Continued)
Confidential and Proprietary
1·357
'-------------------------.---,-,--------..
-"--~-~-
Dctu
~cpu RfAO TRANSAetl~'(lO B,~~~U READ TRANSACTION (HI BVTE~
J-REAOADDA£SS~EAD INPUT~t:'AO ADORE~EAO lNPUT4
COUT
SAL<15:08>
DAL<15:06>
-'"\.1-----------'""'",-----------.
_..I,.....________..,..._..J'-__________ . . . ,,-...J~_
A-:17:10>
PI
--I---+...J
1m
Rii"HB
DELAYED
wr
RIWt'II
SElO.SEU
DATA STRQ8E
DATA STROBE
Read Sequem:e
Figure 7· DCTll 8-bit Dynanic Read and Write Timing Sequence
1-358
Confidential and Propdetary
I--cPu WRfTf-T"MAN'SACTION
(La BYTE~ "AI1'f TftAlilaAcTlON
(Hl ElVTE..--t
I-wRITE AODMSS-+-w"-ITE OUTPUT-+--wRIT£ AOO~AITE OUTPUT-;
...w.".,......_.na~
PI
NORMAL
'11'1'
RiWiJi
'JELA'fEO
SEU),SELI
----~--+-~--~~~+---+-~--~~---
L..r--J '----.r--J
AobRES$ttRoe:ES
DATAST'AOBes ....
L..r--J L.........".--
ADOf'ES$STR08ES ~DA":"$tR08ES
·Wri.~ce
Figure 7· DeT1l 8·bit Dyna~ic.,Read.4.n4W.riteTin#ng~equence (Continued)
Static Operation-The timing sequence for the 16.bitreadand wr~te operation with static memory
is shown in Figure 8. The timing sequence for the 8·bitread or write operation with static memory
is shown in Figure 9. When static :mode is selected, lines AI < l~O> are used to receive interrupt
and DMA requests and the addressfor static memory is on th~ DAL bus. The information on the AI
lines should be valid when the PI signal is asserted. If theAI inputs change during the assertion of
the PI signal, the results are unpredictable.
.,
Confidential and Proprietary
-.
Preliminary
-----cpu READ TRANSACTION-
f.
J.--Ri-.D ADDRESS
READ tNPUr---i,
GOUT'
----I
=~
NORMAl. _
=-
DELAYEO -
Read Sequence
-CPUWAJTE TflANSACTIO'N-N----
rWR'ITE AOOAESS--+-:---WRITE OUTPUT---1
OOUT~______~~~____~
flIIIL< 15:00>
PI
"1.\:b!
R/WHB
NORMAL _ _ _--I
oW
A/WHB
DELAyeD
SElO,SEU
-------t-----;----itt---~
ADDRESS STROBE
DATA STROBES
Write Sequence
Figure 8· DCTll 16-bit Sf4tic Read and Write Timing Sequence
1·360
Confidential and Proprietary
-
DCtU.
n.._1!......~_~
C'n:uDlIIUU"y
~ AEADJ'~CTION (LO BYTEr-:+-cPJ..l.A~"O TRAN.SACTlON tHI ~J!El-*f
~eA,D AODReSS~EAO INPUT~EAO AODAEss+-READ INPuT---f
~<1~>~,,.-+~--------------~--'r~~--------------~--~r---
-+____________,..... . . .A.~I----~-'"'"'......,.........I...-
DAl<15:08> _ "..
PI
--+-_.....1
~8
NOIAWAL
·$e:LO.SEL,1'
Io_-----
---+-~------j._,ol-. . . ....,..,...------_,.....
ADORESS STfJ08E
th\TAST-ROSE ADpRESS STR08E
CO~T
A
WI'
nMU
NORMAL
WI'
RIiVlll
DELAYED
1115
RtWHe _
ADDRESS STROBE
'---v---J
DATASTROBIS
ADDRESS STROBE
DATASTROBtS
Write Sequence
Figure 9 • DeTn 8-bit Static Read and Write Timing Sequence
Confidential and Proprietary
1-361
-
. Preliminary
Address and Data, 16·bit Data Bus-During the 16-bit mode,· shown in Figures 6 and 8,
. DAL < 05:00 > contain the 16-bit address before the assertion of the RAS signal. During a read
cycle, the data must be valid during the assertion of the PI signal and remain valid until the
negation of the CAS signaL During a write cycle, the data is transferred before the assertion of the
PI signal and is valid after the negation of the PI signal.
.
Address and Data, 8-bit Data Bus-During the 8-bit mode, shown in Figure 10, two consecutive
memory locations are used for one PDP-l1 word. Two bus transactions are needed to fetch a PDP·ll
instruction or to read or write a 16-bit ()perand~ The DAL < 15:08> are renamed to SAL < 15 :08 >
(static address lines) and are used to transfer the upper byte of the current 16-bit address.
SAL < 15 :08> signal lines are latched and valid until the end of the transaction. The timing of data
relative to the CAS signal and to the PI signal lines is the same as for 16-bit mode read and write
transactions.
SAL<15:Q8>
fDAU
Of.t.<07:OO>
A
PI
ADIAIWHiI
NORMAL
lIll"lRIii'H!)
DELAYED
SEW
NOTE
ADDRESS STROBE
ADDRESS STROBe
NOTE:
1. SELQ ASSl:iJ:ITEO DURING INSTRUCTION
FETCH AND ONLY FOR THE LO BYTE
2. SEL 1 IS LOW DURING THIS TRANSACTION.
Figure 10 • DCTll 8-bit Read Transaction for 16-bitWoltl Timing Sequence
1·362
Confidential and Proprietary
For an 8-bit mode ibstruction fetch orfor operations on 16-bit data, the SAL< 15:0S>.Iines
coilt$nthe upper byte of the current 16--bit address and DAL < 07:00 > contain the lower byte of
the address. As in 16-bit mode, the address is valid before the assertion of theRASsignal Thelow
byte of the Word is then transferred in or out during"the data part of tbetra,nsllCtion. The
DAL< 07:00 > outputs then the low byte of the word address + 1, and the high byte of the16.bit
won:! is transferred. When dynamic RAM supPort is sdected;theaddl:dson DAL<15:00> is
mUltiplexed through theA! < 7:0>l,i.ne$fOr~ bus transactiol;l,
c
er ,~be
When a PDP·ll BYTE instrUctiOl1is~~t.c¥l.,o.pIy.Ol)f bus ~~on is needed to tJ:a11sf
source or destination operands. ,To fetch any instrUction a word operation is always used.
Read. and Write Control
The DCTU specifies the current bus transaction by the signals on the :R/W'ifB and R/WLB (read/
write) lines which may be modified,w themode;s~ions.
Selection of normal read/write modecausesthe~an(B.t{./'i'LB signals to be asserted before
the MS signal and is valid througha~tthe ~n.
Selecting delayed read/write mode ~"the ~B and.RJWjlB signals to be asserted with the
signal. Selecting the 8- or 16-bit data,bus.operation changes the function of
same timing as the
these lines.
'
,c·
as-
Read/Write and 16.bit Da.. Bus-OI.trlng lb-hi.tbllS modewd~~actions, Figures 6 and 8, the
R/WIiB and R./'Wi.'B signals indicate which byte of DAL< 15:00> will contain valid write data.
During a byte write transaction, all the DAL bus lines will contain information; however, the
unused byte will be undefined. The valid write data is indicated by the read/write signals that is
asserted low. When only one outputisassated;thedataisa byte·operand. When the R,IWiIB line
asserted, the valid data is on DAL<>15:0S >anewhen theRIWLBUne is asserted, the valid data
is on DAL<07:00>. Whenadtherread/write line is lo~, .. read operation occurs and
DAL<05:00> are in a high-impedance condition during this operations. Byte swapping is
performed within DCTll during read transactions.
Read{Write and 8·bit Da.. Bus-Selecting 8-bit data bus mode, shown in Figure 7 and 9, changes
the functions of the sigpalsonthe ~d/~~ ~.TbeRI\'mHine, becomes a read signal when
asserted low, and the R./'WLBsignal becomes a write signal when asserted low. The signal functions
are as follows:
16·Bit Da.. Bus
8·Bit Data Bus
Rj'WiiB (L =write operation)
R/WHB (L ... read operation)
RJWrn (L =' write operation)
R/\'VLB (L:= write operation)
Rj'WiiB (H ... read operation)
R/\'VLB (H = read operation)
The functions of RD and WT signals are also affected by selecting normal or delayed read/write
mode. Normal mode asserts the iID or WT signal before the leading edge of the RAS signal. These
signals are valid for the complete transaction. In the delayed mode, the iID and WT signals have the
same timing as the 00 signal.
Confidential and Proprietary
...
R.efresh..;...The dynamic memory of the system is automatically refreshed,every 2 milliseconds by a:
256.bit counter in the DCTlL A refresh tmnsaction,shown; inFigure.Jll,:addsa mi~le to the
transaction in progress·
• AJt~r every other PDP-llinstruction fetch in 16-bit mode .
• After every PDP-ll instruction fetch ill8-bit mode .
• When an additional refresh occurs for addressing modes 5;6, or 7.
-When a refresh miciocyde occuts twice during a tmpinsttUction.
c.i __
~
________
~
______
PI
SElI-
Figure 11 • DCT11&jresh Transaction Timing Sequence
1·364
Confidential and Proprietary
.Pse1iminary
ExteridingBus ~_tioM-Bus transactions can be extended for slow devices by assertiing the
READY ·sigruil dtiring· the tranSaetions.· Figure -12 shows the READY· signal· timing sequenCe.' In
~dditi6n tbreadstldwrite· transactions. the IAGK· and DMAtransactions mayalso·beextended.
i
_COUT
.ROC
MOD'
~w~i Tn~~~~
fIIon5
NOTE 6
...J...I..>...W..>..U...>..U..l..Uc>.l..=::::":"'.l.L.WW
~MlcRQ(;YCl,.eSt..I"'I--.;.+--IIII'CAOCYCLESltP2~
-illcrrmm[ ~:~:~~,: ~ ~ ]1
""-<1....> _--JxrtT7(((TTn{mrrrr{{((rrT1(((rrrT{(((rTTT{({TTn{({('7TT((((rTT1({{"""'{(((TTT1(((TTT{mrrn{((TTr({{-O-'U-'N
,.,.,,",_
-_',~,_,;; '.~_:';';;:,>
,.';__~~'_~_~~,:~!'t;%.,~,·,
I ----IXm{m{((mmm({~mmm(((((I~~~
_ _ _...A.
'~MiCROCVClE~IP~
"~".i§~
-
.~
_
MICROCYCLES\.IP2--1
XR«(<Ji.nes . TIle AI < 7;0 > lin:es.~ normally ~et. toa.high l~lby lnternalpullqp
circuits and must be dri~r11owtocaJJ&e.an interrupt, ijstatictp(';l(:lt is $elected; thes~ lines ru.:e u~
only as inputs and a~;kepthigh'Qqrlngthe addressp~rof theJ?U!icyde, Tht;se lines provide PF,
HALT, CPO-CP3 int~fUPts an,d theDM.R request.
Confidential and Proprietary
1·}65
-
~ ,Memory Request-When the. processot , it releases control Of thePMA busto~ device thatasSC;tlts the DMR line. The DMAbus
consist\! of the DAL < 15;00> ) AI < 7:0> and ~write lines. The DCTlI maintains control of all
other signals.
Interrupt Request-When one or more of the Ci5O-cp> lines (AI < 4:1> ) are asserted during the
assertion of the PI line, the processor detects an interrupt request. The CPO-CP3 inputs are
encoged, allowing 15 interrupts divided among four maskahle priority levels as described. The
processor decodes these inputs and starts an interrupt acknowledge (lACK) bus transaction when
the current instruction is completed. Each line is dedicated to a specific interrupt or DMA request
as shown in Table 5.
'lllbIe.5. DeTlI Interrupt Request Line Assignments
CPJ
en
m
CPO
Priority
Vector
(All)
(AIl)
(All)
(AI4)
Level
Address
X
X
L
L
L
L
L
L
L
L
H
X
'X
X
X
L
L
X
X
L
H
H
L
HAIT*
PF*
7
7
7
7
L
L
H
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
H
H
L
H
H
L
L
H
H
H
H
L
L
H
L
H
H
6
6
6
6
5
5
5
4
4
24
140
144
150
154
100
104
110
114
124
130
134
60
64
No action
*'ilJJ1 and·pp signals are nonmaskable interrupts. The HALT interrupt loads the PC with the
restart address and the PSW with the value 340.
Vector Assignments-When the VEC line (AI5) is asserted during a priority interrupt and one or
more of the CPO·CP3lines are asserted, the processor will accept an external vector value during an
IACK transaction. If the VEe line is not asserted anhe sametimethat an interrupt is requested,the
processor will provide a vectofaddtess from an internal table. The-vector value will be oneol the 15
assigned to eachCPinterrupt cOde. Four interruptvectbrsareassigned tbeach priority level 7, 6,
5 and three interrupt vectors are assigned to level 4 as indicated in Table 5.
and
Powerfail-A powerfail hardware interrupt that vectors through loCation 24 occurs if .the PF signal
is asserted on line AI6 when the PI signal is asserted. This interrupt is nonmaskable and is
processed regardless of the current interrupt priority level.
1.366
Confidential and Pwprietaty
-
.OCTU
Halt"";'1'he l1i\i'!i'interrupt request, assigned to line AI7"is a nonmaskable interrupt that has a
higher.priority.than PQWerfail. After saving the current program counter and processor status
values, the processor will set the priority to 340 and jump to t~restart address. The restart address
is~.during powerup when the mode register is loaded. The HALT input is pseudo-edge
tri88,eredand must be read asa n~glltionbeforeanother ~tion,.is accepted by the processor. .
Direct Memory Accesa..,....The DGIllprovides a directmem9l}'QCcess (DMA) in,te#i\Ce that can be
connectt!d to singJ,e-Chapnelormu1tipl~-channd DM,A~rcl1jts.Requests forDMAare th!l)ugh the
direct memQry request PMR inl'mtop, ll11e J\IQ. A c.Uiect m,.em9ry grant (DMG) will.occur after
internal arbitration. The processor completes the cUrrent bus transaction and relinquishes bus
mastership. Figure 13 shows the timing sequence of the DMA transaction.
Mt.<15:00>
Jr________
~T~H.~
••~ST~M~.O~_____________
OMG
(SElO)
0,,"
(SELIl
·Pv'Ls£"MOD!: ClOCK (MODE REGfSTER,*'1
figUre·13 • DCTll DMATiming Setjuence
The new bus master gains control of the bus when the SELO and SELl signals are asserted. When a
DMG (SELO and SELl are both high) is received, the bus master must take control of the DMA bus.
The DMA bus consists of the R/WHB and RfWiJ3 lines (Ri5 and WT in 8-bit mode), the
AI < 7:0> , and the DAL < 15:00 > lines. The AI < 7:0> and read/write lines are asserted through
low-current pullup circuits and DAL < 15:00 > are in a high-impedance condition during the DMA
transfer. The processor maintains control over RAS, CAS, PI, COUI, SELO, and SELl lines to
provides the new bus master with convenient timing signals for interfacing to dynamic memories.
Confidential and Proprietary
1·367
The bus master must control the read 'and write functions, provide addresses,ancl be capable of
drivingor receivirigdata. lndynamk memory systems, an address;mustbe multiplexed on tines
AI < 7:0 > so that row and column addresses are provided at the correct times.
When it data input or o~tput transfer occurs, the direction of the transfer is controlled by the state
of the read and write lines. TheDCTll continues to issue grants by asserting the DMG signal until
the DMR signal is not asserted. The DCTll then continues its usual operation.
Becausethe DCTll . controls refresh operations based on the number of transactions. needed to
execute the PDP-llinstruction set, consecutive DMA operations are not recommended:
)
In~pt~tion
The DCTll uses a vectored, multilevel interrupt structure. Four priority levels are masked by the
upper three bits of the processor status register. The two types of interrupts are maskable and
nonmaskable.
Maskable interrupts are requested by an external device on the coded priority inputs lines cpoCP3. These requests will interrupt the processor operation according to the priority level of
interrupt codes 0 through 15. The nonmaskable interrupts are HALf and PF which are not masked
by the processor priority.
Interrupts are received on the CPO-CP3 lines when the PI signal is asserted. The processor
completes all bus transactions in the currentPDP-ll instruction before servicing the interrupt.
Interrupts are latched in the processor during read transactions. The DMR inputs are latched
during read or write transactions. The PI line must be asserted to latch either DMR or interrupts.
Each CP code is connected with a vector address in the DCT1t. A PDP-ll vector consists of two
consecutive memory locations. Vector locations are in low memory (0-376) and must be assigned by
software. The first location must contain the address of the first instruction of the interrupt service
routine. The second location contains the new processor status word. The device causing the
interrupt may provide a vector address. When it asserts the interrupt request code, it also asserts
the VEC signal on line AI5 to indicate that an external vector is present. If the VEC signal is not
asserted, the DCTll provides a predetermined vector.
In~pt Aclmowledge Transaction
The interrupt acknowledge (lACK) transaction, shown in Figure 14, starts when the current
instruction has been completed .. The priority is compared with the value in the processor status
register PSR. If the interrupting device's code has a higher priority than the present PSR value, the
interrupt request is serviced. The SELO and SELl lines indicate that the current bus transaction is
an JACK. The RAS signal is the only timing strobe asserted during lACK. When it is asserted,
DAL< 15:08> (SAL < 15:08> in 8-bit bus mode) transfer the priority interrupt code that is being
acknowledged as shown in Figure 15. The DAL < 07 :02> lines contain the vector input if the VEC
signal is asserted.
1·368
Confidential and Proprietary
-
;.>
'DcTn
D-I:
....!--..."
A't,,;1W'IHIUI'IAI-}
. INTERRUPTA(:KNOWLEOGE DATA
DAL < 07:01 >
VECTOR DATA
~--~------------------~~------
PI
SEW
SELl
lACK DATA
VALID
Figure 14 • DCT11 lACK Transaction Timing Sequence
The current contents Of the PSRate then placredon the hardware stack. The progriimcounter (PC)
value at the time the interrupt is then placed onto the stack: The'PC islOllded with the addressor
the interrupt service routine from the vector location'~mdthenewPSisloaded into the PS.register
from the vector location + 2. When completed, the service routine ends with an RTI (Return from
interrupt) instruction that causes the PC and PSW values to be recovered from the stack and the
processor will continue executing theinterruptedpro~m;
or
/'
.'.
' •. ",
" __ ,~_,.--_
,J.:,'
,;,:1,: ,', :>,';"
" :','
i,~
INTERRUPT
REOUEST
.c_ JNUflRl!PT "
ACKNQWLEDGE
(lACI have previously latched data and the AI<7:0> lines are connected to pullup
circuits during the static mode. The AI < 7:0> lines are undefined in the dynamic mode and all
controls signals are unasserted.
Status Flags
The SELO and SEL 1 lines are processor status indicators. The type of transaction in process can be
detected by decoding these lines. The signal timing of thethese lines dependson the type of
transaction. Table 6 shows the· select line assignments.
Table 6 • DCTll Status Indicator Selection
SELl
SELl
Function
L
L
Read or write, ASPI), bus NOp, or FETCH'
L
H
Instruction FETCH or REFRESH}
H
L
lACK (Interrupt Acknowledge)
H
H
DMG (Direct Memory Grant)
lASPI (Assert Priority In) bus transactions check for interrupts during pOwerup and the PDp·ll
WAlT intructions.
'This code specifies a fetch operation when 4K/16K dynamic mode is selected and AlO is asserted
low during the assertion of the RXS signal.
)This code specifies a fetch operation when static or 64K and dynamic modes are selected, and a
refresh bus cycle when 4K/16K and dyn4mic modes are selected.
1-370
Confidential and Proprietary
In addition to the select line outputs, theAIO line indicates that an instruction fetch is inp.rogress.
This occurs before the assertion of the RAS signal when the 4K/16K chip dynamic RAM .mode i$
selected. The AIO line may also be asserted during a refresh transaction. The AlO signal is
controlled by the most significant bit of the internal're£resh counter. The SELO and SELl signals
can be used to verifythat a refJ:esh operatJ.Onis.. h\ p.roc~. ~~K chip dynamic RAMs are
used, AlO is the. t>J;OCeSsor
address bit·M5..
' .
,
,- ,':'
"
Sipal Line S\UJUIIar)'
.
...
..
The following tables sum.tnarize the.ftmction of data and address bus control signai,.and miscellaneous signal infQrmation Q£ tbeDCT1t
Bus Operation Summary-'1l1ble7 is a swnmaryo£ the function of the information cOntained on
the lines DAL < 15:00 > aOOAl < 7:0> during bus operations.
Table 1- DCTll Data and AddrelsBus Swmnary
P'Ut .
Line
1-7,9
DAL< 15:08:> "16-bit mode
SAL< 15:08> 8-bit mode.
DAL,<07:00> 8-or 16·bitmode
10-17
, ,.,_. '.,r
'2'"
.. ' .. '. ',-
,
,',
,,','
,
"', .. "' .._
,
:.
-'
','.,'
DAL<15:00>
Three-sta~Aur~P¥A ~~assetPdQrity(#rI) ~~()tlS
Contain pteviously data durlDga NOP or refresh. tr1msaction.
DAL< 01:00 >
DAL<15:08>
Read into the mode register on powerup or during the RESET
instruction.
DAL<07:02>
input .~. ~nafVector ~t,I)e in~t~AeVic"d\ll;:ipg~
interrupt acknowledge (lACK) transaction if the
asserted during PI.
DAL
VEe'
sigiW was
Used to output information present on.Al.< 5.:1 > during the lACK
~oo:;
..
AI<5:1>
Used to transfer interrupt 1'equ~t 1:0 the proceSsor.
AIO
Used to transfer
a.DMA request to: the processor.
...
-.
AI<7:0>
Used to transfer ~e row andcoltittm addresses from the processor.
Provides a control signal to indicate when an external vector is to be
AI5
,
used.
AI<7:0>
Receives inputs in static mode and contains previously latched data
in dynamic mode during NOP and lACK transactions.
Confidential atld Proprietary
1
lines is listed in Table 8.
.
..
.
1able 8· OCTll Address Line FunctiOnS
All Modes
Pin
Line
@PI
4K/16K Dynamic
RAS
CAS
64KDynamic
RAS
CAS
32
AlO
i5MR
FET/REF" AI4
A15 .
AI4
33
All
CP3
Al
A2
Al
A2
34
AI2
CP2
A3
A4
A3
A4
35
AD
CP1
A5
A6
A5
A6
36
Al4
CPO
A7
A8
A7
A8
37
Al5
VEe
A9
AlO
A9
AIO
38
AI6
PF
AU .
A12
All
A12
39
AI7
HAIl'
AU
AI4
A13
A14
"PET/REF AlO indicates a fetch or refresh operation in 4K/16K dynamic mode. The encoded SELO
and SELl lines determine which, transaction is occUrring. .
.
'~
Line AIO specifies a fetch or refresh operation for a 4K/16K chip dynamic RAM mode~ The SELl
and S~LO li.tlesJndicate which operation is in proeessas listed in Table 9.
1able 9· DCTll Dynamic RAM Select Line Functions
SELl
SELO
Transaction
L
L
FETCH
L
H
REFRESH
1-372
Confidential and Proprieta:ry
-
Control Signal Sununary-A summary of the control signals is contained in Table 10.
Table 10· DCTllContlOl Signal Summary
Ym
Signal
Function
24
25
SEll
SELO
TranSllct:io6'~~ ij
26
29
READY
30
31
27
RAS
CAS
PI
R/WHB
RD
28
R{WLB
WT
Transaction select 1
Idle.s,tate select
Row address select
Column address select
Priority Interrupt
Read/Write high byte (16·bit) select
Read (8..bitY
Read/Write low byte (8-bit) select
Write (8-bit)
Miscdlaneous Signal Summary-A summarY of theinis<:ellalleOUs signals is listed in Table 11. '
Pin
Sigrud
18
Bus clear
19
PUP
Powerup
21
COUT
Clock.qut
22
XTL1
Crystalinputl
23
XTLO
Crystal input 2
• Inititialization
The powerup (PUP) input has a Schmitt trigger that senSes transitions from low to high and has a
low-current internal puUdown device~tis alwap e~b~. WheMhe :plJINnput is forced high, all
DCTll operation stops. Figure 17 shows the signal timing for the powerupoperation. The assertion
of the PUP line causes the Ba:R signal to be asserted. The ocrJi signal enables the mode register to
be loaded with the configuration information. When the processor detects a high to low transition
on the PUP line, the powerup sequence starts. All information in the internal registers is undefined.
The information on DAL < 15:00 > and AI < 7;0> lines is also undefined. The control and
miscellaneous signals are not asserted. An externa11k 1% resistor must be connected from BeLR
input to ground to assure the correct operation.
Confidential andPreptietary
~----------
1·373
... .......- , - - ._."""'""..............
, ...
H ...
W$Iti""J1L....
_ ....
,.
~
_._ _ _ _"",...._ _
~_.
Ii\iILClI!i4W4i~
. .II
. \\\\.
p~J
J
II~----------~Sir!--------------
'
---r----------~rJ~------T\--~,lh!\--~i--------~
I, l
J
~_.1
L.._.1
RAs __
p,
-..In'---
__________
Figure 17 • DCTll Powerup Timing Sequence
Loading the Mode Register
The DAL < 15: 00 > provide information to change the mode register settings. Figure 18 shows the
connections of the pup line to allow the BCLR signal to load the DCTll mode register information.
During the assertiono£ BCLR, DAL < 02:00 > and DAL< 15:08> are connected to internal puUup
circuits and are asserted unless driven low by the external signals. These lines contain the mode
register information and DAL < 07 :03> are in a high-impedance condition at this time. The BCLR
signal is asserted during the powerup sequence and when a RESET instruction is executed. The
mode register will accept data during the assertion of theBCLR signal.
Vee
DAL<15:08> ,
DAL
.1
oeT11
LS244
PUP
Xl-------!...-
Fikure lS-DCTl1 Mode Reg!ster Loading Configuration
1-374
Confidential and Proprietary
RESET
OOTlt
Refresh and No Operation
The DCTll mode information loded when the BeLR signal is negated. If dynamic RAM support
has been selected; the refresh transactions will be executed to ensure the correct· start for the
dynamic RAMs: Dlliing8-bit'data bus mode, 20 REFRESH transactiohs wiUbe executed and,
during 16~bitmode, ten refresh transactionswiU be executed. During static mode, ilNOP (No
operation) bus transaction will be executed. After the refresh or NOP transactions, 'one ASPI
transaction is performed to determine if interrupts are pendip.g: the ASPI trllnsaqionasserts,CAS
and PI signals and the refresh' transaction asserts only' theRAS signal. No control signals ,are
asserted during a NOP trans9,ction while performing internal operations. .
Starting Address .
, ',.,',
A read transaction to the starting address follows the refresh or NOP transaction. The first
instruction fetch. St!il'ts the DCTll program operation. Qne, of eight$tarting addresses can be
selected by the three .most significant bits of the D10de regi.stq.Ea~! adq.ress has an associ~ted
res~t location. The restart address is the first1ocation to btr~ted when a li,ALTit;lstruction is
executed or a halt interrupt is asserted.
Oock Output
. , ' , . .
The clock ouput (COUT) is a square wave controlled by bit 0 ofth{mode register as shown in
Figure 19. Selecting constant clock mode produces a square-wavebutput at'a one-half of the
internal oscillator or XTLlinJktt frequency. When processor clock mOde (PCM) is selected, the
COUT outpUt proyides a pulSe once during eap!i mi,crocycle. No c~pse ~ relatil;lrisl:U,p ~sts
between the edges of the COUT ~gnal, andthe.int~nal oscillatot: or XTL1 ciQCk input.
lITl!
----------',
Figure 19· DCTll Clock Output Timing Sequence
Confidential and Proprietary
1-375
-
···DCTn
. Performance Data
Thbles 12 tluough 17 list l:heexecuti~n times for rut DCTiLinstructions and are used to determine
the total program exertion time. The tables list the minimum and:r,naximumexecution time of an
instrucrion~ 16-mt and8-bitmode of operation and with the memory refresh function active (on)
..
.
and not active (off). The possible system combinations are . .
• 16-bit mode with memory refreshon
• 16-bit mode with memory refresh off .
• 8-bit mode with memory refresh on
• 8-bit mode ~ith memory refresh off
With refresh on, the refresh cycle increases the execution time. The execution time of an
instruction may also vary with memory refresh on. In 8-bit mode, refresh occnrs every instruction
cycl!!. In 16~bit mode, refresh occurs every other cycle: Addressing modes 5,6', 7, I/O ,and Trap also
increase the time for execution.
The program execution time (PET) is calculated by totaling the average execution time of the
instruction used in the progr:am. The following information applies to Tables 12 thrdugll 17.
'. All times· are in microseconds .
Add 0.4. J;tS for every READY pulse that occursduring.a read or write transaction,
~ Theoperat~ frequency is
7.5 MHz. To compute the program execution time (PET) for
frequencies other ihan7.5 MHz, the following equation is used.
PET=(7.5 MHz +Fop)xIET
where lET is instruction execution time in microseconds from the tables and Fop is the operating
frequency in MHz.
.
Example: Cal<.:ulate the program execution (PET) for a MOV, RO, Rl instruction when in the static,
16-bit mode with memory refresh off. The operating frequency is 6.0 MHz.
The MOV instruction is a double-operand instruction. The IET for the source operand and the
destination operand is listed in Table 13 and 14, respectively.
IET=source mode time + destination mode time = 1.2Ils+0.4l1s= 1.6Ils'(total).
To calculate the program execution time:
PET = (7.5 MHz+6.0 MHz) x (1.6I1s)= 1.25 x 1.6=2.0 I1S
1-316
Confidential and Proprietary
-
·nml1.:
Pre1imioAty
lableU • DCTllXORand Sin@le-operancUnSkuetion Execution Time
8.BitMode
16-BitMode
ON
REFRESH
Instructions'"
Dest.
Mode
Min.
Max.
1.60
2.80
2.80
3.60
3.20
1.7.3
2.93
2.93
3.73
·3.33
4.26
:4.26
'.06
CLR(B),COM(B):
INC(B),DEC{B), ,
NEG(B),ROR(B),
ROL(B),ASR{B),
ASL(B),SWAB,
ADC(B),SBC(B),
SXT,MFPS,
XOR
0
6
7
4.13
4.93
TST(B)
0
1
2
3
4
1.60
2.40
2.40
3.20
2.80
3.73;.
3.73
1
2
3
4
.5
5,',
6
"7
MTPS
2
3
4
5
.6
7
ON
4.13
OFF
t6
2.8
2.8
3.6
3.2
4.0
4.0
4.8
ON
ON
OFF
OFF
Word
Byte
btl'.
Instr.
Word
Instr.
Byte
Instr.
2;53
5;33
253
2.4
5.2
5.2
6.8
2.4
3.6'
3.6
5.2,
5.6
7.2
7.2
5.6
5.6
8.8
7.2
2.4
4.0.,
4.0
5.6
5.2
6.0
2.4
5.33
6.93
5.73
1A6
7,46
9,06
3.73
3.73
5.33
4.13
5.86
5.86
7.46
4.0
1.73
1.6
2.53
2.53'
2,4
2.53
3.33
2.93
2.4
3.2
2.8
4.13
4.13
5.73
5.33
253
J5l
3.33
4.93
3.73
3.86;
1.6
·6.~6.
5.46
3.86
3.6
5.2
5.2
,4.66
4.4
5.46
7.06
6.0
4.53
.,6.26
7.86
7.6
6.8
3.20
4.00
4:00
4.80
4.40
.5.33
5.33
6.13
3.33
4.13
4.13
4.93
4·13
5.46
5..46
6:26
3.2
4.13
4 ..13
14.9,l .. 4.93
4:93
4.93
;'653
6.53
. 5.33
5.33
7.06
7.06
7.06
7.06
8.66
8.66
4.0
4.8
4.0
4,8
4,8·
4.8
6.4
5.2
6.8
6.8
8.4
6.4
5.2
6.8
6.8
8.4
4_0
4.0
4.8
4.4
5.2
5.2
6.0
3.2·
3.2
4.8
3.6
*TheXOR and single~operandinstruction ¢xccution times inc19de instructions fetch, instruction
decode, operand fetch, instru.ction operation, and result Output. In mode 0 and the TST(B)
instl'Uction, there is no output ..
Confidential· and PrQprietary
-------------,---"_..._-_. . . . __......_,_m"'..............
" _
•• _"....,.....".,...,,""'"
-
DGTll
PNIiminary
Table 13 • OCT 11 DoubJe-operan.dInstructionSow:c~cModeExerutionT".me
REFRESH
Instructions .
MOV(B),CMP(B),
ADD,SUB,
BIT(B),BIC(B),
BIS(B)
16·BitMode
ON
ON
Dest.
Src··
Mode (0·4)
Mode'" Min. Max.
0
1
2
3
4
1.20
2.00
2.00
2.80
2040
3.33
3.33
4.13
5
6
7
1.33
2.13
2.13
2.93
2.53
3.33
3.33
4.13
,-,
'ON
ON
8-BitMode
ON
ON
OFF
Dest.
Mode (5-7)
Min. Max.
1.33
2.13
2.13
2.93
2.53
3.33
3.33
4.13
1.33
2.13
2.13
2.93
2.53
3.46
3.46
4.26
OFF
OFF
Word Byte Word Byte
Instr. Instr. .Instr. Instr.
1.2
2.0
2.0
2.8
2.4
3.2
3.2
4.0
2.13
3.73
3.73
5.33
4.13
5.86
5.86
7.46
2.13
2.93
2.93
4.53
3.33
5.06
5.06
6.66
2.0
2.0.
3;6
2.8
2.8 .
3.6
52 . 4.4
4.0
3.2
5.6 . 4;8
5.6
4.8
7.2
6.4
"'Soutee mode times include instruction fetch, instruction decode, and source operand fetch.
TabJe 14 • DCT11 Double-operand Instruction Destination Mode Execution Time
16·BitMode
ON
ON
REFRESH
Instructions*
MOV(B),ADD,
SUB,BIC{B),
BIS(B)
Dest.
Mode
0
1
2
.3
4
5
6
7
CMP(B),BIT(B)
0
1
2
3
4
Min.
Max.
004
0.4
1.6
1.6
2.4
2.0
2.8
2.8
3.6
1.6
1.6
2.4
2.0
2.8
2.8
3.6
0.4
1.2
1.2
2.0
004
1.2
1.2
1.6
2.0
1.6
5
2.4
204
6
2.4
7
3.2
2.4
3.2
8-BitMode
ON
ON
Word Byte
Instr.
Instr.
OFF
004
1.6
0040
.2040
1.6
2.4
2.0
2.8
2.8
5.6
2040
4.00
2.80
4.53
4.53
6.13
0.4
1.2
1.2
2.0
1.6
2.4
2.4
0.40'
2.00
2.00
3.60
3.2
5.73
2040
4.13
4.13
0.40
1.6
1.6
3.20
2.00
3.73
.3.73
5.33
0.40
1.20
1.20
2.80
1.60
3.33
3.33
4.93
OFF
Word
Instr.
0.4
2.4
2.4
4.0
2.8
4.4
4.4
6.0
0.4
2.0
2.0
3.6
204
4.0
4.0
5.6
OFF
Byte
Instr.
0.4
1.6
1.6
3.2
2.0
3.6
3.6
5.2
0.4
1.2
1.2
2.8
1.6
3.2
3.2
4.8
"'Destination mode times include destination operand fetch, instruction operation, and result
output. In destination mode 0 and the CMP{B) and BIT(B) instructions, there are no outputs.
1-378
Confidential and Proprietary
-
Table 15 ·nCTll Branch, Trap, and Interrupt Instruction Execution Time
16·Bit Mode
ON
.ON
REFRESH
OFF
Ile$t.
8·BitMode
ON
ON
Word Byte
Instr.
Instr.
OFF
Word
Instr.
OFF
Ins~
Byte
In$tructions*
Mode
Min.
,Max.
BR,BNE,BEQ,BPL,
NA
1.60
1.73
1.6
2.53
NA
2.4
Nit
NA
NA
NA
6.53
6.66
" '6.4
9:73
9.6
3.20
333
3.2
4.93
4.8
NA
NA
4.40
453
4.4
7.13
NA
NA
NA,
7.0
NA
BMI,BVC.BVS;BCC~
BCS,Bf}E,BLT,BGT,
BtE,BHi;BLOS,'
BHIS,BLO
EMT,TRAp,BPT,IOT
IU'!
RTT
*1. Brancninstruct:ion execution times include in~tructionfetch, instruction decoding, doubling
the Mfset, testing the conditions,\ll'ld adding the offset to the PC if the conditions are met. The
execution times are not affected whether or not a branch is taken.
2. Trap instruction execution times include instruction fetch, instruction decode, pushing the
PSW and PC onto the stack, loading the PC with the contents of the vector location, and loading
the PSWwiththe contents oithe vector location pluuwo.
3. Return frOmIb~pt"inStfudioQ:eiecti!i()n~imes inclu,:Jeinstruction fetch; ;instruction
decode, and removiogt~ 00 information and PS:W.rromtne)stack.
, Table 16 • Dent-Jump andSubroutltJe Instru~ E~cution Time
16·BitMode
ON
.ON
REFRESH
OFF
Dest.
InStructions"
Mode
Min.
. Max.
]MP
1
2
3
4
5
6
7
2.00
2.40
2.40
2.40
2.93
2:93
2,13
2.53
2.53
2.53
1
3.60
4.00
4.00
4.00
]SR
2
5
4
5
6
7
3.73
4.53
453
5.33
2~93
2i9:3
' 3.73
3.73
4.1.3
4.13
4.13
4.53
4.53
5.33
8·BitMode
ON
ON
Word' Byte
Instr.
Instr.
2.0
2.4
2.4
2.4
2.8
2.8
3.6
2.93
3.33
4.13
.'U3
4.53
453
6.13
3.6
5.33
5.73
6.53
5.73
6.93
6.93
8.53
4.0
4.0
4.0
4.4
4.4
5.2
Confidential and Proprietary
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
OFF
Word
Instr.
2.8
3.2
4,0
3.2
4.4
404
6.0
52
5.6
6,4
5.6
6.8
6:8
8.4
9F,F
]Jyte
Insu.
'NA
NA
NA
NA
NA
NA'
'NA
NA
NA
NA
NA
NA
NA
NA
1-379
Preliminary
16..Bit Mode .'
REFRESH
ON
ON
OFF
,:J
&-BitMode
ON
ON
,Word
Instr.
OFF
OFF
Byte
Word
Byte
Instr.
Instr.
!nstr.
Instructions'"
Min.
Max.
RTS
2.80
2.93
2.8
453
NA
4.4
NA
2.40
2.53
2.4
3.33
NA
3.2'
NA
SOB
NA
*1. JMPf.[SR destination mode 0 is an illegal instruction that traps to vector location 10.
2. JMP execution times include instruction fetch, instruction decode, operand fetch, anqloading
the Pc.
.. '
3. JSR execution times include instruction decode, operand fetch, pushing the 1inkag~ register
onto the stack, and loading the PC.
4. RTS execution times inludeinstruction fetch, instruction decode, loading the PC, popping the
stack, and loading the linkage register.
5. SQB execution timesinelude instruction fetch, instruction decode, decrementing the count
register, testing for zero, and branching, if necessary. The execution time is not ,affected whether
or not a branch is taken.
.
TAble 17· DCTU Miscellanealls and Conditi~n Code Instruction ~xecution Time
16-BitMode
REFRESH
ON
ON
S.BitMode
ON
ON
OFF
OFF
Word
!nstr.
Byte
Byte
Instr.
Word
Instr.
Instr.
5.6
8.4
NA
8.0
NA
1.73
1.6
2.43
NA
2.4
NA
14.60
14.73
14.6
16.53
NA
16.4
NA
NA
2.40
2.53
2.4
3.33
NA
3.2
NA
CLC,CLV,CLZ,CLN,
CCC,SEC,SEV,SEZ,
SEN,SCC
NA
2.40
2.53
2.4
3.33
NA
3.2
NA
MFPT
NA
2.00
2.13
2.0
2.93
NA
2.8
NA
Instructions'"
Dest.
Mode
Min.
Max.
HALT
NA
5.73
5.86
WAIT
NA
1.60
RESET
NA,
NOP
OFF
* 1. ,The HALT instruction execution time includes instruction fetch, instruction decode, writing
the PC information and PSW onto the stack, loading the PSW with 340, and loading the PC with
the, testaruddress.
2. The WAIT instruction execUtion time includes instruc~iol1 fetch, instruction decode, pulsing
PI,to samplc;the interrupt lines, and doing a REFRESH cycle if refresh is on. If no interrupt lines
were sensed by the DCTll to be asserted during the PI pulse, the WAIT instruction will cycle in a
t21ls loop pulsing PI. If refresl-) in on, the loop will be 1.3 3llsqlaximum. The looping will continue
until an interrupt line is asserted and sensed by the pCTll.
1-380
Confidential and Proprietary
PreI·
·
. ~ary
3/· The~SET exec\Jtton time includes instruction fetch, instruction decode, the ~onof
8M; mdthe w:ritingof DAL <: 15:00> into the mode register.
4.. The N01?~tiOtl tilDe includes instruction fetch, instrucd0tl decode, and idletime.
5.
Condi~Il~ (CC)~tructionexeQltion ~~~.~.iris~ion fetch, instructiond~e,
.'
and the Setting or resetting of the appropriate statUs ~ in the psw.
Interrupt Latency
Theinterrupt)!!tellCY~~easured from
the time t~'Wtet;lif!~trequest (IRQ) is asserted on the AI
inputs until tnenmethat the DCTll is ready to fetch the'titst instruction in the service routine.
Figure ~Q
sb9WS ~~interrupt
lateru,;y,palllme1;~r,s,
"
- "",
, "-,
- - '''''.
,,<'-' '.',,,-
It
LAST
INl;tRUCTION'
1"
II
lACK
MICROCODE
I
I
I
. . I.:...J'
I
_-1>.-......
I
8-~-- C --:-71
" .
t
I
"r
t
1.1
I;
. I
.
. .,' 't
I
I
,
I
r
I
~I·····l
PI
I
I . , 1:'.1
I
.....----.
'-0.:..
r'
'1
I
t .'
lACK
FlflSTINSTRVCTION
OF SERVICE
..
ROUTINE
".~
----_.,,-,. --".,;1 ...•;,
'<1
The procel\Sor ~ntin.u~ to.~te~c;t~s Jll!.ltiltbe rc::queri~ is.la~che.:l,l?y tht\as~t~pn .ofthe
PI signal which C~~Pl1\~ tl).e.uts~~~ti,9nt~~~in~)~C~I;1~~t'1fe~urJ:'(:n~ inst[U~ti()n is
then completed and~elACKmlcrocode lsexecut@ to ac:knowletlge the lOterrupt request and the
following operationsareperforined.
.'
, .,
• Arbitrate priority.
• Issue t.he lACK signal.
• Store proCe8SotstatUs imdprogramcountetvaiues,.
".• Load' new p.fucess9t~J~tUsi~rid prognllOcounter
values.
>','1' ','
" ",:], .' , ,.;
>
':,"
\'
,.' • • ,"'\"
'
j ','
"
,-' -
","
,-/
'
:,
',,',:'"
"
,
Con£idential·lll\d'Proprietary
.
-
'_=._....','.
..'D-l..:
"L,':~1
The.intel'rupt.~uest:;(IRQ} ,i:tt\sswneq tQ 9c(:J.l;t4l:Jdng;,~;~p'p·llJu~P,;t9:S!1brQ~tip.e . (JSR)
instruction (mode 2 or 4) or duringtm;e~ul~t9rJr~p;{EMT)se~w~nce whichprQvides ~ fi).axiriltim
delay for an IRQ. ,:me, maxinwm latendel( timeS~&s'4r.ne tha,t the PC Tlljs in the,. standard
microqrele mode andthe READY signalis pot asserted during the transaction ..Table 18lists the
maximum latency tiriles for the 16- arid 8-hit modes, during dynamic and statk operatiori;
Table 18· DCTll 8- and 16-bit Mode Latency Time (7.5 MHz)
':}';
16-BitMode
Dest.
Mode
Dynamic
Static
D}tnamic ' Static
CPO-CP3,PF,HAi':J'
(Internal vector)
NA
15.47
15.20
22.13
21.60
VEC,CPO·CP3
(External vector)
NA
15.87
15.60
22.53
22.00
DMR
NA
3.66
3.52
4.46
4.32
WAIT Instruction
Internal vector
NA
7.87
7,73
10.53
10.13
External vector
NA
8.27
8.13
10.93
10.53
DMR
NA
1.66
1.66
1.79
1.66
Active Inputs*
8-BitMode'
*1. The latenqr time is in microseconds and the clock frequenqr is.. 7.5MH2.
2. Interrupt latenqr is calculated from the time the Interrupt Request is asserted either on the AI
lines (in static modes) or on the input of theA! tine driver (in dynamic modes) to the time the
DCTll is ready to fetch th~ first,i~stru<:ti011 in the interrupt's service routine.
3. DMG latency is calculated from the time the DMR signal is valid on the input of the AI line
driver to the time the DCTU.as~rts. the DMG sign.a1.
4. The WAIT instruction latencies are the maximum encountered in the instruction's execution
state and do not include the instruction fetch or the instruction decode.
5. .The worstctase times refer td IRQ oCCUrring durIng aJSR (mode 2 or 4)EMT sequence.
6~ . Theworst-case times refer toDMR CJCcurrihg dUring aMTPS (rhod~ 0) insttuction.
7. The timings assume that the DeTll
is not in long bus qrde·andlJ.o ready slips occur...
DMALatency
The maximum time between a DMA request and grant dep~ndson the DCTll mode.The .
maximum time occurs during a Move byte td ProCf:ssorStatmdM1PS)instruction itt rnodeOand
is measured from the time that the DMR signal is valid on lineAIOuntil the DCTll asserts the
DMG signal. Themaximullllatencies assulllethaftPepClll il!,i~ the :;~l1dard ~croqrcle,mode
and the READY signal is not asserted during
the maxiriium bMR latencies listed
in Table 18.
atransacrlon.
Confidential·and Pn;>prietm'
are
-
.
• Instruction Set
Refer to;:.Appendix B for a IZOnll1lete list of the DCTll micrOprocessor instruction set .
• SpedficatiOns
The mechanical, electrical, and enviromental characteristics and specificatio1"!s£or theBcrU are
described inthef.QUowjngparagraphs. The t~t FOnditiops for~be electricalviilu1!S are :fonows
unless.specified di£ferently,.m the tables. Refer to Digital specification A-PS·2100002-GStor
general information on the integrated circuits.
'as
• Power supply voltage (Vcc): 5.0 ±590
• Rdativepumidity; 10% tQ' 90% (qo;tctmdensing)
M~ ConfigWation
.
.
The physical dimen~ons of the DCTll 40-pinDWare contained in Appendix E.
Absolute Maximum Ratings
'.'
Stresses greater than the absolute maximum ratingsmaycau$e ~manent qij:mag/£ fq'thf! deviCe.
Exposuteto the absolute maximum ratings' foliextended periQd$ may adversely affect the
reliability of this device.
• Pin voltage: -0.5 Y to 7..oV
• Power dissipation: 1.1 W (maximum) at OOG
• Ambient operating temperature: .ooe to 70?:C
• Storage temperature: -55°C to 1?5°~
• Rdativehumidity: 10% to 95% (nohronden'sH{g) ':
----------------------------------------------------~~~-.~
• Supply voltage (Vcc): 5.0 volts ± 5 %
• Supply current (leJ: 190 rnA (maximum)
de: Electrical Characteristics
Thede electrical characteristics oftheDCT 11 for the operating :voltage and temperature ranges
specified and withVss=OV are listed in Table 19. Refer to ,AI <7:0 >.
Vm
High-level inpUt'
voltage for PUP
VIIi
Low-level input
voltage on READY,
DAL < 15:00> ,AI < 7:0 >
V1L
Low-level input
voltage for PUP
V1L
High-level
output voltage
forDAL<15:oo>,
COYT, PI, ~EL1, SEW
VOH
IoH =-700.}lA
High-level
VoliA
lou =:- 700 I.lA
VOHD
(
,;'
"-
',,t'.
,
;j,~ents
Min.
Max.
2.0
Vee
··Circuit
Units
V
"
' ~< ,
d
":'0.5*
0..6
C1,C2
V
C1,C2
2.4
V
C1
2.6
V
C1
2.2
IoH=-700 }lA
terminated with .
V
C1
V
C1
V
·····C2···
output voltage for
AI<7:0.>
High-level
output voltage for
BCLR
lkn resistor to
Vss
.
High-level
VoHe
output voltage for
RAS, CAS, R/WLB, R/WHB
IoH=-100~
2.S .
Low-level
VOL
output vo!tage for
DAL< 15:0.0.> ,AI<7:O.>,
COUT, PI, SEll, SELO,
BCLR, ill, 00,
~=3.2mA
0
oX
: i •.
R,f'Wi:B, R/WHB
Input capacitance
far READY,
DAL< 15:oo>,AI<7:O.>
C;.
Output capaciCoat
tanee for three·
state load on
DAL< 15:00>,AI<7:0>,
COUT, PI, SELl, SELO,
BCLR, RAS, 00, R/WHB,
R/'WLB
1-384
Con4dentW~dJ?ropri~~
10.
pF
20.
pF
....
Test
Condition
Fligh-inputthree-c "~
state leakage
current on DAL < 15:00 >
I
Minimum input
current£or
.internal pullups
on AI < 7:0> ,'f:tEAD'Y
In."
1m
-0.1
V... -2.4V
rnA
C4
rnA
C4
'190
rnA
C7
700
.}1A
-6.4
rnA
-1.0
DAL<02:00>,DAL< 15:07>
Maximum input
1m
current for
internal pullups
on AI < 7:0> ,""'RE-'A]j'"""""'"iY
DAL < 02:00> ,DAL< 15:07 >
Power supply
current on Vcc
Icc
High-input
current on XTLl
~D.IIl
static
2,4 tSVcc>
.' ;X1a.Q,gtlQunded,
.. < 0.6V,
Low-input
-o.~
All others
VOL =0.8 V
VOI.=O.8 V
VoL =O.8 V
VOH =- 2.4 V
Voa=2.2 V
VOH=2.0 V
• Output timings are measured using a purely capacitive load of 80 pF.
• De£ltllttons and abbreviations;· ~
\,,'
",';_'
,{I,','
-J!,,!,;JncTA~freClluency..
.
--.(Le.) = leading edge, (t.e.) =trailing edge
.
-Fop;'" XTL1, XTLO internal oscillator operating frequenCy. If an external TTL clockisusoo, F~p
minimum is 0 Hz (i.e., de). Internal data will not be lost i£ the input clock is stopped at either a
high or low level. The leading (low-to-l1igh) edge of the clock starts theinteinal tirhlngto
produce an output signal(RAS, CAS, PI, etc.). The tr3iling (high-t~-low) edge causes the;~id
to be asserted at the pin of the DCT 11. The delay from the edge of the input clock to the outP\Jt
signal is not defined.
.
tCH---!
Figure 21 • DCTllClockJnput Waveform
Table 20· DCTll Clock Input Timing Parameters
7.'JMHz
Symbol
teH and teL
10 MHz
Description
Min •.
Max.
Min.
Max.
Units
Operating FreqUency
0.1
7.5 .
0.1
10
MHz
CyeleTime
133
100
ns
Pl.l1se Width
20
20
ns
ns
1-386
Confidential and Proprietary
-
Figure 22· Derll Powerup and Reset Signal Timing
Max.
tl'fl'
..hie 21· DCTU PowerupadBesetT"'~
Mm.
'lest Conditions*
PUP(t.e.)to first instrUction fetch
295T
tplIU
PUP(t.e.)to BCLR(t.e)
99T
lOOT
tUPl'
PUP with
100 I.IS
t pMu
PUP(t.e.)to OAL, mode data, valid input
74T
tPIIC
PUP(1.e.)to JRll((1.e.)
lOOns
tllMlI
B'Cm(1.e~) to OAL,
74T
Symbol
mode data valid, POP·ll
315T
RESET instruction
tlCll
BCLR width during a PDP-ll RESET instruction
84T
tMHII
B'Cm(t.e.) to OAL, mode data hold
Ons
tPUr
PUP(1.e.).to DAL, input float
250ns
treo
PUP(t.e.) to COUT(l.e.)
T+60ns
*1. Low-current pullup circuits are provided by the DCTll on OAL < 02:00 > , OAL < 15:08> and
AI < 7:0> lines while the Bern line is &. .serte --------------------~'N~D=.=T.=.~M~'N=A~n~----------------~~
----------~
'.
SElO
"&i' _______ .l
p, ------,
'1'.
J.Nt£RAUfT ACKN~~~ (lAC:JC!JC.~S;~:", ~
,iJ';;i
...
Table 22 • DCTU ~.nd
Ihf.ettUpt1\CJmow~,~Parametets
.
.~
~-
Requirements
Symbol
Test ConditiOns'"
Min.
toeD
COUT period,pulse,mqge, refresh, .
IACK, and DMA .' ..
.
4T
tASK
AI row ad~ss to RAS(1.l!.); set up
T-83ns
tAHK
RAS(t.e.) to AI row address hold'
T'-'60ns
tSHF
RAS(t.e.) to SELO(t,eJ
T-123 ns
tFFII
SELO(l.e.) to RAsa.e.)
T-23 ns
T-SO nst
tFllP
RAS width;'REFRESH, IACK
2T+35ns
tl'SP
SELO width, REFRESH
4T-20 ns
tua
'RAS(l.e.) to COUT(he.)
T-15 ns
t YltO
COUT(t.e.) to ready (l.e.),
multipleC:y¢leexteQsjons
top
SELl width,IACK}
3T-66ns
tSPlt
SELl~,14cK
T
tms
SELl(t.e:) to RA~'(t.e.}
45 ns
t YD
m(l.e.)toREmY~le.)
tltD
SELl(l.e.) set up to RAS(l.e.). IACK
T-63 ns
tWHJl
'RAS(t.e.) to DAL < 15:08 > hold
T-U8 os
T~90 nst
t DSIl
DAL< 15:08> ,IACK datavalid to itAS(l.e.)
T-48 ns
t"RD
RAS(l.e.) to vector, must be valid
on DAL< 07:02 >
tlalS
,
SELi(t.e.) to DAL vector hold
Max.
2T-127 ns
T-103 ns
2T-148 ns
T-25 nst
Ons
* 1. AsSertion of the SELO line depends on mode selection of 4K/16K.
2. Add T(ns) if in long microcycle mode. If READY slips are initiated, add H T(ns) where
T= l/Fop
H == number of READY pulses multiplied by 3 for standard microcycle mode, multiplied by 4 for
long microcycle mode.
3. Violation of tYltJl will cause unpredictable results.
4 t.e. = trailing edge, I.e. =leading edge
+10 MHz version only
..,
PteIum·
•...
Symbol
COUT width when high
T-3}ns
~(l.e.) to COUT(l.e.)
10 ns, '.;
.
Onst
tu,
PI(l.e.) to AI as input, data must
2T-167ns
be valid
t.AE
PI(t.e.) to AI, next address
1-4Ons
tan
SELl(l.e.) ~(l.e.)
21-63ns
DMA bus(DAL,AI,RIW) disable to
Ons
tAl'S
SELO(l.e.)
tMSP
SELO width, DMA
8T-38 ns
tsss
SELO(te.) to SEL1(l.e.)
Ons
tsPR
SELl recovery, IACK, DMA
T
t MSK
SELl width, DMA
7T-68os
t MOC
COUT(t.e.) to GAS(l.e.)
1+10ns
1·391
SymhoI
Test Conditiens'll' .
tam
CAS(t.e.) to DAL, next address
,
~
tltDE
t·,",
RAS(l.e.) to COUT(t.e.)
t MAO
..
T-51 ns
T-118 ns
T ...90nst
,'m(t.e.) tODAL,next address
tMll~.RAS(l.e.) to oo(1.e.), DMA
2T+ 10 ns
3T-90ns
PI(U.) to
AI as input, hold
,
Ons
CAS{l.e.) toPIQ.e.)
T-28ns
~
-
"\
"
2T-47 ns
PI width
2T-J7 nst
*1. Add T(ns) if in long mi~emgde.I(m~ ~ADY •
slips are initiated, add H T(ns)
where
T= l[Fop
H =number of READY pulses multiplied by .3 for standard microcyde mode and multiplied by 4
for long microcyde mage'
2. Add 4T for each READY pulst;.
3. Add 8T for each additional consecunveDMA cycle .
. 4. The DMAdevice aSserts theDAL<15:00 > 1ine~.t\l<:7:Q?:Up.e~.and.readandWrite signals,
The DMA device is responsible for preventing three-state coOructs andfora1i~,for prechatge
times required by their external circuits.
. ...!
~ ~
5. t.e,:: trailing edge, I.e. =leading edge
tlO MHz version only'
\ ,;l
·.PteIi.tnioay
AI
.
OAL
... .lAEAQI.
AIlIt
(OELAVEOI
SELO
Figure 25 • DeT1! Rtmtl,. Write, and Ready Signal Timing
. ;'>~'I:i....
.'~
13ti~?',Q.
Symbol
TestGondition..
.,
COUT width when high
RAS(l.e.)
rot~UT(Le.)
t
"'e'
-
,'~
C"
Max.
T"':33 ns
10ns
2T-U7 ns
COUT(t:e:) toREADV(1.e.)
",
""
\
:RASa.e.) to REAbY(te.}
3T-125 ns
3T-l00 nst
READY recb~·
2T-U5ns
tY1'W
READY pulSewklth .
6005
. , 2T;:-i120ns, .'
T-51 ns
tMBO
tASe
tlHP
tARe
OO(t.e.) to'R:AS(t.e.)
50ns
RASa.e.) to 'CXS(1.e.)
T+10nS
PI(t.e.) to :RAS(t.e.)
CAS width
lOns
,.
3T290ns
CAS{l.e.) PI(l.e.)
T-28ns
AIrowaddfess tom(i.e.), set up
T-8>ns
AI column address to OO(l.e.), set
up
'12ns '
PI(t.e.) to AI as input, hold
Ons
m(l.e.) to AI row address hold
T-60ns
OO{l.e.) to AI column address hold
T-53 ns
2T-167 ns
T-90nst
PI(l.e.) to AI as input, data must
be valid
tPIP
PI width
2T-47 ns
2T-37 ns t
PI(t.e.) to AI, next address
T-40ns
CAS(l.e.) to DAL data valid,
write cycle
80ns
ConndenthitandPropnetary
m
-'\'i1j-7·
;;~tr;~
~...
_
m(~.:e;H;o~~cle·
mode, R/Whold
OO(t.e.) to DAL, read data hold
tNIIIP
R/W width, standati:! ~le
mode
tWIt
0 ns
P
6T-66 ns
SELO(l.e.) to wa.e.),
instruction FEn:H
R/W(l.e.) to OO(l.e.), standard
microcycle mode
tsSF
-'t~X-JT~'8
~PAL,< ~;'t~>. ·l'he>41pu:t·'lWesp:~q~aJ:\,inPQt
only when a low is required Oecause the DCTll provides pullup icircuit~Qn~e"ljn~whe~. th,e
~'~~i!:s:as~~t,.•,.,
Figu;ii~Dctll T;itCill'MOOe Register ~'CircJit
~
Clock Circuits
.. ' .............. ,. . ...
.. . . .
....".. '........;. <
•
The DCTll clock cin:uit is cont~lled extem~i~~~.~rystal~;;~.~.!1J- oscillator
Figure 28. during an lACK transaction. The information is transferred
when the VE'E signal on line Al5 is asserted.
LS244
GND
~SULTlNG
0A107
OALOG
VECTOR"
(S4)
OEV3~
OALOS
(Soli
DEV 2 lACK •
DEV llA.CK
DEVOiiCK
0AL04
0AL03
(64)
(70)
01\\:.02
lACK'
OAL12 -
__l __ ~.J
.iACj( = (S£LO . SEl.l) + (RAs)
"CAN BE HAROWIRED IF A SINGLE EXTERNAL VECTOR INTERRUPT IS USEO
'''USED ONLY WITH BOTH EXTERNAL AND iNTERNAL VECTOR
(IF EXTERNAL ONLY, USE lACK)
Figure 31 • DCTll Typical lACK External Vector Circuit
DMA Request Interface
DMA requests to the DCT11 can be generated by the circuit showl1 in Figure 32. The flip.flop is set
by the peripheral OMA.request when the ~ signalis assertef!provided that the word count
overflow signal is not asserted. When the PI line is asserted, the:request AlO is gated tQ the DCT 11
on line AIO. With the 00 signal asserted, the assertion of ~,t1'ansaction complete (Te) signal
clears the flip-flop. The reset input during thepowerup sequence will aI$O clear the flip-flop.
TC
PERIPHERAL REO (1) H
10---0.)1()-- AIO
RESET
Figure 32 • DCTll Typical DMA Interface Ret/ue$t Circuit
Confidential and Proprietary
1·399
· Section 2-VIdeo Ptocessors and Contl'ollers
Digital's new generation of video chips can be used for terminlilsand display systems and include
new rusplay£eatures for larger screen sizes, varable pitch fonts, ~ar screen region:;, and bit.
map graphics generation.
78680 Video ProcessOI'-The 78680 video processor (VIPER) is .~pin HMOS cerquaddevice that
is used with the 78690 video control to provide high.Sl',*,~el processing of video data
including display refresh, window scrolling, and screen updates. ~t:transfersdata into and out of the
bit-map memory planes according to the instructions issued by,the 78690 video controller.
78690 Video Control- The 78690 video control (ADDER) is an 84-pin ZMOS cerquad device used
with the 78660 video processor to provide scan timing, systemstatl,ls generation, memory address
generation for a video display refresh, and scron and update o~t@tions.
DeJ03 ProF)'tJmmable Videodisplay CU1'Sf»' Logic-The DC503isa44-pin cerquad device used to
display a cursor font on the CRT. The shape of the cursor illp~ainrned into the DC503 thereby
enabling the selection of various character shapes or icons tOPetised as the cursol:'.
Confidential and Proprietary
• TWo FfFO:lm:€£ersi£otscreenrefreshandscrol:ling:·
"
,'" ,
'
~
-
-
y
"
" "
H
-,
• Background fill on scroll
• Barrel shifter to
and scroll data
• Data transfer in either X- or Z·mode
-X-mode, one word = 16 pixels per plane
-Z mode, one word =<\~. planes peJ;',l'ixd.
,i;,
,~'Z: 1_'
,~'\, ' "
~
• Description
t\;, ,
, :'
,;"';.,
_J',:N~;:::,,:_\~<;
\"
""".:"
The 78680 video p~sor (VIPER) is a data.pathchip that is ~$ed with dt~q8690 video control
(Adder) chiptOinlPiement a high-performance, bit-map OOlpmcs sY.$~em "using a color or
monochrome display. Figure 1 is a block diagram of the video processor. .
"~
Figure 1 • 78680 Video Processor Block Diagram
Confidential and Proprietary
2-1
receives commands from the video control and performs the data manipulations requiredJ91'
sc:reen refresh, scrolling of windows, and screenupdates. It provides the bandwidth neceSsru-y to
display up to 850,000 pixels on a high-resolu#on,CRT:at an, aO-Hzrefresh ,1Ili'e, It.qontains a
prograli1n:lable bus-width sttIJctureand ioternalbuffering for~se \Vith64K oJ:'256KRAMs .
. Pin and SignalDescription
This section provides a brief description oftbeil1l>ut 'aildoutPllt signals andp(jWer and ground
connections for the 78680 video processor68·pinCl.'$quadpackage, The pin assignments are
identified in Figure 2 and the signals are summarized in Table 1.
,
"
' '" i '
' '
-, '
~
,,
'- "
, ) ,.,
' ',',';
V$S
VI'S
Vu
Vbb
Vdd
SYNC
RoiWJ!f
128/m
1-------------,
LTCLK
I
I
I
I
v..:;!
I
I
I
V.. l
V•• l
01000
01001
II
01002
I
I
01003
I
I
78660 VIDEO
PROCESS0 ft IVIPE~
CHIP'
I
01005
1002
Vdd
1003
1004
Vss
,
.1006
1
(CA VITYOOWN)
I
I ___..:....-'-_'- __ --_JI
L
01004
IDOl
t
I
I
TOP VIEW
cs
1005
1007
VI'S
Vss
01006
Vn3
Vdd
Vn3
.
.
Fig~re 2· 78680 Pin AssignJtehis
2-2
,
.-.~---~'~,",<-.-",,",,~--------.-~'~~-~-~~~'
Confidential and Proprietary
- - - .... ~-~-~~~.......,.,,--""" ....."""'-~--~----------
31-:3J,~
3~.36;~8
}9.46,;
56-59
x_'
61*
63
SYNC
....",...~."......~~~---=~,....,-..".,...~.,.,..,.....,...,.t't-.,..,.."l'!'-~,..
~',thr:s~'frH~h
tfb¥;~~!l~)~ii:fiiap
'r":.')"
,-"i - ..;.,~-' ,,:--'
9,22,23,
26,37,47
48,53,54,
62
input'
1,20,21,24
input
27-30,34
41-45,51,52
67,68
",'
Ground-Ground :reference.
'''.. c_."
',- -
Bit Map Interface Signals , .......... / ; ' , , ' . . . ."... "'.:,"
, .' ."
Bit.map,,~~, I!tP'Jtl()utput(L'itO:<6itn:;i.)\L:"f1iese1lties;co'fillin.the bit:map data input and
output data to each bitmaP me~,~en th~,:~plW~;~al. is high, 't~~JO < 15 :00> output
drivers ~reahigh"itn~d~cestate. ,
.; ,... ,' ,,'
ScroD (SCROLL)-This sig~~ determines which of th~ data words received on the DIO < 15 :00 >
lines are to be scrolled.
"
~eEnahle(PE)-1'hissignal determines if the bit-mapmemorymay ptocessQ writeoperati6n.
l28~~ 16.LitM6de(l2St16>--Wh'enhigh, this signal enables the processing"f 12S-bits for screen
refreshandSl.:l,'Olling operations. ~enlow, 16 bit bit-map Ilpdate opt!rations are enabled.
BitlmijiMtmory Read/Bit.tnapMemary Write (RIJ/WR)-Whenhigh/this signal allows the
video processor to receive bit-map memory data and the DIG < 15:00> are a high-impedance
state., When low, the falling edge of the RD/WR signal latches the bit-map memory data on the
DlO.<15:oo >', U~sand enablcs'tl;!eJW5 < 15 :O(»o~~P!lt drivers.
Latch Clock (LTCLK)-When the' RD/WR and 128/16 lines are high, the trailing edge of the
r;rcLK sigJ'la11atches ttl, l)it-m,ap metnr.:>ty data on the, OlD < 15 :OO::-.)ines.When this lineis.1ow
',' and the 128/I6line is high, the Iead4'!geqge of LTCLK causes valid scrolled data to be shifted ~ut on
the DIO< 15:00> lines.
'
SynchtOnize (SYNC)-Thls pulse init~es alI internal control flip-fIdps and latches and updates
some maste~slaveregisters.This signru does not perto!:,m th~ f\lnction of a reset input.
Video Bus Interface Signals
Vldeo:(:V1P -< ):p> )"",:"The fi;sfi:l.g ~dge of the ALPHA '1 signal shifts the !jCreep refresh data out on
these lines.
'
ALPHAl~TIlls sig~~ ciu~es the data to beshiftedl;othkVlD< 3:0>
lill(:S.
Instruction/Data Bus InterfaeeSignS!s'
~se J ~ 'Pljase, 2 "qOOu ,{PR,ll and PHI2)- Thes~ "are nOhovef:1~ppipg' clock inpUts that
determille the overall dinirtg ~d con~rol of the video processor.
.
~lf~led (~S) __ Wh~ ¥ue 10 <7 ","is high, thi~, signaHs asserteptoallow the incoming
'fnstru,ction to be I~tchedan? exec~ted. If line lD < 7 > is'lbw, the incoriUnginstruction is ignored
wh~n the CS signal is as~ert~a. When receiving data on lines lD<7:0>, the polarity of CS and/or
lD7is irrelevant.
"
'~tructi6nDat.i (IO<'7:0> ):.i.;..These input and oiitt5ut lines normally remains in a highimpedance state duringfnputinstrtictions and data. The output drivers are enabled by the internal
execution of Z-axis or control store RAM instructions,. ,
."Cbtifidentialandi Proprietary
-
Preliminary
78680
Power and Ground Connections
Power Supply (VDD)-Supplies 5 Vdc power to the 78680 video processor.
Ground (Vss}-Ground reference for all internal logic.
Ground (Vss.)-Groundreference for the output drivers of lines DIO < 15:0> .
GrQund , VID<3:0 >, lind PE signals.
Cavity-Chip sub$trate that connects to VBB pin 60. ,
• Architecture
Summary
A typical bit-map processor system, shown in Figure 3, consists of high-speed timingJogic, a local
processor or remote processor that performsbMA operations, the 7869() video control, the 78680
video processor, bit-map memory planes, and the color map and shift register logic. The timipg
logic generates the system clql:k l'~e~. ,The locru p~cessor P~c¥7s the, c0!llmands to uppa;t~'the
video control memory. The video control performs functions 'that ate C9mmon to alI'lIlemory
planes such as raster computation operations, scan tit)llng,systemstatus generation, at"ld,memory
address generation. Each video processor transfers i~9r,trultion into and out 6'£ its bit-m.ap memorY
plane. The output data is transferred through the shifti:egister to a color mapahddigital-tb-analog
converter to provide the composite video to a monitor.
PROCESSOR
MONITOR
UP TO 24
PLANES
Figure 3· 78680 Typical Bit-map Graphics System Configuration
Confidentiru and Proprietary
2-5
...
"'78680
The video processor communicates through the instruction/data{ID} bus, the bit-map memory
address bus, and the display video bus,
The source, destination, barrel-shift constant; and edge maskdtlta is transferred to the video
processor registers through the 10 bus whicp controls theoperatiqn of the video pro{;essor.ThelD
bus is used to load andread registers and to execute direct or indirect instructions. Data cap als~ be
exchanged between the registers of other video processors through 'this bus. During a source
operation, the video processor receives the source information from the Video control and locates
the source in the bit-map memory. During the destination opemtion, the video processor receives a
destination code and an edge mask to determine which bits of the data bus are to be written.
The display memory bus transfers the address required to automatically refresh the memory, the
scrolling information, and the screen update information.
The display video bus connects the video processor to the display circuits including, the shift
'
registers,;coior map, and digital-to-analog converters.
Hardware Description
The following paragraphs provide a brief description of the major hardware functions of the video
proCessor shown in Figure 1.
'
Input FIFO-The 8-bit hy 17 word first,in/first-out (FIFO) buffer p~rmits uninterrupted data flow
between bit-mat;> memory and the external display circuits forscreel1 refreshing. The maximum
data rate into the input FIFO buffer is approximately 11.5 MHz.
Word.to-nihhle Converter-This converter reads the input FIFO buffer, divides the word into 4bit nibbles, and transfers the nibbles to the video output bus. The maximum docking rate of the
converter is approximately 17.2 MHz.
Output FIFO-Because of the timing constraints, the video processor stores the scrolled data in
the dynamic 16-bit by 16-word output FIFO buffer before returning the data to the bit-map
memory. The maximum data rate from the output FIFO is approximately 115MHz. Data should
not remain in the FIFO buffer for more than 30 microseconds. Any test vector rate should therefore
be greater than 1.25 MHz (less than 800 ns per vector);
Barrel Shifter-The 16-bit barrel shifter is used to provide horizontal motion on the screen. The
barrel shifter multiplexes the indeeendent processes of scrolling and updating the bit-map
memories so they occur concurrently.
Fill Register-During horizontal scrolling, the video processor creates voids at the left and right
edges of the scrolled regions. The fill register holds the data pattern to fill in the voids.
Left and Right ~otmdary Registers-These registers contain masks that determine the actual bit
positions of the edges of the scrolling region.
Logic Unit, Source Register, and Mask Registers-During bit map updates, the logic unit
performs logical operations between data in i:hesource register and incoming bit-map memory
data. The Mask land Mask 2 registers determine those bits within a 16-bit field that the logic unit
will modify. The {ogic unit performs 16 possible operations by selecting data in the foreground or
background register for output to the DIO < 15 ;00> lines.
Switchyard Logic-This logic transfers 1-,2-, or 4"bits that are received on the ID bus to the 16-bit
internal TWID bus. The number of bits received depends on the selection of full-, half-, or quarterresolution mode. The bits on the TWID bus are transferred to. the sQurce, fill, foreground, or
background register. The switchyard logic is used for Z-axis bit-map memory update operations.
ID I/O Holding Registers-These registers provide buffering between the 8-bit 10 bus and the 16bit internal TWID bus: I,
2-6
Confidential and Proprietary
-
78680
Edge :M.sk<~ The edge mask generator converts an 8-bit code into ~·16-bitmask, which·
is a window of variabIewidth and position for raster operations. It may be placed anywhere within
a 16~bit field.
Scron Constant Register-This register stores harrel shifter control data. The scroll constant
provides. shift magnitude and direction. One register bit determines the up or down S lines. Figure 4 shows the register load transfer sequence. The
IDbus instruction is a one-byte code and most instructions are followed bya 16·l)it data transfer or
subinstruction as listed:
Parameter
IN
SI
LB
HB
Meaning
Instruction
Shift constant
Data source-low byte
Data source-high byte
INST:
6
5
a
I I
15
SUBINST:
4
0
2
3
0
REGISTER ADDRESS
8
NONE REQUIRED
0
REGiStER DATA BITS <07:001
LOW BYTE:
HIGH BYTE:
PHI2A
PHI1A
PHI2B
PHil B
I
15
8
L._ _ _ _
R_E_G_IS_TE_R_D_A_T_A_B_IT_S_<1_5_:0_B)_ _ _- '
..fI'Nil
ri'NTlL-__________
fSi1l
rsi2l'--______
[L'BOl
fHiiOl
fLBilL-___
fHBi1..
Figure 4· 78680 Register Load Data Transfer Model
2·8
Confidential and Proprietary
-
PreliminA-q'"
18'80.
The video processor registers, type, and address assi.gnmtmts are listed in Thble·2. Threeoftha
registers are reserved,
.
Table 2 • 78680 Register Address Assignments
Address
(hexadecimal)
Register Name
o
Resolution mode
Bus width
1
2
3
4
5
6
7
8
9
A
B
C
D
E
S~t;Ql1 C.oIlS~l1t
Plane address
Logic function 0
Logic fupct;ion 1
Logic function 2
Logic function 3
Data mask 1
Data mask 2
13
Reserved
14
17
Control store RAM(CSR4}" .
Control store RAM (CSR5)
Control store RAM (CSR6)
Reserved
18
Reserved
16
Mode
Mode
Direct control
Direct control
Indirect control
Indirect control
Indirect control
Indirect control
Data
Data
Data
Data·
t)i.rect control
:.pirect control
Data
Data
Indirect control
Indirect control
Indirect control
7:0
7:0
7:0
7:0
15:0
15:0
1.5:0
10
11
12
15
1:0
3:2
6:0
5:0
.:$;0
Source
Fill
Leftscrollhoundary
Right scroll boundary
Background
Foreground
Control store RAM (CSROr
Control store RAM (CSRl)
Control store RAM (CSR2}z.·.
Ii
Type
Width
15:0
15:0
15:0
'13:0
'6:0
6:0
0:0
6:0
Indirect control
Indirect control
Indirect control
6:0
6:0
Th,~ dat~ and
c.ontrolreiPl\te.rsAthtol,l~rJ?(h~~(t~i~~~~.J6-bi!regis~Fts .ci1at ~]oad~d
by the ID bus load register commands. The mask arid source registers
loaded by data transfers
during the rasterop cycles. The source and fill registers ~an be lo~ded witha data~onstant to select a
solid eoiot-during Z·ans register loadoomman'ds:The least signffie:antbit of the word determmes
the left pixef and the most significanihit determines thenghtpix'eloo the display.'
direct
are
Confi~entialandPra.prietary
~-9
-
Resolution mo~The resolution mOGleregister controls the action of themaskbhs(mask 1, mask
2, and edge mask), the source register, the barrel shifter constant, and the Z-lV(is,€ommanci.Ihis
mode allows the 78680 video processor to respond as 1,2, or 4 planes. Figure 5 shows the format of
the register and Table .3 lists the functions of the register information. Because each video
processor can he programmed for a different resolution, the single barrel-shifter constant should he
truncated for low-resolution applications except when scrolling. Horizontal scrolling should be
used for the lowest-resolution plane to prevent errors caused by truncating to result in the scrolling
of an undesired region.
15
02
01
00
:
'~.--------------------------~~--------------~--~~---~
NOT USED
PLANE
Figure 5· 78680 Resolution Mode Register Format
Table .3 • 78680 Resolution Mode Register Description
Bit
Description
15:02
Not used.
01:00
Planes-Defines the planes of response as follows:
Bit 01
Bit 00 Plane
o
0
1
o
1
2
1
0
.3
114
i
Description
Full resolution
Half resolution
Undefined
Plane I-When plane 1 is specified, each bit in the mask registers and source register controls its
respective mask multiplexer or logic unit bit independently of the remaining bits. The plane
address can he programmed to any value ,and all barrel shifter constants are significant. Dlldng Z~x1S operations, the vid~processor receives or transmits thebtt that corresponds to itsI'lane
address.·
,
p!:i,ne2-Whenplane 2 is specified, the~en~ndodd mask or source bits are OR gated, anq the
results are used to control. the corresponding mask multiplexer or logic unit bits. The)east
significant bits of the barrel shifter constant is truncated so that the data will move only by a
multiple of 2 bits. During Z-axis operations, the video processor receives or transmits 1 bit that
corresponds to its plane address and the next most significant bit. The plane address bit must be
programmed to an even value.
2·10
Confidential and Proprietary
-
Planei4""""'"When plane4 is specified,.tne,4maskor SQt1tcd)its~OR gated and tlie.reswts·ate>llseQ,
to controltherorrespclnding. mask multiplexer or logia unit bits. The two least.significant,bltsQ£
thebarrelshifter'comtant'are .truncated so that thedatawillmo~only by. alllultiple-oi 4 bits.
During Z-axis operations, the video processor receives or transmits the four bits that ~QrresPQ~ to
its plane address and the next most significant hit. The plane address bit must be programmed to a
multiple of four.
Bus width"';;':The hus widthregistetselects the number of vidoobus bitsdependfug orithe rilltp~r
of pixek ~"\lired for .tbe. ~taY,~.]~-9~Qsi~P!'9qe§S9'~0ll!lct?~§.9"QxicI.!'!2 Crmat.andTable41ists thebitse1ections.aOO the
reduction in the videci'bus speed that resJ!llts.
04
15
03
02
01
00
P]
~------------------~--------------------~
NOT USED
BUS WIDTH NOT USED
Bit
Description
15:04
Not used.
03:02'
Bus width...... Selectn·henumhel'()£·vidf!obm.bits usedfol'.thedisplay as follows:
Bit 03
'0
o
1
1
01:00
Bit 02 Data:bu&\Vidth \1id~;~utVut
0
;A~bits
" ,.njits~yfourthalphapu1se
l~blts; .
. .<4 hits't'Wety':(i)theralpha puts~ .
0
undefined
1
l6-bits
4 nits every alpha pulse
-'>
Not used.
",,'~,:~',_
,:
"',',',;1"
" , ' ,',"\1
-
Saoll constant.......1'he Scroll constant register is double bU££e:red and is used to select the Je£for right .
horizontruscrollingand .vertica:fscrolling .operations .• The. data entered. in the.· register becomes
active on the following frame;Pigure 1shows the registerformat and 'Thole 5 lists the functions of .
the register information.
07
15
00
05
04
03
[2]
NOT USED
'--,.,.----...,
.........-.,.----'
X-SCROLL CONSTANT
VERTICAL SCROll D l R E C T I O N - - - - - - - - -.......
SCROLL E N A B L E - - - - - - - - - - - - - - - . . . !
HORIZONTAL SCROLL DIRECTION - - - - - - - - - - - -.......
Figure 7· 78680 Scroll Constant Register Format
Table 5 • 78680 ScroD Constant Register Description
Bit
Description
15:07
Not used.
06
Vertical scroll direction-SeleCts the direction fat the vertical scroll as follows.
Used to compensate for the asymmetries between the up and down scrolling
directions.
O=down, 1 = up, left, or right
05
04
Scroll enable:"""Set to enable the horizontal or vertical scrolling of the data accessed.
Cleared to disable scrolling and the writing of mfi:mory planes.
Horizontal scroll direction,-Control the direction of the X scroll constant specified
by bits 3:0 as follows: Cleared when using the Yscrol1 constant.
o=left, 1 =right
03:00
X-scroll constant-Selects the number of pixels per frame as follows:
For left scrolls: 0 value = 0 pixel and 15 = 15 pixels
For right scrolls: 0 value = 1 pixel and 15 = 16 pixels
Confidential and Proprietary
...
Plane address-The p~e address . e r deternP~the Z-axis operation. The plane addresses
must be different for each 78680 video processor. Addresses cannot overlap. A permanent plane
address is set if the scrolling process loads the fill register in Z-mode. If the fill register is loaded
individually by the scrolling process, then different update regions can have different plane address
arrangements. The register format is shown in Figure 8'and function of the register information is
described in Thble 6 . '
. .
.
06
15
04
: :
:
(3]
06
03
:
'---------N-o-iU-s-EO--------...;.······.~
Z-AxIS
00
BnAOORESS IN Z-AXIS
ilL6cK ADDRESS
Table 6· 78680 Plane A~uRegister Description
Bit
Description
15:06
Not used.
05,04
Z-access block ad<.\ress O.to 37""Defines the high-9rcier bits .of a 6-bit plane address
when using more than 16 plan~ or subplanes within a system.
03:00
Bit address in Z-m blocktho3-This address is set to the bit on which data will
be exchanged on the ID b~s'during Z-mode trarlsfers. Fot low resolution applications, this bit is the low-order' bit and must be a multiple of 2 everything that is a
multiple of 4 is a 11lultipleof2.
.
Logic unit function (O-})-Each of the'fotirlQgic unit function registers (0 through 3) include 8bits of information. The registers combine the word read from destination (D) during a readmodify-write cycle with the contents of .the Spurce (S)register. The results are used to select the
color of the foreground and background of the display. The format of the registers are shown in
Figure 9 and described in Table 7.
15
14.7J
I
14
I
,
13
I
12
I
11
10
I
I
09
I
08
I
07
I
06
I
05
I
04
I
03
I
02
I
01
I
I
......
,
\.
NOT USED
......
00
I
I
FUNCTION
ENABLE RESOLUTION MODE
SOURCE
MASK 2
MASK 1
Figure 9·78680 Logic Unit Function Registers (()"3) Fonnat
Confidential and Proprietary
---_._---------------_._----
-.
2-13
...
Table 7· 78680 Logic Unit Function (0·)Register DesCriptiOn·
."
Bit
Description
15:08
Not used.
07
Enable resolution mode-Cleared to enable the resol~tion mode for the source
register. Set to disable the resolution mode. When disabled, the bits are not
combined with the adjacent bits and are transferred through the logic unit
regardless of the resolution mode register selections.
06
Source::-Set to select the source register word and cleared to select the complement
of the source register word.
05
Mask 2-Cleared to use the content of programmable mask register 2 and set to use
the complement of mask register 2.
04
Mask 1-Cleared to use the content of programmable mask register 1 and set to use
the complement of mask register 1.
03:00
Function-Specifies the contents of the register as follows:
Bits
Function
02
01
00
03
zeros
0
0
0
0
not (D or S)
1
0
0
0
(not D) andS
0
1
0
notD
1
0
0
1
D and (not S)
0,
0
L
0
notS·
1
1
0
0
DXORS
1
0
0
1
not (D andS)
1
1
1
0
DandS
0
1
0
0
not (D XOR S)
1
1
0
0
1
0
S
1
0
(not D) or S
1
1
1
0
1
1
D
0
0
D or (not S)
1
0
1
1
0
DorS
1
1
.1
1
ones
1
1
1
°
2-14
Confidential and Proprietary
-
Mask land....k2....-Programrnable ma~ registers 1 ~p2 areu~ to ~ntt91 rhe1:tits .tha.t a~,
modify-write cycle willmqdi£y. Loaciing the dJltamaskregi1'lter 1 also loeiisdatamasl< registq 2
with.tbesameinfqrmation.The outpat of thesereg~ters and the edge iegister determi~e thebi~s
that will be modified by the 78680 video processor. Figure 1Q shows the format of the da~a mask,
registers.
15
: : :
[8.9}
...
:,
:1,: ". .
...,.
: < : ':
;
00
: :
i
READ· MODIFY WRITE BITS
Figure 10· 78680 Data Mask 1 and 2 Register Format
Source-The source register contains rheSQU(e,e,wotdfor thelogkunit thatiscombirted with the
destination information to select the £oregro~ndandbackground color for each pixel. The Z-mooe
address for this register is 00. The register format iSsOOwh in Fi.fure 11.
15
.:
[AJ
\
. .' Figure 11 • 78680 Source !RegistenrFormat
Fill-The fill register is double buffered and determines the fill area or blank space in memory that
is created when scrolling. Normally, the Z·axisJoad command is used tosclect a solid color. If the
register is loaded directly, all bits that correspond to the same subplane are set to the same value.
The data from the register becomes aCtivedurin~the frame that folloWs.
Because the scroll region boundaries can be contained within one word, the leftmost and rightmost
word can be programmed to any bit position. The scroll region boundaries of the 78690 video
control; hoWever, are limited to a multiple of£out·When thevide6oonttol is used;theooUridaries
must be selected with groups of 4 bits. Only the low 40r 8 bits of this register are significant when
using the 4- or 8-bit video bus widths, respectively. 'rheregister format issh6wO: in Figure 12.
00
15
: -:
[BJ
fILL AREA/BLANK SPACE
Figure 12 • 78680
Fill Register Format
~nfit;lential and. Propt:ierary;
2,15
-
Preliminary
'78680
Left and right scroD boundary-The left scroll boundary register defines the' bouhdary for the left
scron. All bits corresponding to the pixels that contain the left edge of the region are cleared, and all
other bits remain set. Normally, all bits from the pixel are cleared on the edge through the moSt
significant bit of the word. If both of the edges are within one word, only the bits from the left edge
through the right edge are cleared.
The right scroll boundary register defines the boundary for the right scroll. All bits are cleared from
the least significant bit (LSB) of the left edge through the bit corresponding to the rightmost pixel
that are to scroll within the word that contains the right edge of the region. All other bits remain
set. If the right boundary is between words (LSB not scrolled) or if both edges are within one word,
all bits are set. The format of the left and right scroll boundary register is shown in Figure 1.3.
15
IC.DI
I :
14
13
12
11
10
09
08
01
06
05
04
03
02
01
00
~---------------------------~---------~----------------~
CLEAR/SET alTS
Figure 13· 78680 Left and Right Scroll Boundary Register Format
BackgrOund and foteground-The background and foreground registers are loaded by the ill bus
register or Z-axis register load commands. The least significant bit of a word specifies the leftmost
pixel and the most significant bit specifies the rightmost pixel. The infotmation in these registers is
selected 1 bit at time by the logic unit that transfers the information to the mask multiplexer. The
multiplexer selects either this data or the previous destination data. The background register is
selected by a zero output and the foreground register by a one output from the logic unit. The
register format is shown in Figure 14.
15
[E.F]
I :
00
:
I
1
""",-M"'" me
LEFT-MOSTPIXEL---------------------------'-
Figure 14· 78680 Background and Foreground Register Format
2-16
Confidential and Proprietary
PreJ'unmary
.
Control Store RAM (CSRO.CSR6)-The control store RAM registers are CSRO throoghcSR6;;
Register CSR3 is rese!1l~' Duripg raster operations, these registers control the transfer o£rocessor and the cl~ta transfer toior from other ID hus qevi<;es. Dui:ing
each update memory cycle, the 78690 video control addresses~he contentso( theSe re~isters.
When bank J is selected by. the video control, CSRO controls the first read sou.rce, CSRI controls
the second read source, and CSR3 controls the read-modify-writedestination.Whenhank2 is
selected, CSR4· controls· the first read source, CSR5· controIsth,e seconcl read scrqrce'and CSR6
controls theread-modify-write destination. Figure 15 shows the
of the control store RAM
registers and Table 8Usts the function of the register informati'on. .
.
.
rermat
(10-12]
[14-16]
~~--~~--~~--~--~~--~~-r~~~~--~~~
__
__
__
____
L~~~
~~~~
~_~~~
~
~
···'.N.OTUSEO
\.T'; ~;~~~~LLO~"
INTERNAL\.OAP
BARREL SHIFTER DELAY CONTROL - - -_ _ _ _ _ _ _.....J
10 BUS OUTPUT --.....;........;..._.....;...;....._-"-_.....;._-,--,-~"'-':'-"-'.
Figure 15· 78680 Control Store RAM Registers(cSK'a.CSR6}FoWnat;
Bit
Description
15:06
Not used
05
Barrel shifter delay control-Set during
04
03:02
ID bus output-When a CSR is addressed during amemory relKicycle, thisbi~ ~ ,s;(!t
to, enable (ope pl~ne at a timeis ~o,wed)the transfer of data orfth:e ID. bus during a
. memorytead Cycle.
l ' ....
.
Internal Load-Select the register to receive the data t~~' theb~~l shifter
from the local memory plane following a memory read operation as follows:
Bits
03
01:00
afast;~d~ra!;teiope~~tion'tohOld.the
previous word in a delay register so the remairid:et of each souree Woratorrns the
next output word. This prevents excessive read operations tot~ soq:rue~~,j;1lis
bit controls delay registetClne £orCSRO and CSR:4 (fat source i} anddel~&ister·~
for CSRI and CSR5 (for source2).
. " ;. r·· . , · , . ~ .
0
02
0
0
1
1
1
0
1
Register
none
source
mask 1 and mask 2
mask 2
External load-Selects the register to receive the input data from the ID bus
following a memory read operation.
ConndentialandProprietary
...
Preliminary,
. Specifications
The meChanical,;elec~rical, and environmental characteri~tics .andsPecifitations for1:he 786~m
video process6r are "clesciibed in the following paragmphs. The test conditions for the electrical
values are as follows unless,specified
oth~rwise.
,'
.
,
\
-
,
' . '
• Power supply voltage (Von): 5.0V
Mechanical Configuration
The physical dimensions of the 78680 68-pin cerquad package are contained in Appendix E.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to'i:he device.
Exposure· to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device ..
• Power supply voltage (Voo ): -05 V to 5.25 V
• Input voltage appl,ied (VI.): -0.5 V to 6.0 V
• Output voltage applied (vou,): -0.5 V to 6.0 V
• Power dissipation (Po): 1.9 W at 100°C, 2.8 W at ooe
• Storage temperature: -55°C to 125°C
Reoonunended Operating Conditions
• Power supply voltage (V00): 5 V ± 5 %
• Temperature (T)) O°C to 100°C
• Typical operating voltage: 5.0 V
de Elec~ical Characteristics
,
The de electrical parameters of the 78680 video processor for the opera tine voltage and
tempe~ture ranges specified are listed in Table 9.
2-18
Confidential and Proprietary
Symbol
VIR
Test Condition
Requirements
Min.
MII;lC:.
v
2.0
High-level
input voltage
DIO < 15:00 > ,CS;SCROt,
ID<7:0> ,SYNC,
RDfWR,128/I6,
L1t::LK,ALPHA1,
PHIl,PHI2
0.8
Low-level
input voltage
DIO < 15:00> ,CS,SCROL,
ID<7:0> ,SYNC,
RD,rwR,128/I6,
Units
v
ITCL.K;AU'HM"
PHII,PHIl'
High-level'>
output voltage
(allpinsexcept 10, < 7:0> )
v~~.;;!o
.
IoH=-200~
ID<7:0>
Low-level 'Vbti ';"0 V
output voltage
DIO < 15:00> ,PE,
. VID<3:0~
ID<7:0>
101.=5.0 rnA
110
Active supply
current
Input leakage
current (highT
3.0
.\T))D=max
. . y...,"=Vo'u{ri:1ax.)
1nplltl~.kage
current tIow)
VOO=rnax.
V.. =OV
Short~circuit
YOD=rnax.
rnA
output current I
DIO < 1:i:OO > ,PE,
VID<3:0>
ID<7:0>
-15
High-Z state output
current
V.",=OA V
High-Z state output
current'
V""' =2.4 V
VUD=max.
VDD=max.
.... 140
30
3.0
rnA
-
Symbol
C...
Preliminary
Parameter
Requirements
Min.
Max.
Units
Input 'capacitance
4.7
pF
Output capacitance
6.6
pF
1These are computer simulated measurements and cannot be tested. In the test simulation, only
one output at a time may be short circuited to ground.
'The outputs include the driver current and input leakage current.
lCapacitance loading is for the output drivers and input receivers.
ac Electrical Characteristics
The ac timing parameters for the 78680 video processor are grouped according to major cycle
timing, minor cycle timing ID bus and video bus timing, and synchronization cycle timing. The
timing parameters in the tables are in microseconds unless listed otherwise.
Major Cycle Timing
Table 10 lists the symbols, definitions, and specifications for the major cycle timing shown in
Figure 16. A major cycle begins on the rising edge of the PH12 clock pulse and is equal to four PHI2
dock periods. A refresh read memory cycle has two major cycles-a read cycle and a screen refresh
transfer cycle for editing or scrolling. Every second major cycle must be a read cycle. The video
processor provides data to the display during the forward scan time of the screen refresh transfer
cycle. During this cycle, a refresh read memory cycle transfers data from bit-map memory to the
video hus.
Table 10·78680 Major Cycle Timing Parameters
Symbol
Definition
t CVCI
Period of LTCLK
.
Requirements (os)
Min.
Max.
54.5
Period of PHIl or PHI2
148
Period of major cycles
*
Propagation delay of LTCLK rising to valid data on
2-20
DIO<15:00>
32
Propagation delay of 128(i6 switching to an updated value
ofPE.
37
Confidential and Proprietary
-
Symbol
78680
Requirements (ns)
Min.
Max.
Definition
Hold time of RD,wR or 128/16 switching to the falling
edge of LTCLK. This parameter must be met relative to the
last falling edge of LTCLK in a major cycle.
10
Hold time of DIO< 15:00> or SCROLL to the ,falling
edge of LTCLK·
13
Propagation delay of RD/WRgoing high to a higtr.:ilnpec
dance on DIO < 15 :00 >
.3.0
Nonoverlap time, PHIl to PHI2
15.5
18
18
tPWH2
Pulse width high of PHIl or PHI2
55.5
Pulse widthlbw ofl,.1'CLK
.36.5
Setup time of RDJW:R switching to the falling ~ge of
LTCLK. This .parameter must be satisfied· relative· to the
first falling edge of LTCLK in a major cycle.
1.3
Setup time of 128{I6 rising to the rising edge of LfCLK.
This parruneter!l)ust be satisfied rela~iveto the.firstrising
edge of ~LK in a major Cycle ;lJidapplies only to ..
transitions between minor and major write Cycles (guaranteed by not exceeding t pDl).
6.5
Setup time of 010<15:00> orSCRQLL to\the falling
.edge of LTCLK
.
o
Setup time of RDjWR.or 128/J6switching to the first
falling edge of PHIl in any major cycle
26.5
Propagation delay of RDjWR going low to valid data on
DIO<15:00>
3.5
30
*Minimum t CYC } = 4 PHI2 cycles or 16 ALPHA cycles
Confic.lential andProprieta:ry
2-21
LTCLK "
PHil
·~·-·-·-·L
It::
.-:.
L._
I'HI2
MAJOR
CYCLE
1-1-+-----l--tCYC3--·------"-4~,.;j·
128/16
010
SCROll
PE
Figure 16·78680 Major Cycle Timing
ConfidenHaland Proprietary
-
Minor Cycle SignalTiming
Table 11 lists the specifications for the minor cycle events including a memory cycle shown in Figure
14. A memory cycle starts at thebeginning of a major cycle and must end by the beginning of the
next major cycle. Only. one memory cycle must be in progress ~t a time.
Symbol
Requirements (n~)
Definition
Min.
tm
t Ds
tHO}
t H04
t Hm
.'
Max.
Propagation delay of· PHI2 rising to . valid· . Thispatlu.titier applies dilly ~Z.axis
write operations.
63
Propag~tion ~ayQf Ii:> data~ttlP to f()llowing edg~Q;rthe .
second PHil in a ;minor cycle to valid' data on
DIO<15:00::>.
79.5
Hold timeofaii'asserted' C:s tQ···tJjefamlijfedg~ ofPHI2.
. 40'
Hold time of DIO< 15~OO> to the second falling edge of
PHI2 in a minor read"Cycle:
13
Hold time of 010 < 15:00> to the falling edge of RD/wit
0
Propagation delayo£ t~e ri~ingedge
DIO < 15:00 > riSing or falling." .
o
of 128{i6 t9
Setup time of an asserted CS to the falling edge of PHI2.
40
Setup time of DIO < 15:00 > to the falling edge of the
second PHI2 in a minor cycle.
50
Setup time of DIO< 15:00> to the falling edge of RD/
WR.
13
Propagation delay of RD;WR going low to valid data on
DIO< 15:00>.
ConfidentialmdPrt)prietary
3.5
38.5
30
Preliminary
78680'
1 - - - - - - - - - MAJOR CYCLE - - - - - - - - 1
I'HI2
PHil
RDIWR
1281 fij
cs
l;::;: tpD
---".Xl/Il/Ill,
DID
ID
Figure 17· 78680 MinorCycle Signal Timing
2-24
Confidential and Proprietary
-
Prelimibar):. . .
ID Bus and Vtdeo Bus $ignal Tuning
Table UUsts the specifications for the IDbus and video bus timing shown in F~re 18. A major
cycle begins on the rish1g edge of the PH12 dock pulse with 4 PH12 dock periods. PHIl and PliI2
must have the same "j)erlod and must not oyerlap. Ute alpha clock has a timing periodone~foorth of
, the PHI2 clock and has coinddentrisingedges."
R~ts(ns)
S,mhol
Min.
tn
Max.
Time delay to valid data on VID <3:0> is 10 ALPHA
cycles plus tD4 after start of present major cycle. (Not
'
testable).
Propagatiqn .,' dehty,of, PliP .• ~ising ta';vauaqd~~ ,on, '.
VIP<3:~> while ALPHAliShigJl. I : : . I"~ f , : , •
PerioooOt ALPHA.
tJ)4
36
Prol1ag~~nd~y Qtal~:~Qg't9~Yali4,4@~on
vui< 3:~ >~~raw?f.~~~~~~'?~~~'~qt,h;e
the bus width mode:
full page -= C)nce/tJ.:eI:M Slock, ,:
half page= once/tWo ALPHA clo~kS
one-fourth page once/four ALPHA clocks
=
Hold time of ID<7:0> to the falling edge of PHIl or
PHI2.
15.5
Propagation delay of PHIl or PHI2 going low to a High-Z
condition on ID < 7;0> .
3.0
tPWHl
Pulse width high of ALPHA.
18
tPWLl
Pulse width low of ALPHA.
18
tlU
Input rise time (fall time) ID < 7:0 >
tSU1
Setup time of ID < 7:0> to the falling edge of PHIl or
PHI2.
tHO'
tHZ1
tZH2
Propagation delay of PHIl or PHI2 rising to valid data on
ID<7:0>.
40
26.5
13
3.5
40
2·25
,-----,_.
~~-------.-'---------~--------,--,-.-.,
-
ALPHA
y"
Prelimin~r
i !,
dm1l777171O.0iilll7111177117ik
,II--'----.
Figure 18· 78680 ID Bus and Video Bus Signal Ttming
2-26
Confidential and Proprietary
1/4 PAGE
",mM
S~,Cyde,T'111ling
Synchronizatioo<>CCUrSonce perfwneduring theverticalretraceperiod. When the SYNCsigtiai is
asserted, all internal clocks halt in at =0 + state. The video processor suspends all data processing
and,resets the counters that are used to transfer data out to. the video bus an~I Qut of and into the ID
and data bus. The ll'CLK has eight time periods within a major ¢yele. These periods can occur
witbinthecycle to aCComttioaate'differenftypes ofIMmoties.Ta"le 13 lists the syricllroruzatien
timing parameters shown in Figure 19.
'
R~ent5(ns)
SyDiboI
Max.
Min.
tH
Use th~ dsillg ~geof PEII2 as the ipajor C§cleooundiiry
except a£te¥:async~e. (Not·testable). '
The number ef A;tPHA cycles tha1: must elapse before
PfU2'gQeslow;f~r P'l~
fJrst ~e!'1fte(a.1syNecycleisl,
5,
,
9, orB:",' ' , " , ' "
tcVC3
Period of majer cycles. (Not testable).
*
302
tPWH4
Skew between PHI2 falling and ALPHA falling.
tsus
tsu.t
±5.0
Setup rime ef SYNC going low to the first falling edge ef
ALPHA.
302
Setup time of U'CLK falling to the rising edge of PHIZ.
!:,26~~
':
'*, '", ,,~1
tin order for the t)i"specjfic~tiiOn('n1blelZ1toW,~d~dal:ijfJ'lijid:t~~loadedint~ t~in:ternal
,FIFO buffers.' TbetdQl:'ei 'th~fir$,~£~ ~.LTCLJ( ,a114 it$!l~at~dl1tadlU'iaga, IlllitjQl'-rea(i
cycle must precede the third rising edge ef PHIl.
*Minim~~Y(J}C'j'4 PHI2 cyc~sorl6:ALfJil\ ~fll~,
2-27
-
~~~~:
PreIimiaary
_.....I'""II....=======tc_YC_3:::::::. .o.l:.J..I,....: : : : : : : : : : : : : : :.....
:tC. .;Y""'C_3'~'.:':::::::::=::::;'~I--._
SYNC
LTCLK
PHil
PHI2
ALPHA
Figure 19· 78680 Synchronization Cycle Timing
. Interfacing Techniques
The'video processor comrriUhicates with the' video subsystem using. the three TTL-compatible
mterfaces shown in Figure 3'-the system interface, the bit-map interface, and the display
interface.
The system interface lines consist of the chip select (CS), the system clocks, and an 8-bit,
bidirectional instruction/data bus. The system interface connects to the address processor memory
planes and other memory planes.
The bit-map interface includes the 16-bit bidirectional data bus DIO < 15:00> and the LTCLK,
128, RD, SCR, OL, PE, PHIl, and PHI2 signals that control data flow on the bus. The bit-map
interface connects to the bit-map memory planes.
The display interface includes the video bus and the signals that control it. The video bus
VID < 3:0 > connects to the display circuits. The control signals include the ALPHA clock pulses
and the PHIl and PHI2 system clocks pulses. This bus is used during screen refresh cycles.
The instruction/data (ID) bus is used to transfer information between the video processor and
controllers. It is used to load and read registers and to execute direct or indirect instructions.
2-28
Confidential and Proprietary
-
Preliminary
78680
Interface Conn~tions
The following cixcuit and connections are recommended for the proper operation of the 78680
video processor.
Power-The 78680 video processor operates with a 5 Vdc power supply. Ten of the chip pins
connect to VDD and one connects to VS8 ' No special filtering is required. The 5 Vdc connects to the
VDD pins and the power supply ground connects to Vss. Pin 61 (V1m) is the voltage generator output
and must be connected to the pin 60 (cavity) which is the substrate.
Powerup latc:h-The video processor includes a cixcuit to ensure that the ID bus is in a highimpedence state during the powerup sequence. A latch is set during the powerup sequence to force
the ID bus to this state. The deassertion of the CS signal clears the latch.
ID bus lines-Connecting a 50-pF capacitor to ground on each ID bus line compensates for
component variations in the interface design. Multiplane single-module systems may not require
these capacitors. However, the etch capacitance to ground and to other signals should be evaluated.
The noise margin should be limited to 02 V to 0.3 V. The total ID bus load capacitance should be
less than 400 pF.
Confidential and Proprietary
2-29
• Programmable display resolution
• Programmable screen synchronous interrupt
• Displays up to 1024 by 864 pixels at 60 Hz noninterlaced
• Supports video memory add~s:spa~e
~
~
~
~
10 All. BIT MAP
MEMORIES
Figure 1 • 78690 Video Control Block Diagram
Confidential and Proprietary
2-31
Preliminary
·78690
• Pin and Signal Description
This section provides a brief description of the input and output signals and power and ground
connections for the 78690 Video Control 84-pincerquad package. The pin assignments are
identified in Figure 2 and the signals are summarized in Table 1.
DAT01
PHI 1
OATOo
ADD5
77
ADD4
78
ADD3
79
ADD2
80
AD01
81
AD DO
82
!lS
83
AS
84
,------ - - --,
I
I
I
I
I
I
I
I
78690 VIDEO
CONTROL (ADDER)
CHIP
I
I
I
I.
I
I
I
I
I
TOP VIEW
I
I
(CAVITY DOWN)
I
IL ____________ ...JI
AD
iNTf
Vdd
GND
VSVNC
CMPSYN
BLANK
52
MAD10
51
MAD09
50
MAD08
49
MAD07
48
MADOO
47
MAD05
46
MAD04
45
MAD03
44
MAD02
43
MADOl
42
GND
41
Vdd
40
MADOO
39
SCROL
38
37
FORCE
S\iNCR
WE3
SYNC
WE2
iNT
WE1
REO
IOcn
ID
o
ID
ID
2
3
Figure 2· 78690 Pin Assignments
2-32
128
MAD
Confidential and Proprietary
SPARE WED
-
Table 1-18690 Pin ami Sign'aI S1lDlIftary
1
S~,.
RD
input
Read-Indicates a l'elld or write procaSOl' bus cycle.
2
INIT
input
lniti~-=Initializes thevideo.controland processOrbUs.
10
INT
output
11
rum
Qutput
57-60
63-66
69-76
DAT < 15:00>
input/output
77-82
ADD<5:0>
input
Pin
'. I~rupt-Initiateg.aprocessor interrupt request.
"
-""
';
"
",<.,,'-,
,
-.:.
Request......lndicatesa..DMA..
.
access reques. t.
~"
'.'
'
·Data.<15:00>~DatabtlSlines
Address
'
< 5:0 > -Address bus lines
P.tastrobe.......:Enablesdata transfers on the in~
or external data bus .. ,
.
83
84
AS
input
AddtY!ss strobe-Initiates an interface transfer,
.5
VSYNC
output
Vertical synchronize-A video vertical synchronization signal.
6
CMPSYN
output
7
BLANK
. ,output
8
SYNER
output
Composite synchronize-.A video composite hori-
zon~ sYttchn.1tli~~n sigtUil.;."
'
Syndltoni~ .teil1i'($t:-A'sySiems~on
'cYQlcreqiIe$t;
9
SYNC
12
IDCTL
14-16,
18-22
ID<7;(»
25
CAS
' .. COllUM address' sttobe,.....BiIi:-m.mem()lY'~
clook,~.
26
27
PHI3
PHI4
inPQ.t
28
ADS
jnput,
29,30
Spare
32-35
WE<3:0>
output
Write enable~Eftable$ the writing of thebit-~ap
memory;'
36
MRD
output
Map read-Specifies a read or write cycJeo(thebit-
maprm:mory.
37
128~
output
128/16-Indicare:s a major or minorbit-inap memo
orycyde.
Confident!a1 and Proprietary
2-33
_0
····1&.90
Pin
Signal
38
FORCE
output
Fort;e.:...-Enables:adown scrolling writ!! cyde.
39
SCROL
output
Scroll-Selects refrf;sh read memory CYdes during
scrolling .
40,
MAD < 10:00>
outputs
. Memory address < 10:00> -Rowand column
address Hnes for bit-map memories.
53
PHIl
input
Phase input 1-Phase 1 clock signal.
55
PHI2
input
Phase input 2-Phase 2 clock signal.
31
VSB
43-52
Not used.
3,62,67 VOD
17,23,
41,54
4,61,68
13,24,
42,56
GND
input
Voltage-Power supply 5 Vdc.
input
Ground-Ground reference for signals and voltage.
Processor Interface Signals
ReadjWrite (RD)-This signal informs the video control that the processor access is a read or a
write cycle. The processor access is initiated by the assertion of the AS signal.
InitiaJize (iNIT)-This signal caUses the video control to be initialized to a known state. The
processor interface becomes inactive forcing theID bus drivers to a high-impedance state until the
SYNC signal is asserted.
n~t
Direct Memory .Access Request (REQ)-This signal provides a hardware flag for the bits that are
eria:blel:litl the status registet.1'he enabled bits are selected by the request register.
Interrupt (00)-This signal provides a hardware flag for the bits .that are enabled in the status
register. The enabled bits are selected by the interrupt register.
Data (DAT <15:00»-"These are bidirectional,. parallel data lines, through which the video
control interfaces to the processor. During a reacloperation, the bus master enables the ITS input
and the DAT < 15 ;00> information drives the external data bus. During a write operation when
the DS signal is asserted, the DAT < 15:00> signals drive the internal data bus.
Address (ADD < ;:0> )-These inputs select the video control register to be accessed.
Data StJObe (DS).....;;Duriilga register read cyCle, this signal transfers data to the external data bus.
During a regist~rwrite cycle, it transfersda,ta to the internal data bus.
,~ss ,Stro~
0S)-
This signal initiates a video control· interfacetransfer. It. performs a chip
Sclect function and latches the information into the addressed register.
Monitor Timing Signals
Vertical Syncluonization (VSYNC)- This signal in separate vertical SYNC signal for displays that
. donot~e a~mpos,ite SYNC signal.
Vtdeo Composite or Horizontal Syn~tion (CMPSYN)-This signal can be programmed as
either composite SYNC or horizontal SYNC signal.
2-34
Confidentlal and Proprietary
-
78690
Video Composite Blank Signal (BLANK)-The video control uses this signal to blankthemonit()l.
System Sync:lu:onUation Request. (SYNCR)~ The video control asserts this signal to request. the
external clock generation logic togenerate a SYNC cycle. The clock logic asserts the SYNC s~al
and stops the clocks fo;r a predetermirl~ number of serial cycles.
System Sytlehronization (SYNC),..,.,.Theexternalcloekgeneration logic sends this signal to the
video control and video processor to syq.chronize the videosllbsystenh This signal coru:rols all of
the timing generators on the chips.
In Interfaee Signals .
.
.....
..... '.' .. .
.
Chip Select Control (IOCTI.)-The ID bus requires t'o/O chii'.~reWstel'stoallo\V,ind~n<1ent
selection of a video controlfor ID transactions. Whc,n theIDCn.:·~isnalisalow lweI, itselects the
update chip selection tegistet Whenthls sIgnal i8,11 high !~~l.'it seleets·thescroll chip select
register.
.' '.
.
'.
..
..
Instruction/Data Bus (ID < 7:0> )-This bus is a cOtlUllunkations pat,h betwee~ the vide9 control
and video processor.
.
.
.
Memory Interfaee Signals
Address Disable (ADS)-This signal is normally a low level: to allow the video control to drive the
memory interface. When this signal is high level, all update activity h; stopped and all refresh and
scroll activities continue. All update cycles on the bus are no operations (NOP) .16-bit read cycles.
Bitmap Memory Write Enable (WE < 3:0> )-These sign~s ena.ble writing to groups of four bit
map memories.
Memory Read{Write (MRD).....This signalindlCatesareador a write cycle. A high level indicates a
read cycle and a low level indicates a write cycle.
128/16 Bit-map Memory AccesS Width...- This slgnalin~1'hese lines provide the row and column addresses
for the bit-mapinemories that are multiplexed from the .video control. An address is available for
each column address strobe (CAs) pulse.
.
Clock Signals
.
Phase Input t to Phase Input 4 (PHIl to PHI4)-These clock inputs provide the timing control for
all operations of the video control.
.
Column Address Strobe (CAS)-This input is a bit-map memory access strobe,
Power and Ground ConnectiOns
Power Supply (VDo)-Supplies 5-Vdc power to the 78690 video control.
Ground (GND)-Ground reference for all internal logic except for the output drivers.
Confiderttialand Proprietary
2-35
.all.
78690
Preliminary
• Architecture Summary
A typical bit-map prOcessor system, shown in· Figure 3, consists of a local processor or remote
processor that performs DMA operations, the 78690 video control, the 78680 video processor, bitmap memory planes, the color map and shift register logic, and high-speed timing logic. The video
control performs the functions that are common to memory planes which includes local processor
interactiort, raster operation computations, scan timing, system status generation, and memory
address generation for screen refresh and updates.
The video control communicates with the microprocessor through the microprocessor bus and
with the memory through a display memory address bus. It communicates with the video
processors through the instruction/data bus.
The video control contains 64 registers that can be directly or indirectly loaded by the local
processor to control the scan timing, refresh and scrolling operations. The registers are used to
generate interrupts, report status, and to read and write data in the bit-map memory. They also
communicate with the instruction/data bus.
PROCESSOR
AODRESS/DATA BUS
78690
vIDeo CONTROL CHIP
lADDER)
MONITOR
UP TO 24
PLANES
Figure 3· 78690 Typical Bit-map Graphics System Configuration
2-36
Confidential and Proprietary
The 78690 videocoritrol communicates with the processor through the dataaiJd address bus, with
the bit map memory through the' bit-map memory address bus, and with the 78680 video
processors through the instruction/data (In) bus.
'
The localerocessor sends the co~ds to the video ~ontrol to update ~emory" The video control
performsfUrictions such as local procesSor in1=eta~0n."laster comt'tltad?noee:ri~ions, 'scan timing,
system status generation, and memory addres$ generation to refreSh afidupdate tbedis!:,lay, that
are common to all memory planes. , "
'
The displaymemor}r ~~ssblls:tJ:an,sfers th~aO#lref1Sesto
refresh memory, and to scioll theiruormatiori bn#dispiay.
Ilpd~tethedispt~,to alltomatica1ly
. . "',
,,'
"
The instf\lCQon/data bus loads theregisters~the'{id~ proc~ss~r:with~~r destinati()n, barrel
shift constant, and edgemaskdata. Data isalso':exc9a11iledt~';lgh, tHis b1lS, ~~ aScreen
update, the new infor~tion is tmn#erredto th~ videQ ,PtBCess()):. putitlg a sqi,irce 0pen1tiofl? the
video control Sends acDdesPeci£ymgs~~l.?r ~e'? an~:fabaftclshiftCo~taflt tpatshllisthe
source data to align with the destination;-nuring a destliiationo~~io,n,thfvideO confrolse~sa
destination code and an edge mask instructffig the video processertnat sPecffies'whidibits ofth.e
data bus are to be written.
Hardware Description
The followIDg parilgraphs provide a brief description of the tnajOr.ftardware. blm:k,fui1dions oithe
video control. Refer to:Eigure 1.
~Interfaee-'.This logkreCeives the '~lU;ameiersand Co11Utlands from the,local, processor.
The processor iiltenacehandles registetaccesses and controls tirxlmg and'aUti~ bus $ignals
to allow the video control to act as a bus slave to the local processor otDMA deVice.
:oj Control-The IDcontrol selectsttlechipselectregist~t1u\b:fetetminewhicb video processors
will updati the hit-map memory ahd which oneswiB. perrorirt Sdlj1lirig.The:\1pdate process uses
the ill data first-in/first-out (FIFO) buffer and the scroll prb'~sS i:lses" the Insilnd lCS registerS;
J))DaiaFQlO-Dtiring the bit"mapmemoryu~¥'proce!!s;thi~videocontrol uses the ID fhta
FIFO buffer to transfer data to and from the bitmapithroughtheVideo pOOcessot:It isalstiused to
load the video prpces$Or registers.
X and Y Sam Logic-The X-scan circuits generate the X components for the monitor display, the
system synchrOpization ~gilals, theref~Sh IUx{$Cwll ~s$es~~J4<:SCl:On e~able $i~,The
Y:scan circuits generate theYromponents for
monitor displa~~Ystem sy-nchroruzation signal,
refresh and scroll addresses, and determitiesthe~ve times fOr~sfto1img.
Sync Con11'Ol~This
controls horizontal arid vettical·:;ynchr6!lizatron.
Serial Memories-The ~rial memory, c;ontaitls heMs, the con;unands and data' for update
me
airouir
operations.
Main BNsenham ContllOl"":This logil;. CQ~tro}$.Ul,eisePallogicthat coroPut~l;lthe~s.§eCluence
for raster operations; It receives eommandand mode wormation from the serial memories and
generates status bits and control £lags for the niain ,control andaddresscollecti~ subSections. A
raster operation copiesa contiguous section ofbit"~ memOry (source) into adtt£erent locationof
bit-map memory (destination). The modes of raster operations supported are normal raster
operations (rasterops), linear patterns, and polygon fill.
Source
Source Gene1'8tor-The,source generator produces a sequence of addressesror .the,
data
dtiring raSter operations. In normal mode, It"traces arectangWitr section of bit"mapme~ory.I~
linear pattern mode, it loops on a small rectangle to create' arepeitiog pattern ttntil the destinaticiii
completes its operation. In fill mode, it computes the address sequence for one edge of a polygon.
'Confidential and Proprietary
2-37
78690
Destination~l.'!ltot~ The destinationo;generator l?roduc~ asequefl~e of adclressedor the
destinatiqn dataduriQg raster opt;.t:ation~. Ip. the normal and line~ pattern modes,.it traces a
parallelogram by drawing a sequence of arbitrarily oriented parallel lines as the origins follow a
traiectorydefined byanotherarbitrarily oriented line. In fill mode, one part of the generator
computes the address sequence of the second edge of the polygon and another part of the generator
.
fills the polygon by dra~ lines between the two polygon edges.
Source 2 Logic-This logic generates a second sequence of addresses for source. data. The video
processors may access data from two sources and combine it with the destination data, Source 2
data is generated by addlng an offset value to the destination address. It can be used to generate a
tile pattern that repeats the modulo of ariy power of 2 between 16 and 512.
Index Logic-The index logic permits an offset value to be added to the source.and destination
addresses to support the scrolling process. Scrolling is performed by physically moving data in the
bit-map memory. When data is moved, the index may be changed so that the processor is not
required to recompute its display list. The index logic allows data to be written into the hit-map
memory during the scrolling process.
.
Clipping Logic-The clipping logic prevents the writing to the bit-map memory locations beyond a
predefined rectangular window. Status is generated in the main control section to inform the host
processor of the clipping action.
B81'1'el Shift Constant/EdgeMask Logic-This logic computes the data required by the video
processors. The barrel shift constant indicates to the video processor the amount of the source data
shift necessary to align it with the destination data. Each source operation generates . a barrel shift
constant. The edge mask logic defines the left and right edges of the destination. Each destination
.
operation generates an edge mask.
Ad~ss FIFO Buffer-This buffer receives the ~riallogic signals for addresses and flags . for
destination update;.vrites, source 1 update re~s, and source 2 update reads. The FIFO multiplexes
thisclata so it is available when needed.
Address Control-This logic controls the sequence of memory cycles on the. memory interface
including the refresh (read), scroll (write), and update (read-modify-writel cycles.
Write Enable Control-This logic controls the interface to the bit. map memories. The write
enable logic generates the following:
• The timing signals to pass addresses from the RAS/CAS mllltiplexer to the memories
• The low 3 bits of the CAS IIddresses during major cycles
• The write enable signals for the memories during both scroll and update read-modify-write
memory operations
• The SCROL, MRD and 128/16 signal for memory
• The memory interface clocks and timing from the CAS docks
RAS/CAS Multiplexer......'This logic combines the X and Y address togenerate the row and column
address for the hit-map memories. This multiplexer also assures the refreshing of the :bit-map
memories.
~ FlUlCtions
..
....
When>the Joca,J processor .or DMAcontroller loads the cOm.J.p.and register, the video control
~sone of the following co.iUma.qds:
2-38
. Confidential and Proprietaty
-
78690
InstruCtion/Data-The inst,t:Uction/data commands are used.t.o configure and control the video
processor.
Rastet-The raster commands are used to initiate raster operations as defined by the information
previously IO'aded into registers.
Processor/Bit.map'1ilu1sfer-These. cO'I1l1nands are:rised to' totransfefdatabetween the local
'
processor or DMA controner and the video cOhtrol:
Cancel-The cancel" command terminates an
operation status registers.'
..' '.
uPAA~·. operation ih progress. and' clears all raster
.
• .
,
Modes of Operation
The 78690 video control operates in ,the fonowing,modes.
N~~ode'"':"",Thls . mpde i§ use4 for.:o'Iste,t oP~operates.in slow tn9de,
. • '. . ,'.
,,--,
-
'
-
<,
-"
,'".
~,
~
.".""
-,
-
-,-,
~
',}
___
1
..
."
Fill Mode-This~e.,is used.1X;l.,£Jll an..at'Eta be~n twO'~s .. I?o~the sloVi( source and
destination create.~veCto~s,The. fast destination draw:s;~th,erhQrim!1tal or vertical lines
between the twoJC~vecto'!i,;lIp.weyel.j~yectol;Sl ~y inteJ:'se;ct~cb.otl;let,'. ~additis>n, the ~a
to a baseline may~ ~illed' sod.1a,t O'need~is,a fixeclYvalue,.ot:~ {~,~va,l!J~~ The vi.deO' control
uses fast m9de £otltorizontaly~rsanqs1owmodeJor vertical vectors and the mO'de$ClU1 be used
together with the (i1l\{Uqde'. , ' , . "
,
ide Mode:.-ThlsmO'de is usedto fill intersecting polygons so thafthe texture ofeach,is continuous
across the intersection arid applies to soUrCe 2 orily.
Register Descriptions
..... '. .'. ."
. ' .'
, .' . .
The 78690 video control contai~ ~4 reiis4rrs that .;:an commuriica~e~th d,}eprocessor datal
address bus. Three of these registe);sare~e,t:Ved fOl:test purposes .• Theregis~s maybe load~
directly or indirectly through the adtlressoounter (register 0) using an autoJ.n.crement1l}Ode. Thest!';
registers contain the parameters £9rsition 0[1 the sc~n with'O', 0 beingJPeupper-le£t
comer with Xincreasing to the right andY increasiflgdownward.
'
• A DMA controller may load the registers so common combinations are adjacent thereby requiring
a minimum of address register loads.
Confidential and Propl'ietary
2-39
n..._1!_!~
__
. ;rnwuunary
'Dlbte2 • 78690 Register Address Assignments
Address· Name
Width Function
Control Registers
Address counter (ADCT)
1
Request enable (REQ)
2
Interrupt enable (INT)
3
Status (STAT)
4
Reserved for test
15:00
13:00
13:00
13;00
DMA device interface to registers
DMA status flag request enable
Interrupt enable for status flags
Video system status
Spare
Reserved for test
ID data (IDD)
Command (CMD)
15:00
14:00
ID bus data
Mode (MDE)
Command (CMD)
07:00
14:00
o
5
6
7
8
9
A
Command register (same as command register
location A)
Sets varioUs raster operation execution modes
Command register
Scroll Registers
B
C
D
E
F
10
II
12
13
14
Reserved for test
ID scroll data (IDS)
1D scroll command (ICS)
Scroll X Minimum (PXMN)
Scroll X Maximum (PXMX)
Scroll Y Minimum (PYMN)
Scroll Y Maximum (PYMX)
Pause (PS)
Yoffset (PYOF)
Y scroll constant (PYSC)
Update Control Registers
15
Pending X index (PXI)
16
Pending Y index (PYI)
17
NewXindex (NXI)
18
New Yindex (NYI)
19
Old X index (OXI)
lA
Old Y index (OYI)
1B
Clip X minimum (CXMN)
lC
Clip X maximum (CXMX)
ID
Clip Y minimum (CYMN)
1E
Clip Y maximum (CYMX)
IF
Spare
2-40
15:00
15:00
13:00
13:00
13:00
ID bus scroll data
ID command register for scroll process
13:00
10:00
13:00
14:00
Left boundary of scroll region
Right boundary of scroll region
Top boundary Of scroll region
Bottom boundary of scroll region
Screen coordinate to set pause status
Screen to memory coordinate offset
Vertical scroll distance in one frame
13:00
13:00
13:00
13:00
13:00
13:00
13:00
13:00
13;00
13:00
Pending X index
Pending Y index
New X index
NewYindex
Old X index
OldY index
Left clipping boundary
Right clipping boundary
Top clipping boundary
Bottom clipping boundary
Confidential and Proprietary
-
78690
Address· Name
Width Function
RasterCon~l~
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
Fast source 1 dX (fSDX)
Slow source 1 dY (SSDy)
Source 1 X origin (SXO)
Source 1 Yorigin (SYO)
Destination X origin (DXO)
Destination Y origin (DYO)
Fast destination dX (FDX)
Fast destination dY (FDy)
Slow destination dX (SDX)
Slow destination dY (SDY)
Fast scale (FSC)
Slow scale (SSC)
Source 2 X origin (S2XO)
Source2Yorigin (S2YO)
Source 2 Height and
Width (S2HW)
Error 1 (ERRl)
Error 2 (ERR2)
13:00
13:00
13:00
13:00
13:00
13:00
13:00
13;00
13:00
13:00
13:00
13:00
13:00
13:00
07:00
Fast delta X for source 1
Slow delta Y for source 1
X coordinate of source 1
Y coordinate of source 1
X coor.vJin~te. of destination origin
Y coordinate of destination origin
X component of f.astdestination vector
Ycomponeni of fast destination vector
X component of slow destination vector
Y component of slow destination vector
Fast vector scale factor
Slow vector scale factor
Xeoordfuate of source 2
Y cOQ1'diP$!.~of SQurce 2
Size of source 2 tile
13:00
13:00
Error adjust for slow destination
Error adjust for fast destination
13:00
13:00
13:00
13:00
08:00
Vertical timing
Vertical timing
Vertical tilllfug
Vertical timing
Cycles, bus width, number of refresh rows
Widthlimlt on refresh
Height limit qn refresh
X sean colint 0
X scan count 1
8cre@ Fo.tn.18t CcmtrPl &gi$ters
31
35
Y scan count 0 (YCTO)
Y scan count l(YCTl)
Y scan coUnt 2 (yCT2)
Y scan count 3 (YCT3)
X scan configuration (XCONj
36
37
X limit (XL)
Y limit (YL)
38
39
3A
X scan cOunt 0 (XCTO)
X scan count 1 (XCTl)
X scan count 2 (X:CT2)
X scan count 3 (XCT3)
X scan count 4 (XCT4)
X scan count 5 (XCT5)
X scan count 6 (XCT6)
Sync phase (SYNP)
32
33
34
3B
3C
3D
3E
3F
13:00
13:00
15:00
15:00
15:00 . X SC~lfi coUnt 2
15:00 X scan count 3
15:00 X scan count 4
15:00 X scan Count 5
15:00 X scan count 6
14:50 Sync phase adjustment
"Hexadecimal notation
Confidential and Proprietary
2-41
-
Preliminary
78690
Status and Control Registers
The video control logic contains status and control registers used to initiate requests and interrupts,
report status, select modes of operation, and initiate command functions. These registers are described in the following paragraphs. The status and control register formats are shown in Figure 4.
15
[0]
[1
5
6
14
;
..".
DATA (BIT15
DATAFUNCTION
=0)
0
...
.......
ADDRESS (BIT15
= 1)
ADDRESS COUNTER
14
15
[11
0
13
I :
I
........-
~
NOT USED
I
REQUEST ENABLE STATUS
REQUEST ENABLE REGISTER
1&
12J
I
14
:
13
00
....,
~
NOT USED
INTERRUPT ENABLE STATUS
INTERRUPT ENABLE REGISTER
14
15
13)
I
13
12
11
10
09
08
,
07
06
05
04
I
"-----.---'
NOT USED
vERTICAl BLANK
c LIPPING WINDOW DETECT
cLIP AT RIGHT
BOUNDARY-
c UP AT LEFT BOUNDARY
C LIP AT BOTTOM BOUNDARY
C LIP AT TOP BOUNDARY
D SCROLL DATA READ
D DATA TRANSMIT READY
I D DATA RECEIVE READY
A DDRESS OUTPUT COMPLETE
RASTEROP COMPLETE
RASTEROP INITIALIZATION COMPLETE
S CROLL SERVICE
PAUSE COMPLETE
STATUS REGISTER
Figure 4· 78690 Status and Control Register Formats
2-42
Confidential and Proprietary
03
02
01
00
I
15
I7J
1:
10 BUS DATA
10 DATA REGISTER
15
10
13
14
00.
08
0.7
IBI
~------~~------~--~--~
.10 COMMAND
~
SE;LECT FUNCTION
TE;ST
RESE;RVED
SOURCE 2 ENABLE
SOURCE 1. ENABl.e - - - - '
DESTINATION ENABLE _ _..,,-_...J
COMMAND REGISTER
15
lSJ
I
~
...
I
I
I
I
•
I
.L
.......
..L
.
I
•
.1
I
1
~
M9PE
N,OTI)SEO
PEN UP/DOWN
DESTINATION. INDEX ENABl£IOISABLE
SOURCE 1 INDEX ENAIll.ElptSAalE
HOLE FILl. ENABlElDISABLE
.
FilL NORMALlf.lASEliNE
FilL AREA SCAN XlY AXIS
.
MODE REGISTER
15
::
(SAMES AS (S} COMMAND REGISTER,
COMMAND REGISTER
Figure 4· 78690 Status and Control Register Formats (Continued)
Confidential and Proprietary
00
...
Preliminary
··78690
[0] Address Counter-The address counter (ADCT) provides indirect access to the video control
registers and isused with standard DMA controllers. The register information 1S described in Table 3.
Table 3 • 78690 Address Counter Description
Bit
Description
15
Data Function-During write operations, this bit is set to cause the following:
Bit 15 = 0: The data in the counter is transferred to the register selected by the counter and
the counter is incremented.
Bit 15 = 1: The low 6 bits of data replace the original contents of the address counter with
the following exception. If the address counter is pointing to either the ID data register
(IDD) or to the ID scroll data register (IDS), the most significant bit of the data is ignored
and all 16 bits are loaded into the appropriate ID register and the counter is incremented.
When reading the address counter, the register that the contents of the address counter
points to is accessed and the counter is incremented. The INIT signal clears the counter.
14:00
Data/Address-Contains data in bits 14:00 if data function bit 15=0 and address
information in bits 06:00 if data function bit 15 = L
[1] Request Enable Register-The request enable (REQ) register is used to select any of the
corresponding 13 bits of the status register to be enabled to assert a request. When a status
condition sets a bit in the status register, a request will be generated if the corresponding request
enable bit in this register is also set. The DMA controller normally sets a request bit one at a time as
it waits for the specific event to occur. The register information is defined in Table 4.
Table 4 • 78690 Request Enable Register Description
Bit
~pDon
15:14
Not used
13 :00
Request enable-Each bit corresponds to a bit in the status register. When a request bit is
set, a request (REQ) signal is generated when the corresponding bit in the status register is
set. The request register allows a DMA controller to control data and request status.
2-44
Confidential and Proprietary
-
[2] Interrupt Enable Register-The interrupt (INl'}~ register is used by the local processor to
select any of the corresponding 13 bits of the status register. When a status condition sets a bit in
the status regiSter, linihterrupt will be generated if the corresponding interrupt enable bit in this
register is also set. The register informarlonis defined in Table 5.
Bit
15:14
Not used
13:00
Interrupt enable (~N1') ___ EE!':h bit ~~pon~ t9.abit in.~. stams register. When a
interrupt enable bit is set, an J.q~pt:request.(IN'n ~i~ is generated when the
correspo~ .statP$condirlqu c~p~s the status bit, t;o be set .. The interrupt enable
register provides. the loqd P~of,;with interruptcon~:~:--i.-:'
--1-:'. ..--'. ;-.. . . . .,.,:--'. . . . :-.I..:-...--l;..,..-....
I
:L-.-..I;
~------------------------------~----------------~
NOT USED
DELTA XVALUE
SLOW.SOURCE 1 DElTAX REG.ISTER;·
15
14
00
13
[22J
~.~~~~~~~~ _ _~~~~~~~~~~~~~~~~~ _ _- - J
NOT USED
X-COORD1NATIO VALIJ£
SOURCE 1 X ORIGIN REGISTER
15
14
13
12
11'
10
O!!.
,08
07
:
[231
: ::":
;.~
05
04
03
02
01
00
:
,SOURCE 1 Y O~IGIN REGISTER
15'
14
13
::
..
: : :,.,: : :
00
..
DESTINATION X ORIGIN REGISTER
Figure 7· 78690 Raster Operation Control Register Format
2~55
- L·; : :
15
14
13
00
:
[25J
~~----~~----------~~~-~--------~~------~--~
NOT USED
Y,COORDINATE VALUE
DESTINATION Y ORIGIN REGISTER
15
14
13
00
:
[26J
:
~~'~------------~-------------~------------------~
. NOT USED
X·COMPONENT
FAST DESTINATION DELTA X REGISTER
15
14
[27J
13
12
11
10
09
08
07
06
:----_____________________
~
05
04
03
02
01
00
~~------------------------J
NOT USED
Y·COMPONENT
FAST DESTINATION DELTA Y REGISTER
15
14
00
13
[29J
~
NOT USED
......
X·COMPONENT
SLOW DESTINATION DELTA X REGISTER
15
1291
I :
14
00
13
~,
"-'"
Y·COMPONENT
NOT USED
SLOW DESTINATION DELTA Y REGISTER
15
[2AJ
[
14
:
~
NOT USED
13
:
00
......
. VECTOR SCALE FACTOR
FAST SCALE REGISTER
Figure 7· 78690 Raster Operation Control Register Format (Continued)
2·56
Confidential andProprietaty
Preliminary
M
15
I:
[2BJ
786.
13
:
00
:
~.
NOT USED
I
,;
y"
VECTOR SCALE FACTOR
SLOW SCALE REGISTER
15
13
14
[2C]
......
~
NOT USED
ieJtaYReg;.st.el'-The slow source 1 delta Y (SSDY) register contains the value
for the fast + or-delta Y for source 1.
[22] Source 1 X Origin Register-The source 1 X origin (SXO) register contains the value for the X
coordinate of source 1.
[23] Somce 1 Y Origin Register-The source 1 Y origin (SYO) register contains the value for the Y
coordinate of source 1.
[24] Destination X Origin Register-The destination X origin (DXO) register contains the value
for X coordinate of the deStination origin.
[25] Destination Y Origin Register-The destination Y origin (DYO) register contains the value
for Y coordinate of the destination origin. This value can be a device or world coordinate
depending onthe destination selected for the index mode.
[26] Fast Destination Delta X Register-The fast destination delta X (FDX) register contains the
value for the X component of the fast destination vector.
[27] Fast Destination Delta Y Register-The fast destination delta Y (FDY) register contains the
value for the Y component of the fast destination vector.
[28] Slow Destination Delta X Register..... The slow destination delta X (SDX) register contains the
value for the X component of the slow destination vector.
[29] Slow Destination Delta Y Regist.el'-The slow destination delta Y (SDY) register contains the
value for the Y component of the slow destination vector.
[2..\] Fast Scale Regist.et-The fast scale (FSC) register contains the fast vector scale factor for
source land destination innormal and linear pattern mode. Bit 13 =0 selects upscaling and bit
13 = 1 selects downscaling. The binary point precedes bit 12.
[2B] Slow Scale Register-The slow scale (SSC) register contains the slow vector scale factor for
source 1 and destination in normal and linear pattern mode. Bit 13 = 0 selects up scaling and bit
13 = 1 selects down scaling. The binary point precedes bit 12.
[2C] Source 2 X Origin Register-The source 2 X origin (S2XO) register contains the X coordinate
of the source 2 origin that is added to the unindexed destination origin. The source 2 X odgin is
specified as an offset from the destination. No indexing is provided and it can be used to generate
objects that are not (;)0 the display.
[2D] Source 2 Y Origin Register-The source 2 Y origin (S2YO) register contains the X coordinate
of the source 2 origin. The source 2 Y origin is specified 11.& an ·offset from the destination. No
indexing is provided and it can be used to generate objects that are not on the display.
[2E] Soun:e 2 Height and Width Register-:-The source 2 height and width (S2HW) register
determines the size of the source 2 tile. The register bits are defined in Table 10.
Confidential and Proprietary
-
Preliminary
15:08
07
Destination address bit function-,.,Se}ects the destination address bits as follows: .
Bit 7 ... 0: Hish hits of destination axetmn~ before. adding tosow:ce 2 origin.
Bit 7 ... 1: All destination address bits are added to SOU1'ICe 2 origin.
06:04
Tile height (H)-Selects the tile height. H=O to 7 whi¢h
is 2(H+2. from 4 to 512.
,
Reserved
03
02:00
.. ,
~
:-
,
'
;
Tile width (W},-,-,Selects the tile width~ W ...Otd7'~is ~H) from4to512~ lfhe tile
width must not be set to less·thl:i.nthebus width.
..
(2F] Error 1 ReJister-The error .1. (ERR1)registrr contains the .error adjustment vector added
.
.
during raster initialization for the slow destination (13 side) fill mOde.
[2F] Error 2 Register- The error 2 (ERR2) register contains the error adjustment vector added
during raster initialization for the fast destination in normal and linear pattern mode and for the
source 1 (B side) in fill mode.
Screen Format Control Registers
The screen formafoonttol ~isters, shown in FigUre 8, Select the Vd,t;cil and horizontal timing
events, number of read cycles, bus width, and refresh rows.
15
14
13
12
11
10
00
[31·341
~.
~;~T~~::EVENT J
RESERVED -....,..,.---""
Y SCAN COUNT 0 TH ROUGH 3 REGISTERS
09
15
[35J
~
__________
~~
__________
~it
NOT USED
~--N-U-M-B-ER-O-"tREAD CYCLES
MEMORY CONFIGURATION------...J
X SCAN CONFIGURATION R.EGISTER
Figure 8 • 78690 Screen Format Control Register Format
Confidential.and Proprietary
2-59
-
15
14
13
[36]
12
: :
11
10
.09
08
: :
07
05
06
:
: :
04
03
02
·01
00
:,
........
~.~~------~~--~--------~------~------------~~
NOT USED
WIDTH LIMIT
X LIMIT REGISTER
15
{37]
14
13
00
I :
1
~------------------------------------------------~,
NOT USED
HEIGHT LIMIT
Y LIMIT REGISTER
15
'''''',1
14
f
RESERVED
PROGRAM BIT
11
13
10
00
~;
J
EVENT
I
'-----.. .
TIME OF EVENT
X SCAN COUNT 0 THROUGH 6 REGISTERS
15
05
14
04
00
[3F]
NOT USEO
PHASE ADJUSTMENT VALUE
NOT USED
SYNCHRONIZATION PHASE REGISTER
Figure 8· 78690 Screen Format Control Register Formct (Continued)
2-60
Confidential and Proprietary
-
[3t·J41Y Se:aa Count~ten (0·3)-TheY scan count(YCTOthroughYCT3) registers,are:used
to Jil~thevematl e&ents. Each register determines ithe ri.mefur(jne~(:alevertt, suclna:s
vertical blank time, in order of increasing time. If the horizontal period is an odd'tlumberoftruljot
cycles, the vertical period must be set for ,n even number of scans in a frame. Table 11 describes the
function of the. register information.
Bit
~,
15:14' NOt used
13:12 vertical event-Sdectsthe vbncaI's~~llnagl~leveni(iis £(snoWs:
" i!;\ ,l
Bit
Event
13
12
o
o
0
1
0
1
End vertical period. Set vertical bbutk low in the £911owing scan.
Set vertical blank high.
,.. " .,.
."
1
Set vertical sync low.
1
Set vertical sync high.
Example:YCTO~s vet1icalhhUlkhi~YC1!l sets ~'Sfll9higll,¥CT2 sets vertical
sync loW, and YCtl s¢ts verdCii.l~1ank Imvmrestatls:.~~~~Thevideo
i"
•
cOnttol~f!es'S§s~'sYntiequestm tlieSeahprPf·tb·~~~verticalblank. The
X scahregis~~e ~,~d@ng.'"
. ", ,,'
,
11
Reserved (must be zero)
10:00 ' timeof~(~~~ t¥t~6ft'h~'eventfto~¥d~ti~1tot~ical'~
(In scans), ·'~·fot've~~~p.bd~ w~¢ ii~et·t~(he~¢ildfistanSm·a fnlme nlintis
Orle."
i.;
i ' , ".'
. . . . . . , . ; : ,if
. " " " , ·i,,"S,:':."·".'
Gonfidential.andProprietsty
_ _ _ _'_1iii1Bt. n
. ._
'~"""'
_=--_..-,. ". ..-----,
_"""""""i!
__'_ _ _ _'_;iII..
.• ,"
2-61
...
[3'] X Scan C;on6gurationRegister....;.,'fheX sean oonfiguration(X{;OJ:'.Il 'tegist~ detetmibes th~
bus widths, the number Q£~d <:ycles, lll1Q the memorywnfiguration.1'he register infQrm:;\tion is
described in '!able 12.
Table 12 • 78690 X Scan Configumtion Register Description
Bit
Description •.•.
15:09
Notused
08
Memory configuration:-Controls the number of row addresses refreshed on ;,each s,can.
-,
07 :06
Bus width-This mode is programmed in the vid~ control and video proceSsor before a
bitmap memory access is performed as follows:
Bits
Bus width
05 :00
1
6
o
o
0
1
1
1
0
1
4-bit
8-bit
undefined
16-bit
of
Nurn,ber. read cYcles-,The numPer of major read cycles used for each scan. no.rmally set
the smallest il;lteger gtellter than or .equal to the numbe~. of pixels to be cUsplayed on
each scan divided by 128, 64, o.r 32 in the. 16-, 8-, or 4 bhbuswidth mode, reipectively.
to
(36] X Limit Register-The X limit (XL) register selects the width of the memory that willbe read
during the 1'I!fl:t':sh process. This value must be the number of read Cycles ~ the X scan
configuration register multiplied by 128,64, or 32 in 16-, 8-, Qr 4-bit bus widthmQdes, respectively.
(37] Y Limit RegiBfet'....;., The Y limit (YL) register selects the height of memory that will be read
during the refresh process. This value is set to. the memory height plus the number of extra scans
required during down scrolling.
[38·3E] X Scan Count Registers (0-6)-The X scan CQunt (XCTO through XCT6) registers are used
to program most of the horizontal timing events such as horizontal blank time. Each register
determines the time of one horizontal event and the events are stored in the Qrder Qf increasin,g
time. The information in the register is defined in Table 13.
2-62
Confidential and Proprietliry
-
18,"* 13 • 78690 X Sean Count Rqisten (0-6) Delid:iptioos'
Bit.
15
Reserved-Reserved for test. (normally zero)
14
Program bit-Set to one in the X scan count iegiste1'~ theXSCanCOU11t~
that rontains the sync request event (bits 11:0),. rN.s.~~:~ cte~;~:~re~J(
SClln count registers;
13:11
Event~Sdeenthehorizontalpanuneters :a follows:
\i
Bits
1J
o
o
o
o
1
1
1
1
10:00
o
Event
Set horizontal blank loW.,'
Set horizontal 15birik high.
Set horizontal sync low ....' '. ,
Set horizontal $.~.i'
Set horizontal sync lo\\t?
Set hoclZOririilsyncKhigh:
End ho~ntalperiod,
1
Set sync request event.
12
11
o
o
o
1
1
o
1
1
o
o
o
1
1
1
Time of event-Sdects the time of event, in increments of 1/16 of a major cycle, from 3 1h
major cycles that precede tlJ.le start of the first.~ry<:ycleii:lri'1a~;~·sw-tMi
memorycycl~isat; the·n.sing ;edge:'(jf: th~tPffi: 2: Ui~~i~uf~tKe{RlAS'~ ~t
begins the c y c l e . "
.<,:.'
",
1
••. '
. •i'
•
[3FJ S~Phase ~~1'hesync phase(~~~~~t#cOhtait1Sthe sy~p~ adjust~t
vaIue.Th.is is the v~5hat the ~ controlloads into the horizontal sync counter at each system
sync time(<;lDCe petftame).
• Specifications
The mechanical, electrical, and environmental characteristics and s~f~sa~io~ifur the 78690
video, control are described inthefollowingparagmphs., The test conrution${Oft&electricaI values
are as follows unless specified otherwise.
• Powersupplyvoltage(Voo): 5.0V±5%
1)"
;"
Mechanical C o n f i g u r a t i o n , .
" i.'>
.,..
The physical dimensions of the 78690 84-pin cerquad paGkatieareeontained in APpendix E.
-
Absolute Maximu~ltatitlgs! . •. ; ,
. ..
Stresses greater thanthe~bsolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adverl;elyaffect the
reliability of the device.
• J;bw~ supply voltage (Vno): -0.5 V to 6.0 V
• Input voltage applied (Vin): .:..05 V to 6.0 V
• Output voltage applied (VoUt): -0.5 V to 6.0 V
• Power dissipation (Po): 3.5 W at ooe
• Storage temperature: -55°C to 125°C
Recommended Operating Conditions
• Power supply voltage (V00): 5 V ± 5%
• Temperature (TJ: O°C to 70°C
de Elec,nad. Characteristics
The de elel:trieal parameters of the 78690 video control for the o~fating voltage and temperature
ranges specified are listed in Thble 14.
SyDlbol
Table 14 • 78690 de Input and Output Parameters
Requirement$ '.
Test Condition
Parameter
Max.
Min.
VIH
High-level
input voltage
Vn.
Low-level
input voltage
Von
High-level output
voltage
2.0
V
0.8
10"=0.2 rnA
Units··
2.7
V
V
VDn=OV
VOL
Low~level output
101.=-5 rnA
voltage DAT < 15:00 > Vnn=OV
0.5
V
VOL
Low-level output
IoL==-5 rnA
voltage all ot~er outputs
0.4
V
CLKIH
2.7
Clock input high
V
level
CLKn.
Clock input low
level
InD
Active supply
current
2-64
VDD=max
Confidential and Proprietary
0.4
V
0.66
rnA
_.
Symbol
Preliminary
Test Condition
~
78&90
~m.
ltH
Input high leakage
current
VDD=max
VIn =Voo(max)
In.
Input1ow- leakage
current
Voo=max
Vin=OV
1m
Hi-impedance
input high leakage
current
VDD = max
V'" =Vnn(~ax)
In
Hi-impedance
input low leakage
current
VDD = max
V",=OV
C.
Input caPacitance
CIO
Input/output
capacitance
K
Units
Requirements
Max.
20
JJA
-20
JJA
20
!LA
... ':'.20
~
.10
pF
...-;..
10
pF
Electrical Cbatacteiristic:s
The ae timing parameters for tbe,78620.video .cuntrolareJgt'Puped according to clock input,
processor interface, instruction/data bus, me:tnory interface, and monitor timing and synchronization request. Thhle 15 lists the ac input specifications.
Symbol. Definitio~
C..
C..
Input capacit!lnce
10
pF
Input/outpl,ltcapacitance
10
pF
Input s~ rise t;ime
Input signal fall time
os
10
os
The {ollowing conditioosapply to the ac test conditionsubles~()therwisestated.
• The delay times extend from the 1.5 V level of thedotk input to the· Vem or '1101. level of the
measured signal.
from
• The rise times are measured
the 10% to 90% level9f~btl signal, ttansitions. Fall times are
measured from the 90% to 10% of the signal transitions.
• The measurements are with a 50 pF capacitive load on the outputs. Exceptions to this are outputs
ill < 7:0> that have a 500 pF load, and DAT < 15:00 > that have a varying load up to 500 pF.
2-65
-
Clod:~t Tuning
.. ....
'
....
. . .. ..
...
The ac fuput parameters for the phase fuput clock signals PHIl through PHI4 and the CAS signal
are shown in Figure 9 . The parameters are derIDed in Table 16.
14--------- C 1 2 P R - - - - - - - - - ' - - t
t
tC12PW
PHil
PHI2
PHI3
,
__________________~Jr--~~==.~tc~1~2P~W====~~~____
B
tC34PR
tC34PW
CAS
R
h
______
/
~t C34PW
tC34NO
PHI4
. . .r
tc12NO-1'-----------------------·
,1:==
tcCPR
~
~--tC~R
-f I--
tccpw
.
I
C:
-I I- CF
t
_ _ _ _ _ _ _ _ _ __
Figure 9· 78690 Clock Input Timing
Table 16 • 78690 Clod: Input Taming Parameters
Symbol Definition
Requirements (ns)
Min.
Max.
tcUPR
Period of PHIl··~ PHI2
228
684
tc-.
Period of PHI3 and PHl4
114
342
tCCPlt
Period of CAS
85.5
te12pw
Pulse width of PHIl and PHI2
85.5
tcJ4PW
Pulse width of PHI3 and PHI4
28.5
~
Pulse width of CAS
28.5
tca*
Rise time of PHIl, PHI2, PHI3, PHI4, CAS
5.0
ta*
Fall time. of PHIl, PHI2, PHI). PHI4, CAS
5.0
;te12PW
Nonoverlap time of PHIl andPHI2 .
23.5
tcJ4NO
Nonoverlap time of PHI3, PHI4
23.5
teen
Low time between CAS pulses
57
"ruse time is measured from 0.4 V to 2.7 V; fall time, from 2.7 V to 0.4 V.
2-66
Confidential and Proprietary
257
PrOcessor In. .: r•....~
.'
The PlXlCesso~jnterfate timing is ,shown in Figure 10 and the parameters listed on the figure·are
d~ined in !able 17.
.AO(05:00)
RD
DATA (WRITE)
DATA (READ)
Symbol Definition
·.·~tJ'u..)'\"
~m:.. ...
..'Read. Ytlte
tASAS
The time that· the ~ input must ~~be .asserted
before being reasserted.
t05
Setup time for valid input data on the
ADD < 5:0> inputs relative to the falling edge of
the AS input.
0
0
180
180
Hold time for valid input data on the ADD < 5:0 >
after the falling edge of the AS input.
40
40
The time from assertion of the DS input to deassertion of the AS input.
140
75
~aWnuun
J Write
Itead·
Pulse width of the ~ input if the OS input is not
asserted.
Confidential and Proptiemry
.,.,....
2-67
l'L._I! ....... ! __ _
,'.1"'.n:m.n.uuary
Requirements (ns)'" .
Minimum
Maximum
Read Write Read Write
Symbol Deanition
t nssu
Setup time for valid data on the OAT < 15:00>
inputs relative to the falling edge of the os input
during bus write operations.
t DSPW
Pulse width of the DS input.
tltDDS
t DSRD
t DHLn
0
140
95
The time for valid input on the RD input before
the assertion of the DS input.
30
30
Hold time for the RD input after the falling edge of
the DS input until the deassertion of the DS input ..
40
40
Hold time for valid data on the DAT< 15:00>
inputs after the falling edge of DS input during bus
write operations.
40
Delay time for valid data on the DAT < 15 :00 >
outputs relative to the falling edge of the os input
during bus read operations with a 50-pF capacitive
load on the outputs.
140
tDVONAt Delay time£or valid data on the DAT<:15:00>
outputs relative to the falling edge of the DS input
during bus read operations with a 500-pF capacitive load on the outputs.
410
tnvON
Hold time with previous data valid on the
DAT < 15 :00> outputs after the rising edge of DS
during bus read operations
0
The time from deassertion of the INIT input to the
assertion of the AS input.
100
100
tINP'III+
Pulse width of the INIT input.
12xt
12xt
t AOOP
The time from assertion of the AS input to deassertion of the DS input.
180
135
t DVOF
tINAS
t ASDV
Delay time for valid data on the DAT<15:00>
outputs relative to the falling edge of the AS during
bus read operations.
50
180
*Timing is measured at the VOB and V OL levels
ttnvoNA = tDWN + 60 ns per 100-pF capacitance additional loading. (Intermediate values may be
calculated.)
+This para~r is 12 X t where t == PHIl or PHI2 clock period.
2-68
Confidential and Proprietary
-
Instruetion/Data Bus Timing
F'lgw:ell sllbWs tnewtmctidri/databussignaltimi.ngandthe timingpaf9tnetersere listediill Table 18.'
INSTRUCTION
LOW B)'TI: OATA
INSTRUCTION
PHI2
IO«)7:00)
TRANSMIT
10<07:00)
RECEIVE
lOBUS
DON'T CARE
~-r------~----~~~~~~~---h--~~~
--~--------------~~~~~----~---r~--------
IDCTL _ _ _ _ _ _ _
• V_A_L_IO_ _~""""""""--I
Figure 11 • 78690 Instruction/Da/a Bus SigtJat Timing
Symbol DelinitiOltl.
Maximumdelay,~e&m~9U~t?~~I'~'~"'~'<'¥i'~<~~S
relative to the rising edgeo£ the PHIl AandPHI2A input. '
60
Delay time from the faJllng edge of the PHllA and PHUA input to
thehigh-~IUl~levd QtlJqeIQ"~}:Q,> lin~s.
5.0
25
Minimum~~~~t~~~ijt~~(jrl~~'l~~·t~~,.r~~·
re1at~to the
falling edge of the PHll B and PHIl B input.
,,,20,,:
~~tnhold lim~ fo~Vfo\U4jQP~t,c:la!!!.Qn.~~ID51:0? Jines
after the falling:edgelof.pPlllB:and;,~B),.t. ;t,;~J'
;;\',>,
,:,,' ',", ~-: "-
",,' ,..>~:'
, .• ,"
',"',_-,,~:/i, '::- , -' ','
-'I,
ot :,,'
~," ,.-,il,,,,,
,"':.
With pt'eViouSootput'dttta viilld;'iccsH is the I1li.iilrriuri1 held tinle
on the IDCTLQutPJ,lt~tjve to "tl;te. risinge4ge of ~e PHIl B .
signal. (PHIl '8 is ~buttime is(tefere0ced:;to'~P:rulsigniI.,.J"
Maximum delay tim.e for~ltows the memory ;interface sign!lltiming an4the tim,ingparal,lletersare listed in Table 19.,
CAS TIMING
CAS
•.
m:(03:00)
SCROL
MAD<10:00)
tcAOt-
tCAH
\.0-,.
.VAtIOI
I
1 VALID I
VALID.
PHI
~
TIMING
MA;jORCYCLE
MAJOR CYCLE
MEMORY
CYCLES
MINOR CYCLE
MINOR CYCLE
MINOR CYCLE
PHI2
128
FORCE
MRD
PHil TIMING
PHil
ADS
Figure 12· 78690Memory Inter/(keSignal Timing
Symbol Definition
Requirements (ns)
Min.
tCAH
The delay time that the previous outpufof theMAD< 10:00>, ..
WE < 3 :0>, and SC~OL signals is valid after ~he rising edge of
the CAS input.
.
The delay time for valid outputs 'of the MAD < 10:00 >,WE, and
. SCROL signals litter the rising ~e qf the CA,S input.
tecH
2-70
The dday time that the previous.outpUt tif the 128/I6at:ldFORGE
signals is valid after the rising edge of PHI2 A input.
Confidential and Proprietary
Max.
,8.0
55
55
The titne that the previous outllUtohbeMlUl.I,~,~j{~
the rising edge-O{~PNI~4 input~
.l.
I ' ~'}c:
_.'
."
"')~'_-" "_-'_-'~-_;.:\·'_,,_;r:_, ,',,~."{,:<"'''''- _ ~:-f<,
,','--' ,,',',:-,
.
_','_'-~--'
The delaytilnefp~yalid ~,tftlle~.~~;~~~~~;··
edge of the PHI2 A input.
'.i'"
'_
,",'
. 5,{)'"
55
Minim~ hoWti~foi~diilP\lt~l;~AQS:~~~~ tq.'i
thefallingedge!lf;~lnl:JJ 'i;."
.
\H'
f;;';til>i';r.; . . .
27
Monitor TIOlinK and Syncluoniution "'~IB:;'f:'
~ngthe ·s~tililationintetVal,·the'PHI1;PN12~rI't~'~
leveI,-and the CASroputis~ k-LahlghleveL' . t";": ' ! '.' '.' . . . . m~~tion clock
timing and the param~;ar6'-ti:!lt~(Nni1aBW (}.1'he'~W~iibjutr~rs.~:valid fOl'.t4e
SYNC request from thevi~ro~ Oflfrijm~-sowiej"~lli:kfcks'¢.ofl.ue~the SYNC
in~.
;'~'-;';':'"
PHil
~'f'~
PHI 2
~....----..~
PHI 3
~I
PHI 4
'L.fL1LJl-JL
~.su.··J:t'~
tsVR
SYNC
tsVF
I
tsVPW
Figure 13 • 78690 Monitor and SynchroniZlJtion Request Sifflai Timing
2-71
-
.D..._1L.!_
"t;rtalllllIlary
11ALle2b· 78690 Monitor and Synchronimtion Request Timing Paramet.ets
Symbol
Defiriidon
tnm
The delay time for valid output of theVSYNC orSYNCRsignal
Requirements (ns)
Min.
Max. ,
90
relative to the rising edge of the'PHIl or PHLl! inflUt.
tVuH
teMPD
to.m
1:svsu
1:sVJ"&1*
t svPz*
The delay time that the previous output ofthe VSYNC or SYNclt
signals is validiretative to the rising edge of the PHIl orPHI2
inputs.
The delay time fOr valid outtmt of the CMPSYN or BLANK signals
relative to the rising edge of the PHI3 or PHI4 input .. '
The delay time that the previous output of the CMPSYN ot
BLANK signals is valid relative to the rising edge of PHI3 or PHI 4
inputs.
Minimum delay from the assertion of the SYNC signal to the PHI2
input going high. This delay starts the clock freeze period that is a
restriction of the external clock generation control.
The pulse'widtll0ftheSYt)l"Csignal.
0 '
--'
45
5.0 .
. 0
' SOO
. 241lS
400
,24 IJS.
The delayrlme from the deassertion of SYNC to the elld of the
clock D:eeze.time. This delay is·a restrictum of the external clock
generation control.
tsVlt
Input rise time of the SYNC pulse.
50
tm.
Input fall tUne OJ! the SYNC pulse. .
50
*tsv..
+ tsvpz must be equal to (or be a multiple of) 16 periods of the PHIl or PHI2inputs.
2-72
Confidential and· Proprietary
..
Symbol Definition
The assertion .propagation delay for the }NT or REQ signal in
response to • status bit being set when the correspondiqg bit of the
Interrupt or Request Enable register has been set ,previously.
Delay tA is measured from the edge of the or system clock signal
that sets the status bit.
0
140
The deassertion prop3gation delay for the IN! orRm'jsignal in
response to a status bit being cleared when the corresponding bit
of the Interrupt or Request Enable register has been set'previously.
Delay tD is measured from the edge of the DS signal that clears the
status bit.
0
.140
The assertion prop3gation delay for the iNf or REQ signal in
response to setting a bit of the Interrupt or Request Enable
register when the corresponding status bit has been setpreviousIy.
Delay tAM is measured from the edge of the D'S signal that sets the
Interrupt or Request Enable register bit.
0
180
The deassertion propagation delay for the }NT or REQ signal in
response to clearing a bit of the Interrupt or Request Enable
register when the corresponding status bIt has been set'prevlously.
Delay tDM is measured from the edge of the DS signal that initiates
the resetting of the Interrupt or Request register bit.
0
180
ru
. Interfacing Teehniques
Up to twenty-four 78680 video processors may be used with each video con.trol. The video control
includes a system interface, a bit-map memory interface, and a display interface as shown in Figure
3. Refer to the Dragon Video System Hardware Specification for 1I. Complete description of a video
system using the 78680 video processor and 78690 video control.
The system interface connects the video control to· the local p~ssor or DMA controller through
the processor interface. The processor interface transfers 16 data bits, 6 address hits and 6 control
bits and receives the parameters and commands from the local processor. The interface handles
register accesses and controls timing and all necessary bus signals.to allow the video control to act as
a bus slave to the local processor or DMA device. The system interface also connects the video
control to the instruction/data bus through the ID interface.
The ID interface t:rans£ers information on the 8-bit bidirectional instruction/data bus and the chip
select control line. The instruction/data (ID) bus is used to transfer information within the video
processor and to controls its operation. It is used to load and read registers and to execute direct or
indirect instructions.
The bit-map memory interface includes the bit-map memoryaclcfressbu.Sand tHe'sigi'nilsthat
control it. It transfers address information on lllines, write enable iriforniationon 41ines,and
control information on 5 lines.
The display interface connects to the monochrome or color monitor interface for video and riming.
The interface signals include the four synchrcnllzation and blanking signals.
The video control requires a 5-V dc power supply.
2·74
Confidential and Proprietary
• Features
• Programmable for videOOisj:days usinga.maxiOrum of 4096by·4096 phrelJocatioos;
• Compatible with Digital's DC322 video processor and DC323 videocontrol
• Interfaces with the MicroVAX 78032 microprocessor and Motorola 68000 series~ro~essors. ,.
• Selectable cursor characters and single- or double-w,idth hairline cUrSor·,··, .1.'< .... "" .
,', "
_"
_, _ l' ',_
';'
_
~
;
\,
,_', ..
. Description
The DC503 programmable cursor chip (FCC) is contained in a 44;pin c:erquad package and is used
to provide a programmable cursor for use with vid.eodisplay terminals. Figure 1 is a simplified block
diagram of the DC503.
OIIT<16:00>
~.
~~~
__
~
__________________
~~~~~
_________
~ro,
AN)
RI!GION
REGISTERS
SYNC
81.ANK
NllClK
Figure 1 • De50] Simplified Block Ditlgrant
Confidential and Proprietary
2-75
The DC503 enables cursorcharat.ter~ orieons to beprognunlned and poSitioned to the desired
location of a videodisplay. The De50} contains two 16 by 16 memory arrays to store the cursor
sprite. This enables the cursor to sdect up to three colors and display normal video in its
transparent region. In addition, the De50} can be programmed to display either a single- ot: a
double-width full screen hairline cursor. Two programmable boundarY J;egions on the display can be
detected and the cursor can be clipped in either of the two regions on the screen .
• Pin and Signal Description
The input and output signals and power and ground connections are shown in Figure 2 and
summarized in Table 1.
..
..
'"
~~ ~ ~~~~ ~ ~ ~ ~
GND
VDO
DAT07
DAT15
DATOS
DAT14
DAT13
PIN 1 IDENTIFIER
25
DAT04
DATl2
DATIl
DAT03
DC503
IJIlITlO
22
21
VDO
DAT02
VDO
GNO
GND
DATOS
DATl
DAT08
IJIlITO
§ ~ ~ ~ I~ ~ ~ I~ I~
z
!~
TOPVIEW
Figure 2 • DeJ03 Pin Assignments
2-76
·DATD5
Confidential and Proprietary
Table 1 • DC'03 Pin and Signal Summary
Pin
41-44
DAT<15:00> inputs
Data lines
<: 15:00>-Data inputs &om the proces-
sorlms.··
1~2,5,6,
..
'.
.
27·22
19,18
10·7 .
..~ ·lines .<.3:1);> ...,...Address .inputs from . the
AD < 3:0 >inPUJS
p~bus; ..· . • "
11
AS
input
:Address' strobe...2::St~b~s the address . . inputs
AD <3:0 > ··iifto thebdsinU:rface.
14
DS
input
Dl¢llstt1)~S~.the ga~ inWtsDAT<15:00>
','
~
into1;ke1;>us~~.
15
.
\WiIT
Writeenable~:Whert
outputs
29·32
Pffi<3:0>·
outputs
35
PARDI
output
33
PARD2
output
Plane information A <3:0>-Four-bits of the 16bit data word for cursor plane A.
P1me information B< 3:0.> -FmJr..bits of the 16-bit
·d!lta'~.$icin!~t~ B.
~ble.~ctive regi9n 1 detect-~dicatesthat
aCdveregion 1 of the dispt\1has been d~ ..
'~grarnrnable ~vere.gion. 2 detect-:- Iili:Iicates ~t
.IlCfiive region 2 of the display has been detected.
34
TEST
output
3,21,
40
VDD
input.
iVolt4e-PowetSupply voltage
4,12,
20,28
GND
input
Gtound""'-Ground reference.
Confidential and Proprietary
2-77
·Ptelifuinary
• Functional Description
The data (DAT < 15:00 > ) and address(AD~l.O > ).information £rqni the bus is loaded into the
bus interface by the data strobe (D'S) and address strobe (AS) input· respectively. The data
determines the cursor font and specifies the coordinates for the cursor location. Address
AD < .3:0> select:s the register that will receive the data. The write signal (WRT) loads the
information into the command, position, and region registers. The data is transferred to the
memory plane A or B under control.of the timing and control and memory decode logic.
Information from each memory plane is transferred to barrel shifter A and B, under control of the
barrel shifter logic, to the output multiplexers. Each multiplexer output provides 4-bits of
information (PIA<.3:0> and PIB<3:0» every 37.8 os for the 16-bit by 16-bit cursor font.
Timing and control is provided by the sync detector logic that receives the SYNC and BLANK
signals from the controlling device and the NIBCLK clock pulses.· Information from the sync
detector is transferred to the registers that detect one of the two active regions on the display. The
regions are indicated by the PARDHmd PARD2outputs.
The. te$t logic receives PARD 1 and PAR02 signals and the output from each multiplexer. The TEST·
output is used to self-test the cursor memories and active region detectors.
Register· Selections
TheY·
Address bits AD<3:0> select: a command, position, or active region register to·be loaded.
also select the cursor memory by an indirect me~ry address to an internal address Counter. Thble 2
lists the address codes and register selections.
18ble 2· DCS03 Address ~tet Select Functions
Address Line
AD)
AD2
ADt
ADO
~ster"
0
0
0
0
Lqad command register (CMDR)
0
0
0
1
LladX position register (XPOS)
0
0
1
0
Load Y position register (YPOS)
0
0
1
1
LoadXminl active region register
0
1
0
0
Load Xmaxl active region register
0
1
0
1
LOadYminl active region register
0
1
1
0
Load Ymaxl active region register
1
0
1
1
Load Xmin2 active region register
1
1
0
0
Load Xmax2 active region register
1
1
0
1
Load Ymin2 active region register
1
1
1
0
Load Ymax2 active region register
1
1
1
1
Cursor memory (indirect memory address via an
internal address counter)
"All registers are write only.
2-78
Confidential and Proprietary
-
Comouuid Register DesUiption
The command register (CMD) is a write-only register and is used for communication between the
CPU and the programmable cursOr chip. The command registerformat is shown in Figure 3 and is a nibble of cursor memory plane A, and PIB < 0: 3 > is a nibble of cursor
memory plane B.
The TEST output is used to sel£test the cursor memories and active-region detectors. Writing a 0 to
bit 15 of the Command register enables the test hardware. The assertion of any PIA<3:0>,
PIB < 3:0 >, or PARD < 2;1> output will assert the TEST output. The TEST output is disabled by
writing a 1 to bit 15 of the Command register. During normal operation, the timing of the TEST
output is unspecified unless bit 15 is cleared.
2-82
Confidential and Proprietary
-
Preliminary
. Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC503are
described in the following paragraphs. The test conditions for the electrical values are as follows
unless specified otherwise.
• Power supply voltage (Vnn): 5.0 V ± 5%
Mechanical Coofiauraoon
The physical dimensions of the De503 44-pin cerquad package are contained in Appendix,E.
Absolute ~um Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
• Power supply voltage ('II00): -0.5 V to 5.5 V
• Pin voltage: -0.3 V to Vnn +O.3 V
• Power dissipation (T1= O°C): 0.3 W
• Storage temperature: -55°e to 125°e
• Power supply voltage ('IIDD): 5 V ±5%
de Electrical Cha:racteristi.s
The dc. electrical parameters of the DC503 for the operating voltage and temperature ranges
specified are listed in Table 4.
Confidential and Proprietary
2-83
...
Preliminary
DC503
Table 4 • DC50J de: Input and Output Parameters
Parameter
Symbol
Test Condition
Requhements
Min.
High.level
input voltage
Vm
Low-level
input voltage
Va
High-level
clock input
voltage
Vm
Low-level
Va
Units
Max.
V
2.0
0.8
V
2.7
6.0
V
0
0.4
V
clock input
voltage
1m
Vin= Vnn =5.25 V
IlL
V.. =OV
VDD =5.25 V
High-level
output voltage
VOH
IoH=0.2mA
Low-level
output voltage
VOL
IoL=-5.0mA
Input high
leakage current
Input low
leakage current
20
-20
2.7
~
V
0.4
V
8e Electrical Clwaeteristics
The signal timing parameters for the NIBCLK clock input are shown in Figure 6 and defined in
Table 5. The waveforms and propagation delays symbols for the input and output signals are shown
in Figures 7 through 10. The parameters for the symbols on the figures are defined in Table 6. The
specifications and conditions for the ac tests as as follows.
• Input capacitance: 10 pF
• Input signal rise and fall time: 10 ns
• All delay times extend from the 1.5V level of the clock input to the VOH or VOL levels of the
measured signal.
• The rise times are measured from 10% to 90% and fall times are from 90% to 10% of signal
transition.
• All timing parameters assume a 100 pF capacitive load on the output.
2·84
Confidential and Proprietary
NIBCLK
Figure 6· DC503 Clock Input Parameters
Table , • DCS03 Clock Signal Tunin& Parameters
Symbol
Requirements (ns)
Min.
Max.
tM
Rising-ed!Je time
5.0
t pA
Falling-edge time
5.0
tPRD
Clock period
t1"ll'
Pulse width 50% duty cycle ± 5ns
400
37.8
~
. I ...
.
NIBCLK
PIA<3:0>
PIB<3:0>
PAROl
PAR02
I
~
I
I
PIA<3:0>
PIB<3:0>
PAROl
PARD2
I
I
I
---t:r
NIBCLK
SYNC
BLANK
=x
K=
Vlm
--I tsas -t--
tSIlH
I-
Figure 7· DC503 Clock to Input/Output Timing Delays
Confidential and Proprietary
__
._--_. ._--------_.._.. _._--------_.
2-8,
------------~
-
Preliminary
\-1.5\1 .
os
I
I
I
DAT<15:00>
=X_V_AL_'O-+IO_A_T_A_~
I
I
--J
I
tos
I
I
--1-- tOH
I
t--
LOAD DATA
J
\-1.5V
AS
I '------' I
I
r---- tASAS
AO<3:O>
~
I
---..j
~ X~_~+:~_ES_S_~
__
I
I
I
--oo-l
lAS
I
I
I
--I- tAH I-LOAD ADDRESS
Figure 8· DCJ03 Load Da.ta/Address Strobe Timing Delays
I
I
AS
\
(
I
I+---
os
;-
I
tOVLP
---l
\-m----F
Figure 9· DCJ03 Write and Data/Address Strobe Timing Delay
2-86
ConfidetitiaIartd Proprietary
NIBCLK
"1 ,--__-il~~
~
It- T~TOl'\..
Ii·
: -1 5100
.
:1
TEST
.
{..
I .
'--
I'
I
----------------~I
\::
I
I
Figure 10· De503 TEST Output Timing Delay
Symbol
Definition
Requitements (05)
Min.
MaX.
tPOOL
Propagation delay output low··· .
26
trooH
Propll8ation delay output hi~
26
t SBS
SYNC/BLANK setup time
10
SYNC/BLANK hold time
10
..
tSlH..
t05
Data setup time
0
too
Data hold time
40
tAS
Address setup time
tAH
Address hold time
tASAS
Address strobe precharge time
105
toVLP
Overlap time
100
t STOH
Propagation delay to TEST output high
40
tsTOL
Propagation delay to TEST output low
100
0
40
*The SYNC input signal must be active for a minimum of two NICBLK periods. The BLANK input
signal must be active for a minimum of two SYNC signal intervals and must encompass or coincide
with the SYNC signal.
• Interfacing Techniques
The DC503 programmable cursor chip can be interfaced to the DC323 adder and can operate with
a full-page, half-page, and quarter-page display system. Figure 11 shows the full-page display
interface configuration and associated signal timing. The OC323 generates the BLANK and
CMPSYN signals to drive the BLANK and SYNC inputs of the DC503. The BLANK and CMPSYN
signals can be latched into the £lip-flops by the PHI3 or PHI4 phase clock of the DC323 and may
rise on one PHI3/4 clock and fall on the other. The latched BLANK and SYNC signals are received
by the DC503 on the falling edge of NIBCLK pulse. Latches are 374 or the equivalent.
r--
BLANK
BLANK
D
ADDER
DC323
~
DC503
CK
i....---
CMPSYN
I
I
r---"
0
Q
SYNC
PHI3
PHI4
CK
-
NIBCLKH
PHI3
PHI4
Figure 11 • DeJ03 Full-page Display Inter/ace and Timing
Confidential and Proprietary
-
-
DC503
Figure 12 shows the haH- and quarter-page interface configuration and signal timing. The BLANK
and CMPSYN signals from the DC.32.3 are used directly as inputs to the DC50.3.
BLANK
XBLANK
ADDER
DC503
DC323
CMPSYN
NIBCLK
XSYNC
--.J
PHI3
PHI4
_---'n_____n'------'no..--_
Figu1'e 12 • DeJO) Hal/- and Quarter-page Display Interface and Timing
Confidential and Proprietary
2-89
· Section 3-Communication Devices
The asynchronous communication devices enable serial-line information transfers between local
remote systems and terminals.
78808 Eight-channel Asynchronous Receiver/Transmitter-The octal ART is a 68-pin cerquad device
that is programmable and allows the simultaneous transmission and reception of eight serial-line
channels.
DCJ19 DLll Compatible Asynchronous Receiver(fransmitter- The DLART is a 40-pin DIP device
that allows data communication between Digital's microprocessors and console terminals or
communication devices.
Confidential and Proprietary
------"----------------"-""--~-"-""
• Features
• Eight independent full dpplex serial data lines
• Programmable baud rates individually selectable for each line's transmitter/receiver (50 to 19,200
baud)
• Summary registers thai allow a single reooto detect·~ data Set Chll1lge or to determine the cause of
an interrupt on any line· .
.
..
• Triple buffers for c;aeh,.teeeivef
• Device saUlOer m~m that reports interrupt request due transmitterJ~vet interfUpts
• Independently p~ble lines for interrupt-driven operation
• Modem stitus chaPge detection for Data Set ~y(DSR) and Data Carrier Detect (DeD) signals
• Programmable int~pts for modem status changes
~ Synchro~s critic8I read-only ~gisters
• Description
The 78808 Eight-duinnel Asynchronous Req:iver/l'ransmitter (Octal ART) is .·a VLSldevice for
new generations o£'asynchronouS serial communication designs and for micr040mputer·systems.
This 68-pin devia: (performs the basic operations necessary for simultanedus reception and
transmission ofasynduonous messages on eight independent lin~s. Figure 1 is a functional block
diagram ofthe 788Q80cta1 ART. .
:r.oo
RxDO
DSRO
DCOO
TK01
R.kDl
DSRl
OCDl
Tx02
R,I(D2
DSR2
DCD2
TxD3
A)I;03
OSR3
l----I--
DeOl
Tx04
R.D4
DSA.
DC DO
Tx05
Ax05
D'SRS
1 - - - - 1 - - DCDS
r.oo
R.oe
OSRe
1 - - - - 1 - - OCDS
T.07
RxD7
OSR7
'-- _ _. . . . 1 : - - OC07
Figure 1 • 78808 Octal ART Functional Block Diagram
Confidential and Ptoprietary
. ""''''''''_'''__' ' ' ' ' '...' --,...""-~..,.....- -.....- - - - - - - .
-~~""'",~"',_J@!~"""'."'
·,Pin~d ~~efinitions
The input and output pins and power and ground connections of the 78808 Octal ART are shown
in Figure 2. Thble 1 provides a summary of the signals defined in the following paragraphs.
..
N
Ei
a 0
« «
0
a:
~
0
'"Z
..J
0
0
Z
..J
..J
0
0
z
0
0
!:!: !!: !:!: !:!: >
i,,07
VSS2
OSR7
TxD3
DCD7
.:i5SR3 ;"
RxD6
1-.....;""'O:-~--l
0CiTh
I
"RxD3
I
I
5Ci56
OSRIi
I
I
J
I
I
I
I
1
Tx06
TxOS
DSR5
DCPS
RxD5
Ax04
5
DcD4
6
,I
78808
CAVITY DOWN CONNECTIONS
lOP111EW
I
I
I
I
1
38
RxD2
37
DCD2
36
5SR2
35
Tx02
T"OI
m1
5Ci51
I
. _ _ _ ..;.;. _ _ _ .JJ
L.-_
RxDI:.
RxOO
i'iS'R4
29
T"D4
28
VDD
8
9 10 11' 12 13 14 15 16 17 18 19 20 21
22 23 24 25 26 27
Figure 2· 78808 Pitt Jissignments
Confidential and Proprietary
DCoO
i5SRO
T"OO
-
Table 1,·'8808
Pin and Signal Summary ,
,
,--
- ,
,
-
'"
~
Pin
10·13~22-25
Dataliries< 7:0:>-Receiveliand frans-
input/output
'mi~sthe'paralIel dil:tilt
50-52,54.56
~D<5:0>
Chip~I~""".Activ.aresth~ §Jctal~T, to
receiN~ij,nd \tr.!lsmitd~ta over the
17
,DL lines.
Ready-Indicates when the Octal ARTis
ready to p~icipate in data transfer cycles.
14
15,
input
Reset-Initializes the intefuallogic.
57
MRESET
input,
Manufacttrring re~t-Fo~ manufacturin8
use;.
58
eLK
inpUt
Clock-Clock input for timing.
62,67,2;7,
DSR<7:0>
inputs
Data set ready-Monitor data set readt
(DSR) signms froml1lodenis.
41~36,33,28
63,66,},6,
40,37,32,29
Da~ set carrier de~ct-Monitordata s~
cattier det~ (DC D) signals frominodems.
DCD<':O>
49
output
·'lnterrupt ~uest":":'Requests a processor
interrupt.
45-47
output
Interrupt ~uestline number-Indicates
the line number of originating interrupt
request.
48
'IRQTxRx
output·
Interrupt request' transmit/receiv'e-Indicates whether an interrupt request is for
transmitting or re¢eiving data.
61,68,1,8,
'txD<:7:0>
outputs
Transmit data-Provides asynchronous
bit-serialdllta ,output streams.
RxD<7:0>
outputs
Receive da~a-~pts asynchrOnous bitserial datalnput streams.
input
Voltage-Power supply voltage +5 Vdc.
input
Ground-Ground· reference
42,35,34,27
64,65,4,5,.
39,38,31,36
44,26,9
16,59,43
V"
3-3
...
7Sg0S
Data and A d d r e s s .
..... '"
Data lines (DL < 7:0> )-These lirl~s are used for the p~~l 'transmission and reception of data
between the CPU and the Ochd ART,' The receivers 'are active when theclata strobe (DS 1, DS2)
signal is asserted. The output clrivers are active OIily w~n the chip select (CS) signal is asserttxl,the
data strobe (DSl, DS2) signal is asserted, and the write (WR) signal is deasserted. The drivers will
become inactive (high-impedance) within 50 nanoseconds when one or more of the following
occurs: the chip select (CS) signal is deasserted, the data strobe (DST, ~J signal is deasserted, or
the write(WR) signal is asserted.
Address (ADD < .5:0>- )-'fhese lines select which Octal ART internal register is accessible through
thIe data I/O.lines (DL<7:0> ) when the data strobe (DST, DS2) and chip select (CS) signals are
asserted. Table 2 lists the addresses corresponding to each register. The receiver buffer and
transmitter holding register for. each line have' the same address. When the
signal is
deasserted, the address. accesses the. receiver buffer register and when asserted, it accesses the
transmitter holding register.
.
cwm
1able 2- 78808 Registers Address Selection
ADDLine*
4
.5
0
0
0
0
0
3
:2
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0,
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1,
1
1
1
--~-~-
-"~~-~-
0
.0
O.
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
1
0
1
0
1
0
0
.0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
O.
0
1
1
0
1
0
0
0
0
0
0
0
0
-0
1
1
0
0
0
1
1
3-4
,
1
0
0
0
ReadfWrite
Register
Read
Write
Read
Read/Write
Read/Write
Line oReceiver Buffer
Line 0 Transmitter Holding
Line 0 Status
Line 0 Mode Registers 1, 2
Line 0 'Command
Read
Write
Read
Read/Write
Read/Write
Line 1 Receiver Buffer.
Line 1 Transmitter Hol~
Line 1 Status
Line 1 Mode Registerl, Z
Line 1 Command
Read
Write
Read
ReadfWrite
ReadfWrite
Line 2 Receiver Buffer
Line 2 Transmitter Holding
Line 2 Status
Line 2 Mode Register 1, 2
Line 2 Command
Read
Write
Read
ReadfWrite
Read/Write
Line 3 Receiver Buffer
Line 3 Transmitter Holding
Line 3 Status
Line.3 Mode Register 1, 2
Line '3 Command
Read
Write
Read
Read/Write
Read/Write
Line 4 Receiver Buffer
-Line 4 Transmitter Holding
Line 4 Status
Line 4 Mode Regist~ 1, 2
Line 4 Command
Confidential and Proprietary
.
~-~.----~--
~-'---->-~~-~\~~,~~
"-T~~,,"_~~W"'!'
~!7-~
~-~!!'
'_",",_,e __~~N
-,
Read/Wcite
Register
0
Read
Write
Read
Read/Write
1
1
H.e~ad/Write
Line 5 Receiver Buffer
Line 5 Trartsmitter Holdmg
Line 5 Status
Line 5 Mode Register 1, 2
Line 5 Co1ll1ltlind
0
0
0
0
0
0
0
0
1
1
0
0
;Rew;!
.Write
1
0
1
Read
Read/Write
0
0
0
0
0
0
0
Read
1
1
1
1
0
0
1
1
0
1
0
1
'Write
Read
Read/Write
Read/Write
Line 7 Receiver Buffer
Line 7 Transmitter Holding
Line 7 Status
Line 7 Mode Register 1, 2
Line 7 Command .
X
X
1
1
0
0
1
Read
Read
Interrupt Summary
Data Set Change Summary
ADDLine*
4
3
2
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
1
1
1
1
1
18808
~
1
1
1
1
0
1
Read
Line 6 Recdver B~
Line 6 ~tter Holding
Line6Stf,ttus
Line 6 ModeR.egiste~ 1, 2
Line 6 Command
"X = Either 0 or 1.
Bus Transaction Contto1
Chip select (CS)-This signal is asserted to permit data transfers through DL<7:0> to or from
the internal registers. Data transfer is controlled by the data strobe (DS1, DS2) signal and write
(WR) signal.
Data strobe (DS!, DS2)-The data strobe inputs (DSI and DS2) must be connected toget:her..·This
input receives timing information for data transfers. During a writeeycle; the CPU asserts the data
strobe signal when valid output data is availableanddeasserts the data strobe signal before thedara
is removed. During a read cycle, the CPU asserts the data strobe signal and the Octal ARTtliansfers
the valid data. When the data strobe signal is d~rted; DL<7;O> becQme a blghim,pe4ance.
Write {ft).-,;.The write (\VR) signal specifies thed~ion of data transfer on the DL < 7:0:> pins
by controlling the direction of their transceivers. It the WRsigna! is asserted during a data transfer
(the CS, DSl, and DS2 signals asserted), the Octal ART is receiving data from DL<7:0>. Uthe
WR signal is deasserted during a write data transfer, the Octal ART is driving data onto DL < 7:0> .
Interrupt Request
mQ)- The IRQ pin is an Gpendramoutput. The integral interrupt scanner
asserts the IRQ signal when it has detected· an interrupt condition on one of the eight serial data
lines.
Intel'1'Upt request
3-5
...
Preliminary
78808
Interrupt request ti'8nsmit/rec:eive (IRQ1'xlb)-This signal indicates when the interrupt scanner
in the Octal AIa' stops and asserts IRQ because of a transmitter interrupt condition (the IRQTxRx
signal is asserted) or because of a receiver interrupt condition (the IRQTxRx signal is deasserted).
The signal is valid only while IRQ is asserted. The state of IRQTxRx signal also appears as bit 0 of
the interrupt summary register.
Interrupt request line Dumber (IRQLN < 2:0 > )-These lines indicate the line number at which
the Octal ART interrupt scanner stopped and asserted the interrupt request (IRQ) signal. The
number on these lines is valid only while the IRQ signal is asserted. The IRQLN2 is the high-order
bit and lRQLNO is the low-order bit. The state of these signals also appears as hits in the interrupt
summary register: IRQLN2 as bit 3, IRQLNlas bit 2, and IRQLNO as bit 1. Table 3 shows the line
numbers corresponding to settings of IRQLN <2:0>.
Table .} • 78808 Interrupt Request Line Asignments
IRQ Line
1
2
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
1
1
Line
0
1
2
3
4
5
6
7
Serial Data
'llansmit data (TxD<7:0> )-These outputs transmit the asynchronous bit-serial data streams.
They remain at a high level when no data is being transmitted and a low level when the TxBRK bit
in the associated line's command register is set.
Receive data (RxD < 7:0> )-These lines accept asynchronous bit-serial data streams. The input
signals must remain in the high state for at least one-half bit time before a high-to-low transition is
recognized. (A high-to-low transition is required to signal the beginning of a "start" bit and initiate
data reception:)
Modem Signals
Data set ready (DSR < 7:0> )-These eight input pins, one for each serial data line on the 78808,
are typically connected via intervening level converters to the dataset ready outputs of modems, A
TTL low at a DSR pin causes the DSR bit (bit 7) in the corresponding line's status register to be
asserted. A TTL high at a DSR pin causes the DSR bit in the corresponding line's status register to
be deasserted. A change of this input from high-to-low, or low-to-high, causes the assertion of the
data set change (DSCHNG) bit that corresponds to this line in the data set change summary
register. Changes from one state to the other and back again that occur within one microsecond
may not be detected.
.
3-6
Confidential and Proprietary
78808
Carrier detett (DCD<7:0> )-These eight input pins, onefor each serial data line of the Octal
ART, are typiciilly connected through intervening level converters to the receivecl line signal detect
(also calledcatrier detect) outputs of modems. A TTL low at a DeD pin causes the DCD bit of the
corresponding line's status register to be deasserted. A change of this input from high-to-Iow, or
low-to-high, causes the assertion of the data ~ change (DSCHNGlbit corresponding to this line in
the data set change summary register. Changes from one state to the other and Qa¢kagain that
occur within one microsecond may not be detected.
General Control S~s
,
.
Ready (RDY)-TheRDY pin is an open drain output. Upon detecting a negative transition of chip
select (CS), the Octal ART asserts the RDy signal to indicate ~diness to take part in data transfer
cycles. The'RDY signaldeasserts after the trail.ing edge of CS.
Reset (ltESET)-Wht:n tl::t~RE.$Et input is as~ted, the TxD <}:o > lines are asserted and all
internal status bits listed in the "Architecture Sutnmary"discu~si~n are cleared.
Manufacturing reset (MRESET)-This sigrud is. tor1lllmufact~ USe only and t~ input should
be connected to ground' for normal operation.
.
.
MisceOaneous Sigruds
Clock in (CLIC)-Allhaud rates and internal clocks are derivedfJ.'()Jtlthis input. Normal operating
frequency is 4.9152 MHz ±O.1 percent anddutycycie is 50perce'nt ±5perw;:ent.
Power and Ground
Vol. (VDI»-Power supply5Vdc
Ground (Vss)-Ground reference
• Architecture'Summary
The Octal ART functions as a serial-to-parallel, paralle1-to--seriaLconverter/conrrolleL: It can be
programmed by a microprocessor to provide different characteristics for each of its eight serial data
lines (stop bits, parity. character length, split baud rates, etc.).
Each serial line functions the same as a one-line DART-type device thereby reducing the number of
chips and conserving space on communication devices that require mwtiple communications lines.
An integral interrupt scanner checkS for device interrupt condidonson the eight lines. Its scanning
algorithm gives priority to receivers over tra~rs. The s~er can also check for interrupts
reswting from changes in modem control signals DSR and 0CI5.
Line-specific Registers
Each of the eight serial data lines in the Octal ART has a set of reglstet'Siorbuffering data into and
out of the line and for external control of the line's characteristics•..Theseregisters are selected for
access by setting the appropriate address on lines ADD < 5:0> . Lines ADD< 5:3> select one of
the eight data lines. Lines ADD < 2:0> select the specific register for that line. Refer to Table 2 for
the register address assignments.
Receiver buffer register-Each line's receiver consists of a character assembly register and a twoentry FIFO that is the receiver buffer register. When the RxEN bit in a line's command register is
set, received characters are moved automatically into the line's receiver buffer as soon as they have
been deserialized from the associated communications line. When there are characters in this
FIFO, the RxRDY bit is set in the status register for the line.
Confidential and Propriewy
3-7
...
78808
The assertion of the RxRDYsigfUli for a line that already has the RxIE bit of iucommand register
set causes the interrupt scanner logic to stop and generate an interrupt condition (the IRQ signal is
asserted). When the receiver buffer is read, the interrupt condition is cleared (the IRQ signal is
deasserted) and the interrupt scanner resumes operation.
1£ there is another entry in a line's FIFO, the RxRDY bit remains asserted. When the interrupt
scanner reaches this line again, the assertion of RxRDY causes the scanner to halt and assert the
IRQ again.
Asserting the RESET signal or clearing the RxEN bit initializes the receiver logic of Octal ART. The
RxRDY £lag is cleared and the receiver buffer register outputs become undefined. Any data in the
FIFO at that time is lost.
Transmitter holding register-Each line has a writable transmitter holding register. When the
TxEN bit in the line's command register is set, characters are moved automatically from the output
of this register into the transmitter serialization logic whenever the serialization logic becomes idle.
When this register is empty, the TxRDY bit in the line's status register is set. If the transmitter
interrupt enable (TxIE) bit in the line's command register is also set, the interrupt scanner logic
halts and generates an interrupt condition. If a character is then loaded into the register, the
interrupt is cleared and the scanner resumes operation.
Assertion of the RESET signal initializes the transmitter logic of the Octal ART. The TxRDY £lag is
cleared and the transmitter holding register's contents are lost. The transmitter enable (TxEN) bit
in the line's command register is also cleared by RESET. If at the end of the reset process, the TxEN
is reasserted and TxRDY bit is reasserted. Software dearing of TxEN alone produces results
different from the full RESET in that the transmitter holding register's contents are not lost; they
are transmitted when TxEN is set again.
Status register-Each line has a read-only status register that provides information about the
current state of the given line. This register indicates a line's readiness for transmission or reception
of data and flags error conditions in its bit fields. Figure 3 shows the format of the status kgister.
Table 4 lists the £lag bits in each status register.
7
6
5
4
3
2
o
I I I I I I I I I
eSR
DCD
I
I
FER
ORR
PER
TxEMT
R"R DY
TxRD y
Figure 3 • 78808 Sf4tus Registers (Line 0-7) Format
3-8
Confidential and Proprietary
-
PIeIim··.•mary
1'.aWe 4 • 78808 S.tus Registers (Lines 0-1) Description
Bit
Description
7
DSR . Successive access operations (pither read or write, in any combination)
alternate between the two registers at that address by use of an internal pointer. The first operation
addresses modt:! register 1, the next address mode register 2, and another after that would recycle
the pointer to modefegister 1. The pointer is reset to point tomode register tby RESET or by a read
of the command register for this line.· These registers should not be accessed by bit-oriented
instructions that do read/modify/write cycles such as tbe PDP-ll BIS, BIC, and BIT instructions.
Figure 4 shows the format of mode registers 1 and Table 5 describes the function of the register
information.
6
7
5
4
3
2
o
S T O P - - -.....
PAR C T R l - - - - - - - '
CHAR LENGTH - - - - - - - -...
RSRV-------------------------~
MCIE
_ _ _ _ _ _ _ _ _ _--:-_ _ _ _ _....J
Figure 4· 78808 Mode Registers 1 (Line 0-7) FOlmat
Table 5 • 78808 Mode Registers 1 (Lines 0-7) Description
Bit
7,6
Description
.. STOp......These bits determine the number of stop bits that are appended to the
transmitted characters as follOW\. These bits are cleared by asserting the RESET
input.
Bits
7
0
0
1
1
5,4
Stop Bits
6
0
Invalid
1
1.0
1.5
2.0
0
1
PAR CTRL (Parity contro1)-These bits determine parity as follows and are cleared
by asserting the RESET input. X= either 1 or O.
Bits
Parity Type
5
4
1
1
1
o
X
3-10
o
Even
Odd
Disabled
Confidential and Proprietary
....
•188M
Bit
Desedption
.3,2
CHAR LENGTIi (Character length)-These bits determine the length (excluclltlg
stlUtblt. parity, and stop bits) of the. characters receivedlPidsent. Received
characters o£less dUlt} 8 bits are "right aligned"iq. the receiyer buffer with unused
high-order ~i~~,equal to zero.Par!ty bits .are not shO\Vn in the ~~ver buffer. The
charaCter leD&th bits are cleared by asserting tlte ~mput. The character
length bits are defined as follows: .
Bits
Bit Length
3
2
005
016
107
1
1
8
1
RS,RV (Rese~ ~nd cl~d by asserting the REm input.)
o
MCIE (Modem control inte;m1pt enable)-When set and ,RxIE (bit 5) of the
command register is set, the modem control in~pt,s are,enabled. Refer to the
Interrupt Scanner and Interrupt Handling infoqnation. Cleared by asserting the
~input.
Figure 5 shows the fo~t of Dl9de~ters 2. ~ ',lilble 6indic~testh~ b~ll4ra(e~e<;ti()ns of the
register. Bits 7 through 4 of in?d~re~~2 conti:9Itpe ~m\~~U4'~ ~ bi~s 3 tljough 0
control the receiver baud rate. These registers are cleared by wiserrlngREminput.
7
6
I
11+
T
XMIT RATE
RECV RATE
3
4
6
I
0
2
I
I
I
1
Figpre 5- 78808 Mode Registers 2 (Line 0-7) Format
.,
,
-
Confidential and. ~prietary
3-11
...
Preli.miriary
78SQ8
Thble 6 • 78808 Mode Registers 2 (Lines 0.7) Description
Bit
Descriptior;t
7:0
XMIT RATE/RECV RATE (Tmnsmitter/Recever Rate)-Selects the baud rate of the
transmitter (bits 7:4) and receiver (bits 3:0) as follows:
Receiver Bits
2
1
3
Uansmitter Bits
7
6
4
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
Nominal
Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
0
Actual
Rate
Error*'
(percent)
same
same
109.09
133.33
0.826
0.867
same
same
same
same
1745.45
2021.05
3.03
1.05
'Same
3490.91
3.03
same
6981.81
3.03
same
same
*1be frequency of the clock input (ClK) is 4.9152 MHz. The clock input may vary by 0.1 percent.
This variance results in art error that must be added the error listed.
Command register-These read/write registers control various functions on the selected line. Figure
6 shows the format of the command registers and 'Table 6 describes the function of the register
information.
6
7
5
4
3
2
0
I'---v--'
I I I I I '\ I I
OPER
RxlE
RERR
MODE~
TxBRK
RxEN
TxlE
TxEN
Figure 6 • 78808 Command Registers (Line 0-7) Format
3-12
Confidential andProprierary
18808
1Ab1e ,. 78808 Command Registers (Lines 0.7) Desuipdon
7,6
OPER MODE (Operating mode)-These bits control the operating mode of the
channel as follows. Thesebit!'~ cleared by asserting the RESET input.
Bit
Operating Mode
7
6
o
o
0
Normal operation
1
1
0
1
1
~tomalk echo
Loc~loopbll\ck
~motecloop~
5
IWE(ReCeiver interrupt enable).--When set,·the RxlillYfiag (bit 1) of the ~tatus
register for this linewill generate an interrupt.
4
RERR(Reset error)~When set,
bit clears ilietnmrlngerror,overrun error, and
parity ettar ofthe status register associated With this line. This t)it must be cleared
before errorS that occur wil:lpe reccirded in the St:afuSregistet This bit is cleared by
assertl:ngthetrnm"rinput(IlDtse1£-dearing).
.
3
r~RK (lhmsmit break)set, this I*£orces thea,ppropriate rJ(p<:;:o >
line to the. !lpaclng staj;eat the: conclusion of the character presently being
transmitted,. Whefl the.prOgnw;t~thi~ bit, norm.aloperationis restored, ~d
any character pending in the ttansmitterholding register is moved into the
serialization logicarultrarlsmitted: .The minimum break length obtainable is twice
. the cllaractet lengthplml bit tillie,Themaltlmum breakle~th depends on the
amo.unt of time between theprO~settirig arid dearing dlisbit, buds anin~ral
number of bit times. This bit is Cle!ttecl by asserting the·~ input.
2
this
when
RxEN (Receiver enable)- When set, this bit. e~les the receiver I~gic. When
cleared, it stops the assembling of the received character, clears all receiver error bits
and the RxRDY (bit 1) of the status register; clears any receiver interi:upt conditions
associated with this line, 'and initializes an recei'ver logic. This bit is cleared by
asser5a~theImm input;"
1
TxIE(Tnmsmit il)ter~pt enable)-\Vhen set; the~~~ of the associated TxRDY
flag (hit 0) Q~ the s~tus reg~ster i~ mad~available to .~ interrupt scatuler logic.
When the interrupt scanner logic scans this llne, it deternunes if the T~RPY flag is
. asserted and generates an interrupt by asserting We IRQ s~nal.
o
T:!{EN, (Transmitter enable)-:-When set, this hit enablesi · the transmitter lo~ic.
When. cleared,. it inhibits the sedalization of the.chamcters that follow but. the
serialization of the current character is completed. It also clears the TxRPyflag(bit
0) of the status register, dears any trarlsmitter interrupt conditions associated with
this line, and initializes all transmitter logic except that associated with the
transmitter holding register. The character in the transmitter holding register is
retained so that XON/XOFF situations can be properly processed. This bit is cleared
by asserting the RESET input.
Confidenti~ and
Pn;)p!ietary
3-13
_0
7~08
Bits 5 through 0 enable theJ.i.ne's receiverll,nq, ttalilStn,itter, ep.able handling of interrupts, initiate
the transmission of break characters, and ~set error bits fe>t the line. Refer to "Interrupt Scanner"
and "Interrupt Handling" paragraphs for detailed interrupt information. Bits 7 and 6 control the
operating mode of the line. The four modes that can be set are
• Normal operation-The serial data received is assembled in the receiver logic and transferred in
parallel to the receiver buffer register. (The RxEN bit must be set.) Data to be transmitted is
loaded in parallel into the transmitter holding register, then automatically transferred into the
transmitter logic and serialized for transmission. (The TxEN bit must be set.)
• Automatic echo-The serial data received is assembled into parallel in the receiver logic (the
RxEN bit must be set) and transferred to the receiver buffer register. Arriving serial data is also
routed to the line's TxD < n> pin for serial OUtpllt. TxEN is ignored and the transmitter logic is
disabled. TxRDY flags and TxEMT indications are cleared. No transmitter interrupts are
generated.
• Localloopback-The serial data from the RxD input is ignored and the receiver serial
input receives data from the transmitter serial output. That data is assembled into parallel form in
the receiver logic (the RxEN bit must be set) and transferred to the receiver buffer register where
it can be read by the program. Data to be transmitted to the receiver is loaded in parallel form into
the transmitter holding register from which it is automatically moved into the. transmitter logic
and serialized for transmission. (The TxEN bit must be set.) The transmission goes only to the
receiver serial input; the TxD < n > output is held high. As in normal operation, transmission
and reception baud rates are controlled by the transmitter speed and receiver speed entries in
mode register 2.
• Remote loopback-The serial data received on the RxD < n> line is returned to the TxD < n>
line without further action. No data is received or transmitted. The RxRDY, TxRDY, and TxEMT
flags are disabled. The. TxEN and RxEN bits of the command register are held cleared, causing
the transmitter and receiver logic to be disabled.
.
Summary Registers
The Octal ART contains two registers that summarize the current status of al,l eight. serial data lines,
making it possible to determine that a line's status has changed with a single read operation. These
registers are selected for access by setting the appropriate address on pins ADD<2:0>. Because
the registers are shared by eight serial lines, the line-selection bits (ADD < 5:3 > ) are ignored when
these registers are accessed. Refer to "Interrupt Scanner and Interrupt Handling" for detailed
interrupt information.
Interrupt su~ register-This read-only register indicates that a transmitter or receiver
interrupt condition has occurred, and indicates the line number that generated the interrupt.
Figure 7 shows the format of the interrupt summary register and Thble 8 describes register
information.
3-14
Confidential and Proprietary
-
7
6
3
4
o
2
IRQ - - - '
R1
>NO
.Z
-_
- -_
- -_
_ _ _ _ __
IN.T
LINE
_
Tli:/Rx " " " - - ' - - - - - -......._ _ _...:..._ _ _.......- 1
Figure 7· 78808 Interrupt Summary Register Format
'lllbJe8· 78808 InterroptSJlminaty Re~De$C1'iption.
,
'.
:-#,'
'
Bit
Desctiption
7
IRQ (Interrupt request)-When set, this bit indicates that the interrupt scanner
has£ound an interrupting C:;~1l $UOOngJ~ftightse.riallines o£the Octal ART.
These conditions also mult in the Octal A;RJ',alIserting the IR signals~(bit·~3 ... IRQLN<2>, bit2=IRQLN<1>, and bit
1 =IRQLN< 0> . Refer td'fab1eJ:
0*
Tx/Ri {Transwit/rece~ve)~,this bit ~nd,icates, }V~thrrt!te intem1pting conditiQn
was ,caused by a ttansmitter(T#$ieq~als 1) ora~eiver (Tx/lXequaisO).this bjt
corresponds to the IRQTxRx signal of the Octal ART and is setwhen IRQTxRx is ,
asserted.
'
..
*Bits 3-0 above represent the outputs of a£ree.n,mnmg counter
and are vaIid only when bit 7 is set.
Data set change summary register-When the DSR or i5Ci5 inputs that areassociated·witha line
change state, the bit corresponding to that line in this read-only register is set. The
state of
the DSR andDa5 inputs can then be obtained from that lineutatusregkter. If the state oia line
changes twice within one microsecond, The change instate'maynot be detected. Figure 8 shows
the forIIlllt of the dataset change summary registet. '
current
6
OSCHNG 1-0
5
4
3
2
!
1
0
I
I
Figure 8· 78808 Data Set Change Summary Register Format
Confidential and Proprietary
3·15
78808
When the MCIE bit in a line's mode ~giSter 1 is ~etandRxlE is also set, the modem control
interrupts are enabled for that line. If DSCHNG forthat line is then set, the interrupt scanner will
halt and assert the IRQ signaL The data set change summary register bits are cleared by writing a 1
into the bit position. A program that uses this register should read and save a copy of its contents.
The copy can then be written back to the register to clear thebits that were set. The system
interrupts should he disabled and writeback should directly follow the read operation.
Assertion of the RESET signal disables and initializes the data set change logic. When the RESET
signal is deasserted, future changes in DSR and DCD are reported as they occur.
• Interrupt Scanner and Interrupt Handling
The interrupt scanner is a four-bit counter that sequentially checks lines 0 through 7 for a receiver
interrupt (counter positions 0-7) and then checks the lines in the same order for a transmitter
interrupt (counter positions 8-15). If the scanner detects an interrupt condition, it stops and the
IRQ signal is asserted. An interrupt must be serviced by software or no other interrupt request can
be posted.
The scanner determines that a line has a receiver interrupt if the line's receiver buffer is ready and
receiver interrupts are enabled for that line (RxRDY and RxIE= 1) or either of the line's modem
status signals has changed state and both receiver and modem control interrupts are enabled for
that line (DSCHNG and RxIE and MCIE= 1).
The scanner determines that a line has a transmitter interrupt if the line's transmitter holding the
register is empty and transmltter interrupts are enabled for that line (TxRDY and TxIE = 1).
When the scanner detects an interrupt, it reports the line number on th~ IRQ < 2:0 > lines. The
· IRQTxRx signal is asserted for a transmitter interrupt and deasserted for a receiver interrupt. The
appropriate bits are also updated in the interrupt summary register. The IRQ line is deasserted and
the scanner is restarted for each of the following three types of interrupt conditions.
• Reading the receiver buffer or resetting the RxIE bit of the interrupting line for the first type of
receiver interrupt previously described.
• Resetting the MCIE, RxIE, or DSCHNG bit of the interrupting line for the second type of
receiver interrupt previously described.
• Loading the transmitter holding register or resetting the TxIE bit of the interrupting line for
transmitter interrupts.
If the scanner was originally stopped by a receiver interrupt condition, the scanner resumes
sequential operation from where it stopped, thus providing receivers with equal priority. If the
scanner was stopped by a transmitter condition, the scanner restarts from position 0 (line O's
receiver), thus giving receivers priority over transmitters.
• Edge-triggered and Level-triggered Interrupt Sys{f:ms
If the interrupt system of the Octal ART is used only for generating interrupts for thee RxRDY and!
or TxRDY flags, the IRQ line can be connected to a processor having either edge-triggered or leveltriggered interrupt capability. If the modem control interrupts are being used (Me IE in mode
register 1 = 1), the IRQ line can be connected only to a processor that uses level-triggered
interrupts.
3-16
Confidential and Proprietary
. Modem Handling
The TxEMT (transmitte:tempty) bit of the status register is typically used to indicate when a .
program can disable the transmission medium, as when deasserting the request-to-send line of a
modem. A typiCal program will load the last character for transmission and then. monitor the
TxEMT bit of the status register.
The assertion of the TxEMT bit to indicate that transmission is complete may ~r~substantial
time after the loading of the last character. Mter the last character is loaded, oni~r is in the
transmitter holding register and one character is. in the seri~tion.lggic. Theref6~~ will be t.wo
character times before the transmission process is completed.;~iting for theJf:xRDY signal tQ ..
assert before monitoring the TxEMT status shortens this by OOetl:hatacter time because the TxRDY
status bit indicates that there are no characters in ,the trlinsmitterholding register. The times
involved are calculated by taking the reciprocal of the bauciratebeing used, multiplying by the
number of bits per character (a start bit-5,6, 7,or 8 datibits;p}b$.parity bit if enabled; and 1, 1.5,
or 2· stop bits), .and multiplying by either two cnaractets or one, .depending on wh~ TxEMT
monitoring begins.
.
..
.
it
• Specifications
The mechanical, electrical, and environmental cliaracterisli!;S~;~ci£icatiqnll~;thebctal ART
are described in the following paragraphs. The test condit~pns for the electriclljtv:a1ueslll'e as follows
unless specified otherwise.
• Power supply voltage (VDD): 4.75 V to 5.25 V
Mechanical configuration
The physical dimensions of the 68-pin package are contained in Appendix E.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may iidversely affect the
reliability :of the device.
• Power supply voltage (V00): 7.0 V
• Input or output Voltage applied: -5 V to 7.0 V
• Storage temperature: -65~C to 125°e
Recommended Ope..atingConditions
• Power supply voltage (VDO): 5 V ± 5%
de Electrical Characteristics
The de eIe(;'trical characteristics of the Octal ART for the operating voltage and temperature ra~s
specified are listed in Table 9.
..
Confidential and Proprietary
.
3-17
-
78808:
Table 9· 78808 de Electrical Characteristics
SymbolParameter
Test Condition
Requirements
Min.
High-level
MAX.
2.0
V
input voltage
Low-level
0.8
V
input \T91tage
High-level
output voltage
Vr)D =Min.
loH=-3.5 rnA for DL<7:0>.
loH=-2.0 rnA for all
remaining output except
YRQandRDY
Low-level
VDD=Min.
output voltage
lot =5.5 rnA for DL< 7:0>
V
2.4
0.4
V
loL == 3.5 rnA for all
remaining outputs
loZLl
Input current
at maximum
input voltage
VDD"" Max.
VI =V DD (Max.)
Input current
at minimum
input voltage
VDD=Max.
V1 =0.0 V
Short-circuit
output current
forDL<7:0>
all remaining
outputs except
IRQandRDY
VDD=Max.
Three-state
output current
VDD=Max.
Vo =O.4 V
10
~
VDD=Max.
Vo=2.4 V
10
IlA
output current
VuD=Max.
T,,=O°
240
rnA
10
-10
-50
-180
rnA
-30
-110
. rnA
IDD
Supply current
C..
Input
capacitance
4.0
pF
CIO'
Input/output
capacitance
5.0
pF
iNo more than one output should be short circuited at a time and the duration of the sh?rt should
not exceed l$econd. .
. . . .. ..
.
..
. ..
.
ZAll three-state output drivers are wired in an I/O configuration. The paranleters include the driver
and input receiver leakage currents.
.
'The parameters include the capacitive loads of the output driver and the input receiver.
3-18
Confidential and Proprietary
--
•ae.JiIectrical ~
Thedevke propag~ndelays specified in theac characteristicsfigures;ind tables asstinie
loading ConditiOns
in Figure 9.
. ' .
shawn
TEST
POINT
the
V DD
VDD
Ikn
2.7kci·
Ikfl
FROM
OUTPUT >--.l.----'-""\""~II__f
'USED ONLY FOR
IRQ
and iiijf.
"
",. -".
L.OAD A - STANDARD OUTPUTS
TEST
POINT
FROM
OUTPUT
S1 CLOSED: PULL UP
·... saCLOSED: PULL DOWN
S1 ANQ~2CLOSEO:DIVIDER
LOAD B - THREE-STATE OUTPUTS
Figure 9· 78808 Output Load Circuits
3-.19
-
'1880tr
Preliminary
rmung
' Parameters
....
Figure 10 shows the signaltirning for a read cycle: to tt:ansfednformation from the OctalART to the
processor. Figure 11 shOws the signal timing· for a write cycle. to transfer informatio~ from the
processor to the Octal ART. Table 11 lists the timing parameters for the read and write cycles.
1'\
DS11DS2
~tDPWLR_
ADD<5:0 >
WR
XI
I.-
tASU
.IL
f-tWSU
tOPWH
IX
VALID AOORESS
1.-.1- tAHO
1\
.,j.::"tWHo
~
.;
tcsu
tCHO
'\J
tRDL
OL<7:0>
t-tRDH
XI VALID DATAOUTfl
f-FoDZL, tODZH If_tDF--I
tOOLZ, tODHZ
I-tDD-l
I
I
"""-tiD
Figure 10· 78808 Bus Read Cycle Timing
3-20
Confidential and Proprietary
X
-
Preliminary
78868
DSlfDS2
~----tDPWH----- _ _ _''I--++-_,;...-_.......;..++---f _ _ _ _ _ _ _ _ _ _ _ __
Ol<:7:0 >
-----t-i:=~:§:~~c:::J~-----------
Figure n . 78808 Bus Write Cycle Timing
Reguiremtrnts
tAUO
t,uu
Hold time ofa valid ADIlO;::: 5:0 >to a valid high level of
DslandDS2.
tau
Load
Circuit'
10
Setup time of a valid ADD < 5:0> to the falling edge of
mand~.
tcuo
(us)'
Mm.~.
30
Hold time of a valid low leveIof CS to a valid, high level of
mand~.
10
Setup time of a valid low level of CS to thefalling edge of
Dsf and DS'2.
30
Propagationde1ayo£ avalid low level on i5SI and'~ (if
data on
DL<7:0>.
CS is low and WR is high) to valid high or low
Confidential and Proprietary
165
C L = 150 pF
}·21
...
Symbol Definition
tuou
2
tuum:
Requirements
(ns)
Load
Min. Max.
Citcuitl
m
Propagation delay of a valid high level on
and D'S}
(if CS is low and WR is high) to DL<7:0> output
drivers disabled.
50
50
60
60
65
65
tuuu
tuum:
t oDU
toouz
tuDLZ
tDuHZ
tDDZL
Propagation delay of a valid low level on I5SI and ~ (if
toDZH
CS is low and WR is high) to DL<7:0> output driver
CL =50 pF
CL =50 pF
CL = 100 pF
CL = lOOpP
CL = 150 pF
~=150pF
enabled.
0
0
toDZL
t uDm
top
t ono
tOI'WH
tOPWLll
tDI'WLW
tosu
Hold time provided during a read cycle by Octal ART of
valid high or low data on DL < 7:0> after the rising edge
of DS1 and DS2.
Hold time of a valid DL<7:0>
DSI and DS2.
to
0
a valid high level of
30
Pulse width high of DS1 and DS2.
450
Pulse width low of DSI and DS2 when WR is high (read
operation). Refer to timing parameter tOPWLW also.
180
10,000
130
10,000
m
Pulse width low of
and W when WR is low (write
operation). Refer to timing parameter tOPWLII also.
Setup time of a valid DL < 7:0 > to the falling edge of
I5SI and DS2.
tID'
130
Propagation delay of a valid low level on DS 1 and DS2 (if
CS is low) to a high level on IRQ.
tlIDH4
635
tYHO
t wsu
210 CL =50 pF
Propagation delay of a valid low level on CS to a valid low
level on RDY.
Hold time of a valid high or low level of WR to a valid
high level of
and ~.
m
Setup time of a valid high or low level of
falling edge of DSI and DS2.
90 CL =50pF
10
WR to the
lRefer to Figure 9 for the load circuits used with these measurements.
3-22
CL =50pF
Propagation delay of a valid high level of CS to a valid
high level on RDY.
t ROL
165 CL =150pF
165 CL =150pF
Confidential and Proprietary
30
-
2The toDLZ and t _ ~rs are measUred wi,th .Cx. == 150 pF. The values of tDDLZ and tDDHZ for
CL ... 50 pF and C.. -lqO pF have been derived for user convenience.
.
'Total rise time depe~ion i.nternaldelay plus the pullup delay introduced by the external resi$toi'
being
Thetm puUneter can be calculated by the foll~: tm == 500 + R~ where R= value of
the resistor that conned:s to eapacitor Cx. in load A, Figure 9.
4Total rise time depends on internal delay plus thepullupdelay introduced by the exte~resistor
being used. The taDH parameter Can he calculated by the follQWiQg:l_= 75 +RCLwhere R ... value
of the resisror that connects to capacitor CL in load A, Figure 9.
used:
Figures 12 shows the signal timing for the clock inpll~,interrupt ~,effectof the RESET input
on data strobe, data set carrier detect (DG:D)'andiMta sef~t(DSRlinput tittting:, andtbe
transmit data output timing. Thble 11 lists the timing l?arameters~rFigures 12.
ClK
~tCPWL:r1.
i
\
tcP
i;CPWH}
/
I
\
CLOCK
',," ~.
IRO
AESET
~"~~
~;
IRQLN <2:0> • ROTxRx
1 _
1·
051/052
INTeRRUPT
tRES
tORSU
~.
tORHO
.~
EFFECT OF RESET ON DATA STROBE
XI
pc;
------''to
I.:':':':' ';'-' ;'-;;';-;;';t'';'os-pw--';';'_...._...._-_-_-_-_-f~~""----------
OCO/DSR<7:0>
VALID OCD/DSR OATA
DCD/DSR IN PUT
TxD< 7:0>
\"'~--t-TX-S-K--~.LtTXSKJ,--------,rTRANSMIT DATA OUTPUT
Figure 12· 78808 Miscellaneous Signal Timing
Confidential and Proprietary
,3·23
..
_
.Preliminary
18808
Table· U ·78808 Miscellaneous W!iteTnninB Parameters
8,.bol De6nition
Requirements (os)
Min.
tcp
Period of eLK.
tc.wa
Pulse width high of eLK.
95
t"awr.
Pulse width low of eLK.
95
t lWlO
Hold time of a valid high level of DS 1 and DS2 to
a valid high level of mET.
1,000
Setup time of a valid high level ofm and DS2 to
the rising edge of RESET.
900
Pulse width high or low of DeD < 7:0> and
DSR<7:0>.
1,000
Hold time provided by Octal AlIT from !l valid
IRQLN<2:0> and IRQTxRx to a valid high
level of IRQ.
100
Setup time provided by Octal AlIT from a valid
IRQLN <2:0 > and IRQTxRx to a valid low level
of'iRO.
100
tlleSU
tllSPW
t mo
t lSU
Load
Circuitl
203.45 (4.9152 MHz)
tllll5
Pulse width low of RESET.
1,000
tTXSIC
Pulse width high or low provided by Octal ART
on the TxD < 7:0> lines. At each baud rate, the
actual pulse widths provided vary by tTXSK ' This
timing parameter should be used to determine
cumulative reception/transmission errors.
±250
*Re£er to Figure 9 for the load circuits used with these measurements.
:3-24
Max.
Confidential and Proprietary
-
CL =50pF
CL =50pF
-
CL =50pF
Figure 13 shows the input and output voltage waveforms for the propagation delay and setup and
hold measurements. Figure 14 shows the waveforms for the three-state outputs measurements.
VIH (2.4 V) - -__
2.0V-----INPUT STROBe 0.8 v ____ _
--~--~-.--
Vll10.4 V)
INPUT DATA
SET·UP AND HOLO
PROPAGATION DELAY
Figure 13· 78008 Propagation Delay and Setup and Hold Voltage Wave/orms
Confidential and ,Proprietary
,",'f
...
_.................
n ....''''.
iB_~~"'!'I'&f''''i!UM
.....m_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _•_ _,.___ ,___ .__
"""'HiI~_
3-25
-
78808
Villi 12.4'1)
2.0 V
.
OUTPIJTCONTllOl
O.BV
V'LI0.4V)
-
---f
l
'Zl (NOTE 3A)
(NaTE3C)
VOH (4.5 V)
-
- - VOL +0.5 V
--~r-'
VOUT (AS MEASURED)
VOH -0.5 V
-t-:r----_r
(NOTE 3C)
-- -
1.5'1
OUTPUT VOL (NOTE 2)
(0.0 V)
VOH -0.5 V
1.5 V
THREE-STATE OUTPUTS
NOTES:
1. INTERNAL CONDmONS ARE SUCH THATTHE OUTPUT IS LOW EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROL
2. INTERNAL CONOITIONS ARE SUCH THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROL.
3.
REFER TO FIGURE 9. A
z
SI CLOSED. B - 52 CLOSED. C = SI ANDS2 CLOSED.
Figure 14· 78008 Three-state Output Voltage Wave/orms
3-26
Confidential and Proprietary
.Featum
• Hardware cOmpatible with Digital's DLU series oflriterfates
,
• As~~operation
• Internal baud rate generation £toni :300 baud t'0 38Ak PaUd, "
• Four realtime clock interrupt outputs.
• One stop bit only
• Common baud rate for both transmitter and receiVer
• Single 5-volt power supply
• Single TTL clock
. Desclption
The DC319-AA is a Digital Link (DL11) compa:ti~le, asynchroI1~u$receiver/transmitter (DLART)
designed for data communication betweenDi8ftal's micropl:OC¢Ssorsand console terminals or
communication devices. The DC319·AA,..faprica~ using N-chanD.e~ MOS silicon technology, is
contained in a 40-pin dual-in1ine (QIP) ~ge, tJmt can be W~vet)ietUly installed on a microprocessor module or interface modulerFigure 1 is a block diagrant6ftn,e DC319-AA DLART.
r-
DAl<15:0>
<'"
""./
DATA
BUS
BUFFER
A
A
"-
t'
t'
~ ....
vi
'-r INTERNAL
16 BIT
+
"
V
i.
OR
FlSUF
SHIF~Rt;G' ....
DATA BUS
A2_
RCSfl
(S ':':PI
AlAO-
REC~IVfR
COIii!ROl
Cs'----c
REGISTER
ACCESS
CONTROL
Rri----c
U
.'
A";
wui----c
~
INIT-
-..,;
TEST-
")
V
'.
BAUD
RATE
CONTROL
SI
XMIT
IRQ
76,8KHZ
800HZ
BRS'----c
60HZ
50HZ
BRsO--C
Figure 1 • DC319-AA DLART Block Diagram
____
BRKIRO
~CSR
MITTER
CONTROL
BRS2----C
RCV IRQ
XBlJR
:. TRANS:
PBRi---c
SO
MAINTENANCE
OR
SHiFT REG
(P-S)
CLK-
-
.........,,_ _ _ .!
~...".._
~_11
'iI'!I
DC319
The DLART is pro~rnmedby the CPU to ()~ in either g-bit or 16-bit mode with asynchronous baud rates Varying from 300 to 38.4k. The DLART accepts data characters from the CPU in
parallel format and converts them into an asynchronous serial-data stream for transmission. It
can simultaneously receive serial-data streams and convert them into parallel data characters for
the CPU. The DLART notifies the CPU when it is ready to accept new characters for transmission
or when it has received a character from the serial line. The DLART contains an internal baudrate control to reduce support logic required to select baud rates. It also provides four realtime
interrupt outputs. The CPU can read the complete status of the DLART at any time including the
indication of data transmission errors and the status of control signals. Device address detection,
vector generation. and interrupt arbitration must he provided externally. The DLARTprovicles
the DL-defined internal registers allowing it to operate with Digital software .
. Signal and Pin Descriptions
The input and output signals and the power and ground connections for the DC319-AA 40-pin
DIP are shown Figure 2 and defined in Table 1.
.
AD
Vee
Cs
"Wti3
EiRs2
DALOO
8RS1
TEST
DALO'
RTClK60 (60 Hz)
DAl02
RTCLK50 (50 Hz)
DAlO3
RTCLK77 (76.8 KHzl
DAL04
BRK IRQ
DAl05
elK
DAL06
BRSO
DAL07
SO (SERIAL DATA
DAlOS
XMIT IRQ
DAlO9
PBRI
DAL10
SI (SERIAL DATA IN)
DA' ,
Rev IRQ
DA12
RTClKSOO (800Hz)
DA113
INIT
DAL 14
A2
DAL15
A1
Vss
AO
Figure 2 • DC319-AA Pin Assignments
:3-28
oun
Confidential and Proprietary
Pin
I
RJ.)
input
Read-When asserted while the CS signal is
assel;teel and the '\'WLi'3signal is unasserted, the content of the register selected by the Al, AI, and AO
lines is transferred to the DAL.
2
CS
c;Mp~lect-When~sened whileAOU~serted.
lines are trans£e~ to the register selected the A2 and Al inputs.
input
. the SQPtents of the DAL < 15 :00 >
3
'W'tif
input
Write low byte-When asserted and the AO input is
~, the data on the low byte DAL< 07:00 >
fines is written into the writable bits of the register
selected by the A2.~ Al lines.
19-4
DAt < 1'5:00 >
input/output
n~taaddress
21
AO
input
Regist:er byte select-When asserted, the high byte
of .the register selected by the A2 and A 1 lines is
lineS·!< 15:00 > -Multiplexed bidireCtiOrial data lines.
m,~tiplexedtothelowbyteDAL<07:00>
23
22
A2
Al
fines.
~ter address select-These inputs select the
intertll,ll register that is accessible through the DAL
. lines whentheCSline is asserted;
inputs
A2'"
o
o
At
0
1
1
0
I
1
~
RCSR
RBUF
XCSR
XBUF
24
INITinput
It;dti.alize- This input is used to reset the RCV IE bit
in lheRCSR register, and the XMIT IE, MAINT, and
'XMlTBRK bits intheXCSR register.:
25
RTCLKSOO
output
~me clock interrupt (800 Hz)-This output
PtPvldes an 8oo-Hz, 50% duty cycle signal.
26
RCVlRQ
.output
Receiver interrupt request-This interrupt output is
asserted when both the RCV DONE and RCV IE bits
in.theRCSR are set.'
27
SI
input
Serlalinput-This input accepts an asynchronous
bit serial data stream. The input sigrial must remain
in the high (marking) state for at least one-half bit
time before a high-to-Iow (mark-to-space) transition
is recognized. A mark-to-space transition is required
to determine the beginn.ini of a start bit and to
initiate data reception.
Con£identj.al.and.Ptpp~
3-29
....
Den,
Pin
Signal
Input/Output)"
Definition/Function
28
PBRI
input
Progratnmable baud rate inhibit-This input is
optionally held low externally by a jumper to ground
or held high internally. Holding this line low disables
the software programmable baud rate selection
(clears the PBR2-0 and PBRE bits) but makes the
DLAR DL-software compatible.
29
XMlTIRQ
output
Transmitter interrupt request-This interrupt
request output is asserted only when both the XMIT
RDY and XMIT IE bits in the XC5R are set. This
output can also be cleared externally by being forced
low (clamped to ground) by an open-collector transistor for a minimum of 100 ns after being high for a
minimum of 500 ns.
30
50
output
Serial output-This output provides an asynchronous. bit serial-data stream. This line remains high
(marking) when no data is being transmitted. This
line will remain low when the XMIT BRK bit in the
XCSR is set.
32
CLK
input
Clock in-This input requires a 614.4-kHz,0.1 %
square wave. All baud rates and clocks are derived
from this input.
33
BRKIRQ
output
Break detected interrupt request-This output is
asserted when the RCV BRK bit is set and is unasserted by the TEST input or when the RBUF register
is read. This output can also be cleared externally by
being forced low (clamped to ground) by an opencollector transistor for a minimum of 100 ns after
being high for a minimum of 500 ns.
34
RTCLK77
output
Realtime clock interrupt (76.8 kHz)-This output
provides a 76.8-kHz, 50% duty cycle signal. After
being high for a minimum of 500 ns, this output can
be cleared externally by being forced low (clamped
to ground) with an open-collector transistor for a
minimum of 100 ns.
35
RTCLK50
output
Realtime clock interrupt (50 Hz)-This output provides a 50-Hz, 50% duty cycle signal. After being
high for a minimum of 500 ns, this output can be
cleared externally by being forced low (clamped to
ground) with an open-collector transistor for a minimum of 100 ns.
3-30
Confidential and Proprietary
Pin
Signal
InputIOutput*
Definitioo/Function
36
RTCLK60
output
Realtime clock interrupt (60 Hz)- This output provides a 6O-Hz, 50% duty cycle signal. After being
high for minimum of 500 ns, this output can be
cleared externally by being forced low (clamped to
~) w;ith an open-collector transistor for a mini-
OC)19
milin of lOOns.
38,37,
BRS<2:0>
Baud rate se1ect-Th~ inputs. select the· receiver
and f!'all$mittet baud tateswhen the PBRE bit is
cleaJ;edasfoUows: The inputs are optionally asserted
l()W by~ jumper to gt01itid or held high internally.
input
31
BRS Line
B.ud rate
210
H
H
H
H
H
L
H
L
H
H
L
L
L
H
H
L
H
L
L
L
H
L
L
L
300
600
1,200
2,400
4,800
9,600
19,200
38,400
39
TEST
input
Test-This input is used during modale assembly
and test to disable all DLART outputs. It is also used
in a system during powerup to reset all internal logic.
40
Vcr;
input
Voltage-Power supply voltage.
20
Vss
input
Ground reference
*Inputand output signals are TfL levels.
Confidential and Proprietary
3-31
...
DCl19
Read and Write Control Functions
Table 2 lists the control signalleve1s and transitions required to select the read and write functions of the DC319-AA.
Table 2 • DC319·AA Read and Write Control Functions
Control Signals'"
CS
RD
AO
WiJj
Function
L
L
L
H
Read-Register bits 15:00 to DAL< 15:00>
H
L
L
H
Read-Register bits 15:08 to DAL<07:00>
x
H
L
x
Read-no effect
x
x
L
L
Read-no effect
L
1\
x
L
Write-DAL< 15:00> to register bits 15:00
L
L
x
1\
Write-DAL < 07 :00> to register bits 07 :00
x
H
x
1\
Write-no effect
L
x
x
1\
Write-no effect
*x =either high or low
1\ = low-to-high transition
• Register Assignments
The DLll-definedinternal registers are described in the following paragraphs and are available to
the user to program and monitor the operation of the DC319-AA.
Receiver Control and Status Register
The receiver control and status register (RCSR) controls the operation of the receiver and indicates status. Figure 3 shows the format of register, and the register information is described in
Table 3.
3-32
Confidential and Proprietary
DC'!9
A02
~1
IS
RCSA
"
07
06
00
t;1.==:=~T==::::;3;hj;g~¥1b=?;;::'="
='~R~::§d=::;to:ti!R8~~iJElti'~~i~M;E====~Ro5:~o===:=;13
Figure 3· DC319-AA Receiver Cpntroland Status Register Format
Bit"'
Description
15-12
RAZ (Read as zero)
11
RCV ACT (Receiver active)-A read-Qniy bit set when.the receiver is active. This bit is set
at the center of the start bit, which is thebeSinriliig the inputseriil data and cleared
one bit at a time before the leading edge of RCV DONE or TEST, sign'll.
10.08
RAZ(Read as zero)
07
RCVDONE (Receiver done)-Aread-oruybit set when an entire byte has been received
and transferred to the RBUF register. This bit is cleared by readihgtheRBUF register or by
the TEST signal.
06
RCV IE (Receiver Interrupt Enable)-A read/write bit set under program control. The
RCV IRQ line follows the RCV DONEbitandallows:3Q ~terruptrequ,~t to be made when
RCV DONE is set. This bit is cleared by;t;he INI'f sigQlll.~by the TEST sigt;tal.
05-00
RAZ (Read as zero)
of
Receiver Buffer Register
The receiver buffer (RBUF) register is a read-only register that stores the serial information
received from the device and indicates error status. Figtire4Sho\:Vs thefOrtrultbf the information
in the RBUF register and Table 4 contains a description of the register information.
15
A2
AI
o
I
14
13
12.
11
10
,.
,08.
07
00
Figure 4 • Dc319-AA ReceiVer BufferRegjiter .Format
Confidential and Proprietary
3-33
DC319
Table 4 • DC;J19~AA Receiver Buffer Register Desuiption
Bh
~cdptiQn
15
ERR (Error)-A read-only bit set when the overrun or the framing-error bit is set. It is
cleared by iemovingthe error-producing condition.
14
OR ERR (Overrun error)-A read-only bit set when a received byte is transferred to the
RBUF register before the RCV DONE bit is cleared. An overrun error indicates that
reading of the previously received byte was not completed prior to receiving a new byte.
This bit is updated when byte is transferred to the RBUF register and is cleared by the
TEST signal.
U
FR ERR (Framing error}-A read-only bit set when a received byte without a valid stop bit
is. transferred. to the RBUF register. This bit is cleared by the TEST signal or when a
received byte with.a valid stop bit is transferred to the RBUF register.
12
RAZ-Read as zero.
11
RCV BRK (Received break)-A read-only bit set when the serial-in (SI) signal goes from a
mark to a. space and stays in the space condition for 11 bit times after serial reception
starts. This bit is cleared when the SI signal returns to the mark condition or by the TEST
signal.
10:08
RAZ-Read as zero.
07:00
RCV DATA BUFFER (Received data buffer)-Read.-only bits that store the most recent
byte received. When anew byte is transferred to the RCV DATA BUFFER, the RCV DONE
bit in the RCSR is set. 'These bits are cleared by the TEST signal.
'J1.ansmitter Control and Status Register
The transmitter control and status register (XCSR) controls the operation of the transn;llHer in
the DC319-AA. Figure 5 shows the format of the information in the register and Table 5 contains
a description of the register information.
15
A2
Al
08
07
06
05
04
03
XCSR
o
Figure J ·VCJ19-AA Transmitter Control and Status Register Format
3-34
Confidential and Proprietary
02
01
00
Table ,. DC319·AA liansmittet Control and Status Reptet DeseriptiOO
Bit
I)eseription
15:08
RAZ (Read as zero)
07
XMIT RDY (Transmitter ready)-A read-only bit is set when the XBUF is ready to accept
a byte. This bit is cleared by writing to the XBUF and is set by TEST signal.
06
XMIT IE (Transmitter interrupt enable)-A read/write bit set under program control.
The XMITIRQ llnefollowsthe XMlTRDY. hit and allOWs an interrupt !~st to be
initiated when the XMIT RDY bit. is set. 1'hi.Sbitiscleai-edbythe lNit and TEST signal.
05:03
PBR2-PBRO(Progratnm4ble~~d~te ~l-l~~tt;~ the transmitter baud rate
sdected as follows: These bits are cleared by the TESTOt PfiRl' (programmable baud rate
inhibit) signal. These bits are read-only as zero when the i?BiU input is asserted.
Bit
OS
o
o
o
o
1
1
1
1
02
04
03
Baud rate
0
0
1
0
1
0
600
1
1
1,200
2,400
0
0
1
1
0
1
0
1
4,800
9,600
19,200
38,400
300
MAINT. (Majntenapce).:.-A ~dlwrite kit U$edto£~tateamaWtenapc!'!seJf-test. When
this bit 'is set, the transmitter serial output!isco~to ~ ~iVF serial input. The
external serial input is disconnected. This bit is cle~ by the INIT or TEST signal.
01
PBRE (Programmable baud rate enable)-This bit selects the internal and external baud
rate. When set, the baud rate is determined by the PBR <1:0 > bit in the registet. When
clear, the baud rate is determined by the BRS < 2:0 > inputs. This bit is cleared by the
TEST or PBiti' (programmable baud rate inhibit) signals. This bit is read-oolyas'2ero'when
the PBiti' inpp!:is asserte9. OtheJ:\Vise it is reftd/!-Yrite,
00
. XMIT BRK (Transmit break)--A read/write bit .Set when the .serialoittput (SO} line.is
fol'Cedto a space condition. Thlsobids dem:ed by theftNIT.and TEST signals;.
Confidential and .Proprietary
3-35
-
DC319
Transmitter n.... Bufi;~~ster
..
...
. .
The transmitter data buffer (XBUF) register stores the data in the DC319-AA for serial transfer to
the device. Figure 6 shows the format of the information in the register and Table 6 contains a
description of the register information.
08
A2 Al
XBUF
o
1
!
07
: -k:
Figure 6· DC319-AA Transmitter Data Buffer Register Format
TabJe 6· DC319·AA Transmitter BuUer Register Description
Bit
Description
15-08
RAZ (Read as zero)
07-00
XMIT DATA BUFFER (Transmitter Data Buffer}-A read/write byte that stores a copy of
the most recent byte written into it. When a byte is written into this register, the XMIT
RDY bit in the XCSR register is cleared. This byte is copied into the transmitter serialoutput register whenever the register is empty and the XMIT RDY bit is dear. The XMIT
RDY bit is set when a byte is copied from the XBuFinto the serial output register. This
register is cleared by the TEST signal .
• Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC319-AA
are described in the following paragraphs. The test conditions used for the electrical values listed
are as follows unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for the
general specifications for integrated circuits .
• Operating temperature (TA): O°C to 70°C
• Power supply voltage (Vee): 5 V ±5%
Mechanical Configuration
The physical dimensions of the DC319-AA 40-pio DIP are contaL.'1ed in Appendix E.
3-36
Confidential and Proprietary
...
DC319
Absolute Maxitnum Ratings
i
Stre~s greater than the absolute maximum ratings may cause perman~nt damage to the device.
Exposure to the absolute maximum ratings for extended periods f11ay adversely affect the
reliability of the deVice. These ratings are for stress conditions only and do not imply that the
device will function properly at these ratings or ratings above those inditated.
• Power supply voltage (Vcd: -0.3 V to 7.0 V
• Ambient temperature under bias: OCC to 70°C
• Voltage on any pin with respect to ground: -05 V to 7.0 V
• Storage temperature: -65°C to 150°C
• Relative humidity: 0 to 95% (noncondensing)
• Power dissipation: 1.0 W
Recotnmended Operating Conditions
• Power supply voltage {Vcd: 5 V ±5%
de Electrical Characteristics
'The dc electrical parameters of the DC319-AA for the operating voltage and temperature ranges
specified are listed in Table 7. Refer to Appendix C for the test circuit configurations referenced in
the table. All input and output signals are TTL levels.
Table 7 ·DC319·AA de 1bpdt'4ndOutput Characteristics
Parameter
Symbol
Test CondltioDs
l\equh-emen:ts
Min:
Low-level
input voltage
VIL
-0.5
High-level
input voltage
VIH
2.0
Low-level
VOL
IeI..=2.2mA
High-level
output voltage
voltage
VOH
IeL =-400 !iA
Output float
leakage
current
Ion
V..,=Vcc to OAV
.Max.
0.8
Vcr.;
0.4
Units
Test
Circuit
V
Cl,C2
V
Cl,C2
V
C2
V
Cl
output voltage
204
Confidential ~d Proprietary
10
3-37
,-----_._-----
DCl19
Parameter
Symbol
Test Conditions
Requirements
Min ..
. Units
Max.
Test
Circuit
IlL
V",= Vee to 0.4 V
10
~
C5
Power supply
current
Ice
All outputs =high
100
rnA
C7
Standard
V1HOUtput
current
Ion
V... =Vee to 0.4 V
-40
~
Cl
DALVIH
output
current
Ion
V.... =Vee to 0.4 V
-700
Input
leakage
current
Standard
Va output
current
DAL VIL
output
current
IoL
Cl
V... =Vee to 0.4 V
1.6
rnA
C2
V_=Vcc to 0.4 V
3.2
rnA
C2
ac: Eleetrical Characteristics
The switching characteristics of the output signals are listed in Table 8. Refer to the input and
output waveforms in Appendix D for the symbols referenced in tbetable. The signal timing for a
read and write data and control cycle is shown in Figure 7. Table 9 defines the timing parameters
listed in Figure 7 for the operating temperature and voltage ratings specified.
TableS· DC319-AA Signal Switching Characteristics
Symbol
Signal
Description
Requirements (ns)
Min.
Rise time/Fall time*
Interrupt request outputs (IRQ)
Serial-data outputs (S1)
Baud-rate clock (BRCLK)
Max.
250
150
150
*Each DAL line drives 200 pF load. All other outputs drive 1 TTL unit load and 50 pF load. Timing
measurements are made at 2.0 V on a low-to-higb transition and at 0.8 V at a high-to-Iow
transition.
3-38
Confidential and Proprietary
VAUD ADDRESS
ADRS
tAS
tpw 100 NS MIN
tAt-.
o ns min
50 ns min
CTRl
READ
DATA
------~--~~(
VAlIDIlATA'
\)-~""'-.............
.~~--~--~----r-----~I
WRITE
I.
'''~_
l 0:_)
t<;vc4OQ ns. min
T'uneDesc:riptioD'
Re:qUitementS(DIJ)
MiD.
Max.
400
100
!:eve
Cycle time
tl"W
Controlling pulse width
t AS
Address setup time
tAH
Address hold time
tAC
Access time
tn
1'hree-state tim&
0
10
t DS
Data setup time
100
tnH
Data hold time
50
0
250
50
0
'Read control: ~ and RD signal asserted and'W'LB signal uoasserted.
Write control: ~ and 'W'LB signal asserted and AO unasserted.
ltra (off) is measured with DAL drive = 100!lA.
Confiilential and Proprietary
3-39
OC319
Application Information
Figure 8 is an exrunple of an interface using two DC319-AA serial·line units (SLUs). The SLUl
DLARTcommunicates with a console terminal through connector J1. TheSLU2 DLART interfaces
with a communication line through connectorJ2.
The SLUs transmit or receive 8-bit, byte-oriented data with no parity, one start bit, and one stop
hit. SLUl provides the XDLl and RDLl interrupts for the transmit and receive data and the
BREAK output. The BREAK output at M 14 can he connected to M13 by a jumper lead to generate
the HALT interrupt when SLUl is used with a system console. SLU2 provides the XDL2 and RDL2
signal interrupts for transmit and receive data, and three realtime clock interrupts at 50, 60, and
800 Hz. These interrupts are wired to pins M18, M19, and M20 respectively and can be connected
by a jumper lead to pin 17 to generate the TEVNT interrupt.
When the serial-line units are addressed, the CSDLO line is asserted to select SLut and the CSDLl
line is asserted to select SLU 2. These inputs connect to the es inputs of each SLU. Address bits
AD2 and AD 1 are used to select an individual register within the DLART. The READ line connects
to the RD input and when it is asserted, the contents of the register selected will be transferred to
the TDAL bus, provided that the WLB input is not asserted. When the WLB input is asserted, the
low byte of TDAL bus will be written into the register selected. Only the register bits designated as
read/write will be written. The DLCLK input is a crystal-controlled dock reference used by the SLU
to generate baud rates and realtime dock outputs. If the BeLR input is asserted during a RESET
instruction, the RCV IE bit of the RCSR register and the XMIT IE,MAINT, andXMIT BRK bits of
the xeSR register are reset. When the DC LO input is asserted during powerup, all SLU outputs will
be disabled and the internal logic and registers will be reset. The baud rate is set at 300 after the
SLU is initialized by DC LO signal.
The RS232 and RS423 EIA standard signal levels for the interface connector are provided by E30
and E37 dual-line drivers and dual-line receivers. The slew rate for both channels is controlled by
resistor R6. The factory configuration uses a 22-ko resistor to provide a 2-1..15 slew rate for operating
at a 38.4k baud rate.
3-40
Confidential and Proprietary
-
DC319
Jl
M14
CSOLO
BREAK OUT
f-o
r--
M13
D--THAlT
+12F- 10
1
BRClK
SLU1
DLART
E65
RCVIRQ
XMITIRO
DC LO
BCLR
r-- ROLI
I---+- XOLI
AD2
A01
~-
3
;7"
/+
7
~
WlB
8
JR8
-12V
READ
V'
DlClK
r'v-
r---"' 2
-4
-6
-9
":'
'--
"
OAl<15;OO>~
J2
'---
BRCLK
r--
V'~
+12F- 10
1
SlU2
DlART
RS-::-
E30 .-.
E66
3
_ROL2
I---+- XOL2
CSOLl
7
+
E37
50HZ
~8
60HZ
~9M17
D--TEVNT -12V
800HZ
.~R7
~O
8
r--
r--
2
4
J-- 5
~9
'-
DlCLK
03
+5 VOC
05
4.3V
E44
Figure 8· Dual DC319-AA Serial-line Unit Configuration
Confidential and Proprietary
3-41
• Section 4-Bus Support Devices
The bus support devices are available for Q-bus, UNIBUS, and V~BI bu~jnter£ace development:
VAXBI Bus Interiltces.
. ".
.....
.
..
The VAX bus interconnect (VAXBI) is low-cost,hiBh"bandwidth..",j2·bitsyn~JlOusll1lS, ~ to
connect VAX processors to memories, I/O controllers, I/O busadlap~fS, ~~ VJ\X1PtP«S:SOrs.
It provides a large addressing range and high data integrity and allows a.ihlgl~ V~ t>rpc~wr :to
communicate with up to 16 nodes on the VAXBI bus.
VAXBl78732 Bus Interconnect Inter/age:-the .,nncjs a lM~PlA 'Z:¥-Ol);~p~tsetVe$~Sth~
primary interface between the VAXBI bus and a master or slave portjnte~fllCe.
VAXBl7874J BCI Adapter Inte1/ace-The BCAI is a tn-pin ZMQ§chipthatfunctiorius'abuffer
file between user-designed processors, memories, and adapter niQd"ules and theV'AX1U bus.
VAXBI 7873J BCI w MicroVAX II Bus Inte1/ace- '1:'he BCI3 it~rlJ~~pmpackage'tis'edtocOt1necl the
integrated circuit interconnect bus oithe MicroVAX processor ti:J·ffie V~I bUsi:l1mtigHtheVAXBI
c,'"',',,:,,,
7~32BllC.
-
",.,,;
,',,'
-
..
.
..
VAXBl78701 Clock Driver and VAXBI 78702 Clock Receiver-'Th¢Qlo¢lq;hiver-iSa14..pmbipolar
DIP that serves as the clock source for the VAXBI hus system. • 'outp\1t;oft.he¢l&:k1dtwtrds
received by the 16-pin bipolar clock receiver to generate the tim.tngsignalslused1bytheVADI.bus
system.
Q.bus Circuits and Kits
. . ...... . . '.
'. ."
. ,'. ......
.'
.
Digital provides a series of integrated circuits (les) and kits u~Jrtthe~()p!llent()fdevice
interfaces for the Q-bus. The Q-bus is the LSI-ll processor bus. meJCs~avail~l~i;;epw;a~rcOr
as part of the DCKll series of chipkits. The chlpkits contain a ~of ~bi~*~~gQu})l~-~eiMtwiJ:e
wrappable module (W9512), and connecting cables that~be,~to/d~~~d.iin~e~;most
Q-bus interfaces. The chipkits minimize the number of clUp~l:1:~~~arYt9d!;YeJ,QP.<:~~m,p~gram
control or direct memory access (DMA) interfactis:.;:r,hewi~i~· '. '.••. ,¥!~p!-'pvi# .a(tditipttal
space for mounting the special interface logic req~.~fex:tQ
' .P'ser.s~tt~r'document
number EK-01387) for detailed information related Dddisettesoc .ipkitsand for-applic~tion
information. The specifications for the following Q-bus interface chips are contained in this
reference ~ide.
DCOOJ Dual~inierrupt Logic- The bC0031s arq8~pffiDlPbi~r~evite ~at is~setf ~perfijrman
interrupt transaction in a computer system that uses a daisYcllhltf type b£ai'mtmHcl1i '
DC004 RegislerSe!ectof Logic....:TheDC004 isaf?-pin DIP bipOl~ devlcethatbpetates'asa'~ster
selector to control the transfer of data to ilnd from uptd four Wdrd registecr~. " ,"
.
DCOO54-Bit Transceiver~ TheDCOO5 is a 20-pin DIP bipoiar device that isused in interfaces'as a
bidirectional buffer between the Q-bus and device data bus.
DC006 Word Count/Bus Address Logic-The DC006 is a 20-pin DIP bipolar device that is used to
control direct memory access (DMA) data transfers.
DCOlO Direct Memory Access Logic-The DCOIO is a 20-pin DIP bipolar device that provides the
logic to perform the protocol operations required to request and gain control of the Q-bus.
to
Chipkit Description-The following LSI-ll chipkits are available and contain the components
listed.
• DCKll-AA Program Control Bus InterfaceChipkit
1 DC003 Dual-interrupt Logic
1 DC004 Register Selector Logic
4 DC005 4-bit Transceiver Logic
• DCKll"AB Designer's Program Control Bus Interface Chipkit
1 DC003 Dual-interrupt Logic
1 DC004 Register Selector Logic
4 DC005 4"bit Transceiver Logic
1 W9512 Double-height, wire-wrappable module
1 BC07-D lO~foot, 40-conductoJ; plug-in cable
• DCKll-AC DMA Bus Interface Chipkit
1 DC003 Dual-interrupt Logic
1 DC004 Register Selector Logic
4 nc005 4-bit Transceiver Logic
2 DC006 Word count/Bus Address Logic
1 DCOlO Direct Memory Access Logic
• DCKll-AD Designer's DMA Bus Interface Chipkit
1 nc003 Dual-interrupt Logic
1 DC004 Register Selector Logic
4 DC005 4-bit TransceiVer Logic
2 DC006 Word Count/Bus Address Logic
1 DCOlO Direct Memory Access Logic
1 W95U Double"height, wire-wrappable module
1 BC07-D lO-foot, 40-conductor, plug-in cable
UNIBUS Devices
The UNIBUS is an asynchronous bus used with the PDP·ll and VAX processors. TheUNIBUS
devices facilitate the development of the bus interfaces.
DC013 UNIBUS RequestLogjc-The DeOn is a 16-pin DIP device that contains the logic required
to perform bus requests and to gain control of the UNIBUS.
DC021 .Octal Bus Transceiver-The DC02t is a 20-pin DIP device that contains eight bus
transceivers used to transfer information between the UNIBUS and a user-developed interface.
Confidential and Proprietary
• Enables low interface cost
• High-level integration reduces module atea required
• Complete VAXBI arbitration, address decoding and matching logic· to reduce hardware and
software protocol
.~tion
The VAXBI 78732 bus _~ intel:face ~hi.p (~II(;) is .~~. ona13)-pin4MOS
integrated <;ircuit .andserves uthe primal:yiMtt£~ ~'the VAnI .Mpp$~theuser
developed ~ o! anode.. ~ gn<::isf~~.pqrpqse~ac~£orp~ssgt'S> me~ties,
andai;faptez;s tbatope,ra~ wjth.the.VAXBlhut.lt)?l:do~.~~.~I,lS:~~ ~and
match.iqJ. and contrpls the user's interface signals.. FIgUre 1 is a functional block d,i~pf the
VAXaI 787)~ interface.
..
. . . ..
CONTROL
SEQUENCE
~...~
.......•..... '
~.: .•.............~ ....
PH.
input/output'
ai; Data......:Usea;fu#;~fer data and address
information.and to perform arbitration.
EOt-E03
FOl,F02
G01,G02
BIO,Bll
C09
BII<3:0>
All
input/output I
BI Identification....;..Used to transfer com~;:ientod~,tnaster identification, read
status codes, atld write masks.
input/output I
BI Parity odd-Used to transfer odd parity for
the lUD<31:00> and Bl~;~)ij1:t;;~,~
i~ i$;.~.w:heb.atl~·.QUffl~rCl£ bits
·,Qn··the liitw;i1ias~,.
en
input!8utpUtt> ··;m'M();~tij'~~ii~~;te;ihhibit;at1:ti~
trationontn,:m45l(!1!t'i~'>1ine8i]t ·'is~
asse.tted:ld~·~f~nc;·.~~.·.··~;;p~nt;
;oth¢~~~titlg~~'unt;ilaU
. • ~.~y~p~~te',
A14
input/output'
BI Busy-Asserted to inclicate that a transac-
tion is in progress.
A13,B12
Cll
BI CNf
1I1i6
!lYNCI:IRONOUS COfIITRpt. SIGNALS
Bi NoMe
El
81 CNF<2:O>
ASYNCHRONOUS CONTROL SIGNALS
Figure J .• VAXBI 78732 BI Line Functions
BI Data-path Signals
TheBI data-path signals are grouped into the following categories. All data, arbitration,
commands, and address information is transferred through these lines.
BI Data and Address (BI D )-These lines transfer data and addressi.nformation and are
used during the ai'bitrationsequeqc~.
BI Identi6cation (BI 1<3:0»-These lines transfer commands, encoded master identification,
read status codes, and write masks. Commands can be directed to one or more nodes depending on
the type of command. The ootnmlUld codes and types are listed in Table 2.
BIILine
3
2
H
H
H
H
H
H
H
H
H
L
H·
L
H
L
H
L
4-4
Confidential antf Proprietary
BIII..ine
2
3
1
0
L
H
H
H
MR
INTR/1lltertupt
L
H
H
L
SR
IDENT/ld¢ntify
L
H
L
H
L
H
L
L
L
L
H
H
L
L
H
L
L
'L
L
H
INVAL/Invalidate .
, 'BOC$Ttnroad~ij(te~)
\ I
L
L
L
L
"'
MR
,,' :.~" :' :" ;::,i,:~ , , ;','" ,,_ ,'._
,";L ,
*SR is' a single responder, MR is more than one respOiiCIet· .
Bl . Piuity.~)-~cate$theparityof theBI b< 3i:OO;> !and. fil
PlirityCheckitig and 'GeneratiPh.)
.'
'"
t.:::fo.:>
'Jirie$.··(IM~··tQ
.' . . ".' '.
\
.
BI S~ConUolSipais
The Bl synchronous control lines provide coritrol £Uhctions andr¢$pbfiseSto·cktftiaruI command
cycles.
BINo
1}iM~~FP9*~ ~. ~i,~<>\tbeY~Idata Unesfor
arbitration. The nodeslnGnitorthi$sigtuU$OtMtthedata~~m:lIaddtess.inforrmatio1:ldoes
not contend with the arbitration information. If dlem~~ is~serted ~ ~VAnI
ArbitNtiatioIJunN9Mm"r'
cycl~> thenodeslU'epreven~!rottlarbitratinetl~!~ ~Y~Icycle'~Thiss~is ass¢rtedby
• Nociesarbitrating £orthe bus ~the ~~otlqae~
,
• The pending bus master ftomtl:te cycleaf~ Jt"linsthe ll1-l>it~tion until it becomeS .hus. master:
~--~--------~
• The bus master durlngthe fOllowina:
-Embedded ARB cycle of longwotd transaction
-Embedded ARB cycle and thefoHowingcycle ofaqWld~transa~n
-E~ded.ARB cycle through the qrcle after the'~~ttdACK dataqrcle of an octawotd
transaction
• The slave for all data cycles except for the last cycle.
~ All potential slaves for the third cycle (decoded master:£D;):arid for the lOENT arbitration of the
IDENT COmrlland.
• Nodes performing loopback transactions.
• The bus master during its command/address cycle to prevent bus arbitration from occurring. This
allows the bus master to start a bus transaction following the current bus transaction. (This mode
is reserved for use by Digital.)
• Nodes performing self-test operations until the VAXBI registers can be accessed.
4-5
This
BI Busy (BI BSY)sig~.,p~0desthC;,ol;'derly transition of bus mastershlpfrom one node to ,
another node. The nodes monitor this signal to determine the action to be performed dtlring the
following qrcle. The deasserted state of the BI BSY signal indicates that the current transaction has
been completed. The node that. WOn the last arbitration may become bus master in the cycle
following the cycle in which the deasserted state of the signal was detected. The signal is asserted by
• The bus master during the following cycl~s of its transaction
-Command/address and embedded ARB cycle of a longword transaction
-Command/address, embedded ARB, and the following cycle of a quadword transaction
-Command/address, embedded ARB through the cycle following the second ACK data. cycle
of an octaword transaction
• Anode to delay the start of the next· bus transaction until it can respond to another bus
transaction. The maximum stall time by a node should not exceed 16 consecutive cycles 1IDd is
limited by a timeout circuit to 127 consecutive cycles.
• The slaves for all except the last data cycle.
• Nodes performing loopback transactions.
>-)-
BI ~tion (BI CNF < 2:0
These lines provide handshake functions between mas,ter ~d·
slave nodes to reflect detected errors and to indicate the current state of the slave. Table 3 ·1lStsthe
response codes and information. During a transaction, the node must first respond to the
command. For read-type, write-type, and IDENT commands, the slav~ must respond during each
data cycle following the command confirmation cycle.
..
.
Table .3. VAXBI78732 BlConfmnationLine Code Assignments
BI CNF Line
Description
2
1
0
H
H
H
no~ckno~ledge
H
H
L
illegal
H
L
H
illegal
H
L
L
acknowledge
L
H
H
illegal
L
H
L
stall
L
L
H
retry
L
L
L
illegal
.".:;,.,,',
Confidential and Proprietary
PowerOmtroJ Sipals . .. . . .. .
..
The BfA<:: to and til DC tosignilhare used to col(lu:ol the powetl,lp~t*>~wnseguences of
·C .. C . . .
..
.....
..•.. : . '
the nodes on the bus. 'Thesesigrlal.senable the VAXBI to stonnthd retrieve t¥e.~s requimd;
inthe~nt of apoW¢r Jailure·or interruption. The. nlAe lb is asset;tedwhdl *elihe voltage is
below the 'minimum l~~}t~13,I~f~Orsignal is assertecl to indicate an i'mpending loss of~c ~c
power and is also used for Wtialization during the powerup sequence.
.
• BCI Line Func:tions
The BCI bus consists of 64 lines used to traIlSfer data, address. status,and coDtl'Ol infoiJniltiOfi'
be~.theB:rrCan,dthe·I,l~;jI:~~t;e;'l)ble 4~~c~_~tUl!'lCtiouQfmeBCllines. Th;C·
BCI'ljnesaJ'egrouped;l;ly Jh~£U~~s~~in Figure 4. . .
~.. SiIAfW.S
TO BIle···.
FROM
[]
El'
sa AQ
imMM
aile
El
El
HI ·ttAK
fClNXT
EJ
iii¥fiii.
SLAVE .attAI.I
FAOMJlnc
TOBIIC
TOBIIO
8.CI.INT;<7;4>
FR0fIt811C
fiT
U
BCI ACLO
BCIDCLO
EL
BeITI"'II: L
Figu~4'
Bci PHASE L
VAXBI 78732 Bel Line Functitms
-,
Preliminary
Sipa1
Input/OutpUtl
Definition/Functicm' '
J02
BCI D < 31:00> input/outP?t
KOI,K02
LOI,L02
MOl-M06
NOl,N03-NIO
P03-P12
Btl 'Data-Used to transfer data and
address information.
M12
Nll,N12
P13
BCII<3:0>
input/output
BCI Information-Used to transfer come
mands,tead status codes, and write masks.
N14
BClPO
input/output
BCI Parity-Used to transfer and Bcn < 3:0 > lines.
This line is asserted when an even number-of
bits on the lines is asserted.
D14,Fll
BCIRQ< 1:0>2 input
BCJRequest-Used by the master-port
interface to instruct the BIIC to perform a
specified transaction.
input
BCI Master abort-Used by the master-port
interface to instruct the BIIC to abort the
current master-port transaction.
F13
L13
BCI RAC < 1:0> output
BCI Reqqestacknowledged-Usedby the
BIIC to indicate that a transaction requested
by the master-port interface has been
initiated.
M14
BCINXT
BCI Next-Used by BIlC during write transactionstc>' request the next data word from
the master-port interface and during read
transad:iorts to indicate to the master-port
interface that the data on the BCI bus is
output
valid.
G14
BCIMDE
output;
BCIMasterdata enable-Informs the master-port interface to transfer the information
to the HI bu~.
C14,E14
BCI RS < 1:0> 2
input
BCI Response-Used by the slave-port interface to specify the code that will be transferred bytne Bnc on tneVM\:Blbtis.
M13
BCICLE
output
BCI C ycleenable-Indicates the presence of
a command or address cycle to the sl~ve-port
interface.
Confidential and ProprietlU'y
-'
s.....
H14
H03
BClSEL
output
BCI SllWe . _;emlble--:.lndi~ltCil . · the·.
slave-port interface that the ittformation ttY
be transferred ontbe VAXBl'bqs should be
transferred, ioth~,Bt1.data lines.
output
BCI "Se~~~When assert¢d, theBCI
SC <2:0;:J'~S';~lect as1ave-~rt interface
for aVAXB'J:~a¢on.
HOI,H02,
BctSC<2:0>
.
a',
BC I si~ '~~ntrol--Sel~t~
sIa~e.port
interface when the licf sEt line is asserted.
output
JOI
OOI1i1~f!i~t~tequ~s~tt~~
E14,F14
G12,Gll
the~'s;irwerfaCe';'1Urousei!twidltlre\kr
llS<~r;~;1fu,e8,;tI5'~~ions ",during
the cliagnosdc mode.
Jl2JB
BCI EV <4:0 >, outpl,lt, '
~I.g'l,f:tlt""'"tJ!llii~t~~ tb~" ClCCt¥~Cc: (){sig-
t};ni£icanti~~;~the BlIC or 00 the
K13,KI4
VAfC1,i:tJU§;Not~ddutidgthe:~~$~c
L14
"
","" .
BCI'aclciW:::::'Iridicates 'ifie "status of "the ac
mod~:"
"f
N13
Bel Xc ill .,Qutput
poweJ1,tf) the user'sinte!#ce. '
BCl d61ow-Indicates ·~he status·of the de
J14
B14
po~;to~:~·si!l,~~~.
BCI fitne--A ~.MHZ ~L ~'£rom the
VAXB~CIockreCeiver intbe user'~inteclace.
UsedmthtbeB9IPHAS~LIine t;;y the BIle
BCITIMEL
,~~nc:l,1.l~'s ~~.tface to geilerab!~ req~
t~~ign~.
DB
BCI PHASE L
BCI Phase--A' r-MHz ttL signa!, from the
VAXBI clock~eiver in;the user'sJntetfa~.
ioput
USedWi~hij)~ aCI:n:~ritL line by:th~ ;sue
and~r's interface to generare tie required
ti.rniJ:ij\signals. i
....
: .,'
'
,.1
>
,'"
',,,.
t '
All user interface~ig~ areTrtltwels."
,' '
; , , .,.,
2'These signalStnust beconnect~toa.bi.iibJ~ when notu~,in the !looedes.ign.
I
BO Data &th Signals
The BCI data path consists of bidirectional three-state data, information, and parity lines. The
direction of transfer is controlled by the Bel Mf5E and Bet SDR signals.
BCI Data and Adchess (HCID < 31:00 > )-These lines provide a 32-bit path between the BIlC and
user's interface to transfer data and address information. During command/address cycles, the
BCI D < 31:30 > lines contain the data length code and lines BCI D < 29:00 > provide the address.
Table 5. lists the data length code assignments.
BCID'~
Da~Lengtb'
31
30
L'
L
reserved
L
H
longword
H
L
quadword
H
H
octaword
BCI hlformation (BCI I < 3:0 >.),...,.. These lines are used to transfer commands, encoded master ID,
read status, and write masks. Table 6 lists the BCI command code assignments, Table 7 lists the
read~status code assignments, and Table 8 lists the write-mask code assignments.
1i.ble 6· VAXBI 78732 BCI Command Code Assignments
BCntiDes'
'Typel
Command Desaiption
L
H
L
H
SR
SR
SR
READ
IRCI
RCI
reserved
read
interlocked read with cache intent
read with cache intent
L
H
H
L
H
L
H
SR
SR
SR
SR
WRITE
WCI
UWMCI
WMCI
write
write with cache intent
unlock write mask with cache intent
write mask with cache intent
L
L
L
L
L
L
H
H
L
H
L
H
MR
SR
INTR
IDENT
interrupt
identify
reserved
reserved
H
H
H
H
L
L
H
H
L
H
H
H
MR
MR
MR
MR
SJDP
INVAL
BnCST
IPINTR
stop
invalidate
broadcast'
interprocessor interrupt
3
2
1
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
ISR = single responder; MR =multiresponder.
2Refer to Broadcast Transactions (Appendix A) of the VAXBI System Reference Manual.
4-10
Confidential and ProPrietary
BcIlLines
3
2
L
L
L
L
H
H
H
:H
reserved
Ieaddatil
"
*
"
"
.
.
.
.
.ronectedteaddata
.~ddataJs.Ubstirure
" f''',,~-
L
L
reserved'
read dawoonotcache
cOrrected~data{do not cache
H
a,
......... ,<·~.~'$~b~~ldq)~cache
"Line < 2 > is reserved. The Slave must dea8~rt (L)this 1i.tit:!J~i.~s,~$tYpes~thetnaS~s
must ignore the state of this line.
.
BCIILine
asserted
3
<21:24>
2
1
<:23:1~>
<15;02>
<0,7:00>
o
BCI 'Pamy(BCFPO)-Thh ·fuie .' .eOtlWn$ ,th't'lPtirityWti&tprfor·"tibe.BCf·J' and
Bel D< 31:00 > line signals. The paritYsenS¢'lso&:tTh&tf~'lict;m,lme;~'beail~
cluring' user'!.int:er£ate.g¢n_tedpatitymo~wh.en'an ~"l'liIltIlberof. oorp<.3,1:00> arid
Bel 1<):0.> linesare~.'
Thestate'o£tbr,Bq~1in~:is.contp,)~dby.~~,u~er'sj~!I.~,.~i~~~~J1,l,~~;l)U1'~
pGWerup when tIx:fiCl l"StJ15sigruJis assettedf~eBriC]Q~.IIth~~~.~t.~s~ ,wj~ ~e
parity mode; Ifthi: user's futerfaceasserts t:KeBCfPOlin~ ofi40v1S'it'~~~.lJ~lfl~by
default when the BCIDCti5line is~serte~~I"2~~Q >'~,to
allow~,snc to generatet~pa~itr, If~.user'$i~~~~~~tco~~.S~,l~linl:?dtu;~
POWl:l;UP,the BnC,willg~Derate parlty.by default.lt,l B.ll~j~~d~ty mode, the BCIRCl'line
doesoot have to connect rot:heBlIC.
app
If the u~'sinterfacedeas~~ed the'BCI PO ~,'Yhe#tbe»t:li1CiPlineis. ~ted~tbe Bue will
bec:o.ptigured ~oruser~s tn~r£ace.ge~~a~ t'~it)'., 'Theu~er.'& iht~rface..tID;sfP~ide the 'proper
pati%n theBer PO·Jine.w~'the Imc s?1icits dat~ .•,(I3ct~ o~,~r.SD~I~asSerrea.) liIthls
mode, a shorter setllptimek permit~ed on BCtp ~ ·rl:OO.~ ~dBCIJ ~ 3;97~s'£or the data
to be trahsinitted oh the VAXBt bus.lfth¢ us'er'slntei;face geri~~iriCQmct parity; the pantY will
be transmitted on the bus, and a bus error will result,
t¥.
4-11
When data received from tk~~I b¥,s.i~J~sf~t:l1roU8h, the]mC ~~e BCI lines,theBCI
PO line re£lects.the received.state of the BtroJine. During loopbacktransaction cycles, the parity
generated by the user's interface or b, the·l:mcis transferred to the BCL
BCI Master Signals
The BCI master signals are used to request, execute, and tertVinate transactions.
BCI Request (BCI RQ < 1:0 >}-These lines are used by the master-port interface to request that
the Bnc perform a transaction. The lines ate also used to select the BIlC diagnostic mode. Table 9
lists the BCI request codes assigoments.
Table 9 • VAXB! 78732 BCI Request Code Assignments
BCIRQLine
1
0
Description
no request
VAXBI transaction request
loof?back.requ~t
diagnostic mode
H
H
H
L
L
H
L
L
BCI Master Abort (BCI MAB)-This signal is asserted by the master-port interface to indicate to
the BIIC that the present master-port transaction from this node to be aborted. It is also used to
clear the retry state of the Bnc entered after a retry confirmation is received. The assertion of the
BCI MAB signal does not affect BIlG-generated transactions.
is
The user's interface usually cannot abort a requested transaction without generating bus errors that
will be detected by other nodes. The BCI MAB line therefore Should be used to abort a transaction
request only following an error cOJ;ldition. A pipeline-request master should abort ,a traqsaction
request only for the transactiqn subsequent to one that fails.
The user's interface Should deassert the request lines in the same cycle that BCI MAB is asserted.
The actions performed by the BIlC depend on when the BCI MAR signalis asserted as follows:
• If the BCI MAB signal is asserted before the BIlG arbitrationeyde, no. transaciion is iriitiated.
·If theBIIC has won the arbitration cycle and has not transmitted the command/address, it will.
deassert the BI NO ARB line in ~e next cycle.
• If the BCIMAB signhl is asserted after a reti:ycOnfirmation or timeout event code is receiVed
(RCR or RTO),. the,BIIC .aborts its retry.state sethar it can· accept a new request. . The user's
in~!lCe can abtlrtthe retry state only by'asserting thd3Ci MAB signal. FollOwing the assertion
. ofBCI MAB, the user's iriterfaceshouldnbt assert a new request for a minimum of threecycIes.
• .~n a node that.~mys pipelinere9.ues~s, the~sertion of the.BCI MABsignal may 9ccur during a
transactionfrolll thisriOde. If the BCI MAB si.gnal is asserted during transllction, tht; BIlG
caborts the tnm~action'l'he user~s il1te~f.~e ~~y not receive!Ul event code fpr a trat)sacti0 tl t11.at js
~~rted .. A. minimum of
o/c;r(!.s~ol1o~~ the a~~rtion of BClm13ll1u~t.be all9'.Ved)Y the
.,user's interyace ~f()re a De\l{requcrst is gene~ted. Th# useo£ this m.odeshoulgbe a:vpi~d .. ,.
a
tlircrF
4c12
Confideritialand .PrOprietaxy
-'"
~".
BCiRequest ~~ (BdiOOO~fbis)i!u:is: u~l>ytheJnICti>jndicate that the
transttctionrequested},ythemaster-port interface has been initiafied. ThqBCI lilt line is a~ed
only during master pOrt,trar.sactions and is not asserted during BHCfgenerated interrupt' tind
interp:rocessor intert1J>t transactions. The line is asserted during the'mstt:yC1e ofa VAXBI or
loopback transactwnahc;l ~~jlsserted for the c:hnatiQ~lQtthetransaction.' his deasserted
during the cycle whenthei!¥~tC9de is transferred .fl'9n'l~!}~!~ During wtite-type and:
broadcast transactions. the BClRAl'Ellneremainsasserted until the~!!lCknowledgc;<:ycle of the;
slave is on the VAXBl1:nls;,,'l'lW; OC'CW"S three cycles 1:1fter the last da1;S.. ~Je during Wlite-type and,:
broadcast transaawns.Durlng read.typeand identification t~J1$actioJ1$,'theline~as~rted
until two cycles after the last data cycle to allow time for an intemalparlty check. The Bef i l l line
is deasserted during the sixth cycle for a stop, invalidate" and master-port interprocessor
transactions.
.
If'the user'$interfacereassertsthe~CJRQ~1:6>lii'!¢Hkfore ',' '",' '", ,'"ii,6£d#It::J;iARas'
ducirig a pipelit1e~t:thenot~'tirilmg'¢ftheBCH{AJ~\'~'it, ,'iantFtti~iBClm
signal is dea$settedm dte cyclea£tertbe~BCfa.'i!( HJ~Wasl~~tet_tll'W!iH~nhie~at
the, stal't o£thenewly~~~,~~atrDa$m.pc;lrt;inferf~$·;:l
DCI N~ (BCt·NX1')2ThiSline iS~serteab1the~nCtO. ~sr.~,Q~t .~~·~~.f~m~e
master-port interface during VAnI write-typeco~~art(f:'w;in(1~tet6't~inastet·port
interface that;tbeda~ond:~e~H~,~4d~~a.~
..... ~~t~~ri~~~l~~~
qa(a.cycluinwhicPthe~OO l$;receivmg~~;;~, . ·. ..... . . . . . ;~~~"~WliAA~~i;~~l
pr nO.~QW~~ge gJn£it~ati.on.C0de~s·~~wiili.,medlttl:t:ior.J.1.~'i~~'·Pl1dtyoi·t1re
received
lirtesbe£orethe~nmgo£··dtertext~cl~;iBete.~.ml~~~buffi~~l'4ejtl\e helmIT
Hne is asserted dniyoneetol'.eachcl4ta \l.ijra;~'lf th!i!'mtlj~i:jnlste'tfied.ot;,mJIedtot one or
more times.
During read-type transactions; the ilSsertihg~Ofth~'tk:iN!'jsignal.jrt~t&tl'tat't~data()n
the Bel D<31:00>litiesiS_d;;1\bi~fimylieU$al·tbeto&sth~1~ddiita'i~i..bt\l$eP'sintE!rfaee·
BCI··~··J)gta·E"We... ~M~!),.;!lThiS. $i$naf'isas~tbY·t~'BiiC 'd~,~~jcYde'to
~jcate~ to! thefit~tt;r-port.m~~t' ~ha~tFt~~o~~~informatioribr'$t}lf Sl10uldbe
ttimsferred to the, BCl D< 31:00>' ,B(;t! r''''
,
'
Mtiit.
I·
,_',
i;
"
c'",
,,'?
BCISlave Signals
1'he .BCI. slave signais.respond to transactions directed to a nooe.
BClResponse(8t:iRS lines in response to command and data cycles. They are also umifur
diagnostic mode function selectiOn. The s1~poninterf!lcernUst lilSpj:>nd:wil'hth¢approprUtte
codes wheneveratransac.ttion that involves the slave~port intetfac¢OCCUI:'s,Transacti(}nswBUC
registers do not involve the slave-port interface. A.~spon$eis~for each~inwhichthe
slave node transfers information to the BICNF<2:l.b lines. Table 10 lists the slave response
codes.
.
Confidential and Proprietary
·4-13
-.
BCIRSLines
1
0
H
H
H
·L
LH
L
'L
/ ...
Re.pqnse·
. . .. . ...... ......
~IcN~ c~~
Result
no acknowledge (NO ACK)
acknowledge (ACK)
stall
retry
no acknowledge (NO ACK)
ACK or NOACK
stall, ACK,or NO ACK
retry or NO ACK
Correlation does not always exist between the response code and the corresponding confirmation
code transferred on the VJ\XBI bus. When a code is not involved in a transaction, the BIlC
respo~dswith the NO ACK confirmation code regardles~ ofthe code on the BCI RS < 1:0> lines.
Some confirmation codes are illegal during· certain types of cycles. During multiresponder
transactions, a retry is an illegal response. If the slave-pott interface sends an illegal code during a
cyde, the I1IIC .will repJyw;ith a NO ACK code on the BICNP<2:0> lines except when a stall
response occurs to a multiresponder command.
BCI CotlUlWld LatcbEnable (BCI CLE)- This line is· monitored by the user's interface to detect
the presence of a cOmmand/address cycle. The deasserting edge of the signal can be used to latch
the received command/address information from the BCI D < 31:00 > and BCI 1< }:o> Hnes.The
BITC asserts BCI CLE signal during the cycle after the BIIC recognizes that the BINOARBsignal is
asserted and the BI BSY signal is deasserteq .. This noarbitration/busy state corresponds to an
arbitration cycle or the last data cycle of a transaction that has a pending ml'lsteJ:. The BIlC deasserts
the BCI CLE signal during the cycle after. the command/address cycle when the commandl3Cidress
information is on the BCl D<31:oo> and BCI1<3:0> lines. The command/address cycle is
detected at the transition of the BI BSY signal from the deasserted to the asserted state, when the
III NO ARB signal was .asserted during the previous cycle.
The BCICLEsignal may be asserted for more than one cycle following a powerupsequencewhen
differentRlIC nodes complete the self-~st operation at different times. This,can}>CCUf during the
burst mode: and following a pending ~bort by a master. During loopback transactions,tl:te BIlC
sequences the state of the BCl CLE line without regard to the state of the BI BSY and BI NO ARB
signals, however; the timing relative to BCI signals is the same as for a transaction on the
VAXBlbus.
The state of tht::: BCI CLE signal does notdePt:::lld on the receipt of valid parity or whether the node
is selected as a slave. A silo or cache-resiqent node that monitors the bus and examines all VAXBI
transactions can use the deassertion of the BCI CLE signal to latch the information during any
command/address cycle on the VAXBlbus.
The assertion of the BCI CLE line should be used to force the slave-port interface tq. a state from
which it can respond to an SC code during the following cycle. In addition, the slave-port interface
shpuld ensure .that the stall response code is. removed during the cycle when theBCI q,~signal is
asserted.
BCI Slave Data Enable (BCI SDE)-This line is used by the BIle to indicate to the slave.port
interface that the data 'robe transmitted 011 the VAXBI bus should be transferred to the
BCI D<::31:QOI>, BClI<3:0>,andBCIPOlines.
4-14
Confidential and PMprietary
-.
BCISelect(BtISEL)-Thi,:s~is~~er~.by~eBliC tP.in{otm.the #e.portifiterface~t it
has been selected by ia VAXBI transaCtion. The BCI SEL line is
during theell'!bedded
assertkd
arbitration cycle of a transaction if the slave was selected by the;to~dfaddress iilf(!)romrlOh
from the previous cycle. The assertion of the Bel SEL signal is dependent on the receipt of valid
parity'clutingthe' conunandfaQdre$S cycle..
\
1
The. assertion of the t«:IS~ ~.~~m~.g~ th~~lj;Ct'~Cid¢ ontheBCf SC < 2:Q> 1ines.
The BCI~?ll'Qllindsta~~ter :<13GSar~~~~~'~ ~nterface to create a customized
sub$~.o{VAXBI ~i\s ~t' '.' .' •.' .. ct~~~~~P9~ ila~~:;ij~esthat are not required to
~~ndto.qllllticasts~ce.~~~.~~\Vfite'i#. ~m"~J~j:lear the MSEN bit in the
:~:~~:=iJUll~·Rn~'Pwti.~i~~~<~5i~n!~.~pt required. (Refer the BUC
mucls1ttlWe ~iSserted\iheri~.fonQWblgCo~havM:f¢e4received:
",:,0,_"
"
'''' ,"
",
,
;""":;;"","'; ,,"_""·~,',",'r
.:_
-,","':'~""'-'~"'_ -\~,-'l~:~:'
,',:"'l~:>"",:-"."
','~_<":f' ;e',l;~':"':,'::
• A refld·o~w~ty~CQrgm~W'~'~~~lf~~wi~\~qI.~,·space and the MSEN bit is
set in the BCICSR.
• Aread-~ wri~type~Qln~~t lJlll~aqes•. ibe.~~~in~~<;SRspace ~f·the··~· Qnifthe
UCSREN bit is set in the BCICSR.
• Area(kol'wri~typr;:to~nclthat mat<;~~LBiIcCS~~ o{,die noclfl~the"l!ICSREN
.bitis~t jn theBOl(;S~
.'
.
..
.'
• A BDCST command directed at tlw~~~~QC,,:
·.. ···< . '..·"A······ ...... '
... "
~ in the BCICSR.
................_ _ _ _ _ _ __
• AS:rQJ?CQ~(f~i:lt tlteri~~·
,l?flN.. .
iJ;\Jhe BOlC,SR.
• A RESERVED con1mam:hind.theRESEt'U.utj$sellncdte:acI~~,.".
• A~ @Nii ~nullllnd ~d. attheo;~ diaeiiilit~~(tti~I~lrqtR mask register when the
IJ?IN'I'REN bitissetjn:tneBCtcS~.· .'; ....... ! / i ' . ) ' )-These lines transfer detaille )-These lines are used by the user's interface to request
that interrupts be performed by the BIle. The BCI INT < 7:4> signals must be synchronously
asserted. Each INT line signal causes an interrupt at the level corresponding to its bit position. The
Bel INT < 7> initiates level 7 interrupts, BCI INT < 6> initiates level 6 interrupts, etc. Interrupts
can also be genetated by writing to the interrupt control register of the user's interface to set one or
more of the force bits
4-16
Confidential and· Proprietary
the
The BCIINT lines' are'''pseudo-~,;,~. TheBliC samples the state of lines~~~
T150/0. The BUCdctermines when' a transition has occurred on t~ lines by comparing ~.
receivedstateof.~ 11neff()m the p~iouscyde with the received s~of the eurrenteyde.The
ttan!it1onftpmthe~ ~t;lteto the asserted moo specifies an ititcl-rupt ~t.
1)ew::u:N1"<7:4;::.'n.nes ~~:wi~ withthe,BCf RS<;1:0>ilines fordiagnostjc mode
~pscilection.,
.
. '.
BCI 'Jhmsaction Status Sip.Ib'
The ~0D, ~~~pi'9Vicl,e~~;informati,ou tdated!'to the VAXBI in~ace, t¥ VAXBI
bus, or diagnostic ptQ81'am.
BCI Event Code ('10=*",,""1-''''',.!C."...4.....0""";::.-.·
'~'fliese Jines indicate the ~ of':Signi£icant events
within the BnCOl'01l'theVAeI.~tduiingthe diagb<:>sttc~. Thet.hree clitsses otsv codes
are as folloWs~ 'lhble :J.2lists. theevem:.codeS.
BCIEvLine
4
.3
H,
H
H
H
H
H
...'NEV
H
H
H
H
'Mep'
If
:R
H
L
't·
H
L
L
H
L
L
B"
H
H
B:
H
H
H
H
2
L
.... The def~t deassertedstate
'Master~p6rt tranSaction complete'
.AKRSD. ....¥know~~e ~vedflXftn slave ~ data
'lITO
p
. :,·ST·.·.··
If.
t
RCR
It
t
"Bus tit'f'leout
' '.
..,
,
.
,,'" ~~·test passed . . '
., ,. Retry· coptirmation recefved fof' master~_I£
.ROrtoo~
IRW
iRCR
, -i';tf
'lnternaI"r!iister written
, Advance4retty conf~tion received
,,'
,
.(~,
,
,
4-17
Prell~
.
BCIEVLme
43
2
H
L
H
H
H
NJ;CI
HL
H
H
L
NICIPS
H
L
H
L
H
'AKRE
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
IAL
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
L
H
L
L
H
L
L
H
L
EV4,
EV5
EV6
EV7
SID
BPS
H
L
H
L
H
AKRNE4
H
L
AKRNE5
L
L
H
AKRNE6
H
L
L
L
AKRNE7
L
L
H
H
H
RDSR
L
L
H
H
L
ICRMC
L
L
H
L
H
NCRMC
L
L
L
H
L
L
L
H
L
H
ICRMD
L
L
L
L
L
L
H
L
L
H
RID
BPM
L
L
L
L
L
MTCE
ICRSD
BBE
BPR
No ;acknowleg~e, 9~. ill~~al confirmation
~ceived for interrupt command
No acknowledge
illegal confirmation
received for Force-bit interprocessor/~top
command
.
Acknowledge' .confirmation . received .for
error vector
Identification arbitration lost
External vector selected-level 4
External vector selected~level5
External vector selected-l~el6
External vec~orselected.-leve17
Stall timeout on slave transaction .
l>ad parity received (luring slave: transa\::tiol1
illegal confirmation received for slave data
Bus busy error
Acknowledge confirmation received for
nonerl'Or vector-level 4
. A.cknbwledge . confirmation received for
'nonerl'Or vector-level 5
Acknowledge confirmation received for
nonerror vector-.,.·:level6
Acknowledge confirmation received for
nonerl'Or vector-level 7
Read data substitute or res~rved status c~~
received'
illegal confirmation received for masterport command
No acknowledge confirmation received for
master-port command
Bad parity received
Illegal confirmation received by masterport data cycle
Retry timeout:
Bad parity received during master-port
transaction
Master transmit error check
of
Bel Power Status Signals
The power status lines provide information to the user's interface related to the condition of the ac ,
and de power.
4-18
Confidential and PfOpnetary
BCI ftC ·Powet@CI At. LO)..... This signal is a buffeted and s~hro~ BI AC"LO signal to the
user's irtterface to ~ the irtterfaC(!'~mo~r the power status. The ~IIC receives t~$~~ of
A.Ci1) sigfl~~d~a~Q;C)'4:¢d(!lay to verify that the~~v~d$fa«t is srgble.lt thet) ~smits
the state of the s p to·the,tiCI XC
line. The BITC will not ch~gfiiltheStllte of the BCI At LO
.signal unless the state of the line is~t frorritheprecedi[lg state for two cycles.
BCI de Power (Bel fil"IllY";"';'fhis signal incllcates'tJi'le$M\ls o£the,dc~'tothe user'~ interface.
The BIlC asYQ~~~.•~~ct)BCIDC Ill1ine f(;)~'me aSsertion of the,BIl),CLO
signal. The maxi
',. ~isspeclfietf,~~~
.• '
·s. Whent~BIDC
15 is asserted for
. .l'lallO$eCondli•. '··.
......... '.... ,..
1'he Rne oeitSSerts
m
m
the BCI .DC tEfsy~fi6Utit/\\Iith1i~iT~ ~.fOn~$2.ddeassertion·o£ M.OOiLO.
validdeassertionreq#'th.a~,them~r:o·.:;·· ...... " .
A
'. .....~rtwo':!o~tive
cycles. While the BIl1Ct9i$'assertedjthe~1l
.......driwrs includi~.t~eBCI
D < 31:00>, BCI 1<3:0 >~'W BClPO d r i v e r s . " " 'Qf,the VAXBftn'&lUle by
allowing the modules 't6be 't¢stec:i independendy of the;Ba::O~,;' .;;;li
',.
S
~,
,
,. " ,
,,-
'l-'
,d_.
...
->
When the node reset bitof theVAXBi1Ct1ntmt;~;~~~ is set, tl1eBl1Cas~ertS(theJCI DC
LO line regardless oithe stateof.~;:PJ,~gsi~~"~~enthe neOCWis de~,. ~. BIlC
initiates the self'test;TheJ3IICm~nWns a~row:leveloutpu11'-.ltage-QIl thel1cioc t1S when
the BI DC W lS~16~tWithrVcc ~p",l,y vol~e to t~e~I,IC is.in,ttilnsition;
The BIlC loads the node identi£kation,'the>~c:e type. an~revisi9n,and parity mode'identific:ation during the cycle ~£ore the BCl'l5G;~\~~al isdeasser~. Normally, thtt tlSeS7'sjll~rface
transfers the this in£Qrmation to the BCI r.f':Q:>; BCI D< 3ltoo>, andIJClpt}1in~~whUe the
Be! DC LO is asserted.
BCID<31;(jO>-'andJ3CIJ?01inesIZO.~in in~~ puijupsclretitfs that
are enabled during assb'fti()fi'Of the m::lDCllOlfj~S'anaC'~r~~~tO.~~by'de£aUlt.
The default ~ondition m&y be useful in designing anOde. 'I'beoutput current characteris~of the
pullup devices should be verified.
'
The
BCIClockSignaIs
The clock signals from the user's interface provide the basic timing information for,~e VAXBI
interface and user's interface.
BCl Tdne(BCl TIME L}-1hisi~a20:~Zl'tLtilriirlgsigntisuPpliedbythe VAXBidock
receiver in the user's inter£l1ce.lt·isu~d·:WjfN1;he~blpHASEL signal by the ,BIle a1ld i user's
inter£a~ to generate all the r~d:tiroi.og~n~.,
BCl Phase (BCl PHASE L)--:-~is,;a.~,Mij~i,;tr,~;~-~a.l sUJ,>plied by the V~~iclock
receiver in the user's interface: his used with the BCl1'1MEVSignalby the BUC and the user's
interface to generate all required timing signals .
• VAXBI Interface Registers
The VAX,B,1 interface contain~ a co~plete set of VAXBl reg:~ters,~ four geJ1eraI purpose registers
that ~avai1llble to, ~~fdefihedhode l~c.'Tf{~ Biltre~~tet$~~~eaiRtl1~fi&t256 bYtes Of
the' nIle nodespace,'
is des~tedlls tlte;~~e,cs~. s~c~;'1'¥!¢st tticati0nsin~'CS~ node
spa~'are~use4~ Wheria~ad'tYpe~ommand8,~sses the un~~16catiorls, the~ttc tespOnd~by
wftich
readiri3.r.eros.. When . ~'.write;typeCQfD~nd aCc~$sestb~un#a:lOc~tiotl$, th(!BHCacrePt~the
c§~M but ignorl!s' ~data, F~ 5sllowsthe S:lrC':kgistet~ormatandthe ~s
aSsignments.
'
'.
., '. .
,. . ".
...'
'., , ,...
.,
4·19
Preliminary .
31
24 23
.'....
,
..
00
""'.'
'
----
OEVICEREGISTER
AESEAVED
bb+04
VAx'SI cONmqL lSTATUS REGISTER
BUS ERROR ReGISTER
bb+08
bb+OC
16 15
.:'
bt)+OO
ERROR INTERRUPT CONTROL
ERROR VECTOR
....
,
\
bb+10
RESERVED
bb+14
IP INTERRUPT
MASKREGISTER ..
•
r•
RESERVED
bb+18
RESERVED
FORGe IPINTRISTOP DESTINATION
bi)+1C
IP INTERRUPT SQUACEReGlSTER
;
INTERRUPT DESTINATION
:
STARTING ADDRESS .
bb+2O
UNUSED
ENDING ADDRESS
bb+24
bb+28;
.'
,.
UNUSED
BCI(:ONlTROl/ STATUS REGISTER
'.
WRITE stATUS REGISTER
bb+2C
--
bb+30
bb+34
I.'
.
FORCE IPINTR~P COMMAND
UNUSED
;
bb+38
UNUSED
bb+3C
UNUSED
bb+4Q
..
RESERVED
,
"
.'
USER INTERFACE INTR CONTROL
VEqroR .'.
, bb+44
UNUSED
bb+EC
--
bb+FO
GENERAL PURPOSE REGISTER 0
bb+F4
GENERAL PURpq5EREGISTER 1
bb+FB
+
bb+FC
GENERAL PURPOSE REGISTER 2
+
GENEFIAL PURPOSE REGISTER 3
•
+
.'
Figure 5 • VAXBI 78732 BIle Registers and Address Assignments
The I}IIC l,"egist~rs can be accessed by a VAXBI transaction from a node to its associateq BItC or to a
BIICassociate,4 with another node or by a loop1;>ack trans~j()n from the' lllaster-lX?rtipterface, of a
nod,e. When the registers are li\ccessed bya lo()pba~kco111mand fromamaster-port int~rfaceorby a
VAXBI trans~ipn, ,the high-o~erhits BI I) <':'2<;):13> of theaddte~sd;tat select theri~~ ~dclress
spaCe are ignored hUhe BIlC. Thelow-o~erhits (0 < 12:01 » cletetmlne whetherani~ternal
regist~r isselected. A register is selected when bitsD < 12:0S:>
equal to zero and the.l1!maini~
bits D < 07 :00> specify the register to be accessed.
.'. .
.....~
are
4·20
Confidential and Proprietary
-
Preliminary
l
VAXBI78732
The Blle supports write-mask transactions but does not support t e lock functionality for the
internal registers. The interlock-read with cache intent (IRCI) transac~ion isperformed as a normal
read transaction and the unlock-write-mask with cache intent (TJWMCI) transaction is performed
as a write-mask transaction.
I
I
BIle Registers Description
The register description tables contain a code in the "Type" column that defines the type of bits in
the register. '!able 13 lists the codes and definitions.
Table 13· VAXBI 78732 Rep.- Type Codes
Type
Definition...
DCWC
Cleared following a successful self-test when the Bet DC W signal from the BIlC is
deasserted.
DCWL
Loaded on the last cycle in which BCI DC ill is asserted. Set if the BCl signal lines are
not driven during this cycle.
DeLOS
Set following a successful self-test.
DMW
Can be written during the BIlC diagnostic mode which is reserved for use by Digital.
RO
Read-only.
R/W
Normal read/write
SC
Special case. Defined in the VAXBISystemRe£erence Manual.
S10PC
Cleared by a S10P command rothe node.
S10PS
Set by a Stop coIlllllarid to the node.
WIC
Write-l.to-clear. Cannot be set by the user's interfa<:e:
NA
Not applicable.
DS
Disables selection.
'"'Set refers to high level and clear refers toa low level.
Device Register-The device (DTYPE) register contains information to identify the node. It
consists of a device revision and device type field that are loaded from the BCI D < 31:00 > lines
during the last cycle in which the Be! DC ill line is asserted. The register will be set to all one bits if
the information the BCI D < 31:00> lines is not present when the BCI DC W line is asserted.
Figure 6 shows the format of the register information and Table 14 describes the bits.
C9n£idential and. Proprietary
4-21
11• •
VAXBI78'732
1615
31
()()
bb+ol~________D_EV_I_C_E_R_E_V_IS_'O_N________~____~__D_E_V_I_CE__TY_P_E________~
Figure 6· VAXBI 78732 Device Register Format
Table 14 • VAXBI 78732 Device Register Description
Bit
Type
Description
31:16
R/W, DMW,
Identifies the revision level of the device
DCWL
15:00
R/W, DMW,
Identifies the type of node
DCWL
Control and Status Register-The VAXBI control and status register (VAXBICSR) contains
interface identification, error and control information. The register information is shown in Figure
7 and described in Table 15.
31
bb+41
VAXBI INTERFACE REVISION
VAXBI INTERFACE TYPE
HARD ERROR SUMMARY
SOFT ERROR SUMMARY
INITIALIZE
BROKE
16 15 14 13 1211 1009 08 07 06 05 0403
2423
I
I
I I I I I I I I II I I
0
I
SELF·TI;STSTATUS
NODE FlESf;T
UNLOCK WRITE PENDING
HARD ERROR INTR ENABLE
SOFT ERROR INTR ENABLE
ARBITRATION CONTROL
NODE ID
Figure 7· VAXBI 78732 Control andStatus Register Format
4-22
Confidential and Proprietary
00
I
Preliminary
VAXBI78732
Table 15. " VAXBI 78732 VAXBI Control and .Status Regi¥er Description
Bit
Type
Description
31:24
RO
IREV (Interface revision)-Indicates t~ revision level of the BIlC.
The content of this field is incremented for each major revision.
23:16
RO
ITYPE (Interfacetype)--Contams the following code (0000 0001).
15
RO
HES (Hard error suffimatj}-Set todndicate that one or more hard
errors bits in the bus error register are set.
14
RO
SES (Soft error summSry)-Set to indicate that one or.more. soft error
bits are set in the bus~r register.
13
WIC,DCWS
STOPS
INIT(Initialize)~Implementationdependent.
12
WIC,DCLOS
BROKE (Self-test faW-Set to indicate that the BIIGclid not ptaSs tpe
self-test routine.
11
R/W,DCWS
STS (Self-test status)-Set to indicate that the BIlC has passed the selftest.
10
SC
NRST (Node reset)""':'Set to initiate a complete node self-test. Reading
this bit returns a zero. The STS bit is automatically reset by the BIlC
when this bit is set to allow the recording of the new test results.
09
RO
Reserved and cleared to zero.
08
WIC, DCLOC,
SC
UWP (Unlock write pending)-Set to indicate that an interlock read
With cache intent (IRCn t:ransaction~as been completed by the master-
I
port interface at this node and ~.~e 'has not issued a subsequent
unlock write mask w#h cache intent (UWMCI) command. Cleared by a
master-port lJ\'Q]ldCl transactio11 thatltas been successfully completed.
If a UWMCI transaction isattetripted'by the roaster-port interface
when this bit is not set; the ISE bit in the bus error register will be set.
07
R/W, DCLOC,
STOPC
HE IE CHard error interr:upt enable)-Set to enable the generation of
error interrupt when HES(bit 15) is Set. '.
06
R/W,DCLOC,
STOPC
SEIE (Soft error Intel'l"Upt enable}--Set to enable an error interrupt to
be generated when SES (hiH4) is set.
05:04
R/W, DCLOC
ARB (Arbitration cootrol}-Indicates. the mode of arbitration to be
used as fQIIows:
Bit
Desa-iption
03:00
RO, DMW,
DCLOC
:;
4
o
o
0
1
0
1
1
1
Dual round robin ~u:bitration
Fixed high priority (reserved)
Fixed low priotitY(rese;rved)
Disable arbitration (reserved)
NODE ID (node identification)-Anidentification number assigned
to the node. This information is loaded from the BCI 1< 3:0> lines
during the last cycle in which the BCI DC ill signal is asserted.
Confidentilll·and Proprietary
4-23
l1lil1li
VAXB1787)2
Bus Error Register-The bus error regi~ter (BER) provides hard error and soft error indications,
and parity genefation controL AIl bitsfu the error register can be set during the VAXBI and
loopback transactions except where noted, The register information is shown in Figure 8 and
described in Table 16,
313029282726 2524 2322 21201918171615
bb+s!olllllill III II
NO ACK TO MULTI·RESPONDER COMMAND RECEIVED
MASTER TRANSMIT CHECK ERROR
CONTROL TRANSMIT ERROR
MASTER PARllY ERROR
INTERLOCK SEQUENCE ERROR
TRANSMITTER DURING FAULT
IDENT VECTOR ERROR
COMMAND PARITY ERROR
SLAVE PARllY ERROR
READ DATA SUBSTITUTE
RETRY TIMEOUT
STALL TIMEOUT
BUS TIMEOUT
NONEXISTENT ADDRESS
ILLEGAL CONFIRMATION ERROR
I
II
0403020100
"
0',
II I II
USER PARITY ENABLED
ID PARllY ERROR
CORRECTED READ DATA
NULL BUS PARITY ERROR
HARD ERROR BITS
<30:16>
SOFT ERROR BITS
<02:00>
Figure 8· VAXBI 78732 Bus Error Register Format
'lable 16 • VAXBI 78732 Bus Error Register Description
Bit
Type
Description
31
RO
Reserved and cleared to zero.
30
W1C, DCWC
NO ACK (No acknowledge)-Set when a master-port receives a no
acknowledge command in response to an INVAL, INTER, IPINTER,
BDCST, or RESERVED command.
29
W1C, DCWC
MTCE (Master transmit check error}-Set when the data transmitted
is different from the data received. During the transaction cycles in
which the master is the only source of data on the BI data path, the
BlIC verifies that the data to be transferred from the master is the same
as the data that the master receives. If the data is different, this bit is
set, This check is not performed when the encoded ID is transferred
.
from the master during embedded ARB cycles.
28
W1C, DCWC
CTE (Control transmit error)-Set to indicate that a node has detected
a deasserted state of the Bl NO ARB BI BST or Bl CNF < 2:0 > line
during a cycle when the node is attempting to assert the signal. No
check is performed during burst-mode transactions.
27
WIC, DCWC
MPE (Master parity error)-Set if the master detects a parity error on
the bus durfug a read-type or vector acknowledge data cycle.
4-24
Confidential and Proprietary
Bit
Type
Description
26
WIC,DCLOC
ISE (Interlock sequence error)-Set wh~ the node su(cessfully com·
plet(!s a unlock write-mask with cache intent (UWMCI) command and
no correspondinginterlacl<: read with cadle intent (IRCI) was previously iSsued.Theunlockwritepl;!ndingbit in the VAXBI control and
status register is m;)tller.
25
WI C, DClOC
TDF {Transmitter duting:£aplthSet.whenthe master or sb.~ detects a
p!.U:ity ettQr during the following cycl¢tin.which the master or slave was
responsibk #;lr ~·the ptopc?t':Wity on the VAXBI bus. This
bit is not set by parity errors ~t~. during loopback transactions.
\
"
VAXBl.78'D2
.I
I
-CQ1l1Illand/adQIess ~setPi~ ~ter
"""Read-~ ac.kilc>w~e da~FwI~~;i~t:'by the slave
-:-Wdte-type9aUl cyck,:s.,set by the ;nas~
-Broadcast ~.cycles set, by the. m~ter
- Vectoraclmow~c;dge data cy~l('!s.set.hy. the slave
-Embedded arbitration cycles with t:heencoded master identification
seth}\' the master
. ..'
.
24
WIC,DCLOC
23
WIC,DCLOC
WE Udeptification~t~t):Or}""!ffl:'When an acknowledge response
is not receivedfrom the master to indicate that the interrupt vector was
not received correctly.
CPE (Command parity error)-Set if a parity error is detected in a
collltIlalldfad,d¢ss cycl~ ofa VA;XBl o~.lpopgacktnln~qp-..
22
WiC; DCLOC
SPE (Slave parity error);.....$et whenaparityerrorisdetected by asltlve
duriPgR write-type atknowledge;i wtite-typestldk or btoo.dcast
. acknowledge data cycle.
21
WIC, DClOC
RDS (Read data substitute)-Set when read data substitute of reserved
status code is received during a read-type or vector status identification
data cycle. Valid parity must be received during both transactions.
20
" WIC,DCLOC 'RTO (Retry timeoutl-Set when tMmasteft'eCeives 4096 consecutive
retry.~$pon.ses fQrtbe$~mi:~h;i ~t~ trap~c~ion.
19
WIC,DCLOC
SID (Stall timeout)-:-Set when the s!aveportasserts the stall code
information on the BCI RS <'1:0 > lib:e~£()r!l,28~onsecutive cycles.
18
WIC,DClOC
RIO (Bus timeout)-Set when thenodeJ~t01riitiate one of several
transaction that are pending befQte4096cycles ~e elapsed.
17
WIC,DClOC
NEX (nonexistent addiessJ2..Set when the node~ceives a no acknowledge response for a re~d-typeor wri~·type command after a successful
parity check of the node and masterpin-ity clieekhas occurred.
16
RO
ICE (illegal confirmation error)-Set by the master or slave node when
a reserved or illegal confirmation code is received by the BIlC.
15:04
RO
Reserved and cleared to zero
4-25
__--.-------.---.-----.------
-------------_.•.
,~-
_
.
.. -"".-.-.. -~ ....
_....
__
... _.. -
VAXB178732
Bit
Type
Description
3
RO, DCLOC
UPEN (User parity enable)-Indicates the parity mode of the BIlC. Set
to indicate that the user's interface will generate parity. Cleared to
indicate that the BHC will generate parity. The user's interface provides
parity on the BCI PO line when data is requested from the user's
interface. The levels are reversed from those on the BCI PO line.
2
WIC, DCLOC
IPE (Identification parity error)-Set if a parity error is detected on
the BI I < }:o > lines when the encoded ID of the master is asserted
during embedded arbitration cycles. This bit is not set during loopback
transactions.
1
WIC, DCWC
CRD (Corrected read data)-Set when the master receives a corrected
read data status code after valid parity has been received. Valid parity
must be received during the data cycle that contains the corrected read
data code. This bit is set although the transaction may be aborted after
the status code has been received.
o
W1C, DCLOC
NPE (Null bus parity error}-Set when odd parity is detected on the
bus during the second cycle of a two-cycle sequence during which the
'BIARB and BI13SY signals were not asserted.
Error Inteil'mpt Control Register-The error interrupt control register (EINTRCSR) controls the
operation of the interrupts initiated when the BIlC detects a bus error or when the force bit in this
register is set. An error interrupt request can be initiated provided the appropriate interrupt enable
bit in the BIlC control and status register was previously set. The register information is shown in
Figure 9 and described in Table 17.
31
bb+C
252423 ·2221
2019
1615 14 '13
o
O's
INTR ABORT
INTR COMPLETE
INTR SENT
INTR FORCE
LEVEL 7:4
VECTOR
Figure 9· VAXBI 78732 Error Interrupt Control Register Format
4-26
020100
Confidential and Proprietary
0
...
Preliminary
Bit
Table 17- VAXBI787:J2 Error Interrupt ConttolRegist'ef Descripdotl
Type
Description
31:25
RO
Reserved and cleared to zero
24
W1C,DCLOC,
SC
INTRAB (Interrupt abort}-Set by the BirC when an interrupt command initiated by this register is aborted. A command is aborted when
no acknowledge or an illegal confirmation code is received. When set,
the BIlC is not inhibited. from initiating or responding to subsequent
interrupt or identification transactions, This bit is cleared by the user's
interface,
23
W1C,DCLOC,
SC
INTRC (Interrupt complete)-Set when the vector for an error interrupt has been successfully transferred or when.an interrupt command
transfel'tedundel' thecontl,"QiClf' thisregisterisabo~d. This bit is
cleared when the error interrupt~uest has been removed: When set,
no interrupts can be.generatedhfdii:s register. When this bids set, this
register will not iespand to identifkatmn transactions.
22
RO
Reserved and c1earedto zero.
21
W1C,DCLOC,
INtRS (InterruPt;sent}~Set· wherl#tinterrupt command has been
sent, Removal o£the ~rror interruPt~~u~st will clear this bit during an
identification trallSl1Ctio~foU~d~e detection of a level match and a
master identi£ic;9,twn~atch. When~, the interrupt can be sent
theidentiEicatiOnarbitration odf the node wins
again if the node
the arbitration but the vector transmission fails.
STOPC, SC
loses
20
RfW,DCLOC
STOPe
INTRF (Interrupt force)-When set, an error interrupt is posted the
same as in the bus error register except that the request is not qualified
by HEIE bit7 and SlUE bit 6 in tne control and status regiSter.
19:16
RfW,DCLOC
LEVEL 7;4 (InterruPtcot1unatKll~G~dicates the leve!(s) at which
the interrupt commands under corttrol initiated by this register are
transferred.
15:14
RO
Reserved .and cleared to zero
13:2
R/W,DCLOC
VECTOR (Error interrupt vector)-Contains the vector used during
the error interrupt sequence.
.
01:00
RO
Reserved and cleared to zero
Confidential and Proprietary
4-27
VAXBl78732
Interrupt DestinatiC)n,Re8iSbel.....The. interrupt destination (lNTRDES) register identifies the
nodes that have been selected by the interrupt commands. The destination is transferred during
the interrupt command and is monitored by all the nodes todetetmine which node isto respond:
The register information is shown in Figure 10 and described in Table 18.
31
1615
00
bb+l01~__~_________O_'S____________~______IN_T_R_._D_ES_T_IN_A_T_1_O_N______~
Figure 10· VAXBI78732 Interrupt Destination Register Format
Table 18 • VAXBI 78732 Interrupt Destination Register Description
Bit
Type
Description
31:16
RO
Reserved and cleared to zero.
15:00
R/W, Dewe
INTR DEST (Interrupt destination)-During an identification command, a node compares the decoded identification from the master
with the coded information in this field. When the information code is
the same, this node responds to the identification sequence provided
that the· unserviced interrupt request is the same level as the level
transferred during the identification command.
Interprocessor Interrupt Maslt Register-The interprocessor (IP) interrupt mask (IPINTRMSK)
register identifies the nodes that are allowed to send interprocessor interrupts to the BIle. The
register information is shown in Figure 11 and described in Table 19.
31
1615
bb+141~________IP_I_N_T_R_M_A_S_K________
- h_ _ _ _ _ _ _ _ _ _ _ _O_'_S__________
00
~
Figure 11- VAXBJ 78732 IP InterruptMask Register Format
Table 19· VAXBI 78732 IP Interrupt Mask Register Description
Bit
Type
Description
31:16
R/W, Dewe
IPINTR MASK (lnterprocessor Interrupt mask)-When a bit in this
field is set, the interprocessor interrupts directed to the BIle from the
corresponding node will allow selection provided that the IPINTREN
(bit 5) of the Bel control and status register is set.
15:00
RO
Reserved and cleared to zero.
4·28
Confidential and Proprietary
-
VAXBI7S732
,
Force-Lit IPINTR/S1'OP, Destinatiott Register- The force-bit interpnkessor interruptJ~top destination (FlPSDES) register idenrifiesthe nodes that will receive the fotte.hit. inteJt:l:rt>ce!iSor
interrupts or stop commands issued by the BUe. The register informjltion is show~ in Figure 12
and described in Table 20.
.
,:
i
31
1615
00
O's
bb+18
Figure 12- VAXBI78732 Force-bit IPINTRISTOP Destination Register Format
Table 20· VAnI 78732 F~e·bit IPINTlVSTOP ~tinatiQn ~Oescription
31:16
RO
Reserved.and cle~dto zero.'
15 :00
R/W, DCLOC
FORCE-BIT IPiN'nU§rop D.ESTJPQrce-bitinterprocessof interruptI
stop destination)....,;.Cotrunarid/addressinformatiOl1proVicies bytbe
user'sinterface Lf6tt/le maSter·pottinterprocessor interrupt transactions.
Interprocessor Interrupt Source Register-The interprocessor interrupt source register (IPINTRS)
stores the decoded identification of a node tbatsends aninterprocessodnterrupt command to the
BIIC. The register information is shown in Figure 13 and described in Table 21.
1615
00
bb+1C~I_______I_P~IN_T~R_SO__UR_C_E____~~I~.
______~I
31
__________~o'~s~
Figure 13,' VAXBI 78732IPJnfe~pt Sourpe ReFhter Format
Table 21 • VAnI 78732 IP IntemJpt Source Register Description
Bit
Type
Description
31:16
WIC,DCLOC,
SC
IPINTR SOURCE (Interprocessor interrupt source}-Each bit in this
field corresponds to one node and is set when the destination of an
interprocessor command to the BIlC is the same as the identification in
this field.
15:00
RO
Reserved and cleared to zero.
Confidential and Proprietary
4-29
. .II
VAXBI787,2
Starting Address R.egistet- The starting address register (SADR).defines:thestarting address a
256-Kbyte. block of storage in a memory space or ··1/0 space excluding· node space or· multicast
space. The end of the block isde£ined by the ending address register. If the value of this address is
greater than the ending address value, the address will not be recognized. The register information
is shown in Figure 14 and described in Table 22.
00
1817
313029
bb+20~lo~I_OLI____ST_A_R_T_IN_G__A_DD_R_E_~__~~_____________~_s____________~
Figure 14· VAXBI 78732 Starting Address Register Format
'laMe 22 • VAXBI 78732 Starting Address Regis~r Description
Bit
Type
Description
31:30
RO
Reserved and cleared to zero.
29:18
R/W, DCWC
START ADDR (Starting address}-Identifies the address of the first
location of a 256-Kbyte block of storage to be recognized by the BIlC
for selection of the slave port.
17:00
RO
Reserved and cleared to zero.
313029
00
1817
ENDING
ADDRE~
O's
I
Figure 15· VAXBI 78732 Ending Address Register Format
Ending Address Register-The ending address register (EADR) defines the last address of a 256Kbyte block of storage in a memory space or I/O space excluding node space or multicast space.
The starting address of the block is defined by the starting address register, If the starting address
value of this address is greater than the ending address value, the address will not be recognized.
The register information is shown in Figure 15 and described in Table 23.
4-30
Conficlential·and Proprietary
VAXBI78732
. '.&h!tt.ll· VAXBI 78732 Ending Address ~$ter ~on
!
Bit
Type
Description
31:30
RO
Reserved and cleared to zero.
29:18
R/W, DCLOC
END ADDR (Ending address)-Specifichlanad<;hess valu~ that is
by one than the. highesta~~s recognized by the BIle for
:;election by the s~e.port.Thi.':~dte!is m\lSt be the first location of the
.• gteatel'
256·Kbytehlock ot addresses. If.~ /itarWtg address register contains
the value 1~44 OOoo.~decltruVJ:> ancl the ending address register
cqntains thev;due. 1.068 .OPOQ.(~ePmal), then the BIIC will
recognize addresses lC44000 thJ:()ug.h 1D67 FFFF for selection of the
slave port.
17:00 . RO
.
.
. ..
Reserved and cleared to .zero;
BCI· Contt:ol and .·8.,'IU5 .Register--The BCI conttql andsta~s . register (BCICSR) contains
command. enable bitst after a BDCST command has been received.
13
R/W,DCWC
SlDPEN (Stop enable)-When set, the BIlC asserts the BCI SEL DS
line and transfers the appropriate slave code on lines BCI SC<2:0>
after aSlDP command has been received.
12
R/W,DCWC
RESEN (Reserved enable)-When set, the BIlC asserts the BCI SEL
line and transfers the appropriate slave code on lines BCI SC < 2:0 >
after a RESERVED command has been received.
11
R{W,DCIDC
IDENTEN (Identification enable)-Whenset, the BIlC asserts the
BCI SEL line and transfers the appropriate slave code on lines
BCI SC <2:i» after an identification command has been received.
The BIlC will participate in an identification transaction to this node
when this bit is cleared.
10
4·32
R/W,DCLOC,
DS
INVALEN (Invalidate enable)-When set, the BIlC asserts the
BCI SEL line and transfers the appropriate slave code on lines
BCI SC < 2:0 > after an INVAL command has been received.
Confidential and Proprietary
Bit
Type
09
R/W, DCLOC,
SC
08
R/W, DCLOC,
SC
07
R/W, DCLOC,
SC
WINVALEN (Write invalidenab1e)-:-~tn set, the BllCasserts the
BCI SEL line and transfers the appropriate slave code on lines
BCI SC < 2:0 >. This occurs after the./BIIC receives a write-type
command with anaddres$ nQtwithin the .range of .the starting and
ending address register values and not within the I/O space.
UCSREN (User's interface CSR· sPace enable)---When set, the BIlC
asserts the BCI SEt~lllld~~~~ ilieappropriate slave code on
lines BCI SC < 1:6,:>af~~¢i~~. ~7 .or write-type command
directed to the cOntrolant;ls~~ter in ~ user's interface.
BICSREN (BIlC control/states register space enable)-When set, the
BIICasSerts theBCISEL line antHr~ns£er'S'the appropriate slave code
on lines BCI SC <1:0 > after receiving a read- or write-type command
directed to the control and status register in the BUe. The BIlC always
p~paU;~
06
R/W, DCLOC,
INTR.E:N (Intemtpt ~nable)-When s~.Jhe BIIC asserts, the BCI SEL
DS
li11:eand transfers the appropriate slave code on lines BCI.SC < 2:0 >
after receiving aread·
or wnt¢:i:~ command directed to the BIIC. '
..
R/W, DCLOC,
IPINTREN (lnt~~sol'~pt;enable)-When set, the BIlC
assertstlleBCI SELlineandtra,Qsferstheapprop~te slave code on
lines S.¢t sl'! ~ 2:0>~ receiv~gan IPINTR command from a node
that is included. in the itl.~etptocesSor~pt mask registe1: The BIlC
receives the lPINn.cO.nQl~'rf;gafaleSs of the S,tate of this bit.
,'"
05
41 t.I;aps~cti;9ns that~sthis$~.
SC
"
,
'
"'"
,'.,
"
':
'{;,
""
,
04
RjW, QCLOC,
NA
PNXTEN(kiPffine~rellilhle) __\vhen set,thelUIC provides an
additional next>4~ta,':V?n:l ~e ,.~·.Vie last longword is transferred
during write-typeiindHroadCtist. t~il¢tions, Thiscyde can be used to
transfer poitl.$tofirst~in/first~tctF'IFO) buffers in the ttmster port:
03
RjW, DCLOC.
NA
RTOEvEN (Retry>tilneout'~~ble)':'-When set, the BIle transfers a. retry timeout (R'rO) Wte'aao£ ~ ccmfirmation receivedfor
master-port colmnanchRCR)eventcode.on lines BCI EV <4:0 >afttr
a retry timeout has occu:rred. Ifthis bifis cleared, the RID bit in the
bus error register will be set and an error interrupt will be generated if
enabled.
02:00
RO
Confidential and Proprietary
4-33
•.
~---."-------.-.--.---.--~---------.-----------
·-
Prelimirtary
VAXBI78732
Write Status Register-The write status (WSTAT) register indicates which of the general purpose
registers have received information during a write VAXBI transaction. The registerinformation is
shown in Figure 17 and described in Table 25.
3130292827
bb+2C
00
I I II I
II
I
D's
GENERAL. PURPOSE
GENERAL PURPOSE
GENERAL PURPOSE
GENERAL PURPOSE
REGISTER
REGISTER
REGISTER
REGISTER
0
1
2
3
Figure 17· VAXBI 78732 Write Status Register Format
Table 25 • VAXBI 78732 Write Status Register Description
Bit
Type
31
WIC, DCWC
Description
GPR3 (General purpose register 3)-Set by a write VAXBI transaction
to general purpose register 3 if valid parity is received. This bit is not
. set by loopback transactions.
~--------------~~------
,0
WIC, DCWC
GPR2 (General purpose register 2)-Set by a write VAXBI transaction
to general purpose register 2 if valid parity is received. This bit is not
set by Ioopbacktfansactions.
29
WIC, DCWC
GPRI (General purpose register 1)-Set by a write VAXBI transaction
to general purpose register 1 if valid parity is received. This bit is not
seiby loopback transactions.
28
WIC, DCWC
GPRO(General purpose register O)-Set by a write VAXBI transaction
to general purpose register 0 if valid parity is received. This bit is not
set by loopback transactions.
27:00
RO
Reserved and cleared to zero.
Force-bit Interpro<:essor Interrupt/Stop Command Register-The force-bit IPINTRjSIDP command (FIPSCMD) register allows an interprocessor interrupt or stop transaction to be initiated
when one of the interrupt force-bits in the user interface interrupt control register is set. The
register information is shown in Figure 18 and described in Table 26.
31
1615
bb+30LI____________O_.s__________
1211 10
~L-_.--~I~I--------o.-s------~
COMMAND
MASTER ID ENABLE
I
Figure 18· VAXBI 78732 Forre-bit IPINTISTOP Command Register Format
4-34
00
Confidential and Proprietary ,
VAXBI78732
Bit
Type
Description
31:16
RO
Reserved and cleared to zero.
15:12
R/W, DClOC
CMD (Cotnmand)-lrtdkates tb£4-bit com.fIland code used to initiate
an interpro&ssor interrupt or stol' transaction when one of the
interrupt force"bits the User interface mterrupt control register is set.
m
The oomtruuid l:Qdes' are
~d
Bit
14
1
1
Jj
1
l'
11
13
1
0
12
1
0
IPINTR (Interptocessor interrupt)
STOP
, ,~
R/W,DClOC
MIDEN (Master~dentUicatiQnena1?l~).,.....,Set to enable the master
RO
coIJllllfllld field (bits;l5:12) con~,~tdnterprocessor command code
during the command/address cycle. When the command field contains
a STOP command, this hit should becl~ared;
Reserved and clea~to zero" ,
idenri£icationtqQe,t~en-¢d on>the~II><31:00> lines when the
,~,"
10:00
,',
'
",;'
,
'c·
"
-,..
"
."
,'_"
User In.face Interrupt Conuol Registet"":1'he user' interface interrupt control register
(UNITRCSR)conttolsthe operation of the intert\ipts imtlated by&.e'user's interface. The register
information shewn in Figure 19 and descdb&tlinTable 27: T~ interrupt request referred to in
Table 27 arelDterrupts initiatedhy theBeI INto< 7:0,> ,lines Or' by $e,tting theforce,.bits in this
register.
is
020100
o
Confidential and Proprietary
..
--~----.--------.-'- -.-----~-~~-~--------,-----
0
4-35
----,-,-------"
-
Table 27 -VAXBI 78732· User Intetfaee.Interiupt Control Registet DeseriptiOn .
Bit
Type
Description
31:28
W1C, DCLOC,
SC
INTRAB (Interrupt abort 7:4)-These bits correspond to interrupt
7 through 4. A bit is set when an interrupt command sent under
control of this register is aborted causing a no acknowledge or illegal
confirmation code to be received by the BIle. Cleared by the user's
interface. The state of this bit does not prevent the BIIC from
responding to other interrupt or identification transactions.
27:24
Preliminary
W1C, DCLOC,
SC
VAXBl787j2
l~Is
INTRC (Interrupt complete 7:4)-'lhese bits correspond to interrupt
levels 7 through 4. A bit is set when the vector for an interrupt has been
successfully transmitted or when an interrupt command sent under
control of this register is aborted. When a bit is set, no additional
interrupt requests at the level specifIed will be generated. No response
to identification transactions will occur when this bit is set at the
IDENT level. A bit is cleared when the corresponding interrupt request
is removed.
23:20
19:16
W1C,DCWC,
SIDPC, SC
SENT (Interrupt sent)-These bits correspond to the interrupt levels 7
through 4. A bit is set when an interrupt command for the corresponding level has been successfully transferred. This bit is cleared during an
identification command that follows the detection of ~ level and a.
match of the master identification. This bit is cleared when the
interrupt request is deasserted. When cleared, an interrupt request can
be sent again if the BIlC has lost the identification arbitration or if the
.. BIlC has won th~ arbitration but the vector transmission failed.
R/W,DCLOC,
FORCE (Interrupt force 7:4)-These bits correspond to interrupt
levels 7 through 4. When set, the BIlC generates interrupts at the
specified level. Setting a bit is equivalent to asserting the corresponding BCI INT<7:4> line. When multiple interrupt requests are
asserted simultaneously, theBIIG transmits the interrupt command for
the request with the highest priority first. The BIle responds with the
highest pending priority when an identification command solicits
more than one level.
SIDPC
15
R/W,DCLOC
EX VECTOR (External vector)-When set, the BIICsolicits the
interrupt vector from the BCI D< 31:00 > lines in resJlOnse to an
identification transaction to select this register. The slave port transfers
an external vector selected (EVS) level during the cycle preceding the
vector transfer on the BCl D < 31:00 > lines. A slave-port interface that
. is using the BIlC must st1ll the vector by transferring a stall code on the
BCI RS < 2:0 > lines for at least one cycle during the identification
arbitration cycle before transmitting an acknowledge (with vector) or a
retry response.
Confidential and Proprietary
Bit
Type
Description
14
RO
Reserved and cleared to zero.
13:02
RfW,DCLOC
VAXBl78132
., VECTOR (Interrupt sequence vector)-C~ntains the vector used dur-
ing the user's interface interrupt sequences except when the external
vector bit 15 is set. The vector is transferred when the BIIC wins the
identification arbitrati<;m that is the same as the conditions specified
by the user interfacemterrupt control register.
Reserved and cleared to zero.
RO
01:00
('Jenera! Purpose Registers
The BIIC contains four general purpose registers (GPRO through GPR3) that are available to the
user and are implemen~tion specific. The type of bits in thi;!sf! t(!gi~ters are RfW a:Q,d DCWC.
When information is written toa GPR, theWl'ite statusi:egiStet,'identifiesthe'SPR that received
the information. Figure 20 shows the register format.
31
00
...
' "
.
, bb+FO
GENERAL PURPOSE Ri:GISTER 0
bb+F4
bb+F8 ....,
bb+FC
G~.Nf;:RAl"PlJflPOS!:
. ..
f}l:GU)'T!:R;2:
r---------------------~----~----
GENERALPU~~6s'E
REGISTER 3
.:.
..
__
--------~
'
Figure 20· VAXBI78732 qeneralPurpose Register Format
Confidenti,al.;.mdJ?roprietary
.....
_
....•. _.
".-~.--.---.
,---
4-37
-
Preliminary
Slave.onIy Status Register
. .
The slave-only status register (SOSR) is located out of theBBIGCSR space and is used by slave
nodes that have a device-type code and contain zeros in bits 14:08. The register format is shown in
Figure 20A and the information is defined in Table 27A. The Broke bit and Memory Size (MSIZE)
field must contain valid information. This is III read-only register andnlUst not be written into.
31
bb+
1001
2928'
1817
I
I
MEMORY SIZE
BROKE
131211
II
o
I
Figure 20A • VAXBI 78732 Slave-only Status Register Format
1Bble 27A • VAXBI 78732 Slave.onIy Status Register Description
Bit
Type
31:29
28:18
Implementation dependent
RO
17:13
12
11:00
Description
MSIZE (Memory size)-A binary number that indicates the size of
memory as a multiple of 256 Kbytes.
Implementation dependent
RO,SC
Broke-Set by the user's interface before BCI DC ill from the BIlC is
deasserted to indicate the failure of the node to pass the self-test. Must
be cleared by the user's interface upon the successful completion of the
self-test.
Implementation dependent
Receive Console Data Register
The receive console data (RXCD) register, implemented by VAXBI nodes that have a console
terminal on the VAXBI, is used to receive data from other consoles. Nodes without a console must
issue a no acknowledge response to read commands to this register or return a longword with the
Busy 1 (bit 15) set before the Broke bit of the slave-only register is cleared. The RXCD register
responds to longword VAXBI bus transactions directed to this register. If the RXCD register is in a
primary console node, a lock bit must be implemented in the interface. When the optional upper
word of a unlock write with cache intent (UWMCI) command to this register is not used, the mask
bits can be ignored (assumed to be all set).
The register format is shown in Figure 20B and the information is described in Table 27B.
4·38
Confidential and Proprietary
, , VAXBI78132 '
btl" 209
BUSY2~----~-r--~----.-----~~~~--r-~----~----~
NODE 102
CHARACTER :I
BUS¥ 1
NODE 10 1
CHARACTER 1
OPTIONAL
REOUIRED
<31:,16>
Figure 20B· VAXBI 78732 Receit!tCotlSQleData Register Format
Bit
'&ble,27B· VAXBI 78732 Reeeive.('.c)nsole 0.18 Register Ilescription
Type
Description
" ,
31
R/W
Busy 2-Set to intli.8liethat th~ character 2 (CHAR 2)fie1d (bits 23:15)
has not been read bytheremot;e node. This b~trnustbe cleated before
CHAR 2 is available£ot anOther' character. .
30:28
RO
27:24
R/W
~am:lcle~tO zeros. '
I!,
NODE ID 2 (Node identification 2)-Containsthe identification of
the local node that sel}t information to the Character 2 field.
23:16
R/W
CHAR2,(Chara~4)-contains the console command character or
console message Sent fron,. the local to the remote node.
15
R/W
:aUSY, l-Settojndicate that,thechara~r 1 (CHAR 1) field (bits
07 :00) has not been read by the remote node. This bit must be cleared
before CHAR 1 is available for another character.
14:12
RO
Re~ed and cleared tozero~,' ,',
11:08
R/W
NODE ID 1, (NOOt: idehtificarien2)"""'Contains the identification of
,J
the local node that: sent information'to thcfChtracter 1 field.
07:00
R/W
CHAR l' (Cha.racteil)-Contailisthe consol~ command character or
consol~ message sent from the localto the remote notte.
.
. VAXBlIntetface Node
Figure 21 is a diagranl of ,a V~l'node th,at si)f!WS thecopn~ng lines an<;lsigna4~,tweeQ. th~
,
'
BIlC and master~port and slave-port user'sinterfaces, aJ.'V.l b~n the BIle andVAx.sfbus. The
BIlC t;l~es ar@ matc:hc:s theaddtes~s from .the VAJq3I!?us and~rforms all arbitration
fu~ns between the VAXBI busandthel,\IIC. It Includes the primary receiver and l'totocollogic
required to, interface to, .the VAXBI. qus.l,l.nd all'VAXBI bus transceivers a5S9ciated with the, data
transfers and most of the bus receivers. The master-porta.nd ,slave-POrt interfaces communicate
with the BITC through the synchronous interface BCI bus. The SCI bus consists of 64 linestha~
transfer data, address, and control information to and from the BIle. The user's interface can
request transfers through the BCI bus under control of the BIlC.
Confidential and Proprietary
4-39
-
USER INTERFACE,
BIIC
VAXBIB US
BCIBUS
Ir
MASTER
PORT
INTERFACE
l!
'"'BIl.mV
61 NoARS
BI GNF
"
BCI0<31:oo>
=-
SLAVE
PORT
INTERFACE
"ll5i3:O
R81ASE8
Bleg L
'BI
L
B81 ~S~4:0>
:=
BI0<31:00;;-
BCII<3:0>
>
8
SCI RS<1:0>
~
~
-----INTERRUPT
PORT
INTERFACE
t
BCI SC<2:O>
BC/INT<7:4>
BCI TIME L
BCI PHASE l
f
l
I
FROM VAXBI CLOCK RECEIVER
Figure 21· VAXBI 78732 Intet/ace Node Connections
The BIle can detect and transfers commands fromthe VAXBI bus tothe master-port or slave-port
interface. In a multiprocessor environment, the addresses transmitted on the VAXBI bus are
available to the user's interface for monitoring cache invalidate transactions. The BIle supports the
transfer of information between the master and slave within a single node.
Data and address information is transferred between the user's interface and the BIle through the
time multiplexed three-state Bel D < 31:00 > lines. Commands are transferred through the Bel
1< 3:0> lines. The direction control is provided by the BIle. The master-port interface initiates
command sequences by transferring a code on the request BCl RQ lines and the BIle
responds by asserting the appropriate enable signal that transfers the command information to Bel
bus. Command and data confirmation is transferred from the user's interface to the BIlC through
the response lines. Transaction status is transferred to the user's interface through the event BCI
EV <4:0> lines. Several registers in the BIle control the operation of interrupt requests.
Interrupts can be generated by asserting one of the BCI INT < 7:4> lines or by writing
informationinto one of the interrupt control registers, TheBliC provides vector information from
an internal register in response to an identification command or it can solidt vector information
.
from a user's interface.
4-40
Confidential and Proprietary
-
VAXB1.7.8"132 . .•
Master-port Tran~dons
The master-port BCI signals are used to generate internode and intranode transactions. Transactions directed toothertlodes are internocletransactions and are limitJd to longwords. Intranocle
transactions can be VAXBI transactions that are issued by the master Port through the VAXBI bus
or loopback transactions that are not transferred through the VAXBl bUs. These transactions can
transfer longwords, octawords, or quadwords.
The master-port interface requests a transaction by transferring a code on the BCI RQ < 1:0 >
lines. The BUC asserts the BCI MDE line to inform the user's interface that the command/address
information is required on lines BCI I <3:0 >' and BCI D <31:00 > . In subSequent cycles the BIlC
asserts the BCI NXT and BCI MOE lines to request the data &om the user's interface.
Slave-port Transacti9ns
The slave-port interface responds to read and write requests to. memory locations in this node but
not to transactions that access the BIlC registers. It''alsP.~lves commands directed to more than
one responder such as interrupt commands. The slave port will respond to all transactions directed
to it including more.~one transaction received sequentially. It can operate at the. sustained peak
bandwidth of the VAXBI bus if the user's interface is capable of this transfer rate.
Nodes that generate interrupts can use the interrupt port of the slave to request the transfer of an
interrupt and to respond with an external vector to an identification command.
• VAXBI Address Space
The VAXBI address spaCe is grouped into memory address space kx:ations andirlput/output (I/O)
address space locatio~. During the first cycle of a read.~, write-type, and invalid transaction, a
30-bit physical address A29:00 is transferred on the Btl) <29:00 > lines. Lin~ BI D<31:30>
specify the length of the transfer in longwotds•. When bit A2,9.is zero, the 512-Mbyte memory
space from 0000 0000 to 1FFF FFFF (hexadecimal) is accessed. When address bit A29 is a one, the
512-Mbyte I/O address space from 2000 0000 to 3FFF Ff'FF (hexadecimal) is seltfcted. The address
space allocations are s40wn in }1~22.
Con£i~ntial and.Proprietary
441
VAXBI78732
Hex Address
20000000
Node 0 Nodespace
(8KB)
2oo01FFF
··•
2001 EOOO
Node 15 Nodespace
(8KB)
2001 FFFF
20020000
Multicast Space
(128KB)
2003FFFF
20040000
Node Private Space
(3.15MB)
203F FFFF
Node 0
Window Space
(256KB)
···
Node 15
Window Space
(256KB)
20400000
,
2043 FFFF
207COOOO
207F FFFF
RESERVED
22000000
RESERVED
(for multiple VAXBI systems)
(480MB)
3FFFFFFF
Figure 22 • VAXBI 78732 Input/Output Address Space Allocations.
4-42
Confidential and Prop~etary
I
The VAXBI architecture defines the use of the I/O address space ,that contains node space,
multicast space, window space, and reserved space. Up to 16 VAXBI btJes can be accessed. Address
bits A28:25 define the mapping mechanism used to access these buses. If the I/O space is selected
and an address bits A28:25 is ones, a reserved location of 2200,0000 through 3m FFFFF
(hexadecimal) is selected.
I
The I/O spaces are selected by the address configurations shown in Figure 23. Two blocks of I/O
space are partitioned according to the identification of the node. The node space i&:Positioned at
the low end of the I/O address spai::e and coiisiSts)of 16 address bMs eaclt Cohtaining 8 Kbytes.
One nodespace is assigned to each node that can be implemented on the VAXBI bus. The first 256
bytes of each space consists of BIle control and status register space and the remaining space is
assigned to the user's interface control and status information. Thewllidow'splk:e starts at address
2040 0000 (hexadecimal) and contains 16 blocks of 256 Kbytes each and can be used by adapters to
map VAXBI transactions onto the selected bus.
Confidential. and Proptktar1
4·43
...
29
D-l!_= __
.· •
.L"~LU""-"
. ,
EJ 1I0'SI>A~
28
D
25
.
SPECIFIES WHICH VAXBI BUS
24.23
10
OI'F NOT
~RO BITS
24:23 lNDICATj;RESERVED SPACE
;/2
El
WINDOW SPACE
21
18
D
SPECIFIES WHICH NODE'S WINDOW SPACE
17
00
--II
LI_ _ _ _ _ _ _ _ _ _ _ _ _ _
WINDOW SPACE ADDRESS
22
G
NON-WINDOW SPACE
B
21201918
IF NOT ZERO BITS
21: 18
INDICATE NODE PRIVATE SPACE
17
EI
NODESPACE
16
13
DNODEID
12
00
IL._ _ _ _ _ _ _ _ _ _....JI NODESPACE ADDRESS
tl
17
MULTICAST SPACE
16
00
---'1 MULTICAST SPACE ADDRESS
1-1_ _ _ _ _ _ _ _ _ _ _ _ _
Figure 23· VAXBI 78732110 Space Addressing
4·44
Confidential and Proprietary
-
i
\
VAXBI78132
Node Space Assignments
Each node that irtterfaces to the VAXBI bus is assigned an identification number (node ID) of from
oto 15. The ID code determines the bus aild interrupt priority level as~ignments and the locations
of the node's regis~rs.The ID is selected by jumP,er lead connections on the VAXBI baCkplane.
Figure 24 shov{sthe node space allocations. ~!lSsignment Q£.the8-Khyte nodespacedepencIson
the type of node as defined by this ident1ficatioQ,.The. Stal'tWg j~<:Ire$s for a,node is 2000, .0000
(heXadecimal) plus 8K times the node Ip. The baSe addressisreterred to as .ibb."
VAXBI. REGISTERS
NODESPACE
(8 KBYTESJ
Figure 24· VAXBI 78732 Node Space Allocahan
The first 256 bytes ofa node space is re~erve~[£or t~ V~r~ters !:lnd the ~aiping space is
assigned tci user's irtt~ace control and s~~t:¢gi$~(PS!ts). ~CSR space (bb+l00) contains
slave-only status and is us.ecl by m~ nodes that do not im~eii~ the, ~roke bit of the VAXBI
control and status register. Location bb+200 is reserved for the receive console data register
(RXCD) and is implemented by nodes capable of perfoiming"trMsactions with the console
terminal. Nodes that do not have the console capability respond to read commands with a no
acknowledge or with a longword in which the RXCD busy (bit 15) is set.
Because the BIlC has one starting and one ending address register, a node canrtot'~po:nd with a
window space and region of memory space. Responses to multicast space and user CSR spate can
be disabled by the BCI control and StlttusregUtet'.
The BIIC can be configured to respond tb any combination of thef,onOwlng:
•
'
"
1 I
• The node space of t:he node
• The space defined by thestarting addressa'nde:ndi:ng ·addfess of· the node ..
• The multicast space
4-45
-----_._--
Preliminary·
• VAXBI Protocol and Cycle Types
The vAiBInod~s c(m~!lin arbitratio~~iogic. Each llod~.t>rovide,s two arbi~ation levels. To become
bus master, a node asserts one of the 32 data lines . lluring.1ll1 the arbitratio.n transaction and
monitors the remaining data lines to determine if a lower number line has been asserted. If no line
is a~rted,the nodebecotries.bus master Ill1d transfers command/address information immediately
or when theeurrent bus transaction if has been completed.
.
The BI NO ARB line controls access to the bus data path for arbitration. Arbitration can occur
during a cycle or after a cycle following the deassertion of this line. Arbitration cycles can occur
during a transaction or after a tflU1saction. The command/address information from the bus master
is decoded by the node during the next cycle.
Arbitration performed during a tflU1saction cycle is defined as an embedded arbitration cycle.
During the embedded arbitration cycles, all nodes update their arbitration priority according to
the arbitration mode and the ID of the current master. During this cycle, the master of the current
transaction transfers its encoded ID on lines BI 1< 3:0> and parity for these lines. From this
information, the nodes check the parity and calculate the arbitration priority. A master cannot
arbitrate during the embedded arbitration cycle its tflU1saction.
.
of
The node priority is transferred on lines BI D < 31:00 > during the arbitration cycle. Figure 25
shows the node ID assignment and priority level assignment. Lines BI D'< 31:16> are assigned the
lowest priorities of from 15 through 0, respectively, and lines BI D < 16:00 > are assigned the
highest priorities of from 15 through 0, respectively. During powerup, the nodes default to the lowpriority word.
31
LoiN
2423
~riority
·JULOW . . . t. - - - . , . . - - ' - - - -_..._ High
...
OIIIt---_ _ _~_·-;....... High
; . Priority Priority
------~----~v
Priorit¥!
~~~~~---vr~--~--~~
Low-PrioritY Word .
High~Priority
Word
Figpre 25 • VAXBI 78732 Node Identification and Priority Assignments
Arbitration MQdes
The arbitration m.odes, defined by the VAXBI protocol, are dual round robin, fixed-high priority,
and fixed-low priority. The dual round robin mode is the only user authorized mode. The
remaining modes are reserved for use by Digital. The modes are selected by arbitration control (bits
5 and 4) of the VAXBI control and status register and can be changed by a node during system
operation. Any combination of arbitration modes can exist on the VAXBI bus, however; the fixedhigh and fixed-low modes are reserved f<>r use by Digital. Allnodes default to the dual round-robin
mode during the powerup sequence.
Dual Round Robin Mode-During this mode; the node arbitrates on the low-priority word when
the ID of this node is less than or equal to the ID of the previous bus master. When the ID of the
node is greater than the ID of the previous bus master, it arbitrates on the higher priority word. If
this mode is selected by all nodes on the VAXBI bus, all nodes will have equal access to the bus after
a period of time. In multiprocessor configurations, this mode prevents excessive bus latency time
that may occur when a node is denied bus access because several processors are performing
instruction loops.
4-46
Confidential and Proprietary
VAXBI~71J
Faed I..cnv.p6ority Mode-This reserved moclecan be assigned to nod~s that require access to the
bus infrequently.
Faed High-priority Mode-This reserved mode can be assigned to podes where critical access
time to the bus is required.
TransaetionCycles .
The VAXBltransactions are performed using the (:()Olmandlad~,· embedded arbitration, and
data cycles shown in Figure26. The basis aperation is.~troWhy the,B! NO ARB andBI BSY
lines.
I
COMMAND!
ADDRESS
(CIA) CYCLE
IMBEDDED
ARBITRATION
(IA) CYCLE
::
'
",
,
"
"
DATA
CYCLE
,;(",
."
'
",
DATA
CYCLE
X,,
1
Figure 26 • VAXBI 78,(J2 T~#Qn;Cycte Format
"
Command/Address Cyde-This is the first cycle ofilti VAXBI transactions and is identified by a
node when the BI BSY signal is werted following a CYcle where the BI NO ARB s~ was assetted..
During this cycle, the master transmits a 4-bit cC):tntnatid code in lines'BI'I<:3:0:;:::. . Each transaction type is
restricted to one of the formats listed in Table 28.
Table 28 • VAXBI787.32 Command/.AcIdrfts 1'ransaetion Type
'1.iansaction
VAXBI Bus Lin~s
BID<31:165 "
BID
Read-type
Write-type
Invalid
Length code and 30·bit address
Length code and 30-bit address
Length code and 30-bit address
Interprocessor interrupt
Interrupt
Stop
Broadcast
Identification
Decoded master ID
Level',
Reserved
Reserved
Level
Destination ~k
, Destination mask
Destination mask
Destination mask
,':' ReseJ:!VOO
Dt¢ngread-type, write-type, an,dinv,alid.tt:anlj~(;ti.o~,thesele<;tion inf9rmation consists of a
length code and 30·bit address. The sele~iQn information can. al,sp be a16-bit dest4t,ationriwskin
which each bit corresponds to an~ID. This enabl~s£rom ho 16 nodes to be involved in the same
transaction. The destination mask is used for alI multiresponder transactions except for the invalid
transaction. The interprocessor interrupt transaction uses the decoded mask and destination mask
to select a slave. The level field selects the slave during a identification transaction.
Confidential ancl.Pmpr!etarY
4-41
...
Embedded Arbitration Cycle-During the secondcyde of a transaction, the e11COded ID of the
master is transferred on lines BI I < 3:0> and the VAXBI data path is available for arbitration of the
other nodes unless the burst mode is selected.
Data Cycles-One or more data cycles can follow the imbedded arbitration cycle. During these
cycles, data is transferred between the master and slave node through the VAXBI data path. The
number of da~ cycles required normally depends on the length of the transfers and the number of
stall responses issued by the slave. During identification transactions, the number of data cycles
depends only on the number of stall responses. Multiresponder transactions, except for broadcast,
use one reserved transaction. During broadcast transactions, data cycles cannot be stalled.
Therefore, the number of data cycles depends on the length of the transfer. Table 29 lists VAXBI
bus information transferred during the data cycle for each transaction type.
Table 29 • VAXBI 78732 Data Cycle Information Transfer
Transaction
Read-type
Write
Write with cache intent
Write mask with cache intent
Unlock write with cache intent
Invalid
Interprocessorinterrupt
Invalid
Stop
Broadcast
Identification
VAXBI Bus Lines
BID<31:00>
BII<3:0>
read data
write data
write data
write data
write data
reserved
reserved
reserved
reserved
reserved
interrupt vector
read status
reserved
reserved
write mask
write mask
reserved
reserved
reserved
reserved
reserved
vector status
• VAXBI Bus Transactions
This section describes the types of transactions that are supported by the VAXBI bus and defines
their use.
Single and Multiresponder Transactions
Single-responder transactions are directed to one node and multiresponder transactions are
directed to more than one responder. Table 6 lists the commands that can be used with these
transactions.
During single-responder transactions, data is transferred between a master and a slave node. The
master requests that a node be a slave with a 30·bit address. The node receiving the address uses
thisand other information transmitted dilringthe command/address cycle to determine its slave
status.
4-48
Confidential and Proprietary
1
Multiresponder t~ are:in:itiated by the INTR, IPINTR !INVAL, S1Op, and BDCS'!'
commands from ama$ter. During these transactions. the master s:lis.adestination mask instead
of an address. Interrupts are generated by a master.when it issuesa~$n COro.tWlnd-ntessageto one
or more slaves capable of accepting interrupt requests or when it ~sues an IPINTR command to
other processors. The INVAL command is used to notify a node that the cache data in its memory is
invalid. The STOP command is used to diagnose errors. TheBDCST command is reserved by
Digital and is u~ to sen{i ittformation thrOU~ht:he entire system.
.
Interlock Transaetions
The IRCI and UWMCI iqterlock oommandsand the IPIN'!'R~rproceSsOr co~ds sU}1port
interprocessor cOtnffiuclcatiof\S'. These a:Jm~n9sallow P.ro~~to,cOmmtiru.cate by exchanging
messages that ~ ~posited in a shared m~ory. 1Pe. shared~ry .access is syncim>nized
because the -mem&ry access frem one process'ermay be inter~with memory accesses frem
anotherprocesso~ Software~level synduoniza1ionis'achievechhr~trgbthe use of the VAX interlock
and queue instructions, and implemetlted by~e IRClartd UWMpltransact1ons.
During IPINTR transactions, one processor interrupts the operation of another processor. Both
shared memory·.lUl areperfo~ qn ptooe~or~s;\pd~ap~by .~_ IltCl ~ UWMCI
interlock transactions. The interlock f~ature of these ~nsj.rnustPe~plemeJ,lted.Jor
memo!)' andl/O.space ad '.' . ' -.laC! trans~9:ps _~tl~.~.•t>.
~s.JPust.·~f()n~
as SOOll ,as possible by a . . . '. <:1 ~tIcti(>n.to~thel:(.. .......... ..l'Jlode.iSsw;~atllRc:.I
command to. a
lqcatWn, •.~ n~wfu ~i~~-~ii:y~s~.
_~~. tifn~ut'Ym occur
locked
from ~ted ~CI co~dS to.lp<;keJ~~t~n. ReIeitot;h~\?A,: JS.,ste11J·Re!~eM!ltt;tal
for other interlOCkco~d~rati~ns.
Data 'Iiansfer~~
.
. .
.. .
'.
".,,,
.' _. . . . . « . . .
.. .
.., .'.
.
. ..
.'
During the.co~and/~ cyc;lt;: ~f.•~;t~~.~~ 'Y,ri~c:.ty~·tnu:ls~?nsf . ~~. ~ID< 31:30>'
specify the number of bytes to be transferred ana lin~s HI15 < .2~:ut1 > specify'the address.' Thble
30 lists the data length selections.
Table 30 • VAXBI 78732 Data Length Codes
Data Lenatb
BID Lines
Bytes
:n
H
30
H
Reserved
H
L
L
H
LW (longword)
4
QW (quadword)
8
L
L
OW (octaword)
16
The low address of the block of data transferred is a multiple of the size of the block of data in
bytes. During read-type transactions, the address supplied during the command/address cycle may
not contain the low address of the block of data transferred.
4-49
Preliminary
VAXB118732
Address Interttretation-The .intetpretation of the addressdudng read~type and write-type'
transactions depends on the transaction type, address space, data-length field, and low-order
address bits. Figure 27 shows the Iongword and byterefererices in an octaword block.
00
31
01
02
03
D4
I
I
I
I
B3
82
B7
Be
B11
810
815
814
I
I
I
I
En
eo
B5
B4
Be
Be
.913
B12
I
I
I
I
Figure 27 ·VAXBI 78732 Longword and Byte References in an OctawordBlock
Address BO specifies the data length as follows: A <29:02>'OO==longword, A <29:03 > '000=
quadword, A<29:04>; 'OOO=octaword.
Read-type TransactlcnllJ--:'Table .31 lists the interpretation values of the addresses during read-type
transactions. During this transaction, the slave first transfers the addressed longword of data and
the remaining longwords depend on the implementation of the node. The address normally is datalength aJigfl.ed and the remaining longwords are transferred in ascending address order. If the
initially addressed longword is not data-length aligned, the remaining longwords are transmitted in
ascending order until the beginning of the data-length aligned block is reached. A wrap will then
occur and the next longword transferred will be located at the base address' of the block.
Longwords are then transferred in ascending order until the entire block has been transferred.
4-'0
Confidential and Proprietary
Data
Jength'
'libJe 31 • VAXBI 78732 Reit'l-tyPd ':transacdon k1L;;sIntetpretatioo
1Address
Return da.order
Address Address
11!Ceived
spac:e2
transmitted
{,
WS
A29:04'OOXX
A29:04'OlXX
A29:04'lOXX
A29:04'llXX
A29:04'OOA29:04'Ol.A.a9:04'lOA29:04'll-
NWS
NWS
WS
A29:03'OXX
A29:03'lXX
Notused1
A29:0YO-
01andD2
A29:03'l-
02 and 01
A29:02'A.29:02'A29:02'OA29:02'lA29:02'OO
A29::()2'Ol
A29:02'19 .
,A29:0Z,'l1
1)1 (B3, B2,B1, and BO)
01 (B3, B2,B4, and B5)
OW
OW
NWS
NWS
NWS
OW
QW
QW
QW
LW
LW
LW
LW
LW
LW
LW
LW
NWS
WS/L
WS/W
WS/W
WS/B
WS/B
WS{B,
WSfB
ow
A29:02'XX
A29:02'XX
A29:02'OX
A29:02'lX
A29:02'OO
A29:02'01
A29:02'lQ
" A29:0?'1l
Dl,D2, D3, and D4
D2, D3, D4, andDl
D3,D4, Pt,and D2
04, Dl, D2. and D3
PI (XX, XX,Sl,-and BO)
01 (B3, B2,'XX, and xx)
PI (XX, XX, XX, and EO)
Dl lines. When a mask bit is set, the corresponding byte is modified by the information
on the data lines. These lines are not defined for write-type data cycles that do not use the mask.
Table 33 shows the byte assignment for the write mask codes.
lable 33· VAXBI 78732 Write-mask Code Assignm~nts
Asserted
BI I line
3
2
1
o
4-52
Byte
BID line
31:24
23:16
15:08
7:00
Confidential and Proprietary
_.
Preliminary
I
VAXBI 18732
Read Status_TheEl 1< 3:0> Jines traos.£er a read-status code from jhe slave to the master during
the acknowledge data cycle of a read-type or identification transactiqn. The code defines the type
of data returned to the master. Table 34 shows the read status code a~signments.
Table 34· VAXBI 78732 Read Status Code.A~~ts
BlIline
Status
3
2
1
o
H
H
H
H
*
*
H
H
L
L
H
L
H
L
Reserved
R.eaddata
Corrected read data
Read data spbstitute
H
H
L
L
H
L
H
L
Reserved
Read data/do not cache
Corrected rtlid ~tatdo not cache
Rl::Qd data SIlbstitute/do not cache
L
L
L
L
*
*
*
*
*
*
*Reserved
Write-type TransactiOns
The VAXBI bus supports four write-type tra,tl~~oI1s that ¥~ u~~;to tra:ps£er data from a master
node to a slave node. The fo1lowingparagrapllsQesttibe the seq~ used duringthe transactions.
The abbreviations referenced on the write tritmactiontirrtingdiagramsate:
M = master node, S"'; slave node, S5= more than dpe slave, ..\\AN- all arbitrating nodes, AN =all
nodes, APS = all potential; slaves for identU:y'ttansactions' priqr; to' ide~tificati9n arbitration
selection. A (> ) before a response indicates the CNF code tt(l.nSferred ~ing the transaction.
WRITE Command-':The Write transaction tt(l.nSfers data
a truisteho a slave when the master
does not store the data incache merOOry.Figurei2&sh~the transaction timing.o£ a WRITE and
Write with Cache Intent (WCI) command far an ~aword.
;
hom
4·53
vAXBlta732
CYCLE
CIA
3.1
3C
01
IA
02
c,
,
03
..;..----,......__.:...,
DATA
LENGTH
1
I
I
I
I
~
2
2fl
25
24
23
22
21
DECODED
I
I
I
I
I
I
I
I
I
I
I
I
10
lOW
PRIORITY
~
I
I
i
I
I
18.
I
I
I
1
BI 0<31:00>
IE
30 BIT
15
14
ADDR
OArA 1
DATA 2
DATA 4
DATA 3
I
I
I
12
I
"
r
1~
DECODED
.9
e
I
I
I
I
I
I
I
I
10
HIGH,
PRIORITY
:
4
2
1
.~
SOURCE
M
AAN
.'
Nt
M
M
WRITE
COMMAND
10
WRITE
MASK
WRITE
MASK
MASK
WRITE
MASK
SOURCE
M
M
M-
Il!
M
M
GEN
CHI(
II.!
AN
M
M
S
II!
M
S
M
S
>ACK
NOACK
STALL
RETRY
>ACK
NOACK
STAlL
>ACK
NOACK
STAlL
NOACK
S
S
S
S
MASTER
BII<3:O>
iiPii
Nt
AN
81CNF<2:O>
SOURC E
1\1
I
I
M
M,MN
I
M,S
M.S
I
M,S
M,S
I
I
I
I
I
I
I
+---1
I
I
S
>ACK
>ACI(
NOACK
>ACK
NOACK
S
S
STAll
M,S
M.S
•
Figure 28· VAXBI 78732 WRITE and WCI (octaword)
4-54
I
1--"1
Confidential and Proprietary
I
r
I
I
I
I
I
I
I
I
Transaction Timing
Preli~).
.
VAXB178132
During the command/address cycle, the roaster specifies the ~ength of the d~ta on lines
BID <: 31:30 >, the a<:ldress on lines BID < 29:00 > , and the cOllUrufudonlines Btl -< 3:0> . Parity
is generated by the triaster and checked by the nodes. The BI BSV line is asserted until the last
ARB line is deasserted and
acknowledge data c:yck. Duringthe command/address cycle, the Bf
then asserted with thl:! BI BSY line until the end of the cycle" During the embedded arbitration
cycle, all nodes except for the present master can at~itrate for'th~~lls)cQntrol.
The slave transfers a command confirmation code to the blaster duJ;ing cycle D 1. This code
indicates the slave status and errors conditions. Subsequent Cb~ti€ln codes I?tpVide information related to the data transfers.
.
The master sends data to be written during D 1 and sjIcceedingdatacycles. Slaves that are unable to
receive the qata at the specified time can iSsue a stall:response {ora maxitnum of U~ cycles to delay
the data traDskr until it is ready. During the data cycles ofWlUTE command,theinformation on
the BI 1< 3:0 > lines is undefined. Durmg the data, cycleS,' the ~mas~genetates the paritY that is
checked by the slave.
Write with Cache 1nte!nt-I>ur4lg the Write with Cache In~t (WCI) trilflsaction;Shown in Figure
28, the data t:rans£eqed may be written into cache memoq.. 'rlrlscan occur 9ruy if the data
previously written into the same.1ocation in the caclJr is valid. 'l'he¥ave bode mustissue an INVAL
command £Qr subsequent write ~ctions to the ~ame locatio1'iji;that;are not performed with a
WCI VAXBI transaction. The wct transaction is alwaYs perfontied·it'tlle ru,de'is unaf,le todetermine
ifthe data transferred will be written into I;8che.The: response ~o this command by the slave is the
same as a WRITE command, During the: data cycles of WCtcommand, the information on the
BlI < 3:0 > lines is undefined. '
.,
No
Write Maskwitb Cache Intent-The Write Mask With , lines during each data cycle. The
master genetates parity for the entire VAX'SI data path regatdless o(the bytes to be modified. The
WMCI transaction tin:Ung is shown in Figure 29. .
..
.',.
Confidential and l?;roprietary
4-55
VAXB17873:Z
CYCLE
CIA
31
DATA
30
LENGTH
03
01
IA
T--....-'
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i-
1
16
15
14
1
I
1
1
1
1
I
3Ol3rr
ADDR
DATAl
DATA 2
DATA 3
OATA4
I
13
12
I
"'1
11
I
I
I
I
I
I
10
:
:
DECODEO
10
HIGH
PRIORITY
4
2
1
0
SOURCE
I
I
1
M
.'
AAN
MASTER
""BiPO
M
M
UNDEFINED UN6eFINED
FIELD
FIELD
I
M
M
T--i
UNDEFINED UNDEFINED
FIELD
FIELD
1.
1
I
10
SOURC E
M
M
M
M
M
M
GE N
CHK
M
M
AN
M
S
M
AN
S
M
S
M
S
>ACK
NO ACK
STALL
RETRY
S
>ACK
NOACK
STALL
>ACK
NOACK
STALL
>ACK
NOACK
STALL
>ACK
NOACK
>ACK
NOACK
S
S
S
S
S
BICNF<2:0>
SOURC E
,
M
I
I
}-~
M
M.AAN
I
I
M.S
M.S
I
I
M.S
M.S
J
I
I
+---'--4
M.S
I
I
I
I
Figure 29· VAXBI 78732 WMCI and UWMCI (octaword) Transaction Timing
4-56
I
I
I
COMMAND
Confidential and Proprietary
I
I
I
I
D......1:"-:.....................
A U;;.IUUUUU;.1'
I
UnJpck W~ ~ with Cadle Intent-TheJ.Jnlpck Write M;a;sJ} with CllChe Intent (UWMCI)
command ~ used to c~mplete a read-modify-write operation that ~an with an interlock read with
cache intent (IRCI) command. It is used to unlock a shared memory ~truau.t1:.TIieslave should not
clear the lock bit if a Parity error occurs duing this transaction. A nWe must issue this transaction
as soon as possible a£¢r issuing an IReI command. A write ID$sk is ~erred on:Jines BI I < 3:0 >
during each data cycle. The UWMCI tranSaction timing is shbwnmFiP 29.
Read-type Transactions
The VAXBI bus supports three read-type transactions that are Used to transfer data to a master node
from a slave node. The followitlg paragraphs describe the s~uence ~ during"~he transactions.
The abbreviations referenced on the write transaction timing diagnuns' are
.;
M=master node, S=slavenode, Ss=mQre ~one slave, M~;,=:!dlar~~~ nodes, AN =all
nodes, APS = all potential· slaves for identffytransaCrl6nsi. prior· to; identifi~tion arbitration
selection. A (> ) bef~ a response indicates the CNF code~erredduring the transaction.
READ Command-The read transactions transfer data from $lave to master when the data will not
be stored in caChe memory. F~ure 30 shows. the~ransactioo ~ ·0£ a READ command that
transfers an octaword.
4-57
-
VAXBI18712
0/1'.
31
30
;;
fA
<
tXl,J
D
IE
3061T
1~
ADDR
I
I
I
I
OECOOi!!:O
10
24
2
. I
I
DATA 1
OAT,6,2
OATA3
I
I
I
I
I
I
I
.1
I
I
I
I
I
I
I
OATA4
I
1
,1~
r
1~
1
I
11
1(
:
DECODED
10
HIGH
PRIORITY
E
I
1
I
I
I
,!
I
I
I
I
(
SOURCE
~
M
AAN
S
S
S
MASTER
10
STATUS
STATUS
STATUS
COMMAND
SOURCE
M
M
S
GE N
CHK
M
AN
M
AN
>ACK
NOACK
STALL
RETRY
S
SOURC E
M
I
M
I
M,AAN
T--I
STATUS'
I
I
I
I
I
I
I
I
BICNF<2:0>
,
I
S
I
S
S
S
S
S
M
M
S
M
M
>ACK
NOACK
STALL
>ACK
NOACK
STALL
>ACK
NOACK
STALL
>ACK
NOACK
>ACK
NOACK
S
S
S
M
M
M.S
M,S
1
I
M.S
M.S
1
I
-+----4
s
M.S
M.S
I
I
I
I
J
I
I
I
I
Figure 30· VAKBl 78732 READ, RCI, and IRCI (octaword) Transaction Timing
. Confidential and Proprietary
I
PreIqDwy...
VAXBI78132
During the command/address cycle, the master specifies the length of the data word on lines
BI D < 31:30> , the address on lines BI D < 29:00 > ,and the commaild on lines BI I < 3:0> . Parity
is generated by tbe master and checked by the nodes.The~ line is asserted until the last
acknowledge data cycle. During the command/address cycletbe BI ~o ARB line is deasserted and
then asserted with the BI BSY line until the end of the ~le. DuriJIg the embedded arbitration
cycle, all nodes except for the present master can arbi$.~ for the- bus control for the next
transaction.
The slave transfers a command CQrtfirmatipn code to th~:master during cycle Dl. This code
indicates the status of the slave aqd any errors conditions tha~~:may exist. Subsequent confirmation
codes provide information related to tbe data transfers. A oonfirmation code providing information related to the last two data cycles is tran$£erred from the master to the slave.
The slave sends data to be written during 01 and succeediqg.datacycles. Slaves that are unable to
send data at the specified time can issue a stall response for~ maximum of 127 cycles to delay the
data transfer until it is ready. During all datacycl~~fRead¢Qmmand, the~ity generated by the
slave is checked by the master and the read status frOm theslllve on lines 13ft < .,H1 > provides the
master with status information.
Read with Cache Intent-The Read with Cache. Intent (ReI) transaction, shown in Figure 30, is
used to read data that is intended to be stored in cache. If a "do not cache" read status is transferred
on lines BI I<3:0> from t~e slaye,the.m$ster must notC~to~ the data in cache memory. The
response from the slave for this comraand is the same as forthe .Read command. This command is
used for cached multiprocessor systems to worm the slave;that the data read will be stored in the
cache memory of the master.
.
Interlock Read with Cache Intent- The Interlock Read Data with Cache Intent (IRCI) transaction
supports read-modify-write operations and is used with the UWMCI command. The transaction
timing shown in Figure 30 is the same as for the read ~ction. When the memory space of a .
node has been successfully accessed by this command, the l"IO<1e must set a lock bit that will cause
susequent IRCI transactions directed to the s.'ame locked add~S;llJ:be repeated. The lock bit must
remain set until a DWMCI trapsaction di~ tOtne s~me ~ock¢daddress range is successful. The
minimum size of an!l
16
15
14
13
12
30 BI.T
ADOR
. RESERVED
FIELD
11
10
~
DECODED
10
HIGH
PRIORITY
I
6
5
4
3
2
1
C
M
A~
COMMAND
MASTER
10
SOURCE
M
M
GEN
CHK
M
AN
M
AN
SOURCE
BII<3:0>
BfPO
RESERVED
FIELD
RESERVED
FIELD
>ACK
NOACK
BI CNF<2:0>
Ss
SOURCE
)
61SSY
I
61 NO ARB
J
I
M
I
M
I
I
M.AAN
'\
I
I
r
I
I
I
Figure 31- VAXBI 78732 INVAL Transaction Timing
4-'60
Confidential and Proprietary
I
tQe, commanqJad~ss cycle, the. master specifies the~pgth of the data word on lines
BI1> <3l:30> "th~~sson linesBI D<29:00>, and the.Cl)~!Ilatld9nllnes BII.<3:0>. The
During
data lengthcod~ specWes the number of consecutive addresses tpPe invalidated. The low-order
address bits ~~d.Parity is generated by the master and~ecked by the nodes .. Thhle 35
shows the address interpretation during thistranw,:tion,...
,J
Data length
'J&hle 35 • VAXBI 78732 Invalid 1hmsactiQn .t\d~1I In~tion
A~ '".
"', . ." ~~!i";'"
' . . , .....
Octaworo
Quadword
Longworo
transmitted
received
A28:04'OOOO
A28:03'OOO
A28:02'OO
A29:(},3' ---
A29:04' ----
A29:02'--
The nodes, except for the present mastel;, can arbitrate for the bus control for the next transaction
during the IA cycle. The acknowledge and no acknowledge are the only valid responses from the
slaves to this command.
A node can delay the start of the next transaction to allow time to invalidate its cache by asserting
the BI BSY signal through cycle Dl and until the data is invalidated .
• Interrupt Transactions
The VAXBI bus supports device interrupts consisting of INTR and INVAL transactions and
interprocessor interrupt IPINTR transactions. During device interrupts, the interrupting device
supplies an interrupt vector in response to the identify transaction that is unique to the device.
During IPINTR transactions, the interrupt vector and level are the same for all interrupts and are
stored in the receiving node.
Device Interrupts
Nodes that are capable of generating interrupt requests contain a vector that is used by the VAX
processors to select one or more 512-byte locations in memory. These locations contain address
pointers used to select interrupt service routines.
During the command/address cycles of the interrupt transaction, each BI D< 19:16> line
corresponds to an interrupt level. Line 19 is assigned the highest-priority interrupt (level 7) and line
16 the lowest priority interrupt (level 4). These levels correspond to the VAX processor interrupt
priority levels (IPLl7 through IPL14).
An interrupt node issues an identify transaction when it is ready to service an interrupt request.
The interrupt level field from the node must contain only one level of the interrupt it is ready to
service. This level must be the highest priority for which the bus master has received an interrupt
request and has not responded with a identify transaction.
Nodes that have an interrupt pending at the Ident level respond by arbitrating for the bus during
the identify arbitration cycle of the identify transaction. The winner of the arbitration transfers its
interrupt vector during the next cycle. The VAXBI interrupt vector is different from the VAX
system interrupt vector described in the VAX·ll Architecture Reference Manual.
4-61
...
Preliminary
Interrupt v
15
14
13
12
11
to
9
8
7
iNTR
DEST
MASK
DEcOOED
10
HIGH
PRIORITY
M
AAN
COMMAND
MASTER
6
5
4
3
2
1
SOURCE
RESERVED
FIELD
10
BII<3:0>
iii'PO
SOURCE
M
M
GEN
M
AN
M
RESERVED
AN
FIELD
CHK
>ACK
NOACK
BICNF<2:0>
SOURCE
B'i'iSY
S6
~
I
BINOARB
{
M
I
M
~
M,AAN
I
iI
~
Figure 32· VAXBI 78732 INTR Transaction Timing
4-63
-...
During the command/address cycle, the master transfers the interrupt request levd on lines
BI D < 19:16> , the interrupt destination mask on lines BI D < 15:00 > , and the command on lines
BI 1< 3:0 > . Lines BI D < 31:20 > are reserved. Parity is generated by the master and checked by
the nodes.
The nodes, except for the present master, can arbitrate for the bus control for the next transaction
during the IA cycle. During the Dl cycle, the slaves transfer an acknowledge or no acknowledge
response to the master.
The node that received the interrupt t1'!¥lsfersan IDE NT command to the node that initiated the
request to solidta vectot: Only one of the many nodes that may receive the IDENT command"will
transfer the vector.
.
During INTR commands, interrupts may occur at more than one interrupt priority level. Nodes
respond to the commands if their decoded ID is the 'same as the destination code transferred on the
BI D< 15:00> lines during the command/address cycle. Nodes that respond to INTR commands
must store an interrupt pending bit for each of the four interrupt Ievds to permit them to solicit
vectors with IDENT commands. The interrupt level field of a command/address cycle may contain
zeros, however, the slave must respond with an ACK confirmation.
Identify Commands- The identify command (IDENT) is used by nodes to solidt interrupt vectors
in response to an INTR command. Figure 33 shows the transaction timing of a IDENT command.
Confidential and Proprietary
Preliminary
vAXB1787'2'
STALL
veeToA
IOENT
OMIO
IA
CIA
CYClE
AfIB
AqK ....
.VECtOa
31
. OEcooeo
_.... _.,..,----,
I
I
I
1
I
I
f
I
I
0'5
10
. tb\iY"
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IOENT
lEVel
1
I
B1D<31:00>
I
I
I
I
I
I
I
I
I
I
I
I
;\
I
I
I
I
I
I
I
SOURCE
SOURCE
BIPO
M
M.
CHi<
AN
f
I
I
I
:..---i----i
.
I
I
I
l
M
GEN
I
-~"""""""'"'"!':"1
GQMMANO
BikiQ;
I
l
. .
B1CNF<2:0>
SOURCE
BlIfSY
iii"NO'ARii
S
lI
~
M
I
I
l
M '.
M,AAN
M.APS
.j,
M.APS
t
I
I
¥.~
M.APS
·1·I
$'···t
""7:
S
I
I
i.
¥
Figure 33· VAXBI 78732'IDENT Transaction Timing
Confidential andPropri~
M
M
1 :;
t
...
During the command/address cycle, the master transfers the command on lines BI 1< 3:0 > and
the identification level' onlined3ID< 19:16>. The IDENT level field can contain only one
asserted bit. Lines BI D<31:20> andBI D<15:00> are reseved. Parity is generated by the
master and checked by the nodes. Line BI BSY is asserted until the vector is transferred.
During the IA cycle, all nodes except for the present master can arbitrate for bus control during the
next transaction. During this cycle, nodes cannot arbitratefor anlntr thmsaction. The decoded ID
is transferred from the master on lines BI D < 31:16> during the Dl cycle and the parity is
generated by the master and checked by the slaves. Nodes that detect invalid parity must transfer a
no acknowledge response and must not participate in the identify transaction.
Nodes participate in the Ident ARB cycle if all of the following conditions exist:
,; The interrupt level pending corresponds to the level sent during the command/address cycle.
• A command parity error has not been detected.
• A master decoded ID parity error has not been detected.
• The decoded ID from the master is the same as the INTR destination mask.
m
on one of the
The slaves arbitrate by asserting a bit that corresJX>n,ds to their node
BI D<31:16 > lines. Lines BI D < 15:00>, BI I <3:0> and BI PO are reserved during this cycle.
The slave with the highest sublevel priority wins the cycle and transfers an acknowledge, no
acknowledge, retry, or stall response in the next cycle. Figure 33 indicates a stall response in this
cycle. During the ACK Vector cycle the slave transfers the vector on lines BI D < 13:02> and status
on lines BI I < 3:0 > . If the transfer is unsuccessful because of a parity error, the master transfers a
no acknowledge response two cycles after the slave attempts to transfer the information. The
master issues anIDENTcommand at the same level again to obtain the vector. Upon receiving the
acknowledge response indicating no parity error, the master clears the internipt pending bit at the
identify level. When the vector is transferred, lines BI D<31:14> ahd BI D<01:00> must be
zero. The vector parity is generated by the slave and checked by the master.
Two cycles after the vector has been transferred, the master issues an acknowledge confirmation if a
parity error was not detected. The responding sIave_ assumes that the vector is correct when the
final acknowledge is received from the master. If a no acknowledge confirmation is received, the
slave issues theINTR cOmmand again prepares to transfer the vector when the IDENT command is
received.
Nodes .that participate but lose the identify arbitration must again initiate the interrupt
transaction at the same level to prevent the 10ssof previously posted identify levels. Nodes transfer
a no acknowledge responce if the interrupt condition is removed or if the interrupt was serviced by
another node.
4-66
Confidential and Proprietary
VAXBI7l7s2
VAnI Imerrupt Vectors
,
'\
TWo types of iMerrupt:' vectors are issued by VAXBI adapters a.n~ each adapter, is allocated ' four
interrupt vectors. The vector formats are shown in Figure 34.
13
0lMI8 07 0605
0'5
13 ,
I
·02 0100
FIslNoDElDloiol
.". OIl, 011
AOAPNO
.
I
.,'
",.~.c».P.o,
TARGETVEC:'1l(,1
Figure 34· VAXB178732 VAXBllntetmpt Vecmr Formats
1'heoode IJj vegar isloqtted betW~!1~~]bca~iotlS lOO.aQ~l~F(h~edmal). The
vector field assignments aredeS~m Tab~e 36.
,'., ,.
rie>deID
.
'&ble 36· VAXBI 78732 VAXBI Node ID V~ Descriptions
Bits
Description
13:09
MBZ (must be zero)
08
Set toone
07 :06
S (Interrupt vector number)-One of four interrupt vector values assigned to a node.
05:02
NODE
01:00
MBZ (must be zero)
ID (Node identification)-A interrupting node value of from 0 through 15.
4.67
__ J_..
1'~_"'
Y!l
__
'l&_:tI'''_.__
_iDliI.!Ii:i
_____
ili _ _ - = ' I I }
~
;JI!1
_"'1«0 _ _ _ _ _ _ _ _ _ __
The target vector specifies one of up to 128 interrupt service routines. Each,lIPapter t:b,!l~.iss.uestlJis
vector ~s 3.u,tl.jque adapter n\il1llbet; md the mngeof ~ull1bers dete~ tqe l3t1gC! 9£ possible
vectors. The target vector field assignments are described in Table 37.
Table 37 • VAXBI 78732 VAXBI Target Vector Descriptions
Bits
Description
13:09
ADAP NO (Adapter number)-A unique adapter number assigned by the opemting
system software md used in constructing the interrupt vectot.
08:02
TARGET VEe (Target vector)-Speci£ies the rmge of possible vectors in a system. All
zeros indicate a null interrupt.
01:00
MBZ (must be zero)
Interprocessor Interrupt-The interprocessor interrupt (IPINTR) is used by processors to interrupt
the operation of other processors. This commmd is similar to the INTRcommmd except that the
levelmd vector are not transferred during the trmsaction but are stored in the node that receives
the commmd. Figure 35 shows the tmnsaction timingof a IPINTR command.
.
Confidential mdProprietary
r,
,,
CYCLE
31
CIA
IA
r---~--~--------~--------,
30
BID<31!OO>
4
3
2
1
0
SOURCE
M
AAN
COMMAND
RESERVED
FIELD
BII<3:0>
BiPii
SOURCE
M
M
GEN
CHK
M
AN
M
AN
RESERVED
FIELD
>ACK
NOACK
BI CNF<2:0>
SOURCE
Ss
M
'l
I
BIBSY
BINO AAB
{
M
f
I
I
"
M,AAN
I
I
"
Figure 35· VAXBI 78732lPINTR Transaction Timing
Confidential and Proprietary
4-69
Prelinunary
.
During the command/address cycle, the master transfers its decOded ID on lines BI D < 31:16 >,
the command on lines HI 1<3:6>; and the interprocessor destination mask on lines
BI D < 15 :00 > . Parity is genentted by the master and check~by the nodes.
All nodes except for the present master can arbitrate for control of the bus for the next transaction
during the IA cycle.
The nodes that receive the interrupt compare the decod¢d ID from the master with the
corresponding bit position in the IPINTR mask register to determine if they have been selected.
During the D 1 cycle, the slaves transfer an acknowledge or no,acknowledge response to the master;
the information on lines BI D < 31:00> ,BI 1< 3:0 >, and Bfi50 is reserved; and parity is not
generated.
When an interprocessor interrupt request is received by a VAX processor node, a level 14
(hexadecimal) interrupt is generated with an interrupt vector system control block offset value of
80 (hexadecimal) The processor that receives the interrupt examines the IPINTR souce register to
identify the processor that initiated the request. A bit is set in this register indicates that an
interprocessor interrupt has been received from a processor with the corresponding node ID. These
bit should be cleared after being read.
STOP Command-The STOP command selectively forces a node to the stopped state preventing
them from initiating a VAXBI transaction. It causes the node to retain the available error
information. Nodes, howeveJ; can respond to VAXBI transactions. This allows the node to be
accessed and the error information examined during diagnostic tests. After a STOP command is
received, a node can be initialized· by the powerclown/powerup sequence or restarted by the
software from its present state. The lock bit of the node must remain after the STOP command is
received. Figure 36 shows the transaction timing of a STOP command.
4·70
Confidential and Proprietary
VAXBI.ilil2:
CYCI.E
CIA
IA
01
GEN
CHK
M
AN
M
AN
RESERVED
FIELD
BII<:3;0>
BrPO
>ACK
NOACK
81 CNF<:2:0>
Sa
SOURCE
l
BIBSY
BI NOARS
{
M
I
I
1
M
M,AAN
"{
Figure 36· VAXBI 78732 SWP Transaction Timing
Conftdentw.aod Proprietary
4-71
VAXBI7873i
The S'IDP transaction sequence is similar to the interrupt (INtl~J sequence except that the
interrupt level information is not required.
Nodes sdected by the S'IDP command must
• Stop issuing tran~actions as soon as possible.
• Remove posted interrupts by clearing the Sent ~nd Force bits in the user's interface and interrupt
.
control registers.
• Set the hard error interrupt enable bit in the VAXBI control and status register.
The Stop command should be assigned a low level of implementation to assure that the node
reaches the stopped state as soon as possible.
During the command/address cyele, the master transfers the interrupt destination mask on lines
BID < 15:00>, and the cOnlmandonlines BII<3:0>. The information on lines BID<31:16> is
reserved. Parity is generated by the master and checked by the nodes.
The nodes, except for the present master, can arbitrate for the bus control for the next transaction
during the IA cycle. During the D1 cycle, the slaves transfer an acknowledge or no acknowledge
response to the master. A node must perform one of the following while proceeding to the stopped
state.
• Issue a retry response when it receives subsequent single-responder commands.
• Issue a no acknowledge respons~ when it receives subsequent single-responder commands.
• Extend the S'IDP transaction by keeping tht; BI BSY line asserted .
. BTIe Transaction Status Information
Significant events within the BUC or VAXBI bus are reported to the master-port and slave-port
interface through event code lines BCI EV < 4:0 >. These lines provide 32 event codes that are
grouped into summary event codes that provide status at the end of a transaction, status event
codes that provide status during a transaction and special codes that indicate self-test status and
bus timeout information. Table 38 lists the event codes class and type.
4-72
Confidential and Proprietary
-
VAXBl18732
Table 38· VAXBI 78732 BCI Event Oode As~ts
I
Suauraary
No event
NEV
MCP
AKRSD
RCR
IRW
NICI
M:in£o
S;in£o
M:info
S:info
M:error/~o
NICIPS
I:error/info
AKRE
I:in£o
S:error
S:error
S:error
S:error
I:in£o
I:in£o
I:in£o
I:info
SlO
BPS
Master-port transaction romplete
kknowledge~V¢,£(,lrslave ~<;ldatIJ
Retry con£irmatjon~~~v~£~ ~~~por~ COQUllanq
Internal n.:3istef written; i.'.
. ; ."
Noacl.
.,........
, ..... ..•
,'"' ..." ...•.' '.'
.'
AckrioWltdge cOnfiimationtece.tVedfofefr6r\;ecfur
Stall timeout on slave transaction
Bad parity received during slave transaction
Illegal co¢trIIl.8tion received for slave data
Bus busy error'
.
Acknowledge confinnation receiVed for no~errorvector-level4
Acknowl~ confii'~a11on recei*d {or nonerro.rveptOr.......:level 5
AcknowledgeconfifMation recei.Jeci fornonerror veCtOr-level 6
.Acknowledge Confirmation received for nODerror vectQr,..,.,-levd 7
M:error
Read data subStitute otreserved status
received"
M:error
Illegal confirmation l'eCfived for iw.ster-portcommand
M:error/info No acknowledge ron£l11nadon received fOFmaster-port.oommand
M:error . . :rnegatcOnfilmation'~ve&bYttia$ter:pod: data cycle
M:error
Retry timeout
M:error
Bad parity received during master-port transaction
Masteft~t efJ!drcheck
M:error
ICRSD
BBE
AKRNE4
AKRNE5
AKRNE6
AKRNE7
RDSR
ICRMC
NCRMC
ICRMD
RTO
BPM
MTCE
rode
Status
M:in£o
I:in£o
I:in£o
I:in£o
I:info
I:info
M/S:error
ARCR
IAL
EVS4
EVS5
EVS6
EVS7
BPR
Advanced retry confirmation received
Error identification arbitration lost
External vector selected-level 4 ;
External vector selected-level 5 .
External vector sqe~ed-level6'
External vtK:tQr sdeete4-1evel 7
Bad parity received
Special Case
B'TO
STP
M:error
info
Bus timeout
. Self~test )?assed
*M=master, S=sIave, I=interrupt, info=information
Confidential and Proprietary
u ±rmwwITW
_~_I.!Ili'_'_'
__________
~
~_
4-73
. ______. ____,_________" '" "' __
I:
Preliminary. )
SUllltllItty Event CodeQpC~tiQll-"'iO?,~. sumwary EVent (EV)cooe indicates the successfUl
completion of a transaction -or an error condition resulting from a transaction with a node. The
master-port interface receives one master summary EVcodeJoreach transaction unlesstne
transaction is aborted. The slave-port interface receives this code for transactions in which an error
is detected and for successful read-type and identification transactions, and when information is
written into the VAXBI registers from the VAXBI bus.
The summary EV code lines are shared·by the master and slave ports. The information is timemultiplexed with a transaction cycle dedicated to the master codes and a transaction cycle .
dedicated to the slave codes to assure that there is no contention between ports for the information.
Figure 37 shows the summary event code timing for a successful write-type and broadcast
transaction of a longword. Figure 38 shows the event code HIDing for a successful read-type
transaction of a longword. When a bus error causes the transaction to abort, the event code may
occur before the times indicated unless the transaction is intranode.
CYCLE
1
2
3
CIA
IA
D1
ACt<
Slave
BICNFCOOE
SOURCE
ACK
SUM EV
Slave
SOURCE
BCI RAK
ACK
Slave
Slave
. EVCOOES
-
'.
\..
6
5
4
SUMEV
Master
"
Figure 37· VAXBI 78732 Summary Event-WRITE and BDCST Longword Transaction Timing
CYCLE
BI CNF CODE
SOURCE
1
2
3
CIA
IA
01
ACK
Slave
4
5
ACK
Master
Master
EV CODES
SOURCE
BCIRAK
ACK
SUM EV
Master
- "-
6
SUM EV
Slave
1/
Figure 38· VAXBI 78732 Summary Event-READ Transaction Timing
4-74
Confidential and. !?roprietary
-
Figwe ~9shows the summary event code timing for ~ succe~sful S~P, INTR, IPIN.TR, aooINVAL
~n from a $.ast¢r-pott. No ,event code lS transferredl by the slave port for these
trtItlSactions.Durlrtgilie STOp, I~1WTR, and INVAL transactioosl the·atent code is tranSferred
during cycle 6. A no acknowledge or illegal confirmation received EV code is transferred during
cycle 6 by unsuccessful IPINTR and INTR transactions generated by the BIlC.
BICNfCODE
souRCE
EVCODES
SOURCe
BCI RAK
Status Event Code Operation-Status event codes provide status information during a tranSaction. The bad parity received event codes (BPM and BPS) are transferred the cycle after a data cycle
parity error has been detected by a slave or master node. This allows a write-type transaction to be
terminated soon after the error has been detected. These event codes are also transferred at the end
of the designated cycle.
The INTR command results in two types of slave status codes-The external vector selected (EVS4
through EVS7) codes and the identification lost (IAL) code. TheEVS codes are transferred during
cycle 4 and the IAL code during cycle 5.
Spedal Event Code Operation-The bus timeout (BID) and self,test passed (STP) codes are special
event codes that are not related to a transaction. The BID code.can be transferred during any
transaction cycle except the data cycles of a master transaction from this node. Other event codes
are transferred before the BID code. This code is then transferred continuously until the request(s)
are removed or the transaction begins. The STP code is transferred after the BIlC has completed the
self-test operation.
-
VAXBI'i8732·,j
Event COde WinclOiW$~ The :interval of time that the, swnmatyor status event cades can l?e
transferred is from cycle 4 of the transaction until cycle 3 of thefo~g transaction. The node is
required to relate the transaction and associated event codes, Figure 40 shows the transaction event
code windows.
CYCLE
1
CIA 1
2
IA
3
4
5
01
CIA 2
IA
6
01
789
02
C/A3
IA
10
01
BI NOARS
BiBSY
BCICLE
EV codes for-+f----EV COdes 1or.....-~
transaction No. 1
transaction No. 2
Figure 40· VAXB{78732 Transaction Event Code Windows Timing
Event Codes and Bus Error Register
Most event codes that are transferred are dependent on the status of the bus error register (BER)
bits. Figure 41 shows the relationship of the codes to the BER. The event codes are defined in
TableJ9.
4-76
Confidentialamd Proprietary
Event
Codes
\
Preliminary
VAXBI187J2
\
I
Bus Error RegIster 811S I
N
M
A
M
T
C
E
j
C
M
I
E
E
P
T
E
S
T
I
V
E
0
F
C
S
E
E::
P
P
A
T
R
01
S'
8TO
NICI
NICIPS
e
S
T
0
0
T
0
"
J
J
'
,-,
N
e
X
'
J,
J.
,..J,.
STO
I
BPS
..t
:
"
J
.J
ICRSO
BBE
'
"
I'
ROSR
,J
,r,
J
ICAMC
NORM<:
I
0
E
,.
'J
-J
,
BPA
-'
I
-J
'
J
ICRMD
J
RTO
J
BPM
-:
..JI
MTCE
"
"
",
,
KEY
Direct correlation between the output of the EV cilde and the settingol1l1e BUs Error ReQlsler bit
Same as
..J lor master pOltinterfacetransactioritBilClIeneraffdt~ons will n~Yfir C;aU$e IheOUtpul of
the MTCE
~1)Qit1O",
iSJletected,
will,bl!I
,- ,: ,f;,V
,-' cOde
' - ' -if'/:the,error
' ,;
:.;._:;_:.1 ,
:,
';'" The
'" WeE
,'-. " " I:llt.~,
i'"
"".,''.'
",'
&et,
This EV code represent. one error GO!1dl1ion, but, not, the only COAJ:I• • 111M will result ,1111/1e l!8fIing of this
~~
"
'
i
'
"
Same as J'or illegal ONFrespon~; however. this error bit will not be set if !here$pOll$ewas NO AOK
This BER bit represents one errorcondilion. but not the onlycondilion. that wHiresU1! Inthe outputtlf this EV
code,
Figure 41· VAKBl 78712 Event Code and Bus Error RegisterC011r!Idtion
Confidential and Proprietary
4-77
....
VAXBI"1S732
Table 39· VA,XBI Eveot Code Descriptions
Event
Description
NEVe
No event reported (default deasserted state)
MCP
Indicates that the last master-port transaction on the VAXBI bus has been
oompleted successfully. During nonpipeline requests, the MPC code is transferred
during the cycle in which the Ble RAK signal is asserted. If a master perforlDS
pipeline requests, this code may appear during the CIA cycle or embedded ARB
cycle. The master must associate this code with the related transaction. If a stop
transaction selects the slave-port interface of the master, no summary event code
will be sent.
AKRSD
Sent from a slave to indicate that the last read-type transaction was successfully
. completed.
BID
Indicates that a node was unable to start a transaction within 4096 cycles after a
request from the BIIC or a master-port interface had been posted. Sets the BTO bit
in the bus error register. After the bus timeout, the BTO event code is transferred
until all requests are completed or a transaction occurs.
STP
Indicates that the BITC self-test has been successfully completed.
RCR
Indicates that the confirmation received from the slave d.uring the CIA cycle from a
slave or master has occurred previously (retry).
IRW
Indicates the completion of a VAXBI write-type transaction that was directed to the
BIlC control and status register space of this node.
ARCR
Used by the master-port interface to support pipeline requests. This code is
transferred by the BIlC during the the cycle that follows the receipt of the retry
confirmation. Because this event code is transferred one or two cycles before the
retry confirmation received event code, it is useful in support the master-port
design of pipeline requests.
NICI
Transferred if the confirmation received for an Intr transaction is a no acknowledge
code, reserved code, or an illegal response code.
NICIRS
Transferred for IPINTR or STOP c:;ommands that are initiated by settingtbe
IPINTR/STOP bit in the BCI control and status register.
AKRE
Transferred after the slave receives an acknowledge confirmation from the identifying master for the transmitted error vector information from the slave.
IAL
TransfeJ:red by the Bnc two cycles after the identification arbitration was lost by
the slave.
.
.
EVS4-EVS7
Used to solicit an external vector from the user's interface when the BIlC
participates in the identification arbitration, when the EV bit is set in the interrupt
control register of the user's interface, and when no error interrupt is pending at
this node at a level selected by the IDENT command.
sm
Transferred if the user's interface stalls a data cycle for more than 127 consecutive
cycles. A node that is not a slave will receive this code if it extends a VAXBI
transaction for more than 127 cycles.
4-78
C;onfidential and Proppetary
Event
BPS
'fraIlsf¢rred if a slave detects a parity error during. write-type acknowledge or stall
cycle or during a broadcast acknowledge data cycld. This coitditionsets the S),E bit
in the bus error regis~
BPR
Transferred by a mastet'or slave during the cycle after the Bne dettx:ts a parity error
during the following data cycle types:
..
,
-Rea.d-tYpe acknowledge,(fur the master)
-Vector acknowledge (for the master)
-Write-type acknowledge or stall (for the slave)
-Broadcast.acknowledge, (£Or the slave)
ICRMD
Transferred by the Bne during l-ead~type)\Vrite"type;
broadcast transactions if
the slave returns an illegal confirmation codeaftetthe command confirmationhlis
been received.
ana
Transferred by the master for each retry l'eSPQnsc:after 4095 retries from the sl~e
when the RIDEVEN bit is set in the BCI co~l.~ status register.
BPM
Transferred when th~ master detects a parity error on theVAXBI bus during a read·
type or vector acknowl~e data cycle.
.
MTCE
Transferred for master-port transactions when the data receivedobthe
BI D< 31;0>, BII <3:0> and~ lines is not the same asthe datatrarismitted
from this node. This occurs during a. cycle in which the master should be the only
node to transfer information on these lines except when encode ID of the master is
transferred during anel11bedded arbitration cycle. The BnCalsosets the MTCE bit
in the bus error register.
. BllC Operation
The following describes the operation of the BIIC during
transad:ions.
powerup sequcfl.Ceand during VAXBI
Powerup Sequence'
During the powerup sequence, the BIlC disables the VAXBI driver circuits, loads the contiguration
information from the user~sinterface into the BijC registers, and per£orJU~a $elf~test operation.
The BIlCasynchronously a~rts the BqDC ill siggalwhenBtPC l,Q is ~serted< Infort:qation
from the BCI D < 31:00> lines is loaded into the device ~gis~ the node 11) iniQrJPation from the
BCI I <:;:0 > lines is kladed into the V~I,;control and: s~tus regi$ter, and the stateo! the Bel PO
line is loaded into the user parity enable (UPEM;lbit of tlte bus e®rregister. The state of the BCI PO
line determines if the BIlC or user's interface will ge~te parityfor the data transferred from the
BIle.
Confidential and .Propriemry
4-19
VAXBI78732·
Self-test Operation
The BCI DeW line must be asserted for a minimum of 72 cycles (14.4 microseconds) to allow the
BIIC to irlltialize the registers associated with self-teSt. When the BI DC to line is deasserted, the
BIICdeasserts the BCI DC LO line and starts the self-test. The BI NO ARB line is asserted during
the self-test operation to prevent VAXBI bus activity. After the self-test has been successfully
completed, the BIlC transfers the EV code (STP) for one cycle during the cycle after the self-test
completes. BI NO ARB is not asserted during the node reset sequence. The user's interface can
monitor this code or can read the VAXBI control and status.tegisterto determine the results of the
self-test. Table 40 lists the status of of the BIlC and user's interface signals during the self-test
operation.
Table 40 • VAXBI 78732 Self·test Signal Status
BIlC asserted
BUC deasse:rted
lines
lines
User asserted
lines"
BCID<31:00>
BCIMDE
BCIRQ<1:0>
BCII<3:0>
BCISDE
BCIINT<7:4>
BClPO
BCINXT
BCIRS<1:0>
BINOARB**
BCICLE
BClMAB
BCISEL
BCISC<2:0>
BCIEV<4:0>
BID<31:00>
*These lines are optionally asserted. During the self-test, the diagnostic mode code should not
appear on lines BCI RQ < 1:0> to prevent the termination of the self-test before completion.
**The BIlC asserts the BI NO ARB signal during powerup self-test but not during NODE reset selftest.
Retry State
The BIle enters the retry state in response to a legal retry response code from a slave during readtype, write-type, and identification transactions. The BIlC transfers the RCR event code and stores
the command/address information of the trahsaction and the first data longword in its buffers
during write-type and broadcast transactions. When the user's interface deasserts and then
reasserts the request, the BIlC reinitiates the transaction. This provides the node with a variable
delay before the transaction is initiated again. Nodes can initiate a retry transaction by disabling
the VAXBI transaction request with the RCR event code.
After the BIlC receives 4096 consecutive retry confirmation responses, it issues the RTO event
code. The user's interface can then ~ontinue to retry the transaction and the BIlC will continue to
transfer the RTO code each time it receives a RCR response for the recent transaction. The user's
interface must assert the BCI MAB line to terminate the transaction.
4-80
Confidential and Proprietary
Request Codes
i
The ,BnCmotUtors 'the state of the ~uest lines to determine if a tra.osition hasoCCW':red. It
compares the received state of the line from the previous cycle with fhe received state of the current
cycle. The tran.sitioDiof the request lines from the deasserted state· (po request) to the asserted state
(a ~uest other than diagnostic mode) is interpreted as a request. The· reql1eStcode .on the
BCI RQ < 1:0> .linescan Qc removed during any CYcle after the assertion of the BqjL\Ksig~ by
the BIIC. A new request will not be recognized by the BllC until the request lines have heen
deasserted for at least one cycle. Therefore a new ~uest cannot be presenteduntill;he second cycle
after Ii requeSt has been removed.
When the BllC receives' a VAXBI reqQest, it initiates theh~sarbi,Wlt:jol1forthenew transaction as
soon asposible. If the bus master simultaneously ipitiates a nev.r reque~t, the BIle wUl arbitrate for
the new request in the neXt available cycle after thl!lastcyd~Of,~ presel1t~n.
Api~ne reqJ.lest is a~uest i>ostedprlor to the dassertionpf ~BCIMk' s~!p~the p~nt
master-port transaction. Figll11! 42 shows. the sig~timing £Cl.r,thepi~e ~~I\,tsthat~ow the
master-port interface to transfer data at a ,tlm;rogpputl:l1teof 11.4.MhYtes.pc:r. second.
CYCLE
1
2
3
ARB
CIA
fA
4
'5
Bel RAK
BC1RQ 0
I
Earliest cycle in which a new
reQ1est
'l"~y be ~I~rted
Earliest cycle in whlcb.a··
request may be deasserted
'
I
.,'
I
Figure 42 .. VAXBI787J2 Request Signal Timing
VAXBl1'ransaction Request,....'The master-po,rtinterfilCe use~theVAX~U tral1Saction requ~s~ ccx:le
to request transactions on the VAnI bus. The' transactionscan~ dUected to \Ithl!r nodes Oil the
bus or to the slave node on the same VAXBI interface. Only lonii~l:ds can be transferred ~o the
slave port.
All VAXBI commands can be initiated by the user's interface except for the interrupt command.
Interrupts are initiated by asserting a BCI INT<7:4> line or by setting a force-bit in the user's
interface interrupt control register in the BIIC. The interprocessor interrupts can also be initiated
by setting the IPINTR bit in the BCI control and status register.
Loopback Requests-The master-port interface uses the loopback request code to initiate
longword intranode read-type and write-type transactions to node spaces that do not require the
use of the the VAXBI data lines. Loopback transactions permit fast access to the BIlC and slaveport registers regardless of the activity on the VAXBI bus and during some bus failures. A node can
access its node space registers without reference to the node ID. During loopback transactions, the
BIle disables the VAXBI drivers except for the BI NO ARB and BrBSY lines, and the transaction
data is looped back to the VAXBI bus receive logic.
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VAXBl78712
Loopback transactions and VAXBI bus transactions can occur concurrently. A loopback transaction
can occur at one node while two other nodes are performing a VAXBI transaction; To assure proper
bus operation, however,the BIlG will not initiate a loopback transaction when another node is
initiating a VAXBI transaction. Because loopback transactions extend the bus cycle, the system
access latency may be degraded.
Loopback transactions are received by the BUC similarly to VAXBI transactions except for the
following:
• High-order address bits on lines BI D < 29:13 > are ignored by the address selection logic of the
BIlC except for parity qualification. The BIlC completes the transfer the same as if these lines
contained the value 1000000000 OOOn nnn (hexadecimal); where n nnn is the ID of this node.
The address transferred to the slave port interface will be the same as the address received by the
BIlC from the master-port interface. Read-type and write-type loopback transactions have
limited addressing capability because the node ID is not required. The user's interface can access
only the node space within the node that connects to the user's interface. Addresses defined by
the starting and ending address registers of the BHC can be accessed only by VAXBI transaction
requests.
• The BIIC does not arbitrate for the bus and VAXBI transactions are not generated. If the bus is
idle, a loopback transaction begins two cycles after the loopback request is initiated. The BI NO
ARB and BI BSY lines are asserted during the command/address cycle of the loopback request to
assure that no other BIlC will interpret this request as a VAXBI bus transaction. Asserting these
signals extends a current VAXBI transaction to allow the completion of the loopback transaction.
If a VAXBI bus transaction has been initiated, the node with the pending loopback request waits
to verify that it has not been selected for the VAXBI transaction before processing the loopback
request.
• The dual round robin arbitration priority is not updated by the BIlC during the embedded
arbitration cycle of the loopback transaction.
Diagnostic Mode-This mode is reserved for Digital and is used in the development of bus testers,
bus monitors, and other diagnostic equipment. It facilitates testing of the BIlC and provides access
to the VAXBI bus. Refer to the VAXBI Systems Reference Manual for detailed information on the
diagnostic mode.
The BIlC supports the BCI-te-BI and BI-te-BCI transparent mode operations where the BCI signals
are reassigned to correspond with the VAXBI bus signals except for the BI ACW and BI DeLO
signals. The assignments and state of the signals are shown in Table 41.
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18b1e 41- Diagnostic Mode Bus Signal A~signmentl
BCILilte
State
BIUne
D<31:00>
inverted
D.q:31:00>
1<3:0>
inverted
1<3:0>
PO
inverted
PO
EVO
not inverted
CNFO
EV1
not inverted
C~~
EV2
not inverted
CNF2
EV3
not inverted
NO-NU'
EV4.
not inverted
BSY
. In the BCI-to-BI transparent mode, the user's ini:erface transfers ~1l1 on tlle BCI D <.1j:OO > ,
BCI 1< 3:0 >, and)3CI PO lines with. the normal setup time and th~~ qata is synchrOnously
transferred to the VAXBI bus by the BUC.
In the BHo-BCI transparentrnode, the data re<.:eivedfn)tn,theVAXBI bus islatclled:duril;lg each
cycle and transferred: to the BCI lines by the BUCduringeach cycle. Data is transferred: to the BCI
in the same timing ~uence as a nontransparent mode.
The diagnostic mode supports a command that allows the loadtitgof the device type, node ill, and
parity mode ififormation at the end of the assertion of the BClDC LO signal.
During the diagnostic mode, the BIlC examines the BCI interrupt and response lines
Bel RQ< 1:0> to determine the diagnostic mode operation: Thecocleon these lines musfnot be
transferred until the BIlC completes the sel£-test.The diagnostic m6deoomrol signals OIl lines
BCI RQ< i:() > , BCIRS < 1:0> , IlndBCUNT <:: 7:4> maybe trans£erred:during thesamecycldn
which the BIlC is set to transparent mode. The operatlngmodecan be changed by the
BCI RS < 1:0 > and BCI INT < 1:0> lined without deasserting the BcI RQ < 1:0> lines. The new
operation begins within three cycles after the mode change. Table 42 lists the response eodes for
the diagnostic mode.
.
18ble 42 - VAnI 78732 Diagnostic Mode.Opetatiog Codes
BCIRS Line
1
0
BCIINTLine
7
6
,
4
H
H
H
H
H
"H
No operation
H
H
L
L
L
L
BCI-to-BItransparent mode
H
L
H
L
H
L
Load configll):'ation data
L
L
L
L
H
H
BI~to,BCI
~tiofl
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transparent mode
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PreJiminary .
VAXBI781)2
Read-type Transactions .
During master-initiated read-type transaction; the master-port interface requests a VAXBI transaction through the BCI RQ < 1:0 > lines. The BIIC responds to this request by asserting the
BCI MDE signal to indicate to the master that a VAXBI command, address, and parity information
(for user-generated parity) should be transferred on the BCI lines. When the BIIC wins control of
the VAXBI bus, it transfersthls information to the bus and asserts BCI RAK line. The asserting
edge of the Bel NXT signal indicates when valid read data is on the Bel lines. If a STALL command
is received from asIave, the assertion of the BCI NXT signal is delayed until an acknowledge is
received. Following the last data cycle, the BIle issues two acknowledge confirmations on the
VAXBI bus if the transfers were successfuL The final acknowledge can be inhibited by the user's
interface if it asserts the Bel MAE signal. The MPC event code is transferred during the cycle that
the final acknowledge is on the VAXBI bus. The BCI RAK line is also asserted at this time unless the
master port issues a pipeline request.
All BIIC nodes deassert the BCI CLE line during the embedded arbitration cycle to allow the data
from the BCl to be loaded intO the BUC. Each BIlC determines if the transmitted address is within
the range of addresses that are allocated to its node. The BIlC in the selected node asserts the
BCI SEL line and issues the appropriate select code on the BCl SC<2:0> lines. The command
response of the slave must be transferred on the BCl RS < 1:0> lines before the end of the
embedded ARB cycle. An acknowledge response is a positive command confirmation and indicates
to the masterthat the data cycle in process contains valid read data. During a read-type transaction,
a stall response indicates that the data is not valid, a retry response indicates that the command
cannot presently be completed, and II no acknowledge response indicates that the node was not
selected by the transmitted address. The slave provides read data, data status, and responses
continually until all data is transferred from slave to master. At the end of successful transactions,
the BIle of the master node transfers two acknowledge responses on the VAXBI bus .. The BIIC of
the slave node responds with a AKRSD event code during the cycle following the final acknowledge
response of the BIlC.
The BIIC controls the read transactions with its internal registers. The user's interface, however,
can monitor the read transactions of its node ~pace if the BCISREN bit in the BCI control and st?tus
register was set. When a successful read-type transaction to an internal register of theBIIC has been
performed, the BIlC issues an AKRSD event code.
Write-type T'tsnsactions
The master-port interface requests a VAXBI transaction on lines BCI RQ < 1:0>. The BIlC
responds to this request by asserting the BCI MDE line to indicate to the master that a VAXBI
command, address, and parity information (for user-generated parity) should be transferred on the
BCllines. After the BIlC wins the VAXBI bus, it transfers this information to the bus and asserts
the BCI RAK line. During the embedded arbitration cycle,· the assertion edge of the BCI NXT
signal indicates that the first .data word should be ready for transfer to the bus. During the same
cycle the BIlC asserts the BCI MDE line that transfers the first data Iongword from the user's buffer
to the BCI bus. The BCI NXT and BCI MDE signals transfer each data word during a cycle until the
transfer is completed. An additional BCI NXT cycle occurs at the end of this transaction if the
pipeline NXT enable bit in the BCI control and status register is set. After the last write-data cycle,
the slave transfers two acknowledge responses. The BIle then issues an MCP event code to the
user's interface a.nd in the same cycle the Bel RAK line is deasserted unless a pipeline request was
issued from the master-port interface.
All BIlC nodes deassert the BCI CLE line during the embedded arbitration cycle to allow the data
from the BCl to be loaded into the BIle. Each BIlC determines if the transmitted address is within
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I
the range of addresses that are allocated to its node. The BIIG in.the selected node asserts the
BCl SEL line and issues the appropriate select code on the BC~ SC < 2:0> lines. The command
response of the slave must be transferred on the BCI RS < I:P > lines before the end of :the
embedded ARB cycle. An acknowledge response isa positive comlmandconfirmation and indicates
to the master that the data cycle in Ptocess contains valid read d,lita. N,stafi response indicates that
the data from the first data cycle should be rePeated in the sCl!conddata cycle. A retry response
indicates thilt the command cannot presently be· completed.' .A \-to a.ckribwledge response indicates
that the node was not selected by the address transferred.
The slaVe-POrt interface provides an acknoWf&igebr stallrespbnse f¢each data cycle until all the
data is transferredfrrim master to slave. At tBe~d d£ succ~sful.iransacti6ris, the BIIC of the slave
nOde transfers two acknoWledge respon.ses ontbebusand the nne ofthemaSteI node. responds
With a MCPevent code dining the cycle follOwing the £irullacknowledge response of the slave.
The BIlC controls
the write transactions with ,it~ internl1l. regist~rs.The u~'s interface however
can monitor the write transactions if the nCISREN bit in the Bci~ol1trol an!i1status register is set.
A write transaction to anj,nternal register or to Il. ~ is simila,r ~t that .the information on the
BCI RS< 1:0> lines has no effect on the ccmflimation ~spons~ofthe BIlC, When a successful
write-type transaction to an internal register of the nnc has been performed, the BIlC issues an
IRW event code.
Inrerrupt and Ideritification Tmnsactions,
The BIlC can generate a u~er's interface inter~pt bl,"an error interrupt by transmitting an INTR
command on the VAXBlhus. Errorlntenuptrequests have the, highest priority for transaction
transmission and in response toIDENT commands.
The user's interrupt is initiatedbytbe interfacewhenit asse~ts one of the BCIINT < 7:4> lines or
when it performs a write transaCtion to set the appropdate iOterrupt force-hitin the .user's interface
interrupt control register.
The error interrupt is ~litomatically generated by the BIlC when ~bus error is detected and the hard
error interrupt enable (HER) bit of the VAXBl control and status !;Ii:gister is set. The user's interface
can also cause an error interrupt by setting theinterrupdorce(INTR force) bit in the errorinterrupt
control register.
Following an interrupt request, the BIlC arbitrates for the VAXBI bus and, after winning the bus, it
initiates the interrupt transaction. The user's interrupt and error interrupt use . the INTR
destination register to select a node. During the command/address cycle of the interrupt
transaction, the appropriate INTR Sent bit is set inthe user's interface interrupt contrplregister or
the error interrupt control register.
If more than one interrupt level is pending for the user's interface, the BIle::: will transfer an
interrupt request with all interrupt levels indicated when the VAXBI bus is avaih,tble. Because only
the INTR Sent bit of the highest pending level is set, the BIlC "Yill arbitrateforthe VAXBlbus again
to send the remaining levels of the pending interrupts. TheBIIC transmits the INTR command
without interrupt levels if the interrupt condition is removed and the user's interface deasserts BCI
INT < 7 :4> one or two cycles before the arbitration cycle has occurred.
Slave nodes capable of receiving interrupts should set the appropriate interrupt pending bit or its
equivalent to recotti the ir,lterrupt level received. This information is transferred in the level field on
the BCl D < 19:16>- lines during the identification command/address cycle. When the interrupt
command is not successfully received, ,the BIlC sets the INTRAB and INTRC bits in the user
interrupt control and status register at the levels received during the interrupt command. The
INTRC bit prevents additional interrupts at that level from being transferred. Therefore this bit
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VAXBI18132
must be cleared and reset by a node to again initiate an interrupt request. TheINTRC andINTRAB
bits can be cleared by performing a write transaction to the interrupt control register.
The node that receives the interrupt request issues an IDENT command to obtain the vector
information from the node that initiates the interrupt. The IDENT command is initiated by the
master-port interface to request a VAXBI transaction. The identification level information
consisting of only one level bit is provided by the user's interface for transfer during the IDENT
command cycle.
. All slaves with interrupt requests pending at the same identification level will participate in IDENT
commands by veri£ing that the decoded master ID transferred during the third cycle is the same as
the bit set in their interrupt destination register: When both condition exist, the node participates
in the identification arbitration. User's interface data froq} the slave port is not required unless the
external vector bit of the user interface interrupt control register is set. The BIle can transfer an
external vector selected event code (EVS7 through EVS4) during the identification arbitration
cycle if requited.· The event arbitration lost (IAL) event code causes the slave-port interface to
return to the idle state. The use of this code is shown in Figure 43. Nodes that use external vectors
must stall the vector transfer for a minimum of one cycle.
VAXBI ACTIVITY
CYCLE
2
3
4
5
6
CIA
IA
DECODED
MASTER
ID
IDENT
ARB
STALL
VECTOR
ACK
VECTOR
M3
M3
M3,51.
S2
M3.51,
52
51.52
52
M3
M3. S1.
S2
M3.51.
S2.
STALL
51
ACK
S1
1
-"
BISSY
SOURC E.
BI NOARS
SOURCE
,
7
B
ACK
M3
ACK
M3
/
"M3
BI CNF Code
SQURCE
Bel ACTIVITY
I
I
I
I
Sf-Slave that Wi~S IDENT A~B
SLAVEBCIRS <1:0>
I
AKRNEn
EVSn
52-Slave that loses IDENT ARB
SLAVEBCI RS <1:0>'·
EV<4:0> L
EVSn
IAL
+
52 slave port
interface
returns to
an idle state
I
Figure 43' VAXEl 78732 Identification Transaction Event Code Timing
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The winner of the identificati'On arbitrati'On transmits the interru~t vector. The .slave-port interface
can stall if the vector is not itnmediately available. After the masteti of theiclentificati'On transaction
has acknowledged thatthe vector was received, the BIle transfers an evc:nt;eOOe(AKRNE7 through
AKRNE4) and the INTRCbit in the user's intetfa<:e interrupt controlregistetis set. The slave-port
interface can decode the class 'Of the event and use these ~. to deassert the appropriate
interrupt request. User's interfaces that gate multiple interrupt~esonto one interrupt request
line can prevent the loss 'Of a request when thf! request)ineisdea~ert!d by clearing the INTRC bit
after the interrupt is serviced. If a vector transfer to a master tai1siand the master does not transfer
the final acknowledge, the slave-port interface t~fql'S~UJeg~ confirmation received (ICRSD)
event code. The BIlC automatically resen9s thein~'if;the ~terrupt request is still pending
and the master may request the same vectdr in subSequent ident~ation transactions.
l
Interrupt Sequence
Figure 44 shows the interaction ofthe BIlC and the user's interfaF to the INTR transaction. Refer
to the VAXBI System Reference Manual for detailed transaction ir1£'Ormation.
I(
I
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4·87
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. - -..•..- - - - - - . - . _ ._ _ _.......L-... -.... _ ... _ _ _ _ _ _
~_.
_ _ •• _ _:
VAxBI78732
USER (\t(TERFACE
flEQUESTS AN INTR BY
ASSERTING AN
.
.OSER INTERFACE
REQUESTS AN INTR
BY SETTING
INTR FORCE BIT
INTEFlFltlPT SIGNAl
(1NT7:4 )
NODE 1
BIICSENDSAN
INTR AND SETS
INTR SENT BIT
NODE 1
NO
BIIC SETS INTRAB BIT
AND INTRC BIT
NODE 1
YES
SLAVE USER
INTERFACE(S) SET
INTERRUPT PENDING
BITS AT THE
INTR LEVEL(S)
®
NODE 2
WAITS FOR IDENT
NODE 1
NODE 1
Node sending the INTR
NODE 2 Node responding to the INTR
Figure 44· VAXBI 78732 BIle and User's Interface lNTR Sequence Flow Diagram
Identification Sequence
Figure 45 shows the interaction of the BIle and the user's interface to the IDENT transaction.
Refer to the VAXBI System Reference Manual for detailed transaction information.
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VAXBI78~}2
SENDS IDENT.
U~ERINTERFACE
RESETS INl'EAAUPt
PENDlNGBtT
AT THE !DENT
LEVEL
NODE 2
WAIT FOR NEXT IDENT
®
BIIC RESETS
INTR SENT BIT
AT THE IDENT LEVEL
I
YES
TRANSMITS veCTOR
>w.:..__ STOP
(ErrHe:ft INTERNAL
OR EXTERNAL)
NODE 1
NO
I
i .
Bile SETS tNTRC BIT.
NODE 1 Node that sent the INTR
NODE 1
NOOE 2
Node responding 10 the INTR
I,
Figure 45· VAXBI 78732 BIle and User's Inteiface IDENT Sequence Flow Diagram
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Interprocessor Interrupt Thmsaction
Interprocessor interrupt (IPINTR) transactions can be initiated by the master~po1"t .interface by
requesting a VAXBI transaction and issuing an IPINTR command in response to the assertion of the
BCI MDE line. The user's interface must then provide the decoded ID of its own node and the
destination mask.
The IPINTR transaction are also initited by the BIlC when the user's interface sets the IPINTRj
SIDP force-bit in the BCI control and status register using the destination mask froQ:! the IPINTR
destination register. The force bit is cleared by the BIlC after the transaction has been completed. If
the transmission fails, the NICIPS event code is transferred and the NMR bit of the bus error
register is set.
A node is selected when an identification match occurs between the decoded master ID and the
corresponding bit is set in the IPINTR mask register and between the nodes decoded ID and the
corresponding hit in the IPINTR destination field. A slave node that is selected will set the hit that
corresponds to the decoded ID of the master in the IPINTR source register;
Broadcast Thmsactions
Broadcast (BRCST) transactions are reserved for use by Digital Equipment Corporation. The BIlC
responds to these transactions similar to read-type transactions. However, the stall and retry
confirmations are not valid for this multiresponder transaction. The stall code can be transferred
on the response BCI RS < 1:0> lines to extend the time of the transaction by keeping the BCI BSY
line asserted. The stall code produces an acknowledge on the BI CNF<2:0> lines during cycles
where an acknowledge confirmation from a slave node is on the VAXBI bus. The BI BSY line is
asserted during all cycles. If the stall code remains after the last confirmation cycle, no information
remains on the confirmation lines and the BI BSY line remains asserted.
Stop Transaction
The SIDP command is initiated by the master-port interface. The user's interface provides the
destination mask and SIDP command code to be transferred during the command/address cycle. A
slave is selected when the ID decoded by the slave matches the destination information of the
INTR destination register. The slave-port interface provides the command confirmation· on the
BCI RS < 1:0> .response lines and the slave is .initialized.
Invalidate Uansaction
Invalidate (INVAL) commands are initiated by a master-port interface. When the BCI MDE line is
asserted, the user's interface provides an address and data length code that indicates the number of
longwonlsto be invalidated. Slaves that have the INVALEN bit set in the BCI control and status
.
register are selected for this transaction.
Reserved Commands
Reserved commands are recognized by the BHC as three cycle VAXBl transactions consisting of a
command/address cycle that contains user's interface data, an embedded arbitration cycle, and a
data cycle in which the data lines are deasserted. The master requires an MCr, NCRMC,or ICRMC
acknowledge event code from the slave. A slave can respond to a reserved code of (HLHL) or
(HLHH) on lines BCI I < 3:0> if the reserved enable (RESEN) bit is set in BCI control and status
register. The slave responses to the reserved commands can be an acknowledge, no acknowledge or
stall on the BCI RS < 1:0> lines. The event codes used are bus busy error (BBE) and stall timeout
on slave transaction (SID).
.
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VAXBI78732
Transaction Priority
The BIICrecognizes more than one pending request. A VAXBI t~saction request, an error
interrupt request, an interprocessor request, and a user's interfacb interrupt request may be
pending simultaneously. The priority for processing multiple request~ is, listed in Table 43.
;
I
.
i
Table 4} • VAXBI 787321':ra1lsaePon Request Priority fssignments
I
Priority Request
Level
.
I
1
Loopback from master-port interface
2
Interrupts (INTR) controlled by error interrupt control regisfer
3
Interrupts (INTR) from user's interface interrupt control register or BCI INT l~ne (level 7)
4
Interrupts (INTR) from user's interface interrupt control reaisterior BCI INT line (level 6)
5
Interrupts (INTR) from user'sinterfaceinterrupt control ~gisteror BCI INT line (level 5)
6
Interrupts (INTR) from user's interface interrupt control register or BCI INTline (level 4)
7
VAXBI transaction from the master-port interface
8
Interprocessor interrupts (IPlNTR) £roJ;h the BCI control a~status register.
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Figure 46 shows the types of requests and the timing relationship between th«,posting of t~e
request and the priority assignment by the Bue. The BIle examines uhe reque~t and establishes its
priority during the prioritization cycle.
. .
.
PRIORITIZATION
CYCLE
ARBITRATION
CYCLE
IPINTR
FORCE BIT
SET
E1NTRCSR OR
UINTRCSR
FORCE BIT
SET
-
BIIC PRIORITIZES
REQUESTS
INTUNE
ASSERTED
LOOPBACK
REQUEST
(1)
VAXBI TRANSACTION
REQUEST (2)
NOTES:
1.
Loopback transactions have a dummy ARB cycle at this point.
2.
If the VAXBI transaction request is posted while other types of requests are present. the BIIC
prioritizes the VAXBI transaction request along with the other requests during the prioritization cycle.
However. if no other types of requests are present. the BIIC attempts to arbitrate in the next cycle.
,Figure 46· VAXBI 78732 BIIC Transaction Priority Sequence
When no requests are pending, the Bne arbitrates the VAXBI transaction request in the cycle that
follows the request to minimize the bus latency time. If a VAXBI transaction request is posted while
other requests are present, the VAXBI transaction is assigned priority together with the other
requests during the prioritization cycle .
• Transaction Timing Sequences
Figures 47 through 74 are functional diagrams that show the timing sequence of the signals used to
perform VAXBI interface transactions. The signals that communicate with the VAXBI bus are
prefixed with a BI designation and signals that communicate with the user's interface are prefixed
with a Bel designation. Table 44 lists the figure numbers and captions that includes notes that
define the transaction operation.
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Table 44 • VAXBI 787.32 Functional Timing Diagram Descriptions
Condition
48
Loopback lorlgword
read-type
To BIlC CSR space with an idle bus and with BICSREN set.
49
Loopback longword
Occurs within node on top of a longword read with a stalled
VAXBI tranSaction between master-port interface and node 1
and the slave-pbrt.interface and node 2.
read-tYPe with Stall
52
Quadword read-type
with pipeline request
MaSter quadwbrd read to same slave node.
59
Force-bit requested
interrupt
An INTRtransaction initiated by a force bit in the
Force-bit requested
interprocessor interrupt'
An IP~N1'R transaction initiated by it forCe bit in the
66
Stop
. Indicate~' the, .~ultsot one allowable response to a STOP
command. Although BIlC 2 wins the imbedded ARB in cycle
5, itl,lssetts'Bi NOXlm in cycle 6 because of the SlDP
com,rtland. reuSer .2 holds BCt REO asserted, BIlC 2 would
afbitratelh tide '1 and continue the transaction.
67
Stop with extension
Slav~-portintertaceilljtiates a stall response to assert BI BSY
signal while node completes Stop operation.
69
Burst-mode write
operations with pipeline
request
Begins at first arbitration cycle won by this node after the
BURSTEN bit of BCICSR was set by previous transaction. A
quadword write is fonp~d . by a longwon;i write to the
BCICSRto clear BPXS'I'BN'bit .
70
Burst mode writes with
pipeline request and
PNXTEN bit set
.BCI CLE is asserted ina cYclefolloVling a cycle with
BI NO ARB asserted and.HI BSY deasserted and until To of
the command /address cycle.
71
Special case 1
1. Master 1 wins arbitr' from all~tbit~ting nodes
DSM .
destination mask indudingl~,~eld]fi)l: SPCS1' .~mand
IDD
master ID anddestiniition code
ILV
identify level(s) on lines 0< 19:1~>
INTR REQ
interrupt request .
LB REQ
loopbaclr request
LCD
level and destination code
M
master node
MID
master ID
MKI
write mask 1
NAK
no acknowledge confirmation c0ge
REC
retry confirmation received for nlaster~.J? L
81 0IF(2Ie) L
ttlNJERtt 1 I
2 I
Btl RQ(1:0)1:
BtUHT<7:4)
Btl Wl
Btl NKT L
Btl Ill[ l
- ------ -
SCI !WI L·
SCI M4rtl)-L ----- - - .----- -----
ttSlMtt
11
2 I
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Figure 48 • VAXBI 78732 LQopback LQngword &ad~type. Ttttnsaction Timing Sequence
4-97
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VAXBI78732
R£f'ER£NIt
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Figure 49· Loopback LongU'ord Read-type (Stall) Transaction Timing Sequence
4-98
Confidential and Proprietary
Preliminary
VAXBI18132
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Figure 50· VAXBJ 78732 Retry Longword &pd-ty.p,e (Stfl,1l) Tra.1JSaction Timing Sequence
Confidential ~ Propd\-,!tary
4-99
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VAXBI78732
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81 NO filtH
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Figure 53· VAKEI 78732 Quadword Read-type (Pending master) Transaction Timing Sequence
4-102
Confidential and Proprietary
VAXBI78732
I£FDH£.
Bel TIlE!.
Bel
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81 NO ARB L
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Bel
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Bel SOH
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Figure 54 • VAXBI 78732 QuadWbid Write Transaction Timing Sequence
4-103
VAXBI78132
II£'FEI8U
" IICI TIlt: L
81 Nl MIl L
Bl BSY L
BI0f'{2:1)-l
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Figure 55· VAXBI 78732 Quadword Write (Pipeline request) Transaction Timing Sequence
4·104
Confidentill1 and Proprietary
-
VAXBI781'2
Huret!
81 IlSH
StUre:.
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IIUW<2:0) L
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Figure 56 • VAXBI 78732 QuadwordWnte (Stall for each'lonfJilordo/ data) Transaction Timing
Sequence
Confidential 'and PrOprietary
---------... _------_.....
_---------,
4-105
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...
....
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VAXBI78732
REfW)I:E
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Figure 57 • VAXBI 78732 Octaword WMCI (Variable stall for each longwotd of data) Transaction
Timing Sequence
4-106
Confidential and Proprietary
VAXBI78732
,:.,,:
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Btl .... L
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Figure 58· VAXBI 78732 Octaword W,MCI (Variablestalljor et;ll;hlongword()j data and Pipeline NXT
Enable bit set) Transaction Timing Sequence
Confidential and Proprietary
4-107
,
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VAXBI'S732
I!Cl
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IICl WL.
IICI I«T L
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source
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Figure 60- VAX.BI 78732 INT< 7:4> ReqttestedJntertupt TransaetionTimingSequence
Confidential and Proprietary
14 1
VAXBIV87)2
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Figure 61 • VAXBI 78732 Master-port Interprocessor Interrupt Transaction Timing Seqflence
4-110
Confidential and. Proprietary
VAXBl7i132
R£fBEtQ;
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Figure 62· VAXBI78732 Force-bit Requested lnterprocessor Interrupt Transaction Timing Sequence
Confidential and Proprietary
,4-111
-------.----~---"-------,
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Figure 63· VAXBI 78732 [DENT (Internal vector)
4-112
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Confidential and Proprietary
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Figure 64· VAXBI 78732 IDBNT(&temal vector) Transaction Timing Sequence
ConfidtntW and Proprietary
4-113
VAXB1787.32
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Btl TIlt: L
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Figure 65· VAXBI 78732 INVAL Transaction Timing Sequence
4-114
Confidential and Proprietary
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VAXBI78732
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- .----~-.-- ·----4-----~- ------t:----t---··-+----:t----·:::t------f----t=---- .--.,. -----:: :: ~ -- ......+-.---., ----·-+------L____ j-----·-t----·-+-----+----·-t---···-t--··--·t--·-1.----- ------·f
1 ··-----j.------i---·-·-t-··--·-t--~~:·i------+--·t----·--t..---"t"-----t--·-4!---~::!I~·---·--LI' ---A_At
Btl 1<3:0) H
S/---< d'--,
I .-_--L--..-f./
-.
I
I
,
,.
0
Itl
DCI CLE H
DCI SC(2:0)
8Cl EV(4:0}
__0
____
.____
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_
I
_ _ _ _ _~
,
____ •
____•
__________
I
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I
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i
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-L~I'-'---- t------·t·.. ---·~--·- ---t-- --·--t-----··j--·----,---- --1---··-t---·---t-------r-------t-- -----t-------!
t
I
,
!
:
~
1
1
i
i
;
Figure 66· VAXBI 78732 STOP Transaction Timing Sequence
Confidential and Proprietary
4-115
...
VAXB1787)2
REf'EItDIU
Bel Tilt: l
Bel PM L
-
BII«lMBL
sourell
BI IISH
sourell
sa
--12
---oil ---ii-
1-------
'_If
91 0(31:08) L
_ell
l1li
BI 1(310) L
SOUfell
BI CNf<2:0) L
SOUYelI
-At HASrER-At
2 I
1 I
3 I
41
12 I
13 I
14 I
Be! O(31100}
sourell
11:1 1<3:0)
~
15OUTc:e
Itl IQ<1;O)-L
11:1 INT<7:t>
11:1
AAI(
-- -- _- ----....... ----- _- _... __
..
..... ...
.. ...
--- ---- no rlllu st ---- -.----- ------ ----- --."
_- --- -_ -_ -_ _- --- -----...
----
....
... ...
----- ------- ----- -
L
11:1 1«1' L
11:1 IU l
+--+~-
Bel IWI L
Bel EV(410)L
-AtSI.M-At
--t----t--+
-_!!£!-
1 I
2 I
3 I
4 I
8 I
9 I
10 I
11 I
12 I
13 I
14. I
llel 1)(31100)
sourell
Bel CLE H
IICI
SI)[
L
Bel sa L
Bel SCt210}..,.Lt----t
--- --l!:!:_ -
._+---+---- ---- ----
--- -----.. --
Itl £V(418)L
Figure 67· VAXBl 78732 STOP Transaction (Extension) Timing Sequence
4-116
Confidential and Proprietary
-
A£F09ICE
SCI T11£ L
SCI
l
PIN(
81 NO AU L
Huret
BI IISY L
81 I<3:0) l
souret
81 1lIF(218)L ••---- ----
",Sltatt 1 I 2 I
SCI D(311"L ___•• _ _
lit
IlCI 1(318) H
-
- - _ ... -
setret
-"':"'''''!'''
SCI RQ(hO)L IlCI IN1"<1:4r --_.
IlCI W l
Btl tOO" l
Btl It)[ L
-+-",,+-·-r.,__
Btl I'M l
1£1 EV(4:0)"l _ ...-- - - - lH
SUM:
1 I
lH
2 I
3 I
4 I
Btl D(31I88)
MVrc:e
Btl H310)
~
Huret
Btl KS(110) L
Bel CI.E H
Btl SOH
Btl
sa l
SCI !IC(218) l
Figure 68· VAXBI 78732 Quadword BDCST Transaction Timing Sequence
Confidential and Proprietary
4-117
Preliminary
VAXBI78712
'R[f~
SCI TlMEl
SCI PINE l
81 Nl ARB L
--~-
source
\
III 8SY l
source
---.r-
lI1,iz
--iii- ----Iii- -Bi:;2"
\ -dat
91 D(31100) l
sourCII
- 111
--ai- -iii -"it
1----- ------ \
-iii- 1111
-;r-
--Bi-
X' da2 , - ' \
111
111 ,52
--.ar- ,-'-- \ dii r-·
-ai
111
- '...."!!II- lC!!d_
-~- -dfX...!.o __ , ----
BI 1<3:0) L- ----sourCII
111
111
II CNF«10)-i:
111
X
18 I
11 I
---;2
source
it msmt it 1
a. rid- /--
\ a.
---;2-
52
12 I
13 I
14 I
SOUTCII
BCI 1<3:8> H
source
SCI RQ(l :0)-L
";'-T ~
!i::7 -----,- -~- !i:-- -=:==
-=:= ::-=:- :::--
BCI1NH7:4)
SCI WL
SCI NXT l ..
\--- ----- -\_---
BCI fIlE L
IICI tNt
SCI EV<4:0)-L ------ ---- ---
I!
itSlAV£it
___1- ----- .. _-- ------... ____1- ------- -_ ...... - -_ ........ _- ------...
---- -...---- ----.. - ____I
2!
3 I
,----
~
----- ------ ------ ------ ------
:~_
4 I
'I
:I I
----
,-. -.... -_.............. ...-- .._...-. - _......_-
Ii I
7 I
8 I
------ ------ __
10 I
11 I
EL :=!£2:: ------
12 I
13 I
141
BCI O{31:00,:...>-h--+-50urCII
SCI 1<3:0)
~
source
SCI RS(1 :o} L
Bel ClE H
SCI SDE l
SCI sal
BCI £V{4:0) L
-- ------ -----+-.-+----- ----- - - -- -'-r'--t-
Figure 69' VAXBI 78732 Burst-mode Write (Pipeline request) Transaction Timing Sequence
4-118
Confidential and Proprietary
~------~---~----~--.,-.,--~---~.-~--.,..-~----~~~-~------".--~~-,~--'---,--~,-,~~~~~'--~~---~----~~~----------
-
VAXBI.187J2
. REJBiJrICE
acr TD£L
llel PINEL
81 NO ARB L
81 lIS\' l
source
81 0<31 :10> [
source
BI H3lll l- -._-
sourct
III 1l*(2:0) L
it
141
MST£A i t 1
llel 0(31:10,:...>f - - -....
sourct
Bel 1<3:8> : .oMi----c-....
sour~.
acl
W; L
Bel NICT l
llel
til[
L
llel IN l
Bel EV<4iO)1:
it
SlAIIE it
--- ---1 I
2 1
acl 0(31108)
Huret
Bel H31t) H
souret
Bel IISnlll l
Bel a.E H
Bel SIl£ L
IICI sa. l
SCI Be(2:0)~l
SCI f.V( 411>-J,.
Figure 70· VAXBI 78732!3urst-morie Write (pipeline request andl'ipeline NXT Enable bit set)
.
Transaction Timing Sequence
Confidential and Proprietary
4-119
Preliminary
VAXBI78732
REJ'EIIEtQ
SCI TIllE L
1£1 PfIi'lS£ l
81 NIl ARB l
source
8] BSY l
source
81 O(31100) l
source
BI CNF(2:0) l
---
\
source
it
IIASTEJt it 1 I
l! I
3 I
4 I
5 I
----if"
iICk X--.ct
I
112
7 I
X-';- X"""iId- X-ad X--icl° X--idt- I
--if" -Ii
8 I
9 I
~
52- --sf"
131
14
------- ------ ------ ------- ------ ------ ----- ------ -----
_:E~::
::!£e=:
-----~-
3 I
12. I
13 I
14 I
18 I
111
r
12 I
fi
IItI O(31:00!
source
IItI 1<3:8> H
source
SCI RQ{1I0)-l
IICIINT<7:4}
Bel RAK L
----- ------ .....__.....------_... ---- -.I
-------\_\_-
SCI NXT L
SCI HOE L
SCI IWll
SCI EV(410)-l
** r
2 I
StAlE
IItI D(31 :..~
it
4 I
5 I
Ii I
7 I
8 I
"
10 I
11 I
source
Bel I (3:0) ~___________ _
source
scI" RS<1:0) 1: ----SCI CLE II
SCI SIlE L
... _- --------...- -_..__..._---
SCI SEL L
lit! SC(2:0)-[ - - - ---- ----- -----
::£I&~:_
------ ---- ----- :~~_ --!iiy- nr-
-_
-;T---
- --_.._- ---- -...---- ..- ..-...---- ----...._-- ......
_!!L_~
Figure 71· VAXBI 78732 Special Case 1 Transaction Timing Sequence
4..120
Confidential and Proprietary
8i HII MIl L
_rce
81 BSY L
souret
81 0(31:08> L
souret
811(310) l
_ret
8i Of'(211) l
source
** tNT£ll
it
1
,
2 I
IItI O(31:88!
source
IItI H3111} ___________ _
~
IItI RQ<1 :8> -i:
-----
--\~
1£1 W l
IItI IIXT l
1£1 IfOEL
Bel /MIl
1£1 EV<4te>-[
it SI.AUE
**
---- ---1,'
2 I
1£1 O(31I00t. _ _
1£1
1(310)
1/
lOurl:e
1£1 RS<1I8> l
1£1 ctE H _ .______ _ ___ _
IICI SIlEL
IItI sa L
IItI SC(21.)"7lt---1I----fIItHV<4Ie)-l ----- -----
Figure72· VAXBI 787nSPFciai (';ase 2 TransactjQnlimingSequence
Confiden~iatand
Proprietary
4-121
VAXBI78732
ItEFWHtE
SCI Till: l
\
HI BSY L
1-------~- ----~
"urc:.
81 0(31100> L
'_!"L
_
sevrc:.
x: adr-::
x:!!e..
X::!!!1_ r~
111
_
111
111
-RES \"!IId riiid r
---~-
sourelt
---~
-oar
-~;52-
Ilk! X-l1li2
--~
--iii
X_1IIlr leo.!'
112
112
1------ ------X__dal 1
r;r Ciiii" X
--ji2- --ji2-
- - ---.
..,....~.-t
112
l1li1
--;r
r-- ------ ------
x""'"icl- x""'"icl- X-Iii'" X-.ct- x-act
--7 --52 - 52 ---52 --52 ---52- --52
-t--t--t--t\:-::ad~X'- ack
** ItISTER **
2 I
1
3 I
4 I
5 I
(; I
7 I
8 I
9 I
10 I
11 I
12 I
1-----13 I
14 I
IICI D(3lIGe!
SCI
1(310) '-Lt--t---t-'
"arCII
SCI W L
'-I'--_I~_--IC=-
IICJ NXT l
SCI HOE l
\-
=-,'';_'_--==-t-.=± _
____
\_--
SCI !WI L
SCI EV<4:8>-:+.--t---L
---- ----- ----- ------- ------ ----- ------- ------ ------ _!!!L
----- -__ ------_..!:e
oft SIAIE oft
3 I
Z I
1 I
.. I
:I I
I> I
7 I
8 I
!t I
10 I
11 I
12 I
SCI D(31108}
Hure.
SCI 1<3:0)
~
SCI RS(1I0} L
SCI CLE H
SCI &DE l -f---l
llel SEL L
------ ------ ---- _-iii£::
SCI lV(410} L
Figure 73· VAXBI 78732 Specia/Case 3 Transaction Timing Sequence
4-122
Confidential and Proprietary
13 ,
14 I
REfOBU
Btt'lUl: l
II lISt' l
8t D(S!.!") l
IHTct
II 1(311) l-81 01'<21') L
.lit
1fISTER .•lIt .1
2 I
3 I
•
Btl D(311881
_rClt
Btl HaID> !!..r---~--f----+
source
r==t==:::t
tlCl INH7:4>1>
SCI IIIIK L
SCI I«T L
IItI !tIE L
Btl ItlB l
SCI [v(4,O>-[ ------- -----
1 I
2 I
SCI O<31180L ____ _
lItSIJIIEtt
3 I
1£1 1<3111>.8
SCI RS(hO) l
SCI Cl£ H
SCI SIlE l -f---f---f-
SCI SEI. L
IItI 51:(210) l
IItI [v(418)
--- ----
\-
-'-- _.._- -......-
--t~rl-'---
--f---f---f---t
,...-t-'"-t
-r ------- ----Figure 74· VAXBI 78732 Special Case 4 Transaction TimingSetJUCnCc
Confidential and Proprietary
• ,Applica~plnformation
The 'V4XBI SYste.msRe/erence Man~l ~;'htains d~tailed information, of the <:lperation of the VAXBI
bus and applicition information of the BIrG.·
,"
,
• Specifications
The mechanical, electrical, and environmental specifications for the VAXBI interface are as
follows. The test conditions forthevaloes specified ate as follows unless specified otherwise.
• Temperature range: OOG to 125°C
• Supply voltage (Ved: 4.75 V,to 5.25 V
Mechanical Configuration
,
The mechanical dimenSions for mounting the 133-pin VAXBI iriterface package are shown in
AppendixE.
· Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may Cause permanent damage to a device.
Exposure to the absolue maximum rating conditions for extended periods may adversely affect the
reliability of the device.
• Pin voltages: -1.5 V to 7.0 V
io
Operating junction temperature range (TI ): ooe to 125°e
.. Storage temperature range: -5°e to 125°e
• Ambient t~mperature operating range (TA): O°C to 700 e
• Package dissipation: 4.25 W*
*Pac~ge dissipation is approximately 0.575 watts higher than:the product of the maximum supply
current and supply voltage because ofthe dissipation of the VAXBI drivers that sink the external
, VAXBI pullup current.
Recommended Operating Conditions
• Supply voltage (Vcc): 5.0 V ± 5 %
• Inlet temperature: 5°e to 50 0 e
• Humidity: 10% to 95% with maximum wet bulb 32°e and minimum dew point of 2°e
• Altitude: 0 to 2.4 kilometers
• Airflow: 200 linear feet per minute
de Electrical Characteristics
Table 46 contains the de electrical parameters for the input and outputs pins of the VAXBI interface
chip. Unless otherwise specified, all specifications are at TJ=O to 125 degrees e and Vcc=4.75 to
5.25V.
4·124
Confidential and Proprietary
-
Preliminary
VAXBI78132
',fable 46 • VAXBI 78732 de Inpu~ and Output Parameters
Symbol
Parameter
Min.
Max.
Unit
Test Condition
BCI II
Input currentl
0.33
0.10
rnA
0.2 < V", < 5.25V
0< Vee < 5.25V
BCIlm
Input current while
BCI DC LO is asserted2
-Q.25
rnA
rnA
V.=2AV
V.. =OSV
-1.0
BClloH
Output high current.
(except Bcl DC ill)
-400
.pA
V .... =BCIVoH
BClloHD
Output high current
(only for BCI DC W)
-5.4
rnA
V.... =BCIVoH
BCI loL
Output low current
rnA
V••,=BCIVoc
BCIlow
Output low current
(only for BCI DC ill .
when Vee < Vee min.)
4.0
100
lolA
V_=BCIVoL
·0 1 second
BCIClO
Pin capacitance
10
pF
BI II
Inputcurrene
BIioL
Output low current
BrVOL
Output low voltage
BIVoH
Bus voltage high
2.3
BI VIII
Input high voltage
1.95
V
BIVHRy
Input high voltage
(hysteresis voltage)'
1.45
V
BI VlL
Input low voltage
-1.0
BIVLHy
Input low voltage
(hysteresis voltageP
-270
21
V
or
tJA
0< VIa < Vee
0< VIO < BIVoR
rnA
V..,=BI VOL
0.6
V
I..,=BI loL
3.5
V
These are bus terminator specifications
30
1.1
V
1.4
V
Con#dential and Proprietary
4·125
...
Symbol
Icc
Preliminary
Parameter
Power supply current
Min.
VAXBI tSi3:2
ii
.Max.
Unit
6.0
pF
700
530
rnA
rnA
Test Condition
Lu.=O,TJ =27°C'
I••t=O,TJ = 85°C
IThese II specifications apply only when data is not being driven by the output under test.
2While BCI DC LO is asserted, the BCI D and P lines are internally pulled up. While pulled up, these
lines can source a minimum of 250 !lA at .2.4 V. The user interface logic must sink a minimum of
1.0 rnA at 0.5 V to drive any of these lines low when BCI DC LO is asserted.
lThe hysteresis voltage is defined as follows: BI VII{ -The BIIC will not detect a change in input
state if the input voltage drops to BI VHHY following the application of BI BIH • BI V1L- The BITC
will not detect a change in input state if the input voltage rises to BI VillY following the application
of BI VIL •
"The device under test must be powered up during this test and BI DC LO should be asserted,
except when measuring CIO for BI DC LO.
sT! is junction temperature with ambient temperature (TA ) = O°C.
• ac Timing Specifications
Unless otherwise specified, test conditions are at TA '" o°C to 70°C, Vee = 4.15 V to 5.25 V, and the
BCI signal capacitance load =50 pF.
Figure 75 shows the ac timing for the BHC and Table 4 7 lists the timing parameters for the symbols
on the figure. Figure 76 shows the waveforms and symbols used for thetneasurements of the
VAXBI bus. Figure 77 shows the waveforms and symbols used for the measurements of the BCI
bus. Figure 78 shows the load circuit for the VAXBI bus driver measurements. Figure 79 shows the
load circuit for the BCI bus driver measurements.
4~126
Confidential and Proprietary
Preliminary
VAXBI18'132
...-L
IIC[ ttIIE: L
Bel SIlt L
'8CJ oc:; loO L
oct ek41.)L__~__________~________-i-4~t-{~__~__________~J\____________________
Figure 75. VAXBI 78732 ac Timing Sequence
Confidential.ahdProprietary
4-127
. .II
VAXBl78732
Preliminary
Table 47· VAXBI 787)2 ac Timing Pararileters
Symbol Signal definition
Min.
Max.
Unit Reference
1000
ns
T"
TIME period'
49
T,p
TIME pulse width
15
ns
Tp,
PHASE setup time to TIME
10
ns
Tpl
PHASE hold time for TIME
10
ns
T,
Tr
BCI signal rise time2
10
ns
Figure 77-C
BCI signal fall time2
10
ns
Figure 77-C
T p,
BCI signal propagation delay from TIME
(except for BCI MDE and BCI SDE)2
0
30
ns
Figure 77-A
BCI D < 31:00 > , BCI 1< 3:0> , and < BCI PO
line signal propagation delay from TIME'
0
T,y+30 ns
Figure 77-A
Tpl
Tp>
T da•
T.w.
T.....
T.p
T.
Th
T"",
Tin,
T...
Tdp
Tdh
4-128
BCI MDE and BCI SDE signal propagation
delay from TIME'
40
ns
Figure77-A
BCI DC LO assertion delay from BI DC ill
assertion
0
150
ns
BCI DC LO deassertion delay from BI DC LO
deassertion
45
55
us
BCI DC LO assertion width following the
setting of the NRST bit
45
55
us
BCI D< 31:00> and BCII<3:0> line setup
time with BHC configured for BIlC-generated
parity
20
ns
Figure 77-B
BCI signal setup time with BIIC configured for
user interface to supply parity
0
ns
Figure 77-B
15
ns
Figure 77-B
BCI signal hold time from TIME
BCI D<31:00> and BCI 1<3:0> release
time from TIME
0
BCI D<31:00> and BCI I<3:0> release
time to BCI MDE or BCI SDE assertion
0
40
ns
ns
BCI SDE (BCI MDE) deassertion setup time to
BCI MDE (BCI SDE) assertion'
T,y-15
ns
BCI NXT, BCI MDE, and BCI SDE deassertion
pulse width
T,y-l0
ns
BCI D<31:00> and BCII<3:0> hold time
from BCI CLE and BCI NXT
T,y-25
ns
Confidential and Proprietary
Symbol Signal definition
Min.
Max.
Unit Reference
BClD<31:00> andBCII<3:0> setup time
to BCI CLE and BCI NXT
T,,-25
ns
Minimum assertion to assertion period for
BCI NXT.BCIM1)E;ElndB~1 SI5E4
J90
ns
Tbo'
BI signal setup time ~o, 1'iME
20
ns Figure 76-B
TLh
BI signal hold time froml'IME
2O~A"
ns
Figure76-B
T~
BI signal assertion delay from ·TIMfl
Tb<
BI signal release time £rom Ti'ME
TIME
BI signal fall time (C- 410 pF)
T.
T ....
·0
85
ns
Figure 76-A
0
85
,.. ns
Figure 76-A
20
ns Figure 76-C
'The minimum specification allows for proper BIIC operation in environments with up to ± 1.0 ns
of clock period noise jitter.
.
ZParameters T" T" Tpl> TpZ. and Tp} are for 50-pF loads. The following equations describe the
degradation in rise and fall time and propagation delays for a BClline with between 50 and 100 pF
load.
T. (50 pF < C. < 100 pF) =T, (50 pF)+ CJ17.8::--2.8.
Tf (50 pF < C. < 100 pF)=T1 (50 pFf+CJ17.8-2.8.
T'I (50 pF F)+ CJ5.5-9.1.
Tp2 (50 pF < C1 < 1091'£).=:=1'" (50,pF)+,eJ5.5-,-9.1.
Tpl (50 pF < C1 < 100 pF)=Tp) (50 pF)+ CJ5.5-9.1. .
'T.... applies only for equally loaded BCl"MDE sdBCt ~ s~gnals.
4Tup applies only if the lq~ng ontbe BCl output is constim!-'over time.
'Only one transition is ..uowedroprietarY
-
VAXBI787.32
!o_~-
+5.0V
5-0.7 - Vol
101
DEVICE
UNDER
TEST
SCI 1/0 PIN
UNDER TEST
(SCI PUT)
Vah
M~i~
a.15K ohms =
loh
l~
BCI
Signal Change
81
S2
S3
o to 1
OPEN
CLOSED
CLOSED
OPEN
CLOSED
CLOSED
CLOSED
OPEN
CLOSED
CLOSED
CLOSED
CLOSED
CLOSED
CLOSED
OPEN
1 to 0
lto 0
Z to 1
Otolor1 tol
NOTE:
The SENTRY test fixture does not matclh this test configuration.
Figure 79· VAXBl 78732 Bel Bus Load Circuit
Confidential and Proprietary
4-133
• Features
• Supports VAXBI bus system features of low inter£acecost,1ess. than 80o-naoosecond data access
time, and high data integtity
• Supports the full range of datal.ines rieededfot aheffidentVAXBHnterface
• DMA master port allOws datatrans£er at
(un VAXBIspeeds
• Page overflow detection features
• Single 5-volt supply
. Descnption
The VAXB178143 BCI Adapter Int¢ace'BCAI) is,I1·ZMOScustlom int;egmtedcircuitthat
£unctions asa bU££er£ilebetweenuseThdesign~processors,memories; 41ldadapter modules and
Digital's high-performance VAXBI (VAX bus interconnect) bus. A block diagram of the BCAl is
shown in Figure 1.
BCI A<3:0>
IICLRlfB
IIM<3:O>
RC1MLS
iilITNAmS
Ilcl.elliu\Wl
II OMA PGOVF
lIel PO
ADDA LATCH
8CI1<3:0> .
IICI 0<;31:00>
1111<6:0>
Figure 1- VAKB178743 BCAIBlock Diagram
4-135
_
..
VAXBI1874}
The VAXBlbus is a 32-bit general purpose synchronous bus that can be eff~ively used in single or
multiprocessing systems based on VAX computers, other 32-bit processors, and compatible
devices. The VAXBI bus has a maximum length of 15 meters and can contain up to 16 intelligent
nodes on as many as 36 modules with an aggregate throughput of 13.3 Mbytes per second. The
BCAI supports the full range of data lines needed to fulfill an efficient VAXBI interface.
TheBCAr contains a dual-port register file and byte shifter that functions as a buffer file between
the VAXBI bus interconnec.t interface chip (BIlC) and a local adapter bus on a. VAXBI module.
Individual registers within the register file have been customized to support the following
functions:
• A VAXBl master port used for high bandwidth data ti'ansfers (DMA master port)
• A second master port used for lower bandwidth local processor access to the VAXBl (mapped
master port)
• A slave port used to transfer VAXBl transactions onto the local bus (slave port)
A typical VAXBl 78743 BCAl interface configuration is shown in Figure 2. The BCAlperforms
data-path operations and requires external control logic to fully implement a BCI adapter interface.
The data path and the registers of the DMA master port are designed to allow data transfer at full
VAXBl speeds.
LOCAL
MICRO
PROCESSOR
CONTROL
LINES
I-
BCIBUS
CONTROL
LINES
" BUS
INTERFACE
~
MEMORY
BIIC
BCI
CONTROL
lOGIC
-
II ADDRESS
AND CONTROL
DATA
I
VAXBI
i-- BUS
j.-ADDRESS
AND CONTROL
aCAI
l
Bel BUS
PATH
DATAl
INFORMATION
Figure 2· VAXBI 78743 Typical BCAl System Configuration
The BCI control logic interfaces with the BIlC and is used to generate the control signals and
addressing information on the BCI bus in realtime applications. It also decouples the local
processor bus interface for realtime aspects of VAXBI transactions. The processor interface loads
the BCAI interface registers as required, asserts a request signal, and is notified when the
transaction is complete. The data path for the processor interface can be 8-, 16-, or 32-bits wide
because of the byte alignment and masking capabilities of the BCAI.
The data/address and control information to and from the local processor is referred to as II
(Integrated circuit Interconnect) bus information. However, the signals from the BCAl may not be
compatible with every specific II implementation. The II bus address and control functions can be
implemented by a ROM-based microsequencer or by other logic interfaced to the microprocessor
bus.
4-136
Confidential and Proprietary
VAXBI '8'74)
The BCAI contains a dual-port register file consisting of 15 registers, each ofwhkhis 41-bitswide.
The file is aeeessed frorn the Ilbus interface as 2M2-bit registerS and from the Bel bus as 14 36-bit
registers: TheBCI bUs register infOrmation is transferred on 32 data lines and 4 information lines.
Associated with the II bus is a byte swapper and special address decOde logic that PernUts the user
to access one to four contiguous bytes starting from any byte boundary. The registers must be
accessed along longword boundaries from the BCI bus. The register file and byte swapper logic
includes severalad~. arid data lat~es. ~B8Interfac¢'~~tWo ou~t latches, one foro
the master port.al'ld'.one for the slaVe port. A parltjsectionis also aWllable and Checks parity in the
register file.
'
,
Figure 1 shows the functional blocks and the I/01inesp£ the BCAkrouro£ the BClhus control
lines (BC'iRS, BCIWS. BCI W, and.BtI SES) have enable lines that gate the informatiortfrom.
the primary line into the BCAI. This simplifies external controller design by allowing external clock
signals to generate the precise timing required .
• Pin and Signal Definitions
The VAXBI 78743 BCAl, contained in a 133-pin~,£unctions with.~inpqt tUld 'Output
signals and power and$1'OundCptiDectionS shown in Figt:tte 3~ The inputs ana outputs are described
in the following paragraphs,Thesignalsategt;ouped byJI bus~terfacesignals and BCI bus
interface signals.
1413 12 11 10 9
p
N
"".
•
M •
•
•
•
..
•
... -,~,'.
•
'"
•
•
•
•
a
7 6
5
4
3
2
•
•
J
~
• • • • • • M
H •
o
SCAI
G •
F
•
.E
•
..
o • ..
•
.~
c • ..
..
•
A
•
'.
•
•
14 13 12 11'10 9
..
•
•
. ..
• •
B •
P'
• N
l
K
1
8
7
•
L
•
•
K
.J
•
II
H
G
•
F
•
E
•
0
• c
•
S
•
..
..
..
•
•
A
6
5 '4
3
2
1
(TOP VIEW)
avs
R,EFER TO TABLE I,FOR II
INURF.I>,CI' SIGNt-LS.POW;!'ftAND GRO.UND
PIN ASSIGNMENTS,.,
" '.
,'.' '..
' .' "
REFER TO TABLE 4'FORBCI BUS INTERFACE SIGNAL PIN ASSIGNMEms. '
Figure]· VAXBI 78743 Pin Assignments
Confidential alld'PrQprietary
4-137
...
Preliminary·
ll-BQslntetface Sipals
Table. 1 is asumtnary of. the Il bus signals that connect the BCAl ~ the microprocessor bus
interface. The signal functions are described in the paragrapbsthat follow. Table 1 also includes the
power and ground connections to the chip.
Table 1· VAXBI 78743 n Bus Interface Pihand Signal Summary
Pin
Signal
Input/Output Definition/Function
M2,M4,M5,M6 IID<31:00>
N7,N9,N 10,MIO
MJ,P2,P4,N6,
N8,M9,PU,MU,
N2,P3,N5,P6,
P8,P10,Nll,N13,
N3,N4,P5,P7,
P9,Pll,P13,P14
input/output II Data <31:00>-Transfers data to and
from the processor bus interface.
N1,Ml,L2,K2.
input/output II Parity<3:0>-Parjty for each of the four
bytes on lines II D < 31:00 > .
np<3:O>
L13
input
II Data strobe-Loads the II D < 31:00 > line
information into the BCIA.
M14
HOE
input
II Output enable-Controls the data output
to the processor bus interface.
LlJ2,Kl,H3
IIM<3:0>
input
II Mask < 3:0> -Controls the ability to perform a II processor interface operation to
individual byte fields.
H1,Gl;Fl,G2,
F2Jl,H2
IIA<6:0>
input
II Address < 6:0 > -Controls the selection
of the internal registers in the register file.
El
II AS
input
II Address strobe-Loads the information on
the II A<6:0> and II M<3:0> lines into
the BCAI.
K13
IIWS
input
II Write strobe-Controls the write operation
of the internal register file.
Ll4
IIRS
input
II Read strobe-Controls the read operation
for the II interface {>Ort of the register file.
J12
IICLRVB
input
II Clear byte valid-Clears all master port
byte valid bits.
B1
IIPSEL
input
II Parity select-Selects the user supplied or
internally generated parity indication on the
BCl PO line during data output transfers to
the BIlC.
Confidential and Proprietary
VAXBI7874.l,'
Preliminary
Pin
,InPUt/Output
~on '
D12
input
II Parity bad-Indicates that the pGrityis not
valid during data transfers to and from the
BIlC.
II DMA POOVF output
J14
HDMApage overflow-Indicates that the
lOMA address register
is full.
,',
-"
J13
n MAP PGOFV
N14
II DMAfNc ENA input
M13
II MAP INCENA input
output
bMA
n'
incremem enable-Allows the mas·
terpdff DMA .addtesii' register "to beiDfire.
mented.
tf~p i~~llW~!ep~~le""7AJtows t~,lll~t )-Bidirectional data lines that connect to a transparent input latch. The
latch is controlled by the ~ signal. Thethree-state dri\Tei-Siire~nabledby the 'fI15E input.
n Parity (nP< 3:0> )-Paritybits associated with each of thc'fourbytes on the IID< 31:00:>
lines. Valid byte parity must be generated by the userandloadedirito theli3CAI Qn Hnes II P <3 :(i>
when transferring data, addresses, or command/mask/status inforril.ationdntothe.BCALWhen
loading 4·bit command/mask/status infor~tion"t4epari~yg~~~P1DU!it beJor the c0nlplete
byte, including the wus in the ~mple~ented ROrti()~ of the hYt ~£otn1lltionby~ shin~~d enabledbyIIa~sigrut1.
II Data Strobe (IiD$).....This signlll C0~S th¢tra~p~~t 4\tch~. for thi! II ,D
>', input
data. The input latch js transparent whe~ thetrnS input is as~rted and the inforrpatiOD is latched
' , ' ','
,'
, ,
when the signal is d~!!erte,d. '
<
,
"
-,'
,
,
"'.
~',
<:31:06
-
'
,
'
II Output ENlhle(II OE)-Colltro41;heo4tput drlvers.£Qr.tllc;I1 D>31:.oo.:;-atld~IP.-<~:O>
lines. When IIOE is asserted,the~on~ent$o£ the I~ D <31:00>' Qutput latthare,' transferred the
II D <31:QO>, ~ta bus. \1qhen it ,is deasserted, theJI,p <}1:0,0 > lines become ahigh.im~ce
state. Line ~I OE has a 50-vA pullup ~.ircuit. so that if the pin is DOt contlected, it will remain
to
deasserted.
'
II Mask (II M < 3:0 > )-ControIs the ability to perform an II operation to individual byte fidds.
When the selected n M <3:0> lines~' deisserted, anII bus Writeopehttion for the corresponding byte fiddis suppressed and an II read. operationremrnshli zeros including the ptttityBit; The
rrlllsk information is ial:chedbythe assertion ofthe iIAS'lirie.1able2liststhe lrbus interface mask
bit assignments.
Confidential andProprletary
4-U9
------_.
-
p.....t:_.:·......._.'. . .':' ",
.~II.U.tCJ,J;:1'.t<
Table2 • VAXBI78743U Bt!m Masldlit Assignments ,
n Mask lines·
Valid data
Valid parity
1
II D <.31:00 >
IIP<3:0>
0
1
IID<07:00>
lIPO
0
1
0
IID< 15:00>
lIPl
0
1
0
0
' nb<23:16>
IIP2
1
0
0
0
II D<31:24>
lIP3
.3
2
1
O.
1
1
1
0
0
0
*All,other iQput combinations that specify the validity of the bytes on the II D<31:00> lines are
allowed.
D Address (DA< 6:0 > >__Conttols the selection of the internal registers inthe register file. Referto
Fi.gllre 4 for the hexadecimal address values assigned to the registers.
II A < 6:2 > signals pass
through'a transparent latch cantiolled by 'ii"AS inputand may be used in a latched or unlatched mode.
Lines II A < 6:2 > are. used to select. the primary longword register being accessed and lines
II A < 1:0 > control the byte offset multiplexers attached to the internal registers as listed in Table.3.
The
Table 3 ·VAXBI 78743 Byte Offset
Byte offset
DAline·
1
0
L
L
none
L
H
1
H
L
.2
H
H
3
*H == high level,. L := low level;
For registers within the dual octaword buffer, the bytes that extend beyond the primary longword
register are contained in the next adjacent register (A<6:2>+1) except ,whenl! A
< 6:2> ",,00111. When the exception exists, the primary longword register is at the bottotn of the
buffer andthe offset is transferred tothelongword register'addressed by 00000. For regis~rshoi in
the dual octaword buffer, the bytes that are offset beyond the primary longword register are not
written during write operations and are returned as all zeros on read oPerations.
nAddress' Strobe(D AS)-Controls the transparent latCh for the II A<6:0 > data and mask bits
lIM < 3:0 >. The input latch is transparent when II AS is asserted and latched when de asserted:.
D Write Strobe(fl WS )-Controls the writing ofthe internal register file: The input data from the
'transparent latches on lines II D < 31:00> is loaded into the selected register during assertion of
the ifWR strobe. the deassertion of the selected II M< .3: 0 > lines. wilI,'inhibit the wrlte operation
for the cOrresponding byte field. When acce:::sing the DMA octaword data buffers, th~ byte valid bit
for the addressed location is set when its byte is written.
D ~S4'Obe~D ~)..,....Controls the readoperatiolls.£or the I~ bus port of the register file,J'he
.~doperatkln isinitjate~ when the 1I.RS line .is.~tep.l\t\~ the restIlting o~tPtltdata. is helP: ~. the
II D < 31:00> outpudatch when theIl RSsigl)al is de~~erteq.Dea$s~rtionof the selected,lI
M < 3:0 > lines will inhibit the read operation for the correspondingbyte field.
.
Confidential and Proprietaty
Preliminary
Ii Clear Valid Byte (ll CLRVB)-This sign!ll is ~¢d .~. ~l~ all the master port Byte Valid bits
associated with the dualoctaword buffer.·
.
.. .
n Parity settet '(It I-SBL)..;...Seiects which source of parity· (user supplied orintetnally generated) is
passed toBCr PO otitput when data is transferred to the BIIC. A low level selects user parity and
makes the errors within the processor bus interface or the BCAI visible to the VAXBI bus. A high
level selects the internal parity. that ahvaysprovides corre<;t .parity for the ~ being passed to the
BCI bus. This signal is latched by the BCI AS line.
n Parity Bad (ll PBAD)-When set,!t indiClates one of two conditions:
• WhentnnlSmitting data to the BIle; the result of the internal parity generation from theBCI
D<31:00> and BCII<3:0>lbles·£otthis cycle do not agree with the parity bits associated
with the. 5 bytes beingtransmitte<:l.
• When receiving data from the BIIC,theBCI PO line from the BIlC does not agree with the
internal parity generated from the 5 bytes being received on the BCI D<31:00> and BCI
1<3:0> lines.
n DMA Page Overflow (ll'fiMA PGbVif)i.,;..Asserted to indicate that the DMA address register has
reached theOO\lIldary oia ?12~~pl(!ge.
.
n MAP Page Overflow (D MAPPG(l)FV)~Asserted to indicate that the MAP address register has
reached the boundary of a 512-byte page.
n DMA Increment Enable
.input/output BCI Data < 31:00 > - Data lines that transfer
B2,A2,C5,B3,
data between the BCIA and the BIle interface.
A3,B4,A4,B5,
A5,C6,B6,A6,
A7,B7,B8,A8,
A9 ,B9 ;A10,All,
C9,B10,A12,Bll,
A13,B12,Cl1,B13
E14,F13,D14,
F12
BCII<3:0>
input/Olltput BCI Information < 3:0>-Infprmation lines
used to transfer command, mask, and status
information between the BCAl and BIlC
interface.
Confidential and Proprietary
4·141
_i
Preliminary .
VAXBI'11814l,
'.<.
Pili'
Signal
tnputfOu~t
E13
BClPO
input/output BCI Parity-A p~ity indicator from the BIlC
when data .isreceived and to the BIIC when
data is transferred to the the Bile.
.
F14
Defil1itioiif.Etuncticm
,
-~
"-, ;
"
','. "
input
BCI Data strobe-Loads the information on
the Bel D<31:00> and BCI 1<3:0> lines
into the BCAL
Dl,E3,Cl,D2
BCIA<3:0>
input
BCI Address-,-Controls the selection of the
internal registers in the register file.
E2
BCIAS
input
BCI Address strobe-Controls. the loading of
the A<3:0> input information' from' the
BIlG.
Hl2
BCIWS
input
BCI Write strobe-Controls the writing or
from the BIlCtothe register file.
H13
BCIENAWS
input
BCI Enable write strobe-Enables the BCiWS
input to the BCAL
H14
BCIRS
input
BCI Read strobe-Controls the read opera.
tion of thel~gisier file from the BIle.
G14
BCIENARS
input
BCI Enable read strobe~Enables the operation of the BCI RS signal from the BIIC.
BCIENAMLS
input
BCIEnable A master latch strobe-Enables
the operation of the BCI RS signal input from
theBIIC.
B14
BCIENBMLS
input
BCI Enable B master latch strobe-Enables
the operation of the BCI RS signal input from
theBIlC.
E12
BCIMLS
input
BCI Master latch strobe-Controls the operation of the transparent output register.
C14
BCISLS
input
BCI Slave latch strobe"-Controls the transfer
. of information on the BCI D < 3hOO > and
BCI 1< 3:0> lines to the Bne.
D13
BCIENASLS
input
BCI Enable slave latch strobe-Enables the
operation of the BCI SLS input from the BnC.
GU
BCIMDE
input
BCI Master data enable-Controls the slave
output data from the BCAI to the BlIe;
Gn
BCISDE
input
BCl Slave data enable-Controls the transfer
of the $lave data from the BCAI to the BHC.
cn
4-142
I
Confidential and Proprietary
-.
VAXB173743
BClData .(RCI D )-BidirectionaI data lines with·Q transparentmputlatch and tWo
output latches. ~. input latch is controlled by .the·Bcr'DS line.The.~fllitters .fpJ: . .tbe,Qutput
latches are-~ntrolledby BCI MDE. for the master data output latch atl.d by1:heBCI St>£ input fpr
the slave data output latch.
."
'.
.
BCl Informatiou.{IICI I lines ..
BCI Parity (BCl po).....This bidire~ionalline.~ei~stheP~!Y:~~~C;>l1.Wl).~~~ngdata
fromtheBI~C andit is,compared to
paritr.from (he in~hiU~ty~¥t.1nternal,~ityis
generated when the BCI D < 31:0(».and.~Cl I.e: 3,:0> Unes •• r~hed. Wbentrans~tiog qata,
this line supplies user parity or internal p~rlty, as'selected by
II PSEL. If intern~tp~jty ~J1Pt
agree with externally.supplied parity in either directiofl' th~ IT ~bJine is' ~serted. The ~
information is latched and enabled the samesStJie;~cr O<31:00>lil:les.'
.
the
line
BClD~Sttobe(BCIpS)~Con~1~th,~~p~~tU];put~tch{9fB<1~D.,%31:QO>, BClt<3:0>,
and BCIPO fuput data. The input latch is transpattmt when
is latched when it is deasserted.
mm is asserted and the information
.
f
•
The
BeI Address (BCI A < }:o > )-Controls the selection of the jr:ternlllr¢g~t~ f*,~is~et~.,
BCI A < 3:0> lines transfer through a transparent latch controlled by the ~sighaI and may be
used in a latched or unlatched mode.
BO Address Strobe (8OAS)-Con~ls thetrahsparentlatchforBCI A <: 3iO> input data andfor
n PSELinput:The latch is transparent whetl' BelAS isasseitedatid the fufor.illlition is latched
when it is deasserted.
.
.
BCI Write Strobe (Bel WS)-Controls BCI bus write operations to the internal register file. The
input data BCl D< 31:00> from the input latch is loaded into the selected BCAI register during
assertion of this signal.
BCI Enable Wri1e Strobe (BCI ENA WS)-Gates the BCI WS level into the BCAL
BCI Read Strobe (BCI RS)-Controls BCI bus read operations of the internal register file. The
operation is initiated when 'BtTRS is asserted and the resulting data is held in an internal register
upon the deassertion of BCI RS. The byte valid bits for the addressed register are reset when a byte
within the DMA data buffer is read. The BCI ENA RS signal must be asserted or this line will be
disabled.
BCI Enable Read Strobe (BCI ENA RS)-Gates the IiC'i1tS signal into the BCAI.
BCI Master Latch Strobe (BCI MLS)-Controls the transparent output registerfor BCI D < 31:00 >
and BCI I < 3:0> master output data. The latch is transparent when Bcl MSL is asserted and the
information is latched when it is deasserted. Either the BCI ENA MSL or BCI ENB MLS signal
must be asserted or this line will be disabled.
Confidential "nd Proprietary
•••
VAXUI78743
BCI Enable A Master Latch Strobe (BCI ENA MLS)....,.Gates the BCI MLS signal into the BCAI.
BC1EnableB Master Latch (BCI END MLS) .....Satnefunction as theBCI MLS signal.
BCISlaveLatch Strobe (SCI SLs>-Controls the transparent output latch for BCI D<31:00>
and BCI 1< .3:0> slave output data. The latch is transparent when the BCI SLS is asserted and the
. information is latched when it is deasserted.· The BCI ENA SLS signal must be asserted or this line
is disabled.
BCI Enable Slave Latch Strobe (BCI ENA SLS)-Gates the BCI SLS signal into the BCAL
BCI Maillet Data Enable (BCI MOE)-Controls the transfer of the data in the master output latch
to the BCIn < 31:00 > and BcII < 3:0> lines. This signal has an internal 50 !lA pullup device so
that the BCI D<31:00> and BCI 1<3:0> lines remain a high impedance when theBCI MDE
input is not connected.
BCI Slave Data Enable (BCI SDE)-Controls the transfer of the data in the slave outpu~ latch to
the BCI D < 31:00> and BCI I < 3:0 > lines . This signal has an internal 50 !lA pullup device so that
the BCI D < 31:00 > and BCI 1< 3:0> lines remain a high impedance when the BCI SDE input is
not connected .
• General Regis1:e1' Addressing
Figures 5 shows the memory map configuration and information of the BCAl registers. when
accessed by the BCI. bus interface. Figure 6 show register memory map configuration and
information of the BCAI registers accessed from the BCI bus interface. The hexadecimal address'
assignments and read/write capablities of each register are listed in the figures.
4·144
Confidential and Proprietary
_?
IIA<6:O>
Preliminary
I
o
II 0<31:00>
1615
23
31
I I 111.1
I I 1'1.' It"
00
I I
1"1'1 I I I I I I "
MASTER PORT A DMA DATA
I
I
4
I
0807
..
R/W
0, " .
'.
I
I
, MASTER POR'- A OMAOA'-A 1
8
RIW
..I,
I
I
MASTER PORT A OMA DATA 2
RIW
I
I
I
MASTER PORT A DMA,OJ\TA 3
C
I
10
RIW
..
I
I
MASTER·PORT 8 DMADATA 0
RIW
DATA
WRAP AROUND
I
14
MASTERPORTBOMADATA f
R/W
I
I
18
I
MASTER PORT BOMA DATA 2
RIW
,
cl
I
MASTER PORT 8 OMA DATA 3
lC
I
R/W
.l.
,
I
20
MASTER PORT OMA ADDRES§
.'
I I
I
24
. I
.
OCMO
...
RIW
I'"
I
MASTER PORT MAP DATA
.;. "
I
I
2C
I
.
I
28
R/W
.<
'f
RIW
L
J
.1
'1
M..:sK
RiW
ISTATU.S
I
.. 1
30
RiW
MASTER PORT.JA~PAOPRESS
I
I.
34
.
..I
t 1
.'
,
RIW
'.1
NEXT PAGE REGISTER
I
. 3C
1
MCMO
1
38
.1
.1 ZER~S
ZEROS
,....
J
.
RIW
I
..1.
I
40
.
R/W
SLAVE POR'- DATA 1
I
I I
I
44
MASK
I
I
RiW
STATU.S(SPO 1)
'\
48
,
..1
'.,'
f·
1
R/W
SLAVE PORT DATA 2
I I
I
I
4C
MASK
I
..1
I
J
I.
SLPivi:PORt ADDRESs'
50
I
I I'
SCM"
I
58
I
I I
I I I
I I I I III
R= READ ONLY
RIW= REAOIWRITE
I
I
"
54
. .c . •
RIW
STATUS(SPO 2)
I
ZEROS
I II I
I
I
I I
....
-
R
I
I
"
Figure 4· VAXBI 78743 II Bus Intet/ace Register Memory Map
-ConfidentiaIarid Proprietary
4-145
VAXIl''!;8743::
BCI A<3:0>
I
:BCI 0<31:00>
31
1615
I
1 1 1 'I
o
I I
I
1 I
I I
II II I I I I I 1[[
MASTER PORT DMA DATA 0
I
f
r
I
00
II I
I
MASTER PORT A DMA DATA 2
I
A/W
I
I
I
A/W
I
[
MASTER PORT A DMA DATA 3
I
I
4
R/W
I
I
MASTER PORT B DMA DATA 0
I
1
I
[
5
1
R/W
I
MASTER PORT ~ DMA DATA 1
A/W
I
I
I
6
')
I
MASTER PORT ~ DMADATA 2
7
I
I
8
1
MASTER PORT BOMA DATA 3
I
1
MASTER PORT DMA ADDRESS
I
I
T
I
1
MASTER PORT MAP DATA
I
I
MASTER PORT ~AP ADDRESS
I
I
1
I
B
SLAVE
r
PO~T DATA 1
I
I
I
I
SLAVE PORT DATA 2
I
I
I
I
C
ZE~OS
E
I
1 I
I
I
I I
R
R
A
A/W
R
II
I I
ZE~OS
A
DCMD
A
R/w
MASK
A/W
R
MeMO
R
R/W
MASK
A/W
A/W
MASK
AIW
RIW
SCMD
R/W
A
O's
R
R
O's
R
I
I
I
I
R
R/w
I
r
F
I
A
I
SLAVE POIRT ADDRESS
I
I
I
B
I
T
S
I
I
I
I
o
V
A
L
I
D
R
1
I
T
A
B
Y
T
E
I
I
I
9
A
I
I
1
r
r
1
I
3
I
R/W
MASTER PORT A DMA DATA 1
I,
I
2
BCII<3:0>
I
0807
I
I
J
I
I
I
I I I
R=READ ONLY
R/W= READ OR WRITE
Figure 5 • VAXBI 78743 Bcr Bus Intet/ace Read Transaction Timing
The registers within the file are grouped according to their supPorting function. SuPPort for the
DMA port consists of a twooctaword DMA transaction buffer, a command/address register with
increment capability, and a next page frame (NPF) registet: Support for the mapped master port
consists of a com.m.il.nd/address register with increment capability and a· single longword data
register with a mask/status register. Support for the slave port consists of a command/address
register and two longword data registers, each with a mask/status register. Amore detailed
functional description of the registers is described.
. 4-146
Confidential and Proprietary
-,
PreJiminary'
Master !:'ort,&Ptet:s.
The master port Q£.~~ B.CAI is ~for II bus-jpitiated ttansfersto the VAXBI bus. The BCAI
provickst:egi~~ifprt'lllPma$t~ PSlr~s",:",,"a high.speedDMA master port tha~ is optimi2ed forb~k
~~·.and al9ap,l;ll~tel' port. This allows a local processor to periorm longwordaq:esses to the
VAXBI~in the.m1~e 9£. ab~kDMA trans.ction. without~ng the sta~:of thf! previq~
traPsaction to be ~ Themaln difference between the twotoasrerports ijS thesizeo£ their da~a
buffers. The DMA master port has two octaword buffers and"thell',lapmaster .porthasa single
longwqtd data n:gistF. Both llla~terROrts have~c9mmanPf~'~1l!~is~~thautoinqeme~t
cap~ility and.page-croSs detectiOD.t!le
rnasterport inclqdeS nt':rl page frame~ster that
holds the tpapfor :the ~t page.
".
:
" , " " ' ,'
l)¥A
a
:MasfFtr~ 4anc1~ l)MA Data~Tpe DMA data bW:fel-g;>nsi~;s Qlei,gPtcon~iguously
·a~!9ngw<>rds.of read/write ~mory org~d.~tw()iOCt11~tPbuffer~,4 and B. These
buf,f~flllDW QtIe,transactjonbU££ep to l)(::acc¢~sedhyan IIb~~a¢on\lf~ the other is
~ed bya master V~lbus~saction" 'fo s1.tpport all.pos~blc,~~ss alignments, the :SCAI
byte multiplexer directs an II ~us transfer tp ~ .£OUfsequentj.a1~~ .inthe t~ctiQjll buffers.
An overflow that
when reading or writinsfrom either octawg,rd i~ aut0lllatically directed to
the first bytes. of t~.other Qctaword.: The;ef?re. the.f~# lo~rd of anumuttmaUy aligned
octaword transaction can extend into the fifsti:hree.bytes qf theOth~ octawQtd. . . . .
occurs
EachDMA c~r~4iAg~aU4btt~'A io~.: Illldfcates that the
byte is valid. All valid bits ~. cleare4;wh~ the ij CJ.RVB~is~.rted or ;W~1). anlJ bus read
operati~n is Performed"with an address of1F (hexadecimal). When a write ope~tion £roPlth~n
bus to a byte location within the DMA data buffet is performed,. the correspondin,g valid ,bit .f9r
thatlocation is set. Whendata is.read 1:ly .theBClb\1s, thev$.d bits are suppl1edtothe Bel
1<: 3:0> lines and can be u~ to support the YAXSl b~s ma~ked write colllll1ands'.' Typidilly a user
would clear the valid bits, load a portion of an octaword into the DMA data btiffer. arid then initiate
a VAXBI writemaskttaIlsfet.
. .
Master Po~ M8}? Data.~~-1pis, re8i!lter.~~re~the. data to, be read anlwrittell for map
master port transactions. The maskfs~tus ;e&ister~ssociated,~tllthe ~~ ~ster is separately
accessed from the II bus by bits 19:16' '0£ the address imm~tely followitigthe data register
address. When the data l:egisterisaccessedby the Bel bus, the.tnask!statusregi'sterttans£ersthe
information on the DCI 1< 3:0 > lines.
.
~PprtCOnt~Address~j~~the ~ster port.Q~ adc,iress re!#ster artdthe m~ster
port map address re~ster are u~ed to &de tbe VA~1c\~,a&,he~t9r~l1ecom~an;dlad~ss.cycle of
a VAXBI master porttran~act~on. If
Il.IjW~.~N:Ao,nI,~JI\l<:itmlille~ ~asserted
when the. corresponding adcIre.ss. register: i.~ rea~; fromtl1e SC;ll?u5, the,low-order 9. bit~of ~t
address are incremented by the size of the transaction as indicated by the length field {bits 3PO)of
the address register. This increment feature enhances block DMA transfers because 'the user is not
required to reload the address for every VAXBI bus transaction during sesuent~al transfers. Parity
for the two hytesaffectedby thein~;rement is ~utomat;icalh' reclY~ted.,·.·
.
.
fhe.
The access time of the address registers is SlUlle as the other reg;;sters. However. a minimum of 500
ns must be allowed between tWoBCI read operations to the address register with the'increment
feature.enabled. If this. time is not allowed;· the present address will be read correctly, but the next
reael:operation will resultdnanincorrect ,address.. The INCENA:signal. that h essentially the, carry
input to thelO\VeSt bitOfthe mcrementer·must also be asserted 500 nsbefore a Bel:read 0peration
of the .associated address register.
Confidential and Proprietary
4-147
...
Prelimimlry"
The master port DMA command and master.port map command registers a.teusaHoJ?rovidethe
VAXBI command for the command/address cycleofa VAXBltnaster port transaction: Frorrtthell
bus, the command register is located in the IbngWordimmediittely above the address register and
the commmand information is contained in bits 19: 16 of this regtstet. For the Btbus, thecorl1rl1and
and address registers are at the same location. When the command/address register is read fromthe
Bel bus, the cdmmand data is transferred ornhe Bel 1< 3:0> lines arid the address data is
.
trimsferredon the Bel D <31:00 > lines.
Next Page Frame :Register-The DMA master port has a Next Page Frame (NP.F} registetiliat can
be preloaded with the upper address bits for the page following the current page. \Vhen the DMA
address register reaches a page boundary and the II DMPGOVF signal is asserted, bits 31:09 of this
register are autofuaticallytransferred to the DMA itddress re~ster hits 31:09:. This feature can
increase throughput during block DMA transactions. Instead of halting whilewiiting 'fora new
map, VAXBI transactions can continue fotas long as a page while the adapter controllerfetches'and
loads the next map. If an update of the NPF register occurS Concurrent with the second'page
crossing, the value loaded into the DMA address register is unpredictable.
'
The low-order 9 bits of the D&iA address are notloaded from the NPF rc;;gisteJ; s()theT.II'"'In::t;MAr':' -:-·.
PGOVF signal remains asserted Until the next address increment or until an II buswrite tran~action
occurs to the DMA address register or the NPF register. When loading the NPF register from the II
bus, the loW-order 9lSits are not stored. Therefore, parity for the second byte (II D < 15 :08 > ) must
he calculated as if the II D08 bit was zero. The NPF register cannot be directly accessed by the Bel
interface.
S1ave Port Registers
The BCAI provides a commmand/address register and two longword data registers with associated
. . .
.
mask/status registers for the slave port.
Slave Port Data Registers 1 and 2-S1ave port data register 1 and slaye port data 2 registers are
read/write registers used for slave read transactions and for slave write translj.ctions. These registers.
allow a read response code to be written into the the slave read data status register from a II bus
device having torew'nte itfollowinga slave write transaction.
....
SLwePort Co:tDtl)atl(l/Address Register~The slave port command/addn::ss registers are used to
store the command and address data for the command/address cycle of a VAXBI bus master port
transaction. From the II bus, the registers are addressed separately with the command register
located in the Iongword immediately above the address register. The command information is
located in bits 19:16 of this register. From the VAXBl b\ls, the command imd address registers reside
in the same location. When the command/address register is written from the Bel interface, the
command data is loaded £rom the Bel 1<3:0> lines and the address data is loaded from the Bel
D<31:00> Hlines.
Page Boundary Detection
VAX processor memory management functions require that memory addresses are mapped from
virtual to physical space on a per page basis. To facilitate the mapping process, the SCAl provides
the II DMA PGOVF signal for theDMA master port and the II AP PGOVF signal for the map master
port. These signals indicate to the processor that an address register hasinctemented beyond a page
boundary. Anag bit in each address register indicates that a catty signahvasproduced when an
addressinctement occurred. During a BCI read operation,the nDMA PGOVF and IT MAP PGOVF
signals are updated with the contents of the respective carry signals when the BCI RSsignal is
asserted. Therefore, when a BCI read operation of an address register causes the address to
increment from all ones to all zeros, the overflow bit for that register will be a.sserted. The
4-148
Confidential and Proprietary
VAXlJl18743
subsequent read and increment operation will deassert the PGOVFL bit. The II M}1~m<1VF bit is
also deasserted by II bus write operation to the map address register. The II DMA PGOVF bit is
deassertedby an nbus write operation to either theDMA addlessregister 01' to thenextpagefrrune
register. If.a·BCI interface read operation results in a page crossing at the Sttme time an R bus write
operation accurst<> one of the registers that affect that II PGOVF'qit, thestate<;i£ thiIlPGOVF bit
is unpredictable .
• Parity Data Path
All parity gene~d or checked by the BCAI isoddparity, A paritybit is associated with ~byte
of data in the BCAI register file, including bytes that conunncommand, mask, or stl1:tushits. For
the 4-bit command, mask, or status information, the parity is calculated and supplied based on the
complete byte that includes the four zeros above the register. B~e parity is sup~lied.l>y the l.l~r on
the II P< 3:0 > during II bus read operations. Nonexistent hyteS;tldudiilgupper bytes\cifs!ii[ted
read to nonwraparound registers and registet:lith~t. are. de£ined as zero.~ ~ as all zeros. The
parity bits are read as ones. Ther,efoJ;e nonex4t~ byte~ have gooc:lp~ity.
During master-write or slave-read transactions that result in data transfers from the BCAI t() the
BIlC, the BCAI compares the~parity bitsfromthe user after the byte parity and data have been
transferred through the BCAI, with the· results()t its ownintel1l111 parity generator that operates on
theBCI D < 31:00 > and BCI I < 3:0 > lines of thetegisterfile, lhhe parity bits do not Sgree,the
n PBAD line is asserted. The II PSEL line selects w~()£ the twosourcesofp~ityis~sed,to the
BCI PO line. If the II PSEL line is alow level, the user supplied paritylsgivento the~IlC interface.
Therefore if an error has occurred in the BCA! or in the II bus interW:e, the bad parity is passed to
the VAXBI bus where it will stop the memory write operation and the transaction. If user parity is
not required, the II PSEL line can be connected to 11 high level and the parity Will match the data
transferred to the BIlC regardless of the previolls paritY conditlCttlS;
During master read and slave write transat;tionsthat transfer data from the BIlC to theBCAl, the
BCAl generates parity based on the incoming BcI D < 31:00 ::>andllCI 1< ):0> line information
and compares the result with the BCI PO line from the BIIC. If parity is different, the II pBAb line
is asserted. An internal parity generator also determines the parity for each byte of data that is then
transferred through the BCAI to the II bus interface. The byte parity is read on the II P< 3:0>
lines when the register file is read.
The state of the II PSEL line is latched by the assertion of 'OCT'AS signal. The II PBAD signal is
automatically deasserted when the BCf"RS or Bet WS signal is asserted and is updated when the
BCI RS or BCI WS signal is deasserted .
. Initianzation
All the valid bits of the BCAl are cleared by the assertion of the II CLRVB signal or by an II bus read
operation with lines II A < 6:0> = 1111111. The II bus read operation enables the microprocessor to
perform the initialization without the use of external logic. Other states within the BCAI are
undefined during the powerup sequence.
If a write mask is the first DMA master-port transaction to follow the powerup sequence, the valid
bits may have been cleared by the IT CLRVB signal but the data bytes and parity bits that are not
loaded will be undefined. The mask bits for those bytes will be zero and the BCAI and the VAXBI
interface will still be checking their parity. To prevent erroneous parity, the correct parity should be
entered by the user, the II CRLVB line asserted, and the transaction started at a known state.
C()na~ntial and Proprietary
4-149
-
• Spect6catipns
The. mechanical, electrical. and environmental. specifications . for .the . VAXBl interface are· as
follows. rhetest conditions for the values specified areas follows unless specified otherwise.
io
Junction temperature (TJ): ooe to 125°C
• Supply voltage (Vee): 4.75 V to 5.25 V
Mechankal Configuration
The mechanical dimensions for mounting the 133-pin VAXBI interface package are shown .in
AppendixE:
··AbsOlute Maximum Ratings
Stresses greater than the absolute maximum· ratings may' cause permanent damage to a device.
Exposure to the absolute maximum tatingconditions for extended periods may adversely affect
the reliability of the dc;vice.
• Pin voltages: -1.5 V to 7.0 V
• Operating junction temperature range (TJ):
ooe to U5°e.
'. Storage temperature range: -55°e to U5°C·
• Package dissipation: 3.0 watts
Recommended Operating Conditions
• Supply voltage {Ved: 4.75 V to 5.25 V
·4-150
Confidential and Proprietary
de Electrical ~tics
Table )contail1S,the~dectrical parameters for the input and outputs of the BeAl :interfacecbip.
Symbol
Parameter
VIR
High-level
input voltage
Va
2.0
. Low-level
-1.0.
V
0.8
V
input voltage
Von
High-level
output voltage
VOL
Low-level
output voltage
Iou
High-level
output current
IOL
Low-level
output current
II
Input currentl
lILA
Input Cul1'ent
open latch!
los
Output current .
shortd.rcuitl
loB
Enableline
current
Inn
Power supply
current
VaB
Substrate bias
voltage
CIO
2;7
V
0.5
V
A
hiA
4.0
BCUI'lDE.BtisOE,
ii'"lrn' inputs
Generated
internally
Input/p!l~lWt .
50
-3.6
±20
25
i1A
M..
-150
rnA
200.
~
500
rnA
-2.4
V
10
pF
capacitance
Applies to ~he f~g three-state bidirectional signals: BCI D < 31:00).., BCII
<: 3:0 > , BCI Pci,
IID<31:00>. andIIP<3:0>;
IILA applies when the following inputs are opeDancl Ii when Closoo: BCI A<:3:0;:'" , II M<3:0>,
1
II A < 6:0 > , and II PSEL.
. ..
... .
'. '.
2Not more than one output must be short circuited at a time and the duration of the short must not
exceed 1 second.
.
.
Confidential andProprietaty
4-151
-
...
ac Electrical Characteristics
Figure 6 shows the'signal timing for a lead transaction from the BCI bus interface and Table 6 lists
the timing parameters. Figure 7 shows the signal timing for a write transaction from the BCI bus
interface and Table 7 lists the timing parameters. Figure 8 shows the signal timing for an address
increment and Table 8 lists the timing parameters. The signal timing for a II bus interface read
transactio:n is shown in Fig\lre 9 andthe timing panuneter~ are listed in Table 9. Table 10 lists, the
timing parameters for a II bus interf~ce write transaction shown in Figure 10.
~tBS1~)l---tBH1...jtBAH1=4
BCIA<3:0>
_ _ _ _ _- - -
--tt
BASw
7
\.
/
--j1!='BASH'
lE=~
~tBSR
______________---I:-~
------
-ir-tBPCH
--t. . .------~
tBRll1L__
tL_H____________________
BCISLS
BCIMlS
I.. \..
tBMLSW.J
I tBAon
---~Ul
~tB~
BCI 0<31;00>
BCII<3:0>
BCIPO
LO
(
I
I- tBoo "j,...
-eo!
____
--I \ - - - - - - - !--tPEO
Figure 6· VAXBl 78743 Bel Bus Inter/ace Read Transaction Timing.
Thble 6 • VAXBI 78743 BCI Bus Interface Read Timing Parameters
Symbol
Requirements (ns)
Definition
Min.
tUI
BCIA<3:0>.to BCIAS setup time
15
t BUl
BCIA<3;0> to~holdtime
10
t BASW
BCI address latch strobe width
15
t IlAS!1
BCI AS to BCI RS setup time
45
t BAS '
BCI A < :;:0> to i3Ci"RS setup time
45
4-152
Confidential and Proprietary
Max.
~ments(ns)
~.
~ from BCIl{S hold time
tllASHl
"
M~.
15
tBAHl
Read strobe width
tan
tBPCH
100
Read access time
110
t BMLSW
BCI Mis, BCI SLSstrobe hold time
BCI output enable time
BCI QUtput disable time
taon
. parity
error output delay
60
BCIA<3:0>
Bel 0<31:00>
Bel 1<3:0>
BCIPO
IIRS
---..;.-----.:...-.....\
/
Figure 7· VAXJ3178743 BCl Bus Interface Write TranSllCtion Timing
4-153
-
Table' . VAXBI 78743 BCI Bus Interface Write Timing .~
Symbol
Definition
Requirements (ns)
Min. .
t B51
Bel A < 3:0> to Bel As setup time
15
tllHl
Bel A< 3:0 > to BCTAS hold time
10
t BASW
Bel address latch strobe width
15
t BASs2
Bel AS to Bel WS
45
t BAS2
Bel A < 3:0 > to Bel WS setup time
45
tllAH2
Bel A < 3:0 > from Bel WS hold time
15
t BASH2
Bel AS from Bel RS hold time
15
tBDSI
Bel DS to Bel WS setup time
0
tllll»
Bel D < 31:00 > to Bel WS setup time
0
tllSw
Write strobe width
90
t BPCH
Preset width (BCiRS' and Bel WS unasserted)
40
t Bnsw
Bel data strobe pulse width
15
t BS2
Bel data strobe setup time
15
t8H2
Bel data strobe hold time
10
tPJ!D
Parity error output delay
tlllD
Bel WS deasserts to II read (same register)
60
0
11"<6:0>
II M<3:0>
II 0<31:00>
II P<3:0>
Figure 8· VAXBI 7874) II Bus Inter/ace Read Transaction Timing
Confidential and Proprietary
Max.
~menU(m)
Symhol
Min.
II A< 3:0 > to II AS setup time
Max.
15
II A < 3:0 > to II AS hold time
t lAS...
II address latch strobe time
tlASlt
'if:i\S.to II lis setup time
t lAS1
II A <:: 3:0> to II lis setup time
t lAR •
II A< 3:0 > to II RS hold time
tlASHI
'ifXSfrom IfRS hold time
tlSK
Read strobe width
. Preset width (iTRS and lfW'S unasserted)
tIPeR
Read access time
90
tlOE
II output enable time
t Ion
II output disable time
40
40
IIA<3:0>
, liAS
II 0<31:00>
II,P<3:0>
Figure 9- VAXBI 7874311 Bus lnteiface Write Tmnsaction
('Anfidential and Proprietary
4-155
-.
Symbol
Preliminary
.Definition
Requirement$ .(ns)
Min.
n A< 3:0 > to II AS setup time
II A < 3:0> to 'fiA'S hold time
15
t lASW
II address latch strobe time
15
t IASS1
II AS to ~ setup time
60
Max.
10
IIA<3:0> to IIWS setup time
15
IIA<3:0> to IIWS hold time
t'ASH2
II AS from II RS hold time
II DS to II WS setup time
o
IID<31:00> toIIWS
Write strobe width
tlH:l
Preset width (II RS and II WS unasserted)
40
II data strobe width
15
II D < 31:00 > and II P < 3:0 > to II DS setup time
15
II D < 31:00 > and II P < 3:0 > from II DS hold time
10
BCI 0< 31:0"
(DMAIMAP ADDRESS ACCESS)
----------4(
)'
r
tBRD
'\ . . ' ,,.....'. . ...-..
-~\
II DMAINCENA
II MAPINCENA
IIDMAPGOVF
II MAPPGOVF
(INCREMENTED
~
." I
'CI:BS~.tAIHI:.~.
__ ___._____
------~~I.
}~
1-l.-tPO~·
~tDPD
----"----
,.
\
/;::tMIN
\'----11
~
~_I
,;-'""""---
' .
--.j.
I
Figure 10· VAXBl 78743 Bel DMA and MAP Address Increment Timing
4·156
Confidential and Proprietary
-
VAXBI78743
Table 10· VAXBI 78743 DMA and MAP Address Increment Timing Parameters
Symbol
Definition
tBSIt
Read strobe width
t BJID
Read access time
troD
Page overflow dday from BCi'1fS asserted
tillS
tillH
tAIINt
t!olJN2
t DrD
Requirements (ns)
Min.
Max.
90
110
II DMA INC ENA or II MAP INc ENA setup to
to BCl RS deassertion.
0
500
II DMA INC ENA or II MAP INC ENA hold time
from to BCI RS deassertion.
10
Minimum time between BCI reads with increment
500
Minimum time between II writes and BCI reads
with increment
500
Page overflow dday from II DMA INC ENA and
II MAP INC ENA
520
Confidential and Proprietary
70
4-157
• Operates as a memory-rruippedperip~ totlie MictoVAX CPU chip.
• Responds to VA;xBI~~+ns~~sued by ot~ VAn~~ ij:tatl1!icess ~ mem~ry~r
seek to interrupt the BCI3's MkroVAXCPU.
..
.
.
• Automatically ttanslates any. Integrated Circuit Interconnect (II) bus transaction into the
equivalent VAXBI transaction whenever the II bus transactions references a nonlocal resource.
,.: ~
,',
"
-
_
- -
"
• Fast transfer of data blocks between local memory and VAXBf memory at therecluest:ofrhe
MkroVAx CPU.
• Description
The VAXBI 78733 bus interface adapter (BCD), contained in a I32-pin ceramic pin grid array
(PGA) package, is used to connect tb~I~ Circuit Interconnect (II) bus of the MicroVAX
78032 processor to the VAXBI bus through the VAnI 78732 Bus Interface Interconnect (BIlC)
chip. The BCI3 is responsible for the low.-level interface functiooso£the II bus and the high-level
protocol translation necessary for interbus commUniCation. It assists in managing the exchange of
data and provides trans~nt translations of read and writettaris4ctions, error conditions, and
interrupt requests .. A block diagram of the BCI3 is shown in Figurei.
.--.::o.<:-.=;- - - -. - -I
I
I
I
I
I
I
I
I
I
I
I
I
I
I v-~===:'::::::"'..,..-v' "~===~v' I
I
I
Il _ _ _ _ _ _ _ _
_ _ _ _ _ _ JI
Figure 1- VAXB178733 ReI) Block Du,gram
COnfidential and Proprietary
:4-159
The Ben translates protocol,l'QUtes transactions betweenb\lSeS, and. detects and resolves bus
transactions that result in a deadlock condition. Read, write, and interrupt request transactions
from the processor are automatically translated into VAXBI transactions. This includes the transfer
of data and the exchanges of error information when necessary. Devices on the VAXBI hus can
access the II bus resources and interrupt the operation of the processor.
In addition to supporting processor nodes, the Ben can also be used in intelligent MicroVAX-based
peripheral devices. It contains a 5 Mbyte-per-second datamover for high bandwidth block d!lta
transfers used by I/O devices .
• Pin and Signal Descriptions
The VAXBI 78733 is a 132-pin interface that functions with the input and output/signals and
voltage and ground connections described in the following paragraphs. The pin and signal
descriptions are grouped by II bus signals and by Bel bus signals. The pin assignments· are shown in
Figure 2.
p
14 13 12 11 10 9
•
N •
M
.a . . .
7
6
5
4
3
2
•
1
•
•
•
•
•
•
•
•
oft
L
K
•
H •
G •
F
•
E
•
BCI3
•
J
•
H
• G
F
(TOPVlEW)
•
D •
E
•
D
•
C
C •
B •
•
•
•
B
•
•
•
A •
•
•
•
A
4
3
2
1
14 13 12 11 10 9
8
7
6
5
Figure 2· VAXBI 78733 Pin Assignments
4-160
N
M
L
K •
J
p
Confidential and Proprietary
_:
PrelimiAary
II BuS Sipals
.
"
Table 1 is a summary of the input and output signals that connect to then b~. It also includes the
power and ~ndconnections. The signal functions are described in thffoJlowing paragraphs.
llJblel·VA;XB11S7.un Bus Ym and Signal Summary
.],,$
Pin
SipdJnput/Output
~
.
.
N3,P3,MJ,P2
N2,Pl,M2,Nl
K3,Ml,L2,L1
K2,KIJ2Jl
Hl,G2,Gl,G3
Fl,F2,El,E2
Dl,D2,Cl.E3
Bl,C2,A1,C3
II DAL< 31:00 >·input/output II Data address lines < 31:00 > -Supplies
da.hl,and address information.
N4,N6,N5,M6
IIBM<3:0>
input/output II Byte nWk <3:0> lines-Specifies the
bytes to be read or written.
N7,P5,M7
IICS<2:0>
input
,
-
"
II Cycle status <2:0> lines-Used with
the
IlWR line .~d,pedfy the" Q~ra~~nOr ~e
current cycle.
M8
HERR
M9,N12,P14,
M12
IIIRQ<~:O>
N8
··iiRIS
N9
IlDMR
Nll
IIRESET
P4
IIWR
ftt~~pt~t,~3:Q;;> .·1itIe~-In~ertupt
o!l~put
~quest~p7to ~J{:L14,
.. , ' , ".
II Retry ~~sttobe~tin.tro~.the lo~ of
thel:WY:ad~sreids~er.
n DMN ~~$t-'--Requests
aDMA
trans£et
"i" . "
'"
",'"
,,- "
c"
,-,'.'
IIWrite':"'::~d'e$ .:eild 'ahchvtifuc6ritrol of
input
theaus.
P6
lIAS
input/output I I Address ~tr~'7"""l,rl~ites < ",hen valid
addre~~ldycI~:status.and write~ and maSk
J
'
informAtion'isavlillable.
inpu~/outp\ltn Da,hl~~,·~·Jndica~ wIindata.aan be
P7
,tnmsf~ ,onJ;he bJ,ls..
P8
P9
IIRLOE·
.
JIRetry latch "output enabJe--Enables the
.transfer of the retry· addrellslatch infer·matiotl.
input/output II Dat~buffer enable~Control~theDAL bis
transceivers.
P10
input/output II Ready-Indicates the status of a data transfer.
For In~.Us~ Only
4-161
mama.
Preliminary
Pin
signal
Input/Output Def:inition/Function
PH
'II RETRY
input/output II~~ry~Requests;achange in,hus mastership and indicates a locked location.
P12
IIDMG
input
II DMA grant-Indicates that the Bcn has
been granted the bus for a DMA transfer.
P13
IINLMR
input
II Nonlocal memory reference-Indicates
that the memory space is not local.
L13
'1'OD
input
Test output disable-Causes the BCB outputs to become a high impedance. Used for
test purposes.
D3,D12,L3,L12, Von
input
Voltage-Power supply voltage
C5,E12,E13,M4 Vss
M5,MIO,Mll,
input
Ground-Common ground connection.
II Data atidAddress Lines (n DAL < 31:00 »-These lines transfer data and address information
between the Bcn and II bus.
n Address Strobe (ii'AS)-The,II bus master asserts this signal to indicate that a valid address is
available on the II DAL< 31:00 > lines and that valid status information is available on the
II CS< 2:0 >, IrWR,and n BM < 3:0 > lines. The subsequent deassertion of this signal indicates
the end of the bus cycle. This signal is synchronized internally by the BCD.
DData strobe(lfDS)......The II bus master asserts this signal during a read and interrupt
acknowledge transaction to allow the slave to transfer data on the II DAL < 31:00> lines. When
the line is deasserted, it indicates that the selected slave may release the DAL < 31:00 > lines.
During write cycles, this sig~al is asserted to indicate that valid data is available on the
DAL < 31:00> lines and de asserted to indicate that the master will soon release the DAL < 31:00 >
lines. This signal is sychronized internally by the Bcn.
ri Data Buffer Enable (II DBE)-This signal is used by the bus master to enable the DAL < 31:00 >
transceivers.
II Byte Mask (n BM < 3:0 > )-This signal is used by the bus master during a read or write
transaction to indicate which bytes within the data 10ngword are to be read or written.
II Ready (II RDy) ......This signal is asserted during a read transaction to indicate to the bus master
that data is'ready for transfer. During a write transaction; ids asserted to indicate to the bus master
that data has been latched. The sigrial is sydrronized internally by the BCn.
n Bus Error Indicator (II ERR)-Assertion of this signal by the BCD during a MicroVAX-initiate~ Together-with theft sigruil, these lines indicate the Cttttelltbus
cycle type requested by the II bus master. Table 2 lists thebus'cy'eieSelections.·
on'lb.
WR*
"lus~lfi'e
CS line*
2
1
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
'H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
0
L'"
H
L
not used
; HWtertuPt~ledge
L
~ )- These lines are used by the Ben to ~ue~tqus
mastership from the MicroVAX. Each line corresponds to an interrupt priority line IPLailistedjp
Thble 3.
,.
Table 3 • VAXBJ787?3~pt Requtsi Line Assigmnents
Requestlevel
(hexadecimal)
.
,i"q
'_:
IPL17
lPLl6,
lPL15
IPL 14
Confidentialand Froprietaty
4·163
Pre1iminMy
H~DMA Request (H DMR)--This line is· asserted by tlie'BCB, to request hus ~stetship froml:he
MicroVAX CPU.
.
H DMA Grant (II DMG)-Thislineisasserted to indidttet6the SCB that it hasheen grimted
mastership oftbe n bus. After the U DMR line is negated, this line mUS,t be negated befot:ethe
n DMR signal can be reasserted for the next II bus master transaction sequence.
H Nonloc:al Memory Reference (IT NLMR)- The memory controller asserts this signal to indicate
that the address of a memory-space II read or write cycle does not reside in local II bus memory.
II Retry (Ii RETRY)- This signal is asserted by the Bcn to request that the MicroVAX relinquish
bus mastership and reissue the CUt'tent ,II bus transaction ata latel:' time. The memory cootfullel:'
asserts the II RETRY signal in response to an II bllsread lock to indicate that a location is locked~
The BCn assumes that this signal will not be asserted when it is II bus master except in responset6
the n bus read-lock transaction.
II Retry Latch Strobe (IIRLS)-This signal is'asserted to latch the address information on the
II DAL < 31:00 > into the retry 3ddress register. When negated, the retry address register is
transparent.
II Retry Latch Output Enable (II RLOE)-This signal is used to assert the contents of the retry
address register on the n DAL <31:00 > lines.
BCI Bus Signals
Thble 4 contains a s\:t.futllary of the input and output signals that connect to the BCI bus. The signal
functions are described in the follOwing paragraphs.
'.Dahle 4'. VAXBI 78733 BCI Pin and Signal Summary
Pin
Sipal
Input/Output De6nition/Function
B2,A2,C4,A3, BCID<31:00> input/output BCI data < 31:00>-Used to transfer data
B3,A4,B4,A5,
between the Bcn and the Bcn.
B5,A6,B6,A 7,
C7,A8,B7,A9,
A10,B9,All,C9,
A12,BIO,A13,Bll,
A14,B12,B13,Cll,
B14,C12,C14,C13
B8,C8
BCIPOWER
input
BCI power-Monitors the dc power of the
BIIC.
C6,ClO
BqGNp
input
l3CIground..,-Common ground reference for
the Bne signals.
E14,F13,
DI4,D13
BCII<3:0>
input/output BCI Information < 3:0 > -Transfers command values read status and write masks.
F12
BCIMDE
input
4-164
BCI Master data enable~Indicates when data
on lines BCI D<31:00> and BCll<3:0>
should be,transferred to the BIIC.
Confidential and Proprietary
-
VAXBI18:vJ)
Pin
F14
:SCICLE
input
BCI C.ommapci la~h enable-.-Indicates when
BI command/address infOrmation is available
during slave-port .operation.
G12
BCISDE
input
BCI SlaV¢ d~ enable-.-Indicates when the
Bcn should transfer data .on the BO
D< 31:00 >:and :sq<3:0> lines.
G13,G14
BCIRS
.output
BCI Slavere&ponse < 1:0> lines Used by
the BCU t.o acknowledge the slave-poJ't
opera~on.
the event
H12,K14J13,
J12,L14
BCIBV<4:0>
input
BCI Event <4:0> lind.....,Contains
status information from the BIlC.
P14,K12
BCIRQ<1:0>
output
BCrRequest.;....:.Initia.tes· BUCmaster-port
operations.
J14,H13,H14
BCISC<2:lb
in!i'ut
BcI S1a;ecocie<2:0> lines-U~totrans
fer status·iiJformatibrt durlt1g Bnt slave-port
operation.
M13
BCITIME
input
BCI tilTtc!-A. 20-MHz TTL clock reference
signal from the BUG,
M14
BClRAK
input
Bq ~uest acknowledge-P19vides transactiontirning.
':
,
'\'--
N13
OCIPHXSE
input
BCI Phase--A j~MHz clock reference signal
from the SHe.
N14
BClMAB
output
BCIMlI$te~'a.bClrt-Used to halt current BIle
master~{)Qrt;9~tion.
Bel Data (BCI D < 31:00 > )-These lines are used to exchange VAXBI data and address field
values with the BHC.
BCllnformation (BCI I < 3:0> )-These lines are used to exchange VAXBI command field values,
write masks, and read status with the BIlC.
BCI Master Request (BCI RQ<1:0>-These lines are used to initiate BIlC master-port
operations.
BCI Request Acknowledge (BCI RAK)- This signal provides timing information for BHC masterport operations.
BCI Next (BCI NXT)-This signal provides timing information for BIlC master-port operations.
BCI Master Abort (BCI MAB)-This signal aborts current BIlC master-port operations.
BCI Master nata Enable (BCI MDE)-This signal indicates when the Bcn should transfer data on
the BCI D < 31:001 and BCI 1< 3:0 > lines during a BIlC master-port operation.
Confidential and ,Proprietary
4-165
-
BCI Slave RespOnse (BCIlS ;S;.~;b »-1;1tese· si~pal~areJJsed by the BCl> tQ. acknowledge BIle
slave port action when it is aCting as the selected VAXBl slave,
.
BCI Commandl.atd. Enable (BCI CLE)-This signal·illdicares when VAXBI command/address
information is available on the Bel D<31:00> and BCI 1<3:0> lines during Bne slave-port
operation.
DCI Slave Select Code (OCI SC<2tO> }-These signal provide status information during BIle
slave-port operations.
BCI Slave Data l!nable (BCI SDE)-This signal indicates when the Ben should transfer data onto
the Bel D < 31:00 > and BelI < 3:0 > lines during BIle slave-port operations.
BCI Event Code Iniormation(BCI EV < 4:0 > )-These signals provide status information during
BIle master-port and slave-port operations.
BCI Time (BCI TIME)-This signal is the local BI node's versioriof the 20-MHz VAXBI dock
reference signal.
BC.I Phase (';BC~I:--;P~HA;-r;;S""E')signal is the local VAXBI node's version of the '-MHz VAXBldock
reference signaL
Test Output Disable (TOD)-This signal forces all Ben outputs into a high-impedance state. It is
intended to support board-level manufacturing tests andindudes an internal pullup circuit.
Power (VDO) and Ground (Vss)-V DDconnects to the power supply positive voltage and Vss
connects to the power supply and signal ground reference .
nus
• .A:rchitectuml Summary
Figure 3 shows the internal· organization of the Ben interface that includes four major
subsystems-an II bus controller thatihitiates and responds to microprocessor bus transactions, a
VAXBI master controller that initiates system bus transactions,a VAXBI slave controller that
responds to the bus transactions and a datamover controller that coordinates the high-level DMA
operations. Each is individually controlled and the three bus management subsystems each contain
a 36-bit (32-bit data and 4-bit tag) bidirectional data· bus. These four subsystems operate
independently and can simMcineously service multiple transactions.
4-166
Confidential and Proprietary
VAXBt787))
Preliminary
CONTROL AND STATUS FOR eSRs
REQUEST
STATUS
CONTROL AI\ID STATUS FOR
INTERNAL VAXBI MASTER
BUS AND BCI INTERFACE.
OONTROl, AND.srAiuS .F.QR
INTERNAL II BUS AND II
INTERFACE.
CQNTROt.AND ~TATUSFOR
INTERNAL VAXBI SLAVE BUS
AND BCI INTERFACE
Figure 3 • VAXBI 78733 Internal Subsystem Otganhation
In addition to performing requests fromtheMicroVAXor.contron~; the BSI3autotnatically
translates the transactions directly intoVAXBI trans~ctions arld~p()nc1s fu afiinterru~t ~cknoWl~.'
edge tran$actions. It interrupts the MicroVA't uaniriterrupt requeSt; is received from another
VAXBlnode. In response to DMA requests fromtbeVAXBrbus,the Bl:;!I3accessesthellbusllsing
the standard DMA protocoL
Memory IWetenees
When the MicroVAX processor references a memory space location, the memory controller or
eqUivalent logic determines when the addres~spaceiswitbin.th.erange aij,eeaiedto theBGI.3
iriterface.Thecontro1ler asserts the nonlocal memory (II NLMR:). signal to indic"te ·the re£erenceis
not a memOry· location, The Ben translates ~here£erence,i1ltothe.equivMent VAX:RI·trabsactioD,
transfers it to theVAXBI bus,. and reports the.resolts ta the;MictioVAiXusingthe n bus read and
write protocol.
The response (lfthe Ben to the MicroVAXI/OsPate refeienee~.dePendson .theaddress . range
specified. If the address of the MicroVAX is within thenooe privatt¥space, thei:esponse of the Ben
depends the location accessed. The addl:essassigbments of· the Mkri>VAXilnd tM' allocated space
of the Ben interface are shown irJ. Figure 4.
Confidential and PrOprietaty
4.167
-
VAXBJ: "iS7}}
Preliminary
20000000
20040000
IBOOT ROMS)
20040000
2008 0000
LOOPBACK SPACE
2008 2000
2008 4000
NODE PRIVATE SPACE
BC13 (CSR)
USER'S CONTROL AND
STATUS REGISTERS
ICSR)
20100000
r
J
20100000
3FFF FFFF . '-_ _ _ _ _ _ _ _
..1
FigU1e 4· VAXBI 78733 MicroVAX Node Private Space Add1eSS Assignments
The lowest 256 Kbytes of II bus address space is assigned to the ROMs that contain the bootstrap
program, The next address range consists of an 8-Kbyte loopback space and the BCB will respond
to addresses in this range by using the loopback feature of the BITC to permit access to the BITC and
BCll nodespace registers without performing VAXBI transactions. .
The BCI3 control and status registers (CSRs) are located in the next higher 8-Kbyte range. These
registers are accessible through the II bus and are accessed by the BCn without involving the BIlC
or VAXBI bus. The user CSR space is ignored by the BCI3 and may be used by local II bus devices. If
the address of a II bus transaction is not within the private nodespace, the BCB translates the
transaction into a VAXBI bus transaction and reports the results to the processor usj,ng standard
read or write protocol.
Intertupt Vector Requests-An II bus interrupt request can be initiated as a result of a transaction
from the VAXBI, by theBCI3 interface, or by a device on the local VAXBI bus node other than the
BeI3. When the MicroVAX acknowledges an interrupt request, the BCB serves as the local II bus
interrupt arbitrator by determining which of the outstanding interrupt requests will be serviced by
this transaction. If a VAXBI interrupt is being serviced, the BCB will solicit an interrupt vector
from the interruptj,ng VAXBI node usj,ng the VAXBI IDENTtransaction. If the interrupt bej,ng
serviced is a result of a VAXBIIPINTR (IPL 14.only), the BCB returns a fixed vector of 80
(hexadecimal).. If the interrupt is BCB initiated (IPL 16 only), the BCl3 will return a fixed vector of
58 (hexadecimal). If none of these conditions are pending, the BCBinterface returns a vector on
behalf of a local device-the value of which depends on the IPL of the interrupt vector as follows:
FO (IPL 14), F4 (IPL 15), F8 (IPL 16), or FC (IPL 17) .
• Register Description
The BCI3 interface contains two groups of registers. The nodespace register file is accessible from
the VAXBI bus and consists of 12 general purpose l'egisters and a two-ported toggle registers. The
Bcn private registers are accessible from the II bus and consist of 28 registers that are used to
control the transfer of information, to report status, and to generate interrupt requests.
4-168
Confidential and ProprietarY
-.
VAXB1131l'J
Nodespace Registers
TheBC13 •.:iruedace contains 14·nodespace registers used.to facilitate ·com.muniCation.Detween
different BInodes~ Thenodespace registers and address assignments are shown in Figure 5.
31
00
I
BB+200
..
.'
88+204
GENERAL' PURP9SEREGIStEI'I1
88+208
GENERAlPURPfJSE REGIS!eft2
8B+2OC
GENERAt: PURPOSE REGISTER 3
'.
'
'
."
",
i,
....
'
..'
.,
"'"
',,'
", ,
..
,
"=',,:,:.
",i,
88+210
'.
..
""
88+214
GENERAL PURPOSE REGISTER 5
8B+218
GENERAL PURPOSE REGISTER 6
8B+21C
GENERAL' PURPOSE REGISTER 7
B8+22O ,,'
GENERAL' PURPOSE REGISTER .~
i
.'"
',.
,'"
."
'C;
B8+224
GENERALPURPOSE REGiStER' 9
88+228
GENERAL'PIJRPOSE REcnSTERjo
BB+22C
GENEflAL'·PUflPOSE REG1$TER 11
.:i.'~
,i,'
. .
' ...
", "
.,'
BB+23O
I:
1-- -
TOGGLE REGISTER A SET ~RT
-
-
-
-
-
-
-
-
-
-
-
..... ' .... -
-
-
-
...... -
-
-
TOGGLE REGISTER A CLEAR PORT
8B+234
"
"',>.'
88+238
B8+23C
I
l
i
TOGGLE REGISTER B CLEAR !'o.RT
It
.1 h i '
...LtL.LL.LJ. .3..3.i ..1..1
Figure 5.. V4XIU 787:)3 Node$paCt:~gjster File ,
General purpose registers 1 through 11 and the two toggle registers are accessed by 16 VAXBI
longword addresses; bb+200 through bb+23C (hexadecimal). The nodespace registers can be
locked by a read lock command issued to anyone register. This command locks the entire set until a
write unlock command is issued.
Each of the toggle registers can be accessed from two addresses. Writing a 1 into a bit of the lower
address register will set the corresponding bit in the register. Writing a 1 into the higher address
register will clear the corresponding bit in the register.
Confidential and Proprietary
4-169
...
VAXB1781J3
Private Registers
The private registers are.accessible only from the Rbus. They may be referenced usingiongword
length transactions but do not support the masking of write operations; Theregister£ile and
assigned addresses are shown in Figure 6. Some BCn internal address registers in this address space
can be used for diagnostic purposes. However, they must not be used during normal Bcn
operation.
31 .
o0
00
BCI3 CONTROL AND STAT:US
04
. BCI3MASK
08
BIIC EVENT STATUS REGISTER
OC
BIIC EVENT INTERRUPT MASK REGISTER
DATAMOVE CONfiGURATION REGISTER
0
4
BI MASTER COMMAND/ADDRESS REGISTER(JNTERNAL)
8
BI.MASTER DATA REGISTER (lNTERNALI
C
BI SLAVE COMMAND/ADDRESS REGISTER (lNTERNALI
20
rr-
:1C
BI SLAVE DATA REGISTERS (INTERNAL)
r-
-
30
~"v
4 {~
.lJNUSED
48
BI ADDRESS REGISTER'
4C
II ADDRESS REGISTER
50
DATAMOVE DATA REGISTER 0
54
58
DATAMOVE DATA REGISTER 1
DATAMOVE DATA REGISTER 2
5C
DATAMOVE DATA REGISTER 3
9- u
£rv
6
6C
UNUSED
"'u
r~
II ADDRESS REGISTER (ALTERNATE ADDRESS,INTERNAL)
0
DATAMOVE DATA REGISTER 4 (INTERNAL)
4
DATAMOVE DATA REGISTER 5 (INTERNAL)
7a
DATAMOVE DATA RE.GISTER 6 (INTERNAL)
7C
.. DATAMOVE DATA REGISTER 7 UNTERNAL)
Figure 6· VAX13f78733 Private Register Assignments
4-170
"'I'"
INTERRUPT VECTOR CONSTANT GENERATOR (INTERNAL)
44
6
rv
Confidential and Proprietary
-.
BCD Control and Status Register-The Bcn control and status register (BCI} CSR) contains 16
nodespace write sense bits, one for each of the nodespace regi*r addresses shown in Figure 4.
These bits are set when the BCn is accessed by another VAXBI bus node. When information is
written into a nodespa¢eregister, an interrupt request (IPL 16) is generated and the corresponding
bit in this register is set. The interrupt can be masked by t:h~i~~ti()flin the control and status
mask register. The register also contains controlaMstatus'bitsus$1 by the datamover. The register
format is Shown in Figure 7 and the information is described ~n ':fable 5.
2423
31
1615
0807
00
x = IGNORED ON WRITE 6PER~T10NSAND
RETURNS ZERO ON READ OPERATIONS.
Figure 7· VAXBI 78733 BCI3 Control and StatusRegjster For1mif .
Table 5 • VAXBI78733 BCD Control and Status ~tet Deaeription
Bit
DescriptiOn .
"
31;26
Not
25
DMOVE. DONE (Datamove done)...,...When set, .it ..indicates.that the datainove
operation completed successfully.
23
DMOVE ERR (Datamove error)- When set, it indicates that the datamove
operation was aborted due to an error. Cleared by writing II. 1 to this bit.
22:16
Not used.
15:00
N04e~pacewrite sense bits~SC\twl\c:ln the~~pon~~~pace,regjs~~
received data from other Blnodes. Cle~redby\Yl'i~1\l1 to t,his bi~.
.
used:
BCU Control and Status Mask Register-The BCI3 control and status mask (BCn CSMR) register
contains 16 nodespace write sense mask bits that are used to mask the sense bits in the Bcn control
and status register to prevent the generation of an interrupt. The register also contains bits to
enable datamover interrupts arid global interrupt enable bits .. Figure 8 shoWs the register format
and register informatiol1is described in Table 6.
. .
Confidential and Proprietary
4-111
Figure 8· VAXBI 78733 BCIJ Control and Status Mask Register Format
Table 6· VAXBI 78733 BCI3Cont!roi and StatUs Mask Register Descrg,tion
Bit
Description
31
INT EN (Interrupt enable)-Set by the processor to enable an interrupt request
that originate in the Bcn.
30:26
NotJ,!.Sed.
25
DMOVE DONE M (Data move done mask}-Set by the processor to allow an
interrupt when the corresponding bit in the control and status register is set.
24
Notu~.
23
DMOVE ERROR M (Data move error mask)-Set by the proc¢ssor to allow.~
interrupt when the corresponding bit in the control and status register is set.
22:16
. Not used.
15:00
NODESPACE WRITE SENSE MASKS-Seno enable interf\.lpts when the correspondingbits of the control and status register are set.
BnCEvent Status Register-The BIIC event status register (BIlC ESR) indicates the history of
everitsspedfied on theVAXBI event lines BCH~V < 4:0> , eXcept for the1ntel'lOck error indicator
(bit 0). Bit 0 is set if the readlOck fails after the BCI3has read data from the II bus resulting in a II
bus memory lock condition. The bits in this register are set· by the Bcn and cleared by the
processor by writing a 1 into the required location. The Bcn will interrupt the processor when a bit
is set provided that the corresponding mask bit in the event mask register is set. The register format
is shown in Figure 9 and the bits are defined in Table 7.
31
2423
161!>
00
0807
INTERLOCK ERROR
D - DIAGNOSTIC INFORMATION
E = VAXBI/BIIC ERROR INFORMATION
S = VAXBIIBIIC STATUS
Figure 9· VAXBl78733 BIlC Event Status Register Format
. Confidential and Proi'rietaiy
Table 7 • VAXBI 78733 BDe Event Status Register Description
Bit
31:01
Event Code bits-Specifies theBIIC events as'follows:
31
MTCE (Master transmit error check)
30
29
28
ICRMC (Illegal confirmation received for master-port command)
27
BPR (Bad parity received)
26
25
24
RDSR (Read data substitute or reserved status code received)
23
AKRNE7 (Acknowledge confirmation received for nonerror vector-level 7)
22
21
20
19
BBE (Bus busy error)
18
ICRSD(Illeg!ll confirJllati9fl received for s~.cla,tl).
17
BPS (Badpatity received during slave transaction)
16
STO (Stall timeout on slave transaction)
~
"
' " -,,, ':\C'
,
..
,'~'"
,'"
",,'" ". -..
' . , . \ _('
,""
'
"
15
14
EV6 (External' vector selec~:':1~eI6Y'
13
EV5 (External vector selected-level 5)
12
EV4 (External vector selected-level 4)
11
IAL (Identification arbitratiQnJQ~).
10
AKRE (AcJmowledge confifrnatiQn. reCtiived for ~r vector)
09
NICIPS (No acknowledge of illegal conmmlttion received fodoree-bit interprocessor!
stop command)
...
.08
_,,"
,',,_
"',,,.
_." __ "
" " ' , , , ,L . . ,,',
'."
"_,,
NICI (No acknowledge or illegal confirmationrecei~ed fo~ interrupt command)
07
ARCR (Advanced retry confirmation received)
06
IRW (Internal register written)
05
RCR (Retry confirmation received for master-port command)
04
STP (Self-test passed)
Confidential and Ptoprietary
4~17;
-,;
Bit
Description
03
BTO (Bus timeout)
02
AKRSD (Acknowledge received from slave read data)
01
MCP (Master-port transaction complete)
00
INT ERR (interlock error).,.....S~t to interrupt the Mi,croVAX during .,al'l, error conditio!).
provided that the corresponding mask bit is set in the BIlC ~nt mask register.
BllC Event lntqrupt MaJk RegiJter- The BOCeventinterrupt 1lUlSkregister (BIlC EIMR) is used
to mask the event indications in the event status register to prevent the generation of aninterrupt.
The bit mask assignments are shown in Figure 10 and theevetitcodes are defined in Table 7.
31
2423
1615
0907
00
','H M:M:M:M :M:M; MIM:M:M: M:M:M:M:3 M:M:M:M :M:M:M:M!M;M,: M:M;M:M :M:M!
\
I
. '. - EVENT MASK BITS:=]
M=
SET TO ENABLE EVENT INTERRUPT
Figure 10· VAXBI 78733 BIICEvent Interrupt Mizsk Register Format
Datamover Configuration Regis~- The datamover-configuration register (DMCR) is used during
datamove operations and to specify diagnostic mode operations. The register format is shown in
Figure 11 and described in Table 8.
31
2B
21
13,
00
IH"r I: :: ::IbD,~iiD;,:1 :>F~+H++f ::I
- Figure 11 • VAXBI 78733 Datamover Configuration Register Format
Confidential and Proprietary
-
Table 8 .. VAXIU 78733 Datamove Configwation Register Description
.~
Bit
,
31:28
27:20
Nottised.
21
DrAG MODE (Diagnostic mode)--S~tto irriti~te4iagnostic(Ilode opetatiQn.
20:14
Not~d.
13iOO
Transaction coUl1t.cLConWlls'llititWc)'s con1pte~ritoHhenu.t:nbet d£octaWOtas to
be transferred (from 1 to 16K octaWotds)~tne datainove.
'
C'
" ' "
-,
" , ..
"
,"
,',. ,"(1.
"'.
'
"
,','
"
B1BlUi A~s Register-The ,Bladrlress. regis~{~I~)ct?n~;~~ ~~tiqgVAXBI ad~$~,alld
VAXBI~f1saction length code to heu500br tlle~~tl1~r.,~eonteritSofthiS,te$i~r ~m,be
a1tereddlirIDg datamoveroperations. The registe,r forjnitiS
sMWllin
F~l,1!12.'
,
":> "
"
.',,:
. , '
\'
(
,';
,
,t,"
',,'
,
.;&,"'_,
,,_. : ';.,'
,
nBusAddles1lReaiSfet-1'he U bus lKtdteS$regi$~: lines. The BCD sets a bit in the event status register that may result in a processor
interrupt. Critical errors such as BI master transaction errors can terminate the corresponding Bcn
operation. The Bcn notifies the processor of errors detected during windowing operations using
the II ERR signal. Errors detected during datamove operations cause the BCI3 to abort the
operation and to set the datamove error bit in the datamove register.
4-176
Confidential and Proprietary
un, "
PreI' .•. ,. . :
n Bus Read Thmslations-The II bus to VAXBl bus read translations' are'
nJu. eomm.ri~f
VAXlSI B~s~
~d(ls~)
, READ
READ LOCK
Read Lock
Read (D stream, modify intent)
REAP·
Read (D stream, no modify intent)
READ
The length of the VAXBI-generated transaction is a longword with D < 31:30 > equal to 01 in the
command/address cycle .. Bits D <29:00> are transferred to the, VAXBlbus. VAXBlrodesusuaUy
ignore bits D <.: 01:00 .
'>
"
The Ben generates a II bus errot:~whett
• The VAXBI transactio'll.is.notackoowledgedorexceedsthe timespeci£i~ for completion..'
.' InvaliclparitY is detected or an illegal confitm.ation'code is received.
• A read data substitute or reserved read s~tus COde is receivedftotntheVAJmloos.
n Bus Write 'Itanslations-The Itbristo VAXBlibus w.rite tralls~tionsare
IT Bus command
vAnI Bus commaDil
Write (D stream)
Write unlock
,
WlUTEMASK
,WlUTE UNLOCK
The write (P stream)transar;tio~ is transJatedintpaYAXBIWlp~~SK aneJ8 II ~riteu~ is.
always translltted intO'.~.VAXnI WRttEUNLOCKtbfusQdlon.~l~~hOrtbe g~tefJV~I
transaction is alwaYs .a.l&~rd (D < >1:30 ~ fOl~.Jn tbe VAxai#>pmlaf.ldaddieSs~e.Bi~
<29:00> oftheIrJ)usaddtessaret:ranSlel'reJtofheVAXBHt~~. " ,"., ' , i ' ' , , '
The II ERR signal is asserted by the BCn by the following:
• The VAXBI transaction times out.
· Invalid parity orvAX~fbus ~~rS are~tect~;:~VAnlb;'"
n~slPtetntpt~~~~:wp~~;~,n~lW~~~.jUtitl~u~'~~Wlmmalld if~ V~l~I'UPti(~Nl~lis)~&¢~ at~pri~tyl~
specified by the acknowledge. The vector returned by the IDENTcolllmand completestb:;:Ill:ms
interrupt acknowledge t~l1Sactio~'TI:e VAX131 U1!X',~})t~~~~~~jJl Sl~~~~~~ic~f11:pleti09
of the"transaction
or, When
anerio'iis
detectedThe BCI~~ne~te~~n;huS~r.~~\Vhen
'.'... "
"
<- '
_' :' \
'_'
''\'
'_,,'
,).,:,d "C',:
"'-:':":!'_-"
;
',.",
,:$""
.' "'.-"",'"''
C,
-' " . , '
r,
_
._,
• TheIPENT COQlmaQdis ll()tacknO;wledgedPl'PCfl4:~llthe)t~~ f<;)l''COmpl~ion.i
• The Bcn teceivesatl illeghliVAXBrcon£irirl~i6nCCide.
i " ..
4177
VAXBI Bus to IT Bus Tran$4CtjP,lls
The VAXBI bus read and~it~commandsdla1;~~e an ad~~s between the stariiI1~. aJ1d ending
address register values of the BITC interface are trah~lated to II bus read or write coirunands. VAXBI
bus quadword-Iength transactions are translated into two longword length transactions. VAXBlbus
octaword transactions are translated into four 16hgword-length transactions. Table 10 lists the
translation between the VAXBI bus command and II bus transactioris.
18ble 9· VAXBI 78733 VAXBI Command to II Bus Command Transactions
VAXBI Bus commands
II Bus commands
READ
Read (D stream, no modify)
INTERWCK READ*
Read lock
READ WITH CACHE INTENT
Read (D stream, no modify)
WRITE
Write (D stream)
WRITE WITH CACHE INTENT
Write (D stre.am)
UNWCK WRITE MASK
Write unlock
WRITE MASK
Write (D-stream)
*Gommands of quadword length are translated into a II bus ~~d lock transaction followed by a
Read (D stream, no IDodify) transaction. Commands of octaword length are translated into a II
bus read lock transaction followed by three Read (D stream, no modify) transactions.
Read Translations-During read-type transactions from the VAXBI bus, the BCn, w~lnormally
stall the VAXBI node until the translated transaction has cOIDpleted. When the II bus memory
controller transfers the requested data signified by the assertion of the RDY'signal, the Bcn
returns the data through the VAXBI bus with a "read data don't cache" status. If the memory
controller responds with an error (ll ERR) or retry (II RETRY) signal, the BCn returns the
appropriate no acknowledge· or retry confirmation on the VAXBI .bus arid terminates the
transaction.
n
Write 1hmslations--The BCn acknowledges aVAXBI write-type transar;tion when the data has
been successfully received but before the completion of the actual· write operation. Write
transactions that fail because of nonexistent memory' and other conditions are not reported to the
VAXBL This disconnecting of write transactions. ~ows the VAXBI bus tc;> pa,r,ticipate ill other
transactions while the Bcn completes the write (detached) transaction to the II bus. If the BCB
receives another VAXBI read- or write-type transaction before the la.stwrhe operation has been
completed, it willrettyall subsequent VAXBl transactililP8 until the detached write transaction has
completed.
4-178
Con£ide~t.ial and Proprietary
Errorflamllina
The following events occur during an error condition.
-WOOnan enor«CW"son the II bus side during a VAXBI bus to II bus window'read ~tiot1; the
Bcn indicates an error bY.issuing a no acknowledge reply during the comm!U'ldladdress cycIeof
. .... I read traOS;a~9n.
All II bus ¢trQrs ~. ~£>~i&d-, by
*e assertion Qfthe~$~naI
. .· · .
.the. . VAn.
..
...
', ,',;"
-
-
- ,,'
',-
-
,
""
,'.
,',
"
',"
"",""
,,-"
-'
""
""",
;
,,""
-'
.",,,,,
",'
"
""
--
""",,
~
{\
".,',
",
• When an error occurs on the II bus side during aVAXBI btl$to llbus wind6wWrite,~ti()nj·the
~I3 inhibit~~dditiotli1l fL ~,us wrltetr~~p~~.~t ~n%m~~~~iii4J?r'~HltiIQ~~rd
write traQSfet No error wilt he repor~tptlie~l bus. . .'. .....
·.f'·,-,,, .'
<'
""
,,"
:",;
',:,'
,
,
'
, ' - ' , : ' " , ' " . ' ••
',_f
'.'
\, •., ' , ; . " "
-
\"
"
,i.
.
,'-";
.,-.-
. '
".,.
• The II ERR signal is used to inform the MictoVJtX. thatclll;\):us' w~I .bus 'win~
tranliactionb,as Peel} <:.ompl¢ted W¥\1c£e~li~ullY·lfiS.npt ~sieije@~tOj~~<;3.te~(ef#~ res!ll~lrig
,trom an inromIngVAXi3I bus transacti~n;;:'"
. .,
.', . .....,..... ........ .
·Uart error 4ulicatiqQ is ~veddu.-i,oganWCQriijng.VA.XBl~n bu~writetl;&nsact~ontoo'tVU
... 'ti. .l:lg
will.occuro.n. the.·.h.b.,.·.u.'.s •. ,
. . . . . . ' .... , .' .....' ..,. ,.., ..
>
• ,.'.
.c.
';:.'
...
'.
::~d
• If theWAXBI :read look faik.af1;eJfti1eBCI3 ~;tead the dat9:£rOiri'b:tl;I:)tl$(the;BC13 willJnot
unlock ilie II bus memory.
'1 '
• During ()ther YA,XfH to.II bus conditiofl&~fh"~>.J1';ml~~~~~sa,~~~n~.abit In .~.~
status register wiUbe setto i,rlJ:ettllptilie p.l"O¢¢s~:t' l(~(:ql:'~29Q1;liJ18~rerrupt maskl:litlm:sJ1o~
been set.
'
• Special Operations
The BIC3,mte:rface~JhecapaRilipe~.~; peJ:for:!1l,st>eqll1,P~~'tp im~~ th~ ef(igcl1cyof
data transact;ions . ~.~.,.~oF. i$agn~ti~,.t:e..s~p'W~~~~.$~~:cqm~ .~;.th~BGI3 to
transfer a sequence o£QctltWords~~n th~II bus ,and VAJ!;BI~:.··
, ," _',' ' '
",'" , '
',' -
-
,) ',_,
__ -
Datamove Operations ....
'I
0
-
\
"
,~
" •• -
-
' . " ' , , - ' , .,'
,
-
-
,',"-;-
-'
,':
J
.',
,.,
.... ' .....• '. ........ ;.......;.... . ......... '. ...... .
DUiiJ;lgdatamove6petations~ the MicroV'AX ~~e$'d1e])CB to"ttailsfe~a~,~uen<:e of (jCt~\'vdtds
betWeen the II bus and VAXBI bus; The Bd'lb~s'triinteinal~twitho.6m~r~ ~ina~~ns
and transfers them to the other bus. When completed, ilie BCI,,;itertttptsthe llfuC'ess6r.~aU$e
ilie datamove operation uses the VAXBI octawordtransfer, it is mote efficient than the MicroVAX
MOVx command iliat: transfers sequenceso£ individualloogWotcls. In addition, it allows the
processor to perform other operations wl::jeni:heda~ove ttansactiQnisin Ptc)Ccss.
If a RETRY request from the VAXB1 bus isreceim dUring the BI t~acti()n, the BCB will repeat
the transaction until it is successfully compl~or until a timeoufcOridit1on occurs. If the
transaction is not aclmowledgedar times out, i:h~,Bcl3·WiJ:[ s~t thePMO~E fERROR bit in the
control and status register. The cause'of the fan~emustbeGletermiried~mthe BCIJand BilC
interface status regis~s.
The datamove command uses the datafficive copfjgrtration register, control and status register,
control and status mask .register, II bus address re/iister,anrl the B1 bus addressregi~ter in the Bcn .
The data to be transferred must be aligned by octawo.1:'ds and the source anddesdnanon blocks may
not cross a 256·Kbyte address boundary.
ConiidentialandProprienuy
4-179
Data is transferred from the II bus to the VAXBI bus by the following operations. The,datato be
transferred must be octaword aligned on the nbus and.VAXBl bus .
•• The starting ad~s·of the of lIbus data (source) is loaded into the Bcn II bus address register. by
the microp~SSCi)r.
-The starting address of the VAXBI address (destination) is loaded intO the vAXBlbusaddress
register in theBCn by the microprocesSOl:. .
• TheBI WRITE command (Code 0100) is written into the BICMD field and the two's complement
ofthe the number of octawords to be moved is Written into the transfercou'nt field of the
datamove configuration register by the processor.
• The GO DMOV bit of the Bcn control and statliS register is set bY the 1l1icroprocessor to initiate
the data move operation,
status register at theetld of the tran:sa¢tion
or sets the DMOV ERROR bit during the transaction if an error detected during the ttansaction.
These bits can' generate a microprocessor interrupt li enabled by the corresponding mask bitsi in
the controland status mask register.
~. The Bcn Sets theDMOV DONE bidn the control and
The sequence required to transfer data from the VAXBI bw to the II bus is similar to the previous
transfer exceptthat a BlREADcommandcode(OOOl) is Written into the BICMD fie1dofthe data
configuration register by the microprocessor.
• Application Information
Refer to the Bel) Engincet1ng Specification (DC344)for more detailed inforrfiation of the operation
of theVAXBI 78733 interface, the VAXBI System Rej'erenceManual(documettt nurnberEK-\ffiISYRM) for information on the VAXBI bus operation, and the VAX1:I1 78732 Bus Interconnect Inter/aCe
Chip (BIlC) information contained in this databook.
Figure 14 showsa. typical system implementati,onconsisting of three )nicroproce~sors.E~ch
micl'Oprocessorco1'lltnunicates with memory and'devices through its I~ bus and to the VAXBI bus
through the BCn ~nd BIlC interface.
Figure 14· VAXBI 78733 Typical System Configuration
4·180
Confidential and Proprietary
The II bus is a 10 Mbyte-per-second private bus that communicates with the lJ~~te-peN~(.lO~
VAXBI SY!ltem bus through the Ben and BIle intel;face sUUct\lre.BQthb\lsesi.m~.a
common 1.Gbyte address space. All resources with the exception of certain nodespace locations
can be accessed through the uniform addressing arrangement .
• Specifications
The mechanical, electrical,andenvitonmental::cspetlifications £«: the VAXBI interface·a.re.as
follows. The test conditions for the values specified are asfollow$ unless specified otherwise.
• Temperature: 70 0 e
• Supply voltage ~t;ions
The timing fOtthe ac parameters that fonciware measured with a lOO-pF capacitive load on each of
the output~.
FIgUres 15 and 16 shOW' the ac~i.m,i,~ fo!:, th~~Mls\1:$~during IT bus transactiq,ns whell'the BCD
is operating as a slave. Figure 15 is a read andintettupt acknb~~~transactiOll diagram. Figure 16
is a write transaction diagram. Table 11 lists the tiining ~rileters fOr the symbols shown in the
figures.'
DAL<31:00>
====>
~
"1"
~
0
J,...----.·. ·.IJ.'~"Obsl
.
......j
AS
ADDRESS
tAASn
tDSHW
J
.I
;1
DA),A')f""t:ri'}~~"-
~
r.t.o...S.o.
Vr-,,-"';"
OtooI.....
'al
tDSASr.·
\J______J1r - --
~NSD~
tNHD~ ~
I
----------~---~-------------~
'-1 W
\\\Nsf'·',
I
CS<2:0>
BM<3:O>
I
II
~-------------------------I~
l..tBMA~1
II
===x=:J4
I 10
\
' ' ' '-VlT
ffl
Figure 16· VAXBI 78733 Slave II Bus Write Transaction Timing
Table 11· VAXBI 78733 Slave n Bus Signal Timing Parameters
Symbol
Definition
Requirements (os)
Min.
t AAs
Address setup time to AS assertion
20
tASA
Address hoid time after AS assertion
20
Status hold from AS negation
t ASSH
t ASSZ
'1/
t ASWR
.
0
Sta'ttlshighiinpedance frOm AS negatidn
WR, BM<3:0>, CS<2:0> hold time from
40
0
AS negation
tAZI>A
Address high impedance to iSS (read-only)
t BIilAS
BM <
tooDS
Write data setup time before DS assertion
+184
3:0 > setup time before AS asse;tion
Confidential and Proprietary
Max.
0
20
0
·Y.'.'."'''-.
·ft.;~.~
;'~
.
tDJI.A
Read ~ta setup to IrnY assertion
tDSAS
155 negation to 'AS negation
o
TnsD
55
tDSHW
"", '=~'dea$Sertion width"
,,0
twus
'\\ffi, C~<2:0> setup tim~ll
==x:J4
II
I
~I
ROY
ERR
Figure 17· VAXBI 78733 Master II Bus Read Transaction Timing
4.186
Confidential and, Proprietary
IF
DC)(
I
II
~t.,.';:l}l~iQ
~
ADDRESS·
~tA::::j
J!
N"
os
a
DATA
hi:
rDS~
f'jlj'---
L
J
:~ ~".,. ~ ,;:,;"~:~l~.:~~~
I
~I
· · ...:i ll
T h 0
Figure 18- VAXBI 787JJMasterllBus Write '1!tiiiisaction Timing
;y'
,,>;
-::
Symbol
1abIe 12 • VAXBI 7873) Master n Bus SiaPalTinUng Paramete1'&
Definition
~ts (ns)
Min.
Max.
tAAS
Address setup time to AS assertion
20
Address hold time after AS assertion
20
AS assertion to read data valid (only if slave asserts
data lillY before data valid)
220
AS assertion to data valid
105
AS assertion to DS asse.rtion
120
AS negation to read data high impedance
tASHW
5.0
AS negated width
75
AS asserted width
245
~erits(ns)
Symbol
Min.
AS as,sertion to beginning of'RDY. ERR,
'~mp1ilig window
.
Max.
and RETRY,; '.'
...-
: RDY,ERR,and RETRYhold timefromdea~ertion of AS
.WR, BM <: 3:0 >, CS < 2:0 >hqlptime fromAS negation
BM -:;lo > setup time before AS assertion
70
0
5
2P
135
DBEassertion width
Write data setUp tiineto ill assertion
25
.":Read data s~p tt;"RDY assertion when tosm ori::Un:
parameters are not met
20.
DS negation to AS negation
Read data hold.timeafterDS negation"
5
DSdeassertion to'DBE deassertion
5
0
, OS assertion JO .fel1d.data valid when sla~ as~tt~ lIDY
before data valid
,
'
, /
50
"",,
. Write data hold time from DS negation
OS negation to read data high impedance
10
150
tOSHIII'
~. assertion width
80
DAL < 31:00 > three-state to i5BE assertion
t\lVJlAS
4~188
' . .10
:..-p;.;.
WR, CS < 2:0 > setup time before AS assertion
Confidential and Proprietary
0
20
-
Preliminary
VAXBI18133
Figure 19 shoWs the DMA request and grantsignl11 timing when the Ben requests the use of the II
bus. Table l3lists the timing parameters.
\~I-
\"------.II---"..-.JV
1;"""'0-1
II--------JV
H
tOROZ
(1"'------11
----(.
/1
HIGH-Z
HIGH-Z
.
.
I
I
H
J!~------~'_ ~~---H-IG-H--Z
III ~
tASORH
_H_IG_H_.Z____
os
OBEL HIGH·Z
)...- - - - - - tORDZ
__- - - - - - - - - - - -
,r-----.\. J
-----'
/I
I . .\:" ',---------
_
. tDRDZ.
HIGH-Z
".
Figure 19· VAXBI 78733 DMA Request and Gran~Signal Timing
Table 1.3 • VAXBI 78733 DMA 'franS84:-tionT'Jntins Parapteters
Symbol
Requirements (ns)
Min.
Max.
Definition
DMR deassertion to .output high impedance
DMRhold time from ~. assertiQn "
t DGASO
DMG assertion to AS assertion
DMG deassertion to DMR assertion
50
o
210
o
Confidential and Proprietary
----~~-'--~--------------·---~_Zi
4-189
d
......
_
.... _"'.,." ..
L'IIIilIOlIlbIW~~~"OS ......!
VAXBI78733
Figure 20 shows the signal timing fordata transfers to and from the retry address latch (register).
Thble 14 lists the timing parameters.
--IX!
DAL<31:_0>
__
~'__ __
l
VALID DATA
r,,,,, .,:l"
y'-- \'--_---'V
..I"
I...
tRLSLW
-I
tRLSHW
DATA INPUT
DAL<31:0>
----c~
RWE- - ~\J'_r_R_LO_D_~_1
VALID DATA
1-----
) ...
______-J)'Irl"-tR-L-OD-Z---'---------
DATA OUTPUT
Figure 20· VAXBI 78732 RettyAddress Latch Input/Output Signai Timing
Table 14· VAXBI 78733 Retry Address Latch Input/Output Timing Parameters
Symbol
Definition
Requirements (ns)
Min.
Max.
t DSRLS
Data setup to RLS assertion
20
t DHRLS
Data hold after RLS assertion
20
tRLSHW
RLS deassertion width
100
t RLSLW
RLS assertion width
100
tuoDO
RillE assertion to valid
60
tRLODz
RillE assertion to data high impedance
50
4-190
Confidential and Proprietary
• Features
• Custom.l4·pin DIP bipolar integretedcircuit
• Drives 16 clock receivers distributed
over amaXl1IIt1ni1.524 meters ofetch
• Single 5-V power supply
• Differential ECL drive outputs to both BI TIME + /- andJ~lPBASE+I-:• Uses an externally applied 40-MHz crystal oscillator input
• Provides TTL outputs and differential ECL outputs
. Description
The VAXBI 78701 clock driver isa custom-built 14-pin DIP bipolar integrated circuit (Ie) that
serves as the clock source in VAXBI systems. The clock driver is designed to drive 16 clock receivers
distributed over a maximum 5 feet of etch. The device requires only a 5 Vdc operating voltage.
Figure 1 is a functional diagram of the clock-driver. .
GND
TTL Vee
40 MHz
TTL
2
3
14
>
ECl Vee
81 TIME +
20MHz
TTL
10MHz
TTL
4
BI TIME-
5
3-BIT
SYNCH
ECl
COUNTER
11
Ql
OUTPUT
ENABLE
81 PHASE +
BI PHASE_
5 MHz
TTL
6
a
GND
EClVcc
Figure 1 • VAXBl78701 Clock Driver Logic
Confidential and Proprietary
4·191
VAXBI7810t
The circuit provides di£fe~ntialECL drive Qutputs and TTL outputs from an externally applied 40MHz crystal oscillator. The ECL outputs drive both VAXBI bus BI TIME +/ - and BI PHASE + /inputs. The TTL outputs are not recommended for use in a VAXBI system.
The VAXBI 78702 clock receiver must be used with each VAXBI clock driver source to provide the
proper VAXBI clock receive function if the driving source of theVAXBI clock is also a VAXBI node.
The clock driver must be at the electrical beginning of the bused clock etch lines.
An output enable included with the device must be used if more than one node can be installed into
the drive slot of the VAXBI bus. Only one source of docks in VAXBI systems is allowed and the first
slot should be wired to enable this device.
Pin and Signal Descriptions
The input and output signals and the power and ground connections of the clock driver are shown
in Figure 2. Table 1 provides a summary of the input and output signals.
>
GND
>
ECl Vee
TTL Vee
61 TIME+
TTL 4{) MHz
61 TIME->·
TTL 20 MHz
ECl OUT ENA
TTL 10 MHz
61 PHASE+
TTL 5 MHz
BIPHASE-
GND
ECl Vee
TOP VIEW
Figure 2 • VAXBI 78701 Pin Assignments
Table 1 • VAXBI 78701 Pin and Signal Summary
Pin
Signal
Input/Output
Definition/Function
3
40 MHz TTL
input
40 MHz TTL-A 40-MHz square-wave input from
the clock oscillator.
4
20 MHz TTL
output
20 MHz TTL-A 20-MHz square-wave output.
5
10 MHz TTL
output
10 MHz TTL-A lO-MHz square-wave output.
6
5 MHz TTL
output
5 MHz TTL-A 5-MHz square-wave output to logic
functions.
11
ECLENA
input
EeL enable-Enables the EeL outputs when at a
high level. Can be connected to EeL vce.
4-192
Confidential and Proprietary
Pin
Input/Output
DefiOition/FunctiOn
9
10
BIPHASE BIPHASE +
outputs
BI PHASE +/ - (5 MHz)-Differential EeL outputs for the phase signal inputs to the VAXBI 78702
clock .receiyer and VAXBI bus.
12
BITIMEBITIME +
outPUt '
'BI TIMEr-/:- (20'l\4ifz)-.;. Differential EeL outputs
13
2
TIL Vee
TTL voltage-Pawer supply Voltage to TIL logic.
8,14
EeL v cc
EeL voltilge-PoWer supply voltage to EeL l~gic.
1,7
GND*
for the time signal inputs to' ~V'Ax.BI787£)2 clock
ileCtivetandVWI bus: ,
Ground":-COmn'l
"
'.
"
,
':
13I'jIMe'+
,:
XTAL
OSCILLATOR
VAX81
40MHz
78701
,CLOCK
DRIVER
aiTIME--
:'
c
'
81 PHASE:+,
'
','
V
,
.:
al PHASE-
Figure 3· VAXBI 78701 Clock Driver with VAXBI 78702 Clock &ceiver System Configuration
4-193
PreliminaJ:y .
VAXBI78701
Table 2 lists the relationship of the inputandoutppt levels ?f.the VAXBI 78701 clock driver. The
.
states of the inputs and outputs at startup time are not defined.··
. Table 2 • VAXBI 78701 Input and Output Signal Levels
TIL Input 'ITL Outputs
40 MHz
20 MHz 10 MHz
'MHz BIPHASE
L
L
L
L
H
L
H
L
H
L
L
L
H
L
H
L
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
H
L
L
H
H
H
H
L
H
L
L
H
L
L
L
H
L
H
H
t
H
L
L
H
L
H
H
L
L
H
L
H
L
H.
L
H
H
H
L
H
L
H
L
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L
H
H
H
L
H
L
H
H
H
H
H
L
H
L
H
ECLOutputs
+ BIPHASE- BITIME + BITIME-
• Specifications
The mechanical, electrical, and environmental characteristics and specifications for the clock
driver are described in the following paragraphs. The test conditions for the electrical values are as
follows unless specified otherwise ..
• Power supply voltage (Vcc): 5.0 V ± 5%
4-194
Confidential and Proprietary
-
Mechanic:aI ~ ...
The physical dimensions of the7870114-pin CERDIP package are contained in Appendix E.
Absol,!te M"~ ~tinp
Stresses greater than the absolute maximum rating~may cause permanent dllJllBg¢ to the device.
Exposure to the absolute maximum ratings for extended periods may ltdverse1y affect the
reliability of thedevice:
• Power supply vol~ (Vcd: 7.0 V
.. Inputvoltage'l1pplied: -1.5 Vto 7.0 V(40 MHz TTL)
• Output voltage applied: 3.0 V to 7.0 V (Differe~clal :ECL} '.
• TTL output applied current: 40 rnA (low state)
!}
.
';
Recommended Operating Conditions
.. Power supply voltage {Vee}: 5 V ±5%
• Input frequency: 0 to 50 MHz
• Power dissipation: approximataly 500 mW (no load)
dc:Ek!ctrical Charaeteristks
The de electrical parameters of the clock driver £or, the: operating voltage 4l:d·remperature ranges
specified and when at thermal equilibrium are listed in Table 3 and 4. All de specifications,
including capacitanCe values, pertain to .packaged par;a,1'a~le 4 liSts theTTI.,Jnput and ouqrll~
parameters and Table 5 liSts the ECL input andputPUt p~eters. Fjgtm:4s~ the de t~st
circuits use for the measurements. The ECL output loacl ~~tor values uSed test· this device are
not the same as theVAXBlclock termination values. " • '
to
Confidential and Proprietary
-----------------.----.--.
..........--,---~..-.,.-".........--,---~---.-.-.--..-~.-"..•-~-----~---~----.----'
-
VAXBI7s1ot
Preliminary
Table .3 • VAXBI 787Ql de TTL Input and Output
Parameters'
.
,~
Symbol
Parameter
TestCot'lditions
Unit
Vm
High-levd
input voltage
Vec =5.'25 V
V
Pin 3
Vn
1m
Low-level
input voltage
Vee = 5.25 V
High.level
input current
Vm=2.7V
0.8
V
Pin 3
!-LA
Vee=~.25V
Pin 3
In.
Low-level
input current
V1L "" 0.5 V
Vcc =5.25V
-2
rnA
-1.2
V
Pin 3
VIC
Input clamp
voltage
1.. =-18 rnA
Vcc =5.25 V
Pin 3
IlNav
High·level
input current
breadown
C..
Input
capacitance
. VIH =7 V
Vcc =5.25V
Pin 3
Vrn=4 V
High-Ievd
output voltage
10 = loa max.
Vee =4.75 V
Pins 4-6
VoLt
Low-levd
output voltage
10=20 rnA
Vee =4.7:' V .
. Pins 4·6
loa'
High-Ievd
output current
Vo=Voa min.
Pins 4-6
Vee ==4.75 V
Low-level
Vo=O.5V
Vcc=4.75 V
Pins 4-6
20
Vee ==5.25 V
-25
output current
lol
Icc
Short circuit
output current
Power supply
current
~
12
pF
Pin 3
VOHI
loLl
100
204
V
-1000
rnA
-150
rnA
100
rnA
Pins 4-6
Vec =5.25 V
No load
Pin 2
'Testing either (VOH and VOL) or (Iou and IoL) satisfies these requirements.
'TTL outputs shorted to GND, EeL outputs shorted to Vee, or eithl=r outputs open a maximum
duration of 5 minutes. los is current into the output pin when the input conditions cause the
outputs be a logic one before the application of the short.
4-196
ConFtdential and ProprietarY
VAXBI78701
1able 4 • VAXBI 78701 de EeL Output Parameters
Symbol
Parameter
Test Conditions1
Requirements
Mm.
Unit
Max.
VOD1.2
Differential
output voltage
Load A
VOR
High-level
output voltage
Load A
3.5
4.3
V
VOL
Low-level
output voltage
Load A
2.8
3.5
V
Iol
Output disable
current
Voz =4.5V
LoadB
VORS
High output
stress voltage
Load A
Replace 1100 with 600
3.5
4.3
V
VOLS
Low output
stress voltage
Load A
Replace 110 0 with 60 0
2.8
3.5
V
Coz~
Disabled output
capacitance
6
pF
700
mV
50
!-!A
tPins 9 and 10, U and 1.3 for all measurements
2VOD is 318 rnV as measured in Figure 4 across points A and A' of EeL load.
)Perform with pin 11 grounded, pins 1 and 7 =GND, and TTL clock input (pin 3) .hi~. Also
performed with pins 2,. 8, and 14 grounded and at 5.0 V.
4Difference in output capacitance (Coz + minus Coz - ) =2 pF
Confidential and Proprietary .
-----------..-- ._- --
4-197 .
__
. ._-_._-------_._----
ml.a
Preliminary
VAXBI78701
Vee
+'
8
2
14
11
13
3
12
l'IH"IL
4
VAXBI
78701
V,H. V,L
5
6
10
VOH' VOL
VOH' VOL
9
7
LOAD A
Vcc
1
2,8,14
VAXBI
78701
9,10,121-_ _-0--,
OR 13
VOZ4.SV
1,7,11
LOAD B
Figure 4 • de Test Circuits
4-198
Confidential and Propcietary
Preliminary
ac Electric:a1 Charaet.eristies
The timing symbols and waveforms for the propagation delays are shown in Figure 5. The timing
symbols and waveforms for the output signals are shown in Figure 6. Table 7 lists the symbols and
parameters. All measurements are made when the chip is at thermal equilibrium. All ac
specifications, including capacitance values, pertain to packaged parts and apply when all outputs
are loaded and switchedsiniultaneously. The ac t~t circuit configuration is shown in Figure 7 and
TTL and EeL load circuits are shown in Figure 8.
NOTES:
1.
LOAO OUTPUTS PER FIGURE 8
2.
INPUT RISE AND FALL TIMES eQUAL loOns
Figure)· VAXBI {87m
Propagation~lay
Confidential!'OdProprietary ,
Timing
4-199
...
Preliminary
VAXBI78701
A
PINS
9(121
B
PINS
10(131
tSKWl = GREATER OF [A -BJ OR [B -A) ABSOLUTE VALUE
A
PINS
_ _ _ _--J
9(10)
B
PINS
------+--'
12(13)
tSKW2
tSKW2
tSKW2 = GREATER OF [A - BJ OR [B - AJ ABSOLUTE VALUE
Figure 6· VAXBI 78701 Output Signal Timing
'Thble 5· VAXBI 78701 ac Timing Parameters
Symbol
Requirements (ns)
Parameter
Min.
10
Propagation delay
-------
TTL output rise time (VOL max. to Von min.)
8.0
TTL output fall time (VOH min. to VOL max.)
8.0
Single differential output skew
1.0
Differential output to output skew
1.0
Propagation delay
4-200
Max.
12
ECL output rise time (30% to 70%)
0.5
2.5
ECL ouput fall time (30% to 70%)
0.5
2.5
Confidential and Proprietary
-
VAXBI78701
2
4
8 11 14
5
6
VAXBI
78701
IN
OUT
9
10
12
13
Figure 7· VAXBI 78701 ac Test Circuit
PINS 0
4,5,6
I
500n
"I.fV'\j _ _ _
"
TO
son SCOPE
;;;50 PF
TTL lOAD
A
Bon
PINS ().
10,13
PINS
9,12
0
L·
[
..
'\N'v
6 IN
TO 50n SCOPE
-I
eon
""""
!..f~'F
,A
TO 500 SCOPE
Eel lOAD
Figure 8· VAXBI 78701 ac Load Circuits
Confidential and Proprietary
,---_._------,----,-----,
4-201
• Features
• Custom bipolar 16-pin integrated circuit used by all VAXBI nodes
• Receives the differential ECL BI Time + L:~
inputl
Bus data/address lines-The information ontheseJines.is
latched by the ,JjS.YNC .sigrull. frolP. the pus." .~ndust;9to
select one or m(lre of the 8-bit registers connected to the
S'EI:1J, ~, 'S'E'I:4' and SEL"'b lines.
5
BWTBT
inpu~
Write/Byte-Selects a byte or~rdo~tion wn@:the
nPQyT.~i~na1., .is.... asserted:B,,'i'BL . a$serted"" byte,
ir~Tt.tpega~d ... word. The'Gtchei1 output of this sigol!!
is gated with BI50U'l"
a tow:byte· or high-byte
to\select
output.
inpu~
8
9
.. BRPtY
Bus syn~hrqnize-Asser~by the bus master to indicate
tha(ahililttrt;ssis~lithe~OS: 'W'hen ~serted;it disables
all dle' ou~uts extept ·tllel •vectOr· gerrerated· output of
BRPIY.
..
inpu~
Bus datain..,...,Asser~ bY··the;bus.rna$~· tt>e£feetadata
input transaction when the BS"Y'NCsignal isasserted.~ It
generateS the·mrPiY outpufthrough the delay circuit and
the iNWi5 output.
outpUt'
Busreply",--Assertedby":the .slave device· to indicate that
datal$? iWaillible olithc:m5'Atbus or diat the device has
accepted output data from the bus.
Bus da%o~~~~~r.t~!Pr)the ~evice toJ~dicate~h~t
BDOUT
device data~~1'ailabl~on~ ~Jlnes.
. •.
, ... ,
10
GND
input
11
iNWi5
outputl
In word-Asserted to gate the data from a selected ~ter
. to the bus .
U
OUTLB
outputsl
. Out l~-bYte, Out high"bYte+U$ed.U) ~eaQ t4le ~.byte,
high-byte; otboth bytes ofthe write data from the selected
13
OUTHB
14
outputsl
Select decoder 0, 2, 4, and 6 output lines-Selects a word
register for a data transaction.
16
17
SELO
SEL2
SEL4
SEL6
18
RXCX
outpue
External RC nooe-The value of the resistor and capacitor
network connected to this pin determines the delay of the
15
Ground-Common ground connection
register onto the bus.
".
" ",
'
BR'PIX signal.
Confidentialapd Pl'Qp~etary
4225
...
Pin
Signa]
Input/Output ·~tionIFURCtiolt
19
ENB
input'"
Enabl~-Asserted to enable the SEi::O, SEL 2,SEL 4, and
SEL6 outputs . of the decoder and the adQ.ress term of
BRPLY.
20
Vee
input
Voltage-Power supply dc voltage
'TTL level
2high-impedence
Jopen-collector
4connected to Vee through an 8500 resistor
. Application Infortnation
Refer to the Chipkit Users ManualLSI-ll Bus Interface Chips (document no. EJ-0138 7-92) for general
application information. The Q-bus is an LSI-ll bus .
. Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DCOO} are
descrihed in the following paragraphs. The test conditions for the electrical values are as follows
unless specified otherwise.
• Operating temperature (TA):
ooe to 70 e
0
• Supply voltage (Vcd: 5.0 V ±5%
Mechanical Configuration
The physical dimensions of the DC004 20-pin DIP are contained in Appendix E. The materials and
construction of the molded DIP are defined in Digital Specification A-PS-2100002-GS.
Absolute·Maximum Ratings
Stresses greater thanthe absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
• Supply voltage (Vee): 7.0 V
• Input voltage (VI): 5.5 V
• Storage temperature (Ts):
4·226
-65°e to 150 0 e
Confidential and Proprietary
Recommended Operating.Condidons
• Supply w!~ Ned: 4.75 V (minimum), 5;0 V (normal), 5.25 V (maxiinum)
• Supply current (led:
.120 mi\ (maximum)
• Free-air temperature: O°C to 70°C
• Relativehumidity: 10% to 95% (noncondensing)
de Electrical Characteristics
The de elec~rical charac~ristic~ of the D(:@4for the Operat~v91~~and temperature ranges
specified are listed in Tables 2 through 4. Table 2 lists the d~ ,$pecmcati(?l1s £Or the TTL input and
outputs that do notconnect totheQ-pus P\ls.J.lll>Je >~~$.tI1~!4c ~~~ications for tile highimpedance receiver inputs from the Q-bus bus. Ta.ble 4 li~ts thi de specifications for'the()pencollector driver ou~uts that connect to the Q-bus. Refer to Appendix C for test circuit
configurations listed in the tables.
• Note: Pin 18 (RXCX}o£ the DCOO4must be connected to Vccthrough a l-kn ±5% resistor for
performing all the de tesfs'sMwn inth~teSt~tdiagramsin:A!ppendix C.
Table 2·· DCOO4 TTL Input and'OQtput. p;p..meters
Pammeter
Symbol
Test
Re~ts·
Condition
Min
Vru
Low-level
input voltage
Va
Input clamp
voltage
VI
Vee=4.75V
11 =-18 rnA
High-level
output voltage
VOH
Vec=4.75
Io=-l.OmA
Low-level
VOL
Vee =4.75 V
Io=20rnA
Input current
atmaxinlum
input voltage
II
Vee =5.25 V
VI =5.5 V'
High-level
input current
1m
Vce=5.25V
VJ=2.7V'
Circuit
C1.C2
0.8
V
Cl,C2
-1.2
V
C3
V
C1
0.5
V
C2
1.0
rnA
C4
IlA
C4
2.7
Confidential and Proprietary
..
V
2.0
High-level
input voltage
output voltage
Units
Max
50
_a
Parameter
Low-level
input current
Short-circuit
output current
00004
Symbol
IlL
los
Test
Condition
Requirements
Min . Max'
-40
-100
Test
Circuit
-0.70 mA
Vcc =5.25 V
VI = 0.5 V
Vcc =5.25V'
Units
mA
C5
C6
Icc
Vee =5.25 V
120
rnA
C7
'Limits for pin 19 are: 11 = lAmA, IH =-2.25 mA (minimum) and -3.85 mA (maximum), IIL =-4.5
Supply current
mA (minilnurn) and ':'8.0 mA(maximuin).
.
'Not more than one output shall be shorted at It time and the duration of the short shall not exceed
1 second.
.
.
Table.) • DCOO4 High-impedance Bus &ceiver Parameters
Parameter
Symbol
Test
Condition
High-level
input voltage
VIH
Vee=4.75V
Vce =5.25V
Low-level
VIL
Vce=4.75 V
Vee=5.25 V
input voltage
Input clamp
voltage
VI
High-level
input current
1m
Low-level
input current
4-228
Requirements
Min
Max
Units
Test
Circuit
V
V
Cl,C2
V
V
C1,C2
-1.2
V
C3
40
40
l!A
l!A
C4
-10
~
~
C5
C5
' 1.53
1.70
Vee =4.75 V
1.30
1.47
11 =-18 rnA
IlL
VI =3.8 V
Vcc=OV
Vcc =5.25 V
V1=OV
Vcc=OV
Vcc =5.25 V
Confidential and Proprie1;ary
-10
DCOO4·
Table 4 • DCOO4 Open-conector Bus Driver Pamtneters
Parameter
Symbol
'fest
Requiremen~
Condition
Min
Output reverse
current
loR
Vee=4.75 V
VoH =3.5 V
Low-level
VOL
Vee =4.75 V
L... =70mN
"'k= 16 mA'
1,.. = 15 rnA3
output voltage
Units
Max
25'
0.6
0,5
0.5
I-!A
V
V
V
Test
Circuit
Cl
C2
165 I-!A for pin 18 (RXCX).
2Applies to pin 8 only (BRPLY).
}Applies to pin 18 only (RXCX).
ac Electrical Clwacteristics
The input and· output signal timing for the DCOO4 ·is shown in Figure 3. Thble 5 lists the
specifications for the values referenced on
3. The open-collector and TTL output load
circuits referenced in Thble 5 are shOwn in Figure 4. Refer to Appendix D for the standard input
voltage waveforms and for the signal propagation delay measurements.
Figun;
Confidential and Proprietary
4-229
#:!/%%:7;@,~
BDAL<2:0> 2/%a25 Mlt+5MIW
ENBWM~FN JrNW~##~·
I
I
I
-l~F
WJ#~
~000'#~
I
I
I
I
ImmJ'f
15 MIN-.l
I
--ll
b
VECTOR - -_ _ _ _ _ _ _
I
I
I
I
I
-i F
'15
RXCX H
I
-!
-J
r:____________
t16 ...
-TIME REQUIRED TO DISCHARGE RX CXFROM ANY CONDITION ASSERTED
NOTE
TIMES ARE IN NANOSECONDS.
Figure 3 • DC004 Signal Timing Sequence
4-230
/~
Confidential and Proprietary
= 150 ns.
-
DQ)04 . .
4;
TEST
P()tNT
VCC
VCC
R2
00
FROM.
oomrr
.
FROM
OUTPUT
TEST
""'"
12°OPF
ALL
DIODES
FD777
CONDITION 1
R2 = 280n
C2=15pF
CONDITION 2
R2= OPEN
C2 = 160 pF
LOAD A OPEN-COLLECTOR CIRCUIT
LOAD B TIL CIRCUIT
Figure 4 • DC004 Output Load Circuits
Table 5 • DCOO4 Signal Timing Specl&ations
Timing
Reference
Signall
Signall
Output Tuning (ns)
(Load/condition) (Load/c.ondition) Asserted
Negated
Min
Max
Min
Max
T5,T6
SELO (B/2)
SEL2 (B/2)
SEL4 (B/2)
SEL6 (B/2)
BSYNC
T9, TlO
OUTLB (B/2)
OUTHB (Bt2)
Tn, T12
iNWD(B/2)
...,
15
40
40
40
40
5
30
30
30
30
BOOUT
5
5
30
30
5
5
30
30
BDIN
5
30
5
30
15
15
15
Confidential and ProPrietary
5
5
5
Timing
-
Signall
Signal!
Reference
(Load!condition)
(Load!condition)
DCOO4
T13, T14
OUTLB (B/I)
OUTHB (B/l)
INWD (B/l)
VECmR
OUTLB (B/I)
OUTRB (B/I)
INWD (B/l)
VECTOR
T15, T16
RXCX (A) 2
OUTLB
OUTRB
INWD
VEcmR
Output Tlllling (os)
Asserted
Negated
Min
Max
Min
Max
20
20
20
30
300
60
60
60
70
400
-10
-10
-10
0
-10
45
45
330
430
0
45
10
50
10
50
'Refer to Figure 4 for load circuit configurations.
'Pin 18 connections: Rx=3.30n 5%, Cx= 15 pF 5%.
}Pin 18 connections: Rx=4.64 kn 5%, Cx=220 pF 5%.
4-232
Confidential and Proprietary
45
45
45
• Features
• Used with the nc003 and DC004 circuits to.implement a pl'Ogram control dM~int¢rfiace.
• Used with the ncoo,;, DC004,DC006, and DCOIOch:l::uits toimplementa directlPemory access
interface.
• Functions as a bidirectional buffer between the device logic and ootrlputerbus.
• Includes comparison circuit'£~r device address selection.
• Includes constant generator for interrupt vector address generation.
• Includes Q-bus drivers and receivers .
. Description
The DC005 4-bit transceiver, contained in a 20-pin dual-inline package (DIP), implements lowpower Schottky technology and functions as a bidirectional buffer between a data bus and
peripheral device logic bus. It includes a comparison circuit for device address selection and a
constant generator for interrupt-vector addres$get1etatiOn.~tProvides high-impedance inputs and
high-drive, open-conector outputs to allow direct connecti09 toa computer data bus structure. The
bidirectional device port includes TTL inputs and thr¢e-state driver outputs. Figure 1 is a
simplified logic diagram of the DC005.
.
Figure 1 • DeaD5 Simplified Logic Diagram
4-233
-.
DCOO'
Three address select inputs (ian be configured by jumper leads to enable a comparison to he made
between the jumper connections and three bus inputs. An open-collector MATCH output allows
several transceiver outputs to be gated to form a composite address match signal. The address
jumpers can also he configured to disable the address match condition. The address match
condition is controlled by an input line that can enable or disable the MATCH output.
Three vector inputs can also be configured by jumper leads to generate a constant vector value that
is transferred to the computer bus. The vector inputs directly drive three of the bus lines to override
the function of the control lines.
Two control signals are decoded to select the receive data and transmit data operation and to disable
the operation of the device .
. Pin and Signal Descriptions
This section provides a brief description of the input and output signals and power and ground
connections of the DC005 20-pin DIP. The pin assignments are identified in Figure 2 and the
summarized in Table 1.
JA1
JA2
Vee
JA3
MATCH
DATO
DATl
JV3
JV2
JVl
MENS
susn
GND
IltJS1
TOP VIEW
Figure 2 • DC005 Pin Assignments
4-234
Confidential and Proprietary
Table 1 • DCOO; Pin and Signal Summary
Pin
Signal
8-12
BUS < 3:0 > input1/outputl
. Input/Output
6,7,17,18 DAT < 3:0 > inputs/outputs}
16-14
]V < 3:1 >
inputs4
De£inition/Function
Bus 3-0 lines-These lines are bidirectional and connect to the BDAL lines of the Q-bus. A low is equal to 1.
Data 3-0 lines-These lines transfer the inverted data
from the bus to the deviceinreceive mode and from the
device' to the' bus infranswt:tnode: . During· disable
mode, the outputs are ata highanpediUlce.
Vector jumpers'j·l::-theiSe'lines directly ·drive the
BUS < 3:1 > lines. A groul.ld connection or an open
jumper pin causes .an open condition on the corres·
ponding bus pin if the'XMIT signal is asserted. A high
(5 V) connection to thejumpeq,irlwill caUse aone(low')
. on the 'correspOnding buspiit1'F.teBUS <0> line is
not controliedbya jutrtper.'
.
Match enable-A low input wW e~ble the.MATCH
.output when.a matchO(;CUI:s,~n the .. level of
BUS < 3:1 > signals~1:ld the address jumpers JA3
through JA1.
3
MATCH
outpuf
Address match-This output.. is. open when a match
occurs between the level of the BUS,<3:1x.lines.and
the levels ~by~he address i persJV3 through
.JV 1. The output is low when no match occurs.
um
19,2,1
JA < 3:1>
inputsS
. Address jumpers-When connected to .ground, these
pins allow a match to occur with a one Qow) on the
corresponding BUS<3}1 > .Iines;Whert these lines are
nof connected, a.~tCh. can occur witha. zero (high)
level on the corresponding bus lines. When connected
to 5 V, the-corresportding
a<:1clresS bit is disconnected:
.
.. ,
.
5
XMIT
inputs)
4
REC
Transmit/Receive·control-ControIs:the operation of
the transce;.vel' as: follOW'$(,
REC XMIT Function
o
0
Disable(open): BUS and DAT lines
o
1
Transmit: OAT fuBUS lines
1
0
Receive; BUS to DAT lines
1
1
Receive: BUS to DAT lines
20
Vee
input
10
GND
input
"
-,
-
Ground~Common ground
reference
'high-impedence
'open-collector
'TTL level
4TTL level with pull-down circuit
'three-state
Confidential anP::Proprietary
4·235
• Application Information
Refer to the Chipkit Users Manual LSMl BtJs Intetface Chips (document no. £]-01387-92) for general
application info~mation_ The Q-bus is an 1.,SI-11 bus .
• Specifications
The mechanical, electrical, and .environmental characteristics and specifications for the Dca05 are
described in the following paragraphs. The test conditions for the electrical values are as follows
unless specified otherwise.
• Supply voltage (Vee): 5.0 V ±5%
Mechanical Configw:iuion
.
The physical dimensions of the DCOO5. 20~pin DIP are contained in Appendix E. The materials and
construction of the molded DIP are defined in Digital Specification A-PS-2100002-GS.
Ab~lute·Maximum Ratings
Stresses greater tharithe absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
• Supply voltage (Vcc): 7.0 V
• Input voltage (VI): 5.5 V
Recommended Operating Conditions
• Supply voltage (Ved: 4.75 V (minimum), 5.0 V (normal), 5.25 V (maximum)
• Supplycu~ent
(led:
120 rnA (maximum)
• Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics
The dc electrical characteristics of the DC005 for the operating voltage and temperature ranges
specified are Iisted in Tables 2 through 6. Table 2 lists the dc specifications for the TTL input and
outputs that do not connect to the bus. Table 3 lists the dc specifications for· the high-impedance
receiver inputs from the bus. Table 4 lists thedc specifications for the open-collector driver outputs
that connect to the bus .. Table 5 lists the de specifications for the three-state jumper lead
connections inputs used for the address comparison logic. Table 6 lists the dc specifications for the
TTL jumper leads connections used to select a vector address. Refer to Appendix C for test circuit
configurations listed in the tables.
4~236
ConfidetitialllildProprietary
•••
DCOO;
18bIe2 -OCOOS TTL InputandcOutput PtmuDeters (nonbus)
Parameter
Symbol
High-level
input voltage
VIH
Low-level
input voltage
VII.
Input clamp
voltage
VI
Vee =4.75 V
11 =-18 rnA
High-level
output voltage
VOH
Vce=4.7V
Io=-1.0rnA
Low-level
output voltage
VOL
Vcc=4.75V
Io=20rnA
Input current
at maximum
input voltage
II
Vcc =5.25 V
V1 =5.5V
High-level
input current
1m
Vcc =5.25 V
VI=2.7V
Receive:
Transmit:
Low-level
input current
IlL
Test
Condition
Requiretnents
Min.
Max.
Units
Test
Circuit
2.0
V
G1,C2
0.8
V
Cl,C2
-1.2
V
C3
V
Cl
0.5
V
C2
1.0
rnA
C4
3;65
.
C4
100
pA
50
IlA
C5
Vcc =5.25V
VI=O,5Y
ReceiVe: -
-2.2
rnA
Transmit:
-1.1
rnA
Short-circuit
output current
los
Vec =5.25VI
Supply current
Icc
High-impedance
state output
current_'
10
-40
_-100
mA
C6
Vee = 5.25 V
120
rnA
C7
Vee =5.25 V
Vr =3.65 V
VI =O.5 V
100
IlA
-0.36 rnA
INot more than one output shall be short circllitedat atime and the duration of the shott shall not
exceed 1 second.
'Off state, DAT < 3:0 > pins only.
Confidential and Proprietary
_---
---------------_._-_._---------------------_._---_._---------_..
4-237
Parametet
Tablt; 3. " ncoo;. HiBh·itnp~e Bus Receive~Parame~
S,mbol .Test
Requirements
Units
Max.
.- Condition
Min.
High-level
input voltage
Vm
Vee=4.75 V
Vee =5.25 V
Low-level
input voltage
VII.
Vee=4.75 V
Vcc=5.25V
Input damp
voltage
VI
I1 =-18mA
Vee =4.75 V
High-Ie",el
input current
MENB
IIH*
Vr =3.8V'
BUS
Low-level
input current
IlL
1.53
1.70
1.30
1.47
-1.2
Test
Circuit
V
V
Cl,C2
V
V
Cl,C2
V
C3
C4
Vce=OV
Vee =5.25 V
Vce=OV
Vee=55V
40
40
65
65
Vr =O.5 V
Vec=OV
Vce=5.25 V
-10
-10
~
~
.~
~
C5
~
~
*Indudes open-collector leakage current on bus
Thble 4 " DCOO5 Open-collector Bus Driver Parameters
Parameter
Symbol
Test
Condition
Output reverse
current*
loH
Vcc=4.75 V
VOH=5.25 V
Low-level
output voltage
MATCH
BUS<3:0>
VOL
Vcc=4.75 V
Requirements
Min.
Max.
I.lnk=8 rnA
lsink=70 rnA
loink= 16 rnA
*Pin 3 only (MAtCH). For BUS < 3:0> pins, referto IIH Table 2.
4-238
Confidential and Proprietary
25
Units
Test
Circuit
~
Cl
C2
0.5
0.8
0.5
V
V
V
Parameter
High-level
DeOO'
Table 5 • DC005 TTL Three-state Address Input Parameters
S~bol
Test
Condition
Units
'fest
CimUt
V
Cl
0.3
V
Cl
2
V
Requirements
Min.
Max.
4.75
Vm
input voltage
Low-level
input voltage
V1L
Open-circuit
input voltage
VOP
4.75 5.25
. 18ble6 • DCOO5
Parameter
SymboJ
1
rTLveetor Input Parameters
Test
Condition
. Requirements
Min.
Max•.
Test
Circuit
V
Cl
0.8
V
Cl
Vee=4.75V
I1=-18mA
-1.2
V
C3
1IH
Vcc = 5.25 V
V.=2.4 V
1.2
V
C4
Low-level
input voltage
forcing current
Vu
Vcc=4.75V
11 =0.1 rnA
0.8
V
C4*
Input current
at maximum
input voltage
IlL
Vcc=5V
V1=OAV
High-level
input voltage
VIH
Low-level
input voltage
VJL
Input clamp
voltage
VI
High-level
input current
2.0
Units
50
200
C5
*Remaining inputs open.
ac Electrical Charaeteristics
The input and output signal timing parameters for the Dea05 are grouped by functions and shown
in Figure J. Figure 4 shows the load Circuits used to meas\l1'e the sign.al titningfor the open-collector
and three-state outjJuts. FigUre 5 shows the three-state voltage waveform parameters. Refer to
Appendix D for the standard input and output voltage waveforms parameters used to measure
propagation delay.
Copfidential and Proprietary
4-239
...
DCOO5
TRANSMIT DATA TO BUS
<
JI
XMIT _ _ _ _ _ _
-i I--
j.--s
5 TO 30 ns
TO 30 ns
REC(GROUNDI--------------------------------------------------------
I
BUS - OUTPUT
5 TO 25 ns
OAT-INPUT
I
---l
----.......
~I
foe- --I
foe- 5 TO 25 ns
I
____~I----~---?----
RECEIVE DATA FROM BUS (BUS INITIALLY HIGH)
XMITIGROUNDI __________________________________________________
REC
OAT-OUTPUT
BUS-INPUT
-----~
=--I
1---0
TO 30
HI-Z - - .
____
nsrI ____....._--I....;..:__il--_~0:..T~0:..3::0:..:.::ns
I
-;o.f.
~B TO 30 ns
- - - - - r - - - - i_________________________
__________
l
~
~
~
~
HI-Z
______
RECEIVE DATA fROM BUS (BUS INITIALLY LOW)
XMIT (GROUND) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
REC _ _ _ _ _~I
--I
OAT-OUTPUT
foe-- 0 TO 30 ns
---l
...I'
HI-Z _ _ _
\.::6 TO
---1
r--O
TO 30 os
!
30 ns
HI-Z
I
BUS-INPUT - - - - -.....,
VECTOR TRANSFER TO BUS
I
~I
----I
JV1-JV3 _ _ _ _ _ _
1--20 ns MAX
--tool
1---20 os MAX
BUS-OUTPUT------------~~l~________________________~1
ADDRESS DECODING
-J)(~__~~-------------------------I
1--10 TO 40 ns
MATCH __________~--~I------_-~~-~----~X~------~--_+I-------
BUS-INPUT ________________________
--oot
I
I-- 5 TO 40 ns
I
RECEIVE MODE LOGIC DELAY
XMIT
REC _ _ _ _ _~(
--l
I---- 40 TO 90 ns
J
H~ ----------------------~
OAT <3:0> (OUTPUTI
Hgure 3· DC005 Sif!/lol Timing Sequence
4-240
--I
Confidential and Proprietary
1--10 TO 40 ns
DCOO5
RI
ALL
OIOOES
= 2K
=FD777
~S2
=60 n FOR PINS 8, 9. 11. 12.
=476 0 FOR PIN 3.
RI
R1
CI
= 15 pF AT PIN 3.
LOAD B THREE·STATE CIRCUIT
LOAD A OPEN-COLLECTOR CIRCUIT
Figure 4 • DCOO5 Output Load Circuits
------..... - - - - --REC
1.5 V
OAT X
SI OPEN
S2 CLOSED
DATX
1.5 V
OV
SI AND 52 CLOSED
THREE-STATE VOLTAGE WAVEFORMS
Figure 5 • DC005 Three-state Voltage Wave/orms
Confidential and Proprietary
4-241
. Features
• Used with the nc003, DCOO4, DC005, and DCOiO to irriplement a direct memory access
interface.
• Contains two 8-bit binary up counters for word byte count and bus address.
• Implements low-power Schottky circuits.
• Includes read and write control logic.
• Includes comparison circuit for deviCe address selection.
• Two DC006s can be cascaded for 16-bit register implementation.
• Contains internal8-line bus and three-state bus drivers .
. Description
The DC006 word count/bus address logiC, contained tnlil;2Q-pin dual-inline (DIP) package, is
designed for use in a direct memory access. (DMA) dey~jn~erface. The DCOO6 is a low-power
Schottky device that connects to the~·statej()6tpu*softhe nc005 transceiver. The DC006 is
controlled by the DC004 register sel~ the DCOIO dj.rect memory access, and ancillary logic.
Figure 1 is a simplified block diagram of the·DCOO6.
MAX·A
Ci:if.i::
MAX·C
C'N'fiA 0-1----+-+---lii0i
READ
CONTROL
LOGIC
04----/
RD 0 4 - - - - /
RD·A
Figure 1 • DC006 Simplified Block Diagram
Confidential and Proprietary
4-243
...
DCOO6
It includes two separately controlled 8.bitbinary up·counters, onefor word (byte) C9unt and one
for bus address. Each counter can be separately loaded and cleared. The word counter (C counter)
is incremented by a count of one and the address counter (A counter) is incremented by a count of
one for byte addressing and by a count of two for word addressing. Each counter is read separately.
Data from the DCOO6 is transferred to the three-state bus through the internal drivers .
• Pin and Signal De~criptions
TIlls section provides a brief description of the input and output signals and power and ground
connections of the DC005 20-pin DIP. The pin assignments are identified in figure 2 and then
summarized in Table1 . '
-
Vce
soc
MAX-A
S-A
i1i
CLK-A
MAX·C
RD-A
R5
CLK-C
CiiiTiA
1280/F
1 OfF
64 OfF
2 OfF
32 OfF
16 OfF
4 OfF
GNO
8 OfF
TOP VIEW
Figure 2 • DC006 Pin Assignments
4..244
Confidential and Proprietary
-
DC006
Table 1 • DCOO6 Pin and Signal Summary
Ym Signal
InpUt/OutpUt Definition/Function
input
Increment counter A-Controls the least significant bit of the A
counter. When low the A counter is incremented by one. When
high, the least-sig1lllicant bitofthe A counter is disabled and the
count is incremented by two. When two counters are cascaded,
this input shouldJ)e connect~ to ground.
input·
Clock A counter~ The nega'tive edge of this signal increments
the A counter by one or two count~ depending on theCNTIA
level. The CNTlA and LD signals must be stable while the CLK·
A signal is high.
16
CLK·C
input
Clock C counte,r-The negative eclge of this signal increments
the' C counter bY a coup.t of one. The L:O signal· must be stable
while the 'C1':'K-e.signal is high.
2
S-A
input
Select A counter-Selects the outputs and functions of the A
counter during read and write operations as specified in Tables 2
and 3.
19
soC
input
~elect C counter.:-c-Sdects the outputs and functions of the· C
counter during read and write operations as specified in Tables 2
and 3.
.
4
RD-A
input
Read A counter~Selects the outputs and functions of the A
counter during read and write operations as specified in Tables 2
and 3.
5
RD
input
Read-Enables a read operation as specified in Tables 2 and 3.
18
LD
input
LOad~A high-to-Iow trarlsition of this signal enables a load
operation tQbe performed ~s specified in Table 3.
When LD is low, data changes will not Occur.
7
8
9
11
12
13
lD/F
2D/F
outputs*
Data bus-Eight bidirectional lines used to transfer data into or
out of the A counter or C counter.
output
Maximum A count-Indicates that the A counter has reached a
maximum count. The maximum count is 376 when counting by
two and 377 when counting by one. The signal is generated by
gating CLK-A and the maximum count condition of the counter.
4DjF
8DjF
16D/F
14
15
32DjF
64DjF
128DjF
1
MAX-A
Confidential and Proprietary
4-245
t>COO6
Pin
Signal
Input/Output De£initi0l1,lFunction
17
MAX·C
output
20
Vee
input
Voltage-Power supply dc voltage
10
GND
input
Ground-Common ground connection
Maximum C count':-' Indicates that the C counter has ~ached a·
maximum count of 377.
This signal is generated by· gating CLK-C and the maximum
count condition.
"TTL three-state
Functio~ Description
Figure 3 is a simplified logic diagram of the DC006 that shows the read and write control logic ) the
inputs and outputs of the A and C counters, and the multiplexer logic. Table 2 lists the read and
select inputs required to read the counter outputs. Table 3 lists the write-control inputs required to
load and clear the counters.
Table 2 • DCOO6 Read"controJ Functions
Input Levels*
Output Functions
RD·A
RD
g.A
S·C
D/F<7:0>
L
L
L
L
L
L
H
L
H
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
L
H
H
H
X
Clear A and C counters, read C counter
A<7:0>
C<7:0>
High-impedance
High-impedance
Clear A and C counters, read A counter
A<7:0>
A<7:0>
A<7:0>
Clear A and C counters, read A counter
A<7:0>
A<7:0>
A<7:0>
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
"L = TTL low, H
4·246
=
L
.H
L
H
L
H
L
H
TTL high. X = TTL low or high
Confidential and Proprietary
: DCOO6
Table,} • DCOO6 Write-control Functions
Fun¢don
Inputs Levels1
RD-A
ID
L
H
H-L
H-L
H~L
X
H
H
H
L
L
H
H
L
L
H
IUegal2
L
H
L
H
L
H
L
LoadA<7:0>
LOadA<7:0>
Word count/Bus· address not selected
Clear A andBc6u.nters
Loilding ~Jed
L~~ llllSabled .
IL = TTL low, H = TTL high, X = TTL low or high, H-L '" high-to"iow transition.
2Simultaneous load and clear operation results in a clear.
~-T--------~~--------~-----d
ClK-A-,----------------d
.SC-;~----------r-ar~
RO
RO-A
C COUNTER
a Ilit'lIIIIIAlIY;.
LO-,--------r-------~~~
......
co
UP H IINTER
LDC
•.
CiJ{:C - , - - - - - - - - - - - - - ; - - - - q C L K C
L
"-'----leLR it
~.
~::
g: I
Oll
1
.'
C
<7,0>
.
MAX-C
Figure 3 • DC006 Simplifzed Logic Diagram
Confidential and Proprietary
4.247
-'
DC006
. Application Information
Refer to the Chipkit Users Manual LSI-ll Bus Intet/ace Chips (document no. EJ '01387 c92) for general
application information. TheQ-bus is an LSI-ll bus .
. Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC005 are
described in the following paragraphs. The test conditions for the electrical values are as follows
unless specified otherwise.
• Operating temperature (TA ): O°C to 70°C
• Supply voltage (Vcc):5.0 V ±5%
Mechanical Configuration
The physical dimensions of the DC005 20-pin DIP are contained in Appendix E. The materials and
construction of the molded DIP are defined in Digital Specification A-PS-1900002-GS.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
• Supply voltage (Veel: 7.0 V
~ Input voltage (VI): 5.5 V
• Storagetemperature (Ts): -65°C to 150°C (-149°F to 302°F)
Recommepded Operating Conditions
• Supply voltage (Vee): 4.75 V (minimum), 5.0 V (normal), 5.25 V (maximum)
• Supply current (lcc): 140 rnA (maximum)
• Relative humidity: 10% to 95% (noncondensing)
dc Electrical Characteristics
The dc electrical characteristics of the DC006 for the operating voltage and temperature'ranges
specified are listed in Table 4. All input and outputs are TTL levels. Refer to Appendix C for test
circuit configurations referenced in the tables.
4-248
Confidential and Proprietary
00C0e6
Parameter
Table 4 • DC006 Tn Input and Output Parameters (nonbus) .
,
Symbol Test
Requimnent!l
Uni"
Max.
;Min.
V
Cl,C2
0.8
V
Cl,C2
-1.2
V
C3
';:r-
V
C1
V
C2
lnA
C4
2.0
VlL
Test
Circuit
input voltage
Input clamp
voltage
VI
Vcc=4.75V
11 =-18 rnA
High.level
output voltage
VOH
Va: ",,4.75
Io=-tOrnA
low-leVel
V~L
. Vcc=4.75V~
2.7
'-/,'-~
Io=*Z°tnA.
Input current
at maximum'
input voltage
High-level
vci=5.2;5 V
V1 =5.5V1
1m
input cuttent
Three-state .
,:~
Vcc ... 5.25 V
V r =2.7V
Not three-state
Low-level
~
IlL
input current
C4
.~~-:
,
ItA
50
.. 55
~
~
C5
Vcc=5.25 V
VI =0.5 V
CLK-A, CLK-C
-1.1
-1.7
CN'i'IA
rnA
ItA
100
D/F
LD,RD, SoC,
rnA
s:A
RD-A
.200 ..
High-impedance
output current
10
Short-circuit
output current
los
1
Vcc =5·f5V
·Vo=3.75V
Vcc =5.25V2
-40
'
.W\
100
I!A
Cl
-100
rnA
C6
rnA
170
C7
Vee =5.25 V
Icc
IThree-state TTL output in off state.
2Not more than one output shall be short circuited at a time and the duration of the short must not
exceed 1 second.
Supply current
Confidential anclProprietart
4-249
,----------~---,-----------
-
acmecttical Char8cteri$tlcs
The input and output signal timing for the DC006~' shown in Figure 4. Table 51iststbe setup time
and pulse characteristics for the times specified in Figure 4. Table 6 lists the propagation delays for
the signal timing references in Figure 4. Refer to AppendixD for the standard input and output
voltage waveforms parameters used to measure propagation delay. The output loading circuit for
the open collectors and the three-state output loading circuit and voltage waveforms are shown in
Figure 5. These circuits are referenced in Thble 6.
.
.
r
seT
1~
DATA
~
1D/F
20/F
I\\.\.\.'\I
t25
20NS-
~
tlt2-1
SoC
t3-1
!f-A
~
READ &. COUNT
~~
-
~
I
I
S
~~
I
,,\.\.\.\.\.'\\ i:I
~
I
~~~
~
tI4-fr-
t22-
~
I
... I-- t8
t4'" IONS
i- tel-
r n
--tl-te
t'5-.
10NS
..... ~~ 17 JLf-
... t5
-
t241--
-
rt-124
t16', r-I
t 18-1
1 ....
MAX· c
1,2MAX·A
CLEAR
j-o- t 21-
l-
.....
-t,l
RO·A
LOAD
1
r-
~
t 13
l-
i - Ioe-t20
!n
t'9-
I--
Figure 4 • DC006 Signal Timing Sequence
4·250
~
j.I
!-
-jREAD A
I-t-t17
-to
I
~
~\.\.\.\.~ i:I
I
I\.\.\.\.\.'\I
I+- t lO
~
~
O/F(7 :3.
r
tREAD lit COUNT C1
..
Confidential and Proprietary
-.
t23:'"
I+-
'f"mi,,~(
Signals
Reference .
t) (pulse width)
t, (setup)
~
Minimum
Durafton 'll~)
50
D/F<7:0> HtoID
10
10
(setup)
90
t7 (pulse width)
. 20
ta (setup)
til
(pulse width)
tu
(setup).
t 1,
(pulse width)
40;; .
ttS
(setup).
45·.·
S-A to ltD
10
15
~,
(data hold)
LDtodata. in20
Confidential md·Proprietai-y
4·251
---.-----.-~-
-
...
00006>
,~
,"
'
,"
i.bt.6 oDC()06 ~~pagation Delay
Tuning
Input Signal
Reference . ~T.tansition)
Output Signal
(Ttansition)*"
Test
Conditioo
Propagatioo
Delay (ns)"
Min. Max.
tl
SoC (H.L)
S-A (H-L)
D{F<7:0> (X-L)
Load A
RD-A=OA V
(C counter)
15
80
t2
SoC (H-L)
S-A (H-L)
D/F<7:0> (X-L) ,
Load A
RD-A=O.4 V
(A counter)
15
80
t.
RD (L-H)
D/F<7:0>-(Z)
Load A
10
30
t,
RD (H-L)
(Z)-D/F<7:0>
Load A
34
80
t. o
CLK-C (H-L)
MAX-C (L-H)
Load A
18
55
t12
CLK·C (L-H)
MAX-C (L-H)
LoadB
10
35
t ..
CLKcA(L-H)
MAX-A (L-H)
LoadB
10
35
tu
CLK-C (H·L)
MAX-C (L-H) ,
LoadB
10
35
t17
CLK,A(H-L)
D{F2 (L-H)
Load A
18
55
t20
a:K-A (H-L)
MAX-A (H-L)
LoadB
10
'35
t'2
RD-A (L-H)
D{F<7:0> (Z-L)
(Z-H)
Load A
Load A
10
10
30
30
t,)
RD-A (H-L)
D{F<7:0> (L-Z)
(H.Z)
Load A
Load A
8
25
8
25
*Z =high impedance
4-252
Confidentwand Propr~tary
DCOO6
TEST
.POINT
TEST
POINT
VCC
n
200
FROM
OUTPUT
FROM
OUTPUT
I~
50 pF;;r:
ALL
DIODES
,
••
ALL
DIODES
FD700
lK
50 pF
F0700
S2
LOAD ATTLOUTPUT CIRCUIT
OUTPUT
CONTROL
(lOW-lEVEL
~_.
ENABLING)
LOAD B THREE STATE CIRCUIT
L
/i ~3~
.
X,,-3_V_ _ _ _ _ _ _.......
3V
___ 0 V
IZl
WAVEFORM 1
(SEE NOTE I)
--+---.. .
S1 CLOSED
JO"~"
1.3V
51 OPEN
WAVEFORM 2
S2 CLOSED
(SEE NOTE 2) _ _ _ _- J - - - -
'---1.5 V
0V
S1 AND
S2 CLOSED
NOTE
1 WAVf;:FORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS
SUCH THAT THE OUTPUT IS LOW EXCEPT WHEN DISABLED BYTHE
OUTPUT CONTROL.
2. WAVEFORM 2. IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY OUTPUT CONTROL
Figure 5 • DeaD3 Output Load Circuits
Confidential and Proprietary
4-253
• Used with the DC006 to implement a direct memory access interface.
• Contains logic to request and gain control of the Q-bus.
• Allows four-word or multiple-word transfers.
• Contains bus receivers and drivers for cUrect conneCtio~ tQthe computer bus.
• Uses external free-running clock and:futernally generafe'S.eooble and disable clock controls .
. Description
The DCOlO direct memory access (D¥t'-),\Xlntained in a2().pffl dual-inline package (DIP), is a lowpower Schottky device used priIll;aJj}y .ina DMA .device illterface to perform the handshake
operations required to request andg$inicontrol of the Q.b,us. Once bus mastership has been
established. the OCOlO generates the required signals to perform a data-in (DATI) transfer, data-out
(DAlD) transfer, or a data-in/data-out (DATIO) transfer as selected by the control lines to the
DCOlO. Four words or multiple words ~nbetrans:fenedbe£O~'control of the bus is relinquished.
Figure 1 is a simplified diagram of the logic contained on the DCOIO chip. The signals in
parenthesis connect internally.
(MASTER)----o~
R£O-----'---I
iAPt.yl-----~
(MASTER E.NA HI
t£NDUI-1::::============:::::l===~_D
Figure 1 • DC010Simplijied f:.ogic Diagram
4-255
00010
• Pin and Signal DesCriptions
This section provides a brief description of the input and output signals. and power and ground
connections of the DCOI0 20-pin DIP. The pin assignments are identified in Figure 2 and the
summarized in Table 1.
REa
Vcc
5ATiO
i5ArTiii
Ai:iREN
iiiiii'
OATEN
ClK
OOUT
CNT4
DIN
RPLY
TSYNC
TMOUT
B'1i'MGO
BOMGI
MASTER
RSYNC
GND
BDMR
TOP VIEW
Figure 2 • DeOlO Pin Assignments
Table 1 • DeOIO Pin and Signal Summary
Pin
Signal
Input/Output Definition/Function
1
REQ
input'
Request-A high level initiates a bus request. A low level allows
the termination of bus mastership to occur.
13
BDMGI
input'
DMA grant input-A low level allows bus mastership to be
established if a bus request on the REQ line is pending. This
signal is delayed and becomes the BDMGO output if not a low
level.
16
CNT4
input'
Count four input--A high level allows a maximum of four
transfers to occur before bus mastership is relinquished. A low
level allows unlimited transfers to occur when the REQ line is a
high level. If the input is not connected, it assumes a high state.
14
TMOUT
input'"
Timeout-A low when the MASTER ENA signal is high. A highimpedance when the output MASTER ENB signal is low. When
driven low, it prevents the assertion of the BDMR signal. When
driven high, it allows the assertion of the BDMR signal if the
BDMR signal has been negated because of a four-maximum
transfer condition. A resistor and capacitor network can be
connected to this pin to delay the assertion of the BDMR signal.
4·256
Confidential and Proprietary
-
. l"V"'
.•....... :......_ ...•....
~
Data-in-Used with the DAriO'
transfer as specified in Table 3.
si~tQse;l~ the®e,:p£
. . . ,
Data-in/Data-out-Used with the DATIN signal to select the
type of transfer as specified in Table 3. H the input is not
connected. itassumesaW,gb.state, .
12
RSYNC
"Recel~ sya~n~~'¥&.~~e to become bus master
input!
,licc.mding to the relationsll.ip~,thdly--:-Ena,pl~s or~llpl~ ~.'.clcx:k signal and allows the
derice to become busmastet Il<;cordingto the relationship of the
£onqwlQg,
' s 't.g,.",
nils: ' ,
RSYNC + RPIX + MASTER ENA= MASTER
19
INIT
input!
Initialize-Used to initialize the logic so that the REQ signal will
start a bus request transaction. A low level negates the BDMR,
MASTER, i'5ATEf.l, ADREN,.RSYNC, DIN, a1)dDO,-!T si~nals.
11
BDMR
oUt'jPut' .
9
MASTER
output'
.
(,"
.
DMA request~A low levelindi¢$tes that the device i.;'~~srl.ng
··bus 'mastt;tsOiP:M~rbe'~~direcd, tOtheQ~Dw;
,:,,'1.
J' .• )_: ,R': _,'
-":,,,.'-~JJ:~'
'-,,' ,',
:._",. -;
',,-c
'-1-., -,:,,'
1-"
'_,- ',' , .:
Master-Indicates that a device is bus master and that a transfer
sequence is in progress.
8
BDMGO
:.P¥A,8ll\nt.(:l,J,WP~.t;--I( qo,
outPUt'
j
,is:~~, fl:US sigt;'alis .the
r.q~ed. P9~~t'~f the,:, ...., .~rQ{!,m~13tna ,ltXl\lest is
pending, this signal is notasserfed'. MaY~C9lUlected dir¥tly: to
,.,theQ.bus.
7
TSYNC
output!
.,
"
.
,."
Transmitsynchronize-.,ASseI'tf!!dhY:thedeVice ·fu·iridi6ite·tbat.• a
transferis ,in progress.
18
i5ATEN
output'
Data enable-Asserted to indicate that data may be transferred
to the bus.
4
ADREN
output'
A~sse,~~.le.~4s~rte41:Q~~~th,alari add#s~aYbe
6
DIN
output'
Data in-Asserted to indicate~;thtbus.• maste1'dev~(:an
aceeptdata;
5
. DOUT
output'
Dat~ti:(it:..:...A:~Sei:teafd ilidita'te~lliat:ilie'bUs ma,sterdevice has
ttansferred data to .the bus.
transferred 'to'the hus.
. .. ,' .
.'
20
Vee
input
Voltage-.Pow~
10
GND
input
Ground-Common ground connection
'TTLlevel
2high-impedance
)open-c6nector
.'------------------
supply de volta.ge
".
"
-
llCtll0
Functional Description
TheDATINahd DAnO are TTL input levels that select the type of DMA transfer that will occur.
Table 2 lists the inpudevels and the transfer selected.
Table 2· DeOlO Transfer Selection
Inputs Levels* .
liansfer Type
DArIN
DAnO
X
L
DATIO
L
H
DATI
H
H
DATO
*L=TTLlow, H=TTLhigh, X=TTLlowor high
• Application Information
Refer to the Chipkit Users ManuallJI.ll Bus Interface Chips (document no. EJ -0138 7.92) for general
application information. The Q.bus is an LSI-ll bus .
• Specifications
The mechanical, electrical, and eiwironmental characteristics and specifications for the De010 are
described in the following paragraphs.· The test conditions fot the electrical values are as follows
.
unless specified otherwise.
• Supply voltage (Vcd: 5.0 V ± 5%
Mechanical Configuration
The physical dimensionsofthe DCOlO 20-pin DIP are contained in Appendix E. The materials and
construction of the DIP are defined in Digital Specification A-PS-1900002"GS.
Ahsolu~ Maximum
Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximulll ratings for ex.tended petiods may adversely affect the
reliability of the device.
'
• Supply voltage (Vee): 7.0 V
• Input voltage (VI): 5.5 V
4·258
Confidential and Proprietary
• Supply voltage (Vee): 4.75 V (minimum),5.0 V (normal), 5,25 V (maximum)
• Supply current (led: 160 mA (maximum)
• Relative humidity: 10% to 95% (noncondensing)
de EleetrkalCbarac:tetistks
The de electrical parameters of the OCOIO for the operating voltage and temperatu:tetanges
specified are listed in Table 3. Refer to Appendix C for the test circuit configuratioosref~ed in
the table.
Parameter
Symbol
Condition
Requirements
Min
Max
Vcc=4.75
Vcc ... 5.25
2.0
1.53
1.7()
Test
High-level
input voltage
VI
1:30'
V~=4.T5
Test
Circuit
Cl,C2
·W.J
VI
·o.a
Low-level
input voltage
Units
V. cc ';:5.2:5
'IA7
V~'7opt':n
II'~-18 mao
-1.2
VI'
V?,'
f
Cl.C2
.tp,~
,{
Inputoamp
voltage
Vct ...4.75
HigMevel
output voltage
.I.J ... -LOmA
Law-level
Vcc= 4ij'5V
output voltage
Io=8mA
Input current
at maximum
input voltage
High-level
1m
input current
Low-level
input current
IlL
C3
2.7·
'<::2
'0.5
VI
1'o=70mA
0:8
'VJ,4
Vcc =5.25 V
V1 =5.5 V
1.0
1.5
mA'
mAo
Vee =5.25VS
VI=2.7 V
VI=2.7V'
V,=3.8 V
V.=3.8 V
Vr =O.5 V'
Vee=5.25 V
Vcc =5.25V
Vcc =0-5.25 V
Vee =0-5.25 V
;j
C4
C4
65
JJA
JJA
JJA2
JJA'
-1.4
-2.0
mA
mA
50
300
40
C5
-10
-10
Con£id~ an,d ProprietIW
._--_._-----
JJA2
JJA)
4-,259
---~-----.~-
.
-
Parameter
00010
Symbol
Test
COndition
Requirem«mt§ . . . ,
Min
lJnits·
Max
Test
Circuit
25
~4
Cl
Output leakage
loH
Vcc==4.75 V
Vo =5.25 V
Short-circuit
output current .
los
Vcc =5.25V7
-1.5
-60
mN
C6
Supply current
Icc
Vee =5.25 V
125
160
rnA
C7
ITILinput, .
zhigh-impedance input
)high-impedance (Schmidt) input, open-collector output
"open-collector output
'except pin 16 and pin 2
'pin 16 and pin 2
7Not more than one output shall be short circuited at a tiJIl~ atld the duration of the short must not
exceed 1 second.
. . ,
ac Electrical Characteristics
The input and output signal timing for the DeOlO is shown in Figures 3 through 7. The setup time,
pulSe-widths, and switching characteristics referenced in the timing diagtatns are listed in Table 4.
Thble 5 lists the signal propagation delays also referenced in the, timing diagrams. Figure 8 shows
the load circuits used for measuring for the open-collector and TTL outputs. Refer to Appendix D
for the input and output voltage waveforms used for measuring the signal propagation delays.
Figure 3 shows the signal timing required for the DMA bus-request and bus-grant logic. Figure 4
shows the signal timing required for one data-in (DIN)transfer to the DMA interface. The signal
timing required for one data-out transfer is shown in Figure 5. Figure 6 s.hows the signal timing
required for multiple-data transfers in and out of the DMA interface. The signal timing for the
timeout sequence is shown in Figure 7. The values of the resistOl; (Rx) and capacitor (Cx) used in
the timeout circuit shown in Figure 9 are selected for the proper delay for the next DMA request
.
from the interface. The delay circuit connects to pin 14 (TMOUT).
4-260
Confidential and Proprietary
CLK
RSYNC--'L.~~______~~______________________+-~~
i
RP~-'L.______________________________________~I
REO
_ _ _ _ _"------..............":"!,
I
_____________________~~-t5~~
BOMR
I
I
I
I
___....-....;~..,... t 2 r B D M G l J...._..1..
1_---!II
-~I
t"':- t3 . .
~
,
I
I
rl+I--~I------------
I
II I I
~ I
r:~:-'··i-I.;.l,_ _ _ _ __
I
I-ts--i
•
I...., ____
t-
:
*TMOUT
1,1 .
I
t7-1
:
I
_~:~_.........._ __ _
. ·L.I_·.;..:
I
I
I
l r - -13e ..;....;.......;;Iy,;:Iif"I~·I:--1- - -.........
MASTER
ADREN __
__
~~________________~1__~______~~__~! ~~I~··rf=--tl-1-------
-+:__________________________ _____
________________
~tl~
iNiT
__ ____________
I
I .
'--_-'11..11· .
BDMGO
I......-.-=t8~
___________
-U
~
I
I
!oI~f---O---t4
..
'WITH NO RC NETWORK CONNECTED
Figure J ~ DeOlO DMA Bus Request and Grant Signa/Timing Sequence
Confidential and Proprieta,ry
4-261
eLK
~M~~~~I~»~~
1
1
REO
" 1
I
I
I
t32-0
I
I
4' I
I
I
It it'll- -l t21 r:-I----,.._ _
TMOUT ---4>-t!--:I~'_+-__-:1:-:--:-:1~H.......;.-_ _.yl,~~j-+1_14
___-:-1_".....1
1 I'
I t 16-
It
1
t
.
_q_-
I.
t 33
I
:
\11-1--+,"'"
.·.
I
~r_t20_ _ _
II I
I
I
I
I ' '. t25~
I
1
It23..,
I
i
I
I-
r
-:-'1
iL'1-J-+1_ _ _ _ _ _ _ __
I »- 'I
11-:,......
, _ _ _ _ _ _ __
tIS..,
H
j--,.... ________
II
.J .~
l:;t27
MASTER
NOTE: t27 OCCIJRS ON~ CLOCK CYCLE AFTER NEGATION OF DOUT
Figure 5 • DCOlO Data-out Transfer Signal Timing Sequence
. Confid~ial and Proprietary ,
i4~263
lBlIII
NOTE: t27 OCCURS ONE CLOCK CYCLE AFTER NEGATION OF DOUT
Figure 6 • DeOlO Multiple Data-injData-out Transfers Signal Timing Sequence
4-264
Confidential and Proprietary
END OF 4TH
TRANSFER
£
:.ru-LrLn.~
CLK
. . t1, ' I '
REO
tf
"
I
I
{END
I
CYCLE~f)-_ _ _ _ _"'f)ooo_"'' ' '.........,;..;H...,;..;...,;..;_ _ _ _ _ _ _ _ __
(MASTER ENA H)
I
t21-4of
F" »
f
TMOUT
"_
Ji. .
_ _ _---'l--RCOELAY
•
_t3_5:___
I,..'..,'r-<-'~'...
"_'_ _ _ _ _ _ _ _ __
~~+:!,...J)~=~'
..1
..._~___________
'\.
I1IH
'('i
CLK
REO
)
n
CNT4
(END l)
MAstER
LJ
';-
'-~
ft
IJ
If
"
.$
"'i/
o.."L'
"t--', ."
--
--RCOELAY
"
II
..
i
N
TMOUT
:"';
I
I
PARENTHESES -INTERNAL SIGNAL FOR REFERENCE ONLY
Figure 7 • OCOlO Timeout Signal Timing Sequence
-.
Dcnio
Table 4 • DCOlO Pulse Widths and Setup Times
Tune
Signals
Minimum
Refe~ce
Reference
Dumtion(ns)
tl (pulse width)
t. (setup)
35
INIT toREQ
25
35
t6 (setup)
. BDMR to J;3DMGI
t9 (setup)
BDMR to BDMGf
o
CLK (low)
60
eLK (high)
60
t12
(pulse width)
tn (pulse width)
t14
(setup)
REQtoCLK
35
tiS
(setup)
DINtoRPLY
o
60
t22 (setup)
t 28 (setup)
RPLY.tnCLK
30 .
RPLYto DATIO
35
30(1 clock period maximum)
t 2• (pulse width)
t30
65
(setup)
tu (pulse width)
REQ
Confidential and Proprietary
35
mil,
Table'S· DCOIO Signal Propagation Ddays
Output Signal
Input Signal
Tuning
Reference (TransitiOn)
t,
(Transition)
BDMGI (H;JX
;'"
BDMGO(H-L)
Test
Condition l ,2
" Loru:FA"
f"" .
"
Propagation
Delay (ns)
Min.
Max.
95
220
t)
BDMGI(L:H) "
BDMGO(L-H)
Load'A."
15
60
t,
REQ(L-H)
BDMR(H.L)
LoadA1
25
70
t,
BDMGI(H-L)
TMOUT(H.L)
Load A
85
230
~
;.\.
t.
BDMGI (H.L)
BDMR(L.H)
117
306
t,/
CLK (H-L)
4D~~" (J,.:l:l),.
15
60
tu
CLK (H-L)
TSYNC (L-H)
LoadB
18
60J
t"
CLK (H-L)
ADREN(H-L)
LoadB
20
65 1
t17
CLK (H-L)
DIN (L-H)
LoadB
18
6(}l
t 1•
CIJ{ (H-L)
DiN (H-L)
LoadB
18
60
t 20
CLK (H-L)
TSYNC (H-L)
LoadB
18
60
t21
CLK (H-L)
TMOUT (L·fI)
LoadB
30
90
t2•
CLK (H-L)
DOUT(L-H) '"
LoadB
60
175
.
..
t 2,
CLK (H-L)
DOUT(H.L)
LoadB
20
65'
t 26
CLK (H-L)
DATEN (H-L)
LoadB
20
65'
t27
CLK (H-L)
DATEN (L-H)
LoadB
( ,
20
65'
t31
RPLY (H-L)
i5A.'fEN (H·L)
LoadB
20
65
t)32
CLK (H-L)
ADREN (L-H)
LoadB
18
60
t"
TMOUT(L-H)
BDMR (H-L)
LoadB
20
75
t}6
BDMGI (H-L)
MASTER (L-H)
LoadB
90 .
242
t37
CLK(H-L)
MASTER (H-L)
LoadB
18
66
t)8
RSYNC (HeL)
MASTER (L-H)
LoadB
10
58
" "-, ';1':
,~'
ISee Figure 8 for output load circuit configurations.
t,. represents the subsequent assertion of ADREN.
)These propagation delays meet the following requirements:
t to t,,::::; 10 os
t2$ to t27 ::::; 20 ns
"
tn to t 26 ::::;40 os
t" to t 17 ::::; 10 ns
t" to t,,::::; 10 os
t. to t'6::::;27 os
2t" represents the first time ADREN is asserted.
_~.
___. ___"___a_._o._____
-
<.:i
TEST POINT:
':~
, Vee
,
j:'"
'"O.O"'~,
VCC
600
•
FROM OUTPUT
}-,.....L---iIIH
TEST
. POINT
ALL
DIODES
FD7!JD'
T
'5PF
LOAD A OPEN-COLLECTOR CI RCUIT
LOAD B TTL CIRCUIT
Figure 8 • DC010 Output Load Circuits
Vee
fRx
rTMOUT
rcx
Figure 9· DC010 Timeout Delay Circuit
4-268
• Provides the logic to request and gain control of the UNIBUS
• Used to arbitrate for DMA or interrupt mastership
• Bus receivers and drivers compatible with UNIBUS
• Used to devdop UNIBUS interfaces £or~riph~ devices
• Description
The neon is a 16-pin, dual-inline packagt';(DIP) used in the~lopment of device interfaces for
the UNIBUS. It contains the logic required to perform interrupt bus requests (BR) and nonprocessor direct memory access (DMA) requests to gain control;Qf~ UNIBUS.
Input signals from the UNIBUS are' ~i~ by high-impedai18erectivers on the DC013 and signals
from the neon to the UNIBUS are supplied by hi.gh~~nt, open-collector driver outputs. The
signals levels between the UNIBUS and the DC01.3ak compatible. The input and output signals
between the device and Dcon are TTL levels.
The neon circuits includes bus grant logic, bus busy logic, and slave acknowledge logic. The
simplified logic diagram of the DC013 is shown in Figure 1.
BUS NPR
STEAL GRANT
4
~3~=:l:>-.:n
REQUEST 1 1+"""!~~r),....,.-hd
BUS BG/NPG .5
IN
CLR SACK 15
ENe
Figure 1 • DC013 Simplified Logic Diagram
Confidential and Proprietary
4·269
•Pin and Sp~tio1\S
The input and output pins and power and ground connections of the DC013 are shown in Figure 2.
Table 1 provides a summary of the signals defined in the following paragraphs.
Vec
REOUEST
BUSSSYN
CLR SACK ENB
STEAL GRANT
MASTER CLR
IN IT
eUSNPR
SACK
BUS BG/NPG IN
BUS BG/NPG OUT
MASTER
6
BUS SACK
BUS BBSY
BUS BR/NPR
GND
TOP VIEW
Figure 2 • De013 Pin Assignments
Table 1 • DC01.3Pin and Signal Summary
Pin
Signal
Input/Output
De£inition/Function
1
REQUEST
input I
Request-Asserted to request that the DC013 begin
arbitrating for mastership of the UNIBUS.
2
BUS SSYN
input'
Bus slave synchronization-Asserted by the
UNIBUS slave to indicate that it has completed the
operation requested by the master device.
3
STEAL GRANT'
inpuf
Steal grant-Used only when the DC013 is permitted to win bus mastership.
4
BUSNPR
inpue
Bus nonprocessor request-Used only when the
DC013 is allowed to win bus mastership and the
steal G~nt feature is enabled.
5
BUS BGjNPG IN
input>
Bus grant/nonprocessor grant in-Provides the
appropriate UNIBUS grant signal to the DC013.
6
BUS BG/NPG OUT output'
7
BUS SACK
output'
Bus grantjnonprocessor grant out-Transfers the
appropriate grant signal from the DC013 to the
rep1aining devices on the UNIBUS.
Bus sele.ction acknowledge-Indicates to the
UNIBUS arbitrator thllt the DC013 acknowledges its
selection as the next master of thlj UNIBUS.
8
4·270
GND
input
Ground-Common ground connection.
Confidential and Proprietary
-
'.~
Pin
9
InPUt/Output
.BUS BR/NJ?R
O\ltpue
DefmitionfFunctiOn
~us requestlnonprocessor reguest out~I~te"
by.
that the DC013 has. heen requestfd
the
Rl!.oUJ¥~ intmtsignal tci,atbitrate for milStershlp of
UNWYS.·
;
. .
the
10
BUS·BBSY
input>10000tput} Bus bUSY1T1A~.an ipput,iti1llq~ms the DeOll~th~,
the gm:ent;, ;mas~ bas completed it~ use.~ the
UNlBU$..As. ~01;l:tP1J1:, it allows theD;C!lU ,to
indicate iliat (t~b«:Ci'Qme~e cutrent hU,Sl1l3S~.
11
MASTER
output!
Master-Asserted when the Deon is the current
. bus master
and is ••asserting
the BUS BffW',stgp.ai.
..
-",.i'
" -,-.
,",,,,
-,.,
'F _'C',_:'
12
SACK
output!
Sdection acknowl+-Asserted when,•.thenc.e13
js~s~erting thqi~I~St{ signal to 1lCknowl~ \ts
selection as '.1 - ~~.cf the bus.. .: •
13
INIT
input!
14
MASTERCtR
input l
15
CLRSACKENB
input!
<,
"
,~~-"~,~
'
'
_'
"'
'"'
"~to
M~\ier"'cIeh"'::':Asserted to alloW
input to cleh thi:?OC013.' I
c"
16
Vee
IP'Llevd
~i
"
the BUSrSSYN
.'--
input
2Wgh~irnpedance UNIBUS input
;openVS the PCQP to~~a.~
the bus. When the DC013 is used to win DMA mastership, this input may be directly connected to
the UNIBUS or to other logic within the master device.
STEAL GRANT-When the DC013 is used to win interrupt mastership, ,ws:input:signfd:aHowsi1)
to steal and reply to an interru,p~8rant ip.teJ)dedfoT!\nother devi~e, connecte,d to the UNIBUS. This
feature can reduce the civtmill DMAktency.
..
. '..
..
BUS NPR7""'When the steal grant fea~isenabled and theOC913 requests interrupt lll~tet:ship,
thh> input inf()rms theDC013 that a. DMA 4evice is requestingus~ of the bus.
'.'"
BU,~ BG1NOOlN.",..When the DCOn, req\l~tsi~tetrupt '~~~rship, this ~PUt connects to the
appropriate BUS BG7 through BUS BG4 input. When requestingDMA mastership, it col1n~s tp
the BUS NPG input.
BUSBG/NPG OUT-When the DC031 requests interrupt mastership, this output connects ro the
appropriate BUS BG7 through BUS BG4 output. When the Dcon requests DMA mastership, it
connects to BUS NPGoutput.
Confidential and Proprietary
4-271
-
neon
BUS SACK-This output indicates ~p the. UN.~USarbitl'3to! that. the ncon acknowledges its
selection as the next master of the UNIBUS.
BUS BR/Nplt-This output indicates that the Deon has been requested by the 'REQUEST input
to arbitrate for mastership of the UNIBUS. If the DCOl} is requesting interrupt mastership, this
output connects to the appropriate UNIBUS line BOS BR7 through BUS BR4 output. If the Dcon
requests DMA mastership, the output connects to the UNIl3USBUS NPR line.
BUSBBSY-After the DCOl} has been granted next bus mastership, it must wait for the current
master to complete its data transfers. This input informs the DCOl} that the current master has
completed its use of the UNIBUS and provides an output from the DCOl} to indicate that it has
become the current master of the UNIBUS.
Device Signals
....
REQUEST-An input from the device to request that the DCOl} begin arbitrating for mastership
of the UNIBUS.
MASitlt-This output is asserted when the Dcon is asserting the BUS BBSY signal indicating
that the DCOl} is the C1,1l"rent master of the UNIBUS. If the DCOl} is requesting interrupt
mastership, this output indicates that the interrupt vector from the device should be transferred to
the UNI.f,lUS data lines. If the Dcon is requesting DMA mastership, the output is used to trigger
tha data transfer logic of the master device.
SACK-This output is asserted when the DCOl} is asserting the BUS SACK output to acknowledge
its selection as the next bus master.
INIT- This input initializes the logic in the DCOl} to end the bus cycle initiated by the DCOl}.
MASTER CLR-This input allows the BUS SSYN input to clear the Dcon logic. The use of this
input is optional !when the DCOl} is used for DMA transfers.
O;O:C""t""'R""'SA:-:-;OC""K""E="N<"'n""-This input causes the the DCOl} to deassert the BUS SACK output if the DCOn is
also asserting the BUS BBSY output. It allows UNIBUS arbitration to resume when the. Dcon
becomes bus master. When the Dcon is requesting DMA mastership, this output may be used to
delay UNIBUS arbitration during multiple data cycles. During the last data cycle, the the master
logic should assert the CLR SACK ENB input to the Dcon to allow the arbitration to be resumed.
Power and Ground Connections
Supply voltage (Vee): Connects to the 5-Vdc power supply
Groun.d(GND): Common signal and voltage ground
• Functional Operation
The followmg descriptions assume that the reader has a knowledge of the operation of the
UNIBUS. Refer to the PDP-ll UNIBUS Processor Handbook PDP.l1/84, PDP-ll/44,and PDP-ll/24
(Digital document no. EB 26077-41) for a more detailed description of the UNIBUS operation.
Typical UNIBUS interface implementation of the Deon for interrupt and DMA data transfers is
shown in Figure 3. Request and grant signals thatare notused are wired through the interface and
canbeuied by subsequent devices.
4-272
Confidential and Proprietary
and D< 15:10 > lines.
,
Wh6n the SELECT input to the multiplexer is negated, the A' iiiptti's .are trallsferredto the bus.
When the SELECT input is asserted, the B inputs arettansferredto the bus.
The asSertion of theM.ASTER 'outputdriablestheSEL inputs to' the mUltiplexers, enables the
outputS()£ tbebus transceivers linesBUSn < 09:02>and,aft: O°C to 70
D
C
• Storage temperature ('Is): -65°C to 125°C
Recommended Operating Conditions
• Power supply voltage (Vee): 5.0 V ± 5%
• Supply current (led: 140 rnA (maximum)
• Relative humidity: 10% to 95% (noncondensing)
dc Electrical Characteristics
The d~ electrical parameters of the Deon for the operating voltage and temperature ranges
specified are listed in Thbles 2 through 4. Thble 2 lists the specifications of the TTI.. input and
output circuits that do not connect to the bus. Table 3 lists the specificatiorts for the highimpedance receivers that connect to the UNIBUS. Thble 4 lists the dc specifications for the opencollector driver outputs that connect to the UNIBUS. Refer to Appendix C for the test circuit
configurations referenced in the tables.
Thble 2 • DeOn TTL Input and Output Parameters (nonbus)
Parameter
Symbol
Test Condition
Requirements
Min.
High-level
input voltage
VIII
Low-level
input voltage
V 1L
Input damp
voltage
VI
Vcc=open
I,=-18 rnA
High.level
output voltage
VOll
Vec=4.7 V
10=-1.0 mA
Low-level
output voltage
VOL
Vcc=4.75 V
pin 11
pin 12
4·278
Units
Test
Circuit
V
Cl,C2
0.8
V
Cl,C2
-1.2
V
C3
V
Cl
Max.
2.0
2.7
Io=20rnAl
Io=2 rnA
Confidential and Proprietary
C2
0.5
0.5
V
V
-
DC013
Symbol
Parameter
Test Condition
Input current
at maximum
input voltage
II
Vcc =5.25 V
VI =5.5 V
High-level
input current
1m
Vcc =5.25 V
Vr=2.7V
Requirements
Min.
Max.
1.0
50
100
In.
-1.1
Icc
rnA
rnA
C6
-40
-5.0
Supply current
~
pA
Vi;c",,5.25V2
pin 11
pin 12
C3
C5
-0.55
los
rnA
Vcc =5.25V
V1 =0.5V
pin 15
pin 1,13,14
Short-circuit
output current
Test
Circuit
C4
pins 13,15
pins 1,14
Low-level
input current
Units
Vcc =5.25 V
-100
-45
rnA
rnA
140
rnA
C7
lRequires a load current of 70 rnA at pin 10.
'Not more than one output shall be short circuited at a. time and the duration of the short shall not
exceed 1 second.
lable 3 • DCon High-impedance Bus Receiver Parameters
Parameter
Symbol
Test Condition
High-level
input voltage
Vm
Vcc=4.75V
Vcc=5.25V
Low-level
VIL
input voltage
Requirements
Min.
Max.
Units
Test
Circuit
V
V
Cl,C2
1.30 V
·1.47 ·V
C1,C2
1.53
1.70
\'c£=4.75 V
Vee=5.25 V
Input clamp
voltage
VI
Vce=4.75V
11 =-18 rnA
-1.2
V
C3
High-level
inputcurrent*
1m
Vce=OV
VI=3.8 V
Vcc =5.25 V
40
~
C4
40
IJA
Vcc=OV
Vee = 5.25 V
40
65
pA
pA
pin 10
pin 10
Confidential and Proprietary
________ . ___________ •____ .•
_~._"
4.279
_____________________
~r
.Parameter
DCOa
Symbol
Test
Condition
Low-level
IlL
input current*
pin 10
pin 10
Requirements
Min.
Max.
Units
Vcc=OV
V1=O
Vcc =5.25 V
VI ",,0
-10
-10
IlA
Vcc=OV
VI = 0.5 V
Vcc=5.25 V
Vr=0.5V
-10
IlA
-10
tJA
Test
Circuit
C5
IJA
*All pins except pin 10.
Table 4 • neon Open-collector Bus Driver Parameters
Parameter
Symbol
Test Condition
Output reverse
current*
IoH
Vcc=4.75 V
Von = 3.5 V
Requirements
Min.
Max.
pin 10
Low-level
VOl.
output voltage
Vcc=4.75 V
Link = 70 rnA
I,;'k == 16 rnA
Units
Test
Circuit
25
tJA
Cl
65
~
0.8
0.5
V
V
C2
*All pins except pin 10.
ac Electrical Characteristics
The input/output signal timing for the UNIBUS request logic is shown in Figure 7. The transient
specifications for the signals are listed in Table 5. Refer to Figure 8 for the load circuits used in
measuring the TTL outputs and open-collector outputs. Refer to Appendix D for the voltage
waveforms used in measuring the propagation delays.
4-280
Confidential and Proprietary
BUS BG/NPG IN
__--'I
.
i.5 V.
35nij
(MAX)
BUS BR/NPFl
INIT
BUSBBSY
BUSBBSY
Figure 7 • DC01J Signal Timing Sequence
Table' • DCOl3 ac SiP 1hmsient Specifications
Signal
Input Voltage
Parameters (ns)
FaUTime
Rise Time
REQUEST
Oto3
!II! 15
!II!
6
CLRSACKENB
Oto3
::I!!
15
!II!
MASTERCLR
Oto3
!II! 15
::I!!
INIT
Oto3
!II! 15
!II!
6
6
6
BUSNPR
1 to2
!II! 10
!II! 10
STEAL GRANT
lto2
!II! 10
!II! 10
BUS BG/NPG IN
1 to2
!II! 10
!II! 10
B'OSSSYN
1002
!II! 10
!II! 10
BUSBBSY
1to2
!II! 10
!II! 10
Con£i~I.1~.atld. ProPriet:l!ry
4·281
TEST
POINT
VCC
Vce
FROM
OUTPUT
R1'
~on
TEST
POINT
FROM
OUTPUT
ALL
DIODES
FDn7 OR
EQUIVALENT
LOAD A-OPEN-COlLECTOR CIRCUIT
LOAD B-TTL EQUIVALENT CIRCUIT
'Rl IS 280n FOR PIN 11 AND 2Ul FOR PIN 12
Figure 8 • DCOlJOutput Load Circuits
Mechanical Configuratton
The physical dimensions of the De013 20-pin DIP are shown in Appendix E. The materials and
construction of tbe DIP are defined in Digital Specification A-PS-210002-GS.
4-282
Confidential and Proprietary
• Features
• Bidirectional bus transceivers
• Incorporates receiver noise immunity
• Input and output levels compatible with UNmus and Q.bus
• Provides three-state TTL outputs to interface
• Open-collector bus drivers
. Description
'The Deo2t is an octal bus transceiver oontained in a 20-pin dual-inline package (DIP) and is
compatible with both the UNIBUS and Q.bus. The De02t provides eight bidirectional channels
that transfer information between a wired-OR bus and a llserinterface. It provides high-impedance
receiver inputs and high-current, open-collector dr;iver outputs. The De021 transfers TTL-level
signals between the device logic and the bus. The Sdect and Enable inputs to the De02t are used
to control the direction of information transfer.· The simplified logic diagram of the De02t is
shown in Figure 1.
ENABLE
--,--: 5.0 V ±5%
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause:permanent damage to the device.
Exposure to the absolute maximum ratings for extended" periods may adversely affect the
reliability of the device.
• Supply voltage (Ved: 7.0 V
• Input voltage (Vio) and output voltage (vou,): 5.5 V
• Storage temperature (Ts): - 65 Cl C to 150°C
Recommended Operating Conditions
• Power supply voltage (Vccl: 5.QV ±5%
• Supply current (Icd: 240 mA (maximum)
• Relative humidity: 10% to 95% (noncondensing)
Confidential and Proprietary
4-285
-
DC021
de: Elee:tric:al Characteristie:s
The dc e1ectriealspedfiClltions of the De021 for the operating voltage and temperature ranges
specified are listed in Tables 3 through 5. Table 3 lists the de parameters for the bus-to-channel
receiver input and outputs. Table 4 lists the de parameters for the channel-to-bus driver inputs and
outputs. Table 5 lists the dc parameters for the enable and select inputs. Refer to Appendix C for
the test circuit configurationsteferenced in 'Thbles.
Table 3· DC021 Receiver Input and Output de: Parameters
Parameter
Symbol
Test Condition
ReqWrements
Min.
High.level
input voltage
Low-level
input voltage
High-level
output voltage
Low-level
output voltage
Short-drcuit
output current
Three-state
output leakage
current
VIH
V1L
VOH
VOL
los
IoZL
Enable/Select'
Receiver out =20 rnA
Receiver out < 0.5 V
Vcc=4.75 V
V cc =5.25 V
1.72
V
1.9
V
C1,C2
1.50
1.66
2.4
V
C2
0.5
V
C6
-40
Enable/Select<
Receiverin=0.8 V
Receiver out = 0.4 V
'Enable = 0.8 V, Select =2.0 V
'Enable =0.8 V, Select =2.4 V
)Enable=O V, Select = 2.0 V
4Enable=2.0 V, Select =2.0 V
4-286
V
V
Cl
Enable/Selecf
Receiver in =0.4 V
Receiver out = 20 rnA
Vcc=4.75 V
Enable/Selece
Receiver in=O.5 V
Receiver out = 0 V
V cc =5.25 V
Test
Circuit
Cl,C2
Enable/Select'
Receiver out= -2.0 rnA
Receiver out> 2.4 V
Vcc:':4.75 V
Vcc =5.25 V
Enable/Selecf
Receiver in = 0.4 rnA
Receiver out = -2.0 rnA
Vcc=4.75 V
Units
Max.
Confidential and Proprietary
-100
50
rnA
...
00021
18bIe 4 • DC021, Driver Input and Output dc.Parameters
Pariunefer
Symbol Test Condition
High-level
output leakage
current
~ZH
Requirements
Max.
Min.
Units
Test
Circuit
C9
Enable/Select'
Driver in=O.8 V
Driver out = 4.0 V
Vee = 5.25 V
100
Enable/Selece
Driver in=O.8 V
Driver out=4.0 V
Vee = 5.25 V
Enable/Select'
Driverin=O.8 V
Driver out = 0.4 V
100
V~c=OV
100
Enable/Select
Driver m=0.8 V
Driver out = 4.0 V
Vee '" OV
J.tA
l
~H
C4
;Enable/Select?
Driver in ... 0.4 V
Receiver m=5.5 V
Vcc =5.25 V
Enable/Select·
Driverm=2.0 V
Receiver in=4.75 V
Low-level
input current
VOL
III.
Enable/Select!
Driver in=O.8 V
Driver out = 0.4 V
Vee =5.25 V
-85
rnA
Enable/SelectS
Dtiver m=2.0 V
Driver out =0.4 V
Vcc =5.25 V
...,.85
rnA
C8
C9
Enable/Select'
Driver in=2.0 V
Driver out = 100 rnA
Vec=4.75V
Driver out = 130 rnA
0.7
0.75
Enable/Select"
Driver in =0.4 V
Receivedn=0.8 V .
Vcc =5.25V
V
V
C5
-1.6
rnA
4·287
Confidential and Proprietary
... ;oj:
-'.
.....-~-----~-~~¥~
...
"
Low-level
output voltage
Ion
. 60
_
Low-level
output leakage
current
C9
200
~ZH'
~
High-level
input current
and receiver
output leakage
current
100
. . ,.
:;;;Ii _ _ %
...
Parameter
Symbol
T~stCondition
High-level
input voltage
R.equttements
Min.
Max.
Units
2.0
v
Cl,C2
v
Cl,C2
Low-level
input voltage
Test
Cin:uit
0.8
IEnable=0.8 V, Select=0.8 V
lEnable=2.0 V, Select=2.Q V
)Enable=5.5 V, SeIect=5.5 V
4Enable=2.0 V, Select =2.4 V
~Enable=0.8 V, Select =2.0 V
'Enable =0.4 V, Select=OA V
'1m total consists of 40 ~ (maximum) and Ioz 20 J.LA (maximum) leakage current in the highimpedance state.
'Applies to all possible combinations of VIH and VIL at 0.8 V or 2.0 V
Table 5 • DC021 Enable and Select Input de Parameters
Parameter
Symbol
Test Condition
Requirements
Min.
High-l~l
Units
Max.
Cl,C2
V
Cl,C2
Enable or Select
inputl
Low-level
input voltage
V1L
Enable or Select
inputl
High-level
input current
1m
Vee = 5.25 V
Enable=2.4 V
Enable input
80
rnA
Enable = 5.5 V
Enable input
100
rnA
Select =2.4 V
Select Input
80
rnA
Select = 5.5 V
Select input
100
rnA
Low-level
input current
Input diode, damp voltage
IlL
2.0
V
Vm
input voltage
C4
Vee = 5.25 V
Enable or Select
input=OA V
VI
0.8
Vec =5.0V ±5%2
Enable = - 18 rnA
Select = - 18 rnA
Driver in = - 18 rnA
C5
-0.4
Confidential and Proprietary
rnA
C3
-1.2
IApplies to all possible combinations of VIH and V1L atO.g V or 2.0 V.
zAmbient temperature is 25°c' One input at a time.
4-288
Test
Circuit
V
-
DC021
ac Electrical Characteristics
The propagation delays for the receiver input and output signals are listed in Table 6 and the
waveforms referenced in the table are shown in Figures 3 and 4. The load circuits referenced in the
table and used in the delay measurements are shown in Figure 8.
RECEIVER IN
+-_...
RECEIVER...;O;.;:V;.;.T_ _ _
--1.5V
_-+-J. --------VOL
1+--001-- tR lH
tR AND IF
=
10 os BETWEEN 10% AND 90% LEVELS.
REFER TO FIGURE 8. LOAD A FOR OUTPUT CIRCUIT.
Figure 3 • DC021 Receiver Input to Output Propagation Delays
_-----3.0 V
ENABLE
----..:----------oV
TTL OUTPUT
RECEIVER IN = 2.4 V
TIL OUTPUT
RECEIVER IN = 0.8 V
,...---1.5V
51Cl05ED
S20PEN
-1
-------VOl +O.5V
tpZH
- - ~ - -ItOH -0.5
51 OPEN.
I
52 CLOSED
V
'-----1.5 V
_":""'-.J_._ - ----------~- - - -
-c -0 V
SI 8. S2 CLOSED
REFER TO FIGURE 8, LOAD B FOR OUTPUT CIRCUIT
Figure 4 • DC021 Receiver Enable and Disable Propagation Delays
ConfidentiallUld Proprietary
4-289
...
DCOll
The receiver inp4t waveforms for the noise immunity test are shown in Figu~ 5. The values
indicated are for no response at the output. The load.circuit referenc~ in Figure 5 and used in the
delay measurements is shown in Figure 8.
tR AND 'F ; 3.2 ns + 10% BETWEEN 10% AND 90% LEVELS.
RECEIVER OUTPUT> 2.2 V
WAVEFORM A
'R AND IF
= 2.4 ns +10% BETWEEN
10% AND 90% lEVELS.
RECEIVER OUTPUT> 2.2 V
WAVEFORM B
tR AND IF = 3.2 ns
± 1 0% BETWEEN
10% AN D 90% lEVELS.
RECEIVER OUTPUT> 0.7 V
WAVEFORM C
IR AND 'F
= 2.4 ns ±10% BETWEEN
10% AND 90% LEVELS.
RECEIVER OUTPUT). 0.7 V
WAVEFORM 0
REFER TO FIGURE 8. LOAD 8 FOR OUTPUT CIRCUIT. (S 1 AND S2 CLOSED)
Figure 5 • De021 Noise Immunity Input Waveforms
4·290
Confidential and Proprietary
-
DC021
Table 6 • D(;021 Receiver IIC-......
39011
TEST
_J.-....,.._ POINT
FROM
OUTPUT>--r~-.--~~~
1600n
ALL DIODES
ARE IN3064
LOAD A-OPEN COLLECTOR CIRCUIT
LOADS-THREE·STATE TTL CIRCUIT
VCC
FROM
OUTPUT
9Hl
TEST
>-............;1-......,..._ POI NT
LOAD C·OPEN·COlLECTOR CIRCUIT
Figure 8 • DC021 Output Load Circuits
Mechanical Configuration
The physical dimensions of the DC021 20-pin DIP are shown in Appendix E.
4-294
· Section .5-Mass-storage devices
The mass-storage devices are used in the development of disk and tape drive interfaces.
De018 Seritllizer/Deseritllizer Logjc-The DCOlS is a 40-pin DIP bipolar device that converts serial
data from a drive into parallel data and parallel data into serial data.
DC024 Encoder/Decoder Logic-The DC024 is a 28-pinDIP device that encodes and decodes the
information between the head electronics of a mass-storage device and the logic of the DC016
serializer/deserializer.
DC309 Reed Solomon Generator for BCC-The DC309 is a 28-pin DIP dynamic NMOS device that
implements a Reed Solomon error correction code (ECC).
Confidential and Proprietary
-------.----~."-.."-.-
. Features
• Converts serillI data into parallel data and ,pa.nij}el
data into serial data.
,
"
" "
":
''''
-,-,
~'--,
• Corre1ationlogicprovides autosum capabilities.
• Two speed variations available. ,
• Selectabl~ word length of 8,10, 'W'J6 bits ..
. Description
'The OCOl8 ~rializer!deseri~er, contained in a 40.piq dual·inlitl~ pac~e,r(D~)t.lsc~ bipolar LSI
device developed for ~eind,i*-dpve co~tl'Ollers. I~ provides,!hecircults Ilfid 10ficreq~ to
convert serial da~ itlto p~dataandParaItefctatain~ ~~iiUda~. The J:)C(llS performs the
conversion at alninirnumSeriiU.bit time of 36 nanoS¢COnds. f~ 1 I~ Iisitnpll#ed bIOckcliagram
of De018.
. ..
.
....
UPP!:R
110<15>
SHIFT REG.
CONTROL
LOWER
SHIFT REG.
UPPER SHIFT REG.
7 9 15
CONTROL
CE
I'Oi'S!:
POM
WLSO
WLSl
SDIO
SDll
OUTPUT SHIFT
REG.MUX
OUTPUT
SHIFT
REG.
TSSCO
TSSDO
500
SCI
IlR
DR
m
!rom
SDtC
O/UR
CHIP
STATUS
PRDY
WRC
Figurj? 1 • DC018 Simpli/iedBlock Diagram
5-1
The De0l8 isaVallable.in the following variations depending on t,he clock speed required.
Clock Frequency
Digital Part No.
14.3 Megahertz (maximum)
19-17043-00
27.7 Megahertz (maximum)
19-17043-01
The DC018contains input logic that selects the serial data input line and parallel data word length,
and controls the conversion process. An upper and lower 16-bit shift register and associated logic
control the parallel I/O data transfers to and from the chip. The parallel data is available from threestate drivers circuits. The serial data outputs are available from the output shift register. One
output provides TTL levels and is used for serially cascading two DC0l8 chips. The remaining
output provides three-state driver output levels that are externally controlled for the para1lelport
and serial port operation. An autostart feature allows the serial-ta-parallel conversion process to
begin upon recognition of a serial-input bit pattern.
Autocorrelation logic detects 9 serial-input bits out of 12 bits at clock frequencies up to 14.3
Megahertz. At clock frequencies from 14.3 to 27.7 Megahertz, the autocorrelation logic detects 10
serial-input bits out of 12 bits. During the shifting operations, the logic searches for a maximum of
5 bits that are in agreement. When the correlation is detected, the conVersion process occurs in any
one of the selectable word lengths of 8 bits, 10 bits, or 12 bits .
• Pin and Signal Description
This section provides a brief description of the input and output signals and power and ground
connections of the DCOlS 40-pin DIP. The pin assignments are identified in Figure 2 and
summarized in Table 1.
Vee
Tsseo
TTLGND
ACI5
TSSOO
O/UA
SOO
PROY
WRC
SOi'S'l:'
11007
11008
7
11006
11009
11005
110 10
11004
11011
11012
11002
11013
11001
11014
11000
11015
SOil
m
SOlO
POM
110 GNO
SOIC
,;m
~
CE
WLSl
GND
WLSO
TOP VIEW
Figure 2 • De018 Pin Assignments
5-2
Confidential and Proprietary
IlCOltr
Pin
Sipl
1
TTLCND
2
ACD
3
SCI
TTL ground-A TTL ground reference. Pin 1 con, neets to pin 20 in the shortest possible path.
input
Autocorrelator detect-Asserted by the sync byte
detector when li'sync byte is present. Used for test
P\U1?~es only.
'
"
Seri~dock-Data
is shifted into the shift register
011 the poSitive edgeqf ~ssignal.
,',
4
O/UR
output1
5
PRDY
output'
,
"'c,
Overrun/Underrun-Indicates that data has been
~dduring "Q ttansf~r on the ~elport, as
fon~r Cleared by the master reset pt\lse (Mi).
l.P~ in mode-Asserted to indicate an overrun
. condition in the parallel outmode-when the POM
sigtntl and parallel reaay(PRDy) Signill· are asserted
; "aOdthe data ready (DR) signal is not asserted within
the word time.
,2. Parallel out mOde.....Asserted tomdicate an
underrUn condition when POM signal is negated
and PlDY signal' is asserted, if the parallel input
strobea>il) is not asserted within the word time.
'1>~ ready-Indicates that the DCOlS is ready to
transfer or receive data as fOllows:
1. Asserted in the pa.mll.el out mode.(PaH asserted)
whefidata is available on pins JjO< 15:00> and if
t1ie~elout ~~tate enable .~ signal is
asserted. It is negated by the aSsertion of data
received (DR) if ~ is asserted.
2; As'serted in the parallel in mode (PaM negated)
when the DC018 is ready to receive parallel data and
the master reset (MR) is negated. It is negated by the
negative edge of the panillel input strobe {PLS}.
?~ If.cohditions 1 ap,d} do not ocQ):,PIIDY will be
negated before the parrulel data beCOt11~S invalid and
or underrun .condition. (O/UR) .will be
an'
.• indiC1lted.
overrun
6
DR
Data i:eceiyed~ Asserte;d. by the tlSer to indicate that
theparatIel data on pins 1/0<15:00> has been
received. In the panillel out mode (POM asserted)
wh~n the data is available and the POI'SE signal is
.asserted, the DC0l8 asserts the PRDY line. After the
data is received, the assertion edge of the DR signal
negates the PRDY signal.
Confidential and Proprietary
-
Pin
Signal
7-14
1/0<15:00> inputsVoutpu~
00018
Input/OutpUt
27~34
15
SDIl
input l
16
smo
input 1
De£initiOn/PLlIlWo(l
.Pa1'llllel data irlput/~utPut-SiXteetlpamlleI datq
lines that provide controllable t~"state level outputs and include TTL level gates for the parallel
input signals. ThePOM input selects the function of
the lines .
. Serial data in 1-Serial data input channel 1
selected when the serial data input control (SDIC)
signal is high.
Serial data in O-Serial data input channel 0
selected when the the smc signal is low.
17
SDIC
inputl
Serim data input control-When high, this input
selects serial data input channel 1 (SmO) and when
low it selects serial data input channel 0 (SDIO).
18
POTSE
input l
Parallel output three-state enable-Asserted to
enable. and negated to disable the parallel three-state
outputs I/O < 15 :00 > ).
19
CE
input l
Counter enable-In the parallel.in, serial·out mode,
this line is asserted to allow the next positive edge of
the dock input (SCI) to enable the internal bit-rate
counter. In the serial-in, parallel-out mode, this line
is asserted to permit the detection of a sync pattern
of the serial data to enable the bit-rate counter.
20
GND
input
Ground-A ground reference. Pin 20 connects to
pin 1 in the shortest connection possible.
21
WLSO
input l
Word length select O-Used with word length select
1 to select the length of the parallel data output
word, as follows:
WLSI
Word length
WLSO
H
H
L
H
L
H
16 bits
10 bits
8 bits
22
WLS1
input!
Word length select 1-Refer to word length select 0
description.
23
MR
input1
Master reset-Asserted to reset all internal registers
and counters in the DC018.
24
I/OGND·
input
Input/Output ground-An isolated ground referenee for parallel outputs I/O < 15:00> .
25
roM
input l
Parallel out mode-Asserted to select the serial-in,
parallel-out mode and negated to select the parallelin; serial-out mode.
5·4
Confidential and Proprietary
Pin
Input/Output
Definition/Funetion
Pal:aneI strobe-In the parallel-in, ~ial-outmode"
this signal is asserted after the parallelteady(PRDY) '.
is asserted, to· Ibad thepatallel data on lines
26
1/0< l,';i:OO> into the
p~elregistets()t
the
DC01S. TheiPRDYsigna}fnegated when ~signal
becomes low b¢foi:e, the·nei;tj:ycie can <*:Ut
,
input
35
36
'-,/','.",,;,
,,\,.',
Serial-out three-state enable......Assertedtoenable
and negated to disable the outputs of three-state
serial data out (T58DO) and serial clock out
(TSSCO) lines.
l
,.. . Word rate clock" 'It dbCk output with a '50 percent
duty cycle that is decoded from the modulo n (n= 8
bit, 10 bit, or 16 bit) counter with a clock period of n
WRC
bit times. The me sig~i~.~ser~.:'¥~thl!t C()t:WX o/~
, ~$Uldneg""~~t1!/~ pi~t.jplet
i
37
soo
output
'
,
.
'
.'
SeriaIdata(jutpu.~l!Jsedtocas same
serial clock input (SCI). It exhibits the same delay
characteristics ItS· .theserlald!lialqptit; ,(Sbl(j~
SnU) and the'"I!O<15:00;> ()Utputsasdesaibed
for.the rssnQ sigpal, .'l1iem'inim ·J:'lOpigation
um
delay from 'Whenthe$~al,~.SCIsisn*,l.,i.nput
becornes,high1evet~acm~m~ei?tlte SD() level,
is greater than .the ~uniho1d tWeoi} the, SOIO
or SDIl inputs with respect to the SCI mput.
38
Th.tee,state .'. seii~·il:i!ata . '.6ijt·C6n~11~!:l';'f:&"'ih~
·~ta.· t1'ansi~ionsonthisJine are
Tssno
SOTSE signal.
synch±oni~4¥tfiiilwp(lSitive. edges of Jhe'1's'SCO
signal.
.
,', , ' .
'
.
39
~stateserial~ock out--A seri.al clOck output
TSSCO
&atijjad~ayed sa-i8Iclock inputiSCF~;The
delay' conforms to the propagation time incurred by
the Tssno output; ~~.I. t~j,posid~going
.• ~Qge ohhe~~p~ is.~yn~~ ~i,thT~Sn,()
i;)utput,pit~. '!he dopkoutput .isCQtltroUeQ J.;>eclle
sors:E s i g n a l . · '
40
input
.... ..
.....
."
Voltage-Power supply de voltage
lTTL levels.
2Three-state.
Confidential and Proprietary
5-5
" - - -...
--~--"""",~--..----'
-
. Specifications
The mechanical. electriaaJ., and envirOnm~ntal ch~risHcs and specifications of t~ De018 are
described in the following pa,ragraphs. Th~ test ~onQitions for the electrical values are as follows
unless specified otherwise .. Refer to Digital specification A-PS-2100002-GS for detailed specificationsofthe DeOl8".·
.
• Supply voltage (V~J: 5.0 V ±5%
Mechanical Configuration
The physical dimensions of the De018 40-pinDIP are contained in Appendix E.
<
'
,
"
,
Ahsblute Maxitnum Ratings
Stresses greater than the absolutelllaXimum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings £Or extended periods may adversely affect the
reliability of the device.
° Supply voltage (Vcc): 7.0 V
• Input voltage (VI): 5.5 V
o$toragetetnperature (T,): -65°C to 125°C
Re~mmended Operatlng Conditions
··.Supplyvoli:age (Vee): 5.0 V ±5%
° Supplycurrent (Ic;d: 425 mA(maximum)
• Relative. humidity: 10% to 95% (noncoqdensing)
de Electrical Characteristics
The dc electrical parameters of the De018 for the operating voltage and temperature ranges
listed in Table 2. Refer to Appendix Ctor the test circuit configurations referenced in
specified
the table.
.
are
5-6
Confidential and Proprietary
",
Parameter
" 'AWe?' Dc018dcInPut aruf()utput Parameters
Test
Symbol Condition
~t
" ,Iil,
~t
Max.
Min.
2.0
High-level
input voltage
Vm
Table 4
Low-level
inputvriltlige
VII.
Tab!e4
Iriput clamp
voltage
VI
!Vcc""'open
II=-U ,trul
-.1.5
High-level
output voltage
VOH
Vcc=4.7V
2.4
0.8
-
<'
Units
Chcuit
V
C1
V
cr
·v
V
Cl
V
C2
lot
Table 4
Low-l~
outp1,ltVoltage
YOL
Vq;=4.75 V
0.5
102
Table 4
Input current
at maxUnum
input voltage
1;
High-level
input current
,IIH
Vcc ... 5.25 V
V1 ..;;z.4
Low-level
input cartent
k
Vcc=~,,~'
Short-circuit
ouqlUtcw:rent
los
High-ilnpedence
state output
current
Ion
Voc=:5.~25V
Vi
""1";0
,,'V
mA
1lA,
,
; ..A,
C4
C4
,lllA,/
C5
mA
C6
IlA
C8
VI =0,4
Vcc =5.25 V'
-100'
-5.0'
;..,
Vcc=5.25 V
Vo "",O.4 V
TabIe4
10m
,C9
Vcc =5,'}SV
VQ =2.4: V
ThbIe4
Supply current
Icc
Input
capacitance
Cin
Vcc =5.25N
42,
,e7
8.0
pF
110=-1 rnA for Soo, -6.5 rnA for TSCCO and TSSDO, -400 rnA for all other outputs.
'10 = 1 rnA for ACD, 20 rnA for TSSCO, TSSDO, and SDO, 5 mA for all other outputs.
'Im=20 IlA for smo, SDU, MR, and ~ 40 IlA for SCI, SDIC, CE, POM, DR, PLS, WLSO, and
WLS1, 80 ~ for POi"'SE, -140 ~for 1<15:00>.
411L =-400 IlA for smo, SCll, sarSE, 1< 15:00>, and DR, -800
WLSO, WLS1, MR, and'i5O'fSE, -1.0 mA for SDIC.
IlA for SCI,
CE, POM,PLS,
'Not more than one output shall be short-circuited at a time and the duration of the short shall not
exceed 1 second.
5-7
-
·(108 for WRC) Failure to per£o.rfIl~ ~st.whe:re .indi~ated on Tagle .l.wm cause the WRC output to
change states. los for.ACD,.. .,.20 rnA. (nimimwn) and -50 rnA (maximum).
7Ion =501lA, 10m =-50 IlA forT$SCO ahciTSSDO, Ion =IlL, IoZJI= It for 1< 15:00>.
ac Electtic:al Characteristics
The input and output signal timing for the DCOl8 is shown .in Figures 3 through 10. The'
propagation delays and conditions for the symbols on the timing diagrams are described in Thbles 3
through 8. Refer to Appendix D for the input and output voltage waveform parameters used for
measuring the signal propagation delays. Figure 11 shows the load circuit for the TTL outputs and
the load circuit and waveforms for the three-state outputs.
SCI
PRDY--+-....I
DR--~_+~~. .~~~~~~~~~~~~~~~r_
POTSE
-------f--·
I
--\-f--,
I
, I
I
1
110 <15:00>
-f::2!!1:~=====3L
__./====:=J23~~=-::
,-
DfUR-~---------I,
/""lI
r- - - t - . .
).
\-lr-"",,,
seE
NOTE
i--@,-....
·I..o--@>---l
------;1
I I....____~
FPM ASSERTED
NOTE: TWO ARROWS DEFINING AN EDGE IMPLY THF
EDGE OCCURSWHEN BOTH CONDITIONS ARE SATISF lED.'
Figure 3 • DC018 Signal Timing A
5-8
I
r--------------........
WRC _ _-....I
DR
I
I
I
ConfidentiaIand Proprietalj
, Taite)· DCOl8 SijW TJi:Dirig A ~s "
Symbol
Propaption Delay' (ns)
c..=15 pF
c..=SOpF
Min.
Max.
Min.
Max.
Conditions
1
55
2
30
3
0
0
-
4
6
7
~ •• ~<
DR can be asserted up to
(m-1)(ta)....;t..... (nanosecobds)
30
36
" ...
18
18
after the negative-going edge of SCI
where;
m=8, 10, or 16 bits,
tcp = input clock period,
t....,';';18ns (as s~,
8
1S
9
25
10
70
If DR is not asserted during the previous
word cycle, O/UR will be asserted by the
DCOlS.
50
11
12
WRC will be negated by DC018·inthe
middle of the 8 (4th bit), 10 (5th bit),
or 16 (8th bit) word cycle.
13
Pulse width low
40
40
14
Pulse width high
40
40
15
Valid data will be present on
I/O < 15:00 > before PRDY is asserted.
45
Confidential andl10prletary
50
5.0
5-9
DR
PRDY-~...,
Figure 4 • DC018 Signal Timing B
'liable 4· DC018 Signal Tunmg B Parameters
Symbol Conditions
Propagation Delay (ns)
~=15pF
Min.
1
Setup time
25
Setup time
40
4
.5-10
Ct=50pF
Min.
Max.
25
-
2
3
Max.
30
40
45
Confidential and Proprietary
,SCI
D / U R - T - - - - - - - -..fH..-~
\---------:--t-----.. . . .--
WRC--.......
EXPANDED DIAGRAM
.. ~
"o<,,:------...;.·.p;-......;v~:::4r~-!-A-};.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .---POM NEGATED
Figure,5 • De018 Signal TimintC
Table ,. DeolS Sipal illlling C Pardteters
~De1ay(ns)
Symbol Conditions
CL =1SpF
Min.
Max.
Cr.='OpF
Min.
Max:.
1
55
2
35
3
50
4
WRC will be negated by DCOlS in the
middle of the 4th bit, 5th bit, or 8th
bit word cycle depending on the 8, 10,
or 16 bit (respectively) word length
45
50
selected.
5
30
Confidential'andProprletary
5·11
-
OCOll"
Symbql€:oQditions .
I'l'o~tion I>et.y(,.);i
4=15 pF
C~=50pF
.'
Min.
Max.
MaX.
Min.
6
18
18
0
0
PLS·aan he asserted up to
(m-1)(to)-~nanoseconds
after the negative-going edge of SCI
where:
m=8, 10, or 16 bits
to ... input clock period
doad = 18 ns (as specified)
7
8
If PLS is not asserted during the
previous word cycle, O/UR will
be asserted by the DC0l8.
9
If PIS isassereted, it must be
negated up to (m)(1:cp)-t...op
70
5.0
5.0
nanoseconds after the positive edge of
SCI where:
m=8, 10, or 16 bits
tep =input clock period
tsetup = 5 ns (as specified)
10
Pulse-width low
25
25
11
Setup time
40
40
12
Hold time
5-12
5.0
Confidential and Proprietary
5.0
~-----------@------------~
SCI--"";
SDI1,SDI0
""'""~"'"""'.fJ.''\;;,;;~--++-\-----''----''''''''-
Tssoo-...!:!!:~";"",,t1iC.==t=::S~===~H7:~:
.sole
SOO
----~~--------~~~~~~~~--------
Figure 6 • DC018 Signal Timing D
Symbol Descripticm,·
~tion~ay(ns)
19~11Q·4)411
1,..1,7041.00
Ct=tspF.
4=50pE
15
}O
17
30
30
5
5
5
12
"12
12
c.,=;OpF
Min. Mu. Min. Max. Min. Max. Min. Max.
1
SCll!ptlI~.width low .
'1'
2
SCIHpulse-wi4th high
17
5
3
SOlO or sm1 setup
time
4
SOlO or SDU
hold q!1le
12
scihigh to TSSCO
13
5
.......
>~,
33
13
4·t\);J';.pE
4(f '.'.13 ..... 57"
13
45
high
5a
8
8
10
10
6
8
8
10
10
20
25
20
25
7
S5TSE lowto
TSSCO (active)
0>nfiPential and Pmptietary
5·13
PropagatiorideJay (ns)
Symbol Description
19.17043·00
19·17043·01
CL =15pF
Ct=15 pF
CL =50pF
CL=SOpF
Min. Max. Min. Maxi Min. Max. Min. Max.
20
25
25
.20
8
sorSElowto
TSSDO (active) .
9
Setup time
25
10
SCI to SDO*
13
11
SorSE high to , ..
TSSCO (Hi-z)
18
18
12
SOTSEro 1'8SOO
18
18
13
Input clock period
(SCI)
36
14
SCl low to TSSCO low
13
14a
25
33
13
25
40
13
40
5
5
37
13
70
36
33
25
13
45
70
37
13
5
13
45
5
*Propagation de1aycontroned to allow cascading of two or more DC018 chips using a common
clock.
FI RST POSITIVE
GOING CLOCK
EDGE AFTER CE
THAT IS
~---"""'-,-.--....,
LAST NEGATIVE
GOtNGClOCK
EDGE
RECOGNIZED BY
CHIP
SCI
WuroOR--------~----...............----~--~~ ~----~
~~,-r----
WLSl
POM _________________
-J~~
__
--------~~
PRDY (WHEN POM IS.NEGATIVEI
CE
PRDY
\
.POM
\
rn
®
~~
Figure 7· DC018 Signal Timing E
5·14
Confidential and Proprietary
~------------------~~T~----------------
1/0<15:0>
M1t
(SEE.FIGURE 7'FOR
MORI! DETAILED TIMING
INFORMATION OF THE POM
SIGNALI
SDll0R - _ _ _ _ _-:-_ _ _ _ _ _ _ _ _ _........-..
SDIO
(SEE fIGUR':& FOR MORE
DETAILED riMING INFl'I INFORMATION
OF THE SOIO.SDItSIGNAI.~.
~
NOTE:
FAILURE TO SATISFY THIS
REQUIREMENT (161 MAY CAUSE
A~YN(lHftONI2li R~'OBL,EM
; IN'[MHP.·· . "
~*",'Dehly(fi')
'4=':'l5pF'
Min.. Max.
. -,,-,-';:'>:,'., -
'4= 50 pF
Min.
Max•
1
For initialization
60
60
2
Pulse-width low
80
80
3
If POM is negated, PRDY becomes high
after MRL is negated. If POM is asserted,
PRDY remains negated until the sync
byte is detected.
4
50
75
75
5
Setup time
50
50
6
Setup time
25
25
7
Hold time
15
15
·5-15
PtopagationDetay .(nil) ...
CL =15pF·
Ct=50pF
Min.
Max.
Min.
Max.
Symbol Conditions
8
PRDY must ~ negatedbefere POM can
o
o
85
85
0
0
25
25
be negated to assure the validity of the
data.
9
10
11
Pulse-width low*
12
Figure 11
Tm
TLz
34
41
40
50
55
13
14
Hold time
15
Hold time
3.5
30
3.5
30
*Refer to Figure 7 and notes for additional PLS signal information.
SCI
SDIO or 1
SDll
-~-..,
~--------------------~~
WRC----------------------------------~~------------~~
Figure 9 • D(018 Signal Timing F
Confidential and Proprietary
.....~
Symbol Conditions
Table 8 • OC018 Signal Timing F Patam$rS
Propagation Delay(ns)
~=15pF·
Min.
1
Max.
Signal ACi5 wiJIhe asserted after the
12th bit the ~nc byte is shifted in.
Max.
70
of
2
3
~=50pF
Min.
70
The sync byte ~tor will nigger when
a minimum o£9, 10, 11, or 12;bits are in
a.greement or wl;tenlO, 11, or 12 are
in a.greement for the specified clock rate.
9
10
SCI
PLS - - . . ,
PRDY ---.......0...+-....
SDO
--~-----.------------~~~~---------'
figure 10 • DC018SignaiTiming G
C~nfidential and Ptuprietary
5-17
...
TEST
POINT
TEST
POINT
2KQ
FROM
OUTPUT
FROM
OUTPUT
ALL
DIODES
FD7000R
EQUIVALENT
15 pF
15pF
ALL
DIODES
FD700 OR
EQUIVALENT
R2
52
LOAD A TTL OUTPUTS
Rl u 2Kn, R2=lKn FOR
PI N5 7·14, 27·34
Rl=26On, R2= 1KS"! FOR PIN
PINS 38. 39.
LOAD B THREE·STATE OUTPUT
ff"-------3V
OUTPUT
CONTROL
~
L lLOW LEVEL
ENABLING)
0
V""T_(_N_O_T_E_3_1_ _ _ _- - '
tZLr-WAVEFORM
,---+---..d------
(NOTE 11
51 CLOSED
S20PEN
tZH
WAVEFORM 2
(NOTE 2)
~~ ________ °V
tLZ
Co ~~ ~~SED
O.SV
4 . 5V
......--i--l.5V
VTlNOTE 3)
Ir-------\---t-- FO.
tHZ
f
51 OPEN
_ _._S...
2..;,C...
L...
OS
...E;.;DJ.
-----l--I----
VOL
0.5 V
1
VTINOTE 3)
____. _ OV
1.5 V
Sl AND
S2CLOSED
NOTES:
WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT
THE OUTPUT IS LOW EXCEPT WHEN DISABLED BY THE OUTPUT CONTROL
2
WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT
THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY THE OUTPUT CONTROL
3
VT=1.3 V FOR ALL OUTPUT PINS EXCEPT 3B AND 39
VT~
1.5 V FOR PINS 38 AND 39
THREE·STATE OUTPUT WAVEFORMS
Figure 11 • DC018 Output Load Circuits and Waveforms
5-18
5V
~VOH
Confidential andPtoI?rietary
•
~ -rate encoder/decoder algoithm for
mass-storage devices
• Compatible with the DC018 Serializer/Deserializer
• TTL and ECL inputs and outputs
• Phase detector and counter/divider
• Diagnostic mode operation
. Description
The DC024 encoder/decoder, containedrin a.28-pin duahinline package (DIP), provides the
functions required to encode and decode,j:he data betweenlhe head electronics o£a mass-storage
device and the logic of the DC018 seril1i~/deserializer.'.ln'addition to the encoder and decoder
logic, the DC024 contains phase deteetot~.'dividers, and&attoUogic for a phased-locked loop. A
test mode is provided to allow the DBO~4 and DC018 SEf1a1l'zer)Deserializer to be operated in an
end-around configuration for diagnoStief purposes. F~'l is a simplified block diagram of
DC024.
'
The DC024 performs the ~ -rate encciamg,ldecoding~oiifum for mass storage products. It
operates with TTL and ECL level inputs and outputs'and requiresll. .5 V and -.5.2 V power supply.
EflO+/EOO-
Figure 1 • DC024 Simplif:ea Block Diagram
5-19
This section provides a brief description of the input and output signals and power and ground
connections of the DC024 28-pin DIP. The pin assignments are identified in 'Figure2a1'ld
summarized in Table 1.
ERD+
EROVCK+
VCKup+
UpGND
ON+
VCK
owc
DIAG
ORC
ORO
Vet
GND
0111-
E,WD+
EWDVEE
GND
CLR
DWD
EWe
Al
AO
TOP VIew
Figure 2 • DC024 Pin Assignments
;-:20
Confidential and Proprietary
_..
28
ERD+'
27
ERD-
u
DWD
inpUtsl
EnCoded read data---A signal from the read circuits. Each flux
reversal to theread'cireuitsresruts in a pulse input on this line.
During m0derebeing
Written: oij the media.'
'
••••.• ".
15
16
",.
".'.
.
.
.
l)<:ood«tiW'ri~cl~k-An!.t with It clock frequency of one
~e;b.¢a.chde~ writ~~tabit. When writing, this signal
is .~ of~inpu.tS.tO th,e··phase detector. An internal loop signal
o£;the· sarot.~~nc)t and·phase when locked clocks the
.decpd~ ~ite, da~~ip.tQ~~~This:inputmUSt be fPtmected
~ytoJM·~#te4ecl~.source or indirectly through the
d(:~~.lt'~apnotoe uSc@directlyto clock the decoded write
data into;y, ,_;;'
the DC024.
.
,
A()
Al
....
'\ ~>: i
, J
inpu~"
2
I . . .,
,"
"J,
0','"
S\ "\
. Al "
,()
b
Mti(f~
.'f.:(~Il-)
B' (p~l\1ble-truneate),
l'
.~(4~)
1
D{~)
i.
II
CLEAR
inpuf,.
Clear-Willen,assertedjiallD~24 storage. elementS'i1re .cleared
and the logic is set to a known state.
26
25
VCK+
VCK":
inputs'
Voltage control ~- The di£t~ntia1 i;nput from an external
voltage controlled oscillator, Provides a frequency of two ~cles
rfot .~.encodeddata:bit(tbree~esiper detodeddata bit).···
1
VCK
inpuf
Voltage dock-Used during diagnostic mode as th~pful~
locked loop feedback clock.
3
DIAG
inpue
Diagnostic mode-When asserted, the DC024. enterstlJ.~~iag
nostic mode. The VCK clock signal is used as a substitute'for the
VCK + IVCK~clockinput as the feedback dOck £Orr the phaselockedloop.
outputs'
Up freqtieney::.....The phase deteCtOr output sigt)alsthai: causes
the. voltagecontrolledosCillat<>r . 1»' increase~~frequency. The
duration of the assertion of this signal is proportional to the
magnitude of the phase error.
24
23
UP+
'UP-
Pin
. Signal
21
20
DN+
. DN-
14
EWC
Encoded write dock-A dock output from the phase-locked
loop circuit with one cycle for each encoded write data bit.
19
18
EWD + .' outputs1
EWD-
Encoded write datl:! __Acombined output of the NRZ encoded
write data and the encoded write clock. Every "one" input of the
NRZ encoded write data signal causes the· outputs' to change
4
DRC:
Down frequerit:y:c..::. The ph!!Se 'detecror'oo.tput that· causes the'
voltage controll~d oscillator to decrease itsfrequency,The dura.
rion of the ~sserton of th~signal is proportional to the magnitilde of the phase error,
outputs 1
. Decoded read clock-This sigoal is a clock output that is phase
locked to the external input of phase-locked loop (ERD + /ERDwhen decoding or' Dwe whenencodingj 'at iii £requericy of one
cycle for a decoded data bit. Used to clock the decoded read data
from the DC024 during read operations and as a clock Source
into a deseri~zer during write operations.
outpue
Dec~ded read data-This signal is an NRZ serial output of the
DC024 that is decoded from the serial input to the when reading
encoded 2/3 rate) data. from the peripheral. This signal is
normally used as an input to II deserializer. While writing to the
media, this signal is not disabled and shifts the decoded data
(DWD) out delayed by 10.5 VCK+/VCK- cycles.
5
6,7
Vee
input
8,9
GND
input
17
VIlE
input
Voltage-Power supply 5 Vdc.
.. Ground-Ground reference fo~ 5 Vdc.
Voltage-Power supply -5.2 Vo
'Ground,.....Groundreference for the -2.5 V..
1-,U, GND
22
'ECLleveIs
2TTL levels
'it'
)The multiple power and ground pins of the'DC024 must he properly connected to assure proper
operation,
• Operation"
TheOC024encooer/decoder consists of three main logic sections-a phase detector, a counter/
divider; and an encoder/decoder. It implements the 93-ratemodtIlation code shown in Table 2. In
the bit seql.leI),<:¢~,t,h¢ bits at the left are. the first in time.
Note: Sign@> tefet;eoc;ed it).. the descriptions that. QI;e e.pclosed in brackets [ ] are internal signals
only.
5·22
Confidential and· Pn>prietary
Table.2 ·nc024 2/3·Rate Modulation ~
Data Bits
00
01
10
010
1100
xooooo
1101
XOOOOI
1110
010000
1111
010001
*X =The complement of the l~t bit of thepn!viously encoded data.
Phase Detector '
The phase deti!ctor p~rates in o~·of t~ four. m!Xies ~~d.br;the 1\O.,and.Alinputs, These
inputs are decoded brihe 'counteildividedogic to 'Select themooelr listed ifitnihle 3', .
Mode
Mode;eontrol
At
AO
A
0
0
··ERb+/ERD'"
B
0
1
ERD+/ERD-
C
1
1
.~Rq+lERD-
D
1
0
{
.
[V2~6]""'"
Preamble
[VCR/6]
PreamBle-Truncate
Read/decode
[VCK/3]
Write/encode
*Signals enclosed in brackets [1 are internal to the DC024 ,
~,J\ . .·. This,lllog~,·~·.alX3~tivelo~~'inru}~::'J:~:p~,~~~,~~'~.f~.~,£~~is~;of
flip~fll)p~,E1q~ !\~E.~q7, ~ffirfl9PE,:lQ~ is~t~W~ ~isi~*~~~~~~.l~,g~~p~t
divided by 6. Flip·flop E107 is set by tlJetrll~,~;9f~ ~~'(~9fi¥~fH9t9Pcil:lp}lt[l!~~]~
Both flip-flops are cleared immediately after they are both set. The output of flip-flop E108
indicates that the VCK clock frequency is low and is used to increase the charge of a filter network.
Flip-flop E 107 indicates that the VCK frequency is high and is used to decrease the charge on a
filter network. At the statt of a read operation, a special data pattern designated as the "preamble"
is decoded to establish a phase lock before the normal data is read. The decoded preamble consists
of all zeros. When encoded, the bit pattern is 100, 100, 100 etc. A lower frequency clock from the
counter/divider is used as feedback to the phase detector when the preamble is expected.
Con£identiarWPrO~tibtary
.5-23
ON -
CLR r--::>--+----,
Up·
VCK+
EWC
ORC
Figure 3 • Mode A Phase Detktor Operation
Mode B-Figure 4 shows the logic for mode B. When the phase of the loop is locked, a lost bit in
the preamble data, indicating an error condition, could cause the loop to differ by one or more bits.
A truncate function is provided 'so the phase'detector can be resetby a signal ffum the counter/
divider after on~-half cycle of the feedback signal. This function should notbeused until frequency
lock is established as it may extend rime to frequency lock.
r
.
5-24
Confidential and Proprietary
[TRUNC ClK HI!
[TRUNC ClR HI! --/--.,...........--'
EWC
ORe
[TRUNC ClR HI
[TRUNC CKl HI
[PT1J __~______~~~~~__~__~__~~~~~~-J~________
[PT2J----________-"~----------------------------~--.----(VCK/6]
[EROll
ON·
UP-
Figure 4 • Mode B Phase fJeteeto1'~vn
Confidet;ltial·an4 Proprietary
5-25
-
Mode C-During a decoding (read) operation, the data input to the phased locked loop contains
ones (pulses) and zeros (missing pulses}. Figure 5 shows the logic circuit and signal timing for mode
B. The leading edge of the encoded read data [ERDL] pulses are used by the phase detector to
prevent missing pulses from being interpreted as late pulses. This is performed by allowing a phase
comparison to take place on the trailing edge.
[HI
0
Eloe
[H]
[VCK/2]
ClK ti
ON·
CLR
[H]
D
El07
ClK Q
CLR
[ERDLI
[PT3] ---><---_
EWC
ORC
[PT3] - - - ' - - - . . . . . ,
[VCK/2]
[ERDLJ
ON
Up·
Figure 5 • Mode C Phase Detector Operation
5-26
Confidential and Proprietary
. Up·
Mode D-'The operation of the phase detector during the encoding (write) operationjsYII~to
the decoding(Rad)~tion except that the encoded Rad data{ERP +/ERD--)si~~& .replaced
with the deooded writ¢clock (l5WC)slgnal.Figure 6 shows the wgic circuit andsign,alti$i,ngfor
mode D.· Feedback to the phase detector is provided by a[VCK/3] signalfromthecOWlt~dividel'
logic.
ORe
Figure 6· Mode D Phase Detector Operation
Confidentia1'and:Ptoprietatj
'·27
Countet/Divider
The ¢01:U1ter/divider provides the timing and clock signals to control the operation of the DC024
andfe~ckto the phase detector. The logic receives a differentialfnput (VCK+ and VCK-) from
an externalvoltage~(jntrolled oscillator during normal modes of operation. The counter/divider· .
provides divide-by-two [VCK/2], divide-by-three [VCK/3], and divide-by-six [VCK/6] clock pulse to
the phase detector depending on the operating mode selected. During diagnostic mode, the
internal VCK signal is used as the feedback clock to the phase detector and the external signals are
inhibited.
Encoder/Dewder
The encoder/decoder logic implements the ¥.I-rate modulation code and consists of a 4-bit fast
serial shift register (Fast SR), a 4-bitslow serial shift register (Slow SR), a decode logic matrix, and
an encode logic matrix. The encoded shift register (fast) is clocked by the clock [VCK/2] signal from
the counter/divider and transfers the encoded data stream coming from or going to the disk
interface. The decoded shift register (slow) is clocked by the [VCK/3] signal from the counterI
divider and transfers the decoded data stream coming from or going to the DC024. The decoding
function and signal timing is shown in Figure 7. During this function, the serial data read from a
disk is synchronized by the [VCK/2] clock pulses and seriallyloaded into the encoded shift register.
Every three bits shifted into this register are decoded to two Qitsiby the decoder matrix. The
decoder matrix transfers the information in parallel to the decoded shift register. The data from
this register is serially shifted to the DC024 logic functions.
[ENCODED DATA IN]
[VCKI2]
(LOAD H)
ORO
(ORC INT)
SHIFT
I
,
SHIFT
SHIFT
I
SHIFT
I
SHIFT
SHIFT
I
I
[VCK/2]
VCK+
[ORC INT]
I
[LOAD HJ - - - ,
LOAD
SHIFT
I
LOAD
I
SHIFT
Figure 7· DC024 Decode Function and Signal Timing
5-28
Confit!ential. ant! .Proprietary
DC024
The encoding opemtion and signal tinring are shown ipFigure 8. A serial data stream is transferred
serially to the decoded shift register. Every two bits shifted into this register are encoded to three
bits by the encode logic matrix. This information is then transferred in parallel to the encoded shift
register that serially shifts the data to the disk interface.
IEWDH]
DWDH1-I~-'-"
LOAD
SHIFT
SHIFT
LOAD
I
I
I
I
SHIFT
,J
SHIFT
I
JVCKl21
[LOAD HJ
VCK+
[DRCINT1~
I
. 'SHIFT
r
I
1
SHIFT "
I
SHIFT
r
SHIFT
Figure 8· DC024 Encode Function and Signal Timing
When the mAG line is asserted, a special diagnostic function is enabled by connecting the encoded
shift register in an end-around configuration as shown in Figllre 9. This function may be used as an
open-loop test of the DC024 by bypassing the VCO controlled phase-locked loop. By selecting the
proper operating modes through AO and Allines, two serial bits on the DWD input can be shifted
into the decoded register, encoded through the encoded matrix, and loaded into the encoded shift
register. The end-around connection reshifts the encoded write data into the encoded register
which is then decoded through the decoded logic matrix. This information is then transferred in
parallel to the decoded shift register that serially shifts the data to the DRD output.
Confidential and· Proprietary
5-29
ORD
Figure 9 • DC024 Diagnostic Mode Function
The timing for a typical diagnostic mode operation is shown in Figure 10. Table 4 contains the
possible decoded write data input patterns and the expected decoded read data output patterns.
VCK
~
CLR
n
~
~
~ ~
~n ~R
~
~
n
n n~
Al
AO
DWD
Al
A2 A3
MI A5
A6
A7
I
I
Al A2
A3
II
ORO
ORe
~
81
A4 A5
~ ~
.1
a2
~
I 82 I B3184
rk!-
.3
85
B1
~
'X - UNDEFINED
Figure 10 • DC024 Typical Diagnostic Mode Signal Timing
'·30
Confidential and Proprietary
B6
871
II I
82
~
B3
84
85 bl
~
DC014'
'1llbl¢ lf o l)COl4 Typical~.Mode DeoodedDataPatterna
Write Data Input·
Read 0.18 Output
At
Al
A3
1\4
AS
A6
A7
a1
a2
83
0
1
1
1
0
0
X
1
1
0
0
1
1
X
1
0
X
1
1
1
X
0
1
0
1
0
X
1
1
1
X
0
1
J
0
0
X
0:
0
1
X
0
1
1
0
1
0
0
0
1
X
0
1
1
0
1
1
1
0
1
X
0
1
1
1
0
X
0
1
0
X
0
1
1
1
1
0
0
1
1
X
0
1
1'
I
1
1
1
X
X
0
0
0
0
0
0
"-'
""'"
X
X
0
0
0
1
0
0
0
X
X
0
0
,,0
1
1
0
0
X
X
0
0
1
0
X
1
0
0
X
X
0
1
0
0
X
0
0
1
X
X
0
1
0
1
0
()
0
1
X
X
0
1
0
1
1
1
0
1
X
X
0
1
1
0
X
0
1
0
X
X
0
1
1
1
0
0
1
1
X
X
0
1
1
1
1
1
1
1
X
X
1
0
0
0
X
1
1
0
IX represents eith~r a 1 or 0 sta,~. '.
.'.
".
.
Application of all input stafe~ lis~will ~ercise 93 p
OC024
DC024
GNC
CIRCUIT B
CIRCIUT A
VeE
Vee
VEE
Vee
UP+
DN+
EWO+
up-
~
Al
ON-
EWD-
AO
VCK
ClR
DC024
GNO
=
CIRCUIT C
DWOH
0C024
GND.
-2.0 V
~-
=
CIRCUIT 0
FigureV· DC024dc
Test Circuits'
Confidential and Proprietary
5·37
Vee
VEe
"VCCIMA)(I
"
VEE
Icc~
DC024
GND
CIRCUIT E
Vee
CIRCUIT F
VEEIMAI
tlEE
DWC
"T{'
OC024
V'N
GND
CIRCUIT G
or
VeL
J
Figure 14 • DC024 de Test Circuits
CQnfidentia! and,Pl'Oprietary
~
A1
AD
VCK
CLR
DC024
DWDH
GND
CIRCUIT H
Coadition ..
FiJurelCireuit
Reference
1. The Vmand VOl. for the TTL inputs· are determined by the test c;ircuit logic.
131A
2. Refer toTable 5 for ECL input conditions. VIH and V1Lapplied as indicated by
the test s¢q1,lence.l~/A
3. Each input is tested separately. Allotheriilputs mllst~~ tPe.testrequixe·
ments at the voltage speci.£iedin Table 5 forVIl;andVm•
..
B/A
4. The ECI.inputs are tested by differential pairs and the: inputvoltages.are \13/A,13/B,nC.
applied to· meet the VIII and VOL specifications of Tabl~ 5.
;r,
t3/D,14E,14/F
14/G
,.
5. 'the test conditions aielisted in Table5.
are
6,· The input condltions
determined'by the test sequencec.a:taPy¥Pl~·.•
within the range specified for Vrn and V{)L'
. . ~/B,n/c
7.. The input conditions are indicated in Table;: .,.,
13/D;14/E
8. Each input is tested separately with the remainingTI;L inp?ts connected to
GND.
..
.,
.'.
1~/D,14{H
9. Eachdiffe~ntial l.rtputpair is Jested 5ql~teli..•.
10. ·TheTTtoutputs ~ open.
. 13/D,14/E,14/F
11. The ~er supply current must not eXceed the limits spedl1edfutable 5 for
any combination.ofinput logic levels.
14/F.14/G
ac.Elfttrical Characteristics
.
.. . . ,
..
. ,.
. ..
The input and output signal timing for the DC024 is shown in Figures 15 through 19. The
propagatiOn delays and conditions for the symbols on the timmg-PiagramsaredeSd1bed in Tables7
and s: Refer to ApperidixD forihe si:a¥a.til m:: mput and QU~utvoJtag~wa~pim'parameter$
used for measuring the sigflalpropagationddays.. Figure20 shoWs the TTL and ECL,~utputwadihg
circuits used for measuring the ac parameters. The time measurements of TTL
at 1.5 V and dle
EeL mea$u~ments·are from the voltage;: crossing of the difiefeIi?a1'signlils.
are
Symbol
Definition
Max•
. VOltage control pulse
25
Early data ~dow margiD.
Late dam window margin
Confidential and, Proprietary
t ycp -2.5
t ycp -
3.0
t vcp -
3.0
5·39
...
OC()24·>·
Table 8· DC024 Signal TimingPetameters
Symbol·
Description
tosv
DWD setup to VCK + ( + )
tORv
DWDhold to VCK+(+)
20
18jD
t ASY
AI, AO setup to VCK +( + )
10
18/A
tAHV
AI, AO hold to VCK + ( + )
15
18/A
tASV
At, AO setup to VCK( + )
10
18/A
t ARy
AI, AO hold to VCK( + )
15
18/A
toso
DWD setup to VCK( + )
tOHD
DWD hold to VCK( + )
20
19/DIAG-B
tc.v
CLR release to VCK + ( +)
25
16/A
tc.v
CLR release to VCK( + )
25
16/A
tCRH
CLR release to ERD-( + )
25
16jA
taw
CLR pulse width high level
20
16jA
tun
ERD- pulSe width high (Mode C)l
.45
17jA,B,C
tJlPL
ERD- pulse width low
20
17/A,B,C
tVPH
VCK + pulse width high
12
17/A,B,C
17/D
tvn
VCK + pulse width low
Requirements(ns)
Min.
Max.
1
5.0
Figule/Mede
18/D
5.0
19/DIAG-B
17/A,B,C
8.0
17/D
tvuo
VCK pulse width high in diagnostic mode 18
19/DIAG-A
tVLD
VCK pulse width low in diagnostic mode 18
19/DIAd-A '.
tDWH
DWC pulse width high
20
17/0
t DPL
DWC pulse width low
20
17/0
ton
DWCperiod
75
17/D .
tYPe
VCK + /VCK-period
25
17/A,B,C,D
17/D
two
VCK period in diagnostic mode
40
19/DIAG-A
1:cnP
cut tODRC(-) propagation delay:
CL =15 pF
CL =70 pF
tcpo
5-40
CLR to DRDH propagation delay:
CL =15pF
CL =70pF
16jA
5.0
32
16/A
5.0
Confidential and Proprietary
33
Requirements(ris)
Min.
Max.
CLR to EWD + (-) propagation delay:
Cx.=15 pF
Cx.-70pF
16/A
5.0
30
CLR to DN-( +) propagation delay:
CL =15 pF
CL =70pF
,16/A
5.0
3D
CLR to UP-( +) propagation delay
16/A
CL =15 pF
CL =70pF.
ERD-( + ) to'UP-{-) propagation delay:
17/A,B,C
CL =15pF
CL =70pF
DWCH to -UP-H propagation delay:
CL =15 pF
CL =70pF
5.0
i17/A,B,C
VCK + (+ ) to DN-H proagation delay:
CL =15 pF
CL =70pF
17/D
5.0
VCK + (+ ) to - TRUNC UP-( + )
I
i17/B
propagation delay:
CL =15pF
CL =70pF
VCK + (+ ) to TRUNC DN-( +)
propagation delay:
CL =15 pF .
CL =70 pF
VCK + (+ ) to DRC( + ) propagatio:Q.delay:
CL =15pF
Cx.=70pF
16/C
9.0
30
VCK + (-) to DRC(-) propagation delay:
CL =15 pF
Cx.=70 pF
VCK + (-) to DRD( + ) propagation delay:
CL =15pF
CL =70 pF
16/C
5.0
16/C
fo'
VCK + (-) to DRDH propagation delay:
CL =15pF
CL =70pF
tEDU
16/C
5.0
VCK + ( +) to EWD + ( +) propagation
dday
5.0
32
25
16/D
5-41
~~M!iJIIII!!"":lI!I
1lA!.~
___
' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_
..
_
Symbbl
tEDD
t vCIt
tvCP
titm4
Requirements(nsl .
Min.
Max:.
Descriptioil·
VCK+( +) to EWD+(-) propagation
delay
5.0
VCK( + ) to DRC( + ) propagation delay
in diagnostic mode:
CL =15 pF
C L =70pF
25
F1gure/MOde
16/D
19/DIAG-A
5.0
35
VCK(-) to DRC(-) propagation delay
19/DIAG-A
in diagnostic mode:
CI-=15pF
C L =70pF
tWit
tVDF
tWN
VCK{-) to DRD( + ) propagation delay
in diagnostic mode:
C L =15pF
C L =70pF
VCK{-) to DN-H propagation delay
. in diagnostic mode:
CL =15pF
C L =70pF
5.0
30
19/DIAG-A
5.0
-
33
19/DIAG-A
5.0
33
VCK( +) to DN-H propagation delay
19/DIAG-A.
in diagnostic mode:
C L =15pF
CL =70pF
tvru
5.0
30
. VCK( +) to TRUNC UP-( +) propagation
delay:
5.0
C L =15pF
C L =70 pF
17/B
40
VCK( +) to TRUNC DN-( + ) propagation
delay:
5.0
C L =15pF
CL =70pF
40
tVI'L
UP- pulse width low
5.0
25
17/D
tONL
DN- pulse width low
5.0
25
17/A,B,C
tom-tuPL
UP- pulse to DN- pulse skew
-2.5
VCK + H to DRC(-) to VCK + (+ )
to DRC( + } skew:
CL =15pF
C L =70pF
-5.0
-5.0
tvro
tOCU-tOCD
5-42
ConflderltW and Proprietary
17/B
2.5
12
10
Symbol
Rt\quirements(ns)'
~.
Min.
VCK + H to riRC{-) to VCK + (-)
to DRri(+ ) skew:
CL ==15 pF
CL =70pF
VCK+(+) toDRC(-) to VCK+H
to DRD(-) skew:
CL = 15 pF
CL =70pF
VCK+ ( +) toE\v'D+ ( +) to VcK':"
(+ )
-5;6
-5.0
12
12
-5.0
-5.0
12
12
1.0
-1.0
18/A;B,C,D
VCK + ( + ) to EWC(...) 'propagation delay:
5.0
CL =15 pF
CL ==70 pF
27
VCK + (+) to EWC( +) propagation delay:
CL =15 pF
18/A,B.C,D
5.0
25
Ct "",70pF
C:LR to EWC( + ) propagation delay:
tau
19/A,B,C,D
CL =15.PF
5.0
CL =70pF
" .
r~
-
";, 26,
Optimum ERD +IEm- pulse widtb is tvcp+3,5ns.with.no~~Vtc;X]l!~;'tA'
UP +, UP-, DN + , DN- must drive matched loads of 15 pF to 1tl:pF:
) EWD+ and EWD- mustdrivematchedloads of15pFto70pF: .
1
2
VCK+
ERD-
U
U
upON-
Figure 15 • DC024 Read Data Capture Window Signal Timing
Coniiclentialancl Proprietary
IiI!D_.....
I!I?i!_....._..........
_""""""llB_ _ _ _ _ _
•...,.
......
_ ....
!§
. *J:;tiQ
. ........
,!t'j!(~
............
JtI;.-""
__
~
~-.----~..,,-.------~--
5-43
-
·00024
::~
___I-_tDCY_·······_J-+--!t:
MOOEC
MOOED
tepw
CLR
DRC
teEr
EWD+
teoN
DNtcup
Up-
000
tcpo
tCRV
VCK+OR VCK
teAH
ERD--
MODEA
Figure 16· DC024 Signal Timing A
5·44
Confidential and·Proprietary
VCK+
ERDUP-
-'""!---Ittv~-r-tVPH1
~r==~IVCP-----tot1r-,"----'L
l~'I-=,tEUP=''~II=t~EfH~~~9,---_
-,
I
!'=--tePl--J 1...._ _
__________________________
+;--J_
~_;~t~v~-------------------
ON-
L-.J
-l
I-tONL
MOO!:SA. !;I,C
MOOED
VCK+OR VCK
uP-
----_....
ON-
EWC
ORC
-------'
MODES
Figure 17· DC024 Signal Timing B
Confidential ancfl?lnprietMy
VCK+ OR VCK .....""'-"-1---'
ORC
.·~"''';;''''_ _ _ _;''';-'';;''''''';';';;';-II
x:
_ _ _ _ _ _ _ _ .l+-tosv±tOHV::!l •. _ _ - - - - - - - - - - - OWD
VAUO DATA
:A. . ___
-...:;o;._ _ _ _ _ _,..;:...---,_ _
MOOED
VCK+
----'
--I
EWC _ _ _-..J
MODES A, S, C, 0
VCK+OR VCK
EWC
ORC
--,rr:~~~~=~--J
tASV
A 1. AO __" ......._ _
V_AL.;.;.ID....;.ST
__A..;.T;..;;E___---l
MODES A, S, C, 0
Figure 18 • DC024 Signal Timing C
5-46
Conndential and PrOprietary
j-t-tecu
I
VCK
ORC
----'
OOD ______________~~.
00-
MOOE:OIAGNOSTIC
ClR
I
-I
\-tceu
~OOES
.4. B. C, D
MOOE:DIAGNOSTIC
~,
"
_.
,-
,'-
!'
Figure 19· DC024 Signal Timing D
CohfidentiaI and PrOtm~
-
-2.0 V
son
FROM
c>--~--..I..-~ TEST
OUTPUT
POINT
lOAD A: ECl CIRCUIT
TEST Vee TTL
POINT
DIODES
IN916
OR
IN3064
LOAD B: TTL CIRCUIT
Figure 20 • DC024 Output Load Circuit
5-48
Confidential and Prqprietary
• Implements error correction code (ECC)
• Accepts up to 10,060 bits of data in a lO-bit parallel form
• Corrects any number of errors contained in up to
any eight of the IO·bit symbols in the data field ,
• Generates 170-bits of Eee information ~rn
parallel fOf~"
0'
"'!,:' ,,' ,
! ;-,
u
'0',
• Compares 170-bits of calculated Eee wi'tbJ,70-bits of ~E<;:C
• Description
The DC309 Reed Solomon generator .is'&n~ui a 2S¥l'iil'tiual-in1ine package (DIP) and is a
dynamic NMOS LSI chip that implente'tlts:a Reed So1dnrott'~r correction code (EeC). The
DC309 accepts up to 10060 bits of of ESCin!t5rmation in.1Q::ht!paral1el form. It contains the logic
to compare 17o·bits of calculated EeC~tion with l1Q·bjfs j;)head Eee information. This is
performed by generating in lO-bit ~i4!tm the excl~Vt-
----1--1
INE _ - - . -_ _- '
Fa.
--+--+---1
-
~
CLK
CLOCK
OSH£RATOR
PHASE 1
}
TO All
REGISTERS
~ ~~
Figure 1 • DC309 Block Diagram
Confidential and Proprietary
5-49
"",,"
"
,
.~au4,~~~,
This section provides a brief description of the input and output signals and power and ground
connections of the DC309 28-pin DIP. The pin assignments are identified in Figure 2,and,
summarized in Table 1.
'
vee
004
"
002
012
016
006
010
000
008
INE
018
fBE
eLK
001
Voo
011
003
013
019
D09
'007
a::R
017
005
015
Vss
TOP VIEW
Figure 2 .. DC)09 Pin Assignments
5-50
Confidential and Proprietary
-
Table .10 DC)09 Pin and Signal Summary
T_.... JOu
" ....t:.....:..:
• "__ fD ...:........
~~....'f . tput ~14~'1"'·un..- .
10,7,13,
:rjj<:9:(»
Data in: < 9~0 > - Dattl input lines that receive the
data mpudn 10,bit par.allelform.
input
4;15,2,18
26,20,25'· .
11,6;12, . J)O < 9:ri>~t~ut
5,16,,1,
19;27,21
24
:
··Y>'taout < 9:0~--D~ta.·outP,U~lines'tlutt~s~er
170'bi,'tso£10 ....
... (lUbyl1)ECCfoHowlng
thec!H8iiLt'. . •. . . . . '.. putda~lmd wh~170bits
of lU;bit'p~cl'lIO'bYfj)·reStd~ ' ltre tmnsfetted
forcortehi&ri)"'\ .' '..... • ", '.
'v-"
22
~
J
input
FBE
~
23
enable-'i&Se.rtW Whend.tlt is ~i~ .for
ECt~tion:andiwhem;the.£CCi$.~eived tp
genera~the;out~tte$ld~.· ~. sigp~,is~ated
'WhentheJ~C~Mmp~~
~eEc"O Qllt.
"-'"'jJC/d{t,'_,',,,-, ", ,,' '-,,,,
>",
17
eLK
8
"
•• '
,
.- ."
,'ii~,', ,j
, ,,',
, )'"
.
input
Clear-Asserted fora {ulldock time to initialize the
DC309 before starting any ECC process.
input
Clock~ThetnAin~.~·. ~~n~tha:t controls the
OO~9optimtiok;~ n()rtnal operation, the
iiiput Sigri~'Q" '~~,.s.d the outputs signals are
a~!I~Jeoa'the;:,:~e of dock signal~T~
vaNti0nsambeimplemeAtedProvided the switch,
itl$tifDes~~ spec:i~~are ~d.
3
QQtPllt
Errprout~Asta!liql~Y ~tO~sign~that i,negated
by the dear input for initialization purpos~s ~d
aSSerted wl;tttfth1fresi~ is fout# to ¥~!lzel.'P'
28
input
TheJat~hisenab1¥whenthe ~BE'sigMl :i~.n¢gat¢d
ilndtheiNE S'~is 'a!&erted.
Voltage-Power supply 5 Vdc
9
input
Voltage-Power supply 12 Vdc
14
input
Ground-Ground reference
~F51
'"~
"!!f
~
.. _!t:i!
,~ell!1l!l
"JiIIiJI!''''f!'f:ItI _ _ !WI
~~
_ _ _ _•_ _ _ • _ _ _
~_~,
_____________ _
Functional Operation
. . . . ....
..... , . )
... , .
The DC309 contains 17 ·lO-bit re~ister~tages,analpha generatOr .tIDd feedback logic, an error
detector latch, and a dock generator. Theregistefstages 'and etror detector are deattfd by the dear
signal. A two-phase dock output from the dock generator is distributed toeachof th~ registers.
To generate the ECC, 10 bits of parallel data on lines DI < 9;0 > are entered through the input AND
gates when enabled by the input enable (INE) signal. The parallel data from the input gates is
transferred thJ;ough the feedback gate to the alpha generator wht':n enabled by the feedback enable
(FBE) signal. The alpha generator produces eight lO-bit alpha-terms: 'Each bit of the alpha-t:<;:rlll is
composed of an exdusive-QR gated combination of from three to seven input bits and is OR gllted
with the register~tputs.Theresults are clocked into the next register stage. This proce,ss
continues until all data words are entered. The ECC is then stored at the outputs of the 17 register
stages. The INE and FBE signals to the error detector latch are negated to shift out the 17-word
ECC register data.
To compare the internally generated ECC with an external ECC, the INE signal is asserted and the
FBE signal is. negated. The internally generated ECC is shifted through the register stages and
exclusive-OR gated with the input ECC. The resulting comparison data is transferred on the data
oUt lines DO < 9:0> and to the error detector. The error detector output (ERR) is asserted when
the input ECC does not equal the internally generated ECC.
Table 2 lists the loWt levels required to select the DC309 functions.
Table 2 ·OC309 Logic Function Selection
Interface Signals'"
Function
DI<910>
00<9:0>
FBE
INE
Clear
X
L
X
X
L
H
Calculate ECC
M
X
H
H
H
H
OutputECC
X
M·
L
L
H
H
Output remainder
M
M
L
H
H
M
*H = High logic level,L.,. Low logic level, X =High or low, M = Meaningful data .
• Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC309 are
described in the following paragraphs. The test conditions for the electrical values are as follows
unless specified otherwise. Refer to Digital specification A-PS·2100002-GS for the general
specifications for integrated circuits.
• Operating temperature (TJ: O°C to noe
• Power supply voltage Ned: 5.0 V ± 5 %
• Power supply voltage (VDD): 12.0 V ±5%
5-52
Confidential af}d :Proprietary
Mechanical ~tioQ
. ,.
. . y.
Thephysicalclimemions of the DC3092S-pm DIP are contained in Appendix E.
AbsolUte ~.RatinJJs
'Stresscsgteater thad the absolute maximum ratings may cause permanent· d~ totb1!. dev~e.
Exposure to the absolute maximum ratings fur extended periods
adversely E~"l~K~,"'"~-3V
CLEAR (CLR)
--------'
1
M
'
,~-------- 0'1
I
.)E'bS3:I :;<='
, ...,..",.,.,.,- 3'1
I
INPUT ENABLE (INE)
......_-""'--_..,...,........""" '"
, 'I'
'"---------
OV
I
I
FEEDBACK ENABlE (FBE' _ _
~"-_"-"-"-..J)f~si~j('",:=,.-,.-_____ :
t
I'
DATA IN (DI<9:o» _ _ _ _,.-_ _ _
. '-------::
.
-'>tt~E~fj(
,5-55
""Ii_
,~"',Ilil'l£"',
.............
,,.._ _.......,_
....
U ...
I9 ...
I'M............._ _ _
.. _ _ _ _ _ _ _ _ ,
...
c::
CLOCK (ClK)
INPUT ENABLE
UNE)
v.r----t------.r--------
II
...;.._...;...;..;..."",!S.
PIDO
.;.....;...;..-4•
DATA OUT
(00<9:0"'")
----1.
I
I
!
:
I""....
· - - - - - - tPCLDO
3V
OV
------~.~oot:'"'-_______ :::
CLOCK AND INPUT ENABLE TO DATA OUT
3V
DATA IN (00<9:0»
>K
OV
I
I
I
I·
DATA OUT (01<9:0»
tPDIDQ
~
VOH
VOL
DATA IN TO DATA OUT
Note: Input enable INE is high.
__-;I_______
~=R O U T _ ,
.
tpCLE
~.....-------------VOH
_
•
" " - - - - - - - - - - - - - - - - VOL
CLOCK TO ERROR OUT
Figure 4 • DC309 ac Signal Propagation Delays
Confide:htial and Proprietary
Symbol
Tsble 4 • DC309 ae Signal Toning Parameters
Deiinition*~ts.(tlS)
Min.
tcvc
Max.·
100,000
C~ cycle time
Clock high time
Clock low time
75
Input enable setup time
30
Feedback enable setup time
40
Data input setup time
Clear setup time
45
.. 1
115
Input enable hold time
25
Feedback enable hold
35
nata input hold time
50
Clear hold time
tPCLDO
Clock to output data
propagation clelay
30
Input enab~to oUtput
200
125
data propagation delay
Data input to output
data propagation delay
80
Clock to error
propagation d~y
160
Clear to error
propagation delay
160
*All time measurements .shaIl be made fro~ the. ~.5, y~ ofi~llpp~priate signals. Input rise
and fall times shall be 15 os maximum meaSured at the 10% and 90% levels. Valid output data
prior to low-going transition must remain valid for a minimum of 30 ns after the clock transition.
FROM
OUTPUT
ALL DIODES
IN9l6 OR
IN3064
Figure 5 • DC309 ac Load Circuit
Confidential and Proprietary
· Typical Application
Figure 6 shows a typicIU .appUcation of the DG309. During a media write sequence, data is read
from main memory, an ECC is calculated, and the data and ECC are written into the serial memory.
During the following read-back data sequence, the data and ECG are read from the serial memory,
and an EGC is again calculated from the da.ta read. If the ECC that accompanies the data read is
different from the calculated ECC, an error condition is indicated.
PROCESSOR
OC01S
SERIALIZER/
DESERIALIZER
DC309
SERIAL
MEMORY
MEDIA
ERROR OUT
(ERR)
Figure 6 • DC309 Typical Bec Application Block Diagram
Figure 7 shows the timing sequence for clearing the DC309, for calculating the EGC, and for
transferring the ECC output information during a write operation. Figure 8 shows the timing
sequence for clearing the DC309,for calculating the ECC, and for transferring the EGC output
information during a read operation.
5-58
Confidential and Proprietary
01<9:0>
DATA OUT
VAliD . ts>ce-.
~~--""------:-V1----:---'
ERROR OUT
VALID
!mRl
Figure 7· DC309 Typical Read Operation Signal Timing
Confidential and Pnlprietaty
-
DC)(l9
elK
DATA IN
VALID
INE
FBE
DATA OUT
VALID
----~-----_t'.J_---.....:...-l.......
00 <:9:0>
tPCLOO--l
Figure 8· Typical Write Operation Signal Timing
During a media write sequence, 16 bits of parallel data read from main memory are transferred to
the serializer. The data from memory can be transferred in blocks consisting of up to 10,060-bits.
The serializer converts the parallel data to serial data and transfers it to the serial memory. The
parallel data is also converted into lO-bit parallel symbol form and transferred to the DC309. The
DC309 generates an ECC from the data received and transfers the ECC to the serializer where it is
transferred to the media.
During a read-back operation following the write operation, the serial data and ECC from the
media are read and transferred to the deserializer. The data read is changed into a 10-bit parallel
symbol form and transferred with the ECC to the DC309. After all the data is read, if the data is the
same as previously written, the 170 bits of ECC will be the same. The DC309 generates the
exclusive-OR function of the 170 bits of read-back ECC and the 170 bits of recently calculated ECC
and the results (residue) are transferred to the main memory.
The DC309 checks the 170 bits of residue 10 bits at a time for all zero content. If the residue is all
zeros, the read-back ECC is equal to the calculated ECC and no data errors are indicated. If the
residue is not all zeros, the read-back ECC was not equal to the calculated ECC and the 170-bits of
nonzero residue allow external mathematical calculations to correct any errors contained in any 8 of
the lO-bit data symbols. A resulting error indication is transferred to main memory where it can be
used to correct certain types of errors if required.
:,..60
Confidential and Proprietary
• Section 6-Gene:ral Purpose. Devices
The general purpose devices facilitate the development of pux:essor interfaces for the control and
transfer of information from processors to memory and other devices.
DC022 16- Wbnl by 4-Bit Register File-The DC022 is a 28-pin DIP device that provides two
independent read/write ports to allow simultaneous asynchronous access to a register file from
either port.
DC102 Eight Channel Equals Checker-The DC 102 is a 20-pin DIP that provides eight dual-input
channels used to compare data in pairs for equality.
DC301 Dual Baud Rate Generator- TheOC301 is an I8-pin DIP that provides prognun selectable
baud rates ('0 to 38,400) and separate transmit and receive frequency outputs to control the
transfer of serial-line information.
Confidential and Proprietary
• lWoindependentre·adfwrite ports
• 10k series, ECL compatible input/output port capable' of dri~ins
Ijq.~~s
• Tn input/output port capable of sinking 20 rnA in a low state
• ECL and TTL address decoder and bidirectional data buffer
• DesctiptioD .
The DC022 register file, contained in a 28-pin dual.in1inepackage (DIP), provides storage for up to
16 4-bit words and two independent read/write ports that allow simultaneoUs asynchronous access
to the register file information from either port. Figure 1 is a simplified block diagram of the
DC022.
Figure 1 • DC022 Simplified Block Diagram
Confidential andProprietaty
_ ..........._T__•_ _ _
____
~
6-1
~_._._~
_____._. __
,':--';,"
,
,
"',,
,
,,'.
.
,/'/
'~eldata ill~j\lIf~dtollnd from the f1let~\lShf6ur~s6fbidirectid~at,dlltalines, ones~t
for each port. Each port receives address inputs and read and Write enable lines. One port has ECL
10k series macrocell arrays (MCA) compatible inputs and data outputs capable of driving}5 J.LA
loads. The remaining port has TTL compatible inputs and outputs and is capable of sinking 20
milliamperes in the low state. A location in the file can be written from either port by specifying the
address on the address inputs, negating the read enable input, transferring the data to the inputl
output lines, and asserting the write enable input. A lo<;:atiori from the file is ~ad from either port
by specifying the address at the address inputs and by asserting the read enable input while the
write enable input is negated .
• Pin and Signal Description
This section provides a brief description of the'input and output signals and power and ground
connections of the DC022 28-pin DIP. The pin assignments are identified in Figure 2 and,
summarized in Thble 1.
.
D2-T
GND
D3-T
Dl·T
DO-T
RDEN-T
A2-T
WREN"Tc
A3-T
Vee
GNO
A3.£
VEE
A2~E
WREN-E
Al,E .
AO-E
VEe
DO-E
GNO
GNO
D3-E
D1-E
GND
D¥-E
Figure 2 • DC022 Pin Assignments
6-2
Confidential and Proprietary
lAble 1 • DC022 P'm and Signal Summary
Pin
22-19
EeL addres~ 'bits <3:0> .,.,.,Biu·} ~Oofihe EeL
A.<3:0>:-E inputs'
pprt~dre/ls.
Eet ~fit~etiab~~WbenllSsert&l;'
.~tn the ECL
daUitiheS' <~!Q;~:' '~i1!eh;< ,'. ,~~th file
'l€id" thliEttaddtltSi~·BitS<3!'O>.
9
tIle
·Jlfe~$·tH~~ttptesent.
.'_ ".,~,
1" ,,'
.; ,,',-,_ ,',", ,;;.' ':" ',",_.,~ .,/,,'1
."
£CL:tead,;.enable~'Cd~ts . o£ ;th~,~s~r file
" lbcatiort.:spdiedi·by,~La~~,<3:0>. is
tran&ferred,to'the:ECJ;;;Q.at.lfueS . ,<3,Q.> •
13-18
ti <:3 :0> ~E inl>~ts9outl>ut~,2 .EC:L.a~t~~s; ~jW,'3> Bid1i'ectif)nalIip~$~ugh
01>£ t~!Cr:: pi;l,naa~Wi~ the'~tt;~~fdUb\vetdriv'ets
enabled by fm'f!~:.'f!~~n~L"'·P
,
t~~d~~,b~t,~~;q~;'Bit,~.~ ~O~£t~rI'L
6-3
port ad is written to thereg~ter fIle IOcR:
tion specified by the Tn address bits < 3:0>. When
negated, the location retains the data p~m.
25
·:r'lfL. ~!~ble!"":'"~.'~QnteQ;fS.:of :thej~ter.. file
RDEN-T
locationspeci:fIm~;j~'I1'~!~s
lines.<3;O> is
transferr¢t:hotf!ft.datl'lines !tM>'!.lIhtbe ~.
state drivers.
2,1,
27,26
D<3:0>-T
23
inputs3/outputs·
input"·7
TILdataline.s<3:0>,~Bic,l1~j~I~}j;~O
6ftheTILdata pprt'With t~.~~tt ~\1ersenabied by
RDEN,T signal.
. . . . " .. '
Voltage":""PO:wersupplyvoltage ioTTI:.fuput and.
out-
put buffers.
8,11
input"·,
7,14,28 GND
input'·7
Voltal!e-Pow~ slJP~fvol~e tdlhe~ t~t:clt. EeL":
output bu.££ers:atJ.dassociated iwnerb1inbgic:~
.
lECtlevels
2Eminerfollower drivers
'TIL levels
41bree-state
'Pins 7, 12, 14,17, and 28 connect to network ground KiND).
6Pins 8.and 11 connect to VilE' Piri23 connects toVcc.
..
'The power and ground pins must be connected externally to the specified ~and gt'OUl'ldplane.
Confidential and Proprietary
_a_..._.___. ________
w_
••
!~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
6-3
...
• Operation
The DC022 consists of an ECL and. n'L ad4re~s decoder, anEGL"nd TTL bidirec~ional data
buffer, and a 16 word by 4-bit array latch. The ttL bidirectional 'buffa:t~sfers data between the.
three-state data bus and the array latch. When the read enable RDEN"T signal is asserted, the data
from the array latch is transferred to the three-state TTL data lines D < 3:0> -T. When the read
enable signal is negated, the three-state output buffers are in a high impedance state. The ECL
bidirectional datli;buffer tra~fers data between the 25 ~ emitter OR gate type data bus and the
array latch. Whenthe read enable RDEN-E line is asserted, data from the array latch is transferred
to the ECL datl!.lines D < 3:0 > ~E. Whe~ the~ad enable signal is negated, the ECL data lines are a
high-impedance state. The TTL address decoder decodes the four TTL address bits A < 3:0 > -T to
select one of the 16 4-bit words in the address latch for a read or write transaction. The 16 words are
accessed through the 16 TTL address decoder and 16ECL address decoder select lines. The TTL or
ECL input data from the bidirectional data buffer is written into the location selected by the TTL or
ECL.addressbits when tbewriteenable (WREN·T or WREN·E) lines are asserted. Data is read
from the array lat~ and transferred to the TTL.or EeL bidirectional data buffer by selecting the
pioper word through the appropriate TTL or EeL ad<:iress bits. The dual select lines, data paths,
and read/write controls allow simultaneous and independent operation of the TTL and EeL ports
for any rombination of read/write transactions. Simultaneous write operations from the two ports
to the same word location, however, will result in undefined logic states for the addressed word.
Simultaneous read and write operations to the same. location will cause the data read to Pe the same
as the data written.
.
. Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC022 are'
described in the following paragraphs. The test conditions for the electrical values are as follows
unless specified otherwise. Refer to Digital specification A-PS·2100002-GS for the general
specifications for integrated circuits.
• Supply voltage (Vcd: 5.0V ±5%
• Relative humidity: 0 to .95% (noncondensing)
Mechanical G~nfiguration
The physical dimensions of the DCO.22 i8-pin DIP are contained in Appendix E.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely. affect the
reliability of the device.
• Positive supply voltage (Vcd: -0.3 V to 7.0 V
• Negative supply voltage (VEE): -8.0 V to 0.3 V
• ECL input voltage (Via): 0.3 V to VEE·
• TTL input voltage (V••):-0.5 V to 7.0 V
• Relative humidity: 10% to 95% (noncondensing)
6-4
Confidential andPropri~tary
• Supply voltage (Vcd: 4.75 V to5.25 v (V!E): -5.46 V to -4.94 V
• Supply current (lcd: 425 mA(maximum)
• Linear air flow 500 feet/minute (minimum)
de Electrical Charaeteristics
The dc electrical parameters of the DC022 for the operating'voltage and temperature ranges
specified are listed in Thble 2. Re£er to Figures 3 and 4 for the ~t cil'Cui~configurations referenced
in the Table 2. Table 3 lists the conditions that apply to theti~t. ciniUits.
neon•• E1edriCal·~
Symbol Test
Conditions
~~~
Units
F~
VIH
V
3/A
Table 2·
Parameter
l .,
High-level
input voltage
Low-level
input voltage
VIL
D<3:0>-T
A<3:0>-T
WREN-T
RDEN-T
D<3:0>-E
A<3:0>-E
WREN-E
RDEN-E
ooe
25°C
]joe
D<3:0>-T
A<3:0>-T
WREN·T
RDEN-T
D<3:0>-E
A<3:0>-E
WREN-E
RDEN-E
oce
25°e
75°e
2.0
.5.25
3IB
-1.14' . -0.74
-1.105 -0.71
-1.405 -0.62
V
V
V
-O.P
V
0.$
3/A
3IB
3/A
-2.5
-2.5
-2.5
Confidential and. Proprietary
-1049
-1.475
-1.45
V
V
V
6-5
-
PBr.meter
High-level
!)c022
Symbol Test
1m
input current
Conditions1"
D<3:0>-T
VIa=2.7V
A<3:0>-T
WREN-T
VIo=2.7V
RDEN-T
Vlu=2.7V
D<3:0>-E
Requttements .
Max.
tJnits
F~··
3/C
Min.
0
·100
~
0
20
~
0
50
~
0
300
.~
3/D
0
200
~
3/D
D<3:0>~T
-500
-400
0
0
~
~
3/C
A<3:0:>.T
RDEN-T
-200
0
V.." =0.5 V
D<3:0>-E
Via =-2.0
ItA
-800
20
ItA
A<3:0>-E
0
20
~
-1.2
0
V~=VIHmax
A<3:0>-E
WREN-E
RDEN-E
V..,,=V1Hmax
Low-level
input current
IlL
WREN-T
V..,,==O.5 V
3/D
WREN-E
RDEN-T
V.." =-2.0 V
Input clamp
voltage
VIC
D<3:0>-T
A<3:0>-T
V
3{E
3/C
WREN.T
RDEN-T
Im=-18 mN
Input current
at maximum
input voltage
lIM
D<3:0>-T
VIa=7.0V
A<3:0>-T
0
300
ItA
0
100
~
WREN-T
RDEN-T
Via"" 7.0 V
6-6
Confidential and Proprietary
DC(JZZ
Parameter
High-level
Symbol Test
VOl!
outP\1t
voltage
Min.
D<3:0>-T
L..=-2,6mA
2.4
25°C
75°C
VOl.
output voltage
Low-level
loL
output current
FfgUl'e/Test:
V
3/B
3jA
D<3:0>-T
L=-20.0mA
D<3:0>-E
-1.0
-0.84
.,.Q.96
-0.81
V
V
-0.9
-0.72
V
0
0.5
V
l/B
-800
.20' ..
~
3jA
rnA
4/F
45 ..
rnA
4/G
0
rnA
4/G
V... =~2.{)V
-40
Short circuit
output current
los
Positive power
supply: current
Icc
0
Negative power
supply: current
lEE
-400
I
Units
D<3:0>-E
L=40mA
L=50mA
ope
Low-level
Requirements
Max.
Conditionsl.'
D<3:0>T4
... 100
All inputs .IDustbe at the voltage ltW'els ~pecjf~ed ¥1 achiey~ the;desired logicstate.Open inputs will
result in undefined logic states being propagated through the device. All voltages are specified
with respect to network ground.
20 n a transient basis, Va (min.) for TTL inputs is considered to have a value equal to the input
clamp voltage (VIC) as measured for the device under test. The device must meet functional
requirements when any combination of inputs is subjected to a VIC transient of up to 100
nanoseconds.
'The duration of the specified input current CL.,) on a TTL input for the input clamp voltage (VIC)
test must not exceed 1.0 milliseconds.
4All TTL outputs must meet all dc and ac characteristics after the application of ground for 1.0
seconds. Only one output may be shorted to ground at a time.
IThe definitions of input and output voltage and current parameters apply to both TTL and EeL
inputs and outputs unless stated otherwise.
Confidential and }l1'QPrietary
6-7
-
DC022
Table) • Dc022 de Test Circuit Conditions
Ftgure/Test Condition
3/A,3/B
Each input is tested separately. The test requirement must be met with other inputs at
any voltage within the range specified and for any voltage within the range specified
for Va or V IH • Pins D<3:0>-E are terminated to -2.0 V through a 250 resistor 'for
input test.
3/C
Each input is tested separately. To test D < 3:0> -T, RDEN-T must be driven by a highlevel voltage and the input currents specified must be met over the range of VIH
specified £o~ RDEN·T.
3/D
Each input is tested separately. To test D<3:0>-E, RDEN-E must be driven by a
high-level voltage and the input currents specified must be met over the range of Vrn
specified for RDEN-E.
3/E
Each inputis tested separately. To test D < 3:0 > -T, RDEN- T must be driven by a highlevel voltage and the input currents specified must be met over the range of VIH
specified for RDEN-T.
'
4/F
Each inpht is tested separately. To test D < 3:0 > -T, RDEN· T must be driven by a lowlevel voltage. The short circuit currents (los) specified must be met over the range of
Vm specified for RDEN-T.
4/G
6-8
Each input is tested separately.
1. The power supply currents may not exceed the limits specified for any combination
of input logic levels.
2. The total power dissipatiorl will increase when the outputs are connected to loads.
Confidential and Proprietary
Vee
Vee
VEE
VEE
oo-E
VIH. Vll
AO-T
Al-T
A2-T
A3-T
AOo£
Al-E
A2-E
A3-E
VIH,VIL
VIH. VII.
ADEN-T
V ... -
WREN-E
VIl-
Ri5EN-E
VOH VOL
OO-T
AO-E
AH!
AO-T
AH
A2-T
A3-T
A3-E
}v.v.
~,
VIHDC022
RDEN"E
VIH- WREN-E
V.. -
ffiiii:'f
DC022
GNO
GND
=
CIRCUITS
-=
CIRCUIT A
Vee
VEE
I
Ill.IoH. hM
Ol-T
PloT
A2O£
~
VIH-
00-1'
Ol-E
02-E
03-E
} VOH, VOl, lot.
I
OO-T
01-T
02-T
03-T
OS"£:
AO-T
Al-T
A2-T
A3-T
AO·E
Al-E
A2-E
A3·E
000£
010£
020£
III..~
~
I7imN-T
RJ5m'f
DC022
OC022
RDEN'E
GND
ONO
~
-=
CIRCUIT C
CIRCUIT 0
Figure 3 • DC022 Test Circuits
Confidential and Proprietary
6-9
DC022
VeE
Vc£
!
I
OO-T
OO-T
01-T
02-T
D3-T
VIC
11M
Dl-T
D2-T
03-T
AO-T
Al-T
A2-T
A3-T
WREN-T
RDEN-T
GNO
1
CIRCUIT F
CIRCUIT E
I~ICC
REFER TO
TABLE 3
NOTE 1 FOR
TEST CURCUIT
GINPUTS
1
DC022
OC022
GND
Vee
los
VEE
. 1+1EE
AO-T
Al-T
A2-T
A3-T
OO-T
01-T
02-T
03-T
AO-E
Al-E
A2-E
A3-E
DO-E
Dl-E
02-E
03-E
OPEN
WREN-T
ImE'N-f
WREN-E
AOEN-E
DC022
GND
1-
CIRCUIT G
Figure 4 • DC022 Test Circuits
ac Electrical Characteristics
Table 4 lists ac timing parameters for the input and outputs signals shown in Figures 5 through 9.
The symbols referenced in the figures and tables are defined in Table 5. The TTL and EeL output
load circuits used to measure the ac signal parameters are shown in Figure 10. Refer to Appendix D
for the input and output voltage waveform parameters used for measuring the signal propagation
delays.
6-10
Confidential and Proprietary
DC022
Table 4 • DC022 ac Parameter Defmitions
Symbol
Address access time-The time between the specified references on the address input
and data output voltage waveforms with the output changing (rom one defined level
(high or low) to the other defined level. (Read enable is asserted and write enable is
negated.)
Data access time-The time betwe~the specified referepces on. the. data input
voltage waveforms of one port aDd the data output Voltage waveforms of the other port
with the output changing from~me.de£ined level (high or low) to .the other defined
array lat~ (Write enable is
level. The first mentioned port is set up towrite
asserted and read enable is negated.) The second pOrt is set up to x,eadth,e array latch
(read'enable is asserted and write enaBle is negated), and both ports are set up to access
the same location in the arraylatch.
..
"
tHe
Write access time-The tim~between the specified reference poults on the write
enable input voltage waveform'tif one port and thedataou~put voltage waveforms of
the other port with the output changing from one def~ned level :(highorlow) to the
other defined level. The first mentioned port is. setup· to write tbe array latch. (read
enable is negated and write enable ism the process of being asSerted) . The second port
is set up to read the array latch (read eoobleis asserted aDd. write enable is negated), and
both ports are set up to access tht;:! sam~ location in the array latch,
Output enable time-The propagation delay tiniebetween the.~i£ied reference
points on tberead enable input and the data output voltage ~veforrris With the output
changing from the high-impedance (off) stateto either of the defined active levels
(high or low). For the three-state TTL outputs, both the high aDd. Iowlevelsare active.
.
For the openc.emitter ECL outputs, only the high level is active.
Output disable time-The propagation delay timebet:\Veen the specified reference
points on the read enable input arid the data output voltage waveforms with theo1.ltput
changing from either of the activetevds(high or low) to the high-impedance (off)
state. For the three-state TTL outputs, both the high and low levels are active. For the
open-emitter ECL outputs, only the high level is active.
Address setup time-The time interval between the specified reference points on tbe
address input and write enable input waveforms that defines the earliest point in time
that the address inputs must assume stable logic states with respect to the write enable
input pulse. The logic levels at tbe address inputs must remain stable between the
points in time defined by the address setup and hold times to ensure proper transfer of
logic levels at the data inputs into the array location specified by the address without
affecting any otber location in the array.
Address hold time-The time interval between the specified reference points on the
write enable input and address input waveforms that defines the latest point in time
that the address inputs must maintain stable logic states with respect to the write
enable input pulse. The logic levels at the address inputs must remain stable between
the points in time defined by the address setup and hold times to ensure proper
transfer of logic levels at the data inputs into the array location specified by the address
without affecting any other location in the array.
Confidential and Proprietary
6-11
_
OC022
Symbol
Name/Definition'"
t ns
Data setup time-The time interval between the specified reference points on the data
input and write enabJe input waveforms that defines the earliest point in time that the
data inputs must assume stable logic states with respect to the write enable input pulse.
The logic levels at the data inputs must remain stable between the points in time
defined by the data setup and hold times to ensure proper transfer of logic levels at the
data inputs into the array location specified by the address.
tDH
twp
til
Data hold time-The time interval between the specified reference points on the write
enable input and data input waveforms that defines the latest point in time that the
data inputs must maintain stable logic states with respect to the write enable input
pulse. The logic levels at the data inputs must remain stable between the points in time
defined by the data setup and hold times to ensure proper transfer of logic levels at the
data inputs into the array location specified by the address.
Write pulse width-The time interval between the specified reference points on the
leading and trailing edges of the waveform that must be applied to the write enable
input to ensure proper transfer of logic levels at the data inputs into the array location
specified by the address.
Rise-time-The time between a specified low-level voltage and a specified high-level
is changing from the low level to the high level.
vol~e on a waveform that
tF
c.
R.
Fall-time-The time between a specified high-level voltage and a specified low-level
voltage on a waveform that is changing from the high level to the low level.
Input capacitance-The capacitance measured at the specified pins with power
applied to the device.
Real input impedance-The real portion of the input impedance measured at the
specified pins with power applied to the device.
*The definition of the input and output voltage and current parameters and the timing parameters
apply to the TTL and EeL ports unless stated otherwise.
6-12
Confidential and Proprietary
....
DC022
Table 5 • DC022 ac EIed:rieal Characteristics
Symbol
Delinition
Load (c..)
tM
Address access time!
A<3:0>-T input to
D<3:0>-Toutput
Address access time:
A<3:0>-E inputto
D < 3:0 > -E output
tDII
Data access time1
D<3:0>-Einput
D<3:0>-T output
Data access time4
D<3:0>-T input
D<3:0>-E output
tWII
Write access time1
WREN·E input
D<3:0>-T output
Requirements (os)
Min.
Max.
Figure/Level
15pF
50pF
150pF
2.0
2.0
2.0
30
30
40
5/TTL
30pF
90pF
2.0
2.0
30
30
5fECL
15pF
50pF
150pF
6.0
6.0
6.0
30
30
33
6/TTL
.30 pF
90pF
6.0
6.0
30
30
6/ECL
15 pF
50pF
150pF
6.0
6.0
6.0
32
32
36
7/TTL
30pF
90pF
6.0
6.0
32
32
7/ECL
15 pF
50pF
150pF
3.5pF
30pF
90pF
5.0
5.0
5.0
5.0
5.0
5.0
22
22
28
22
23
25
15pF
50pF
150pF
3.5 pF
30pF
90pF
3.0
3.0
3.0
2.0
20
20
40
Write access time'
WREN·! input
D<3:0>-E output
tol!
Output enable time
RDEN· Tinput
D < 3:0>·T output
RDEN·E ioput
D<3:0>-Eoutput
Output disable time
RDEN-T input
D<3:0>-Toutput
RDEN·E input
D-E output
t llS
Address setup time7
A-T input'
A<3:0>-E input'
8/TTL
8/ECL
8/TTL
8/ECL
18
20
5.0
8.0
Confidential and Pniprietary
9/TTL
9/ECL
6-13
DC022
Symbol
De£'mition
Load (4.)
Requirements (ns)
Min.
Address hold time'
A < 3:0 > -T inputS
A<3:0>-E input~
8.0
9.0
9/TTL
9/ECL
Data setup time'
D<3:0>-Tinput8
D<3:0>-E input 9
11.0
3.0
9/TTL
9/ECL
Data hold time?
D < 3:0> -T inputB
D<3:0>-E input 9
12.0
18.0
19.0
9/TTL
9/ECL
Write pulse width1
WREN-T inputS
WREN-E input'
18.0
15.0
9/TTL
9/ECL
Rise time'O
D<3:0>-Toutput
D<3:0>-E output
Fall time"
D<3:0>-Toutput
D<3:0>-T output
e",
15pF
50pF
3.0
3.5pF
90pF
1.0
15pF
50pF
3.5 pF
90pF
1.0
8.0
5.0
8.0
0.5
Input capacitance
D<3:0>-T= 10 pF (max)12
A < 3:0> -T = 10 pF (max)
WREN·T "",lOpF
RDEN- T = 10 pF (max)
D < 3:0 > -E = 10 pF (max)"
A<3:0>-E=8 pF
WREN-E=8pF
RDEN-E=8pF
R;.
6-14
Fagure/Level
Max.
Real inputimpedance'4
D<3:0>-T=OO
A<3:0>-T=OO
WREN-T-OO
RDEN-T-OO
D<3:0>-E=OO
A<3:0>-E=OO
WREN-E=OO
RDEN-E=on
Confidential and Proprietary
4.0
IWREN-T and WREN-E= Vm, RDEN-T - VIL , A<3:0>-E are stable.
2WREN_T and WREN-E =Vm, RDEN-E =VIL. A< 3:0 > -T are stable.
JWREN-T and RDEN-E=Vm, RDEN-T ahd WREN-E=VIL' A<3:0>·T and A<3:0>-E are
stable with the same address.
·WREN-T and RDEN-E=V1L , RDEN-T and WREN.E- Vm , A<3:0>-E and A<3:0>-T are
stable with the same address.
'WREN-Tand RDEN·E- Vm, RDEN·T - VIL' D<3:0>-E are stable, A<3:0>-TandA<3:0>E are stable with the same address.
'WREN-E and RDEN·T=Vm, RDEN-E=VIL' D<3:0>-T are stable and A<3:0>-T and
A<3:0>-E are stable with the same address."
7S etup times, hold times, and input pulse widths are specified as minimum values and represent the
requirements imposed by the device cll1the input signal timing r;}ationshlps.
8RDEN-T= VIII'
'RDEN·E = Vm'
I°For D < 3:0>-T, the rise time is measured from 0.8 to 2.0 volts. For D< 3:0>-E, the rise time is
measured from -1.5 to -1.1 volts.
uFor D<3:0>-T, the fall time is measured from 2.0 to 0.8 volts. For D3:0-E, the fall time is
measured from -1.1 t'o -15volts.
12Capacitance is measured at the D < 3 :0> -T pins with· the three-state buffers disabled. The
requirement specified muSt.be mefforahVlHapplied to the RDEN·T input that meets the
requirements of Thble 2 .
"Capacitance is measured at the D < 0:3 > -E pillS with the emitter follower outputs in the off
state. The requirement specified roust be met for any Vm applied to the RDEN-E input that meets
the requirements of Table 2.
.'
. .
14This parameter specifies the real portion of the input impedance to be positive for all frequencies
that will ensure that the device will not cause oscillations in a system environment.
Confidential and Proprietary
6-15
...
0<:022
x:
------""'\
A<3:0> - T
, . - - - - - , . - VII<
1.5 V
~_---:-.J ~-tA.A-=1-"'- V,L
E
D<3:0>-T
TTL OUTPUTS
A<3:0> - E
,..------V..
X-,·3V
------' t-tA-A-~----' V,L
E
D<3:0>-E
Eel OUTPUTS
0<3:0> - T. - E
~VVVVVVVV~~MM~----------~----H
____
____________
l
Al\A/\AIV\/\
V ALtO
LK~~~~~--
~
\---tAA-+l
0<3:0> - T, - E
~
VALID
:vyvyvvvyvvvyvvv:::::::::,:::::==========H
L
NONMONOTONIC INPUTS
Figure 5 • De022 Address Access Timing
6·16
Confidential and Proprietary
0<3:0> - E
E ..~E
:~
0<3:0> - T _ _ _ _ _ _ _ _ _ _
TTj...OUTPUTS
---v----------V
IH
0<3:0> - T - A - l . 5 V
~-tDA~--"""'
0<3:0> - E
..- ....
.
E
Vll
eCLOUTP!JTS
0<3:0> - E. - T
0<3:0> - T. - E
~vvvvvvvv~~~~----------------H
IV\AI\IV\A/\
V
AUO
=~"':.lC..:.loI.
.•:.,Jj. .-".~
~ .-". :'-'.:':.loI.. ''''. .:.~~'~
. ,~.~
•. -.:tb~':A~.:..-·~~·:·":l"··~·~·:~~:~~::_V~_A~_L-I~O~_-:-=_:
:
NONMONPTONtc INPUT$
Figure 6· DC022 Data Access Timing
ConfidetrtialandPropHetary
6-17
DC022
----y----------V'H
WREN-E - - , , \ - - 1 . 3 V
~-tWA==J---V'l
0<3:0> - T _ -_ _ _ _ _ _ _ _
E
TTL OUTPUTS
~----------VIH
~.'.5V _ _ _ _ _~__ V'L
_"·T
J
---:.-.------E
tWA---
0<3:0> - E
EClOUTPUTS
WREN-E. - THIGH
XXX
LOW
....
XXX....,..,~-- H
~~~~r-~tw~A~~~1___________ ~
0<3:0> - T. -E
xx:xx:xxxxx:>OO
VALID
NONMONOiONIC INPUTS
Figure 7 • DC022 Write Access Timing
6-18
Confidential and Proprietary
L
-
~ K-"v
0<3<» _T
V "
"\..
-L--1.5.
S2 CLOSED.
0<3.0>
::
~~_~5 -fs,_~~~~~_____ ~ .~.~
.S.1 CLOSED,
S2 OPEN--
.
5"v
_ S1 OPEN-
T
...
. ..
. .
..
v
Vo..
..
. V
\------------V:
-0.5 V
\;
_ 1.5 V
...
V
SIANI}S2CLOSED
---O.OV
TTL OUTPUTS
~-"3V·.
~"1
0<3:0> -E
j'""-1.-3-V---
VIH
t--'-too~
----VOl
____. . . !-1.3
. V
~
EeL OUTPUTS
RDEN-T,· E
HIGH
10£
(MAX)~"";'..",.....,..,.,.--,~
toE
D<3:0> - T, -E
.~lf'7':''!''o-~-----
{MINI-+t--~___'"
__
H
~~--~--~~~-------------l
"""".,--,----to!--toD (MAXI
,....._.........-.+-+-too (MIN)
----~P~F~F-~~~~--~~~n------H
~~---~~~~~~~~------L
'j
>,
NoNMONOTONIC INPUTS
Figure 8· DC022 Enable and Disable Signal Timing
Confidential and Proprietary
6-19
0<3:0> -
T_____
X--U
~
tos
¥=:---_1=.5=~========::
~t~~
v
TTL PORT
Eel PORT
0<3:0> - T. - E
A<3:0> - T. - E
WREN - T. - E
~~TT~~~------------~~~~---H
YYYXtXfYX.
VAllO
~tVS-i-1 t~
XXXXX
r-
:XXX:.lL,~"'.l..""
_-___
- _-V=A_l-IO=====.:...I~_-.;. ':"'=.:XXXXXX;;;;::==:
\
~~ .~twP-1 ~tAH
HIGH :xxx lOW XXX
HIGH
NONMONOTONIC INPUTS
Figure 9· DC022 Write Sequence Timing
6·20
L
, COnfidential and Proprietary
:
-
DC022
TEST
POINT
FROM
OUTPUT
DIODES
IN916
OR
IN3064
• Ct INCLUDES PROBE CAPACITANCE
Load A TTL Circuit
FROM
TEST
OUTPUT >---"""'---'--<>POINT
25
n
- 2.0 V
• CllNCLUDES PROBE CAPACITANCE
load B TTL Circuit
Figure 10· De022 ac Output Load Circuits
Confidential and Proprietary
6-21
• Features
• High-speed, 8-charmel equals checker function
• TTL compatible inputs and output
• Description
The DC 102 equals checker, contained in a 20-pin dual-inline package (DIP), provides eight dualinput channels to compare data in pairs for equality. The equals checker output is a low level
when anyone or mo~ input pairs are not at equal logic levels. Figure 1 is a simplified logic diagram of the OC102.
INOA (1l - - - ' \
INOB (2)
---I,
IN1A (3) ---'\
IN1B(4)--J
IN2A(5),~
IN2B (6)--J
I N3A (7) ---'\
IN3B (8)--1
(9) OUT
IN4A(12)~
--I
E
IN5A (14)---,\
IN5B (15)
F
IN4B (13)
--I
IN6A(16)~
IN6B (17)
IN78 (18)
IN7B (19)
---J
--1
---J
NOTE:
Numbers in ( ) Denote Terminal Numbers.
Figure 1 • DCI02 Simplified Logic Diagram
Confidential and Propri~
6-23
.DC102
The DC 102 is provided in tbefollbwing twO variations..Referto Table:; for the ac parameters for
each variation .
• DC102: Digital part no. 1913888-00 and 1913888-01
. Pin and Signal Description
The input and output signals and the power and ground connections for the DC 102 20-pin DIP
are shown in Figure 2 and summarized in Table 1.
INOA
Vee
lNOB
IN7B
INIA
IN7A
INIB
INBB
IN2A
IN6A
IN2B
IN5B
IN3A
INSA
IN3B
IN4B
OUT
IN4A
GND
NC
TOP VIEW
Figure 2· DC102 Pin Assignments
Confidential and Proprietary
OCl02
Table 1 • DCI02 Pin and Signal Summary
Pin
1,2
INOA,INOB
input
Input,AO and BO-Dual data inputs to ga~ A
3,4
IN1A,INlB
input
Input Al and Bl-DuaI dat~inPUts togat:eB
5,6
IN2A,IN2B
input
InputsA2 arldB2~Dualdatitfuputs to pte C
7,8
IN3A,IN3B
input
Inputs A3 andIH~Dual.data'iripdts to gate D
12,13
IN4A,IN4B
input
Inputs A4 and B4-Dual data inputs to gate E
14,15
IN5A,IN.5B
inPu,t
16,17
IN6A,IN6B
input
18,19
IN7A,IN7B
9
OUT
11
NC
10
GND
input
Ground-Ground
reference
._
"
u._
_,'.'._
20
V
input
Voltage---Pdwer supplyvolr:age
Inputs A6 and B6-Dual data inputs to gate G
output**
No connection
*All signals are TTL levels
**Open collector
Functional Description
Figure 3 is a functiorull symbol of the DC 102 that shows the input signa,l groups.
EIGHT A
INPUTS
DC102
EIGHT B
INPUTS
OUT
OUTPUT
Figure 3 • DC102 Functional Symbol
Confidentialahd Proprietary
6-25
00102
• Specifications ,
The mechanical,. electrical, and environmental characteristics and spedfications for the DC 102
are described in the following pa'ragraphs. The test conditions for the electrical values are as
follows unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for the general
specifications of integrated ci.t:cuits.
• Power supply voltage Ned: 5.0 V ±5%
Mechanical Configuration
The physical dimensions of the DC 102 20-pin DIP are contained in Appendix E.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the relia.
bility of the device.
• Supply voltage (Vcd: 7.0 V
• Operating temperature (TA): O°C to 70°C
• Relative humidity: 0 to 95% (noncondensing)
Recommended Operating Conditions
• Supply voltage (Vcd: 5 V ± 5 %
• Supply current (led: 160 rnA
de Electrical Clwacteristies \
The dc electrical parameters of the DC 102 for the operating voltage and temperature ranges
specified are listed in Table 2. Refer to Appendix C for the test circuits configurations referenced
in the tables.
6-26
Confidential and Proprietary
00.2
~
18ble 2 • DC102 de Input and Output Parameters
Symbol Test Condition
Units
. Requirements
Min.
Max.
Low-level
input voltage
Vn.
0.8
High-level
input voltage
Vm
Low-level
input current
In.
V1L =0.4 V
·Vcc ... 5.25V
0.1
High-level
input current
1m
VIH==2.7V
Vee =5.25 V
-0.1
Input current
at maximum
input voltage
II
Vm=7V
Vee=5.25 V
Low-level
output voltage
VOL
Vcc=4.75 V
I OL =150rnA
Pin 1=0.8V
All other
inputs=2.0 V
Vee=4.75 V
I OL =120rnA
Pinl=0.8V
All other
inputs =2.0 V
Test
Circuit
V
C1,a
V
Cl
-0.2
rnA
C4
0.2
rnA
C4
rnA
C4
055
V
C2
0.5
V
C2
rnA
C1
V
C3
rnA
C7
2.0
10
Output reverse
current
loR
Vcc=4.75 V
VQH=3.75V
All inputs""
2.0V
0.1
Input clamp
voltage
VI
Vee=4.75 V
11 =-18 rnA
-1.2
Supply current
Icc
Va:. =5.25 V
Pin 1 ""Vm,
all other inputs
=Vn."!'
160
*Connect 330 resistor from Vee to OUT (Pin 9)
Confidential and Proprietary
6-27
-
···J:)Cl82
ae Electrkat Characteristics
.'
.
".
The voltage Waveforms and propagation~elays symbols for the input and output signals l1re ...
shown in, Figure 4 and define4 in Table}. Refer to Figure .5 for' the load ·circuit used in measuring
the propagation delays. The following t~st conditions apply to the ac propagation delay measurements.
• V'L=O V to 0.8 V,Vm=2.0 V to 3.5 V for inputs not being tested.
• The DCI02 must meet the speed requirements for the specified input voltage range and performance must not be degraded by momentary negative voltage spikes on the inputs.
• The nominal test conditions are Via (0) =0 V, V.. (1)=3.0 V, V1L =0.5 V and Vm =2.7 V.
I-- tpw-----l
3V - - -
I
I
90%--+>-----........
tR = IF = 0.5 V/ns
tpw = 180 ns
I
OV
V;n:O V ~ (V;nO) ~0.8 V
I
1
t-*I tR
2.0 V ~ (Von 1} ~ 3.5 V
Input Waveform
~1.3V
INPUT (V;n)
Output Oul-Of-Phase
-./j "- .
.~ V(O)
+13vl. ~
.:
IPlH
--oooj
:
~ I • ..>
too-
--oooj
v
too- IPl"
~1.3.'V
~I.H:~
OiJtput In-Phase
I
IPCH
---i
I
I
I-- -I
I
I-- tPLH
Figure 4 • DC102 ac Signa/Timing Delay
6-28
Confidential and Proprietary
DC 102
Table 3 • DCI02 lie Propagation Delay
Symbol
tPLJI
Delinition
Units
Requirements
1913888·00*
Min.
Max.
1913888·01**
Min.
Max.
Low-to-high level
output
20
13
ns
High-to-Iow level
20
13
ns
output
*CL =150pF
**CL =100pF
Vee
~
3!l
FROM
OUTPUT
TEST
POINT
1
CL
Figure 5 • DCI02 ac Load Circuit
Confidential and Proprietary
6-29
• Features
• Separate transmit and receive frequency out{luts
• Program selectable baud rates from 50 to 38,400
• External TTL dock or crystal inputs
• TTL compatible inputs and outputs
. Description
The DC301 dual baud·rate generator, contained in a 18-pin dual-inline package (DIP), provides a
transmit and receive output to control the transfer of serial line information. Figure 1 is a simplified block diagram of the DC301 baud rate generator.
STT )-'----.
XMIT
FREQ
REC
FREQ
RA
REC
ADDA
12)
{ Re
(11)
(9)
~~~
Ac
Ao
Vee GND Voo
STR >-(B...:.}_-,
Figure 1 • DC301 Simplified Block Diagram
Confidential and Proprietary
6·31
'iDC301
TheDC301 consistJlofa crystal-controlled Oscmato~1 two programmable frequency dividers, and
two divide-by-two counters. The input frequency to the oscillator can be supplied by an external
TTL generator or controlled bya crystal connected direccly to the De30l. Separate programmable
inputs are provided for both the transmit and receive channels. These inputs select their respective baud rates that may deviate depending on the frequencyof the crystal of TTL input. The
frequency decode and control logic is ROM·based and controls the functions of the divider.
. Pin and Signal Description
The input and output signals and the power and ground cormections for the DC30118-pin DIP
are shown in Figure 2 and surrunadzed in Table 1.
XTAl/EXTl
XTAljEXT2
Vee
XMIT FREO
REe FREe
XMIT ADDRTA
REe ADDR R"
XMIT ADDR Ta
As
XMIT ADDR T c
REC ADDRRe
XMIT ADDR To
RECADDR.
STT
STR
GND
Voo
NC
REe ADDR
TOP VIEW
Figure 2· DC301 Pin Assignments
6-32
Confidential and Proprietary
-
Table 1 • DC301 Pin and Signal Summary
,
Input/Output
-- r
Delinition/Function
Pin
Signal
1
XTAL/EXTl
Crystal/external 1-Connects to one lead of the
crystal or to a TTL input.
18
XTAI./EXT2 .
Cryst~~ternal:2T:cpnnectsto .the other lead of
the Cry$ta1; the 6P1;ldsitepolarity a TTL input, or not
connected.
17
XMITFREQ
output'
Transmit. frequency .(£T) ___ The fre9ue1l:t'youtpnt
selected by the ttllllsIIliuer address.
.
3
RECFREQ
output'
Receive .frequenCY(£R) ___ The frequency output
selected byt;l}/: ~iver·ac:ldt:ess.
.'
RECADDRRA,
input'
Receiver address-Four receiver address inputs that
select the output freq\lency of the receiver. (RECV
4~7
R..Rc,RD
OUT).
8
16-13
STR
input'
Strobe receiver addliss-Asserted' tolqad the
receiver address into the receiver address register.
XMIT ADDR TA> input2
'Trinsnutaddress--Fol.lf· transmit ad~it:tputs
that select the output frequency of the transmitter
TB,Tc,To
(XMITOUT).
12
. 10
11
SIT
input'
NC
GND
No connection
. input
2
9
Strobe transmitter address-Asserted to load the
transmitter address into the transmitter address
register.
input
Voo
input
Voltage-Power supplY'l2(V connection'
ITTL levels or crystal input
2TTLleve1
Confidential and Proprietaty
...
DC301
Frequency Selection
. .
The DC301 is available in several variations depending on the baud rates required and the external .
clock connections as listed in Table 2.
.
Table 2 • DC.301 Electrical Variations
Digital
External Oock
Baud Rates
Part Number
Power
Supplies
2112623-00
TTL
50 to 19,200
(Table 3)
12V,5V
or.5 V only
2112623-01
TTL or crystal
50 to 19,200
(Thble 3)
12V,5V
or 5 V only
2112623-02
TTL
50 to 19,200
(Thble 4)
12V,5V
or 5 V only
2112623-03
TTL
50 to 10,200
(Table 5)
12V,5V
or 5 V only
2112623-04
TTL
100 to 38,400
(Thble 6)
12V,5V
or 5 V only
2112623-05
. TTL
50 to 19,200
(Table 3)
5 V only
Thbles 3 through Glist the transmit and receive addresses required to select the desired baud rates
for the crystal frequency specified. The tables also contain the characteristics of the DC30! signals for the selected baud rates.
6·34
Confidential and Proprietary
DC30t·
Table 'oOC3OlBtud.lbl1eSeleetion andCbal'ileteristies(Crystal Frequency S.0688 MHt)
Actual
Duty
Tbeoretical
1iansmit/Reeeive
Address
D C B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
a
0
1
1
0
0
1
1
Rates
Frequency .
Frequency
Percent
l:6X C1ock(ld&) 16XClock(kH:t) Error
Cycle
A
%
Divisor
0
1
0
1
0
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
0.8
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
5'0/50
50/50
50/50
50/50
50/50
50/50
48/52
50/50
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
Baud
1
0
1
0
1
0
1
0
1
0
1
0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
0.016
--'
-.;
0.253
3.121
Table 4 OClO1 ~~~ ~.~~~(~~ l.1~80Mliz)
.. Duiy
.Adual, .
Theoretical
'liansmit/Receive
Address
Frequenc;y;
Baud Frequ~.
~ Cycle
D C B A Rate
Divisor
16X.CJo.ck «db) 16X;~~· EmH:; %
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
50
0.8
1.2
75
110
1.76
134.5 2.152
150
2.4
200
3.2
300
4.8
600
9.6
1200
19.2
28.8
1800
2000
32.0
2400
38.4
57.6
3600
4800
76.8
9600 153.6
19200 307.2
0.8
1.2
1.76
2.1523
2.4
3.2
4$
9.6
19.2
28.8
32.149
38.4
57.6
76.8
153.6
307.2
Confidentialand.Proprietary
0
0
-.006
..,.019
0
0
0
0
0
0
+.465
0
0
0
0
0
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
44/56
3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9
6-35
:~
Table'· nC301 S.ud:aate~a and ~~·,cm~Fr~eaey~;."18.nM~)
Duty
Theoretical
Acw..
Tr8llsmit/Reeclv.
Address
Baud Frequency
Percent Cycle
Frequenq
D C B A Rate
16X Oock (tub) 16X Oock (kIh) ErrQf
%
Divisor
0
0
0
0
0
.0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
a
1
1
1
0
0
0
0
1
1
1
1
1
1
0
.l
0
.1
0
1
0
1
0
1
0
1
0
1
0
1
50
0.8
75
1.2
110
1.76
134.5 2.152
150
2.4
200
3.2
4.8
300
600
9.6
1200
19.2
1800
28.8
2000
32.0
2400
38.4
57.6
3600
4800
76.8
9600 153.6
19200 307.2
0.8
1.20
1.76
2.152
2.4
3.2
4.8
9.6
19.23
28.8
32.0
38.33
57.6
76.8
153.6
307.2
0
0
0
0
O·
0
0
0
+;14
0
0
-.17
0
0
0
0
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
7523
5015
3420
2797
2508
1881
1254
627
313
209
188
157
104
78
39
20
Table 6 .'00301 Baud RateSeleetion aad Characteristics (Crystal Frequency 5 •.52960 MHz)
TransmitjReceive
Address
D C B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
6-36
Theoretical
Actual
Percent
Frequency
Frequency
Rate . 16K Cloc:k:!(kHz) 16X Clock (kHz) Error
Duty
Cycle
%
Divisor
100
1.6
2.4
150
220
3.52
269
4.304
300
4.8
400
6.4
600
9.6
19.2
1200
2400
38.4
57.6
3600
4000
64.0
4800
76.8
7200 115.2
9600 153.6
19200 -307.2
38400 614.8
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
44/56
3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9
Baud
A
0
0
0
1
1
0
O·
1
1
0
0
1
1
0
0
1
1
1
0
1
"0
1
0
1
0
1
0
1
0
1
0
1
1.6
2.4
3:5197
4.3032
4.8
6.4
9.6
19.2
38.4
57.6
64.298
76.8
115.2
153.6
307.2
614.8
CoafidentialandProprietary
0
0
-.006
-.019
0
0
a
0
0
0
+.466
0
0
0"
0
o.
-
• Specifications
The mecl1ankal, e1ectrlcal,and environmentalchMacteristics and 'Speclficationsfor the ))C301
are described in the follOwing paragraphs; The test conditions for the electticalv~ are as"
follows unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for tbet!en~ .
era!. specifications of integrated circuits.
• Power supply voltage (Vcc): 5.0 V ±5%
• Power supply Voltage 0 nshy increasmgthe minimum strobe width by 50 ns to a
total of 200 ns.
VIH
STROBE(STR/STTI
VIL--.L.--
VI~
ADDRESS
VOL
• Address 'need only be valid during the last Tpw, Min time of the input strobe,
Figure 3· DC301 ac Timing Parameters
Confidential and Proprietary
"-_ .. _"-'-----""--------,
6-39
,------------------
..
-
DC10l
External Frequency
Figure 4 shows typical external circuit;; l,lSed to copnect the TTL frequency inputs and crystalcontrolled inputs to the DPOL
'f'fL •
INPUT
TTL'
INPUT
DC301
DC301
• totem pole or open collector output
Typical TTL Input Circuit
DC301
Typical Crystal Input Connections
Figure 4 • DC301 External Frequency Connections
6-40
Confidential and Proprietary
Instruction Set
This appendix provides a Sllnunary of the VAX-llinstructions implemented by the MicroVAX
78032, the floating-point instructiolUisUPPO~ by the floating-point unit, and the emUlated
instructions that are assisted by the MicrqVAX 780n's microcode. The; standard notat,ion for
operand specifiers is
< name> < access type> < data type >
1. Name-A suggestive name for the ot>erand in the context of the instruction. It istbe capitalized
name of a register or block for implied operands.
2. Access type-A letter denoting the opetlUldspecifier access type.
a = address operand
b =branch displacement
m:"modified operand (both readanttwritten)
r =read only operand
v = if not "Rn," same as address dperand, otherwise R[n + 1]'R[n]
w =write only operand
.
.
3. Data type-A letter denoting the data type of the operand.
b=byte
'
d = D_floating
f =F_.JIoating
g = GJIoating
l=longword
q=quadword
v = fidd (used only in implied operands)
w=word
* = multiple longwords (used only in implied~)
4. Implied operands-Locationf! that ~. actesseclby the instruction, but nonpedfied in an
operand, are denoted by braces { }. The abb1'eViations for condition codes are
* =conditionally set/cleared
- =not affected
O=cleared
1 = set
The abbreviations for exceptions are
rsv = reserved operand fault
iov = integer overflow trap
idvz =integer divide by zero trap
fov = floating overflow fault
fuv = floating underflow fault
fdvz == floating divide by zero fault
dov = decimal overflow trap
ddvz = decimal divide by zero trap
sub = subscript range trap
prv = privileged instruction fault
Opcode values are given in hexadecimal.
CI;mfidentialandProprietary
A-l
APt""-~
-...... .l=_ A
• Integer. Atithmetic and Logical Instructions
OP Mnemonic and Arguments
Description
NZ VC Exceptions
58 ADAWI add.rw, sum.mw
Add aligned word interlocked
80 ADDB2 add.rh, sum.mb
CO ADDU add.rl, sum.ml
AO ADDW2 add.rw, sum.mw
Add byte 2-operand
Add long 2-operand
Add word 2-operand
" " " "
" " * *
81 ADDB} add1.rb. add2.rb, sum.wb
Cl ADDL3 addl.rl, add2.rl, sum.wI
Al ADDW3 addl.rw, add2.rw, sum.ww
Add byte 3-operand
Add long 3·operand
Add word }-operand
D8 ADWC add.rI, sum.ml
Add with carry
78
79
Arithmetic shift left
Arithmetic shift quad
ASHL cnt.rb sre.rI, dst.wl
ASHQ cnt.rb sre.rq, dst.wq
8A BICB2 mask.rb, dst.mb
CA BICL2 mask.rl, dst.ml
AA BICW2 mask.rw, dst.mw
Bit clear byte 2-operand
Bit clear long 2-operand
Bit clear word 2-operand
8B BICB3 mask.rb, sre.rb, dst. wb
CB BICL3 mask.rl, sre.rl, dst.ml
AB BICW} mask.rw, sre.rw, dst.mw
Bit clear byte 3.operand
Bit clear long 3·operand
Bit clear word }-operand
88 BISB2 mask.rb, dst.mb
C8 BISU mask.rI, dst.ml
A8 BISW2 mask.rw, dst.mw
Bit set byte 2-operand
Bit set long 2-operand
Bit set word 2-operand
89 BISB3 mask.rb, sre.rb, dst.mb
C9 BISO mask.rl, sre.rI, dst.ml
A9 BISW3 mask:rw, sre.rw, dst.mw
Bit set byte 3-operand
Bit set long 3·operand
Bit set word 3-operand
93 BITE mask.rb, sre.rb
D3 BITL mask.rI, sre.r1
B3 BITW mask.rw, sre.rw
Bit test byte
Bit test long
Bit test word
"
* * *
* * * "
* * * *
* " * *
* " " *
* " " *
" " * 0
" * * 0
* " 0 * * 0 * " 0 -
"
"
"
"
"
"
"
* 0
"
"
* "
* "
" "
" *
" *
" "
*
0
0
0
-
0
0 * 0 1 0
1 0 1 0 I 0 -
'-
CMPB srel.rb, src2.rb
B1 CMPW srcl.rw, src2.rw
Compare byte
Compare long
Compare word
" "
" "
" "
98
99
F6
F7
33
32
Convert byte to long
Convert byte to word
Convert long to byte
Convert long to word
Convert word to byte
Convert word to long
*
*
*
*
*
*
97 DECBdif.mb
D7 DECLdif.l
97 DECWdi£'mw
Decrement byte
Decrement long
Decrement word
*
"
* * " *
86 DIVB2 divr.rb, quo.mb
C6' DIVU divt:d, quo.m1
A6 DIVW2 divr.rw, quo.mw
Divide byte 2-operand
Divide long 2-operand
Divide word 2-operand
A-2
Confidential and Proprietary
"
0
0
0
"
"
"
"
"
0 0
0
0 iov
0 iov
0 iov
0
* 0
" *
* "
* *
* 0
* *
* * "
" * *
*
*
iov
10V
0 -
0
91
CVTBL src.rb, dst.wl
CVTBW src.rb, dst.wl
CVTLB src.rl, dst.wb
CVTLW src.rl, dst.ww
CVTWB src.rw, dst.wb
CVTWL src.rw, dst. wI
iov
-
Clear byte
Clear long
Clear quad
Clear word
Dl CMPL srcl.rl, src2.rI
iov
iov
iov
0 0
0 -
CLRBdst.wb
CLRLdst.wl
CLRQdst.wq
CLRWdst.ww
0
0
iov
iov
iov
-
94
D4
7C
B4
0
0
iov
iov
iov
* iov
0 iov, idvz
* 0 iov,idvz
* 0 iov, idvz
Preliminary
N Z V CEEeptions
87 DIVB} divr.rh, divd.rb, quo. wb
C7' DIVL3 divr.rl, divd.r1, quo. wi
A7 DIVW3 divr.rw, divd.rw, quo. ww
Divide byte }·operand
Divide long J·operand
Divide word }-operand
7B' EDIV c1inrl, divd.rq, quo. wI, rem. wI
Extended divide
7A' EMULmulr.rl, rnuld.rl, add.r!, prod.wq . Extended multiply
96 INCB sum.mb
D6 INCL sum.mI
B6 INCW sum.mw
Increment byte
lnaement long
Increment word
92 MCOMB stub, dst.wb
D2 MCOML slt.rl, dst.wl
B2 MCOMW Slt.rw, dst. ww
Move complemented byte
. MCilVecomp1ementedlong
Move complemented word' , .
8E MNEGB SlC.rb, dst.wb
CE MNEGL Slt.rl, dst. wI
AE MNEGW Slt.rw, dst.ww
...
... • 0 iov, idvz
...
...
....
iov, idvz
'i.m'jidvz
'
... ...
iov,idvz
* ... ... "', iov'
... ... ... ... iov
• ... 0 -
* * 0 ... ... 0 -
Move negated byte' ,
MOve negated long
Move negated word
"'*"'*Wv
* * * * ioV
* * * * iov
90 MOVB Slt.rb, dst. wb
DO MOVL Slt.rl, dst.wl
BO MOVW SlC.rw, dst.WW
Move byte
1o* 0 -
Move lopg
Moveword .
* * 0 ... ... 0 ....
9A MOVZBW slt.rb,dst.wb
9B MOVZBL slt.J,"b, dst.wl
3C MOVZWL Slt.rw, dst.ww
Move ze~nct~ lJyretoword
Move zet'CH!Xtep~byte toloflt?; .
Moveze~ word to long
o :; :
o ..
84 MULB2 mulr.rb, prod.mb
"Mubiply byte,~.()perand' ,
C4' MULL2 mulr.rl, prod.mlMultiply long 2-operand
A4 MULW2 mulr.rw, prod.mw
Multiply ~h~1perand
85 MULB3 mulr.rb, mUld.rb, prod.mb
C5 t MULL} mulr.:tI, muld.rl, prod.mI
A5 MULW3 mulr.rw; muld.rw, prod.mw
Multiplybyte}-opetahd
Mqltiply, long 3-operand
Multiplyword }-operand
DD PUSHL Slt.rl,
Push long
9C ROTLcnt.rb, SlC.rl, dst.wl
Rotate long
D9 SBWC sub,rl, dif.ml
.SubtraCt Witbcarry
82 SUBB2 sub.rb, dif.mb
C2 SUBL2 sub;rl, c1if.ml
A2 SUBW2 sub.rw, dif.row
Subt1;\lct,byte 2-operand
Subtract long 2-operand
Subtract word 2·operand
83 SUBB} sub.rh, min.rb, dif.mh
C3 SUBL} sub.rl, min.rl, dif.mI
A3 SUBW3 sub.tw, min.rw, dif.row
Subtract byte 3-operand
Subtract Ion~ }·operand
Subtract wp.rd3~
95 TSTB s l t . r b r e s t b y t e
D5 TSTL SlC.rI
'reSt long
B5 TSTW Slt.rw
rest word
o ... 0 0 -
0
'. •
* *'
...
...
•
... .... ...
* ... ...
* * *
..,*
,
0 ,iov
0 iov
0 iov.
0 iov
0/ ioV
0 iov
'" "lov
* ... ... *i iov
...
iov
"... ...
iov
*
*
... '" ...
* * *
* * *
*
*
...
... .. 0 0
... * 0 0
... * 0 0
Exclusive or byte 2-operand
Exclusive or long 2-operand
Exclusive ()I: word 2.;operand
.. .. 0 <\'
* 0 -
8D XORB3 mask.rb, SlC.rb, dst.wb
Exclusive or byte 3-operand
CD XORL} mask.rl, slt.rl, dst.wlExclusiveor long 3-operand
AD XORW3 mask.rw, Slt.rw, dst. ww
ExclusiVe or word 3-operand
* * 0'-
8C XORB2 mask.rb, dst.mb
CC XORL2 mask.rI, dst.ml
AC XORW2 mask.rw, dst.row
1ov"'"
... iov
* igv
* *
0,,-
* * 0 ** 0 -
1. The MicroVAX 78132 FPU, when present; accelerates execution of these integer multiplication
instructions.
Confidential and Proprietary
A-3
-
Preliminary
2. The MicroVAX 78132 FPU, when present, ~cd.erates execution oImese inte~'; division,
instructions .
• Address .Instructions
OP Mnemonic and Arguments
Description
N Z V CExceptioDS
9E
DE
7E
3E
MOVAB src.ab, dst.wl
MOVAL {=F} sn:.al, dst.wl
MOVAQ {=D=G} sn:.aq, dst.wI
MOVAW sn:.aw, dst.wl
Move address of byte
Move address of long
Move address of quad
Move address of word
*
...
*
...
9F PUSHAB sn:.ab, {-(SP).wI}
DF PUSHAL {=F} sn:.al, {-(SP).wl}
7F PUSHAQ {=D=G} sn:.aq, {-(SP).wI}
3F PUSHAW src.aw, {-(SP).wl}
Push address of byte
Push address of long
Push address of quad
Push-address of word
* * 0 -'
* * 0 * * 0 -
...
...
...
...
* *
0
0
0
0
-
o-
• Variable-length Bit Field Instructions
OP Mnemonic and Arguments
Description
NZVC
Compare field
* '" o * rsv
ED CMPZV J?Os.rl, size.rb, base.vb,
{field.rv J, sn:.rl
Compare :tero-extehded field
**O"'rsv
EE EXTV pos.rl, size.rb, base. vb,
{field.tv} , dst.wl
Extract field
**O-rsv
EF EXTZVpos.rl, size.rb, base.vb,
{field.rv}, dst.wl
Extract zero-extended field
* * o .- rsv
Insert field
----rsv
Find first clear bit
**O-rsv
Firid first set bit
**O-rsv
EC CMPV pos.rl, size.rb. base.rb,
{fieId.rv},sn:.rl
FO INSV sn:.rl, pos.rll size.rb,
base.vb, {field.wv}
EB FFC s~.rl size.rb, base.vb,
{field.rv} , findpos. wI
EA
FFS$~s.rl,
size.rb, base.vb,
{field. tv} , findpos. wI
• Control Instructions
OP Mnemonic and Arguments
Description
N Z V C Exceptions
9D ACBB limit.rb, add.rb,
index.mb, displ.bw
Add compare and branch byte
***-iov
Add compare and branch long
***-iov
Add compare and branch word
***-iov
FI ACBL limit.rl, add.rl, index.mI,
displ.bw
3D ACBW limit.rw, add.rw,
index.mw, dispLbw
F3 AOBLEQ limit.rl, index.mI,
displ.bb
F2 AOBLSS limit,rl, index.mI,
displ.bb
Add9De and brahch9n less or equal
Add one and branch on less
Con£i4entj.al1Uid Proprietary
***-iov
OP Mnemonic and Alpments
Desuiption
IE BCC{=BGEQU}dispLhb
iF BeS{ =BLSSUf~pl.bb
13 BEQL{ "",BEQIiU},displ.bb
18 BGEQ disl'tbb
14 BGTRdispLbb
lA BGTRU displ.bb
15 BLEQ displ.bb
IB BLEQU displ.bb
19 BLSS disp1.bb
12 BNEQ {==BNEQU} displ.bb
IC BYe displ.bb
10 BVS displbb
Branch on carry clear
Branch on carry set
El BBCpos.r1, base. vb. displ.bb,
{field.tv}
'..
:ara~onequal
Bratlch on Fater or equal
Branch On greater
Btanch on greIlterunsigned
Branch on less Or eqUal
Branch on less or equal unsigned
Branch on less
Branch on not equal
Brandt otI~:dear
Branchon'~set
f' :_
.
Branch oribitdeat
----tSv
EO BBS poul, base.vb, displ.bb,
{field.tv}
E5 BBCC pos.rI, base.vb, dispJ.bb,
{field.mv}
E3 BBCSpos.rl, base.vb, dispLbb,
{field.mv}
.
E4 BBSC poul, base.vb, displ.bb,
{field.mv}
E2 BBSSpos.rl, base.vb, disl'l.bb,
{field.mv}
E7 BIlCCI pos.rl, base.vb, dislp.bb,
{field.mv}
Branch on bit.set
rsv
Bralichon bit clear and Clear
Branch on bit~and set
Brancho~ bitsetlllld clear
rsv
Branch on ~tset aild set
" Branch 9Il'hlt ~. and clear intciiloc;~
rsv
Branch on bit set and set interlocked
rsv
E6 BBSSIpos.rl, base. vb, dislp.bb,
{field.mv}
E9 BLBC src.rI, displ.bb
. E8 BLBS src.rl, dispI.bb
U"BRB displ.hb
31 BRWdispl.bw
10
BSBB displ.bb {-(SP). wI}
30
BSBW displ.bw
t ..(SP).wl}
Branch on low bit clear
Branch on I9W bit set
Branch .wi1)1 byte;dis~ment ...
,·B~with~.pl~nt
Branch tosl.l~Wi.h bite
displacement
Branch to subtoutirlewith word
disp~nt"
. ..
. ..
8F CASEB selectoub, base.rb,
limit.rb, displ.bw-list
CF CASEL selectoul,base.rl,
limit.rI, displ.bw·list
AF CASEW selectouw, base.rw,
limit.rw, displ.bw-list
Case long
17 JMPdst.ab
Jump
16 ISH dst.ab, {-(SP).wl}
Jump to sUhfui:ttitie
Return from subroutine .
05
RSB {(SP) + .rI}
F4 SOBGEQ index:mI, displ.bb
F5 SOBGTRindex.ml; displ.bb
*
* 0 "
* *
o
*
Case word
Subtract one and branch on gt'eater
or equal
..'
..•
*"*-iov
Subtract one and branch on greater
" ". * -
iov
A-5
-,.
Preliminary
• ProcecIure Call1nstructions
OP Mnemonic and Arguments
Descript.on
NZ VC Exceptions
FA CALLG arglist.ab, dst.ab, {-(SP).w'}
Call with general argument list
0 0 0 0 rsv
FB CALLS numarg.rl, dst.ab, {-(SP).w'}
Call with argument list on stack
0 0 0 0 rsv
04 RET {(SP) + .r'}
Return from procedure
* * * * rsv
• Miscellaneous Instructions
OP Mnemonic and Arguments
Description
N Z V C Exceptions
B9 .BICPSW mask.rw
Bit clear processor status word
****rsv
B8 BISPSW mask.rw
Bit set processor status word
* * * *
03
BPT {-(KSP).w'}
Break point fault
o
0 0 0
00
HALT {-(KSP).w'}
Halt rt,be write access
-
- - -
rsv,prv
'"
'"
rsv, prv
'"
* 0
-
'" 0 '" 0 '" '" * '"
nv, prv
0
0
02 REI {(SP)+.r'}
07 SVPCTX {(SP) + .r*, PCB.w·}
0
Save PIXlCe5S context
(kernel rnode only) •
rsv
priv
• Microcode-assisted Emulated InstructiOns
The MicroVAX 78032 provides microcode ass~tllnce for the etnulatipn of these instructions by
system software. The processor processes the I)perand SJ:leCiftet!i,.~tes II; stan.dardargument list,
and takes an emulated instruction fault. For a description of e~ted instructionprt'lCe$sing, refer
to the MicroVAX 78032 User's Guide.
OP Mnemonic and Alpmetits
Description
N Z V C
20 ADDP4 addlen.rw, addaddr.ab, sumlen.rw,
suma.ckb:ab
Add packed 4-operand
'" '" '" o rsv, dov
21
ADDP6 addllen.rw, addladdr.ab. add2len.rW,
add2addr.ab, sumlen.rw, swnaddr.ab
Mdpacked ~pa-and
F8 ASHP cnt.rb, srclen.rw, srcaddr.ab, round.rb, .·Arithmetic shi£~.and round
packed
.,
dstlen.rw, dstaddr.ab
29 CMPC3 len.cw, sreladdub, src2addr.ab
Compare character
3-operand
2D CMPC5srellen.rw, srcladdr.ab, fill.rb,
Compare ch\U'llctet
src2ien.rw, sre2adckab
5-operand . . :
35 CMPP3 len.cw, sre1addr.ab, sre2addr.ab
37 CMPP4 srellen.rw,srcladckab, src2len.rW.
src2add.ab
.Com{>i!l"e packed 3-operand
OB CRC thl.ab, inicre.d, strien.rw, stream.ab
Calculate cyclic
redundancy check
F9 CVTLP src.rl, dstlen.rw, dstaddr.ab
Convert long to packed
36 CVTPL srelen.rw, srcadckab, dst.wl
Convert packed to long
08 CVTPS, sruen.rw, srcaddr.ab, dstlen.rw,
Convert packed to leading
dstaddr.ab
separat;e
09 CVTSp, srelen.rw, srcaddr., dstlen.rw,
Convert leading separate to
packed
dstaddr.ab
Confidential and Proprietary
'"
'" '" o
'"
'" "
'"
.
.
'"
'"
.,.
.,
.. ..
'"
'"
.,.
'it
'"
r5V,
dov
0 rsv, dov
o
.'it
0
..
0 0
0
'"
0 0
'" '" .'.,."
'it
EKeprlODS
.,
,.
0 rsv, dov
0 rsv, iov
0 rsv,dov
0 rsv,dov
A-7
-.
Appendix A
OP Mnemonic and Argumep.ts
Description
24 CVTPT srden.tw, srcaddr.ab, tbladdr.ab,
dstIel'l.tw. dstaddr.ab
26 CVTTP srclen.tw, srcaddub, tbladdr.ab,
dstlen.rw, dstaddr.ab
Convert packed to trailing *
Convert packed to trailing
* * * 0 rsv,dov
27 DIVP divrien.rw, divraddr.ab, divdien.rw,
quolen.tw, quoaddr.ab
Divide packed
* * * 0 rsv, doo, ddvz
38 EDITPC srcien.rw, srcaddr.ab, pattern.ab,
dstaddr.ab
Edit packed to character
string
3A LOCC char.rb, len.rw, addr.ab
Locate character
* * * * rsv, doo
o * 0 0
J9
MATCHC ohilen.rw, objaddr.ah, srclen.rw,
srcaddr.ab
* * o
Match characters
o *
34 MOVP len.rw, srcaddr.ab, dstaddr.ab
Move packed
* * 0 0
2E MOVTC srclen.rw, srcaddr.ab, fill.rb,
tbladdr.ab, dstlen.tw, dstaddr.ab
Move translated characters * * 0 *
2F MOVTIJC srclen.rw, srcaddr.ab, esc.rb,
tbladdr.ab, dstlen.rw, dstaddr.ab
Move translated until
character
2.5
MULP mulrien.rw, mulraddr.ab, muldlen.rw,
muldaddr.ab, prodlen.tw, prodaddr.ab
rsv,doo
0 0
* * * *
Multiply packed
* * * 0 rsv, dov
2A SCANe len.rw. addr.ab, tbladdr.ab, maskrb
Scan for ch.aracter
0 * 0 0
3B SKPC char.rb, len.rw, addr.ab
Skip character
0
* 0 0
2B SPANC len.rw, len.1W, tbladdr.ab, maskrb
Scan characters
0
*
22 SuBP4sublen.rw, subaddr.ab, diflen.tw,
difaddr.ab
Subtract packed 4-operand
* * *
0 rsv, dov
~ubtract packed 6:operan,d
* * *
o
23
SUBP6 sublen.rw, subaddr.ab, minlen.1W,
minaddr.ab, diflen.rw, difaddr.ab
0 0
rsv, dov
. MicroVAX 78032 Fosting-point Instructions
These instructions are implemented in hardware if the optional MicroVAX 78132 floating-point
unit is present in the system. They must be software emulated if the MicroVAX 78132 is not
included.
OP
Mnemonic and Arguments
Description
06F
ACED limit.rd, add.rd, index.md
04F
ACBF limit.rf, add.rf, index.rf
Add compare and branch
D_floating
Add compare and branch
FJIoating
Add compare and branch
G_floating
4FFD ACBG limit.rg, add.rg, index.mg
060 ADDD2 add.rd, sum.md
040 ADDF2 add.rf, sum.mf
40FD ADDG2 add.rg, sum.mg
Add DJloating 2-operand
Add FJloating 2-operand
Add G_f1oating 2-operand
061
ADDD3 addl.rd, add2.rd, sum.wd Add D_floating 3-operand
041
ADDF3 add1.rf, add2.rf, sum.wf
Add. FJloating 3-operand
41FD ADDG3 addl.rg, add2.rg,sum.wg Add G....floating 3-operand
A-8
Confidential and Proprietary
NZ V C Exceptions
'" '"
0
* *
0 - rsv, foo, fuv
'" '"
'"
0
."
0 0 rsv, fov, fuv
'"
."
0 0 rsv, foo, fuv
0 0 rsv, foo, fuv
'" '"
'" '" '"
."
-
rsv, foo, fuv
0 rsv, foo, fuv
0 rsv, foo, fuv
* 0 rsv, £ov, fuv
'" * *
'"
rsv, fov, fuv
A~A
OP
Mnemonic _
Arguments
071
CMPD src1.ttl, src2.ro
051
CMPF srcl.rf, src2.rf
51FD CMPG srel.rg, ~.rg
CVTBD src.rb, dst. wd
04C CVTBF src.rb, dst. wf
4CFD CVTBG src.rb, dst. wg
O6C
CVTDB sre.rb, dst.wb
CVTDF sre.ro, dst.wf
CVTDL src.ro, dst. wI
CVTDW src.ro, dst.ww
CVTFB sre.rf, dst.wb
056 CVTFD src.rf, dst.wg
99FD CVTFG sre.r£, dst.wg
068
076
06A
069
048
04A' cVTFL src.r£, dst.wl
049
CVTFW src.rf, dst. ww
48FD CVTGB sre.rg, dst.wb
33FD CVTGF src.rg, dst.wf
4AFD CVTGL src.rg, dst.wl
49FD CVTGW sre.rg, dst.ww
06E CVTLD src.rl, dst. wb
04 E CVTLF sre.r~ dst. wf
4EFD CVTLG src.rl, cist.wg
O6D CVTWD src.rw, dst.wd
041:) CVTWF src.rw, dIlt.wf
4DFD CvTwG sre.rw, dst.wg
06B
CVTRDL sre.ro, cist. wI
04B
CVTRFL sre.rf, dst.wl
NZ VC Exeptions
Compare D_fIoating
Compare F.JlOating
Compare GJloating
COfl'llertbyteto DJloating
~byte toF_floating
Convert,byte·toG.-Jloating
,'Convert D..:1lOating to 'byte
Convert D.;.;.fi€iating to'F.JlOat
ConVertD;.;;;fiooting to long
ConvertD,J}qatingto word
ConvertF...,..DQating to byte
Convert l;1.Jloating to DJloat
Con:vert F.JloatingtoG.J1oat
CoIlWltF....Jlp~ting to lbl)g
CoDvtrtF~ to wOttl
Co~G~to,htte
Coma1 G.Jloating to F.Jloat
Convert GJloilting to long
Convert G.:..ftoating to -word
Convert long to D.JlOliting
Conyert long to F.Jloating
ComiertlqtOG..Ji6aJing' '
Convert woro to D.J1oating
Convert WOrd to F.Jl00
INC (B)
DEC (B)
NEG (B)
TST (B)
tWRTLCK
oo72DO
tTSTSET
COM (B)
Description
N
~aear destination
ComplemeJ:l:ftklstirultion
Increment destitmtion
Decrement des;t:Uiation
Negate destination
Test destinatiop,
Read/lock destIDation,
write/unlock RO into destination
Test destination, set low bit
Z
V
C
0
0
o:;}: '
0
1
" l'
*
*
*
'*
*
*
*
*
''It
0
'*
'"
*
*
0
0
*
*
N
Z
V
c
'*
'"
*
*
'*
'*
'*
11
"
'"
Shift and Rotate
Opcode
0062DD
006300
0060DD
00610D
0003DD
Mnemonic
Description
ASR(B)
ASL (B)
ROR(B)
ROL(B)
SWAB
Arithmetic shift rigb,t
Arithmetic shift left
Rot'aterlght
Rotate left
Swap bytes
"
*
*
*
*
*
N
Z
1:
*
0
*
*
*
0
Multiple-precision
Opoode
Mnemonic
0055DD
0056DD
0067DD
ADC(B)
SBC (B)
SXT
Add carry
Subtract carry
Sign extend
1:
*
*
*
*
vc
* *
* *
o
B-l
~--~-.-
--~--
---------.~
.
---_~~_~~_m
____ ___
~
Preliminary.
PNcessor Status (PS) Word Operators
Opcode
1067DD
1064SS
Mnemonic
MFPS
MTPS
Description
N
Z
V
Move byte from PS
Move. byte toPS
",
0
*
*
*
*
*
C
C
. Double Operand
General
Opcode
Mnemonic
Description
N
Z
V
D1SSDD
D2SSDD
06SSDD
16SSDD
072RSS
073RSS
070RSS
071RSS
MOV(B)
CMP(B)
ADD
SUB
tASH
tASHC
tMUL
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
+DIV
Move source to destination
Compare source to destination
Add source to destination
Subtract source from destination
Arithmetic shift
Arithmetic shift combine~
Multiply
Divide
Opcode
Mnemonic
Description
N
D3SSDD
D4SSDD
D5SSDD
074RDD
BIT (B)
BIC (B)
BIS (B)
XOR
Bit test
Bit dear
Bit set
Exclusive OR
0
*
*
*
*
*
*
*
*
Z
V
C
*
*
*
*
*
*
*
*
0
0
0
0
N
Z
V
*
*
*
*
*
Logkal
• Program Control
Branch
Opcodeor
Base Code
Mnemonie
Deseripdon
000400
001000
001400
100000
100400
102000
102400
103000
103400
BR
BNE
BEQ
BPL
BMI
BVC
BVS
BCC
BCS
Branch unconditional
Branch if not equal to zero
Branch if equal to zero
Branch if plus
Branch if minus
Branch if overflow is dear
Branch if overflow is set
Branch if carry is clear
Branch if carry is set
B-2
Confidential and Proprietary
C
-.
ApPendixB
Preliminary
Signed Conditional Brandt
Opcodeor
Base Code
Mnemonic
Description
N
002000
002400
003000
003400
BGE
BLT
BGT
BLE
Branch if greater than or equal to zero
Branch if less than zero
Branch if greater than zero
Branch if less than or equal to zero
-
Mnemonic
Description
BHI
BLOS
BRIS
Branchif higher
Branch if lower or same
Branch if higher Qr same
Branch i£1ower
Z
V
C
N
Z
V
C
N
Z
V
C
Unsigned Conditional Brandt
Opcodeor
Base Code
101000
101400
103000
103400
BW
Jump and Subroutine
Opcodeor
Base Code
OOOlDD
004RDD
0OO20R
077Roo
Mnemonic
Description
JMP
JSR
RTS
Jump
Jump to subroutine
SOB
Return from subroutine
Subtract one and branch if not equal to
zero
1lap and Interrupt
Opcodeor
Base Code
104000 to
104377
104400 to
104777
000003
000004
000002
000006
Mnemonic
Description
N
Z
V
C
EMT
Emulator trap
*
*
*
*
TRAP
BPT
Trap
Breakpoint trap
Input/output trap
Return from interrupt
Return from interrupt
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
lOT
RTI
RTT
Comidential·and ·Ptoprietary
*
*
B-3
...
Preliminary .
Appendi:jlJ
Miseellaneous Program Control
Opcodeor
Base Code
Mnemonic
Description
0070DD
oo64NN
00023N
tCSM
tMARK
tSPL
Call to supervisor mode
Mark
Set priority level
Base Code
Mnemonic
Description
000000
000001
000005
000007
1066SS
0066SS
0065SS
1065SS
HAlT
WAIT
~aitforinterrupt
RESET
MFPT
tMTPD
tMTPI
tMFPD
tMFPI
Reset external bus .
Move processor type
Move to previous data space
Move to previous instruction space
Move from previous data space
Move from previous instruction space
N
Z
V
C
N
Z
V
C
Miscellaneous
Opcodeor
Halt
*
*
*
*
*
*
*
*
0
N
Z
V· C
0
0
0
• Condition Code Operators
Opcodeor
Base Code
Mnemonic
Description
000241
000242
000244
000250
000257
000261
000262
000264
000270
000277
000240
CLC
CLV
CLZ
CLN
CCC
SEC
SEV
SEZ
SEN
SCC
NOP
ClearC
Clear V
Clear Z
Clear N
Clear all CC bits
SetC
Set V
SetZ
SetN
Set all CC bits
No operation
B-4
CQn£idential and. Proprietary
0
0
0
0
0
0
0
O.
1
1
1
1
1
1
1
1
'the following electrical circuit configurations are useq in performing the. de tests. A definition of
the parameters
used in the tests is contained in Table C.l.
Current flow into the device is a negative value a;ndcurrent flow out ofthe device is
value.
.
. .
a pOsitive
High (H) assertion signals are true or asst;rted.fot high.level voltasesand false or negated for low·
level voltages. Low (L)assertion si~nalsare. true or· asserted for tmv"level voltages and false or
negated for high"level voltages.
.
Table C.I • de T~stSpeei&ation Parameters
V IH
High-level input voltage-An input voltagelevd withlnthe more positive (lessnegative)
of the two ranges of values used to represent the binary variables.
V1L
Low-level input voltage-An input voltage level within the less positive (more negative)
of the two ranges of values used to represent the binary variables.
1m
High-level input current-The current intQ an input when a high level voltage is applied
.
to that input.
IlL
Low-level input current--Thecurrent into an input when a low level voltage is applied to
that input.
VIC
Input clamp voltage-An input.';VGltage in a region of ~atively low differential resistance
that serves to limit the input·vbltage swin~. This,,parameter applies to TTL inputs that
have clamping diodes to ground that becOme forward biased for negative excursions of
the input voltage.
lIM
Input current at maximum input voltage-The current into an input when the maximum
input voltage is applied to t~at input. This parameter applies to TTL inputs.
VOR
High-level output voltage-The voltage at an output terminal with input conditions
applied that according to the specification will establish a high level at the output.
VOL
Low-level output voltage-The voltage at the output terminal with input conditions
applied that according to the specification will establish a low level at the output.
lot.
Low-level output current-The current into an output with input conditions applied that
according to the specification will establish a low level at the output.
los
Short circuit output current---:The current into 'an 0lltpdtwhen that output is shortcircuited to ground with mput conditions applied to establish the output logic level
farthest from ground potential. This parameter applies to TTL outputs.
lozL
Low-level output leakage current-The current from an output with a low level applied to
the output and with the input conditions applied so that the output is a high impedance.
ConfidentW and .Proprietary
___"'' _&¥t'' ' '........m"""................,_ _ _ _ _ _ _ _
• ..,fIIIil1IIll'' '._.___
= ___
.1Vt_'_h___
'~""_'
~,
C-l
___,___,__:
AppendixC
Preliminary
Symbol Name/Definition
10m
High-level output leakage current-":The current from an output with a high-level applied
to the output and with the input conditions applied so that the output is a high
impedance.
Icc
Positive power supply current-The current into the Vee input from the power supply. Vee
represents the positive power supply voltage applied to the device.
lEE
Negative power supply current-The current into theVEE supply terminal of the device.
represents the negative power supply voltage applied to the device.
VEE
e
Input capacitance-The capacitance measured at the specified pins with power applied to
the device.
R..
Real input impedance-The real portion of the input impedance measured at the
specified pins with power applied to the device.
in
VCC
(+)
IOH ..
OPEN
COLLECTOR OUTPUTS
INPuT CONDITIONS
V,H OR V,l AS
DICTATED BY THE
lOGIC
HloH
DCTESTCIRCUITCI
Vee
IN PUT CONDITIONS
V,H OR V,L AS
DICTATED BY LOGIC
GND
VOL
-
1
DC TEST CIRCUIT C2
(,-2
Confidential and Proprietary
+
T--
AppendkC
Vcc
Vcc
I
REMAI. NING {.
INPUTS
OP£1Ij
GND
DC TEST CIRCUIT C3
Vcc
IIORIIH - - - _
..
.OUTPUTISj
REMAINING
INPtITS
GND
00 TEST CIRCUIT C4
Vee
Vcc
0UTPUT(s1
OPEN
GND
DC TEST CIRCUIT C5
Confidential and Proprietary
C-3
-,
.. . . •. . . .
Pre"fD1It1a'rY
...
Vee
Vee
!
INPUT
CO.NDITIO
GND
OR
4.5 V AS. NS {
DICTATED BYTHf
LOGIC
•
(-)Ias
OND
DC TEST CIRCUIT C6
+
Vee
ICC
INPUTCONDITIONS {
. GNDOR 4.5VAS.
DICTATED BY THE
OUTPUT(S)
OPEN
lOGIC
GND
DC TEST CIRCUIT C7
VCC
Vec
INPUT CONDITIONS . {
GND OR 3.0 V AS
OICTiUED 6YTH/:
lOGIC
'OZl(+)
GND
1
T
DC TEST CIRCUIT C8
C-4
Confidential QJlICl Proprietary
AppendixC
Vee
Vee
INPUT CONDITIONS {
GND OR 3.0 V /IS
DICTATED BY THE
LOGIC
GND
DC TEST CIRCUIT C9
Confidential and Proprietary
C-5
Figure D.1 shows the waveforms and symbols used to measure the propagation delay for some
input and output voltages.
INPUT
OUTPUT VOLTAGE
IN PHASE
1.5 V
OUTPUT VOLTAGE
OUT OF PHASE .
Figure Dol • Input/Output Propagation Delay Symbols
Confidential and Proprietary
D-1
Figure E.lanQ E.2~P9W the configurations of the molded plastic{t:~C dgai-jnJipepaqg.ges.
Figure E.3. shOws the configw.-ation of the DCTll 40-pin ceramic package. TaWe ~.1nsts 'the pin
and package dimensions.
Figure EA sh0'-VS the dime~siCl~£or the DCJ1160-pin ceramic pa~!:~l}d figpJ;(:&,:?SPRiys the
dimensionsfor the FPJll 40-pin cerawc package.
;. '
.'
FigureE.6 sh<>w$the configuratiort.and dimensions of the cerquadili1ine~.
Figure E. 7 shOW$the configuratiQn <:If the pin grid array (PGA) p~ckage,and T~l~ E;2 U$ts'i:he
package dimensions.
Table E.t • MoidedUIP Package Dimensions
Package
r4'~pin
16..pin· "lH~pm'
20-pin
28.pin
4O.pin
Dimension Min. Max. Min. Max. Mcin. Max. Min. Max.l~· Mu';Min.·:M.,x..
A
0.28. 0.29.0.28 0.29.0,;l8 0.29 0.28 0.29 ;058 059 0.58 0.59·,
.,
--'
,.
-
:.
-'
.-,-
'.,'
,
"
,-
i7
-
-q:
.~
B
0.6050.7050.7050.8050.8050.9050.905 1.05 1.3051.405 1.9052:05
C
0.08 0.18 0.08 0.18 0.08 0.18 0.08 0.18 J>'08: (U&.O.08 0.18.
D
0.12
-
0 ..1;2
0,12
-
0.12
-
0;12
0.12
E
0.1 ± 0.01*
F
0.0140.0220.0140.0220.0.140.0220.0140.022 0.014 0.0~·O.014 0.022
G
0.015 0.06 0.015 0:06 0.015 0.06 0.015 0.06 0.015 0.06 0.015 0.06
H
0.044 0.07 0.044 0.07 0.044 0.07 0.044 0.07 0.0440.07 0.044 0.07
I
0.008 0.075 0.008 0.075 0.008 Q.D75.0iOO8 0.075 0.008 0.075 0.008 0.075
J
0.008 0.014 0.008 0.014 O.OO8·0~014 0.008 0.014 0.012 0.02 0.0120.02
}(
0.4
0.4
0.4
L
0.35
0.350.35'
0.4
0.7
0.7
0:35'
0,35'':':'"
0.35
*Non-cumulative at seating plane
Confidential·ancl Propl'ietary
E-l
14-PIN
IS-PIN
II:::::::~
~ ~I
-II-H
~"
IS-PIN
Figure.E.1 • 14·, 16·, 18- and 20-pin PhsticjCeramic DIP Configurations
E-2
Confidential and Proprietary
~
. . I.._ .. :/~"):. • .•. . . . . . . . '. . . "~.~ -1
. •.
TT
I.:. •
? •.. . . . •. . . •.
'1).
,.' . • . .
,.'
..,
,.0.
.
...
. . T --\'.,1- . ..'r-HF~
.
'
'
.
.
~".
',.,
J
I€::::::::::::::::J
,--II--
I·
c
e
-I
0
~
==
o
-y .' ..•...••............
Figure B.2 • 28- and 40-pin Plastic/Ceramic DIP Configurations
T~
21
A
1~1~~~~20
. r--,
'~'
±~l '7~~lP--i
~+ ~~" +~
K~Jt]
-----I
L ...
1----1..
Figure E.3 • DCT11 40-pin Ceramic DIP Configuration and Dimensions
f c - - - - - - - - - - 3 . 0 0 0 ± ·CI3O-----'--"-----3"in
-1 r-
_ . - - - - - - - .100. 29" 2.900 •.008 _ _ _ _ _ _ _--1
. 100
TOL NON ACCUM .
.1.008
I
~
I
I
I
I
/I I I I I
.018 ± .002 TVP.
Figure E.4 • DCJll 60-pin Ceramic DIP Configuration and Dimensions
E:.4
Confidential lind
Piopnetary
.211 MAX
1oo-_ _ _ _ _ _ L916
2.100
_-------1
PIN NO.
INOEXMAAK
v-m_u
_~
.
'
.
.
I
,.-_u
.•
u-~ u~ILr~
~.·t··.:E
. . I20'!
.
..L
. . .•.
"00
1.900
~.:;
Figure E.5 • FP]n 40-pi1l-Cemmic DIP Configurizaon amJ Dimensions
MINIMUM CLEAR
LEADFRAME ZONE
i~
f'~·"
I
Jri":
.180MAX
-I I- .030 MIN
Number of
Leads
Dimensions
A
B
C
D
44
0.6
0.02
0.05
0.825
68
0.9
0.02
0.05
1.125
84
1.1
0.02
0.05
1.325
132
0.9
0.012
0.025
1.125
164
1.1
0.012
0.025
1.325
Figure E. 6 • Cerquad Package Configuration and Dimensions
Cpnfidentialand Propri~
PreJiminaty
Table E.2 • Pin Grid Anay Package Dimensions
Type*
M,IE,F
A
B
C
D
,. Dimensions
F
E
G
72
1.17
1.0
0.1
0·,05
0.16
1.32
1.4
1.3
0.1
N/A N/A NfA N/A NtA N/A 0.18
132
1.4
1.3
0.12
0.05
1.3
0.12
N/A " N/A N{A N/A NtAt N/A :0.18
Pins
BC13
132 • '1.4
*Package Identification: '
0.12
0;1
On2
0.36
0.35
H
J
0.145 0.88
o.n
0.74
K
0.17
0.18
Type li =VAXBI bus BGAl and 'BIle chips
M= V-ll M chip
I/E = V-U I/E chip
F = V-ll F chip
Ben = VAXBI bus Bel3 chip
E-7
.'..',
Prel:-.:....:.A¥&&U1a&1'("
r··'"
A
1
1.1 MAX.
1
KEY PIN'
PIN AI'
INDICATOR
STANDOFF'
H ...
J
~
o
1
~
1
I
-£fl-
~~
~
F
STANDOFF
PINS
T
PADS'
;
r--'"
I..--.J....
---
I--E
PIN Al AND
PACKAGE IDENTIFICATION
(REFER TO TABLE E2)
lKey pin is nonelectrical and is for alignment on type I! chips only.
2Pin Al is indicated by a protrusion on the standoff collar.
'Standoff pins are positioned at the four exterior corners of the 132-pin PGA and at the four
interior corners of the 72-pin PGA.
·Capacitor pads not available on the I! and Bcn PGA versions.
Figure E. 7 • PGA Package Configuration and Dimensions
E-8
Confidential and,Proprietaty
i
'\_--!!@'!~~--~""""~~~---~~
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