Scanned Semiconductor_Handbook_V2_1987 Semiconductor Handbook V2 1987

User Manual: Pdf Semiconductor_Handbook_V2_1987

Open the PDF directly: View PDF .
Page Count: 320

Download
Open PDF In Browser	View PDF

1987

Semiconductor

Databook
Volume 2

USA
ISRAEL
SCOTLAND

Confidential and Proprietary

1

,
• Foreword
We at Semiconductor Operations (SCO) are committed to provide excellence in integrated circuit technologies, products, and services to support our customers, the Digital Systems Groups.
Our primary objective is to optimize Digital's competitive market position by developing leadership system performance at the lowest possible cost and :.vi thin the appropriate
time constraints.
The execution of programs designed to achieve this objective has resulted in the technologies
and products described in the 1987 Semiconductor Databook Volumes 1 and 2. While the basic
charter of SCO is to provide strategic and tactical management of all integrated circuit
requirements, the VLSI design and manufacturing function of SCO has become the focal point
for unique and complex circuits that have contributed significantly to the success of many new
Digital products. A strategic investment has been made in CMOS technology and in the design
tools necessary to take advantage of this technology. Increased circuit densities and performance have resulted, and capabilities have been extended from full-custom design for maximum
performance to semi-custom design for fast time-to-market application. CAD tools are
continually being developed to further enhance design and design methodology.
SCO is continually expanding its facilities to provide you with better service. While Hudson
and Andover, Massachusetts are the nucleus of the engineering and manufacturing operations,
supplemental design faciliti~s are available in Israel and Japan and additional manufacturing
capacity is being planned in Scotland. In addition, a new 6-inch wafer pilot fabrication line has
been approved for construction in Hudson to aid in the state-of-the-art development of the
advanced CMOS devices.
During the past yea!; many new integrated circuits have been developed and released. Although
some are application-specific, the circuits that are suitable for general use are described in
Volumes 1 and 2 of this databook. Volume 1 is a revision to the 1986 Databook and includes the
latest revis.ions and changes. Volume 2 contains information related to the new CMOS products
that have been recently developed for general use. We encourage you to become familiar with
these products and to use them in the design of Digital's systems products when possible. We are
ready to assist you in your design process and in support of your production needs.
Our ultimate goal is to ensure that DIgital's systems continue to maintain significant competitive advantage through the use of SCO services and products.

Confidential and Proprietary

.'

lV

Confidential and Proprietary

. Part Identification Codes
The following identification codes are used with the devices in this databook.
780 Series

78xyz - xx
0 = Processors
1 = Coprocessor
2 = Memories
3 = I/O devices
4 = Reserved

L

5 = Controllers
6 == Graphic devices
7 = Bus interfaces
8 = Communications devices
9 = Reserved

DC Series
DCxyz
i 0 = Custom bipolar devices
--1 = Custom bipolar devices

. xx
GA = Gullwing
f-oA = Straight
PA = Pin grid array

3 = MaS devices
5 = MaS devices

• Cross-referencing of Semiconductor Products
Part

Part

Purchase

Name

Number

Number

DC341
DC513
DC509
DC551
DC357
DC527
DC514

78034-GA
78134-GA
78135·GA
78332-GA
78588-PA
78711-GA

21-24674-01
21-26604·01
21-24673-01
21-24942-01
21-25091-01
21-25972-01
21-24674-01

Description

CVAX Central Processing Unit (CVAX CPU)
CVAX Floating-point Accelerator (CPPA)
CVAX Clock Generator (CCLOCK)
MicroVAX System Support Chip (SSC)
CVAX Memory Controller (CMCTL)
CVAX Q22-bus Interface Chip (CQBIC)
CMOS VAXBI Bus Interface Chip (CBIC)

Confidential and Proprietary

v

VI

Confidential and Proprietary

Contents

Section 1 • Microprocessor and Support Devices

CVAX 78034 32-bit Central Processing Unit ...................................... 1-1
CVAX 78134 Floating-point Accelerator ........................................ 1-91
CVAX 78135 Clock Generator ............................................... 1-109
MicroVAX 78332 System Support Chip ....................................... 1-123
Section 2 • Bus Support Devices

CVAX 78588 Memory Controller .............................................. 2-1
CVAX 78711 Q22-bus Interface Chip ......................................... .2-55
DC514 CMOS VAXBI Bus Interface Chip ..................................... .2-107
Appendix· Mechanical Specifications

Confidential and Proprietary

Vll

· Section i-Microprocessor and Support Devices
The CVAX 78034 microprocessor and support devices are the latest development in CMOS devices.
They provide the increased performance and the versatility required for the design of new and
faster VAX systems.
CVAX 78034 Central Processing Unit-The CVAX 78034 CPU is a low-cost high-performance, 32bit virtual memory microprocessor. It is implemented in double-metal CMOS and is functionally
compatible with the MicroVAX 78032 CPU. It contains a l-Kbyte cache memory and provides
pipeline architectures and instruction prefetch.
CVAX 78134 Floating-point Accelerator- The CVAX 78134 CFPA is a high-performance coprocessor
used with the CVAX 78034 CPU to accelerate the execution of floating-point instructions. It
eliminates the need to emulate floating-point operations in software.
CVAX 78135 Clock Generator-The CVAX 78135 CCLOCK generates the precision MaS dock
signals required by the CVAX 78034 CPU, CVAX 78134 CFPA, and up to two additional support
chips.
MicroVAX 78332 System Support Chip-The MicroVAX 78332 sse is a multifunction device that

provides the common functions necessary to support the MicroVAX 78032 and CVAX 78034 CPU.
It includes support logic for an external ROM, two asynchronous serial-line ports, programmable
address decoders, programmable timers, and a realtime dock.

• High performance
-32-bit internal and external data path
-1 Kbyte on-chip instruction/data cache
-Pipellned architecture
- Instruction prefetch
Optimized floating-point accelerator interface
• VAX instruction set
-304 instructions (59 emulated)
-21 address modes
-14 data types

• Sixteen 32-bit general purpose registers
• 22 interrupt levels
-15 software
-7 hardware

• Vectored software and hardware interrupts
• VAX memory management
-Full memory protection
-Fourptivilege modes
- Process andsystem space mapped

• 4 gigabyte virtual address space
• 1 gigabyte physical addres~ space
-512 megabyte memory space
- 512 megabyte I/O space
• Data parity checking
• Industry compatible external interface
• Single 5-volt power supply
• 84-pin surfacemollnt package

. Description
The CVAX 78034 Central Processing Unit (CVAX CPU) is a .32-bit, virtual memory microprocessor.
Implemented in a double-metal CMOS process, the CVAX CPU is a low-cost, high-performance
microprocessor for single-board computers, single-user workstations, low-end systems, and other
applications such as multiprocessing configurations. The CVAX CPU is functionally compatible
with the MicroVAX 78032 CPU and offers the system designer software compatibility, faster bus
cycle times, a l-KByte on-chip cache, and an optimized interface for the Cv:-\X 781.34 Floatingpoint Accelerator (CFPA). Figure 1 is a block diagram of the CVAX 78034 CPU.

Figure 1 • CVAX 78034 Microprocessor Block Diagram
Confidential and Proprietary

1-1

•. Pin and SignilDescriptiohs
This section provides a description of the input and output signals and power and ground
connections used by the CVAX 78034 cpu. The signal pin assignments are identified in Figure 2
and summarized in Table 1.

DAll'4

\ISS

voo
VDD

DA125
QAL2&
DAL27

0A~22

DAt20

DALIS

OALlG

~)Al '4

OAL12

PAllO

DAlOS

DAlOS

75

'.
'"
'.

I:lAL:lO
PAL31

VDD

51

vss

,.
50

so

"

..

OAi_Z8

OAL29

53

ill

..
83

DALO:>:
DAlO2
nALOl
DALOO

BMO
OMI

"
CVAX mOJ4 CPU

VDD·

vss

41

_ eMl
8M3
CSDPO

CroATS

eSP-PI

CI"OA1'4

CSDf'2

';POArJ

;~9

(PDlln

l8

OPE

YOS

CF'OATI
ePDA-TO

VOD

,35

CPSTAI

CPSTAO

CSD?)

"
"

IQ

mao

IRQl

IRQ:'!

PW'ii'FL

H:sr·"\ISS

vSS

ccn

OMR

ERR

As

me;
CU Input/Output Data/Address Lines-Time-multiplexed data and
address lines used to transfer address and data information between the CVAX cpu and memory, external
processor registers, CFPA, or I/O devices.

39-42

CSDP< 3:0 >

1-2

Input/Output Definition/Function

Input/Output Control Status and Data Parity-Time-multiplexed
lines used to transfer cydestatus information and data
parity.

Confidential and Proprietary

_.i·'
Signal

Pin

Prelimmary .
Input/Output. ·De£inruonjFuncdon

38

Input/Output Data Parity Enable-A signal used to enable parity
checking and to indicate valid parity information on
CSDP<3 i O>.

30

Input/Output Address Strobe-A strobe that indicates the initial
information on DAL<31:00> and CSDP<3:0> is
valid. Tht;leading e~e can he,use~tO,latch the
~l1£ormat,ion on the lines.
.

29

--------------------------~~~~---

DS

O\J.tput

43-46

BM<3:0>

Output

32

WR

Output

pata Stroqe-A stro~ ..that indicates to~he system
interface that DAL<31:00> and CSDP<3:0> are
ready to receive data during il CPU rt;'dd,external
processor register read, br interrupt ackhoWledge cycle.
his'deasserted to indicate that the data has been
received. 1ta180 contajn~valid omgoing;data during a
CPU write cycle or e:x:ternal processor register write
qrde. and is deasserted when the data is ready to be
removed,

13,y~eMasks-Spe~ify 'Nhich bytes of DAL data and
associated parity bits are valid during the second part of
an I/O cyde.
Write-S:pecifies the direction of data transfer on the

DAL
31

DEE

Output

Data Buffer Enable-Used with YilR to control exter,
nal DALtransceivers.

27

RDY

Input

Ready-Asserted by external logic to indicate thenarmal termination of the current bus cvcle.RDY and ERR
can be asserted together to reqti.~s{ atefiyl 6f the bus
cycle.

28

Input

Erro,r-Asserted by external logic to indicate the
abnormal termination of the current bus cycle. ERR
andRDY can be asserted'together to request a retry of
the bus cycle.

35

Input

Reset-Asserted by external logic to initialize the
CVAX CPUro a predetermined initial state.
Halt-AI19hmaskable~nterrupt used

19

to .transfer con·

trol to console macrocode.
14-11
18

IRQ<3:0>

Input

Interrupt Request-Four maskable interrupt request
lines for device interrupts.

Input

:row¢rhil~A maskaple interrupt. used to indicMe a
powerfail conciition ..

Confiden,tial and Proprietary

1·3

Preliminary
Pin

Signal

16

Input/Output Definition/Function

Input

Corrected Read Data-A maskable interrupt used to
signal an ECC correctable read error in a memory
subsystem.

15

INTTIM

Input

Interval Timer-A maskable interrupt used to provide
system timing information from the interval timer.

17

MEMERR

Input

Memory Error-A maskable interrupt used to indicate
a memory error.

26

DMR

Input

DMA Request-Asserted by external logic to request a
DMA cycle.

25

DMG

Output

DMA Grant-Asserted by the CVAX CPU to acknowledge a DMA request.

24

CCTL

Input

Cache Control-Used by external logic to control the
operation of the internal cache memory during DMA
and CPU read cycles.

3-8

CPDAT<5:0> Input/Output Coprocessor Data-Used to transfer opcode, control
information, condition code, and exception status
between the CVAX CPU and the CFPA.

9,10

CPSTA< 1:0> Input/Output Coprocessor Status-Used to transfer status information between the CVAX CPU and the CFPA.

1,21,36, Voo
53,76,77

Input

Voltage-5-volt power supply.

2,22,37, Vss
51,52,75

Input

Ground-Ground reference.

Input

Clock A and Clock B-Supply the basic clock timing to
the CVAX CPU. CLKA and CLKB are phase shifted by
180 degrees. These inputs are nominal 20-MHz, MOS
level, square-wave signals.

Output

Clear Write Buffer-Used to indicate that conditions
internal to the CPU require the external write buffer (if
included) to be cleared. This signal provides test information when the TEST input is asserted and its test
output is reserved for chip manufacturing test.

Input

Test/Vss-Reserved for chip manufacturing test. TEST
must be connected to V's when not in test mode.

34,33

CLKA,CLKB

----~----------------------

23

20

TESTIV~s

Data/Address
DatajAddress Lines (DAL < 31:00 > )- These are bidirectional time-multiplexed lines used to
transfer address, data, and interrupt information. The information on DAL < 31:00 > depends on
the type of bus cycle being executed. During the first part of a CPU read or CPU write cycle,
DAL<31:00> specify the length of the memory operand and DAL<29:02> contain the
longword address of the memory operand. DAL29 is used to distinguish a memory space address

1-4

Confidential and Proprietary

_2
from an I/O space address. DAL < Ol:OO>.are r~served. BM < 3:0> determine whkl1byte(s) of tb~
longword address are to be used. Refer to the Memory A,ccess Protocol section for additional
information. TheDALinformation is defined in Table 2;

18.ble 2 • CVAX 78034 pata~nd Address; Line Information
.Operand length

T~

OAL
31

30

0

0

DMAhexword

0

,Memory

0

1

longword

1

Iii) .

1

0

quadw{)tp ..

OAL
29'

DAL
«28:02> .

OAL

•Iongword ~ddress

reserved

1

Dudng the firsLpart of ~~in~riup~,~d4~9~le~gecycle.,

DAL!:;ess.or
Rrec~vein~qIDiq.g:ii1£or~a­
tion. During' the,sec()n\l".partof.~ ~,PI;r' wdre or.ext~rpWI'p~~$sOr r<;gi~ter wntecyCle.
DAL<: 31:00> arc used to transmit the data to be 'o/ritt~q.,.
. .
. '., .' .
.

or

Cycle StatUl/,and ~ta Pari~}' (CSPP :
and\~f)~ provides~~usinform~dQri~t:rhe
l;urren~
pUp cycle, as listed,-in _Tabk:
3,.
_ . _ ' _ . _ , };:,;
' ; , ,.,'
,
.'. - ! "
"
'i-,',. ',,"_'_', .. /,'./',.),:' .. '
',,'. __: ,. __ .',,;
"
C~I?,P3indicatt1s ~~eset intheintet~,als'!;che qlemory~hat~s .J:,~~.all()cate~duripga cachablf read
operati91}i1odjs .ul1qefine~t ~uringal.l~9th~r bU~1 cycks 'iC:i~~? isas~rted to Seecify se~ land
negated tpspecify setZ:' ..
. '. .. . '. . '
.
. .
.
..

ptlrins

"_~,,,,;-,

I

_,:,._",_;:~

I

Tabl~) .evAx 180)4 BusCyde'Status~'
Bus cycle type

H

L

H

H

L

H

L

H

H

H

L

H

H

H

H

demand D-stream read (no lock or modifyinteflt)

L.
L
L

L

exterflallP.R write
C:;Ju£idential and Proprietary

1-5

Bus'cyc1etyPe
"

L

H

L

H

H

'L

I-t

L

H

Write unlock'

L

H

H

L

reserved

L

H

H

H

write no unlock

L
L

'".'
"

'.

,

reserved for use by DMA devices

L

*H = high level, L = low level
During the second part of a bus cycle, CSDP < 3:0 > transfer byte parityinformationfor DAL line
data during a CPU read, CPU write, or external processor write cycle. Parity checking is not
performed during external processor register read cycles or during transfers between the CPU and
the optionaHloatirtg-point accelerator. Even parity is checkyd orgerlerared on even bytes, and odd
parityisc:;heckedorgenerated on odd bytes; During aCrfJreadc:;ycle, thecptJ reads and checks the
data parity on the bytes speCified by the BM< 3:0 > inform'ation. During aCPU write or external
p\:bcessor register write transactlc>u;the CPUgen~ratesdata parity for all bytes regardless of the
statebf BM< 3:0>~' TheDPEsignal specifies whert the CPU hto check or generate parity. It must
not be asserted during external processor register 'read dpenitionsor during transfers between the
CPU and the optional floating-point accelerator.
:

nita Parity Enable (DPE)-Thls hidirectionaf signal controls the checkingor generation of data
parity. During a CPU read cycle mintetrupt acknowledge Cycle, DPE i's asserted by exte~nallogic
}Viththe DAL datat~enable Parity checkingbytheCPUof the incoming data. During a CPU write
cycle .orexterrtal prciessor registetwrite cycle, the CPU assertsDPE to indicate that valid parity
irtformationis' on CSDP< 3:0 >. DPE must not be asserteClduringexternal processor tegisterread
transfers or transfers between the CPU and the optional floating-point acceler~1tor.DPE requh'eS~lD
external pullup resistor and must beassertedby an external interhcethat requires the CPU to check
parity.
"
,
Bus Control
A~dress Strobe (AS)-This bidirectional signal indicates that valid address information is on the
DAL lines. The CPU asserts AS to indicate that the acldress and control information on
DAL < 31:00> and CSDP < 3:0> is valid,. During a DMA transfer, the CPU uses the assertion of
AS by the DMA device to latch the DMA address. The CPUuses this address during a DMA cache
invalidate cycle.
Data Strobe (DS)-This signal pn;rvides timing lnfmmationJordata transfers. During a CPU read,
externalprocessor register read, ~r interrupt acknowledge bus cycle, the CPU asserts DS to indicate
that DAL< 31:00> and CSDP< 3:0> areavailable to receive incoming data and deasserts DS to
indicate that the incoming data has. been latch<;:d into thepPU. During. a CPU wrIte or external
processor register write cycle, the CPU asserts DS to indicate that DAL<31:00> and
CSDP < 3:0> ccrnt-)- These signals indicate which bytes of the DAL lines c.ontain valid data.
During a CPU read cycle, they indicate the bytes of data and associated parity bits that are to be
transferred onto the DAL and CSDP Iines.l)UI:ing a CPU write c:;ycle, they indicate the' bytes of the
DAL lines and CSDPlines that contain valid data and parity informatton. The BM < 3:0 > line
information is qualified by the assertion AS.

1-6

Confidential and Proprietary

-"

Wtit:eJWl}~Thi.s signal indic.ates the direction of data transfer

on theDAL bus tor the current
bus cycle. When asserted during a CPU bus cycle, the CPU 'wilItransfel' data oilto theDALJines.
Whend,eas~ert~ dwinga CPU bu~. cycle, the CPU will read df!,t a f I'~I1eiCVAX.CPtJ enters the
restart process with arestart code equal to2,and th't!F1AJ:l"signal! isa~sert~9,ftALT is edgesensitive, samplecieirery microcydc, and'ihterrtallysyncnroniied:
..
,C.
.
"i

, ",

.:" ": ,

" 1

Interrupt Ctmttol

: ,. ,~ , 1

: ,. , •

,

,

' . ,.

'.....

Interrupt Request (lRQ<3 :O»~Tl1esesignals ai1ow~X'terhallogicto transfer interl'upttequ~sts
to the CPU. The CPU responds to the assertion of one or more of these signals by executing an
interrupt acknowledge bus cycle for thehighest pendingIntertllpt Pri{)rityLeveI tl~t).TheIPL
associated with.each line iS'listed in Tabli:l4: !'fhe IRQ<3:0 ,>,sign!ilsare'lb!d-sen'SiiNeaiJ:8.tire
saillpled ;~el0' microcyde.
Thble 4 • CVAX 78034 Interrupt Request Line Assignments

InterruptPriotity

Level (~cUriaI)

IPL 17
,IPL 16;

IPL 15
IPL 14
Powerfai1 (PWRFL)- This signal allows external logic to notify the CVAX CPU of a P9\Ver,:.fai1v.xe.
When asserted, it results in the generation of an interrupt at.. ~P.L)E (hexadecimal). ·Jhe •. ~Py
responds to the interrupt by accessing System Control Block (SeE) vector OC (hexadecill1al): The,
CPU does not execute an interrupt acknowledge bus cycle when resjxmdingtothis' interrupt. This'
signal is edge-sensitive, sampled every microcycle, and internally synchronized by the:- C:PU.

95

Corrected ReaA I)a~ (C:ttD~7 This ~ign,~ a~ows. ~ternallQg~s to p.otifyt~" C;P 1.J ap£¢<;: errol: in
mern9ty, Asserting, fhis sigllW results in the geneta~ion of an ipterrupt at ~rL. lA. (hexadecimal).
The CPU responds to this interrupt by accessing SCB vector 54 (hexadeciwal); The CPU does not
1-7

~---.-------.----------.--------~---- .. ,-----~-.-.~-~~~--------------------"------~-------------'

Preliminary
execute an interruptacknowlttdge bus cyde when responding'to thisinterrapt. This signal is edgesensitivt':\sampled every mkrocyde, and internally synchrotiizedby the CPU.
Interval Timer (lNTIIM)-,- This sigrlal alIdws external logic tbsign~l an interval timer rollover to
the CPu. The assertion of this signal results in the generation of ali interrupt at 1FL 16
(hexadecimal). The CPU responds to this interrupt by accessing SCB vector CO (hexadecimal). The
CPU does not execute an interrupt acknowledge bus cycle whenrespondirig to thisintel:rtlPt. Iris
edge-sensitive, sampled every micro<-),cle, and internally synchronized by the CPU ..
Memory Error (MEMERR)-This signal allows external logic tbindicate1::o the Crbthata memory
error has been detected. The assertion of this signal results in the generation of an interruptal'IPL
ID (hexadecimal)_ The CPU responds to this interrupt by accessing SCB vector 60 (hexadecimal)
and does not execute an interrupt acknowledge bus cycle. MEMERR provides support' for the
implementation of a memory subsystem with multiple write buffers or delayed writetransfers.
When the cpu writes to this type of memory subsystem, the addr{iss and dlJ,ta are latchf-x:l and the
RDY signal is asserted. If an error occurs it is reported to the CPU when M.EMERR is asserted. It is
edge-sensitive, sampled every microcyde, and internally synchronized by the CPU,
Direct Memory Access Control
DMA Request (DMR)-This signal, allows external logic to request use of the DALand relat.ed
control signals for a DMA transfers or for other purposes. !tis a level-sensitive signal, sampl AS, DS, BM<3:0>,
DBE, DPE, CSDP< 3:0 >, and WR lines to a high-impedance state. When externallQgic deasserto;
DMR, the cpu responds by deasserting DMG and by starting the next bus cycle.
Cache Control
ClIche Control (CCTL)-The function of this signal depends on the type of bus cycle.
During a DMA cycle, the assertion of this signal by external logic initiates aconciitional cache
invalidate cycle. CC1'L is edge-sensitive, sampled every microcycie, and internally synchronized by
the CPU.
During a cpu read cycle, this signal is asserted to prevent the accessed data from being stored in the
internal cache memory of the CPU. CC1'L is level-sensitive andinust be asserted synchronously
,.
with the timing sampling point for the CPU read cycle.
Floating.point Accelerator Control
FPA Data (CPDAT < 5:0»- These bidirectional lines transfer opcodes, control information,
condition codes, and exception status information between theCVAX CPU and the CVAX FPA_ .
FPAStatus (CPSTA )_These bidirectional lines indicate the interpretation of the CPDA1'
< 5:0> line information to the CVAX CPU or CVAX FPA.
Power Supply
'.
Voltage (Vp~):-5-volt powersuppl)i
Ground (Vss)-Ground reference
'.'
. . . . .. '...'.'
. '..
'... ,. . '...... ". . "..' ...•.. ' •... "
Clock Timing
Clock A and Clock B (CLKA and CLKB).....:.These inputs supply ,the bask dock' tiffiin'g to'the cvAX'
CPU. The inp~ts arehorniriaIly 20 MHz and ~re MO$~levelsq{lil.re-WaV~ signaIs.CLKA is 'phase
shifted from CBKB by 180 degrees.
. . '
"
1-3

Confidential and Proprietary

Preliminary
Miscellaneous

Clear Write Buffer. (CWB)-This signal is asserted by. the CPU to indicate that internal conditions
of the CPU· require clearing of the external write buffer (if included). This signal provides test
information when the TEST input is asserted. It is reserved for manufacturing test. The CPU
asserts CWB
• At the start of an instruction or sequence that can chan.ge the processor state, These are CHMx,
REI, start of an interrupt,exceptiofior abort (including n+.iChme check, BPT, erc:), otentry to the
console (including HALT) .

• As a part of an instruction or sequencethatcanchangecontextsuch asend of LDPCTx or e~dof
SVPCTX.

.

...

- As a part of an instruction.. or sequence involv,ed in errorrecpverysuchas a write to tpeMAPEN,
CADR, or MSER registers.
Test (TEST)-Reserved for manufacturingtesLThis input provides the'groundfor the AS logic
and must be connected to V~sduril1g normal operation:

- Architecture Summary
The programming model for theCVAX 78C)34 architecture is shownin Figure 3. I:t isgrpupe9into
application programming (user) area and system programming area.
The sixteen general registers and Processor Status Word (PSW) are user accessible. The system
registers are privileged registers that are used by the 0lletatlng sYStem. These registers ate llsed for
context switching, memory management, clldle memory control, reporting of memory subsystem
.. .
'
.
status, exception and interrupt handling, ana processor control. . .,.
APPL.lCA TlO·\Js

PROGRAMMING

GENERAL REG:STERS

RO
,':"

,In'!

02

I

,....

AP

I:;

FP't

';'"

,

RJ

KSP

,A4

ESP

Rli

ssP

R£

W~P

...

R7

R8

..

R9

PC

,

~no

, t~ 11
SYSTEM

flR6tmAMMINd

PROCESS CONTROL REG1STERS

jNn RRUP'f,HEGISTEAS

PCBB

SISR

MEMPA-Y MANAGE.ME;NT REGISTERS;

POBR

POI.R
P1BR

P1Lfl.
SBR

SlR
MA?EN

I
I
I

M~MORYSYi;TI'M AEGISTERS

I

I

dADR'
MS"R

PHOCESSOR 5T AT US LO:.JGWOAt)

IIPll

PSW

Figure 3 -CVAX 78034 Programming Model
Confidential and Propr~etary

1·9

Preliminary;
General Registers
The (:VAX 78034 has sixteen 32-bit general registers that c~n be used .for temporary storage as

accum!Jlators, base registers;, and index registers. The registers used for specific functions are· the
Stack Pointer (SP), Argument PoiIlter.(AP), Frame Pointer (FP), and Program Counter (PC).
Stack Pointer (SP)-Five SP registers are included, one for each operating mode of the processor
and one for use by ~he .system when handling interrupts. The SP contains the address of the
p~cessQr. defined stack. The .stack pointer(s) used is determined by the oPerating mode of the
processor.
Argument Pointer (AP)- The VAX procedure call convention uses a data structure called an

argUment list. The AP register contains the address of the base of this structure.
Frame Pointer (FP)- The VAX procedure nUl convention builds a data structure on the stack called
a stack frame'. TheFP register contaiflsthe address of the base of thkstrutture.
Program CQunter (PC)- The PC register contains the address of the next byte of the program and

is Bat used as an accumulator, index, or temporary register.
Processor Status Word (PSW)- The PSW contains the condition codes and trap enable flags for
the CVAX 78034 CPU. The PSW is the user accessible portion of the proCcess()t statu;; !Qngword.

The lower 16 bits of the PSL contain the PSW. The format of the PSW is show~ in Figure 4 and
described lr1Tillile 5.
.
1$

1<

14

:

13

12

11

: ·M~Z

10

09

08

07

06

05

FU

IV

04

03

oi

01

00

V

c

I Dv'l ,I ITI I z I I
N

I

Figure 4 • CVAX 78034 Processor Status Word Format

Thble 5 • CVAX 78034 Processor Status

Word Description

Bit

Description

1.5:08

MBZ-Must be zero.

07 :04

Trap enable flags- These bits are used to enable traps to occur in special circumstances.
DV (Decimal overflow)-Used by macrocode'in the emulation of decimal instructions.
PU (Floating underflow)-When set, this bh cal!ses a floating underflow trap after an
instruction that produced a floating result too small in magnitude to be represented.
IV (Integer overflowl-When set, this bit .causes an integer overflow trap after an
instruction that produced an integer result that could not be correctly represented in the
space provided.
T (Trace)-When set, this bit catises a trace trap to occUr after execution of the next
instruction.

03:00

Condition Codes-These bits contain information related toth~ result of the last CPU
arithmetic or lqgical dpemtion. The bits are set as follows: . .•.
N = 1 if the result was negative.
Z = 1 if the result was zero.
V = 1 if the operationresuIted in an arithmedeoverflow.
C = 1 if the operand reslJltedin a carry oUf of6r borrow Into the most significant bit.

1-10

Confidential and Proprietary

...

Preliminary

Proc:ess Control Registers
The process control registers are used by the system to access the system control block and the
process control block.
System Control Block Base register (SCBB)-The SCBB register contains the base address of the
System Control Block (SCB). The SCB contains the vectors use(r-fbr servicing interrupts and
exceptions.
Process Control Block Base register (PCBB)- The PCBR contains the base address of the Process
Control Block (PCB). The PCB contains thehard\ttarecont6i:t'of the current process.
Memory Management Registers
These registers are used by the system to enable the internal memory man~ementunit of the
CVAX CPU and to access the page-table entries in memory used totranslflte virtual ftddressesinto
physical addresses.'t'he function of each 131 these regiSters' described in the Memory Management
section.

is

Interrupt Registers
These registers are used to control the interrupt system of the processor. They monitor interrupt
requests,. current interrupt priority level, and. the interruptstaok poirlt¢r.The funaiol:lof each of
these registers is described in the ExceptiorlS and Jl1tf:mtptsection.
Memory Sys.temRegiSWS
These registers are used to controltheopenttiom of the inte.rnalcache memol'yand to repor~ status
and errors for both thecftche memory. and the external memQrysubsystem,
Cache Disable Register (CADR)-The CADR controls the internal tache memory. This register
enables and disablesth its t:i!g and data.

ProcesSot Status tong\V~td (PSL)-The PSL contains process\'i;~hl,s information. The lower 16
bits are, the useraccessibleProcessqr Status Word (PSW):t&e up~r 16'bits areptLvileged and
accessed only by the system. The format of the PSL is shown in Figure 7 arid described in Table 8.
Refer to the Cache Memory section for a des~l,'iption ofthe P~W.

:f'SL

I'igure7' CVAX 780)4 ProceSSOr Status Lcmgword Fomiat

'18ble8' CVAX 18tl34P'totesSot
Suitti.ff.onp'ord
D~iption
,
.
.
.
-

Bit

DeSlo'riptiOJ;l

31

MBZ,:. :-Must be zero.

30

TP (Trace pending)-Forces a trace trap when set at the beginningo£ any inst~llctiOn. Set
by the processor if the T bit in thePSW is set at the beginning of an instruction,

29:28

MBZ-Must be zero.

27

FPD (First part done)"":':Setwhel1 ah exception or interrupt occurs during an instruction
that can be suspel1de~. If IiI?D is set whenJhe processOl:returnsfrom a:t;) exception or
interrupt, it resumes the interrupted operation from where it stopped ratber than
restarting the completeinstruc;tiqn.
,.' ( i
,,:. • "

26

IS (Interrupt stack)~Set when the prcx:essor isexetuting on the interruptstack. "

Confidential and Proprietary

1-13

Bit

Description

25;24", eUR MOD (Current rpode).......,-Indicates the acces,s mode )of ~he c~lrtently 'executing
process.

23:22

Bit
25

24

0
0
1
1

0
1
0
1

Mode

PRY MOD (Previous model-Loaded from CUR MOD bits 25:24 by exceptions and
Change.mode (eH~x) instructions. Cleared by interrupt$, afl9,re,st;oredby.Retl-lrn fTQm
. gxception or Intem~pt (REI) instruction,' . . .
. ""..' '
. ,.,. " . .
"

21:
20:16

15:00

Kernel
Executive
Supervisqr
,User

._-

.',

",

,"",

"

'

,

,"',

•

; ,

,

' , j

MBZ:""""Mustbe zero,
IPL (Interrupt Priority Leve1)-C~ntainsthe current processor p~i~rity in therange 0 to
IF (hexadecimal). The processor will accept interrupts only on k"Vels greater than the its
current IPL.
Processot Status Word-Contains processor status that isaccessibleby the user.

Implementation Specific Registers
The registers that are specific to the CVAX 78034 epu are the Interval Clock, Control and Status
(ICeS) register, Console Saved PSL (SAVPSL) register, and the Console Saved PC (SAVPC) register.
Interval Clock, Control, and Status Register (ICCS)-The Ices registel~ Figure 8, controls the
interval timer interrupt. It contains a read/write IE bit 06 that is used to enable or disable interval
timer interrupts gen,erfltedby the ~ssertion of the ~]\JT:rLM input..When thiiibi1iis set, the interval
timerinterrupts are enabled and the assertion of INTTIM results in an interrupt request at IPL 16
(hexadecimal). When this bit is dear, the int(~rval timer interrupts are disabled arid the assertion of
INTTIM does not generate an interrupt request. Bits 31:07 and05:00 are read as;z;eros and are
ignored during write operations.
31'

070605

I:::: ::: ::::: :::::::::: ::j~

00

1 ::: : :]

:rces

Figure 8- CVAX 78034 Interval Clock, Control,and Status'Regitter Format
Console Saved Registers (SAVPC and SAVPSL)-The SAvre and SAVPSL regIstetsrecord the value
of the PCarrdPSL when the eVAXCPU restarts: The SAVPC1-egister cOhtains the previous value of
the PCbefore thetestart operation. The SAVPC and SAVPSL register formats are shown in Figure 9.
The SAVPSL register contains the information described in Table 9.

1-14

Confidential apd Proprietary

Preliminary
31

00

I::::::::::StV:E~P~O~R:A~~O~NIE~ : : : : : : : ::: L

iSAVPC

Figure 9· CVAX 78034 Console $aved Register Formats

Table 9· CVAX 78034 Console Saved Processor Status Longword Register Description

Bit

Description

31:16

PSL (Processor Status Longword)-Contains the previous PSL value.

15

MAPEN (Map Enable)-Set to enable th~ map. '

14

Valid stack flag-Set to indicate a valid stack flag.

13:08

Restarttode-Contains the restart code (hexadecimal) as follows
Code' Dd'inition.

2
3

4
5

6
7
8

A
10
11
12

13
19

lA
IB
ID

IE
IF
07:00

HALT asserted
,initial power on
interrupt Stack not valid;duting exception
machine check normal exception
HM:'f instructloneiecuted in kern~llTIode
'... SeB vectQr bhs 01;00== U
SeE vector bits 01:00:= 10
CBMx executed while on interrupt stack
ACV or TNV during machine check exception
ACV or TNV during kernel stack not valid exception
machine check during machine check exception
machine check during kernel stack not valid exception"
PSL bits 26:24 = 101 during interrupt or exception
PSL bits 26:24:= 110 during interrupt or exception
PSL bits 26:24 = 111 during interrupt or exception
PSL bits 26:24"" 101 during REI
PSL bits 26:24 = 110 during REI
PSL bitd 26:24 = 111 during REI

PSW (Processor

'

Wordl-Contains the previous PSW value.

System IdentifiCation Register (SID)- The SID register is a read-only register that specifies the
processor type as a CVAX CPU and defines its microcode revision level. Figure 10 shows the register
format.

Confidential and Proprietary

1-15

Preliminary
31

CVAX780.34
0807

2423

00

Figure'1O. CVAX 78034 System Identification Register Format

. Data Types
The architecture of the CVAX 78034 supports the following data types: byte, word, longword,
quadword, character string, variable~length bit Held, and, rhrough the optional floating-point
accelerator, F_floating, D_floating, and G_floating. Figures il shows the integer, character string,
and field data types. Figure 12 shows the floating-point data types.

WORD

If

00

I ::::: :::: :: ::: : I

:A

LONGWORD

31

00

I:,: ::::: :::::::::::::: :: :::: :::: I
OUADWORD
31

:A

'00

I ': ~ ': ': ::': :': :': ':: :::': :': ': ':: '::: :::::': I

:A
:A+4

32

63

CHARACTER STRING

a
07

00

:A
:A+l

I
I

07

:00

I: :::::: I

:A+H

VARIABLE LENGTH BIT FIELD

P+S P+G-l

I

P P-l

FFFFFFFFFFFFFFFFFFFFFFFFf'FFFFI

5-1

00

I

:A

00

Figure 11 • C'V/lX 780J4 Integer, Character String, and Field Data Types

1-16

Confidential and Proprietary

mUlilID

07

s

CVAX780.34

Preliminary

I

00

06

I

EXPONENT

:A

FRACTION

FRACTION

:A+2

FRACTION

:A+4
:A+6

FRACTION
I

48

63'

15

14

07

06

00

16

31

15

s

04

14

I

EXPONENT

."

03

I

00
I

I

:A

FRACTION
;

FRACTION

:A+4

FRACTION

,
FRACTION
I

I

:A+6
I

I

48

63

Figure 12· CV/1X 78034 Floating-point Data 7:»pes

. Instruction Formats
The VAX instruction set has a variable-length instruction format that may be one byte or more
depending on the type of instruction. The general format of a VAX instruction is shown in Figure
13. Each instruction is made up of an operation code (apcade) followed by no operand or up to six
operand specifiers. The number and type of operand specifiers dependon theopcode.A}loperand
specifiers arc similar and consist of an address mode plus additi~ital information used to lo~ate the
operand.This additional information cQlltainO! up to two register designatorsandaddre.ssds, data,
or displacement values. The use of the operand is determined implicitly from the opcode and is the
operand type. It includes both the access type and the data type.

Confidential and ProprIetary

1-17

:mUIIIID

Preliminary.

CVAX78034

OPCODE (1 DR 2 BYTESI
OPERAND SPECIFIER 1

OPERAND SPECIFIER 2

OPERAND SPECIFIER 3

I
I
I
I
_h

h

-

OPERAND SPECIFIER 6

Figure 13· CVAX 78034 Instruction Format

Opcode Format
Each VAX instruction contains an opcade that specifies the desired operation to be performed. The
opcode may be one or two bytes depending on the contents of the byte at address A. The opcode is
two bytes if the value of the byte at address A is FD (hexadecimal). Figure 14 shows the apcade
format.

ONE BYTE OPCODE:

07

00

:

IA

TWO BYTE OPCODE:

Figure 14· CVAX 78034 Opcode Format

1·18

Confidential and Proprietary

Preliminary

CVAX78034

Operand Type
The operand type specifies the use of the operand associated with an instruction. Information
plpvided by the opcode includes the data type of each operand and its method of access; An
operand may be accessed as follows:
• Read-The specified operand is read-only.
• Write-The specified operand is write-only.
• Modify-The specified operand is read, mayor may not be modified, and is written.
• Address-Address calculation occurs until the actual address ofthe operand is obtained. In this
mode, the data type indicates the operand size to be used in the address calculation. The
specified operand is not accessed directly although the instruction may use the address to access
that operand.
• Variable bit field base address-If only R[n] is specified, the field is in general registe~R[n] ~~ in
R[n + IJ'R(nJ (i.e., R[n + 1] concatenated with R[n]). Otherwise, the address calculation OCcUrs
until the actual address of the operand i.sobtained. This address specifies the base to which the
field position (offset) is applied.
• Branch-No operand is accessed. The operand specifier is the branch displacement. In the
specifier, the data type indicates the size of the branch displacement .

• Addressing MOdes
A summary of the addressing modes used by the CVAX 78034 is listed in Table 10. Abdef
description of each mode follows.
Table 10· CVAX 78034 Summary of Addressing Modes
General Register Addressing Mode
Hexadecimal

0-3
4
5
6
7
8
9

A
B
C

D
E
f

Name

Assembler

literal
index
register
register deferred
l\lltodecrement
autoincrement
£lutOincrement
deferred·
bytt' displacc.ment
. byte displacement
deferred
wCll,:1 displacement
word displacement
deferred
longword displacement

longi.vord displacement
deferred

t

Access
m w a

"

S' #litt'nd

v

j

(Rx)
Rn

v

fRn)

y £ y
y y y v y
y v v y y

-(Rnl

y

v y

v
v

y

y

y

Wd(Rn)
y v
@Wd(Rni y. y

(Rn)+

@(Rl1l

y
y

\YJ' c\(Rn) v
@\YJ'dCRnJ y

L'd(Rn)
v
@L'd(Rn) ~'

y

v
v

y

y y

y
v

y

y

v

,Y

~,r

y

y
Y
Y

\'

Y

\'

V

l,l.

uq

ll.

Y

u

y

y~--.-~-

f

y

ux

y

v

SP Indexahle?

y

y
v

\'

PC

:v;;

p

y

:'y

P
p

,.'J'

y

v

y

P

y

Y

P

v

y

.

--.'-.--'---'-~-----

ConfidentialllndProprietary

1-19

,

. .10

Preliminary

CVAX78034

Program Counter Addressing Mode
Hexadecimal

Name

Assembler r

Access
m w a

v

8
9

immcdi,ltc
absolute
byte relative
b\,te relative deferred
word relmive
word relative deferred
longword relative
longword relative
deferred

r #constant

u

II

\'

V

\'

\'

V

V

A
B
C
D

E
F

\'
@#address v
g' address y
@B' addressy
\X'; address y
Wf' address y
L' address \'
LA address \'

Indexable?
u
y
Y

v

v

\'

V

v

y

v

y

y

\'

Y
v

\'

y

Y
v

y

y

V

Y

Y

y
y
y

Y
Y

Y

Y
Y

Addressing Legend
Access:
r

= read

m

=

modify
w "" write,
a = address
v "" field

Syntax:

= any indexable address mode
d = displacement
Rn "" general register. n 0 to 15
Rx = general register, x 0 to 14

Results:
y = yes, always valid address mode
f = reserved address mode fault
- = logically impossible
p "" program counter addressing
u = unpredictable
uq = unpredictable for quad, D_iG ..Jloating, or field ii pas + size> 32
ux = unpredictable if index reg = base reg

General Register Address Modes
The general register address modes use one or more general registers, depending on the instruction
and data type, to contain the operand(s) or information required to locate the operand(s) to be used
by the specified instruction,
Register Mode-The operand is contained in one of the general registers tRn).
Register Deferred Mode-Register Rn contains the address of the operand.
Autoincrement Mode-Register Rn contains the address of the ,operand,
After the operand address is determined, the size of the operand in bytes (determined by its data
type) is added to the contents of Rn and the result is placed in Rn.
Autoincrement Deferred Mode-Register Rn contains a longword address that is a pointer to the
operand address, After the operand address has been determined, the value of four is added to the
contents of Rn and the contents of Rn are replaced by the result.
Autodecrement Mode-The size of the operand in bytes (determined by its data type) is subtracted
from the contents of Rn and the contents of Rn are replaced by the result. The updated contents of
Rn are the address of the operand.

1·20

Confidential and Proprietary

Preliminary ·
Literal Mode-Literal mode addressing provides an efficient means of spedfyinginteg~:£9nst~~S
in the range from 0 to 63 (decimal). In addition to short integer literals, this mode can be used. to
specify floating-point liqirals.The value is contained in the operand specifier.
Displacement Mode-:thedisplacement contained, in the oper~~d specifier" after,
signextended to 32 bits if it is a byte or word, is added to the contents of register Rn. The'~sultisi:he
operand address.
'
, '"

Qjflg,

Displacement Deferred Mode-The displacement contained in the operand specifier, aftef b~ing
sign-extended to,.32 bits if it is a byte or word, is added to the contents of register Rn. The,reslJit \S
the longword address of the operand address.
, , '
,
Index Mode-The operand specifier consists ofa minimutJ? oftwo bytes, a primary ()perand
specifier, and a base operand specifier. The primary operand specifier contained inbitsO.through 7
includes the index register (Rx) and a mode specifier of 4. The address of the primary opt;rand is
determined by multiplying the contents of index register Rx by the size of the primary operan<;l in
bytes as determined by operand type. This value is then added to theaddr~$s specified1w the base
operand specifier (bits 15:08) and the result is used as the p~i~ary operandal:!dre~s,

Program Counter Addressing
Register 15 is used as the Program Counter (PC). hcan also be used as a register in addressing
modes. The processor increments the program counter as the opcode, opt~rand specifier, and
immediate data or addresses of the instruction are evaluated. The incremented '.I:alue is determined
by the opcode, number of operand specifiers, etc. The PC can be used with
VAX addressing
modes except regi~ter, index, register deferred, or autodecrement.
;

JII

Immediate mode- This mode is autoincrement mode when the PC is used as the general register.
The contents of the location following the addressing mode are immediate data~

Absolute mode-This mode is autoincrement deferred using the PC as the general register. Thf
contents of the location following the addressing mode are used ast;he oper;m~ address. This is
i!1~erpreted as an absolute address (an address that remains constant regard1e~s of the location
memory where the assembled instruction is executed)"
. . ',,1,
~lative mode-This mode is displacement mode with the PC used as~he,ge~taI register, The
diSplacement that follows the operand specifier is added to the contents of the Pc"and the result is
the address of the operand.

Relative deferred mode-This mode is similar to relative mode except that the displacement that
follows the addressing mode is added to the contents of the,PC; ,and.theresu!.t~s/thelong:urord
address ofthe operand.
Branch Addressing

fe', •

During branch displacement addressing, the byte or word displacement is sign.e~~~~?,tp 32 bits
and added to the updated content of the PC. The updated content of the,PCis,tij:~~ss of the
first byte beyond the operand specifier.

Confidential and Proprietary

Preliminary
. Instruction Set
This section provides a sIJromary ~ the VAX ins.tructions implemented':}:>y theCYAX''780)4, the
floatinif-point instructions supported by ~he floatil1~-point accelerator, a~"d t?{!.!rniW~~ed inst.f\1ctions that are assisted by the microcode of the, CVAX78034, The standartl notation uSt;9 for the
operand specifiers is
.
.'
' . ' ';L
  
1.

.,

.

Narile~Asuggestive name felt' the operand in the context ofthc illstruction.'It}s thecapitaliz~a
name of a register or block for implied operands.
.
..!

2 .. Access type--' A letter denoting the operimd spe~ifle~~ccess type.

a = address operand
. hranchdisplacement

In=modified~perahd (bothr~ad and written)
r"" read
opef!lnd
.
v = if not "Rn;' iame as address operand, otherwise R[n + l),R[n]
w = write omy operand

omy

3. Dat~ type-A letter denoting the data. type of the operand .

. b=byte

.

d=D.,..Jloating

f,= F_floating
g == G_floa.ting
l=longword
q~quadword

v = field (used only inimplied operands)
w'"=word
* ." multiple longWords (used only in implied operands)
4. Implied operahds-:I:'ocations that ~re accessecl by the instru~tion, but not specified in
operand, are denoted by braces { }. The abbreviations for condition codes are
,; =ccmditiollally s e t / c l e a r e d ·
. .
.- = not affected
O=cleared
1 = set
The· abbreviations forex"Ceptions' are
rsv"" reserved operand fault
lov = integer overflow trap
idvz = integer divide by zero trap
fov = flO'atingoverflow fault
tuv ""floating underflow fault
fdvz = floating divide by zero fault
dov = decimal overflow trap
ddvz = decimal divide by zero trap
sub = subscript range trap
prv = privileged instruction fault
Opcade values are given in hexadecimal.

1-22

Confidential and Proprietary

Preliminary

CVAX1S0.34

• Integer Arithmetic and Logical Instructions
OP Mnemonic and Arguments

Description

N Z V C Extepdons

1\1.11.1 aligned word interlocked

~'~

~.(

"

1(

"

~'r

t,

."

"

i,

~\t

"

,,;-'r

*

"

.';;

~.,

~':

,',

t,

"J:

.,'.

"

.~

~'":

Arithmetic shift left
j\rithmetic .shift quad

t.

~.!

* 0

~'r

~,,:

~~

Bit clear byte 2-operand
Bit clearlong 2·operand
Bit dear word 2·opemnd

* * 0
0
*
~r

'k

0

8B BICB3 maskrb, src.rb, dst.wb
CB BlCD mask.rl, src.rI, dst.ml
AB BlCW3 mask.rw. src.rw, dst.mw

Bit clear byte 3-operand
Bit dear long .'I-operand
Bit clear word 3-operand

*

,';:

0 0 0 -

88 BISB2 mask.rb, dst.mb
C8 B1S12 mask.rt dSLml
AS BISW2 mask.fw, dst.mw

Bit set byte2-operand
Bit set long2-operand
Bit'set word 2-operand

89 BISB3 mask.rb, src.rb, dst.mb
C9 BISL3 mask.rl, src.d, dSLml
A9 BISW.3 mask.rw, sre,tw, dst.mw

Bit set byte 3-operand
Bit set long3-operand
Bit set word 3-operand

9.3 BITB mask,rb, src.rb
D3 BITL mask.rl, src.rl

58

ADAW 1 add.rw, sum.mw

80 ADDB2 add.rb, sum.mb
CO ADDL2 add.rl, sum.ml
AO ADDW2 add.rw, sum.mw

Add byte2-operand
Add long 2-operand
Add word 2-operand

81 ADDB3 add1.rb, add2.rb, sum.wb
C1 ADDU addl.rl, add2.rl, sum. wI
Al ADbw3 add1.rw, add2.rw, sum.ww

Add byte .3-operand
Add long 3,operand
Add word}-operand

D8 AD\"QC add.rl, sum.m1

78
79

with carry

ASHL ent.rb src.d, dst.wl
ASHQ cnt.rb src.rq, dst.wq

sA BICB2 mask.rb, dSLmb
CA BICL2 mask.fl, dst.m1
AA BICW2 mask.rw, dst.mw

B3

BITW mask.rw, src.tw

Bit test byte
Bit test long
Bit test word

94
D4
7C
B4

CLRBdst.wb
CLRLdst.wl
CLRQdst.wq
CLRWdst.ww

Clear byte
Clear long
Clear quad
Clear word

91 CMPB src1.rb, src2.rb
Dl CMPL src 1. 1'1. src2.r1
Bl CMpW sre1.rw, src2.rw
98
99

F6
F7
33
32

CVTBL src.rb, dst.wl
CVTBW stc.rb, dst. wI
CVTLB sre.rI. dst.wb
CVTLW src.rl, dst.ww
CVTWB stC.tw, dst.wb
CVTWL sre.rw, clst.w!

97 DECBdif.mb
D7 DECLdif.!
97 DECW dif.mw

86 DIVB2 divr.rb, quo.mb
C6 DIVL2 divul, quo,1l11
A6 DIVW2 divr.rw, quo.mw

Compare byte
Compare long
Compru.-e word
Convert byte to long
Convert byte to word
Convert long to byte
Convert long to word
Convert word to byte
Convert word to long

lOV

iov
IOV

-;,

iov

;,

.'>

iov

i,

"

IOV

* iov
~~

IOV

lOV

0 iov

~',

~'(

"

t,
;,

"

~~

-~f

,'~

~':

*

0
0
0

" * 0
" '.' 0
*' * 0
'if

Ie

..;;:

"

-

0

* 0
,', 0

0 1 lJ
0
0
0
0 0
0 ~

"*

"

'*;,

,'t

.'~

0

~':

~'.:

0 *

,':

" 0 0
\':
0 0

oJ:

"

~'r

"k

*

~'~

~',

-;~

~'r

t,

"

0 0

.,:

0 iov
0 iov
()

IOV

Decrement byte
Decrement long
Decrement word

.j;

'if

*

"

~'.

*

~'(

* iov

i':

;/{

Divide byte 2-openmd
Divide long 2-operand
Divide word 2-operand

'1:

"

* 0 iov, idvz

'k

"1:

1,

,':

<-

0:,

Confidential and Proprietary

",.

'.'

iov
iov

0 JOY, idvz
0 iov, idvz

1-23

OP Mnemonic and Arguments

Description

87 D1VB3divl'.rb, divd.rL, quo.wb
C7 DIVL3 din.r!' divd.rl, quo.wI
A7 DIVW3 divr.rw, divd.fW, quo.ww

Divide byte 3-openmd

Divide IOl1g 3-operand
Divide word 3-aperand

7B EDlV divr.!'!, divd.rq, quo.wl, rem.wI
7 A EMUL mulr.rl,muld.r1, add.rl, prod.wq

.r:~x:[em]eo

96

Increment byte

INCH sum.mh
D6 INCL sum.ml
B6 INCW sum.lllw

multiply

Inerelnetit word
Move complemented byte
Move complemented long

8E MNEGB sre.rb, dst.wb
CE MNEGLsre.rl,dst.wl
AE MNEG\'C sre.rw, dsLww

o

Extended divide

I nercment long

92 MCOMB sre.rh, dst.wb
D2 MCOML ol'e.rl, dst. wI
B2 MeOM\1\' src.1'W, dst.ww

" ·>1·"',O,iev;ldvz·
',', >1 '" U iov, idvz
" ,. '* 0 iov, idvz

.. .

* *
* * "
* 0
'1:

;,
;,

~'.

0

Move cOl'rl:plemenred word
Mlwe negated byte
.Move negated long
M(JVe negated word

',i

_"k

()

"/,

'.':

~lr

l'<

;,

"

"

..

;,

"
" *

Move byte

" " 0

Move Jong

'k

Move word

" " 0 -

9A r>IOVZBW src.rb, dst.wb

Move~ro:~xte~ded byte to ~ord

9B MOVZBL src.rb, dst.wl

Move zero-extended byte to long
Move zero-extended word to long

o o o ;, o o * 0-

Multiply long 2-operand

IS,

Multiply byte 3-operand

MULB,

10V

10v
iov

0.'

l~

0

10V

joy

Multiply word 2-operand

muld.rb, prod,mb

C5 MULU mulr.rl,muld.rl, prod.ml
A5 MUL\\I.3 mult.fw, muld.fw, prod.mw

Multiply long 3-operand
Multiply word 3-operand

o

iov'

----------~~----------------~----~~~~--.~,'~

Push long

DD PUSHL
9C ROTL cnub, sre.rl, dst. wI

Rotate long

D9 SBWC sub.d, dif.ml

Subtract with carry

82 SlIBB2 sub.l'b, diLmh
C2 SUBL2 sub.rl, dif.ml
1\2 SUBW2 sub.rw, diLmw

Sub~ract long

83 SUBB 3 sub. rb, min. rh, dif.mb
C.3 SUBUsub.rI, min.rl, diLrnl
A3 SUBW3 sub.fw, minsw, diLmw

Subtract byte 3-operand
Subtract long3-operand
Subtract word 3-operand

95 TSTB src.rb
D5 T51'L src.rI
B5 TSTW sruw

Test byte
Test long
Test word

8C XORB2 mask.l'b, dst.mb
CC XORL2 mask.rl, dst.ml
AC XORW2 mask.fw, dst.mw

Exclusive or byte
Exclusive or long 2·operand
Exclusive or word 2·operand

8D XORB3 m,lsk.rb,stC.rb,
CD XORL-"i mask-d, src.rl, dst.wl
AD XORW.3mask.rw, Sl'c.rw, dst.ww

r:.x<:m'5!VC or
Exclusive or long -"i-operand
Exclusive or word 3-operand

1-24

'"

" *

Multiply

84 MULB2 mulr.rb, prod.rnb
C4 NlULL2 multrl, prod.ml
A4 MULW2 mulr.fw, pi'od.mw

iov
iov

~Ir

90 MOVB sre.rb, dst.wb
DO MOVL sterL dsuvl
BO MOV\\/ src.tw, dst.ww

3C MOVZWL srtrw, dSLWW

(oY, idvz.·

" * 0

Snbttact byte 2-operand

2-operand
word 2.opernnd

Confidenti"l and Proprietary .

" * 0

CVAX. l1S014

Preliminary

-Address Instructions
OP Mnemonic and Arguments

N Z VC Exceptions

Description

Move address of byte
.. " Move address of long
Move \'Iddress of quad
M~ve, addry:~ of word

9E
DE
7E
3E

MOVAB src.ab, dst.wl
MOVAL{ =F} src.al, dst.wl
MOVAQ {=D=G} src.aq, dst.wl
MOVAW src.aw, dst.w!

9F
DF
7F
3F

PlJSHAB src.ab, {-(SP).wl}
PUSHAL { = F} src.aI, {-(SP).wl}
PUSHAQ {.=D=G} src.aq, {-(SP).wl}
PUSHAW src.aw, {-(SP).wI}

" '" 0 0
* I, 0
'"
I,
0

* *

Push ~dre$s of byte
Push address of long
Push address of quad
Pu~h address of word

" .. 0 " * 0

* " 0 -

,. *

0

~

. Variable-length Bit Field Instructions
.. N Z V C It~ptions

OP Mnemonic and Arguments

Description

EC CMPV pes.rl, size.rb, base.rb,
{field.rv}, src.r!

Compare field

* * '0 * rsv

ED CMPZV
size.rb, base.vb,
{field.rv , src.rl

Cotppare zero-e)(tended field

**O*rsv

EE EXTV pos.r!, size.rb, base.vb,
{field.rv}, dst. wI

Extract field

* * 0 - rsv

EF EXTZV pes.d, size.rb, base. vb,
{field.!v}, dst. wI

Extract ze~~7e"teodedJit.'!ld

rs.rl,

FO

INSV src.rl, pos.r!, size.rb,
baseevb, {field.wv}
.

EB FFC startpos.rl size.rb, base.vb,
{field.rv}, findpos. wi

,,,

* * o -

rs",

-

rsv

~

Insertfield
Find first dear bit

EA FFS starTos.r1, size.rb, base. vb,
{field.rv ,findpos.w!

o -

. Control Instructions
OP Mnemonic and Arguments

Description

9D ACBB Iimit.rb, add.rb,
index.mb, dispLbw

Add compare and branch byte

'*

i~

* *

PI ACBL limiLd, add.rl, index.mI,
dispI.bw
3D ACBW limit-tw, add.tw,
index.mw, disptbw

Add compare and brapchlong

-

icv

Add compare and branch word

-

iov

F3

AOBLEQ.limit.rJ, index.ml,
displ.bb

Add one and branch on less' or equal

F2

AOBLSS limit-rI, index.ml,
dispI.bb

Add one and branch on less

ConfideFltial and Pmprietary

iov
~:

* * - iov

1-25

----------_._--_.__.-._-_._-_ ..- _----_._._._----_.-----------_._----_._---_.._._--_
....

... _-----_._.

OP Mnemonic and Arguments

Description

1E BCe{ =BGEQU} displ.bb

Branch on carry clear
Branch on.qtrry set
Branchon equal
Branch on greater or equal
Branch on greater
Branch on greater unsigned
Branch on less or equal
Branch on less or equal unsigned
Branch on less
Branch 011 not equal
Branch on overflow clear
Branch on overflow set

IF BeS{ = BLSSU} displ. bb
13 BEQL{ =BEQLU} displ.bb
18 BGEQ dispLbb

14

BGTR displ.bb
lA BGTRlJ dispJ.bb
1.5 BLEQdispl.bb
113 BLEQU displ.bb
19 BLSS disp1.bb
12 BNEQ {=BNEQU} displ.bb
lC Eve displ.bb
1D BVS displ. bb

E1
EO
E5
E3
E4
E2

BBC paul, base. vb, displ.bb,
{field.rv}
BBS poul, base.vb, dispLbb,
{field.rv} .
BBC(: pos.rl,base.vb, dispJ.bb,
{field.my}
BBes pos.rl,'base.vb, displ.bb,
{field.mv}
BESC pos.rl,. base.vb, displ.bb,
{field.my}
BBSS pos.rl, base. vb, displ.bb,
{field.mv}

Branch on bit. cleal'
Branch on bit set

-

1'5\"

Branch 011 bit clear and clear

-

rsv"

Branch on bit clcar and sct

-. rsv

Branch on bit set and clear

-

-

rsv

Branch 011 bit set and set

-

rsv

;Branth onblt deal' and clear interlocked

-

fSV

Branch on bit set'andsetinterlocked

-

rsv

E7

BBCCI pos.rI, base. vb, dislp.bb,
{field.my}
£6 BBSSI pos.r!, base. vb, dislp.bb,
{ field.mv}

E9 BLBC sre.rI, dispLbb
E8 BLBS src.r1,displ.bb

Branch on low
clear
Branch on low bit set·

11
31

BRB disp1.bb
BRW displ.bw

Branch with byte displacement
Branch with word

10

BSBB disp1.bb {-(SP).wl}

30

BSBW displ.bw HSP).wl}

Branch to subroutine with byte
displacement
Branch to subroutine with word
displacement

8F CASEB selectoKl'b; base.rb,

,',

" ;, 0 *

Ca~elong

* " 0 "

Case word

17

Jump

]MP dst.ab

\1

Case byte

limit.rb, disp!. bw-list
CF CASEL selector.rI, base.rI,
limit.rl, dispJ.bw-list
AF CASEW selectouw, base.rw,
limit.rw, displ.bw-list

16 ]SB dst.ab, HSP).wl}

Jump to subroutine

05

RSB {(SP)+.rl}

Return from subroutine

F4

SOBGEQ index.ml, displ.bb

Subtract one and branch on greater
or equal'

"i:

Subtract one and branch on greater

"

F5

SOBGTR index.ml, displ.bb

----

-------------------------

1-26

Confidential and.I:lroprietary

~':

* -;,

-

IOV
IOV

'. Var~~Rle.l~ngthllit Field Instructions
OP Mnemonic and Arguments

Description

N Z V. C .:Ex~ptions

EC CMPV pos.r!, size.rb, base.rb,
{field. tv }, src.rl

Compare field

* * o * rsv

ED CMPZV rs.rl, size.rb, base. vb,
{field.rv ,src.rl

Compare zero-e.xtended field

EE ExTV pos.rI, size.rb, base.vb,
{field. tv}, dst. wI

Extract field

EF EXIZV pos.rl, size.rb, base.vb,
{field. tv}, dst. wl

Extract . zero-extendeg #~d

FO

INSV sre.rI, pos.rl, size.rb,
base.vb, {field.wv}

r,sv

I psert. Held

EB FFC startpos.rl size.rb, base. vb,
{field.rv}, findpos. wI

EA

O. -

Find first dea!'bit

i

FFS startpos.rl, size.rb, base.vb,
{ field. rv}, findpos_ wI

. Control Instructions
OP Mnemonic and Arguments

9D ACBE limit.tb, add.rb,
index.mb, disp1.bw

Fl ACBL limit.rI, add.rl, index.ml,
disp!. bw
3D ACB\X' Iimit.rw, add.rw,
index.mw, displ.bw
F3

Add compare and branch byte
Add compare and branch l~ng
Add compare and b!"anch. word

AOBLEQ limit.rl, index.ml,

displ.bb

"" .iov

Add one and branch

on. less .or equal

-

iov

F2 AOBLS5 limit.d, index.ml,
displ.bb
IE
IF
13
18
14
IA
15
lB

Bee{ =EGEQU} displ.bb

BCS{ =BLSSU} displ.bb
BEQL{ = BEQLU} displ.bb
BGEQ displ.bb
BGIR dispJ.bb
BGTRU displ.bb
BLEQ displ.bb
BLEQU displ.bb
1<) BLSS displ. bb .
12 BNEQ { "" BNEQU} dispLBb
1C Bve displ. bb
1D BVS d.ispl.bb

Addope and branch on less
Brarioo on carry dear,
Branch on carry set
Brrulchqn eq\.lal
Bmnch on greateroreguaJ
Branch on greater
Branch on greater unsigned
Branch on less or equal
Branch 011 !es$ or equal unsigJicd
Branch ptlleks' "
. Braru:h on noteq~al
Br":

",':

0 "

Case long

*

;,

0

Case word

* * 0 *

17 JMPdst.ab

Jump

16 ]SBdst.ab, {-(SP).wl}

Jump to subroutine

~'~

05

RSB {(SP) + ,r!}

Return from subroutine

F4

SOBGEQ index.mI, displ.bb

Subtract one and branch on greater
or equal

-

iov

Subtract one and branch on greater

-

iov

F5

SOBGTR index.ml, displ.bb

• Procedure Call Instructions
I

OP Mnemonic and Arguments

Description

N Z V C E)(ceptions

f-A CALLG arglist.ab, dst.ab, {-(SP).w'}

Call with general argument list

0 0 0 0 rsv

FB

CALLS numarg.r1, dst.ab, {-(SP).w}

Call with argument list on stack

0 0 0 0 rsv

04

RET {(SP)+.r}

Return from procedure

-.',

1-28

Confidential and Proprietary

'h

*

-k

rsv

· Miscellaneous Instructions

, Bitdear processor status word

.. Bit set processor status word

B8 BISPSWmask:fv:'

----Break. ppiut £~ult

----'--~

;.-

HKSP).w'}

0.3

BPT

00

HALT HKSP).w'}

,--'---

.

rsv

--.-

~-,

0 o. 0,. {}

Halt (kernel rnode only) .

"~---

.; -. prY

OA' INDEX.sllbscript.rl, low.r!, high.rI,
size.d, indexin.rl, indexout.wl

DC
01

NOP

BA

BB

FC

· Queue Instructions
OP Mnemonic and Arguments

Description

5C INSQHI entry. lib header.aq

Insert at

SD INSQrI entry.abbeader.aq' 'Insert at~:ilofqu~tie',:jlltb:loCk.ed " 0 "O*rsv'
~--..-,..~-,-------~-.,.,..,.----:-:-.,.,...~-+,.

.---~.,-,-~

OE INSQOEentry.ab, pred.~b

Il1~ert!nt~q~i~l,e"
________

5E REMQHI header.aq, addr. wI

Remove from head of queue, mterl,xt;e"

5F

ad dr. w[

~,...;.-..,.-~

'f' "0 ;,

,--c_'_'_'

~_,""-~"'-C-.~ _ _
' ~..:z~"'_c._'_','_,

o "

1,

;,

rsv

from

OE REM(){]Eentry.ll.b, addt.wI

· Character String Instructions
OP 'Mnemonic andArgumentli
, .,',' ,
" ,Descriptwn , ",
',". N 'l V C E1!;~q>tiuns
29 CMI!C3 len.rw, srcladdr.ab, src2addr,a~¢o~pa~e ;hamc"t~J7~'~~--'''-~
,,-operand
* 0. 1{
2D CMPC5 srcllen.rw, srcladdr.ab, fill.rb i
Comparecnitr'.i,cter5·operand "
src21en.rw, src2addr.ab
3A

28

Mave character 3.operand

o

10.0

.-~...,..,.,....,.,---,.......--,-~

2C

Moves srelen.rw, srcaddr.ab, tilLrb,
dstlen:rw, dstaddr.ab, {RO-S.w!}

M6vecharacter .5-operand

2A SCANC len.fw, addr.ab,
.3B
28

SKPC char.rb, 1en.l'w, addr.ab
len.rw, len.rw, tbladdr.ab, maskrb

Scan characters

Confidenth!l and Propr~etary

1·29

!JDIIIID

Preliminary

. System Support Instructions
OP Mnemonic and Arguments
BD
BC
BE
BF

NZ VC

Description

CHME param.rw, {-(ySP). w'}
Change mode to executive
CHMK param.rw, {-(ySP).w'}
Change mode to kernel
CHMS param.rw, {-(ySP).w'}
Change mode to supervisor
CHMU param.rw, {-{ySP).w'}
Change mode to user
Where y = MINU(x .PSL < currenLmode < )

06 LDPCTX {PCB.r', -(KSP).w'}
DB MFPRprocreg.rl, dst.wl
DA MTPR src.rI, procreg.rl
OC PROBER mode.rb, len.rw, base.ab
OD PROBEW mode.rb, len.tw, base.ab
02

REI {(SP) + .1"}

Return from exception 01' interrupt

07

SVPCTX {(SP)+.r', PCB.w}

Save process context
(kernel mode only)

0 0 0
0 0 0
0 0 0
0 0 0

0
0
0
0

Load process context
(kernel mode only)
Move from processor register
(kernel mode only)
Move to processor register
(kernel mode only)
Probe read access
Probe write access

Exceptions

-

rsv, pry

* * 0

rsv, pry

"

rsv, pry

* 0 -

o "

0 -

o " 0 rsv
-

-

-

-

pry

. Microcode-assisted EmuJated Instructions
The CVAX 78034 provides microcode assistance for the emulation of these instructions by
system software. The processor processes the operand specifiers, creates a standard argument list,
and takes an emulated instruction fault.

OP Mnemonic and Arguments
20

ADDP4 addlen.nv, addaddr.ab, sumlen.rw,
sLlmaddr.ab

21

Description

N Z V C Exceptions

Add packed 4-operancl

-!~

,,/.:

~~

* " 0 rsv, dov

ADDP6 add Ilen. rw, addladdr.ab, add2Ien.fw,
add2addr.ab, sumlen.rw, sumaddr.:ab
Add packed 6-operand

*

0 rsv,dov

F8 ASHP cnLrb, srden.rw, srcaddr.ab, round.rb, Arithmetic shift and round
dstlen.rw, dstaddr.ab

35
37

CMP!'3 len.rw, srcladdr.ab, src2:addr.ab
CMPP4 src1Jen.rw, src1addr.ab, src2Ien.rw,
src2add.ab

OB CRe tbLab, inicrc.r1, strien.rw, stream.ab

~';

* * 0
Compare packed 3-operand " * 0 0
packed

*:

0 *

Calculate cyclic
redundancy check

*

,\:

0 0

1,

~\:

* 0 rsv, dov

CVTLP src.rl, dstlen.rw, dstaddr.ab
CVTPL srclen.rw, srcaddr.ab, dst.wl

Convert long to packed
Convert packed to long

08

CVTPS, srclen.rw, srcaddr.ab, dstlell.rw,
dstaddr.ab
CVTSp, srden.rw, srcaddr., dstlen.rw,
dstaddr.ab

Convert packed to leading
,;',
separate
Convert leading separate to
packed
"

1-30

dov

Compare packed 3-operand ,',

F9
36

09

r5V,

Confidential and Proprietary

*

,<

* 0

rsv, iov

."

.;~

0 rsv, dov

*

-I:

0 r5V, dov

24
26
27
38

39
34

Preliminary

CVTPT srcien.rw, srcaddr.ab, tbladdr.ab,
dstlen.rw, dstaddr.ab
CVTTP srclen.rw, srcaddr.ab, tb!addr.ab,
dstlen.rw, dstaddr.ab
DIVP divrien.rw, divraddr.ab, divdieri.rw,·
quolen.rw, quoaddr.ab
EDlTPC srden.rw, srcaddr.ab, pattern.ab,
dstaddr.ab
MATCHC objlen.rw, objaddr.ab, srclen . rw,
srcaddr.ab
MOVP len.rw, srcaddr.ab, dstaddr.ab

Desctipt.iQn

N Z V C Exceptions

Convert packed to trailing

* * * 0 tsv, dov

Convert packed to trailing

"

Divide packed

* *

* * 0 rsv, dov
ok

0 rsv, dov, ddvz

Edit packed to character

String

* " " * rsv,dov

0

. Match characters

.,,:

MoVe packed

.

0 0

" 0 0

2E MOVTC srclel1.rw, srcaddr.ab, flll.rb,
tbJaddr.ab,dstlen.rw, dstaddr.ab

Move thins1ate~ characters *, * 0 *

2F MOVTUC srden.rw, srcaddr.ab, esc.rb,
tblacldr.ab, dstlen.rw, dstaddr.ab

Move translated until
character

25

MULP mulrien.rw, mulraddr.ab, muld)en.rw,
muldaddl:.ab, prodlen.rw, prodaddr.ab

22

SUBP4 sublen.rw, subaddr.ab, dWen.tw,
djfaddr.ab

23

sublen.rw, subaddr:ab, nrinlen.rw,
minaddr.ab, diflen.rw, difaddr.ab

*
;,

Mpltipiy packed

..

* *

* * 0 rsv, clov

" " 0
SubtractPlIcked 6-operand * *

*

l"SV,

dov

0 rsv, dov

. Floating-point Instructions
These instructiol'.lS tire implemented in hardwal'eonly if the optional CVAX 78134 Floating-point
acceleratotis present in the system. They must be software emulated if the CVAX 781.34 is not
included.
OP

Mnemonic and Arguments

UesiZription

06F

ACBD limit.rd, add.rd, index.md

04F

ACBF limit.rf, add.rf, index.tf

Add compare and branch
D_floating
Add compare and branch
F_floating
Add compare and branch
G_floating

4FFD ACBG limit.rg, add.rg, index.ru~
060
ADDD2 add.rd, sum.md
040
ADDF2 add.d, sum.mf
40FD ADDG2 add.rg, sum.mg

Add D...Jloating 2-operaud
Add F_floating 2-operand
Add G_floating 2-operand

061
ADDD.) addl.rd. add2.rd, sum:wd
041
ADDF3 addl.rf, add2.rf, sum.wf
41FD ADDG3 addl.rg, add2.rg, sum.wg

Add D_f1oating 3-operand
Add F_floating 3-operand
Add GJ]oating 3-operand

Confidential and Proprietary

N Z V C Exci!p'tions

* *

0

* * 0
-"'i.~

rsv, fov,

fllV

rsv,tov, iuv

rsv, fov, fllV
* 0
* 0 0 rsv, fov, fuv

" * 0 0 rsv, fov, fuv
* * 0 0 rsv, fov, fllv

" *
",,( *
*

."
'k

'"

0 rsv, fov, fllv
0 rsv,fov, Iuv
0 rsv, fov, fuv

1-31

PreJimiwuy
---.-.....

-~-.

071
051

CMPD srcl.rd, src2.rd

'-'"-"'-"

-'

..

~.~

Compare D_floating
CbmpitreF_floating
'AHHlf' lQV

o
" o
..
if

;,

~',

l':

~'r

-1.
.,,~

o ()

.~

rsv, fov, fuv

" " " 0 rsv, iov
'.'
".

"
,',

" 0 rsv, iov
() 0

"
0 0
.... 0 0
,', ;, 0 0
,', ,', 0 0
t,
,'.
0 0
t,

.

* 0

0

1'51!, iov

1':

1:

-J:

,',.

~'r

~~

~':

~':

1:-

{,

Ci 0
0 0 rsv fov' [llV fdd

0 rsv ioy
l

;':

:'.:

0

0

0 rsv Eov fllV fdvi

-~~.~----------.-------

067
DIVD} divr.rd, divud, quo.\vd
047
DIVD,3 divl'.rf, dinr£, quo.wE
47FD DIVDJ divr.rg, divl'.rg, guo. wg

074

E:'vfODD muir,rd, multx.rd,
muId.rd, int.wI, fract.wd

054

EJ'vIODFmuir.rf, mulrx.rb,

muld.rd int.wl, fraet.wf

54FD EMODG
muld.tg
072
052

52FD
070
050

"I'vlNEGD src.rd, dst.wd
;';ovINEGF src.rf, dst.wf

sre.rg, dSt.\\ig

"

0 0 rsv fov fuv fdvz
0 l'SV fov fuv fdvz
0 0 rsv fov
fdvz

o
" *

Extended modulus D_f1oating

"

0 rsv

Extendedmodulus F_fl'lating

,',

0

,',

'k

0 rsv

,", "

0

0 rsv

'-,X'I-"HWfl

<'1\-10\'1) src.rd, dst.wd
*MOVF ,re.d, dst.wf
.50FD "MOVe; src.rg, dst.wg

1-32

Divide D __ float.ing 3-operand
Divide F_floating 3·operand
Divide G_floati.ng 3-operand

modulus G_Jloating

Move negated D_floating
Move negated F....Jhuing
Movy
G_f1oating
Move D_floating

Mow F_floath~g .
Move G_flciating

Confidential ilnd Proprietary

"

,1'
~'r

1~

':, - 0

"

0

-k

()

(/

-

()

_

1,' ~"

{nv iov

rsv fov fuviov

; and Arguments

N Z V C. EXceptiOns

Description

Multiply D_floating 2-operand I, " 0 0 rsv, foo, full'
MultiplyF_floating 2.operand " " 0 0 rsv, foo, full'
Multiply G_floating 2-operand ;, " 0 0 esv, fov, fuv

064
MUL02 multrd, prod.rod
044
MULF2 mulr.r£, prod.mf
44FD MULe) m,ulr.rg, prod.rug

065
MUL03 mulr.rd, muId.rd, prod.wd Multiply D~floating "operand " " 0 0 rsv,foo, fuv
045
MULF3 mukrf, muld.rf, prod.wf
Multiply F-iHoating},operand " " 0 0 tsv,fov,fuv
45FD MULG3 mukrf, muld.rg, prod.wg, Multiply G310ating 3-operand " " 0 O. rsv, £00, ftlv

075
POLYO arg.rd, degree rw, tbladder.ab£valuate polynomial D",.Jloating" " 0 0 rsv, foo, fuv
0 0 rsv, foo, iuv
055
POlYP a;g.r£, degte\': rw,tbladder.a~ Evaluate polynomial F_floating *
55FD POlYO arg.rg, degreerw,tbladder.ab Evaluate polynomial G_floating * " 0 O. rsv, roo, full'
Subtract D_float:ingZ:opernnd" 'II () '0' rsv, £ov,fuv
Subtl"act FJloating 2-operand " " 0 0 rsv, foo, iuv
Subtract G_floating 2-operand
* " .0 O· rsv, £ov, fuv
,

062
SUB02 sub.rd, diLmd
042
SUBF2.sub.rf, dif.mf
42FD SUBG2 sub.;g, dif.mg
06.3
SUBD3 sub.rd,mi~ rd,dif.md
04.3
SUBF2 sub.r£, minrf, dif.mf
43FD SUBG2 sub.rg, min rg, dif.mg

Subtract DJloating 3.operand ,,'*,* o· rsv fov fuv
Subtract F_floating 3~operand ;, ;, 0 0 rsv fov fuv
S.ubtractG_cfloating 3~ope.tand 1, * 0 O.ter (SI,;RiWi~hil1tP~
limits defined by the length registers, the ac<;t!ss is contrQll~bya·p~g~ table tba~:spedfies the
validity; access requirements,andloC3.tionofea~ page inth~region;:
/~.,1.·

Access control
The accesscontroHunction validates thetyp::,9f memoty'uccess that is allowed to a~ce~sa page.
Each page has a protection code for eachmo3e tnat determines if read or wri~~ 't'ef~fertces are

.

all~.

Four hierarchical modes are used by"fhe¢yAX 7$034. The processor mode th.~t,.is·cpFren~~
running is stored in the current mode field of the Processor Status Longword (PSL). The modes in
order of most to least privileged are
"H.,
" is 'Y .'!.,.}
,',',", ,;~J

• 0 Kernel";";' Used by the kernel of.theopeF~ting; sysrem'fe'r: pa',geimatlagemcht, sdiedtiUng,\itrid Itb
drivers.

,,.> ",

• 1 Executive-Used for

many ofihe'dpbAi¥fng isysterti·$~~fcei¢~ns.;

• 2 Supervisor-Used for services such as command interpretation.

• 3 User-Used for user'levercode:;ui:i1ities;-Eompaer~Idi::fju$gh~,
:

'

".--,-

-

ert.'

L

The protection code';lbcated'in thepage"tibfuentry fotth!tt page,'~peclfih:'whelher the page can
be accessed for each m.ode. These codes are described in Table 12.

1-35

...!a

CVAX11~O~4

Preliminar,i
TabJe. t2 •. CVA"X 71:\034 J?rotectioo;t:;ode!)' Assign!)1¢pt s

Code
decimal

binary

Mnemonic Current mode'
K
E

0

0000

NA

1

0001

2

0010

KW

RW

3

0011

KR

R

4

0100

UW

RW

RW

5

0101

EW

RW

RW

6

0110

ERKW

RW

R

7

0111

ER

R

R

8

1000

SW

RW

RW

RW

9

1001

SREW

RW

RW

R

10

1010

SRKW

RW

R

R

11

1011

SR

R

R

R

12.

1100

U~SW

RW

RW

RW

R

13

1101

DREW

RW

RW

R

R

14

1110

URKW

RW

R

R

R

15

1111

UR

H

R

R

R

1

-=00

S

U

Comment
no access

~'(*

reserved

**

access

RW

RW

all access

K=Kernel
E = Executive
S = Supervisor
U=User

,,*= uIlpredictable
R=readonly

RW = read/write

Memory-management Control
The three registers used. tQ control the memory management function are de.scribedas follows;
Map Enable register (MAPEN)- This register is used to enable and disable memory management.
The format of the register is shown in Figure 17 ansic.lcs(,:.ribedin Table 13.

I::: ::::::: :::: ~+: :::: ::: :<:: ::: 11
31

01 00

"

.

'

'.

•

•

••

. , "

••

<

••

\

MME

Figure 17· CVAX 78034 Map Enable Register Fonnat

1-36

Confidential aDd Proprietary

Table 1.3 ~ CVAX 7$034 Map Efiabte~~$teiUescnption
Bit

D~~tip*Wn·

31:01

MBZ-Must be zero

00

MME (Memory management enable)-Enable and disable memory management as
follows:.'

i

MME == 1 (enabled)
MME =0 (disabled)
Translation buffer-This buHer,is used to.sa'Veitheact~aIme!11ory~ferences when pages are
recotdsuccessful virtual address
repeatedly referenced. TheCVAXCPUuses thisbufMt
translations and page status. The translation buffer contaim 28 fully associative entries. Both
system space and process space references share the entries. Translation buffer entries are replaced
using a Not Last Used (I::J.\;.:W~<:l:rjthJnitQ t;f~~:n;F:kj.qti"'~\11~~p~~eme~t.~i4~er is not pointi~g to the
last tran&Iation buffer entry to be usel>pi!~~j~mgp~d'\:!Y the PO Page
Table (POPT) .tgat i~,lO}:ated in system.:viJ:tl1alJl.ddre~~ space: thel>fJ region addres3i~.d.~fined by the
PO Base Register (OOBR).The pagetableen6l'ypeint@dtobythePOBRmaps th@Hrstpage of the PO
region of the virtual address space which is virtual byte address O. The PO Length Register (POLR)
contains the number of page table entries in longwords. Figure 23 shows the POER and POLR
mapping formats.fhe process of translating
vittua[ address to ~ physical addt-ess is shown
in Figure 2 4 . '
.

arb

,POBR

Figure 23 • CVAX 78034 PO R~giotl MappingF?,egisters Forrnat

00

09))8

PVA,
I?ROCESS VIRTUAL

BYTE NUMBER

ADDRESS)

020100

a
ADD

31

POBR,

0100

I:: ::: . ::.:
YIELDS

FETCH BY $YSTEM SPACE

TRANSLAl"JO~'ALGORtTHM:
INCLUDING LENGTH AND
KERNEL MODE ACCESS CHECKS

PTE,
CHECK ACCESS

PHYSICAL ADR,oF Dp,Tf.>,;

Figure 24· CVAX 78034 PO Virtual-fa-physical Address 7.ranslatian
1-40

Confidential and Proprietary

Pl'~~e

PI Region Address Translation-The PI region of the address spaceismal?ped by:trre

Tahle (PIPT} that is located ih system virtual address space. The, P~regiotl' is .ddinedhy·the 'P 1

&'ise Registet (PIB'R) and the PI Length Register (PILR);Be~ause the Plspaceoovlinces toward

smalleradcb:tSsesahd because a consistent hardware interpretation o~th~base andIengthtegisters
is not desirable, NBRand PILRo"e£ine the portion of Pl'spaee that is. not accessibfe~The PILR
contains the numbetof nonexistent nEs: ;Pl$Rcomains,the sysrerl1'i;firixial addresseE \vhatw6uld
be the PTE for the first page of Pl which is virtual byte address 40000000 (hexadecimal). The
address in PIBR may not be a valid system virtual address but all acld~$wtlfP:l'Es;.mu$:tthe:*,$id
svstem virtual addresses. The P IBR andPILR rn.~ppil")gfor~~t issho\Vnin Figu~ :25. The prqcess
dE virtua.I-address ph~sical address transliad<)fi issh6w~ in ~igdre[ 26, " ,

to

"

1

. , ,

,- ",

•

':

\,'-'.

"'-"_

"r

:-,.,-.,',

_

"

"VA:
IPA OCESS VI RTUA L

ADDRESS)

P1BR:

vi ElDS,
;0100

31

FETCH BYS",S'\gM:~/l.G:~l::
TRANSLAHON ALGORITHM.
INCLUDING LENGTil.AIl

Figure 29· CllAX;786J4ini~i7~pt
_

,C

.., " . :

Interrupts

, ..

l~y:"

Prio'rity Uvfl RegisWjP6nnat
':",/':: :",'·:;'-'-1

. .. ,J'.:" . :

Hardware and software intet;rJ.lptsate. iAitiatedpy.the£~Uowing
conditions.
-""-'_,l§/'_'",,,-_
Hardware interrupts-Hardware interruptsiare;U,U,t:i:ll,ted by' HALT (nonmaskable interrupt),
PWRFL, MEMERR; CRD;INTTIM, andlRQ < 3;O:>s~nals. nest signals a.re sarnpl~don:ceea~h
microcycle by Jbe .im~l1uPt~om1'9Uer ,. of the .
n~'intert'U.Pt .\':ontrolle.t..comp~re5ih'e, IPi
fl#ioci~~ed wjt~ ,alily,.s,ig,MitMt i.S>a$s~rtdd 1lotheClirnwt 1PL of tbe CPU..lfany'·of;trn.nlsserted
signals hav.eati.IPLhlgh~rthantbe CP:U,alltnterruptwillbe taken. For interrupts generated by the
HALT, PWRFL, MEMERR, CRD,ap.dINT1'lM,theCJ?U::internally generates a vector which is an
offset into the seE. For interr\lPtsgen~ra.ted;by.IR.Q, the CPU executes an interrupt
acknowledgecyde to fetch the vectodrcm the devicetequesti.ng the interrupt.
Aninterrupt is serviced at its priority levelexcept for interrupts requested~1Ii';R""·Q~·.•. ··;-':<::'l!'5n:O'l':>:!""·tllafa~
serviced at eithertheintssociatedlPL or 1PL17{hexadedhlai);'Thelexlclat whkhan interrupt
reqaesred 'by afl'IitQ3:0 ::> is serviced is determih~ by. {}ALOO When the··devke&enas· the vector to
the CPU. WheriDALOO fs a fO, the' ihi:etmptisse'r'VicW'at:' the I:PL' assOciatt~dwith the" ai;serted
signal. When DALOO is a 1, the interrupt is serviced at IPL 17 (hexadecimal).
;,'

.

:'\ .• ~'.J,,'jc,;,,'

',i/'

I

,,,.'~

'"-,,i

CrO:.

1-43

-_ .... ...
~

~-----------

Software interrupts:-Soft wareim(:rruPt~arerequ(!Stf:o:l.bysys.~em 8rU$erJl,1llf.;I'fX;Qt/e by writing a
value into the Software Interrupd~~questRegister(SIRR). The value 'wtitten to the SIRR is one of
the IPL levels (hexadecirnal).assig.n&tto softwiu:e' interrupts. Writing a value to the SIRR results in
setting the correspqnding bit in the software interrupt summary register. The interrupt controller
compares the IPL of the highest pending software interrupt request to the currentIPL of the CPU.
If no outstanding hardware interrupt exist and theIPL ofthesoftware interrupt is higher than the
current IPL of the CPU, the interrupt will be granted. The CPU internally generates the interrupt
vector in the SCB.
The sJftwarein~etrupt system is affected by an.R.EI instruction orother event that change~theI'ri£
ohheCPU. I(theIPL'ischanged to avalue lower than the highest pending software int~rrupt
request and no hardware interrupts are pending, the interrupt controller grants the softw~e
int~rtupt.
.
.
.
.
Exceptions
An exception is an event resulting from the execution of a specific instruction. Exceptions also
include errors automatically detected by the prqc.esso.r such as.improperly formed inStructions. The
CVAX 78034 recognizes the six classes of exceptions summarized in Table 16.
Table 16 • CVAX 78034 CPU Summary of Exceptions
Exception class

Cause

arithmetic traps/faults

integer overflow trap
integer dividehy zero trap
subscript range trap
floating overflow fault
floating divide by zero fault
poating underflow fault

memory management ex,ceptions

aq:esscontrolviolation (Aev) fault
translation not valid (TNV) fault

operand reference exceptions

reserved ~dqre;ssing mode fault.
reserved operand fault or abort

instruction execution exceptions

reserved/privileged instruction fault
emulated instruction fault
custoinerreserved insttllction fault
breakpoint fault

;),

trace fault
System failure exceptions .

Sx~ternC~ntroIBlock.

.'

machine check ~hort including read/write b\lS aod parity
errors, cache parity errors, and FPAiJt6tocol'errors
kernel smckndtvalid abort
.... '
interrupt stack not valid abort ;

.

TlJ,e System C(~ll1trol ,Bloc1; (SCB) isa page alignedtt

Type'

(n.decimal) '..

00
04
08
OC

interrupt ;'

passiveiclease

machine check
kernel stackhot~alid
po~erfaif , r

10
14

tesefved/privU~.a~d·histhtction

18
IC
20

re~.rV~dqperand
Cre~rv'edaddrcssiriglll~(Je'
accesseonfroI vibiati'C:ih
tnitlS'llltioJ:1'not'valid
trace pending (TP)
breakpoint instruction

24

28
2C

ustomer reserved'

instnictlon""

30
34
38:")C

unused
arithmetic'

40
4C

CHMK
CHME
CHMS
CHMU

50

unused

54

corrected read data
unused
memory error

44

48

,5&-5C

60
64-80

84
88
8C
9O-BC

CO
C4

CS
CC
DO,,-FC
100-1FC
200-FFFC

. abort

'flbtJri
im:etrupt

fault" '

'£Ju1~"

·laGleMb but only one interrupt grant is daisychained. Devices on the
Q-bus are also arranged so that higher-priority devices are electrically closer to the bus master. If an
IRQl is being serviced, a device with a higher priority may intercept the grant. Software must
determine the level of the device that was serviced and set the 1Pt to the correct value.

is

External devices, except devices that emulate the console storage and terminal hardware, should
use only the vectors in the range of 100 to FFFC ~hexadecimaI).
Machine Check
A machine check occurs as a result of serious internal CPU errors or external CPU errors such as
memory subsystem errors. These errors and conditions include

• FPA protocol errors.

---------------------------------------------

• Impossible situations in memory management.
• Unused 1PL requests.

-------------------

• Impossible situations in the CPU microcode.
• Bus memory errors.

• Multiple errors.
Machine Check Processing-The CPU processes a machine check as fonows:

• If an exception is in progress and a machine check occurs, a processor restart is executed by the
CPU. Refer to the Processor Restart description that follows.
• If the current instruction can be suspended (MOVC3, MOVC.5), the state of the processor should
be saved and the machine check handled.

• If the instruction cannot be suspended, the state of the processor should be returned to the
beginning of the instruction, if possible, and then the machine check should occur.
An instruction that cannot be restarted after the machine check is considered nonrecoverable and
the current process or the operating system must be terminated,
When a machine check is generated, the CPU sets an internal serious error flag and performs
machine check exception processing through SCB vector 4. A machine check exception is always
processed on the interrupt stack. \Xfhen machine check exception processing is complete, the CPU
clears its internal serious error flag and the next instruction is decoded. The parameters recorded
on the stack for a machine check are shown in Figure 31 and listed in Table 18.

1-46

Confidential and Proprietary

PrelimiMry
...

. , .>.
:$P

BYTE COUNT (0000001 0 HEX)

MACHINE CHECK CODE
.

MOST RECENT MEMORY ADDRESS

,.

INTERNAL STATE INFORMATION 2
INTERNAL STATE INFORNl~TION

1

PC

J.

PSL

,.

.....

Figure 31· CVAX 78034 Machine Chell/Stack

Table 18· CVAX 780~4 Machine Cheek Parameters

Machine cheekcode(~declmal>:
code

definition

1
2

FPA protocol error ..
FPA res!"'rvecl.insttuction

3

FPA unknown error

4

FPAunknown error.
process PTE in PO space (TB miss)
process PTE in P1 space (TB miss)
process PTE in PO space (M "'" 0)
process PTE in PI space (M=O)
undefined. interrupt.ID code
impossible microcode state (MO'VCx) .
read bus error,notmal read
read. bus error,SPTE, PCB, or SCB read
write bus error, normal write
write bus error,SPTE CltPCB write

5
6

7
8
9
A'

80 .
81
82
83

Most recent memory address:
address
value

31:00

currentcohtcnts of VAl? register

Internal state infurmation!:
bits
value
31:24
23:20
19:16.
15:08

07:00·

current contents of opcode 7:0
1111 .
current contents of HSIR 3:0.
current contents ofCADR 07:00
current contents of MSBR 07 :00

Confidential and f?roprietary

1-47

Internal state iJIformiirlon2i'
bits
value
31:24
current contents of SC 7:0
11·
2.3:22
cutrent contt~nts of State 5:0
21:16
15
current contents of VAX CAN'T RESTART bit
14:12
111
11:08
cu~rent ALU condition codes
07:00
delta PC at time of exception
Program counter (PC)

bits

value

31:00

PC of start of current instruction

Processor status longword (PSL)

bits

value

31:00

current contents of PSL

Machine Check Errors
Machine check errors include protocol errors, memory manag(:rnentand l11icrococie.inJ.p9;ssihle
situations, bus memory errors, and multiple errors.
Protocol-CVAX 78134 FPA checks for the proper order of requeSts frorn the CPU. If a protocOl
violation is detected, a machine check occurs. All FPA protocol error machIne checks are
nonrecoverable. The error should be logged and the currently runningpr(\cess or the operating
system should be terminated. TIle hexadecimal codes generated for a FPA pwtocol error are
Code

Error

1
2
3 and 4

FPA protocol
FPA reserved instruction
FPA unknown

Impossible situations (memory management)-The CVAX CPU checks for some impossible
conditions in the memory management unit. If an Impossible situation is detected, a machine
check occurs. All impossible memory management machine checks are nonrecoverable. The error
should be logged and the currently running process or operating system shouldbeterminated. The
current memory management registers (POER, PIER, SBR,POLR,PILR, and SLR) should also be
logged. The hexadecimal codes generated are
Code
5

Machine check error
The calculated virtual address for a process PTE is in PO space (T13 miss flows)

6

The calculated virtual address for a Process PTE is in PI space ('fB m~ss.flows)

7

The calculated virtual address for a Process PTE is in PO space (M = 0 fl~W?)

8

The calculated virtual address for a Process PTE is ~n PI space(M = Oflow~)

Unused IPL request-The CVAX CPU uses 13 of the 16 hardware interrupt priority levels as
defined in the VAX architecture. If an interrupt at an unused hardware IPk isrequested;ia
hexadecimal code and machine check occurs. The unLlsed IPLmachine.·check isorronrecoverable.
The error should be logged. A nonvectored interrupt representing aseriolts error (corrected'reacl
data, memory error, powerfail, or processor halt) has probably been lost. The operating system
should be terminated. The hexadecimal code and error is
Con£ident~al.and

Proprktary

Preliminui
Code

Machine check etror

9

The interrupt controller returned an interrupting IPL of 18, 19, o~ IB(bexadecimaIf.

Impossible situatWils (microcOOe) __:Bec~use of ~ize constwnts', erron~usbranches in microcode
will usually result in the execution orranqprrJUicrOinstruCri()~s.H0'PeYer.ihhe microcode detect.s
an impossible situ~tion,

a ma~hine cheH~ .oc<;urs.

The

imPRssib,ie'~l~~9<1e 'machine check.~s

nonrecove~le. Tht!errorshould be logg,ed,:;a;Id the cup;e~tlJ'.ttiA~tli.P1;C1c1f~s,or the operatlpg
system should be terminated. 'the folIowirig~:Kadecima1
error is.ge9~~ted.' .

cooeana

Code

Machine check e~r

A

MOVC3 or MOVC5 in impossible state

&sme~ory ~:::--U~l'terna1JQgi~ a,sse~t~,U;~E".~· ry~eSw~~:t;o!a!~s~,oty~~~·!?iher.,f~'ap

.l\.

/aqq.

instruction pr~fetch Or· inter11lpt.acknpw-ledge, ,fU~c~:!;~k .·G<;;~u1\$
the .
he:xaciecimalc(ldeis g~nerate4..·'
... ' .' .. .'. ,'. ....
. ..'

Code

Machine check error

80
81
82
83

read bus error, normal read
read. bus error, SPTE, PCB, or SCBread
ritebu~error; normal write
write bus error, SPTEorPCB write

tqIlQ'Wlns
.'

Bus memory error machine checks may be recoverabl/tdepetldiog on theettorcode,fhe:VAX Can't
Restart flag, and FPD flags iothe machine checkstackfrnme;Busmemoryerror machine checks
that are recogn~dby the CPU as restartable may be nooreeov~l;1tb1efor system reasons (e.g. , a read
lock may be outstanding). On a nonrecoverable,error, iheerro*,shou!d 00 logged, and the currently
running procesSjor theoperatingsystern shouldhe terminated. The code andrelationship is

Code

VAX can't

FPD~Actioll

restart*

80,81

82,83

1

.1

X
0
1

restartable
nonrecoverable
restattable

X

X

nonrecoverable

0

* X is either lorD.

Multiple Errors..:..lhheCVAXCPU enc6uhtersseti0tls,erfot's that are nested together (e.g., kernel
stack not valid inside a machine check) or otber p4ition.srhattannbrbe p~cessedby the system
macrocode (e.g., HALT instruction in kernel mode!;,themkrocode places the current PCin internal
processor registerSAVPC and the current PSL, MA,P£?N, tHlErutartcedeinintemai processor
register SAvPSL'. It then executes a. processor restart, ..

co

Processor Itesutrt-H thehal'dwareor lrernd~oftw*envi:ronment becomesseverely,corrupted,
the CPU maYndtBeable.tocontinue.n~rmalpro0esslng;The-CPU"thef'e~~tes~processor restart
operation and transfers control to the~coverycode.beginning· ~t physi(;aladdress 20040000
(hexadecimal). l'heSAVI'C register c.outruns theprbiious PC v:alue.and the SAVPSLregister contains
the previous PSL value \VithM,APE.N in bi~l?, il. yqJi<:l ~~iJ.ckUl!g~n\Jit. J4,it,p9. are~r.arf~e in bits
13:08. The restart codes are summarized in Table 9. The stateqft.he CP,Ufq,fllprq:esSQ.rrestart is as
follows. All other registers are not defined.

1·49

Register

Condition

SAVPC
SAVPSL

saved PC . . '

pC
lv1APEN

... ' C ' ;
,,
'.
,"
.'
saved PSL bits 31:16. 07:00in bits ?1:l6and 07:00 rsavedj'4APEf\jOin bit15,yalid
~tackflag inbit'14, and saved restart code in'bIts t3~08' ."H ',;', ',':' " "
interrupt st~ckp~inter'
ASTI"VL ,,'
(powerup0I?-lv) ,
'
041 FOOOO (hexadecimal)
, tces
,'cleared (powen;p 9tUY)
20040000(hexudecimal)
MSER,
'de~4(p~werup,only)
cleared
CADR
cleared (powerup only)

SISR

cleared (powerup only)

,4

sF
PSL

Process Structure

A process is a single thteid of execu~km. The context ~f the curreritprocessi~ cdnta'rri~diri the
ProcessControi Block (PCB). The PCB, as defined by the (VAX 78034 CPU, is shown in Figure 3L.

The PCB is located in physical memory and is pointed to by the Process Control Block Ba~e register
(PCBB) shown in Figure 33.

00

31

KSP

:PCIl

ESP

+4

SSP
,

" USP

+8

,

+1

RO

+

,~

~

:,

Rl

R2

+

':~,

R3

(

+28

:.\

"

+32

R4

;

c
"

,

A5

+36

R6

+40

R7

+44

RS

+48

R9

+ 52

RIO

+56

.

Rll

"

:1-'60

"
,

AP (RI2)

+64
+68

FP IR13)

PC

:

,',

+72

PSL

+71\::

POBR

MIjZ
,
PMEL

,I NT
,

[MBZ!
:

"

; ',MEZ,

'c,

"

POLR
PIBR

,~~
.,'

J

.

,

'b

'L'

Figure 32· CVAX 78034 Process Control Block Format

1-50

Confid~ntiaI

andProprietaJ:'Y

+S4

--'"

""-

P1Lfj

"

:,

+BO

. 81l,' ,

+92:

:pcnH

'Figure 33· CVAX 78034 Process ContralBlock Base Register
Processor Registers
The VAX architecture defines thelnternai Pnx:essor Register~(lfRs).Some of treseregisters 'at'e
implementedin the CVAX 78034 CPU and s6ni~ canb~ ilJ1Pll:!~ert~~in~tetria)lbiii~~nd ~ccess~d
by the CVAX CPU. These registers are explicitly accessed p)i.:'t,'he'MQve;To'>P1'OccssOr Regisier
(MTPR) and Move From ,~rotes~or ·R,tj5i~trr(MFPR)ihstroctiolis. ,~ql~ '"~,~.',,.lij;~s.','tl;te iliternil
processor registers and their categories that are defined asJollows: ,., ... ' . .' ,

1 Implemented by the cVAXCPTJas specifiM in the
032).

VAXAJ:chiteCdl~St?hdaiq(1::iEcS~atld;1rd
'

2 Implemented only by t4e \0lAX(:PU.

3 Passed to ex terna1Iogic •via an qternal p,rQc~ssor register CYCle, If not externallyirn;plementti/,
they are read as zero and perform nofuncdonduringwfiteoperations.

4 Access not allowed (reserved o~~and fauli).

Number Register Name

o

I'

,.

,

,) "

M!.i~th.Jnk·f~j Sc~P('

.Kernel Sta-c-k-P-o-in-t-er"""'-''~---""""'-K~'SP

,J-t\Xi

PROC";

"Category'~
1

J

2

3
-1

5
6

reserved

4

7

reserved

4

8

PO Base

9

I.

10

1

11

L

12

System

13

System

14

reserved

-1

15

reserved'

4

16

Process Control Block J3;1se

,', Refer to Processor Register description.

1

SLR

PCB))

I\W

CPU

1

Preliminary·······
Mncmol1ic,Type ~.~nitWi~e Category'"

Number Register ..Name.

---"-~----------'--'--~---------------"-7 lines during the addl'esspart of a bus cyd~.
Data Class-The data class inch~en:sfream(il1~trucEi{ji:f;sijeam) and D·stream (data stream).
I-stream references are genemted b¥theGPUwhen"prefei()~ i~structions in the instruction
stream. D-stream references are generated by the CPU when data is required by the executing
instruction.,\Vlwnres()lvi~ a fa*dI~streallll'eference, 0.1: w~nfi11(Qga,FlAchem~m~ryl~

when ::In/9P~l"fln4t P,,:T?, SCB~d ~!3, ~fere!¢c~s.;;¥l g~firl.rte.•~e,m,a!1qJ:)~stream.reads,
Wt;ite oyde~ are·gen.eratedwhen dalia.istobewxittehtocl1chei!mdexter~alme~.

Preliminary:
Re9ue~t~hdde~Itdmadcy9~~··resp()[,!~. di£ferently to errors report~#'rR4rin~,.tqe refe~llpe.
Request read errors usmilly do not affect program flow, and demand read errors cause a machine
check abort. The effects of errors on the operation of the CPU during these cycles are described in
the Envr Handling section.
Cache Memory

To optimize the performance of the memory subsystem, the CVAX CPU contains a 1 KByte, twoway associative, 8-byte block cache memory. Cache memory can be configured to store I-stream
only, I-stream andD-stream, or D-stream only (diagnostic use) references.

Organization- The CVAX CPU cache memory is organized into twCl sets of 64 rowsas shown in
Figure 34. Each row in a set is made up of a Valid (V) bit, a 20·bit tag with.parity, and 8-byte data
block with byte parity shown in Figure 35.

SET 2

SET 1

DATA

TAG

DATA

TAG

12 o· BITS WITH

{S BYTES WITH PARITY}

{20·BITS WITH
PARIT'! AND
VALID BITI

PARITY AND
VALID BITI

93

n

00

71

18 BYTES WITH PARITY}

72 71

93

DO

Figure 34· (,VAX 78034 Cache MemoryOrgalliz(ltiori
00

19
TAG

p ~ PARITY IllT
V' VALID BlT

hgure 35' ('VAX 78034 Cache Jag arid Data Format

Control

Operation of cache memory lscontrolled by the Ca~che Disable :Register (CADR) 'arid th.~ CCTL
signal. Status informatiotl'is reported by the Memory Error Register (.MElMER)ahci CSDP3: 1ht:
CADI{ register determines the operating mode of the cache and selects the set(s) to be enabled.

1-54

Confidential and Proprietary

....

Preliminary

Extetnallogic can use the ccn signal to prevent the storing of data in cache during CPU read
cydesandtoinvalidate cache entries during DMA cycles that write to a memory Iocaiion stored in
cache. CSDP3ailows external logic to track the set in the internal cache that has been allocated.
This allows a coherent external cache memory system to be constructed.

Access-A cache memory location is accessed by a physical address generated by the CPU. The
cache physicaladdresses ate shown in Figure 36. The function of each field of the physical address
is described in Table 20.

2928

0908

0302

lhl

III ::::::: ;iAfe{ :;: : : : ;:I++~+~~l
. . :I:1
110 SPACE

BmIWORD/lOIIJCWORD
SELECT

Figure 36· CVAX 780.34 Physical AddressforCacheAtcess

Table 20 • CVAX 780.34 PbysicalAddress Description
Bit

Descrjption

29

I/O (input/output)-Thisbrt'indicat~s ~he'iherthephysiciladdress isi~'r/O space. When
set, tbephysical addressisin I/O space. IjOspace references' are never stored in cache. i

28:09

Label.....c. These bits are compared to the TAG field(s) of the row selectedhy the Cache
Index bits 08:03.

08:03

Cache Index-These bits select the row in cache memory to be accessed.

02:00

Byte/WQrd/Longword Select-These bits select the bytes to be accessed in the data block
when there is a cache hit.

Cachable reference-A cachable reference has thefoilowing characteristics:
• The reference matches the type selected bybit$ 05:04 of the CADR. These are I-stream only,
I-stream and D-stream, or D-stream only (diagnostic use).
• The reference is not .aread lock reference.
• The reference is not in I/O space, bit 29 of the physidlirddre'ss is O.
Cache hit-,.A cache hit occqrs when the requested data iSPfesent and validin cache memory. Ahit
is recognized when the label field of the physical.addre~sisthe san,'Je as:a tag in tbteselected set(s)
and the entry is valid. During:a CPU readopepltion, the data 1$ ftom cache tl;lemory and noekternal
bus cycle is. performed. During. a CPU write opel?.ltion,cache memory al).d external memory are
updated. This is defined as a write-through.
Cache miss-A cache miss occurs when theJ'eque~ted data is hot in cache memory or. is not valid. A
cache miss during a CPU read operation re:>(utsin a cache allrn;ation if the te£erence is a cachable. A
cache location cannot be allocated on a write, miss.
Cache allocation-The CVAX CPU allocates a 'Cache memory location when a CPU read operation
to a cacheable reference results in a cache miss.\X'hen thcCVAXailocates a cache memory location,
Confidential and Proprietary

mBIBIII

Preliminary

it initiates a multiple transfer c:ru read cycle. This bus cyde will read1wc;>longw9rds from memory
to fill the alloc.ated 8-byte row in cache. The first longword read is the one that contaihs the data
requested by the c:ru (preferred longword). The second longword read completes the quadword in
the row.
Random set selection is used when both sets in cache memory are selected. The CPU does not
differentiate between valid and invalid entries when selecting the set for a cache allocation. When
the CPU allocates a row in cache, it clears the valid bit for the row in the selected set, fetches the
preferred longword, fills the row with the second longword, and sets the valid hit if no errors occur.
Refer to the Multiple Tmns/er CPU Read Cycles section.
Error Handling
The response of the CVAX 78034 CPU to errors depends on the type of error reported and the
function being performed at the time the error was reported. Some errors result in an interrupt,
and the CPU responds to other errors. Errors reported by the assertion of the CRD,. MEMERR, and
PWRFL signals generate interrupts. Bus errors, DAL parity errors, cache parity errors, and memory
management errors have a defined response from the CPU.
Bus errors-External logic notifies the CPU of a bus error by asserting the ERR signal during a bus
cycle. The response of the CPU to a bus errors is summarized in Table 21. External logic can also
request a retry of some bus cycles by asserting the ERR and RDYsignals.

Table 21 • CVAX 78034 Response to Bus Errors andDAL Parity Errors

Cycle type

Prefetch

demand D·stream
(read)

Cache'

Error status'

Results

entry is
invalidated

logged in
MESRbits 06:05

machine check
abort
machine check
abort

write
request D-stream
(read)
,-request I-stream
(read)

prefetch
halted

entry is
invalidated

logged in
MESR bit 06

entry is
invalidated

logged in
MSER bit 06

'The entire row in cache memory selected by the faulting address is invalidated whether the
reference is cachable or not cachable. lbe entries from both sets are invalidated.
'Only DAL parity errors will log the status.
DAL parity errors-External logic enables DAL parity checking by asserting the DPE signal. Each
8-bit byte of DAL data is conditionally checked by a patity bit. Odd data bytes have odd patityand
even data bytes have even parity. The parity sense is alternated in order to detect stuck-at-one faults
and stuck-at-zero faults. DAL parity checking can be disabled, reference by reference, by
deasserting the DPE signal.

The action following the detection of a DAL parity error depends on the type 6f referenc:e; Durirtga
demand D-stream reference, the cache entry is invalidated, the cauSe of the error is logged in the
MSER bits 06:05, and a machine check abort is initiated. During request D-stream and I-stream
references, the cache entry is invalidated,. the cause of the error is logged in MSER bit 06, and no
abort occurs. Table 21 lists responses of the CPU to DAL parity errors.
1-56

Confidential and Proprietary

'.

Preliminary .

CVAX7S&34

Cache parity-The CVAX CPU protects the internal cache with parity. Each 8-bit byte of cache
data and the 20-bit tag field is checked by a parity bit. Odd data bytes record odd parity and even
data bytes record even parity. The tag field records odd parity. The stored parity is valid only when
the valid bit associated with the cache entry is set. Cache parity is checked on all cachable read and
write references that can be stored in cache and on DMA invalidate cycles. Read cycles report cache
parity errors when a valid tag matches bits 28:09 of the physical address and either the stored tag or
the longword selected by address bit 02 generate a parity error. Write' and DMA invalidate cycles
report cache parity errors when a valid tag matches bits 28:09 of the physical address and the stored
tag generates a parity error.
The res4ltsof detecting a cachy.parityerrordepend on the reference type'l:)uring a. demand
D-stream reference, the entire cache is cleared and disabled (CAbR is cleared), thecauseof the
error is logged in MSER bits 04:00, and a machine check abort is initiated. D~irig a DMA
invalidate cycle, the cache remains unchanged, the cause of the,errqris loggedin MSER bits }:O,
and an ~hqrt does not occur. During areque.s~I";stteamref~rence. the e~tirec:aclre is cleal'ed but it
~,mainsenabh;d,thecau~e of.the error is loggedinMS~Rbits '3:0, prefetchingis halted, and an
abort does not occurs,
The responses of the CPU to cache parity errors is listed·in.l'ahle22.
Table. 2.2 • CVAX.7.,. 8.034. Respbhse f.CI Cache.·• •. Parity.·.Error
'"

Cycle type

prefetch

! ',', . .

demand D-stream
(read)

cleatcach~ .

write
cache hit

clear tache!

DMA invalidate
cache hit

no cache
change

write
cache miss

(not possihle)

request D-stream
(read)

(not pOssible)

request I-stream
(read)

and disabled'

prefetch
halted

,

-'"

"

Cach~

clear cache

Results
logged in
machine check
MSER bits 04:00 abort
-logged in
MSER bits 03:001
logged in
MSER bits 03:00'

logged in
MSER bits 03:00

'The cache is cleared only if CADR bit 00 is cleared.
A parity error is detected only in the tags.

2

Memory Management Error-The CPU resf)Onsetomemorymanagement faults is listed in Table
23. Refer to Memory-mafUlgement Faults for a &~scription of memory management faults.

lable 23 • CVAX 78034 Response to Memory-management Faults
Cydetype
demand D-stream
(read)

Prefetch

Results
memory-management fault (ACV, TNV, etc.)

Confidential anciProprietary

1-51

Results

Prefetch

.Cycle type,:'

mem~ry-manageme~t fault (ACV, TNV,etc.)

write
requestD-stteam
(read)

(not po~sible)

reqqestI-stream
(read)

prefetch halted

Interfacing Requirements
.
The power supply, clock timing, and bus connections totheCVAX CPU chip are described in the
'following paragraphs.
Power and Ground Connection's
The CVAX 78034 requires a singleS-volt power supply. Six Voo pins and six Vss pins connecitothe
,power supply and ground. The TEST/V% pin connects to the supply ground or can be used for test
purposes. Figure 37 shows the power and ground connection and decoupling.Table 24 lists the
CVAX CPU pin and associated power and ground requirements;

Note
Care must be taken when cO.Q?ecting the Vnnand Vss pins,.1he VoDpins should be connected
together and to the 5-voli pow~r plane using short wires. The Vss pins should also connect together
and to the ground!plane using short leads. The power supply should bedecoupled by cotinect'inga
0:33 f and a 0.047 f ceramic or equivalent capacitor between each Voo pin and its associatedyss pin.

75

53

+5 V

16

52

+5V

77

III

51

041' 3;f

+5V

VDO

I.
vss

CVAX .78034 CPU

VSS

+5V
All VALUES IN ~F. ALL (fAPACITOru;; C;EHAMIC OR EOlJIVALf.N\!

Figure 37· CVAX 78034 CPU Power and Ground Connections

1-58

C;:Ol1fidential and Proprieta:t;y

+5V

Table 24 • CVAX 78034 CPU Power Distribution
Pin

Type

Output signals powered

76,53

Voo

DAL<31:00>, BM<3:0>

75,52

Vss

DAL<31:00>, BM<3;O>

77

Vpo

cache and internal lDAL drivers

51

Vss

ca~h~ anQ..internal rDAL drivers ,

1,36

Voo

interhallQgic

2,37

Vss

internal logic

21

Vpo

22

v;,s

20

C:PDAT<5:0>,.cPSAT,TEST,CWB, CCTL,DMG, DS, WR,

csnp<3:0> .

Vss

Clocks and Synchronization
The CVAXCPU uses two precision M6s,clock inputs to generate its internal timing and control
signals. These clocl~s are provided by the CVAX 78135 clock generator. The TTL level oscillator
input provides the two 180·degree,' phaSe shifted, precision MOS clock signals required by the
CPU.
The RESET, RDY, and ERR.signals to the CPU must be asserted synchronously with respect to the
CLKA and cI.Jd3 inputs. To aid the system designer, the <:VAX 78V5,c~ock (CCLOCK) generator
provides a common synchronization point for these signaIs.Thisanow~peripheml support chips
and other devices to operate asynchronously with the CCLOCK and to synchronize these inputs to
meet the timing requirements ofthe'CPU. Figure 38Shows the tVAX 78135 CCLOCK in a CVAX
78034 CPU system. Care must be taken during board layout to limit the amount of skew between
the CLKA and CLKB inputs of the CVAX CPU so that the timing parameters are met.

Confidential jl.qd Proprietary

IDall,

CVAX78034
VDD

vss~

TEST CONTROL
TEST CLOCK SOURCE

TEST
TCLLIN
ClKIN

TTL OSC

MCLKA.B

--

RESET
_ _ _ ROY
POWER UP
lOG'C

r-- 'S'YSERR

-00-

ASYNCHRONOUS
SYSTEM
INTERFACE

CVAX 78034
CPU

SYSRESET _
ERR

--SYSRDY

:

DMG

-OS

r - ACLKA. B. C

f-

CVAX78135
CLOCK CHIP

"-

f-

-

r.-

f--

CVAX 78134
FPA

-

....,.....

OTHER
SYNCHRONOUS
SUPPORT
CHIPS

NOTE:
TEST. TClICJN. SYSROY. SYSERR. RDY.
ANDERI' REQUIREPULL,UP RESISTORS.

Figure 38· CVAX78034 CPU System with CVAX 78135 Clock Generator

Strobe Termination
To eliminate interactions between the output strobes of the CVAX 78034 CPU" each strobe output
must be terminated with a series resistor. The strobe ouputs that requiring resistors are AS, DS,
DEE, WR, DPE, CSDP<3:0>, andCWB. The resistor value should befrom200 to 470, however,
the value depends on the layout and loading of each strobe. The resistor value selected should
dampen the transmission line reflections. A IOn series resistor reduces a glitch by approximately
1.0 volt. The terminating resistors should be connected as close to the signal pin as possible.
Bus Cycles
The CVAX CPU performs a bus cycle when

• Reading or writing information to or from memory, a peripheral device, or an externally
implemented processor register.
• Acknowledging an interrupt and reading a device interrupt vector.
• Transferring information from or to the CVAX 78134 FPA.

1-60

Confidential and Proprietary

Preliminary:.

CVAX78034

.Figure 39 shows the bus connections used by the CVAXCPU .

.

INTE~.RIIPT

CONTROL

{

r;:.JAX 78034

CENTRAL PROCESSOR
UN I"

DMA
{
CONTROL

.

CACHE MEMORY
AND WR!TE BUfFEIl {
CONTROL
CPSTA<'l :0> t-..,...,..,.-.,-..;....,..;.......,
CPDAT<.5:q> .......,.--,-.,....,...,.,...,..

Figure 39· CVAX 78034 CPU Blls Connections
A micro cycle is the basic timing unit for a bus cycle. A microcycle is defined as four dock phases (Pi
through P4) as shown in Figure 40. Detailed timing information for the following bus cycles is
contained in the ac Electrical Characteristics.

ClKA

eL.KS

Figure 40· CVAX 78034 Microcycle

Confidential andProptietary

1-61

Preliminary
Idle cycle-An idle cycle requires one microcyde. During an idle cycle, DAL<31:00> are
undefined and the bus control signals are not asserted.
Single transfer CPU read cycle-During a single transfer CPU read cycle, shown in Figure 41, the
CPU reads a minimum of one Iongworcl from maih memory or from an 1/0 device. A single transfer

CPU read cycle requires two or more microcycles. Additional microcyc1es are always in increments
of a microcycle. The 'sequence of events is

1. The CPU transfers the physicallongword address onto DAL < 29:02 > . DAL <31:30> are set to
01 to indicate a single longword transfer.
2. B,'vl < 3:0 > and CSDP< 3:0 > are asserted as required and Wit is negated.
3. The CPU asserts AS indicating that the physical address, BM < 3:0 > , "'C""S""D""p:-'<--"'3""':0:->-, and WR
are valid and can be latched.

4. The CPU asserts DBE to enable the external interface to drive the DAL and asserts DS to indicate
that DAL are available to receive the incoming data.
5. The CPU checks for a complete cycle once every two dock phases statting at the next possibJe PI
edge. The three Responses are used by external logic to indicate to the CPU that the cycle is
complete are
a. If no error occurs, external logic places the required data on DAL < 31:00 > and parity
information on CSD < 3:0> , asserts DPE if DAL parity is to be checked, and asserts RDY with
ERR deasserted. The CPU reads the data and corresponding byte parity information from
DAL < 31;00 > and CSDP < 3:0 >. If a parity error occurs, the appropriate error information is
logged in the memory system error register, the CPU ignores the data on DAL < 31:00 >, and
generates a machine check if the cycle was a demand read cycle.
b. If an error occurs, external logic asserts ERR with RDY deasserted. The CPU ignores the data
on DAL < 31:00> and generates a machine check if the cycle was a demand read cycle. An error
will be recognized only if RDY is deasserted for two consecutive PI sample points. If the error
response (ERR asserted and RDY deasserted) is detected at the first PI sample point, but RDY is
asserted at the second PI sample point, the cycle will terminate according to the retry protocol.
c. External logic can request a retry of the cycle by asserting RDY and EHR. Retrying a read cycle
can eliminate deadlocks on the DAt because the CPU guarantees that bus arbitration occurs
before the cycle is restarted (DMG will be granted if DMR is asserted). Certain request read
cycles will not reissue a bus cycle if they are retried. Specifically,if the retry occurs on a prefetch
reference, the operation may not be reissued because the CPU may execute a branch operation
before the prefetch can be retried.
6 The CPU completes the cycle by deasserting DS, DEE and AS.

1-62

Confidential and Proprietary

CVAX78C)j4

Preliminary
,,

PI

P3

I

-":'-"-'-M!CAOC'rt:lE--~

!-----MiCROCYClE--·

PI

P3

I

elM

ClI

Figure 41 • CE4X 78034 Siiigle .Tral1sjerCPU Read Cycle

Multiple transfer CPU read cycle-During multiple transfer CPU read cycles shown in Figure 42,
the CPU reads two longwords (one quadword) from main memory. A multiple transfer CPU read
cycle requires a minimum of three microc:ycles. Each longword transfer may be increased in
increments of one micrO(:ycle. IIO space read references always occur as single transfer read cycles.
The sequence of events for a multiple transfer CPU read cycle is

1. The CPU transfers the physical address of the preferred longword that is to be accessed onto
DAL < 29:02 >. This address can be aligned with either of the longword addresses within the
quadword block. DAL< 31:30> are set to 10 to indicate a quadword transfer. The CPU sends an
address only on the initiallongword (preferred) transfer of a multiple transfer read cycle. The
address associated with the second (cache fill) transfer is implied and therefore is not transferred
by the CPU. External logic can generate the implied address by inverting address bit 02 of the
preferred address. All references, therefore, remain within a quadword block. For example, if
the initial Iongword address in a quadword transfer is 0007FB36 (hexadecimal), the implied
address is 0007FB32.
Confidential and Proprietary

1-63

Preliminary
2. BM < 3:0> and CSDP <.3:0> are asserted and WR is not asserted.
3. Tne CPU asserts AS to indicate that the physical address, BM < 3:0>, CSDP<3:0 > and WR
are valid and can be latched.
4. The CPU asserts DBE to indicate that the external interface can transfer information onto
DAL < 31:00 > . DBE is not asserted b(~tween each data transfer.
5. The CPU asserts DS for each data transfer to indicate that DAL < 31:00 > are available to receive
incoming data.
6. The CPU checks for a complete cycle after each longword transfer. This check is performed once
every micro cycle at the first PI edge after DS is asserted for .each transfer. The response by the
external logic is
a. If no error occurs, external logic places the required data onDAL<31:00> and parity
information on CSDP < 3:0 >, asserts DPE if DAL parity is to be checked, asserts CCTL if data
caching is to be prevented, and asserts RDY with EmR deasserted for each transfer. The CPU
reads the data from the OAL lines and the corresponding byte parity information from
CSDP < 3:0> and deasserts DS. If data caching was not prevented (CCTL deasserted), the CPU
continues on to read the next longword by reasserting ITS. If data caching is prevented, the cycle
immediately terminates without reading the second longword of data. If a parity error occurs,
the appropriate error information is logged into the MSER register, the CPU ignores the data on
DAL<31:00> and generates a machine check if the cycle was a demand read cycle. If a DAL
parity error is detected on the first longword transfer, the CPU will perform the second data
transfer and ignore the data.
b. If an error occurs during either data transfer, external logic asserts ERR with RDY deasserted.
The CPU ignores the data on DAL < 31:00;>, terbiinates the cycle\vithout reading any
additional data, and generates a machine check if the cycle was a demand read cycle. Only the
first transfer can be a demand cycle. An error will be recog{lized only if·RDY is deasserted for
two consecutive PI sampk points. If the error response (ERR asserted and RDY deasserted) is
detected at the first PI sample point but RDY is asserted at the second PI sample point, the cycle
will terbiinate according to the retry protocol.
c. Tb request a retry, external logic asserts both RDY and ERR. Retrying a read cycle can
elibiinate DAL deadlocks because the CPU guarantees that bus arbitration occurs before the
cycle is restarted (BMG will be granted if DMR is asserted). If the retry occurs during the second
longword transfer, the read (:ycle will not be reissued.
7. The CPU completes the cycle by deasserting AS, DBE, and DS.

1-64

Confidential and Proprietary

CVAX78034
---M1CRIXYClE--+---MICROCYCLE----+---------,."C""""',,-----oi
Pl

!

f'3

Pl

PJ

OAt<31 ,00>

I

\

\

I

r-

I
,

X

"

,',

VAI.ID B'r7E MASKS

I

i

/

\

Figure 42· CVAX 78034 Multiple Tran;jer'CPU Read Cycle

Normally, a multiple transfer CPU read cycle reads two Iongwordsof data. However, the cycle
terminates after the first data transfer if ERR is ,asserted anqRQY isdeasser~ (memqty ~rrol;), or
if CCTL is asserted to prevent data cachipg. The cycle does nQt ,ter:minate ea,rly if a DAL parity error
is detected on the first transfer. Table 25 lists the possible multiple transfer cyclerespgnses.

'raMe25· CVAX 78034 Resporises toa MultipJeT....nsferCPU Read Cycle

Condition
CCTL' RDY

DAL parity
ERR
error

~tion

FirSt reference

Seconcl reference

X

H

H,

X

wait for data

wait for data

X

H

L

X

machine check if demand
invalidate cache entry
no second reference

no machine check'
invalidate cache'entry

H

L

H

H

no machine check
update cache
proceed to second reference

n()machine check
update cache

Confidential and Proprietary

1-65

CVAX780~4

Prelilllirutry
Condition
CCTL RDY

DAL parity
ERR
error

.Action
First reference

L

L

H

H

no machine check
invalidate cache entry
no second reference

no machine check
update cache

H

L

H

L

machine check if demand
invalidate cache entry
log error in MSER
proceed to second reference

no machine check
invalidate cache entry
log error in MSER

L

L

H

L

machine check if demand
invalidate cache entry
log error in MSER
no second reference

no machine check
invalidate cache entry
log error in MSER

x

L

L

x

no machine check
no cache change
no second reference-retry·

no machine check
invalidate cache entry
no retry

Second reference

X is either high or low level

CPU Write Cycle~During a CPU write cycle, shown in Figure 43, the CPU writes information to
main mem{)ry or to an I/O device. A CPU write cycle requires a minimum of two microcydes. Each
transfer can be increased in increments of one microcycle. The sequence of events for a CPU write
cycle is
1. The CPU chip transfers the physical Iongword address onto DAL< 29:02 >. DAL< 31:30 > are
set to 01 to indicate a longword transfer.
2. BM < 3:0> and CSDP <3:0> are asserted as required and WR is asserted.
3. The CPU asserts AS to indicate that the physical address, BM < 3:0> , ""'C""'SD=P-<""'3'-':0""'>:-, and WR
are valid and can be latched.
4. The CPU asserts DBE to indicate the write data can be ttansferred onto an external bus.
5. The CPU transfers the output data onto DAL <.31:00 > and byte parity information onto
CSDP < 3:0>, assertsi5J5E to indicate that valid parity information is available, and asserts DS
to indicate that the DAL contains valid data.

6. The CPU checksfor a completecyde once every two dockphalies starting at the next possible
P 1. The response of the extern~llogic is
a. If no error occurs, externilllogic reads the data from the'DAL< 31:00 > and asserts RDY with
ERR deassetted.
b. If an error occurs, external logic asserts ERR with RDY deasserted. Aborting a write cycle
generates a machine check External logic can report a DAL parity error by asserting ERR and
deasserting RpY An error will be ~cognized only if RDY is deasserted for two consecutive PI
samplepQints. If the error response ERR adserted and RDY deassertedl is detected at the first PI
sample point but RDY is asserted at the second PI sample point, the cyde will terminate
.
according to the retry protocol.
c. To request a retry, eXtel:nallogic asserts both RDYand ERR. DAL arbitration occurs after the
write operation is terminated.
.
7. The CPU completes the cycle by deasserting AS, DBE, and DS.

1·66

Confidential and Proprietary

.1 .,'...

....

.

~---MfCROCW:l(--I ·
, ' Pi ,," ,
;
'1'3

-+:-'. .' .
-

'.

. ---MICROCYCU:-.-'-. - ._
. .
1>"
' • "
. J'3

Figure 43· CVAX780J4

crqWritt(;yqk.'
,'_','

-

It':· ,\

~ ,<

External Processor Register Read Cycle-An external processort:egis'Eerreaaqc>leisinitiated
when a category 3 processor register (re!j::t to ]?rp ,atld DAL< 31:30 > are
set to 01 to indkiilte,long'Wotd transfer.
' .

2," BM<4:''):O>arealt ass€rtoo,CSDP<3;0jare~s$erted as requIred arldWR is unasserted .. '
3. The CPU asserts AS indicating that the register number,
are valid and can be latched.
' •. ;
4~,Th~

Cl?Uasserts DBEto indic~t(!thatiJ,"eIid,d;ifllcanbe
tP'lpefe.rn;:dcQJ;1totbeP4I,.
... ;
'"j'__
,',_., _ • ',.- ,
""" ',.
The CPU asserts DS to indicate that DAL llfeavailable ta'~ve ineoming.data.
The CPU checks for a complete cycle once every ;two dock: phase.<;rttthenext poSlliblePL The
J,"esponse of externallogicis
..
a. If the processor register is implemented, external logic/transfers ithe requireddata'on
DAL < 31:00:>, deasserts DPE, and assertsRDYwithERR:'deasserte,d; .·TheCPUreadsthed~ta
fromDAL<31:00>. ..
h. Iftheprocessorregistet is not implemented, externallogk assertSE'i:tR with R1'5Ydeasserted.
The CPI::l ighoresthe data on DAL <: Jl:{)O> and internalfyforcesthe result to zero. A detected
parity 'error will force the result to zero and isn6treport~d. Therefore, it isrecomm~tldedthat
",:

5.
6.

,
.'

BM<:5;:5:>',CSDP<'3:0:>,ahdWR

_,

0'

•

.'.

'__ " "

_'or

_:'-

'e"-

'._

,', ....

,_

.,

',',

"

_,-".

e,

"".,y.,"'<"--"

"

1-67

DPE remain deasserted during a processor register read. The unimplemented response will be
recognized only if RDY is deasserted for two consecutive PI sample points. If this response (ERR
asserted and RDY deasserted) is detected at the first.Pl sample point but RDYis as;erted at the
second PI sample point, the cycle will terminate according to the retry protocol.
c. To request a retry, external logic asserts bothRDY and ERR. DAL arbitration occurs after the
initial read cycle is terminated.

7. The CPU completes the cycle by deasserting AS, DBE, and DS.

External Processor Register Write Cycle-An external processor register write lycle is initiated
when a category 3 processor register (refer to Processor Registers) is written using.a MTPR
instruction. An external processor register write Cycle is the same as a CPU write cycle shown in
Figure 43. This cycle requires a minimum of two microcycles and may be extended in increments of
one microcycle. The sequenceaf events for an external processor register write cycle is

1. The CPU transfers the processor register number ontoDAL < 07 :02> and DAL < 31 :30 > are
set to 01 to indicate a longword transfer.
2. BM< }:o > are all asserted, CSDP< 3:0> are asserted as required, and 'WR is asserted.
3. The CPU asserts AS to indicate that tht register number, EM < 3:0> , CSDP < 3:0> and WR
are valid and can be latched.

4. The CPU asserts DEE to indicate that the data to be written can be transferred onto an external
bus.
5. The CPU transfers the data onto DAL<.31:00> and asserts DS to indicate that the DAL
contains valid data.
6. The CPU checks for a complete cycle once every two clock phases, starting at the next possible
Pl. The response of the external logic is
a. If the processor register is implemented, external logic reads the data from DAL and asserts
RDY while ERR is deasserted.
b. If the processor register is not implemented, external
logic either responds as if the register isimpletnented by asserting ERR when RDY is deasserted.
Both responses have the ·samedfect and no special action is taken. The unimpleme1'lted
response initiates no special action only ifRDY isdeasserted for two consecutive PI· sample
points. If this response is detected at the fjrst·Pl sample point,butRDY is Asserted at the
second PI sample point, the cycle will terminate according to the retrypro~()cQl.
c. To request a retry, external logic asserts both RDY and ERR. DAL atbitration occurs after the
initial write cycle is terminated.
7. The CPU completes the cycle by deasserting AS, DBE, and DS.
Interrupt Acknowledge Cycle-An ihterrupt acknowledge cycle· sequence is similar to a single

transfer CPU read cycle shown in Figure 41. The sequence of events is
1.·DAL<06:02> transfers the IPL of the interrupt being acknowledged with IPL ·17, IPL 16, IPL
15 and IPL 14 as IRQ3, IRQ2, IRQl, and IRQO, respectively. DAL<31:30> are set to 01, and
DAL<29:07> andDAL < 01;00 > are sett.o zeros.
2. The data read is used to generate the vector and new IPL for the interrupt sequence. Bits 15:02
of the incoming data are used to create the vector offset within the system <:;onttol block. The
new pr9Cessor .statU$ Iongword priority level is de~eJ;tp,ined either by the externaLinterrupt
request level that causedthe interrlJpt DF by bit 00 of the value supplied by ~xternal havQware: If
bit DO is 0, the new IPL is determined.by the interrupt reques.t levelbeing serviced. IRQ3 sets the

1-68

Confidential aoci Proprietary

PrelipUnmoy .
1PLto)7 (he:lU\dedmal) and IRQO to!PL 14 (hexadecimal). If bit 00 of the value supplied by
ext;emalhardware is 1, the new IPL is forced to 17 (hexadecimal}. Bits <31;16> and bit 01 of
the iru:om,ing data are ignored.
3. Assertion of ERR in the proper order with RDY causes.the bus cycle to be reissued or aborted.
An abort causes the DAL data to be ignored and the CPU continues.$ if ~he interrupt request
never OCcurred (passive release of the interrupt reque:>t). A,dctected DAL parity error also Causes
a passive release and is not reported. Therefore, it is recommend~ that WE remain dea,.sserted
durnganintemipt acknowledge c y c l e . ' .
'.
..

OMA Grant Cycle-The CPU can relinquish its control of the OAL bus and related contl:'91 signah
upon request from a DMA device or another CPU. Figure 44 shows the sequence of the DMA grant
cycle. The sequence is
1. The external dt;vicerequests control of the bus by asserting OMR.
2. At the conclusion of the current bus cycle, the CPU respo:nds by causing DAL < 31;00 >, AS, ns,
. WR, DBE,BM < 3 :0 > ,and CSDP < 3 :0> to become ahighimpedanoeand asserts DMG.
3. The external devieemay now use the nAL to transfer data.
4. To return control of DAL to the CPU; the external device deasserts DMR. The CPU responds by
deasserting DMG and starting the next bus cycle.
The CPU ensuresthat suocessive DMA requests (DMR asserted) cannot prevent all CPU activity. As
an example, one CVAX cycle oan 9<:<:Uf between tWQ.suc<:.cs.sive assertions of DMR.

------~\'rl------~~~'r'~

____________________________-Jr___

Figure 44 • CVAX 78034 DMA Grant Cycle

Cache Invalidate Cycles-External logic initiates a conditional oache invalidate cycle, shown in
Figures 45 and 46, to allow the CPU to detect and invalidate stale data that isstored.iri tnecache,A
conditional invalidate cycle uses ~ .minimum of three microcycies. The sequence of events for a
cache ·invalidate cycle is
1; After DMG is asserted by the CPU ,external logic asynchronously trartsfers the physical address
bnto· •DAL < 31:00>, asynohronously" asserts' AS to latch· the address into the CPU, and
asynchronouslyasserts.CCTt to start a conditional invalidate cYcle. .
2. The CPU invalidates the quadword cache entry s~lected by the DMA address
stored in the cache.
CQ~fidentiai and Proprietary

if the location is

1-69

Preliminar~

}, ExternallogicdeassertS cC'rt: atl:d optionally reasserts CCTL to conditionally invalidate the
alternate qlladword formed bY'inverting address bit 03 of the physical address, Thisal10ws
external logic to detect and invalidate stale data stored in any naturally alignedoctaworcL
4, The tycle ends when external logic deasserts bothASand CCTL

If a cache parity error is detected during the conditional invalidate operation, no machine check is
generated, no invalidate occurs, and the error is logged in the MSE:R,
The CPU detects and invalidates quadword stale data in three microcydes, Therefore, the
maximum cache invalidate rate cannot exceed 8-byte or three microcycles (nominally 26,6 Mbytes
persecorrd),

ClKA

ClKB

CCTI.

AS

--'X

DAl<:,3':OO> _ _ _ _ _ _ _

l)MAlI.DOFlESS

X. . .___--I~:\__________JX

~;~~~~A

Figure 45· CVilX78034 Quadword CaeheInvalidate Cyete

£~~~(<.-~

"1

.J\\

X

X

~---------------4~--~!

I'

t,:

',\

\'~------------------~'~.

------

-----

~------------------~\'~,

IJI)

Figure 46· CVAX 780}4 Oetaword Cache Invalidate Cycle
Coprocessor Protocols
Coprocessor protocols are used by the CVAX CPU when communicating with the bptionalCVAX
78134 FPA (CFPA), These devices communicate with each other through the CPSTA <1:0 :>and
CPO!\l';<5:0 > lines andD,AL<:31:00> A~PSTA< LO > inform the CPU or (:FPA orithe method
of interpretation of the CPDAT <5 :0> information. The CPDAT < 5;0 > lines transfer opcode and
control information to the CEPA an,d, return condition code and exception status to the. CPU,
DAL <31:00 > are used to transfer operands and r~sults:,

Confidential and Proprietary

...

Preliminaty

The protocol for the transfer of information between the two devices is

1. The CPU sends the opeode for the instruction to be executed and the operand(s) to the CFPA.
2. The CPU waits for the CFPA to complete the instruction. DMA devices may be granted use of
DAL < 31:00 > and its associated control signals while the CPU wllits.
3. The CFPA notifies the CPU that the result is ready, Condition codesianderror information are
transferred on CPDAT < 5: 0> lines by the FPA.

4 The CFPA transfers any results of the complttation through HAL < 31:0G> during consecutive
microCfdes.
5 . When the operation is complete, the CPU causend anotheropcode 1''0 theGFPA.

Opcode Transfer ...../fhe CPOtransfets opcod~informai:ioh toftbeCFPA'whenthet~ is ready to
execute an instructi~n.The tra~sfer cydeis shb\vn in Figuie47. Th~ CPUtra~erlsixl&v~6raer
bits oftl1e opcodeonto the CPDAT<5:0> lines and the opcode type (F,D, G floaHngdiiriteger),
onto the CFSTA< 1:0 >: lines.

p,

p,

PI

p,

C,KA

CU lines to 00 to indicate that the operation is encoded on
CPDAT<5:0>.
2. The CPU transfers information related to the operand transfer onto CPDAT < 5:0 >. The line
information is
CPDAT Line Description
<5:4>

Address alignment code. These are zeros when the operand originates from
general registers. They transfer the two low·order address bits of the reference
when the operand originates from cache or external memory.

3

ofor an operand transfel~
Confidential and Protlrietary

1·71

Preliminary
CPDAT Line
2

Description
0 when PSL 06 is cleared
1 when PSL6 is., set

1

0 for no action
1 when DAL< 31:00 > contains the operand
o
0 for no action
1 when DAL < 05 :00> is a short literal (DAL < 31:06 > are.zeros.
3. The operand is transferred to the CFPA on DAL < 31:00 >. The CFPA aligns all unaligned data.
When the operand originates from external memory (AS asserted), the, CFPA reads
DAL < )1:00 > according to the full memory read protocol (RDY and/or ;ERR ass(!rt~d). W4en
the operand~riginatesfroll1the general registers OJ;' internal cach~ memory of the CPU, thl.! data
is tp-ns£erred onto DAL< 31:00> .at P3 of the cycle and samJ?led by the FPA at the next PI. .
4. If a parity error is detected by the CPU when the source of the operand is dtherthe internal
cache memory or external memory, it aborts the FPA operation. The CPU aborts the operation
by not informing the CFPA of the current result. The CFPA is reset when the CPU sends a new
opcode.

.,

.3

P1

P3

CLKA

.,

crSTA

DAL<31:00>

P2

"

cu::s

A
X
X

A
OPERAND ON OAl

OPERAND

X
X

Figure 48 • CVAX 78034 Single-precision CPU to CFPA Transfer'

1-72

Confidential and Proprietary

maIIi

Prelilmnary'·

~

CPSTA<1 :0>

CPDAT

DAl<31:00>

I.
,I

X

OPERAND ON DAL

X

FIRSTOPERANO

,

<-

;/

X
'1

X

x:

OPERAND ON OM

.K

X

SECPNO Of ERANO
~

! '

)(
X

: Ie

-

~:

:

CFPA Re~t Tran~fer-After receiving
opsodean4o~ef~~a~,>h~ :CFPA,.e~ecutesthe
instruction and tr~nsfers condition codes, status informa.tion, and result ()f the computadon to. the
CPU. Figure 50shawsv a single-precision~t~PA 't~t:'P"lJtrans£er; andFig~l1'e '51 shoWs .;t. doubleprecision CFPA to CPt! transfer.' Theprotocoi'fcrthe transfeds"
.;
. , .

the

1. When the CPU is ready for a result it set the CPSTA < 1:0> lines to zero ~d the cPDAnline to
1. Ownership of CPSTA < 1:0> and CPDAT < 5:0> lines is then transferred to the CFPA. The
DAL<31:00> are set to a high-impedan(':elltllte at thell~t P2 edge,

2. The CFPAgains ownership of the CPSTA< 1:0> and CPDA! <5:0 > lines bytransf~tring zeros
on lines .CPSTA < 1:0,> indicating that the. result is not ready aQ,dundefinec:t- during the next P3e.age: The'\<;;'PPA continues" to transfer zeros on
CPSTA < 1:0 > at.ea~h P3 edge. The.CPUco1}tinl,l.o.~ly monitors the CPSTA < 1:0>1ines until a
lLis present iridrcating thatthe result is ready. While waiiirlg tQr the CFPA to teturn the result
ready condition, the CPU can grant .use,.of the DA,L andit$ associ~tedcontl\)l signals (DMG
asserted) to a DMA device .. TheCPUaSsert.g.BMGon,aP4 :edge.andstops sampling
CPSTA < 1:0> until.it deas;;erts DMG.
3. The CFPA sets the CPS'fA<'l:O:> t~ 11 andtransfe;s condition codes and status infortrr'ation on
Hnes·· CPDAT< 5-:0 > on·the next· P:3 edge; If a DMAcyc,l.eis- in progress 'Or is granted on the
following P4 edge, the CFPA repeats the response until DMG it!'deasserted.
4. The CPU reads the CflDAT < 5 :(l> information to determine the response of the FPA, and a
DMA request is not granted until the end of the operation. '!Pe CPDAT < 5:0> lines are
encoded as follows: .
'
.
. '
CPDAT Line

Description

5

0 if the result clears the N bit of the PSL
1 if the result sets the N bit of the PSL

4

0 if the result clears the Z bit of the PSL
1 if the result sets the Z bit of the PSL

3

0 if the result clears the V bit of the PSL
1 if the result sets the V bit of the PSL (integer overflow/ACB condition met)

Confic:lential and Propl.'letary

1-73

PrelimID~ ," t

<2:0> . .

These
bits define.,the
status of the information
"
';
' r
COde

Status

Data transfer

0.00
.001 ,
01.0

protocol error .
reserved opcode
reserved operand trap
diY-ide by zero
floating-point overflow
.floating"pointunderflow
reserved-prdtocol error
no error

abotted
aborted
aborted
aborted
aborted
aborted
aborted
.continue

'011

100
101
.' 11.0

III

The results are transferred on DAL< 31:.00 > in consecutive microcydes immediately following
the return, of the condition codes . ..fIt single unaligned longword is transferred. for a singleprecision result (F floating) and two unaligned longwords are transferred for a double-precision
result (D or G floating). The CPU aligns the data and performs the final transfer if the
destination of the data is memory.
.

If CPDAT < 2:.0 > indicate a protocol error, reserved opcode, reserved operand trap, divide by
zero, floating-point overflow or underflow, no data is transferred. The CFPA will not return a
£loating~pointundetflow error ifpSL6 is dear.

.,

..,

5. TheCFPA sets the CPSTA< 1:0> and CPDAT<5:0> lines toa pigh-impedance state on the
ne.~t P2 edge. The CPU gains control of CPSTA < 1:0 > an~ CPDAT < 5:.0 > on the following P3
edge to complete the transfer.
. '

u,.,

r--.....,,--/,.
' ..~
. . "--/j4
Pl . . .,'.,.,

...I

•

P2'.

".

1-\'~,_,
.~
... ~,~
~',

elKS.

CP~'-!\

___

~

'---.J \-_ _ _ _ _ _ _-{
___-,.......Il'

7\\

~~G
1__
r
- __CVM1~DALC~DA;_'
"-.NO CPSYA MASTER

_._

J.

--,

L.':'.

~

_. CFPAISCPDA;A.ND_. _ _'~+-"-· _C~f>AtSOAL.crDAT_'J

.

Cf'STA MASTER

.

AND CPST4 MASTER

.l

z..igure 50 ~ CVAX 78034 Si';gle-p~cision OPA to CPU Transfer
,:'

1-74

Confidential and Proprietary

,'L

'

Preliirrinary
;;t.AA

. ~.'
"....,'.:
"_"'_'_.~'
...".' .. ' 'r.
.
~' " ;;'---/
Pl

J

f':l

~,,~.
.

DM(;

--"

.

--------"
Figt,lre
51· CVAX:
78034
[)Qtf/?je-prec.i,~iQnC:FP(l,tQ,
C['U
,
'
_'
,"
';,,' ._:J -, '
___ '",:.'
",'~,

_~I.

;""

Mupsfi.en

•. ;_'_~~ __

.,

Memory Access Protocol
The 28-bit address provided by the CVAX CPU on DAL < 29:02 > is a long:worJad to facilitate byte accesses within 32-01t memoryloc~tioris: The CPU
imposes no restrictions on data alignment. Any data itemregardlcss of size maYistart'at' (!'lily
memory address except for the aligned operands of ADAWI and the interlocked queue instructions.
Memory is viewed as four parallel 8-bit banks each of which receives,~lpng\\lOnhaddress
DAL <29;02, >, .• in,paralkL Each,blilnk,reIWs{)!, wtitesone !;;yt'¢ oi,the:,data f1'0mJJ)}tk~3~;OO(>'
when its byte mask signal is asserted. Figure 52 shows the memory organization.

Figure 52· CVAX 78034 Memory Organization

1-15

Any CPU read or write operation c:;m be a byte.access, word access within a longword, ""ord access
across Iongwords, aligned !ongword access, or umiligned lo~gword access; Quadword accesses are
performed as two successive longword accesses with no optimization. Byte accesses, word accesses
within a Iongword, and aligned Iongword accesses require one bus cycle. Word accesses that cross a
l()ngword bovndary and unaligned longwordaccesses}t:quire two bus·cycles.

I-stteam Prefetching
TheCVAX CPU contains a 12-byte I-stream prefetch buffer organized as three aligned Iongwords.
The CPU generates an I~stream prefetch cycle when an aligned longword in the buffer is empty. At
any time the CPtJcan use up to a maximum of 6 bytes from the pre fetch buffer.

. Specifications
The mechanical, electrical, and envirol1mental specifications of the CVAX 78034 are contained in
the following paragraphs. The test conditions for the values specified are listed as follows unless
indicated otherwise_

~PoWer supply voltage (Voo ):/f.r5V

• Ground (Vss): 0

Meehanital Configuration
The physidYdimensionsof the CVAX 78034 CPU 84-pinsurfacemount package are contained in
the Appendix.

Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may ~ause permanent damage to the device.
Exposure:to the absolute maximum i-atingsfor extended periods of time may adversely affect the
reliability of the device.
• Storage ~emperature range (1~): -55°C to 125°C

• Power supply voltage (VOD ): -O.5V to 7.6V
• Input or output voltage applied: -1.0 V to 7.0 V
Recomm~ded

Operating Conditions

• Power

voltage (VDD ): 4.75 V to 5.25 V

1-.76

Preliminary
de Elec:trieal Characteristics
Thedtinputand output parameters are listed in 1i1ble 26.

High-l~el input
voltage (TTL),
•

Vti.

c-

v

2.0

I

Low-Ievd:injilUt

voltage. (TTL)
High-level output
voltl1ge(MOS} ,

Low-leVel output
voltage (M6s) ',. '
High~level

v

input

voltage (MOS)
, " " ' . • "._.,1

VtLM

Low-level input
voltage (MOS)

30% Von

High-level output

v
v.

2.4

IoH=-4QOvA

'101tage

v

Low-Ieveloutput.voltage
(all pins except DRE)
DBEpin

.' -10

Input leakage current
Output leakage current

0< Vin

10

-10

Active supply current

*

OJy to Figures 53 through 67 and their a.ssociatedtirn~g
table,$;
>,'" ".; , "'. "',
,

,

:

i

.

,.;,",-',' _""

'j"

:

• All times are in nanoseconds (ns) except wh¢'~ooted.
• Cto..l=d30pF (exceptior CPDAT <5:0> andCPSTA< 1:0»

• ac highsfor MOS inputs are measured at VIIlM and lows are measured at V1LM •

'

• ac highs for MOS outputs are measured at VOaM and lows are measured at VOLM '
• ac highs for TTL inputs are measured at 'Vra and lows are measured at 'VrL.

ConfJdential and Proprietary ,

1-77

PrelilTlittary ... '. .
• ac highs for TTL outputs are measured at VOH and lows are measured,at VOL'

• MOS inputs are driven to V".M or VOHM~ndT'tL input~ aredrl~~nto VOL orV~H'
-RDY and ERR sampling is performed by the CPU to determine if one of the following bus cycles
is to be completed: cpu riaci cyde, irtterrtiptacknowledge cycle, mt11tiple transfer CPU read
cycle, al?d aCPU writecycIe. If RDY orER~ is not asserted during the sampling windoWithe
bus cy~le is extended in increments of one microcycle lIntil RDY or ERR are asserted. The
following restrictions apply to the assertion and deassertion of RDY or ERR with respect to the
sampling window.

-Only a high to low transition (assertion) is allowed on RDY or ERR during a P4 that is part of
the sampling window. If the assertion of RDY or ERR meets setup time t sws , the CPU
recognizes the assertion of the signal. The result of a low-to-high transition (deassertion) of
either of these signals during P4 is unpredictable.

-If RDY or ERR is to be recognized by the CPU as deasserted, the signal must be dttasserted prior
to the P4 that starts the sampling window and held deasserted through the sampling window.
-RDY and ERR can be asserted prior toP4 that starts the sampling window and rem'ain asserted
through the sampling window if they are to be recognized by the CPU as asserted.
Clock Timing-Figure 53 shows the timing symbols used to define theCLKA and CLKB clock
inputs. The timing parameters are defined in lable 27.

CLKA

elKS

Figure 53· CVAX 78034 Clock Input Timing

Thble 27 • CVAX 78034 Oock Timing Paramete!,~
Symbol

Requirements (ns)

Definition

Min.

Max.

tCLKOL'

CLKA to CLKB delay

tc Y

HAlT,

--------------------------------------~__i~~--~----------~-----------

~Fi.

...J"-_ _ _ _ _ _.........._ _ _ __

CI>$TA<10::.,
r.f'DAT<:5:0> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Figure 55 • CVAX 78034 Clear Write Buffer and Test Signal Timing

Table 29· CVAX 78034 Clear Write Buffer and TEST Signal Parameters

Symbol

Deftnition '"

Requirements (ns)
Max.
Min.

t TESTD

CWBdrive

0

t TESTH

CWB'hold.

0

tm

Test input hql~

5,0

t TS

Test input setup

10

.32

External Interrupt Timing
"
Figure 56 shows external interrupt timing sequence, and Table 30 lists the timing parameters •

.,

.3

.
,

Figure 56· CVAX 78034 External Interrupt Input Timing

Confidential and Proprietary

-

.

. ,.

...

•....

Table )Oi "CVAX 78034 ''EXternal InterruPttn~t TiRUrig ~rs
RequiFeinen~(ns)
Min.
Max.

Symbol
CCTL width during cache invalidates

4:CTLW

Asynchronous input fall time

15

Asynchronous input hold
Asynchronous input ri5<: time
Asynchronoulinputs~tup

t SYNS

15

l' . .

"IRQ < 3:0 > are level sensitive and must be asserte~f6ra's(':tlip(t~Yl!I8)~~a' hdld time
the end P2 to assUre recognition.
.
..

of

(tSyNHJ nef,ir

Low going pulses that OCcur outside the setup and holq; '¥~tjq~:aJ:enptJ·I,:.;;ognj.zed:
MEMERR, eRD, PWRFL, INTTIM, and HAlT areec\ges71!s~d~.ThetransitiQn fmmdeasserted
to asserted must occur one setup time (tSYNS ) be£ore'the e:ndofl?2·t'i:rassti~ re~ognitiol1; otherwise,
recognition is delayed one microcyc1e.

External nMA. Timing
Figure 57. ~ws the' til11ingsequence .' fort4e
parameters.

ex~.ern~. DM!.signqig,

:Thblf:; ·. 31listl> the Hmil'1g

. Figure 57- (,VAX 780J4ExtefflalfJMA Thning·

Symbol

tDALHlZ

Requirements (ns)

DAL hig,h-impedance delay
DAL active drive delay

tDMGSDI

Min.

Max.

o
o

20
20

DMG strobe a~sertion delay
DMG strobedeassertion delay

tOSOlY

DS delay froJ:]1receiving DMG

t SH1•Z

:S,trobe,high-impedance delay
Asynchronous input fall time
Asynchronousinput hold

15

.As~nchronous i~put rise time

tSZHL

Asynchronous input setup

15

Strobe active drive delay

0

4\J

mMG is asserted at P4 whenDMRis asserted eight phases ea:rlier and no CPU 110 cyCle has slarted.
2DMG is deasserted at P3 when DMR is deasserted seven phases earlier.

and t SYNH are the setup and hold times needed at a synchronizer to ensure that a signal is
recognized by the CPU as expected.

3t SYNS

Cache Invalidate Timing
Figure 58 shows the timing sequence for a quadword cache invalidate cycle and Figure 59 shows the
timing sequence for a octaword cache invalidate cycle. Table.32 lists the timing parameters.

CLi

_ _ _ _ _ _ _ _.J

Figure 58· CVAX 78034 Quadword Cache Invalidate Cycle Timing

1-82

X

1'-----.11" '-_ _ _ _..... \-_ _ _ _ _ _ _ _..J.

•

NE:XT DMA
ADDR'SS

Figu,re 59 .. CVAX· 78034 OctawordCachelnvalidate Cycle Timing .

SynibOl

Definidon*
D~L hold during cache .invaHdiites

Requttements{ns)
Min.
····;2Cj'··

Max.

20

20
tCCTLCVC

CCTL cycle 'time during octaword invalidates

6
"

; ".,.-

.. t SVNS

tCCTLW

Asynchronous input hold

15

Asynchronous input setup

15

+ t SYNH
-

- ",""."

'2 X !cYCLE - tCLKH (max.) + t SYNS - tCCTLADRS'
2t ASH is measured from the third P4 that follows recognition of CCTL. On octaword invalidate
cycles, it is measured from the third P4 that follows the second CCTL.
3tCCTLCYC - 2 x t ASDLY + t ASWQ + tASDLY (max.).
44 X !cVCLE+tCCTLADRs+tAsn+tAsDLY (max.) - t ASDLy •
'tCCTtADRS is measured from the P4 that follows the recognition of CCTL. On octaword invalidate
cycles, it is measured from the first recognition of CCi'L.

'6 x

tC\'CLE

+ t SYNS + t SYNH '

'tSYNS and t SYNH are the setup and hold times needed at a synchronizer to ensure a signal is recognized
by the CPU as expected.

Read and Write Timing
Figure 60 shows the timing sequence for a single-transfer read and interrupt cycle, Figure 61 shows
the timing sequence for a multiple-transfer read bus cycle, and Figure 62 shows the timing
sequence for CPU write bus cycle. Table 331ists the read and write cycle timing parameters.

Figure 60· CVAX 78034 Single-transfer Read andTnterrupt Bus Cycle Timing

1-84

Confidel1tial and Proprietary

:t:L'KA,

w:.

DAL<31:QO>

cs DP<,3:0~

_ _ _ _)"---~

Figure 61 • CVAX 78034 Multiple-transfer Read BUJ Cycle Timing

Conficlentialand Proprietary

h85

CVAX78934

Preliminary'

CtKB

DAL

os

Figure 62 • CE4X 78034 CPU Write Bus Cycle Timing

Thble 33 . CVAX 78034 Read and Write Bus Cycle Timing Parameters
Symbol

Definition

Requirements (ns)
Min.
Max.

t ASD

AS strobe assertion delay

0

15

t ASlD

AS strobe deassertion delay

()

20

tnMH

BM and WR hold

0

toAU)

DAL drive

0

tOAtH

DALhold

-.-----

5.0
..

20
-------------

20

tOALHLZ

DAL high-impedance delay

0

tOH

DALhold

5.0

tops

Parity setup

20

t DS

DAL setup

25

toso

DS strobe assertion delay

0

20

t"$10

DS strobe deassertion delay

0

18

1-86

Confidential and Proprietary

-----

Symbol

Definition

Requirements (ns)

Min.

t SWDS

Max.

DAL high impedance

tCYCLE

DP drive

0

DPhold

Q

General strobe assertion delay

()

20

Strobe·deassertiotJ.'c1e1at'

0

20

RDYand ERR deasserti';n set~p .

taKH

RDyand ERR sal11plt;~\Vindow hold.

5.0

tSWLMAX

RDY and ERR maximum assertion time

t sws

RDY andERE{ sample~window setUp

35

40

Coprocessor Timing
These following specifications are in effect when the CVAX 78034 CPU is operating with the CVAX
781.34 floating-point accelerator (CFPA) l;oprocessot.Figure 63 shows the timi;ngseqvence for the
operand trahsfer cycle. Figure 64 shows the·CPU to CFPktitning sequence for single-precision
transfers, and Figure 65 shows the CPU ~o CEPA timingsequ~nce for siouble-precisiontransfers.
Figures 66 and 67 sho\y the CFPA toCVAX CPU singJe-(iod doublt:·.ere~lsion transf(,:rs, respectively.
Table 34 lists the coprocessor timing parameters.

I.

EXECUTION OF N E W - 1
1--.-- - - v A X INSTRucnON
BEGINS

Figure 63· CVAX 78034 Operand Transfer Cycle Timi11g

1-87

,.--------------~---------------.------~"""""'-----------..-..~~-,

Preliminary, .
P3

P1

p,

CLKA

CLKB

CPSTA<1:0>

CPDAT<5:0>

DAl<31:QO>

Figure 64 • CVAX 780)4 Single-precision (PU to CFPA Transfer Timing

CLI

CPDAT<5.0>

DAL<31:00>

Figure 65· CVAX 78034 Double-precision CPU to CFPA Transfer Timing

1-88

Confidential and Proprietary

,
..

elK.<

eLKS

CPST.... <1:0>

CP[)AT

READY

FOfI

RESULT;

--I}---Il-----------<

""'.<31 00> _ _ _ _ _ _ _ _ _ _ _

OMG

_ _ _ _ _ _ _ _ _ _./ I',

_J
~.----CV4XISDAl.CPDAT--MASTER

r-

~

MDCPSTA

r-

L __________ CFfIC\.!S CPOAT AND _ _ _.+.__ CFPA IS DAl. CPOAl _,--1
~CPSTAMASTf.R

ANOCpsrA""A5TER~

OJIV,IS""L
CI"OAT.AND

CPS1A MASTER

-1

Figure 66· CVAX 780)4 Single-precision CFPA to CPU Transfer Timing

VJ

1"1

Pl

r~J

~" --if\---t~
...... 1
CLt

-,~..,

~

,-:::......

'LJ

'----J!
''''''-1
---r

,~
~

Icf'OHI....

__________~~r---------~L=~____~
"" ----------/',
Figure 67· CVAX 780)4 Double-precision CFPA to CPU Transfer Timing

Table 34 • CVAX 78034 Coprocessor Timing Parameters

Symbol

Definition

Requirements (ns)

Min.

Max.

20

Coprocessor line hold

o
o

Coprocessor line hold

23

Coprocessor high-impedance delay

o

Coprocessor line setup

23

Coprocessor line drive

Confidential andPI'Op1iietary

20

1·89

Symbol

to:~LH

DefiI?Jtion

Requitements (ns)

Min.

Max:'

DALdri~~ .

o

20

DALhold·.

o

20

DALhoid

5,0

DALsetup'

25

Confidential and Proprietary

. Features. ,
• High-performance, floating-point processor for use with the CVAX 78034 CPU
• VA,'{ floating-point instruction set (70 instructions)

• Processes VAX integer data types
-byte
-word
-Iongword
• Processes standard VAX floating-point data types
-single-precision" (E_Jloating)
-double-precision (D_floating)
-extended range double precision (G...Jloating)
• Enhanced CP1) interface
• Single 5-~olt pow~r supply

. Description
The CVAX 78134 Floating-point Accelerator (CFPA) is a high-peliformance coprocessor for use with
the CVAX 78034 Central Processing Unit (CVAXCPU). The primary purposeofthe FPA is to
acceleratf~ the execution of floating-point instructions by eliminating the ne~d taewulate them in
software. TheCFPA handles single-precision, double-precision, and ext~ded:l1Mge, doubleprecision, floating· point data types. The CFPA supports floating-point add, subtract, multiply,
divide, convert, and otbet.floating-roin(operatio,{).$,:Itmbacc:t:tet"ates.the execution of integer
multiply and divide operations £odon~~ord$pqly.Fi&L'\r(:J is a block. diagram of the CFPA.

MUl,npUER
DECODe

MULTIPLIER
REGISTERS

SIGN

PnoCE&...¢>OF\
STATUSl.OG1C
f RAC110N-A\'U

E:XECUTION yNlT

SEQUENCER
t60x44

;

Figure 1 • CVAX 78134 Floating-pointAccelel'ator Block

Confidential and ;Ptopttewy

Diagram

-_

',"./;"
. _:ir;.,

.....•......•......... ,

II

!

"

.:Pin.and Signal De~riptjOfl$
This section provides a description of the input and output signals and power and ground
connections used by the CFPA. The signal pin assignments are identified in Figure 2 and
summarized in Table 1.

DAlO6 DALOB OAL 10 DAll 2

60 59 58 57 56 55 54 53

VDD

52 51

VSS

DAL 14 DAL 16 OALl B

50 49 48 47

46 45 44
OAl19

OALOS

61

43

OAL04

62

42

OAL20

DAL03

63

41

OAL21

DAL02 -

64

40

DAL22

DALOl

65

39

VSS

DALOO

66

38

VOD

VOO

67

37

VOO

VDD

68

36

VSS

35

DAL23

evAX 78134
FLOATING POINT ACCELERATOR
ICAVITY DOWN I

VSS

VSS
CPSTAO
C?STAl

4

CPOATO

34

OAL24

33 -

DAL2S

32

- DAL26

31

OAL27

CPDAT1

6

30

DAL2S

CPOAT2

'7

29

DAL29

CPOAT3

S

28

DAL30

CPOAT4

9
10 11 12 13 14 15 16 17

27

OAL31

VDD

CPOATS

18 19 20 21 22 23

24 25 26

eLKA

Figure 2· CVAX 78134 Pin Assignments

Table 1 • CVAX 78134 Pin and Signal Summary

Pin

Signal

Input/Output Definition/Function

27-35,40-43,
44-49,54-66

DAL< 31:00>

Input/Output Data/Address lines-Time-multiplexed data and
address lines used to transfer data between the
CFPA and the CVAX CPU and memoty.

18

Input

Address strobe-Monitored by· the CFPA to
determine if data is coming from CPU internal
cache or registers or from memory_

20

Input

Ready-Asserted by external logic to indicate
that valid data is on the DAL. The CFPA uses this
signal to detect valid memory data.

Confidential and Proprietary

-,
Pin

Signal

Input/OutpUt llefinition/Function

19

Input

. Error-Ali~erted by e4Cterna(logic to indicate
!lbnormal termination of the current bus cycle.
The CFPA ~ses this signal tOd~tect faUlty memorycydes.'

15

Input

Reset-Asserted to force the CFPA to its initial
powerup state.

21

Input

1)MA gl!~nt--1iJ~SigrulI, is

tored>by

tnricl
the
CFPA to detertnineif a DMA cycle)s progress ..

10"5

DPDAT< 5:0 >

Input/Output ·Copr\D~s¢.r) d$l.ta:linelk-Used,tatratiS£er
o~e,.contl'Otin£ottnati.6n;/rondition .'codes,
and~cep,tiQn sta.tus,bet~enthe GFPAanathe
C;VA!CPJ).

4,3

CPSTA

Input/OutputCoprocesSOt~statlls Iines~Used

16,17

CLKA,CLKB

Input

to notify the
'CPPA orCVAXiCPUofthe·type ofinfbrmation
present on CPDAT < 5:0> .

Clcicks.:....Suppl¥ baSitd~ titnibgto theCFPA.

cm are

CLKA and
nomirial 20-MHz, MOS
level, square-wave signals that are phase shifted
from each ,other by 180 degrees ..
13,14,37,38,
51,52,67,68

Vnn

Input '.

1,2,11,12
36,39,50,53

Vs•

Input

Ground~Ground reference.

23,22

TST

Input

Test 2 and Test l"::"Reserved for CFPA manufacturing test.

CVAXBus and Control
Data And Address Lines (DAL < 31:00 > )- These are bidirectional time-multiplexed lines used by
the CFPA toexthange data with the CVAX CPU. The CFPA receives operands from the CPU or
memory over DAL < 3.1:00 > .~d returns the results over these lines.. •
Address Strobe (AS)-This signal is used by the CFPA to determine if an operand is from the
internal registers or cache memory ofthe CVAX CPU or £romej(tetnafruel;Uory. When the operand
is from the internal registers or cache memory, the CPUdoesnor~~;t'~ d~dng the operand
transfer. When the operand isfrom externalmemory,tht! CPU asserts AS and the CFPA reads the
operand following the normal protocol for a CPU read bus cycle. .
Ready (RDY)-This signal is asserted by external logic to indicate that valid data is on
DAL < 3.1:00 > . Tl;te CFPAmorutors this:signal when an opera11Pcomes from external memory to
determine if valid data is on DAL < 31;00 > .
Error (ERR)-This signal is asserted by external logic to indicate abnormal termination of the
current bus cycle. The CFPA monitors this signal to detect bad memory references when an operand
comes from external memory.
.

CVAX~i18134
Note
RDY and ERR must be asserted synchronously with respect to the timing sampling point of the
CPPA and must not change during the sample window.
DMAGrant (DMG)-This signal is assel'tedby the CPU to grant control of the DAL and its
associated control signals to external logic. The CFPA monitors this signal to determine if a DMA
cycle is in progress.
Coprocessor Signals
Coprocessor Data Lines (CFDA! < 5:0 »-The CFPA uses these lines to receive opcode and
control information from the CPU and to return condition codes and exception status to the CPU.
The CVAX CPU drives these lines when it is not waiting for data to be returned from the CFPA. The
CFPA drives these lines after the CVAX CPU indicates it is ready for the result and until the CPPA
indicates status ready and DMG is not asserted. The CPDAT < 5:0> lines are sampled synchronously by the destination at the beginning of Pl.
Coprocessor Status lines (CPSTA < 1:0> )-These bidirectional lines are used by the FPA and CPU
to determine the interpretation of the contents of CPDAT < 5:0>. CPSTA < 1:0> are sampled
synchronously at the beginning of P1 and indicate the contents of CPDAT < 5:0> to the
destination processor.
Table 2 lists the function of the coprocessor status information from the CPU to the CFPA. Table 3
lists the function ofthecoprocessor status information from the CFPA to the CPU.

T!lble 2 • CVAX 78134 CPU to CFPA Status Line Information

CPSTA
<1:0>

Function

CPDAT
<5:0>

Description

00

Operation encoded on
CPDAT<5:0>'" .

<5:4>
3
2
1

Address alignment code
CPU ready for result
Floating underflow (PSL6)
Next floating-point operand is on
DAL< 3l:00 >
Next floating-point operand is a
short literal on DAL < 05 :00:> ;
DAL< 31:06 > are zeros.

o
01

Integer opcode
on CPDAT<5:0>

<5:0>

Integer opcode

10

F _/D_floating-point
opcode on CPDAT < 5:0 >

<5:0>

Floating-point opcode

11

G_floating-point
opcode on CPDAT < 5:0 >

<5:0>

Floating-point opcode

"Operand on bus (CPDATl = 1) and short literal (CPDATO= 1) are mutually exclusive.

1-94

Confidential and Proprietary

Table 3 • CVAX 78134 CFPA to CPU Status Line Information
CPSTA

CPDAT

Function

<1:0>

Description

<5:0>

00

Result not ready

01

illegal

10

illegal

11

Condition codes ready

reserved

5
4

.3
<2:0>

N condition code
Z condition code
VCMdirion code "or ACBf branch
Status code as follows:
000 protocoleri:6r·
00 1 illegal qpcode
010 reserved operand trap
011 divide by zero
100 floating-poim overflow
101 floating-point underflow
110 reserved (error)
111 no fatal error

Power and Clocks
Care must be taken to connect tbe power and ground pirrswitbtheshortest wires or powerplane
possible.
Voltage (VDD )-5-volt power supply.
Ground (Vss)-Ground referent.'e.
Clock A In and Clock B In (CLKA,CLKB)- These inputs provide the basic clock timing to the
CFPA. CtKA and CLKB are nominally LO-MHz, KmS-level,"square-wavesignals that are phase
shifted from each other by 180 degrees.

Miscellaneous
Reset (RESET)- This signal is asserted by external logic to force the CFPA to its initial powerup
state. Deassertion of RESETisinternally synchronizedsoihat ihe first rising edge of CLKA that
foll()ws the deassertion of RESET corresponds to PI.
Test 2 and Test 1 (TST <2:1 > )-These signals are reserved for CFPA manufacturing use .

• Architecture Summary
.
The foUowingis a brief description of the CFPA architecture: The CFPA has no user-accessible
registers or mode bits. 'The general registers and cOl1ditioficodes are cOl1tained in 'the CPU. Round
or truncate operational modes and F_Hoatingor D_floating data types are determined by
commands sentfrom the CPU to the CFPA.
Data Types
The architecture of the CVAX 78134 FPA supports seven data types,--byte, word, longword,
quadword, F _floating, DJloating, and GJloating. Figures 3 and 4 show the organization of
these data types.
Confidential and Proprietary

1-95

IlIIIalI .,
WORD

I": :: :: : :: : ::: :: :00[,

,m (': : : : : :

:"1'

LONGWORO

.r: ::::::: ::::::::::::::::::::::;00\ A
Q\JAOWORO

Figure 3· C1;I1X 78134 Integer Data Types

D •. FLOATING
15
14

s

07

I

00

06
I

I

EXPONENT

:A

FRACTION

FRACTION

:A+2

FRACTION

:A+4
:A+fj. ,

FRACTION

I

.'

'

I

I

48

63'

15

s

I

04

14

03

00

I

EXPONENT

:A

FRACTION

FRACTION

:A+2

FRACTION

:A+4

FRACTION
I

I

I

I

I

:A+6
.~

63

Figure 4· CVAX 78134 Floating-point Data Types
1·96

Confidential and Proprietary

. I

j

I

'
. 48

Preliminary·' .
Instruction Set
The CFPA instruction set consists of 70 floating-point instructions and five integer instructions
that provide the following operations.
Addition and Subtraction-For single-precision and double-precision Hoating-point numbers.
Multiplication and Division-For single-precision and double-precision floating-point numbers
and for integers (longwords only).
Conversion-The CFPA performs floating-to-integer and integer-to-floating' conversions and
double-precision to or from single-precision floating-point conversions.
Comparison- The CfPA has.a compare (CMP) and t:t;:st('rST)~structionassQr::iat~d With each of
the three ,floating-point data types~'
.
.

Add Compare and Brandl-TheCFPA assists the CPO in executing an Add Compare and Branch
(ACB) instruction by performing the add and compareportiol}s of the instruction. There is an ACB
instruction associated with ~achqfthe.thre,e floa~jflg·poi1)td~tQ.types..

Polyn()mialEvaluation-The CFPA assists the CPU in executingthejXJlynomiaLevaluation (P()LY).
instruction. The CFPA performs the floating-point addition and multiplication operations asSoci:
ated with the polynomial evaluation. There is a POLY instruction for eachfloating-pOillt data type.
Extended Multiply and Integerize-The CFPA has'an ex'tendedmultiply and iriteg~riie (EMOD)
instruc.tiQn.associated with each floati~-pOintQa~a typefori~curate range repuctkmsof math
function arguments.
.
Instruction Set Notation
The standard notation for operand specifiers is

< name> . < access type >,,< dl;tt~ type>
l. Name is a suggestive name forthe operand in the context ofthe instruction. His the capitalized
name of a register or block for implied operands.

2. Access type is a letter denoting theop~rand .,5pj::Cifier aCCeSS type. 1
a = address operand

b = branch displacement
m = modified operand (both read artdWritten)
r = read -only operand· .'

w = write-only operand
3. Data type is a letter denoting the data type of the o~rand.
b= byte
..
fc; i
d T' R,.floating
f = F_floating
g = G_floating
l,,=lbngword
q=quadword
w=word

The abbreviations for condition codes are
"=conditionally set/cleared
- == not affected
o= cleared
l=set.

Confidential and Proprietary

1-97

Preliminary'
The abbreviations for exceptions are

rsv =reservedoperind fall It
iov = integer overflow trap
idvz"" integer divide by zero trap
fov = floating overflow fault
fuv = floating underflow fault
fdvz = floating divide by zero fault
Integer Instructions
1he CFPAaccelerateS the integer irtstructions listed in Table 4. The table lists the VAX apcode
(hexadecimal) for the instruction, code transferred by the CPSTA <: 1:0> and CPDAT<5:0>
lines, instruction; condition codes affected, and exceptions that can be reported.
Table 4· CVAX 78134 Integer Instructions

N

Z

V C

Ex~eptions

,',

-k

,';

0

iov,idvz

DlVU divr.rI,divd.rl,quo. wI

1,

,',

:;.',

0

iov,idvz

,',

Opcode CPSTA/CPDAT Instruction
codes
DlVL2 divr.r1,quo.ml .

C6
C7
7A

01111010

EMUL mulr.rl,muld.rl,add.rl,prod.wq

~'~

C4

01000100

MULL2 mulr.rl,prod.mI

1,

MULL3mulr.rl,muld.r1,prod.wl

'1<

C5

01000101

0

"

t,

a

iov

"

-/:

0

iov

Floating-point Instructions
The CFPA implements all the floating-point instructions for F _floating, D_.floating, and G_floating data types except for CLRF which is equivalent to CLRL, and CLRD/G which is equivalent to
CLRQ. Table 5 lists the floating-point instructions implemented by the CFPA giving the VAX
opcode (hexadecimal), code transferred over the CPSTA <.1:0 > and CPDAT < 5:0 > lines,
instruction, condition codes affected, and exceptions that can he reported.

Table 5 • CVAX 78134 Floating-point Instructions
Opcode CPSTA/CPDAT Instruction
codes

6F
4F
4FFD
60
40
40FD
61
41
41FD
71
51

1-98·

10 101111
10 001111
11 001111
10 100000
10 000000
11000000
10 100001
10 000001
11 000001
10110001
10010001

ACED limit.rd,add.rd,index.md,dispLbw
ACBF limit.rf,add.rf,index.mf,displ.bw
ACBG limit.rg,add.rg,index.mg,dispI. bw
ADDD2 add.rd,sum.md
ADDF2 add.rf,sum.mf
ADDG2 add.rg,sum.mg
ADDD} addl.rd,add2.rd,sum.wd
ADDF3 addl.rf,add2.rf,sum.wf
ADDG} addl.rg,add2.rg,sum.wg
CMPD src1.rd,src2.rd
CMPF src1.rf,src2.rf
Confidential and Proprietary

N Z V C· Exceptions
'It

;,~

0

~'<

~'<

a

,,/.:

,~

!'(

~'(

,,,

*
*
*
*

,.

.,:

...

...'t

.,..

...,-:
'k

0
0
0
0
0
0

',

a

"

0
0

-k

- rsv,fov,fuv
- rsv,fov,.fuv
- rsv,fov,fuv
o rsv,fov,fuv
6 .rsv,fov,fuv
a rsv,fov,fuv
o rsv,fov,fuv
o rsv, fov;fuv
o rsv,fov,fuv
0 rsv
o rsv

Prellininari;" .
Opcede' OPSTA/CPDAT Instruction
codes

51FD
6C
4C
4CFD

68
76
6A
69
48
56
99FD
4A
49
48FD
33FD
4AFD
49FD

6E
4E
4EFD
6D
4D
4DFD
6B
4B
4BFD
66
46
46FD
67
47
47#D
74
,to

54
54FD
72
52
52FD

70
50
5QFD
64'
44

CMPG src1.rg,src2 . rg
11 010001
CVTBD src.rb,dst.wd
10 101100
1000nOO
CVTBF src.rb,dst.\¥f'
CVTBG src.rb,dst.wg
11001100
10101000
CVTDB src.rd,dst~wb
CVTDF src.rd,dst.wfi ,
10 110110
CVTDL srud,dst.wl
10 101010
·10101001
CVTDW src.rd,dst.ww
,10001{)00
CVTFB src.rf,dst.wb
10 010110
CVTFD src.rf,dst.wd
CVTFG src.rf,dst.wg..
11011001
CVTFL src.rf,dst,wl
10001010
CVTFW src.rf,dst:ww::
10001001
CVTGB src.rg,dst. wb
11001000
CVTGF src.rg,dst.wf
11110011
CVTGL src.rg,dst.wl
11001010
CVTGW src.rg,dst.Ww
11 001001
CVTLD src.rl,dst.wd
10 101110
CVTLF src.rl,dst.wf
10 001110
11 001110
CVTLG src.rl,dst::"8
1010i'101
tVrtfD src.rw,dst.wti ..
1000h01
CVTWFsrc .rw,ds(w£"
110011'01
CV'rWdsri::.rw,dsi:.~g
10 101€Jll
CVTRDLsrc.td;dst.wJ
1000ta1'! , , ' CVTRFLstc.rf,dst\v~i'
CVTRGL src.rg,dst,wl
11 001011
10100HO
DIVD2 divud;quo.mclf
. DIVF2 divut,quo;lnf! ..
iOOOOIlO
.DlV02 divhrg,quo.rog ", .
11 000110
DIVD3 divr.rd,divd.rd,quo. wd
10 100111
10 000111
,DIVF3 dlyr.rf,d,iv9.ri,qU\\wtr:"
11 000111
DIVG3 div~\tg>divd.rgtq/..lOiWg ';
10 110100
EMqDD 111~It:rd,111vkx.rb)nWl.d.r4,
iqt.
wI. fract.wd
", "
. . . i.
.'
10010100
EMODF ~ulr.rf,111ulp!;,.r:b"rould•.rf,
int.w1,fract.wf '.' .....•.•.........•. ' •...... ~
11010100
EMODG' IIllllr.t~,mutri .
muld.rg,irit.wl,ttai:i."yg .: ...
MNEGb src.rd,dst:wd
10 110010
MNEGFsrt.'rf,dst.wf " .'
10010010
,11 Otool0
MNEGGsrC.tg,dst:wg
10110000
MOVD src.rd,dst. wd
MOVF src.rf,dst.wf
10 010000
11 OlQOQO
MOVG src,J:'g,dst;wg
.10100100
MULD2 11111lrdd,prod,md'
1Q.000100
MULf2 mulr.rf,prod.ml.

rw,· .

* .*
*,
.,~

a
a

\I;

* 0

\I;

* 0

0 rsv
0
0
0

a rsvjiov

\I;

, "t(j

.;*

. . *,

:'*

\I;

;>*

'f

'II;

" , '",*

. ,

a

O' rsV,foV
Orsv,im'
\I; '0 rsv,iov
*O'rt;v,iov
\I;

o Qtsv'

0 .Orsv'!

.\1;

,~

,\1;

"* " Ors«iov

\1; ••

* * :O'tS'il,iov

'*

\~

*>

* 0 OrsV,fov,fuv

!I(;
\I;

.\<
\I;

\I;

•

Orsv,i6v

* 0 rsv,iov

* 0 rsv,iov

* 0 0
" * 0 9
9" '0
'I,

"

\1;'

\I;
\I;

*

\I;

b Q
'0 (j
*0"0
*'0 ·tsv,itiv
(c,
f) rsv;ltiv
* '* 0 rsv,iov
\I;

;.,

o· o· fsvjiov,fuv,fdv.z:
*0 0 rsv,fov,fuv,fdvz
* ,* ,0 O::rsv,lkw,fuv,fdvz'
* * o 0 rsv.fov,fuv;fdvz
Q ;9, ):~v,fv

" * 0 0 rsv
,\I;

1,

0

~

:*, 0

"-C

'I<

,.*.

\I;

\I;

*

0
0

"~I

\I;

{)

rsv.

tsv
- rsv

"..

o rsv;fov,fuv.
o.tsv.,fov,£uv

m_

cVAxi8'114-

Prelimhmry:

Opcode. CPs'l'.MCPJ)AT. Instruction
codes

N ZV ,C :Exceptions

44FD
65
45
45FD
75
55
55FD
62
42
42FD
63
43
43FD
73
53
53FD

-1,

11000100
10 100101
10000101
11 000101
10 110101
10 010101
11 010101
10100010
10 000010
11 000010
10 100011
10 000011
11 000011
10 110011
10010011
11 010011

MULG2 mulr.rg,prod.mg
MULD3 mulr.rd,muld.rd,prod. wd
MULF3 mulr.rf,muld.rf,prod.wf
MULG3 mulr.rg,muld.rg,prod.wg
POLYD arg.rd,degree.rw,table:ab
POLYF arg.rf,degree.rw, table.ab
POLYG arg.rf,degree.rw, table.ab
SUBD2 sub.rd,dif.md
SUBF2 sub.rf,dif.mf
SUBG2 sub.rg,dif.mg
SUBD} sub.rd,min.rd,dif.wd
SUBFJ sub.rf,min.rf,dif.wf
SUBG3 sub.rg,min.rg,dif.wg
TSTD sre.rd
TSTP src.rf
TSTG src.rg

. ',

"
i,

..,',

-k

.,::

""l~

~,

.,1'.

;,

*'

* -k
* *

.. ,',
,..

-I:

0
0
00
0
0
0
0
0
0

a

'"k

*

"

-k

0

"'k

-!(

-k

-k

..;,

1:

-0
0
0

'1:

"

0

0 rsv, fov,fuv
0 rsv,fov,fuv
o rsv,fov,fuv
D rsv,fov;fuv
0 rsv, fov,fuv
a rsv, fov,fuv
0 rsv, fov,fuv
a rsv,fov,fuv
0 rsv,fov,fuv
0 rsv,fov,fuv
o rsv,fov,fuv
o rsv,fov,fuv
0 rsv,fov,fuv'
0 rsv
0 rsv
0 rsv

Instruction Processing
During normal operations, the opcode and all operands associated with the instruction to be
executed are transferred to the CFPA. The CFPA executes the instruction and returns the status
including all errors and the results. The exceptions tcll:bis genera! case are described as follows.
Integer divide (DIVL2, DIVL3)-During integerdividein~truction, the CPU detect and reports a
divide by zero condition. It does not request a result and the CFPA will abort the integer divide
operation.
Floating compare (CMPD, CMPF, CMPG)-Duiing a floating compare instruction, the only result
transferred is the status of the PSL condition codes. To maintain the normal return result protocol,
the CFPA will return a longword result. The CVAX CPU should discard this longword as its contents
are unpredictable.
Floating Add Compare and Branch (ACBF, ACBD, ACBG)-Durlng a floating add compare and
branch instruction, the CFPA reports, in addition tothe normal result, whether the branch should
be taken. This is encoded in bit 3 of the returned status. Bit -' is normally used to report integer
overflow, which cannot occur on a floating add, compare, and branch: After testing this bit, the
CPU must ensure that the V bit in its PSL is cleared.
.
. Extended Modulus (EMODF, EMODD, EMODG)-The extended modulus instructions compute
two results. The CFPA returns the integer result followed by the floating result. Therefore, EMODF
returns two longwords and EMODD and EMODG re.turn three longwords.

Polynomial Evaluation {POLYF, POLYD, POLYG)-The CFPA supports the polynomial evaluation
instructions by implementing a POIY step function .. Given theargllment and the current partial
result, the CFPAreads the new coefficient, computes the partiaLresult, and return'i status and the
new partial result to the CPU.
The protocol for the startup and poly step loop phase between the CVAX cpDand the CFPA for
POlYP; POLYD, and POLYG instructions is described. 'After the setup phase, the CPU and CFPA
enter the POIYSTEP loop. The CPU records the loop count using the degree operand.
1-100

Confidential and Proprietary

-.

CVAX78n4

Startup Phase
1. The CPU sends the opcode for POLyp, POLYD, or POLYG to the CFPA.

2. The CPU sends the argument operand to the CFPA.
3. The CPU sends the degree operand to the CFPA which checks for a reserved operand (degree
GTR 31). If found, the CFPA returns reserved operand status when the CPU indicates it is ready
for the results.
4. The CPU does not send the table address operand to the CFPA.

5. The CPU indicates when it is ready for.aresult. Th~ CFg.t\,~sP9ndsby transferring status and a
result equal to. the. argument· ~verilnq.Jf theatgumehtW~s<1short literal, the. CFPA returns the
argUD;l.c;'tllt in expanded fo1'.1);1: one 10ngwm:~JQr,:pQLYF, two longwords for POLYDorPOLYG;
6. The CPU sends the seed partial result.'tothe CFPA::If the instruction is being started, the seed
will be Zero; if the instructionis being restarted, the seed will.Qethelast partial result.
POLY STEP Loop

1. The CPU sends the new coefficient to. the CFPA. The FPAch,ecks the ~ coefficient for a

reserved operand. The FPA compute~n~ partial result whlch is equal to the current partial
result * argument) plus coefficient,

2. The CPU indicates when it is ready for the result.· The CFPA respondsby transferring status and
the new partial result. The status includes the reserved operlind check on the coefficient and any
errors from the polynomial step computation.

3. The FPA executes the POLY STEP loop until a new opcode is received .

. Specifications
The mechanical, electrical and envirpnmental spedficatiohs of the CFPA are C?htained· in the
following paragraphs. The test conditions for the values specified are listed as follows unless
indicated otherwise.

• Power supply voltage (VOl): 4.75 V
• Ground (Vss ): 0 V

Mechanical Configuration
The physical dimensions of the CVAX 781)5 44-pin surfacemountcerquad package are contained
in the Appendix_

Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause perrnanentCIamage to the device.
Exposure to the absolute maximum ratings for extended periods· oftirne 'adversely affect the
reliability of the device.
• Storage temperatu.re range (1'.,): -55°e to 125°C
• Active temperature range (TA):

ooe to 125°C

• Power supply voltage (VDD):-O.5 V to * V
• Input or output voltage applied: -1. 0 V to ~ V
*To be determined.
Confidential and

Proprietary

1-101

Preliminary
Recommended Operating Conditions

• Power supply voltage (Voo ) 4.5 V to 5.5 V

de Electrical. Characteristics
The de input and output parameters are listed in Table 6.

Table 6·CVAX 78U4 dc Input and OutP~t .parameters
Symbol

Parameter

Requirements
Min.
Max.

Units

Vm

High-level input voltage

2.0

V

Test Condition

(TTL)

VIL

0.8

Low-level input voltage

V

(TTL)

VOH

(TTL)

VOL

.

High-level output, voltage

2.4

Low-level output voltage

0.4

= -400 rtA

V

IOH

V

IOL=2.0 rnA

(TTL)

VIHM

High-level input voltage

V

70% Von

(MOS)
VrLM

30% Von V

Low-level input voltage
(MOS)

VOIIM

High-level output voltage

90% Vno

-

V

I OL =-1.0 rnA

0.4

V

101.=1.0 rnA

o < v'n < 5.25 V
a < v'n < 5.25 V

(MOS)

VOLM

Low-level output voltage
(MOS)

IlL

Input leakage current

-20

20

IlA

Ioz

Output leakage curret:Jt.

-20

20

IlA

Icc

Active supply current

200

rnA

Iou. =0
TA=O°C

C'n
Coni

Input capadtance

*

pF

Output capacitance

.,~

pF

1'To be determined.

ac Electrical Characteristics
The following notes apply to Figures 5 through 12 and their associated timing tables.
• All times are in nanoseconds (ns) except where noted.

• C"',I = 130 pF (excepdor CPDAT < 5:0> and CPSTA < 1:0> )
1-102

Confidential and Proprietary

CVAX78134
• ac highs for Mas inputs are measured at

"'HM and lows are measured~t"'LM'

• ac highs for Mas outputs are measured at VOHM and lows are measured atVo~M'
• ac highs for:TTL inputs are measured at VIH and lows are measured at Vn .
• ac highs for TTL outputs are measured at V01i and lows aremeasuted at VOL'

• MaS inputs are driven to VO~M or V OHM abdTT:Linpu'ts'a:re:driven to VOL otVOH '
Clock Input
Figure 5 shows the clock input timing and the parameters ate. listed in Table}.

elM

CL.KB

Figure 5· CVAX 78134 Clock Input Timing

Table 7 • CVAX 78134 Clock Input Timing Parame.~rs

Symbol

Parameter

Requirements (ns)

Min.

Max.

CLKA to CLKB delay

tC;YC;LJ2-2

(nominal)

23

tCYCLE/2 +2
27

External clock high

5.0

25

Externaldocklow

5.0

25

tCLKE

EiKternal clock edge rate

0

10

tC'iCLE

External clock cycle

50

*

tCLKDLY
tCLKH

*To be determined.

Initialization
Figure 6 shows the initialization timing and the parameters are listed in Ta.ble8.

ClM~

- ---'--=tf.---'RES'
1
W
t:
RESEr

DAl<:1I:00>

.--1

Cf'STA<:I'O;.
CPDA'·,-S,C.:>

rr--

·AESW

tR~Sf'TOLl'

.\-.---------+,1--------------I: '\'

----'-----ll
-----'+----..,H-

--I

tCf'HLl.

Jr-------------"

_________

Figure 6· CVAX 78134 Initialization Timing

Confidential and Proprietary

1-103

· Table 8 ·CVAX 78134 Initiallzation 'l'imingParametets
Symbol

Paraineter

Requirements (ns)
Max~
Min.

tcpHI.Z

Coprocessor lUgh~impedance delay

0

20

tRESETDLY

Output drive from RESET assertion

0

25

tRESEI'S

RESET input setup prior to PI

20

tCYCLE-IO

40

(nominal)
tREsErw

tREsETZ

(nominal)

10 x t CYCLE
500

Bus high-impedance time from RESET·

0

RESET input width

25

External DMATiming
Figure7 shows the DMA signaltirning, and the timing parameters are listed in Table 9.

WG

_ - - : . . . . ..}'7.~,~GO

-----------f'''''''"'
Figure 7 • CVAX 78134 External DMATirning

Table 9· CVAX 78134 External DMA Timing Parameters
Symbol

Parameter*

Requirements (ris)
Max.
Min.

tDALHLZ

DAL high-impedance delay

0

20

tDALZHl.

DAL active drive delay

0

20

t DMGH

DMGhold

5.0

t DMGS

DMG setup

25

*DMG must remain asserted during all DMA cycles to avoid conflict on the DAt.

1-104

Confidential and Proprietary .

Coprocessor Timing
Figures 8 through 12 show the timing of the transfers between the CPU and CFPA, and the timing
parameters are listed in Table 10.

elKA

CPS1A<1,O:,..

CPUAT,'O>

J.

,~.~.,.'H-»

--..."...--,-.,-.....,..,...--'t}~-,--.."...,..".......,X~-------­

k,---

---.,-~~X
r-: ~~UTl~N

OF' N'EWVAX

IrJ~·~-~no~,..aE~I~S ~

NOTE
C'JAX DRNr5 CPSTA< 1 :0> ANDCf'I)JIT
leVAX DRIVING:

_ _ _- - '

l'---t---f
I-.:::~:..j-:-:---------t-:-:-----t--:---I----t----

(eVAX DRIVING~ _ _ _- - ' 11..
CPDAT

DAL~J~·OO." -------1("}.--~---~~~----_4-----+_----~---Jf

·:CVM DRIVING)

_______

Cf'STA< 1.0-'
CI"DAT<5:Q>
(CFPA DRIVI!\tG)

Figure 11 • CVAX 78134 Bus Control Transfer /t'01n CPU to CFPA Timing

elM

r-____
CI'STA<: 1 ,();..

CPDAT<.!;;C"·

~~~__

.~'-'--~~

+-_______

~'DAIO --j """OAt""·· ·~t='DAlD L_'OAtO;r-'' ' 'HLl

~------x

,,'",DATA

C

~

'.ASTGATA

)f-I------

Figure 12· CVAX 78134 Data and Status 'Traiisfer /t'OtJt CFPA to CPU Timing

Table 10· CVAX 78134 Coprocessor Timing Parameters
Symbol

Parame~r

Requirements (ns)
Min.
Max.

AS hold

5

AS setup.

25

Coprocessor line drive delay

o

Coprocessor line hold

0"

Coprocessor line drive hold

23*

Copnx; ~ ~ ~ ~

i ~ ~ ~

76

52
51
50
49
48
47
46
45

77

78

WR

79

EPS
CS2
CS1
CSO

80
81
82

iSS
AS

84

VSS
VOOI
DAL31
DAL30
DAL29
DAL28
DAL27
DAL26
DAL25
VDOX

o~

iilo
OPT 3

OPT2

44

OPT1
OPTO
CSDI
CSDO
CTor

43

eroo

42
41
40

VSS
VOOI

5
6

39

DALOO
DALOl
DAL02
DAL03
DAL04
DAL05
VODX

83

MicroVAX 78332
SYSTEM SUPPORT CHIP

2
3

4

38

7

37

8

36

9

35

10

34

33

m

(j)

... '"
N

> -J
 00 r-(j)
N
-J
'"-J :i
«
0
0
Cl Cl ~
Cl ~ Cl Cl Cl Cl Cl Cl

Figure 2· MicroVAX 78332 Pin Assignments

1-124

ROMWIDO
ROMWID1

Confidential and Proprietary

(j)

S'EC'Ci5N

"'-

MicroVAX.7il.l32
1ablel- MicroVAX 76332 Pin and Signal Summary

Pin

Signal

Type .

Description/Function

4-10,13~31,

DAL<'31:00>

input/output

Data and Address Lines-Time multiplexed
lines used to transfer address and data information between the sse, the CPU, and the sse

34-39

RO¥, ....
81-8:3

CS<2:0>

input/output Cycle status-Provides status and control information about the cnrrent bus cycle. Connects to
CS/PP<.2:0:>on theeVAX.
fr',:

Address ,strobe"""7Provi~' tinting and contt:Ol
information to the sse.

1
.84

inp:ut

Data s.tro,be ......Provides. ummg and control
information for data transfers to and from the
sse.

54-57

BM<3:0>

input

Byte ~-Indicates which bytes of DAL lines
data contain valid information during the secondpartaf an I/O cycle.

79

WR

input

Write-Specifies the direction of data transfer
oritheDAL

78

RDY

output

Ready-Asserted by the SSC to indicate the
end Qfhq.s cycle.

77

ERR

output

Error-Asserted by the SSC to indicate a bus
timeout condition.
.

80

EPS

input

External processor strobe-Coordinates the
Miq()VAXe:xternal proc:essor transactions.

76

RESET

input

Reset-Asserted during power system transitions,and during battery.baekup mode. The
deassertion of the RESET signal initializes the

sse.

60

CPUHALT

Olatput

CPU Halt-A halt request to the CPU.

59

HALTIN

input

Halt Lu"';'"A. halt request fro111 the extemallogic.

40

SECCON

input

Secure console-When asserted, the halt
requests received by the console terminal are
not transmitted to the CPU,

58

RUN

output

Run""':Asserted when the halt signals are
enabled.

68

IRQ

output

InterrlJpt request-An interrupt request to a
CPU.

Cqnfidential and Proprietary

1.. 125

gma..

PrelinUnary

MicroVAX78:332

Pin

Signal

Type

Description/Function:

67

IAKEO

output

Interrupt acknowledge enable out-Asserted
by the SSC upon receipt of an interrupt
acknowledge from the CPU if no SSC interrupts
are pending at the interrupt acknowledge level.

66

lORE SET

output

1/0 System B-eset-Asserted by the SSC when
. the CPU writes to processor register IPR #55.
Typically used to reset a Q-bus system.

72

ROMEN

output

ROM Enable-Enables the external ROM.

70,71

ROMADR < 1:0 >

output

ROM Address-Selects the correct bytes during a ROM read operation.

53,52

ROMWID< 1:0>

inptlt

ROM Width-Determines the width of the
ROM and is also used to cause the SSC input!
output lines to become high impedance.

44

CTm

input

Console Terminal Data In-A serial input to
the console terminal receiver.

43

CTDO

output

Console Terminal Data Out-A serial output
of the console terminal transmitter.

46

csm

input

Console Storage Data In-A serial input to the
console storage receiver.

45

CSDO

output

Console Storage Data Out-A serial output of
the console storage transmitter.

62,61

ADS<1:0>

output

Decoder Strobes-Asserted when the selected
addresses are detected by the sse.

50,47

OPT<3:0>

output

Output Port-Can be used to control output
devices such as LED indicators.

65

INTCLKO

output

Interval Timer Clock Output-A lOO-Hz interval timer signal.

74

CLK!

input

CJock In-An SSC clock timing signal nominally40 MHz.

73

TB40M

input

Time Base 40 MHz-Provides a 40-MHz timebase to the baud rate generator, the bus timeout
logic, -arid the interval and programmable timers. Also provides a timebase to the time-ofyear dock if theTB25K input is grounded.

69

TB25K

input

Time Base 25.6 KHz-Provides the timebase
for the time-of-year clock.

51

BLO

input

Battery Low-Indicates that the battery power
is low.

1-126

Confidential and Proprietary

Pin

Signal

3,41

VDm

. Type

Description/Function

input

Voltage~Contipuous

5 Vde power to the

sse

internal circuits.
11,33,64

VDDX

input

2,12,32,63

Vss

input

VOltage-,-5 Vde powertothe sse pads.
. Cround-Groundreference.

Data and Address Lin~ .. .... > .. < . ,. .•...• . . . '
Data and Address LineS (DAL < 31:00' »":"-Thedata and aa~~s lines are time-multiplexed and
transmit addresses and data between the CPU and other devices. Theproi:ooois used· for the
MicroVAX CPU and the CVAX CPU are as follows.
During the first part of a MicroVAX CPU read or write cycle, DAL < 29 :02> contain thelongv.'Qrd
address of the operand. During the second part of a CPU read cycle DAL< 3l:00> are used to
transmit information to the CPU. During the second part of a Micr6VAX CPU write cycle,
DAL < 31:00 > are used to receive incoming information.
.
During the first part of an MicroVAX interrupt acknowledge cycle, DAL <04:00 > contain the
interrupt priority level of the interrupt beingacknow!edged, DAi<31:30> ;= 1O.and
DAL< 29:05> are zero~.Duringt4e second part ohhecw;le, the interrupt vectods transmitted to
the CPU on DAL < 09:Q2 >..
..
.
During a MicroVAX external processor (EP) writecommandcyde, the CPU t~nstet's the processor
registe~ number on DAL < 05:00:;>: and theup\Xlrniug .transactipn type on OAL3l (read? 1,
write=O).
During a.MkroVAX EP read response cycle,DAV:, transmit ·information to the CPU.
During ariEPwrite data cycle, DAL<31:00». receives incoming, information frain·the CPU,
During the first part of a CVAX CPU read or write cycie,DAL<29:02:> contail1 the longword
address of the operand. During the second part of ra.readcycle,DAL<31:00> transmit
infoxmation to the epu.
During the second part of a write cycle, DAL<31:00>rece:i.ve incomlbg information from the

cro.

.

During the first part of a CVAX CPU interruptackrtowledge rcycle, DAL < 06:02 :> . contain· the
interrupt priority level of the interrup{beingacknowledged· and DAL < 31:07> and
OAL<01:00> equal zero. During the second part d£ thecycle,DAL<31:00>transmjtirifbrma~r
tionto the CPU.
Du.ring the first part of a CVAX EP read or write cycle, the· CPU transfers· the processor register
number on DAL<07:02> and zeros on DAL<10:D8:>.Dtiringtheset6nd part of an EPread
cycle, DAL<31:00> transmit information to the CPU.Duringthe second.part of anEPwrite
cycle, DAL < 31: 00 > receive incoming information from the CPU.
Control Lines

.

.

Address Strobe (AS)-During a CPU read or wr.i;e cy<;le, aCYAXExterna! Processor register. read
or write cycle, or an interrupt acknowledge cycle, the CPU asserts the AS line when the information
on DAL < 31:00 > is valid and deasserts the line when the bus cycle has been completed.

Data Strobe (DS)-During a CPU read cycle or interrupt acknowledge L),de, the CPU asserts the

os signal to indicate that DAL < 31:00 >

are available to receive incoming data and deasserts the

Confidential and Proprietary

1-127

MicroVA~/1kjj~

IIBIB

55 signal to indicate that ithas••J:tCe~v~d sllR latched the incogling data. [)uringa CPU write cycle
or CVAX external proce~sorregister 'w~it~ -cycle, it is asserted by the CPU to indicate that
DAL<31:00> contain valid datEt'and deasserted when the data is not valid.
During a CPU write cycle, the CPU asSerts the DS line to indicate that DAL< 31:00> contain valid
outgoing data and deasserts the DS line to indicate that the data will be removed from the bus.
Byte Mask (BM < 3:0> )-The byte mask specifies which bytes of the DAL contain valid
information during the second part of a CPU write cycle. The SSC ignores the byte mask except
during write operations to the RAM. The byte mask assignments are shown in Table 2 .
. Table 2· MicroVAX 78332 Byte MaskData Setecpon

Byte Mask

Valid Lines

Line
BM3

DAL<31:24>

BM2

DAL<23:16>

BMI

DAL<15:08>

BMO

DA.L<07:00>

Write (WR)-This input specifies the direction of data transfer on the the DAL.WhenWR is
asserted, the CPU transfers data on the DAL. When WR is not asserted, the CPU receives data from
the DAL. The WR signal is latched when the AS. input is asserted.

Ready (RDY).1... The sse asserts this output to indicate that the current bus cycle should be
successfully terminated. During a read cycle or interrupt acknowledge cycle, the assertion of the
RDY signal indicates that theSSC has placed the required data on the DAL. Duting a write cycle,
the assertion indicates that the SSC has latched the data. It remains asserted until the AS input is
deasserted. This is an open-drain output.
Error (ERR)- The sse asserts this output to indicate that a timeout of the current bus cycle has
occurred. The length of the timeout period is determined by the value loaded into the Bus Timeout
Control register of the sse. The ERR output remains asserted until the DS input is deassetted.
This is an open-drain output.
External Processor Strobe (EPS)-This signal is used by the MicroVAX CPU to coordinate external
processortransactions. It is not used by the CVAX CPU.

Reset (RESET)-The deassertion of the RESET input initializes the sse to its powerup state. It
must be asserted during battery backup mode (i.e., during a power loss) or when there isa
transition on a power supply output. When asserted, the DAL< 31:00 >, RDY, ERR, and the eS2
forced to a high-impedance state. All other outputs are deasserted.

lin~s .are

Cycle Status(CS <2:0»-These lines and the WR line provide status and control information for
the cutrent bus cycle. The CS < 2:0:> line information is latched when the AS line is asserted.
In a CVAX CPU system, the cs <2:0> lines connect to and are time-multiplexed with the Cycle
Status/Data Parity lines (CS/DP<2:0». The SSC ignores the DAL Hne parity and latches the
CS < 2:0 > lines information at the assertion of the AS input.
T:.ible31ists the bus cycle selected during a CPU read or write cycle, an interrupt acknowledge cycle,
or a CVAX EP read or write cycle.

1-128

Confidential and Proprietary

Thble 3 • MicroVAX 78332 BusCycIe (:~ntroISeleCtion(nori-MicroVAXEp'cyde)*
WR

ControfLine
CS2
CS t

H

L

L

READ

H

L

H

CVAX EP ~~gisterl'ead '

H

L

H

H

H

H

L

L

H

L

H

read

H

H

H

L

read

H

H

H

H

read

L

L

H

L

CVAX EP register write

L

H

L

H

write
,;,

L

H

H

H

write

Write

Bus Cycle Type

CSO

interrupt acknowledge

*AS"" Land EPS c H. The CS <2:0>' combinations not listedare' reserVed.

During a MicroVAX EP.transacti~nih,:,oIvl~ th~ sse, theeS2line~ np~,used exceptdur:ingan Ef,
Read Response cycle whereeS2 is pUlled low by the SSC. Table 4 snows the bus Cycle selected
during a MicroVAX EPread or wiite cycle.
' ,

Thble 4· MicroVAX 78332 Bus Cycle Control Selection (MicroVAX EP cycle)*

Write

Control Line'pu.!lCYcl«;<:I'ype

WR

CS2

cst

CSO

H

X'

H

H

read response

L

X

L

H

write data

L

x

H

L

write command'

= Band EPS = L. The CS < 2:0 > combinations not listeliare reserved.
H = high level; L = low level, X == high or low level

-i, AS
I

'During an EP write cQmmanli cyde ,PAL31 indicates that the transaction that follows is a read (H)
or a write (L).
,:
'
'Precharged high (H) aJ}d asst:rte~.low .dudR,gre\idresponse: '
CPU Halt (CPUHALT)-This signal is asserted for at least eight microcydes (nominally 800
nanoseconds) when a halt request is detected by the SSC. It connects to the HALT input of the
CPU.
Halt In, (HALTIN)-This isa level,sensitiveinpuqhat receives.halt requests from external logic.
When appropriate, these requests are pas5ed to the CPU through the CPUHALf output ..
Secure Console (SECCON)...,.;When this input i~ conneCted ,to ground,hreaks received. by the
Console Terminal UART are prevented from asserting CPUHALT.

Confidential and Proprietary

Run (RUN),..,.,.. flUs ;o~tp!ut j~~ssertt:d ,'!'!l),e;n th~ h~t qonditionsare e~!~bled andis de~ss~t:ted when
the halt conditions are disabled. During the first microsecond after the RESET input is deasserted,
the RUN signal will oscillate at approximate1ylO MHz (for test purposes}atid tBen operate
OO~~

.

Interrupt Request (IRQ )-This open-drain output requests an interrupt from the epu on
one of the four CPU IRQ lines. The interrupt priority level is defined by bits < 25:24 > of the sse
Configuration register and must correspond to the IRQ level to which the IRQ < n > output is
connected.
Interrupt Acknowledge Enable Out (IAKEO)-The sse asserts this output when it receives
interrupt acknowledge cycle that it has not requested. This output is not asserted if an sse
interrupt is pending and the IPL is the same as defined by bits < 25:24 > of the sse Configuration
register. The sse deasserts the lAKEO output when the epu deasserts the DS signal.
I/O Reset (IORESET)-The sse asserts this output when a write Cycle to Jnternal Processor
Register 55 is a request for a bus reset.
ROM Select
ROM Enable (ROMEN}-The assertion of this output by the
read. It connects to the Chip Enable inputs of the ROM(s).

sse enables the ROM bank to be

ROM Address (ROMADR< 1:0:> )~When using an external \VordwideROM, the ROMADRI
output c';J11nects to the. AO input on the ROM. When using an external byte-wide ROM, the
ROMADRI and ROMADRO outputs connect to Al and AO inputs, respectively, on the ROM.
ROM Width (ROMWID < 1:0»-These outputs select the width of the boot ROM and theDAL
that connect to the ROM. It also selects a high-impedance state for all sse I/O outputs. The
selections are listed in Table 5.

'Thble 5 • MicroVAX 78332 Boot ROM Width Selection
ROMWID
1
0

Width

Lines

H

H

32

DAL<31:00>

H

L

16

DAL< 15:00>

L

H

8

DAL<07:00>

L

L

high impedance (all sse I/O and output lines)

The ROMWID outputs that are to remain a high level connect to VDD through resistors. When both
pins are connected to ground, all sse 1/0 and ollt:put1ines are high impedance.

Serial Data
Console Terminal Data In (CTDI)--- This input provides seriaLcharacter data to the console
terminal receiver of t:heSSC ...
Console Terminal Data Out .(CTDO)-This output provides senaIcharacter data from the console
terminal transmitter of the sse.
Console Storage UART Data In (CSDI)-This input provides serial character data to the Console
Storage UART receiver of the sse.
Confidential and Proprietary

ConsoieStotage;lJJART DataOUt·(CSDO)-/fhlsoutput provIdes serial characterdata'·frotn the
Console Storage BART trimsmitter of the sse:
Miscellaneous Signals
Address Decoder Strobes (ADS < 1:0> )-These outputs provide strobe signals to external logic
whenpred~fined addressesaredetected by the sse.

Output Port (OM'<;l:6> l.,:;;../fHeSe' MtputS~:&!om;the Outt;utQY ,a.;tf!l(~i!~",aJ .25 .6- KHz oscillator, thls input
supplies the timebase for theT~m9rof::yegtif CroY)'Gk~<:k,;ro,~~t~in the my dock when $ystem
power is removed, this oS(':illator ~bQUl4,b~Jluppli@ PQWerftqlD;gattery backup lIDit. Wl)etllhi~
input is connected to ground"thet~Y.Jl9<::k;iU~swaeXJ#lQ~$ignal as its timeb~se whilNyste,nl
power is supplied. This input requires a: CMeSlevelal:J:d ffillstnotbe switched between the
oscillator and ground while theSSC isrufl!li,f!R.
.,
,
. ,

Power and Ground
Battery Low (BLO)-If this input is asserted while the RE~1[';iil~(lt is asserted, the BLO bit31:of
the sse Configuration Register is set. It can~pleared;~yl;1r th(!.user. If the BLO bit is setwben
the sse is reset, the time-of-year clock is cleared.
Voltage (VoOl)-These inputs provide continuous dc power'w·the internal circuits oftl1eSSC;
When theRESEj' input is asserted, a lower vo16igF§~6,n;~e,#tJssuppliedso that the RAM \ViJJ
hold its state and the time-of-year clock will contin.vetoopetflte. The RESET input ml4sti~
asserted when the voltage on these inputs is ~l1InsitiQrijng:
.'
.
.
, ;; .; ,: : ..
~,;"

','

,",

Voltage (VDDX ) - These inputs provide dc ~!tto,the,pa~driv;¢ts of the sse. The RESE!J:in.J:)llt
must be asserted when the voltageorrthesernputsis ttansit~oned:,

Internal Ground (Vss ) - These input pins provide th~'gJ.P~dr#erence to the SSC.
,

j

;

• Registers
The sse contains ten VAX Internal Processor Registers (IPR) ll;1at ~ay be addressed either Wtheir
IPR number {through MTPR or MFPRinstructions} or by their 110 space address: All sse register
accesses are 32-bits wide and longword aligned. The SSC registers are contained in a relocatable 2KB block of I/O space except for the Base Address register (BA) which has a fixed I/O space address
Confidential ~l'ld Eropriietary

1-1,31

of 20140000. Storage elemf;11t locations are defi~d asoffsets£r()rn;tlle,yal~~ contr4ne,djntbe ill\;
register. The notation "BA + < offset> " denotes the address of the.storage element~.
The sse registers are listed in Table 6. The offsets are shown in hexadecimal notation and the IPR
numbers in decimal notation.

Thble 6· Mi!!wVAX78332 Internal: Registe:r Offset and Number.
Offset

IPR Register

000-003
004-00F
010-013
0l4-OlF
020-023
024-02F
030-033
034-06B
06C-06F

27

Base Address (BA)
Reserved
sse Configuration
Reserved
Bus Timeout Control
Reserved
Output Port
Reserved
Time-of-Year (TOY)

070-073
074-077
07S-07B
07C-07F

28
29
30.·
31

Console Storage Receiver Status (eSRS)
Console Storage Receiver Data (eSRD)
Console Storage.Transmitter Status (eSTS)
Console Storage Transmitter Data (CSDB)

080-083
084<087
088-0SB
OSC-OSF

32
33
34
35

Console Receiver ControVStatus (RXCS)
Console Receiver Data Buffer (RXDB)
Console Transmitter Control/Status (TKeS)
Console Transmitter Data Buffer (TXDB)

090-0DB
ODC-ODF
OEO-OEF
OFO·OF3
OF4·0F?
OFS-OFB
OFe-OFF·

Reserved

55

I/O System Reset (IORESET)

Reserved
Rom Data*
Bus Timeout Ccunter*
Interval Timer*
Reserved

toO-l03
104·107
lOS-lOB
lOC-lOF

Timer 0 Control
Timer 0 Interval
Timer 0 Next Interval
Timer 0 Interrupt Vector

110-113
114-117
lIS-lIB
llC-llF

Timer
Timer
Timer
Timer

120·IFF·

Reserved

I-B2

1 C~ntrol
1 interval
1 Next Interval
1 Interrupt Vector

Confidential and Proprietary

Offset

Address Decode Channel 0 Match
Address Decode Channel 0 Mask
Reserved
Address Decode Channell Match
..Address Decode "Channel
IMask
"j', , .,', -, ,.'

BO·tH
134·137
138c13F
140·143
144-147
148-3FF
400-7FF

Reserved
Internal RAM

*These registers are used for test purposes and should not be accessed by the

user: . ., .

The h~rdWate updates the register ,bits ir resI?Onse to ~nts withint~SSf Theteg~ter
information that is accessible by the user isdefinecl as follows. ..
RW
Read/Write-Can be read or written by the user. The hardware can change the value of
the bit o,nly w!t<:\flthi!l\J?;SET input ~s asserted... .
RW'
Read/WHte'~CaQ t;Cdearedby t:~~Harqwa~.~t~y t~~; Writing to,fhese bit by the
user is igl;Iored ifl.:l~aJ'C9by~ h~ttlW!ll*<.h~l",,*g).tl:i,~~~j!~Ie.
RO
Read Only-;-Caribe,read o11ly by the user. Only thehlU' line of the MicroVAXorCVAX CPU to which the
SSC line is connected. For example, if the sse IRQ  output \5 connected to the CPU
IRQ21ine, bits 25:24 must be set to lO.'fhe encodings are as follows
Bits

25

24

o
a

0
1
0
1

1
1

1-134

IPL Level

IRQ Line .

Priority

14

IRQO
IRQ1
IRQ2
IRQ3

lowest (default)

15
16
17

Confidential and Proprietary

highest

-

MicroVAX783)2

Bit

Description

23

RSP (ROM Speed)-This bit selects the ROM access. time. The RESE'Y input dears this
bit. The ROM access tj,mes are
Bit 23 =0: 350ns (default)
Bit 23 ... 1: 250 ns

22:20

ROM SIZE SEL (ROM Size Select)-Thes~~itss*ecify the extent of the ROM address
space. The RESET input clears these bits. Th~i de£~ult ROM size is 8 KB. Theencodings
are defined below.
Bits
22

21

20

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0

ROM Address Space ..

1
0
1
0
1

20040000·20041 FFF
20040000·20043FFE
20040000·20047FFF
20040000-2004FFFF
20040000·2005FFFF
20Q.40000·1007FFF'f
.2004,QO~0.200BFFff
. 2004(lQOQ.20UFFFF

ROM Size (KB)

8 (default)
16
32
64
128
25~

512,
W.24

19

MBZ (Must be,zero)

18:16

HAL'Y PROf SPACE (Halt protect space) ....... S~tectsthe halt· protected address space. The
RESET input clears these bits. The lowest 8 KB b'tROM spaceis halt· protected by default.
The halt.protected address space may be largetthan the ROM address space. The
encodings are
Bits
18

o
o
o
o
o
1
1

1
15

17

16

0
0
1
1
0
0
1
1

0
1
0

Halt.protected
ROM Address Space

Halt.protected
Extent (

20040000·20041FRF.
20040aOO·20043FFF
20040000·20047FFF
20040000·2004FFFF
004QOOO:.2Q05FFFF

0

2,094QOQ!'h,~0:7FFFF
20040009~200BJWFF

8 (default)
16
32
64
12·8,
256 .
512

1

None

None

1
.2

1

CTp (ControtPEnable).:-C'YRIdPisrecQgn~d,11S a break.in the cOfl$CJle terminal DART
if this bit is set. When this bit is cleared, 20 consecutive spac,e bits are recognized as a
break. This bit is cleared by the RESETinput.
q',,!

Confidentialand.lProptietary

1·1.35 .

Bit

Description

14:12

OT BAUD'SEL (Console terminal baudselectl-Sdectsthe baud rate of the console
terminal UART. These bits are cleared by the RESET input. The default baud rate is 300.
The boot code should write the proper value into the register before the· first console
access. The sse baud dock runs about 1. 75 percent faster. The bit baud rates available are

Bits
14

o

o
a
1
1
1
1

Baud Rate
(default)

U

12 .

0
1

1
.0

600

1

1

2400

0
0
1
1

a

4800

1
0
1

9600

1200

19.2 K
38.4 K

11

MBZ (Must be zero)

10:08

AUX BAUD SEL (Auxiliary baud select)-Selects the baud rate of the console storage
UART. These bits are cleared by the RESET input. The default baud rate is 300. The boot
code should write the proper value into the register before the first console access. The
sse baud clock runs about 1. 75 percent faster. The baud rates available are

Bits
10

Baud Rate
09

08

(default)

o
o

0
1
1

1
1
1
1

a

1
0
1
0
1
0
1

600
1200
2400
4800
9600
19.2 K
38.4K

a

0
1
1

07

MHZ (Must be zero)

06

RDE (Ready Enable}-When set, the RDY output of Programmable Address Strobe
Channel 1 is asserted eight sse microcycles(nominally 800 nanoseconds) after the
corresponding address strobe. WhenRDE isdeared, the sse takes no action after
asserting the address strobe. This bit is cleared by the RESET input.

05:04

ENA· (Enable)...:-These bits enable the read and write chann~lsof Address Strobe
Channell as follows:

ENA
05

03

1-136

ReadWtite

o
o

04
0
1

1
1

0
1

disabled
disabled
enabled
enabled

disabled (default)
enabled
disabled
enabled

MBZ (Must be zero)

Confidential and Proprietary

MicroV.A'X7g~32
Bit

Description

02

RDE (Re~dy Enable).,When. set, the RDYoutpulof the ProgralUl11ableAddress Strobe
Ch\IDJld 0 is asserted eight IIliGrocycles (nominally .800nanosecondss) after the correspondipgacidressstrobe. When RDE isdeared, the SSCtakes no action after 811serting the
address strobe. This bit is cleared by the RESET,input.

01:00

ENA (Enable)-These bits enable the read ~nd .write channels of Add;~ss Strobe
Channel 0 as follows:

Bits
01

o
o
1
1

00
0 .
1

0
1

Read.

Wdte

disabled
disabled
enabled
enabled

enabled
disabled
enabled

dis~d:j]ed (default)

Bus Timeout C~ntrol:R:~gis~r .' , ......... , " . . ".
'.
The sse monitors the assertion and deassertiof.l of the
inp~t to prevent disabling the system
operation resulting fromiinansweredCPU:relidorwrite accesses,CVAXEPread or write accesses,
or interrupt acknowledge cycles. The bus timeout is controlled by the Bus Timeout Control register
that stores the required timeout interval. Each time the AS input is asserted, the sse clears and
starts an internal counter. When the AS input is deasserted, the counter is stopped. If the counter
value becomes the.s!lITleas .~h~ value.\fl.tge~us'tipli;;quhq.)~~l~~ist~f,. tpecounter is stolJped,
the ERR outpJJt iSaSse'rted, and the Btobiijfirithi~reg1~fer:iS~~t:thi~inaicates that the bus
cycle should be aborted. The ERR output is de asserted when the DSiri~tisd~asserted. If the
timed-out transaction is a epu Read orCPUWf1tetransatti9n" theRWT bit 30 is also set. This
register is cleared by the RESET input. The registedorroatis sh6~ni~ F~e 5 and Table 9 defines
the funCtion of the bits.

AS

Figure 5· MicroVAX 78332 Bus Timeout Control Register rot1tJat

Bits

Description

31

BTO (Bus Timeoutl-When set, this bit indicates that a bus timeout has occurred during
a transaction.

30

RWT (Read or Write Transaction)-When SC-t, this bidndicates that a bus timeout bas
occurred duripg a CPU.l'ead qr CPU write transactipn.

29:1'4

MBZ(Mustbe zero)

Coniidentiltl.and ,PrQptietary

1-137

Bits

Description

23:00

BusTi.trteoiitlnterval-These1lltSsp~eify the tiineoutpet'iod.The available range of 1 to
FFFFFF (hexadecimal) torresponds to a seleei:able;timeout interval .rn the range of 1
microsecond to 16.77 seconds in 1 microsecond increments. Writing a zero to this field
disables the bus timeout function.

4·Bit Output Port Register

The 4-bit Output Port register provides four data outputs OPT < 3:0:;::' that can be used to control
LED indicators or similar devices. The data value in this register continually drives the outputs.
This register is cleared during the powerup sequence. Figure 6 shows the register format and lable
10 lists the bit functions.

31

0403

00

I : : : : : : : : : : : : HZ; : : : : : : : : : : ::lHT~ I
F:~gure6 • MicroVAX

78332 Output P9rt Register Format

ThblelO' MicroVAX 7S332 Output P(m Re.gisterDescription
Bits

Description

31:04

MBZ (Must be zero)

03:00

Data-The register data value that is continually driven on the OPT < 3:0 >
output. Bit 03 corresponds to the OPT3 output and bit 1 to the OPTl output.

Time-of-Year Regillter
The Time-of-Year (IDY) clock is controlled by the Time-of-Year register that can be addressed

either as IPR #27 or bya CPU read and write transaction. Refer,to the Functional Operation section
for detailed time-of-year clock information. Figure 7 shows the register format.

Figure 7· Time-of Year Register Format

u>nsole Terminal aridCOllsole Storage UAR'fS
The SSC contains a console storageUART and acotlsole termirtglUARTthiitlopefate similarly to
Digital's DC319 DLART. Each UARt contains four internal processorregistcrs,'the IPR nU11)lbers
assigned to each register are listed in Tables 11 and 12.
"
, .

1-138

Confidehtialand .Proprietary

·. Table 11· MicroVAX 78332Console Storage UART RegisterS

28

Console Storage Receiver Status (CSRS)
Console Storage Receiver Data (CSRD) . .
Console Storage TransmitterStatus (CS1.S)
Console Storage Transmitter Data (CSTD)

29
30
31

IPRNumber

33

Console Receiver C6ntr~fS:taius (RXCS)
Console Receiver DataB~f~r(RXDB):

34
35

Console Transmitter Data Buffer (TXDB)

32

ConsoIe1ran'smitt~r C~nttol{Statlis'{Txd) .

These registers are typka11yaccessedbye~te~aI·process(')J"~egisterpr?tocols,but rn~yalso be
accessed by< CPU read'a~\Jt1te trrinsacl16ns/t)niyig:~itdll.ia ~a single steiP hit o~~ratio!1s'witho\lt
parity
supported.

are

The selectable baud rates are 300, 600,1200; 2400, 4800; 9600, 19.2 K, ani.13:8A K~Baud rate
Configuratiooregi!itef. Framing and overrun errors ~
selection is achieved by writing to the
indi<;atedby theset:ting \of error bits in the receWoo &'ta iegistHs>CSRD lilid· RX:!»B..

sse

TheCbn901e Storage'UART ·andCansole Teifulinalt1AltTaresijnila:r.i The differe~ces are noted in
thqegister descriptions thatfogow,.
.
,.
RecelverRegis.~Each. DART hasaReceiVet,Bootr01am..t$~s register (CSRSand ROCCS) and
a Receiver,Data Buffer (CSRD and RXIDB) ~~r:rnbese ~iiltersare dearedby the RESET signal.

and

Figure 8 shows th~format oftbet:SftD
RXCSregistets.aptt'I;ably n.desfribes ,the function of
the bits. Figure9'ihows theforma{oftheCSRSkooncs re.gistersand tibleJ4lists the function
of the bits.

('::,::: ::: :i+KH
[{i'.F{::>~~17r:+H~
,
,.
'ROT"
• •.• .

RIiV

:ii.·f

•..•.

Figure 8· MicroVAX 783:)2; ReMivet(j}(jntmi aiU!Status (€SRSJRNCS) Regi~k/rfFd11nat

31:08

MBZ (Must be zero)

07

DON (Done)-Set when a character is received. Cleared when the RXDB isreaq ...

~

,.1

~

::,_,'

,

'.,,'

_,

~"_~'

,:'~i"-

,,;:-:-,,' :'-

":H~:

".

),~_,,':

Confidential and Proprietary

",;i','

'_

,'-.

1-139

Bits

Description",

06

IE (Interrupt enable)-Can be set or cleared by writing to the RXC8 or eSRS registers.
An interrupt is generated whenever IE af\d DON transitions to a one state. Interrupt
requests are cleared when the corresponding interrupt request is acknowledged or by
dearing the IE or DON bits.
' .'"
'

05:00

MBZ (Must be zero)

Figure 9 • MicroVAX 78332 Receiver Data Buffer (CSRD/RXDB) Register Format

'. J8ble 14 -l\ficroVAX 78332 Receiver Data ~uffer (CSRDjRXD,B) Register Description
Bits

Description

31:16 'MBZ (Must be zelU)

15

ERR (Error)-,set if ORE bit 14 or FRE bitD are set, These error bits are updated when
data isloaded into the register anddeared \phen the RXDB or eSRD registers are read,

14

ORE (Overrun error)-The receiver is double buffered, If both buffers are full wheh data
,is received, the, assembly register is overwritten and thiSbi't is set when the overwriting
eharact{!ris loaded into RXDB oreSRD register. When set, the ERR bit 15 as also set.

13

PRE (Framing errorl-Set if a frarning error oc:curs, Whenset, the ERR bit 15 is also set.

12

MBZ (Must be zero)

11

RBR Received Break-Set if the receiver detects a break condition. Cleared by reading
the RXDB or eSRD registers. The RXDB register recognizes either 20 consecutively
receiveq space bits or a CTRL/Pchara<.1:eras ahreak condition as specified the CTP bit 15
of the sse Configui-ation Register, The eSRD register only recognizes 20 space bits as a
break condition.' If the break was the result of 20 space bits, the FRE bit 13 is also set.
Breaks received by the Console Terminal UART may halt the CPU, However, breaks
receivC,':d I?ythe Copsole Storage UART will not hakthe CPU.

10:08

MBZ (Must be zero)

'07 :00

Data-Contains the received data.

Transmit1erRf?gi~ters".,.Each U1\RThasa Transmitter CQntro1and Status

register (CSTS'.and
TXeS) and a Transmitter Data Buffer register (CSTD and TXDB). The data tob~ sent ~utis writte l1
into bits 07:00 of the CSTD or TXDB registers which are cleared by the RESET input. The format'
of the of th~ eSTS and Txes registers is shown in Figure 10 and Table 15 defines the fltlnctiori of
the bits. ,Figure 11 shows the format of the eSTD andTXDB registers and Table 16 defines the
functionofthe bits.'
, '.
..
".
1-140·

COll£is!ential and :proprietary

()8070605··

31

I:··:: :: : :

030~mOO·

Rol

RW RW

RW

'lable ~5 • MkroVAX78l}lTtansmittetlineat the user-selected IPL
le.veL The interrupt
vector
is also user programmable.
.
.
. These registers are cleared by the RESET
input.

RW WO

Figure 12· MicroVAX 78332 Timer Control Registers (0 and 1) Folmat

Table 17· MicroVAX 78332 Timer Control Registers (0 and 1) Description

Bit

Description

31

ERR (Error)-Set to indicate a missed overflow when the Timer Interval register
overflows and the If-if bit 07 is set.

30:08

MBZ (Must be zero)

07

INT (Interrupt)-c-Set when the Timerlntet'\,~l register overflows.·Ifthe IE bit 06 is set
when the INT bit is set, an interrupt request is posted.

06

IE (Interrupt enablel-Set or deared by the software to indicate that an interrupt request
should be posted when the INT bit 07 is set.

05

SGl. (Single)-:"'Wh~h the

1-142

RUN bit 00 IS cleared,~riting'a 1 to this bit causes the!imer
Interval register to be incremented by a value of L When the Timer Interval Count (IGR}
overflows because of the assertion of SGL, STPis ignored and the. counter is reloaded.
When the RUNbitOO or XFR bit 04 are set, write operations to· theSGL bit areignored.
This bit is always read as a zero.
Confidential and Proprietary

04

XFR' (Troosfer)~Writing a ofie to this bit causes the Timer N:ext'lnterval register to be
copied to the Timer Interval register. This bh is always read 'as a zero.

03

MBZ (Must be zero)

02

STP (Stop)- This bit determines whether the timer stops after it overflows. When this bit
is set, the RUN bit OOisse!, andthe Timer Interval register overflows. the RUN bit is
cleared and thec9untingstops.
.
."
.~

'!':' '. . ." ....

RUN..:..;\Vhefi thisbifis set, the Tirllei' Infd:val:nbglsfef is 'inc~fuented once per
microsecond. The INT bit 07 is set when the timerover£1ows. If the STP bit is set when

00

the timer overflows,theRUN.biti$cleatedb;tthe!hardware.

Timer Interval Count Registers (0 and 1)-These registers contain the interval count value. Figure
13 shows the format of the register information.

31

I: . :: ;:::. :; :}~E~'~1f~yA~R~+~+:;:::'::::::.1
" ' '. ,",,'

""

"'"

"f~)

'-""

,

""

' - ' ' , , ,,"

, , , , , , , , ' " ;,,".

,," " ,

REA.DOIIILY

Figure 1) • MicroVAXZ83J2 Timer IntewalCount Regist~(i:ra~d 1) Format

Thoet: NeXtIn~va1<:ountJl~gis~~(O!mdJ)_'tPe$e~gi~te,f$coqt~nfhe vaJ~e;that ~(IQaded

into theTil11er!nteryal C;Qunt.~~i*rs~tt;ranqverfI~~s PCcpr11edRrin ~sfl9,nset9!\l!r~ting ;t.1
to $~t XFR (bit:b~lof ~e.'Ti!pef C;q~~!re,gister(; l1ds.~~¥ter~~de~b)' theRE.~ET ~np~t:The
fprmat for the register in£prmatipn;isshpwnin'~i~ 14 ...
'.

;

'-,

-;

-::'" ,

'

,," <,,'

,

'

,;'"

',';,': -;

",,'

,

,,:,

,\:' ' "

READ;WRITE

Figure 14· MicroVAX 78332 Timer Next Interval Count Registers (0 and 1) Format

Timer InterruptVect.or.Registers. (0 and. l)dTheseregistets store.the interrupt vectp! value tp be
transferred to the cpu. An interrupt request is posted when the IE bit 06 and TNT bit 07 are
transitioned to a L When the SSC detects an interrupt acknowledge cycle and one of the timers is
set to the highest internal priority requesting aninterrtiplt;the internipt 'vecturfor that timer is

Confidential and Proprietary

1-143

transferred to the DAL. Thecotrespondihg interrupt request is then cleared.• I~t.~r~upt~quest~ pan
also be deared by clearing the IE or the INT bits. Timer 0 has the higher piiority.·The Interrupt
Vector ;registero$ are~Ieared by the RESET input. 'I'he format oithe Timer Interrupt Vector register
is shown in Figure 15 .. Table 18.defines the register bits.

Figure 15· MicroVAX 78}32 Timer Interrupt Vector Registers Wand 1) Format

Table 18 - MicroVAX 78332 Timer Interrupt Vector Registers (0 and 1) Description
Bit

Description

31:10

MBZ (Musfbe zero)

09:02

Interrupt Vectof-'-The interrupt vector address to be transferred to the CPU.

01:00

MBZ (Must be

Decode Channels
The Programmable address decoders are used to decode the address on the DAL to select channel 0
or 1. Each channel consist of an address decode channel Mask and Match register. When the AS
iriputisassertedand the bus cycle isatPU read onvrite'transaction, the addIb$sbn the DAL is
compll1:ed to all the hits of the Match register for which the corresponding Mask register bit is zero.
If the comparison is successful, the corresponding output strobe is asserted. The ADSO output to
the external logic is asserted to select Channel 0 and the ADS 1 is asserted to select Channell. Bits
06:04 of the sse Configuration register control the operation of the programmable address
decoder for Channell and bits 02:00 control the operation of Channel O. When the RESET input
is asserted, both output strobes are disabled and the Match and Mask registers are cleared.
Figure 16 shows the format of theAddress Del;ode 0 and 1 Matd) registers and the register bits are
defined in Table 19. Figure 17 shows the format of thl; Address Decode 0 and 1 Mask registers and
the register bits are defined in Thble 20.

Mwa

~moo

IMH:: :::: : ::: ~A;+++SJ+:::::::.: : :}H
RliAOIWRITE

figurtf 16- MicrvVAX 78332 AddressDecodf.Channcl (Qand 1) Match Registers forma't
1444

Confidential and Proprietary

,

Bit~iption
31:30

MBZ (Must be z~ro)

29:02

MATcI-i--Cont~s \:he add3!!istQ be,mmp~~red with the PAL. address ,

01:00

MBZ (Must be zero)

,

l'

Mmoo

~ww

HBZj : : : : : : : : : : :M~K~+++:
REAO/WRITE

:::::::::Hj

Figure 17· MicroVAX 78332 Address Decode Channel (0 and 1) Mask~~tFormat '" .

Thble 20 • MicroVAX 78332 Address Decode Channel (0 and 1) Mask Registers Description
Bit

Description

31:30

MBZ (Must be zero)

29:02

MASK-Each of the bits that is to correspond to ~n address bit of the Match
register is cleared. the re,maining bitsi~te set.

01:00

MBZ (Must be zero)

Test R e g i s t e r s ,

.' ". .... . ,

.

The ROM Data register (BA+OFO), Bus Timeout Counter (BA+OF4) and the Interval Timer
(BA + OF8) registers are used for test purposes during manufacturing and should not be accessed by
the user. The results of such acceS:sIt includes a~ internal RAM and provides
support for an external ROM. The IA}i:EO output provides interrupt acknowledge support for
other interfaces on the bus.

1·145

·lIlllIl

J ••.•.•

lAKED

SERIAL
II N ES

OSCILLATORS
AN D CLOCK

Figure .18· MicroVAX 78332 CPU to sse Interface System Configuration

I/O Space Assignments
The sse operates with the fixed I/O space and relocatable I/O space shown in Figure 19. The
address assignments for the external ROM and Base Address register are within the fixed I/O space.
The internal sse registers and RAM are assigned to the relocatable I/O space.

FIXED 110 SPACE

2004000Q

ROM

.

t

1 MB

I

20140000

BASE ADDRESS REGISTER

OFFSET .
FROM (BAl.

RELOCATABLE I/O SPACE

BA

SSC REGISTERS

..

+ 004

BA + 3FF
l,.,

"

.BA+ 40q

RAM

BA + 7EF.

NOTE.
BA = CONTENTS OF THE BASE ADDRESS REGISTER.

Figure 19· MicroVAX 78332 I/O Space Allocations

1·146

0.....
." .. '. !>_
.•:'....._.............
"~{&~'J'j.U'1

, Tj1~ ~OM is con~rolled by an external adqress latej1 that stores ,the appropl:iatebits of
DAL < 29:02 >. The sse drives the ROM chip select inputs and the data lines ofthe ROM: connect
directly to the DAL asshown. The ROM address space beginsataddress 20040000. The ROM~ust
conimriaHeast 8:K13(default). A larger ROM size can be seleCted by wHtingto sse Conf~iion
register bits 22:20 before making a ROM access at an address greater than 8 KB. The ROMs can be
16,' 32, 64, 128, 256,512 KB and 1 MB.The sse responCls all CPU reads operations within the
ROM space. Write operations to a space other than those spedfied are ignored. TheSSCcan be
used with fastotslow ROMs . Whenbit 23 ofthethea~esstillle~3.50J1anosecol:tds whkhis the default
condition,
E}\:cept
for write o'p€ratiQus t9t~~, alla~c~~s~\~re;327b~ts w;de 'll!ld longw9rd
alIgned.
. . ' . . . , ,'...
.
' . '.
, ' ... ' ... ..

to

The RAM and the sse ~istersare tocat~at; fixedof(s~~$fromthe BA addtes$~f 2014°000 Ipaded
into the sse Base ~4d¢~s'~gister. The! bAt<.29:02 »C(l~~in l\il~ longword ildd~~s .otihe
storage element being accessed. Byte wdtes .tbthe'RAM: ~fe st*ifl~d 'lJY OA:(,<:29,:02:>
the

bytem\u,k(BM.,,

•

••

..

Interrupt Logic
Because the s~e does hOt c6htaifianIAKEIlhJ?U~,itrnu$t. be~slgnedthe hig!lesfexterna1.d~ice
'priority that~s~ona~' to;i#t~rrtipt,a;tcri~!~~ '<):cl$s .~r it~; ~e~?llil'teci i~terruPt.l~v~l. .the
IRQ output from theSSe¢ol)n~ts totheapprop~iale CPU,1RQ.lineand the
Configuration register hits <::15 l,24>mustbtl,.set!:ospecifythisll!'JeI:'
InterruptRequests~the
requests an interrupt by assertmgthe =IR~Q"""'-<-:"n~>- output when any
of the conditions listed in Table 21 occur if their respective Interrupt Enable bits are set,

sse

Priority
Assjtwn~t

COhsOle'rermlmtltfARtfIteS~I~i'
R~aH9"
".' "'-, .c. "'" '" _ ,,-,-,' ,,-:, ,,':. "'. , ' .,.,
, '. Cbrlsple Stor~getIART ReceiverR,,:a.df

3'

,-.

',,',",.'

i/"':_"

'_,' ,,' '''.' V",'i ,-

'1,

--. __

'''"

:'

";""~

"

OOOOOOFO

,," ',: .-'"

4

.·OOOOOOF4

5

*Us¢r programmable and stored in Interrupt Vector regisi.ers.

• C~n&Q1e$,tqra~UAl{.TRec~jverEe~dY-WhelllEbit O.~andi:h.e DQNhh 07 ofCqnsele-Stonrge

Receiver-Status rGgistenr~si~ioJl.tpa~.

;

..

,'-

'

""

'

'''.,

' ,

,,,'

'"

,

" ".

'"

-

,~ ':

,,'

.

,'..,

'

,

Confidential' anu Ptopfie'tary

1-147

• Console Storage UART 1'ransmitter Rellciy...:..:When the IE bit 06 andtheRDY bit o7of the
,'Consoli StOrage Transmitter :register transition to Ill.
'
,

.Ti~er < 0:1 > "lCRoverflow''':''': When. the IE bit 06~d INT bit 070ftheTimer Contror'register
, transition to a 1.

'

Interrupt Acknowledge-1beSse respond~ to interntpt a«knowledgecyclesas follows;:

• If the interrupt acknowledge is not at the'IPl. level speCified by the SSC or if no irtternal ssc
interrupts are pending, the sse asserts the IAKEO oUtput to indicate that it has no interrupts
pending at the given IPL level.

',

• Iftheipterrupt acknowledge is at its IPL level, al1di(there is at least ope interllal sse interrupt
pending, the response of the SSC depends on the state of the IVD bit 27 of the Configuration
register. If the IVD is cleared, the SSC places the interrupt vector of the highest prioriFyinternal
interrupt pending onto the DAL, clears its corresponding internal interrupt request, and if no
other internal interrupts are pending, deasserts the IRQ < n > ou tput.
·I£IVD isset,the SSC clears itsii1ternal interrupt request for the highest priority pending internal
interrupt. If 'there are no other internal interrupts are pending, it deasserts the IRQ < n > 0utput.
• The deassertion of the DS input causes the deassertion of theIAKEO output.

Break Detect/Transmit Logic
The Cons~le Terminal andConsole Storage UAR,T~ include break detection and tral1smidogic. The
UART registers are described 1n Register sehion.
.
.
Break Detect,-The Console Terminal UART recognizes either 20 consecutively received space bits
(default) or a CTRL/P command received as a break condition, as determined by the CTP bit 150£
the Configuration register. The break generates a CPU halt operation if the halts are enabled and
the co~sole is not secured. The Console Sto~ge IJART rec~gnizes only 20' ~onsecutively received
space bits as a break condition. A break received by the Console Storagt UART cannot generate a
CPU halt. If either UARTdetects a valid break condition, The RBRbit 11 of the RXDBor CSRD
registers are set. If the break was the result of 20 consecutively received space bits, the FRE bit 13 is
also set. The RBR is cleared by reading the RXDB drCSRD registers and cati be set only by a break
condition received by the UART.
Break Transmit-Setting the XBR bit 00 of the TXCS 01' CSTSregisters cat],ses the UART to senhe
serial output line to the space condition. Clearing the bit termi.nates the break: The UART does not
react to a change in the state of XBR bit until it has finished transmitting the ,current character.
\XThen the XBR bit is set,the transmitter operates normally but theoutpur line remains low.
Therefore, the user can send dummy characters in order to time the break. After cl~aringthe XBR
bit, the user ~an provide an extended MARK ch,aracterbyqIIowing theJransmitter to idle for the
desired peribd: , ' .
.
" , .. ,
'

Halt Arbitration Logic
The console terminal UART,can.1'equesta CPU h~t whep, a .• break. condition is·. detected if the
SECCON input is not asserted. A CPU halt request can also be generated if th~ HAtT'IN iriput'frtinl
the external logic is asserted. Either of these conditions normal1y results intheas·seftion oUbe
1-148

Confidential and Proprietary

CPUHAtii6Utput bfthe SSC that conhects to the HALT'inplit o{theCPU. The halt 'arbitration
logic of the SSCmayconditional1y prevent;theGPU halttequestasdeseribed.:
ThehWt"proted:edaddress~pace of the ROM is defined by l>its 18:16of the. SSC ConfigUration
registe£.A CPU halt request is disabled when halt-protected space is accessed by anI-stream read
ttans'lktion;OneathI~stt611nreadtransactiOtl, theSSCdetermines whethertne target address: is in
the balt-protected space. If the address is in this space, then tlieCPtJllAtff'Obtput'is &isableduntiI
the next. ~.$tte~teadtranSactiQn,lf the .ild~$s is ;n9t, ili ithe,haIt;~pt'GteCt¢d s:paJ;e, then. the
CPUHAL~ outp~tis ~sertePuntilthenext l-~trt;aiMe~~:mmactionoccurs ..

l1aJt

Assertion of the HAL'I'IN input will assert the CPUHALi output if the
condition is enabled. If
the HALTIN output is asserte,d when the halt functions are disabl~d ,~tbehalt isfueWenaateCi,
the sse asserts'CP'UHAL'i' until haIts ateltgafn~isahJed6r''fntilthe ItAL11Ni ~tpUtis&;!isserted.

Iia break is received by theC6nsqle!erlhlnat UARt'~h~eHalt requd~s are'enableda~d .the
consOle is n6t ~cuted (Sf!et5N cfeassertecl); the'Ssd~sertlS'fhe CmI¥LT'oUfputulltil the halt
conditions are disabled, the cOfiSole issecured~ orthe.bteak conditionIsdekd bysofiware.

The softWare canexecute a ~ernel moo~H~):Tcomtnanclto,~u~~ CPUhalt ~henthe l1altsare
disabled. Asserting the RESET input
a:l$oer.ilible th(! ha1i::~quests. The R(j'fi4'o:utputisaSserted
wheiHhe halt t6n:$:tioos a~ enable(f.' i ;
"
'" ... ........ . . . . '
,
.. ,
.

\\'ill

Whe'l1 Wledwith,th~ CV4XCPU ,. t';sscd~s~tdet:ccti~~a~~ferencesthat"are~edto
theCVAJ{ CPUinte+nal cache: Whe~us;iwiththe,Mi~toVAi(~PU, acopY(~10vC)instru~tion ~o
the halt~prOtected locations disables the h~t'r¢qijests
until ihe1copY:.!' -transaction
is, complete, .'
i
. ', .
-, - ',"',
; ". _ i';.
<.",
I -,

Bus SupporiLogic

~

.

,

"

_; •

_!

. .' .... ........... '. '. ' .." '. .....

I

-I

~

i _.

!.,

............ , ....... '\ '" .... .' .'

,

:

.... .

the ssc dears and' shirts 'an internal counter. When AS is
deasserted,thecounteris stopped. \'qhen th,e counter reaches a value e'J-\jal!o the,\T~l.le loadedfu.to
the 'Bus Timeout Controlregister,·i:he coontetisstoppeoithelJTO;bit)1' in this regisrerisset,
the. ERR . output' is .asSerted ito' indicateithtltthe bUs' Cycle snbtiloalso.hIe acoossed.byCPUread and wdte
transactions, The register counts only when it contains anw'}zerOVa1ue·. The roVdockis driven
from the TB25Kinputbyan extetnal25,6cKHz oscillator. IfTB25K is connected to ground, the

Confidential ana Proprietary

1·149

tilTlebase fo): the.clock is suppli~d by thellO-MHZosdllatot at the.TB40M input whici1 aisoproviqes
the timebase for thebaudrategen~rator apd the Iptervaland P~ogtammable#metS.
The counter function is maintained during power£ailcopditions by the battery-backup supply to

the sse and to the. 25.6-KHz external oscillator.. If the BLObit 31 (Battery low) of the

.configuration register is set, the sse is reset and the register is cleared and remains cleared until a
nonzero value is writteriby software.
The Interval timer provides a 100-Hz input to the TOY clock and to the INTCLKO output. It can be
used as the INTTIM input to the CPU which drives the epu Ices register (Il'R #24).

ProgranuQable Address Decoder
The programmable address decoders (channel 0 and channel 1) selectively decode bus addresses
during epu read and write transactions to generate address strobe signals for external devices.
Each address decoder consists of a Match register and Mask register which are within the
relocatable I/O address space.
When the AS input is asserted, the address on DAL < 29:02> is compared with all the
corresponding bitsof the Match register that have been selected. The Match register bitsthat are
to be compared with bus address bits are selected by the Mas,!<. register. If a Mask register bit is zero,
then the corresponding Match register bit will be used in the comparison. The remaining bits of
the Match register that are not selected bya Mask register bit are not used in the comparison .
. When a match exists, an output strobe ADS 1 (channel 1) or AD SO (channel O)is asserted between
one and two sse microcycles (nominally 100 t~ 200 nanoseconds) after the assertion of the As
input provided that the bus cycle is a CPU read or write transaction and the assertion of the strobe
is enabled by ENA bits 05:04 for channel 1 or bits 03:02 for channel 2 of the Configuratiqn
r(,:gister.
.{\fter the ADS! or ADS2 output strobe is asserted, the sse can assert the .RDY output eight
micro cycles (nominally 800 nanoseconds) later to permit the externaldevice time to respond. The
RDY output is controlled by the RDE bits in the Configuration register. The deassertion of the DS
input causes the deassertion of the address strobe.
The.address decoders for channel 0 or 1 should be not be programmed with the RDY signal asserted
if another device in the system can respond to the read or write transaction programmed into that
channel or if the programmed address is located within the sse ROM, RAM, or I/O register address
space.
When RESET is asserted, th~ ADS < 0: 1 > output strobes are disabled and the Match and Mask
registers are cleared.
Some examples of implementing the address strobes are
• A channel can be programmed to respond to a single longword read address. The ADSO or ADS!
strobe is used to gate the value selected by external switches to the DAL. The SSCcan then assert
the RDY output to complete the cycle.
" A channel can be programmed to decode only some of the high-order DAL. The strobe is then
.used with an external decoder to select other devices .
• An address strobe can drive the chip select (CS) input of another peripheral dup such asa direct
memory access (MicroDMA) or vectored interrupt conttoller(MicroVAX VIC) .. The·· peripheral
chip must then assert the RDYoutput.

1-150

Confidential· and Proprietary

M~s!>f, Qpentti()l1

The sse operate$,ip..I1ormal j:nodeapd. battery~backup writedllta, .¥ielpYAX ,E~ re~#rejlprA~J~J?'i~ad,<;;V~¥ EP ~ite, ,dle,al)d
interl"1JPtacfq,!'\VI~Q~e;,
sse intetf~~es,a,sY9-chro.n9u$ly~the .M~clp~C~P, Qr;CVAX CPU.
Re(ertQth.~ 4cSpecificatigtts sectionforthe tnpls.ll,Ction t,imf~g;diasr~s 9~s~ribed}n thefollpwing
paragraphs.'.
..., . "
.
,.'.

The

CPU Read, CVAX:EP Read,' 6t lnterrupt kkno\\H~ge
,,
During CPU read transactions or interrupt acknowledge cycles, the CPU addresses the'SSC otthe
external ROM to receive data. A CPU read tra,nsaction ty;q~s 3minimulD pf, six~SC mip"OCy!=l!'[s
(nominally 600 nanoseconds). The
irlputfs,u~a~i>erte~l ~d tlie'.byte'paskBM <,3:lb.
inforrmitt6n h ig?<,~.Th0SSC Ijtt~h~stheinfo~mairQ~o~ ~tL < 31:00> • ~,andeS < 2:0:>
when the AS input· is assert&!. The' type '6f readactess isd~t~rthin:edb)r 'iheCS <'2:'OY input. .

WR

Dl,lring the first part of,a read <;}Tde, .the,CPU t~ansf~~,the adcl~~s,on the ])AL. If,the~ccess'is a
longWoid read,th~CPU traI1jife1'$th~ pliys~c~lOn~rd'1l.~ssonnNL ~29:02 >.If
aCcess is
a CVAX EP~ad, the CPU trlinsferS the proce!ls~rregistetnurn~er onDAL <::07 :02:;> arid zeros on
DAL< 10:08>. For CVAX systemi£ the 'ac:ceis is' aiiirttetruptaclcnoW'ledge'cscle, 'the 'CPU
transfers the priority of the interrupt being acknowle1;lged (IPL) on DAL<06:02>. The
nAL < 31:07 > ahdr>AL4 01:00>=,0,: With a MicroVAX !lyStem, the IPL is'on DAL ,
DAL<31;30>~'10,'andDAL<.29:0j:::>-\,l.The'CPU'dien>assedsitheAStnputto UidiCate that
the'address is vaIid:t'VhennbdevicempMdsro the addtess, the Skmayassert the BRRoutpuf to
indicate thata' bus timeobt" h a s o c c u t : r e d . ·
.
.

tlie

a

During the second part of a read cycle, the CPU accepts the addressed data ftom the bAt. If the
access is to internal storage, the sse transfers the required data o~PAL<31:00> and assens the
RDY. output. Ihe epu ,reads the. dataan~ d~~sserts, the,
to' end~lie read
transaction. Hfhe access.is·dire(:ied ai eJdernaloytewide k9M •.th~sse aSserts the ROMEN signal
when OS is aSflerted ,and thenperform& fo'ur'R9M rea~ s~~uc:n.c~$.lt·latches the ROM data and
increments. the ROMA))R< 1:0,> outPuta£\~.eachfeadopehttlO:n: 1'b~,~SC,the1l4eassertsthe
ROMEN o~tput,transfers .weunpackedk)~wordontP~<)1:00>',and assert,s the ID'SY
o~tpLtt. The'CPU reads this data and deas~rtsthe Asa~d .~, irl~uts .t6·~nqth~ read trans~ction.

XSatid .P'Sinputs,

If the ,aec~ss ,is di~cfed t~al1 ~~er~ ,~~;'~hykie,I\9M,.$e~S~~s~t~th~R9MENo~tPutwhen

the DS input is asserted and then performs two ROM read seqUences. It lat<;:h~s t~e ROM data after
each read operation and inverts the ROMADRI after the first read. The sse then deasserts the
RaMEN output, transfers the unpacked longword to DAL < 31:00 > , at,lAas,serts the RDY out;put.
TbeCPUreads the data. froIT). the pAl.;. and deasserts the AS and.i$ inputs to end the read
transaction.

If the access is directed at externallongwordwicle ROM, the sse asserts the ROMEN output when
the DS input is asserted and latches the ROM data when it is valid. The SSC then deasserts

Confidential and Proprietary

1-151

ROMEN, transfers the latched longword on DAL < 31:00 >, and asserts the RD'¥ootput.' The'CPU
reads the ROM data and deasserts the .j\$. andm outputs to eh.d,the read·trahsacti:on:· .
Duririgan Interrupt acknowledge CYcle, the .
tra'nsters'. the interrupt v~ctor . ·data op
DAL < 09:02> and asserts the RDY outPl,lt. The CPU reads thIs data and then deasser'ts the AS ahd
DS outputs to end the read transaction.
'.
.

Sse

CPU Wri.te and CVAX EP Write
During a write cycle, the CPU writes information to storage elements in the sse. A writecyde
requires six sse microcycles (nominally 600 nanoseconds). The first half of a writecycie i.s'si1'\lilar
to a CPU read transaction except that the WR input is asserted. The CPU transfers the address and
the opetand length onto DAL < 31:02> and asserts the· AS input. If the access is directed to
inter~al storageinthe sse, the sse latches the data from DAL<31:00> after the DSinputis
assert~d. The BM < 3:0 > linesspedfy which bytes of the target Iongword should be written. The
sse stores the data and asserts RDY output. The CPU then deasserts AS and DSsignals' to end the
write transaction. Write transactions to the ROM address space are ignored.

If a device does not responds to the addre~s, a bus timeout may occur and the SSC will assert the
ERRoutput.
" , . . . .
MkroVAXExternal ProctlssOr Register Transa.l;tions

. ..

,

.

The SS<;: responds to two sequences of MicroVAX External Proces.sor Register transactions: an EP
Write command followed by an EP Read Response and an EP Write command followed by EP
Write Data command.
During itn EP Write command/EP Read Response, the CPU rt;:ads data from the sse. In th~ first
part ()f the transaction, the CPU performs an EP Write Command transaction. TheDAL<; 05:00 >
.contain. the address of the required register and DAL3 i is a 1 to indicate that the read transaction
will follow.
.
The sse latches the DAL <:.3 1:00> information on the rising edge of EPS input. Duringthe next
two SSemicroCYcJes (one MicroVAX microcycle is nominally 200 nanoseconds), theSSCaccesses
and stores. the requested data. After this delay, the CPU executes an EP Read Response cyc;le during
which the sse uses the EPS signal as a strobe to transfer the datato DAL < 31:00 > andte pulldown
the.eS2 output level.
EP WriteCommand/Write Data
The CPU writes data tothe sse during this transaction. In the first part of the tninsa£;tion, the CPU
,~rforms an EP Write Command transaction .. The DAL <: 05:00 > specify the •location of ,the
~quired register. When DAL31 bit is a 0, a write transaction will foll(jw. The .sse transfers the
DAL < .31:00 > information on the rising edge of EPS input. In the next MicroVAX microcycle, the
sse latches ~he data from DAL<3l:00 > on the ris,ingedgeofEPS. The sse stores the qa,ta
internally during the following two sse microcyc1es. No accesses may therefore be directed at the
sse fortwe sse microcydes (one MicroVAX microcycle is nominally 200 nanoseconds) after an EP
Write Data transaction.

Trimsactidn Time :Estimates
Table 22 shows the estimated maximum transactiontim~ for· a longword, word; and byte transfer
when the epu and the sse are operating at 40 MHz.

1.152

Confidential and Proprietary

-,

Preliminary

Thble 22 • MicroVAX 78.332 sse EstilllatedTransaction Times
Access Type

eVAX

MicroV4X
Lon~Word

Byte

Longword Word

Byte

EP Read

600

600

EP Write

800

600

Internal RAM Read

800

700

Internal RAM Write

800

600

250 ns External ROM

1000

1400

2000

1000

1300

1900

350 ns External ROM

1000

1600

2400

1100

1500

2300

• Intet;facing Requirements
Figure 20 shows a typical system interctmnectioh of the sse and MicroVAX CPU or CVAX CPU.
The input and output signals between the, sse, terminals,ande~ternal devices are also shown.

Confidential and Proprietary

------_..--.-----_._-_.._-_._.._._-----

1·153

~~-':2:0> (MicroVAX) -CSlOP<2.0> (CVAAl ~
EPS -~- (MicroVAX ONLy)

------l

I

DAL<31,OO> - CPU

-

BM<3:0>

- - - !

(MicroVAX DR CVAX)

- ROY

ERR - - - - - - - ,

IRQ<3,O> - - - - - - -

CS<2:0> OR CS/DP<2:0>H-f--HH--H-+-j

ClKI

- l:ffi-·. - - - - - - - - - - H - + + I - + + H

. _ - CTDI-!~--~"I
+ - emo - - - I

TO AUXILIARY
I/O DEVICED

TO EXTERNAL LOGIC ...._- ADS< 1;0> -

TO NEXT peRIPHERAL

As ---~------+++-+_H
- DS---------MicroVAX 78332

TO VDO/VSS ON BOARD

TO I/O SYSTEM CONTROL

DAL<31 :DO> -~---+-H-+--H---H

iliVk3,O> -------+-+--I-+--H-I

eSDI _ - eSDO - - - - -

SYSTEM
_ - IAKEO

---I

_ _ IORESET - OPT5~:0>

SUPPORT

CHIP

WR---------

--- ROY - - - - - - - - - - - ERR--------~­

LOW-POWER
SENSOR

-~--

FROM EXTERNAL [ - .- . $ICCON
LOGIC OR
- - RESET - - ----- - HALTIN

I

(SSG)

:

RUN - - - - I

SWITCHES

I

IRO - - - - - - -

OSCillATORS

---

TB40M

40 MHz

TB25K

25_6 KHz

CONTINUOUS VOD - - - - - VDDI - -

R ~ LOG2 (NUMBER OF BYTES IN ROM)

DAL +-+-+-+H---H

ADDRESS LATCH
--

I
I I

TO REST OF MicroVAX/CVAX SYSTEM

Figure 20 • MicroVAX 78332 SSC to CPU Typical Interconnections

Power Supply Interfacing
A typical block diagram of the power supply and external power control circuit is shown in Figure
21. The power circuit provides continuous power to the Time-of-Year (TOY) dock and to the RAM
circuits to maintain memory data during a power interruption or failure. During normal operation,
the power supply provides both V001 and Voox voltages to the sse. During battery backup mode,
the power source is switched by the power control logic to the battery and the VODI input provides
the power to maintain the TOY dock and RAM. The VODI also provides continuous power to the
external 25.6-Hz oscillator to maintain the roy dock operation.

1-154

Cortfidentialand Proprietary

1 - - - - -..

RESET

CONTINUOUS
I-PO~W_E_R_ _. . VOOI
POWER
SUPPLY
12 V.5V

POWER
CONTROL
LOGIC

SUPPLY POWER

78332
SSC

VOOX

"

BIO

CHARGE
CURRENT

Figure 21 • MicroVAX 78332 Power Supply Interconnection .

The power connections to the sse ate shown in Figtite 22, f-ach V;o;and Vooxpinshould be
bypassed to Vss with a O.01-F capacitQr}ocated as dose to the package pin as possible. All Vnnx pins
should connect to the same supply. Both Vom pins conned together and are bypassed with asingle
O.33~F

capacitor.

CONTINUOUS ---,r-....,.--------------,=-'~-.-.-,....,.,....,.,....,.-,."
POWER

64
VDOX

POWER

SUPPLY '--,----..,.---'-,.........:..,

VDOX r3~3=---r-:-~4r--,

vss

. Figure 22· MicteVAX 78332 Power Supply Connections
Confidential and 'BfC>prue~ary

1-155

. Specifications
The mechanical, electrical, and environmental characteristics and specifications for the sse are
described in the following paragraphs. The test conditions for the electrical values are as follows
unless specified otherwise.
- Ambient temperature (TA): -55°C to 125°C
• Power supply voltage (VnDx): 5.0 V ±5%
• Continuous supply voltage (Vom ): 5.0 V ± 10%

Mechanical Configuration
The physical dimensions of the sse 84~pin cerquad package are shown in the Appendix.

Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
• Supply voltagdVoo ): 05V to 7.0 V
-Input (Vin ) and output voltage (Voo '): 0.5 V to 7.0 V
• Ambient temperature

cr.'): O°C to 70

0

e

- Storage temperature (Ts): 55°e to 125°e

Recommended Operating Conditions
- Power supply voltage (Voox ): 5.0 V ± 5 %
• Power supply voltage (Vom ): 5.0 V ± 10%
• Operating temperature (TA ): O°C to 70 0 e
- Relative humidity: 10% to 95% (noncondensing)
- Power Dissipation: 1.0 \YJ

dc Electrical Characteristics
The dc electrical parameters of the sse for the operating voltage and temperature ranges specified
are listed in Tables 23 and 24. Refer to 1able 1 for the pin designations of the signals listed in the
tables. Table 25 lists the characteristics output and 25. Refer to Figure 23 for the output load
circuits used for the teSt.
Table 23 • MicroVAX 78332 de Input Pal'lbnceters
--------------------~--------

Symbol

Paraln~ter

High-level

------~---------------------------

Test Condition

Requirements
Min.
Max.

Units

2.0

V

3.2

V

input voltage
except TB15K input
TB25K input

1-156

eonfidential and Proprietal'Y

Symbol

Parameter

V1L

Low-level
input voltage

Test Condition

Units

0.8

V

10

MA

Input capacitance
except TB25K input

12

pF

TB25Kinput

15

pF

0< Via < 5.25 V

Inputleakage
current
C'n

Requirements
Min.
Max.

-10

lable 24 • MicroVAX 78H2 de Output :PaUameters
Symbol

Parameter

'fest Condition

Vm /

High-level
output voltage

IOL=3.2 rnA

VOL'

Low-level
output voltage

IoH=-2.0 rnA

VOL'

Low-level
output voltage

IoL=23 rnA

10H Z

Output leakage
current

0< VOH < Von

VOH}

High-level
output voltage

IoH=-8.0

VOL'

Low-level
output voltage

l oL =10 rnA

Requirements
Min.
Max.
0.4

Units

Load
Cireuit

V

Fig23A

V

Fig23A

0.4

V

Fig 23B

10

A

Fig 23B

V

Fig 23C

V

Fig 23C

4.0

Von-1.0
0.4

'Outputs DAL < 31:00 > , eTDO, CSDO, CPUHALT, ADS < 1:0>, INTCLKO, 10RESET~IA,~O,
ROMADR < 1;0> , and ROMEN. Q~tPl1t, signals capable of clriving a £an~out loadpf eight LSTTL
loads
.
or
two standard TTL loads.
'Outputs ERR, RDY, ""IR""'Q""-<::-n-:>"", and CS2. Open-drain pulldown output capable of operating with
a 250- pullup resistor.
'Outputs OPT<3:0> and RUN. OPT<3:0> capable of driving TTL or low current LED
indicators.

Confidential and Proprietary

1-157

.1111011·

Preliminary
D1
Rl
FROM· ·O:-'·....,..-'--"--*-,--'-"W.........
OUTPUT

-------o +5 V

I

05

D4

03

D2

R2

Rl :
R2:
Cl:
D1 to 05:

- ' - CL

12K
1.7K
130 pF

lN4152

I
LOAD A

FROM
OUTPUT

Rl

O>--lr---'VVI..,...----O +5 V

-:;;r CL

250 OHMS
100 pF

Rl:
CL:

lOAD 8

01
Rl
FROM
OUTPUT o---,r----+4-----'V\fv----<> +5
02

R2

v

Rl :
R2:
CL:
01,02:

400 OHMS
370 OHMS
100 pF

lN4152

LOAD C

Figure 23· MicroVAX 78332 de Output Load Circuits

ac Characteristics
The clock input waveform and timing symbols are shown in Figure 24. Table 25 lists the clock
input timing parameters.

telR

Figure 24· MicroVAX 78332 Clock Input Wavefo11tl
1-158

Confidential and Proprietary

. .II
Table. 25- MicroVAX 78332· Clock Input Timing Parametet.$

Symbol

:Definition

telR

Clock In rise time

4.5

tC[F

Clock In fall time

45

teIH

Clock In high

tell

Clock Inlow

telP

Clock In period .

Requirementstns}
Min.
Max.

~,

8.0

~

25Q

Figure 25 shows the' timi~g and sy~holS Jor the sse i;ntializiltiol1 and Table 26 lists the
initialization parameters. The following specifications apply to the signals.
1. During cold-start powemp, the order in which VDm and Voox are powered up is unimportant, and
the Bill input is ignored.

2. For total power down of Vom and VO[)x with no battery backup, the sequencing or transition
times of VDm and VDDX ire noi specified aQd the RESET input need not be asserted.
3. In any transition to normal operation, the RESET input should not bedeasserted until the
eLKI, TB40M, and all other input signals are within specification.
4. The deassertionof the RESET inpu.t initializes the sse to its powemp state.TheSSe should not
be accessed until at least 1.0 microsecond after RESET is deasserted.
5. In battery backup mode, the high level of input signals TB25K, Bill, and R.ESET must reach the
value of V[)OI' All other input must have a low impedance to ground during battery backup and
should be powered from VDDX during .normal operation.
.

I

MjRMAl

O?ER/~TION

..

voox

f.iORMAl
QP(IWll(JN

~y,----------------,.\~---

~-rflsv --i

;"'-~VR5 ---..1

,

i
i

AESf[ - - - - - - - - - , ' \ ' -_ _ _

vnDI

-1

eAITERY BACKUrOf't.RAfION

I

l~RS

11;\\

f----

IVRS ..

~

1li77l1Jt!2Mhl

--~------------.

riG5
WHEN
ASSEHfED

NOTE:

:.:: UNKNOWN INTERMfDlATE VOtTA,sE

Figure 25· MicroVAX 783321nitialization Timing

Confiidential and Proprietary

1-159

Preliminary

MicroVAX78l~2

Table 26 • MicroVAX 18H2IrutialliatioriTiming Parameters

Symbol

tBLown

Definition

Requirements (ns)
Min.
Max.

VOOI or Vnnx in normal operation range to RESET deasserted

o

RESET asserted to VnOl or Vnnx out of normal operation range

50

BLO asserted to RESET deasserted

50

BLO pulse width

25

The timing sequence for the CPU Read, CVAX EP Read, and Interrupt Acknowledge transactions
are shown in Figure 26. Table 27 lists the timing parameters for the transactions shown. The
specifications listed are relevant· for transactions directed only at the sse except for t ASH andtASL
parameters.

'WHEN ASSERTED

Figure 26 • MicroVAX 78332 CPU Read, CVAX Read, and Interrupt Acknowledge Timing

1-160

Confidential and Proprietary

Preliminary
Thble 27 • MicroVAX 78332 CPU Read, CVAXEP Read, and
Interrupt Acknowledge Timing Parameters

Symbol]

Requlrements(ns)
Min.
Max.

Definition

AS ass~rt:ed to RDY asserted
CSR access
RAM access
250-ns longwordwide ROM access
250-ns wordwide ROM access
250-ns bytewide ROM access
350-n8 Iongwordwide ROM access
3.50-ns word wide ROM access
350-nshytewide ROM access

t ASDS

tDSDAT

t RMRDy

c:

150
250
550
,850
1450
650
1050
1850

Address setup before AS asserted

15

Address hold after AS asserted

10

AS asserted to ADS <.n > asserted

100

AS asserted to DS asserted

25

Address strobe high time

45

AS asserted to IAKEO asserted

150

Address strobe low time

75

250
350

650
950
1550

750
1150
1950

200

250

DS?d~sserted.to DAL line high impedance

DS deassertedto RDY deasserted

50

RDY asserted . data valid

75

RDY asserted to DS deass.erted

75

ROMEN deasserted toRDY asserted'

75

'Except for t,\SH and tASI. values, the above specificationsare'~devant only for transactions directed
at the SSC.
Figure 27 shows the signal timing for the CPU Write and C;Y!q. EP Wt;ite tmnsactions. Table 28
lists the timing parameters.
.

Con£ident~al

aru:i I'roprie~ary

1-1:61

<

DAL<31:00>~
II

:i'

7o~rA

,"',-"'"

»)'----'-'-'-'-------

.II
~fbAT~1~-j

I'

1':

..

~fi2:0> ~"..... ....,._ _--...,I,----_ _-,-------------........,...
'ADRAS

J1-- f.-

I

I

'AD'flO

~-------------+

- '.5H-1

----iC=

~--'-I
"\SBMl_
____

-

I

t ----

---+--.------.----+I

I

VALID

--=-'1------ ,tD'Ds~A1

-:--~_'_AS_DS_

'ASL

______________

I

~)----'---"-----

1__~~

'WRITL---------t-___. _

'"DVD5-:--~rr----I

I

.-.'

----~I------------~~~

r--------

ROY

'ASADS

'.

...... 'DSRPY

I)

--------1

L-__ ----~'----.---------1-----,-I/
'\
/r----IASIOR

'WHEN ASS[;IHED

Figure 27· MicroVAX 78332 CPU Write and CVAX EP Write Transaction Timing

Table 28 • MicroVAX 78332 CPU Write and CVAX EP Write TransacnonTiming Parameters
Symbol'

Defmition

Requiremehts (ns)

Min.

Max.

tADRAS

Address setup before AS asserted

15

tAoRHD

Address hold after AS asserted

10

tASADS

AS asserted to ADS < n > asserted

100

t ASBM

AS asserted to byte mask valid

t ASDS

AS asserted to iSS asserted

0

t ASH

Address strobe high time

45

tASIOR

AS asserted to IORESET asserted

175

tASL

Address strobe low time

75

t ASRDY

AS deasserted to RDY high impedance

tBMHD

Byte mask hold time after AS

275

tOATHD

Data hold time after RDY asserted

75

tDSDAT

DS asserted to data valid

50

tOSRDY

DS deasserted to RDY deasserted

50

1-162

Confidential and Proprietary

~,"""~~"""",,~~~~"""',,Tl!!l"O

200

75

275
25

...
Symbol'

Requirements (ns)

IORESET asserted to RDY asserted
RDY asserted to DS deasserted '

Min.

Max.

775

8002

75

,.' fOO

DS asserted to RDYasserted

2002

'Except fort ASH and t ASL values, the above specifications ru:~.relevant only rbiiransactions directed
at the sse.
'When ~IO=R"'E""S::O;E::-;:T:;:; is asserted, t[ORDY determines when i{DY.~~sseJtedap.9~t~!lJP\is i)ot used. '
Figure 28 shows the the minimum transaction timing for the MicroVAX EP Wr,iteCommand and
Read Response transaction and Table 29 lists the timingParametet~~ . .~.

Figure 28· MicroVAX 78332 MicroVAX EP Write and Read Response Transaction Timing

Table
29',' •_MicroVAX
78332l\.UcrpVAX
lW
Wri~.an4Rf.ni~.~t.e~~
:' '_,
- ,: _-:.
''',
,.• ", >"
_","
-:~;

Symbol'

< -

",-./

;, , . "

'.' ' • .'

i

' .. J "

Definition

'"

_

.:. -,

'"

'

Min.
tADlIF.P

'

I , , " , ' _,', ' " _

-".'d,'

__-~ _,,'

,

Requirements (ns)

Address setup time before EPS deassertion

15

Address hold time after EPS deassertion

10

Max.

tcS2HD

CS2 hold time after EPS deassertion

25

tOATHD

Data hold time after EPS deassertion

25

Confidential and Proprietary

1-163

Symbol'
tDNEXT

Definition

Requirements (ns)
Min.
Max.

75

EPS deasserted to next assertion of AS
EPS deasserted to next assertion of EPS

225

EPS deasserted to data valid

225

325

EPS deasserted to CS2 asserted

150

250

EPS asserted to data valid

50'

EPS asserted to CS2 asserted

25'

EPS assertion time

75

Last deassertion of EPS to assertion of EPS

225

'Except for t EPL , tLASEP, and tDNEXT, these specifications are relevant only for transactions directed at
the sse.
'Although the DAL will be driven tllP2AC time after EPS is asserted, the data will be valid after tF.?IAC'
'CS2 is deasserted after t EPlCS , however, it will not be asserted until twcs after the second assertion
of EPS.
The minimum time for MicroVAX EP Write command and Write data transaction are shown in
Figure 29 and Table 30 lists the timing parameters.

EPS

~ L"EP'--fJ
ilASEP---J

DAL<3~:OO>

\~-'EPL_._1.
-1

--,

~----!EPEPW----·

-~ I

_ _ _ _ _ _ _ _-«r-A-OO-RH-.S

lI
CS<1.0> _ _ _ _ _ _ _ _.....(

'AOREP

I

'I

L

-: 'OATEP~
--.j

'DAT!-ID

~

~'-

~\-fl----_---_-_ _- - _ -_ _

I - - - - . E P 1 1 0 ....

lciREm

(r---'-OA-TA~~r-_ _ _ _ _ _ __

tADRH'O !

VALID

~

- - - . - . O N l X T - . - - - -..
.,

I
_ _ _ _ _ _ _ _ _ _-'-_ _

---Jf, ',

IVYHEN ASSERTED I

)

-~

I
r-_110RH~-----i
I
/'r------

\

\

THE TAANSACTIOfll MAY BE WIDENED HERE
NO

sse ACCESSES ARf! AlLOVVED DURING THIS Dl.:lAY

Figure 19- MicroVAX 78JJ1MicroVAX EP Write Command and Write Data Transaction Timing

1-164

Confidential and Proprietary

...

Preliminary

MicroVAX 78332

Table 30· MicroVAX 78332 MicroVAX EP Write Command and Write Data Transaction Parameters

Symbol'

Requirements (ns)

Definition

Min.

tADRHD

tDNEXT

Address setup time before EPS deassertion

15

Address hold time after EPS de assertion

10

Data setup time before EPS deassertion

15

Data hold time after EPS deassettion

15

EPS de assertion to next assertion of AS'
EPS deassertion to next assertion of EPS

225
225

EPS deassertion to IORESET assertion

175

Address EPS deassertion to data EPS deassertion

150

EPS assertion time

75

IORESET assertion time

200

Last deassertion of EPS to assertion of EPS

225

Max.

275

200

IExcept for tEPL, t LASEP , and tDNEXT, these specifications are relevant only for transactions directed to
the sse.

Confidential and Proprietary

1-165

· Section 2-Bus Support Devices
The bus support devices provide the interfaces for CVAX memory bus, VAXBI bus, and Q22-bus.
CVAX 78588 Metyory Controller-The CVAX 78588 CMCTL is a high-performance dynamic
memory controller for CVAX systems. It provides an interface between devices on the CVAX bus
and the MOS private memory interconnect bus for memory arrays.
CVAX 78711 Q22-bus Inter/ace Chip- The CVAX 78711 CQBlC provides an asynchronous interface
between the CVAX CPU bus and the Q22-bus. It supports byte, word, and longword transfers and
block mode DMA transfers.

DC514 CMOS VAXBI Bus Inter/ace Chip- The DC514 CBIC is a high-performance interface used
between the VAXEl bus and a user-developed interface of a node. It combines the functions of the
the VAXBI 78742 BCAl and the VAXBl 78732 BIlC.

1

. Features
• High-performance CMOS dynamic-memory controller for CVAX systems
• Two error checking modes; 7-bit BCC or single-bit parity
• Address multiplexing f91' 256 Kbit by 1 and 1 Mbit by 1

• RAM access

of 120 and 150 nanoseconds

• Synchronous or asynchronous interface to DNlA devices
• Optimized write-through cache control
• Support$ memory array diagnostics
• CPU interface compatible with CVAX Bus

• Integral refresh logic
• Single 5-volt

supply

Description
The CVAX 78588 Memory Controller (CMCTL) is contained in a 132-pin package and
provides an interface between devices on the CVAX bus and an MOS private memory interconnect
(PMI) bus to memory arrays. The CMCTL performs read or write operations initiated by the CVAX
CPU in synchronous mode or initiated by external DMA devices connected to the CVAX bus in
synchronous or asynchronous mode. The CMCTL controls from one to four memory arrays and
one, two, or four banks of dynamic random access memory per array. The CMCTL allows mixed
RAM sizes and provides error checking between arrays. Figure 1 is a functional block diagram of
theCMCTL.

Figure 1 • C\1,1X 78588 Memory Controller Functional Block Diagram
Confidential and Proprietary

lI

!rill an4ISigna1De~
TheCMCTL operates with the I/O signals and power and ground connections shown in Figure 2.
The signals are summarized in Table 1 and the signal functions are described in the following
paragraphs.
'

V5SX

117

"

-

~

~

N

".

-

0

~ ~ §~

~

~

0

0

M

0

" @ill Zl

~

:;; :;:

~

. '"
~

M

~

",-,

- <> gj ::: '" "''" :if

~I'h

~

'"

;l;
OJ

VSSX

82

COAL 1 1

119

,81

Cp.t>.i.l0

120
121

80

CDAWS

MD17

10

CDAW8

MOlo

122

MOl{)
MD19

MOlE!

.I\IID15

12,.)

NlD14

124

MD13
MD12
!VDll

MOIO
MOO9

MOOS

,.
n

7,

,,125

r----------------~

I

'"

131

MooB

132

:

iI

".

12'
HO

M007

I

MEMORY CO"iTROllFJ,

I

Moofi

I

MOOl

I

r

I
I

MODO

L _______

M038

10

MD36

11

MDJ4

~

,.
J.

If$SX

17

6.

I

I
I

Mool

6'

I

MOO3

MOO,,"

.,

~.,

I

i'CAWfY !)OWN)

I

~~

____

CDAlO6
CDAlP5
COAloa
COAlO:)
C,OA~Q2

CDALOl

CPALOO

iWf
fi9

I
I

DIN< 18588

I

VSSI

"
"

I
I
I

I

VDOl

M03}

,.

7$

COAlO7

54

.3

.J.2

I

C!lrn':l'
, 'vs;it
VDDI

=P:l
CSDPl
~."'

WR
REm'
~lAA

60
,5£f

~~

12
MOj~1

M032

13

"

'"

g

~ ~

N

~

~

'0

'" '"

N

'"0,

1)

g ;;

N

"

N

~

M

;:: ::; " '" 'I
~

;;!

'J

~
~

.

NOTe!;:

V00X AND VSSx ARE POWER AND GROUND FOR THE Qurpt;T DRiVERS,
VDDI AND vSSi ARt: POWER AND GROUND fOR THE INT€RNAL LOGiC.

Figure 2· CVAX 78588 Pin Assignments

2-2

.

.,

1S

Confidential ~nd Propriet~ry

51

~

;-

~

'iI :il

RIW
~
V$SX

.....

Preliminllty
Thblel·'CVAX7858SPUlll.fid Signal Summary

Pitt

Input/Output' Oefinition/Function

59

input
BM

Addre$sstrobe~Indicates that the (:VAX bus contains
valid cOntrol and address information.

input

13yte masks-Specify which bytes on CDAL< 31:00>
.~ontain vaUd information during memory write opera-

tions.
32-35

CAS<3:0>

56

output

Column address strobe-:--Asserted ... during memory
operations to indicate that MA <9:0> lines contain
valid column address information. In fast diagnostic
InOde; 'the CAS < 3:0 > lines are asserted simultaneously, 1ti normal diagnostic mode or signature read,
only ofleof CAS<3:0> is asserted. The CAS<3:0>
lines are deasserted during refresh mode.

output

Cotreeted read data-:--During memory read operations,
this line indicates that the data 011 CDAL< 31:00> is
correct. During masked memory write operation, it
indicatesthat the CDAL < 31:00 > eontains correctable
memory q;;tta in the read part of the operation and no
pacityerror.

1

69,66-64 CS/DP < 3:0:> input/output

104-85,

Contr6fJfatus/data parity-Transfers cycle status and
data parity information.

CDAL <' ~ 1:00> input/output (VAX data and address-Transfers 82-71 address and
data information between the CMCTL,CVAX CPU,
an.dexternal DMA devices.

57

DMA grant-Asserted to indicate that a DMA operation is in' process. When deasserted, it indicates that

input

. the opera,tion is initiatedpy the CVAXqPU.
70

input/output

Data parity enable-Enables patitychecking and indica~es thanhe CS/DP<;J:Q.:> contain ~alid parity inforpata strobe-Asserted during read operations to indi.cate that the CMCTL can transfer information on
·(])AL <31:00> and during write operations to indi~
care thllt CDAL< 31:00 > contains valid data.

input

inputtoutputE~ror""'-Indicates abnormal termination of the ~ur~nt

52

bus (.)'cle. The ERR and RDY inputs may be.s;mUl&,
neosly asserted to request a retry of the bus cycle.' .
20-29

MA<9:0>

output

Memory address-Time-multiplexed output speCifying a row, column, or memory refresh address.

Confidential and Proprietary

2-3

Pin

Signal

61

MCLKA

input.

60

MCLKB.

input

<,::!ock A-Pro",id~ t~. time base to the,CM.CTL and is
180 degree~ out of phase with the MCLK13 input .

t;

.' Clock B-Provides the time base the ClI.1.CTL and is
180 degrees out of phase with the MCLKAinput.

9-15,
MD<38:00> input!<;,,utput Memory data-Provides memory data between the
105·115,
CMCtL and the memory arrays.
118-132,
output

Memory error-Asserted as an interrupt to the CPU
when a parity error is detected on CDAL < 31:00 >
duringa,CVAX CPU single-transfer unmasked memory
:write operation.

55

NLMR

output

• Noruocal memory reference-Asserted to indicate that
thetncmory, loaded from CDAL < 31:00 >, is not
\Vithin.therange of tbeCi\1CTL.

38.41

RAS<3:0>

oUtput

•'Row address strobe- Indicates which MA < 9:0 > lines
l¥wea valid row address and which MD lines have a
valid -coqlmand for a memory read or write operation.

input/output R.~ady-"-'Asserted to indicate normal termination of a

53

cutrefit OOS cycle. The RDY and ERR inputs may be
sirri41talleously assert;;:

inf9.ftp,afipn to indicate a refresh operation and with
the CAS < 3:0> information to indicate that lines
hID < 4;0> contain signature read information from
·.theCMCn,.

16

TRIOUT

input

1Hree·state'outputs-Assertedto indicate that all outPUtS~. high impedance.

Write enable-Asserted with the CAS < 3:0> informationrb indicate that the MD < 38:00 > information
. is valid. Ifdeasseriedwilli the CAS<3:0> informaiJon.;the
MD < 38:00 >ib'lormation is CMCTL inputs .
.".'.'
-t--·:
- -,',

WR

input·

, WriteC"-'!\sserted to specify a read operation and deassertedfor awrite operation .

2,1$,30, VDD
36 1,37,42,
50,67,84, .
116,1,17,

ipput

19,31,43, Vss
68,83,117

input

2-4

.Voltage:-power supply voltage

Ground~Common ground reference.

Confidential and Proprietary.

Preliminary
OatA:.artd Address Lines
CVAX~ and. atldress {CDAL < 31:00 >.-'-Bidirection~ time-multiplexed lines used to transfer
addresses and data betweer; the eMCTL, CVAX CPU, .and eXternal DMA devices.
During the first part of a read or write cycle, these lines provide address and control information to
the CMCTL TPe information transferred during a memory read or write transaction is listed in
Table 2.
Table 2· CVAX78;8S
IWtd ()l' Write COAL Information
,
~i

j

COAL
31

.}O

Length

CDAL

29

Type

L

L

hexword

L

m~~ory spacetongword address

----~------~~--------~--~~------~

L

H

longword

H

L

quadword

H

H

octaword

H

I/O space

CDAL

COAL

<28~02>

<::01:00>

. for transfer

ignored by
'CMCTL

During the second part or amemoty or control status register (CSR) wr{teoperation, the
CDAL <31:00:> provide information to 'theCMCTL. During the second part ofatnemoryorCSR
read operation, the CDAL< 31:00 > transferinformationfrom theCMCI'LDUrUig memory read
operations, the data on the MD < 31:00 > lines are transferred to the CDAL< 31:00 > . During a
memory write operation, the data on CDAL< 31;00> is transferred to the MD < 31:00> lines.
Address strobe (AS)-This inputis asser.tedl;>y the ~ternaJ logic to indicate that the CVAX bus
contains v~id control and addre$.s ibformadotl. When assiried, .the CDAL < 31:00 >. and control
signals BM < 3:0> , estDP < 3;0> , and WR are evaluated. At the conclusion ofthe bus cycle, the
external logic deasserts AS.
Byte masks (BM < 3:0 > )-During memory wrjteQperatjpps, these inputs specify which bytes on
CDAL < 31:00> contain valid information as· shown in Thole 3. The byte masks are net used by the
CMCTL· during configuration register (CSR) read or write operations or duting memory read
operations.
Table.} • CVAX 7S588 Byte Mask Assignments
BM<3:0>*

Valid Bytes

L

L

L

L

CDAL<31:00>

H

H

H

L

CDAL

H

H

L

H

CDAL < 15:08 >

H

L

H

H

CDAL:'::::l:H6>

L

H

H

H

CDAL< 31:24 >

H

H

H

H

read but no write

"'All other binary combinations that specify the validity of two or three bytes on CDAL < 31:00 >

are allowed.

'

Confidential and Proprietary

2-5

Preliminary.
When AS is asserted, the CMCTL evaluates the BM<3:0> information for a memory write
operation. If the operation isa multiple transfer and the first transfer coinpletessuccessfully, then
following each assertion of DS, the B'M <3:0> information is evaluated ob. each data transfer to
determine unmasked and masked memory write operations. If the BM< 3:0 > lines are all
asserted, an unmasked memory write is performed by the CMCTL. Otherwise, a masked memory
write is performed. The CMCTL ignores the BM<3:0> information during memory read and
CSR read or write operations. A masked memory write occurs on a byte or word operation.
Corrected read data (CRD)-This output is asserted during memory read operations and masked
memory write operations to indicate that the CMCTL data h;8 been qmected. During memory
read operations, if the CDAL<31:00> contains corrected data from the CMCTL, both the CRD
and RDY inputs are asserted. During masked memory write operations, a memory read is
performed to detect and correct single-bit errors before the masked write to memory occurs. If a
correctable error occurs during a memory read portion and no parity. errors were detected on
CDAL < 31:00 > , the CMCTL asserts both the CRD and RDY outputs.
Control status/data parity (CS/DP < 3:0 > )-These bidirectional, time-multiplexed lines transfer
control, status, and parity information. In the first part of an I/O cycle the CS/DP3 input is asserted
by a DMA device to request a synchronous operation. This input has an internal pullup resistor to
accommodate asynchronous DMA devices that do not drive the CS/DP3line.
The CS/OP < 2:0 > inputs and the WR signalprovide control inform"ltion about the current bus
cycle when the AS input is asserted as defined in Table 4.

Thble 4 • CVAX 78588 Bus Cycle Selection
WR

Bus cycle

CMCTL Function'"

L

request D-stream read

read

L

H

reserved

NOP (no operation)

L

H

L

externallPR read

NOP (no operation)

H

L

H

H

interrupt acknowledge

NOP (no operation)

H

H

L

L

request I-stream read

read

H

L

H

H

demand D-stream read (lock)

read memory (lock) or
read CSR (no lock)

H

H

H

L

demand D-stream read
(modify intent)

read

H

H

H

H

demand D-stream read
(no lock or modify intent)

read

L

L

L

L

reserved

NOP (no operation)

L

L

L

H

reserved

NOP (no operation)

L

L

H

L

external IPR write

NOP (no operation)

L

L

H

H

reserved for DMA device use

NOP (no operation)

CS/DP line
2
1

0

H

L

L

H

L

H

2-6

Confidential and Proprietary

Preliminary
CS/DPline·
1

2
L

H

L

L

L

L

H

H

H

H

CVAX78j88

Bus cycle

CMCTL Function'"

L

reserved

NOP (no operation)

H

write unlock .

write memory (unlock) or
write CSR (no unlock)

o

NOP (no operation)

H

write nO'unlOck

write

*The read and write operations are executed only if the address .on CDAL <: ;31:00> is within the
programmeci range of the CMC;TL. If ,the a4drei\s is not in ~.he. range,a.nq operation (NOP) occurs.
During the second part of an I/O cycle', the cslOp <:3:0>\:,urputs provide byte parity for data on
CDAL <31:00 > duting amemoryorCSR :ti:adjwtite. Even parity is checked or generated for even
bytes and odd parity is checked or generated for odd bytes.
During a write operation, theCS/DP<·$;O> providcll.input information; lithe DPE input is
asserted,.trre CMCTLtests theCDAL< 31:00> .£or paiHYerrors .. TheCS/DP<3:0> iniorrrmtion
must have valid parity for all bytes on CDAL<3Hl(1)regal'dless of the BM<3C:O> inputS:. If
parity errors are detected duril1g a mel11,ory write op¢l'ation, the data andincofrectcheck bitsa,re
.
written to Il1e~orY.,A CSR writeopetatil;m wjth~~rityerror&jsabqrted.
Duril1g a read operation, the CS/DP<;J:O> QutP\:l1iS contain parity information generated by I;he
CMCTL for all bytes regardless of thethe.BM,<:J:O> iqputs.J.he parity assignwents,are listed in
Table5.
.

Table 5 • CVAX 78588 Read Optration'Parity Assignments
j

Paritybii

~

1

Byte
,

CS/DP3

CDAL <3:;:24.:;>

CS/DP2

'CDAL<:2J:16>

,(

CDAL <15;08 >

CS/DPO

CDAL<:07:00:>

DMA Grant (DMG)- This input is assert~d by external Iogk to signify a DMA operation. It is
. .
deasserted to specify an operationt!-tlit was initiated by the tVAX CPU.

Oata Parity Enable (DPE )-Thls l;,idirectiqpal, sigpal is used to contrql the checking or generation
of data parity when the OS input is <'lsserted: Duting a memql'}':read operation, th'( CMCTJ;., asserts
DPE if the CSjDP<3:0> lines contain valid'parity information: Outing a write cycle, the:QPE
input enables parity chedcingon the incomil1g data., Ifnot  information. This is an open-drain output and must be
connected to Von through an external resistor to maintain high level when the outputs are a high
impedance.
.
DataSp.-obe(DS)-Thisinput pr()vides timing information tor data transfers. During a memory or
CSR read operation, it is asserted by the CVAX CPU or external logic to allow the CMC';rLto
transfer data to the CVAX bus. When an asynchronous operation is specified by the CS/DP <: 3:0 >
information, the CMCTL stalls a read operation until the DS input is asserted. When external logic
Confidential and Proprietary

2-7

Preliminat'y •.
receives and latches the data, it deasserts DS. When deassetted at theehd cif ~ CMCTLoperatiQn,
it causes the CS/DP<3:0>, CDAL<31:00> , and i5i5E lines to become a fiighinipedanceand
deasserts the ERR and RDY signals.
Error (ERR)...... This signal is used by the external logic and the CMCTL to indicate an error
condition and is asserted during memory read operations until the CMCTL,transfers data to the
cvAX bus. If it is asserted by external logic during memory read operations, the CMCTL
terminates the operation and does not transfer data. The CMCTL asserts ERR to indicate that a
CDAL< 31:00 > parity error has occurred during a DMA write operation or that an uncorrectable
error has been detected during a memory read or on the read portion of a masked memory write
operation .. Memory parity errors are considered uncorrectable. During a retry on a read lock
request,the RDY signal is asserted.
The i l l signal is asserted by the CMCTL when a read-lock request occurs and the lock-bit test
results in a hit. Both the ERR and RDY signals are asserted for dne sampling window to indicate a
retry,. For asynchronous DMA read operations, the ERR input is asserted first and the RDY input is
asserted after phase.
When a single-transfer unmasked write operation (durnp and run) is initiated by the CVAX CPU in
which a parity error is detected, the ERR signal is not asserted by the CMCTL. Refer to the
MEMERR signal description for additional information.
When the· DSinput is deasserted, the E'RR signal is also deasserted. When the AS· input is
deasserted, ERR is a highiinpedance. This output requires an external pullup resistor connected
Voo to maintain high level when the outputs are a high impedance.
Memory Address (MA<9:0> )-These time-multiplexed lines provide row address, column
address, or memory refresh address to the memory array.
Master Clock A (MCLKA)-A dock input that provides the timebase for the CMCTL. It is phaseshifted by 180 degrees from the MCLKB inpllct.
Master Clock B (MCLKB)-A dock input that provides the timebase for the CMCTL. It is phaseshifted by 180 degrees from the MCLKA input.
Memory Data (MD < 38:00 > )-Bidirectional lines that provide memory data between the
CMCTL and one of four external memory arrays. When theCMCTL is in ECC mode; the
MD < 38:32 > lines contain the seven ECC check bits. In parity mode, the MD32 line contains odd
parity, the MD < 38:33 > lines are ignored during memory read operations, and the MD < 38:33 >
lines contain zeros during memory write operations. If an error detection mode is not enabled
(controlled by the CSR in the memory), then the MD<38:32> information is ignored during
memory read operations. The MD < 38:32 > lines contain zeros during memory write operations.
When the RAS<3:0> outputs are valid, each MD30, MD20, MDI0, and MDOO line contains a
valid command for the external logic on the memory array. The MD lines indicate the logic value of
thefast' diagnostic test bit 9 of control and status register(CSR17). If each of these MD lines is a
iero, subsequent memory read and write operations occur normally. If each line is a 1) subsequent
memory read and write operations occur in fast diagnostic test mode, all RAS < 3:0 > strobes are
asserted and deasserted simultaneously, and all CAS strobes are simultarieouslyasserted
and deasseited.
During a signature read operation, the MD < 04:00 > lines are asserted when not controlled by a
memory array. When the SE output is asserted with the assertion of one of the CAS < 3;0 > lines,
signatur~information is transferred on the MD < 04:00> lines by each memory array as defined in
Table 6.

2-8

Confidential and Proprietary

-.

'-'-,';

CVAX78588
Table 6 ~ GVAX 78588 MemoryDataSitln~tur,e ~ation

MD
04

H
H
L
L

Memoryc:heek bits
03
:z:ero

L

one

H
L

reserved·

MD

se\fen

Memory banks·

01

00

H
L
L

H
L
H
L

none
one
two

four

Meln;ory Error (~E;ME;1,{Jl)..,..;.:TlFsQutp!1t,int~rl'UPt:ssingl,eTt;~Qsfer. unmask~mem~miJ;e
operations initiated by the CVAX CPU in which a parity error has been detected on the incoming
data. In~his op~rating ~ode, .~h~..:~{[~Xjnput .i~a~~rt:e~tgefqt:e.tl;le. iP,Pilt di;lta. p~ritY:'tc;hec~~,
This. output proyides a ~eans io report late errors~It i~·aP9pe~-itr,ah~. qutput andmtist cQutle,cted
to VnD through an exter:~alresistor,:
... . . •
...
.•.
:
Nonlocal Memory Reference (NLMR)-This output is asserted by the CMGTL to indi~tothe
external logic that the memory or CSRa~ssftomthe ~J:)AI.< 31:00> is not a CMCTL aci )--Th~CMC'rL aSserts ot1~()f the th~se liues during a memory
read or write operation if the address on the CDAL < 31:00 > is within the programmed rapg~of
the CMCTL and if a refresh request is not pending. At a low-to-hjgh transition, the RAs<3~>
informat~on i1}dkates that tile MA <;9 ;0> lines ,*9!ll~ain !lY!lli4~W~~S!iand .tl;te. M.PJOj' MD20,
MD 10,a!}d MDOO lin~s hav~. a ,vqlidcl)omm@d.£§:jf lQgj~QQ t:hfimemot'Y~y;!l'heRA~~ 3~o.):>
lines are asserted simultanCQlJsly dqt;i.pg a,J:n¢fl\AliY ~f~hQrta~t.tl~s~ ~stIDodeop,eratiQn.
C()lqllln .Ad4ress8t;n.>~ [.(C~<;;~:O ;:!,):"'"""Ih,<::$.eQutPUU!.~.;~s~~(d) b>y; .th~h:1CMC\f:L diwiAg
memoty.read or write ope1i!l.tionS;tQipdicat, tlla,tavalld;cQ~ym.naddl):$.& is~>n ~s
if the CDAL'S> 1:00> li~s'lont:~ina:valid C.MCrI,.i!l4d~ss.~aret~h f¢q1J~stis nQt;.~ding;
During.a sigpatuJie read.operatiqnj' one,.o~theCAS<.J~O > lk~es. i$. asserted,! d~~.hdingon:whid1
signature read reque~ bitlis liet in theCSRregj£~fthaHs a~1llfl.~.DutlflS.a;re~~h Of)l;:tation, Jhe
CAS < 3:0> lines are deasserted.

Ready (RDY)- This signal indicates when bus operations can occur. As an input, it prevents the
CMCTL from completing a read operation. As an output, it indicates that a read operation with
valid parity has been completed or that parity has been checked.
During memory read operations, RDY is an input until the CMCTL transfers data to the CVAX bus.
When asserted by the external logic, the CMCTL terminates the read operation and does not
transfer data to the CVAX bus. The RDY signal is asserted by the CMCTL to indicate that the CSt
DP3:0> lines, CDAL < 31:00 > , and DPE line contain valid data. During single-transfer unmasked
memory write operations initiated by the CVAX CPU, the RI5Y signal is asserted when the CMCTL
has latched the data from CDAL < 31:00 >. For all other write operations, the CMCTL asserts the
RDY signal after the CDAL< 31:00> data is latched and valid parity has been detected.

2-9

The RDY signal may beassettedd~ting the $ampling\llhidow, except for ~ Fetty of asynchronous
transfers when it is: as~erted on I?h~se npl)Qt a clock cycle. It is &a~sertedwhen the DS input is
deasserted and becomes a high impedance when the AS input is deasserted.The RDY input must
be connected to Von through a resistor.
Reset(RESET)-When this input is asserted, the CAS <3:0>, CRD, NLMR, RAS <3:0>, SE,
and WE lines are deasserted. The CSjDP<3:0>, CDAL<3l:00>, DPE, ERR, MEMERR, and
RDY lines are set to a high impedance. The MA < 9:0 > and MD < 38:00 > 'lines, the control and
status registers, the refresh countel~ and the refresh request counter are cleared. The lock bit is set
to the unlocked condition. When RESET is deasserted, the CMCTL is synchronized with the first
low-to-high transition of the MCLKAinputat the start of phase (Pl) and the refresh timeout
counter begins counting.
'"
Signature Enable (SE)-This output is asserted with the CAS < 3:0 > outputs to request signature
information and to indicate that the MD < 04:()Q > lines contain input information. When the SE
output is asserted, the RAS < 3:0> and WE outputs are deasserted. The SE output and
RAS < 3:0> outputs are asserted when the CMCTL is performing a memory-refresh operation.
Three-state Outputs (TRI OUT)-When asserted, this input causes all outputs to become high
impedance.
'

Write (WR)-Thisinflutisasserted to specify a write bus cycleandisdeasserthl to specifyardd
bus cycle.
'
Write Enable (WE)~This output isassel'ted to enable a memory read or write ciperations. If WE
and ('AS < 3:0> are a'ssetted duririg memory write cycles, the MD <38:00 > information is valid.
If de asserted when the CAS<3:0> lines are asserted, the MD<38:00> contains input
information.
Voltage (VDn ) -This is the 5~volt in6ut from the powerSupply.
Ground (Vss)-This is the signal andpoo/~rground reference .

• Registers"
The CMCTLcornains 18 conttol and status tegisters(CSRO throngh (,SRI7). CSRO through CSR15
are configuration registers, CSR16is a system error status register, and CSR17 is a'Mode Conttol
and Diagnostic Status Register. Each registers must be longwdrd accessed.

Coo figuration Registers ('CSRO""CSR15) ....,-A, configuration 'register isassigrled to each of the 16
banks Qf'inernory that can beconnccted to theCMCTL. CSRO through CSR3 correspond to' the
four banks onarray·O, CSR4 through CSRr'to the four banks 011 array 1, CSR8 through CSRll
conespondto the£bur banks on array 2, and CSR12 througl'iCSRl5 to the fO'urpossible hanks on
artayJ;Figure 3shows·theteadformat and Figure 4 shows the write format of these registers.
Table 7 describes the function of the register information.

2-10

ConfideJ",Itial and Proprietary

-

p~

...

3130292827262524232221201918171615141312 11 1009080706050403020100

ERfilORMODE

RAMSllE
·BANKU$AGE

Figure 3· CVAX 78588 Configuration Registers (CSRChlC5R15) Read Format

WRITE FORMAT:
3130292B2726252423222120Jjl.HU7161514 ,l3121U009080JOO0504030201 00

BASE ADDRESS VALID

Figure 4~CVAX 78588 to~figuration 'Registers (CSRO~CSRb) Write Format
,.if"'.'

Some of these registers contain information used at th~aJ;~y:l~el,1'he fields !of the foUl' registers
related to an array will contain the same information. For example, a signature read request issued
by the processor can be performed through anyone of the four registers related to an array. All of
the related registers receive the signature information. The CSRO tarQugh CSR15 are cleared when
the RESET signal is asserted.

Bit

Description

31

Base address valid-Set when the base address is written to enable the addressing of the
bank indicating that the base address CSR<~8:20;::',i~. valid. This bit is cleared during
powerup and may be used by diagnostics to disliblearoemory bame.
..

. .

...

.

.

....

....

'

.....

30':29 . Notused~Read as zeros and a write has 00 effect,',
28:20

MemotyBaseAddress...... Specifies. thebaseaddressofrhe related m~l!10ry b~k, If the
bank contains 256 KB RAMs, all nine bits are used in the address (:ompare. If the RAM
size is.1 MB, only bits 28:22 are used. All nine bits
read and written. Refer to the
Addressing section for the use of the base address.
.

are

..>

19:07

Not usecl----,Read as zeros

06

Lo(:k bit-InQicates the status of the lock bit for all 16 banks of RAM.ll11sblt IS cleared
during powerup and unlocks the CMCTL. When set, the CMCTL is prevented from
performing a read-lockrequest.N1em:ory ~ad6peratibris withdut theiock qualifier are
not affected by the status of this bit and the installation of this function is optionaL
Confidential aoo·Proprietary

2·11

Preliminilfy \

05

Signatun:' reakItiq~~~t:-Caus~~ the'J:;MCrf1:o\'read the. memory array signature
informat'on. When set, the CMCTL reads the related memoryarray.ancL!oads bits 04:00
with the information. All four registers associated with the array receive thdnformation.
The signature may then be read by the processor to initialize the base addresses of all
banks. This bit is cleared by theCMCTL on completion of the signature read operation.

04:03

Error mode---'Indicates the errol' detection/correction mode that is usedon a given array.
The encoding .is
Bit
04

Mooe
03

o
o

no detection/correction

1
1
02

RAM size-Indicates the size of the RAM used on the array.

0=256 Kb (1 MB bank) and 1= 1 Mb (4 MB bank).
01:00

Bank used-In,picates the number of banks used,on an, array as follows

Bit
01

Banks
00

00

aiTaY not present
one

o
1
1

System Error Status Register
The CMCTL stores error data in the system error status register (CSR16). The error status flags (bits
30:29) are cleared by writing a 1 to the bit. Once these bits are cleared, the state of the error status
flags will not, !=hange.Thisr(;;gister is cleared when tJ-re RESET inpl,ltis asserted. The read format of
this register is shown in Figure 5, and Figure 6 shows the write format. Table 8 describes the
function of the register information.

READ FORMAT:
3130292827262524232221 201918171615141312 111009080706050403020100

RDS ERROR LOG REQUEST
IMOf1E:TI-lAN 181T (RcRORI
RD$ HIGHERRORI'l'ATE

DMA ERHOR LOG
BUS ERROR LOG
~.C;CEI3RORSYNOROME

2-12

6:0·

Confidential and PropHetary

Preliminary·
WRITE FORMAT:
31302928272625242322'2120191811 16 151413 ;21l100~08(11060504030201 00

RDS Ell ROlHOGR.EQ\Jj;$T (W.FU1iE J. TO:CkaAR)
RDS HIGH ERROR RATE (WRITE 1 TO CLEAR)

CilDERROR LOG REQUEST (WRITE 1 TO CLEAR)
OMA ERROR LOG (WRITE 1 TO CLEAR)
BUS ERROR LOG (WRITE 1 TO CLEAR I

Bit

Descriptioa

31

RDS error 10g-This bit is set when~~~~orrectable Bec or parity error occurs during a
memory read or m~edwrite operation. It is clearedby.writing a ItO this bit.

30

RDS high error log-This bit i5set when an uncorreetahleECCnrparity error occurs
while the RDSerror log bit (bit 31) is set. It is cIearedbyWnting.al to this bit.

29

CRD errorlog-This bit is setwhen a correctable {sirigle bit) error occurs during a
memoryre.ad9r
maskepwrite
()l'l!t1I~ion. ~~ iscle~by,writ,ing a 1to ~s bit.
'," " '
, , ' '.'" ' i"'" '-", " '
, \' : ,,-' :

28:09

Page address of error-Identifies the page (511.byte block) where an error occurred
during a memory operation. The logging of the error address is prioritized. If an address
has already been logged by an error of equal or higher priority, the address. is not
overwritten. Tpeel:1"()r <:onditiopstha~ maycaQSetheJ~gjng,ofthe error address may
occur during either::f ;CVAX CP~Jir.litil1tt'!drnmsf~l'·c}\'· a D~·opetation. The error
condition priority is
.....
.

'j"

-,

:! ' / ,

"

",' ','-

- -','

'"

:

,.'

,

'.

'

,

"

-,

~

1. A bus patity~rror occursdurfu~ a writ~' operation and is logged by the Bus Error Log
bit 07 of the system error status register.
2. An uncorrectable error occursdm:inga melJlQry~ad ~m~kedwrite operation and is
logged by the RDS Error lpg.Requestbit.31 In parity.ihode,paritjlerrors are considered
uncorrectable.

3. A correctable error OCcurs dutinga metnoiyreador masked write operation and is
logged by the eRD error log bit 29.
08

DMA error log-Set when an error has occurred during a D~i:)peradon and cleared by
' .... ,.
writing a 1 tb this bit.

07

Bus error Iog~Set when a bus parity error has been &tected during a write operation and
cleared by writing a 1 to this bit.

06:00

Er~r syndrome-If a memory eITClf is detected inECC mode, this field stores the error
syndrome which is loaded with the error address field when a memory error is detected.
When parity mode is enabled and a memory error is detected, this read-only field will be
read as zeros.

ConfidentiaLand Proprietary

2·13

Preliminary
Mode Control and Diagnostic Status Register
The modecontroland diagnostic status register (CSR17) controls the selection of operating modes
and stores diagnOsticstl\f~sjnforniat10h. This~~st~r is deared when RESET input is asserted.
The .read format of this :registeris ~hown in iFigute 7 :and the write format is shown in Figure 8.
Table 9 describes the function of the register bits and Table 10 describes the che.:;k bit field (bits
06:00).
READ FORMAT:
31 30292827262524232221 2019181716151413121110 09080706050403020100

PMI CYCLE SELECT
ENABLE CROINTERRUPT
fOB CE R!OF RESHI\E_Ci_U_ES_T_-,--_-:--_ _ _~
DISABLE ERROR DETECT

DIAGNOSTIC CHECK MODE

IF ECC MODE, THEN
.CHECKBITS-=:6.;.::00--_ _ _ _ _ _ _ _ _ _-,-_ _ _-'-_--i
IF PARITY MODE. THEN
CHECK BITS 06: 1,0 = XXXXXX,O

Figure?· CVAX 78588 Mode Control andDiaglJostiCS~tus Register Read Format

313029282f262524232221201918171615141312 11100908070605040302bl 00

PMI CYCLE SELECT
ENABLE CRt} INTERRUPT
FOHCE

R~F,RESH

REQUEST

DISABLE ERROR DETECT
FAST DIAGNOSTIC TEST

DIAGNOSTIC CHECK MODE

IF PARITY MODE, THEN
CHECK BITS XXXXXX.O

FigureS- CVAX 78588 Mode Control and Diagnostic Status Register Write Format

2-14

Confidential and Proprietary

Table 9· CVAX 78588 Mode Control and Diagnostic Status Regiskl'DesetiptiOn
Bit

Description

31:14

Not used and read as zeros

13

PMI cycle s~lect~Settose1ect. the pri"ate11l~ory inte!xp~Si (PMI)i~as an integral
multiple of CVAX bus o/cle~:. 'If1~sg~tJHt!~iflfains a fi0t;d;P¥I cycle q~li tb,e time that
the speed ofCVAXbus;cyc;:19in,c:Il.7~~f~.1(}O to 8qn~p,~FOnds. IF~s the use of
RAMs with faste!: a<:c~~s tirpe.:~en *~;:I;li.ti~ deareQ.,ltIfYQe is addedt()c@:!:h memory
read transfel; and'the RDY OutP~t i~ slipped ~n:e CY~Ie"W~en.set.acydeisreWoved from
each memory read transfer. Refe.r to the Op~(ltian}';~~cf.i6fi (ott ~dffirigH~tfuformation.
The relationship of tbe!b'li~~igs'~11d~fi::J~~¥ilne i s ' > ' :
" ,

CVAX bus
cycle

)'.

RAM,at:;~s time

PMI bus

. ",

~i

100 ns
100 ns

4/2
~/3

~m$

12

{-;"

~m

Enable C~]):-:-\Vh~n seh t~eCOl:~t¥1ble(si~gle-"WJS::~D .¢rror~~~?,r~2t!!d~fh'e~Cc
logic. ''!'he eRD rn~rt'\lptsi$#~I. i~~ ,a.sSe~tt#.tq :&poi~tn,~' errol: Th1spitd~~ il,q! .~g~t
. tn,epage add~ss !?its 28;O~,':t~eCRti,~r loi §it,'t~;'o(~S~161' Ot; tl1~I~9~ahd
reportingofunc()treciable ~purs.'I'his bit
when.no errorOccurs?r an
. uncorredableerrOro~!1I'~' '
" ..
.,,!,

is;9e,aroo

i!

-/:.','§

"1"

,1;,

Forcerefresh~l:his bit cauSes a memotlyrefresn opetati<:lri to be· perfot'irted:imrnediately
following: the' CSRwrite ,ttal'lSaction·thabsetsthis hiit;~Whenil~, the1dreshconttol

. logic operatesiin:ooormal mode, Settingtms:bit·al1owSthespeed'.of;th¢refres1i.IQgicl:1Ybe
'increased'duringC:MeTLmanU£~~~'test; Thisbitill'Wititedniyandisreaq'as\2'kl'o:ilt

is cleared by the CMCTL atf.erthe.fOf£OOrefreshisCt:)IDpieted.:
10

tt-

". 'Oisable memor}r'ertordete
Wherlsef,'tlteeITqr detectlbh (ECC ~hdpi5it~niode} and
mrrection' TE'C€: mod~Ot11y)is';disi\bJed:Tnem{,r logging in' CSR16: i~disam~4~nd
melllory.errorref'O.rri@ isIt#b~iedoritfulERR'O're~poot~dis.Whencreaiid';~he'~trOr
detectibn:ahdcortection areena:bfed.:'
'._

09

._"

07

t.!F', ,; .'

0>

.<"

,.

_, __ ,_

".

c~,

' ,.

".

,,_t,", __

""

,
_

, ..r .. ,',.,.,

.
""_""

,(;~--'~

Fast ..q.iaStl()stic: test....,.. ~nsetat1ldb,irs 29;it? 01 the,~dr<:;~ >~ .. cleare, and CAS or MD~2'IFhesdw:iI'lg'amemory read
o~ration in .Bc:e or pai:hy.moHe. Only uJilhasked jllem6ty write bperations can be used
. .
.... ,
in this iriode;'

.~:OOCheck bits....,.l'his,f~eldc~insthe check bit(s) resulting,from or used with the error
.' detection and .correction oper~tio:ns, 'the relationsh,ip of this inforru~tion depenason the
modes selected and the typeo! ppeffltions as listed.
Confidential· and, Proprietary

Bit

(\ ~scription
Diagnostic check mode
ECC
Parity
mode
mode
enabled'
disabled
. disabled
enabled
disabled
disabled
disabled
disabled

Write operation

bits 06:00 transfer to MD<28:32>
bit 00 transfers to MD32
000000 transfers to MD < 38:33 >
OoOoobO transfers to MD <38: 32 >

NontJiagnostic check mode
"M¢~ory read operation
Parity
mode
mode
enabled
.disabled
MD < 28:32 > tran~£er to bits 06:00
disabled
enabled
MD32 transfers tobitOO
disabled
disabled
000000 transfers to bits 06:01
disabled
disabled
0000000 transfers to bits 06:00

Eee

Error Ch~king
The CMCTL candperate without error checking, in error checking and correction (ECC) mode, or
in parity mode. In ECC mode, the CMCfL flags and corrects single-bit errors and flags double-bit
errors: Single-bit errors . are' corrected on CDAL < 31:00> but not corrected in memory, Error
correction in memory is an optional software function. In parity mode; the CMCTL performs as in
Eee mode except that memory parity errors are considered uncorrectable. If an uncorrectable
error is detected during a transfer, the assertion of ERR·· sigrial terminates the memory read
operation; As ah example, Han uncorrectable erroris detected in the firstlongword read from
memory during an octaword transfer, the transfer is terminated by asserting ERR. The remaining
three longwords are not read from memory. In either ECC or parity mode, a correctable error is
reported as an interrupt by the assertion of the CRD and RDY signals.

-Eee -mode data-During memory write operations, the MD31:0Q > contains the same.informationas
CDAL"::: 31:00 > together with seven check bits generated f~9m an gcc gen~rator. During memory
re~d operatioos, error chec~ng and correctionisgenerateP, from the ¥D3~:OO > inputs and compared
to the MD < 38:32 > check bits. The ECC mode uses a .32-bit modifiedHamming code to encode a

32-bit data longword with seven check bits. When an error i~ detected, the syndrome is loaded into
bits 06:00 of the system error status register. The BCC logic detects and corrects single"bit errors in
the MD < 31:00> data HeId.Single"bit errors in the check bit field are detected and reported.
Double-bit errors are detected but riot corrected and arerepo'rted by asserting the ERR signal.

The modified Hamming code, shown in Table 10, generates seven check bits that are stored in
memory. For a memory write operation, bits MD < 31:00 > that are exclusively QR(XOR) gatedare
indicated by. all Xioea<;:h row. From this value, parity thatis eVen is gel1etatedon C1, C2, arid CT
and odd parity is generated onC4, C8,C16, and C32.·
- ,
During a memory read operation, the data bitsind;.cated with an ,X in each row are XOR gated
again and c\-1I:;ck bits are again generated. These check bits are XOR gated wit~the check bits stored
inmemofY' If the 7-bitre~ult is zero, no errpp were generated. Ifthe result is notze.tO, one or more
errors in the data has been detected or an error in a check bit has been detect~d. TheECC error
syndrome is the result of an error and is stored in CSR16 bits 06:00. If the syndrome matches any
column of bits that contain an X inMD < 32:38 > ,the errer is correctable and the column number
corresponds to thebinhat is cotrected. Fot example, ifthememorycheckhits ate 0111100 and an
error is indicated in MDOO, the check bits generated 6n a' memory Wl'itewouidbe 1100100.
2-16

Confidential and Proprietary

PreJimmary
~fore.theOllUOO vruueisXORgated with 1100100 to equallO:tlOOO. Thisresulrcorresponds
to~yndrome bitsSr, S3.2, S16, S08"S04,S02,andSm and can be readundercoJumnMOOOby
rttading th(! pits that contain an Xas a oneancl the bits without an X as zero . Any sYrldrome ~ue
that ~s cnot, match the v~ueinThble 10 it}dicates an, uncor:rectahle erJ:Qr, '1abl~ 11 listss~mple

syndromes that can be read from bits 06:00.

.

Mq~,11:00> •

,,-Ml> <;;: }8:}~ >eTC-

'Genera~ Chei:klJits

, 'C'tcliC16c8C4C2Cl
Syn.
Bits 3130292827262524232221201918 17 16 15 14 B 12 11 1!.IIJ.!i,(l807 ~"O',0403 02,9~,qo J8n}6.Jp4!~~2
51

S2
S4
S8
516
532
534

XXXX
XXXX

XXXX"
'XXXX
X·
XX
XXXXXXXX
XXXXXXXXXXXXXXXX
X X X X X X X X X X X X X X X x
,:WXX'XX X)( x
X X X X X X X X X X X X X X X X
X X X,X X
X
X
X X
X X
X
X
X' X
X
X

x

xx

x

XXXX
XXX X

x

xx

x

€SR·im
06:00

et'f'()U

1011000'

MDOO

1111001

MD31

0000001

MD32

1000000

MD38

0000011

uncorrectable

XXXX
XXX X

x

xx

x,

x

x

x

x

X
X
X

During a memory write operation wh~~ ~J,da~Pltrity~~risdlitocted'on!CDAL<31:00>,
incorrect check bits are generated and transferred to the MD < 38:32 > outputsf'!f df:tection on a
subsequent memory read operation. The algorithm that generates the incOttect~~~k Bits
complements the generated check bits for the MD < 34:32 > outputs and trans(efs the 'generated
check bits unchanged to MD < 38:35 > outputs.
>

'

Patitymode tIata 'D~l'lga' lllemoty rt!aa' olieti{ti61J1~heCMCTIr ~~~~tesoddb;ki:t)'rf~m the
MD <: 51: 00> ihputs andcorii~a*stht7gene~te,d value to~>2. If thep\lfity hit c;ompariSQriacies
not match, an error isdetected.'1:furlhga ni~fuofy writ~oliel'~t;t(jn, Odd' pantt is written to memory

by tne MD32;'th~k bit.Whenadafa'~ity efti<}riS' de~dri ~DAV<31::00>,tfje:foree
incorreCt check bit logiecomplemiilntsthe~teti'odd'~ritiybeforeil'is,tta:Mferred' ttl the'MD52
output.

Adlh:essin$ ~ch~me; ,',

"', '
", ," ", ',' ,;,
"
" n,
•
The C¥CTL cal1.coPt~l up to 16h~s,~f 2S6!{p or ,~ M,h,MM.E 3cCllJocation(;an ~onllist of 52
bii:s~fdata anaO, '1, or 7 bits of er!9rdetecti9n 9rcorrecti~njrlfprmation.E~chbank has a,j,2,bit
base'address th~t resides in tlle~MCTL.Sevenor9 bitso£thb~ddressaresigIli£icant. Ifth¢RAM
size is 256 Kb (bit 02 of' CSRO through CSR15 is z~ro), the base adC1ress' is map~ to
CDAL < 28 :20>. If the RAM size is 1 Mb (bit 2 is 1) the base address is mapped to
CDAL < 28: 22> . Refer to the Register section for reading and writing the base addresses. When a
GonfidentmIilrid Proprietary

2-17

,.base addressmatmes the address onCBAV<;Jl:00 » thebahk:telatet:irto :thataddress isattWltted.
foteither a read or' writeoIJeration. The C£)A1:29 iii lilWay.szeroindkatmg a memory addrtls1§~pate.
'RAMacccSs is l~roVided\by 'theMA <·9~O, ,RASc<:3:0>, aod 'tAS<3:ti > outputs.' The
'RA:S< 3:0 >: and CAS <: 3:0> enable obe of the banks: The MA <'9=Q > outputs (MA9is not used
for 256 Kb RAMs) provide the memory address within a'bankas deseribed.

",

MA <: 9:0 > addresse$-r-:'Fh~ $Qprce of d:heMA,"': ?:Q ;>optpudmorrpll/:ion d(tpend on the type of
memory operati~n. TheMA<9:0'> output contains a row address during the low-to-high
t!;itpsitionOf t~e RAS < 3:0> output and a coluum address during a low-to-high transition of the
(;AS<3:0> ~:>Utputs.
Duringa single transfetmemory

operations

Row

CDAL20 transfers to MA9
CDAL<19:11 >. transfers MA < 8:0 >

Column

CDAL2Q transfers to MA9
CDAL< 10:02> transfers to MA<8:0>

During multipletransfCr me~ory operations, the MA<9:0>, RAS<3:0>, and CAS<3:0>
output information is in page mode format. The CMCTL compares the address on CDAL < 31:00 >
with the CSR address.p~e .of theRAS <: 3:0 > lin~sis t~(!n: aS$¢rte,q followed by the assertion of
one of the. CAS <: 3:9:> liri~s.After comp1etingthe first operation~ theRAS < 3:0> line is held
asserted while the CAS < 3:0 > line is continually negated andreass~rted for the remain~ oftbe
operation. Because the RAS < 3:0> line is not negated and re~~serted, the time required. to
perform the operation is minimized. MA9is not used when 256 Kb RAMs are present. The address
information on MA < 9:0 > is
Row

CDAL2I transfers to MA9
CDA < 19:11 > transfers to MA < 8:0 >

Column(O)

CDAL20 transfers to MA9
CDAL < 10:02> transfers to MA < 8:0 >

Column(n)*

CDAUO transfers to MA9
CDAL< 10:04:> transfers to MA< 8:2:> ".
LW CTR 1:0rrans£ers to MA < 1:0 >

~ri";{(quad~ord) :
n=2{he}{word) .
n";' 3 (6chiw~rd)
~p.e l();l:)g\forq wunteX J~W CTEo) is. initialized;-yiti:l; th~~ddJ;e~sj value, 9n .~DAL.<)O,l;.op 0 ~w~e
ftr;;t transfer.. For ,a quadword tran~fer,. lW, CTR,lntO ~,s.then.c9rnplernl!ntecl. ,If thetran§feli 15
h~~ord, pr()~t\lwor~, t~e. c?unter isipc,rernented ,1:f90r t11r~e ykes,resm':ctive1y.
..

Hap internal IllemorY.!:efresh reqlJ~stis pending whil.et~GMCTL i:jin the idkstate, the CMcn
peliform~ oo1Y,a RA,S.mem()ry re£re~". If the ASinpl,l~is asserted, the addrc:$g 9n CDAI., <: .31:00>. is
latched and the requested operation is stalled until the memory refresh completes. All the
RAS < 3:0> outputs 00 the memory bus are asserted and all CAS <: 3:0> outp~t~~redeas~erted.
The source. of the MA~.9:0 > refI:esh, addressisa ,9-bit (0,8:0) refreshcouriter. 'fli~{tpter'is
·~le.ared by theRES~1: 'Hiput ~nd iOCfernentedatter the~£n\~? operation has ~e~c0!llpleted: J'he
·'RESET inputaIso c~:ars th~ l-ef,resh timer thatproviCle.the.refresh request .. TabI~.12 spedfiesthe
num8~t6f c1dck ~cl~s (J\1CIJcA or MCLKB) between each refresh request.
' ... ' '" .
•

2-.18

,

,-, - :

-

-.,;

•

1

-

;

- ~

~',

-

-,,'

'

;

i

~

.ConfideritiaLand Proprietary

,,'

"

. - _"

'\ _: -

' ),

PreIimieary
Table<12-CVAX 78>88 Refresh Request Tuning'
~'

tlOck

Overhead

select·

Qock
periods(ns)

cycles

(percent)

1

55

226

2.7

12.43

1

50

226

2.7

11,3

0

40

228

3.5

9;12

0

50

228

3.5

.,IL4

PMlcycle

,,'tate (~S)2

IBit 13 of the mode control and status register (CSR17)
2Includes 4.0 microseconds for the completion of an asynchronous DMA octaword wdttt,,*pe.ra~Qn

,anq foraslo~i~k)(;l<.cycle,
&AS < 3:0 >md eAS'<)r.(» ~ddtt!sse~ Ifiabaseaddmssof II menloryb~lf4:llia'tches fueifddress
COAL < 28:02;): ,
of ,the RAS< 3't(},'s:d outputsllodonei 6f the'C.AS~ 3:(11)' ioutputs 'is
'asserted. 'fable 13 SUll1tnatiZeS' the })arlit/addressing 6rt ea¢h ~'as It'fundionoftneaS!lmed

on

'one

RAS <3:0:> and CAS'<3:0 >"signafis.

'

.

0'
1

.3

RAS.3and~s6

4

, RASOandCASl

i

RAS land CASI
: 1

6
RAs3 and GASI'

7

rio

~giste.rad~s~J-Ea<:h /l!gis~r {cSRQ'i~~ ,~~Rm h~. a ~i}l;ed add~ssin,Jhe
space of
the evAX CPU. If a register's address ma:t~l:lesibel}d~~~,pq t:,~,,'h ~1~99~ ,.areado~.w:riite
operation to or from one of the registers occurs. The register
Table 14. '

aa&esses irelistea in

'i~ter '. ,Mdress

(hexadecln1al)

Regilltel'i

Address·

(hexad~al)

0

20080100

9

20080124

1

20080104

10

20080128

2

20080108

11

2008012C

.3

2\)0801OC

12

20080130

Con£~ntialandProprietary

2~19

Register
Address
(heXadeciirUll)

4

2Q080110

13

20080134

5

20080114

14

20080138

6

20080118

15

2008013C

7

2008011C

16

20080140

20080120

17

20080144

8

i

Operations '
The CMCTL performs memory read, memory write, CSR read, and CSRwrite operatiOns under the
eVM bus.:lkfore an operation can he. initiat~d, asignatuJ:tZread operati-onds
performed during system ooottime to loa<;ia bank ad~ss into CSRO through CSR15. The
, signature information for each memory array connected to the PM~busis stored in CSRO through
CSR1S. A signature read operation is initiated for each registerl:lywritinga Lto the signature read
request bit in CSRO, CSR4, CSR8, or CSR12. The RDY output is not asserted until the signature
inf6rmationis I(),~ded into the .c~l{. During this.pperati()n~the¥D < 04:00.> outputs' are first
asserted. One ofthe ('.AS < 3:0> outputs is thenasserted together With the SE output to enable
the signature read logic on the selected merrioryitrray. The RAS<3:0> and WEsignakate
deassertedl. The memory array transfers th~ array signatureinformationto the ,MD< 04:00:>
outputs. Refer to the ac Specifications for the signature read operation. The relationship between
the CSRs and CAS < 3:0> is provided in the Addressing section.
co~t~olof thl:!,

The signature information in theCSRs canbe read to determine the number o£banks and the RAM
size on each memory array. The system boot program determines the addressfor each banks.;>!
RAM and can selectively write to a valid bank address in CSRO through CSR15:
"

Memory read-The CMCTL sripports masked or unmasked, single- and muItiple-longword read
operations' (quadword, hexword, and octaword). Before a memory read ope~tion, the RESET
signal must be asserted to initialize CSRO through CSR15.
'
The number of cycles necessary to complete a read transfer is a function of the transfe'r type, the
clock (MCLK) input period, the type of memory error detected, if a parity error was detected in an
external cache, or if a DMA retry occurred.
"
The number o£ cycles requirecl to complete the different types ofsynchroHot:lsmeinoryre~d
, operations if no error is detected ii; shown in Table 15.'
.

TAhJer 15 •. CVAX 18588 Synehmhotls'MefiioryiRE:a .•.
• Addonecyclef()t each asynchtonoustl'an~fifr:
•

, "

_,

•

_. , "

._.,.",',

_•

'.

_,'

'~,'

,_

~,

....
,

,'"

,

.....
_

_' ;

•

.....
' , '

..
"

f

• A read lock with thelockl;>it already set>teql.lire(t,lu:; Satll, compares the address the values stored in CSROtmoughCSR15,
evaluates CDAL< :>1:30> for transfer length, and evaluate.s the C? and DMG inputs.
During a syncmonousoperation, the CMCTL e.valuates theRDY or ERR inputstoderermine. if the
operation should be aborted. This function is inhibited during synchronous operati0l1,' If RDY or
ERR is asserted, the memory read cycle on the PMI bus is completed, but the (MCT!. does not
drive the CVAX bus. If RDY or ERR is not asserted, the (iMCTLreads data from the PMI bus and
checks the data for errors, The CM CTL assel;ts RDYor ERR to indicate the trans£<:ris complete.

as

Multiple transfers-During a multiple transfer read operation,. the04CTL lo~ds an aqdress from
CDAL < 31:00 > and returns two longwords (quadword), three longwords (hexword), or {emr
longwords (hexword). TheCMCIT then loads the address from CDAL<31:00> , compates'the
address to the values stored in (SR() through CSR 15, evaluates CDAL < 31:30> for t~fer length,
'.,
"
.
and evaluates the CS and i5MG inputs. '. . '
During a synchronous operation, the CMCTL evaluates the RDY or ERR inputsto determine if the
operation should be aborted. The abort function is inhibited during asynchronous operation. If
RDY,orERR is aSSerted, the PMlbus read cycle is completed. The CMeTL does notd!:i'liC.tl}e CVAX
bus and the operatl~nis aborted. If RDY 01' ill is notasserted,the CMCTL reads datafrom the
PMI bus, checks the data for e~ro~s, passeqhe data to CDAL < 31;00>, appasserts the RDY or
ill to flag' the termination of the transfer. Theoperation is tet:minated when thelast Iongword is
read from the PMI bus.
.
.'
. " .
.
.
.

. R~ad lock- The CMCTLperforms .the read lock oper;ation$ $itnH~ to .;a,1U<;mory read operation
an91Uorrit9JS the loc~'bit 6 Q£ .q(lnfig).lration~gi~ters (e $l~O;C SR15). If ~ J(Cad l{;Fk is detected. the
. CMCTL requests a retry and'completes the PMI bus read operation on the first transfer. It thep
terminates theopcration on the C~AX bus by asserting both tbe,ERR and RDY~ignals .. '!he
CMC:TLwill no~retryaread lock. If. a read lock is not detected,'rheCMCTL completes the
requested read bperation.
'
.'
..
The CMCTL sets the lock bit if an uncorrectable error does not occu~ on any transfer. An extra cycle
is added to the first transfer to allow sufficient time for external asynchronous logic to terminate
the operation with the RDY or ERR signals.

Cdnfide11tial and P~oprietaty

Preliminary'
Memory write-The CMCTL performs single and multiple word memory write operations
(m~sked Ot; !Jnmas~)on eachtrans£er, The RESET signal must be asserted, prm.!: to tl:u;qperatiQD.
The number of CYcles necessary to complete a write operation is a functkm of the t,.ransf,er~Y,Pe, the
status of PMI cycle.select bit in CSRI7, the 8M < ):0 > inputsj.aUdwhetherthe tranSfer is
synchronous or asynchronous.
Table 17liststhe number of cycles required to complete eachtypeQf synchronol,ls write. Wbenthe
PMI cycl.e~l~ bjtis 1, o~ CVAXhus cydeis 100 nanOSeOOi1d&iiWhen the PM!cyC1(iselect bitisQ,
one CVAX bus cycle is 80 nanoseconds.

type

PM1CYcl~
Sel~i:il .

longword

1

Thinsfer

'CVAX

.jCYcle"

L

TowI

cytle~& .

longword

1.3,),
15

hexword
octaword

Iongword.

hexword
octaWord

longword

hexword
octaword

ISitl3 of the mode c{)fitrolartdstatus.regis~ei'(CSR17)L
'Tbe PMlblts cycle period is an' integralntln'lbe.tof:CVAX huscycles;·· Example:A/2' speCi£tes that
the first l~ngword is read in four eVA'.k bustyde and theremainiri~lbrigWotdsin' two CVAX bus
cycles. When the PMI cycle select is 1, the PMi bus Cycle is 4/2 andoneieyde is'100 ns..Whenthe
PMlcycie select b~t isO,the,PMlbuS cyclds 5/3'~QJ;)ecyrleis80ns.
JOne CVAX:pus cyclc;ott;WOMCLKA or: MCLKadQck cycles.,.

Confidential imd Proprietary

2-23

Preliminary
The follo~ing are exceptions· to the synebronolfl! write: operations:
• When an operation collides with a refresh operation, add£our cyCles if the PMtcyde seleCt bit is a.
land fivecycIes iHt is a O.

• If a data parity error or an uncorrectable memory error occurs during a write operation,. add one
cycle.
• When theBM<3:0> information changes between masked and uhmasked during a write'
transfer, add one cycle.
• Add one cycle for each asynchronous transfer.

Error handling-When DPE is asserted, the CMCTL tests the data parIty on CDAL < 31:00 >. If a
dataparity error is detected durhlg an unmasked or masked transfer with no uncorrectable memory
errors, the CMCTL writes the data and the incorrect check bits onto the PMI bus. The algorithm
for generating incorrect check bits is specified in the Error Checking section.
The CMCTL performs masked write transfers by 'doing a memory read and checking the data for
memory errors. If a correctable memory error is detected, it is corrected before the memory write is
completed. If an uncorrectable error is detected including the data on CDAL< 31:00>, the
CMCTL does not execute the write portion of the masked write. A memory read operation Instead
of the memory write operation does not change the data in memory.
The ERR output is asserted to indicate uncorrectable memory errors and DMA-related data parity
errors. A correctable error is reported as an interrupt by the assertion Df the CRD output. The
MEMERR OUtput is asserted to indicate data parity errors resulting from operations mitiated by the
CVAXCPU.

Single transfers-During a single transfer write operation, the CMCTL loads the address from
CDAL < 31:00 >, compares the address to the values stored in CSRO through CSR15, evaluates
CDAL< 31:30 > for transfer length and monitors the CS and DMG inputs.
If the DMG signal is not asserted, the write cycle is CVAX-initiated and the CMCTL evaluates the
BM < 3:0> inputs to determine if the write transfer is masked or unmasked. An unmasked write is
a dump ahd run operation to allow the CM CTL to keep up wi th an external write-through cache and
not degrade the single transfer write performance. During a masked write operation, the CMCTL
receives data from CDAL < 31:00 > and asserts the RDY signal. If the DPE signal is asserted, the
data is checked for parity errors. If no error is detected, a PMI bus write is initiated with correct
check bits. If an error is detected, the CMCTL asserts the MEMERR output, a PMI bus write
operation is initiated, and the data is transferred to the PMI bus with incorrect check bits.
During DMA transfers, the DMG signal is asserted. If DPE is asserted, the data is checked for
parity errors. If an error is not detected, the RDYsignal is asserted, the CMCTL transfers the data to
the PMI bus with correct check bits, and the CVAX bus is released. If an error is detected, the data
is transferred to the PMI bus with incorrect check bits and the ERR outputis asserted for two CVAX
bus cycles.

Multiple transfers-Multiple-transfer write operations are performed as a page mode write
operation to the PM! bus. The CMCTL load~ a single address and performs multiple page mode
memory data transfers (including check bits) from the CVAX bus to the PM! bus. Refer to the
Addressing section for a description of the page mode;
During the write operation, the CMCTL receives the address ftomCDAL <31:00 >' and compares
the address to the values stored in CSROthrough CSRl). It evaluatestheCDAL<51:30> for
transfer length, the CS and DMG inputs, and the BM < 3:0 > inputs to determine if the transfer is
2-24

Confidential and Proprietary

Preli~y
m~sked orunmasl outputSat'¢'fiotu~ tovaJi(;i~~d~~'PAL< 11;QQ;:> idatadutiPgthe. tual qR write
operations. The CMCTL begins the write:opet'ation bylollding and f:hetltihift!ieCDAL<13hOQ>
address and by evaluating the Cs and DMG inputs. IfJh,DPE i'pput is asser~d,,!he 411ta,on
CDAL < 31:00> is ch~cked £Or parity error~Jf an error i~ detec:~,the wpl;er.pperatiofiisabort~d
and the ERR output is asserted for two CVAX~b6s C'yoes.Ifan error is nofd'iStected,' the selected
CSR is 10ade,d;MthCPAL<31:00> information and t~r.RQY;outP?-t i~~~c~te~
.

ac

Bus Operating Modes
When a DMA device is bus master of the CVAX bus~t~e. CMCTLC'.tllt~n!>fer .data either
synchronously or asynchronously.Tbe DMAbus operat~n;CXIeis' controlled'bY theCS/DP3Iine.
When the CVAX CPU ishus masreroftheCVAX bus,theCMCR fe's'[>oosets synchronous with the
CVAXCPU.
.
Asynchronous DMA Mode-If CS/DP3 is not asserted during the first part of an I/O cycle initiated
by a DMA device, the CMCTL responds asynchronously to the CVAX bus by monitqf~@"f~'~
DSinputs. Beforethe C~CTL starts the next operatio~,i~ waitsfor theasse~tion ~f t~eASbefo~
evaluating theCVAX bus to detef'IDir1e the nettopetlrtion;Tilc:!ls'input mustlbe~se~t~d ~fd~.
the CMCTL initiates a tTan$£et.Whe:ntheCMCfLacltnowIe~s li.tmnsfei:; it assertsfheRDY6t
ERR output and waits for the de assertion andsubsequent assettiori(}fm'~meohtifltill:lgfOthe
next transfer.
.
.... .
.
~

"

;

During read operations, the DSirtput mllst be asserted befQii;:JheCV~~b.usoutPuts,¥e·el1a9I~.
During write operations, .oS must be deas~~rtedto deterQMe if CDAL.<
vllli<1niita.
before performing the write operation.

31:0:0> ha.s

Synchronous'Mode-All operations initiated by the C\TAXCPU are synchronous. The CMCTL
responds synchronously during DMA transfers if the CS/DP3 signal is as~~~~~ tl1~Jif~tlP~S
oian I/()cycle. I)~ri,ng sync:hrqnQUS 9P~.t;a~i,ws,.th~ ,9$ si~n~~}~!l9~~I1d f4¢.c¥sn.;d9~"qol;·
stalL. Before stari~n~a~ynchron8\1~pperatio~d~f)f¥c:r~.~~ck~~?l:th~:as~er~io~Of.As, .

• Interfacing Requirements
A typical CVAX system interface, using the CVAX 7858SC'.:MCl'L,is.'8howninF.igtlre 9. The
CMCTL can control up to four DRAM arrays on thePMIhus. Itprov:ides anonlocl"ll memoJ."Y.
reference for a DMA interface to initiate transfer from external bus devices. .. . ........ .

Confidential and Proprietary

Prelil'ltiltary.
: MtLKA ,

IviClKA

~EWT'E!

KB
X"Cb
SET

~MA<9:0>
RAS<3:0>

_

=_= =_ =_)=_ =_

-_ __

.CASO

CMCTL

CAS1

_ ,_

.4

CAS2
CAS3

r-~--~~~+---r-r-~~~~~

ClfAX
BUS

BUFFERED
f:,\iAX PIN .BUS

BUFFER

MCLKA
MftKB

A SET

i

,'~~

elK REF
~

SYSREsH

ciklN

EXTERNAL
CACHE

Q-BUS: VAXBI BUS, OR OTHER DMA'SUS

Figwe 9· CVAX 78588 CPU System InterfaceDiagram

. Specifications "
~

mechanical"electrical, ,at:ldenvironmentalcharljl,cteristics andspt;cifications for the CVAX

78588 are, described in the following paragraphs. The test conditions for the electrical values are as
follows un1e~s specified otherwise.,
• Ambient temperature (TA): 70°C

.S~pply
voltage (VoD,):4.'75 V to 5.25 V
,:,;'
),',

'

".

• Ground reference (Vss): 0 V

AbsolUt¢maiimuM raMgs
Stresses : greater than absolut:e fuaximtim ratings" may cause permanent damage' to a device.
Exposure to absoIutemaximum rating conditions for extended periods may affeCt device
reliability.
• Power supply voltage (VDD): -05 V to 7.0 V
• Storagl:: temperatUl'e(Ts):-55"C to 125°C

• Package dissipation: 1.8 W
• Input or output voltage applied: (Vss -O,5 V) to (Voo + 1.5 V = 7_0 V)
2-26

Confidential and Proprietary

-.
• Powet supplY voltage (Vcc):5. 0 V ± 5%
• Supply current C4:c):J36 rrJ:A (maximum),
_.

• Relative humidity: 10% to 95% (nOncondensing)

• Air flow: 100 linear feet/minute

de Eleetric41 Chmetet'istics.
".
., Table 18 c9ntamsthedc electrical pammetexsfottht IDPutfUldoutptit sign.us oftheCMCI.L: Rider,
to Table 1 for the pin numbers of the~signals referenced in'lable 18'/Table 19 lists tfilelttst!sthat.aie·
applicable for the inputs and outputs,.

Symbol

';'Unit"

Parameter
High-level
input-voltage
(TTL)
(MaS)

V1L

2.0

V

70%V~D

V

Low-leveL
input voltage

0.8

(TTL)
(MaS)

V

30%'VOD ./V

LoW-level
output voltage
VOLl (TTL)

0.4

v

VQP (MOS)

0.4

V

Jt;;, =2.0 rnA
". ==24.0 nlA

v

-0.5 rnA

High~leveI

outpatvoItage
(MOS)

Low-level
output voltage
(MaS)

-10
.. current

o <'·V;,.,··<:'5:z5V
current

Vnn =.5.25 V:·

Active supply

TIUOUT==OV
10 =0, r:== 70 e
,_'_._.,

ettrrent

336

"'0
0

VDti =.525 V
,

'~

-,

-" i

ml••B,

~li'>, ~::;>. :\C)

,i,i" ';; \'';I,~;i~,

CVAX\r~S~83.;·

Preli~at)l; •. , .

',,",

Table 19· CVAX78588 de Te!it sulrirDiry

'-;',L~·i;

)1:"--~

Applicable Test
Signal Name

V.H I

v.1.

1

VOLll

v: •
OL

IL

V.il 2

X

CRD
BM3-BMO

X

X

CS/DP2-CS/DPO

X

CDAL31-CDALOO

X

"

X

X

X

X

X

X

X

X

X

X

'X

X

.X

DMG
DPE

X
X
X

X

X

MA9-MAO

X

MEMERR

RAS3-RASO

X

X

.X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

WE

X

X

X

SE

WR

X·

X

X

NLMR

X

X

X

MD38-MDOO

TRIOUT

X

X

MCLKA and MCLKB

RESET

X

X

DS
ERRandRDY

Vo/

X

X

X

Vou'

X

CAS3-CASO
CSjDP3

VlL'

X

X

AS

'.

10

X

ITTLlevel
'MOS level
BC

Electricai· Characteristics

The ac load circuits used in the measurements of the ac parameters are showrt in Figure 10 and
summarized in Table 20, The input and output pin capacitance is listedin T~le/21.The test.
conditions are
.
.
..

·VoD -4.75 V {~ceptasnoted)
2-28

Confidential and Proprietary

Prelimiaary·· i

DUTPIN
o---~----

__a.5mA

~-------oVDD

DUTPIN
0-__
~____~_O._5m_A_·____--oVDO

2.0mA

T

24,OmA

T

CL = 130pF

VSS

CL "'·130 PF

VSS

VSS

VSS

B

A

DUTPIN

0 - -......- - - . . . . , . ........- - - 0

voo

22.0mA

TCl = 130pF
VSS

.

VSS

C

D

'. FigurelO-CWl;X78588ap TestCitr:uitr

Test

VOL 1 and Von'

CRD

CS/DP'::::2i O>

66.64

COAL < .31:00 >NLMR

56

104·71

55

'69

B

52
'·53

i5PE

70

c

MEMERR

54
:32·35

D

CAS<.3:0>
MA<9:0>
MD<3$;OO>

20-29
~·lJ,105-1l5,

'i18-132,3 c 8

RAS<3:0>
SE
WE

38-41
45
44

ITTLleveI
IMOSlevel

Corifidentihl and PtClprietiry

2·29

Preliminary
Table 21- CVAX 78588 Pin Capacitance

Symbol

Requirements (pF)
Min.
"M~
CV~Xb8S inpqts
BM<3:0>, DMG, DS
RESE1~ TRI OUT, WR

10

AS

15

CVAX bus outputs
CRD, MEMERR, NLMR

10

PMI bus outputs

15

CAS <3:0 >, MA, RA..S.:<:J:O > ,
SE,WE
CVAX. Bus.input/output
CDAL<31:00> , DPE,

10

CS/DP<3:0>, MD<38:00>
ERR,RDY

15

Clock input

20

Table 22 lists the signals that can be connected to Voo through an external resistor. Refer to Table 1
for the pin numbers of the signals listed.

Signal

MEMERR

R.!'sistance n
Min.
Max.

Remarks

200

Accommodates asynchronous DMA devices that do not clrive
this pin.
.

620

4k

Used as a passive pull-up for~ternallogic that may. be wire
OReel to this input. Larger value may be used if the passive
pullup timing can be met.

200

Required for external logic.

200

Used as a passive pull-up for external logic that may be wire
ORed to this input. Larger value may be used if the passive
pullup timing can be met.

200

Required for externalJdgic.

ac Synchronous Characteristics
A subset of the CMCTL operations is used to specify the phase timing for the CMCTL signals. The
ae test conditions are

• Supply voltage (Voo): 4.75 V
• Ambient temperature (TAl: 70°C

2-30

Coofi4;mial and P~prjetarY

• Va (MOS) =W?b VQD

I;

• V;H (MOS)""",90% VDn
• V;L (TTL) =0.8 V
• Vm (TTL) =2.0 V

Table 23 lists the input signal timing parameters and Til'ble 24'Ustthe6ui~tlt signal timing
parameters.
,

,

,

Table 2 J ·CVAX 78588 SynchrOnous Iripuf Titiing Parameters, ",',.

Symbol

Definition

tAS

ASserupLk'.'·'
,,,h

t BS
tBH

Requirements (os)
Min.
Max.
i' "

:,,;-" •• ,,,'

,

("

25" '

BM<3:b>
set'
,'u,,' , ,'",,'?P

"""L,',

o

,BM<3:0> hOM

tee

External clock cycle

teo

'MCLKA to MGLKB delay

teH

External clockhigh

teL

External dock low

teR

External clock rise/fall

tess

CS setup

tesH

cShold

t DAS

CDAL address setup

tOAIl

,CDAL address hold

toos

CDAL data setup

tODH

CDAL data hold

t ERS

' ERR and RDY setup

tERH

ERR and RDY hold

tps

{DP and DPE setup

t pM

DP and DPE hold

t pMIS

MD < 38:00 > setup

tpMlH

PMI bus input hold

tas

'Reset input prior to PI setup

tRW

Resetinput width

tss

Strobe setup
Confidentilll and Proprietary
.-

",i

"",

.-

'-,-,"'!

2-31

Preliminary
',.,

Symbol

Defmition

tSH

Strobe hold

0

t SYNS

AS and DS synchronizer setup

10

~YNH

AS and ])S synchronizer hold

10

tws

WR setup

25

tWH

WRhold

0

*To be continued

Table 24 • cvAx 78588 Synchronous Output Timing Parameters
Symbol

Requirements (us)
Min;
Max.

Parameter

<

tASERH

AS to ERR and RDY hold time

o
70*

CRD, MEMERR and NLMR delay

25

CDAL<31:00> delay

20

DS to ERR and RDY delay
tOSODH

25
'25

AS to NLMRde1ay
CAS < 3:0 > low

•

DS to CDAL < 31:00 > high impedance
DS to DP and DPE high impedance

o
o

ERR and RDY delay

25
. 25

25
30

MA<9:0> toCAS<3:0> hold

150*'

MA < 9:0 > to strobe setup

20*

MA<9:0> toRAS<3:0> hold

2.5*

MD<38:00> delay

o

30

MD<38:00> hold

o

25

DP and DPE delay

25

PM! bus delay

'15

RAS<3:0> low,
RESET to CDAL<31:00>, CSDP<310>,
DPE, RDY, ERR, MEMERR, CRD, andNLMR
*Preliminary values subject

2-32

to

change

Confidential and Proprietary

50

Preliminary
Clock Input Timing
Figure Ushqws the MCLKA and MCLKB external dock input timing for synchronous operation of
the CMGTL.The timing parameters are listed in Table· 24.

90'lt:

M'ClM

90%
MCLKfl
10%

Figure 11· CVAX 78588 Clock Input Timing

Initialization
Figure 12 shows the RESET input timing for initializing of the CMCTL for synchronous operation.

--fU=t
I r--t--+4
_

I

RESET

'

I

Jr-+--+---+--+---+---,f---+----i-__
_

I

CVAXBus Reset Timing·
Figure 13 shows the relationship of the RESET signal to the>C'VAXbussignals. When RESET is
asserted, CDAL < 31:00 > , CS/DP < 3:0> , DPE, RDY, ERR and MEMERR outputs are asynchronously set to a high impedance and CRD and NLMR are asynchronously deasserted.

\~-------------------

==============)t--------------.J

CDAL<31.00>

tRSTD

ROY/ERA
MEMUfR _ _ _ _ _ _ _ _ _ _ _ _ _ _- , J T - - - - - - - - - - - - -

Figure 13· CVAX 78588 CVAX Bus Reset Timing
Confidential and Proprietary

2-33

Synchronous DMG and AS Timing
Figure '14 shovls the phase tirni1l:gofthe DMG and AS inputs during a synchronous DMAoperation.
The timing relation of these signals is the samdor a CSR or memory operation. Th~'CS/DP> input
selects synchronous or asynchronous DMA operation.

CVAX BUS

MeLKA

MClKB

Figure 14· CVAX 78588 Synchronous DMG and AS Timing

CPU or SynchronousDMA Read Operation Timing
Figures 15 through 21 show the CPU or synchronous DMA read timing for the various transfer
operation. For all operations CDAL< 31:00> selects single or quadword transfers, CS/DS < 3:0>
selects no read lock and the PMI cycle is 4/2 selected by th~ control and status register CSRI7. For
additional information on read lock, refer to the Operations section. Refer to the Register section for
information on the PMI cycle select functions of CSR17.
Single Transfer Read (no memory errors)-Figure 15 shows the phase timing for a single transfer to
a CSR or a memory read operation with no errors detected. The phase timing relationshl,pjs not
shown in the following diagrams unless it is different.

2-34

Confidential and Proprietary

Figure 15 • CVAX 78588 .CPU or Synchronous DMARead Timing (Single-No Memory Error)

Confidential ru;ld Proprietary

,~-~~~-

..

.

-----.---~ --"--<--~-.------

--

2-35

CVAX78588
QuadwordTransfer Read (no memory error)--Figure 16·shows the pha$e timing for a quadword
memory read operation after the AS signal is asserted with no memory erJX)r detected.

CVAX BUS

MelKA

MCLKB

CDAL<31 :00>

ROY

Figure 16· CVAX 78588 CPU or Synchronous DMA Read Timing (Quadword-No Memory Error)

Single Transfer Read (uncorrectable memory error)-Figure 17 shows the timing for the ERR
output during a single transfer memory read operation with an uncorrectable memory error. The
memory read operation is terminated when the ERR signal is asserted indicating that an
uncorrectable error was detected. This timing is similiar for quadword, hexword, and octaword
transfers.

2-36

Confidential and Proprietary

_

Preliminary
CVAXSUS

I

P1

!

P2,1 P3 [ P4

I

p,

!

P2! P3

I

CVAX 18588'
-"P'+p-'-'+p_4....I_p_'-'-;;...L...;.;..."-~-'-'c...;."""-'c;.J.-'-'

P4,r---2CYClES~;..'_P'-",-'

MelKA

MelKB

CDAl<31 :00>

ADDRESS

IERD

Figure 17· CVAX 78588 CPU or Synchronous DMA Read Timing,
(Single- Uncorrectable Memory Error)

Confidential and Proprietary

2-37

mOlllla

Preliminary

Single Transfer Read (correctable memory error)-Figure 18 shows the timing for the eRD and
RDY outputs during a memory read trans'fer with a correctable memory error detected.

CVAX BUS

MelKA

MelKB

CD!\L<31:00>

ROv

~

-I

Ir----------~-

,~----------------------------~,

Figure 18· CVAX 78588 CPU or Synchronous DMA Read Timing (.)ingle-Correctable Memory Error)

2-38

Confidential ,and, PrQ'prietary

:-

Preliminary

QwtdW\)r4 TransferRead(co~table memoryerror)-Figure 19 sho~s

thep~e timing £0J: a
quactword memory read after the AS input is asserted with~ correctable memory error detected.

c:.tAX BUS

MeLKA

MeLKS

CDAL<31:00>

Figure .19- CVAX 7$588 CPU or Synchronous DMA ReadiTiming

.

(Quadword~C(Jrrectable M~oryError)

Confidential and Proprietary

·2-39

CVAX78li88

Preliminary

Single Transfer Read (address miss NOP)~Figure20 shows the timing fdr the NLMR output
during a CPU or DMA single transfer to a CSR or a memory read operation when the address on
CDAL< 31:00> is not within the programmed mngeof the CMCTL.

P1

eVAX BUS

I

P2

I

p, I I P'
P4

P2

I

P3

I

P4

I

P1

I

P2

I P' I P4

MeLKA

MeLKS

CDAL<31:00>

Figuew 20· CVAX 78588 CPU or Synchronous DMA NOP Timing

(Address Miss)

CPU Single '.&ansfer Read {abort)-Figure 21 shows the timing for the ERR and RDY inputs during
a CPU single transfer memory read operation initiated by the CPU when the address on
CDAL < 31:00> is within the programmed range of the CMCTL. The ERR or RDY signals are
asserted by external logic in time to abort the operation.

1..'VA.X BUS

MelKA

MeLKB

CDAL<:)1.00>

INPUT

ERR
.R5Y
LAST SAMPLE WINOOW TO ABORT CMCTl.

HAST SAMPLE WINDOW TO ABORT CMCTL

Figure 21 • CVAX 78588 CPU Memory Read Abort Timing (External Logic)

2-40

Confidential and Proprietary

Prelirinary
CPUorSynclu:ooous DMA Write Operation Timing
Figures 22 and 23 show the phase rirningfor the CPU or synchronous DMA write operations,
Single Transfer CPU Write (unmasked}-Figure 22 shows the timing of the MEMERR output.
This is an opencdtainoutput; and requires an external pullup resistor conneC1:edto VIS- Other
timing considerations are the. same as shown in Figure 23.

NOTE:

THIS IS A·lOW·Cl,.,RRENT PlliL·UP.-tTS TRANsITION TIME FROM nu ASSEA1'W,To.'tlolE ·OMSSEf-IT£D
STATE IS NOT GI.JAAANTEEO.

Figure 22· CVAX 78588 CPU Write Timing (Single-Unmasked)

Quadword Transfer DMA write (no error)-Figure 23 shows the timing for synchronous quadword
unmasked write operation when no parity errors are detected on the CDAL < 31:00 > data. When a
parity error is detecte~> ~he,EJ9l ~igp~iS:.a~~~~ inHead~~~r )U)Y,~~n,a1 and at the same tiine.
When ERR is asserted, the DSinput must remain asserted for. an additional cycle before it is
deasserted to start the next datalrtrlisfer.'The timingforth~ERR signal is the same ast~e
synchronous read operation. Thetiml:ng'fur\a masked wrllte ~mtion is similiarf{')theunmas'ked
write tumng except that one or more slip I.:ydes occur after ASi~~~sertedand until the Rl?X f?r;E:R,~
signaHs asserted. There are also more errol; conditions.~ble:45 lists the number of slip cycles
addecl.in relation to the type of.write operationanderfufcondition. TheCRD,ERR, and RDY
signals are asserted for the same dti1ilHonas for a memory read'operation.

GonfMentialand 'Proprietary

Preliminaq·.

Figure 23· CVAX 78588 Synchronous DMA Write Timing (Quadword-No Error)

Tahle25 ·CVAX785S8 Write Operation Slip Cycles
Slip cycles

: £rom RDY (ns)

Write operation

J:l,rtQr type

Unmasked'

none
bus parity

o

First transfer masked'

none
correctable
uncorrectable

4tcc=200
4tcc = 200 RDY and CRD
4tcc=200 ERR

Second transfer masked>"

none
correctable
uncorrectable
bus parity

6tcc = 300
6tcc = 300 RDY and CRD
6t cc = 300 ERR
6t cc = 300 ERR

o

Add 2tcc = 100 us to all transfers except the first if the previous transfer is masked.
Add 2tcc = 100 ns if the PMI cycle select bit of CSR 17 is set.
1Add 2tcc = 100 ns to all transfers except the first if the previous transfer is unmasked.

1
2

Confidential and Proprietary

Output

asserted

Preliminary
PMI B"sTnning
Figures 24JbrOUgh 33 show the tin:ii.ng of the PMI bus during a reset.condition and during read
an,d wHteopetations. The timing shown is a result of thePMI cycle select bitbdng.set and no
errors being detected. When· the cycle select bit is cleared, the CAS <3:0> outputs are asserted
for an additional.microcyde dUring a memory read operation or during the read portion of a
masked write operation ~ndthe RAS < 3:0> and SE outputs are asserted for an additional cycle
during a memoryrefreshoperation.:No timing conditions on. the CAS < 3:0>, MA < 9:0> ,
RAS < 3:0;>, and WE outputs for an error condition are not critical and are not specified.
The timing for multiple masked write operations is similar to it single masked write, Figure 28,
except that the RASe( 3:0;> outputs· are asserted during the operation.·· For the read signature
operation, the RAS < 3:0 >. outputs are negated.
Duringmem,.ory refresh, Figure 34,theCAS<3:0>aDdWE~putsarenegatedand the
MD< 38:00 > Iinesprovidesth~ command.
The synchroni~er tirning for asynchroJ1oiIs DM,t\ operatioris,Figu,re 34, is uS(!d 9.uri!1gmanufacturing test to determine tpeasyhcruonoUs.6ycletesffi)nse time ofCMCTL.
.

RESET -Figure 24 shows the timing of the PMI bus signals with respect to the RESET input.

When RESET isasserted,aJ1{PMf;:t)utpu-t§ are asynthronl:)usl}r' negated. The RAS < 3:0 >,
CAS < 3:0 >, WE, and SE outputs are negated and then asserted for the first pass of the CMCTL

chip.

Figure 24· CVAX 78588 PM! Reset Timing

Conficlent1~ a,pd Proprietary

CVAX78588

PreUminary
PMI BUS

MelKA

MelKa

RAS

CAS

MA<9:0>

MD<38;OO>

Figure25· CVAX 78588 PMI Read Timing (Single

Transfer)

Figure 26 • CVAX 78588 PMI Read Timing (Multiple Transfer)

2·44

Confidential and Proprietary

-

eVA}'" '185.18

PMt-mJS

MeLKA

MCLKB

CAS

MA<9:0>

WE

Figure 27· CVAX 78588 PM! Write Timing (Sitzgie Unmasked Transfer)

PMtBUS

MeLKA

MCLl(fj

CAS

tpMIO
MA<9:0>

WE

MI:l<38:00>

Figure 28· CVAX78588PMIWrite Timing (Single Masked Transfer)

Confidet;ttial and):?l"QpriCi:tary

2-45

10••11.

PreliminfUlj .

Figure 29· CVAX 78588 PMI Write Timing (Multiple Unmasked Tra~sfer)

Figure 30· CVAX 78588 PMI Write Timing (Multiple Unmasked and Masked Transfer)

2-46

Confide'ntial and· Proprietary

...

Preliminary,

PMI9U$

MeLKA

MCl!o!:B

RAS

CJ:!.S

WE

Figure 31- CVAX 78)88 PMIWrtte Timing (Multiple Masked and Unmasked)

...' Figffre 32 - CVAX 78588Redd Signature Ti'miiig
" ' <,

> :.

~

'- ,.

:

,"

Confidential andProprieta.ry

2"47

Preliminary
CAS<3:0> ~ 0000, wE"" 0, MD<3BrOO> "" COMMAND

Figure 33· CVAX 78588 Memory Refresh Timing

CVAX BUS
MelKA

MeLKB

AS
os
_ _ _...I '-,.--_ _ _ _ _ _ __

Figure 34· CVAX 78588Synchronizer Timing/or Asynchronous DMA Operations

ace Asynchronous Characteristics
A subset of the CMCTL operations are used to specify the asynchronous timing for the CMCTL.
Table 26 lists the asynchronous input timing and Table 27 lists the asynchronous output timing
parameters.

Thble 26 • CVAX 78588 Asynchronous Input Timing Parameters

Symbol

tASDSRL

2-48

Parameter

Requirements (ns)1
Min.
Max.

AS to DMG lead time

o

AS to DS read lead time

50

AS to DS write lead time

50

AS high width

100

AS low width

3.5tcc

Confidential and Proprietary

2tcc'

4000

Preliminary
Symbol

tDMASL

CVAX78588

Parameter

Requirements (ns)l
Min.
Max.

AS to BM < 3:0 > and WR hold

o

Input to AS setup

20

CS/DP3 to AS setup

40

Input to AS hold

20

DMG to AS lead time

100

DS to AS lead time

o
5.0

DS to data delay

tOSHWI

DS to data hold

o

DS high width

175

DS high width

20

4000

DSlowwidth

ns.
'The lead time that results in an AS memory read access relative to DS without synchronization slip
cycles.
'The lead time that results in an AS memory write relative to the DS signal without synchronization
slipcydes.
4The minimum occurs during an address miss and.results irtassertion of· the NLMRsignal for a
minimum of 25 ns (O.5t cc ). The maximum ensures proper refresh timing for dynamic RAMs
'When the ERR signal is asserted, theDS signal must remain asserted for lOOns (2tcC> before·it is
deasserted.
It=50

Thble 27 • CVAX 78588 A~ynchronous Output Timing PIU'8Meters
Symbol

Req~li~ments·(nsl'

Parameter

Min..
tASERH

AS to E.RR and RDY hold

0

t ASNLD

AS to NLMR low delay

2.5tcc

t ASNHD

AS to NLMRhigh delay

t"SERD

DS to ERRand~DY delay

0

t:.)LW

Output low width

100

t RASOD

Read AS to output delay

6.5tcc
8.5tcc
8.5tce
8. 5tcc
10. 5 tee
lO.5tcc

PM!

Max.

cycle

·25
24:5tc~

25
25

8.5tcc
1O.5tcc
1O.5tee
1O.5tcc
12. 5tcc
l2.5tcc

Confidential and Proprietary

N
C
U
N
C
U

4/2'·4
4/2

4/2
5/3
5/3 10
5/3 10

2·49

maliD
Symbol
tRDson

tW!\SOD

tWDSOD

Preliminary
Parameter

CVAX7S'8S'

Requirements (ns)'
Min.
Max.

Read DS to output delay

Write AS to output delay

Write DSto output delay

Error/

PMI

Condition'

cycle

N

2.5t cc
4.5t c<:
4.5t cc
2.5t cc
4.5tcc
4.5tcc

4..5tcc
6.5tcc
6.5tcc
4.5t cc
6. 5tl:c
6.5tcc

U

4/2 1-.
4/2 7
4/2
5/3,,10
5/3';10
5/3 10

4.5t cc
8.5 t cc
lO. 5tcc

6.5tcc
1O.5tcc
12.5tcc

unmasked
masked
masked

4/2"
5/},0

2.5tcc
2.5t cc

4.5tcc
4.5tcc

8.5tcc

1O. 5tcc

1O.5tcc

12.5tcc

unmasked
masked 1st
transfer
masked 2nd
transfer
masked 2nd
second
transfer

C

U
N
C

5,8.H

9,11

4/2,,11
5/3,,11

't=50 ns.

)N l'" O(ime, C == correctable, U =tincorrectable
>During the first transfer of a read (no lock), the output delay is determined by DS when tASDSru.is
greater than 4tcCl and the output delay is determined by AS when tASDSRL is less than or equal to
4tcc ·
 is not within the programm~d range of the CMCTL.

~
. . 'D~ASL_·1_j t~~
'ASCS3SJ

~'ASI"

.r---'-1,\

esoP' jTJ(/,77'//.717i.71'/i,71()71')/'"(j,77')/,77((,77'/1.77
')j,71(/,77!/,7l'jj,TT'/i,7T.

OPTIONAL""'"

\'----

-----({~<:i;:;;:AX;;S;;T.rus;;;-')--

)""":

Figure 35 • CVAX 78588 DMA Transfer Timing (DMG and AS Signals)

Confidential and Proprietary

2·51

Preliminary

Figure 36· CVAX 78588 DMA Read Timing (Single Transfer)

Figure 37· CVAX 78588 DMA Write Timing
2-52

Confidential and Proprietary

Preliminary
As

CDAL<3',OO>

NlMA

CVAX78588

\~-------~1

-.I

=:::::>---<

AIlOOi--r_)_ _ 'ASNLD _ _

\'----

~~_DATA_~--,f'AS:'SS >\_

.

Figure 38· CVAX 78588 DMA Address Miss Timing (NOP)

Mechanical Configuration
The physical dimensions of the CVAX 78588 I32-pin package are contained in the Appendix.

Confidential and Proprietary

2·53

~-----,-----"--.-------------------------------

2-54

Confidential and Proprietary

. Features
• 32-bit CVAX bus to16~bit Q22-bu$i~terface .
• Integral Q22-bus transceivers
• 16-entry cached copy of the external 8 K longword scatter and gather map
%',',1 *',:, .'r

'

• Performs scatter and gather operations and map control and address tr~nslation
."

'

. '

I:

j

• .Powerup, initializati0l1,po~ed~. andpqw:erdown contrql
• Integral address decoding for internal registers, scatter and gather map locations, and Q2'2'Jbus
references
• MicroVAX II-compatible doorbe'Il register

• 1wo Q22-busoctawordwrit~ buffers apd a qmtdword readjJuHer
• Transparent alignment of 52-hit and 16-bitdata transactions
• Longword, quadword, hexaword, and octaword CVAX bus DMA transactions

• Q22-bus nonblock and block-mode transaction support
• Q22 cbus arbiter or auxiliary mode operation
• Single 5-~lt power supply

. Description
The CVAX 78711 Q22-bus Interface Chip (CQBIC) is an asynchronous interface adapter for use
between the 32-bit CVAX 78034 CPU and its it)ternal memory and the 16-bit Q22-bus. :Figure 1 is a
block diagram of the CVAX 78711 CQBIC.

(l22·BVS
Mi\"l'Ht .:aNTROL

Figure 1 • CVAX 78711 Q22-bus Inter/ace Block Diagram
Confidential a~d Proprktary

2-5,5

Preliminary

CVAX78711

The CQBIC performs the necessary address mapping and 32-bitand 16-hit data alignment. The
CQBIC can function as the Q22-busarbiter or as an auxiliary device. The CQBIC contains scatter
and gather map translation and control logic, a 16-entry cache of the external 8 K longword
mapping registers, a system configuration register, a DMA error register with master and slave
address error registers, a MicroVAX II-compatible doorbell register and Q22-bus transceivers. The
CQBIC uses a single 5-volt power supply, is available in a 132-pin surfacemount ceramic package,
and dissipates less than 1.5 watts of power.

• Pin and Signal Descriptions
This section provides a description of the input and output signals and power and ground
connections used by the CQBIC. The signal pin assignments are shown in Figure 2 and summarized
in Table 1.

fORESET

AUX

118

VSS

82

CDAl03

VDO

119

81

CDAl02

CS5P2

1.20

80

CDAL01

CSDPT
BiorD
TAKI

121

COALOO

123

79
78
77

lAQ3

124

76

TB40M

i'RQ2

125

r----------------~

IRQ1

126

I
I
I
I
I

75
1.

TEST

122

TROO

127

PWAFL

128

SvSRESET

129

RTNiT

130

NCQBjtR
vss

131

132

8M3
8M2

SMl
SMO

I
I
I
I
I

I

I

1
I
I
I

r,:NAX 78711 022·BUS INTERFACE CHIP

(CAVITY DOWN)

I

NLMA

I
I
I
I

I

I
I
I
I
IL ______________ I

WR
AS

os

~

CLKOUT

VOO
VS5

73

BTRQ4

72

BiR05
BI1i06

71

70

BTAQ'f

69

EXTCAP

68

vss

67

V[)O

66

VBIAS

65

BOCOK

64

8POK

63

B5MA

62
61

BHAlT

60

aSACK

BREF

59

BOOUT

58

V55

11

57

12

56

Jmffi
WIN

,.

55

BSYNC

CCTl

54

BWfBT

P.liEMERR

15

53

B1ART

HALTIN

16

52

BIAKO

V55

17

51

voo

VDD

SYSERR

10

SYSRDY

DMR

OMG

13

Figure 2· CVAX 78711 Pin Assignments

2-56

83

Confidential and Proprietary

Table lCVAX 18711 Pin and Signal Summary
Pin

Signal

18-22
24-26,28,
29,32-36,
38-42,44,45

BDAL<21:00> Input/Output

Q22-bus Data/Address Lines-Time multiplexeQ, bidirectional data and address lines.

63

Input/Output

Q22-bus DMA Request-Requests bus mastership for DMAtransfets.

62

Input

Q22-bus Halt-A CPU halt request by way of
the liALTINsigna!.

61

InputjOl.l t put

Q22-busre£erence;c...A. strobe used to coordi.
'nate block-tnode trankfers.

. Input/Output

Denniti .
...
-~r'·

57

Input/Output

Q22-bus Reply-A strobe to indicate that the
slave .

Input/Output

Q22-bus Write and Byte Select-Provides bus'
cycle control. During the address portion of a
bus cycle, it indicates an output cycle. During
the data portion of a bus cycle. it indicates a
byte transfer.

53

Input

Q22-bus Interrupt Acknowledge In-Intermpt
acknowle;dge daisydlain input ..

52

Output

Q22-bus Interrupt Acknowledge Out-Interruptacknowledge daisychain output.

.54

BWTBT

Confidential' and Proprietary

2-57

Preliminary.
Pin

Signal

Input/Output

CVAX78711

Definition/Function
Q22.:bus Interrupt Request lines-Interrupt
request lines for Q22-bus devices.

70-73
49

Input/Output

Q22-bus Bank 7 Select-Indicates an I/O page
reference or block-mode transfer.

48

BDMGI

Input/Output

Q22-bus DMA Grant In-The DMA grant
daisychain input.

47

BDMGO

Input/Output

Q22-bus DMA Grant Out-The DMA grant
daisychain output.

46

BINIT

Input/Output

Q22-bus Initialize-Q22-bus reset signal.

79-82,
84-90,
92-98;
100-107,
109-115

CDAL < 31:00 > Input/Output

CVAX Data/Address lines-Time multiplexed,
bidirectional data and address bus.

120·122

CSDP<2:0>

Input/Output

Control Status/Data Parity-Provide status
information about bus cycle.

7

Input/Output

CVAX Address Strobe-CVAX system address
strobe.

8

Input/Output

CVAX Data Strobe-CVAX system data strobe.

Input/Output

CVAX Byte Masks-Identify the bytes of the
CVAX bus and parity bits that are valid.

Input/Output

CVAX Write-Provides read and write control
for the bus ..

1-4

BM<.3:0>

6
11

SYSRDY

Input/Output

CVAX System Ready-Provides normal termination of the current bus cycle. Used with the
SYSERR signal to request a retry of the current
bus cycle.

10

SYSERR

Input/Output

CVAX System Error-Provides abnormal termination of the current bus cycle in the event of
an error. Used with SYSRDY to request a retry
of the current bus cycle.

12

Output

CVAX nMA Request-Requests the bus for
DMA transfers.

13

Input

CVAX DMA Grant-Grants the bus for a DMA
transfer.

Odtput

CVAX Interrupt Request lines-These lines are
used to ~pass interrupt requests to the CVAX

124-127

IRQ<3:0>

CPU.

2·58

Confidential and Proprietary

mliDDIJ

Preliminary

Pin

Signal

Input/OUtpUt

Definition/Function

15

MEMERR

Output

CVAX Memory Error-CQBIC requests an

interrupt for a nonexistent memory error.
128

PWRFL

Output

CVAX Powerfail-Indicates a powerfail condi-

tion on theQ22-bus.

14

CCTL

Output

CVAX Cache Control-Provides the means to
invalidate CVAX cache entries when the CQBIC

accesses local memory.
129

SYSRESET

Output

Syste,m Reset-initializ~s C"VAX cpu during
the powerupsequence.··
/'j .

16

HALTIN

Output

118

AUX

Input

, :~l

.

,;'" .

Halt-fIaltsthe CVAX CPU.

'Auxiliary....:-Sdects·the operating mode of the
.CQBIC.

117

IORESET

Input

131

NCQBICR

0\ftput

123

IAKI

Input

I/O Reset-Ee,sets devic.es on the CVAX bus and

Q22-bur

·'i·;

.' ...•.

•.

.,

.•...

Not CQBlC R~f;eren~:..;;,;.~n4icate~ that the
adPrcssonthe CVAX bus is not for tlAc CQBIC.

Interrupt Acknowledge In .......:Ena:hles the
CQBlC to .respond to. an interrupt acknowleoge

cycle on the·CVAX bus.
Input

5

Not Local·· Memory Refer:ence~ lriditateS 'that
the address on the C,'lA'XbU:sis noti local
memory address.

Outp)Jt

130

76

TB40M

Input

78

CLKOUT

Output

~eceiv~ Initialize-lIJidtUiies the•. cvAx . blis
an4 bril)~~ ,sy~t~m toa predetermjned ~tate.

Clock'Out-,--Thisoutput is used for test dUrihg
manufacturing of the CQBlC: .

9,51,67,
91,106,

'

Input

Voltage~Pow~r
supply vohage.' , '.
. '.,

Input.

Ground ,reference,

Input

Q22-bus Bias~Provides the bias voltage for
Q22-bus transc~ivers on the CQBlC.;.

.'

;

;

,

108,119

17,23,27,
31,32,37,

43,50,58,
68,75,83,
99,116,132

66

Confidential and.Proprietary

2-59

Preliminary

CVAX787U

Pin

Signal

69

EXTCAP

Input

External Capacitor-Provides a 100 ms delay
of the nDCOK input when 1.0 i-lF external
capacitor is connected to this pin.

74

TEST

Input

Test-Used for test during manufacturing of
the CQBIC.

, Input/Output

Definition/Function

Q22-Bus Signals
Q22-Bus Dam Address Lines (BDAL < 21:18 > )- These lines are used to transfer address
information between the CQBIC and the Q22-bus.

Q22-Bus Dam Address Lines (BDAL < 17 :00»-These time-multiplexed lines are used to
transfer address, data, and parity control information between the CQBIC and the Q22-bus.
During address protocol, BDAL < 17:01 > transfer address information and BDALOO specifies a
high or low byte during DATOB and DATIOB cycles. During data protocol, BDAL < 17 :16> transfer
parity control information, and BDAL < 15:00> transfer data.

Direct Memory Access Request (BDMR)- This line is asserted by the CQBIC or another device on
the Q22-bus to request bus mastership.

Processor Halt (BHALT)- This signal, when asserted, requests a CPU Halt through the BALTIN
output. The CQBIC asserts the BALTIN signal if it is enabled by the SCR registel:

Block Mode Reference (BREF)-This signal is asserted or deasserted with the BRPLY signal by
block mode slave devices to indicate to the bus master that the slave can accept another block mode
data in (DIN) or data out (DOUT) tmnsfer.
DC Power OK (BDCOK)- This is a power supply generated signal that is asserted when sufficient
dc voltage is available to allow reliable system operation. It used as part of the powerup and
powerdown protocol and boot protocol.
AC PowerOK (BPOK)- This signal is asserted by tbe power supply when the primary ac power is
normal. If the signal is deasserted during processor operation, a powerfail trap is initiated. This is
part of the powerup and powerdown protocol.

Slave Acknowledge (BSACK)- This signal is asserted by a DMA device wben it becomes Q22-bus
master. Tqe device will assert this signal while it is bus master. Wben the device has completed
using the bus, it deasserts BSACK.
Dam Output (BDOUT)- This signal is asserted by the Q22-bus master to indicate that an output
transfer, with respect to the bus master, is in progress and that valid data is on BDAL < 15 :00> .
This signal is deskewed with respect to the data placed on the bus.

Reply (BR.PI.X)- This signal is asserted by a Q22-bus slave device in response to the assertion of
the BDOUT or BDIN signal or by a device responding to an interrupt acknowledge (IAK) transfer.
When BRPLY is asserted in response to the BDOUT signal, the slave device has read the data from
BDAL < 15 :00>. When it is asserted in response to the BDIN signal, the slave device has placed
the requested data on BDAL < 15 :00> . When BRPLY is asserted during an IAK transfer, the device
responding to the interrupt has placed a vector on BDAL < 15 :00>.
Data Input (BDIN)- This sighal is asserted during the time that BSYNC is asserted to indicate that
the current hns master requiresaresponse from the addressed sla~e device. It is also asserted by the
interrupt fielding processor and is followed by the assertion of the BlACK output to initiate the
interrupt service.
2-60

Confidential and Proprietary

CVAX787l1
Synchronize (DSYNC)-This signal is asserted by the Q22-bus master to start a bus transfer and to
indicate thatithas transferred an address onto the BDAL< 22:0'1> lines ..The transfer continues
until this signal ~sdeasserted. For blockmodetransfers, the BSYNC signal is asserted until the; last
transfer cycle is cC:lmplete.
Write Byte (BWTBT)-This signal is used to control a bus cycle. It is asserted during the address
portion of a bus cycle to indicate that a DATO, DAIDB, or DATBO output cycle is to follow instead
of an input cycle. It is alsoassertesi4IJril1g the.q~~iportion9iabATOB()rDATBO cycle to indicate
that a byte transfer will follow' instead of a wordtranifer. .
Interrupt Acknowledge In (DIAKI) and Interrupt ACittnwledge Out (DIAKO)-The processor
asserts the BIAKO input to acknowledge an interrupt request according to the ini~rrupt protocol.
The bus transmits the status of this signal to the BIAKI input ofthe next priority device electrically
closest to the processor. This device accepts the interrupt acknowledge, if it had previously
requested the bus, by asserting one of the interrupt requestHhd(BIRQ < 7:4 » or if it is assigned
the highest priority interrupt request on the bus when the ,~p.fN$jgnal was previously asserted. If
both of these conditions do not exist, the device asserts theBIAKOoutput to the next device on
the bus. This process continues in a daisychain configuradon until the device with the highest
interrupt priority reCeives theBIA,Ivledgesign~ and continues the interrupt
protoc~Is~uence.·
.
.'.
..
"
Q22~~us.Jnterrupt Request(BIRQ.~ 7:4 > )",,:-These~ignalsa.rt; asserted by devices on.the Q22·
bus to request an interrupt. If .the CQBJC i.s in arbiterrnfJ~f;, 'theCQIHC wil1tra~fer these signals
to the appropl'iateCVAX IRQ< 3:0;;:- line asindic~ted in T~bl~ 2:

Bank 7 Select (BBS7)-This signal is asserted by the bus rnasterto reference the I/O p~e including
the part of the 1/0 page reserved forru::ll:lexigtefitmemory.When'BBS7 is asserted, the address on
BDAL < 12:00> isthe I/O page address. During DATBI transfers,the bus master asserts this signal
transfe~s will occur.
to indicate to-: the,"block-mode
slave device that subsequent
",
>.< ':i"'":,::."!,;F",,
DMA Grant In (BDMGI) and DMA Grant Out (BDMGO)-The bus arbiter asserts these signal to
grant bus mastership to a device that had requ~sted useofthtfbusby asserting the BDMR signal.
The arbiter grants the use of the bus by asserting the BDMGq signal. This signal is passed in the
daisychain configuration through the bus to theBDMGlinputof the next priority device
electrically closest to the bus. This device accepts the grant ififnidasserted the Bi5MR signal. If it
did not, the device passes the DMA grant to the n.ext de\!ij;e pp. thehus by asserting BDM GO. This
sequence continues until the BDMGI input of the requesting device is asserted. The device stops
the DMA grant by not asserting its BDMGO output and acknowledges the grant by asserting the
BSACK signal after both the BRPIY and BSYNC signals are deasserted.
Initialjze (BINIT)-This signal is used to reset the system. When asserted, all. the devices on the
bus are set to a known state. The initialize process includes clearing registers, disabling bus drivers,
and setting the internal logic for an operation. ,Exceptions to the normal initialization must be
documented in programming engineering specifications'for the device.
Confidential and Proprietary

2~61

Preliminary .
CVAXBus and System.conuol·
CVAX Data/Address t1.ines(CoAt <31:00 » ...... 'These are bidireetidhal time-multiplexed lines
uSed to transfer information between the CQBIC and the CVAXCPU or local memory.
During the first part of a read or write bus cycle, CDAL < 31: 30> indicates the lehgth of the
memory operand as listed in Table .3.
Thble3 ~ CQBIC 78711 Memory Operand Length
CDJ\Lline

3i

3()

0

0

hexaword

o.

1

longword

1

0

guadword

1

1

octaword

CDAL<29:02>coritain the longwordaddress o{the memory operand. The BM<3:b> lines
specify which byte(s) of the longword address are to be used. The CDAL29 specifies a memory
spat.e address or aoI/O space address. When CDAL29 is 0, memory space is specified,andWben
CDAL29 is 1, I/Ospaceis specified. The CDAL < 01:00 > ) are reserved.
During the first part of an interrupt acknowledge cyeIe,CDAL < 06:02 > transfer the hexadecimal
number of interrupt priori~Yleve~9h~ interrupt being acknoVlleclg~d and CDAL < 31:07 > and
DCAL < 01:00 > are zeros. During the second part of a read cycle, CDAL < 31:00 > transfers the
incoming data. During the second part of an interrupt ackilowledge cycle, CDAL<31:00>
transfer the vector required by the CPU. During the second part of a write cycle, CDAL < 31:00 >
transferthe outgoing information.
Coptrol Staws/Data Parity ('' c;';;s;;::n'' 'p;:-'<-::.-;:;:2-;:0"">"-)-These lines and the WR line provide the status of the
current bus cycle as listed in Table 4. The CSDP< 2:0 > line information is valid when the AS line
is asserted. The CSDP<2:0> lines are not used with the CQBIC which does not support CVAX
bus parity.
Table 4 • CQBIC 78711 Cycle Status*

WR

CQ~IC

CSDP
2
1

0

L

.L

L

H'

reServed

none

H

L

eX~i7rnalIPR read,

none

H

H

interrupt acknowledge

IAK

H

,L

ryguest ~ead (I-stre~m) .

read
read-lock

H
H

Bus
transaction
,
,":-

"(

read

H

H

L

H

demand read-Ibck

H

H

H

L

demand read (D-strea

H

2-62

Operation

rn, modHyinterit)

derhandread.(D.stream,no modify intent) .

Copfidential and Proprietary

read

!IIIIII

Prelitninary

WR

Bus

CSDP
1
2

0

transaction .

CQBIC
Operation

L

L

L

L

reserved

L

L

L

H

reserved

L

L.

H

L

~xternallPR .wri4!

H

H

reserved fdrDM1\ device

L

L

H

L

L

reserved

L

H

L

H

write-unlock

L

H

H

L

reserved

L

H

H

H

write (D-stream)

(-~

none

:

write-unlock
"

,"

. hone

*H is a high level, L is a low level
The CQBIC ignores modify intent transactions and considers a write transactiolias.a write-unlock.
When the CQBICoccesses to local memory,: the CSDP<::Z:O::>1in& are set high 'for all tead and "
write operations.

Address Strobe (As):-This bidirectiotiaI signal indicatesthatv~lid address inf?rmadonis present
on the CVAX bus. The AS signal is asserted at th~ beginiring ofa bus cyde:toindicarethatvali'd
address and control information is on CDAL <:31:00> ,CSDr <: 2:fJ>, BM< 3:0> 'and Wit lines.
AS is deassertedaf the conclusion of the bus cycle.
Data Strobe (DS)-This signal provides timinginf6rmatiotdor  are available to
receive incoming data and is deasserted to indicate that the data has been received and latched by
the requestingdevice (CVAXCPOjCQB1C,etc~),,'purirlg!lwri.t;~ cycle,.~tM.asserted to indicate ihat
CDAL < 31: 00> contain valid outgoing data ~nd isdeasserted to indicate that the sending device
will remove the d a t a . ·
'
Byte Masks (BM <3:0 > )-These signals indicatewhichbytf!S of the cVAx'bhstontain valid qata
during the second part of a read or write bus cycle as defined in Table 5. During a read cycle, these
signals indicate which bytes oftlie CVAX bus musttran1'fer-tl1e data. All other bytes ate ignored.
During a write cycle, the BM < 3:0> lines indicate which bytei; of the CVAX bUs containvalid data.
During an interrupt acknowledge bus cycle, all four byte mask lines are asserte/;1. The BM < 3:0::"::!
lines are qualified by the asscrtionof the ASsignaI.For read bus cycles, all bits of the byte(s)
specified by BM < 3:0> must be set tohigh or low levels in accordance with thr; setup times
defined in the Specification ?ection.
"',

<

-.:

,"

" " ,

,Table; • CVAX 787U i3yteMaskf.fapp~
,i

Byte mask
asserted

"

_,', " -

:':

' , ""

-

,

, ' ; ~,

.

Valid data
CDAL < 31:24 >
CDAL<23:16>
CDAL< 15:08>
CDAL< 07:00 >

2-63

Preliminary •

CVAX787U

Write (WR)-This signal indicates the direction of the data tl1lnsfer on the CVAX pus for the
current bllscycle.When WR is asserted during a bus cycle,da,t,a ist~nsferred to the CVAX bus by
the originator the bus cycle. When WR is deasserted durIng a bus cycle, the requested data is
transferred to the hus by the responding device. WR is qualified by the assertion of the AS signal.

of

System Ready (SYSRDY)-This bidirectional signal indicates that the normal termination of the
current CVAX buscyc1e has occurred. It is also used with the SYSERR signal to request a retry of a
bus cycle generated by the CVAX CPU. Assertion of this signal during a CVAX bus read or interrupt
acknowledge bus cycle indicates that external logic will transfer the requested data onto the bus
according to the timing requirements of the bus cycle in progress. Assertion of this signal during a
CVAX bus write c.ycle indicates that external logic will receive the information on the bus according
to the timing r~qujrements of a write bus cycle.
System Error (SYSERR)-This bidirectional signal indicates the abnormal termination of the
current bus cycle. It is also used with with the SYSRDY signal to request the retry of a bus cycle
generated by the CVAX CPU.
DMA Request (DMR}-This signal is asserted by the CQBIC to request use of the CVAX bus and its
related control signals.
DMAGrant (DMG)-This signal is asserted by the CPU to grant control of the CVAX bus and its
related control signals to external logic. If the CQBIC has asserted the DMR signal, the CQBIC will
respond to the assertion of i5MG by assuming control of the CVAX bus and its control signals.
Interrupt Reqllest(IRQ < 3:0 »-These signals are used to pass interrupt requests to the CVAX
CPU. The CQBIC tlses IRQO to pass a Doorbell register interprocessor interrupt request to the local
system. When the CQBIC is in arbiter mode, it maps the interrupt requests from the BlRQ < 7:4 >
of the Q22-bus to IRQ < 3:0 > as listed in Table 6.

'Thble6 • CVAX 78711 InteruptRequest Mapping
Q22-hus
request

CVAX
request

Priority level
(hexadecimal)

BIRQ7

IRQ3

1PL 17

BIRQ6

IRQ2

1PL 16

BIRQ5

IRQ1

IFL 15

BIRQ4

IRQO

IPL 14

Memory Error (MEMERR)-This signal indicates that a nonexistent memory interrupt request to
the CVAX CPU has occurred. The CQBlC asserts this signal with the assertion of the AS signal at
the beginning of the next CVA:X'lJl.isc.ycIe.It remains asserted until the DS signal is deasserted at
the end of the bus cycle.
Powerfai1 (PWRFL)-This signal indicates a power fail condition on the Q22-bus. The CQBIC
asserts this signal when the BPOK input is deasserted.
Cache Control (CCTL)-This signal is used to invalidate the cache memory in the CVAX CPU
during write transactions to local memory. The CQBIC asserts this signal when it performs a write
to local memory and causes the CVAX CPU to perform a cache invaHdate cycle.
System Reset (SYSRESET)-This signal is used during the powerup seq\.lence to initialize the
CVAX CPU. It is asserted when the BDCOK input is deasserted.
2-64

Confidential and Proprietary

Preliminary

CVAX78711

Halt In (HALTIN)-This signal is asserted in response to the assertion of the BHALT input frqrn
the Q22-bus. It is controlled by bit 14 of the system configuration register, by bit 08 of the doorbell
register and by the operating mode of the CQBle.
CQBIC and System Control
Auxiliary Mode (AUX)- This signal selects the operating mode of the arbitration logic of the
CQBlC, the master logic, the powerup and reset sequences; and the doorbell register. The CQBlC
samples tIlls signal when the AS signal is asserted to determine its operating mode. When it is
deasserted, the arbitration mode of the Q22-btlSis selected. The CQBle is then the arbiter for the
Q22-bus. Only oneCBIC can be bus arbiter when more than one;CBICare available. When this
signal is asserted, auxiliary mode is seleCted arid the CQBlJ!C does not' perform arbitration for
Q22-bus.
"

I/O Reset (IORESET)-This signal resets the devices on theCVAX bus and the Q22-bus as
determined by CQBlC operating mode. When ids asserted,theCQBlC gains control of the CVAX
bus and the Q22-bus by first asserting theI5MRoutput anclihen the BDMR output. When the
DMG and BDMGI signakare asserted, the CQBIC asserts theRINlT output to initialize tbe
devices on the CVAX bus. 'If the CBIC is not in auxiliary mode {AUXdeasserted), it asserts tbe
RINIT output to initialize the Q22-bus.
Not CQBlC Reference (NCQBlCR)-This signal indicates that the address on the CVAX bus is not
a CQBlC address. When the CVAX initiates a bps ttWlsactionthat is not intended for the CQBIC'or
a bus transaction that is not an interrupt ackn6wledge cyde,the CQSTe asserts this signal when the
DS signal is asserted by the cvAx.
'
Interrupt Acknowledge Enahle(JAKI)-This signal is asserted to allow the CQBlC to respond to
interrupt acknowledge l)Tcleson the CVAX bus.' It is normally connected in a daisychain
'
configuration with theC~)'BIC as the last device in the chain .. ,
Not Local Memory Reference(N~MR)- T/lissignal indicaLy~that the address on the CVAX bus is
not a local memory address. When asserted •.it notifies thG CQBlG of an attempt ,to ,access
nonexistent local memory from the Q22-b~s. '
Rece~ve Initialize (RINIl')- This signal is used to initialize devices on the CVAXbus and initialize
the system to predetermined state. It isaS{lerted during thepowerup sequence or in response to the
assertion of the IORESET input.

,
Clock Timing
40-MHt Clock (TB40M)-,-A 40-MHz dock inputforthe CQBlC timing. This inputis divided by
two (20 MHz) for use by the CQBIC Thetirning sequence is started by the first rising edge of this
input following the deassertion of SYSRESET input.
C]ock Output (CLKout)-A 20-MHz clock output from the CQBle. This signal is generated by
the CQBlC and is used only during manufacturing test of the CQBlC.
'
Power and Ground
Voltage (VuD)-5-volt power supply input.
Ground (Vss)-Ground l;eference.
Voltage ,Bias (VBIAS)-The bias voltage for the Qn-bus transceivers. This pin should be
connected to gro\lnd through a resistor with a tolerance of 1 percent. The value of the resistor is
selected to provide.a bias current of 300 microamperes.

Confidential and Proprietary

2-65

Preliminary
Miscellaneous·
External Capacitor (EXTCAP)-This pin connects to an externa11.0 [.IF capacitor to generate the
lOO-millisecond delay for EDCOK output during the pO\l,l'erup sequence.
Test (TEST)-Used only for manufacturing test of the CQBIC.

Functional Description
The CQBIC provides the interface between the CVAX 78034 CPU and its local memory and the
Q22-bus. The CQBIC can perform Q22-bus arbitration or can function as an auxiliary device on
the Q22-bus. The CQBIC contains a 32-bit CVAX bus to 16-bit Q22-bus interface, scatter and
gather map translation and control logic, a 16-entry cache register that contains the external 8 K
Jongword mapping registers, a system configuration register, a DMAerror register with master and
slave address error registers, a MicroVAX II-compatible doorbell register and Q22-bus transceivers.
The CQBIC contains a master, slave, arbiter, .md cache section. The master section monitors the
CVAX bus addresses and control signals and performs operations directed to the internal regi~ters
of the CQBIC. It moriitors the Q22-bus master transactions and requests assistance with scatter
and gather. map operations from the slave section. 'TI1e slave section monitors the Q22-bus
addresses and control signals and performs operations directed to the CQBIC from a Q22-bus
master. It controls the doorbell register and performs transfers to and from local memory. The
master and slave sections of the CQBIC use the cache registers to validate Q22-bus addresses that
are to be mapped into local memory. The cache section uses the slave section to perform the local
memory operations directed to the scatter and gather map registers in local memory. The arbiter
section resolves conflicts between the master and slave sections that relate to the use of the CVAX
bus, the Q22-bus, and Q22-bus DMA and interrupt acknowledge arbitration. It also controls the
powerup and pawerdown sequence and the initialization protocols.
The CQBIC supports master transactions that are byte, word, and Iongword transfers from the
CVAX bus to the Q22-bus and to the internal registers of the CQBIC. It also supports slave write
transactions that are byte and word write transfers, blockmode word write transfers from the Q22bus to local memory on the CVAX bus, and slave read-modify-write word transactions that are
block-mode word read transfers from Q22-bus to local memory. The CQB£C also supports localmiss and global-hit transactions from the CVAX CPO to Q22-bus memory space where the Q22-bus
map translates the address back into the local memory space,
Q22-bus Interface
The Q22-bus interface supports nonblock-mode and block-mode transactions. As a Q22-bus slave,
the CQBIC supports the following DEC Standard 160 transactions: DATI, DATIB, DATO, DATOB,
DATIO, DATIOH, DKfBO, and DATBl. As Q22-bus master, the CQBIC supports the following
transactions: DATI, DATIB, DATO, DATOB, DATHO, DATBI, and interrupt acknowledge (IAK)
transactions. As Q22-bus masterl the CQBIC supports Q22-bus master read parity errors and Q2;2bus nonexistent memory timeollts.
.
.
When the CQBIC functions as a slave to a Q22-bus block-mode write transaction, it stores up to 16
words and maintains the address alignments. The contents of the storage buffer.is thep. transferred
to local memory in two octaword transfers. When a Q22-bus block-mode transfer is not 16-word
aligned, the CQBIC stores up to the 16-word boundary, stops replying as a Q22-bus block-mode
slave, and performs the transfer to local memory. The CQBIC controls address alignments of blockmode write transfers of two to eight words~ \'Q'hen the CQBIC responds as a slave to a Q22~bus read
transaction, it stores up to a quadword of data before the Q22-bus block-mode read transfer. The
CQBIC performs a read prefetch operation froin local memory when the third word of its internal
quadword buffer is transferred to the Q22-bus block-mode master that is performing a DATEI
transaction.
2-66

Confidential and Proprietary

Prelnnmary
Address Decoding

.

The CQBIC performs all address decoding for its internal registers, Q22-bus memory and Q22-bus
I/O address spaces, and for the external scatter and gather map registers. It also ptovides a notaddreslled signal (NCQBICR) for system use. The CQBIC latches the address from the CVAX bus
wiFh the..assertion of the AS signal. In addition to the address.. the <;:QBlC Jatches the
CSDP<2:cb, BM~3:P>, and W'~ inforrnlltlonto determine the type of tt'a.psact;ion. The valid
physkal addresses that are decoded by the CQBle are listed in Thble 7. All other physical addresses
cause the CQBIC to assert its NCQBICR signal.
Table 7· CVAX 7871l~VAX BusPltr~calr\ddr~sD~~es
CVAX ~us addresses

. Address description.

20000000 to 2000 IFFF

Q22-bus I/O space

2008 0000 to 2008 0010

CQBlC lhternalregisters

2008 8000 to 2008 FFFC

Q22-bus scattel! ,a.ndgi;lther m~lp registers

30060000 to 303F FFFF
The doorbell register is located in Q22-bus 1/0 space. Its address is determined by ttlem6de of
pperation of the CQBIC and bits 03:01 of the system configUt'~tion register.

Clock,....

The CQBIC requires lln external 40-MH.z TTLcIQc~in~9t that can be async~rol1ous (lr
synchronous to the dockohhe CVAX CPU. This fixed :raieclo~kptoduces a two-phase 'mt~rna120MHz clock and the requiredQ22-hus timing in accdrdaricewith DEC Standard 160. TheCQBIC
operates with a CVAxbuscycletime of 100 to 80nanoset6nrts aad a Q22-bus with fixed timing.
Registers
The CQBIC contain:s$appingregisters, error registers, an4.u configuration register. Ituses.the
doorbell register, located in the I/O page of.tpe Q22,hU:~, address space, for interprocessor
communications .. '
.
"

MappingRegisters (MRA)-The Q22-bus scatter a,n~ gather milp contains 8192 mapping registers.
Each MRA maps a page (512 bytes) of Q22-bus address space into a selected page of local memory.
The MRA format is shown in Figure 3 and described in Table 8.
'

3130 ' 2 0 1 9

00

If I:: :: t: :::I:;:; ;;: :tH1~: :::::::I
Figure 3 • CVAX 78711 Mapping Register Format

Confidential and Proprietary

2~67

CVXXiS1U
Thble 8 • CVAX 78711 Mapping Register Description

Bit

De~ripdon

31

V (Valid)-Whdt set; this bit indicates that mapping is enabled to a page in Q22-bus
address space specified by bits 19:00 of this register. When cleared, the mapping for the
selected page in Q22~bus address space is disabled and the CQBIC does not respond.

30:20

MBZ (Must be zeros)- These bits are read as zeros.

19:00

A28 to A09 (Address bits 28:09)-This field contain the physical page address in local
memory to which the Q22-bus address is mapped.

The mapping registers are located in the local processors I/O space at physical addresses 2008 8000
through 2008 FFFC (hexadecimal). Each MRA is located on a longword boundary and is byte
addressable. The physicallongword address of each register is such that bits 14:02 of the physical
address are identical to bits 21:09 of the Q22-bus address. The actual location of the scatter and
gather map in local memory is determined by the map base register that contain the starting
address of an aligned 8 Kblock of local memory. Only the local processor can directly access these
registers through the CQBIC. Table 9 shows the relationship of the mapping registers to the Q22·
bus addresses.
Table 9· CVAX 78711 CBIC to Q22.bus Address Mapping
Register address
(hexadecimal)

Q22·bus address
Mapped (hexadecimal) ,

Mapped (octal)

20088000
20088004
20088008
2008800C

00 0000 - 00 OlFF
000200 -00 03FF
00 0400 - 00 05FF
000600 - 00 07FF

00 000 000- 00 000777
00 001000- 00 001 777
00 002 000 - 00 002 777
00003 000 - 00 003 777

20088010
20088014
20088018
2008801C

00 0800 - 00 09FF
00 DAOO - ocroBFF
00 OCOO - 00 ODFF
00 aEOO - 00 OFFF

00004, 000 00 005 000 00006000 00007 000 -

00 004 717
00 005 777
00 006 777
00 007717

•
2008 FFFO
2008 FFF4
2008 FFF8
2008 FFFC

3F F800 - 3F F9FF
3FFAOO - 3F FBFF
3FFCOO - 3F FDFF
3F FEOO - 3F FFFF

17774000 -17 774 777
17 775 000 - 17 775 777
17776 000 '" 17 776 777
17776000 -17777777

Note
The system boot PROM must remove the local memory space used fot the scatter and gather map
registers from the bit map of good memory. Direct accesses to the local memory copy of the map by
a device other than the CQBIC can result in nonvaIid data in the cache of map registers of the
CQBIC and the results are unpredictable.

At powerup time, the scatter and gather map registers and their valid bits are undefined. These
registers are not altered by system or local resets.

2-68

Confidential and Proprietary

CVAXi8711
Cached Map Registers (CMR)- The CQBlC maintains a 16-entry cache .of map registers that
performe all mapping fundions. If the cache does not contain a valid copy or the map register used
to map a Q22-bus address into local memory, the CQBlC obtains the required reghtetinformation
from the scatter and gather map. Only map registers that have their valid bit set are stored inthe
cache of the CQBle. The CMR replacement algorithm is first-in/fitst-out (FIFO). The format of
the CMR is shown in Figure 4 and described in Table 10.

3332

2019

00

:::1.

a
1I \ : : ++BHAfR:21H . ::\:
::::
... :.;
. .;.:
. . ::
. . >1 . ;Af9:
.....
"........

.0

cv

Figure. 4·~ CVAi¥ 78711 Cat.hed Map Regj?ter Format

Table 10· CVAX 78711 Cached Map Register Description
Bit

Description

33

CV (CAM valid}-When set, this bit indica\es that the CMR contains a valid copy of a
map register, and mapping is enabl~d for the page in Q22-bus addres~ space. When
cleared, it indicates that the contents' of the CMR are not valid and mapping is disabled.
The CQBIC must update the cache from the scatter and gather map to determine if
mapping is enabled for the Q22-bus.adc:lress to belJ,lllpped..

32:20

Q22-BUS ADR 21:09 (Q22-bus address 21:09)-This field contains the address of the
page in Q22-bus address space mapped by the map register address bits stored in bits
19:00 of this register.

19:00

A28-A09 (Address hits 28:09)-Thisfiekfcontains the address of the page in local
memory that the associated Q22-bus address is mapped to.

Map Base register-This longword accessible register is located at physical address 2008 0010
(hexadecimal) and contains the startinga~~s of the scat~r .aQ~ gather map in local memory. This
address. must be locatedqn an aligned 8 K loagwordblockofl~lllmemory. The system boot PROM
must indicate when this block of memory is una\lailable. Th~ onlY.acc;ef>s to the scatter and gather
map should be through the CQBlC. A write operjll;ion to daemap base registe.t clears all the CAM
valid bits in the CMR. This removes the cached copy of the map registers when changing the
location of the scatter and gather map in local memory. The format of the map base register is
shown in Figure 5 and is described in Table 11.

31

2928

1514

00

I:< I:::: ~~P~fEi\ : : : : I:::::::a: : : : : : , I
Figure 5 • CVAX 78711 Map Base Register Format

Confidential.and Proprietary

2-69

~DIIIID

Preliminary
Table 11 • drAX 78711 Map Base Register nescription
.'!

. . '

' . " . ' "

'

"

-,

"

Bit

Description

31:29

Notused.Read as zeros.

28:15

MAP BASE (Map base address)-These bits are used as physicala,ddress bits 28:15 when
the CQBIC accesses the scatter and gather map. Bits 14:02 of the map register address are
used as physical address bits 14:02. Bits 01:00 are zeros.

14:00

Not

Readas zeros.

System Configuration Register (SCR)....l..The system configuration is used by the CVAX 78034 CPU
to configure the operation of the CQBIe. This register controls the doorbell register offset address,
the enabling and disabling of theQ22-bus BHALT signaland the Pov.ier OK (POK) and AUX flag.
The SCR is located at CVAX physical address 2008 0000 (hexadecimal). The format of this register
is shown in Figure 6 and described in Table 12. The SCR is cleared during the powerup sequence or
when the SYSRESET signal is asserted. This register is not affected by a processor programmed
reset.
31

16151413

111009

04113

DOORBElL
OFFSET
BHALT ENS

Figure 6· CVAX 78711 System· Conliguratio~Register Fomtat

Table U· CVAX 78711 System Configuration Register Description
Bit

Description

31:16

. Not used. Read as zeros.

15

POK (Power OK)-This is a read-only bit that indicates the the state of the BPOK signal
on the Q22-bus. It is synchronized and latched at each assertion of the AS signal on the
CVAX bus and is set to indicate that thepowet is OK and normal operation is poSsible. 1fi5
cleared to indicate that the power supply has failed or that the supply voltage is below
.normaL

14BHALT ENB (BHALT Enable)-This read/write bit is used to enable th~ tra~sfer~f
BHALT signal from the Q22-bus to the HALTIN output of the CQBle. When set, the
state of BHALT is transferred to HALTIN. When cleared, BHALT has no effect on the
BALTIN output.

13:11
10

2-70

Not used. Read aszcros.
AUX (Auxiliary mode)-This read-only bit)ndicatesthe statepf tbeAU~ input to the
CQBIC and the operating mode of the CQBIC. When set, the AUX input is asserted and
auxiliary mode is selected. WhencIeared; the AUX input isnega'ted and arbiter mode is
selected.

Confidential and Proprietary

Preliminary
Bit

Description

09;04"

Not usetL Read as zeros.

03:01

Doorbe~- These t zeros, .

Auk Hd (Auxiliary halt)-This read/write bit is used when the CQBlC is in auxiliary
mode. It is typically set by the arbiter CPU and cau~es the HALTIN output of the CQBJC
to be asserted. This bit is cleared by writing a 0 to it or by the assertion of the RINIT
output. The BHALT enable bit 14 of the system configuration register has no effect on
this bit. When the CQBIC is in arbiter mode, this bit is read-only and is read as O.
---_.
07
Not used. Read as O.
08

06

DBI IE (Doorbell interrupt enable)-This bit is sedoenable interprocessor doorbell
interrupt requests through the DBR bit 00. It is cleared to disable interprocessor doorbell
interrupt requests. It is a read/write bit when the CQBle .is Q22-bus master and a readonJy bit when another device or CPU is Q22-bus master. It is cleared by theRINIT output.

05

LM EAE (Local memory external access enable)-This bit is set to enable access to local
memory from the Q22-bus. This bit is cleared to disable access to local memory from the
Q22-bus. It is a read/write bit when the CQBIC is Q22-bus master and a read-only bit
when another device or CPU is Q22-bus master. It is cleared by the assertion of the
RINiT output when the CQBlC is in auxiliary mode and by the assertion of the
SYSRESET signal when the CQBIC is in arbiter mode.

04:01

Not used. Read as zeros.

00

DBI RQ (Doorbell interrupt request)-The function of this bit is enabled and disabled by
bit 06 (DBI IE) of this register. WhenDBI IE is set, writing a 1 to DBI RQ causes the
CQBICto iassert the IRQO output to post an interruptrequest to the localptocessor. When
DB lIE is cleared, the CQBIC holds DBI RQ dearedand writing a 1 to this bit has no
effect. Writing a 0 to this bit never has an eHect. Ids cleared by an IPL 14 interrupt
acknowledge cycle to the CQBIC or by the assertion of the RINIT output.

2- 74

Confidential and Proprietary'

Preliminary
Scatter and Gather Map Operation
The CQBlC uses a.scatter and gather. map to.store Q22-bus addresses into local memory. The map
consists of 8192 mapping registers stored externally in local memory, a map base register record
the location of the external map registers, and a 16-entry cache containing the moS.t recently used
map registers. Each map register selects a 512 byte page of Q22-bus address space in local memory.
The map enabled or disabled by the W EAj;\ bit 05 in the doorbell register of the CQBlC. All
mapping is performed from the internalca~he of map registers. Therefore, if th~re9uired map
register is not present inthe cache, theCQtnC updatest~~ cache with the~quiredmap register
from local memory ~nd then continues the mapping oper~t~n.TIlrough the use of a valid bit
each register, the software can selectively' enable and disable d:ie mapping of seI~1:ed pa~es in Q22~
bus address space.
. .
",'

to

is

it:i

The CQBlC morutorseach Q22-buscyde and responds if the LM EAEbit 05in·~h~. doorbell
register is set or if the Valid bit 31 of th~ selected mapping resIster is se~ . c 1,.M,EAE bit is ignored
for a local miss or hit transaction. Only map registers ,that have th(;':ir valid bit set are stored in the
CQBIC cache.
.
.

Th

DUring read operations, the mappingn;gistermust map th~iQ;Z2-h\ls add~ss into an !-:Jdstinglocru

memory, or a bus tilneout will occur.Duringwrite op~rations, theCQBIC asserts theBR}?LY signlll
tothe Q22-bus before checking for 10ca1meIBoryan~ abu~timeout does not occur.'
Figure 11 shows the translation from a Q22-bl;l!; addreSlJ! to a local memory address. The sequence is

1. Bits 21:09 of the Q22"btlS address are extracted and used to select the map register.
2. The rnap register is selected and its V bit 31 is checked. If the Vbit is not set, the operation
terminates.

3. Map register bits 19:00 are used for bits 28:09 of .the ~ocalmemory physical address and bits
. 08:00 of the Q22-busaddress are usedfofbits 08:00 of the'local memory physiCal address.

21

00

0900

EXTRACT TO SELECT
MAP REGISTER

3130

00

2019

28

I : :: :

0908

::pr++l:A~~+s;o~Lf~+~++:

00

::: :: :1

Figure 11 • CVAX 7871l Q22-Bus toLocal Memory Address Mapping

Confidential and Proprietary

2·75

mamll!D·

Preliminary

Operation Modes
The CQBIC operates in arbiter or auxiliary mode as.selected by the AUX input. When AUK IS
negated, arbiter mode is selected. When it is asserted, auxiliary mode is selected.
Arbiter mode-During this mode, the CQBIC is the Q22-bus arbiter and controls the Q22-bu~
DMA arbitration, powerup and powerdown and reset protocols, ana powerfail and restart
detection. It also supports the no-grant timeouts and Do-sack bus grant aborts.
Auxiliary mode-During this mode, the CQBIC is a Q22-bus auxiliary device and controls the
powerup and powerdown and reset protocols, and the powerfail and restart detection. It also
s,upports Q22-bus request and mastership protocols, the DMA and IAK daisychain functions, and
the nonexistent Q22-bus memory timeouts.
Retry Handling
The CQBIC requests a retry that causes the CVAX to release ownership of the CVAX bus and to
retry the current transaction. This allows the CQBIC to obtain bus ownership and to perform a
transaction such as fetching a map register from local memory or handling a bus deadlock.
The CQBIC detects a retry request when the ERR or RDY signal is asserted. The SYSERR and
SYSRDY signals are synchronized by the CVAX clock and become the RDY and ERR inputs to the
CVAX CPt). The CVAX cPu uses two sampling windows to detect an error.or a retry request. When
ERR is asserted in the first sampling window, the CVAX CPU waits for the second sampling
window. If RDYis asserted in the second window, theCVAX CPU retries the transaction and if RDY
is not asserted in the second sampling window, the CVAX CPU detects an error. The CQBIC
requests a retry by assertin,g SYSERR, waiting 50 nanoseconds, and then asserting SYSRDY. The 50
nanosecond delay ensures that the CVAX clock chip synchronizer does not skew the SYSRDY signal
so that the retry request is not detected by the CVAX CPU.
Any CQBIC master transaction that is deadlocked because the CQBIC slave controller needs eVAX
bus ownership results in the CQBIC issuing a retry request to the CVAX CPU. These transactions are

• A master read transaction to the Q22-bus.
• A master read or read-lock transaction to the scatter and gather map when the map register is not
in the CMAP.
• A master write transaction to the Q22-bus, system configuration register, DMA system error
register, or map base register.
• A master read-lock transaction to local memory, Q22-bus, or internal registers.
• A local-miss or global-hit transaction.
• A eVAX interrupt acknowledge transaction.
A retry is used for all read-lock transactions to local memory or to the CQBIc:. During a read-lock
transaction until the CQBIC becomes Q22-bus master, each eVAX CPU transaction is retried. This
prevents a Q22-bus device from breaking the lock via the slave controller of the CQBle. If the
CQBIC does not receive a no-grant timeout while attempting to gain Q22-bus mastership, it asserts
the SYSERR signal instead of attemptihg retry transaction. The CQBIC retains Q22-bus mastership after the completion of the read-lock transaction and until the next eVAX bus write-unlock
transaction or other CQBlC transactions. This prevents the CQBIC from holding the eVAX bus if
the CVAX CPU does not recognize the read-lock transaction find does not complete the writeunlock.

2-76

Confidential and Proprietary

Intettupt Handling
The function of the CQBIC during an interrupt request depends on its mode. In arbiter mode, the
CQBle provides the irt~rfa€e between the CVAXinterrupt system and theQ22-bus. In auxiliary
mode the CQBICrespooos as an auxiliary deVice on the Q22-bus and as a devire on the CVAX bus.
It blocks interrupt acknowledge cycles from the Q22-bus.
The CQBlC is pladedafthe end of the daisychairironfiguratlon for all four interrupt priority levels
used by. the· CVAXCPU. This is necessary s() th~t whenrt6othet~evke otfthe~VAX bus has
requested an interrupt and when the CQBlCihasooolitstandmg mterrupts: it ·ttanSfersthe
assertion ofIAKI signal to theQ2i-bus otblock~ it andll!>serts rhe'm signal.

Arbiter mocfe-During arbiter mode, the CQBtc ,transtersQ1~"t)us interrul't requests directly to
thelocal procesSor by' mapping ,the. Q22-btlsititerrupt~qu~t on the' rn~Q <1:4>. fines, to the
mQ < .3:0 > inputs of the loc~:l processor. ·The. CVAX respOnds to anjilterruptteqtlest onthe~eli~s
with an interrupt acknowledge cycle. The CQBlC can' alsofe1uest an interrupt by asserting the
MEMERRsignaland/or thePWRFL signali; TheCVAX·dcieSriotrespond tOMBMERRbr PW1'iFL
intetrupt requests with an interrltpt acknowledgeeyde.

",

The CQBIC responds to a CVAX CPU interrupt acknowledge cycle when the IAKI input is asserted.
The response is ·determined by' the·i1Pt .ackn6wledged·andif· theCQBICihas ianyoutstanditig
interrupts as follows:
.
• For an interruptacknowledgeatWL 17,IPL 16,'orIPL l),theCQBICitrltiates aQ22·bus TAK
transaction. Wh~n the q)BlC receiy~s.the ~t<)r.fJ:Qm.the int;etTllPt;it1!}Aevice on,J:heq~f-btlS,
it appends bits 9 and 0 to the yector, and pas~es the v;ectpF ~Q.~helocaI prot;;essq~ Both bits.9.jU1d 0
of the vector are set to force the vector address into ufiallocateddevice vector space (> 200
hexadecirnal)andfotte tneprocessors tn.t'~u:pt prior1Wl~ WIPL n,
• For· an inter1!Uptacknowledgecyd~at IP;L 14' \Vhetl, thFC.Q~~C. ~ ",~~rbtli m~\lptrequest
pending, theCQBIC responds by returning vector 204 (htOOidecimal}to theCVAX CPU and by
asserting the.RDY outP"!. When no qQQvbellinterruptr«l~llt ispend\.og, tlieCQ,Bl.c Wtiate$.a
Q22-bus interrupt ~wknowledge tran~etiQn; ,This, tJ:mlsa;ction is processed. the same. as an
interrupt acknowle4ge cycle at 11?i" 17,.IPL 16;,01: IPL 15.

Auxiliary mode-During auxiliary mode, the . CQBle bloc\s intermptacknowledgecycles .jn
response toIPL17, IPL16, land IPL 15£tbmbeingtht~e~ tothe.Q22:b~s:tn~cCQ~IC
processes interrupt requests from its doorbell regist~randtan ~lS~'reque~fan in~rupt by asserting
the MEMERR and/or .i.'I'WitFL signaL 'The· CVAXdoeS ubi- respond·
interrupt request with al1ihterrupt ackn0\.rJedge cycle.

to a MEMERR or mFL

The r;esponse ohhe CQBlC toa CVJ\4 CPQ interFupta.:knowledge cycle when its IAKiinput is
asserted ~s deterrnine<;lby .~he IPL acknowledged .and if out$~t1dingintenllptsare pending as
follows:
.
-Fot an interrupt aclwowledg~ cydefl.! IJ?L .17, IPL 16, or I,I.>L Ifl, the·CQBIC blocks the cyde from
the Q22-hus and asserts the SYSERR output to end the cycle.
• Foran intyrrupt acknowledg~ cyd~ at IPL 14 when theCQBIC has, a doorbell interruptre~uest
pending, the CQBIC responds qy ~turning vector 404 (hexadecimal) to the CVAX CPU and by
asserting the RDyoutput. When 00 doorbell inten-upt request is pending, the CQBIC blocks the
cycle from the QZ2-hus and asserts the $YSERR sig~al to end the cycle. When SYSEI\R
terminates the cycle, the CVAXCPUignores the interruptiequest llnd does not take an exception
to the termination.

Confidential and Proprietary

2-77

Preliminary
Error Handling
. Thecl.~&SeS Qferrors detected and. reported bytheGQBIC art;~.nonexistentQ22-busmefiK}ry arid
IjOreferences, nonexilltc)lt lQ<;fiJ memory ,rererences; no-grant timeout,no-sl;l,Ck,.;:lbort,. ,slave
memory error,reporti,p.g, master parity error detection, ,and locahnissand global-hit nonexistent
memory and memory errors. These are grou~d into errors processed by the.master section of the
global-hit errors,
andCQBIC arbiter errors.
CQBIC, the slave section of the CQBIC, local-miss and
':
"

"

'

,

'

'

"

"

TPeCQBICreports. errors and error status to the CVIIX CPU using the following signals and
registers: SYSERR, MEMERR; PWRFL, the DMA System Error Register (DSER). Master Error
Address Register (MEAR,)i,andSlave Error Address Register (SEAR). The assertionoftheSYSERR
signal causes the CPU to termiqate the current transaction and to take a machine check for, errors
il.1.atoccur onde~and read ,and wdtetransiictions. When reporting an error to the CVAXCPU by
. as.serting'SYSERR, thec::QBIC sets CDAL<31:00> to valid logic levels. The assertion of the
MEMERR and PWRFLsigl~als are recognizf;d asit;lterrupt requests by the CVAX CPU.
All parity and memory error flags and error addresses are latched and hetd until cleared by the
CVAX CPU. Additional parity or memory errors that occur will set the Lost Error bit·03 in .the
qSER .
.,Mastel section errots- The CQBIC processes nonexistej1t memory errors as follows:
• During demand read transactions, the CQBIC asserts the SYSERR signal to terminate the
transaction, sets the N:x:M flag bit07 in the DSER, and latches the address in the MEAR.
• During a request read or interrupt acknowledge transaction, the cejBIc asserts the SYSERR
.' signal to terrIDn'ate the transaction and no error Information is logged.
.
i

• During a write transaction, the CQBIC sets the NXM flag bit 07 in the DSER and asserts the
MEMERR signal to post a write timeout interrupt request. MEMERR is asserted with the next
. assertion of theAS signal lind deasse~ted with the next ~sserdon oftheDS signal.
Multiplelongword tl'jlnsfer to Q22"bus-If the CVAX CPU attempts to Petforma multiple
longword transfer to the Q22-bus, the CQBIC asserts SYSERR to terminate the transaction.
Because the Q22-bus address space is located in the I/O-space of the CPU,onlylongword transfers
with byte masks to this space are legal.
No-grant timeo~t_If the CVAX CPU ~ttempts to obtain Q22-bus mastership anddoes not succeed
within 10 milliseconds, the CQBIC ternlinates the transaction by asserting SYSERR. If ~he
trarls~tion
a demand read, the No Grant 'Timeout bitOiis set in theDSER.
.
,
,
,
'

is

"

'

" , : " ,

,

Master parity error-The CQBIC processes :master parity errors as follows:
'. During a demand read transaction from the Q22-bus, the tQBIC asSerts SYSERRfoterminate
the transaction, sets the Master Patity Error bit 05 in the DSER, and latches the address in the
MEAR.
• During a request read transaction, the CQBICasserts SYSERR to terminate the transaction and
no error information is logged.
Sillvese&on errors-A slave read or write transac1:ion thatresuIts ina bonexistent memory error
causes the CQBIC to set the SLAVE DMA NXM flag bit 00 in the OSER~ latch the error address in
the SEAR, and assert MEMERR to post an interrupt to the GVAX CPU.
'. '.
Aslave reado~ write traps;lctiqn tha~ results in an error with theth~ SYSERR signal asserted is as
foU~wS:

2-78

,.,.,

..

. .....

."

Confidential and Proprietary

...

• A slave read transaction thafl;e.sults in a parity error causes the CQBlC to set the DMA QME bit
15 in the dporbcll register, set Slave Memory Error bit 04 in the DSER, and latch the translated
error address into the SEAR: The CQBIC then reports the error to the Q22-bus by asserting
BDAL < 17~16 > during the data transferof the transaction.
• A slave write transaction that results inarretror.causes the CQBlC to set theDMA QME bit 15 in
the doorbell register and tl:).e 8.1avt!Mel11()fyEi"f()r pit 04.1n the DSER, latch t~ translated.error
address in the SEAR and~ssertMEMERR·topostan interrupt to the CVAX,CPU. The CQBIC
does not inform the Q22-bllsiof the error.......
.

..

• A slave read or write transacti9!l to.the.scatter and gather map. that resultsij1an error causes the
CQBlC to set the Slave Memory Error bit 04 in the DSER,hm:h the ttll.tlslated error address in~o
the SEAR, ,and assert MEME1:{I{ topPsf ~n.ihterrllpttoOtheCYAXCPU.

LocaJ·miss and global.b:itert'()tS~Durin81pcat·rnis~ ~n~glt>bal-rutreadtral1s11ction, the CQBIC
issues a retry request to the CPU by asser~ing SY~ERR~~.,;SYSRDY a~d latch~s the mapped
address. The CQBIC performs !ilread transaction from lo~~mory an4stoJ;e$ the data. When tlie
tlledata. If an ertor\Vas'detec~ during the read transfer from
CPU tries again, the CQBlC
local memory, the c::;QBIC I-\ssetts SYSE~Rito riotify the CPU of the ~rr~r, latchestheaCldress ihthe
SEAR, and if the transaction is a demand re~i it set~;t~~ Slave Memory Error bit 04 or Slave DMA
,.
NXM bit 00 in the D S E R . ' · .\ !

retprns

During local-miss and global-hit write transactions, the CQBlC l~tches the address and write data
and asserts SYSRDY. The CQBI<;: performs a write transact101Howtlte to local memory. If an error
occurs during the transfer to local memory, theCQ~JC.tatches the addressiiito the SEAR, sets the
slave memory error bit 04, or Slave DMA NXM bit 00 in the DSER, and asserts the MEMERR
signal to post an interrupt to the CPU.
<

Arbiter enors- When the CQBICarbiter g ts the,Q2~-bus by asserting the BDMGO signal and
does not receive the assertion of nSACKwitruri '1'0 iniCrbsecbh-cls', removes the grant and no errors
are reported. The arbiter waits 500 nanoseconds for the BDMGO daisychain to clear before
beginning arbitration again.

rru1

it

Initialization
.
. . ..,
When the IORESET input is asserted, the CQBIC asserts the DMR and BDMR outputs
gain
, ownership of both buses' befofe·the ilSOOl'tiot/' bfe:nyre~t; sighals; OtlcetheCQBId'hilsl!ken
grantedownershlp ofbbth'bllses(DMG~n64U!)MGI~~erred'f,:$t8SSertSlth~:RimT-dutpuPkiJ; 'I0
microseconds. The assertion of RINIT can be used to clear local devicesorregistet..s/focll.fi.infeffilPt
enable bits, and pending local interrupts. The d()Orbellfegis~~anj:{ PMAsySt~rp~rj:Oriregi~t\!r
reset. If the CQBlC isQ22-bus arbiter, it assertsBlNIT foramirrimumoflOmicroseco~dstodear
the Q22-bus. If the CQBIC is in auxiliary mooe,BINIT is 'riot· asserted. ·After·'ll'} micro§e't6Ads,
RINIT and BINIT are deasserted and are followed by' theoeasserdofl of DMR and BDMR:The
system is now initialized and normal system operation can follow.

to

are

The response of the CQBle to tb.efl;ss.<::rtiQn ofBINrr.on:,the'Q2,2,chus isllietel'min'edby hs !11(Iooe 1of
operation. In arbiter mode, the assertion of BfN1'f is ignored and in auxiliary mode the assertion of
BINIT causes the CQBIC to assert RINIT and SYSRESET to reset the local processor. The RINIT,
DMR, and BDMR signals are asserted when IORESET is asserted.
Dutlngpowerup,the CQBIC sets the CVAXb«s and QQQ45Us lines toa higlHcipectance .

. Interfacing Requirements
Figure 12 shows a CVAX CPU system using the CQBle a~~arHnterf&ce to the Q22-blls,
Confidential and Proprietary

;£679

"liD·

Preliminary
,.

AND

>

eVA)( 18'134
FPA

T~40M

, AuX
.sYS'RESET

CVAX"7871 ,

. QBIC

1miif'
1M)

iORESEr

sse

CPU

::=

lAKEd

./M,,,QVAX
78332

ColA'/.. 78034

.~

IORESET
HAlliN

,HALTIN

OMR
DMG

OMR

5MG
lRO<3:0>

IRil<3:0>

PWRFi:

PVVRfL

MEMERR

MEMERh
CCTL

CCTl
DAL<31:00>

CDAl<:;31:00>

Q·22 .BUS

F.

AS

As

os

Os
WR

WR

~

BM'<3:O>

ROY
ERR

~

~ RDY
-,"-VAX 78135 CLOCK
5YSADY

__

ERR

I

~

F

SYSR,DY
SYSER~

.

..,....,.,.
...

I~

CSDP~.2:0~

8~r<3~·O>

lffi

~

M

v

MEMORY CONTROllER

NcaBICR

~
A

cl 15
CVAX 765'88

N"UiA

I~ If~ 18 I~ I~

!

D

ITO LOCAL MEMORY,

Figure 12 • CVAX 78711 System Interconnect Diagram

• Specifications
The mt!chanical, electrical, and environmental characteristics and specifications for the (:QBIC are
described in the followingpaxagraphs. The test conditions for the electrical values are as follows
unless specified otherwise.
• Ambient temperature (TAl:

ooe to 70°C

• Power supply.voltage (Vnn): 4,75 V to 5.25 V
Mechanical Configuration
The physical'dimensions of the CVAX 78711 I32-pin cerquad package are contained in the
Appendix.
.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the dwice.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device .
• Storage temperature (Ts): -55°C to 125°C

2-80

Confidential and Proprietary

&eliminary

• Power supply voltage (Vnn): -0.5 V to 7.0 V
• Input or output voltage applied: -0.5 V to Vnn + 0.5 V
dc Electrical Characteristics
The dc electrical characteristics for the CQBlC are grouped into Q22-bus signals and CVAX bl1s and
CQBIC specific signals. Table 18 lists the electrical specifications for the Q22-bus signals and Thble
19 lists the electrical specifications for the CVAX bus and CQBIG specific signals. The specifications for the dc tests are
• Power dissipation:

<

1.5 watts

• Minimum airflow: 100 linear ft/min

• Power supply voltage (VDn): 4.75 V (except where noted)
• Ground (Vss ): 0 V

Table 18- CVAX 78711 Q22"bus de Parameters
Symbol

Parameter

V IH

Uruts

Requirements

Max.

Min.
High-level input voltage

V

1.9
1.72

Test
Conditions

Vi. =5.25 V

V

v.. =4.75 V

V
V

Vin =5.25 V
Vin=4.75 V .

V

L..=100 rnA .

VfL

Low-level input voltage

VOLD

Low-level output voltage
(open drain)

0.9

IlL

Input leakage cur~nt

-10

10

ilA

0< Vi. <5.25 V

IOL

Output leakage current

-50

50

~

·0 <:: Vin < 5.25 V

Cm

Input capacitance

10

pF

Caul

Output capacitance .

10

pF

1.66
1.5

Table 19 • CVAX 78711 CQBIC and CVAX Bus de Parameters

Symbol

Requirements

Parameter

Min.
VII<

High-level inpuf volta.ge

VIL

Low-level input voltage

Max.

Uruts

Test
Conditions

V
0.8

Confidential and Pro prjeU1IY

V
2-81

_ . _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~ _ _ _ _ _ _ _ _ _.flIlMiP'I'_'!i11

,auIlD·!

CVAX7&ru

Preliminary .•

Symbol

Pmmeter

Requirements
Min.
Max.

Units

Test
Conditions

VOH

High-level output voltage

2,4

V

I oH = -400 fJA

VOL

Low-level output voltage

0,4

V

IOL=2.0 rnA

\T9 LD

Low-level output voltage
(open drain)

0.2

V

IoL ",,20 rnA

V

IOH=-lOO!lA .

02

V

I oL = 1.0 rnA

High-level output voltage
(MOS signal)

3.0

VOLM

Low-level output voltage
(MOS signal)

IlL

Input leakage current

-10

10

tJA

0< Vin < 5.25 V

Input leakage current
(sus truner)

0.2

1.5

rnA

V'n=OA V

IoL

Output leakage current

-10

10

tJA

0< Vin < 5.25 V

Ioo

Active supply current

220

rnA

10.. =0, TA=O°C

7.0

pF

IlLS

Cin

. Input capacitance

C ••,

Output capacita~ce

10

pF

C'o

13idir~ctiona1capaci tance

20

pF

ac ElectticaI C~cteristics
. The Q22-bus ac charateristics are measured under the following test conditions except where
noted.
• Ambienttemperature(TA): 70°C
• Power supply voltage (Vo!)): 4.75 V
• Capadtiveloaci (C l ) : 15pF/330 pF
~

Pullupresistor (Rl): 910

• Pulldown resistor (R2): 200n

• V••,:L60 V

• ~H:

L72V

• Input rise and fall.JilTl~: lQ ns (l.2to2.2 V), (O.S to,2.6 V)
The following not¢,l$ ,app! y to .Figures 13 through 53 and their associated timing Tables 2() through 27.

'1\11 timesdhiln,'nanoseconds e.xcept where noted.
• The TB

Figure 26· CVAX 78711 DMA Grant In/Out Daisycbain (Auxiliary Mode) Timing

Table 23 • CVAX 78711 CVAX Bus to CQBIC Timing Parameters
Symbol

Definition

Requirements (ns)
Min.
Max.

tOOALHZ

DAt high-impedance delay

0

20

tOERRA

SYSERR assertion delay

0

.35

tDERRN

SYSERR deassertion delay

0

10

tDHz

DAt high-impedance delay

0

40

tOMEA

MEMERR assertion delay

{)

45

tDMEN

MEMERR deassertion delay

0

115

tD~QnA

NCQBICR assertion delay

0

40

tDNQlIN

NCQBICR deassertion delay

0

60

tDRDAT

Read data valid delay time

0

40

tORIlYA

SYSRDY assertion delay

0

35

t pRDYN

SYSRDY deassertion delay

0

10

tDwDAT

Write data valid delay time

0

20

tHAIlK

Address hold time

11

Confidential and Proprietary

2-89

~DmDD9 .

CVAX'78711

Preliminary

Symbol

Definition

Requirements (ns)
Min.
Max.

tllBM

BMhold time

5.0

tiles

CS hold time

11

tHlAKI

IAKI hold time

o

tflRf}AT

Read data hold time

5.0

tIlWf}AT

Write data hold time

11

t HwR

WRhold time

5.0

t IAs

AS deassertion to assertion

45

t IDS

DS deassertion to assertion

100

tSADR

Address setup time

22

t SAS

AS setup time

26

tSBM

BM setup time

2.0

tses

CS setup time

22

tsos

DS setup time

20

tSIAKI

IAKI setup time

17

tSWR

WR setup time

22

C[)Al<31 ;00>

CSDP<2,0>

--"",j~~~,r-r-------~--------~~--~--~----~~:~----~------------------

~<:~~~~~~~::~~---~~--~-----r------~r---'--r---------1r\----~~----------------

1

'J.i.-tDRDYrIt

~------~--~---------+--------~~--~--~r-----~r-----~)~-------------tOADYA

ClKOUT

Figure 27· CVAX 78711 CPU to CQBIC Read Cycle (System Ready) Timing

2-90

Confidential and Ptoprietary

.....

Preli.mnary

COAl<31;OO>

CVAX787U
~{

~

l-----,--~':~T~-----

(ADDRESS LATCHED BY COBIC)

.

-t----{<===

-\'~,
BM<3.0>

--~~~--~r-r--------L------\l------------------1\r\----~-----------------­

--~,r~f~------~--~~--\r------~--~-1\r\---,---------------

WR ~-~+-f---+-------~~--~----4l-~------------~I~\----~------------~----~-~--------r---------4r--~----------~\r\-----T---------------------

""'ERR

-----+-----1-------1-------\\.

\

•

.~

/j

'J.- tOFRFiN

.:...~~------------

) ...

..

~'~

ClKOUT

Figure 28· CVAX 78711 CPU to CQBIC Read Cycle (System Error) Timing

CDAL<3i"OO">

J.

ADDRESS

jc tHADR---1

-J

ti·l
i4-

I 'SA""

I

-----~~
'ODAlHl

1

\

~1

t.-

IADDRESSlATCHEOeYCUBlC1

8':

~\

)\-\---:--j

'OROAT

,IHADAr'--------

'OKZ

AS

CSDP<2.0>

.MZi~

--~T-~--'r~-------+-------\l-------------_1\r\--~----------------\\-\___-,_________________

''\
',I

wR-2----+-r--~----~--~--------I~-------------~r---~------------------

II

II

I

l

rtDERAN

f

~ t

r-1DRD'fN

~-----~----+-------+--------~r-----+------~
tSAS-..!

CLKOUT

Figure 29· CVAX 78711 CPU to CQBIC Read Cycle (Retry) Timing

Confidential and Proprietary
> _ _

~~_.

_ _ _ • _ _ _ ,_ _ _ _ _

~~~_~~~_~.~.~_~_"

2-91

-----------_<11'»1'_---

__ .....,. _ _ _ _ _ _ _ _ _ _ _ _ _ _

_~

Preliminary
ADDRESS

~HAOR
~

'
:

CVAX78711
II

WRITEOATA
X~---------'---....:.;:.=;~~----4i
--~.,---~f-lHWDAT

1_,

\-1

tOWDAT

~~~----~\'~,~i~i_----"_AS-1_~\

r----'os-----J

r-~~~rL-~4~~------------------------------~~\~\rl~~~~:~~=X~---------­

I

~ --~~--~-i~~---_4I__--------------------__1\I_\-----L---------------------

.r--L----~~----------------~::~---J------------------.J

WR -+----+-+---T-----~I__--------------------__4II_'___,-_____________________
SYSriDY
SYSERA

, 'DRDYN
'DERRN'

----+----+----~\----...,

r--

------11----'---'1

CLKOUT

Figure 30· CVAX 78711 CPU to CQBIC

COAL <31.00>

11'--==:'-:'---

WRlTf DATA

Wiite Cycle Timing

jl,
I)

-.

"

1,(,

WR

.r--J----~1_-----------------4\1_\

____- L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

~---+~--~----41_-----------------4\\1----~-------------------

f

;;:;s;my

---+----+----1,

~
_

: 1'OERRNj

\
i-- 'OERRA

II.-

1

\,

IDRDYN

r--

/r--------------

~~I-'--~

CLKOU1

Figure 31· CVAX 78711 CPU to CQBIC Write Cycle (Retry) Timing

2-92

Confidential and Proprietary

_.

CVAX78711

Preliminary

CQAl<31:00>

"iARi

--,,.--+---+----\
'ORO'"

I

SYSRriY

CIKOOT~~

'

I ···1

1-:=_ _ __

....

'~---~r_----"

Figure 32· CVAX 78711 CPU to CQBIC IAK Cycle Timing

',\

}~
~"AS

AS

.

os

=t:

~

BM<3:O'>

llOS

}-

(

I·

WR

SYSEAli
i

~

SvSROY

: .~

rf

tOEARN

tIDR;':N

I

ClKOUT

Figure 33 • CVAX 78m CPU to Local Memory Read Lock Cycle (No Q22-Bus Mastership Retry)
Timing

Confidential and Proprietary

2-93

Preliminary. i
CDAl<31;OO>

~1"-;

_--,__

~--~--~\~\----~=========

-'K
\----.r
\..---tIAS---i'------

-(

~b--_---I~f.--I Ilos_J.~-~~~~.r---------------~\---~---------------------

WR~'"_·M.~I--:1,------,---

SYsi'Rii

-+----------1<-------1: J

ClIO:OUT

Figure 34· CVAX 78711

CPU to

Local Memory Read Lock Cycle (No Grant TimeoutError) Timing

1-------------\I------"~"ASJ~---1----LI05------(11

--------~--'.~-----

L __ RDY
L .. ERR
LOMG

...

; SYNC DELAY M1NtMUM ANO MAXIMUM.

Figure 36· CVAX 7871.1 CQBIC Clock to IntemalTimitigSynchirmization

'I!lt>Ie 21 • CVAX 78711 CVAX Busl'inUrtgPitrameters

Symbol

Definition

,Requirements (ns)

Min.:,.

Max.

AS assertion width

200,,2

AS assertion to DSassertion (read)

25

.70

AS assertion to DS assertion (write)

40

70

AS assertion to NLMR assertion
t.\.sNW

AS deassertion width
AS' assertion to CCfL assertion'

40

tASNBWZ

BM < 3:0 > high-impedance delay

30

tASNNL~RN

AS deassertion toNLMR deassedion'
Address hold time

20

Address setup time

30

CCTL cydetime

445

CCTL assertion width

40

DMG assertion to AS assertion

60

DMRassertion to DMGassertion

o

DMR deassertion width

130

tOMRNGN

DMR dea~sertion to DMG deassertion

o

tOMRNZ

DMR deassertic)Q to output high-impedance

tCCTLCYC

tOMGAS

Conficlential and Proprietary

70

250

300

100'
2-95

mamaama

CVAX7S1U

Preliminary

Symbol

Defmition

Requirements (ns)

Min.

Max.

tOSAW

DS assertion width

200

tOSDW

Data setup time (write)

5.0

tOSNW

DS deassertion width (read and write)

40

tOSSERR

DS assertion to SYSERR assertion

200(0)'

tOSSRDY

DS assertion to SYSRDY assertion

200 (O)l

tDSNASN

DS deassertion to AS de assertion

30

tDSNDH

Data hold time (read)

tOSNOMRN

DS deassertion to DMR deassertion

tDSNON

Data hold time (write)

o
o
o

tOSNSERRN

DS deassertion to SYSERR deassertion

tOSNSRDYN

DS deassertion to SYSRDY deassertion

tNLMROSN

NLMR assertion to DS deassertion

tSERRO

SYSERR assertion to data delay

tSERROSN

SYSERR assertion to DS deassertion

100

tSERRSRDY

SYSERR assertion to SYSRDY assertion

10

tSRDYD

SYSRDY assertion to data delay

tSRDYDSN

SYSRDY assertion to DS deassertion

130

no

170

5.0
45

5.0

o

lValid for all CVAX bus signals driven by CQBIC duringDMA.

'500+4 (iSS to SYSERR): octaword write to LM
l200 nanoseconds is required to satisfy the minimum CCTL cycle time (tcCTLCYc). The CQBIC
operates properly with 0 nanoseconds minimum cycle time except that the CCTL cycle time is not
satisfied.
'SYSERR and SYSERR must be deasserted a minimum of 100 nanoseconds for synchronization.

COBleClK

DMR
_

~

\

I

P1

I

"2

I

['1

I

"2

I \\ I

P1

I p, I ., I

P2

I

PI

I "' I I \ I

~~
~ 1aMRNiN---=:)-

DMG,

"2

I pi I \', I

"2

I

P1

I

'2

I

P1

I

P2

I" I

---\\~,
.

\1---------1\1--\

~

Itt
j)

'
j

-.'DMRG~

DiViG----i\\

,'DMRNGN

- - - - - - - - 1 \ \.-----1

rf---

'""_-+_____

-'1"

~-IDMG AS-----,
\

----~I \

1-\

'L..-,I-\- - - - I I - - - ! - - - F
-tDMRN'Z

os ----\1 \-1-------I',\-\------'-"--'---"--1\ ~~.

Figure 37· CVAX 78711 Bus Arbitration Timing
2-96

Confidential and Proprietary

CVAX78711

Prelimimll'Y
en.,ccl..

I p, I

p',

I '2 I p, I ., I"

P2

I

P'

'2

I

"\

I PI I ., I

P1

I ., I

P1

I " I

P1

,-.

.2

1"

P2

P,

1"

I .,

-tASAW---------------oojr-_ _ _ _ _ _ _ _ _ __

-

\I
lAS DSR

1------,'---'D8 AW

i'Asos-j
CDAL<31:00>

=>--

lDSN ASN

I,

IOSN DH-'

-!ASOH

)(

ADDRESS

DATA

,
,

I

=:r-

;

STATUS

PARfTV

~

r

i

--I

!
i
i

tSRDYiSEAR! 0
~IDS SRDY(SfRR, ___ _

~SRDY

I

i

tSR.OYtSERRI DSN

tASNBVIIZ

~

---------------------------4\ r-----, ,

~-------~

BYSERR

NOTE: OUADWORD READ TIMfNG CAN BE DERIVED FROM THE TIM!NG ABOVE BY USING
lOS NA AS NE(>A.TlON TIME OF L)$.

Figure 38· CVAX 78711 CQBIC to Local Memory Read Timing

COBleC,.K

';cs

I

P,

j "

I

.2

i

PI

I " i"

P2

1\ \-\.Li_..J1L-.;..p''-l..'-,,:.'..Ji_·..:'-Li.:.p.:.'..JI...;p..:':..·J....:.P':"-ll--l'd

t=-'ASN'N=:jf....- - -

I ., 1 ., t

PI

I

--I·1

- - - - - l A S A W - - -_ _ _ _-,-,._ _ _ _

tASNBWZ1

-tASDly--+i

os

I p, I

-11"-,---.-,\;-\-----~........---I\~

~CTLw1 . II
eerl

P1

....... 11

~

t--

~~
-'CCTl\c-----------.~o!--,O-S~'-W
___ 1CCTl.c~\VC
"DSNAS"j

-------H~---_,[I--

DBl

002:

0<;3

I
'DSDW

CDAI <31 :00>

DATA;

DAfA2

8M.

aM2

DATAJ

;

8M3

WR\!,'- r - - ' - - - - - t - I I - - f - - - + - - - - - - - ' - - - - I i - - - - - - - I ,):-~ --~-----------------------i

_____- - - - \

f------i~

~

Figure 39· CVAX 78711 CQBIC to Loca!Memory ':t7rite Timing

Confidential and Proprietary

2-97

CVAX78711

Preliminary
~P2~

__~__~-L__~~__-L_P1~I_p~2JI--4\~\__~1_P1~_P_2~I_P_'~_P'~I_P_'~P_2~I_f_"_I~P2~I_P_'~I_p_2~I~P_'~I_P2~I_P_'~

1~--__--------~----~-r'~-A-W------------------~1r---------------------­

i'O",ASN-..,

'AW

Os-----------------*--~I

,

i

II

1'-----\
laso H

I

l-

IOSN SF1DYN(SERRNf_

CDAl < 31 :00>

cs

DP<2:0>

READ LOCK

i

r--

--0

tASN

awz

I

I

WR - - - - ' ,

Il - l D S S R D V _
'SADY DSN
_ _--I
S'iSROv

I

--------------------1\ \----..11'-_ _ _-'
tSERR SROY

Figure 40· CVAX 78711 CPU Retry Timing

cosle eLK

AS

1

P2

1 PI '1 F'2

I P1

I 1'2

1 .2 I P1 1 P? 1 P1

1 P' 1

P2

1 PI

1 P2 1 PI 1

I-lAS NW - - - - - ; 1----------- 11\5 A W - - - - - - - - ,

P'

1 PI

P2

I PI

yl'--"·
. ~!_ _ _ _ __

i

r-"ASOCY'---1
I

!

tcCTL.Vv....f

~~~~==. ==-======~1C~C~rLECY~C================9--,~---------

'--------"

f--"'.5()SW-.

I--IDSNASN-·...

r----

-Ds'~-,------rt------~I

050

~------1-~L--------

!--"50 5--0

tASO H
CDAL<31:00>

-1

iI

IDS AW-<---.--!

-,

1

....

INlMR

D~;N ~

r

lDSN ON

---tlt=~A~DD~R~r5~s~=j(
X~==~Jt===:~=~OA~TA~O~~===~j-----

~---1====s~c~~~u,~,~~~--------_1L---------------_t--1i-----------

"~, -t=====~====~"M~O~~========~~----­
I

J..--..-tAS Nl.MR--_
NLMR--~------------------------~

_______________________I¥

Figure 41 • CVAX 78711 Not Local Memory Riference Timing

Confidential and Proprietary

Preliminary

CVAX 78711 ,

Table 26 • CVAX 78711 CQBIC to Q22·hus Timing Parameters

Symbol

Definition

ReqlJttements(ris)
Min.
Max.

tOBS7A

BBS 7 assertion delay

tOBS7N

BBS7 deassertion delay

tOOINA

BDIN assertion delay

o
o
o

42

tOOINN

BDIN deassertion delay

o

4'5

tOOOUN

BDOUT deassertion delay

40 •

tODOUTA

BDOUT assertion delay

tDiAKA

BIAKOassertion delay

tDlAKN

BIAKO deassertion delay

tOQDALA

BDAL data assertion delay

tOQDLN

BDAL data deassertion delay

o
o
o
o
o
o

tOSYNCA

BSYNC assertion delay

37

tOSYNN

BSYNC deassertion delay

35

tOWTBN

BWTBT de assertion delay

o

55

tOWTBTA

BWTBT assertion delay

o

52

tUQDAL

BDAL data hold time

o

tHQRDAT

BDALread data hold time

10

t HREP

BREF hold time

io

t HR P1.Y

BRPLY hold- time

1{)

tSREF

BREFsetup time

82

tSRl'LY

BRPLY setup time

57

tSQRDAT

Bi'5.A'[ read datasetup time

82

Confidential and Pr()ptietMy:

37
35

42
43
43

60
55

2-99

CVAX781n

_

~DSYNN

¥

~-~Ir·r-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_~Jr--~r---~------------------~r-----+--------------......J

tDBS7A

~IIT--------------

____________~r_------~--------------------~~------~-----------------IS":! 1-.
\~
\
ISRPLY

II

\p

'\

Figure 42· CVAX 78711 CQBIC to Q22-bus Single Transfer Read Timing

II .1 I

I

DAT

I~

I OO!NA

REFER
SINGLE
rRANSFER

~

\

I

p'

51HZ

READ CYCLE
TIME CHART

I

BWrB1

---------------IS-RP-llV~---+f._------~----I \-,--+[-IS-RP-LY'-"----'I '"--1----+--.,-R-"-Y"-________~-__I

Bili'1Y

BRI:F

-------------1\

•

tSREF-.J

~

r,t

Vl<--------II I-i.....______
1iREF

-\f, I-'I-------'CO::.--

1-\_ _ _ _ _ _ _ _ _

Figure 43· CVAX 78711 CQBIC to Q22-bus Block-mode Multiple Transfer Read Timing

2-100

Confidential and Proprietary

CVAJC18711

Preliminary

BDAl<: 21 :00>

_'-d-~_'D:::':;;S:.;'A~_..,.-~~..!.,' r'08S7A

X \ \ - - 1 - - - - - + - - \ \-_1-_ _

'L

BsS7

BWiiIT - - - _ -_ _ _ _ _-\Ir-_+_____+_-\I-_+___________

.-:, r-

'SRPlY

REFER
SINGLE

~T!1ANSFER

RtAOCYClE
tSRPLY

TIME CHART

~----+-~~~-------------

BRET

----------"""""""~t..----'S~"''-.F-J-j·.....--''''t.,."';'~'"i

R_'_'- - - - - - - - - - - - - - - - - -

Figure 44· CVAX 78711 C;QBIC to Q22-bus NonbkJck~mode Multiple Tr.ltnsferF,ead Timing

WRITE DATA

ilSYNC -1---\
tOOOUN

tg!
.'

800iJf
BEffi7.

'OBS'\A

tOWTaTA

~DVVTBN

'OWTtlN

- - - - ' - ! r - - - - \-I\
\ '\-.\' ---.,---------!fl----..".---~
\.

-wr
•

~£

t'Des",z

~ir:::::---'--------:~jy-r------I
\-'!

.\-\_ _ _ _ _ _4C-_ _ _ _

BT

, .., Ir-

'SRPlY

~

tSRPlY

BRPLY

--I',\\------I',~.
.

iiREf

----1\ - - - - - - - - - - - 1 \ \\-~~\::.::::::::::::::~ip\-.-.-r---------

-I\

L._ _ _ _ _ _ _ _ _ _ _

Ir-'---~-

1-\

Figure 45· CVAX78711 CQBIC to Q22-bus Single Transfer Write Timing

For Inu:rnllll,Jse Only
."_"'...._ $UW_""...,,.."'."'._......R.........

__

~_~

&_fi:m~.

_ _ _ _ _ _ _ _ _ _ _ _ _ _-

________

--.----....--.--"-·~'--.--,-----------~---.-~-

2-101

Prelim~.'

i

I

\---t----+--I I---+----~~~-I

\------'-:1:-----\

:t
u

.

tSAPlV

BRPiY ---\ \-\- - - - - - - - - . . . . . . ,

"B'R'tF

L_ _ _ _ _ _--l\-_ _-'I'-_ _~4'-\,),'HREf
---\'t"
---\ \-',----------\

i

'"""

VI/RITE CYCL E

T1Mf: CHART

I

'""'"*

"'--_ _--t--IrlJ,-L------lI

"1

~~:~~E

TRANSF[R

N,1<---

II-'--~--

1\-1---

Figttre 46· CVAX 78711 CQBIC to Q22-bus Block-mode Write Timing

II

f;:).. KQljT

1--:-:-I=::-:--..l..1J---'---\ ~

BDAl<:21 :00>

I II

WR1TE JDATA (LOW

WO!RP~

,-" lt1~"
88S7

iiWiFff '

.

~ ~""'

,lJ:jWT~'=.'=A=======~~rr--'fJW-T-B'-A-\ 1---1Ir-----t-I--I\---t-----rd-----tD-W-T"-N-.--.j.J.i~~-~r,~,~E~~C~,~tEA-~AlTE
Y

----.c...)(:

1-\

I\

i

I

\ \-_.,.-_-'

..

~_,_'---;Sf1PL~P-] :)1-------

--\\--I

~l\-_ . . . . . . ~'~'_,,_.-II ~l--j'HA-"

____

-_---~

Figure 47'. CVAX 78711 CQBIC to Q22-bus NonMock Mode W,ite Timing

2-102

For Internal Use Only

Preliminary

iiiAKi5 - - - - - - - - - - ' .
iiRPlY,- --------~--:"".

Figure 48 • CVAX (~7U: CQBIc tog22.bu~IntcrrUPtAcknowkdge Timing "

Symbol

Dt;fmition,
.')

Datasetlilp time

130

tDINNRPLYN

BDIN deassertion toBRPLY deassertibfl

tDINRPLY

BDIN assertion to BRPLY assertion

30

130

tDlNRP[,YO

BDIN assertion to BRPLY assertion'

A

B

]3DIN aS$ertion ,~oBRPLY assertiqn'

.30

160

BDINassertion to BRPLY assertion}

c

D

Data hold time

25

tOOUTNON
tOOUTRPl.Y

" BDOUT assertion to ,~ass~riion '

tOOUTRPLYO

BDOUTasslfrtian t6BiIPi':YasSertionJ ,""

tOOU"fRP1Yl

BDOUT assertion to BRPLY assertion'

tDOUTNRPLYN BDOUT deass<;rtiqn to BRIlLY deassertion
t RPLYD
BRPLY assertion to valid data

"'30

no
F

505

160

30

130

o

60

BRPLY deassertiontoBDIN deassertitin

150

tRPLYDlNN

BRPLY assertion to BDIN deassertion

200

tRPLYNDN

Data hold time

o

tRPLYNOOUT

BRPLY deassertion to BDOUT assertion

150

tRPLYNSYNC

BRPLY deassertion to BSYNC assertion

300

tRPLYDOUTN

BRPLY assertion to BDOUT deassertion

150

tSYNCDlN

BSYNC assertion to BDIN assertion

25

tSYNCH

Address hold time

25
For Internal Use Only

i

30

2·103

maumD.{
Symbol

P~liminary

cvAX78m

Definition

Requirements (ns)

Min.
tSYNCS

Address setup time

75

tSYNCNW

BSYNC deas.sertion width

100

Max.

'BRPLY for the first BDIN
A = internal propagation delay (20 ns + synch of BSYNC (30 ns) + CAM check (200 ns)+ LM
access + 50 ns from first DS deassertion- tSYNCI>IN (max.)
B=internal propagation delay (40 ns)+ synch of BSYNC (80 ns)+CAM check (200ns)+EMAP
access + LM access + 80 ns from first DS deassertion - tSYNCI>IN (25 ns min.)
2BRPLY after the second BDIN and before crossing quadwordboundary
'BRPLY for the first BDIN after crossing quadword boundary
C = synch of BDIN (30 ns) + LM access + 150 ns from AS deassertion - two BDIN
D = synch or BDIN (80 ns) + LM access + 180 ns from AS deassertion - two BDIN CQBIC starts to
read LM when thirdBDlN is asserted, therefore-two BDIN
'BRPLY for the first BDOUT
E = internal propagation delay (20 ns) + synch of BSYNC (30 ns) + CAM check (200 ns)+ LM
access +150 ns from AS deassertion-tsYNCDOUT (max.)
F = internal propagation delay (40 ns) + synch of BSYNC (80 ns) + CAM check (200 ns) + EMAP
access + LM access + 180 ns from AS deassertion - tSYNCDOUT (25 ns min.)
'BRPLY after the second BDOUT
.

COBle elK

I

P'

I PI I .2 I ., I P2 I ., I P' I PI

p, I

!'~i~I_P'~I~.Pl~I_P_'~I_P'-LI_Pl~I~r-~~~

__~-L~

i
-...I

~ tDINN RPlYN

Figure 49· CVAX 78711 Q22-bus DATI to CQBIC Doorbell Register Timing

2-104

For Internal Use Only

-.
COBle elK

I ., I

PI

I

I ., I

F2

P2

I ., I

P2

I ., I "' I

\\

I

P1

.1

.2

I

I

PI

.?2

I" I

I ., J

'2

\\

I P2 I ., I !'2

J

~'smoNW

BDAl

.....

:...-.-'SYNC

s

j

I'j

to- 'SYNC H

-.,

-

C,
., P "ADA
b--

K

fiDATA

RAOO

...

DON-TCARE

-II

ASSEfmON - eYTe

DON T CARE

-:F~

.

.

-~'L

.
tRFlYDOUTN

..,'

..-

'OOUTI\t DN--

-

\
1-'1iolifN R,?lYN

v---:-;

Figure 50· CVAX 78711 Q22-bus DATa and DATOB 'roCQBIC DoorbellRegiskrTiming

COBIC elK

I

.2

I

P1

I

P2

I

P'

I P'

j .,

I '2 J p,

'2

j

.'1 "1 P'l P,; I \ \ I

'2

J

PI

j .2

!

PI! \

~

IP' I

P2

I

Figure 51 • Q22-bus DATIO, DATIOB to CQBIC Doorbell Register or Local Memory Timing

For Internal Use Only

2-105

Preliminary,
COSIC Ct~

I

P2

I

Pl

P2

I

P1

I P2 I " I 'f2

Pf

I P2 \', I p, I P1

~

., I ., I

I P1 I p, I"II I P,

P2

',\

P1

I "Ii I

P,1

I P2

I',

II

BDAl - . . J . - - - - - ' - - - - - . i r - - - " r - - \ \----r-------rll--IO-AT-A....,......,/r----'----\) \-\- - - - V--:~-,-I

-'----t

BmIT--T--------~---~-~----~I--~--~-------~---\\\-\-----------\\\-\------­

p

~--~---~r~------------r_~I----------~\'r'----ISYNeDINJ'

._lOIN RPlVO

BRPlY

ilR'EF

---------------~~c'
tRPl~DIN
NOTE: TIMING !"OR THE TERMINATION OF TRAf';SACTION IS THE SAME AS FOR DBR DATI

Figure 52· .cVAX 78711 Q22-bus DATI and DATBJ to CQBIC Local Memory Timing

COB,e eLK

j .,

I

PI

I

P2

I

P1

I

P2

I ., I "I ., I ',',

., I

.2

I

I \ \ I P1

PI

P2

I \', I

P'

1"

\', 1"

'2

I

= t - - - - - - I I I - \- - - - - 1 \ 1-\----1\ \1------\\1-\- - -

r-ISYNCS-

6DAl

~

-tsvNC H~

I--~RO=AT,,-A--:--::--'! ~ p<

RADR

~l

CONTeARE

.J.

*"

\---.,----\\ \

DON'T r.ARE

-

S

i

1\

)(}IJT

-1l--looU:" DN

,

I~

,tRtLYOOUTN
tOOUT RPLYQ

J;
~

1iJUllV - - - - - - - -_ _ _~

,-

\

~_

'I-I

\1-\- - -

~t ",' tx

'r-l-"S-SE-RT-IO-N---Bvr-.

ID(

,

\

RDATA

1'1

DONT CARE

l~l: : : : : : : : : : : : : :

:L

'1-\--

,tOQUTN

RPl.~N

tOOUT RPIYl

'RPl.VN DOUl

\

\

1iRE'F
NOTE: TIMING FOR THE TERMINATION OF TAANSACTK)N IS n-~E SAME AS FOR OBA iDATO

Figure 5,3· CVAX 78711 Q22-bus DATO, DATBO and DATOB to CQBfC Local Memory Timing

2-106

For Internal Use Only

. Fe3tufeS
• Supports VAXBl bus features of low interface cost, less than SOO-nanosecond data access' time,
and high data integrity

• High-level integration reduces module area required
• Extensive error detection
• Complete VAXBl bus arbitration, address decoding,
software protocol

and matching 10gic' to. reduce hardware and

• Single 5-vohsupply

. Description
The DC514 CMOS VAXBI Bus Interface Chip (CBIC) is a 133-pin integrated circuit that cornhines
the functionality of the VAKBI 7&74 3BCAlandVAXBI 78132BIIC withoutthe BCI bus lines. The
CBIC is the interface between. Digital's VAKBI bus aria :,l user~developed .interface of a node. It
functions as a bufferfile,performs bus trahsactiOrls, and decodes andtnatches addresses. Figure 1
is a functional block diagram of the crnc:

1--1----1 Fi~~~1<
5t-UfT
REGISTER

VAX81INTERFACE

Figure .1 • DC514 VAXBI Bus Inter/ace Chip Block Diagram
For InternalUse Only

"•..,...."'."""'' '""
. __ ____'_iillO_._q_!''l_'____._II1II.. _ _ _ _ _ _ _ _-,..,.,.....,,, _ _ _ __
"'''~

2-107

VAXBIDC5t4
The C13ICoperates with the VAXBI bus, which is a 32.bit, general purpose synchronous bus that
can he used with single a processot or multi processor systems based on the VAXprocessors or other
32-bit processors or compatible devices. The VAXBI bus has a maximum length of 1.5 meters and
connects up to 16 intelligent nodes. The combined throughput rate of the nodes is 13.3 Mbytes/
second. This document assumes the reader has an w!derstandingof. the VAXBI bus and its
operation. Refer to the VAXBI System Refererlce Manual (document number EK-VBISY-RM-OOl) for
information relating to its operation .

. Pin and Signal Description
This section describes the input and output signals and power and ground connections used by the
eRIc. The signal and pin assignments are shown in Figure 2 and summarized in Table L The
signals that communicate with the user interface through the integrated circuit interconnect bus
are prefixed with II. Signals that communicate with the VAXBI bus are prefixed with BL

13

12

10

P

BJACrO

IIP1

ilP3

11D01

!IDOl

IID05

11006

11D17

11018

IID21

11023

11010

11D11

VSS

N

II RWE;N

IIACeCi

liPa

IIP;~

IiDDO

IID04

1100:;

11016

IID19

IID22

11009

IIDI3

11014

11026

N

M

ilClKB

IICS

IIAHO

"i-,oEI-:

liIAH']

11003

GND

GND

IID20

flDOI:!

IID12

11015

IID24-

11027

M

'IBM2

IICLKA

GNO

VDn

11028

11030

L

IIBMO

118M3

GND

DRVPWR

IID/:9

IlAH6

II(JCLO

IISEL

IIBM1

IiD25

11031

IIAH4

iiSTQj.'>

BToc16

TiRM

IIAH5

IIAH3

IIAH2

~

II[STAT

118STAT

GI\lI}

BI029

ELID31

G

iTRW

IIEV4

1i£V"2

GND

BlUTa

61D30

F

IIROQ

iIEv1

IfDMAEN

8,'.024

BJD26

81D27

E

IIfv3

Bl?HASE

VDD

PIN

BlP19

81D22

BID25

IIEva

8 1NOARB

vss

BiCNTo

l.NO

Bii3

GND

GNO

BID09

Bi?i1S

OND

GREF

81D20

B'i5'i3

BITIME

BIBROKE

BiCNFi

nliO-

i':iii2

Bi501

-B1004

BIDO!;.

B!i5'Ci8

'BtDTi

8i6T3

BiDi5

BI018

Bi'521

BI8U5Y

BICNf-2

Bt1i

~ir

1lIDoo

BIDOl

81003

81006

61007

;0

61012

61DI4

81017

VREF

'3

12

"

10

G

A

KEY

Figure 2 • DC5N Pin Assignments

For Internal Use Only

J

C

'Thble 1'· nest. Ym and Signal Summary

Pin

Input/Qqtput Definition/Function

]2,Ll,K2,L2, IID<31:00>
M1,NIJ,3,M,2,.
P4,N5,f'5,M6,

Input/Output' II Data Bus-Transfers data to or from the processor bus interface.

N6,P6,P7,N7, .
M3,N2,N3,M4,
P2,P3,N4;M5,

N8,P8,P9,N9,
M9,PIO,PH,
NIO.

P12,Nll,P13, IIP<3:0>
N12

InpUt/Ou~putl II Parity-Indicates parity

K1,H3Jl,H2, lIAH<6:0>.
Hl,MlO,M12

Jnput l

II Address-Controls the selection of the CBIC
data buffer
(DBF) reais~s;

. K13,L14Jlf '. IIEM<3:Q>
K14

.Input'

II Byte Mask-Specifies which UD < 31:00 >
and lIP < 3:-0> lines contllin valid data during a
transfer:
r
."
.

the four bytes on the

lID < 31:00>"lines.

£ile

L13

IICLKA

Input l

lIClock A-Oto 10 MHz externaLclock.

M14

IICLKB

Inpue"

II Clock S:""'O to 40 MHz external clock.

M13

lIts

Input'

lIDEN

Input l

Mll

'_,c ':,' ",

S

II Chip Se1t:tt -

', __ ,_; ,,::

Initiate~dll.tp.

.tralisfers .to .or

from th~ OBt;;
,

. II Data Enable-Enables the transfer of data on
lines lrrY<.~1:00> .an?parify on lines
. lIP < 3:0 >' during II
rea 'Input"!

IlReqUest<:l!O > -ReqllestiS~ VAXBI bus transaction.

Ollrrmt'

I I Request Acknowledge-Indicates that a
requested VAXB1 bus master-pod transactionh\ls
been initiated.

lIE STAT

Output'

II Event Status-Asserted when the ESR
receives the first unmasked event code to be
generated since the register was previduslyread.

lIB STAT

Outpue

II Bus Status.....".Asserted when a. bit in the VAXBI

H12

G13

bus error register is set.'
J13

IISEL

Output'

H14

IISTOP

Output'

F13,D14,F12, IIEV<4:0>
E13,C14

Output'

n Event-Indicate that a significant event in the
CBIC or on the VAXBI bus hasoceurred.

N13

Outp\lt '

II ac Low-Asserted when the line voltage is

IIACLO

below a specified minimuml~vd.

imp~nding loss of' dc
power. Also used for initialization during
powerup ..

Tl4

IIDCLO

Output'

II de Low-Indicates an

BH.

IIBROKE

Input'

II Broke-Used during self-test to indicate a

node has failed and when to light the LED status
indicators of the node.

G 1,Fl,G2,F2, BID < 31:00> IPPl,lt/Outj:?ut' B1 Data<31:00> -Transfers data and address
information to and from the VAXBI bus and
performs arbitration.

El,E2,Dl,E3,
Cl;D2 ,B 1,C2;
. D3,B2,A2,C5,
BJ,A3,B4,A4,
. B5,A5,C6,B6,
•A6,A7,B7;B8,
A8,A9;B9,AIO
BII<3:0

Input/Output' BI Information-Transfers commands, master
. identification,read statu~, and write masks.~

All

BW.

Input/Output' B1 Parity-Indicates parity for the
BID<31:00> and BIl<3:0> lines.

C13

BINOARB

Input/Output' B1 No Arbitration-Inhibits arbitration on lines
BID < 31:00 >. Used during self-test to prevent a
node from starting until all nodes are ready.

C9,BlO,A12,

Bll

Fo!: Internal USe Only

,Pin

Signal

A14

BIBUSY

A13,B12,Cll

BICNF<2:0> Input/Output' BI Confirmation-Indicates a re~pollseto c~m-

Input/Output' BI Busy-Indicates a transactionis inprog~ss.;
mand and da.taFYdes.

P14

BIACLO

"

BI ae Low-IfMleates that the ac li~;~Itage df a
critical bqs component i~ below safe lirriit ..

Input'
;

'..

,1,,-1

(;

,e· )'

"'0,,

J,

/'-

•

a

i:·,'" -,:. Lt.:'

J,

'

~:>',:-",'_?<>

:!',

'BIde Low...,.,. I~testhat·tliedcvoltages t!!renot
·within thei:rspecifie~Lllmits;,!;. ,

1-113

Bttiminjr~PMHi'$q~are w~~e~~ifatedby a

'each

separ~tedif£erekdal,E~~ rec~"e;r~t
nOde,
tised with}be '13fpfrA~)::sighal't6 '~fne~te
VAXBlbtis'timing,"

',,;' ,,' :~..t

,','

.'. ," .,".

", '"

"

t
~ti:i L~ 'i'. ,_,\.,.%:~<, ,_." "
BIPkls~5,MfJ~,tinyng ,squat~W!'IYegelJeI'

. " , ' ", ',',

,""

c.

".,

II Parity (rn'<}:O:> , __When'data is, tta~fcirrea behVeen. the Itb~~h1aste'r'ahd ih~ Ofill, one
parity bit fpr dch byte data
nD< 3l:00 >, 'is transfer~~fo~ t1.e ~P< io > line'S . Th~i data
qytes and their assoda~ Plltity'bits a~ show.n.in Table. 2. rh' a~~ tea:d tblnsaction" the S13IC
generates and transf~rs parity, D~ring a 'data 'writ~ operation,ihe II. busm.aster generates and
,transfers the parity: These are three-statelmes.
'
" ..

at

on

For IntetJhalUse Omy

table 2· DCS14 1;I.Dat8 ~ity B~t,&signmen1:s
Data hyte

Parity hit

IID<31:24>
IID<23:16>
lID < 15:08>
lID <07.:00 >

IIP3
IIP2
IIPI
IIPO

II Address (IIAH < 6:0 > )-During II bus read or write accesses to the DBF, .the II bus master
transfers a 7-bit address on theses lines to select the register to be accessed. When accessing the
dual-octaword data buffer, this address selects the first byte of a Iongword access. The dualoctaword data buffer registers can be accessed on any even or noneven longword boundary.. A
noneven aligned access to the eighth register wraps to the first register in the dual-octaword space,
providing a ~ira.ilar a;,ddressspace. When accessing any other DBF register, only the upper five
address bits are significant. The lower two bits are assumed to be zeros.
II Byte Mask (IIBM < 3:0> l-During II bus read and write accesses to the CBIC DBF, these
inputs specify which bytes of the data lines (lID < 31:00 > rand which bits ofthe IIP < 3:0 > lines
contain valid information as listed in Table 3. In write accesses, any bytes that are not specified as
being valid will not be written. During read accesses, bytes not specified as being valid appear as
zeros on tines IID < 31:00 >, with correct parity generated on lines IIP < 3:0 >. By using the
information on the IIBM < 3:0 > and IlAH < 6:0 > lines, every byte in the DBF can be accessed.
Therefore, 8-, 16-, or 32-bit processors can be easily interfaced to the CBIC.
laMe 3 • DC514 II Byte Mask Assignments
lIBMLine*
2
1
3

L

L

L

H

II

H

H
H
L

H
L
H

L
H
H

Valid data

Valid parity

0

L
L
H
H
H

IID<31:00>
IID<07:00>
lID < 15:08>
IID<23:16>
IID<31:24>

IIP<3:0>

lIPO
IIP1
IIP2
lIP3

*L = low level, H = high level. All other binary input combinations that specify the valldity of two
or three bytes on lID < 31:00 > are allowed.
II Clock A (IICLKA)-Input clock frequency that must be provided by the user. The CBIC is fully
static, therefore the clock frequency requirement is from 0 to 10 MHz maximum. The. IICLJiCA
input generates the internal four-phase dock of the CBIC, which controls then bus it?terfac~. this
signiu is synchronous with the IICLKB input and with all II bus accesses to the CBIC .

II Clock B (IICLKB)-Aninput clock frequency of four times the frequency of IICLKA that must
be prOyidedby the user. This frequency is frorn.O to 40 MHz maximum. The HCLKB input
generates the internalfour-phase dock of the CBIC that controls the II bus interface. This signal is
synchronous with the IICLKA input and with all II bus accesses to the CBlc'.
.
II Chlp Select (IICS)-The II bus master asserts this. input to initiate the.II. bus read and write
accesses to the DBF. In addition, the IICLKA input cycle of from to to t100 immediately preceding the
assertion of this input defines the address subcyde of an II bus access. The tlOO of the address
subcycle defines the deasserting edge of an address strobe signal and latches the address and byte
mask information on lines IIAH < 6:0 > and HBM < 3:0> by the II bus master.

2-112

For Internal Use Only

-

Preliminary

..

II Data Enable (IlDEN)-The Il bus master asserts this input during IT bus read accesses to the
DBF to enable theG8lC to transfer data and parity to lines IID < 31:00> and lIP < 3:0> . During
II bus write accesses to the DBF, the input IlCLKA cycle of from 4. to tl(l& immediately preceding the
assertion of the IIDEN input, defines the data subcyde of an II bus access. The t,OD of that data
subcycle defines the de asserting edge of a data strobe, latching data and ·IYdrity values pla<;:ed on
lines IID< 31:00> and lIP < 3:0> by the II busmaster.
.
,

.

' .

'

.

II Read/Write Enable (IIRWEN)-During tlOO of an addresssubcycle, the II bus master asserts this
input to initiatean Ubus read acceSs to the DBF and deasserl:sit for il,nrI hils wtlteacc;ess.
nDMA/Map Port Enable (IIDMAEN)-Ifasserted during aVAXBI bustransactionreql.lcst to the
II bus master, the GBlCexecutes an octaworclVAXBl bus trnnsactlontd aCcess the master-port DMA
registers for the data,address, and command information'It thiSoslgr,l,1il.,js ,deas~erted d\lring a
VAXBI bus transaction request to the II bus master, the CBIC executes a IongworoVAXBlbus
transaction accessing the master-port map ~gisters data, address, ancicomm,and information.
II Increntent Enable (mNCENA1-When'::t~serted ~ptin~.~ereg\l~t"4lq t:X~cutionof a DMA
VAXBlbus transaction, this input enables apipelined increlnent of the address in the master-port
DMA address register to occur. The nextoctaword trans:ktibn lobereqllestedarldexeeutedby the
CBIC accesses theqext sequential OC!aword inVAXBI bUs·~e1,llory. Thi~op¢r:at;ion eliminates the
need for the II bus master to update the .m!lstet·portDMA'!l9~SS r,e,gistet for e.a~h.o~word
transactionof a block move operation.When.asserted duriqga mapV~BIbustransaction, this
signal performs a similar function with'the master-port map addttssregister. TheaddJ.-ess of the
next master·port map transaction is incremented by a longwo.rd instead of resulting in an octaword
increment.
II Request(IIRQ<'1:0> )-These inputs are asserted by 'the nbus ~a~tett()request II VAXBfhus
transaction that executes a CBrc transaction. When the :tIRQlin{'Ut is asserted, a locipback
transaction is requested, This is used only when accessing a GBi(..ndeon th~lIEV <'4:0 > lines ~orrespond to the bit position in the event status register (ESR).
(Example: QCtal code, 30 represents the event defined by bit 30 of the ESR described in this
document.)'
lUhe EVSYNC bit 27 qf the CErc CSR i9 not set,. the information on lines IIEV.<4;O> js
synchroruzedwith the IICLKAand I~CLKB inputs by the CBIC . The informatioqrem"insfor One
Or more succ~ding IIC:LKAc,xcles. If tb,e EVSYNC bit.is set~ the event information is generatcQ

2-iU4

For Internal Use Only

_i
synchtonoullly with the VAXBI bus information and rftinains fordne VAXBI bus cycle, The user
must provide synchtonization ohhe node clock. This mode can be used £Or oodeswhen the system
clol;k is slower, than the VAXBI bus BIPHASE clock input.
n ac Low (llACLO)-This output is asserted when the line voltage is below the minimum level
specified, It performs the same functionas\Jhe BCIACLOsignahif the'BIICwhiChisd.efinediri the
VAXBI System Reference Manual.
~dc ~ow (IJD<;:LO}-This output isassertedtoiAdicate that a·dt; powel! kiss /Will occur. It is usW
for initialization during the powerup sequence. It performs the same function asili:eBClDCLO
signal of theBIIC which is defined in the V4)())I Systeml ).LThese bidJtectibnal·lines are the>pclnlaryinformition path·· ~f the
VAXBI bus. All address and data transfers and arbitrations~ences oCCuro'n ib~~eJines:
.

BI Init)rthatio~ (an <3:0 »~!~ bidireCtional. Iin!!~ ttan~fefco~mandk,/ en~Od8d. ~~ster
identification, tead status cOdes,.an~ writ«; masks. CQmm~ c~ be ~cteato':oij~ or lllore
nodes depending on the type of command. the coromand c:odes arid types ~ 'listea in Thble 4,
: '.! .

- ,,',

':,,:

\ ;.- ; ::'

" : ~ '.'

_~

4 "

, ",

~

,". -'

,',

j

:

~'-,

;

1able4 • 00514 conlmand Go«.t\Ssiturrentil·

Type'"

BII Line
3

2

1

0

H
H

H

H

H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L

H
L

H
H
H
H
H

H
L
L
L
L
L

L
L
L

H
H
L
L
L
L
H

H
H
H
L
L
L
L

H
L
H
L

Reserved
SR
SR
SR
SR
SR

H

SR

L

SR
MR
SR

H
L
H
L
H
L
H
L

Command/Description

MR
MR

MR
MR

~ad

RCI/Re~d with c~ch'e iht;ebt

IRCI/lnterlockread Wit¥! ckche intent
Write
WClfWilte~iilii~Heinteht
UWMcI/Unlochvl-lte mask wit:h caChe intent
WMCI/Write mask with cache intent
INTR/Interrupt
IDENT/Identify
Reserved
Reserved
Stop
INVAL/lnvalidate
BDCST/Broadcast (reserved)
IPINTR/Interprocessor internipt

*SR is as.ingle responder andMR is more than one responder.
BJParity (BIP)-A bidirectional signal that indicates the parity of the BID<31:00> and
Bll< 3:0.> information. It is asserted to generate odd parity if the sum of asserted bits in these two
fielclsisan even number.
For Internal Use Only

2-115

.-----------------"'--------,---------~-,-----~-----

VAXBIOC514
BI No' Arbitratioll .(BINOARB) ...... A bidirectional signal that is asserted'to inhibit using the
BID < 31:00 > line information when nodes are arbitrating for· control ofthe VAXBI bus: It is also
used during the cmc self-test progmm to prevent other 'nodes from starting transactions until all
n,odes arexeady to participate.
SI Busy (BIBUSY)-A bidirectionalsignalthat is asserted to indicate that a tmnsactionis in
progress.
BI Confirmation (BICNF < 2:0 > )- These bidirectional lines contain the response to command
and data cycles.
BI ae Low ("B;:C-IA"'C""LO-:O"")_ This inpnd1'l.dicates that the ac line voltage
below a specified minimum level.

cif a critical bus component is

BI de Low: (BIDCLO)- Thi~ input indicates that the dc voltages are not within their specified
limits. . . '
.

j

•

.

.

•

•

.'

BI Broke (BIBROKE)-This input drives the BLEAD line of the VAXBl bus to inform the systems
on the VAXBI bus that a self-test failure of a node has occurred. !tis also used to determine when
the statlls LED indicators of a node will be lighted. An open-drain buffer circuit is required when
connecting this signal tothe VAXBI bus.
..
BI Timing (BITIME)-This inPYet is a 20-MHz square-wave signal that isgenemtedbyan ~tern~
differential EeL receiver at e~ch node. This input and the BIPHASEinput are used by the.CBIC to
g~nerate all the reqUired VAXBI bus synchronous timing signals. An open-dmin b1J.ffer circuit is
required when connecting this signal to the VAXBIbus.
BI Phase (BIPHASE)-A 5-MHz square-wave input that is generated by an external differential
ECL receiver device at each node. It is used with the BITIME input to generate all required VAXBI
bus synchronous timing sigp,als. An open-drain buffer,drcuit is required to connect this signal to
the VAXBl bus .

• Standm-d VAXBI Node Registers
The CBlC contains standard node registers that are defined in the VAXBI System Reference Manual
and listed in Table 5. The CBICregister functions that are. different from those defined in the
VAXBI System Reference Manual aredescrihed.
Table 5 • DC514 StaQdard VAXBI Node Registers

Register

Mnemonic

Address"

Device
VAXBI Control and Status
Bus Error
Error Interrupt Control
Interrupt Destination
Interprocessor Interrupt Mask
Force-bit IPINTRjSTOP Destination
Interprocessor Interrupt Source
Starting Address
.
Ending Address
Bel COlJ,trol and Smtus
Write Status
Force-bit IPINTRjSTOP command

DTYPE
VAXBICSR

bb+O
bb+4
bb+8
bb+C
bb+lO
bb+14
bb+18
bb+1C
bb+20
bb+24
bb+.28
bb+2C'
bb+30

2-116

HER
EINTRCSR
INTRDES
IPINTRMSK
FIPSDES
IPINTRSIC
SADR
EADR
BCICSR
WSTAT
FIPSDES
For Internal Use Only

i_

VAXBIOC514

Register

Mnemonic

Address"

UserInterfacdnterrupt Control
Bus Error Mask
General Purpo~ 0
General Purpose 1
General Purpose 2
GeneiaI Purpose 3

UINTRCSR
BEMR
GPRO
GPRl
.GPR2
GPR}

bb+40
bb + 48
pb+FO
bb+F4
bb+F8
bb + Fe

"bb is the base ~ddress of the first location of the nod~spilce.tileBUs Error. Mask Register (BEMR)
is implemetlte~ ll1 the CBlc: but not definedihthe VAXB'lSysteftfR4ere.nce Manual. .
Bus Error Register__ The User Parity Enable(UPt:N}bi~lno£ the CBIC~gister is
and read as a zem.

not writable

Bus Error Register-The User Parity 'Enable (UPEN) bit 050£ the CBIC register is
and read asa z¢to.
, .
.

not writable

Bus Error Mask Register-Contains abit-for.bit correspottdeoce with the Bus Error Register
(BER). Setting a bit in ihis register inhlhii;s~heassefti:oi),Qfthe IIBSTAT output when the
corresponding bit in the BER is set there\'JY dist1.QlipglheilltettUf!t,requesr.

VAXBI ConttWandStatusRegister~The Br?ke bit 124et~.rmipesthe state of theBIBROKE
output of the GBIC. It is a read/write (R{W)bit.
.
.
User Interface Interrupt ControIRegis~-The External Vector (EXVECTOR) bit 150£ the CBIC
register is not wdtableand is read as zem.lnternalwcmFs areprovicled inres('IGn~Jo IDENT
transactions only.

Bel Control and Status Begister-The. BIICCSR s:paceEnalJle(BICSREN)..bit 07 of the CBIC
register is not writable and is read as a zero. Accesses to the Bnc CSR space are processed internally
to theCBIC .

. Data 8uHerFJle R~~s
The Data ·BufferFile (DBF) ccinrains'additional registersto the standard VAXBI ~gisters.These
are the master·port registers,slave'.porttegisters, controlat1d 'status .registers, and valid-bit:dearon-read register.··1'he hexadeditnlll'addressassigntn~ntsand read1\\tri'teicapabilines o£each register
are shown.· Refer to the' VAXBI SySte1ft Ri/erenceManuatfdr: registers1'eferred to but not described in
this document.
.
.
Master~portRegisters

Master-port'registers are used for II bus·iriitiated transfers to the VAXBrbus. The'CBICcontains
high~speed DMA master ports optimized for block data tranSfers and a map Illasterpor:t. Both the
DMA master pottsahdthe map rnasterport have a commd;addlt

00

...

..

. 00

MASTER PORT A DMA DATA 0

04

MASTER PORT A, OMA DATA 1

.'

08

MASTER PORT A, DMA DATA 2

R

, DC

MASTER PORT A, OMA DATA 2

RIW

DATA

10

MASTER PORT B, OMA DATA 0

RIW

14

MASTER PORT S, DMA DATA 1

RIW

18

MASTER ~T S, DMA DATA 2

1C

MASTER.PORT 6, qMA DATA 3

20

MASTER PORT DMAADDRESS REGISTER

fIIW

I

MASTER PORT OMA COMMAND REGISTER

RIVV

24

,

38

58

,',
,

RIW

'

R/W'

MASTER PORT NEXT PAGE FRAME REGISTER

,

.'.

MASTER PORT VALID BIT REGISTER

6C

MASTER PORT VALID 8ft REGISTE:R

60

MASTER PORT VALID SIT'REGrSTER

64

MASTER PORT VALID BIT REGISTER

68

MASTER PORT VALID BIT REGISTER

6C

MASTER PORT VALID BIT REGISTER

.'

70
74

RI?J)I

.'

L

,

.

.

WI'IAP-

R
;

R

A
i,

;, .;

' .1,

R

R
....

.

R

MASTER PORT VALID BIT REGISTER

R

IVlASTER ~ORTVALID BIT REGISTER

R

Figure 3· DC514 Master-port DAfA RegistC1'S
The Master-port DMA data registers store eight contiguous long'ltroroi inreadfwritememory. The
registers ,are. designated Mas~r;portA registers (DataO-Data ~)flcnd Master-port 13 registers (Data
.O-;-Data3t Thelongwordsareorganized into the octaword data buffers~ The CBICsupports all
possible address alignments to these buffer~ by )Js,i:ngany foUl' seqm:ntial bytes of the two p<:tawords
refened to. as a transaction buffer. One transac;tion buffer maY,be accessed by an II,q1,1s transaction
while the other is accessed by the CBIC master control device to generate a VAXBI bus transaction.
If an overflow occurs when reading or writing from either octaword, it is automatically directed to
the first bytes of the other octaword. For example, the fourth longword of anunnatwally aligJ;J.ed
octftword transaction will extend into the first three bytes of the remaining octaV{ol.'d,
The Master-port DMA Address register. contains t11e address for the command/address cycle of.a
VAXBI, bus master-port transa.ction during a DMA operation. If the II1NCENA input is :asserted
dUring the transaction request,. the lower 9-bits of the' address are incremented by ,16, For. the next
masterc\Xll.'tDMAtransaction, this, register contains the address of the next seqm,ti1tialoctaword in
YA.XBI bus m~t;no,ry- When executing block DMA transfers, the tt:lcten1ent feature ell1lUnate~the
p'"~ed oft)1.e II
b~s mastert,o reload the DMA address befqr~
requesting
the next VAXBI bus
.
.
transaction.
The Master-port DMA Command register contains the VAXBI bus command for the command/
address cycle of a VAXBI bus master-port transaction during a DMA operation. The 4-bit command
is written into bits 19:16 of this register as shown Figure 4.

2-118

For Internal Use Only

~

OM" CO"'!Il!W'lD

Figure 4 • DC514 Master-port DMA Command Register Format

During II bus write operations to thisregister, only .the bits assf!rJJd on datalines IIP$J~:16 > are
written. The CBIC checks for correct parity only on these lines so that the value{6nIIP2 isa
calculation for the four command bits. The parity on the remaining IIP} and IIP < b6'2> lines are
not significant:·
During II bus read operations of this register, bits 31:20 and 15:00 are read as zeros; The CBIC
generates correct panty. on lines IIPi<3:0>t()I'.4he entirelongwqrd. .
.
The Master-port Next Page-frame Register (NPFR) holds the map'for the next page. It is'preloaded
by the II bus master with the highestadiltess of the next physical page to be accessed duting a DMA
block move operation'after the DMA [address register has been incremented beYond a page
boundary. When thePMA addtess¥gi~7ertea¢?es apagebou~dary, bi~s 31:09cifth,e NPFR sf!
transferred to the Master-port DMA~ddress register bits 31:09. This feature can increa$e the data
throughput during block DMA trans~qtiQns. Instead of halting wWle waiting for a new' ~ap, VAXBI
bus transactio~scan continue for ul~to a page while the II bus ~aster fetches and Io~asthe next
map, via transactions through the master-port map. Bits 08:.o.o·of this register are not transferred.
DuringU bus write o~ratiorls to tliisregistcr.the· infbrmatiorl,on·datalines IID'. is trot
written: The CBIC  and the 'r"aritY ts indicated on
lines UP < J:l:> The uPO line value is riotsigtiificant.. ."
,
Durin.glI bus read opetati6t1S, bitsO$:OOo£ this register ;rire ,re~d i~z~tbs:Th~ CBICgerlerates
correct parity forthe entire long\iiord on lines IIP<3;O

>-:' . '.

.

One master-port valid-bit register is ~ssigne~ .t~ each of tll~ eightrn'fster-port. cittaregistersJpthe
DBE Figiire5 shows the master-p(jrt valid~9it register f61'iri~ts: Bits!9 ifir'8tigh 16 "coniaitf the validbit information related to each byte of data:··
'.
.
.

31

19

16

~
. VAl:IOBITS .

Figure 5 -DC514 Master-port ValiJ·bitRegisterFormat
Valid bits ate set when data is written into bytelocatioris in the data register if the byte mask input
HBM < 3:0 > th~t c6rrespdfiastb the datatocatiorfitldkates thattlie data is valid. Table 6 lists the
byte locations and their correspondi,ng valid bits.

For lnternalUs~ Only

2-119

Prelimirtary
Table 6 • DC514 Master-port Valid.bit Register Assignments
Master-port A
Register
AddressByte

Valid-bit
Register
AddressBit

Master-port B
Register
AddressByte

Valid·bit
Register
AddressBit

00

07:00
15:08
23:16
31:24

58

16
17
18
19

10

07:00
15:08
23:16
31:24

68

16
17
18
19

04

07:00
15:08
23:16
23:16

5C

16
17
18
18

14

07:00
15:08
23:16
31:24

6C

16

07:00
5:08
23:16
31:24

60

16
17
18
19

18

07:00
15:08
23:16
31:24

70

07:00
15:08
23:16
31:24

64

16

lC

07:00
15:08
23:16
31:24

74

08

OC

17
18
19

17
18
19
16
17
18

19
16
17
18
19

The valid bit is used as the data mask on the BII < 3:0 > lines during the data L)'de of.a VAXBI bus
UWMCI or WMCI write transaction. The valid bits are :;lccessible to the II bus as read-only
locations in bits 19:16 of addresses 58 to 74 (hexadecimal). A valid bit is cleared when its
corresponding byte is accessed by the CBIC master control device in supplying data for a VAXBI bus
octaword write transaction. All valid bits are cleared by a II bus read transaction from location 7C
and following the self-test of the CBIC.

Map Master-port Registers- The map master port contains a Iongword data register, a mask/status
register, an address register, and a command register as shown in Figure 6.

IIAH<6:0>

110<31:00>

31

00

28

MASTER- PORT MAP DATA REGISTER

FIIW

2C

MASTER - PORT MAP MASK/STATUS REGISTER

FIIW

30

MASTER - PORT MAP ADDRESS REGISTER

FIIW

34

MASTER- PORT MAP COMMANDAEGISTEA

FIIW

Figure 6· DC514 Master-port Map Registers

For Internal Use Only

The Master-port Map Data register stores a longword of data during read or wr~te ll}~ster7port map
transactions .
The Master-port Map Mask/Status register contains mask information during map write transactions and status information during map read transactions. Figure 7 shows the register format.
During VAXBI bus UWMCI and WMCI transactions to the master port, bits 19:16 of thlstegister
are preloaded by the II bus master with the4cbitmas.kassoci.ated with.thedata ih the master-port
DMA data register. During II bus write operations to this.register, only the infohnation on data
lines lID < 19 :16 > is written.· The CRIC checks for correct parity on data lID < ,19; 16 > and the
mask bit parity is indicated on line HP2. Tlaepatity on lines lIP < 3,1:0 > is not significant.
19.

31

00

16

MASKlSiATOSBITS'

Figure 7· DC514M:aster-portMapMask/SfatusRegister Fonnat

Following a VAXBIbus. map n;:aqt~nsactioq to th.e ma~t~r po,~t, pits-;:;:J9:16~contain. th~ 4-bit
read sta~s c,Of,le for, the,dataJn th¢.mas~r-portlJ~U\. d;.lta~~~t.Ouring}Jp.us~~!i ()p~l'ati9n of
this regis~er, 9.i~sJl;2Q aqq.15:00 a~,re~das z~ros: Th~Pl\ltity"~f'lr~e eptirelongwordi:;;dn4icate<:i
bytpe ClUC 00 lines IIP< 3:0 >
. .
The Master-port Map Address register·ptQVidesthe caddresdiill'.theoommahdladdress;cycle of a
VAXBI bu.s master-port transaction during a

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Creator Tool                    : HardCopy
Modify Date                     : 2018:07:11 14:34:05-07:00
Create Date                     : 2018:07:11 13:08:31-07:00
Metadata Date                   : 2018:07:11 14:34:05-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Title                           : Scanned Document
Document ID                     : uuid:a93881e3-ec0c-9448-94dd-ba347f7fb49d
Instance ID                     : uuid:60d2476a-3c39-5e4c-b827-d383dfcb7c25
Page Layout                     : SinglePage
Page Count                      : 320
Creator                         : HardCopy