The Designer's Guide To VHDL

• cover.jpg
• sdarticle.pdf
  • Dedication
• sdarticle_001.pdf
  • Preface
    • Structure of the Book
    • Changes in the Second and Third Editions
    • Resources for Help and Information
    • Acknowledgments
• sdarticle_002.pdf
  • Chapter 1 Fundamental Concepts
    • 1.1 Modeling Digital Systems
    • 1.2 Domains and Levels of Modeling
    • 1.3 Modeling Languages
    • 1.4 VHDL Modeling Concepts
    • 1.5 Learning a New Language: Lexical Elements and Syntax
    • Exercises
• sdarticle_003.pdf
  • Chapter 2 Scalar Data Types and Operations
    • 2.1 Constants and Variables
    • 2.2 Scalar Types
    • 2.3 Type Classification
    • 2.4 Attributes of Scalar Types
    • 2.5 Expressions and Predefined Operations
    • Exercises
• sdarticle_004.pdf
  • Chapter 3 Sequential Statements
    • 3.1 If Statements
    • 3.2 Case Statements
    • 3.3 Null Statements
    • 3.4 Loop Statements
    • 3.5 Assertion and Report Statements
    • Exercises
• sdarticle_005.pdf
  • Chapter 4 Composite Data Types and Operations
    • 4.1 Arrays
    • 4.2 Unconstrained Array Types
    • 4.3 Array Operations and Referencing
    • 4.4 Records
    • Exercises
• sdarticle_006.pdf
  • Chapter 5 Basic Modeling Constructs
    • 5.1 Entity Declarations and Architecture Bodies
    • 5.2 Behavioral Descriptions
    • 5.3 Structural Descriptions
    • 5.4 Design Processing
    • Exercises
• sdarticle_007.pdf
  • Chapter 6 Subprograms
    • 6.1 Procedures
    • 6.2 Procedure Parameters
    • 6.3 Concurrent Procedure Call Statements
    • 6.4 Functions
    • 6.5 Overloading
    • 6.6 Visibility of Declarations
    • Exercises
• sdarticle_008.pdf
  • Chapter 7 Packages and Use Clauses
    • 7.1 Package Declarations
    • 7.2 Package Bodies
    • 7.3 Use Clauses
    • Exercises
• sdarticle_009.pdf
  • Chapter 8 Resolved Signals
    • 8.1 Basic Resolved Signals
    • 8.2 Resolved Signals, Ports, and Parameters
    • Exercises
• sdarticle_010.pdf
  • Chapter 9 Predefined and Standard Packages
    • 9.1 The Predefined Packages standard and env
    • 9.2 IEEE Standard Packages
    • Exercises
• sdarticle_011.pdf
  • Chapter 10 Case Study: A Pipelined Multiplier Accumulator
    • 10.1 Algorithm Outline
    • 10.2 A Behavioral Model
    • 10.3 A Register-Transfer-Level Model
    • Exercises
• sdarticle_012.pdf
  • Chapter 11 Aliases
    • 11.1 Aliases for Data Objects
    • 11.2 Aliases for Non-Data Items
    • Exercises
• sdarticle_013.pdf
  • Chapter 12 Generics
    • 12.1 Generic Constants
    • 12.2 Generic Types
    • 12.3 Generic Lists in Packages
    • 12.4 Generic Lists in Subprograms
    • 12.5 Generic Subprograms
    • 12.6 Generic Packages
    • Exercises
• sdarticle_014.pdf
  • Chapter 13 Components and Configurations
    • 13.1 Components
    • 13.2 Configuring Component Instances
    • 13.3 Configuration Specifications
    • Exercises
• sdarticle_015.pdf
  • Chapter 14 Generate Statements
    • 14.1 Generating Iterative Structures
    • 14.2 Conditionally Generating Structures
    • 14.3 Configuration of Generate Statements
    • Exercises
• sdarticle_016.pdf
  • Chapter 15 Access Types
    • 15.1 Access Types
    • 15.2 Linked Data Structures
    • 15.3 An Ordered-Dictionary ADT Using Access Types
    • Exercises
• sdarticle_017.pdf
  • Chapter 16 Files and Input/Output
    • 16.1 Files
    • 16.2 The Package Textio
    • Exercises
• sdarticle_018.pdf
  • Chapter 17 Case Study: A Package for Memories
    • 17.1 The Memories Package
    • 17.2 Using the Memories Package
    • Exercises
• sdarticle_019.pdf
  • Chapter 18 Test Bench and Verification Features
    • 18.1 External Names
    • 18.2 Force and Release Assignments
    • 18.3 Embedded PSL in VHDL
    • Exercises
• sdarticle_020.pdf
  • Chapter 19 Shared Variables and Protected Types
    • 19.1 Shared Variables and Mutual Exclusion
    • 19.2 Uninstantiated Methods in Protected Types
    • Exercises
• sdarticle_021.pdf
  • Chapter 20 Attributes and Groups
    • 20.1 Predefined Attributes
    • 20.2 User-Defined Attributes
    • 20.3 Groups
    • Exercises
• sdarticle_022.pdf
  • Chapter 21 Design for Synthesis
    • 21.1 Synthesizable Subsets
    • 21.2 Use of Data Types
    • 21.3 Interpretation of Standard Logic Values
    • 21.4 Modeling Combinational Logic
    • 21.5 Modeling Sequential Logic
    • 21.6 Modeling Memories
    • 21.7 Synthesis Attributes
    • 21.8 Metacomments
    • Exercises
• sdarticle_023.pdf
  • Chapter 22 Case Study: System Design Using the Gumnut Core
    • 22.1 Overview of the Gumnut
    • 22.2 A Behavioral Model
    • 22.3 A Register-Transfer-Level Model
    • 22.4 A Digital Alarm Clock
    • Exercises
• sdarticle_024.pdf
  • Chapter 23 Miscellaneous Topics
    • 23.1 Guards and Blocks
    • 23.2 IP Encryption
    • 23.3 VHDL Procedural Interface (VHPI)
    • 23.4 Postponed Processes
    • 23.5 Conversion Functions in Association Lists
    • 23.6 Linkage Ports
    • Exercises
• sdarticle_025.pdf
  • Appendix A: Standard Packages
    • A.1 The Predefined Package standard
    • A.2 The Predefined Package env
    • A.3 The Predefined Package textio
    • A.4 Standard VHDL Mathematical Packages
    • A.5 The std_logic_1164 Multivalue Logic System Package
    • A.6 Standard Integer Numeric Packages
    • A.7 Standard Fixed-Point Packages
    • A.8 Standard Floating-Point Packages
• sdarticle_026.pdf
  • Appendix B: VHDL Syntax
    • B.1 Design File
    • B.2 Library Unit Declarations
    • B.3 Declarations and Specifications
    • B.4 Type Definitions
    • B.5 Concurrent Statements
    • B.6 Sequential Statements
    • B.7 Interfaces and Associations
    • B.8 Expressions and Names
• sdarticle_027.pdf
  • Appendix C: Answers to Exercises
    • Chapter 1
    • Chapter 2
    • Chapter 3
    • Chapter 4
    • Chapter 5
    • Chapter 6
    • Chapter 7
    • Chapter 8
    • Chapter 9
    • Chapter 10
    • Chapter 11
    • Chapter 13
    • Chapter 14
    • Chapter 15
    • Chapter 16
    • Chapter 17
    • Chapter 19
    • Chapter 20
    • Chapter 21
    • Chapter 22
    • Chapter 23
• sdarticle_028.pdf
  • References
• sdarticle_029.pdf
  • Index
    • Operators and Symbols
    • A
    • B
    • C
    • D
    • E
    • F
    • G
    • H
    • I
    • J
    • K
    • L
    • M
    • N
    • O
    • P
    • Q
    • R
    • S
    • T
    • U
    • V
    • W
    • X
    • Z