UP 3912_1050_Central_Processor_Reference_Manual 3912 1050 Central Processor Reference Manual
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CENTRAL
PROCESSOR
o
U P-3912 Rev. 1
()
This manual is published by the UNIVAC. Division in loose leaf format as
a rapid and complete means of keeping recipients apprised of UNIVAC
Systems developments. The UNIVAC Division will issue updating packages,
utilizing primarily a page-for-page or unit replacement technique. Such
issuance will provide notification of hardware and/or software changes
and refinements. The UNIVAC Division reserves the right to make such
additions, corrections, and/or deletions as, in the judgment of the UNIVAC
Division, are required by the development of its respective Systems .
• REGISTERED TRADEMARK OF THE SPERRY RAND CORPORATION
~~~~~-~.~~~~~~-~-----~-------~~~-
UNIVAC 1050 SYSTEMS
UP-3912
CENTRAL PRDCESSDR
Rev. 1
Contents
SECTION.
1
PAGE.
CONTENTS
C
CONTENTS
1 to 3
1. INTRODUCTION
1-1 to 1-13
1.1.
SCOPE
1-1
1.2.
1.2.1.
1.2.2.
1.2.3.
GENERAL DESCRIPTION
Control Function
Arithmetic Function
Storage Function
1-1
1-1
1-1
1-1
1.3.
1.3.1.
INFORMATION REPRESENTATION
Type of Notation
1-1
1-1
1.4.
1.4.1.
1.4.2.
DATA AND INSTRUCTION FORMATS
General Description
General Instruction Form at
1-9
1-9
1-9
1.5.
STORAGE
General
Tetrads
Fixed Interrupt Locations
Addressing
1-10
1-10
1-11
1-12
1-13
1.5.1.
1.5.2.
1.5.3.
1.5.4.
2. CODING IN ASSEMBLY LANGUAGE
C
2-1 to 2-11
2.1.
2.1.1.
2.1.2.
2.1.3.
2.1.4.
2.1.5.
2.1.6.
CODING FORM
Program I D
Sequence
Label
Operation
Operands
Comments
2-1
2-1
2-3
2-4
2-5
2-5
2-6
2.2.
SYMBOLS AND CONVENTIONS
2-6
2.3.
DATA GENERATION
2-9
2.4.
PAL JR ASSEMBLY SYSTEM
2-11
UNIVAC 1050 SYSTEMS
UP-3912
CENTRAL PRDCESSDR
Rev. 1
3. INSTRUCTION REPERTOIRE
2
Contents
SECTION:
3-1 to 3-73
PAGE:
/~
"-='
3.1.
3.1.1.
3.1.2.
3.1.3.
3.1.4.
3.1.5.
TETRAD INSTRUCTIONS
Bring to Tetrad
Sto re Tetr ad
Add to Tetrad
Compare Tetrad
Fix Tetrad
3-6
3-7
3-7
3-8
3-9
3-10
3.2.
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.2.5.
3.2.6.
3.2.7.
DATA TRANSFER INSTRUCTIONS
Bring Decimal
Bring Alphanumeric
Store Arithmetic Register
Store Both Arithmetic Registers
Store Character
Transfer Block from Store
Transfer Block to Store
3-12
3-14
3-16
3-17
3-17
3-18
3-20
3-22
3.3.
3.3.1.
3.3.2.
3.3.3.
3.3.4.
3.3.5.
3.3.6.
3.3.7.
3.3.8.
3.3.9.
3.3.10.
ARITHMETIC INSTRUCTIONS
Add Decimal
Subtract Decimal
Add to Memory
Subtract from Memory
Multiply Noncumulative
Multiply Cumulative
Divide
Add Binary
Subtract Binary
Add Ch aracter
3-24
3-26
3-28
3-29
3-31
3-32
3-34
3-36
3-38
3-39
3-40
3.4.
3.4.1.
3.4.2.
3.4.3.
3.4.4.
COMPARISON INSTRUCTIONS
Compare Decimal
Compare Binary
Compare Character
Logi cal Compare
3-42
3-44
3-46
3-47
3-48
3.5.
3.5.1.
3.5.2.
3.5.3.
3.5.4.
3.5.5.
3.5.6.
3.5.7.
3.5.8.
3.5.9.
3.5.10.
SEQUENCE CONTROL INSTRUCTIONS
Jump
Jump if Greater
Jump if Equal
Jump if Unequal
Jump if Smaller
Halt then Jump
Jump Display
Jump Conditional
Jump Return
Jump Loop
3-50
3-51
3-51
3-51
3-51
3-51
3-53
3-53
3-54
3-56
3-59
3.6.
3.6.1.
3.6.2.
3.6.3.
3.6.4.
3.6.5.
3.6.6.
3.6.7.
3.6.8.
3.6.9.
EDITING INSTRUCTIONS
Transl ate
Edit
Zero Suppress
Pad Blanks
Pad Zeros
Logical Sum
Logical Product
Bit Shift
Bit Circulate
3-60
3-61
3-63
3-66
3-68
3-68
3-69
3-70
3-71
3-72
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UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
c
CENTRAL PRDCESSDR
SECTION:
4.1.
GENERAL DESCRIPTION
4-1
4.2.
PROGRAMMING CONSIDERATIONS
Classes of Interrupt
Programmed Interrupt Inhibit
Instructions Associated with Interrupt Control
Fixed Interrupt Locations
4-1
4-1
4-3
4-3
4-3
4.2.2.
4.2.3.
4.2.4.
PAGE:
4-1 to 4-5
4. AUTOMATIC PROGRAM INTERRUPT
4.2.1.
3
Contents
5-1 to 5-12
5. CENTRAL PROCESSOR CONSOLE OPERATION
5.1.
5.1.1.
5.1.2.
5.1.3.
NORMAL OPERATION
Start Up and Shut Down
Program Start and Program Stop
Operating Mode
5-1
5-1
5-1
5-1
5.2.
PANEL CONTROLS AND INDICATORS
5-2
5.3.
5.3.1.
5.3.2.
5.3.3.
PROGRAM DEBUGGING AND TESTING
Use of Display Lights and Switches
Error Indicators
Sense Switches and Operator Request
5-7
5-7
5-10
5-11
Octal - Decimal Conversion Table
1 to 4
APPENDIX
A.
c
TABLES AND
FIGURES
TABLES
1-1
1-2
3-1
3-2
3-3a
3-3b
3-4
4-1
5-1
UNIVAC 1050 Character Set
Tetrad Location Chart
Suggested Standard Equal ity Statements
Instruction Repertoi re
Mnemonic Operations, Ordered by Operation Code
Mnemonic Operations, Ordered Alphabetically
Instruction Execution Times
Indicator List
Control Console Switch and Indicator Descriptions
1-6
1-11
3-2
3-3
3-5
3-5
3-73
4-4
5-2
Layout of The First Six Rows of Store
PAL Assembler Coding Form
PAL SO-Column Source Card
PAL 90-Column Source Card
Layout of Fi rst Si x Rows of Store
Central Processor Console
1-10
2-2
2-3
2-3
3-4
5-12
FIGURES
C
1-1
2-1
2-2
2-3
3-1
5-1
.~~~~~~~~~
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1
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PRDCESSDR
SECTION.
1
PAGE.
1. INTRODUCTION
1.1. SCOPE
The primary purpose of this manual is to provide the basic knowledge necessary for programming
the UNIVAC 1050 Central Processor, and serve as a reference for the programmer. Background
information is provided on the internal operation of the Central Processor and the different types
of information representation, as well as information on data and instruction formats, specialized
areas of storage (registers, I/O control tetrads, etc.), coding, the instruction repertoire, and
automatic program interrupt.
A second purpose of this manual is to describe the Central Processor Console and its operation,
and serve as a reference for the operator. A detailed description of all the console controls and
indicators is provided along with a description of their use to communicate with the program and
control various normal and abnormal conditions.
1.2. GENERAL DESCRIPTION
The Central Processor is the control center of the UNIVAC 1050 System. It contains the circuitry
for logic and arithmetic operations, the core storage and the power supply.
The Central Processor performs three main functions:
•
Control
• Storage
• Arithmetic Computation
1.2.1. Control Function
The control circuitry of the Central Processor accesses and executes instructions from storage.
It also maintains control over the operation of all peripheral devices. External control is
facilitated by the lights and buttons on the Central Processor Console.
1.2.2. Arithmetic Function
The arithmetic function instructions employ the arithmetic registers to perform binary and decimal addition and subtraction, as well as decimal multiplication and division. Overflow is indicated and decimal sign control is provided.
1.2.3. Storage Function
The storage function of the UNIVAC 1050 Central Processor is provided by one to eight modules
of core storage, each containing 4096 characters.
1.3. INFORMATION REPRESENTATION*
1.3.1. Type of Notation
c
Digital computers employ a system of notation called the binary system. Unlike the decimal
system which uses ten symbols (0 through 9) and is based on a radix (root) of 10, the binary
system employs only two symbols (0 and 1) and is based on a radix of 2.
*
The reader familiar with numbering systems may wish to skip to Section 1.4. DATA AND INSTRUCTION
FORMATS.
UP-3912
Rev. 1
1
UNIVAC 1060 SYSTEMS
CENTRAL PRDCESSDR
SECTION.
2
PAGE:
The two symbols of the binary system represent the two possible states of an information conveying electronic device. The 1 symbol indicates a registered pulse while the 0 symbol indicates a
no pulse registration. Information is represented in the computer by pulse-no-pulse combinations
with a specific pattern for each alphabetic, numeric, and special character.
1.3.1.1. Decimal and Binary
Numbering systems are based on positional notation. That is, each digit in a quantity is
weighted with a specific value. The value of a digit is determined by its position within the
quantity and the radix of the numbering system. For example, using decimal notation, the
number seven thousand four hundred sixty nine would be represented as 7469 which is
equi valen t to
Note that each digit, from right to left, is considered to be multiplied by a successively higher
power of 10.
The binary system is also based on a system of positional notation, but, as was stated
previously, it uses a radix of 2 and employs only two symbols to represent quantities. For
example, the number nine expressed in pure binary would be
1001
which is equivalent to
Note that each binary digit (bit), from right to left, is multiplied by successively higher powers
of 2.
1.3.1.2. Fixed Length Notation
Instead of specifying information with a variable series of binary digits (the length of the series
dependent upon the quantity to be specified) representing successively higher powers of 2, a
system of notation is used that specifies information by smaller, fixed length groupings of
binary digits. Each grouping, fixed in format as well as length, is used to represent a digit, an
alphabetic character, or a special symbol. Assuming a system of notation that employs a fixed
length format, a single digit would be represented by a single group of bits, a two digit
polynomial by two bit groupings, a three digit polynomial by three bit-groupings, and so forth.
For example, in pure binary the number 27 would be
11011
which is equivalent to
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'~'
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UNIVAC 10150 SYSTEMS
CENTRAL PRDCESSDR
SECTION:
3
PAGE:
However, by employing a fixed format of 4 bit notation, known as binary coded decimal, the
number 27 would be represented as
0010
0111
2
7
and similarly, the num ber 369 as
0011
0110
1001
3
6
9
Note that within each 4 bit grouping, the bit positions are weighted with a value of 8, 4, 2, and
1 or 2 3 , 22, 21, and 2°. The decimal digits 0 through 9 then are represented in the following
manner:
DECIMAL
BINARY 4 BIT NOTATION
0
0000
0001
c
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
With 4 bit positional notation, only 16 unique permutations can be created. This is obviously
insufficient to specify all numeric, alphabetic, and special characters generally employed in a
computing system. By adding two more bit positions and using them as a qualifying factor to a
4 bit combination, a total of 64 unique permutations can be represented. The four bit positions
on the right are called the numeric portion. Two additional positions on the left, which
represent no actual numeric quantity, are called the zone portion.
Qualification of a numeric quantity is unnecessary, therefore, the zone portion is always 00.
When representing alphabetic characters or special symbols, however, a 1 bit is entered in
either or both zone positions. The letters A through I, therefore, may be represented with the
numeric portion specifying a value from 1 to 9 (0001 to 1001) and the zone portion containing a
01 qualifier; the letters J through R with the same numeric specifications but with a zone
qualification of 10; and finally, the letters S through Z with a numeric specification of from 2
to 9 and a zone qualification of 11. So, for example, the letters A, J, and S would be
represented as
ZONE
NUMERIC
CHARACTER
01
0001
A
10
0001
J
11
0010
5
UP-3912
Rev. 1
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UNIVAC 1050 SYSTEMS
CENTRAL PROCESSOR
SECTION.
4
PAGE.
--------~----------------------------------~--------~~~----~~------I
This is not the same as UNIVAC 1050 code however.
The zone and numeric specifications for special symbols such as the comma, apostrophe,
asterisk, and so forth are dependent upon computer design. That is, computers are wired to
accept a unique bit combination for a particular special symbol. Since there is no natural
sequence relationship between special symbols, as with numerics or alphabetics, the bit
configuration for special symbols must be arbitrary. The sequence for UNIVAC 1050 special
symbols is shown in Table 1-1.
1.3.1.3. Excess Three (XS 3)
Excess three (XS 3) is a method of notation that is used by the UNIVAC 1050
System. It establishes some measure of compatibility with the data formats of the other UNIVAC
Computing Systems. The zone position is specified in the standard manner previously described
for fixed length binary coded decimal notation. The difference exists in the numeric portion
where each binary specification is a value that is three greater than its decimal equivalent.
For example, the number 8 is represented in XS 3 as
ZONE
NUMERIC
00
101 1
Note that the numeric portion, weighted with positional values of 8, 4, 2, and 1 from left to
right, is actually equal to 11. Similarly, the number 6 is represented as
ZONE
NUMERIC
00
1001
Here the numeric portion is specified as 9 or three greater than the decimal digit it represents.
There are several reasons for utilizing this method of notation in certain UNIVAC Systems;
some of these reasons are
•
It allows three quantities to test less than. O.
•
It facilitates complementation.
•
It permits the carry to occur as in decimal notation.
An involved discussion of these and other reasons for the utilization of XS 3 notation is beyond
the scope of this manual. It is sufficient that the programmer is aware of the basic format and
that this provides in the UNIVAC 1050 Computer a factor of data compatibility with other
UNIVAC Systems. Table 1-1 gives a listing of the XS 3 code configurations for all the
alphabetic, numeric, and special characters utilized in the UNIVAC 1050 System.
{-",
\.~J'
o
1
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PROCESSOR
SECTION.
5
PAC;E:
1.3.1.4. Parity
A parity check is used by the computer to ensure that accurate transmission of data occurs.
The parity position is an extra bit position added to ensure that there will always be an odd
number of 1 bits in any character representation. In this way, if a bit is either dropped or added
in transmission, the odd parity check will indicate an improper registration. For example, the
alphabetic S contains an even number of 1 bits:
ZONE
NUMERIC
11
0101
To pass the odd parity check, a 1 bit is added to the parity position, thereby creating an odd
number of 1 bits in the representation:
PARITY
ZONE
NUME RIC
11
0101
If the number of 1 bits in the configuration is already odd, the parity position will be O.
1.3.1.5. Octal Numbers and Complements
o
Octal notation is used in source language and program testi~g diagnostic printouts. The octal
or base 8, number system expresses values as multiples of powers of 8.
Octal notation is a fixed length system of binary notation. The binary number is interpreted
octaUy by grouping the bits into bytes of three, starting from the right, and interpreting each
byte into its octal equivalent. W.ithin each byte the bit positions are weighted with the value of
4,2, and 1, or 22, 2', and 2°. If, after grouping the bits in the fashion described, the most
significant byte contains less than three bits, as many binary zeros are implied to the left as
are required to bring the number of bits in that group to three. For example, the binllry number
10011101101 is interpreted octally as follows:
(0) 10
011
101
101
2
3
5
5
An octal number such as the one derived from the binary number described is noted with the
subscript 8 following it, e.g., 2355 8 , to distinguish it from the decimal number 2355 ,0 , In the
PAL assembly language employed in programming the UNIVAC 1050 System, however, an octal
number is noted by preceding it with a zero; thus, 02355 means 2355 8 , while 2355 means 2355 ,0 ,
.....
UP-3912
Rev. 1
1
UNIVAC 1050 SYSTEMS
CENTRAL PROCESSOR
CARD CODES
80
BINARY CODE
(Machine Collatin!
Sequence)
SECTION:
HIGH-SPEED
PRINTER
CHARACTER
COLUMN
90
COLUMN
NO PUNCH
NO PUNCH
11-5-8
1-3-5-7
000000
000001
11
0
1
2
3
4
5
6
0-3-5-7
0
1
1-9
3
3-9
5
5-9
000010
000011
000100
000101
000110
000111
001000
001001
7
8
9
0-6-8
11-6-8
12-5-812
5-8
12-3-8
12-0
7
7-9
9
0-1-3-7-9
1-3-5-7-9
0-5-7-9
0-1-3-5-7
1-3-7-9
1-3-5-9
0-1-3
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
3-8
1-5-9
1-5
0-7
0-3-5
0-3
1-7-9
5-7
3-7
3-5
0-1-5-7
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
12-6-8
12-7-8
7-8
11-4-8
11-3-8
11-0
11-1
11-2
11-3
11-4
0-1-5-9
0-1-3-5-7-9
0-1-5-7-9
0-1
0-1-3-5-9
0-3-7-9
1-3-5
3-5-9
0-9
0-5
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
11-5
11-6
11-7
11-8
11-9
0-5-8
4-8
11-7-8
0-2-8
0-4-8
0-5-9
1-3
1-3-7
3-5-7
1-7
0-1-9
0-1-3-7
0-1-7
0-1-7-9
0-1-5
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
0-3-8
2-8
0-1
0-2
0-3
0-4
0-5
0-6
0-7
0-8
0-3-5-9
1-5-7-9
3-5-7-9
1-5-7
3-7-9
0-5-7
0-3-9
0-3-7
0-7-9
1-3-9
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
,(comma)
&
0-9
12-4-8
6-8
0-7-8
5-7-9
0-1-3-9
0-3-5-7-9
0-1-3-5
111100
111101
111110
111111
Z
STANDARD
Space
(Non-Printing)
]
- (minus or
hyphen)
0
OPTIONAL
OCTAL
NUMBER
00
01
0
1
02
03
04
05
06
07
10
11
2
3
4
5
6
7
8
9
12
13
14
15
16
17
20
21
22
23
10
11
12
13
14
15
16
17
18
19
24
25
26
27
30
31
32
33
34
35
20
21
22
23
24
25
26
27
28
29
36
37
40
41
42
43
44
45
46
47
30
31
32
33
34
35
36
37
38
39
50
51
52
53
54
55
56
57
60
61
40
41
42
43
62
63
64
65
66
67
70
71
72
73
50
51
52
53
54
55
56
57
58
59
):l
74
75
76
)
77
60
61
62
63
1
2
3
4
5
6
7
8
9
";
[
+
&
: (colon)
_(period)
?
A
B
C
D
E
F
G
H
I
-
#
#
=-
<
@
• (apostrophe)
*
$
!
J
K
L
M
N
0
P
Q
R
%
' (apostrophe)
(
@
f:,
*"
(
J
%
+
S
T
U
V
W
X
y
)
>
):l
*NOTE: Only the characters that differ from the standard are listed for the optional print drum.
Table 1.1. UNIVAC 1050 Character Set.
44
45
46
47
48
49
6
PAGE:
UP-3912
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.
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.
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UNIVAC 1050 SYSTEMS
CENTRAL PRDCESSDR
SECTION.
The binary number 10011101101 is the sum of
j
1 x 2'0
1024
ox
29
0
0 x
28
0
x 27
128
x
26
x
25
64
32
0 x 24
0
23
8
x 22
4
0 x 2'
0
x
x 20
1261
Therefore, 2355 8 = 1261, o.
o
Appendix A provides a two-way octal to decimal and decimal to octal conversion table. For the
convenience of the programmer who wishes to do his own conversions, the following paragraphs
present an octal to decimal and a decimal to octal conversion procedure.
To convert an octal representation to its decimal equivalent, multiply the most significant digit by 8,
and add the next most significant digit to the product. Multiply this sum by 8 and add the third
most significant digit to the product. Repeat the multiplication and addition process until the
least significant digit has been added, whereupon this final sum will be the decimal equivalent
of the octal number.
The following example illustrates how this method converts 2355 8 into its decimal equivalent:
2x8=16
+
3
19x8=152
+
5
157x8=1256
+
5
1261
To convert a decimal number into its octal equivalent, divide 8 into the number and record the
remainder (0 through 7) as the last significant digit of the octal equivalent. Divide 8 into the
quotient, and record the remainder as the next least significant digit. Repeat the division of
the quotient recording the remainder until a quotient less than eight is realized, whereupon
the final quotient is the most significant digit of the octal equivalent and the final remainder
is the next most significant digit of the octal equivalent.
7
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The following example illustrates how this method converts 1261'0 into its octal equivalent:
REMAINDER
.. 2
0
B~
.. 3
B~
.. 5
Brt3f.
.. 5
B) 1261
I
No signs are involved in binary operations in the UNIVAC 1050 System; however, negative
binary values - or, effectively, their equivalent - can be developed and represented within the
computer. These negative binary values are represented as the two's complement of the binary
representation of the absolute value of the numbers. The two's complement is formed by adding
1 to the one's complement of the value, ignoring any carry beyond the most significant bit
position; and the one's complement, in turn, is formed by converting every 1 bit in the binary
representation to 0, and converting every 0 bit to 1.
For example, the binary representation of +1261'0 is
010011101101
the one's complement of this binary number is
101100010010
and the two's complement of the number is
101100010010
+
1
101100010011
=
5423 8
Whenever the binary integer 101100010011 is employed as an operand in a binary add or subtract
operation, the effective value of this operand is -1261,0'
,,<'
""'\
\~~)
c
1
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PRDCESSDR
9
SECTION,
PAGE.
1.4. DATA AND INSTRUCTION FORMATS
1.4.1. General Description
Instructions are contained in storage. They are always five characters in length
whereas data fie~ds may be any number of characters in length. Instructions are
executed in sequence except where a programmed instruction initiates a break in
the sequence.
The arithmetic unit of the Central Processor performs the calculations and data manipulation called for by the instructions. It contains an adder for decimal and binary
arithmetic operations, and additional circuitry which provides a wide range of data
handling abilities.
The control unit of the Central Processor selects, interprets, and initiates the execution of instructions in the stored programs which govern the operation of the
system.
1.4.2. General Instruction Format
1st CHARACTER
I
2nd CHARACTER
I
I
OBITS
OPERATION
CODE
vi
It:l DEX
w
REGISTER It:
I
23 22 21
26 2S I
30
BIT POSITIONS
c:'
l
3rd CHARACTER
i
I
I
5th CHARACTER
4th CHARACTER
I
I
DETAIL
STORAGE
ADDRESS
I
I
I
I
i
I
7 6
1
NAME
30 - 26
OP ERATION CODE
The operation code specifies the function which
the Central Processor is to execute.
25 - 23
INDEX REGISTER
The index register modifies the oddress specified
in the instruction.
22
RESERVED
This bit is reserved.
21 - 7
STORAGE ADDRESS
This is the (M) portion of the instruction. It
specifies the store address of the operand. If an
operand is greater than one character in length, (M)
refers to the least significant character of the
operand (rightmost). There are two exceptions:
Zero Suppress and Block Transfer instructions in
which (M) specifies the most significant character
of the operand.
6
DETAIL FIELD
Depending on the instruction, the detail field may
specify operand length, tetrad number, a comparison
indicator, an arithmetic register, or number of bits.
- 1
--~----
---~--------
1
UNIVAC 1050 SYSTEMS
llP-3912
Rev. 1
.--.------~---
CENTRAL PROCESSOR
SECTION:
10
PAGE:
1.5. STORAGE
1.5.1. General
The basic unit of storage in the UNIVAC 1050 store is the character which consists of six
information bits and one parity bit. The parity bit is of no concern to the programmer. It is used
only by the circuitry and is not accessible to him.
The UNIVAC 1050 Central Processor may have from 1 to 8 sections of storage, each
section comprisi ng 4096 character positions or locations. Each position has its own address
and each position is directly addressable.
Each section of main store is divided into rows. There are 64 rows in each section. A row
consists of 64 consecutive characters. The address of the most significant character (leftmost)
is either zero or some integral multiple of 64.
Program instructions and data are contained in storage. Each instruction occupies five consecutive locations. Data fields are variable in length. The sign, if any, of a data field is in the
most significant bit of the least significant character.
The first six rows of storage, portions of which perform unique functions, are illustrated in
Figure 1-1.
ROW
o
CHAR.
,
ROW
CHAR.
ROW
2
CHAR.
ROW
J
CHAR.
,
ROW
ZERDCDUNT
'e
'b
TRA.NSLATION TABLE ADDRESS
'f
L~EADVANCECOUNT
COLUMN COUNT FOR COLUMN READER
*c
BLDCKTRA.NSFERCOUNT
~d'
CfoIARACTER COUNTI
'g
'h
HOlF COU'H ,post-punch read ao~ punchl'
HOLE COUNT 'wait and p,e·punchl ,
"
_Reserved
'r
'Kl
,USED ONLY BY CONTROL UNITS
Figure 1-1.
Layout of First Six Rows of Store.
ROI'I COUNT Ipul1r.l>
'I
RDIVCQUNTIpr""readl'
'k "ROW COUNT FOR ROW READER
'1(2 PARITYODQLDCATIQrI
PARITY EVEN LOCATION
c
11
1
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PROCESSOR
SECTION:
PAGE:
1.5.2. Tetrads
The first four rows of storage in the UNIVAC 1050 System are subdivided into 64 fields of four
characters each and are called tetrads. Tetrads are addressable either by tetrad number or the
actual storage location. The method of addressing tetrads is dependent upon the instruction
being used. Certain tetrads are designed for specific functions. A description of what these
tetrads do is given in the following table.
TETRADS
o
PURPOSE
LOCATIONS
0-3
0-15
*Arithmetic Register 1 (ARl)
4-7
16-31
*Arithmetic Register 2 (AR2)
8
32,33
Character bit sum storage.
9-15
36-63
16
64-67
Destination address for Block Transfer
17
68-71
Origin address for Block Transfer
18
72
Address of table for trans lation
18
73
Count of zeros suppressed after Zero Suppress.
18
74,75
Controls number of characters in Block Transfer
19
77-79
Control Counter Storage
20-21
80-87
Multiplier - Quotient
22-31
88-127
Unassigned
32-35
128-143
Printer I/O, Channel 0
36-39
144-159
Reader I/O, Channell
40-43
160-175
Punch I/O, Channel 2
44-47
176-191
Communications I/O, Channel.3
48-51
192-207
Tape Read, Channe I 4
52-55
208-223
Tape Write, Channel 5
56-59
224-239
FASTRAND I/O, Channel 6
60-63
240-255
Channel 7, available for expansion
*Index Registers 1-7
* The
arithmetic registers and index reQisters can be addressed in three different ways: as arithmetic or index
re,isters, 8S tetrads, and as store locations.
Table 1-2.
Tetrad Location Chart
1.5.2.1. Arithmetic Registers
Tetrads 0 through 7 function as arithmetic registers. Arithmetic Register 1 (AR 1) comprises
tetrads 0 through 3 (store locations 16 through 31). The arithmetic registers are addressed
either by AR 1 or AR 2, tetrad number, or actual storage location.
UP-3912
Rev. 1
1
UNIVAC 1060 SYSTEMS
CENTRAL PROCESSOR
SECTION:
12
PAGEl
(
1.5.2.2. Index Registers
Tetrads 9 through 15 function as index registers 1 through 7. Since only tRe 15 least significant bits (contained in the three least significant characters) of each index register are used
in an indexed operation, the most significant character of each index register tetrad is available to be used for other purposes.
There are no signs in the index registers. The value in the index register is treated as an
absolute binary value in an indexed operation. Negative indexing may be accomplished by
placing the two's complement of the decrement number in the index register.
The index registers may be addressed by index register number, tetrad number, or actual
storage location number.
1.5.2.3. Input/Output Control Tetrads
A fixed storage area consisting of four consecutive tetrads is associated with each input/output channel. Information placed in this area controls the operation of the peripheral device.
The input/output control tetrads, that are located in storage rows two and three, are shown in
Figure 1-1.
1.5.3.
Fixed Interrupt Locations
Store locations 256 through 335 are fixed locations associated with the interrupt circuitry of
the system. These eighty locations are divided into ten groups of eight consecutive characters
each, which are known as interrupt entries. These interrupt entries are assigned as follows:
OCTAL
DECIMAL
INTERRUPT ENTRY ASSIGNMENTS
0400 - 0407
256 - 263
Channel 0: Printer
0410 - 0417
264 - 271
Channel 1 : Reader
0420 - 0427
272 - 279
Channel 2 : Card Punch Unit
0430 - 0437
280 - 287
Channel 3 : Communications
0440 - 0447
288 - 295
Channel 4: Magnetic Tape Read
0450 - 0457
296 - 303
Channel 5: Magnetic Tape Write
0460 - 0467
304 - 311
Channel 6 : Mass Storage
0470 - 0477
312- 319
Channel 7 : Unassigned
0500 - 0507
320 - 327
Class I Interrupt Entry
0510 - 0517
328 - 335
Class II Interrupt Entry
The format of these interrupt entries, and their functions, are discussed fully in the section
on Automatic Program Interrupt (Section 4).
UP-3912
Rev. 1
C
CENTRAL PRDCESSDR
13
1
UNIVAC 10150 SYSTEMS
SECTION:
""caE:
1.5.4. Addressing
Instructions and data in storage are accessed by other instructions through the 15 bit memory
address designated the M portion of the instruction.
Whenever an instruction references a multicharacter field, the M portion usually designates the
address of the rightmost or least significant character. (The exceptions will be explained in
the description of the instructions involved.)
C·.·"'
.".
1
2
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PROCESSOR
SECTION:
PAGE:
o
2. CODING IN ASSEMBLY LANGUAGE
2.1. CODING FORM
Most programs for a UNIVAC 1050 System with 8192 character storage or larger are written in the
language of the PAL Assembly System. Programs for a system with 4096 character storage are
written in PAL Jr. See Section 2.4. The PAL assembler is a UNIVAC 1050 program which
accepts mnemonic and symbolic input, a form meaningful to the programmer, and generates instructions in absolute binary form, the only form meaningful to the computer. Any action based on
attempts to employ instruction forms not described in this reference manual deviates from UNIVAC
recommendations and must be the user's responsibility.
Figure 2-1 shows the symbolic coding form for the UNIVAC 1050 Pal Assembly System.
In the description of this form, which follows, certain terms are used with specific definitions:
c)
•
•
•
Alphabetic
character means a character of the English alphabet set (A through Z).
Numeric
character means a character of the Arabic numeral set (0 through 9).
Alphanumeric
character means an alphabetic character, a numeric character, or a special
symbol.
The symbolic coding format is composed of fixed format fields for program identification, page,
line, insert, label, operation, and variable format fields for operands and comments.
It will be noted that numbers are associated with each subdivision of the coding form. These indi-
cate the card columns into which the characters written by the programmer are to be punched. These
column numbers hold true for both 80 and 90 column cards. The 80 column source card is shown
in Figure 2-2; the 90 column source card, in Figure 2-3 In 90 column systems, columns 81 through
90 are also available to the Program-ID field, but their contents will not be printed on the output
listing; their use, therefore, is not recommended.
2.1.1.
Program-ID
The program name is written in this field. It is composed of from one to six alphanumeric
characters, and is written starting at column 75. An example of an entry in this field is
PROGRAM-ID
75
80
IP ,A , Y 0 1 I
I
I
I
::tiC:::
Cb
"0
< '
.w
\0
........
tv
"'%"""'-"'1-'
PAGE
UNIVAC
U
PROGRAM·ID
75
I
PAL ASSEMBLER CODING FORM
PROGRAM ________________________________________________________________
80
I
I
I
PROGRAMMER _________________ DATE
PAGE ___ OF_ _ PAGES
For BEGIN onl
SEQUENCE
{ AGE3
kiN! ;;
, ,
~
LABEL
7
11
I
I
I
I
I
18 19
I
I
I
I
,I COMMENTS
OPERANDS
OPERATION
13
I
30
I
I
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I
I
I
t
I
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I
45 146
40
I
I
,I
I
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;
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.L
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I
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I
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I
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I
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.L
I
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L
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;
,
:
;
,
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I
,"~I
,
I
I
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J
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1
I
I
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c
n
m~
9G
.' .
,
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<
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.......
,,'
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D@
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)10
>,
~~
-a~
.i
D~
am
n
m
en
en
a
D
I
,
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1ft
I
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n
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,
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/',
I
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,
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..
80
75
I
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PROGRAM.ID
70
60
.'
:
I
~
50
:
I
I
I
I
I
I
I
I
I
I
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III
::!
o
z
tv
,I
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1,1
I
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1
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(80·90 COLUMN FORM)
UD1·802 13/1256 125M 7/65
Figure 2-1. PAL A. -embler Coding Form
'U
~
51
III
-'"
tv
UP-3912
Rev. 1
o
3
2
UNIVAC 1050 SYSTEMS
CENTRAL PRDCESSDR
I
PAGE LINE I LABEL OPER.
PECT'ON.
OPERANDS
:
R
T
PAGE.
PROGRA
IDENT.
COMMENTS
000 00 000000 0000000 ooooooooooooooooooooooooooo~oooooooooooooooooooooooooo 0 0 000000
, 2 3 4 I
, '3 14 15 111111 11202'22 22 24 25 2121212130 3111 33 34 35.31 • • 4114142 43 44.:. 41 • • 115152 53 54l1li11151111111011121314 II II 611111111 II n 1114 7111 n Ill. .'
I ,. "'"
1 1 1 11 111111 1111111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1:1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 111111
I
222 22 222222 2222222 222222222222222222222222222:222222222222222222222222 2 2 2 22 222222
I
333 33 333333 3333333 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 333 3 3 313 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 33 333333
444 44 444444 4444444 44444444444444444444 44 4 44 4 4:4 44 4 4 4 44 44 4 4 4 44 4 4444 4 4 4 444 4 44 444444
I
555 55 555555 5555555 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 555 5 5 5:5 5 5 55 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 55 555555
I
86& && &&&&86 1868686 6 6 6 6 6 6 6 6 6 & 6 && &&& &&&&&&& 6 & &6:6 & 6 &&& & &&6 6 &1 6 6 6 1 6 6 6 6 6 6 6 6 6 6 66 866666
I
711 71 717171 1777777 11111111111111 7 11 7 1 7 7 111 7 7 111111 7 7 111 7 7 11111111 7 111111 7 71 177771
I
888 88 888888 8888888 888888888888888888888888888:888888888888888888888888 8 8 8 88 888888
I
999 99 999999 9999999 999999999999999999999999999:999999999999999999999999 999 99 999999
t 2 S 4 5
,'8,1111
12111411111111 1120~222224252121D2520~II333425.31 • • 4II~424344.~61 • • 30~525354I111I1151I1I1.I15ZI3I4.I161UIl1llIln 1114 1518 n 1111.
I
Figure 2-2. PAL 80-Column Source Cord.
,
PAGE LINE IER LABEL
,
ii-1z-12- Ii-Ii i2 1i-G-1z-i"2--ii
(.~
--
"1\
OPERATION
OPERANDS
ii- 1z-G-I2"-i"z--'z Iz-lzlz-1;-'z-li-'z-lz-i"2Iz-i"i-'z-li-G-I2"-';-'z-'i-'z-li-'z-lz-'212"-';-'z-lz
3. 3. 3. 3. 3. 34 3<1 3. 3. 3. 3.
3. ~. 3. 3. 3. 3. 3. 3. 34 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3+ 3. 3+ 3. 3.
56 56 56 56 56 56 56 56 56 56 56
56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56
/
1
,
3
• • •
7
8
•
10
11
12
13
14
IS
1.
17
18
"
20
21
"
23
,.
os
,.
OPERANDS / COMMENTS
'2 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
'2
12 '2 12 12 12 12
30
31
3.
32
35
34 34 3+ 3. 3+ 3. 3. 34 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3.
34 3. 34 3. 3. 3.
56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56
56 56 56 56 56 56
78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78
78 78 78 78 78 78
9
••
9
.7
.. ..
9
9
9
9
9
9
9
'0
51
52
53
54
,.9
9
56
9
.7
9
58
9
••
9
60
.,9
9
9
9
62
53
54
9
••
.. '7 .. ..
9
9
9
9
9
9
9
70
71
72
..
.,
••
"
PROGRAM
IDENTIFICA nON
----12-';-'Z-'2-'212 -------------------------
21" 28
--------------------------------------------------------------------
'2
,.
78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78 78
78 78 78 78 78 78 78 78 78 78 78
9
73
74
75
9
7.
9
9
9
9
77
78
7.
80
3.
37
38
3.
40
41
81
8'
83
8.
8'
8.
43
87
88
8'
'0
Figure 2-3 •• PAL 90-Column Source Cord.
2.1.2. Sequence
This field is a six character numeric field composed of a three digit page field, a two digit
line field, and a one digit insert field. There may be a page field entry and a line field entry
on each card.
While processing input lines, the assem bIer performs a sequence check on this field to make
sure that page and line entries are in ascending sequence. An out of sequence line is flagged
on the output listing as an "s" error.
UP-3912
Rev. 1
2
UNIVAC 1050 SYSTEMS
CENTRAL PRDCESSDR
SECTION.
4
PAGE.
The insert field is provided to permit the insertion of additional coding lines when correcting a source program. The insert field entry consists of one numeric digit. This field is used
when a line of coding is to be inserted on a particular page following a particular line. To
insert a line of coding between lines 23 and 24 of page 10, the coding used could be
SEQUENCE \
4 56 7
,PAGE3 LlN,l= ':IS
0,1
o2
3 7
i
I
I
There is one restriction on the digit used for INS. If more than one instruction is to follow
a particular page and line, each insertion line must have a sequentially higher INS number
than any preceding it.
If inserts are made, the cards punched from the insert lines must be physically placed in
their proper places in the source deck, prior to assembly.
2.1.3. Label
A label is an alphanumeric symbol associated with the line on which it appears. It consists
of five characters or less, the first character of which must be an alphabetic character
other than the letter X. A label must begin in column 7,and is terminated either by column
12 or by the first blank appearing in the field. The entire field may be blank. (Column 12
can be used only by a six character label, if any, of the assembler directive BEGIN or by
a comments line. Otherwise it is always left blank.)
The label of an instruction line names the leftmost character of the instruction, while the
label of a data field or a constant names the rightmost character of the field or constant.
Some examples of labels are
E
~T 7
.......
"
LABEL
0
j
13
11
S T A R T ",;
1"1':,
G 1 2
EN DR
I
-
-
N
~1,~
I
)
:,'.:
,(-,
\~j
....
-.-.-.-.-.~-~-
.....
2
UNIVAC 10150 SYSTEMS
UP-3912
Rev. 1
CENTRAL PROCESSOR
c
SECTION,
5
PAGE,
If column 7 contains a period, the entire line is a comment. It produces no coding, but the
line is printed on the output listing.
OPERANDS
30
2.1.4. Operation
The operation field is a six character field beginning in column 13. This field may not be
blank. The field usually contains a mnemonic operation code, which the assembler converts
into a five bit operation code. The operation field may also contain an assembler directive
or a data generating code.
An entry in this field must begin in column 13 and is terminated by the first blank appearing
in the field or by the end of the field.
The following are examples of operation field entries:
() ,
E
~
6 7
.,
LABEL
11
OPERATION
18 19
13
t
J
6
1
1
I
I
I
I
I
I
I
-
I
I
I
-
.I~
1
I
CT
+
45!~
40
30
I
<,; B A 1
~~-~
:~
OPERANDS
'-
-
- -
2.1.5. Operands
The operands field usually contains symbolic or absolute descriptions of the Index Register,
Storage Address, and Detail portions of an instruction. These descriptions are called
expressions.
Each expression except the last one on a line must be terminated by a comma immediately
following the last character of the expression. The last expression on a line is terminated
by a blank. The first blank following a character which is neither a blank nor a comma indicates that no more expressions follow. Column 72 also terminates the operands field.
The assembler processes the operands field from left to right, a character at a time. Whenever a comma is encountered, the assembler recognizes the end of an expression and expects at least one other expression to follow; but whenever a blank appears following a
non blank character which is not a comma, the assembler expects no more expressions to
follow on the same line. Two successive commas within a string of expressions indicate a
blank expression. An expression may have any number of preceding blanks.
~
6
2
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PRDCESSDR
SECTION:
PAGE:
The maximum number of expressions that may be written on one line and the interpretation
of each expression is determined by the contents of the operation field. Any line may have
less than the maximum number of expressions. For example, a symbol written as the M
expression on an instruction line might also define the length of the field addressed. In this
case, the L portion of the instruction line may be omitted.
Some possible forms for the OPERANDS field are
OPERANDS
30
M
is an expression designating the operand address.
L
is a decimal or octal number or defined label specifying the operand length in terms of
characters.
X
is an expression naming an index register.
I
is an expression identifying an indicator.
o
Note that if the last expression which might appear on a line is omitted, the comma which
would have preceded it is omitted. Also, if the M exprE:ssion is to be specified as zero, it
may not be represented by a comma, but must be written as zero (0).
2.1.6. Comments
Significant comments may be written anywhere on the line beyond the blank which terminates
the last expression. It is recommended, however, that comments be indented at column 46,
for the sake of obtaining an output listing which is easier to read. For example,
E
'r7
LABEL
OPERATION
11 ~13
I N I
TL
J C
-- -
I
OPERANDS
18 19
30
I
0
I
-
-
2.2. SYMBOLS AND CONVENTIONS
-
COMMENTS----,)
45 146
40
I
- --
I
EX I T
50
IL I N,E<
There are three general types of expressions:
•
Symbolic
value is assigned by the assembler
•
Constant
value is assigned by programmer
•
Combined value may be wholly or partially assigned by either the assembler or programmer
I
UNIVAC 10150 SYSTEMS
UP-3912
Rev. 1
c
2
CENTRAL PRDCESSDR
7
SECTION,
PAcaE,
A symbolic expression is one whose first character is an alphabetic character and is not preceded
by an apostrophe. An example of a symbolic expression is
OPERATION
OPERANDS
3
40
30
45
A constant expression is one whose first character is either an apostrophe or a number. A constant expression may be alphanumeric, decimal, or octal.
An alphanumeric constant is represented by enclosing it in apostrophes. From the expression, the
assembler generates the UNIVAC 1050 six bit code for every character appearing within the apostrophes. For example, the expression
~6 7
LABEL
~
11
,13
18 19
i!~i~
30
• 1 7 •
m:,t
I-...
:1
OPERANDS
OPERATION
-
40
I
45 146
I
i
I
i
-
I
produces the bit configurations 00 0100 and 00 1010, which are the UNIVAC 1050 six bit codes
for the characters 1 and 7, respectively.
A constant is decimal if its first character is a number other than zero. The assembler generates
the binary equivalent of the decimal number. For example, the expression
LABEL
7
OPERATION
11
3
1819
OPERANDS
30
produces the bit configuration 010001, which is the number seventeen expressed in binary.
If the first character of a constant expression is zero, the number is taken to be an octal number
and is converted from octal to binary. For example, the expression
OPERATION
3
is converted into 001111.
1
OPERANDS
30
40
-----
----~--
8
2
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PRDCESSOR
SECTION:
PAGE:
A special constant expression is the dollar sign ($), which means the current value of the
location counter. Its value is one greater than the address of the last location which the
assembler has assigned.
The following chart summarizes the interpretation given to each type expression.
TYPE OF ABBREVIAEXPRESSION
TION
Symbol
Location
S
FORM
one to five alphanumeric
characters beginn ing
with an alphabetic
character other than
the letter X.
VALUE
value assigned to the symbol as a result of an EQU
directive or of appearance
in the LABEL field.
current value of location
counter, namely the address
of the most sign ificant
character of the I ine in
EXAMPLE
L
TAP02
COST
+ 15
L
$
Octal
0
zero followed by octal
(0-7) digits.
value interpreted as base 8
and converted to binary.
017 has the va lue 001111
Decimal
to
Binary
0
non zero digit followed
by decimal (0-9) digits.
value interpreted as base
10 and converted to binary.
17 has the va lue 010001
Alphanumeric
A
$
wh ich the item $ appears.
any characters (excluding va lue of each character in
apostrophes) enclosed in
apostrophes (').
corresponding position
right justified (6-bit representation).
'ABC' has the value,
010100010101 010110;
'17' has the value
000100 001010
A combined expression is one that has two or three symbolic or constant expressions connected by a plus (+) ora minus (-) sign.
An expression may have a leading plus or minus sign to denote a positive or a negative
quantity. If an expression does not have a sign, it is assumed to be positive.
Since all expressions are converted into binary, a negative expression is converted into
the two's complement of the value.
('"
l\.j
UP-3912
UNIVAC 1060 SYSTEMS
C
2
CENTRAL PRDCESSDR
Rev. 1
9
SECTION.
PAGE.
2.3. DATA GENERATION
The PAL assembly system provides means of generating data other than instructions from a coding
line.
A constant of up to 16 characters is generated by writing +n or -n in the operation field of a line.
The n is a decimal number ranging from 1 through 16 specifying the number of characters in the
constant. An alphanumeric constant can range in length from 1 to 16 characters. This constant
must be written within apostrophes. A decimal constant can range in length from 1 to 7 characters.
An octal constant which can occupy from 1 to 8 characters is written with 1 to 16 digits plus a
preceding zero.
The label of such a line names the least significant character generated from the entry in the
operands field of that line.
The operands field must contain a single expression, which may be alphanumeric, decimal, octal,
or a label. If the value of the expression is an integer of less than n characters, the assembler
generates as many binary zeros to the left of the integer as are needed to fill out the rest of the
field. For example, from the line
~
~7
OPERANDS
OPERATION
LABEL
11
13
II
30
18 19
40
45 146
I
)
K 5
L-~
__
+ 3
I
5
-- -
I
I
I
.-
I
-
I
I
I
~
the assembler generates 000000 000000 000101. KS names the least significant character.
If the operands field expression is alphanumeric and the sign in the operation field is negative, the
sign bit of the constant is reversed. For example,' from the line
~6 7
OPERANDS
OPERATION
LABEL
11 ,13
30
18 19
--
+2
• 2 4 •
1..-,--_
I
-
the assembler generates 000101 000111, while from the line
11
13
- 2
C,'\
"
-- -I
I
I
18 19
• 2 4 •
the assembler generates 000101 100111.
30
45:
I
I
I
I
I
OPERANDS
OPERATION
!..J
40
40
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
10
2
CENTRAL PROCESSOR
SECTION.
PAGE.
When the operands field expression is decimal or octal, and the sign in the operation field is
negative, the two's complement of the expression value is generated. For example,
LABEL
'[
r
7
OPERATION
11
18 19
13
+2
1,...-0
-
-
I (
OPERANDS
o23
30
4
--
-
I
40
I
45 146
1
J
- --
-
I
II
...u
produces 000010 011100, while
~
~7
.....
LABEL
OPERANDS
OPERATION
11
18 19
13
- 2
-
---
o2 3
-,--""""",
30
4
-
I,J
40
I
-
,
I
45146
I
I
I
I
produces 111101 100100.
When the expression in the operands field is a label, unmodified, or with a constant modifier, and
the operation field contains:
~.
V
+1 - the length (in number of characters) of the field named by that label is supplied.
+3 - the 15 bit address which the assembler assigns to the label will be supplied, preceded by
three binary zeros.
+4 - or higher - the 15 bit address assigned to the label occupies the 15 least significant bit
positions of the n character field, The rest of the field contains binary zeros.
.t ....."'.
V
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
C
CENTRAL PROCESSOR
11
2
SECTION:
PAGE:
2.4. PAL JR ASSEMBLY SYSTEM
The PAL JR card assembler is used with a Central Processor that has a storage capacity of
4096 characters. The features of PAL JR are the same as those of the PAL assembler with
certain limi ta tions:
•
Label size is limited to three characters.
•
There are no implied fi.eld lengths. Field lengths and index registers must be specified in the
instructions.
•
The EQU directive may not be employed to specify the field length or the index register. AREA
directives may not be employed to specify index registers or fill characters and cannot define
subfields.
•
The second expression in the operands field of the Tetrad instructions must be a Tetrad number.
•
The I/O areas have fixed labels and index registers and cannot exceed two backup areas for
each unit.
•
The Comparison Jumps (JG, JE, JU, JS) are elimi nated in this system. The Jump Conditional
(JC) instruction is employed to perform their function.
•
The maximum value of a decimal or octal constant that can be described by the EQU directive
is 4095 (07777).
UP-3912
Rev. 1
c
CENTRAL PROCESSOR
1
3
UNIVAC 10150 SYSTEMS
SECTION:
PAGE:
3. INSTRUCTION REPERTOIRE
The instruction repertoire of the UNIVAC 1050 System is arranged in the following pages by functional category. Each category is introduced by a brief description of the general coding rules for
the instructions in that category.
Each instruction is described in the following manner:
OPERATION
Format:
PAL Mnemonic Required Expressions
Function:
(Concise description of what the instruction accomplishes)
Notes:
(Programming considerations and further description of the instruction)
Example(s):
(Programming examples and description of the operands in verbal and graphic form,
showing the operands before and after the execution of the instruction, if necessary)
In describing the operation of the various instructions, the abbreviation Mx specifies the effective
character or field position in main store. By effective character is meant M as modified by the
contents of index register X (if i~ is called for).
Any expression of the instruction other than M and X is the detail field. The detail field may have
subfields, some of which are extensions of the operation code. This accounts for the fact that the
octal operation codes for two or more instructions may be identical.
Preferably, the more commonly used special purpose tetrads should be addressed by means of a
label rather than a tetrad number. The ability to do so is provided by the EQU directive, which is
fully discussed later in this section. Table 3-1 presents a list of the labels used in the coding
examples.
In the Univac 1050 System there are 64 indicators addressed as decimal numbers 0 through 63
(octal 0 through 077). These indicators fall within three functional groups; indicators that
are testable, indicators that cause an unconditional jump and specific function to be performed,
and indicators that cause a certain function to be performed but do not break the sequence of
instructions. The function performed depends upon the indicator involved.
Among the testable indicators are those which test the settings of the three Sense Switches and
the thl'ee Sense Indicators. Sense Indicators are internal devices which are set and reset under
program control. Sense Switches are on the console and are set and reset manually. Unlike
comparison indicators which are set and reset as a result of a comparison, the Sense Indicators
may be set and reset arbitrarily to provide programmable switches.
c
UP-3912
Rev. 1
3
UNIVAC 1050 SYSTEMS
CENTRAL PROCESSOR
LABEL
OPERATION
SECTION:
2
PAGE:
OPERAND
OCTAL
DECIMAL
15
Arithmetic Register 1
037
31
Arithmetic Register 2
047
39
indeX register 1
ARl
EQU
017
AR2
EQU
Xl
EQU
X2
EQU
053
43
indeX register 2
X3
EQU
057
47
indeX register 3
X4
EQU
063
51
indeX register 4
X5
EQU
067
55
indeX regis ter 5
X6
EQU
073
59
indeX register 6
X7
EQU
077
63
indeX register 7
DST
EQU
0103
67
DeST ination address for
EQU
0107
Transfer From (TFR, TFI)
ORG
71
ORiGin addresS from
Transfer To (TTR, TTl)
TRO
ZCT
EQU
0110
72
EQU
0111
73
Translate table ROw address
Number of characters
suppressed
TCT
EQU
0113
75
Number of characters to be
transferred
MLR
QTN
EQU
0127
87
MultiplieR
EQU
0127
87
QuoTieNt
INDICATORS-NOT IN STORE
EQU
040
32
No operation
KHI
EQU
041
33
High indicator
KEQ
EQU
042
34
Equal indicator
EQU
043
35
Unequal indicator
EQU
044
EQU
045
36
37
Indicator of arithmetic
EQU
046
38
KNO
KUQ
KLO
KZR
Low indicator
result zero
KM
Ind icator of dec ima I
arithmetic result minus
KNB
EQU
047
39
Indicates overflow otcured in
last binary subtract or didn't
EQU
050
40
Dec ima I overflow ind icator
occur in last binary add
KDF
Table 3-1. Suggested Standard Equality Statements.
The use of these indicators is discussed in detail with the instructions involved. Normally the
indicators will be addressed using a label which is equated to the indicator number. The EQU
operation is defined in the Card Assembly System Manual. Table 3-1 lists the more commonly
used indicators and their suggested labels.
Tables 3-2 and 3-3, respectively, summarize the instruction repertoire and the mnemonic operation
codes of the UNIVAC 1050 System. The instruction execution times appear in Table 3-4 on page
3-73.
{~"
\~)
3
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PRDCESSDR
SECTION:
o
...
oa=
I-
z
o
u
I-
is
III
I\. = LOGICAL. AND
V
= LOGICAl..
OR
• = SENTINEL.
*
t
=M DESIGNATES THE
§
MOST SIGNIFICANT
CHAR. OF THE FIEL.O
= I,
00 IS INTERPRETED BY THE CIRCUITRY AS 0".
'*
000 IS INTERPRETED BY THE CIRCUITRY AS ala.
IS INTERPRETED BY. THE CIRCUITRY AS 020.
NOTE: SUBSCRIPT t INDICATES IMMEDIATE
** 0000
IF
a
BIT 15:;: 0; IF
DATA., AS OPPOSED TO REFERENCED
DATA.
C',
"
a = 2. BIT lIS = I.
Table 3-2.
Ins truction Repertoire.
3
PAGE:
~c::
~ -p
<
W
........\0
~
L
TETRAD
CHAR.
ROW
0
• • • • • •
nm~C
2~
-I ...
:a~
:.:.0
r-~
en
'a~
CHAR.
:a~
aen
n
m
ROW
2
ROW
3
•
K~~U.
K~AU
CHAR.
ADDRESS
COUNT
RECORD
READ
BASE
I
•
MEMORY
BASE
•
cHAR":. A~~:SS
RECORD
COU NT
I
DRUM
ADDRESS
ml:.lY\\JM:T
ADDRESS
RECORD
ADDRESS
•
RECORDED
BASE
ADDRESS
en
en
a
I :a
I
CHAR.
ROW
4
CHA'R.
ROW
5
III
PI
n
::!
ZERO COUNT
*b = TRANSLATION TABLE ADDRESS
*c = BLOCK TRANSFER COUNT
*e = LINE ADVANCE COUNT
*i
*1 = COLUMN COUNT FOR COLUMN READER
*g:: HOLE COUNT (Post-punch read and punch) t
*j
*d = CHARACTER COUNTt
*h
*a =
Reserved
Figure 3-1. Layout of First Six Rows of Store
= HOLE COUNT (wait and pre.punch) t
= ROW COUNT (punch) t
= ROW COUNT (pre-read) t
0
~
*k = ROW COUNT FOR ROW READER
*K2 = PARITY ODD LOCATION
*K! = PARITY EVEN LOCATION
W
t USED ONLY BY CONTROL UNITS
,.
'U
GI
!!I
()
()
~
()
UP-3912
Rev. 1
CENTRAL PRDCESSDR
c
OCTAL
OP CODE
MNEMONIC
00
02
04
06
10
12
DESCRIPTION
-
(Unassigned)
16
16
20
22
22
JR
TR
LC
BCn
BSn
FT
ZS*
ZS$
22
ZS
24
TFI
Jump Return
TRanslate
Logical Comparison
Bit Circulate
Bit Shilt
Fix Tetrad
Zero Suppress wi th asterisk Ii II
Zero Suppress with Iloating
dollar sign
Zero Suppress with no floating dollar sign
Transfer From memory, Increment destination address
Transfer From memory, Reset destination address
Transfer To Memory, Increment origin address
Transfer To memory, Reset
origin address
PaD blanks
PaD decimal zeros
Compare Decimal
Jump
Jump Conditi ona Ily
Jump Display
Jump if Equal
Jump if Greater
Halt, then Jump
Jump if Smaller
Jump if Unequal
Jump Loop
Compare Character
(Unassigned)
eXternal Function
Store Tetrad
Store Character
Bring to Tetrad
DiVide
MultiPly Cumulative
Mu Iti PIy Noncumu lative
EDit
Store Arithmetic register
Store both Arithmetic Registers
Logical Product
Bring Alphanumeric
Bring Decimal
Add Character
Add to Memory
Subtract from Memory
Logical Sum
Add Decimal
Subtract Decimal
Compare Binary
Add Binary
Subtract Binary
Compare Tetrad
Add to Tetrad
14
24
TFR
24
TTl
24
TTR
26
26
26
30
30
30
30
30
30
30
30
32
34
36
40
42
44
46
50
50
50
52
52
52
54
56
56
60
62
62
64
66
66
70
72
72
74
76
PD
PDO
CDa
J
JC
JD
JE
JG
JHJ
JS
JU
JL
CC
Table 3-30.
-
XF
ST
SC
BT
DV
MPC
MPN
ED
SAa
SAR
LP
BAa
BOa
AC
AMa
SMa
LS
ADa
SDa
CBa
ABa
SBa
CT
AT
"
"
"
Mnemonic Operations Ordered by
Operation Code.
*
5
3
UNIVAC 1050 SYSTEMS
SECTION:
MNEMONIC
OCTAL
INSTRUCTION OP CODE
DESCRIPTION
PAGE:
SEE
PAGE
Add Binary
3-38
Add Character
40
Add Decimal
26
Add to Memory
29
Add
to-Tetrad
7
f
'
_
------Sr-- Bring AiphanL1meric
16
16
Bit Circulate
72
56
Bring Decimal
14
Binary Shift
16
71
46
Bring to Tetrad
6
--TO-- CompareBinaij------- ---46
34
Compare Characte"r
CC
47
26
Compare Decimal
CDa
44
74
Compare Tetrad
CT
9
DV
50
DiVide
___ ~IL
---ED---- ---52-- EDIf---------- -
72
ABa
AC
ADa
AMa
___AJ___
BAa
BCn
BOa
BSn
BT
60
66 •
62
76
---cs;;---
63
FT
J
JC
JD
---JE---JG
JHJ
JL
__ JR ____
20
30
30
30
Fix Tetrad
10
Jump
51
Jump Conditiona Ily
54
Jump Display
--TIl--- JumpiTEquaT-------- ___ ~:L
51
Jump if Greater
30
51
Halt, then Jump
30
53
Jump Loop
32
59
10
J!!.!!1Q.!!!!t!!r1!.. _______ ___ ~IL
--3D-- Jump.if Smaller
51
30
Jump if Unequal
51
14
Logical Comparison
48
54
Logical Product
70
JS
JU
LC
LP
64
LS
69
---MPC--- --50-- .~.Q.gJ..!:~~u.!!l..----------34
MultiPly Cumulative
32
50
MultiPly Noncumulative
MPN
68
PO
26
PaD blanks
26
PaD decimal zeros
PDO
68
1752
Store Arithmetic register
SAa
1
---SAR--- c---52-- Storeboth-AfithmetTcRegiSters
17
39
72
Subtract Binary
SBa
18
44
Store Character
SC
28
66
Subtract Decimal
SDa
3162
SMa
~i!!.r'!.c!..f!!ll!!.. ~1!!9!y ____
---ft---f--T2--- Store Tetrad
6
24
Transfer From memory, InTFI
20
crement destination address
24
Transfer From memory, Reset
TFR
20
destination address
-------12-- TRanslate--------- - - - -61TR
24
Transler To memory, IncreTTl
ment origin address
22
24
Transfer To memory, Reset
TTR
origin address
22
---:ZST--22-- Zero Suppresswl1h-astefTSiI-- - - - - 66
fi II
ZS$
22
Zero Suppress with floating
66
dollar sign
22
Zero Suppress with no Iloating
ZS
66
dollar sign
*
- - -XF
- - - - - - - 40
- - - e~!!r.!l.a.!£~~i~ ______ - - - - -
Table 3-3b.
Mnemonic Operations Ordered
Alphabetically.
The XF instruction is explained in the peripheral hardware manual fot the unit to which it pertains.
3
UNIVAC 1050 SYSTEMS '
UP-3912
Rev. 1
CENTRAL PRDCESSDR
3.1
6
SECTION:
PAGE:
TETRAD INSTRUCTIONS
The format of a tetrad instructfon is
,
~7
LABEL
,13
11
-./"
-..r
where
OP
T ,
M,
40
45 14
I
X
I
-
-"
-
I.--'"
I
30
18 19
0 P
:
OPERANDS
OPERATION
I
I
'I
-
is the mnemonic operation code,
M is an expression designating the operand address,
T is an expression naming a tetrad,
X is an expression naming an index register modifier.
.~:
If index register modification is not desired, X may be omitted, and 'an instruction may be
written as follows:
~,
f; 7
,,
LABEL
OPERANDS
OPERATION
11 ,13
OP
I
M,
--
v- ~-
30
18 19
T
!~
4514~
40
I
I
I
I
--..
-
"
I
\
-.-..!-J
The assembler will, in this case, supply binary zeros in the index register portion of the
ins truction.
3.1.1.
BRING TO TETRAD
Format:
8T
Function:
Bring the four characters at Mx -3, Mx -2, Mx -l, and Mx into the specified
tetrad T.
M, T, X
Note:
The contents of Mx -3, Mx -2, Mx -l, and Mx are not changed.
Example:
Bring the contents of the four character field labeled START into tetrad 9 (IR1).
,
~7
LA8EL
11
}
~
13
S T A RT,
1---""'"---' .......
-----
I
30
18 19
BT
:~
OPERANDS
OPERA TlON
)
45 146 1
40
I
9
I
-.;---
--
I
I
' I
~
I
----I
o
CENTRAL PROCESSOR
Rev. 1
C
3
UNIVAC 1050 SYSTEMS
UP-3912
3.1.2.
7
SECTION:
PAQE:
STORE TETRAD
Format:
ST M, T, X
Function:
Store the contents of the specified tetrad T into Mx -3, Mx -2, Mx-l, andM x .
Note:
The contents of the tetrad are not altered.
...
. ,/
Example:
Store the contents of tetrad 9 into the four character field labeled TEMP.
OPERATION
11
13
OPERANDS
30
18 19
T E M P',
ST
I
I
40
45 146
9
. ~.'.
3.1.3.
o
ADD TO TETRAD
Format:
AT M, T, X
Function:
Perform a binary addition of the four character field at Mx -3, Mx -2, Mx-l,
and Mx to the specified tetrad T.
Notes:
a. The addition is a binary add. No signs are involved.
b.
Both operands are always 24 bits in length.
c. If overflow occurs beyond the most significant character position of the tetrad,
KNB (the Binary Overflow Indicator) is set to O. If overflow does not occur,
KNB is set to 1.
d. If overflow occurs, the carry beyond the most significant character position of
the tetrad is lost.
e.
o
The field at Mx -3, Mx -2, Mx-l, and Mx is not altered.
3
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PRDC.ESSDR
8
SECTION:
PAGE:
Examples:
• Add the 24-bit field INCR to tetrad 15.
E
1'r 7
I N C,R ,
AT
:I C)
30
18 19
11 ,13
.........
OPERANDS
OPERATION
LABEL
-I.-.
45 146
I
-
1 5
40
I
I
I
Tetrad 15 (before)
= 000000
INCR (before)
= 000000 000000 000000 000001
Tetrad 15 (after)
= 000000 010110 101101 111000
INCR (after)
= 000000
I
I
I
I
- -
-
--
I
I
010110 101101 110111
000000 000000 000001
Overflow has not occurred; KNB = 1.
•
~
LABEL
'r 7
Add the 24 bit field INCR to tetrad 14.
OPERATION
11
13
18 19
AT
v~_-
:c
OPERANDS
I N CR,
'-~
I
30
1
.(
-
40
45 146
I
-
I
I
-
-
I
I
- - I
\
Tetrad 14 (before) = 111111 111111 111111 111111
INCR (before)
= 000000 000000 000000 000001
Tetrad 14 (after)
= 000000 000000 000000 000000
INCR (after)
= 000000 000000 000000 000001
Overflow has occurred; KNB =
O.
o
------------------------------
UP-3912
Rev. 1
UNIVAC 1050 SYSTEMS
3
CENTRAL PRDCESSDR
o
9
SECTION:
PAGE:
COMPARE TETRAD
3.1.4.
Format:
CT M, T, X
Function:
Compare the contents of the specified tetrad T against the contents of
Mx ·3, Mx ·2, Mx ·l, and Mx'
Notes:
a. The comparison is a 24 bit binary comparison. No signs are involved.
b. The result of the comparison is stored in testable indicators as follows:
Result of
Comparison *
Status of Indicators after Comparison
Indicator Number (octal)
041
042
043
044
33
34
35
36
KEQ
(Equal)
KUQ
(Unequal)
KLO
(Low)
Indicator Number (decimal)
Suggested Mnemonic
0
c.
KHI
(High)
(T) = (Mx)
0
1
0
0
(T) < (Mx)
0
0
1
1
(T) > (Mx)
1
0
1
0
Neither operand is altered.
Example:
Compare the contents of tetrad 9 against the four character field labeled LIMIT.
~6 7
11
l
i-"
,13
- -_
l
CT
....
!~
OPERANDS
OPERATION
LABEL
30
18 19
4514~
40
)
I
LIMI T
9
-
I
-
-
I
-
I
---.I.
"
\
........
If tetrad 9 contains 001000 101011 100011 010101
and LIMIT contains 000100 101011 100011 010101
the contents of tetrad 9 are greater than the contents of the field LIMIT. After this
comparison is made, KHI and KUQ are set to 1, and KLO and KEQ are set to O.
c
*
(T) means "the contents 01 tetrad Til; (Mx? means "the
contents 01 M
x
"'.
/
UNIVAC 1060 SYSTEMS
UP-3912
Rev. 1
3
CENTRAL PRDCESSDR
3.1.5.
SECTION.
10
i·
PAGE.
o
FIX TETRAD
Format:
FT M, T, X
Function:
Place the 15 bit M portion of the instruction into the 15 least significant bit
positions of the specified tetrad T.
Notes:
a. The value of M is placed in the tetrad specified: not the value at the address
specified by M; but the 15 bit value of M itself. In this instruction, M is a constant.
After the instruction is executed, the 15 least significant bits of the tetrad will
equal the M portion of the FT instruction.
b. Binary zeros are inserted in the most significant bits of the second most significant character of the tetrad.
c. The most significant character of the tetrad is not affected by the instruction.
d. The interpretation of indexing is unique for this instruction. If the index register
is used, the value which is stored in the tetrad is the binary sum of the M portion
and the contents of the index register specified. Carries beyond the fifteenth bit
are ignored.
Examples:
•
Place the binary equivalent of a decimal 128 in tetrad 9 (index register 1).
•
This replaces the contents, if any, of IRl.
OPERANDS
OPERATION
11
13
30
1819
128,
Xl (before)
SAME
o
FT Instruction:
Xl (after)
Xl
'*
::L
010100
~~~~ fo~~
010100
::r
111111 111111 111111
M
0
1000 000010 000000 1
===r==
~1~~
000000 000010 000000
Note that the most significant character is not altered, and that binary zeros are
inserted into the three most significant bit positions of the second character.
,(.~
• This
form cannot be used in the processor with 4096 stora~e locations. PAL Jr. does not have the facility
to compute a tetrad number from an index re~ister desi~nation. The tetrad number must be used in the T
expression position.
\i.
'
'J
-- -- ....
_- ._-------_.--.-
--
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
3
CENTRAL PROCESSOR
c
•
SECTION:
PAGE:
Add the binary equivalent of a decimal 128 to the contents of index register 1.
OPERANDS
Opt.RATION
11
11
13
30
1819
FT
--....
Xl (before)
010100
-------------
000000 000010 000000
+
SAME
o
FT Instruction:
Xl (after)
010100
~
-------'000
00001~
000000 I
1001~~
---L--
000000 000100 000000
I
•
Subtract the binary equivalent of a decimal 128 from the contents of index register 1.
OPERANDS
Opt.RATION
13
30
1819
F T
-128,X1,X1
or
~
~, 7
f
.....
Opt. RATION
LABEL
11
I
-
13
FT
- ---
'-
- - --
o7
40
30
18 19
lI
OPERANDS
7 6 0 0 , Xl, X 11
45 146
1
--
I
-
-
I
I
I
-
Xl (before) = 010100 000000 000100 000000
Xl (after)
= 010100 000000 000010 000000
Note that the value to be subtracted is expressed either as a decimal integer with a
a leading minus sign, or octally as the fifteen bit two's complement of the value.
C'
,#-
N.B. Although the examples show values in the most significant character position
of an index register tetrad, it is not advisable to have anything in that character
but binary zeros. An index register tetrad should not contain anything other than an
index register value.
J.
UP-3912
Rev. 1
CENTRAL PRDCESSQR
3.2.
12
3
UNIVAC 1050 SYSTEMS
I'ECTION:
PAGE:
DATA TRANSFER INSTRUCTIONS
The UNIVAC 1050 System has two types of data transfer instructions: instructions involving
the arithmetic registers, and instructions which do not involve arithmetic registers. Under the
first category, data is transferred into and out of arithmetic registers. In the second category,
data are transferred either from one area of store to another, or from the instruction itself into
store.
a. The format of data transfer instructions using the arithmetic registers is
LABEL
7
OPERANDS
OPERATION
1819
13
11
oP
M,
a
40
30
x
L,
where
OP is the mnemonic operation code,
a
is 1 or 2, indicating arithmetic register 1 or arithmetic register 2,
M is an expression naming the operand address,
L is a decimal or octal number or a defined label specifying the operand length in
terms of characters,
X is an expression naming an index register.
If index register modification is not desired, the X expression is omitted. The assembler
will insert binary zeros in the index register portion of the instruction.
The format of data transfer instructions using the arithmetic registers is
~6 7
LABEL
OPERATION
11
13
18 19
0 P
I
M
i.-.~~
(See Store Character)
E
T7
LABEL
-
30
c
X
---
--
13
oP
(See Transfer Block)
I
-"*"'"
I
-
1
I
1
- -
M
X
-- -
.....
I
45!461
40
I
I
: 6
30
I.
I
1
OPERANDS
18 19
-
I
45!46t
40
or
OPERATION
11
:
OPERANDS
1
--I
I
I
_I
)
I
---..
o
UP-3912
Rev. 1
UNIVAC 1050 SYSTEMS
CENTRAL PRDCESSDR
3
SECTION:
where
•
OP is the mnemonic operation code,
•
M is an expression naming an operand address,
•
C is the actual character that is to be transferred,
•
X is an index register expression.
Note: In all data transfer instructions, the sending field is never altered except when
sending and receiving fields overlap.
13
PAGE.
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
14
3
CENTRAL PROCESSOR
S .. CTION.
PAGE.
3.2.1. BRING DECIMAL
BOa M, L, X
Format:
Function:
Bring the L consecutive characters whose least significant character
is at Mx into the least significant characters of ARI or 2. Al1 zone bits
except the sign bit are changed to binary zeros.
Notes:
a. L is a decimal number ranging from 1 to 16, or an equivalent expression.
b. If less than sixteen characters are transferred, a sentinel is inserted in that
character position of the arithmetic register which is immediately to the left of
the Lth character copied. This sentinel is the character &, which, in the UNIVAC
1050 character set, is 110011. Insertion of the sentinel is an automatic hardware
function. Characters to the left of the sentinel are not affected.
c. The zone bits of each character with the exception of sign the bit (most significant
bit of the LSD) are changed to binary zeros.
Examples:
•
~6 7
......
LABEL
Bring the four character constant Kl into the four least significant character
positions of ARlo
11
•
13
BD 1
---"'ARI (before)
K 1 ,
4
-I7 I9
40
-
I
1
- -
~
I
141 2 1 4 1 5 1 5 1 2 1 7 1 3
18
I
-
1 6
I 0
,
45 146
I
I
Kl
ARI (after)
~
I
30
18 19
I
,
OPERANDS
OPERATION
I
I
I
)
-
1 8 1 2 1: 1
~I
3 18 &I 7 I 9 I I ~
1 7 1911
1 7 1 9 141 2
I
4 1 5 1 5 1 2 1 7 1
1
1
i
'I
!
UNIVAC 1060 SYSTEMS
UP-3912
3
CENTRAL PRDCESSDR
Rev. 1
o
•
If a field containing information other than numeric information is brought to an
arithmetic register by a BDa instruction, all zone bits are deleted in the transfer,
with the exception of the sign bit. For example,
OPERANDS
OPERATION
11
SECTION.
13
B D1
30
1819
N AM E
40
10
results in
ARI (before)
NAME
/7/W/I/2/4/5/5/2/7/3/8/6/0/8/2/~/
IJ/ Iwl IL/LI IA/M/s/
ARI (after)
The least significant character of NAME is an S (110101). When it is transferred
to ARl, only the sign bit appears in AR1; the least significant zone bit is
deleted, changing the S to K (100101).
C:'
15
-----,----
UP-3912
UNIVAC 1050 SYSTEMS
-
.
3
CENTRAL PRDCESSDR
Rev. 1
3.2.2.
16
SECTION:
PAGE:
BRING ALPHANUMERIC
Format:
BAa M, L, X
Function:
Bring the L consecutive characters whose least significant character is
at Mx into the L least significant character positions of AR1 or 2.
Notes:
a.
L is a decimal number ranging from 1 to 16, or an equivalent expression.
b.
The zone bits of all characters are transferred, and no sentinel is inserted.
Example:
Bring the 10 character field NAME into the 10 least significant positions of ARl.
,
~7
L
OPERATION
LABEL
13
11
--
--
BA 1
......
AR1 (before)
NAME
AR1 (after)
: '-
OPERANDS
30
18 19
NAME,
-
1 0
-
45 146)
40
I
I
-.L
-.L
I
I
I
-
I 7 I 9 t 4 I 2 I 4 I 5 I 5 I 2 I 7 I 3 I8 161 0 I8 I 2 141
IJI IwlllLILI IAIMlsl
I
_I
o
UP-3912
Rev. 1
UNIVAC 1060 SYSTEMS
C
3.2.3.
17
3
CENTRAL PRDCESSDR,
SECTION:
PAGE:
STORE ARITHMETIC REGISTER
Format:
SAa M, L., X
Function:
Store 'the L least significant characters of AR1 or 2 in the L consecutive
character positions whose least significant character is at Mx'
Note:
L is a decimal number ranging from 1 to 16, or an equivalent expression.
Example:
Store 8 characters from AR2 into TOTAL.
OPERANDS
OPERATION
13
40
30
1819
L
S A2
8
(~~)
.. ./
3.2.4.
STORE BOTH ARITHMETIC REGISTERS
Format:
SAR M"X
Function:
Store the contents of arithmetic registers 1 and 2 in the 32 consecutive
store positions whose least significant character is at Mx'
Note:
This instruction stores every position of both arithmetic registers, making the L
portion of the instruction superfluous.
Example:
Store the contents of both arithmetic registers in TEMP.
'E
~7
11
-- I
13
S A R
30
18 19
-
I~
OPERANDS
OPERATION
LABEL
T EM P
-
--
45 146 )
40
- -- ----I
-
I
-
.
I
I
-
\
1-/
UNIVAC 1060 SYSTEMS
UP-3912
3
CENTRAL PRDCESSDR
Rev. 1
18
SECTION:
PAGE:
3.2.5. STORE CHARACTER
Format:
SC M, C, X
Function:
Store the six bit character C in location Mx
Notes:
a.
This instruction stores the six bit character C in Mx' The arithmetic registers
are not involved in the operation, unless Mx refers to some position in an
arithmetic register.
b.
C is either
•
a decimal number ranging from 0 through 63, or
•
an octal number ranging from 0 through 077, or
•
a single character bounded by apostrophes.
Examples:
•
,~
T7
Store a binary 1 in COUNT.
11
S C
.--
COUNT,
-- ---
I
•
1
4C
-I
45!46
I
-
I
-i
I
1
~
-
.--!-
Store the UNIVAC 1050 six bit code for the digit 1 in COUNT.
OPERATION
11
30
18 19
13
lI
OPERANDS
OPERATION
LABEL
13
1819
OPERANDS
30
SC
c
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
o
•
19
3
CENTRAL PROCESSOR
SECTION:
PAQE:
Store the six bit configuration 010100 in INDIC. This may be written in anyone
of three ways:
OPERANDS
OPERATION
30
18 19
S C
I N 0 I C
40
2 0
because 010100 is the binary representation of 20;
OPERANDS
OPERATION
13
s
c
C
I
I N 0 I C
45 146
024
because the binary number 010100 is noted octally as 024; or
,
'f LABEL
~
7
11
13
~
:~
OPERANDS
OPERATION
S C
I
NO
- -
Ie.
• A •
~
I
40
30
18 19
I
-
-
45!46
I
-
because 010100 is the UNIVAC 1050 six bit code for the letter A.
c
I
40
30
1819
I
I
-
I
I
I
---'"""--....
~--------
UP-3912
Rev. 1
UNIVAC
1050~
SYSTEMS
CENTRAL PRDCESSDR
3.2.6.
---
3
I'ECTION.
20
PAGE.
TRANSFER BLOCK FROM STORE
TFR (reset)
TFI (increment) M"
Format:
Function:
X
Transfer a block of consecutive characters beginning with the most
significant character at Mx to that area in store whose most significant
character position is stored in DST (tetrad 16).
Notes:
a.
In the transfer block instructions, Mx addresses the most significant character
position of the sending field.
b. Prior to the execution of the TFR or TFI instruction, the binary count of
characters to be transferred must be program set in the ten least significant
bits of TCT (tetrad 18). The maximum number of characters that may be transferred is 1024. If the ten least significant bits of TCT are binary zeros, 1024
characters will be transferred.
The difference between the TFR and TFI instructions is that the address in DST
is reset to its original value after the TFR (Transfer From, Reset) instruction
is executed. After a TFI instruction the address in DST is incremented by the
number of characters specified by TCT. If TCT contains zeros, DST is incremented
by 1024. The original content of TCT is not disturbed by execution of this
instruction.
c. Prior to the execution of the TFR or TFI instruction, the address of the most
significant position of the receiving field must be program set in DST (tetrad
16).
o
d. After the TFR instruction has been executed, the address in DST is reset to
its original value.
e. After the TFI instruction is executed, the address in tetrad 16 is set to a value one
greater than the address of the latest character of the sending field.
o
--~---~--~.----
----
UP-3912
Rev. 1
UNIVAC 1050 SYSTEMS
3
CENTRAL PROCESSOR
SECTION.
21
PAGEl
Example:
Transfer a block of eighty consecutive characters from the area whose most
significant character position is labeled WSTOR, to the area whose most significant
character position is labeled PUNCH. The sequence of instructions required to
effect this transfer, using the TFR instruction, is as follows:
~
{r 7
,
LABEL
11
I
~ ......
30
18 19
13
FT
8 0"
F T
PUN C H
T F R.
W S T OJR
-
---
!C)
OPERANDS
OPERATIOH
45 1
I
T,C TI
-
461
40
D S T
-
-
I
I
I
I
I
I
-- -
I
-
I I
I
i
I
-
:
1-
I.
UNIVAC 1050 SYSTEMS
UP-3912
3
22
I·;
Rev.
1
_ _ _ _ _ _ _...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....._ _ _ _ _ _........;:S;;;E;,:C:.:,T.:,;IO;,:N;:.::_ _ _-&..:P;.:A;:.:G:,:E;.;._ _ _-I/
CENTRAL PRDCESSDR
l
j
3.2.7.
TRANSFER BLOCK TO STORE
Format:
TTR (reset)
TTl (increment) M" X
Function:
Transfer a specified number of characters, the address of whose most
significant character is stored in ORG (tetrad 17), to that area in store
whose most sil?;nificant character is Mx'
o
Notes:
a. In the transfer block instructions, Mx addresses the most significant character
position of the receiving field.
b. Prior to the execution of the TTR or TTl instruction, the binary count of characters
to be transferred must be program set in TCT (Tetrad 18). The maximum number of
characters that may be transferred is 1024. If the ten least significant bits of TCT
are binary zeros, 1024 characters are transferred.
The difference between the TTR and TTl instructions is that the address in ORG
is reset to its original value after the TTR (Transfer To, Reset) instruction is
executed; after the TTl (Transfer To, Increment) instruction is executed, the
address in ORG is incremented by the number of characters specified by TCT. If
TCT contains zeros, ORG is incremented by 1024. On completion of the instruction TCT contains its original value.
f"\
U
c. Prior to the execution of the TTR or TTl instruction, the address of the most
significant position of the sendin g field must be program set in ORG (tetrad 17).
d. After the TTR instruction has been executed, the address in ORG (tetrad 17) is
reset to its original value.
e. After the TTl instruction is executed, the address in tetrad 17 is set to a value one
greater than the address of the latest character of the sending field.
o
"'"
UNIVAC 10150 SYSTEMS
UP-3912
o
'-'-'''''-
~~~-
3
CENTRAL PROCESSOR
Rev. 1
'",,--,--
23
SECTION:
PAGE:
Example:
Using the TTl instruction, transfer a block of 80 consecutive characters from the
area whose most significant character position is labeled WSTOR, to the area whose
most significant character position is labeled PUNCH. After the transfer, leave ORG
set to refer to WSTOR + 80.
~
IT 7
11
13
F T
I
-
.
80,
T C T.
WS10R,
11 I
PUN C.H
_.....
-
40
30
18 19
FT
- --
•
ORG
-
45 146
I
I
I
•
•
I
,
}
I
I
• I •
•
"
c
~ ~)
OPERANDS
OPERATION
LABEL
•
I
I
•• • I
l
-
~
J
UP-3912
Rev. 1
UNIVAC 1050 SYSTEMS
CENTRAL PROCESSOR
3.3. ARITHMETIC INSTRUCTIONS
The UNIVAC 1050 System adds and subtracts in both the decimal mode and the binary mode,
and performs multiplication and division in the decimal mode. Decimal arithmetic operations
are governed by the following general rules:
a. The length of an operand in an arithmetic register is specified by the sentinel character &
(110011) immediately to the left of the most significant character of the operand.
b. The length of an operand in store is specified by the instruction.
i
I'
c. Operands in the arithmetic registers must always occupy the least significant character
positions of the register.
d. Except for the sign bit and the zone bits of the sentinel character, the zone bits of operands
are ignored and do not appear in the result.
e. If the result of a decimal arithmetic operation generates a carry beyond the most significant
character position of the result field, decimal overflow occurs. This terminates the
instruction, sets a testable indicator, and initiates a Class II interrupt.
In decimal add and subtract operations, the four characters (blank, +, @, ;t) having the internal
form xxOOOO will be converted to XS 3 zeros (000011) before the operation. Decimal operations
should not be performed with any of the following invalid numeric digits:
BINARY VALUE
SOURCE CHARACTERS
xx0001
* (
xxOOlO
$
xxllOl
%)
< ' >
xxl110
xxl111
Binary arithmetic operations are governed by the following general rules:
a. No algebraic signs are associated with an operand.
b. If the result of a binary arithmetic operation generates a carry beyond the most significant
bit position of the result field, binary overflow occurs, which terminates the instruction and
sets a testable indicator. Unlike decimal overflow, binary overflow does not initiate any
interrupt.
-----_._---------- . _ - - - - -
o
UP-3912
UNIVAC 10150 SYSTEMS
25
3
CENTRAL PRDCESSDR
Rev. 1
SECTION:
PAGE:
The formats of arithmetic instructions are
,
~7
LABEL
OPERANDS
OPERATIO"
18 19
13
11
o
P a
-
-1../
"""
M,
f
30
L ,
I
40
4S 146
I
X
J
-- -
- -
-
./-
I
--
--
I
~
and
~
T7
LABEL
OPERATION
11
13
18 19
OP
j
1__ .........-
-
:~
OPERANDS
M
-
30
C ,
-
X
-
J
.....
4S 146?
40
- -
I
I
I
a
is the mnemonic operation code,
is 1 or 2, specifying the arithmetic register to be used,
M is an operand address,
L is usually a decimal or an octal number specifying the length of one of the operands,
C may be
- a single character enclosed in apostrophes,
- a decimal number ranging from 0 th'rough 63,
- an octal number ranging from 0 through 077, or
- a symbolic expression.
X is an index register expression.
I
,I
- -!-J
where.
oP
)
I
i
UP~3912
UNIVAC 1050 SYSTEMS
CENTRAL PRDCESSDR
Rev. 1
3.3.1.
26
3
SECTION.
PAGE.
l-"
ADD DECIMAL
,-~J
Format:
ADa M, L, X
Function:
Perform a decimal algebraic addition of the L character field whose
least significant character is in Mx to the contents ofARl 01' 2 and
store the result in ARl or 2
Notes:
a. If no sentinel character appears in ARa, the working length of ARa is sixteen
characters. Otherwise, the sentinel character specifies the working length of
ARa.
b. Blanks (00 0000) in either operand are treated as decimal zeros (00 0011).
c. Zone bits other than the sign bit of the operand and the zone bits of the
sentinel are ignored and do not appear in the result.
d. If the length of ARa is equal to or greater than L, the instruction is terminated
when L characters have been added to ARa.
e. If the length of ARa is less than L, decimal zeros are substituted for the first
sentinel encountered in ARa and for all higher order positions of ARa, up to
and including the Lth position. A sentinel is then inserted into the position
immediately to the left of the Lth position of ARa, and addition proceeds.
f. Carries are propagated up to the sentinel position. A carry into the sentinel
does not alter the sentinel, but causes decimal overflow.
g. When decimal overflow occurs, the AD instruction is terminated, and an
interrupt is initiated which causes a transfer of control to the decimal overflow
'interrupt entry, a fixed hardware location.
h. Decimal overflow interrupt can be inhibited either manually on the system console, or by programmed instruction. If interrupt has been inhibited, a testable
indicator is set when overflow occurs.
i. The result of an AD instruction is recorded in testable indicators as follows:
If sum = 0, KZR (Indicator 37) is set to 1
If sum f. 0, KZR (Indicator 37) is set to 0
If sum is +, KM (Indicator 38) is set to 0
If sum is -, KM (Indicator 38) is set to 1
If overflow, KDF (Indicator 40) is set to 1
If no overflow, KDF (Indicator 40) is set to 0
a
3
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PRDCESSDR
c
27
SECTION:
PAGE:
j. A decimal zero result is always positi ve, with the following exceptions:
(1) -0 + (-0)
= -0
(2) a false zero result (such as that obtained by adding 99 and 1, which
should yield 100 but, on account of the sentinel, results in &00) will
carry the sign of the full result.
Examples:
Add the five digit field labeled FLDA to arithmetic register 1.
•
~6 7
11
_......
AD1
I
FLDA,
-
-
ARI (before)
:~
OPERANDS
30
OPERATION
18 19
13
LABEL
I
)
45!~
40
I
5
I
-
-
\3\2\6\9\8\
&
11 \21
I
-
I
& \
I
I
-
I
-
.-1
-
0 \ 0 \3\4\511 \ ~ \
FLDA
19 12 \ 3 \ 0 \
~\
ARI (after)
•
E
IF!
6 7
I
LABEL
11
-
Add the five digit field labeled FLDA to arithmetic register 2.
AD 2
-~
-
FLDA,
-
AR2 (before)
FLDA
C-)·,
'.
OPERANDS
30
OPERATION
18 19
13
AR2 (after)
5
-- - -
I
-
-
l~
45 1
40
--- --
I
I
I
I I I~ ,
1 3 1 2 1 6 1 9 18 1& 11 12'10 , 0 , 0 1 314 &
I 9 I 2 13 I 0 I ~ 1
II
, 3 1 2 1 6 1 9 , 8 1&., 1 12 , 0 1 0 1 &1 9 2 3 1 2 ,
~
,
I
I
)
....J.._
UP-3912
Rev. 1
3
UNIVAC 1050 SYSTEMS
CENTRAL PRDCESSDR
28
flECTION.
PAGIE.
o
3.3.2. SUBTRACT DECIMAL
SDa M, L, X
Format:
Function:
Perform a decimal algebraic subtraction of the L character field whose
least significant character is in Mx from the contents of ARI or 2. and
store the result in ARI or 2.
Note:
This in,struction operates identically to the ADa instruction, with the sole
exception that the operation is a subtraction. Otherwise, the notes under
, the ADa instruction apply.
Ii
I
Examples:
Subtract the five digit field labeled FLDA from arithmetic register 1.
•
,
,:
~
LABEL
7
OPERATION
13
11
18 19
30
FLO A
SO 1
I
-
-
" - ...........
!~
OPERANDS
5
I
-
45:
40
-~i
,
1
-
- - - '\~I
=\3\216\9\8\&\1121&10101314\&\
AR1 (before)
19121 3 101
FLDA
,I
I
~I
ARI (after)
•
E
l'r 7
LABEL
Subtract the five digit field labeled FLDA from arithmetic register 2.
11
13
18 19
S 02
l.,..oo""'- _-
-
II
OPERANDS
OPERATION
30
FLO A
-
I
5
40
I
-'-
45!46j
I
--I
~
AR2 (before)
= \ 3\2\6\9\8\' &\1 \2 \ &I 0 \ 0 \ 9\ 5\ 0 \ 0 I ~
FLDA
=
)
~
IJ
\
1912\3\0\~\
o
AR2 (after)
I
I
l~
---------~-----
---
-~-~---
UP-3912
Rev. 1
C
UNIVAC 10150 SYSTEMS
CENTRAL PRDCESSDR
3.3.3.
SECTION.
ADD TO MEMORY
Format:
AMa M,L, X
Function:
Perform a decimal algebraic addition of the L least significant
characters of ARI or 2 to the L consecutive characters in store whose
least significant character is Mx ' and place the sum in the field
at Mx'
Notes:
a.
Addition is terminated when L characters have been added from the arithmetic
register.
b.
If a sentinel is encountered in the arithmetic register before the Lth
character is added, addition proceeds as though the sentinel and all
characters to the left of the sentinel, up to the Lth position, were decimal
zeros. The contents of the arithmetic register, however, are unchanged.
c.
Carries are allowed to propagate up to the Lth character in store. A carry
occurring when the Lth character is added terminates the addition, and
decimal overflow occurs, causing an interrupt and setting KDF (IndicatOr
40) to 1. The carry is lost.
d.
Except for the sign bit, zone bits are ignored, and they do not appear in the
result.
e.
A zero result is always positive, except for the following cases:
(1) -0 + (-0) = -0
(2) A false zero result occurring when a carry is lost carries the sign of the
full true result.
f.
The results of the AM instruction are recorded in testable indicators as
follows:
If the sum
= 0, KZR (Indicator 37) is set to 1
If the sum f. 0, KZR (Indicator 37) is set to 0
If the sum is +, KM (Indicator 38) is set to 0
If the sum is -, KM (Indicator 38) is set to 1
If overflow, KDF (Indicator 40) is set to 1
If no overflow, KDF (Indicator 40) is set to 0
29
3
PAGE.
UNIVAC 1050 SYSTEMS
UP-3912
Re.v.l
3
CENTRAL PROCESSOR
30
SECTION:
PAGE.
Examples:
•
LABEL
7
Add the 5 least significant characters of arithmetic register 1 to the field
labeled FLDA.
OPERANDS
OPERATION
13
11
30
1819
A
F L DA
40
5
I'
=13121619181&11121&lololoI415111~1
ARl (before
& after)
FLDA (before) =
191213101~1
=
191618121~1
FLDA (after)
,,
•
LABEL
7
'--
Add the 5 least significant characters of arithmetic register 2 to the field
labeled FLDA.
13
11
-
30
18 19
AM2
AR2 (before
& after)
1I
OPERANDS
OPERATION
F L D A,.
-
S
- -
40
-- I
45!46j
I
- --
I
=13121619181711 121 01 01 01 3141 &111
.i
-
I
I
~I
FLDA (before) =
191213191~1
FLDA (after)
191214111~1
=
o
o
UNIVAC 1050 SYSTEMS
UP-3912
C:
3.3.4.
31
3
CENTRAL PRDCESSDR
Rev. 1
PAC;E:
SECTION:
SUBTRACT FROM MEMORY
Format:
SMa M, L, X
Function:
Perform a decimal algebraic subtraction of the L least significant
characters of AR1 or 2 from the L characters whose least significant
character is at Mx ' and store the difference in the field at Mx'
Note:
This instruction operates identically to the AMa instruction, except that the
operation is a subtraction. Otherwise, the notes under the AMa instruction
apply.
Example:
Subtract the 5 least significant characters of AR2 from the 5 characters at
BLNCE.
~6 7
~
'-
LABEL
-
11
13
BLNCE
(before)
BLNCE
(after)
c
B L NC E ,
~
AR2 (before
& after)
I
30
18 19
S M2
:
OPERANDS
OPERATION
15
40
45 146
I
I
-
,
I
-
-
15 16 13 10 141 s 171713141 &1 4 10 12 16 1; 1
I s 1719141;1
1417161sl~1
I
-
I
)
UP-3912
Rev. 1
UNIVAC 1050 SYSTEMS
CENTRAL PROCESSOR
3.3.5.
32
3
SECTION.
PAGE.
C)
MUL TIPL Y NON-CUMULATIVE
Format:
MPN ,L
Function:
Clear arithmetic register 1 to decimal zeros; multiply the multiplicand
in arithmetic register 2 by the L least significant characters of MLR
(tetrads 20 and 21); store the product, without sentinel, in arithmetic
register 1.
Notes:
a.
Both the multiplicand and the multiplier must be positioned by previous
instructions. The multiplier must be stored in the least significant character
positions of tetrads 20 and 21 (MLR) and must be preceded by decimal zeros if
less than eight characters. This field is eight characters long and is treated as
one field. The L specifies the L least significant characters of the field.
b.
The length of the multiplicand is determined by the sentinel in AR2. This
implies that the multiplicand must be loaded in AR2 by means of a BD2
instruction, rather than a BA2 instruction. No blanks should appear in the multiplicand field.
c.
The number of characters in the multiplicand plus the number of characters in the
multiplier must not exceed 16. The product is limited to the sixteen character
positions of AR1. If the number of characters in the product exceeds 16, undetected overflow may occur. A carry from the 16th position of AR1 will cause a
detected decimal overflow which will set indicator 40 and cause a class II
interrupt unless interrupt is inhibited.
f-~\
'0
The following are permissible combinations in multiplication.
L (number of characters)
in MLR
Allowable length of multiplicand
in AR2
1.15
2
1.14
3
1.13
4
1.12
5
1.11
6
1.10
7
1.9
,8
1·8
d.
The sign of the product is governed by normal algebraic rules. Like signs
yield a positive product, and unlike signs yield a negative product.
e.
If a sentinel appears in the least significant character position of AR2, the
multiplicand is considered to be -0 and, depending on the sign of the multiplier,
AR1 is cleared to either minus zeros or plus zeros.
f.
Multiplication destroys the contents of MLR (tetrads 20 and 21) but leaves the
multiplicand in AR2 unaltered.
o
UP-3912
Rev. 1
UNIVAC 1050 SYSTEMS
3
CENTRAL PRDCESSDR
c
g.
33
SECTION.
PAGE;
The result of the MPN instruction is recorded in the testable indicators as
follows:
If product
= 0, KZR (Indicator 37) is set to 1
If product -I 0, KZR (Indicator 37) is set to 0
If product is +, KM (Indicator 38) is set to 0
If product is -, KM (Indicator 38) is set to 1
If overflow occurs, KDF (Indicator 40) is set to 1.
h.
The index register and M portions of the instruction are ignored. When an MPN
instruction is coded, a blank expression must be written for the M portion.
Example:
Multiply a five digit multiplicand by a one digit multiplier. The first two
instructions position the multiplicand and the multiplier.
g
~7
LABEL
11
BT
K 5 , ML R
I
BD 2
RAT E,
J
M, PN
,
l .....
-
--
-
-
I
30
18 19
13
:\
OPERANDS
OPERATION
I
5
1
I
I
-- - I
-
I
I
I
-
~
I x I x I x I x I x I x I x I x I x I' x I x I x I x I x I x I x I
AR2
=1 xl xl xl xlxl xl xlxl xl xl &1
6 16 13
1 7 1; I
I al al a lal a la I
MLR
al~
I
~
I
The multiplicand is 66377, and the multiplier is 5.
After the MPN instruction is executed:
I a I a I a I a I a I a 1a I a I a I a 1 3 1 3 1
ARI
=
AR2
=1 xl xl xix Ixl xl x Ixl x Ixl &1
MLR
6
}
I
1
I ,\
1
~
--..!-
Before the MPN instruction is executed:
=
I
I
(Note: In the illustrations below, the x's represent characters the values of
which are immaterial to the MPN instruction.)
ARI
)
45!46I
40
Is lsi
I 6 13 17 I; I
Ix I xl x Ixlx Ix Ix I
~I
34
3
UNIVAC 1060 SYSTEMS
UP-3912
Rev. 1
CENTRAL PROCESSOR
SECTION:
PAGE,.
\
3.3.6.
o
MULTIPLY CUMULATIVE
Format:
MPC .L
Function:
Multiply the multiplicand in arithmetic register 2 by the L least
significant characters of MLR (tetrads 20 to 21), and add the product
to the contents of arithmetic register 1.
Notes:
This instruction operates identically to the MPN instruction, with the following
differences:
a.
AR1 is not cleared to zero.
b.
Any sentinel in AR1 is treated as a decimal zero.
c.
When the product is added to the contents of AR1, the absolute values of the
products and of AR1 are added, and AR1 takes the sign of the product.
d.
KZR is not affected if the cumulative product is O.
e.
If a carry occurs beyond the most significant character position of AR1, KDF
I
(Indicator 40) is set to 1 and decimal overflow occurs. The carry is lost,
o
f. Blanks in either AR1 or AR2 will result in an erroneous product.
Example:
Multiply a five digit multiplicand by a one digit multiplier. AR1 contains the
value 7163398238.
~7
LABEL
11
,13
BT
.1
t..--
-
30
18 19
K
5,
M L R
B D 2
RAT E ,
MPC
,
-
l \
OPERANDS
OPERATION
1
-
I
5
45lJ
40
1
-.l
I
I
I
I
I
\
I
I
I
I
- - -
-
..1
I I
I
I
I
I
J
I
I
-
:
_I
--....
o
UP-3912
Rev. 1
CENTRAL PRDCESSDR
SECTION:
(Note: In the illustrations below, the x's represent characters the values of
which are immaterial to the MPC instruction.)
Before the MPC instruction is executed:
I 7\1 I 6\ 3\ 3\
AR1
= \ x \ x \ x \ x \ xl
AR2
= \ x 1 x 1 xl xl x \ x\ x \ xl x 1 xl
&
&1
91 81
2\3
61 61
3\ 7\ ; I
I 0 I0 I 0 I 0I
MLR
0
1; 1
1 0 10 1
~1
The multiplicand is 66377, and the multiplier is 5.
After the MPC instruction is executed:
AR1
= I x 1 xl x 1 x I xl x I 7\1 1 6
AR2
=
1 x 1x1x 1x 1x \
MLR
(66377 x 5 = 331885)
c.·. '
..
35
3
UNIVAC 1050 SYSTEMS
\3\71 3 1 0 11 12
x \ x 1x 1x 1x \ &
\61 6 \3
1;
I
\7 \;
1
Ixlxlxlxlx Ix Ix Ix \
PAGE:
UP-3912
Rev. 1
36
3
UNIVAC 1050 SYSTEMS
CENTRAL PRDCESSDR
!'ECTION.
PAears in Mx.
b.
The contents of the arithmetic register are not changed, unless Mx addresses
either arithmetic register in which case the contents of the two registers could
be added or the content of one arithmetic register could be added to itself.
c.
The instruction specifies L characters; therefore the number of bits involved is
always 6L.
d.
No algebraic signs are associated with the operands.
e.
A carry beyond the most significant bit of the operand in store is lost, but KNB
(Indicator 39) is set to O.
f.
If there is no carry beyond the most significant bit of the operand in store, KNB
(Indicator 39) is set to 1.
g.
C''',
"
'
I
If the contents of the L store positions are binary zeros after the addition, KZR
(Indicator 37) is set to 1; otherwise, it is set to O.
Example:
Add, in binary, three characters from AR2 to TOTAL.
,
~7
11
A 82
1
J_
,13
--""
AR2 (before
& after)
I,
OPERANDS
OPERATION
LA8EL
3
TOTAL,
-
-- - =1 I I 1 I I I I 1
x
I
30
18 19
x
x
x
x
x
x
x
I
x
_I
1x
I
1
x
1
I
-- -
1
-
)
45!46j
I )
~
I
I
•
-
I
1 x 1 x 11 11 1 0 (octal 040403)
TOTAL
(before)
=
I I 51 wI
TOTAL
(after)
=
I EI 91 z I (octal 301474)
A
(octal 241071)'
o
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
c:
3
CENTRAL PROCESSOR
39
SECTION:
PAGE:
3.3.9. SUBTRACT BINARY
Format:
SBa M, L, X
Function:
Perform a binary subtraction of the L least significant characters of ARI or 2
from the L characters in store (whose least significant character is in
Mx )' and place the binary difference in the field at Mx.
Notes:
a.
The SBa instruction subtracts the contents of ARa from Mx placing the difference
in Mx.
b.
The contents of the arithmetic register are not changed, unless Mx addresses
either arithmetic register.
c.
The instruction specifies L characters; therefore the number of bits involved is
always 6L.
d.
No algebraic signs are associated with the operands.
e.
This instruction adds the 2's complement of the value in the arithmetic register
to the value in store.
f.
Carries propagate up to, but not beyond, the most significant bit of the field in
store. A carry beyond the most significant bit is lost, but sets Indicator 39 to 1.
If there is no carry KNB (Indicator 39) is set to O. This differs from the setting
described under the ABa instruction, because a carry beyond the most significant
bit indicates that the result in Mx is the true difference. If there is no carry, the
result is the complement of the true difference.
g.
If the contents of the L character positions are binary zeros after the subtraction,
KZR (Indicator 37) is set to 1; otherwise it is set to O.
Example:
Subtract, in binary, the 3 least significant characters of AR2 from QNTY.
~
~7
-
11
S B2
--....'"
I
~
AR2 (before
& after)
QNTY (before) =
c
30
18 19
13
QNTY{after)
,: t}
OPERANDS
OPERATION
LABEL
QNTY,
I
-
--.
Ix I I I
x
x
x
45!46
I
3
--
..0
1x 1x I x 1 x
I
x
1x 1x
I I
x
x
16 15
I
}
I
--LJ
131
(octal 111006)
Is 16 I I (octal 131145)
I-I ] I# 1(octal 020137)
K
UP-3912
Rev. 1
3
UNIVAC 1050 SYSTEMS
CENTRAL PRDCESSDR
40
SECTION.
PAGE.
ADD CHARACTER
3.3.10.
Format:
AC M,C,X
Function:
Add, in binary, the character C to the contents of Mx ' and store the
sum in Mx.
Notes:
a.
The binary value contained in the last six bit positions of the instruction is the
increment.
b.
The binary sum is stored at Mx.
c.
Carries are allowedto propagate into Mx-1 and as far as necessary.
d.
A carry beyond the most significant bit of Mx sets KNB (Indicator 39) to 0; if
there is no carry beyond this position, KNB is set to 1.
e.
The arithmetic registers are not affected by this instruction, unless Mx
addresses a character in AR1 or AR2.
Example:
o
Add the binary equivalent of a decimal 25 (011001) to the character labeled
COUNT.
'r:
tt
LABEL
7
•
~- -
11
~13
-
-.
-
45!4ll
40
I
2 5
CO U NT
- --- -
I
30
18 19
AC
:~
OPERANDS
OPERATION
-
.-
I
-
I
-
I
-
I
I
1
COUNT (before) = decimal 25
COUNT (after)
= decimal 50
This instruction may also be written as
,
~~ 7
I
........
LABEL
--
11 ,13
AC
I
-
I
30
18 19
-
:
OPERANDS
OPERATION
COU NT,
-
• F '
,
45!46/
40
I
I
-
I
1
1
1
-
I
--
Since 011001 is the UNIVAC 1050 character code for the letter F, it may
also be written as
I
1-
01
UP-3912
o
r
7
_
"
...........
....
AC
COUNT,
-
--
o3
1
- -
4S!.w
40
I
I
I
I
I
--
In all three cases, the assembler produces the bit configuration 011001.
o
PAGE.
I\
30
18 19
13
11
SECTION.
OPERANDS
OPERATION
LABEL
'(
41
3
UNIVAC 1060 SYSTEMS
CENTRAL PROCESSOR
Rev. 1
I
I
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
3
CENTRAL PRDCESSDR
SECTION.
3.4. COMPARISON INSTRUCTIONS
These instructions compare two values, and the result of the comparison is recorded in the
following indicators:
INDICATOR NAME
42
PAGE.
c
NUMBER
KHI (High Indicator)
33
KEQ (Equal Indicator)
34
KUQ (Unequal Indicator)
35
KLO (Low Indicator)
36
!'
The settings of these indicators can be tested by the program and appropriate action can
be taken.
Neither of the two fields involved in the comparison is changed as a result of the comparison.
The formats of the comparison instructions are
OPERANDS
30
x
c
and
OPERANDS
30
40
where
OP is the mnemonic operation code,
a
is 1 or 2, specifying the arithmetic register to be used,
o
UP-3912
Rev. 1
.0
CENTRAL PRDCESSDR
M is an operand address,
L is an expression specifying operand length,
C may be
- a single alphanumeric character enclosed in apostrophes,
- a decimal number ranging from 0 through 63,
- an octal number ranging from 0 through 077,
- a symbolic expression,
X is an index register expression.
C~·
~
.
43
3
UNIVAC 1050 SYSTEMS
SECTION:
PAGE:
UP-3912
Rev. 1
UNIVAC 1050 SYSTEMS
3
CENTRAL PRDCESSDR
3.4.1.
SECTION:
44
i
PAQE:
COMPARE DECIMAL
Format:
CDa M, L, X
Function:
Compare algebraically a signed number compri sing all digits to the right
of the rightmost sentinel in AR1 or 2 to a signed numeric field of L
(maximum of L is 16) decimal digits, starting with the least significant
digit location at Mx' Except for the sign bit zone portions are ignored; all
characters are treated as decimal digits. *
Notes:
I
a. If the signs of the two fields are unlike, the comparison is terminated immediately.
b. If no sentinel is present in the specified arithmetic register, all sixteen characters of the register are used in the comparison.
c. If there is a difference in the field lengths of the two operands, decimal zeros
are assumed in the implied high order positions of the shorter field, i.e., if one
field is five characters long and the other is eight characters long, the CD instruction assumes that the five character field is preceded by three decimal
zeros.
d. Comparison stops upon locating a sign difference or when the most significant
character of the longer field has been compared algebraically.
e. The result of the algebraic comparison is stored in testable indicators as
follows:
Result of
Comparison**
Status of Indicators after Comparison
Indicator Number (octal)
041
042
043
044
33
34
35
36
KHI
(High)
KEQ
(Equal)
KUQ
(Unequal)
KLO
(Low)
(ARa) = (Mx)
0
1
0
0
(ARa) < (Mx)
0
0
1
1
(ARa) > (Mx)
1
0
1
0
Indicator Number (decimal)
Suggested Mnemonic
* Compare
0
V
Binary should be employed lor comparisons involving alphabetics •
•• (ARa) means "the contents 01 ARa", and (M ) means "the contents 01 M ".
K
X
o
UP-3912
Rev. 1
UNIVAC 10150 SYSTEMS
CENTRAL PRDCESSDR
o
45
3
SECTION.
PAGE.
Example:
Compare decimally the five character field at CONST with the seven character
field in AR2.
1=
It; 7
LABEL
11
..
fL..,
c
D 2
AR2 (before )
& (after)
CON S
I
=
CONST (before) =
& (after)
I
x
I
30
18 19
13
:
OPERANDS
OPERATION
"
I
x
I
x
T,
I
x
5
I
x
I
I
x
I
x
I
x
I
45!~
40
& 101
-
I
0
I
I
4
I
4
I
131
5
I
0
I
t
I
lsi ~ I
The CD instruction assumes that CONST is a seven character field and treats it as
if it were 0013582. Since the contents of AR2 are greater than the contents of
CONST. the KHI and KUQ indicators are set.
o
I
!
1-
UNIVAC 10150 SYSTEMS
UP-3912
Rev. 1·
3
CENTRAL PROCESSOR
3.4.2.
SECTION:
46
PAGlE:
COMPARE BINARY
Format:
CBa M, L, X
Function:
Perform an absolute binary comparison of the L least significant
character positions of AR1 or 2 to the L characters whose least significant location is at Mx'
Notes:
a. The comparison is an absolute binary comparison; therefore the operation continues until L characters have been compared.
b. Since L specifies a length in terms of characters, the number of bits involved
in the comparison is 6 L.
c. The result of the comparison is recorded in the testable indicators as follows:
Result of
Comparison
Indicator Number (octal)
Status of Indicators after Comparison
041
042
043
044
33
34
35
36
KHI
(High)
KEQ
(Equal)
KUQ
(Unequal)
KLO
(Low)
(ARa) = (Mx)
0
1
0
0
(ARa) < (Mx)
0
0
1
1
(ARa) > (Mx)
1
0
1
0
Indicator NQmber (decimal)
Suggested Mnemonic
C
Example:
Compare the two characters at CODEX against the two Ie ast significant characters
of ARl.
o P.E RA N D S
40
30
CODEX
=
AR1
=
rn
Ix 1 x I x 1 x 1 x I x 1 x 1 x 1 x 1 x 1 x I x 1 x 1 x 1 B 1 2
(010101 000110)
1(010101000101)
Since the absolute binary value in AR1 is less than that in Mx' the KUQ (35) and
KLO (36) Indicators are set to 1.
-.--.-
.. --.--~---.----
..... --..
---.--------~
c'
UP-3912
c
UNIVAC 10150 SYSTEMS
SECTION.
COMPARE CHARACTER - CC M, C, X
Function:
Perform an absolute binary comparison of the character represented by
C to the character in Mx.
Notes:
a. C may be
•
a single alphanumeric character enclosed in apostrophes,
•
a decimal number ranging from 0 through 63,
•
an octal number ranging from 0 through 77, or
•
a symbolic expression.
b. The result of the comparison is stored in the testable indicators as follows:
C)
Result of
Comparison
Status of Indicators after Comparison
041
042
043
044
33
34
35
36
KHI
(High)
KEQ
(Equal)
KUQ
(Unequal)
KLO
(Low)
= (Mx)
t
1
0
t
C < (M x )
C> (Mx)
0
0
1
1
1
0
1
0
Indicator Number (octal)
Indicator Number (decimal)
Suggested Mnemonic
C
Example:
Compare the character at KEY1 against the character D.
OPERANDS
1819
c
30
40
If KEY1 contains the character G (011010), the character D (010111) is less than
KEY1, the Unequal (35) and Low (36) Indicators are set to 1.
t Unchangefl.
47
3-B
CENTRAL PRDCESSDR
PAGlE:
UNIVAC 1050 SYSTEMS
48
3-B
tJP-3912
CENTRAL' PROCESSDR
__S_E_C_T_IO~N~:______~P~A*G~E~:________~____________~____________________________--------------------~----------~i;
LOGICAL COMPARE - LC M, C, X
Function:
Test the character at Mx for the presence of 1 bit in every bit position
that corresponds to those bit positions of C which contain 1 bits.
Notes:
a. Only those corresponding bit positions in Mx and C containing 1 bits are
compared. All other bits are ignored.
\'
b. If all bit positions in Mx that correspond to the 1 bits in C are also 1 bits,
Mx and C are considered to be equal, and KEQ is set. Otherwise, C is considered to be higher in value.
c. If C is binary zeros, Mx and C are considered to be equal, regardless of the
contents of Mx'
d. The .result of the comparison is recorded in the testable indicators as follows:
Result of
Comparison
Status of Indicators after Comparison
Indicator Number (octal)
041
042
043
044
33
34
35
36
KHI
(High)
KEQ
(Equal)
KUQ
(Unequal)
KLO
(Low)
1
0
t
0
1
0
Indicator Number (decimal)
Suggested Mnemonic
'>
C
= (Mx)
t
1
C t- (Mx)
Example:
Compare the 1 bits of the character
r:
(r.r 7
LABEL
-
'8'
18 19
11 ,13
-
:I 0)
OPERANDS
OPERATION
LC
with the 1 bits of the character at CODE.
CODE ,
30
,
8 '
-
45i461
40
I
-
-
I
I
-.
I
I
I
I
I
-'
l~'"
t Unchanged.
"
,
I
,
UP-3912
Rev. 1
c
UNIVAC 1050 SYSTEMS
CENTRAL PROCESSOR
SECTION:
Since the UNIVAC 1050 bit configuration for the character '8' is 001011, CODE
will be considered equal to 8 if the first, second, and fourth bits (counting from the
rightmost bit) of CODE are 1 bits. Therefore the following bit configurations will
set the Equal Indicator:
001011
(8)
011011
(H)
101011
(Q)
111011
(V)
001111
([)
011111
(#)
101111
(~)
111111
(J:()
Any other bit configurations will set the KUQ and KHI Indicators.
c'
3
49
PAGE:
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
50
3
CENTRAL PRDCESSDR
SECTION.
PAGE.
3.5. SEQUENCE CONTROL INSTRUCTIONS
Normally the instructions in a UNIVAC 1050 program are accessed and executed
sequentially, i.e., in the order that they appear in main store. Whenever the conditions of the program require a break in this normal sequence, the sequence control instructions are used.
In the normal, sequential execution of instructions, the control counter is automatically incremented by five whenever an instruction is executed. This provides
the control unit with the address of the next instruction to be accessed by the
control register.
Sequence control instructions override this normal incrementation by changing the
contents of the control counter. This transfers program control to some instruction
which is not in sequence.
The format of a sequence control instruction is
,
LABEL
E
~
11
7
OP
t'r 7
M,
LABEL
I ,
or
I
~ {
i-I
-
OPERANDS
II
30
M , N , X
-
~
where
M
45 1461
-
18 19
13
II
40
I
-
-
.-
oP
oP
X
OPERATION
11
l
30
18 19
13
\1.-. _
E
OPERANDS
OPERATION
40
-
-
-
)
45!48
I
J
I
Cl
i
I
I
,
I
is the mnemonic operation code,
is the label of an instruction,
is an expression identifying an indicator,
N
is an expression giving a number,
X
is an index register expression.
In some special forms of sequence control instructions, the I expression is implied
by the operation code, in which case the instruction is written as follows:
[
?7
LABEL
11 ,13
----
OP
.........
-
OP.:RAHDS
OPERATION
30
18 19
i
M
-~
I
X
-- ,.
45 146)
40
I
I
-
-
-
-- - - o
I
1
I
.i-
I
! .
I
C
CENTRAL PRDCESSDR
3.5.1.
51
3
UNIVAC 1050 SYSTEMS
UP·3912
Rev. 1
SECTION.
PAGE.
JUMP
Format:
J M,X
Function:
Transfer program control unconditionally to the instruction labeled Mx.
Example:
Transfer program control unconditionally to the instruction labeled ENDRN.
,
~1
LABEL
J
1..-" ....... _ 3.5.2.
-
Cc;
-
-
-
45 14
I
-
I
-
I
-
-
I
I
--L_
JG M,X
JE M,X
JUMP IF UNEQUAL
Format:
3.5.5.
END R N
40
JUMP IF EQUAL
Format:
3.5.4.
----
30
JUMP IF GREATER
Format:
3.5.3.
18 19
13
11
II
OPERANDS
OPERATION
JU M,X
JUMP IF SMALLER
Format:
Function:
JS M, X
Test the comparison indicator specified by the operation code. If the
indicator is set to 1, transfer control to the instruction labeled Mx; if
it is set to 0, execute the next instruction in sequence.
Notes:
a. These four conditional jump instructions are not available with the PAL Jr.
System which is employed on the 4096 character storage capacity Central
Processor. The PAL Jr. System uses the Jump Conditional instruction with
indicator 33 for Jump if Greater, 34 for Jump if Equal, 35 for Jump if Unequal,
and 36 for Jump if Smaller.
b. These instructions are used in conjunction with the comparison instructions
(CT, CDa, CBa, CC, and LC). After a comp&rison instruction has been executed,
one or more of the comparison indicators (KHI, KEQ, KUQ, KLO) is set. The
comparison jumps test these indicators.
c. If a second expression appears on a line, it is interpreted as an index register
expression.
UP-3912
Rev. 1
UNIVAC 10150 SYSTEMS
52
3
CENTRAL PROCESSOR
SECTION:
PAGE.
r--""
Example:
'0
A comparison instruction has just been executed. If the Equal Indicator was set
as a result of the comparison, transfer control to the instruction labeled HEADR.
OPERANDS
OPERATION
13
1819
30
HE A D R
I'
c
.-w-'-...,-.,------------'_"4W-.,.--------
UP-3912
UNIVAC 1050 SYSTEMS
SECTION:
HAL T. THEN JUMP - JHJ M, X
Function:
Stop the computer. When the Program Start button on the console is
depressed, transfer program control to the instruction labeled Mx'
Notes:
a. This instruction is provided to allow the program to stop'the computer and
await some action on the part of the operator before processing is resumed.
b. When the computer stops, the control counter already contains the address of the
instruction to be executed when the Program Start button is depressed.
JUMP DISPLAY - JD M, X
Function:
53
3-B
CENTRAL PROCESSOR
Stop the computer and display the binary value at Mx on the console
dis play lights. When the Program Start button on the console is
depressed, execute the next instructi on in sequence.
Note:
The notes under the JHJ instruction apply, except that Mx is ignored and is
used for display purposes only. When the Program Start button is depressed,
control is transferred to the next instruction in sequence.'
\
PAGE:
UNIVAC 1050 SYSTEMS
3-B
SECTION:
54
CENTRAL PRDCESSOR
PAGE.
UP-3912
JUMP CONDITIONAL* - JC M, I, X
Transfer control according to the specification I.
Function:
Notes:
•
Conditional
1. The following indicators are associated with arithmetic operations.
Indicator
Control is transferred to Mx if:
I,
37 (KZR)
The result of the last arithmetic operation was zero.
38 (KM)
The result of the last decimal arithmetic operation was negative.
39 (KNB)
No overflow occurred in the last binary add operation or overflow
did occur in last binary subtract operation.
40 (KDF)
Decimal overflow occurred since the las t test for this condition. **
2.· The following values of I test the Sense Indicators. The Sense Indicators are devices
which are·set and reset by program instructions (See Unconditional, Note 1). The Sense
Indicators exist as a convenience for the programmer; while the comparison indicators
are set and reset as a result of a comparison, the Sense Indicators may be set and reset
arbitrarily.
Indicator
r
Control is transferred to Mx if:
53
Sense Indicator 1 is set to 1.
54
Sense Indicator 2 is set to 1.
55
Sense Indicator 3 is set to 1.
<'_J/'
3. The following indicators test the setting of the Sense Switches, which are set and
reset manually. These Sense Switches are on the console.
Indicator
Control is transferred to Mx if:
50
Sense Switch 1 is ON
51
Sense Switch 2 is ON
52
Sense Switch 3 is ON
* A listin~ of the various values of I and of their si~nificance is provided on pa~e
• * KDF is reset to zero. when tested. A11 other indicators are unaffected by testinQ.
" i
3-E-4 •
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PROCESSDR
c
•
55
3
SECTION:
PAGE:
Unconditional
a. The following indicators set and reset the testable Sense Indicators (See Conditional,
Note b). The Sense Indicators are not tested. After they are set'or reset, the instruction causes an unconditional transfer of control to Mx'
Indicator
Function
18
Set Sense Indicator 1 to 1 and jump to Mx'
19
Set Sense Indicator 2 to 1 and jump to Mx'
20
Set Sense Indicator 3 to 1 and jump to Mx'
21
Reset Sense Indicator 1 to 0 and jump to Mx'
22
Reset Sense Indicator 2 to 0 and jump to Mx'
23
Reset Sense Indicator 3 to 0 and jump to Mx'
b. The indicators 00 and 24 cause an unconditional transfer of control to Mx ' i.e., they
cause the JC instruction to operate identically to the J instruction. The J instruction
is actually a JC instruction which the assembler automatically supplies with the
indicator 00.
c. The indicators 32 and 56 do not test any of the hardware indicators. Control is always
transferred to the next instruction in sequence; in other words, a JC instruction with
an I expression of either 32 or 56 is a skip, or a No-Operation instruction.
C::
d. Indicator 41 stores the settings of comparison indicators 33 and 34 and the arithmetic
indicators 37-40 in Mx' It is unnecessary to store indicators 35 and 36 (unequal and
low) with indicators 33 and 34 (high and equal) stored. These indicators are stored
in character Mx in the following order: 40, 39, 38, 37, 34, 33.
Indicator 42 sets indicators 33-40 from Mx' Be careful that indicator 40 (decimal
overflow) is set properly. If by setting indicator 42 indicator 40 is set, a Class II
interrupt will be caused.
Example:
If the result of the last arithmetic operation was zero, transfer control to ZRBAL.
r
)
L,...oo
·~'
C
-
-"
.. '
11
7
I
30
18 19
13
J C
-
II
OPERANDS
OPERATION
t. LABEL
Z R B A L , 3.1 7
-
-
40
~
45 146
I
I
I
I
!
-
.i.
II
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PROCESSOR
3.5.9.
"
'
_
,
c
~
~
~
_ _ _ "_ _ _ _ _ _ . _____ •• _. _. _ _ _ _ _
~
___
~
~
________________
56
3
SECTION:
PAGE:
JUMP RETURN
Format:
JR M, I, X
Function:
Test the indicator specified by 1*. If it is set to 1, store the address
of the next instruction in sequence in the address portion of the
instruction at Mx' Program control is then transfer-red to the instruction immediately followingthe one at Mx'
Notes:
a. This instruction provides the programmer with the facility of breaking program
sequence and executing a subroutine; then it returns program control to the
instruction immediately following the JR instruction.
b. In order that control be returned to the instruction immediately following the
JR, the last line of the subroutine must be a J to the same label (M) as the
label to which the JR was executed.
c. The instruction at Mx must be a J instruction with no index register expression.
The address portion of this J instruction is usually zero, although any value may be
placed in it. This portion is destroyed when the JR to that line is executed.
d. The JR instruction tests the same indicators as those which the JC instruction does. The only difference between a JR and a JC instruction, other than
in timing, is that a JR stores the address of the instruction immediately follOWing it in the address portion of the instruction labeled M and transfers
.
x
control to Mx + 5, wh1le the JC merely transfers control to Mx .
e. Additional values of I are as follows:
Indicator
Function
16
Stop the computer. When the Program Start button
on the console is depressed, store the address of
the instruction immediately following in the address
portion of the instruction at Mx' and transfer control
to Mx + 5.
33 (KHI)
If the High Indicator is set, store the address of the
instruction immediately following in the address
portion of the instruction at Mx' and transfer control
to Mx + 5.
34 (KEQ)
If the Equal Indicator is set, store the address of the
instruction immediately following in the address portion of the instruction at Mx' and transfer control to
Mx + 5.
listing of the various values of I Bnd of their si~nificance is provided in Table 4,,1,
Page 4-4.
*A
I
I
UNIVAC 1050 SYSTEMS
UP-3912
3-B
CENTRAL PRDCESSDR
o
57
PACJE:
SECTION:
35 (KUQ)
If the Unequal indicator is set, store the address of
the instruction immediately following in the address
portion of the instruction at Mx ' and transfer control
to Mx + 5.
36 (KLO)
If the Low Indicator is set, store the address of the
instruction immediately following in the addressportion of the instruction at Mx ' and transfer control to
Mx + 5.
Example:
A binary subtract instruction has just been executed. If no overflow has occurred,
the result is the complement of the true result, and must be recomplemented. The
subroutine whose first instruction is RCMPL must be performed..-fn either case,
processing must continue whether or not the recomplementation subroutine has.
been executed.
Test for binary overflow; if none has occurred, perform the subroutine whose first
line is labeled RCMPL; otherwise, continue processing.
OPERANDS
OPERATION
o
11
13
30
1819
40
PL,KNB
J R
The line labeled RCMPL might be
OPERANDS
30
If the JR instruction above
effectively,
\
~
LABEL
7
a transfer of control, this line will become,
OPERATION
11
ReM P L
I....-~
~ffects
13
J
V-
OPERANOS
T EST + 5
- - - --
I\
30
18 19
I
40
40
-I
I
-
I
i
--
45 14d
I
1
I
.-
,
UNIVAC 1060 SYSTEMS
SECTION:
CENTRAL PRDCESSOR
58
3-B
PAGE:
c
and the last line of the subroutine must be
,
~7
L.-
LABEL
OPERATION
11
--
18 19
13
J
-
:
461
OPERANDS
ReM P L
30
40
I
--
I
I
I
I
-'
45 1
I
\
I
I
- - I
/
which will transfer control to TEST + 5.
c;
i
I
!
UNIVAC 1050 SYSTEMS
UP-3912
c
59
3-B
CENTRAL PRDCESSDR
SECTION:
PAGE:
JUMP LOOP - JL M, N, X
Test the N portion of the instruction against binary zeros (000000).
If equal, execute the next instruction in sequence. If unequal, decrement the N portion by a binary 1 (000001) and restore the new
value of N in the N portion of the instruction in main store. If the
new value of N is still unequal to 000000, transfer program control
to the instruction at Mx; otherwise,execute the next instruction
in sequence.
Function:
Notes:
a· The N portion of the instruction is never decremented past 000000.
b. The N portion serves as the working counter for the instruction. His decremented by 000001 every time that the JL instruction is executed.
c. The maximum value of N is 63.
d. After N has been decremented to 000000, N must be reset by a program instruction (usually an SC instruction) to its original value. Otherwise, N
will.remain at 000000 the next time that the JL instruction is executed.
c
Example:
Execute the subroutine, the first line of which is labeled BINAD, 9 times. The
line of the subroutine may be coded as follows:
't
~7
11 ,13
:
OPERANDS
OPERATION
LABEL
I
30
18 19
40
45 146j
\
- --
R PTA D
......
-- -
B I N AD,
J L
,
I
9
I
- - 1
I
I
-
I
I
.-
-
I
)
I
I
It is recommended that the next line be
~6 7
\ .....
LABEL
11 ,13
-
SC
R PTA D
.
30
18 19
I
:~
OPERANDS
OPERATION
+4 ,
9
- -
40
45:4'
I
I
I
-
I
-
so that, when the N portion of the line labeled RPT AD is decremented to 000000,
it is reset to its original value of 9.
I
UNIVAC 1050 SYSTEMS
SECTION.
UP-3912
CENTRAL PROCESSOR
60
3-B
PAGE.
c
6· EDITING INSTRUCTIONS
The editing instructions in the UNIVAC 1050 instruction repertoire are used to alter the form of
information in store by means other than arithmetic instructions. The formats of editing instructions are:
~6 7
LABEL
11
,
, 0 P a
t
.
OP
-- -
I
45:46
40
\
I ,(
I
1
oP
oP
30
18 19
13
I~
OPERANDS
OPERAT<10N
n
1
-
-.L
I
M
L
X
I
M
L ,
X
I
I
M ,
S ,
X
I
I
:
M.J
C
X
I
I
L
I
-
.1
it
i
L1
1.
~
-
J
I
I
I
- - ---J-J
where
•
OP is a mnemonic operation code,
•
a is 1 or 2, specifying an arithmetic register,
•
n is the number of characters involved in a bit shift,
•
M is an expression specifying an operand address,
•
L is an expression specifying operand length,
•
S is an expression specifying the number of bit positions that an operand is to be shifted,
•
C is a six bit editing pattern, and
•
X is an index register expression.
)
UP-3912
c
UNIVAC 10150 SYSTEMS
CENTRAL PRDCESSDR
61
3-B
SECTION:
PAGE:
TRANSLATE - TR M, L, X
Function:
Replace the L characters whose least significant character is in Mx
using a translation table.
Notes:
a.
The maximum value of L is 64 ..
b.
A translation table may consist of a maximum of 64 characters stored in any row
of store from 0-63. The row number must be program sl;lt in absolute location
72 (TRO).
c.
The Mx expression specifies the location of the least significant character to
be translated. Translation works from the least significant to the most significant character, until the number of characters specified by L have been
translated.
d.
The TR instruction replaces each character in the field to be translated with
a character selected from the row specified by TRO .. The basis for selecting
the replacemj:!nt character is the binary value of the character to be replaced.
The binary value of any six bit character ranges from zero (000000) through
63 (111111). This binary value provides the character address of the particular
six bit configuration within the specified row which is to replace the character.
In other words, a character with a binary value of zero (000000) is replaced by
whatever character is prestored in position 0 of the translate row; a character
with a binary value of 1 (000001) is replaced by whatever character is prestored
in position 1 of the translate row; and so on.
e.
The contents of the translate row are not altered by the instruction, unless
the translate row itself is translated.
f.
If L is greater than 15, L may not be implied by means of a previous
definition (cf. AREA Directive).
..
_S.E~C~T'~O~N~:
~
UNIVAC 1050 SYSTEMS
UP-3912
CENTRAL PRDCESSDR
62
3-B
____~~PA~G~E~:________~____________________________________________----------------------------~I
o
Example:
A three character field containing the bit configurations 010101 010100 100010 is
labeled FLDI. These bit configurations are the 90 column card codes for the
characters ABC. FLDI is to be printed and must be tnitfslated from 90 column
card code to UNIVAC 1050 XS 3 code. The translation table is in Row 10 (locations
640-703). The first in~truction places the row number in TRO.
\~
~7
LABEL
11
•
-
-- -
F L D 1 ,
FLDI (before)
. 90 column equivalent
=
=
Decimal value
40
45:46
I
T R0 , T 0
S C
T R
30
18 19
13
lJ
OPERANDS
OPERATION
I
I
- - --
3
I
-
-
I
---
I
\
I .(
->
010101 010100 100010
A
B
C
21
20
34
()
Character position
Row 10
20
21
(010101) (010100) .
1050 equivalent
FLDI (after)
1050 equivalent
A
B
=
34
. (010110) .
C
010100 010101 010110
A
B
C
C·'
.
,
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
c
CENTRAL PRDCESSDR
3.6.2.
63
3
SECTION:
PAQE:
EDIT
Format:
ED M, L,X
Function:
Edit the L least significant characters of arithmetic register 1 into
the store positions whose least significant character is Mx under
control of the pattern in AR2.
Notes:
a.
The maximum value of L plus E is 16. *
b.
The edit instruction facilitates the following operations on a data field
•
elimination of the sign bit
•
translation of the sign to a form suitable for printing
•
insertion of punctuation (any alphanumeric character except @) in the data field:
c.
Data in ARI is placed in the designated storage, in character positions that
correspond to the location of the @ and J::( characters in AR2.
d.
If the least significant character in AR2 is
(.~
- a minus sign (000010), two functions will be performed:
J::(
•
if the field in ARI is negative, a minus sign is placed in
positive, a blank is pl,aced in Mx'
•
the least significant character in ARI is transferred to
are placed in the zone bits.
Mx;
~-1
if the field is
and binary, zeros
a lozenge (111111), the numeric bits of the least significant character of ARI are
copied in to location Mx ' and binary zer os are placed in the zone bits of ~.
@ an "at" character (100000), the least significant character of ARI is copied into
Mx without alteration.
Any other character appearing in the least significant character position of AR2 is
transferred to location ~ unaltered.
e.
Except as noted in note d, any character in AR 2, other than an @, is transferred
unaltered to a corresponding position in the designated storage area; an @causes
the corresponding character in ARt to be transferred to the designated storage area
unaltered.
f.
The number of @characters in AR2 must be at least equal to the number of characters
specified by L.
• E
=
number of characters inRerted into the edited field.
UNIVAC 1050 SYSTEMS
UP-39l2
Rev. 1
, 64
3
CENTRAL PROCESSOR
SECTION',
PACilE,
o
Examples:
•
Edit the 10 least significant characters of ARl according to the pattern contained in AR2, placing the edited field in the locations whose least significant
character is labeled TOTAL.
30
6
ED
I
I
.....
- ---
TOT A LJ
_/'" L....---I
ARl = I 0 I 0 I 0 I 0
10
I0
11 12 13 14
I
40
-
11 0
I @ I @ 1 @I ' I @I @1 @I '
AR2 = I
:~
OPERANDS
L7 LABEL 11 ,,3OPERATION18 19
I
I5
16 17
Is
1 @I @1 @1 .
191
I
1
-
-
-- t
}
45!461
I
I
)
,I
---."
I
I @ I @ I-I
After the instruction is executed, the field labeled TOTAL contains
o
Character position TOTAL is blank because the field is positive. If it were negative, TOTAL would contain
•
Edit the 8 least significant characters of AR1 according to the pattern in AR2 and
store the edited field in the field labeled TOTAL.
I
--
.OPERANDS
OPERATION
\6 7 LABEL 11
18 19
13
ED
I
....
-
I
I
30
TOT A L
--
AR1 = I 0
1
AR2 = I 0
10
0 I 0 I 0
I0
II \ )
.
8
------10 10 1 0
1 @ 1@ 1 '
I0
40
1 -'
-
,.L i
i
-
\3 14 [5 16 17
I @ I @ I @ I,
Is
I@ \ @ I @ \.
-
I
J
19 I 0
45 146
-
I
I
...
)
I
I
I
J
I
\ @ \@ I
After the instruction is executed, TOTAL will contain
r
...---r'1
X I--'--x
1 x--'--I
3 .,..--r14I---r-s
I -'--1
6 "'---'1
I --'-.
19 """""""1
! I
7 I---r-s
TOTAL
o
I.
I~
UNIVAC 1050 SYSTEMS
UP-3912
c
SECTION:
PAGE:
because the minus sign appears in the zone bits of the least significant
character in AR1, the least significant @character in AR2 acts as a J:t and the
zone bits are not transferred. (If the zone bits were to be transferred the result
would be the 1050 character for the exclamation point.)
•
,~
~
~
LABEL
Edit the 8 least significant characters of AR1 according to the pattern in AR2
and store the edited field in the field labeled TOTAL.
11 ,13
7
--
OPERANDS
OPERATION
TOTAL,
40
I
-
I
-
0
0
0
0
0
0
0 \3
T
T
0
A
L
After the instruction is executed, TOTAL will contain
1314151, 16171 s 1 ·19 10 1*
I
~
I I I I I I I I \4 15 16 17 Is 19 16 I
I @\ @I@I, I @I@ I @I . I @ I@·I* I I I I I I
0
45 146
I
8
-
AR2
:I 0)
30
18 19
E 0
ARl
c
65
3-B
CENTRAL PRDCESSDR
I
T
10
1
T IA IL I
--..---,----~------~~
UNIVAC 1050 SYSTEMS
3-B
SECTI~9N:
UP-3912
CENTRALPRDCESSa·R
66
PAGE:
i
I
o
ZERO SUPPRESS...., ZS M, L, X
ZS$ M, L, X
ZS* M, L, X
Function:
Beginning at location Mj{ and working to the right on a maximum of L
characters, replace blanks, zeros, and commas until a character which
is neither a blank, a zero, nor a comma is encountered.
Notes:
a.
In this' instruction, Mx specifies the most significant character position of the
field, as the instruction operates on the field from left to right.
b.
The maximum value of L is 16.
c. A ZS instruction replaces all leading blanks, zeros, and commas with blanks.
d.
A ZS$ instruction replaces all leading blanks, zeros, and commas with blanks,
and inserts a dollar sign ($) in the position immediately to the left of the first
character encountered which is neither a blank, a zero, nor a comma.
e.
A ZS* instruction replaces 'all leading blanks, zeros, and commas with
asterisks (*).
f.
A count (from 0 to 16), expressed in binary, of the number of characters suppressed
is stored by the circuitry in ZCT (absolute location 73).
g. If Mx is not a blank, a zero, or a comma, and'a ZS$ instruction is executed, a
dollar sign is inserted into Mx-I.
Example:
Suppress leading zeros, commas, and blanks in the field whose most significant
character is labeled TOTAL-IS.
TOTAL-IS through TOTAL
=
I 0 I ' I0
11 12
I ' 13 14 Is
1 ' 16171
s1 ·19 f 0 I
If the instruction is
E
~
LABEL
11 ,13
6 7
ZS
18 19
- --
~
.. - .•..
~.~-
..
-~
:~
OPERANDS
OPERATION
TOTAL-15 ,
~-----
. . . . . . . --.--~~------~---~------
30
13I
-
45!~
40
l
I
I
I
-
I
II
I
-
c
67
3
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
CENTRAL PROCESSOR
SECTION:
PAGE:
a!ter the instruction is executed, the field TOTAL -15 through TOTAL would contain
TOTAL -15 ]
TOTAL
If the instruction is
~6 7
11
j
OPERANDS
OPERATION
LABEL
Z S ,$
.-L
--
-
30
18 19
13
---
TOT A ,L - 115 '
1 31
-- -
-
: ki(
45 146
40
I
I
I
- -- -
-
_I
the field would contain
11\$\i\2\,\3\4\5\,\6\7\8\'\9\01
TOTAL -15
L
j
TOTAL
If the instruction is
~~ 7
LABEL
OPERATION
11
l-L
18 19
13
Z,S
-
OPERANDS
*
•
l\
30
T,O T,A L _,1.5 ,
- -
1
40
~I
.
I
~
-./
45,..;
1
-
the field would contain
TOTAL-IS
In all three cases, ZCT would contain a 3 expressed in binary (000011) .
o
I
!
1
I
UP-3912
Rev. 1
UNIVAC 1050 SYSTEMS
3.6.4.
I'ECTION:
PAGEl
o
PAD BLANKS
PD
Format:
3.6.5.
68
3
CENTRAL PRDCESSDR
M, L, X
PAD ZEROS
Format:
PDO M, L, X
Function:
Place decimal zeros (000011) or blanks (000000), as indicated by the
operation code, in the L locations whose least significant character
is at Mx'
Notes:
a.
The arithmetic registers are not involved in the operation of this instruction,
unless Mx is the address of a location in either arithmetic register.
b.
The maximum value of L is 16.
Example:
Place blanks in the 16 character field whose least significant character position
is labeled TOTAL.
T
LABEL
7
11
--
PD
~"---
-
TOT AL (before)
TOTAL (after)
II \-)
OPERANDS
OPERATION
,18 19
13
30
TOT A L
1 6
I
-
45!~
40
I
-
--
I
I
-
I
-~
I* I~ 1* 11121,1314151,1617181.1910 I
1
,,'
'I
"
1
I"
,
1
,
,
I ,
I
I
I
I
UNIVAC 10150 SYSTEMS
UP-3912
SECTION:
LOGICAL SUM - LS M, C, X
Function:
For every bit position in C containing a one, place a one in the
corresponding bit position in Mx'
Notes:
a. The bit positions of Mx which correspond to those bit positions of C containing
o bits are unchanged.
b.
C is not altered after the instruction is executed.
Example:
Superimpose the character 110000 on the characters IND1, IND2,and IND3.
LABEL
OPERATION
6711
13
1819
LS
IND1 (before)
IND1 (after)
001111
111111
IND2 (before)
IND2 (after)
000011
110011
IND3 (before)
IND3 (after)
,=
100011
110011
69
3-B
CENTRAL PROCESSOR
OPERANDS
30
PAGE.
,
UNIVAC 1050 SYSIEMS
SECTION:
~
"CENTR-AL -PROCESSOR
70
3-B
PAGE,
C '
,'J
LOGICAL PRODUCT - LP M, C, X
Function:
For every bit position in C containing a zero, place a zero in the
corresponding bit pos·ition in Mx'
Notes:
a.
The bit positions of Mx which correspond to those bit positions of C containing
1 bits are unchanged.
b.
C is not altered after the instruction is executed.
Example:
Extract the three least significant bit positions of the characters IND4, INDS, and
IND6. (C must be 111000.)
~ LABEL
~7
' 11
6
13
:~
OPERANDS
OPERATIOjq
I
30
18 19
40
I
LP
I ND4
o7
0
I
I
I
LP
I ND5
07
O~
I
I
I
LP
I ND6
o7
0
I
l
,..~--
}
45 146J
I
- -
IND4 (before)
IND4 (after)
111111
111000
INDS (before)
INDS (after)
101101
101000
IND6(before)
IND6 (after)
001011
001000
-'-
- -
- --
L
c
I
--!..-
c
UNIVAC 10150 SYSTEMS
UP-3912
Rev. 1
c
3
CENTRAL PRDCESSDR
3.6.8.
71
SECTION:
PAGE:
BIT SHIFT
Format:
BSn M, S, X
Function:
Shift the n characters whose least significant location is Mx ' S bit
positions left, replacing the S least significant bit positions of Mx
with binary zeros. Note that this instruction is a hit shift involving
an integral number of characters.
Notes:
a.
n may he 1, 2, 3, or 4, specifying the number of six bit characters involved in
the shift.
b.
S specifies the number of bit positions that the field is to be shifted left. A
maximum shift of 7 is possible.
c. Bits shifted beyond the most significant bit position of the most signficant
character are lost.
d.
Zeros replace the hits shifted out of the least significant bit positions of the
least significant character(s).
Example:
Shift the two character field, DATA3, 3 bit positions left.
~
~7
LABEL
11
,
L.~
18 19
13
B S2
-L...-
-
-
30
D A,T A 3 •
~
3
45 1
40
I
-
DATA3-1 through DATA3 (before) = 110101 001111
DATA3-1 through DATA3 (after) = 101001 111000
c
I)
OPERANDS
OPERATION
-
I
-
I
I
- -
I
I
CENTRAL PRDCESSDR
3.6.9.
72
3
UNIVAC 1050 SYSTEMS
UP-3912
Rev. 1
SECTION.
PAGE,
o
BIT CIRCULATE
Format:
BCn M, S, X
Function:
Shift the n characters whose least significant location is Mx' S bit
positions left. The Smost significant bits are moved into the S least
significant bit positions of Mx' Note that this instruction is a bit
shift involving an integral number of characters.
Notes:
a.
n may be 1, 2, 3, or 4, specifying the number of six bit characters involved in
the shift.
b.
S specifies the number of bit positions that the field is to be shifted left. A
maximum shift of 7 is possible.
c.
Bits shifted beyond the most significant bit position of the most significant
character are entered into the least significant bit positions of the least
significant character(s).
Example:
Shift the three character field, DATA4, 5 bit positions left, circularly.
L
,7
11
-B C 3
3~
....
13
-
.;....
:~
OPERANDS
OPERATION
LABEL
I
30
18 19
D A T A.4
5
-
I
-
461
40
-
I
I
DATA4-2 through DATA4 (before) = 100110 110101 001111
DA TA4-2 through DATA4 (after)
= 011010 100111 110011
I
45 1
I
-
I
I
I
J
I
UP-3912
Rev, 1
UNIVAC 1050 SYSTEMS
3
CENTRAL PROCESSOR
PAGE
NO'S,
MNEM OPERANDS
CODE
3-14
BOa
-16
-6
TIMES IN MICROSECONDS
INSTRUCTION
M, L, x
BRING DECIMAL
36 + 9L
BAa
M, L, X
BRING ALPHANUMERIC
27 + 9L
BT
M, T, X
BRING TETRAD
63
M, L, X
STORE ARITHMETIC REG,
27 + 9L
STORE BOTH ARITHMETIC
REGISTERS
324
63
_17
c.:
SAo
-17
W
II-
SAR
M
Z
-C
ST
M, T. X
STORE TETRAD
_18
I-
SC
M, C, X
STORE CHARACTER
40,5
-10
-C
FT
M, T, X
FIX TETRAD
81
-C
TFI
M , ,X*
TRANSFER BLOCK FROM
STORE, INCREMENT
II)
c.:
I-20
Q
X
"
R:~~~~~RBELS~;'K
FROM
103.5+ 9B
90+ 9B
-20
TFR
M, , X *
-22
TTl
M
Xt
TR;~~~~~I~~~~~ETNOT
103.5
-22
TTR
M
xt
TRANSFER BLOCK TO
STORE, RESET
90+ 9B
3-26
ADa
M, L, X
ADD DECIMAL
49.5+ 13.5 (L+ Lc); if IMxl
-38
ABa
M, L, X
ADD BINARY
27+ 13,5L
-29
-7
-40
-28
-39
-31
+ 9B
>
AMa
M, L, X
ADD TO MEMORY
49.5+ 13.5; if IARal
~
AT
M, T, X
ADD TO TETRAD
81
W
AC
M, C, X
ADD CHARACTER
45+ 13.5Le
SDa
M, L, X
SUBTRACT DECIMAL
49.5+ 13.5 (L+ Lc); if
SBa
M, L, X
SUBTRACT BINARY
27+ 13.5L
I~
:z::
!::
c.:
-C
> IAR~
IMxl
IMJ
>
>
IARaI
SMa
M, L, X
SUBTRACT FROM MEMORY
49.5+ 13.5L; if
-32
MPN
L
MULTIPLY NON-CUMULAT,
L (33.75K+63.5) +99
-34
MPC
L
MULTIPLY CUMULATIVE
L (33.75K+63.5) +27
-36
DV
L
DIVIDE
L (74.25K+ 128.25) + 13.5K+49.5
3-44
Z
CDa
M, L, X
COMPARE DECIMAL
36+ 13.5L'; if
!!!
c.:
CBa
M, L, X
COMPARE BINARY
27+ 13.5L
0
46
-47
-9
-48
-C
CC
M, C, X
COMPARE CHARACTER
40.5
~
CT
M, T, X
COMPARE TETRAD
81
U
LC
M. C, X
LOGICAL COMPARE
40.'
JE
M, X
JUMP EQUAL
31.5
a..
0
3-51
-51
JG
M, X
JUMP GREATER
,31.5
c.:
JS
M, X
JUMP SMALLER
31.5
Z
JU
M, X
JUMP UNEQUAL
31.5
U
J
M, X
JUMP
31.5
U
JC
M, I, X
JUMP CONDITIONAL
31.5
W
JL
M, N, X
JUMI;' LOOP
40.5
JR
M, I, X
JUMP RETURN
45
JD
M, X
JUMP DISPLAY
31.5
.J
0
-51
··51
-51
-54
IMxt
t.
49.5+ 31 L
and signs
and signs
=,
=,
49.5+27L
49.5+31L
36
I-
0
W
Z
-59
t.
IARal
and signs~, 49.5+27L
and signs
:::l
-56
a
W
-53
II)
-53
:3 -72
-71
M, X
HALT, THEN JUMP
BCn
M, S, X
BIT CIRCULATE
40.5+S (9+ 18n)
IIL
:z::
BSn
M, S, X
BIT SHIFT
40.5 + S (9+ 18n)
3-69
LS
M, C, X
LOGICAL SUM
40.5
-70
LP
M, C, X
LOGICAL PRODUCT
40,5
-68
PO
M, L, X
PAD BLANKS
27+4.5L
PDO
M, L, X
PAD ZEROS
27 + 4.5L
ZS
M, L,Xt
45+ 9Z
ZS$
M, L,Xt
-66
ZS*
M, L,X *
ZERO SUPPRESS
ZERO SUPPRESS AND
FLOATING $ SIGN
ZERO SUPPRESS WITH
ASTERISK FILL
-63
ED
M, L, X
EDIT
36+ 13.5L+ 9E
-61
TR
M, L, X
TRANSLATE
36+ 13.5L
on
-68
I-66
-66
c
JHJ
31.5
Q
W
XF INSTRUCTION TIME IS 72 MICROSECONDS.
B = NUMBER OF CHARACTERS TRANSFERRED
E = NUMBER OF CHARACTERS INSERTED INTO
EDITED FIELD
K = DIVISOR OR MULTIPLICAND LENGTH
L
L
= OPERAND LENGTH OR LENGTH OF QUOTIENT
= LENGTH OF THE LONGER OF TWO FIELDS
Table 3-4,
49,5+ 9Z
45+ 9Z
Lc
= CARRIES
BEYOND L lH DIGIT
IMxl= ABSOLU'TE VALUE OF Mx
N
= NUMBER OF CHARACTERS SHIFTED
5
= BIT POSITIONS SHIFTED
=NUMBER OF CHARACTERS
Instruction Execution Times
73
PAGE:
APPROXIMATE INSTRUCTION EXECUTION
TYPE
-6
SECTION:
SUPPRESSED
c,·.·,
I
:
o
UP-3912
Rev. 1
UNIVAC 10150 SYSTEMS
CENTRAL PRDCESSDR
4
SECTION.
1
PAGE:
4. AUTOMATIC PROGRAM INTERRUPT
4.1. General Description
Automatic program interrupt is a concept incorporated into the control circuitry of the UNIVAC
1050 System which enables the system to operate at optimum overall efficiency. The automatic
program interrupt feature permits the efficient utilization of all input/output devices operating under
control of the Central Processor without sacrificing any processing time within the program cyclean essential consideration in the maintenance of maximum input/output speeds.
Basically, automatic program interrupt consists of the generation of a signal to the Central Processor upon the recognition of a condition that require.s immediate attention from the program. These
interrupt signals are assigned a priority within a hierarchy of interrupts in order to facilitate their
processing.
Associated with automatic program interrupt is interrupt inhibit, which prevents the acceptance of
an interrupt signal when it is generated. However, the interrupt signal is stored in an indicator
that can be tested subsequently by a program instruction.
Interrupt results from one of two general classes of occurrences: first, an error, fault, or emergency
condition occurring either in the Central Processor or in an input/output device; and, second, successful completion of an input/output function or, in some cases, when an input/output device is
ready to accept an input/output command.
Upon the occurrence of an interrupt, and if interrupt has not been inhibited, control is transferred
to one of ten fixed store locations which must contain the starting address of a routine that processes the interrupt.
Programs that use the PAL Assembler library of input/output routines supplied by UNIVAC are
relieved from the burden of controlling and coordinating interrupts since comprehensive interrupt
coding is included in these routines.
For the benefit of the programmer who wishes to write his own input/output and interrupt coordinating routines, the following subsection presents the considerations attendant upon interrupt
programming.
4.2. Programming Considerations
4.2.1. Classes of Interrupt
There are three classes of interrupt which are named in the order of their priority: Class I,
Class II, and Class III.
When a Class I interrupt occurs, a Class I Interrupt Inhibit bit is set automatically. While this
bit is set, the processing (but not the storage) of all subsequent interrupts is prohibited. If a
Class I interrupt occurs while the Class I Interupt Inhibit bit is set, the Central Processor stalls.
When a Class II interrupt occurs, a Class II Interrupt Inhibit bit is set automatically. While this
bit is set, the processing (but not the storage) of subsequent Class II and Class III interrupts
is prohibited. A Class I interrupt, however, will be processed in spite of the inhibition of Class
II interrupts.
UNIVAC 10150 SYSTEMS
UP-3912
Rev. 1
CENTRAL PROCESSOR
2
4
SECTION.
PAGE.
When a Class III interrupt occurs, a Class III Interrupt Inhibit bit is set automatically. While thiO'
'.
bit is set, the processing (but not the storage) of subsequent Class III inteuupts is prohibited.' .
Class I and Class II interrupts" however, will be processed in spite of the inhibition of Class
III interrupts.
4.2.1.1.
Class I Interrupt
A Class I interrupt occurs upon the recognition of a main store parity error when the control
circuits of the Central Processor obtain and execute instructions. Such an error is known as
an internal parity error. Parity errors occurring while input/output devices are accessing
main store are excluded from this definition.
4.2.1.2.
Class II Interrupt
A Class II interrupt is caused by either
4.2.1.3.
•
decimal overflow or improper division, both of which set the Decimal Overflow Indicator
(Indicator 40), or
•
the depression of the Operator Request Switch on the console, which sets the Operator
Interrupt Indicator (Indicator 44).
Class III Interrupt
A Class III interrupt is generated by the Synchronizers associated with the input/output
devices of the UNIVAC 1050 System upon the occurrence of any of the following:
•
Successful completion of an input/output function, which may result from
- the normal termination of a requested input/output function without detected errors, or
- an interrupt request from a demand device without detected errors. A demand device is one
that is expected to generate an interrupt request at fixed time intervals whether or not
an instruction has been issued to it.
•
Error conditions when
- normal termination of a requested input/output function is accompanied by the detection
of an error or errors; or
- an error occurs while an input/output function is in progress which will prevent normal
termination.
•
Off normal conditions resulting from
- the issuance of an input/output instruction to a device that has not completed a previously requested operation;
- the detection of an error or fault condition in a device that is not in use; or
- the existence of a condition whereby the acceptance of the instruction would violate
the rules governing the simultaneous use of input/output channels - a condition known
as Storage Overload. The purpose of these rules is to prevent the occurrence of an
input/output data transfer rate that exceeds the main store data transfer rate.
0
-~~-----------------------------
UNIVAC 10150 SYSTEMS
UP-3912
Rev. 1
c
CENTRAL PROCESSOR
4
SECTION.
3
PAGE.
When an instruction requests an off normal device, an interrupt request is generated and the
instruction is disregarded.
4.2.2. Programmed Interrupt Inhibit
Class II and Class III interrupts may be inhibited by program instruction. The following rules
govern programmed interrupt inhibit.
•
Operator Interrupt may be inhibited by instruction. Such inhibit can only be released by
instruction or by the depression of the CLEAR button on the console.
•
Decimal Overflow Interrupt may be inhibited by instruction. Such inhibit can only be
released by instruction.
•
Setting of a programmed Decimal Overflow Interrupt Inhibit sets an indicator (Indicator
47), which may be tested by a program instruction.
•
Class III Interrupt from all input/output channels may be inhibited by instruction. Such
inhibit can only be released by program instruction. Setting the Class III Interrupt Inhibit sets Indicator 45, which may be tested by a program instruction. This inhibits all
Class III Interrupts.
This general Class III interrupt inhibit is distinct from the channel interrupt inhibit specifiable
in an XF instruction which inhibits further interrupts only from the ~pecified channel and
which is released by a subsequent XF instruction to that channel. *
c\
The setting and resetting of programmed interrupt inhibit does not affect, nor is affected by,
any other class of interrupt.
4.2.3. Instructions Associated with Interrupt Control
The Jump Conditional and Jump Return instructions are used to control the processing of
interrupts of all classes. Table 4-1 lists all the indicators; those associated with interrupts
and used by the Jump Conditional and Jump Return instructions are marked with a dagger.
4.2.4.
Fixed Interrupt Locations
Associated with each class of interrupt, and with each input/output channel on the UNIVAC
1050 System, is a group of eight consecutive character positions through which communication
with the interrupt routines is maintained. The foldout Figure 3-1 on page 3-2 shows the
location of these fixed interrupt addresses.
*
The XF instrucUon will be tully explained in the applicable 1050 peripheral subsystem manual.
UP-3912
Rev. 1
UNIVAC 1050 SYSTEMS
CENTRAL PRDCESSDR
4
SECTION.
4
PAGE.
The indicators in the table below are divided into two groups: testable and nontestable. The nontestable indicators (00-31) cause a certain function to be performed and an unconditional jump. The
conditional jump indicators (32-63) are tested and cause a jump only if the indicator has been set.
32-63 Conditional Jump
00-31 Unconditional Jump to M Address
00
§ 14
§I5
16
17
18
19
20
21
22
23
24
t*25
t 26
t 27
t28
t*29
t*30
t 31
0
Unconditional Jump
Release Operator Interrupt Inhibit and jump
Set Operator Interrupt Inhibit and jump
Stop, Jump when Console Restart
Button is depressed
Set Tracing Stall and Jump
Set Sense Indicator 1 to 1 and jump
Set Sense Indicator 2 to 1 and jump
Set Sense Indicator 3 to 1 and jump
Set Sense Indicator 1 to 0 and jump
Set Sense Indicator 2 to 0 and jump
Set Sense Indicator 3 to 0 and jump
Unconditional Jump
Release Class 3 Interrupt Inhibit and jump
Set 1/0 Interrupt Inhibit and jump (Class 3)
ReleaS1! 1/0 Interrupt Inhibit and jump
(Class 3) (Resets Programmed Inhibit Only)
Set Decimal Overflow Interrupt Inhibit and
jump (Class 2)
Release Class 2 Interrupt Inhibit and jump
Release Processor Parity or Abnormal
Interrupt Inhibit and jump (Class 1)
Release Decimal Overflow Interrupt Inhibit
and jump (Class 2), (Resets Programmed
Inhibit Only)
*RESETS the inhibit automatically generated when the
interrupt occurred.
tSee Section 4.2.3.
§Also inquiry typewriter, if preset.
Table 4-1.
Exceptions to conditional jump are 32, 41, 42, 48, and 56.
The status of the indicators is unaltered by the JC and JR
instructions except as shown.
32 (KNO)
33 (KHI )
34 (KEQ)
35 (KUQ)
36 (KLO)
37 (KZR)
38 (KM)
NOOP
High
These four indi cators are affected
Equal
by the comparison instructions:
Unequal
CC, LC, CD, CB, CT.
Low
Result of last arithmetic operation was zero
Result of last decimal arithmetic operation
was negative.
39 (KN B) No overflow in las"t add binary operation or
overflow did occur in the last binary subtract
operation.
t40(KDF) Decimal Overflow occurre"d since last test.
If the indicator is set to 1, reset iUo 0 and
jump.
t 41
Store Indi cators 33-40 in Mx memory position
and proceed to next instruction
Set Indicators 33-40 from Mx memory position
t 42
and proceed to next instruction
Input-Output status test found indicator(s)
43
set to 1
Test and reset operator interrupt request
t 44
Input-Output Interrupt is inhibited (Class 3)
t 45
46
Test and reset inquiry typewriter request
t 47
Decimal Overflow Interrupt is inhibited
(Class 2)
48
StoplGo to control counter when console
start is depressed, ignore M used for display.
49
Processor Parity and Abnorm~1 Interrupt is
inhibited (Class 1) (Manual Switch Only)
50
Sense Switch 1 on console is ON
51
Sense Switch 2 on console is ON
52
Sense Switch 3 on console is ON
53
Sense Indicator 1 is set (to 1)
54
Sense Indicator 2 is set (to 1)
55
Sense Indicator 3 is set (to 1)
56
Skip (no operation)
57
If Trace Indicator is set to 1, reset Trace
Indi cator and Trace Stall to 0 and jump
t 58
Operator Interrupt is inhibited
Indicator List
C)
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The format of each eight character group is as follows:
".J'
Character
1
2
3
4
5
6
7
8
c=r=-a.,:,"-==r=-:-----------'.':":.:".':,
-----------Control Counter Storage
Address of Interrupt
Routine
When an interrupt occurs, the contents of the control counter are stored in the 15 least signifi·
cant bits of characters 2, 3, and 4; zeros are placed in the three most significant bit positions
of character 2. The 15 least significant bits of characters 6, 7, and 8 are then read into the
control counter. These characters should contain the starting address of the interrupt routine
associated with the particular fixed interrupt locations.
The following sequence of events takes place when an interrupt request is accepted:
a. The instruction currently being executed by the Central Processor is completed. Exception:
When a Class I interrupt occurs, an ending pulse is immediately generated for the instruction
currently being executed.
b. The address of the next instruction in the program being interrupted (contents of the control
counter) is stored in characters 2, 3, and 4 of the fixed locations associated with the channel which initiated the request.
c. The 15 least significant bits of characters 6, 7, and 8 (starting address of the interrupt
routine) are read into the control counter. In addition, a signal is generated which prevents
the Central Processor from accepting additional interrupt requests from channels of the same
or lower classes. This signal persists until an Automatic Interrupt Inhibit Release instruction for this class is executed.
d. The Central Processor does not recognize additional interrupt requests of any kind during
the time required to execute steps 2 and 3. Beginning with the completion of step 3, interrupt
requests from higher classes will be accepted.
Control is returned to the interrupted program by means of the address stored in characters
2, 3, and 4. Char~cter 1 should contain the operation code for a JC instruction, and character
5 should contain the indicator releasing the automatic class interrupt inhibit for the class with
which this channel is associated.
With the exception of characters 2, 3, and 4 of the area, the area must be preset by the initializing subroutine of each program.
It should be noted that Class I and Class II interrupts each have a single fixed interrupt area.
It is a function of the Class II interrupt routine to determine whether the interrupt was caused
by decimal overflow or by an operator interrupt request.
o
Class III interrupts have eight fixed interrupt areas, one for each input/output channel. Fixed
priorities within the class are assigned to each channel to avoid conflict by simultaneous
interrupt reques ts. Once an interrupt request has been accepted, however, it cannot be interrupted by another request from a channel of higher priority within the same class until an instruction releasing the Automatic Class III Interrupt Inhibit has been executed.
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5.
CENTRAL PROCESSOR
CONSOLE OPERATION
The Central Processor Console provides a communication link between the Central Processor
and the operator. The console contains display indicators that allow the operator to determine
normal and abnormal conditions, and to access registers and selected positions in main storage. In addition, the console contains switches that allow the operator to correct or override
error conditions, debug programs online, and manually set sense switches for program use.
5.1. NORMAL OPERA TION
5.1.1. Start Up and Shut Down
The first operation necessary is that of turning the UNIVAC 1050 System on and shutting the
system off. Two buttons are used for system start-up and close-down, SYSTEM ON and SYSTEM
OFF.
•
Depressing the SYSTEM ON button turns power on, the SYSTEM ON button will light. When
the system is at full operating power, the SYSTEM OFF button will be extinguished.
•
Depressing the SYSTEM OFF button removes power from the peripheral units and the Central
Processor in an orderly fashion. While this power removal sequence is being completed, both
the SYSTEM ON and SYSTEM OFF buttons will be lit. After completion, the SYSTEM ON
button will be extinguished.
5.1.2. Program Start and Program Stop
Depression of the PROGRAM START button will illuminate the PROGRAM START button, extinguish the PARITY error indicator, and PROGRAM STOP button; and will permit the processor
to proceed under control of the mode buttons.
Depression of the PROGRAM STOP button, or a programmed halt, will illuminate the PROGRAM
STOP button and extinguish the PROGRAM START button. The processor will halt after completing the instruction in progress. Input/Output orders in progress will be completed; interrupt
requests will be stored, unless inhibited.
If neither the PROGRAM START button nor the PROGRAM STOP button is lit, the processor is
in a stall condition.
5.1.3. Operating Mode
The six mutually exclusive mode control switches are used to control the operation of the
processor in conjunction with the PROGRAM START button.
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5.2. PANEL CONTROLS AND INDICATORS
a. Switch/Indicators
All Switch/Indicators Are Momentary Action Switches.
DESIGNATION
DESCRIPTION
I
I
I
SYSTEM
ON
I
Turns system on.
Lights when depressed; extinguishes when SYSTEM OFF indicator is depressed.
I
I'
(Green)
I
SYSTEM
OFF
I
I
Turns system off.
Lights when depressed; extinguishes when SYSTEM ON switch is depressed.
(Red)
I
CLEAR
(White)
I
General clear of testable indicators, counters, and stored interrupts; and initiates a
console lamp test.
Lights when depressed; extinguishes when released.
I
PROC
ABNORMAL
I
(Red)
I
PARITY
(Yellow)
I
CLASS III
INHIBITED
I
OVERFLOW
INHIBITED
I
I
(Yellow)
I
(Yellow)
Lights when a second parity error is recognized and a previous parity error has not
been cleared. Depressing this button when illuminated turns it off, but does not
clear the parity error. May also be on due to maintenance operations.
Indicator only.
Lights when a parity error is detected in a character read from storage. Parity errors
cause an immediate processor halt. (See Section 5.3.4 on how to clear a parity error).
o
Indicator only.
Lights when a Class III Interrupt Inhibit is stored; extinguishes when the inhibit is
released by the program.
Indicator only.
Lights when a Decimal Overflow Interrupt Inhibit is set.
Extinguishes when the inhibit is cleared by the program.
Lights when fault develops in corresponding 110 channel.
CHANNEL
ABNORMAL
Extinguish by clearing error at peripheral unit and then depressing switch.
0-7
(8 Red)
Lights when depressed; extinguishes when depressed again.
SENSE
123
Used in conjunction with programmed tests and program operating instructions.
(3 White)
I
OPERATOR
REQUEST
(White)
1
Lights under program control.
Can be depressed when illuminated to stop program by causing a Class II interrupt.
Depressing the OPERATOR REQUEST button when extinguished has no effect.
Table 5-7. Control Console Switch and Indicator Description
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DESCRIPTION
NEXT
INSTRUCTION
I
M
I
(White)
Directs processor to M portion of the current instruction.
Lights when depressed or under program control; control is transferred to the M
portion of the current instruction.
Extinguishes when CC switch is depressed or under program control.
I
CC
(White)
I
Forces the processor to obtain the next instruction from the address in the control
counter; that is, it overrides a jump instruction.
Lights when depressed or under program control.
Extinguishes when M switch is depressed or under program control. Either the M or
the CC button will always be illuminated.
Note:
I
PROGRAM
START
I
PROGRAM
STOP
J
DISPLAY
(White)
operation in the continuous mode, the Next Instruction switch/indicator will light accordin~ to the instruction sequence and dependin~ on the
result of pro~rammed tests and comparisons. Consequently, these buttons
should not be depressed durin~ continuous operations. Doin~ so could force
an incorrect instruction sequence.
Depressing when extinguished initiates execution of program under control of Mode
switches. This indicator may flash on and off rapidly during the execution of a
long instruction, but this should be ignored unless light stays off for longer than
a few seconds.
I
Lights when depressed or when program stops.
Extinguishes when PROGRAM START switch is depressed. When both PROGRAM
START and PROGRAM STOP buttons extinguish and will not illuminate, processor
is stalled. Depress ONE INST Mode and PROGRAM START buttons.
I
When depressed causes the contents of the storage location represented in the M
portion of the Display/Alter switches to be displayed in lights in the C portion.
(Red)
I
Durin~
Lights when depressed.
(Green)
Lights when depressed.
Extinguishes when released.
I
ALTER
(White)
I
When depressed causes the character represented by the setting of the C alter
switches to be stored into the address specified in the M portion of the Display/
Alter switches.
Lights when depressed.
Extinguishes when released.
Table 5-1. Control Console Switch and Indicator Descriptions (continued)
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b. Illuminating Pushbuttons
,
,.
Depress To Set; Depress To Release; Lights When Depressed.
DESIGNA TION
DESCRIPTION
The MODE push buttons operate one at a time. One of these buttons must be i Iluminated at all times.
MODE
LOAD
CARD
When depressed and illuminated, depressing the PROGRAM START button causes one
card to be read from the reader into octal location 400. Depressing PROGRAM START
again, with the CONTinuous mode button depressed, causes control to be transferred
to octal location 400, when UNIVAC standard code cards are used.
LOAD
TAPE
When depressed and illuminated, depressing the PROGRAM START button will cause
one block of tape to be read from logical tape unit 0 into storage starting at octal location 400. Changing to the continuous mode and depressing PROGRAM START immediately after, will transfer control to this location.
ONE
CYCLE
When depressed and illuminated, depress ing the PROGRAM START button wi II cause
instructions to be executed one instruction cycle at a time. This mode is generally
used by UNIVAC Field Engineering personnel only.
ONE
INSTR.
When depressed and illuminated, depressing the PROGRAM START button will cause
one instruction to be executed and the next instruction accessed.
CONT
DISPLAY/AL TER
SELECTION
Ql
Q2
.
When set and the PROGRAM START switch is depressed, a program will run in the
normally used continuous mode.
o
In order to display or alter the contents of storage the Display/Alter Selection buttons
are used in conjunction with the display lights and alter switches. The functions of
the Display/Alter Selection buttons are as follows:
When set, these buttons display internal registers and indicators on the control console. They are primarily for UNIVAC Field Engineering use.
CC
When set, the contents of the control counter are displayed in the M portion of the display lights.
INST.
When set, the contents of the instruction register (the next instruction to be executed)
are displayed in the 30 display lights.
.
OP/CH
When set, the entire instruction is displayed but only the operation code and. the channel (index register) designation portions of the instruction register are alterable.
M
When set, the entire instruction is displayed but only the operand address (M portion)
of the instruction register is alterable.
C
When set, the entire instruction register is displayed but only the C portion (detail
field) of the instruction register is alterable.
MEM
When set, it causes the contents of the storage location specified by the Malter
switches to be displayed when the DISPLAY switch is depressed, and altered when
the ALTER switch is depressed.
SEQ
When set, it is used in conjunction with the ALTER or DISPLAY switch to display or
alter the contents of sequential memory locations.
TobIe 5.1. Control Console Switch and Indicator Descriptions (continued)
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DESIGNATION
TRACE
MODE
DESCRIPTION
SWitches OP, CC, PROC, WRITE, and I/O operate one at a time; TRACE STOP may
be used with anyone of the five Trace Mode switches. If TRACE STOP is not used,
a program testable indicator is set.
OP
When set with TRACE STOP, the computer will stop when the program operation code
matches the settings of the five most-significant-digit alter switches (OP portion of
the top row of indicators).
CC
When set with TRACE STOP, the computer will stop when the contents of the control
counter match the settings of the Trace Address switches.
PROC
When set with TRACE STOP, the computer stops when an operand address matches
the settings of the Trace Address switches.
WRITE
When set with TRACE STOP, the computer stops when a character is to be written
into an address location which matches the settings of the Trace Address switches.
I/O
When set with TRACE STOP, the computer will stop when a control unit reference to
a storage address matches the settings of the Trace Address switches.
TRACE
STOP
When set, the program stops at a specified location if one of Trace Mode switches
is also set.
c. Toggle Switches
ALTER
SWITCHES
Not labeled as such; they are the row of 30 switches immediately below the control
indicators in groups labeled OP, CH, M, and C. They are two-position toggle switches
with up and center positions only: a switch in the up position represents a binary 1;
in the center position, a binary O. A binary pattern can be stored in these switches;
this pattern can then be used to alter the area of the processor that is designated by
th·e Display/Alter election pushbuttons. Alteration occurs only when the DISPLAY
or ALTER switches ar e depressed.
TRACE
ADDRESS
SiXteen three-position toggle switches which correspond to the M portion of the instruction: up represents a binary 1; down represents a binary 0; the center position is
either a 1 or a 0 and will compare with both. For example, a switch pattern of up down
middle will trace either 101 or 100. The trace address positions correspond to parts of
the instruction and are repeatedly compared to the instruction for equality. If equality
is detected and one of the Trace Mode pushbuttons is depressed, an indicator is set;
if the TRACE STOP button is also depressed the program stops.
Table 5-1. Control Console Switch and Indicator Descriptions (continued)
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S N I
y-.{
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d. Rotary Switches
CLASS I
6
5
DESCRIPTION
Three-position rotary switch; used for manual control of Class I interrupts.
Positions are:
S N I -
STALL
NORMAL
INHIBIT
In the STALL position the processor stops each time a parity error is detected. It is
restarted by depressing PROGRAM START. In the NORMAL position interrupt requests are processed through the interrupt entry channel. The processor will not stall
unless another Class I interrupt occurs while in the interrupt mode.
In the INHIBIT position Class I interrupts are ignored. However, it is recommended
that the program stop on a Class I interrupt since recovery without operator intervention is not specified.
OF
S
7
N
Operates same as above but for Class II interrupts: Overflow (0 F), improper division,
operator request.
I
CLASS III
N
Operates same as above but for Class III interrupts.*
o
)--.,.!
I
*
See Section 4 tor a complete description ot Class I, II, and III interrupts.
Table 5-7. Control Console Switch and Indicator Descriptions (continued)
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5.3. PROGRAM DEBUGGING AND TESTING
5.3.1. Use of Display Lights and Switches
The 30 display lights and corresponding toggle switches at the top of the console are a primary
means of communication between the operator and a running program. These lights and switches
must be read as octal numbers. To do this they are interpreted in groups of three binary digits.
A binary digit, or bit, can have a value of either 0 or 1; in this case, an illuminated (on) display
light represents a 1, while an extinguished (off) display light represents a O. Similarly, an octal
digit can have a value from 0 to 7, and any octal digit can be represented by three binary bits.
The bit patterns, or groups of display lights, representing all the octal digits are as follows:
Octal Number
Bit Pattern
0
1
2
3
000
001
010
011
100
101
110
111
4
5
6
7
By interpreting the 30 display lights as 10 groups of three each, any display can be read as 10
octal digits.
The setting of the Display/Alter Select buttons at the middle of the console determi nes what
will be displayed in the 30 lights. Normally, the lNST Display/Alter Select button remains depressed so an entire 30-bit instruction will be displayed. Various portions of the instruction are
delimited by the labels on the console between the display lights and their corresponding
switches. The first five bits on the left comprise the operation code;* the next three bits are the
channel number or index register used, if any; the next sixteen bits specify the storage address
referred to; and the final six bits on the right comprise the detail field of the instruction.
When the computer comes to a programmed display stop, the instruction OP code will always be
30, and the detail field will always be 60 or 20; when the detail is 20 a blank is displayed. The
configuration displayed in the M portion of the instruction is the "message" for that stop, and
~hould be explained in the operating instructions for the run being executed. Display stops are
usually defined only in terms of this M portion; the OP code of 30 and detail of 60 being understood. Consequently, a stop of 3007000160 would probably be written as stop 070001.
5.3.1.1. Display Contents of a Storage Location
a. Set the address of the location to be displayed in the M portion of the alter switches.
b. Depress the MEM Display/Alter Selection button.
c. Depress the DISPLAY button.
d. The contents of the selected storage location will be displayed in the six rightmost display lights (above the C notation on the console), and the address of the location displayed
+1 will appear in the M display lights.
* When
readins the OP code, a siJCth least sisnificant bit, which is always zero, is implied. As a result all
octal OP codes are even numbers.
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If sequential storage locations are to be displayed, the above procedure should be followed
to display the first character. Then, to display subsequent locations
(1)
Depress the SEQ Display/Alter Selection button.
(2)
Depress the DISPLAY button to display the next location.
O'c'}
Every time the DISPLAY button is now depressed, the M address will be increased by one,
and the contents of Location M-l will be displayed in the C lights.
5.3.1.2. Altering the Contents of Storage
a. Depress the MEM Display/Alter Selection button.
b. Set the address of the memory location to be altered in the M alter switches.
c. Set the bit configuration of the character to be stored into this location in the six C alter
switches.
d. Depress the ALTER button.
The procedure for altering sequential locations is analogous to that for displaying them
a. Alter the first location as outlined above.
b. Depress the SEQ Display! Alter Selection button.
c. Set the new bit configuration to be stored in the next character location in the six C alter
switches.
d. Depress the AL TER button.
e. Steps 3 and 4 shouid be repeated until all sequential character locations have been altered.
5.3.1.3. Altering the Next Instruction
To alter the instruction register (as displayed in the lights) the procedure is the same as that
for altering the contents of storage except that the INST, OP/CH, M, or C Display/Alter Selection buttons may be used in place of the MEM and SEQ buttons.
5.3.1.4. Manual Instruction Execution
Although the CONTinuous Mode is the normal operating mode, during program testing it may
occasionally be more desirable to execute one instruction at a time in order to follow the exact path taken in a particular phase of processing. This is accomplished by using the ONE
INSTruction Mode button. When operating in this mode, the INST Display/Alter Selection
button usually remains depressed, but the CC button may also be used to display the contents
of the control counter, thereby determining the location within the program of the instruction
following the one about to be executed.
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With the INST Display/Alter Select button depressed, operation in the one instruction mode
will cause a single instruction to be executed each time the PROGRAM START button is depressed. The instruction displayed is always the next instruction to be executed; a subsequent push of the PROGRAM START button will cause this instruction to be executed and display the next one in the 30 display lights. If the CC Display/ Alter Select button is depressed,
the address of the next instruction in sequence, following the one displayed by pushing the
INST button, will appear in the 16 lights of the M portion of the display. Note that the instruction specified by the address in the control counter is not always the next instruction to be
executed. A jump or conditional jump instruction may cause a different path to be taken.
5.3.1.5. Next Instruction Switches
Depression of the M button inserts binary zeros in the C portion of the instruction "register.
Depression of the CC button, when the processor is stopped, will force a Jump Conditional instruction into the instruction register. The following parts of the instruction word are affected:
a. The operation code is staticized to Jump Conditional.
b. The C portion is changed to a value that initiates the unconditional skip associated with
the Jump Conditional operation code.
When the processor is restarted, the new instruction will be performed. In this manner, any
instruction may be skipped.
If a Jump Conditional or Jump Return instruction is staticized, and the processor is stopped,
depressing the M button will force the processor to take its next instruction from the address
in the M portion. In this manner, any jump instruction may be forced to follow the M path.
Thus, if the M Next Instruction button is illuminated when a Jump Conditional instruction is
being displayed, the condition tested for has been met. The next instruction to be executed is
at the address specified in the M portion of the display lights. If the CC Next Instruction
button is illuminated, the next instruction to be executed is the one following the jump instruction. Its address may be displayed by pushing the CC Display/Alter Select button.
5.3.1.6. Altering Instruction Sequence
The sequence of program instructions may be altered by using the Next Instruction switch/indicators. If a programmed comparison has been made, and the M button light is lit along with
the Jump Conditional instruction display, it may be desirable to see what would happen if the
program would take the other path. This may be done by depressing the CC button to illuminate
it, and depressing the PROGRAM START button to execute the next instruction (which is now
the one specified by the control counter). This procedure does not in any way alter the contents of storage; the next time these instructions are executed, they will be unchanged. Any
instruction (with the exception of Jump Loop, in which the control counter is only incremented
by four instead of five) may be executed manually while the computer is in the one instruction
mode. The following procedure must be followed:
a. Depress the CC Display/ Alter Selection button to obtain the value of the control counter,
if this value must be recorded for later use.
( ~.
./
b. Depress the INST Display/Alter Select button •
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c. Set the bit configuration of the instruction to be executed in the 30 alter switches.
d. Depress the ALTER button. The new instruction will be displayed.
e. Depress the PROGRAM START button.
f. The computer will execute the new instruction and stop. displaying the next instruction to
be executed. The.new contents of the control counter may be displayed by depressing the
CC Display/Alter Selection button. Storage has not been altered; the next time this sequence
of instructions is to be executed, the original instructions will be performed.
5.3.1.7. Tracing
Frequently during program execution, and especially during program testing, it is desirable to
search (Trace) through the running program for a particular instruction, location or operation.
This is accomplished through the Trace Mode buttons and Trace Address switches. The Trace
Mode buttons are used to specify the type of trace being performed. The TRACE STOP button
must be depressed in order to stop the computer if the traced value sought is found. However,
whether or not the TRACE STOP button is depressed, a program-testable indicator is set when
the trace conditions are met. If the trace is on a particular address, the value of that address
must be set in the Trace Address toggle switches. These are three-position switches in which
the down position indicates a 0, the up position indicates a 1, and the middle position can
stand for either one. This latter feature enables tracing on several addresses at once. The
five Trace Mode buttons and their uses are described in section b. of Table 5-1.
5.3.2. Error Indicators
There are two types of Central Processor errors that will cause an interrupt: a Class I interrupt,
which is a parity error in a character read from storage, and a Class II inter11lpt (decimal overflow), caused by improper division or too great a carry in decimal addition.
A Class III interrupt is a normal interrupt of central processor operation that allows for the completion of input/output functions in the peripheral units. This class of interrupt, as well as
Class II decimal overflow interrupt, may be permitted or inhibited by program instructions. If
either type of interrupt is inhibited during a running program, the associated indicator will light.
(During the operation of most programs, these lights may be seen flickering on and off.) All
three classes of interrupt may be inhibited manually by setting the rotary switches at the bottom
of the console to I (inhibit), however this setting is not recommended to anyone except UNIVAC
Field Engineering personnel.
Errors that occur in the peripheral units will be indicated by a red light on the appropriate Channel Abnormal switch/indicator. Each input/output device is assigned one of the Central Processor's eight I/O channels.
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The following are the standard channel assignments:
Channel 0
Channell
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
-
Printer
Card Reader
Card Punch
Communications
Tape Read
Tape Write
FASTRAND
Unassigned
If a red Channel Abnormal light goes on, the operator should check the unites) associated with
that channel for error conditions and clear them before attempting to continue the run. Clearing
the error at the peripheral location will usually cause the error light on the console to go out,
and program operation can be resumed.
All standard UNIVAC 1050 software routines have display stops in them which will occur simultaneously with a channel abnormal error stop to indicate the nature of the problem in the peripheral unit. (For detailed descriptions of these stops, refer to the software routine's operating
instructions .)
5.3.3. Sense Switches and Operator Request
Immediately above the five Mode buttons in the lower right-hand portion of the console is a row
of four switch/indicators. The leftmost three are Sense switches, which may be used by programs to determine one among alternative courses of action (for example, to produce out put in
punched card format rather than a printed listing). The use of Sense switches for any given program should be outlined in the operating instructions for that program. If no mention is made of
Sense switches in the operating instructions, it is understood that they should all be off (light
extinguished).
The OPERATOR REQUEST buttan .can be depressed when illuminated to interrupt a running
program. Operator request is another form of Class II program interrupt. For tape systems running
under the Executive Routine, depressing this button causes a unique display stop at which one
of several courses of action may be selected. (For a detailed discussion of these alternatives,
see the tape system software operating instructions.)
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Gi
..c:
..
'0
0
LJ
....
..
0
GI
u
0
C'
-E
0..
c:
GI
LJ
...:
.;..
.
GI
::>
01
LL
c
..... -~---
... - .. -' ..
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APPENDIX A. OCTAL-DECIMAL
CONVERSION TABLE
c
0000 to 0777
OCTAL
....
.....•• ...••••..
.... .
0
0000
0010
0020
0030
0040
0050
0060
0070
0100
HI~
-...-.....--
I~I
C:
1
Appendix A
CENTRAL PRDCESSDR
Rev. 1
0320
0330
0340
0350
0360
0370
0400
0410
0420
0430
0440
0450
0460
0470
0500
0510
0520
0530
0540
0550
0560
0570
0600
0610
0620
0630
0640
0650
0660
0670
0700
0710
0720
0730
0740
0750
0760
0770
:
•
' 0025
0033
'
0041
0048 0049
0056 0057
0064 0065
0072 0073
0080 0081
0088 0089
0096 0097
0104 0105
0112 0113
0120 0121
0128 0129
0136 0137
0144 0145
0152 0153
0160 0161
0168 0169
0176 0177
0184 0185
0192 0193
0200 0201
0208 0209
0216 0217
0224 0225
0232 0233
0240 0241
0248 0249
• • •
0264 0265
0272 0273
0280 0281
0288 0289
0296 0297
0304 0305
0312 0313
0320 0321
0328 0329
0336 0337
0344 0345
0352 0353
0360 0361
0368 0369
0376 0377
0384 0385
0392 0393
0400 0401
0408 0409
0416 0417
0424 0425
0432 0433
0440 0441
0448 0449
0456 0457
0464 0465
0472 0473
0480 0481
0488 0489
0496 0497
0504 0505
2
0002
0010
0018
0026
0034
0042
0050
0058
0066
0074
0082
0090
0098
0106
0114
0122
0130
0138
0146
0154
0162
0170
0178
0186
0194
0202
0210
0218
0226
0234
0242
0250
0258
0266
0274
0282
0290
0298
0306
0314
0322
0330
0338
0346
0354
0362
0370
0378
0386
0394
0402
0410
0418
0426
0434
0442
0450
0458
0466
0474
0482
0490
0498
0506
DECIMAL
0000 to 0511
3
4
5
6
7
0004
0012
0020
0028
0036
0044
0052
0060
0068
0076
0084
0092
0100
0108
0116
0124
0132
0140
0148
0156
0164
0172
0180
0188
0196
0204
0212
0220
0228
0236
0244
0252
0260
0268
0276
0284
0292
0300
0308
0316
0324
0332
0340
0348
0356
0364
0372
0380
0388
0396
0404
0412
0420
0428
0436
0444
0452
0460
0468
0476
0484
0492
0500
0508
0005
0013
0021
0029
0037
0045
0053
0061
0069
0077
0085
0093
0101
0109
0117
0125
0133
0141
0149
0157
0165
0173
0181
0189
0197
0205
0213
0221
0229
0237
0245
0253
0261
0269
0277
0285
0293
0301
0309
0317
0325
0333
0341
0349
0357
0365
0373
0381
0389
0397
0405
0413
0421
0429
0437
0445
0453
0461
0469
0477
0485
0493
0501
0509
0006
0014
0022
0030
0038
0046
0054
0062
0070
0078
0086
0094
0102
0110
0118
0126
0134
0142
0150
0158
0166
0174
0182
0190
0198
0206
0214
0222
0230
0238
0246
0254
0262
0270
0278
0286
0294
0302
0310
0318
0326
0334
0342
0350
0358
0366
0374
0382
0390
0398
0406
0414
0422
0430
0438
0446
0454
0462
0470
0478
0486
0494
0502
0510
0007
0015
0023
0031
0039
0047
0055
0063
0071
0079
0087
0095
0103
0111
0119
0127
0135
0143
0151
0159
0167
0175
0183
0191
0199
0207
0215
0223
0231
0239
0247
0255
0263
0271
0279
0287
0295
0303
0311
0319
0327
0335
0343
0351
0359
0367
0375
0383
0391
0399
0407
0415
0423
0431
0439
0447
0455
0463
0471
0479
0487
0495
0503
0511
0003
0011
0019
0027
0035
0043
0051
0059
0067
0075
0083
0091
0099
0107
0115
0123
0131
0139
0147
0155
0163
0171
0179
0187
0195
0203
0211
0219
0227
0235
0243
0251
0259
0267
0275
0283
0291
0299
0307
0315
0323
0331
0339
0347
0355
0363
0371
0379
0387
0395
0403
0411
0419
0427
0435
0443
0451
0459
0467
0475
0483
0491
0499
0507
1000~1777
OCTAL
2
0
1000
1010
1020
1030
1040
1050
1060
1070
1100
1110
1120
1130
1140
1150
1160
1170
1200
1210
1220
1230
1240
1250
1260
1270
1300
1310
1320
. 1330
1340
1350
1360
1370
1400
1410
1420
1430
1440
1450
1460
1470
1500
1510
1520
1530
1540
1550
1560
1570
1600
1610
1620
1630
1640
1650
1660
1670
1700
1710
1720
1730
1740
1750
1760
1770
0512
0520
0528
0536
0544
0552
0560
0568
0576
0584
0592
0600
0608
0616
0624
0632
0640
0648
0656
0664
0672
0680
0688
0696
0704
0712
0720
0728
0736
0744
0752
0760
0768
0776
0784
0792
0800
0808
0816
0824
0832
0840
0848
0856
0864
087.2
0880
0888
0896
0904
0912
0920
0928
0936
0944
0952
0513 0514
0521 0522
0529 0530
0537 0538
0545 0546
0553 0554
0561 0562
0569 0570
0577 0578
0585 0586
0593 0594
0601 0602
0609 0610
0617 0618
0625 0626
0633 0634
0641 0642
0649 0650
0657 0658
0665 0666
0673 0674
0681 0682
0689 0690
0697 0698
0705 0706
0713 0714
0721 0722
0729 0730
0737 0738
0745 0746
0753 0754
0761 0762
0769 0770
0777 0778
0785 0786
0793 0794
0801 0802
0809 0810
0817 0818
0825 0826
0833 0834
0841 0842
0849 0850
0857 0858
0865 0866
0873 0874
0881 0882
0889 0890
0897 0898
0905 0906
0913 0914
0921 0922
09290930
0937 0938
0945 0946
0953 0954
•• 0962
0969 0970
0977 0978
0985 0986
0993 0994
1001 1002
1009 1010
1017 1018
•••• •
0968
0976
0984
0992
1000
1008
1016
DECIMAL
0512 to 1023
3
4
5
6
7
0515
0523
0531
0539
0547
0555
0563
0571
0579
0587
0595
0603
0611
0619
0627
0635
0643
0651
0659
0667
0675
0683
0691
0699
0707
0715
0723
0731
0739
0747
0755
0763
0771
0779
0787
0795
0803
0811
0819
0827
0835
0843
0851
0859
0867
0875
0883
0891
0899
0907
0915
0923
0931
0939
0947
0955
0963
0971
0979
0987
0995
1003
1011
1019
0516
0524
0532
0540
0548
0556
0564
0572
0580
0588
0596
0604
0612
0620
0628
0636
0644
0652
0660
0668
0676
0684
0692
0700
0708
0716
0724
0732
0740
0748
0756
0764
0772
0780
0788
0796
0804
0812
0820
0828
0836
0844
0852
0860
0868
0876
0884
0892
0900
0908
0916
0924
0932
0940
0948
0956
0964
0972
0980
0988
0996
1004
1012
1020
0517
0525
0533
0541
0549
0557
0565
0573
0581
0589
0597
0605
0613
0621
0629
0637
0645
0653
0661
0669
0677
0685
0693
0701
0709
0717
0725
0733
0741
0749
0757
0765
0773
0781
0789
0797
0805
0813
0821
0829
0837
0845
0853
0861
0869
0877
0885
0893
0901
0909
0917
0925
0933
0941
0949
0957
0965
0973
0981
0989
0997
1005
1013
1021
0518
0526
0534
0542
0550
0558
0566
0574
0582
0590
0598
0606
0614
0622
0630
0638
0646
0654
0662
0670
0678
0686
0694
0702
0710
07i8
0726
0734
0742
0750
0758
0766
0774
0782
0790
0798
0806
0814
0822
0830
0838
0846
0854
0862
0870
0878
0886
0894
0902
0910
0918
0926
0934
0942
0950
0958
0966
0974
0982
0990
0998
1006
1014
1022
0519
0527
0535
0543
0551
0559
0567
0575
0583
0591
0599
0607
0615
0623
0631
0639
0647
0655
0663
0671
0679
0687
0695
0703
0711
0719
0727
0735
0743
0751
0759
0767
0775
0783
0791
0799
0807
0815
0823
0831
0839
0847
0855
0863
0871
0879
0887
0895
0903
0911
0919
0927
0935
0943
0951
0959
0967
0975
0983
0991
0999
1007
1015
1023
-
....
UNIVAC 1050 SYSTEMS
UP-3912
SECTION:
~-
2
Appendix A
CENTRAL PRDCESSDR
Rev. 1
.....- .... - -..
PAQE:
o
OCTAL
2000~2777
0
2000
2010
2020
2030
2040
2050
2060
2070
2100
2110
2120
2130
2140
2150
2160
2170
2200
2210
2220
2230
2240
2250
2260
2270
1024
1032
1040
1048
1056
1064
1072
1080
1088
1096
1104
1112
1120
1128
1136
1144
1152
1160
1168
1176
1184
1192
1200
1208
1216
1224
1232
124Q
1248
1256
1264
1272
1280
1288
1296
1304
1312
1320
1328
1336
1344
1352
1360
1368
1376
1384
1392
1400
1408
1416
1424
1432
1440
1448
1456
1464
1472
1480
1488
1496
1504
1512
1520
1528
1025
1033
1041
1049
1057
1065
1073
1081
1089
1097
1105
1113
1121
1129
1137
1145
1153
1161
1169
1177
1185
1193
1201
1209
1217
1225
1233
1241
1249
1257
1265
1273
1281
1289
1297
1305
1313
1321
1329
1337
1345
1353
1361
1369
1377
1385
1393
1401
1409
1417
1425
1433
1441
1449
1457
1465
1473
1481
1489
1497
1505
1513
1521
1529
DECIMAL
1024 to 1535
2
3
4
5
1026
1034
1042
1050
1058
1066
1074
1082
1090
1098
1106
1114
1122
1130
1138
1146
1154
1162
1170
1178
1186
1194
1202
1210
1218
1226
1234
1242
1250
1258
1266
1274
1282
1290
1298
1306
1314
1322
1330
1338
1346
1354
1362
1370
1378
1386
1394
1402
1410
1418
1426
1434
1442
1450
1458
1466
1474
1482
1490
1498
1506
1514
1522
1530
1027
1035
1043
1051
1059
1067
1075
1083
1091
1099
1107
1115
1123
1131
1139
1147
1155
1163
1171
1179
1187
1195
1203
1211
1219
1227
1235
1243
1251
1259
1267
1275
1283
1291
1299
1307
1315
1323
1331
1339
1347
1355
1363
1371
1379
1387
1395
1403
1411
1419
1427
1435
1443
1451
1459
1467
1475
1483
1491
1499
1507
1515
1523
1531
1028
1036
1044
1052
1060
1068
1076
1084
1092
1100
1108
1116
1124
1132
1140
1148
1156
1164
1172
1180
1188
1196
1204
1212
1220
1228
1236
1244
1252
1260
1268
1276
1284
1292
1300
1308
1316
1324
1332
1340
1348
1356
1364
1372
1380
1388
1396
1404
1412
1420
1428
1436
1444
1452
1460
1468
1476
1484
1492
1500
1508
1516
1524
1532
1029
1.037
1045
1053
1061
1069
1077
1085
1093
1101
1109
1117
1125
1133
1141
1149
1157
1165
1173
1181
1189
1197
1205
1213
1221
1229
1237
1245
1253
1261
1269
1277
1285
1293
1301
1309
1317
1325
1333
1341
1349
1357
1365
1373
1381
1389
1397
1405
1413
1421
1429
1437
1445
1453
1461
1469
1477
1485
1493
1501
1509
1517
1525
1533
6
7
1094
1102
1110
1118
1126
1134
1142
1150
1158
1166
1174
1182
1190
1198
1206
1214
1222
1230
1238
1246
1254
1262
1270
1278
1286
1294
1302
1310
1318
1326
1334
1342
1350
1358
1366
1374
1382
1390
1398
1406
1414
1422
1430
1438
1446
1454
1462
1470
1478
1486
1494
1502
1510
1518
1526
1534
1031
1039
1047
1055
1063
1071
1079
1087
1095
1103
1111
1119
1127
1135
1143
1151
1159
1167
1175
1183
1191
1199
1207
1215
1223
1231
1239
1247
1255
1263
1271
1279
1287
1295
1303
1311
1319
1327
1335
1343
1351
1359
1367
1375
1383
1391
1399
1407
1415
1423
1431
1439
1447
1455
1463
1471
1479
1487
1495
1503
1511
1519
1527
1535
OCTAL
3000 to 3777
1536
1544
1552
1560
1568
1576
1584
1592
1600
1608
1616
1624
1632
1640
1648
1656
1664
1672
1680
1688
1696
1704
1712
1720
1728
1736
1744
1752
1760
1768
1776
1784
1792
1800
1808
1816
1824
1832
1840
1848
1856
1864
1872
1880
1888
1896
1904
1912
1920
1928
1936
1944
1952
1960
1968
1976
1984
1992
2000
2008
2016
2024
2032
2040
DECIMAL
•••
1537
1545
1553
1561
1569
1577
1585
1593
1601
1609
1617
1625
1633
1641
1649
1657
1665
1673
1681
1689
1697
1705
1713
1721
1729
1737
1745
1753
1761
1769
1777
1785
1793
1801
1809
1817
1825
1833
1841
1849
1857
1865
1873
1881
1889
1897
1905
1913
1921
1929
1937
1945
1953
1961
1969
1977
1985
1993
2001
2009
2017
2025
2033
2041
1538
1546
1554
1562
1570
1578
1586
1594
1602
1610
1618
1626
1634
1642
1650
1658
1666
1674
1682
1690
1698
1706
1714
1722
1730
1738
1746
1754
1762
1770
1778
1786
1794
1802
1810
1818
1826
1834
1842
1850
1858
1866
1874
1882
1890
1898
1906
1914
1922
1930
1938
1946
1954
1962
1970
1978
1986
1994
2002
2010
2018
2026
2034
2042
1539 1540
1547 1548
1555 1556
1563 1564
1571 1572
1579 1580
1587 1588
1595 1596
1603 1604
1611 1612
1619 1620
1627 .1628
1635 1636
1643 1644
1651 1652
1659 1660
1667 1668
1675 1676
1683 1684
1691 1692
1699 1700
1707 1708
1715 1716
1723 1724
1731 1732
1739 1740
1747 1748
1755 1756
1763 1764
1771 1772
1779 1780
1787 1788
1795 1796
1803 1804
1811 1812
1819 1820
1827 1828
1835 1836
1843 1844
1851 1852
1859 1860
1867 1868
1875 1876
1883 1884
1891 1892
1899 1900
1907 1908
1915 1916
1923 1924
1931 1932
1939 1940
1947 1948
1955 1956
1963 1964
1971 1972
1979 1980
1987 1988
1995 1996
2003 2004
2011 2012
2019 2020
2027 2028
2035 2036
2043 2044
1536 to 2047
1541
1549
1557
1565
1573
1581
1589
1597
1605
1613
1621
1629
1637
1645
1653
1661
1669
1677
1685
1693
1701
1709
1717
1725
1733
1741
1749
1757
1765
1773
1781
1789
1797
1805
1813
1821
1829
1837
1845
1853
1861
1869
1877
1885
1893
1901
1909
1917
1925
1933
1941
1949
1957
1965
1973
1981
1989
1997
2005
2013
2021
2029
2037
2045
1542
1550
1558
1566
1574
1582
1590
1598
1606
1614
1622
1630
1638
1646
1654
1662
1670
1678
1686
1694
1702
1710
1718
1726
1734
1742
1750
1758
1766
1774
1782
1790
1798
1806
1814
1822
1830
1838
1846
1854
1862
1870
1878
1886
1894
1902
1910
1918
1926
1934
1942
1950
1958
1966
1974
1982
1990
1998
2006
2014
2022
2030
2038
2046
1543
1551
1559
1567
1575
1583
1591
1599
1607
1615
1623
1631
1639
1647
1655
1663
1671
1679
1687
1695
1703
1711
1719
1727
1735
1743
1751
1759
1767
1775
1783
1791
1799
1807
1815
1823
1831
1839
1847
1855
1863
1871
1879
1887
1895
1903
1911
1919
1927
1935
1943
1951
1959
1967
1975
1.983
1991
1999
2007
2015
2023
2031
2039
2047
C\
C
..
UNIVAC 1050 SYSTEMS
UP-3912
Appendix A
CENTRAL PROCESSOR
Rev. 1
OCTAL
4000 to 4777
··,..
·.,.
0
2
DECIMAL
2048 to 2559
3
5
4
6
SECTION.
OCTAL
5000~5777
7
4000
~ : 2049 2050 2051 2052 2053 2054 2'055
4010
2057 2058 2059 2060 2061 2062 2063
4020
2065 2066 2067
2069 2070 2071
' 2073 2074 2075 2068
4030
2076 2077 2078 2079
4040
: 2081 2082 2083 2084 2085 2086 2087
4050
2089 2090 2091 2092 2093 2094 2095
4060 2096 2097 2098 2099 2100 2101 2102 2103
4070 2104 2105 2106 2107 2108 2109 2110 2111
4100 2112 2113 2114 2115 2116 2117 2118 2119
4110 2120 2121 2122 2123 2124 2125 2126 2127
4120 2128 2129 2130 2131 2132 2133 2134 2135
4130 2136 2137 2138 2139 2140 2141 2142 2143
4140 2144 2145 2146 2147 2148 2149 2150 2151
4150 2152 2153 2154 2155 2156 2157 2158 2159
4160 2160 2161 2162 2163 2164 2165 2166 2167
4170 2168 2169 2170 2171 2172 2173 2174 2175
4200
2177 2178 2179 2180 2181 2182 2183
4210
: ' 2185 2186 2187 2188 2189 2190 2191
4220
2193 2194 2195 2196 2197 2198 2199
4230
2201 2202 2203 2204 2205 2206 2207
: 2209 2210 2211 2212 2213 2214 2215
4240
4250
2217 2218 2219 2220 2221 2222 2223
4260
2225 2226 2227 2228 2229 2230 2231
4270
2233 2234 2235 2236 2237 2238 2239
4300 2240 2241 2242 2243 2244 2245 2246 2247
4310 2248 2249 2250 2251 2252 2253 2254 2255
..
...
(~')
2256
2264
2272
2280
2288
2296
2312
2320
2328
2336
2344
2352
2360
2368
2376
·2384
2392
2400
2408
2416
2424
2440
2448
2456
2464
2472
2480
2488
0
2512
2520
2528
2536
2544
2552
2257 2258
2265 2266
2273 2274
2281 2282
2289 2290
2297 2298
2305 2306
2313 2314
2321 2322
2329 2330
2337 2338
2345 2346
2353 2354
2361 2362
2369 2370
2377 2378
2385 2386
2393 2394
2401 2402
2409 2410
2417 2418
2425 2426
2433 2434
2441 2442
2449 2450
2457 2458
2465 2466
2473 2474
2481 2482
24890 2490
2497 2498
2505 2506
2513 2514
2521 2522
2529 2530
2537 2538
2545 2546
2553 .2554
2259
2267
2275
2283
2291
2299
2307
2315
2323
2331
2339
2347
2355
2363
2371
2379
2387
2395
2403
2411
2419
2427
2435
2443
2451
2459
2467
2475
2483
2491
2499
2507
2515
2523
2531
2539
2547
2555
2260
2268
2276
2284
2292
2300
2308
2316
2324
2332
2340
2348
2356
2364
2372
2380
2388
2396
2404
2412
2420
2428
2436
2444
2452
2460
2468
2476
2484
2492
2500
2508
2516
2524
2532
2540
2548
2556
2261
2269
2277
2285
2293
2301
2309
2317
2325
2333
2341
2349
2357
2365
2373
2381
2389
2397
2405
2413
2421
2429
2437
2445
2453
2461
2469
2477
2485
2493
2501
2509
2517
2525
2533
2541
2549
2557
2262
2270
2278
2286
2294
2302
2310
2318
2326
2334
2342
2350
2358
2366
.2374
2382
2390
2398
2406
2414
2422
2430
2438
2446
2454
2462
2470
2478
2486
2494
2502
2510
2518
2526
2534
2542
2550
2558
DECIMAL
2263
2271
2279
2287
2295
2303
2311
2319
2327
2335
2343
2351
2359
2367
2375
2383
2391
2399
2407
2415
2423
2431
2439
2447
2455
2463
2471
2479
2487
2495
2503
2511
2519
2527
2535
2543
2551
2559
2688
2696
2704
2712
2720
2728
2736
2744
2752
2760
2768
2776
2784
2792
2800
2808
2816
2824
2832
2840
2848
2856
2864
2872
2880
2888
2896
2904
2912
2920
2928
2936
2992
3000
3008
3016
3024
3032
3040
3048
3056
3064
2561
2569
2577
2585
2593
2601
2609
2617
2625
2633
2641
2649
2657
2665
2673
2681
2689
2697
2705
2713
2721
2729
2737
2745
2753
2761
2769
2777
2785
2793
2801
2809
2817
2825
2833
2841
2849
2857
2865
2873
2881
2889
2897
2905
2913
2921
2929
2937
2945
2953
2961
2969
2977
2985
2993
3001
3009
3017
3025
3033
3041
3049
3057
3065
2562
2570
2578
2586
2594
2602
2610
2618
2626
2634
2642
2650
2658
2666
2674
2682
2690
2698
2706
2714
2722
2730
2738
2746
2754
2762
2770
2778
2786
2794
2802
2810
2818
2826
2834
2842
2850
2858
2866
2874
2882
2890
2898
2906
2914
2922
2930
2938
2946
2954
2962
2970
2978
2986
2994
3002
3010
'3018
3026
3034
3042
3050
3058
3066
2563
2571
2579
2587
2595
2603
2611
2619
2627
2635
2643
2651
2659
2667
2675
2683
2691
2699
2707
2715
2723
2731
2739
2747
2755
2763
2771
2779
2787
2795
2803
2811
2819
2827
2835
2843
2851
2859
2867
2875
2883
2891
2899
2907
2915
2923
2931
2939
2947
2955
2963
2971
2979
2987
2995
3003
3011
3019
3027
3035
3043
3051
3059
3067
2564
2572
2580
2588
2596
2604
2612
2620
2628
2636
2644
2652
2660
2668
2676
2684
2692
2700
2708
2716
2724
2732
2740
2748
2756
2764
2772
2780
2788
2796
2804
2812
2820
2828
2836
2844
2852
2860
2868
2876
2884
2892
2900
2908
2916
2924
2932
2940
2948
2956
2964
2972
2980
2988
2996
3004
3012
3020
3028
3036
3044
3052
3060
3068
3
P"GE.
2560 to 3071
•
2565
2573
2581
2589
2597
2605
2613
262i
2629
2637
2645
2653
2661
2669
2677
2685
2693
2701
2709
2717
2725
2733
2741
2749
2757
2765
2773
2781
2789
2797
2805
2813
2821
2829
2837
2845
2853
2861
2869
2877
2885
2893
2901
2909
2917
2925
2933
2941
2949
2957
2965
2973
2981
2989
2997
3005
3013
3021
3029
3037
3045
3053
3061
3069
2566
2574
2582
2590
2598
2606
2614
2622
2630
2638
2646
2654
2662
2670
2678
2686
2694
2702
2710
2718
2726
2734
2742
2750
2758
2766
2774
2782
2790
2798
2806
2814
2822
2830
2838.
2846
2854
2862
2870
2878
2886
2894
2902
2910
2918
2926
2934
2942
2950
2958
2966
2974
2982
2990
2998
3006
3014
3022
3030
3038
3046
3054
3062
3070
2567
2575
2583
2591
2599
2607
2615
2623
2631
2639
2647
2655
2663
2671
2679
2687
2695
2703
2711
2719
2727
2735
2743
2751
2759
2767
2775
2783
2791
2799
2807
2815
2823
2831
2839
2847
2855
2863
2871
2879
2887
2895
2903
2911
2919
2927
2935
2943
2951
2959
2967
2975
2983
2991
2999
3007
3015
3023
3031
3039
3047
3055
3063
3071
......
UP-3912
UNIVAC 1050 SYSTEMS
Appendix A
CENTRAL PROCESSOR
Rev. 1
OCTAL
6000 to 6177
0
6000
6010
6020
6030
6040
6050
6060
6070
6100
6110
6120
6130
6140
6150
6160
6170
3072
3080
3088
3096
3104
3112
3120
3128
3136
3144
3152
3160
3168
3176
3184
3192
3200
3208
3216
3224
3232
3240
3248
3256
3264
3272
3280
3288
3296
3304
3312
3320
3328
3336
3344
3352
3360
3368
3376
3384
3392
3400
3408
3416
3424
3432
3440
3448
3456
3464
3472
3480
3488
3496
3504
3512
3520
3528
3536
3544
3552
3560
3568
3576
3073
3081
3089
3097
3105
3113
3121
3129
3137
3145
3153
3161
3169
3177
3185
3193
3201
3209
3217
3225
3233
3241
3249
3257
3265
3273
3281
3289
3297
3305
3313
3321
3329
3337
3345
3353
3361
3369
3377
3385
3393
3401
3409
3417
3425
3433
3441
3449
3457
3465
3473
3481
3489
3497
3505
3513
3521
3529
3537
3545
3553
3561
3569
3577
DECIMAL
3072 to 3583
2
3
4
5
6
7
3074
3082
3090
3098
3106
3114
3122
3130
3138
3146
3154
3162
3170
3178
3186
3194
3202
3210
3218
3226
3234
3242
3250
3258
3266
3274
3282
3290
3298
3306
3314
3322
3330
3338
3346
3354
3362
3370
3378
3386
3394
3402
3410
3418
3426
3434
3442
3450
3458
3466
3474
3482
3490
3498
3506
3514
3522
3530
3538
3546
3554
3562
3570
3578
3075
3083
3091
3099
3107
3115
3123
3131
3139
3147
3155
3163
3171
3179
3187
3195
3203
3211
3219
3227
3235
3243
3251
3259
3267
3275
3283
3291
3299
3307
3315
3323
3331
3339
3347
3355
3363
3371
3379
3387
3395
3403
3411
3419
3427
3435
3443
3451
3459
3467
3475
3483
3491
3499
3507
3515
3523
3531
3539
3547
3555
3563
3571
3579
3076
3084
3092
3100
3108
3116
3124
3132
3140
3148
3156
3164
3172
3180
3188
3196
3204
3212
3220
3228
3236
3244
3252
3260
3268
3276
3284
3292
3300
3308
3316
3324
3332
3340
3348
3356
3364
3372
3380
3388
3396
3404
3412
3420
3428
3436
3444
3452
3460
3468
3476
3484
3492
3500
3508
3516
3524
3532
3540
3548
3556
3564
3572
3580
3077
3085
3093
3101
3109
3117
3125
3133
3141
3149
3157
3165
3173
3181
3189
3197
3205
3213
3221
3229
3237
3245
3253
3261
3269
3277
3285
3293
3301
3309
3317
3325
3333
3341
3349
3357
3365
3373
3381
3389
3397
3405
3413
3421
3429
3437
3445
3453
3461
3409
3477
3485
3493
3501
3509
3517
3525
3533
3541
3549
3557
3565
3573
3581
3078
3086
3094
3102
3110
3118
3126
3134
3142
3150
3158
3166
3174
3182
3190
3198
3206
3214
3222
3230
3238
3246
3254
3262
3270
3278
3286
3294
3302
3310
3318
3326
3334
3342
3350
3358
3366
3374
3382
3390
3398
3406
3414
3422
3430
3438
3446
3454
3462
3470
3478
3486
3494
3502
3510
3518
3526
3534
3542
3550
3558
3566
3574
3582
3079
3087
3095
3103
3111
3119
3127
3135
3143
3151
3159
3167
3175
3183
3191
3199
3207
3215
3223
3231
3239
3247
3255
3263
3271
3279
3287
3295
3303
3311
3319
3327
3335
3343
3351
3359
3367
3375
3383
3391
3399
3407
3415
3423
3431
3439
3447
3455
3463
3471
3479
3487
3495
3503
3511
3519
3527
3535
3543
3551
3559
3567
3575
3583
SECTION:
OCTAL
7000 to 7177
3624
3632
3640
3648
3656
3664
3672
3680
3688
3696
3704
3848
3856
3864
3872
3880
3888
3896
3904
3912
3920
3928
3936
3944
3952
3960
4008
4016
4024
4032
4040
4048
4056
4064
4072
4080
4088
3585
3593
3601
3609
3617
3625
3633
3641
3649
3657
3665
3673
3681
3689
3697
3705
3713
3721
3729
3737
3745
3753
3761
3769
3777
3785
3793
3801
3809
3817
3825
3833
3841
3849
3857
3865
3873
3881
3889
3897
3905
3913
3921
3929
3937
3945
3953
3961
3969
3977
3985
3993
4001
4009
4017
4025
4033
4041
4049
4057
4065
4073
4081
4089
3586
3594
3602
3610
3618
3626
3634
3642
3650
3658
3666
3674
3682
3690
3698
3706
3714
3722
3730
3738
3746
3754
3762
3770
3778
3786
3794
3802
3810
3818
3826
3834
3842
3850
3858
3866
3874
3882
3890
3898
3906
3914
3922
3930
3938
3946
3954
3962
3970
3978
3986
3994
4002
4010
4018
4026
4034
4042
4050
4058
4066
4074
4082
4090
DECIMAL
3587
3595
3603
3611
3619
3627
3635
3643
3651
3659
3667
3675
3683
3691
3699
3707
3715
3723
3731
3739
3747
3755
3763
3771
3779
3787
3795
3803
3811
3819
3827
3835
3843
3851
3859
3867
3875
3883
3891
3899
3907
3915
3923
3931
3939
3947
3955
3963
3971
3979
3987
3995
4003
4011
4019
4027
4035
4043
4051
4059
4067
4075
4083
4091
3588
3596
3604
3612
3620
3628
3636
3644
3652
3660
3668
3676
3684
3692
3700
3708
3716
3724
3732
3740
3748
3756
3764
3772
3780
3788
3796
3804
3812
3820
3828
3836
3844
3852
3860
3868
3876
3884
3892
3900
3908
3916
3924
3932
3940
3948
3956
3964
3972
3980
3988
3996
4004
4012
4020
4028
4036
4044
4052
4060
4068
4076
4084
4092
4
PAGE:
3584 to 4095
3589
3597
3605
3613
3621
3629
3637
3645
3653
3661
3669
3677
3685
3693
3701
3709
3717
3725
3733
3741
3749
3757
3765
3773
3781
3789
3797
3805
3813
3821
3829
3837
3845
3853
3861
3869
3877
3885
3893
3901
3909
3917
3925
3933
3941
3949
3957
3965
3973
3981
3989
3997
4005
4013
4021
4029
4037
4045
4053
4061
4069
4077
4085
4093
3590
3598
3606
3614
3622
3630
3638
3646
3654
3662
3670
3678
3686
3694
3702
3710
3718
3726
3734
3742
3750
3758
3766
3774
3782
3790
3798
3806
3814
3822
3830
3838
3846
3854
3862
3870
3878
3886
3894
3902
3910
3918
3926
3934
3942
3950
3958
3966
3974
3982
3990
3998
4006
4014
4022
4030
4038
4046
4054
4062
4070
4078
4086
4094
3591
3599
3607
3615
3623
3631
3639
3647
3655
3663
3671
3679
3687
3695
3703
3711
3719
3727
3735
3743
3751
3759
3767
3775
3783
3791
3799
3807
3815
3823
3831
3839
3847
3855
3863
3871
3879
3887
3895
3903
3911
3919
3927
3935
3943
3951
3959
3967
3975
3983
3991
3999
4007
4015
4023
4031
4039
4047
4055
4063
4071
4079
4087
4095
!r
.4··"
'~
C:
...
~.~-
.....
---------~-----
c
c
)}'fI!I'II""'"
o
i·
I
o
I
UP.3912
o
Rev. 1
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Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2018:04:18 19:32:57-08:00 Modify Date : 2018:04:18 19:54:31-07:00 Metadata Date : 2018:04:18 19:54:31-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:c3a45744-bcd6-ee4d-8080-2f98a43a36d7 Instance ID : uuid:f551dd67-a01f-0847-8dec-946436277111 Page Layout : SinglePage Page Mode : UseNone Page Count : 130EXIF Metadata provided by EXIF.tools