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UNIVAC
DATA PROCESSING DIVISION
•
ASSEMBLER-BD
c
U'P·4084
c·
This manual is published by the UNIVAC Division of Sperry Rand Corporation in loose leaf format as a rapid and complete means of keeping recipients apprised of UNIVAC ® Systems developments. The UNIVAC
. Division will issue updating packages, utilizing primarily a page-for-page
or unit replacement technique. Such issuance will provide notification of
hardware and/or software changes and refinements. The UNIVAC Division
reserves the right to make such additions, corrections, and/or deletions
as in the judgment of the UNIVAC Division, are required by the development of its respective Systems.
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®
REGISTERED TRADEMARK OF THE SPERRY RAND CORPORATION
PRINTED IN U.S.A.
-
...........
~
..... ---..-.•.- ..-•.
~-~.--.--.-.-.-.-~---.-
..-.-.-..
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UNIVAC 100S
UP-4084
1
Contents
ASSEMBLER.SO
SECTION:
PAGE:
CONTENTS
1 t04
CONTENTS
.(~:
./
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1. INTRODUCTION TO THE UNIVAC 1005 AND INTERNALLY STORED PROGRAMMING
1-1 to 1-9
1.1. ADDRESSING TECHNIQUE
1-1
1.2. BASIC LOGIC AND FORMAT
1-2
1.3. CONTROL SECTION OPERATION
1-3
1.4. OTHER INSTRUCTION FORMATS
1-4
1.5. STORAGE ALLOCATION AND USE
1..,4
1.6. INDIRECT ADDRESSING
1-5
1.7. OTHER SPECIAL REGISTERS
1-8
1.8. SPECIAL REGISTER LOCATIONS
1-8
1.9. ADDRESSING AND USE OF COLUMN 32
1-9
2. INTRODUCTION TO ASSEMBLY SYSTEMS
2-1 to 2-4
2.1. PURPOSE OF ASSEMBLY SYSTEMS
2-1
2.2. MNEMONIC CODING
2-1
2.3. SYMBOLIC CODING
2-2
2.4. RELATIVE CODING
2-2
2.5. MEMORY MAPPING
2-2
2.6. DECLARATIVE INSTRUCTIONS
2-3
2.7. ASSEMBLER PROCESSING
2-4
---------------~-~~==~~-~~~~~~~-~
,...-...
"",~-=-
--_ .. _ - _ . _ - - _ .. -
--~~-~-----~--~~.~-----
....
~
__ . ___
~
_ _ _ _ _ _ _ ._ _ _ _ ··n.
UNIVAC 1005
____U_P_-_4_0_84__~_______________A_S_S_E_M_B_L_E_R_-_8_0______________~__________~S_E_C;_I_~:_~_e_nt_s__~p_A_GE_:__2__~.~
3. INTRODUCTION TO THE UNIVAC 1005 ASSEMBLY SYSTEM
3-1 to 3-15
3.1. TERMINOLOGY DEFINITIONS
3-1
3.2. CODING FORM
3.2.1. LABEL
3.2.2. OPERATION
3.2.3. OPERAND 1
3.2.3.1. IA
3.2.3.2. FIELD A
3.3.3.3. ± INC
3.2.4. OPERAND 2
3.2.4.1. lA, FIELD B, ± INC
3.2.4.2. FIELD C, ± INC
3.2.5. COMMENTS
3.2.6. CARD NUMBER
3.2.7. REMAINDER
3-1
3-1
3-2
3-3
3-3
3-3
3-3
3-4
3-4
3-4
3-5
3-5
3-5
3.3. OPERAND 1 ADDRESS SPECIFICATION
3.3.1. Symbolic Address (Label) Specification
3.3.2. Increments to Symbolic Addresses
3.3.3. Decimal Addressing
3.3.4. Rowand Column Addressing
3.3.5. Instruction Location Counter (ILC) Addressing
3-6
3-6
3-7
3-8
3-8
3-9
3.4. OPERAND 2 ADDRESS SPECIFICATION
3.4.1. Operand 2, Field C, Blank Addressing
3.4.2. Operand 2 Indirect Addressing
3-10
3-10
3-12
3.5. SUMMARY OF FIELD A, FIELD B, AND FIELD C SPECIFICATIONS
3.5.1. FIELD A
3.5.2. FIELD B
3.5.3. FIELD C
3-13
3-13
3-13
3-14
3.6. STANDARD SYSTEMS LABELS
3-14
4. UNIVAC 1005 ASSEMBL Y SYSTEM INSTRUCTIONS
4-1 to 4-98
4.1. LEGEND
4-1
4.2. LENGTH OF OPERANDS
4-1
4.3. TRANSFER INSTRUCTIONS
4.3.1. TRANSFER DESCENDING
4.3.2. TRANSFER ASCENDING
4.3.3. TRANSFER CLEAR
4.3.4. TRANSFER NUMERIC
4.3.5. TRANSFER CONSTANT
4.3.5.1. Symbol i c Address Substitution
4.3.5.2. Row/Column and Decimal Addressing
4.3.5.3. Binary Coded Constants
4.3.6. TRANSFER TO REGISTER X
4.3.7. TRANSLATE
4-4
4-4
4-7
4-9
4-10
4-10
4-14
4-15
4-16
4-18
4-19
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UNIVAC 1005
· UP-4084
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ASSEMBLER·SO
Contents
SECTION:
3
PAGE:
4.4. ADDITION AND SUBTRACTION
4.4.1. ADD ALGEBRAIC
4.4.2. SUBTRACT ALGEBRAIC
4.4.3. ABSOLUTE ADD (ADD MAGNITUDE)
4.4.4. ABSOLUTE SUBTRACT (SUBTRACT MAGNITUDE)
4.4.5. ADD CONSTANT
4-23
4-24
4-25
4-26
4-26
4-27
4.5. COMPARE INSTRUCTIONS
4.5.1. COMPARE NUMERIC SIGNED COMPARISON
4.5.2. COMPARE ABSOLUTE (MAGNITUDE) UNSIGNED COMPARISON
4.5.3. COMPARE ALPHANUMERIC UNSIGNED COMPARISON
4.5.4. COMPARE CONSTANT UNSIGNED COMPARISON
4-28
4-29
4-30
4-32
4-34
4.6. CON DITION IN DICA TORS
4.6.1. SET CONDITION
4.6.2. STOP (HA LT)
4-36
4-36
4-39
4.7. SEQUENCE CONTROL INSTRUCTIONS
4.7.1. JUMP CONDITION
4.7.2. JUMP TEST
4.7.3. UNCONDITIONAL JUMP
4.7.4. JUMP RETURN
4.7.5. JUMP COMPARE
4.7.6. JUMP LOOP
4.7.7. JUMP INDIRECT
4-39
4-39
4-44
4-46
4-46
4-49
4-51
4-54
4.8. COUNT
4-55
4.9. EDIT INSTRUCTIONS
4.9.1. EDIT LOGICAL
4.9.2. EDIT ERASE
4.9.3. EDIT SUPERIMPOSE
4.9.4. ED IT
4-57
4-58
4-60
4-60
4-61
4.10 DECLARATIVE INSTRUCTIONS
4.10.1. DEFINE INSTRUCTION LOCATION COUNTER
4.10.2. DEFINE AREA
4.10.2.1. DEFINE SUB-FIELD
4.10.2.2. Subfields of Specific Fixed Address Areas
4.10.3. DEFINE CONSTANT
4.10.3.1. In-line Constants
4.10.3.2. In-line Comments
4.10.4. DEFINE INDIRECT ADDRESS CONSTANT
4.10.5. DEFINE END
4-65
4-65
4-68
4-69
4-71
4-72
4-74
4-75
4-76
4-79
4.11. MULTIPLICATION INSTRUCTIONS
4.11.1. MULTIPLY
4.11.2. MULTIPLY (LONG)
4-79
4-80
4-82
4.12. DIVIDE INSTRUCTION
4.12.1. DIVIDE
4-83
4-84
UNIVAC 1005
UP-4084
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SECTION,
4
PAGE,
4.13. INPUT/OUTPUT INSTRUCTIONS
4.13.1. SHORTENED GENERAL COMMAN DS
4.13.2. GENERAL COMMANDS
4.13.3. READ MAGNETIC TAPE
4.13.4. WRITE MAGNETIC TAPE
4.13.5. RECEIVE DATA LINE
4.13.6. SEND DATA LINE
4.13.7. RECEIVE INTERFACE
4.13.8. SEND INTERFACE
4-85
4-86
4-87
4-92
4-93
4-94
4-95
4-96
4-97
5. OPERATING PROCEDURES FOR 1005 ASSEMBLY
5-1 to 5-3
5.1. LOADING SOURCE PROGRAM
5.2. LOADING OBJECT PROGRAM
5.3. FINAL LISTING
5.3.1. Original Source Code
5.3.2. Unfound Indicators
5.3.3. Sequence Number
5.3.4. Object Code Instruction
5.3.5. Load Instruction
5.3.6. Diagnostic Message
5-1
5-2
5-2
5-2
5-2
5-3
5-3
5-3
5-3
6. PROGRAM TESTING AIDS
6-1 to 6-3
APPENDIX A.
UNIVAC 1005 ASSEMBLER CODING FORM
A-I to A-I
APPENDIX B.
UNIVAC 1005 INSTRUCTION TIMING (80)
B-1 to B-1.
C"
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August 23, 1966
UNIVAC 1005 System
ASSEMBLER-80 Programmer's Reference
UP-4084
UPDATING PACKAGE "A"
UNIVAC 1005 System P.I.E. Bulletin 4, UP-4072.4, releases and announces
the availability of Updating Package "A" for the "UNIVAC 1005 SYSTEM
ASSEMBLER-80 Programmer's Reference," UP-4084, 59 pages plus 1 Updating
Summary Sheet. This material should be utilized in the following manner:
SECTION
1
3
4
DESTROY FORMER
PAGES NUMBERED
1
&
2
3 & 4
9 & 10
13 & 14
1 & 2
5 & 6
7 & 8
11 & 12
15 & 16
19 & 20
21
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35
37
39
41
51
53
55
61
63
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& 42
& 52
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& 68
& 74
& 82
& 84
& 86
& 98
1 & 2
3
*These pages, backups of
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FILE NEW PAGE
NUMBERED
1* & 2 Rev.l
3 Rev.l & 4*
9 Rev.l & 10*
13* & 14 Rev.l
1 Rev.l & 2*
5 Rev.l & 6*
7 Rev.l & 8 Rev.l
11* & 12 Rev.l
15 Rev.l & 16 Rev.l
19* & 20 Rev.l
21 Rev. 1 & 22*
29 Rev.l & 30*
35* & 36 Rev.l
37 Rev.l & 38*
39 Rev.l & 40*
41 Rev.l & 42*
51 Rev.l & 52*
53* & 54 Rev.l
55 Rev.l & 56*
61 Rev.l & 62 Rev.l
63 Rev.l & 64 Rev.l
65 Rev.l & 66*
67 Rev.l & 68*
73 Rev.l & 74 Rev.l
81 Rev.l & 82 Rev.l
83 Rev.l & 84*
85 Rev.l & 86*
97 Rev. 1 & 98*
1 Rev.l & 2*
3 Rev.l
revised pages, remain unchanged.
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UNIVAC 1005
UP-4084
ASSEMBLER·SO
1
SECTION.
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1. INTRODUCTION
TO THE UNIVAC 1005
AND INTERNALLY STORED
PROGRAMMING
The UNIVAC 1005 is a general purpose, stored program, digital computer. The main
store consists of either two or four banks of core memory with 1024 locations per
bank. In addition to providing storage for instructions and data, two types of
Special Registers are provided in core memory to control the operation of the
UNIVAC 1005. The special registers are addressable and in some cases can be used
as additional data storage.
1.1.
ADDRESSING TECHNIQUE
Each bank of core memory consists of a 32 row by 32 column matrix of six-bit
memory locations. Each location is addressed by specifying its Row and.Column
coordinates. For example; the first memory location has an address of Row 1,
Column 1; the last memory location has an address of Row 32, Column 32. These
address designations are abbreviated to R11C1 and R32/C32.
In order to store the address of instructions and data in memory, the six bits of two
adjacent memory locations are required. Five of the six bits of the left-hand
location are used to specify the Row coordinate, and five of the six bits of the righthand location are used to specify the Column coordinate. A combination of the
sixth bits of both locations is used to specify which of the four possible banks of
memory is involved.
The UNIVAC 1005 utilizes a special five-bit address concept which operates on a
logical rather than a binary arithmetic basis. Special combinations of these five
bits are employed for the values 1 to 31 used as row or column coordinates. These
five-bit combinations, plus the sixth bit required for bank designation, correspond
to the 64 characters of the UNIVAC 1005. Thus, the address of any location in any
bank of core memory can be specified by the proper selection of two of these sixbit characters.
c
The foregoing description indicates the similarity and compatibility of the memory
of the UNIVAC 1005 and the UNIV.AC 1004.
1
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UNIVAC 100S
UP-4084
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ASSEMBLER-80
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SECTION,
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For the purpose of stored-programming, the main store of the UNIVAC 1005 should
be considered as 1922 (or 3844) consecutively numbered, decimally addressed
memory locations exclusive of all rows numbered 32 and all Columns numbered 32
of each row. The physical arrangement of main store is then no longer a concern of
the programmer. Using this method, the main store of the UNIVAC 1005 takes on
the following appearance:
1
101
100
200
300
201
1701
1801
1901
2001
2000
2100
12100
2200
3601
3701
3801
3700
3800
h923
3844
I
1800
1900
1922
I
BANKS 1 and 2
BANKS 3 and 4
Decimal addressing would then produce the following facility for programming:
First location of Read Input Storage (Card Col. 1)
Last location of Read Input Storage (Card Col. 80)
First location of Print Storage (Print Pos. 1)
Last location of Print Storage (Print Pos. 132)
First location of Punch Storage (Card Col. 1)
Last location of Punch. Storage (Card Col. 80)
DECIMAL ADDRESS
1
80
161
292
293
372
Since Print Position 1 is located at address 161, Print Position 23, for example, is
located 22 positions away at address 183. This same convenience is extended to
the addressing of the programmer's data areas as well as to the other reserved areas
of Input Output storage. A complete description of decimal addressing as provided
by the UNIVAC 1005 Assembly System appears in Section 3.3.3. of this manual.
1.2.
BASIC LOGIC AND FORMAT
The UNIVAC 1005 operates on a basic two address instruction logic. A UNIVAC
1005 instruction may contain the address of one or two units of information called
Operands, and an operation code for the process to be performed with these Operands.
The Operands are defined by specifying the address of the most Significant location
(abbreviated MSL), or the address of the least significant location (abbreviated
LSL), or both, depending on the operation to be performed. Operations are specified
by a one character code.
o
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--~~- ,,,--.".-.~~~-------
..~.,~--~,-~-~-~~"---~'~"·'"-'·-"""--uN IVAC -100S
- "'~.~---"-"""-".'-~-----'-.-~.......~-~~
ASSEMBLER.80
UP-4084
---'"------,------,-.--------~ I"-~-~--~~~~'
Rev. 1
1
IECTION:
The majority of the UNIV AC 1005 instructions require seven character locations in
the following format:
OP
A
B
C
is
is
is
is
a single character which specifies the operation to be performed.
the two character address of the MSL or the LSL of Operand 1.
the two character address of the MSL of Operand 2.
the two character address of the LSL of Operand 2.
A, B or C may also represent constant information.
The function called for by an instruction is executed in ascending (LSL to MSL) or
descending (MSL to LSL) mode. If the operation is performed in ascending mode,
the A portion specifies the LSL of Operand 1. If the operation is performed in
descending mode, the A portion specifies the MSL of Operand 1. The use of UNIVAC
1005 character codes to specify operation codes and addresses is called absolute
coding or machine coding. A table of these codes and their equivalents is shown
in Section 6. As will be explained in succeeding sections of this manual, the UNIVAC
1005 Assembly System provides a convenient method of specifying these codes. The
output of the Assembler processing is a deck of punched cards containing instructions
in machine code. These cards are read by the UNIVAC 1005 and the instructions stored
in core memory under the control of a Load program. The Load program supplied by
UNIV AC is a special header card which is placed in the front of the instruction cards.
1.3.
CONTROL SECTION OPERATION
After the program has been loaded, operation of the UNIVAC 1005 proceeds under
the control of the Instruction Control Counter (ICC). The ICC is one of the Special
Registers located in core memory. The ICC is a two character register which contains
the address of the MSL of the instruction to be accessed next by the UNIVAC 1005.
As each instruction is accessed for execution, the contents of the ICC are incremented by the number of characters in the instruction - - usually seven. This incremen t is automatically added to the right-hand character of the ICC, the Column
address portion. When the Column count passes 31, an increment of one is added
to the Row address portion of the ICC, and the Column portion is returned to 1.
The ICC will never create an address of Row 32 or Column 32 because the increment
of 1 to "31" produces a result of 1. Memory Bank specification is also advanced
as the Row count passes 31. Thus,the access and execution of instructions
proceeds in a sequential manner. Instructions are provided to vary this sequential
operation when required.
As each instruction is accessed, according to the address in the ICC, it is transferred to the Instruction Register (IR). The IR is a seven character Special Register
which is used to examine the instruction. The bit configuration of the single
character Operation code is analyzed by the circuitry which establishes and controls
the functions necessary to perform the required operation. The address portions of
the IR are transferred to the internal storage address controls for OP 1 and OP 2.
3
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-----------[fNTv-..\"cToos· ...
UP-4084
4
ASSEMB LER-BO
The normal operation of the UNIVAC 1005 when executing instructions is to access
the first character from either the LSL or the MSL of OP 1, and the corresponding
character from OP 2 (LSL or MSL) and perform the process. The determination of
whether the LSL or the MSL is used is based on the mode--ascending or descending
--of the instruction. After operating on the first characters from OP 1 and OP 2, the
operation proceeds with successive corresponding characters of OP 1 and OP 2
until the processing of the last character location of OP 2 has been completed.
This signals the end of the instruction.
o
During the execution of each instruction, the contents of the ICC are incremented
according to the number of characters in the instruction itself. When the end
operation signal is generated, the new address in the ICC is used to control the
access of the next instruction (NI). The execution of the program proceeds in this
manner to direct the UNIV AC 1005 to accomplish the desired results.
1.4.
I
OTHER INSTRUCTION FORMATS
The instruction repertoire of the UNIV AC 1005 includes a complete set of commands
for control of the operation of the system. In addition to the type of commands
previously mentioned--seven characters, with an OP 1 and an OP 2 address--there
is a second type of command which provides for flexibility and ease of control of
the programming requirements necessary to internally stored program operation.
The second type of instruction is five characters in length and has the following
format:
OP
A
B
o
Where:
OP is a one character operation code.
A is a two character address or constant whose value is used or whose
bit configuration is used to perform special functions.
B is a two character address of a loe ation in memory.
As is the case with most stored program computers, there are special commands in
the UNIVAC 1005 with a format that does not precisely conform to these two basic
formats. The Set Condition Instruction is a unique exception to the general rule in
that "B" is used for the normal purpose of "A." These special commands will be
either five or seven characters in length, and the format variation will be indicated
along with a complete description of the operation.
1.5.
STORAGE ALLOCATION AND USE
The main store of the UNIVAC 1005 is separated by the hardware into two major
areas--input output store, and working store. Input output store consists of selected
portions of memory reserved for the information received from and transferred to the
input/output devices. When an input or output device is not required by a particular
o
UNIVAC 1005
UP-4084
ASSEMBLER·SO
c
1
SECTION:
program, the reserved memory area of that device may be used by the programmer for
storage of instructions or data. The working store consists of these portions of
memory not reserved for input/output information--the remainder of core memory.
The working store is separated by the programmer into two types of areas according
to his programming requirements. A portion of working store is established by the
programmer to store the information (other than input/output) to be processed. The
remainder of working store is used to st'ore the program instructions.
A note should be made at this point that the addressing capability of the instruction
address extends to all of main store. This means that the contents of any memory
location or locations can be accessed as data to be processed. This includes those
locations used by the programmer to store instructions. The use of this capability
to operate on instructions as if they were data is an important technique of internally
stored programming.
1.6.
(~:
INDIRECT ADDRESSING
Another facility provided by the UNIVAC 1005 is the ability to perform Indirect
Addressing. In the UNIVAC 1005, Indirect Addressing is the ability to specify in
the address portion of an instruction the address of the memory location which contains not the data to be processed, but a secondary address which specifies the
location of the data to be processed. From a hardware standpoint, this is accomplished by using the primary address--the address in the instruction--to control the
transfer of the secondary address to the IR where it is then used as the address of
the data to be processed.
From a programming standpoint, Indirect Addressing allows the programmer to
establish one series of instructions which perform a programming operation on
separately stored but related items of information. This is accomplished by programming the instructions once using primary addresses, and changing the secondary
addre,ss to refer to the proper item for each use of the series of instructions. For
example: a detail card contains four twenty-column transaction items. Each item
contains four five-column fields. The program is written using primary addresses
which refer to a table of secondary addresses. The table is set up to refer to the
address of the fields within an item. A series of addresses in the form of constants
is created by the programmer and stored in a portion of working store. There is a
series of addresses for each of the transaction items as they will appear in Read
Input Storage. Before processing the first transaction item, the program transfers
the series of addresses which refer to this item, to the secondary address table
locations referred to by the primary addresses in the instructions. The first item
is then processed. At the conclusion of the processing of the first item, the program
then transfers the series of addresses which refer to the second transaction to the
table of secondary addresses. The series of instructions is then executed again,
only this time, the table of secondary address references the locations of the fields
of the second transaction item causing it to be processed. The program action of
changing the contents of the secondary address table is then repeated for the
processing of the third and fourth transaction items. An explanation of this example
is shown in Figure 1-1.
5
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UNIVAC 1005
UP-4084
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1
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SECTION:
o
READ INPUT STORAGE
FIELD I
1
56
FIELD 2
FIELD 3
10 II
FIE LD 4
15 16
FIELD I
2021
FIELD 2
2526
FIELD 3
3031
~
TRANSACTION FOUR
TRANSACTION THREE
TRANSACTION TWO
TRANSACTION ONE
FIELD 4
3536
FIELD I
4041
FIELD 3
FIELD 2
4546
5051
FIELD 4
5556
FIE~D
60 61
I
FIELD 2
6566
FIELD 3
7071
FIELD 4
7576
80
SECONDARY ADDRESS TABLE
ENTRY I
ENTRY 2
ENTRY 3
ENTRY 4
ADR. OF
FIELD I
ADR. OF
FIELD 2
ADR.OF
FIELD 3
ADR.OF
FIELD 4
MSL LSL
MSL LSL
MSL LSL
MSL LSL
,---1234
o
CONSTANT STORAGE
{ENTRY I
ADR.OF
FD. I, ITEM I
ADR.OF
FD. 2, ITEM I
ADR.OF
FD. 3, ITEM I
ADR.OF
FD. 4, ITEM 1
ENTRY 2
ADR.OF
FD.l ITEM 2
ADR.OF
FD.2 ITEM 2
ADR.OF
FD. 3, ITEM 2
ADR.OF
FD. 4, ITEM 2
ENTRY 3
ADR.OF
FD. I, ITEM 3
ADR.OF
FD. 2, ITEM 3
ADR.OF
FD. 3, ITEM 3
ADR.OF
FD. 4, ITEM 3
ENTRY 4
ADR.OF
FD. I, ITEM 4
ADR.OF
FD. 2, ITEM 4
ADR.OF
FD. 3, ITEM 4
ADR.OF
FD. 4, ITEM 4
Figure 1-1. Example of Indirect Addressing
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UNIVAC 100S
UP-4084
SECTION:
INSTRUCTIONS REQUIRED
The * ind icates Ind irect Address ing
OPERATION
Instr. 1
TRF-D
FIELD A
MSL of Entry
1 in constant
storage
FIELD B
-
FIELD C
ACTION
MSL of
Sec Adr
Table
LSL of Sec
Adr Table
The MS Land LS L addresses of
the Fields of Transaction One
are transferred to the Sec Adr
Table
2
ADD-ALG
*ADR of Loc 3
Entry 1, Sec
Adr Table
(LSL Field)
*ADR of
Loc 1
Entry 2,
Sec Adr
(MSL Fd 2)
ADR of Loc
3 Entry 2
Sec Adr
(LSL Fd 2)
The primary address in the A
position of the instruction refers
to the lower 2 characters of Entry
1 in the Sec Adr Table. These
two characters are then used as
the A address of this instruction.
The primary addresses in the
Band Cpos iti ons similarly refer
to the Sec Adr Table Entry 2, and
address substitution occurs.
3
ADD-ALG
*ADR of Loc 3
Entry 2, Sec
Adr (LSL Fd 2)
*ADR of Loc
1 Entry 3
Sec Adr
(MSL Fd 3)
ADR of Loc
3 Entry 3
Sec Adr
(LSL Fd 3)
Same as for Instruction 2 except
that substitutes are made from
Entry 2 and Entry 3.
4
SUB-ALG
*ADR of Loc 3
Entry 3, Sec
Adr (LSL Fd 3)
*ADR of Loc
1 Entry 4,
Sec Adr
(MSL Fd 4)
ADR of Loc
3 Entry 4
Sec Adr
(LSL Fd 4)
Same as for Instruction 3 except
that substitutions are made from
Entry 3 and Entry 4.
5
TRF-D
MSL of Entry
2, then 3, then
4, in constant
storage
MSL of Sec
Adr Table
LSL of Sec
Adr Table
The addresses of the next item
are set up in the Sec Adr Table.
6
Return to
Instruction
2
Transfer control to instruction
2 to initiate processing of the
next item.
NOTE: Additional programming techniques are necessary to control the number of times these instructions
are to be executed for each card read. They are not involved with the use of Indirect Addressing,
and were omitted in order to confine the example to the discussion. They will be covered a long
with the UNIVAC 1005 Operations which are used for the additional techniques. (See the JL and
CC instructions if desired.)
Instructions 2, 3 and 4 will not have anything coded in Field C. The MSL and LSL to be used is
defined in Field B.
The normal use of Indirect Addressing is with data which contains a multiple item
format similar to the punched card format in the preceding example. The multiple
item concept is generally used for magnetic tape master and detail files. The use
of the Indirect Addressing capability of the UNIVAC 1005 is not restricted to the
multiple item concept.
c'
7
1
ASSEMBLER-SO
Other UNIVAC 1005 Operations and capabilities designed to implement stored
programming techniques are described in this manual along with an example of the
application of the technique.
PAGE:
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-------
'--'---::--~-
UNIVAC 1005
UP-4084
1
ASSEMBLER-SO
SECTION:
1.7.
8
PAGE:
c
OTHER SPECIAL REGISTERS
There are two Special Registers in addition to the Instruction Control Counter and
the Instruction Register. These are the Multiply /DivideRegister (MDR), and a
multi-purpose register called Register X (rX).
The MDR is 31 locations in length, and is used in the process of Multiplication and
Division. The most significant 10 positions of the MDR are used by the IR and the
ICC during part of each Instruction Cycle. When not required for this purpose, the
least significant 21 locations may be used for intermediate results of other programming operations.
Register X is 31 locations in length and is used primarily with the Edit Mask
Operation, otherwise it may be used when Add or Subtract operations involve
Operands of unequal length.
A thorough explanation of the use of rX and the MDR is given in this manual where
the Oper,ations which reference them are discussed.
It should be'remembered that all Special Registers are located in core memory, are
explicitly addressable, and are in addition to the basic two or four banks of main
store.
1.8.
SPECIAL REGISTER LOCATIONS
The Instruction Register (IR), the Instruction Control Counter (ICC), and the
Multiply/Divide Register (MDR) constitute an extra row of core memory--Row 32.
This set of special registers is in Row 32 of BANK 1
1
COLUMN
c
31
1
ROW
BANK 1
HARDWARE RESTRICTION
COLUMN 10 CANNOT
BE USED
IR
MDR
32
1
Regist~r
7 8
9 10
11
31
X constitutes an .extra row of core memory--Row 32 of BANK 2.
1
COLUMN·
31
- 1
ROW
BANK 2
IX
32~______________~
1
31
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UNIVAC 1005
UP-4084
ASSEMBLER-SO
(~.
1
SEC TION:
When the ICC is incremented for sequential access of instructions, it advances from
R31/C31 of Bank 1, Bank 2, Bank 3, and Bank 4, to Rl/Cl of Bank 2, Bank 3, Bank
4, and Bank 1 respectively, thus bypassing Row 32 and the special registers. The
use of decimal addressing does not include the specification of the addresses of the
Special Registers.
1.9.
ADDRESSING AND USE OF COLUMN 32
Each of the 32 Rows of memory contains 32 columnar positions. The allocation of
memory by the Assembler program is made on the basis of 31 Rows and 31 Columns
per Bank. As described in Secti.on 1.8, Row 32 of Bank 1, 2, 3, and Bank 4 are
excluded from Assembler allocation and are used for the Special Registers. The
explanation of the advance of the Rowand Column portions of the Instruction
Control Counter indicates that not only is Row 32 of memory bypassed, but also
Column 32 of each Row of memory is also excluded from Assembler allocation.
Column 32 of each Row in Bank 2, 3, and 4 becomes a series of one character
locations which can be used by the programmer for such things as single character
constants, control settings, program switches, etc. Decimal addressing does not
include the addressing of any Column 32.
NOTE: Column 32 of each of the Rows in Bank 1 are reserved for hardware/software
control purposes an'd must not be used by the programmer.
Row 32 of Bank 3 and Bank 4 are also not included in the allocation processing of
the Assembler program. Row 32 of Bank 3 and Bank .4 can be used by the programmer
for the storage of data and intermediate results of processing.
Control of an internally stored program computer is accomplished by providing the
computer with a set of instructions which have been designed to produce the desired
results. These instructions are created by the programmer according to the specific
requirements and capabilities of the computer. The instructions must be entered in
the computer memory in a specific sequence using a precise set of characters. This
set of characters constitutes the vocabulary or language of the machine. Machine
languages are dictated by the design characteristics of the computer and seldom
bear any relationship to human language. Furthermore, machine languages seldom
follow any logical pattern that a person could use when writing a program. In
addition to the language barrier, there are many clerical-type functions which a
programmer must perform when writing a program.
9
PAGE:
- - - - - - - - - - - - - - - - - ...._._------_ ...• _ - - - - - -
o
()
UNIVAC 1005
UP-4084
ASSEMBLER-SO
2. INTRODUCTION
TO ASSEMBLY SYSTEMS
2.1.
PURPOSE OF ASSEMBLY SYSTEMS
In order to overcome the language barrier, and to provide the programmer with
clerical-type assistance, an assembly system is usually provided as part of the
software of an internally stored program computer.
The assembly system allows the programmer to use a machine-oriented language
which is also human oriented. The programmer writes the instructions in assembly
language according to the rules of the assembly system. These instructions are
punched into cards and are read into the computer under the control of a program
called the assembler program. The assembler program analyzes the assembly
language instructions and translates or converts this language into the precise
machine language of the computer. An output deck of punched cards is produced
by the assembler processing which contains the machine language instructions.
This deck of cards is then read into the computer under the control of a load
program which stores the instructions in the required sequence. The computer is
then instructed to execute the program.
(-
The deck of cards which contains the instructions written in assembly language is
called the source deck. The output deck of cards which contains the instructions
in machine language is called the object deck. In some cases, the assembly
language is referred to as the source language or source code, and the machine
language is referred to as the object language or object code.
2.2.
MNEMONIC CODING
The terms mnemonic, symbolic, and relative coding are sometimes erroneously used
as synonyms. Each term has a specific meaning, and each one constitutes an important characteristic of an assembler.
c
1
2
SECTION:
An assembly language usually contains a set of mnemonic codes which represent
the Operation codes of the computer. These mnemonic codes are established to
help the programmer remember the code to be used for the Operation needed.
PAGE:
UNIVAC 1005
UP-4084
ASSEMB LE R-80
2.3.
2
SECTION:
SYMBOLIC CODING
2
PAGE:
o
Symbolic codes are a usual provision of an assembly language to allow the programmer to assign meaningful names to important information within his program.
For example, the fields of data in a payroll card are known to the programmer b.y
the type of information they contain, such as Employee Number, Department, Gross
Pay, etc. There is normally a limitation on the let).gth of a symbolic name. However,
this length is usually enough to permit meaningful abbreviations or contractions.
In the example above, the Employee Number field could be named EMPNO; the
Department field could be named DEP1"; the Gross Pay field could be named
GRPAY. As will be discussed in the section on memory mapping, the actual
addresses of these fields in memory are assigned by the assembler program. When
the name or label appears anywhere in the source language instructions, the assembler
program will use the assigned actual address in the object language instruction.
Symbolic labels are also assigned to instructions in the program which are referenced by other instructions in the program. When a non-sequential transfer of
control is required from one series of instructions to another, the programmer must
specify the point to which control is to be transferred. Since actual addresses are
assigned by the assembly program, the programmer cannot provide the actual
address. By labelling the instruction to which control is to be transferred, he can
use the symbolic address for the same purpose.
2.4.
RELATIVE CODING
Relative coding is another assembly system technique which allows the programmer
to specify the location of instructions and data, even though the actual addresses
are assigned by the assembly program. To use the relative coding technique, the
programmer must have a thorough understanding of the memory mapping operation of
the assembler program. Once this is understood, relative coding is a simple yet
powerful programming technique. In the preceding section on symbolic coding is an
explanation of the assembler program assignment of addresses to symbolic labels.
This creates a common fixed point of reference between the programmer and the
assembler program. By using this common fixed point of reference (the label) as a
base, the programmer can specify other locations by their position relative to the
base. For example, if the memory lo-<:ation which is to contain the information from
card column 1 has been given a label of DETCD, then the memory location which is
to contain the information from card column 5 would be 4 locations away. By
specifying an operand of DETCD + 4, the programmer causes the assembler program
to assign the actual address of the operand by mathematically adding the increment
of 4 to the actual address of DETCD. The assembly system usually provides for
decrements to symbolic labels as well as increments.
2.5.
MEMORY MAPPING
In order to assign the location of instructions and data, the assembler program must
keep track of the. locations that are used as the assembler processing is performed.
To do this, the assembler program contains an Instruction Location Counter (ILC).
------------------------
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UNIVAC 1005
UP-4084
SECTION:
This is a program created device, not a piece of hardware. The loading of the
assembler program itself usually sets the ILC to the actual address of the first
memory location. The assembler program then causes the reading.of the first
source language instruction. This instruction is assigned to an actual address
according to the present value of the ILC (in this case, the first memory location).
After the machine language for the instruction has been created by the assembler
processing, a card is punched containing the machine language instruction. The
number of locations that will be required to store the instruction is added by the
assembler program to the value of the ILC creating a new value in the ILC. The
assembler program then causes the next source language instruction card to be
read. This instruction is assigned to an actual address according to the present
value of the ILC. Assume that the actual address assigned to the preceding instruction had been R25/Cl and that the instruction was seven characters in length.
(R25/Cl becomes the address of the MSL of the instruction.) The assembler
program would then add seven (the number of locations for the first instruction) to
the machine code equivalent stored in the ILC, and arrive at the machine code
equivalent of R25/C8. This is the actual address assigned to the second instruction
assembled.
The use of this procedure by the assembler program insures that the assignment of
addresses to instructions follows the sequential access of the instructions by the
computer when the object program is executed.
In addition to an ILC, an assembler program may contain a Data Location Counter
(DLC). The DLC provides the programmer with the ability to assign locations to
his data in an area of memory other than the area to be used for instructions. Instructions are usually assigned to locations starting with the first memory address
(low-numbered locations) and proceeding in ascending sequence. Data is usually
assigned to locations starting with the last memory address (high-numbered
locations) and proceeding in descending sequence.
2.6.
3
2
ASSEMB LER-80
DECLARATIVE INSTRUCTIONS
An assembly system with an ILC and a DLC usually provides a set of pseudooperations which allow the programmer to establish and modify the value in the
location counters. In addition to the pseudo-operations which manipulate the ILC
and the DLC, there are usually other pseudo-operations which are required to
instruct the assembler program as to the manner in which the assembly processing
is to take place. These pseudo-operations are called declarative instructions.
Unlike the previously mentioned pseudo-operations, declarative instructions, which
are included in the source language deck, do not produce instructions in the object
language deck. The declarative instructions are for the use of the assembler
program during the assembly processing, and not for the computer as part of the
object program.
An example of a declarative instruction would be one that updates the DLC.
Assume the problem called for storing the contents of a header card to print headings
on each new page. The programmer would label the source language instruction
PAGE:
UNIVAC 1005
UP-4084
2
ASSEMBLER-SO
SECTION.
line, write the mnemonic pseudo-operation code that decrements the DLC, and
indicate the value of the decrement (the number of locations to be reserved for the
data). Such a line of source code might appear as
Label
HDRCD
4
PAGE.
o
OP Code
It of Locations
DA
80
(stands for Define Area)
When this line of source coding is encountered, the DA tells the assembler program
to refer to the DLC. The contents of the DLC are decremented by the number of
locations to be reserved. The new value of the DLC is assigned as the address
of HDRCD. In order to reference the information in the HDRCD area, the programmer
can use relative coding.
2.7.
I'
ASSEMBLER PROCESSING
An assembler program consists of a set of machine code instructions designed to
produce specific results. As is the case with any computer program, the assembler
program is designed to receive specific information prepared in a precise format.
It is the responsibility of the programmer to prepare the source language program
deck according to the rules of the assembly system. Any errors in the source
language will produce incorrect results from the assembler processing.
In order to produce a complete object program, the assembler program must read
the entire source program before producing any object instruction cards. During
the reading of the source cards, the assembler program performs a preliminary
analysis and converts or translates from source language to object language wherever possible, eg: the mnemonic operation codes. As each source card is read and
the mnemonic operation code is translated, the assembler program determines the
length of the instruction. The instruction is assigned to an actual address, and
the ILC is updated. If the source language instruction has been assigned a
symbolic address by the programmer, the label and the actual address are stored in
a table. When these labels appear in the source language instructions as Operand
addresses, the assembler program searches the label table using the symbolic
address as the key, and secures the actual address assigned to the label. The
actual address is substituted for the programmer's symbolic operand address.
0····
"
The assembler program contains many other tables which it references for conversion of th.e source language to object language. After complete analysis and conversion of the source language, the assembler program causes the object program
to be listed and punched.
o
--------~.- .
···--·-----~~~~ _ _
-·~__'____ _ _ _·~·"____ _ _ _ _ _ "L ____ _
UNIVAC 1005
UP-4084
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3.
INTRODUCTION TO
THE UNIVAC 1005
ASSEMBLY SYSTEM
Most of the programs for the UNIVAC 1005 will be written in the language of the
UNIVAC 1005 Assembly System. The UNIVAC 1005 Assembly System provides the
programmer with the necessary functions and convenience described in the preceding
section. The use of instruction forms not described in this manual deviates from
UNIV AC recommendations and must be the user's responsibility.
3.1.
TERMINOLOGY DEFINITIONS
Alphabetic means a letter from the English alphabet (A through Z)
Numeric means an Arabic numeral (0 through 9)
Alphanumeric means the entire 64 character set of the UNIVAC 1005 which includes
letters, numbers, and special characters.
C:
3.2.
CODING FORM
A coding form to be used to record the programmers instruction for subse quent key
punching and processing by the UNIVAC 1005 Assembler program is shown in
Appendix A. The coding form is set up in the same format as the punched card,
and contains an indication of the card columns to be used for each field.
3.2.1. LABEL
LABEL
Columns 1 through 5
!
I
I
: .1
I
c
1
3
ASSEMBLER-SO
This field is provided for the symbolic Labels assigned to those lines of coding
which are referenced by the object program instructions. A Label may consist
of from one to five characters (inclusive) and must begin in column 1 of the field.
The first (left-most) character of a Label must be an alphabetic character. The
remainder of the characters in a Label can be Alphabetic or Numeric. There is no
limit to the number of Labels in a source program. However, if the number of
labels exceeds the limit of the Assembler (approximately 40 labels for the 2 Bank
Assembler and 310 labels for the 4 Bank Assembler) extra processing is required
by the Assembler program. This is fully explained in the section on Operating
the Assembler System. Five positions are provided in the Label field to allow
meaningful assignment of programmer names. However, only the left-most three
positions of a Label are significant to Assembler processing. The first three
positions of each Label must be unique within a program. Extreme care should
be taken when creating Labels.
PAGE:
UNIVAC 1005
UP-4084
3
ASSEMBLER·SO
SECTION.
Labels used in a single program must be unique and may appear only once in the
Label field. Labels will be used in the Operand address portion of instruction
lines and may appear there as often as necessary. The explanations in this
manual of the use of the relative coding technique of increments and decrements
to Labels should enable the programmer to address the data in his program without
an excess of Labels.
2
PAGE:
o
The Label of a line of coding becomes the symbolic address for the left-most
(MSL) position of the instruction, and is used whenever the instruction is referenced.
Labels are also used for the lines of coding which define data areas, and become
the symbolic address for the left-most (MSL) position of the area set aside for
data.
Since not all1ines of coding require a label, the field may be left blank. Some
examples of labels are:
LABEL
1
!
B~E,G:I IN
I
I ,
I
S TI AI Rt T
I
I I i I
I
N,EIT: I
I
I
I
.& II : ,
I
I
3.2.2. OPERATION
Columns 6 through 10
c
OPERATION
6
I
,
I
I
This field is for the mnemonic operation codes provided by the Assembler.
Operation codes are usually alphabetic. The majority of Assembler Operation
codes are two characters in length, and must begin in column 6.
c
UNIVAC 1005
UP-4084
3
ASSEMBLER-80
SECTION,
Some examples of Operation codes are:
OPERATION
6
T,A
't DI
A. DI I I
SIU 1 I I
M1U1
o.VI I
EINID
I
OPERAND 1
I.
A.
*
FIELD A
12
INC.
18
I
(~-
±
I
I
3.2.3. OPERAND 1
This is a heading for those columns which are normally used to specify the
address of the MSL or LSL of OP 1 depending on the ascending or descending
mode of the instruction. This portion of the coding form is also used for other
purposes, since not all Operations involve an Operand 1. The following description of the OPERAND 1 fields is based on the normal use to specify OP 1
addresses. A complete explanation of Operand 1 addressing begins in Section 3.3.
3.2.3.1. IA
Column 11
This column is used to indicate Indirect Addressing. When the OP 1 of an instruction is a primary address, an asterisk (*) is placed in this column. It must
be left blank at all other times.
3.2.3.2. FIELD A
Columns 12 through 16
This fie-Idof the form will normally contain a programmer's symbolic address
for the location of instructions and data within his program. Any Labels which
appear here must also appear in the LABEL field of some line of coding. Field
A is a five position field for OP 1 Labels which always begin in column 12.
3.2.3.3. ± INC
Columns 17 through 20
These columns are normally used to indicate an increment to the address assigned to a Label. Increments are shown in decimal numbers. If column 17
contains a plus sign (+) the increment is added. If column 17 contains a minus
3
PAGE,
UNIVAC 1005
UP-4084
ASSEMBLER-SO
3
SECTION:
sign (-) the increment becomes a decrement and is subtracted from the Label
address. Increments must be left-justified (begin in column 18). Some examples
of OPERAND 1 addresses are:
4
PAGE:
o
OPERAND 1
I.
A.
*
FIELD A
±
INC.
18
12
D.E T CD
*
CIAITII
- 11 I
I I i I
I I
IIAl11
I
OPERAND 2
I.
A.
*
FIELD B
±
INC.
28
22
I
I
±
FIELD C
32
I
INC.
38
I
I
I
I
I
3.2.4. OPERAND 2
This is a heading for those co lumns which are normally used to specify the MSL
and LSL addresses of Operand 2 in the instruction. This portion of the form is
also used for other purposes. The following description of the OPERAND 2 fields
is based on the normal use to specify OP 2 addresses. A complete description of
OPERAND 2 addressing is found in Section 3.3.
3.2.4.1. lA, FIELD B, ± INC
Columns 21 through 30
These fields are normally used to specify the most significant location (MSL)
of OP 2. The description of the contents of these fields is the same as the
description of the contents of OPERAND 1.
3.2.4.2. FIELD C, ± INC
Columns 32 through 40
These fields are normally used to specify the least significant location (LSL)
of OP 2.
NOTE: The indication for OP 2 Indirect Addressing is in column 21 only.
Column 31 is not used as part of the specification for OP 2 LSL.
The description of FIELD C and ± INC is the same as the corresponding fields
of OPERAND 1.
o
UNIVAC 1005
UP-4084
3
ASSEMBLER-SO
c
PAGE:
COMMENTS
-
56 57
41
I
3.2.5. COMMENTS
5
SECTION:
I
I
I
I
I
I
I
I
I
I
I
61 '
I
Columns 41 through 61
This portion of the form is provided to allow the programmer to include pertinent
comments as to the purpose of the line or lines of coding. The comments are not
considered by the Assembler processing and merely pass through to the printed
and punched output. These columns are also used to indicate constant values
which are to be included in the object program. This use is described in the
section which covers Constants. Comments used for (1) DC operations, (2)
Comma (,) operations, (3) In line constant operations (*), and Comment Card
operations may not extend beyond column 61. Comments for all other source code
operations may not extend beyond column 56.
CARD NO.
PG LN
62
64
('
3.2.6. CARD NUMBER
~i
Columns 62 through 66
This portion of the form is subdivided into three fields--PAGE NUMBER, LINE
NUMBER, and INSERT NUMBER. These columns are used to indicate the number
of the page of coding, and the number of the line from which the key punched card
was produced. The Card Number field will assist the key punching effort as well
as provide for the re-sequencing of the cards in the event the original sequence is
disturbed. For proper assembly processing, it is necessary that the cards be read
by the Assembler program in the sequence in which they appear in the source
program. The Card Number field is used for external control purposes only. The
Assembler program does not check the sequence as it reads the card.
The INSERT NUMBER column is provided as a facility to insert additional lines
of coding in a source program, after the initial effort, without disturbing the
sequence established by Page and Line Number.
During the assembly processing, the Assembler program assigns a consecutive
number to the output cards in the object program deck. The Assembler assigned
card number is punched into columns 62 through 65. Column 66 is blank in the
output card.
3.2.7. REMAINDER
The remainder of the card columns are not examined by the Assembler program, and
are available for whatever use the programmer may determine. Such things as Job
Number, Programmer's Initials, and Date may be included on a repetitive punching
basis. These items will not appear in the object deck or on the output listing
produced by the Assembler. Card Columns 67 through 73 are used for the object
language instructions, and columns 74 through 80 are used for instructions to the
Load program.
I
I
I
UNIVAC 1005
3
UP-4084
i;
6
ASSEMBLER-SO
SECTION:
PAGE:
--------~----------------------------------~--------~~~~--~~~~----I
3.3.
c
OPERAND 1 ADDRESS SPECIFICATION
There are several methods of specifying operand addresses in the UNIVAC 1005
Assembly System. A description of the most commonly used methods follows below.
3.3.1. Symbolic Address
(Label)
Specification
A definition of a symbolic address and some examples of Labels have been given
in preceding sections. In the UNIVAC 1005 Assembly System, when a Label is used
on a line of coding which defines a data area, that line of coding also includes the
length of the area to be allocated to the data. The Label is theri used to specify
the MSL of the data area. By placing a plus sign (+) as a prefix to the Label when
it is used as an operand address, the programmer can specify the LSL of the data
area.
Example: A Declarative has been used to establish a data area of six positions
with a Label NAME. Assume the data area has been allocated in
memory as:
COLUMN
ROW
25
I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I 9 110 111 I 121
NAME
The following use of the Label NAME as an Operand 1 address of a TRF -D instruction would then cause a substitution of R25/C6, since a Label specifies the
MSL of the area.
LABEL
I.
A.
*
6
1
I
I
I
I
OPERAND 1
OPERATION
I
'tD
FIELD A
±
INC.
18
12
NAME
The use of the plus sign (+) prefix to the Label NAME as an Operand 1 address
in a TRF-A instruction would then cause a substitution of R25/Cll, the LSL of
the area.
LABEL
I.
A.
*
6
1
OPERAND 1
OPERATION
FIELD A
12
±
INC.
18
I
, , :I ,
T,A I
I
+,N,A,M1E
c
---------------------------------
,
..c"."""_.~ •. ~_,,~_,,_.~,,_~L, ___ ~~_,,,.
,~,'~_,'
.-"-,,-,~,,'.,',-,~-~,~"-
~.'---"~-r~~-
""", ,"'" "..
"'''''_._,--~
UNIVAC 100S
UP-4084
SECTION:
NOTE: The plus sign (+) can be used as a prefix to 5 character Labels by coding
the first 4 characters only. The first 3 characters are significant to the
Assembler program.
Labels must be coded starting in the left-hand position of Field A (column 12).
If the plus sign (+) prefix is used, it must appear in column 12, and the Label
starts in column 13.
3.3.2. Increments To Symbolic Addresses
When a Label has been placed on a line of coding, the programmer knows that the
Assembler program is going to allocate the number of memory locations required by
that line of coding, and will also assign an actual address to the Locations. The
programmer does not know the actual address which will be assigned, but he knows
that the use of the same Label will cause the Assembler program to substitute whatever actual address was assigned. Based on this knowledge, the programmer is then
able to specify the address of locations relative to his line of coding. This is
accomplished by indicating an increment or decrement to the Label in the ± INC
field of the Coding form.
Assume that allocation has been made according to the previous example. The
following coding would cause the Assembler program to produce these substitute
addresses:
c
OPERAND 1
I.
A.
*
FIELD A
±
INC.
18
12
= address R25/C7
N,A,ME,
(MSL + 1)
+ 1
I I
= address R25/Cll (MSL + 5 = LSL)
NIAIMIEI
+ 51 I
I I I I
I I
= address R25/CI0 (LSL - 1)
+IN1A1M E- 11 I
I I
I
I
+ N,AM,E- 5
I I I I
NIAIMIEI
= address
R25/C6
(LSL - 5
= MSL)
I
I I
= address R25/C3
(Outside of area)
- 31
I
+NAME + 11
I
7
3
ASSEMBLER-SO
= address R25/C12 (Outside of area)
I
It should be noted that the use of increments is
not restricted to addresses within the area allocated
by the line of coding.
PAGE:
A_S_~N_E_I~_~_C_L_~_~_~_8_0
___
U_P_-_40_8_4_...I._ _ _ _ _ _ _ _ _
_
When an increment is used, a plus or minus sign must appear in column 17, and the
amount of the increment (in decimal numbers) must start in column 18.
3.3.3. Decimal Addressing
As mentioned in Section 1.1., decimal addressing is provided for by the UNIVAC
1005 Assembly System. This technique allows the programmer to consider the
layout of Input Output, instructions, and data in a consecutive sequential manner.
This eliminates the problems associated with advancing that takes place in Row
and Column addressing.
When a decimal address is specified to the Assembler program, the decimal number
is converted to the two-character address required in the object language.
Decimal addresses take the following form:
l:( N through l:( NNNN
= the special character lozenge which indicates to the Assembler
program that what follows is a decimal number.
l:(
= a decimal number which must be left-justified.
N through NNNN
Indirect Addressing is allowed with decimal addressing.
Examples of decimal addressing
OPERAND 1
I.
FIELD A
A.
*
'NC.
18
12
l:( 11
±
= First location of Read Input Storage (Rl/C1, Bank 1)
I
l:( 8 I O.
l:(19 16,2
= Last location of Read Input Storage (R3/C18, Bank 1)
I
l:(11 19.2 12
1 1
= First location in Bank 2 (R1/C1, Bank 2)
I
= Last location in Bank 2 (R31/C31, Bank 2)
I
I:
_ _ _ _ _ _............._ _ _ _ _......I.,;;S,;;;E,;;,C.;,;TI;.,;;;O.;,;N.;.,'_3_ _...L.;.,PA;.;.G;;.;E:,;.,_8_ _ _
When decimal addressing is used, the lozenge (l:() must appear in column 12. The
decimal number must begin in column 13. The decimal number cannot exceed 4
digits, since the maximum address is l:(3844 (four bank system).
3.3.4. Row And Column Addressing
Rowand Column addressing is used when the programmer knows the actual address
of the data. An actual or absolute address in the UNIVAC 1005 is specified by two
6-bit characters which are converted by the computer circuitry into Row, Column
and Bank. Rowand Column addressing in the UNIVAC 1005 Assembly System
allows the programmer to specify Row, Column, and Bank eliminating the need to
memorize or reference tables of the two-character codes required in the object
program.
o
UNIVAC 100S
UP-4084
Rev. 1
ASSEMBLER·80
3
SECTION.
The following format is used to specify Rowand Column address:
$RRCCBn
$ is the indication to the Assembler program that what follows is a Row
and Column address
RR
=the numeric Row Number (1 - 32)
CC = the numeric Column Number (1 - 32)
B
must be placed in the ± column of the OPERAND field
=the
n
numeric Bank Number (1 - 4)
Example:
OPERAND 1
I.
A.
• 12
FIELD A
t
INC.
18
MSL of Read Input
'$ 0 1 0 1 B 1
LSL of Read Input
$10131118 B 111
1
jlt
1
I
LSL of rX
$131213 1 B 21 1
Indirect Addressing can be specified with machine-oriented addresses by placing
an asterisk (*) in the appropriate column (11 or 21) of the form.
The $ must appear in column 12, 22, or 32, and the letter B must appear in column
17, 27, or 37. Increments to Rowand Column address are not allowed.
Rowand Column address is also used to specify the address of the Special
Registers.
3.3.5. Instruction Location Counter (ILC) Addressing
The ILC is the counter in the Assembler program which keeps track of the allocation of memory locations to instructions. The use of the current value of the
ILC for addressing purposes is provided by the UNIVAC 1005 Assembly System.
Proper use of this technique is based on the programmer's knowledge of the memory
mapping process of the Assembler program. (See Section 2.5).
The $ character, alone, in the left-hand position of Field A, Field B, or Field C
of the coding form, instructs the Assembler program to use the current value of the
MSL of the instruction being assembled as the address for the A, B, or C portion
of the object instruction. An increment or decrement to the address currently in
the ILC can also be specified in the ± INC fields for each address. This increment
or decrement does not change the value of the ILC itself. The maximum increment
or decrement ·is 961.
9
PAGE.
UNIVAC 100S
UP-4084
SECTION.
Example 1: Assume the value of the ILC is J:l745 (R25/C1, B1)at the time the
following descending transfer instruction is to be assembled.
I.
A.
*
6
1
!
I
I
I
I
TIDI
1
PAGE.
o
OPERAND 1
OPERATION
LABEL
10
3
ASSEMBLER·SO
FIELD A
INC.
18
12
$
1
±
I
+ 7
I
$ + 7 produces an address of 752 (745 + 7) which is the address which will be
assigned to the next instruction.
Example 2: The following coding of a descending transfer instruction will cause
the instruction itself to be transferred.
LABEL
OPERATION
I.
A.
*
6
1
OPERAND 1
FIELD A
±
INC.
18
12
I
1
1
:
I
3.4.
1
TIQ
1
1
$11
1
I
-L
OPERAND 2 ADDRESS SPECIFICATION
The rules for OPERAND 1 address specification (Section 3.3.) apply to OPERAND
2 address specification.
3.4.1. Operand 2, Field C, Blank Addressing
The majority of UNIVAC 1005 Operations require the specification of an A address
(OP 1 MSL or LSL), a B address (OP 2, MSL), and a C address (OP 2 LSL). The
UNIVAC 1005 Assembly System allows the programmer to leave the Field C portion
of the source language instruction blank when a symbolic address is used in Field
B. When a Label is used in the Field B portion of the instruction, the Assembler
program references the Label Table to acquire the MSL address of the area it has
assigned to the Label. The same reference to the Label Table will also produce
the LSL address of the assigned area which the Assembler program will then automatically include in the object instructions as the C address.
If Field B of the instruction does not contain a Label, automatic (blank) addressing
will not be performed. If the Field C portion of the instruction contains any information, automatic (blank) addressing will not be performed, and the address
specified in Field C will be used. If the LSL of the area indicated by the Label
in Field B is not to be used, the programmer must specify the desired address in
Field C.
For the following examples, DATA is the Label of a 6 character field assigned by
the Assembler program to R25/C1, B1 (MSL) through R25/C6, B1 (LSL).
o
'uNlv'At'i'iios~
UP-4084
" ....... '~~~~-"'-~""T"---SECTION:
Example 1:
OPERAND 2
I.
A.
*
FIELD B
±
22
FIELD C
INC.
28
±
32
INC.
38
DA T A
J
.L
The Assembler program will automatically assign R25/C6, Bias the C address.
Example 2:
OPERAND 2
I.
A.
*
FIELD B
±
22
FIELD C
INC.
28
+,D,A,T,A
±
32
.1
j
1
INC.
38
,
I ,
The coding in Field B specifies that the LSL of DAT A (+ prefix) is to
be the MSL of the instruction. The blank Field C specifies that the
LSL of DATA is to be the LSL of the instruction. This coding produces a one character operand with an MSL and LSL of R25/C6, B 1.
Example 3:
OPERAND 2
FIELD B
I.
A.
*
±
22
DATA
INC.
FIELD C
28
32
+ 3
-'
±
INC.
38
i
II
Field B specifies that the MSL of DATA plus 3 locations (R25/C4,
B 1) is the MSL of OP 2. Again the blank Field C will automatically
produce the LSL of DATA (R25/C6, Bl) as the LSL of OP 2. OP 2
is a 3 character operand.
Example 4:
OPERAND 2
FIELD B
I.
A.
*
22
11
3
ASSEMBLER-SO
±
INC.
28
+ ID A T A- 3
FIELD C
32
±
INC.
38
+D A TA - 1 I
I
PAGE:
UNIVAC 1005
UP-4084
3
ASSEMBLER·SO
SECTION:
Field B specifies that the LSL of DATA (+ sign) - 3 (R25/C3, H1) is
to be used as OP 2, MSL. The presence of information in Field C
prevents the automatic (blank) addressing of OP 2, LSL. Field C
specifies that the LSL of DATA (+ sign) -1 (R25/C5, B1) is to be
used as the LSL of OP 2. OP 2 is a 3 character operand.
12
PAGE:
o
3.4.2. Operand 2 Indirect Addressing
As explained in Section 1.6., Indirect Addressing utilizes a primary address in the
instruction which specifies the location of a secondary address in memory which
contains the address of the data to be used in the Operation.
When Indirect Addressing is used for OP 2 of an instruction, the primary address
in the instruction must refer to the MSL of a 4 character location that contains the
secondary address. A 4 character secondary address is necessary due to the fact
that OP 2 of the object instruction must specify a 2 character MSL address and a
2 character LSL address.
The specification of Indirect Addressing will cause the UNIVAC 1005, at object
execution time, to perform a 4 location descending transfer from the address
specified in the B portion of the instruction to the Band C portions of the Instruction Register. The OP 2 will then be accessed based on the new addresses
in the Instruction Register.
If a Label is used with OP 2 Indirect Addressing, the Label is specified in Field
B, and Field C is blank. The Label in Field B must specify an assigned area of
4 characters which contain a B and a C address. The UNIVAC 1005 Assembly
System provides a pseudo-operation which is used for this purpose. (See the DI
Operation, Section 4.10 .. 4.) OP 2 Indirect Addressing is specified by an asterisk
(*) in the IA Field of OPERAND 2 (Column 21). No indication is made in Column
c
31.
Example: Label JOE has been defined as the primary address for the secondary
address DATA. DATA has been defined as a 6 character area. JOE has
been assigned to locations J::t 801 through J::t 804. DATA has been assigned to locations J::t 745 through J::t 750. Thus, in location J::t 801 and
J::t 802 is the machine code equivalent of J::t 745, and in location J::t 803
and J::t 804 is the machine code equivalent of J::t 750.
The following coding will produce a correct Indirect Address reference
to DATA as the OP 2 of an instruction.
OPERAND 2
I.
A.
FIELD B
*
22
*
.TIO E
±
INC.
28
FIELD C
32
±
INC.
38
c
,
....... ,,"---"-- ,---_._--..
UNIVAC 100S
UP-4084
3
ASSEMBLER-SO
.I:CTIONr
When decimal or Row /Column Indirect Addressing is used. Field B must specify
the MSL of the location of the 4 character secondary address.
Example 1:
Same as above
OPERAND 2
I.
A.
FIELD B
*
22
*
txlS ,0,
±
INC.
28
I,
±
FIELD C
I
I
INC.
38
32
I
I
I
L
I
~
R25/C25, Bl = 801
Example 2:
OPERAND 2
FIELD B
I.
A.
*
*
22
±
INC.
28
FIELD C
32
±
INC.
38
$1 2 5 2 5 B 1
L _L
3.5. SUMMARY OF FIELD A, FIELD B, AND FIELD C SPECIFICATIONS
3.5.1. FIELD A
Field A of the source language instruction may specify:
1. LSL address of OP 1
2. MSL address of OP 1
3'. Decimal digits
4. Octal digits
5. Test bit conditions
6. Destination address of JUMP TEST Operation
7. Two machine language characters
3.5.2. FIELD B
Field B of the source language instruction may specify:
1.
2.
3.
4.
5.
6.
7.
c
MSL address of OP 2
MSL address of OP 1
Set condition bits
Decimal digits
Octal digits
Destination address of JUMP TEST Operations
Two machine language characters
13
PAGEr
UNIVAC 1005
UP-4084
Rev. 1
ASSEMB LER-80
14
3
SECTION:
PAGE:
o
3.5.3. FIELD C
Field C of the source language instruction may specify:
1. LSL address of OP 2
2. Two machine language characters
NOTE: Those specifications not previously explained will be covered in the
Section with the instructions that require or allow the specification.
3.6.
STANDARD SYSTEM LABELS
In addition to the programmer assigned symbolic Labels previously discussed, the
UNIV AC 1005 Assembly System provides 15 Standard Labels for predesignated
areas of main store. These Standard Labels are not counted in with the number of
Labels assigned by the programmer. The purpose of the Standard Labels is to
provide uniformity of assignment of these predesignated areas, and reduce the processing time of the Assembler program for handling repetitive references to these
areas.
The Standard Labels and predesignated areas are:
STANDARD LABEL
DECIMAL ADDRESS
PREDESIGNATED AREA
ROW/COLUMN ADDRESS
$Rl
SO Column Reod Input
%:(
1 • %:( SO
Rl/Cl.R3/C1S, Bl
$R2
2nd Ha If af 160 Col. Reod
Code Image
%:( Sl • %:(160
R3/C19·R6/C5, B 1
$RC
160 Column Read Code Imoge
%:(
Rl/Cl·R6/C5, Bl
$PR
132 Column Print Starage
%:( 161 • %:(292
R6/C6·R 10/C13, B1
$Pl
SO Column PUNCH Storage
%:( 293 • %:( 372
Rl0/C14·R12/C31, Bl
$Pl
SO Column Read/Punch Read
Storage
%:( 293 - %:( 372
Rl0/C14·Rl2!C31, Bl
$P2
SO Column Read/Punch Punch
Storage
%:( 373 • %:( 452
R13/C1·R15/C1S, B1
$PC
160 Column Code Image
Punch Storage
%:(293· %:(452
R 10/C 14·R 15/C lS, B 1
$Zl
160 Column Read/Punch
Code Image Read Storage
%:( 293 • %:( 452
RI0/C14·R15/C1S, Bl
$Z2
160 Column Read/Punch Code
Image Punch Storage
%:(453 • %:( 612
R 15/C19·R20/C23, B 1
$BM
First Location beyond Input
Output Storage
%:(613
R20/C24, Bl
$IR
Instruction Register
None
R32/C1.R32/C7, B 1
$CC
Instruction Control Counter
None
R32/CS·R32!C9, B 1
$XR
Register X
None
R32/C1·R32/C31, B2
$TR
Translation Table
or
$S f1
First SO Positions of
Print Area
$AR
Arithmetic Register
1 • %:( 160
%:( lS2S • %:( lS91
%:(3750 • %:(3S13
or
R2S/C30-R30/C31,B2
R2S/C30·R30/C31,B4
R6/C6·RS/C23
None
o
R32/Cl.R32/C31,B 1
o
UNIVAC 1005
UP-4084
ASSEMB LER-80
3
SECTION:
The Assembler processing associated with Standard Labels is the same as for the
Labels assigned by the programmer. That is, the use of a Standard Label as an
address specification within a line of coding will cause the Assembler program to
substitute the MSL of the area identified by the Standard Label. The LSL address
is also specified and substituted in the same manner as for programmer's Labels.
The Standard Label $TR refers to the required location for translation tables when
the hardware translate option of the UNIVAC 1005 is part of the object system.
15
PAGE:
c
c
c
r-----
UNIVAC 1005
UP-4084
ASSEMB LER·80
4.
4
Rev. 1
SECTION:
UNIVAC 1005 ASSEMBLY
SYSTEM INSTRUCTIONS
This section of the manual covers the instruction repertoire of the UNIV AC 1005
as programmed through the language of the UNIVAC 1005 Assembly Systems and
the declarative instructions which direct the processing of the Assembler program.
4.1.
LEGEND
The following abbreviations are used in the description of the UNIVAC 1005
Assembly System.
1L
1M
2L
2M
3L
K
D
CC
NI
( )
(-
~
)S
IA
= Operand 1, LSL
= Operand 1, MSL
= Operand 2, LSL
= Operand 2, MSL
= least significant location of quotient or product
= any alphanumeric character
= any numeric character
= characters whose bit positions represent Condition Indicators
= MSL Address of the next instruction to be executed
= contents of the area specified within the parentheses
= transfer to
= a blank column (space code), used to establish positional notation
= Indirect Addressing
NOTE: For a description of Operand·1, Operand 2, and the UNIVAC 1005 machine
language instructions, see Section 1.2.
4.2.
LENGTH OF OPERANDS
The length of the Operand(s) in a UNIVAC 1005 instruction is normally defined by
the addresses of Operand 2. An instruction is normally terminated when the last
location (LSL if descending mode, MSL if ascending mode) of OP 2 has been
handled. This means that the number of locations in OP 1 must be the same as
the number of locations in OP 2. The maximum size operand for a transfer, arithmetic,
or compare instruction is 961 locations unless otherwise specified.
c
If the lengths of the Operands (as defined by the programmer) to be processed in an
instruction are not the same, special programming involving the use of Register X
is required. The "Transfer to rX" (TX) command allows the programmer to specify
OP 1, MSL and OP 1, LSL, thus defining the length of OP 1. (See Section 4.3.6.
for complete description of TX.) The destination (OP 2) of the TX command is rX
(31 positions). The TX instruction performs an Ascending Transfer of OP 1 to rX,
beginning at the LSL of each. When the OP 1, MSL (as specified in the instruction)
has been transferred to rX, access of OP 1 is terminated. The TX instruction
continues, transferring space codes into the excess positions of rX until the MSL
of rX has been filled. This signals the end of the instruction.
1
PAGE:
UNIVAC 1005
UP-4084
4
ASSEMBLER·80
SECTION.
After transferring the smaller of the two Operands to rX, the programmer then uses
the appropriate location in rX as the OP 1 address of the instruction which does the
required processing. This insures the use of space codes in the locations which are
added to make the length of OP 1 equal the length of OP 2. This condition is
particularly important for the Arithmetic, the Compare, and the Transfer instructions.
2
PAGE:
o
Following is an example of the incorrect use of unequal length Operands and the
erroneous result produced, as well as an example of the use of the TX command to
produce correct results.
-Ix I Ix Ix------I
OP 1
Given:
...............
g
X
X
708
703
701
---------.
OP 2
710
Locations J:l703
- J:l708 contain
the OP 1 data
(6 locations).
...............
--------------------
808
801
Locations J:l801 - J:l808 is
to be the OP 2 (8 Locations)
Example 1: If an Ascending Transfer of OP 1 to OP 2 is executed, the results in
the OP 2 locations would be
X
X
X
X
808
801
o
since the length of OP 2 (8 Locations) determines the length of the
Operand 1.
Example 2: If a Descending Transfer of OP 1 to OP 2 is executed, the results in
the OP 2 locations would be
I I
X
801
X
X
X
X
X
808
since the length of OP 2 (8 Locations) determines the length of
Operand 1.
In Examples 1 and 2, extraneous locations (the Z's and V's) which are not part of
OP 1 would be transferred. If an Arithmetic instruction was executed using the
same operands, the locations containing the Z's would become part of the OP 1 and
would be combined with the values in J:l801 and J:l802, producing an erroneous result.
Using the same conditions given for the preceding examples, the following example
methods can be used to produce correct results.
o
I
-~~---
----
----~~~~~~~~~~~~~~-~~~~~~~~
UNIVAC 1005
UP-4084
4
ASSEMBLER-SO
3
SECTION:
PAGE:
Example 3: Instruction 1. Transfer OP 1 to rX using the TX command. The TX
command provides for specification of OP 1, MSL and LSL.
OP 1
.-
...............
X
X
X
X
X
703
R32, B2
)S
I I
X
708
rX
14
1
I
I
25
31
26
Instruction 2: Ascending Transfer specifying the LSL of rX ($3231B2) as OP 1,
LSL to the destination OP 2 (}:t801 - }:t808). The length of the OP 2 (8 locations)
will cause the low-order 8 locations of rX to be transferred. This will produce the
following results in OP 2.
X
X
X
X
801
(-.
808
Example 4: In order to perform Arithmetic instructions on Operands of unequal
length, the type of operation performed in Instruction 1, Example 3
would establish OP 1 in rX. The length of the OP 2 of the Arithmetic
instruction would then control the number of locations to be used from
rX (including high order spaces).
Instruction 1: Transfer OP 1 to rX
I5 I5
703
Row 32, B 2
)S
14
5
5
5
5
708
1 -I)S
1
1
25
5
5
5
5
5
5
31
26
Instruction 2: Assume an ADD-ALG instruction
OF 11
Row 32, B 2
J
1
Original OP 2
Final OP 2
\
)S
I24:1 ~\
)S
5
'15 :\
=
801
808
801
808
=
.... --_....
----.-""--.------.--~.
-~~--.-~
- - -.. ---
- ·---·c·--·-------
UNIVAC 1005
UP-4084
4
ASSEMBLER-SO
SECTION.
4
PAGE.
I
I
\
Example 5: In order to perform a Descending Transfer producing a result of the
smaller OP 1 left-justified (in the most significant locations) in OP 2
and spaces in the remaining low-order positions of OP 2, two instructions
are required.
c
Instruction 1: Descending Transfer, specifying the portion of the OP 2 locations
which are to receive the significant data, as the OP 2 of the TD
instruction.
-I
OP 1
...............
X
703
---
I
X
X
X
X
708
OP 2
...............
X
I I
X
X
X
X
X
I I
801
X
unk
unk
806
807
808
Instruction 2: Use the Transfer Constant (TK) Instruction to transfer space codes
to the low-order positions of OP 2. (See Section 4.3.5 for a description of the TK instruction.) This will produce the desired result.
X
X
X
I
X
801
808
An alternate method to produce the results indicated by Example 5 can
be:
(1) A TX of Operand 1 to the XR.
(2) A TD of R32C26 to locations 801 through 808. The TD instruction
will "wrap around" and pick up two blank characters from R32C1 a
and R32C2, thereby producing a left justified result.
4.3.
TRANSFER INSTRUCTIONS
4.3.1. TRANSFER DESCENDING
Mnemonic:
LABEL
TD
Mode:
OPERATION
Length: 7
OPERAND 1
I.
A.
*
6
1
DESCENDING
FIELD A
±
YES
OPERAND 2
INC.
18
12
IA:
I.
A.
*
FIELD B
22
±
INC.
28
I
I I '
I
I
TIDI I
1 MI
I
-----_._------_._-
I
21M
I
±
FIELD C
I
.-------~-.-
2,L,
INC.
38
32
,
..1 ..1
c
UNIVAC 1005
UP-4084
Rev. 1
ASSEMBLER-SO
4
Function:
Transfer descending beginning from OP 1 - MSL specified by Field A; to OP 2 MSL specified by Field B, until OP 2 - LSL specified by Field C has been filled.
Example 1:
Given: A 6 location area with the Label CAT has been allocated to R31/Cl
through R31/C6 in Bank 1 (r:t931 through r:t936).
Problem: Transfer Descending the data from card columns 4 through 9 to the area
CAT.
LABEL
OPERATION
OPERAND 1
I.
6
1
A.
*
FIELD A
OPERAND 2
INC.
1:
18
12
I.
A.
*
FIELD B
INC.
1:
22
28
FIELD C
1:
INC.
38
32
I
I
I
I
TD
$ Rll
I
+ 3
C A.T
I
FIELD A; OP 1, MSL:
The Standard Label $R 1 specifies the MSL of Read Input Storage (the location of
card column 1). The increment of +3 causes the MSL of this OP 1 to be the
location of card column 4. $0104Bl or r:t4 can be used to specify the same OP 1,
MSL since the location is known to the programmer.
FIELD B; OP 2, MSL:
The programmer's Label CAT specifies the MSL of the area assigned to CAT by
the Assembler program.
NOTE: $3101Bl or r:t931 could not be used since the programmer does not know
the actual address which will be aSSigned to area CAT.
FIELD C: OP 2, LSL:
Blank addressing will cause the Assembler program to use the LSL address of
the area specified by the Label in Field B. The programmer can also use CAT
+ 5, or + CAT in Field C and produce the same result.
Example 2:
Given: The same area with the Label CAT from example 1. Also, a 6 location
area with the Label DOG has been allocated to Rl/Cl through Rl/C6 of Bank 2
(r:t962 through r:t967).
Problem: Transfer Descending the (CAT) to DOG.
LABEL
OPERATION
6
1
OPERAND 1
I.
A.
*
FIELD A
1:
OPERAND 2
INC.
FIELD B
I.
A.
•
18
12
22
1:
INC.
28
FIELD C
32
1:
INC.
38
I
~ I
lI
I
TID ••
~A,T,
I
I
D,O G I
I
I
I
5
PAGE:
SECTION:
I
UNIVAC 1005
UP-4084
4
ASSEMBLER·SO
SECTION.
6
PAGE.
o
FIELD A; OP 1, MSL:
The Label CAT specifies the MSL address of the area assigned to CAT.
FIELD B; OP 2, MSL:
The Label DOG specifies the MSL address of the area assigned to DOG.
FIELD C; OP 2, LSL:
Blank addressing will cause the Assembler program to use the LSL address of the
area specified by the Label in Field B. The programmer can also use DOG + 5,
or + Dog in Field C and produce the same result.
NOTE: Row/Column or Decimal Addressing can not be used for any of the
addresses, since the actual locations of the data are not known by the programmer.
Example 3:
Problem: Transfer the entire contents of the card in Read Storage to the first 80
print positions of Print Storage.
LABEL
OPERATION
I.
A.
*
6
1
:
TiD ••
OPERAND 1
I
FIELD A
12
$,R •1 ••
I
±
OPERAND 2
INC.
I.
A.
18
*
•
±
FIELD B
$.P,R,
INC.
28
22
I
±
FIELD C
32
•
I
$,P, R•
INC.
38
•
t
7 19
I
FIELD A; OP 1, MSL:
The Standard Label $R1 specifies the MSL of the Read Input Storage area.
$010 1B1 or ):(1 could have been used.
FIELD B; OP 2, MSL:
The Standard Label $PR specifies the MSL of the Print Storage area $0606B1 or
):(161 could have been used.
FIELD C; OP 2, LSL:
Blank addressing can not be used, since this would cause the Assembler program
to use the LSL of $PR, the last column of the Print Storage area. $PR t 79 is
the address of Print position 80 which should be the LSL of OP 2. $0823B1 or
):(240 could have been used.
o
UNIVAC 1005
UP-4084
4
Rev. 1
ASSEMB LER-BO
SECTION,
Example 4:
Problem: Transfer the data from column 80 of an input card to column 80 of an
output card.
LABEL
OPERATION
I.
A.
*
6
1
:
TLD,]
OPERAND 1
FIELD A
±
OPERAND 2
INC.
18
12
+,$lR, 1 l
1
I.
A.
*
±
INC.
28
+,$, P ,1 1
I
I
FIELD B
22
FIELD C
±
32
INC.
38
•
I I , ,
I
1
I
FIELD A; OP 1, MSL:
The plus sign (+) prefix to the Standard Label $R1 specifies the LSL of Read
Input Storage as the MSL of OP 1. $0318B1 or J:l80 could have been used.
FIELD B; OP 2, MSL:
The plus sign (+) prefix to the Standard Label $P1 specifies the LSL of Punch
Storage as the MSL of OP 2. $1231B1 or J:l372 could have been used.
FIELD C; OP 2, LSL:
Blank addressing in Field C specifies the LSL of the area whose Label is in
Field B. (The plus sign in Field B does not constitute part of the Label. It
instructs the Assembler program to use the LSL address of the labeled area.)
$1231B1 or J:l372 could have been used.
NOTE: Since OP 2, MSL and OP 2, LSL specify the same address, a one location
Operand is produced.
4.3.2. TRANSFER ASCENDING
Mnemonic:
LABEL
TA
Mode:
OPERATION
6
1
ASCENDING
Length:
7
OPERAND 1
I.
A.
*
FIELD A
12
±
YES
IA:
OPERAND 2
INC.
18
I.
A.
*
FIELD B
22
±
INC.
28
FIELD C
32
±
INC.
38
I
i
L
!I
1
TlAI I ,
I,Ll' I
21M
1
2,L,
,
Function:
Transfer ascending beginning from OP 1 - LSL specified by Field A; to OP 2 LSL specified by Field C, until OP 2 - MSL specified by Field B has been filled.
Example 1:
Given: A 6 location area with the Label CAT has been allocated to R31/C1
through R31/C6 in Bank 1 (J:l931 through J:(936).
c
7
PAGE,
UNIVAC 100S
UP-4084
4
Rev. 1
ASSEMB LER-80
SECTION,
Problem: Transfer Ascending the data from card columns 4 through 9 to the area
CAT.
LABEL
OPERATION
I.
A.
*
6
1
l
I
OPERAND 1
T,A, ,
FIELD A
OPERAND 2
±
INC.
18
12
$,R, I, ,
I.
A.
*
+ 8
FIELD B
±
22
INC.
28
±
FIELD C
32
INC.
38
CIA T
I
FIELD Ai OP 1, LSL:
$Rl is the Standard Label for the MSL of Read Input Storage (the location of card
column 1). The increment of + 8 causes the LSL of this OP 1 to be the location
of card column 9. $0109Bl or J:l9 can be used to specify the same OP 1, LSL
since the location is known to the programmer.
FIELD Bi OP 2, MSL:
The programmer's Label CAT specifies the MSL of the area assigned to CAT by
the Assembler program.
NOTE: $3101Bl or J:l931 could not be used since the programmer does not know
the actual address which w ill be assigned to area CAT.
FIELD Ci OP 1, LSL:.
Blank addressing will cause the Assembler program to use the LSL address of
the area specified by the Label in Field B. The programmer can also use CAT
+ 5, or + CAT in Field C and produce the same result.
Example 2:
Given: The same area with the Label CAT from Example 1. Also, a 6 location
area with the Label DOG has been allocated to RIICl through RI/C6 of Bank 2
(J:l962 through J:l967).
Problem: Transfer Ascending the (CA T) to DOG.
LABEL
OPERATION
OPERAND 1
I.
1
,
, I ' ,
A.
6
*
TIAI ,
FIELD A
12
+,C,A,T,
±
OPERAND 2
INC.
18
I.
A.
*
,
I
FIELD B
22
D,O,G, I
±
INC.
28
±
FIELD C
32
I
I
INC.
38
,
I
,
FIELD Ai OP 1, LSL:
The Label CAT with a plus sign (+) prefix specifies the LSL of the area assigned to CAT.
FIELD Bi OP 2, MSL:
The Label DOG specifies the MSL of the area assigned to DOG.
-
-----..
~~-.----
...
--~--.-------
-----------
1
8
PAGE.
I
c
UNIVAC 1005
UP-4084
4
ASSEMB LER-BO
SECTION:
FIELD C; OP 2, LSL:
Blank addressing will cause the Assembler program to use the LSL address of the
area specified by the Label in Field B. The programmer can also use DOG + 5,
or + DOG in Field C and produce the same result.
NOTE: Row/Column or Decimal Addressing can not be used for any of the
addresses, since the actual locations of the data are not known by the programmer.
Example 3:
Given: A 7 position location with the Label XT1 as the last instruction of
a subroutine.
Problem: Transfer Ascending the previous 7 character instruction to the exit line
XT1 of the subroutine.
LABEL
OPERATION
I.
A.
*
6
1
I
:
OPERANO 1
TA
FIELO A
OPERANO 2
±
INC.
12
18
$
- 1
I.
A.
*
FIELO B
±
22
INC.
28
XT I i
I
J
1
±
FIELO C
32
INC.
38
J
j
_I
_I
I
FIELD A; OP 1, LSL:
$-1 instructs the Assembler program to use the current value of the ILC minus one
as the address of OP 1, LSL of this instruction. The current value of the ILC is
the MSL of this instruction. The MSL of this instruction minus one is the LSL of
the previous instruction.
FIELD B; OP 2, MSL:
The Label XT1 specifies the MSL of the locations assigned to that instruction by
the Assembler program.
FIELD C; OP 1, LSL:
Blank addressing will cause the Assembler program to use the LSL of the locations
assigned to the instruction stored at XTl.
4.3.3. TRANSFER CLEAR
Mnemonic:
LABEL
TC
Mode:
OPERATION
6
1
ASCENDING
Length:
7
OPERANO 1
I.
A.
*
FIELO A
±
Yes
OPERANO 2
INC.
18
12
IA:
I.
A.
*
FIELO B
22
±
28
±
FIELO C
INC.
32
INC.
38
I
I
1
I
I
TC
1 L
I
I
21M
1
I
2L
I
I
9
PAGE:
I
UNIVAC 1005
UP-4084
I"
4
ASSEMBLER·SO
SECTION.
I'I
10
PAGE.
Function:
Transfer ascending beginning from OP 1 - LSL specified by Field c:A.j' to OP 2 LSL specified by Field C, until OP 2 - MSL specified by Field B has been filled.
Clear the OP 1 locations to space codes during the process.
This instruction performs exactly the same as a TA (Transfer Ascending) instruction. The only difference is that as the characters are accessed from the
OP 1 locations, they are not returned to the OP 1 locations. The effect of this
instruction leaves the OP 1 characters cleared to space codes.
The rules for coding a TC instruction are the same as the rules for coding the TA
instruction (See Section 4.3.2.)
4.3.4. TRANSFER NUMERIC
Mnemonic:
LABEL
TN
OPERATION
I
I
!
I
I
ASCENDING
Length:
7
IA:' YES
OPERAND 1
I.
FIELD A
A.
.. 12
6
1
Mode:
1 LI
TINI I
I
±
OPERAND 2
INC.
18
I.
A•
..
FIELD B
±
22
FIELD C
INC.
28
2M
I
±
32
INC.
38
2 L
I
Function:
Transfer ascending beginning from the OP 1 - LSL specified by Field Aj to OP 2
- LSL specified by Field C, until OP 2 - MSL specified by Field B has been
filled. Delete the X and Y bit-positions of the data delivered to OP 2.
This instruction performs exactly like the TA (Transfer Ascending) instruction.
The only difference is that before the characters are stored in the OP 2 locations,
the zone bits (X and Y bit-positions) are stripped off (set to binary zero). The
contents of OP 1 remain unchanged.
The rules for coding a TN instruction are the same as the rules for coding the T A
instruction (See Section 4.3.2.)
4.3.5. TRANSFER CONSTANT
Mnemonic:
LABEL
OPERATION
6
1
I
I
I
TK
I
Mode:
ASCENDING
Length:
7
IA:
OPERAND 1
I.
FIELD A
A.
.. 12
TIKI I
KtKI
I
±
YES
OPERAND 2
INC.
18
I.
A•
.
FIELD B
22
21M
±
INC.
28
FIELD C
32
2 LI
±
INC.
38
I I
c
'-~'----"---"'----~------
UNIVAC 1005
UP-4084
SECTION.
Function:
Transfer ascending beginning from location 3 of the Instruction Register (IR); to
OP 2 - LSL specified by Field C, until OP 2 - MSL specified by Field B has been
filled. Transfer a maximum of 2 locations (KK) from the IR. If OP 2 is more than
two locations in length, space-fill the unentered high-order locations of OP 2.
When a TK instruction is brought to the IR for execution, the two alphanumeric
characters KK will occupy locations 2 and 3 of the IR. These two locations are
used similar to an OP 1 in an Ascending Transfer. However, the Operation code
(TK) will cause the transfer from OP 1 to cease after the second transfer. The
execution of the instruction will continue until OP 2, MSL has been filled. If
there are more than two locations in OP 2, the excess high-order locations of
OP 2 will be filled with space codes. If there are exactly two locations in OP 2,
the instruction will transfer locations 2 and 3 of the IR (the constant KK). If
there is only one location in OP 2, only position 3 of the IR will be transferred.
NOTE: The character J:( (lozenge) may not be used as the first character of a
constant in Field A of this instruction. Code in its bit configuration. (See
Section 4.3.5.3.)
Example 1:
Problem: Store the letters CR in the last (low-order) two locations of Print
Storage.
LABEL
OPERATION
6
1
OPERAND 1
I.
A.
*
FIELD A
±
OPERAND 2
INC.
18
12
I.
A.
*
FIELD B
22
±
INC.
28
FIELD C
32
±
INC.
38
I
I
I :
I
I
TIKI I
C RI
I
+$ P R
- 1.
FIELD A; KK:
The letters CR.
FIELD B; OP 2, MSL:
$PR is the Standard Label for the Print Storage area. The plus sign instructs
the Assembler program to use the LSL of Print Storage, and the minus one causes
the address of Print position 131 to become the MSL of this instruction.
FIELD C; OP 2, LSL:
Blank addressing will cause the Assembler program to use the LSL address of the
area specified by the Label in Field B. The use of the plus sign and the increment in Field B have no effect on this Assembler program procedure.
c
11
4
ASSEMBLER·80
PAGE.
UNIVAC 100S
UP-4084
SECTION.
PAGE.
Example 2:
OPERATION
1
I
:
OPERAND 1
I.
FIELD A
A.
• 12
6
~
TK
I
-
i
!
OPERAND 2
INC.
.~
FIELD B
I.
A•
•
18
!
22
F,O.X I I
~
INC.
28
FIELD C
I
INC.
!
32
38
• , I I
•
,
J
FIELD A: KK:
The ~ (space code) becomes location 2, and the minus sign (-) becomes location
3 of the IR. After they are transferred, the remainder of FOX is space filled.
FIELD B; OP 2, MSL:
The MSL of the area assigned to FOX becomes the MSL of this instruction.
FIELD C; OP 2, LSL:
Blank addressing causes the Assembler program to use the LSL of the area assigned to the Label in Field B (FOX) as the LSL of this instruction.
NOTE: See Example 5 for a description of negative constants.
Example 3:
Given: Several fields of the print line are to have a printed sign of plus (+) or
minus (-) based on a condition developed by the program.
Problem: Store the proper sign indication in each of the fields using the TK instruction with Indirect Addressing.
LABEL
OPERATION
1
!
S II GIN
I
I
I
I
I , : I
OPERAND 1
I.
A.
*
6
FIELD A
12
t
OPERAND 2
INC.
18
I.
A.
FIELD B
* 22
TK
* : S liG N - 1
+ i F3 D jl
T KI
*:
S I IG N - 1
+ F D 2
TIKI I I
*: ISII,G N - 11 I
+IF,D I3 I
±
INC.
FIELD C
32
28
I I
±
INC.
38
I I I I
I ,
!
Solution: The location immediately preceding the instruction labeled SIGN has
been established as the secondary address location for the Indirect Addressing
to be performed in the instruction SIGN.
----~-------.---------.-
C'
"
Problem: Store a minus sign (-) in the LSL of the 10 character area assigned to
FOX. Clear the high-order 9 locations of FOX to spaces.
LABEL
12
4
Rev. 1
ASSEMBLER·80
..- - - - . - - - - - - - - - - - - - - - - - - - - -
_ ."j
UNIVAC 1005
UP-4084
SECTION:
The processing in the program will previously determine the sign requirements of
the printed fields. This same portion of the program will then transfer the
appropriate character to location SIGN - 1, and execute a Jump instruction which
transfers control to SIGN.
The instruction in SIGN is then brought to the Instruction Register. Before it is
executed the instruction is examined by the hardware to see if it ca11s for Indirect
Addressing. In this case, it does.
The hardware then automatically uses the address in the A portion of the IR as
the LSL of a two location transfer from memory to the A portion of the IR. The
hardware then examines the Operation code and performs the TK instruction using
the "new" contents of the A portion of the IR as the two character constant KK.
Field B specifies that the LSL of FD 1 is to be used as the MSL of the instruction.
Blank addressing in Field C will cause the same address to be the LSL of the
instruction thus creating a one character OP 2. Each of the instructions will
then transfer the appropriate sign indication to the LSL of each of the print fields.
Example 4:
Problem: Clear Bank 2 to space codes.
c
LABEL
OPERATION
6
1
:
I
TIKI I I
OPERAND 1
I.
A.
*
FIELD A
12
16116 I I I
±
13
4
ASS EMB L ER-80
OPERAND 2
INC.
18
I.
A.
*
I
FIELD B
22
l:t 19 ,6,2,
±
INC.
28
FIELD C
±
32
,
I
INC.
38
l:t1922
FIELD A; KK:
The blank columns in the Field A will cause KK to become space codes.
FIELD B; OP 2, MSL:
l:t962 is the decimal address for the first location in Bank 2, which becomes the
MSL of OP 2.
FIELD C; OP 2, LSL:
l:t1922 is the decimal address of the last location in Bank 2, which becomes the
LSL of OP 2.
Solution: This instruction will first transfer the two space codes, and then spacefi11 the remainder of OP 2---the rest of Bank 2.
If the KK portion of a TK instruction is to contain a negative constant, the minus
sign (-) is used as a prefix to the two decimal digit constant. The Assembler
program wi11 place an X-bit over both of the numerals in KK. If the negative
constant is to be a value from -1 through -9, a zero must be coded between the
minus sign and the decimal numeral.
PAGE:
UNIVAC 100S
I
I
4
14
ASSEMBLER·SO
_ _ _ _ _ _ _......_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....._ _ _ _ _ _..L..S...
E...
C...
T_'O...N...' _ _ _....r....
P...
A.,;;G,;E;,.'_ _ _ _
UP-4084
I
If the KK portion of a TK instruction is to contain a positive constant, no sign
indication is required.
o
Example 5:
Problem: Store a -1 in the 2 location area assigned to COUNT.
LABEL
OPERATION
OPERAND 1
I.
6
1
FIELD A
A.
*
12
OPERAND 2
±
INC.
18
I.
A.
*
FIELD B
22
±
INC.
28
I
i
I
:
I
T,K, ,
1.,!il,1, ,
I
•
C,O U,N.T
FIELD C
32
• •
±
INC.
38
. , ..
, ,
FIELD A; KK:
The minus sign causes the Assembler program to place a binary 1 in the X bit
position of both the 0 and the 1 in the object language instruction. (See Section
4.4.)
FIELD B; OP 2, MSL:
The address of the MSL of the area assigned to COUNT is used as the MSL of
this instruction.
FIELD C; OP 2, LSL:
Blank addressing causes the Assembler program to use the address of the LSL
of the area assigned to COUNT as the LSL of this instruction.
"·
C
-f
NOTE: The minus sign (-) symbol cannot.be used as the first character of a
constant in the TK instruction. Code in its bit configuration. (See 4.5.3.)
4.3.5.1. Symbolic Address Substitution
The TK instruction can also be used to change the A, B, or C address of an
instruction. The UNIVAC 1005 Assembly System provides for source language
coding of Labels in the Field A portion of a TK instruction. These Labels are
converted to the two character machine language address assigned by the
Assembler program and stored as KK in the A portion of the object language
TK instruction.
The symbol colon (:) is used in column 12 as a prefix to the Label whose assigned address is to become KK.
C:
UNIVAC 1005
UP-4084
SECTION.
PAGE.
Example 6:
Problem: Change the A address portion of a T A instruction stored in DOG to
refer to CAT.
OPERATION
LABEL
I.
A.
1
FIELD A
~
i
1
tI
1
:!:
* 12
6
TIKI 1
OPERAND 2
OPERAND 1
:_1
I
INC.
18
+ lC1A~T
I.
A.
*
_1_
FIELD B
±
INC.
DIOIGl
~
FIELD C
±
32
28
22
+ 1
INC.
38
DOG
+ 2
FIELD A; KK:
The symbol colon C:) informs the Assembler program that a Labe I appears in
Field A of this TK instruction. The plus sign (+) prefix instructs the Assembler
to use the LSL address of the area assigned to CAT as KK in this instruction.
(The LSL is required due to the ascending mode of the TA instruction.)
FIELD B; OP 2, MSL:
The MSL of the TA instruction stored at DOG contains the Operation code.
Therefore, the MSL of the A portion of that instruction is stored at DOG + 1,
which becomes the MSL of the TK instruction.
FIELD C; OP 2, LSL:
DOG + 2 is the address of the LSL of the A portion of the T A instruction stored
at DOG. This address is used as the LSL of OP 2 of the TK instruction.
NOTE: If the symbol colon (:) is to be used as the constant K, it must be coded
in its bit configuration. (See Section 4.3.5.3. below.)
4.3.5.2. Row/Column and Decimal Addressing
Row /Column and Decimal Addressing can also be used to cause a machine
language address to be placed in the A portion of the TK ins truction.
Example 7:
Problem: Store the machine language of decimal location )::nOOO as the LSL
of a 7 character instruction stored in FOX.
OPERATION
LABEL
I.
A.
*
6
1
~
J
I
lI
I
TI
OPERAND 1
K.
I
FIELD A
12
~11010111l
±
OPERAND 2
INC.
18
FIELD B
I.
A.
*
22
FlO XI
±
INC.
28
+ 5
15
4
Rev. 1
ASSEMB LER·80
FIELD C
32
:!:
INC.
38
I
I
I
UNIVAC 1005
UP-4084
Rev. 1
ASSEMB LER-80
16
4
SECTION,
FIELD A; KK:
The Assembler program will use the two character code for address ):(1000 as
KK in this instruction.
PAGE,
c
FIELD B; OP 2, MSL:
FOX is the MSL address of the 7 character instruction. The LSL address
portion (the C portion) of FOX is therefore FOX + 5, which will be used as the
OP 2 MSL of this instruction.
FIELD C; OP 2, LSL:
Blank addressing will cause the Assembler program to use the LSL of the area
assigned to FOX as the OP 2, LSL of this instruction. This is the LSL of the
C portion of FOX.
Example 8:
1000 is the decimal address of R2/C8, Bank 2. The coding for Example 7 could
have read as follows and produce the same result.
LABEL
OPERATION
6
1
:
I
1
TIKI I I
OPERAND 2
OPERAND 1
I.
A.
*
FIELD A
INC.
18
12
$I~
±
12 I~ 18 B2
I.
A.
*
I
±
FIELD B
INC.
28
22
FlO XI
I
+ 5,
±
FIELD C
32
I
INC.
38
I
I
I
I
4.3.5.3. Binary Coded Constants
The basic level of machine code is a series of binary bits. In the UNIVAC
1005, 6 binary digits (bits) are stored in each memory location. The UNIVAC
1005 Assembly System allows the programmer to use binary indications, if
necessary, to code his program.
In order to reduce the number of source language columns required for binary
indication,the UNIVAC 1005 Assembly System provides for octal coding. An
octal code is made up of three adjacent binary digits. Thus,two octal digits
can be used to express the contents of one UNIVAC 1005 location. To determine
the octal equivalent of the 6-bit binary code, the following is suggested.
UNIVAC 1005 bit position
(4)
(2)
(1)
(4)
(2)
(1)
X
y
8
4
2
1
Octal Digit
11: 1
Octal Digit
11:2
Add the binary value of the bits in the (4), (2), and (1) bit positions (maximum
sum = 7) to create Octal Digit 11:2. Using the same values (4), (2), (1) add the
sum of the X, Y, and 8-bit positions (maximum 7) to create Octal Digit 1I:l.
Write as a two place number.
o
UNIVAC 1005
UP-4084
SECTION:
PAGE:
For example: the bit configuration of the letter A equals
x
o
Y
1
8
4
2
1
o
1
o
o
Position 1 = 0
2=0
4 = 4
sum
4 equals Octal Digit #2
Position 8 = 0
Y=2
X=O
sum
2 equals Octal Digit #1
Thus the octal form of the letter A is 24. In the same manner, any six bit configuration can be shown by uSing the two digit octal form.
The symbol for number (#) is used as a prefix to indicate to the Assembler
program that octal coding has been used. This symbol (#) must precede the
four octal digits.
Example 9:
Problem: Store two lozenge symbols (tf tf) in the least significant locations of
the area assigned to RAT. (Reminder, the lozenge symbol cannot be used for
KK in the TK instruction.) = 111 101
LABEL
OPERATION
OPERAND 1
I.
6
1
FIELD A
A.
*
12
±
OPERAND 2
INC.
FIELD B
I.
A.
*
18
±
INC.
28
22
FIELD C
±
INC.
38
32
I
I
I
~
I
TIKI I
#,7,5,7 15
17
4
ASSEMBLER-SO
I
+I
R AIT
- 11
I
I I , ,
I
FIELD A; KK:
The number symbol (#) indicates to the Assembler program that what follows is
octal coding. The Assembler program then forms the two characters KK.
FIELD B; OP 2, MSL:
+ RAT -1 is the second least significant location of RAT.
FIELD C; OP 2, LSL:
Blank addressing causes the Assembler program to use the LSL of the area assigned to RAT as the LSL of this instruction.
I
UNIVAC 1005
UP-4084
18
4
ASSEMBLER-SO
SECTION,
PAGE,
NOTE: Octal coding can also be used as a method for addressing in the UNIVAC
1005 Assembly System. See Section 6.1 for a complete description.
0
4.3.6. TRANSFER TO REGISTER X
Mnemonic:
LABEL
TX
OPERATION
6
1
:
I
Mode:
I
ASCENDING
5
Length:
IA:
OPERAND 1
I.
A.
*
FIELD A
±
TX
OPERAND 2
INC.
18
12
NO
I.
A.
*
1 L
±
FIELD B
22
INC.
28
11M~1
I
±
FIELD C
_J1
I
INC.
~8
32
1 J
~.J
Function:
(OP 2 in the TX command is rX). Transfer ascending beginning from OP 1 - LSL;
continuing until OP 1 - MSL has been transferred. Space fill any unentered high
order positions of rX. Maximum OP 1 operand length is 31 locations. (See Section
4.2 for further information.)
NOTE: 1m in Field "B" applies in this case to OP 1 and not to OP 2.
This instruction has an implied OP 2 of rX, which is indicated by the Operation
code. The purpose of this instruction is to provide for the handling of unequal
length operands. Complete specification of the length of OP 1 is made in Field
A and Field B (two addresses), and rX is OP 2.
The TX instruction is a 5
character instruction.
Example 1:
Problem: Transfer the 5 characters from card columns 1 thru 5 to the 8 character
field assigned to CAT. NOTE: This requires two instructions:
LABEL
OPERATION
6
1
:
I
I
:
I
I.
A.
*
FIELD A
12
±
INC.
$ R 1
I
TIAI
$ 3 12 13 1 B 2
Instruction 1
*
+ 4
TX
I.
A.
18
I
t
I
OPERAND 2
OPERAND 1
FIELD B
22
±
INC.
28
$IR 11
I
INC.
38
I I
C A TI I
±
FIELD C
32
I
I
I
I
I
TX
FIELD A; OP 1, LSL:
The Standard Label $Rl + 4 specifies that the address of the fifth position of
Read Input storage is to be the LSL of this instruction.
--
.--~------
------------~-
---~
--------
-------------~
c
-- - -
UNIVAC 1005
UP-4084
SECTION:
PAGE:
FIELD B; OP 1, MSL:
The Standard Label $R1 specifies that the address of the first position is to be
the MSL of this instruction.
FIELD C; Ignored
Instruction 1 transfers locations 1 through 5 of Read Input storage to the low
order 5 locations of rX (R32/C27, Bank 2 through R32/C31, Bank 2). The
remainder of rX (R32/C1, Bank 2 through R32/C26, Bank 2) is filled with space
codes.
Instruction 2
TA
FIELD A; OP 1, LSL:
$3231B2 specifies that the LSL of rX is to be used as the OP 1, LSL of this instruction.
FIELD B; OP 2', MSL:
The MSL address of the area assigned to CAT is to be used as the OP 2, MSL of
this instruction.
FIELD C; OP 2, LSL:
Blank addressing specifies that the LSL address of the area assigned to CAT is
to be used as the OP 2, LSL address of this instruction.
The ascending transfer in Instruction 2 calls for an 8 location transfer (the length
of OP 2, CAT). The low order 5 locations of CAT will contain the 5 characters
from the card which were transferred to the low order positions of rX by Instruction
1. The 3 high order positions of CAT will contain space codes from the un-entered
portion of rX.
4.3.7. TRANSLATE (Optional)
NOTE: The Translate instruction can only be used if the UNIVAC 1005 system
for which the program is being assembled has the hardware translate option.
Mnemonic:
LABEL
TR
Mode:
OPERATION
DESCENDING
Length:
7
OPERAND 1
I.
FIELD A
A.
• 12
6
1
±
IA:
YES
OPERAND 2
INC.
18
I.
A.
•
FIELD B
22
±
INC.
28
FIELD C
32
±
INC.
38
I
1
I
I
I
(-
1
TIRI
I
I
I
I
19
4
ASSEMBLER·SO
21M
2 L
I
I
UNIVAC 1005
UP-4084
ASSEMBLER·SO
4
Rev. 1
SECTION,
Function:
Translate each of the characters in the field defined as OP 2 (except the LSL)
according to the Translation Table. Return the translated character to OP 2.
20
PAGE.
o
The use of the Translate option on the UNIVAC 1005 requires that the translated
characters be returned to the same locations from which the characters to be
translated were obtained. Thus,2M and 2L not only define OP 2, they also define
OP 1. Furthermore, the Translate option also requires that OP 2 be one location
longer than OP 1 at the LSL end of OP 2. 2M specifies both OP 1 and OP 2 MSL.
2L specifies the OP 2 LSL, and the hardware automatically uses 2L-1 as the OP 1,
LSL.
The TR instruction replaces each character in the field to be translated with a
character selected from the translate table ($TR). The basis for selecting the
replacement character is the binary value of the character to be replaced (see
Figure 4-1). The binary value of any six-bit character ranges from zero (000000)
through 63 (111111). This binary value provides the character address of the
particular six-bit configuration within the translate table which is to replace the
character. In other words, a character with a binary value of (011111) is replaced
by whatever character is pre-stored in R28/C30 of the translate table; a character
with a binary value of (111111) is replaced by whatever character is pre-stored
in R28/C31 of the translate table; a character with a binary value of (000000) is
replaced with whatever character is pre-stored in R29/C1 of the translate table;
and so on. The contents of the translate table are not altered by the instruction.
The characters to be translated must be in the same bank of storage as the translate table.
The Translation Table must be stored in locations R28/C30, Bank 2 (MSL)
through R30/C31, Bank 2 (LSL) of a 2 bank UNIVAC 1005 system; or in R28/C30,
Bank 4 (MSL) through R30/C31, Bank 4 of a 4 bank UNIVAC 1005 system. More
than one Translation Table can be used in a program provided that the program
transfers the proper set of translation codes to the Translation Table locations
prior to each change in use.
o
Example 1:
Given: A field of 80 characters received in a communication code stored in an 80
location area assigned the Label INMSG. (INMSG must be in the Last Bank of
storage ).
A table of XS-3 codes stored in a 64 location area assigned the Label XS3.
o
UNIVAC 1005
UP-4084
ASSEMBLER-80
21
4
Rev. 1
SECTION:
ROW
ROW
28
28
COL
I
10
ORIG.
CHAR.
I
I
1 1 1 1 1
x:y
010
oI 0
oi0
oI0
oi0
oI1
8
0
0
0
0
0
0 10
0
oI
0
010
oI 1
0
1
oI
0
1
o I 1
o ! 0
0
1
oI 1
o I 1
0
1
0
1
0 0
1
1
3
1
4
1
1
1
0
5
1
1
1
1
0
0
6
1 I1
11 1
1
1
0
0
1
1
1
0
8
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
9
10
11
1
0
12
13
14
0
1
1
1
0
1
1
0
1
oI 1
1
0
0
1
1
1
1
0
0 ' 0
1
1
1
0
1
1
0
1
0
0
1
1
0
0
7
1 11
1 10
1 10
0
0
1
0
1 :1
I 10 0
1 I 0 0
0
16
1 i 0
1
1
17
1 I 1 0
1
18
19
1 i 0
1 I 1
1
1
1
1
1
20
21
1 1
1 I 1
i
1
1
0
1
0
22
i
1
I 0
0
23
1
1
1
1
1
1
1
24
1 I 1
1
0
0
1
0
0
0
1
25
26
1
1
27
1
1
0
1
1
1
0
0
0
0
0
0
0
0
ITI
1 I 0
1 : 1
1 I 0
28
29
30
1 I 0
1 I 1
31
1
I
0
0
1
x
Figure 4-1. Character Translate Table
4
5
1
0
8
0
9
10
1
0
11
12
13
14
15
16
17
18
19
1
1
20
0
22
0
1
23
1
0
24
0
0
0
1
25
26
21
1
0
0
0
1
1
27
0
1
1
0
1
1
0
0
28
;19
1 0
30
0
0
0
0
0
0
31
Y 8
4
2
1
1
I
421
30
6
7
0 0
0 0 1
0 1 0
1 0 1
0 1 0
1 0 1
0 1 1
1 1 1
15
1
1
0
I i 0
1 I 1
0
Y8
2
1
1
X
1
0
1
1
0
1
0
0
1
1
o I 0
oil
oI 1
I
0 0
0
0
1
1
0
0
1 I0
0
0 1 0
0
1 10
1 0
1
0
1
oI 1
1
1
1
1
0
Tt~cE
COL
li o
0
0
2
T~BLE
2
1
oI
o:
4
ORIG.
CHAR.
3
0
oI
8
I
1 I0
NEW
CHAR.
1
1
1
xi y
29
1
0
1
0
TA BLE
ROW
ROW
I
31
ORIGINAL CODE
IN 1005 STORAGE
I ADDRESS CODE
I OF TABLE COL
TABLE
1
1
1
1
2
I
1
0
0
1
I
I
11 I 1 I I I
0
0
0
Oil
Oil
o I 0
o 0
o I 1
l
4
COL
30
ORIGINAL CODE
IN 1005 STORAGE
I ADDRESS CODE
I OF TABLE COL
PAGE:
NEW
CHAR.
UNIVAC 1005
UP-4084
22
4
ASSEMBLER·SO
SECTION.
PAGE.
A table of communication codes stored in a 64 location area assigned the Label COMCD.
LABEL
OPERATION
OPERANO 1
I.
1
FIELD A
A.
*
6
±
OPERAND 2
INC.
18
12
I.
A.
*
FIELD B
±
INC.
28
22
FIELD C
32
±
INC.
38
I
I
I
I
J
TID
I
ITIRI
I
J
I
:
I
1$
XS3
I
Instruction 1
I I
I
TR
II,N,M,SG
,
I
+ I IN M S + 1
TD
FIELD A; OP 1, MSL:
The Label XS3 specifies that the MSL address of the XS-3 table is to be used as
OP 1, MSL.
FIELD B; OP 2, MSL:
The Standard Label $TR specifies that the MSL of the area required for the Translation Table is to be used as OP 2, MSL of this instruction.
FIELD C; OP 2, LSL:
Blank addressing specifies that the LSL of the area specified by $TR is to be
used as the LSL of this instruction.
Instruction 1 loads the Translation Table with the correct translation characters.
Instruction 2
o
TR
FIELD A; Ignored
FIELD B; OP 1 and OP 2 MSL:
The characters to be translated must be obtained from and replaced in the same
locations by the translated characters. The address of the MSL of the area assigned to INMSG will be used as OP 1 and OP 2 MSL of this instruction.
FIELD C; OP 2, LSL:
This must specify the location + 1 of the last character to be translated. The
character in this location is not disturbed. + INMS (four characters of the INMSG)
specifies the address of the LSL of the characters to be translated. + INMS + 1
specifies the correct OP 2, LSL for this instruction.
If the results of processing are to be translated from XS-3 to Communication code,
two similar instructions could be used. Instruction 1 would load the Translation
Table locations from the COMCD table, and Instruction 2 would cause the translation.
c
--~
------- .._.
__......_ . _ - - - - - - - - - -
UNIVAC 1005
UP-4084
PAGE:
SECTION:
(-LABEL
OPERATION
*
6
1
OPERAND 1
I.
A.
FIELD A
±
OPERAND 2
INC.
18
12
*
±
FIELD B
I.
A.
22
INC.
28
I
I
I
T,D,
I
I
TIRI
I
I
I
!
I
I
I
I
I
I
I
I N M,S
±
INC.
38
, ,
i$,T R,
C,O,MC,D
FIELD C
32
I
I
23
4
ASSEMB LER-80
IG
,
+oI,NMS + 1
I
1
4.4. ADDITION AND SUBTRACTION
Addition is accomplished in the UNIV AC 1005 in ascending mode using a one character adder. The LSL of OP 1 is placed in the adder. The LSL of OP 2 is then
added, and the sum digit is returned to the LSL of OP 2. The adder circuitry retains
the presence of a carry, if any. The next corresponding locations are added from
OP 1 and OP 2 (and the preceding carry, if any) and the sum digit is returned to
OP 2. This process continues until the sum digit has been returned to the MSL of
OP 2. Thus OP 2 defines the length of both Operands. Subtraction is accomplished
by adding the tens complement of OP 1 to OP 2.
There are two types of addition and subtraction in the UNIVAC 1005--Algebraic and
absolute.
For Algebraic Add and Subtract operations, the presence of a binary 1 in the X bit
position of the LSL of an Operand indicates a negative value. A negative result
will have a binary 1 in the X bit position of both the MSL and the LSL. A zero
result will have a binary 1 in the Y bit position of the MSL and will have the sign of
OP 2. Spaces in OP 1 and OP 2 are treated as zeroes, and zeroes will be placed
in result locations which do not contain 1 through 9.
For Absolute Add and Subtract, the signs of OP 1 and OP 2 are ignored. Absolute
Add can produce only a positive result. Absolute Subtract is performed by complemented addition and may produce a negative result. However the negative sign
indication is not stored. A zero result will have a binary 1 in the Y bit of the MSL.
Associated with the adder circuitry is a Sign Comparator. As a result of every
arithmetic operation, the Sign Comparator is set to one of three conditions--plus,
minus, or zero. The condition of the Sign Comparator can be tested, for sequential
control purposes. (See Section 4.7.1, JC instruction.)
In the event that a carry isproduce4 'as a result of adding the OP 1 and OP 2 MSL,
an Overflow indicator is set. Thl!S!: condition can also be tested. (See Section
4.7.1, JC instruction.)
The conditions of the Sign Comparator and the Overflow indicator are set following
every arithmetic operation, and must be tested, if required, before the next arithmetic
operation.
If the Operands for a required arithmetic operation are not of equal length, the
shorter of the two must be transferred to rX using the TX instruction.. rX can then
be used as OP 1.
UNIVAC 1005
UP-4084
SECTION:
PAGE:
o
4.4.1. ADD ALGEBRAIC
Mnemonic:
LABEL
AD
1
~
Mode:
OPERATION
*
!
III
I
AID,
I
ASCENDING
Length:
7
IA:
OPERAND 1
I.
A.
6
FIELD A
±
12
I
YES
OPERAND 2
INC.
18
11L,
I
24
4
ASSEMB LER-80
I.
A.
*
,
I
±
FIELD B
INC.
21M,
I
I
FIELD C
±
32
28
22
I
2j L
j
INC.
38
j
Function:
Condition the adder circuitry according to the sign bits of OP 1 and OP 2.
Ascending add the OP 1 - LSL specified by Field A to the OP 2 - LSL specified
by Field C; replacing OP 2 - LSL with the sum digit. Continue until a sum digit
has been placed in OP 2 - MSL specified by Field B. Set the Sign Comparator.
Set the Overflow indicator, if necessary. The arithmetic is performed according
to the rules for algebraic addition.
Example 1: EQUAL LENGTH OPERANDS
Problem: Add Quantity 1 from card columns 1 through 5 to Quantity 2 from card
columns 6 through 10. Store the result in the Quantity 2 locations.
LABEL
OPERATION
OPERAND 1
I.
A.
*
6
1
FIELD A
±
OPERAND 2
INC.
18
12
FIELD B
I.
A.
*
±
22
28
±
FIELD C
INC.
INC.
38
32
I
I
I
I
I
AID
I
):( 5 I
):( 1 .0
):(6
I
I
•
I
•
FIELD A; OP 1, LSL:
):( 5 is the decimal address for the LSL of Quantity 1.
FIELD B; OP 2, MSL:
):( 6 is the decimal address of the MSL of Quantity 2.
FIELD C; OP 2, LSL:
):( 10 is the decimal address of the LSL of Quantity 2.
Example 2: UNEQUAL LENGTH OPERANDS
Given: Input Amount is in card columns 61 through 65. TOTAL is the Label
assigned to an area of 10 locations.
Problem: Add Input Amount to TOTAL
~~~~~
----_._--
-~--------
-~~----
--------
o
,
-
UNIVAC 1005
UP-4084
LABEL
OPERATION
1
SECTION:
OPERAND 1
I.
A.
*
6
±
FIELD A
PAGE:
OPERAND 2
INC.
18
12
I.
A.
*
FIELD B
±
22
INC.
28
±
FIELD C
32
INC.
38
I
I
I : I
TIX I I
):(16 151
I
A DI I
+ .$IXIR I
I
I
Instruction 1
I
I I
):(16 11
•
TO TIA,L
•
•
•
•
•
•
I
TX
FIELD A; OP 1, LSL:
):(65 is the decimal address of the LSL of Input Amount in Read Input Storage.
FIELD B; OP 1, MSL:
):(61 is the decimal address of the MSL of Input Amount in Read Input Storage.
FIELD C; Ignored
This instruction transfers the 5 character Input Amount field to the low order 5
locations of rX. The high order locations of rX are space filled.
Instruction 2
AD
FIELD A; OP 1, LSL:
$XR is the Standard Label for the MSL of rX. +$XR specifies the LSL of rX.
FIELD B; OP 2, MSL:
The Label TOTAL specifies the MSL of the area assigned to TOTAL.
FIELD C; OP 2, LSL:
Blank addressing causes the Assembler program to use the LSL of the area assigned to TOTAL.
This instruction specifies a 10 character OP 1 and OP 2. The 10 character OP 1
will consist of the 5 low order locations of rX that were transferred from Input
Amount, and the next 5 locations of rX known to contain space codes.
4.4.2. SUBTRACT ALGEBRAIC
Mnemonic:
LABEL
I
:I
I
Mode:
OPERATION
6
1
SU
I~ ITT
ASCENDING
Length:
7
IA:
FIELD A
* 12
1.LI
±
INC.
18
I
YES
OPERAND 2
OPERAND 1
I.
A.
25
4
ASSEMBLER·SO
I.
A.
*
FIELD B
22
21M
±
INC.
28
•
±
FIELD C
32
•
2.L
INC.
38
I
I
I I
-- - - - - - - - - - " - - " - " -
-------""-------~-"
---------"--- -"--- ----"--
UNIVAC 100S
UP-4084
SECTION:
I,
26
4
ASSEMBLER-SO
PAGE:
Function:
This instruction performs exactly the same as ADD ALGEBRAIC (Section 4.4.1.).
c
NOTE: OP I is subtracted from OP 2 and the result is delivered to OP 2.
4.4.3. ABSOLUTE ADD (ADD MAGNITUDE)
Mnemonic:
LABEL
AM
Mode:
OPERATION
I.
1
, . I' ,
Length:
7
IA:
OPERAND 1
*
INC.
I.
1·
18
12
YES
OPERAND 2
±
FIELD A
A.
6
ASCENDING
FIELD B
±
22
INC.
FIELD C
±
32
28
INC.
38
I
AIMI I
I LI
2L
21M
I
I
I
Function:
Ignore the signs of OP I and OP 2. Ascending add the OP I - LSL specified by
Field A to the OP 2 - LSL specified by Field C, replacing OP 2 - LSL with the
sum digit. Continue until a sum digit has been placed in OP 2 - MSL specified
by Field B. Set the Sign Comparator. Set the Overflow indicator if necessary.
This instruction performs the same as Algebraic Add except the sign bits of OP I
and OP 2 are ignored during the process. The X bit of OP 2, LSL is not changed
by this ins truction.
c
4.4.4. ABSOLUTE SUBTRACT (SUBTRACT MAGNITUDE)
Mnemonic:
LABEL
SM
Mode:
OPERATION
I.
:
SM
I
*
•
Length:"" 7
OPERAND 1
FIELD A
A.
6
1
ASCENDING
I.L, •
YES
OPERAND 2
±
INC.
I
I.
FIELD B
1· 22
18
12
IA:
I
2.M , • I
±
INC.
28
±
FIELD C
32
I
I
21LI
INC.
38
I
I
I
•
Function:
This instruction performs exactly the same as ADD MAGNITUDE (Section 4.4.3.)
NOTE: OP I is subtracted from OP 2 and the result is delivered to OP 2. The
comparator is s_et to the results of the subtract (+, or -, or ~).
Although the signs are ignored for the processing if a negative result is produced,
it will be stored in true (not complement) form in OP 2.
For example: OP I = 7, OP 2 = 3, 3-7 = 4 which is the result stored in OP 2. The
X bit of the original OP 2, LSL remains unchanged.
----"--- - - - - - - - - -
--"-----------
"--
---------------""----- - - - -
c
UNIVAC 1005
UP-4084
C'-
SECTION:
PAGE:
4.4.5. ADD CONSTANT
Mnemonic:
LABEL
AK
OPERATION
!
I
*
7
Length:
IA:
FIELD A
±
INC.
18
12
YES
OPERAND 2
I.
A.
*
FIELD B
±
2 L,
INC.
38
32
,
I
±
FIELD C
INC.
28
22
2 M
DD
AK
I
ASCENDING
OPERAND 1
I.
A.
6
1
i
Mode:
,
I
I
I
Function:
Add algegraic ascending beginning with location 3 of the Instruction Register; to
the OP 2 - LSL specified by Field C, until OP 2 - MSL specified by Field B has
received a sum digit. Add a maximum of 2 locations (DD) from the IR. If OP 2
is more than two locations in length, spaces are considered as a prefix to DD.
Set the Sign Comparator. Set the Overflow indicator if necessary.
DD must always appear as a two digit constant. If the value of DD is less than
ten, place a '" in column 12. The maximum value of DD is 99.
Negative constants are specified by placing a minus sign (-) in column 12
followed by a two digit DD. The Assembler program will use this indication to
place a binary 1 in the X bit position of both digits. The X bit over the right hand
digit becomes the sign of the constant DD. The X bit over the left hand digit is
ignored in the AK instruction.
Example 1:
Problem: Add 1 to the value of a 4 location area assigned to COUNT.
LABEL
OPERATION
OPERAND 1
I.
A.
FIELD A
* 12
6
1
±
OPERAND 2
INC.
18
I.
A.
FIELD B
* 22
±
INC.
28
FIELD C
32
±
INC.
38
I
I
I
I
I
A,K
I
I
'" 1
27
4
ASSEMBLER-SO
CO U NT
I
FIELD A; DD:
01 becomes the two characters in locations 2 and 3 of the IR when this instruction
is executed.
FIELD B; OP 2, MSL:
The address of the MSL of the area assigned to COUNT is used as the OP 2, MSL
of this instruction.
FIELD C; OP 2, LSL:
Blank addressing causes the Assembler program to use the address of the LSL of
COUNT as the OP 2, LSL of this instruction.
UNIVAC 1005
28
______________~_________________A_S_S_E_M
__B_L_E__R_.8_0________________~~__________~~S=E~C~TI~O~N~:______~P~A~G~E~:______
~I
UP-4084
When the addition is performed, it operates the same as the Add Algebraic (AD)
instruction, except that if the OP 2 is more than two locations in length (as in
Example 1), space codes are added to the excess locations. The carty, if any,
also is added in the excess locations. The AK instruction terminates when a sum
digit has been delivered to the MSL of OP 2.
c
Example 2:
Problem: Subtract 1 from the value ofa 4 location area assigned to COUNT.
NOTE: Subtraction is performed by adding a negative constant.
LABEL
OPERATION
6
1
OPERAND 1
I.
A.
*
FIELD A
12
±
OPERAND 2
INC.
18
I.
A.
*
FIELD B
22
±
INC.
28
FIELD C
32
±
INC.
38
r
I
I
AK
I
- 01
COUNT
FIELD A; DD:
The minus sign (-) prefix to the constant 0 1 (DD) causes the Assembler program
to place a binary 1 in the X bit positions of locations 2 and 3 of this instruction.
The X bit of position 3 is the sign of the constant DD. The X bit of position 2
is ignored in the AK instruction.
FIELD B; OP 2, MSL:
The address of the MSL of the area assigned to COUNT is used as the OP 2, MSL
of this instruction.
FIELD C; OP 2, LSL:
Blank addressing causes the Assembler program to use the address of the LSL of
COUNT as the OP 2, LSL of this instruction.
Space codes will be subtracted from the two high order locations of COUNT, and
borrows will occur, if any.
4.5. COMPARE INSTRUCTIONS
Comparison in the UNIVAC 1005 may be considered to consist of two phases-performing the comparison, and testing the result of that comparison. The first
phase--performing the comparison is accomplished through use of one of the Compare
instructions. The purpose of a Compare instruction is to establish (set) a condition
in the Comparator based on the relationship of the Operands which are compared.
The condition of the Comparator is then tested by means of a Jump Test instruction.
The Comparator which is set and tested by the Compare and Jump Test instructions
should not be confused with the Sign Comparator which is set and tested by the
Arithmetic and Jump Condition instructions.
c
UNIVAC 1005
UP-4084
Rev. 1
ASSEMBLER·SO
The condition of the Comparator is set as a result (the only result) of the execution
of a Compare instruction. The contents of OP 1 and OP 2 remain unchanged by a
Compare instruction. The condition of the Comparator will not change until another
Compare instruction is executed. The Comparator may be tested as often as required.
The Compare instructions operate in ascending mode. In the event of a signed
comparison, this enables the circuitry to first examine the sign bits, which are
located in the LSL of the Operands. Except for sign considerations, the result
condition of the Comparator is based on the last difference, if any, encountered
during the comparison.
The Operands in a Compare instruction must be of equal length. For signed comparison of unequal length Operands, the shorter of the two should be transferred to
rX using the TX instruction (Section 4.3.6 ). In signed Compare instructions, space
codes are considered equal to zeros.
The maximum Operand length in a Compare instruction is 961 locations.
4.5.1. COMPARE NUMERIC
Mnemonic:
LABEL
CN
OPERATION
1
ASCENDING
7
Length:
OPERAND 1
I.
A.
*
6
SIGNED COMPARISON
Mode:
FIELD A
±
YES
OPERAND 2
INC.
18
12
IA:
I.
A.
*
FIELD B
22
±
INC.
28
±
FIELD C
INC.
38
32
I
I
I
I
I
C,N
I
1 L,
I
2 M
2 LI
I
1 i
I
Function:
Compare ascending the OP 1 - LSL (including sign) specified by Field A, to the
OP 2 - LSL (including sign) specified by Field C. Continue until the OP 2 - MSL
specified by Field B has been compared. Ignore the X and Y bit positions of OP 1
and OP 2 (except sign). Set the Comparator to one of three conditions.
OP 1
>
OP 2; OP 1
<
OP 2: OP 1 = OP 2.
When a signed comparison is performed, the relationship of OP 1 and OP 2 can be
established if the signs (X bit position of LSL) are not alike. If the signs are
alike, the values of OP 1 and OP 2 are then automatically compared to determine
the result.
If the signs are alike and both plus, the Operand with the larger absolute value
is the greater. If the signs are alike and 'both minus, the Operand with the larger
absolute value is the least. If the signs are not alike, the Operand with the plus
sign is the greater. Only if the signs are alike and the absolute values are the
same is the result equal.
c
29
4
SECTION:
PAGE:
UNIVAC 1005
UP-4084
30
4
ASSEMB LER·80
SECTION.
In Compare Numeric (CN), the zone bits (X and Y positionS) of OP 1 and OP 2
are ignored (except for the consideration of the sign bits). Space codes are
compared as equal to zeros.
PAGE.
c
The result of a CN instruction is set in the Comparator, and must be tested by a
JT instruction (Section 4.7.2) before the execution of any subsequent
Compare instruction.
Example 1:
Problem: Compare Total Deductions from card columns 5 through 10 to the Gross
Pay in a 6 character area assigned to GRPAY.
LABEL
OPERATION
OPERAND 1
I.
A.
.. 12
6
1
1
~
!
i_I
I
C 1N1
I
1
FIELD A
!
OPERAND 2
INC.
18
llll.r'~1
I
I.
A.
..
FIELD B
22
!
32
28
G1RIP1AIY
I
FIELD C
INC.
!
I I
1
INC.
38
~
1
J
FIELD Ai OP 1, LSL:
ll10 is the decimal address of the LSL of Total Deductions (column 10 of Read
Input Storage).
FIELD Bi OP 2, MSL:
The Label GRPA Y specifies the MSL address of the area assigned to GRPAY.
FIELD Ci OP 2, LSL:
Blank addressing causes the Assembler program to use the LSL of the area assigned to GRPA Y as the LSL of this instruction.
1) If Total Deductions (OP 1) is more than Gross Pay (OP 2), the Comparator is
set to Greater Than. OP 1
>
OP 2.
2) If Total Deductions (OP 1) is the same as Gross Pay (OP 2), the Comparator
is set to Equal. OP 1 = OP 2.
3) If Total Deductions (OP 1) is smaller than Gross Pay (OP 2), the Comparator
is set to Less Than. OP 1
OP 2.
<
4.5.2. COMPARE ABSOLUTE (MAGNITUDE) UNSIGNED COMPARISON
Mnemonic:
LABEL
CM
ASCENDING
Length:
7
I.
FIELD A
A.
.. 12
!
IA:
YES
OPERAND 2
OPERAND 1
OPERATION
6
1
Mode:
INC.
18
I.
..
A.
FIELD B
INC.
±
FIELD C
32
28
22
±
INC.
38
I
I I : I
I
CIM l
I
j
1 L
21M
I
I I
21L
I
c
UNIVAC 1005
UP-4084
4
ASSEMB LER-80
SECTION.
Function:
Compare ascending the numeric bits (8, 4, 2, 1) of OP 1 - LSL (excluding sign)
specified by Field A, to the OP 2 - LSL specified by Field C. Continue until
the OP 2 - MSL specified by Field B has been compared. Ignore the X and Y bit
positions of OP 1 and OP 2 including the sign bits. Set the Comparator to one of
three conditions:
>
OP 1
OP 2; OP 1
<
OP 2; OP 1 = OP 2.
The comparison is made on the absolute magnitude of the numeric (8, 4, 2, 1)
values of OP 1 and OP2. The X bit positions of OP 1, LSL and OP 2, LSL (sign
bits) are also excluded from consideration. Thus a plus 3 would compare equal
to a minus 3. Space codes are compared as equal to zeroes.
The result of a CM instruction is set in the Comparator, and must be tested by a
JT instruction (Section 4.7.2) before the execution of any subsequent
Compare instruction.
Example 1:
Problem: Compare Actual Tolerance from the area assigned to ACTOL (5 locations)
to the Allowed Tolerance in the area assigned to AL TOL (5 locations).
LABEL
OPERATION
I.
A.
*
6
1
OPERAND 2
OPERAND 1
FIELD A
12
±
INC.
I.
A.
*
18
FIELD B
22
±
INC.
28
FIELD C
32
±
INC.
38
I
I
I
:
I
I
C,M ,
I
I
+,AIC,TI O
1
A1L1TI01L
-.l-.l
-.l
FIELD A; OP 1, LSL:
The plus sign (+) prefix to the Label ACTO causes the Assembler to use the
address of the LSL of the area assigned to ACTOL.
FIELD B; OP 2, MSL:
The address of the MSL of AL TOL is used as the MSL of OP 2.
FIELD C; OP 2, LSL:
Blank addressing causes the Assembler program to use the address of the LSL
of ALTOL as LSL of OP 2.
31
PAGE.
I
_ _U
....._f>-,-4-0-8-4_-.._ _- -_____
A_SU_SN_~_~_~_~_1_:_~_~8_0_ _ _ _ _ _ _ _
-L._ _ _ _ _ _
. .L:.S.:.;EC: .T.:.:j.: :.O: : ;N:~4_~' L.!P~A~G:!E:.:.:_3_2_ _~J
__
i
Tolerances are usually ± n. If AL TOL contains n, the Actual Tolerance (ACTOL)
could have been calculated to a plus or minus value. The CM instruction will
ignore the signs, and compare to determine if the absolute value of the Actual
Tolerance is greater than the Allowed Tolerance.
o
1) If the Actual Tolerance (OP 1) is more than the Allowed Tolerance (OP 2), the
Comparator is set to Greater Than. OP 1
OP 2.
>
2) If the Actual Toleran<;:e (OP 1) is the same as the Allowed Tolerance (OP 2),
the Comparator is set to Equal. OP 1 = OP 2.
3) If the Actual Tolerance (OP 1) is smaller than the Allowed Tolerance (OP 2),
the Comparator is set to Less Than. OP 1
OP 2.
<
If the Allowed Tolerance is 5, an Actual Tolerance of ± 4 would compare Less
Than.
.
4.5.3. COMPARE ALPHANUMERIC
Mnemonic:
LABEL
CA
Mode:
OPERATION
6
ASCENDING,
Length:
7
A.
*
FIELD A
12
±
IA:
YES
OPERAND 2
OPERAND 1
I.
1
UNSIGNED COMPARISON
INC.
18
I.
A.
*
FIELD B
22
±
INC.
28
FIELD C
32
±
INC.
38
.I
I
I
I
I
CtA
1 L
2M
2 L
I
I
Function:
Compare ascending the bit pattern of OP 1 - LSL specified by Field A, to the bit
pattern of OP 2 - LSL specified by Field C. Continue until the bit pattern of
OP 2 - MSL specified by Field B has been compared. Exclude sign considerations,
but include sign bit positions. Set the Comparator to one of two conditions.
OP 1 = OP 2; OP 1 f. (unequal to) OP 2.
The purpose of the CA instruction is to determine if all bits in OP 1 are exactly
the same as all bits in OP 2. There are only two results: all the bits of OP 1
are exactly the same (equal condition), or they are not the same (unequal condition). Spaces do not equal zeroes.
The comparison is performed on an ascending b.asis using the X Y 8 4 2 1 bits of
each corresponding location of OP 1 and O.P 2 beginning with the LSL. The
determination of the condition which exists between the two Operands is made as
soon as any difference is detected between characters in corresponding locations.
If all locations have been compared and no difference is detected, an equal condition exists.
c
.-.",-,,~,,----~----,-----
I
.-c.....r~-~-.~--.-.---~--
UP-4084
-_._____._. ___________
'.
33
PAGE:
Example 1:
Given: Employee Number (5 locations) and Employee Name, last name first (24
locations) from a Payroll Master Card have been stored in two adjacent areas
assigned to MNUM and MNAME.
MNUM
I
MNAME
'
...'
I.,
Detail cards containing the Employee Number in columns 1 through 5 and the first
four letters of the last name of the employee are in columns 6 through 9.
Problem: Compare Employee Number and Name from the detail card to MNUM and
the first four locations of MN AME.
LABEL
:,
OPERAND 1
OPERATION
6
1
CIA, ,
I.
A.
*
FIELD A
INC.
, ,
I.
A.
*
18
12
):(,9,
±
OPERAND 2
,
FIELD B
22
M,N U,M
±
INC.
28
FIELD C
32
,
±
INC.
38
M,N,A,M,E + 3 I
I
I
.'
FIELD A; OP 1, LSL:
c
__ ._
4
ASSEMBLER-SO
SECTION:
, I
~~
UNIVAC 1005
):( 9 is the decimal address of the Read Input Storage location which contains the
information from card column 9.
FIELD B; OP 2, MSL:
The Label MNUM causes the address of the MSL of the area assigned to MNUM
to be used as the MSL of this instruction.
FIELD C; OP 2, LSL:
MNAME + 3 is the address of the location of MNAME that contains the fourth letter
of last name stored from the master card. This address becomes the LSL of the
CA instruction.
Solution: The 5 locations of MNUM and the first 4 (high order) locations of MNAME
become a 9 location OP 2, and are compared to the information from card columns
1 through 9 in Read Input Storage. The assignment of the two Labelled Storage
areas· (MNUM and MNAME) to adjacent memory locations is accomplished by proper
use of Declarative instructions.
The result of the CA instruction is set in the Comparator and can be tested in the
next or some subsequent instruction (provided no intervening Compare instruction
is executed).
UNIVAC 1005
'
_ ___U_P_-4_0_8_4__~_____________A_S_S_E_M_B_L_E_R_-8_0______________~________~~~~4
____~~~3_4
__~1\
SECTION:
PAGE:.
4.5.4. COMPARE CONSTANT
Mnemonic:
LABEL
CK
OPERATION
1
J
I
CIK.
*
1
ASCENDING
Length:
7
IA:
OPERAND 1
I.
A.
6
1
!
_I ~
Mode:
FIELD A
±
INC.
18
12
YES
OPERAND 2
K.K • • •
•
o
UNSIGNED COMPARISON
I.
A.
*
FIELD B
INC.
28
21M..! ,
l
±
22
I
±
FIELD C
32
_1
I
INC.
38
2,LI
.L
1
Function:
Compare alphanumeric ascending the bit pattern of KK specified in Field A;
beginning with the bit pattern stored in the location 2L specified by Field C;
continuing until the bit pattern stored in the location 2M has been compared.
Compare all bits. If 2M and 2L specify the same address, a one character comparison is made. If 2M and 2L specify more than a 2 location OP 2, space codes
(binary zeroes) are compared to the excess positions of OP 2. Set the Comparator'
to one of two conditions: KK = OP 2; KK lOP 2.
When a CK instruction is brought'to the IR for execution, the two alphanumeric
characters (KK) will occupy locations 2 and 3 of the IR. These two locations are
used similar to an OP 1 in a Compare Alphanumeric instruction (Section 4.5.3.)
However, the Operation code CK will cause the comparison to continue after the
second character comparison has been made. Space codes are compared to any
additional locations of OP 2.
The CK instruction is an unsigned bit-for-bit compare instruction. Spaces do not
equal zeroes, and sign considerations are ignored. OP 2 will usually be a one or
a two character operand.
The instruction is to be used
storage location. (The Jump
used to test for the presence
coding (Section 4.3.5.3.) may
a character comparison.
to test for the presence of whole characters in
Compare OK) instruction (Section 4.7.5) can be
of specific bits in a storage location.) Binary
be used, but should not be necessary, since this is
Example 1:
Problem: Test the information in card column
LABEL
OPERATION
6
1
I
:•
I
CK
80
for a
OPERAND 1
I.
A.
*
FIELD A
12
1~3
±
3.
OPERAND 2
INC.
18 .
I.
A.
*
FIELD B
22
~ 8,0
±
INC.
28
FIELD C
32
±
INC.
38
J:t 8,0
c
UNIVAC 1005
UP-4084
35
4
ASSEMBLER-SO
SECTION:
PAGE:
FIELD A; KK:
The )S 3 in the KK positions of Field A will be in locations 2 and 3 of the IR
when this instruction is executed.
FIELD B; OP 2, MSL:
J:l 80 is the decimal address of the location in Read Input Storage which contains
the information from card column 80.
FIELD C; OP 2, LSL:
J:l 80 is the decimal address of the location in Read Input Storage which contains
the information from card column 80.
Solution: Since the OP 2 - MSL and OP 2 - LSL specify the same location, a one
character comparison is made, using the 3 from location 3 of the IR (the right-hand
K). The space code ()S) is required to position the 3 so that it is in the right-hand
K position (column 13 of the form). If card column 80 contained only a 3 punch,
the Comparator is set to equal. If card column 80 contained any other punches
(or none at all), the Comparator is set to unequal. The Comparator is tested by
use of the Jump Test OT) instruction.
Example 2:
Given: A two location counter is being arithmetically reduced by 1. The counter
is stored in the two locations assigned to COUNT.
Problem: Test the value of COUNT to see if it is equal to zero.
LABEL
OPERATION
6
1
I
:
I
rlK
OPERAND 1
I.
A.
*
FIELD A
12
? 0111
!
OPERAND 2
INC.
18
I.
A.
*
FIELD B
22
INC.
!
28
FIELD C
32
±
INC.
38
C OUN T
I
FIELD A; KK:
The characters? 0 in the KK positions of Field A become locations 2 and 3 of
the IR when this instruction is executed.
FIELD B; OP 2, MSL:
The address of the MSL of the area assigned to COUNT is used as the OP 2, MSL
of this instruction.
FIELD C; OP 2, LSL:
Blank addressing causes the Assembler program to use the address of the LSL of
the area assigned to COUNT as the OP 2, LSL of this instruction.
j
f
UNIVAC 1005
UP-4084
Rev. 1
ASSEMBLER-SO
4
SECTION.
Solution: The contents of COUNT are being arithmetically reduced by 1. When
the value of COUNT is reduced to zero, the operation of the Arithmetic unit of
the UNIVAC 1005 will cause a Y bit to be placed over the MSL of the result. The
internal code for the question mark (?) is the same as an XS-3 zero with a Y bit.
The CK instruction performs a bit-for-bit comparison. When COUNT is reduced
to zero, this CK instruction will set the Comparator to equal.
36
PAGE.
o
NOTE: Addresses can also be specified in the KK portion of a CK instruction by
using the same notation described in Sections 4.3.5.1.; 4.3.5.2.; and 4.3.5.3.
4.6. CONDITION INDICATORS
The UNIVAC 1005 provides for two program controlled sensing switches, Sense 1tl
and Sense 11:2. By using the Set Condition (SC) instruction, the programmer can turn
these switches ON (Set to 1) or OFF (reset to 0) during the execution of a program.
The condition of the Sense switches can be used to control the sequence of the
execution of instructions during the program through use of the Jump Condition
(JC) instruction. The Jump Condition instruction is used to test for the ON condition of the switches. If the Sense switch being tested is ON (Set), the transfer
of control will occur. If the Sense switch being tested is OFF (reset), the program
proceeds with the next sequential instruction (NI).
There are other uses for the Set Condition and Jump Condition instruction. A
complete description of both instructions is given below.
o
4.6.1. SET CONDITION
Mnemonic:
LABEL
:
Mode:
OPERATION
6
1
SC
S C
SPECIAL
Length:
5
IA:
OPERAND 1
I.
A.
*
FIELD A
12
±
NO
OPERAND 2
INC.
18
I.
A.
*
FIELD B
22
±
INC.
28
FIELD C
32
±
INC.
38
CC
I
Function:
Set or reset the Conditions or Controls which correspond to each bit position of
CC which contains a binary 1 as specified in Field A.
Each of the bit positions of CC correspond to a Condition Indicator or a Control
setting. The presence of a binary 1 in a bit position of CC will cause the Condition or Control to be set or reset by the SC instruction. The presence of a binary
zero in a bit position will not change the status of a Condition or Control.
Although coded in Field A (to simplify source coding), the bit patterns of CC must
occupy locations 4 and 5 (the B portion) of the object instruction. Locations 2
and 3 of the object instruction are ignored by the UNIVAC 1005, and should be
blank. Locations 4 and 5 constitute bit positions 19 through 24 and 25 through
30 of the instruction.
o
UNIVAC 1005
UP-4084
Rev. 1
ASSEMBLER·SO
4
SEC TION:
The Conditions and Controls which correspond to the bit position of CC are as
follows:
BIT POSITION
19 (X) .
20 (Y)
21
22
23
24
(8)
(4)
(2)
(1)
25 (X)
26 (Y)
27
28
29
30
(8)
(4)
(2)
(1)
CONDITION/CONTROL
SET ODD PARITY (See Section 4.13.) (Magnetic Tape)
SET EVEN PARITY (See Section 4.13.) (Magnetic Tape)
SET SENSE 2 (ON)
SET SENSE 1 (ON)
RESET SENSE 2 (OFF)
RESET SENSE 1 (OFF)
RESET PPT for channel 8 punching
SET PPT for channel 8 punching
SET SERVO 2 (See Section 4.13.)
SET SERVO 1 (See Section 4.13.)
SET CONSOLE INDICATOR 2 (ON) and HALT
SET CONSOLE INDICATOR 1 (ON) and HALT
The Condition Indicators and Controls can be set (or reset) individually or in
multiples as the programmer requires.
c-
NOTE: Caution should be used when coding multiple bits in CC, in order to
prevent illogical bit patterns which require the UNIV AC 1005 to establish opposing
conditions. The results of such a conflict are unpredictable.
Binary coding is normally used to specify a multiple bit pattern for CC (See
Section 4.3.5.3.), in which case Field A must always contain a number sign (11)
in column 12 followed by four octal digits for binary coding.
The UNIVAC 1005 Assembly System provides the following mnemonic Switch
Names if only a single Condition or control is to be set (or reset) by the SC instruction. A number sign (11) must appear in column 12 followed by the two-place
mnemonic Switch Name in columns 13 and 14.
SWITCH NAME
11 SO (Alpha)
lISE
11+2
11
+1
2
- 1
11-
11
S2
Sl
lIH2
lIH1
11 H3
11
11
BIT POSITION
19
20
21
22
23
24
27
28
29
30
29,30
CONDITION /CONTROL
SET ODD PARITY
SET EVEN PARITY
SET SENSE 2 (ON)
SET SENSE 1 (ON)
RESET SENSE 2 (OFF)
RESET SENSE 1 (OFF)
SET SERVO 2
SET SERVO 1
CONSOLE INDICATOR 2 and HALT
CONSOLE INDICATOR 1 and HALT
CONSOLE INDICATORS 1 & 2 & HALT
37
PAGE:
UNIVAC 100S
UP-4084
38
4
ASSEMB LER-80
SECTION:
PAGE:
It should be noted that the Switch Names for the Sense switches have a plus sign
(+) for set (ON) and a minus sign (-) for reset (OFF); the Controls for magnetic
tape operations have a prefix of the letter S; and the Halt and Console Indicators
have a prefix of the letter H.
c
Example 1:
Problem: Set Sense 1 (ON)
LABEL
OPERATION
I.
A.
*
6
1
OPERAND 1
FIELD A
±
OPERANO 2
INC.
18
12
I.
A.
*
FIELD B
±
FIELD C
INC.
28
22
±
32
INC.
38
I
I
•
I
•
I
S.C.
#
I
+.1
•
I
I
I
I
FIELD A; CC:
The Switch Name # + 1 causes the Assembler program to create a binary 1 in bit
position 22, and the binary zeros in all other bit positions of CC.
NOTE: The octal coded constant #
1341313 would produce the same CC.
FIELD Band C:
o
Blanks.
Example 2:
Problem: Reset Sense 2 (OFF) and Halt the UNIVAC 1005 with Console Indicator
#1 ON.
LABEL
OPERATION
6
1
•
:•
SIC
OPERAND 1
I.
A.
*
FIELD A
INC.
18
12
#
±
OPERAND 2
III 2 1 1/1.1
I.
A.
*
FIELD B
22
±
INC.
28
FIELD C
32
I
±
INC.
38
I
I
FIELD A; CC:
The bit pattern of the octal constant #0201 will cause a binary 1 in bit positions
23 and 30, and binary zeros in all other bit positions of CC.
NOTE: Switch Names cannot be used since multiple bits are required.
UNIVAC 1005
UP-4084
Rev. 1
ASSEMBLER-SO
PAGE:
4.6.2. STOP (HALT)
Mnemonic:
lABEL
STOP
Mode:
OPERATION
IA:
5
OPERAND 1
I.
A.
*
6
1
Length:
SPECIAL
FIELD A
±
NO
OPERAND 2
INC.
18
12
I.
A.
*
±
FIELD B
22
INC.
28
±
FIELD C
32
INC.
38
I
I I
I
I
[(ISlelel
SITIOIP
B e I
10
w I) I
J
I
I
1
I
I
i
...i
Function:
The STOP command is a variation of the SC instruction (Section 4.6.1.) provided
in the UNIVAC 1005 Assembly System to enable the programmer to easily specify
and rapidly recognize those instructions which STOP (HALT) the operation of the
UNIVAC 1005 during the execution of the object program. Permissible specifications in Field A are Switch Names ttHl or ttH2 or ItH3. One of these switch
names must be coded in Field A.
4.7. SEQUENCE CONTROL INSTRUCTIONS
Instructions in the UNIVAC 1005 are stored, accessed, and executed in serial
sequence. This sequential operation is used as long as the program does not
require branching.
The accessing of instructions is under the control of the Instruction Control
Counters. There are two single position counters; one for Rqw R32/C8/B1, and
one for Column R32/C9/B1. The Column Counter is automatically incremented by
five or seven as each instruction is transferred to the Instruction Register. The
increment is determined by instruction type. The Row Counter is advanced by one
each time the Column Counter advances beyond thirty-one and returns to one. Bank
specification is also modified when the Row Counter passes 31. The Instruction
Control Counters provide the Control Unit with the address of the next instruction
(NI).
JUMP instructions are used in the UNIVAC 1005 to vary the normal instruction
sequence. The JUMP instructions change the contents of the Instruction Control
Counters if conditions specified by the JUMP instruction are present. If not, the
contents of the Instruction Control Counters remain unchanged, and the normal
execution sequence (NI) is followed.
The UNIVAC 1005 instruction repertoire contains seven Jump instructions for
sequence variation.
4.7.1. JUMP CONDITION
Mnemonic:
lABEL
JC
OPERATION
I
:
I
J ICI
*
I
SPECIAL
Length:
5
IA:
OPERAND 1
I.
A.
6
1
Mode:
FIELD A
12
CC
±
NO
OPERAND 2
INC.
18
I.
A.
*
_1
FIELD B
22
J,A
±
INC.
28
I
39
4
SECTION:
FIELD C
32
±
INC.
38
...i i i
J ...i
UNIV.AC 1005
UP-4084
40
4
ASSEMB LER·80
SECTION:
Function:
If any of the conditions are met which correspond to binary 1 bits of CC specified
by Field A; transfer control (JUMP) to the Jump Address (JA) specified by Field
B. Otherwise, execute the next sequential instruction (NI).
PAGE:
o
NOTE: In some cases, the indicators specified by 1 bits in CC are reset by this
ins truction.
The J A specified by Field B must be the address of the MSL of the instruction
to which control is to be transferred if the Jump occurs. Since instruction addresses
are assigned by the Assembler program, Field B will normally contain a programmer's Label. The current value of the ILC maintained by the Assembler
program during assembly processing can also be used by specifying the dollar
sign symbol ($) with Increment. The J A occupies locations 4 and 5 of the instruction.
The bit patterns of CC occupy locations 2 and 3 of the JC instruction. Locations
2 and 3 constitute bit positions 7 through 12 and l3 through 18 of the instruction.
If a single binary 1 bit appears in any of the bit positions of CC and the corresponding condition (indicator) is set (ON), the Jump will occur. If multiple 1 bits
are present in CC and anyone of the corresponding conditions (indicators) is
set (ON), the Jump will occur. Otherwise, the next sequential instruction is
executed.
The conditions and indicators which correspond to the bit positions of CC are
as follows:
BIT POSITION
7 (X)
CONDITION/INDICATOR TESTED
Form Overflow. Form Overflow is set when the Form Overflow position of the Forms Control Tape is sensed by the
carriage.
Form Overflow is reset when tested.
8 (Y)
Arithmetic Overflow. Arithmetic Overflow is set when the
result of an Arithmetic ADD or SUBTRACT instruction
exceeds the capacity of OP 2.
Arithmetic Overflow is not reset when tested.
NOTE: Form Overflow and Arithmetic Overflow cannot be
tested in the same JC instruction. (See below.)
7 and 8(X, Y)
End of Tape. End of Tape is set when that condition is
detected by a Uniservo. The presence of binary l's in bits
7 and 8 of CC constitute a specific test for End of Tape.
If both bits are present, Form Overflow and Arithmetic Overflow are not tested or changed.
c
UNIVAC laOS
UP-4084
ASSEMBLER-SO
SECTION:
End of Tape is reset when tested.
c~
NOTE: EOT is a separate indicator that is set by the
Uniservo. It can be tested only through the combination
bits 7 and 8 of character 2. The indicator is reset when
tested.
9 (8)
Sense 2 Set. The Sense 2 Indicator has been set by the SC
ins truction.
Sense 2 is not reset when tested.
10 (4)
Sense 1 Set. The Sense 1 Indicator has been set by the SC
instruction.
Sense 1 is not reset when tested.
11 (2)
Alternate Hold 2 Set. Alternate Hold 2 Condition Indicator
is set (ON) when the Alternate Hold Switch 11 2 console
light is turned ON by depression of the switch.
Alternate Hold 2 is not reset when tested.
12 (1)
A Iternate Hold 1 Set. Alternate Hold 1 Condition Indicator
is set (ON) when the Alternate Hold Switch 11 1 console
light is turned ON by depression of the switch.
Alternate Hold 1 is not reset when tested.
13 (X)
Interrupt. Interrupt is set when the UNIVAC 1005 receives
an Interrupt Signal from a peripheral unit.
Interrupt is not reset when tested.
14 (Y)
Unit A lert. Unit Alert is set when a peripheral unit is in
an abnormal condition.
Unit Afert is not reset when tested.
15 (8)
Parity Error. Parity Error is set when a parity error is
detected. This may be set as the result of a magnetic
tape parity error, mod error (OL Tl), invalid card code, or
paper tape read (even parity detected).
Parity Error is reset when tested.
16 (4)
Sign Comparator Plus. The Sign Comparator is set to Plus
when the result of an Arithmetic instruction is positive, and
not zero.
The Sign Comparator is not reset when tested.
41
4
Rev. 1
PAGE:
UNIVAC 100S
UP-4084
4
ASSEMBLER-SO
SECTION,
17 (2)
Sign Comparator Zero. The Sign Comparator is set to Zero
when the result of an Arithmetic instruction is zero.
42
PAGE,
o
The Sign Comparator is not reset when tested.
18 (1)
Sign Comparator Minus. The Sign Comparator is set to
Minus when the result of an Arithmetic instruction is
negative and not zero.
The Sign Comparator is not reset when tested.
The conditions may be tested individually or in multiples (except Form Overflow
and Arithmetic Overflow) as the programmer requires. Binary coding is normally
used to specify a multiple bit pattern for CC (See Section 4.3.5.3.), in which case
Field A must always contain a number sign (#) in column 12 followed by four octal
digits for binary coding.
The UNIVAC 1005 Assembly System provides the following mnemonic Condition
Names if only a single condition is to be tested by the jC instruction. A number
sign (#) must appear in column 12 followed by the two-place mnemonic Condition
N arne in columns 13 and 14.
CONDITION NAME
BIT POSITION
CONDITION
#FF
7
Form Overflow
#AF
8
Arithmetic Overflow
#+2
9
Sense 2 Set
#+1
10
Sense 1 Set
#-2
11
Alternate Hold 2 (ON)
#-1
12
Alternate Hold 1 (ON)
#IN
13
Interrupt
#UA
14
Unit Alert
#PE
15
Parity Error
#AP
16
Sign Comparator Plus
#AZ
17
Sign Comparator Zero
#AM
18
Sign Comparator Minus
#ET
7x8
End of Tape
c
When the jC command is executed by the UNIVAC 1005 at object time, and the
jump is to occur, locations 4 and 5 of the IR are transferred to the Instruction
Control Counter. Locations 4 and 5 of the IR contain the jump address specified
in the jC command. These two characters become the address used by the ICC
to control the access of the next instruction.
o
I;
I
UNIVAC 1005
UP-4084
c
SECTION:
Example 1:
Problem: Transfer control to the instruction labelled FOF if Form Overflow has
occurred.
LABEL
OPERATION
OPERAND 1
I.
A.
*
6
1
:
J C
I
FIELD A
±
It
OPERAND 2
INC.
18
12
I.
A.
*
F F
FIELD B
±
INC.
28
22
±
FIELD C
32
INC.
38
FOF
FIELD A; CC:
FF is the Condition Name for Form Overflow and causes the Assembler program
to place a binary 1 in position 7, and binary zeroes in all other positions of CC.
It 4000 would produce the same pattern for CC.
It
FIELD B; JA:
The programmer's label FOF causes the Assembler program to use the address of
the MSL of that instruction as the J A of this instruction. If Form Overflow has
been sensed, the jump will occur.
Example 2:
Problem: Do not jump to the instruction labelled ERROR if the last previously
executed Arithmetic instruction produced a positive result without Arithmetic
Overflow.
OPERATION
LABEL
..
6
1
1
:
I
J ICI
I
OPERAND 2
OPERAND 1
I.
A.
FIELD A
12
It 12101013
±
INC.
I.
A.
•
18
I
FIELD B
22
ERR 0, R
±
INC.
28
±
FIELD C
INC.
38
32
I
I
I
I
I
FIELD A; CC:
The octal coding will produce binary 1 's to test Arithmetic Overflow, Sign Comparator Zero, and Sign Comparator Minus.
FIELD B; JA:
The address of the MSL of the instruction labelled ERROR will be used as the
jump address in this instruction.
c
43
4
ASSEMBLER-SO
Solution: The jump will occur if any of the three conditions tested does exist.
The jump will not occur if none of the three conditions tested exists.
PAGE:
UNIVAC,l005
UP-4084
4
ASSEMBLER-SO
SECTION:
o
4.7.2. JUMP TEST
Mnemonic:
LABEL
JT
Mode:
OPERATION
Length:
SPECIAL
5
IA:
OPERAND 1
I.
A.
*
6
1
FIELD A
±
OPERAND 2
INC.
18
12
NO
I.
A.
*
±
FIELD B
INC.
I
I
I
J ,T,
I
I
J ,A 1 1 ,
-
I
I
J,A 2,
I
±
FIELD C
32
28
22
I
INC.
38
I
I
44
PAGE:
I
,
,
I
I
<
Function:
Test the
If equal,
unequal,
by Field
(NI).
condition established by the last previously executed Compare instruction.
transfer control to instruction J A1 specified by Field A. If less than (or
for alphanumeric comparison), transfer control to instruction J A2 specified
B. If greater than, allow control to pass to the next sequential-instruction
The result of a Compare instruction is the setting of the Comparator based on the
relationship of OP 1 to OP 2. If the Compare was a numeric comparison, the
Comparator is set to one of three conditions: equal, less than, or greater than. If
the Compare was an alphanumeric comparison, the Comparator is set to one of two
conditions: equal, or unequal. The Comparator remains set until another Compare
instruction is executed.
The purpose of the JT instruction is to test the setting of the Comparator, and
transfer control to the addresses specified in the JT instruction, based on the
setting. There are three possible settings of the Comparator as ~ result of a
numeric comparison, and only two addresses in the JT instruction. The necessary
"third" address is implied, and is the instruction which immediately follows the
JT instruction. If the previously executed comparison was an alphanumeric
comparison, only two settings are possible, so that the JT instruction will always
jump to one of the two addresses specified in the instruction, following an alphanumeric comparison.
Since the Assembler program assigns addresses to instructions, the addresses
specified in the JT instruction will usually be programmer's labels. The current
value of the ILC maintained by the Assembler program during Assembly processing
can also be used, by specifying the dollar sign symbol ($) with increment.
Example 1:
Given: A comparison has been made of the Quantity Ordered(OP l)to the
Quantity on Hand (OP 2).
Problem: If the Quantity Ordered is equal to Quantity on Hand, transfer control
to the instruction labelled SAME. If the Quantity Ordered is less than the Quantity
on Hand, transfer control to the instruction labelled SHIP. (If the Quantity
Ordered is greater than the Quantity on Hand, control will automatically pass to
the next instruction.)
-------~.-~~~
~-
..
------~~-.-~---.-
c
UNIVAC 1005
UP-4084
4
ASSEMBLER-SO
LABEL
OPERATION
OPERAND 2
OPERAND 1
I.
A.
*
6
1
SECTION:
FIELD A
INC.
:t
18
12
I.
A.
*
FIELD B
±
22
INC.
28
:t
FIELD C
INC.
38
32
I
I I ' ,
SIAIMIEI
IJ ,T, I I
S,H I IP I
I
I
I
J
I
_II
~
FIELD A; JA1 (equal):
If the Comparator is set to equal, the address of the MSL of the instruction
labelled SAME, locations 2 and 3 of the JT instruction, is transferred to the ICC.
FIELD B; JA 2 (less than):
If the Comparator is set to less than, the address of the MSL of the instruction
labelled SHIP, locations 4 and 5 of the JT instruction, is transferred to the ICC.
Example 2:
Given: The Employee Name from a detail card (OP 1) has been compared to the
Employee Name from a Master Card.
Problem: If the Names are equal, transfer control to the address which follows
the LSL of the JT instruction. If the names are unequal, transfer control to the
instruction labelled ERROR.
LABEL
OPERATION
I.
A.
*
6
1
I
:
I
IT
OPERAND 1
T
FIELD A
±
INC.
18
12
$
OPERAND 2
j
11
+5
I.
A.
*
1
FIELD B
22
E,RJRIOIR
±
INC.
28
±
FIELD C
32
I I
INC.
38
J II
I
L1
I
FIELD A; JA1 (equal):
The dollar sign symbol ($) causes the Assembler program to use the current
value of the Ins truction Location Counter with an increment of 5 as the J A 1
address of the JT instruction.
FIELD B; JA2 (unequal):
The address of the MSL of the instruction labelled ERROR is used as the JA2
address.
Solution: The source language instruction taken from the card which immediately
follows the JT instruction during the Assembly processing, will be assigned to
the address which follows the LSL of the JT instruction. During the Assembly
processing of the JT instruction, the ILC contains the address which is assigned
to the JT instruction MSL. The JT instruction will occupy that location, and 4
more. Thus the ILC ($) plus an increment of 5 wi'll be the same address that will
be assigned to the instruction which is assembled after the JT.
45
PAGE:
UNIVAC 1005
UP-4084
4
ASSEMBLER-SO
o
4.7.3. UNCONDITIONAL JUMP
Mnemonic:
LABEL
J
Mode:
OPERATION
I
JI
*
I
5'IA:
FIELD A
±
INC.
18
12
J,A,
I
I
NO
OPERAND 2
I
,,',
Length:
OPERAND 1
I.
A.
6
1
SPECIAL
46
PAGE:
SECTION:
I.
A.
*
INC.
±
FIELD C
28
,
,
I
±
FIELD B
22
I
I
I
INC.
38
32
I
,
I
I
I'
Function:
Transfer control to instruction JA specified by Field A.
When this instruction is executed, an unconditional transfer is made of the J A to
the ICC. Thus the address specified in Field A becomes the address of the next
instruction to be executed.
In many cases, a J instruction will be the last instruction of a sub-routine which
has been entered through use of the JR instruction.
The J A address occupies locations 4 and 5 in the object instruction.
o
4.7.4. JUMP RETURN
Mnemonic:
LABEL
JR
Mode:
I.
1
A.
*
I
,
I
'
,
J,R, ,
I
7
Length:
IA:
FIELD A
±
J
INC.
18
12
NO
OPERAND 2
OPERAND 1
OPERATION
6
SPECIAL
*
INC.
,
I
FIELD C
32
28
22
2,L
A
±
FIELD B
I.
A.
I
±
INC.
38
RA
I
I
I
The object language instruction produced from the source language JR above, has
the format and will appear in the Instruction Register as follows:
IR Locations
A
B
C
1
23
45
67
JR
RA
JA
2L
Function:
Transfer ascending, locations 3 and 2 of the IR (RA) specified by Field C;
beginning with the address 2L specified by Field B. Then transfer the J A
specified by Field A to the ICC.
c
UNIVAC 1005
UP-4084
SECTION:
The two characters produced from the RA (Return Address) are stored in locations
2 and 3. The two characters produced from the JA are stored in locations 4 and
5. The two characters produced from 2L are stored in locations 6 and 7. These
location numbers refer to the positions of the object instruction as it is stored in
memory, and to the positions the instruction will occupy in the Instruction Register
(IR) when the instruction is executed.
When the instruction is executed, the following operations are automatically performed:
1. Locations 2 and 3 of the IR are transferred (ascending) beginning at the memory
location whose address is in positions 6 and 7 of the IR.
2. Locations 4 and 5 of the IR are transferred to the Instruction Control Counter
(ICC) and are used to control the access of the instruction to be executed next.
The purpose of the JR instruction is to provide a simple method of interrupting the
sequential execution of instructions in order to execute a special subroutine.
After the execution of the special subroutine, control is to be returned to the instruction which sequentially follows the JR instruction.
The special subroutine is called a closed subroutine. This means that the
entrance (the first instruction executed) is closed as far as the initiation of the
subroutine by the sequential advance of the ICC. It also means that the exit
(the last instruction executed) is closed to prevent resumption of the program
through the sequential advance of the ICC.
A closed subroutine normally has the following form:
(1).
The first instruction to be executed (the entrance line) has a label which is
the name of the subroutine.
(2). The last instruction to be executed (the exit line) has a label, and is usually
an unconditional jump instruction (Operation J).
(3). If there are multiple points within the subroutine from which exit might occur,
they must transfer control to the exit line.
Using this form for closed subroutines, the JR instruction is then set up as
follows:
FIELD A; JA:
Contains the label of the entrance line of the subroutine.
FIELD B; 2L:
Contains the address of the LSL of the exit line of the subroutine.
FIELD C; RA:
C"
.
~
47
4
ASSEMB LER-BO
Contains the label of the address of the MSL of the instruction to which control is
to be transferred after the subroutine has been executed .
PAGE:
- --
r··-·-·---~-·-···-----·-·~--------··-----
- - - - - - ----
UNIVAC 1005
4
ASSEMBLER-SO
UP-4084
SECTION.
NOTE: If the return address (RA) of the JR instruction is to be the address of the
instruction stored sequentially following the JR instruction ($ + 7), Field C of the
JR instruction may be left blank. The Assembler program will automatically insert
the address equivalent of $ + 7 in locations 2 and 3 of the object instruction. If
the return address (RA) of the JR instruction is to be anything other than $ + 7,
the required address must be coded in Field C according to the rules for Assembly
System addressing.
48
PAGE:
o
Example 1:
Given: A subroutine has been established to calculate square root. The entrance
line is labelled SQRT. The exit line is a J instruction labelled EXIT ..
Problem: Execute the subroutine, and return control to the next sequential instruction.
LABEL
OPERATION
OPERAND 1
I.
A.
6
1
I
:
I
I
TR
*
FIELD A
INC.
18
12
SIO
±
OPERAND 2
R T
I.
A.
*
FIELD B
22
+E X I T
±
INC.
28
FIELD C
32
±
INC.
38
I
FIELD A; JA:
The address of the MSL of SQRT is used in Locations 4 and 5 of the object instruction.
o
FIELD B; 2L:
The plus sign (+) prefix to the label EXIT causes the address of the LSL of that
instruction to be used as the locations 6 and 7 of this instruction.
FIELD C; RA:
Blanks in Fie ld C cause the Assembler program to use the current value of the
ILC (the address of the JR instruction) plus 7 as the address RA in locations 2
and 3 of this instruction.
Solution: At the time the JR instruction is assembled, the ILC contains the
address assigned to the JR .instruction. The implied $ + 7 is the same as the
value which will be in the ILC when the Assembler program assigns an address
to the next instruction. At execution time, this two character address of the next
instruction is transferred automatically in ascending mode, from locations 3 and
2 of the IR to the LSL and LSL minus one of the instruction EXIT. These two
locations of the instruction EXIT constitute the J A of an unconditional jump (])
instruction.
After setting up the RA in the exit line, the two characters from locations 4 and
5 of the JR instruction are automatically transferred to the ICC. This causes the
instruction stored at SQRT to become the next instruction executed.
o
.... ,
UNIVAC 1005
UP-4084
c'
SECTION:
PAGE:
After the execution of the instructions in the subroutine, the instruction EXIT
will be executed. The J instruction stored at EXIT now contains a J A address
set up by the JR instruction. This J A address is the address of the instruction
stored sequentially following the JR instruction. Thus control is returned to the
main chain of the program.
When the square root subroutine is reused at another point in the program, the
entry is also made by a similar JR instruction. This JR instruction will set upa
new RA in the exit line (EXIT) which will return control to the instruction which
follows the new JR instruction.
The effect of the JR instruction can be produced by using a TK instruction followed
by a J instruction.
LABEL
OPERATION
I
I
:
I
1I
J,
I
INC.
,
: $,
,
S Q,R,T
I
FIELD B
I.
A.
18
I
-.l -.l
±
FIELD A
* 12
T,K
OPERAND 2
OPERAND 1
I.
A.
6
1
*
+ 12
±
22
INC.
I I
I
I
INC.
38
32
+ IE XII T - 1
I
±
FIELD C
28
I
I
I
I
I
I
.1
The instruction which is to follow the execution of the square root subroutine is
the one which will be coded and assembled following the J ins truction. The
address which will be assigned to that instruction is the value of the ILC at the
time the TK is assigned, plus 7 for the length of the TK instruction, plus 5 for
the length of the J instruction--$ + 12.
The use of the JR instruction thus saves the memory locations required for the J
instruction, the access time of the J instruction, and the programmer time to
calculate the return address.
4.7.5. JUMP COMPARE
Mnemonic:
LABEL
JK
Mode:
OPERATION
I.
6.
1
SPECIAL
Length:
7
IA:
OPERAND 1
A.
FIELD A
* 12
±
NO
OPERAND 2
INC.
18
I.
A.
*
FIELD B
22
±
INC.
±
FIELD C
32
28
INC.
38
I
I
I
:
I
11K, ,
K. , , ,
I
IIA
I
I
I
21L,
I
I
I
Function:
c)
49
4
ASSEMBLER-SO
Using the bit positions of K, specified in Field A, which contain binary 1 bits;
test the corresponding bit positions of the memory location whose address is
specified by 2L in Field C. If the bit positions of 2L which correspond to binary
1 bit positions of K all contain binary 1 bits, transfer control to the JA address
specified in Field B. If any of the bit positions of 2L which correspond to binary
1 bit positions of K do not contain a binary 1 bit, proceed with the next sequential
instruction (NI).
NOTE: Bit positions of 2L which correspond to binary zero positions of K are
ignored by the test and may contain binary zero or binary one.
UNIVAC 1005
UP-4084
4
ASSEMBLER-SO
50
-----i
.-.._ _ _ _ _ _"-_ _ _ _ _ _ _ _ _ _ _ _ _.-.._ _ _ _ _ _ _ _ _ _ _...L_ _ _ _ _ _ _--1L.;S;.,;E;.,;C;.,;T:.;,IO:.N;,;;';"""_ _.....L,;.P,;.;",:;G,:E,;.'
The purpose of the JK instruction is to perform a test for bit(s) present in the
contents of a memory location. If K contains only a single binary 1 in the X bit
position, and the contents of the memory location specified by Field C also
contains a binary 1 in the X bit position, the jump to JA will occur. If the memory
location specified by Field C does not contain a binary 1 in the X bit position,
the jump will not occur, and the program continues with the next sequential instruction (NI). The presence or absence of binary 1 's in the other bit positions
of 2L are not involved in the operation, and have no effect on the result.
If K contains multiple binary 1 bits, then each corresponding bit position of 2L
must also contain a binary 1, or the jump will not occur.
I
I,·
!
Example 1:
Problem: Test the information stored in location 80 for the presence of a binary
1 in the X bit position. If present, transfer control to CRDT.
LABEL
OPERATION
OPERAND 1
I.
A.
6
1
*
I
I
I
I
I
J,K
I
I
FIELD A
12
±
OPERAND 2
INC.
18
*
,
I
I
I.
A.
I
FIELD B
±
INC.
28
22
FIELD C
32
l:(,8 IO
CIR D,T
±
INC.
38
I
I
c
FIELD A; K:
The apostrophe (') is the UNIVAC 1005 character which contains a binary 1 in
only the X bit position.
FIELD B; JA:
The address of the MSL of the instruction labelled CRDT is used as the J A of
this instruction.
FIELD C; JA:
l:( 80 is the decimal address of the location which contains the information from
card column 80 of Read Input.
Solution: If the information stored from card column 80 contains a binary 1 in the
X bit position, the jump to CRDT will occur.
Example 2:
Problem: If card column 25 contains only the letter D, transfer control to DED.
If card column 25 contains anything other than the letter D, transfer control to
NOTO.
D = 010 111
c
...
-~-~.~.~------~.
------
.---~
..-
--
UNIVAC 1005
UP-4084
ASSEMBLER-SO
4
Rev. 1
SECTION:
LABEL
OPERATION
OPERAND 1
I.
~. 12
6
1
FIELD A
±
OPERAND 2
INC.
18
*
±
FIELD B
I.
A.
22
INC.
±
FIELD C
28
32
INC.
38
I
I
I
:
I
i TIKI
I
,
"
I
••
N,O,T.D,
I
I
J:t, 2 15 1
0
I
Ii
I
I
•
•
1, K
~2
N 0. T. D
5
5
o ,
I
•
:
JIK.
I
•
.
N.O.T:o.
•
0
I
Do
0
0
••••
••
D,E.D.
••
••
•
I
•
o
0
•
0
••
0
J:t. 2.5.
•
I •
I •
I
I
0
I
Instruction 1:
If card column 25 contains a binary 1 in the X bit position, it does not contain
only the letter D, and control is transferred to NOTD.
Instruction 2:
If card column 25 contains a binary 1 in the 8-bit position (X S3 code for 5), it
does not contain only the letter D, and control is transferred to NOTD.
Instruction 3:
The previous two instructions have eliminated the possibility of the presence of
binary 1 in the X bit and the 8-bit pos itions. If the remaining positions all contain
binary 1 bits, this instruction will transfer control to DED. If card column 25 did
not contain a D, this instruction will not jump, and control will sequentially pass
to the next instruction--which is NOTD.
The character K will appear in location 2 of the object instruction. Location 3
is not used. Locations 4 and 5 will contain the] A address. Locations 6 and 7
will contain the address of the location to be tested.
NOTE: Octal coding may be used in Field A to specify K of the JK instruction.
Column 12 must contain a number sign (It), and columns 13 and 14 must contain
two octal digits whose bit pattern must produce the required K. Columns 15 and
16 of the coding form must contain fiJfiJ. Location 3 of the JK instruction is ignored.
4.7.6. JUMP LOOP
Mnemonic:
LABEL
•
:
I
Mode:
OPERATION
IT L
*
•
SPECIAL
Length:
7
IA:
OPERAND 1
I.
A.
6
1
JL
FIELD A
OD
±
•
NO
OPERAND 2
INC.
I.
A.
*
18
12
!
FIELD B
22
il.A
±
INC.
28
FIELD C
32
Is.
±
INC.
38
I
••
51
PAGE:
+ 2 ••
UNIVAC 100S
UP-4084
52
4
ASSEMBLER-SO
SECTION.
Function:
Subtract 1 from locations 2 and 3 of the IR (which will contain DD specified by
Field A). Transfer ascending the result from locations 2 and 3 of the IR to 2L
specified by Field C. If the result is positive or zero, transfer control to the JA
specified in Field B. If the result is negative, proceed with the next sequential
instruction.
PAGE:
o
NOTE: 2L must specify the address of the least significant 0 in memory, Maximum
OD = 99.
$ + 2 in Field C may be left blank, in which case the Assembler will provide the
$ + 2 address.
The purpose of the JL instruction is to provide a means to control the number of
times a series of instructions are to be repetitively executed. The series of instructions is called a loop.
A loop is established to perform a common operation on each of a set of similar
data, thus eliminating the need for a separate series of instructions for each of
the set of data.
A loop may consist of four sections
(1) Initialization
(2) Processing
(3) Modification
(4) Control
The Initialization section prepares the loop to be used for the first of the repetitive executions. The Processing section cons ists of the operations to be performed on the data. The Modification section changes the addresses in the
Processing instructions to refer to the next set of data. The Control section
determines when the loop has been executed the required number of times.
The Control section of a loop in the UNIVAC 1005 will usually consist of a single
JL instruction. The DO portion of the JL instruction must be set to a beginning
condition in the Initialization section, due to the fact that DO is changed during
the execution of the loop. Assume a loop is to be executed three times. DD will
be 02 in the JL instruction at load time. After the execution of the Processing
and Modification sections, the JL instruction is executed for the first time. 2L
specifies the memory address of DO. DD is reduced by 1 in the IR and the result
(01) is stored at 2L, replacing the 02. The result is positive, so the jump occurs
to JA which usually specifies the first instruction in the Processing section.
After the execution of the Processing and Modification sections, the JL instruction
is executed the second time. DO, which now is 01, is again reduced by one in the
IR, and the result (00) is stored at 2L, replacing the 01. The result is zero, so
the jump occurs to JA. After the execution of the Processing and Modification
sections, the JL instruction is executed the third time. DO, which now is 00, is
o
UNIVAC 1005
UP-4084
4
ASSEMBLER·SO
c
again reduced by one in the IR, and the result (-1) is stored at 2L, replacing the
00. This time, the result is negative. Therefore,the jump to JA does not occur,
and the program continues with the instruction (NI) which sequentially follows
the JL instruction. The loop has been executed exactly "DD" + 1 times, three in
this example. However, the value of DD in the stored JL instruction has been
changed by the execution of the loop and now reads -1. Before the loop is executed
again, the value of DD must be re-stored to the correct number of times the loop
is to be executed. This is usually accomplished in the Initialization section by
using a TK instruction with KK equal to the initial value of DD. The 2M and 2L
of the TK instruction specifies the address of the DD portion of the JL instruction.
A skeleton example of the coding for the previously described loop is as follows:
LABEL
OPERATION
I.
A.
*
6
1
OPERANO 1
FIELD A
±
OPERANO 2
INC.
18
12
I. . FIELD B
A.
* 22
±
INC.
28
FIELD C
32
±
INC.
38
I
I IN IITI
TIK
02
I
I
1
P
I : I
I
~OIC
I I
S
I
I I
I
M 0 D'F Y
,
1
I
I
I
~
I
I
I
1
I
,
,
I
,
I
I
,
CNTRL+ 21 I
I
,
1
I : I
I I
I
C,N TIR L JILl
I
,
C N T RL + 1
1 ,
02
I
1
I.
,
I
11
,,
11 . L l
I
I
i
I I
1
I
PROCS
I
CNTRL+ 2
53
PAGE:
SECTION:
I
The loop is entered by executing the instruction labeled UNIT. This sets DD
equal to 02 in the JL instruction, labeled CNTRL. There are usually other
operations required in the Initialization section. The fact that DD is 02 when
loaded, and is reset to 02 for the first use of the loop should not be of concern to
the programmer. Notice that Field C specifies the address of DD in memory.
NOTE: If Field C is left blank by the programmer, the Assembler automatically
provides the value of $ + 2 for Field C.
The Modification section will usually involve the use of the COUNT (CC) instruction, which is explained in Section 4.8.
Section 1.6. on Indirect Addressing contains an example of the use of a loop. In
the example, Instruction 6 would be a JL instruction with a DD of 03, and a JA of
the address of Instruction 1, the first instruction of the Processing section. Instruction 5 would be replaced by the instructions necessary to perform the
Modification section requirements. Instruction 1 would be preceded by the Initialization section instructions including a TK instruction which sets the DD of the
JL instruction to 03.
UNIVAC 1005
UP-4084
Rev. 1
ASSEMB LER·80
4
SECTION:
o
4.7.7. JUMP INDIRECT
Mnemonic:
LABEL
JI
OPERATION
1
I
I
:
I
J, I,
SPECIAL
Length:
7
IA:
*
,
FIELD A
±
I
INC.
,J ,A
,
I.
A.
*
18
12
YES
OPERAND 2
OPERAND 1
I.
A.
6
I
Mode:
54
PAGE,
FIELD B
±
22
,
I
INC.
28
I
±
FIELD C
INC.
38
32
I
I
I
,
I
I
I
I
Function:
Transfer descending two locations be ginning with the IJ A (Indirect Jump Address)
specified in Field A to the Instruction Control Counter (ICC).
NOTE: If Indirect Addressing is specified (asterisk in column 11) two levels of
IJA will occur.
Field A of a Jump instruction 0) specifies the address to which control is to be
transferred. Field A of the Jump Indirect instruction (1) specifies the address of
the address to which control is to be transferred.
The JI instruction is a pseudo-operation in the UNIVAC 1005 Assembly System.
The JI instruction produces a TD command which has an OP 1 of the IJA, and an
OP 2 of the ICC. OP 1 contains the address of an instruction (2 characters).
When these two characte'rs are transferred to the ICC, they are used to control the
access of the next instruction. Thus control is transferred, not to the IJA, but to
the address stored in the locations specified by the IJA.
'\
C
)
Assume there are several points in a closed subroutine at which the processing is
concluded. Each one of these points must return control to the instruction which
follows the JR instruction used to enter the closed subroutine. This can be
accomplished by coding a Jump 0) instruction at each of the ending points in the
subroutine which transfers control to the exit instruction. The J A of the exit
instruction was set up by the JR instruction to transfer control to the instruction
following the JR instruction. However, by coding a Jump Indirect (1) instruction
at each of the ending points with an IJ A that refers to the J A portion of the exit
instruction, the execution of the second jump is eliminated.
Assume that EXIT is the label of the exit instruction of a closed subroutine. Each
of the ending points would conclude with the following instruction:
LABEL
OPERATION
6
1
I
~
I
I
I
I
J ,I, ,
OPERAND 2
OPERAND 1
I.
A.
*
FIELD A
12
E,X, I, T,
±
INC.
18
+ 3
I.
A.
*
I
FIELD B
22
±
INC.
28
I
I
±
FIELD C
32
I
INC.
38
,
I
I
I
I
c
.M·······
...... _..
_~~
...... _._. .. ..... .....,,_...,
~
~.."~.,,~.~,,~
...._..........___......... _____.__._....
_~
..
UNIVAC 1005
UP-4084
SECTION:
PAGE:
When the JI instruction is executed, the two character address stored in locations
4 and 5 of EXIT, by the JR instruction, are transferred to the ICC. This effectively
transfers control to the instruction following the JR instruction.
4.8. COUNT
Mnemonic:
LABEL
:
Mode:
OPERATION
6
1
CC
CC
I
SPECIAL
Length:
5
IA:
OPERAND 1
I.
A.
*
FIELD A
D.D.
!
I
I
NO
OPERAND 2
INC.
18
12
I.
A.
*
I
FIELD B
!
22
21M,
INC.
28
I
I
±
FIELD C
32
I
I
INC.
38
I
55
4
Rev. 1
ASSEMB LER·80
I
I
I
1
I
Function:
Using address arithmetic, modify by DD, specified in Field A; the two character
Row, Column, and Bank address stored beginning at 2M, specified by Field B.
The purpose of the CC instruction is to provide a means of address modification
according to the special logic of row, column, and bank addressing employed 'in the
UNIVAC 1005. Addresses are specified by the full 6-bit positions of two adjacent
characters. The Arithmetic Unit of the UNIVAC 1005 operates on a 4-bit numeric
basis. Thus, the Add and Subtract instructions cannot be used for address modification.
The CC instruction operates on the full 6 bits of the two character address stored
in the locations specified by 2M using the decimal value of DD as the modifier. If
the address is to be decremented, a minus sign (-) is placed in column 12 of Field
A, and DD is placed in columns 13 and 14. If the address is to be incremented,
DD is placed in columns 12 and 13 and assumed to be plus. DD must always be two
digits (00 through 99 maximum). If DD is less than ten, a 0 is placed in column 12.
When DD is a decrement, the Assembler program places an X bit over both of the
numeric digits in the object instruction.
2M usually specifies the address of the MSL of the A portion of another instruction
which is to be modified to reference a new set of data.
Section 1.6.on Indirect Addressing contains an example of the use of a loop. The
Modification section of the loop would consist of a single CC instruction that would
replace Instruction 5. The CC instruction would modify the A portion of Instruction
1 by the number of locations required for each entry in constant storage. Since two
characters are required for MSL and two for the LSL of each of the four fields in a
Transaction, the value of DD must be 16.
Assume that Entry 1 of the constant storage area was labeled ENTl, and the
Secondary Address Table was labeled SECAT. Instruction 1 would be:
UNIVAC 1005
UP-4084
4
ASSEMBLER-SO
LABEL
I.
A.
FIELD A
!:
* 12
!
P~R OIC S TD
INC.
18
E NIT 11
FIELD B
I.
A.
*
28
22
INC.
!:
o
38
32
SECAT + 1 15 1
SIE,CIA,T
I
FIELD C
INC.
!:
56
PAGE:
OPERAND 2
OPERAND 1
OPERATION
6
1
SECTION:
I
The first execution of this instruction will cause a descending transfer beginning
with the MSL of ENT1 (Entry 1 of constant storage) to the MSL of SECAT (the
Secondary Address Table). The transfer will continue until the LSL of the
Secondary Address Table has been filled. The remainder of the processing will
then operate on Transaction 1.
Before Instruction 1 is executed the second time, the two characters in locations
2 and 3 of Instruction 1 must be modified to transfer from Entry 2 of constant storage
to the Secondary Address Table. The following CC instruction would be used to
modify PROCS (Instruction 1, locations 2 and 3).
LABEL
6
1
:
I
OPERAND 2
OPERAND 1
OPERATION
I.
A.
*
ac
FIELD A
!:
INC.
*
18
12
FIELD B
I.
A.
±
P ROC S + 1
1 6
INC.
32
28
22
±
FIELD C
INC.
38
I I
I
I I
·" .
C
~
Each time this CC instruction is executed, the OP 1-MSL address in PROCS is incremented by 16. This will cause successive transfers of each of the entries in
constant storage. However, after the last execution of the loop, the A portion of
PROCS will have an address of the location which follows the last location of
constant storage. The Initialization section must then contain the following TK
instruction which is executed before PROCS:
LABEL
OPERATION
6
1
:
I
TK
OPERAND 1
I.
A.
*
FIELD A
12
: E1N ,T,l
±
.
~
OPERAND 2
INC.
18
I.
A.
*
1
FIELD B
22
±
INC.
28
PIRjOjC,S + 1, ,
FIELD C
±
I.
INC.
32
138
PjR1O,CjS +
b~
i
I
The use of the colon (:) will cause the Assembler to use the address of ENT1 as
KK in the TK instruction. These two characters are transferred to locations 2 and
3 of PROCS, so that each first execution of PROCS will refer to Entry 1 of constant
storage.
The complete coding for the loop is as follows:
o
UNIVAC 1005
UP-4084
LABEL
OPERATION
*
6
1
SECTION:
OPERAND 1
I.
A.
FIELD A
12
±
PAGE:
OPERAND 2
INC.
18
I.
A.
*
FIELD B
22
±
INC.
28
±
FIELD C
32
INC.
38
I
I N I'TI
TK
13 3
C N TLR1L + 1
C N T
T K,
: E N,T 1
PROCS+ 1
PROCS + 2
I
I
I
R~L
+ 2
I
P,R,O:C,S T,O, ,
,
I
E,N I TI1,
I
I
S,E1C,A,T
I
I
,
I
,
,
:
,
A,O ,
I
I
* S,E,C,A,T + 2, ,
* S ,E,CIA,T + 4,
,
,
,
I
A. Q
I
I
*S,E,C,AT + 6 ,
* S E C A T+ 8
j
it,
L
* S,E,C A,T + 1 i13 L * S E,C,A,T + 1,2,
:
L S ,U 1 L
M,o,olF Y C,C,
,
I
C~N1TLRt l J,LL L
,
57
4
ASSEMBLER-SO
I
I
1,6, , ,
,
I
I3 L3 L , L
L L
I
P R,O,C,S + 1, ,
P,R,OLC,S
S,E,C,A,T + 1,5,
,
,
I
,
I ,
I
I
,
,,
C,N TLR, L + 2
, I
,
4.9. EDIT INSTRUCTIONS
The UNIVAC 1005 instruction repertoire includes two types of instructions which
perform editing and logical operations. The logical operations provide for the
deletion (erasing) of 1 bits and the insertion (superimposing) of 1 bits on the bit
positions of a memory location. The edit instruction provides for the preparation
of output data for printing and punching. The edit functions include such things
as zero suppression, character insertion, asterisk fi1l, etc.
The erase function performs logical (or binary) multiplication of the corresponding
bit positions of a constant and the contents of a memory location and stores the bit
by bit product back in the same memory location. A binary zero in either or both
corresponding bit positions of the constant and the memory location contents will
produce a zero bit in the product. Only if both bit positions contain a binary 1 will
the product bit be binary 1. Thus 13 x 13 = Ilem: Write a block of magnetic tape from TPOUT.
LABEL
OPERATION
OPERAND 1
I.
6
1
I
:
WT
FIELD A
A.
*
12
±
OPERAND 2
INC.
18
+TPOU + 2
I.
A.
*
FIELD B
22
TPOUT
±
INC.
28
FIELD C
32
±
INC.
38
+TPOU + 5
I
I
I
Consideration need not be given to the contents of the five locations to the right
of the LSL of TPOUT;. since they are not changed by this instruction.
c
NOTE: The Servo on which writing will occur is the Servo last set by a Set
Condition (SC) instruction.
93
PAGE:
- . - - - - - - - - - . -.. - - . - - -...----.- - - . - - - - . - - - - - r - - - - - - - . - - - - - - - - - , - - - . - - - UNIVAC TOOS
UP-4084
4
ASSEMB LER·80
SECTION:
94
PAGE,
A Servo must be set by an SC instruction before the first magnetic tape operation
is given. Console Clear leaves no Servo set.
o
4.13.5. RECEIVE DATA LINE
Mnemonic:
LABEL
RD
OPERATION
,
:
DESCENDING
Length:
7
OPERAND 1
I.
A.
*
6
1
Mode:
RD
FIELD A
±
NO
OPERAND 2
INC.
18
12
IA:
I.
A.
*
1 M
FIELD B
±
FIELD C
INC.
28
22
±
32
INC.
38
2 L
2 M/ 1 M
I
I
Function:
Receive from the Data Line. Store descending beginning at OP 2-MSL specified
in Field B, continuing until OP 2-LSL specified in Field C has been filled. The
last two characters stored in OP 2 will be the End of Message character and the
Longitudinal Parity Character. The preceding characters will be the Data
characters.
OP 2-MSL is automatically used as OP 1-MSL. Field A which specifies OP 1LSL should contain the same address as Field B. Thus OP 1 becomes a one
character location. There must be an OP 1 in an RD function fo.r control purposes.
Blank addressing should not be used in Field C.
Example 1:
Given: RDIN is the label of a DA declarative which established an 82 location
area.
Problem: Receive the contents of the card transmitted.
LABEL
OPERATION
I.
A.
*
6
1
:.
R,D,
OPERAND 1
1
,
FIELD A
12
R,D,I,N,
±
OPERAND 2
INC.
18
I.
A.
*
,
FIELD B
22
R,D I,N
±
INC.
28
FIELD C
32
,
+ ,RP I IN
±
INC.
38
,
I
The contents of the transmitted card will be stored in RDIN through RDIN + 79.
RDIN + 80 will contain EOM. RDIN + 81 (+ RDIN) will contain the LPC.
o
UNIVAC 1005
UP-4084
PAGE:
SECT'ON:
(~
4.13.6. SEND DATA LINE
Mnemonic: SD
LABEL
Mode:
OPERATION
:
DESCENDING
Length:
7
*
SD
FIELD A
t
INC.
18
12
IA:
NO
OPERAND 2
OPERAND 1
I.
A.
6
1
I.
A.
*
1 L
±
FIELD B
22
INC.
28
1,M
±
FIELD C
32
INC.
38
,
2 L,
/.2 M
I
Function:
Send via the Data Line. Transfer descending to the Data Line, the information
beginning at the MSL of OP 1 specified in Field B, continuing until the LSL of
OP 1 specified in Field A has been transferred to the Data Line. Simultaneously
transfer descending, the same infoqnation to OP 2. The OP I-MSL is used as
the OP 2-MSL. OP 2-LSL specified in Field C must be the same as OP l-LSL
specified in Field A. Blank addressing should not be used.
The information to be transferred from memory to the Data Line consists of
Transmission Control Characters, and the data; in the following format:
OP 1, MSL to OP 1, MSL + 3
Four synchronizing characters
OP 1, MSL + 4
Space code
OP 1, MSL + 5 to n
Data
OP 1, LSL - 3
Turn off Request to Transmit--right hand
parenthesis ( ) )
OP 1, LSL - 2
End of Message Code
OP 1, LSL - 1 and OP 1, LSL
Space Codes
Example:
Problem: Transmit the contents of a card.
LABEL
OPER,ATlON
!
EO M'
OPERAND 1
I.
A.
*
6
1
DC, , ,
FIELD A
±
OPERAND 2
INC.
18
12
4, , , ,
I.
A.
*
+) B,
FIELD B
22
±
INC.
28
,
, ,
±
FIELD C
32
I
INC.
38
, , , ,
,
,
,
I
D,A T:~
, D A,
P,R,E: A,M D,C,
,
, , l ,
I
, I : ,
8 IIJ
, ,
I I I ,
T,D, I ,
5,
,,
, , I ,
$, R ,I,
S , , , ,
, ,
,
, , D,A T,A
'+ S,S,S
,
I
I
I
l, , ;G. C;
, , l
I
I I
I S,D, , ,
#llIJlftl ftl,lIJ
+,E,O,M,
95
4
ASSEMBLER-SO
.I
I
# ftl, 0 IIJIIIJ
, I
P R,E,A M
, ,
, ,
,
, I
,
I
# IIJ 2 0,IIJ
+EOM
,
_
...... .... _ - - - - - -
~"'-~~"-"'-----,----~----~'---'-'----------'--'"
UP-4084
- - . - -..
-------._.
......-
..--- ..
UNIVAC 1005
96
4
ASSEMBLER·SO
SECTION:
PAGE:
Solution: The DC and DA dec1aratives allocate a message area of storage which
contains the 5 constant preamble (PREAM), the data (DATA), and the 4 constant
trailer. These are allocated in reverse sequence to the order assembled.
The TD transfers the card data from Read Input storage to the data portion of
the message area. The GC sets Request to Transmit. The SD does the sending.
4.13.7. RECEIVE INTERFACE
Mnemonic:
LABEL
RF
Mode:
OPERATION
Length:
7
OPERAND 1
I.
A.
*
6
1
Descending
FIELD A
12
±
IA:
NO
OPERAND 2
INC.
18
I.
A.
*
FIELD B
±
22
INC.
28
FIELD C
32
±
INC.
38
!
...L J
1
I
I
RIFI
••
C.C • • •
•
M••••
••
LL ••
J
.L ...L
Function:
Receive data from the Unit selected by bits in CC specified in Field A, and store
in the area whose MSL is specified in Field B, and LSL is specified in Field C.
The address specified in Field B becomes OP 1-MSL and OP 2-MSL, and the
address specified in Field C becomes OP 1-LSL and OP 2-LSL during the RF
function. The M address occupies locations 4 and 5, and the L address occupies
location 6 and 7.
The bit positions of CC appear in locations 2 and 3 and are used to indicate
Unit Number, Input Control, and Output Control. Octal coding is used to specify
the bit pattern of CC. The number sign (#) followed by four octal digits is
required to specify octal coding.
The bit positions of CC and corresponding Unit Number and Input/Output Control
are as follows:
Location 2
Location 3
X not used
Y Output Control 3
8 Output Control 2
X not used
Y Input Control 3
8 Input Control 2
4 Output Control 1
2 Unit 4
1 Unit 3
4 Input Control 1
2 Unit 2
1 Unit 1
c
-------.---~----
.~.~.~"--,-,-_.
__ ",_ ,_
,~~,
".,
"~,,_,_.,,
"M.'. ___
~,,,,.,.,,,,,,
__ •_ _ _ _ _ _ _ _ _ _
~
____ ._,,_
UNIVAC 1005
UP-4084
Rev. 1
ASSEMBLER·SO
PAGE:
Example 1:
Problem: Receive an 80 column record from Unit 1 through Input Control 1 and
store in an 80 location area labeled IN!.
LABEL
OPERATION
I.
A.
*
6
1
OPERAND 2
OPERAND 1
±
FIELD A
INC.
18
12
I.
A.
*
FIELD B
±
INC.
±
FIELD C
32
28
22
INC.
38
I
I , I I
#1 0 10 10 15
R,F, I
I IN 11 ,
I
I
I ,
+ II,N,1 1
1
1
I
Solution: #0005 is octal for
Control 1.
000 000 000 101, which selects Unit 1 and Input
4.13.8. SEND INTERFACE
Mnemonic:
LABEL
SF
Mode:
OPERATION
6
1
Descending
Length:
OPERAND 1
I.
A.
*
FIELD A
12
±
,
:
I
I
SIFI I
C,C I I I
IA:
NO
OPERAND 2
INC.
I.
A.
*
18
FIELD B
I
MI
±
INC.
28
22
I
1
7
I
±
FIELD C
L,
INC.
38
32
,
I
I
1
I
Function:
Send data to the Unit Selected by bits in CC specified in Field A; from the area
whose MSL is specified in Field 8, and LSL is specified in Field C.
The address specified in Field 8 becomes the OP I-MSL and OP 2-MSL, and the
address specified in Field C becomes the OP 1-LSL and OP 2-LSL during the SF
function. The M address occupies locations 4 and 5, and the L address occupies
locations 6 and 7.
The bit positions of CC appear in locations 2 and 3 and are used to indicate Unit
Number, Input Control, and Output Control. Octal coding is Ij.sed to specify the
bit pattern of CC. The number sign (#) followed by four octal digits is required
to specify octal coding.
The bit positions of CC and corresponding Unit Number and Input/Output Control
are listed in the section on Receive Interface (Section 4.13.7)
c
97
4
SECTION:
UNIVAC 1005
UP-4084
4
ASSEMBLER·SO
SECTION:
98
PAGE:
Example:
Problem: Send to Unit 2 through Output Control 1 the information stored in a
160 location area labeled OU2.
LABEL
OPERATION
OPERAND 1
I.
FIELD A
A.
*
6
I
12
±
OPERAND 2
INC.
I.
A.
18
*
±
FIELD B
22
INC.
28
FIELD C
32
INC.
!
38
I
I
,
:
,
S ,F
I
,
I
#1 0 ,4 10,2
I
0,U 1 2 1
1
I
1
+ 10lU I 2 1
1
1
I
Solution: #0402 is octal for 000 100 0"0 010 which selects Unit 2 and Output
Control 1.
o
----~~-------.- ..
--.-
-~-------------
UNIVAC 1005
UP-4084
ASSEMBLER-SO
5.
5
SECTION:
OPERATING PROCEDURES
FOR 1005 ASSEMBLY
5.1. LOADING SOURCE PROGRAM
(1) Set Manual Alteration Switch No.1 on. Place the assembler deck in the input
hopper followed by the source code deck. Press Start, Clear, Feed and Run.
The line "Univac 1005 IPM Assembler Pass 1" is printed followed by "Reset
Alteration Switch No.1". Operator will reset Alteration Switch No. 1 and press
Run. In the event Alteration Switch No.1 is not reset and Run is pressed, the
message "Reset Alteration Switch No. I" is printed until the switch is reset.
During Pass 1, cards with invalid mnemonics will be l.isted. When the processor
halts (hopper empty) press Run and Stop. It is suggested that the cards with
invalid mnemonics be repunched and inserted into the source code deck and
Pass I rerun from the beginning. However, as an alternate recovery, the cards
with invalid mnemonics should be repunched and then rerun by pressing Feed
and Run. If Clear or Start was pressed at the end of the Pass, the cards with
invalid mnemonics could be rerun by (a) doing a manual start at location 148
or by (b) rerunning Pass I for those cards only. The new cards may then be
inserted in the intermediate deck.
(2) Place the assembler deck in the input hopper followed by intermediate deck 1.
Press Start, Clear, Feed and Run. The line "Univac 1005 IPM Assembler
Pass 2" is printed. During Pass 2, all assembler dec1aratives are listed except
for End. When the processor halts (hopper empty), press Run and Stop. Remove
intermediate deck 2 from the punch stacker.
(3) Place the assembler deck in the input hopper followed by intermediate deck 2.
Press Start, Clear, Feed and Run. The line "Univac 1005 IPM Assembler Pass
3" is printed. Either (a), (b), or (c) occurs.
(a) Final assembly listing occurs. Continue at (d).
(b) Halt #1 occurs followed by the printing of "Set Alt Switch 2". Operator
must set Alteration Switch No.2 and press Run. In the event Alteration
Switch No.2 is not set and Run is pressed, the message "Set Alt Switch
2" is printed until the switch is set. Continue at (d).
1
PAGE:
------------
~-
UNIVAC 1005
UP-4084
5
ASSEMBLER·80
SECTION:
(c) Neither (a) nor (b) occurs. Continue at (d).
(d) When the processor halts (hopper empty), press Run and Stop. Remove the
output deck from punch stacker. If (a) occurred, this is the final object
deck, and the assembly is complete. If either (b) or (c) occurred, repeat
steps (2) and (3) without resetting Alteration Switch No.2; use the most
recent output as intermediate deck 1.
NOTE:
If it is necessary to rerun passes 2 and 3, printouts "Rerunning Univac 1005 IPM
Assembler Pass 2" and "Rerunning Univac 1005 IPM Assembler Pass 3" will occur
while rerunning these respective passes.
5.2.
LOADING OBJECT PROGRAM
A load card is needed to load the object code program when assembly is complete.
In normal circumstances the first card of the assembly deck can be used for this
purpose. The load card should be reproduced to avoid misplacement. This card
inserts the necessary 4 bit into location R31/C32 of bank 1 and commences loading
the object program. When using this method for loading, the programmer should not
use memory locations 81 thru 92 in this program.
5.3.
FINAL LISTING
When assembly is complete, a final listing is produced. This listing contains the
following:
•
Original Source Code
•
Unfound Indicators
•
Sequence Numbers
• Object Code Instruction
•
Load Instruction
•
Diagnostic Message
The columns discussed represent the print positions starting from print position 1.
5.3.1. Original Source Code
Columns 1 to 61 inclusive is exactly the same as coded by the programmer.
1.
2.
3.
4.
5.
Instructions
Positive Constants
Negative Constants (minus in Col. 17)
Comment Card
Comment on Instruction Card
Columns
Columns
Columns
Columns
Columns
1 to 40
18 to 61
18 to 42
8 to 61
41 to 56
5.3.2. Unfound Indicators
Columns 59, 60 and 61 represent the unfound addresses of Field A, Field Band
Field C respectively. The character U will print in the respective column when
one or more of the Fields are unfound.
2
PAGE:
UNIVAC 1005
UP-4084
SECTION:
PAGE:
Example:
Transfer descending 80 columns of Read to the first 80 columns of Punch.
TD
Field A
$Rl
Field B
$Pl
Field C
$Plt 79
If Field B was not specified
TD
Field A
$Rl
Field B
Blank
Field C
$Pl + 79
the character U will print in column 60.
NOTE: If Field C was not specified
TD
Field A
$Rl
Field B
$Pl
Field C
Blank
the character U will not print because in this example Field C is optional (See
instruction formats).
5.3.3. Sequence Number
Columns 62 to 65 inclusive is the sequence number of the object program deck.
5.3.4. Object Code Instruction
Columns 67 to 73 is the Source Code Instruction translated to actual machine code.
Example:
Source Code Instruction
Column
Object Code Instruction
67
TA
III
68 69
$Rl +79
III
[
70 71
$PR
I
72 73
$PR+79
I
\
5.3.5. Load Instruction
Columns 74 to 80 places the Object Code Instruction in the assigned storage area.
5.3.6. Diagnostic Message
Column 82 indicated the following types of errors found:
1. '(Apostrophe, XBIT) Doubly defined label indication.
2. & (Ampersand, YBIT) Continuation of a Define Constant out of sequence.
3. 5 (Five, 8BIT) Define Sub-Field out of sequence.
4. 1 (One, 4BIT) Length of Define Area or Define Constant equal or less than
zero.
5. - (Minus, 2BIT) Extra continuation of a Define Constant.
c'
3
5
ASSEMBLER-SO
NOTE: A combination of the bit pattern of the above error messages may be
produced.
UNIVAC 1005
UP-4084
1
6
Rev. 1
ASSEMB LER-BO
SECTION:
6.
PROGRAM
TESTING
PAGE:
AIDS
The following tables and charts are provided to facilitate Program Testing. Table
6-1 can be used to determine several equivalent forms of actual addresses of assembled
instructions and constants. Table 6-2 describes basic characteristics of the assembled
UNIVAC 1005 Instruction Repertoire
ROW OR COLUMN WITHOUT BANK BIT
ROW OR COLUMN WITH BANK BIT
ROW
OR
COLUMN
NUMBER
CHAR.
EQUIV.
MACHINE
CODE
XY8421
OCTAL
EQUIV.
ROW
OR
COLUMN
NUMBER
1
space
0 0 0 0 0 0
00
1
MACHINE
CODE
XY8421
OCTAL
EQUIV.
.
1 0 0 0 0 0
40
*
1 0 0 0 0 1
41
!
1 0 0 0 1 1
43
M
1 0 0 1 1 1
47
@
1 0 1 1 1 0
56
6
Z
1 1 1 1 0 0
74
7
W,
1 1 1 0 0 1
71
1 1 0 0 1 0
62
2
]
0 0 0 0 0 1
01
2
3
"
03
3
4
4-
0 0 0 0 1 1
0 0 0 1 1 1
07
4
5
;
0 0 1 1 1 0
16
5
6
I
0 1 1 1 0 0
34
7
F
0 1 1 0 0 1
0 1 0 0 1 0
31
22
8
8
CHAR.
EQUIV.
9
1
0 0 0 1 0 0
04
9
J
1 0 0 1 0 0
44
10
5
0 0 1 0 0 0
10
10
N
1 0 1 0 0 0
50
11
:
0 1 0 0 0 1
21
11
%
1 1 0 0 0 1
61
12
-
0 0 0 0 1 0
02
12
$
1 0 0 0 1 0
42
13
2
0 0 0 1 0 1
05
13
K
1 0 0 1 0 1
45
14
7
0 0 1 0 1 0
12
14
P
1 0 1 0 1 0
52
15
B
0 1 0 1 0 1
25
15
S
1 1 0 1 0 1
65
53
16
8
0 0 1 0 1 1
13
16
Q
1 0 1 0 1 1
17
D
0 1 0 1 1 1
27
17
U
1 1 0 1 1 1
67
18
[
17
18
~
57
<
36
19
>
1 0 1 1 1 1
19
0 0 1 1 1 1
0 1 1 1 1 0
1 1 1 1 1 0
76
20
It
0 1 1 1 0 1
35
20
l:(
1 1 1 1 0 1
75
21
H
0 1 1 0 1 1
33
21
Y
1 1 1 0 1 1
73
22
C
0 1 0 1 1 0
26
22
T
1 1 0 1 1 0
66
23
\
0 0 1 1 0 1
15
23
(
1 0 1 1 0 1
55
24
G
0 1 1 0 1 0
32
24
X
1 1 1 0 1 0
72
25
A
0 1 0 1 0 0
24
25
/
1 1 0 1 0 0
64
26
6
0 0 1 0 0 1
11
26
0
?
0 1 0 0 1 1
23
27
+
1 0 1 0 0 1
1 1 0 0 1 1
51
27
28
3
0 0 0 1 1 0
06
28
L
1 0 0 1 1 0
46
29
9
0 0 1 1 0 0
14
29
R
1 0 1 1 0 0
54
30
E
0 1 1 0 0 0
30
30
V
1 1 1 0 0 0
70
31
&
0 1 0 0 0 0
20
31
i
1 1 0 0 0 0
60
=
0 1 1 1 1 1
37
32
)
1 1 1 1 1 1
77
32
Table 6-1.
UNIVAC 1005 Address Codes
Row, Column, Character and Octal Equivalent.
63
-- - - - - - - - - - - - - - - - - - - -
-."-----~-.
UNIVAC 1005
UP-4084
6
ASSEMBLER-SO
SECTION:
2
PAGE:
BANK BITS - (X BIT POSITION)
BANK
ROW
COLUMN
1
USE TABLE 1
2
USE TABLE 1
USE TABLE 1
USE TABLE 2
3
4
USE TABLE 2
USE TABLE 1
USE TABLE 2
USE TABLE 2
Example:
Convert R16/C6 Bank 4 into Octal.
Bank 4 requires the programmer to look up the Row in Table 2 and the Column in
Table 2.
Row 16 in Table 2 is Octal 53. Column 6 in Table 2 is Octal 74.
The octal address for R16/C6 B4 is #5374.
R2l1C30 Bank 3 is #7330.
R lIC 1 Bank 1 is #0000
LABEL
OPERATION
OPERAND 1
I.
A.
6
1
I
:
I
I
FIELD A
* 12
It
±
OPERAND 2
INC.
18
I.
A.
*
FIELD B
22
±
INC.
28
FIELD C
32
o 0 o0
t
INC.
38
I
I
o
------------------ -
.~---------
UNIVAC 1005
UP-4084
z
~
I-
~
C
'"
"'CII:w"
a..
,;»
0
SECTION:
z
U
CHARACTERS
..JO
st
~
w
DESCRIPTION
~~~ 2/3 4/5 6/7
1-""'8
""'~0
IN OBJECT
FORM
uCII:
Z
:2:
6
Rev. 1
ASSEMBLER-SO
3
PAGE:
~z
O~
:J:II- U
C)::I
MODE
INDIRECT
ADDRESSING
zDi:
wli;
..J~
TRANSFER INSTRUCTIONS
TA
TC
TO
TK
TN
TR
TX
0
Transfer Asc.
Transfer Clear
4
Transfer Desc.
]
Transfer Constant
2
Transfer Numeric
;
lL
1L
1M
KK
lL
Trans late
9
:i!:
lL
2M
2M
2M
2M
2M
2M
1M
I
7
F
lL
KK
lL
lL
2M
2M
2M
2M
2L
2L
2L
2L
7
7
7
7
Asc.
Add Algebraic
Add Magnitude
1
5
Divide
@
Multiply Long
Multiply
Subtract Magn.
Subtract Algebr.
Add Constant
M
lL
lL
lL
lL
lL
lL
lL
DO
2M
2M
2M
2M
2M
2M
2M
2M
2L
2L
3L
3L
3L
2L
2L
2L
7
7
7
7
7
7
7
7
Asc.
Asc.
A+D
A+D
A+D
Asc.
Transfer to Regi ster X
2L
2L
2L
2L
2L
2L
7
7
7
7
7
7
Asc.
Asc.
Oese.
-
5
Asc.
Asc.
Asc.
Oese.
Yes
Yes
Yes
Yes
Yes
Yes
No
COMPARE INSTRUCTIONS
Compare Alphanumeric
CA
CK
CM
CN
Compare Constant
Compare Magnitude
Compare Numeric
Asc.
Asc.
Asc.
Yes
Yes
Yes
Yes
ARITHMETIC INSTRUCTIONS
AD
AM
DV
ML
MU
SM
SU
AK
*
:
6
COUNT INSTRUCTION
CC
I
W
Count
I
±DD
2M
KK
-K
K1M
1M
5
Asc.
Asc.
I
Spec.
Yes
Yes
No
No
No
Yes
Yes
Yes
I
No
EDIT INSTRUCTIONS
c/
EL
ES
EE
ED
Edit Logicol
Edit Superimpose
Edit Erase
Edit
G
IM
2M
2M
2M
2L
7
7
7
7
Spec.
Spec.
Spec.
Oese.
No
No
No
Yes
SET INSTRUCTIONS
Set Conditions
Stop
No
No
CC
CC
JUMP INSTRUCTIONS
JC
JK
JL
JR
Jump on Conditions
X
Jump Compare
(
Jump Loop
JT
Jump Test
Jump
Jump Ind irect
J
N
Y
J
JI
Jump Return
/
]
CC
KDO
RA
JA=
-
JA
JA
JA
JA
JA<
JA
2L
2L
-
IA
5
7
7
7
5
5
7
Spec.
Spec.
Spec.
Spec.
Spec.
Spec.
Spec.
No
No
No
No
No
No
Yes
I/O
No
No
No
No
No
No
No
INPUT /OUTPUT INSTRUCTIONS
GC
RT
WT
RD
SO
RF
SF
General Commands
Read Magnetic Tape
Write Magnetic Tape
Rece ive Data Line
Send Data Line
Receive Interface
Send Interface
%
CC
$
K
P
S
Q
U
lL
1M
lL
CC
CC
CC
2M
M
M
M
M
M
CC
2L
2L
2L
2L
L
L
7
7
7
7
7
7
7
Dese.
Dese.
Dese.
Dese.
Dese.
Dese.
LEGEND
SYMBOL
c'
lL
1M
2L
2M
3L
-K
KKK
IA
DESCRIPTION
Operand 1 Least Significant Character
Operand 1 Most Significant Character ..
Operand 2 Least Significant Character
Operand 2 Most Significant Character
Least Significant Character of Product or Quotient
One Character right justified
One Character left justified
Two Characters
Indirect Jump Address
DO
CC
JA
M
L
ASC.
DESC.
AtD
RA
Two Decimal Digits
Characters whose: bits represent cond itions of Flip Flops
Address of Next Instruction of a Jump
Most Significant Position of Both Operand 1 and 2
Least Significant Position of Both Operand 1 and 2
Ascend ing
Descend ing
Ascending and Descending
Not Applicable
Return Address
Table 6·2. UNIVAC 1005 Instruction Repertoire
c
UNIVAC 1005
UP-4084
SECTION:
APPENDIX
.
A.
-
w
"
'"
UNIVAC 1005
ASSEMBLER CODING
".
«
"
:'
"J
"':
.'.
I>.
I
I
'
.. .
PAGE:
FORM
,
.,
u.
0
liI
iii
w
~
.
I>.
w
--.--------------------------~
:«<
•
~
iJ'
~
(~~
§
IL
I!I
------------------------------
~
2
""
D
D
U
.,
IE
w
m
:E
oJ
~
~
w
ID
ID
c(
""
N
"g
.."
..:iL
~
l;j
~
"w-'
iL
!:::
"-i*
-"
~
':i
0(
"
iL
:'I
~ "..:
:::
'ci-
("
~,
------------------------------
:E
IE
D
z
"
U
eI: I!
->Z
:J
I
i
I
I
I
g.>=
~
II<
"
0
II<
I>.
"
..:
:5'"
1
Appendix A
ASSEMBLER-SO
c
I
.~
..~.
________
~
~
__
~
~
_
c
~
__ _ _ _ _ ._ _ _ _ _ _ _ _ _ _ _ _
~
___
~
~
~
~
~
~
~
_
__
UNIVAC 1005
UP-4084
ASSEMBLER-SO
Appendix B
SECTION:
APPENDIX
B.
UNIVAC 1005
INSTRUCTION
OPERATION
DESCRIPTION
CODE
TIMING
1005 II AND III
1005 1
Transfer Instructions
Transfer Descend ing
Transfer Ascend ing
Transfer Clear
Transfer Numeric
Transfer Constant
Transfer to Register X
Trans late (Optional Feature)
Addition and Subtraction
Add Algebra ic
Subtract Algebraic
Add Magn itude
Subtract Magn itude
Add Constant
TO
TA
TC
TN
TK
TX
TR
176
176
176
176
176
176
176
n
+
+
+
+
+
+
+
16(n}us
143 + 13(n Jus
16(n}us
143 + 13(n}us
16(n}us
143 + 13(n}us
143 + 13(n}us
16(n}us
16(n)us
143 + 13(n Jus
16(n}us
143 + 13(n}us
143 + 26(n}us
32(n}us
number of characters in Operand 2
AD
SU
AM
SM
AK
176
176
176
176
176
n
+
+
+
+
+
143 +
16(n}us
143 +
16(n}us
143 +
16(n}us
143 +
16(n}us
16(n}us
143 +
number of characters
13(n}us
13(n}us
13(n}us
13(n}us
13(n Jus
in Operand 2
CN
CM
CA
CK
176 +
176 +
176+
176 +
n
16(n}us
143 +
143 +
16(n}us
143 +
16(n}us
143 +
16(n}us
number of characters
13 (n}us
13(n}us
13(n}us
13(n}us
in Operand 2
SC
STOP
144 uS
144 us
=
=
Compare Instructions
Compare Numeric
Compare Magn itude
Compare Alphanumeric
Compare Constant
=
Condition Indicators
Set Cond ition
Stop
117 us
117 us
Sequence Control Instructions
Jump Cond ition
Jump Test
Unconditional Jump
Jump Return
Jump Compare
Jump Loop
Jump Indirect
JC
JT
J
JR
JK
JL
JI
144
144
208
272
256
208
208
Count
CC
240 + 112(00 Jus *
195 + 91(DD}us**
Edit Instructions
Edit Logical
Edit Erase
Ed it Superimpose
Edit
EL
EE
ES
ED
240
240
240
208
195
195
195
169
us,
us,
us
us
us,
us,
uS
117
117
169
221
320 if jump 208
336 if jump 169
169
208 if jump
208 if jump
uS
us
us
+ 32(n Jus
n = number
us,
us,
us
us
us,
us,
us
169 if jump
169 if jump
260 if jump
273 if jump
uS
uS
us
+ 26(n}us
of characters in mask
Multiply Instructions
Multiply
Multiply Long
MU
ML
6.4 ms Avg.
18.5 ms Avg.
5.2 ms Avg.
15.0 ms Avg.
Divide
Divide
DV
13.7 ms Avg.
11.1 ms Avg.
GC
RT
WT
RD
SO
RF
SF
144
144
144
144
144
144
144
liD
General
Read Tape
Write Tape
Receive Dota Line
Send Data Line
Rece ive Interface
Send Interface
Ind irect Address ing
OPI - Add to normal time
OP2 - Add to norma I time
* Add 80 US for each change of row.
Add 80 uS for each change of bank.
us
us
us
US
us
us
us
+
+
+
+
+
+
+
liD
liD
liD
liD
liD
liD
liD
Time
Time
Time
Time
Time
Time
Time
64 us
80 us
** Add 65 us for each chonge of row.
Add 65 us for each change of bank.
117
117
117
117
117
117
117
us
us
us
us
us
uS
uS
52 uS
65 us
+
+
+
+
+
+
+
liD
liD
liD
liD
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