Xilinx XST User Guide For Virtex 4, 5, Spartan 3, And Newer CPLD Devices (UG627)
XST%20User%20Guide%20for%20Virtex-4%2C%20Virtex-5%2C%20Spartan-3%2C%20and%20Newer%20CPLD%20Devices
XST%20User%20Guide%20for%20Virtex-4%2C%20Virtex-5%2C%20Spartan-3%2C%20and%20Newer%20CPLD%20Devices
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- XST User Guide for Virtex-4, Virtex-5, Spartan-3, and Newer CPLD Devices
- Table of Contents
- Ch. 1: About This Guide
- Ch. 2: Introduction to Xilinx Synthesis Technology (XST)
- Ch. 3: XST HDL Coding Techniques
- Signed and Unsigned Support in XST
- Registers HDL Coding Techniques
- Latches HDL Coding Techniques
- Tristates HDL Coding Techniques
- Counters HDL Coding Techniques
- Accumulators HDL Coding Techniques
- Shift Registers HDL Coding Techniques
- Dynamic Shift Registers HDL Coding Techniques
- Multiplexers HDL Coding Techniques
- Decoders HDL Coding Techniques
- Priority Encoders HDL Coding Techniques
- Logical Shifters HDL Coding Techniques
- Arithmetic Operators HDL Coding Techniques
- Adders, Subtractors, and Adders/Subtractors HDL Coding Technique
- Comparators HDL Coding Techniques
- Multipliers HDL Coding Techniques
- Sequential Complex Multipliers HDL Coding Techniques
- Pipelined Multipliers HDL Coding Techniques
- Multiply Adder/Subtractors HDL Coding Techniques
- Multiply Accumulate HDL Coding Techniques
- Dividers HDL Coding Techniques
- Resource Sharing HDL Coding Techniques
- RAMs and ROMs HDL Coding Techniques
- ROMs Using Block RAM Resources HDL Coding Techniques
- Pipelined Distributed RAM HDL Coding Techniques
- FSM HDL Coding Techniques
- Black Boxes HDL Coding Techniques
- Ch. 4: XST FPGA Optimization
- FPGA Synthesis and Optimization
- FPGA Specific Synthesis Options
- Macro Generation
- DSP48 Block Resources
- Mapping Logic Onto Block RAM
- Flip-Flop Retiming
- Partitions
- Speed Optimization Under Area Constraint
- FPGA Device Optimization Report Section
- Implementation Constraints
- FPGA Device Primitive Support
- Cores Processing
- Specifying INIT and RLOC
- Using PCI Flow With XST
- Ch. 5: XST CPLD Optimization
- Ch. 6: XST Design Constraints
- About XST Design Constraints
- Mechanisms for Specifying Constraints
- Global and Local Constraint Settings
- Rules for Applying Constraints
- Setting Global Constraints and Options
- VHDL Attribute Syntax
- Verilog-2001 Attributes
- XST Constraint File (XCF)
- Constraints Priority
- XST Specific Non-Timing Options
- XST Command Line Only Options
- Ch. 7: XST General Constraints
- Add I/O Buffers (-iobuf)
- BoxType (BOX_TYPE)
- Bus Delimiter (-bus_delimiter)
- Case (-case)
- Case Implementation Style (-vlgcase)
- Duplication Suffix (-duplication_suffix)
- Full Case (FULL_CASE)
- Generate RTL Schematic (-rtlview)
- Generics (-generics)
- HDL Library Mapping File (-xsthdpini)
- Hierarchy Separator (-hierarchy_separator)
- I/O Standard (IOSTANDARD)
- Keep (KEEP)
- Keep Hierarchy (KEEP_HIERARCHY)
- Library Search Order (-lso)
- LOC
- Netlist Hierarchy (-netlist_hierarchy)
- Optimization Effort (OPT_LEVEL)
- Optimization Goal (OPT_MODE)
- Parallel Case (PARALLEL_CASE)
- RLOC (RLOC)
- Save (S)
- Synthesis Constraint File (-uc)
- Translate Off (TRANSLATE_OFF) and Translate On (TRANSLATE_ON)
- Ignore Synthesis Constraints File (–iuc)
- Verilog 2001 (-verilog2001)
- Verilog Include Directories (-vlgincdir)
- Verilog Macros (-define)
- Work Directory (-xsthdpdir)
- Ch. 8: XST HDL Constraints
- Automatic FSM Extraction (FSM_EXTRACT)
- Enumerated Encoding (ENUM_ENCODING)
- Equivalent Register Removal (EQUIVALENT_REGISTER_REMOVAL)
- FSM Encoding Algorithm (FSM_ENCODING)
- Mux Extraction (MUX_EXTRACT)
- Resource Sharing (RESOURCE_SHARING)
- Safe Implementation (SAFE_IMPLEMENTATION)
- Signal Encoding (SIGNAL_ENCODING)
- Safe Recovery State (SAFE_RECOVERY_STATE)
- Ch. 9: XST FPGA Constraints (Non-Timing)
- Asynchronous to Synchronous (ASYNC_TO_SYNC)
- Automatic BRAM Packing (AUTO_BRAM_PACKING)
- BRAM Utilization Ratio (BRAM_UTILIZATION_RATIO)
- Buffer Type (BUFFER_TYPE)
- Convert Tristates to Logic (TRISTATE2LOGIC)
- Cores Search Directories (-sd)
- Decoder Extraction (DECODER_EXTRACT)
- DSP Utilization Ratio (DSP_UTILIZATION_RATIO)
- Extract BUFGCE (BUFGCE)
- FSM Style (FSM_STYLE)
- Logical Shifter Extraction (SHIFT_EXTRACT)
- LUT Combining (LC)
- Map Entity on a Single LUT (LUT_MAP)
- Map Logic on BRAM (BRAM_MAP)
- Max Fanout (MAX_FANOUT)
- Move First Stage (MOVE_FIRST_STAGE)
- Move Last Stage (MOVE_LAST_STAGE)
- Multiplier Style (MULT_STYLE)
- Mux Style (MUX_STYLE)
- Number of Global Clock Buffers (-bufg)
- Number of Regional Clock Buffers (-bufr)
- Optimize Instantiated Primitives (OPTIMIZE_PRIMITIVES)
- Pack I/O Registers Into IOBs (IOB)
- Power Reduction (POWER)
- Priority Encoder Extraction (PRIORITY_EXTRACT)
- RAM Extraction (RAM_EXTRACT)
- RAM Style (RAM_STYLE)
- Read Cores (READ_CORES)
- Reduce Control Sets (REDUCE_CONTROL_SETS)
- Register Balancing (REGISTER_BALANCING)
- Register Duplication (REGISTER_DUPLICATION)
- ROM Extraction (ROM_EXTRACT)
- ROM Style (ROM_STYLE)
- Shift Register Extraction (SHREG_EXTRACT)
- Slice (LUT-FF Pairs) Utilization Ratio (SLICE_UTILIZATION_RATIO)
- Slice (LUT-FF Pairs) Utilization Ratio Delta (SLICE_UTILIZATION_
- Slice Packing (-slice_packing)
- Use Low Skew Lines (USELOWSKEWLINES)
- Use Carry Chain (USE_CARRY_CHAIN)
- Use Clock Enable (USE_CLOCK_ENABLE)
- USE_DSP48 (Use DSP48)
- Use Synchronous Set (USE_SYNC_SET)
- Use Synchronous Reset (USE_SYNC_RESET)
- XOR Collapsing (XOR_COLLAPSE)
- Ch. 10: XST CPLD Constraints (Non-Timing)
- Ch. 11: XST Timing Constraints
- Applying Timing Constraints
- XCF Timing Constraint Support
- Clock Signal (CLOCK_SIGNAL)
- Cross Clock Analysis (-cross_clock_analysis)
- From-To (FROM-TO)
- Global Optimization Goal (-glob_opt)
- Offset (OFFSET)
- Period (PERIOD)
- Timing Name (TNM)
- Timing Name on a Net (TNM_NET)
- Timegroup (TIMEGRP)
- Timing Ignore (TIG)
- Write Timing Constraints (-write_timing_constraints)
- Ch. 12: XST Implementation Constraints
- Ch. 13: XST Supported Third Party Constraints
- Ch. 14: XST VHDL Language Support
- VHDL Logic Descriptions
- VHDL IEEE Support
- VHDL File Type Support
- VHDL Debugging Using Write Operation
- VHDL Data Types
- VHDL Record Types
- VHDL Initial Values
- VHDL Objects
- VHDL Operators
- VHDL Entity and Architecture Descriptions
- VHDL Combinatorial Circuits
- VHDL Sequential Circuits
- VHDL Functions and Procedures
- VHDL Assert Statements
- VHDL Models Defined Using Packages
- VHDL Constructs Supported in XST
- VHDL Reserved Words
- Ch. 15: XST Verilog Language Support
- About XST Verilog Language Support
- Behavioral Verilog
- Variable Part Selects
- Structural Verilog Features
- Verilog Parameters
- Verilog Parameter and Attribute Conflicts
- Verilog Limitations in XST
- Verilog Attributes and Meta Comments
- Verilog Constructs Supported in XST
- Verilog System Tasks and Functions Supported in XST
- Verilog Primitives
- Verilog Reserved Keywords
- Verilog-2001 Support in XST
- Ch. 16: XST Behavioral Verilog Language Support
- Behavioral Verilog Variable Declarations
- Behavioral Verilog Initial Values
- Behavioral Verilog Local Reset
- Behavioral Verilog Arrays
- Behavioral Verilog Multi-Dimensional Arrays
- Behavioral Verilog Data Types
- Behavioral Verilog Legal Statements
- Behavioral Verilog Expressions
- Behavioral Verilog Blocks
- Behavioral Verilog Modules
- Behavioral Verilog Module Declarations
- Behavioral Verilog Continuous Assignments
- Behavioral Verilog Procedural Assignments
- About Behavioral Verilog Procedural Assignments
- Behavioral Verilog Combinatorial Always Blocks
- Behavioral Verilog If... Else Statement
- Behavioral Verilog Case Statements
- Behavioral Verilog For and Repeat Loops
- Behavioral Verilog While Loops
- Behavioral Verilog Sequential Always Blocks
- Behavioral Verilog Assign and Deassign Statements
- Behavioral Verilog Assignment Extension Past 32 Bits
- Behavioral Verilog Tasks and Functions
- Behavioral Verilog Recursive Tasks and Functions
- Behavioral Verilog Constant Functions
- Behavioral Verilog Blocking Versus Non-Blocking Procedural Assig
- Behavioral Verilog Constants
- Behavioral Verilog Macros
- Behavioral Verilog Include Files
- Behavioral Verilog Comments
- Behavioral Verilog Generate Statements
- Ch. 17: XST Mixed Language Support
- Ch. 18: XST Log File
- Ch. 19: XST Naming Conventions
- Ch. 20: XST Command Line Mode
- About XST Command Line Mode
- Launching XST in Command Line Mode Using the XST Shell
- Launching XST in Command Line Mode Using a Script File
- Setting Up an XST Script Using the Run Command
- Setting Up an XST Script Using the Set Command
- Setting Up an XST Script Using the Elaborate Command
- Running XST in Script Mode (VHDL)
- Running XST in Script Mode (Verilog)
- Running XST in Script Mode (Mixed Language)
- Synthesizing VHDL Designs Using Command Line Mode
- Synthesizing Verilog Designs Using Command Line Mode
- Synthesizing Mixed Designs Using Command Line Mode
XSTUserGuideforVirtex-4,
Virtex-5,Spartan-3,andNewer
CPLDDevices
UG627(v14.5)March20,2013
This document applies to the following software versions: ISE Design Suite 14.5 through 14.7This document applies to the following software versions: ISE Design Suite 14.5 through 14.7This document applies to the following software versions: ISE Design Suite 14.5 through 14.7This document applies to the following software versions: ISE Design Suite 14.5 through 14.7
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TableofContents
Chapter1AboutThisGuide......................................................................................11
GuideOverview...................................................................................................11
SupportedDevices...............................................................................................12
Chapter2IntroductiontoXilinxSynthesisTechnology(XST)...............................13
AboutXST............................................................................................................13
SettingXSTOptions............................................................................................13
Chapter3XSTHDLCodingTechniques..................................................................15
SignedandUnsignedSupportinXST................................................................16
RegistersHDLCodingTechniques.....................................................................17
LatchesHDLCodingTechniques........................................................................27
TristatesHDLCodingTechniques......................................................................32
CountersHDLCodingTechniques.....................................................................36
AccumulatorsHDLCodingTechniques.............................................................49
ShiftRegistersHDLCodingTechniques...........................................................53
DynamicShiftRegistersHDLCodingTechniques...........................................59
MultiplexersHDLCodingTechniques...............................................................63
DecodersHDLCodingTechniques....................................................................72
PriorityEncodersHDLCodingTechniques.......................................................78
LogicalShiftersHDLCodingTechniques..........................................................81
ArithmeticOperatorsHDLCodingTechniques................................................86
Adders,Subtractors,andAdders/SubtractorsHDLCoding
Techniques....................................................................................................88
ComparatorsHDLCodingTechniques...............................................................99
MultipliersHDLCodingTechniques...............................................................101
SequentialComplexMultipliersHDLCodingTechniques............................105
PipelinedMultipliersHDLCodingTechniques..............................................109
MultiplyAdder/SubtractorsHDLCodingTechniques...................................116
MultiplyAccumulateHDLCodingTechniques..............................................122
DividersHDLCodingTechniques...................................................................128
ResourceSharingHDLCodingTechniques.....................................................130
RAMsandROMsHDLCodingTechniques....................................................133
ROMsUsingBlockRAMResourcesHDLCodingTechniques......................188
PipelinedDistributedRAMHDLCodingTechniques...................................195
FSMHDLCodingTechniques..........................................................................199
BlackBoxesHDLCodingTechniques..............................................................212
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Chapter4XSTFPGAOptimization.........................................................................215
FPGASynthesisandOptimization...................................................................215
FPGASpecicSynthesisOptions.....................................................................216
MacroGeneration..............................................................................................216
DSP48BlockResources.....................................................................................221
MappingLogicOntoBlockRAM.....................................................................223
Flip-FlopRetiming.............................................................................................227
Partitions.............................................................................................................228
SpeedOptimizationUnderAreaConstraint....................................................228
FPGADeviceOptimizationReportSection.....................................................230
ImplementationConstraints.............................................................................236
FPGADevicePrimitiveSupport.......................................................................237
CoresProcessing................................................................................................243
SpecifyingINITandRLOC...............................................................................245
UsingPCIFlowWithXST.................................................................................251
Chapter5XSTCPLDOptimization.........................................................................253
CPLDSynthesisOptions...................................................................................253
ImplementationDetailsforMacroGeneration................................................254
CPLDSynthesisLogFileAnalysis...................................................................255
CPLDSynthesisConstraints.............................................................................257
ImprovingResultsinCPLDSynthesis.............................................................257
Chapter6XSTDesignConstraints.........................................................................261
AboutXSTDesignConstraints.........................................................................261
MechanismsforSpecifyingConstraints...........................................................262
GlobalandLocalConstraintSettings...............................................................262
RulesforApplyingConstraints........................................................................262
SettingGlobalConstraintsandOptions..........................................................263
VHDLAttributeSyntax.....................................................................................268
Verilog-2001Attributes......................................................................................268
XSTConstraintFile(XCF).................................................................................270
ConstraintsPriority............................................................................................272
XSTSpecicNon-TimingOptions...................................................................273
XSTCommandLineOnlyOptions...................................................................279
Chapter7XSTGeneralConstraints.......................................................................285
AddI/OBuffers(-iobuf)....................................................................................286
BoxType(BOX_TYPE)........................................................................................287
BusDelimiter(-bus_delimiter).........................................................................288
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Case(-case).........................................................................................................289
CaseImplementationStyle(-vlgcase)...............................................................289
DuplicationSufx(-duplication_sufx)...........................................................290
FullCase(FULL_CASE).....................................................................................292
GenerateRTLSchematic(-rtlview)...................................................................293
Generics(-generics)............................................................................................294
HDLLibraryMappingFile(-xsthdpini)...........................................................295
HierarchySeparator(-hierarchy_separator).....................................................297
I/OStandard(IOSTANDARD).........................................................................298
Keep(KEEP).......................................................................................................298
KeepHierarchy(KEEP_HIERARCHY).............................................................298
LibrarySearchOrder(-lso)................................................................................300
LOC.....................................................................................................................301
NetlistHierarchy(-netlist_hierarchy)...............................................................301
OptimizationEffort(OPT_LEVEL)...................................................................302
OptimizationGoal(OPT_MODE)....................................................................303
ParallelCase(PARALLEL_CASE).....................................................................304
RLOC(RLOC)....................................................................................................306
Save(S)...............................................................................................................306
SynthesisConstraintFile(-uc)..........................................................................307
TranslateOff(TRANSLATE_OFF)andTranslateOn
(TRANSLATE_ON)....................................................................................308
IgnoreSynthesisConstraintsFile(–iuc)...........................................................309
Verilog2001(-verilog2001).................................................................................309
VerilogIncludeDirectories(-vlgincdir)............................................................310
VerilogMacros(-dene)....................................................................................311
WorkDirectory(-xsthdpdir)..............................................................................312
Chapter8XSTHDLConstraints.............................................................................315
AutomaticFSMExtraction(FSM_EXTRACT)..................................................316
EnumeratedEncoding(ENUM_ENCODING).................................................317
EquivalentRegisterRemoval
(EQUIV ALENT_REGISTER_REMOV AL)................................................318
FSMEncodingAlgorithm(FSM_ENCODING)...............................................320
MuxExtraction(MUX_EXTRACT)...................................................................321
ResourceSharing(RESOURCE_SHARING)...................................................322
SafeImplementation(SAFE_IMPLEMENTATION)........................................324
SignalEncoding(SIGNAL_ENCODING)........................................................325
SafeRecoveryState(SAFE_RECOVERY_STATE)...........................................326
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Chapter9XSTFPGAConstraints(Non-Timing)...................................................329
AsynchronoustoSynchronous(ASYNC_TO_SYNC).....................................331
AutomaticBRAMPacking(AUTO_BRAM_PACKING).................................332
BRAMUtilizationRatio(BRAM_UTILIZATION_RATIO)............................332
BufferType(BUFFER_TYPE)............................................................................334
ConvertTristatestoLogic(TRISTATE2LOGIC)..............................................335
CoresSearchDirectories(-sd)...........................................................................337
DecoderExtraction(DECODER_EXTRACT)...................................................338
DSPUtilizationRatio(DSP_UTILIZATION_RATIO)....................................339
ExtractBUFGCE(BUFGCE)...............................................................................341
FSMStyle(FSM_STYLE)...................................................................................342
LogicalShifterExtraction(SHIFT_EXTRACT)................................................343
LUTCombining(LC).........................................................................................344
MapEntityonaSingleLUT(LUT_MAP)........................................................345
MapLogiconBRAM(BRAM_MAP)................................................................346
MaxFanout(MAX_FANOUT)...........................................................................347
MoveFirstStage(MOVE_FIRST_STAGE).......................................................349
MoveLastStage(MOVE_LAST_STAGE)........................................................351
MultiplierStyle(MULT_STYLE)......................................................................353
MuxStyle(MUX_STYLE)..................................................................................354
NumberofGlobalClockBuffers(-bufg).........................................................356
NumberofRegionalClockBuffers(-bufr).......................................................357
OptimizeInstantiatedPrimitives(OPTIMIZE_PRIMITIVES).......................358
PackI/ORegistersIntoIOBs(IOB)..................................................................359
PowerReduction(POWER)...............................................................................359
PriorityEncoderExtraction(PRIORITY_EXTRACT).......................................361
RAMExtraction(RAM_EXTRACT)..................................................................362
RAMStyle(RAM_STYLE)................................................................................363
ReadCores(READ_CORES).............................................................................365
ReduceControlSets(REDUCE_CONTROL_SETS)........................................367
RegisterBalancing(REGISTER_BALANCING)..............................................367
RegisterDuplication(REGISTER_DUPLICATION).......................................371
ROMExtraction(ROM_EXTRACT).................................................................372
ROMStyle(ROM_STYLE)................................................................................373
ShiftRegisterExtraction(SHREG_EXTRACT)................................................374
Slice(LUT-FFPairs)UtilizationRatio
(SLICE_UTILIZATION_RATIO)...............................................................376
Slice(LUT-FFPairs)UtilizationRatioDelta
(SLICE_UTILIZATION_RATIO_MAXMARGIN)...................................378
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SlicePacking(-slice_packing)...........................................................................379
UseLowSkewLines(USELOWSKEWLINES)................................................380
UseCarryChain(USE_CARRY_CHAIN).........................................................380
UseClockEnable(USE_CLOCK_ENABLE).....................................................382
USE_DSP48(UseDSP48)...................................................................................383
UseSynchronousSet(USE_SYNC_SET)..........................................................385
UseSynchronousReset(USE_SYNC_RESET).................................................387
XORCollapsing(XOR_COLLAPSE)................................................................388
Chapter10XSTCPLDConstraints(Non-Timing)..................................................391
ClockEnable(-pld_ce).......................................................................................391
DataGate(DATA_GATE)..................................................................................392
MacroPreserve(-pld_mp).................................................................................392
NoReduce(NOREDUCE).................................................................................393
WYSIWYG(-wysiwyg)......................................................................................393
XORPreserve(-pld_xp).....................................................................................394
Chapter11XSTTimingConstraints.......................................................................397
ApplyingTimingConstraints...........................................................................398
XCFTimingConstraintSupport.......................................................................399
ClockSignal(CLOCK_SIGNAL)......................................................................399
CrossClockAnalysis(-cross_clock_analysis)..................................................400
From-To(FROM-TO).........................................................................................401
GlobalOptimizationGoal(-glob_opt).............................................................401
Offset(OFFSET).................................................................................................404
Period(PERIOD)................................................................................................404
TimingName(TNM).........................................................................................405
TimingNameonaNet(TNM_NET).................................................................405
Timegroup(TIMEGRP).....................................................................................405
TimingIgnore(TIG)..........................................................................................406
WriteTimingConstraints(-write_timing_constraints)....................................406
Chapter12XSTImplementationConstraints........................................................409
ImplementationConstraintsSyntaxExamples................................................409
NoReduce(NOREDUCE).................................................................................410
PowerMode(PWR_MODE)..............................................................................411
RLOC(RLOC)....................................................................................................411
Chapter13XSTSupportedThirdPartyConstraints.............................................413
XSTEquivalentstoThirdPartyConstraints....................................................413
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ThirdPartyConstraintsSyntaxExamples........................................................416
Chapter14XSTVHDLLanguageSupport.............................................................417
VHDLLogicDescriptions.................................................................................417
VHDLIEEESupport..........................................................................................418
VHDLFileTypeSupport...................................................................................419
VHDLDebuggingUsingWriteOperation.......................................................420
VHDLDataTypes..............................................................................................423
VHDLRecordTypes..........................................................................................427
VHDLInitialValues..........................................................................................427
VHDLObjects....................................................................................................430
VHDLOperators................................................................................................431
VHDLEntityandArchitectureDescriptions...................................................432
VHDLCombinatorialCircuits..........................................................................438
VHDLSequentialCircuits................................................................................444
VHDLFunctionsandProcedures......................................................................450
VHDLAssertStatements...................................................................................452
VHDLModelsDenedUsingPackages...........................................................455
VHDLConstructsSupportedinXST................................................................458
VHDLReservedWords......................................................................................462
Chapter15XSTVerilogLanguageSupport...........................................................463
AboutXSTVerilogLanguageSupport.............................................................463
BehavioralVerilog..............................................................................................464
VariablePartSelects...........................................................................................464
StructuralVerilogFeatures................................................................................464
VerilogParameters.............................................................................................468
VerilogParameterandAttributeConicts.......................................................469
VerilogLimitationsinXST................................................................................470
VerilogAttributesandMetaComments...........................................................473
VerilogConstructsSupportedinXST...............................................................475
VerilogSystemTasksandFunctionsSupportedinXST.................................478
VerilogPrimitives..............................................................................................480
VerilogReservedKeywords..............................................................................481
Verilog-2001SupportinXST.............................................................................482
Chapter16XSTBehavioralVerilogLanguageSupport........................................483
BehavioralVerilogVariableDeclarations.........................................................484
BehavioralVerilogInitialValues......................................................................485
BehavioralVerilogLocalReset..........................................................................486
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BehavioralVerilogArrays.................................................................................487
BehavioralVerilogMulti-DimensionalArrays................................................487
BehavioralVerilogDataTypes..........................................................................488
BehavioralVerilogLegalStatements................................................................490
BehavioralVerilogExpressions.........................................................................491
BehavioralVerilogBlocks.................................................................................494
BehavioralVerilogModules..............................................................................494
BehavioralVerilogModuleDeclarations.........................................................495
BehavioralVerilogContinuousAssignments..................................................496
BehavioralVerilogProceduralAssignments....................................................497
BehavioralVerilogConstants............................................................................510
BehavioralVerilogMacros................................................................................510
BehavioralVerilogIncludeFiles.......................................................................511
BehavioralVerilogComments...........................................................................512
BehavioralVerilogGenerateStatements..........................................................513
Chapter17XSTMixedLanguageSupport.............................................................515
AboutXSTMixedLanguageSupport...............................................................515
MixedLanguageProjectFiles...........................................................................516
VHDLandVerilogBoundaryRulesinMixedLanguageProjects..................517
PortMappinginMixedLanguageProjects......................................................519
GenericsSupportinMixedLanguageProjects................................................520
LSOFilesinMixedLanguageProjects.............................................................520
Chapter18XSTLogFile..........................................................................................523
XSTFPGALogFileContents............................................................................523
ReducingtheSizeoftheXSTLogFile.............................................................527
MacrosinXSTLogFiles....................................................................................529
XSTLogFileExamples......................................................................................529
Chapter19XSTNamingConventions....................................................................551
XSTNetNamingConventions..........................................................................551
XSTInstanceNamingConventions..................................................................551
XSTNameGenerationControl.........................................................................552
Chapter20XSTCommandLineMode...................................................................553
AboutXSTCommandLineMode.....................................................................553
LaunchingXSTinCommandLineModeUsingtheXSTShell......................554
LaunchingXSTinCommandLineModeUsingaScriptFile.........................554
SettingUpanXSTScriptUsingtheRunCommand.......................................555
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SettingUpanXSTScriptUsingtheSetCommand.........................................558
SettingUpanXSTScriptUsingtheElaborateCommand...............................558
RunningXSTinScriptMode(VHDL).............................................................559
RunningXSTinScriptMode(Verilog)............................................................561
RunningXSTinScriptMode(MixedLanguage).............................................563
SynthesizingVHDLDesignsUsingCommandLineMode............................564
SynthesizingVerilogDesignsUsingCommandLineMode...........................566
SynthesizingMixedDesignsUsingCommandLineMode............................568
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Chapter1
AboutThisGuide
Thischapterincludes:
•GuideOverview
•SupportedDevices
•AdditionalResources
•Conventions
GuideOverview
ThisGuide:
•AppliesonlytothedeviceslistedinSupportedDevices.
•DescribesXilinxSynthesisTechnology(XST)supportfor:
–HardwareDescriptionLanguage(HDL)designs
–SupportedXilinx®devices
–DesignconstraintsfortheXilinxISE®DesignSuitesoftware
•Discussesoptimizationandcodingtechniqueswhencreatingdesignsforusewith
XST.
•ExplainshowtorunXSTfromthe:
–ISEDesignSuiteProcesswindow
–Commandline
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Chapter1:AboutThisGuide
SupportedDevices
ThisGuideappliestothefollowingXilinx®devicesonly:
•FPGADevices
–Virtex®-4
–Virtex-5
–Spartan®-3devicefamily,including:
♦Spartan-3
♦Spartan-3A
♦Spartan-3ADSP
♦Spartan-3AN
♦Spartan-3E
♦Spartan-3L
•CPLDDevices
–CoolRunner™XPLA3
–CoolRunner-II
–XC9500
–XC9500XL
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Chapter2
IntroductiontoXilinxSynthesis
Technology(XST)
Thischapterincludes:
•AboutXST
•SettingXSTOptions
AboutXST
XilinxSynthesisTechnology(XST)isaXilinx®applicationthatsynthesizesHardware
DescriptionLanguage(HDL)designstocreateXilinxspecicnetlistlescalledNGC
les.
TheNGCle:
•Isanetlistthatcontainsbothlogicaldesigndataandconstraints.
•TakestheplaceofbothElectronicDataInterchangeFormat(EDIF)andNetlist
ConstraintsFile(NCF)les.
Formoreinformation,see:
XilinxSynthesisTechnology(XST)-FrequentlyAskedQuestions(FAQ)
SearchforkeywordXSTF AQ.
SettingXSTOptions
Beforesynthesizingyourdesign,youcansetavarietyofoptionsforXST.
Designsareusuallymadeupof:
•Combinatoriallogic
•Macrossuchasip-ops,adders,subtractors,counters,FSMs,andRAMs
Macrosgreatlyimproveperformanceofthesynthesizeddesigns.Itisimportanttouse
codingtechniquestomodelthemacrossotheyareoptimallyprocessedbyXST.
XSTrsttriestorecognize(infer)asmanymacrosaspossible.Thesemacrosarethen
passedtotheLowLevelOptimizationstep.Inordertoobtainbetteroptimization
results,themacrosareeitherpreservedasseparateblocks,ormergedwithsurrounded
logic.Thislteringdependsonthetypeandsizeofamacro.Forexample,bydefault,
2-to-1multiplexersarenotpreservedbytheoptimizationengine.Synthesisconstraints
controltheprocessingofinferredmacros.
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Chapter3
XSTHDLCodingTechniques
ThischapterdiscussesXSTHDLCodingTechniques,andincludes:
•SignedandUnsignedSupportinXST
•RegistersHDLCodingTechniques
•LatchesHDLCodingTechniques
•TristatesHDLCodingTechniques
•CountersHDLCodingTechniques
•AccumulatorsHDLCodingTechniques
•ShiftRegistersHDLCodingTechniques
•DynamicShiftRegistersHDLCodingTechniques
•MultiplexersHDLCodingTechniques
•DecodersHDLCodingTechniques
•PriorityEncodersHDLCodingTechniques
•LogicalShiftersHDLCodingTechniques
•ArithmeticOperatorsHDLCodingTechniques
•Adders,Subtractors,andAdders/SubtractorsHDLCodingTechniques
•ComparatorsHDLCodingTechniques
•MultipliersHDLCodingTechniques
•SequentialComplexMultipliersHDLCodingTechniques
•PipelinedMultipliersHDLCodingTechniques
•MultiplyAdder/SubtractorsHDLCodingTechniques
•MultiplyAccumulateHDLCodingTechniques
•DividersHDLCodingTechniques
•ResourceSharingHDLCodingTechniques
•RAMsandROMsHDLCodingTechniques
•ROMsUsingBlockRAMResourcesHDLCodingTechniques
•PipelinedDistributedRAMHDLCodingTechniques
•FSMHDLCodingTechniques
•BlackBoxesHDLCodingTechniques
Formoreinformation,see:
•XSTFPGAOptimization
•XSTCPLDOptimization
ForinformationonaccessingthesynthesistemplatesfromISE®DesignSuite,seethe
ISEDesignSuiteHelp.
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Chapter3:XSTHDLCodingTechniques
SignedandUnsignedSupportinXST
WhenusingVerilogorVHDLinXST,somemacros,suchasaddersorcounters,canbe
implementedforsignedandunsignedvalues.
ToenablesupportforsignedandunsignedvaluesinVerilog,enableVerilog-2001
asfollows:
•ISE®DesignSuite
SelectVerilog2001asinstructedintheSynthesisOptionstopicofISEDesignSuite
Help
•XSTCommandLine
Set-verilog2001toyes.
ForVHDL,dependingontheoperationandtypeoftheoperands,youmustinclude
additionalpackagesinyourcode.Forexample,tocreateanunsignedadder,usethe
arithmeticpackagesandtypesthatoperateonunsignedvaluesshowninthefollowing
table.
UnsignedAdders
PACKAGETYPE
numeric_stdunsigned
std_logic_arithunsigned
std_logic_unsignedstd_logic_vector
Tocreateasignedadder,usethearithmeticpackagesandtypesthatoperateonsigned
valuesshowninthefollowingtable.
SignedAdders
PACKAGETYPE
numeric_stdsigned
std_logic_arithsigned
std_logic_signedstd_logic_vector
Formoreinformationaboutavailabletypes,seetheIEEEVHDLManual.
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Chapter3:XSTHDLCodingTechniques
RegistersHDLCodingTechniques
ThissectiondiscussesRegistersHDLCodingTechniques,andincludes:
•AboutRegisters
•RegistersLogFile
•RegistersRelatedConstraints
•RegistersCodingExamples
AboutRegisters
XSTrecognizesip-opswiththefollowingcontrolsignals:
•AsynchronousSet/Reset
•SynchronousSet/Reset
•ClockEnable
Formoreinformation,see:
SpecifyingINITandRLOC
RegistersLogFile
TheXSTloglereportsthetypeandsizeofrecognizedip-opsduringtheMacro
Recognitionstep.
WithdevicefamiliessuchastheVirtex®-4devicefamily,XSTmayoptimizedifferent
slicesofthesameregisterindifferentways.Forexample,XSTmaypushapartofa
registerintoaDSP48block,whileanotherpartmaybeimplementedonslices,oreven
becomeapartofashiftregister.XSTreportsthetotalnumberofFFbitsinthedesignin
theHDLSynthesisReportaftertheAdvancedHDLSynthesisstep.
RegistersLogFileExample
...
===============================================================
*HDLSynthesis*
===============================================================
SynthesizingUnit<registers_5>.
Relatedsourcefileis"registers_5.vhd".
Found4-bitregisterforsignal<Q>.
Summary:
inferred4D-typeflip-flop(s).
Unit<registers_5>synthesized.
===============================================================
HDLSynthesisReport
MacroStatistics
#Registers:1
4-bitregister:1
===============================================================
===============================================================
*AdvancedHDLSynthesis*
===============================================================
===============================================================
AdvancedHDLSynthesisReport
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Chapter3:XSTHDLCodingTechniques
MacroStatistics
#Registers:4
Flip-Flops/Latches:4
===============================================================
...
RegistersRelatedConstraints
•PackI/ORegistersIntoIOBs(IOB)
•RegisterDuplication(REGISTER_DUPLICATION)
•EquivalentRegisterRemoval(EQUIVALENT_REGISTER_REMOVAL)
•RegisterBalancing(REGISTER_BALANCING)
RegistersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
Flip-FlopWithPositive-EdgeClockDiagram
Flip-FlopWithPositive-EdgeClockPinDescriptions
IOPinsDescription
DDataInput
CPositive-EdgeClock
QDataOutput
Flip-FlopWithPositiveEdgeClockVHDLCodingExample
--
--Flip-FlopwithPositive-EdgeClock
--
libraryieee;
useieee.std_logic_1164.all;
entityregisters_1is
port(C,D:instd_logic;
Q:outstd_logic);
endregisters_1;
architecturearchiofregisters_1is
begin
process(C)
begin
if(C’eventandC=’1’)then
Q<=D;
endif;
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Chapter3:XSTHDLCodingTechniques
endprocess;
endarchi;
WhenusingVHDLforapositive-edgeclock,insteadofusing:
if(C’eventandC=’1’)then
youcanalsouse:
if(rising_edge(C))then
Flip-FlopWithPositive-EdgeClockVerilogCodingExample
//
//Flip-FlopwithPositive-EdgeClock
//
modulev_registers_1(C,D,Q);
inputC,D;
outputQ;
regQ;
always@(posedgeC)
begin
Q<=D;
end
endmodule
Flip-FlopWithPositiveEdgeClockwithINITSTATEoftheFlopSetVerilog
CodingExample
moduletest(d,C,q);
inputd;
inputC;
outputq;
regqtemp=’b1;
always@(posedgeC)
begin
qtemp=d;
end
assignq=qtemp;
endmodule
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Chapter3:XSTHDLCodingTechniques
Flip-FlopWithPositiveEdgeClockwithINITSTATEoftheFlopSetVHDL
CodingExample
libraryieee;
useieee.std_logic_1164.all;
entityregisters_1is
port(C,D:instd_logic;
Q:outstd_logic);
endregisters_1;
architecturearchiofregisters_1is
signalqtemp:std_logic:=’1’;
begin
process(C)
begin
if(C’eventandC=’1’)then
qtemp<=D;
endif;
Q<=Qtemp;
endprocess;
endarchi;
Flip-FlopWithNegative-EdgeClockandAsynchronousReset
Diagram
Flip-FlopWithNegative-EdgeClockandAsynchronousReset
PinDescriptions
IOPinsDescription
DDataInput
CNegative-EdgeClock
CLRAsynchronousReset(active-High)
QDataOutput
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Chapter3:XSTHDLCodingTechniques
Flip-FlopWithNegative-EdgeClockandAsynchronousResetVHDL
CodingExample
--
--Flip-FlopwithNegative-EdgeClockandAsynchronousReset
--
libraryieee;
useieee.std_logic_1164.all;
entityregisters_2is
port(C,D,CLR:instd_logic;
Q:outstd_logic);
endregisters_2;
architecturearchiofregisters_2is
begin
process(C,CLR)
begin
if(CLR=’1’)then
Q<=’0’;
elsif(C’eventandC=’0’)then
Q<=D;
endif;
endprocess;
endarchi;
Flip-FlopWithNegative-EdgeClockandAsynchronousResetVerilog
CodingExample
//
//Flip-FlopwithNegative-EdgeClockandAsynchronousReset
//
modulev_registers_2(C,D,CLR,Q);
inputC,D,CLR;
outputQ;
regQ;
always@(negedgeCorposedgeCLR)
begin
if(CLR)
Q<=1’b0;
else
Q<=D;
end
endmodule
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Flip-FlopWithPositive-EdgeClockandSynchronousSetDiagram
Flip-FlopWithPositive-EdgeClockandSynchronousSetPin
Descriptions
IOPinsDescription
DDataInput
CPositive-EdgeClock
SSynchronousSet(active-High)
QDataOutput
Flip-FlopWithPositive-EdgeClockandSynchronousSetVHDLCoding
Example
--
--Flip-FlopwithPositive-EdgeClockandSynchronousSet
--
libraryieee;
useieee.std_logic_1164.all;
entityregisters_3is
port(C,D,S:instd_logic;
Q:outstd_logic);
endregisters_3;
architecturearchiofregisters_3is
begin
process(C)
begin
if(C’eventandC=’1’)then
if(S=’1’)then
Q<=’1’;
else
Q<=D;
endif;
endif;
endprocess;
endarchi;
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Chapter3:XSTHDLCodingTechniques
Flip-FlopWithPositive-EdgeClockandSynchronousSetVerilogCoding
Example
//
//Flip-FlopwithPositive-EdgeClockandSynchronousSet
//
modulev_registers_3(C,D,S,Q);
inputC,D,S;
outputQ;
regQ;
always@(posedgeC)
begin
if(S)
Q<=1’b1;
else
Q<=D;
end
endmodule
Flip-FlopWithPositive-EdgeClockandClockEnableDiagram
Flip-FlopWithPositive-EdgeClockandClockEnablePin
Descriptions
IOPinsDescription
DDataInput
CPositive-EdgeClock
CEClockEnable(active-High)
QDataOutput
Flip-FlopWithPositive-EdgeClockandClockEnableVHDLCoding
Example
--
--Flip-FlopwithPositive-EdgeClockandClockEnable
--
libraryieee;
useieee.std_logic_1164.all;
entityregisters_4is
port(C,D,CE:instd_logic;
Q:outstd_logic);
endregisters_4;
architecturearchiofregisters_4is
begin
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Chapter3:XSTHDLCodingTechniques
process(C)
begin
if(C’eventandC=’1’)then
if(CE=’1’)then
Q<=D;
endif;
endif;
endprocess;
endarchi;
Flip-FlopWithPositive-EdgeClockandClockEnableVerilogCoding
Example
//
//Flip-FlopwithPositive-EdgeClockandClockEnable
//
modulev_registers_4(C,D,CE,Q);
inputC,D,CE;
outputQ;
regQ;
always@(posedgeC)
begin
if(CE)
Q<=D;
end
endmodule
4-BitRegisterWithPositive-EdgeClock,AsynchronousSet,and
ClockEnableDiagram
4-BitRegisterWithPositive-EdgeClock,AsynchronousSet,and
ClockEnablePinDescriptions
IOPinsDescription
DDataInput
CPositive-EdgeClock
PREAsynchronousSet(active-High)
CEClockEnable(active-High)
QDataOutput
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Chapter3:XSTHDLCodingTechniques
4-BitRegisterWithPositive-EdgeClock,AsynchronousSet,andClock
EnableVHDLCodingExample
--
--4-bitRegisterwithPositive-EdgeClock,
--AsynchronousSetandClockEnable
--
libraryieee;
useieee.std_logic_1164.all;
entityregisters_5is
port(C,CE,PRE:instd_logic;
D:instd_logic_vector(3downto0);
Q:outstd_logic_vector(3downto0));
endregisters_5;
architecturearchiofregisters_5is
begin
process(C,PRE)
begin
if(PRE=’1’)then
Q<="1111";
elsif(C’eventandC=’1’)then
if(CE=’1’)then
Q<=D;
endif;
endif;
endprocess;
endarchi;
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Chapter3:XSTHDLCodingTechniques
4-BitRegisterWithPositive-EdgeClock,AsynchronousSet,andClock
EnableVerilogCodingExample
//
//4-bitRegisterwithPositive-EdgeClock,
//AsynchronousSetandClockEnable
//
modulev_registers_5(C,D,CE,PRE,Q);
inputC,CE,PRE;
input[3:0]D;
output[3:0]Q;
reg[3:0]Q;
always@(posedgeCorposedgePRE)
begin
if(PRE)
Q<=4’b1111;
else
if(CE)
Q<=D;
end
endmodule
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Chapter3:XSTHDLCodingTechniques
LatchesHDLCodingTechniques
Thissectionincludes:
•AboutLatches
•LatchesLogFile
•LatchesRelatedConstraints
•LatchesCodingExamples
AboutLatches
XSTcanrecognizelatcheswithasynchronousset/resetcontrolsignals.Latchescan
bedescribedusing:
•Process(VHDL)
•Alwaysblock(Verilog)
•Concurrentstateassignment
XSTdoesnotsupportwaitstatements(VHDL)forlatchdescriptions.
LatchesLogFile
TheXSTloglereportsthetypeandsizeofrecognizedlatchesduringtheMacro
Recognitionstep.
LatchesLogFileExample
...
SynthesizingUnit<latch>.
Relatedsourcefileislatch_1.vhd.
WARNING:Xst:737-Found1-bitlatchforsignal<q>.
Summary:
inferred1Latch(s).
Unit<latch>synthesized.
=======================================
HDLSynthesisReport
MacroStatistics
#Latches:1
1-bitlatch:1
========================================
...
LatchesRelatedConstraints
PackI/ORegistersIntoIOBs(IOB)
LatchesCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
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Chapter3:XSTHDLCodingTechniques
LatchWithPositiveGateDiagram
LatchWithPositiveGatePinDescriptions
IOPinsDescription
DDataInput
GPositiveGate
QDataOutput
LatchWithPositiveGateVHDLCodingExample
--
--LatchwithPositiveGate
--
libraryieee;
useieee.std_logic_1164.all;
entitylatches_1is
port(G,D:instd_logic;
Q:outstd_logic);
endlatches_1;
architecturearchioflatches_1is
begin
process(G,D)
begin
if(G=’1’)then
Q<=D;
endif;
endprocess;
endarchi;
LatchWithPositiveGateVerilogCodingExample
//
//LatchwithPositiveGate
//
modulev_latches_1(G,D,Q);
inputG,D;
outputQ;
regQ;
always@(GorD)
begin
if(G)
Q=D;
end
endmodule
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LatchWithPositiveGateandAsynchronousResetDiagram
LatchWithPositiveGateandAsynchronousResetPin
Descriptions
IOPinsDescription
DDataInput
GPositiveGate
CLRAsynchronousReset(active-High)
QDataOutput
LatchWithPositiveGateandAsynchronousResetVHDLCodingExample
--
--LatchwithPositiveGateandAsynchronousReset
--
libraryieee;
useieee.std_logic_1164.all;
entitylatches_2is
port(G,D,CLR:instd_logic;
Q:outstd_logic);
endlatches_2;
architecturearchioflatches_2is
begin
process(CLR,D,G)
begin
if(CLR=’1’)then
Q<=’0’;
elsif(G=’1’)then
Q<=D;
endif;
endprocess;
endarchi;
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Chapter3:XSTHDLCodingTechniques
LatchWithPositiveGateandAsynchronousResetVerilogCodingExample
//
//LatchwithPositiveGateandAsynchronousReset
//
modulev_latches_2(G,D,CLR,Q);
inputG,D,CLR;
outputQ;
regQ;
always@(GorDorCLR)
begin
if(CLR)
Q=1’b0;
elseif(G)
Q=D;
end
endmodule
4-BitLatchWithInvertedGateandAsynchronousSetDiagram
4-BitLatchWithInvertedGateandAsynchronousSetPin
Descriptions
IOPinsDescription
DDataInput
GInvertedGate
PREAsynchronousPreset(active-High)
QDataOutput
4-BitLatchWithInvertedGateandAsynchronousSetVHDLCoding
Example
--
--4-bitLatchwithInvertedGateandAsynchronousSet
--
libraryieee;
useieee.std_logic_1164.all;
entitylatches_3is
port(D:instd_logic_vector(3downto0);
G,PRE:instd_logic;
Q:outstd_logic_vector(3downto0));
endlatches_3;
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architecturearchioflatches_3is
begin
process(PRE,G,D)
begin
if(PRE=’1’)then
Q<="1111";
elsif(G=’0’)then
Q<=D;
endif;
endprocess;
endarchi;
4-BitLatchWithInvertedGateandAsynchronousSetVerilogCoding
Example
//
//4-bitLatchwithInvertedGateandAsynchronousSet
//
modulev_latches_3(G,D,PRE,Q);
inputG,PRE;
input[3:0]D;
output[3:0]Q;
reg[3:0]Q;
always@(GorDorPRE)
begin
if(PRE)
Q=4’b1111;
elseif(~G)
Q=D;
end
endmodule
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Chapter3:XSTHDLCodingTechniques
TristatesHDLCodingTechniques
ThissectiondiscussesTristatesHDLCodingTechniques,andincludes:
•AboutTristates
•TristatesLogFile
•TristatesRelatedConstraints
•TristatesCodingExamples
AboutTristates
Tristateelementscanbedescribedusing:
•Combinatorialprocess(VHDL)
•Alwaysblock(Verilog)
•Concurrentassignment
IntheTristatesCodingExamples,comparingto0insteadof1infersaBUFTprimitive
insteadofaBUFEmacro.TheBUFEmacrohasaninverterontheEpin.
TristatesLogFile
TheXSTloglereportsthetypeandsizeofrecognizedtristatesduringtheMacro
Recognitionstep.
TristatesLogFileExample
...
SynthesizingUnit<three_st>.
Relatedsourcefileistristates_1.vhd.
Found1-bittristatebufferforsignal<o>.
Summary:
inferred1Tristate(s).
Unit<three_st>synthesized.
=============================
HDLSynthesisReport
MacroStatistics
#Tristates:1
1-bittristatebuffer:1
=============================
...
TristatesRelatedConstraints
ConvertTristatestoLogic(TRISTATE2LOGIC)
TristatesCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
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Chapter3:XSTHDLCodingTechniques
TristateDescriptionUsingCombinatorialProcessandAlways
BlockDiagram
TristateDescriptionUsingCombinatorialProcessandAlways
BlockPinDescriptions
IOPinsDescription
IDataInput
TOutputEnable(active-Low)
ODataOutput
TristateDescriptionUsingCombinatorialProcessVHDLCodingExample
--
--TristateDescriptionUsingCombinatorialProcess
--
libraryieee;
useieee.std_logic_1164.all;
entitythree_st_1is
port(T:instd_logic;
I:instd_logic;
O:outstd_logic);
endthree_st_1;
architecturearchiofthree_st_1is
begin
process(I,T)
begin
if(T=’0’)then
O<=I;
else
O<=’Z’;
endif;
endprocess;
endarchi;
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Chapter3:XSTHDLCodingTechniques
TristateDescriptionUsingCombinatorialAlwaysBlockVerilogCoding
Example
//
//TristateDescriptionUsingCombinatorialAlwaysBlock
//
modulev_three_st_1(T,I,O);
inputT,I;
outputO;
regO;
always@(TorI)
begin
if(~T)
O=I;
else
O=1’bZ;
end
endmodule
TristateDescriptionUsingConcurrentAssignmentDiagram
TristateDescriptionUsingConcurrentAssignmentPin
Descriptions
IOPinsDescription
IDataInput
TOutputEnable(active-Low)
ODataOutput
TristateDescriptionUsingConcurrentAssignmentVHDLCodingExample
--
--TristateDescriptionUsingConcurrentAssignment
--
libraryieee;
useieee.std_logic_1164.all;
entitythree_st_2is
port(T:instd_logic;
I:instd_logic;
O:outstd_logic);
endthree_st_2;
architecturearchiofthree_st_2is
begin
O<=Iwhen(T=’0’)else’Z’;
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Chapter3:XSTHDLCodingTechniques
CountersHDLCodingTechniques
ThissectiondiscussesCountersHDLCodingTechniques,andincludes:
•AboutCounters
•CountersLogFile
•CountersRelatedConstraints
•CountersCodingExamples
AboutCounters
XSTrecognizescounterswiththefollowingcontrolsignals:
•AsynchronousSet/Reset
•SynchronousSet/Reset
•Asynchronous/SynchronousLoad(signalorconstantorboth)
•ClockEnable
•Modes(Up,Down,Up/Down)
•Mixtureofalloftheabove
HardwareDescriptionLanguage(HDL)codingstylesforthefollowingcontrolsignals
areequivalenttothosedescribedinRegistersHDLCodingTechniques.
•Clock
•AsynchronousSet/Reset
•SynchronousSet/Reset
XSTsupportsbothunsignedandsignedcounters.
CountersLogFile
TheXSTloglereportsthetypeandsizeofrecognizedcountersduringtheMacro
Recognitionstep.
CountersLogFileExample
...
SynthesizingUnit<counter>.
Relatedsourcefileiscounters_1.vhd.
Found4-bitupcounterforsignal<tmp>.
Summary:
inferred1Counter(s).
Unit<counter>synthesized.
==============================
HDLSynthesisReport
MacroStatistics
#Counters:1
4-bitupcounter:1
==============================
...
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Chapter3:XSTHDLCodingTechniques
CountersRelatedConstraints
•UseDSP48(USE_DSP48)
•DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
•Keep(KEEP)
CountersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
4-BitUnsignedUpCounterWithAsynchronousResetDiagram
4-BitUnsignedUpCounterWithAsynchronousResetPin
Descriptions
IOPinsDescription
CPositive-EdgeClock
CLRAsynchronousReset(active-High)
QDataOutput
4-BitUnsignedUpCounterWithAsynchronousResetVHDLCoding
Example
--
--4-bitunsignedupcounterwithanasynchronousreset.
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounters_1is
port(C,CLR:instd_logic;
Q:outstd_logic_vector(3downto0));
endcounters_1;
architecturearchiofcounters_1is
signaltmp:std_logic_vector(3downto0);
begin
process(C,CLR)
begin
if(CLR=’1’)then
tmp<="0000";
elsif(C’eventandC=’1’)then
tmp<=tmp+1;
endif;
endprocess;
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Q<=tmp;
endarchi;
4-BitUnsignedUpCounterWithAsynchronousResetVerilogCoding
Example
//
//4-bitunsignedupcounterwithanasynchronousreset.
//
modulev_counters_1(C,CLR,Q);
inputC,CLR;
output[3:0]Q;
reg[3:0]tmp;
always@(posedgeCorposedgeCLR)
begin
if(CLR)
tmp<=4’b0000;
else
tmp<=tmp+1’b1;
end
assignQ=tmp;
endmodule
4-BitUnsignedDownCounterWithSynchronousSetDiagram
4-BitUnsignedDownCounterWithSynchronousSetPin
Descriptions
IOPinsDescription
CPositive-EdgeClock
SSynchronousSet(active-High)
QDataOutput
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4-BitUnsignedDownCounterWithSynchronousSetVHDLCoding
Example
--
--4-bitunsigneddowncounterwithasynchronousset.
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounters_2is
port(C,S:instd_logic;
Q:outstd_logic_vector(3downto0));
endcounters_2;
architecturearchiofcounters_2is
signaltmp:std_logic_vector(3downto0);
begin
process(C)
begin
if(C’eventandC=’1’)then
if(S=’1’)then
tmp<="1111";
else
tmp<=tmp-1;
endif;
endif;
endprocess;
Q<=tmp;
endarchi;
4-BitUnsignedDownCounterWithSynchronousSetVerilogCoding
Example
//
//4-bitunsigneddowncounterwithasynchronousset.
//
modulev_counters_2(C,S,Q);
inputC,S;
output[3:0]Q;
reg[3:0]tmp;
always@(posedgeC)
begin
if(S)
tmp<=4’b1111;
else
tmp<=tmp-1’b1;
end
assignQ=tmp;
endmodule
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4-BitUnsignedUpCounterWithAsynchronousLoadFrom
PrimaryInputDiagram
4-BitUnsignedUpCounterWithAsynchronousLoadFrom
PrimaryInputPinDescriptions
IOPinsDescription
CPositive-EdgeClock
ALOADAsynchronousLoad(active-High)
DDataInput
QDataOutput
4-BitUnsignedUpCounterWithAsynchronousLoadFromPrimaryInput
VHDLCodingExample
--
--4-bitUnsignedUpCounterwithAsynchronousLoad
--fromPrimaryInput
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounters_3is
port(C,ALOAD:instd_logic;
D:instd_logic_vector(3downto0);
Q:outstd_logic_vector(3downto0));
endcounters_3;
architecturearchiofcounters_3is
signaltmp:std_logic_vector(3downto0);
begin
process(C,ALOAD,D)
begin
if(ALOAD=’1’)then
tmp<=D;
elsif(C’eventandC=’1’)then
tmp<=tmp+1;
endif;
endprocess;
Q<=tmp;
endarchi;
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Chapter3:XSTHDLCodingTechniques
4-BitUnsignedUpCounterWithAsynchronousLoadFromPrimaryInput
VerilogCodingExample
//
//4-bitUnsignedUpCounterwithAsynchronousLoad
//fromPrimaryInput
//
modulev_counters_3(C,ALOAD,D,Q);
inputC,ALOAD;
input[3:0]D;
output[3:0]Q;
reg[3:0]tmp;
always@(posedgeCorposedgeALOAD)
begin
if(ALOAD)
tmp<=D;
else
tmp<=tmp+1’b1;
end
assignQ=tmp;
endmodule
4-BitUnsignedUpCounterWithSynchronousLoadWith
ConstantDiagram
4-BitUnsignedUpCounterWithSynchronousLoadWith
ConstantPinDescriptions
IOPinsDescription
CPositive-EdgeClock
SLOADSynchronousLoad(active-High)
QDataOutput
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4-BitUnsignedUpCounterWithSynchronousLoadWithConstantVHDL
CodingExample
--
--4-bitUnsignedUpCounterwithSynchronousLoad
--withaConstant
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounters_4is
port(C,SLOAD:instd_logic;
Q:outstd_logic_vector(3downto0));
endcounters_4;
architecturearchiofcounters_4is
signaltmp:std_logic_vector(3downto0);
begin
process(C)
begin
if(C’eventandC=’1’)then
if(SLOAD=’1’)then
tmp<="1010";
else
tmp<=tmp+1;
endif;
endif;
endprocess;
Q<=tmp;
endarchi;
4-BitUnsignedUpCounterWithSynchronousLoadWithConstantVerilog
CodingExample
//
//4-bitUnsignedUpCounterwithSynchronousLoad
//withaConstant
//
modulev_counters_4(C,SLOAD,Q);
inputC,SLOAD;
output[3:0]Q;
reg[3:0]tmp;
always@(posedgeC)
begin
if(SLOAD)
tmp<=4’b1010;
else
tmp<=tmp+1’b1;
end
assignQ=tmp;
endmodule
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4-BitUnsignedUpCounterWithAsynchronousResetandClock
EnableDiagram
4-BitUnsignedUpCounterWithAsynchronousResetandClock
EnablePinDescriptions
IOPinsDescription
CPositive-EdgeClock
CLRAsynchronousReset(active-High)
CEClockEnable
QDataOutput
4-BitUnsignedUpCounterWithAsynchronousResetandClockEnable
VHDLCodingExample
--
--4-bitUnsignedUpCounterwithAsynchronousReset
--andClockEnable
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounters_5is
port(C,CLR,CE:instd_logic;
Q:outstd_logic_vector(3downto0));
endcounters_5;
architecturearchiofcounters_5is
signaltmp:std_logic_vector(3downto0);
begin
process(C,CLR)
begin
if(CLR=’1’)then
tmp<="0000";
elsif(C’eventandC=’1’)then
if(CE=’1’)then
tmp<=tmp+1;
endif;
endif;
endprocess;
Q<=tmp;
endarchi;
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4-BitUnsignedUpCounterWithAsynchronousResetandClockEnable
VerilogCodingExample
//
//4-bitUnsignedUpCounterwithAsynchronousReset
//andClockEnable
//
modulev_counters_5(C,CLR,CE,Q);
inputC,CLR,CE;
output[3:0]Q;
reg[3:0]tmp;
always@(posedgeCorposedgeCLR)
begin
if(CLR)
tmp<=4’b0000;
elseif(CE)
tmp<=tmp+1’b1;
end
assignQ=tmp;
endmodule
4-BitUnsignedUp/DownCounterWithAsynchronousReset
Diagram
4-BitUnsignedUp/DownCounterWithAsynchronousResetPin
Descriptions
IOPinsDescription
CPositive-EdgeClock
CLRAsynchronousReset(active-High)
UP_DOWNUp/DownCountModeSelector
QDataOutput
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4-BitUnsignedUp/DownCounterWithAsynchronousResetVHDLCoding
Example
--
--4-bitUnsignedUp/Downcounter
--withAsynchronousReset
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounters_6is
port(C,CLR,UP_DOWN:instd_logic;
Q:outstd_logic_vector(3downto0));
endcounters_6;
architecturearchiofcounters_6is
signaltmp:std_logic_vector(3downto0);
begin
process(C,CLR)
begin
if(CLR=’1’)then
tmp<="0000";
elsif(C’eventandC=’1’)then
if(UP_DOWN=’1’)then
tmp<=tmp+1;
else
tmp<=tmp-1;
endif;
endif;
endprocess;
Q<=tmp;
endarchi;
4-BitUnsignedUp/DownCounterWithAsynchronousResetVerilog
CodingExample
//
//4-bitUnsignedUp/Downcounter
//withAsynchronousReset
//
modulev_counters_6(C,CLR,UP_DOWN,Q);
inputC,CLR,UP_DOWN;
output[3:0]Q;
reg[3:0]tmp;
always@(posedgeCorposedgeCLR)
begin
if(CLR)
tmp<=4’b0000;
elseif(UP_DOWN)
tmp<=tmp+1’b1;
else
tmp<=tmp-1’b1;
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end
assignQ=tmp;
endmodule
4-BitSignedUpCounterWithAsynchronousResetDiagram
4-BitSignedUpCounterWithAsynchronousResetPin
Descriptions
IOPinsDescription
CPositive-EdgeClock
CLRAsynchronousReset(active-High)
QDataOutput
4-BitSignedUpCounterWithAsynchronousResetVHDLCodingExample
--
--4-bitSignedUpCounterwithAsynchronousReset
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
entitycounters_7is
port(C,CLR:instd_logic;
Q:outstd_logic_vector(3downto0));
endcounters_7;
architecturearchiofcounters_7is
signaltmp:std_logic_vector(3downto0);
begin
process(C,CLR)
begin
if(CLR=’1’)then
tmp<="0000";
elsif(C’eventandC=’1’)then
tmp<=tmp+1;
endif;
endprocess;
Q<=tmp;
endarchi;
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Chapter3:XSTHDLCodingTechniques
4-BitSignedUpCounterWithAsynchronousResetVerilogCoding
Example
//
//4-bitSignedUpCounterwithAsynchronousReset
//
modulev_counters_7(C,CLR,Q);
inputC,CLR;
outputsigned[3:0]Q;
regsigned[3:0]tmp;
always@(posedgeCorposedgeCLR)
begin
if(CLR)
tmp<=4’b0000;
else
tmp<=tmp+1’b1;
end
assignQ=tmp;
endmodule
4-BitSignedUpCounterWithAsynchronousResetandModulo
MaximumDiagram
4-BitSignedUpCounterWithAsynchronousResetandModulo
MaximumPinDescriptions
IOPinsDescription
CPositive-EdgeClock
CLRAsynchronousReset(active-High)
QDataOutput
4-BitSignedUpCounterWithAsynchronousResetandModuloMaximum
VHDLCodingExample
--
--4-bitSignedUpCounterwithAsynchronousReset
--andModuloMaximum
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
entitycounters_8is
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generic(MAX:integer:=16);
port(C,CLR:instd_logic;
Q:outintegerrange0toMAX-1);
endcounters_8;
architecturearchiofcounters_8is
signalcnt:integerrange0toMAX-1;
begin
process(C,CLR)
begin
if(CLR=’1’)then
cnt<=0;
elsif(rising_edge(C))then
cnt<=(cnt+1)modMAX;
endif;
endprocess;
Q<=cnt;
endarchi;
4-BitSignedUpCounterWithAsynchronousResetandModuloMaximum
VerilogCodingExample
//
//4-bitSignedUpCounterwithAsynchronousReset
//andModuloMaximum
//
modulev_counters_8(C,CLR,Q);
parameter
MAX_SQRT=4,
MAX=(MAX_SQRT*MAX_SQRT);
inputC,CLR;
output[MAX_SQRT-1:0]Q;
reg[MAX_SQRT-1:0]cnt;
always@(posedgeCorposedgeCLR)
begin
if(CLR)
cnt<=0;
else
cnt<=(cnt+1)%MAX;
end
assignQ=cnt;
endmodule
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Chapter3:XSTHDLCodingTechniques
AccumulatorsHDLCodingTechniques
ThissectiondiscussesAccumulatorsHDLCodingTechniques,andincludes:
•AboutAccumulators
•AccumulatorsinVirtex®-4DevicesandVirtex-5Device
•AccumulatorsLogFile
•AccumulatorsRelatedConstraints
•AccumulatorsCodingExamples
AboutAccumulators
Anaccumulatordiffersfromacounterinthenatureoftheoperandsoftheaddand
subtractoperation.
•Inacounter:
–Thedestinationandrstoperandisasignalorvariable
–Thesecondoperandisaconstantequalto1:
A<=A+1
•Inanaccumulator:
–Thedestinationandrstoperandisasignalorvariable
–Thesecondoperandiseither:
♦Asignalorvariable:
A<=A+B
♦Aconstantnotequalto1:
A<=A+Constant
Aninferredaccumulatorcanbeup,down,orupdown.Foranupdownaccumulator,
theaccumulateddatamaydifferbetweentheupanddownmode:
...
ifupdown=’1’then
a<=a+b;
else
a<=a-c;
...
XSTcaninferanaccumulatorwiththesamesetofcontrolsignalsavailableforcounters.
Formoreinformation,see:
CountersHDLCodingTechniques
AccumulatorsinVirtex-4DevicesandVirtex-5Devices
ThissectiondiscussesAccumulatorsinVirtex®-4DevicesandVirtex-5Devices,and
includes:
•AboutAccumulatorsinVirtex-4DevicesandVirtex-5Devices
•MacroImplementationonDSP48Resources
•MaximumMacroConguration
•ReportingofInferredAccumulators
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Chapter3:XSTHDLCodingTechniques
AboutAccumulatorsinVirtex-4DevicesandVirtex-5Devices
Virtex-4devicesandVirtex-5devicesenableaccumulatorstobeimplementedonDSP48
resources.XSTcanpushuptotwolevelsofinputregistersintoDSP48blocks.
XSTcanimplementanaccumulatorinaDSP48blockifitsimplementationrequiresonly
asingleDSP48resource.IfanaccumulatormacrodoesnottinasingleDSP48,XST
implementstheentiremacrousingslicelogic.
MacroImplementationonDSP48Resources
MacroimplementationonDSP48resourcesiscontrolledbyUseDSP48(USE_DSP48),
withadefaultvalueofauto.Inautomode,XSTimplementsaccumulatorstakinginto
accountDSP48resourcesonthedevice.
UseDSPUtilizationRatio(DSP_UTILIZATION_RATIO)inautomodetocontrolDSP48
resourcesforsynthesis.Bydefault,XSTtriestoutilizeallDSP48resources.
Formoreinformation,see:
DSP48BlockResources
MaximumMacroConfiguration
Todeliverthebestperformance,XSTbydefaulttriestoinferandimplementthe
maximummacroconguration,includingasmanyregistersaspossibleintheDSP48.
UseKeep(KEEP)toshapeamacroinaspecicway.Forexample,toexcludetherst
registerstagefromtheDSP48,placeKeep(KEEP)constraintsontheoutputsofthese
registers.
ReportingofInferredAccumulators
XSTreportsthedetailsofinferredaccumulatorsattheHDLSynthesisstep.Because
accumulatorsareimplementedwithintheMACimplementationmechanism,theyare
nolongervisibleintheFinalSynthesisReport.
AccumulatorsLogFile
TheXSTloglereportsthetypeandsizeofrecognizedaccumulatorsduringtheMacro
Recognitionstep.
AccumulatorsLogFileExample
...
SynthesizingUnit<accum>.
Relatedsourcefileisaccumulators_1.vhd.
Found4-bitupaccumulatorforsignal<tmp>.
Summary:
inferred1Accumulator(s).
Unit<accum>synthesized.
==============================
HDLSynthesisReport
MacroStatistics
#Accumulators:1
4-bitupaccumulator:1
==============================
...
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Chapter3:XSTHDLCodingTechniques
AccumulatorsRelatedConstraints
•UseDSP48(USE_DSP48)
•DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
•Keep(KEEP)
AccumulatorsCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
4-BitUnsignedUpAccumulatorWithAsynchronousReset
Diagram
4-BitUnsignedUpAccumulatorWithAsynchronousResetPin
Descriptions
IOPinsDescription
CPositive-EdgeClock
CLRAsynchronousReset(active-High)
DDataInput
QDataOutput
4-BitUnsignedUpAccumulatorWithAsynchronousResetVHDLCoding
Example
--
--4-bitUnsignedUpAccumulatorwithAsynchronousReset
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityaccumulators_1is
port(C,CLR:instd_logic;
D:instd_logic_vector(3downto0);
Q:outstd_logic_vector(3downto0));
endaccumulators_1;
architecturearchiofaccumulators_1is
signaltmp:std_logic_vector(3downto0);
begin
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process(C,CLR)
begin
if(CLR=’1’)then
tmp<="0000";
elsif(C’eventandC=’1’)then
tmp<=tmp+D;
endif;
endprocess;
Q<=tmp;
endarchi;
4-BitUnsignedUpAccumulatorWithAsynchronousResetVerilogCoding
Example
//
//4-bitUnsignedUpAccumulatorwithAsynchronousReset
//
modulev_accumulators_1(C,CLR,D,Q);
inputC,CLR;
input[3:0]D;
output[3:0]Q;
reg[3:0]tmp;
always@(posedgeCorposedgeCLR)
begin
if(CLR)
tmp=4’b0000;
else
tmp=tmp+D;
end
assignQ=tmp;
endmodule
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Chapter3:XSTHDLCodingTechniques
ShiftRegistersHDLCodingTechniques
ThissectiondiscussesShiftRegistersHDLCodingTechniques,andincludes:
•AboutShiftRegisters
•ShiftRegistersLogFile
•ShiftRegistersRelatedConstraints
•ShiftRegistersCodingExamples
AboutShiftRegisters
ThissectiondiscussesAboutShiftRegisters,andincludes:
•ShiftRegisterDenition
•StaticShiftRegisterComponents
•AdditionalFunctionality
•DescribingShiftRegisters
•ImplementingShiftRegisters
ShiftRegisterDefinition
Ashiftregisterisachainofip-opsallowingpropagationofdataacrossaxed(static)
numberoflatencystages.InDynamicShiftRegistersHDLCodingTechniques,the
lengthofthepropagationchaindynamicallyvariesduringcircuitoperation.
StaticShiftRegisterComponents
Astaticshiftregisterusuallyinvolves:
•Aclock
•Anoptionalclockenable
•Aserialdatainput
•Aserialdataoutput
AdditionalFunctionality
Youcanincludeadditionalfunctionality,suchasreset,set,orparallelloadlogic.
Inthiscasehowever,XSTmaynotalwaysbeabletotakeadvantageofdedicated
SRL-typeprimitivesforreduceddeviceutilizationandoptimizedperformance.Xilinx®
recommendsremovingsuchlogic,andloadingthedesiredcontentsseriallyinstead.
DescribingShiftRegisters
WaystodescribeshiftregistersinVHDLinclude:
•Concatenationoperator
shreg<=shreg(6downto0)&SI;
•Forloopconstruct
foriin0to6loop
shreg(i+1)<=shreg(i);
endloop;
shreg(0)<=SI;
•Predenedshiftoperators(forexample,SLLorSRL)
Formoreinformation,seeyourVHDLandVeriloglanguagereferencemanuals.
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Chapter3:XSTHDLCodingTechniques
ImplementingShiftRegisters
InferredshiftregistersareimplementedonSRL-typeresources.Theresourcesshownin
thefollowingtableareleveraged.
DevicesSRL16SRL16ESRLC16SRLC16ESRLC32E
Spartan®-3
Spartan-3E
Spartan-3A
YesYesYesYesNo
Virtex®-4YesYesYesYesNo
Virtex-5YesYesYesYesYes
ShiftRegistersLogFile
XSTrecognizesshiftregistersintheLowLevelOptimizationstep.TheXSTlogle
reportsthesizeofrecognizedshiftregisters.
ShiftRegistersLogFileExample
...
=============================================
*HDLSynthesis*
=============================================
SynthesizingUnit<shift_registers_1>.
Relatedsourcefileis"shift_registers_1.vhd".
Found8-bitregisterforsignal<tmp>.
Summary:
inferred8D-typeflip-flop(s).
Unit<shift_registers_1>synthesized.
=============================================
*AdvancedHDLSynthesis*
=============================================
AdvancedHDLSynthesisReport
MacroStatistics
#Registers:8
Flip-Flops:8
=============================================
=============================================
*LowLevelSynthesis*
=============================================
ProcessingUnit<shift_registers_1>:
Found8-bitshiftregisterforsignal<tmp_7>.
Unit<shift_registers_1>processed.
=============================================
FinalRegisterReport
MacroStatistics
#ShiftRegisters:1
8-bitshiftregister:1
=============================================
ShiftRegistersRelatedConstraints
ShiftRegisterExtraction(SHREG_EXTRACT)
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Chapter3:XSTHDLCodingTechniques
ShiftRegistersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
8-BitShift-LeftRegisterWithPositive-EdgeClock,SerialInand
SerialOutDiagram
8-BitShift-LeftRegisterWithPositive-EdgeClock,SerialInand
SerialOutPinDescriptions
IOPinsDescription
CPositive-EdgeClock
SISerialIn
SOSerialOutput
8-BitShift-LeftRegisterWithPositive-EdgeClock,SerialInandSerial
OutVHDLCodingExample
--
--8-bitShift-LeftRegisterwithPositive-EdgeClock,
--SerialIn,andSerialOut
--
libraryieee;
useieee.std_logic_1164.all;
entityshift_registers_1is
port(C,SI:instd_logic;
SO:outstd_logic);
endshift_registers_1;
architecturearchiofshift_registers_1is
signaltmp:std_logic_vector(7downto0);
begin
process(C)
begin
if(C’eventandC=’1’)then
foriin0to6loop
tmp(i+1)<=tmp(i);
endloop;
tmp(0)<=SI;
endif;
endprocess;
SO<=tmp(7);
endarchi;
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Chapter3:XSTHDLCodingTechniques
8-BitShift-LeftRegisterWithPositive-EdgeClock,SerialInandSerial
OutVerilogCodingExample
//
//8-bitShift-LeftRegisterwithPositive-EdgeClock,
//SerialIn,andSerialOut
//
modulev_shift_registers_1(C,SI,SO);
inputC,SI;
outputSO;
reg[7:0]tmp;
always@(posedgeC)
begin
tmp={tmp[6:0],SI};
end
assignSO=tmp[7];
endmodule
8-BitShift-LeftRegisterWithNegative-EdgeClock,ClockEnable,
SerialInandSerialOutDiagram
8-BitShift-LeftRegisterWithNegative-EdgeClock,ClockEnable,
SerialInandSerialOutPinDescriptions
IOPinsDescription
CNegative-EdgeClock
SISerialIn
CEClockEnable(active-High)
SOSerialOutput
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8-BitShift-LeftRegisterWithNegative-EdgeClock,ClockEnable,SerialIn
andSerialOutVHDLCodingExample
--
--8-bitShift-LeftRegisterwithNegative-EdgeClock,
--ClockEnable,SerialIn,andSerialOut
--
libraryieee;
useieee.std_logic_1164.all;
entityshift_registers_2is
port(C,SI,CE:instd_logic;
SO:outstd_logic);
endshift_registers_2;
architecturearchiofshift_registers_2is
signaltmp:std_logic_vector(7downto0);
begin
process(C)
begin
if(C’eventandC=’0’)then
if(CE=’1’)then
foriin0to6loop
tmp(i+1)<=tmp(i);
endloop;
tmp(0)<=SI;
endif;
endif;
endprocess;
SO<=tmp(7);
endarchi;
Frontmatter
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Chapter3:XSTHDLCodingTechniques
8-BitShift-LeftRegisterWithNegative-EdgeClock,ClockEnable,SerialIn
andSerialOutVerilogCodingExample
//
//8-bitShift-LeftRegisterwithNegative-EdgeClock,
//ClockEnable,SerialIn,andSerialOut
//
modulev_shift_registers_2(C,CE,SI,SO);
inputC,SI,CE;
outputSO;
reg[7:0]tmp;
always@(negedgeC)
begin
if(CE)
begin
tmp={tmp[6:0],SI};
end
end
assignSO=tmp[7];
endmodule
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Chapter3:XSTHDLCodingTechniques
DynamicShiftRegistersHDLCodingTechniques
ThissectiondiscussesDynamicShiftRegistersHDLCodingTechniques,andincludes:
•AboutDynamicShiftRegisters
•DynamicShiftRegistersLogFile
•DynamicShiftRegistersRelatedConstraints
•DynamicShiftRegistersCodingExamples
AboutDynamicShiftRegisters
XSTcaninferDynamicShiftRegisters.OnceaDynamicShiftRegisterhasbeen
identied,itscharacteristicsarehandedtotheXSTmacrogeneratorforoptimal
implementationusingtheprimitivesshowninthefollowingtable.
DevicesSRL16SRL16ESRLC16SRLC16ESRLC32E
Spartan®-3
Spartan-3E
Spartan-3A
YesYesYesYesNo
Virtex®-4YesYesYesYesNo
Virtex-5YesYesYesYesYes
DynamicShiftRegistersLogFile
DynamicshiftregistersarerecognizedintheAdvancedHDLSynthesisstep.The
XSTloglereportsthesizeofrecognizeddynamicshiftregistersduringtheMacro
Recognitionstep.
DynamicShiftRegistersLogFileExample
...
=============================================
*HDLSynthesis*
=============================================
SynthesizingUnit<dynamic_shift_registers_1>.
Relatedsourcefileis"dynamic_shift_registers_1.vhd".
Found1-bit16-to-1multiplexerforsignal<Q>.
Found16-bitregisterforsignal<SRL_SIG>.
Summary:
inferred16D-typeflip-flop(s).
inferred1Multiplexer(s).
Unit<dynamic_shift_registers_1>synthesized.
=============================================
*AdvancedHDLSynthesis*
=============================================
...
Synthesizing(advanced)Unit<dynamic_shift_registers_1>.
Found16-bitdynamicshiftregisterforsignal<Q>.
Unit<dynamic_shift_registers_1>synthesized(advanced).
=============================================
HDLSynthesisReport
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Chapter3:XSTHDLCodingTechniques
MacroStatistics
#ShiftRegisters:1
16-bitdynamicshiftregister:1
=============================================
...
DynamicShiftRegistersRelatedConstraints
ShiftRegisterExtraction(SHREG_EXTRACT)
DynamicShiftRegistersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
16-BitDynamicShiftRegisterWithPositive-EdgeClock,SerialIn
andSerialOutDiagram
Thefollowingtableshowspindescriptionsforadynamicregister.Theregistercan:
•Beeitherserialorparallel
•Beleftorright
•Haveasynchronousorasynchronousreset
•Haveadepthupto16bits.
16-BitDynamicShiftRegisterWithPositive-EdgeClock,SerialIn
andSerialOutPinDescriptions
IOPinsDescription
CPositive-EdgeClock
SISerialIn
AClrAsynchronousReset
SClrSynchronousReset
SLoadSynchronousParallelLoad
DataParallelDataInputPort
ClkEnClockEnable
LeftRightDirectionselection
SerialInRightSerialInputRightforBidirectionalShift
Register
PSOSerialorParallelOutput
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Chapter3:XSTHDLCodingTechniques
16-BitDynamicShiftRegisterWithPositive-EdgeClock,SerialInand
SerialOutVHDLCodingExample
--
--16-bitdynamicshiftregister.
--
libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.std_logic_unsigned.all;
entitydynamic_shift_registers_1is
port(CLK:instd_logic;
DATA:instd_logic;
CE:instd_logic;
A:instd_logic_vector(3downto0);
Q:outstd_logic);
enddynamic_shift_registers_1;
architecturertlofdynamic_shift_registers_1is
constantDEPTH_WIDTH:integer:=16;
typeSRL_ARRAYisarray(0toDEPTH_WIDTH-1)ofstd_logic;
--ThetypeSRL_ARRAYcanbearray
--(0toDEPTH_WIDTH-1)of
--std_logic_vector(BUS_WIDTHdownto0)
--orarray(DEPTH_WIDTH-1downto0)of
--std_logic_vector(BUS_WIDTHdownto0)
--(thesubtypeisforward(seebelow))
signalSRL_SIG:SRL_ARRAY;
begin
PROC_SRL16:process(CLK)
begin
if(CLK’eventandCLK=’1’)then
if(CE=’1’)then
SRL_SIG<=DATA&SRL_SIG(0toDEPTH_WIDTH-2);
endif;
endif;
endprocess;
Q<=SRL_SIG(conv_integer(A));
endrtl;
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Chapter3:XSTHDLCodingTechniques
16-BitDynamicShiftRegisterWithPositive-EdgeClock,SerialInand
SerialOutVerilogCodingExample
//
//16-bitdynamicshiftregister.
//
modulev_dynamic_shift_registers_1(Q,CE,CLK,D,A);
inputCLK,D,CE;
input[3:0]A;
outputQ;
reg[15:0]data;
assignQ=data[A];
always@(posedgeCLK)
begin
if(CE==1’b1)
data<={data[14:0],D};
end
endmodule
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Chapter3:XSTHDLCodingTechniques
MultiplexersHDLCodingTechniques
ThissectiondiscussesMultiplexersHDLCodingTechniques,andincludes:
•AboutMultiplexers
•MultiplexersLogFile
•MultiplexersRelatedConstraints
•MultiplexersCodingExamples
AboutMultiplexers
ThissectiondiscussesAboutMultiplexers,andincludes:
•MultiplexersDescriptionStyles
•VerilogCaseStatements
•VerilogCaseStatementResources
•CaseImplementationStyleParameter
•MultiplexersCaseStatements
MultiplexersDescriptionStyles
XSTsupportsdifferentdescriptionstylesformultiplexers(MUX),suchas:
•if-then-else
•case
IfyoudescribeaMUXusingacasestatement,andyoudonotspecifyallvaluesofthe
selector,theresultmaybelatchesinsteadofamultiplexer.WhenwritingaMUX,you
canusedontcaretodescribeselectorvalues.
XSTdecideswhethertoinfertheMUXduringtheMacroInferencestep.IftheMUXhas
severalinputsthatarethesame,XSTcandecidenottoinferit.UseMUX_EXTRACT
toforceXSTtoinfertheMUX.
VerilogCaseStatements
Verilogcasestatementscanbe:
•fullornotfull
•parallelornotparallel
AVerilogcasestatementis:
•fullifallpossiblebranchesarespecied
•parallelifitdoesnotcontainbranchesthatcanbeexecutedsimultaneously
VerilogCaseStatementResources
VerilogCaseStatementResourcesindicatestheresourcesusedtosynthesizethe
MultiplexersCaseStatementExamplesusingthefourCaseImplementationStyles.
Thetermresourcesmeansthefunctionality.
Forexample,ifyoucodethecasestatementneitherfullnorparallelwithCase
ImplementationStylesettonone,fromthefunctionalitypointofview,XSTimplements
apriorityencoder+latch.ButitdoesnotinevitablymeanthatXSTinfersthepriority
encoderduringtheMacroRecognitionstep.
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Chapter3:XSTHDLCodingTechniques
Parameter
ValueCaseImplementation
FullNotFullNeitherFullnorParallel
noneMUXLatchPriorityEncoder+Latch
parallelMUXLatchLatch
fullMUXMUXPriorityEncoder
full-parallelMUXMUXMUX
Specifyingfull,parallelorfull-parallelmayresultinanimplementationwitha
behaviorthatmaydifferfromthebehavioroftheinitialmodel.
CaseImplementationStyleParameter
ThischaracterizationofthecasestatementscanbeguidedormodiedbyusingCase
ImplementationStyle.Acceptedvaluesforthisparameterare:
•none
•full
•parallel
•full-parallel
ValueXSTBehavior
none
(default)Implementstheexactbehaviorofthecasestatements
fullConsidersthatcasestatementsarecompleteandavoidslatchcreation
parallelConsidersthatthebranchescannotoccurinparallelanddoesnotuseapriority
encoder
full-parallelConsidersthatcasestatementsarecompleteandthatthebranchescannotoccur
inparallel,thereforesavinglatchesandpriorityencoders
Formoreinformation,see:
XSTDesignConstraints
MultiplexersCaseStatements
FollowingarethreeexamplesofCasestatements:
•FullandParallelCaseStatement
•NotFullButParallelCaseStatement
•NeitherFullNorParallelCaseStatement
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Chapter3:XSTHDLCodingTechniques
FullandParallelCaseStatement
modulefull(sel,i1,i2,i3,i4,o1);
input[1:0]sel;
input[1:0]i1,i2,i3,i4;
output[1:0]o1;
reg[1:0]o1;
always@(selori1ori2ori3ori4)
begin
case(sel)
2’b00:o1=i1;
2’b01:o1=i2;
2’b10:o1=i3;
2’b11:o1=i4;
endcase
end
endmodule
NotFullButParallelCaseStatement
modulenotfull(sel,i1,i2,i3,o1);
input[1:0]sel;
input[1:0]i1,i2,i3;
output[1:0]o1;
reg[1:0]o1;
always@(selori1ori2ori3)
begin
case(sel)
2’b00:o1=i1;
2’b01:o1=i2;
2’b10:o1=i3;
endcase
end
endmodule
NeitherFullNorParallelCaseStatement
modulenotfull_notparallel(sel1,sel2,i1,i2,o1);
input[1:0]sel1,sel2;
input[1:0]i1,i2;
output[1:0]o1;
reg[1:0]o1;
always@(sel1orsel2)
begin
case(2’b00)
sel1:o1=i1;
sel2:o1=i2;
endcase
end
endmodule
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Chapter3:XSTHDLCodingTechniques
XSTautomaticallydeterminesthecharacteristicsofthecasestatementsandgenerates
logicusingmultiplexers,priorityencoders,andlatchesthatbestimplementtheexact
behaviorofthecasestatement.
MultiplexersLogFile
TheXSTloglereportsthetypeandsizeofrecognizedmultiplexers(MUX)duringthe
MacroRecognitionstep.
MultiplexersLogFileExample
...
SynthesizingUnit<mux>.
Relatedsourcefileismultiplexers_1.vhd.
Found1-bit4-to-1multiplexerforsignal<o>.
Summary:
inferred1Multiplexer(s).
Unit<mux>synthesized.
=============================
HDLSynthesisReport
MacroStatistics
#Multiplexers:1
1-bit4-to-1multiplexer:1
==============================
...
Explicitinferenceandreportingofmultiplexersmayvarydependingonthetargeted
devicefamilies.Thefollowingcodingexamplesarelimitedto4-to-1multiplexers.They
arereportedasshownaboveonlyifthetargetisaLUT4-baseddevicefamily .For
Virtex®-5devices,multiplexersareexplicitlyinferredonlyforsizesof8-to-1andabove.
MultiplexersRelatedConstraints
•MuxExtraction(MUX_EXTRACT)
•MuxStyle(MUX_STYLE)
•EnumeratedEncoding(ENUM_ENCODING)
MultiplexersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
4-to-11-BitMUXUsingIFStatementDiagram
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Chapter3:XSTHDLCodingTechniques
4-to-11-BitMUXUsingIFStatementPinDescriptions
IOPinsDescription
a,b,c,dDataInputs
sMUXSelector
oDataOutput
4-to-11-BitMUXUsingIFStatementVHDLCodingExample
--
--4-to-11-bitMUXusinganIfstatement.
--
libraryieee;
useieee.std_logic_1164.all;
entitymultiplexers_1is
port(a,b,c,d:instd_logic;
s:instd_logic_vector(1downto0);
o:outstd_logic);
endmultiplexers_1;
architecturearchiofmultiplexers_1is
begin
process(a,b,c,d,s)
begin
if(s="00")theno<=a;
elsif(s="01")theno<=b;
elsif(s="10")theno<=c;
elseo<=d;
endif;
endprocess;
endarchi;
4-to-11-BitMUXUsingIFStatementVerilogCodingExample
//
//4-to-11-bitMUXusinganIfstatement.
//
modulev_multiplexers_1(a,b,c,d,s,o);
inputa,b,c,d;
input[1:0]s;
outputo;
rego;
always@(aorborcordors)
begin
if(s==2’b00)o=a;
elseif(s==2’b01)o=b;
elseif(s==2’b10)o=c;
elseo=d;
end
endmodule
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Chapter3:XSTHDLCodingTechniques
4-to-11-BitMUXUsingCaseStatementDiagram
4-to-11-BitMUXUsingCaseStatementPinDescriptions
IOPinsDescription
a,b,c,dDataInputs
sMUXSelector
oDataOutput
4-to-11-BitMUXUsingCaseStatementVHDLCodingExample
--
--4-to-11-bitMUXusingaCasestatement.
--
libraryieee;
useieee.std_logic_1164.all;
entitymultiplexers_2is
port(a,b,c,d:instd_logic;
s:instd_logic_vector(1downto0);
o:outstd_logic);
endmultiplexers_2;
architecturearchiofmultiplexers_2is
begin
process(a,b,c,d,s)
begin
casesis
when"00"=>o<=a;
when"01"=>o<=b;
when"10"=>o<=c;
whenothers=>o<=d;
endcase;
endprocess;
endarchi;
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Chapter3:XSTHDLCodingTechniques
4-to-11-BitMUXUsingCaseStatementVerilogCodingExample
//
//4-to-11-bitMUXusingaCasestatement.
//
modulev_multiplexers_2(a,b,c,d,s,o);
inputa,b,c,d;
input[1:0]s;
outputo;
rego;
always@(aorborcordors)
begin
case(s)
2’b00:o=a;
2’b01:o=b;
2’b10:o=c;
default:o=d;
endcase
end
endmodule
4-to-11-BitMUXUsingTristateBuffersDiagram
4-to-11-BitMUXUsingTristateBuffersPinDescriptions
IOPinsDescription
a,b,c,dDataInputs
sMUXSelector
oDataOutput
4-to-11-BitMUXUsingTristateBuffersVHDLCodingExample
--
--4-to-11-bitMUXusingtristatebuffers.
--
libraryieee;
useieee.std_logic_1164.all;
entitymultiplexers_3is
port(a,b,c,d:instd_logic;
s:instd_logic_vector(3downto0);
o:outstd_logic);
endmultiplexers_3;
architecturearchiofmultiplexers_3is
begin
o<=awhen(s(0)=’0’)else’Z’;
o<=bwhen(s(1)=’0’)else’Z’;
o<=cwhen(s(2)=’0’)else’Z’;
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Chapter3:XSTHDLCodingTechniques
o<=dwhen(s(3)=’0’)else’Z’;
endarchi;
4-to-11-BitMUXUsingTristateBuffersVerilogCodingExample
//
//4-to-11-bitMUXusingtristatebuffers.
//
modulev_multiplexers_3(a,b,c,d,s,o);
inputa,b,c,d;
input[3:0]s;
outputo;
assigno=s[3]?a:1’bz;
assigno=s[2]?b:1’bz;
assigno=s[1]?c:1’bz;
assigno=s[0]?d:1’bz;
endmodule
VHDLCodingExampleofaMissingElseStatementLeadingtoaLatch
Inference
ThefollowingcodingexamplesillustratehowXSTinfersalatchwhennoelsestatement
isdescribedattheendofanif/elsifconstruct.Sincetheelsestatementismissing,XST
assumesthat,forthes=11case,oretainsitsoldvalue,andthatamemoryelementis
needed.XSTissuesthefollowingwarningmessage.
WARNING:Xst:737-Found1-bitlatchforsignal<o1>.INFO:Xst
-HDLADVISOR-Logicfunctionsrespectivelydrivingthedata
andgateenableinputsofthislatchsharecommonterms.This
situationwillpotentiallyleadtosetup/holdviolationsand,
asaresult,tosimulationproblems.Thissituationmaycome
fromanincompletecasestatement(allselectorvaluesare
notcovered).Youshouldcarefullyreviewifitwasinyour
intentionstodescribesuchalatch.
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Chapter3:XSTHDLCodingTechniques
Unlessyouactuallyintendedtodescribesuchalatch,addthemissingelsestatement.
Caution!Leavingoutanelsestatementmayresultinerrorsduringsimulation.
--
--3-to-11-bitMUXwitha1-bitlatch.
--
libraryieee;
useieee.std_logic_1164.all;
entitymultiplexers_4is
port(a,b,c:instd_logic;
s:instd_logic_vector(1downto0);
o:outstd_logic);
endmultiplexers_4;
architecturearchiofmultiplexers_4is
begin
process(a,b,c,s)
begin
if(s="00")theno<=a;
elsif(s="01")theno<=b;
elsif(s="10")theno<=c;
endif;
endprocess;
endarchi;
VerilogCodingExampleofaMissingElseStatementLeadingtoaLatch
Inference
//
//3-to-11-bitMUXwitha1-bitlatch.
//
modulev_multiplexers_4(a,b,c,s,o);
inputa,b,c;
input[1:0]s;
outputo;
rego;
always@(aorborcors)
begin
if(s==2’b00)o=a;
elseif(s==2’b01)o=b;
elseif(s==2’b10)o=c;
end
endmodule
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Chapter3:XSTHDLCodingTechniques
DecodersHDLCodingTechniques
Thissectionincludes:
•AboutDecoders
•DecodersLogFile
•DecodersRelatedConstraints
•DecodersCodingExamples
AboutDecoders
Adecoderisamultiplexertheinputsofwhichareallconstantwithdistinctone-hot(or
one-cold)codedvalues.
Formoreinformation,see:
MultiplexersHDLCodingTechniques
DecodersLogFile
TheXSTloglereportsthetypeandsizeofrecognizeddecodersduringtheMacro
Recognitionstep.
DecodersLogFileExample
SynthesizingUnit<dec>.
Relatedsourcefileisdecoders_1.vhd.
Found1-of-8decoderforsignal<res>.
Summary:
inferred1Decoder(s).
Unit<dec>synthesized.
==============================
HDLSynthesisReport
MacroStatistics
#Decoders:1
1-of-8decoder:1
==============================
...
DecodersRelatedConstraints
DecoderExtraction(DECODER_EXTRACT)
DecodersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
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Chapter3:XSTHDLCodingTechniques
1-of-8Decoder(One-Hot)Diagram
1-of-8Decoders(One-Hot)PinDescriptions
IOPinsDescription
sSelector
resDataOutput
1-of-8Decoder(One-Hot)VHDLCodingExample
--
--1-of-8decoder(One-Hot)
--
libraryieee;
useieee.std_logic_1164.all;
entitydecoders_1is
port(sel:instd_logic_vector(2downto0);
res:outstd_logic_vector(7downto0));
enddecoders_1;
architecturearchiofdecoders_1is
begin
res<="00000001"whensel="000"else
"00000010"whensel="001"else
"00000100"whensel="010"else
"00001000"whensel="011"else
"00010000"whensel="100"else
"00100000"whensel="101"else
"01000000"whensel="110"else
"10000000";
endarchi;
1-of-8decoder(One-Hot)VerilogCodingExample
//
//1-of-8decoder(One-Hot)
//
modulev_decoders_1(sel,res);
input[2:0]sel;
output[7:0]res;
reg[7:0]res;
always@(selorres)
begin
case(sel)
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Chapter3:XSTHDLCodingTechniques
3’b000:res=8’b00000001;
3’b001:res=8’b00000010;
3’b010:res=8’b00000100;
3’b011:res=8’b00001000;
3’b100:res=8’b00010000;
3’b101:res=8’b00100000;
3’b110:res=8’b01000000;
default:res=8’b10000000;
endcase
end
endmodule
1-of-8Decoder(One-Cold)PinDescriptions
IOPinsDescription
sSelector
resDataOutput
1-of-8decoder(One-Cold)VHDLCodingExample
--
--1-of-8decoder(One-Cold)
--
libraryieee;
useieee.std_logic_1164.all;
entitydecoders_2is
port(sel:instd_logic_vector(2downto0);
res:outstd_logic_vector(7downto0));
enddecoders_2;
architecturearchiofdecoders_2is
begin
res<="11111110"whensel="000"else
"11111101"whensel="001"else
"11111011"whensel="010"else
"11110111"whensel="011"else
"11101111"whensel="100"else
"11011111"whensel="101"else
"10111111"whensel="110"else
"01111111";
endarchi;
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Chapter3:XSTHDLCodingTechniques
1-of-8Decoder(One-Cold)VerilogCodingExample
//
//1-of-8decoder(One-Cold)
//
modulev_decoders_2(sel,res);
input[2:0]sel;
output[7:0]res;
reg[7:0]res;
always@(sel)
begin
case(sel)
3’b000:res=8’b11111110;
3’b001:res=8’b11111101;
3’b010:res=8’b11111011;
3’b011:res=8’b11110111;
3’b100:res=8’b11101111;
3’b101:res=8’b11011111;
3’b110:res=8’b10111111;
default:res=8’b01111111;
endcase
end
endmodule
DecoderWithUnselectedOutputsPinDescriptions
IOPinsDescription
sSelector
resDataOutput
NoDecoderInference(UnusedDecoderOutput)VHDLCodingExample
--
--NoDecoderInference(unuseddecoderoutput)
--
libraryieee;
useieee.std_logic_1164.all;
entitydecoders_3is
port(sel:instd_logic_vector(2downto0);
res:outstd_logic_vector(7downto0));
enddecoders_3;
architecturearchiofdecoders_3is
begin
res<="00000001"whensel="000"else
--unuseddecoderoutput
"XXXXXXXX"whensel="001"else
"00000100"whensel="010"else
"00001000"whensel="011"else
"00010000"whensel="100"else
"00100000"whensel="101"else
"01000000"whensel="110"else
"10000000";
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endarchi;
NoDecoderInference(UnusedDecoderOutput)VerilogCodingExample
//
//NoDecoderInference(unuseddecoderoutput)
//
modulev_decoders_3(sel,res);
input[2:0]sel;
output[7:0]res;
reg[7:0]res;
always@(sel)
begin
case(sel)
3’b000:res=8’b00000001;
//unuseddecoderoutput
3’b001:res=8’bxxxxxxxx;
3’b010:res=8’b00000100;
3’b011:res=8’b00001000;
3’b100:res=8’b00010000;
3’b101:res=8’b00100000;
3’b110:res=8’b01000000;
default:res=8’b10000000;
endcase
end
endmodule
NoDecoderInference(SomeSelectorValuesUnused)VHDLCoding
Example
--
--NoDecoderInference(someselectorvaluesareunused)
--
libraryieee;
useieee.std_logic_1164.all;
entitydecoders_4is
port(sel:instd_logic_vector(2downto0);
res:outstd_logic_vector(7downto0));
enddecoders_4;
architecturearchiofdecoders_4is
begin
res<="00000001"whensel="000"else
"00000010"whensel="001"else
"00000100"whensel="010"else
"00001000"whensel="011"else
"00010000"whensel="100"else
"00100000"whensel="101"else
--110and111selectorvaluesareunused
"XXXXXXXX";
endarchi;
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Chapter3:XSTHDLCodingTechniques
NoDecoderInference(SomeSelectorValuesUnused)VerilogCoding
Example
//
//NoDecoderInference(someselectorvaluesareunused)
//
modulev_decoders_4(sel,res);
input[2:0]sel;
output[7:0]res;
reg[7:0]res;
always@(selorres)
begin
case(sel)
3’b000:res=8’b00000001;
3’b001:res=8’b00000010;
3’b010:res=8’b00000100;
3’b011:res=8’b00001000;
3’b100:res=8’b00010000;
3’b101:res=8’b00100000;
//110and111selectorvaluesareunused
default:res=8’bxxxxxxxx;
endcase
end
endmodule
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Chapter3:XSTHDLCodingTechniques
PriorityEncodersHDLCodingTechniques
ThissectiondiscussesPriorityEncodersHDLCodingTechniques,andincludes:
•AboutPriorityEncoders
•PriorityEncodersLogFile
•PriorityEncodersRelatedConstraints
•PriorityEncodersCodingExamples
AboutPriorityEncoders
XSTcanrecognizeapriorityencoder,butinmostcasesXSTdoesnotinferit.Toforce
priorityencoderinference,usePriorityEncoderExtraction(PRIORITY_EXTRACT)
withthevalueforce.
Xilinx®recommendsthatyouusePriorityEncoderExtraction(PRIORITY_EXTRACT)on
asignal-by-signalbasis.Otherwise,PriorityEncoderExtraction(PRIORITY_EXTRACT)
maygivelessthanoptimalresults.
PriorityEncodersLogFile
TheXSTloglereportsthetypeandsizeofrecognizedpriorityencodersduringthe
MacroRecognitionstep.
PriorityEncodersLogFileExample
...
SynthesizingUnit<priority>.
Relatedsourcefileispriority_encoders_1.vhd.
Found3-bit1-of-9priorityencoderforsignal<code>.
Summary:
inferred3Priorityencoder(s).
Unit<priority>synthesized.
==============================
HDLSynthesisReport
MacroStatistics
#PriorityEncoders:1
3-bit1-of-9priorityencoder:1
==============================
...
PriorityEncodersRelatedConstraints
PriorityEncoderExtraction(PRIORITY_EXTRACT)
PriorityEncodersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
ForthisexampleXSTmayinferapriorityencoder.UsePriorityEncoderExtraction
(PRIORITY_EXTRACT)withavalueofforcetoforceitsinference.
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Chapter3:XSTHDLCodingTechniques
3-Bit1-of-9PriorityEncoderPinDescriptions
IOPinsDescription
selSelector
codeEncodedOutputBus
3-Bit1-of-9PriorityEncoderVHDLCodingExample
--
--3-Bit1-of-9PriorityEncoder
--
libraryieee;
useieee.std_logic_1164.all;
entitypriority_encoder_1is
port(sel:instd_logic_vector(7downto0);
code:outstd_logic_vector(2downto0));
attributepriority_extract:string;
attributepriority_extractofpriority_encoder_1:entityis"force";
endpriority_encoder_1;
architecturearchiofpriority_encoder_1is
begin
code<="000"whensel(0)=’1’else
"001"whensel(1)=’1’else
"010"whensel(2)=’1’else
"011"whensel(3)=’1’else
"100"whensel(4)=’1’else
"101"whensel(5)=’1’else
"110"whensel(6)=’1’else
"111"whensel(7)=’1’else
"---";
endarchi;
3-Bit1-of-9PriorityEncoderVerilogCodingExample
//
//3-Bit1-of-9PriorityEncoder
//
(*priority_extract="force"*)
modulev_priority_encoder_1(sel,code);
input[7:0]sel;
output[2:0]code;
reg[2:0]code;
always@(sel)
begin
if(sel[0])code=3’b000;
elseif(sel[1])code=3’b001;
elseif(sel[2])code=3’b010;
elseif(sel[3])code=3’b011;
elseif(sel[4])code=3’b100;
elseif(sel[5])code=3’b101;
elseif(sel[6])code=3’b110;
elseif(sel[7])code=3’b111;
elsecode=3’bxxx;
end
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Chapter3:XSTHDLCodingTechniques
LogicalShiftersHDLCodingTechniques
ThissectiondiscussesLogicalShiftersHDLCodingTechniques,andincludes:
•AboutLogicalShifters
•LogicalShiftersLogFile
•LogicalShiftersRelatedConstraints
•LogicalShiftersCodingExamples
AboutLogicalShifters
Xilinx®denesalogicalshifterasacombinatorialcircuitwith2inputsand1output:
•Therstinputisadatainputthatisshifted.
•Thesecondinputisaselectorwhosebinaryvaluedenestheshiftdistance.
•Theoutputistheresultoftheshiftoperation.
AlloftheseI/Osaremandatory .Otherwise,XSTdoesnotinferalogicalshifter.
WhenwritingyourHardwareDescriptionLanguage(HDL)code:
•Useonlylogical,arithmetic,androtateshiftoperators.Shiftoperationsthatll
vacatedpositionswithvaluesfromanothersignalarenotrecognized.
•ForVHDL,youcanusepredenedshift(forexample,SLL,SRL,ROL)or
concatenationoperationsonly.Formoreinformationonpredenedshiftoperations,
seetheIEEEVHDLreferencemanual.
•Useonlyonetypeofshiftoperation.
•Thenvalueintheshiftoperationmustbeincrementedordecrementedonlyby1for
eachconsequentbinaryvalueoftheselector.
•Thenvaluecanbepositiveonly.
•Allvaluesoftheselectormustbepresented.
LogicalShiftersLogFile
TheXSTloglereportsthetypeandsizeofarecognizedlogicalshifterduringthe
MacroRecognitionstep.
LogicalShiftersLogFileExample
...
SynthesizingUnit<lshift>.
RelatedsourcefileisLogical_Shifters_1.vhd.
Found8-bitshifterlogicalleftforsignal<so>.
Summary:
inferred1Combinationallogicshifter(s).
Unit<lshift>synthesized.
...
==============================
HDLSynthesisReport
MacroStatistics
#Logicshifters:1
8-bitshifterlogicalleft:1
==============================
...
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Chapter3:XSTHDLCodingTechniques
LogicalShiftersRelatedConstraints
LogicalShifterExtraction(SHIFT_EXTRACT)
LogicalShiftersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
TheminimalsizeforXSTtoexplicitlyinferlogicalshiftermacrosmayvarydepending
onthetargeteddevicefamily.Thefollowingcodingexampleshavebeenvalidatedon
LUT4-baseddevicefamiliessuchasVirtex®-4devices.ForVirtex-5devices,logical
shiftersareexplicitlyinferredonlywhentheselectorsizeisatleast3.
LogicalShifterOneDiagram
LogicalShifterOnePinDescriptions
IOPinsDescription
DIDataInput
SELShiftDistanceSelector
SODataOutput
LogicalShifterOneVHDLCodingExample
--
--FollowingistheVHDLcodeforalogicalshifter.
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitylogical_shifters_1is
port(DI:inunsigned(7downto0);
SEL:inunsigned(1downto0);
SO:outunsigned(7downto0));
endlogical_shifters_1;
architecturearchioflogical_shifters_1is
begin
withSELselect
SO<=DIwhen"00",
DIsll1when"01",
DIsll2when"10",
DIsll3whenothers;
endarchi;
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Chapter3:XSTHDLCodingTechniques
LogicalShifterOneVerilogCodingExample
//
//FollowingistheVerilogcodeforalogicalshifter.
//
modulev_logical_shifters_1(DI,SEL,SO);
input[7:0]DI;
input[1:0]SEL;
output[7:0]SO;
reg[7:0]SO;
always@(DIorSEL)
begin
case(SEL)
2’b00:SO=DI;
2’b01:SO=DI<<1;
2’b10:SO=DI<<2;
default:SO=DI<<3;
endcase
end
endmodule
LogicalShifterTwoPinDescriptions
IOPinsDescription
DIDataInput
SELShiftDistanceSelector
SODataOutput
LogicalShifterTwoVHDLCodingExample
XSTdoesnotinferalogicalshifterforLogicalShifterTwo,sincenotallselectorvalues
arepresented.
--
--XSTdoesnotinferalogicalshifterforthisexample,
--asnotalloftheselectorvaluesarepresented.
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitylogical_shifters_2is
port(DI:inunsigned(7downto0);
SEL:inunsigned(1downto0);
SO:outunsigned(7downto0));
endlogical_shifters_2;
architecturearchioflogical_shifters_2is
begin
withSELselect
SO<=DIwhen"00",
DIsll1when"01",
DIsll2whenothers;
endarchi;
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Chapter3:XSTHDLCodingTechniques
LogicalShifterTwoVerilogCodingExample
//
//XSTdoesnotinferalogicalshifterforthisexample,
//asnotalloftheselectorvaluesarepresented.
//
modulev_logical_shifters_2(DI,SEL,SO);
input[7:0]DI;
input[1:0]SEL;
output[7:0]SO;
reg[7:0]SO;
always@(DIorSEL)
begin
case(SEL)
2’b00:SO=DI;
2’b01:SO=DI<<1;
default:SO=DI<<2;
endcase
end
endmodule
LogicalShifterThreePinDescriptions
IOPinsDescription
DIDataInput
SELShiftDistanceSelector
SODataOutput
LogicalShifterThreeVHDLCodingExample
XSTdoesnotinferalogicalshifterforthisexample,asthevalueisnotincrementedby1
foreachconsequentbinaryvalueoftheselector.
--
--XSTdoesnotinferalogicalshifterforthisexample,
--asthevalueisnotincrementedby1foreachconsequent
--binaryvalueoftheselector.
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitylogical_shifters_3is
port(DI:inunsigned(7downto0);
SEL:inunsigned(1downto0);
SO:outunsigned(7downto0));
endlogical_shifters_3;
architecturearchioflogical_shifters_3is
begin
withSELselect
SO<=DIwhen"00",
DIsll1when"01",
DIsll3when"10",
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Chapter3:XSTHDLCodingTechniques
DIsll2whenothers;
endarchi;
LogicalShifterThreeVerilogCodingExample
//
//XSTdoesnotinferalogicalshifterforthisexample,
//asthevalueisnotincrementedby1foreachconsequent
//binaryvalueoftheselector.
//
modulev_logical_shifters_3(DI,SEL,SO);
input[7:0]DI;
input[1:0]SEL;
output[7:0]SO;
reg[7:0]SO;
always@(DIorSEL)
begin
case(SEL)
2’b00:SO=DI;
2’b01:SO=DI<<1;
2’b10:SO=DI<<3;
default:SO=DI<<2;
endcase
end
endmodule
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Chapter3:XSTHDLCodingTechniques
ArithmeticOperatorsHDLCodingTechniques
Thissectionandincludes:
•AboutArithmeticOperators
•ArithmeticOperatorsLogFile
•ArithmeticOperatorsRelatedConstraints
•ArithmeticOperatorsCodingExamples
AboutArithmeticOperators
ThissectiondiscussesArithmeticOperators,andincludes:
•SupportedArithmeticOperators
•SignedandUnsignedOperators
•ResourceSharing
SupportedArithmeticOperators
XSTsupportsthefollowingarithmeticoperators:
•Adderswith:
–CarryIn
–CarryOut
–CarryIn/Out
•Subtractors
•Adders/Subtractors
•Comparators:
–=
–/=
–<
–<=
–>
–>=
•Multipliers
•Dividers
SignedandUnsignedOperators
XSTsupportsthefollowingforsignedandunsignedoperators:
•Adders
•Subtractors
•Comparators
•Multipliers
FormoreinformationonsignedandunsignedoperatorssupportinVHDL,see:
RegistersHDLCodingTechniques
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Chapter3:XSTHDLCodingTechniques
ResourceSharing
XSTperformsresourcesharingfor:
•Adders
•Subtractors
•Adders/subtractors
•Multipliers
ArithmeticOperatorsLogFile
TheXSTloglereportsthetypeandsizeofrecognizedadder,subtractorand
adder/subtractorduringtheMacroRecognitionstep.
ArithmeticOperatorsLogFileExample
...
SynthesizingUnit<adder>.
Relatedsourcefileisarithmetic_operations_1.vhd.
Found8-bitadderforsignal<sum>.
Summary:
inferred1Adder/Subtracter(s).
Unit<adder>synthesized.
=============================
HDLSynthesisReport
MacroStatistics
#Adders/Subtractors:1
8-bitadder:1
==============================
ArithmeticOperatorsRelatedConstraints
•UseDSP48(USE_DSP48)
•DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
•Keep(KEEP)
ArithmeticOperatorsCodingExamples
None
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Chapter3:XSTHDLCodingTechniques
Adders,Subtractors,andAdders/SubtractorsHDLCoding
Techniques
Thissectionincludes:
•AboutAdders,Subtractors,andAdders/Subtractors
•Adders,Subtractors,andAdders/SubtractorsLogFile
•Adders,Subtractors,andAdders/SubtractorsRelatedConstraints
•Adders,Subtractors,andAdders/SubtractorsCodingExamples
AboutAdders,Subtractors,andAdders/Subtractors
Thissectionincludes:
•SupportedDeviceFamilies
•XSTDSP48BlockSupport
•MacroImplementationonDSP48Blocks
•AutomaticDSP48ResourceControl
•MaximumMacroConguration
SupportedDeviceFamilies
Thefollowingdevicefamiliesallowaddersandsubtractorstobeimplementedon
DSP48resources:
•Virtex®-4
•Virtex-5
•Spartan®-3ADSP
XSTDSP48BlockSupport
XSTsupportstheonelevelofoutputregistersintoDSP48blocks.IftheCarryInor
Add/Suboperationselectorsareregistered,XSTpushestheseregistersintotheDSP48as
well.
XSTcanimplementanadder/subtractorinaDSP48blockifitsimplementationrequires
onlyasingleDSP48resource.Ifanadder/subtractormacrodoesnottinasingle
DSP48,XSTimplementstheentiremacrousingslicelogic.
MacroImplementationonDSP48Blocks
MacroimplementationonDSP48blocksiscontrolledbyDSPUtilizationRatio
(DSP_UTILIZATION_RATIO)withadefaultvalueofauto.Inautomode,ifan
adder/subtractorisapartofamorecomplexmacrosuchasalter,XSTautomatically
placesitontheDSPblock.Otherwise,XSTimplementsadders/subtractorsusingLUTs.
SetthevalueofUseDSP48(USE_DSP48)toyesinordertoforceXSTtopushthese
macrosintoaDSP48.WhenplacinganAdder/SubtractoronaDSPblock,XSTchecks
toseeifitisconnectedtootherDSPchains.Ifso,XSTtriestotakeadvantageoffast
DSPconnections,andconnectsthisadder/subtractortotheDSPchainusingthesefast
connections.
AutomaticDSP48ResourceControl
Whenimplementingadders/subtractorsonDSP48blocks,XSTperformsautomatic
DSP48resourcecontrol.
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Chapter3:XSTHDLCodingTechniques
MaximumMacroConfiguration
Todeliverthebestperformance,XSTbydefaulttriestoinferandimplementthe
maximummacroconguration,includingasmanyregistersintheDSP48aspossible.
UseKeep(KEEP)toshapeamacroinaspecicway.Forexample,toexcludetherst
registerstagefromtheDSP48,placeKeep(KEEP)constraintsontheoutputsofthese
registers.
Adders,Subtractors,andAdders/SubtractorsLogFile
Inthelogle,XSTreportsthedetailsofinferredmultipliers,adders,subtractors,and
registersattheHDLSynthesisstep.XSTreportsaboutinferredMACsduringthe
AdvancedHDLSynthesisStepwheretheMACimplementationmechanismtakesplace.
Adders,Subtractors,andAdders/SubtractorsLogFileExample
SynthesizingUnit<v_adders_4>.
Relatedsourcefileis"v_adders_4.v".
Found8-bitaddercarryin/outforsignal<$addsub0000>.
Summary:
inferred1Adder/Subtractor(s).
Unit<v_adders_4>synthesized.
===========================================================
HDLSynthesisReport
MacroStatistics
#Adders/Subtractors:1
8-bitaddercarryin/out:1
============================================================
Adders,Subtractors,andAdders/SubtractorsRelatedConstraints
•UseDSP48(USE_DSP48)
•DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
•Keep(KEEP)
Adders,Subtractors,andAdders/SubtractorsCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
Unsigned8-BitAdderDiagram
Frontmatter
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Chapter3:XSTHDLCodingTechniques
Unsigned8-BitAdderPinDescriptionsIOPins
IOPinsDescription
A,BAddOperands
SUMAddResult
Unsigned8-BitAdderVHDLCodingExample
--
--Unsigned8-bitAdder
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityadders_1is
port(A,B:instd_logic_vector(7downto0);
SUM:outstd_logic_vector(7downto0));
endadders_1;
architecturearchiofadders_1is
begin
SUM<=A+B;
endarchi;
Unsigned8-BitAdderVerilogCodingExample
//
//Unsigned8-bitAdder
//
modulev_adders_1(A,B,SUM);
input[7:0]A;
input[7:0]B;
output[7:0]SUM;
assignSUM=A+B;
endmodule
Unsigned8-BitAdderWithCarryInDiagram
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Chapter3:XSTHDLCodingTechniques
Unsigned8-BitAdderWithCarryInPinDescriptionsIOPins
IOPinsDescription
A,BAddOperands
CICarryIn
SUMAddResult
Unsigned8-BitAdderWithCarryInVHDLCodingExample
--
--Unsigned8-bitAdderwithCarryIn
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityadders_2is
port(A,B:instd_logic_vector(7downto0);
CI:instd_logic;
SUM:outstd_logic_vector(7downto0));
endadders_2;
architecturearchiofadders_2is
begin
SUM<=A+B+CI;
endarchi;
Unsigned8-BitAdderWithCarryInVerilogCodingExample
//
//Unsigned8-bitAdderwithCarryIn
//
modulev_adders_2(A,B,CI,SUM);
input[7:0]A;
input[7:0]B;
inputCI;
output[7:0]SUM;
assignSUM=A+B+CI;
endmodule
Unsigned8-BitAdderWithCarryOut
Beforewritinga+(plus)operationwithcarryoutinVHDL,readthearithmeticpackage
youplantouse.Forexample,std_logic_unsigneddoesnotallowyoutowrite+(plus)
inthefollowingformtoobtainCarryOut:
Res(9-bit)=A(8-bit)+B(8-bit)
Thereasonisthatthesizeoftheresultfor+(plus)inthispackageisequaltothesize
ofthelongestargument(8bits).
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Chapter3:XSTHDLCodingTechniques
OnesolutionfortheexampleistoadjustthesizeofoperandsAandBto9bitsusing
concatenation.
Res<=("0"&A)+("0"&B);
Inthiscase,XSTrecognizesthatthis9-bitaddercanbeimplementedasan8-bitadder
withcarryout.
Anothersolutionis:
•ConvertAandBtointegers
•Converttheresultbacktothestd_logicvector
•Specifythesizeofthevectorequalto9
Unsigned8-BitAdderWithCarryOutDiagram
Unsigned8-BitAdderWithCarryOutPinDescriptionsIOPins
IOPinsDescription
A,BAddOperands
SUMAddResult
COCarryOut
Unsigned8-BitAdderWithCarryOutVHDLCodingExample
--
--Unsigned8-bitAdderwithCarryOut
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityadders_3is
port(A,B:instd_logic_vector(7downto0);
SUM:outstd_logic_vector(7downto0);
CO:outstd_logic);
endadders_3;
architecturearchiofadders_3is
signaltmp:std_logic_vector(8downto0);
begin
tmp<=conv_std_logic_vector((conv_integer(A)+conv_integer(B)),9);
SUM<=tmp(7downto0);
CO<=tmp(8);
endarchi;
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Chapter3:XSTHDLCodingTechniques
Theprecedingexampleusestwoarithmeticpackages:
•std_logic_arith
Containstheintegertostd_logicconversionfunction(conv_std_logic_vector)
•std_logic_unsigned
Containstheunsigned+(plus)operation
Unsigned8-BitAdderWithCarryOutVerilogCodingExample
//
//Unsigned8-bitAdderwithCarryOut
//
modulev_adders_3(A,B,SUM,CO);
input[7:0]A;
input[7:0]B;
output[7:0]SUM;
outputCO;
wire[8:0]tmp;
assigntmp=A+B;
assignSUM=tmp[7:0];
assignCO=tmp[8];
endmodule
Unsigned8-BitAdderWithCarryInandCarryOutDiagram
Unsigned8-BitAdderWithCarryInandCarryOutPinDescriptionsIOPins
IOPinsDescription
A,BAddOperands
CICarryIn
SUMAddResult
COCarryOut
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Chapter3:XSTHDLCodingTechniques
Unsigned8-BitAdderWithCarryInandCarryOutVHDLCodingExample
--
--Unsigned8-bitAdderwithCarryInandCarryOut
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityadders_4is
port(A,B:instd_logic_vector(7downto0);
CI:instd_logic;
SUM:outstd_logic_vector(7downto0);
CO:outstd_logic);
endadders_4;
architecturearchiofadders_4is
signaltmp:std_logic_vector(8downto0);
begin
tmp<=conv_std_logic_vector((conv_integer(A)+conv_integer(B)+conv_integer(CI)),9);
SUM<=tmp(7downto0);
CO<=tmp(8);
endarchi;
Unsigned8-BitAdderWithCarryInandCarryOutVerilogCodingExample
//
//Unsigned8-bitAdderwithCarryInandCarryOut
//
modulev_adders_4(A,B,CI,SUM,CO);
inputCI;
input[7:0]A;
input[7:0]B;
output[7:0]SUM;
outputCO;
wire[8:0]tmp;
assigntmp=A+B+CI;
assignSUM=tmp[7:0];
assignCO=tmp[8];
endmodule
Signed8-BitAdderDiagram
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Chapter3:XSTHDLCodingTechniques
Signed8-BitAdderPinDescriptionsIOPins
IOPinsDescription
A,BAddOperands
SUMAddResult
Signed8-BitAdderVHDLCodingExample
--
--Signed8-bitAdder
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
entityadders_5is
port(A,B:instd_logic_vector(7downto0);
SUM:outstd_logic_vector(7downto0));
endadders_5;
architecturearchiofadders_5is
begin
SUM<=A+B;
endarchi;
Signed8-BitAdderVerilogCodingExample
//
//Signed8-bitAdder
//
modulev_adders_5(A,B,SUM);
inputsigned[7:0]A;
inputsigned[7:0]B;
outputsigned[7:0]SUM;
wiresigned[7:0]SUM;
assignSUM=A+B;
endmodule
Unsigned8-BitSubtractorDiagram
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Chapter3:XSTHDLCodingTechniques
Unsigned8-BitSubtractorPinDescriptions
IOPinsDescription
A,BSubOperands
RESSubResult
Unsigned8-BitSubtractorVHDLCodingExample
--
--Unsigned8-bitSubtractor
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityadders_6is
port(A,B:instd_logic_vector(7downto0);
RES:outstd_logic_vector(7downto0));
endadders_6;
architecturearchiofadders_6is
begin
RES<=A-B;
endarchi;
Unsigned8-BitSubtractorVerilogCodingExample
//
//Unsigned8-bitSubtractor
//
modulev_adders_6(A,B,RES);
input[7:0]A;
input[7:0]B;
output[7:0]RES;
assignRES=A-B;
endmodule
Unsigned8-BitSubtractorWithBorrowInPinDescriptions
IOPinsDescription
A,BSubOperands
BIBorrowIn
RESSubResult
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Chapter3:XSTHDLCodingTechniques
Unsigned8-BitSubtractorWithBorrowInVHDLCodingExample
--
--Unsigned8-bitSubtractorwithBorrowIn
--
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityadders_8is
port(A,B:instd_logic_vector(7downto0);
BI:instd_logic;
RES:outstd_logic_vector(7downto0));
endadders_8;
architecturearchiofadders_8is
begin
RES<=A-B-BI;
endarchi;
Unsigned8-BitSubtractorWithBorrowInVerilogCodingExample
//
//Unsigned8-bitSubtractorwithBorrowIn
//
modulev_adders_8(A,B,BI,RES);
input[7:0]A;
input[7:0]B;
inputBI;
output[7:0]RES;
assignRES=A-B-BI;
endmodule
Unsigned8-BitAdder/SubtractorDiagram
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Unsigned8-BitAdder/SubtractorPinDescriptions
IOPinsDescription
A,BAdd/SubOperands
OPERAdd/SubSelect
SUMAdd/SubResult
Unsigned8-BitAdder/SubtractorVHDLCodingExample
--
--Unsigned8-bitAdder/Subtractor
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityadders_7is
port(A,B:instd_logic_vector(7downto0);
OPER:instd_logic;
RES:outstd_logic_vector(7downto0));
endadders_7;
architecturearchiofadders_7is
begin
RES<=A+BwhenOPER=’0’
elseA-B;
endarchi;
Unsigned8-BitAdder/SubtractorVerilogCodingExample
//
//Unsigned8-bitAdder/Subtractor
//
modulev_adders_7(A,B,OPER,RES);
inputOPER;
input[7:0]A;
input[7:0]B;
output[7:0]RES;
reg[7:0]RES;
always@(AorBorOPER)
begin
if(OPER==1’b0)RES=A+B;
elseRES=A-B;
end
endmodule
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Chapter3:XSTHDLCodingTechniques
ComparatorsHDLCodingTechniques
ThissectiondiscussesComparatorsHDLCodingTechniques,andincludes:
•AboutComparators
•ComparatorsLogFile
•ComparatorsRelatedConstraints
•ComparatorsCodingExamples
AboutComparators
Notapplicable.
ComparatorsLogFile
TheXSTloglereportsthetypeandsizeofrecognizedcomparatorsduringtheMacro
Recognitionstep.
ComparatorsLogFileExample
...
SynthesizingUnit<compar>.
Relatedsourcefileiscomparators_1.vhd.
Found8-bitcomparatorgreatequalforsignal<$n0000>createdatline10.
Summary:
inferred1Comparator(s).
Unit<compar>synthesized.
=============================
HDLSynthesisReport
MacroStatistics
#Comparators:1
8-bitcomparatorgreatequal:1
==============================
...
ComparatorsRelatedConstraints
None
ComparatorsCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
Unsigned8-BitGreaterorEqualComparatorDiagram
Unsigned8-BitGreaterorEqualComparatorPinDescriptions
IOPinsDescription
A,BComparisonOperands
CMPComparisonResult
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Unsigned8-BitGreaterorEqualComparatorVHDLCodingExample
--
--Unsigned8-bitGreaterorEqualComparator
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycomparator_1is
port(A,B:instd_logic_vector(7downto0);
CMP:outstd_logic);
endcomparator_1;
architecturearchiofcomparator_1is
begin
CMP<=’1’whenA>=Belse’0’;
endarchi;
Unsigned8-BitGreaterorEqualComparatorVerilogCodingExample
//
//Unsigned8-bitGreaterorEqualComparator
//
modulev_comparator_1(A,B,CMP);
input[7:0]A;
input[7:0]B;
outputCMP;
assignCMP=(A>=B)?1’b1:1’b0;
endmodule
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Chapter3:XSTHDLCodingTechniques
MultipliersHDLCodingTechniques
ThissectiondiscussesMultipliersHDLCodingTechniques,andincludes:
•AboutMultipliers
•Multipliers(Virtex®-4,Virtex-5,andSpartan®-3ADSPDevices)
•MultipliersLogFile
•MultipliersRelatedConstraints
•MultipliersCodingExamples
AboutMultipliers
ThissectiondiscussesMultipliers,andincludes:
•ImplementingaMultiplier
•RegisteredMultipliers
•MultiplicationwithConstant
ImplementingaMultiplier
Whenimplementingamultiplier,thesizeoftheresultingsignalisequaltothesumof
twooperandlengths.Forexample,ifyoumultiplyA(8-bitsignal)byB(4-bitsignal),
thesizeoftheresultmustbedeclaredasa12-bitsignal.
RegisteredMultipliers
Ininstanceswhereamultiplierwouldhavearegisteredoutput,XSTinfersaunique
registeredmultiplierforthefollowingdevices:
•Virtex®-4
•Virtex-5
Thisregisteredmultiplieris18x18bits.
Underthefollowingconditions,aregisteredmultiplierisnotused,andamultiplier+
registerisusedinstead.
•Outputfromthemultipliergoestoanycomponentotherthantheregister.
•TheMultiplierStyle(MULT_STYLE)constraintissetto:
lut
•Themultiplierisasynchronous.
•Themultiplierhascontrolsignalsotherthansynchronousresetorclockenable.
•Themultiplierdoesnottinasingle18x18bitblockmultiplier.
Thefollowingpinsareoptionalforaregisteredmultiplier:
•Clockenableport
•Synchronousandasynchronousreset,andloadports
MultiplicationwithConstant
Whenoneoftheargumentsisaconstant,XSTcancreateefcientdedicated
implementationsofamultiplierwithaconstantusingtwomethods:
•ConstantCoefcientMultiplier(KCM)
•CanonicalSignedDigit(CSD)
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Dedicatedimplementationsdonotalwaysprovidethebestresultsformultiplication
withconstants.XSTcanautomaticallychoosebetweenKCMorstandardmultiplier
implementation.TheCSDmethodcannotbeautomaticallychosen.UseMuxStyle
(MUX_STYLE)toforceCSDimplementation.
XSTdoesnotsupportKCMorCSDimplementationforsignednumbers.
Iftheeitheroftheargumentsislargerthan32bits,XSTdoesnotuseKCMorCSD
implementation,evenifitisspeciedwithMultiplierStyle(MULT_STYLE).
Multipliers(Virtex-4,Virtex-5,andSpartan-3ADSPDevices)
NoteThissectionappliestoVirtex®-4devices,Virtex-5devices,andSpartan®-3A
DSPdevicesonly.
ThissectiondiscussesMultipliers(Virtex-4,Virtex-5,andSpartan-3ADSPDevices),
andincludes:
•ImplementingMultipliersonDSP48Resources
•MultipleDSP48Resources
•MacroImplementationonDSP48Blocks
•RecognizingtheMultiplierStyleConstraint
•MaximumMacroConguration
ImplementingMultipliersonDSP48Resources
Virtex-4devices,Virtex-5devices,andSpartan-3ADSPdevicesallowmultipliersto
beimplementedonDSP48resources.XSTsupportstheregisteredversionofthese
macrosandcanpushupto2levelsofinputregistersand2levelsofoutputregisters
intoDSP48blocks.
MultipleDSP48Resources
IfamultiplierimplementationrequiresmultipleDSP48resources,XSTautomatically
decomposesitontomultipleDSP48blocks.Dependingontheoperandsize,andto
obtainthebestperformance,XSTmayimplementmostofamultiplierusingDSP48
blocks,anduseslicelogicfortherestofthemacro.Forexample,itisnotsufcienttouse
asingleDSP48toimplementan18x18unsignedmultiplier.Inthiscase,XSTimplements
mostofthelogicinoneDSP48,andtherestinLUTs.
ForVirtex-4devices,Virtex-5devices,andSpartan-3ADSPdevices,XSTcaninfer
pipelinedmultipliers,notonlyfortheLUTimplementation,butfortheDSP48
implementationaswell.
MacroImplementationonDSP48Blocks
MacroimplementationonDSP48blocksiscontrolledbytheUseDSP48(USE_DSP48)
constraintorcommandlineoption,withadefaultvalueofauto.Inthismode,XST
implementsmultiplierstakingintoaccountavailableDSP48resourcesinthedevice.
Inautomode,useDSPUtilizationRatio(DSP_UTILIZATION_RATIO)tocontrolDSP48
resourcesforsynthesis.Bydefault,XSTtriestoutilizeallDSP48resources.
Formoreinformation,see:
DSP48BlockResources.
RecognizingtheMultiplierStyleConstraint
XSTcanautomaticallyrecognizetheMultiplierStyle(MULT_STYLE)constraintwith
valueslutandblockandthenconvertittoUseDSP48(USE_DSP48).
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Xilinx®recommends:
•UseUseDSP48(USE_DSP48)forVirtex-4devicesandVirtex-5devicestodene
FPGAresourcesusedformultiplierimplementation.
•UseMultiplierStyle(MULT_STYLE)todenethemultiplierimplementation
methodontheselectedFPGAresources.
Thefollowingrulesapply:
•IfUseDSP48(USE_DSP48)issettoautooryes,youmayusemult_style=pipe_block
topipelinetheDSP48implementationifthemultiplierimplementationrequires
multipleDSP48blocks.
•IfUseDSP48(USE_DSP48)issettono,usemult_style=pipe_lut|KCM|CSDto
denethemultiplierimplementationmethodonLUTs.
MaximumMacroConfiguration
Todeliverthebestperformance,XSTbydefaulttriestoinferandimplementthe
maximummacroconguration,includingasmanyregistersintheDSP48aspossible.
UseKeep(KEEP)toshapeamacroinaspecicway.Forexample,toexcludetherst
registerstagefromtheDSP48,placeKeep(KEEP)constraintsontheoutputsofthese
registers.
MultipliersLogFile
TheXSTloglereportsthetypeandsizeofrecognizedmultipliersduringtheMacro
Recognitionstep.
MultipliersLogFileExample
...
SynthesizingUnit<mux>.
Relatedsourcefileismultiplexers_1.vhd.
Found1-bit4-to-1multiplexerforsignal<o>.
Summary:
inferred1Multiplexer(s).
Unit<mux>synthesized.
=============================
HDLSynthesisReport
MacroStatistics
#Multiplexers:1
1-bit4-to-1multiplexer:1
==============================
...
MultipliersRelatedConstraints
•MultiplierStyle(MULT_STYLE)
•UseDSP48(USE_DSP48)
•DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
•Keep(KEEP)
MultipliersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
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Chapter3:XSTHDLCodingTechniques
Unsigned8x4-BitMultiplierDiagram
Unsigned8x4-BitMultiplierPinDescriptions
IOPinsDescription
A,BMULTOperands
RESMULTResult
Unsigned8x4-BitMultiplierVHDLCodingExample
--
--Unsigned8x4-bitMultiplier
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymultipliers_1is
port(A:instd_logic_vector(7downto0);
B:instd_logic_vector(3downto0);
RES:outstd_logic_vector(11downto0));
endmultipliers_1;
architecturebehofmultipliers_1is
begin
RES<=A*B;
endbeh;
Unsigned8x4-BitMultiplierVerilogCodingExample
//
//Unsigned8x4-bitMultiplier
//
modulev_multipliers_1(A,B,RES);
input[7:0]A;
input[3:0]B;
output[11:0]RES;
assignRES=A*B;
endmodule
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Chapter3:XSTHDLCodingTechniques
SequentialComplexMultipliersHDLCodingTechniques
ThissectiondiscussesSequentialComplexMultipliersHDLCodingTechniques,and
includes:
•AboutSequentialComplexMultipliers
•SequentialComplexMultipliersLogFile
•SequentialComplexMultipliersRelatedConstraints
•SequentialComplexMultipliersCodingExamples
AboutSequentialComplexMultipliers
Asequentialcomplexmultiplierrequires:
•Fourcyclestomakeacompletemultiplicationbyaccumulatingintermediateresults.
•OneDSPblockforimplementation.
MultiplyingtwocomplexnumbersAandBrequiresfourcycles.
Thersttworstcyclescompute:
Res_real=A_real*B_real-A_imag*B_imag
Thesecondtwocyclescompute:
Res_imag=A_real*B_imag+A_imag*B_real
Whileseveraltemplatescouldbeusedtodescribetheabovefunctionality ,XSTdoesnot
supportusingenumorintegertypestodescribethedifferentDSPmodesandstore
theenumvalues.Instead,Xilinx®recommendsaveryregulartemplatetoeaseXST
inferencing.ThisgeneralaccumulatortemplateallowsXSTtoinferenceasingleDSPto
performthefollowingoperations:
•Load:P<=Value
•Load:P<=-Value
•Accumulate:P<=P+V alue
•Accumulate:P<=P-Value
Thistemplateworkswiththefollowingtwocontrolsignalsthatperformtheabove
fouroperationswhencombined:
•load
•addsub
SequentialComplexMultipliersLogFile
None
SequentialComplexMultipliersRelatedConstraints
None
SequentialComplexMultipliersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
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Chapter3:XSTHDLCodingTechniques
Signed18x18-bitSequentialComplexMultiplierPinDescriptions
IOPinsDescription
CLKClockSignal
Oper_Load,Oper_AddSubControlSignalscontrollingLoadandAddSub
Operations
A,BMULTOperands
RESMULTResult
Signed18x18-bitSequentialComplexMultiplierVHDLCodingExample
--
--SequentialComplexMultiplier
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitymultipliers_8is
generic(A_WIDTH:positive:=18;
B_WIDTH:positive:=18;
RES_WIDTH:positive:=48);
port(CLK:instd_logic;
A:insigned(A_WIDTH-1downto0);
B:insigned(B_WIDTH-1downto0);
Oper_Load:instd_logic;
Oper_AddSub:instd_logic;
--Oper_LoadOper_AddSubOperation
--00R=+A*B
--01R=-A*B
--10R=R+A*B
--11R=R-A*B
RES:outsigned(RES_WIDTH-1downto0)
);
endmultipliers_8;
architecturebehofmultipliers_8is
constantP_WIDTH:integer:=A_WIDTH+B_WIDTH;
signaloper_load0:std_logic:=’0’;
signaloper_addsub0:std_logic:=’0’;
signalp1:signed(P_WIDTH-1downto0):=(others=>’0’);
signaloper_load1:std_logic:=’0’;
signaloper_addsub1:std_logic:=’0’;
signalres0:signed(RES_WIDTH-1downto0);
begin
process(clk)
variableacc:signed(RES_WIDTH-1downto0);
begin
ifrising_edge(clk)then
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Chapter3:XSTHDLCodingTechniques
oper_load0<=Oper_Load;
oper_addsub0<=Oper_AddSub;
p1<=A*B;
oper_load1<=oper_load0;
oper_addsub1<=oper_addsub0;
if(oper_load1=’1’)then
acc:=res0;
else
acc:=(others=>’0’);
endif;
if(oper_addsub1=’1’)then
res0<=acc-p1;
else
res0<=acc+p1;
endif;
endif;
endprocess;
RES<=res0;
endarchitecture;
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Chapter3:XSTHDLCodingTechniques
Signed18x18-bitSequentialComplexMultiplierVerilogCodingExample
modulev_multipliers_8(CLK,A,B,Oper_Load,Oper_AddSub,RES);
parameterA_WIDTH=18;
parameterB_WIDTH=18;
parameterRES_WIDTH=48;
parameterP_WIDTH=A_WIDTH+B_WIDTH;
inputCLK;
inputsigned[A_WIDTH-1:0]A,B;
inputOper_Load,Oper_AddSub;
//Oper_LoadOper_AddSubOperation
//00R=+A*B
//01R=-A*B
//10R=R+A*B
//11R=R-A*B
output[RES_WIDTH-1:0]RES;
regoper_load0=0;
regoper_addsub0=0;
regsigned[P_WIDTH-1:0]p1=0;
regoper_load1=0;
regoper_addsub1=0;
regsigned[RES_WIDTH-1:0]res0=0;
regsigned[RES_WIDTH-1:0]acc;
always@(posedgeCLK)
begin
oper_load0<=Oper_Load;
oper_addsub0<=Oper_AddSub;
p1<=A*B;
oper_load1<=oper_load0;
oper_addsub1<=oper_addsub0;
if(oper_load1==1’b1)
acc=res0;
else
acc=0;
if(oper_addsub1==1’b1)
res0<=acc-p1;
else
res0<=acc+p1;
end
assignRES=res0;
endmodule
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Chapter3:XSTHDLCodingTechniques
PipelinedMultipliersHDLCodingTechniques
ThissectiondiscussesPipelinedMultipliersHDLCodingTechniques,andincludes:
•AboutPipelinedMultipliers
•PipelinedMultipliersLogFile
•PipelinedMultipliersRelatedConstraints
•PipelinedMultipliersCodingExamples
AboutPipelinedMultipliers
ThissectiondiscussesAboutPipelinedMultipliers,andincludes:
•InferringPipelinedMultipliers
•MaximizingPerformance
•ImplementingUnusedStages
•XSTLimitations
InferringPipelinedMultipliers
Inordertoincreasethespeedofdesignswithlargemultipliers,XSTcaninferpipelined
multipliers.Byinterspersingregistersbetweenthestagesoflargemultipliers,pipelining
cansignicantlyincreasetheoverallfrequencyofyourdesign.Theeffectofpipelining
issimilartoFlip-FlopRetiming.
Toinsertpipelinestages:
1.DescribethenecessaryregistersinyourHDLcode
2.Placethemafteranymultipliers
3.SetMultiplierStyle(MULT_STYLE)to:
pipe_lut
XSTcanalsopipelineanimplementationwhen:
•ThetargetisaVirtex®-4deviceoraVirtex-5device,and
•ImplementationofamultiplierrequiresmultipleDSP48blocks
SetMultiplierStyle(MULT_STYLE)inthisinstanceto:
pipe_block
MaximizingPerformance
Inordertoreachthemaximummultiplierspeed,XSTusesthemaximumnumberof
availableregisterswhen:
•XSTdetectsvalidregistersforpipelining,and
•MultiplierStyle(MULT_STYLE)issetto:
pipe_lutorpipe_block
Inordertoobtainthebestfrequency,XSTautomaticallycalculatesthemaximum
numberofregistersforeachmultiplier.
DuringtheAdvancedHDLSynthesisstep,theXSTHDLAdvisoradvisesyoutospecify
theoptimumnumberofregisterstagesif:
•Youhavenotspeciedsufcientregisterstages,and
•MultiplierStyle(MULT_STYLE)iscodeddirectlyonasignal,
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ImplementingUnusedStages
XSTimplementstheunusedstagesasshiftregistersif:
•Thenumberofregistersplacedafterthemultiplierexceedsthemaximumrequired,
and
•Shiftregisterextractionisactivated
XSTLimitations
XSThasthefollowinglimitations:
•XSTcannotpipelinehardwareMultipliers(implementationusingMULT18X18S
resource)
•XSTcannotpipelineMultipliersifregisterscontainasyncset/resetorsyncreset
signals.XSTcanpipelineifregisterscontainsyncresetsignals.
PipelinedMultipliersLogFile
FollowingisaPipelinedMultipliersLogFileExample.
PipelinedMultipliersLogFileExample
====================================================================
*HDLSynthesis*
====================================================================
SynthesizingUnit<multipliers_2>.
Relatedsourcefileis"multipliers_2.vhd".
Found36-bitregisterforsignal<MULT>.
Found18-bitregisterforsignal<a_in>.
Found18-bitregisterforsignal<b_in>.
Found18x18-bitmultiplierforsignal<mult_res>.
Found36-bitregisterforsignal<pipe_1>.
Found36-bitregisterforsignal<pipe_2>.
Found36-bitregisterforsignal<pipe_3>.
Summary:
inferred180D-typeflip-flop(s).
inferred1Multiplier(s).
Unit<multipliers_2>synthesized.
...
====================================================================
*AdvancedHDLSynthesis*
====================================================================
Synthesizing(advanced)Unit<multipliers_2>.
Foundpipelinedmultiplieronsignal<mult_res>:
-4pipelinelevel(s)foundinaregisterconnectedtothe
multipliermacrooutput.
Pushingregister(s)intothemultipliermacro.
INFO:Xst-HDLADVISOR-Youcanimprovetheperformanceofthe
multiplierMmult_mult_resbyadding1registerlevel(s).
Unit<multipliers_2>synthesized(advanced).
====================================================================
HDLSynthesisReport
MacroStatistics
#Multipliers:1
18x18-bitregisteredmultiplier:1
====================================================================
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Chapter3:XSTHDLCodingTechniques
PipelinedMultipliersRelatedConstraints
•UseDSP48(USE_DSP48)
•DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
•Keep(KEEP)
•MultiplierStyle(MULT_STYLE)
PipelinedMultipliersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
PipelinedMultiplier(Outside,Single)Diagram
PipelinedMultiplier(Outside,Single)PinDescriptions
IOPinsDescription
clkPositive-EdgeClock
A,BMULTOperands
MULTMULTResult
PipelinedMultiplier(Outside,Single)VHDLCodingExample
--
--Pipelinedmultiplier
--Themultiplicationoperationplacedoutsidethe
--processblockandthepipelinestagesrepresented
--assingleregisters.
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitymultipliers_2is
generic(A_port_size:integer:=18;
B_port_size:integer:=18);
port(clk:instd_logic;
A:inunsigned(A_port_size-1downto0);
B:inunsigned(B_port_size-1downto0);
MULT:outunsigned((A_port_size+B_port_size-1)downto0));
attributemult_style:string;
attributemult_styleofmultipliers_2:entityis"pipe_lut";
endmultipliers_2;
architecturebehofmultipliers_2is
signala_in,b_in:unsigned(A_port_size-1downto0);
signalmult_res:unsigned((A_port_size+B_port_size-1)downto0);
signalpipe_1,
pipe_2,
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pipe_3:unsigned((A_port_size+B_port_size-1)downto0);
begin
mult_res<=a_in*b_in;
process(clk)
begin
if(clk’eventandclk=’1’)then
a_in<=A;b_in<=B;
pipe_1<=mult_res;
pipe_2<=pipe_1;
pipe_3<=pipe_2;
MULT<=pipe_3;
endif;
endprocess;
endbeh;
PipelinedMultiplier(Outside,Single)VerilogCodingExample
//
//Pipelinedmultiplier
//Themultiplicationoperationplacedoutsidethe
//alwaysblockandthepipelinestagesrepresented
//assingleregisters.
//
(*mult_style="pipe_lut"*)
modulev_multipliers_2(clk,A,B,MULT);
inputclk;
input[17:0]A;
input[17:0]B;
output[35:0]MULT;
reg[35:0]MULT;
reg[17:0]a_in,b_in;
wire[35:0]mult_res;
reg[35:0]pipe_1,pipe_2,pipe_3;
assignmult_res=a_in*b_in;
always@(posedgeclk)
begin
a_in<=A;b_in<=B;
pipe_1<=mult_res;
pipe_2<=pipe_1;
pipe_3<=pipe_2;
MULT<=pipe_3;
end
endmodule
PipelinedMultiplier(Inside,Single)PinDescriptions
IOPinsDescription
clkPositive-EdgeClock
A,BMULTOperands
MULTMULTResult
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PipelinedMultiplier(Inside,Single)VHDLCodingExample
--
--Pipelinedmultiplier
--Themultiplicationoperationplacedinsidethe
--processblockandthepipelinestagesrepresented
--assingleregisters.
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitymultipliers_3is
generic(A_port_size:integer:=18;
B_port_size:integer:=18);
port(clk:instd_logic;
A:inunsigned(A_port_size-1downto0);
B:inunsigned(B_port_size-1downto0);
MULT:outunsigned((A_port_size+B_port_size-1)downto0));
attributemult_style:string;
attributemult_styleofmultipliers_3:entityis"pipe_lut";
endmultipliers_3;
architecturebehofmultipliers_3is
signala_in,b_in:unsigned(A_port_size-1downto0);
signalmult_res:unsigned((A_port_size+B_port_size-1)downto0);
signalpipe_2,
pipe_3:unsigned((A_port_size+B_port_size-1)downto0);
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
a_in<=A;b_in<=B;
mult_res<=a_in*b_in;
pipe_2<=mult_res;
pipe_3<=pipe_2;
MULT<=pipe_3;
endif;
endprocess;
endbeh;
PipelinedMultiplier(Inside,Single)VerilogCodingExample
//
//Pipelinedmultiplier
//Themultiplicationoperationplacedinsidethe
//processblockandthepipelinestagesarerepresented
//assingleregisters.
//
(*mult_style="pipe_lut"*)
modulev_multipliers_3(clk,A,B,MULT);
inputclk;
input[17:0]A;
input[17:0]B;
output[35:0]MULT;
reg[35:0]MULT;
reg[17:0]a_in,b_in;
reg[35:0]mult_res;
reg[35:0]pipe_2,pipe_3;
always@(posedgeclk)
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begin
a_in<=A;b_in<=B;
mult_res<=a_in*b_in;
pipe_2<=mult_res;
pipe_3<=pipe_2;
MULT<=pipe_3;
end
endmodule
PipelinedMultiplier(Outside,Shift)PinDescriptions
IOPinsDescription
clkPositive-EdgeClock
A,BMULTOperands
MULTMULTResult
PipelinedMultiplier(Outside,Shift)VHDLCodingExample
--
--Pipelinedmultiplier
--Themultiplicationoperationplacedoutsidethe
--processblockandthepipelinestagesrepresented
--asshiftregisters.
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitymultipliers_4is
generic(A_port_size:integer:=18;
B_port_size:integer:=18);
port(clk:instd_logic;
A:inunsigned(A_port_size-1downto0);
B:inunsigned(B_port_size-1downto0);
MULT:outunsigned((A_port_size+B_port_size-1)downto0));
attributemult_style:string;
attributemult_styleofmultipliers_4:entityis"pipe_lut";
endmultipliers_4;
architecturebehofmultipliers_4is
signala_in,b_in:unsigned(A_port_size-1downto0);
signalmult_res:unsigned((A_port_size+B_port_size-1)downto0);
typepipe_reg_typeisarray(2downto0)ofunsigned((A_port_size+B_port_size-1)downto0);
signalpipe_regs:pipe_reg_type;
begin
mult_res<=a_in*b_in;
process(clk)
begin
if(clk’eventandclk=’1’)then
a_in<=A;b_in<=B;
pipe_regs<=mult_res&pipe_regs(2downto1);
MULT<=pipe_regs(0);
endif;
endprocess;
endbeh;
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PipelinedMultiplier(Outside,Shift)VerilogCodingExample
//
//Pipelinedmultiplier
//Themultiplicationoperationplacedoutsidethe
//alwaysblockandthepipelinestagesrepresented
//asshiftregisters.
//
(*mult_style="pipe_lut"*)
modulev_multipliers_4(clk,A,B,MULT);
inputclk;
input[17:0]A;
input[17:0]B;
output[35:0]MULT;
reg[35:0]MULT;
reg[17:0]a_in,b_in;
wire[35:0]mult_res;
reg[35:0]pipe_regs[2:0];
integeri;
assignmult_res=a_in*b_in;
always@(posedgeclk)
begin
a_in<=A;b_in<=B;
pipe_regs[2]<=mult_res;
for(i=0;i<=1;i=i+1)pipe_regs[i]<=pipe_regs[i+1];
MULT<=pipe_regs[0];
end
endmodule
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Chapter3:XSTHDLCodingTechniques
MultiplyAdder/SubtractorsHDLCodingTechniques
ThissectiondiscussesMultiplyAdder/SubtractorsHDLCodingTechniques,and
includes:
•AboutMultiplyAdder/Subtractors
•MultiplyAdder/SubtractorsinVirtex-4DevicesandVirtex-5Devices
•MultiplyAdder/SubtractorsLogFile
•MultiplyAdder/SubtractorsRelatedConstraints
•MultiplyAdder/SubtractorsCodingExamples
AboutMultiplyAdder/Subtractors
TheMultiplyAdder/Subtractormacroisacomplexmacroconsistingofseveralbasic
macrossuchas:
•Multipliers
•Adder/subtractors
•Registers
TherecognitionofthiscomplexmacroenablesXSTtoimplementitondedicatedDSP48
resourcesinthefollowingdevices:
•Virtex®-4
•Virtex-5
MultiplyAdder/SubtractorsinVirtex-4DevicesandVirtex-5Devices
ThissectiondiscussesMultiplyAdder/SubtractorsinVirtex®-4DevicesandVirtex-5
Devices,andincludes:
•XSTRegisteredMacroSupport
•XSTDSP48BlockSupport
•MacroImplementationonDSP48Blocks
•MaximumMacroConguration
XSTRegisteredMacroSupport
XSTsupportstheregisteredversionofthismacroandcanpushupto:
•Twolevelsofinputregistersonmultiplierinputs
•OneregisterlevelontheAdder/Subtractorinput
•OnelevelofoutputregisterintotheDSP48block
IftheCarryInorAdd/Suboperationselectorsareregistered,XSTpushestheseregisters
intotheDSP48.Inaddition,themultiplicationoperationcouldberegisteredaswell.
XSTDSP48BlockSupport
XSTcanimplementamultiplyadder/subtractorinaDSP48blockifitsimplementation
requiresonlyasingleDSP48resource.IfthemacroexceedsthelimitsofasingleDSP48,
XSTprocessesitastwoseparateMultiplierandAdder/Subtractormacros,making
independentdecisionsoneachmacro.
Formoreinformation,see:
•MultipliersHardwareDescriptionLanguage(HDL)CodingTechniques
•Adders,Subtractors,andAdders/SubtractorsHardwareDescriptionLanguage
(HDL)CodingTechniques
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MacroImplementationonDSP48Blocks
MacroimplementationonDSP48blocksiscontrolledbyUseDSP48(USE_DSP48)witha
defaultvalueofauto.Inthismode,XSTimplementsmultiplyadder/subtractorstaking
intoaccountDSP48resourcesinthedevice.
Inautomode,useDSPUtilizationRatio(DSP_UTILIZATION_RATIO)tocontrolDSP48
resourcesforthesynthesis.Bydefault,XSTtriestoutilizeallavailableDSP48resources.
Formoreinformation,see:
DSP48BlockResources
MaximumMacroConfiguration
Todeliverthebestperformance,XSTbydefaulttriestoinferandimplementthe
maximummacroconguration,includingasmanyregistersintheDSP48aspossible.
UseKeep(KEEP)toshapeamacroinaspecicway.Forexample,toexcludetherst
registerstagefromtheDSP48,placeKeep(KEEP)constraintsontheoutputsofthese
registers.
MultiplyAdder/SubtractorsLogFile
Inthelogle,XSTreportsthedetailsofinferredmultipliers,adder/subtractorsand
registersattheHDLSynthesisstep.Thecompositionofmultiplyadder/subtractor
macroshappensattheAdvancedHDLSynthesisstep.XSTreportsinformationabout
inferredMACs,becausetheyareimplementedwithintheMACimplementation
mechanism.
MultiplyAdder/SubtractorsLogFileExample
====================================================================
*HDLSynthesis*
====================================================================
SynthesizingUnit<multipliers_6>.
Relatedsourcefileis"multipliers_6.vhd".
Found8-bitregisterforsignal<A_reg1>.
Found8-bitregisterforsignal<A_reg2>.
Found8-bitregisterforsignal<B_reg1>.
Found8-bitregisterforsignal<B_reg2>.
Found8x8-bitmultiplierforsignal<mult>.
Found16-bitaddsubforsignal<multaddsub>.
Summary:
inferred32D-typeflip-flop(s).
inferred1Adder/Subtractor(s).
inferred1Multiplier(s).
Unit<multipliers_6>synthesized.
...
====================================================================
*AdvancedHDLSynthesis*
====================================================================
...
Synthesizing(advanced)Unit<Mmult_mult>.
Multiplier<Mmult_mult>inblock<multipliers_6>andadder/subtractor
<Maddsub_multaddsub>inblock<multipliers_6>arecombinedintoa
MAC<Mmac_Maddsub_multaddsub>.
ThefollowingregistersarealsoabsorbedbytheMAC:<A_reg2>inblock
<multipliers_6>,<A_reg1>inblock<multipliers_6>,<B_reg2>in
block<multipliers_6>,<B_reg1>inblock<multipliers_6>.
Unit<Mmult_mult>synthesized(advanced).
====================================================================
HDLSynthesisReport
MacroStatistics
#MACs:1
8x8-to-16-bitMAC:1
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====================================================================
MultiplyAdder/SubtractorsRelatedConstraints
•UseDSP48(USE_DSP48)
•DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
•Keep(KEEP)
MultiplyAdder/SubtractorsCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
MultiplierAdderWith2RegisterLevelsonMultiplierInputs
Diagram
MultiplierAdderWith2RegisterLevelsonMultiplierInputsPin
Descriptions
IOPinsDescription
clkPositive-EdgeClock
A,B,CMULT-AddOperands
RESMULT-AddResult
MultiplierAdderWith2RegisterLevelsonMultiplierInputsVHDLCoding
Example
--
--MultiplierAdderwith2RegisterLevelsonMultiplierInputs
--
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitymultipliers_5is
generic(p_width:integer:=8);
port(clk:instd_logic;
A,B,C:instd_logic_vector(p_width-1downto0);
RES:outstd_logic_vector(p_width*2-1downto0));
endmultipliers_5;
architecturebehofmultipliers_5is
signalA_reg1,A_reg2,
B_reg1,B_reg2:std_logic_vector(p_width-1downto0);
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signalmultaddsub:std_logic_vector(p_width*2-1downto0);
begin
multaddsub<=A_reg2*B_reg2+C;
process(clk)
begin
if(clk’eventandclk=’1’)then
A_reg1<=A;A_reg2<=A_reg1;
B_reg1<=B;B_reg2<=B_reg1;
endif;
endprocess;
RES<=multaddsub;
endbeh;
MultiplierAdderWith2RegisterLevelsonMultiplierInputsVerilogCoding
Example
//
//MultiplierAdderwith2RegisterLevelsonMultiplierInputs
//
modulev_multipliers_5(clk,A,B,C,RES);
inputclk;
input[7:0]A;
input[7:0]B;
input[7:0]C;
output[15:0]RES;
reg[7:0]A_reg1,A_reg2,B_reg1,B_reg2;
wire[15:0]multaddsub;
always@(posedgeclk)
begin
A_reg1<=A;A_reg2<=A_reg1;
B_reg1<=B;B_reg2<=B_reg1;
end
assignmultaddsub=A_reg2*B_reg2+C;
assignRES=multaddsub;
endmodule
MultiplierAdder/SubtractorWith2RegisterLevelsOnMultiplier
InputsDiagram
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MultiplierAdder/SubtractorWith2RegisterLevelsOnMultiplier
InputsPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
add_subAddSubSelector
A,B,CMULT-AddSubOperands
RESMULT-AddSubResult
MultiplierAdder/SubtractorWith2RegisterLevelsOnMultiplierInputs
VHDLCodingExample
--
--MultiplierAdder/Subtractorwith
--2RegisterLevelsonMultiplierInputs
--
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitymultipliers_6is
generic(p_width:integer:=8);
port(clk,add_sub:instd_logic;
A,B,C:instd_logic_vector(p_width-1downto0);
RES:outstd_logic_vector(p_width*2-1downto0));
endmultipliers_6;
architecturebehofmultipliers_6is
signalA_reg1,A_reg2,
B_reg1,B_reg2:std_logic_vector(p_width-1downto0);
signalmult,multaddsub:std_logic_vector(p_width*2-1downto0);
begin
mult<=A_reg2*B_reg2;
multaddsub<=C+multwhenadd_sub=’1’elseC-mult;
process(clk)
begin
if(clk’eventandclk=’1’)then
A_reg1<=A;A_reg2<=A_reg1;
B_reg1<=B;B_reg2<=B_reg1;
endif;
endprocess;
RES<=multaddsub;
endbeh;
MultiplierAdder/SubtractorWith2RegisterLevelsOnMultiplierInputs
VerilogCodingExample
//
//MultiplierAdder/Subtractorwith
//2RegisterLevelsonMultiplierInputs
//
modulev_multipliers_6(clk,add_sub,A,B,C,RES);
inputclk,add_sub;
input[7:0]A;
input[7:0]B;
input[7:0]C;
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output[15:0]RES;
reg[7:0]A_reg1,A_reg2,B_reg1,B_reg2;
wire[15:0]mult,multaddsub;
always@(posedgeclk)
begin
A_reg1<=A;A_reg2<=A_reg1;
B_reg1<=B;B_reg2<=B_reg1;
end
assignmult=A_reg2*B_reg2;
assignmultaddsub=add_sub?C+mult:C-mult;
assignRES=multaddsub;
endmodule
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MultiplyAccumulateHDLCodingTechniques
ThissectiondiscussesMultiplyAccumulateHDLCodingTechniques,andincludes:
•AboutMultiplyAccumulate
•MultiplyAccumulateinVirtex-4DevicesandVirtex-5Devices
•MultiplyAccumulateLogFile
•MultiplyAccumulateRelatedConstraints
•MultiplyAccumulateCodingExamples
AboutMultiplyAccumulate
TheMultiplyAccumulatemacroisacomplexmacroconsistingofseveralbasicmacros
suchas:
•Multipliers
•Accumulators
•Registers
TherecognitionofthiscomplexmacroenablesXSTtoimplementitondedicatedDSP48
resourcesinthefollowingdevices:
•Virtex®-4
•Virtex-5
MultiplyAccumulateinVirtex-4DevicesandVirtex-5Devices
ThissectiondiscussesMultiplyAccumulateinVirtex®-4DevicesandVirtex-5Devices,
andincludes:
•XSTRegisteredMacroSupport
•XSTDSP48BlockSupport
•MacroImplementationonDSP48Blocks
•MaximumMacroConguration
Formoreinformation,see:
•MultipliersHDLCodingTechniques
•AccumulatorsHDLCodingTechniques
XSTRegisteredMacroSupport
XSTsupportstheregisteredversionofthismacro,andcanpushupto2levelsofinput
registersintotheDSP48block.IfAdder/Subtractoroperationselectorsareregistered,
XSTpushestheseregistersintotheDSP48.Inaddition,themultiplicationoperation
couldberegisteredaswell.
XSTDSP48BlockSupport
XSTcanimplementamultiplyaccumulateinaDSP48blockifitsimplementation
requiresonlyasingleDSP48resource.Ifthemacroexceedsthelimitsofasingle
DSP48,XSTprocessesitastwoseparateMultiplierandAccumulatemacros,making
independentdecisionsoneachmacro.
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MacroImplementationonDSP48Blocks
MacroimplementationonDSP48blocksiscontrolledbytheUseDSP48(USE_DSP48)
constraintorcommandlineoption,withadefaultvalueofauto.Inautomode,XST
implementsmultiplyaccumulatetakingintoaccountavailableDSP48resourcesinthe
device.
Inautomode,useDSPUtilizationRatio(DSP_UTILIZATION_RATIO)tocontrol
DSP48resources.XSTtriestoutilizeasmanyDSP48resourcesaspossible.Formore
information,seeDSP48BlockResources.
MaximumMacroConfiguration
Todeliverthebestperformance,XSTbydefaulttriestoinferandimplementthe
maximummacroconguration,includingasmanyregistersintheDSP48aspossible.
Toshapeamacroinaspecicway ,usetheKeep(KEEP)constraint.Forexample,to
excludetherstregisterstagefromtheDSP48,placeKeep(KEEP)constraintsonthe
outputsoftheseregisters.
MultiplyAccumulateLogFile
XSTreportsthefollowinginformationintheMultiplyAccumulateLogFile.
StepReport
HDLSynthesisDetailsofinferredmultipliers,accumulators
andregisters
AdvancedHDLSynthesisCompositionofmultiplyaccumulatemacros
MultiplyAccumulateLogFileExample
====================================================================
*HDLSynthesis*
====================================================================
...
SynthesizingUnit<multipliers_7a>.
Relatedsourcefileis"multipliers_7a.vhd".
Found8x8-bitmultiplierforsignal<$n0002>createdatline28.
Found16-bitupaccumulatorforsignal<accum>.
Found16-bitregisterforsignal<mult>.
Summary:
inferred1Accumulator(s).
inferred16D-typeflip-flop(s).
inferred1Multiplier(s).
Unit<multipliers_7a>synthesized....
====================================================================
*AdvancedHDLSynthesis*
====================================================================
...
Synthesizing(advanced)Unit<Mmult__n0002>.
Multiplier<Mmult__n0002>inblock<multipliers_7a>andaccumulator
<accum>inblock<multipliers_7a>arecombinedintoaMAC<Mmac_accum>.
ThefollowingregistersarealsoabsorbedbytheMAC:<mult>inblock
<multipliers_7a>.Unit<Mmult__n0002>synthesized(advanced).
====================================================================
HDLSynthesisReport
MacroStatistics
#MACs:1
8x8-to-16-bitMAC:1
====================================================================
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MultiplyAccumulateRelatedConstraints
•UseDSP48(USE_DSP48)
•DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
•Keep(KEEP)
MultiplyAccumulateCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
MultiplierUpAccumulateWithRegisterAfterMultiplication
Diagram
MultiplierUpAccumulateWithRegisterAfterMultiplicationPin
Descriptions
IOPinsDescription
clkPositive-EdgeClock
resetSynchronousReset
A,BMACOperands
RESMACResult
MultiplierUpAccumulateWithRegisterAfterMultiplicationVHDLCoding
Example
--
--MultiplierUpAccumulatewithRegisterAfterMultiplication
--
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitymultipliers_7ais
generic(p_width:integer:=8);
port(clk,reset:instd_logic;
A,B:instd_logic_vector(p_width-1downto0);
RES:outstd_logic_vector(p_width*2-1downto0));
endmultipliers_7a;
architecturebehofmultipliers_7ais
signalmult,accum:std_logic_vector(p_width*2-1downto0);
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begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(reset=’1’)then
accum<=(others=>’0’);
mult<=(others=>’0’);
else
accum<=accum+mult;
mult<=A*B;
endif;
endif;
endprocess;
RES<=accum;
endbeh;
MultiplierUpAccumulateWithRegisterAfterMultiplicationVerilogCoding
Example
//
//MultiplierUpAccumulatewithRegisterAfterMultiplication
//
modulev_multipliers_7a(clk,reset,A,B,RES);
inputclk,reset;
input[7:0]A;
input[7:0]B;
output[15:0]RES;
reg[15:0]mult,accum;
always@(posedgeclk)
begin
if(reset)
mult<=16’b0000000000000000;
else
mult<=A*B;
end
always@(posedgeclk)
begin
if(reset)
accum<=16’b0000000000000000;
else
accum<=accum+mult;
end
assignRES=accum;
endmodule
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MultiplierUp/DownAccumulateWithRegisterAfterMultiplication
Diagram
MultiplierUp/DownAccumulateWithRegisterAfterMultiplication
PinDescriptions
IOPinsDescription
clkPositive-EdgeClock
resetSynchronousReset
add_subAddSubSelector
A,BMACOperands
RESMACResult
MultiplierUp/DownAccumulateWithRegisterAfterMultiplicationVHDL
CodingExample
--
--MultiplierUp/DownAccumulatewithRegister
--AfterMultiplication
--
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitymultipliers_7bis
generic(p_width:integer:=8);
port(clk,reset,add_sub:instd_logic;
A,B:instd_logic_vector(p_width-1downto0);
RES:outstd_logic_vector(p_width*2-1downto0));
endmultipliers_7b;
architecturebehofmultipliers_7bis
signalmult,accum:std_logic_vector(p_width*2-1downto0);
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(reset=’1’)then
accum<=(others=>’0’);
mult<=(others=>’0’);
else
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if(add_sub=’1’)then
accum<=accum+mult;
else
accum<=accum-mult;
endif;
mult<=A*B;
endif;
endif;
endprocess;
RES<=accum;
endbeh;
MultiplierUp/DownAccumulateWithRegisterAfterMultiplicationVerilog
CodingExample
//
//MultiplierUp/DownAccumulatewithRegister
//AfterMultiplication
//
modulev_multipliers_7b(clk,reset,add_sub,A,B,RES);
inputclk,reset,add_sub;
input[7:0]A;
input[7:0]B;
output[15:0]RES;
reg[15:0]mult,accum;
always@(posedgeclk)
begin
if(reset)
mult<=16’b0000000000000000;
else
mult<=A*B;
end
always@(posedgeclk)
begin
if(reset)
accum<=16’b0000000000000000;
else
if(add_sub)
accum<=accum+mult;
else
accum<=accum-mult;
end
assignRES=accum;
endmodule
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DividersHDLCodingTechniques
ThissectiondiscussesDividersHDLCodingTechniques,andincludes:
•AboutDividers
•DividersLogFile
•DividersRelatedConstraints
•DividersCodingExamples
AboutDividers
Dividersaresupportedonlywhenthedivisorisaconstantandisapowerof2.Inthat
case,theoperatorisimplementedasashifter.Otherwise,XSTissuesanerrormessage.
DividersLogFile
Whenyouimplementadividerwithaconstantwiththepowerof2,XSTdoesnotissue
anymessageduringtheMacroRecognitionstep.Ifthedividerdoesnotcorrespondto
thecasesupportedbyXST,thenXSTissuesthefollowingerrormessage:
...
ERROR:Xst:719-file1.vhd(Line172).
Operatorisnotsupportedyet:’DIVIDE’
...
DividersRelatedConstraints
None
DividersCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
DivisionbyConstant2DividerDiagram
DivisionbyConstant2DividerPinDescriptions
IOPinsDescription
DIDivisionOperands
DODivisionResult
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DivisionbyConstant2DividerVHDLCodingExample
--
--DivisionByConstant2
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitydivider_1is
port(DI:inunsigned(7downto0);
DO:outunsigned(7downto0));
enddivider_1;
architecturearchiofdivider_1is
begin
DO<=DI/2;
endarchi;
DivisionbyConstant2DividerVerilogCodingExample
//
//DivisionByConstant2
//
modulev_divider_1(DI,DO);
input[7:0]DI;
output[7:0]DO;
assignDO=DI/2;
endmodule
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ResourceSharingHDLCodingTechniques
ThissectiondiscussesResourceSharingHDLCodingTechniques,andincludes:
•AboutResourceSharing
•ResourceSharingLogFile
•ResourceSharingRelatedConstraints
•ResourceSharingCodingExamples
AboutResourceSharing
Thegoalofresourcesharing(alsoknownasfolding)istominimizethenumberof
operatorsandthesubsequentlogicinthesynthesizeddesign.Thisoptimizationisbased
ontheprinciplethattwosimilararithmeticresourcesmaybeimplementedasonesingle
arithmeticoperatoriftheyareneverusedatthesametime.XSTperformsbothresource
sharingand,ifrequired,reducesthenumberofmultiplexers.
XSTsupportsresourcesharingfor:
•Adders
•Subtractors
•Adders/subtractors
•Multipliers
Iftheoptimizationgoalisspeed,disablingresourcesharingmaygivebetterresults.To
improveclockfrequency ,Xilinx®recommendsdeactivatingresourcesharingatthe
AdvancedHDLSynthesisstep.
ResourceSharingLogFile
TheXSTloglereportsthetypeandsizeofrecognizedarithmeticblocksand
multiplexersduringtheMacroRecognitionstep.
ResourceSharingLogFileExample
...
SynthesizingUnit<addsub>.
Relatedsourcefileisresource_sharing_1.vhd.
Found8-bitaddsubforsignal<res>.
Found81-bit2-to-1multiplexers.
Summary:
inferred1Adder/Subtracter(s).
inferred8Multiplexer(s).
Unit<addsub>synthesized.
==============================
HDLSynthesisReport
MacroStatistics
#Multiplexers:1
2-to-1multiplexer:1
#Adders/Subtractors:1
8-bitaddsub:1
==============================
...
===================================================================
*AdvancedHDLSynthesis*
===================================================================
INFO:Xst-HDLADVISOR-Resourcesharinghasidentifiedthatsome
arithmeticoperationsinthisdesigncansharethesamephysicalresources
forreduceddeviceutilization.Forimprovedclockfrequencyyoumay
trytodisableresourcesharing.
...
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Chapter3:XSTHDLCodingTechniques
ResourceSharingRelatedConstraints
ResourceSharing(RESOURCE_SHARING)
ResourceSharingCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
ForthefollowingVHDLandVerilogexamples,XSTgivesthefollowingsolution.
ResourceSharingDiagram
ResourceSharingPinDescriptions
IOPinsDescription
A,B,COperands
OPEROperationSelector
RESDataOutput
ResourceSharingVHDLCodingExample
--
--ResourceSharing
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityresource_sharing_1is
port(A,B,C:instd_logic_vector(7downto0);
OPER:instd_logic;
RES:outstd_logic_vector(7downto0));
endresource_sharing_1;
architecturearchiofresource_sharing_1is
begin
RES<=A+BwhenOPER=’0’elseA-C;
endarchi;
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Chapter3:XSTHDLCodingTechniques
RAMsandROMsHDLCodingTechniques
ThissectiondiscussesRAMsandROMsHDLCodingTechniques,andincludes:
•AboutRAMsandROMs
•RAMsandROMsLogFile
•RAMsandROMsRelatedConstraints
•RAMsandROMsCodingExamples
•InitializingRAMCodingExamples
•InitializingRAMFromanExternalFileCodingExamples
AboutRAMsandROMs
ThissectiondiscussesAboutRAMsandROMs,andincludes:
•AutomaticRAMRecognition
•RAMsandROMswithNegativeAddresses
•TypesofInferredRAM
•BlockandDistributedRAM
•UnsupportedBlockRAMFeatures
•Speed-OrientedImplementation
•AdditionalXSTCapabilities
•AutomaticBRAMResourceControl
•SmallRAMsandROMs
•AvailableBRAMResources
AutomaticRAMRecognition
IfyoudonotwanttoinstantiateRAMprimitivestokeepyourHardwareDescription
Language(HDL)codearchitectureindependent,useXSTautomaticRAMrecognition.
XSTcaninferdistributedaswellasblockRAM.Itcoversthefollowingcharacteristics,
offeredbytheseRAMtypes:
•Synchronouswrite
•Writeenable
•RAMenable
•Asynchronousorsynchronousread
•Resetofthedataoutputlatches
•Dataoutputreset
•Single,dual,ormultiple-portread
•Single-portanddual-portwrite
•Paritybits
•BlockRamwithByte-WideWriteEnable
•Simpledual-portBRAM
RAMsandROMswithNegativeAddresses
XSTdoesnotsupportRAMsandROMswithnegativeaddresses.
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Chapter3:XSTHDLCodingTechniques
TypesofInferredRAM
ThetypeofInferredRAMdependsonitsdescription.
•RAMdescriptionswithanasynchronousreadgenerateadistributedRAMmacro.
•RAMdescriptionswithasynchronousreadgenerateablockRAMmacro.Insome
cases,ablockRAMmacrocanactuallybeimplementedwithdistributedRAM.The
decisionontheactualRAMimplementationisdonebythemacrogenerator.
BlockandDistributedRAM
IfagiventemplatecanbeimplementedusingBlockandDistributedRAM,XST
implementsBLOCKones.UsetheRAMStyle(RAM_STYLE)constrainttocontrolRAM
implementationandselectadesirableRAMtype.
Formoreinformation,see:
XSTDesignConstraints
UnsupportedBlockRAMFeatures
ThefollowingblockRAMfeaturesarenotsupported:
•Paritybits
•Differentaspectratiosoneachport
•Simpledual-portdistributedRAMs
•Quad-portdistributedRAMs
Speed-OrientedImplementation
XSTusesspeed-orientedimplementationtoimplementRAMsonBRAMresources.This
givesgoodresultsforspeed,butmayrequiremoreBRAMresourcesthanarea-oriented
implementation.XSTdoesnotsupportarea-orientedBRAMimplementation.Xilinx®
recommendstheCOREGenerator™softwareforarea-orientedimplementation.
Formoreinformation,see:
XSTFPGAOptimization
AdditionalXSTCapabilities
XSTcan:
•ImplementFiniteStateMachine(FSM)components.
Formoreinformation,see:
FiniteStateMachine(FSM)HDLCodingTechniques.
•MapgenerallogicontoblockRAMs
Formoreinformation,see:
MappingLogicOntoBlockRAM
AutomaticBRAMResourceControl
XSTautomaticallycontrolsBRAMresourcesonthetargetdevice.BRAMUtilization
Ratio(BRAM_UTILIZATION_RATIO)allowsyoutospecifythenumberofBRAM
blocksthatXSTmustnotexceedduringsynthesis.
SmallRAMsandROMs
UseRAMStyle(RAM_STYLE)andROMStyle(ROM_STYLE)toforceimplementation
ofsmallRAMsandROMsonBRAMresources.
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Chapter3:XSTHDLCodingTechniques
Toachievebetterdesignspeed,XSTimplementssmallRAMsandROMsusing
distributedresources.RAMsandROMsareconsideredsmalliftheirsizesfollowthe
rulesshowninthefollowingtable.
DevicesSize(bits)*Width(bits)
Virtex®-4<=512
Virtex-5<=512
AvailableBRAMResources
XSTcalculatestheavailableBRAMresourcesforinferenceusingthefollowingformula:
Total_Number_of_Available_BRAMs-Number_of_Reserved_BRAMs
where
Total_Number_of_Available_BRAMsisthenumberofBRAMsspeciedbytheBRAM
UtilizationRatio(BRAM_UTILIZATION_RATIO)constraint.Bydefaultitis100%.
TheNumberofReserved_BRAMsencapsulates:
•ThenumberofinstantiatedBRAMsintheHardwareDescriptionLanguage(HDL)
codefromtheUNISIMlibrary
•ThenumberofRAMwhichwereforcedtobeimplementedasBRAMsbytheRAM
Style(RAM_STYLE)andROMStyle(ROM_STYLE)constraints
•ThenumberofBRAMsgeneratedusingBRAMmappingoptimizations
(BRAM_MAP).
WherethereareavailableBRAMresources,XSTimplementsthelargestinferredRAMs
andROMsusingBRAM,andthesmallestondistributedresources.
IftheNumber_of_Reserved_BRAMsexceedsavailableresources,XSTimplements
themasblockRAMs,andallinferredRAMsareimplementedondistributedmemory.
Assoonasthisprocessiscompleted,XSTcanautomaticallypacktwosmallsingle-port
BRAMsinasingleBRAMprimitive.ThisoptimizationiscontrolledbyAutomatic
BRAMPacking(AUTO_BRAM_PACKING).Itisdisabledbydefault.
Formoreinformation,see:
•BRAMUtilizationRatio(BRAM_UTILIZATION_RATIO)
•AutomaticBRAMPacking(AUTO_BRAM_PACKING)
RAMsandROMsLogFile
TheXSTRAMsandROMsloglereportsthefollowing:
•TypeandsizeofrecognizedRAM
•CompleteinformationonitsI/Oports
StepsinRAMRecognition
StepXSTBehavior
HDLSynthesisRecognizesthepresenceofthememorystructureintheHardware
DescriptionLanguage(HDL)code
AdvancedHDL
Synthesis
Decideshowtoimplementaspecicmemory(thatis,whethertouse
BlockorDistributedmemoryresources)
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RAMsandROMsLogFileExample
=========================================================================
*HDLSynthesis*
=========================================================================
SynthesizingUnit<rams_16>.
Relatedsourcefileis"rams_16.vhd".
Found64x16-bitdual-portRAM<Mram_RAM>forsignal<RAM>.
Found16-bitregisterforsignal<doa>.
Found16-bitregisterforsignal<dob>.
Summary:
inferred1RAM(s).
inferred32D-typeflip-flop(s).
Unit<rams_16>synthesized.
=========================================================================
HDLSynthesisReport
MacroStatistics
#RAMs:1
64x16-bitdual-portRAM:1
#Registers:2
16-bitregister:2
=========================================================================
=========================================================================
*AdvancedHDLSynthesis*
=========================================================================
Synthesizing(advanced)Unit<rams_16>.
INFO:Xst-TheRAM<Mram_RAM>willbeimplementedasaBLOCKRAM,absorbing
thefollowingregister(s):<doa><dob>
-----------------------------------------------------------------------
|ram_type|Block||
-----------------------------------------------------------------------
|PortA|
|aspectratio|64-wordx16-bit||
|mode|write-first||
|clkA|connectedtosignal<clka>|rise|
|enA|connectedtosignal<ena>|high|
|weA|connectedtointernal<wea>|high|
|addrA|connectedtosignal<addra>||
|diA|connectedtointernal<dia>||
|doA|connectedtosignal<doa>||
-----------------------------------------------------------------------
|optimization|speed||
=========================================================================
-----------------------------------------------------------------------
|ram_type|Block||
-----------------------------------------------------------------------
|PortB|
|aspectratio|64-wordx16-bit||
|mode|write-first||
|clkB|connectedtosignal<clkb>|rise|
|enB|connectedtosignal<enb>|high|
|weB|connectedtointernal<web>|high|
|addrB|connectedtosignal<addrb>||
|diB|connectedtointernal<dib>||
|doB|connectedtosignal<dob>||
-----------------------------------------------------------------------
|optimization|speed||
=========================================================================
-----------------------------------------------------------------------
Unit<rams_16>synthesized(advanced).
=========================================================================
AdvancedHDLSynthesisReport
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MacroStatistics
#RAMs:1
64x16-bitdual-portblockRAM:1
=========================================================================
RAMsandROMsRelatedConstraints
•BRAMUtilizationRatio(BRAM_UTILIZATION_RATIO)
•AutomaticBRAMPacking(AUTO_BRAM_PACKING)
•RAMExtraction(RAM_EXTRACT)
•RAMStyle(RAM_STYLE)
•ROMExtraction(ROM_EXTRACT)
•ROMStyle(ROM_STYLE)
XSTacceptsLOCandRLOCconstraintsoninferredRAMsthatcanbeimplemented
inasingleblockRAMprimitive.TheLOCandRLOCconstraintsarepropagated
totheNGCnetlist.
RAMsandROMsCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
SeeAlso:
InitializingRAMCodingExamples
InitializingRAMFromanExternalFileCodingExamples
AboutRAMsandROMsCodingExamples
BlockRAMresourcesinthefollowingdevicesofferdifferentread/writesynchronization
modes:
•Virtex®-4
•Virtex-5
•Spartan®-3
•Spartan-3E
•Spartan-3A
Thefollowingcodingexamplesdescribeasingle-portblockRAM.Youcandeduce
descriptionsofdual-portblockRAMsfromtheseexamples.Dual-portblockRAMs
canbeconguredwithadifferentread/writemodeoneachport.Inferencesupports
thiscapability.
Thistablesummarizessupportforread/writemodesaccordingtothetargeteddevices
andhowXSThandlesit.
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Chapter3:XSTHDLCodingTechniques
SupportForRead/WriteModes
DevicesInferredModesBehavior
Spartan-3
Spartan-3E
Spartan-3A
Virtex-4
Virtex-5
write-rst
read-rst
no-change
Macroinferenceandgeneration
AttachadequateWRITE_MODE,
WRITE_MODE_A,WRITE_MODE_B
constraintstogeneratedblockRAMs
inNCF
CPLDnoneRAMinferencecompletelydisabled
Single-PortRAMinRead-FirstModeDiagram
Single-PortRAMinRead-FirstModePinDescriptions
IOPinsDescription
clkPositive-EdgeClock
weSynchronousWriteEnable(active-High)
enClockEnable
addrRead/WriteAddress
diDataInput
doDataOutput
Single-PortRAMinRead-FirstModeVHDLCodingExampleOne
--
--Read-FirstMode
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_01is
port(clk:instd_logic;
we:instd_logic;
en:instd_logic;
addr:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do:outstd_logic_vector(15downto0));
endrams_01;
architecturesynoframs_01is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
begin
process(clk)
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begin
ifclk’eventandclk=’1’then
ifen=’1’then
ifwe=’1’then
RAM(conv_integer(addr))<=di;
endif;
do<=RAM(conv_integer(addr));
endif;
endif;
endprocess;
endsyn;
Single-PortRAMinRead-FirstModeVerilogCodingExampleOne
//
//Read-FirstMode
//
modulev_rams_01(clk,en,we,addr,di,do);
inputclk;
inputwe;
inputen;
input[5:0]addr;
input[15:0]di;
output[15:0]do;
reg[15:0]RAM[63:0];
reg[15:0]do;
always@(posedgeclk)
begin
if(en)
begin
if(we)
RAM[addr]<=di;
do<=RAM[addr];
end
end
endmodule
Single-PortRAMinWrite-FirstModeDiagram
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Single-PortRAMinWrite-FirstModePinDescriptions
IOPinsDescription
clkPositive-EdgeClock
weSynchronousWriteEnable(active-High)
enClockEnable
addrRead/WriteAddress
diDataInput
doDataOutput
Single-PortRAMinWrite-FirstModeVHDLCodingExampleOne
--
--Write-FirstMode(template1)
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_02ais
port(clk:instd_logic;
we:instd_logic;
en:instd_logic;
addr:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do:outstd_logic_vector(15downto0));
endrams_02a;
architecturesynoframs_02ais
typeram_typeisarray(63downto0)
ofstd_logic_vector(15downto0);
signalRAM:ram_type;
begin
process(clk)
begin
ifclk’eventandclk=’1’then
ifen=’1’then
ifwe=’1’then
RAM(conv_integer(addr))<=di;
do<=di;
else
do<=RAM(conv_integer(addr));
endif;
endif;
endif;
endprocess;
endsyn;
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Chapter3:XSTHDLCodingTechniques
Single-PortRAMinWrite-FirstModeVHDLCodingExampleTwo
--
--Write-FirstMode(template2)
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_02bis
port(clk:instd_logic;
we:instd_logic;
en:instd_logic;
addr:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do:outstd_logic_vector(15downto0));
endrams_02b;
architecturesynoframs_02bis
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
signalread_addr:std_logic_vector(5downto0);
begin
process(clk)
begin
ifclk’eventandclk=’1’then
ifen=’1’then
ifwe=’1’then
ram(conv_integer(addr))<=di;
endif;
read_addr<=addr;
endif;
endif;
endprocess;
do<=ram(conv_integer(read_addr));
endsyn;
Single-PortRAMInWrite-FirstModeVerilogCodingExampleOne
//
//Write-FirstMode(template1)
//
modulev_rams_02a(clk,we,en,addr,di,do);
inputclk;
inputwe;
inputen;
input[5:0]addr;
input[15:0]di;
output[15:0]do;
reg[15:0]RAM[63:0];
reg[15:0]do;
always@(posedgeclk)
begin
if(en)
begin
if(we)
begin
RAM[addr]<=di;
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do<=di;
end
else
do<=RAM[addr];
end
end
endmodule
Single-PortRAMInWrite-FirstModeVerilogCodingExampleTwo
//
//Write-FirstMode(template2)
//
modulev_rams_02b(clk,we,en,addr,di,do);
inputclk;
inputwe;
inputen;
input[5:0]addr;
input[15:0]di;
output[15:0]do;
reg[15:0]RAM[63:0];
reg[5:0]read_addr;
always@(posedgeclk)
begin
if(en)
begin
if(we)
RAM[addr]<=di;
read_addr<=addr;
end
end
assigndo=RAM[read_addr];
endmodule
Single-PortRAMInNo-ChangeModeDiagram
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Single-PortRAMInNo-ChangeModePinDescriptions
IOPinsDescription
clkPositive-EdgeClock
weSynchronousWriteEnable(active-High)
enClockEnable
addrRead/WriteAddress
diDataInput
doDataOutput
Single-PortRAMInNo-ChangeModeVHDLCodingExampleTwo
--
--No-ChangeMode(template1)
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_03is
port(clk:instd_logic;
we:instd_logic;
en:instd_logic;
addr:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do:outstd_logic_vector(15downto0));
endrams_03;
architecturesynoframs_03is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
begin
process(clk)
begin
ifclk’eventandclk=’1’then
ifen=’1’then
ifwe=’1’then
RAM(conv_integer(addr))<=di;
else
do<=RAM(conv_integer(addr));
endif;
endif;
endif;
endprocess;
endsyn;
Single-PortRAMInNo-ChangeModeVerilogCodingExampleTwo
//
//No-ChangeMode(template1)
//
modulev_rams_03(clk,we,en,addr,di,do);
inputclk;
inputwe;
inputen;
input[5:0]addr;
input[15:0]di;
output[15:0]do;
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reg[15:0]RAM[63:0];
reg[15:0]do;
always@(posedgeclk)
begin
if(en)
begin
if(we)
RAM[addr]<=di;
else
do<=RAM[addr];
end
end
endmodule
ThefollowingdescriptionsaredirectlymappableontodistributedRAMonly.
Single-PortRAMWithAsynchronousReadDiagram
Single-PortRAMWithAsynchronousReadPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
weSynchronousWriteEnable(active-High)
aRead/WriteAddress
diDataInput
doDataOutput
Single-PortRAMWithAsynchronousReadVHDLCodingExample
--
--Single-PortRAMwithAsynchronousRead
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_04is
port(clk:instd_logic;
we:instd_logic;
a:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do:outstd_logic_vector(15downto0));
endrams_04;
architecturesynoframs_04is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
begin
process(clk)
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begin
if(clk’eventandclk=’1’)then
if(we=’1’)then
RAM(conv_integer(a))<=di;
endif;
endif;
endprocess;
do<=RAM(conv_integer(a));
endsyn;
Single-PortRAMWithAsynchronousReadVerilogCodingExample
//
//Single-PortRAMwithAsynchronousRead
//
modulev_rams_04(clk,we,a,di,do);
inputclk;
inputwe;
input[5:0]a;
input[15:0]di;
output[15:0]do;
reg[15:0]ram[63:0];
always@(posedgeclk)begin
if(we)
ram[a]<=di;
end
assigndo=ram[a];
endmodule
Thefollowingdescriptionimplementsatruesynchronousread.Atruesynchronous
readisthesynchronizationmechanisminVirtexdeviceblockRAMs,wheretheread
addressisregisteredontheRAMclockedge.Suchdescriptionsaredirectlymappable
ontoblockRAM,asshowninthediagrambelow.Thesamedescriptionscanalsobe
mappedontoDistributedRAM.
Single-PortRAMWithSynchronousRead(ReadThrough)
Diagram
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Single-PortRAMWithSynchronousRead(ReadThrough)Pin
Descriptions
IOPinsDescription
clkPositive-EdgeClock
weSynchronousWriteEnable(active-High)
aRead/WriteAddress
diDataInput
doDataOutput
Single-PortRAMWithSynchronousRead(ReadThrough)VHDLCoding
Example
--
--Single-PortRAMwithSynchronousRead(ReadThrough)
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_07is
port(clk:instd_logic;
we:instd_logic;
a:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do:outstd_logic_vector(15downto0));
endrams_07;
architecturesynoframs_07is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
signalread_a:std_logic_vector(5downto0);
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(we=’1’)then
RAM(conv_integer(a))<=di;
endif;
read_a<=a;
endif;
endprocess;
do<=RAM(conv_integer(read_a));
endsyn;
Single-PortRAMWithSynchronousRead(ReadThrough)VerilogCoding
Example
//
//Single-PortRAMwithSynchronousRead(ReadThrough)
//
modulev_rams_07(clk,we,a,di,do);
inputclk;
inputwe;
input[5:0]a;
input[15:0]di;
output[15:0]do;
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reg[15:0]ram[63:0];
reg[5:0]read_a;
always@(posedgeclk)begin
if(we)
ram[a]<=di;
read_a<=a;
end
assigndo=ram[read_a];
endmodule
Single-PortRAMWithEnableDiagram
Single-PortRAMWithEnablePinDescriptions
IOPinsDescription
clkPositive-EdgeClock
enGlobalEnable
weSynchronousWriteEnable(active-High)
aRead/WriteAddress
diDataInput
doDataOutput
Single-PortRAMWithEnableVHDLCodingExample
--
--Single-PortRAMwithEnable
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_08is
port(clk:instd_logic;
en:instd_logic;
we:instd_logic;
a:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do:outstd_logic_vector(15downto0));
endrams_08;
architecturesynoframs_08is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
signalread_a:std_logic_vector(5downto0);
begin
process(clk)
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begin
if(clk’eventandclk=’1’)then
if(en=’1’)then
if(we=’1’)then
RAM(conv_integer(a))<=di;
endif;
read_a<=a;
endif;
endif;
endprocess;
do<=RAM(conv_integer(read_a));
endsyn;
Single-PortRAMWithEnableVerilogCodingExample
//
//Single-PortRAMwithEnable
//
modulev_rams_08(clk,en,we,a,di,do);
inputclk;
inputen;
inputwe;
input[5:0]a;
input[15:0]di;
output[15:0]do;
reg[15:0]ram[63:0];
reg[5:0]read_a;
always@(posedgeclk)begin
if(en)
begin
if(we)
ram[a]<=di;
read_a<=a;
end
end
assigndo=ram[read_a];
endmodule
Thefollowingdiagramshowswherethetwooutputportsareused.Itisdirectly
mappableontoDistributedRAMonly.
Dual-PortRAMWithAsynchronousReadDiagram
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Dual-PortRAMWithAsynchronousReadPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
weSynchronousWriteEnable(active-High)
aWriteAddress/PrimaryReadAddress
dpraDualReadAddress
diDataInput
spoPrimaryOutputPort
dpoDualOutputPort
Dual-PortRAMWithAsynchronousReadVHDLCodingExample
--
--Dual-PortRAMwithAsynchronousRead
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_09is
port(clk:instd_logic;
we:instd_logic;
a:instd_logic_vector(5downto0);
dpra:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
spo:outstd_logic_vector(15downto0);
dpo:outstd_logic_vector(15downto0));
endrams_09;
architecturesynoframs_09is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(we=’1’)then
RAM(conv_integer(a))<=di;
endif;
endif;
endprocess;
spo<=RAM(conv_integer(a));
dpo<=RAM(conv_integer(dpra));
endsyn;
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Dual-PortRAMWithAsynchronousReadVerilogCodingExample
//
//Dual-PortRAMwithAsynchronousRead
//
modulev_rams_09(clk,we,a,dpra,di,spo,dpo);
inputclk;
inputwe;
input[5:0]a;
input[5:0]dpra;
input[15:0]di;
output[15:0]spo;
output[15:0]dpo;
reg[15:0]ram[63:0];
always@(posedgeclk)begin
if(we)
ram[a]<=di;
end
assignspo=ram[a];
assigndpo=ram[dpra];
endmodule
ThefollowingdescriptionsaredirectlymappableontoblockRAM,asshowninthe
diagrambelow.TheymayalsobeimplementedwithDistributedRAM.
Dual-PortRAMWithSynchronousRead(ReadThrough)Diagram
Dual-PortRAMWithSynchronousRead(ReadThrough)Pin
Descriptions
IOPinsDescription
clkPositive-EdgeClock
weSynchronousWriteEnable(active-High)
aWriteAddress/PrimaryReadAddress
dpraDualReadAddress
diDataInput
spoPrimaryOutputPort
dpoDualOutputPort
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Dual-PortRAMWithSynchronousRead(ReadThrough)VHDLCoding
Example
--
--Dual-PortRAMwithSynchronousRead(ReadThrough)
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_11is
port(clk:instd_logic;
we:instd_logic;
a:instd_logic_vector(5downto0);
dpra:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
spo:outstd_logic_vector(15downto0);
dpo:outstd_logic_vector(15downto0));
endrams_11;
architecturesynoframs_11is
typeram_typeisarray(63downto0)
ofstd_logic_vector(15downto0);
signalRAM:ram_type;
signalread_a:std_logic_vector(5downto0);
signalread_dpra:std_logic_vector(5downto0);
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(we=’1’)then
RAM(conv_integer(a))<=di;
endif;
read_a<=a;
read_dpra<=dpra;
endif;
endprocess;
spo<=RAM(conv_integer(read_a));
dpo<=RAM(conv_integer(read_dpra));
endsyn;
Dual-PortRAMWithSynchronousRead(ReadThrough)VerilogCoding
Example
//
//Dual-PortRAMwithSynchronousRead(ReadThrough)
//
modulev_rams_11(clk,we,a,dpra,di,spo,dpo);
inputclk;
inputwe;
input[5:0]a;
input[5:0]dpra;
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input[15:0]di;
output[15:0]spo;
output[15:0]dpo;
reg[15:0]ram[63:0];
reg[5:0]read_a;
reg[5:0]read_dpra;
always@(posedgeclk)begin
if(we)
ram[a]<=di;
read_a<=a;
read_dpra<=dpra;
end
assignspo=ram[read_a];
assigndpo=ram[read_dpra];
endmodule
Dual-PortRAMWithSynchronousRead(ReadThrough)andTwo
ClocksDiagram
Dual-PortRAMWithSynchronousRead(ReadThrough)andTwo
ClocksPinDescriptions
IOPinsDescription
clk1Positive-EdgeWrite/PrimaryReadClock
clk2Positive-EdgeDualReadClock
weSynchronousWriteEnable(active-High)
add1Write/PrimaryReadAddress
add2DualReadAddress
diDataInput
do1PrimaryOutputPort
do2DualOutputPort
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Dual-PortRAMWithSynchronousRead(ReadThrough)andTwoClocks
VHDLCodingExample
--
--Dual-PortRAMwithSynchronousRead(ReadThrough)
--usingMorethanOneClock
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_12is
port(clk1:instd_logic;
clk2:instd_logic;
we:instd_logic;
add1:instd_logic_vector(5downto0);
add2:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do1:outstd_logic_vector(15downto0);
do2:outstd_logic_vector(15downto0));
endrams_12;
architecturesynoframs_12is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
signalread_add1:std_logic_vector(5downto0);
signalread_add2:std_logic_vector(5downto0);
begin
process(clk1)
begin
if(clk1’eventandclk1=’1’)then
if(we=’1’)then
RAM(conv_integer(add1))<=di;
endif;
read_add1<=add1;
endif;
endprocess;
do1<=RAM(conv_integer(read_add1));
process(clk2)
begin
if(clk2’eventandclk2=’1’)then
read_add2<=add2;
endif;
endprocess;
do2<=RAM(conv_integer(read_add2));
endsyn;
Dual-PortRAMWithSynchronousRead(ReadThrough)andTwoClocks
VerilogCodingExample
//
//Dual-PortRAMwithSynchronousRead(ReadThrough)
//usingMorethanOneClock
//
modulev_rams_12(clk1,clk2,we,add1,add2,di,do1,do2);
inputclk1;
inputclk2;
inputwe;
input[5:0]add1;
input[5:0]add2;
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input[15:0]di;
output[15:0]do1;
output[15:0]do2;
reg[15:0]ram[63:0];
reg[5:0]read_add1;
reg[5:0]read_add2;
always@(posedgeclk1)begin
if(we)
ram[add1]<=di;
read_add1<=add1;
end
assigndo1=ram[read_add1];
always@(posedgeclk2)begin
read_add2<=add2;
end
assigndo2=ram[read_add2];
endmodule
Dual-PortRAMWithOneEnableControllingBothPortsDiagram
Dual-PortRAMWithOneEnableControllingBothPortsPin
Descriptions
IOPinsDescription
clkPositive-EdgeClock
enPrimaryGlobalEnable(active-High)
wePrimarySynchronousWriteEnable(active-High)
addraWriteAddress/PrimaryReadAddress
addrbDualReadAddress
diPrimaryDataInput
doaPrimaryOutputPort
dobDualOutputPort
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Dual-PortRAMWithOneEnableControllingBothPortsVHDLCoding
Example
--
--Dual-PortRAMwithOneEnableControllingBothPorts
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_13is
port(clk:instd_logic;
en:instd_logic;
we:instd_logic;
addra:instd_logic_vector(5downto0);
addrb:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
doa:outstd_logic_vector(15downto0);
dob:outstd_logic_vector(15downto0));
endrams_13;
architecturesynoframs_13is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
signalread_addra:std_logic_vector(5downto0);
signalread_addrb:std_logic_vector(5downto0);
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(en=’1’)then
if(we=’1’)then
RAM(conv_integer(addra))<=di;
endif;
read_addra<=addra;
read_addrb<=addrb;
endif;
endif;
endprocess;
doa<=RAM(conv_integer(read_addra));
dob<=RAM(conv_integer(read_addrb));
endsyn;
Dual-PortRAMWithOneEnableControllingBothPortsVerilogCoding
Example
//
//Dual-PortRAMwithOneEnableControllingBothPorts
//
modulev_rams_13(clk,en,we,addra,addrb,di,doa,dob);
inputclk;
inputen;
inputwe;
input[5:0]addra;
input[5:0]addrb;
input[15:0]di;
output[15:0]doa;
output[15:0]dob;
reg[15:0]ram[63:0];
reg[5:0]read_addra;
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reg[5:0]read_addrb;
always@(posedgeclk)begin
if(en)
begin
if(we)
ram[addra]<=di;
read_addra<=addra;
read_addrb<=addrb;
end
end
assigndoa=ram[read_addra];
assigndob=ram[read_addrb];
endmodule
ThefollowingdescriptionsaredirectlymappableontoblockRAM,asshowninthe
diagram.
DualPortRAMWithEnableonEachPortDiagram
DualPortRAMWithEnableonEachPortPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
enaPrimaryGlobalEnable(active-High)
enbDualGlobalEnable(active-High)
weaPrimarySynchronousWriteEnable
(active-High)
addraWriteAddress/PrimaryReadAddress
addrbDualReadAddress
diaPrimaryDataInput
doaPrimaryOutputPort
dobDualOutputPort
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DualPortRAMWithEnableonEachPortVHDLCodingExample
--
--Dual-PortRAMwithEnableonEachPort
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_14is
port(clk:instd_logic;
ena:instd_logic;
enb:instd_logic;
wea:instd_logic;
addra:instd_logic_vector(5downto0);
addrb:instd_logic_vector(5downto0);
dia:instd_logic_vector(15downto0);
doa:outstd_logic_vector(15downto0);
dob:outstd_logic_vector(15downto0));
endrams_14;
architecturesynoframs_14is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
signalread_addra:std_logic_vector(5downto0);
signalread_addrb:std_logic_vector(5downto0);
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(ena=’1’)then
if(wea=’1’)then
RAM(conv_integer(addra))<=dia;
endif;
read_addra<=addra;
endif;
if(enb=’1’)then
read_addrb<=addrb;
endif;
endif;
endprocess;
doa<=RAM(conv_integer(read_addra));
dob<=RAM(conv_integer(read_addrb));
endsyn;
DualPortRAMWithEnableonEachPortVerilogCodingExample
//
//Dual-PortRAMwithEnableonEachPort
//
modulev_rams_14(clk,ena,enb,wea,addra,addrb,dia,doa,dob);
inputclk;
inputena;
inputenb;
inputwea;
input[5:0]addra;
input[5:0]addrb;
input[15:0]dia;
output[15:0]doa;
output[15:0]dob;
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reg[15:0]ram[63:0];
reg[5:0]read_addra;
reg[5:0]read_addrb;
always@(posedgeclk)begin
if(ena)
begin
if(wea)
ram[addra]<=dia;
read_addra<=addra;
end
if(enb)
read_addrb<=addrb;
end
assigndoa=ram[read_addra];
assigndob=ram[read_addrb];
endmodule
Dual-PortBlockRAMWithDifferentClocksDiagram
Dual-PortBlockRAMWithDifferentClockPinDescriptions
IOPinsDescription
clkaPositive-EdgeClock
clkbPositive-EdgeClock
weaPrimarySynchronousWriteEnable
(active-High)
addraWriteAddress/PrimaryReadAddress
addrbDualReadAddress
diaPrimaryDataInput
doaPrimaryOutputPort
dobDualOutputPort
XSTsupportsdual-portblockRAMswithtwowriteportsforVHDLandVerilog.
Theconceptofdual-writeportsimpliesnotonlydistinctdataports,butthepossibility
ofdistinctwriteclocksandwriteenablesaswell.Distinctwriteclocksalsomeandistinct
readclocks,sincethedual-portblockRAMofferstwoclocks,onesharedbytheprimary
readandwriteport,theothersharedbythesecondaryreadandwriteport.
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InVHDL,thedescriptionofthistypeofblockRAMisbasedontheusageofshared
variables.TheXSTVHDLanalyzeracceptssharedvariables,buterrorsoutintheHDL
SynthesisstepifasharedvariabledoesnotdescribeavalidRAMmacro.
Dual-PortBlockRAMWithTwoWritePortsDiagram
Dual-PortBlockRAMWithTwoWritePortsPinDescriptions
IOPinsDescription
clka,clkbPositive-EdgeClock
enaPrimaryGlobalEnable(active-High)
enbDualGlobalEnable(active-High)
wea,webPrimarySynchronousWriteEnable
(active-High)
addraWriteAddress/PrimaryReadAddress
addrbDualReadAddress
diaPrimaryDataInput
dibDualDataInput
doaPrimaryOutputPort
dobDualOutputPort
Dual-PortBlockRAMWithTwoWritePortsVHDLCodingExample
Thisisthemostgeneralexample.Ithasdifferentclocks,enables,andwriteenables.
--
--Dual-PortBlockRAMwithTwoWritePorts
--
libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.std_logic_unsigned.all;
entityrams_16is
port(clka:instd_logic;
clkb:instd_logic;
ena:instd_logic;
enb:instd_logic;
wea:instd_logic;
web:instd_logic;
addra:instd_logic_vector(5downto0);
addrb:instd_logic_vector(5downto0);
dia:instd_logic_vector(15downto0);
dib:instd_logic_vector(15downto0);
doa:outstd_logic_vector(15downto0);
dob:outstd_logic_vector(15downto0));
endrams_16;
architecturesynoframs_16is
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typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
sharedvariableRAM:ram_type;
begin
process(CLKA)
begin
ifCLKA’eventandCLKA=’1’then
ifENA=’1’then
ifWEA=’1’then
RAM(conv_integer(ADDRA)):=DIA;
endif;
DOA<=RAM(conv_integer(ADDRA));
endif;
endif;
endprocess;
process(CLKB)
begin
ifCLKB’eventandCLKB=’1’then
ifENB=’1’then
ifWEB=’1’then
RAM(conv_integer(ADDRB)):=DIB;
endif;
DOB<=RAM(conv_integer(ADDRB));
endif;
endif;
endprocess;
endsyn;
Becauseofthesharedvariable,thedescriptionofthedifferentread/write
synchronizationsmaybedifferentfromcodingexamplesrecommendedforsingle-write
RAMs.Theorderofappearanceofthedifferentlinesofcodeissignicant.
Dual-PortBlockRAMWithTwoWritePortsVerilogCodingExample
Thisisthemostgeneralexample.Ithasdifferentclocks,enables,andwriteenables.
//
//Dual-PortBlockRAMwithTwoWritePorts
//
modulev_rams_16(clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
inputclka,clkb,ena,enb,wea,web;
input[5:0]addra,addrb;
input[15:0]dia,dib;
output[15:0]doa,dob;
reg[15:0]ram[63:0];
reg[15:0]doa,dob;
always@(posedgeclka)begin
if(ena)
begin
if(wea)
ram[addra]<=dia;
doa<=ram[addra];
end
end
always@(posedgeclkb)begin
if(enb)
begin
if(web)
ram[addrb]<=dib;
dob<=ram[addrb];
end
end
endmodule
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Write-FirstSynchronizationCodingExampleOne
process(CLKA)
begin
ifCLKA’eventandCLKA=’1’then
ifWEA=’1’then
RAM(conv_integer(ADDRA)):=DIA;
DOA<=DIA;
else
DOA<=RAM(conv_integer(ADDRA));
endif;
endif;
endprocess;
Write-FirstSynchronizationCodingExampleTwo
Inthisexample,thereadstatementnecessarilycomesafterthewritestatement.
process(CLKA)
begin
ifCLKA’eventandCLKA=’1’then
ifWEA=’1’then
RAM(conv_integer(ADDRA)):=DIA;
endif;
DOA<=RAM(conv_integer(ADDRA));--Thereadstatementmustcome
--AFTERthewritestatement
endif;
endprocess;
Althoughtheymaylookthesameexceptforthesignal/variabledifference,itisalso
importanttounderstandthefunctionaldifferencebetweenthistemplateandthe
followingwellknowntemplatewhichdescribesaread-rstsynchronizationina
single-writeRAM.
signalRAM:RAMtype;
process(CLKA)
begin
ifCLKA’eventandCLKA=’1’then
ifWEA=’1’then
RAM(conv_integer(ADDRA))<=DIA;
endif;
DOA<=RAM(conv_integer(ADDRA));
endif;
endprocess;
Read-FirstSynchronizationCodingExample
Aread-rstsynchronizationisdescribedasfollows,wherethereadstatementmust
comeBEFOREthewritestatement.
process(CLKA)
begin
ifCLKA’eventandCLKA=’1’then
DOA<=RAM(conv_integer(ADDRA));--Thereadstatementmustcome
--BEFOREthewritestatement
ifWEA=’1’then
RAM(conv_integer(ADDRA)):=DIA;
endif;
endif;
endprocess;
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No-ChangeSynchronizationCodingExample
process(CLKA)
begin
ifCLKA’eventandCLKA=’1’then
ifWEA=’1’then
RAM(conv_integer(ADDRA)):=DIA;
else
DOA<=RAM(conv_integer(ADDRA));
endif;
endif;
endprocess;
SingleandDual-PortBlockRAMwithByte-WideWriteEnable
XSTsupportssingleanddual-portblockRAMwithByte-wideWriteEnableforVHDL
andVerilog.TheRAMcanbeseenasacollectionofequalsizecolumns.Duringawrite
cycle,youseparatelycontrolwritingintoeachofthesecolumns.
•MultipleWriteStatement
Thereisoneseparatewriteaccessstatement,includingthedescriptionoftherelated
writeenable,foreachcolumn.
•SingleWriteStatement
Allowsyoutodescribeonlyonewriteaccessstatement.Thewriteenablesare
describedseparatelyoutsidethemainsequentialprocess.XSTcurrentlysupports
thismethodonly.
Thetwomethodsfordescribingcolumn-basedRAMwritesareshowninthefollowing
codingexamples.
MultipleWriteStatementVHDLCodingExample
typeram_typeisarray(SIZE-1downto0)
ofstd_logic_vector(2*WIDTH-1downto0);
signalRAM:ram_type;
(...)
process(clk)
begin
ifposedge(clk)then
ifwe(1)=’1’then
RAM(conv_integer(addr))(2*WIDTH-1downtoWIDTH)<=di(2*WIDTH-1downtoWIDTH);
endif;
ifwe(0)=’1’then
RAM(conv_integer(addr))(WIDTH-1downto0)<=di(WIDTH-1downto0);
endif;
do<=RAM(conv_integer(addr));
endif;
endprocess;
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MultipleWriteStatementVerilogCodingExample
reg[2*DI_WIDTH-1:0]RAM[SIZE-1:0];
always@(posedgeclk)
begin
if(we[1])then
RAM[addr][2*WIDTH-1:WIDTH]<=di[2*WIDTH-1:WIDTH];
endif;
if(we[0])then
RAM[addr][WIDTH-1:0]<=di[WIDTH-1:0;
endif;
do<=RAM[addr];
end
SingleWriteStatementVHDLCodingExample
typeram_typeisarray(SIZE-1downto0)
ofstd_logic_vector(2*WIDTH-1downto0);
signalRAM:ram_type;
signaldi0,di1:std_logic_vector(WIDTH-1downto0);
(...)
--Writeenablesdescribedoutsidemainsequentialprocess
process(we,di,addr)
begin
ifwe(1)=’1’then
di1<=di(2*WIDTH-1downtoWIDTH);
else
di1<=RAM(conv_integer(addr))(2*WIDTH-1downtoWIDTH);
endif;
ifwe(0)=’1’then
di0<=di(WIDTH-1downto0);
else
di0<=RAM(conv_integer(addr))(WIDTH-1downto0);
endif;
endprocess;
process(clk)
begin
ifposedge(clk)then
ifen=’1’then
RAM(conv_integer(addr))<=di1&di0;--singlewriteaccessstatement
do<=RAM(conv_integer(addr));
endif;
endif;
endprocess;
SingleWriteStatementVerilogCodingExample
reg[2*DI_WIDTH-1:0]RAM[SIZE-1:0];
reg[DI_WIDTH-1:0]di0,di1;
always@(weordioraddr)
begin
if(we[1])
di1=di[2*DI_WIDTH-1:1*DI_WIDTH];
else
di1=RAM[addr][2*DI_WIDTH-1:1*DI_WIDTH];
if(we[0])
di0=di[DI_WIDTH-1:0];
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else
di0=RAM[addr][DI_WIDTH-1:0];
end
always@(posedgeclk)
begin
RAM[addr]<={di1,di0};
do<=RAM[addr];
end
Tosimplifytheunderstandingofbyte-widewriteenabletemplates,thefollowing
codingexamplesusesingle-portblockRAMs.XSTsupportsdual-portBlockRAM,as
wellasbyte-widewriteenable.
Read-FirstMode:Single-PortBRAMwithByte-wideWriteEnable
(2Bytes)PinDescriptions
IOPinsDescription
clkPositive-EdgeClock
weWriteEnable
addrWrite/ReadAddress
diDataInput
doRAMOutputPort
Read-FirstMode:Single-PortBRAMWithByte-WideWriteEnable(2Bytes)
VHDLCodingExample
--
--Single-PortBRAMwithByte-wideWriteEnable(2bytes)inRead-FirstMode
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_24is
generic(SIZE:integer:=512;
ADDR_WIDTH:integer:=9;
DI_WIDTH:integer:=8);
port(clk:instd_logic;
we:instd_logic_vector(1downto0);
addr:instd_logic_vector(ADDR_WIDTH-1downto0);
di:instd_logic_vector(2*DI_WIDTH-1downto0);
do:outstd_logic_vector(2*DI_WIDTH-1downto0));
endrams_24;
architecturesynoframs_24is
typeram_typeisarray(SIZE-1downto0)ofstd_logic_vector(2*DI_WIDTH-1downto0);
signalRAM:ram_type;
signaldi0,di1:std_logic_vector(DI_WIDTH-1downto0);
begin
process(we,di)
begin
ifwe(1)=’1’then
di1<=di(2*DI_WIDTH-1downto1*DI_WIDTH);
else
di1<=RAM(conv_integer(addr))(2*DI_WIDTH-1downto1*DI_WIDTH);
endif;
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ifwe(0)=’1’then
di0<=di(DI_WIDTH-1downto0);
else
di0<=RAM(conv_integer(addr))(DI_WIDTH-1downto0);
endif;
endprocess;
process(clk)
begin
if(clk’eventandclk=’1’)then
RAM(conv_integer(addr))<=di1&di0;
do<=RAM(conv_integer(addr));
endif;
endprocess;
endsyn;
Read-FirstMode:Single-PortBRAMWithByte-wideWriteEnable(2Bytes)
VerilogCodingExample
//
//Single-PortBRAMwithByte-wideWriteEnable(2bytes)inRead-FirstMode
//
modulev_rams_24(clk,we,addr,di,do);
parameterSIZE=512;
parameterADDR_WIDTH=9;
parameterDI_WIDTH=8;
inputclk;
input[1:0]we;
input[ADDR_WIDTH-1:0]addr;
input[2*DI_WIDTH-1:0]di;
output[2*DI_WIDTH-1:0]do;
reg[2*DI_WIDTH-1:0]RAM[SIZE-1:0];
reg[2*DI_WIDTH-1:0]do;
reg[DI_WIDTH-1:0]di0,di1;
always@(weordi)
begin
if(we[1])
di1=di[2*DI_WIDTH-1:1*DI_WIDTH];
else
di1=RAM[addr][2*DI_WIDTH-1:1*DI_WIDTH];
if(we[0])
di0=di[DI_WIDTH-1:0];
else
di0=RAM[addr][DI_WIDTH-1:0];
end
always@(posedgeclk)
begin
RAM[addr]<={di1,di0};
do<=RAM[addr];
end
endmodule
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Write-FirstMode:Single-PortBRAMwithByte-wideWriteEnable
(2Bytes)PinDescriptions
IOPinsDescription
ClkPositive-EdgeClock
WeWriteEnable
AddrWrite/ReadAddress
DiDataInput
DoRAMOutputPort
Write-FirstMode:Single-PortBRAMwithByte-WideWriteEnable(2Bytes)
VHDLCodingExample
--
--Single-PortBRAMwithByte-wideWriteEnable(2bytes)inWrite-FirstMode
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_25is
generic(SIZE:integer:=512;
ADDR_WIDTH:integer:=9;
DI_WIDTH:integer:=8);
port(clk:instd_logic;
we:instd_logic_vector(1downto0);
addr:instd_logic_vector(ADDR_WIDTH-1downto0);
di:instd_logic_vector(2*DI_WIDTH-1downto0);
do:outstd_logic_vector(2*DI_WIDTH-1downto0));
endrams_25;
architecturesynoframs_25is
typeram_typeisarray(SIZE-1downto0)ofstd_logic_vector(2*DI_WIDTH-1downto0);
signalRAM:ram_type;
signaldi0,di1:std_logic_vector(DI_WIDTH-1downto0);
signaldo0,do1:std_logic_vector(DI_WIDTH-1downto0);
begin
process(we,di)
begin
ifwe(1)=’1’then
di1<=di(2*DI_WIDTH-1downto1*DI_WIDTH);
do1<=di(2*DI_WIDTH-1downto1*DI_WIDTH);
else
di1<=RAM(conv_integer(addr))(2*DI_WIDTH-1downto1*DI_WIDTH);
do1<=RAM(conv_integer(addr))(2*DI_WIDTH-1downto1*DI_WIDTH);
endif;
ifwe(0)=’1’then
di0<=di(DI_WIDTH-1downto0);
do0<=di(DI_WIDTH-1downto0);
else
di0<=RAM(conv_integer(addr))(DI_WIDTH-1downto0);
do0<=RAM(conv_integer(addr))(DI_WIDTH-1downto0);
endif;
endprocess;
process(clk)
begin
if(clk’eventandclk=’1’)then
RAM(conv_integer(addr))<=di1&di0;
do<=do1&do0;
endif;
endprocess;
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endsyn;
Write-FirstMode:Single-PortBRAMwithByte-WideWriteEnable(2Bytes)
VerilogCodingExample
//
//Single-PortBRAMwithByte-wideWriteEnable
//(2bytes)inWrite-FirstMode
//
modulev_rams_25(clk,we,addr,di,do);
parameterSIZE=512;
parameterADDR_WIDTH=9;
parameterDI_WIDTH=8;
inputclk;
input[1:0]we;
input[ADDR_WIDTH-1:0]addr;
input[2*DI_WIDTH-1:0]di;
output[2*DI_WIDTH-1:0]do;
reg[2*DI_WIDTH-1:0]RAM[SIZE-1:0];
reg[2*DI_WIDTH-1:0]do;
reg[DI_WIDTH-1:0]di0,di1;
reg[DI_WIDTH-1:0]do0,do1;
always@(weordi)
begin
if(we[1])
begin
di1=di[2*DI_WIDTH-1:1*DI_WIDTH];
do1=di[2*DI_WIDTH-1:1*DI_WIDTH];
end
else
begin
di1=RAM[addr][2*DI_WIDTH-1:1*DI_WIDTH];
do1=RAM[addr][2*DI_WIDTH-1:1*DI_WIDTH];
end
if(we[0])
begin
di0<=di[DI_WIDTH-1:0];
do0<=di[DI_WIDTH-1:0];
end
else
begin
di0<=RAM[addr][DI_WIDTH-1:0];
do0<=RAM[addr][DI_WIDTH-1:0];
end
end
always@(posedgeclk)
begin
RAM[addr]<={di1,di0};
do<={do1,do0};
end
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endmodule
No-ChangeMode:Single-PortBRAMwithByte-WideWriteEnable
(2Bytes)PinDescriptions
IOPinsDescription
ClkPositive-EdgeClock
WeWriteEnable
AddrWrite/ReadAddress
DiDataInput
DoRAMOutputPort
XSTinferslatchesfordo1anddo0signalsduringthebasicHDLSynthesis.These
latchesareabsorbedbyBRAMduringtheAdvancedHDLSynthesisstep.
No-ChangeMode:Single-PortBRAMwithByte-WideWriteEnable(2
Bytes)VHDLCodingExample
--
--Single-PortBRAMwithByte-wideWriteEnable(2bytes)inNo-ChangeMode
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_26is
generic(SIZE:integer:=512;
ADDR_WIDTH:integer:=9;
DI_WIDTH:integer:=8);
port(clk:instd_logic;
we:instd_logic_vector(1downto0);
addr:instd_logic_vector(ADDR_WIDTH-1downto0);
di:instd_logic_vector(2*DI_WIDTH-1downto0);
do:outstd_logic_vector(2*DI_WIDTH-1downto0));
endrams_26;
architecturesynoframs_26is
typeram_typeisarray(SIZE-1downto0)ofstd_logic_vector(2*DI_WIDTH-1downto0);
signalRAM:ram_type;
signaldi0,di1:std_logic_vector(DI_WIDTH-1downto0);
signaldo0,do1:std_logic_vector(DI_WIDTH-1downto0);
begin
process(we,di)
begin
ifwe(1)=’1’then
di1<=di(2*DI_WIDTH-1downto1*DI_WIDTH);
else
di1<=RAM(conv_integer(addr))(2*DI_WIDTH-1downto1*DI_WIDTH);
do1<=RAM(conv_integer(addr))(2*DI_WIDTH-1downto1*DI_WIDTH);
endif;
ifwe(0)=’1’then
di0<=di(DI_WIDTH-1downto0);
else
di0<=RAM(conv_integer(addr))(DI_WIDTH-1downto0);
do0<=RAM(conv_integer(addr))(DI_WIDTH-1downto0);
endif;
endprocess;
process(clk)
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begin
if(clk’eventandclk=’1’)then
RAM(conv_integer(addr))<=di1&di0;
do<=do1&do0;
endif;
endprocess;
endsyn;
No-ChangeMode:Single-PortBRAMwithByte-WideWriteEnable(2
Bytes)inVerilogCodingExample
//
//Single-PortBRAMwithByte-wideWriteEnable
//(2bytes)inNo-ChangeMode
//
modulev_rams_26(clk,we,addr,di,do);
parameterSIZE=512;
parameterADDR_WIDTH=9;
parameterDI_WIDTH=8;
inputclk;
input[1:0]we;
input[ADDR_WIDTH-1:0]addr;
input[2*DI_WIDTH-1:0]di;
output[2*DI_WIDTH-1:0]do;
reg[2*DI_WIDTH-1:0]RAM[SIZE-1:0];
reg[2*DI_WIDTH-1:0]do;
reg[DI_WIDTH-1:0]di0,di1;
reg[DI_WIDTH-1:0]do0,do1;
always@(weordi)
begin
if(we[1])
di1=di[2*DI_WIDTH-1:1*DI_WIDTH];
else
begin
di1=RAM[addr][2*DI_WIDTH-1:1*DI_WIDTH];
do1=RAM[addr][2*DI_WIDTH-1:1*DI_WIDTH];
end
if(we[0])
di0<=di[DI_WIDTH-1:0];
else
begin
di0<=RAM[addr][DI_WIDTH-1:0];
do0<=RAM[addr][DI_WIDTH-1:0];
end
end
always@(posedgeclk)
begin
RAM[addr]<={di1,di0};
do<={do1,do0};
end
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endmodule
XSTcanidentifyRAMdescriptionswithtwoormorereadportsthataccesstheRAM
contentsataddressesdifferentfromthewriteaddress.However,therecanonlybeone
writeport.XSTimplementsthefollowingdescriptionsbyreplicatingtheRAMcontents
foreachoutputport,asshowninthefollowinggure.
Multiple-PortRAMDescriptionsDiagram
Multiple-PortRAMDescriptionsPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
weSynchronousWriteEnable(active-High)
waWriteAddress
ra1ReadAddressoftheFirstRAM
ra2ReadAddressoftheSecondRAM
diDataInput
do1FirstRAMOutputPort
do2SecondRAMOutputPort
Multiple-PortRAMDescriptionsVHDLCodingExample
--
--Multiple-PortRAMDescriptions
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_17is
port(clk:instd_logic;
we:instd_logic;
wa:instd_logic_vector(5downto0);
ra1:instd_logic_vector(5downto0);
ra2:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do1:outstd_logic_vector(15downto0);
do2:outstd_logic_vector(15downto0));
endrams_17;
architecturesynoframs_17is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type;
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(we=’1’)then
RAM(conv_integer(wa))<=di;
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endif;
endif;
endprocess;
do1<=RAM(conv_integer(ra1));
do2<=RAM(conv_integer(ra2));
endsyn;
Multiple-PortRAMDescriptionsVerilogCodingExample
//
//Multiple-PortRAMDescriptions
//
modulev_rams_17(clk,we,wa,ra1,ra2,di,do1,do2);
inputclk;
inputwe;
input[5:0]wa;
input[5:0]ra1;
input[5:0]ra2;
input[15:0]di;
output[15:0]do1;
output[15:0]do2;
reg[15:0]ram[63:0];
always@(posedgeclk)
begin
if(we)
ram[wa]<=di;
end
assigndo1=ram[ra1];
assigndo2=ram[ra2];
endmodule
BlockRAMwithResetontheDataOutputs
XSTsupportsblockRAMwithresetonthedataoutputs,asofferedwithVirtex-4
devices,Virtex-5devices,andrelatedblockRAMresources.Optionally,youcaninclude
asynchronouslycontrolledinitializationoftheRAMdataoutputs.
BlockRAMwiththefollowingsynchronizationmodescanhavere-settabledataports.
•Read-FirstBlockRAMwithReset
•Write-FirstBlockRAMwithReset
•No-ChangeBlockRAMwithReset
•RegisteredROMwithReset
•SupportedDual-PortTemplates
BecauseXSTdoesnotsupportblockRAMswithdual-writeinadual-readblockRAM
description,bothdataoutputsmaybereset,butthevariousread-writesynchronizations
areallowedfortheprimarydataoutputonly.ThedualoutputmaybeusedinRead-First
Modeonly.
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BlockRAMWithResetPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
enGlobalEnable
weWriteEnable(active-High)
addrRead/WriteAddress
rstResetfordataoutput
diDataInput
doRAMOutputPort
BlockRAMWithResetVHDLCodingExample
--
--BlockRAMwithReset
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_18is
port(clk:instd_logic;
en:instd_logic;
we:instd_logic;
rst:instd_logic;
addr:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
do:outstd_logic_vector(15downto0));
endrams_18;
architecturesynoframs_18is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalram:ram_type;
begin
process(clk)
begin
ifclk’eventandclk=’1’then
ifen=’1’then--optionalenable
ifwe=’1’then--writeenable
ram(conv_integer(addr))<=di;
endif;
ifrst=’1’then--optionalreset
do<=(others=>’0’);
else
do<=ram(conv_integer(addr));
endif;
endif;
endif;
endprocess;
endsyn;
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BlockRAMWithResetVerilogCodingExample
//
//BlockRAMwithReset
//
modulev_rams_18(clk,en,we,rst,addr,di,do);
inputclk;
inputen;
inputwe;
inputrst;
input[5:0]addr;
input[15:0]di;
output[15:0]do;
reg[15:0]ram[63:0];
reg[15:0]do;
always@(posedgeclk)
begin
if(en)//optionalenable
begin
if(we)//writeenable
ram[addr]<=di;
if(rst)//optionalreset
do<=16’h0000;
else
do<=ram[addr];
end
end
endmodule
BlockRAMWithOptionalOutputRegistersDiagram
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BlockRAMWithOptionalOutputRegistersPinDescriptions
IOPinsDescription
clk1,clk2Positive-EdgeClock
weWriteEnable
en1,en2ClockEnable(active-High)
addr1PrimaryReadAddress
addr2DualReadAddress
diDataInput
res1PrimaryOutputPort
res2DualOutputPort
BlockRAMWithOptionalOutputRegistersVHDLCodingExample
--
--BlockRAMwithOptionalOutputRegisters
--
libraryIEEE;
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityrams_19is
port(clk1,clk2:instd_logic;
we,en1,en2:instd_logic;
addr1:instd_logic_vector(5downto0);
addr2:instd_logic_vector(5downto0);
di:instd_logic_vector(15downto0);
res1:outstd_logic_vector(15downto0);
res2:outstd_logic_vector(15downto0));
endrams_19;
architecturebehoframs_19is
typeram_typeisarray(63downto0)ofstd_logic_vector(15downto0);
signalram:ram_type;
signaldo1:std_logic_vector(15downto0);
signaldo2:std_logic_vector(15downto0);
begin
process(clk1)
begin
ifrising_edge(clk1)then
ifwe=’1’then
ram(conv_integer(addr1))<=di;
endif;
do1<=ram(conv_integer(addr1));
endif;
endprocess;
process(clk2)
begin
ifrising_edge(clk2)then
do2<=ram(conv_integer(addr2));
endif;
endprocess;
process(clk1)
begin
ifrising_edge(clk1)then
ifen1=’1’then
res1<=do1;
endif;
endif;
endprocess;
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process(clk2)
begin
ifrising_edge(clk2)then
ifen2=’1’then
res2<=do2;
endif;
endif;
endprocess;
endbeh;
BlockRAMWithOptionalOutputRegistersVerilogCodingExample
//
//BlockRAMwithOptionalOutputRegisters
//
modulev_rams_19(clk1,clk2,we,en1,en2,addr1,addr2,di,res1,res2);
inputclk1;
inputclk2;
inputwe,en1,en2;
input[5:0]addr1;
input[5:0]addr2;
input[15:0]di;
output[15:0]res1;
output[15:0]res2;
reg[15:0]res1;
reg[15:0]res2;
reg[15:0]RAM[63:0];
reg[15:0]do1;
reg[15:0]do2;
always@(posedgeclk1)
begin
if(we==1’b1)
RAM[addr1]<=di;
do1<=RAM[addr1];
end
always@(posedgeclk2)
begin
do2<=RAM[addr2];
end
always@(posedgeclk1)
begin
if(en1==1’b1)
res1<=do1;
end
always@(posedgeclk2)
begin
if(en2==1’b1)
res2<=do2;
end
endmodule
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InitializingRAMCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
BlockanddistributedRAMinitialcontentscanbespeciedbyinitializationofthesignal
describingthememoryarrayinyourHDLcode.DothisdirectlyinyourHDLcode,or
specifyalecontainingtheinitializationdata.
XSTsupportsRAMinitializationinbothVHDLandVerilog.
ThefollowingcodingexamplesshowhowtoinitializeRAMdirectlyinHardware
DescriptionLanguage(HDL)code.
RAMInitialContentsVHDLCodingExample(Hexadecimal)
TospecifyRAMinitialcontents,initializethesignaldescribingthememoryarrayinthe
VHDLcodeasshowninthefollowingcodingexample.
...
typeram_typeisarray(0to63)ofstd_logic_vector(19downto0);
signalRAM:ram_type:=
(
X"0200A",X"00300",X"08101",X"04000",X"08601",X"0233A",
X"00300",X"08602",X"02310",X"0203B",X"08300",X"04002",
X"08201",X"00500",X"04001",X"02500",X"00340",X"00241",
X"04002",X"08300",X"08201",X"00500",X"08101",X"00602",
X"04003",X"0241E",X"00301",X"00102",X"02122",X"02021",
X"00301",X"00102",X"02222",X"04001",X"00342",X"0232B",
X"00900",X"00302",X"00102",X"04002",X"00900",X"08201",
X"02023",X"00303",X"02433",X"00301",X"04004",X"00301",
X"00102",X"02137",X"02036",X"00301",X"00102",X"02237",
X"04004",X"00304",X"04040",X"02500",X"02500",X"02500",
X"0030D",X"02341",X"08201",X"0400D");
...
process(clk)
begin
ifrising_edge(clk)then
ifwe=’1’then
RAM(conv_integer(a))<=di;
endif;
ra<=a;
endif;
endprocess;
...
do<=RAM(conv_integer(ra));
InitializingBlockRAMVerilogCodingExample(Hexadecimal)
TospecifyRAMinitialcontents,initializethesignaldescribingthememoryarrayin
yourVerilogcodeusinginitialstatementsasshowninthefollowingcodingexample.
...
reg[19:0]ram[63:0];
initialbegin
ram[63]=20’h0200A;ram[62]=20’h00300;ram[61]=20’h08101;
ram[60]=20’h04000;ram[59]=20’h08601;ram[58]=20’h0233A;
...
ram[2]=20’h02341;ram[1]=20’h08201;ram[0]=20’h0400D;
end
...
always@(posedgeclk)
begin
if(we)
ram[addr]<=di;
do<=ram[addr];
end
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RAMInitialContentsVHDLCodingExample(Binary)
RAMinitialcontentscanbespeciedinhexadecimal,asshowninRAMInitialContents
VHDLCodingExample(Hexadecimal),orinbinaryasshowninthefollowingcoding
example.
...
typeram_typeisarray(0toSIZE-1)ofstd_logic_vector(15downto0);
signalRAM:ram_type:=
(
"0111100100000101",
"0000010110111101",
"1100001101010000",
...
"0000100101110011");
InitializingBlockRAMVerilogCodingExample(Binary)
RAMinitialcontentscanbespeciedinhexadecimal,asshowninInitializingBlockRAM
VerilogCodingExample(Hexadecimal),orinbinaryasshowninthefollowingcoding
example.
...
reg[15:0]ram[63:0];
initialbegin
ram[63]=16’b0111100100000101;
ram[62]=16’b0000010110111101;
ram[61]=16’b1100001101010000;
...
ram[0]=16’b0000100101110011;
end
...
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Single-PortBRAMInitialContentsVHDLCodingExample
--
--InitializingBlockRAM(Single-PortBRAM)
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_20ais
port(clk:instd_logic;
we:instd_logic;
addr:instd_logic_vector(5downto0);
di:instd_logic_vector(19downto0);
do:outstd_logic_vector(19downto0));
endrams_20a;
architecturesynoframs_20ais
typeram_typeisarray(63downto0)ofstd_logic_vector(19downto0);
signalRAM:ram_type:=(X"0200A",X"00300",X"08101",X"04000",X"08601",X"0233A",
X"00300",X"08602",X"02310",X"0203B",X"08300",X"04002",
X"08201",X"00500",X"04001",X"02500",X"00340",X"00241",
X"04002",X"08300",X"08201",X"00500",X"08101",X"00602",
X"04003",X"0241E",X"00301",X"00102",X"02122",X"02021",
X"00301",X"00102",X"02222",X"04001",X"00342",X"0232B",
X"00900",X"00302",X"00102",X"04002",X"00900",X"08201",
X"02023",X"00303",X"02433",X"00301",X"04004",X"00301",
X"00102",X"02137",X"02036",X"00301",X"00102",X"02237",
X"04004",X"00304",X"04040",X"02500",X"02500",X"02500",
X"0030D",X"02341",X"08201",X"0400D");
begin
process(clk)
begin
ifrising_edge(clk)then
ifwe=’1’then
RAM(conv_integer(addr))<=di;
endif;
do<=RAM(conv_integer(addr));
endif;
endprocess;
endsyn;
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Single-PortBRAMInitialContentsVerilogCodingExample
//
//InitializingBlockRAM(Single-PortBRAM)
//
modulev_rams_20a(clk,we,addr,di,do);
inputclk;
inputwe;
input[5:0]addr;
input[19:0]di;
output[19:0]do;
reg[19:0]ram[63:0];
reg[19:0]do;
initialbegin
ram[63]=20’h0200A;ram[62]=20’h00300;ram[61]=20’h08101;
ram[60]=20’h04000;ram[59]=20’h08601;ram[58]=20’h0233A;
ram[57]=20’h00300;ram[56]=20’h08602;ram[55]=20’h02310;
ram[54]=20’h0203B;ram[53]=20’h08300;ram[52]=20’h04002;
ram[51]=20’h08201;ram[50]=20’h00500;ram[49]=20’h04001;
ram[48]=20’h02500;ram[47]=20’h00340;ram[46]=20’h00241;
ram[45]=20’h04002;ram[44]=20’h08300;ram[43]=20’h08201;
ram[42]=20’h00500;ram[41]=20’h08101;ram[40]=20’h00602;
ram[39]=20’h04003;ram[38]=20’h0241E;ram[37]=20’h00301;
ram[36]=20’h00102;ram[35]=20’h02122;ram[34]=20’h02021;
ram[33]=20’h00301;ram[32]=20’h00102;ram[31]=20’h02222;
ram[30]=20’h04001;ram[29]=20’h00342;ram[28]=20’h0232B;
ram[27]=20’h00900;ram[26]=20’h00302;ram[25]=20’h00102;
ram[24]=20’h04002;ram[23]=20’h00900;ram[22]=20’h08201;
ram[21]=20’h02023;ram[20]=20’h00303;ram[19]=20’h02433;
ram[18]=20’h00301;ram[17]=20’h04004;ram[16]=20’h00301;
ram[15]=20’h00102;ram[14]=20’h02137;ram[13]=20’h02036;
ram[12]=20’h00301;ram[11]=20’h00102;ram[10]=20’h02237;
ram[9]=20’h04004;ram[8]=20’h00304;ram[7]=20’h04040;
ram[6]=20’h02500;ram[5]=20’h02500;ram[4]=20’h02500;
ram[3]=20’h0030D;ram[2]=20’h02341;ram[1]=20’h08201;
ram[0]=20’h0400D;
end
always@(posedgeclk)
begin
if(we)
ram[addr]<=di;
do<=ram[addr];
end
endmodule
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Chapter3:XSTHDLCodingTechniques
Dual-PortRAMInitialContentsVHDLCodingExample
--
--InitializingBlockRAM(Dual-PortBRAM)
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_20bis
port(clk1:instd_logic;
clk2:instd_logic;
we:instd_logic;
addr1:instd_logic_vector(7downto0);
addr2:instd_logic_vector(7downto0);
di:instd_logic_vector(15downto0);
do1:outstd_logic_vector(15downto0);
do2:outstd_logic_vector(15downto0));
endrams_20b;
architecturesynoframs_20bis
typeram_typeisarray(255downto0)ofstd_logic_vector(15downto0);
signalRAM:ram_type:=(255downto100=>X"B8B8",99downto0=>X"8282");
begin
process(clk1)
begin
ifrising_edge(clk1)then
ifwe=’1’then
RAM(conv_integer(addr1))<=di;
endif;
do1<=RAM(conv_integer(addr1));
endif;
endprocess;
process(clk2)
begin
ifrising_edge(clk2)then
do2<=RAM(conv_integer(addr2));
endif;
endprocess;
endsyn;
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Dual-PortRAMInitialContentsVerilogCodingExample
//
//InitializingBlockRAM(Dual-PortBRAM)
//
modulev_rams_20b(clk1,clk2,we,addr1,addr2,di,do1,do2);
inputclk1,clk2;
inputwe;
input[7:0]addr1,addr2;
input[15:0]di;
output[15:0]do1,do2;
reg[15:0]ram[255:0];
reg[15:0]do1,do2;
integerindex;
initialbegin
for(index=0;index<=99;index=index+1)begin
ram[index]=16’h8282;
end
for(index=100;index<=255;index=index+1)begin
ram[index]=16’hB8B8;
end
end
always@(posedgeclk1)
begin
if(we)
ram[addr1]<=di;
do1<=ram[addr1];
end
always@(posedgeclk2)
begin
do2<=ram[addr2];
end
endmodule
InitializingRAMFromanExternalFileCodingExamples
ThefollowingcodingexamplesshowhowtoinitializeRAMfromanexternalle.
ToinitializeRAMfromvaluescontainedinanexternalle,useareadfunctioninthe
VHDLcode.
Formoreinformation,see:
VHDLFileTypeSupport.
Setuptheinitializationleasfollows.
•Useeachlineoftheinitializationletorepresenttheinitialcontentsofagiven
rowintheRAM.
•RAMcontentscanberepresentedinbinaryorhexadecimal.
•ThereshouldbeasmanylinesintheleastherearerowsintheRAMarray.
Followingisanexampleofthecontentsofaleinitializingan8x32-bitRAMwith
binaryvalues:
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
00001111000011110000111100001111
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Chapter3:XSTHDLCodingTechniques
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
InitializingBlockRAM(ExternalDataFile)
RAMinitialvaluesmaybestoredinanexternaldatalethatisaccessedfromwithin
theHDLcode.Thedatalemustbepurebinaryorhexadecimalcontentwithno
commentsorotherinformation.
Followingisanexampleofthecontentsofaleinitializingan8x32-bitRAMwith
binaryvalues.Forbothexamples,thedatalereferencediscalledrams_20c.data.
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
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InitializingBlockRAM(ExternalDataFile)VHDLCodingExample
Inthefollowingcodingexample,theloopthatgeneratestheinitialvalueiscontrolledby
testingthatweareintheRAMaddressrange.Thefollowingcodingexamplesshow
initializingBlockRAMfromanexternaldatale.
--
--InitializingBlockRAMfromexternaldatafile
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
usestd.textio.all;
entityrams_20cis
port(clk:instd_logic;
we:instd_logic;
addr:instd_logic_vector(5downto0);
din:instd_logic_vector(31downto0);
dout:outstd_logic_vector(31downto0));
endrams_20c;
architecturesynoframs_20cis
typeRamTypeisarray(0to63)ofbit_vector(31downto0);
impurefunctionInitRamFromFile(RamFileName:instring)returnRamTypeis
FILERamFile:textisinRamFileName;
variableRamFileLine:line;
variableRAM:RamType;
begin
forIinRamType’rangeloop
readline(RamFile,RamFileLine);
read(RamFileLine,RAM(I));
endloop;
returnRAM;
endfunction;
signalRAM:RamType:=InitRamFromFile("rams_20c.data");
begin
process(clk)
begin
ifclk’eventandclk=’1’then
ifwe=’1’then
RAM(conv_integer(addr))<=to_bitvector(din);
endif;
dout<=to_stdlogicvector(RAM(conv_integer(addr)));
endif;
endprocess;
endsyn;
Iftherearenotenoughlinesintheexternaldatale,XSTissuesthefollowingmessage.
ERROR:Xst-raminitfile1.vhdline40:Line<RamFileLinehasnot
enoughelementsfortarget<RAM<63>>.
InitializingBlockRAM(ExternalDataFile)VerilogCodingExample
ToinitializeRAMfromvaluescontainedinanexternalle,usea$readmembor
$readmemhsystemtaskinyourVerilogcode.
Formoreinformation,see:
XSTBehavioralVerilogLanguageSupport
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Setuptheinitializationleasfollows.
•Arrangeeachlineoftheinitializationletorepresenttheinitialcontentsofagiven
rowintheRAM
•RAMcontentscanberepresentedinbinaryorhexadecimal.
•Use$readmembforbinaryand$readmemhforhexadecimalrepresentation.
ToavoidthepossibledifferencebetweenXSTandsimulatorbehavior,Xilinx®
recommendsthatyouuseindexparametersinthesesystemtasks.Seethefollowing
codingexample.
$readmemb("rams_20c.data",ram,0,7);
CreateasmanylinesintheleastherearerowsintheRAMarray.
//
//InitializingBlockRAMfromexternaldatafile
//
modulev_rams_20c(clk,we,addr,din,dout);
inputclk;
inputwe;
input[5:0]addr;
input[31:0]din;
output[31:0]dout;
reg[31:0]ram[0:63];
reg[31:0]dout;
initial
begin
$readmemb("rams_20c.data",ram,0,63);
end
always@(posedgeclk)
begin
if(we)
ram[addr]<=din;
dout<=ram[addr];
end
endmodule
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InitializingRAMFromanExternalFileCodingExamples
ThefollowingcodingexamplesshowhowtoinitializeRAMfromanexternalle.
ToinitializeRAMfromvaluescontainedinanexternalle,useareadfunctioninthe
VHDLcode.
Formoreinformation,see:
VHDLFileTypeSupport.
Setuptheinitializationleasfollows.
•Useeachlineoftheinitializationletorepresenttheinitialcontentsofagiven
rowintheRAM.
•RAMcontentscanberepresentedinbinaryorhexadecimal.
•ThereshouldbeasmanylinesintheleastherearerowsintheRAMarray.
Followingisanexampleofthecontentsofaleinitializingan8x32-bitRAMwith
binaryvalues:
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
InitializingBlockRAM(ExternalDataFile)
RAMinitialvaluesmaybestoredinanexternaldatalethatisaccessedfromwithin
theHDLcode.Thedatalemustbepurebinaryorhexadecimalcontentwithno
commentsorotherinformation.
Followingisanexampleofthecontentsofaleinitializingan8x32-bitRAMwith
binaryvalues.Forbothexamples,thedatalereferencediscalledrams_20c.data.
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
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Chapter3:XSTHDLCodingTechniques
InitializingBlockRAM(ExternalDataFile)VHDLCodingExample
Inthefollowingcodingexample,theloopthatgeneratestheinitialvalueiscontrolledby
testingthatweareintheRAMaddressrange.Thefollowingcodingexamplesshow
initializingBlockRAMfromanexternaldatale.
--
--InitializingBlockRAMfromexternaldatafile
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
usestd.textio.all;
entityrams_20cis
port(clk:instd_logic;
we:instd_logic;
addr:instd_logic_vector(5downto0);
din:instd_logic_vector(31downto0);
dout:outstd_logic_vector(31downto0));
endrams_20c;
architecturesynoframs_20cis
typeRamTypeisarray(0to63)ofbit_vector(31downto0);
impurefunctionInitRamFromFile(RamFileName:instring)returnRamTypeis
FILERamFile:textisinRamFileName;
variableRamFileLine:line;
variableRAM:RamType;
begin
forIinRamType’rangeloop
readline(RamFile,RamFileLine);
read(RamFileLine,RAM(I));
endloop;
returnRAM;
endfunction;
signalRAM:RamType:=InitRamFromFile("rams_20c.data");
begin
process(clk)
begin
ifclk’eventandclk=’1’then
ifwe=’1’then
RAM(conv_integer(addr))<=to_bitvector(din);
endif;
dout<=to_stdlogicvector(RAM(conv_integer(addr)));
endif;
endprocess;
endsyn;
Iftherearenotenoughlinesintheexternaldatale,XSTissuesthefollowingmessage.
ERROR:Xst-raminitfile1.vhdline40:Line<RamFileLinehasnot
enoughelementsfortarget<RAM<63>>.
InitializingBlockRAM(ExternalDataFile)VerilogCodingExample
ToinitializeRAMfromvaluescontainedinanexternalle,usea$readmembor
$readmemhsystemtaskinyourVerilogcode.
Formoreinformation,see:
XSTBehavioralVerilogLanguageSupport
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Setuptheinitializationleasfollows.
•Arrangeeachlineoftheinitializationletorepresenttheinitialcontentsofagiven
rowintheRAM
•RAMcontentscanberepresentedinbinaryorhexadecimal.
•Use$readmembforbinaryand$readmemhforhexadecimalrepresentation.
ToavoidthepossibledifferencebetweenXSTandsimulatorbehavior,Xilinx®
recommendsthatyouuseindexparametersinthesesystemtasks.Seethefollowing
codingexample.
$readmemb("rams_20c.data",ram,0,7);
CreateasmanylinesintheleastherearerowsintheRAMarray.
//
//InitializingBlockRAMfromexternaldatafile
//
modulev_rams_20c(clk,we,addr,din,dout);
inputclk;
inputwe;
input[5:0]addr;
input[31:0]din;
output[31:0]dout;
reg[31:0]ram[0:63];
reg[31:0]dout;
initial
begin
$readmemb("rams_20c.data",ram,0,63);
end
always@(posedgeclk)
begin
if(we)
ram[addr]<=din;
dout<=ram[addr];
end
endmodule
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Chapter3:XSTHDLCodingTechniques
ROMsUsingBlockRAMResourcesHDLCodingTechniques
ThissectiondiscussesROMsUsingBlockRAMResourcesHDLCodingTechniques,
andincludes:
•AboutROMsUsingBlockRAMResources
•ROMsUsingBlockRAMResourcesLogFile
•ROMsUsingBlockRAMResourcesRelatedConstraints
•ROMsUsingBlockRAMResourcesCodingExamples
AboutROMsUsingBlockRAMResources
XSTcanuseblockRAMresourcestoimplementROMswithsynchronousoutputsor
addressinputs.TheseROMsareimplementedassingle-portordual-portblockRAMs
dependingontheHDLdescription.
XSTcaninferblockROMacrosshierarchiesifKeepHierarchy(KEEP_HIERARCHY)is
settono.Inthiscase,ROMandthedataoutputoraddressregistercanbedescribedin
separatehierarchyblocks.ThisinferenceisperformedduringAdvancedHDLSynthesis.
UsingblockRAMresourcestoimplementROMsiscontrolledbytheROMStyle
(ROM_STYLE)constraint.
FormoreinformationaboutROMStyle(ROM_STYLE),see:
XSTDesignConstraints
FormoreinformationaboutROMimplementation,see:
XSTFPGAOptimization
ROMsUsingBlockRAMResourcesLogFile
FollowingisaROMsUsingBlockRAMResourcesLogFileExample.
ROMsUsingBlockRAMResourcesLogFileExample
=========================================================================
*HDLSynthesis*
=========================================================================
SynthesizingUnit<rams_21a>.
Relatedsourcefileis"rams_21a.vhd".
Found64x20-bitROMforsignal<$varindex0000>createdatline38.
Found20-bitregisterforsignal<data>.
Summary:
inferred1ROM(s).
inferred20D-typeflip-flop(s).
Unit<rams_21a>synthesized.
=========================================================================
HDLSynthesisReport
MacroStatistics
#ROMs:1
64x20-bitROM:1
#Registers:1
20-bitregister:1
=========================================================================
=========================================================================
*AdvancedHDLSynthesis*
=========================================================================
INFO:Xst-Unit<rams_21a>:TheROM<Mrom__varindex0000>willbeimplemented
asaread-onlyBLOCKRAM,absorbingtheregister:<data>.
-----------------------------------------------------------------------
|ram_type|Block||
-----------------------------------------------------------------------
|PortA|
|aspectratio|64-wordx20-bit(6.9%)||
|mode|write-first||
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|clkA|connectedtosignal<clk>|rise|
|enA|connectedtosignal<en>|high|
|weA|connectedtointernalnode|high|
|addrA|connectedtosignal<addr>||
|diA|connectedtointernalnode||
|doA|connectedtosignal<data>||
-----------------------------------------------------------------------
=========================================================================
AdvancedHDLSynthesisReport
MacroStatistics
#RAMs:1
64x20-bitsingle-portblockRAM:1
=========================================================================
ROMsUsingBlockRAMResourcesRelatedConstraints
ROMStyle(ROM_STYLE)
ROMsUsingBlockRAMResourcesCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
ROMWithRegisteredOutputDiagram
ROMWithRegisteredOutputPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
enSynchronousEnable(active-High)
addrReadAddress
dataDataOutput
ROMWithRegisteredOutputVHDLCodingExampleOne
--
--ROMsUsingBlockRAMResources.
--VHDLcodeforaROMwithregisteredoutput(template1)
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_21ais
port(clk:instd_logic;
en:instd_logic;
addr:instd_logic_vector(5downto0);
data:outstd_logic_vector(19downto0));
endrams_21a;
architecturesynoframs_21ais
typerom_typeisarray(63downto0)ofstd_logic_vector(19downto0);
signalROM:rom_type:=(X"0200A",X"00300",X"08101",X"04000",X"08601",X"0233A",
X"00300",X"08602",X"02310",X"0203B",X"08300",X"04002",
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X"08201",X"00500",X"04001",X"02500",X"00340",X"00241",
X"04002",X"08300",X"08201",X"00500",X"08101",X"00602",
X"04003",X"0241E",X"00301",X"00102",X"02122",X"02021",
X"00301",X"00102",X"02222",X"04001",X"00342",X"0232B",
X"00900",X"00302",X"00102",X"04002",X"00900",X"08201",
X"02023",X"00303",X"02433",X"00301",X"04004",X"00301",
X"00102",X"02137",X"02036",X"00301",X"00102",X"02237",
X"04004",X"00304",X"04040",X"02500",X"02500",X"02500",
X"0030D",X"02341",X"08201",X"0400D");
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(en=’1’)then
data<=ROM(conv_integer(addr));
endif;
endif;
endprocess;
endsyn;
ROMWithRegisteredOutputVHDLCodingExampleTwo
--
--ROMsUsingBlockRAMResources.
--VHDLcodeforaROMwithregisteredoutput(template2)
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_21bis
port(clk:instd_logic;
en:instd_logic;
addr:instd_logic_vector(5downto0);
data:outstd_logic_vector(19downto0));
endrams_21b;
architecturesynoframs_21bis
typerom_typeisarray(63downto0)ofstd_logic_vector(19downto0);
signalROM:rom_type:=(X"0200A",X"00300",X"08101",X"04000",X"08601",X"0233A",
X"00300",X"08602",X"02310",X"0203B",X"08300",X"04002",
X"08201",X"00500",X"04001",X"02500",X"00340",X"00241",
X"04002",X"08300",X"08201",X"00500",X"08101",X"00602",
X"04003",X"0241E",X"00301",X"00102",X"02122",X"02021",
X"00301",X"00102",X"02222",X"04001",X"00342",X"0232B",
X"00900",X"00302",X"00102",X"04002",X"00900",X"08201",
X"02023",X"00303",X"02433",X"00301",X"04004",X"00301",
X"00102",X"02137",X"02036",X"00301",X"00102",X"02237",
X"04004",X"00304",X"04040",X"02500",X"02500",X"02500",
X"0030D",X"02341",X"08201",X"0400D");
signalrdata:std_logic_vector(19downto0);
begin
rdata<=ROM(conv_integer(addr));
process(clk)
begin
if(clk’eventandclk=’1’)then
if(en=’1’)then
data<=rdata;
endif;
endif;
endprocess;
endsyn;
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ROMWithRegisteredOutputVerilogCodingExampleOne
//
//ROMsUsingBlockRAMResources.
//VerilogcodeforaROMwithregisteredoutput(template1)
//
modulev_rams_21a(clk,en,addr,data);
inputclk;
inputen;
input[5:0]addr;
outputreg[19:0]data;
always@(posedgeclk)begin
if(en)
case(addr)
6’b000000:data<=20’h0200A;6’b100000:data<=20’h02222;
6’b000001:data<=20’h00300;6’b100001:data<=20’h04001;
6’b000010:data<=20’h08101;6’b100010:data<=20’h00342;
6’b000011:data<=20’h04000;6’b100011:data<=20’h0232B;
6’b000100:data<=20’h08601;6’b100100:data<=20’h00900;
6’b000101:data<=20’h0233A;6’b100101:data<=20’h00302;
6’b000110:data<=20’h00300;6’b100110:data<=20’h00102;
6’b000111:data<=20’h08602;6’b100111:data<=20’h04002;
6’b001000:data<=20’h02310;6’b101000:data<=20’h00900;
6’b001001:data<=20’h0203B;6’b101001:data<=20’h08201;
6’b001010:data<=20’h08300;6’b101010:data<=20’h02023;
6’b001011:data<=20’h04002;6’b101011:data<=20’h00303;
6’b001100:data<=20’h08201;6’b101100:data<=20’h02433;
6’b001101:data<=20’h00500;6’b101101:data<=20’h00301;
6’b001110:data<=20’h04001;6’b101110:data<=20’h04004;
6’b001111:data<=20’h02500;6’b101111:data<=20’h00301;
6’b010000:data<=20’h00340;6’b110000:data<=20’h00102;
6’b010001:data<=20’h00241;6’b110001:data<=20’h02137;
6’b010010:data<=20’h04002;6’b110010:data<=20’h02036;
6’b010011:data<=20’h08300;6’b110011:data<=20’h00301;
6’b010100:data<=20’h08201;6’b110100:data<=20’h00102;
6’b010101:data<=20’h00500;6’b110101:data<=20’h02237;
6’b010110:data<=20’h08101;6’b110110:data<=20’h04004;
6’b010111:data<=20’h00602;6’b110111:data<=20’h00304;
6’b011000:data<=20’h04003;6’b111000:data<=20’h04040;
6’b011001:data<=20’h0241E;6’b111001:data<=20’h02500;
6’b011010:data<=20’h00301;6’b111010:data<=20’h02500;
6’b011011:data<=20’h00102;6’b111011:data<=20’h02500;
6’b011100:data<=20’h02122;6’b111100:data<=20’h0030D;
6’b011101:data<=20’h02021;6’b111101:data<=20’h02341;
6’b011110:data<=20’h00301;6’b111110:data<=20’h08201;
6’b011111:data<=20’h00102;6’b111111:data<=20’h0400D;
endcase
end
endmodule
ROMWithRegisteredOutputVerilogCodingExampleTwo
//
//ROMsUsingBlockRAMResources.
//VerilogcodeforaROMwithregisteredoutput(template2)
//
modulev_rams_21b(clk,en,addr,data);
inputclk;
inputen;
input[5:0]addr;
outputreg[19:0]data;
reg[19:0]rdata;
always@(addr)begin
case(addr)
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6’b000000:rdata<=20’h0200A;6’b100000:rdata<=20’h02222;
6’b000001:rdata<=20’h00300;6’b100001:rdata<=20’h04001;
6’b000010:rdata<=20’h08101;6’b100010:rdata<=20’h00342;
6’b000011:rdata<=20’h04000;6’b100011:rdata<=20’h0232B;
6’b000100:rdata<=20’h08601;6’b100100:rdata<=20’h00900;
6’b000101:rdata<=20’h0233A;6’b100101:rdata<=20’h00302;
6’b000110:rdata<=20’h00300;6’b100110:rdata<=20’h00102;
6’b000111:rdata<=20’h08602;6’b100111:rdata<=20’h04002;
6’b001000:rdata<=20’h02310;6’b101000:rdata<=20’h00900;
6’b001001:rdata<=20’h0203B;6’b101001:rdata<=20’h08201;
6’b001010:rdata<=20’h08300;6’b101010:rdata<=20’h02023;
6’b001011:rdata<=20’h04002;6’b101011:rdata<=20’h00303;
6’b001100:rdata<=20’h08201;6’b101100:rdata<=20’h02433;
6’b001101:rdata<=20’h00500;6’b101101:rdata<=20’h00301;
6’b001110:rdata<=20’h04001;6’b101110:rdata<=20’h04004;
6’b001111:rdata<=20’h02500;6’b101111:rdata<=20’h00301;
6’b010000:rdata<=20’h00340;6’b110000:rdata<=20’h00102;
6’b010001:rdata<=20’h00241;6’b110001:rdata<=20’h02137;
6’b010010:rdata<=20’h04002;6’b110010:rdata<=20’h02036;
6’b010011:rdata<=20’h08300;6’b110011:rdata<=20’h00301;
6’b010100:rdata<=20’h08201;6’b110100:rdata<=20’h00102;
6’b010101:rdata<=20’h00500;6’b110101:rdata<=20’h02237;
6’b010110:rdata<=20’h08101;6’b110110:rdata<=20’h04004;
6’b010111:rdata<=20’h00602;6’b110111:rdata<=20’h00304;
6’b011000:rdata<=20’h04003;6’b111000:rdata<=20’h04040;
6’b011001:rdata<=20’h0241E;6’b111001:rdata<=20’h02500;
6’b011010:rdata<=20’h00301;6’b111010:rdata<=20’h02500;
6’b011011:rdata<=20’h00102;6’b111011:rdata<=20’h02500;
6’b011100:rdata<=20’h02122;6’b111100:rdata<=20’h0030D;
6’b011101:rdata<=20’h02021;6’b111101:rdata<=20’h02341;
6’b011110:rdata<=20’h00301;6’b111110:rdata<=20’h08201;
6’b011111:rdata<=20’h00102;6’b111111:rdata<=20’h0400D;
endcase
end
always@(posedgeclk)begin
if(en)
data<=rdata;
end
endmodule
ROMWithRegisteredAddressDiagram
ROMWithRegisteredAddressPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
enSynchronousEnable(active-High)
addrReadAddress
dataDataOutput
clkPositive-EdgeClock
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Chapter3:XSTHDLCodingTechniques
ROMWithRegisteredAddressVHDLCodingExample
--
--ROMsUsingBlockRAMResources.
--VHDLcodeforaROMwithregisteredaddress
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_21cis
port(clk:instd_logic;
en:instd_logic;
addr:instd_logic_vector(5downto0);
data:outstd_logic_vector(19downto0));
endrams_21c;
architecturesynoframs_21cis
typerom_typeisarray(63downto0)ofstd_logic_vector(19downto0);
signalROM:rom_type:=(X"0200A",X"00300",X"08101",X"04000",X"08601",X"0233A",
X"00300",X"08602",X"02310",X"0203B",X"08300",X"04002",
X"08201",X"00500",X"04001",X"02500",X"00340",X"00241",
X"04002",X"08300",X"08201",X"00500",X"08101",X"00602",
X"04003",X"0241E",X"00301",X"00102",X"02122",X"02021",
X"00301",X"00102",X"02222",X"04001",X"00342",X"0232B",
X"00900",X"00302",X"00102",X"04002",X"00900",X"08201",
X"02023",X"00303",X"02433",X"00301",X"04004",X"00301",
X"00102",X"02137",X"02036",X"00301",X"00102",X"02237",
X"04004",X"00304",X"04040",X"02500",X"02500",X"02500",
X"0030D",X"02341",X"08201",X"0400D");
signalraddr:std_logic_vector(5downto0);
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(en=’1’)then
raddr<=addr;
endif;
endif;
endprocess;
data<=ROM(conv_integer(raddr));
endsyn;
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ROMWithRegisteredAddressVerilogCodingExample
//
//ROMsUsingBlockRAMResources.
//VerilogcodeforaROMwithregisteredaddress
//
modulev_rams_21c(clk,en,addr,data);
inputclk;
inputen;
input[5:0]addr;
outputreg[19:0]data;
reg[5:0]raddr;
always@(posedgeclk)begin
if(en)
raddr<=addr;
end
always@(raddr)begin
case(raddr)
6’b000000:data<=20’h0200A;6’b100000:data<=20’h02222;
6’b000001:data<=20’h00300;6’b100001:data<=20’h04001;
6’b000010:data<=20’h08101;6’b100010:data<=20’h00342;
6’b000011:data<=20’h04000;6’b100011:data<=20’h0232B;
6’b000100:data<=20’h08601;6’b100100:data<=20’h00900;
6’b000101:data<=20’h0233A;6’b100101:data<=20’h00302;
6’b000110:data<=20’h00300;6’b100110:data<=20’h00102;
6’b000111:data<=20’h08602;6’b100111:data<=20’h04002;
6’b001000:data<=20’h02310;6’b101000:data<=20’h00900;
6’b001001:data<=20’h0203B;6’b101001:data<=20’h08201;
6’b001010:data<=20’h08300;6’b101010:data<=20’h02023;
6’b001011:data<=20’h04002;6’b101011:data<=20’h00303;
6’b001100:data<=20’h08201;6’b101100:data<=20’h02433;
6’b001101:data<=20’h00500;6’b101101:data<=20’h00301;
6’b001110:data<=20’h04001;6’b101110:data<=20’h04004;
6’b001111:data<=20’h02500;6’b101111:data<=20’h00301;
6’b010000:data<=20’h00340;6’b110000:data<=20’h00102;
6’b010001:data<=20’h00241;6’b110001:data<=20’h02137;
6’b010010:data<=20’h04002;6’b110010:data<=20’h02036;
6’b010011:data<=20’h08300;6’b110011:data<=20’h00301;
6’b010100:data<=20’h08201;6’b110100:data<=20’h00102;
6’b010101:data<=20’h00500;6’b110101:data<=20’h02237;
6’b010110:data<=20’h08101;6’b110110:data<=20’h04004;
6’b010111:data<=20’h00602;6’b110111:data<=20’h00304;
6’b011000:data<=20’h04003;6’b111000:data<=20’h04040;
6’b011001:data<=20’h0241E;6’b111001:data<=20’h02500;
6’b011010:data<=20’h00301;6’b111010:data<=20’h02500;
6’b011011:data<=20’h00102;6’b111011:data<=20’h02500;
6’b011100:data<=20’h02122;6’b111100:data<=20’h0030D;
6’b011101:data<=20’h02021;6’b111101:data<=20’h02341;
6’b011110:data<=20’h00301;6’b111110:data<=20’h08201;
6’b011111:data<=20’h00102;6’b111111:data<=20’h0400D;
endcase
end
endmodule
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Chapter3:XSTHDLCodingTechniques
PipelinedDistributedRAMHDLCodingTechniques
ThissectiondiscussesPipelinedDistributedRAMHDLCodingTechniques,and
includes:
•AboutPipelinedDistributedRAM
•PipelinedDistributedRAMLogFile
•PipelinedDistributedRAMRelatedConstraints
•PipelinedDistributedRAMCodingExamples
AboutPipelinedDistributedRAM
Inordertoincreasethespeedofdesigns,XSTcaninferpipelineddistributedRAM.
ByinterspersingregistersbetweenthestagesofdistributedRAM,pipeliningcan
signicantlyincreasetheoverallfrequencyofyourdesign.Theeffectofpipelining
issimilartoFlip-FlopRetiming.
Toinsertpipelinestages:
1.DescribethenecessaryregistersinyourHardwareDescriptionLanguage(HDL)
code
2.PlacethemafteranydistributedRAM
3.SetRAMStyle(RAM_STYLE)to:
pipe_distributed
InordertoreachthemaximumdistributedRAMspeed,XSTusesthemaximumnumber
ofavailableregisterswhen:
•Itdetectsvalidregistersforpipelining,and
•RAM_STYLEissetto:
pipe_distributed
Inordertoobtainthebestfrequency,XSTautomaticallycalculatesthemaximum
numberofregistersforeachRAM.
DuringtheAdvancedHDLSynthesisstep,theXSTHDLAdvisoradvisesyoutospecify
theoptimumnumberofregisterstagesif:
•Youhavenotspeciedsufcientregisterstages,and
•RAM_STYLEiscodeddirectlyonasignal
XSTimplementstheunusedstagesasshiftregistersif:
•Thenumberofregistersplacedafterthemultiplierexceedsthemaximumrequired,
and
•Shiftregisterextractionisactivated
XSTcannotpipelineRAMifregisterscontainasynchronousset/resetsignals.XSTcan
pipelineRAMifregisterscontainsynchronousresetsignals.
PipelinedDistributedRAMLogFile
FollowingisaPipelinedDistributedRAMLogFileExample.
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Chapter3:XSTHDLCodingTechniques
PipelinedDistributedRAMLogFileExample
====================================================================
*HDLSynthesis*
====================================================================
SynthesizingUnit<rams_22>.
Relatedsourcefileis"rams_22.vhd".
Found64x4-bitsingle-portRAMforsignal<RAM>.
Found4-bitregisterforsignal<do>.
Summary:
inferred1RAM(s).
inferred4D-typeflip-flop(s).
Unit<rams_22>synthesized.
=========================================================================
HDLSynthesisReport
MacroStatistics
#RAMs:1
64x4-bitsingle-portRAM:1
#Registers:1
4-bitregister:1
=========================================================================
====================================================================
*AdvancedHDLSynthesis*
====================================================================
INFO:Xst-Unit<rams_22>:TheRAM<Mram_RAM>willbeimplementedasa
distributedRAM,absorbingthefollowingregister(s):<do>.
-------------------------------------------------------------
|aspectratio|64-wordx4-bit||
|clock|connectedtosignal<clk>|rise|
|writeenable|connectedtosignal<we>|high|
|address|connectedtosignal<addr>||
|datain|connectedtosignal<di>||
|dataout|connectedtointernalnode||
|ram_style|distributed||
-------------------------------------------------------------
Synthesizing(advanced)Unit<rams_22>.
Foundpipelinedramonsignal<_varindex0000>:
-1pipelinelevel(s)foundinaregisteronsignal<_varindex0000>.
Pushingregister(s)intotherammacro.
INFO:Xst:2390-HDLADVISOR-Youcanimprovetheperformanceof
theramMram_RAMbyadding1registerlevel(s)onoutputsignal_varindex0000.
Unit<rams_22>synthesized(advanced).
=========================================================================
AdvancedHDLSynthesisReport
MacroStatistics
#RAMs:1
64x4-bitregisteredsingle-portdistributedRAM:1
=========================================================================
PipelinedDistributedRAMRelatedConstraints
•RAMExtraction(RAM_EXTRACT)
•RAMStyle(RAM_STYLE)
•ROMExtraction(ROM_EXTRACT)
•ROMStyle(ROM_STYLE)
•BRAMUtilizationRatio(BRAM_UTILIZATION_RATIO)
•AutomaticBRAMPacking(AUTO_BRAM_PACKING)
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PipelinedDistributedRAMCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
PipelinedDistributedRAMDiagram
PipelinedDistributedRAMPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
weSynchronousWriteEnable(active-High)
addrRead/WriteAddress
diDataInput
doDataOutput
PipelinedDistributedRAMVHDLCodingExample
--
--PipelinedistributedRAMs
--
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrams_22is
port(clk:instd_logic;
we:instd_logic;
addr:instd_logic_vector(8downto0);
di:instd_logic_vector(3downto0);
do:outstd_logic_vector(3downto0));
endrams_22;
architecturesynoframs_22is
typeram_typeisarray(511downto0)ofstd_logic_vector(3downto0);
signalRAM:ram_type;
signalpipe_reg:std_logic_vector(3downto0);
attributeram_style:string;
attributeram_styleofRAM:signalis"pipe_distributed";
begin
process(clk)
begin
ifclk’eventandclk=’1’then
ifwe=’1’then
RAM(conv_integer(addr))<=di;
else
pipe_reg<=RAM(conv_integer(addr));
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Chapter3:XSTHDLCodingTechniques
endif;
do<=pipe_reg;
endif;
endprocess;
endsyn;
PipelinedDistributedRAMVerilogCodingExample
//
//PipelinedistributedRAMs
//
modulev_rams_22(clk,we,addr,di,do);
inputclk;
inputwe;
input[8:0]addr;
input[3:0]di;
output[3:0]do;
(*ram_style="pipe_distributed"*)
reg[3:0]RAM[511:0];
reg[3:0]do;
reg[3:0]pipe_reg;
always@(posedgeclk)
begin
if(we)
RAM[addr]<=di;
else
pipe_reg<=RAM[addr];
do<=pipe_reg;
end
endmodule
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Chapter3:XSTHDLCodingTechniques
FSMHDLCodingTechniques
ThissectiondiscussesFiniteStateMachine(FSM)HDLCodingTechniques,andincludes:
•AboutFSMComponents
•DescribinganFSMComponent
•StateEncodingTechniques
•RAM-BasedFSMSynthesis
•SafeFSMImplementation
•FSMLogFile
•FSMRelatedConstraints
•FSMCodingExamples
AboutFSMComponents
TheXilinxSynthesisTechnology(XST)software:
•IncludesalargesetoftemplatestodescribeFiniteStateMachine(FSM)components
•Canapplyseveralstateencodingtechniquestoobtainbetterperformanceorlessarea
•Canre-encodeyourinitialencoding
•Canhandleonlysynchronousstatemachines
TodisableFSMextraction,useAutomaticFSMExtraction(FSM_EXTRACT).
DescribinganFSMComponent
TherearemanywaystodescribeaFiniteStateMachine(FSM)component.Atraditional
FSMrepresentationincorporatesMealyandMooremachines,asshowninthefollowing
diagram.XSTsupportsbothmodels.
FSMRepresentationIncorporatingMealyandMooreMachines
Diagram
DescribingFSMComponentswithProcessandAlways
ForHDL,process(VHDL)andalwaysblocks(Verilog)arethebestwaystodescribe
FSMcomponents.Xilinx®usesprocesstorefertobothVHDLprocessesandVerilog
alwaysblocks.
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Youmayhaveseveralprocesses(1,2or3)inyourdescription,dependinguponhowyou
consideranddecomposethedifferentpartsoftheprecedingmodel.Followingisan
exampleoftheMooreMachinewithAsynchronousReset,RESET.
•4states
–s1
–s2
–s3
–s4
•5transitions
•1input
x1com
•1output
outp
Theabovemodelisrepresentedbythefollowingbubblediagram.
BubbleDiagram
StateRegisters
ForXSTtosuccessfullyidentifyaFiniteStateMachine(FSM),descriptionsofthestate
registershouldincludeeither:
•Apower-upstate
Thepower-upstatemustuseproperVHDLorVerilogsignalinitialization.
•Anoperationalreset
Theoperationalresetcanbeasynchronousorsynchronous.
ForcodingexamplesonhowtowriteAsynchronousandSynchronousinitialization
signals,see:
RegistersHDLCodingTechniques
InVHDL,thetypeofastateregistercanbeadifferenttype,suchas:
•integer
•bit_vector
•std_logic_vector
Butitiscommonandconvenienttodeneanenumeratedtypecontainingallpossible
statevaluesandtodeclareyourstateregisterwiththattype.
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Chapter3:XSTHDLCodingTechniques
InVerilog,thetypeofstateregistercanbeanintegerorasetofdenedparameters.In
thefollowingVerilogexamplesthestateassignmentscouldhavebeenmadeasfollows:
parameter[3:0]
s1=4’b0001,
s2=4’b0010,
s3=4’b0100,
s4=4’b1000;
reg[3:0]state;
Theseparameterscanbemodiedtorepresentdifferentstateencodingschemes.
NextStateEquations
Nextstateequationscanbedescribeddirectlyinthesequentialprocessorinadistinct
combinatorialprocess.Thesimplestcodingexampleisbasedonacasestatement.If
usingaseparatecombinatorialprocess,itssensitivitylistshouldcontainthestatesignal
andallFSMinputs.
UnreachableStates
XSTcandetectunreachablestatesinanFSM.ItliststheminthelogleintheHDL
Synthesisstep.
OutputsandInputs
Non-registeredoutputsaredescribedeitherinthecombinatorialprocessorinconcurrent
assignments.Registeredoutputsmustbeassignedwithinthesequentialprocess.
Registeredinputsaredescribedusinginternalsignals,whichareassignedinthe
sequentialprocess.
StateEncodingTechniques
XSTsupportsthefollowingstateencodingtechniques:
•AutoStateEncoding
•One-HotStateEncoding
•GrayStateEncoding
•CompactStateEncoding
•JohnsonStateEncoding
•SequentialStateEncoding
•Speed1StateEncoding
•UserStateEncoding
AutoStateEncoding
InAutoStateEncoding,XSTtriestoselectthebestsuitedencodingalgorithmforeach
FiniteStateMachine(FSM).
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One-HotStateEncoding
One-HotStateEncoding:
•Isthedefaultencodingscheme.
•Associatesonecodebitandoneip-optoeachstate.Atagivenclockcycleduring
operation,oneandonlyonebitofthestatevariableisasserted.Onlytwobitstoggle
duringatransitionbetweentwostates.
•IsappropriatewithmostFPGAtargetswherealargenumberofip-opsare
available.
•Isagoodalternativewhentryingtooptimizespeedortoreducepowerdissipation.
GrayStateEncoding
GrayStateEncoding:
•Guaranteesthatonlyonebitswitchesbetweentwoconsecutivestates.
•Isappropriateforcontrollersexhibitinglongpathswithoutbranching.
•Minimizeshazardsandglitches.
•GivesgoodresultswhenimplementingthestateregisterwithTip-ops.
CompactStateEncoding
CompactStateEncoding:
•Minimizesthenumberofbitsinthestatevariablesandip-ops.
•Isbasedonhypercubeimmersion.
•Isappropriatewhentryingtooptimizearea.
JohnsonStateEncoding
LikeGrayStateEncoding,JohnsonStateEncodingshowsbenetswithstatemachines
containinglongpathswithnobranching.
SequentialStateEncoding
SequentialStateEncoding:
•Identieslongpathsandappliessuccessiveradixtwocodestothestatesonthese
paths.
•Minimizesnextstateequations.
Speed1StateEncoding
Speed1StateEncodingisorientedforspeedoptimization.Thenumberofbitsforastate
registerdependsontheparticularFSM,butgenerallyitisgreaterthanthenumber
ofFSMstates.
UserStateEncoding
InUserStateEncoding,XSTusestheoriginalencodingspeciedintheHDLle.For
example,ifyouuseenumeratedtypesforastateregister,useEnumeratedEncoding
(ENUM_ENCODING)toassignaspecicbinaryvaluetoeachstate.
Formoreinformation,see:
XSTDesignConstraints
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RAM-BasedFSMSynthesis
LargeFiniteStateMachine(FSM)componentscanbemademorecompactandfasterby
implementingthemintheblockRAMresourcesprovidedinVirtex®devicesandlater
technologies.FSMStyle(FSM_STYLE)directsXSTtouseblockRAMresourcesforFSMs.
ValuesforFSMStyle(FSM_STYLE)are:
•lut(default)
XSTmapstheFSMusingLUTs.
•bram
XSTmapstheFSMontoblockRAM.
InvokeFSMStyle(FSM_STYLE)asfollows:
•ISE®DesignSuite
SelectLUTorBlockRAMasinstructedintheHDLOptionstopicsoftheISEDesign
SuiteHelp.
•Commandline
Usethe-fsm_stylecommandlineoption.
•HardwareDescriptionLanguage(HDL)code
UseFSMStyle(FSM_STYLE)
IfitcannotimplementastatemachineonblockRAM,XST:
•IssuesawarningintheAdvancedHDLSynthesisstepofthelogle.
•AutomaticallyimplementsthestatemachineusingLUTs.
Forexample,ifFSMhasanasynchronousreset,itcannotbeimplementedusingblock
RAM.InthiscaseXSTinformsyou:
...
===============================================================
*AdvancedHDLSynthesis*
===============================================================
WARNING:Xst-UnabletofitFSM<FSM_0>inBRAM(resetis
asynchronous).
SelectingencodingforFSM_0...
OptimizingFSM<FSM_0>onsignal<current_state>
withone-hotencoding.
...
SafeFSMImplementation
XSTcanaddlogictoaFiniteStateMachine(FSM)implementationthatwillletastate
machinerecoverfromaninvalidstate.Ifduringitsexecution,astatemachineentersan
invalidstate,thelogicaddedbyXSTbringsitbacktoaknownstate,calledarecovery
state.ThisisknownasSafeImplementationmode.
ToactivateSafeFSMimplementation:
•InISE®DesignSuite,selectSafeImplementationasinstructedintheHDLOptions
topicofISEDesignSuiteHelp,or
•ApplySafeImplementation(SAFE_IMPLEMENTATION)tothehierarchicalblock
orsignalthatrepresentsthestateregister.
Bydefault,XSTautomaticallyselectsaresetstateastherecoverystate.Ifthe
FSMdoesnothaveaninitializationsignal,XSTselectsapower-upstateasthe
recoverystate.Tomanuallydenetherecoverystate,applySafeRecoveryState
(SAFE_RECOVERY_STATE).
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FSMLogFile
TheXSTloglereportsthefullinformationofrecognizedFiniteStateMachine(FSM)
componentsduringtheMacroRecognitionstep.IfyouallowXSTtochoosethebest
encodingalgorithmforyourFSMs,itreportsthealgorithmitchoseforeachFSM.As
soonasencodingisselected,XSTreportstheoriginalandnalFSMencoding.Ifthe
targetisanFPGAdevice,XSTreportsthisencodingattheHDLSynthesisstep.Ifthe
targetisaCPLDdevice,thenXSTreportsthisencodingattheLowLevelOptimization
step.
FSMLogFileExample
...
SynthesizingUnit<fsm_1>.
Relatedsourcefileis"/state_machines_1.vhd".
Foundfinitestatemachine<FSM_0>forsignal<state>.
------------------------------------------------------
|States|4|
|Transitions|5|
|Inputs|1|
|Outputs|4|
|Clock|clk(rising_edge)|
|Reset|reset(positive)|
|Resettype|asynchronous|
|ResetState|s1|
|PowerUpState|s1|
|Encoding|automatic|
|Implementation|LUT|
------------------------------------------------------
Found1-bitregisterforsignal<outp>.
Summary:
inferred1FiniteStateMachine(s).
inferred1D-typeflip-flop(s).
Unit<fsm_1>synthesized.
========================================================
HDLSynthesisReport
MacroStatistics
#Registers:1
1-bitregister:1
========================================================
========================================================
*AdvancedHDLSynthesis*
========================================================
AdvancedRegisteredAddSubinference...
AnalyzingFSM<FSM_0>forbestencoding.
OptimizingFSM<state/FSM_0>onsignal<state[1:2]>
withgrayencoding.
-------------------
State|Encoding
-------------------
s1|00
s2|01
s3|11
s4|10
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Chapter3:XSTHDLCodingTechniques
-------------------
=======================================================
HDLSynthesisReport
MacroStatistics
#FSMs:1
=======================================================
FSMRelatedConstraints
•AutomaticFSMExtraction(FSM_EXTRACT)
•FSMStyle(FSM_STYLE)
•FSMEncodingAlgorithm(FSM_ENCODING)
•EnumeratedEncoding(ENUM_ENCODING)
•SafeImplementation(SAFE_IMPLEMENTATION)
•SafeRecoveryState(SAFE_RECOVERY_STATE)
FSMCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
FSMWithOneProcessPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
resetAsynchronousReset(active-High)
x1FSMInput
outpFSMOutput
FSMWithOneProcessVHDLCodingExample
--
--StateMachinewithasingleprocess.
--
libraryIEEE;
useIEEE.std_logic_1164.all;
entityfsm_1is
port(clk,reset,x1:INstd_logic;
outp:OUTstd_logic);
endentity;
architecturebeh1offsm_1is
typestate_typeis(s1,s2,s3,s4);
signalstate:state_type;
begin
process(clk,reset)
begin
if(reset=’1’)then
state<=s1;
outp<=’1’;
elsif(clk=’1’andclk’event)then
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Chapter3:XSTHDLCodingTechniques
casestateis
whens1=>ifx1=’1’then
state<=s2;
outp<=’1’;
else
state<=s3;
outp<=’0’;
endif;
whens2=>state<=s4;outp<=’0’;
whens3=>state<=s4;outp<=’0’;
whens4=>state<=s1;outp<=’1’;
endcase;
endif;
endprocess;
endbeh1;
FSMWithSingleAlwaysBlockVerilogCodingExample
//
//StateMachinewithasinglealwaysblock.
//
modulev_fsm_1(clk,reset,x1,outp);
inputclk,reset,x1;
outputoutp;
regoutp;
reg[1:0]state;
parameters1=2’b00;parameters2=2’b01;
parameters3=2’b10;parameters4=2’b11;
initialbegin
state=2’b00;
end
always@(posedgeclkorposedgereset)
begin
if(reset)
begin
state<=s1;outp<=1’b1;
end
else
begin
case(state)
s1:begin
if(x1==1’b1)
begin
state<=s2;
outp<=1’b1;
end
else
begin
state<=s3;
outp<=1’b0;
end
end
s2:begin
state<=s4;outp<=1’b1;
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Chapter3:XSTHDLCodingTechniques
end
s3:begin
state<=s4;outp<=1’b0;
end
s4:begin
state<=s1;outp<=1’b0;
end
endcase
end
end
endmodule
FSMWithTwoProcesses
Toeliminatearegisterfromtheoutputs,removeallassignmentsoutp<=…from
theClocksynchronizationsection.Thiscanbedonebyintroducingtwoprocessesas
shownbelow.
FSMWithTwoProcessesDiagram
FSMWithTwoProcessesPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
resetAsynchronousReset(active-High)
x1FSMInput
outpFSMOutput
FSMWithTwoProcessesVHDLCodingExample
--
--StateMachinewithtwoprocesses.
--
libraryIEEE;
useIEEE.std_logic_1164.all;
entityfsm_2is
port(clk,reset,x1:INstd_logic;
outp:OUTstd_logic);
endentity;
architecturebeh1offsm_2is
typestate_typeis(s1,s2,s3,s4);
signalstate:state_type;
begin
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process1:process(clk,reset)
begin
if(reset=’1’)thenstate<=s1;
elsif(clk=’1’andclk’Event)then
casestateis
whens1=>ifx1=’1’then
state<=s2;
else
state<=s3;
endif;
whens2=>state<=s4;
whens3=>state<=s4;
whens4=>state<=s1;
endcase;
endif;
endprocessprocess1;
process2:process(state)
begin
casestateis
whens1=>outp<=’1’;
whens2=>outp<=’1’;
whens3=>outp<=’0’;
whens4=>outp<=’0’;
endcase;
endprocessprocess2;
endbeh1;
FSMWithTwoAlwaysBlocksVerilogCodingExample
//
//StateMachinewithtwoalwaysblocks.
//
modulev_fsm_2(clk,reset,x1,outp);
inputclk,reset,x1;
outputoutp;
regoutp;
reg[1:0]state;
parameters1=2’b00;parameters2=2’b01;
parameters3=2’b10;parameters4=2’b11;
initialbegin
state=2’b00;
end
always@(posedgeclkorposedgereset)
begin
if(reset)
state<=s1;
else
begin
case(state)
s1:if(x1==1’b1)
state<=s2;
else
state<=s3;
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Chapter3:XSTHDLCodingTechniques
s2:state<=s4;
s3:state<=s4;
s4:state<=s1;
endcase
end
end
always@(state)
begin
case(state)
s1:outp=1’b1;
s2:outp=1’b1;
s3:outp=1’b0;
s4:outp=1’b0;
endcase
end
endmodule
YoucanalsoseparatetheNEXTStatefunctionfromthestateregister.
FSMWithThreeProcessesDiagram
FSMWithThreeProcessesPinDescriptions
IOPinsDescription
clkPositive-EdgeClock
resetAsynchronousReset(active-High)
x1FSMInput
outpFSMOutput
FSMWithThreeProcessesVHDLCodingExample
--
--StateMachinewiththreeprocesses.
--
libraryIEEE;
useIEEE.std_logic_1164.all;
entityfsm_3is
port(clk,reset,x1:INstd_logic;
outp:OUTstd_logic);
endentity;
architecturebeh1offsm_3is
typestate_typeis(s1,s2,s3,s4);
signalstate,next_state:state_type;
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begin
process1:process(clk,reset)
begin
if(reset=’1’)then
state<=s1;
elsif(clk=’1’andclk’Event)then
state<=next_state;
endif;
endprocessprocess1;
process2:process(state,x1)
begin
casestateis
whens1=>ifx1=’1’then
next_state<=s2;
else
next_state<=s3;
endif;
whens2=>next_state<=s4;
whens3=>next_state<=s4;
whens4=>next_state<=s1;
endcase;
endprocessprocess2;
process3:process(state)
begin
casestateis
whens1=>outp<=’1’;
whens2=>outp<=’1’;
whens3=>outp<=’0’;
whens4=>outp<=’0’;
endcase;
endprocessprocess3;
endbeh1;
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Chapter3:XSTHDLCodingTechniques
FSMWithThreeAlwaysBlocksVerilogCodingExample
//
//StateMachinewiththreealwaysblocks.
//
modulev_fsm_3(clk,reset,x1,outp);
inputclk,reset,x1;
outputoutp;
regoutp;
reg[1:0]state;
reg[1:0]next_state;
parameters1=2’b00;parameters2=2’b01;
parameters3=2’b10;parameters4=2’b11;
initialbegin
state=2’b00;
end
always@(posedgeclkorposedgereset)
begin
if(reset)state<=s1;
elsestate<=next_state;
end
always@(stateorx1)
begin
case(state)
s1:if(x1==1’b1)
next_state=s2;
else
next_state=s3;
s2:next_state=s4;
s3:next_state=s4;
s4:next_state=s1;
endcase
end
always@(state)
begin
case(state)
s1:outp=1’b1;
s2:outp=1’b1;
s3:outp=1’b0;
s4:outp=1’b0;
endcase
end
endmodule
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Chapter3:XSTHDLCodingTechniques
BlackBoxesHDLCodingTechniques
ThissectiondiscussesBlackBoxesHDLCodingTechniques,andincludes:
•AboutBlackBoxes
•BlackBoxLogFile
•BlackBoxRelatedConstraints
•BlackBoxCodingExamples
AboutBlackBoxes
YourdesignmaycontainElectronicDataInterchangeFormat(EDIF)orNGCles
generatedby:
•Synthesistools
•Schematictexteditors
•Anyotherdesignentrymechanism
Thesemodulesmustbeinstantiatedinyourcodeinordertobeconnectedtotherestof
yourdesign.TodosoinXST,useBlackBoxinstantiationintheVHDLorVerilogcode.
Thenetlistispropagatedtothenaltop-levelnetlistwithoutbeingprocessedbyXST.
XSTenablesyoutoattachspecicconstraintstotheseBlackBoxinstantiations,which
arepassedtotheNGCle.
Inaddition,youmayhaveadesignblockforwhichyouhaveanRegisterTransferLevel
(RTL)model,aswellasyourownimplementationofthisblockintheformofanEDIF
netlist.TheRTLmodelisvalidforsimulationpurposesonly.UseBoxType(BOX_TYPE)
todirectXSTtoskipsynthesisofthisRTLcodeandcreateaBlackBox.TheEDIFnetlist
islinkedtothesynthesizeddesignduringNGDBuild.
OnceyoumakeadesignaBlackBox,eachinstanceofthatdesignisaBlackBox.While
youcanattachconstraintstotheinstance,XSTignoresanyconstraintattachedtothe
originaldesign.
Formoreinformation,see:
•XSTGeneralConstraints
•ConstraintsGuide
BlackBoxLogFile
SinceXSTrecognizesBlackBoxesbeforemacroinference,theBlackBoxloglediffers
fromtheloglesgeneratedforothermacros.
BlackBoxLogFileExample
...
AnalyzingEntity<black_b>(Architecture<archi>).
WARNING:Xst:766-black_box_1.vhd(Line15).
GeneratingaBlackBoxforcomponent<my_block>.
Entity<black_b>analyzed.Unit<black_b>generated
....
BlackBoxRelatedConstraints
BoxType(BOX_TYPE)
BoxTypewasintroducedfordeviceprimitiveinstantiationinXST.Beforeusing
BoxType,see:
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Chapter3:XSTHDLCodingTechniques
DevicePrimitiveSupport
BlackBoxCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
BlackBoxVHDLCodingExample
--
--BlackBox
--
libraryieee;
useieee.std_logic_1164.all;
entityblack_box_1is
port(DI_1,DI_2:instd_logic;
DOUT:outstd_logic);
endblack_box_1;
architecturearchiofblack_box_1is
componentmy_block
port(I1:instd_logic;
I2:instd_logic;
O:outstd_logic);
endcomponent;
begin
inst:my_blockportmap(I1=>DI_1,I2=>DI_2,O=>DOUT);
endarchi;
BlackBoxVerilogCodingExample
//
//BlackBox
//
modulev_my_block(in1,in2,dout);
inputin1,in2;
outputdout;
endmodule
modulev_black_box_1(DI_1,DI_2,DOUT);
inputDI_1,DI_2;
outputDOUT;
v_my_blockinst(
.in1(DI_1),
.in2(DI_2),
.dout(DOUT));
endmodule
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Chapter4
XSTFPGAOptimization
ThischapterdiscussesXSTFPGAOptimization,andincludes:
•FPGASynthesisandOptimization
•FPGASpecicSynthesisOptions
•MacroGeneration
•DSP48BlockResources
•MappingLogicOntoBlockRAM
•Flip-FlopRetiming
•Partitions
•SpeedOptimizationUnderAreaConstraint
•FPGAOptimizationReport
•ImplementationConstraints
•FPGADevicePrimitiveSupport
•CoresProcessing
•SpecifyingINITandRLOC
•UsingPCI™FlowWithXST
FPGASynthesisandOptimization
XSTperformsthefollowingstepsduringFPGAsynthesisandoptimization:
•Mappingandoptimizationonanentitybyentityormodulebymodulebasis
•Globaloptimizationonthecompletedesign
TheoutputisanNGCle.
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Chapter4:XSTFPGAOptimization
FPGASpecificSynthesisOptions
XSTsupportsthefollowingoptionstone-tuneFPGAsynthesistomeetuserconstraints:
•ExtractBUFGCE(BUFGCE)
•CoresSearchDirectories(-sd)
•DecoderExtraction(DECODER_EXTRACT)
•FSMStyle(FSM_STYLE)
•GlobalOptimizationGoal(-glob_opt)
•KeepHierarchy(KEEP_HIERARCHY)
•LogicalShifterExtraction(SHIFT_EXTRACT)
•MapLogiconBRAM(BRAM_MAP)
•MaxFanout(MAX_FANOUT)
•MoveFirstStage(MOVE_FIRST_STAGE)
•MoveLastStage(MOVE_LAST_STAGE)
•MultiplierStyle(MULT_STYLE)
•MuxStyle(MUX_STYLE)
•NumberofGlobalClockBuffers(-bufg)
•OptimizeInstantiatedPrimitives(OPTIMIZE_PRIMITIVES)
•PackI/ORegistersIntoIOBs(IOB)
•PriorityEncoderExtraction(PRIORITY_EXTRACT)
•RAMStyle(RAM_STYLE)
•RegisterBalancing(REGISTER_BALANCING)
•RegisterDuplication(REGISTER_DUPLICATION)
•SignalEncoding(SIGNAL_ENCODING)
•SlicePacking(-slice_packing)
•UseCarryChain(USE_CARRY_CHAIN)
•WriteTimingConstraints(-write_timing_constraints)
•XORCollapsing(XOR_COLLAPSE)
Formoreinformation,see:
XSTFPGAConstraints(Non-Timing)
MacroGeneration
TheFPGADeviceMacroGeneratormoduleprovidestheXSTHDLFlowwithacatalog
offunctions.ThesefunctionsareidentiedbytheinferenceenginefromtheHardware
DescriptionLanguage(HDL)description.TheircharacteristicsarehandedtotheMacro
Generatorforoptimalimplementation.
Thesetofinferredfunctionsrangesincomplexityfromsimplearithmeticoperators
(suchasadders,accumulators,countersandmultiplexers),tomorecomplexbuilding
blocks(suchasmultipliers,shiftregistersandmemories).
Inferredfunctionsareoptimizedtodeliverthehighestlevelsofperformanceand
efciencyfortheselectedVirtex®architectureorSpartan®architecture,andthen
integratedintotherestofthedesign.Inaddition,thegeneratedfunctionsareoptimized
throughtheirbordersdependingonthedesigncontext.
Thissectioncategorizes,byfunction,allavailablemacrosandbrieydescribes
technologyresourcesusedinthebuildingandoptimizationphase.
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Chapter4:XSTFPGAOptimization
MacroGenerationcanbecontrolledthroughattributes.Theseattributesarelistedin
eachsubsection.
XSTusesdedicatedcarrychainlogictoimplementmanymacros.Insomesituations
carrychainlogicmayresultinlessthanidealoptimization.UseCarryChain
(USE_CARRY_CHAIN)deactivatesthisfeature.
Formoreinformation,see:
XSTDesignConstraints
ArithmeticFunctionsinMacroGeneration
ForArithmeticFunctions,XSTprovidesthefollowingelements:
•Adders,SubtractorsandAdder/Subtractors
•CascadableBinaryCounters
•Accumulators
•Incrementers,DecrementersandIncrementer/Decrementers
•SignedandUnsignedMultipliers
XSTusesfastcarrylogic(MUXCY)toprovidefastarithmeticcarrycapabilityfor
high-speedarithmeticfunctions.ThesumlogicformedfromtwoXORgatesis
implementedusingLUTsandthededicatedcarry-XORs(XORCY).Inaddition,XST
benetsfromadedicatedcarry-ANDs(MULTAND)resourceforhigh-speedmultiplier
implementation.
LoadableFunctionsinMacroGeneration
ForLoadablefunctionsXSTprovidesthefollowingelements:
•LoadableUp,DownandUp/DownBinaryCounters
•LoadableUp,DownandUp/DownAccumulators
XSTcanprovidesynchronouslyloadable,cascadablebinarycountersandaccumulators
inferredintheHDLow.Fastcarrylogicisusedtocascadethedifferentstagesof
themacros.SynchronousloadingandcountfunctionsarepackedinthesameLUT
primitiveforoptimalimplementation.
ForUp/Downcountersandaccumulators,XSTusesdedicatedcarry-ANDstoimprove
performance.
MultiplexersinMacroGeneration
Formultiplexers,theMacroGeneratorprovidesthefollowingtwoarchitectures:
•MUXFxbasedmultiplexers
•DedicatedCarry-MUXsbasedmultiplexers
ForVirtex®-4devices,XSTcanimplementmultiplexersusingtheprimitivesshownin
thefollowingtable.
MultiplexerCLBPrimitive
16:1singleCLBMUXF7
32:1acrosstwoCLBsMUXF8
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Chapter4:XSTFPGAOptimization
Tobettercontroltheimplementationoftheinferredmultiplexer,XSToffersaway
toselectthegenerationofeithertheMUXF5/MUXF6orDedicatedCarry-MUXs
architectures.TheattributeMUX_STYLE(MuxStyle)speciesthataninferred
multiplexerbeimplementedonaMUXFxbasedarchitectureifthevalueisMUXF,ora
DedicatedCarry-MUXsbasedarchitectureifthevalueisMUXCY.
Youcanapplythisattributetoeitherasignalthatdenesthemultiplexerortheinstance
nameofthemultiplexer.Thisattributecanalsobeglobal.
TheattributeMUX_EXTRACT(MuxExtraction)with,respectively,thevaluenoorforce
canbeusedtodisableorforcetheinferenceofthemultiplexer.
YoustillmayhaveMUXFxelementsinthenalnetlistevenifmultiplexerinferenceis
disabledusingtheMUX_EXTRACT(MuxExtraction)constraint.Theseelementscome
fromthegeneralmappingprocedureofBooleanequations.
PriorityEncodersinMacroGeneration
Theif/elsifstructuredescribedinPriorityEncodersHDLCodingTechniquesis
implementedwitha1-of-npriorityencoder.
XSTusestheMUXCYprimitivetochaintheconditionsofthepriorityencoder,which
resultsinitshigh-speedimplementation.
UsePriorityEncoderExtraction(PRIORITY_EXTRACT)toenableordisablepriority
encoderinference.
XSTdoesnotgenerallyinfer(andthereforedoesnotgenerate)alargenumberof
priorityencoders.Toenablepriorityencoders,usePriorityEncoderExtraction
(PRIORITY_EXTRACT)withtheforceoption.
DecodersinMacroGeneration
Adecoderisademultiplexerwhoseinputsareallconstantwithdistinctone-hot(or
one-cold)codedvalues.Ann-bitor1-of-mdecoderismainlycharacterizedbyanm-bit
dataoutputandann-bitselectioninput,suchthat:
n**(2-1)<m<=n**2
OnceXSThasinferredthedecoder,theimplementationusestheMUXF5orMUXCY
primitivedependingonthesizeofthedecoder.
UseDecoderExtraction(DECODER_EXTRACT)toenableordisabledecoderinference.
RAMsinMacroGeneration
TwotypesofRAMareavailableduringinferenceandgeneration:
•DistributedRAM
IftheRAMisasynchronousREAD,DistributedRAMisinferredandgenerated.
•BlockRAM(default)
IftheRAMissynchronousREAD,blockRAMisinferred.Inthiscase,XSTcan
implementblockRAMordistributedRAM.
PrimitivesUsedbyXST
Thissectionappliestothefollowingdevices:
•Virtex®-4
•Spartan®-3
Forthesedevices,XSTusestheprimitivesshowninthefollowingtable.
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Chapter4:XSTFPGAOptimization
RAMClockEdgePrimitives
Single-PortSynchronousDistributed
RAM
DistributedSingle-PortRAMwith
positiveclockedge
RAM16X1S,RAM16X2S,RAM16X4S,
RAM16X8S,RAM32X1S,RAM32X2S,
RAM32X4S,RAM32X8S,RAM64X1S,
RAM64X2S,RAM128X1S
Single-PortSynchronousDistributed
RAM
DistributedSingle-PortRAMwith
negativeclockedge
RAM16X1S_1,RAM32X1S_1,
RAM64X1S_1,RAM128X1S_1
Dual-PortSynchronousDistributed
RAM
DistributedDual-PortRAMwith
positiveclockedge
RAM16X1D,RAM32X1D,RAM64X1D
Dual-PortSynchronousDistributed
RAM
DistributedDual-PortRAMwith
negativeclockedge
RAM16X1D_1,RAM32X1D_1,
RAM64X1D_1
Single-PortSynchronousBlockRAMN/ARAMB4_Sn
Dual-PortSynchronousBlockRAMN/ARAMB4_Sm_Sn
ControllingImplementationofInferredRAM
TobettercontroltheimplementationoftheinferredRAM,XSToffersawaytocontrol
RAMinference,andtoselectthegenerationofdistributedRAMorblockRAMs(if
possible).
TheRAMStyle(RAM_STYLE)attributespeciesthataninferredRAMbegenerated
using:
•BlockRAMifthevalueisblock
•DistributedRAMifthevalueisdistributed
ApplytheRAMStyle(RAM_STYLE)attributeto:
•AsignalthatdenestheRAM,or
•TheinstancenameoftheRAM
TheRAMStyle(RAM_STYLE)attributecanalsobeglobal.
IftheRAMresourcesarelimited,XSTcangenerateadditionalRAMsusingregisters.
TogenerateadditionalRAMsusingregisters,useRAMExtraction(RAM_EXTRACT)
withthevaluesettono.
ROMsinMacroGeneration
ThissectiondiscussesROMsinMacroGeneration,andincludes:
•InferringROMWhenAssignedContextsareConstants
•InferringROMfromanArray
•TypesofROMAvailableDuringInferenceandGeneration
•TypeofSynchronousROMInferredbyXST
•ApplyingRAMStyle
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Chapter4:XSTFPGAOptimization
InferringROMWhenAssignedContextsareConstants
AROMcanbeinferredwhenallassignedcontextsinacaseorif...elsestatementare
constants.MacroinferenceconsidersonlyROMsofatleast16wordswithnowidth
restriction.Forexample,thefollowingHardwareDescriptionLanguage(HDL)equation
canbeimplementedwithaROMof16wordsof4bits:
data=ifaddress=0000then0010
ifaddress=0001then1100
ifaddress=0010then1011
...
ifaddress=1111then0001
InferringROMfromanArray
AROMcanalsobeinferredfromanarraycomposedentirelyofconstants,asshownin
thefollowingcodingexample.
typeROM_TYPEisarray(15downto0)ofstd_logic_vector(3downto0);
constantROM:rom_type:=("0010","1100","1011",...,"0001");
...
data<=ROM(conv_integer(address));
ROMExtraction(ROM_EXTRACT)canbeusedtodisabletheinferenceofROMs.
•ToenableROMinference,setthevaluetoyes.
•TodisableROMinference,setthevaluetono.
Thedefaultisyes.
TypesofROMAvailableDuringInferenceandGeneration
TwotypesofROMareavailableduringinferenceandgeneration:
•DistributedROM
DistributedROMsaregeneratedbyusingtheoptimaltreestructureofLUT,MUXF5,
MUXF6,MUXF7andMUXF8primitives,whichallowscompactimplementation
oflargeinferredROMs.
•BlockROM
BlockROMsaregeneratedbyusingblockRAMresources.Whenasynchronous
ROMisidentied,itcanbeinferredeitherasadistributedROMplusaregister,orit
canbeinferredusingblockRAMresources.
TypeofSynchronousROMInferredbyXST
ROMStyle(ROM_STYLE)specieswhichtypeofsynchronousROMXSTinfersas
showninthefollowingtable.
OptionXSTBehavior
blockInferstheROMusingblockRAMresources,providedtheROMtsentirelyonasingleblockof
RAM.
distributedInfersadistributedROMplusregister.
auto(default)Determinesthemostefcientmethodtouse,andinferstheROMaccordingly.
ApplyingRAMStyle
YoucanapplyRAMStyle(RAM_STYLE)asaVHDLattributeoraVerilogmeta
commentto:
•Anindividualsignal
•TheentityormoduleoftheROM
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Chapter4:XSTFPGAOptimization
RAMStyle(RAM_STYLE)canalsobeappliedgloballyfrom:
•ISE®DesignSuitein:
Process>ProcessProperties
•Thecommandline
DSP48BlockResources
ThissectiondiscussesDSP48BlockResources,andincludes:
•MacroImplementationonDSP48Blocks
•DisablingAutomaticDSPResourceManagement
•MaximumMacroConguration
•AsynchronousSet/ResetSignals
•InterconnectedMacros
MacroImplementationonDSP48Blocks
XSTcanautomaticallyimplementthefollowingmacrosonaDSP48block:
•Adders/subtractors
•Accumulators
•Multipliers
•Multiplyadder/subtractors
•Multiplyaccumulate(MAC)
XSTalsosupportstheregisteredversionsofthesemacros.
MacroimplementationonDSP48blocksiscontrolledbyUseDSP48(USE_DSP48)with
adefaultvalueofauto.
Inautomode,XSTattemptstoimplementaccumulators,multipliers,multiply
adder/subtractorsandMACsonDSP48resources.XSTdoesnotimplement
adders/subtractorsonDSP48resourcesinautomode.Topushadder/subtractorsintoa
DSP48,setUseDSP48(USE_DSP48)toyes.
XSTperformsautomaticresourcecontrolinautomodeforallmacros.UsetheDSP
UtilizationRatio(DSP_UTILIZATION_RATIO)constraintinthismodetocontrol
availableDSP48resourcesforthesynthesis.Bydefault,XSTtriestoutilizeallavailable
DSP48resourcesasmuchaspossible.
DisablingAutomaticDSPResourceManagement
Ifthenumberofuser-speciedDSPslicesexceedsthenumberofavailableDSPresources
onthetargetFPGAdevice,XSTissuesawarning,andusesonlyavailableDSPresources
onthechipforsynthesis.DisableautomaticDSPresourcemanagementtoseethe
numberofDSPsthatXSTcanpotentiallyinferforaspecicdesign.Todisableautomatic
DSPresourcemanagement,setvalue=-1.
MaximumMacroConfiguration
Todeliverthebestperformance,XSTbydefaulttriestoinferandimplementthe
maximummacroconguration,includingasmanyregistersintheDSP48aspossible.
UseKeep(KEEP)toshapeamacroinaspecicway.Forexample,ifyourdesignhasa
multiplierwithtworegisterlevelsoneachinput,placeKeep(KEEP)constraintsonthe
outputsoftheseregisterstoexcludetherstregisterstagefromtheDSP48.
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Chapter4:XSTFPGAOptimization
AsynchronousSet/ResetSignals
DSP48blocksdonotsupportregisterswithAsynchronousSet/Resetsignals.Sincesuch
registerscannotbeabsorbedbyDSP48,thismayleadtosub-optimalperformance.The
AsynchronoustoSynchronous(ASYNC_TO_SYNC)constraintallowsyoutoreplace
AsynchronousSet/ResetsignalswithSynchronoussignalsthroughouttheentiredesign.
ThisallowsabsorptionofregistersbyDSP48,therebyimprovingqualityofresults.
ReplacingAsynchronousSet/ResetsignalsbySynchronoussignalsmakesthegenerated
NGCnetlistNOTequivalenttotheinitialRTLdescription.Youmustensurethat
thesynthesizeddesignsatisestheinitialspecication.Formoreinformation,see
AsynchronoustoSynchronous(ASYNC_TO_SYNC).
Formoreinformationonindividualmacroprocessing,see:
XSTHDLCodingTechniques
InterconnectedMacros
Ifyourdesigncontainsseveralinterconnectedmacros,whereeachmacrocanbe
implementedonDSP48,XSTattemptstointerconnectDSP48blocksusingfast
BCIN/BCOUTandPCIN/PCOUTconnections.Suchsituationsaretypicalinlterand
complexmultiplierdescriptions.
XSTcanbuildcomplexDSPmacrosandDSP48chainsacrossthehierarchywhenKeep
Hierarchy(KEEP_HIERARCHY)issettono.ThisisthedefaultinISE®DesignSuite.
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Chapter4:XSTFPGAOptimization
MappingLogicOntoBlockRAM
Ifyourdesigndoesnottintothetargetdevice,youcanplacesomeofthedesignlogic
intounusedblockRAM:
1.PutthepartoftheRTLdescriptiontobeplacedintoblockRAMinaseparate
hierarchicalblock.
2.AttachaBRAM_MAP(MapLogiconBRAM)constrainttotheseparatehierarchical
block,eitherdirectlyinHardwareDescriptionLanguage(HDL)code,orintheXST
ConstraintFile(XCF).
XSTcannotautomaticallydecidewhichlogiccanbeplacedinblockRAM.
Logicplacedintoaseparateblockmustsatisfythefollowingcriteria:
•Alloutputsareregistered.
•Theblockcontainsonlyonelevelofregisters,whichareoutputregisters.
•Alloutputregistershavethesamecontrolsignals.
•TheoutputregistershaveaSynchronousResetsignal.
•Theblockdoesnotcontainmultisourcesortristatebuses.
•Keep(KEEP)isnotallowedonintermediatesignals.
XSTattemptstomapthelogicontoblockRAMduringtheAdvancedSynthesisstep.
Ifanyofthelistedrequirementsarenotsatised,XSTdoesnotmapthelogiconto
blockRAM,andissuesawarning.IfthelogiccannotbeplacedinasingleblockRAM
primitive,XSTspreadsitoverseveralblockRAMs.
MappingLogicOntoBlockRAMLogFileExampleOne
...
=============================================================
*HDLSynthesis*
=============================================================
eis"bram_map_1.vhd".
Found4-bitregisterforsignal<RES>.
Found4-bitadderforsignal<$n0001>createdatline29.
Summary:
inferred4D-typeflip-flop(s).
inferred1Adder/Subtractor(s).
Unit<logic_bram_1>synthesized.
=============================================================
*AdvancedHDLSynthesis*
=============================================================
...
Entity<logic_bram_1>mappedonBRAM.
...
=============================================================
HDLSynthesisReport
MacroStatistics
#BlockRAMs:1
256x4-bitsingle-portblockRAM:1
=============================================================
...
Frontmatter
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Chapter4:XSTFPGAOptimization
MappingLogicOntoBlockRAMLogFileExampleTwo
...
=============================================================
*AdvancedHDLSynthesis*
=============================================================
...
INFO:Xst:1789-Unabletomapblock<no_logic_bram>onBRAM.
OutputFF<RES>musthaveasynchronousreset.
8-BitAddersWithConstantinaSingleBlockRamPrimitiveVHDLCoding
Example
--
--Thefollowingexampleplaces8-bitadderswith
--constantinasingleblockRAMprimitive
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitylogic_bram_1is
port(clk,rst:instd_logic;
A,B:inunsigned(3downto0);
RES:outunsigned(3downto0));
attributebram_map:string;
attributebram_mapoflogic_bram_1:entityis"yes";
endlogic_bram_1;
architecturebehoflogic_bram_1is
begin
process(clk)
begin
if(clk’eventandclk=’1’)then
if(rst=’1’)then
RES<="0000";
else
RES<=A+B+"0001";
endif;
endif;
endprocess;
endbeh;
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Chapter4:XSTFPGAOptimization
8-BitAddersWithConstantinaSingleBlockRamPrimitiveVerilogCoding
Example
//
//Thefollowingexampleplaces8-bitadderswith
//constantinasingleblockRAMprimitive
//
(*bram_map="yes"*)
modulev_logic_bram_1(clk,rst,A,B,RES);
inputclk,rst;
input[3:0]A,B;
output[3:0]RES;
reg[3:0]RES;
always@(posedgeclk)
begin
if(rst)
RES<=4’b0000;
else
RES<=A+B+8’b0001;
end
endmodule
Frontmatter
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Chapter4:XSTFPGAOptimization
AsynchronousResetVHDLCodingExample
--
--Inthefollowingexample,anasynchronousresetisusedand
--so,thelogicisnotmappedontoblockRAM
--
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitylogic_bram_2is
port(clk,rst:instd_logic;
A,B:inunsigned(3downto0);
RES:outunsigned(3downto0));
attributebram_map:string;
attributebram_mapoflogic_bram_2:entityis"yes";
endlogic_bram_2;
architecturebehoflogic_bram_2is
begin
process(clk,rst)
begin
if(rst=’1’)then
RES<="0000";
elsif(clk’eventandclk=’1’)then
RES<=A+B+"0001";
endif;
endprocess;
endbeh;
AsynchronousResetVerilogCodingExample
//
//Inthefollowingexample,anasynchronousresetisusedand
//so,thelogicisnotmappedontoblockRAM
//
(*bram_map="yes"*)
modulev_logic_bram_2(clk,rst,A,B,RES);
inputclk,rst;
input[3:0]A,B;
output[3:0]RES;
reg[3:0]RES;
always@(posedgeclkorposedgerst)
begin
if(rst)
RES<=4’b0000;
else
RES<=A+B+8’b0001;
end
endmodule
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Chapter4:XSTFPGAOptimization
Flip-FlopRetiming
ThissectiondiscussesFlip-FlopRetiming,andincludes:
•AboutFlip-FlopRetiming
•GlobalOptimization
•Flip-FlopRetimingMessages
•LimitationsofFlip-FlopRetiming
•ControllingFlip-FlopRetiming
AboutFlip-FlopRetiming
Flip-opretimingconsistsofmovingip-opsandlatchesacrosslogicforthepurpose
ofimprovingtiming,thusincreasingclockfrequency.
Flip-opretimingcanbeeitherforwardorbackward:
•Forwardretimingmovesasetofip-opsthataretheinputofaLUTtoasingle
ip-opatitsoutput.
•Backwardretimingmovesaip-opthatisattheoutputofaLUTtoasetof
ip-opsatitsinput.
Flip-opretimingcan:
•Signicantlyincreasethenumberofip-ops
•Removesomeip-ops
Nevertheless,thebehaviorofthedesignsremainsthesame.Onlytimingdelaysare
modied.
GlobalOptimization
Flip-opretimingispartofglobaloptimization.Itrespectsthesameconstraintsas
allotheroptimizationtechniques.Sinceretimingisincremental,aip-opthatisthe
resultofaretimingcanbemovedagaininthesamedirection(forwardorbackward)
ifitresultsinbettertiming.Theonlylimitfortheretimingoccurswhenthetiming
constraintsaresatised,orifnomoreimprovementsintimingcanbeobtained.
Flip-FlopRetimingMessages
Foreachip-opmoved,amessageisprintedspecifying:
•Theoriginalandnewip-opnames
•Whetheritisaforwardorbackwardretiming
LimitationsofFlip-FlopRetiming
Flip-opretiminghasthefollowinglimitations:
•Flip-opretimingisnotappliedtoip-opsthathavetheIOB=TRUEproperty.
•Flip-opsarenotmovedforwardiftheip-oportheoutputsignalhastheKeep
(KEEP)property .
•Flip-opsarenotmovedbackwardiftheinputsignalhastheKeep(KEEP)property .
•Instantiatedip-opsaremovedonlyiftheOptimizeInstantiatedPrimitives
constraintorcommandlineoptionissettoyes.
•Flip-FlopsaremovedacrossinstantiatedprimitivesonlyiftheOptimizeInstantiated
Primitivescommandlineoptionorconstraintissettoyes.
•Flip-opswithbothasetandaresetarenotmoved.
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Chapter4:XSTFPGAOptimization
ControllingFlip-FlopRetiming
Usethefollowingconstraintstocontrolip-opretiming:
•RegisterBalancing(REGISTER_BALANCING)
•MoveFirstStage(MOVE_FIRST_STAGE)
•MoveLastStage(MOVE_LAST_STAGE)
Partitions
XSTnowsupportsPartitionsinplaceofIncrementalSynthesis.IncrementalSynthesisis
nolongersupported.Theincremental_synthesisandresynthesizeconstraintsareno
longersupported.FormoreinformationonPartitions,seetheISE®DesignSuiteHelp.
SpeedOptimizationUnderAreaConstraint
XSTperformstimingoptimizationundertheareaconstraint.Thisoptionisnamed:
•LUT-FFPairsUtilizationRatio
Virtex®-5devices
•Slice(LUT-FFPairs)UtilizationRatio(SLICE_UTILIZATION_RATIO)”
AllotherFPGAdevices
DeneinISE®DesignSuitewith:
Process>ProcessProperties>XSTSynthesisOptions.
Bydefaultthisconstraintissetto100%oftheselecteddevicesize.
ThisconstrainthasinuenceatlowlevelsynthesisonlyItdoesnotcontrolinference.
Ifthisconstraintisspecied,XSTmakesanareaestimation.Ifthespeciedconstraint
ismet,XSTcontinuestimingoptimizationtryingnottoexceedtheconstraint.Ifthe
designislargerthanrequested,XSTtriestoreducethearearst.Iftheareaconstraint
ismet,XSTbeginstimingoptimization.
ExampleOne(100%)
Inthefollowingexampletheareaconstraintwasspeciedas100%andinitialestimation
showsthatinfactitoccupies102%oftheselecteddevice.XSTbeginsoptimizationand
reaches95%.
...
================================================================
*
*LowLevelSynthesis
*
================================================================
Foundareaconstraintratioof100(+5)onblocktge,
actualratiois102.
Optimizingblock<tge>tomeetratio100(+5)of1536
slices:
Areaconstraintismetforblock<tge>,finalratiois95.
================================================================
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Chapter4:XSTFPGAOptimization
ExampleTwo(70%)
Iftheareaconstraintcannotbemet,XSTignoresitduringtimingoptimizationandruns
lowlevelsynthesistoachievethebestfrequency.Inthefollowingexample,thetarget
areaconstraintissetto70%.SinceXSTwasunabletosatisfythetargetareaconstraint,
XSTissuesthefollowingwarning:
...
================================================================
*
*LowLevelSynthesis
*
================================================================
Foundareaconstraintratioof70(+5)onblockfpga_hm,
actualratiois64.
Optimizingblock<fpga_hm>tomeetratio70(+5)of1536
slices:
WARNING:Xst-Areaconstraintcouldnotbemetforblock<tge>,
finalratiois94
...
================================================================
...
Note(+5)standsforthemaxmarginoftheareaconstraint.Iftheareaconstraintis
notmet,butthedifferencebetweentherequestedareaandobtainedareaduringarea
optimizationislessorequalthen5%,thenXSTrunstimingoptimizationtakinginto
accounttheachievedarea,notexceedingit.
ExampleThree(55%)
Inthefollowingexample,theareawasspeciedas55%.XSTachievedonly60%.But
takingintoaccountthatthedifferencebetweenrequestedandachievedareaisnotmore
than5%,XSTconsidersthattheareaconstraintwasmet.
...
================================================================
*
*LowLevelSynthesis
*
================================================================
Foundareaconstraintratioof55(+5)onblockfpga_hm,
actualratiois64.
Optimizingblock<fpga_hm>tomeetratio55(+5)of1536
slices:
Areaconstraintismetforblock<fpga_hm>,finalratiois60.
================================================================
...
Insomesituations,itisimportanttodisableautomaticresourcemanagement.Todoso,
specify-1asthevalueforSLICE_UTILIZATION_RATIO.
Slice(LUT-FFPairs)UtilizationRatio(SLICE_UTILIZATION_RATIO)canbeattachedto
aspecicblockofadesign.Youcanspecifyanabsolutenumberofslices(orFF-LUT
pairs)asapercentageofthetotalnumber.
Frontmatter
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Chapter4:XSTFPGAOptimization
FPGADeviceOptimizationReportSection
ThissectiondiscussesFPGADeviceOptimizationReportSection,andincludes:
•AboutFPGADeviceOptimizationReportSection
•CellUsageReport
•TimingReport
AboutFPGADeviceOptimizationReportSection
Duringdesignoptimization,XSTreports:
•Potentialremovalofequivalentip-ops
Twoip-ops(latches)areequivalentwhentheyhavethesamedataandcontrol
pins.
•Registerreplication
Registerreplicationisusedto:
–Improvetimingperformance
–SatisfyMAX_FANOUTconstraints
UseRegisterDuplication(REGISTER_DUPLICATION)toturnoffregister
replication.
FPGADeviceOptimizationReportSectionExample
Startinglowlevelsynthesis...
Optimizingunit<down4cnt>...
Optimizingunit<doc_readwrite>...
...
Optimizingunit<doc>...
Buildingandoptimizingfinalnetlist...
TheFF/Latch<doc_readwrite/state_D2>inUnit<doc>is
equivalenttothefollowing2FFs/Latches,
whichwillberemoved:<doc_readwrite/state_P2>
<doc_readwrite/state_M2>Register
doc_reset_I_reset_outhasbeenreplicated2time(s)
Registerwr_lhasbeenreplicated2time(s)
CellUsageReport
TheCellUsagesectionoftheFinalReportgivesthecountofalltheprimitivesusedin
thedesign.Theprimitivesareclassiedinthefollowinggroups:
•BELSCellUsage
•Flip-FlopsandLatchesCellUsage
•RAMSCellUsage
•SHIFTERSCellUsage
•TristatesCellUsage
•ClockBuffersCellUsage
•IOBuffersCellUsage
•LOGICALCellUsage
•OTHERCellUsage
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Chapter4:XSTFPGAOptimization
BELSCellUsage
TheBELSgroupintheCellUsagesectionoftheFinalReportcontainsallthelogicalcells
thatarebasicelementsofthetargetedFPGAdevicefamily ,forexample:
•LUTs
•MUXCY
•MUXF5
•MUXF6
•MUXF7
•MUXF8
Flip-FlopsandLatchesCellUsage
TheFlip-FlopsandLatchesgroupintheCellUsagesectionoftheFinalReportcontains
alltheip-opsandlatchesthatareprimitivesofthetargetedFPGAdevicefamily,for
example:
•FDR
•FDRE
•LD
RAMSCellUsage
TheRAMSgroupintheCellUsagesectionoftheFinalReportcontainsalltheRAMs.
SHIFTERSCellUsage
TheSHIFTERSgroupintheCellUsagesectionoftheFinalReportcontainsalltheshift
registersthatusetheVirtex®deviceprimitive:
•TSRL16
•SRL16_1
•SRL16E
•SRL16E_1
•SRLC
TristatesCellUsage
TheTristatesgroupintheCellUsagesectionoftheFinalReportcontainsallthetristate
primitives:
BUFT
ClockBuffersCellUsage
TheClockBuffersgroupintheCellUsagesectionoftheFinalReportcontainsallthe
clockbuffers:
•BUFG
•BUFGP
•BUFGDLL
Frontmatter
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Chapter4:XSTFPGAOptimization
IOBuffersCellUsage
TheIOBuffersgroupintheCellUsagesectionoftheFinalReportcontainsallthe
standardI/Obuffers(excepttheclockbuffer):
•IBUF
•OBUF
•IOBUF
•OBUFT
•IBUF_GTL...
LOGICALCellUsage
TheLOGICALgroupintheCellUsagesectionoftheFinalReportcontainsallthelogical
cellsprimitivesthatarenotbasicelements:
•AND2
•OR2...
OTHERCellUsage
TheOTHERgroupintheCellUsagesectionoftheFinalReportcontainsallthecellsthat
havenotbeenclassiedinthepreviousgroups.
CellUsageReportExample
==================================================
...
CellUsage:
#BELS:70
#LUT2:34
#LUT3:3
#LUT4:34
#FlipFlops/Latches:9
#FDC:8
#FDP:1
#ClockBuffers:1
#BUFGP:1
#IOBuffers:24
#IBUF:16
#OBUF:8
==================================================
WhereXSTestimatesthenumberofslicesandgives,forexample,thenumberof
ip-ops,IOBs,andBRAMS.ThisreportcloselyresemblesthereportproducedbyMAP .
Shorttablesgiveinformationabout:
•Thenumberofclocksinthedesign,howeachclockisbuffered,andhowmany
loadsithas
•Thenumberofasynchronousset/resetsignalsinthedesign,howeachsignalis
buffered,andhowmanyloadsithas
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Chapter4:XSTFPGAOptimization
TimingReport
ThissectiondiscussesTimingReport,andincludes:
•AboutTimingReport
•TimingReportTimingSummarySection
•TimingReportTimingDetailSection
•TimingReportPathsandPorts
AboutTimingReport
Attheendofsynthesis,XSTreportsthetiminginformationforthedesign.TheTiming
Reportshowstheinformationforallfourpossibledomainsofanetlist:
•registertoregister
•inputtoregister
•registertooutpad
•inpadtooutpad
Frontmatter
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Chapter4:XSTFPGAOptimization
TimingReportExample
Thesetimingnumbersareonlyasynthesisestimate.Foraccuratetiminginformation,
seetheTRACEreportgeneratedafterplace-and-route.
ClockInformation:
------------------
-----------------------------------+------------------------+-------+
ClockSignal|Clockbuffer(FFname)|Load|
-----------------------------------+------------------------+-------+
CLK|BUFGP|11|
-----------------------------------+------------------------+-------+
AsynchronousControlSignalsInformation:
----------------------------------------
-------------------------------------+-------------------------------+-------+
ControlSignal|Buffer(FFname)|Load|
-------------------------------------+-------------------------------+-------+
rstint(MACHINE/current_state_Out01:O)|NONE(sixty/lsbcount/qoutsig_3)|4|
RESET|IBUF|3|
sixty/msbclr(sixty/msbclr:O)|NONE(sixty/msbcount/qoutsig_3)|4|
-------------------------------------+-------------------------------+-------+
TimingSummary:
---------------
SpeedGrade:-12
Minimumperiod:2.644ns(MaximumFrequency:378.165MHz)
Minimuminputarrivaltimebeforeclock:2.148ns
Maximumoutputrequiredtimeafterclock:4.803ns
Maximumcombinationalpathdelay:4.473ns
TimingDetail:
--------------
Allvaluesdisplayedinnanoseconds(ns)
=========================================================================
Timingconstraint:DefaultperiodanalysisforClock’CLK’
Clockperiod:2.644ns(frequency:378.165MHz)
Totalnumberofpaths/destinationports:77/11
-------------------------------------------------------------------------
Delay:2.644ns(LevelsofLogic=3)
Source:MACHINE/current_state_FFd3(FF)
Destination:sixty/msbcount/qoutsig_3(FF)
SourceClock:CLKrising
DestinationClock:CLKrising
DataPath:MACHINE/current_state_FFd3tosixty/msbcount/qoutsig_3
GateNet
Cell:in->outfanoutDelayDelayLogicalName(NetName)
----------------------------------------------------
FDC:C->Q80.2720.642MACHINE/current_state_FFd3(MACHINE/current_state_FFd3)
LUT3:I0->O30.1470.541Ker81(clkenable)
LUT4_D:I1->O10.1470.451sixty/msbce(sixty/msbce)
LUT3:I2->O10.1470.000sixty/msbcount/qoutsig_3_rstpot(N43)
FDC:D0.297sixty/msbcount/qoutsig_3
----------------------------------------
Total2.644ns(1.010nslogic,1.634nsroute)
(38.2%logic,61.8%route)
Frontmatter
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Chapter4:XSTFPGAOptimization
TimingReportTimingSummarySection
TheTimingSummarysectionoftheTimingReportsummarizesthetimingpathsforall
fourdomains:
•Thepathfromanyclocktoanyclockinthedesign:
Minimumperiod:7.523ns(MaximumFrequency:132.926MHz)
•Themaximumpathfromallprimaryinputstothesequentialelements:
Minimuminputarrivaltimebeforeclock:8.945ns
•Themaximumpathfromthesequentialelementstoallprimaryoutputs:
Maximumoutputrequiredtimebeforeclock:14.220ns
•Themaximumpathfrominputstooutputs:
Maximumcombinationalpathdelay:10.899ns
Ifthereisnopathinthedomain,Nopathfoundisprintedinsteadofthevalue.
TimingReportTimingDetailSection
TheTimingDetailsectionoftheTimingReportdescribesthemostcriticalpathindetail
foreachregion:
•Startpointofthepath
•Endpointofthepath
•Maximumdelayofthepath
•Slack
Thestartandendpointscanbe:
•Clock(withthephase:rising/falling),or
•Port
PathfromClock’ sysclk’risingtoClock’sysclk’rising:7.523ns(Slack:-7.523ns)
Thedetailedpathshows:
•Celltype
•Inputandoutputofthisgate
•Fanoutattheoutput
•Gatedelay
•Netdelayestimate
•Nameoftheinstance.
Whenenteringahierarchicalblock,beginscopeisprinted.Whenexitingahierarchical
block,endscopeisprinted.
Theprecedingreportcorrespondstothefollowingschematic.
Frontmatter
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Chapter4:XSTFPGAOptimization
TimingReportSchematic
TimingReportPathsandPorts
TheTimingReportsectionshowsthenumberofanalyzedpathsandports.IfXSTis
runwithtimingconstraints,italsoshowsthenumberoffailedpathsandports.The
numberofanalyzedandfailedpathsshowshowmanytimingproblemstherearein
thedesign.Thenumberofanalyzedandfailedportsmayshowhowtheyarespreadin
thedesign.Thenumberofportsinatimingreportrepresentthenumberofdestination
elementsforatimingconstraint.
Forexample,ifyouusethefollowingtimingconstraints:
TIMESPEC"TSidentifier"=FROM"source_group"TO"dest_group"value
units;
thenthenumberofportscorrespondstothenumberofelementsinthedestination
group.
Foragiventimingconstraint,XSTmayreportthatthenumberoffailedpathsis100,
butthatthenumberoffaileddestinationportsisonlytwoip-ops.Inthatcase,itis
sufcienttoanalyzethedesigndescriptionforthesetwoip-opsonlyinorderto
detectthechangesnecessarytomeettiming.
ImplementationConstraints
XSTwritesallimplementationconstraintsgeneratedfromHardwareDescription
Language(HDL)orconstraintleattributes(suchasLOC)intotheoutputNGCle.
Keep(KEEP)propertiesaregeneratedduringbufferinsertionformaximumfanout
controlorforoptimization.
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Chapter4:XSTFPGAOptimization
FPGADevicePrimitiveSupport
ThissectiondiscussesFPGADevicePrimitiveSupport,andincludes:
•AboutFPGADevicePrimitiveSupport
•GeneratingPrimitivesThroughAttributes
•PrimitivesandBlackBoxes
•VHDLandVerilogDevicePrimitivesLibraries
•ReportingofInstantiatedDevicePrimitives
•PrimitivesRelatedConstraints
•PrimitivesCodingExamples
•UsingtheUniMacroLibrary
AboutFPGADevicePrimitiveSupport
XSTenablesyoutoinstantiatedeviceprimitivesdirectlyinVHDLorVerilogcode.
PrimitivessuchasthefollowingcanbemanuallyinsertedinaHardwareDescription
Language(HDL)designthroughinstantiation:
•MUXCY_L
•LUT4_L
•CLKDLL
•RAMB4_S1_S16
•IBUFG_PCI33_5
•NAND3b2
Theseprimitives:
•ArecompiledintheUNISIMlibrary
•ArenotoptimizedbyXSTbydefault
•AreavailableinthenalNGCle
UseOptimizeInstantiatedPrimitivessynthesistooptimizeinstantiatedprimitivesand
obtainbetterresults.Timinginformationisavailableformostoftheprimitives,allowing
XSTtoperformefcienttiming-drivenoptimization.
InordertosimplifyinstantiationofcomplexprimitivesasRAMs,XSTsupportsan
additionallibrarycalledUniMacro.
Formoreinformation,seetheLibrariesGuides.
Frontmatter
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Chapter4:XSTFPGAOptimization
GeneratingPrimitivesThroughAttributes
Someprimitivescanbegeneratedthroughattributes:
•BufferType(BUFFER_TYPE)
Canbeassignedtotheprimaryinputorinternalsignaltoforcetheuseofthe
following:
–BUFGDLL
–IBUFG
–BUFR
–BUFGP
Thesameconstraintscanbeusedtodisablebufferinsertion.
•I/OStandard(IOSTANDARD)
CanbeusedtoassignanI/OstandardtoanI/Oprimitive.
Forexample,thefollowingassignsPCI33_5I/OstandardtotheI/Oport:
//synthesisattributeIOSTANDARDofin1isPCI33_5
PrimitivesandBlackBoxes
Theprimitivesupportisbasedontheconceptoftheblackbox.Forinformationonthe
basicsofblackboxsupport,seeSafeFSMImplementation.
Thereisasignicantdifferencebetweenblackboxandprimitivesupport.Assumeyou
haveadesignwithasubmodulecalledMUXF5.Ingeneral,theMUXF5canbeyourown
functionalblockoraXilinx®deviceprimitive.ToavoidconfusionabouthowXST
interpretsthismodule,attachBoxType(BOX_TYPE)tothecomponentdeclarationof
MUXF5.
IfBoxType(BOX_TYPE)isattachedtotheMUXF5withavalueof:
•primitive,orblack_box
XSTtriestointerpretthismoduleasaXilinxdeviceprimitiveanduseitsparameters,
forinstance,incriticalpathestimation.
•user_black_box
XSTprocessesitasaregularuserblackbox.
IfthenameoftheuserblackboxisthesameasthatofaXilinxdeviceprimitive,XST
renamesittoauniquenameandissuesawarning.Forexample,MUX5couldbe
renamedtoMUX51asshowninthefollowinglogleexample.
...
================================================================
*LowLevelSynthesis*
================================================================
WARNING:Xst:79-Model’muxf5’hasdifferentcharacteristicsin
destinationlibrary
WARNING:Xst:80-Modelnamehasbeenchangedto’muxf51’
...
IfBoxType(BOX_TYPE)isnotattachedtotheMUXF5,XSTprocessesthisblockasa
userhierarchicalblock.IfthenameoftheuserblackboxisthesameasthatofaXilinx
deviceprimitive,XSTrenamesittoauniquenameandissuesawarning.
Frontmatter
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Chapter4:XSTFPGAOptimization
VHDLandVerilogDevicePrimitivesLibraries
XSTprovidesdedicatedlibraries,bothinVHDLandVerilog,simplifyinginstantiationof
Xilinx®deviceprimitivesinyourHDLsourcecodeTheselibrariescontainthecomplete
setofXilinxdeviceprimitivesdeclarationswithaBoxType(BOX_TYPE)constraint
attachedtoeachcomponent.
DeviceLibraries
InVHDL,declarelibraryUNISIMwithitspackagevcomponentsinyoursourcecode:
libraryunisim;
useunisim.vcomponents.all;
ThesourcecodeofthispackagecanbefoundinthefollowingleoftheXSTinstallation:
vhdl\src\unisims\unisims_vcomp.vhd
InVerilog,theUNISIMlibraryisprecompiled.XSTautomaticallylinksitwithyour
design.
PrimitiveInstantiationGuidelines
UseUPPERCASEforgeneric(VHDL)andparameter(Verilog)valueswheninstantiating
primitives.ForexampletheODDRelementhasthefollowingcomponentdeclaration
intheUNISIMlibrary:
componentODDR
generic
(DDR_CLK_EDGE:string:="OPPOSITE_EDGE";
INIT:bit:=’0’;
SRTYPE:string:="SYNC");
port(Q:outstd_ulogic;
C:instd_ulogic;
CE:instd_ulogic;
D1:instd_ulogic;
D2:instd_ulogic;
R:instd_ulogic;
S:instd_ulogic);
endcomponent;
Whenyouinstantiatethisprimitiveinyourcode,thevaluesofDDR_CLK_EDGEand
SRTYPEgenericsmustbeinUPPERCASE.Ifnot,XSTissuesawarningstatingthat
unknownvaluesareused.
Someprimitives,suchasLUT1,enableyoutouseanINITduringinstantiation.Thetwo
waystopassanINITtothenalnetlistare:
•AttachanINITattributetotheinstantiatedprimitive.
•PasstheINITwiththegenericsmechanism(VHDL),ortheparametersmechanism
(Verilog).Xilinxrecommendsthismethod,sinceitallowsyoutousethesamecode
forsynthesisandsimulation.
ReportingofInstantiatedDevicePrimitives
XSTdoesnotissueanymessageconcerninginstantiationofinstantiateddevice
primitivesduringHDLsynthesisbecausetheBoxType(BOX_TYPE)attributewithits
value,primitive,isattachedtoeachprimitiveintheUNISIMlibrary.
Frontmatter
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Chapter4:XSTFPGAOptimization
XSTissuesawarningasshowninthelogleexamplebelowif:
•Youinstantiateablock(nonprimitive)inyourdesign
AND
•Theblockhasnocontents(nologicdescription)
OR
•Theblockhasalogicdescription
AND
•YouattachaBoxType(BOX_TYPE)constrainttoitwithavalueofuser_black_box.
LogFileExample
...
AnalyzingEntity<black_b>(Architecture<archi>).
WARNING:(VHDL_0103).c:\jm\des.vhd(Line23).
GeneratingaBlackBoxforcomponent<my_block>.
Entity<black_b>analyzed.Unit<black_b>generated.
...
PrimitivesRelatedConstraints
•BoxType(BOX_TYPE)
•ThePARconstraintsthatcanbepassedfromHDLtoNGCwithoutprocessing
PrimitivesCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
PassinganINITValueViatheINITConstraintVHDLCodingExample
--
--PassinganINITvalueviatheINITconstraint.
--
libraryieee;
useieee.std_logic_1164.all;
libraryunisim;
useunisim.vcomponents.all;
entityprimitive_1is
port(I0,I1:instd_logic;
O:outstd_logic);
endprimitive_1;
architecturebehofprimitive_1is
attributeINIT:string;
attributeINITofinst:labelis"1";
begin
inst:LUT2portmap(I0=>I0,I1=>I1,O=>O);
endbeh;
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Chapter4:XSTFPGAOptimization
PassinganINITValueViatheINITConstraintVerilogCodingExample
//
//PassinganINITvalueviatheINITconstraint.
//
modulev_primitive_1(I0,I1,O);
inputI0,I1;
outputO;
(*INIT="1"*)
LUT2inst(.I0(I0),.I1(I1),.O(O));
endmodule
PassinganINITValueViatheGenericsMechanismVHDLCodingExample
--
--PassinganINITvalueviathegenericsmechanism.
--
libraryieee;
useieee.std_logic_1164.all;
libraryunisim;
useunisim.vcomponents.all;
entityprimitive_2is
port(I0,I1:instd_logic;
O:outstd_logic);
endprimitive_2;
architecturebehofprimitive_2is
begin
inst:LUT2genericmap(INIT=>"1")
portmap(I0=>I0,I1=>I1,O=>O);
endbeh;
PassinganINITValueViatheParametersMechanismVerilogCoding
Example
//
//PassinganINITvalueviatheparametersmechanism.
//
modulev_primitive_2(I0,I1,O);
inputI0,I1;
outputO;
LUT2#(4’h1)inst(.I0(I0),.I1(I1),.O(O));
endmodule
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Chapter4:XSTFPGAOptimization
PassinganINITValueViatheDefparamMechanismVerilogCoding
Example
//
//PassinganINITvalueviathedefparammechanism.
//
modulev_primitive_3(I0,I1,O);
inputI0,I1;
outputO;
LUT2inst(.I0(I0),.I1(I1),.O(O));
defparaminst.INIT=4’h1;
endmodule
UsingtheUniMacroLibrary
ThissectiondiscussesUsingtheUniMacroLibrary ,andincludes:
•AboutUsingtheUniMacroLibrary
•UniMacroLibraryDeviceSupport
•UsingtheUniMacroLibraryinVHDL
•UsingtheUniMacroLibraryinVerilog
AboutUsingtheUniMacroLibrary
InordertosimplifyinstantiationofsuchcomplexprimitivesasRAMs,XSTsupportsan
additionallibrarycalledUniMacro.
Formoreinformation,seetheLibrariesGuides.
UniMacroLibraryDeviceSupport
TheUniMacrolibrarysupportsthefollowingdevices:
•Virtex®-4
•Virtex-5andnewer
UsingtheUniMacroLibraryinVHDL
InVHDL,declarethelibraryunimacrowithitspackagevcomponentsinyoursource
code:
libraryunimacro;
useunimacro.vcomponents.all;
ThesourcecodeofthispackageislocatedinthefollowingleintheXSTinstallation:
vhdl\src\unisims\unisims_vcomp.vhd
UsingtheUniMacroLibraryinVerilog
InVerilog,theUniMacrolibraryisprecompiled.XSTautomaticallylinksitwithyour
design.
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Chapter4:XSTFPGAOptimization
CoresProcessing
IfadesigncontainscoresrepresentedbyanElectronicDataInterchangeFormat(EDIF)
oranNGCle,XSTcanautomaticallyreadthemfortimingestimationandarea
utilizationcontrol.UseISE®DesignSuiteProcess>ProcessProperties>Synthesis
Options>ReadCorestoenableordisablethisfeature.Usingtheread_coresoptionof
theruncommandfromthecommandline,youcanalsospecifyoptimize.Thisenables
coresprocessing,andallowsXSTtointegratethecorenetlistintotheoveralldesign.XST
readscoresbydefault.
IfReadCoresisdisabled,XSTestimatesMaximumCombinationalPathDelayas6.639ns
(criticalpathgoesthroughasimpleANDfunction)andanareaofoneslice.
IfReadCoresisenabled,XSTissuesthefollowingmessagesduringLowLevelSynthesis:
...
============================================================
*
*LowLevelSynthesis
*
============================================================
Launcher:Executingedif2ngd-noa"my_add.edn""my_add.ngo"
INFO:NgdBuild-Release6.1i-edif2ngdG.21
INFO:NgdBuild-Copyright(c)1995-2003Xilinx,Inc.
Allrightsreserved.
Writingthedesignto"my_add.ngo"...
Loadingcore<my_add>fortimingandareainformation
forinstance<inst>.
============================================================
...
EstimationofMaximumCombinationalPathDelayis8.281nswithanareaofveslices.
Bydefault,XSTreadsElectronicDataInterchangeFormat(EDIF)andNGCcoresfrom
thecurrent(project)directory.Ifthecoresarenotintheprojectdirectory,specifythe
directoryinwhichthecoresarelocatedwithCoresSearchDirectories(-sd).
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Chapter4:XSTFPGAOptimization
CodingExample
InthefollowingVHDLcodingexample,theblockmy_addisanadder,whichis
representedasablackboxinthedesignwhosenetlistwasgeneratedbytheCORE
Generator™software.
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
entityread_coresis
port(
A,B:instd_logic_vector(7downto0);
a1,b1:instd_logic;
SUM:outstd_logic_vector(7downto0);
res:outstd_logic);
endread_cores;
architecturebehofread_coresis
componentmy_add
port(
A,B:instd_logic_vector(7downto0);
S:outstd_logic_vector(7downto0));
endcomponent;
begin
res<=a1andb1;
inst:my_addportmap(A=>A,B=>B,S=>SUM);
endbeh;
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Chapter4:XSTFPGAOptimization
SpecifyingINITandRLOC
UsetheUNISIMlibrarytodirectlyinstantiateLUTcomponentsinyourHardware
DescriptionLanguage(HDL)code.TospecifyafunctionthataparticularLUTmust
execute,applyanINITconstrainttotheinstanceoftheLUT.Toplaceaninstantiated
LUTorregisterinaparticularsliceofthechip,attachanRLOCconstrainttothesame
instance.
ItisnotalwaysconvenienttocalculateINITfunctionsanddifferentmethodsthatcanbe
usedtoachievethis.Instead,youcandescribethefunctionthatyouwanttomapontoa
singleLUTinyourVHDLorVerilogcodeinaseparateblock.
AttachingaMapEntityonaSingleLUT(LUT_MAP)constrainttothisblockindicatesto
XSTthatthisblockmustbemappedonasingleLUT.XSTautomaticallycalculatesthe
INITvaluefortheLUTandpreservesthisLUTduringoptimization.
XSTautomaticallyrecognizestheXC_MAPconstraintsupportedbySynopsys.
PassinganINITValueViatheLUT_MAPConstraintCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
ThefollowingcodingexamplesshowhowtopassanINITvalueusingtheLUT_MAP
constraint.
Intheseexamples,thetopblockcontainstheinstantiationoftwoANDgates,described
inand_oneandand_twoblocks.XSTgeneratestwoLUT2sanddoesnotmergethem.
Formoreinformation,see:
MapEntityonaSingleLUT(LUT_MAP)
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PassinganINITValueViatheLUT_MAPConstraintVHDLCodingExample
--
--MappingonLUTsviaLUT_MAPconstraint
--
libraryieee;
useieee.std_logic_1164.all;
entityand_oneis
port(A,B:instd_logic;
REZ:outstd_logic);
attributeLUT_MAP:string;
attributeLUT_MAPofand_one:entityis"yes";
endand_one;
architecturebehofand_oneis
begin
REZ<=AandB;
endbeh;
--------------------------------------------------
libraryieee;
useieee.std_logic_1164.all;
entityand_twois
port(A,B:instd_logic;
REZ:outstd_logic);
attributeLUT_MAP:string;
attributeLUT_MAPofand_two:entityis"yes";
endand_two;
architecturebehofand_twois
begin
REZ<=AorB;
endbeh;
--------------------------------------------------
libraryieee;
useieee.std_logic_1164.all;
entityinits_rlocs_1is
port(A,B,C:instd_logic;
REZ:outstd_logic);
endinits_rlocs_1;
architecturebehofinits_rlocs_1is
componentand_one
port(A,B:instd_logic;
REZ:outstd_logic);
endcomponent;
componentand_two
port(A,B:instd_logic;
REZ:outstd_logic);
endcomponent;
signaltmp:std_logic;
begin
inst_and_one:and_oneportmap(A=>A,B=>B,REZ=>tmp);
inst_and_two:and_twoportmap(A=>tmp,B=>C,REZ=>REZ);
endbeh;
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PassinganINITValueViatheLUT_MAPConstraintVerilogCodingExample
//
//MappingonLUTsviaLUT_MAPconstraint
//
(*LUT_MAP="yes"*)
modulev_and_one(A,B,REZ);
inputA,B;
outputREZ;
andand_inst(REZ,A,B);
endmodule
//--------------------------------------------------
(*LUT_MAP="yes"*)
modulev_and_two(A,B,REZ);
inputA,B;
outputREZ;
oror_inst(REZ,A,B);
endmodule
//--------------------------------------------------
modulev_inits_rlocs_1(A,B,C,REZ);
inputA,B,C;
outputREZ;
wiretmp;
v_and_oneinst_and_one(A,B,tmp);
v_and_twoinst_and_two(tmp,C,REZ);
endmodule
SpecifyingINITValueforaFlip-FlopCodingExamples
IfafunctioncannotbemappedonasingleLUT,XSTissuesanerrormessageand
interruptssynthesis.TodeneanINITvalueforaip-oporashiftregister,described
atRTLlevel,assignitsinitialvalueinthesignaldeclarationstage.Thisvalueisnot
ignoredduringsynthesisandispropagatedtothenalnetlistasanINITconstraint
attachedtotheip-oporshiftregister.
Inthefollowingcodingexamples,a4-bitregisterisinferredforsignaltmp.
AnINITvalueequal1011isattachedtotheinferredregisterandpropagatedtothe
nalnetlist.
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SpecifyingINITValueforaFlip-FlopVHDLCodingExample
--
--SpecificationonanINITvalueforaflip-flop,
--describedatRTLlevel
--
libraryieee;
useieee.std_logic_1164.all;
entityinits_rlocs_2is
port(CLK:instd_logic;
DI:instd_logic_vector(3downto0);
DO:outstd_logic_vector(3downto0));
endinits_rlocs_2;
architecturebehofinits_rlocs_2issignal
tmp:std_logic_vector(3downto0):="1011";
begin
process(CLK)
begin
if(clk’eventandclk=’1’)then
tmp<=DI;
endif;
endprocess;
DO<=tmp;
endbeh;
SpecifyingINITValueforaFlip-FlopVerilogCodingExample
//
//SpecificationonanINITvalueforaflip-flop,
//describedatRTLlevel
//
modulev_inits_rlocs_2(clk,di,do);
inputclk;
input[3:0]di;
output[3:0]do;
reg[3:0]tmp;
initialbegin
tmp=4’b1011;
end
always@(posedgeclk)
begin
tmp<=di;
end
assigndo=tmp;
endmodule
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Chapter4:XSTFPGAOptimization
SpecifyingINITandRLOCValuesforaFlip-FlopCodingExamples
Toinferaregisterandplaceitinaspeciclocationofachip,attachanRLOCconstraint
tothetmpsignalasshowninthefollowingcodingexamples.
XSTpropagatesittothenalnetlist.XSTsupportsthisfeatureissupportedfor:
•Registers,and
•InferredblockRAMifitcanbeimplementedonasingleblockRAMprimitive
SpecifyingINITandRLOCValuesforaFlip-FlopVHDLCodingExample
--
--SpecificationonanINITandRLOCvaluesforaflip-flop,
--describedatRTLlevel
--
libraryieee;
useieee.std_logic_1164.all;
entityinits_rlocs_3is
port(CLK:instd_logic;
DI:instd_logic_vector(3downto0);
DO:outstd_logic_vector(3downto0));
endinits_rlocs_3;
architecturebehofinits_rlocs_3is
signaltmp:std_logic_vector(3downto0):="1011";
attributeRLOC:string;
attributeRLOCoftmp:signalis"X3Y0X2Y0X1Y0X0Y0";
begin
process(CLK)
begin
if(clk’eventandclk=’1’)then
tmp<=DI;
endif;
endprocess;
DO<=tmp;
endbeh;
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Chapter4:XSTFPGAOptimization
SpecifyingINITandRLOCValuesforaFlip-FlopVerilogCodingExample
//
//SpecificationonanINITandRLOCvaluesforaflip-flop,
//describedatRTLlevel
//
modulev_inits_rlocs_3(clk,di,do);
inputclk;
input[3:0]di;
output[3:0]do;
(*RLOC="X3Y0X2Y0X1Y0X0Y0"*)
reg[3:0]tmp;
initialbegin
tmp=4’b1011;
end
always@(posedgeclk)
begin
tmp<=di;
end
assigndo=tmp;
endmodule
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Chapter4:XSTFPGAOptimization
UsingPCIFlowWithXST
ThissectiondiscussesUsingPCI™FlowWithXST,andincludes:
•RulesforUsingPCIFlowWithXST
•PreventingLogicandFlip-FlopReplication
•DisablingReadCores
RulesforUsingPCIFlowWithXST
Followtheserulestosatisfyplacementconstraintsandmeettimingrequirementswhen
usingPCIowwithXST.
•ForVHDL,ensurethatthenamesinthegeneratednetlistareallinUPPERcase.
Thedefaultcaseislower.
SpecifythecaseinISE®DesignSuitein:
Process>ProcessProperties>SynthesisOptions>Case
•ForVerilog,ensurethatCaseissettomaintain.
Thedefaultcaseismaintain.
SpecifythecaseinISEDesignSuitein:
Process>ProcessProperties>SynthesisOptions>Case
•Preservethehierarchyofthedesign.
SpecifytheKeepHierarchy(KEEP_HIERARCHY)settinginISEDesignSuitein:
Process>ProcessProperties>SynthesisOptions>KeepHierarchy
•Preserveequivalentip-ops.
XSTremovesequivalentip-opsbydefault.
SpecifytheEquivalentRegisterRemoval(EQUIVALENT_REGISTER_REMOVAL)
settinginISEDesignSuitein:
Process>ProcessProperties>Xilinx®SpecicOptions>EquivalentRegister
Removal
PreventingLogicandFlip-FlopReplication
Topreventlogicandip-opreplicationcausedbyahighfanoutip-opset/reset
signal:
•SetahighmaximumfanoutvaluefortheentiredesigninISE®DesignSuitein:
Process>ProcessProperties>SynthesisOptions>MaxFanout,or
•UseMaxFanout(MAX_FANOUT)tosetahighmaximumfanoutvalueforthe
initializationsignalconnectedtotheRSTportofthePCI™core.
Example:
max_fanout=2048
DisablingReadCores
DisablingReadCorespreventsXSTfromautomaticallyreadingPCI™coresfortiming
andareaestimation.InreadingPCIcores,XSTmayperformlogicoptimizationthat
doesnotallowthedesigntomeettimingrequirements,orwhichmightleadtoerrors
duringMAP .Bydefault,XSTreadscoresfortimingandareaestimation.Todisable
ReadCores,uncheckitinISE®DesignSuitein:
Process>ProcessProperties>SynthesisOptions>ReadCores
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Chapter5
XSTCPLDOptimization
ThischapterdiscussesXSTCPLDOptimization,andincludes:
•CPLDSynthesisOptions
•ImplementationDetailsforMacroGeneration
•CPLDSynthesisLogFileAnalysis
•CPLDSynthesisConstraints
•ImprovingResultsinCPLDSynthesis
CPLDSynthesisOptions
ThissectiondiscussestheXSToptionsrelatedonlytoCPLDsynthesisthatcanbeset
ISE®DesignSuitein:
Process>ProcessProperties
XSTgeneratesanNGClereadyfortheCPLDtter.
ThegeneralowofXSTforCPLDsynthesisis:
1.HardwareDescriptionLanguage(HDL)synthesisofVHDLorVerilogdesigns
2.Macroinference
3.Moduleoptimization
4.NGClegeneration
CPLDSynthesisSupportedDevices
XSTsupportsCPLDsynthesisforthefollowingdevices:
•CoolRunner™XPLA3
•CoolRunner-II
•XC9500
•XC9500XL
ThesynthesisforCoolRunnerXPLA3devicefamiliesandXC9500XLdevicefamilies
includesclockenableprocessing.Youcanalloworinvalidatetheclockenablesignal.
Wheninvalidated,itisreplacedbyequivalentlogic.
Theselectionofthemacrosthatusetheclockenable(counters,forinstance)depends
onthedevicetype.AcounterwithclockenableisacceptedfortheCoolRunnerXPLA3
devicefamiliesandXC9500XLdevicefamilies,butrejected(replacedbyequivalent
logic)forXC9500devices.
SettingCPLDSynthesisOptions
SetthefollowingCPLDsynthesisoptionsinISE®DesignSuitein:
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Chapter5:XSTCPLDOptimization
Process>ProcessProperties>SynthesisOptions
•KeepHierarchy(KEEP_HIERARCHY)
•MacroPreserve(-pld_mp)
•XORPreserve(-pld_xp)
•EquivalentRegisterRemoval(EQUIVALENT_REGISTER_REMOVAL)
•ClockEnable(-pld_ce)
•WYSIWYG(-wysiwyg)
•NoReduce(NOREDUCE)
Formoreinformation,see:
XSTCPLDConstraints(Non-Timing)
ImplementationDetailsforMacroGeneration
XSTprocessesthefollowingmacros:
•Adders
•Subtractors
•Add/sub
•Multipliers
•Comparators
•Multiplexers
•Counters
•Logicalshifters
•Registers(ip-opsandlatches)
•XORs
ThemacrogenerationisdecidedbytheMacroPreservecommandlineoption,which
cantaketwovalues:
•yes
Macrogenerationisallowed.
•no
Macrogenerationisinhibited.
Thegeneralmacrogenerationowis:
1.HardwareDescriptionLanguage(HDL)infersmacrosandsubmitsthemtothe
low-levelsynthesizer.
2.Low-levelsynthesizeracceptsorrejectsthemacrosdependingontheresources
requiredforthemacroimplementations.
Anacceptedmacroisgeneratedbyaninternalmacrogenerator.Arejectedmacrois
replacedbyequivalentlogicgeneratedbytheHDLsynthesizer.Arejectedmacromay
bedecomposedbytheHDLsynthesizerintocomponentblockssothatonecomponent
maybeanewmacrorequiringfewerresourcesthantheinitialone,andanothersmaller
macromaybeacceptedbyXST.Forinstance,aip-opmacrowithclockenable(CE)
cannotbeacceptedwhenmappingontotheXC9500.InthiscasetheHDLsynthesizer
submitstwonewmacros:
•Aip-opmacrowithoutclockenablesignal
•AMUXmacroimplementingtheclockenablefunction
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Chapter5:XSTCPLDOptimization
Ageneratedmacroisoptimizedseparatelyandthenmergedwithsurroundedlogic
becauseoptimizationgivesbetterresultsforlargercomponents.
CPLDSynthesisLogFileAnalysis
XSTmessagesrelatedtoCPLDsynthesisarelocatedafterthefollowingmessage:
LowLevelSynthesis
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Chapter5:XSTCPLDOptimization
TheXSTloglecontains:
•Tracingofprogressiveunitoptimizations
Optimizingunitunit_name...
•Information,warningsorfatalmessagesrelatedtounitoptimization:
–Whenequationshapingisapplied(XC9500devicesonly):
Collapsing...
–Removingequivalentip-ops
Registerff1equivalenttoff2hasbeenremoved
–UserconstraintsfullledbyXST:
implementationconstraint:constraint_name[=value]:signal_name
•Finalresultsstatistics
FinalResults
TopLevelOutputfilename:file_name
Outputformat:ngc
Optimizationgoal:{area|speed}
TargetTechnology:{9500|9500xl|9500xv|xpla3|xbr|cr2s}
KeepHierarchy:{yes|soft|no}
MacroPreserve:{yes|no}
XORPreserve:{yes|no}
DesignStatistics
NGCInstances:nb_of_instances
I/Os:nb_of_io_ports
MacroStatistics
#FSMs:nb_of_FSMs
#Registers:nb_of_registers
#Tristates:nb_of_tristates
#Comparators:nb_of_comparators
n-bitcomparator{equal|notequal|greater|less|greatequal|lessequal}:
nb_of_n_bit_comparators
#Multiplexers:nb_of_multiplexers
n-bitm-to-1multiplexer:
nb_of_n_bit_m_to_1_multiplexers
#Adders/Subtractors:nb_of_adds_subs
n-bitadder:nb_of_n_bit_adds
n-bitsubtractor:nb_of_n_bit_subs
#Multipliers:nb_of_multipliers
#LogicShifters:nb_of_logic_shifters
#Counters:nb_of_counters
n-bit{up|down|updown}counter:nb_of_n_bit_counters
#XORs:nb_of_xors
CellUsage:
#BELS:nb_of_bels
#AND...:nb_of_and...
#OR...:nb_of_or...
#INV:nb_of_inv
#XOR2:nb_of_xor2
#GND:nb_of_gnd#VCC:nb_of_vcc
#FlipFlops/Latches:nb_of_ff_latch
#FD...:nb_of_fd...
#LD...:nb_of_ld...
#Tri-States:nb_of_tristates
#BUFE:nb_of_bufe
#BUFT:nb_of_buft
#IOBuffers:nb_of_iobuffers
#IBUF:nb_of_ibuf
#OBUF:nb_of_obuf
#IOBUF:nb_of_iobuf
#OBUFE:nb_of_obufe
#OBUFT:nb_of_obuft#Others:nb_of_others
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Chapter5:XSTCPLDOptimization
CPLDSynthesisConstraints
Theconstraints(attributes)speciedintheHardwareDescriptionLanguage(HDL)
designorintheconstraintlesarewrittenbyXSTintotheNGCleassignalproperties.
ImprovingResultsinCPLDSynthesis
XSTproducesoptimizednetlistsfortheCPLDtter,which:
•Fitstheminspecieddevices
•Createsthedownloadprogrammableles
TheCPLDlow-leveloptimizationofXSTconsistsof:
•Logicminimization
•Subfunctioncollapsing
•Logicfactorization
•Logicdecomposition
OptimizationresultsinanNGCnetlistcorrespondingtoBooleanequations.TheCPLD
tterreassemblestheseequationstotthebestofthemacrocellcapacities.Aspecial
XSToptimizationprocess,knownasequationshaping,isappliedforXC9500and
XC9500XLdeviceswhenthefollowingoptionsareselected:
•KeepHierarchy
No
•OptimizationEffort
2orHigh
•MacroPreserve
No
Theequationshapingprocessingalsoincludesacriticalpathoptimizationalgorithm.
Thisalgorithmtriestoreducethenumberoflevelsofcriticalpaths.
Xilinx®recommendsCPLDttermultileveloptimizationbecauseofthespecial
optimizationsdonebythetter:
•DtoTip-opconversion
•DeMorganBooleanexpressionselection
ObtainingBetterFrequency
Thefrequencydependsonthenumberoflogiclevels(logicdepth).Toreducethe
numberoflevels,Xilinx®recommendsthefollowingoptions:
•OptimizationEffort
SetOptimizationEffortto2orHigh.
Thisvalueimpliesthecallingofthecollapsingalgorithm,whichtriestoreducethe
numberoflevelswithoutincreasingthecomplexitybeyondcertainlimits.
•OptimizationGoal
SetOptimizationGoaltoSpeed.
Thepriorityisthereductionofnumberoflevels.
ObtainingthebestfrequencydependsontheCPLDtteroptimization.Xilinx
recommendsrunningthemulti-leveloptimizationoftheCPLDtterwithdifferent
valuesforthe-ptermsoptions,beginningwith20andnishingwith50withastepof5.
Statisticallythevalue30givesthebestresultsforfrequency .
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Chapter5:XSTCPLDOptimization
Thefollowingtries,inthisorder,maygivesuccessivelybetterresultsforfrequency:
•ObtainingBetterFrequencyTry1
•ObtainingBetterFrequencyTry2
•ObtainingBetterFrequencyTry3
•ObtainingBetterFrequencyTry4
TheCPUtimeincreasesfromTry1toTry4.
ObtainingBetterFrequencyTry1
Selectonlyoptimizationeffort2andspeedoptimization.Theotheroptionshavedefault
values.
•Optimizationeffort
2orHigh
•OptimizationGoal
Speed
ObtainingBetterFrequencyTry2
Flattentheuserhierarchy.Inthiscaseoptimizationhasaglobalviewofthedesign,
andthedepthreductionmaybebetter.
•Optimizationeffort
1/Normalor2/High
•OptimizationGoal
Speed
•KeepHierarchy
no
ObtainingBetterFrequencyTry3
Mergethemacroswithsurroundedlogic.Thedesignatteningisincreased.
•Optimizationeffort
1orNormal
•OptimizationGoal
Speed
•KeepHierarchy
no
•MacroPreserve
no
ObtainingBetterFrequencyTry4
Applytheequationshapingalgorithm.Optionstobeselected:
•Optimizationeffort
2orHigh
•MacroPreserve
no
•KeepHierarchy
no
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Chapter5:XSTCPLDOptimization
FittingaLargeDesign
Adesignmaynottinthetargetdevicebecauseitexceedsthenumberofdevice
macrocellsordeviceP-Termcapacity.Inthatevent,youmay:
•SelectanAreaOptimizationforXST,or
•UsetheWYSIWYGCommandLineOption
SelectanAreaOptimizationforXST
WhenyouselectanareaoptimizationforXST,statisticallythebestarearesultsare
obtainedwiththefollowingoptions:
•Optimizationeffort
1(Normal)or2(High)
•OptimizationGoal
area
•Defaultvaluesforotheroptions
UsetheWYSIWYGCommandLineOption
AnotheroptionforttingalargedesignistousetheWYSIWYG(-wysiwyg)command
lineoptionwiththefollowingsetting:
-wysiwygyes
TheWYSIWYGcommandlineoptionmaybeusefulwhen:
•Thedesigncannotbesimpliedbydefaultoptimizationstrategies,and
•Thecomplexity(innumberofP-Terms)isnearthedevicecapacity.
Defaultoptimizations,bytryingtoreducethenumberoflogiclevels,maycreatelarger
equations.ThisincreasesthenumberofP-Termsandpreventsthedesignfromtting.
Unlikethoseoptimizations,theWYSIWYG(-wysiwyg)commandlineoptionenablesan
approachthatdoesnotincreasethenumberofP-Terms,ideallyallowingthedesigntot.
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Chapter6
XSTDesignConstraints
ThischaptergivesgeneralinformationaboutXSTDesignConstraints,andincludes:
•AboutXSTDesignConstraints
•MechanismsforSpecifyingConstraints
•GlobalandLocalConstraintSettings
•RulesforApplyingConstraints
•SettingGlobalConstraintsandOptions
•VHDLAttributeSyntax
•Verilog-2001Attributes
•XSTConstraintFile(XCF)
•ConstraintsPriority
•XSTSpecicNon-TimingOptions
•XSTCommandLineOnlyOptions
ForinformationaboutspecicXSTdesignconstraints,see:
•XSTGeneralConstraints
•XSTHDLConstraints
•XSTFPGAConstraints(Non-Timing)
•XSTCPLDConstraints(Non-Timing)
•XSTTimingConstraints
•XSTImplementationConstraints
•XST-SupportedThirdPartyConstraints
AboutXSTDesignConstraints
Constraintshelpyoumeetyourdesigngoalsandobtainthebestimplementationof
yourcircuit.Constraintscontrolvariousaspectsofsynthesis,aswellasplacementand
routing.Synthesisalgorithmsandheuristicsautomaticallyprovideoptimalresults
inmostsituations.Ifsynthesisfailstoinitiallyachieveoptimalresults,useavailable
constraintstotryothersynthesisalternatives.
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Chapter6:XSTDesignConstraints
MechanismsforSpecifyingConstraints
Thefollowingmechanismsareavailabletospecifyconstraints:
•Optionsprovideglobalcontrolofmostsynthesisaspects.Theycanbeseteitherin:
–ISE®DesignSuiteinProcess>Properties>SynthesisOptions,or
–bytheruncommandfromthecommandline
•InVHDL,attributescanbedirectlyinsertedintotheVHDLcodeandattachedto
individualelementsofthedesigntocontrolbothsynthesis,andplacementand
routing.
•InVerilog,constraintscanbeaddedas:
–Verilogattributes(preferred)
–Verilogmetacomments
•Constraintscanbespeciedinaseparateconstraintle.
GlobalandLocalConstraintSettings
GlobalsynthesissettingsaretypicallydenedinISE®DesignSuiteinProcess>
Properties>SynthesisOptions,orfromthecommandline.VHDLandVerilog
attributesandVerilogmetacommentscanbeinsertedinyoursourcecodetospecify
differentchoicesforindividualpartsofthedesign.
Thelocalspecicationofaconstraintoverridesitsglobalsetting.Similarly,ifaconstraint
issetbothonanode(oraninstance)andontheenclosingdesignunit,theformertakes
precedencefortheconsiderednode(orinstance).
RulesforApplyingConstraints
Followthesegeneralruleswhenapplyingconstraints:
•Severalconstraintscanbeappliedonsignals.Inthiscase,theconstraintmustbe
placedintheblockwherethesignalisdeclaredandused.
•Ifaconstraintcanbeappliedonanentity(VHDL),thenitcanalsobeappliedon
thecomponentdeclaration.Theabilitytoapplyconstraintsoncomponentsisnot
explicitlystatedforeachindividualconstraint,sinceitisageneralXSTrule.
•Somethirdpartysynthesistoolsallowyoutoapplyconstraintsonarchitectures.
XSTallowsconstraintsonarchitecturesonlyforthosethirdpartyconstraints
automaticallysupportedbyXST.
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Chapter6:XSTDesignConstraints
SettingGlobalConstraintsandOptions
ThissectiondiscussesSettingGlobalConstraintsandOptions,andincludes:
•SettingSynthesisOptions
•SettingHDLOptions
•SettingXilinxSpecicOptions
•SettingOtherXSTCommandLineOptions
•CustomCompileFileList
ThissectionexplainshowtosetglobalconstraintsandoptionsinISE®DesignSuite
inProcess>ProcessProperties.
Foradescriptionofeachconstraintthatappliesgenerally(thatis,toFPGAdevices,
CPLDdevices,VHDL,andVerilog)seetheConstraintsGuide.
ExceptforV alueeldswithcheckboxes,thereisapulldownarroworbrowsebuttonin
eachV alueeld.ThearrowisnotvisibleuntilyouclickintheValueeld.
SettingSynthesisOptions
TosetHardwareDescriptionLanguage(HDL)synthesisoptionsfromISE®DesignSuite:
1.SelectasourcelefromtheSourceFilewindow.
2.Right-clickSynthesize-XSTintheProcesswindow.
3.SelectProperties.
4.SelectSynthesisOptions.
5.Dependingonthedevicetypeyouhaveselected(FPGAorCPLDdevices),oneof
twodialogboxesopens.
6.Selectanyofthefollowingsynthesisoptions:
•OptimizationGoal(OPT_MODE)
•OptimizationEffort(OPT_LEVEL)
•UseSynthesisConstraintsFile(-iuc)
•SynthesisConstraintFile(-uc)
•LibrarySearchOrder(-lso)
•GlobalOptimizationGoal(-glob_opt)
•GenerateRTLSchematic(-rtlview)
•WriteTimingConstraints(-write_timing_constraints)
•Verilog2001(-verilog2001)
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Chapter6:XSTDesignConstraints
SelectEdit>Preferences>Processes>PropertyDisplayLevel>Advancedtoviewthe
followingoptions:
•KeepHierarchy(KEEP_HIERARCHY)
•CoresSearchDirectories(-sd)
•CrossClockAnalysis(-cross_clock_analysis)
•HierarchySeparator(-hierarchy_separator)
•BusDelimiter(-bus_delimiter)
•Case(-case)
•WorkDirectory(-xsthdpdir)
•HDLLibraryMappingFile(-xsthdpini)
•VerilogIncludeDirectories(-vlgincdir)
•Slice(LUT-FFPairs)UtilizationRatio(SLICE_UTILIZATION_RATIO)
SettingHDLOptions
ThissectiondiscussesSettingHDLOptions,andincludes:
•HowtoSetHDLOptions
•SettingHDLOptionsforFPGADevices
•SettingHDLOptionsforCPLDDevices
HowtoSetHDLOptions
TosetHardwareDescriptionLanguage(HDL)optionsforFPGAdevicesandCPLD
devicesinISE®DesignSuiteselect:
Process>ProcessProperties>Synthesize-XST>HDLOptions
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Chapter6:XSTDesignConstraints
SettingHDLOptionsforFPGADevices
ThefollowingHDLOptionscanbesetforFPGAdevices:
•FSMEncodingAlgorithm(FSM_ENCODING)
•SafeImplementation(SAFE_IMPLEMENTATION)
•CaseImplementationStyle(-vlgcase)
•FSMStyle(FSM_STYLE)
ToviewFSMStyle,selectEdit>Preferences>Processes>PropertyDisplayLevel
>Advanced
•RAMExtraction(RAM_EXTRACT)
•RAMStyle(RAM_STYLE)
•ROMExtraction(ROM_EXTRACT)
•ROMStyle(ROM_STYLE)
•MuxExtraction(MUX_EXTRACT)
•MuxStyle(MUX_STYLE)
•DecoderExtraction(DECODER_EXTRACT)
•PriorityEncoderExtraction(PRIORITY_EXTRACT)
•ShiftRegisterExtraction(SHREG_EXTRACT)
•LogicalShifterExtraction(SHIFT_EXTRACT)
•XORCollapsing(XOR_COLLAPSE)
•ResourceSharing(RESOURCE_SHARING)
•MultiplierStyle(MULT_STYLE)
Forlaterdevices,MultiplierStyleisrenamedasfollows:
–UseDSP48
Virtex®-4devices
–UseDSPBlock
Virtex-5devicesandSpartan®-3ADSPdevices
•UseDSP48(USE_DSP48)
SettingHDLOptionsforCPLDDevices
ThefollowingHDLOptionscanbesetforCPLDdevices:
•FSMEncodingAlgorithm(FSM_ENCODING)
•SafeImplementation(SAFE_IMPLEMENTATION)
•CaseImplementationStyle(-vlgcase)
•MuxExtraction(MUX_EXTRACT)
•ResourceSharing(RESOURCE_SHARING)
SettingXilinxSpecificOptions
ThissectiondiscussesSettingXilinx®SpecicOptions,andincludes:
•HowtoSetXilinxSpecicOptions
•SettingXilinxSpecicOptionsforFPGADevices
•SettingXilinxSpecicOptionsforCPLDDevices
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Chapter6:XSTDesignConstraints
HowtoSetXilinxSpecificOptions
TosetXilinxspecicoptionsinISE®DesignSuite,select:
Process>ProcessProperties>SynthesisOptions>XilinxSpecicOptions
SettingXilinxSpecificOptionsforFPGADevices
ThefollowingXilinxspecicoptionscanbesetforFPGAdevices:
•AddI/OBuffers(-iobuf)
•LUTCombining(LC)
•MaxFanout(MAX_FANOUT)
•RegisterDuplication(REGISTER_DUPLICATION)
•ReduceControlSets(REDUCE_CONTROL_SETS)
•EquivalentRegisterRemoval(EQUIVALENT_REGISTER_REMOVAL)
•RegisterBalancing(REGISTER_BALANCING)
•MoveFirstStage(MOVE_FIRST_STAGE)
•MoveLastStage(MOVE_LAST_STAGE)
•ConvertTristatestoLogic(TRISTATE2LOGIC)
ConvertTristatetoLogicappearsonlywhenworkingwithdeviceswithinternal
tristateresources.
•UseClockEnable(USE_CLOCK_ENABLE)
•UseSynchronousSet(USE_SYNC_SET)
•UseSynchronousReset(USE_SYNC_RESET)
SelectEdit>Preferences>Processes>PropertyDisplayLevel>AdvancedinISE
DesignSuitetodisplaythefollowingoptions:
•NumberofGlobalClockBuffers(-bufg)
•NumberofRegionalClockBuffers(-bufr)
SettingXilinxSpecificOptionsforCPLDDevices
ThefollowingXilinxspecicoptionscanbesetforCPLDdevices:
•AddI/OBuffers(-iobuf)
•EquivalentRegisterRemoval(EQUIVALENT_REGISTER_REMOVAL)
•ClockEnable(-pld_ce)
•MacroPreserve(-pld_mp)
•XORPreserve(-pld_xp)
•WYSIWYG(-wysiwyg)
SettingOtherXSTCommandLineOptions
ThissectiondiscussesSettingOtherXSTCommandLineOptions,andincludes:
•SettingOptionsinISEDesignSuite
•TipsforSettingOptions
•OptionsPrecedence
•IllegalorUnrecognizedOptions
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Chapter6:XSTDesignConstraints
SettingOptionsinISEDesignSuite
SetotherXSTcommandlineoptionsinISE®DesignSuitein:
Process>ProcessProperties>OtherXSTCommandLineOptions
Thisisanadvancedproperty.
TipsforSettingOptions
WhensettingXSTcommandlineoptions:
•UsethesyntaxdescribedinXSTCommandLineMode.
•Separatemultipleoptionswithaspace.
OptionsPrecedence
WhilethispropertyisintendedforoptionsnotlistedinProcess>ProcessProperties,if
anoptionalreadylistedisentered,precedenceisgiventothatoption.
IllegalorUnrecognizedOptions
IllegalorunrecognizedoptionscauseXSTtostopprocessingandgenerateamessage
suchas:
ERROR:Xst:1363-Option"-verilog2002"isnotavailable
forcommandrun.
CustomCompileFileList
UsetheCustomCompileFileListpropertytochangetheorderinwhichXSTprocesses
sourcelesareprocessed.Withthisproperty,youselectauser-denedcompilelistle
thatXSTusestodeterminetheorderinwhichitprocesseslibrariesanddesignles.
Otherwise,XSTusesanautomaticallygeneratedlist.
Listalldesignlesandtheirlibrariesintheorderinwhichtheyaretobecompiled,
fromtoptobottom.Typeeachleandlibrarypaironitsownline,withasemicolon
separatingthelibraryfromtheleasfollows:
library_name;le_name[library_name;le_name]...
Example:
work;stopwatch.vhd
work;statmach.vhd
...
SincethispropertyisnotconnectedtoSimulationProperties>CustomCompileFile
List,adifferentcompilelistleisusedforsynthesisthanforsimulation.
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Chapter6:XSTDesignConstraints
VHDLAttributeSyntax
YoucandescribeconstraintswithVHDLattributesintheVHDLcode.
Declareasfollows:
attributeAttributeName:Type;
SyntaxExampleOne
attributeRLOC:string;
Theattributetypedenesthetypeoftheattributevalue.TheonlyallowedtypeforXST
isstring.Anattributecanbedeclaredinanentityorarchitecture.Ifdeclaredinthe
entity,itisvisiblebothintheentityandthearchitecturebody.Iftheattributeisdeclared
inthearchitecture,itcannotbeusedintheentitydeclaration.
Specifyasfollows:
attributeAttributeNameofObjectList:ObjectTypeisAttributeValue;
SyntaxExampleTwo
attributeRLOCofu123:labelisR11C1.S0;attributebufgofmy_signal:signalissr;
AcceptedObjectTypes
Theobjectlistisacommaseparatedlistofidentiers.Acceptedobjecttypesare:
•entity
•component
•label
•signal
•variable
•type
GeneralRules
•Ifaconstraintcanbeappliedonanentity(VHDL),thenitcanalsobeappliedon
thecomponentdeclaration.Theabilitytoapplyconstraintsoncomponentsisnot
explicitlystatedforeachindividualconstraint,sinceitisageneralXSTrule.
•Somethirdpartysynthesistoolsallowyoutoapplyconstraintsonarchitectures.
XSTallowsconstraintsonarchitecturesonlyforthosethirdpartyconstraints
automaticallysupportedbyXST.
Verilog-2001Attributes
XSTsupportsVerilog-2001attributestatements.Attributesarecommentsthatpass
specicinformationtosoftwaretoolssuchassynthesistools.Verilog-2001attributes
canbespeciedanywhereforoperatorsorsignalswithinmoduledeclarationsand
instantiations.Otherattributedeclarationsmaybesupportedbythecompiler,but
areignoredbyXST.
Verilog-2001AttributesSyntax
Verilog-2001attributesareboundedbytheasteriskcharacter(*).
(*attribute_name=attribute_value*)
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Chapter6:XSTDesignConstraints
where
•attributeprecedesthesignal,module,orinstancedeclarationtowhichitrefers.
•attribute_valueisastring.Nointegerorscalarvaluesareallowed.
•attribute_valueisbetweenquotes.
•Thedefaultis1.
•(*attribute_name*)isthesameas(*attribute_name="1"*).
SyntaxExampleOne
(*clock_buffer="IBUFG"*)inputCLK;
SyntaxExampleTwo
(*INIT="0000"*)reg[3:0]d_out;
SyntaxExampleThree
always@(current_stateorreset)begin(*parallel_case*)(*full_case*)case
(current_state)...
SyntaxExampleFour
(*mult_style="pipe_lut"*)MULTmy_mult(a,b,c);
Verilog-2001Limitations
Verilog-2001attributesarenotsupportedfor:
•Signaldeclarations
•Statements
•Portconnections
•Expressionoperators
Verilog-2001MetaComments
ConstraintscanalsobespeciedinVerilogcodeusingmetacomments.TheVerilog-2001
formatisthepreferredsyntax,butthemetacommentstyleisstillsupported.Usethe
followingsyntax:
//synthesisattributeAttributeName[of]ObjectName[is]AttributeValue
Verilog-2001MetaCommentsExamples
//synthesisattributeRLOCofu123isR11C1.S0
//synthesisattributeHU_SETu1MY_SET
//synthesisattributebufgofmy_clockis"clk"
Thefollowingconstraintsuseadifferentsyntax:
•ParallelCase(PARALLEL_CASE)
•FullCase(FULL_CASE)
•TranslateOff(TRANSLATE_OFF)andTranslateOn(TRANSLATE_ON)
Formoreinformation,see:
VerilogAttributesandMetaComments
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Chapter6:XSTDesignConstraints
XSTConstraintFile(XCF)
Thissectionincludes:
•SpecifyingConstraintsintheXCF
•XCFSyntaxandUtilization
•NativeandNon-NativeUCFConstraintsSyntax
•XCFSyntaxLimitations
SpecifyingConstraintsintheXCF
XSTconstraintscanbespeciedintheXSTConstraintFile(XCF).
TheXCFhasanextensionof.xcf.
YoucanspecifytheXCFin:
•ISE®DesignSuite
Formoreinformation,see:
ISEDesignSuiteHelp
•CommandLineMode
TospecifytheXCFincommandlinemode,useSynthesisConstraintFile(-uc)with
theruncommand.
Formoreinformation,see:
XSTCommandLineMode
XCFSyntaxandUtilization
ThissectiondiscussesXCFSyntaxandUtilization,andincludes:
•AboutXCFSyntaxandUtilization
•Syntax
•SyntaxExamplesandSettings
•XSTSynthesisConstraints
AboutXCFSyntaxandUtilization
TheXSTConstraintFile(XCF)syntaxenablesyoutospecifyaspecicconstraintfor:
•Theentiredevice(globally),or
•Specicmodules
TheXCFsyntaxisbasicallythesameastheUserConstraintsFile(UCF)syntaxfor
applyingconstraintstonetsorinstances,butwithanextensiontothesyntaxtoallow
constraintstobeappliedtospeciclevelsofhierarchy.UsethekeywordMODELtodene
theentityormoduletowhichtheconstraintisapplied.Ifaconstraintisappliedtoan
entityormodule,theconstraintisappliedtoeachinstanceoftheentityormodule.
DeneconstraintsinISE®DesignSuiteinProcess>ProcessProperties,ortheXST
runscript,ifrunningonthecommandline.SpecifyexceptionsintheXCFle.The
constraintsspeciedintheXCFleareappliedonlytothemodulelisted,andnotto
anysubmodulesbelowit.
Syntax
Toapplyaconstrainttotheentireentityormoduleusethefollowingsyntax:
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Chapter6:XSTDesignConstraints
MODELentitynameconstraintname=constraintvalue;
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XCFSyntaxExampleOne
MODELtopmux_extract=false;MODELmy_designmax_fanout=256;
Iftheentitymy_designisinstantiatedseveraltimesinthedesign,themax_fanout=256
constraintisappliedtoeachinstanceofmy_design.
Toapplyconstraintstospecicinstancesorsignalswithinanentityormodule,usethe
INSTorNETkeywords.XSTdoesnotsupportconstraintsthatareappliedtoVHDL
variables.
BEGINMODELentityname
INSTinstancenameconstraintname=constraintvalue;
NETsignalnameconstraintname=constraintvalue;
END;
XCFSyntaxExampleTwo
BEGINMODELcrc32
INSTstopwatchopt_mode=area;
INSTU2ram_style=block;
NETmyclockclock_buffer=true;
NETdata_iniob=true;
END;
XSTSynthesisConstraints
ForacompletelistofXSTsynthesisconstraints,see:
XSTSpecicNon-TimingOptions
NativeandNon-NativeUCFConstraintsSyntax
AllconstraintssupportedbyXSTcanbedividedintotwogroups:
•NativeUCFConstraints
•Non-NativeUCFConstraints
NativeUCFConstraints
OnlyTimingandAreaGroupconstraintsusenativeUserConstraintsFile(UCF)syntax.
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Chapter6:XSTDesignConstraints
UsenativeUCFsyntax,includingwildcardsandhierarchicalnames,fornativeUCF
constraintssuchas:
•Period(PERIOD)
•Offset(OFFSET)
•TimingNameonaNet(TNM_NET)
•Timegroup(TIMEGRP)
•TimingIgnore(TIG)
•From-To(FROM-TO)
RestrictionDonotusetheseconstraintsinsidetheBEGINMODEL...ENDconstruct.
Ifyoudo,XSTissuesanerror.
Non-NativeUCFConstraints
Forallnon-nativeUserConstraintsFile(UCF)constraints,usetheMODELorBEGIN
MODEL...END;constructs.Thisincludes:
•PureXSTconstraintssuchas:
–AutomaticFSMExtraction(FSM_EXTRACT)
–RAMStyle(RAM_STYLE)
•Implementationnon-timingconstraintssuchas:
–RLOC
–Keep(KEEP)
IfyouspecifytimingconstraintsintheXSTConstraintFile(XCF),Xilinx®recommends
thatyouuseaforwardslash(/)asahierarchyseparatorinsteadofanunderscore(_).
Formoreinformation,see:
HierarchySeparator(-hierarchy_separator)
XCFSyntaxLimitations
XSTConstraintFile(XCF)syntaxhasthefollowinglimitations:
•Nestedmodelstatementsarenotsupported.
•InstanceorsignalnameslistedbetweentheBEGINMODELstatementandthe
ENDstatementareonlytheonesvisibleinsidetheentity.Hierarchicalinstanceor
signalnamesarenotsupported.
•Wildcardsininstanceandsignalnamesarenotsupported,exceptintiming
constraints.
•NotallnativeUserConstraintsFile(UCF)constraintsaresupported.
Formoreinformation,seetheConstraintsGuide.
ConstraintsPriority
Constraintsprioritydependsontheleinwhichtheconstraintappears.Aconstraintin
aleaccessedlaterinthedesignowoverridesaconstraintinaleaccessedearlier
inthedesignow.
Priorityisasfollows,fromhighesttolowest:
1.SynthesisConstraintFile
2.HardwareDescriptionLanguage(HDL)le
3.ISE®DesignSuiteProcess>ProcessProperties,orthecommandline
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Chapter6:XSTDesignConstraints
XSTSpecificNon-TimingOptions
Thefollowingtableshows:
•Allowedvaluesforeachconstraint
•Typeofobjectstowhichtheycanbeapplied
•Usagerestrictions
Inmanycases,aparticularconstraintcanbeappliedgloballytoanentireentityor
model,oralternatively,itcanbeappliedlocallytoindividualsignals,netsorinstances.
Constraint
NameConstraint
Value
VHDL
Target
Verilog
TargetXCFTargetCommand
LineCommand
Value
BoxTypeprimitive
black_box
user_black_box
entity
inst
module
inst
model
inst(inmodel)
N/AN/A
MapLogicon
BRAM
yes
no
entitymodulemodelN/AN/A
BufferTypebufgdll
ibufg
bufg
bufgp
ibuf
bufr
none
signalsignalnet(inmodel)N/AN/A
Extract
BUFGCE
yes
no
primary
clock
signal
primary
clock
signal
net(inmodel)-bufgceyes
no
default:no
ClockSignalyes
no
clock
signal
clock
signal
clock
signal
net(inmodel)
N/AN/A
Decoder
Extraction
yes
no
entity
signal
entity
signal
model
net(inmodel)
-decoder
_extract
yes
no
default:yes
Enumerated
Encoding
string
containing
space-separated
binarycodes
typesignalnet(inmodel)N/AN/A
Equivalent
Register
Removal
yes
no
entity
signal
module
signal
model
net(inmodel)
-equivalent
_register
_removal
yes
no
default:yes
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Chapter6:XSTDesignConstraints
Constraint
NameConstraint
Value
VHDL
Target
Verilog
TargetXCFTargetCommand
LineCommand
Value
FSMEncoding
Algorithm
auto
one-hot
compact
sequential
gray
johnson
speed1
user
entity
signal
module
signal
model
net(inmodel)
-fsm
_encoding
auto
one-hot
compact
sequential
gray
johnson
speed1
user
default:auto
Automatic
FSMExtraction
yes
no
entity
signal
module
signal
model
net(inmodel)
-fsm
_extract
yes
no
default:yes
FSMStylelut
bram
entity
signal
module
signal
model
net(inmodel)
-fsm
_style
lut
bram
default:lut
FullCaseN/AN/AcasestatementN/AN/AN/A
PackI/O
RegistersInto
IOBs
true
false
auto
signal
instance
signal
instance
net(inmodel)
inst(inmodel)
-iobtrue
false
auto
default:auto
I/OStandardstring
Formore
information,
seethe
Constraints
Guide.
signal
instance
signal
instance
net(inmodel)
inst(inmodel)
N/AN/A
Keeptrue
false
soft
signalsignalnet(inmodel)N/AN/A
Keep
Hierarchy
yes
no
soft
entitymodulemodel-keep
_hierarchy
yesdefault
(CPLD)
nodefault
(FPGA)
soft
LOCstringsignal(primary
IO)
instance
signal(primary
IO)
instance
net(inmodel)
inst(inmodel)
N/AN/A
MapEntityon
aSingleLUT
yes
no
entity
architecture
modulemodelN/AN/A
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Chapter6:XSTDesignConstraints
Constraint
NameConstraint
Value
VHDL
Target
Verilog
TargetXCFTargetCommand
LineCommand
Value
MaxFanoutintegerentity
signal
module
signal
model
net(inmodel)
-max
_fanoutinteger
default:see
detailed
description
MoveFirst
Stage
yes
no
entity
primary
clock
signal
module
primary
clock
signal
model
primaryclock
signal
net(inmodel)
-move
_rst
_stage
yes
no
default:yes
MoveLast
Stage
yes
no
entity
primary
clock
signal
module
primary
clock
signal
model
primaryclock
signal
net(inmodel
-move
_last
_stage
yes
no
default:yes
Multiplier
Style
auto
block
pipe_block
kcm
csd
lut
pipe_lut
entity
signal
module
signal
model
net(inmodel)
-mult
_style
auto
block
pipe_block
kcm
csd
lut
pipe_lut
default:auto
MuxExtractionyes
no
force
entity
signal
module
signal
model
net(inmodel)
-mux
_extract
yes
no
force
default:yes
MuxStyleauto
muxf
muxcy
entity
signal
module
signal
model
net(inmodel)
-mux
_styleauto
muxf
muxcy
default:auto
NoReduceyes
no
signalsignalnet(inmodel)N/AN/A
Optimization
Effort
1
2
entitymodulemodel-opt
_level
1
2
default:1
Optimization
Goal
speed
area
entitymodulemodel-opt
_modespeed
area
default:speed
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Chapter6:XSTDesignConstraints
Constraint
NameConstraint
Value
VHDL
Target
Verilog
TargetXCFTargetCommand
LineCommand
Value
Optimize
Instantiated
Primitives
yes
no
entity
instance
module
instance
model
instance(in
model)
-optimize
_primitives
yes
no
default:no
ParallelCaseN/AN/AcasestatementN/AN/AN/A
Power
Reduction
yes
no
entitymodulemodel-poweryes
no
default:no
Priority
Encoder
Extraction
yes
no
force
entity
signal
module
signal
model
net(inmodel)
-priority
_extract
yes
no
force
default:yes
RAM
Extraction
yes
no
entity
signal
module
signal
model
net(inmodel)
-ram
_extract
yes
no
default:yes
RAMStyleauto
block
distributed
pipe_distributed
block_power1
block_power2
entity
signal
module
signal
model
net(inmodel)
-ram
_styleauto
block
distributed
default:auto
ReadCoresyes
no
optimize
entity
component
module
label
model
inst(inmodel)
-read
_cores
yes
no
optimize
default:yes
Register
Balancing
yes
no
forward
backward
entity
signal
FF
instancename
module
signal
FF
instancename
primaryclock
signal
modelnet(in
model)inst(in
model)
-register
_balancing
yes
no
forward
backward
default:no
Register
Duplication
yes
no
entity
signal
modulemodel
net(inmodel)
-register
_duplication
yes
no
default:yes
Resource
Sharing
yes
no
entity
signal
module
signal
model
net(inmodel)
-resource
_sharing
yes
no
default:yes
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Chapter6:XSTDesignConstraints
Constraint
NameConstraint
Value
VHDL
Target
Verilog
TargetXCFTargetCommand
LineCommand
Value
ROM
Extraction
yes
no
entity
signal
module
signal
model
net(inmodel)
-rom
_extract
yes
no
default:yes
ROMStyleauto
block
distributed
entity
signal
module
signal
model
net(inmodel)
-rom
_styleauto
block
distributed
default:auto
Saveyes
no
signal
instof
primitive
signal
instof
primitive
net(inmodel)
instof
primitive(in
model)
N/AN/A
Safe
Implementation
yes
no
entity
signal
module
signal
model
net(inmodel)
-safe
_implementation
yes
no
default:no
SafeRecovery
State
stringsignalsignalnet(inmodel)N/AN/A
LogicalShifter
Extraction
yes
no
entity
signal
module
signal
model
net(inmodel)
-shift
_extract
yes
no
default:yes
ShiftRegister
Extraction
yes
no
entity
signal
module
signal
model
net(inmodel)
-shreg
extract
yes
no
default:yes
Signal
Encoding
auto
one-hot
user
entity
signal
module
signal
model
net(inmodel)
-signal
_encoding
auto
one-hot
user
default:auto
Slice
Utilization
Ratio
integer(range
-1to100)
integer%
(range-1to
100)
integer#
entitymodulemodel-slice
_utilization
_ratio
integer(range
-1to100)
integer%
(range-1to
100)
integer#
default:100
Slice
Utilization
RatioDelta
integer(range
0to100)
integer%
(range0to100)
integer#
entitymodulemodel-slice
_utilization
_ratio
_maxmargin
integer(range
0to100)
integer%
(range0to100)
integer#
default:0
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Chapter6:XSTDesignConstraints
Constraint
NameConstraint
Value
VHDL
Target
Verilog
TargetXCFTargetCommand
LineCommand
Value
TranslateOff
andTranslate
On
N/Alocal
notarget
local
notarget
N/AN/AN/A
Convert
Tristatesto
Logic
yes
no
entity
signal
modulesignalmodel
net(inmodel)
-tristate2logicyes
no
default:yes
UseCarry
Chain
yes
no
entity
signal
module
signal
model
net(inmodel)
-use
_carry
_chain
yes
no
default:yes
UseClock
Enable
auto
yes
no
entity
signal
FF
instance
name
module
signal
FF
instance
name
model
net(inmodel)
inst(inmodel)
-use
_clock
_enable
auto
yes
no
default:auto
UseDSP48auto
yes
no
entity
signal
module
signal
model
net(inmodel)
-use
_dsp48auto
yes
no
default:auto
Use
Synchronous
Reset
auto
yes
no
entity
signal
FF
instance
name
module
signal
FF
instance
name
model
net(inmodel)
inst(inmodel)
-use
_sync
_reset
auto
yes
no
default:auto
Use
Synchronous
Set
auto
yes
no
entity
signal
FF
instance
name
module
signal
FF
instance
name
model
net(inmodel)
inst(inmodel)
-use
_sync
_set
auto
yes
no
default:auto
XOR
Collapsing
yes
no
entity
signal
module
signal
model
net(inmodel)
-xor
_collapse
yes
no
default:yes
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Chapter6:XSTDesignConstraints
XSTCommandLineOnlyOptions
ThissectiondiscussesXSTCommandLineOnlyOptions,andincludes:
•XSTSpecicNon-TimingOptionsSupportedOnlyintheCommandLine
•InvokingXSTTimingOptions
•XSTTimingConstraintsSupportedOnlyinProcess>ProcessProperties,orthe
CommandLine
•XSTTimingConstraintsSupportedOnlyintheXCF
XSTSpecificNon-TimingOptionsSupportedOnlyintheCommand
Line
ConstraintNameCommandLineCommandValue
VHDLTopLevelArchitecture-archarchitecture_name
default:N/A
AsynchronoustoSynchronous-async_to_syncyes
no
default:no
AutomaticBRAMPacking-auto_bram_packingyes
no
default:no
BRAMUtilizationRatio
(BRAM_UTILIZATION_RATIO)
-bram_utilization_
ratio
integer(range-1to100)
integer%(range-1to100)
integer#
default:100
MaximumGlobalClockBuffers-bufgInteger
default:maxnumberofbuffersin
targetdevice
MaximumRegionalClockBuffers-bufrInteger
default:maxnumberofbuffersin
targetdevice
BusDelimiter-bus_delimiter<>
[]
{}
()
default:<>
Case-caseupper
lower
maintain
default:maintain
VerilogMacros-dene{name=value}
default:N/A
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Chapter6:XSTDesignConstraints
ConstraintNameCommandLineCommandValue
DSPUtilizationRatio
(DSP_UTILIZATION_RATIO)
-dsp_utilization_ratiointeger(range-1to100)
integer%(range-1to100)
integer#
default:100
Duplicationsufx-duplication_sufxstring%dstring
default:_%d
VHDLTop-Levelblock
(ValidonlywhenoldVHDLproject
formatisused(-ifmtVHDL).Use
projectformat(-ifmtmixed)and-top
optiontospecifywhichtoplevelblock
tosynthesize.)
-ententity_name
default:N/A
Generics-generics{name=value}
default:N/A
HDLFileCompilationOrder-hdl_compilation_orderauto
user
default:auto
HierarchySeparator-hierarchy_separator_
/
default:/
InputFormat-ifmtmixed
vhdl
verilog
default:mixed
Input/ProjectFileName-ifnle_name
default:N/A
AddI/OBuffers-iobufyes
no
default:yes
IgnoreUserConstraints-iucyes
no
default:no
LibrarySearchOrder-lsole_name.lso
default:N/A
LUTCombining-lcauto
area
off
default:off
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Chapter6:XSTDesignConstraints
ConstraintNameCommandLineCommandValue
NetlistHierarchy-netlist_hierarchyas_optimized
rebuilt
default:as_optimized
OutputFileFormat-ofmtngc
default:ngc
OutputFileName-ofnle_name
default:N/A
TargetDevice-ppart-package-speed(Forexample:
xc5vfx30t-ff324-2)
default:N/A
ClockEnable-pld_ceyes
no
default:yes
MacroPreserve-pld_mpyes
no
default:yes
XORPreserve-pld_xpyes
no
default:yes
ReduceControlSets-reduce_control_setsauto
no
default:no
GenerateRTLSchematic-rtlviewyes
no
only
default:no
CoresSearchDirectories-sddirectories
default:N/A
SlicePacking-slice_packingyes
no
default:yes
TopLevelBlock-topblock_name
default:N/A
SynthesisConstraintsFile-ucle_name.xcf
default:N/A
Verilog2001-verilog2001yes
no
default:yes
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Chapter6:XSTDesignConstraints
ConstraintNameCommandLineCommandValue
CaseImplementationStyle-vlgcasefull
parallel
full-parallel
default:N/A
VerilogIncludeDirectories-vlgincdirdirectories
default:N/A
WorkLibrary-work_libdirectory
default:work
wysiwyg-wysiwygyes
no
default:no
WorkDirectory-xsthdpdirDirectory
default:./xst
HDLLibraryMappingFile-xsthdpinile_name.ini
default:N/A
InvokingXSTTimingOptions
InvokeXSTtimingoptionsfrom:
•ISE®DesignSuiteinProcess>ProcessProperties
•Commandline
•XSTConstraintFile(XCF)
XSTTimingConstraintsSupportedOnlyinProcess>Process
Properties,ortheCommandLine
OptionProcess>ProcessProperties
(ISE®DesignSuite)Values
glob_optGlobalOptimizationGoalallclocknetsinpad
_to_outpadoffset
_in_beforeoffset
_out_aftermax
_delay
default:allclocknets
cross_clock_analysisCrossClockAnalysisyes
no(default)
write_timing_constraintsWriteTimingConstraintsyes
no(default)
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Chapter6:XSTDesignConstraints
XSTTimingConstraintsSupportedOnlyintheXCF
ThefollowingXSTtimingconstraintscanbeappliedforsynthesisonlythroughthe
XSTConstraintFile(XCF):
•Period(PERIOD)
•Offset(OFFSET)
•From-To(FROM-TO)
•TimingName(TNM)
•TimingNameonaNet(TNM_NET)
•Timegroup(TIMEGRP)
•TimingIgnore(TIG)
•TimingSpecications(TIMESPEC)
•TimingSpecicationIdentier(TSidentier)
Thesetimingconstraintsinuencesynthesisoptimization,andcanbepassedontoplace
androutebyselectingtheWriteTimingConstraintscommandlineoption.
Formoreinformation,seetheConstraintsGuide.
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Chapter7
XSTGeneralConstraints
Thischapterdiscussesthefollowingconstraints:
•AddI/OBuffers(-iobuf)
•BoxType(BOX_TYPE)
•BusDelimiter(-bus_delimiter)
•Case(-case)
•CaseImplementationStyle(-vlgcase)
•DuplicationSufx(-duplication_sufx)
•FullCase(FULL_CASE)
•GenerateRTLSchematic(-rtlview)
•Generics(-generics)
•HDLLibraryMappingFile(-xsthdpini)
•HierarchySeparator(-hierarchy_separator)
•I/OStandard(IOSTANDARD)
•Keep(KEEP)
•KeepHierarchy(KEEP_HIERARCHY)
•LibrarySearchOrder(-lso)
•LOC
•NetlistHierarchy(-netlist_hierarchy)
•OptimizationEffort(OPT_LEVEL)
•OptimizationGoal(OPT_MODE)
•ParallelCase(PARALLEL_CASE)
•RLOC
•Save(S/SAVE)
•SynthesisConstraintFile(-uc)
•TranslateOff(TRANSLATE_OFF)andTranslateOn(TRANSLATE_ON)
•UseSynthesisConstraintsFile(-iuc)
•Verilog2001(-verilog2001)
•VerilogIncludeDirectories(-vlgincdir)
•VerilogMacros(-dene)
•WorkDirectory(-xsthdpdir)
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Chapter7:XSTGeneralConstraints
AddI/OBuffers(-iobuf)
TheAddI/OBuffers(-iobuf)commandlineoption:
•EnablesordisablesI/Obufferinsertion.
•Canbeusedtosynthesizeapartofadesigntobeinstantiatedlateron.
XSTautomaticallyinsertsInput/OutputBuffersintothedesign.Ifyoumanually
instantiateI/OBuffersforsomeoralltheI/Os,XSTinsertsI/OBuffersonlyforthe
remainingI/Os.IfyoudonotwantXSTtoinsertI/OBuffers,set-iobuftono.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
AppliestodesignprimaryIOs.
Syntax
-iobuf{yes|no|true|false|soft}
•yes(default)
TellsXSTtogenerateIBUFandOBUFprimitivesandconnectedthemtoI/Oports
ofthetop-levelmodule.
•no
TellsXSTnottogenerateIBUFandOBUFprimitives,andmustbeusedwhenXSTis
calledtosynthesizeaninternalmodulethatisinstantiatedlaterinalargerdesign.
IfI/Obuffersareaddedtoadesign,thisdesigncannotbeusedasasubmodule
ofanotherdesign.
•true
•false
•soft
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-iobufyes
AddsI/Obufferstothetoplevelmoduleofthedesign.
ISE®DesignSuite
Process>ProcessProperties>Xilinx®-SpecicOptions>AddI/OBuffers
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Chapter7:XSTGeneralConstraints
BoxType(BOX_TYPE)
TheBoxType(BOX_TYPE)constraintisasynthesisconstraint.
IfBoxTypeisappliedtoatleastasingleinstanceofablockofadesign,BoxTypeis
propagatedtoallotherinstancesoftheentiredesign.Thisfeaturewasimplemented
forVerilogandXSTConstraintFile(XCF)inordertohaveaVHDL-likesupport,where
BoxTypecanbeappliedtoacomponent.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestothefollowingdesignelements:
•VHDL
component,entity
•Verilog
module,instance
•XSTConstraintFile(XCF)
model,instance
PropagationRules
Appliestothedesignelementtowhichitisattached.
Syntax
•primitive
•black_box
Equivalenttoprimitive.Willeventuallybecomeobsolete.
•user_black_box
XSTreportsinferenceofablackboxinthelogleunlessprimitiveisspecied.
ThesevaluesinstructXSTnottosynthesizethebehaviorofamodule.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributebox_type:string;
Specifyasfollows:
attributebox_typeof{component_name|entity_name}:{component|entity}is
"{primitive|black_box|user_black_box}";
Verilog
Placeimmediatelybeforetheinstantiation:
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Chapter7:XSTGeneralConstraints
(*box_type="{primitive|black_box|user_black_box}"*)
XCFSyntaxExampleOne
MODEL"entity_name"box_type="{primitive|black_box|user_black_box}";
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
INST"instance_name"
box_type="{primitive|black_box|user_black_box}";
END;
BusDelimiter(-bus_delimiter)
TheBusDelimiter(-bus_delimiter)commandlineoptiondenestheformatofsignals
belongingtobusesintheoutputnetlist.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestosyntax.
PropagationRules
Notapplicable.
Syntax
-bus_delimiter{<>|[]|{}|()}
•<>(default)
•[]
•{}
•()
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-bus_delimiter[]
Denesbusdelimitersgloballyassquarebraces([]).
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>BusDelimiter
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Chapter7:XSTGeneralConstraints
Case(-case)
TheCase(-case)commandlineoptiondeterminesifinstanceandnetnamesarewritten
inthenalnetlistusingalllowercaseoruppercaseletters,orifthecaseismaintained
fromthesource.
ThecasecanbemaintainedforeitherVerilogorVHDL.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestosyntax.
PropagationRules
Notapplicable.
Syntax
-case{upper|lower|maintain}
•upper
•lower
•maintain(default)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-caseupper
Denescasegloballytouppercase.
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>Case
CaseImplementationStyle(-vlgcase)
TheCaseImplementationStyle(-vlgcase)commandlineoption:
•IsvalidforVerilogdesignsonly.
•InstructsXSThowtointerpretVerilogcasestatements.
Formoreinformation,see:
•MultiplexersHDLCodingTechniques
•FULL_CASE(FullCase)
•PARALLEL_CASE(ParallelCase)
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Chapter7:XSTGeneralConstraints
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-vlgcase{full|parallel|full-parallel}
•full
XSTassumesthatthecasestatementsarecomplete,andavoidslatchcreation.
•parallel
XSTassumesthatthebranchescannotoccurinparallel,anddoesnotuseapriority
encoder.
•full-parallel
XSTassumesthatthecasestatementsarecomplete,andthatthebranchescannot
occurinparallel,thereforesavinglatchesandpriorityencoders.
Bydefault,thereisnovalue.Iftheoptionisnotspecied,XSTimplementstheexact
behaviorofthecasestatements.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-vlgcasefull
DenesCaseImplementationStylegloballytofull.
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>CaseImplementationStyle
DuplicationSuffix(-duplication_suffix)
TheDuplicationSufx(-duplication_sufx)commandlineoptioncontrolshowXST
namesreplicatedip-ops.
Bydefault,whenXSTreplicatesaip-op,itcreatesanameforthenewip-opby
takingthenameoftheoriginalip-opandadding_ntotheendofit,wherenisan
indexnumber.
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Chapter7:XSTGeneralConstraints
Forinstance,iftheoriginalip-opnameismy_ff,andthisip-opwasreplicated
threetimes,XSTgeneratesip-opswiththefollowingnames:
•my_ff_1
•my_ff_2
•my_ff_3
DuplicationSufxletsyouchangethestringthatisaddedtotheoriginalname.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestoles.
PropagationRules
Notapplicable.
Syntax
-duplication_sufxstring%dstring
Thedefaultis%d.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLineExampleOne
xstrun-duplication_sufx_dupreg_%d
Iftheip-opnamedmy_ffisduplicatedthreetimes,thiscommandtellsXSTto
generatethefollowingnames:
•my_ff_dupreg_1
•my_ff_dupreg_2
•my_ff_dupreg_3
XSTCommandLineExampleTwo
xstrun-duplication_sufx_dup_%d_reg
The%descapecharactercanbeplacedanywhereinthesufxdenition.Ifthe
ip-opnamedmy_ffisduplicatedthreetimes,thiscommandtellsXSTtogenerate
thefollowingnames:
•my_ff_dup_1_reg
•my_ff_dup_2_reg
•my_ff_dup_3_reg
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Chapter7:XSTGeneralConstraints
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>Propertydisplaylevel>Advanced
>OtherXSTCommandLineOptions
FullCase(FULL_CASE)
TheFullCase(FULL_CASE)constraint:
•IsvalidforVerilogdesignsonly.
•Indicatesthatallpossibleselectorvalueshavebeenexpressedinacase,casex,or
casezstatement.
•PreventsXSTfromcreatingadditionalhardwareforthoseconditionsnotexpressed.
Formoreinformation,see:
MultiplexersHDLCodingTechniques
ArchitectureSupport
Architectureindependent.
ApplicableElements
AppliestocasestatementsinVerilogmetacomments.
PropagationRules
Notapplicable.
Syntax
-vlgcase[full|parallel|full-parallel]
•full
•parallel
•full-parallel
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
Verilog
Thesyntaxis:
(*full_case*)
SinceFULL_CASEdoesnotcontainatargetreference,theattributeimmediately
precedestheselector:
(*full_case*)
casexselect
4’b1xxx:res=data1;
4’bx1xx:res=data2;
4’bxx1x:res=data3;
4’bxxx1:res=data4;
endcase
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Chapter7:XSTGeneralConstraints
FULL_CASEisalsoavailableasametacommentintheVerilogcode.Thesyntaxdiffers
fromthestandardmetacommentsyntaxasshowninthefollowing:
//synthesisfull_case
SinceFULL_CASEdoesnotcontainatargetreference,themetacommentimmediately
followstheselector:
casexselect//synthesisfull_case
4’b1xxx:res=data1;
4’bx1xx:res=data2;
4’bxx1x:res=data3;
4’bxxx1:res=data4;
endcase
XSTCommandLine
xstrun-vlgcase[full|parallel|full-parallel]
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>FullCase.
ForCaseImplementationStyle,selectfull.
GenerateRTLSchematic(-rtlview)
TheGenerateRTLSchematic(-rtlview)commandlineoptiontellsXSTtogenerate
anetlistlerepresentingaRegisterTransferLevel(RTL)structureofthedesign.This
netlistcanbeviewedbytheRTLandTechnologyViewers.
ThelecontainingtheRTLviewhasanNGRleextension.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestoles.
PropagationRules
Notapplicable.
Syntax
-rtlview{yes|no|only}
•yes
TellsXSTtogenerateanRTLview.
•no(default)
TellsXSTnottogeneratetheRTLview.
•only
TellsXSTtostopthesynthesisoncetheRTLviewisgenerated.
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Chapter7:XSTGeneralConstraints
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-rtlviewyes
TellsXSTtogenerateanetlistlerepresentingtheRTLstructureofthedesign.
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>GenerateRTLSchematic
Generics(-generics)
TheGenerics(-generics)commandlineoptionallowsyoutoredenegenerics(VHDL)
orparameters(Verilog)valuesdenedinthetop-leveldesignblock.
ThisallowsyoutoeasilymodifythedesigncongurationwithoutanyHardware
DescriptionLanguage(HDL)sourcemodications,suchasforIPcoregenerationand
testingows.Ifthedenedvaluedoesnotcorrespondtothedatatypedenedinthe
VHDLorVerilogcode,thenXSTtriestodetectthesituationandissuesawarning,
ignoringthecommandlinedenition.
Insomesituations,XSTmayfailtodetectatypemismatch.Inthatcase,XSTattemptsto
applythisvaluebyadoptingittothetypedenedintheVHDLorVeriloglewithout
anywarning.Besurethatthevalueyouspeciedcorrespondstothetypedenedin
theVHDLorVerilogcode.Ifadenedgenericorparameternamedoesnotexistinthe
design,nomessageisgiven,andthedenitionisignored.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-generics{name=valuename=value...}
where
•nameisthenameofagenericorparameterofthetopleveldesignblock
•valueisthevalueofagenericorparameterofthetopleveldesignblock
Thedefaultisanemptydenition.
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Chapter7:XSTGeneralConstraints
Followtheserules:
•Placethevaluesinsidecurlybraces({...}).
•Separatethevalueswithspaces.
•XSTcanacceptasvaluesonlyconstantsofscalartypes.Compositedatatypes
(arraysorrecords)aresupportedonlyinthefollowingsituations:
–string
–std_logic_vector
–std_ulogic_vector
–signed,unsigned
–bit_vector
•Therearenospacesbetweentheprexandthecorrespondingvalue.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-generics{company="Xilinx"width=5init_vector=b100101}
Thiscommandsets:
•companytoXilinx®
•widthto5
•init_vectortob100101
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>Generics,Parameters
HDLLibraryMappingFile(-xsthdpini)
TheHDLLibraryMappingFile(-xsthdpini)commandlineoptiondenesthelibrary
mapping.
XSTmaintainstwolibrarymappingles:
•Thepre-installed(default)INIle,whichisinstalledduringtheXilinx®software
installation
•Theuserle,whichyoumaydeneforyourownprojects
Thepre-installed(default)INIle:
•Isnamedxhdp.ini.
•Islocatedin%XILINX%\vhdl\xst.
•ContainsinformationaboutthelocationsofthestandardVHDLandUNISIM
libraries.
•Shouldnotbemodied
NoteYoucancopythesyntaxforyourownlibrarymappingle
Alibrarymappinglelookslikethefollowing:
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Chapter7:XSTGeneralConstraints
--DefaultlibmappingforXSTstd=$XILINX/vhdl/xst/std
ieee=$XILINX/vhdl/xst/unisimunisim=$XILINX/vhdl/xst/unisim
aim=$XILINX/vhdl/xst/aimpls=$XILINX/vhdl/xst/pls
Usethisleformattodenewhereeachofyourownlibrariesmustbeplaced.By
default,allcompiledVHDLiesarestoredinthexstsubdirectoryoftheISEDesign
Suiteprojectdirectory.
Thelibrarymappinglecontainsalistoflibraries,oneperlinewiththefollowing
information:
•Thelibraryname
•Thedirectoryinwhichthelibraryiscompiled
Youcangivethislibrarymappingleanynameyouwish,butitisbesttokeepthe
.iniclassication.
Theformatforeachlineis:
library_name=path_to_compiled_directory
Useadoubledash(--)tostartacommentline.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestoles.
PropagationRules
Notapplicable.
Syntax
-xsthdpinile_name
Youcanspecifyonlyonelibrarymappingle.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstset-xsthdpinic:/data/my_libraries/my.inile_name
Speciesc:/data/my_libraries/my.iniasthelethatwillpointtoallofyour
libraries.
Youmustrunthissetcommandbeforeanyruncommands.
FollowingisanMY.INIexampletext:
work1=H:\Users\conf\my_lib\work1work2=C:\mylib\work2
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Chapter7:XSTGeneralConstraints
ISE®DesignSuite
TosetthelibrarymappinglelocationinISEDesignSuite:
1.SelectProcess>ProcessProperties>SynthesisOptions
2.FromthePropertydisplaylevellist,selectAdvanced
3.SettheHDLINIFileproperty.
HierarchySeparator(-hierarchy_separator)
TheHierarchySeparator(-hierarchy_separator)commandlineoptiondenesthe
hierarchyseparatorcharacterthatisusedinnamegenerationwhenthedesignhierarchy
isattened.
Ifadesigncontainsasub-blockwithinstanceINST1,andthissub-blockcontainsanet
calledTMP_NET,thenthehierarchyisattenedandthehierarchyseparatorcharacter
is/(forwardslash).ThenameTMP_NETbecomesINST1_TMP_NET.Ifthehierarchy
separatorcharacteris/(forwardslash),thenetnameisINST1/TMP_NET.
Using/(forwardslash)asahierarchyseparatorisusefulindesigndebuggingbecause
the/(forwardslash)separatormakesitmucheasiertoidentifyanameifitishierarchical.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestoles.
PropagationRules
Notapplicable.
Syntax
-hierarchy_separator{/|_}
Thetwosupportedcharactersare:
•_(underscore)
•/(forwardslash)
Thedefaultis/(forwardslash)fornewlycreatedprojects.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-hierarchy_separator_
Setsthehierarchyseparatorto“_”(underscore)
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Chapter7:XSTGeneralConstraints
ISE®DesignSuite
1.SelectProcess>ProcessProperties>SynthesisOptions.
2.FromthePropertydisplaylevellist,selectAdvanced
3.SettheHierarchySeparatorproperty .
I/OStandard(IOSTANDARD)
TheI/OStandard(IOSTANDARD)constraintassignsanI/OstandardtoanI/O
primitive.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
Keep(KEEP)
Keep(Keep)isanadvancedmappingconstraint.
Whenadesignismapped,somenetsmaybeabsorbedintologicblocks.Whenanet
isabsorbedintoablock,itcannolongerbeseeninthephysicaldesigndatabase.This
mayhappen,forexample,ifthecomponentsconnectedtoeachsideofanetaremapped
intothesamelogicblock.Thenetmaythenbeabsorbedintotheblockcontainingthe
components.Keeppreventsthisfromhappening.
Inadditiontotrueandfalsevaluessupportedbytheimplementationow,XSTsupports
asoftvalue.IfthisvalueisspeciedXSTpreservesthedesignatednetasinthecaseof
thetruevalue,butdoesnotattachtheKeepconstraintinthenalnetlisttothisnet.
Keeppreservestheexistenceofthesignalinthenalnetlist,butnotitsstructure.For
example,ifyourdesignhasa2-bitmultiplexerselectorandyouattachKeeptoit,this
signalispreservedinthenalnetlist.Butthemultiplexercouldbeautomatically
re-encodedbyXSTusingone-hotencoding.Asaconsequence,thissignalinthenal
netlistisfourbitswideinsteadoftheoriginaltwo.Topreservethestructureofthesignal,
inadditiontoKeep,youmustalsouseEnumeratedEncoding(ENUM_ENCODING)’
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
KeepHierarchy(KEEP_HIERARCHY)
TheKeepHierarchy(KEEP_HIERARCHY)constraintisasynthesisandimplementation
constraint.
Ifhierarchyismaintainedduringsynthesis,theimplementationtoolsuseKeep
Hierarchytopreservethehierarchythroughoutimplementation,andallowasimulation
netlisttobecreatedwiththedesiredhierarchy.
XSTcanattenthedesigntoobtainbetterresultsbyoptimizingentityormodule
boundaries.YoucansetKeepHierarchytotruesothatthegeneratednetlistis
hierarchicalandrespectsthehierarchyandinterfaceofanyentityormoduleinyour
design.
KeepHierarchyisrelatedtothehierarchicalblocks(VHDLentities,Verilogmodules)
speciedintheHardwareDescriptionLanguage(HDL)design,anddoesnotconcern
themacrosinferredbytheHDLsynthesizer.
Ingeneral,aHardwareDescriptionLanguage(HDL)designisacollectionofhierarchical
blocks.Preservingthehierarchygivestheadvantageoffastprocessingbecausethe
optimizationisdoneonseparatepiecesofreducedcomplexity.Nevertheless,very
often,mergingthehierarchyblocksimprovesthettingresults(fewerPTermsand
devicemacrocells,betterfrequency)becausetheoptimizationprocesses(collapsing,
factorization)areappliedgloballyontheentirelogic.
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Chapter7:XSTGeneralConstraints
Inthefollowinggure,ifKeepHierarchyissettotheentityormoduleI2,thehierarchy
ofI2isinthenalnetlist,butitscontentsI4,I5areattenedinsideI2.I1,I3,I6,andI7
arealsoattened.
KeepHierarchyDiagram
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestologicalblocks,includingblocksofhierarchyorsymbols.
PropagationRules
Appliestotheentityormoduletowhichitisattached.
Syntax
-keep_hierarchy{yes|no|soft}
•yes
•no
•true
Allowsthepreservationofthedesignhierarchy,asdescribedintheHDLproject.If
thisvalueisappliedtosynthesis,itisalsopropagatedtoimplementation.
ThedefaultistrueforCPLDdevices.
•false
Hierarchicalblocksaremergedinthetoplevelmodule.
ThedefaultisfalseforFPGAdevices.
•soft
Allowsthepreservationofthedesignhierarchyinsynthesis,butKEEP_HIERARCHY
isnotpropagatedtoimplementation.
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Chapter7:XSTGeneralConstraints
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
SchematicSyntaxExample
•Attachtotheentityormodulesymbol.
•AttributeName
KEEP_HIERARCHY
•AttributeValues
SeeSyntaxsectionabove.
VHDL
Declareasfollows:
attributekeep_hierarchy:string;
Specifyasfollows:
attributekeep_hierarchyofarchitecture_name:architectureis"{yes|no|true|false|soft}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*keep_hierarchy="{yes|no|true|false|soft}"*)
XCF
MODEL"entity_name"keep_hierarchy={yes|no|true|false|soft};
XSTCommandLine
xstrun-keep_hierarchy{yes|no|soft}
Formoreinformation,see:
XSTCommandLineMode
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>KeepHierarchy
LibrarySearchOrder(-lso)
TheLibrarySearchOrder(-lso)commandlineoptionspeciesthelocationofthe
librarysearchorderle.
Formoreinformation,see:
LibrarySearchOrder(LSO)FilesinMixedLanguageProjects
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestoles.
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Chapter7:XSTGeneralConstraints
PropagationRules
Notapplicable.
Syntax
-lsole_name.lso
Thereisnodefaultlename.Ifnotspecied,XSTusesthedefaultsearchorder.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstelaborate-lsoc:/data/my_libraries/my.lso
Speciesc:/data/my_libraries/my.lsoasthelethatsetsyourlibrarysearch
order.
ISE®DesignSuite
TospecifythelibrarysearchorderleinISEDesignSuite:
1.SelectProcess>ProcessProperties>SynthesisOptions.
2.FromthePropertydisplaylevellist,selectAdvanced
3.SettheLibrarySearchOrderproperty .
LOC
TheLOCconstraintdeneswhereadesignelementcanbeplacedwithinanFPGAor
CPLDdevice.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
NetlistHierarchy(-netlist_hierarchy)
TheNetlistHierarchy(-netlist_hierarchy)commandlineoption:
•ControlstheforminwhichthenalNGCnetlistisgenerated.
•Allowsyoutowritethehierarchicalnetlisteveniftheoptimizationwasdoneona
partiallyorfullyatteneddesign.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
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Chapter7:XSTGeneralConstraints
Syntax
-netlist_hierarchy{as_optimized|rebuilt}
•as_optimized(default)
XSTtakesintoaccounttheKeepHierarchy(KEEP_HIERARCHY)constraint,and
generatestheNGCnetlistintheforminwhichitwasoptimized.Inthismode,some
hierarchicalblockscanbeattened,andsomecanmaintainhierarchyboundaries.
•rebuilt
XSTwritesahierarchicalNGCnetlist,regardlessoftheKeepHierarchy
(KEEP_HIERARCHY)constraint.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
-netlist_hierarchy{as_optimized|rebuilt}
ISE®DesignSuite
1.SelectProcess>ProcessProperties>SynthesisOptions.
2.FromthePropertydisplaylevellist,selectAdvanced
3.SettheNetlistHierarchyproperty.
OptimizationEffort(OPT_LEVEL)
TheOptimizationEffort(OPT_LEVEL)constraintdenesthesynthesisoptimization
effortlevel.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign,ortoanentityormodule.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
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Chapter7:XSTGeneralConstraints
Syntax
-opt_level{1|2}
•1(normaloptimization)(default)
Use1(normaloptimization)forveryfastprocessing,especiallyforhierarchical
designs.Inspeedoptimizationmode,Xilinx®recommendsusing1(normal
optimization)forthemajorityofdesigns.
•2(higheroptimization)
While2(higheroptimization)ismoretimeconsuming,itsometimesgivesbetter
resultsinthenumberofslices/macrocellsormaximumfrequency.Selecting2
(higheroptimization)usuallyresultsinincreasedsynthesisruntimes,anddoesnot
alwaysbringoptimizationgain.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeopt_level:string;
Specifyasfollows:
attributeopt_levelofentity_name:entityis"{1|2}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*opt_level="{1|2}"*)
XCF
MODEL"entity_name"opt_level={1|2};
XSTCommandLine
xstrun-opt_level{1|2}
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>OptimizationEffort
OptimizationGoal(OPT_MODE)
TheOptimizationGoal(OPT_MODE)constraintdenesthesynthesisoptimization
strategy.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign,ortoanentityormodule.
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Chapter7:XSTGeneralConstraints
PropagationRules
Appliestotheentityormoduletowhichitisattached.
Syntax
-opt_mode{area|speed}
•speed(default)
Thepriorityofspeedistoreducethenumberoflogiclevelsandthereforeto
increasefrequency .
•area
Thepriorityofareaistoreducethetotalamountoflogicusedfordesign
implementationandthereforeimprovedesigntting.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeopt_mode:string;
Specifyasfollows:
attributeopt_modeofentity_name:entityis"{speed|area}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*opt_mode="{speed|area}"*)
XCF
MODEL"entity_name"opt_mode={speed|area};
XSTCommandLine
xstrun-opt_mode{area|speed}
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>OptimizationGoal
ParallelCase(PARALLEL_CASE)
TheParallelCase(PARALLEL_CASE)constraint:
•IsvalidforVerilogdesignsonly.
•Forcesacasestatementtobesynthesizedasaparallelmultiplexer.
•Preventsthecasestatementfrombeingtransformedintoaprioritizedif...elsif
cascade.
Formoreinformation,see:
MultiplexersHDLCodingTechniques.
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Chapter7:XSTGeneralConstraints
ArchitectureSupport
Architectureindependent.
ApplicableElements
AppliestocasestatementsinVerilogmetacommentsonly.
PropagationRules
Notapplicable.
Syntax
-vlgcase{full|parallel|full-parallel}
•full
•parallel
•full-parallel
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
Verilog
(*parallel_case*)
SincePARALLEL_CASEdoesnotcontainatargetreference,theattributeimmediately
precedestheselector.
(*parallel_case*)
casexselect
4’b1xxx:res=data1;
4’bx1xx:res=data2;
4’bxx1x:res=data3;
4’bxxx1:res=data4;
endcase
PARALLEL_CASEisalsoavailableasametacommentintheVerilogcode.Thesyntax
differsfromthestandardmetacommentsyntaxasshowninthefollowing:
//synthesisparallel_case
SincePARALLEL_CASEdoesnotcontainatargetreference,themetacomment
immediatelyfollowstheselector:
casexselect//synthesisparallel_case
4’b1xxx:res=data1;
4’bx1xx:res=data2;
4’bxx1x:res=data3;
4’bxxx1:res=data4;
endcase
XSTCommandLine
xstrun-vlgcase{full|parallel|full-parallel}
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Chapter7:XSTGeneralConstraints
RLOC(RLOC)
TheRLOC(RLOC)constraint:
•Isabasicmappingandplacementconstraint.
•Groupslogicelementsintodiscretesets.
•Allowsyoutodenethelocationofanyelementwithinthesetrelativetoother
elementsintheset,regardlessofeventualplacementintheoveralldesign.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
Verilog
AssuminganSRL16instancenamedsrl1tobeplacedatlocationR9C0.S0,youmay
specifythefollowingintheVerilogcode:
//synthesisattributeRLOCofsrl1:"R9C0.S0";
XCF
YoumayspecifythesameattributeintheXSTConstraintFile(XCF)asfollows:
BEGINMODELENTNAME
INSTsr11RLOC=R9C0.SO;
END;
ThebinaryequivalentofthefollowinglineiswrittentotheoutputNGCle:
INSTsrl1RLOC=R9C0.S0;
Save(S)
TheSave(S)constraintisanadvancedmappingconstraint.
Whenthedesignismapped,somenetsmaybeabsorbedintologicblocks,andsome
elementssuchasLUTscanbeoptimizedaway .Whenanetisabsorbedintoablock,ora
blockisoptimizedaway,itcannolongerbeseeninthephysicaldesigndatabase.Save
(S)preventsthisfromhappening.Severaloptimizationtechniquessuchasnetsorblocks
replicationandregisterbalancingarealsodisabledbytheSave(S)constraint.
IfSave(S)isappliedtoanet,XSTpreservesthenetwithallelementsdirectlyconnected
toitinthenalnetlist.Thisincludesnetsconnectedtotheseelements.
IfSave(S)isappliedtoablocksuchasaLUT,XSTpreservestheLUTwithallsignals
connectedtoit.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
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SynthesisConstraintFile(-uc)
TheSynthesisConstraintFile(-uc)commandlineoptionspeciesthesynthesis
constraintleforXSTtouse.
TheXSTConstraintFile(XCF)hasanextensionof.xcf.Iftheextensionisnot.xcf,
XSTerrorsoutandstopsprocessing.
Formoreinformation,see:
XSTConstraintFile(XCF)
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestoles.
PropagationRules
Notapplicable.
Syntax
-uclename
lenameistheonlyvalue.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-ucmy_constraints.xcf
Speciesmy_constraints.xcfastheconstraintleforthisproject.
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>SynthesisConstraintFile
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Chapter7:XSTGeneralConstraints
TranslateOff(TRANSLATE_OFF)andTranslateOn
(TRANSLATE_ON)
TheTranslateOff(TRANSLATE_OFF)andTranslateOn(TRANSLATE_ON)
constraints:
•InstructXSTtoignoreportionsofVHDLorVerilogcodethatarenotrelevantfor
synthesis,suchassimulationcode.
•AreSynopsysdirectivesthatXSTsupportsinVerilog.Automaticconversionisalso
availableinVHDLandVerilog
•Canbeusedwiththefollowingwords
–synthesis
–Synopsys
–pragma
•Operateasfollows:
–TRANSLATE_OFFmarksthebeginningofthesectiontobeignored.
–TRANSLATE_ONinstructsXSTtoresumesynthesisfromthatpoint.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Applieslocally.
PropagationRules
Instructsthesynthesistooltoenableordisableportionsofcode
Syntax
Thefollowingsectionsshowthesyntaxforthisconstraint.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
--synthesistranslate_off
...codenotsynthesized...
--synthesistranslate_on
Verilog
TheVerilogsyntaxdiffersfromthestandardmetacommentsyntaxpresentedearlier,as
showninthefollowingcodingexample.
//synthesistranslate_off
...codenotsynthesized...
//synthesistranslate_on
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IgnoreSynthesisConstraintsFile(–iuc)
UsetheIgnoreSynthesisConstraintsFile(–iuc)commandlineoptiontoignorethe
constraintlespeciedwithSynthesisConstraintsFile(-uc)duringsynthesis.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestoles.
PropagationRules
Notapplicable.
Syntax
-iuc{yes|no}
•yes
•no(default)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-iucyes
ISEDesignSuite
Caution!IgnoreSynthesisConstraintsFileisshownasSynthesisConstraintsFilein
ISE®DesignSuite.Theconstraintleisignoredifyouuncheckthisoption.Itischecked
bydefault(thereforeresultingina–iucnocommandlineswitch),meaningthatany
synthesisconstraintsleyouspecifyistakenintoaccount.
Process>ProcessProperties>SynthesisOptions>UseSynthesisConstraintsFile
Verilog2001(-verilog2001)
TheVerilog2001(-verilog2001)commandlineoptionenablesordisablesinterpreting
VerilogsourcecodebytheVerilog2001standard.
BydefaultVerilogsourcecodeisinterpretedastheVerilog2001standard.
ArchitectureSupport
Architectureindependent.
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Chapter7:XSTGeneralConstraints
ApplicableElements
Appliestosyntax.
PropagationRules
Notapplicable.
Syntax
-verilog2001{yes|no}
•yes(default)
•no
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstelaborate-verilog2001no
XSTdoesnotinterpretVerilogcodeaccordingtotheVerilog2001standard.
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>V erilog2001
VerilogIncludeDirectories(-vlgincdir)
TheVerilogIncludeDirectories(-vlgincdir)commandlineoptionhelpstheparsernd
lesreferencedby‘includestatements.
Whenan‘includestatementreferencesale,XSTlooksindifferentareasinthisorder:
•Relativetothecurrentdirectory.
•Relativetotheincdirectories.
•Relativetothecurrentle.
NoteVerilogIncludeDirectoriesshouldbeusedwith‘include
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestodirectories.
PropagationRules
Notapplicable.
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Chapter7:XSTGeneralConstraints
Syntax
-vlgincdir{directory_path[directory_path]}
where
directory_pathisthenameofadirectory
Formoreinformation,see:
NamesWithSpacesinCommandLineMode.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstelaborate-vlgincdirc:/my_verilog
Addsc:/my_verilogtothelistofdirectoriesinwhichXSTlooksforale.
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>Propertydisplaylevel>Advanced
>VerilogIncludeDirectories
VerilogMacros(-define)
TheVerilogMacros(-dene)commandlineoption:
•IsvalidforVerilogdesignsonly.
•Allowsyoutodene(orredene)Verilogmacros.
Thisallowsyoutoeasilymodifythedesigncongurationwithoutmodifyingsource
code,suchasforIPcoregenerationandtestingows.Ifthedenedmacroisnotusedin
thedesign,nomessageisgiven.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-dene{name[=value]name[=value]}
where
•nameisamacroname
•valueisthemacrotext
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Chapter7:XSTGeneralConstraints
Thedefaultisanemptydenition.
Note
•Valuesformacrosarenotmandatory.
•Placethevaluesinsidecurlybraces({...}).
•Separatethevalueswithspaces.
•Macrotextcanbespeciedbetweenquotationmarks("..."),orwithoutthem.Ifthe
macrotextcontainsspaces,youmustusequotationmarks("...").
-dene{macro1=Xilinxmacro2="XilinxVirtex4"}
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-denemacro1=Xilinxmacro2="XilinxVirtex4"
Denestwomacrosnamedmacro1andmacro2.
ISEDesignSuite
TodeneVerilogmacrosinISE®DesignSuite:
1.SelectProcess>ProcessProperties>SynthesisOptions.
2.FromthePropertydisplaylevellist,selectAdvanced.
3.SettheV erilogMacrosproperty.
Donotusecurlybraces({...})whenspecifyingvaluesinISEDesignSuite.
WorkDirectory(-xsthdpdir)
WorkDirectory(-xsthdpdir)denesthelocationinwhichVHDL-compiledlesmustbe
placedifthelocationisnotdenedbylibrarymappingles.
ToaccessWorkDirectory:
•InISE®DesignSuite,select:
Process>ProcessProperties>SynthesisOptions>VHDLWorkingDirectory
•Instandalonemode,runthefollowingcommand:
set-xsthdpdirdirectory
Assumeforpurposesofthisexample:
•Threedifferentusersareworkingonthesameproject.
•Theyshareonestandard,precompiledlibrary,shlib.
•Thislibrarycontainsspecicmacroblocksfortheirproject.
•Eachuseralsomaintainsalocalworklibrary.
•User3placesherlocalworklibraryoutsidetheprojectdirectory(forexample,in
c:\temp).
•Users1and2shareanotherlibrary(lib12)betweenthem,butnotwithUser3.
Thesettingsrequiredforthethreeusersareasfollows:
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Chapter7:XSTGeneralConstraints
ExampleUserOne
Mappingle
schlib=z:\sharedlibs\shliblib12=z:\userlibs\lib12
ExampleUserTwo
Mappingle
schlib=z:\sharedlibs\shliblib12=z:\userlibs\lib12
ExampleUserThree
Mappingle
schlib=z:\sharedlibs\shlib
UserThreewillalsoset:
XSTHDPDIR=c:\temp
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestodirectories.
PropagationRules
Notapplicable.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
DeneWorkDirectorygloballywithset-xsthdpdirbeforerunningtheruncommand:
set-xsthdpdirdirectory
WorkDirectorycanacceptasinglepathonly.Youmustspecifythedirectory.There
isnodefault.
ISEDesignSuite
Process>ProcessProperties>SynthesisOptions>VHDLWorkDirectory
ToviewWorkDirectory,select:
Edit>Preferences>Processes>PropertyDisplayLevel>Advanced
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Chapter8
XSTHDLConstraints
ThefollowingHDLconstraintscanbesetgloballyinISE®DesignSuiteinProcess>
ProcessProperties>HDLOptions:
•AutomaticFSMExtraction(FSM_EXTRACT)
•EquivalentRegisterRemoval(EQUIVALENT_REGISTER_REMOVAL)
•FSMEncodingAlgorithm(FSM_ENCODING)
•MuxExtraction(MUX_EXTRACT)
•ResourceSharing(RESOURCE_SHARING)
•SafeImplementation(SAFE_IMPLEMENTATION)
ThefollowingHDLconstraintscannotbesetinProcess>ProcessProperties:
•EnumeratedEncoding(ENUM_ENCODING)
•SafeRecoveryState(SAFE_RECOVERY_STATE)
•SignalEncoding(SIGNAL_ENCODING)
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Chapter8:XSTHDLConstraints
AutomaticFSMExtraction(FSM_EXTRACT)
TheAutomaticFSMExtraction(FSM_EXTRACT)constraint:
•EnablesordisablesFiniteStateMachine(FSM)extractionandspecicsynthesis
optimizations.
•MustbeenabledinordertosetvaluesforFSMEncodingAlgorithm
(FSM_ENCODING).
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-fsm_extract{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributefsm_extract:string;
Specifyasfollows:
attributefsm_extractof{entity_name|signal_name}:{entity|signal}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*fsm_extract="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"fsm_extract={yes|no|true|false};
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Chapter8:XSTHDLConstraints
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"fsm_extract={yes|no|true|false};
END;
XSTCommandLine
xstrun-fsm_extract{yes|no}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>FSMEncodingAlgorithm
Thisoptiondenesboth–fsm_extractandFSMStyle(FSM_STYLE).
•WhenFSMEncodingAlgorithm(FSM_ENCODING)issettonone:
–-fsm_extractissettono
–-fsm_encodingisirrelevantandisleftunspecied
•WhenFSMEncodingAlgorithm(FSM_ENCODING)issettoanyothervalue:
–-fsm_extractissettoyes
–-fsm_encodingissettotheselectedvalue
Formoreinformationabout-fsm_encoding,see:
FSMEncodingAlgorithm(FSM_ENCODING)
EnumeratedEncoding(ENUM_ENCODING)
TheEnumeratedEncoding(ENUM_ENCODING)constraint:
•AppliesaspecicencodingtoaVHDLenumeratedtype.Thevalueisastring
containingspace-separatedbinarycodes.
•CanbespeciedonlyasaVHDLconstraintontheconsideredenumeratedtype.
WhendescribingaFiniteStateMachine(FSM)usinganenumeratedtypeforthestate
register,youmayspecifyaparticularencodingschemewithENUM_ENCODING.
InorderforthisencodingtobeusedbyXST,setFSMEncodingAlgorithm
(FSM_ENCODING)touserfortheconsideredstateregister.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestosignalsortypes.
BecauseENUM_ENCODINGmustpreservetheexternaldesigninterface,XSTignores
ENUM_ENCODINGwhenitisusedonaport.
PropagationRules
Appliestothesignalortypetowhichitisattached.
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Chapter8:XSTHDLConstraints
Syntax
Thefollowingsectionsshowthesyntaxforthisconstraint.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
SpecifyasaVHDLconstraintontheconsideredenumeratedtype:
...
...
architecturebehaviorofexampleis
typestatetypeis(ST0,ST1,ST2,ST3);
attributeenum_encoding:string;
attributeenum_encodingofstatetype:typeis"001010100111";
signalstate1:statetype;
signalstate2:statetype;
begin
...
XCF
BEGINMODEL"entity_name"
NET"signal_name"enum_encoding="string";
END;
EquivalentRegisterRemoval
(EQUIVALENT_REGISTER_REMOVAL)
TheEquivalentRegisterRemoval(EQUIV ALENT_REGISTER_REMOV AL)constraint
enablesordisablesremovalofequivalentregistersdescribedattheRTLLevel.
Bydefault,XSTdoesnotremoveequivalentip-opsiftheyareinstantiatedfroma
Xilinx®primitivelibrary.
Flip-opoptimizationincludesremoving:
•Equivalentip-opsforFPGAandCPLDdevices
•Flip-opswithconstantinputsforCPLDdevices
Thisprocessingincreasesthettingsuccessasaresultofthelogicsimplicationimplied
bytheip-opselimination.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
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Chapter8:XSTHDLConstraints
PropagationRules
Removesequivalentip-opsandip-opswithconstantinputs.
Syntax
-equivalent_register_removal{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
Whenthevalueissettoyes,ip-opoptimizationisallowed.
Whenthevalueissettono,ip-opoptimizationisinhibited.
TipTheip-opoptimizationalgorithmistimeconsuming.Forfastprocessing,useno.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeequivalent_register_removal:string;
Specifyasfollows:
attributeequivalent_register_removalof{entity_name|signal_name}:{signal|entity}
is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*equivalent_register_removal="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"equivalent_register_removal={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"equivalent_register_removal={yes|no|true|false};
END;
XSTCommandLine
xstrun-equivalent_register_removal{yes|no}
ISE®DesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>EquivalentRegisterRemoval
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Chapter8:XSTHDLConstraints
FSMEncodingAlgorithm(FSM_ENCODING)
TheFSMEncodingAlgorithm(FSM_ENCODING)constraintselectstheFiniteState
Machine(FSM)codingtechnique.
InordertoselectavaluefortheFSMEncodingAlgorithm,AutomaticFSMExtraction
(FSM_EXTRACT)mustbeenabled.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-fsm_encoding{auto|one-hot|compact|sequential|gray|johnson|speed1|user}
•auto(default)
Thebestcodingtechniqueisautomaticallyselectedforeachindividualstate
machine.
•one-hot
•compact
•sequential
•gray
•johnson
•speed1
•user
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributefsm_encoding:string;
Specifyasfollows:
attributefsm_encodingof{entity_name|signal_name}:{entity|signal}is
"{auto|one-hot|compact|sequential|gray|johnson|speed1|user}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*fsm_encoding="{auto|one-hot|compact|sequential|gray|johnson|speed1|user}"
*)
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Chapter8:XSTHDLConstraints
XCFSyntaxExampleOne
MODEL"entity_name"
fsm_encoding={auto|one-hot|compact|sequential|gray|johnson|speed1|user};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"fsm_encoding={auto
|one-hot|compact|sequential|gray|johnson|speed1|user};
END;
XSTCommandLine
runxst-fsm_encoding
{auto|one-hot|compact|sequential|gray|johnson|speed1|user}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>FSMEncodingAlgorithm
Theseoptionsare:
•IftheFSMEncodingAlgorithmmenuissettonone,and-fsm_extractissettono,
-fsm_encodinghasnoinuenceonthesynthesis.
•Inallothercases,-fsm_extractissettoyesand-fsm_encodingissettothevalue
selectedinthemenu.
Formoreinformation,see:
AutomaticFSMExtraction(FSM_EXTRACT)
MuxExtraction(MUX_EXTRACT)
TheMuxExtraction(MUX_EXTRACT)constraintenablesordisablesmultiplexermacro
inference.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
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Chapter8:XSTHDLConstraints
Syntax
-mux_extract{yes|no|force}
•yes(default)
•no
•force
•true(XCFonly)
•false(XCFonly)
Bydefault,multiplexerinferenceisenabledwiththeyesoption.Foreachidentied
multiplexerdescription,basedonsomeinternaldecisionrules,XSTactuallycreatesa
macrooroptimizesitwiththerestofthelogic.Theforcevalueoverridesthosedecision
rules,andforcesXSTtocreatetheMUXmacro.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributemux_extract:string;
Specifyasfollows:
attributemux_extractof{signal_name|entity_name}:{entity|signal}is"{yes|no|force}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*mux_extract="{yes|no|force}"*)
XCFSyntaxExampleOne
MODEL"entity_name"mux_extract={yes|no|true|false|force};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"mux_extract={yes|no|true|false|force};
END;
XSTCommandLine
xstrun-mux_extract{yes|no|force}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions
ResourceSharing(RESOURCE_SHARING)
TheResourceSharing(RESOURCE_SHARING)constraintenablesordisablesresource
sharingofarithmeticoperators.
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Chapter8:XSTHDLConstraints
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign,ortodesignelements.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-resource_sharing{yes|no}
•yes(default)
•no
•force
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeresource_sharing:string;
Specifyasfollows:
attributeresource_sharingofentity_name:entityis"{yes|no}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*resource_sharing="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"resource_sharing={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"resource_sharing={yes|no|true|false};
END;
XSTCommandLine
xstrun-resource_sharing{yes|no}
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Chapter8:XSTHDLConstraints
ISE®DesignSuite
HDLOptions>ResourceSharing
SafeImplementation(SAFE_IMPLEMENTATION)
TheSafeImplementation(SAFE_IMPLEMENTATION)constraintimplementsFinite
StateMachine(FSM)componentsinSafeImplementationmode.
InSafeImplementationmode,XSTgeneratesadditionallogicthatforcesanFSM
toavalidstate(recoverystate)iftheFSMentersaninvalidstate.Bydefault,XST
automaticallyselectsresetastherecoverystate.IftheFSMdoesnothaveaninitialization
signal,XSTselectspower-upastherecoverystate.
DenetherecoverystatemanuallywithSafeRecoveryState(SAFE_RECOVERY_STATE).
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliesto:
•AnentiredesignthroughtheXSTcommandline
•Aparticularblock(entity ,architecture,component)
•Asignal
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-safe_implementation{yes|no}
•yes
•no(default)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributesafe_implementation:string;
Specifyasfollows:
attributesafe_implementationof{entity_name|component_name|signal_name}:
{entity|component|signal}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*safe_implementation="{yes|no}"*)
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Chapter8:XSTHDLConstraints
XCFSyntaxExampleOne
MODEL"entity_name"safe_implementation={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"safe_implementation={yes|no|true|false};
END;
XSTCommandLine
xstrun-safe_implementation{yes|no}
ISE®DesignSuite
ToactivateSafeImplementationin:
•ISEDesignSuite
SelectProcess>ProcessProperties>HDLOptions>SafeImplementation
•HardwareDescriptionLanguage(HDL)
ApplySafeImplementationtothehierarchicalblockorsignalthatrepresentsthe
stateregisterintheFSM.
SignalEncoding(SIGNAL_ENCODING)
TheSignalEncoding(SIGNAL_ENCODING)constraintselectsthecodingtechniqueto
useforinternalsignals.
ArchitectureSupport
Architectureindependent.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-signal_encoding{auto|one-hot|user}
•auto(default)
Thebestcodingtechniqueisautomaticallyselectedforeachindividualsignal.
•one-hot
Forcestheencodingtoaone-hotencoding.
•user
ForcesXSTtokeepyourencoding.
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Chapter8:XSTHDLConstraints
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributesignal_encoding:string;
Specifyasfollows:
attributesignal_encodingof{component_name|signal_name|entity_name|label_name}:
{component|signal|entity|label}is"{auto|one-hot|user}";
Verilog
Placeimmediatelybeforethesignaldeclaration:
(*signal_encoding="{auto|one-hot|user}"*)
XCFSyntaxExampleOne
MODEL"entity_name"signal_encoding={auto|one-hot|user};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"signal_encoding={auto|one-hot|user};
END;
XSTCommandLine
xstrun-signal_encoding{auto|one-hot|user}
SafeRecoveryState(SAFE_RECOVERY_STATE)
TheSafeRecoveryState(SAFE_RECOVERY_STATE)constraintdenesarecoverystate
forusewhenaFiniteStateMachine(FSM)isimplementedinSafeImplementationmode.
IftheFSMentersaninvalidstate,XSTusesadditionallogictoforcetheFSMtoa
validrecoverystate.ByimplementingFSMinsafemode,XSTcollectsallcodenot
participatinginthenormalFSMbehaviorandtreatsitasillegal.
XSTuseslogicthatreturnstheFSMsynchronouslytothe:
•Knownstate
•Resetstate
•Powerupstate
•StateyouspeciedusingSafeRecoveryState
Formoreinformation,see:
SafeImplementation(SAFE_IMPLEMENTATION)
ArchitectureSupport
Architectureindependent.
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ApplicableElements
Appliestoasignalrepresentingastateregister.
PropagationRules
Appliestothesignaltowhichitisattached.
Syntax
Thefollowingsectionsshowthesyntaxforthisconstraint.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributesafe_recovery_state:string;
Specifyasfollows:
attributesafe_recovery_stateof{signal_name}:signalis"<value>";
Verilog
Placeimmediatelybeforethesignaldeclaration:
(*safe_recovery_state="<value>"*)
XCF
BEGINMODEL"entity_name"
NET"signal_name"safe_recovery_state="<value>";
END;
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Chapter9
XSTFPGAConstraints(Non-Timing)
Important!TheconstraintsdescribedinthischapterapplytoFPGAdevicesonly.They
donotapplytoCPLDdevices.
Thischapterdiscussesthefollowingconstraints:
•AsynchronoustoSynchronous(ASYNC_TO_SYNC)
•AutomaticBRAMPacking(AUTO_BRAM_PACKING)
•BRAMUtilizationRatio(BRAM_UTILIZATION_RATIO)
•BufferType(BUFFER_TYPE)
•ConvertTristatestoLogic(TRISTATE2LOGIC)
•CoresSearchDirectories(-sd)
•DecoderExtraction(DECODER_EXTRACT)
•DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
•ExtractBUFGCE(BUFGCE)
•FSMStyle(FSM_STYLE)
•LUTCombining(LC)
•PowerReduction(POWER)
•ReadCores(READ_CORES)
•LogicalShifterExtraction(SHIFT_EXTRACT)
•MapEntityonaSingleLUT(LUT_MAP)
•MapLogiconBRAM(BRAM_MAP)
•MaxFanout(MAX_FANOUT)
•MoveFirstStage(MOVE_FIRST_STAGE)
•MoveLastStage(MOVE_LAST_STAGE)
•MultiplierStyle(MULT_STYLE)
•MuxStyle(MUX_STYLE)
•NumberofGlobalClockBuffers(-bufg)
•NumberofRegionalClockBuffers(-bufr)
•OptimizeInstantiatedPrimitives(OPTIMIZE_PRIMITIVES)
•PackI/ORegistersIntoIOBs(IOB)
•PriorityEncoderExtraction(PRIORITY_EXTRACT)
•RAMExtraction(RAM_EXTRACT)
•RAMStyle(RAM_STYLE)
•ReduceControlSets(REDUCE_CONTROL_SETS)
•RegisterBalancing(REGISTER_BALANCING)
•RegisterDuplication(REGISTER_DUPLICATION)
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Chapter9:XSTFPGAConstraints(Non-Timing)
•ROMExtraction(ROM_EXTRACT)
•ROMStyle(ROM_STYLE)
•ShiftRegisterExtraction(SHREG_EXTRACT)
•SlicePacking(-slice_packing)
•Slice(LUT-FFPairs)UtilizationRatio(SLICE_UTILIZATION_RATIO)
•Slice(LUT-FFPairs)UtilizationRatioDelta
(SLICE_UTILIZATION_RATIO_MAXMARGIN)
•UseCarryChain(USE_CARRY_CHAIN)
•UseClockEnable(USE_CLOCK_ENABLE)
•UseSynchronousSet(USE_SYNC_SET)
•UseSynchronousReset(USE_SYNC_RESET)
•UseDSP48(USE_DSP48)
•XORCollapsing(XOR_COLLAPSE)
Someconstraintscanbeapplied:
•globallytoanentireentityormodel,OR
•locallytoindividualsignals,netsorinstances
Forvalidconstrainttargets,see:
•XSTSpecicNon-TimingOptions
•XSTSpecicNon-TimingOptionsSupportedOnlyintheCommandLine
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Chapter9:XSTFPGAConstraints(Non-Timing)
AsynchronoustoSynchronous(ASYNC_TO_SYNC)
TheAsynchronoustoSynchronous(ASYNC_TO_SYNC)constraint:
•AllowsyoutoreplaceAsynchronousSet/ResetsignalswithSynchronoussignals
throughouttheentiredesign.
•AllowsabsorptionofregistersbyDSP48andBRAMs,therebyimprovingquality
ofresults.
•Mayhaveapositiveimpactonpoweroptimization.
AlthoughXSTcanplaceFiniteStateMachine(FSM)componentsonBRAMs,inmost
casesanFSMhasanAsynchronousSet/Resetsignal,whichdoesnotallowFSM
implementationonBRAMs.ASYNC_TO_SYNCallowsyoutomoreeasilyplaceFSMs
onBRAMsbyeliminatingtheneedtomanuallychangethedesign.
ReplacingAsynchronousSet/ResetsignalsbySynchronoussignalsmakesthegenerated
NGCnetlistNOTequivalenttotheinitialRTLdescription.Youmustensurethatthe
synthesizeddesignsatisestheinitialspecication.XSTissuesthefollowingwarning:
WARNING:Youhaverequestedthatasynchronouscontrolsignals
ofsequentialelementsbetreatedasiftheyweresynchronous.
Ifyouhaven’tdonesoyet,pleasecarefullyreviewtherelated
documentationmaterial.Ifyouhaveoptedtoasynchronously
controlflip-flopinitialization,thisfeatureallowsyou
tobetterexplorethepossibilitiesofferedbytheXilinx
solutionwithouthavingtogothroughapainfulrewriting
effort.However,bewellawarethatthesynthesisresult,while
providingyouwithagoodwaytoassessfinaldeviceusageand
designperformance,isnotfunctionallyequivalenttoyourHDL
description.Asaresult,youwillnotbeabletovalidate
yourdesignbycomparisonofpre-synthesisandpost-synthesis
simulationresults.Pleasealsonotethatingeneralwestrongly
recommendsynchronousflip-flopinitialization.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-async_to_sync{yes|no}
•yes
•no(default)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
Frontmatter
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XSTCommandLine
xstrun-async_to_syncyes
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>AsynchronoustoSynchronous
AutomaticBRAMPacking(AUTO_BRAM_PACKING)
TheAutomaticBRAMPacking(AUTO_BRAM_PACKING)constraintallowsyouto
packtwosmallBRAMsinasingleBRAMprimitiveasdual-portBRAM.
XSTpacksBRAMstogetheronlyiftheyaresituatedinthesamehierarchicallevel.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-auto_bram_packing{yes|no}
•yes
•no(default)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-auto_bram_packingno
ISE®DesignSuite
Process>ProcessProperties>AutomaticBRAMPacking
BRAMUtilizationRatio(BRAM_UTILIZATION_RATIO)
TheBRAMUtilizationRatio(BRAM_UTILIZATION_RATIO)constraintdenesthe
numberofBRAMblocksthatXSTmustnotexceedduringsynthesis.
BRAMsinthedesignmaycomenotonlyfromBRAMinferenceprocesses,butfrom
instantiationandBRAMmappingoptimizations.YoumayisolateanRTLdescriptionof
logicinaseparateblock,andthenaskXSTtomapthislogictoBRAM.
Formoreinformation,see:
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MappingLogicOntoBlockRAM
InstantiatedBRAMsaretheprimarycandidatesforavailableBRAMresources.The
inferredRAMsareplacedontheremainingBRAMresources.However,ifthenumber
ofinstantiatedBRAMsexceedsthenumberofavailableresources,XSTdoesnotmodify
theinstantiationsandimplementthemasblockRAMs.Thesamebehavioroccursif
youforcespecicRAMstobeimplementedasBRAMs.Iftherearenoresources,XST
respectsuserconstraints,evenifthenumberofBRAMresourcesisexceeded.
Ifthenumberofuser-speciedBRAMsexceedsthenumberofavailableBRAM
resourcesonthetargetFPGAdevice,XSTissuesawarning,andusesonlyavailable
BRAMresourcesonthechipforsynthesis.However,youmaydisableautomaticBRAM
resourcemanagementbyusingvalue-1.ThiscanbeusedtoseethenumberofBRAMs
XSTcanpotentiallyinferforaspecicdesign.
YoumayexperiencesignicantsynthesistimeifthenumberofBRAMsinthedesign
signicantlyexceedsthenumberofavailableBRAMsonthetargetFPGAdevice
(hundredsofBRAMs).Thismayhappenduetoasignicantincreaseindesign
complexitywhenallnon-ttableBRAMsareconvertedtodistributedRAMs.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
•%
•#
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-bram_utilization_ratio<integer>[%][#]
where
<integer>rangeis[-1to100]when%isusedorboth%and#areomitted
Thedefaultis100.
XSTCommandLineSyntaxExampleOne
xstrun-bram_utilization_ratio50
where
50means50%ofBRAMblocksinthetargetdevice
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Chapter9:XSTFPGAConstraints(Non-Timing)
XSTCommandLineSyntaxExampleTwo
xstrun-bram_utilization_ratio50%
where
50%means50%ofBRAMblocksinthetargetdevice
XSTCommandLineSyntaxExampleThree
xstrun-bram_utilization_ratio50#
where
50#means50BRAMblocks
Theremustbenospacebetweentheintegervalueandthepercent(%)orpound(#)
characters.
Insomesituations,youcandisableautomaticBRAMresourcemanagement(forexample,
toseehowmanyBRAMsXSTcanpotentiallyinferforaspecicdesign).Todisable
automaticresourcemanagement,specify-1(oranynegativevalue)asaconstraintvalue.
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>BRAMUtilizationRatio
InISEDesignSuite,youcandenethevalueofBRAMUtilizationRatioonlyasa
percentage.ThedenitionofthevalueintheformofabsolutenumberofBRAMsis
notsupported.
BufferType(BUFFER_TYPE)
TheBufferType(BUFFER_TYPE)constraintselectsthetypeofbuffertobeinserted
ontheinputportorinternalnet.
XSTsupportsthebufrvalueforVirtex®-4devicesandVirtex-5devicesonly.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestosignals.
PropagationRules
Appliestothesignaltowhichitisattached.
Syntax
•bufgdll
•ibufg
•bufgp
•ibuf
•bufr
•none
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SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributebuffer_type:string;
Specifyasfollows:
attributebuffer_typeofsignal_name:signalis"
{bufgdll|ibufg|bufgp|ibuf|bufr|none}";
Verilog
Placeimmediatelybeforethesignaldeclaration:
(*buffer_type="{bufgdll|ibufg|bufgp|ibuf|bufr|none}"*)
XCF
BEGINMODEL"entity_name"
NET"signal_name"buffer_type={bufgdll|ibufg|bufgp|ibuf|bufr|none};
END;
ConvertTristatestoLogic(TRISTATE2LOGIC)
Sincesomedevicesdonotsupportinternaltristates,XSTautomaticallyreplacestristates
withequivalentlogic.Becausethelogicgeneratedfromtristatescanbecombinedand
optimizedwithsurroundinglogic,tristatetologicreplacementforotherdevicescan
leadtobetterspeed,andinsomecases,betterareaoptimization.Butingeneraltristate
tologicreplacementmayleadtoareaincrease.IftheoptimizationgoalisArea,you
shouldapplyConvertTristatestoLogicsettono.
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Chapter9:XSTFPGAConstraints(Non-Timing)
LimitationstoConvertTristatestoLogic
FollowingarelimitationstoConvertTristatestoLogic:
•Onlyinternaltristatesarereplacedbylogic.Thetristatesofthetopmodule
connectedtooutputpadsarepreserved.
•ConvertTristatestoLogicdoesnotapplytotechnologiesthatdonothaveinternal
tristates,suchasSpartan®-3devicesorVirtex®-4devices.Inthiscase,the
conversionoftristatestologicisperformedautomatically.InsomesituationsXST
isunabletomakethereplacementautomatically ,duetothefactthatthismaylead
towrongdesignbehaviorormulti-source.Thismayhappenwhenthehierarchy
ispreservedorXSTdoesnothavefulldesignvisibility(forexample,designis
synthesizedonablock-by-blockbasis).Inthesecases,XSTissuesawarningatthe
lowleveloptimizationstep.Dependingontheparticulardesignsituation,you
maycontinuethedesignowandthereplacementcouldbedonebyMAP ,oryou
canforcethereplacementbyapplyingConvertTristatestoLogicsettoyesona
particularblockorsignal.
•ThesituationsinwhichXSTisunabletoreplaceatristatebylogicare:
–Thetristateisconnectedtoablackbox.
–Thetristateisconnectedtotheoutputofablock,andthehierarchyoftheblock
ispreserved.
–Thetristateisconnectedtoatop-leveloutput.
–ConvertTristatestoLogicissettonoontheblockwheretristatesareplaced,
oronthesignalstowhichtristatesareconnected.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliesto:
•AnentiredesignthroughtheXSTcommandline
•Aparticularblock(entity ,architecture,component)
•Asignal
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-tristate2logic{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
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Chapter9:XSTFPGAConstraints(Non-Timing)
VHDL
Declareasfollows:
attributetristate2logic:string;
Specifyasfollows:
attributetristate2logicof{entity_name|component_name|signal_name}:
{entity|component|signal}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*tristate2logic="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"tristate2logic={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"tristate2logic={yes|no|true|false};
END;
XSTCommandLine
xstrun-tristate2logic{yes|no}
ISE®DesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>ConvertTristatestoLogic
CoresSearchDirectories(-sd)
TheCoresSearchDirectories(-sd)commandlineoptiontellsXSTtolookforcoresin
directoriesotherthanthedefault.
BydefaultXSTsearchesforcoresinthedirectoryspeciedinthe-ifnoption.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-sd{directory_path[directory_path]]
Theonlyvalueisdirectory_path.Thereisnodefault.
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SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-sdc:/data/coresc:/ise/cores
TellsXSTtosearchforcoresinc:/data/coresandc:/ise/coresinadditionto
thedefaultdirectory.
Formoreinformation,see:
NamesWithSpacesinCommandLineMode
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>CoresSearchDirectory
DecoderExtraction(DECODER_EXTRACT)
TheDecoderExtraction(DECODER_EXTRACT)constraintenablesordisablesdecoder
macroinference.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Whenattachedtoanetorsignal,DecoderExtractionappliestotheattachedsignal.
Whenattachedtoanentityormodule,DecoderExtractionispropagatedtoallapplicable
elementsinthehierarchywithintheentityormodule.
Syntax
-decoder_extract{yes|no}
•yes(default)
•no
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
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attributedecoder_extract:string;
Specifyasfollows:
attributedecoder_extractof{entity_name|signal_name}:{entity|signal}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*decoder_extract"{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"decoder_extract={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"decoder_extract={yes|no|true|false};
END;
XSTCommandLine
xstrun-decoder_extract{yes|no}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>DecoderExtraction
DSPUtilizationRatio(DSP_UTILIZATION_RATIO)
TheDSPUtilizationRatio(DSP_UTILIZATION_RATIO)constraintdenesthenumber
ofDSPslices(inabsolutenumberorpercentofslices)thatXSTmustnotexceedduring
synthesisoptimization.
Thedefaultis100%ofthetargetdevice.
DSPslicesinthedesignmaycomenotonlyfromDSPinferenceprocesses,butalso
frominstantiation.InstantiatedDSPslicesaretheprimarycandidatesforavailableDSP
resources.TheinferredDSPsareplacedontheremainingDSPresources.Ifthenumber
ofinstantiatedDSPsexceedsthenumberofavailableresources,XSTdoesnotmodifythe
instantiationsandimplementthemasblockDSPslices.Thesamebehavioroccursifyou
forcespecicmacroimplementationtobeimplementedasDSPslicesbyusingtheUse
DSP48(USE_DSP48)constraint.Iftherearenoresources,XSTrespectsuserconstraints
evenifthenumberofDSPslicesisexceeded.
Ifthenumberofuser-speciedDSPslicesexceedsthenumberofavailableDSPresources
onthetargetFPGAdevice,XSTissuesawarning,andusesonlyavailableDSPresources
onthechipforsynthesis.
YoucandisableautomaticDSPresourcemanagement(forexample,toseehowmany
DSPsXSTcanpotentiallyinferforaspecicdesign)byspecifying-1(oranynegative
value)asaconstraintvalue.
Frontmatter
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Chapter9:XSTFPGAConstraints(Non-Timing)
ArchitectureSupport
Appliestothefollowingdevicesonly.Doesnotapplytoanyotherdevices.
•Virtex®-4
•Virtex-5
•Spartan®-3ADSP
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
Thefollowingsectionsshowthesyntaxforthisconstraint.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
-dsp_utilization_ratiointeger[%|#]
where
integeris[-1to100]when
–%isused,or
–both%and#areomitted
Tospecifyapercentoftotalslicesuse%.Tospecifyanabsolutenumberofslicesuse#
Thedefaultis%.
Forexample:
•Tospecify50%ofDSPblocksofthetargetdeviceenter:
-dsp_utilization_ratio50
•Tospecify50%ofDSPblocksofthetargetdeviceenter:
-dsp_utilization_ratio50%
•Tospecify50DSPblocksenter:
-dsp_utilization_ratio50#
NoteTheremustbenospacebetweentheintegervalueandthepercent(%)orpound
(#)characters.
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>DSPUtilizationRatio
InISEDesignSuite,youcandenethevalueofDSPUtilizationRatioonlyasa
percentage.Youcannotdenethevalueasanabsolutenumberofslices.
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Chapter9:XSTFPGAConstraints(Non-Timing)
ExtractBUFGCE(BUFGCE)
TheExtractBUFGCE(BUFGCE)constraint:
•ImplementsBUFGMUXfunctionalitybyinferringaBUFGMUXprimitive.
Thisoperationreducesthewiring.Clockandclockenablesignalsaredriventon
sequentialcomponentsbyasinglewire.
•Mustbeattachedtotheprimaryclocksignal.
•IsaccessiblethroughHardwareDescriptionLanguage(HDL)code.
Ifbufgce=yes,XSTimplementsBUFGMUXfunctionalityifpossible.Allip-ops
musthavethesameclockenablesignal.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestoclocksignals.
PropagationRules
Appliestothesignaltowhichitisattached.
Syntax
•yes
•no
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDLSyntaxExample
Declareasfollows:
attributebufgce:string;
Specifyasfollows:
attributebufgceofsignal_name:signalis"{yes|no}";
Verilog
Placeimmediatelybeforethesignaldeclaration:
(*bufgce="{yes|no}"*)
XCF
BEGINMODEL"entity_name"
NET"primary_clock_signal"bufgce={yes|no|true|false};
END;
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Chapter9:XSTFPGAConstraints(Non-Timing)
FSMStyle(FSM_STYLE)
TheFSMStyle(FSM_STYLE)constraint:
•Isbothaglobalandalocalconstraint.
•CanmakelargeFiniteStateMachine(FSM)componentsmorecompactandfaster
byimplementingthemintheblockRAMresourcesprovidedinVirtex®devices
andlater.
•CanbeusedtodirectXSTtouseblockRAMresourcesratherthanLUTs(default)to
implementFSMs.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
•lut(default)
•bram
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributefsm_style:string;
Declareasfollows:
attributefsm_styleof{entity_name|signal_name}:{entity|signal}is"{lut|bram}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*fsm_style="{lut|bram}"*)
XCFSyntaxExampleOne
MODEL"entity_name"fsm_style={lut|bram};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name”
NET"signal_name"fsm_style={lut|bram};
END;
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Chapter9:XSTFPGAConstraints(Non-Timing)
XCFSyntaxExampleThree
BEGINMODEL"entity_name"
INST"instance_name"fsm_style={lut|bram};
END;
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>FSMStyle
LogicalShifterExtraction(SHIFT_EXTRACT)
TheLogicalShifterExtraction(SHIFT_EXTRACT)constraintenablesordisableslogical
shiftermacroinference.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortodesignelementsandnets.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-shift_extract{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeshift_extract:string;
Specifyasfollows:
attributeshift_extractof{entity_name|signal_name}:{signal|entity}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*shift_extract="{yes|no}"*)
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XCFSyntaxExampleOne
MODEL"entity_name"shift_extract={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"shift_extract={yes|no|true|false};
END;
XSTCommandLine
xstrun-shift_extract{yes|no}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>LogicalShifterExtraction
LUTCombining(LC)
TheLUTCombining(LC)constraintenablesthemergingofLUTpairswithcommon
inputsintosingledual-outputLUT6sinordertoimprovedesignarea.Thisoptimization
processmayreducedesignspeed.
ArchitectureSupport
AppliestoVirtex®-5devicesonly.Doesnotapplytoanyotherdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-lc{auto|area|off}
•auto
XSTtriestomakeatrade-offbetweenareaandspeed.
•area
XSTperformsmaximumLUTcombiningtoprovideassmallanimplementationas
possible.
•off(default)
DisablesLUTCombining.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
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Chapter9:XSTFPGAConstraints(Non-Timing)
XSTCommandLine
xstrun-lc{auto|area|off}
ISE®DesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>LUTCombining
MapEntityonaSingleLUT(LUT_MAP)
TheMapEntityonaSingleLUT(LUT_MAP)constraintforcesXSTtomapasingleblock
intoasingleLUT.IfadescribedfunctiononanRTLleveldescriptiondoesnottina
singleLUT,XSTissuesanerrormessage.
UsetheUNISIMlibrarytodirectlyinstantiateLUTcomponentsinyourHardware
DescriptionLanguage(HDL)code.TospecifyafunctionthataparticularLUTmust
execute,applyanINITconstrainttotheinstanceoftheLUT.Toplaceaninstantiated
LUTorregisterinaparticularslice,attachanRLOCconstrainttothesameinstance.
ItisnotalwaysconvenienttocalculateINITfunctionsanddifferentmethodscanbe
usedtoachievethis.Instead,youcandescribethefunctionthatyouwanttomapontoa
singleLUTinyourVHDLorVerilogcodeinaseparateblock.AttachingaLUT_MAP
constrainttothisblockindicatestoXSTthatthisblockmustbemappedonasingle
LUT.XSTautomaticallycalculatestheINITvaluefortheLUTandpreservesthisLUT
duringoptimization.
Formoreinformation,see:
SpecifyingINITandRLOC
XSTautomaticallyrecognizestheXC_MAPconstraintsupportedbySynopsys.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
AppliestoaVHDLentityorVerilogmodule.
PropagationRules
Appliestotheentityormoduletowhichitisattached.
Syntax
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
Frontmatter
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Chapter9:XSTFPGAConstraints(Non-Timing)
attributelut_map:string;
Specifyasfollows:
attributelut_mapofentity_name:entityis"{yes|no}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*lut_map="{yes|no}"*)
XCF
MODEL"entity_name"lut_map={yes|no|true|false};
MapLogiconBRAM(BRAM_MAP)
TheMapLogiconBRAM(BRAM_MAP)constraint:
•Isbothaglobalandalocalconstraint.
•IsusedtomapanentirehierarchicalblockontheblockRAMresourcesavailablein
Virtex®devicesandlatertechnologies.
Formoreinformation,see:
MappingLogicOntoBlockRAM
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
BRAMs.
PropagationRules
Isolatethelogic(includingoutputregister)tobemappedonRAMinaseparate
hierarchicallevel.LogicthatdoesnottonasingleblockRAMisnotmapped.Ensure
thatthewholeentityts,notjustpartofit.
TheattributeBRAM_MAPissetontheinstanceorentity .IfnoblockRAMcanbe
inferred,thelogicispassedtoGlobalOptimization,whereitisoptimized.Themacros
arenotinferred.BesurethatXSThasmappedthelogic.
Syntax
•yes
•no(default)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
Frontmatter
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Chapter9:XSTFPGAConstraints(Non-Timing)
VHDL
Declareasfollows:
attributebram_map:string;
Specifyasfollows:
attributebram_mapofcomponent_name:componentis"{yes|no}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*bram_map="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"bram_map={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
INST"instance_name"bram_map={yes|no|true|false};
END;
MaxFanout(MAX_FANOUT)
TheMaxFanout(MAX_FANOUT)constraint:
•Isbothaglobalandalocalconstraint.
•Limitsthefanoutofnetsorsignals.
Largefanoutscancauseroutabilityproblems.SeeConstraintValuesbelow.XSTtriesto
limitfanoutbyduplicatinggatesorbyinsertingbuffers.Thislimitisnotatechnology
limit,butonlyaguidetoXST.Thislimitmaynotbepreciselyrespected,especiallywhen
thelimitissmall(lessthan30).
Inmostcases,fanoutcontrolisperformedbyduplicatingthegatedrivingthenetwitha
largefanout.Iftheduplicationcannotbeperformed,buffersareinserted.Thesebuffers
areprotectedagainstlogictrimmingattheimplementationlevelbydeningaKeep
(KEEP)attributeintheNGCle.
Iftheregisterreplicationoptionissettono,onlybuffersareusedtocontrolfanout
ofip-opsandlatches.
MaxFanoutisglobalforthedesign,butyoucancontrolmaximumfanoutindependently
foreachentityormoduleorforgivenindividualsignalsbyusingconstraints.
IftheactualnetfanoutislessthantheMaxFanoutvalue,XSTbehaviordependsonhow
MaxFanoutisspecied.
•IfthevalueofMaxFanoutissetinISE®DesignSuiteorinthecommandline,oris
attachedtoaspecichierarchicalblock,XSTinterpretsitsvalueasaguidance.
•IfMaxFanoutisattachedtoaspecicnet,XSTdoesnotperformlogicreplication.
PlacingMaxFanoutonthenetmaypreventXSTfromimprovingtiming
optimization.
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Chapter9:XSTFPGAConstraints(Non-Timing)
Forexample,supposethefollowing:
•Thecriticalpathgoesthroughthenet.
•Theactualfanoutis80.
•TheMaxFanoutvalueissetto100.
Inthatinstance:
•IfMaxFanoutisspeciedinISEDesignSuite,XSTmayreplicateit,tryingto
improvetiming.
•IfMaxFanoutisattachedtothenetitself,XSTdoesnotperformlogicreplication.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-max_fanoutinteger
Theconstraintvalueisaninteger.Thedefaultvaluevariesdependingonthetargeted
devicefamilyasshowninthefollowingtable.
MaxFanoutDefaultValue
DevicesDefaultValue
Spartan®-3
Spartan-3E
Spartan-3A
Spartan-3ADSP
500
Virtex®-4500
Virtex-5100000(OneHundredThousand)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributemax_fanout:string;
Specifyasfollows:
attributemax_fanoutof{signal_name|entity_name}:{signal|entity}is"integer";
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Chapter9:XSTFPGAConstraints(Non-Timing)
Verilog
Placeimmediatelybeforethesignaldeclaration:
(*max_fanout="integer"*)
XCFSyntaxExampleOne
MODEL"entity_name"max_fanout=integer;
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"max_fanout=integer;
END;
XSTCommandLine
xstrun-max_fanoutinteger
ISEDesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>MaxFanout
MoveFirstStage(MOVE_FIRST_STAGE)
TheMoveFirstStage(MOVE_FIRST_STAGE)constraintcontrolstheretimingof
registerswithpathscomingfromprimaryinputs.
BothMoveFirstStageandMoveLastStage(MOVE_LAST_STAGE)relatetoRegister
Balancing.
Severalconstraintsinuenceregisterbalancing.
Formoreinformation,see:
RegisterBalancing(REGISTER_BALANCING)
Note
•Aip-op(FFinthediagram)belongstotheFirstStageifitisonthepathscoming
fromprimaryinputs.
•Aip-opbelongstotheLastStageifitisonthepathsgoingtoprimaryoutputs.
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MoveFirstStageDiagram
DuringRegisterBalancing
Duringregisterbalancing:
•FirstStageip-opsaremovedforward
•LastStageip-opsaremovedbackward.
Thisprocesscandramaticallyincreaseinput-to-clockandclock-to-outputtiming,
whichisnotdesirable.Topreventthis,youmayuseOFFSET_IN_BEFOREand
OFFSET_IN_AFTERconstraints.
If:
•Thedesigndoesnothaveastrongrequirements,or
•Youwanttoseetherstresultswithouttouchingtherstandlastip-opstages,
Youcanusetwoadditionalconstraints:
•MoveFirstStage
•MoveLastStage
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestothefollowingonly:
•Entiredesign
•Singlemodulesorentities
•Primaryclocksignal
PropagationRules
ForMoveFirstStagepropagationrules,seethegureabove.
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Syntax
-move_rst_stage{yes|no}
BothMoveFirstStageandMoveLastStagemayhaveeitheroftwovalues:
•yes
•no
–MOVE_FIRST_STAGE=no
Preventstherstip-opstagefrommoving
–MOVE_LAST_STAGE=no
Preventsthelastip-opstagefrommoving
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributemove_rst_stage:string;
Specifyasfollows:
attributemove_rst_stageof{entity_name|signal_name}:{signal|entity}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*move_rst_stage="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"move_rst_stage={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"primary_clock_signal"move_rst_stage={yes|no|true|false};
END;
XSTCommandLine
xstrun-move_rst_stage{yes|no}
ISE®DesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>MoveFirstFlip-FlopStage
MoveLastStage(MOVE_LAST_STAGE)
TheMoveLastStage(MOVE_LAST_STAGE)constraintcontrolstheretimingof
registerswithpathsgoingtoprimaryoutputs.
BothMoveLastStageandMoveFirstStage(MOVE_FIRST_STAGE)relatetoRegister
Balancing.
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ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestothefollowing:
•Entiredesign
•Singlemodulesorentities
•Primaryclocksignal
PropagationRules
SeeMoveFirstStage(MOVE_FIRST_STAGE).
Syntax
-move_last_stage{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributemove_last_stage:string;
Specifyasfollows:
attributemove_last_stageof{entity_name|signal_name}:{signal|entity}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*move_last_stage="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"move_last_stage={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"primary_clock_signal"move_last_stage={yes|no|true|false};
END;
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XSTCommandLine
xstrun-move_last_stage{yes|no}
ISE®DesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>MoveLastStage
MultiplierStyle(MULT_STYLE)
TheMultiplierStyle(MULT_STYLE)constraintcontrolsthewaythemacrogenerator
implementsthemultipliermacros.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-mult_style{auto|block|kcm|csd|lut|pipe_lut}
•auto(default)
InstructsXSTtolookforthebestimplementationforeachconsideredmacro.
•block
•pipe_block
–UsedtopipelineDSP48basedmultipliers.
–Availableforthefollowingdevicesonly:
♦Virtex®-4
♦Virtex-5
♦Spartan®-3ADSP
•kcm
•csd
•lut
•pipe_lut
Forpipelineslice-basedmultipliersonly.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
Frontmatter
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attributemult_style:string;
Specifyasfollows:
attributemult_styleof{signal_name|entity_name}:{signal|entity}is
"{auto|block|pipe_block|kcm|csd|lut|pipe_lut}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*mult_style="{auto|block|pipe_block|kcm|csd|lut|pipe_lut}"*)
XCFSyntaxExampleOne
MODEL"entity_name"mult_style={auto|block|pipe_block|kcm|csd|lut|pipe_lut};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name”
NET"signal_name"mult_style={auto|block|pipe_block|kcm|csd|lut|pipe_lut};
END;
XSTCommandLine
xstrun-mult_style{auto|block|kcm|csd|lut|pipe_lut}
The-mult_stylecommandlineoptionisnotsupportedforthefollowingdevices:
•Virtex-4
•Virtex-5
•Spartan-3A
Forthosedevices,use:
-use_dsp48
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>MultiplierStyle
MuxStyle(MUX_STYLE)
TheMuxStyle(MUX_STYLE)constraintcontrolsthewaythemacrogenerator
implementsthemultiplexermacros.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
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AvailableDevices
DevicesResources
Spartan®-3
Spartan-3E
Spartan-3A
Spartan-3ADSP
Virtex®-4
Virtex-5
MUXF
MUXF6
MUXCY
MUXF7
MUXF8
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
mux_style{auto|muxf|muxcy}
•auto(default)
XSTlooksforthebestimplementationforeachconsideredmacro.
•muxf
•muxcy
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributemux_style:string;
Specifyasfollows:
attributemux_styleof{signal_name|entity_name}:{signal|entity}is
"{auto|muxf|muxcy}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*mux_style="{auto|muxf|muxcy}"*)
XCFSyntaxExampleOne
MODEL"entity_name"mux_style={auto|muxf|muxcy};
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XCFSyntaxExampleTwo
BEGINMODEL"entity_name”
NET"signal_name"mux_style={auto|muxf|muxcy};
END;
XSTCommandLine
xstrun-mux_style{auto|muxf|muxcy}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>MuxStyle
NumberofGlobalClockBuffers(-bufg)
TheNumberofGlobalClockBuffers(-bufg)commandlineoptioncontrolsthe
maximumnumberofBUFGcomponentscreatedbyXST.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-bufginteger
Thevalueisaninteger.Thedefaultvaluedependsonthetargetdevice,andisequal
tothemaximumnumberofavailableBUFGcomponents.Defaultsforselected
architecturesareshownbelow.
DevicesDefaultValue
Virtex®-4
Virtex-5
32
Spartan®-38
Spartan-3E
Spartan-3A
Spartan-3ADSP
24
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
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XSTCommandLine
xstrun-bufg8
Setsthenumberofglobalclockbuffersto8.
ISE®DesignSuite
TosetthenumberofglobalclockbuffersinISEDesignSuite:
1.SelectProcess>ProcessProperties>Xilinx®-SpecicOptions.
2.FromthePropertydisplaylevellist,selectAdvanced
3.SettheNumberofClockBuffersproperty.
NumberofRegionalClockBuffers(-bufr)
TheNumberofRegionalClockBuffers(-bufr)commandlineoptioncontrolsthe
maximumnumberofBUFRscreatedbyXST.
ArchitectureSupport
•MaybeusedwithVirtex®-4devicesonly .
•MayNOTbeusedwithVirtex-5devices.
•MayNOTbeusedwithSpartan®-3devices.
•MayNOTbeusedwithCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-bufrinteger
Thevalueisaninteger.Thedefaultvaluedependsonthetargetdevice,andisequalto
themaximumnumberofavailableBUFRs.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-bufr66
Setsthenumberofregionalclockbuffersto6.
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ISE®DesignSuite
TosetthenumberofregionalclockbuffersinISEDesignSuite:
1.SelectProcess>ProcessProperties>Xilinx®-SpecicOptions
2.FromthePropertydisplaylevellist,selectAdvanced
3.SettheNumberofRegionalClockBuffersproperty .
OptimizeInstantiatedPrimitives(OPTIMIZE_PRIMITIVES)
TheOptimizeInstantiatedPrimitives(OPTIMIZE_PRIMITIVES)constraint:
•SwitchesoffthedefaultbywhichXSTdoesnotoptimizeinstantiatedprimitivesin
HardwareDescriptionLanguage(HDL)designs.
•AllowsXSTtooptimizeXilinx®libraryprimitivesthathavebeeninstantiatedinan
HDLdesign.
Optimizationofinstantiatedprimitivesislimitedbythefollowingfactors:
•IfaninstantiatedprimitivehasspecicconstraintssuchasRLOCattached,XST
preservesitasis.
•NotallprimitivesareconsideredbyXSTforoptimization.Suchhardwareelements
asthefollowingarenotoptimized(modied)evenifoptimizationofinstantiated
primitivesisenabled:
–MULT18x18
–BRAM
–DSP48
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestohierarchicalblocks,components,andinstances.
PropagationRules
Appliestothecomponentorinstancetowhichitisattached.
Syntax
•yes
•no(default)
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
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SchematicSyntaxExamples
•Attachtoavalidinstance
•AttributeName
OPTIMIZE_PRIMITIVES
•AttributeValues
SeeSyntaxsectionabove.
VHDL
Declareasfollows:
attributeoptimize_primitives:string;
Specifyasfollows:
attributeoptimize_primitivesof{component_name|entity_name|label_name}:
{component|entity|label}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*optimize_primitives="{yes|no}"*)
XCF
MODEL"entity_name"optimize_primitives={yes|no|true|false};
ISE®DesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>OptimizeInstantiated
Primitives
PackI/ORegistersIntoIOBs(IOB)
ThePackI/ORegistersIntoIOBs(IOB)constraintpacksip-opsintheI/Ostoimprove
input/outputpathtiming.
WhenIOBissettoauto,theactionXSTtakesdependsontheOptimizationsetting:
•IfOptimizationissettoarea,XSTpacksregistersastightlyaspossibletotheIOBsin
ordertoreducethenumberofslicesoccupiedbythedesign.
•IfOptimizationissettospeed,XSTpacksregisterstotheIOBsprovidedtheyare
notcoveredbytimingconstraints(inotherwords,theyarenottakenintoaccount
bytimingoptimization).Forexample,ifyouspecifyaperiodconstraint,XSTpacks
aregistertotheIOBifitisnotcoveredbytheperiodconstraint.Ifaregisteris
coveredbytimingoptimization,butyoudowanttopackittoanIOB,youmust
applytheIOBconstraintlocallytotheregister.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
PowerReduction(POWER)
ThePowerReduction(POWER)constraintinstructsXSTtooptimizethedesignto
consumeaslittlepoweraspossible.
Macroprocessingdecisionsaremadetoimplementfunctionsinamannerthanuses
minimalpower.AlthoughPOWERisallowedinbothAREAandSPEEDmodes,itmay
negativelyimpactthenaloverallareaandspeedofthedesign.
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Chapter9:XSTFPGAConstraints(Non-Timing)
Inthecurrentrelease,poweroptimizationdonebyXSTisdedicatedtoDSP48and
BRAMblocks.
XSTsupportstwoBRAMoptimizationmethods:
•MethodOnedoesnotsignicantlyimpactareaandspeed.MethodOneisusedby
defaultwhenpoweroptimizationisenabled.
•MethodTwosavesmorepower,butmaysignicantlyimpactareaandspeed.
BothmethodscanbecontrolledbyusingtheRAMStyle(RAM_STYLE)constraintwith
block_power1forMethodOneandblock_power2forMethodTwo.
Insomesituations,XSTmayissueanHDLAdvisormessagegivingyoutipsonhow
toimproveyourdesign.Forexample,ifXSTdetectsthatReadFirstmodeisusedfor
BRAM,XSTrecommendsthatyouuseWriteFirstorNoChangemodes.
ArchitectureSupport
AppliestoVirtex®-4devicesandVirtex-5devicesonly.Doesnotapplytoanyother
FPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliesto:
•Acomponentorentity(VHDL)
•Amodelorlabel(instance)(Verilog)
•AmodelorINST(inmodel)(XCF)
•Theentiredesign(XSTcommandline)
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-power{yes|no}
•yes
•no(default)
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributepower:string;
Specifyasfollows:
attributepowerof{component_name|entity_name}:{component_name|entity_name}is
"{yes|no}";
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Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*power="{yes|no}"*)
XCF
MODEL"entity_name"power={yes|no|true|false};
Thedefaultisfalse.
XSTCommandLine
xstrun-power{yes|no}
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>PowerReduction
PriorityEncoderExtraction(PRIORITY_EXTRACT)
ThePriorityEncoderExtraction(PRIORITY_EXTRACT)constraintenablesordisables
priorityencodermacroinference.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
•yes(default)
•no
•force
•true(XCFonly)
•false(XCFonly)
Foreachidentiedpriorityencoderdescription,basedoninternaldecisionrules,XST
createsamacrooroptimizesitwiththerestofthelogic.Theforcevalueallowsyouto
overridethoseinternaldecisionrulesandforceXSTtoextractthemacro.
-priority_extract{yes|no|force}
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
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VHDL
Declareasfollows:
attributepriority_extract:string;
Specifyasfollows:
attributepriority_extractof{signal_name|entity_name}:{signal|entity}is
"{yes|no|force}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*priority_extract="{yes|no|force}"*)
XCFSyntaxExampleOne
MODEL"entity_name"priority_extract={yes|no|true|false|force};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"priority_extract={yes|no|true|false|force};
END;
XSTCommandLine
xstrun-priority_extract{yes|no|force}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>PriorityEncoderExtraction
RAMExtraction(RAM_EXTRACT)
TheRAMExtraction(RAM_EXTRACT)constraintenablesordisablesRAMmacro
inference.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
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Syntax
-ram_extract{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeram_extract:string;
Specifyasfollows:
attributeram_extractof{signal_name|entity_name}:{signal|entity}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*ram_extract="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"ram_extract={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"ram_extract={yes|no|true|false};
END;
XSTCommandLine
xstrun-ram_extract{yes|no}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>RAMExtraction
RAMStyle(RAM_STYLE)
TheRAMStyle(RAM_STYLE)constraintcontrolsthewaythemacrogenerator
implementstheinferredRAMmacros.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
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ThefollowingaresupportedforVirtex®-4devicesandVirtex-5devicesonly:
•block_power1
•block_power2
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
ram_style{auto|block|distributed}
•auto(default)
•block
•distributed
•pipe_distributed
•block_power1
•block_power2
XSTlooksforthebestimplementationforeachinferredRAM.
Youmustuseblock_power1andblock_power2inordertoachievepower-oriented
BRAMoptimization.
Formoreinformation,see:
PowerReduction(POWER)
TheimplementationstylecanbemanuallyforcedtouseblockRAMordistributed
RAMresources.
YoucanspecifythefollowingonlythroughVHDL,Verilog,orXCFconstraints:
•pipe_distributed
•block_power1
•block_power2
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeram_style:string;
Specifyasfollows:
attributeram_styleof{signal_name|entity_name}:{signal|entity}is
"{auto|block|distributed|pipe_distributed|block_power1|block_power2}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
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(*ram_style=
"{auto|block|distributed|pipe_distributed|block_power1|block_power2}"*)
XCFSyntaxExampleOne
MODEL"entity_name"
ram_style={auto|block|distributed|pipe_distributed|block_power1|block_power2};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"
ram_style={auto|block|distributed|pipe_distributed|block_power1|block_power2};
END;
XSTCommandLine
xstrun-ram_style{auto|block|distributed}
Thepipe_distributedvalueisnotaccessiblethroughthecommandline.
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>RAMStyle
ReadCores(READ_CORES)
TheReadCores(READ_CORES)constraintenablesordisablestheabilityofXSTto
readElectronicDataInterchangeFormat(EDIF)orNGCcorelesfortimingestimation
anddeviceutilizationcontrol.
Byreadingaspeciccore,XSTisbetterabletooptimizelogicaroundthecore,sinceit
seeshowthelogicisconnected.However,insomecasestheReadCoresoperationmust
bedisabledinXSTinordertoobtainthedesiredresults.Forexample,thePCI™core
mustnotbevisibletoXST,sincethelogicdirectlyconnectedtothePCIcoremustbe
optimizeddifferentlyascomparedtoothercores.ReadCoresallowsyoutoenableor
disablereadoperationsonacorebycorebasis.
Formoreinformation,see:
CoresProcessing
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
SincethisconstraintcanbeusedwithBoxType(BOX_TYPE)thesetofobjectsonwhich
thebothconstraintscanbeappliedmustbethesame.
ApplyReadCoresto:
•Acomponentorentity(VHDL)
•Amodelorlabel(instance)(Verilog)
•AmodelorINST(inmodel)(XCF)
•Theentiredesign(XSTcommandline)
IfReadCoresisappliedtoatleastasingleinstanceofablock,thenReadCoresisapplied
toallotherinstancesofthisblockfortheentiredesign.
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PropagationRules
Notapplicable.
Syntax
-read_cores{yes|no|optimize}
•no(false)
Disablescoresprocessing
•yes(true)(default)
Enablescoresprocessing,butmaintainsthecoreasablackboxanddoesnotfurther
incorporatethecoreintothedesign
•optimize
Enablescoresprocessing,andmergesthecoresnetlistintotheoveralldesign.This
valueisavailablethroughtheXSTcommandlinemodeonly.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeread_cores:string;
Specifyasfollows:
attributeread_coresof{component_name|entity_name}:{component|entity}is
"{yes|no|optimize}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*read_cores="{yes|no|optimize}"*)
XCFSyntaxExampleOne
MODEL"entity_name"read_cores={yes|no|true|false|optimize};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"END;
INST"instance_name"read_cores={yes|no|true|false|optimize};
END;
XSTCommandLine
xstrun-read_cores{yes|no|optimize}
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>ReadCores
NoteTheoptimizeoptionisnotavailableinISEDesignSuite.
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ReduceControlSets(REDUCE_CONTROL_SETS)
TheReduceControlSets(REDUCE_CONTROL_SETS)constraintallowsyoutoreduce
thenumberofcontrolsetsand,asaconsequence,reducethedesignarea.
Reducingthenumberofcontrolsetsshould:
•Improvethepackingprocessinmap.
•ReducethenumberofusedslicesevenifthenumberofLUTsisincreased.
ArchitectureSupport
AppliestoVirtex®-5devicesonly.Doesnotapplytoanyotherdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-reduce_control_sets{auto|no}
•auto
XSToptimizesautomatically ,andreducestheexistingcontrolsetsinthedesign.
•no(default)
XSTperformsnocontrolsetoptimization.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-reduce_control_sets{auto|no}
ISE®DesignSuite
Process>ProcessProperties>XilinxSpecicOptions>ReduceControlSets
RegisterBalancing(REGISTER_BALANCING)
TheRegisterBalancing(REGISTER_BALANCING)constraintenablesip-op
retiming.
Themaingoalofregisterbalancingistomoveip-opsandlatchesacrosslogicto
increaseclockfrequency.
ThetwocategoriesofREGISTER_BALANCINGare:
•ForwardRegisterBalancing
•BackwardRegisterBalancing
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ForwardRegisterBalancing
ForwardRegisterBalancingmovesasetofip-opsattheinputsofaLUTtoasingle
ip-opatitsoutput.
Whenreplacingseveralip-opswithone,selectthenamebasedonthenameofthe
LUTacrosswhichtheip-opsaremovingasshowninthefollowing:
LutName_FRBId
BackwardRegisterBalancing
BackwardRegisterBalancingmovesaip-opattheoutputofaLUTtoasetof
ip-opsatitsinputs.
Asaconsequencethenumberofip-opsinthedesigncanbeincreasedordecreased.
Thenewip-ophasthesamenameastheoriginalip-opwithanindexedsufxas
showninthefollowing:
OriginalFFName_BRBId
AdditionalConstraintsThatImpactRegisterBalancing
Twoadditionalconstraintscontrolregisterbalancing:
•MoveFirstStage(MOVE_FIRST_STAGE)
•MoveLastStage(MOVE_LAST_STAGE)
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Severalotherconstraintsalsoinuenceregisterbalancing:
•KeepHierarchy(KEEP_HIERARCHY)
–Ifthehierarchyispreserved,ip-opsaremovedonlyinsidetheblock
boundaries.
–Ifthehierarchyisattened,ip-opsmayleavetheblockboundaries.
•PackI/ORegistersIntoIOBs(IOB)
IfIOB=TRUE,registerbalancingisnotappliedtotheip-opshavingthisproperty.
•OptimizeInstantiatedPrimitives(OPTIMIZE_PRIMITIVES)
Instantiatedip-opsaremovedonlyifOPTIMIZE_PRIMITIVES=YES.
•Flip-opsaremovedacrossinstantiatedprimitivesonlyif
OPTIMIZE_PRIMITIVES=YES.
•Keep(KEEP)
Ifappliedtotheoutputip-opsignal,theip-opisnotmovedforward.
AppliedtotheInputFlip-FlopSignal
Ifappliedtotheinputip-opsignal,theip-opisnotmovedbackward.
Ifappliedtoboththeinputandoutputoftheip-op,itisequivalentto
REGISTER_BALANCING=no
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliesto:
•TheentiredesignusingthecommandlineorISE®DesignSuite
•Anentityormodule
•Asignalcorrespondingtotheip-opdescription(RTL)
•Aip-opinstance
•ThePrimaryClockSignal
Inthiscasetheregisterbalancingisperformedonlyforip-opssynchronized
bythisclock.
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Chapter9:XSTFPGAConstraints(Non-Timing)
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-register_balancing{yes|no|forward|backward}
•yes
Bothforwardandbackwardretimingareallowed.
•no(default)
Neitherforwardnorbackwardretimingisallowed.
•forward
Onlyforwardretimingisallowed
•backward
Onlybackwardretimingisallowed.
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeregister_balancing:string;
Specifyasfollows:
attributeregister_balancingof{signal_name|entity_name}:{signal|entity}is
"{yes|no|forward|backward}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*register_balancing="{yes|no|forward|backward}"*)
XCFSyntaxExampleOne
MODEL"entity_name"register_balancing={yes|no|true|false|forward|backward};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"primary_clock_signal"
register_balancing={yes|no|true|false|forward|backward};"
END;
XCFExampleThree
BEGINMODEL"entity_name”
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Chapter9:XSTFPGAConstraints(Non-Timing)
INST"instance_name"register_balancing={yes|no|true|false|forward|backward};
END;
XSTCommandLine
xstrun-register_balancing{yes|no|forward|backward}
ISEDesignSuite
Process>ProcessProperties>XilinxSpecicOptions>RegisterBalancing
RegisterDuplication(REGISTER_DUPLICATION)
TheRegisterDuplication(REGISTER_DUPLICATION)constraint:
•Enablesordisablesregisterreplication.
•Isenabled,andisperformedduringtimingoptimizationandfanoutcontrol.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentityormoduletowhichitisattached.
Syntax
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeregister_duplication:string;
Specifyasfollows:
attributeregister_duplicationofentity_name:entityis"{yes|no}";
Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
Frontmatter
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(*register_duplication="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"register_duplication={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"register_duplication={yes|no|true|false};
END;
ISE®DesignSuite
Process>ProcessProperties>XilinxSpecicOptions>RegisterDuplication
ROMExtraction(ROM_EXTRACT)
TheROMExtraction(ROM_EXTRACT)constraintenablesordisablesROMmacro
inference.
Typically,aROMcanbeinferredfromacasestatementwhereallassignedcontexts
areconstantvalues.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoadesignelementorsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-rom_extract{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
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attributerom_extract:string;
Specifyasfollows:
attributerom_extractof{signal_name|entity_name}:{signal|entity}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*rom_extract="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"rom_extract={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"rom_extract={yes|no|true|false};
END;
XSTCommandLine
xstrun-rom_extract{yes|no}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>ROMExtraction
ROMStyle(ROM_STYLE)
TheROMStyle(ROM_STYLE)constraintcontrolsthewaythemacrogenerator
implementstheinferredROMmacros.
Caution!ROMExtraction(ROM_EXTRACT)mustbesettoyesinordertouseROM
Style(ROM_STYLE).
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
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Syntax
-rom_style{auto|block|distributed}
•auto(default)
XSTlooksforthebestimplementationforeachinferredROM.Theimplementation
stylecanbemanuallyforcedtouseblockROMordistributedROMresources.
•block
•distributed
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributerom_style:string;
Specifyasfollows:
attributerom_styleof{signal_name|entity_name}:{signal|entity}is
"{auto|block|distributed}";
Verilog
Declareasfollows:
(*rom_style="{auto|block|distributed}"*)
XCFSyntaxExampleOne
MODEL"entity_name"rom_style={auto|block|distributed};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"rom_style={auto|block|distributed};
END;
XSTCommandLine
xstrun-rom_style{auto|block|distributed}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>ROMStyle
ShiftRegisterExtraction(SHREG_EXTRACT)
TheShiftRegisterExtraction(SHREG_EXTRACT)constraint:
•Enablesordisablesshiftregistermacroinference.
•ResultsintheusageofdedicatedhardwareresourcessuchasSRL16andSRLC16.
Formoreinformation,see:
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Chapter9:XSTFPGAConstraints(Non-Timing)
ShiftRegistersHDLCodingTechniques
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoadesignelementorsignal.
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-shreg_extract{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeshreg_extract:string;
Specifyasfollows:
attributeshreg_extractof{signal_name|entity_name}:{signal|entity}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*shreg_extract="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"shreg_extract={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"shreg_extract={yes|no|true|false};
END;
XSTCommandLine
xstrun-shreg_extract{yes|no}
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ISE®DesignSuite
Process>ProcessProperties>HDLOptions>ShiftRegisterExtraction
Slice(LUT-FFPairs)UtilizationRatio(SLICE_UTILIZATION_RATIO)
TheSlice(LUT-FFPairs)UtilizationRatio(SLICE_UTILIZATION_RATIO)constraint
denestheareasizeinabsolutenumbersorpercentoftotalnumbersofthefollowing
componentsthatXSTmustnotexceedduringtimingoptimization:
•LUT-FFpairs(Virtex®-5devices)
•slices(allotherdevices)
Iftheareaconstraintcannotbesatised,XSTmakestimingoptimizationregardless
oftheareaconstraint.Todisableautomaticresourcemanagement,specify-1asa
constraintvalue.
Formoreinformation,see:
SpeedOptimizationUnderAreaConstraint
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentityormoduletowhichitisattached.
Syntax
Thefollowingsectionsshowthesyntaxforthisconstraint.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeslice_utilization_ratio:string;
Specifyasfollows:
attributeslice_utilization_ratioofentity_name:entityis"integer";
attributeslice_utilization_ratioofentity_name:entityis"integer%";
attributeslice_utilization_ratioofentity_name:entityis"integer#";
XSTinterpretstheintegervaluesinthersttwoexamplesaboveasapercentageandin
thelastexampleasanabsolutenumberofslicesorFF-LUTpairs.
Theintegervaluerangeis0to100whenpercent(%)isusedorbothpercent(%)and
pound(#)areomitted.
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Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*slice_utilization_ratio="integer"*)
(*slice_utilization_ratio="integer%"*)
(*slice_utilization_ratio="integer#"*)
XSTinterpretstheintegervaluesinthersttwoexamplesaboveasapercentageandin
thelastexampleasanabsolutenumberofslicesorFF-LUTpairs.
Theintegervaluerangeis0to100whenpercent(%)isusedorbothpercent(%)and
pound(#)areomitted.
XCF
MODEL"entity_name"slice_utilization_ratio=integer;
MODEL"entity_name"slice_utilization_ratio=integer%;
MODEL"entity_name"slice_utilization_ratio=integer#;
XSTinterpretstheintegervaluesinthersttwoexamplesaboveasapercentageandin
thelastexampleasanabsolutenumberofslicesorFF-LUTpairs.
Theintegervaluerangeis0to100whenpercent(%)isusedorbothpercent(%)and
pound(#)areomitted.
Theremustbenospacebetweentheintegervalueandthepercent(%)orpound(#)
characters.
Youmustsurroundtheintegervalueandthepercent(%)andpound(#)characters
withdoublequotes("...")becausethepercent(%)andpound(#)charactersarespecial
charactersintheXSTConstraintFile(XCF).
XSTCommandLine
xstrun-slice_utilization_ratiointeger
xstrun-slice_utilization_ratiointeger%
xstrun-slice_utilization_ratiointeger#
XSTinterpretstheintegervaluesinthersttwoexamplesaboveasapercentageandin
thelastexampleasanabsolutenumberofslicesorFF-LUTpairs.
Theintegervaluerangeis0to100whenpercent(%)isusedorbothpercent(%)and
pound(#)areomitted.
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>SliceUtilizationRatioorProcess>
ProcessProperties>SynthesisOptions>LUT-FFPairsUtilizationRatio
InISEDesignSuite,youcandenethevalueofSlice(LUT-FFPairs)UtilizationRatio
onlyasapercentage.Youcannotdenethevalueasanabsolutenumberofslices.
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Slice(LUT-FFPairs)UtilizationRatioDelta
(SLICE_UTILIZATION_RATIO_MAXMARGIN)
TheSlice(LUT-FFPairs)UtilizationRatioDelta
(SLICE_UTILIZATION_RATIO_MAXMARGIN)constraint:
•IscloselyrelatedtoSlice(LUT-FFPairs)UtilizationRatio
(SLICE_UTILIZATION_RATIO).
•DenesthetolerancemarginforSlice(LUT-FFPairs)UtilizationRatio
(SLICE_UTILIZATION_RATIO).
Thevalueoftheparametercanbedenedintheformofpercentageaswellasanabsolute
numberofslicesorLUT-FFpairs.
Iftheratioiswithinthemarginset,theconstraintismetandtimingoptimizationcan
continue.
Formoreinformation,see:
SpeedOptimizationUnderAreaConstraint
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortoanentity,component,module,orsignal.
PropagationRules
Appliestotheentityormoduletowhichitisattached.
Syntax
Thefollowingsectionsshowthesyntaxforthisconstraint.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeslice_utilization_ratio_maxmargin:string;
Specifyasfollows:
attributeslice_utilization_ratio_maxmarginofentity_name:entityis"integer";
attributeslice_utilization_ratio_maxmarginofentity_name:entityis"integer%";
attributeslice_utilization_ratio_maxmarginofentity_name:entityis"integer#";
XSTinterpretstheintegervaluesinthersttwoexamplesaboveasapercentageandin
thelastexampleasanabsolutenumberofslicesorFF-LUTpairs.
Theintegervaluerangeis0to100whenpercent(%)isusedorbothpercent(%)and
pound(#)areomitted.
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Verilog
Placeimmediatelybeforethemoduledeclarationorinstantiation:
(*slice_utilization_ratio_maxmargin="integer"*)
(*slice_utilization_ratio_maxmargin="integer%"*)
(*slice_utilization_ratio_maxmargin="integer#"*)
XSTinterpretstheintegervaluesinthersttwoexamplesaboveasapercentageandin
thelastexampleasanabsolutenumberofslicesorFF-LUTpairs.
Theintegervaluerangeis0to100whenpercent(%)isusedorbothpercent(%)and
pound(#)areomitted.
XCF
MODEL"entity_name"slice_utilization_ratio_maxmargin=integer;
MODEL"entity_name"slice_utilization_ratio_maxmargin="integer%";
MODEL"entity_name"slice_utilization_ratio_maxmargin="integer#";
XSTinterpretstheintegervaluesinthersttwoexamplesaboveasapercentageandin
thelastexampleasanabsolutenumberofslicesorFF-LUTpairs.
Theintegervaluerangeis0to100whenpercent(%)isusedorbothpercent(%)and
pound(#)areomitted.
Theremustbenospacebetweentheintegervalueandthepercent(%)orpound(#)
characters.
Youmustsurroundtheintegervalueandthepercent(%)andpound(#)characters
withdoublequotes("...")becausethepercent(%)andpound(#)charactersarespecial
charactersintheXSTConstraintFile(XCF).
XSTCommandLine
xstrun-slice_utilization_ratio_maxmargininteger
xstrun-slice_utilization_ratio_maxmargininteger%
xstrun-slice_utilization_ratio_maxmargininteger#
XSTinterpretstheintegervaluesinthersttwoexamplesaboveasapercentageandin
thelastexampleasanabsolutenumberofslicesorFF-LUTpairs.
Theintegervaluerangeis0to100whenpercent(%)isusedorbothpercent(%)and
pound(#)areomitted.
SlicePacking(-slice_packing)
TheSlicePacking(-slice_packing)commandlineoptionenablestheXSTinternalpacker.
ThepackerattemptstopackcriticalLUT-to-LUTconnectionswithinasliceoraCLB.
ThisexploitsthefastfeedbackconnectionsamongtheLUTsinaCLB.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
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PropagationRules
Notapplicable.
Syntax
-slice_packing{yes|no}
•yes
•no
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-slice_packingno
DisablestheXSTinternalslicepacker.
ISE®DesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>SlicePacking
UseLowSkewLines(USELOWSKEWLINES)
TheUseLowSkewLines(USELOWSKEWLINES)constraint:
•Isabasicroutingconstraint.
•PreventsXSTfromusingdedicatedclockresourcesandlogicreplicationduring
synthesis,basedonthevalueoftheMaxFanout(MAX_FANOUT)constraint.
•Speciestheuseoflowskewroutingresourcesforanynet.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
UseCarryChain(USE_CARRY_CHAIN)
TheUseCarryChain(USE_CARRY_CHAIN)constraint:
•Isbothaglobalandalocalconstraint
•Candeactivatecarrychainuseformacrogeneration
XSTusescarrychainresourcestoimplementcertainmacros,buttherearesituations
whereyoucanobtainbetterresultsbynotusingcarrychain.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign,ortosignals.
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PropagationRules
Appliestothesignaltowhichitisattached.
Syntax
-use_carry_chain{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
Schematic
•Attachtoavalidinstance
•AttributeName
USE_CARRY_CHAIN
•AttributeValues
SeeSyntaxsectionabove.
VHDL
Declareasfollows:
attributeuse_carry_chain:string;
Specifyasfollows:
attributeuse_carry_chainofsignal_name:signalis"{yes|no}";
Verilog
Placeimmediatelybeforethesignaldeclaration:
(*use_carry_chain="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"use_carry_chain={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"use_carry_chain={yes|no|true|false};
END;
XSTCommandLine
xstrun-use_carry_chain{yes|no}
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UseClockEnable(USE_CLOCK_ENABLE)
TheUseClockEnable(USE_CLOCK_ENABLE)constraintenablesordisablestheclock
enablefunctioninip-ops.
ThedisablingoftheclockenablefunctionistypicallyusedforASICprototypingon
FPGAdevices.
BydetectingUseClockEnablewithavalueofnoorfalse,XSTavoidsusingCE
resourcesinthenalimplementation.Moreover,forsomedesigns,puttingtheClock
Enablefunctiononthedatainputoftheip-opallowsbetterlogicoptimizationand
thereforebetterqualityofresults.
Inautomode,XSTtriestoestimateatradeoffbetweenusingadedicatedclockenable
inputofaip-opinputandputtingclockenablelogicontheDinputofaip-op.Ina
casewhereaip-opisinstantiatedbyyou,XSTremovestheclockenableonlyifthe
OptimizeInstantiatedPrimitivesoptionissettoyes.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliesto:
•AnentiredesignthroughtheXSTcommandline
•Aparticularblock(entity ,architecture,component)
•Asignalrepresentingaip-op
•Aninstancerepresentinganinstantiatedip-op
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-use_clock_enable{auto|yes|no}
•auto(default)
•yes
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeuse_clock_enable:string;
Specifyasfollows:
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attributeuse_clock_enableof{entity_name|component_name|signal_name|instance_name}
:{entity|component|signal|label}is"{auto|yes|no}";
Verilog
Placeimmediatelybeforetheinstance,module,orsignaldeclaration:
(*use_clock_enable="{auto|yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"use_clock_enable={auto|yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"use_clock_enable={auto|yes|no|true|false};
END
XCFSyntaxExampleThree
BEGINMODEL"entity_name;"
INST"instance_name"use_clock_enable={auto|yes|no|true|false};
END
XSTCommandLine
xstrun-use_clock_enable{auto|yes|no}
ISE®DesignSuite
Process>ProcessProperties>XilinxSpecicOptions>UseClockEnable
USE_DSP48(UseDSP48)
Thisconstraintiscalled:
•UseDSP48
Virtex®-4devices
•UseDSPBlock
Virtex-5devicesandSpartan®-3ADSPdevices
XSTenablesyoutousetheresourcesoftheDSP48blocksintroducedinVirtex-4devices.
Inautomode,XSTautomaticallyimplementssuchmacrosasMACandaccumulateson
DSP48,butsomeofthemasaddersareimplementedonslices.Youhavetoforcetheir
implementationonDSP48usingavalueofyesortrue.
Formoreinformationonsupportedmacrosandtheirimplementationcontrol,see:
XSTHDLCodingTechniques
Severalmacros(forexample,MAC)thatcanbeplacedonDSP48areinfacta
compositionofsimplermacrossuchasmultipliers,accumulators,andregisters.To
achievethebestperformance,XSTbydefaulttriestoinferandimplementthemaximum
macroconguration.Toshapeamacroinaspecicway,usetheKeep(KEEP)constraint.
Forexample,DSP48allowsyoutoimplementamultiplewithtwoinputregisters.To
leavetherstregisterstageoutsideoftheDSP48,placetheKeep(KEEP)constraintin
theiroutputs.
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Chapter9:XSTFPGAConstraints(Non-Timing)
ArchitectureSupport
Appliestothefollowingdevicesonly.Doesnotapplytoanyotherdevices.
•Spartan-3ADSP
•Virtex-4
•Virtex-5
ApplicableElements
Appliesto:
•AnentiredesignthroughtheXSTcommandline
•Aparticularblock(entity ,architecture,component)
•AsignalrepresentingamacrodescribedattheRTLlevel
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-use_dsp48{auto|yes|no}
•auto(default)
•yes
•no
•true(XCFonly)
•false(XCFonly)
InautomodeyoucancontrolthenumberofavailableDSP48resourcesforsynthesis
usingDSPUtilizationRatio(DSP_UTILIZATION_RATIO).Bydefault,XSTtriesto
utilize,asmuchaspossible,allavailableDSP48resources.
Formoreinformation,see:
DSP48BlockResources
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeuse_dsp48:string;
Specifyasfollows:
attributeuse_dsp48of{"entity_name|component_name|signal_name"}:
{entity|component|signal}is"{auto|yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*use_dsp48="{auto|yes|no}"*)
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XCFSyntaxExampleOne
MODEL"entity_name"use_dsp48={auto|yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name”
NET"signal_name"use_dsp48={auto|yes|no|true|false};
END;"
XSTCommandLine
xstrun-use_dsp48{auto|yes|no}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>UseDSP48
UseSynchronousSet(USE_SYNC_SET)
TheUseSynchronousSet(USE_SYNC_SET)constraintenablesordisablesthe
synchronoussetfunctioninip-ops.
DisablingthesynchronoussetfunctionistypicallyusedforASICprototypingonFPGA
devices.WhenXSTdetectsUseSynchronousSetwithavalueofnoorfalse,XSTavoids
usingsynchronousresetresourcesinthenalimplementation.Forsomedesigns,
puttingsynchronousresetfunctionondatainputoftheip-opallowsbetterlogic
optimizationandthereforegivesbetterqualityofresults.
Inautomode,XSTtriestoestimateatradeoffbetweenusingdedicatedSynchronousSet
inputofaip-opinputandputtingSynchronousSetlogicontheDinputofaip-op.
Whenaip-opisinstantiatedbythedesigner,XSTremovesthesynchronousresetonly
ifOptimizeInstantiatedPrimitivesissettoyes.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliesto:
•AnentiredesignthroughtheXSTcommandline
•Aparticularblock(entity ,architecture,component)
•Asignalrepresentingaip-op
•Aninstancerepresentinganinstantiatedip-op
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
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Syntax
-use_sync_set{auto|yes|no}
•auto(default)
•yes
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeuse_sync_set:string;
Specifyasfollows:
attributeuse_sync_setof{entity_name|component_name|signal_name|instance_name}:
{entity|component|signal|label}is"{auto|yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*use_sync_set="{auto|yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"use_sync_set={auto|yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"use_sync_set={auto|yes|no|true|false};
END;
XCFSyntaxExampleThree
BEGINMODEL"entity_name"
INST"instance_name"use_sync_set={auto|yes|no|true|false};
END;
XSTCommandLine
xstrun-use_sync_set{auto|yes|no}
ISE®DesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>UseSynchronousSet
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Chapter9:XSTFPGAConstraints(Non-Timing)
UseSynchronousReset(USE_SYNC_RESET)
TheUseSynchronousReset(USE_SYNC_RESET)constraintenablesordisablesthe
usageofsynchronousresetfunctionofip-ops.
DisablingsynchronousresetcanbeusedforASICprototypingowonFPGAdevices.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliesto:
•AnentiredesignthroughtheXSTcommandline
•Aparticularblock(entity ,architecture,component)
•Asignalrepresentingaip-op
•Aninstancerepresentinganinstantiatedip-op
PropagationRules
Appliestotheentity,component,module,orsignaltowhichitisattached.
Syntax
-use_sync_reset{auto|yes|no}
•auto(default)
•yes
•no
•true(XCFonly)
•false(XCFonly)
WhenXSTdetectsUseSynchronousResetwithavalueofnoorfalse,XSTavoidsusing
synchronousresetresourcesinthenalimplementation.Forsomedesigns,putting
synchronousresetfunctionondatainputoftheip-opallowsbetterlogicoptimization
andthereforebetterqualityofresults.
Inautomode,XSTtriestoestimateatradeoffbetweenusingadedicatedSynchronous
Resetinputonaip-opinputandputtingSynchronousResetlogicontheDinputofa
ip-op.Whenaip-opisinstantiatedbyadesigner,XSTremovesthesynchronous
resetonlyiftheOptimizeInstantiatedPrimitivesoptionissettoyes.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeuse_sync_reset:string;
Specifyasfollows:
attributeuse_sync_resetof{entity_name|component_name|signal_name|instance_name}
:{entity|component|signal|label}is"{auto|yes|no}";
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Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*use_sync_reset="{auto|yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"use_sync_reset={auto|yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"use_sync_reset={auto|yes|no|true|false};
END;
XCFSyntaxExampleThree
BEGINMODEL"entity_name"
INST"instance_name"use_sync_reset={auto|yes|no|true|false};
END;
XSTCommandLine
xstrun-use_sync_reset{auto|yes|no}
ISE®DesignSuite
Process>ProcessProperties>XilinxSpecicOptions>UseSynchronousReset
XORCollapsing(XOR_COLLAPSE)
TheXORCollapsing(XOR_COLLAPSE)constraintcontrolswhethercascadedXORs
shouldbecollapsedintoasingleXOR.
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
AppliestocascadedXORs.
PropagationRules
Notapplicable.
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Syntax
-xor_collapse{yes|no}
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributexor_collapse:string;
Specifyasfollows:
attributexor_collapse{signal_name|entity_name}:{signal|entity}is"{yes|no}";
Verilog
Placeimmediatelybeforethemoduleorsignaldeclaration:
(*xor_collapse="{yes|no}"*)
XCFSyntaxExampleOne
MODEL"entity_name"xor_collapse={yes|no|true|false};
XCFSyntaxExampleTwo
BEGINMODEL"entity_name"
NET"signal_name"xor_collapse={yes|no|true|false};
END;
XSTCommandLine
xstrun-xor_collapse{yes|no}
ISE®DesignSuite
Process>ProcessProperties>HDLOptions>XORCollapsing
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Chapter10
XSTCPLDConstraints(Non-Timing)
Important!TheconstraintsdescribedinthischapterapplytoCPLDdevicesonly.They
donotapplytoFPGAdevices.
Thischapterdiscussesthefollowingconstraints:
•ClockEnable(-pld_ce)
•DataGate(DATA_GATE)
•MacroPreserve(-pld_mp)
•NoReduce(NOREDUCE)
•WYSIWYG(-wysiwyg)
•XORPreserve(-pld_xp)
ClockEnable(-pld_ce)
TheClockEnable(-pld_ce)commandlineoptionspecieshowsequentiallogicshould
beimplementedwhenitcontainsaclockenable,eitherusingthespecicdevice
resourcesavailablefortheclockenableorgeneratingequivalentlogic.
Keepingornotkeepingtheclockenablesignaldependsonthedesignlogic.When
theclockenableistheresultofaBooleanexpression,settingClockEnabletonomay
improvethettingresult.Theinputdataoftheip-opissimpliedwhenitismerged
withtheclockenableexpression.
ArchitectureSupport
AppliestoallCPLDdevices.DoesnotapplytoFPGAdevices.
ApplicableElements
AppliestoanentiredesignthroughtheXSTcommandline.
PropagationRules
Notapplicable.
Syntax
-pld_ce{yes|no}
•yes(default)
Thesynthesizerimplementstheclockenablesignalofthedevice.
•no
Theclockenablefunctionisimplementedthroughequivalentlogic.
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Chapter10:XSTCPLDConstraints(Non-Timing)
SyntaxExamplesandSettings
xstrun-pld_ceyes
DenesClockEnablegloballytoyes.Theclockenablefunctionisimplementedthrough
equivalentlogic.
ISE®DesignSuite
Process>ProcessProperties>Xilinx-SpecicOptions>ClockEnable
DataGate(DATA_GATE)
TheDataGate(DATA_GATE)constraint:
•AppliestoCoolRunner™-IIdevicesonly.
•Providesadirectmeansofreducingpowerconsumptioninyourdesign.
EachI/Opininputsignalpassesthroughalatchthatcanblockthepropagationof
incidenttransitionsduringperiodswhensuchtransitionsarenotofinteresttoyour
CPLDdesign.
InputtransitionsthatdonotaffecttheCPLDdesignfunctionstillconsumepower,ifnot
latched,sincetheyareroutedamongtheCPLD’sFunctionBlocks.ByassertingtheData
GatecontrolI/Opinonthedevice,selectedI/Opininputsbecomelatched,eliminating
thepowerdissipationassociatedwithexternaltransitionsonthosepins.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
MacroPreserve(-pld_mp)
TheMacroPreserve(-pld_mp)commandlineoption:
•Makesmacrohandlingindependentofdesignhierarchyprocessing.
•Allowsyoutomergeallhierarchicalblocksinthetopmodule,whilestillkeeping
themacrosashierarchicalmodules
Youcankeepthedesignhierarchyexceptforthemacros,whicharemergedwiththe
surroundinglogic.Mergingthemacrossometimesgivesbetterresultsfordesigntting.
ArchitectureSupport
AppliestoallCPLDdevices.DoesnotapplytoFPGAdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
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Syntax
-pld_mp{yes|no}
•yes(default)
MacrosarepreservedandgeneratedbyMacro+.
•no
MacrosarerejectedandgeneratedbyHDLsynthesizer
DependingontheFlattenHierarchyvalue,arejectedmacroiseithermergedinthe
designlogic,orbecomesahierarchicalblockasshowninthefollowingtable.
FlattenHierarchyValueDisposition
yesMergedinthedesignlogic
noBecomesahierarchicalblock
Verysmallmacrossuchas2-bitaddersand4-bitmultiplexersarealwaysmerged,
independentoftheMacroPreserveorFlattenHierarchyoptions.
SyntaxandSettingsExamples
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-pld_mpno
MacrosarerejectedandgeneratedbyHDLsynthesizer.
ISE®DesignSuite
Process>ProcessProperties>Xilinx®-SpecicOptions>MacroPreserve
NoReduce(NOREDUCE)
TheNoReduce(NOREDUCE)constraint:
•Preventsminimizationofredundantlogictermsthataretypicallyincludedina
designtoavoidlogichazardsorraceconditions.
•Identiestheoutputnodeofacombinatorialfeedbacklooptoensurecorrect
mapping.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
WYSIWYG(-wysiwyg)
TheWYSIWYG(-wysiwyg)commandlineoptionmakesanetlistreecttheuser
specicationascloselyaspossible.Thatis,allthenodesdeclaredintheHardware
DescriptionLanguage(HDL)designarepreserved.
IfWYSIWYGmodeisenabled(yes),XST:
•Preservesalluserinternalsignals(nodes)
•CreatesSOURCE_NODEconstraintsintheNGCleforallthesenodes
•Skipsdesignoptimization(collapse,factorization)
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Chapter10:XSTCPLDConstraints(Non-Timing)
OnlyBooleanequationminimizationisperformed.
ArchitectureSupport
AppliestoallCPLDdevices.DoesnotapplytoFPGAdevices.
ApplicableElements
AppliestoanentiredesignthroughtheXSTcommandline.
PropagationRules
Notapplicable.
Syntax
•yes
•no(default)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-wysiwyg{yes|no}
ISE®DesignSuite
Process>ProcessProperties>Xilinx®SpecicOptions>WYSIWYG
XORPreserve(-pld_xp)
TheXORPreserve(-pld_xp)commandlineoptionenablesordisableshierarchical
atteningofXORmacros.
TheXORsinferredbyHardwareDescriptionLanguage(HDL)synthesisarealso
consideredasmacroblocksintheCPLDow.Theyareprocessedseparatelytogive
moreexibilityforusingdevicemacrocellsXORgates.Youcanattenitsdesign(Flatten
Hierarchyyes,MacroPreserveno)butXilinx®recommendspreservingtheXORsto:
•Reducedesigncomplexity
•ReducethenumberofPTerms
Setthevaluenotoobtaincompletelyatnetlists.Applyingglobaloptimizationona
completelyatdesignsometimesimprovesdesigntting.
ArchitectureSupport
AppliestoallCPLDdevices.DoesnotapplytoFPGAdevices.
ApplicableElements
Appliestotheentiredesign.
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PropagationRules
Notapplicable.
Syntax
-pld_xp{yes|no}
•yes(default)
•no
yespreservesXORmacros.
nomergesXORmacroswithsurroundedlogic.
Selectthefollowingoptionstoobtainacompletelyatteneddesign:
•FlattenHierarchy
yes
•MacroPreserve
no
•XORPreserve
no
ThenovaluedoesnotguaranteetheeliminationoftheXORoperatorfromtheElectronic
DataInterchangeFormat(EDIF)netlist.Duringthenetlistgeneration,thenetlist
mappertriestorecognizeandinferXORgatesinordertodecreasethelogiccomplexity.
ThisprocessisindependentoftheXORpreservationdonebyHardwareDescription
Language(HDL)synthesis,andisguidedonlybythegoalofcomplexityreduction.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-pld_xpyes
PreservesXORmacros.
ISE®DesignSuite
Process>ProcessProperties>Xilinx-SpecicOptions>XORPreserve
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Chapter11
XSTTimingConstraints
Thischapterdiscussesthefollowingconstraints:
•ClockSignal(CLOCK_SIGNAL)
•CrossClockAnalysis(-cross_clock_analysis)
•From-To(FROM-TO)
•GlobalOptimizationGoal(-glob_opt)
•Offset(OFFSET)
•Period(PERIOD)
•TimingName(TNM)
•TimingNameonaNet(TNM_NET)
•Timegroup(TIMEGRP)
•TimingIgnore(TIG)
•WriteTimingConstraints(-write_timing_constraints)
Formoreinformation,see:
•ApplyingTimingConstraints
•XCFTimingConstraintSupport
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Chapter11:XSTTimingConstraints
ApplyingTimingConstraints
Thissectionincludes:
•AboutApplyingTimingConstraints
•ApplyingTimingConstraintsUsingGlobalOptimizationGoal
•ApplyingTimingConstraintsUsingtheUCF
•WritingConstraintstotheNGCFile
•AdditionalOptionsAffectingTimingConstraintProcessing
AboutApplyingTimingConstraints
ApplyXST-supportedtimingconstraintswith:
•GlobalOptimizationGoal(-glob_opt)
•ISE®DesignSuitein:
Process>Properties>SynthesisOptions>GlobalOptimizationGoal
•UserConstraintsFile(UCF)
ApplyingTimingConstraintsUsingGlobalOptimizationGoal
GlobalOptimizationGoal(-glob_opt)allowsyoutoapplytheveglobaltiming
constraints:
•ALLCLOCKNETS
•OFFSET_IN_BEFORE
•OFFSET_OUT_AFTER
•INPAD_TO_OUTPAD
•MAX_DELAY
Theseconstraintsareappliedgloballytotheentiredesign.Youcannotspecifyavaluefor
theseconstraints,sinceXSToptimizesthemforthebestperformance.Theseconstraints
areoverriddenbyconstraintsspeciedintheUserConstraintsFile(UCF).
ApplyingTimingConstraintsUsingtheUCF
TheUserConstraintsFile(UCF)allowsyoutospecifytimingconstraintsusingnative
UCFsyntax.XSTsupportsconstraintssuchas:
•TimingName(TNM)
•Timegroup(TIMEGRP)
•Period(PERIOD)
•TimingIgnore(TIG)
•From-To(FROM-TO)
XSTsupportswildcardsandhierarchicalnameswiththeseconstraints.
WritingConstraintstotheNGCFile
TimingconstraintsarenotwrittentotheNGClebydefault.Timingconstraintsare
writtentotheNGCleonlywhen:
•WriteTimingConstraintsischeckedyesinISEDesignSuiteinProcess>Process
Properties,or
•The-write_timing_constraintsoptionisspeciedwhenusingthecommandline.
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Chapter11:XSTTimingConstraints
AdditionalOptionsAffectingTimingConstraintProcessing
Threeadditionaloptionsaffecttimingconstraintprocessing,regardlessofhowthe
timingconstraintsarespecied:
•CrossClockAnalysis(-cross_clock_analysis)
•WriteTimingConstraints(-write_timing_constraints)
•ClockSignal(CLOCK_SIGNAL)
XCFTimingConstraintSupport
ThissectiondiscussesXSTConstraintFile(XCF)TimingConstraintSupportand
includes:
•HierarchySeparator
•SupportedTimingConstraints
•UnsupportedTimingConstraints
HierarchySeparator
IfyouspecifytimingconstraintsintheXSTConstraintFile(XCF),Xilinx®recommends
thatyouuseaforwardslash(/)asahierarchyseparatorinsteadofanunderscore(_).
Formoreinformation,see:
HierarchySeparator(-hierarchy_separator)
SupportedTimingConstraints
TheXSTConstraintFile(XCF)supportsthefollowingtimingconstraints:
•Period(PERIOD)
•Offset(OFFSET)
•From-To(FROM-TO)
•TimingName(TNM)
•TimingNameonaNet(TNM_NET)
•Timegroup(TIMEGRP)
•TimingIgnore(TIG)
UnsupportedTimingConstraints
IfXSTdoesnotsupportallorpartofaspeciedtimingconstraint,thenXST:
•Issuesawarning,and
•Ignorestheunsupportedtimingconstraint(orunsupportedpartofit)intheTiming
Optimizationstep
IfWriteTimingConstraintsissettoyes,XSTpropagatestheentireconstrainttothenal
netlist,evenifitwasignoredattheTimingOptimizationstep.
ClockSignal(CLOCK_SIGNAL)
TheClockSignal(CLOCK_SIGNAL)constraintallowsyoutodeneaclocksignal
whenthesignalgoesthroughcombinatoriallogicbeforebeingconnectedtotheclock
inputofaip-op.
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Chapter11:XSTTimingConstraints
Inthatinstance,XSTcannotidentifywhichinputpinorinternalsignalistherealclock
signal.Youmustdeneitmanually
ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestosignals.
PropagationRules
Appliestoclocksignals.
Syntax
•yes(default)
•no
•true(XCFonly)
•false(XCFonly)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
VHDL
Declareasfollows:
attributeclock_signal:string;
Specifyasfollows:
attributeclock_signalofsignal_name:signalis{yes|no};
Verilog
Placeimmediatelybeforethesignaldeclaration:
(*clock_signal="{yes|no}"*)
XCF
BEGINMODEL"entity_name"
NET"primary_clock_signal"clock_signal={yes|no|true|false};
END;
CrossClockAnalysis(-cross_clock_analysis)
TheCrossClockAnalysis(-cross_clock_analysis)commandlineoptiontellsXSTto
performinter-clockdomainanalysisduringtimingoptimization.
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ArchitectureSupport
AppliestoallFPGAdevices.DoesnotapplytoCPLDdevices.
ApplicableElements
Appliestotheentiredesign.
PropagationRules
Notapplicable.
Syntax
-cross_clock_analysis{yes|no}
•yes
•no(default)
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-cross_clock_analysisyes
TellsXSTtoperforminter-clockdomainanalysisduringtimingoptimization.
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>CrossClockAnalysis
From-To(FROM-TO)
TheFrom-To(FROM-TO)constraintdenesatimingconstraintbetweentwogroups.
Agroupcanbeuser-denedorpredened:
•FF
•PAD
•RAM
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
SyntaxExample
TIMESPECTSname=FROMgroup1TOgroup2value;
GlobalOptimizationGoal(-glob_opt)
TheGlobalOptimizationGoal(-glob_opt)commandlineoptionselectstheglobal
optimizationgoal.
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Chapter11:XSTTimingConstraints
DependingontheGlobalOptimizationGoal,XSTcanoptimizethefollowingdesign
regions:
•RegistertoRegister
•InpadtoRegister
•RegistertoOutpad
•InpadtoOutpad
Foradetaileddescriptionofsupportedtimingconstraints,see:
Partitions
ApplythefollowingconstraintswithGlobalOptimizationGoal:
•ALLCLOCKNETS(RegistertoRegister)
Optimizestheperiodoftheentiredesign.
XSTidenties,bydefault,allpathsfromregistertoregisteronthesameclockforall
clocksinadesign.Totakeinter-clockdomaindelaysintoaccount,setCrossClock
Analysis(-cross_clock_analysis)toyes.
•OFFSET_IN_BEFORE(InpadtoRegister)
Optimizesthemaximumdelayfrominputpadtoclock,eitherforaspecicclock
orforanentiredesign.
XSTidentiesallpathsfromeitherallsequentialelementsorthesequentialelements
drivenbythegivenclocksignalnametoallprimaryoutputports.
•OFFSET_OUT_AFTER(RegistertoOutpad)
Optimizesthemaximumdelayfromclocktooutputpad,eitherforaspecicclock
orforanentiredesign.
XSTidentiesallpathsfromallprimaryinputportstoeitherallsequentialelements
orthesequentialelementsdrivenbythegivenclocksignalname.
•INPAD_TO_OUTPAD(InpadtoOutpad)
Optimizesthemaximumdelayfrominputpadtooutputpadthroughoutanentire
design.
•MAX_DELAY
Incorporatesallpreviouslymentionedconstraints
Theseconstraintsaffecttheentiredesign.Theyapplyonlyifnotimingconstraintsare
speciedintheconstraintle.
Syntax
-glob_opt
{allclocknets|offset_in_before|offset_out_after|inpad_to_outpad|max_delay}
YoucannotspecifyavalueforGlobalOptimizationGoal.XSToptimizestheentire
designforthebestperformance.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-glob_optOFFSET_OUT_AFTER
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Chapter11:XSTTimingConstraints
Optimizesthemaximumdelayfromclocktooutputpadfortheentiredesign
ISE®DesignSuite
Process>ProcessProperties>SynthesisOptions>GlobalOptimizationGoal
GlobalOptimizationGoalDomainDefinitions
Thepossibledomainsareshowninthefollowingschematic.
•ALLCLOCKNETS(registertoregister)
Identies,bydefault,allpathsfromregistertoregisteronthesameclockforall
clocksinadesign.Totakeinter-clockdomaindelaysintoaccount,setCrossClock
Analysis(–cross_clock_analysis)toyes.
•OFFSET_IN_BEFORE(inpadtoregister)
Identiesallpathsfromallprimaryinputportstoeitherallsequentialelementsor
thesequentialelementsdrivenbythegivenclocksignalname.
•OFFSET_OUT_AFTER(registertooutpad)
Similartothepreviousconstraint,butsetstheconstraintfromthesequential
elementstoallprimaryoutputports.
•INPAD_TO_OUTPAD(inpadtooutpad)
Setsamaximumcombinatorialpathconstraint.
•MAX_DELAY
Identiesallpathsdenedbythefollowingtimingconstraints:
–ALLCLOCKNETS
–OFFSET_IN_BEFORE
–OFFSET_OUT_AFTER
–INPAD_TO_OUTPAD
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Chapter11:XSTTimingConstraints
Offset(OFFSET)
TheOffset(OFFSET)constraint:
•Isabasictimingconstraint.
•Speciesthetimingrelationshipbetweenanexternalclockanditsassociateddata-in
ordata-outpin.
•Isusedonlyforpad-relatedsignals.
•Cannotbeusedtoextendthearrivaltimespecicationmethodtotheinternal
signalsinadesign.
•Allowsyouto:
–Calculatewhetherasetuptimeisbeingviolatedataip-opwhosedataand
clockinputsarederivedfromexternalnets.
–SpecifythedelayofanexternaloutputnetderivedfromtheQoutputofan
internalip-opbeingclockedfromanexternaldevicepin.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
Syntax
OFFSET={IN|OUT}offset_time[units]{BEFORE|AFTER}clk_name[TIMEGRP
group_name];
Period(PERIOD)
ThePeriod(PERIOD)constraintisabasictimingconstraintandsynthesisconstraint.
Aclockperiodspecicationcheckstimingbetweenallsynchronouselementswithinthe
clockdomainasdenedinthedestinationelementgroup.Thegroupmaycontainpaths
thatpassbetweenclockdomainsiftheclocksaredenedasafunctionofoneortheother.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
Syntax
NETnetnamePERIOD=value[{HIGH|LOW}value];
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Chapter11:XSTTimingConstraints
TimingName(TNM)
TheTimingName(TNM)constraint:
•Isabasicgroupingconstraint.
•Identiestheelementsthatmakeupagrouptobeusedinatimingspecication.
•Tagsthefollowingspecicelementsasmembersofagrouptosimplifythe
applicationoftimingspecicationstothegroup.
–FF
–RAM
–LATCH
–PAD
–CPU
–BRAM_PORTA
–BRAM_PORTB
–HSIO
–MULT
TheRISINGandFALLINGkeywordsmaybeusedwithTNMconstraints.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
Syntax
{INST|NET|PIN}inst_net_or_pin_nameTNM=[predened_group:]identier;
TimingNameonaNet(TNM_NET)
TheTimingNameonaNet(TNM_NET)constraint:
•IsessentiallyequivalenttoTimingName(TNM)onanetexceptforinputpadnets.
NoteSpecialrulesapplywhenusingTimingNameonaNetwiththePeriod
(PERIOD)constraintforDLLandDCMcomponents.
Formoreinformation,see:
PERIODSpecicationsonCLKDLLsandDCMsintheConstraintsGuide
•IsapropertythatyounormallyuseinconjunctionwithaHardwareDescription
Language(HDL)designtotagaspecicnet.
NoteAlldownstreamsynchronouselementsandpadstaggedwiththeTiming
NameonaNetidentierareconsideredagroup.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
Syntax
NETnetnameTNM_NET=[predened_group:]identier;
Timegroup(TIMEGRP)
TheTimegroup(TIMEGRP)constraintisabasicgroupingconstraint.
InadditiontonaminggroupsusingtheTNMidentier,youcanalsodenegroupsin
termsofothergroups.Youcancreateagroupthatisacombinationofexistinggroups
bydeningaTimegroupconstraint.
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Chapter11:XSTTimingConstraints
PlaceTimegroupconstraintsinanXSTConstraintFile(XCF)oraNetlistConstraints
File(NCF).
UseTimegroupattributestocreategroupsusingthefollowingmethods:
•Combiningmultiplegroupsintoone
•Deningip-opsubgroupsbyclocksense
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
Syntax
TIMEGRPnewgroup=existing_grp1existing_grp2[existing_grp3...];
TimingIgnore(TIG)
TheTimingIgnore(TIG)constraint:
•Causesallpathsgoingthroughaspecicnettobeignoredfortiminganalysesand
optimizationpurposes.
•Canbeappliedtothenameofthesignalaffected.
Formoreinformationaboutthisconstraint,seetheConstraintsGuide.
Syntax
NETnet_nameTIG;
WriteTimingConstraints(-write_timing_constraints)
TheWriteTimingConstraints(-write_timing_constraints)commandlineoption
specieswhentimingconstraintsarewrittentotheNGCle.
TimingconstraintsarewrittentotheNGCleonlywhen:
•WriteTimingConstraintsischeckedyesinISE®DesignSuiteinProcess>Process
Properties,or
•The-write_timing_constraintsoptionisspeciedwhenusingthecommandline.
TimingconstraintsarenotwrittentotheNGClebydefault.
ArchitectureSupport
Architectureindependent.
ApplicableElements
AppliestoanentiredesignthroughtheXSTcommandline.
PropagationRules
Notapplicable.
Syntax
-write_timing_constraints{yes|no}
•yes(default)
•no
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Chapter11:XSTTimingConstraints
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XSTCommandLine
xstrun-write_timing_constraintsyes
TimingconstraintsarewrittentotheNGCle.
ISEDesignSuite
Process>ProcessProperties>SynthesisOptions>WriteTimingConstraints
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Chapter12
XSTImplementationConstraints
Thischapterdiscussesthefollowingconstraints:
•NoReduce(NOREDUCE)
•PowerMode(PWR_MODE)
•RLOC
Implementationconstraintscontrolplacementandrouting.Theyarenotdirectlyused
byXST,butarepropagatedandmadeavailabletotheimplementationtools.Theobject
towhichanimplementationconstraintisattachedispreserved.
AbinaryequivalentoftheimplementationconstraintiswrittentotheNGCle.Since
theleisbinary,youcannoteditanimplementationconstraintintheNGCle.
YoucancodeanimplementationconstraintintheXSTConstraintFile(XCF)as
illustratedinImplementationConstraintsSyntaxExamples.
Formoreinformation,seetheConstraintsGuide.
ImplementationConstraintsSyntaxExamples
ThissectiongivesthefollowingImplementationConstraintssyntaxexamples:
•XCFSyntaxExamples
•VHDLSyntaxExamples
•VerilogSyntaxExamples
XCFSyntaxExamples
ThissectiongivestwoXCFSyntaxExamples,including,foreachexample,onefor
MethodOneandoneforMethodTwo.
XCFSyntaxExampleOne
Toapplyanimplementationconstrainttoanentireentity,useeitherofthefollowing
XSTConstraintFile(XCF)syntaxes:
MethodOne
MODELEntityNamePropertyName;
MethodTwo
MODELEntityNamePropertyName=PropertyValue;
XCFSyntaxExampleTwo
Toapplyanimplementationconstrainttospecicinstances,nets,orpinswithinan
entity,useeitherofthefollowingsyntaxes:
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Chapter12:XSTImplementationConstraints
MethodOne
BEGINMODELEntityName{NET|INST|PIN}{NetName|InstName|SigName}
PropertyName;
END;
MethodTwo
BEGINMODELEntityName{NET|INST|PIN}{NetName|InstName|SigName}
PropertyName=Propertyvalue;
END;
VHDLSyntaxExamples
SpecifyimplementationconstraintsinVHDLasfollows:
attributePropertyNameof{NetName|InstName|PinName}:{signal|label}is
"PropertyValue";
VerilogSyntaxExamples
SpecifyimplementationconstraintsinVerilogasfollows:
//synthesisattributePropertyNameof{NetName|InstName|PinName}is"PropertyValue";
InVerilog-2001,wheredescriptionsprecedethesignal,module,orinstancetowhich
theyrefer,specifyimplementationconstraintsasfollows:
(*PropertyName="PropertyValue"*)
NoReduce(NOREDUCE)
AppliestoallCPLDdevices.DoesnotapplytoFPGAdevices.
NoReduce(NOREDUCE)preventstheoptimizationoftheBooleanequationgenerating
agivensignal.Assumingalocalsignalisassignedthearbitraryfunctionbelow,andNo
Reduceattachedtothesignals:
signals:std_logic;
attributeNOREDUCE:boolean;
attributeNOREDUCEofs:signalis"true";
...
s<=aor(aandb);
SpecifyNoReduceintheXSTConstraintFile(XCF)asfollows:
BEGINMODELENTNAME
NETsNOREDUCE;
NETsKEEP;
END;
XSTwritesthefollowingstatementstotheNGCle:
NETsNOREDUCE;
NETsKEEP;
Formoreinformation,seetheConstraintsGuide.
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Chapter12:XSTImplementationConstraints
PowerMode(PWR_MODE)
ThePowerMode(PWR_MODE)constraintcontrolsthepowerconsumption
characteristicsofmacrocells.
ThefollowingVHDLstatementspeciesthatthefunctiongeneratingsignalsshouldbe
optimizedforlowpowerconsumption:
attributePWR_MODE:string;
attributePWR_MODEofs:signalis"LOW";
XSTwritesthefollowingstatementtotheNGCle:
NETsPWR_MODE=LOW;
NETsKEEP;
TheHDLattributecanbeappliedtothesignalonwhichXSTinferstheinstanceif:
•Theattributeappliestoaninstance,and
•Theinstanceisnotavailable(notinstantiated)intheHDLsource
Examplesofinstancesinclude:
•PackI/ORegistersIntoIOBs(IOB)
•DRIVE
•IOSTANDARD
ArchitectureSupport
AppliestoallCPLDdevices.DoesnotapplytoFPGAdevices.
SyntaxExamplesandSettings
Thefollowingsyntaxexamplesandsettingsshowhowtousethisconstraintor
commandlineoptionwithparticulartoolsormethods.Ifatoolormethodisnotlisted,
youcannotusethisconstraintorcommandlineoptionwithit.
XCF
MODELENTNAME
NETsPWR_MODE=LOW;
NETsKEEP;
END;
RLOC(RLOC)
See:
RLOC(RLOC)
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Chapter13
XSTSupportedThirdPartyConstraints
ThischapterdescribesXSTSupportedThirdPartyConstraints,andincludes:
•XSTEquivalentstoThirdPartyConstraints
•ThirdPartyConstraintsSyntaxExamples
XSTEquivalentstoThirdPartyConstraints
ThissectionshowstheXSTequivalentforeachofthethirdpartyconstraints.Forspecic
informationontheseconstraints,seethevendordocumentation.
SeveralthirdpartyconstraintsareautomaticallysupportedbyXST,asshowninthe
tablebelow.Constraintsmarkedyesarefullysupported.Ifaconstraintisonlypartially
supported,thesupportconditionsareshownintheAutomaticRecognitioncolumn.
Thefollowingrulesapply:
•VHDLusesstandardattributesyntax.NochangesareneededtotheHardware
DescriptionLanguage(HDL)code.
•ForVerilogwiththirdpartymeta-commentsyntax,themeta-commentsyntaxmust
bechangedtoconformtoXSTconventions.Theconstraintnameanditsvaluecan
beusedasshowninthethirdpartytool.
•ForVerilog2001attributes,nochangesareneededtotheHDLcode.Theconstraint
isautomaticallytranslatedasinthecaseofVHDLattributesyntax.
XSTEquivalentstoThirdPartyConstraints
NameVendorXSTEquivalentAutomatic
RecognitionAvailableFor
black_boxSynopsysBoxTypeN/AVHDL,Verilog
black_box_pad_pinSynopsysN/AN/AN/A
black_box_tri_pinsSynopsysN/AN/AN/A
cell_listSynopsysN/AN/AN/A
clock_listSynopsysN/AN/AN/A
EnumSynopsysN/AN/AN/A
full_caseSynopsysFullCaseN/AVerilog
ispadSynopsysN/AN/AN/A
map_to_moduleSynopsysN/AN/AN/A
net_nameSynopsysN/AN/AN/A
parallel_caseSynopsysParallelCaseN/AVerilog
return_port_nameSynopsysN/AN/AN/A
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Chapter13:XSTSupportedThirdPartyConstraints
NameVendorXSTEquivalentAutomatic
RecognitionAvailableFor
resource_sharing
directives
SynopsysResourceSharingN/AVHDL,Verilog
set_dont_touch_networkSynopsysnotrequiredN/AN/A
set_dont_touchSynopsysnotrequiredN/AN/A
set_dont_use_cel_nameSynopsysnotrequiredN/AN/A
set_preferSynopsysN/AN/AN/A
state_vectorSynopsysN/AN/AN/A
syn_allow_retimingSynopsysRegisterBalancingN/AVHDL,Verilog
syn_black_boxSynopsysBoxTypeYesVHDL,Verilog
syn_direct_enableSynopsysN/AN/AN/A
syn_edif_bit_formatSynopsysN/AN/AN/A
syn_edif_scalar_formatSynopsysN/AN/AN/A
syn_encodingSynopsysFSMEncoding
Algorithm
Yes(Thevaluesafe
isnotsupported
forautomatic
recognition.Use
SafeImplementation
inXSTtoactivatethis
mode.)
VHDL,Verilog
syn_enum_encodingSynopsysEnumeratedEncodingN/AVHDL
syn_hierSynopsysKeepHierarchyYes
syn_hier=
hardrecognized
askeep_hierarchy=
soft
syn_hier=
removerecognized
askeep_hierarchy=no
(XSTsupportsonly
thevalueshard
andremovefor
syn_hierinautomatic
recognition.)
VHDL,Verilog
syn_isclockSynopsysN/AN/AN/A
syn_keepSynopsysKeepYes(XSTpreservesthe
designatednetinthe
nalnetlist,butdoes
notattachanyKEEP
constrainttoit.)
VHDL,Verilog
syn_maxfanSynopsysMaxFanoutYesVHDL,Verilog
syn_netlist_hierarchySynopsysNetlistHierarchyN/AVHDL,Verilog
syn_noarrayportsSynopsysN/AN/AN/A
syn_noclockbufSynopsysBufferTypeYesVHDL,Verilog
syn_nopruneSynopsysOptimizeInstantiated
Primitives
YesVHDL,Verilog
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Chapter13:XSTSupportedThirdPartyConstraints
NameVendorXSTEquivalentAutomatic
RecognitionAvailableFor
syn_pipelineSynopsysRegisterBalancingN/AVHDL,Verilog
syn_preserveSynopsysEquivalentRegister
Removal
YesVHDL,Verilog
syn_ramstyleSynopsysram_extractand
ram_style
Yes
XSTimplements
RAMsin
no_rw_check
moderegardless
ifno_rw_checkis
speciedornot
theareavalueis
ignored
VHDL,Verilog
syn_reference_clockSynopsysN/AN/AN/A
syn_replicateSynopsysRegisterDuplicationYesVHDL,Verilog
syn_romstyleSynopsysrom_extractand
rom_style
YesVHDL,Verilog
syn_sharingSynopsysN/AN/AVHDL,Verilog
syn_state_machineSynopsysAutomaticFSM
Extraction
YesVHDL,Verilog
syn_tco<n>SynopsysN/AN/AN/A
syn_tpd<n>SynopsysN/AN/AN/A
syn_tristateSynopsysN/AN/AN/A
syn_tristatetomuxSynopsysN/AN/AN/A
syn_tsu<n>SynopsysN/AN/AN/A
syn_useenablesSynopsysN/AN/AN/A
syn_useioffSynopsysPackI/ORegistersInto
IOBs
N/AVHDL,Verilog
synthesistranslate_off
synthesistranslate_on
SynopsysTranslateOff
TranslateOn
YesVHDL,Verilog
xc_aliasSynopsysN/AN/AN/A
xc_clockbuftypeSynopsysBufferTypeN/AVHDL,Verilog
xc_fastSynopsysFASTN/AVHDL,Verilog
xc_fast_autoSynopsysFASTN/AVHDL,Verilog
xc_global_buffersSynopsysBUFG(XST)N/AVHDL,Verilog
xc_ioffSynopsysPackI/ORegistersInto
IOBs
N/AVHDL,Verilog
xc_isgsrSynopsysN/AN/AN/A
xc_locSynopsysLOCYesVHDL,Verilog
xc_mapSynopsysLUT_MAPYes(XSTsupports
onlythevalue
lutforautomatic
recognition.)
VHDL,Verilog
xc_ncf_auto_relaxSynopsysN/AN/AN/A
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Chapter13:XSTSupportedThirdPartyConstraints
NameVendorXSTEquivalentAutomatic
RecognitionAvailableFor
xc_nodelaySynopsysNODELAYN/AVHDL,Verilog
xc_padtypeSynopsysI/OStandardN/AVHDL,Verilog
xc_propsSynopsysN/AN/AN/A
xc_pullupSynopsysPULLUPN/AVHDL,Verilog
xc_rlocSynopsysRLOCYesVHDL,Verilog
xc_fastSynopsysFASTN/AVHDL,Verilog
xc_slowSynopsysN/AN/AN/A
xc_usetSynopsysU_SETYesVHDL,Verilog
ThirdPartyConstraintsSyntaxExamples
Thefollowingthirdpartyconstraintssyntaxexamplesaretheonlywaysto:
•Preserveasignal/netinaHardwareDescriptionLanguage(HDL)design,and
•Preventoptimizationonthesignalornetduringsynthesis
ThirdPartyConstraintsVerilogSyntaxExample
moduletestkeep(in1,in2,out1);
inputin1;
inputin2;
outputout1;
(*keep="yes"*)wireaux1;
(*keep="yes"*)wireaux2;
assignaux1=in1;
assignaux2=in2;
assignout1=aux1&aux2;
endmodule
ThirdPartyConstraintsXCFSyntaxExample
Keep(KEEP)canalsobeappliedthroughtheseparatesynthesisconstraintle:
BEGINMODELtestkeep
NETaux1KEEP=true;
END;
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Chapter14
XSTVHDLLanguageSupport
Thischapter:
•ExplainshowXSTsupportstheVHSICHardwareDescriptionLanguage(VHDL)
•ProvidesdetailsonVHDLsupportedconstructsandsynthesisoptions
Thischapterincludes:
•VHDLLogicDescriptions
•VHDLIEEESupport
•VHDLFileTypeSupport
•VHDLDebuggingUsingWriteOperation
•VHDLDataTypes
•VHDLRecordTypes
•VHDLInitialValues
•VHDLObjects
•VHDLOperators
•VHDLEntityandArchitectureDescriptions
•VHDLCombinatorialCircuits
•VHDLSequentialCircuits
•VHDLFunctionsandProcedures
•VHDLAssertStatements
•VHDLModelsDenedUsingPackages
•VHDLConstructsSupportedinXST
•VHDLReservedWords
VHDLLogicDescriptions
VHDLoffersabroadsetofconstructsforcompactlydescribingcomplicatedlogic:
•Allowsthedescriptionofthestructureofasystem:
–Howitisdecomposedintosubsystems
–Howthosesubsystemsareinterconnected
•Allowsthespecicationofthefunctionofasystemusingfamiliarprogramming
languageforms.
•Allowsthedesignofasystemtobesimulatedbeforebeingimplementedand
manufactured.Thisfeatureallowsyoutotestforcorrectnesswithoutthedelay
andexpenseofhardwareprototyping.
•Providesamechanismforeasilyproducingadetailed,device-dependentversionof
adesigntobesynthesizedfromamoreabstractspecication.Thisfeatureallows
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Chapter14:XSTVHDLLanguageSupport
youtoconcentrateonmorestrategicdesigndecisions,andreducetheoveralltimeto
marketforthedesign.
Formoreinformation,see:
•IEEEVHDLLanguageReferenceManual
•XSTDesignConstraints
•VHDLAttributeSyntax
VHDLIEEESupport
ThissectiondiscussesVHDLIEEESupport,andincludes:
•SupportedVHDLIEEEStandards
•VHDLIEEEConicts
•Non-LRMCompliantConstructsinVHDL
SupportedVHDLIEEEStandards
XSTsupportsthefollowingVHDLIEEEstandards:
•Std1076-1987
•Std1076-1993
•Std1076-2006
NoteStd1076-2006isonlypartiallyimplemented.XSTallowsinstantiationforStd
1076-2006asshowninthefollowingtable.
FormalPortAssociatedActual
bufferout
outbuffer
VHDLIEEEConflicts
VHDLIEEEStd1076-1987constructsareacceptediftheydonotconictwithVHDL
IEEEStd1076-1993.Incaseofaconict,Std1076-1993behavioroverridesStd1076-1987.
Incaseswhere:
•Std1076-1993requiresaconstructtobeanerroneouscase,but
•Std1076-1987acceptsit,
XSTissuesawarninginsteadofanerror.Anerrorwouldstopanalysis.
VHDLIEEEConflictExample
FollowingisanexampleofaVHDLIEEEconict:
•Std1076-1993requiresanimpurefunctiontousetheimpurekeywordwhile
declaringafunction.
•Std1076-1987hasnosuchrequirement.
Inthiscase,XST:
•AcceptstheVHDLcodewrittenforStd1076-1987
•IssuesawarningstatingStd1076-1993behavior
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Chapter14:XSTVHDLLanguageSupport
Non-LRMCompliantConstructsinVHDL
XSTsupportssomenon-LRMcompliantconstructs.XSTsupportsaspecicnon-LRM
compliantconstructwhen:
•Amajorityofsynthesisorsimulationthird-partytoolssupporttheconstruct,and
•Itisareallanguagelimitationfordesigncoding,andhasnoimpactonqualityof
resultsorproblemdetectioninthedesign.
Forexample,theLRMdoesnotallowinstantiationwhentheformalportisabufferand
theeffectiveoneisanout(andvice-versa).
VHDLFileTypeSupport
XSTsupportsalimitedFileReadandFileWritecapabilityforVHDLasshowninthe
followingtable.
CapabilityUsageExamples
FileReadInitializeRAMsfromanexternalle
FileWrite•Debugprocesses
•Writeaspecicconstantorgenericvaluetoanexternalle
Formoreinformation,see:
InitializingRAMCodingExamples
Useanyofthereadfunctionsshowninthefollowingtable.Thesereadfunctionsare
supportedbythefollowingpackages:
•standard
•std.textio
•ieee.std_logic_textio
FunctionPackage
le(typetextonly)standard
access(typelineonly)standard
le_open(le,name,open_kind)standard
le_close(le)standard
endle(le)standard
textstd.textio
linestd.textio
widthstd.textio
readline(text,line)std.textio
readline(line,bit,boolean)std.textio
read(line,bit)std.textio
readline(line,bit_vector,boolean)std.textio
read(line,bit_vector)std.textio
read(line,boolean,boolean)std.textio
read(line,boolean)std.textio
read(line,character,boolean)std.textio
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Chapter14:XSTVHDLLanguageSupport
FunctionPackage
read(line,character)std.textio
read(line,string,boolean)std.textio
read(line,string)std.textio
write(le,line)std.textio
write(line,bit,boolean)std.textio
write(line,bit)std.textio
write(line,bit_vector,boolean)std.textio
write(line,bit_vector)std.textio
write(line,boolean,boolean)std.textio
write(line,boolean)std.textio
write(line,character,boolean)std.textio
write(line,character)std.textio
write(line,integer,boolean)std.textio
write(line,integer)std.textio
write(line,string,boolean)std.textio
write(line,string)std.textio
read(line,std_ulogic,boolean)ieee.std_logic_textio
read(line,std_ulogic)ieee.std_logic_textio
read(line,std_ulogic_vector),booleanieee.std_logic_textio
read(line,std_ulogic_vector)ieee.std_logic_textio
read(line,std_logic_vector,boolean)ieee.std_logic_textio
read(line,std_logic_vector)ieee.std_logic_textio
write(line,std_ulogic,boolean)ieee.std_logic_textio
write(line,std_ulogic)ieee.std_logic_textio
write(line,std_ulogic_vector,boolean)ieee.std_logic_textio
write(line,std_ulogic_vector)ieee.std_logic_textio
write(line,std_logic_vector,boolean)ieee.std_logic_textio
write(line,std_logic_vector)ieee.std_logic_textio
hreadieee.std_logic_textio
VHDLDebuggingUsingWriteOperation
ThissectiondiscussesVHDLDebuggingUsingWriteOperation,andincludes:
•RulesforDebugging
•UsingtheEndleFunction
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Chapter14:XSTVHDLLanguageSupport
RulesforDebugging
FollowtheserulesfordebuggingusingwriteoperationinVHDL:
•Duringastd_logicreadoperation,theonlyallowedcharactersare0and1.Other
valuessuchasXandZarenotallowed.XSTrejectsthedesigniftheleincludes
charactersotherthan0and1,exceptthatXSTignoresablankspacecharacter.
•Donotuseidenticalnamesforlesplacedindifferentdirectories.
•Donotuseconditionalcallstoreadprocedures,asshowninthefollowingcoding
example.
ifSEL=’1’then
read(MY_LINE,A(3downto0));
else
read(MY_LINE,A(1downto0));
endif;
UsingtheEndfileFunction
XSTrejectsthedesignifyouusethefollowingdescriptionstylewiththeendlefunction:
while(notendfile(MY_FILE))loop
readline(MY_FILE,MY_LINE);
read(MY_LINE,MY_DATA);
endloop;
XSTissuesthefollowingerrormessage:
Line<MY_LINE>hasnotenoughelementsfortarget<MY_DATA>.
Toxtheproblem,addexitwhenendle(MY_FILE);tothewhileloop.
while(notendfile(MY_FILE))loop
readline(MY_FILE,MY_LINE);
exitwhenendfile(MY_FILE);
read(MY_LINE,MY_DATA);
endloop;
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Chapter14:XSTVHDLLanguageSupport
CodingExample
--
--Print2constantstotheoutputfile
--
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_arith.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
useSTD.TEXTIO.all;
useIEEE.STD_LOGIC_TEXTIO.all;
entityfile_support_1is
generic(data_width:integer:=4);
port(clk,sel:instd_logic;
din:instd_logic_vector(data_width-1downto0);
dout:outstd_logic_vector(data_width-1downto0));
endfile_support_1;
architectureBehavioraloffile_support_1is
fileresults:textisout"test.dat";
constantbase_const:std_logic_vector(data_width-1downto0):=conv_std_logic_vector(3,data_width);
constantnew_const:std_logic_vector(data_width-1downto0):=base_const+"1000";
begin
process(clk)
variabletxtline:LINE;
begin
write(txtline,string’("--------------------"));
writeline(results,txtline);
write(txtline,string’("BaseConst:"));
write(txtline,base_const);
writeline(results,txtline);
write(txtline,string’("NewConst:"));
write(txtline,new_const);
writeline(results,txtline);
write(txtline,string’("--------------------"));
writeline(results,txtline);
if(clk’eventandclk=’1’)then
if(sel=’1’)then
dout<=new_const;
else
dout<=din;
endif;
endif;
endprocess;
endBehavioral;
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Chapter14:XSTVHDLLanguageSupport
VHDLDataTypes
ThissectiondiscussesVHDLDataTypes,andincludes:
•AcceptedVHDLDataTypes
•VHDLOverloadedDataTypes
•VHDLMulti-DimensionalArrayTypes
AcceptedVHDLDataTypes
XSTacceptsthefollowingVHDLdatatypes:
•VHDLEnumeratedTypes
•VHDLUser-DenedEnumeratedTypes
•VHDLBitVectorTypes
•VHDLIntegerTypes
•VHDLPredenedTypes
•VHDLSTD_LOGIC_1164IEEETypes
VHDLEnumeratedTypes
TypeValuesMeaningComment
BIT0,1----
BOOLEANfalse,true----
REAL$-.to$+.----
STD_LOGICUunitializedNotacceptedbyXST
XunknownTreatedasdon’tcare
0lowTreatedidenticallytoL
1highTreatedidenticallytoH
ZhighimpedanceTreatedashighimpedance
WweakunknownNotacceptedbyXST
LweaklowTreatedidenticallyto0
HweakhighTreatedidenticallyto1
-don’tcareTreatedasdon’tcare
VHDLUser-DefinedEnumeratedTypes
typeCOLORis(RED,GREEN,YELLOW);
VHDLBitVectorTypes
•BIT_VECTOR
•STD_LOGIC_VECTOR
VHDLIntegerTypes
INTEGER
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VHDLPredefinedTypes
•BIT
•BOOLEAN
•BIT_VECTOR
•INTEGER
•REAL
VHDLSTD_LOGIC_1164IEEETypes
ThefollowingtypesaredeclaredintheSTD_LOGIC_1164IEEEpackage:
•STD_LOGIC
•STD_LOGIC_VECTOR
ThispackageiscompiledintheIEEElibrary .Touseoneofthesetypes,addthefollowing
twolinestotheVHDLspecication:
libraryIEEE;useIEEE.STD_LOGIC_1164.all;
VHDLOverloadedDataTypes
Thefollowingdatatypescanbeoverloaded:
•VHDLOverloadedEnumeratedTypes
•VHDLOverloadedBitVectorTypes
•VHDLOverloadedIntegerTypes
•VHDLOverloadedSTD_LOGIC_1164IEEETypes
•VHDLOverloadedSTD_LOGIC_ARITHIEEETypes
VHDLOverloadedEnumeratedTypes
•STD_ULOGIC
ContainsthesameninevaluesastheSTD_LOGICtype,butdoesnotcontain
predenedresolutionfunctions
•X01
SubtypeofSTD_ULOGICcontainingtheX,0and1values
•X01Z
SubtypeofSTD_ULOGICcontainingtheX,0,1andZvalues
•UX01
SubtypeofSTD_ULOGICcontainingtheU,X,0and1values
•UX01Z
SubtypeofSTD_ULOGICcontainingtheU,X,0,1,andZvalues
VHDLOverloadedBitVectorTypes
•STD_ULOGIC_VECTOR
•UNSIGNED
•SIGNED
Unconstrainedtypes(typeswhoselengthisnotdened)arenotaccepted.
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VHDLOverloadedIntegerTypes
•NATURAL
•POSITIVE
Anyintegertypewithinauser-denedrange.Forexample:
typeMSBisrange8to15;
meansanyinteger:
•greaterthan7,or
•lessthan16
ThetypesNATURALandPOSITIVEareVHDLpredenedtypes.
VHDLOverloadedSTD_LOGIC_1164IEEETypes
ThefollowingtypesaredeclaredintheSTD_LOGIC_1164IEEEpackage:
•STD_ULOGIC(andsubtypesX01,X01Z,UX01,UX01Z)
•STD_LOGIC
•STD_ULOGIC_VECTOR
•STD_LOGIC_VECTOR
ThispackageiscompiledinthelibraryIEEE.Touseoneofthesetypes,addthefollowing
twolinestotheVHDLspecication:
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
VHDLOverloadedSTD_LOGIC_ARITHIEEETypes
ThetypesUNSIGNEDandSIGNED(denedasanarrayofSTD_LOGIC)aredeclared
intheSTD_LOGIC_ARITHIEEEpackage.
ThispackageiscompiledinthelibraryIEEE.Tousethesetypes,addthefollowingtwo
linestotheVHDLspecication:
libraryIEEE;
useIEEE.STD_LOGIC_ARITH.all;
VHDLMulti-DimensionalArrayTypes
XSTsupportsmulti-dimensionalarraytypesofuptothreedimensions.BRAMsarenot
inferred.Arrayscanbe:
•Signals
•Constants
•VHDLvariables
Youcandoassignmentsandarithmeticoperationswitharrays.Youcanalsopass
multi-dimensionalarraystofunctions,andusethemininstantiations.
CodingExampleOne
Thearraymustbefullyconstrainedinalldimensions,asshowninthefollowingcoding
example.
subtypeWORD8isSTD_LOGIC_VECTOR(7downto0);
typeTAB12isarray(11downto0)ofWORD8;
typeTAB03isarray(2downto0)ofTAB12;
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CodingExampleTwo
Youcanalsodeclareanarrayasamatrix,asshowninthefollowingcodingexample.
subtypeTAB13isarray(7downto0,4downto0)of
STD_LOGIC_VECTOR(8downto0);
Considerthefollowingdeclarations:
subtypeWORD8isSTD_LOGIC_VECTOR(7downto0);
typeTAB05isarray(4downto0)ofWORD8;
typeTAB03isarray(2downto0)ofTAB05;
signalWORD_A:WORD8;
signalTAB_A,TAB_B:TAB05;
signalTAB_C,TAB_D:TAB03;
constantCNST_A:TAB03:=(
("00000000","01000001","01000010","10000011","00001100"),
("00100000","00100001","00101010","10100011","00101100"),
("01000010","01000010","01000100","01000111","01000100"));
Thefollowingcannowbespecied:
•Amulti-dimensionalarraysignalorvariable
TAB_A<=TAB_B;TAB_C<=TAB_D;TAB_C<=CNST_A;
•Anindexofonearray
TAB_A(5)<=WORD_A;TAB_C(1)<=TAB_A;
•Indexesofthemaximumnumberofdimensions
TAB_A(5)(0)<=’1’;TAB_C(2)(5)(0)<=’0’
•Asliceoftherstarray
TAB_A(4downto1)<=TAB_B(3downto0);
•Anindexofahigherlevelarrayandasliceofalowerlevelarray:
TAB_C(2)(5)(3downto0)<=TAB_B(3)(4downto1);TAB_D
(0)(4)(2downto0)<=CNST_A(5downto3)
CodingExampleThree
Addthefollowingdeclaration:
subtypeMATRIX15isarray(4downto0,2downto0)of
STD_LOGIC_VECTOR(7downto0);signalMATRIX_A:MATRIX15;
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Thefollowingcannowbespecied:
•Amulti-dimensionalarraysignalorvariable
MATRIXA<=CNST_A;
•Anindexofonerowofthearray
MATRIXA(5)<=TAB_A;
•Indexesofthemaximumnumberofdimensions
MATRIXA(5,0)(0)<=’1’;
Indexesmaybevariable.
VHDLRecordTypes
XSTsupportsVHDLrecordtypes,asshowninthefollowingCodingExample.
•Recordtypescancontainotherrecordtypes.
•Constantscanberecordtypes.
•Recordtypescannotcontainattributes.
•XSTsupportsaggregateassignmentstorecordsignals.
CodingExample
typeREC1isrecord
field1:std_logic;
field2:std_logic_vector(3downto0)
endrecord;
VHDLInitialValues
ThissectiondiscussesVHDLInitialValues,andincludes:
•InitializingRegisters
•VHDLLocalReset/GlobalReset
•DefaultInitialValuesonMemoryElementsinVHDL
InitializingRegisters
InVHDL,youcaninitializeregisterswhenyoudeclarethem.
Thevalue:
•Isaconstant
•Cannotdependonearlierinitialvalues
•Cannotbeafunctionortaskcall
•Canbeaparametervaluepropagatedtoaregister
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CodingExampleOne
Whenyougivearegisteraninitialvalueinadeclaration,XSTsetsthisvalue:
•Ontheoutputoftheregisteratglobalreset,or
•Atpowerup
Theassignedvalue:
•IscarriedintheNGCleasanINITattributeontheregister
•Isindependentofanylocalreset
signalarb_onebit:std_logic:=’0’;
signalarb_priority:std_logic_vector(3downto0):="1011";
CodingExampleTwo
Youcanalsoassignaset/resetvaluetoaregisterinbehavioralVHDLcode.Assigna
valuetoaregisterwhentheregisterresetlinegoestotheappropriatevalue.
process(clk,rst)
begin
ifrst=’1’then
arb_onebit<=’0’;
endif;
endprocess;
Whenyousettheinitialvalueofavariableinthebehavioralcode,itisimplementedin
thedesignasaip-opwhoseoutputcanbecontrolledbyalocalreset.Assuch,itis
carriedintheNGCleasanFDPorFDCip-op.
VHDLLocalReset/GlobalReset
Localresetisindependentofglobalreset.Registerscontrolledbyalocalresetmaybeset
toadifferentvaluefromregisterswhosevalueisonlyresetatglobalreset(powerup).
Inthefollowingcodingexample,theregisterarb_onebitissetto1atglobalreset,but
apulseonthelocalreset(rst)canchangeitsvalueto0.
LocalReset/GlobalResetVHDLCodingExample
Thefollowingcodingexamplesetstheinitialvalueontheregisteroutputto1(one)at
initialpowerup,butsincethisisdependentuponalocalreset,thevaluechangesto0
(zero)wheneverthelocalset/resetisactivated.
entitytopis
Port(
clk,rst:instd_logic;
a_in:instd_logic;
dout:outstd_logic);
endtop;
architectureBehavioraloftopis
signalarb_onebit:std_logic:=’1’;
begin
process(clk,rst)
begin
ifrst=’1’then
arb_onebit<=’0’;
elsif(clk’eventandclk=’1’)then
arb_onebit<=a_in;
endif;
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endprocess;
dout<=arb_onebit;
endBehavioral;
DefaultInitialValuesonMemoryElementsinVHDL
BecauseeverymemoryelementinaXilinx®FPGAdevicemustcomeupinaknown
state,incertaincases,XSTdoesnotuseIEEEstandardsforinitialvalues.IntheLocal
Reset/GlobalResetVHDLCodingExample,ifsignalarb_onebitwerenotinitialized
to1(one),XSTwouldassignitadefaultof0(zero)asitsinitialstate.Inthiscase,XST
doesnotfollowtheIEEEstandard,whereUisthedefaultforstd_logic.Thisprocessof
initializationisthesameforbothregistersandRAMs.
Wherepossible,XSTadherestotheIEEEVHDLstandardwheninitializingsignal
values.IfnoinitialvaluesaresuppliedintheVHDLcode,XSTusesthedefaultvalues
(wherepossible)asshownintheXSTcolumninthefollowingtable.
TypeIEEEXST
bit’0’’0’
std_logic’U’’0’
bit_vector(3downto0)00000000
std_logic_vector(3downto0)00000000
integer(unconstrained)integer’leftinteger’left
integerrange7downto0integer’left=7integer’left=7(codedas111)
integerrange0to7integer’left=0integer’left=0(codedas000)
BooleanFALSEFALSE(codedas0)
enum(S0,S1,S2,S3)type’left=S0type’left=S0(codedas000)
UnconnectedoutputportsdefaulttothevaluesshownintheXSTcolumnofVHDL
InitialValues.Iftheoutputporthasaninitialcondition,XSTtiestheunconnected
outputporttotheexplicitlydenedinitialcondition.AccordingtotheIEEEVHDL
specication,inputportscannotbeleftunconnected.Asaresult,XSTissuesanerror
messageifaninputportisnotconnected.Eventheopenkeywordisnotsufcient
foranunconnectedinputport.
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VHDLObjects
ThissectiondiscussesVHDLObjects,andinclude:
•SignalsinVHDL
•VariablesinVHDL
•ConstantsinVHDL
SignalsinVHDL
SignalsinVHDLcanbe:
•Declaredinanarchitecturedeclarativepart.
•Usedanywherewithinthearchitecture.
•Declaredinablock.
•Usedwithinthatblock.
•Assignedbytheassignmentoperator<=.
CodingExample
signalsig1:std_logic;sig1<=’1’;
VariablesinVHDL
VariablesinVHDL:
•Aredeclaredinaprocessorasubprogram.
•Areusedwithinthatprocessorthatsubprogram.
•Canbeassignedbytheassignmentoperator:
:=
CodingExample
variablevar1:std_logic_vector(7downto0);var1:="01010011";
ConstantsinVHDL
ConstantsinVHDL:
•Canbedeclaredinanydeclarativeregion.
•Canbeusedwithinthatregion.
•Cannothavetheirvaluesbechangedoncedeclared.
CodingExample
signalsig1:std_logic_vector(5downto0);
constantinit0:std_logic_vector(5downto0):="010111";
sig1<=init0;
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VHDLOperators
SupportedoperatorsarelistedinVHDLExpressions.Thissectionprovidescoding
examplesforeachshiftoperator.
ShiftLeftLogicalVHDLCodingExample
sll(ShiftLeftLogical)sig1<=A(4downto0)sll2
logicallyequivalentto:
sig1<=A(2downto0)&"00";
ShiftRightLogicalVHDLCodingExample
srl(ShiftRightLogical)sig1<=A(4downto0)srl2
logicallyequivalentto:
sig1<="00"&A(4downto2);
ShiftLeftArithmeticVHDLCodingExample
sla(ShiftLeftArithmetic)sig1<=A(4downto0)sla2
logicallyequivalentto:
sig1<=A(2downto0)&A(0)&A(0);
ShiftRightArithmeticVHDLCodingExample
sra(ShiftRightArithmetic)sig1<=A(4downto0)sra2
logicallyequivalentto:
sig1<=<=A(4)&A(4)&A(4downto2);
RotateLeftVHDLCodingExample
rol(RotateLeft)sig1<=A(4downto0)rol2
logicallyequivalentto:
sig1<=A(2downto0)&A(4downto3);
RotateRightVHDLCodingExample
ror(RotateRight)A(4downto0)ror2
logicallyequivalentto:
sig1<=A(1downto0)&A(4downto2);
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Chapter14:XSTVHDLLanguageSupport
VHDLEntityandArchitectureDescriptions
VHDLentityandarchitecturedescriptionsinclude:
•CircuitDescriptions
•EntityDeclarations
•ArchitectureDeclarations
•ComponentInstantiation
•RecursiveComponentInstantiation
•ComponentConguration
•GenericParameterDeclarations
•GenericandAttributeConict
VHDLCircuitDescriptions
AcircuitdescriptioninVHDLconsistsoftwoparts:
•Theinterface(deningtheI/Oports)
•Thebody
InVHDL:
•Theentitycorrespondstotheinterface
•Thearchitecturedescribesthebehavior
VHDLEntityDeclarations
TheI/Oportsofthecircuitaredeclaredintheentity.Eachporthas:
•Aname
•Amode
–in
–out
–inout
–buffer
•Atype(oneofthefollowingportsintheEntityandArchitectureDeclarationVHDL
CodingExample)
–A
–B
–C
–D
–E
Notmorethanone-dimensionalarraytypesareacceptedasports.
VHDLArchitectureDeclarations
Internalsignalsmaybedeclaredinthearchitecture.Eachinternalsignalhas:
•Aname
•Atype
SignalTasshownbelowinthefollowingcodingexample
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CodingExample
LibraryIEEE;
useIEEE.std_logic_1164.all;
entityEXAMPLEis
port(
A,B,C:instd_logic;
D,E:outstd_logic);
endEXAMPLE;
architectureARCHIofEXAMPLEis
signalT:std_logic;
begin
...
endARCHI;
VHDLComponentInstantiation
Structuraldescriptionsassembleseveralblocks,andallowtheintroductionofhierarchy
inadesign.
ConceptDescription
ComponentBuildingorbasicblock
PortComponentI/Oconnector
SignalCorrespondstoawirebetweencomponents
InVHDL,acomponentisrepresentedbyadesignentity .Thedesignentityisa
compositeconsistingoftheconceptsshowninthefollowingtable.
ConceptViewDescribes
EntitydeclarationExternalWhatcanbeseenfrom
theoutside,includingthe
componentports
ArchitecturebodyInternalThebehaviororthestructure
ofthecomponent
Theconnectionsbetweencomponentsarespeciedwithincomponentinstantiation
statements.Thesestatementsspecifyaninstanceofacomponentoccurringinsidean
architectureofanothercomponent.Eachcomponentinstantiationstatementislabeled
withanidentier.
Besidesnamingacomponentdeclaredinalocalcomponentdeclaration,acomponent
instantiationstatementcontainsanassociationlist--theparenthesizedlistfollowingthe
reservedwordportmap.Theassociationlistspecieswhichactualsignalsorportsare
associatedwithwhichlocalportsofthecomponentdeclaration.
XSTsupportsunconstrainedvectorsincomponentdeclarations.
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CodingExample
Thefollowingcodingexampleshowsthestructuraldescriptionofahalfadder
composedoffournand2components:
entityNAND2is
port(
A,B:inBIT;
Y:outBIT);
endNAND2;
architectureARCHIofNAND2is
begin
Y<=AnandB;
endARCHI;
entityHALFADDERis
port(
X,Y:inBIT;
C,S:outBIT);
endHALFADDER;
architectureARCHIofHALFADDERis
componentNAND2
port(
A,B:inBIT;
Y:outBIT);
endcomponent;
forall:NAND2useentitywork.NAND2(ARCHI);
signalS1,S2,S3:BIT;
begin
NANDA:NAND2portmap(X,Y,S3);
NANDB:NAND2portmap(X,S3,S1);
NANDC:NAND2portmap(S3,Y,S2);
NANDD:NAND2portmap(S1,S2,S);
C<=S3;
endARCHI;
SynthesizedTopLevelNetlistDiagram
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VHDLRecursiveComponentInstantiation
XSTsupportsrecursivecomponentinstantiation.Directinstantiationisnotsupported
forrecursion.Topreventendlessrecursivecalls,thenumberofrecursionsislimited
bydefaultto64.Use-recursion_iteration_limittocontrolthenumberofallowed
recursivecalls.
4-BitShiftRegisterWithRecursiveComponentInstantiationVHDLCoding
Example
libraryieee;
useieee.std_logic_1164.all;
libraryunisim;
useunisim.vcomponents.all;
entitysingle_stageis
generic(sh_st:integer:=4);
port(
CLK:instd_logic;
DI:instd_logic;
DO:outstd_logic);
endentitysingle_stage;
architecturerecursiveofsingle_stageis
componentsingle_stage
generic(sh_st:integer);
port(
CLK:instd_logic;
DI:instd_logic;
DO:outstd_logic);
endcomponent;
signaltmp:std_logic;
begin
GEN_FD_LAST:ifsh_st=1generate
inst_fd:FDportmap(D=>DI,C=>CLK,Q=>DO);
endgenerate;
GEN_FD_INTERM:ifsh_st/=1generate
inst_fd:FDportmap(D=>DI,C=>CLK,Q=>tmp);
inst_sstage:single_stagegenericmap(sh_st=>sh_st-1)
portmap(DI=>tmp,CLK=>CLK,DO=>DO);
endgenerate;
endrecursive;
VHDLComponentConfiguration
Associatinganentityandarchitecturepairtoacomponentinstanceprovidesthemeans
oflinkingcomponentswiththeappropriatemodel(entityandarchitecturepair).
XSTsupportscomponentcongurationinthedeclarativepartofthearchitecture:
forinstantiation_list:component_nameuseLibName.entity_Name(Architecture_Name);
CodingExample
Thefollowingcodingexampleshowshowtouseacongurationclauseforcomponent
instantiation.Theexamplecontainsaforallstatement.
forall:NAND2useentitywork.NAND2(ARCHI);
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ThisstatementindicatesthatallNAND2componentsusetheentityNAND2and
ArchitectureARCHI.
Whenthecongurationclauseismissingforacomponentinstantiation,XSTlinksthe
componenttotheentitywiththesamename(andsameinterface)andtheselected
architecturetothemostrecentlycompiledarchitecture.Ifnoentityorarchitectureis
found,ablackboxisgeneratedduringsynthesis.
Incommandlinemode,youmayalsouseadedicatedcongurationdeclarationtolink
componentinstantiationsinyourdesigntodesignentitiesandarchitectures.Inthiscase,
thevalueofthemandatoryTopModuleName(-top)optionintheruncommandisthe
congurationnameinsteadofthetoplevelentityname.
VHDLGenericParameterDeclarations
TheGenerics(-generics)VHDLcommandlineoptionallowsyoutoredenegenerics
valuesdenedinthetop-leveldesignblock.Thisallowsyoutoeasilymodifythe
designcongurationwithoutanyHardwareDescriptionLanguage(HDL)source
modications,suchasforIPcoregenerationandtestingows.
Genericparametersmaybedeclaredintheentitydeclarationpart.XSTsupportsall
typesforgenericsincluding,forexample:
•Integer
•Boolean
•String
•Real
•std_logic_vector
Anexampleofusinggenericparametersissettingthewidthofthedesign.
CodingExample
Bydescribingcircuitswithgenericports,thesamecomponentcanbeinstantiated
repeatedlywithdifferentvaluesofgenericportsasshowninthefollowingcoding
example.
LibraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.std_logic_unsigned.all;
entityaddernis
generic(width:integer:=8);
port(
A,B:instd_logic_vector(width-1downto0);
Y:outstd_logic_vector(width-1downto0));
endaddern;
architecturebhvofaddernis
begin
Y<=A+B;
endbhv;
LibraryIEEE;
useIEEE.std_logic_1164.all;
entitytopis
port(
X,Y,Z:instd_logic_vector(12downto0);
A,B:instd_logic_vector(4downto0);
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S:outstd_logic_vector(16downto0));
endtop;
architecturebhvoftopis
componentaddern
generic(width:integer:=8);
port(
A,B:instd_logic_vector(width-1downto0);
Y:outstd_logic_vector(width-1downto0));
endcomponent;
forall:addernuseentitywork.addern(bhv);
signalC1:std_logic_vector(12downto0);
signalC2,C3:std_logic_vector(16downto0);
begin
U1:adderngenericmap(n=>13)portmap(X,Y,C1);
C2<=C1&A;
C3<=Z&B;
U2:adderngenericmap(n=>17)portmap(C2,C3,S);
endbhv;
VHDLGenericandAttributeConflicts
Sincegenericsandattributescanbeappliedtobothinstancesandcomponentsinthe
VHDLcode,andattributescanalsobespeciedinaconstraintsle,fromtimetotime,
conictsmayarise.Toresolvetheseconicts,XSTusesthefollowingrulesofprecedence:
1.Whateverisspeciedonaninstance(lowerlevel)takesprecedenceoverwhatis
speciedonacomponent(higherlevel).
2.Ifagenericandanattributearespeciedoneitherthesameinstanceorthesame
component,thegenerictakesprecedence,andXSTissuesamessagewarningofthe
conict.
3.AnattributespeciedintheXSTConstraintFile(XCF)alwaystakesprecedenceover
attributesorgenericsspeciedintheVHDLcode.
Whenanattributespeciedonaninstanceoverridesagenericspeciedonacomponent
inXST,itispossiblethatyoursimulationtoolmayneverthelessusethegeneric.This
maycausethesimulationresultstonotmatchthesynthesisresults.
PrecedenceinVHDL
GenericonanInstanceGenericonaComponent
AttributeonanInstanceApplyGeneric(XSTissues
warning)
ApplyAttribute(possible
simulationmismatch)
AttributeonaComponentApplyGenericApplyGeneric(XSTissues
warning)
AttributeinXCFApplyAttributeXSTissues
warning)
ApplyAttribute
Securityattributesontheblockdenitionalwayshavehigherprecedencethanany
otherattributeorgeneric.
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VHDLCombinatorialCircuits
XSTsupportsthefollowingVHDLcombinatorialcircuits:
•ConcurrentSignalAssignments
•GenerateStatements
•CombinatorialProcesses
•If...ElseStatements
•CaseStatements
•For...LoopStatements
VHDLConcurrentSignalAssignments
CombinatoriallogicinVHDLmaybedescribedusingconcurrentsignalassignments.
Thesecanbedenedwithinthebodyofthearchitecture.VHDLoffersthreetypesof
concurrentsignalassignments:
•Simple
•Selected
•Conditional
Youcandescribeasmanyconcurrentstatementsasneeded.Theorderofconcurrent
signaldenitioninthearchitectureisirrelevant.
Aconcurrentassignmentconsistsoftwosides:
•Left-hand
•Right-hand
Theassignmentchangeswhenanysignalintherightsidechanges.Inthiscase,the
resultisassignedtothesignalontheleftside.
SimpleSignalAssignmentVHDLCodingExample
T<=AandB;
MUXDescriptionUsingSelectedSignalAssignmentVHDLCodingExample
libraryIEEE;
useIEEE.std_logic_1164.all;
entityselect_bhvis
generic(width:integer:=8);
port(
a,b,c,d:instd_logic_vector(width-1downto0);
selector:instd_logic_vector(1downto0);
T:outstd_logic_vector(width-1downto0));
endselect_bhv;
architecturebhvofselect_bhvis
begin
withselectorselect
T<=awhen"00",
bwhen"01",
cwhen"10",
dwhenothers;
endbhv;
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MUXDescriptionUsingConditionalSignalAssignmentVHDLCoding
Example
entitywhen_entis
generic(width:integer:=8);
port(
a,b,c,d:instd_logic_vector(width-1downto0);
selector:instd_logic_vector(1downto0);
T:outstd_logic_vector(width-1downto0));
endwhen_ent;
architecturebhvofwhen_entis
begin
T<=awhenselector="00"else
bwhenselector="01"else
cwhenselector="10"else
d;
endbhv;
VHDLGenerateStatements
RepetitivestructuresaredeclaredwiththegenerateVHDLstatement.Forthispurpose,
forIin1toNgeneratemeansthatthebitslicedescriptionisrepeatedNtimes.
8-BitAdderDescribedWithFor...GenerateStatementVHDLCoding
Example
Thefollowingcodingexampledescribesan8-bitadderbydeclaringthebitslice
structure.
entityEXAMPLEis
port(
A,B:inBIT_VECTOR(0to7);
CIN:inBIT;
SUM:outBIT_VECTOR(0to7);
COUT:outBIT);
endEXAMPLE;
architectureARCHIofEXAMPLEis
signalC:BIT_VECTOR(0to8);
begin
C(0)<=CIN;
COUT<=C(8);
LOOP_ADD:forIin0to7generate
SUM(I)<=A(I)xorB(I)xorC(I);
C(I+1)<=(A(I)andB(I))or(A(I)andC(I))or(B(I)andC(I));
endgenerate;
endARCHI;
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N-BitAdderDescribedWithIf...GenerateandFor…GenerateStatement
VHDLCodingExample
XSTsupportstheifconditiongeneratestatementforstatic(non-dynamic)conditions.
ThefollowingcodingexampleshowsagenericN-bitadderwithawidthranging
between4and32.
entityEXAMPLEis
generic(N:INTEGER:=8);
port(
A,B:inBIT_VECTOR(Ndownto0);
CIN:inBIT;
SUM:outBIT_VECTOR(Ndownto0);
COUT:outBIT);
endEXAMPLE;
architectureARCHIofEXAMPLEis
signalC:BIT_VECTOR(N+1downto0);
begin
L1:if(N>=4andN<=32)generate
C(0)<=CIN;
COUT<=C(N+1);
LOOP_ADD:forIin0toNgenerate
SUM(I)<=A(I)xorB(I)xorC(I);
C(I+1)<=(A(I)andB(I))or(A(I)andC(I))or(B(I)andC(I));
endgenerate;
endgenerate;
endARCHI;
VHDLCombinatorialProcesses
Aprocessassignsvaluestosignalsdifferentlythanwhenusingconcurrentsignal
assignments.Thevalueassignmentsaremadeinasequentialmode.Laterassignments
maycancelpreviousones.SeeAssignmentsinaProcessVHDLCodingExample.Firstthe
signalSisassignedto0,butlateron(for(AandB)=1),thevalueforSischangedto1.
Aprocessiscombinatorialwhenitsinferredhardwaredoesnotinvolveanymemory
elements.Saiddifferently,whenallassignedsignalsinaprocessarealwaysexplicitly
assignedinallpathsoftheProcessstatements,theprocessiscombinatorial.
Acombinatorialprocesshasasensitivitylistappearingwithinparenthesesafterthe
wordprocess.Aprocessisactivatedifanevent(valuechange)appearsononeofthe
sensitivitylistsignals.Foracombinatorialprocess,thissensitivitylistmustcontain:
•Allsignalsinconditions(forexample,ifandcase)
•Allsignalsontheright-handsideofanassignment
Ifoneormoresignalsaremissingfromthesensitivitylist,XSTissuesawarningmessage
forthemissingsignalsandaddsthemtothesensitivitylist.Inthiscase,theresultofthe
synthesismaybedifferentfromtheinitialdesignspecication.
Aprocessmaycontainlocalvariables.Thevariablesarehandledinasimilarmanner
assignals(butarenot,ofcourse,outputstothedesign).
InCombinatorialProcessVHDLCodingExampleOne,avariablenamedAUXisdeclaredin
thedeclarativepartoftheprocess,andisassignedtoavalue(with:=)inthestatement
partoftheprocess.
Incombinatorialprocesses,ifasignalisnotexplicitlyassignedinallbranchesofifor
casestatements,XSTgeneratesalatchtoholdthelastvalue.Toavoidlatchcreation,
ensurethatallassignedsignalsinacombinatorialprocessarealwaysexplicitlyassigned
inallpathsoftheProcessstatements.
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Differentstatementscanbeusedinaprocess:
•Variableandsignalassignment
•Ifstatement
•Casestatement
•For...Loopstatement
•Functionandprocedurecall
AssignmentsinaProcessVHDLCodingExample
entityEXAMPLEis
port(
A,B:inBIT;
S:outBIT);
endEXAMPLE;
architectureARCHIofEXAMPLEis
begin
process(A,B)
begin
S<=’0’;
if((AandB)=’1’)then
S<=’1’;
endif;
endprocess;
endARCHI;
CodingExampleOne
libraryASYL;
useASYL.ARITH.all;
entityADDSUBis
port(
A,B:inBIT_VECTOR(3downto0);
ADD_SUB:inBIT;
S:outBIT_VECTOR(3downto0));
endADDSUB;
architectureARCHIofADDSUBis
begin
process(A,B,ADD_SUB)
variableAUX:BIT_VECTOR(3downto0);
begin
ifADD_SUB=’1’then
AUX:=A+B;
else
AUX:=A-B;
endif;
S<=AUX;
endprocess;
endARCHI;
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CodingExampleTwo
entityEXAMPLEis
port(
A,B:inBIT;
S:outBIT);
endEXAMPLE;
architectureARCHIofEXAMPLEis
begin
process(A,B)
variableX,Y:BIT;
begin
X:=AandB;
Y:=BandA;
ifX=Ythen
S<=’1’;
endif;
endprocess;
endARCHI;
VHDLIf...ElseStatements
If...elsestatements:
•Usetrueandfalseconditionstoexecutestatements.
•Maybenested.
•Maybeexecutedinablockofmultiplestatementsusingbeginandendkeywords.
ExpressionEvaluatesToStatementExecuted
trueFirststatement
falseelsestatement
xelsestatement
zelsestatement
CodingExample
libraryIEEE;
useIEEE.std_logic_1164.all;
entitymux4is
port(
a,b,c,d:instd_logic_vector(7downto0);
sel1,sel2:instd_logic;
outmux:outstd_logic_vector(7downto0));
endmux4;
architecturebehaviorofmux4is
begin
process(a,b,c,d,sel1,sel2)
begin
if(sel1=’1’)then
if(sel2=’1’)then
outmux<=a;
else
outmux<=b;
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endif;
else
if(sel2=’1’)then
outmux<=c;
else
outmux<=d;
endif;
endif;
endprocess;
endbehavior;
VHDLCaseStatements
Casestatementsperformacomparisontoanexpressiontoevaluateoneofanumber
ofparallelbranches.Thecasestatementevaluatesthebranchesintheordertheyare
written.Therstbranchthatevaluatestotrueisexecuted.Ifnoneofthebranches
match,thedefaultbranchisexecuted.
VHDLCaseStatementCodingExample
libraryIEEE;
useIEEE.std_logic_1164.all;
entitymux4is
port(
a,b,c,d:instd_logic_vector(7downto0);
sel:instd_logic_vector(1downto0);
outmux:outstd_logic_vector(7downto0));
endmux4;
architecturebehaviorofmux4is
begin
process(a,b,c,d,sel)
begin
caseselis
when"00"=>outmux<=a;
when"01"=>outmux<=b;
when"10"=>outmux<=c;
whenothers=>outmux<=d;--casestatement
--mustbecomplete
endcase;
endprocess;
endbehavior;
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VHDLFor...LoopStatements
XSTsupportstheforstatementfor:
•Constantbounds
•Stoptestconditionusinganyofthefollowingoperators:
–<
–<=
–>
–>=
•Nextstepcomputationfallingwithinoneofthefollowingspecications:
–var=var+step
–var=var-step
where
♦varistheloopvariable
♦stepisaconstantvalue
•Nextandexitstatements
VHDLFor...LoopStatementCodingExample
libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.std_logic_unsigned.all;
entitycountzerosis
port(
a:instd_logic_vector(7downto0);
Count:outstd_logic_vector(2downto0));
endmux4;
architecturebehaviorofmux4is
signalCount_Aux:std_logic_vector(2downto0);
begin
process(a)
begin
Count_Aux<="000";
foriina’rangeloop
if(a[i]=’0’)then
Count_Aux<=Count_Aux+1;--operator"+"defined
--instd_logic_unsigned
endif;
endloop;
Count<=Count_Aux;
endprocess;
endbehavior;
VHDLSequentialCircuits
Sequentialcircuitscanbedescribedusingsequentialprocesses.XSTallows:
•VHDLSequentialProcessWithaSensitivityList
•VHDLSequentialProcessWithoutaSensitivityList
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VHDLSequentialProcessWithaSensitivityList
Aprocessissequentialwhenitisnotacombinatorialprocess.Inotherwords,aprocess
issequentialwhensomeassignedsignalsarenotexplicitlyassignedinallpathsof
thestatements.Inthiscase,thehardwaregeneratedhasaninternalstateormemory
(ip-opsorlatches).
Thefollowingcodingexampleprovidesatemplatefordescribingsequentialcircuits.
Formoreinformation,see:
XSTHDLCodingTechniques
Thistopicdescribesmacroinference(forexample,registersandcounters).
CodingExample
Declareasynchronoussignalsinthesensitivitylist.Otherwise,XSTissuesawarning
andaddsthemtothesensitivitylist.Inthiscase,thebehaviorofthesynthesisresult
maybedifferentfromtheinitialspecication.
process(CLK,RST)...
begin
ifRST=<’0’|’1’>then
--anasynchronouspartmayappearhere
--optionalpart
.......
elsif<CLK’EVENT|notCLK’STABLE>
andCLK=<’0’|’1’>then
--synchronouspart
--sequentialstatementsmayappearhere
endif;
endprocess;
VHDLSequentialProcessWithoutaSensitivityList
SequentialprocesseswithoutasensitivitylistmustcontainaWaitstatement.TheWait
statementmustbetherststatementoftheprocess.TheconditionintheWaitstatement
mustbeaconditionontheclocksignal.SeveralWaitstatementsinthesameprocessare
accepted,butasetofspecicconditionsmustberespected.
Formoreinformation,see:
VHDLMultipleWaitStatementsDescriptions
Anasynchronouspartcannotbespeciedwithinprocesseswithoutasensitivitylist.
VHDLSequentialProcessWithoutaSensitivityListCodingExample
ThefollowingVHDLcodingexampleshowstheskeletonoftheprocessdescribedinthis
section.Theclockconditionmaybeafallingorarisingedge.
process...
begin
waituntil<CLK’EVENT|notCLK’STABLE>andCLK=<’0’|’1’>;
...--asynchronouspartmaybespecifiedhere.
endprocess;
XSTdoesnotsupportclockandclockenabledescriptionswithinthesameWait
statement.Instead,codethesedescriptionsasshowninClockandClockEnable(Supported)
VHDLCodingExample.
XSTdoesnotsupportWaitstatementsforlatchdescriptions.
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ClockandClockEnable(NotSupported)VHDLCodingExample
Caution!ThiscodingstyleisNOTsupported.
waituntilCLOCK’eventandCLOCK=’0’andENABLE=’1’;
ClockandClockEnable(Supported)VHDLCodingExample
"8BitCounterDescriptionUsingaProcesswithaSensitivityList"ifENABLE=’1’then...
RegisterandCounterDescriptionsVHDLCodingExamples
Codingexamplescanbedownloadedintextformatfrom
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
8-BitRegisterDescriptionUsingaProcessWithaSensitivityListVHDL
CodingExample
entityEXAMPLEis
port(
DI:inBIT_VECTOR(7downto0);
CLK:inBIT;
DO:outBIT_VECTOR(7downto0));
endEXAMPLE;
architectureARCHIofEXAMPLEis
begin
process(CLK)
begin
ifCLK’EVENTandCLK=’1’then
DO<=DI;
endif;
endprocess;
endARCHI;
8BitRegisterDescriptionUsingaProcessWithoutaSensitivityList
ContainingaWaitStatementVHDLCodingExample
entityEXAMPLEis
port(
DI:inBIT_VECTOR(7downto0);
CLK:inBIT;
DO:outBIT_VECTOR(7downto0));
endEXAMPLE;
architectureARCHIofEXAMPLEis
begin
processbegin
waituntilCLK’EVENTandCLK=’1’;
DO<=DI;
endprocess;
endARCHI;
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8-BitRegisterWithClockSignalandAsynchronousResetSignalVHDL
CodingExample
entityEXAMPLEis
port(
DI:inBIT_VECTOR(7downto0);
CLK:inBIT;
RST:inBIT;
DO:outBIT_VECTOR(7downto0));
endEXAMPLE;
architectureARCHIofEXAMPLEis
begin
process(CLK,RST)
begin
ifRST=’1’then
DO<="00000000";
elsifCLK’EVENTandCLK=’1’then
DO<=DI;
endif;
endprocess;
endARCHI;
8-BitCounterDescriptionUsingaProcessWithaSensitivityListVHDL
CodingExample
libraryASYL;
useASYL.PKG_ARITH.all;
entityEXAMPLEis
port(
CLK:inBIT;
RST:inBIT;
DO:outBIT_VECTOR(7downto0));
endEXAMPLE;
architectureARCHIofEXAMPLEis
begin
process(CLK,RST)
variableCOUNT:BIT_VECTOR(7downto0);
begin
ifRST=’1’then
COUNT:="00000000";
elsifCLK’EVENTandCLK=’1’then
COUNT:=COUNT+"00000001";
endif;
DO<=COUNT;
endprocess;
endARCHI;
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VHDLMultipleWaitStatementsDescriptions
SequentialcircuitscanbedescribedinVHDLwithmultiplewaitstatementsinaprocess.
Followtheseruleswhenusingmultiplewaitstatements:
•Theprocesscontainsonlyoneloopstatement.
•Therststatementintheloopisawaitstatement.
•Aftereachwaitstatement,anextorexitstatementisdened.
•Theconditioninthewaitstatementsisthesameforeachwaitstatement.
•Thisconditionuseonlyonesignal—theclocksignal.
•Thisconditionhasthefollowingform:
"wait[onclock_signal]until[(clock_signal’EVENT|notclock_signal’STABLE)and]
clock_signal={’0’|’1’};"
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Chapter14:XSTVHDLLanguageSupport
CodingExample
ThefollowingVHDLcodingexampleusesmultiplewaitstatements.Thisexample
describesasequentialcircuitperformingfourdifferentoperationsinsequence.
Thedesigncycleisdelimitedbytwosuccessiverisingedgesoftheclocksignal.A
synchronousresetisdenedprovidingawaytorestartthesequenceofoperationsat
thebeginning.Thesequenceofoperationsconsistsofassigningeachofthefollowing
fourinputstotheoutputRESULT:
•DATA1
•DATA2
•DATA3
•DATA4
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
entityEXAMPLEis
port(
DATA1,DATA2,DATA3,DATA4:inSTD_LOGIC_VECTOR(3downto0);
RESULT:outSTD_LOGIC_VECTOR(3downto0);
CLK:inSTD_LOGIC;
RST:inSTD_LOGIC);
endEXAMPLE;
architectureARCHofEXAMPLEis
begin
processbegin
SEQ_LOOP:loop
waituntilCLK’EVENTandCLK=’1’;
exitSEQ_LOOPwhenRST=’1’;
RESULT<=DATA1;
waituntilCLK’EVENTandCLK=’1’;
exitSEQ_LOOPwhenRST=’1’;
RESULT<=DATA2;
waituntilCLK’EVENTandCLK=’1’;
exitSEQ_LOOPwhenRST=’1’;
RESULT<=DATA3;
waituntilCLK’EVENTandCLK=’1’;
exitSEQ_LOOPwhenRST=’1’;
RESULT<=DATA4;
endloop;
endprocess;
endARCH;
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Chapter14:XSTVHDLLanguageSupport
VHDLFunctionsandProcedures
ThedeclarationofafunctionoraprocedureinVHDLprovidesamechanismfor
handlingblocksusedmultipletimesinadesign.Functionsandprocedurescanbe
declaredinthedeclarativepartofanentity,inanarchitectureorinpackages.The
headingpartcontains:
•Inputparametersforfunctionsandinput
•Outputandinoutparametersforprocedures.
Theseparameterscanbeunconstrained.Theyarenotconstrainedtoagivenbound.The
contentissimilartothecombinatorialprocesscontent.
ResolutionfunctionsarenotsupportedexcepttheonedenedintheIEEEstd_logic_1164
package.
FunctionDeclarationandFunctionCallVHDLCodingExample
ThefollowingVHDLcodingexampleshowsafunctiondeclaredwithinapackage.The
ADDfunctiondeclaredhereisasinglebitadder.Thisfunctioniscalledfourtimeswith
theproperparametersinthearchitecturetocreatea4-bitadder.Thesameexampleusing
aprocedureisshowninProcedureDeclarationandProcedureCallVHDLCodingExample.
packagePKGis
functionADD(A,B,CIN:BIT)
returnBIT_VECTOR;
endPKG;
packagebodyPKGis
functionADD(A,B,CIN:BIT)
returnBIT_VECTORis
variableS,COUT:BIT;
variableRESULT:BIT_VECTOR(1downto0);
begin
S:=AxorBxorCIN;
COUT:=(AandB)or(AandCIN)or(BandCIN);
RESULT:=COUT&S;
returnRESULT;
endADD;
endPKG;
usework.PKG.all;
entityEXAMPLEis
port(
A,B:inBIT_VECTOR(3downto0);
CIN:inBIT;
S:outBIT_VECTOR(3downto0);
COUT:outBIT);
endEXAMPLE;
architectureARCHIofEXAMPLEis
signalS0,S1,S2,S3:BIT_VECTOR(1downto0);
begin
S0<=ADD(A(0),B(0),CIN);
S1<=ADD(A(1),B(1),S0(1));
S2<=ADD(A(2),B(2),S1(1));
S3<=ADD(A(3),B(3),S2(1));
S<=S3(0)&S2(0)&S1(0)&S0(0);
COUT<=S3(1);
endARCHI;
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ProcedureDeclarationandProcedureCallVHDLCodingExample
packagePKGis
procedureADD(
A,B,CIN:inBIT;
C:outBIT_VECTOR(1downto0));
endPKG;
packagebodyPKGis
procedureADD(
A,B,CIN:inBIT;
C:outBIT_VECTOR(1downto0)
)is
variableS,COUT:BIT;
begin
S:=AxorBxorCIN;
COUT:=(AandB)or(AandCIN)or(BandCIN);
C:=COUT&S;
endADD;
endPKG;
usework.PKG.all;
entityEXAMPLEis
port(
A,B:inBIT_VECTOR(3downto0);
CIN:inBIT;
S:outBIT_VECTOR(3downto0);
COUT:outBIT);
endEXAMPLE;
architectureARCHIofEXAMPLEis
begin
process(A,B,CIN)
variableS0,S1,S2,S3:BIT_VECTOR(1downto0);
begin
ADD(A(0),B(0),CIN,S0);
ADD(A(1),B(1),S0(1),S1);
ADD(A(2),B(2),S1(1),S2);
ADD(A(3),B(3),S2(1),S3);
S<=S3(0)&S2(0)&S1(0)&S0(0);
COUT<=S3(1);
endprocess;
endARCHI;
RecursiveFunctionVHDLCodingExample
XSTsupportsrecursivefunctions.Thefollowingcodingexamplerepresentsn!function:
functionmy_func(x:integer)returnintegeris
begin
ifx=1then
returnx;
else
return(x*my_func(x-1));
endif;
endfunctionmy_func;
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VHDLAssertStatements
XSTsupportsVHDLAssertstatements.Assertstatementsenableyoutodetect
undesirableconditionsinVHDLdesigns,suchasbadvaluesfor:
•conditions:
–generics
–constants
–generate
•parametersincalledfunctions
ForanyfailedconditioninanAssertstatement,XST(dependingontheseveritylevel)
either:
•Issuesawarningmessage,or
•Rejectsthedesignandissuesanerrormessage.
XSTsupportstheAssertstatementonlywithstaticcondition.
CodingExample
ThefollowingcodingexamplecontainsablockSINGLE_SRLwhichdescribesashift
register.ThesizeoftheshiftregisterdependsontheSRL_WIDTHgenericvalue.The
Assertstatementensuresthattheimplementationofasingleshiftregisterdoesnot
exceedthesizeofasingleShiftRegisterLUT(SRL).
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SincethesizeoftheSRLis16bit,andXSTimplementsthelaststageoftheshiftregister
usingaip-opinaslice,thenthemaximumsizeoftheshiftregistercannotexceed17
bits.TheSINGLE_SRLblockisinstantiatedtwiceintheentitynamedTOP:
•rstwithSRL_WIDTHequalto13
•secondwithSRL_WIDTHequalto18
libraryieee;
useieee.std_logic_1164.all;
entitySINGLE_SRLis
generic(SRL_WIDTH:integer:=16);
port(
clk:instd_logic;
inp:instd_logic;
outp:outstd_logic);
endSINGLE_SRL;
architecturebehofSINGLE_SRLis
signalshift_reg:std_logic_vector(SRL_WIDTH-1downto0);
begin
assertSRL_WIDTH<=17
report"ThesizeofShiftRegisterexceedsthesizeofasingleSRL"
severityFAILURE;
process(clk)
begin
if(clk’eventandclk=’1’)then
shift_reg<=shift_reg(SRL_WIDTH-1downto1)&inp;
endif;
endprocess;
outp<=shift_reg(SRL_WIDTH-1);
endbeh;
libraryieee;
useieee.std_logic_1164.all;
entityTOPis
port(
clk:instd_logic;
inp1,inp2:instd_logic;
outp1,outp2:outstd_logic);
endTOP;
architecturebehofTOPis
componentSINGLE_SRLis
generic(SRL_WIDTH:integer:=16);
port(
clk:instd_logic;
inp:instd_logic;
outp:outstd_logic);
endcomponent;
begin
inst1:SINGLE_SRLgenericmap(SRL_WIDTH=>13)
portmap(
clk=>clk,
inp=>inp1,
outp=>outp1);
inst2:SINGLE_SRLgenericmap(SRL_WIDTH=>18)
portmap(
clk=>clk,
inp=>inp2,
outp=>outp2);
endbeh;
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ErrorMessage
Ifyourunthecodingexampleabove,XSTissuesthefollowingerrormessage:
...
================================================================
*HDLAnalysis*
================================================================
AnalyzingEntity<top>(Architecture<beh>).
Entity<top>analyzed.Unit<top>generated.
AnalyzinggenericEntity<single_srl>(Architecture<beh>).
SRL_WIDTH=13
Entity<single_srl>analyzed.Unit<single_srl>generated.
AnalyzinggenericEntity<single_srl>(Architecture<beh>).
SRL_WIDTH=18
ERROR:Xst-assert_1.vhdline15:FAILURE:
ThesizeofShiftRegisterexceedsthesizeofasingleSRL
...
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Chapter14:XSTVHDLLanguageSupport
VHDLModelsDefinedUsingPackages
ThissectiondiscussesVHDLModelsDenedUsingPackages,andincludes:
•AboutVHDLModelsDenedUsingPackages
•UsingStandardPackagestoDeneVHDLModels
•UsingIEEEPackagestoDeneVHDLModels
•UsingSynopsysPackagestoDeneVHDLModels
AboutVHDLModelsDefinedUsingPackages
VHDLmodelsmaybedenedusingpackages.Packagescontain:
•Typeandsubtypedeclarations
•Constantdenitions
•Functionandproceduredenitions
•Componentdeclarations
UsingpackagestodeneVHDLmodelsprovidestheabilitytochangeparametersand
constantsofthedesign,suchasconstantvaluesandfunctiondenitions.
Packagesmaycontaintwodeclarativeparts:
•Bodydeclaration
•Packagedeclaration
Thebodydeclarationincludesthedescriptionoffunctionbodiesdeclaredinthepackage
declaration.
librarylib_pack;
--lib_packisthenameofthelibraryspecified
--wherethepackagehasbeencompiled(workbydefault)
uselib_pack.pack_name.all;
--pack_nameisthenameofthedefinedpackage.
XSTalsosupportspredenedpackages.Thesepackagesarepre-compiledandcanbe
includedinVHDLdesigns.Thesepackagesareintendedforuseduringsynthesis,but
mayalsobeusedforsimulation.
UsingStandardPackagestoDefineVHDLModels
TheStandardpackage:
•Isincludedbydefault
•Containsbasictypes:
–bit
–bit_vector
–integer
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VHDLModelsDefinedUsingIEEEPackages
XSTsupportsthefollowingIEEEpackages:
•std_logic_1164
Supportsthefollowingtypes:
–std_logic
–std_ulogic
–std_logic_vector
–std_ulogic_vector
XSTalsosupportsconversionfunctionsbasedonthesetypes.
•numeric_bit
Supportsthefollowingtypesbasedontypebit:
–Unsignedvectors
–Signedvectors
XSTalsosupports:
♦Alloverloadedarithmeticoperatorsonthesetypes
♦Conversionandextendedfunctionsforthesetypes
•numeric_std
Supportsthefollowingtypesbasedontypestd_logic:
–Unsignedvectors
–Signedvectors
Thispackageisequivalenttostd_logic_arith.
•math_real
Supportsthefollowing:
–RealnumberconstantsasshowninVHDLRealNumberConstants
–RealnumberfunctionsasshowninVHDLRealNumberConstants
–Theprocedureuniform,whichgeneratessuccessivevaluesbetween0.0and1.0
VHDLRealNumberConstants
ConstantValueConstantValue
math_eemath_log_of_2ln2
math_1_over_e1/emath_log_of_10ln10
math_pimath_log2_of_elog2e
math_2_pimath_log10_of_elog10e
math_1_over_pimath_sqrt_2
math_pi_over_2math_1_oversqrt_2
math_pi_over_3math_sqrt_pi
math_pi_over_4math_deg_to_rad
math_3_pi_over_2math_rad_to_deg
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VHDLRealNumberFunctions
ceil(x)realmax(x,y)exp(x)cos(x)cosh(x)
oor(x)realmin(x,y)log(x)tan(x)tanh(x)
round(x)sqrt(x)log2(x)arcsin(x)arcsinh(x)
trunc(x)cbrt(x)log10(x)arctan(x)arccosh(x)
sign(x)"**"(n,y)log(x,y)arctan(y ,x)arctanh(x)
"mod"(x,y)"**"(x,y)sin(x)sinh(x)
Functionsandproceduresinthemath_realpackages,aswellastherealtype,arefor
calculationsonly.TheyarenotsupportedforsynthesisinXST.
CodingExample
libraryieee;
useIEEE.std_logic_signed.all;
signala,b,c:std_logic_vector(5downto0);
c<=a+b;
--thisoperator"+"isdefinedinpackagestd_logic_signed.
--Operandsareconvertedtosignedvectors,andfunction"+"
--definedinpackagestd_logic_arithiscalledwithsigned
--operands.
UsingSynopsysPackagestoDefineVHDLModels
ThefollowingSynopsyspackagesaresupportedintheIEEElibrary:
•std_logic_arith
Supportstypesunsigned,signedvectors,andalloverloadedarithmeticoperatorson
thesetypes.Italsodenesconversionandextendedfunctionsforthesetypes.
•std_logic_unsigned
Denesarithmeticoperatorsonstd_ulogic_vectorandconsidersthemasunsigned
operators.
•std_logic_signed
Denesarithmeticoperatorsonstd_logic_vectorandconsidersthemassigned
operators.
•std_logic_misc
Denessupplementaltypes,subtypes,constants,andfunctionsforthe
std_logic_1164package,suchas:
–and_reduce
–or_reduce
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Chapter14:XSTVHDLLanguageSupport
VHDLConstructsSupportedinXST
XSTsupportsthefollowingVHDLConstructs:
•DesignEntitiesandCongurations
•Expressions
•Statements
VHDLDesignEntitiesandConfigurations
NoteXSTdoesnotallowunderscoresastherstcharacterofsignalnames(for
example,_DATA_1).
XSTsupportsVHDLdesignentitiesandcongurationsexceptasshowninthefollowing
sections:
•VHDLEntityHeaders
•VHDLPackages
•VHDLPhysicalTypes
•VHDLModes
•VHDLDeclarations
•VHDLObjects
•VHDLSpecications
VHDLEntityHeaders
•Generics
Supported
•Ports
Supported
•EntityStatementPart
Partialsupport.Allowedstatementsinclude:
–Attributedeclarations
–Attributespecications
–Constantdeclarations
VHDLPackages
STANDARD
TypeTIMEisnotsupported
VHDLPhysicalTypes
•TIME
Ignored
•REAL
Supported,butonlyinfunctionsforconstantcalculations
VHDLModes
Linkage
Unsupported
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Chapter14:XSTVHDLLanguageSupport
VHDLDeclarations
Type
Supportedfor:
–enumeratedtypes
–typeswithpositiverangehavingconstantbounds
–bitvectortypes
–multi-dimensionalarrays
VHDLObjects
•ConstantDeclaration
Supportedexceptfordeferredconstant
•SignalDeclaration
Supportedexceptforregisterandbustypesignals
•AttributeDeclaration
Supportedforsomeattributes,otherwiseskipped
Formoreinformation,see:
XSTDesignConstraints
VHDLSpecifications
•Attribute
Supportedforsomepredenedattributesonly:
–HIGH
–LOW
–LEFT
–RIGHT
–RANGE
–REVERSE_RANGE
–LENGTH
–POS
–ASCENDING
–EVENT
–LAST_V ALUE
•Conguration
Supportedonlywiththeallclauseforinstanceslist.Ifnoclauseisadded,XSTlooks
fortheentityorarchitecturecompiledinthedefaultlibrary
•Disconnection
Unsupported
VHDLExpressions
XSTsupportsthefollowingexpressions:
•VHDLOperators
•VHDLOperands
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Chapter14:XSTVHDLLanguageSupport
VHDLOperators
OperatorSupported/Unsupported
LogicalOperators:
and,or,nand,nor,xor,xnor,not
Supported
RelationalOperators:
=,/=,<,<=,>,>=
Supported
&(concatenation)Supported
AddingOperators:+,-Supported
*Supported
/,remSupportediftherightoperandisaconstantpowerof2
modSupportediftherightoperandisaconstantpowerof2
ShiftOperators:
sll,srl,sla,sra,rol,ror
Supported
absSupported
**Onlysupportediftheleftoperandis2
Sign:+,-Supported
VHDLOperands
OperandSupported/Unsupported
AbstractLiteralsOnlyintegerliteralsaresupported
PhysicalLiteralsIgnored
EnumerationLiteralsSupported
StringLiteralsSupported
BitStringLiteralsSupported
RecordAggregatesSupported
ArrayAggregatesSupported
FunctionCallSupported
QualiedExpressionsSupportedforacceptedpredenedattributes
TypesConversionsSupported
AllocatorsUnsupported
StaticExpressionsSupported
VHDLStatements
XSTsupportsallVHDLstatementsexceptasshowninthefollowingsections:
•VHDLWaitStatements
•VHDLLoopStatements
•VHDLConcurrentStatements
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Chapter14:XSTVHDLLanguageSupport
VHDLWaitStatements
WaitStatementSupported/Unsupported
Waitonsensitivity_listuntilBoolean_expression.
Formoreinformation,see:
VHDLSequentialCircuits
Supportedwithonesignalinthesensitivitylistandinthe
Booleanexpression.IncaseofmultipleWaitstatements,
thesensitivitylistandtheBooleanexpressionmustbethe
sameforeachWaitstatement.
NoteXSTdoesnotsupportWaitstatementsforlatch
descriptions.
Waitfortime_expression...
Formoreinformation,see:
VHDLSequentialCircuits
Unsupported
AssertionStatementSupported(onlyforstaticconditions)
SignalAssignment
Statement
Supported(delayisignored)
VHDLLoopStatements
LoopStatementSupported/Unsupported
for...loop...endloopSupportedforconstantboundsonly.Disablestatements
arenotsupported.
loop...endloopOnlysupportedintheparticularcaseofmultipleWait
statements
VHDLConcurrentStatements
ConcurrentStatementSupported/Unsupported
ConcurrentSignal
AssignmentStatement
Supported(noafterclause,notransportorguardedoptions,
nowaveforms)UNAFFECTEDissupported.
For...GenerateStatementsupportedforconstantboundsonly
If...GenerateStatementsupportedforstaticconditiononly
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Chapter14:XSTVHDLLanguageSupport
VHDLReservedWords
absaccessafteralias
allandarchitecturearray
assertattributebeginblock
bodybufferbuscase
componentcongurationconstantdisconnect
downtoelseelsifend
entityexitlefor
functiongenerategenericgroup
guardedifimpurein
inertialinoutislabel
librarylinkageliteralloop
mapmodnandnew
nextnornotnull
ofonopenor
othersoutpackageport
postponedprocedureprocesspure
rangerecordregisterreject
remreportreturnrol
rorselectseveritysignal
sharedslasllsra
srlsubtypethento
transporttypeunaffectedunits
untilusevariablewait
whenwhilewithxnor
xor
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Chapter15
XSTVerilogLanguageSupport
ThischapterdiscussesXSTVerilogLanguageSupport,andincludes:
•AboutXSTVerilogLanguageSupport
•BehavioralVerilog
•VariablePartSelects
•StructuralVerilogFeatures
•VerilogParameters
•VerilogParameterandAttributeConicts
•VerilogLimitationsinXST
•VerilogAttributesandMetaComments
•VerilogConstructsSupportedinXST
•VerilogSystemTasksandFunctionsSupportedinXST
•VerilogPrimitives
•VerilogReservedKeywords
•Verilog-2001SupportinXST
AboutXSTVerilogLanguageSupport
Complexcircuitsarecommonlydesignedusingatopdownmethodology.Various
specicationlevelsarerequiredateachstageofthedesignprocess.Forexample,atthe
architecturallevel,aspecicationmaycorrespondtoablockdiagramoranAlgorithmic
StateMachine(ASM)chart.AblockorASMstagecorrespondstoaregistertransfer
blockwheretheconnectionsareN-bitwires,suchas:
•Register
•Adder
•Counter
•Multiplexer
•Gluelogic
•FiniteStateMachine(FSM)
AHardwareDescriptionLanguage(HDL)suchasVerilogallowstheexpressionof
notationssuchasASMchartsandcircuitdiagramsinacomputerlanguage.
Verilogprovidesbothbehavioralandstructurallanguagestructures.Thesestructures
allowexpressingdesignobjectsathighandlowlevelsofabstraction.Designing
hardwarewithalanguagesuchasVerilogallowsusingsoftwareconceptssuchas
parallelprocessingandobject-orientedprogramming.VeriloghasasyntaxsimilartoC
andPascal.XSTsupportsitasIEEE1364.
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Chapter15:XSTVerilogLanguageSupport
TheVerilogsupportinXSTprovidesanefcientwaytodescribeboththeglobalcircuit
andeachblockaccordingtothemostefcientstyle.Synthesisisthenperformedwith
thebestsynthesisowforeachblock.Synthesisinthiscontextisthecompilationof
high-levelbehavioralandstructuralVerilogHardwareDescriptionLanguage(HDL)
statementsintoaattenedgate-levelnetlist,whichcanthenbeusedtocustomprogram
aprogrammablelogicdevicesuchasaVirtex®device.Differentsynthesismethodsare
usedforarithmeticblocks,gluelogic,andFiniteStateMachine(FSM)components.
TheXSTUserGuideforVirtex-4,Virtex-5,Spartan-3,andNewerCPLDDevicesassumesthat
youarefamiliarwithbasicVerilogconcepts.
Formoreinformation,see:
•Verilogdesignconstraintsandoptions
XSTDesignConstraints
•Verilogattributesyntax
Verilog-2001Attributes
•SettingVerilogoptionsintheProcesswindowofISE®DesignSuite
XSTGeneralConstraints
•GeneralVeriloginformation
IEEEVerilogHDLReferenceManual
BehavioralVerilog
ForinformationaboutBehavioralVerilog,see:
XSTBehavioralVerilogLanguageSupport
VariablePartSelects
Verilog2001addsthecapabilityofusingvariablestoselectagroupofbitsfromavector.
Avariablepartselectisdenedbythestartingpointofitsrangeandthewidthofthe
vector,insteadofbeingboundedbytwoexplicitvalues.Thestartingpointofthepart
selectcanvary ,butthewidthofthepartselectremainsconstant.
VariablePartSelectSymbols
SymbolMeaning
+(plus)Thepartselectincreasesfromthestartingpoint
-(minus)Thepartselectdecreasesfromthestartingpoint
CodingExample
reg[3:0]data;
reg[3:0]select;//avaluefrom0to7
wire[7:0]byte=data[select+:8];
StructuralVerilogFeatures
ThissectiondiscussesStructuralVerilogFeatures,andincludes:
•AboutStructuralVerilogFeatures
•InstantiatingPre-DenedPrimitives
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Chapter15:XSTVerilogLanguageSupport
AboutStructuralVerilogFeatures
StructuralVerilogdescriptionsassembleseveralblocksofcodeandallowthe
introductionofhierarchyinadesign.Thebasicconceptsofhardwarestructureare:
•Component
Thebuildingorbasicblock
•Port
AcomponentI/Oconnector
•Signal
Correspondstoawirebetweencomponents
InVerilog,acomponentisrepresentedbyadesignmodule.Themoduledeclaration
providestheexternalviewofthecomponent.Itdescribeswhatcanbeseenfromthe
outside,includingthecomponentports.Themodulebodyprovidesaninternalview.It
describesthebehaviororthestructureofthecomponent.
Theconnectionsbetweencomponentsarespeciedwithincomponentinstantiation
statements.Thesestatementsspecifyaninstanceofacomponentoccurringwithin
anothercomponentorthecircuit.Eachcomponentinstantiationstatementislabeled
withanidentier.
Besidesnamingacomponentdeclaredinalocalcomponentdeclaration,acomponent
instantiationstatementcontainsanassociationlist(theparenthesizedlist)thatspecies
whichactualsignalsorportsareassociatedwithwhichlocalportsofthecomponent
declaration.
Verilogprovidesalargesetofbuilt-inlogicgateswhichcanbeinstantiatedtobuild
largerlogiccircuits.Thesetoflogicalfunctionsdescribedbythebuilt-ingatesincludes:
•AND
•OR
•XOR
•NAND
•NOR
•NOT
BuildingaBasicXORFunctionStructuralVerilogCodingExample
FollowingisanexampleofbuildingabasicXORfunctionoftwosinglebitinputs
aandb:
modulebuild_xor(a,b,c);
inputa,b;
outputc;
wirec,a_not,b_not;
nota_inv(a_not,a);
notb_inv(b_not,b);
anda1(x,a_not,b);
anda2(y,b_not,a);
orout(c,x,y);
endmodule
Eachinstanceofthebuilt-inmoduleshasauniqueinstantiationnamesuchas:
•a_inv
•b_inv
•out
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Chapter15:XSTVerilogLanguageSupport
StructuralDescriptionofaHalfAdderStructuralVerilogCodingExample
Thefollowingcodingexampleshowsthestructuraldescriptionofahalfadder
composedoffour,2inputnandmodules:
modulehalfadd(X,Y,C,S);
inputX,Y;
outputC,S;
wireS1,S2,S3;
nandNANDA(S3,X,Y);
nandNANDB(S1,X,S3);
nandNANDC(S2,S3,Y);
nandNANDD(S,S1,S2);
assignC=S3;
endmodule
SynthesizedTopLevelNetlistDiagram
InstantiatingPre-DefinedPrimitives
ThestructuralfeaturesofVerilogalsoallowyoutodesigncircuitsbyinstantiating
pre-denedprimitivessuchas:
•gates
•registers
•Xilinx®specicprimitivessuchas:
–CLKDLL
–BUFG
TheseprimitivesareotherthanthoseincludedinVerilog.Thesepre-denedprimitives
aresuppliedwiththeXSTVeriloglibraries(unisim_comp.v).
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Chapter15:XSTVerilogLanguageSupport
StructuralInstantiationofREGISTERandBUFGStructuralVerilogCoding
Example
modulefoo(sysclk,in,reset,out);
inputsysclk,in,reset;
outputout;
regout;
wiresysclk_out;
FDCregister(out,sysclk_out,reset,in);
//positionbasedreferencing
BUFGclk(.O(sysclk_out),.I(sysclk));
//namebasedreferencing
...
endmodule
Theunisim_comp.vlibrarylesuppliedwithXST,includesthedenitionsfor:
•FDC
•BUFG
(*BOX_TYPE="PRIMITIVE"*)//Verilog-2001
moduleFDC(Q,C,CLR,D);
parameterINIT=1’b0;
outputQ;
inputC;
inputCLR;
inputD;
endmodule
(*BOX_TYPE="PRIMITIVE"*)//Verilog-2001
moduleBUFG(O,I);
outputO;
inputI;
endmodule
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Chapter15:XSTVerilogLanguageSupport
VerilogParameters
Verilogmodulesallowyoutodeneconstantsknownasparameters.Parameterscanbe
passedtomoduleinstancestodenecircuitsofarbitrarywidths.Parametersformthe
basisofcreatingandusingparameterizedblocksinadesigntoachievehierarchy .
CodingExample
ThefollowingVerilogcodingexampleshowstheuseofparameters.Nullstring
parametersarenotsupported.
modulelpm_reg(out,in,en,reset,clk);
parameterSIZE=1;
inputin,en,reset,clk;
outputout;
wire[SIZE-1:0]in;
reg[SIZE-1:0]out;
always@(posedgeclkornegedgereset)
begin
if(!reset)
out<=1’b0;
else
if(en)
out<=in;
else
out<=out;//redundantassignment
end
endmodule
moduletop();//portlistleftblankintentionally
...
wire[7:0]sys_in,sys_out;
wiresys_en,sys_reset,sysclk;
lpm_reg#8buf_373(sys_out,sys_in,sys_en,sys_reset,sysclk);
...
endmodule
Instantiationofthemodulelpm_regwithainstantiationwidthof8causestheinstance
buf_373tobe8bitswide.
TheGenerics(-generics)commandlineoptionallowsyoutoredeneparameters
(Verilog)valuesdenedinthetop-leveldesignblock.Thisallowsyoutoeasilymodify
thedesigncongurationwithoutanyHardwareDescriptionLanguage(HDL)source
modications,suchasforIPcoregenerationandtestingows.
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Chapter15:XSTVerilogLanguageSupport
VerilogParameterandAttributeConflicts
ThissectiondiscussesVerilogParameterandAttributeConicts,andincludes:
•ResolvingVerilogParameterandAttributeConicts
•VerilogParameterandAttributeConictsPrecedence
ResolvingVerilogParameterandAttributeConflicts
SinceparametersandattributescanbeappliedtobothinstancesandmodulesinVerilog
code,andattributescanalsobespeciedinaconstraintsle,conictswilloccasionally
arise.
XSTusesthefollowingrulesofprecedencetoresolvetheseconicts:
1.Specicationsonaninstance(lowerlevel)takesprecedenceoverspecicationsona
module(higherlevel).
2.Ifaparameterandanattributearespeciedoneitherthesameinstanceorthesame
module,theparametertakesprecedence.XSTissuesawarningmessage.
3.AnattributespeciedintheXSTConstraintFile(XCF)takesprecedenceover
attributesorparametersspeciedintheVerilogcode.
Whenanattributespeciedonaninstanceoverridesaparameterspeciedonamodule
inXST,thesimulationtoolmayusetheparameteranyway.Ifthathappens,the
simulationresultsmaynotmatchthesynthesisresults.
VerilogParameterandAttributeConflictsPrecedence
ParameteronanInstanceParameteronaModule
AttributeonanInstanceApplyParameter(XSTissues
warning)
ApplyAttribute(possible
simulationmismatch)
AttributeonaModuleApplyParameterApplyParameter(XSTissues
warning)
AttributeinXCFApplyAttribute(XSTissues
warning)
ApplyAttribute
Securityattributesonthemoduledenitionalwayshavehigherprecedencethanany
otherattributeorparameter.
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Chapter15:XSTVerilogLanguageSupport
VerilogLimitationsinXST
ThissectiondescribesVerilogLimitationsinXST,andincludes:
•VerilogCaseSensitivity
•VerilogBlockingandNonblockingAssignments
•VerilogIntegerHandling
VerilogCaseSensitivity
SinceVerilogiscasesensitive,moduleandinstancenamescanbemadeuniqueby
changingcapitalization.However,forcompatibilitywithlenames,mixedlanguage
support,andothertools,Xilinx®recommendsthatyoudonotrelyoncapitalization
onlytomakeinstancenamesunique.
XSTdoesnotallowmodulenamestodifferbycapitalizationonly.Itrenamesinstances
andsignalnamestoensurethatlackofcasesensitivitysupportinothertoolsinyour
owdoesnotadverselyimpactyourdesign.
XSTSupportforVerilogCaseSensitivity
XSTsupportsVerilogcasesensitivityasfollows:
•DesignscanusecaseequivalentnamesforI/Oports,nets,regsandmemories.
•Equivalentnamesarerenamedusingapostx(rnm<Index>).
•ArenameconstructisgeneratedintheNGCle.
•DesignscanuseVerilogidentiersthatdifferincaseonly.XSTrenamesthemusing
apostxaswithequivalentnames.
Forinstance:
moduleupperlower4(input1,INPUT1,output1,output2);
inputinput1;
inputINPUT1;
Forthisexample,INPUT1isrenamedtoINPUT1_rnm0.
VerilogRestrictionsWithinXST
XSTrejectscodeusingequivalentnames(namedblocks,tasks,andfunctions)suchas
thefollowing:
...
always@(clk)
begin:fir_main5
reg[4:0]fir_main5_w1;
reg[4:0]fir_main5_W1;
XSTissuesthefollowingerrormessage:
ERROR:Xst:863-"design.v",line6:Nameconflict
(<fir_main5/fir_main5_w1>and<fir_main5/fir_main5_W1>)
Codeusingcaseequivalentmodulenamessuchasthefollowingisrejected:
moduleUPPERLOWER10(...);
...
moduleupperlower10(...);
...
XSTissuesthefollowingerrormessage:
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Chapter15:XSTVerilogLanguageSupport
ERROR:Xst:909-Modulenameconflict(UPPERLOWER10and
upperlower10)
VerilogBlockingandNonblockingAssignments
Thissectiongivestworejectedcodingexamplesforblockingandnonblocking
assignments.
RejectedCodingExampleOne
XSTrejectsVerilogdesignsifagivensignalisassignedthroughbothblockingand
nonblockingassignmentsasshowninthefollowingcodingexample.
always@(in1)
begin
if(in2)
out1=in1;
else
out1<=in2;
end
RejectedCodingExampleTwo
Thefollowingcodingexampleisrejectedevenifthereisnorealmixingofblocking
andnonblockingassignments.
if(in2)
begin
out1[0]=1’b0;
out1[1]<=in1;
end
else
begin
out1[0]=in2;
out1[1]<=1’b1;
end
Ifavariableisassignedinbothablockingandnonblockingassignment,XSTissuesthe
followingerrormessage:
ERROR:Xst:880-"design.v",linen:
Cannotmixblockingandnon-blockingassignmentsonsignal<out1>.
Therearealsorestrictionswhenmixingblockingandnonblockingassignmentson
bitsandslices.
Errorsarecheckedatthesignallevel,notatthebitlevel.
Ifthereismorethanoneblockingornonblockingerror,onlytherstisreported.
Insomecases,thelinenumberfortheerrormightbeincorrect(astheremightbe
multiplelineswherethesignalhasbeenassigned).
VerilogIntegerHandling
XSThandlesVerilogintegersdifferentlyfromothersynthesistoolsinseveralinstances.
Theymustbecodedinaparticularway.UnsizedintegersinVerilogcaseitem
expressionsandconcatenationsmaycauseunpredictableresults
UnsizedIntegersinVerilogCaseItemExpressions
UnsizedintegersinVerilogcaseitemexpressionsmaycauseunpredictableresults.
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Chapter15:XSTVerilogLanguageSupport
Inthefollowingcodingexample,thecaseitemexpression4isanunsizedintegerthat
causesunpredictableresults.Toavoidproblems,sizethe4to3bitsasfollows:
reg[2:0]condition1;
always@(condition1)
begin
case(condition1)
4:data_out=2;//<willgeneratebadlogic
3’d4:data_out=2;//<willwork
endcase
end
UnsizedIntegersinVerilogConcatenations
UnsizedintegersinVerilogconcatenationsmaycauseunpredictableresults.
Ifyouuseanexpressionthatresultsinanunsizedinteger:
1.Assigntheexpressiontoatemporarysignal.
2.Usethetemporarysignalintheconcatenationasfollows:
reg[31:0]temp;
assigntemp=4’b1111%2;
assigndout={12/3,temp,din};
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Chapter15:XSTVerilogLanguageSupport
VerilogAttributesandMetaComments
XSTsupportsbothofthefollowinginVerilog:
•Verilog-2001styleattributes
Xilinx®recommendsVerilog-2001attributessincetheyaremoregenerallyaccepted.
•Verilogmetacomments
MetacommentsarecommentsthatareunderstoodbytheVerilogparser.
Verilog-2001Attributes
XSTsupportsVerilog-2001attributestatements.Attributesarecommentsthatpass
specicinformationtosoftwaretoolssuchassynthesistools.Verilog-2001attributes
canbespeciedanywhereforoperatorsorsignalswithinmoduledeclarationsand
instantiations.Otherattributedeclarationsmaybesupportedbythecompiler,but
areignoredbyXST.
VerilogMetaComments
UseVerilogmetacommentsto:
•Setconstraintsonindividualobjectssuchas:
–module
–instance
–net
•Setdirectivesonsynthesis:
–parallel_caseandfull_casedirectives
–translate_onandtranslate_offdirectives
–alltoolspecicdirectives
Example:
syn_sharing
Formoreinformation,see:
XSTDesignConstraints
XSTsupportsbothC-styleandVerilogstylemetacomments.
WritingVerilogMetaComments
StyleSyntaxLineRules
C-style/*...*/Commentscanbemultiple
line
Verilogstyle//...Commentsendattheendof
theline
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Chapter15:XSTVerilogLanguageSupport
SupportedConstraints
XSTsupportsthefollowingconstraints:
•TranslateOff(TRANSLATE_OFF)andTranslateOn(TRANSLATE_ON)
//synthesistranslate_on
//synthesistranslate_off
•ParallelCase(PARALLEL_CASE)
//synthesisparallel_casefull_case
//synthesisparallel_case
//synthesisfull_case
•Constraintsonindividualobjects
Syntax
//synthesisattribute[of]ObjectName[is]AttributeValue
CodingExample
//synthesisattributeRLOCofu123isR11C1.S0
//synthesisattributeHUSETu1MY_SET
//synthesisattributefsm_extractofState2is"yes"
//synthesisattributefsm_encodingofState2is"gray"
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Chapter15:XSTVerilogLanguageSupport
VerilogConstructsSupportedinXST
ThissectiondiscussesVerilogConstructsSupportedinXST,including:
•Constants
•DataTypes
•ContinuousAssignments
•ProceduralAssignments
•DesignHierarchies
•CompilerDirectives
NoteXSTdoesnotallowunderscoresastherstcharacterofsignalnames(for
example,_DATA_1)
VerilogConstantsSupportedinXST
ConstantSupported/Unsupported
IntegerConstantsSupported
RealConstantsSupported
StringsConstantsUnsupported
VerilogDataTypesSupportedinXST
XSTsupportsallVerilogdatatypesexceptasshowninthefollowingtable.
NetTypesDriveStrengthsRegistersNamedEvents
tri0,tri1,andtrireg
areunsupported.
Alldrivestrengths
areignored.
Realandrealtime
registersare
unsupported.
Allnamedeventsare
unsupported.
VerilogContinuousAssignmentsSupportedinXST
ContinuousAssignmentSupported/Unsupported
DriveStrengthIgnored
DelayIgnored
VerilogProceduralAssignmentsSupportedinXST
XSTsupportsVerilogProceduralAssignmentsexceptasnotedbelow:
•assign
Supportedwithlimitations
Formoreinformation,see:
BehavioralVerilogAssignandDeassignStatements
•deassign
Supportedwithlimitations.
Formoreinformation,see:
BehavioralVerilogAssignandDeassignStatements
•force
Unsupported
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Chapter15:XSTVerilogLanguageSupport
•release
Unsupported
•foreverstatements
Unsupported
•repeatstatements
Supported,butrepeatvaluemustbeconstant
•forstatements
Supported,butboundsmustbestatic
•delay(#)
Ignored
•event(@)
Unsupported
•wait
Unsupported
•NamedEvents
Unsupported
•ParallelBlocks
Unsupported
•SpecifyBlocks
Ignored
•Disable
SupportedexceptinForandRepeatLoopstatements.
VerilogDesignHierarchiesSupportedinXST
DesignHierarchySupported/Unsupported
moduledenitionSupported
macromoduledenitionUnsupported
hierarchicalnamesUnsupported
defparamSupported
arrayofinstancesSupported
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Chapter15:XSTVerilogLanguageSupport
VerilogCompilerDirectivesSupportinXST
CompilerDirectiveSupported/Unsupported
‘celldene‘endcelldeneIgnored
‘default_nettypeSupported
‘deneSupported
‘ifdef‘else‘endifSupported
‘undef,‘ifndef,‘elsif,Supported
‘includeSupported
‘resetallIgnored
‘timescaleIgnored
‘unconnected_drive
‘nounconnected_drive
Ignored
‘uselibUnsupported
‘le,‘lineSupported
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Chapter15:XSTVerilogLanguageSupport
VerilogSystemTasksandFunctionsSupportedinXST
ThissectiondiscussesVerilogSystemTasksandFunctionsSupportedinXST,and
includes:
•SupportedSystemTasksandFunctions
•UnsupportedSystemTasks
•SignedandUnsignedSystemTasks
•ReadmembandReadmemhSystemTasks
•OtherSystemTasks
•VerilogDisplaySyntaxExample
SupportedSystemTasksandFunctions
SystemTaskorFunctionSupported/UnsupportedComment
$displaySupportedEscapesequencesarelimitedto%d,
%b,%h,%o,%cand%s
$fcloseSupported
$fdisplaySupported
$fgetsSupported
$nishSupported$nishissupportedforstaticallynever
activeconditionalbranchesonly
$fopenSupported
$fscanfSupportedEscapesequencesarelimitedto%band
%d
$fwriteSupported
$monitorIgnored
$randomIgnored
$readmembSupported
$readmemhSupported
$signedSupported
$stopIgnored
$strobeIgnored
$timeIgnored
$unsignedSupported
$writeSupportedEscapesequencesarelimitedto%d,
%b,%h,%o,%cand%s
allothersIgnored
UnsupportedSystemTasks
TheXSTVerilogcompilerignoresunsupportedsystemtasks.
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Chapter15:XSTVerilogLanguageSupport
SignedandUnsignedSystemTasks
The$signedand$unsignedsystemtaskscanbecalledonanyexpressionusingthe
followingsyntax:
•$signed(expr)or
•$unsigned(expr)
Thereturnvaluefromthesecallsisthesamesizeastheinputvalue.Itssignisforced
regardlessofanyprevioussign.
ReadmembandReadmemhSystemTasks
The$readmemband$readmemhsystemtaskscanbeusedtoinitializeblockmemories.
Formoreinformation,see:
InitializingRAMFromanExternalFileCodingExamples
Use$readmembforbinaryand$readmemhforhexadecimalrepresentation.Toavoid
thepossibledifferencebetweenXSTandsimulatorbehavior,Xilinx®recommendsthat
youuseindexparametersinthesesystemtasks.Seethefollowingcodingexample.
$readmemb("rams_20c.data",ram,0,7);
OtherSystemTasks
Theremainderofthesystemtaskscanbeusedtodisplayinformationtoyourcomputer
screenandlogleduringprocessing,ortoopenandusealeduringsynthesis.
Youmustcallthesetasksfromwithininitialblocks.XSTsupportsasubsetofescape
sequences,specically:
•%h
•%d
•%o
•%b
•%c
•%s
VerilogDisplaySyntaxExample
Thefollowingexampleshowsthesyntaxfor$displaythatreportsthevalueofabinary
constantindecimalformat:
parameterc=8’b00101010;
initial
begin
$display("Thevalueofcis%d",c);
end
ThefollowinginformationiswrittentothelogleduringtheHDLAnalysisphase:
Analyzingtopmodule<example>.
c=8’b00101010
"foo.v"line9:$display:Thevalueofcis42
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Chapter15:XSTVerilogLanguageSupport
VerilogPrimitives
ThissectiondiscussesVerilogPrimitives,andincludes:
•SupportedPrimitives
•UnsupportedPrimitives
•Syntax
SupportedPrimitives
XSTsupportsthefollowingVeriloggate-levelprimitivesexceptasindicated:
•PulldownandPullup
Unsupported
•Drivestrengthanddelay
Ignored
•Arraysofprimitives
Unsupported
UnsupportedPrimitives
XSTdoesnotsupport:
•Verilogswitch-levelprimitives,suchas:
–cmos,nmos,pmos,rcmos,rnmos,rpmos
–rtran,rtranif0,rtranif1,tran,tranif0,tranif1
•Veriloguser-denedprimitives
Syntax
gate_typeinstance_name(output,inputs,...);
CodingExample
andU1(out,in1,in2);bufif1U2(triout,data,trienable);
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Chapter15:XSTVerilogLanguageSupport
VerilogReservedKeywords
Keywordsmarkedwithanasterisk(*)arereservedbyVerilog,butarenotsupportedby
XST.
alwaysandassignautomatic
beginbufbuf0buf1
casecasexcasezcell*
cmoscong*deassigndefault
defparamdesign*disableedge
elseendendcaseendcong*
endfunctionendgenerateendmoduleendprimitive
endspecifyendtableendtaskevent
forforceforeverfork
functiongenerategenvarhighz0
highz1ififnoneincdir*
include*initialinoutinput
instance*integerjoinlarge
liblist*library*localparam*macromodule
mediummodulenandnegedge
nmosnornoshow-cancelled*not
notif0notif1oroutput
parameterpmosposedgeprimitive
pull0pull1pulluppulldown
pulsestyle-_ondetect*pulsestyle-_onevent*rcmosreal
realtimeregreleaserepeat
rnmosrpmosrtranrtranif0
rtranif1scalaredshow-cancelled*signed
smallspecifyspecparamstrong0
strong1supply0supply1table
tasktimetrantranif0
tranif1tritri0tri1
triandtriortrireguse*
vectoredwaitwandweak0
weak1whilewirewor
xnorxor
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Chapter15:XSTVerilogLanguageSupport
Verilog-2001SupportinXST
XSTsupportsthefollowingVerilog-2001features:
•Generatestatements
•Combinedport/datatypedeclarations
•ANSI-styleportlists
•Moduleparameterportlists
•ANSICstyletask/functiondeclarations
•Commaseparatedsensitivitylist
•Combinatoriallogicsensitivity
•Defaultnetswithcontinuousassigns
•Disabledefaultnetdeclarations
•Indexedvectorpartselects
•Multi-dimensionalarrays
•Arraysofnetandrealdatatypes
•Arraybitandpartselects
•Signedreg,net,andportdeclarations
•Signedbasedintegernumbers
•Signedarithmeticexpressions
•Arithmeticshiftoperators
•Automaticwidthextensionpast32bits
•Poweroperator
•Nsizedparameters
•Explicitin-lineparameterpassing
•Fixedlocalparameters
•Enhancedconditionalcompilation
•Fileandlinecompilerdirectives
•Variablepartselects
•RecursiveTasksandFunctions
•ConstantFunctions
Formoreinformation,see:
•Sutherland,Stuart.Verilog2001:AGuidetotheNewFeaturesoftheVERILOGHardware
DescriptionLanguage(2002)
•IEEEStandardsAssociation.1364-2001:IEEEStandardVerilogHardwareDescription
Language(2001)
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Chapter16
XSTBehavioralVerilogLanguage
Support
ThischapterdiscussesXSTBehavioralVerilogLanguageSupport,andincludes:
•BehavioralVerilogVariableDeclarations
•BehavioralVerilogInitialValues
•BehavioralVerilogLocalReset
•BehavioralVerilogArrays
•BehavioralVerilogMulti-DimensionalArrays
•BehavioralVerilogDataTypes
•BehavioralVerilogLegalStatements
•BehavioralVerilogExpressions
•BehavioralVerilogBlocks
•BehavioralVerilogModules
•BehavioralVerilogModuleDeclarations
•BehavioralVerilogContinuousAssignments
•BehavioralVerilogProceduralAssignments
•BehavioralVerilogConstants
•BehavioralVerilogMacros
•BehavioralVerilogIncludeFiles
•BehavioralVerilogComments
•BehavioralVerilogGenerateStatements
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogVariableDeclarations
VariablesinVerilogmaybedeclaredasintegersorreal.Thesedeclarationsareintended
foruseintestcodeonly.Verilogprovidesdatatypessuchasregandwireforactual
hardwaredescription.
VariablesinVerilog
DataTypeVariableGiven
ValueInDefaultWidthVerilog-2001
regproceduralblockonebit(scalar)signedorunsigned
wirecontinuous
assignment
onebit(scalar)signedorunsigned
CodingExample
TospecifyanN-bitwidth(vectors)foradeclaredregorwire,theleftandrightbit
positionsaredenedinsquarebracketsseparatedbyacolon.
reg[3:0]arb_priority;
wire[31:0]arb_request;
wiresigned[8:0]arb_signed;
where
•arb_request[31]istheMSB
•arb_request[0]istheLSB
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogInitialValues
InVerilog-2001,youcaninitializeregisterswhenyoudeclarethem.
Thevalue:
•Isaconstant
•Cannotdependonearlierinitialvalues
•Cannotbeafunctionortaskcall
•Canbeaparametervaluepropagatedtotheregister
•Speciesallbitsofavector
Whenyouassignaregisteraninitialvalueinadeclaration,XSTsetsthisinitialvalueon
theoutputoftheregister:
•Atglobalreset,or
•Atpowerup
Aninitialvalueassignedinthismanner:
•IscarriedintheNGCleasanINITattributeontheregister
•Isindependentofanylocalreset
regarb_onebit=1’b0;
reg[3:0]arb_priority=4’b1011;
Youcanalsoassignaset/reset(initial)valuetoaregisterinthebehavioralVerilogcode.
Assignavaluetoaregisterwhentheregisterresetlinegoestotheappropriatevalueas
showninthefollowingcodingexample.
always@(posedgeclk)
begin
if(rst)
arb_onebit<=1’b0;
end
end
Whenyousettheinitialvalueofavariableinthebehavioralcode,itisimplementedin
thedesignasaip-opwhoseoutputcanbecontrolledbyalocalreset.Assuch,itis
carriedintheNGCleasanFDPorFDCip-op.
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogLocalReset
Localresetisindependentofglobalreset.Registerscontrolledbyalocalresetmaybeset
toadifferentvaluethanoneswhosevalueisonlyresetatglobalreset(powerup).In
thefollowingcodingexample,theregister,arb_onebit,issetto0atglobalreset,but
apulseonthelocalreset(rst)canchangeitsvalueto1.
CodingExample
modulemult(clk,rst,A_IN,B_OUT);
inputclk,rst,A_IN;
outputB_OUT;
regarb_onebit=1’b0;
always@(posedgeclkorposedgerst)
begin
if(rst)
arb_onebit<=1’b1;
else
arb_onebit<=A_IN;
end
end
B_OUT<=arb_onebit;
endmodule
Thissetstheset/resetvalueontheregisteroutputatinitialpowerup,butsincethisis
dependentuponalocalreset,thevaluechangeswheneverthelocalset/resetisactivated.
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogArrays
Verilogallowsarraysofregandwirestobedenedasshowninthefollowingcoding
examples.
BehavioralVerilogArraysCodingExample
Thefollowingcodingexampledescribesanarrayof32elementseach,4bitswidewhich
canbeassignedinbehavioralVerilogcode:
reg[3:0]mem_array[31:0];
StructuralVerilogArraysCodingExample
Thefollowingcodingexampledescribesanarrayof64elementseach8bitswidewhich
canbeassignedonlyinstructuralVerilogcode:
wire[7:0]mem_array[63:0];
BehavioralVerilogMulti-DimensionalArrays
XSTsupportsmulti-dimensionalarraytypesofuptotwodimensions.Multi-dimensional
arrayscanbeanynetoranyvariabledatatype.Youcancodeassignmentsand
arithmeticoperationswitharrays,butyoucannotselectmorethanoneelementof
anarrayatonetime.Youcannotpassmulti-dimensionalarraystosystemtasksor
functions,ortoregulartasksorfunctions.
CodingExampleOne
ThefollowingVerilogcodingexampledescribesanarrayof256x16wireelementseach
8bitswide,whichcanbeassignedonlyinstructuralVerilogcode:
wire[7:0]array2[0:255][0:15];
CodingExampleTwo
ThefollowingVerilogcodingexampledescribesanarrayof256x8registerelements,
each64bitswide,whichcanbeassignedinbehavioralVerilogcode:
reg[63:0]regarray2[255:0][7:0];
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogDataTypes
ThissectiondiscussesBehavioralVerilogDataTypes,andincludes:
•BitDataTypeValues
•SupportedVerilogDataTypes
•NetsandRegisters
BitDataTypeValues
TheVerilogrepresentationofthebitdatatypecontainsthefollowingvalues:
•0
logiczero
•1
logicone
•x
unknownlogicvalue
•z
highimpedance
SupportedVerilogDataTypes
XSTsupportsthefollowingVerilogdatatypes:
•Net
–wire
–tri
–triand/wand
–trior/wor
•Registers
–reg
–integer
•Supplynets
–supply0
–supply1
•Constants
parameter
•Multi-DimensionalArrays(Memories)
NetsandRegisters
Netsandregisterscanbeeither:
•Singlebit(scalar)
•Multiplebit(vectors)
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Chapter16:XSTBehavioralVerilogLanguageSupport
CodingExample
ThefollowingBehavioralVerilogcodingexampleshowssampleVerilogdatatypes
foundinthedeclarationsectionofaVerilogmodule.
wirenet1;//singlebitnet
regr1;//singlebitregister
tri[7:0]bus1;//8bittristatebus
reg[15:0]bus1;//15bitregister
reg[7:0]mem[0:127];//8x128memoryregister
parameterstate1=3’b001;//3bitconstant
parametercomponent="TMS380C16";//string
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogLegalStatements
ThefollowingstatementsarelegalinBehavioralVerilog.
•Variableandsignalassignments
–Variable=expression
–if(condition)statement
–elsestatement
–case(expression)
expression:statement
...
default:statement
endcase
–for(variable=expression;condition;variable=variable+expression)statement
–while(condition)statement
–foreverstatement
–functionsandtasks
•Allvariablesaredeclaredasintegerorreg.
NoteAvariablecannotbedeclaredasawire.
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogExpressions
Anexpressioninvolvesconstantsandvariableswitharithmetic,logical,relational,and
conditionaloperatorsasshowninOperatorsSupportedinBehavioralVerilog.
Thelogicaloperatorsarefurtherdividedasbit-wiseversuslogical,dependingon
whetheritisappliedtoanexpressioninvolvingseveralbitsorasinglebit.
OperatorsSupportedinBehavioralVerilog
ArithmeticLogicalRelationalConditional
+&<?
-&&==
*|===
**||<=
/^>=
%~>=
~^!=
^~!==
<<>
>>
<<<
>>>
ExpressionsSupportedinBehavioralVerilog
ExpressionSymbolSupported/Unsupported
Concatenation{}Supported
Replication{{}}Supported
Arithmetic
+,-,*,**Supported
/Supportedonlyifsecondoperandisa
powerof2
Modulus%Supportedonlyifsecondoperandisa
powerof2
Addition+Supported
Subtraction-Supported
Multiplication*Supported
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Chapter16:XSTBehavioralVerilogLanguageSupport
ExpressionSymbolSupported/Unsupported
Power**Supported
•Bothoperandsareconstants,
withthesecondoperandbeing
non-negative.
•Iftherstoperandisa2,thenthe
secondoperandmaybeavariable.
•XSTdoesnotsupportthereal
datatype.Anycombinationof
operandsthatresultsinarealtype
causesanerror.
•ThevaluesX(unknown)andZ
(highimpedance)arenotallowed.
Division/Supported
XSTgeneratesincorrectlogicforthe
divisionoperatorbetweensigned
andunsignedconstants.Example:
-1235/3’b111
Relational>,<,>=,<=Supported
LogicalNegation!Supported
LogicalAND&&Supported
LogicalOR||Supported
LogicalEquality==Supported
LogicalInequality!=Supported
CaseEquality===Supported
CaseInequality!==Supported
BitwiseNegation~Supported
BitwiseAND&Supported
BitwiseInclusiveOR|Supported
BitwiseExclusiveOR^Supported
BitwiseEquivalence~^,^~Supported
ReductionAND&Supported
ReductionNAND~&Supported
ReductionOR|Supported
ReductionNOR~|Supported
ReductionXOR^Supported
ReductionXNOR~^,^~Supported
LeftShift<<Supported
RightShiftSigned>>>Supported
LeftShiftSigned<<<Supported
RightShift>>Supported
Conditional?:Supported
EventORor,’,’Supported
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Chapter16:XSTBehavioralVerilogLanguageSupport
ResultsofEvaluatingExpressionsinBehavioralVerilog
Thefollowingtableliststheresultsofevaluatingexpressionsusingthemorefrequently
usedoperatorssupportedbyXST.
The(===)and(!==)operatorsarespecialcomparisonoperatorsusefulinsimulationsto
checkifavariableisassignedavalueof(x)or(z).Theyaretreatedas(==)or(!=)in
synthesis.
aba==ba===ba!=ba!==ba&ba&&ba|ba||ba^b
00110000000
01001100111
0xx0x100xxx
0zx0x100xxx
10001100111
11110011110
1xx0x1xx11x
1zx0x1xx11x
x0x0x100xxx
x1x0x1xx11x
xxx1x0xxxxx
xzx0x1xxxxx
z0x0x100xxx
z1x0x1xx11x
zxx0x1xxxxx
zzx1x0xxxxx
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogBlocks
Blockstatementsareusedtogroupstatementstogether.
XSTsupportssequentialblocksonly.Withintheseblocks,thestatementsareexecuted
intheorderlisted.
Blockstatementsaredesignatedbybeginandendkeywords.
XSTdoesnotsupportparallelblocks.
BehavioralVerilogModules
InVerilogadesigncomponentisrepresentedbyamodule.Theconnectionsbetween
componentsarespeciedwithinmoduleinstantiationstatements.Suchastatement
speciesaninstanceofamodule.Eachmoduleinstantiationstatementhasaname
(instancename).Inadditiontothename,amoduleinstantiationstatementcontainsan
associationlistthatspecieswhichactualnetsorportsareassociatedwithwhichlocal
ports(formals)ofthemoduledeclaration.
Allproceduralstatementsoccurinblocksthataredenedinsidemodules.Thetwo
kindsofproceduralblocksare:
•initialblock
•alwaysblock
Withineachblock,Verilogusesabeginandendtoenclosethestatements.Sinceinitial
blocksareignoredduringsynthesis,onlyalwaysblocksarediscussed.Thealways
blocksusuallytakethefollowingformat:
always
begin
statement
....
end
Eachstatementisaproceduralassignmentlineterminatedbyasemicolon.
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogModuleDeclarations
TheI/Oportsofthecircuitaredeclaredinthemoduledeclaration.Eachporthas:
•Aname
•Amode
–in
–out
–inout
TheinputandoutputportsdenedinthemoduledeclarationcalledEXAMPLEinthe
followingcodingexamplearethebasicinputandoutputI/Osignalsforthedesign.The
in-outportinVerilogisanalogoustoabi-directionalI/Opinonthedevicewiththedata
owforoutputversusinputbeingcontrolledbytheenablesignaltothetristatebuffer.
ThefollowingcodingexampledescribesEasatristatebufferwithahigh-trueoutput
enablesignal.
•Ifoe=1,thevalueofsignalAisoutputonthepinrepresentedbyE.
•Ifoe=0,thebufferisinhighimpedance(Z),andanyinputvaluedrivenonthe
pinE(fromtheexternallogic)isbroughtintothedeviceandfedtothesignal
representedbyD.
CodingExample
moduleEXAMPLE(A,B,C,D,E);
inputA,B,C;
outputD;
inoutE;
wireD,E;
...
assignE=oe?A:1’bz;
assignD=B&E;
...
endmodule
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogContinuousAssignments
Continuousassignmentsmodelcombinatoriallogicinaconciseway.
XSTsupportsbothexplicitandimplicitcontinuousassignments.
•Explicitcontinuousassignmentsareintroducedbytheassignkeywordafterthenet
hasbeenseparatelydeclared.
•Implicitcontinuousassignmentscombinedeclarationandassignment.
•XSTignoresdelaysandstrengthsgiventoacontinuousassignment.
•Continuousassignmentsareallowedonwireandtridatatypesonly.
ExplicitContinuousAssignmentCodingExample
wirepar_eq_1;
....
assignpar_eq_1=select?b:a;
ImplicitContinuousAssignmentCodingExample
wiretemp_hold=a|b;
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogProceduralAssignments
ThissectiondiscussesBehavioralVerilogProceduralAssignments,andincludes:
•AboutBehavioralVerilogProceduralAssignments
•BehavioralVerilogCombinatorialAlwaysBlocks
•BehavioralVerilogIf...ElseStatement
•BehavioralVerilogCaseStatements
•BehavioralVerilogForandRepeatLoops
•BehavioralVerilogWhileLoops
•BehavioralVerilogSequentialAlwaysBlocks
•BehavioralVerilogAssignandDeassignStatements
•BehavioralVerilogAssignmentExtensionPast32Bits
•BehavioralVerilogTasksandFunctions
•BehavioralVerilogRecursiveTasksandFunctions
•BehavioralVerilogConstantFunctions
•BehavioralVerilogBlockingVersusNon-BlockingProceduralAssignments
AboutBehavioralVerilogProceduralAssignments
BehavioralVerilogproceduralassignmentsare:
•Usedtoassignvaluestovariablesdeclaredasregs.
•Introducedbyalwaysblocks,tasks,andfunctions
•UsuallyusedtomodelregistersandFiniteStateMachine(FSM)components.
XSTsupports:
•Combinatorialfunctions
•Combinatorialandsequentialtasks
•Combinatorialandsequentialalwaysblocks
BehavioralVerilogCombinatorialAlwaysBlocks
CombinatoriallogiccanbemodeledefcientlyusingtwoformsofVerilogtimecontrol
statements:
•#(pound)
•*(asterisk)
Sincethe#(pound)timecontrolstatementisignoredforsynthesis,thisdiscussion
describesmodelingcombinatoriallogicwiththe*(asterisk)timecontrolstatement.
Acombinatorialalwaysblockhasasensitivitylistappearingwithinparenthesesafter
thewordalways.Analwaysblockisactivatedifanevent(valuechangeoredge)
appearsononeofthesensitivitylistsignals.Thissensitivitylistcancontainanysignal
thatappearsinconditions(iforcase,forexample),andanysignalappearingonthe
right-handsideofanassignment.Bysubstitutingan*(asterisk)withoutparenthesesfor
alistofsignals,thealwaysblockisactivatedforaneventinanyofthealwaysblock’s
signalsasdescribedabove.
Incombinatorialprocesses,ifasignalisnotexplicitlyassignedinallbranchesofifor
casestatements,XSTgeneratesalatchtoholdthelastvalue.Toavoidlatchcreation,be
surethatallassignedsignalsinacombinatorialprocessarealwaysexplicitlyassignedin
allpathsoftheprocessstatements.
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Chapter16:XSTBehavioralVerilogLanguageSupport
Thefollowingstatementscanbeusedinaprocess:
•Variableandsignalassignment
•if...elsestatement
•casestatement
•forandwhileloopstatement
•Functionandtaskcall
BehavioralVerilogIf...ElseStatement
If...elsestatementsusetrue/falseconditionstoexecutestatements.
•Iftheexpressionevaluatestotrue,therststatementisexecuted.
•Iftheexpressionevaluatestofalse(orxorz)theelsestatementisexecuted.
Ablockofmultiplestatementsmaybeexecutedusingbeginandendkeywords.
If...elsestatementsmaybenested.
CodingExample
ThefollowingcodingexampleshowshowaMUXcanbedescribedusinganif...else
statement:
modulemux4(sel,a,b,c,d,outmux);
input[1:0]sel;
input[1:0]a,b,c,d;
output[1:0]outmux;
reg[1:0]outmux;
always@(seloraorborcord)
begin
if(sel[1])
if(sel[0])
outmux=d;
else
outmux=c;
else
if(sel[0])
outmux=b;
else
outmux=a;
end
endmodule
BehavioralVerilogCaseStatements
Acasestatement:
•Performsacomparisontoanexpressiontoevaluateoneofanumberofparallel
branches.
•Evaluatesthebranchesintheordertheyarewritten.
–Therstbranchthatevaluatestotrueisexecuted.
–Ifnoneofthebranchesmatch,thedefaultbranchisexecuted.
Donotuseunsizedintegersincasestatements.Alwayssizeintegerstoaspecicnumber
ofbits,orresultscanbeunpredictable.
caseztreatsallzvaluesinanybitpositionofthebranchalternativeasadontcare.
casextreatsallxandzvaluesinanybitpositionofthebranchalternativeasadontcare.
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Chapter16:XSTBehavioralVerilogLanguageSupport
Thequestionmark(?)canbeusedasadontcareineitherthecasezorcasexcase
statements.
CodingExample
ThefollowingcodingexampleshowshowaMUXcanbedescribedusingacase
statement:
modulemux4(sel,a,b,c,d,outmux);
input[1:0]sel;
input[1:0]a,b,c,d;
output[1:0]outmux;
reg[1:0]outmux;
always@(seloraorborcord)
begin
case(sel)
2’b00:outmux=a;
2’b01:outmux=b;
2’b10:outmux=c;
default:outmux=d;
endcase
end
endmodule
Theprecedingcasestatementevaluatesthevaluesoftheinputselinpriorityorder.To
avoidpriorityprocessing,Xilinx®recommendsthatyouuseaparallel-caseVerilog
attributetoensureparallelevaluationoftheselinputsasshowninthefollowing:
(*parallel_case*)case(sel)
BehavioralVerilogForandRepeatLoops
Whenusingalwaysblocks,repetitiveorbitslicestructurescanalsobedescribedusing
theforstatementortherepeatstatement.
ForStatement
Theforstatementissupportedfor:
•Constantbounds
•Stoptestconditionusingoneofthefollowingoperators:
–<
–<=
–>
–>=
•Nextstepcomputationfallinginoneofthefollowingspecications:
–var=var+step
–var=var-step
where
♦varistheloopvariable
♦stepisaconstantvalue
RepeatStatement
Therepeatstatementissupportedforconstantvaluesonly .
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Chapter16:XSTBehavioralVerilogLanguageSupport
DisableStatements
Disablestatementsarenotsupported.
CodingExample
modulecountzeros(a,Count);
input[7:0]a;
output[2:0]Count;
reg[2:0]Count;
reg[2:0]Count_Aux;
integeri;
always@(a)
begin
Count_Aux=3’b0;
for(i=0;i<8;i=i+1)
begin
if(!a[i])
Count_Aux=Count_Aux+1;
end
Count=Count_Aux;
end
endmodule
BehavioralVerilogWhileLoops
Whenusingalwaysblocks,usethewhilestatementtoexecuterepetitiveprocedures.A
whileloopexecutesotherstatementsuntilitstestexpressionbecomesfalse.Itisnot
executedifthetestexpressionisinitiallyfalse.
•ThetestexpressionisanyvalidVerilogexpression.
•Topreventendlessloops,use-loop_iteration_limit.
•whileloopscanhavedisablestatements.Thedisablestatementisusedinsidea
labeledblock,sincethesyntaxisdisable<blockname>.
CodingExample
parameterP=4;
always@(ID_complete)
begin:UNIDENTIFIED
integeri;
regfound;
unidentified=0;
i=0;
found=0;
while(!found&&(i<P))
begin
found=!ID_complete[i];
unidentified[i]=!ID_complete[i];
i=i+1;
end
end
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogSequentialAlwaysBlocks
Sequentialcircuitdescriptionisbasedonalwaysblockswithasensitivitylist.The
sensitivitylistcontainsamaximumofthreeedge-triggeredevents:
•Aclocksignalevent(mandatory)
•Aresetsignalevent(possibly)
•Asetsignalevent
One,andonlyone,if...elsestatementisacceptedinsuchanalwaysblock.
Anasynchronouspartmayappearbeforethesynchronouspartintherstandthe
secondbranchoftheif...elsestatement.Signalsassignedintheasynchronouspartare
assignedtothefollowingconstantvalues:
•0
•1
•X
•Z
•Anyvectorcomposedofthesevalues
Thesesamesignalsarealsoassignedinthesynchronouspart(thatis,thelastbranch
oftheif...elsestatement).Theclocksignalconditionistheconditionofthelastbranch
oftheif...elsestatement.
8BitRegisterUsinganAlwaysBlockBehavioralVerilogCodingExample
moduleseq1(DI,CLK,DO);
input[7:0]DI;
inputCLK;
output[7:0]DO;
reg[7:0]DO;
always@(posedgeCLK)
DO<=DI;
8BitRegisterwithAsynchronousReset(High-True)UsinganAlwaysBlock
BehavioralVerilogCodingExample
moduleEXAMPLE(DI,CLK,RST,DO);
input[7:0]DI;
inputCLK,RST;
output[7:0]DO;
reg[7:0]DO;
always@(posedgeCLKorposedgeRST)
if(RST==1’b1)
DO<=8’b00000000;
else
DO<=DI;
endmodule
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Chapter16:XSTBehavioralVerilogLanguageSupport
8BitCounterwithAsynchronousReset(Low-True)UsinganAlwaysBlock
BehavioralVerilogCodingExample
moduleseq2(CLK,RST,DO);
inputCLK,RST;
output[7:0]DO;
reg[7:0]DO;
always@(posedgeCLKorposedgeRST)
if(RST==1’b1)
DO<=8’b00000000;
else
DO<=DO+8’b00000001;
endmodule
BehavioralVerilogAssignandDeassignStatements
Assignanddeassignstatementsaresupportedwithinsimpletemplates.
BehavioralVerilogAssignandDeassignStatementsGeneralTemplate
moduleassig(RST,SELECT,STATE,CLOCK,DATA_IN);
inputRST;
inputSELECT;
inputCLOCK;
input[0:3]DATA_IN;
output[0:3]STATE;
reg[0:3]STATE;
always@(RST)
if(RST)
begin
assignSTATE=4’b0;
end
else
begin
deassignSTATE;
end
always@(posedgeCLOCK)
begin
STATE<=DATA_IN;
end
endmodule
Themainlimitationsonsupportoftheassign/deassignstatementinXSTare:
•Foragivensignal,thereisonlyoneassign/deassignstatement.
•Theassign/deassignstatementisperformedinthesamealwaysblockthroughan
if/elsestatement.
•Youcannotassignabit/partselectofasignalthroughanassign/deassignstatement.
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogAssign/DeassignStatement
Foragivensignal,thereisonlyoneassign/deassignstatement.Forexample,XSTrejects
thefollowingdesign:
moduledflop(RST,SET,STATE,CLOCK,DATA_IN);
inputRST;
inputSET;
inputCLOCK;
inputDATA_IN;
outputSTATE;
regSTATE;
always@(RST)//blockb1
if(RST)
assignSTATE=1’b0;
else
deassignSTATE;
always@(SET)//blockb1
if(SET)
assignSTATE=1’b1;
else
deassignSTATE;
always@(posedgeCLOCK)//blockb2
begin
STATE<=DATA_IN;
end
endmodule
BehavioralVerilogAssign/DeassignStatementPerformedinSame
AlwaysBlock
Theassign/deassignstatementisperformedinthesamealwaysblockthroughan
if...elsestatement.Forexample,XSTrejectsthefollowingdesign:
moduledflop(RST,SET,STATE,CLOCK,DATA_IN);
inputRST;
inputSET;
inputCLOCK;
inputDATA_IN;
outputSTATE;
regSTATE;
always@(RSTorSET)//blockb1
case({RST,SET})
2’b00:assignSTATE=1’b0;
2’b01:assignSTATE=1’b0;
2’b10:assignSTATE=1’b1;
2’b11:deassignSTATE;
endcase
always@(posedgeCLOCK)//blockb2
begin
STATE<=DATA_IN;
end
endmodule
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Chapter16:XSTBehavioralVerilogLanguageSupport
CannotAssignBit/PartSelectofSignalThroughAssign/Deassign
Statement
Youcannotassignabit/partselectofasignalthroughanassign/deassignstatement.For
example,XSTrejectsthefollowingdesign:
moduleassig(RST,SELECT,STATE,CLOCK,DATA_IN);
inputRST;
inputSELECT;
inputCLOCK;
input[0:7]DATA_IN;
output[0:7]STATE;
reg[0:7]STATE;
always@(RST)//blockb1
if(RST)
begin
assignSTATE[0:7]=8’b0;
end
else
begin
deassignSTATE[0:7];
end
always@(posedgeCLOCK)//blockb2
begin
if(SELECT)
STATE[0:3]<=DATA_IN[0:3];
else
STATE[4:7]<=DATA_IN[4:7];
end
BehavioralVerilogAssignmentExtensionPast32Bits
Iftheexpressionontheleft-handsideofanassignmentiswiderthantheexpressionon
theright-handside,theleft-handsideispaddedtotheleftaccordingtothefollowing
rules:
•Iftheright-handexpressionissigned,theleft-handexpressionispaddedwiththe
signbit:
–0forpositive
–1fornegative
–zforhighimpedance
–xforunknown
•Iftheright-handexpressionisunsigned,theleft-handexpressionispaddedwith
0(zeros).
•Forunsizedxorzconstantsonly,thefollowingruleapplies.Ifthevalueof
theright-handexpression’ sleftmostbitisz(highimpedance)orx(unknown),
regardlessofwhethertheright-handexpressionissignedorunsigned,theleft-hand
expressionispaddedwiththatvalue(zorx,respectively).
TheserulesfollowtheVerilog-2001standard.Theyarenotbackwardlycompatible
withVerilog-1995.
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogTasksandFunctions
Thedeclarationofafunctionortaskisintendedforhandlingblocksusedmultipletimes
inadesign.Theymustbedeclaredandusedinamodule.Theheadingpartcontainsthe
parameters:inputparameters(only)forfunctionsandinput/output/inoutparameters
fortasks.Thereturnvalueofafunctioncanbedeclaredeithersignedorunsigned.The
contentissimilartothecombinatorialalwaysblockcontent.
CodingExampleOne
Thefollowingcodingexampleshowsafunctiondeclaredwithinamodule.
•TheADDfunctiondeclaredisasingle-bitadder.
•Thisfunctioniscalledfourtimeswiththeproperparametersinthearchitecture
tocreatea4-bitadder.
modulecomb15(A,B,CIN,S,COUT);
input[3:0]A,B;
inputCIN;
output[3:0]S;
outputCOUT;
wire[1:0]S0,S1,S2,S3;
functionsigned[1:0]ADD;
inputA,B,CIN;
regS,COUT;
begin
S=A^B^CIN;
COUT=(A&B)|(A&CIN)|(B&CIN);
ADD={COUT,S};
end
endfunction
assignS0=ADD(A[0],B[0],CIN),
S1=ADD(A[1],B[1],S0[1]),
S2=ADD(A[2],B[2],S1[1]),
S3=ADD(A[3],B[3],S2[1]),
S={S3[0],S2[0],S1[0],S0[0]},
COUT=S3[1];
endmodule
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Chapter16:XSTBehavioralVerilogLanguageSupport
CodingExampleTwo
ThefollowingcodingexampleshowsCodingExampleOnedescribedwithatask.
moduleEXAMPLE(A,B,CIN,S,COUT);
input[3:0]A,B;
inputCIN;
output[3:0]S;
outputCOUT;
reg[3:0]S;
regCOUT;
reg[1:0]S0,S1,S2,S3;
taskADD;
inputA,B,CIN;
output[1:0]C;
reg[1:0]C;
regS,COUT;
begin
S=A^B^CIN;
COUT=(A&B)|(A&CIN)|(B&CIN);
C={COUT,S};
end
endtask
always@(AorBorCIN)
begin
ADD(A[0],B[0],CIN,S0);
ADD(A[1],B[1],S0[1],S1);
ADD(A[2],B[2],S1[1],S2);
ADD(A[3],B[3],S2[1],S3);
S={S3[0],S2[0],S1[0],S0[0]};
COUT=S3[1];
end
endmodule
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogRecursiveTasksandFunctions
Verilog-2001supportsrecursivetasksandfunctions.
Youcanuserecursiononlywiththeautomatickeyword.
Topreventendlessrecursivecalls,thenumberofrecursionsislimitedbydefaultto64.
Use-recursion_iteration_limittocontrolthenumberofallowedrecursivecalls.
CodingExample
functionautomatic[31:0]fac;
input[15:0]n;
if(n==1)
fac=1;
else
fac=n*fac(n-1);//recursivefunctioncall
endfunction
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogConstantFunctions
Verilog-2001addssupportforconstantfunctions.XSTsupportsfunctioncallsto
calculateconstantvalues.
CodingExample
modulerams_cf(clk,we,a,di,do);
parameterDEPTH=1024;
inputclk;
inputwe;
input[4:0]a;
input[3:0]di;
output[3:0]do;
reg[3:0]ram[size(DEPTH):0];
always@(posedgeclk)begin
if(we)
ram[a]<=di;
end
assigndo=ram[a];
functionintegersize;
inputdepth;
integeri;
begin
size=1;
for(i=0;2**i<depth;i=i+1)
size=i+1;
end
endfunction
endmodule
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogBlockingVersusNon-BlockingProcedural
Assignments
Thepound(#)andatsymbol(@)timecontrolstatementsdelayexecutionofthe
statementfollowingthemuntilthespeciedeventisevaluatedastrue.Blockingand
non-blockingproceduralassignmentshavetimecontrolbuiltintotheirrespective
assignmentstatement.Thepound(#)delayisignoredforsynthesis.
BehavioralVerilogBlockingProceduralAssignmentSyntaxExample
Thesyntaxforablockingproceduralassignmentisshowninthefollowingexample.
rega;a=#10(b|c);
or
if(in1)out=1’b0;elseout=in2;
Asthenameimplies,thesetypesofassignmentsblockthecurrentprocessfrom
continuingtoexecuteadditionalstatementsatthesametime.Theseshouldmainlybe
usedinsimulation.
Non-blockingassignments,ontheotherhand,evaluatetheexpressionwhenthe
statementexecutes,butallowotherstatementsinthesameprocesstoexecuteaswellat
thesametime.Thevariablechangeoccursonlyafterthespecieddelay.
BehavioralVerilogNon-BlockingProceduralAssignmentSyntaxExample
Thefollowingsyntaxexampleshowsthesyntaxforanon-blockingprocedural
assignment.
variable<=@(posedge_or_negedge_bit)expression;
CodingExample
Thefollowingcodingexampleshowshowtouseanon-blockingproceduralassignment.
if(in1)out<=1’b1;elseout<=in2;
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogConstants
Bydefault,constantsinVerilogareassumedtobedecimalintegers.Theycanbe
speciedexplicitlyinbinary,octal,decimal,orhexadecimalbyprefacingthemwiththe
appropriatesyntax.Forexample,thefollowingallrepresentthesamevalue:
•4’b1010
•4’o12
•4’d10
•4’ha
BehavioralVerilogMacros
Verilogprovidesawaytodenemacrosasshowninthefollowingcodingexample.
‘defineTESTEQ14’b1101
Laterinthedesigncode,areferencetothedenedmacroismadeasfollows:
if(request==‘TESTEQ1)
Thisisshowninthefollowingcodingexample.
‘definemyzero0
assignmysig=‘myzero;
TheVerilog‘ifdefand‘endifconstructsdeterminewhetherornotamacroisdened.
Theseconstructsareusedtodeneconditionalcompilation.Ifthemacrocalledoutby
the‘ifdefcommandhasbeendened,thatcodeiscompiled.Ifnot,thecodefollowing
the‘elsecommandiscompiled.The‘elseisnotrequired,but‘endifmustcomplete
theconditionalstatement.
The‘ifdefand‘endifconstructsareshowninthefollowingcodingexample.
‘ifdefMYVAR
moduleif_MYVAR_is_declared;
...
endmodule
‘else
moduleif_MYVAR_is_not_declared;
...
endmodule
‘endif
VerilogMacros(-dene)allowsyoutodene(orredene)Verilogmacros.Thisallows
youtoeasilymodifythedesigncongurationwithoutanyHardwareDescription
Language(HDL)sourcemodications,suchasforIPcoregenerationandtestingows.
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogIncludeFiles
Verilogallowsyoutoseparatesourcecodeintomorethanonele.Toreferencethecode
containedinanotherle,usethefollowingsyntaxinthecurrentle:
‘include"path/le-to-be-included"
Thepathcanberelativeorabsolute.
Multiple‘includestatementsareallowedinasingleVerilogle.Thisfeaturemakes
yourcodemoremanageableinateamdesignenvironmentwheredifferentlesdescribe
differentmodulesofthedesign.
IdentifyingtheDirectory
Toenabletheleinyour‘includestatementtoberecognized,identifythedirectory
whereitresides,eithertoISE®DesignSuiteortoXST.
•SinceISEDesignSuitesearchestheISEDesignSuiteprojectdirectorybydefault,
addingtheletoyourprojectdirectoryidentiestheletoISEDesignSuite
•TodirectISEDesignSuitetoadifferentdirectory,includeapath(relativeor
absolute)inthe‘includestatementinyoursourcecode.
•TopointXSTdirectlytoyourincludeledirectory,useVerilogIncludeDirectories
(-vlgincdir)
•Ifthe‘includeleisrequiredforISEDesignSuitetoconstructthedesignhierarchy,
theleneednotbeaddedtotheproject,butthelemusteither:
–Resideintheprojectdirectory
or
–Bereferencedbyarelativeorabsolutepath
IncludeFileConflicts
Conictsmayoccurwhenthespeciedle:
•HasbeenaddedtoanISEDesignSuiteprojectdirectory
and
•Isspeciedwith‘include
CodingExample
‘timescale1ns/1ps
‘include"modules.v"
...
XSTissuesanerrormessage:
ERROR:Xst:1068-fifo.v,line2.Duplicatedeclarationsof
module’RAMB4_S8_S8’
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogComments
BehavioralVerilogsupportstwoformsofcommentsasshowninthefollowingtable.
BehavioralVerilogcommentsaresimilartothecommentsusedinalanguagesuchas
C++.
SymbolDescriptionUsedforExample
//Doubleforward
slash
One-linecomments//Deneaone-linecommentasillustratedbythissentence
/*SlashasteriskMulti-linecomments/*Deneamulti-linecommentbyenclosingitasillustrated
bythissentence*/
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Chapter16:XSTBehavioralVerilogLanguageSupport
BehavioralVerilogGenerateStatements
AgeneratestatementallowsyoutodynamicallycreateVerilogcodefromconditional
statements.Thisallowsyoutocreaterepetitivestructuresorstructuresthatare
appropriateonlyundercertainconditions.
Structureslikelytobecreatedusingageneratestatementare:
•Primitiveormoduleinstances
•Initialoralwaysproceduralblocks
•Continuousassignments
•Netandvariabledeclarations
•Parameterredenitions
•Taskorfunctiondenitions
GenerateForStatements
UseaBehavioralVeriloggenerateforlooptocreateoneormoreinstancesthatcanbe
placedinsideamodule.Usethegenerateforloopthesamewayyouwouldanormal
Verilogforloop,withthefollowinglimitations:
•Theindexforagenerateforloophasagenvarvariable.
•Theassignmentsintheforloopcontrolreferstothegenvarvariable.
•Thecontentsoftheforloopareenclosedbybeginandendstatements.Thebegin
statementisnamedwithauniquequalier.
CodingExample
Followingisan8-bitadderusingagenerateforloopbehavioralVerilogcodingexample.
generate
genvari;
for(i=0;i<=7;i=i+1)
begin:for_name
adderadd(a[8*i+7:8*i],b[8*i+7:8*i],ci[i],sum_for[8*i+7:8*i],c0_or[i+1]);end
endgenerate
GenerateIf...elseStatements
UseaBehavioralVeriloggenerateif...elsestatementinsideagenerateblockto
conditionallycontrolwhichobjectsaregenerated.
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Chapter16:XSTBehavioralVerilogLanguageSupport
CodingExample
Inthefollowingcodingexampleofagenerateif...elsestatement:
•generatecontrolsthetypeofmultiplierthatisinstantiated
•Thecontentsofeachbranchoftheif...elsestatementareenclosedbybeginand
endstatements.
•Thebeginstatementisnamedwithauniquequalier.
generate
if(IF_WIDTH<10)
begin:if_name
adder#(IF_WIDTH)u1(a,b,sum_if);
end
else
begin:else_name
subtractor#(IF_WIDTH)u2(a,b,sum_if);
end
endgenerate
GenerateCaseStatements
UseaBehavioralVeriloggeneratecasestatementinsideagenerateblocktoconditionally
controlwhichobjectsaregenerated.Useageneratecasestatementwhenthereare
severalconditionstobetestedtodeterminewhatthegeneratedcodewouldbe.
•Eachteststatementinageneratecaseisenclosedbybeginandendstatements.
•Thebeginstatementisnamedwithauniquequalier.
CodingExample
Inthefollowingcodingexampleofageneratecasestatement,generatecontrolsthe
typeofadderthatisinstantiated:
generate
case(WIDTH)
1:
begin:case1_name
adder#(WIDTH*8)x1(a,b,ci,sum_case,c0_case);
end
2:
begin:case2_name
adder#(WIDTH*4)x2(a,b,ci,sum_case,c0_case);
end
default:
begin:d_case_name
adderx3(a,b,ci,sum_case,c0_case);
end
endcase
endgenerate
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Chapter17
XSTMixedLanguageSupport
ThischapterdiscussesXSTMixedLanguageSupport,andincludes:
•AboutXSTMixedLanguageSupport
•MixedLanguageProjectFiles
•VHDLandVerilogBoundaryRulesinMixedLanguageProjects
•PortMappinginMixedLanguageProjects
•GenericsSupportinMixedLanguageProjects
•LSOFilesinMixedLanguageProjects
AboutXSTMixedLanguageSupport
XSTsupportsmixedVHDLandVerilogprojects.
•MixingVHDLandVerilogisrestrictedtodesignunit(cell)instantiationonly.
–AVHDLdesigncaninstantiateaVerilogmodule.
–AVerilogdesigncaninstantiateaVHDLentity .
–NoothermixingbetweenVHDLandVerilogisnotsupported.
•InaVHDLdesign,arestrictedsubsetofVHDLtypes,generics,andportsisallowed
ontheboundarytoaVerilogmodule.
•InaVerilogdesign,arestrictedsubsetofVerilogtypes,parameters,andportsis
allowedontheboundarytoaVHDLentityorconguration.
•XSTbindsVHDLdesignunitstoaVerilogmoduleduringElaboration.
•ComponentinstantiationbasedondefaultbindingisusedforbindingVerilog
modulestoaVHDLdesignunit.
•Congurationspecication,directinstantiationandcomponentcongurationsare
notsupportedforaVerilogmoduleinstantiationinVHDL.
•VHDLandVerilogprojectlesareunied.
•VHDLandVeriloglibrariesarelogicallyunied.
•Specicationoftheworkdirectoryforcompilation(xsthdpdir),previously
availableonlyforVHDL,isnowavailableforVerilog.
•Thexhdp.inimechanismformappingalogicallibrarynametoaphysicaldirectory
nameonthehostlesystem,previouslyavailableonlyforVHDL,isnowavailable
forVerilog.
•Mixedlanguageprojectsacceptasearchorderusedforsearchinguniedlogical
librariesindesignunits(cells).DuringElaboration,XSTfollowsthissearchorder
forpickingandbindingaVHDLentityoraVerilogmoduletothemixedlanguage
project.
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Chapter17:XSTMixedLanguageSupport
MixedLanguageProjectFiles
XSTusesdedicatedmixedlanguageprojectlestosupportmixedVHDLandVerilog
designs.Youcanusethismixedlanguageformatnotonlyformixedprojects,butalso
forpurelyVHDLorVerilogprojects.
•IfyourunXSTfromISE®DesignSuite,XSTcreatestheprojectle.Itisalways
amixedlanguageprojectle.
•IfyourunXSTfromthecommandline,youmustcreatethemixedlanguageproject
leyourself.
ProjectTypeSet-ifmtto
commandlinemixedorvalueomitted
VHDLvhdl
Verilogverilog
TheVHDLandVerilogformatscanbeusedforexistingdesigns.
Thesyntaxforinvokingalibraryoranyexternalleinamixedlanguageprojectis:
languagelibraryle_name.ext
CodingExample
Thefollowingexampleshowshowtoinvokelibrariesinamixedlanguageproject.
vhdlworkmy_vhdl1.vhd
verilogworkmy_vlg1.v
vhdlmy_vhdl_libmy_vhdl2.vhd
verilogmy_vlg_libmy_vlg2.v
•EachrowspeciesasingleHardwareDescriptionLanguage(HDL)designle.
•Eachcolumnhasthemeaningshowninthefollowingtable.
ColumnSyntaxExampleSpecifies
FirstlanguagevhdlWhethertheHDLle
isVHDLorVerilog
SecondlibraryworkThelogiclibrary
wheretheHDLis
compiled.Thedefault
logiclibraryiswork.
Thirdle_name.extmy_vhdl1.vhdThenameoftheHDL
le.
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Chapter17:XSTMixedLanguageSupport
VHDLandVerilogBoundaryRulesinMixedLanguageProjects
TheboundarybetweenVHDLandVerilogisenforcedatthedesignunitlevel.
AVHDLdesigncaninstantiateaVerilogmodule.
AVerilogdesigncaninstantiateaVHDLentity.
InstantiatingaVerilogModuleinaVHDLDesign
ToinstantiateaVerilogmoduleinaVHDLdesign:
1.DeclareaVHDLcomponentwiththesamename(respectingcasesensitivity)as
theVerilogmoduleyouwanttoinstantiate.IftheVerilogmodulenameisnotall
lowercase,usethecasepropertytopreservethecaseofyourVerilogmodule.
a.InISE®DesignSuite,select:
Process>ProcessProperties>SynthesisOptions>Case>Maintain
or
b.Setthe-casecommandlineoptiontomaintain
2.InstantiatetheVerilogcomponentasifyouwereinstantiatingaVHDLcomponent.
UsingaVHDLcongurationdeclaration,youcouldattempttobindthiscomponenttoa
particulardesignunitfromaparticularlibrary .Suchbindingisnotsupported.Only
defaultVerilogmodulebindingissupported.
TheonlyVerilogconstructthatcanbeinstantiatedinaVHDLdesignisaVerilog
module.NootherVerilogconstructsarevisibletoVHDLcode.
Duringelaboration,allcomponentssubjecttodefaultbindingareregardedasdesign
unitswiththesamenameasthecorrespondingcomponentname.Duringbinding,XST
treatsacomponentnameasaVHDLdesignunitnameandsearchesforitinthelogical
librarywork.IfXSTndsaVHDLdesignunit,XSTbindsit.IfXSTcannotndaVHDL
designunit,ittreatsthecomponentnameasaVerilogmodulename,andsearchesforit
usingacasesensitivesearch.XSTsearchesfortheVerilogmoduleintheuser-specied
listofuniedlogicallibrariesintheuser-speciedsearchorder.
Formoreinformation,see:
LibrarySearchOrder(LSO)FilesinMixedLanguageProjects
XSTselectstherstVerilogmodulematchingthename,andbindsit.
Sincelibrariesareunied,aVerilogcellbythesamenameasthatofaVHDLdesign
unitcannotco-existinthesamelogicallibrary.Anewlycompiledcell/unitoverridesa
previouslycompiledone.
InstantiatingaVHDLDesignUnitinaVerilogDesign
Thissectionincludes:
•HowtoInstantiateaVHDLEntity
•Binding
•Limitations
HowtoInstantiateaVHDLEntity
ToinstantiateaVHDLentity:
1.DeclareamodulenamewiththesameasnameastheVHDLentity(optionally
followedbyanarchitecturename)thatyouwanttoinstantiate.
2.PerformanormalVeriloginstantiation.
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Chapter17:XSTMixedLanguageSupport
TheonlyVHDLconstructthatcanbeinstantiatedinaVerilogdesignisaVHDLentity.
NootherVHDLconstructsarevisibletoVerilogcode.Whenyoudothis,XSTusesthe
entity/architecturepairastheVerilog/VHDLboundary .
Binding
XSTperformsthebindingduringelaboration.
XSTrst:
1.SearchesforaVerilogmoduleasfollows:
•Usesthenameoftheinstantiatedmodule.
•Searchesintheuser-speciedlistofuniedlogicallibraries.
•Searchesintheuser-speciedorder.
•Ignoresanyarchitecturenamespeciedinthemoduleinstantiation.
2.Bindsthenameiffound.
IfXSTcannotndaVerilogmodule,thenXST:
1.TreatsthenameoftheinstantiatedmoduleasaVHDLentity.
2.SearchesfortheVHDLentityasfollows:
•Performsacasesensitivesearch
•Searchesintheuser-speciedlistofuniedlogicallibraries
•Searchesintheuser-speciedorder
NoteThisassumesthataVHDLdesignunitwasstoredwithanextendedidentier.
3.SelectstherstVHDLentitymatchingthename.
4.Bindstheentity.
Formoreinformation,see:
LibrarySearchOrder(LSO)FilesinMixedLanguageProjects
Limitations
XSThasthefollowinglimitationswheninstantiatingaVHDLdesignunitfromaVerilog
module:
•Useexplicitportassociation.Specifyformalandeffectiveportnamesintheport
map.
•Allparametersarepassedatinstantiation,eveniftheyareunchanged.
•Theparameteroverrideisnamedandnotordered.Theparameteroverrideoccurs
throughinstantiation,andnotthroughdefparams.
CorrectUseofParameterOverrideCodingExample
ff#(.init(2’b01))u1(.sel(sel),.din(din),.dout(dout));
IncorrectUseofParameterOverrideCodingExample
XSTdoesnotacceptthefollowing:
ffu1(.sel(sel),.din(din),.dout(dout));
defparamu1.init=2’b01;
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Chapter17:XSTMixedLanguageSupport
PortMappinginMixedLanguageProjects
PortMappinginmixedlanguageprojectsincludes:
•VHDLinVerilogPortMapping
•VeriloginVHDLPortMapping
•VHDLinMixedLanguagePortMapping
•VeriloginMixedLanguagePortMapping
VHDLinVerilogPortMapping
ForVHDLentitiesinstantiatedinVerilogdesigns,XSTsupportsthefollowingporttypes:
•in
•out
•inout
XSTdoesnotsupportVHDLbufferandlinkageports.
VeriloginVHDLPortMapping
ForVerilogmodulesinstantiatedinVHDLdesigns,XSTsupportsthefollowingport
types:
•input
•output
•inout
XSTdoesnotsupportconnectiontobi-directionalpassoptionsinVerilog.
XSTdoesnotsupportunnamedVerilogportsformixedlanguageboundaries.
Useanequivalentcomponentdeclarationforconnectingtoacasesensitiveportina
Verilogmodule.Bydefault,XSTassumesVerilogportsareinalllowercase.
VHDLinMixedLanguagePortMapping
XSTsupportsthefollowingVHDLdatatypesformixedlanguagedesigns:
•bit
•bit_vector
•std_logic
•std_ulogic
•std_logic_vector
•std_ulogic_vector
VeriloginMixedLanguagePortMapping
XSTsupportsthefollowingVerilogdatatypesformixedlanguagedesigns:
•wire
•reg
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Chapter17:XSTMixedLanguageSupport
GenericsSupportinMixedLanguageProjects
XSTsupportsthefollowingVHDLgenerictypesandtheirVerilogequivalentsformixed
languagedesigns:
•integer
•real
•string
•boolean
LSOFilesinMixedLanguageProjects
TheLibrarySearchOrder(LSO)lespeciesthesearchorderthatXSTusestolinkthe
librariesusedinVHDLandVerilogmixedlanguagedesigns.Bydefault,XSTsearches
thelesspeciedintheprojectleintheorderinwhichtheyappearinthatle.
XSTusesthedefaultsearchorderwhen:
•TheDEFAULT_SEARCH_ORDERkeywordisusedintheLSOle,or
•TheLSOleisnotspecied
SpecifyingtheLSOFileinISEDesignSuite
InISE®DesignSuite,thedefaultnamefortheLibrarySearchOrder(LSO)leis
project_name.lso.Ifaproject_name.lsoledoesnotalreadyexist,ISEDesign
Suiteautomaticallycreatesone.
IfISEDesignSuitedetectsanexistingproject_name.lsole,thisleispreservedand
usedasis.InISEDesignSuite,thenameoftheprojectisthenameofthetop-levelblock.
IncreatingadefaultLSOle,ISEDesignSuiteplacestheDEFAULT_SEARCH_ORDER
keywordintherstlineofthele.
SpecifyingtheLSOFileintheCommandLine
LibrarySearchOrder(LSO)(-lso)speciestheLibrarySearchOrder(LSO)lewhen
runningXSTfromthecommandline.If-lsoisomitted,XSTusesthedefaultlibrary
searchorderwithoutusinganLSOle.
LSORules
Whenprocessingamixedlanguageproject,XSTobeysthefollowingsearchorderrules,
dependingonthecontentsoftheLibrarySearchOrder(LSO)le:
•LibrarySearchOrder(LSO)Empty
•DEFAULT_SEARCH_ORDERKeywordOnly
•DEFAULT_SEARCH_ORDERKeywordandListofLibraries
•ListofLibrariesOnly
•DEFAULT_SEARCH_ORDERKeywordandNon-ExistentLibraryName”
LibrarySearchOrder(LSO)Empty
WhentheLibrarySearchOrder(LSO)leisempty,XST:
•IssuesawarningstatingthattheLSOleisempty
•Searchesthelesspeciedintheprojectleusingthedefaultlibrarysearchorder
•UpdatestheLSOlebyaddingthelistoflibrariesintheorderthattheyappear
intheprojectle.
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Chapter17:XSTMixedLanguageSupport
DEFAULT_SEARCH_ORDERKeywordOnly
WhentheLibrarySearchOrder(LSO)lecontainsonlytheDEFAULT_SEARCH_ORDER
keyword,XST:
•Searchesthespeciedlibrarylesintheorderinwhichtheyappearintheprojectle
•UpdatestheLSOleby:
–RemovingtheDEFAULT_SEARCH_ORDERkeyword
–AddingthelistoflibrariestotheLSOleintheorderinwhichtheyappear
intheprojectle
Foraprojectle,my_proj.prj,withthefollowingcontents:
vhdlvhlib1f1.vhdverilogrtfllibf1.vvhdlvhlib2f3.vhdLSO
fileCreatedbyProjNav
andanLSOle,my_proj.lso,createdbyISE®DesignSuite,withthefollowing
contents:
DEFAULT_SEARCH_ORDER
XSTusesthefollowingsearchorder.
vhlib1rtfllibvhlib2
Afterprocessing,thecontentsofmy_proj.lsois:
vhlib1rtfllibvhlib2
DEFAULT_SEARCH_ORDERKeywordandListofLibraries
WhentheLibrarySearchOrder(LSO)lecontainstheDEFAULT_SEARCH_ORDER
keyword,andalistofthelibraries,XST:
•Searchesthespeciedlibrarylesintheorderinwhichtheyappearintheprojectle
•IgnoresthelistoflibrarylesintheLSOle
•LeavestheLSOleunchanged
Foraprojectle,my_proj.prj,withthefollowingcontents:
vhdlvhlib1f1.vhdverilogrtfllibf1.vvhdlvhlib2f3.vhd
andanLSOle,my_proj.lso,createdwiththefollowingcontents:
rtfllibvhlib2vhlib1DEFAULT_SEARCH_ORDER
XSTusesthefollowingsearchorder:
vhlib1rtfllibvhlib2
Afterprocessing,thecontentsofmy_proj.lsois:
rtfllibvhlib2vhlib1DEFAULT_SEARCH_ORDER
ListofLibrariesOnly
WhentheLibrarySearchOrder(LSO)lecontainsalistofthelibrarieswithoutthe
DEFAULT_SEARCH_ORDERkeyword,XST:
•SearchesthelibrarylesintheorderinwhichtheyappearintheLSOle
•LeavestheLSOleunchanged
Foraprojectle,my_proj.prj,withthefollowingcontents:
vhdlvhlib1f1.vhdverilogrtfllibf1.vvhdlvhlib2f3.vhd
andanLSOle,my_proj.lso,createdwiththefollowingcontents:
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Chapter17:XSTMixedLanguageSupport
rtfllibvhlib2vhlib1
XSTusesthefollowingsearchorder:
rtfllibvhlib2vhlib1
Afterprocessing,thecontentsofmy_proj.lsois:
rtfllibvhlib2vhlib1
DEFAULT_SEARCH_ORDERKeywordandNon-ExistentLibraryName
WhentheLibrarySearchOrder(LSO)lecontainsalibrarynamethatdoesnotexistin
theprojectorINIle,andtheLSOledoesnotcontaintheDEFAULT_SEARCH_ORDER
keyword,XSTignoresthelibrary.
Foraprojectle,my_proj.prj,withthefollowingcontents:
vhdlvhlib1f1.vhdverilogrtfllibf1.vvhdlvhlib2f3.vhd
andanLSOle,my_proj.lso,createdwiththefollowingcontents:
personal_librtfllibvhlib2vhlib1
XSTusesthefollowingsearchorder:
rtfllibvhlib2vhlib1
Afterprocessing,thecontentsofmy_proj.lsois:
rtfllibvhlib2vhlib1
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Chapter18
XSTLogFile
ThischapterdiscussestheXSTLogFile,andincludes:
•XSTLogFileContents
•ReducingtheSizeoftheXSTLogFile
•MacrosinXSTLogFiles
•XSTLogFileExamples
XSTFPGALogFileContents
TheXSTFPGAloglecontains:
•CopyrightStatement
•TableofContents
•SynthesisOptionsSummary
•HDLCompilation
•DesignHierarchyAnalyzer
•HDLAnalysis
•HDLSynthesisReport
•AdvancedHDLSynthesisReport
•LowLevelSynthesis
•PartitionReport
•FinalReport
CopyrightStatement
TheXSTFPGAloglecopyrightstatementcontains:
•ISE®DesignSuitereleasenumber
•Xilinx®noticeofcopyright
TableofContents
TheXSTFPGAlogletableofcontentsliststhemajorsectionsinthelogle.These
headingsarenotlinked.UsetheFindfunctioninyourtexteditor.
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Chapter18:XSTLogFile
SynthesisOptionsSummary
TheXSTFPGAlogleSynthesisOptionsSummarycontainsinformationrelatingto:
•SourceParameters
•TargetParameters
•SourceOptions
•TargetOptions
•GeneralOptions
•OtherOptions
HDLCompilation
ForinformationonHardwareDescriptionLanguage(HDL)Compilation,see:
XSTFPGALogFileHDLAnalysis
DesignHierarchyAnalyzer
ForinformationonDesignHierarchyAnalyzer,see:
XSTFPGALogFileHDLAnalysis
HDLAnalysis
DuringHardwareDescriptionLanguage(HDL)Compilation,DesignHierarchy
Analyzer,andHDLAnalysis,XST:
•ParsesandanalyzesVHDLandVerilogles
•Recognizesthedesignhierarchy
•Givesthenamesofthelibrariesintowhichtheyarecompiled
Duringthisstep,XSTmayreport:
•Potentialmismatchesbetweensynthesisandsimulationresults
•Potentialmulti-sources
•Otherissues
HDLSynthesisReport
DuringHardwareDescriptionLanguage(HDL)Synthesis,XSTtriestorecognizeas
manybasicmacrosaspossibletocreateatechnology-specicimplementation.Thisis
doneonablockbyblockbasis.Attheendofthisstep,XSTissuestheHDLSynthesis
Report.
Formoreinformationabouttheprocessingofeachmacroandthecorresponding
messagesissuedduringsynthesis,see:
XSTHDLCodingTechniques
AdvancedHDLSynthesisReport
XSTperformsadvancedmacrorecognitionandinference.Inthisstep,XST:
•Recognizes,forexample,dynamicshiftregisters
•Implementspipelinedmultipliers
•Codesstatemachines
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Chapter18:XSTLogFile
TheAdvancedHDLSynthesisReportcontainsasummaryofrecognizedmacrosin
theoveralldesign,sortedbymacrotype.
LowLevelSynthesis
IntheXSTFPGALogFileLowLevelSynthesisphase,XSTreportsthepotentialremoval
of,forexample:
•equivalentip-ops
•registerreplication
Formoreinformation,see:
FPGAOptimizationReportSection
PartitionReport
Ifthedesignispartitioned,theXSTFPGAloglePartitionReportcontainsinformation
detailingthedesignpartitions.
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Chapter18:XSTLogFile
FinalReport
TheXSTFPGAlogleFinalReportincludes:
•FinalResults,including
–RTLTopLevelOutputFileName(forexample,stopwatch.ngr)
–TopLevelOutputFileName(forexample,stopwatch)
–OutputFormat(forexample,NGC)
–OptimizationGoal(forexample,Speed)
–WhethertheKeepHierarchyconstraintisused(forexample,No)
•Cellusage
Cellusagereportson,forexample,thenumberandtypeofBELS,ClockBuffers,
andIOBuffers.
•DeviceUtilizationSummary
TheDeviceUtilizationSummaryestimatesthenumberofslices,andgives,for
example,thenumberofip-ops,IOBs,andBRAMS.TheDeviceUtilization
SummarycloselyapproximatesthereportproducedbyMAP .
•PartitionResourceSummary
ThePartitionResourceSummaryestimatesthenumberofslices,andgives,for
example,thenumberofip-ops,IOBs,andBRAMSforeachpartition.The
PartitionResourceSummarycloselyresemblesthereportproducedbyMAP .
•TimingReport
Attheendofsynthesis,XSTreportsthetiminginformationforthedesign.The
TimingReportshowstheinformationforallfourpossibledomainsofanetlist:
–registertoregister
–inputtoregister
–registertooutpad
–inpadtooutpad
Foranexample,see:
TimingReportsectioninXSTFPGALogFileExample
Formoreinformation,see:
FPGAOptimizationReportSection
•EncryptedModules
Ifadesigncontainsencryptedmodules,XSThidestheinformationaboutthese
modules.
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Chapter18:XSTLogFile
ReducingtheSizeoftheXSTLogFile
ToreducethesizeoftheXSTLogFile:
•UseMessageFiltering
•UseQuietMode
•UseSilentMode
•HideSpecicMessages
UseMessageFiltering
WhenrunningXSTfromISE®DesignSuite,usetheMessageFilteringwizardtolter
specicmessagesoutofthelogle.
Formoreinformation,see:
UsingtheMessageFiltersintheISEDesignSuiteHelp
UseQuietMode
QuietModelimitsthenumberofmessagesprintedtothecomputerscreen(stdout).
ToinvokeQuietMode,set-intstyletoeitherofthefollowing:
•ise
FormatsmessagesforISE®DesignSuite
•xow
FormatsmessagesforXFLOW
Normally,XSTprintstheentirelogtostdout.InQuietMode,XSTdoesnotprintthe
followingportionsofthelogtostdout:
•CopyrightMessage
•TableofContents
•SynthesisOptionsSummary
•ThefollowingportionsoftheFinalReport
–FinalResultsheaderforCPLDdevices
–FinalResultssectionforFPGAdevices
–AnoteintheTimingReportstatingthatthetimingnumbersareonlyasynthesis
estimate.
–TimingDetail
–CPU(XSTruntime)
–Memoryusage
ThefollowingsectionsarestillavailableforFPGAdevices:
•DeviceUtilizationSummary
•ClockInformation
•TimingSummary
UseSilentMode
SilentModepreventsanymessagesfrombeingsenttothecomputerscreen(stdout),
althoughXSTcontinuestogeneratetheentirelogle.
ToinvokeSilentMode,setthe-intstylecommandlineoptionto:
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Chapter18:XSTLogFile
silent
HideSpecificMessages
Thissectionincludes:
•XIL_XST_HIDEMESSAGESEnvironmentVariableValues
•MessagesHiddenWhenValueisSettohdl_levelandhdl_and_low_levels
•MessagesHiddenWhenValueisSettolow_levelorhdl_and_low_levels
XIL_XST_HIDEMESSAGESEnvironmentVariableValues
TohidespecicmessagesattheHDLorLowLevelSynthesissteps,setthe
XIL_XST_HIDEMESSAGESenvironmentvariabletooneofthevaluesshowninthe
followingtable.
ValueMeaning
none(default)Maximumverbosity .Allmessagesareprinted
out.
hdl_levelReduceverbosityduringVHDLorVerilog
AnalysisandHDLBasicandAdvanced
Synthesis.
low_levelReduceverbosityduringLow-levelSynthesis.
hdl_and_low_levelsReduceverbosityatallstages.
MessagesHiddenWhenValueisSettohdl_levelandhdl_and_low_levels
ThefollowingmessagesarehiddenwhenthevalueoftheXIL_XST_HIDEMESSAGES
environmentvariableissettohdl_levelandhdl_and_low_levels:
•WARNING:HDLCompilers:38-design.vline5Macro’my_macro’
redefined
NoteThismessageisissuedbytheVerilogcompileronly.
•WARNING:Xst:916-design.vhdline5:Delayisignoredfor
synthesis.
•WARNING:Xst:766-design.vhdline5:GeneratingaBlackBox
forcomponentcomp.
•InstantiatingcomponentcompfromLibrarylib.
•Setuser-definedproperty"LOC=X1Y1"forinstanceinstin
unitblock.
•Setuser-definedproperty"RLOC=X1Y1"forinstanceinstin
unitblock.
•Setuser-definedproperty"INIT=1"forinstanceinstinunit
block.
•Registerreg1equivalenttoreg2hasbeenremoved.
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Chapter18:XSTLogFile
MessagesHiddenWhenValueisSettolow_levelorhdl_and_low_levels
ThefollowingmessagesarehiddenwhenthevalueoftheXIL_XST_HIDEMESSAGES
environmentvariableissettolow_levelorhdl_and_low_levels:
•WARNING:Xst:382-Registerreg1isequivalenttoreg2.
Registerreg1equivalenttoreg2hasbeenremoved.
•WARNING:Xst:1710-FF/Latchreg(withoutinitvalue)is
constantinblockblock.
•WARNING:Xst1293-FF/Latchregisconstantinblockblock.
•WARNING:Xst:1291-FF/Latchregisunconnectedinblockblock.
•WARNING:Xst:1426-ThevalueinitoftheFF/Latchreghinders
theconstantcleaningintheblockblock.Youcouldachieve
betterresultsbysettingthisinittovalue.
MacrosinXSTLogFiles
XSTLogFilescontaindetailedinformationaboutthesetofmacrosandassociated
signalsinferredbyXSTfromtheVHDLorVerilogsourceonablockbyblockbasis.
Macroinferenceisdoneintwosteps:
1.HDLSynthesis
XSTrecognizesasmanysimplemacroblocksaspossible,suchasadders,
subtractors,andregisters.
2.AdvancedHDLSynthesis
XSTdoesadditionalmacroprocessingbyimprovingthemacros(forexample,
pipeliningofmultipliers)recognizedattheHDLsynthesisstep,orbycreating
thenew,morecomplexones,suchasdynamicshiftregisters.TheMacro
RecognitionreportattheAdvancedHDLSynthesisstepisformattedthesameas
thecorrespondingreportattheHDLSynthesisstep.
XSTgivesoverallstatisticsofrecognizedmacrostwice:
•AftertheHDLSynthesisstep
•AftertheAdvancedHDLSynthesisstep
XSTnolongerlistsstatisticsofpreservedmacrosinthenalreport.
XSTLogFileExamples
Thissectionincludes:
•RecognizedMacrosXSTLogFileExample
•AdditionalMacroProcessingXSTLogFileExample
•XSTFPGALogFileExample
•XSTCPLDLogFileExample
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Chapter18:XSTLogFile
RecognizedMacrosXSTLogFileExample
Thefollowinglogleexampleshowsthesetofrecognizedmacrosonablockbyblock
basis,aswellastheoverallmacrostatisticsafterthisstep.
===================================================
*HDLSynthesis*
===================================================
...
SynthesizingUnit<decode>.
Relatedsourcefileis"decode.vhd".
Found16x10-bitROMforsignal<one_hot>.
Summary:
inferred1ROM(s).
Unit<decode>synthesized.
SynthesizingUnit<statmach>.
Relatedsourcefileis"statmach.vhd".
Foundfinitestatemachine<FSM_0>forsignal<current_state>.
------------------------------------------------------
|States|6|
|Transitions|11|
|Inputs|1|
|Outputs|2|
|Clock|CLK(rising_edge)|
|Reset|RESET(positive)|
|Resettype|asynchronous|
|ResetState|clear|
|PowerUpState|clear|
|Encoding|automatic|
|Implementation|LUT|
------------------------------------------------------
Summary:
inferred1FiniteStateMachine(s).
Unit<statmach>synthesized.
...
==============================================================
HDLSynthesisReport
MacroStatistics
#ROMs:3
16x10-bitROM:1
16x7-bitROM:2
#Counters:2
4-bitupcounter:2
==============================================================
...
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Chapter18:XSTLogFile
AdditionalMacroProcessingXSTLogFileExample
ThefollowingXSTFPGAlogleexampleshowstheadditionalmacroprocessingdone
duringtheAdvancedHDLSynthesisstepandtheoverallmacrostatisticsafterthisstep.
===================================================
*AdvancedHDLSynthesis*
===================================================
AnalyzingFSM<FSM_0>forbestencoding.
OptimizingFSM<MACHINE/current_state/FSM_0>onsignal<current_state[1:3]>withgrayencoding.
----------------------
State|Encoding
----------------------
clear|000
zero|001
start|011
counting|010
stop|110
stopped|111
----------------------
============================================================
AdvancedHDLSynthesisReport
MacroStatistics
#FSMs:1
#ROMs:3
16x10-bitROM:1
16x7-bitROM:2
#Counters:2
4-bitupcounter:2
#Registers:3
Flip-Flops/Latches:3
============================================================
...
XSTFPGALogFileExample
ThefollowingisanexampleofanXSTlogleforFPGAsynthesis.Release10.1-xst
K.31(nt64)
Copyright(c)1995-2008Xilinx,Inc.Allrightsreserved.
TABLEOFCONTENTS
1)SynthesisOptionsSummary
2)HDLCompilation
3)DesignHierarchyAnalysis
4)HDLAnalysis
5)HDLSynthesis
5.1)HDLSynthesisReport
6)AdvancedHDLSynthesis
6.1)AdvancedHDLSynthesisReport
7)LowLevelSynthesis
8)PartitionReport
9)FinalReport
9.1)Deviceutilizationsummary
9.2)PartitionResourceSummary
9.3)TIMINGREPORT
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Chapter18:XSTLogFile
=============================
*SynthesisOptionsSummary*
=============================
----SourceParameters
InputFileName:"stopwatch.prj"
InputFormat:mixed
IgnoreSynthesisConstraintFile:NO
----TargetParameters
OutputFileName:"stopwatch"
OutputFormat:NGC
TargetDevice:xc4vlx15-12-sf363
----SourceOptions
TopModuleName:stopwatch
AutomaticFSMExtraction:YES
FSMEncodingAlgorithm:Auto
SafeImplementation:No
FSMStyle:lut
RAMExtraction:Yes
RAMStyle:Auto
ROMExtraction:Yes
MuxStyle:Auto
DecoderExtraction:YES
PriorityEncoderExtraction:YES
ShiftRegisterExtraction:YES
LogicalShifterExtraction:YES
XORCollapsing:YES
ROMStyle:Auto
MuxExtraction:YES
ResourceSharing:YES
AsynchronousToSynchronous:NO
UseDSPBlock:auto
AutomaticRegisterBalancing:No
----TargetOptions
AddIOBuffers:YES
GlobalMaximumFanout:500
AddGenericClockBuffer(BUFG):32
NumberofRegionalClockBuffers:16
RegisterDuplication:YES
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Chapter18:XSTLogFile
SlicePacking:YES
OptimizeInstantiatedPrimitives:NO
UseClockEnable:Auto
UseSynchronousSet:Auto
UseSynchronousReset:Auto
PackIORegistersintoIOBs:auto
EquivalentregisterRemoval:YES
----GeneralOptions
OptimizationGoal:Speed
OptimizationEffort:1
PowerReduction:NO
LibrarySearchOrder:stopwatch.lso
KeepHierarchy:NO
NetlistHierarchy:as_optimized
RTLOutput:Yes
GlobalOptimization:AllClockNets
ReadCores:YES
WriteTimingConstraints:NO
CrossClockAnalysis:NO
HierarchySeparator:/
BusDelimiter:<>
CaseSpecifier:maintain
SliceUtilizationRatio:100
BRAMUtilizationRatio:100
DSP48UtilizationRatio:100
Verilog2001:YES
AutoBRAMPacking:NO
SliceUtilizationRatioDelta:5
===================================================
===================================================
*HDLCompilation*
===================================================
Compilingverilogfile"smallcntr.v"inlibrarywork
Compilingverilogfile"statmach.v"inlibrarywork
Module<smallcntr>compiled
Compilingverilogfile"hex2led.v"inlibrarywork
Module<statmach>compiled
Compilingverilogfile"decode.v"inlibrarywork
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Chapter18:XSTLogFile
Module<hex2led>compiled
Compilingverilogfile"cnt60.v"inlibrarywork
Module<decode>compiled
Compilingverilogfile"stopwatch.v"inlibrarywork
Module<cnt60>compiled
Module<stopwatch>compiled
Noerrorsincompilation
Analysisoffile<"stopwatch.prj">succeeded.
Compilingvhdlfile"C:/xst/watchver/tenths.vhd"inLibrarywork.
Entity<tenths>compiled.
Entity<tenths>(Architecture<tenths_a>)compiled.
Compilingvhdlfile"C:/xst/watchver/dcm1.vhd"inLibrarywork.
Entity<dcm1>compiled.
Entity<dcm1>(Architecture<BEHAVIORAL>)compiled.
===================================================
*DesignHierarchyAnalysis*
===================================================
Analyzinghierarchyformodule<stopwatch>inlibrary<work>.
Analyzinghierarchyforentity<dcm1>inlibrary<work>
(architecture<BEHAVIORAL>).
Analyzinghierarchyformodule<statmach>inlibrary<work>with
parameters.
clear="000001"
counting="001000"
start="000100"
stop="010000"
stopped="100000"
zero="000010"
Analyzinghierarchyformodule<decode>inlibrary<work>.
Analyzinghierarchyformodule<cnt60>inlibrary<work>.
Analyzinghierarchyformodule<hex2led>inlibrary<work>.
Analyzinghierarchyformodule<smallcntr>inlibrary<work>.
===================================================
*HDLAnalysis*
===================================================
Analyzingtopmodule<stopwatch>.
Module<stopwatch>iscorrectforsynthesis.
AnalyzingEntity<dcm1>inlibrary<work>(Architecture
<BEHAVIORAL>).
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Chapter18:XSTLogFile
Setuser-definedproperty"CAPACITANCE=DONT_CARE"forinstance
<CLKIN_IBUFG_INST>inunit<dcm1>.
Setuser-definedproperty"IBUF_DELAY_VALUE=0"forinstance
<CLKIN_IBUFG_INST>inunit<dcm1>.
Setuser-definedproperty"IOSTANDARD=DEFAULT"forinstance
<CLKIN_IBUFG_INST>inunit<dcm1>.
Setuser-definedproperty"CLKDV_DIVIDE=2.0000000000000000"for
instance<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"CLKFX_DIVIDE=1"forinstance
<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"CLKFX_MULTIPLY=4"forinstance
<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"CLKIN_DIVIDE_BY_2=FALSE"for
instance<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"CLKIN_PERIOD=20.0000000000000000"
forinstance<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"CLKOUT_PHASE_SHIFT=NONE"for
instance<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"CLK_FEEDBACK=1X"forinstance
<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"DESKEW_ADJUST=SYSTEM_SYNCHRONOUS"
forinstance<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"DFS_FREQUENCY_MODE=LOW"forinstance
<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"DLL_FREQUENCY_MODE=LOW"forinstance
<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"DSS_MODE=NONE"forinstance
<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"DUTY_CYCLE_CORRECTION=TRUE"for
instance<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"FACTORY_JF=C080"forinstance
<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"PHASE_SHIFT=0"forinstance
<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"SIM_MODE=SAFE"forinstance
<DCM_INST>inunit<dcm1>.
Setuser-definedproperty"STARTUP_WAIT=TRUE"forinstance
<DCM_INST>inunit<dcm1>.
Entity<dcm1>analyzed.Unit<dcm1>generated.
Analyzingmodule<statmach>inlibrary<work>.
clear=6’b000001
counting=6’b001000
start=6’b000100
stop=6’b010000
stopped=6’b100000
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Chapter18:XSTLogFile
zero=6’b000010
Module<statmach>iscorrectforsynthesis.
Analyzingmodule<decode>inlibrary<work>.
Module<decode>iscorrectforsynthesis.
Analyzingmodule<cnt60>inlibrary<work>.
Module<cnt60>iscorrectforsynthesis.
Analyzingmodule<smallcntr>inlibrary<work>.
Module<smallcntr>iscorrectforsynthesis.
Analyzingmodule<hex2led>inlibrary<work>.
Module<hex2led>iscorrectforsynthesis.
===================================================
*HDLSynthesis*
===================================================
Performingbidirectionalportresolution...
SynthesizingUnit<statmach>.
Relatedsourcefileis"statmach.v".
Foundfinitestatemachine<FSM_0>forsignal<current_state>.
-------------------------------------------------
|States|6|
|Transitions|15|
|Inputs|2|
|Outputs|2|
|Clock|CLK(rising_edge)|
|Reset|RESET(positive)|
|Resettype|asynchronous|
|ResetState|000001|
|Encoding|automatic|
|Implementation|LUT|
-------------------------------------------------
Found1-bitregisterforsignal<CLKEN>.
Found1-bitregisterforsignal<RST>.
Summary:
inferred1FiniteStateMachine(s).
inferred2D-typeflip-flop(s).
Unit<statmach>synthesized.
SynthesizingUnit<decode>.
Relatedsourcefileis"decode.v".
Found16x10-bitROMforsignal<ONE_HOT>.
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Summary:
inferred1ROM(s).
Unit<decode>synthesized.
SynthesizingUnit<hex2led>.
Relatedsourcefileis"hex2led.v".
Found16x7-bitROMforsignal<LED>.
Summary:
inferred1ROM(s).
Unit<hex2led>synthesized.
SynthesizingUnit<smallcntr>.
Relatedsourcefileis"smallcntr.v".
Found4-bitupcounterforsignal<QOUT>.
Summary:
inferred1Counter(s).
Unit<smallcntr>synthesized.
SynthesizingUnit<dcm1>.
Relatedsourcefileis"C:/xst/watchver/dcm1.vhd".
Unit<dcm1>synthesized.
SynthesizingUnit<cnt60>.
Relatedsourcefileis"cnt60.v".
Unit<cnt60>synthesized.
SynthesizingUnit<stopwatch>.
Relatedsourcefileis"stopwatch.v".
Unit<stopwatch>synthesized.
=======================================
HDLSynthesisReport
MacroStatistics
#ROMs:3
16x10-bitROM:1
16x7-bitROM:2
#Counters:2
4-bitupcounter:2
#Registers:2
1-bitregister:2
===================================================
===================================================
*AdvancedHDLSynthesis*
===================================================
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AnalyzingFSM<FSM_0>forbestencoding.
OptimizingFSM<MACHINE/current_state/FSM>onsignal
<current_state[1:3]>withsequentialencoding.
--------------------
State|Encoding
--------------------
000001|000
000010|001
000100|010
001000|011
010000|100
100000|101
--------------------
LoadingdeviceforapplicationRf_Devicefromfile’4vlx15.nph’
inenvironmentC:\xilinx.
Executingedif2ngd-noa"tenths.edn""tenths.ngo"
Release10.1-edif2ngdK.31(nt64)
Copyright(c)1995-2008Xilinx,Inc.Allrightsreserved.
INFO:NgdBuild-Release10.1edif2ngdK.31(nt64)
INFO:NgdBuild-Copyright(c)1995-2008Xilinx,Inc.Allrights
reserved.
Writingmoduleto"tenths.ngo"...
Readingcore<tenths_c_counter_binary_v8_0_xst_1.ngc>.
Loadingcore<tenths_c_counter_binary_v8_0_xst_1>fortimingand
areainformationforinstance<BU2>.
Loadingcore<tenths>fortimingandareainformationfor
instance<xcounter>.
===================================================
AdvancedHDLSynthesisReport
MacroStatistics
#ROMs:3
16x10-bitROM:1
16x7-bitROM:2
#Counters:2
4-bitupcounter:2
#Registers:5
Flip-Flops:5
===================================================
===================================================
*LowLevelSynthesis*
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===================================================
Optimizingunit<stopwatch>...
Mappingallequations...
Buildingandoptimizingfinalnetlist...
Foundareaconstraintratioof100(+5)onblockstopwatch,
actualratiois0.
NumberofLUTreplicatedforflop-pairpacking:0
FinalMacroProcessing...
===================================================
FinalRegisterReport
MacroStatistics
#Registers:13
Flip-Flops:13
===================================================
===================================================
*PartitionReport*
===================================================
PartitionImplementationStatus
-------------------------------
NoPartitionswerefoundinthisdesign.
-------------------------------
===================================================
*FinalReport*
===================================================
FinalResults
RTLTopLevelOutputFileName:stopwatch.ngr
TopLevelOutputFileName:stopwatch
OutputFormat:NGC
OptimizationGoal:Speed
KeepHierarchy:NO
DesignStatistics
#IOs:27
CellUsage:
#BELS:70
#GND:2
#INV:1
#LUT1:3
#LUT2:1
#LUT2_L:1
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#LUT3:8
#LUT3_D:1
#LUT3_L:1
#LUT4:37
#LUT4_D:1
#LUT4_L:4
#MUXCY:3
#MUXF5:2
#VCC:1
#XORCY:4
#FlipFlops/Latches:17
#FDC:13
#FDCE:4
#ClockBuffers:1
#BUFG:1
#IOBuffers:27
#IBUF:2
#IBUFG:1
#OBUF:24
#DCM_ADVs:1
#DCM_ADV:1
===================================================
Deviceutilizationsummary:
---------------------------
SelectedDevice:4vlx15sf363-12
NumberofSlices:32outof61440%
NumberofSliceFlipFlops:17outof122880%
Numberof4inputLUTs:58outof122880%
NumberofIOs:27
NumberofbondedIOBs:27outof24011%
NumberofGCLKs:1outof323%
NumberofDCM_ADVs:1outof425%
---------------------------
PartitionResourceSummary:
---------------------------
NoPartitionswerefoundinthisdesign.
---------------------------
===================================================
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TIMINGREPORT
NOTE:THESETIMINGNUMBERSAREONLYASYNTHESISESTIMATE.
FORACCURATETIMINGINFORMATIONPLEASEREFERTOTHETRACEREPORT
GENERATEDAFTERPLACE-and-ROUTE.
ClockInformation:
------------------
-----------------------------------+-----------
ClockSignal|Clockbuffer(FFname)|Load|
-----------------------------------+-----------
CLK|Inst_dcm1/DCM_INST:CLK0|17|
-----------------------------------+-----------
AsynchronousControlSignalsInformation:
----------------------------------------
-----------------------------------+---------------
ControlSignal|Buffer(FFname)|Load|
-----------------------------------+---------------
MACHINE/RST(MACHINE/RST:Q)|NONE(sixty/lsbcount/QOUT_1)|8|
RESET|IBUF|5|
sixty/msbclr(sixty/msbclr_f5:O)|NONE(sixty/msbcount/QOUT_0)|
4|
-----------------------------------+---------------
TimingSummary:
---------------
SpeedGrade:-12
Minimumperiod:2.282ns(MaximumFrequency:438.212MHz)
Minimuminputarrivaltimebeforeclock:1.655ns
Maximumoutputrequiredtimeafterclock:4.617ns
Maximumcombinationalpathdelay:Nopathfound
TimingDetail:
--------------
Allvaluesdisplayedinnanoseconds(ns)
===================================================
Timingconstraint:DefaultperiodanalysisforClock’CLK’
Clockperiod:2.282ns(frequency:438.212MHz)
Totalnumberofpaths/destinationports:134/21
---------------------------------------------------
Delay:2.282ns(LevelsofLogic=4)
Source:xcounter/BU2/U0/q_i_1(FF)
Destination:sixty/msbcount/QOUT_1(FF)
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SourceClock:CLKrising
DestinationClock:CLKrising
DataPath:xcounter/BU2/U0/q_i_1tosixty/msbcount/QOUT_1
GateNet
Cell:in->outfanoutDelayDelayLogicalName(NetName)
----------------------------------------------------
FDCE:C->Q120.2720.672U0/q_i_1(q(1))
LUT4:I0->O110.1470.492U0/thresh0_i_cmp_eq00001(thresh0)
endscope:’BU2’
endscope:’xcounter’
LUT4_D:I3->O10.1470.388sixty/msbce(sixty/msbce)
LUT3:I2->O10.1470.000sixty/msbcount/QOUT_1_rstpot
(sixty/msbcount/QOUT_1_rstpot)
FDC:D0.017sixty/msbcount/QOUT_1
----------------------------------------
Total2.282ns(0.730nslogic,1.552nsroute)
(32.0%logic,68.0%route)
===================================================
Timingconstraint:DefaultOFFSETINBEFOREforClock’CLK’
Totalnumberofpaths/destinationports:4/3
---------------------------------------------------
Offset:1.655ns(LevelsofLogic=3)
Source:STRTSTOP(PAD)
Destination:MACHINE/current_state_FSM_FFd3(FF)
DestinationClock:CLKrising
DataPath:STRTSTOPtoMACHINE/current_state_FSM_FFd3
GateNet
Cell:in->outfanoutDelayDelayLogicalName(NetName)
----------------------------------------------------
IBUF:I->O40.7540.446STRTSTOP_IBUF(STRTSTOP_IBUF)
LUT4:I2->O10.1470.000MACHINE/current_state_FSM_FFd3-In_F
(N48)
MUXF5:I0->O10.2910.000MACHINE/current_state_FSM_FFd3-In
(MACHINE/current_state_FSM_FFd3-In)
FDC:D0.017MACHINE/current_state_FSM_FFd3
----------------------------------------
Total1.655ns(1.209nslogic,0.446nsroute)
(73.0%logic,27.0%route)
===================================================
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Timingconstraint:DefaultOFFSETOUTAFTERforClock’CLK’
Totalnumberofpaths/destinationports:96/24
---------------------------------------------------
Offset:4.617ns(LevelsofLogic=2)
Source:sixty/lsbcount/QOUT_1(FF)
Destination:ONESOUT<6>(PAD)
SourceClock:CLKrising
DataPath:sixty/lsbcount/QOUT_1toONESOUT<6>
GateNet
Cell:in->outfanoutDelayDelayLogicalName(NetName)
----------------------------------------------------
FDC:C->Q130.2720.677sixty/lsbcount/QOUT_1
(sixty/lsbcount/QOUT_1)
LUT4:I0->O10.1470.266lsbled/Mrom_LED21(lsbled/Mrom_LED2)
OBUF:I->O3.255ONESOUT_2_OBUF(ONESOUT<2>)
----------------------------------------
Total4.617ns(3.674nslogic,0.943nsroute)
(79.6%logic,20.4%route)
===================================================
TotalREALtimetoXstcompletion:20.00secs
TotalCPUtimetoXstcompletion:19.53secs
-->
Totalmemoryusageis333688kilobytes
Numberoferrors:0(0filtered)
)Numberofwarnings:0(0filtered
Numberofinfos:1(0filtered)
XSTCPLDLogFileExample
ThefollowingisanexampleofanXSTlogfileforCPLD
synthesis.
Release10.1-xstK.31(nt64)
Copyright(c)1995-2008Xilinx,Inc.Allrightsreserved.
TABLEOFCONTENTS
1)SynthesisOptionsSummary
2)HDLCompilation
3)DesignHierarchyAnalysis
4)HDLAnalysis
5)HDLSynthesis
5.1)HDLSynthesisReport
6)AdvancedHDLSynthesis
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6.1)AdvancedHDLSynthesisReport
7)LowLevelSynthesis
8)PartitionReport
9)FinalReport
======================================================
*SynthesisOptionsSummary*
======================================================
----SourceParameters
InputFileName:"stopwatch.prj"
InputFormat:mixed
IgnoreSynthesisConstraintFile:NO
----TargetParameters
OutputFileName:"stopwatch"
OutputFormat:NGC
TargetDevice:CoolRunner2CPLDs
----SourceOptions
TopModuleName:stopwatch
AutomaticFSMExtraction:YES
FSMEncodingAlgorithm:Auto
SafeImplementation:No
MuxExtraction:YES
ResourceSharing:YES
----TargetOptions
AddIOBuffers:YES
MACROPreserve:YES
XORPreserve:YES
EquivalentregisterRemoval:YES
----GeneralOptions
OptimizationGoal:Speed
OptimizationEffort:1
LibrarySearchOrder:stopwatch.lso
KeepHierarchy:YES
NetlistHierarchy:as_optimized
RTLOutput:Yes
HierarchySeparator:/
BusDelimiter:<>
CaseSpecifier:maintain
Verilog2001:YES
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----OtherOptions
ClockEnable:YES
wysiwyg:NO
======================================================
======================================================
*HDLCompilation*
======================================================
Compilingverilogfile"smallcntr.v"inlibrarywork
Compilingverilogfile"tenths.v"inlibrarywork
Module<smallcntr>compiled
Compilingverilogfile"statmach.v"inlibrarywork
Module<tenths>compiled
Compilingverilogfile"hex2led.v"inlibrarywork
Module<statmach>compiled
Compilingverilogfile"decode.v"inlibrarywork
Module<hex2led>compiled
Compilingverilogfile"cnt60.v"inlibrarywork
Module<decode>compiled
Compilingverilogfile"stopwatch.v"inlibrarywork
Module<cnt60>compiled
Module<stopwatch>compiled
Noerrorsincompilation
Analysisoffile<"stopwatch.prj">succeeded.
======================================================
*DesignHierarchyAnalysis*
======================================================
Analyzinghierarchyformodule<stopwatch>inlibrary<work>.
Analyzinghierarchyformodule<statmach>inlibrary<work>with
parameters.
clear="000001"
counting="001000"
start="000100"
stop="010000"
stopped="100000"
zero="000010"
Analyzinghierarchyformodule<tenths>inlibrary<work>.
Analyzinghierarchyformodule<decode>inlibrary<work>.
Analyzinghierarchyformodule<cnt60>inlibrary<work>.
Analyzinghierarchyformodule<hex2led>inlibrary<work>.
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Analyzinghierarchyformodule<smallcntr>inlibrary<work>.
======================================================
*HDLAnalysis*
======================================================
Analyzingtopmodule<stopwatch>.
Module<stopwatch>iscorrectforsynthesis.
Analyzingmodule<statmach>inlibrary<work>.
clear=6’b000001
counting=6’b001000
start=6’b000100
stop=6’b010000
stopped=6’b100000
zero=6’b000010
Module<statmach>iscorrectforsynthesis.
Analyzingmodule<tenths>inlibrary<work>.
Module<tenths>iscorrectforsynthesis.
Analyzingmodule<decode>inlibrary<work>.
Module<decode>iscorrectforsynthesis.
Analyzingmodule<cnt60>inlibrary<work>.
Module<cnt60>iscorrectforsynthesis.
Analyzingmodule<smallcntr>inlibrary<work>.
Module<smallcntr>iscorrectforsynthesis.
Analyzingmodule<hex2led>inlibrary<work>.
Module<hex2led>iscorrectforsynthesis.
======================================================
*HDLSynthesis*
======================================================
Performingbidirectionalportresolution...
SynthesizingUnit<statmach>.
Relatedsourcefileis"statmach.v".
Foundfinitestatemachine<FSM_0>forsignal<current_state>.
-------------------------------------------------
|States|6|
|Transitions|15|
|Inputs|2|
|Outputs|2|
|Clock|CLK(rising_edge)|
|Reset|RESET(positive)|
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|Resettype|asynchronous|
|ResetState|000001|
|Encoding|automatic|
|Implementation|automatic|
-------------------------------------------------
Found1-bitregisterforsignal<CLKEN>.
Found1-bitregisterforsignal<RST>.
Summary:
inferred1FiniteStateMachine(s).
inferred2D-typeflip-flop(s).
Unit<statmach>synthesized.
SynthesizingUnit<tenths>.
Relatedsourcefileis"tenths.v".
Found4-bitupcounterforsignal<Q>.
Summary:
inferred1Counter(s).
Unit<tenths>synthesized.
SynthesizingUnit<decode>.
Relatedsourcefileis"decode.v".
Found16x10-bitROMforsignal<ONE_HOT>.
Summary:
inferred1ROM(s).
.Unit<decode>synthesized
SynthesizingUnit<hex2led>.
Relatedsourcefileis"hex2led.v".
Found16x7-bitROMforsignal<LED>.
Summary:
inferred1ROM(s).
Unit<hex2led>synthesized.
SynthesizingUnit<smallcntr>.
Relatedsourcefileis"smallcntr.v".
Found4-bitupcounterforsignal<QOUT>.
Summary:
inferred1Counter(s).
Unit<smallcntr>synthesized.
SynthesizingUnit<cnt60>.
Relatedsourcefileis"cnt60.v".
Unit<cnt60>synthesized.
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SynthesizingUnit<stopwatch>.
Relatedsourcefileis"stopwatch.v".
Found1-bitregisterforsignal<strtstopinv>.
Summary:
inferred1D-typeflip-flop(s).
Unit<stopwatch>synthesized.
======================================================
HDLSynthesisReport
MacroStatistics
#ROMs:3
16x10-bitROM:1
16x7-bitROM:2
#Counters:3
4-bitupcounter:3
#Registers:3
1-bitregister:3
======================================================
======================================================
*AdvancedHDLSynthesis*
======================================================
AnalyzingFSM<FSM_0>forbestencoding.
OptimizingFSM<MACHINE/current_state/FSM>onsignal
<current_state[1:3]>withsequentialencoding.
--------------------
State|Encoding
--------------------
000001|000
000010|001
000100|010
001000|011
010000|100
100000|101
--------------------
======================================================
AdvancedHDLSynthesisReport
MacroStatistics
#ROMs:3
16x10-bitROM:1
16x7-bitROM:2
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#Counters:3
4-bitupcounter:3
#Registers:6
Flip-Flops:6
======================================================
======================================================
*LowLevelSynthesis*
======================================================
Optimizingunit<stopwatch>...
Optimizingunit<statmach>...
Optimizingunit<decode>...
Optimizingunit<hex2led>...
Optimizingunit<tenths>...
Optimizingunit<smallcntr>...
Optimizingunit<cnt60>...
============================================
*PartitionReport*
======================================================
PartitionImplementationStatus
-------------------------------
NoPartitionswerefoundinthisdesign.
-------------------------------
======================================================
*FinalReport*
======================================================
FinalResults
RTLTopLevelOutputFileName:stopwatch.ngr
TopLevelOutputFileName:stopwatch
OutputFormat:NGC
OptimizationGoal:Speed
KeepHierarchy:YES
TargetTechnology:CoolRunner2CPLDs
MacroPreserve:YES
XORPreserve:YES
ClockEnable:YES
wysiwyg:NO
DesignStatistics
#IOs:28
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CellUsage:
#BELS:413
#AND2:120
#AND3:10
#AND4:6
#INV:174
#OR2:93
#OR3:1
#XOR2:9
#FlipFlops/Latches:18
#FD:1
#FDC:5
#FDCE:12
#IOBuffers:28
#IBUF:4
#OBUF:24
======================================================
TotalREALtimetoXstcompletion:7.00secs
TotalCPUtimetoXstcompletion:6.83secs
-->
Totalmemoryusageis196636kilobytes
Numberoferrors:0(0filtered)
Numberofwarnings:0(0filtered)
Numberofinfos:0(0filtered)
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Chapter19
XSTNamingConventions
ThischapterdiscussesXSTNamingConventions,andincludes:
•XSTNetNamingConventions
•XSTInstanceNamingConventions
•XSTNameGenerationControl
XSTNetNamingConventions
ThefollowingXSTnetnamingconventionsarelistedinorderofnamingpriority:
1.Maintainexternalpinnames.
2.Keephierarchyinsignalnames,usingforwardslashes(/)orunderscores(_)as
hierarchydesignators.
3.Maintainoutputsignalnamesofregisters,includingstatebits.Usethehierarchical
namefromthelevelwheretheregisterwasinferred.
4.Ensurethatoutputsignalsofclockbuffersget_clockbuffertype(suchas_BUFGP
or_IBUFG)followtheclocksignalname.
5.Maintaininputnetstoregistersandtristatesnames.
6.Maintainnamesofsignalsconnectedtoprimitivesandblackboxes.
7.NameoutputnetnamesofIBUFsusingtheformnet_name_IBUF.Forexample,for
anIBUFwithanoutputnetnameofDIN,theoutputIBUFnetnameisDIN_IBUF.
8.NameinputnetnamestoOBUFsusingtheformnet_name_OBUF.Forexample,
foranOBUFwithaninputnetnameofDOUT,theinputOBUFnetnameis
DOUT_OBUF.
9.Basenamesforinternal(combinatorial)netsonuserHDLsignalnameswhere
possible.
XSTInstanceNamingConventions
Xilinx®highlyrecommendsthatyouusethefollowinginstancenamingconventions.
TouseinstancenamingconventionsfrompreviousreleasesofISE®DesignSuite,insert
thefollowingcommandlineoptionintheXSTcommandline:
-old_instance_names1
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Chapter19:XSTNamingConventions
Thefollowingrulesarelistedinorderofnamingpriority:
1.Keephierarchyininstancenames,usingforwardslashes(/)orunderscores(_)as
hierarchydesignators.
WheninstancenamesaregeneratedfromVHDLorVeriloggeneratestatements,
labelsfromgeneratestatementsareusedincompositionofinstancenames.
Forexample,forthefollowingVHDLgeneratestatement:
i1_loop:foriin1to10generate
inst_lut:LUT2genericmap(INIT=>"00")
XSTgeneratesthefollowinginstancenamesforLUT2:
i1_loop[1].inst_lut
i1_loop[2].inst_lut
i1_loop[9].inst_lut
...
i1_loop[10].inst_lut
2.Nameregisterinstances,includingstatebits,fortheoutputsignal.
3.Nameclockbufferinstances_clockbuffertype(suchas_BUFGPor_IBUFG)after
theoutputsignal.
4.Maintaininstantiationinstancenamesofblackboxes.
5.Maintaininstantiationinstancenamesoflibraryprimitives.
6.Nameinputandoutputbuffersusingtheform_IBUFor_OBUFafterthepadname.
7.NameOutputinstancenamesofIBUFsusingtheforminstance_name_IBUF.
8.NameinputinstancenamestoOBUFsusingtheforminstance_name_OBUF.
XSTNameGenerationControl
Thefollowingconstraintscontrolhownamesarewritten.
•HierarchySeparator(-hierarchy_separator)
•BusDelimiter(-bus_delimiter)
•Case(-case)
•DuplicationSufx(-duplication_sufx)
DeneinISEDesignSuitein:
•SynthesisProperties,OR
•Thecommandline
Formoreinformation,see:
XSTDesignConstraints
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Chapter20
XSTCommandLineMode
ThischapterdiscussesXSTCommandLineMode,andincludes:
•AboutXSTCommandLineMode
•LaunchingXSTinCommandLineModeUsingtheXSTShell
•LaunchingXSTinCommandLineModeUsingaScriptFile
•RunningXSTinScriptMode(VHDL)
•RunningXSTinScriptMode(Verilog)
•RunningXSTinScriptMode(MixedLanguage)
•SettingUpanXSTScriptUsingtheRunCommand
•SettingUpanXSTScriptUsingtheSetCommand
•SettingUpanXSTScriptUsingtheElaborateCommand
•SynthesizingVHDLDesignsUsingCommandLineMode
•SynthesizingVerilogDesignsUsingCommandLineMode
•SynthesizingMixedDesignsUsingCommandLineMode
AboutXSTCommandLineMode
ThissectiondiscussesAboutXSTCommandLineMode,andincludes:
•RunningXSTinCommandLineMode
•XSTFileTypesinCommandLineMode
•TemporaryFilesinCommandLineMode
•NamesWithSpacesinCommandLineMode
RunningXSTinCommandLineMode
TorunXSTincommandlinemode:
•Onaworkstation,runxst
•OnaPC,runxst.exe
XSTFileTypesinCommandLineMode
XSTgeneratesthefollowinglestypesincommandlinemode:
•Designoutputle,NGC(.ngc)
Thisleisgeneratedinthecurrentoutputdirectory(seethe-ofnoption).
•RegisterTransferLevel(RTL)netlistforRTLandTechnologyViewers(.ngr)
•Synthesislogle(.srp)
•Temporaryles
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TemporaryFilesinCommandLineMode
TemporarylesaregeneratedintheXSTtempdirectoryincommandlinemode.By
default,theXSTtempdirectoryis:
•Workstations
/tmp
•Windows
ThedirectoryspeciedbyeithertheTEMPorTMPenvironmentvariable
Useset-tmpdir<directory>tochangetheXSTtempdirectory.
VHDLorVerilogcompilationlesaregeneratedinthetempdirectory.Thedefaulttemp
directoryisthexstsubdirectoryofthecurrentdirectory.
TipXilinx®recommendsthatyoucleantheXSTtempdirectoryregularly .Thetemp
directorycontainsthelesresultingfromthecompilationofallVHDLandVerilogles
duringallXSTsessions.Eventually ,thenumberoflesstoredinthetempdirectorymay
severelyimpactCPUperformance.XSTdoesnotautomaticallycleanthetempdirectory .
NamesWithSpacesinCommandLineMode
XSTsupportsleanddirectorynameswithspacesincommandlinemode.
Encloseleordirectorynamescontainingspacesindoublequotes:
"C:\myproject"
Enclosemultipledirectoriesinbraces:
-vlgincdir{"C:\myproject"C:\temp}
LaunchingXSTinCommandLineModeUsingtheXSTShell
TypexsttoenterdirectlyintoanXSTshell.Enteryourcommandsandexecutethem.
Torunsynthesis,specifyacompletecommandwithallrequiredoptions.XSTdoesnot
acceptamodewhereyoucanrstentersetoption_1,thensetoption_2,andthenenter
run.
Sincealloptionsaresetatthesametime,Xilinx®recommendsthatyouuseascriptle.
LaunchingXSTinCommandLineModeUsingaScriptFile
Storeyourcommandsinaseparatescriptleandrunthemallatonce.Toexecuteyour
scriptle,runthefollowingworkstationorPCcommand:
xst-ifnin_le_name-ofnout_le_name-intstyle{silent|ise|xow}
The-ofnoptionisnotmandatory.Ifyouomitit,XSTautomaticallygeneratesalogle
withtheleextension.srp,andallmessagesdisplayonthescreen.Usethefollowingto
limitthenumberofmessagesprintedtothescreen:
•The-intstylesilentoption
•TheXIL_XST_HIDEMESSAGESenvironmentvariable
•ThemessagelterfeatureinISE®DesignSuite
Formoreinformation,see:
ReducingtheSizeoftheXSTLogFile
Forexample,assumethatthefollowingtextiscontainedinalefoo.scr:
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Chapter20:XSTCommandLineMode
run-ifntt1.prj-toptt1-ifmtMIXED-opt_modeSPEED-opt_level1-ofntt1.ngc-p
<parttype>
ThisscriptlecanbeexecutedunderXSTusingthefollowingcommand:
xst-ifnfoo.scr
Youcanalsogeneratealoglewiththefollowingcommand:
xst-ifnfoo.scr-ofnfoo.log
Ascriptlecanberuneitherusingxst-ifnscriptname,orexecutedundertheXST
prompt,byusingthescriptscript_namecommand.
scriptfoo.scr
IfyoumakeamistakeinanXSTcommandoption,oritsvalue,XSTissuesanerror
messageandstopsexecution.Forexample,ifinthepreviousscriptexampleVHDLis
incorrectlyspelled(“VHDLL”),XSTgivesthefollowingerrormessage:
-->ERROR:Xst:1361-Syntaxerrorincommandrunforoption
"-ifmt":parameter"VHDLL"isnotallowed.
IfyoucreatedyourprojectusingISEDesignSuite,andhaverunXSTatleastoncefrom
ISEDesignSuite,youcanswitchtoXSTcommandlinemodeandusethescriptand
projectlesthatwerecreatedbyISEDesignSuite.
TorunXSTfromthecommandline,runthefollowingcommandfromprojectdirectory:
xst-ifn<top_level_block>.xst-ofn<top_level_block>.syr
SettingUpanXSTScriptUsingtheRunCommand
ThissectiondiscussesSettingUpanXSTScriptUsingtheRunCommand,andincludes:
•AbouttheRunCommand
•WritingaScriptFile
•XSTSpecicNon-TimingRelatedOptions
•OnlineHelp
•SupportedFamilies
•CommandsforaSpecicDevice
•RunCommandOptionsandValues(Virtex-5Devices)
AbouttheRunCommand
Theruncommand:
•Isthemainsynthesiscommand.
•Allowsyoutorunsynthesisinitsentirety,beginningwiththeparsingofthe
HardwareDescriptionLanguage(HDL)les,andendingwiththegeneration
ofthenalnetlist.
•Canbeusedonlyonceperscriptle.
•Beginswithakeywordrun,whichisfollowedbyasetofoptionsanditsvalues:
runoption_1valueoption_2value...
NoteXilinxdoesnotsupportorrecommendtheuseofmultipleruncommandsina
singlescript.
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Chapter20:XSTCommandLineMode
WritingaScriptFile
Observethefollowingruleswhenwritingascriptle:
•Placeeachoption-valuepaironaseparateline.
•Usethepound(#)charactertocommentoutoptions,orplaceadditionalcomments
inthescriptle.
run
option_1value
#option_2value
option_3value
•Therstlinecontainsonlytheruncommandwithoutanyoptions.
•Therearenoblanklinesinthemiddleofthecommand.
•Eachoptionnamebeginswithdash.Forexample:-ifn,-ifmt,-ofn.
•Eachoptionhasonevalue.Therearenooptionswithoutavalue.
•Thevalueforagivenoptioncanbeoneofthefollowing:
–PredenedbyXST(forinstance,yesorno)
–Anystring(forinstance,alenameoranameofthetoplevelentity).Options
suchas-vlgincdiracceptseveraldirectoriesasvalues.Separatethedirectories
byspaces,andenclosetheminbraces({}):
-vlgincdir{c:\vlg1c:\vlg2}
Formoreinformation,seeNamesWithSpacesinCommandLineMode.
–Aninteger
XSTSpecificNon-TimingRelatedOptions
ThefollowingtopicssummarizeXSTspecicnon-timingrelatedoptions,including
runcommandoptionsandtheirvalues:
•XSTSpecicNon-TimingOptions
•XSTSpecicNon-TimingOptions:XSTCommandLineOnly
OnlineHelp
XSTprovidesonlineHelpfromthecommandline.Thefollowinginformationis
availablebytypinghelpatthecommandline.TheXSThelpfunctionprovidesalistof
supportedfamilies,availablecommands,optionsandtheirvaluesforeachsupported
devicefamily.
ToseeadetailedexplanationofanXSTcommand,usethefollowingsyntax.
help-archfamily_name-commandcommand_name
where:
•family_nameisalistofsupportedXilinx®familiesinthecurrentversionofXST
•command_nameisoneofthefollowingXSTcommands:
–run
–set
–elaborate
–time
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Chapter20:XSTCommandLineMode
SupportedFamilies
Toseealistofsupportedfamilies,typehelpatthecommandlinepromptwithno
argument.XSTissuesthefollowingmessage.
-->help
ERROR:Xst:1356-Help:Missing"-arch<family>".
Pleasespecifywhatfamilyyouwanttotarget
availablefamilies:
acr2
aspartan3
aspartan3a
aspartan3adsp
aspartan3e
avirtex4
fpgacore
qrvirtex4
qvirtex4
spartan3
spartan3a
spartan3adsp
spartan3e
virtex4
virtex5
xa9500xl
xbr
xc9500
xc9500xl
xpla3
CommandsforaSpecificDevice
Toseealistofcommandsforaspecicdevice,typethefollowingatthecommand
linepromptwithnoargument.
help-archfamily_name
Forexample:
help-archvirtex
RunCommandOptionsandValues(Virtex-5Devices)
Usethefollowingcommandtoseealistofoptionsandvaluesfortheruncommandfor
Virtex®-5devices.
-->help-archvirtex5-commandrun
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Chapter20:XSTCommandLineMode
Thiscommandgivesthefollowingoutput:
-mult_style:MultiplierStyle
block/lut/auto/pipe_lut
-bufg:MaximumGlobalBuffers
*
-bufgce:BUFGCEExtraction
YES/NO
-decoder_extract:DecoderExtraction
YES/NO
....
-ifn:*
-ifmt:Mixed/VHDL/Verilog
-ofn:*
-ofmt:NGC/NCD
-p:*
-ent:*
-top:*
-opt_mode:AREA/SPEED
-opt_level:1/2
-keep_hierarchy:YES/NO
-vlgincdir:*
-verilog2001:YES/NO
-vlgcase:Full/Parallel/Full-Parallel
....
SettingUpanXSTScriptUsingtheSetCommand
XSTrecognizesthesetcommand.
Formoreinformation,see:
XSTDesignConstraints
SetCommandOptions
OptionDescriptionValues
-tmpdirLocationofalltemporaryles
generatedbyXSTduringasession
Anyvalidpathtoadirectory
-xsthdpdirWorkDirectory—locationofall
lesresultingfromVHDLorVerilog
compilation
Anyvalidpathtoadirectory
-xsthdpiniHDLLibraryMappingFile(.INIFile)file_name
SettingUpanXSTScriptUsingtheElaborateCommand
Usetheelaboratecommandto:
•Pre-compileVHDLandVeriloglesinaspeciclibrary ,or
•VerifyVerilogleswithoutsynthesizingthedesign
Sincecompilationisincludedintherun,theelaboratecommandisoptional.
Formoreinformation,see:
XSTDesignConstraints
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ElaborateCommandOptions
OptionDescriptionValues
-ifnProjectFilele_name
-ifmtFormatvhdl,verilog,mixed
-lsoLibrarySearchOrderle_name.lso
-work_libWorkLibraryforCompilation—library
wherethetoplevelblockwascompiled
name,work
-verilog2001Verilog-2001yes,no
-vlgpathVerilogSearchPathsAnyvalidpathtodirectoriesseparatedbyspaces,and
enclosedindoublequotes("...")
-vlgincdirVerilogIncludeDirectoriesAnyvalidpathtodirectoriesseparatedbyspaces,and
enclosedinbraces({...})
RunningXSTinScriptMode(VHDL)
TorunXSTinscriptmodeinVHDL:
1.Openanewlenamedstopwatch.xstinthecurrentdirectory.
2.PutthepreviouslyexecutedXSTshellcommandintothisleandsaveit.
run-ifnwatchvhd.prj-ifmtmixed-topstopwatch-ofnwatchvhd.ngc
-ofmtNGC-pxc5vfx30t-2-ff324-opt_modeSpeed-opt_level1
3.Fromthetcshorothershell,enterthefollowingcommandtobeginsynthesis:
xst-ifnstopwatch.xst
FilesCreatedDuringRun(VHDL)
Duringthisrun,XSTcreatesthefollowingles.
•watchvhd.ngc
AnNGClereadyfortheimplementationtools
•xst.srp
TheXSTlogle
SavingXSTMessagesinaDifferentLogFile(VHDL)
TosaveXSTmessagesinadifferentlogle,runthefollowingcommand:
xst-ifnstopwatch.xst-ofn<lename>.log
Followingisanexampleusingwatchvhd.log:
xst-ifnstopwatch.xst-ofnwatchvhd.log
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Chapter20:XSTCommandLineMode
Forthisexample,stopwatch.xstappearsasfollows:
run
-ifnwatchvhd.prj
-ifmtmixed
-topstopwatch
-ofnwatchvhd.ngc
-ofmtNGC
-pxc5vfx30t-2-ff324
-opt_modeSpeed
-opt_level1
ImprovingReadability(VHDL)
Observethefollowingrulestoimprovethereadabilityofthestopwatch.xstle,
especiallyifyouusemanyoptionstorunsynthesis:
•Eachoptionwithitsvalueisonaseparateline.
•Therstlinecontainsonlytheruncommandwithoutanyoptions.
•Therearenoblanklinesinthemiddleofthecommand.
•Eachlineexcepttherstbeginswithadash.
LeadingSpaces(VHDL)
Anerroroccursifaleadingspaceisenteredinthevalueeld.
ISE®DesignSuiteautomaticallystripsleadingspacesfromaprocessvalue.Accordingly,
the.xstlewrittenbyISEDesignSuiteisnotaffectedbyleadingspaces.
Ifyouhand-editthe.xstleandrunXSTfromthecommandline,manuallydelete
anyleadingspaces.
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Chapter20:XSTCommandLineMode
RunningXSTinScriptMode(Verilog)
ThissectiondiscussesRunningXSTinScriptMode(Verilog),andincludes:
•HowtoRunXSTinScriptMode(Verilog)
•FilesCreatedDuringRun(Verilog)
•SavingXSTMessagesinaDifferentLogFile(Verilog)
•ImprovingReadability(Verilog)
HowtoRunXSTinScriptMode(Verilog)
TorunXSTinscriptmode:
1.Openanewlecalleddesign.xstinthecurrentdirectory .Putthepreviously
executedXSTshellcommandintothisleandsaveit.
run
-ifnwatchver.prj
-ifmtmixed
-ofnwatchver.ngc
-ofmtNGC
-pxc5vfx30t-2-ff324
-opt_modeSpeed
-opt_level1
2.Fromthetcshorothershell,enterthefollowingcommandtobeginsynthesis.
xst-ifndesign.xst
Forthepreviouscommandexample,thedesign.xstleshouldlooklikethefollowing:
run
-ifnwatchver.prj
-ifmtmixed
-topstopwatch
-ofnwatchver.ngc
-ofmtNGC
-pxc5vfx30t-2-ff324
-opt_modeSpeed
-opt_level1
FilesCreatedDuringRun(Verilog)
Duringthisrun,XSTcreatesthefollowingles.
•watchvhd.ngc
AnNGClereadyfortheimplementationtools
•design.srp
TheXSTscriptlogle
SavingXSTMessagesinaDifferentLogFile(Verilog)
TosaveXSTmessagesinadifferentlogle(forexample,watchver.log),run:
xst-ifndesign.xst-ofnwatchver.log
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Chapter20:XSTCommandLineMode
ImprovingReadability(Verilog)
Toimprovethereadabilityofthedesign.xstle,especiallyifyouusemanyoptions
torunsynthesis,placeeachoptionwithitsvalueonaseparateline.Observethe
followingrules:
•Therstlinecontainsonlytheruncommandwithoutanyoptions.
•Therearenoblanklinesinthemiddleofthecommand.
•Eachline(excepttherstone)beginswithadash(-).
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Chapter20:XSTCommandLineMode
RunningXSTinScriptMode(MixedLanguage)
ThissectiondiscussesRunningXSTinScriptMode(MixedLanguage),andincludes:
•HowtoRunXSTinScriptMode(MixedLanguage)
•FilesCreatedDuringRun
•SavingXSTMessagesinaDifferentLogFile(MixedLanguage)
•ImprovingReadability(MixedLanguage)
HowtoRunXSTinScriptMode(MixedLanguage)
TorunXSTinscriptmode:
1.Openanewlecalledstopwatch.xstinthecurrentdirectory.Putthepreviously
executedXSTshellcommandintothisleandsaveit.
run
-ifnwatchver.prj
-ifmtmixed
-topstopwatch
-ofnwatchver.ngc
-ofmtNGC
-ofnwatchver.ngc
-ofmtNGC
-pxc5vfx30t-2-ff324
-opt_modeSpeed
-opt_level1
2.Fromthetcshorothershell,enterthefollowingcommandtobeginsynthesis.
xst-ifnstopwatch.xst
Forthepreviouscommandexample,thestopwatch.xstleshouldlooklike:
run
-ifnwatchver.prj
-ifmtmixed
-ofnwatchver.ngc
-ofmtNGC
-pxc5vfx30t-2-ff324
-opt_modeSpeed
-opt_level1
FilesCreatedDuringRun(MixedLanguage)
Duringthisrun,XSTcreatesthefollowingles:
•watchver.ngc
AnNGClereadyfortheimplementationtools
•xst.srp
TheXSTscriptlogle
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Chapter20:XSTCommandLineMode
SavingXSTMessagesinaDifferentLogFile(MixedLanguage)
TosaveXSTmessagestoadifferentlogle(forexample,watchver.log)run:
xst-ifnstopwatch.xst-ofn<lename>.log
Followingisanexampleusingwatchver.log:
xst-ifnstopwatch.xst-ofnwatchver.log
ImprovingReadability(MixedLanguage)
Toimprovethereadabilityofthestopwatch.xstle,especiallyifyouusemany
optionstorunsynthesis,placeeachoptionwithitsvalueonaseparateline.Observe
thefollowingrules:
•Therstlinecontainsonlytheruncommandwithoutanyoptions.
•Therearenoblanklinesinthemiddleofthecommand.
•Eachline(excepttherstone)beginswithadash.
SynthesizingVHDLDesignsUsingCommandLineMode
ThissectiondiscussesSynthesizingVHDLDesignsUsingCommandLineMode,and
includes:
•VHDLDesignFilesandEntities
•ExampleUsingCommandLineMode
•SynthesizingtheDesign
•LibraryNames
•XSTFileOrderWarning
ThefollowingcodingexampleshowshowtosynthesizeahierarchicalVHDLdesignfor
aVirtex®deviceusingcommandlinemode.
VHDLDesignFilesandEntities
TheexampleusesaVHDLdesigncalledwatchvhd.Thelesforwatchvhdare
locatedintheISEexamples\watchvhddirectoryoftheISE®DesignSuiteinstallation
directory.
Thisdesigncontainssevenentities:
•stopwatch
•statmach
•tenths(aCOREGenerator™softwarecore)
•decode
•smallcntr
•cnt60
•hex2led
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Chapter20:XSTCommandLineMode
ExampleUsingCommandLineMode
FollowingisanexampleofhowtosynthesizeaVHDLdesignusingcommandlinemode.
1.Createanewdirectorynamedvhdl_m.
2.CopythefollowinglesfromtheISEexamples\watchvhddirectoryoftheISE
DesignSuiteinstallationdirectorytothenewlycreatedvhdl_mdirectory .
•stopwatch.vhd
•statmach.vhd
•decode.vhd
•cnt60.vhd
•smallcntr.vhd
•tenths.vhd
•hex2led.vhd
3.Tosynthesizethedesign,whichisnowrepresentedbysevenVHDLles,create
aproject.
SynthesizingtheDesign
XSTsupportsmixedVHDLandVerilogprojects.Xilinx®recommendsthatyouusethe
newprojectformat,whetherornotitisarealmixedlanguageproject.Thisexampleuses
thenewprojectformat.TocreateaprojectlecontainingonlyVHDLles,placealistof
VHDLlesprecededbykeywordVHDLinaseparatele.Theorderofthelesisnot
important.XSTcanrecognizethehierarchy,andcompileVHDLlesinthecorrectorder.
Fortheexample,performthefollowingsteps:
1.Openanewlecalledwatchvhd.prj
2.EnterthenamesoftheVHDLlesinanyorderintothisleandsavethele:
vhdlworkstatmach.vhd
vhdlworkdecode.vhd
vhdlworkstopwatch.vhd
vhdlworkcnt60.vhd
vhdlworksmallcntr.vhd
vhdlworktenths.vhd
vhdlworkhex2led.vhd
3.Tosynthesizethedesign,executethefollowingcommandfromtheXSTshellor
thescriptle:
run-ifnwatchvhd.prj-ifmtmixed-topstopwatch-ofn
watchvhd.ngc-ofmtNGC-pxc5vfx30t-2-ff324-opt_modeSpeed
-opt_level1
Youmustspecifyatop-leveldesignblockwiththe-topcommandlineoption.
Tosynthesizejusthex2ledandcheckitsperformanceindependentlyoftheotherblocks,
youcanspecifythetop-levelentitytosynthesizeonthecommandline,usingthe-top
option.
run-ifnwatchvhd.prj-ifmtmixed-ofnwatchvhd.ngc-ofmtNGC-p
xc5vfx30t-2-ff324-opt_modeSpeed-opt_level1-tophex2led
Formoreinformation,see:
XSTSpecicNon-TimingOptions
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Chapter20:XSTCommandLineMode
LibraryNames
DuringVHDLcompilation,XSTusesthelibraryworkasthedefault.IfsomeVHDLles
aretobecompiledtodifferentlibraries,addthelibrarynamebeforethelename.For
example,tocompilehexl2ledintothelibrarymy_lib,writetheprojectleasfollows:
vhdlworkstatmach.vhdvhdlworkdecode.vhdvhdlwork
stopwatch.vhdvhdlworkcnt60.vhdvhdlworksmallcntr.vhdvhdl
worktenths.vhdvhdlmy_libhex2led.vhd
XSTFileOrderWarning
IfXSTdoesnotrecognizetheleorder,itissuesthefollowingwarning:
WARNING:XST:3204.Thesortofthevhdlfilesfailed,theywill
becompiledintheorderoftheprojectfile.
Inthiscase,youmust:
•PutallVHDLlesinthecorrectorder.
•Addthe-hdl_compilation_orderoptionwithvalueusertotheXSTruncommand:
run-ifnwatchvhd.prj-ifmtmixed-topstopwatch-ofn
watchvhd.ngc-ofmtNGC-pxc5vfx30t-2-ff324-opt_modeSpeed
-opt_level1-tophex2led-hdl_compilation_orderuser
SynthesizingVerilogDesignsUsingCommandLineMode
ThissectiondiscussesSynthesizingVerilogDesignsUsingCommandLineMode,and
includes:
•VerilogDesignFilesandModules
•ExampleUsingCommandLineMode
•SynthesizingtheDesign
•SynthesizingHEX2LED
ThefollowingcodingexampleshowsthesynthesisofahierarchicalVerilogdesignfora
Virtex®deviceusingcommandlinemode.
VerilogDesignFilesandModules
TheexampleusesaVerilogdesigncalledwatchver.Theselesarefoundinthefollowing
directoryoftheISE®DesignSuiteinstallationdirectory:
ISEexamples\watchver
Thelesare:
•stopwatch.v
•statmach.v
•decode.v
•cnt60.v
•smallcntr.v
•tenths.v
•hex2led.v
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Thisdesigncontainssevenmodules:
•stopwatch
•statmach
•tenths(aCOREGenerator™softwarecore)
•decode
•cnt60
•smallcntr
•hex2led
ExampleUsingCommandLineMode
1.Createanewdirectorynamedvlg_m.
2.CopythewatchverdesignlesfromtheISEexamples\watchverdirectoryof
theISEDesignSuiteinstallationdirectorytothenewlycreatedvlg_mdirectory .
Specifythetop-leveldesignblockwiththe-topcommandlineoption.
SynthesizingtheDesign
Tosynthesizethedesign,whichisnowrepresentedbysevenVerilogles,createa
project.XSTnowsupportsmixedVHDLandVerilogprojects.Therefore,Xilinx®
recommendsthatyouusethenewprojectformatwhetheritisarealmixedlanguage
projectornot.Inthisexample,weusethenewprojectformat.Tocreateaprojectle
containingonlyVerilogles,placealistofVeriloglesprecededbythekeywordverilog
inaseparatele.Theorderofthelesisnotimportant.XSTcanrecognizethehierarchy
andcompileVeriloglesinthecorrectorder.
1.Openanewle,calledwatchver.v.
2.EnterthenamesoftheVeriloglesintothisleinanyorderandsaveit:
verilogworkdecode.v
verilogworkstatmach.v
verilogworkstopwatch.v
verilogworkcnt60.v
verilogworksmallcntr.v
verilogworkhex2led.v
3.Tosynthesizethedesign,executethefollowingcommandfromtheXSTshellora
scriptle:
run-ifnwatchver.v-ifmtmixed-topstopwatch-ofn
watchver.ngc-ofmtNGC-pxc5vfx30t-2-ff324-opt_modeSpeed
-opt_level1
SynthesizingHEX2LED
TosynthesizejustHEX2LEDandcheckitsperformanceindependentlyoftheother
blocks,specifythetop-levelmoduletosynthesizeinthecommandline,usingthe-top
option.
run-ifnwatchver.v-ifmtVerilog-ofnwatchver.ngc-ofmtNGC-p
xc5vfx30t-2-ff324-opt_modeSpeed-opt_level1-topHEX2LED
Formoreinformation,see:
XSTSpecicNon-TimingOptions
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SynthesizingMixedDesignsUsingCommandLineMode
ThissectiondiscussesSynthesizingMixedDesignsUsingCommandLineMode,and
includes:
•ExampleUsingCommandLineMode
•SynthesizingtheDesign
•FileOrder
ThisexampleshowsthesynthesisofahierarchicalmixedVHDLandVerilogdesignfor
aVirtex®deviceusingcommandlinemode.
ExampleUsingCommandLineMode
1.Createanewdirectorynamedvhdl_verilog.
2.CopythefollowinglesfromtheISEexamples\watchvhddirectoryoftheISE®
DesignSuiteinstallationdirectorytothenewly-createdvhdl_verilogdirectory.
•stopwatch.vhd
•statmach.vhd
•decode.vhd
•cnt60.vhd
•smallcntr.vhd
•tenths.vhd
3.Copythehex2led.vlefromtheISEexamples\watchverdirectoryoftheISE
DesignSuiteinstallationdirectorytothenewlycreatedvhdl_verilogdirectory.
[
SynthesizingtheDesign
ThedesignisnowrepresentedbysixVHDLlesandoneVerilogle.Tosynthesize
thedesign,createaproject.Tocreateaprojectle,placealistofVHDLlespreceded
bykeywordvhdl,andalistofVeriloglesprecededbykeywordverilogina
separatele.
FileOrder
Theorderofthelesisnotimportant.XSTrecognizesthehierarchyandcompiles
HardwareDescriptionLanguage(HDL)lesinthecorrectorder.
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